1072 files changed, 29705 insertions, 19877 deletions
diff --git a/Documentation/devicetree/bindings/arm/calxeda.txt b/Documentation/devicetree/bindings/arm/calxeda.txt
new file mode 100644
index 000000000000..4755caaccba6
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/calxeda.txt
@@ -0,0 +1,8 @@
+Calxeda Highbank Platforms Device Tree Bindings
+-----------------------------------------------
+Boards with Calxeda Cortex-A9 based Highbank SOC shall have the following
+properties.
+Required root node properties:
+    - compatible = "calxeda,highbank";
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
new file mode 100644
index 000000000000..c9848ad0e2e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -0,0 +1,26 @@
+Freescale i.MX Platforms Device Tree Bindings
+-----------------------------------------------
+i.MX51 Babbage Board
+Required root node properties:
+    - compatible = "fsl,imx51-babbage", "fsl,imx51";
+i.MX53 Automotive Reference Design Board
+Required root node properties:
+    - compatible = "fsl,imx53-ard", "fsl,imx53";
+i.MX53 Evaluation Kit
+Required root node properties:
+    - compatible = "fsl,imx53-evk", "fsl,imx53";
+i.MX53 Quick Start Board
+Required root node properties:
+    - compatible = "fsl,imx53-qsb", "fsl,imx53";
+i.MX53 Smart Mobile Reference Design Board
+Required root node properties:
+    - compatible = "fsl,imx53-smd", "fsl,imx53";
+i.MX6 Quad SABRE Automotive Board
+Required root node properties:
+    - compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
new file mode 100644
index 000000000000..52916b4aa1fe
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -0,0 +1,55 @@
+* ARM Generic Interrupt Controller
+ARM SMP cores are often associated with a GIC, providing per processor
+interrupts (PPI), shared processor interrupts (SPI) and software
+generated interrupts (SGI).
+Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
+Secondary GICs are cascaded into the upward interrupt controller and do not
+have PPIs or SGIs.
+Main node required properties:
+- compatible : should be one of:
+        "arm,cortex-a9-gic"
+        "arm,arm11mp-gic"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source.  The type shall be a <u32> and the value shall be 3.
+  The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
+  interrupts.
+  The 2nd cell contains the interrupt number for the interrupt type.
+  SPI interrupts are in the range [0-987].  PPI interrupts are in the
+  range [0-15].
+  The 3rd cell is the flags, encoded as follows:
+        bits[3:0] trigger type and level flags.
+                1 = low-to-high edge triggered
+                2 = high-to-low edge triggered
+                4 = active high level-sensitive
+                8 = active low level-sensitive
+        bits[15:8] PPI interrupt cpu mask.  Each bit corresponds to each of
+        the 8 possible cpus attached to the GIC.  A bit set to '1' indicated
+        the interrupt is wired to that CPU.  Only valid for PPI interrupts.
+- reg : Specifies base physical address(s) and size of the GIC registers. The
+  first region is the GIC distributor register base and size. The 2nd region is
+  the GIC cpu interface register base and size.
+Optional
+- interrupts    : Interrupt source of the parent interrupt controller. Only
+  present on secondary GICs.
+Example:
+        intc: interrupt-controller@fff11000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <1>;
+                interrupt-controller;
+                reg = <0xfff11000 0x1000>,
+                      <0xfff10100 0x100>;
+        };
diff --git a/Documentation/devicetree/bindings/arm/omap/dsp.txt b/Documentation/devicetree/bindings/arm/omap/dsp.txt
new file mode 100644
index 000000000000..d3830a32ce08
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/omap/dsp.txt
@@ -0,0 +1,14 @@
+* TI - DSP (Digital Signal Processor)
+TI DSP included in OMAP SoC
+Required properties:
+- compatible : Should be "ti,omap3-c64" for OMAP3 & 4
+- ti,hwmods: "dsp"
+Examples:
+dsp {
+    compatible = "ti,omap3-c64";
+    ti,hwmods = "dsp";
+};
diff --git a/Documentation/devicetree/bindings/arm/omap/iva.txt b/Documentation/devicetree/bindings/arm/omap/iva.txt
new file mode 100644
index 000000000000..6d6295171358
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/omap/iva.txt
@@ -0,0 +1,19 @@
+* TI - IVA (Imaging and Video Accelerator) subsystem
+The IVA contain various audio, video or imaging HW accelerator
+depending of the version.
+Required properties:
+- compatible : Should be:
+  - "ti,ivahd" for OMAP4
+  - "ti,iva2.2" for OMAP3
+  - "ti,iva2.1" for OMAP2430
+  - "ti,iva1" for OMAP2420
+- ti,hwmods: "iva"
+Examples:
+iva {
+    compatible = "ti,ivahd", "ti,iva";
+    ti,hwmods = "iva";
+};
diff --git a/Documentation/devicetree/bindings/arm/omap/l3-noc.txt b/Documentation/devicetree/bindings/arm/omap/l3-noc.txt
new file mode 100644
index 000000000000..6888a5efc860
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/omap/l3-noc.txt
@@ -0,0 +1,19 @@
+* TI - L3 Network On Chip (NoC)
+This version is an implementation of the generic NoC IP
+provided by Arteris.
+Required properties:
+- compatible : Should be "ti,omap3-l3-smx" for OMAP3 family
+               Should be "ti,omap4-l3-noc" for OMAP4 family
+- ti,hwmods: "l3_main_1", ... One hwmod for each noc domain.
+Examples:
+ocp {
+        compatible = "ti,omap4-l3-noc", "simple-bus";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges;
+        ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
+};
diff --git a/Documentation/devicetree/bindings/arm/omap/mpu.txt b/Documentation/devicetree/bindings/arm/omap/mpu.txt
new file mode 100644
index 000000000000..1a5a42ce21bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/omap/mpu.txt
@@ -0,0 +1,27 @@
+* TI - MPU (Main Processor Unit) subsystem
+The MPU subsystem contain one or several ARM cores
+depending of the version.
+The MPU contain CPUs, GIC, L2 cache and a local PRCM.
+Required properties:
+- compatible : Should be "ti,omap3-mpu" for OMAP3
+               Should be "ti,omap4-mpu" for OMAP4
+- ti,hwmods: "mpu"
+Examples:
+- For an OMAP4 SMP system:
+mpu {
+    compatible = "ti,omap4-mpu";
+    ti,hwmods = "mpu";
+};
+- For an OMAP3 monocore system:
+mpu {
+    compatible = "ti,omap3-mpu";
+    ti,hwmods = "mpu";
+};
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
new file mode 100644
index 000000000000..dbdab40ed3a6
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -0,0 +1,43 @@
+* Texas Instruments OMAP
+OMAP is currently using a static file per SoC family to describe the
+IPs present in the SoC.
+On top of that an omap_device is created to extend the platform_device
+capabilities and to allow binding with one or several hwmods.
+The hwmods will contain all the information to build the device:
+adresse range, irq lines, dma lines, interconnect, PRCM register,
+clock domain, input clocks.
+For the moment just point to the existing hwmod, the next step will be
+to move data from hwmod to device-tree representation.
+Required properties:
+- compatible: Every devices present in OMAP SoC should be in the
+  form: "ti,XXX"
+- ti,hwmods: list of hwmod names (ascii strings), that comes from the OMAP
+  HW documentation, attached to a device. Must contain at least
+  one hwmod.
+Optional properties:
+- ti,no_idle_on_suspend: When present, it prevents the PM to idle the module
+  during suspend.
+Example:
+spinlock@1 {
+    compatible = "ti,omap4-spinlock";
+    ti,hwmods = "spinlock";
+};
+Boards:
+- OMAP3 BeagleBoard : Low cost community board
+  compatible = "ti,omap3-beagle", "ti,omap3"
+- OMAP4 SDP : Software Developement Board
+  compatible = "ti,omap4-sdp", "ti,omap4430"
+- OMAP4 PandaBoard : Low cost community board
+  compatible = "ti,omap4-panda", "ti,omap4430"
diff --git a/Documentation/devicetree/bindings/arm/picoxcell.txt b/Documentation/devicetree/bindings/arm/picoxcell.txt
new file mode 100644
index 000000000000..e75c0ef51e69
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/picoxcell.txt
@@ -0,0 +1,24 @@
+Picochip picoXcell device tree bindings.
+========================================
+Required root node properties:
+    - compatible:
+        - "picochip,pc7302-pc3x3" : PC7302 development board with PC3X3 device.
+        - "picochip,pc7302-pc3x2" : PC7302 development board with PC3X2 device.
+        - "picochip,pc3x3" : picoXcell PC3X3 device based board.
+        - "picochip,pc3x2" : picoXcell PC3X2 device based board.
+Timers required properties:
+    - compatible = "picochip,pc3x2-timer"
+    - interrupts : The single IRQ line for the timer.
+    - clock-freq : The frequency in HZ of the timer.
+    - reg : The register bank for the timer.
+Note: two timers are required - one for the scheduler clock and one for the
+event tick/NOHZ.
+VIC required properties:
+    - compatible = "arm,pl192-vic".
+    - interrupt-controller.
+    - reg : The register bank for the device.
+    - #interrupt-cells : Must be 1.
diff --git a/Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt b/Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt
new file mode 100644
index 000000000000..36f82dbdd14d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt
@@ -0,0 +1,5 @@
+NVIDIA Tegra 2 pinmux controller
+Required properties:
+- compatible : "nvidia,tegra20-pinmux"
diff --git a/Documentation/devicetree/bindings/tty/serial/msm_serial.txt b/Documentation/devicetree/bindings/tty/serial/msm_serial.txt
new file mode 100644
index 000000000000..aef383eb8876
--- /dev/null
+++ b/Documentation/devicetree/bindings/tty/serial/msm_serial.txt
@@ -0,0 +1,27 @@
+* Qualcomm MSM UART
+Required properties:
+- compatible :
+        - "qcom,msm-uart", and one of "qcom,msm-hsuart" or
+          "qcom,msm-lsuart".
+- reg : offset and length of the register set for the device
+        for the hsuart operating in compatible mode, there should be a
+        second pair describing the gsbi registers.
+- interrupts : should contain the uart interrupt.
+There are two different UART blocks used in MSM devices,
+"qcom,msm-hsuart" and "qcom,msm-lsuart".  The msm-serial driver is
+able to handle both of these, and matches against the "qcom,msm-uart"
+as the compatibility.
+The registers for the "qcom,msm-hsuart" device need to specify both
+register blocks, even for the common driver.
+Example:
+        uart@19c400000 {
+                compatible = "qcom,msm-hsuart", "qcom,msm-uart";
+                reg = <0x19c40000 0x1000>,
+                      <0x19c00000 0x1000>;
+                interrupts = <195>;
+        };
diff --git a/Documentation/filesystems/Locking b/Documentation/filesystems/Locking
index 653380793a6c..d819ba16a0c7 100644
--- a/Documentation/filesystems/Locking
+++ b/Documentation/filesystems/Locking
@@ -29,6 +29,7 @@ d_hash		no		no		no		maybe
 d_compare:      yes             no              no              maybe
 d_delete:       no              yes             no              no
 d_release:      no              no              yes             no
+d_prune:        no              yes             no              no
 d_iput:         no              no              yes             no
 d_dname:        no              no              no              no
 d_automount:    no              no              yes             no
diff --git a/Documentation/filesystems/ext3.txt b/Documentation/filesystems/ext3.txt
index 22f3a0eda1d2..b100adc38adb 100644
--- a/Documentation/filesystems/ext3.txt
+++ b/Documentation/filesystems/ext3.txt
@@ -73,14 +73,6 @@ nobarrier	(*)	This also requires an IO stack which can support
                        also be used to enable or disable barriers, for
                        consistency with other ext3 mount options.
-orlov           (*)     This enables the new Orlov block allocator. It is
-                        enabled by default.
-oldalloc                This disables the Orlov block allocator and enables
-                        the old block allocator.  Orlov should have better
-                        performance - we'd like to get some feedback if it's
-                        the contrary for you.
 user_xattr              Enables Extended User Attributes.  Additionally, you
                        need to have extended attribute support enabled in the
                        kernel configuration (CONFIG_EXT3_FS_XATTR).  See the
diff --git a/Documentation/filesystems/ext4.txt b/Documentation/filesystems/ext4.txt
index 232a575a0c48..4917cf24a5e0 100644
--- a/Documentation/filesystems/ext4.txt
+++ b/Documentation/filesystems/ext4.txt
@@ -160,7 +160,9 @@ noload			if the filesystem was not unmounted cleanly,
                        lead to any number of problems.
 data=journal            All data are committed into the journal prior to being
-                        written into the main file system.
+                        written into the main file system.  Enabling
+                        this mode will disable delayed allocation and
+                        O_DIRECT support.
 data=ordered    (*)     All data are forced directly out to the main file
                        system prior to its metadata being committed to the
@@ -201,30 +203,19 @@ inode_readahead_blks=n	This tuning parameter controls the maximum
                        table readahead algorithm will pre-read into
                        the buffer cache.  The default value is 32 blocks.
-orlov           (*)     This enables the new Orlov block allocator. It is
+nouser_xattr            Disables Extended User Attributes. If you have extended
-                        enabled by default.
+                        attribute support enabled in the kernel configuration
+                        (CONFIG_EXT4_FS_XATTR), extended attribute support
-oldalloc                This disables the Orlov block allocator and enables
+                        is enabled by default on mount. See the attr(5) manual
-                        the old block allocator.  Orlov should have better
+                        page and http://acl.bestbits.at/ for more information
-                        performance - we'd like to get some feedback if it's
+                        about extended attributes.
-                        the contrary for you.
-user_xattr              Enables Extended User Attributes.  Additionally, you
-                        need to have extended attribute support enabled in the
-                        kernel configuration (CONFIG_EXT4_FS_XATTR).  See the
-                        attr(5) manual page and http://acl.bestbits.at/ to
-                        learn more about extended attributes.
-nouser_xattr            Disables Extended User Attributes.
-acl                     Enables POSIX Access Control Lists support.
-                        Additionally, you need to have ACL support enabled in
-                        the kernel configuration (CONFIG_EXT4_FS_POSIX_ACL).
-                        See the acl(5) manual page and http://acl.bestbits.at/
-                        for more information.
 noacl                   This option disables POSIX Access Control List
-                        support.
+                        support. If ACL support is enabled in the kernel
+                        configuration (CONFIG_EXT4_FS_POSIX_ACL), ACL is
+                        enabled by default on mount. See the acl(5) manual
+                        page and http://acl.bestbits.at/ for more information
+                        about acl.
 bsddf           (*)     Make 'df' act like BSD.
 minixdf                 Make 'df' act like Minix.
@@ -419,8 +410,8 @@ written to the journal first, and then to its final location.
 In the event of a crash, the journal can be replayed, bringing both data and
 metadata into a consistent state.  This mode is the slowest except when data
 needs to be read from and written to disk at the same time where it
-outperforms all others modes.  Currently ext4 does not have delayed
+outperforms all others modes.  Enabling this mode will disable delayed
-allocation support if this data journalling mode is selected.
+allocation and O_DIRECT support.
 /proc entries
 =============
diff --git a/Documentation/virtual/uml/UserModeLinux-HOWTO.txt b/Documentation/virtual/uml/UserModeLinux-HOWTO.txt
index 5d0fc8bfcdb9..77dfecf4e2d6 100644
--- a/Documentation/virtual/uml/UserModeLinux-HOWTO.txt
+++ b/Documentation/virtual/uml/UserModeLinux-HOWTO.txt
@@ -134,13 +134,13 @@
  ______________________________________________________________________
-  11..  IInnttrroodduuccttiioonn
+  1.  Introduction
  Welcome to User Mode Linux.  It's going to be fun.
-  11..11..  HHooww iiss UUsseerr MMooddee LLiinnuuxx DDiiffffeerreenntt??
+  1.1.  How is User Mode Linux Different?
  Normally, the Linux Kernel talks straight to your hardware (video
  card, keyboard, hard drives, etc), and any programs which run ask the
@@ -181,7 +181,7 @@
-  11..22..  WWhhyy WWoouulldd II WWaanntt UUsseerr MMooddee LLiinnuuxx??
+  1.2.  Why Would I Want User Mode Linux?
  1. If User Mode Linux crashes, your host kernel is still fine.
@@ -206,12 +206,12 @@
-  22..  CCoommppiilliinngg tthhee kkeerrnneell aanndd mmoodduulleess
+  2.  Compiling the kernel and modules
-  22..11..  CCoommppiilliinngg tthhee kkeerrnneell
+  2.1.  Compiling the kernel
  Compiling the user mode kernel is just like compiling any other
@@ -322,7 +322,7 @@
  bug fixes and enhancements that have gone into subsequent releases.
-  22..22..  CCoommppiilliinngg aanndd iinnssttaalllliinngg kkeerrnneell mmoodduulleess
+  2.2.  Compiling and installing kernel modules
  UML modules are built in the same way as the native kernel (with the
  exception of the 'ARCH=um' that you always need for UML):
@@ -386,19 +386,19 @@
-  22..33..  CCoommppiilliinngg aanndd iinnssttaalllliinngg uummll__uuttiilliittiieess
+  2.3.  Compiling and installing uml_utilities
  Many features of the UML kernel require a user-space helper program,
  so a uml_utilities package is distributed separately from the kernel
  patch which provides these helpers. Included within this is:
-  +o  port-helper - Used by consoles which connect to xterms or ports
+  o  port-helper - Used by consoles which connect to xterms or ports
-  +o  tunctl - Configuration tool to create and delete tap devices
+  o  tunctl - Configuration tool to create and delete tap devices
-  +o  uml_net - Setuid binary for automatic tap device configuration
+  o  uml_net - Setuid binary for automatic tap device configuration
-  +o  uml_switch - User-space virtual switch required for daemon
+  o  uml_switch - User-space virtual switch required for daemon
     transport
     The uml_utilities tree is compiled with:
@@ -423,11 +423,11 @@
-  33..  RRuunnnniinngg UUMMLL aanndd llooggggiinngg iinn
+  3.  Running UML and logging in
-  33..11..  RRuunnnniinngg UUMMLL
+  3.1.  Running UML
  It runs on 2.2.15 or later, and all 2.4 kernels.
@@ -454,7 +454,7 @@
-  33..22..  LLooggggiinngg iinn
+  3.2.  Logging in
@@ -468,7 +468,7 @@
  There are a couple of other ways to log in:
-  +o  On a virtual console
+  o  On a virtual console
@@ -480,7 +480,7 @@
-  +o  Over the serial line
+  o  Over the serial line
     In the boot output, find a line that looks like:
@@ -503,7 +503,7 @@
-  +o  Over the net
+  o  Over the net
     If the network is running, then you can telnet to the virtual
@@ -514,13 +514,13 @@
  down and the process will exit.
-  33..33..  EExxaammpplleess
+  3.3.  Examples
  Here are some examples of UML in action:
-  +o  A login session <http://user-mode-linux.sourceforge.net/login.html>
+  o  A login session <http://user-mode-linux.sourceforge.net/login.html>
-  +o  A virtual network <http://user-mode-linux.sourceforge.net/net.html>
+  o  A virtual network <http://user-mode-linux.sourceforge.net/net.html>
@@ -528,12 +528,12 @@
-  44..  UUMMLL oonn 22GG//22GG hhoossttss
+  4.  UML on 2G/2G hosts
-  44..11..  IInnttrroodduuccttiioonn
+  4.1.  Introduction
  Most Linux machines are configured so that the kernel occupies the
@@ -546,7 +546,7 @@
-  44..22..  TThhee pprroobblleemm
+  4.2.  The problem
  The prebuilt UML binaries on this site will not run on 2G/2G hosts
@@ -558,7 +558,7 @@
-  44..33..  TThhee ssoolluuttiioonn
+  4.3.  The solution
  The fix for this is to rebuild UML from source after enabling
@@ -576,7 +576,7 @@
-  55..  SSeettttiinngg uupp sseerriiaall lliinneess aanndd ccoonnssoolleess
+  5.  Setting up serial lines and consoles
  It is possible to attach UML serial lines and consoles to many types
@@ -586,12 +586,12 @@
  You can attach them to host ptys, ttys, file descriptors, and ports.
  This allows you to do things like
-  +o  have a UML console appear on an unused host console,
+  o  have a UML console appear on an unused host console,
-  +o  hook two virtual machines together by having one attach to a pty
+  o  hook two virtual machines together by having one attach to a pty
     and having the other attach to the corresponding tty
-  +o  make a virtual machine accessible from the net by attaching a
+  o  make a virtual machine accessible from the net by attaching a
     console to a port on the host.
@@ -599,7 +599,7 @@
-  55..11..  SSppeecciiffyyiinngg tthhee ddeevviiccee
+  5.1.  Specifying the device
  Devices are specified with "con" or "ssl" (console or serial line,
  respectively), optionally with a device number if you are talking
@@ -626,13 +626,13 @@
-  55..22..  SSppeecciiffyyiinngg tthhee cchhaannnneell
+  5.2.  Specifying the channel
  There are a number of different types of channels to attach a UML
  device to, each with a different way of specifying exactly what to
  attach to.
-  +o  pseudo-terminals - device=pty pts terminals - device=pts
+  o  pseudo-terminals - device=pty pts terminals - device=pts
     This will cause UML to allocate a free host pseudo-terminal for the
@@ -640,20 +640,20 @@
     log.  You access it by attaching a terminal program to the
     corresponding tty:
-  +o  screen /dev/pts/n
+  o  screen /dev/pts/n
-  +o  screen /dev/ttyxx
+  o  screen /dev/ttyxx
-  +o  minicom -o -p /dev/ttyxx - minicom seems not able to handle pts
+  o  minicom -o -p /dev/ttyxx - minicom seems not able to handle pts
     devices
-  +o  kermit - start it up, 'open' the device, then 'connect'
+  o  kermit - start it up, 'open' the device, then 'connect'
-  +o  terminals - device=tty:tty device file
+  o  terminals - device=tty:tty device file
     This will make UML attach the device to the specified tty (i.e
@@ -672,7 +672,7 @@
-  +o  xterms - device=xterm
+  o  xterms - device=xterm
     UML will run an xterm and the device will be attached to it.
@@ -681,7 +681,7 @@
-  +o  Port - device=port:port number
+  o  Port - device=port:port number
     This will attach the UML devices to the specified host port.
@@ -725,7 +725,7 @@
-  +o  already-existing file descriptors - device=file descriptor
+  o  already-existing file descriptors - device=file descriptor
     If you set up a file descriptor on the UML command line, you can
@@ -743,7 +743,7 @@
-  +o  Nothing - device=null
+  o  Nothing - device=null
     This allows the device to be opened, in contrast to 'none', but
@@ -754,7 +754,7 @@
-  +o  None - device=none
+  o  None - device=none
     This causes the device to disappear.
@@ -770,7 +770,7 @@
-  will cause serial line 3 to accept input on the host's /dev/tty3 and
+  will cause serial line 3 to accept input on the host's /dev/tty2 and
  display output on an xterm.  That's a silly example - the most common
  use of this syntax is to reattach the main console to stdin and stdout
  as shown above.
@@ -785,7 +785,7 @@
-  55..33..  EExxaammpplleess
+  5.3.  Examples
  There are a number of interesting things you can do with this
  capability.
@@ -838,7 +838,7 @@
  prompt of the other virtual machine.
-  66..  SSeettttiinngg uupp tthhee nneettwwoorrkk
+  6.  Setting up the network
@@ -858,19 +858,19 @@
  There are currently five transport types available for a UML virtual
  machine to exchange packets with other hosts:
-  +o  ethertap
+  o  ethertap
-  +o  TUN/TAP
+  o  TUN/TAP
-  +o  Multicast
+  o  Multicast
-  +o  a switch daemon
+  o  a switch daemon
-  +o  slip
+  o  slip
-  +o  slirp
+  o  slirp
-  +o  pcap
+  o  pcap
     The TUN/TAP, ethertap, slip, and slirp transports allow a UML
     instance to exchange packets with the host.  They may be directed
@@ -893,28 +893,28 @@
  With so many host transports, which one should you use?  Here's when
  you should use each one:
-  +o  ethertap - if you want access to the host networking and it is
+  o  ethertap - if you want access to the host networking and it is
     running 2.2
-  +o  TUN/TAP - if you want access to the host networking and it is
+  o  TUN/TAP - if you want access to the host networking and it is
     running 2.4.  Also, the TUN/TAP transport is able to use a
     preconfigured device, allowing it to avoid using the setuid uml_net
     helper, which is a security advantage.
-  +o  Multicast - if you want a purely virtual network and you don't want
+  o  Multicast - if you want a purely virtual network and you don't want
     to set up anything but the UML
-  +o  a switch daemon - if you want a purely virtual network and you
+  o  a switch daemon - if you want a purely virtual network and you
     don't mind running the daemon in order to get somewhat better
     performance
-  +o  slip - there is no particular reason to run the slip backend unless
+  o  slip - there is no particular reason to run the slip backend unless
     ethertap and TUN/TAP are just not available for some reason
-  +o  slirp - if you don't have root access on the host to setup
+  o  slirp - if you don't have root access on the host to setup
     networking, or if you don't want to allocate an IP to your UML
-  +o  pcap - not much use for actual network connectivity, but great for
+  o  pcap - not much use for actual network connectivity, but great for
     monitoring traffic on the host
     Ethertap is available on 2.4 and works fine.  TUN/TAP is preferred
@@ -926,7 +926,7 @@
     exploit the helper's root privileges.
-  66..11..  GGeenneerraall sseettuupp
+  6.1.  General setup
  First, you must have the virtual network enabled in your UML.  If are
  running a prebuilt kernel from this site, everything is already
@@ -995,7 +995,7 @@
-  66..22..  UUsseerrssppaaccee ddaaeemmoonnss
+  6.2.  Userspace daemons
  You will likely need the setuid helper, or the switch daemon, or both.
  They are both installed with the RPM and deb, so if you've installed
@@ -1011,7 +1011,7 @@
-  66..33..  SSppeecciiffyyiinngg eetthheerrnneett aaddddrreesssseess
+  6.3.  Specifying ethernet addresses
  Below, you will see that the TUN/TAP, ethertap, and daemon interfaces
  allow you to specify hardware addresses for the virtual ethernet
@@ -1023,11 +1023,11 @@
  sufficient to guarantee a unique hardware address for the device.  A
  couple of exceptions are:
-  +o  Another set of virtual ethernet devices are on the same network and
+  o  Another set of virtual ethernet devices are on the same network and
     they are assigned hardware addresses using a different scheme which
     may conflict with the UML IP address-based scheme
-  +o  You aren't going to use the device for IP networking, so you don't
+  o  You aren't going to use the device for IP networking, so you don't
     assign the device an IP address
     If you let the driver provide the hardware address, you should make
@@ -1049,7 +1049,7 @@
-  66..44..  UUMMLL iinntteerrffaaccee sseettuupp
+  6.4.  UML interface setup
  Once the network devices have been described on the command line, you
  should boot UML and log in.
@@ -1131,7 +1131,7 @@
-  66..55..  MMuullttiiccaasstt
+  6.5.  Multicast
  The simplest way to set up a virtual network between multiple UMLs is
  to use the mcast transport.  This was written by Harald Welte and is
@@ -1194,7 +1194,7 @@
-  66..66..  TTUUNN//TTAAPP wwiitthh tthhee uummll__nneett hheellppeerr
+  6.6.  TUN/TAP with the uml_net helper
  TUN/TAP is the preferred mechanism on 2.4 to exchange packets with the
  host.  The TUN/TAP backend has been in UML since 2.4.9-3um.
@@ -1247,10 +1247,10 @@
  There are a couple potential problems with running the TUN/TAP
  transport on a 2.4 host kernel
-  +o  TUN/TAP seems not to work on 2.4.3 and earlier.  Upgrade the host
+  o  TUN/TAP seems not to work on 2.4.3 and earlier.  Upgrade the host
     kernel or use the ethertap transport.
-  +o  With an upgraded kernel, TUN/TAP may fail with
+  o  With an upgraded kernel, TUN/TAP may fail with
       File descriptor in bad state
@@ -1269,7 +1269,7 @@
-  66..77..  TTUUNN//TTAAPP wwiitthh aa pprreeccoonnffiigguurreedd ttaapp ddeevviiccee
+  6.7.  TUN/TAP with a preconfigured tap device
  If you prefer not to have UML use uml_net (which is somewhat
  insecure), with UML 2.4.17-11, you can set up a TUN/TAP device
@@ -1277,7 +1277,7 @@
  there is no need for root assistance.  Setting up the device is done
  as follows:
-  +o  Create the device with tunctl (available from the UML utilities
+  o  Create the device with tunctl (available from the UML utilities
     tarball)
@@ -1291,7 +1291,7 @@
  where uid is the user id or username that UML will be run as.  This
  will tell you what device was created.
-  +o  Configure the device IP (change IP addresses and device name to
+  o  Configure the device IP (change IP addresses and device name to
     suit)
@@ -1303,7 +1303,7 @@
-  +o  Set up routing and arping if desired - this is my recipe, there are
+  o  Set up routing and arping if desired - this is my recipe, there are
     other ways of doing the same thing
@@ -1338,7 +1338,7 @@
  utility which reads the information from a config file and sets up
  devices at boot time.
-  +o  Rather than using up two IPs and ARPing for one of them, you can
+  o  Rather than using up two IPs and ARPing for one of them, you can
     also provide direct access to your LAN by the UML by using a
     bridge.
@@ -1417,7 +1417,7 @@
  Note that 'br0' should be setup using ifconfig with the existing IP
  address of eth0, as eth0 no longer has its own IP.
-  +o
+  o
     Also, the /dev/net/tun device must be writable by the user running
@@ -1438,11 +1438,11 @@
  devices and chgrp /dev/net/tun to that group with mode 664 or 660.
-  +o  Once the device is set up, run UML with 'eth0=tuntap,device name'
+  o  Once the device is set up, run UML with 'eth0=tuntap,device name'
     (i.e. 'eth0=tuntap,tap0') on the command line (or do it with the
     mconsole config command).
-  +o  Bring the eth device up in UML and you're in business.
+  o  Bring the eth device up in UML and you're in business.
     If you don't want that tap device any more, you can make it non-
     persistent with
@@ -1465,7 +1465,7 @@
-  66..88..  EEtthheerrttaapp
+  6.8.  Ethertap
  Ethertap is the general mechanism on 2.2 for userspace processes to
  exchange packets with the kernel.
@@ -1561,9 +1561,9 @@
-  66..99..  TThhee sswwiittcchh ddaaeemmoonn
+  6.9.  The switch daemon
-  NNoottee: This is the daemon formerly known as uml_router, but which was
+  Note: This is the daemon formerly known as uml_router, but which was
  renamed so the network weenies of the world would stop growling at me.
@@ -1649,7 +1649,7 @@
-  66..1100..  SSlliipp
+  6.10.  Slip
  Slip is another, less general, mechanism for a process to communicate
  with the host networking.  In contrast to the ethertap interface,
@@ -1681,7 +1681,7 @@
-  66..1111..  SSlliirrpp
+  6.11.  Slirp
  slirp uses an external program, usually /usr/bin/slirp, to provide IP
  only networking connectivity through the host. This is similar to IP
@@ -1737,7 +1737,7 @@
-  66..1122..  ppccaapp
+  6.12.  pcap
  The pcap transport is attached to a UML ethernet device on the command
  line or with uml_mconsole with the following syntax:
@@ -1777,7 +1777,7 @@
-  66..1133..  SSeettttiinngg uupp tthhee hhoosstt yyoouurrsseellff
+  6.13.  Setting up the host yourself
  If you don't specify an address for the host side of the ethertap or
  slip device, UML won't do any setup on the host.  So this is what is
@@ -1785,7 +1785,7 @@
  192.168.0.251 and a UML-side IP of 192.168.0.250 - adjust to suit your
  own network):
-  +o  The device needs to be configured with its IP address.  Tap devices
+  o  The device needs to be configured with its IP address.  Tap devices
     are also configured with an mtu of 1484.  Slip devices are
     configured with a point-to-point address pointing at the UML ip
     address.
@@ -1805,7 +1805,7 @@
-  +o  If a tap device is being set up, a route is set to the UML IP.
+  o  If a tap device is being set up, a route is set to the UML IP.
       UML# route add -host 192.168.0.250 gw 192.168.0.251
@@ -1814,7 +1814,7 @@
-  +o  To allow other hosts on your network to see the virtual machine,
+  o  To allow other hosts on your network to see the virtual machine,
     proxy arp is set up for it.
@@ -1824,7 +1824,7 @@
-  +o  Finally, the host is set up to route packets.
+  o  Finally, the host is set up to route packets.
       host#  echo 1 > /proc/sys/net/ipv4/ip_forward
@@ -1838,12 +1838,12 @@
-  77..  SShhaarriinngg FFiilleessyysstteemmss bbeettwweeeenn VViirrttuuaall MMaacchhiinneess
+  7.  Sharing Filesystems between Virtual Machines
-  77..11..  AA wwaarrnniinngg
+  7.1.  A warning
  Don't attempt to share filesystems simply by booting two UMLs from the
  same file.  That's the same thing as booting two physical machines
@@ -1851,7 +1851,7 @@
-  77..22..  UUssiinngg llaayyeerreedd bblloocckk ddeevviicceess
+  7.2.  Using layered block devices
  The way to share a filesystem between two virtual machines is to use
  the copy-on-write (COW) layering capability of the ubd block driver.
@@ -1896,7 +1896,7 @@
-  77..33..  NNoottee!!
+  7.3.  Note!
  When checking the size of the COW file in order to see the gobs of
  space that you're saving, make sure you use 'ls -ls' to see the actual
@@ -1926,7 +1926,7 @@
-  77..44..  AAnnootthheerr wwaarrnniinngg
+  7.4.  Another warning
  Once a filesystem is being used as a readonly backing file for a COW
  file, do not boot directly from it or modify it in any way.  Doing so
@@ -1952,7 +1952,7 @@
-  77..55..  uummll__mmoooo :: MMeerrggiinngg aa CCOOWW ffiillee wwiitthh iittss bbaacckkiinngg ffiillee
+  7.5.  uml_moo : Merging a COW file with its backing file
  Depending on how you use UML and COW devices, it may be advisable to
  merge the changes in the COW file into the backing file every once in
@@ -2001,7 +2001,7 @@
-  88..  CCrreeaattiinngg ffiilleessyysstteemmss
+  8.  Creating filesystems
  You may want to create and mount new UML filesystems, either because
@@ -2015,7 +2015,7 @@
  should be easy to translate to the filesystem of your choice.
-  88..11..  CCrreeaattee tthhee ffiilleessyysstteemm ffiillee
+  8.1.  Create the filesystem file
  dd is your friend.  All you need to do is tell dd to create an empty
  file of the appropriate size.  I usually make it sparse to save time
@@ -2032,7 +2032,7 @@
-  88..22..  AAssssiiggnn tthhee ffiillee ttoo aa UUMMLL ddeevviiccee
+  8.2.  Assign the file to a UML device
  Add an argument like the following to the UML command line:
@@ -2045,7 +2045,7 @@
-  88..33..  CCrreeaattiinngg aanndd mmoouunnttiinngg tthhee ffiilleessyysstteemm
+  8.3.  Creating and mounting the filesystem
  Make sure that the filesystem is available, either by being built into
  the kernel, or available as a module, then boot up UML and log in.  If
@@ -2096,7 +2096,7 @@
-  99..  HHoosstt ffiillee aacccceessss
+  9.  Host file access
  If you want to access files on the host machine from inside UML, you
@@ -2112,7 +2112,7 @@
  files contained in it just as you would on the host.
-  99..11..  UUssiinngg hhoossttffss
+  9.1.  Using hostfs
  To begin with, make sure that hostfs is available inside the virtual
  machine with
@@ -2151,7 +2151,7 @@
-  99..22..  hhoossttffss aass tthhee rroooott ffiilleessyysstteemm
+  9.2.  hostfs as the root filesystem
  It's possible to boot from a directory hierarchy on the host using
  hostfs rather than using the standard filesystem in a file.
@@ -2194,20 +2194,20 @@
  UML should then boot as it does normally.
-  99..33..  BBuuiillddiinngg hhoossttffss
+  9.3.  Building hostfs
  If you need to build hostfs because it's not in your kernel, you have
  two choices:
-  +o  Compiling hostfs into the kernel:
+  o  Compiling hostfs into the kernel:
     Reconfigure the kernel and set the 'Host filesystem' option under
-  +o  Compiling hostfs as a module:
+  o  Compiling hostfs as a module:
     Reconfigure the kernel and set the 'Host filesystem' option under
@@ -2228,7 +2228,7 @@
-  1100..  TThhee MMaannaaggeemmeenntt CCoonnssoollee
+  10.  The Management Console
@@ -2240,15 +2240,15 @@
  There are a number of things you can do with the mconsole interface:
-  +o  get the kernel version
+  o  get the kernel version
-  +o  add and remove devices
+  o  add and remove devices
-  +o  halt or reboot the machine
+  o  halt or reboot the machine
-  +o  Send SysRq commands
+  o  Send SysRq commands
-  +o  Pause and resume the UML
+  o  Pause and resume the UML
  You need the mconsole client (uml_mconsole) which is present in CVS
@@ -2300,28 +2300,28 @@
  You'll get a prompt, at which you can run one of these commands:
-  +o  version
+  o  version
-  +o  halt
+  o  halt
-  +o  reboot
+  o  reboot
-  +o  config
+  o  config
-  +o  remove
+  o  remove
-  +o  sysrq
+  o  sysrq
-  +o  help
+  o  help
-  +o  cad
+  o  cad
-  +o  stop
+  o  stop
-  +o  go
+  o  go
-  1100..11..  vveerrssiioonn
+  10.1.  version
  This takes no arguments.  It prints the UML version.
@@ -2342,7 +2342,7 @@
-  1100..22..  hhaalltt aanndd rreebboooott
+  10.2.  halt and reboot
  These take no arguments.  They shut the machine down immediately, with
  no syncing of disks and no clean shutdown of userspace.  So, they are
@@ -2357,7 +2357,7 @@
-  1100..33..  ccoonnffiigg
+  10.3.  config
  "config" adds a new device to the virtual machine.  Currently the ubd
  and network drivers support this.  It takes one argument, which is the
@@ -2378,7 +2378,7 @@
-  1100..44..  rreemmoovvee
+  10.4.  remove
  "remove" deletes a device from the system.  Its argument is just the
  name of the device to be removed. The device must be idle in whatever
@@ -2397,7 +2397,7 @@
-  1100..55..  ssyyssrrqq
+  10.5.  sysrq
  This takes one argument, which is a single letter.  It calls the
  generic kernel's SysRq driver, which does whatever is called for by
@@ -2407,14 +2407,14 @@
-  1100..66..  hheellpp
+  10.6.  help
  "help" returns a string listing the valid commands and what each one
  does.
-  1100..77..  ccaadd
+  10.7.  cad
  This invokes the Ctl-Alt-Del action on init.  What exactly this ends
  up doing is up to /etc/inittab.  Normally, it reboots the machine.
@@ -2432,7 +2432,7 @@
-  1100..88..  ssttoopp
+  10.8.  stop
  This puts the UML in a loop reading mconsole requests until a 'go'
  mconsole command is received. This is very useful for making backups
@@ -2448,7 +2448,7 @@
-  1100..99..  ggoo
+  10.9.  go
  This resumes a UML after being paused by a 'stop' command. Note that
  when the UML has resumed, TCP connections may have timed out and if
@@ -2462,10 +2462,10 @@
-  1111..  KKeerrnneell ddeebbuuggggiinngg
+  11.  Kernel debugging
-  NNoottee:: The interface that makes debugging, as described here, possible
+  Note: The interface that makes debugging, as described here, possible
  is present in 2.4.0-test6 kernels and later.
@@ -2485,7 +2485,7 @@
-  1111..11..  SSttaarrttiinngg tthhee kkeerrnneell uunnddeerr ggddbb
+  11.1.  Starting the kernel under gdb
  You can have the kernel running under the control of gdb from the
  beginning by putting 'debug' on the command line.  You will get an
@@ -2498,7 +2498,7 @@
  There is a transcript of a debugging session  here <debug-
  session.html> , with breakpoints being set in the scheduler and in an
  interrupt handler.
-  1111..22..  EExxaammiinniinngg sslleeeeppiinngg pprroocceesssseess
+  11.2.  Examining sleeping processes
  Not every bug is evident in the currently running process.  Sometimes,
  processes hang in the kernel when they shouldn't because they've
@@ -2516,7 +2516,7 @@
  Now what you do is this:
-  +o  detach from the current thread
+  o  detach from the current thread
       (UML gdb)  det
@@ -2525,7 +2525,7 @@
-  +o  attach to the thread you are interested in
+  o  attach to the thread you are interested in
       (UML gdb)  att <host pid>
@@ -2534,7 +2534,7 @@
-  +o  look at its stack and anything else of interest
+  o  look at its stack and anything else of interest
       (UML gdb)  bt
@@ -2545,7 +2545,7 @@
  Note that you can't do anything at this point that requires that a
  process execute, e.g. calling a function
-  +o  when you're done looking at that process, reattach to the current
+  o  when you're done looking at that process, reattach to the current
     thread and continue it
@@ -2569,12 +2569,12 @@
-  1111..33..  RRuunnnniinngg dddddd oonn UUMMLL
+  11.3.  Running ddd on UML
  ddd works on UML, but requires a special kludge.  The process goes
  like this:
-  +o  Start ddd
+  o  Start ddd
       host% ddd linux
@@ -2583,14 +2583,14 @@
-  +o  With ps, get the pid of the gdb that ddd started.  You can ask the
+  o  With ps, get the pid of the gdb that ddd started.  You can ask the
     gdb to tell you, but for some reason that confuses things and
     causes a hang.
-  +o  run UML with 'debug=parent gdb-pid=<pid>' added to the command line
+  o  run UML with 'debug=parent gdb-pid=<pid>' added to the command line
     - it will just sit there after you hit return
-  +o  type 'att 1' to the ddd gdb and you will see something like
+  o  type 'att 1' to the ddd gdb and you will see something like
       0xa013dc51 in __kill ()
@@ -2602,12 +2602,12 @@
-  +o  At this point, type 'c', UML will boot up, and you can use ddd just
+  o  At this point, type 'c', UML will boot up, and you can use ddd just
     as you do on any other process.
-  1111..44..  DDeebbuuggggiinngg mmoodduulleess
+  11.4.  Debugging modules
  gdb has support for debugging code which is dynamically loaded into
  the process.  This support is what is needed to debug kernel modules
@@ -2823,7 +2823,7 @@
-  1111..55..  AAttttaacchhiinngg ggddbb ttoo tthhee kkeerrnneell
+  11.5.  Attaching gdb to the kernel
  If you don't have the kernel running under gdb, you can attach gdb to
  it later by sending the tracing thread a SIGUSR1.  The first line of
@@ -2857,7 +2857,7 @@
-  1111..66..  UUssiinngg aalltteerrnnaattee ddeebbuuggggeerrss
+  11.6.  Using alternate debuggers
  UML has support for attaching to an already running debugger rather
  than starting gdb itself.  This is present in CVS as of 17 Apr 2001.
@@ -2886,7 +2886,7 @@
  An example of an alternate debugger is strace.  You can strace the
  actual kernel as follows:
-  +o  Run the following in a shell
+  o  Run the following in a shell
       host%
@@ -2894,10 +2894,10 @@
-  +o  Run UML with 'debug' and 'gdb-pid=<pid>' with the pid printed out
+  o  Run UML with 'debug' and 'gdb-pid=<pid>' with the pid printed out
     by the previous command
-  +o  Hit return in the shell, and UML will start running, and strace
+  o  Hit return in the shell, and UML will start running, and strace
     output will start accumulating in the output file.
     Note that this is different from running
@@ -2917,9 +2917,9 @@
-  1122..  KKeerrnneell ddeebbuuggggiinngg eexxaammpplleess
+  12.  Kernel debugging examples
-  1122..11..  TThhee ccaassee ooff tthhee hhuunngg ffsscckk
+  12.1.  The case of the hung fsck
  When booting up the kernel, fsck failed, and dropped me into a shell
  to fix things up.  I ran fsck -y, which hung:
@@ -3154,9 +3154,9 @@
  The interesting things here are :
-  +o  There are two segfaults on this stack (frames 9 and 14)
+  o  There are two segfaults on this stack (frames 9 and 14)
-  +o  The first faulting address (frame 11) is 0x50000800
+  o  The first faulting address (frame 11) is 0x50000800
  (gdb) p (void *)1342179328
  $16 = (void *) 0x50000800
@@ -3399,7 +3399,7 @@
  on will be somewhat clearer.
-  1122..22..  EEppiissooddee 22:: TThhee ccaassee ooff tthhee hhuunngg ffsscckk
+  12.2.  Episode 2: The case of the hung fsck
  After setting a trap in the SEGV handler for accesses to the signal
  thread's stack, I reran the kernel.
@@ -3788,12 +3788,12 @@
-  1133..  WWhhaatt ttoo ddoo wwhheenn UUMMLL ddooeessnn''tt wwoorrkk
+  13.  What to do when UML doesn't work
-  1133..11..  SSttrraannggee ccoommppiillaattiioonn eerrrroorrss wwhheenn yyoouu bbuuiilldd ffrroomm ssoouurrccee
+  13.1.  Strange compilation errors when you build from source
  As of test11, it is necessary to have "ARCH=um" in the environment or
  on the make command line for all steps in building UML, including
@@ -3824,8 +3824,8 @@
-  1133..33..  AA vvaarriieettyy ooff ppaanniiccss aanndd hhaannggss wwiitthh //ttmmpp oonn aa rreeiisseerrffss  ffiilleessyyss--
+  13.3.  A variety of panics and hangs with /tmp on a reiserfs  filesys-
-  tteemm
+  tem
  I saw this on reiserfs 3.5.21 and it seems to be fixed in 3.5.27.
  Panics preceded by
@@ -3842,8 +3842,8 @@
-  1133..44..  TThhee ccoommppiillee ffaaiillss wwiitthh eerrrroorrss aabboouutt ccoonnfflliiccttiinngg ttyyppeess ffoorr
+  13.4.  The compile fails with errors about conflicting types for
-  ''ooppeenn'',, ''dduupp'',, aanndd ''wwaaiittppiidd''
+  'open', 'dup', and 'waitpid'
  This happens when you build in /usr/src/linux.  The UML build makes
  the include/asm link point to include/asm-um.  /usr/include/asm points
@@ -3854,14 +3854,14 @@
-  1133..55..  UUMMLL ddooeessnn''tt wwoorrkk wwhheenn //ttmmpp iiss aann NNFFSS ffiilleessyysstteemm
+  13.5.  UML doesn't work when /tmp is an NFS filesystem
  This seems to be a similar situation with the ReiserFS problem above.
  Some versions of NFS seems not to handle mmap correctly, which UML
  depends on.  The workaround is have /tmp be a non-NFS directory.
-  1133..66..  UUMMLL hhaannggss oonn bboooott wwhheenn ccoommppiilleedd wwiitthh ggpprrooff ssuuppppoorrtt
+  13.6.  UML hangs on boot when compiled with gprof support
  If you build UML with gprof support and, early in the boot, it does
  this
@@ -3878,7 +3878,7 @@
-  1133..77..  ssyyssllooggdd ddiieess wwiitthh aa SSIIGGTTEERRMM oonn ssttaarrttuupp
+  13.7.  syslogd dies with a SIGTERM on startup
  The exact boot error depends on the distribution that you're booting,
  but Debian produces this:
@@ -3897,17 +3897,17 @@
-  1133..88..  TTUUNN//TTAAPP nneettwwoorrkkiinngg ddooeessnn''tt wwoorrkk oonn aa 22..44 hhoosstt
+  13.8.  TUN/TAP networking doesn't work on a 2.4 host
  There are a couple of problems which were
  <http://www.geocrawler.com/lists/3/SourceForge/597/0/> name="pointed
  out">  by Tim Robinson <timro at trkr dot net>
-  +o  It doesn't work on hosts running 2.4.7 (or thereabouts) or earlier.
+  o  It doesn't work on hosts running 2.4.7 (or thereabouts) or earlier.
     The fix is to upgrade to something more recent and then read the
     next item.
-  +o  If you see
+  o  If you see
       File descriptor in bad state
@@ -3921,8 +3921,8 @@
-  1133..99..  YYoouu ccaann nneettwwoorrkk ttoo tthhee hhoosstt bbuutt nnoott ttoo ootthheerr mmaacchhiinneess oonn tthhee
+  13.9.  You can network to the host but not to other machines on the
-  nneett
+  net
  If you can connect to the host, and the host can connect to UML, but
  you cannot connect to any other machines, then you may need to enable
@@ -3972,7 +3972,7 @@
-  1133..1100..  II hhaavvee nnoo rroooott aanndd II wwaanntt ttoo ssccrreeaamm
+  13.10.  I have no root and I want to scream
  Thanks to Birgit Wahlich for telling me about this strange one.  It
  turns out that there's a limit of six environment variables on the
@@ -3987,7 +3987,7 @@
-  1133..1111..  UUMMLL bbuuiilldd ccoonnfflliicctt bbeettwweeeenn ppttrraaccee..hh aanndd uuccoonntteexxtt..hh
+  13.11.  UML build conflict between ptrace.h and ucontext.h
  On some older systems, /usr/include/asm/ptrace.h and
  /usr/include/sys/ucontext.h define the same names.  So, when they're
@@ -4007,7 +4007,7 @@
-  1133..1122..  TThhee UUMMLL BBooggooMMiippss iiss eexxaaccttllyy hhaallff tthhee hhoosstt''ss BBooggooMMiippss
+  13.12.  The UML BogoMips is exactly half the host's BogoMips
  On i386 kernels, there are two ways of running the loop that is used
  to calculate the BogoMips rating, using the TSC if it's there or using
@@ -4019,7 +4019,7 @@
-  1133..1133..  WWhheenn yyoouu rruunn UUMMLL,, iitt iimmmmeeddiiaatteellyy sseeggffaauullttss
+  13.13.  When you run UML, it immediately segfaults
  If the host is configured with the 2G/2G address space split, that's
  why.  See ``UML on 2G/2G hosts''  for the details on getting UML to
@@ -4027,7 +4027,7 @@
-  1133..1144..  xxtteerrmmss aappppeeaarr,, tthheenn iimmmmeeddiiaatteellyy ddiissaappppeeaarr
+  13.14.  xterms appear, then immediately disappear
  If you're running an up to date kernel with an old release of
  uml_utilities, the port-helper program will not work properly, so
@@ -4039,7 +4039,7 @@
-  1133..1155..  AAnnyy ootthheerr ppaanniicc,, hhaanngg,, oorr ssttrraannggee bbeehhaavviioorr
+  13.15.  Any other panic, hang, or strange behavior
  If you're seeing truly strange behavior, such as hangs or panics that
  happen in random places, or you try running the debugger to see what's
@@ -4059,7 +4059,7 @@
  If you want to be super-helpful, read ``Diagnosing Problems'' and
  follow the instructions contained therein.
-  1144..  DDiiaaggnnoossiinngg PPrroobblleemmss
+  14.  Diagnosing Problems
  If you get UML to crash, hang, or otherwise misbehave, you should
@@ -4078,7 +4078,7 @@
  ``Kernel debugging''  UML first.
-  1144..11..  CCaassee 11 :: NNoorrmmaall kkeerrnneell ppaanniiccss
+  14.1.  Case 1 : Normal kernel panics
  The most common case is for a normal thread to panic.  To debug this,
  you will need to run it under the debugger (add 'debug' to the command
@@ -4128,7 +4128,7 @@
  to get that information from the faulting ip.
-  1144..22..  CCaassee 22 :: TTrraacciinngg tthhrreeaadd ppaanniiccss
+  14.2.  Case 2 : Tracing thread panics
  The less common and more painful case is when the tracing thread
  panics.  In this case, the kernel debugger will be useless because it
@@ -4161,7 +4161,7 @@
  backtrace in and wait for our crack debugging team to fix the problem.
-  1144..33..  CCaassee 33 :: TTrraacciinngg tthhrreeaadd ppaanniiccss ccaauusseedd bbyy ootthheerr tthhrreeaaddss
+  14.3.  Case 3 : Tracing thread panics caused by other threads
  However, there are cases where the misbehavior of another thread
  caused the problem.  The most common panic of this type is:
@@ -4227,7 +4227,7 @@
-  1144..44..  CCaassee 44 :: HHaannggss
+  14.4.  Case 4 : Hangs
  Hangs seem to be fairly rare, but they sometimes happen.  When a hang
  happens, we need a backtrace from the offending process.  Run the
@@ -4257,7 +4257,7 @@
-  1155..  TThhaannkkss
+  15.  Thanks
  A number of people have helped this project in various ways, and this
@@ -4274,20 +4274,20 @@
  bookkeeping lapses and I forget about contributions.
-  1155..11..  CCooddee aanndd DDooccuummeennttaattiioonn
+  15.1.  Code and Documentation
  Rusty Russell <rusty at linuxcare.com.au>  -
-  +o  wrote the  HOWTO <http://user-mode-
+  o  wrote the  HOWTO <http://user-mode-
     linux.sourceforge.net/UserModeLinux-HOWTO.html>
-  +o  prodded me into making this project official and putting it on
+  o  prodded me into making this project official and putting it on
     SourceForge
-  +o  came up with the way cool UML logo <http://user-mode-
+  o  came up with the way cool UML logo <http://user-mode-
     linux.sourceforge.net/uml-small.png>
-  +o  redid the config process
+  o  redid the config process
  Peter Moulder <reiter at netspace.net.au>  - Fixed my config and build
@@ -4296,18 +4296,18 @@
  Bill Stearns <wstearns at pobox.com>  -
-  +o  HOWTO updates
+  o  HOWTO updates
-  +o  lots of bug reports
+  o  lots of bug reports
-  +o  lots of testing
+  o  lots of testing
-  +o  dedicated a box (uml.ists.dartmouth.edu) to support UML development
+  o  dedicated a box (uml.ists.dartmouth.edu) to support UML development
-  +o  wrote the mkrootfs script, which allows bootable filesystems of
+  o  wrote the mkrootfs script, which allows bootable filesystems of
     RPM-based distributions to be cranked out
-  +o  cranked out a large number of filesystems with said script
+  o  cranked out a large number of filesystems with said script
  Jim Leu <jleu at mindspring.com>  - Wrote the virtual ethernet driver
@@ -4375,176 +4375,176 @@
  David Coulson <http://davidcoulson.net>  -
-  +o  Set up the usermodelinux.org <http://usermodelinux.org>  site,
+  o  Set up the usermodelinux.org <http://usermodelinux.org>  site,
     which is a great way of keeping the UML user community on top of
     UML goings-on.
-  +o  Site documentation and updates
+  o  Site documentation and updates
-  +o  Nifty little UML management daemon  UMLd
+  o  Nifty little UML management daemon  UMLd
     <http://uml.openconsultancy.com/umld/>
-  +o  Lots of testing and bug reports
+  o  Lots of testing and bug reports
-  1155..22..  FFlluusshhiinngg oouutt bbuuggss
+  15.2.  Flushing out bugs
-  +o  Yuri Pudgorodsky
+  o  Yuri Pudgorodsky
-  +o  Gerald Britton
+  o  Gerald Britton
-  +o  Ian Wehrman
+  o  Ian Wehrman
-  +o  Gord Lamb
+  o  Gord Lamb
-  +o  Eugene Koontz
+  o  Eugene Koontz
-  +o  John H. Hartman
+  o  John H. Hartman
-  +o  Anders Karlsson
+  o  Anders Karlsson
-  +o  Daniel Phillips
+  o  Daniel Phillips
-  +o  John Fremlin
+  o  John Fremlin
-  +o  Rainer Burgstaller
+  o  Rainer Burgstaller
-  +o  James Stevenson
+  o  James Stevenson
-  +o  Matt Clay
+  o  Matt Clay
-  +o  Cliff Jefferies
+  o  Cliff Jefferies
-  +o  Geoff Hoff
+  o  Geoff Hoff
-  +o  Lennert Buytenhek
+  o  Lennert Buytenhek
-  +o  Al Viro
+  o  Al Viro
-  +o  Frank Klingenhoefer
+  o  Frank Klingenhoefer
-  +o  Livio Baldini Soares
+  o  Livio Baldini Soares
-  +o  Jon Burgess
+  o  Jon Burgess
-  +o  Petru Paler
+  o  Petru Paler
-  +o  Paul
+  o  Paul
-  +o  Chris Reahard
+  o  Chris Reahard
-  +o  Sverker Nilsson
+  o  Sverker Nilsson
-  +o  Gong Su
+  o  Gong Su
-  +o  johan verrept
+  o  johan verrept
-  +o  Bjorn Eriksson
+  o  Bjorn Eriksson
-  +o  Lorenzo Allegrucci
+  o  Lorenzo Allegrucci
-  +o  Muli Ben-Yehuda
+  o  Muli Ben-Yehuda
-  +o  David Mansfield
+  o  David Mansfield
-  +o  Howard Goff
+  o  Howard Goff
-  +o  Mike Anderson
+  o  Mike Anderson
-  +o  John Byrne
+  o  John Byrne
-  +o  Sapan J. Batia
+  o  Sapan J. Batia
-  +o  Iris Huang
+  o  Iris Huang
-  +o  Jan Hudec
+  o  Jan Hudec
-  +o  Voluspa
+  o  Voluspa
-  1155..33..  BBuugglleettss aanndd cclleeaann--uuppss
+  15.3.  Buglets and clean-ups
-  +o  Dave Zarzycki
+  o  Dave Zarzycki
-  +o  Adam Lazur
+  o  Adam Lazur
-  +o  Boria Feigin
+  o  Boria Feigin
-  +o  Brian J. Murrell
+  o  Brian J. Murrell
-  +o  JS
+  o  JS
-  +o  Roman Zippel
+  o  Roman Zippel
-  +o  Wil Cooley
+  o  Wil Cooley
-  +o  Ayelet Shemesh
+  o  Ayelet Shemesh
-  +o  Will Dyson
+  o  Will Dyson
-  +o  Sverker Nilsson
+  o  Sverker Nilsson
-  +o  dvorak
+  o  dvorak
-  +o  v.naga srinivas
+  o  v.naga srinivas
-  +o  Shlomi Fish
+  o  Shlomi Fish
-  +o  Roger Binns
+  o  Roger Binns
-  +o  johan verrept
+  o  johan verrept
-  +o  MrChuoi
+  o  MrChuoi
-  +o  Peter Cleve
+  o  Peter Cleve
-  +o  Vincent Guffens
+  o  Vincent Guffens
-  +o  Nathan Scott
+  o  Nathan Scott
-  +o  Patrick Caulfield
+  o  Patrick Caulfield
-  +o  jbearce
+  o  jbearce
-  +o  Catalin Marinas
+  o  Catalin Marinas
-  +o  Shane Spencer
+  o  Shane Spencer
-  +o  Zou Min
+  o  Zou Min
-  +o  Ryan Boder
+  o  Ryan Boder
-  +o  Lorenzo Colitti
+  o  Lorenzo Colitti
-  +o  Gwendal Grignou
+  o  Gwendal Grignou
-  +o  Andre' Breiler
+  o  Andre' Breiler
-  +o  Tsutomu Yasuda
+  o  Tsutomu Yasuda
-  1155..44..  CCaassee SSttuuddiieess
+  15.4.  Case Studies
-  +o  Jon Wright
+  o  Jon Wright
-  +o  William McEwan
+  o  William McEwan
-  +o  Michael Richardson
+  o  Michael Richardson
-  1155..55..  OOtthheerr ccoonnttrriibbuuttiioonnss
+  15.5.  Other contributions
  Bill Carr <Bill.Carr at compaq.com>  made the Red Hat mkrootfs script
diff --git a/MAINTAINERS b/MAINTAINERS
index 5d6941f8c436..479beaa39131 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -692,6 +692,12 @@ F:	drivers/mtd/nand/bcm_umi_nand.c
 F:      drivers/mtd/nand/bcm_umi_bch.c
 F:      drivers/mtd/nand/nand_bcm_umi.h
+ARM/CALXEDA HIGHBANK ARCHITECTURE
+M:      Rob Herring <rob.herring@calxeda.com>
+L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S:      Maintained
+F:      arch/arm/mach-highbank/
 ARM/CAVIUM NETWORKS CNS3XXX MACHINE SUPPORT
 M:      Anton Vorontsov <avorontsov@mvista.com>
 S:      Maintained
@@ -791,6 +797,13 @@ L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:      Maintained
 F:      arch/arm/mach-mx5/
+ARM/FREESCALE IMX6
+M:      Shawn Guo <shawn.guo@linaro.org>
+L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S:      Maintained
+T:      git git://git.linaro.org/people/shawnguo/linux-2.6.git
+F:      arch/arm/mach-imx/*imx6*
 ARM/GLOMATION GESBC9312SX MACHINE SUPPORT
 M:      Lennert Buytenhek <kernel@wantstofly.org>
 L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@ -6670,7 +6683,6 @@ F:	drivers/net/ethernet/8390/ne-h8300.c
 UDF FILESYSTEM
 M:      Jan Kara <jack@suse.cz>
-W:      http://linux-udf.sourceforge.net
 S:      Maintained
 F:      Documentation/filesystems/udf.txt
 F:      fs/udf/
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5ca86e7ab66d..fe6b0526b3a6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -334,6 +334,20 @@ config ARCH_BCMRING
        help
          Support for Broadcom's BCMRing platform.
+config ARCH_HIGHBANK
+        bool "Calxeda Highbank-based"
+        select ARCH_WANT_OPTIONAL_GPIOLIB
+        select ARM_AMBA
+        select ARM_GIC
+        select ARM_TIMER_SP804
+        select CLKDEV_LOOKUP
+        select CPU_V7
+        select GENERIC_CLOCKEVENTS
+        select HAVE_ARM_SCU
+        select USE_OF
+        help
+          Support for the Calxeda Highbank SoC based boards.
 config ARCH_CLPS711X
        bool "Cirrus Logic CLPS711x/EP721x-based"
        select CPU_ARM720T
@@ -394,7 +408,7 @@ config ARCH_EP93XX
        select ARCH_REQUIRE_GPIOLIB
        select ARCH_HAS_HOLES_MEMORYMODEL
        select ARCH_USES_GETTIMEOFFSET
-        select NEED_MEMORY_H
+        select NEED_MACH_MEMORY_H
        help
          This enables support for the Cirrus EP93xx series of CPUs.
@@ -417,6 +431,7 @@ config ARCH_MXC
        select CLKSRC_MMIO
        select GENERIC_IRQ_CHIP
        select HAVE_SCHED_CLOCK
+        select MULTI_IRQ_HANDLER
        help
          Support for Freescale MXC/iMX-based family of processors
@@ -609,14 +624,6 @@ config ARCH_W90X900
          <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
                ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
-config ARCH_NUC93X
-        bool "Nuvoton NUC93X CPU"
-        select CPU_ARM926T
-        select CLKDEV_LOOKUP
-        help
-          Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
-          low-power and high performance MPEG-4/JPEG multimedia controller chip.
 config ARCH_TEGRA
        bool "NVIDIA Tegra"
        select CLKDEV_LOOKUP
@@ -630,6 +637,24 @@ config ARCH_TEGRA
          This enables support for NVIDIA Tegra based systems (Tegra APX,
          Tegra 6xx and Tegra 2 series).
+config ARCH_PICOXCELL
+        bool "Picochip picoXcell"
+        select ARCH_REQUIRE_GPIOLIB
+        select ARM_PATCH_PHYS_VIRT
+        select ARM_VIC
+        select CPU_V6K
+        select DW_APB_TIMER
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_GPIO
+        select HAVE_SCHED_CLOCK
+        select HAVE_TCM
+        select NO_IOPORT
+        select USE_OF
+        help
+          This enables support for systems based on the Picochip picoXcell
+          family of Femtocell devices.  The picoxcell support requires device tree
+          for all boards.
 config ARCH_PNX4008
        bool "Philips Nexperia PNX4008 Mobile"
        select CPU_ARM926T
@@ -861,6 +886,7 @@ config ARCH_U300
        select HAVE_SCHED_CLOCK
        select HAVE_TCM
        select ARM_AMBA
+        select ARM_PATCH_PHYS_VIRT
        select ARM_VIC
        select GENERIC_CLOCKEVENTS
        select CLKDEV_LOOKUP
@@ -1011,8 +1037,6 @@ source "arch/arm/mach-netx/Kconfig"
 source "arch/arm/mach-nomadik/Kconfig"
 source "arch/arm/plat-nomadik/Kconfig"
-source "arch/arm/mach-nuc93x/Kconfig"
 source "arch/arm/plat-omap/Kconfig"
 source "arch/arm/mach-omap1/Kconfig"
@@ -1406,7 +1430,7 @@ config SMP
        depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
                 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
                 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
-                 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
+                 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK || SOC_IMX6Q
        depends on MMU
        select USE_GENERIC_SMP_HELPERS
        select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
@@ -2044,6 +2068,7 @@ config CPU_FREQ_PXA
        bool
        depends on CPU_FREQ && ARCH_PXA && PXA25x
        default y
+        select CPU_FREQ_TABLE
        select CPU_FREQ_DEFAULT_GOV_USERSPACE
 config CPU_FREQ_S3C
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index f283938c2fc7..c5213e78606b 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -128,6 +128,125 @@ choice
                  Say Y here if you want the debug print routines to direct
                  their output to the second serial port on these devices.
+        config DEBUG_HIGHBANK_UART
+                bool "Kernel low-level debugging messages via Highbank UART"
+                depends on ARCH_HIGHBANK
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to the UART on Highbank based devices.
+        config DEBUG_IMX1_UART
+                bool "i.MX1 Debug UART"
+                depends on SOC_IMX1
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on i.MX1.
+        config DEBUG_IMX23_UART
+                bool "i.MX23 Debug UART"
+                depends on SOC_IMX23
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on i.MX23.
+        config DEBUG_IMX25_UART
+                bool "i.MX25 Debug UART"
+                depends on SOC_IMX25
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on i.MX25.
+        config DEBUG_IMX21_IMX27_UART
+                bool "i.MX21 and i.MX27 Debug UART"
+                depends on SOC_IMX21 || SOC_IMX27
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on i.MX21 or i.MX27.
+        config DEBUG_IMX28_UART
+                bool "i.MX28 Debug UART"
+                depends on SOC_IMX28
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on i.MX28.
+        config DEBUG_IMX31_IMX35_UART
+                bool "i.MX31 and i.MX35 Debug UART"
+                depends on SOC_IMX31 || SOC_IMX35
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on i.MX31 or i.MX35.
+        config DEBUG_IMX51_UART
+                bool "i.MX51 Debug UART"
+                depends on SOC_IMX51
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on i.MX51.
+        config DEBUG_IMX50_IMX53_UART
+                bool "i.MX50 and i.MX53 Debug UART"
+                depends on SOC_IMX50 || SOC_IMX53
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on i.MX50 or i.MX53.
+        config DEBUG_IMX6Q_UART
+                bool "i.MX6Q Debug UART"
+                depends on SOC_IMX6Q
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on i.MX6Q.
+        config DEBUG_S3C_UART0
+                depends on PLAT_SAMSUNG
+                bool "Use S3C UART 0 for low-level debug"
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to UART 0. The port must have been initialised
+                  by the boot-loader before use.
+                  The uncompressor code port configuration is now handled
+                  by CONFIG_S3C_LOWLEVEL_UART_PORT.
+        config DEBUG_S3C_UART1
+                depends on PLAT_SAMSUNG
+                bool "Use S3C UART 1 for low-level debug"
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to UART 1. The port must have been initialised
+                  by the boot-loader before use.
+                  The uncompressor code port configuration is now handled
+                  by CONFIG_S3C_LOWLEVEL_UART_PORT.
+        config DEBUG_S3C_UART2
+                depends on PLAT_SAMSUNG
+                bool "Use S3C UART 2 for low-level debug"
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to UART 2. The port must have been initialised
+                  by the boot-loader before use.
+                  The uncompressor code port configuration is now handled
+                  by CONFIG_S3C_LOWLEVEL_UART_PORT.
+        config DEBUG_REALVIEW_STD_PORT
+                bool "RealView Default UART"
+                depends on ARCH_REALVIEW
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to the serial port on RealView EB, PB11MP, PBA8
+                  and PBX platforms.
+        config DEBUG_REALVIEW_PB1176_PORT
+                bool "RealView PB1176 UART"
+                depends on MACH_REALVIEW_PB1176
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to the standard serial port on the RealView
+                  PB1176 platform.
 endchoice
 config EARLY_PRINTK
@@ -146,18 +265,6 @@ config OC_ETM
          buffer driver that will allow you to collect traces of the
          kernel code.
-config DEBUG_S3C_UART
-        depends on PLAT_SAMSUNG
-        int "S3C UART to use for low-level debug"
-        default "0"
-        help
-          Choice for UART for kernel low-level using S3C UARTS,
-          should be between zero and two. The port must have been
-          initialised by the boot-loader before use.
-          The uncompressor code port configuration is now handled
-          by CONFIG_S3C_LOWLEVEL_UART_PORT.
 config ARM_KPROBES_TEST
        tristate "Kprobes test module"
        depends on KPROBES && MODULES
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 5665c2a3b652..b7c2d377a6c2 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -144,6 +144,7 @@ machine-$(CONFIG_ARCH_EBSA110)		:= ebsa110
 machine-$(CONFIG_ARCH_EP93XX)           := ep93xx
 machine-$(CONFIG_ARCH_GEMINI)           := gemini
 machine-$(CONFIG_ARCH_H720X)            := h720x
+machine-$(CONFIG_ARCH_HIGHBANK)         := highbank
 machine-$(CONFIG_ARCH_INTEGRATOR)       := integrator
 machine-$(CONFIG_ARCH_IOP13XX)          := iop13xx
 machine-$(CONFIG_ARCH_IOP32X)           := iop32x
@@ -157,10 +158,8 @@ machine-$(CONFIG_ARCH_LPC32XX)		:= lpc32xx
 machine-$(CONFIG_ARCH_MMP)              := mmp
 machine-$(CONFIG_ARCH_MSM)              := msm
 machine-$(CONFIG_ARCH_MV78XX0)          := mv78xx0
-machine-$(CONFIG_ARCH_MX1)              := imx
+machine-$(CONFIG_ARCH_IMX_V4_V5)        := imx
-machine-$(CONFIG_ARCH_MX2)              := imx
+machine-$(CONFIG_ARCH_IMX_V6_V7)        := imx
-machine-$(CONFIG_ARCH_MX25)             := imx
-machine-$(CONFIG_ARCH_MX3)              := imx
 machine-$(CONFIG_ARCH_MX5)              := mx5
 machine-$(CONFIG_ARCH_MXS)              := mxs
 machine-$(CONFIG_ARCH_NETX)             := netx
@@ -170,6 +169,7 @@ machine-$(CONFIG_ARCH_OMAP2)		:= omap2
 machine-$(CONFIG_ARCH_OMAP3)            := omap2
 machine-$(CONFIG_ARCH_OMAP4)            := omap2
 machine-$(CONFIG_ARCH_ORION5X)          := orion5x
+machine-$(CONFIG_ARCH_PICOXCELL)        := picoxcell
 machine-$(CONFIG_ARCH_PNX4008)          := pnx4008
 machine-$(CONFIG_ARCH_PRIMA2)           := prima2
 machine-$(CONFIG_ARCH_PXA)              := pxa
@@ -192,7 +192,6 @@ machine-$(CONFIG_ARCH_VERSATILE)	:= versatile
 machine-$(CONFIG_ARCH_VEXPRESS)         := vexpress
 machine-$(CONFIG_ARCH_VT8500)           := vt8500
 machine-$(CONFIG_ARCH_W90X900)          := w90x900
-machine-$(CONFIG_ARCH_NUC93X)           := nuc93x
 machine-$(CONFIG_FOOTBRIDGE)            := footbridge
 machine-$(CONFIG_MACH_SPEAR300)         := spear3xx
 machine-$(CONFIG_MACH_SPEAR310)         := spear3xx
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
new file mode 100644
index 000000000000..aeef04269cf8
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -0,0 +1,119 @@
+/*
+ * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC
+ *
+ *  Copyright (C) 2011 Atmel,
+ *                2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
+ *                2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/include/ "skeleton.dtsi"
+/ {
+        model = "Atmel AT91SAM9G20 family SoC";
+        compatible = "atmel,at91sam9g20";
+        interrupt-parent = <&aic>;
+        aliases {
+                serial0 = &dbgu;
+                serial1 = &usart0;
+                serial2 = &usart1;
+                serial3 = &usart2;
+                serial4 = &usart3;
+                serial5 = &usart4;
+                serial6 = &usart5;
+        };
+        cpus {
+                cpu@0 {
+                        compatible = "arm,arm926ejs";
+                };
+        };
+        memory@20000000 {
+                reg = <0x20000000 0x08000000>;
+        };
+        ahb {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                apb {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        aic: interrupt-controller@fffff000 {
+                                #interrupt-cells = <1>;
+                                compatible = "atmel,at91rm9200-aic";
+                                interrupt-controller;
+                                interrupt-parent;
+                                reg = <0xfffff000 0x200>;
+                        };
+                        dbgu: serial@fffff200 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffff200 0x200>;
+                                interrupts = <1>;
+                                status = "disabled";
+                        };
+                        usart0: serial@fffb0000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffb0000 0x200>;
+                                interrupts = <6>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+                        usart1: serial@fffb4000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffb4000 0x200>;
+                                interrupts = <7>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+                        usart2: serial@fffb8000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffb8000 0x200>;
+                                interrupts = <8>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+                        usart3: serial@fffd0000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffd0000 0x200>;
+                                interrupts = <23>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+                        usart4: serial@fffd4000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffd4000 0x200>;
+                                interrupts = <24>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+                        usart5: serial@fffd8000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffd8000 0x200>;
+                                interrupts = <25>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
new file mode 100644
index 000000000000..db6a45202f26
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -0,0 +1,106 @@
+/*
+ * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
+ *                    applies to AT91SAM9G45, AT91SAM9M10,
+ *                    AT91SAM9G46, AT91SAM9M11 SoC
+ *
+ *  Copyright (C) 2011 Atmel,
+ *                2011 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/include/ "skeleton.dtsi"
+/ {
+        model = "Atmel AT91SAM9G45 family SoC";
+        compatible = "atmel,at91sam9g45";
+        interrupt-parent = <&aic>;
+        aliases {
+                serial0 = &dbgu;
+                serial1 = &usart0;
+                serial2 = &usart1;
+                serial3 = &usart2;
+                serial4 = &usart3;
+        };
+        cpus {
+                cpu@0 {
+                        compatible = "arm,arm926ejs";
+                };
+        };
+        memory@70000000 {
+                reg = <0x70000000 0x10000000>;
+        };
+        ahb {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                apb {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        aic: interrupt-controller@fffff000 {
+                                #interrupt-cells = <1>;
+                                compatible = "atmel,at91rm9200-aic";
+                                interrupt-controller;
+                                interrupt-parent;
+                                reg = <0xfffff000 0x200>;
+                        };
+                        dma: dma-controller@ffffec00 {
+                                compatible = "atmel,at91sam9g45-dma";
+                                reg = <0xffffec00 0x200>;
+                                interrupts = <21>;
+                        };
+                        dbgu: serial@ffffee00 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xffffee00 0x200>;
+                                interrupts = <1>;
+                                status = "disabled";
+                        };
+                        usart0: serial@fff8c000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfff8c000 0x200>;
+                                interrupts = <7>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+                        usart1: serial@fff90000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfff90000 0x200>;
+                                interrupts = <8>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+                        usart2: serial@fff94000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfff94000 0x200>;
+                                interrupts = <9>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+                        usart3: serial@fff98000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfff98000 0x200>;
+                                interrupts = <10>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
new file mode 100644
index 000000000000..85b34f59cd82
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -0,0 +1,35 @@
+/*
+ * at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board
+ *
+ *  Copyright (C) 2011 Atmel,
+ *                2011 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "at91sam9g45.dtsi"
+/ {
+        model = "Atmel AT91SAM9M10G45-EK";
+        compatible = "atmel,at91sam9m10g45ek", "atmel,at91sam9g45", "atmel,at91sam9";
+        chosen {
+                bootargs = "mem=64M console=ttyS0,115200 mtdparts=atmel_nand:4M(bootstrap/uboot/kernel)ro,60M(rootfs),-(data) root=/dev/mtdblock1 rw rootfstype=jffs2";
+        };
+        memory@70000000 {
+                reg = <0x70000000 0x4000000>;
+        };
+        ahb {
+                apb {
+                        dbgu: serial@ffffee00 {
+                                status = "okay";
+                        };
+                        usart1: serial@fff90000 {
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
new file mode 100644
index 000000000000..aeb1a7578fad
--- /dev/null
+++ b/arch/arm/boot/dts/highbank.dts
@@ -0,0 +1,198 @@
+/*
+ * Copyright 2011 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/dts-v1/;
+/* First 4KB has pen for secondary cores. */
+/memreserve/ 0x00000000 0x0001000;
+/ {
+        model = "Calxeda Highbank";
+        compatible = "calxeda,highbank";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        compatible = "arm,cortex-a9";
+                        reg = <0>;
+                        next-level-cache = <&L2>;
+                };
+                cpu@1 {
+                        compatible = "arm,cortex-a9";
+                        reg = <1>;
+                        next-level-cache = <&L2>;
+                };
+                cpu@2 {
+                        compatible = "arm,cortex-a9";
+                        reg = <2>;
+                        next-level-cache = <&L2>;
+                };
+                cpu@3 {
+                        compatible = "arm,cortex-a9";
+                        reg = <3>;
+                        next-level-cache = <&L2>;
+                };
+        };
+        memory {
+                name = "memory";
+                device_type = "memory";
+                reg = <0x00000000 0xff900000>;
+        };
+        chosen {
+                bootargs = "console=ttyAMA0";
+        };
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&intc>;
+                ranges;
+                timer@fff10600 {
+                        compatible = "arm,smp-twd";
+                        reg = <0xfff10600 0x20>;
+                        interrupts = <1 13 0xf04>;
+                };
+                watchdog@fff10620 {
+                        compatible = "arm,cortex-a9-wdt";
+                        reg = <0xfff10620 0x20>;
+                        interrupts = <1 14 0xf04>;
+                };
+                intc: interrupt-controller@fff11000 {
+                        compatible = "arm,cortex-a9-gic";
+                        #interrupt-cells = <3>;
+                        #size-cells = <0>;
+                        #address-cells = <1>;
+                        interrupt-controller;
+                        interrupt-parent;
+                        reg = <0xfff11000 0x1000>,
+                              <0xfff10100 0x100>;
+                };
+                L2: l2-cache {
+                        compatible = "arm,pl310-cache";
+                        reg = <0xfff12000 0x1000>;
+                        interrupts = <0 70 4>;
+                        cache-unified;
+                        cache-level = <2>;
+                };
+                pmu {
+                        compatible = "arm,cortex-a9-pmu";
+                        interrupts = <0 76 4  0 75 4  0 74 4  0 73 4>;
+                };
+                sata@ffe08000 {
+                        compatible = "calxeda,hb-ahci";
+                        reg = <0xffe08000 0x10000>;
+                        interrupts = <0 83 4>;
+                };
+                sdhci@ffe0e000 {
+                        compatible = "calxeda,hb-sdhci";
+                        reg = <0xffe0e000 0x1000>;
+                        interrupts = <0 90 4>;
+                };
+                ipc@fff20000 {
+                        compatible = "arm,pl320", "arm,primecell";
+                        reg = <0xfff20000 0x1000>;
+                        interrupts = <0 7 4>;
+                };
+                gpioe: gpio@fff30000 {
+                        #gpio-cells = <2>;
+                        compatible = "arm,pl061", "arm,primecell";
+                        gpio-controller;
+                        reg = <0xfff30000 0x1000>;
+                        interrupts = <0 14 4>;
+                };
+                gpiof: gpio@fff31000 {
+                        #gpio-cells = <2>;
+                        compatible = "arm,pl061", "arm,primecell";
+                        gpio-controller;
+                        reg = <0xfff31000 0x1000>;
+                        interrupts = <0 15 4>;
+                };
+                gpiog: gpio@fff32000 {
+                        #gpio-cells = <2>;
+                        compatible = "arm,pl061", "arm,primecell";
+                        gpio-controller;
+                        reg = <0xfff32000 0x1000>;
+                        interrupts = <0 16 4>;
+                };
+                gpioh: gpio@fff33000 {
+                        #gpio-cells = <2>;
+                        compatible = "arm,pl061", "arm,primecell";
+                        gpio-controller;
+                        reg = <0xfff33000 0x1000>;
+                        interrupts = <0 17 4>;
+                };
+                timer {
+                        compatible = "arm,sp804", "arm,primecell";
+                        reg = <0xfff34000 0x1000>;
+                        interrupts = <0 18 4>;
+                };
+                rtc@fff35000 {
+                        compatible = "arm,pl031", "arm,primecell";
+                        reg = <0xfff35000 0x1000>;
+                        interrupts = <0 19 4>;
+                };
+                serial@fff36000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0xfff36000 0x1000>;
+                        interrupts = <0 20 4>;
+                };
+                smic@fff3a000 {
+                        compatible = "ipmi-smic";
+                        device_type = "ipmi";
+                        reg = <0xfff3a000 0x1000>;
+                        interrupts = <0 24 4>;
+                        reg-size = <4>;
+                        reg-spacing = <4>;
+                };
+                sregs@fff3c000 {
+                        compatible = "calxeda,hb-sregs";
+                        reg = <0xfff3c000 0x1000>;
+                };
+                dma@fff3d000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0xfff3d000 0x1000>;
+                        interrupts = <0 92 4>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
new file mode 100644
index 000000000000..f8766af11215
--- /dev/null
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -0,0 +1,135 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "imx51.dtsi"
+/ {
+        model = "Freescale i.MX51 Babbage Board";
+        compatible = "fsl,imx51-babbage", "fsl,imx51";
+        chosen {
+                bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
+        };
+        memory {
+                reg = <0x90000000 0x20000000>;
+        };
+        soc {
+                aips@70000000 { /* aips-1 */
+                        spba@70000000 {
+                                esdhc@70004000 { /* ESDHC1 */
+                                        fsl,cd-internal;
+                                        fsl,wp-internal;
+                                        status = "okay";
+                                };
+                                esdhc@70008000 { /* ESDHC2 */
+                                        cd-gpios = <&gpio0 6 0>; /* GPIO1_6 */
+                                        wp-gpios = <&gpio0 5 0>; /* GPIO1_5 */
+                                        status = "okay";
+                                };
+                                uart2: uart@7000c000 { /* UART3 */
+                                        fsl,uart-has-rtscts;
+                                        status = "okay";
+                                };
+                                ecspi@70010000 { /* ECSPI1 */
+                                        fsl,spi-num-chipselects = <2>;
+                                        cs-gpios = <&gpio3 24 0>, /* GPIO4_24 */
+                                                   <&gpio3 25 0>; /* GPIO4_25 */
+                                        status = "okay";
+                                        pmic: mc13892@0 {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                                compatible = "fsl,mc13892";
+                                                spi-max-frequency = <6000000>;
+                                                reg = <0>;
+                                                mc13xxx-irq-gpios = <&gpio0 8 0>; /* GPIO1_8 */
+                                                fsl,mc13xxx-uses-regulator;
+                                        };
+                                        flash: at45db321d@1 {
+                                                #address-cells = <1>;
+                                                #size-cells = <1>;
+                                                compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
+                                                spi-max-frequency = <25000000>;
+                                                reg = <1>;
+                                                partition@0 {
+                                                        label = "U-Boot";
+                                                        reg = <0x0 0x40000>;
+                                                        read-only;
+                                                };
+                                                partition@40000 {
+                                                        label = "Kernel";
+                                                        reg = <0x40000 0x3c0000>;
+                                                };
+                                        };
+                                };
+                        };
+                        wdog@73f98000 { /* WDOG1 */
+                                status = "okay";
+                        };
+                        iomuxc@73fa8000 {
+                                compatible = "fsl,imx51-iomuxc-babbage";
+                                reg = <0x73fa8000 0x4000>;
+                        };
+                        uart0: uart@73fbc000 {
+                                fsl,uart-has-rtscts;
+                                status = "okay";
+                        };
+                        uart1: uart@73fc0000 {
+                                status = "okay";
+                        };
+                };
+                aips@80000000 { /* aips-2 */
+                        sdma@83fb0000 {
+                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
+                        };
+                        i2c@83fc4000 { /* I2C2 */
+                                status = "okay";
+                                codec: sgtl5000@0a {
+                                        compatible = "fsl,sgtl5000";
+                                        reg = <0x0a>;
+                                };
+                        };
+                        fec@83fec000 {
+                                phy-mode = "mii";
+                                status = "okay";
+                        };
+                };
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                power {
+                        label = "Power Button";
+                        gpios = <&gpio1 21 0>;
+                        linux,code = <116>; /* KEY_POWER */
+                        gpio-key,wakeup;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
new file mode 100644
index 000000000000..327ab8e3a4c8
--- /dev/null
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -0,0 +1,246 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/include/ "skeleton.dtsi"
+/ {
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+        };
+        tzic: tz-interrupt-controller@e0000000 {
+                compatible = "fsl,imx51-tzic", "fsl,tzic";
+                interrupt-controller;
+                #interrupt-cells = <1>;
+                reg = <0xe0000000 0x4000>;
+        };
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                ckil {
+                        compatible = "fsl,imx-ckil", "fixed-clock";
+                        clock-frequency = <32768>;
+                };
+                ckih1 {
+                        compatible = "fsl,imx-ckih1", "fixed-clock";
+                        clock-frequency = <22579200>;
+                };
+                ckih2 {
+                        compatible = "fsl,imx-ckih2", "fixed-clock";
+                        clock-frequency = <0>;
+                };
+                osc {
+                        compatible = "fsl,imx-osc", "fixed-clock";
+                        clock-frequency = <24000000>;
+                };
+        };
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&tzic>;
+                ranges;
+                aips@70000000 { /* AIPS1 */
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x70000000 0x10000000>;
+                        ranges;
+                        spba@70000000 {
+                                compatible = "fsl,spba-bus", "simple-bus";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0x70000000 0x40000>;
+                                ranges;
+                                esdhc@70004000 { /* ESDHC1 */
+                                        compatible = "fsl,imx51-esdhc";
+                                        reg = <0x70004000 0x4000>;
+                                        interrupts = <1>;
+                                        status = "disabled";
+                                };
+                                esdhc@70008000 { /* ESDHC2 */
+                                        compatible = "fsl,imx51-esdhc";
+                                        reg = <0x70008000 0x4000>;
+                                        interrupts = <2>;
+                                        status = "disabled";
+                                };
+                                uart2: uart@7000c000 { /* UART3 */
+                                        compatible = "fsl,imx51-uart", "fsl,imx21-uart";
+                                        reg = <0x7000c000 0x4000>;
+                                        interrupts = <33>;
+                                        status = "disabled";
+                                };
+                                ecspi@70010000 { /* ECSPI1 */
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "fsl,imx51-ecspi";
+                                        reg = <0x70010000 0x4000>;
+                                        interrupts = <36>;
+                                        status = "disabled";
+                                };
+                                esdhc@70020000 { /* ESDHC3 */
+                                        compatible = "fsl,imx51-esdhc";
+                                        reg = <0x70020000 0x4000>;
+                                        interrupts = <3>;
+                                        status = "disabled";
+                                };
+                                esdhc@70024000 { /* ESDHC4 */
+                                        compatible = "fsl,imx51-esdhc";
+                                        reg = <0x70024000 0x4000>;
+                                        interrupts = <4>;
+                                        status = "disabled";
+                                };
+                        };
+                        gpio0: gpio@73f84000 { /* GPIO1 */
+                                compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
+                                reg = <0x73f84000 0x4000>;
+                                interrupts = <50 51>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+                        gpio1: gpio@73f88000 { /* GPIO2 */
+                                compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
+                                reg = <0x73f88000 0x4000>;
+                                interrupts = <52 53>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+                        gpio2: gpio@73f8c000 { /* GPIO3 */
+                                compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
+                                reg = <0x73f8c000 0x4000>;
+                                interrupts = <54 55>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+                        gpio3: gpio@73f90000 { /* GPIO4 */
+                                compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
+                                reg = <0x73f90000 0x4000>;
+                                interrupts = <56 57>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+                        wdog@73f98000 { /* WDOG1 */
+                                compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
+                                reg = <0x73f98000 0x4000>;
+                                interrupts = <58>;
+                                status = "disabled";
+                        };
+                        wdog@73f9c000 { /* WDOG2 */
+                                compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
+                                reg = <0x73f9c000 0x4000>;
+                                interrupts = <59>;
+                                status = "disabled";
+                        };
+                        uart0: uart@73fbc000 {
+                                compatible = "fsl,imx51-uart", "fsl,imx21-uart";
+                                reg = <0x73fbc000 0x4000>;
+                                interrupts = <31>;
+                                status = "disabled";
+                        };
+                        uart1: uart@73fc0000 {
+                                compatible = "fsl,imx51-uart", "fsl,imx21-uart";
+                                reg = <0x73fc0000 0x4000>;
+                                interrupts = <32>;
+                                status = "disabled";
+                        };
+                };
+                aips@80000000 { /* AIPS2 */
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x80000000 0x10000000>;
+                        ranges;
+                        ecspi@83fac000 { /* ECSPI2 */
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx51-ecspi";
+                                reg = <0x83fac000 0x4000>;
+                                interrupts = <37>;
+                                status = "disabled";
+                        };
+                        sdma@83fb0000 {
+                                compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
+                                reg = <0x83fb0000 0x4000>;
+                                interrupts = <6>;
+                        };
+                        cspi@83fc0000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
+                                reg = <0x83fc0000 0x4000>;
+                                interrupts = <38>;
+                                status = "disabled";
+                        };
+                        i2c@83fc4000 { /* I2C2 */
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
+                                reg = <0x83fc4000 0x4000>;
+                                interrupts = <63>;
+                                status = "disabled";
+                        };
+                        i2c@83fc8000 { /* I2C1 */
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
+                                reg = <0x83fc8000 0x4000>;
+                                interrupts = <62>;
+                                status = "disabled";
+                        };
+                        fec@83fec000 {
+                                compatible = "fsl,imx51-fec", "fsl,imx27-fec";
+                                reg = <0x83fec000 0x4000>;
+                                interrupts = <87>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
new file mode 100644
index 000000000000..2ab7f80a0a35
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -0,0 +1,113 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "imx53.dtsi"
+/ {
+        model = "Freescale i.MX53 Automotive Reference Design Board";
+        compatible = "fsl,imx53-ard", "fsl,imx53";
+        chosen {
+                bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
+        };
+        memory {
+                reg = <0x70000000 0x40000000>;
+        };
+        soc {
+                aips@50000000 { /* AIPS1 */
+                        spba@50000000 {
+                                esdhc@50004000 { /* ESDHC1 */
+                                        cd-gpios = <&gpio0 1 0>; /* GPIO1_1 */
+                                        wp-gpios = <&gpio0 9 0>; /* GPIO1_9 */
+                                        status = "okay";
+                                };
+                        };
+                        wdog@53f98000 { /* WDOG1 */
+                                status = "okay";
+                        };
+                        iomuxc@53fa8000 {
+                                compatible = "fsl,imx53-iomuxc-ard";
+                                reg = <0x53fa8000 0x4000>;
+                        };
+                        uart0: uart@53fbc000 { /* UART1 */
+                                status = "okay";
+                        };
+                };
+                aips@60000000 { /* AIPS2 */
+                        sdma@63fb0000 {
+                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
+                        };
+                };
+        };
+        eim-cs1@f4000000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "fsl,eim-bus", "simple-bus";
+                reg = <0xf4000000 0x3ff0000>;
+                ranges;
+                lan9220@f4000000 {
+                        compatible = "smsc,lan9220", "smsc,lan9115";
+                        reg = <0xf4000000 0x2000000>;
+                        phy-mode = "mii";
+                        interrupt-parent = <&gpio1>;
+                        interrupts = <31>;
+                        reg-io-width = <4>;
+                        smsc,irq-push-pull;
+                };
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                home {
+                        label = "Home";
+                        gpios = <&gpio4 10 0>; /* GPIO5_10 */
+                        linux,code = <102>; /* KEY_HOME */
+                        gpio-key,wakeup;
+                };
+                back {
+                        label = "Back";
+                        gpios = <&gpio4 11 0>; /* GPIO5_11 */
+                        linux,code = <158>; /* KEY_BACK */
+                        gpio-key,wakeup;
+                };
+                program {
+                        label = "Program";
+                        gpios = <&gpio4 12 0>; /* GPIO5_12 */
+                        linux,code = <362>; /* KEY_PROGRAM */
+                        gpio-key,wakeup;
+                };
+                volume-up {
+                        label = "Volume Up";
+                        gpios = <&gpio4 13 0>; /* GPIO5_13 */
+                        linux,code = <115>; /* KEY_VOLUMEUP */
+                };
+                volume-down {
+                        label = "Volume Down";
+                        gpios = <&gpio3 0 0>; /* GPIO4_0 */
+                        linux,code = <114>; /* KEY_VOLUMEDOWN */
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts
new file mode 100644
index 000000000000..3f3a88185ff8
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-evk.dts
@@ -0,0 +1,120 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "imx53.dtsi"
+/ {
+        model = "Freescale i.MX53 Evaluation Kit";
+        compatible = "fsl,imx53-evk", "fsl,imx53";
+        chosen {
+                bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
+        };
+        memory {
+                reg = <0x70000000 0x80000000>;
+        };
+        soc {
+                aips@50000000 { /* AIPS1 */
+                        spba@50000000 {
+                                esdhc@50004000 { /* ESDHC1 */
+                                        cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */
+                                        wp-gpios = <&gpio2 14 0>; /* GPIO3_14 */
+                                        status = "okay";
+                                };
+                                ecspi@50010000 { /* ECSPI1 */
+                                        fsl,spi-num-chipselects = <2>;
+                                        cs-gpios = <&gpio1 30 0>, /* GPIO2_30 */
+                                                   <&gpio2 19 0>; /* GPIO3_19 */
+                                        status = "okay";
+                                        flash: at45db321d@1 {
+                                                #address-cells = <1>;
+                                                #size-cells = <1>;
+                                                compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
+                                                spi-max-frequency = <25000000>;
+                                                reg = <1>;
+                                                partition@0 {
+                                                        label = "U-Boot";
+                                                        reg = <0x0 0x40000>;
+                                                        read-only;
+                                                };
+                                                partition@40000 {
+                                                        label = "Kernel";
+                                                        reg = <0x40000 0x3c0000>;
+                                                };
+                                        };
+                                };
+                                esdhc@50020000 { /* ESDHC3 */
+                                        cd-gpios = <&gpio2 11 0>; /* GPIO3_11 */
+                                        wp-gpios = <&gpio2 12 0>; /* GPIO3_12 */
+                                        status = "okay";
+                                };
+                        };
+                        wdog@53f98000 { /* WDOG1 */
+                                status = "okay";
+                        };
+                        iomuxc@53fa8000 {
+                                compatible = "fsl,imx53-iomuxc-evk";
+                                reg = <0x53fa8000 0x4000>;
+                        };
+                        uart0: uart@53fbc000 { /* UART1 */
+                                status = "okay";
+                        };
+                };
+                aips@60000000 { /* AIPS2 */
+                        sdma@63fb0000 {
+                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
+                        };
+                        i2c@63fc4000 { /* I2C2 */
+                                status = "okay";
+                                pmic: mc13892@08 {
+                                        compatible = "fsl,mc13892", "fsl,mc13xxx";
+                                        reg = <0x08>;
+                                };
+                                codec: sgtl5000@0a {
+                                        compatible = "fsl,sgtl5000";
+                                        reg = <0x0a>;
+                                };
+                        };
+                        fec@63fec000 {
+                                phy-mode = "rmii";
+                                phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */
+                                status = "okay";
+                        };
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                green {
+                        label = "Heartbeat";
+                        gpios = <&gpio6 7 0>; /* GPIO7_7 */
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
new file mode 100644
index 000000000000..ae6de6d0c3f1
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -0,0 +1,125 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "imx53.dtsi"
+/ {
+        model = "Freescale i.MX53 Quick Start Board";
+        compatible = "fsl,imx53-qsb", "fsl,imx53";
+        chosen {
+                bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
+        };
+        memory {
+                reg = <0x70000000 0x40000000>;
+        };
+        soc {
+                aips@50000000 { /* AIPS1 */
+                        spba@50000000 {
+                                esdhc@50004000 { /* ESDHC1 */
+                                        cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */
+                                        status = "okay";
+                                };
+                                esdhc@50020000 { /* ESDHC3 */
+                                        cd-gpios = <&gpio2 11 0>; /* GPIO3_11 */
+                                        wp-gpios = <&gpio2 12 0>; /* GPIO3_12 */
+                                        status = "okay";
+                                };
+                        };
+                        wdog@53f98000 { /* WDOG1 */
+                                status = "okay";
+                        };
+                        iomuxc@53fa8000 {
+                                compatible = "fsl,imx53-iomuxc-qsb";
+                                reg = <0x53fa8000 0x4000>;
+                        };
+                        uart0: uart@53fbc000 { /* UART1 */
+                                status = "okay";
+                        };
+                };
+                aips@60000000 { /* AIPS2 */
+                        sdma@63fb0000 {
+                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
+                        };
+                        i2c@63fc4000 { /* I2C2 */
+                                status = "okay";
+                                codec: sgtl5000@0a {
+                                        compatible = "fsl,sgtl5000";
+                                        reg = <0x0a>;
+                                };
+                        };
+                        i2c@63fc8000 { /* I2C1 */
+                                status = "okay";
+                                accelerometer: mma8450@1c {
+                                        compatible = "fsl,mma8450";
+                                        reg = <0x1c>;
+                                };
+                                pmic: dialog@48 {
+                                        compatible = "dialog,da9053", "dialog,da9052";
+                                        reg = <0x48>;
+                                };
+                        };
+                        fec@63fec000 {
+                                phy-mode = "rmii";
+                                phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */
+                                status = "okay";
+                        };
+                };
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                power {
+                        label = "Power Button";
+                        gpios = <&gpio0 8 0>; /* GPIO1_8 */
+                        linux,code = <116>; /* KEY_POWER */
+                        gpio-key,wakeup;
+                };
+                volume-up {
+                        label = "Volume Up";
+                        gpios = <&gpio1 14 0>; /* GPIO2_14 */
+                        linux,code = <115>; /* KEY_VOLUMEUP */
+                };
+                volume-down {
+                        label = "Volume Down";
+                        gpios = <&gpio1 15 0>; /* GPIO2_15 */
+                        linux,code = <114>; /* KEY_VOLUMEDOWN */
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                user {
+                        label = "Heartbeat";
+                        gpios = <&gpio6 7 0>; /* GPIO7_7 */
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
new file mode 100644
index 000000000000..b1c062eea715
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -0,0 +1,169 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "imx53.dtsi"
+/ {
+        model = "Freescale i.MX53 Smart Mobile Reference Design Board";
+        compatible = "fsl,imx53-smd", "fsl,imx53";
+        chosen {
+                bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
+        };
+        memory {
+                reg = <0x70000000 0x40000000>;
+        };
+        soc {
+                aips@50000000 { /* AIPS1 */
+                        spba@50000000 {
+                                esdhc@50004000 { /* ESDHC1 */
+                                        cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */
+                                        wp-gpios = <&gpio3 11 0>; /* GPIO4_11 */
+                                        status = "okay";
+                                };
+                                esdhc@50008000 { /* ESDHC2 */
+                                        fsl,card-wired;
+                                        status = "okay";
+                                };
+                                uart2: uart@5000c000 { /* UART3 */
+                                        fsl,uart-has-rtscts;
+                                        status = "okay";
+                                };
+                                ecspi@50010000 { /* ECSPI1 */
+                                        fsl,spi-num-chipselects = <2>;
+                                        cs-gpios = <&gpio1 30 0>, /* GPIO2_30 */
+                                                   <&gpio2 19 0>; /* GPIO3_19 */
+                                        status = "okay";
+                                        zigbee: mc1323@0 {
+                                                compatible = "fsl,mc1323";
+                                                spi-max-frequency = <8000000>;
+                                                reg = <0>;
+                                        };
+                                        flash: m25p32@1 {
+                                                #address-cells = <1>;
+                                                #size-cells = <1>;
+                                                compatible = "st,m25p32", "st,m25p";
+                                                spi-max-frequency = <20000000>;
+                                                reg = <1>;
+                                                partition@0 {
+                                                        label = "U-Boot";
+                                                        reg = <0x0 0x40000>;
+                                                        read-only;
+                                                };
+                                                partition@40000 {
+                                                        label = "Kernel";
+                                                        reg = <0x40000 0x3c0000>;
+                                                };
+                                        };
+                                };
+                                esdhc@50020000 { /* ESDHC3 */
+                                        fsl,card-wired;
+                                        status = "okay";
+                                };
+                        };
+                        wdog@53f98000 { /* WDOG1 */
+                                status = "okay";
+                        };
+                        iomuxc@53fa8000 {
+                                compatible = "fsl,imx53-iomuxc-smd";
+                                reg = <0x53fa8000 0x4000>;
+                        };
+                        uart0: uart@53fbc000 { /* UART1 */
+                                status = "okay";
+                        };
+                        uart1: uart@53fc0000 { /* UART2 */
+                                status = "okay";
+                        };
+                };
+                aips@60000000 { /* AIPS2 */
+                        sdma@63fb0000 {
+                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
+                        };
+                        i2c@63fc4000 { /* I2C2 */
+                                status = "okay";
+                                codec: sgtl5000@0a {
+                                        compatible = "fsl,sgtl5000";
+                                        reg = <0x0a>;
+                                };
+                                magnetometer: mag3110@0e {
+                                        compatible = "fsl,mag3110";
+                                        reg = <0x0e>;
+                                };
+                                touchkey: mpr121@5a {
+                                        compatible = "fsl,mpr121";
+                                        reg = <0x5a>;
+                                };
+                        };
+                        i2c@63fc8000 { /* I2C1 */
+                                status = "okay";
+                                accelerometer: mma8450@1c {
+                                        compatible = "fsl,mma8450";
+                                        reg = <0x1c>;
+                                };
+                                camera: ov5642@3c {
+                                        compatible = "ovti,ov5642";
+                                        reg = <0x3c>;
+                                };
+                                pmic: dialog@48 {
+                                        compatible = "dialog,da9053", "dialog,da9052";
+                                        reg = <0x48>;
+                                };
+                        };
+                        fec@63fec000 {
+                                phy-mode = "rmii";
+                                phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */
+                                status = "okay";
+                        };
+                };
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                volume-up {
+                        label = "Volume Up";
+                        gpios = <&gpio1 14 0>; /* GPIO2_14 */
+                        linux,code = <115>; /* KEY_VOLUMEUP */
+                };
+                volume-down {
+                        label = "Volume Down";
+                        gpios = <&gpio1 15 0>; /* GPIO2_15 */
+                        linux,code = <114>; /* KEY_VOLUMEDOWN */
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
new file mode 100644
index 000000000000..099cd84ee372
--- /dev/null
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -0,0 +1,301 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/include/ "skeleton.dtsi"
+/ {
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
+                serial4 = &uart4;
+        };
+        tzic: tz-interrupt-controller@0fffc000 {
+                compatible = "fsl,imx53-tzic", "fsl,tzic";
+                interrupt-controller;
+                #interrupt-cells = <1>;
+                reg = <0x0fffc000 0x4000>;
+        };
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                ckil {
+                        compatible = "fsl,imx-ckil", "fixed-clock";
+                        clock-frequency = <32768>;
+                };
+                ckih1 {
+                        compatible = "fsl,imx-ckih1", "fixed-clock";
+                        clock-frequency = <22579200>;
+                };
+                ckih2 {
+                        compatible = "fsl,imx-ckih2", "fixed-clock";
+                        clock-frequency = <0>;
+                };
+                osc {
+                        compatible = "fsl,imx-osc", "fixed-clock";
+                        clock-frequency = <24000000>;
+                };
+        };
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&tzic>;
+                ranges;
+                aips@50000000 { /* AIPS1 */
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x50000000 0x10000000>;
+                        ranges;
+                        spba@50000000 {
+                                compatible = "fsl,spba-bus", "simple-bus";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0x50000000 0x40000>;
+                                ranges;
+                                esdhc@50004000 { /* ESDHC1 */
+                                        compatible = "fsl,imx53-esdhc";
+                                        reg = <0x50004000 0x4000>;
+                                        interrupts = <1>;
+                                        status = "disabled";
+                                };
+                                esdhc@50008000 { /* ESDHC2 */
+                                        compatible = "fsl,imx53-esdhc";
+                                        reg = <0x50008000 0x4000>;
+                                        interrupts = <2>;
+                                        status = "disabled";
+                                };
+                                uart2: uart@5000c000 { /* UART3 */
+                                        compatible = "fsl,imx53-uart", "fsl,imx21-uart";
+                                        reg = <0x5000c000 0x4000>;
+                                        interrupts = <33>;
+                                        status = "disabled";
+                                };
+                                ecspi@50010000 { /* ECSPI1 */
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
+                                        reg = <0x50010000 0x4000>;
+                                        interrupts = <36>;
+                                        status = "disabled";
+                                };
+                                esdhc@50020000 { /* ESDHC3 */
+                                        compatible = "fsl,imx53-esdhc";
+                                        reg = <0x50020000 0x4000>;
+                                        interrupts = <3>;
+                                        status = "disabled";
+                                };
+                                esdhc@50024000 { /* ESDHC4 */
+                                        compatible = "fsl,imx53-esdhc";
+                                        reg = <0x50024000 0x4000>;
+                                        interrupts = <4>;
+                                        status = "disabled";
+                                };
+                        };
+                        gpio0: gpio@53f84000 { /* GPIO1 */
+                                compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+                                reg = <0x53f84000 0x4000>;
+                                interrupts = <50 51>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+                        gpio1: gpio@53f88000 { /* GPIO2 */
+                                compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+                                reg = <0x53f88000 0x4000>;
+                                interrupts = <52 53>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+                        gpio2: gpio@53f8c000 { /* GPIO3 */
+                                compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+                                reg = <0x53f8c000 0x4000>;
+                                interrupts = <54 55>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+                        gpio3: gpio@53f90000 { /* GPIO4 */
+                                compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+                                reg = <0x53f90000 0x4000>;
+                                interrupts = <56 57>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+                        wdog@53f98000 { /* WDOG1 */
+                                compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
+                                reg = <0x53f98000 0x4000>;
+                                interrupts = <58>;
+                                status = "disabled";
+                        };
+                        wdog@53f9c000 { /* WDOG2 */
+                                compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
+                                reg = <0x53f9c000 0x4000>;
+                                interrupts = <59>;
+                                status = "disabled";
+                        };
+                        uart0: uart@53fbc000 { /* UART1 */
+                                compatible = "fsl,imx53-uart", "fsl,imx21-uart";
+                                reg = <0x53fbc000 0x4000>;
+                                interrupts = <31>;
+                                status = "disabled";
+                        };
+                        uart1: uart@53fc0000 { /* UART2 */
+                                compatible = "fsl,imx53-uart", "fsl,imx21-uart";
+                                reg = <0x53fc0000 0x4000>;
+                                interrupts = <32>;
+                                status = "disabled";
+                        };
+                        gpio4: gpio@53fdc000 { /* GPIO5 */
+                                compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+                                reg = <0x53fdc000 0x4000>;
+                                interrupts = <103 104>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+                        gpio5: gpio@53fe0000 { /* GPIO6 */
+                                compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+                                reg = <0x53fe0000 0x4000>;
+                                interrupts = <105 106>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+                        gpio6: gpio@53fe4000 { /* GPIO7 */
+                                compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+                                reg = <0x53fe4000 0x4000>;
+                                interrupts = <107 108>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+                        i2c@53fec000 { /* I2C3 */
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
+                                reg = <0x53fec000 0x4000>;
+                                interrupts = <64>;
+                                status = "disabled";
+                        };
+                        uart3: uart@53ff0000 { /* UART4 */
+                                compatible = "fsl,imx53-uart", "fsl,imx21-uart";
+                                reg = <0x53ff0000 0x4000>;
+                                interrupts = <13>;
+                                status = "disabled";
+                        };
+                };
+                aips@60000000 { /* AIPS2 */
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x60000000 0x10000000>;
+                        ranges;
+                        uart4: uart@63f90000 { /* UART5 */
+                                compatible = "fsl,imx53-uart", "fsl,imx21-uart";
+                                reg = <0x63f90000 0x4000>;
+                                interrupts = <86>;
+                                status = "disabled";
+                        };
+                        ecspi@63fac000 { /* ECSPI2 */
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
+                                reg = <0x63fac000 0x4000>;
+                                interrupts = <37>;
+                                status = "disabled";
+                        };
+                        sdma@63fb0000 {
+                                compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
+                                reg = <0x63fb0000 0x4000>;
+                                interrupts = <6>;
+                        };
+                        cspi@63fc0000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
+                                reg = <0x63fc0000 0x4000>;
+                                interrupts = <38>;
+                                status = "disabled";
+                        };
+                        i2c@63fc4000 { /* I2C2 */
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
+                                reg = <0x63fc4000 0x4000>;
+                                interrupts = <63>;
+                                status = "disabled";
+                        };
+                        i2c@63fc8000 { /* I2C1 */
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
+                                reg = <0x63fc8000 0x4000>;
+                                interrupts = <62>;
+                                status = "disabled";
+                        };
+                        fec@63fec000 {
+                                compatible = "fsl,imx53-fec", "fsl,imx25-fec";
+                                reg = <0x63fec000 0x4000>;
+                                interrupts = <87>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts
new file mode 100644
index 000000000000..072974e443f2
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "imx6q.dtsi"
+/ {
+        model = "Freescale i.MX6 Quad SABRE Automotive Board";
+        compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
+        chosen {
+                bootargs = "console=ttymxc0,115200 root=/dev/mmcblk3p3 rootwait";
+        };
+        memory {
+                reg = <0x10000000 0x80000000>;
+        };
+        soc {
+                aips-bus@02100000 { /* AIPS2 */
+                        enet@02188000 {
+                                phy-mode = "rgmii";
+                                local-mac-address = [00 04 9F 01 1B 61];
+                                status = "okay";
+                        };
+                        usdhc@02198000 { /* uSDHC3 */
+                                cd-gpios = <&gpio5 11 0>; /* GPIO6_11 */
+                                wp-gpios = <&gpio5 14 0>; /* GPIO6_14 */
+                                status = "okay";
+                        };
+                        usdhc@0219c000 { /* uSDHC4 */
+                                fsl,card-wired;
+                                status = "okay";
+                        };
+                        uart3: uart@021f0000 { /* UART4 */
+                                status = "okay";
+                        };
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                debug-led {
+                        label = "Heartbeat";
+                        gpios = <&gpio2 25 0>; /* GPIO3_25 */
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
new file mode 100644
index 000000000000..7dda599558cc
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -0,0 +1,575 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/include/ "skeleton.dtsi"
+/ {
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
+                serial4 = &uart4;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        compatible = "arm,cortex-a9";
+                        reg = <0>;
+                        next-level-cache = <&L2>;
+                };
+                cpu@1 {
+                        compatible = "arm,cortex-a9";
+                        reg = <1>;
+                        next-level-cache = <&L2>;
+                };
+                cpu@2 {
+                        compatible = "arm,cortex-a9";
+                        reg = <2>;
+                        next-level-cache = <&L2>;
+                };
+                cpu@3 {
+                        compatible = "arm,cortex-a9";
+                        reg = <3>;
+                        next-level-cache = <&L2>;
+                };
+        };
+        intc: interrupt-controller@00a01000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                interrupt-controller;
+                reg = <0x00a01000 0x1000>,
+                      <0x00a00100 0x100>;
+        };
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                ckil {
+                        compatible = "fsl,imx-ckil", "fixed-clock";
+                        clock-frequency = <32768>;
+                };
+                ckih1 {
+                        compatible = "fsl,imx-ckih1", "fixed-clock";
+                        clock-frequency = <0>;
+                };
+                osc {
+                        compatible = "fsl,imx-osc", "fixed-clock";
+                        clock-frequency = <24000000>;
+                };
+        };
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&intc>;
+                ranges;
+                timer@00a00600 {
+                        compatible = "arm,smp-twd";
+                        reg = <0x00a00600 0x100>;
+                        interrupts = <1 13 0xf4>;
+                };
+                L2: l2-cache@00a02000 {
+                        compatible = "arm,pl310-cache";
+                        reg = <0x00a02000 0x1000>;
+                        interrupts = <0 92 0x04>;
+                        cache-unified;
+                        cache-level = <2>;
+                };
+                aips-bus@02000000 { /* AIPS1 */
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x02000000 0x100000>;
+                        ranges;
+                        spba-bus@02000000 {
+                                compatible = "fsl,spba-bus", "simple-bus";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0x02000000 0x40000>;
+                                ranges;
+                                spdif@02004000 {
+                                        reg = <0x02004000 0x4000>;
+                                        interrupts = <0 52 0x04>;
+                                };
+                                ecspi@02008000 { /* eCSPI1 */
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
+                                        reg = <0x02008000 0x4000>;
+                                        interrupts = <0 31 0x04>;
+                                        status = "disabled";
+                                };
+                                ecspi@0200c000 { /* eCSPI2 */
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
+                                        reg = <0x0200c000 0x4000>;
+                                        interrupts = <0 32 0x04>;
+                                        status = "disabled";
+                                };
+                                ecspi@02010000 { /* eCSPI3 */
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
+                                        reg = <0x02010000 0x4000>;
+                                        interrupts = <0 33 0x04>;
+                                        status = "disabled";
+                                };
+                                ecspi@02014000 { /* eCSPI4 */
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
+                                        reg = <0x02014000 0x4000>;
+                                        interrupts = <0 34 0x04>;
+                                        status = "disabled";
+                                };
+                                ecspi@02018000 { /* eCSPI5 */
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
+                                        reg = <0x02018000 0x4000>;
+                                        interrupts = <0 35 0x04>;
+                                        status = "disabled";
+                                };
+                                uart0: uart@02020000 { /* UART1 */
+                                        compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+                                        reg = <0x02020000 0x4000>;
+                                        interrupts = <0 26 0x04>;
+                                        status = "disabled";
+                                };
+                                esai@02024000 {
+                                        reg = <0x02024000 0x4000>;
+                                        interrupts = <0 51 0x04>;
+                                };
+                                ssi@02028000 { /* SSI1 */
+                                        reg = <0x02028000 0x4000>;
+                                        interrupts = <0 46 0x04>;
+                                };
+                                ssi@0202c000 { /* SSI2 */
+                                        reg = <0x0202c000 0x4000>;
+                                        interrupts = <0 47 0x04>;
+                                };
+                                ssi@02030000 { /* SSI3 */
+                                        reg = <0x02030000 0x4000>;
+                                        interrupts = <0 48 0x04>;
+                                };
+                                asrc@02034000 {
+                                        reg = <0x02034000 0x4000>;
+                                        interrupts = <0 50 0x04>;
+                                };
+                                spba@0203c000 {
+                                        reg = <0x0203c000 0x4000>;
+                                };
+                        };
+                        vpu@02040000 {
+                                reg = <0x02040000 0x3c000>;
+                                interrupts = <0 3 0x04 0 12 0x04>;
+                        };
+                        aipstz@0207c000 { /* AIPSTZ1 */
+                                reg = <0x0207c000 0x4000>;
+                        };
+                        pwm@02080000 { /* PWM1 */
+                                reg = <0x02080000 0x4000>;
+                                interrupts = <0 83 0x04>;
+                        };
+                        pwm@02084000 { /* PWM2 */
+                                reg = <0x02084000 0x4000>;
+                                interrupts = <0 84 0x04>;
+                        };
+                        pwm@02088000 { /* PWM3 */
+                                reg = <0x02088000 0x4000>;
+                                interrupts = <0 85 0x04>;
+                        };
+                        pwm@0208c000 { /* PWM4 */
+                                reg = <0x0208c000 0x4000>;
+                                interrupts = <0 86 0x04>;
+                        };
+                        flexcan@02090000 { /* CAN1 */
+                                reg = <0x02090000 0x4000>;
+                                interrupts = <0 110 0x04>;
+                        };
+                        flexcan@02094000 { /* CAN2 */
+                                reg = <0x02094000 0x4000>;
+                                interrupts = <0 111 0x04>;
+                        };
+                        gpt@02098000 {
+                                compatible = "fsl,imx6q-gpt";
+                                reg = <0x02098000 0x4000>;
+                                interrupts = <0 55 0x04>;
+                        };
+                        gpio0: gpio@0209c000 { /* GPIO1 */
+                                compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
+                                reg = <0x0209c000 0x4000>;
+                                interrupts = <0 66 0x04 0 67 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+                        gpio1: gpio@020a0000 { /* GPIO2 */
+                                compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
+                                reg = <0x020a0000 0x4000>;
+                                interrupts = <0 68 0x04 0 69 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+                        gpio2: gpio@020a4000 { /* GPIO3 */
+                                compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
+                                reg = <0x020a4000 0x4000>;
+                                interrupts = <0 70 0x04 0 71 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+                        gpio3: gpio@020a8000 { /* GPIO4 */
+                                compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
+                                reg = <0x020a8000 0x4000>;
+                                interrupts = <0 72 0x04 0 73 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+                        gpio4: gpio@020ac000 { /* GPIO5 */
+                                compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
+                                reg = <0x020ac000 0x4000>;
+                                interrupts = <0 74 0x04 0 75 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+                        gpio5: gpio@020b0000 { /* GPIO6 */
+                                compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
+                                reg = <0x020b0000 0x4000>;
+                                interrupts = <0 76 0x04 0 77 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+                        gpio6: gpio@020b4000 { /* GPIO7 */
+                                compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
+                                reg = <0x020b4000 0x4000>;
+                                interrupts = <0 78 0x04 0 79 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+                        kpp@020b8000 {
+                                reg = <0x020b8000 0x4000>;
+                                interrupts = <0 82 0x04>;
+                        };
+                        wdog@020bc000 { /* WDOG1 */
+                                compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
+                                reg = <0x020bc000 0x4000>;
+                                interrupts = <0 80 0x04>;
+                                status = "disabled";
+                        };
+                        wdog@020c0000 { /* WDOG2 */
+                                compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
+                                reg = <0x020c0000 0x4000>;
+                                interrupts = <0 81 0x04>;
+                                status = "disabled";
+                        };
+                        ccm@020c4000 {
+                                compatible = "fsl,imx6q-ccm";
+                                reg = <0x020c4000 0x4000>;
+                                interrupts = <0 87 0x04 0 88 0x04>;
+                        };
+                        anatop@020c8000 {
+                                compatible = "fsl,imx6q-anatop";
+                                reg = <0x020c8000 0x1000>;
+                                interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
+                        };
+                        usbphy@020c9000 { /* USBPHY1 */
+                                reg = <0x020c9000 0x1000>;
+                                interrupts = <0 44 0x04>;
+                        };
+                        usbphy@020ca000 { /* USBPHY2 */
+                                reg = <0x020ca000 0x1000>;
+                                interrupts = <0 45 0x04>;
+                        };
+                        snvs@020cc000 {
+                                reg = <0x020cc000 0x4000>;
+                                interrupts = <0 19 0x04 0 20 0x04>;
+                        };
+                        epit@020d0000 { /* EPIT1 */
+                                reg = <0x020d0000 0x4000>;
+                                interrupts = <0 56 0x04>;
+                        };
+                        epit@020d4000 { /* EPIT2 */
+                                reg = <0x020d4000 0x4000>;
+                                interrupts = <0 57 0x04>;
+                        };
+                        src@020d8000 {
+                                compatible = "fsl,imx6q-src";
+                                reg = <0x020d8000 0x4000>;
+                                interrupts = <0 91 0x04 0 96 0x04>;
+                        };
+                        gpc@020dc000 {
+                                compatible = "fsl,imx6q-gpc";
+                                reg = <0x020dc000 0x4000>;
+                                interrupts = <0 89 0x04 0 90 0x04>;
+                        };
+                        iomuxc@020e0000 {
+                                reg = <0x020e0000 0x4000>;
+                        };
+                        dcic@020e4000 { /* DCIC1 */
+                                reg = <0x020e4000 0x4000>;
+                                interrupts = <0 124 0x04>;
+                        };
+                        dcic@020e8000 { /* DCIC2 */
+                                reg = <0x020e8000 0x4000>;
+                                interrupts = <0 125 0x04>;
+                        };
+                        sdma@020ec000 {
+                                compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
+                                reg = <0x020ec000 0x4000>;
+                                interrupts = <0 2 0x04>;
+                        };
+                };
+                aips-bus@02100000 { /* AIPS2 */
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x02100000 0x100000>;
+                        ranges;
+                        caam@02100000 {
+                                reg = <0x02100000 0x40000>;
+                                interrupts = <0 105 0x04 0 106 0x04>;
+                        };
+                        aipstz@0217c000 { /* AIPSTZ2 */
+                                reg = <0x0217c000 0x4000>;
+                        };
+                        enet@02188000 {
+                                compatible = "fsl,imx6q-fec";
+                                reg = <0x02188000 0x4000>;
+                                interrupts = <0 118 0x04 0 119 0x04>;
+                                status = "disabled";
+                        };
+                        mlb@0218c000 {
+                                reg = <0x0218c000 0x4000>;
+                                interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
+                        };
+                        usdhc@02190000 { /* uSDHC1 */
+                                compatible = "fsl,imx6q-usdhc";
+                                reg = <0x02190000 0x4000>;
+                                interrupts = <0 22 0x04>;
+                                status = "disabled";
+                        };
+                        usdhc@02194000 { /* uSDHC2 */
+                                compatible = "fsl,imx6q-usdhc";
+                                reg = <0x02194000 0x4000>;
+                                interrupts = <0 23 0x04>;
+                                status = "disabled";
+                        };
+                        usdhc@02198000 { /* uSDHC3 */
+                                compatible = "fsl,imx6q-usdhc";
+                                reg = <0x02198000 0x4000>;
+                                interrupts = <0 24 0x04>;
+                                status = "disabled";
+                        };
+                        usdhc@0219c000 { /* uSDHC4 */
+                                compatible = "fsl,imx6q-usdhc";
+                                reg = <0x0219c000 0x4000>;
+                                interrupts = <0 25 0x04>;
+                                status = "disabled";
+                        };
+                        i2c@021a0000 { /* I2C1 */
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
+                                reg = <0x021a0000 0x4000>;
+                                interrupts = <0 36 0x04>;
+                                status = "disabled";
+                        };
+                        i2c@021a4000 { /* I2C2 */
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
+                                reg = <0x021a4000 0x4000>;
+                                interrupts = <0 37 0x04>;
+                                status = "disabled";
+                        };
+                        i2c@021a8000 { /* I2C3 */
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
+                                reg = <0x021a8000 0x4000>;
+                                interrupts = <0 38 0x04>;
+                                status = "disabled";
+                        };
+                        romcp@021ac000 {
+                                reg = <0x021ac000 0x4000>;
+                        };
+                        mmdc@021b0000 { /* MMDC0 */
+                                compatible = "fsl,imx6q-mmdc";
+                                reg = <0x021b0000 0x4000>;
+                        };
+                        mmdc@021b4000 { /* MMDC1 */
+                                reg = <0x021b4000 0x4000>;
+                        };
+                        weim@021b8000 {
+                                reg = <0x021b8000 0x4000>;
+                                interrupts = <0 14 0x04>;
+                        };
+                        ocotp@021bc000 {
+                                reg = <0x021bc000 0x4000>;
+                        };
+                        ocotp@021c0000 {
+                                reg = <0x021c0000 0x4000>;
+                                interrupts = <0 21 0x04>;
+                        };
+                        tzasc@021d0000 { /* TZASC1 */
+                                reg = <0x021d0000 0x4000>;
+                                interrupts = <0 108 0x04>;
+                        };
+                        tzasc@021d4000 { /* TZASC2 */
+                                reg = <0x021d4000 0x4000>;
+                                interrupts = <0 109 0x04>;
+                        };
+                        audmux@021d8000 {
+                                reg = <0x021d8000 0x4000>;
+                        };
+                        mipi@021dc000 { /* MIPI-CSI */
+                                reg = <0x021dc000 0x4000>;
+                        };
+                        mipi@021e0000 { /* MIPI-DSI */
+                                reg = <0x021e0000 0x4000>;
+                        };
+                        vdoa@021e4000 {
+                                reg = <0x021e4000 0x4000>;
+                                interrupts = <0 18 0x04>;
+                        };
+                        uart1: uart@021e8000 { /* UART2 */
+                                compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+                                reg = <0x021e8000 0x4000>;
+                                interrupts = <0 27 0x04>;
+                                status = "disabled";
+                        };
+                        uart2: uart@021ec000 { /* UART3 */
+                                compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+                                reg = <0x021ec000 0x4000>;
+                                interrupts = <0 28 0x04>;
+                                status = "disabled";
+                        };
+                        uart3: uart@021f0000 { /* UART4 */
+                                compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+                                reg = <0x021f0000 0x4000>;
+                                interrupts = <0 29 0x04>;
+                                status = "disabled";
+                        };
+                        uart4: uart@021f4000 { /* UART5 */
+                                compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+                                reg = <0x021f4000 0x4000>;
+                                interrupts = <0 30 0x04>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts
new file mode 100644
index 000000000000..15ded0deaa79
--- /dev/null
+++ b/arch/arm/boot/dts/msm8660-surf.dts
@@ -0,0 +1,24 @@
+/dts-v1/;
+/include/ "skeleton.dtsi"
+/ {
+        model = "Qualcomm MSM8660 SURF";
+        compatible = "qcom,msm8660-surf", "qcom,msm8660";
+        interrupt-parent = <&intc>;
+        intc: interrupt-controller@02080000 {
+                compatible = "qcom,msm-8660-qgic";
+                interrupt-controller;
+                #interrupt-cells = <1>;
+                reg = < 0x02080000 0x1000 >,
+                      < 0x02081000 0x1000 >;
+        };
+        serial@19c400000 {
+                compatible = "qcom,msm-hsuart", "qcom,msm-uart";
+                reg = <0x19c40000 0x1000>,
+                      <0x19c00000 0x1000>;
+                interrupts = <195>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
new file mode 100644
index 000000000000..9486be62bcdd
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+/include/ "omap3.dtsi"
+/ {
+        model = "TI OMAP3 BeagleBoard";
+        compatible = "ti,omap3-beagle", "ti,omap3";
+        /*
+         * Since the initial device tree board file does not create any
+         * devices (MMC, network...), the only way to boot is to provide a
+         * ramdisk.
+         */
+        chosen {
+                bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug earlyprintk";
+        };
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x20000000>; /* 512 MB */
+        };
+};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
new file mode 100644
index 000000000000..d202bb5ec7ef
--- /dev/null
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -0,0 +1,63 @@
+/*
+ * Device Tree Source for OMAP3 SoC
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+/include/ "skeleton.dtsi"
+/ {
+        compatible = "ti,omap3430", "ti,omap3";
+        cpus {
+                cpu@0 {
+                        compatible = "arm,cortex-a8";
+                };
+        };
+        /*
+         * The soc node represents the soc top level view. It is uses for IPs
+         * that are not memory mapped in the MPU view or for the MPU itself.
+         */
+        soc {
+                compatible = "ti,omap-infra";
+                mpu {
+                        compatible = "ti,omap3-mpu";
+                        ti,hwmods = "mpu";
+                };
+                iva {
+                        compatible = "ti,iva2.2";
+                        ti,hwmods = "iva";
+                        dsp {
+                                compatible = "ti,omap3-c64";
+                        };
+                };
+        };
+        /*
+         * XXX: Use a flat representation of the OMAP3 interconnect.
+         * The real OMAP interconnect network is quite complex.
+         * Since that will not bring real advantage to represent that in DT for
+         * the moment, just use a fake OCP bus entry to represent the whole bus
+         * hierarchy.
+         */
+        ocp {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                ti,hwmods = "l3_main";
+                intc: interrupt-controller@1 {
+                        compatible = "ti,omap3-intc";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
new file mode 100644
index 000000000000..c7026578ce7d
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+/include/ "omap4.dtsi"
+/ {
+        model = "TI OMAP4 PandaBoard";
+        compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4";
+        /*
+         * Since the initial device tree board file does not create any
+         * devices (MMC, network...), the only way to boot is to provide a
+         * ramdisk.
+         */
+        chosen {
+                bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug";
+        };
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x40000000>; /* 1 GB */
+        };
+};
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
new file mode 100644
index 000000000000..066e28c90328
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+/include/ "omap4.dtsi"
+/ {
+        model = "TI OMAP4 SDP board";
+        compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4";
+        /*
+         * Since the initial device tree board file does not create any
+         * devices (MMC, network...), the only way to boot is to provide a
+         * ramdisk.
+         */
+        chosen {
+                bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug";
+        };
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x40000000>; /* 1 GB */
+        };
+};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
new file mode 100644
index 000000000000..4c61c829043a
--- /dev/null
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*
+ * Carveout for multimedia usecases
+ * It should be the last 48MB of the first 512MB memory part
+ * In theory, it should not even exist. That zone should be reserved
+ * dynamically during the .reserve callback.
+ */
+/memreserve/ 0x9d000000 0x03000000;
+/include/ "skeleton.dtsi"
+/ {
+        compatible = "ti,omap4430", "ti,omap4";
+        interrupt-parent = <&gic>;
+        aliases {
+        };
+        cpus {
+                cpu@0 {
+                        compatible = "arm,cortex-a9";
+                };
+                cpu@1 {
+                        compatible = "arm,cortex-a9";
+                };
+        };
+        /*
+         * The soc node represents the soc top level view. It is uses for IPs
+         * that are not memory mapped in the MPU view or for the MPU itself.
+         */
+        soc {
+                compatible = "ti,omap-infra";
+                mpu {
+                        compatible = "ti,omap4-mpu";
+                        ti,hwmods = "mpu";
+                };
+                dsp {
+                        compatible = "ti,omap3-c64";
+                        ti,hwmods = "dsp";
+                };
+                iva {
+                        compatible = "ti,ivahd";
+                        ti,hwmods = "iva";
+                };
+        };
+        /*
+         * XXX: Use a flat representation of the OMAP4 interconnect.
+         * The real OMAP interconnect network is quite complex.
+         *
+         * MPU -+-- MPU_PRIVATE - GIC, L2
+         *      |
+         *      +----------------+----------+
+         *      |                |          |
+         *      +            +- EMIF - DDR  |
+         *      |            |              |
+         *      |            +     +--------+
+         *      |            |     |
+         *      |            +- L4_ABE - AESS, MCBSP, TIMERs...
+         *      |            |
+         *      +- L3_MAIN --+- L4_CORE - IPs...
+         *                   |
+         *                   +- L4_PER - IPs...
+         *                   |
+         *                   +- L4_CFG -+- L4_WKUP - IPs...
+         *                   |          |
+         *                   |          +- IPs...
+         *                   +- IPU ----+
+         *                   |          |
+         *                   +- DSP ----+
+         *                   |          |
+         *                   +- DSS ----+
+         *
+         * Since that will not bring real advantage to represent that in DT for
+         * the moment, just use a fake OCP bus entry to represent the whole bus
+         * hierarchy.
+         */
+        ocp {
+                compatible = "ti,omap4-l3-noc", "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
+                gic: interrupt-controller@48241000 {
+                        compatible = "arm,cortex-a9-gic";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        reg = <0x48241000 0x1000>,
+                              <0x48240100 0x0100>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
new file mode 100644
index 000000000000..f0a8c2068ea7
--- /dev/null
+++ b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
@@ -0,0 +1,249 @@
+/*
+ *  Copyright (C) 2011 Picochip, Jamie Iles
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/include/ "skeleton.dtsi"
+/ {
+        model = "Picochip picoXcell PC3X2";
+        compatible = "picochip,pc3x2";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        compatible = "arm,1176jz-s";
+                        clock-frequency = <400000000>;
+                        reg = <0>;
+                        d-cache-line-size = <32>;
+                        d-cache-size = <32768>;
+                        i-cache-line-size = <32>;
+                        i-cache-size = <32768>;
+                };
+        };
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                pclk: clock@0 {
+                        compatible = "fixed-clock";
+                        clock-outputs = "bus", "pclk";
+                        clock-frequency = <200000000>;
+                        ref-clock = <&ref_clk>, "ref";
+                };
+        };
+        paxi {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0 0x80000000 0x400000>;
+                emac: gem@30000 {
+                        compatible = "cadence,gem";
+                        reg = <0x30000 0x10000>;
+                        interrupts = <31>;
+                };
+                dmac1: dmac@40000 {
+                        compatible = "snps,dw-dmac";
+                        reg = <0x40000 0x10000>;
+                        interrupts = <25>;
+                };
+                dmac2: dmac@50000 {
+                        compatible = "snps,dw-dmac";
+                        reg = <0x50000 0x10000>;
+                        interrupts = <26>;
+                };
+                vic0: interrupt-controller@60000 {
+                        compatible = "arm,pl192-vic";
+                        interrupt-controller;
+                        reg = <0x60000 0x1000>;
+                        #interrupt-cells = <1>;
+                };
+                vic1: interrupt-controller@64000 {
+                        compatible = "arm,pl192-vic";
+                        interrupt-controller;
+                        reg = <0x64000 0x1000>;
+                        #interrupt-cells = <1>;
+                };
+                fuse: picoxcell-fuse@80000 {
+                        compatible = "picoxcell,fuse-pc3x2";
+                        reg = <0x80000 0x10000>;
+                };
+                ssi: picoxcell-spi@90000 {
+                        compatible = "picoxcell,spi";
+                        reg = <0x90000 0x10000>;
+                        interrupt-parent = <&vic0>;
+                        interrupts = <10>;
+                };
+                ipsec: spacc@100000 {
+                        compatible = "picochip,spacc-ipsec";
+                        reg = <0x100000 0x10000>;
+                        interrupt-parent = <&vic0>;
+                        interrupts = <24>;
+                        ref-clock = <&pclk>, "ref";
+                };
+                srtp: spacc@140000 {
+                        compatible = "picochip,spacc-srtp";
+                        reg = <0x140000 0x10000>;
+                        interrupt-parent = <&vic0>;
+                        interrupts = <23>;
+                };
+                l2_engine: spacc@180000 {
+                        compatible = "picochip,spacc-l2";
+                        reg = <0x180000 0x10000>;
+                        interrupt-parent = <&vic0>;
+                        interrupts = <22>;
+                        ref-clock = <&pclk>, "ref";
+                };
+                apb {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x200000 0x80000>;
+                        rtc0: rtc@00000 {
+                                compatible = "picochip,pc3x2-rtc";
+                                clock-freq = <200000000>;
+                                reg = <0x00000 0xf>;
+                                interrupt-parent = <&vic1>;
+                                interrupts = <8>;
+                        };
+                        timer0: timer@10000 {
+                                compatible = "picochip,pc3x2-timer";
+                                interrupt-parent = <&vic0>;
+                                interrupts = <4>;
+                                clock-freq = <200000000>;
+                                reg = <0x10000 0x14>;
+                        };
+                        timer1: timer@10014 {
+                                compatible = "picochip,pc3x2-timer";
+                                interrupt-parent = <&vic0>;
+                                interrupts = <5>;
+                                clock-freq = <200000000>;
+                                reg = <0x10014 0x14>;
+                        };
+                        timer2: timer@10028 {
+                                compatible = "picochip,pc3x2-timer";
+                                interrupt-parent = <&vic0>;
+                                interrupts = <6>;
+                                clock-freq = <200000000>;
+                                reg = <0x10028 0x14>;
+                        };
+                        timer3: timer@1003c {
+                                compatible = "picochip,pc3x2-timer";
+                                interrupt-parent = <&vic0>;
+                                interrupts = <7>;
+                                clock-freq = <200000000>;
+                                reg = <0x1003c 0x14>;
+                        };
+                        gpio: gpio@20000 {
+                                compatible = "snps,dw-apb-gpio";
+                                reg = <0x20000 0x1000>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg-io-width = <4>;
+                                banka: gpio-controller@0 {
+                                        compatible = "snps,dw-apb-gpio-bank";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        gpio-generic,nr-gpio = <8>;
+                                        regoffset-dat = <0x50>;
+                                        regoffset-set = <0x00>;
+                                        regoffset-dirout = <0x04>;
+                                };
+                                bankb: gpio-controller@1 {
+                                        compatible = "snps,dw-apb-gpio-bank";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        gpio-generic,nr-gpio = <8>;
+                                        regoffset-dat = <0x54>;
+                                        regoffset-set = <0x0c>;
+                                        regoffset-dirout = <0x10>;
+                                };
+                        };
+                        uart0: uart@30000 {
+                                compatible = "snps,dw-apb-uart";
+                                reg = <0x30000 0x1000>;
+                                interrupt-parent = <&vic1>;
+                                interrupts = <10>;
+                                clock-frequency = <3686400>;
+                                reg-shift = <2>;
+                                reg-io-width = <4>;
+                        };
+                        uart1: uart@40000 {
+                                compatible = "snps,dw-apb-uart";
+                                reg = <0x40000 0x1000>;
+                                interrupt-parent = <&vic1>;
+                                interrupts = <9>;
+                                clock-frequency = <3686400>;
+                                reg-shift = <2>;
+                                reg-io-width = <4>;
+                        };
+                        wdog: watchdog@50000 {
+                                compatible = "snps,dw-apb-wdg";
+                                reg = <0x50000 0x10000>;
+                                interrupt-parent = <&vic0>;
+                                interrupts = <11>;
+                                bus-clock = <&pclk>, "bus";
+                        };
+                };
+        };
+        rwid-axi {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges;
+                ebi@50000000 {
+                        compatible = "simple-bus";
+                        #address-cells = <2>;
+                        #size-cells = <1>;
+                        ranges = <0 0 0x40000000 0x08000000
+                                  1 0 0x48000000 0x08000000
+                                  2 0 0x50000000 0x08000000
+                                  3 0 0x58000000 0x08000000>;
+                };
+                axi2pico@c0000000 {
+                        compatible = "picochip,axi2pico-pc3x2";
+                        reg = <0xc0000000 0x10000>;
+                        interrupts = <13 14 15 16 17 18 19 20 21>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
new file mode 100644
index 000000000000..daa962d191e6
--- /dev/null
+++ b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
@@ -0,0 +1,365 @@
+/*
+ *  Copyright (C) 2011 Picochip, Jamie Iles
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/include/ "skeleton.dtsi"
+/ {
+        model = "Picochip picoXcell PC3X3";
+        compatible = "picochip,pc3x3";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        compatible = "arm,1176jz-s";
+                        cpu-clock = <&arm_clk>, "cpu";
+                        reg = <0>;
+                        d-cache-line-size = <32>;
+                        d-cache-size = <32768>;
+                        i-cache-line-size = <32>;
+                        i-cache-size = <32768>;
+                };
+        };
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                clkgate: clkgate@800a0048 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x800a0048 4>;
+                        compatible = "picochip,pc3x3-clk-gate";
+                        tzprot_clk: clock@0 {
+                                compatible = "picochip,pc3x3-gated-clk";
+                                clock-outputs = "bus";
+                                picochip,clk-disable-bit = <0>;
+                                clock-frequency = <200000000>;
+                                ref-clock = <&ref_clk>, "ref";
+                        };
+                        spi_clk: clock@1 {
+                                compatible = "picochip,pc3x3-gated-clk";
+                                clock-outputs = "bus";
+                                picochip,clk-disable-bit = <1>;
+                                clock-frequency = <200000000>;
+                                ref-clock = <&ref_clk>, "ref";
+                        };
+                        dmac0_clk: clock@2 {
+                                compatible = "picochip,pc3x3-gated-clk";
+                                clock-outputs = "bus";
+                                picochip,clk-disable-bit = <2>;
+                                clock-frequency = <200000000>;
+                                ref-clock = <&ref_clk>, "ref";
+                        };
+                        dmac1_clk: clock@3 {
+                                compatible = "picochip,pc3x3-gated-clk";
+                                clock-outputs = "bus";
+                                picochip,clk-disable-bit = <3>;
+                                clock-frequency = <200000000>;
+                                ref-clock = <&ref_clk>, "ref";
+                        };
+                        ebi_clk: clock@4 {
+                                compatible = "picochip,pc3x3-gated-clk";
+                                clock-outputs = "bus";
+                                picochip,clk-disable-bit = <4>;
+                                clock-frequency = <200000000>;
+                                ref-clock = <&ref_clk>, "ref";
+                        };
+                        ipsec_clk: clock@5 {
+                                compatible = "picochip,pc3x3-gated-clk";
+                                clock-outputs = "bus";
+                                picochip,clk-disable-bit = <5>;
+                                clock-frequency = <200000000>;
+                                ref-clock = <&ref_clk>, "ref";
+                        };
+                        l2_clk: clock@6 {
+                                compatible = "picochip,pc3x3-gated-clk";
+                                clock-outputs = "bus";
+                                picochip,clk-disable-bit = <6>;
+                                clock-frequency = <200000000>;
+                                ref-clock = <&ref_clk>, "ref";
+                        };
+                        trng_clk: clock@7 {
+                                compatible = "picochip,pc3x3-gated-clk";
+                                clock-outputs = "bus";
+                                picochip,clk-disable-bit = <7>;
+                                clock-frequency = <200000000>;
+                                ref-clock = <&ref_clk>, "ref";
+                        };
+                        fuse_clk: clock@8 {
+                                compatible = "picochip,pc3x3-gated-clk";
+                                clock-outputs = "bus";
+                                picochip,clk-disable-bit = <8>;
+                                clock-frequency = <200000000>;
+                                ref-clock = <&ref_clk>, "ref";
+                        };
+                        otp_clk: clock@9 {
+                                compatible = "picochip,pc3x3-gated-clk";
+                                clock-outputs = "bus";
+                                picochip,clk-disable-bit = <9>;
+                                clock-frequency = <200000000>;
+                                ref-clock = <&ref_clk>, "ref";
+                        };
+                };
+                arm_clk: clock@11 {
+                        compatible = "picochip,pc3x3-pll";
+                        reg = <0x800a0050 0x8>;
+                        picochip,min-freq = <140000000>;
+                        picochip,max-freq = <700000000>;
+                        ref-clock = <&ref_clk>, "ref";
+                        clock-outputs = "cpu";
+                };
+                pclk: clock@12 {
+                        compatible = "fixed-clock";
+                        clock-outputs = "bus", "pclk";
+                        clock-frequency = <200000000>;
+                        ref-clock = <&ref_clk>, "ref";
+                };
+        };
+        paxi {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0 0x80000000 0x400000>;
+                emac: gem@30000 {
+                        compatible = "cadence,gem";
+                        reg = <0x30000 0x10000>;
+                        interrupt-parent = <&vic0>;
+                        interrupts = <31>;
+                };
+                dmac1: dmac@40000 {
+                        compatible = "snps,dw-dmac";
+                        reg = <0x40000 0x10000>;
+                        interrupt-parent = <&vic0>;
+                        interrupts = <25>;
+                };
+                dmac2: dmac@50000 {
+                        compatible = "snps,dw-dmac";
+                        reg = <0x50000 0x10000>;
+                        interrupt-parent = <&vic0>;
+                        interrupts = <26>;
+                };
+                vic0: interrupt-controller@60000 {
+                        compatible = "arm,pl192-vic";
+                        interrupt-controller;
+                        reg = <0x60000 0x1000>;
+                        #interrupt-cells = <1>;
+                };
+                vic1: interrupt-controller@64000 {
+                        compatible = "arm,pl192-vic";
+                        interrupt-controller;
+                        reg = <0x64000 0x1000>;
+                        #interrupt-cells = <1>;
+                };
+                fuse: picoxcell-fuse@80000 {
+                        compatible = "picoxcell,fuse-pc3x3";
+                        reg = <0x80000 0x10000>;
+                };
+                ssi: picoxcell-spi@90000 {
+                        compatible = "picoxcell,spi";
+                        reg = <0x90000 0x10000>;
+                        interrupt-parent = <&vic0>;
+                        interrupts = <10>;
+                };
+                ipsec: spacc@100000 {
+                        compatible = "picochip,spacc-ipsec";
+                        reg = <0x100000 0x10000>;
+                        interrupt-parent = <&vic0>;
+                        interrupts = <24>;
+                        ref-clock = <&ipsec_clk>, "ref";
+                };
+                srtp: spacc@140000 {
+                        compatible = "picochip,spacc-srtp";
+                        reg = <0x140000 0x10000>;
+                        interrupt-parent = <&vic0>;
+                        interrupts = <23>;
+                };
+                l2_engine: spacc@180000 {
+                        compatible = "picochip,spacc-l2";
+                        reg = <0x180000 0x10000>;
+                        interrupt-parent = <&vic0>;
+                        interrupts = <22>;
+                        ref-clock = <&l2_clk>, "ref";
+                };
+                apb {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x200000 0x80000>;
+                        rtc0: rtc@00000 {
+                                compatible = "picochip,pc3x2-rtc";
+                                clock-freq = <200000000>;
+                                reg = <0x00000 0xf>;
+                                interrupt-parent = <&vic0>;
+                                interrupts = <8>;
+                        };
+                        timer0: timer@10000 {
+                                compatible = "picochip,pc3x2-timer";
+                                interrupt-parent = <&vic0>;
+                                interrupts = <4>;
+                                clock-freq = <200000000>;
+                                reg = <0x10000 0x14>;
+                        };
+                        timer1: timer@10014 {
+                                compatible = "picochip,pc3x2-timer";
+                                interrupt-parent = <&vic0>;
+                                interrupts = <5>;
+                                clock-freq = <200000000>;
+                                reg = <0x10014 0x14>;
+                        };
+                        gpio: gpio@20000 {
+                                compatible = "snps,dw-apb-gpio";
+                                reg = <0x20000 0x1000>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg-io-width = <4>;
+                                banka: gpio-controller@0 {
+                                        compatible = "snps,dw-apb-gpio-bank";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        gpio-generic,nr-gpio = <8>;
+                                        regoffset-dat = <0x50>;
+                                        regoffset-set = <0x00>;
+                                        regoffset-dirout = <0x04>;
+                                };
+                                bankb: gpio-controller@1 {
+                                        compatible = "snps,dw-apb-gpio-bank";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        gpio-generic,nr-gpio = <16>;
+                                        regoffset-dat = <0x54>;
+                                        regoffset-set = <0x0c>;
+                                        regoffset-dirout = <0x10>;
+                                };
+                                bankd: gpio-controller@2 {
+                                        compatible = "snps,dw-apb-gpio-bank";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        gpio-generic,nr-gpio = <30>;
+                                        regoffset-dat = <0x5c>;
+                                        regoffset-set = <0x24>;
+                                        regoffset-dirout = <0x28>;
+                                };
+                        };
+                        uart0: uart@30000 {
+                                compatible = "snps,dw-apb-uart";
+                                reg = <0x30000 0x1000>;
+                                interrupt-parent = <&vic1>;
+                                interrupts = <10>;
+                                clock-frequency = <3686400>;
+                                reg-shift = <2>;
+                                reg-io-width = <4>;
+                        };
+                        uart1: uart@40000 {
+                                compatible = "snps,dw-apb-uart";
+                                reg = <0x40000 0x1000>;
+                                interrupt-parent = <&vic1>;
+                                interrupts = <9>;
+                                clock-frequency = <3686400>;
+                                reg-shift = <2>;
+                                reg-io-width = <4>;
+                        };
+                        wdog: watchdog@50000 {
+                                compatible = "snps,dw-apb-wdg";
+                                reg = <0x50000 0x10000>;
+                                interrupt-parent = <&vic0>;
+                                interrupts = <11>;
+                                bus-clock = <&pclk>, "bus";
+                        };
+                        timer2: timer@60000 {
+                                compatible = "picochip,pc3x2-timer";
+                                interrupt-parent = <&vic0>;
+                                interrupts = <6>;
+                                clock-freq = <200000000>;
+                                reg = <0x60000 0x14>;
+                        };
+                        timer3: timer@60014 {
+                                compatible = "picochip,pc3x2-timer";
+                                interrupt-parent = <&vic0>;
+                                interrupts = <7>;
+                                clock-freq = <200000000>;
+                                reg = <0x60014 0x14>;
+                        };
+                };
+        };
+        rwid-axi {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges;
+                ebi@50000000 {
+                        compatible = "simple-bus";
+                        #address-cells = <2>;
+                        #size-cells = <1>;
+                        ranges = <0 0 0x40000000 0x08000000
+                                  1 0 0x48000000 0x08000000
+                                  2 0 0x50000000 0x08000000
+                                  3 0 0x58000000 0x08000000>;
+                };
+                axi2pico@c0000000 {
+                        compatible = "picochip,axi2pico-pc3x3";
+                        reg = <0xc0000000 0x10000>;
+                        interrupt-parent = <&vic0>;
+                        interrupts = <13 14 15 16 17 18 19 20 21>;
+                };
+                otp@ffff8000 {
+                        compatible = "picochip,otp-pc3x3";
+                        reg = <0xffff8000 0x8000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts b/arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts
new file mode 100644
index 000000000000..1297414dd649
--- /dev/null
+++ b/arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts
@@ -0,0 +1,86 @@
+/*
+ *  Copyright (C) 2011 Picochip, Jamie Iles
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/dts-v1/;
+/include/ "picoxcell-pc3x2.dtsi"
+/ {
+        model = "Picochip PC7302 (PC3X2)";
+        compatible = "picochip,pc7302-pc3x2", "picochip,pc3x2";
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x08000000>;
+        };
+        chosen {
+                linux,stdout-path = &uart0;
+        };
+        clocks {
+                ref_clk: clock@1 {
+                        compatible = "fixed-clock";
+                        clock-outputs = "ref";
+                        clock-frequency = <20000000>;
+                };
+        };
+        rwid-axi {
+                ebi@50000000 {
+                        nand: gpio-nand@2,0 {
+                                compatible = "gpio-control-nand";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <2 0x0000 0x1000>;
+                                bus-clock = <&pclk>, "bus";
+                                gpio-control-nand,io-sync-reg =
+                                        <0x00000000 0x80220000>;
+                                gpios = <&banka 1 0     /* rdy */
+                                         &banka 2 0     /* nce */
+                                         &banka 3 0     /* ale */
+                                         &banka 4 0     /* cle */
+                                         0              /* nwp */>;
+                                boot@100000 {
+                                        label = "Boot";
+                                        reg = <0x100000 0x80000>;
+                                };
+                                redundant-boot@200000 {
+                                        label = "Redundant Boot";
+                                        reg = <0x200000 0x80000>;
+                                };
+                                boot-env@300000 {
+                                        label = "Boot Evironment";
+                                        reg = <0x300000 0x20000>;
+                                };
+                                redundant-boot-env@320000 {
+                                        label = "Redundant Boot Environment";
+                                        reg = <0x300000 0x20000>;
+                                };
+                                kernel@380000 {
+                                        label = "Kernel";
+                                        reg = <0x380000 0x800000>;
+                                };
+                                fs@b80000 {
+                                        label = "File System";
+                                        reg = <0xb80000 0xf480000>;
+                                };
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts b/arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts
new file mode 100644
index 000000000000..9e317a4f431c
--- /dev/null
+++ b/arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts
@@ -0,0 +1,92 @@
+/*
+ *  Copyright (C) 2011 Picochip, Jamie Iles
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/dts-v1/;
+/include/ "picoxcell-pc3x3.dtsi"
+/ {
+        model = "Picochip PC7302 (PC3X3)";
+        compatible = "picochip,pc7302-pc3x3", "picochip,pc3x3";
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x08000000>;
+        };
+        chosen {
+                linux,stdout-path = &uart0;
+        };
+        clocks {
+                ref_clk: clock@10 {
+                        compatible = "fixed-clock";
+                        clock-outputs = "ref";
+                        clock-frequency = <20000000>;
+                };
+                clkgate: clkgate@800a0048 {
+                        clock@4 {
+                                picochip,clk-no-disable;
+                        };
+                };
+        };
+        rwid-axi {
+                ebi@50000000 {
+                        nand: gpio-nand@2,0 {
+                                compatible = "gpio-control-nand";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <2 0x0000 0x1000>;
+                                bus-clock = <&ebi_clk>, "bus";
+                                gpio-control-nand,io-sync-reg =
+                                        <0x00000000 0x80220000>;
+                                gpios = <&banka 1 0     /* rdy */
+                                         &banka 2 0     /* nce */
+                                         &banka 3 0     /* ale */
+                                         &banka 4 0     /* cle */
+                                         0              /* nwp */>;
+                                boot@100000 {
+                                        label = "Boot";
+                                        reg = <0x100000 0x80000>;
+                                };
+                                redundant-boot@200000 {
+                                        label = "Redundant Boot";
+                                        reg = <0x200000 0x80000>;
+                                };
+                                boot-env@300000 {
+                                        label = "Boot Evironment";
+                                        reg = <0x300000 0x20000>;
+                                };
+                                redundant-boot-env@320000 {
+                                        label = "Redundant Boot Environment";
+                                        reg = <0x300000 0x20000>;
+                                };
+                                kernel@380000 {
+                                        label = "Kernel";
+                                        reg = <0x380000 0x800000>;
+                                };
+                                fs@b80000 {
+                                        label = "File System";
+                                        reg = <0xb80000 0xf480000>;
+                                };
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/prima2-cb.dts b/arch/arm/boot/dts/prima2-cb.dts
index 6fecc88065b2..34ae3a64ba25 100644
--- a/arch/arm/boot/dts/prima2-cb.dts
+++ b/arch/arm/boot/dts/prima2-cb.dts
@@ -39,9 +39,12 @@
                ranges = <0x40000000 0x40000000 0x80000000>;
                l2-cache-controller@80040000 {
-                        compatible = "arm,pl310-cache";
+                        compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache";
                        reg = <0x80040000 0x1000>;
                        interrupts = <59>;
+                        arm,tag-latency = <1 1 1>;
+                        arm,data-latency = <1 1 1>;
+                        arm,filter-ranges = <0 0x40000000>;
                };
                intc: interrupt-controller@80020000 {
@@ -67,6 +70,11 @@
                                compatible = "sirf,prima2-rstc";
                                reg = <0x88010000 0x1000>;
                        };
+                        rsc-controller@88020000 {
+                                compatible = "sirf,prima2-rsc";
+                                reg = <0x88020000 0x1000>;
+                        };
                };
                mem-iobg {
@@ -274,7 +282,7 @@
                        gpio: gpio-controller@b0120000 {
                                #gpio-cells = <2>;
                                #interrupt-cells = <2>;
-                                compatible = "sirf,prima2-gpio";
+                                compatible = "sirf,prima2-gpio-pinmux";
                                reg = <0xb0120000 0x10000>;
                                gpio-controller;
                                interrupt-controller;
@@ -358,7 +366,7 @@
                };
                rtc-iobg {
-                        compatible = "sirf,prima2-rtciobg", "simple-bus";
+                        compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        reg = <0x80030000 0x10000>;
diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts
index e5818668d091..0e225b86b652 100644
--- a/arch/arm/boot/dts/tegra-harmony.dts
+++ b/arch/arm/boot/dts/tegra-harmony.dts
@@ -66,5 +66,6 @@
                cd-gpios = <&gpio 58 0>; /* gpio PH2 */
                wp-gpios = <&gpio 59 0>; /* gpio PH3 */
                power-gpios = <&gpio 70 0>; /* gpio PI6 */
+                support-8bit;
        };
 };
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
index 64cedca6fc79..a72299b8e668 100644
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -25,4 +25,8 @@
                wp-gpios = <&gpio 57 0>; /* gpio PH1 */
                power-gpios = <&gpio 70 0>; /* gpio PI6 */
        };
+        sdhci@c8000600 {
+                support-8bit;
+        };
 };
diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts
new file mode 100644
index 000000000000..9b29a623aaf1
--- /dev/null
+++ b/arch/arm/boot/dts/tegra-ventana.dts
@@ -0,0 +1,32 @@
+/dts-v1/;
+/memreserve/ 0x1c000000 0x04000000;
+/include/ "tegra20.dtsi"
+/ {
+        model = "NVIDIA Tegra2 Ventana evaluation board";
+        compatible = "nvidia,ventana", "nvidia,tegra20";
+        chosen {
+                bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/ram rdinit=/sbin/init";
+        };
+        memory {
+                reg = < 0x00000000 0x40000000 >;
+        };
+        serial@70006300 {
+                clock-frequency = < 216000000 >;
+        };
+        sdhci@c8000400 {
+                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+                wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+                power-gpios = <&gpio 155 0>; /* gpio PT3 */
+        };
+        sdhci@c8000600 {
+                power-gpios = <&gpio 70 0>; /* gpio PI6 */
+                support-8bit;
+        };
+};
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 5727595cde61..65d7e6a333eb 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -77,6 +77,14 @@
                gpio-controller;
        };
+        pinmux: pinmux@70000000 {
+                compatible = "nvidia,tegra20-pinmux";
+                reg = < 0x70000014 0x10    /* Tri-state registers */
+                        0x70000080 0x20    /* Mux registers */
+                        0x700000a0 0x14    /* Pull-up/down registers */
+                        0x70000868 0xa8 >; /* Pad control registers */
+        };
        serial@70006000 {
                compatible = "nvidia,tegra20-uart";
                reg = <0x70006000 0x40>;
diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts
new file mode 100644
index 000000000000..d66e2c00ac35
--- /dev/null
+++ b/arch/arm/boot/dts/usb_a9g20.dts
@@ -0,0 +1,30 @@
+/*
+ * usb_a9g20.dts - Device Tree file for Caloa USB A9G20 board
+ *
+ *  Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "at91sam9g20.dtsi"
+/ {
+        model = "Calao USB A9G20";
+        compatible = "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9";
+        chosen {
+                bootargs = "mem=64M console=ttyS0,115200 mtdparts=atmel_nand:128k(at91bootstrap),256k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),4M(kernel),120M(rootfs),-(data) root=/dev/mtdblock5 rw rootfstype=ubifs";
+        };
+        memory@20000000 {
+                reg = <0x20000000 0x4000000>;
+        };
+        ahb {
+                apb {
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index 4b71766fb21d..74df9ca2be31 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -1,4 +1,5 @@
 config ARM_GIC
+        select IRQ_DOMAIN
        bool
 config ARM_VIC
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index a8fc6b237592..0e6ae470c94f 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -24,11 +24,17 @@
 */
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/module.h>
 #include <linux/list.h>
 #include <linux/smp.h>
 #include <linux/cpu_pm.h>
 #include <linux/cpumask.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/irqdomain.h>
 #include <linux/interrupt.h>
 #include <linux/percpu.h>
 #include <linux/slab.h>
@@ -75,8 +81,7 @@ static inline void __iomem *gic_cpu_base(struct irq_data *d)
 static inline unsigned int gic_irq(struct irq_data *d)
 {
-        struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
+        return d->hwirq;
-        return d->irq - gic_data->irq_offset;
 }
 /*
@@ -84,7 +89,7 @@ static inline unsigned int gic_irq(struct irq_data *d)
 */
 static void gic_mask_irq(struct irq_data *d)
 {
-        u32 mask = 1 << (d->irq % 32);
+        u32 mask = 1 << (gic_irq(d) % 32);
        raw_spin_lock(&irq_controller_lock);
        writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
@@ -95,7 +100,7 @@ static void gic_mask_irq(struct irq_data *d)
 static void gic_unmask_irq(struct irq_data *d)
 {
-        u32 mask = 1 << (d->irq % 32);
+        u32 mask = 1 << (gic_irq(d) % 32);
        raw_spin_lock(&irq_controller_lock);
        if (gic_arch_extn.irq_unmask)
@@ -176,7 +181,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
                            bool force)
 {
        void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
-        unsigned int shift = (d->irq % 4) * 8;
+        unsigned int shift = (gic_irq(d) % 4) * 8;
        unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
        u32 val, mask, bit;
@@ -227,7 +232,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
        if (gic_irq == 1023)
                goto out;
-        cascade_irq = gic_irq + chip_data->irq_offset;
+        cascade_irq = irq_domain_to_irq(&chip_data->domain, gic_irq);
        if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS))
                do_bad_IRQ(cascade_irq, desc);
        else
@@ -259,14 +264,14 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
        irq_set_chained_handler(irq, gic_handle_cascade_irq);
 }
-static void __init gic_dist_init(struct gic_chip_data *gic,
+static void __init gic_dist_init(struct gic_chip_data *gic)
-        unsigned int irq_start)
 {
-        unsigned int gic_irqs, irq_limit, i;
+        unsigned int i, irq;
        u32 cpumask;
+        unsigned int gic_irqs = gic->gic_irqs;
+        struct irq_domain *domain = &gic->domain;
        void __iomem *base = gic->dist_base;
        u32 cpu = 0;
-        u32 nrppis = 0, ppi_base = 0;
 #ifdef CONFIG_SMP
        cpu = cpu_logical_map(smp_processor_id());
@@ -279,34 +284,6 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
        writel_relaxed(0, base + GIC_DIST_CTRL);
        /*
-         * Find out how many interrupts are supported.
-         * The GIC only supports up to 1020 interrupt sources.
-         */
-        gic_irqs = readl_relaxed(base + GIC_DIST_CTR) & 0x1f;
-        gic_irqs = (gic_irqs + 1) * 32;
-        if (gic_irqs > 1020)
-                gic_irqs = 1020;
-        gic->gic_irqs = gic_irqs;
-        /*
-         * Nobody would be insane enough to use PPIs on a secondary
-         * GIC, right?
-         */
-        if (gic == &gic_data[0]) {
-                nrppis = (32 - irq_start) & 31;
-                /* The GIC only supports up to 16 PPIs. */
-                if (nrppis > 16)
-                        BUG();
-                ppi_base = gic->irq_offset + 32 - nrppis;
-        }
-        pr_info("Configuring GIC with %d sources (%d PPIs)\n",
-                gic_irqs, (gic == &gic_data[0]) ? nrppis : 0);
-        /*
         * Set all global interrupts to be level triggered, active low.
         */
        for (i = 32; i < gic_irqs; i += 16)
@@ -332,29 +309,20 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
                writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
        /*
-         * Limit number of interrupts registered to the platform maximum
-         */
-        irq_limit = gic->irq_offset + gic_irqs;
-        if (WARN_ON(irq_limit > NR_IRQS))
-                irq_limit = NR_IRQS;
-        /*
         * Setup the Linux IRQ subsystem.
         */
-        for (i = 0; i < nrppis; i++) {
+        irq_domain_for_each_irq(domain, i, irq) {
-                int ppi = i + ppi_base;
+                if (i < 32) {
+                        irq_set_percpu_devid(irq);
-                irq_set_percpu_devid(ppi);
+                        irq_set_chip_and_handler(irq, &gic_chip,
-                irq_set_chip_and_handler(ppi, &gic_chip,
+                                                 handle_percpu_devid_irq);
-                                         handle_percpu_devid_irq);
+                        set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
-                irq_set_chip_data(ppi, gic);
+                } else {
-                set_irq_flags(ppi, IRQF_VALID | IRQF_NOAUTOEN);
+                        irq_set_chip_and_handler(irq, &gic_chip,
-        }
+                                                 handle_fasteoi_irq);
+                        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-        for (i = irq_start + nrppis; i < irq_limit; i++) {
+                }
-                irq_set_chip_and_handler(i, &gic_chip, handle_fasteoi_irq);
+                irq_set_chip_data(irq, gic);
-                irq_set_chip_data(i, gic);
-                set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
        }
        writel_relaxed(1, base + GIC_DIST_CTRL);
@@ -566,23 +534,85 @@ static void __init gic_pm_init(struct gic_chip_data *gic)
 }
 #endif
-void __init gic_init(unsigned int gic_nr, unsigned int irq_start,
+#ifdef CONFIG_OF
+static int gic_irq_domain_dt_translate(struct irq_domain *d,
+                                       struct device_node *controller,
+                                       const u32 *intspec, unsigned int intsize,
+                                       unsigned long *out_hwirq, unsigned int *out_type)
+{
+        if (d->of_node != controller)
+                return -EINVAL;
+        if (intsize < 3)
+                return -EINVAL;
+        /* Get the interrupt number and add 16 to skip over SGIs */
+        *out_hwirq = intspec[1] + 16;
+        /* For SPIs, we need to add 16 more to get the GIC irq ID number */
+        if (!intspec[0])
+                *out_hwirq += 16;
+        *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
+        return 0;
+}
+#endif
+const struct irq_domain_ops gic_irq_domain_ops = {
+#ifdef CONFIG_OF
+        .dt_translate = gic_irq_domain_dt_translate,
+#endif
+};
+void __init gic_init(unsigned int gic_nr, int irq_start,
        void __iomem *dist_base, void __iomem *cpu_base)
 {
        struct gic_chip_data *gic;
+        struct irq_domain *domain;
+        int gic_irqs;
        BUG_ON(gic_nr >= MAX_GIC_NR);
        gic = &gic_data[gic_nr];
+        domain = &gic->domain;
        gic->dist_base = dist_base;
        gic->cpu_base = cpu_base;
-        gic->irq_offset = (irq_start - 1) & ~31;
-        if (gic_nr == 0)
+        /*
+         * For primary GICs, skip over SGIs.
+         * For secondary GICs, skip over PPIs, too.
+         */
+        if (gic_nr == 0) {
                gic_cpu_base_addr = cpu_base;
+                domain->hwirq_base = 16;
+                if (irq_start > 0)
+                        irq_start = (irq_start & ~31) + 16;
+        } else
+                domain->hwirq_base = 32;
+        /*
+         * Find out how many interrupts are supported.
+         * The GIC only supports up to 1020 interrupt sources.
+         */
+        gic_irqs = readl_relaxed(dist_base + GIC_DIST_CTR) & 0x1f;
+        gic_irqs = (gic_irqs + 1) * 32;
+        if (gic_irqs > 1020)
+                gic_irqs = 1020;
+        gic->gic_irqs = gic_irqs;
+        domain->nr_irq = gic_irqs - domain->hwirq_base;
+        domain->irq_base = irq_alloc_descs(irq_start, 16, domain->nr_irq,
+                                           numa_node_id());
+        if (IS_ERR_VALUE(domain->irq_base)) {
+                WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
+                     irq_start);
+                domain->irq_base = irq_start;
+        }
+        domain->priv = gic;
+        domain->ops = &gic_irq_domain_ops;
+        irq_domain_add(domain);
        gic_chip.flags |= gic_arch_extn.flags;
-        gic_dist_init(gic, irq_start);
+        gic_dist_init(gic);
        gic_cpu_init(gic);
        gic_pm_init(gic);
 }
@@ -614,3 +644,35 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
        writel_relaxed(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
 }
 #endif
+#ifdef CONFIG_OF
+static int gic_cnt __initdata = 0;
+int __init gic_of_init(struct device_node *node, struct device_node *parent)
+{
+        void __iomem *cpu_base;
+        void __iomem *dist_base;
+        int irq;
+        struct irq_domain *domain = &gic_data[gic_cnt].domain;
+        if (WARN_ON(!node))
+                return -ENODEV;
+        dist_base = of_iomap(node, 0);
+        WARN(!dist_base, "unable to map gic dist registers\n");
+        cpu_base = of_iomap(node, 1);
+        WARN(!cpu_base, "unable to map gic cpu registers\n");
+        domain->of_node = of_node_get(node);
+        gic_init(gic_cnt, -1, dist_base, cpu_base);
+        if (parent) {
+                irq = irq_of_parse_and_map(node, 0);
+                gic_cascade_irq(gic_cnt, irq);
+        }
+        gic_cnt++;
+        return 0;
+}
+#endif
diff --git a/arch/arm/configs/at91sam9g45_defconfig b/arch/arm/configs/at91sam9g45_defconfig
new file mode 100644
index 000000000000..c5876d244f4b
--- /dev/null
+++ b/arch/arm/configs/at91sam9g45_defconfig
@@ -0,0 +1,214 @@
+CONFIG_EXPERIMENTAL=y
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_AT91=y
+CONFIG_ARCH_AT91SAM9G45=y
+CONFIG_MACH_AT91SAM9M10G45EK=y
+CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+CONFIG_AT91_SLOW_CLOCK=y
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_LEDS=y
+CONFIG_LEDS_CPU=y
+CONFIG_UACCESS_WITH_MEMCPY=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="mem=128M console=ttyS0,115200 initrd=0x71100000,25165824 root=/dev/ram0 rw"
+CONFIG_AUTO_ZRELADDR=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+CONFIG_IPV6=y
+# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET6_XFRM_MODE_BEET is not set
+CONFIG_IPV6_SIT_6RD=y
+CONFIG_CFG80211=y
+CONFIG_LIB80211=y
+CONFIG_MAC80211=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_DATAFLASH=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_ATMEL=y
+CONFIG_MTD_UBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=4
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_MISC_DEVICES=y
+CONFIG_ATMEL_PWM=y
+CONFIG_ATMEL_TCLIB=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_NETDEVICES=y
+CONFIG_MII=y
+CONFIG_DAVICOM_PHY=y
+CONFIG_NET_ETHERNET=y
+CONFIG_MACB=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+CONFIG_LIBERTAS_THINFIRM=m
+CONFIG_LIBERTAS_THINFIRM_USB=m
+CONFIG_AT76C50X_USB=m
+CONFIG_USB_ZD1201=m
+CONFIG_RTL8187=m
+CONFIG_ATH_COMMON=m
+CONFIG_ATH9K=m
+CONFIG_CARL9170=m
+CONFIG_B43=m
+CONFIG_B43_PHY_N=y
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_USB=m
+CONFIG_LIBERTAS_SDIO=m
+CONFIG_LIBERTAS_SPI=m
+CONFIG_RT2X00=m
+CONFIG_RT2500USB=m
+CONFIG_RT73USB=m
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT53XX=y
+CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_RTL8192CU=m
+CONFIG_WL1251=m
+CONFIG_WL1251_SDIO=m
+CONFIG_WL12XX_MENU=m
+CONFIG_WL12XX=m
+CONFIG_WL12XX_SDIO=m
+CONFIG_ZD1211RW=m
+CONFIG_MWIFIEX=m
+CONFIG_MWIFIEX_SDIO=m
+CONFIG_INPUT_POLLDEV=m
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=480
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=272
+CONFIG_INPUT_JOYDEV=y
+CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_QT1070=m
+CONFIG_KEYBOARD_QT2160=m
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ATMEL_MXT=m
+CONFIG_TOUCHSCREEN_ATMEL_TSADCC=y
+# CONFIG_SERIO is not set
+CONFIG_LEGACY_PTY_COUNT=4
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_I2C=y
+CONFIG_I2C_GPIO=y
+CONFIG_SPI=y
+CONFIG_SPI_ATMEL=y
+# CONFIG_HWMON is not set
+# CONFIG_MFD_SUPPORT is not set
+CONFIG_FB=y
+CONFIG_FB_ATMEL=y
+CONFIG_FB_UDL=m
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_ATMEL_LCDC=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SEQUENCER=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_ARM is not set
+CONFIG_SND_ATMEL_AC97C=y
+# CONFIG_SND_SPI is not set
+CONFIG_SND_USB_AUDIO=m
+# CONFIG_USB_HID is not set
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_ACM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_ATMEL_USBA=m
+CONFIG_USB_ZERO=m
+CONFIG_USB_AUDIO=m
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_EEM=y
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_G_SERIAL=m
+CONFIG_USB_CDC_COMPOSITE=m
+CONFIG_USB_G_MULTI=m
+CONFIG_USB_G_MULTI_CDC=y
+CONFIG_MMC=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
+CONFIG_SDIO_UART=m
+CONFIG_MMC_ATMELMCI=y
+CONFIG_MMC_ATMELMCI_DMA=y
+CONFIG_LEDS_ATMEL_PWM=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_AT91RM9200=y
+CONFIG_DMADEVICES=y
+CONFIG_AT_HDMAC=y
+CONFIG_DMATEST=m
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT2_FS=y
+CONFIG_FANOTIFY=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_CRAMFS=m
+CONFIG_SQUASHFS=m
+CONFIG_SQUASHFS_EMBEDDED=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_STRIP_ASM_SYMS=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_USER=y
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_USER_API_HASH=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
+# CONFIG_CRYPTO_HW is not set
diff --git a/arch/arm/configs/exynos4_defconfig b/arch/arm/configs/exynos4_defconfig
index da53ff3b4d70..cd40bb56e568 100644
--- a/arch/arm/configs/exynos4_defconfig
+++ b/arch/arm/configs/exynos4_defconfig
@@ -11,6 +11,7 @@ CONFIG_MACH_SMDKV310=y
 CONFIG_MACH_ARMLEX4210=y
 CONFIG_MACH_UNIVERSAL_C210=y
 CONFIG_MACH_NURI=y
+CONFIG_MACH_ORIGEN=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_SMP=y
diff --git a/arch/arm/configs/mx27_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index 9ad4c656c9bd..11a4192197c8 100644
--- a/arch/arm/configs/mx27_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -3,9 +3,7 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_EXPERT=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
 # CONFIG_COMPAT_BRK is not set
 CONFIG_SLAB=y
 CONFIG_PROFILING=y
@@ -17,8 +15,12 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_MXC=y
-CONFIG_ARCH_MX2=y
+CONFIG_ARCH_IMX_V4_V5=y
-CONFIG_MACH_MX27=y
+CONFIG_ARCH_MX1ADS=y
+CONFIG_MACH_SCB9328=y
+CONFIG_MACH_MX21ADS=y
+CONFIG_MACH_MX25_3DS=y
+CONFIG_MACH_EUKREA_CPUIMX25=y
 CONFIG_MACH_MX27ADS=y
 CONFIG_MACH_PCM038=y
 CONFIG_MACH_CPUIMX27=y
@@ -29,6 +31,7 @@ CONFIG_MACH_IMX27_VISSTRIM_M10=y
 CONFIG_MACH_IMX27LITE=y
 CONFIG_MACH_PCA100=y
 CONFIG_MACH_MXT_TD60=y
+CONFIG_MACH_IMX27IPCAM=y
 CONFIG_MXC_IRQ_PRIOR=y
 CONFIG_MXC_PWM=y
 CONFIG_NO_HZ=y
@@ -39,7 +42,6 @@ CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_FPE_NWFPE=y
 CONFIG_FPE_NWFPE_XP=y
-CONFIG_PM=y
 CONFIG_PM_DEBUG=y
 CONFIG_NET=y
 CONFIG_PACKET=y
@@ -55,8 +57,9 @@ CONFIG_IP_PNP_DHCP=y
 # CONFIG_INET_DIAG is not set
 # CONFIG_IPV6 is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
@@ -69,12 +72,15 @@ CONFIG_MTD_CFI_GEOMETRY=y
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_PHYSMAP=y
 CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_MXC=y
 CONFIG_MTD_UBI=y
+CONFIG_MISC_DEVICES=y
 CONFIG_EEPROM_AT24=y
+CONFIG_EEPROM_AT25=y
 CONFIG_NETDEVICES=y
 CONFIG_NET_ETHERNET=y
-CONFIG_FEC=y
+CONFIG_SMC91X=y
+CONFIG_DM9000=y
+CONFIG_SMC911X=y
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
 # CONFIG_INPUT_MOUSEDEV is not set
@@ -84,10 +90,10 @@ CONFIG_INPUT_EVDEV=y
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_ADS7846=m
 # CONFIG_SERIO is not set
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_8250=m
 CONFIG_SERIAL_IMX=y
 CONFIG_SERIAL_IMX_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
@@ -98,19 +104,56 @@ CONFIG_W1=y
 CONFIG_W1_MASTER_MXC=y
 CONFIG_W1_SLAVE_THERM=y
 # CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_IMX2_WDT=y
+CONFIG_MFD_MC13XXX=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_MC13783=y
+CONFIG_REGULATOR_MC13892=y
 CONFIG_FB=y
 CONFIG_FB_IMX=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_PWM=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FONTS=y
 CONFIG_FONT_8x8=y
-# CONFIG_HID_SUPPORT is not set
+CONFIG_LOGO=y
-CONFIG_USB=m
+CONFIG_SOUND=y
+CONFIG_SND=y
+# CONFIG_SND_ARM is not set
+# CONFIG_SND_SPI is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_IMX_SOC=y
+CONFIG_SND_SOC_MX27VIS_AIC32X4=y
+CONFIG_SND_SOC_PHYCORE_AC97=y
+CONFIG_SND_SOC_EUKREA_TLV320=y
+CONFIG_USB_HID=m
+CONFIG_USB=y
 # CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_MXC=y
 CONFIG_USB_ULPI=y
 CONFIG_MMC=y
 CONFIG_MMC_MXC=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_MC13783=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_PCF8563=y
+CONFIG_RTC_DRV_IMXDI=y
+CONFIG_RTC_MXC=y
+CONFIG_DMADEVICES=y
+CONFIG_IMX_SDMA=y
+CONFIG_IMX_DMA=y
+# CONFIG_IOMMU_SUPPORT is not set
 # CONFIG_DNOTIFY is not set
 # CONFIG_PROC_PAGE_MONITOR is not set
 CONFIG_TMPFS=y
@@ -119,12 +162,9 @@ CONFIG_UBIFS_FS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
-CONFIG_NLS=y
 CONFIG_NLS_CODEPAGE_437=m
 CONFIG_NLS_CODEPAGE_850=m
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_15=m
-CONFIG_DEBUG_FS=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/arm/configs/mx1_defconfig b/arch/arm/configs/mx1_defconfig
deleted file mode 100644
index c9436d0bf593..000000000000
--- a/arch/arm/configs/mx1_defconfig
+++ /dev/null
@@ -1,91 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_EXPERT=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_MXC=y
-CONFIG_ARCH_MX1=y
-CONFIG_ARCH_MX1ADS=y
-CONFIG_MACH_SCB9328=y
-CONFIG_MACH_APF9328=y
-CONFIG_MXC_IRQ_PRIOR=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw ip=off"
-CONFIG_PM=y
-CONFIG_PM_DEBUG=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_FW_LOADER=m
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_PHYSMAP=y
-# CONFIG_BLK_DEV is not set
-# CONFIG_MISC_DEVICES is not set
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-CONFIG_SMSC_PHY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_DM9000=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_IMX=y
-CONFIG_SERIAL_IMX_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_IMX=y
-CONFIG_W1=y
-CONFIG_W1_MASTER_MXC=y
-CONFIG_W1_SLAVE_THERM=y
-# CONFIG_HWMON is not set
-CONFIG_FB=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_IMX=y
-CONFIG_USB_ETH=m
-CONFIG_MMC=y
-CONFIG_MMC_MXC=y
-# CONFIG_DNOTIFY is not set
-CONFIG_INOTIFY=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-# CONFIG_ENABLE_MUST_CHECK is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/arm/configs/mx21_defconfig b/arch/arm/configs/mx21_defconfig
deleted file mode 100644
index 411f88dd4402..000000000000
--- a/arch/arm/configs/mx21_defconfig
+++ /dev/null
@@ -1,97 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_MXC=y
-CONFIG_ARCH_MX2=y
-CONFIG_MACH_MX21ADS=y
-CONFIG_MXC_PWM=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_NET=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_DEBUG=y
-CONFIG_MTD_DEBUG_VERBOSE=3
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_MXC=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-# CONFIG_SERIO is not set
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=1
-CONFIG_SERIAL_IMX=y
-CONFIG_SERIAL_IMX_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_IMX=y
-CONFIG_SPI=y
-# CONFIG_HWMON is not set
-CONFIG_FB=y
-CONFIG_FB_IMX=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_LOGO=y
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_MMC_MXC=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/arm/configs/mx3_defconfig b/arch/arm/configs/mx3_defconfig
index 7c4b30b34952..cb0717fbb03d 100644
--- a/arch/arm/configs/mx3_defconfig
+++ b/arch/arm/configs/mx3_defconfig
@@ -3,7 +3,6 @@ CONFIG_SYSVIPC=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_EXPERT=y
 CONFIG_SLAB=y
 CONFIG_MODULES=y
@@ -13,20 +12,21 @@ CONFIG_MODVERSIONS=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_ARCH_MXC=y
 CONFIG_MACH_MX31ADS_WM1133_EV1=y
+CONFIG_MACH_MX31LILLY=y
+CONFIG_MACH_MX31LITE=y
 CONFIG_MACH_PCM037=y
 CONFIG_MACH_PCM037_EET=y
-CONFIG_MACH_MX31LITE=y
 CONFIG_MACH_MX31_3DS=y
 CONFIG_MACH_MX31MOBOARD=y
-CONFIG_MACH_MX31LILLY=y
 CONFIG_MACH_QONG=y
-CONFIG_MACH_PCM043=y
 CONFIG_MACH_ARMADILLO5X0=y
-CONFIG_MACH_MX35_3DS=y
 CONFIG_MACH_KZM_ARM11_01=y
+CONFIG_MACH_PCM043=y
+CONFIG_MACH_MX35_3DS=y
 CONFIG_MACH_EUKREA_CPUIMX35=y
 CONFIG_MXC_IRQ_PRIOR=y
 CONFIG_MXC_PWM=y
+CONFIG_ARM_ERRATA_411920=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT=y
@@ -35,7 +35,6 @@ CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw ip=off"
 CONFIG_VFP=y
-CONFIG_PM=y
 CONFIG_PM_DEBUG=y
 CONFIG_NET=y
 CONFIG_PACKET=y
@@ -52,7 +51,6 @@ CONFIG_IP_PNP_DHCP=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_FW_LOADER=m
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
@@ -62,24 +60,27 @@ CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_MXC=y
 CONFIG_MTD_UBI=y
 # CONFIG_BLK_DEV is not set
+CONFIG_MISC_DEVICES=y
 CONFIG_EEPROM_AT24=y
 CONFIG_NETDEVICES=y
 CONFIG_SMSC_PHY=y
 CONFIG_NET_ETHERNET=y
 CONFIG_SMSC911X=y
 CONFIG_DNET=y
-CONFIG_FEC=y
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
-# CONFIG_INPUT is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_IMX=y
+# CONFIG_INPUT_MOUSE is not set
 # CONFIG_SERIO is not set
 # CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_8250=m
 CONFIG_SERIAL_8250_EXTENDED=y
 CONFIG_SERIAL_8250_SHARE_IRQ=y
 CONFIG_SERIAL_IMX=y
 CONFIG_SERIAL_IMX_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
@@ -89,12 +90,15 @@ CONFIG_W1=y
 CONFIG_W1_MASTER_MXC=y
 CONFIG_W1_SLAVE_THERM=y
 # CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_IMX2_WDT=y
 CONFIG_MFD_WM8350_I2C=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_WM8350=y
 CONFIG_MEDIA_SUPPORT=y
 CONFIG_VIDEO_DEV=y
-# CONFIG_VIDEO_ALLOW_V4L1 is not set
+# CONFIG_RC_CORE is not set
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
 CONFIG_SOC_CAMERA=y
 CONFIG_SOC_CAMERA_MT9M001=y
 CONFIG_SOC_CAMERA_MT9M111=y
@@ -105,9 +109,26 @@ CONFIG_SOC_CAMERA_OV772X=y
 CONFIG_VIDEO_MX3=y
 # CONFIG_RADIO_ADAPTERS is not set
 CONFIG_FB=y
-# CONFIG_USB_SUPPORT is not set
+CONFIG_SOUND=y
+CONFIG_SND=y
+# CONFIG_SND_ARM is not set
+# CONFIG_SND_SPI is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_IMX_SOC=y
+CONFIG_SND_MXC_SOC_WM1133_EV1=y
+CONFIG_SND_SOC_PHYCORE_AC97=y
+CONFIG_SND_SOC_EUKREA_TLV320=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_MXC=y
+CONFIG_USB_GADGET=m
+CONFIG_USB_FSL_USB2=m
+CONFIG_USB_G_SERIAL=m
+CONFIG_USB_ULPI=y
 CONFIG_MMC=y
 CONFIG_MMC_MXC=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_MXC=y
 CONFIG_DMADEVICES=y
 # CONFIG_DNOTIFY is not set
 CONFIG_TMPFS=y
@@ -119,6 +140,5 @@ CONFIG_NFS_V4=y
 CONFIG_ROOT_NFS=y
 # CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/arm/configs/mx51_defconfig b/arch/arm/configs/mx5_defconfig
index 88c5802a2351..d0d8dfece37e 100644
--- a/arch/arm/configs/mx51_defconfig
+++ b/arch/arm/configs/mx5_defconfig
@@ -1,5 +1,6 @@
 CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_KERNEL_LZO=y
 CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=18
 CONFIG_RELAY=y
@@ -13,21 +14,29 @@ CONFIG_MODULE_SRCVERSION_ALL=y
 # CONFIG_LBDAF is not set
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_ARCH_MXC=y
-CONFIG_ARCH_MX51=y
+CONFIG_ARCH_MX5=y
 CONFIG_MACH_MX51_BABBAGE=y
 CONFIG_MACH_MX51_3DS=y
 CONFIG_MACH_EUKREA_CPUIMX51=y
+CONFIG_MACH_EUKREA_CPUIMX51SD=y
+CONFIG_MACH_MX51_EFIKAMX=y
+CONFIG_MACH_MX51_EFIKASB=y
+CONFIG_MACH_MX53_EVK=y
+CONFIG_MACH_MX53_SMD=y
+CONFIG_MACH_MX53_LOCO=y
+CONFIG_MACH_MX53_ARD=y
+CONFIG_MXC_PWM=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
+CONFIG_VMSPLIT_2G=y
 CONFIG_PREEMPT_VOLUNTARY=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
 CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/nfs nfsroot=192.168.0.101:/shared/nfs ip=dhcp"
+CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
 CONFIG_VFP=y
 CONFIG_NEON=y
 CONFIG_BINFMT_MISC=m
-CONFIG_PM=y
 CONFIG_PM_DEBUG=y
 CONFIG_PM_TEST_SUSPEND=y
 CONFIG_NET=y
@@ -42,13 +51,13 @@ CONFIG_IP_PNP_DHCP=y
 # CONFIG_INET_LRO is not set
 # CONFIG_IPV6 is not set
 # CONFIG_WIRELESS is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_STANDALONE is not set
 CONFIG_CONNECTOR=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=65536
-# CONFIG_MISC_DEVICES is not set
-CONFIG_SCSI=y
 # CONFIG_SCSI_PROC_FS is not set
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
@@ -56,8 +65,10 @@ CONFIG_SCSI_CONSTANTS=y
 CONFIG_SCSI_LOGGING=y
 CONFIG_SCSI_SCAN_ASYNC=y
 # CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_ATA=m
+CONFIG_ATA=y
+CONFIG_PATA_IMX=y
 CONFIG_NETDEVICES=y
+CONFIG_MII=m
 CONFIG_MARVELL_PHY=y
 CONFIG_DAVICOM_PHY=y
 CONFIG_QSEMI_PHY=y
@@ -71,49 +82,57 @@ CONFIG_REALTEK_PHY=y
 CONFIG_NATIONAL_PHY=y
 CONFIG_STE10XP=y
 CONFIG_LSI_ET1011C_PHY=y
-CONFIG_MDIO_BITBANG=y
+CONFIG_MICREL_PHY=y
-CONFIG_MDIO_GPIO=y
 CONFIG_NET_ETHERNET=y
-CONFIG_MII=m
-CONFIG_FEC=y
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
 # CONFIG_WLAN is not set
-CONFIG_INPUT_FF_MEMLESS=m
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 CONFIG_INPUT_EVDEV=y
-CONFIG_KEYBOARD_GPIO=y
 CONFIG_INPUT_EVBUG=m
+CONFIG_KEYBOARD_GPIO=y
 CONFIG_MOUSE_PS2=m
 CONFIG_MOUSE_PS2_ELANTECH=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_MMA8450=y
 CONFIG_SERIO_SERPORT=m
 CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_LEGACY_PTYS is not set
 # CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_IMX=y
 CONFIG_SERIAL_IMX_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
 CONFIG_HW_RANDOM=y
 CONFIG_I2C=y
 # CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_CHARDEV=y
 # CONFIG_I2C_HELPER_AUTO is not set
 CONFIG_I2C_ALGOBIT=m
 CONFIG_I2C_ALGOPCF=m
 CONFIG_I2C_ALGOPCA=m
+CONFIG_I2C_IMX=y
+CONFIG_SPI=y
+CONFIG_SPI_IMX=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
-# CONFIG_HID_SUPPORT is not set
+CONFIG_WATCHDOG=y
+CONFIG_IMX2_WDT=y
+CONFIG_MFD_MC13XXX=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_MC13892=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_MXC=y
 CONFIG_USB_STORAGE=y
 CONFIG_MMC=y
 CONFIG_MMC_BLOCK=m
-CONFIG_MMC_SDHCI=m
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_ESDHC_IMX=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+CONFIG_RTC_MXC=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
@@ -127,7 +146,6 @@ CONFIG_EXT4_FS_SECURITY=y
 CONFIG_QUOTA=y
 CONFIG_QUOTA_NETLINK_INTERFACE=y
 # CONFIG_PRINT_QUOTA_WARNING is not set
-CONFIG_AUTOFS_FS=y
 CONFIG_AUTOFS4_FS=y
 CONFIG_FUSE_FS=y
 CONFIG_ISO9660_FS=m
@@ -151,17 +169,13 @@ CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_UTF8=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_FTRACE is not set
 # CONFIG_ARM_UNWIND is not set
-CONFIG_DEBUG_LL=y
-CONFIG_EARLY_PRINTK=y
 CONFIG_SECURITYFS=y
-CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DEFLATE=m
-CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_LZO=m
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 # CONFIG_CRYPTO_HW is not set
 CONFIG_CRC_CCITT=m
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index db2cb7d180dc..6ee781bf6bf1 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -26,6 +26,7 @@ CONFIG_MACH_MX23EVK=y
 CONFIG_MACH_MX28EVK=y
 CONFIG_MACH_STMP378X_DEVB=y
 CONFIG_MACH_TX28=y
+CONFIG_MACH_M28EVK=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 8845f1c9925d..195729760aeb 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -25,6 +25,7 @@ CONFIG_MACH_KAEN=y
 CONFIG_MACH_PAZ00=y
 CONFIG_MACH_TRIMSLICE=y
 CONFIG_MACH_WARIO=y
+CONFIG_MACH_VENTANA=y
 CONFIG_TEGRA_DEBUG_UARTD=y
 CONFIG_ARM_ERRATA_742230=y
 CONFIG_NO_HZ=y
@@ -38,7 +39,6 @@ CONFIG_HIGHMEM=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_VFP=y
-CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -65,6 +65,7 @@ CONFIG_IPV6_TUNNEL=y
 CONFIG_IPV6_MULTIPLE_TABLES=y
 # CONFIG_WIRELESS is not set
 # CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_MISC_DEVICES=y
 CONFIG_AD525X_DPOT=y
@@ -72,34 +73,61 @@ CONFIG_AD525X_DPOT_I2C=y
 CONFIG_ICS932S401=y
 CONFIG_APDS9802ALS=y
 CONFIG_ISL29003=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+# CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=y
+CONFIG_NET_ETHERNET=y
 CONFIG_R8169=y
 # CONFIG_NETDEV_10000 is not set
 # CONFIG_WLAN is not set
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_SMSC75XX=y
+CONFIG_USB_NET_SMSC95XX=y
 # CONFIG_INPUT is not set
 # CONFIG_SERIO is not set
 # CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
 # CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
 # CONFIG_I2C_COMPAT is not set
 # CONFIG_I2C_HELPER_AUTO is not set
 CONFIG_I2C_TEGRA=y
+CONFIG_SPI=y
+CONFIG_SPI_TEGRA=y
 CONFIG_SENSORS_LM90=y
 CONFIG_MFD_TPS6586X=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_TPS6586X=y
-# CONFIG_USB_SUPPORT is not set
+CONFIG_SOUND=y
+CONFIG_SND=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_PCI is not set
+# CONFIG_SND_ARM is not set
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_USB is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_TEGRA=y
+CONFIG_SND_SOC_TEGRA_WM8903=y
+CONFIG_SND_SOC_TEGRA_TRIMSLICE=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_STORAGE=y
 CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_TEGRA=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_TEGRA=y
 CONFIG_STAGING=y
-# CONFIG_STAGING_EXCLUDE_BUILD is not set
 CONFIG_IIO=y
 CONFIG_SENSORS_ISL29018=y
 CONFIG_SENSORS_AK8975=y
@@ -123,18 +151,15 @@ CONFIG_NLS_ISO8859_1=y
 CONFIG_PRINTK_TIME=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_SCHEDSTATS=y
 CONFIG_TIMER_STATS=y
 CONFIG_DEBUG_SLAB=y
 # CONFIG_DEBUG_PREEMPT is not set
 CONFIG_DEBUG_MUTEXES=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
 CONFIG_DEBUG_INFO=y
 CONFIG_DEBUG_VM=y
 CONFIG_DEBUG_SG=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 CONFIG_DEBUG_LL=y
 CONFIG_EARLY_PRINTK=y
 CONFIG_CRYPTO_ECB=y
diff --git a/arch/arm/include/asm/device.h b/arch/arm/include/asm/device.h
index 6615f03f56a5..7aa368003b05 100644
--- a/arch/arm/include/asm/device.h
+++ b/arch/arm/include/asm/device.h
@@ -15,7 +15,12 @@ struct dev_archdata {
 #endif
 };
+struct omap_device;
 struct pdev_archdata {
+#ifdef CONFIG_ARCH_OMAP
+        struct omap_device *od;
+#endif
 };
 #endif
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 434edccdf7f3..1db1143a9483 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -102,7 +102,14 @@
 #ifndef __ASSEMBLY__
 extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask);
+#if defined(CONFIG_CACHE_L2X0) && defined(CONFIG_OF)
 extern int l2x0_of_init(__u32 aux_val, __u32 aux_mask);
+#else
+static inline int l2x0_of_init(__u32 aux_val, __u32 aux_mask)
+{
+        return -ENODEV;
+}
+#endif
 struct l2x0_regs {
        unsigned long phy_base;
@@ -121,6 +128,6 @@ struct l2x0_regs {
 extern struct l2x0_regs l2x0_saved_regs;
-#endif
+#endif /* __ASSEMBLY__ */
 #endif
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
index 14867e12f205..3e91f22046f5 100644
--- a/arch/arm/include/asm/hardware/gic.h
+++ b/arch/arm/include/asm/hardware/gic.h
@@ -33,16 +33,19 @@
 #define GIC_DIST_SOFTINT                0xf00
 #ifndef __ASSEMBLY__
+#include <linux/irqdomain.h>
+struct device_node;
 extern void __iomem *gic_cpu_base_addr;
 extern struct irq_chip gic_arch_extn;
-void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *);
+void gic_init(unsigned int, int, void __iomem *, void __iomem *);
+int gic_of_init(struct device_node *node, struct device_node *parent);
 void gic_secondary_init(unsigned int);
 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
 void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
 struct gic_chip_data {
-        unsigned int irq_offset;
        void __iomem *dist_base;
        void __iomem *cpu_base;
 #ifdef CONFIG_CPU_PM
@@ -52,6 +55,9 @@ struct gic_chip_data {
        u32 __percpu *saved_ppi_enable;
        u32 __percpu *saved_ppi_conf;
 #endif
+#ifdef CONFIG_IRQ_DOMAIN
+        struct irq_domain domain;
+#endif
        unsigned int gic_irqs;
 };
 #endif
diff --git a/arch/arm/include/asm/hardware/it8152.h b/arch/arm/include/asm/hardware/it8152.h
index b3fea38d55c6..43cab498bc27 100644
--- a/arch/arm/include/asm/hardware/it8152.h
+++ b/arch/arm/include/asm/hardware/it8152.h
@@ -9,7 +9,7 @@
 #ifndef __ASM_HARDWARE_IT8152_H
 #define __ASM_HARDWARE_IT8152_H
-extern unsigned long it8152_base_address;
+extern void __iomem *it8152_base_address;
 #define IT8152_IO_BASE                  (it8152_base_address + 0x03e00000)
 #define IT8152_CFGREG_BASE              (it8152_base_address + 0x03f00000)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 22484670e7ba..a6b7991d7fe8 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -182,6 +182,11 @@ config MACH_ECO920
        help
          Select this if you are using the eco920 board
+config MACH_RSI_EWS
+        bool "RSI Embedded Webserver"
+        depends on ARCH_AT91RM9200
+        help
+          Select this if you are using RSIs EWS board.
 endif
 # ----------------------------------------------------------
@@ -381,6 +386,14 @@ config MACH_GSIA18S
          This enables support for the GS_IA18_S board
          produced by GeoSIG Ltd company. This is an internet accelerograph.
          <http://www.geosig.com>
+config MACH_USB_A9G20
+        bool "CALAO USB-A9G20"
+        depends on ARCH_AT91SAM9G20
+        help
+          Select this if you are using a Calao Systems USB-A9G20.
+          <http://www.calao-systems.com>
 endif
 if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20)
@@ -442,6 +455,17 @@ endif
 # ----------------------------------------------------------
+comment "Generic Board Type"
+config MACH_AT91SAM_DT
+        bool "Atmel AT91SAM Evaluation Kits with device-tree support"
+        select USE_OF
+        help
+          Select this if you want to experiment device-tree with
+          an Atmel Evaluation Kit.
+# ----------------------------------------------------------
 comment "AT91 Board Options"
 config MTD_AT91_DATAFLASH_CARD
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index bf57e8b1c9d0..242174f9f355 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -36,12 +36,13 @@ obj-$(CONFIG_MACH_ECBAT91)	+= board-ecbat91.o
 obj-$(CONFIG_MACH_YL9200)       += board-yl-9200.o
 obj-$(CONFIG_MACH_CPUAT91)      += board-cpuat91.o
 obj-$(CONFIG_MACH_ECO920)       += board-eco920.o
+obj-$(CONFIG_MACH_RSI_EWS)      += board-rsi-ews.o
 # AT91SAM9260 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
 obj-$(CONFIG_MACH_CAM60)        += board-cam60.o
 obj-$(CONFIG_MACH_SAM9_L9260)   += board-sam9-l9260.o
-obj-$(CONFIG_MACH_USB_A9260)    += board-usb-a9260.o
+obj-$(CONFIG_MACH_USB_A9260)    += board-usb-a926x.o
 obj-$(CONFIG_MACH_QIL_A9260)    += board-qil-a9260.o
 obj-$(CONFIG_MACH_AFEB9260)     += board-afeb-9260v1.o
 obj-$(CONFIG_MACH_CPU9260)      += board-cpu9krea.o
@@ -53,7 +54,7 @@ obj-$(CONFIG_MACH_AT91SAM9G10EK) += board-sam9261ek.o
 # AT91SAM9263 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o
-obj-$(CONFIG_MACH_USB_A9263)    += board-usb-a9263.o
+obj-$(CONFIG_MACH_USB_A9263)    += board-usb-a926x.o
 obj-$(CONFIG_MACH_NEOCORE926)   += board-neocore926.o
 # AT91SAM9RL board-specific support
@@ -67,6 +68,7 @@ obj-$(CONFIG_MACH_STAMP9G20)	+= board-stamp9g20.o
 obj-$(CONFIG_MACH_PORTUXG20)    += board-stamp9g20.o
 obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o board-stamp9g20.o
 obj-$(CONFIG_MACH_GSIA18S)      += board-gsia18s.o board-stamp9g20.o
+obj-$(CONFIG_MACH_USB_A9G20)    += board-usb-a926x.o
 # AT91SAM9260/AT91SAM9G20 board-specific support
 obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
@@ -74,6 +76,9 @@ obj-$(CONFIG_MACH_SNAPPER_9260)	+= board-snapper9260.o
 # AT91SAM9G45 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
+# AT91SAM board with device-tree
+obj-$(CONFIG_MACH_AT91SAM_DT) += board-dt.o
 # AT91CAP9 board-specific support
 obj-$(CONFIG_MACH_AT91CAP9ADK)  += board-cap9adk.o
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
index 9ab5a3e5f4f1..8ddafadfdc7d 100644
--- a/arch/arm/mach-at91/Makefile.boot
+++ b/arch/arm/mach-at91/Makefile.boot
@@ -16,3 +16,5 @@ else
 params_phys-y   := 0x20000100
 initrd_phys-y   := 0x20410000
 endif
+dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb usb_a9g20.dtb
diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c
index bfc684441ef8..ecdd54dd68c6 100644
--- a/arch/arm/mach-at91/at91cap9.c
+++ b/arch/arm/mach-at91/at91cap9.c
@@ -219,6 +219,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
        CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
        CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
+        /* fake hclk clock */
+        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
 };
 static struct clk_lookup usart_clocks_lookups[] = {
diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c
index f87f5040e78e..a4401d6b5b07 100644
--- a/arch/arm/mach-at91/at91cap9_devices.c
+++ b/arch/arm/mach-at91/at91cap9_devices.c
@@ -80,6 +80,12 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data)
                        at91_set_gpio_output(data->vbus_pin[i], 0);
        }
+        /* Enable overcurrent notification */
+        for (i = 0; i < data->ports; i++) {
+                if (data->overcurrent_pin[i])
+                        at91_set_gpio_input(data->overcurrent_pin[i], 1);
+        }
        usbh_data = *data;
        platform_device_register(&at91_usbh_device);
 }
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index f73302dbc6a5..713d3bdbd284 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -193,6 +193,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
        CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
        CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
+        /* fake hclk clock */
+        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
 };
 static struct clk_lookup usart_clocks_lookups[] = {
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 978be950035a..01d8bbd1468b 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -60,9 +60,17 @@ static struct platform_device at91rm9200_usbh_device = {
 void __init at91_add_device_usbh(struct at91_usbh_data *data)
 {
+        int i;
        if (!data)
                return;
+        /* Enable overcurrent notification */
+        for (i = 0; i < data->ports; i++) {
+                if (data->overcurrent_pin[i])
+                        at91_set_gpio_input(data->overcurrent_pin[i], 1);
+        }
        usbh_data = *data;
        platform_device_register(&at91rm9200_usbh_device);
 }
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index cb397be14448..b84a9f642f59 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -199,6 +199,16 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("t4_clk", "atmel_tcb.1", &tc4_clk),
        CLKDEV_CON_DEV_ID("t5_clk", "atmel_tcb.1", &tc5_clk),
        CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk),
+        /* more usart lookup table for DT entries */
+        CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
+        CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
+        CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk),
+        CLKDEV_CON_DEV_ID("usart", "fffb8000.serial", &usart2_clk),
+        CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
+        CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
+        CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
+        /* fake hclk clock */
+        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
 };
 static struct clk_lookup usart_clocks_lookups[] = {
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 3c2b580b9d75..24b6f8c0440d 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -61,9 +61,17 @@ static struct platform_device at91_usbh_device = {
 void __init at91_add_device_usbh(struct at91_usbh_data *data)
 {
+        int i;
        if (!data)
                return;
+        /* Enable overcurrent notification */
+        for (i = 0; i < data->ports; i++) {
+                if (data->overcurrent_pin[i])
+                        at91_set_gpio_input(data->overcurrent_pin[i], 1);
+        }
        usbh_data = *data;
        platform_device_register(&at91_usbh_device);
 }
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 6c8e3b5f669f..658a5185abfd 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -129,6 +129,20 @@ static struct clk lcdc_clk = {
        .type           = CLK_TYPE_PERIPHERAL,
 };
+/* HClocks */
+static struct clk hck0 = {
+        .name           = "hck0",
+        .pmc_mask       = AT91_PMC_HCK0,
+        .type           = CLK_TYPE_SYSTEM,
+        .id             = 0,
+};
+static struct clk hck1 = {
+        .name           = "hck1",
+        .pmc_mask       = AT91_PMC_HCK1,
+        .type           = CLK_TYPE_SYSTEM,
+        .id             = 1,
+};
 static struct clk *periph_clocks[] __initdata = {
        &pioA_clk,
        &pioB_clk,
@@ -161,6 +175,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
        CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
        CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
+        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0),
 };
 static struct clk_lookup usart_clocks_lookups[] = {
@@ -199,20 +214,6 @@ static struct clk pck3 = {
        .id             = 3,
 };
-/* HClocks */
-static struct clk hck0 = {
-        .name           = "hck0",
-        .pmc_mask       = AT91_PMC_HCK0,
-        .type           = CLK_TYPE_SYSTEM,
-        .id             = 0,
-};
-static struct clk hck1 = {
-        .name           = "hck1",
-        .pmc_mask       = AT91_PMC_HCK1,
-        .type           = CLK_TYPE_SYSTEM,
-        .id             = 1,
-};
 static void __init at91sam9261_register_clocks(void)
 {
        int i;
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 4e647b653339..3b70b3897d95 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -64,9 +64,17 @@ static struct platform_device at91sam9261_usbh_device = {
 void __init at91_add_device_usbh(struct at91_usbh_data *data)
 {
+        int i;
        if (!data)
                return;
+        /* Enable overcurrent notification */
+        for (i = 0; i < data->ports; i++) {
+                if (data->overcurrent_pin[i])
+                        at91_set_gpio_input(data->overcurrent_pin[i], 1);
+        }
        usbh_data = *data;
        platform_device_register(&at91sam9261_usbh_device);
 }
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 044f3c927e64..f83fbb0ee0c5 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -189,6 +189,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
+        /* fake hclk clock */
+        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
 };
 static struct clk_lookup usart_clocks_lookups[] = {
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index dd7662bc395f..3faa1fde9ad9 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -74,6 +74,12 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data)
                        at91_set_gpio_output(data->vbus_pin[i], 0);
        }
+        /* Enable overcurrent notification */
+        for (i = 0; i < data->ports; i++) {
+                if (data->overcurrent_pin[i])
+                        at91_set_gpio_input(data->overcurrent_pin[i], 1);
+        }
        usbh_data = *data;
        platform_device_register(&at91_usbh_device);
 }
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 1532b508c814..318b0407ea04 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -54,6 +54,11 @@ static struct clk pioDE_clk = {
        .pmc_mask       = 1 << AT91SAM9G45_ID_PIODE,
        .type           = CLK_TYPE_PERIPHERAL,
 };
+static struct clk trng_clk = {
+        .name           = "trng_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_TRNG,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
 static struct clk usart0_clk = {
        .name           = "usart0_clk",
        .pmc_mask       = 1 << AT91SAM9G45_ID_US0,
@@ -177,6 +182,7 @@ static struct clk *periph_clocks[] __initdata = {
        &pioB_clk,
        &pioC_clk,
        &pioDE_clk,
+        &trng_clk,
        &usart0_clk,
        &usart1_clk,
        &usart2_clk,
@@ -216,6 +222,15 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
        CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
        CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
+        CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
+        /* more usart lookup table for DT entries */
+        CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
+        CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
+        CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
+        CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
+        CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
+        /* fake hclk clock */
+        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
 };
 static struct clk_lookup usart_clocks_lookups[] = {
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index c3dfb1b3b1e3..000b5e1da965 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -124,6 +124,12 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
                        at91_set_gpio_output(data->vbus_pin[i], 0);
        }
+        /* Enable overcurrent notification */
+        for (i = 0; i < data->ports; i++) {
+                if (data->overcurrent_pin[i])
+                        at91_set_gpio_input(data->overcurrent_pin[i], 1);
+        }
        usbh_ohci_data = *data;
        platform_device_register(&at91_usbh_ohci_device);
 }
@@ -1095,6 +1101,34 @@ static void __init at91_add_device_rtt(void)
 /* --------------------------------------------------------------------
+ *  TRNG
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_HW_RANDOM_ATMEL) || defined(CONFIG_HW_RANDOM_ATMEL_MODULE)
+static struct resource trng_resources[] = {
+        {
+                .start  = AT91SAM9G45_BASE_TRNG,
+                .end    = AT91SAM9G45_BASE_TRNG + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+static struct platform_device at91sam9g45_trng_device = {
+        .name           = "atmel-trng",
+        .id             = -1,
+        .resource       = trng_resources,
+        .num_resources  = ARRAY_SIZE(trng_resources),
+};
+static void __init at91_add_device_trng(void)
+{
+        platform_device_register(&at91sam9g45_trng_device);
+}
+#else
+static void __init at91_add_device_trng(void) {}
+#endif
+/* --------------------------------------------------------------------
 *  Watchdog
 * -------------------------------------------------------------------- */
@@ -1583,6 +1617,7 @@ static int __init at91_add_standard_devices(void)
        at91_add_device_hdmac();
        at91_add_device_rtc();
        at91_add_device_rtt();
+        at91_add_device_trng();
        at91_add_device_watchdog();
        at91_add_device_tc();
        return 0;
diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c
new file mode 100644
index 000000000000..0b7d32778210
--- /dev/null
+++ b/arch/arm/mach-at91/board-dt.c
@@ -0,0 +1,123 @@
+/*
+ *  Setup code for AT91SAM Evaluation Kits with Device Tree support
+ *
+ *  Covers: * AT91SAM9G45-EKES  board
+ *          * AT91SAM9M10-EKES  board
+ *          * AT91SAM9M10G45-EK board
+ *
+ *  Copyright (C) 2011 Atmel,
+ *                2011 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/gpio.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <mach/hardware.h>
+#include <mach/board.h>
+#include <mach/system_rev.h>
+#include <mach/at91sam9_smc.h>
+#include <asm/setup.h>
+#include <asm/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include "sam9_smc.h"
+#include "generic.h"
+static void __init ek_init_early(void)
+{
+        /* Initialize processor: 12.000 MHz crystal */
+        at91_initialize(12000000);
+        /* DGBU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
+}
+/* det_pin is not connected */
+static struct atmel_nand_data __initdata ek_nand_data = {
+        .ale            = 21,
+        .cle            = 22,
+        .rdy_pin        = AT91_PIN_PC8,
+        .enable_pin     = AT91_PIN_PC14,
+};
+static struct sam9_smc_config __initdata ek_nand_smc_config = {
+        .ncs_read_setup         = 0,
+        .nrd_setup              = 2,
+        .ncs_write_setup        = 0,
+        .nwe_setup              = 2,
+        .ncs_read_pulse         = 4,
+        .nrd_pulse              = 4,
+        .ncs_write_pulse        = 4,
+        .nwe_pulse              = 4,
+        .read_cycle             = 7,
+        .write_cycle            = 7,
+        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
+        .tdf_cycles             = 3,
+};
+static void __init ek_add_device_nand(void)
+{
+        ek_nand_data.bus_width_16 = board_have_nand_16bit();
+        /* setup bus-width (8 or 16) */
+        if (ek_nand_data.bus_width_16)
+                ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
+        else
+                ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
+        /* configure chip-select 3 (NAND) */
+        sam9_smc_configure(3, &ek_nand_smc_config);
+        at91_add_device_nand(&ek_nand_data);
+}
+static const struct of_device_id aic_of_match[] __initconst = {
+        { .compatible = "atmel,at91rm9200-aic", },
+        {},
+};
+static void __init at91_dt_init_irq(void)
+{
+        irq_domain_generate_simple(aic_of_match, 0xfffff000, 0);
+        at91_init_irq_default();
+}
+static void __init at91_dt_device_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+        /* NAND */
+        ek_add_device_nand();
+}
+static const char *at91_dt_board_compat[] __initdata = {
+        "atmel,at91sam9m10g45ek",
+        "calao,usb-a9g20",
+        NULL
+};
+DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")
+        /* Maintainer: Atmel */
+        .timer          = &at91sam926x_timer,
+        .map_io         = at91_map_io,
+        .init_early     = ek_init_early,
+        .init_irq       = at91_dt_init_irq,
+        .init_machine   = at91_dt_device_init,
+        .dt_compat      = at91_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c
new file mode 100644
index 000000000000..e927df0175df
--- /dev/null
+++ b/arch/arm/mach-at91/board-rsi-ews.c
@@ -0,0 +1,233 @@
+/*
+ * board-rsi-ews.c
+ *
+ *  Copyright (C)
+ *  2005 SAN People,
+ *  2008-2011 R-S-I Elektrotechnik GmbH & Co. KG
+ *
+ * Licensed under GPLv2 or later.
+ */
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/mtd/physmap.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <mach/hardware.h>
+#include <mach/board.h>
+#include <linux/gpio.h>
+#include "generic.h"
+static void __init rsi_ews_init_early(void)
+{
+        /* Initialize processor: 18.432 MHz crystal */
+        at91_initialize(18432000);
+        /* Setup the LEDs */
+        at91_init_leds(AT91_PIN_PB6, AT91_PIN_PB9);
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        /* This one is for debugging */
+        at91_register_uart(0, 0, 0);
+        /* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        /* Dialin/-out modem interface */
+        at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS
+                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                           | ATMEL_UART_RI);
+        /* USART3 on ttyS4. (Rx, Tx, RTS) */
+        /* RS485 communication */
+        at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_RTS);
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
+}
+/*
+ * Ethernet
+ */
+static struct at91_eth_data rsi_ews_eth_data __initdata = {
+        .phy_irq_pin    = AT91_PIN_PC4,
+        .is_rmii        = 1,
+};
+/*
+ * USB Host
+ */
+static struct at91_usbh_data rsi_ews_usbh_data __initdata = {
+        .ports          = 1,
+};
+/*
+ * SD/MC
+ */
+static struct at91_mmc_data rsi_ews_mmc_data __initdata = {
+        .slot_b         = 0,
+        .wire4          = 1,
+        .det_pin        = AT91_PIN_PB27,
+        .wp_pin         = AT91_PIN_PB29,
+};
+/*
+ * I2C
+ */
+static struct i2c_board_info rsi_ews_i2c_devices[] __initdata = {
+        {
+                I2C_BOARD_INFO("ds1337", 0x68),
+        },
+        {
+                I2C_BOARD_INFO("24c01", 0x50),
+        }
+};
+/*
+ * LEDs
+ */
+static struct gpio_led rsi_ews_leds[] = {
+        {
+                .name                   = "led0",
+                .gpio                   = AT91_PIN_PB6,
+                .active_low             = 0,
+        },
+        {
+                .name                   = "led1",
+                .gpio                   = AT91_PIN_PB7,
+                .active_low             = 0,
+        },
+        {
+                .name                   = "led2",
+                .gpio                   = AT91_PIN_PB8,
+                .active_low             = 0,
+        },
+        {
+                .name                   = "led3",
+                .gpio                   = AT91_PIN_PB9,
+                .active_low             = 0,
+        },
+};
+/*
+ * DataFlash
+ */
+static struct spi_board_info rsi_ews_spi_devices[] = {
+        {       /* DataFlash chip 1*/
+                .modalias       = "mtd_dataflash",
+                .chip_select    = 0,
+                .max_speed_hz   = 5 * 1000 * 1000,
+        },
+        {       /* DataFlash chip 2*/
+                .modalias       = "mtd_dataflash",
+                .chip_select    = 1,
+                .max_speed_hz   = 5 * 1000 * 1000,
+        },
+};
+/*
+ * NOR flash
+ */
+static struct mtd_partition rsiews_nor_partitions[] = {
+        {
+                .name           = "boot",
+                .offset         = 0,
+                .size           = 3 * SZ_128K,
+                .mask_flags     = MTD_WRITEABLE
+        },
+        {
+                .name           = "kernel",
+                .offset         = MTDPART_OFS_NXTBLK,
+                .size           = SZ_2M - (3 * SZ_128K)
+        },
+        {
+                .name           = "root",
+                .offset         = MTDPART_OFS_NXTBLK,
+                .size           = SZ_8M
+        },
+        {
+                .name           = "kernelupd",
+                .offset         = MTDPART_OFS_NXTBLK,
+                .size           = 3 * SZ_512K,
+                .mask_flags     = MTD_WRITEABLE
+        },
+        {
+                .name           = "rootupd",
+                .offset         = MTDPART_OFS_NXTBLK,
+                .size           = 9 * SZ_512K,
+                .mask_flags     = MTD_WRITEABLE
+        },
+};
+static struct physmap_flash_data rsiews_nor_data = {
+        .width          = 2,
+        .parts          = rsiews_nor_partitions,
+        .nr_parts       = ARRAY_SIZE(rsiews_nor_partitions),
+};
+#define NOR_BASE        AT91_CHIPSELECT_0
+#define NOR_SIZE        SZ_16M
+static struct resource nor_flash_resources[] = {
+        {
+                .start  = NOR_BASE,
+                .end    = NOR_BASE + NOR_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+static struct platform_device rsiews_nor_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                                .platform_data  = &rsiews_nor_data,
+        },
+        .resource       = nor_flash_resources,
+        .num_resources  = ARRAY_SIZE(nor_flash_resources),
+};
+/*
+ * Init Func
+ */
+static void __init rsi_ews_board_init(void)
+{
+        /* Serial */
+        at91_add_device_serial();
+        at91_set_gpio_output(AT91_PIN_PA21, 0);
+        /* Ethernet */
+        at91_add_device_eth(&rsi_ews_eth_data);
+        /* USB Host */
+        at91_add_device_usbh(&rsi_ews_usbh_data);
+        /* I2C */
+        at91_add_device_i2c(rsi_ews_i2c_devices,
+                        ARRAY_SIZE(rsi_ews_i2c_devices));
+        /* SPI */
+        at91_add_device_spi(rsi_ews_spi_devices,
+                        ARRAY_SIZE(rsi_ews_spi_devices));
+        /* MMC */
+        at91_add_device_mmc(0, &rsi_ews_mmc_data);
+        /* NOR Flash */
+        platform_device_register(&rsiews_nor_flash);
+        /* LEDs */
+        at91_gpio_leds(rsi_ews_leds, ARRAY_SIZE(rsi_ews_leds));
+}
+MACHINE_START(RSI_EWS, "RSI EWS")
+        /* Maintainer: Josef Holzmayr <holzmayr@rsi-elektrotechnik.de> */
+        .timer          = &at91rm9200_timer,
+        .map_io         = at91_map_io,
+        .init_early     = rsi_ews_init_early,
+        .init_irq       = at91_init_irq_default,
+        .init_machine   = rsi_ews_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/board-usb-a9260.c b/arch/arm/mach-at91/board-usb-a9260.c
deleted file mode 100644
index bac9b65cf551..000000000000
--- a/arch/arm/mach-at91/board-usb-a9260.c
+++ /dev/null
@@ -1,230 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-usb-a9260.c
- *
- *  Copyright (C) 2005 SAN People
- *  Copyright (C) 2006 Atmel
- *  Copyright (C) 2007 Calao-systems
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/clk.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91_shdwc.h>
-#include "sam9_smc.h"
-#include "generic.h"
-static void __init ek_init_early(void)
-{
-        /* Initialize processor: 12.000 MHz crystal */
-        at91_initialize(12000000);
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
-}
-/*
- * USB Host port
- */
-static struct at91_usbh_data __initdata ek_usbh_data = {
-        .ports          = 2,
-};
-/*
- * USB Device port
- */
-static struct at91_udc_data __initdata ek_udc_data = {
-        .vbus_pin       = AT91_PIN_PC5,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
-};
-/*
- * MACB Ethernet device
- */
-static struct at91_eth_data __initdata ek_macb_data = {
-        .phy_irq_pin    = AT91_PIN_PA31,
-        .is_rmii        = 1,
-};
-/*
- * NAND flash
- */
-static struct mtd_partition __initdata ek_nand_partition[] = {
-        {
-                .name   = "Uboot & Kernel",
-                .offset = 0,
-                .size   = SZ_16M,
-        },
-        {
-                .name   = "Root FS",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = 120 * SZ_1M,
-        },
-        {
-                .name   = "FS",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = 120 * SZ_1M,
-        }
-};
-static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
-{
-        *num_partitions = ARRAY_SIZE(ek_nand_partition);
-        return ek_nand_partition;
-}
-static struct atmel_nand_data __initdata ek_nand_data = {
-        .ale            = 21,
-        .cle            = 22,
-//      .det_pin        = ... not connected
-        .rdy_pin        = AT91_PIN_PC13,
-        .enable_pin     = AT91_PIN_PC14,
-        .partition_info = nand_partitions,
-};
-static struct sam9_smc_config __initdata ek_nand_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 1,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 1,
-        .ncs_read_pulse         = 3,
-        .nrd_pulse              = 3,
-        .ncs_write_pulse        = 3,
-        .nwe_pulse              = 3,
-        .read_cycle             = 5,
-        .write_cycle            = 5,
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
-        .tdf_cycles             = 2,
-};
-static void __init ek_add_device_nand(void)
-{
-        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &ek_nand_smc_config);
-        at91_add_device_nand(&ek_nand_data);
-}
-/*
- * GPIO Buttons
- */
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
-static struct gpio_keys_button ek_buttons[] = {
-        {       /* USER PUSH BUTTON */
-                .code           = KEY_ENTER,
-                .gpio           = AT91_PIN_PB10,
-                .active_low     = 1,
-                .desc           = "user_pb",
-                .wakeup         = 1,
-        }
-};
-static struct gpio_keys_platform_data ek_button_data = {
-        .buttons        = ek_buttons,
-        .nbuttons       = ARRAY_SIZE(ek_buttons),
-};
-static struct platform_device ek_button_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &ek_button_data,
-        }
-};
-static void __init ek_add_device_buttons(void)
-{
-        at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* user push button, pull up enabled */
-        at91_set_deglitch(AT91_PIN_PB10, 1);
-        platform_device_register(&ek_button_device);
-}
-#else
-static void __init ek_add_device_buttons(void) {}
-#endif
-/*
- * LEDs
- */
-static struct gpio_led ek_leds[] = {
-        {       /* user_led (green) */
-                .name                   = "user_led",
-                .gpio                   = AT91_PIN_PB21,
-                .active_low             = 0,
-                .default_trigger        = "heartbeat",
-        }
-};
-static void __init ek_board_init(void)
-{
-        /* Serial */
-        at91_add_device_serial();
-        /* USB Host */
-        at91_add_device_usbh(&ek_usbh_data);
-        /* USB Device */
-        at91_add_device_udc(&ek_udc_data);
-        /* NAND */
-        ek_add_device_nand();
-        /* I2C */
-        at91_add_device_i2c(NULL, 0);
-        /* Ethernet */
-        at91_add_device_eth(&ek_macb_data);
-        /* Push Buttons */
-        ek_add_device_buttons();
-        /* LEDs */
-        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
-        /* shutdown controller, wakeup button (5 msec low) */
-        at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW
-                                | AT91_SHDW_RTTWKEN);
-}
-MACHINE_START(USB_A9260, "CALAO USB_A9260")
-        /* Maintainer: calao-systems */
-        .timer          = &at91sam926x_timer,
-        .map_io         = at91_map_io,
-        .init_early     = ek_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = ek_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-usb-a9263.c b/arch/arm/mach-at91/board-usb-a926x.c
index 5bd735787d6d..5852d3d9890c 100644
--- a/arch/arm/mach-at91/board-usb-a9263.c
+++ b/arch/arm/mach-at91/board-usb-a926x.c
@@ -1,9 +1,10 @@
 /*
- * linux/arch/arm/mach-at91/board-usb-a9263.c
+ * linux/arch/arm/mach-at91/board-usb-a926x.c
 *
 *  Copyright (C) 2005 SAN People
 *  Copyright (C) 2007 Atmel Corporation.
 *  Copyright (C) 2007 Calao-systems
+ *  Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -21,14 +22,15 @@
 */
 #include <linux/types.h>
-#include <linux/gpio.h>
 #include <linux/init.h>
 #include <linux/mm.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
 #include <linux/gpio_keys.h>
+#include <linux/gpio.h>
 #include <linux/input.h>
+#include <linux/spi/mmc_spi.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -74,10 +76,42 @@ static struct at91_udc_data __initdata ek_udc_data = {
        .pullup_pin     = 0,            /* pull-up driven by UDC */
 };
+static void __init ek_add_device_udc(void)
+{
+        if (machine_is_usb_a9260() || machine_is_usb_a9g20())
+                ek_udc_data.vbus_pin = AT91_PIN_PC5;
+        at91_add_device_udc(&ek_udc_data);
+}
+#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#define MMC_SPI_CARD_DETECT_INT AT91_PIN_PC4
+static int at91_mmc_spi_init(struct device *dev,
+        irqreturn_t (*detect_int)(int, void *), void *data)
+{
+        /* Configure Interrupt pin as input, no pull-up */
+        at91_set_gpio_input(MMC_SPI_CARD_DETECT_INT, 0);
+        return request_irq(gpio_to_irq(MMC_SPI_CARD_DETECT_INT), detect_int,
+                IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
+                "mmc-spi-detect", data);
+}
+static void at91_mmc_spi_exit(struct device *dev, void *data)
+{
+        free_irq(gpio_to_irq(MMC_SPI_CARD_DETECT_INT), data);
+}
+static struct mmc_spi_platform_data at91_mmc_spi_pdata = {
+        .init = at91_mmc_spi_init,
+        .exit = at91_mmc_spi_exit,
+        .detect_delay = 100, /* msecs */
+};
+#endif
 /*
 * SPI devices.
 */
-static struct spi_board_info ek_spi_devices[] = {
+static struct spi_board_info usb_a9263_spi_devices[] = {
 #if !defined(CONFIG_MMC_AT91)
        {       /* DataFlash chip */
                .modalias       = "mtd_dataflash",
@@ -88,6 +122,27 @@ static struct spi_board_info ek_spi_devices[] = {
 #endif
 };
+static struct spi_board_info usb_a9g20_spi_devices[] = {
+#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+        {
+                .modalias = "mmc_spi",
+                .max_speed_hz = 20000000,       /* max spi clock (SCK) speed in HZ */
+                .bus_num = 1,
+                .chip_select = 0,
+                .platform_data = &at91_mmc_spi_pdata,
+                .mode = SPI_MODE_3,
+        },
+#endif
+};
+static void __init ek_add_device_spi(void)
+{
+        if (machine_is_usb_a9263())
+                at91_add_device_spi(usb_a9263_spi_devices, ARRAY_SIZE(usb_a9263_spi_devices));
+        else if (machine_is_usb_a9g20())
+                at91_add_device_spi(usb_a9g20_spi_devices, ARRAY_SIZE(usb_a9g20_spi_devices));
+}
 /*
 * MACB Ethernet device
 */
@@ -96,24 +151,42 @@ static struct at91_eth_data __initdata ek_macb_data = {
        .is_rmii        = 1,
 };
+static void __init ek_add_device_eth(void)
+{
+        if (machine_is_usb_a9260() || machine_is_usb_a9g20())
+                ek_macb_data.phy_irq_pin = AT91_PIN_PA31;
+        at91_add_device_eth(&ek_macb_data);
+}
 /*
 * NAND flash
 */
 static struct mtd_partition __initdata ek_nand_partition[] = {
        {
-                .name   = "Linux Kernel",
+                .name   = "barebox",
                .offset = 0,
-                .size   = SZ_16M,
+                .size   = 3 * SZ_128K,
-        },
+        }, {
-        {
+                .name   = "bareboxenv",
-                .name   = "Root FS",
                .offset = MTDPART_OFS_NXTBLK,
-                .size   = 120 * SZ_1M,
+                .size   = SZ_128K,
-        },
+        }, {
-        {
+                .name   = "bareboxenv2",
-                .name   = "FS",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = SZ_128K,
+        }, {
+                .name   = "kernel",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = 4 * SZ_1M,
+        }, {
+                .name   = "rootfs",
                .offset = MTDPART_OFS_NXTBLK,
                .size   = 120 * SZ_1M,
+        }, {
+                .name   = "data",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = MTDPART_SIZ_FULL,
        }
 };
@@ -132,7 +205,7 @@ static struct atmel_nand_data __initdata ek_nand_data = {
        .partition_info = nand_partitions,
 };
-static struct sam9_smc_config __initdata ek_nand_smc_config = {
+static struct sam9_smc_config __initdata usb_a9260_nand_smc_config = {
        .ncs_read_setup         = 0,
        .nrd_setup              = 1,
        .ncs_write_setup        = 0,
@@ -150,10 +223,36 @@ static struct sam9_smc_config __initdata ek_nand_smc_config = {
        .tdf_cycles             = 2,
 };
+static struct sam9_smc_config __initdata usb_a9g20_nand_smc_config = {
+        .ncs_read_setup         = 0,
+        .nrd_setup              = 2,
+        .ncs_write_setup        = 0,
+        .nwe_setup              = 2,
+        .ncs_read_pulse         = 4,
+        .nrd_pulse              = 4,
+        .ncs_write_pulse        = 4,
+        .nwe_pulse              = 4,
+        .read_cycle             = 7,
+        .write_cycle            = 7,
+        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
+        .tdf_cycles             = 3,
+};
 static void __init ek_add_device_nand(void)
 {
+        if (machine_is_usb_a9260() || machine_is_usb_a9g20()) {
+                ek_nand_data.rdy_pin    = AT91_PIN_PC13;
+                ek_nand_data.enable_pin = AT91_PIN_PC14;
+        }
        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &ek_nand_smc_config);
+        if (machine_is_usb_a9g20())
+                sam9_smc_configure(3, &usb_a9g20_nand_smc_config);
+        else
+                sam9_smc_configure(3, &usb_a9260_nand_smc_config);
        at91_add_device_nand(&ek_nand_data);
 }
@@ -210,6 +309,19 @@ static struct gpio_led ek_leds[] = {
        }
 };
+static struct i2c_board_info __initdata ek_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("rv3029c2", 0x56),
+        },
+};
+static void __init ek_add_device_leds(void)
+{
+        if (machine_is_usb_a9260() || machine_is_usb_a9g20())
+                ek_leds[0].active_low = 0;
+        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
+}
 static void __init ek_board_init(void)
 {
@@ -218,22 +330,29 @@ static void __init ek_board_init(void)
        /* USB Host */
        at91_add_device_usbh(&ek_usbh_data);
        /* USB Device */
-        at91_add_device_udc(&ek_udc_data);
+        ek_add_device_udc();
        /* SPI */
-        at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
+        ek_add_device_spi();
        /* Ethernet */
-        at91_add_device_eth(&ek_macb_data);
+        ek_add_device_eth();
        /* NAND */
        ek_add_device_nand();
-        /* I2C */
-        at91_add_device_i2c(NULL, 0);
        /* Push Buttons */
        ek_add_device_buttons();
        /* LEDs */
-        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
+        ek_add_device_leds();
-        /* shutdown controller, wakeup button (5 msec low) */
-        at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW
+        if (machine_is_usb_a9g20()) {
+                /* I2C */
+                at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
+        } else {
+                /* I2C */
+                at91_add_device_i2c(NULL, 0);
+                /* shutdown controller, wakeup button (5 msec low) */
+                at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10)
+                                | AT91_SHDW_WKMODE0_LOW
                                | AT91_SHDW_RTTWKEN);
+        }
 }
 MACHINE_START(USB_A9263, "CALAO USB_A9263")
@@ -244,3 +363,21 @@ MACHINE_START(USB_A9263, "CALAO USB_A9263")
        .init_irq       = at91_init_irq_default,
        .init_machine   = ek_board_init,
 MACHINE_END
+MACHINE_START(USB_A9260, "CALAO USB_A9260")
+        /* Maintainer: calao-systems */
+        .timer          = &at91sam926x_timer,
+        .map_io         = at91_map_io,
+        .init_early     = ek_init_early,
+        .init_irq       = at91_init_irq_default,
+        .init_machine   = ek_board_init,
+MACHINE_END
+MACHINE_START(USB_A9G20, "CALAO USB_A92G0")
+        /* Maintainer: Jean-Christophe PLAGNIOL-VILLARD */
+        .timer          = &at91sam926x_timer,
+        .map_io         = at91_map_io,
+        .init_early     = ek_init_early,
+        .init_irq       = at91_init_irq_default,
+        .init_machine   = ek_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index ed544a0d5a1d..d07767f4052e 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -98,6 +98,11 @@ extern void __init at91_add_device_eth(struct at91_eth_data *data);
 struct at91_usbh_data {
        u8              ports;          /* number of ports on root hub */
        u8              vbus_pin[2];    /* port power-control pin */
+        u8              vbus_pin_inverted;
+        u8              overcurrent_supported;
+        u8              overcurrent_pin[2];
+        u8              overcurrent_status[2];
+        u8              overcurrent_changed[2];
 };
 extern void __init at91_add_device_usbh(struct at91_usbh_data *data);
 extern void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data);
diff --git a/arch/arm/mach-at91/include/mach/timex.h b/arch/arm/mach-at91/include/mach/timex.h
index 31ac2d97f14c..85820ad801cc 100644
--- a/arch/arm/mach-at91/include/mach/timex.h
+++ b/arch/arm/mach-at91/include/mach/timex.h
@@ -64,7 +64,12 @@
 #elif defined(CONFIG_ARCH_AT91SAM9G20)
+#if defined(CONFIG_MACH_USB_A9G20)
+#define AT91SAM9_MASTER_CLOCK   133000000
+#else
 #define AT91SAM9_MASTER_CLOCK   132096000
+#endif
 #define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
 #elif defined(CONFIG_ARCH_AT91SAM9G45)
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index c0deacae778d..32d837d8eab9 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -192,6 +192,16 @@ config DA850_UI_RMII
 endchoice
+config DA850_WL12XX
+        bool "AM18x wl1271 daughter board"
+        depends on MACH_DAVINCI_DA850_EVM
+        help
+          The wl1271 daughter card for AM18x EVMs is a combo wireless
+          connectivity add-on card, based on the LS Research TiWi module with
+          Texas Instruments' wl1271 solution.
+          Say Y if you want to use a wl1271 expansion card connected to the
+          AM18x EVM.
 config GPIO_PCA953X
        default MACH_DAVINCI_DA850_EVM
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 6e41cb5baeb4..ec21663f8ddc 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -31,6 +31,8 @@
 #include <linux/input/tps6507x-ts.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
+#include <linux/delay.h>
+#include <linux/wl12xx.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -49,6 +51,9 @@
 #define DA850_MMCSD_CD_PIN              GPIO_TO_PIN(4, 0)
 #define DA850_MMCSD_WP_PIN              GPIO_TO_PIN(4, 1)
+#define DA850_WLAN_EN                   GPIO_TO_PIN(6, 9)
+#define DA850_WLAN_IRQ                  GPIO_TO_PIN(6, 10)
 #define DA850_MII_MDIO_CLKEN_PIN        GPIO_TO_PIN(2, 6)
 static struct mtd_partition da850evm_spiflash_part[] = {
@@ -1143,6 +1148,110 @@ static __init int da850_evm_init_cpufreq(void)
 static __init int da850_evm_init_cpufreq(void) { return 0; }
 #endif
+#ifdef CONFIG_DA850_WL12XX
+static void wl12xx_set_power(int index, bool power_on)
+{
+        static bool power_state;
+        pr_debug("Powering %s wl12xx", power_on ? "on" : "off");
+        if (power_on == power_state)
+                return;
+        power_state = power_on;
+        if (power_on) {
+                /* Power up sequence required for wl127x devices */
+                gpio_set_value(DA850_WLAN_EN, 1);
+                usleep_range(15000, 15000);
+                gpio_set_value(DA850_WLAN_EN, 0);
+                usleep_range(1000, 1000);
+                gpio_set_value(DA850_WLAN_EN, 1);
+                msleep(70);
+        } else {
+                gpio_set_value(DA850_WLAN_EN, 0);
+        }
+}
+static struct davinci_mmc_config da850_wl12xx_mmc_config = {
+        .set_power      = wl12xx_set_power,
+        .wires          = 4,
+        .max_freq       = 25000000,
+        .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_NONREMOVABLE |
+                          MMC_CAP_POWER_OFF_CARD,
+        .version        = MMC_CTLR_VERSION_2,
+};
+static const short da850_wl12xx_pins[] __initconst = {
+        DA850_MMCSD1_DAT_0, DA850_MMCSD1_DAT_1, DA850_MMCSD1_DAT_2,
+        DA850_MMCSD1_DAT_3, DA850_MMCSD1_CLK, DA850_MMCSD1_CMD,
+        DA850_GPIO6_9, DA850_GPIO6_10,
+        -1
+};
+static struct wl12xx_platform_data da850_wl12xx_wlan_data __initdata = {
+        .irq                    = -1,
+        .board_ref_clock        = WL12XX_REFCLOCK_38,
+        .platform_quirks        = WL12XX_PLATFORM_QUIRK_EDGE_IRQ,
+};
+static __init int da850_wl12xx_init(void)
+{
+        int ret;
+        ret = davinci_cfg_reg_list(da850_wl12xx_pins);
+        if (ret) {
+                pr_err("wl12xx/mmc mux setup failed: %d\n", ret);
+                goto exit;
+        }
+        ret = da850_register_mmcsd1(&da850_wl12xx_mmc_config);
+        if (ret) {
+                pr_err("wl12xx/mmc registration failed: %d\n", ret);
+                goto exit;
+        }
+        ret = gpio_request_one(DA850_WLAN_EN, GPIOF_OUT_INIT_LOW, "wl12xx_en");
+        if (ret) {
+                pr_err("Could not request wl12xx enable gpio: %d\n", ret);
+                goto exit;
+        }
+        ret = gpio_request_one(DA850_WLAN_IRQ, GPIOF_IN, "wl12xx_irq");
+        if (ret) {
+                pr_err("Could not request wl12xx irq gpio: %d\n", ret);
+                goto free_wlan_en;
+        }
+        da850_wl12xx_wlan_data.irq = gpio_to_irq(DA850_WLAN_IRQ);
+        ret = wl12xx_set_platform_data(&da850_wl12xx_wlan_data);
+        if (ret) {
+                pr_err("Could not set wl12xx data: %d\n", ret);
+                goto free_wlan_irq;
+        }
+        return 0;
+free_wlan_irq:
+        gpio_free(DA850_WLAN_IRQ);
+free_wlan_en:
+        gpio_free(DA850_WLAN_EN);
+exit:
+        return ret;
+}
+#else /* CONFIG_DA850_WL12XX */
+static __init int da850_wl12xx_init(void)
+{
+        return 0;
+}
+#endif /* CONFIG_DA850_WL12XX */
 #define DA850EVM_SATA_REFCLKPN_RATE     (100 * 1000 * 1000)
 static __init void da850_evm_init(void)
@@ -1197,6 +1306,11 @@ static __init void da850_evm_init(void)
                if (ret)
                        pr_warning("da850_evm_init: mmcsd0 registration failed:"
                                        " %d\n", ret);
+                ret = da850_wl12xx_init();
+                if (ret)
+                        pr_warning("da850_evm_init: wl12xx initialization"
+                                   " failed: %d\n", ret);
        }
        davinci_serial_init(&da850_evm_uart_config);
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 4aae01576aab..b047f8702278 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -536,6 +536,13 @@ static const struct mux_config da850_pins[] = {
        MUX_CFG(DA850, MMCSD0_DAT_3,    10,     20,     15,     2,      false)
        MUX_CFG(DA850, MMCSD0_CLK,      10,     0,      15,     2,      false)
        MUX_CFG(DA850, MMCSD0_CMD,      10,     4,      15,     2,      false)
+        /* MMC/SD1 function */
+        MUX_CFG(DA850, MMCSD1_DAT_0,    18,     8,      15,     2,      false)
+        MUX_CFG(DA850, MMCSD1_DAT_1,    19,     16,     15,     2,      false)
+        MUX_CFG(DA850, MMCSD1_DAT_2,    19,     12,     15,     2,      false)
+        MUX_CFG(DA850, MMCSD1_DAT_3,    19,     8,      15,     2,      false)
+        MUX_CFG(DA850, MMCSD1_CLK,      18,     12,     15,     2,      false)
+        MUX_CFG(DA850, MMCSD1_CMD,      18,     16,     15,     2,      false)
        /* EMIF2.5/EMIFA function */
        MUX_CFG(DA850, EMA_D_7,         9,      0,      15,     1,      false)
        MUX_CFG(DA850, EMA_D_6,         9,      4,      15,     1,      false)
@@ -594,6 +601,8 @@ static const struct mux_config da850_pins[] = {
        MUX_CFG(DA850, GPIO3_13,        7,      8,      15,     8,      false)
        MUX_CFG(DA850, GPIO4_0,         10,     28,     15,     8,      false)
        MUX_CFG(DA850, GPIO4_1,         10,     24,     15,     8,      false)
+        MUX_CFG(DA850, GPIO6_9,         13,     24,     15,     8,      false)
+        MUX_CFG(DA850, GPIO6_10,        13,     20,     15,     8,      false)
        MUX_CFG(DA850, GPIO6_13,        13,     8,      15,     8,      false)
        MUX_CFG(DA850, RTC_ALARM,       0,      28,     15,     2,      false)
 #endif
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 2f7e719636f1..68def7188868 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -136,6 +136,7 @@ static struct edma_soc_info da830_edma_cc0_info = {
        .n_cc                   = 1,
        .queue_tc_mapping       = da8xx_queue_tc_mapping,
        .queue_priority_mapping = da8xx_queue_priority_mapping,
+        .default_queue          = EVENTQ_1,
 };
 static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = {
@@ -151,6 +152,7 @@ static struct edma_soc_info da850_edma_cc_info[] = {
                .n_cc                   = 1,
                .queue_tc_mapping       = da8xx_queue_tc_mapping,
                .queue_priority_mapping = da8xx_queue_priority_mapping,
+                .default_queue          = EVENTQ_1,
        },
        {
                .n_channel              = 32,
@@ -160,6 +162,7 @@ static struct edma_soc_info da850_edma_cc_info[] = {
                .n_cc                   = 1,
                .queue_tc_mapping       = da850_queue_tc_mapping,
                .queue_priority_mapping = da850_queue_priority_mapping,
+                .default_queue          = EVENTQ_0,
        },
 };
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
index 6162cae7f868..29b17f7d3a5f 100644
--- a/arch/arm/mach-davinci/devices-tnetv107x.c
+++ b/arch/arm/mach-davinci/devices-tnetv107x.c
@@ -80,6 +80,7 @@ static struct edma_soc_info edma_cc0_info = {
        .n_cc                   = 1,
        .queue_tc_mapping       = edma_tc_mapping,
        .queue_priority_mapping = edma_priority_mapping,
+        .default_queue          = EVENTQ_1,
 };
 static struct edma_soc_info *tnetv107x_edma_info[EDMA_MAX_CC] = {
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index c143f43addcc..fe520d4167a2 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -591,6 +591,7 @@ static struct edma_soc_info edma_cc0_info = {
        .n_cc                   = 1,
        .queue_tc_mapping       = queue_tc_mapping,
        .queue_priority_mapping = queue_priority_mapping,
+        .default_queue          = EVENTQ_1,
 };
 static struct edma_soc_info *dm355_edma_info[EDMA_MAX_CC] = {
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 9a274665edc5..3470983aa343 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -514,6 +514,7 @@ static struct edma_soc_info edma_cc0_info = {
        .n_cc                   = 1,
        .queue_tc_mapping       = queue_tc_mapping,
        .queue_priority_mapping = queue_priority_mapping,
+        .default_queue          = EVENTQ_1,
 };
 static struct edma_soc_info *dm644x_edma_info[EDMA_MAX_CC] = {
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 03e5f4931b42..0b68ed534f8e 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -555,6 +555,7 @@ static struct edma_soc_info edma_cc0_info = {
        .n_cc                   = 1,
        .queue_tc_mapping       = dm646x_queue_tc_mapping,
        .queue_priority_mapping = dm646x_queue_priority_mapping,
+        .default_queue          = EVENTQ_1,
 };
 static struct edma_soc_info *dm646x_edma_info[EDMA_MAX_CC] = {
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index 6b9669869c46..da90103a313d 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -1435,12 +1435,11 @@ static int __init edma_probe(struct platform_device *pdev)
                        goto fail1;
                }
-                edma_cc[j] = kmalloc(sizeof(struct edma), GFP_KERNEL);
+                edma_cc[j] = kzalloc(sizeof(struct edma), GFP_KERNEL);
                if (!edma_cc[j]) {
                        status = -ENOMEM;
                        goto fail1;
                }
-                memset(edma_cc[j], 0, sizeof(struct edma));
                edma_cc[j]->num_channels = min_t(unsigned, info[j]->n_channel,
                                                        EDMA_MAX_DMACH);
@@ -1450,8 +1449,6 @@ static int __init edma_probe(struct platform_device *pdev)
                                                        EDMA_MAX_CC);
                edma_cc[j]->default_queue = info[j]->default_queue;
-                if (!edma_cc[j]->default_queue)
-                        edma_cc[j]->default_queue = EVENTQ_1;
                dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
                        edmacc_regs_base[j]);
diff --git a/arch/arm/mach-davinci/include/mach/mmc.h b/arch/arm/mach-davinci/include/mach/mmc.h
index d4f1e9675069..5ba6b22ce338 100644
--- a/arch/arm/mach-davinci/include/mach/mmc.h
+++ b/arch/arm/mach-davinci/include/mach/mmc.h
@@ -12,6 +12,9 @@ struct davinci_mmc_config {
        /* get_cd()/get_wp() may sleep */
        int     (*get_cd)(int module);
        int     (*get_ro)(int module);
+        void    (*set_power)(int module, bool on);
        /* wires == 0 is equivalent to wires == 4 (4-bit parallel) */
        u8      wires;
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index 5d4e0fed828a..a7e92fca32e6 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -857,6 +857,14 @@ enum davinci_da850_index {
        DA850_MMCSD0_CLK,
        DA850_MMCSD0_CMD,
+        /* MMC/SD1 function */
+        DA850_MMCSD1_DAT_0,
+        DA850_MMCSD1_DAT_1,
+        DA850_MMCSD1_DAT_2,
+        DA850_MMCSD1_DAT_3,
+        DA850_MMCSD1_CLK,
+        DA850_MMCSD1_CMD,
        /* EMIF2.5/EMIFA function */
        DA850_EMA_D_7,
        DA850_EMA_D_6,
@@ -916,6 +924,8 @@ enum davinci_da850_index {
        DA850_GPIO3_13,
        DA850_GPIO4_0,
        DA850_GPIO4_1,
+        DA850_GPIO6_9,
+        DA850_GPIO6_10,
        DA850_GPIO6_13,
        DA850_RTC_ALARM,
 };
diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig
index 3a08b18f6433..97a249395b5a 100644
--- a/arch/arm/mach-ep93xx/Kconfig
+++ b/arch/arm/mach-ep93xx/Kconfig
@@ -182,6 +182,13 @@ config MACH_TS72XX
          Say 'Y' here if you want your kernel to support the
          Technologic Systems TS-72xx board.
+config MACH_VISION_EP9307
+        bool "Support Vision Engraving Systems EP9307 SoM"
+        depends on EP93XX_SDCE0_PHYS_OFFSET
+        help
+          Say 'Y' here if you want your kernel to support the
+          Vision Engraving Systems EP9307 SoM.
 choice
        prompt "Select a UART for early kernel messages"
diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile
index 3cedcf2d39e5..574209d9e246 100644
--- a/arch/arm/mach-ep93xx/Makefile
+++ b/arch/arm/mach-ep93xx/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_MACH_MICRO9)	+= micro9.o
 obj-$(CONFIG_MACH_SIM_ONE)      += simone.o
 obj-$(CONFIG_MACH_SNAPPER_CL15) += snappercl15.o
 obj-$(CONFIG_MACH_TS72XX)       += ts72xx.o
+obj-$(CONFIG_MACH_VISION_EP9307)+= vision_ep9307.o
diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vision_ep9307.c
new file mode 100644
index 000000000000..d96e4dbec6a8
--- /dev/null
+++ b/arch/arm/mach-ep93xx/vision_ep9307.c
@@ -0,0 +1,364 @@
+/*
+ * arch/arm/mach-ep93xx/vision_ep9307.c
+ * Vision Engraving Systems EP9307 SoM support.
+ *
+ * Copyright (C) 2008-2011 Vision Engraving Systems
+ * H Hartley Sweeten <hsweeten@visionengravers.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ */
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/fb.h>
+#include <linux/io.h>
+#include <linux/mtd/partitions.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+#include <linux/i2c/pca953x.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/mmc_spi.h>
+#include <linux/mmc/host.h>
+#include <mach/hardware.h>
+#include <mach/fb.h>
+#include <mach/ep93xx_spi.h>
+#include <asm/mach-types.h>
+#include <asm/mach/map.h>
+#include <asm/mach/arch.h>
+/*************************************************************************
+ * Static I/O mappings for the FPGA
+ *************************************************************************/
+#define VISION_PHYS_BASE        EP93XX_CS7_PHYS_BASE
+#define VISION_VIRT_BASE        0xfebff000
+static struct map_desc vision_io_desc[] __initdata = {
+        {
+                .virtual        = VISION_VIRT_BASE,
+                .pfn            = __phys_to_pfn(VISION_PHYS_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        },
+};
+static void __init vision_map_io(void)
+{
+        ep93xx_map_io();
+        iotable_init(vision_io_desc, ARRAY_SIZE(vision_io_desc));
+}
+/*************************************************************************
+ * Ethernet
+ *************************************************************************/
+static struct ep93xx_eth_data vision_eth_data __initdata = {
+        .phy_id         = 1,
+};
+/*************************************************************************
+ * Framebuffer
+ *************************************************************************/
+#define VISION_LCD_ENABLE       EP93XX_GPIO_LINE_EGPIO1
+static int vision_lcd_setup(struct platform_device *pdev)
+{
+        int err;
+        err = gpio_request_one(VISION_LCD_ENABLE, GPIOF_INIT_HIGH,
+                                dev_name(&pdev->dev));
+        if (err)
+                return err;
+        ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_RAS |
+                                 EP93XX_SYSCON_DEVCFG_RASONP3 |
+                                 EP93XX_SYSCON_DEVCFG_EXVC);
+        return 0;
+}
+static void vision_lcd_teardown(struct platform_device *pdev)
+{
+        gpio_free(VISION_LCD_ENABLE);
+}
+static void vision_lcd_blank(int blank_mode, struct fb_info *info)
+{
+        if (blank_mode)
+                gpio_set_value(VISION_LCD_ENABLE, 0);
+        else
+                gpio_set_value(VISION_LCD_ENABLE, 1);
+}
+static struct ep93xxfb_mach_info ep93xxfb_info __initdata = {
+        .num_modes      = EP93XXFB_USE_MODEDB,
+        .bpp            = 16,
+        .flags          = EP93XXFB_USE_SDCSN0 | EP93XXFB_PCLK_FALLING,
+        .setup          = vision_lcd_setup,
+        .teardown       = vision_lcd_teardown,
+        .blank          = vision_lcd_blank,
+};
+/*************************************************************************
+ * GPIO Expanders
+ *************************************************************************/
+#define PCA9539_74_GPIO_BASE    (EP93XX_GPIO_LINE_MAX + 1)
+#define PCA9539_75_GPIO_BASE    (PCA9539_74_GPIO_BASE + 16)
+#define PCA9539_76_GPIO_BASE    (PCA9539_75_GPIO_BASE + 16)
+#define PCA9539_77_GPIO_BASE    (PCA9539_76_GPIO_BASE + 16)
+static struct pca953x_platform_data pca953x_74_gpio_data = {
+        .gpio_base      = PCA9539_74_GPIO_BASE,
+        .irq_base       = EP93XX_BOARD_IRQ(0),
+};
+static struct pca953x_platform_data pca953x_75_gpio_data = {
+        .gpio_base      = PCA9539_75_GPIO_BASE,
+        .irq_base       = -1,
+};
+static struct pca953x_platform_data pca953x_76_gpio_data = {
+        .gpio_base      = PCA9539_76_GPIO_BASE,
+        .irq_base       = -1,
+};
+static struct pca953x_platform_data pca953x_77_gpio_data = {
+        .gpio_base      = PCA9539_77_GPIO_BASE,
+        .irq_base       = -1,
+};
+/*************************************************************************
+ * I2C Bus
+ *************************************************************************/
+static struct i2c_gpio_platform_data vision_i2c_gpio_data __initdata = {
+        .sda_pin                = EP93XX_GPIO_LINE_EEDAT,
+        .scl_pin                = EP93XX_GPIO_LINE_EECLK,
+};
+static struct i2c_board_info vision_i2c_info[] __initdata = {
+        {
+                I2C_BOARD_INFO("isl1208", 0x6f),
+                .irq            = IRQ_EP93XX_EXT1,
+        }, {
+                I2C_BOARD_INFO("pca9539", 0x74),
+                .platform_data  = &pca953x_74_gpio_data,
+                .irq            = gpio_to_irq(EP93XX_GPIO_LINE_F(7)),
+        }, {
+                I2C_BOARD_INFO("pca9539", 0x75),
+                .platform_data  = &pca953x_75_gpio_data,
+        }, {
+                I2C_BOARD_INFO("pca9539", 0x76),
+                .platform_data  = &pca953x_76_gpio_data,
+        }, {
+                I2C_BOARD_INFO("pca9539", 0x77),
+                .platform_data  = &pca953x_77_gpio_data,
+        },
+};
+/*************************************************************************
+ * SPI Flash
+ *************************************************************************/
+#define VISION_SPI_FLASH_CS     EP93XX_GPIO_LINE_EGPIO7
+static struct mtd_partition vision_spi_flash_partitions[] = {
+        {
+                .name   = "SPI bootstrap",
+                .offset = 0,
+                .size   = SZ_4K,
+        }, {
+                .name   = "Bootstrap config",
+                .offset = MTDPART_OFS_APPEND,
+                .size   = SZ_4K,
+        }, {
+                .name   = "System config",
+                .offset = MTDPART_OFS_APPEND,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+static struct flash_platform_data vision_spi_flash_data = {
+        .name           = "SPI Flash",
+        .parts          = vision_spi_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(vision_spi_flash_partitions),
+};
+static int vision_spi_flash_hw_setup(struct spi_device *spi)
+{
+        return gpio_request_one(VISION_SPI_FLASH_CS, GPIOF_INIT_HIGH,
+                                spi->modalias);
+}
+static void vision_spi_flash_hw_cleanup(struct spi_device *spi)
+{
+        gpio_free(VISION_SPI_FLASH_CS);
+}
+static void vision_spi_flash_hw_cs_control(struct spi_device *spi, int value)
+{
+        gpio_set_value(VISION_SPI_FLASH_CS, value);
+}
+static struct ep93xx_spi_chip_ops vision_spi_flash_hw = {
+        .setup          = vision_spi_flash_hw_setup,
+        .cleanup        = vision_spi_flash_hw_cleanup,
+        .cs_control     = vision_spi_flash_hw_cs_control,
+};
+/*************************************************************************
+ * SPI SD/MMC host
+ *************************************************************************/
+#define VISION_SPI_MMC_CS       EP93XX_GPIO_LINE_G(2)
+#define VISION_SPI_MMC_WP       EP93XX_GPIO_LINE_F(0)
+#define VISION_SPI_MMC_CD       EP93XX_GPIO_LINE_EGPIO15
+static struct gpio vision_spi_mmc_gpios[] = {
+        { VISION_SPI_MMC_WP, GPIOF_DIR_IN, "mmc_spi:wp" },
+        { VISION_SPI_MMC_CD, GPIOF_DIR_IN, "mmc_spi:cd" },
+};
+static int vision_spi_mmc_init(struct device *pdev,
+                        irqreturn_t (*func)(int, void *), void *pdata)
+{
+        int err;
+        err = gpio_request_array(vision_spi_mmc_gpios,
+                                 ARRAY_SIZE(vision_spi_mmc_gpios));
+        if (err)
+                return err;
+        err = gpio_set_debounce(VISION_SPI_MMC_CD, 1);
+        if (err)
+                goto exit_err;
+        err = request_irq(gpio_to_irq(VISION_SPI_MMC_CD), func,
+                        IRQ_TYPE_EDGE_BOTH, "mmc_spi:cd", pdata);
+        if (err)
+                goto exit_err;
+        return 0;
+exit_err:
+        gpio_free_array(vision_spi_mmc_gpios, ARRAY_SIZE(vision_spi_mmc_gpios));
+        return err;
+}
+static void vision_spi_mmc_exit(struct device *pdev, void *pdata)
+{
+        free_irq(gpio_to_irq(VISION_SPI_MMC_CD), pdata);
+        gpio_free_array(vision_spi_mmc_gpios, ARRAY_SIZE(vision_spi_mmc_gpios));
+}
+static int vision_spi_mmc_get_ro(struct device *pdev)
+{
+        return !!gpio_get_value(VISION_SPI_MMC_WP);
+}
+static int vision_spi_mmc_get_cd(struct device *pdev)
+{
+        return !gpio_get_value(VISION_SPI_MMC_CD);
+}
+static struct mmc_spi_platform_data vision_spi_mmc_data = {
+        .init           = vision_spi_mmc_init,
+        .exit           = vision_spi_mmc_exit,
+        .get_ro         = vision_spi_mmc_get_ro,
+        .get_cd         = vision_spi_mmc_get_cd,
+        .detect_delay   = 100,
+        .powerup_msecs  = 100,
+        .ocr_mask       = MMC_VDD_32_33 | MMC_VDD_33_34,
+};
+static int vision_spi_mmc_hw_setup(struct spi_device *spi)
+{
+        return gpio_request_one(VISION_SPI_MMC_CS, GPIOF_INIT_HIGH,
+                                spi->modalias);
+}
+static void vision_spi_mmc_hw_cleanup(struct spi_device *spi)
+{
+        gpio_free(VISION_SPI_MMC_CS);
+}
+static void vision_spi_mmc_hw_cs_control(struct spi_device *spi, int value)
+{
+        gpio_set_value(VISION_SPI_MMC_CS, value);
+}
+static struct ep93xx_spi_chip_ops vision_spi_mmc_hw = {
+        .setup          = vision_spi_mmc_hw_setup,
+        .cleanup        = vision_spi_mmc_hw_cleanup,
+        .cs_control     = vision_spi_mmc_hw_cs_control,
+};
+/*************************************************************************
+ * SPI Bus
+ *************************************************************************/
+static struct spi_board_info vision_spi_board_info[] __initdata = {
+        {
+                .modalias               = "sst25l",
+                .platform_data          = &vision_spi_flash_data,
+                .controller_data        = &vision_spi_flash_hw,
+                .max_speed_hz           = 20000000,
+                .bus_num                = 0,
+                .chip_select            = 0,
+                .mode                   = SPI_MODE_3,
+        }, {
+                .modalias               = "mmc_spi",
+                .platform_data          = &vision_spi_mmc_data,
+                .controller_data        = &vision_spi_mmc_hw,
+                .max_speed_hz           = 20000000,
+                .bus_num                = 0,
+                .chip_select            = 1,
+                .mode                   = SPI_MODE_3,
+        },
+};
+static struct ep93xx_spi_info vision_spi_master __initdata = {
+        .num_chipselect         = ARRAY_SIZE(vision_spi_board_info),
+};
+/*************************************************************************
+ * Machine Initialization
+ *************************************************************************/
+static void __init vision_init_machine(void)
+{
+        ep93xx_init_devices();
+        ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_64M);
+        ep93xx_register_eth(&vision_eth_data, 1);
+        ep93xx_register_fb(&ep93xxfb_info);
+        ep93xx_register_pwm(1, 0);
+        /*
+         * Request the gpio expander's interrupt gpio line now to prevent
+         * the kernel from doing a WARN in gpiolib:gpio_ensure_requested().
+         */
+        if (gpio_request_one(EP93XX_GPIO_LINE_F(7), GPIOF_DIR_IN,
+                                "pca9539:74"))
+                pr_warn("cannot request interrupt gpio for pca9539:74\n");
+        ep93xx_register_i2c(&vision_i2c_gpio_data, vision_i2c_info,
+                                ARRAY_SIZE(vision_i2c_info));
+        ep93xx_register_spi(&vision_spi_master, vision_spi_board_info,
+                                ARRAY_SIZE(vision_spi_board_info));
+}
+MACHINE_START(VISION_EP9307, "Vision Engraving Systems EP9307")
+        /* Maintainer: H Hartley Sweeten <hsweeten@visionengravers.com> */
+        .atag_offset    = 0x100,
+        .map_io         = vision_map_io,
+        .init_irq       = ep93xx_init_irq,
+        .timer          = &ep93xx_timer,
+        .init_machine   = vision_init_machine,
+MACHINE_END
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index fc1f92dfbea8..a65273598036 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -16,6 +16,16 @@ config CPU_EXYNOS4210
        help
          Enable EXYNOS4210 CPU support
+config SOC_EXYNOS4212
+        bool
+        help
+          Enable EXYNOS4212 SoC support
+config SOC_EXYNOS4412
+        bool
+        help
+          Enable EXYNOS4412 SoC support
 config EXYNOS4_MCT
        bool
        default y
@@ -112,24 +122,11 @@ config EXYNOS4_SETUP_USB_PHY
 menu "EXYNOS4 Machines"
+comment "EXYNOS4210 Boards"
 config MACH_SMDKC210
        bool "SMDKC210"
-        select CPU_EXYNOS4210
+        select MACH_SMDKV310
-        select S5P_DEV_FIMD0
-        select S3C_DEV_RTC
-        select S3C_DEV_WDT
-        select S3C_DEV_I2C1
-        select S3C_DEV_HSMMC
-        select S3C_DEV_HSMMC1
-        select S3C_DEV_HSMMC2
-        select S3C_DEV_HSMMC3
-        select SAMSUNG_DEV_PWM
-        select SAMSUNG_DEV_BACKLIGHT
-        select EXYNOS4_DEV_PD
-        select EXYNOS4_DEV_SYSMMU
-        select EXYNOS4_SETUP_FIMD0
-        select EXYNOS4_SETUP_I2C1
-        select EXYNOS4_SETUP_SDHCI
        help
          Machine support for Samsung SMDKC210
@@ -219,6 +216,48 @@ config MACH_NURI
        help
          Machine support for Samsung Mobile NURI Board.
+config MACH_ORIGEN
+        bool "ORIGEN"
+        select CPU_EXYNOS4210
+        select S3C_DEV_RTC
+        select S3C_DEV_WDT
+        select S3C_DEV_HSMMC2
+        select EXYNOS4_SETUP_SDHCI
+        help
+          Machine support for ORIGEN based on Samsung EXYNOS4210
+comment "EXYNOS4212 Boards"
+config MACH_SMDK4212
+        bool "SMDK4212"
+        select SOC_EXYNOS4212
+        select S3C_DEV_HSMMC2
+        select S3C_DEV_HSMMC3
+        select S3C_DEV_I2C1
+        select S3C_DEV_I2C3
+        select S3C_DEV_I2C7
+        select S3C_DEV_RTC
+        select S3C_DEV_WDT
+        select SAMSUNG_DEV_BACKLIGHT
+        select SAMSUNG_DEV_KEYPAD
+        select SAMSUNG_DEV_PWM
+        select EXYNOS4_SETUP_I2C1
+        select EXYNOS4_SETUP_I2C3
+        select EXYNOS4_SETUP_I2C7
+        select EXYNOS4_SETUP_KEYPAD
+        select EXYNOS4_SETUP_SDHCI
+        help
+          Machine support for Samsung SMDK4212
+comment "EXYNOS4412 Boards"
+config MACH_SMDK4412
+        bool "SMDK4412"
+        select SOC_EXYNOS4412
+        select MACH_SMDK4212
+        help
+          Machine support for Samsung SMDK4412
 endmenu
 comment "Configuration for HSMMC bus width"
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index b7fe1d7b0b1f..c9b2e1f97e44 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -12,8 +12,10 @@ obj-				:=
 # Core support for EXYNOS4 system
-obj-$(CONFIG_CPU_EXYNOS4210)    += cpu.o init.o clock.o irq-combiner.o
+obj-$(CONFIG_ARCH_EXYNOS4)      += cpu.o init.o clock.o irq-combiner.o
-obj-$(CONFIG_CPU_EXYNOS4210)    += setup-i2c0.o irq-eint.o dma.o pmu.o
+obj-$(CONFIG_ARCH_EXYNOS4)      += setup-i2c0.o irq-eint.o dma.o pmu.o
+obj-$(CONFIG_CPU_EXYNOS4210)    += clock-exynos4210.o
+obj-$(CONFIG_SOC_EXYNOS4212)    += clock-exynos4212.o
 obj-$(CONFIG_PM)                += pm.o sleep.o
 obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
@@ -25,11 +27,15 @@ obj-$(CONFIG_HOTPLUG_CPU)	+= hotplug.o
 # machine support
-obj-$(CONFIG_MACH_SMDKC210)             += mach-smdkc210.o
+obj-$(CONFIG_MACH_SMDKC210)             += mach-smdkv310.o
 obj-$(CONFIG_MACH_SMDKV310)             += mach-smdkv310.o
 obj-$(CONFIG_MACH_ARMLEX4210)           += mach-armlex4210.o
 obj-$(CONFIG_MACH_UNIVERSAL_C210)       += mach-universal_c210.o
 obj-$(CONFIG_MACH_NURI)                 += mach-nuri.o
+obj-$(CONFIG_MACH_ORIGEN)               += mach-origen.o
+obj-$(CONFIG_MACH_SMDK4212)             += mach-smdk4x12.o
+obj-$(CONFIG_MACH_SMDK4412)             += mach-smdk4x12.o
 # device support
diff --git a/arch/arm/mach-exynos4/clock-exynos4210.c b/arch/arm/mach-exynos4/clock-exynos4210.c
new file mode 100644
index 000000000000..b9d5ef670eb4
--- /dev/null
+++ b/arch/arm/mach-exynos4/clock-exynos4210.c
@@ -0,0 +1,139 @@
+/*
+ * linux/arch/arm/mach-exynos4/clock-exynos4210.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * EXYNOS4210 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/syscore_ops.h>
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/exynos4.h>
+#include <plat/pm.h>
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/exynos4-clock.h>
+static struct sleep_save exynos4210_clock_save[] = {
+        SAVE_ITEM(S5P_CLKSRC_IMAGE),
+        SAVE_ITEM(S5P_CLKSRC_LCD1),
+        SAVE_ITEM(S5P_CLKDIV_IMAGE),
+        SAVE_ITEM(S5P_CLKDIV_LCD1),
+        SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
+        SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),
+        SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
+        SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
+};
+static struct clksrc_clk *sysclks[] = {
+        /* nothing here yet */
+};
+static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
+}
+static struct clksrc_clk clksrcs[] = {
+        {
+                .clk            = {
+                        .name           = "sclk_sata",
+                        .id             = -1,
+                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
+                        .ctrlbit        = (1 << 24),
+                },
+                .sources = &clkset_mout_corebus,
+                .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
+                .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_fimd",
+                        .devname        = "exynos4-fb.1",
+                        .enable         = exynos4_clksrc_mask_lcd1_ctrl,
+                        .ctrlbit        = (1 << 0),
+                },
+                .sources = &clkset_group,
+                .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
+                .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
+        },
+};
+static struct clk init_clocks_off[] = {
+        {
+                .name           = "sataphy",
+                .id             = -1,
+                .parent         = &clk_aclk_133.clk,
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "sata",
+                .id             = -1,
+                .parent         = &clk_aclk_133.clk,
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 10),
+        }, {
+                .name           = "fimd",
+                .devname        = "exynos4-fb.1",
+                .enable         = exynos4_clk_ip_lcd1_ctrl,
+                .ctrlbit        = (1 << 0),
+        },
+};
+#ifdef CONFIG_PM_SLEEP
+static int exynos4210_clock_suspend(void)
+{
+        s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
+        return 0;
+}
+static void exynos4210_clock_resume(void)
+{
+        s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
+}
+#else
+#define exynos4210_clock_suspend NULL
+#define exynos4210_clock_resume NULL
+#endif
+struct syscore_ops exynos4210_clock_syscore_ops = {
+        .suspend        = exynos4210_clock_suspend,
+        .resume         = exynos4210_clock_resume,
+};
+void __init exynos4210_register_clocks(void)
+{
+        int ptr;
+        clk_mout_mpll.reg_src.reg = S5P_CLKSRC_CPU;
+        clk_mout_mpll.reg_src.shift = 8;
+        clk_mout_mpll.reg_src.size = 1;
+        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
+                s3c_register_clksrc(sysclks[ptr], 1);
+        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        register_syscore_ops(&exynos4210_clock_syscore_ops);
+}
diff --git a/arch/arm/mach-exynos4/clock-exynos4212.c b/arch/arm/mach-exynos4/clock-exynos4212.c
new file mode 100644
index 000000000000..77d5decb34fd
--- /dev/null
+++ b/arch/arm/mach-exynos4/clock-exynos4212.c
@@ -0,0 +1,118 @@
+/*
+ * linux/arch/arm/mach-exynos4/clock-exynos4212.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * EXYNOS4212 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/syscore_ops.h>
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/exynos4.h>
+#include <plat/pm.h>
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/exynos4-clock.h>
+static struct sleep_save exynos4212_clock_save[] = {
+        SAVE_ITEM(S5P_CLKSRC_IMAGE),
+        SAVE_ITEM(S5P_CLKDIV_IMAGE),
+        SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
+        SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
+};
+static struct clk *clk_src_mpll_user_list[] = {
+        [0] = &clk_fin_mpll,
+        [1] = &clk_mout_mpll.clk,
+};
+static struct clksrc_sources clk_src_mpll_user = {
+        .sources        = clk_src_mpll_user_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_mpll_user_list),
+};
+static struct clksrc_clk clk_mout_mpll_user = {
+        .clk = {
+                .name           = "mout_mpll_user",
+        },
+        .sources        = &clk_src_mpll_user,
+        .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 24, .size = 1 },
+};
+static struct clksrc_clk *sysclks[] = {
+        &clk_mout_mpll_user,
+};
+static struct clksrc_clk clksrcs[] = {
+        /* nothing here yet */
+};
+static struct clk init_clocks_off[] = {
+        /* nothing here yet */
+};
+#ifdef CONFIG_PM_SLEEP
+static int exynos4212_clock_suspend(void)
+{
+        s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
+        return 0;
+}
+static void exynos4212_clock_resume(void)
+{
+        s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
+}
+#else
+#define exynos4212_clock_suspend NULL
+#define exynos4212_clock_resume NULL
+#endif
+struct syscore_ops exynos4212_clock_syscore_ops = {
+        .suspend        = exynos4212_clock_suspend,
+        .resume         = exynos4212_clock_resume,
+};
+void __init exynos4212_register_clocks(void)
+{
+        int ptr;
+        /* usbphy1 is removed */
+        clkset_group_list[4] = NULL;
+        /* mout_mpll_user is used */
+        clkset_group_list[6] = &clk_mout_mpll_user.clk;
+        clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
+        clk_mout_mpll.reg_src.reg = S5P_CLKSRC_DMC;
+        clk_mout_mpll.reg_src.shift = 12;
+        clk_mout_mpll.reg_src.size = 1;
+        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
+                s3c_register_clksrc(sysclks[ptr], 1);
+        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        register_syscore_ops(&exynos4212_clock_syscore_ops);
+}
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index 86964d2e9e1b..0d59be3fa1fe 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -13,6 +13,7 @@
 #include <linux/kernel.h>
 #include <linux/err.h>
 #include <linux/io.h>
+#include <linux/syscore_ops.h>
 #include <plat/cpu-freq.h>
 #include <plat/clock.h>
@@ -20,26 +21,93 @@
 #include <plat/pll.h>
 #include <plat/s5p-clock.h>
 #include <plat/clock-clksrc.h>
+#include <plat/exynos4.h>
+#include <plat/pm.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
 #include <mach/sysmmu.h>
+#include <mach/exynos4-clock.h>
-static struct clk clk_sclk_hdmi27m = {
+static struct sleep_save exynos4_clock_save[] = {
+        SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
+        SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
+        SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
+        SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
+        SAVE_ITEM(S5P_CLKSRC_TOP0),
+        SAVE_ITEM(S5P_CLKSRC_TOP1),
+        SAVE_ITEM(S5P_CLKSRC_CAM),
+        SAVE_ITEM(S5P_CLKSRC_TV),
+        SAVE_ITEM(S5P_CLKSRC_MFC),
+        SAVE_ITEM(S5P_CLKSRC_G3D),
+        SAVE_ITEM(S5P_CLKSRC_LCD0),
+        SAVE_ITEM(S5P_CLKSRC_MAUDIO),
+        SAVE_ITEM(S5P_CLKSRC_FSYS),
+        SAVE_ITEM(S5P_CLKSRC_PERIL0),
+        SAVE_ITEM(S5P_CLKSRC_PERIL1),
+        SAVE_ITEM(S5P_CLKDIV_CAM),
+        SAVE_ITEM(S5P_CLKDIV_TV),
+        SAVE_ITEM(S5P_CLKDIV_MFC),
+        SAVE_ITEM(S5P_CLKDIV_G3D),
+        SAVE_ITEM(S5P_CLKDIV_LCD0),
+        SAVE_ITEM(S5P_CLKDIV_MAUDIO),
+        SAVE_ITEM(S5P_CLKDIV_FSYS0),
+        SAVE_ITEM(S5P_CLKDIV_FSYS1),
+        SAVE_ITEM(S5P_CLKDIV_FSYS2),
+        SAVE_ITEM(S5P_CLKDIV_FSYS3),
+        SAVE_ITEM(S5P_CLKDIV_PERIL0),
+        SAVE_ITEM(S5P_CLKDIV_PERIL1),
+        SAVE_ITEM(S5P_CLKDIV_PERIL2),
+        SAVE_ITEM(S5P_CLKDIV_PERIL3),
+        SAVE_ITEM(S5P_CLKDIV_PERIL4),
+        SAVE_ITEM(S5P_CLKDIV_PERIL5),
+        SAVE_ITEM(S5P_CLKDIV_TOP),
+        SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
+        SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
+        SAVE_ITEM(S5P_CLKSRC_MASK_TV),
+        SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
+        SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
+        SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
+        SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
+        SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
+        SAVE_ITEM(S5P_CLKDIV2_RATIO),
+        SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
+        SAVE_ITEM(S5P_CLKGATE_IP_CAM),
+        SAVE_ITEM(S5P_CLKGATE_IP_TV),
+        SAVE_ITEM(S5P_CLKGATE_IP_MFC),
+        SAVE_ITEM(S5P_CLKGATE_IP_G3D),
+        SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
+        SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
+        SAVE_ITEM(S5P_CLKGATE_IP_GPS),
+        SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
+        SAVE_ITEM(S5P_CLKGATE_BLOCK),
+        SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
+        SAVE_ITEM(S5P_CLKSRC_DMC),
+        SAVE_ITEM(S5P_CLKDIV_DMC0),
+        SAVE_ITEM(S5P_CLKDIV_DMC1),
+        SAVE_ITEM(S5P_CLKGATE_IP_DMC),
+        SAVE_ITEM(S5P_CLKSRC_CPU),
+        SAVE_ITEM(S5P_CLKDIV_CPU),
+        SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
+        SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
+        SAVE_ITEM(S5P_CLKGATE_IP_CPU),
+};
+struct clk clk_sclk_hdmi27m = {
        .name           = "sclk_hdmi27m",
        .rate           = 27000000,
 };
-static struct clk clk_sclk_hdmiphy = {
+struct clk clk_sclk_hdmiphy = {
        .name           = "sclk_hdmiphy",
 };
-static struct clk clk_sclk_usbphy0 = {
+struct clk clk_sclk_usbphy0 = {
        .name           = "sclk_usbphy0",
        .rate           = 27000000,
 };
-static struct clk clk_sclk_usbphy1 = {
+struct clk clk_sclk_usbphy1 = {
        .name           = "sclk_usbphy1",
 };
@@ -58,12 +126,7 @@ static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
        return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
 }
-static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
+int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
-}
-static int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
 {
        return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
 }
@@ -103,12 +166,12 @@ static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
        return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
 }
-static int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
+int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
 {
        return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
 }
-static int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
+int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
 {
        return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
 }
@@ -133,7 +196,7 @@ static struct clksrc_clk clk_mout_apll = {
        .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
 };
-static struct clksrc_clk clk_sclk_apll = {
+struct clksrc_clk clk_sclk_apll = {
        .clk    = {
                .name           = "sclk_apll",
                .parent         = &clk_mout_apll.clk,
@@ -141,7 +204,7 @@ static struct clksrc_clk clk_sclk_apll = {
        .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
 };
-static struct clksrc_clk clk_mout_epll = {
+struct clksrc_clk clk_mout_epll = {
        .clk    = {
                .name           = "mout_epll",
        },
@@ -149,12 +212,13 @@ static struct clksrc_clk clk_mout_epll = {
        .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
 };
-static struct clksrc_clk clk_mout_mpll = {
+struct clksrc_clk clk_mout_mpll = {
        .clk = {
                .name           = "mout_mpll",
        },
        .sources        = &clk_src_mpll,
-        .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
+        /* reg_src will be added in each SoCs' clock */
 };
 static struct clk *clkset_moutcore_list[] = {
@@ -224,12 +288,12 @@ static struct clksrc_clk clk_periphclk = {
 /* Core list of CMU_CORE side */
-static struct clk *clkset_corebus_list[] = {
+struct clk *clkset_corebus_list[] = {
        [0] = &clk_mout_mpll.clk,
        [1] = &clk_sclk_apll.clk,
 };
-static struct clksrc_sources clkset_mout_corebus = {
+struct clksrc_sources clkset_mout_corebus = {
        .sources        = clkset_corebus_list,
        .nr_sources     = ARRAY_SIZE(clkset_corebus_list),
 };
@@ -284,12 +348,12 @@ static struct clksrc_clk clk_pclk_acp = {
 /* Core list of CMU_TOP side */
-static struct clk *clkset_aclk_top_list[] = {
+struct clk *clkset_aclk_top_list[] = {
        [0] = &clk_mout_mpll.clk,
        [1] = &clk_sclk_apll.clk,
 };
-static struct clksrc_sources clkset_aclk = {
+struct clksrc_sources clkset_aclk = {
        .sources        = clkset_aclk_top_list,
        .nr_sources     = ARRAY_SIZE(clkset_aclk_top_list),
 };
@@ -321,7 +385,7 @@ static struct clksrc_clk clk_aclk_160 = {
        .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
 };
-static struct clksrc_clk clk_aclk_133 = {
+struct clksrc_clk clk_aclk_133 = {
        .clk    = {
                .name           = "aclk_133",
        },
@@ -360,7 +424,7 @@ static struct clksrc_sources clkset_sclk_vpll = {
        .nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
 };
-static struct clksrc_clk clk_sclk_vpll = {
+struct clksrc_clk clk_sclk_vpll = {
        .clk    = {
                .name           = "sclk_vpll",
        },
@@ -410,16 +474,6 @@ static struct clk init_clocks_off[] = {
                .enable         = exynos4_clk_ip_lcd0_ctrl,
                .ctrlbit        = (1 << 0),
        }, {
-                .name           = "fimd",
-                .devname        = "exynos4-fb.1",
-                .enable         = exynos4_clk_ip_lcd1_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "sataphy",
-                .parent         = &clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
                .name           = "hsmmc",
                .devname        = "s3c-sdhci.0",
                .parent         = &clk_aclk_133.clk,
@@ -449,11 +503,6 @@ static struct clk init_clocks_off[] = {
                .enable         = exynos4_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 9),
        }, {
-                .name           = "sata",
-                .parent         = &clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
                .name           = "pdma",
                .devname        = "s3c-pl330.0",
                .enable         = exynos4_clk_ip_fsys_ctrl,
@@ -673,7 +722,7 @@ static struct clk init_clocks[] = {
        }
 };
-static struct clk *clkset_group_list[] = {
+struct clk *clkset_group_list[] = {
        [0] = &clk_ext_xtal_mux,
        [1] = &clk_xusbxti,
        [2] = &clk_sclk_hdmi27m,
@@ -685,7 +734,7 @@ static struct clk *clkset_group_list[] = {
        [8] = &clk_sclk_vpll.clk,
 };
-static struct clksrc_sources clkset_group = {
+struct clksrc_sources clkset_group = {
        .sources        = clkset_group_list,
        .nr_sources     = ARRAY_SIZE(clkset_group_list),
 };
@@ -967,25 +1016,6 @@ static struct clksrc_clk clksrcs[] = {
                .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
        }, {
                .clk            = {
-                        .name           = "sclk_fimd",
-                        .devname        = "exynos4-fb.1",
-                        .enable         = exynos4_clksrc_mask_lcd1_ctrl,
-                        .ctrlbit        = (1 << 0),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_sata",
-                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &clkset_mout_corebus,
-                .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
-                .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
-        }, {
-                .clk            = {
                        .name           = "sclk_spi",
                        .devname        = "s3c64xx-spi.0",
                        .enable         = exynos4_clksrc_mask_peril1_ctrl,
@@ -1114,7 +1144,13 @@ static int xtal_rate;
 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
 {
-        return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508);
+        if (soc_is_exynos4210())
+                return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
+                                        pll_4508);
+        else if (soc_is_exynos4212() || soc_is_exynos4412())
+                return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
+        else
+                return 0;
 }
 static struct clk_ops exynos4_fout_apll_ops = {
@@ -1124,10 +1160,10 @@ static struct clk_ops exynos4_fout_apll_ops = {
 void __init_or_cpufreq exynos4_setup_clocks(void)
 {
        struct clk *xtal_clk;
-        unsigned long apll;
+        unsigned long apll = 0;
-        unsigned long mpll;
+        unsigned long mpll = 0;
-        unsigned long epll;
+        unsigned long epll = 0;
-        unsigned long vpll;
+        unsigned long vpll = 0;
        unsigned long vpllsrc;
        unsigned long xtal;
        unsigned long armclk;
@@ -1151,14 +1187,29 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
        printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
-        apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508);
+        if (soc_is_exynos4210()) {
-        mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508);
+                apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0),
-        epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
+                                        pll_4508);
-                                __raw_readl(S5P_EPLL_CON1), pll_4600);
+                mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0),
+                                        pll_4508);
-        vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
+                epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
-        vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
+                                        __raw_readl(S5P_EPLL_CON1), pll_4600);
-                                __raw_readl(S5P_VPLL_CON1), pll_4650c);
+                vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
+                vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
+                                        __raw_readl(S5P_VPLL_CON1), pll_4650c);
+        } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
+                apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
+                mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
+                epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),
+                                        __raw_readl(S5P_EPLL_CON1));
+                vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
+                vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
+                                        __raw_readl(S5P_VPLL_CON1));
+        } else {
+                /* nothing */
+        }
        clk_fout_apll.ops = &exynos4_fout_apll_ops;
        clk_fout_mpll.rate = mpll;
@@ -1193,6 +1244,28 @@ static struct clk *clks[] __initdata = {
        /* Nothing here yet */
 };
+#ifdef CONFIG_PM_SLEEP
+static int exynos4_clock_suspend(void)
+{
+        s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
+        return 0;
+}
+static void exynos4_clock_resume(void)
+{
+        s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
+}
+#else
+#define exynos4_clock_suspend NULL
+#define exynos4_clock_resume NULL
+#endif
+struct syscore_ops exynos4_clock_syscore_ops = {
+        .suspend        = exynos4_clock_suspend,
+        .resume         = exynos4_clock_resume,
+};
 void __init exynos4_register_clocks(void)
 {
        int ptr;
@@ -1208,5 +1281,6 @@ void __init exynos4_register_clocks(void)
        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        register_syscore_ops(&exynos4_clock_syscore_ops);
        s3c_pwmclk_init();
 }
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 746d6fc6d397..a348434f17b5 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -32,6 +32,8 @@
 #include <mach/regs-irq.h>
 #include <mach/regs-pmu.h>
+unsigned int gic_bank_offset __read_mostly;
 extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
                         unsigned int irq_start);
 extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
@@ -44,11 +46,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
                .length         = SZ_4K,
                .type           = MT_DEVICE,
        }, {
-                .virtual        = (unsigned long)S5P_VA_SYSRAM,
-                .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
                .virtual        = (unsigned long)S5P_VA_CMU,
                .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
                .length         = SZ_128K,
@@ -121,6 +118,24 @@ static struct map_desc exynos4_iodesc[] __initdata = {
        },
 };
+static struct map_desc exynos4_iodesc0[] __initdata = {
+        {
+                .virtual        = (unsigned long)S5P_VA_SYSRAM,
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        },
+};
+static struct map_desc exynos4_iodesc1[] __initdata = {
+        {
+                .virtual        = (unsigned long)S5P_VA_SYSRAM,
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        },
+};
 static void exynos4_idle(void)
 {
        if (!need_resched())
@@ -143,6 +158,11 @@ void __init exynos4_map_io(void)
 {
        iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
+        if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
+                iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
+        else
+                iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
        /* initialize device information early */
        exynos4_default_sdhci0();
        exynos4_default_sdhci1();
@@ -170,24 +190,37 @@ void __init exynos4_init_clocks(int xtal)
        s3c24xx_register_baseclocks(xtal);
        s5p_register_clocks(xtal);
+        if (soc_is_exynos4210())
+                exynos4210_register_clocks();
+        else if (soc_is_exynos4212() || soc_is_exynos4412())
+                exynos4212_register_clocks();
        exynos4_register_clocks();
        exynos4_setup_clocks();
 }
-static void exynos4_gic_irq_eoi(struct irq_data *d)
+static void exynos4_gic_irq_fix_base(struct irq_data *d)
 {
        struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
        gic_data->cpu_base = S5P_VA_GIC_CPU +
-                            (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
+                            (gic_bank_offset * smp_processor_id());
+        gic_data->dist_base = S5P_VA_GIC_DIST +
+                            (gic_bank_offset * smp_processor_id());
 }
 void __init exynos4_init_irq(void)
 {
        int irq;
-        gic_init(0, IRQ_SPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+        gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
-        gic_arch_extn.irq_eoi = exynos4_gic_irq_eoi;
+        gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+        gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
+        gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
+        gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;
        for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
@@ -223,7 +256,11 @@ static int __init exynos4_l2x0_cache_init(void)
 {
        /* TAG, Data Latency Control: 2cycle */
        __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
-        __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
+        if (soc_is_exynos4210())
+                __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
+        else if (soc_is_exynos4212() || soc_is_exynos4412())
+                __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
        /* L2X0 Prefetch Control */
        __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
diff --git a/arch/arm/mach-exynos4/hotplug.c b/arch/arm/mach-exynos4/hotplug.c
index 7490789784c9..da70e7e39937 100644
--- a/arch/arm/mach-exynos4/hotplug.c
+++ b/arch/arm/mach-exynos4/hotplug.c
@@ -75,7 +75,7 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
                    :
                    : "memory", "cc");
-                if (pen_release == cpu) {
+                if (pen_release == cpu_logical_map(cpu)) {
                        /*
                         * OK, proper wakeup, we're done
                         */
diff --git a/arch/arm/mach-exynos4/include/mach/entry-macro.S b/arch/arm/mach-exynos4/include/mach/entry-macro.S
index 006a4f4c65c6..f5e9fd8e37b4 100644
--- a/arch/arm/mach-exynos4/include/mach/entry-macro.S
+++ b/arch/arm/mach-exynos4/include/mach/entry-macro.S
@@ -17,12 +17,25 @@
                .endm
                .macro  get_irqnr_preamble, base, tmp
-                ldr     \base, =gic_cpu_base_addr
+                mov     \tmp, #0
+                mrc     p15, 0, \base, c0, c0, 5
+                and     \base, \base, #3
+                cmp     \base, #0
+                beq     1f
+                ldr     \tmp, =gic_bank_offset
+                ldr     \tmp, [\tmp]
+                cmp     \base, #1
+                beq     1f
+                cmp     \base, #2
+                addeq   \tmp, \tmp, \tmp
+                addne   \tmp, \tmp, \tmp, LSL #1
+1:              ldr     \base, =gic_cpu_base_addr
                ldr     \base, [\base]
-                mrc     p15, 0, \tmp, c0, c0, 5
+                add     \base, \base, \tmp
-                and     \tmp, \tmp, #3
-                cmp     \tmp, #1
-                addeq   \base, \base, #EXYNOS4_GIC_BANK_OFFSET
                .endm
                .macro  arch_ret_to_user, tmp1, tmp2
diff --git a/arch/arm/mach-exynos4/include/mach/exynos4-clock.h b/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
new file mode 100644
index 000000000000..a07fcbf55251
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
@@ -0,0 +1,43 @@
+/*
+ * linux/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Header file for exynos4 clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H __FILE__
+#include <linux/clk.h>
+extern struct clk clk_sclk_hdmi27m;
+extern struct clk clk_sclk_usbphy0;
+extern struct clk clk_sclk_usbphy1;
+extern struct clk clk_sclk_hdmiphy;
+extern struct clksrc_clk clk_sclk_apll;
+extern struct clksrc_clk clk_mout_mpll;
+extern struct clksrc_clk clk_aclk_133;
+extern struct clksrc_clk clk_mout_epll;
+extern struct clksrc_clk clk_sclk_vpll;
+extern struct clk *clkset_corebus_list[];
+extern struct clksrc_sources clkset_mout_corebus;
+extern struct clk *clkset_aclk_top_list[];
+extern struct clksrc_sources clkset_aclk;
+extern struct clk *clkset_group_list[];
+extern struct clksrc_sources clkset_group;
+extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos4/include/mach/irqs.h b/arch/arm/mach-exynos4/include/mach/irqs.h
index f8952f8f3757..2d3f6bcd9bc0 100644
--- a/arch/arm/mach-exynos4/include/mach/irqs.h
+++ b/arch/arm/mach-exynos4/include/mach/irqs.h
@@ -19,6 +19,8 @@
 #define IRQ_PPI(x)              S5P_IRQ(x+16)
+#define IRQ_MCT_LOCALTIMER      IRQ_PPI(12)
 /* SPI: Shared Peripheral Interrupt */
 #define IRQ_SPI(x)              S5P_IRQ(x+32)
diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos4/include/mach/map.h
index d32296dc65e2..9f97eb8499ee 100644
--- a/arch/arm/mach-exynos4/include/mach/map.h
+++ b/arch/arm/mach-exynos4/include/mach/map.h
@@ -23,7 +23,8 @@
 #include <plat/map-s5p.h>
-#define EXYNOS4_PA_SYSRAM               0x02020000
+#define EXYNOS4_PA_SYSRAM0              0x02025000
+#define EXYNOS4_PA_SYSRAM1              0x02020000
 #define EXYNOS4_PA_FIMC0                0x11800000
 #define EXYNOS4_PA_FIMC1                0x11810000
@@ -61,7 +62,6 @@
 #define EXYNOS4_PA_GIC_CPU              0x10480000
 #define EXYNOS4_PA_GIC_DIST             0x10490000
-#define EXYNOS4_GIC_BANK_OFFSET         0x8000
 #define EXYNOS4_PA_COREPERI             0x10500000
 #define EXYNOS4_PA_TWD                  0x10500600
diff --git a/arch/arm/mach-exynos4/include/mach/regs-clock.h b/arch/arm/mach-exynos4/include/mach/regs-clock.h
index d493fdb422ff..6c37ebe94829 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h
@@ -13,6 +13,7 @@
 #ifndef __ASM_ARCH_REGS_CLOCK_H
 #define __ASM_ARCH_REGS_CLOCK_H __FILE__
+#include <plat/cpu.h>
 #include <mach/map.h>
 #define S5P_CLKREG(x)                   (S5P_VA_CMU + (x))
@@ -41,12 +42,20 @@
 #define S5P_CLKSRC_G3D                  S5P_CLKREG(0x0C22C)
 #define S5P_CLKSRC_IMAGE                S5P_CLKREG(0x0C230)
 #define S5P_CLKSRC_LCD0                 S5P_CLKREG(0x0C234)
-#define S5P_CLKSRC_LCD1                 S5P_CLKREG(0x0C238)
 #define S5P_CLKSRC_MAUDIO               S5P_CLKREG(0x0C23C)
 #define S5P_CLKSRC_FSYS                 S5P_CLKREG(0x0C240)
 #define S5P_CLKSRC_PERIL0               S5P_CLKREG(0x0C250)
 #define S5P_CLKSRC_PERIL1               S5P_CLKREG(0x0C254)
+#define S5P_CLKSRC_MASK_TOP             S5P_CLKREG(0x0C310)
+#define S5P_CLKSRC_MASK_CAM             S5P_CLKREG(0x0C320)
+#define S5P_CLKSRC_MASK_TV              S5P_CLKREG(0x0C324)
+#define S5P_CLKSRC_MASK_LCD0            S5P_CLKREG(0x0C334)
+#define S5P_CLKSRC_MASK_MAUDIO          S5P_CLKREG(0x0C33C)
+#define S5P_CLKSRC_MASK_FSYS            S5P_CLKREG(0x0C340)
+#define S5P_CLKSRC_MASK_PERIL0          S5P_CLKREG(0x0C350)
+#define S5P_CLKSRC_MASK_PERIL1          S5P_CLKREG(0x0C354)
 #define S5P_CLKDIV_TOP                  S5P_CLKREG(0x0C510)
 #define S5P_CLKDIV_CAM                  S5P_CLKREG(0x0C520)
 #define S5P_CLKDIV_TV                   S5P_CLKREG(0x0C524)
@@ -54,7 +63,6 @@
 #define S5P_CLKDIV_G3D                  S5P_CLKREG(0x0C52C)
 #define S5P_CLKDIV_IMAGE                S5P_CLKREG(0x0C530)
 #define S5P_CLKDIV_LCD0                 S5P_CLKREG(0x0C534)
-#define S5P_CLKDIV_LCD1                 S5P_CLKREG(0x0C538)
 #define S5P_CLKDIV_MAUDIO               S5P_CLKREG(0x0C53C)
 #define S5P_CLKDIV_FSYS0                S5P_CLKREG(0x0C540)
 #define S5P_CLKDIV_FSYS1                S5P_CLKREG(0x0C544)
@@ -68,16 +76,6 @@
 #define S5P_CLKDIV_PERIL5               S5P_CLKREG(0x0C564)
 #define S5P_CLKDIV2_RATIO               S5P_CLKREG(0x0C580)
-#define S5P_CLKSRC_MASK_TOP             S5P_CLKREG(0x0C310)
-#define S5P_CLKSRC_MASK_CAM             S5P_CLKREG(0x0C320)
-#define S5P_CLKSRC_MASK_TV              S5P_CLKREG(0x0C324)
-#define S5P_CLKSRC_MASK_LCD0            S5P_CLKREG(0x0C334)
-#define S5P_CLKSRC_MASK_LCD1            S5P_CLKREG(0x0C338)
-#define S5P_CLKSRC_MASK_MAUDIO          S5P_CLKREG(0x0C33C)
-#define S5P_CLKSRC_MASK_FSYS            S5P_CLKREG(0x0C340)
-#define S5P_CLKSRC_MASK_PERIL0          S5P_CLKREG(0x0C350)
-#define S5P_CLKSRC_MASK_PERIL1          S5P_CLKREG(0x0C354)
 #define S5P_CLKDIV_STAT_TOP             S5P_CLKREG(0x0C610)
 #define S5P_CLKGATE_SCLKCAM             S5P_CLKREG(0x0C820)
@@ -85,13 +83,20 @@
 #define S5P_CLKGATE_IP_TV               S5P_CLKREG(0x0C924)
 #define S5P_CLKGATE_IP_MFC              S5P_CLKREG(0x0C928)
 #define S5P_CLKGATE_IP_G3D              S5P_CLKREG(0x0C92C)
-#define S5P_CLKGATE_IP_IMAGE            S5P_CLKREG(0x0C930)
+#define S5P_CLKGATE_IP_IMAGE            (soc_is_exynos4210() ? \
+                                        S5P_CLKREG(0x0C930) : \
+                                        S5P_CLKREG(0x04930))
+#define S5P_CLKGATE_IP_IMAGE_4210       S5P_CLKREG(0x0C930)
+#define S5P_CLKGATE_IP_IMAGE_4212       S5P_CLKREG(0x04930)
 #define S5P_CLKGATE_IP_LCD0             S5P_CLKREG(0x0C934)
-#define S5P_CLKGATE_IP_LCD1             S5P_CLKREG(0x0C938)
 #define S5P_CLKGATE_IP_FSYS             S5P_CLKREG(0x0C940)
 #define S5P_CLKGATE_IP_GPS              S5P_CLKREG(0x0C94C)
 #define S5P_CLKGATE_IP_PERIL            S5P_CLKREG(0x0C950)
-#define S5P_CLKGATE_IP_PERIR            S5P_CLKREG(0x0C960)
+#define S5P_CLKGATE_IP_PERIR            (soc_is_exynos4210() ? \
+                                        S5P_CLKREG(0x0C960) : \
+                                        S5P_CLKREG(0x08960))
+#define S5P_CLKGATE_IP_PERIR_4210       S5P_CLKREG(0x0C960)
+#define S5P_CLKGATE_IP_PERIR_4212       S5P_CLKREG(0x08960)
 #define S5P_CLKGATE_BLOCK               S5P_CLKREG(0x0C970)
 #define S5P_CLKSRC_MASK_DMC             S5P_CLKREG(0x10300)
@@ -102,11 +107,17 @@
 #define S5P_CLKGATE_IP_DMC              S5P_CLKREG(0x10900)
 #define S5P_APLL_LOCK                   S5P_CLKREG(0x14000)
-#define S5P_MPLL_LOCK                   S5P_CLKREG(0x14004)
+#define S5P_MPLL_LOCK                   (soc_is_exynos4210() ? \
+                                        S5P_CLKREG(0x14004) :  \
+                                        S5P_CLKREG(0x10008))
 #define S5P_APLL_CON0                   S5P_CLKREG(0x14100)
 #define S5P_APLL_CON1                   S5P_CLKREG(0x14104)
-#define S5P_MPLL_CON0                   S5P_CLKREG(0x14108)
+#define S5P_MPLL_CON0                   (soc_is_exynos4210() ? \
-#define S5P_MPLL_CON1                   S5P_CLKREG(0x1410C)
+                                        S5P_CLKREG(0x14108) : \
+                                        S5P_CLKREG(0x10108))
+#define S5P_MPLL_CON1                   (soc_is_exynos4210() ? \
+                                        S5P_CLKREG(0x1410C) : \
+                                        S5P_CLKREG(0x1010C))
 #define S5P_CLKSRC_CPU                  S5P_CLKREG(0x14200)
 #define S5P_CLKMUX_STATCPU              S5P_CLKREG(0x14400)
@@ -183,6 +194,13 @@
 #define S5P_CLKDIV_BUS_GPLR_SHIFT       (4)
 #define S5P_CLKDIV_BUS_GPLR_MASK        (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT)
+/* Only for EXYNOS4210 */
+#define S5P_CLKSRC_LCD1                 S5P_CLKREG(0x0C238)
+#define S5P_CLKSRC_MASK_LCD1            S5P_CLKREG(0x0C338)
+#define S5P_CLKDIV_LCD1                 S5P_CLKREG(0x0C538)
+#define S5P_CLKGATE_IP_LCD1             S5P_CLKREG(0x0C938)
 /* Compatibility defines and inclusion */
 #include <mach/regs-pmu.h>
diff --git a/arch/arm/mach-exynos4/include/mach/regs-mct.h b/arch/arm/mach-exynos4/include/mach/regs-mct.h
index ca9c8434b023..80dd02ad6d61 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-mct.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-mct.h
@@ -31,8 +31,9 @@
 #define EXYNOS4_MCT_G_INT_ENB           EXYNOS4_MCTREG(0x248)
 #define EXYNOS4_MCT_G_WSTAT             EXYNOS4_MCTREG(0x24C)
-#define EXYNOS4_MCT_L0_BASE             EXYNOS4_MCTREG(0x300)
+#define _EXYNOS4_MCT_L_BASE             EXYNOS4_MCTREG(0x300)
-#define EXYNOS4_MCT_L1_BASE             EXYNOS4_MCTREG(0x400)
+#define EXYNOS4_MCT_L_BASE(x)           (_EXYNOS4_MCT_L_BASE + (0x100 * x))
+#define EXYNOS4_MCT_L_MASK              (0xffffff00)
 #define MCT_L_TCNTB_OFFSET              (0x00)
 #define MCT_L_ICNTB_OFFSET              (0x08)
diff --git a/arch/arm/mach-exynos4/mach-origen.c b/arch/arm/mach-exynos4/mach-origen.c
new file mode 100644
index 000000000000..b5f6f38557c9
--- /dev/null
+++ b/arch/arm/mach-exynos4/mach-origen.c
@@ -0,0 +1,108 @@
+/* linux/arch/arm/mach-exynos4/mach-origen.c
+ *
+ * Copyright (c) 2011 Insignal Co., Ltd.
+ *              http://www.insignal.co.kr/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/serial_core.h>
+#include <linux/gpio.h>
+#include <linux/mmc/host.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/input.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <plat/regs-serial.h>
+#include <plat/exynos4.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/sdhci.h>
+#include <plat/iic.h>
+#include <mach/map.h>
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define ORIGEN_UCON_DEFAULT     (S3C2410_UCON_TXILEVEL |        \
+                                 S3C2410_UCON_RXILEVEL |        \
+                                 S3C2410_UCON_TXIRQMODE |       \
+                                 S3C2410_UCON_RXIRQMODE |       \
+                                 S3C2410_UCON_RXFIFO_TOI |      \
+                                 S3C2443_UCON_RXERR_IRQEN)
+#define ORIGEN_ULCON_DEFAULT    S3C2410_LCON_CS8
+#define ORIGEN_UFCON_DEFAULT    (S3C2410_UFCON_FIFOMODE |       \
+                                 S5PV210_UFCON_TXTRIG4 |        \
+                                 S5PV210_UFCON_RXTRIG4)
+static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = {
+        [0] = {
+                .hwport         = 0,
+                .flags          = 0,
+                .ucon           = ORIGEN_UCON_DEFAULT,
+                .ulcon          = ORIGEN_ULCON_DEFAULT,
+                .ufcon          = ORIGEN_UFCON_DEFAULT,
+        },
+        [1] = {
+                .hwport         = 1,
+                .flags          = 0,
+                .ucon           = ORIGEN_UCON_DEFAULT,
+                .ulcon          = ORIGEN_ULCON_DEFAULT,
+                .ufcon          = ORIGEN_UFCON_DEFAULT,
+        },
+        [2] = {
+                .hwport         = 2,
+                .flags          = 0,
+                .ucon           = ORIGEN_UCON_DEFAULT,
+                .ulcon          = ORIGEN_ULCON_DEFAULT,
+                .ufcon          = ORIGEN_UFCON_DEFAULT,
+        },
+        [3] = {
+                .hwport         = 3,
+                .flags          = 0,
+                .ucon           = ORIGEN_UCON_DEFAULT,
+                .ulcon          = ORIGEN_ULCON_DEFAULT,
+                .ufcon          = ORIGEN_UFCON_DEFAULT,
+        },
+};
+static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = {
+        .cd_type                = S3C_SDHCI_CD_GPIO,
+        .ext_cd_gpio            = EXYNOS4_GPK2(2),
+        .ext_cd_gpio_invert     = 1,
+        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+static struct platform_device *origen_devices[] __initdata = {
+        &s3c_device_hsmmc2,
+        &s3c_device_rtc,
+        &s3c_device_wdt,
+};
+static void __init origen_map_io(void)
+{
+        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+        s3c24xx_init_clocks(24000000);
+        s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
+}
+static void __init origen_machine_init(void)
+{
+        s3c_sdhci2_set_platdata(&origen_hsmmc2_pdata);
+        platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices));
+}
+MACHINE_START(ORIGEN, "ORIGEN")
+        /* Maintainer: JeongHyeon Kim <jhkim@insignal.co.kr> */
+        .atag_offset    = 0x100,
+        .init_irq       = exynos4_init_irq,
+        .map_io         = origen_map_io,
+        .init_machine   = origen_machine_init,
+        .timer          = &exynos4_timer,
+MACHINE_END
diff --git a/arch/arm/mach-exynos4/mach-smdk4x12.c b/arch/arm/mach-exynos4/mach-smdk4x12.c
new file mode 100644
index 000000000000..fcf2e0e23d53
--- /dev/null
+++ b/arch/arm/mach-exynos4/mach-smdk4x12.c
@@ -0,0 +1,302 @@
+/*
+ * linux/arch/arm/mach-exynos4/mach-smdk4x12.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/input.h>
+#include <linux/io.h>
+#include <linux/mfd/max8997.h>
+#include <linux/mmc/host.h>
+#include <linux/platform_device.h>
+#include <linux/pwm_backlight.h>
+#include <linux/regulator/machine.h>
+#include <linux/serial_core.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <plat/backlight.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/exynos4.h>
+#include <plat/gpio-cfg.h>
+#include <plat/iic.h>
+#include <plat/keypad.h>
+#include <plat/regs-serial.h>
+#include <plat/sdhci.h>
+#include <mach/map.h>
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define SMDK4X12_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
+                                 S3C2410_UCON_RXILEVEL |        \
+                                 S3C2410_UCON_TXIRQMODE |       \
+                                 S3C2410_UCON_RXIRQMODE |       \
+                                 S3C2410_UCON_RXFIFO_TOI |      \
+                                 S3C2443_UCON_RXERR_IRQEN)
+#define SMDK4X12_ULCON_DEFAULT  S3C2410_LCON_CS8
+#define SMDK4X12_UFCON_DEFAULT  (S3C2410_UFCON_FIFOMODE |       \
+                                 S5PV210_UFCON_TXTRIG4 |        \
+                                 S5PV210_UFCON_RXTRIG4)
+static struct s3c2410_uartcfg smdk4x12_uartcfgs[] __initdata = {
+        [0] = {
+                .hwport         = 0,
+                .flags          = 0,
+                .ucon           = SMDK4X12_UCON_DEFAULT,
+                .ulcon          = SMDK4X12_ULCON_DEFAULT,
+                .ufcon          = SMDK4X12_UFCON_DEFAULT,
+        },
+        [1] = {
+                .hwport         = 1,
+                .flags          = 0,
+                .ucon           = SMDK4X12_UCON_DEFAULT,
+                .ulcon          = SMDK4X12_ULCON_DEFAULT,
+                .ufcon          = SMDK4X12_UFCON_DEFAULT,
+        },
+        [2] = {
+                .hwport         = 2,
+                .flags          = 0,
+                .ucon           = SMDK4X12_UCON_DEFAULT,
+                .ulcon          = SMDK4X12_ULCON_DEFAULT,
+                .ufcon          = SMDK4X12_UFCON_DEFAULT,
+        },
+        [3] = {
+                .hwport         = 3,
+                .flags          = 0,
+                .ucon           = SMDK4X12_UCON_DEFAULT,
+                .ulcon          = SMDK4X12_ULCON_DEFAULT,
+                .ufcon          = SMDK4X12_UFCON_DEFAULT,
+        },
+};
+static struct s3c_sdhci_platdata smdk4x12_hsmmc2_pdata __initdata = {
+        .cd_type                = S3C_SDHCI_CD_INTERNAL,
+        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
+        .max_width              = 8,
+        .host_caps              = MMC_CAP_8_BIT_DATA,
+#endif
+};
+static struct s3c_sdhci_platdata smdk4x12_hsmmc3_pdata __initdata = {
+        .cd_type                = S3C_SDHCI_CD_INTERNAL,
+        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+static struct regulator_consumer_supply max8997_buck1 =
+        REGULATOR_SUPPLY("vdd_arm", NULL);
+static struct regulator_consumer_supply max8997_buck2 =
+        REGULATOR_SUPPLY("vdd_int", NULL);
+static struct regulator_consumer_supply max8997_buck3 =
+        REGULATOR_SUPPLY("vdd_g3d", NULL);
+static struct regulator_init_data max8997_buck1_data = {
+        .constraints    = {
+                .name           = "VDD_ARM_SMDK4X12",
+                .min_uV         = 925000,
+                .max_uV         = 1350000,
+                .always_on      = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &max8997_buck1,
+};
+static struct regulator_init_data max8997_buck2_data = {
+        .constraints    = {
+                .name           = "VDD_INT_SMDK4X12",
+                .min_uV         = 950000,
+                .max_uV         = 1150000,
+                .always_on      = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &max8997_buck2,
+};
+static struct regulator_init_data max8997_buck3_data = {
+        .constraints    = {
+                .name           = "VDD_G3D_SMDK4X12",
+                .min_uV         = 950000,
+                .max_uV         = 1150000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                  REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &max8997_buck3,
+};
+static struct max8997_regulator_data smdk4x12_max8997_regulators[] = {
+        { MAX8997_BUCK1, &max8997_buck1_data },
+        { MAX8997_BUCK2, &max8997_buck2_data },
+        { MAX8997_BUCK3, &max8997_buck3_data },
+};
+static struct max8997_platform_data smdk4x12_max8997_pdata = {
+        .num_regulators = ARRAY_SIZE(smdk4x12_max8997_regulators),
+        .regulators     = smdk4x12_max8997_regulators,
+        .buck1_voltage[0] = 1100000,    /* 1.1V */
+        .buck1_voltage[1] = 1100000,    /* 1.1V */
+        .buck1_voltage[2] = 1100000,    /* 1.1V */
+        .buck1_voltage[3] = 1100000,    /* 1.1V */
+        .buck1_voltage[4] = 1100000,    /* 1.1V */
+        .buck1_voltage[5] = 1100000,    /* 1.1V */
+        .buck1_voltage[6] = 1000000,    /* 1.0V */
+        .buck1_voltage[7] = 950000,     /* 0.95V */
+        .buck2_voltage[0] = 1100000,    /* 1.1V */
+        .buck2_voltage[1] = 1000000,    /* 1.0V */
+        .buck2_voltage[2] = 950000,     /* 0.95V */
+        .buck2_voltage[3] = 900000,     /* 0.9V */
+        .buck2_voltage[4] = 1100000,    /* 1.1V */
+        .buck2_voltage[5] = 1000000,    /* 1.0V */
+        .buck2_voltage[6] = 950000,     /* 0.95V */
+        .buck2_voltage[7] = 900000,     /* 0.9V */
+        .buck5_voltage[0] = 1100000,    /* 1.1V */
+        .buck5_voltage[1] = 1100000,    /* 1.1V */
+        .buck5_voltage[2] = 1100000,    /* 1.1V */
+        .buck5_voltage[3] = 1100000,    /* 1.1V */
+        .buck5_voltage[4] = 1100000,    /* 1.1V */
+        .buck5_voltage[5] = 1100000,    /* 1.1V */
+        .buck5_voltage[6] = 1100000,    /* 1.1V */
+        .buck5_voltage[7] = 1100000,    /* 1.1V */
+};
+static struct i2c_board_info smdk4x12_i2c_devs0[] __initdata = {
+        {
+                I2C_BOARD_INFO("max8997", 0x66),
+                .platform_data  = &smdk4x12_max8997_pdata,
+        }
+};
+static struct i2c_board_info smdk4x12_i2c_devs1[] __initdata = {
+        { I2C_BOARD_INFO("wm8994", 0x1a), }
+};
+static struct i2c_board_info smdk4x12_i2c_devs3[] __initdata = {
+        /* nothing here yet */
+};
+static struct i2c_board_info smdk4x12_i2c_devs7[] __initdata = {
+        /* nothing here yet */
+};
+static struct samsung_bl_gpio_info smdk4x12_bl_gpio_info = {
+        .no = EXYNOS4_GPD0(1),
+        .func = S3C_GPIO_SFN(2),
+};
+static struct platform_pwm_backlight_data smdk4x12_bl_data = {
+        .pwm_id = 1,
+        .pwm_period_ns  = 1000,
+};
+static uint32_t smdk4x12_keymap[] __initdata = {
+        /* KEY(row, col, keycode) */
+        KEY(1, 0, KEY_D), KEY(1, 1, KEY_A), KEY(1, 2, KEY_B),
+        KEY(1, 3, KEY_E), KEY(1, 4, KEY_C)
+};
+static struct matrix_keymap_data smdk4x12_keymap_data __initdata = {
+        .keymap         = smdk4x12_keymap,
+        .keymap_size    = ARRAY_SIZE(smdk4x12_keymap),
+};
+static struct samsung_keypad_platdata smdk4x12_keypad_data __initdata = {
+        .keymap_data    = &smdk4x12_keymap_data,
+        .rows           = 2,
+        .cols           = 5,
+};
+static struct platform_device *smdk4x12_devices[] __initdata = {
+        &s3c_device_hsmmc2,
+        &s3c_device_hsmmc3,
+        &s3c_device_i2c0,
+        &s3c_device_i2c1,
+        &s3c_device_i2c3,
+        &s3c_device_i2c7,
+        &s3c_device_rtc,
+        &s3c_device_wdt,
+        &samsung_device_keypad,
+};
+static void __init smdk4x12_map_io(void)
+{
+        clk_xusbxti.rate = 24000000;
+        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+        s3c24xx_init_clocks(clk_xusbxti.rate);
+        s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
+}
+static void __init smdk4x12_machine_init(void)
+{
+        s3c_i2c0_set_platdata(NULL);
+        i2c_register_board_info(0, smdk4x12_i2c_devs0,
+                                ARRAY_SIZE(smdk4x12_i2c_devs0));
+        s3c_i2c1_set_platdata(NULL);
+        i2c_register_board_info(1, smdk4x12_i2c_devs1,
+                                ARRAY_SIZE(smdk4x12_i2c_devs1));
+        s3c_i2c3_set_platdata(NULL);
+        i2c_register_board_info(3, smdk4x12_i2c_devs3,
+                                ARRAY_SIZE(smdk4x12_i2c_devs3));
+        s3c_i2c7_set_platdata(NULL);
+        i2c_register_board_info(7, smdk4x12_i2c_devs7,
+                                ARRAY_SIZE(smdk4x12_i2c_devs7));
+        samsung_bl_set(&smdk4x12_bl_gpio_info, &smdk4x12_bl_data);
+        samsung_keypad_set_platdata(&smdk4x12_keypad_data);
+        s3c_sdhci2_set_platdata(&smdk4x12_hsmmc2_pdata);
+        s3c_sdhci3_set_platdata(&smdk4x12_hsmmc3_pdata);
+        platform_add_devices(smdk4x12_devices, ARRAY_SIZE(smdk4x12_devices));
+}
+MACHINE_START(SMDK4212, "SMDK4212")
+        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+        .atag_offset    = 0x100,
+        .init_irq       = exynos4_init_irq,
+        .map_io         = smdk4x12_map_io,
+        .init_machine   = smdk4x12_machine_init,
+        .timer          = &exynos4_timer,
+MACHINE_END
+MACHINE_START(SMDK4412, "SMDK4412")
+        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+        /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
+        .atag_offset    = 0x100,
+        .init_irq       = exynos4_init_irq,
+        .map_io         = smdk4x12_map_io,
+        .init_machine   = smdk4x12_machine_init,
+        .timer          = &exynos4_timer,
+MACHINE_END
diff --git a/arch/arm/mach-exynos4/mach-smdkc210.c b/arch/arm/mach-exynos4/mach-smdkc210.c
deleted file mode 100644
index b24ddd7ad8fe..000000000000
--- a/arch/arm/mach-exynos4/mach-smdkc210.c
+++ /dev/null
@@ -1,309 +0,0 @@
-/* linux/arch/arm/mach-exynos4/mach-smdkc210.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/serial_core.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/lcd.h>
-#include <linux/mmc/host.h>
-#include <linux/platform_device.h>
-#include <linux/smsc911x.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
-#include <linux/pwm_backlight.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <video/platform_lcd.h>
-#include <plat/regs-serial.h>
-#include <plat/regs-srom.h>
-#include <plat/regs-fb-v4.h>
-#include <plat/exynos4.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/fb.h>
-#include <plat/sdhci.h>
-#include <plat/iic.h>
-#include <plat/pd.h>
-#include <plat/gpio-cfg.h>
-#include <plat/backlight.h>
-#include <mach/map.h>
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define SMDKC210_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
-                                 S3C2410_UCON_RXILEVEL |        \
-                                 S3C2410_UCON_TXIRQMODE |       \
-                                 S3C2410_UCON_RXIRQMODE |       \
-                                 S3C2410_UCON_RXFIFO_TOI |      \
-                                 S3C2443_UCON_RXERR_IRQEN)
-#define SMDKC210_ULCON_DEFAULT  S3C2410_LCON_CS8
-#define SMDKC210_UFCON_DEFAULT  (S3C2410_UFCON_FIFOMODE |       \
-                                 S5PV210_UFCON_TXTRIG4 |        \
-                                 S5PV210_UFCON_RXTRIG4)
-static struct s3c2410_uartcfg smdkc210_uartcfgs[] __initdata = {
-        [0] = {
-                .hwport         = 0,
-                .flags          = 0,
-                .ucon           = SMDKC210_UCON_DEFAULT,
-                .ulcon          = SMDKC210_ULCON_DEFAULT,
-                .ufcon          = SMDKC210_UFCON_DEFAULT,
-        },
-        [1] = {
-                .hwport         = 1,
-                .flags          = 0,
-                .ucon           = SMDKC210_UCON_DEFAULT,
-                .ulcon          = SMDKC210_ULCON_DEFAULT,
-                .ufcon          = SMDKC210_UFCON_DEFAULT,
-        },
-        [2] = {
-                .hwport         = 2,
-                .flags          = 0,
-                .ucon           = SMDKC210_UCON_DEFAULT,
-                .ulcon          = SMDKC210_ULCON_DEFAULT,
-                .ufcon          = SMDKC210_UFCON_DEFAULT,
-        },
-        [3] = {
-                .hwport         = 3,
-                .flags          = 0,
-                .ucon           = SMDKC210_UCON_DEFAULT,
-                .ulcon          = SMDKC210_ULCON_DEFAULT,
-                .ufcon          = SMDKC210_UFCON_DEFAULT,
-        },
-};
-static struct s3c_sdhci_platdata smdkc210_hsmmc0_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = EXYNOS4_GPK0(2),
-        .ext_cd_gpio_invert     = 1,
-        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
-        .max_width              = 8,
-        .host_caps              = MMC_CAP_8_BIT_DATA,
-#endif
-};
-static struct s3c_sdhci_platdata smdkc210_hsmmc1_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = EXYNOS4_GPK0(2),
-        .ext_cd_gpio_invert     = 1,
-        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-};
-static struct s3c_sdhci_platdata smdkc210_hsmmc2_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = EXYNOS4_GPK2(2),
-        .ext_cd_gpio_invert     = 1,
-        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
-        .max_width              = 8,
-        .host_caps              = MMC_CAP_8_BIT_DATA,
-#endif
-};
-static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = EXYNOS4_GPK2(2),
-        .ext_cd_gpio_invert     = 1,
-        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-};
-static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
-                                   unsigned int power)
-{
-        if (power) {
-#if !defined(CONFIG_BACKLIGHT_PWM)
-                gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
-                gpio_free(EXYNOS4_GPD0(1));
-#endif
-                /* fire nRESET on power up */
-                gpio_request(EXYNOS4_GPX0(6), "GPX0");
-                gpio_direction_output(EXYNOS4_GPX0(6), 1);
-                mdelay(100);
-                gpio_set_value(EXYNOS4_GPX0(6), 0);
-                mdelay(10);
-                gpio_set_value(EXYNOS4_GPX0(6), 1);
-                mdelay(10);
-                gpio_free(EXYNOS4_GPX0(6));
-        } else {
-#if !defined(CONFIG_BACKLIGHT_PWM)
-                gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
-                gpio_free(EXYNOS4_GPD0(1));
-#endif
-        }
-}
-static struct plat_lcd_data smdkc210_lcd_lte480wv_data = {
-        .set_power              = lcd_lte480wv_set_power,
-};
-static struct platform_device smdkc210_lcd_lte480wv = {
-        .name                   = "platform-lcd",
-        .dev.parent             = &s5p_device_fimd0.dev,
-        .dev.platform_data      = &smdkc210_lcd_lte480wv_data,
-};
-static struct s3c_fb_pd_win smdkc210_fb_win0 = {
-        .win_mode = {
-                .left_margin    = 13,
-                .right_margin   = 8,
-                .upper_margin   = 7,
-                .lower_margin   = 5,
-                .hsync_len      = 3,
-                .vsync_len      = 1,
-                .xres           = 800,
-                .yres           = 480,
-        },
-        .max_bpp                = 32,
-        .default_bpp            = 24,
-};
-static struct s3c_fb_platdata smdkc210_lcd0_pdata __initdata = {
-        .win[0]         = &smdkc210_fb_win0,
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-        .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
-};
-static struct resource smdkc210_smsc911x_resources[] = {
-        [0] = {
-                .start  = EXYNOS4_PA_SROM_BANK(1),
-                .end    = EXYNOS4_PA_SROM_BANK(1) + SZ_64K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_EINT(5),
-                .end    = IRQ_EINT(5),
-                .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
-        },
-};
-static struct smsc911x_platform_config smsc9215_config = {
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
-        .flags          = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
-        .phy_interface  = PHY_INTERFACE_MODE_MII,
-        .mac            = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
-};
-static struct platform_device smdkc210_smsc911x = {
-        .name           = "smsc911x",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(smdkc210_smsc911x_resources),
-        .resource       = smdkc210_smsc911x_resources,
-        .dev            = {
-                .platform_data  = &smsc9215_config,
-        },
-};
-static struct i2c_board_info i2c_devs1[] __initdata = {
-        {I2C_BOARD_INFO("wm8994", 0x1a),},
-};
-static struct platform_device *smdkc210_devices[] __initdata = {
-        &s3c_device_hsmmc0,
-        &s3c_device_hsmmc1,
-        &s3c_device_hsmmc2,
-        &s3c_device_hsmmc3,
-        &s3c_device_i2c1,
-        &s3c_device_rtc,
-        &s3c_device_wdt,
-        &exynos4_device_ac97,
-        &exynos4_device_i2s0,
-        &exynos4_device_pd[PD_MFC],
-        &exynos4_device_pd[PD_G3D],
-        &exynos4_device_pd[PD_LCD0],
-        &exynos4_device_pd[PD_LCD1],
-        &exynos4_device_pd[PD_CAM],
-        &exynos4_device_pd[PD_TV],
-        &exynos4_device_pd[PD_GPS],
-        &exynos4_device_sysmmu,
-        &samsung_asoc_dma,
-        &s5p_device_fimd0,
-        &smdkc210_lcd_lte480wv,
-        &smdkc210_smsc911x,
-};
-static void __init smdkc210_smsc911x_init(void)
-{
-        u32 cs1;
-        /* configure nCS1 width to 16 bits */
-        cs1 = __raw_readl(S5P_SROM_BW) &
-                ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
-        cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
-                (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
-                (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
-                S5P_SROM_BW__NCS1__SHIFT;
-        __raw_writel(cs1, S5P_SROM_BW);
-        /* set timing for nCS1 suitable for ethernet chip */
-        __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
-                     (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
-                     (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
-                     (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
-                     (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
-                     (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
-                     (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
-}
-/* LCD Backlight data */
-static struct samsung_bl_gpio_info smdkc210_bl_gpio_info = {
-        .no = EXYNOS4_GPD0(1),
-        .func = S3C_GPIO_SFN(2),
-};
-static struct platform_pwm_backlight_data smdkc210_bl_data = {
-        .pwm_id = 1,
-        .pwm_period_ns  = 1000,
-};
-static void __init smdkc210_map_io(void)
-{
-        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
-        s3c24xx_init_clocks(24000000);
-        s3c24xx_init_uarts(smdkc210_uartcfgs, ARRAY_SIZE(smdkc210_uartcfgs));
-}
-static void __init smdkc210_machine_init(void)
-{
-        s3c_i2c1_set_platdata(NULL);
-        i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
-        smdkc210_smsc911x_init();
-        s3c_sdhci0_set_platdata(&smdkc210_hsmmc0_pdata);
-        s3c_sdhci1_set_platdata(&smdkc210_hsmmc1_pdata);
-        s3c_sdhci2_set_platdata(&smdkc210_hsmmc2_pdata);
-        s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata);
-        samsung_bl_set(&smdkc210_bl_gpio_info, &smdkc210_bl_data);
-        s5p_fimd0_set_platdata(&smdkc210_lcd0_pdata);
-        platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices));
-}
-MACHINE_START(SMDKC210, "SMDKC210")
-        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        .atag_offset    = 0x100,
-        .init_irq       = exynos4_init_irq,
-        .map_io         = smdkc210_map_io,
-        .init_machine   = smdkc210_machine_init,
-        .timer          = &exynos4_timer,
-MACHINE_END
diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c
index d90fcddbee1f..2c1a076c6a73 100644
--- a/arch/arm/mach-exynos4/mach-smdkv310.c
+++ b/arch/arm/mach-exynos4/mach-smdkv310.c
@@ -9,7 +9,9 @@
 */
 #include <linux/serial_core.h>
+#include <linux/delay.h>
 #include <linux/gpio.h>
+#include <linux/lcd.h>
 #include <linux/mmc/host.h>
 #include <linux/platform_device.h>
 #include <linux/smsc911x.h>
@@ -21,11 +23,14 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
+#include <video/platform_lcd.h>
 #include <plat/regs-serial.h>
 #include <plat/regs-srom.h>
+#include <plat/regs-fb-v4.h>
 #include <plat/exynos4.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
+#include <plat/fb.h>
 #include <plat/keypad.h>
 #include <plat/sdhci.h>
 #include <plat/iic.h>
@@ -112,6 +117,67 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 };
+static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
+                                   unsigned int power)
+{
+        if (power) {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+                gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
+                gpio_free(EXYNOS4_GPD0(1));
+#endif
+                /* fire nRESET on power up */
+                gpio_request(EXYNOS4_GPX0(6), "GPX0");
+                gpio_direction_output(EXYNOS4_GPX0(6), 1);
+                mdelay(100);
+                gpio_set_value(EXYNOS4_GPX0(6), 0);
+                mdelay(10);
+                gpio_set_value(EXYNOS4_GPX0(6), 1);
+                mdelay(10);
+                gpio_free(EXYNOS4_GPX0(6));
+        } else {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+                gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
+                gpio_free(EXYNOS4_GPD0(1));
+#endif
+        }
+}
+static struct plat_lcd_data smdkv310_lcd_lte480wv_data = {
+        .set_power              = lcd_lte480wv_set_power,
+};
+static struct platform_device smdkv310_lcd_lte480wv = {
+        .name                   = "platform-lcd",
+        .dev.parent             = &s5p_device_fimd0.dev,
+        .dev.platform_data      = &smdkv310_lcd_lte480wv_data,
+};
+static struct s3c_fb_pd_win smdkv310_fb_win0 = {
+        .win_mode = {
+                .left_margin    = 13,
+                .right_margin   = 8,
+                .upper_margin   = 7,
+                .lower_margin   = 5,
+                .hsync_len      = 3,
+                .vsync_len      = 1,
+                .xres           = 800,
+                .yres           = 480,
+        },
+        .max_bpp                = 32,
+        .default_bpp            = 24,
+};
+static struct s3c_fb_platdata smdkv310_lcd0_pdata __initdata = {
+        .win[0]         = &smdkv310_fb_win0,
+        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+        .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
+};
 static struct resource smdkv310_smsc911x_resources[] = {
        [0] = {
                .start  = EXYNOS4_PA_SROM_BANK(1),
@@ -188,6 +254,8 @@ static struct platform_device *smdkv310_devices[] __initdata = {
        &exynos4_device_sysmmu,
        &samsung_asoc_dma,
        &samsung_asoc_idma,
+        &s5p_device_fimd0,
+        &smdkv310_lcd_lte480wv,
        &smdkv310_smsc911x,
        &exynos4_device_ahci,
 };
@@ -248,6 +316,7 @@ static void __init smdkv310_machine_init(void)
        samsung_keypad_set_platdata(&smdkv310_keypad_data);
        samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data);
+        s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata);
        platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
 }
@@ -261,3 +330,12 @@ MACHINE_START(SMDKV310, "SMDKV310")
        .init_machine   = smdkv310_machine_init,
        .timer          = &exynos4_timer,
 MACHINE_END
+MACHINE_START(SMDKC210, "SMDKC210")
+        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+        .atag_offset    = 0x100,
+        .init_irq       = exynos4_init_irq,
+        .map_io         = smdkv310_map_io,
+        .init_machine   = smdkv310_machine_init,
+        .timer          = &exynos4_timer,
+MACHINE_END
diff --git a/arch/arm/mach-exynos4/mct.c b/arch/arm/mach-exynos4/mct.c
index 582b874aab0e..f191608b28d6 100644
--- a/arch/arm/mach-exynos4/mct.c
+++ b/arch/arm/mach-exynos4/mct.c
@@ -20,19 +20,31 @@
 #include <linux/delay.h>
 #include <linux/percpu.h>
+#include <asm/hardware/gic.h>
+#include <plat/cpu.h>
 #include <mach/map.h>
+#include <mach/irqs.h>
 #include <mach/regs-mct.h>
 #include <asm/mach/time.h>
+enum {
+        MCT_INT_SPI,
+        MCT_INT_PPI
+};
 static unsigned long clk_cnt_per_tick;
 static unsigned long clk_rate;
+static unsigned int mct_int_type;
 struct mct_clock_event_device {
        struct clock_event_device *evt;
        void __iomem *base;
+        char name[10];
 };
-struct mct_clock_event_device mct_tick[2];
+struct mct_clock_event_device mct_tick[NR_CPUS];
 static void exynos4_mct_write(unsigned int value, void *addr)
 {
@@ -42,57 +54,53 @@ static void exynos4_mct_write(unsigned int value, void *addr)
        __raw_writel(value, addr);
-        switch ((u32) addr) {
+        if (likely(addr >= EXYNOS4_MCT_L_BASE(0))) {
-        case (u32) EXYNOS4_MCT_G_TCON:
+                u32 base = (u32) addr & EXYNOS4_MCT_L_MASK;
-                stat_addr = EXYNOS4_MCT_G_WSTAT;
+                switch ((u32) addr & ~EXYNOS4_MCT_L_MASK) {
-                mask = 1 << 16;         /* G_TCON write status */
+                case (u32) MCT_L_TCON_OFFSET:
-                break;
+                        stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
-        case (u32) EXYNOS4_MCT_G_COMP0_L:
+                        mask = 1 << 3;          /* L_TCON write status */
-                stat_addr = EXYNOS4_MCT_G_WSTAT;
+                        break;
-                mask = 1 << 0;          /* G_COMP0_L write status */
+                case (u32) MCT_L_ICNTB_OFFSET:
-                break;
+                        stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
-        case (u32) EXYNOS4_MCT_G_COMP0_U:
+                        mask = 1 << 1;          /* L_ICNTB write status */
-                stat_addr = EXYNOS4_MCT_G_WSTAT;
+                        break;
-                mask = 1 << 1;          /* G_COMP0_U write status */
+                case (u32) MCT_L_TCNTB_OFFSET:
-                break;
+                        stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
-        case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
+                        mask = 1 << 0;          /* L_TCNTB write status */
-                stat_addr = EXYNOS4_MCT_G_WSTAT;
+                        break;
-                mask = 1 << 2;          /* G_COMP0_ADD_INCR write status */
+                default:
-                break;
+                        return;
-        case (u32) EXYNOS4_MCT_G_CNT_L:
+                }
-                stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
+        } else {
-                mask = 1 << 0;          /* G_CNT_L write status */
+                switch ((u32) addr) {
-                break;
+                case (u32) EXYNOS4_MCT_G_TCON:
-        case (u32) EXYNOS4_MCT_G_CNT_U:
+                        stat_addr = EXYNOS4_MCT_G_WSTAT;
-                stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
+                        mask = 1 << 16;         /* G_TCON write status */
-                mask = 1 << 1;          /* G_CNT_U write status */
+                        break;
-                break;
+                case (u32) EXYNOS4_MCT_G_COMP0_L:
-        case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCON_OFFSET):
+                        stat_addr = EXYNOS4_MCT_G_WSTAT;
-                stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
+                        mask = 1 << 0;          /* G_COMP0_L write status */
-                mask = 1 << 3;          /* L0_TCON write status */
+                        break;
-                break;
+                case (u32) EXYNOS4_MCT_G_COMP0_U:
-        case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCON_OFFSET):
+                        stat_addr = EXYNOS4_MCT_G_WSTAT;
-                stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
+                        mask = 1 << 1;          /* G_COMP0_U write status */
-                mask = 1 << 3;          /* L1_TCON write status */
+                        break;
-                break;
+                case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
-        case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCNTB_OFFSET):
+                        stat_addr = EXYNOS4_MCT_G_WSTAT;
-                stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
+                        mask = 1 << 2;          /* G_COMP0_ADD_INCR w status */
-                mask = 1 << 0;          /* L0_TCNTB write status */
+                        break;
-                break;
+                case (u32) EXYNOS4_MCT_G_CNT_L:
-        case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCNTB_OFFSET):
+                        stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
-                stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
+                        mask = 1 << 0;          /* G_CNT_L write status */
-                mask = 1 << 0;          /* L1_TCNTB write status */
+                        break;
-                break;
+                case (u32) EXYNOS4_MCT_G_CNT_U:
-        case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_ICNTB_OFFSET):
+                        stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
-                stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
+                        mask = 1 << 1;          /* G_CNT_U write status */
-                mask = 1 << 1;          /* L0_ICNTB write status */
+                        break;
-                break;
+                default:
-        case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_ICNTB_OFFSET):
+                        return;
-                stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
+                }
-                mask = 1 << 1;          /* L1_ICNTB write status */
-                break;
-        default:
-                return;
        }
        /* Wait maximum 1 ms until written values are applied */
@@ -321,9 +329,8 @@ static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
        }
 }
-static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
+static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
 {
-        struct mct_clock_event_device *mevt = dev_id;
        struct clock_event_device *evt = mevt->evt;
        /*
@@ -335,7 +342,20 @@ static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
                exynos4_mct_tick_stop(mevt);
        /* Clear the MCT tick interrupt */
-        exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
+        if (__raw_readl(mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
+                exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
+                return 1;
+        } else {
+                return 0;
+        }
+}
+static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
+{
+        struct mct_clock_event_device *mevt = dev_id;
+        struct clock_event_device *evt = mevt->evt;
+        exynos4_mct_tick_clear(mevt);
        evt->event_handler(evt);
@@ -360,14 +380,10 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
        mct_tick[cpu].evt = evt;
-        if (cpu == 0) {
+        mct_tick[cpu].base = EXYNOS4_MCT_L_BASE(cpu);
-                mct_tick[cpu].base = EXYNOS4_MCT_L0_BASE;
+        sprintf(mct_tick[cpu].name, "mct_tick%d", cpu);
-                evt->name = "mct_tick0";
-        } else {
-                mct_tick[cpu].base = EXYNOS4_MCT_L1_BASE;
-                evt->name = "mct_tick1";
-        }
+        evt->name = mct_tick[cpu].name;
        evt->cpumask = cpumask_of(cpu);
        evt->set_next_event = exynos4_tick_set_next_event;
        evt->set_mode = exynos4_tick_set_mode;
@@ -384,15 +400,19 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
        exynos4_mct_write(0x1, mct_tick[cpu].base + MCT_L_TCNTB_OFFSET);
-        if (cpu == 0) {
+        if (mct_int_type == MCT_INT_SPI) {
-                mct_tick0_event_irq.dev_id = &mct_tick[cpu];
+                if (cpu == 0) {
-                evt->irq = IRQ_MCT_L0;
+                        mct_tick0_event_irq.dev_id = &mct_tick[cpu];
-                setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
+                        evt->irq = IRQ_MCT_L0;
+                        setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
+                } else {
+                        mct_tick1_event_irq.dev_id = &mct_tick[cpu];
+                        evt->irq = IRQ_MCT_L1;
+                        setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
+                        irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
+                }
        } else {
-                mct_tick1_event_irq.dev_id = &mct_tick[cpu];
+                gic_enable_ppi(IRQ_MCT_LOCALTIMER);
-                evt->irq = IRQ_MCT_L1;
-                setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
-                irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
        }
 }
@@ -422,6 +442,11 @@ static void __init exynos4_timer_resources(void)
 static void __init exynos4_timer_init(void)
 {
+        if (soc_is_exynos4210())
+                mct_int_type = MCT_INT_SPI;
+        else
+                mct_int_type = MCT_INT_PPI;
        exynos4_timer_resources();
        exynos4_clocksource_init();
        exynos4_clockevent_init();
diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c
index 0c90896ad9a0..05595407e9ff 100644
--- a/arch/arm/mach-exynos4/platsmp.c
+++ b/arch/arm/mach-exynos4/platsmp.c
@@ -30,9 +30,13 @@
 #include <mach/regs-clock.h>
 #include <mach/regs-pmu.h>
+#include <plat/cpu.h>
+extern unsigned int gic_bank_offset;
 extern void exynos4_secondary_startup(void);
-#define CPU1_BOOT_REG S5P_VA_SYSRAM
+#define CPU1_BOOT_REG           (samsung_rev() == EXYNOS4210_REV_1_1 ? \
+                                S5P_INFORM5 : S5P_VA_SYSRAM)
 /*
 * control for which core is the next to come out of the secondary
@@ -64,9 +68,9 @@ static DEFINE_SPINLOCK(boot_lock);
 static void __cpuinit exynos4_gic_secondary_init(void)
 {
        void __iomem *dist_base = S5P_VA_GIC_DIST +
-                                 (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
+                                (gic_bank_offset * smp_processor_id());
        void __iomem *cpu_base = S5P_VA_GIC_CPU +
-                                (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
+                                (gic_bank_offset * smp_processor_id());
        int i;
        /*
@@ -128,7 +132,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
         * Note that "pen_release" is the hardware CPU ID, whereas
         * "cpu" is Linux's internal ID.
         */
-        write_pen_release(cpu);
+        write_pen_release(cpu_logical_map(cpu));
        if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
                __raw_writel(S5P_CORE_LOCAL_PWR_EN,
@@ -216,5 +220,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
         * until it receives a soft interrupt, and then the
         * secondary CPU branches to this address.
         */
-        __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), S5P_VA_SYSRAM);
+        __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
+                        CPU1_BOOT_REG);
 }
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index bc6ca9482de1..62e4f4363006 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -41,7 +41,6 @@ static struct sleep_save exynos4_set_clksrc[] = {
        { .reg = S5P_CLKSRC_MASK_CAM                    , .val = 0x11111111, },
        { .reg = S5P_CLKSRC_MASK_TV                     , .val = 0x00000111, },
        { .reg = S5P_CLKSRC_MASK_LCD0                   , .val = 0x00001111, },
-        { .reg = S5P_CLKSRC_MASK_LCD1                   , .val = 0x00001111, },
        { .reg = S5P_CLKSRC_MASK_MAUDIO                 , .val = 0x00000001, },
        { .reg = S5P_CLKSRC_MASK_FSYS                   , .val = 0x01011111, },
        { .reg = S5P_CLKSRC_MASK_PERIL0                 , .val = 0x01111111, },
@@ -49,6 +48,10 @@ static struct sleep_save exynos4_set_clksrc[] = {
        { .reg = S5P_CLKSRC_MASK_DMC                    , .val = 0x00010000, },
 };
+static struct sleep_save exynos4210_set_clksrc[] = {
+        { .reg = S5P_CLKSRC_MASK_LCD1                   , .val = 0x00001111, },
+};
 static struct sleep_save exynos4_epll_save[] = {
        SAVE_ITEM(S5P_EPLL_CON0),
        SAVE_ITEM(S5P_EPLL_CON1),
@@ -60,77 +63,6 @@ static struct sleep_save exynos4_vpll_save[] = {
 };
 static struct sleep_save exynos4_core_save[] = {
-        /* CMU side */
-        SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
-        SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
-        SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
-        SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
-        SAVE_ITEM(S5P_CLKSRC_TOP0),
-        SAVE_ITEM(S5P_CLKSRC_TOP1),
-        SAVE_ITEM(S5P_CLKSRC_CAM),
-        SAVE_ITEM(S5P_CLKSRC_TV),
-        SAVE_ITEM(S5P_CLKSRC_MFC),
-        SAVE_ITEM(S5P_CLKSRC_G3D),
-        SAVE_ITEM(S5P_CLKSRC_IMAGE),
-        SAVE_ITEM(S5P_CLKSRC_LCD0),
-        SAVE_ITEM(S5P_CLKSRC_LCD1),
-        SAVE_ITEM(S5P_CLKSRC_MAUDIO),
-        SAVE_ITEM(S5P_CLKSRC_FSYS),
-        SAVE_ITEM(S5P_CLKSRC_PERIL0),
-        SAVE_ITEM(S5P_CLKSRC_PERIL1),
-        SAVE_ITEM(S5P_CLKDIV_CAM),
-        SAVE_ITEM(S5P_CLKDIV_TV),
-        SAVE_ITEM(S5P_CLKDIV_MFC),
-        SAVE_ITEM(S5P_CLKDIV_G3D),
-        SAVE_ITEM(S5P_CLKDIV_IMAGE),
-        SAVE_ITEM(S5P_CLKDIV_LCD0),
-        SAVE_ITEM(S5P_CLKDIV_LCD1),
-        SAVE_ITEM(S5P_CLKDIV_MAUDIO),
-        SAVE_ITEM(S5P_CLKDIV_FSYS0),
-        SAVE_ITEM(S5P_CLKDIV_FSYS1),
-        SAVE_ITEM(S5P_CLKDIV_FSYS2),
-        SAVE_ITEM(S5P_CLKDIV_FSYS3),
-        SAVE_ITEM(S5P_CLKDIV_PERIL0),
-        SAVE_ITEM(S5P_CLKDIV_PERIL1),
-        SAVE_ITEM(S5P_CLKDIV_PERIL2),
-        SAVE_ITEM(S5P_CLKDIV_PERIL3),
-        SAVE_ITEM(S5P_CLKDIV_PERIL4),
-        SAVE_ITEM(S5P_CLKDIV_PERIL5),
-        SAVE_ITEM(S5P_CLKDIV_TOP),
-        SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
-        SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
-        SAVE_ITEM(S5P_CLKSRC_MASK_TV),
-        SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
-        SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
-        SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
-        SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
-        SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
-        SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
-        SAVE_ITEM(S5P_CLKDIV2_RATIO),
-        SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
-        SAVE_ITEM(S5P_CLKGATE_IP_CAM),
-        SAVE_ITEM(S5P_CLKGATE_IP_TV),
-        SAVE_ITEM(S5P_CLKGATE_IP_MFC),
-        SAVE_ITEM(S5P_CLKGATE_IP_G3D),
-        SAVE_ITEM(S5P_CLKGATE_IP_IMAGE),
-        SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
-        SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
-        SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
-        SAVE_ITEM(S5P_CLKGATE_IP_GPS),
-        SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
-        SAVE_ITEM(S5P_CLKGATE_IP_PERIR),
-        SAVE_ITEM(S5P_CLKGATE_BLOCK),
-        SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
-        SAVE_ITEM(S5P_CLKSRC_DMC),
-        SAVE_ITEM(S5P_CLKDIV_DMC0),
-        SAVE_ITEM(S5P_CLKDIV_DMC1),
-        SAVE_ITEM(S5P_CLKGATE_IP_DMC),
-        SAVE_ITEM(S5P_CLKSRC_CPU),
-        SAVE_ITEM(S5P_CLKDIV_CPU),
-        SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
-        SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
-        SAVE_ITEM(S5P_CLKGATE_IP_CPU),
        /* GIC side */
        SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
        SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
@@ -268,6 +200,9 @@ static void exynos4_pm_prepare(void)
        s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
+        if (soc_is_exynos4210())
+                s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
 }
 static int exynos4_pm_add(struct sys_device *sysdev)
diff --git a/arch/arm/mach-highbank/Makefile b/arch/arm/mach-highbank/Makefile
new file mode 100644
index 000000000000..986958a5a720
--- /dev/null
+++ b/arch/arm/mach-highbank/Makefile
@@ -0,0 +1,6 @@
+obj-y                                   := clock.o highbank.o system.o
+obj-$(CONFIG_DEBUG_HIGHBANK_UART)       += lluart.o
+obj-$(CONFIG_SMP)                       += platsmp.o
+obj-$(CONFIG_LOCAL_TIMERS)              += localtimer.o
+obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
+obj-$(CONFIG_PM_SLEEP)                  += pm.o
diff --git a/arch/arm/mach-highbank/Makefile.boot b/arch/arm/mach-highbank/Makefile.boot
new file mode 100644
index 000000000000..dae9661a7689
--- /dev/null
+++ b/arch/arm/mach-highbank/Makefile.boot
@@ -0,0 +1 @@
+zreladdr-y      := 0x00008000
diff --git a/arch/arm/mach-highbank/clock.c b/arch/arm/mach-highbank/clock.c
new file mode 100644
index 000000000000..c25a2ae4fde1
--- /dev/null
+++ b/arch/arm/mach-highbank/clock.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2011 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+struct clk {
+        unsigned long rate;
+};
+int clk_enable(struct clk *clk)
+{
+        return 0;
+}
+void clk_disable(struct clk *clk)
+{}
+unsigned long clk_get_rate(struct clk *clk)
+{
+        return clk->rate;
+}
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+        return clk->rate;
+}
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        return 0;
+}
+static struct clk eclk = { .rate = 200000000 };
+static struct clk pclk = { .rate = 150000000 };
+static struct clk_lookup lookups[] = {
+        { .clk = &pclk, .con_id = "apb_pclk", },
+        { .clk = &pclk, .dev_id = "sp804", },
+        { .clk = &eclk, .dev_id = "ffe0e000.sdhci", },
+        { .clk = &pclk, .dev_id = "fff36000.serial", },
+};
+void __init highbank_clocks_init(void)
+{
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+}
diff --git a/arch/arm/mach-highbank/core.h b/arch/arm/mach-highbank/core.h
new file mode 100644
index 000000000000..7e33fc94cd1e
--- /dev/null
+++ b/arch/arm/mach-highbank/core.h
@@ -0,0 +1,9 @@
+extern void highbank_set_cpu_jump(int cpu, void *jump_addr);
+extern void highbank_clocks_init(void);
+extern void __iomem *scu_base_addr;
+#ifdef CONFIG_DEBUG_HIGHBANK_UART
+extern void highbank_lluart_map_io(void);
+#else
+static inline void highbank_lluart_map_io(void) {}
+#endif
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
new file mode 100644
index 000000000000..b82dcf08e747
--- /dev/null
+++ b/arch/arm/mach-highbank/highbank.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright 2010-2011 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <asm/cacheflush.h>
+#include <asm/unified.h>
+#include <asm/smp_scu.h>
+#include <asm/hardware/arm_timer.h>
+#include <asm/hardware/timer-sp.h>
+#include <asm/hardware/gic.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <mach/irqs.h>
+#include "core.h"
+#include "sysregs.h"
+void __iomem *sregs_base;
+#define HB_SCU_VIRT_BASE        0xfee00000
+void __iomem *scu_base_addr = ((void __iomem *)(HB_SCU_VIRT_BASE));
+static struct map_desc scu_io_desc __initdata = {
+        .virtual        = HB_SCU_VIRT_BASE,
+        .pfn            = 0, /* run-time */
+        .length         = SZ_4K,
+        .type           = MT_DEVICE,
+};
+static void __init highbank_scu_map_io(void)
+{
+        unsigned long base;
+        /* Get SCU base */
+        asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
+        scu_io_desc.pfn = __phys_to_pfn(base);
+        iotable_init(&scu_io_desc, 1);
+}
+static void __init highbank_map_io(void)
+{
+        highbank_scu_map_io();
+        highbank_lluart_map_io();
+}
+#define HB_JUMP_TABLE_PHYS(cpu)         (0x40 + (0x10 * (cpu)))
+#define HB_JUMP_TABLE_VIRT(cpu)         phys_to_virt(HB_JUMP_TABLE_PHYS(cpu))
+void highbank_set_cpu_jump(int cpu, void *jump_addr)
+{
+        writel(BSYM(virt_to_phys(jump_addr)), HB_JUMP_TABLE_VIRT(cpu));
+        __cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16);
+        outer_clean_range(HB_JUMP_TABLE_PHYS(cpu),
+                          HB_JUMP_TABLE_PHYS(cpu) + 15);
+}
+const static struct of_device_id irq_match[] = {
+        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+        {}
+};
+static void __init highbank_init_irq(void)
+{
+        of_irq_init(irq_match);
+        l2x0_of_init(0, ~0UL);
+}
+static void __init highbank_timer_init(void)
+{
+        int irq;
+        struct device_node *np;
+        void __iomem *timer_base;
+        /* Map system registers */
+        np = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");
+        sregs_base = of_iomap(np, 0);
+        WARN_ON(!sregs_base);
+        np = of_find_compatible_node(NULL, NULL, "arm,sp804");
+        timer_base = of_iomap(np, 0);
+        WARN_ON(!timer_base);
+        irq = irq_of_parse_and_map(np, 0);
+        highbank_clocks_init();
+        sp804_clocksource_init(timer_base + 0x20, "timer1");
+        sp804_clockevents_init(timer_base, irq, "timer0");
+}
+static struct sys_timer highbank_timer = {
+        .init = highbank_timer_init,
+};
+static void highbank_power_off(void)
+{
+        hignbank_set_pwr_shutdown();
+        scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
+        while (1)
+                cpu_do_idle();
+}
+static void __init highbank_init(void)
+{
+        pm_power_off = highbank_power_off;
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+static const char *highbank_match[] __initconst = {
+        "calxeda,highbank",
+        NULL,
+};
+DT_MACHINE_START(HIGHBANK, "Highbank")
+        .map_io         = highbank_map_io,
+        .init_irq       = highbank_init_irq,
+        .timer          = &highbank_timer,
+        .init_machine   = highbank_init,
+        .dt_compat      = highbank_match,
+MACHINE_END
diff --git a/arch/arm/mach-highbank/hotplug.c b/arch/arm/mach-highbank/hotplug.c
new file mode 100644
index 000000000000..977cebbea580
--- /dev/null
+++ b/arch/arm/mach-highbank/hotplug.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2011 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+#include <asm/smp_scu.h>
+#include <asm/cacheflush.h>
+#include "core.h"
+extern void secondary_startup(void);
+int platform_cpu_kill(unsigned int cpu)
+{
+        return 1;
+}
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ */
+void platform_cpu_die(unsigned int cpu)
+{
+        flush_cache_all();
+        highbank_set_cpu_jump(cpu, secondary_startup);
+        scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
+        cpu_do_idle();
+        /* We should never return from idle */
+        panic("highbank: cpu %d unexpectedly exit from shutdown\n", cpu);
+}
+int platform_cpu_disable(unsigned int cpu)
+{
+        /*
+         * CPU0 should not be shut down via hotplug.  cpu_idle can WFI
+         * or a proper shutdown or hibernate should be used.
+         */
+        return cpu == 0 ? -EPERM : 0;
+}
diff --git a/arch/arm/mach-highbank/include/mach/debug-macro.S b/arch/arm/mach-highbank/include/mach/debug-macro.S
new file mode 100644
index 000000000000..cb57fe5bcd04
--- /dev/null
+++ b/arch/arm/mach-highbank/include/mach/debug-macro.S
@@ -0,0 +1,19 @@
+/*
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+                .macro  addruart,rp,rv,tmp
+                movw    \rv, #0x6000
+                movt    \rv, #0xfee3
+                movw    \rp, #0x6000
+                movt    \rp, #0xfff3
+                .endm
+#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-highbank/include/mach/entry-macro.S b/arch/arm/mach-highbank/include/mach/entry-macro.S
new file mode 100644
index 000000000000..73c11297509e
--- /dev/null
+++ b/arch/arm/mach-highbank/include/mach/entry-macro.S
@@ -0,0 +1,7 @@
+#include <asm/hardware/entry-macro-gic.S>
+        .macro  disable_fiq
+        .endm
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
diff --git a/arch/um/include/asm/ftrace.h b/arch/arm/mach-highbank/include/mach/gpio.h
index 40a8c178f10d..40a8c178f10d 100644
--- a/arch/um/include/asm/ftrace.h
+++ b/arch/arm/mach-highbank/include/mach/gpio.h
diff --git a/arch/arm/mach-highbank/include/mach/io.h b/arch/arm/mach-highbank/include/mach/io.h
new file mode 100644
index 000000000000..70cfa3ba7697
--- /dev/null
+++ b/arch/arm/mach-highbank/include/mach/io.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_IO_H
+#define __MACH_IO_H
+#define __io(a)         ({ (void)(a); __typesafe_io(0); })
+#define __mem_pci(a)    (a)
+#endif
diff --git a/arch/arm/mach-highbank/include/mach/irqs.h b/arch/arm/mach-highbank/include/mach/irqs.h
new file mode 100644
index 000000000000..9746aab14e9a
--- /dev/null
+++ b/arch/arm/mach-highbank/include/mach/irqs.h
@@ -0,0 +1,6 @@
+#ifndef __MACH_IRQS_H
+#define __MACH_IRQS_H
+#define NR_IRQS                 192
+#endif
diff --git a/arch/arm/mach-highbank/include/mach/memory.h b/arch/arm/mach-highbank/include/mach/memory.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/arch/arm/mach-highbank/include/mach/memory.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/arch/arm/mach-highbank/include/mach/system.h b/arch/arm/mach-highbank/include/mach/system.h
new file mode 100644
index 000000000000..7e8192296cae
--- /dev/null
+++ b/arch/arm/mach-highbank/include/mach/system.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2010-2011 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __MACH_SYSTEM_H
+#define __MACH_SYSTEM_H
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+extern void arch_reset(char mode, const char *cmd);
+#endif
diff --git a/arch/arm/mach-highbank/include/mach/timex.h b/arch/arm/mach-highbank/include/mach/timex.h
new file mode 100644
index 000000000000..88dac7a55a97
--- /dev/null
+++ b/arch/arm/mach-highbank/include/mach/timex.h
@@ -0,0 +1,6 @@
+#ifndef __MACH_TIMEX_H
+#define __MACH_TIMEX_H
+#define CLOCK_TICK_RATE         1000000
+#endif
diff --git a/arch/arm/mach-highbank/include/mach/uncompress.h b/arch/arm/mach-highbank/include/mach/uncompress.h
new file mode 100644
index 000000000000..bbe20e696325
--- /dev/null
+++ b/arch/arm/mach-highbank/include/mach/uncompress.h
@@ -0,0 +1,9 @@
+#ifndef __MACH_UNCOMPRESS_H
+#define __MACH_UNCOMPRESS_H
+#define putc(c)
+#define flush()
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
+#endif
diff --git a/arch/arm/mach-highbank/include/mach/vmalloc.h b/arch/arm/mach-highbank/include/mach/vmalloc.h
new file mode 100644
index 000000000000..1969e954277a
--- /dev/null
+++ b/arch/arm/mach-highbank/include/mach/vmalloc.h
@@ -0,0 +1 @@
+#define VMALLOC_END             0xFEE00000UL
diff --git a/arch/arm/mach-highbank/lluart.c b/arch/arm/mach-highbank/lluart.c
new file mode 100644
index 000000000000..371575019f33
--- /dev/null
+++ b/arch/arm/mach-highbank/lluart.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2011 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/init.h>
+#include <asm/page.h>
+#include <asm/sizes.h>
+#include <asm/mach/map.h>
+#define HB_DEBUG_LL_PHYS_BASE   0xfff36000
+#define HB_DEBUG_LL_VIRT_BASE   0xfee36000
+static struct map_desc lluart_io_desc __initdata = {
+        .virtual        = HB_DEBUG_LL_VIRT_BASE,
+        .pfn            = __phys_to_pfn(HB_DEBUG_LL_PHYS_BASE),
+        .length         = SZ_4K,
+        .type           = MT_DEVICE,
+};
+void __init highbank_lluart_map_io(void)
+{
+        iotable_init(&lluart_io_desc, 1);
+}
diff --git a/arch/arm/mach-highbank/localtimer.c b/arch/arm/mach-highbank/localtimer.c
new file mode 100644
index 000000000000..5a00e7945fdf
--- /dev/null
+++ b/arch/arm/mach-highbank/localtimer.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2010-2011 Calxeda, Inc.
+ * Based on localtimer.c, Copyright (C) 2002 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/init.h>
+#include <linux/clockchips.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <asm/smp_twd.h>
+/*
+ * Setup the local clock events for a CPU.
+ */
+int __cpuinit local_timer_setup(struct clock_event_device *evt)
+{
+        struct device_node *np;
+        np = of_find_compatible_node(NULL, NULL, "arm,smp-twd");
+        if (!twd_base) {
+                twd_base = of_iomap(np, 0);
+                WARN_ON(!twd_base);
+        }
+        evt->irq = irq_of_parse_and_map(np, 0);
+        twd_timer_setup(evt);
+        return 0;
+}
diff --git a/arch/arm/mach-highbank/platsmp.c b/arch/arm/mach-highbank/platsmp.c
new file mode 100644
index 000000000000..d01364c72b45
--- /dev/null
+++ b/arch/arm/mach-highbank/platsmp.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2010-2011 Calxeda, Inc.
+ * Based on platsmp.c, Copyright (C) 2002 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <asm/smp_scu.h>
+#include <asm/hardware/gic.h>
+#include "core.h"
+extern void secondary_startup(void);
+void __cpuinit platform_secondary_init(unsigned int cpu)
+{
+        gic_secondary_init(0);
+}
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        gic_raise_softirq(cpumask_of(cpu), 0);
+        return 0;
+}
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system.
+ */
+void __init smp_init_cpus(void)
+{
+        unsigned int i, ncores;
+        ncores = scu_get_core_count(scu_base_addr);
+        /* sanity check */
+        if (ncores > NR_CPUS) {
+                printk(KERN_WARNING
+                       "highbank: no. of cores (%d) greater than configured "
+                       "maximum of %d - clipping\n",
+                       ncores, NR_CPUS);
+                ncores = NR_CPUS;
+        }
+        for (i = 0; i < ncores; i++)
+                set_cpu_possible(i, true);
+        set_smp_cross_call(gic_raise_softirq);
+}
+void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+{
+        int i;
+        scu_enable(scu_base_addr);
+        /*
+         * Write the address of secondary startup into the jump table
+         * The cores are in wfi and wait until they receive a soft interrupt
+         * and a non-zero value to jump to. Then the secondary CPU branches
+         * to this address.
+         */
+        for (i = 1; i < max_cpus; i++)
+                highbank_set_cpu_jump(i, secondary_startup);
+}
diff --git a/arch/arm/mach-highbank/pm.c b/arch/arm/mach-highbank/pm.c
new file mode 100644
index 000000000000..33b3beb89982
--- /dev/null
+++ b/arch/arm/mach-highbank/pm.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2011 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/suspend.h>
+#include <asm/proc-fns.h>
+#include <asm/smp_scu.h>
+#include <asm/suspend.h>
+#include "core.h"
+#include "sysregs.h"
+static int highbank_suspend_finish(unsigned long val)
+{
+        cpu_do_idle();
+        return 0;
+}
+static int highbank_pm_enter(suspend_state_t state)
+{
+        hignbank_set_pwr_suspend();
+        highbank_set_cpu_jump(0, cpu_resume);
+        scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
+        cpu_suspend(0, highbank_suspend_finish);
+        return 0;
+}
+static const struct platform_suspend_ops highbank_pm_ops = {
+        .enter = highbank_pm_enter,
+        .valid = suspend_valid_only_mem,
+};
+static int __init highbank_pm_init(void)
+{
+        suspend_set_ops(&highbank_pm_ops);
+        return 0;
+}
+module_init(highbank_pm_init);
diff --git a/arch/arm/mach-highbank/sysregs.h b/arch/arm/mach-highbank/sysregs.h
new file mode 100644
index 000000000000..0e913389f445
--- /dev/null
+++ b/arch/arm/mach-highbank/sysregs.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2011 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef _MACH_HIGHBANK__SYSREGS_H_
+#define _MACH_HIGHBANK__SYSREGS_H_
+#include <linux/io.h>
+extern void __iomem *sregs_base;
+#define HB_SREG_A9_PWR_REQ              0xf00
+#define HB_SREG_A9_BOOT_STAT            0xf04
+#define HB_SREG_A9_BOOT_DATA            0xf08
+#define HB_PWR_SUSPEND                  0
+#define HB_PWR_SOFT_RESET               1
+#define HB_PWR_HARD_RESET               2
+#define HB_PWR_SHUTDOWN                 3
+static inline void hignbank_set_pwr_suspend(void)
+{
+        writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ);
+}
+static inline void hignbank_set_pwr_shutdown(void)
+{
+        writel(HB_PWR_SHUTDOWN, sregs_base + HB_SREG_A9_PWR_REQ);
+}
+static inline void hignbank_set_pwr_soft_reset(void)
+{
+        writel(HB_PWR_SOFT_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
+}
+static inline void hignbank_set_pwr_hard_reset(void)
+{
+        writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
+}
+#endif
diff --git a/arch/arm/mach-highbank/system.c b/arch/arm/mach-highbank/system.c
new file mode 100644
index 000000000000..53f0c4c5ef1c
--- /dev/null
+++ b/arch/arm/mach-highbank/system.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2011 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/io.h>
+#include <asm/smp_scu.h>
+#include <asm/proc-fns.h>
+#include "core.h"
+#include "sysregs.h"
+void arch_reset(char mode, const char *cmd)
+{
+        if (mode == 'h')
+                hignbank_set_pwr_hard_reset();
+        else
+                hignbank_set_pwr_soft_reset();
+        scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
+        cpu_do_idle();
+}
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 0519dd7f034b..5f7f9c2a34ae 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,10 +1,32 @@
 config IMX_HAVE_DMA_V1
        bool
+config HAVE_IMX_GPC
+        bool
+config HAVE_IMX_MMDC
+        bool
+config HAVE_IMX_SRC
+        bool
 #
 # ARCH_MX31 and ARCH_MX35 are left for compatibility
 # Some usages assume that having one of them implies not having (e.g.) ARCH_MX2.
 # To easily distinguish good and reviewed from unreviewed usages new (and IMHO
 # more sensible) names are used: SOC_IMX31 and SOC_IMX35
+config ARCH_MX1
+        bool
+config MACH_MX21
+        bool
+config ARCH_MX25
+        bool
+config MACH_MX27
+        bool
 config ARCH_MX31
        bool
@@ -13,6 +35,7 @@ config ARCH_MX35
 config SOC_IMX1
        bool
+        select ARCH_MX1
        select CPU_ARM920T
        select IMX_HAVE_DMA_V1
        select IMX_HAVE_IOMUX_V1
@@ -20,6 +43,7 @@ config SOC_IMX1
 config SOC_IMX21
        bool
+        select MACH_MX21
        select CPU_ARM926T
        select ARCH_MXC_AUDMUX_V1
        select IMX_HAVE_DMA_V1
@@ -28,6 +52,7 @@ config SOC_IMX21
 config SOC_IMX25
        bool
+        select ARCH_MX25
        select CPU_ARM926T
        select ARCH_MXC_AUDMUX_V2
        select ARCH_MXC_IOMUX_V3
@@ -35,6 +60,7 @@ config SOC_IMX25
 config SOC_IMX27
        bool
+        select MACH_MX27
        select CPU_ARM926T
        select ARCH_MXC_AUDMUX_V1
        select IMX_HAVE_DMA_V1
@@ -48,6 +74,7 @@ config SOC_IMX31
        select ARCH_MXC_AUDMUX_V2
        select ARCH_MX31
        select MXC_AVIC
+        select SMP_ON_UP if SMP
 config SOC_IMX35
        bool
@@ -57,9 +84,10 @@ config SOC_IMX35
        select HAVE_EPIT
        select ARCH_MX35
        select MXC_AVIC
+        select SMP_ON_UP if SMP
-if ARCH_MX1
+if ARCH_IMX_V4_V5
 comment "MX1 platforms:"
 config MACH_MXLADS
@@ -87,30 +115,6 @@ config MACH_APF9328
        help
          Say Yes here if you are using the Armadeus APF9328 development board
-endif
-if ARCH_MX2
-choice
-        prompt "CPUs:"
-        default MACH_MX21
-config MACH_MX21
-        bool "i.MX21 support"
-        help
-          This enables support for Freescale's MX2 based i.MX21 processor.
-config MACH_MX27
-        bool "i.MX27 support"
-        help
-          This enables support for Freescale's MX2 based i.MX27 processor.
-endchoice
-endif
-if MACH_MX21
 comment "MX21 platforms:"
 config MACH_MX21ADS
@@ -124,15 +128,12 @@ config MACH_MX21ADS
          Include support for MX21ADS platform. This includes specific
          configurations for the board and its peripherals.
-endif
-if ARCH_MX25
 comment "MX25 platforms:"
 config MACH_MX25_3DS
        bool "Support MX25PDK (3DS) Platform"
        select SOC_IMX25
+        select IMX_HAVE_PLATFORM_FLEXCAN
        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
        select IMX_HAVE_PLATFORM_IMX2_WDT
        select IMX_HAVE_PLATFORM_IMXDI_RTC
@@ -174,10 +175,6 @@ config MACH_EUKREA_MBIMXSD25_BASEBOARD
 endchoice
-endif
-if MACH_MX27
 comment "MX27 platforms:"
 config MACH_MX27ADS
@@ -356,7 +353,7 @@ config MACH_IMX27IPCAM
 endif
-if ARCH_MX3
+if ARCH_IMX_V6_V7
 comment "MX31 platforms:"
@@ -449,6 +446,7 @@ config MACH_MX31_3DS
        select IMX_HAVE_PLATFORM_IMX_UART
        select IMX_HAVE_PLATFORM_IPU_CORE
        select IMX_HAVE_PLATFORM_MXC_EHCI
+        select IMX_HAVE_PLATFORM_MXC_MMC
        select IMX_HAVE_PLATFORM_MXC_NAND
        select IMX_HAVE_PLATFORM_SPI_IMX
        select MXC_ULPI if USB_ULPI
@@ -485,6 +483,7 @@ config MACH_QONG
        bool "Support Dave/DENX QongEVB-LITE platform"
        select SOC_IMX31
        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_IMX2_WDT
        help
          Include support for Dave/DENX QongEVB-LITE platform. This includes
          specific configurations for the board and its peripherals.
@@ -605,4 +604,20 @@ config MACH_VPR200
          Include support for VPR200 platform. This includes specific
          configurations for the board and its peripherals.
+comment "i.MX6 family:"
+config SOC_IMX6Q
+        bool "i.MX6 Quad support"
+        select ARM_GIC
+        select CACHE_L2X0
+        select CPU_V7
+        select HAVE_ARM_SCU
+        select HAVE_IMX_GPC
+        select HAVE_IMX_MMDC
+        select HAVE_IMX_SRC
+        select USE_OF
+        help
+          This enables support for Freescale i.MX6 Quad processor.
 endif
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index e9eb36dad888..aba73214c2a8 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -1,16 +1,15 @@
 obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
-obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o
+obj-$(CONFIG_SOC_IMX1) += clock-imx1.o mm-imx1.o
-obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o
+obj-$(CONFIG_SOC_IMX21) += clock-imx21.o mm-imx21.o
-obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o ehci-imx25.o
+obj-$(CONFIG_SOC_IMX25) += clock-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o
-obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o
+obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o
-obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
+obj-$(CONFIG_SOC_IMX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
-obj-$(CONFIG_SOC_IMX31) += mm-imx31.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o
+obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o
-obj-$(CONFIG_SOC_IMX35) += mm-imx35.o cpu-imx35.o clock-imx35.o ehci-imx35.o
+obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o
-obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
 # Support for CMOS sensor interface
 obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
@@ -61,3 +60,14 @@ obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX35) += mach-cpuimx35.o
 obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o
 obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
+obj-$(CONFIG_DEBUG_LL) += lluart.o
+obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
+obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
+obj-$(CONFIG_HAVE_IMX_SRC) += src.o
+obj-$(CONFIG_CPU_V7) += head-v7.o
+AFLAGS_head-v7.o :=-Wa,-march=armv7-a
+obj-$(CONFIG_SMP) += platsmp.o
+obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
+obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
+obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o pm-imx6q.o
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
index dbe61201bcd8..22d85889f622 100644
--- a/arch/arm/mach-imx/Makefile.boot
+++ b/arch/arm/mach-imx/Makefile.boot
@@ -17,3 +17,7 @@ initrd_phys-$(CONFIG_MACH_MX27)	:= 0xA0800000
 zreladdr-$(CONFIG_ARCH_MX3)     += 0x80008000
 params_phys-$(CONFIG_ARCH_MX3)  := 0x80000100
 initrd_phys-$(CONFIG_ARCH_MX3)  := 0x80800000
+zreladdr-$(CONFIG_SOC_IMX6Q)    += 0x10008000
+params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100
+initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000
diff --git a/arch/arm/mach-imx/cache-l2x0.c b/arch/arm/mach-imx/cache-l2x0.c
deleted file mode 100644
index 69d1322add3c..000000000000
--- a/arch/arm/mach-imx/cache-l2x0.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Pengutronix
- * Sascha Hauer <s.hauer@pengutronix.de>
- * Juergen Beisert <j.beisert@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/init.h>
-#include <linux/err.h>
-#include <linux/kernel.h>
-#include <asm/hardware/cache-l2x0.h>
-#include <mach/hardware.h>
-static int mxc_init_l2x0(void)
-{
-        void __iomem *l2x0_base;
-        void __iomem *clkctl_base;
-        if (!cpu_is_mx31() && !cpu_is_mx35())
-                return 0;
-/*
- * First of all, we must repair broken chip settings. There are some
- * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
- * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
- * Workaraound is to setup the correct register setting prior enabling the
- * L2 cache. This should not hurt already working CPUs, as they are using the
- * same value.
- */
-#define L2_MEM_VAL 0x10
-        clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
-        if (clkctl_base != NULL) {
-                writel(0x00000515, clkctl_base + L2_MEM_VAL);
-                iounmap(clkctl_base);
-        } else {
-                pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
-        }
-        l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
-        if (IS_ERR(l2x0_base)) {
-                printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
-                                PTR_ERR(l2x0_base));
-                return 0;
-        }
-        l2x0_init(l2x0_base, 0x00030024, 0x00000000);
-        return 0;
-}
-arch_initcall(mxc_init_l2x0);
diff --git a/arch/arm/mach-imx/clock-imx25.c b/arch/arm/mach-imx/clock-imx25.c
index e63e23504fe5..b0fec74c8c91 100644
--- a/arch/arm/mach-imx/clock-imx25.c
+++ b/arch/arm/mach-imx/clock-imx25.c
@@ -263,6 +263,7 @@ DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL);
 DEFINE_CLOCK(csi_clk,    0, CCM_CGCR1,  4, get_rate_csi, NULL,  &csi_per_clk);
 DEFINE_CLOCK(can1_clk,   0, CCM_CGCR1,  2, get_rate_ipg, NULL, NULL);
 DEFINE_CLOCK(can2_clk,   1, CCM_CGCR1,  3, get_rate_ipg, NULL, NULL);
+DEFINE_CLOCK(iim_clk,    0, CCM_CGCR1, 26, NULL, NULL, NULL);
 #define _REGISTER_CLOCK(d, n, c)        \
        {                               \
@@ -310,6 +311,7 @@ static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
        /* i.mx25 has the i.mx35 type sdma */
        _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
+        _REGISTER_CLOCK(NULL, "iim", iim_clk)
 };
 int __init mx25_clocks_init(void)
@@ -334,6 +336,10 @@ int __init mx25_clocks_init(void)
        /* Clock source for gpt is ahb_div */
        __raw_writel(__raw_readl(CRM_BASE+0x64) & ~(1 << 5), CRM_BASE + 0x64);
+        clk_enable(&iim_clk);
+        imx_print_silicon_rev("i.MX25", mx25_revision());
+        clk_disable(&iim_clk);
        mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
        return 0;
diff --git a/arch/arm/mach-imx/clock-imx27.c b/arch/arm/mach-imx/clock-imx27.c
index 6912b821b37b..88fe00a146e3 100644
--- a/arch/arm/mach-imx/clock-imx27.c
+++ b/arch/arm/mach-imx/clock-imx27.c
@@ -583,7 +583,7 @@ DEFINE_CLOCK(emi_clk,      0, PCCR1, 19, NULL, NULL, &ahb_clk);
 DEFINE_CLOCK(dma_clk1,     0, PCCR1, 20, NULL, NULL, &ahb_clk);
 DEFINE_CLOCK(csi_clk1,     0, PCCR1, 21, NULL, NULL, &ahb_clk);
 DEFINE_CLOCK(brom_clk,     0, PCCR1, 22, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(ata_clk,      0, PCCR1, 23, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(pata_clk,      0, PCCR1, 23, NULL, NULL, &ahb_clk);
 DEFINE_CLOCK(wdog_clk,     0, PCCR1, 24, NULL, NULL, &ipg_clk);
 DEFINE_CLOCK(usb_clk,      0, PCCR1, 25, get_rate_usb, &usb_clk1, &spll_clk);
 DEFINE_CLOCK(uart6_clk1,   0, PCCR1, 26, NULL, NULL, &ipg_clk);
@@ -666,7 +666,7 @@ static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk)
        _REGISTER_CLOCK(NULL, "emi", emi_clk)
        _REGISTER_CLOCK(NULL, "sahara2", sahara2_clk)
-        _REGISTER_CLOCK(NULL, "ata", ata_clk)
+        _REGISTER_CLOCK("pata_imx", NULL, pata_clk)
        _REGISTER_CLOCK(NULL, "mstick", mstick_clk)
        _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
        _REGISTER_CLOCK(NULL, "gpio", gpio_clk)
@@ -751,6 +751,8 @@ int __init mx27_clocks_init(unsigned long fref)
        clk_enable(&gpio_clk);
        clk_enable(&emi_clk);
        clk_enable(&iim_clk);
+        imx_print_silicon_rev("i.MX27", mx27_revision());
+        clk_disable(&iim_clk);
 #if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
        clk_enable(&uart1_clk);
diff --git a/arch/arm/mach-imx/clock-imx31.c b/arch/arm/mach-imx/clock-imx31.c
index d973770b1f96..988a28178d4c 100644
--- a/arch/arm/mach-imx/clock-imx31.c
+++ b/arch/arm/mach-imx/clock-imx31.c
@@ -476,7 +476,7 @@ DEFINE_CLOCK(gpt_clk,     0, MXC_CCM_CGR0,  4, NULL, NULL, &perclk_clk);
 DEFINE_CLOCK(epit1_clk,   0, MXC_CCM_CGR0,  6, NULL, NULL, &perclk_clk);
 DEFINE_CLOCK(epit2_clk,   1, MXC_CCM_CGR0,  8, NULL, NULL, &perclk_clk);
 DEFINE_CLOCK(iim_clk,     0, MXC_CCM_CGR0, 10, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(ata_clk,     0, MXC_CCM_CGR0, 12, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(pata_clk,     0, MXC_CCM_CGR0, 12, NULL, NULL, &ipg_clk);
 DEFINE_CLOCK(sdma_clk1,   0, MXC_CCM_CGR0, 14, NULL, NULL, &ahb_clk);
 DEFINE_CLOCK(cspi3_clk,   2, MXC_CCM_CGR0, 16, NULL, NULL, &ipg_clk);
 DEFINE_CLOCK(rng_clk,     0, MXC_CCM_CGR0, 18, NULL, NULL, &ipg_clk);
@@ -562,7 +562,7 @@ static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
        _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
        _REGISTER_CLOCK(NULL, "firi", firi_clk)
-        _REGISTER_CLOCK(NULL, "ata", ata_clk)
+        _REGISTER_CLOCK("pata_imx", NULL, pata_clk)
        _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
        _REGISTER_CLOCK(NULL, "rng", rng_clk)
        _REGISTER_CLOCK("imx31-sdma", NULL, sdma_clk1)
@@ -611,11 +611,11 @@ int __init mx31_clocks_init(unsigned long fref)
        clk_enable(&gpt_clk);
        clk_enable(&emi_clk);
        clk_enable(&iim_clk);
+        mx31_revision();
+        clk_disable(&iim_clk);
        clk_enable(&serial_pll_clk);
-        mx31_read_cpu_rev();
        if (mx31_revision() >= IMX_CHIP_REVISION_2_0) {
                reg = __raw_readl(MXC_CCM_PMCR1);
                /* No PLL restart on DVFS switch; enable auto EMI handshake */
diff --git a/arch/arm/mach-imx/clock-imx35.c b/arch/arm/mach-imx/clock-imx35.c
index 88b62a071aea..8116f119517d 100644
--- a/arch/arm/mach-imx/clock-imx35.c
+++ b/arch/arm/mach-imx/clock-imx35.c
@@ -354,7 +354,7 @@ static void clk_cgr_disable(struct clk *clk)
        }
 DEFINE_CLOCK(asrc_clk,   0, CCM_CGR0,  0, NULL, NULL);
-DEFINE_CLOCK(ata_clk,    0, CCM_CGR0,  2, get_rate_ipg, NULL);
+DEFINE_CLOCK(pata_clk,    0, CCM_CGR0,  2, get_rate_ipg, NULL);
 /* DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0,  4, NULL, NULL); */
 DEFINE_CLOCK(can1_clk,   0, CCM_CGR0,  6, get_rate_ipg, NULL);
 DEFINE_CLOCK(can2_clk,   1, CCM_CGR0,  8, get_rate_ipg, NULL);
@@ -447,7 +447,7 @@ static struct clk nfc_clk = {
 static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK(NULL, "asrc", asrc_clk)
-        _REGISTER_CLOCK(NULL, "ata", ata_clk)
+        _REGISTER_CLOCK("pata_imx", NULL, pata_clk)
        _REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
        _REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
        _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi1_clk)
@@ -537,7 +537,8 @@ int __init mx35_clocks_init()
        __raw_writel(cgr3, CCM_BASE + CCM_CGR3);
        clk_enable(&iim_clk);
-        mx35_read_cpu_rev();
+        imx_print_silicon_rev("i.MX35", mx35_revision());
+        clk_disable(&iim_clk);
 #ifdef CONFIG_MXC_USE_EPIT
        epit_timer_init(&epit1_clk,
diff --git a/arch/arm/mach-imx/clock-imx6q.c b/arch/arm/mach-imx/clock-imx6q.c
new file mode 100644
index 000000000000..e0b926dfeced
--- /dev/null
+++ b/arch/arm/mach-imx/clock-imx6q.c
@@ -0,0 +1,2012 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <asm/div64.h>
+#include <asm/mach/map.h>
+#include <mach/clock.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#define PLL_BASE                IMX_IO_ADDRESS(MX6Q_ANATOP_BASE_ADDR)
+#define PLL1_SYS                (PLL_BASE + 0x000)
+#define PLL2_BUS                (PLL_BASE + 0x030)
+#define PLL3_USB_OTG            (PLL_BASE + 0x010)
+#define PLL4_AUDIO              (PLL_BASE + 0x070)
+#define PLL5_VIDEO              (PLL_BASE + 0x0a0)
+#define PLL6_MLB                (PLL_BASE + 0x0d0)
+#define PLL7_USB_HOST           (PLL_BASE + 0x020)
+#define PLL8_ENET               (PLL_BASE + 0x0e0)
+#define PFD_480                 (PLL_BASE + 0x0f0)
+#define PFD_528                 (PLL_BASE + 0x100)
+#define PLL_NUM_OFFSET          0x010
+#define PLL_DENOM_OFFSET        0x020
+#define PFD0                    7
+#define PFD1                    15
+#define PFD2                    23
+#define PFD3                    31
+#define PFD_FRAC_MASK           0x3f
+#define BM_PLL_BYPASS                   (0x1 << 16)
+#define BM_PLL_ENABLE                   (0x1 << 13)
+#define BM_PLL_POWER_DOWN               (0x1 << 12)
+#define BM_PLL_LOCK                     (0x1 << 31)
+#define BP_PLL_SYS_DIV_SELECT           0
+#define BM_PLL_SYS_DIV_SELECT           (0x7f << 0)
+#define BP_PLL_BUS_DIV_SELECT           0
+#define BM_PLL_BUS_DIV_SELECT           (0x1 << 0)
+#define BP_PLL_USB_DIV_SELECT           0
+#define BM_PLL_USB_DIV_SELECT           (0x3 << 0)
+#define BP_PLL_AV_DIV_SELECT            0
+#define BM_PLL_AV_DIV_SELECT            (0x7f << 0)
+#define BP_PLL_ENET_DIV_SELECT          0
+#define BM_PLL_ENET_DIV_SELECT          (0x3 << 0)
+#define BM_PLL_ENET_EN_PCIE             (0x1 << 19)
+#define BM_PLL_ENET_EN_SATA             (0x1 << 20)
+#define CCM_BASE        IMX_IO_ADDRESS(MX6Q_CCM_BASE_ADDR)
+#define CCR             (CCM_BASE + 0x00)
+#define CCDR            (CCM_BASE + 0x04)
+#define CSR             (CCM_BASE + 0x08)
+#define CCSR            (CCM_BASE + 0x0c)
+#define CACRR           (CCM_BASE + 0x10)
+#define CBCDR           (CCM_BASE + 0x14)
+#define CBCMR           (CCM_BASE + 0x18)
+#define CSCMR1          (CCM_BASE + 0x1c)
+#define CSCMR2          (CCM_BASE + 0x20)
+#define CSCDR1          (CCM_BASE + 0x24)
+#define CS1CDR          (CCM_BASE + 0x28)
+#define CS2CDR          (CCM_BASE + 0x2c)
+#define CDCDR           (CCM_BASE + 0x30)
+#define CHSCCDR         (CCM_BASE + 0x34)
+#define CSCDR2          (CCM_BASE + 0x38)
+#define CSCDR3          (CCM_BASE + 0x3c)
+#define CSCDR4          (CCM_BASE + 0x40)
+#define CWDR            (CCM_BASE + 0x44)
+#define CDHIPR          (CCM_BASE + 0x48)
+#define CDCR            (CCM_BASE + 0x4c)
+#define CTOR            (CCM_BASE + 0x50)
+#define CLPCR           (CCM_BASE + 0x54)
+#define CISR            (CCM_BASE + 0x58)
+#define CIMR            (CCM_BASE + 0x5c)
+#define CCOSR           (CCM_BASE + 0x60)
+#define CGPR            (CCM_BASE + 0x64)
+#define CCGR0           (CCM_BASE + 0x68)
+#define CCGR1           (CCM_BASE + 0x6c)
+#define CCGR2           (CCM_BASE + 0x70)
+#define CCGR3           (CCM_BASE + 0x74)
+#define CCGR4           (CCM_BASE + 0x78)
+#define CCGR5           (CCM_BASE + 0x7c)
+#define CCGR6           (CCM_BASE + 0x80)
+#define CCGR7           (CCM_BASE + 0x84)
+#define CMEOR           (CCM_BASE + 0x88)
+#define CG0             0
+#define CG1             2
+#define CG2             4
+#define CG3             6
+#define CG4             8
+#define CG5             10
+#define CG6             12
+#define CG7             14
+#define CG8             16
+#define CG9             18
+#define CG10            20
+#define CG11            22
+#define CG12            24
+#define CG13            26
+#define CG14            28
+#define CG15            30
+#define BM_CCSR_PLL1_SW_SEL             (0x1 << 2)
+#define BM_CCSR_STEP_SEL                (0x1 << 8)
+#define BP_CACRR_ARM_PODF               0
+#define BM_CACRR_ARM_PODF               (0x7 << 0)
+#define BP_CBCDR_PERIPH2_CLK2_PODF      0
+#define BM_CBCDR_PERIPH2_CLK2_PODF      (0x7 << 0)
+#define BP_CBCDR_MMDC_CH1_AXI_PODF      3
+#define BM_CBCDR_MMDC_CH1_AXI_PODF      (0x7 << 3)
+#define BP_CBCDR_AXI_SEL                6
+#define BM_CBCDR_AXI_SEL                (0x3 << 6)
+#define BP_CBCDR_IPG_PODF               8
+#define BM_CBCDR_IPG_PODF               (0x3 << 8)
+#define BP_CBCDR_AHB_PODF               10
+#define BM_CBCDR_AHB_PODF               (0x7 << 10)
+#define BP_CBCDR_AXI_PODF               16
+#define BM_CBCDR_AXI_PODF               (0x7 << 16)
+#define BP_CBCDR_MMDC_CH0_AXI_PODF      19
+#define BM_CBCDR_MMDC_CH0_AXI_PODF      (0x7 << 19)
+#define BP_CBCDR_PERIPH_CLK_SEL         25
+#define BM_CBCDR_PERIPH_CLK_SEL         (0x1 << 25)
+#define BP_CBCDR_PERIPH2_CLK_SEL        26
+#define BM_CBCDR_PERIPH2_CLK_SEL        (0x1 << 26)
+#define BP_CBCDR_PERIPH_CLK2_PODF       27
+#define BM_CBCDR_PERIPH_CLK2_PODF       (0x7 << 27)
+#define BP_CBCMR_GPU2D_AXI_SEL          0
+#define BM_CBCMR_GPU2D_AXI_SEL          (0x1 << 0)
+#define BP_CBCMR_GPU3D_AXI_SEL          1
+#define BM_CBCMR_GPU3D_AXI_SEL          (0x1 << 1)
+#define BP_CBCMR_GPU3D_CORE_SEL         4
+#define BM_CBCMR_GPU3D_CORE_SEL         (0x3 << 4)
+#define BP_CBCMR_GPU3D_SHADER_SEL       8
+#define BM_CBCMR_GPU3D_SHADER_SEL       (0x3 << 8)
+#define BP_CBCMR_PCIE_AXI_SEL           10
+#define BM_CBCMR_PCIE_AXI_SEL           (0x1 << 10)
+#define BP_CBCMR_VDO_AXI_SEL            11
+#define BM_CBCMR_VDO_AXI_SEL            (0x1 << 11)
+#define BP_CBCMR_PERIPH_CLK2_SEL        12
+#define BM_CBCMR_PERIPH_CLK2_SEL        (0x3 << 12)
+#define BP_CBCMR_VPU_AXI_SEL            14
+#define BM_CBCMR_VPU_AXI_SEL            (0x3 << 14)
+#define BP_CBCMR_GPU2D_CORE_SEL         16
+#define BM_CBCMR_GPU2D_CORE_SEL         (0x3 << 16)
+#define BP_CBCMR_PRE_PERIPH_CLK_SEL     18
+#define BM_CBCMR_PRE_PERIPH_CLK_SEL     (0x3 << 18)
+#define BP_CBCMR_PERIPH2_CLK2_SEL       20
+#define BM_CBCMR_PERIPH2_CLK2_SEL       (0x1 << 20)
+#define BP_CBCMR_PRE_PERIPH2_CLK_SEL    21
+#define BM_CBCMR_PRE_PERIPH2_CLK_SEL    (0x3 << 21)
+#define BP_CBCMR_GPU2D_CORE_PODF        23
+#define BM_CBCMR_GPU2D_CORE_PODF        (0x7 << 23)
+#define BP_CBCMR_GPU3D_CORE_PODF        26
+#define BM_CBCMR_GPU3D_CORE_PODF        (0x7 << 26)
+#define BP_CBCMR_GPU3D_SHADER_PODF      29
+#define BM_CBCMR_GPU3D_SHADER_PODF      (0x7 << 29)
+#define BP_CSCMR1_PERCLK_PODF           0
+#define BM_CSCMR1_PERCLK_PODF           (0x3f << 0)
+#define BP_CSCMR1_SSI1_SEL              10
+#define BM_CSCMR1_SSI1_SEL              (0x3 << 10)
+#define BP_CSCMR1_SSI2_SEL              12
+#define BM_CSCMR1_SSI2_SEL              (0x3 << 12)
+#define BP_CSCMR1_SSI3_SEL              14
+#define BM_CSCMR1_SSI3_SEL              (0x3 << 14)
+#define BP_CSCMR1_USDHC1_SEL            16
+#define BM_CSCMR1_USDHC1_SEL            (0x1 << 16)
+#define BP_CSCMR1_USDHC2_SEL            17
+#define BM_CSCMR1_USDHC2_SEL            (0x1 << 17)
+#define BP_CSCMR1_USDHC3_SEL            18
+#define BM_CSCMR1_USDHC3_SEL            (0x1 << 18)
+#define BP_CSCMR1_USDHC4_SEL            19
+#define BM_CSCMR1_USDHC4_SEL            (0x1 << 19)
+#define BP_CSCMR1_EMI_PODF              20
+#define BM_CSCMR1_EMI_PODF              (0x7 << 20)
+#define BP_CSCMR1_EMI_SLOW_PODF         23
+#define BM_CSCMR1_EMI_SLOW_PODF         (0x7 << 23)
+#define BP_CSCMR1_EMI_SEL               27
+#define BM_CSCMR1_EMI_SEL               (0x3 << 27)
+#define BP_CSCMR1_EMI_SLOW_SEL          29
+#define BM_CSCMR1_EMI_SLOW_SEL          (0x3 << 29)
+#define BP_CSCMR2_CAN_PODF              2
+#define BM_CSCMR2_CAN_PODF              (0x3f << 2)
+#define BM_CSCMR2_LDB_DI0_IPU_DIV       (0x1 << 10)
+#define BM_CSCMR2_LDB_DI1_IPU_DIV       (0x1 << 11)
+#define BP_CSCMR2_ESAI_SEL              19
+#define BM_CSCMR2_ESAI_SEL              (0x3 << 19)
+#define BP_CSCDR1_UART_PODF             0
+#define BM_CSCDR1_UART_PODF             (0x3f << 0)
+#define BP_CSCDR1_USDHC1_PODF           11
+#define BM_CSCDR1_USDHC1_PODF           (0x7 << 11)
+#define BP_CSCDR1_USDHC2_PODF           16
+#define BM_CSCDR1_USDHC2_PODF           (0x7 << 16)
+#define BP_CSCDR1_USDHC3_PODF           19
+#define BM_CSCDR1_USDHC3_PODF           (0x7 << 19)
+#define BP_CSCDR1_USDHC4_PODF           22
+#define BM_CSCDR1_USDHC4_PODF           (0x7 << 22)
+#define BP_CSCDR1_VPU_AXI_PODF          25
+#define BM_CSCDR1_VPU_AXI_PODF          (0x7 << 25)
+#define BP_CS1CDR_SSI1_PODF             0
+#define BM_CS1CDR_SSI1_PODF             (0x3f << 0)
+#define BP_CS1CDR_SSI1_PRED             6
+#define BM_CS1CDR_SSI1_PRED             (0x7 << 6)
+#define BP_CS1CDR_ESAI_PRED             9
+#define BM_CS1CDR_ESAI_PRED             (0x7 << 9)
+#define BP_CS1CDR_SSI3_PODF             16
+#define BM_CS1CDR_SSI3_PODF             (0x3f << 16)
+#define BP_CS1CDR_SSI3_PRED             22
+#define BM_CS1CDR_SSI3_PRED             (0x7 << 22)
+#define BP_CS1CDR_ESAI_PODF             25
+#define BM_CS1CDR_ESAI_PODF             (0x7 << 25)
+#define BP_CS2CDR_SSI2_PODF             0
+#define BM_CS2CDR_SSI2_PODF             (0x3f << 0)
+#define BP_CS2CDR_SSI2_PRED             6
+#define BM_CS2CDR_SSI2_PRED             (0x7 << 6)
+#define BP_CS2CDR_LDB_DI0_SEL           9
+#define BM_CS2CDR_LDB_DI0_SEL           (0x7 << 9)
+#define BP_CS2CDR_LDB_DI1_SEL           12
+#define BM_CS2CDR_LDB_DI1_SEL           (0x7 << 12)
+#define BP_CS2CDR_ENFC_SEL              16
+#define BM_CS2CDR_ENFC_SEL              (0x3 << 16)
+#define BP_CS2CDR_ENFC_PRED             18
+#define BM_CS2CDR_ENFC_PRED             (0x7 << 18)
+#define BP_CS2CDR_ENFC_PODF             21
+#define BM_CS2CDR_ENFC_PODF             (0x3f << 21)
+#define BP_CDCDR_ASRC_SERIAL_SEL        7
+#define BM_CDCDR_ASRC_SERIAL_SEL        (0x3 << 7)
+#define BP_CDCDR_ASRC_SERIAL_PODF       9
+#define BM_CDCDR_ASRC_SERIAL_PODF       (0x7 << 9)
+#define BP_CDCDR_ASRC_SERIAL_PRED       12
+#define BM_CDCDR_ASRC_SERIAL_PRED       (0x7 << 12)
+#define BP_CDCDR_SPDIF_SEL              20
+#define BM_CDCDR_SPDIF_SEL              (0x3 << 20)
+#define BP_CDCDR_SPDIF_PODF             22
+#define BM_CDCDR_SPDIF_PODF             (0x7 << 22)
+#define BP_CDCDR_SPDIF_PRED             25
+#define BM_CDCDR_SPDIF_PRED             (0x7 << 25)
+#define BP_CDCDR_HSI_TX_PODF            29
+#define BM_CDCDR_HSI_TX_PODF            (0x7 << 29)
+#define BP_CDCDR_HSI_TX_SEL             28
+#define BM_CDCDR_HSI_TX_SEL             (0x1 << 28)
+#define BP_CHSCCDR_IPU1_DI0_SEL         0
+#define BM_CHSCCDR_IPU1_DI0_SEL         (0x7 << 0)
+#define BP_CHSCCDR_IPU1_DI0_PRE_PODF    3
+#define BM_CHSCCDR_IPU1_DI0_PRE_PODF    (0x7 << 3)
+#define BP_CHSCCDR_IPU1_DI0_PRE_SEL     6
+#define BM_CHSCCDR_IPU1_DI0_PRE_SEL     (0x7 << 6)
+#define BP_CHSCCDR_IPU1_DI1_SEL         9
+#define BM_CHSCCDR_IPU1_DI1_SEL         (0x7 << 9)
+#define BP_CHSCCDR_IPU1_DI1_PRE_PODF    12
+#define BM_CHSCCDR_IPU1_DI1_PRE_PODF    (0x7 << 12)
+#define BP_CHSCCDR_IPU1_DI1_PRE_SEL     15
+#define BM_CHSCCDR_IPU1_DI1_PRE_SEL     (0x7 << 15)
+#define BP_CSCDR2_IPU2_DI0_SEL          0
+#define BM_CSCDR2_IPU2_DI0_SEL          (0x7)
+#define BP_CSCDR2_IPU2_DI0_PRE_PODF     3
+#define BM_CSCDR2_IPU2_DI0_PRE_PODF     (0x7 << 3)
+#define BP_CSCDR2_IPU2_DI0_PRE_SEL      6
+#define BM_CSCDR2_IPU2_DI0_PRE_SEL      (0x7 << 6)
+#define BP_CSCDR2_IPU2_DI1_SEL          9
+#define BM_CSCDR2_IPU2_DI1_SEL          (0x7 << 9)
+#define BP_CSCDR2_IPU2_DI1_PRE_PODF     12
+#define BM_CSCDR2_IPU2_DI1_PRE_PODF     (0x7 << 12)
+#define BP_CSCDR2_IPU2_DI1_PRE_SEL      15
+#define BM_CSCDR2_IPU2_DI1_PRE_SEL      (0x7 << 15)
+#define BP_CSCDR2_ECSPI_CLK_PODF        19
+#define BM_CSCDR2_ECSPI_CLK_PODF        (0x3f << 19)
+#define BP_CSCDR3_IPU1_HSP_SEL          9
+#define BM_CSCDR3_IPU1_HSP_SEL          (0x3 << 9)
+#define BP_CSCDR3_IPU1_HSP_PODF         11
+#define BM_CSCDR3_IPU1_HSP_PODF         (0x7 << 11)
+#define BP_CSCDR3_IPU2_HSP_SEL          14
+#define BM_CSCDR3_IPU2_HSP_SEL          (0x3 << 14)
+#define BP_CSCDR3_IPU2_HSP_PODF         16
+#define BM_CSCDR3_IPU2_HSP_PODF         (0x7 << 16)
+#define BM_CDHIPR_AXI_PODF_BUSY         (0x1 << 0)
+#define BM_CDHIPR_AHB_PODF_BUSY         (0x1 << 1)
+#define BM_CDHIPR_MMDC_CH1_PODF_BUSY    (0x1 << 2)
+#define BM_CDHIPR_PERIPH2_SEL_BUSY      (0x1 << 3)
+#define BM_CDHIPR_MMDC_CH0_PODF_BUSY    (0x1 << 4)
+#define BM_CDHIPR_PERIPH_SEL_BUSY       (0x1 << 5)
+#define BM_CDHIPR_ARM_PODF_BUSY         (0x1 << 16)
+#define BP_CLPCR_LPM                    0
+#define BM_CLPCR_LPM                    (0x3 << 0)
+#define BM_CLPCR_BYPASS_PMIC_READY      (0x1 << 2)
+#define BM_CLPCR_ARM_CLK_DIS_ON_LPM     (0x1 << 5)
+#define BM_CLPCR_SBYOS                  (0x1 << 6)
+#define BM_CLPCR_DIS_REF_OSC            (0x1 << 7)
+#define BM_CLPCR_VSTBY                  (0x1 << 8)
+#define BP_CLPCR_STBY_COUNT             9
+#define BM_CLPCR_STBY_COUNT             (0x3 << 9)
+#define BM_CLPCR_COSC_PWRDOWN           (0x1 << 11)
+#define BM_CLPCR_WB_PER_AT_LPM          (0x1 << 16)
+#define BM_CLPCR_WB_CORE_AT_LPM         (0x1 << 17)
+#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS    (0x1 << 19)
+#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS    (0x1 << 21)
+#define BM_CLPCR_MASK_CORE0_WFI         (0x1 << 22)
+#define BM_CLPCR_MASK_CORE1_WFI         (0x1 << 23)
+#define BM_CLPCR_MASK_CORE2_WFI         (0x1 << 24)
+#define BM_CLPCR_MASK_CORE3_WFI         (0x1 << 25)
+#define BM_CLPCR_MASK_SCU_IDLE          (0x1 << 26)
+#define BM_CLPCR_MASK_L2CC_IDLE         (0x1 << 27)
+#define FREQ_480M       480000000
+#define FREQ_528M       528000000
+#define FREQ_594M       594000000
+#define FREQ_650M       650000000
+#define FREQ_1300M      1300000000
+static struct clk pll1_sys;
+static struct clk pll2_bus;
+static struct clk pll3_usb_otg;
+static struct clk pll4_audio;
+static struct clk pll5_video;
+static struct clk pll6_mlb;
+static struct clk pll7_usb_host;
+static struct clk pll8_enet;
+static struct clk apbh_dma_clk;
+static struct clk arm_clk;
+static struct clk ipg_clk;
+static struct clk ahb_clk;
+static struct clk axi_clk;
+static struct clk mmdc_ch0_axi_clk;
+static struct clk mmdc_ch1_axi_clk;
+static struct clk periph_clk;
+static struct clk periph_pre_clk;
+static struct clk periph_clk2_clk;
+static struct clk periph2_clk;
+static struct clk periph2_pre_clk;
+static struct clk periph2_clk2_clk;
+static struct clk gpu2d_core_clk;
+static struct clk gpu3d_core_clk;
+static struct clk gpu3d_shader_clk;
+static struct clk ipg_perclk;
+static struct clk emi_clk;
+static struct clk emi_slow_clk;
+static struct clk can1_clk;
+static struct clk uart_clk;
+static struct clk usdhc1_clk;
+static struct clk usdhc2_clk;
+static struct clk usdhc3_clk;
+static struct clk usdhc4_clk;
+static struct clk vpu_clk;
+static struct clk hsi_tx_clk;
+static struct clk ipu1_di0_pre_clk;
+static struct clk ipu1_di1_pre_clk;
+static struct clk ipu2_di0_pre_clk;
+static struct clk ipu2_di1_pre_clk;
+static struct clk ipu1_clk;
+static struct clk ipu2_clk;
+static struct clk ssi1_clk;
+static struct clk ssi3_clk;
+static struct clk esai_clk;
+static struct clk ssi2_clk;
+static struct clk spdif_clk;
+static struct clk asrc_serial_clk;
+static struct clk gpu2d_axi_clk;
+static struct clk gpu3d_axi_clk;
+static struct clk pcie_clk;
+static struct clk vdo_axi_clk;
+static struct clk ldb_di0_clk;
+static struct clk ldb_di1_clk;
+static struct clk ipu1_di0_clk;
+static struct clk ipu1_di1_clk;
+static struct clk ipu2_di0_clk;
+static struct clk ipu2_di1_clk;
+static struct clk enfc_clk;
+static struct clk dummy_clk = {};
+static unsigned long external_high_reference;
+static unsigned long external_low_reference;
+static unsigned long oscillator_reference;
+static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
+{
+        return oscillator_reference;
+}
+static unsigned long get_high_reference_clock_rate(struct clk *clk)
+{
+        return external_high_reference;
+}
+static unsigned long get_low_reference_clock_rate(struct clk *clk)
+{
+        return external_low_reference;
+}
+static struct clk ckil_clk = {
+        .get_rate = get_low_reference_clock_rate,
+};
+static struct clk ckih_clk = {
+        .get_rate = get_high_reference_clock_rate,
+};
+static struct clk osc_clk = {
+        .get_rate = get_oscillator_reference_clock_rate,
+};
+static inline void __iomem *pll_get_reg_addr(struct clk *pll)
+{
+        if (pll == &pll1_sys)
+                return PLL1_SYS;
+        else if (pll == &pll2_bus)
+                return PLL2_BUS;
+        else if (pll == &pll3_usb_otg)
+                return PLL3_USB_OTG;
+        else if (pll == &pll4_audio)
+                return PLL4_AUDIO;
+        else if (pll == &pll5_video)
+                return PLL5_VIDEO;
+        else if (pll == &pll6_mlb)
+                return PLL6_MLB;
+        else if (pll == &pll7_usb_host)
+                return PLL7_USB_HOST;
+        else if (pll == &pll8_enet)
+                return PLL8_ENET;
+        else
+                BUG();
+        return NULL;
+}
+static int pll_enable(struct clk *clk)
+{
+        int timeout = 0x100000;
+        void __iomem *reg;
+        u32 val;
+        reg = pll_get_reg_addr(clk);
+        val = readl_relaxed(reg);
+        val &= ~BM_PLL_BYPASS;
+        val &= ~BM_PLL_POWER_DOWN;
+        /* 480MHz PLLs have the opposite definition for power bit */
+        if (clk == &pll3_usb_otg || clk == &pll7_usb_host)
+                val |= BM_PLL_POWER_DOWN;
+        writel_relaxed(val, reg);
+        /* Wait for PLL to lock */
+        while (!(readl_relaxed(reg) & BM_PLL_LOCK) && --timeout)
+                cpu_relax();
+        if (unlikely(!timeout))
+                return -EBUSY;
+        /* Enable the PLL output now */
+        val = readl_relaxed(reg);
+        val |= BM_PLL_ENABLE;
+        writel_relaxed(val, reg);
+        return 0;
+}
+static void pll_disable(struct clk *clk)
+{
+        void __iomem *reg;
+        u32 val;
+        reg = pll_get_reg_addr(clk);
+        val = readl_relaxed(reg);
+        val &= ~BM_PLL_ENABLE;
+        val |= BM_PLL_BYPASS;
+        val |= BM_PLL_POWER_DOWN;
+        if (clk == &pll3_usb_otg || clk == &pll7_usb_host)
+                val &= ~BM_PLL_POWER_DOWN;
+        writel_relaxed(val, reg);
+}
+static unsigned long pll1_sys_get_rate(struct clk *clk)
+{
+        u32 div = (readl_relaxed(PLL1_SYS) & BM_PLL_SYS_DIV_SELECT) >>
+                  BP_PLL_SYS_DIV_SELECT;
+        return clk_get_rate(clk->parent) * div / 2;
+}
+static int pll1_sys_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 val, div;
+        if (rate < FREQ_650M || rate > FREQ_1300M)
+                return -EINVAL;
+        div = rate * 2 / clk_get_rate(clk->parent);
+        val = readl_relaxed(PLL1_SYS);
+        val &= ~BM_PLL_SYS_DIV_SELECT;
+        val |= div << BP_PLL_SYS_DIV_SELECT;
+        writel_relaxed(val, PLL1_SYS);
+        return 0;
+}
+static unsigned long pll8_enet_get_rate(struct clk *clk)
+{
+        u32 div = (readl_relaxed(PLL8_ENET) & BM_PLL_ENET_DIV_SELECT) >>
+                  BP_PLL_ENET_DIV_SELECT;
+        switch (div) {
+        case 0:
+                return 25000000;
+        case 1:
+                return 50000000;
+        case 2:
+                return 100000000;
+        case 3:
+                return 125000000;
+        }
+        return 0;
+}
+static int pll8_enet_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 val, div;
+        switch (rate) {
+        case 25000000:
+                div = 0;
+                break;
+        case 50000000:
+                div = 1;
+                break;
+        case 100000000:
+                div = 2;
+                break;
+        case 125000000:
+                div = 3;
+                break;
+        default:
+                return -EINVAL;
+        }
+        val = readl_relaxed(PLL8_ENET);
+        val &= ~BM_PLL_ENET_DIV_SELECT;
+        val |= div << BP_PLL_ENET_DIV_SELECT;
+        writel_relaxed(val, PLL8_ENET);
+        return 0;
+}
+static unsigned long pll_av_get_rate(struct clk *clk)
+{
+        void __iomem *reg = (clk == &pll4_audio) ? PLL4_AUDIO : PLL5_VIDEO;
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        u32 mfn = readl_relaxed(reg + PLL_NUM_OFFSET);
+        u32 mfd = readl_relaxed(reg + PLL_DENOM_OFFSET);
+        u32 div = (readl_relaxed(reg) & BM_PLL_AV_DIV_SELECT) >>
+                  BP_PLL_AV_DIV_SELECT;
+        return (parent_rate * div) + ((parent_rate / mfd) * mfn);
+}
+static int pll_av_set_rate(struct clk *clk, unsigned long rate)
+{
+        void __iomem *reg = (clk == &pll4_audio) ? PLL4_AUDIO : PLL5_VIDEO;
+        unsigned int parent_rate = clk_get_rate(clk->parent);
+        u32 val, div;
+        u32 mfn, mfd = 1000000;
+        s64 temp64;
+        if (rate < FREQ_650M || rate > FREQ_1300M)
+                return -EINVAL;
+        div = rate / parent_rate;
+        temp64 = (u64) (rate - div * parent_rate);
+        temp64 *= mfd;
+        do_div(temp64, parent_rate);
+        mfn = temp64;
+        val = readl_relaxed(reg);
+        val &= ~BM_PLL_AV_DIV_SELECT;
+        val |= div << BP_PLL_AV_DIV_SELECT;
+        writel_relaxed(val, reg);
+        writel_relaxed(mfn, reg + PLL_NUM_OFFSET);
+        writel_relaxed(mfd, reg + PLL_DENOM_OFFSET);
+        return 0;
+}
+static void __iomem *pll_get_div_reg_bit(struct clk *clk, u32 *bp, u32 *bm)
+{
+        void __iomem *reg;
+        if (clk == &pll2_bus) {
+                reg = PLL2_BUS;
+                *bp = BP_PLL_BUS_DIV_SELECT;
+                *bm = BM_PLL_BUS_DIV_SELECT;
+        } else if (clk == &pll3_usb_otg) {
+                reg = PLL3_USB_OTG;
+                *bp = BP_PLL_USB_DIV_SELECT;
+                *bm = BM_PLL_USB_DIV_SELECT;
+        } else if (clk == &pll7_usb_host) {
+                reg = PLL7_USB_HOST;
+                *bp = BP_PLL_USB_DIV_SELECT;
+                *bm = BM_PLL_USB_DIV_SELECT;
+        } else {
+                BUG();
+        }
+        return reg;
+}
+static unsigned long pll_get_rate(struct clk *clk)
+{
+        void __iomem *reg;
+        u32 div, bp, bm;
+        reg = pll_get_div_reg_bit(clk, &bp, &bm);
+        div = (readl_relaxed(reg) & bm) >> bp;
+        return (div == 1) ? clk_get_rate(clk->parent) * 22 :
+                            clk_get_rate(clk->parent) * 20;
+}
+static int pll_set_rate(struct clk *clk, unsigned long rate)
+{
+        void __iomem *reg;
+        u32 val, div, bp, bm;
+        if (rate == FREQ_528M)
+                div = 1;
+        else if (rate == FREQ_480M)
+                div = 0;
+        else
+                return -EINVAL;
+        reg = pll_get_div_reg_bit(clk, &bp, &bm);
+        val = readl_relaxed(reg);
+        val &= ~bm;
+        val |= div << bp;
+        writel_relaxed(val, reg);
+        return 0;
+}
+#define pll2_bus_get_rate       pll_get_rate
+#define pll2_bus_set_rate       pll_set_rate
+#define pll3_usb_otg_get_rate   pll_get_rate
+#define pll3_usb_otg_set_rate   pll_set_rate
+#define pll7_usb_host_get_rate  pll_get_rate
+#define pll7_usb_host_set_rate  pll_set_rate
+#define pll4_audio_get_rate     pll_av_get_rate
+#define pll4_audio_set_rate     pll_av_set_rate
+#define pll5_video_get_rate     pll_av_get_rate
+#define pll5_video_set_rate     pll_av_set_rate
+#define pll6_mlb_get_rate       NULL
+#define pll6_mlb_set_rate       NULL
+#define DEF_PLL(name)                                   \
+        static struct clk name = {                      \
+                .enable         = pll_enable,           \
+                .disable        = pll_disable,          \
+                .get_rate       = name##_get_rate,      \
+                .set_rate       = name##_set_rate,      \
+                .parent         = &osc_clk,             \
+        }
+DEF_PLL(pll1_sys);
+DEF_PLL(pll2_bus);
+DEF_PLL(pll3_usb_otg);
+DEF_PLL(pll4_audio);
+DEF_PLL(pll5_video);
+DEF_PLL(pll6_mlb);
+DEF_PLL(pll7_usb_host);
+DEF_PLL(pll8_enet);
+static unsigned long pfd_get_rate(struct clk *clk)
+{
+        u64 tmp = (u64) clk_get_rate(clk->parent) * 18;
+        u32 frac, bp_frac;
+        if (apbh_dma_clk.usecount == 0)
+                apbh_dma_clk.enable(&apbh_dma_clk);
+        bp_frac = clk->enable_shift - 7;
+        frac = readl_relaxed(clk->enable_reg) >> bp_frac & PFD_FRAC_MASK;
+        do_div(tmp, frac);
+        return tmp;
+}
+static int pfd_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 val, frac, bp_frac;
+        u64 tmp = (u64) clk_get_rate(clk->parent) * 18;
+        if (apbh_dma_clk.usecount == 0)
+                apbh_dma_clk.enable(&apbh_dma_clk);
+        /*
+         * Round up the divider so that we don't set a rate
+         * higher than what is requested
+         */
+        tmp += rate / 2;
+        do_div(tmp, rate);
+        frac = tmp;
+        frac = (frac < 12) ? 12 : frac;
+        frac = (frac > 35) ? 35 : frac;
+        /*
+         * The frac field always starts from 7 bits lower
+         * position of enable bit
+         */
+        bp_frac = clk->enable_shift - 7;
+        val = readl_relaxed(clk->enable_reg);
+        val &= ~(PFD_FRAC_MASK << bp_frac);
+        val |= frac << bp_frac;
+        writel_relaxed(val, clk->enable_reg);
+        tmp = (u64) clk_get_rate(clk->parent) * 18;
+        do_div(tmp, frac);
+        if (apbh_dma_clk.usecount == 0)
+                apbh_dma_clk.disable(&apbh_dma_clk);
+        return 0;
+}
+static unsigned long pfd_round_rate(struct clk *clk, unsigned long rate)
+{
+        u32 frac;
+        u64 tmp;
+        tmp = (u64) clk_get_rate(clk->parent) * 18;
+        tmp += rate / 2;
+        do_div(tmp, rate);
+        frac = tmp;
+        frac = (frac < 12) ? 12 : frac;
+        frac = (frac > 35) ? 35 : frac;
+        tmp = (u64) clk_get_rate(clk->parent) * 18;
+        do_div(tmp, frac);
+        return tmp;
+}
+static int pfd_enable(struct clk *clk)
+{
+        u32 val;
+        if (apbh_dma_clk.usecount == 0)
+                apbh_dma_clk.enable(&apbh_dma_clk);
+        val = readl_relaxed(clk->enable_reg);
+        val &= ~(1 << clk->enable_shift);
+        writel_relaxed(val, clk->enable_reg);
+        if (apbh_dma_clk.usecount == 0)
+                apbh_dma_clk.disable(&apbh_dma_clk);
+        return 0;
+}
+static void pfd_disable(struct clk *clk)
+{
+        u32 val;
+        if (apbh_dma_clk.usecount == 0)
+                apbh_dma_clk.enable(&apbh_dma_clk);
+        val = readl_relaxed(clk->enable_reg);
+        val |= 1 << clk->enable_shift;
+        writel_relaxed(val, clk->enable_reg);
+        if (apbh_dma_clk.usecount == 0)
+                apbh_dma_clk.disable(&apbh_dma_clk);
+}
+#define DEF_PFD(name, er, es, p)                        \
+        static struct clk name = {                      \
+                .enable_reg     = er,                   \
+                .enable_shift   = es,                   \
+                .enable         = pfd_enable,           \
+                .disable        = pfd_disable,          \
+                .get_rate       = pfd_get_rate,         \
+                .set_rate       = pfd_set_rate,         \
+                .round_rate     = pfd_round_rate,       \
+                .parent         = p,                    \
+        }
+DEF_PFD(pll2_pfd_352m, PFD_528, PFD0, &pll2_bus);
+DEF_PFD(pll2_pfd_594m, PFD_528, PFD1, &pll2_bus);
+DEF_PFD(pll2_pfd_400m, PFD_528, PFD2, &pll2_bus);
+DEF_PFD(pll3_pfd_720m, PFD_480, PFD0, &pll3_usb_otg);
+DEF_PFD(pll3_pfd_540m, PFD_480, PFD1, &pll3_usb_otg);
+DEF_PFD(pll3_pfd_508m, PFD_480, PFD2, &pll3_usb_otg);
+DEF_PFD(pll3_pfd_454m, PFD_480, PFD3, &pll3_usb_otg);
+static unsigned long pll2_200m_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) / 2;
+}
+static struct clk pll2_200m = {
+        .parent = &pll2_pfd_400m,
+        .get_rate = pll2_200m_get_rate,
+};
+static unsigned long pll3_120m_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) / 4;
+}
+static struct clk pll3_120m = {
+        .parent = &pll3_usb_otg,
+        .get_rate = pll3_120m_get_rate,
+};
+static unsigned long pll3_80m_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) / 6;
+}
+static struct clk pll3_80m = {
+        .parent = &pll3_usb_otg,
+        .get_rate = pll3_80m_get_rate,
+};
+static unsigned long pll3_60m_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) / 8;
+}
+static struct clk pll3_60m = {
+        .parent = &pll3_usb_otg,
+        .get_rate = pll3_60m_get_rate,
+};
+static int pll1_sw_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+        u32 val = readl_relaxed(CCSR);
+        if (parent == &pll1_sys) {
+                val &= ~BM_CCSR_PLL1_SW_SEL;
+                val &= ~BM_CCSR_STEP_SEL;
+        } else if (parent == &osc_clk) {
+                val |= BM_CCSR_PLL1_SW_SEL;
+                val &= ~BM_CCSR_STEP_SEL;
+        } else if (parent == &pll2_pfd_400m) {
+                val |= BM_CCSR_PLL1_SW_SEL;
+                val |= BM_CCSR_STEP_SEL;
+        } else {
+                return -EINVAL;
+        }
+        writel_relaxed(val, CCSR);
+        return 0;
+}
+static struct clk pll1_sw_clk = {
+        .parent = &pll1_sys,
+        .set_parent = pll1_sw_clk_set_parent,
+};
+static void calc_pred_podf_dividers(u32 div, u32 *pred, u32 *podf)
+{
+        u32 min_pred, temp_pred, old_err, err;
+        if (div >= 512) {
+                *pred = 8;
+                *podf = 64;
+        } else if (div >= 8) {
+                min_pred = (div - 1) / 64 + 1;
+                old_err = 8;
+                for (temp_pred = 8; temp_pred >= min_pred; temp_pred--) {
+                        err = div % temp_pred;
+                        if (err == 0) {
+                                *pred = temp_pred;
+                                break;
+                        }
+                        err = temp_pred - err;
+                        if (err < old_err) {
+                                old_err = err;
+                                *pred = temp_pred;
+                        }
+                }
+                *podf = (div + *pred - 1) / *pred;
+        } else if (div < 8) {
+                *pred = div;
+                *podf = 1;
+        }
+}
+static int _clk_enable(struct clk *clk)
+{
+        u32 reg;
+        reg = readl_relaxed(clk->enable_reg);
+        reg |= 0x3 << clk->enable_shift;
+        writel_relaxed(reg, clk->enable_reg);
+        return 0;
+}
+static void _clk_disable(struct clk *clk)
+{
+        u32 reg;
+        reg = readl_relaxed(clk->enable_reg);
+        reg &= ~(0x3 << clk->enable_shift);
+        writel_relaxed(reg, clk->enable_reg);
+}
+struct divider {
+        struct clk *clk;
+        void __iomem *reg;
+        u32 bp_pred;
+        u32 bm_pred;
+        u32 bp_podf;
+        u32 bm_podf;
+};
+#define DEF_CLK_DIV1(d, c, r, b)                                \
+        static struct divider d = {                             \
+                .clk = c,                                       \
+                .reg = r,                                       \
+                .bp_podf = BP_##r##_##b##_PODF,                 \
+                .bm_podf = BM_##r##_##b##_PODF,                 \
+        }
+DEF_CLK_DIV1(arm_div,           &arm_clk,               CACRR,  ARM);
+DEF_CLK_DIV1(ipg_div,           &ipg_clk,               CBCDR,  IPG);
+DEF_CLK_DIV1(ahb_div,           &ahb_clk,               CBCDR,  AHB);
+DEF_CLK_DIV1(axi_div,           &axi_clk,               CBCDR,  AXI);
+DEF_CLK_DIV1(mmdc_ch0_axi_div,  &mmdc_ch0_axi_clk,      CBCDR,  MMDC_CH0_AXI);
+DEF_CLK_DIV1(mmdc_ch1_axi_div,  &mmdc_ch1_axi_clk,      CBCDR,  MMDC_CH1_AXI);
+DEF_CLK_DIV1(periph_clk2_div,   &periph_clk2_clk,       CBCDR,  PERIPH_CLK2);
+DEF_CLK_DIV1(periph2_clk2_div,  &periph2_clk2_clk,      CBCDR,  PERIPH2_CLK2);
+DEF_CLK_DIV1(gpu2d_core_div,    &gpu2d_core_clk,        CBCMR,  GPU2D_CORE);
+DEF_CLK_DIV1(gpu3d_core_div,    &gpu3d_core_clk,        CBCMR,  GPU3D_CORE);
+DEF_CLK_DIV1(gpu3d_shader_div,  &gpu3d_shader_clk,      CBCMR,  GPU3D_SHADER);
+DEF_CLK_DIV1(ipg_perclk_div,    &ipg_perclk,            CSCMR1, PERCLK);
+DEF_CLK_DIV1(emi_div,           &emi_clk,               CSCMR1, EMI);
+DEF_CLK_DIV1(emi_slow_div,      &emi_slow_clk,          CSCMR1, EMI_SLOW);
+DEF_CLK_DIV1(can_div,           &can1_clk,              CSCMR2, CAN);
+DEF_CLK_DIV1(uart_div,          &uart_clk,              CSCDR1, UART);
+DEF_CLK_DIV1(usdhc1_div,        &usdhc1_clk,            CSCDR1, USDHC1);
+DEF_CLK_DIV1(usdhc2_div,        &usdhc2_clk,            CSCDR1, USDHC2);
+DEF_CLK_DIV1(usdhc3_div,        &usdhc3_clk,            CSCDR1, USDHC3);
+DEF_CLK_DIV1(usdhc4_div,        &usdhc4_clk,            CSCDR1, USDHC4);
+DEF_CLK_DIV1(vpu_div,           &vpu_clk,               CSCDR1, VPU_AXI);
+DEF_CLK_DIV1(hsi_tx_div,        &hsi_tx_clk,            CDCDR,  HSI_TX);
+DEF_CLK_DIV1(ipu1_di0_pre_div,  &ipu1_di0_pre_clk,      CHSCCDR, IPU1_DI0_PRE);
+DEF_CLK_DIV1(ipu1_di1_pre_div,  &ipu1_di1_pre_clk,      CHSCCDR, IPU1_DI1_PRE);
+DEF_CLK_DIV1(ipu2_di0_pre_div,  &ipu2_di0_pre_clk,      CSCDR2, IPU2_DI0_PRE);
+DEF_CLK_DIV1(ipu2_di1_pre_div,  &ipu2_di1_pre_clk,      CSCDR2, IPU2_DI1_PRE);
+DEF_CLK_DIV1(ipu1_div,          &ipu1_clk,              CSCDR3, IPU1_HSP);
+DEF_CLK_DIV1(ipu2_div,          &ipu2_clk,              CSCDR3, IPU2_HSP);
+#define DEF_CLK_DIV2(d, c, r, b)                                \
+        static struct divider d = {                             \
+                .clk = c,                                       \
+                .reg = r,                                       \
+                .bp_pred = BP_##r##_##b##_PRED,                 \
+                .bm_pred = BM_##r##_##b##_PRED,                 \
+                .bp_podf = BP_##r##_##b##_PODF,                 \
+                .bm_podf = BM_##r##_##b##_PODF,                 \
+        }
+DEF_CLK_DIV2(ssi1_div,          &ssi1_clk,              CS1CDR, SSI1);
+DEF_CLK_DIV2(ssi3_div,          &ssi3_clk,              CS1CDR, SSI3);
+DEF_CLK_DIV2(esai_div,          &esai_clk,              CS1CDR, ESAI);
+DEF_CLK_DIV2(ssi2_div,          &ssi2_clk,              CS2CDR, SSI2);
+DEF_CLK_DIV2(enfc_div,          &enfc_clk,              CS2CDR, ENFC);
+DEF_CLK_DIV2(spdif_div,         &spdif_clk,             CDCDR,  SPDIF);
+DEF_CLK_DIV2(asrc_serial_div,   &asrc_serial_clk,       CDCDR,  ASRC_SERIAL);
+static struct divider *dividers[] = {
+        &arm_div,
+        &ipg_div,
+        &ahb_div,
+        &axi_div,
+        &mmdc_ch0_axi_div,
+        &mmdc_ch1_axi_div,
+        &periph_clk2_div,
+        &periph2_clk2_div,
+        &gpu2d_core_div,
+        &gpu3d_core_div,
+        &gpu3d_shader_div,
+        &ipg_perclk_div,
+        &emi_div,
+        &emi_slow_div,
+        &can_div,
+        &uart_div,
+        &usdhc1_div,
+        &usdhc2_div,
+        &usdhc3_div,
+        &usdhc4_div,
+        &vpu_div,
+        &hsi_tx_div,
+        &ipu1_di0_pre_div,
+        &ipu1_di1_pre_div,
+        &ipu2_di0_pre_div,
+        &ipu2_di1_pre_div,
+        &ipu1_div,
+        &ipu2_div,
+        &ssi1_div,
+        &ssi3_div,
+        &esai_div,
+        &ssi2_div,
+        &enfc_div,
+        &spdif_div,
+        &asrc_serial_div,
+};
+static unsigned long ldb_di_clk_get_rate(struct clk *clk)
+{
+        u32 val = readl_relaxed(CSCMR2);
+        val &= (clk == &ldb_di0_clk) ? BM_CSCMR2_LDB_DI0_IPU_DIV :
+                                       BM_CSCMR2_LDB_DI1_IPU_DIV;
+        if (val)
+                return clk_get_rate(clk->parent) / 7;
+        else
+                return clk_get_rate(clk->parent) * 2 / 7;
+}
+static int ldb_di_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        u32 val = readl_relaxed(CSCMR2);
+        if (rate * 7 <= parent_rate + parent_rate / 20)
+                val |= BM_CSCMR2_LDB_DI0_IPU_DIV;
+        else
+                val &= ~BM_CSCMR2_LDB_DI0_IPU_DIV;
+        writel_relaxed(val, CSCMR2);
+        return 0;
+}
+static unsigned long ldb_di_clk_round_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        if (rate * 7 <= parent_rate + parent_rate / 20)
+                return parent_rate / 7;
+        else
+                return 2 * parent_rate / 7;
+}
+static unsigned long _clk_get_rate(struct clk *clk)
+{
+        struct divider *d;
+        u32 val, pred, podf;
+        int i, num;
+        if (clk == &ldb_di0_clk || clk == &ldb_di1_clk)
+                return ldb_di_clk_get_rate(clk);
+        num = ARRAY_SIZE(dividers);
+        for (i = 0; i < num; i++)
+                if (dividers[i]->clk == clk) {
+                        d = dividers[i];
+                        break;
+                }
+        if (i == num)
+                return clk_get_rate(clk->parent);
+        val = readl_relaxed(d->reg);
+        pred = ((val & d->bm_pred) >> d->bp_pred) + 1;
+        podf = ((val & d->bm_podf) >> d->bp_podf) + 1;
+        return clk_get_rate(clk->parent) / (pred * podf);
+}
+static int clk_busy_wait(struct clk *clk)
+{
+        int timeout = 0x100000;
+        u32 bm;
+        if (clk == &axi_clk)
+                bm = BM_CDHIPR_AXI_PODF_BUSY;
+        else if (clk == &ahb_clk)
+                bm = BM_CDHIPR_AHB_PODF_BUSY;
+        else if (clk == &mmdc_ch0_axi_clk)
+                bm = BM_CDHIPR_MMDC_CH0_PODF_BUSY;
+        else if (clk == &periph_clk)
+                bm = BM_CDHIPR_PERIPH_SEL_BUSY;
+        else if (clk == &arm_clk)
+                bm = BM_CDHIPR_ARM_PODF_BUSY;
+        else
+                return -EINVAL;
+        while ((readl_relaxed(CDHIPR) & bm) && --timeout)
+                cpu_relax();
+        if (unlikely(!timeout))
+                return -EBUSY;
+        return 0;
+}
+static int _clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        struct divider *d;
+        u32 val, div, max_div, pred = 0, podf;
+        int i, num;
+        if (clk == &ldb_di0_clk || clk == &ldb_di1_clk)
+                return ldb_di_clk_set_rate(clk, rate);
+        num = ARRAY_SIZE(dividers);
+        for (i = 0; i < num; i++)
+                if (dividers[i]->clk == clk) {
+                        d = dividers[i];
+                        break;
+                }
+        if (i == num)
+                return -EINVAL;
+        max_div = ((d->bm_pred >> d->bp_pred) + 1) *
+                  ((d->bm_pred >> d->bp_pred) + 1);
+        div = parent_rate / rate;
+        if (div == 0)
+                div++;
+        if ((parent_rate / div != rate) || div > max_div)
+                return -EINVAL;
+        if (d->bm_pred) {
+                calc_pred_podf_dividers(div, &pred, &podf);
+        } else {
+                pred = 1;
+                podf = div;
+        }
+        val = readl_relaxed(d->reg);
+        val &= ~(d->bm_pred | d->bm_podf);
+        val |= (pred - 1) << d->bp_pred | (podf - 1) << d->bp_podf;
+        writel_relaxed(val, d->reg);
+        if (clk == &axi_clk || clk == &ahb_clk ||
+            clk == &mmdc_ch0_axi_clk || clk == &arm_clk)
+                return clk_busy_wait(clk);
+        return 0;
+}
+static unsigned long _clk_round_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        u32 div = parent_rate / rate;
+        u32 div_max, pred = 0, podf;
+        struct divider *d;
+        int i, num;
+        if (clk == &ldb_di0_clk || clk == &ldb_di1_clk)
+                return ldb_di_clk_round_rate(clk, rate);
+        num = ARRAY_SIZE(dividers);
+        for (i = 0; i < num; i++)
+                if (dividers[i]->clk == clk) {
+                        d = dividers[i];
+                        break;
+                }
+        if (i == num)
+                return -EINVAL;
+        if (div == 0 || parent_rate % rate)
+                div++;
+        if (d->bm_pred) {
+                calc_pred_podf_dividers(div, &pred, &podf);
+                div = pred * podf;
+        } else {
+                div_max = (d->bm_podf >> d->bp_podf) + 1;
+                if (div > div_max)
+                        div = div_max;
+        }
+        return parent_rate / div;
+}
+struct multiplexer {
+        struct clk *clk;
+        void __iomem *reg;
+        u32 bp;
+        u32 bm;
+        int pnum;
+        struct clk *parents[];
+};
+static struct multiplexer axi_mux = {
+        .clk = &axi_clk,
+        .reg = CBCDR,
+        .bp = BP_CBCDR_AXI_SEL,
+        .bm = BM_CBCDR_AXI_SEL,
+        .parents = {
+                &periph_clk,
+                &pll2_pfd_400m,
+                &pll3_pfd_540m,
+                NULL
+        },
+};
+static struct multiplexer periph_mux = {
+        .clk = &periph_clk,
+        .reg = CBCDR,
+        .bp = BP_CBCDR_PERIPH_CLK_SEL,
+        .bm = BM_CBCDR_PERIPH_CLK_SEL,
+        .parents = {
+                &periph_pre_clk,
+                &periph_clk2_clk,
+                NULL
+        },
+};
+static struct multiplexer periph_pre_mux = {
+        .clk = &periph_pre_clk,
+        .reg = CBCMR,
+        .bp = BP_CBCMR_PRE_PERIPH_CLK_SEL,
+        .bm = BM_CBCMR_PRE_PERIPH_CLK_SEL,
+        .parents = {
+                &pll2_bus,
+                &pll2_pfd_400m,
+                &pll2_pfd_352m,
+                &pll2_200m,
+                NULL
+        },
+};
+static struct multiplexer periph_clk2_mux = {
+        .clk = &periph_clk2_clk,
+        .reg = CBCMR,
+        .bp = BP_CBCMR_PERIPH_CLK2_SEL,
+        .bm = BM_CBCMR_PERIPH_CLK2_SEL,
+        .parents = {
+                &pll3_usb_otg,
+                &osc_clk,
+                NULL
+        },
+};
+static struct multiplexer periph2_mux = {
+        .clk = &periph2_clk,
+        .reg = CBCDR,
+        .bp = BP_CBCDR_PERIPH2_CLK_SEL,
+        .bm = BM_CBCDR_PERIPH2_CLK_SEL,
+        .parents = {
+                &periph2_pre_clk,
+                &periph2_clk2_clk,
+                NULL
+        },
+};
+static struct multiplexer periph2_pre_mux = {
+        .clk = &periph2_pre_clk,
+        .reg = CBCMR,
+        .bp = BP_CBCMR_PRE_PERIPH2_CLK_SEL,
+        .bm = BM_CBCMR_PRE_PERIPH2_CLK_SEL,
+        .parents = {
+                &pll2_bus,
+                &pll2_pfd_400m,
+                &pll2_pfd_352m,
+                &pll2_200m,
+                NULL
+        },
+};
+static struct multiplexer periph2_clk2_mux = {
+        .clk = &periph2_clk2_clk,
+        .reg = CBCMR,
+        .bp = BP_CBCMR_PERIPH2_CLK2_SEL,
+        .bm = BM_CBCMR_PERIPH2_CLK2_SEL,
+        .parents = {
+                &pll3_usb_otg,
+                &osc_clk,
+                NULL
+        },
+};
+static struct multiplexer gpu2d_axi_mux = {
+        .clk = &gpu2d_axi_clk,
+        .reg = CBCMR,
+        .bp = BP_CBCMR_GPU2D_AXI_SEL,
+        .bm = BM_CBCMR_GPU2D_AXI_SEL,
+        .parents = {
+                &axi_clk,
+                &ahb_clk,
+                NULL
+        },
+};
+static struct multiplexer gpu3d_axi_mux = {
+        .clk = &gpu3d_axi_clk,
+        .reg = CBCMR,
+        .bp = BP_CBCMR_GPU3D_AXI_SEL,
+        .bm = BM_CBCMR_GPU3D_AXI_SEL,
+        .parents = {
+                &axi_clk,
+                &ahb_clk,
+                NULL
+        },
+};
+static struct multiplexer gpu3d_core_mux = {
+        .clk = &gpu3d_core_clk,
+        .reg = CBCMR,
+        .bp = BP_CBCMR_GPU3D_CORE_SEL,
+        .bm = BM_CBCMR_GPU3D_CORE_SEL,
+        .parents = {
+                &mmdc_ch0_axi_clk,
+                &pll3_usb_otg,
+                &pll2_pfd_594m,
+                &pll2_pfd_400m,
+                NULL
+        },
+};
+static struct multiplexer gpu3d_shader_mux = {
+        .clk = &gpu3d_shader_clk,
+        .reg = CBCMR,
+        .bp = BP_CBCMR_GPU3D_SHADER_SEL,
+        .bm = BM_CBCMR_GPU3D_SHADER_SEL,
+        .parents = {
+                &mmdc_ch0_axi_clk,
+                &pll3_usb_otg,
+                &pll2_pfd_594m,
+                &pll3_pfd_720m,
+                NULL
+        },
+};
+static struct multiplexer pcie_axi_mux = {
+        .clk = &pcie_clk,
+        .reg = CBCMR,
+        .bp = BP_CBCMR_PCIE_AXI_SEL,
+        .bm = BM_CBCMR_PCIE_AXI_SEL,
+        .parents = {
+                &axi_clk,
+                &ahb_clk,
+                NULL
+        },
+};
+static struct multiplexer vdo_axi_mux = {
+        .clk = &vdo_axi_clk,
+        .reg = CBCMR,
+        .bp = BP_CBCMR_VDO_AXI_SEL,
+        .bm = BM_CBCMR_VDO_AXI_SEL,
+        .parents = {
+                &axi_clk,
+                &ahb_clk,
+                NULL
+        },
+};
+static struct multiplexer vpu_axi_mux = {
+        .clk = &vpu_clk,
+        .reg = CBCMR,
+        .bp = BP_CBCMR_VPU_AXI_SEL,
+        .bm = BM_CBCMR_VPU_AXI_SEL,
+        .parents = {
+                &axi_clk,
+                &pll2_pfd_400m,
+                &pll2_pfd_352m,
+                NULL
+        },
+};
+static struct multiplexer gpu2d_core_mux = {
+        .clk = &gpu2d_core_clk,
+        .reg = CBCMR,
+        .bp = BP_CBCMR_GPU2D_CORE_SEL,
+        .bm = BM_CBCMR_GPU2D_CORE_SEL,
+        .parents = {
+                &axi_clk,
+                &pll3_usb_otg,
+                &pll2_pfd_352m,
+                &pll2_pfd_400m,
+                NULL
+        },
+};
+#define DEF_SSI_MUX(id)                                                 \
+        static struct multiplexer ssi##id##_mux = {                     \
+                .clk = &ssi##id##_clk,                                  \
+                .reg = CSCMR1,                                          \
+                .bp = BP_CSCMR1_SSI##id##_SEL,                          \
+                .bm = BM_CSCMR1_SSI##id##_SEL,                          \
+                .parents = {                                            \
+                        &pll3_pfd_508m,                                 \
+                        &pll3_pfd_454m,                                 \
+                        &pll4_audio,                                    \
+                        NULL                                            \
+                },                                                      \
+        }
+DEF_SSI_MUX(1);
+DEF_SSI_MUX(2);
+DEF_SSI_MUX(3);
+#define DEF_USDHC_MUX(id)                                               \
+        static struct multiplexer usdhc##id##_mux = {                   \
+                .clk = &usdhc##id##_clk,                                \
+                .reg = CSCMR1,                                          \
+                .bp = BP_CSCMR1_USDHC##id##_SEL,                        \
+                .bm = BM_CSCMR1_USDHC##id##_SEL,                        \
+                .parents = {                                            \
+                        &pll2_pfd_400m,                                 \
+                        &pll2_pfd_352m,                                 \
+                        NULL                                            \
+                },                                                      \
+        }
+DEF_USDHC_MUX(1);
+DEF_USDHC_MUX(2);
+DEF_USDHC_MUX(3);
+DEF_USDHC_MUX(4);
+static struct multiplexer emi_mux = {
+        .clk = &emi_clk,
+        .reg = CSCMR1,
+        .bp = BP_CSCMR1_EMI_SEL,
+        .bm = BM_CSCMR1_EMI_SEL,
+        .parents = {
+                &axi_clk,
+                &pll3_usb_otg,
+                &pll2_pfd_400m,
+                &pll2_pfd_352m,
+                NULL
+        },
+};
+static struct multiplexer emi_slow_mux = {
+        .clk = &emi_slow_clk,
+        .reg = CSCMR1,
+        .bp = BP_CSCMR1_EMI_SLOW_SEL,
+        .bm = BM_CSCMR1_EMI_SLOW_SEL,
+        .parents = {
+                &axi_clk,
+                &pll3_usb_otg,
+                &pll2_pfd_400m,
+                &pll2_pfd_352m,
+                NULL
+        },
+};
+static struct multiplexer esai_mux = {
+        .clk = &esai_clk,
+        .reg = CSCMR2,
+        .bp = BP_CSCMR2_ESAI_SEL,
+        .bm = BM_CSCMR2_ESAI_SEL,
+        .parents = {
+                &pll4_audio,
+                &pll3_pfd_508m,
+                &pll3_pfd_454m,
+                &pll3_usb_otg,
+                NULL
+        },
+};
+#define DEF_LDB_DI_MUX(id)                                              \
+        static struct multiplexer ldb_di##id##_mux = {                  \
+                .clk = &ldb_di##id##_clk,                               \
+                .reg = CS2CDR,                                          \
+                .bp = BP_CS2CDR_LDB_DI##id##_SEL,                       \
+                .bm = BM_CS2CDR_LDB_DI##id##_SEL,                       \
+                .parents = {                                            \
+                        &pll5_video,                                    \
+                        &pll2_pfd_352m,                                 \
+                        &pll2_pfd_400m,                                 \
+                        &pll3_pfd_540m,                                 \
+                        &pll3_usb_otg,                                  \
+                        NULL                                            \
+                },                                                      \
+        }
+DEF_LDB_DI_MUX(0);
+DEF_LDB_DI_MUX(1);
+static struct multiplexer enfc_mux = {
+        .clk = &enfc_clk,
+        .reg = CS2CDR,
+        .bp = BP_CS2CDR_ENFC_SEL,
+        .bm = BM_CS2CDR_ENFC_SEL,
+        .parents = {
+                &pll2_pfd_352m,
+                &pll2_bus,
+                &pll3_usb_otg,
+                &pll2_pfd_400m,
+                NULL
+        },
+};
+static struct multiplexer spdif_mux = {
+        .clk = &spdif_clk,
+        .reg = CDCDR,
+        .bp = BP_CDCDR_SPDIF_SEL,
+        .bm = BM_CDCDR_SPDIF_SEL,
+        .parents = {
+                &pll4_audio,
+                &pll3_pfd_508m,
+                &pll3_pfd_454m,
+                &pll3_usb_otg,
+                NULL
+        },
+};
+static struct multiplexer asrc_serial_mux = {
+        .clk = &asrc_serial_clk,
+        .reg = CDCDR,
+        .bp = BP_CDCDR_ASRC_SERIAL_SEL,
+        .bm = BM_CDCDR_ASRC_SERIAL_SEL,
+        .parents = {
+                &pll4_audio,
+                &pll3_pfd_508m,
+                &pll3_pfd_454m,
+                &pll3_usb_otg,
+                NULL
+        },
+};
+static struct multiplexer hsi_tx_mux = {
+        .clk = &hsi_tx_clk,
+        .reg = CDCDR,
+        .bp = BP_CDCDR_HSI_TX_SEL,
+        .bm = BM_CDCDR_HSI_TX_SEL,
+        .parents = {
+                &pll3_120m,
+                &pll2_pfd_400m,
+                NULL
+        },
+};
+#define DEF_IPU_DI_PRE_MUX(r, i, d)                                     \
+        static struct multiplexer ipu##i##_di##d##_pre_mux = {          \
+                .clk = &ipu##i##_di##d##_pre_clk,                       \
+                .reg = r,                                               \
+                .bp = BP_##r##_IPU##i##_DI##d##_PRE_SEL,                \
+                .bm = BM_##r##_IPU##i##_DI##d##_PRE_SEL,                \
+                .parents = {                                            \
+                        &mmdc_ch0_axi_clk,                              \
+                        &pll3_usb_otg,                                  \
+                        &pll5_video,                                    \
+                        &pll2_pfd_352m,                                 \
+                        &pll2_pfd_400m,                                 \
+                        &pll3_pfd_540m,                                 \
+                        NULL                                            \
+                },                                                      \
+        }
+DEF_IPU_DI_PRE_MUX(CHSCCDR, 1, 0);
+DEF_IPU_DI_PRE_MUX(CHSCCDR, 1, 1);
+DEF_IPU_DI_PRE_MUX(CSCDR2, 2, 0);
+DEF_IPU_DI_PRE_MUX(CSCDR2, 2, 1);
+#define DEF_IPU_DI_MUX(r, i, d)                                         \
+        static struct multiplexer ipu##i##_di##d##_mux = {              \
+                .clk = &ipu##i##_di##d##_clk,                           \
+                .reg = r,                                               \
+                .bp = BP_##r##_IPU##i##_DI##d##_SEL,                    \
+                .bm = BM_##r##_IPU##i##_DI##d##_SEL,                    \
+                .parents = {                                            \
+                        &ipu##i##_di##d##_pre_clk,                      \
+                        &dummy_clk,                                     \
+                        &dummy_clk,                                     \
+                        &ldb_di0_clk,                                   \
+                        &ldb_di1_clk,                                   \
+                        NULL                                            \
+                },                                                      \
+        }
+DEF_IPU_DI_MUX(CHSCCDR, 1, 0);
+DEF_IPU_DI_MUX(CHSCCDR, 1, 1);
+DEF_IPU_DI_MUX(CSCDR2, 2, 0);
+DEF_IPU_DI_MUX(CSCDR2, 2, 1);
+#define DEF_IPU_MUX(id)                                                 \
+        static struct multiplexer ipu##id##_mux = {                     \
+                .clk = &ipu##id##_clk,                                  \
+                .reg = CSCDR3,                                          \
+                .bp = BP_CSCDR3_IPU##id##_HSP_SEL,                      \
+                .bm = BM_CSCDR3_IPU##id##_HSP_SEL,                      \
+                .parents = {                                            \
+                        &mmdc_ch0_axi_clk,                              \
+                        &pll2_pfd_400m,                                 \
+                        &pll3_120m,                                     \
+                        &pll3_pfd_540m,                                 \
+                        NULL                                            \
+                },                                                      \
+        }
+DEF_IPU_MUX(1);
+DEF_IPU_MUX(2);
+static struct multiplexer *multiplexers[] = {
+        &axi_mux,
+        &periph_mux,
+        &periph_pre_mux,
+        &periph_clk2_mux,
+        &periph2_mux,
+        &periph2_pre_mux,
+        &periph2_clk2_mux,
+        &gpu2d_axi_mux,
+        &gpu3d_axi_mux,
+        &gpu3d_core_mux,
+        &gpu3d_shader_mux,
+        &pcie_axi_mux,
+        &vdo_axi_mux,
+        &vpu_axi_mux,
+        &gpu2d_core_mux,
+        &ssi1_mux,
+        &ssi2_mux,
+        &ssi3_mux,
+        &usdhc1_mux,
+        &usdhc2_mux,
+        &usdhc3_mux,
+        &usdhc4_mux,
+        &emi_mux,
+        &emi_slow_mux,
+        &esai_mux,
+        &ldb_di0_mux,
+        &ldb_di1_mux,
+        &enfc_mux,
+        &spdif_mux,
+        &asrc_serial_mux,
+        &hsi_tx_mux,
+        &ipu1_di0_pre_mux,
+        &ipu1_di0_mux,
+        &ipu1_di1_pre_mux,
+        &ipu1_di1_mux,
+        &ipu2_di0_pre_mux,
+        &ipu2_di0_mux,
+        &ipu2_di1_pre_mux,
+        &ipu2_di1_mux,
+        &ipu1_mux,
+        &ipu2_mux,
+};
+static int _clk_set_parent(struct clk *clk, struct clk *parent)
+{
+        struct multiplexer *m;
+        int i, num;
+        u32 val;
+        num = ARRAY_SIZE(multiplexers);
+        for (i = 0; i < num; i++)
+                if (multiplexers[i]->clk == clk) {
+                        m = multiplexers[i];
+                        break;
+                }
+        if (i == num)
+                return -EINVAL;
+        i = 0;
+        while (m->parents[i]) {
+                if (parent == m->parents[i])
+                        break;
+                i++;
+        }
+        if (!m->parents[i])
+                return -EINVAL;
+        val = readl_relaxed(m->reg);
+        val &= ~m->bm;
+        val |= i << m->bp;
+        writel_relaxed(val, m->reg);
+        if (clk == &periph_clk)
+                return clk_busy_wait(clk);
+        return 0;
+}
+#define DEF_NG_CLK(name, p)                             \
+        static struct clk name = {                      \
+                .get_rate       = _clk_get_rate,        \
+                .set_rate       = _clk_set_rate,        \
+                .round_rate     = _clk_round_rate,      \
+                .set_parent     = _clk_set_parent,      \
+                .parent         = p,                    \
+        }
+DEF_NG_CLK(periph_clk2_clk,     &osc_clk);
+DEF_NG_CLK(periph_pre_clk,      &pll2_bus);
+DEF_NG_CLK(periph_clk,          &periph_pre_clk);
+DEF_NG_CLK(periph2_clk2_clk,    &osc_clk);
+DEF_NG_CLK(periph2_pre_clk,     &pll2_bus);
+DEF_NG_CLK(periph2_clk,         &periph2_pre_clk);
+DEF_NG_CLK(axi_clk,             &periph_clk);
+DEF_NG_CLK(emi_clk,             &axi_clk);
+DEF_NG_CLK(arm_clk,             &pll1_sw_clk);
+DEF_NG_CLK(ahb_clk,             &periph_clk);
+DEF_NG_CLK(ipg_clk,             &ahb_clk);
+DEF_NG_CLK(ipg_perclk,          &ipg_clk);
+DEF_NG_CLK(ipu1_di0_pre_clk,    &pll3_pfd_540m);
+DEF_NG_CLK(ipu1_di1_pre_clk,    &pll3_pfd_540m);
+DEF_NG_CLK(ipu2_di0_pre_clk,    &pll3_pfd_540m);
+DEF_NG_CLK(ipu2_di1_pre_clk,    &pll3_pfd_540m);
+DEF_NG_CLK(asrc_serial_clk,     &pll3_usb_otg);
+#define DEF_CLK(name, er, es, p, s)                     \
+        static struct clk name = {                      \
+                .enable_reg     = er,                   \
+                .enable_shift   = es,                   \
+                .enable         = _clk_enable,          \
+                .disable        = _clk_disable,         \
+                .get_rate       = _clk_get_rate,        \
+                .set_rate       = _clk_set_rate,        \
+                .round_rate     = _clk_round_rate,      \
+                .set_parent     = _clk_set_parent,      \
+                .parent         = p,                    \
+                .secondary      = s,                    \
+        }
+DEF_CLK(aips_tz1_clk,     CCGR0, CG0,  &ahb_clk,          NULL);
+DEF_CLK(aips_tz2_clk,     CCGR0, CG1,  &ahb_clk,          NULL);
+DEF_CLK(apbh_dma_clk,     CCGR0, CG2,  &ahb_clk,          NULL);
+DEF_CLK(asrc_clk,         CCGR0, CG3,  &pll4_audio,       NULL);
+DEF_CLK(can1_serial_clk,  CCGR0, CG8,  &pll3_usb_otg,     NULL);
+DEF_CLK(can1_clk,         CCGR0, CG7,  &pll3_usb_otg,     &can1_serial_clk);
+DEF_CLK(can2_serial_clk,  CCGR0, CG10, &pll3_usb_otg,     NULL);
+DEF_CLK(can2_clk,         CCGR0, CG9,  &pll3_usb_otg,     &can2_serial_clk);
+DEF_CLK(ecspi1_clk,       CCGR1, CG0,  &pll3_60m,         NULL);
+DEF_CLK(ecspi2_clk,       CCGR1, CG1,  &pll3_60m,         NULL);
+DEF_CLK(ecspi3_clk,       CCGR1, CG2,  &pll3_60m,         NULL);
+DEF_CLK(ecspi4_clk,       CCGR1, CG3,  &pll3_60m,         NULL);
+DEF_CLK(ecspi5_clk,       CCGR1, CG4,  &pll3_60m,         NULL);
+DEF_CLK(enet_clk,         CCGR1, CG5,  &ipg_clk,          NULL);
+DEF_CLK(esai_clk,         CCGR1, CG8,  &pll3_usb_otg,     NULL);
+DEF_CLK(gpt_serial_clk,   CCGR1, CG11, &ipg_perclk,       NULL);
+DEF_CLK(gpt_clk,          CCGR1, CG10, &ipg_perclk,       &gpt_serial_clk);
+DEF_CLK(gpu2d_core_clk,   CCGR1, CG12, &pll2_pfd_352m,    &gpu2d_axi_clk);
+DEF_CLK(gpu3d_core_clk,   CCGR1, CG13, &pll2_pfd_594m,    &gpu3d_axi_clk);
+DEF_CLK(gpu3d_shader_clk, CCGR1, CG13, &pll3_pfd_720m,    &gpu3d_axi_clk);
+DEF_CLK(hdmi_iahb_clk,    CCGR2, CG0,  &ahb_clk,          NULL);
+DEF_CLK(hdmi_isfr_clk,    CCGR2, CG2,  &pll3_pfd_540m,    &hdmi_iahb_clk);
+DEF_CLK(i2c1_clk,         CCGR2, CG3,  &ipg_perclk,       NULL);
+DEF_CLK(i2c2_clk,         CCGR2, CG4,  &ipg_perclk,       NULL);
+DEF_CLK(i2c3_clk,         CCGR2, CG5,  &ipg_perclk,       NULL);
+DEF_CLK(iim_clk,          CCGR2, CG6,  &ipg_clk,          NULL);
+DEF_CLK(enfc_clk,         CCGR2, CG7,  &pll2_pfd_352m,    NULL);
+DEF_CLK(ipu1_clk,         CCGR3, CG0,  &mmdc_ch0_axi_clk, NULL);
+DEF_CLK(ipu1_di0_clk,     CCGR3, CG1,  &ipu1_di0_pre_clk, NULL);
+DEF_CLK(ipu1_di1_clk,     CCGR3, CG2,  &ipu1_di1_pre_clk, NULL);
+DEF_CLK(ipu2_clk,         CCGR3, CG3,  &mmdc_ch0_axi_clk, NULL);
+DEF_CLK(ipu2_di0_clk,     CCGR3, CG4,  &ipu2_di0_pre_clk, NULL);
+DEF_CLK(ipu2_di1_clk,     CCGR3, CG5,  &ipu2_di1_pre_clk, NULL);
+DEF_CLK(ldb_di0_clk,      CCGR3, CG6,  &pll3_pfd_540m,    NULL);
+DEF_CLK(ldb_di1_clk,      CCGR3, CG7,  &pll3_pfd_540m,    NULL);
+DEF_CLK(hsi_tx_clk,       CCGR3, CG8,  &pll2_pfd_400m,    NULL);
+DEF_CLK(mlb_clk,          CCGR3, CG9,  &pll6_mlb,         NULL);
+DEF_CLK(mmdc_ch0_ipg_clk, CCGR3, CG12, &ipg_clk,          NULL);
+DEF_CLK(mmdc_ch0_axi_clk, CCGR3, CG10, &periph_clk,       &mmdc_ch0_ipg_clk);
+DEF_CLK(mmdc_ch1_ipg_clk, CCGR3, CG13, &ipg_clk,          NULL);
+DEF_CLK(mmdc_ch1_axi_clk, CCGR3, CG11, &periph2_clk,      &mmdc_ch1_ipg_clk);
+DEF_CLK(openvg_axi_clk,   CCGR3, CG13, &axi_clk,          NULL);
+DEF_CLK(pwm1_clk,         CCGR4, CG8,  &ipg_perclk,       NULL);
+DEF_CLK(pwm2_clk,         CCGR4, CG9,  &ipg_perclk,       NULL);
+DEF_CLK(pwm3_clk,         CCGR4, CG10, &ipg_perclk,       NULL);
+DEF_CLK(pwm4_clk,         CCGR4, CG11, &ipg_perclk,       NULL);
+DEF_CLK(gpmi_bch_apb_clk, CCGR4, CG12, &usdhc3_clk,       NULL);
+DEF_CLK(gpmi_bch_clk,     CCGR4, CG13, &usdhc4_clk,       &gpmi_bch_apb_clk);
+DEF_CLK(gpmi_apb_clk,     CCGR4, CG15, &usdhc3_clk,       &gpmi_bch_clk);
+DEF_CLK(gpmi_io_clk,      CCGR4, CG14, &enfc_clk,         &gpmi_apb_clk);
+DEF_CLK(sdma_clk,         CCGR5, CG3,  &ahb_clk,          NULL);
+DEF_CLK(spba_clk,         CCGR5, CG6,  &ipg_clk,          NULL);
+DEF_CLK(spdif_clk,        CCGR5, CG7,  &pll3_usb_otg,     &spba_clk);
+DEF_CLK(ssi1_clk,         CCGR5, CG9,  &pll3_pfd_508m,    NULL);
+DEF_CLK(ssi2_clk,         CCGR5, CG10, &pll3_pfd_508m,    NULL);
+DEF_CLK(ssi3_clk,         CCGR5, CG11, &pll3_pfd_508m,    NULL);
+DEF_CLK(uart_serial_clk,  CCGR5, CG13, &pll3_usb_otg,     NULL);
+DEF_CLK(uart_clk,         CCGR5, CG12, &pll3_80m,         &uart_serial_clk);
+DEF_CLK(usboh3_clk,       CCGR6, CG0,  &ipg_clk,          NULL);
+DEF_CLK(usdhc1_clk,       CCGR6, CG1,  &pll2_pfd_400m,    NULL);
+DEF_CLK(usdhc2_clk,       CCGR6, CG2,  &pll2_pfd_400m,    NULL);
+DEF_CLK(usdhc3_clk,       CCGR6, CG3,  &pll2_pfd_400m,    NULL);
+DEF_CLK(usdhc4_clk,       CCGR6, CG4,  &pll2_pfd_400m,    NULL);
+DEF_CLK(emi_slow_clk,     CCGR6, CG5,  &axi_clk,          NULL);
+DEF_CLK(vdo_axi_clk,      CCGR6, CG6,  &axi_clk,          NULL);
+DEF_CLK(vpu_clk,          CCGR6, CG7,  &axi_clk,          NULL);
+static int pcie_clk_enable(struct clk *clk)
+{
+        u32 val;
+        val = readl_relaxed(PLL8_ENET);
+        val |= BM_PLL_ENET_EN_PCIE;
+        writel_relaxed(val, PLL8_ENET);
+        return _clk_enable(clk);
+}
+static void pcie_clk_disable(struct clk *clk)
+{
+        u32 val;
+        _clk_disable(clk);
+        val = readl_relaxed(PLL8_ENET);
+        val &= BM_PLL_ENET_EN_PCIE;
+        writel_relaxed(val, PLL8_ENET);
+}
+static struct clk pcie_clk = {
+        .enable_reg = CCGR4,
+        .enable_shift = CG0,
+        .enable = pcie_clk_enable,
+        .disable = pcie_clk_disable,
+        .set_parent = _clk_set_parent,
+        .parent = &axi_clk,
+        .secondary = &pll8_enet,
+};
+static int sata_clk_enable(struct clk *clk)
+{
+        u32 val;
+        val = readl_relaxed(PLL8_ENET);
+        val |= BM_PLL_ENET_EN_SATA;
+        writel_relaxed(val, PLL8_ENET);
+        return _clk_enable(clk);
+}
+static void sata_clk_disable(struct clk *clk)
+{
+        u32 val;
+        _clk_disable(clk);
+        val = readl_relaxed(PLL8_ENET);
+        val &= BM_PLL_ENET_EN_SATA;
+        writel_relaxed(val, PLL8_ENET);
+}
+static struct clk sata_clk = {
+        .enable_reg = CCGR5,
+        .enable_shift = CG2,
+        .enable = sata_clk_enable,
+        .disable = sata_clk_disable,
+        .parent = &ipg_clk,
+        .secondary = &pll8_enet,
+};
+#define _REGISTER_CLOCK(d, n, c) \
+        { \
+                .dev_id = d, \
+                .con_id = n, \
+                .clk = &c, \
+        }
+static struct clk_lookup lookups[] = {
+        _REGISTER_CLOCK("2020000.uart", NULL, uart_clk),
+        _REGISTER_CLOCK("21e8000.uart", NULL, uart_clk),
+        _REGISTER_CLOCK("21ec000.uart", NULL, uart_clk),
+        _REGISTER_CLOCK("21f0000.uart", NULL, uart_clk),
+        _REGISTER_CLOCK("21f4000.uart", NULL, uart_clk),
+        _REGISTER_CLOCK("2188000.enet", NULL, enet_clk),
+        _REGISTER_CLOCK("2190000.usdhc", NULL, usdhc1_clk),
+        _REGISTER_CLOCK("2194000.usdhc", NULL, usdhc2_clk),
+        _REGISTER_CLOCK("2198000.usdhc", NULL, usdhc3_clk),
+        _REGISTER_CLOCK("219c000.usdhc", NULL, usdhc4_clk),
+        _REGISTER_CLOCK("21a0000.i2c", NULL, i2c1_clk),
+        _REGISTER_CLOCK("21a4000.i2c", NULL, i2c2_clk),
+        _REGISTER_CLOCK("21a8000.i2c", NULL, i2c3_clk),
+        _REGISTER_CLOCK("2008000.ecspi", NULL, ecspi1_clk),
+        _REGISTER_CLOCK("200c000.ecspi", NULL, ecspi2_clk),
+        _REGISTER_CLOCK("2010000.ecspi", NULL, ecspi3_clk),
+        _REGISTER_CLOCK("2014000.ecspi", NULL, ecspi4_clk),
+        _REGISTER_CLOCK("2018000.ecspi", NULL, ecspi5_clk),
+        _REGISTER_CLOCK("20ec000.sdma", NULL, sdma_clk),
+        _REGISTER_CLOCK("20bc000.wdog", NULL, dummy_clk),
+        _REGISTER_CLOCK("20c0000.wdog", NULL, dummy_clk),
+        _REGISTER_CLOCK(NULL, "ckih", ckih_clk),
+        _REGISTER_CLOCK(NULL, "ckil_clk", ckil_clk),
+        _REGISTER_CLOCK(NULL, "aips_tz1_clk", aips_tz1_clk),
+        _REGISTER_CLOCK(NULL, "aips_tz2_clk", aips_tz2_clk),
+        _REGISTER_CLOCK(NULL, "asrc_clk", asrc_clk),
+        _REGISTER_CLOCK(NULL, "can2_clk", can2_clk),
+        _REGISTER_CLOCK(NULL, "hdmi_isfr_clk", hdmi_isfr_clk),
+        _REGISTER_CLOCK(NULL, "iim_clk", iim_clk),
+        _REGISTER_CLOCK(NULL, "mlb_clk", mlb_clk),
+        _REGISTER_CLOCK(NULL, "openvg_axi_clk", openvg_axi_clk),
+        _REGISTER_CLOCK(NULL, "pwm1_clk", pwm1_clk),
+        _REGISTER_CLOCK(NULL, "pwm2_clk", pwm2_clk),
+        _REGISTER_CLOCK(NULL, "pwm3_clk", pwm3_clk),
+        _REGISTER_CLOCK(NULL, "pwm4_clk", pwm4_clk),
+        _REGISTER_CLOCK(NULL, "gpmi_io_clk", gpmi_io_clk),
+        _REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk),
+        _REGISTER_CLOCK(NULL, "sata_clk", sata_clk),
+};
+int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
+{
+        u32 val = readl_relaxed(CLPCR);
+        val &= ~BM_CLPCR_LPM;
+        switch (mode) {
+        case WAIT_CLOCKED:
+                break;
+        case WAIT_UNCLOCKED:
+                val |= 0x1 << BP_CLPCR_LPM;
+                break;
+        case STOP_POWER_ON:
+                val |= 0x2 << BP_CLPCR_LPM;
+                break;
+        case WAIT_UNCLOCKED_POWER_OFF:
+                val |= 0x1 << BP_CLPCR_LPM;
+                val &= ~BM_CLPCR_VSTBY;
+                val &= ~BM_CLPCR_SBYOS;
+                val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
+                break;
+        case STOP_POWER_OFF:
+                val |= 0x2 << BP_CLPCR_LPM;
+                val |= 0x3 << BP_CLPCR_STBY_COUNT;
+                val |= BM_CLPCR_VSTBY;
+                val |= BM_CLPCR_SBYOS;
+                val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
+                break;
+        default:
+                return -EINVAL;
+        }
+        writel_relaxed(val, CLPCR);
+        return 0;
+}
+static struct map_desc imx6q_clock_desc[] = {
+        imx_map_entry(MX6Q, CCM, MT_DEVICE),
+        imx_map_entry(MX6Q, ANATOP, MT_DEVICE),
+};
+int __init mx6q_clocks_init(void)
+{
+        struct device_node *np;
+        void __iomem *base;
+        int i, irq;
+        iotable_init(imx6q_clock_desc, ARRAY_SIZE(imx6q_clock_desc));
+        /* retrieve the freqency of fixed clocks from device tree */
+        for_each_compatible_node(np, NULL, "fixed-clock") {
+                u32 rate;
+                if (of_property_read_u32(np, "clock-frequency", &rate))
+                        continue;
+                if (of_device_is_compatible(np, "fsl,imx-ckil"))
+                        external_low_reference = rate;
+                else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
+                        external_high_reference = rate;
+                else if (of_device_is_compatible(np, "fsl,imx-osc"))
+                        oscillator_reference = rate;
+        }
+        for (i = 0; i < ARRAY_SIZE(lookups); i++)
+                clkdev_add(&lookups[i]);
+        /* only keep necessary clocks on */
+        writel_relaxed(0x3 << CG0  | 0x3 << CG1  | 0x3 << CG2,  CCGR0);
+        writel_relaxed(0x3 << CG8  | 0x3 << CG9  | 0x3 << CG10, CCGR2);
+        writel_relaxed(0x3 << CG10 | 0x3 << CG12,               CCGR3);
+        writel_relaxed(0x3 << CG4  | 0x3 << CG6  | 0x3 << CG7,  CCGR4);
+        writel_relaxed(0x3 << CG0,                              CCGR5);
+        writel_relaxed(0,                                       CCGR6);
+        writel_relaxed(0,                                       CCGR7);
+        clk_enable(&uart_clk);
+        clk_enable(&mmdc_ch0_axi_clk);
+        clk_set_rate(&pll4_audio, FREQ_650M);
+        clk_set_rate(&pll5_video, FREQ_650M);
+        clk_set_parent(&ipu1_di0_clk, &ipu1_di0_pre_clk);
+        clk_set_parent(&ipu1_di0_pre_clk, &pll5_video);
+        clk_set_parent(&gpu3d_shader_clk, &pll2_pfd_594m);
+        clk_set_rate(&gpu3d_shader_clk, FREQ_594M);
+        clk_set_parent(&gpu3d_core_clk, &mmdc_ch0_axi_clk);
+        clk_set_rate(&gpu3d_core_clk, FREQ_528M);
+        clk_set_parent(&asrc_serial_clk, &pll3_usb_otg);
+        clk_set_rate(&asrc_serial_clk, 1500000);
+        clk_set_rate(&enfc_clk, 11000000);
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
+        base = of_iomap(np, 0);
+        WARN_ON(!base);
+        irq = irq_of_parse_and_map(np, 0);
+        mxc_timer_init(&gpt_clk, base, irq);
+        return 0;
+}
diff --git a/arch/arm/mach-imx/cpu-imx25.c b/arch/arm/mach-imx/cpu-imx25.c
new file mode 100644
index 000000000000..6914bcbf84e4
--- /dev/null
+++ b/arch/arm/mach-imx/cpu-imx25.c
@@ -0,0 +1,41 @@
+/*
+ * MX25 CPU type detection
+ *
+ * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/iim.h>
+static int mx25_cpu_rev = -1;
+static int mx25_read_cpu_rev(void)
+{
+        u32 rev;
+        rev = __raw_readl(MX25_IO_ADDRESS(MX25_IIM_BASE_ADDR + MXC_IIMSREV));
+        switch (rev) {
+        case 0x00:
+                return IMX_CHIP_REVISION_1_0;
+        case 0x01:
+                return IMX_CHIP_REVISION_1_1;
+        default:
+                return IMX_CHIP_REVISION_UNKNOWN;
+        }
+}
+int mx25_revision(void)
+{
+        if (mx25_cpu_rev == -1)
+                mx25_cpu_rev = mx25_read_cpu_rev();
+        return mx25_cpu_rev;
+}
+EXPORT_SYMBOL(mx25_revision);
diff --git a/arch/arm/mach-imx/cpu-imx27.c b/arch/arm/mach-imx/cpu-imx27.c
index 3b117be37bd2..ff38e1505f67 100644
--- a/arch/arm/mach-imx/cpu-imx27.c
+++ b/arch/arm/mach-imx/cpu-imx27.c
@@ -26,12 +26,12 @@
 #include <mach/hardware.h>
-static int cpu_silicon_rev = -1;
+static int mx27_cpu_rev = -1;
-static int cpu_partnumber;
+static int mx27_cpu_partnumber;
 #define SYS_CHIP_ID             0x00    /* The offset of CHIP ID register */
-static void query_silicon_parameter(void)
+static int mx27_read_cpu_rev(void)
 {
        u32 val;
        /*
@@ -42,20 +42,18 @@ static void query_silicon_parameter(void)
        val = __raw_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR
                                + SYS_CHIP_ID));
+        mx27_cpu_partnumber = (int)((val >> 12) & 0xFFFF);
        switch (val >> 28) {
        case 0:
-                cpu_silicon_rev = IMX_CHIP_REVISION_1_0;
+                return IMX_CHIP_REVISION_1_0;
-                break;
        case 1:
-                cpu_silicon_rev = IMX_CHIP_REVISION_2_0;
+                return IMX_CHIP_REVISION_2_0;
-                break;
        case 2:
-                cpu_silicon_rev = IMX_CHIP_REVISION_2_1;
+                return IMX_CHIP_REVISION_2_1;
-                break;
        default:
-                cpu_silicon_rev = IMX_CHIP_REVISION_UNKNOWN;
+                return IMX_CHIP_REVISION_UNKNOWN;
        }
-        cpu_partnumber = (int)((val >> 12) & 0xFFFF);
 }
 /*
@@ -65,12 +63,12 @@ static void query_silicon_parameter(void)
 */
 int mx27_revision(void)
 {
-        if (cpu_silicon_rev == -1)
+        if (mx27_cpu_rev == -1)
-                query_silicon_parameter();
+                mx27_cpu_rev = mx27_read_cpu_rev();
-        if (cpu_partnumber != 0x8821)
+        if (mx27_cpu_partnumber != 0x8821)
                return -EINVAL;
-        return cpu_silicon_rev;
+        return mx27_cpu_rev;
 }
 EXPORT_SYMBOL(mx27_revision);
diff --git a/arch/arm/mach-imx/cpu-imx31.c b/arch/arm/mach-imx/cpu-imx31.c
index a3780700a882..3f2345f0cdaf 100644
--- a/arch/arm/mach-imx/cpu-imx31.c
+++ b/arch/arm/mach-imx/cpu-imx31.c
@@ -13,45 +13,50 @@
 #include <linux/io.h>
 #include <mach/hardware.h>
 #include <mach/iim.h>
+#include <mach/common.h>
-unsigned int mx31_cpu_rev;
+static int mx31_cpu_rev = -1;
-EXPORT_SYMBOL(mx31_cpu_rev);
 static struct {
        u8 srev;
        const char *name;
-        const char *v;
        unsigned int rev;
-} mx31_cpu_type[] __initdata = {
+} mx31_cpu_type[] = {
-        { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0",  .rev = IMX_CHIP_REVISION_1_0  },
+        { .srev = 0x00, .name = "i.MX31(L)", .rev = IMX_CHIP_REVISION_1_0 },
-        { .srev = 0x10, .name = "i.MX31",    .v = "1.1",  .rev = IMX_CHIP_REVISION_1_1  },
+        { .srev = 0x10, .name = "i.MX31",    .rev = IMX_CHIP_REVISION_1_1 },
-        { .srev = 0x11, .name = "i.MX31L",   .v = "1.1",  .rev = IMX_CHIP_REVISION_1_1  },
+        { .srev = 0x11, .name = "i.MX31L",   .rev = IMX_CHIP_REVISION_1_1 },
-        { .srev = 0x12, .name = "i.MX31",    .v = "1.15", .rev = IMX_CHIP_REVISION_1_1  },
+        { .srev = 0x12, .name = "i.MX31",    .rev = IMX_CHIP_REVISION_1_1 },
-        { .srev = 0x13, .name = "i.MX31L",   .v = "1.15", .rev = IMX_CHIP_REVISION_1_1  },
+        { .srev = 0x13, .name = "i.MX31L",   .rev = IMX_CHIP_REVISION_1_1 },
-        { .srev = 0x14, .name = "i.MX31",    .v = "1.2",  .rev = IMX_CHIP_REVISION_1_2  },
+        { .srev = 0x14, .name = "i.MX31",    .rev = IMX_CHIP_REVISION_1_2 },
-        { .srev = 0x15, .name = "i.MX31L",   .v = "1.2",  .rev = IMX_CHIP_REVISION_1_2  },
+        { .srev = 0x15, .name = "i.MX31L",   .rev = IMX_CHIP_REVISION_1_2 },
-        { .srev = 0x28, .name = "i.MX31",    .v = "2.0",  .rev = IMX_CHIP_REVISION_2_0  },
+        { .srev = 0x28, .name = "i.MX31",    .rev = IMX_CHIP_REVISION_2_0 },
-        { .srev = 0x29, .name = "i.MX31L",   .v = "2.0",  .rev = IMX_CHIP_REVISION_2_0  },
+        { .srev = 0x29, .name = "i.MX31L",   .rev = IMX_CHIP_REVISION_2_0 },
 };
-void __init mx31_read_cpu_rev(void)
+static int mx31_read_cpu_rev(void)
 {
        u32 i, srev;
        /* read SREV register from IIM module */
        srev = __raw_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV));
+        srev &= 0xff;
        for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
                if (srev == mx31_cpu_type[i].srev) {
-                        printk(KERN_INFO
+                        imx_print_silicon_rev(mx31_cpu_type[i].name,
-                                "CPU identified as %s, silicon rev %s\n",
+                                                mx31_cpu_type[i].rev);
-                                mx31_cpu_type[i].name, mx31_cpu_type[i].v);
+                        return mx31_cpu_type[i].rev;
-                        mx31_cpu_rev = mx31_cpu_type[i].rev;
-                        return;
                }
-        mx31_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
+        imx_print_silicon_rev("i.MX31", IMX_CHIP_REVISION_UNKNOWN);
+        return IMX_CHIP_REVISION_UNKNOWN;
+}
+int mx31_revision(void)
+{
+        if (mx31_cpu_rev == -1)
+                mx31_cpu_rev = mx31_read_cpu_rev();
-        printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev);
+        return mx31_cpu_rev;
 }
+EXPORT_SYMBOL(mx31_revision);
diff --git a/arch/arm/mach-imx/cpu-imx35.c b/arch/arm/mach-imx/cpu-imx35.c
index 6637cd819ecb..846e46eb8cbf 100644
--- a/arch/arm/mach-imx/cpu-imx35.c
+++ b/arch/arm/mach-imx/cpu-imx35.c
@@ -13,32 +13,30 @@
 #include <mach/hardware.h>
 #include <mach/iim.h>
-unsigned int mx35_cpu_rev;
+static int mx35_cpu_rev = -1;
-EXPORT_SYMBOL(mx35_cpu_rev);
-void __init mx35_read_cpu_rev(void)
+static int mx35_read_cpu_rev(void)
 {
        u32 rev;
-        char *srev;
        rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));
        switch (rev) {
        case 0x00:
-                mx35_cpu_rev = IMX_CHIP_REVISION_1_0;
+                return IMX_CHIP_REVISION_1_0;
-                srev = "1.0";
-                break;
        case 0x10:
-                mx35_cpu_rev = IMX_CHIP_REVISION_2_0;
+                return IMX_CHIP_REVISION_2_0;
-                srev = "2.0";
-                break;
        case 0x11:
-                mx35_cpu_rev = IMX_CHIP_REVISION_2_1;
+                return IMX_CHIP_REVISION_2_1;
-                srev = "2.1";
-                break;
        default:
-                mx35_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
+                return IMX_CHIP_REVISION_UNKNOWN;
-                srev = "unknown";
        }
+}
+int mx35_revision(void)
+{
+        if (mx35_cpu_rev == -1)
+                mx35_cpu_rev = mx35_read_cpu_rev();
-        printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev);
+        return mx35_cpu_rev;
 }
+EXPORT_SYMBOL(mx35_revision);
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h
index 7f97a3cdd41d..2f727d7c380c 100644
--- a/arch/arm/mach-imx/devices-imx27.h
+++ b/arch/arm/mach-imx/devices-imx27.h
@@ -76,3 +76,7 @@ extern const struct imx_spi_imx_data imx27_cspi_data[];
 #define imx27_add_spi_imx0(pdata)       imx27_add_cspi(0, pdata)
 #define imx27_add_spi_imx1(pdata)       imx27_add_cspi(1, pdata)
 #define imx27_add_spi_imx2(pdata)       imx27_add_cspi(2, pdata)
+extern const struct imx_pata_imx_data imx27_pata_imx_data;
+#define imx27_add_pata_imx() \
+        imx_add_pata_imx(&imx27_pata_imx_data)
diff --git a/arch/arm/mach-imx/devices-imx31.h b/arch/arm/mach-imx/devices-imx31.h
index dbe940d9c53a..488e241a6db6 100644
--- a/arch/arm/mach-imx/devices-imx31.h
+++ b/arch/arm/mach-imx/devices-imx31.h
@@ -78,3 +78,7 @@ extern const struct imx_spi_imx_data imx31_cspi_data[];
 #define imx31_add_spi_imx0(pdata)       imx31_add_cspi(0, pdata)
 #define imx31_add_spi_imx1(pdata)       imx31_add_cspi(1, pdata)
 #define imx31_add_spi_imx2(pdata)       imx31_add_cspi(2, pdata)
+extern const struct imx_pata_imx_data imx31_pata_imx_data;
+#define imx31_add_pata_imx() \
+        imx_add_pata_imx(&imx31_pata_imx_data)
diff --git a/arch/arm/mach-imx/devices-imx35.h b/arch/arm/mach-imx/devices-imx35.h
index 234cbd3c18af..7b99ef0bb501 100644
--- a/arch/arm/mach-imx/devices-imx35.h
+++ b/arch/arm/mach-imx/devices-imx35.h
@@ -81,3 +81,7 @@ extern const struct imx_spi_imx_data imx35_cspi_data[];
        imx_add_spi_imx(&imx35_cspi_data[id], pdata)
 #define imx35_add_spi_imx0(pdata)       imx35_add_cspi(0, pdata)
 #define imx35_add_spi_imx1(pdata)       imx35_add_cspi(1, pdata)
+extern const struct imx_pata_imx_data imx35_pata_imx_data;
+#define imx35_add_pata_imx() \
+        imx_add_pata_imx(&imx35_pata_imx_data)
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
new file mode 100644
index 000000000000..e1537f9e45b8
--- /dev/null
+++ b/arch/arm/mach-imx/gpc.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <asm/hardware/gic.h>
+#define GPC_IMR1                0x008
+#define GPC_PGC_CPU_PDN         0x2a0
+#define IMR_NUM                 4
+static void __iomem *gpc_base;
+static u32 gpc_wake_irqs[IMR_NUM];
+static u32 gpc_saved_imrs[IMR_NUM];
+void imx_gpc_pre_suspend(void)
+{
+        void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
+        int i;
+        /* Tell GPC to power off ARM core when suspend */
+        writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN);
+        for (i = 0; i < IMR_NUM; i++) {
+                gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
+                writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4);
+        }
+}
+void imx_gpc_post_resume(void)
+{
+        void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
+        int i;
+        /* Keep ARM core powered on for other low-power modes */
+        writel_relaxed(0x0, gpc_base + GPC_PGC_CPU_PDN);
+        for (i = 0; i < IMR_NUM; i++)
+                writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
+}
+static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
+{
+        unsigned int idx = d->irq / 32 - 1;
+        u32 mask;
+        /* Sanity check for SPI irq */
+        if (d->irq < 32)
+                return -EINVAL;
+        mask = 1 << d->irq % 32;
+        gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
+                                  gpc_wake_irqs[idx] & ~mask;
+        return 0;
+}
+static void imx_gpc_irq_unmask(struct irq_data *d)
+{
+        void __iomem *reg;
+        u32 val;
+        /* Sanity check for SPI irq */
+        if (d->irq < 32)
+                return;
+        reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4;
+        val = readl_relaxed(reg);
+        val &= ~(1 << d->irq % 32);
+        writel_relaxed(val, reg);
+}
+static void imx_gpc_irq_mask(struct irq_data *d)
+{
+        void __iomem *reg;
+        u32 val;
+        /* Sanity check for SPI irq */
+        if (d->irq < 32)
+                return;
+        reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4;
+        val = readl_relaxed(reg);
+        val |= 1 << (d->irq % 32);
+        writel_relaxed(val, reg);
+}
+void __init imx_gpc_init(void)
+{
+        struct device_node *np;
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
+        gpc_base = of_iomap(np, 0);
+        WARN_ON(!gpc_base);
+        /* Register GPC as the secondary interrupt controller behind GIC */
+        gic_arch_extn.irq_mask = imx_gpc_irq_mask;
+        gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;
+        gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake;
+}
diff --git a/arch/arm/mach-imx/head-v7.S b/arch/arm/mach-imx/head-v7.S
new file mode 100644
index 000000000000..6229efbc70cb
--- /dev/null
+++ b/arch/arm/mach-imx/head-v7.S
@@ -0,0 +1,99 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/asm-offsets.h>
+#include <asm/hardware/cache-l2x0.h>
+        .section ".text.head", "ax"
+        __CPUINIT
+/*
+ * The secondary kernel init calls v7_flush_dcache_all before it enables
+ * the L1; however, the L1 comes out of reset in an undefined state, so
+ * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
+ * of cache lines with uninitialized data and uninitialized tags to get
+ * written out to memory, which does really unpleasant things to the main
+ * processor.  We fix this by performing an invalidate, rather than a
+ * clean + invalidate, before jumping into the kernel.
+ *
+ * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs
+ * to be called for both secondary cores startup and primary core resume
+ * procedures.  Ideally, it should be moved into arch/arm/mm/cache-v7.S.
+ */
+ENTRY(v7_invalidate_l1)
+        mov     r0, #0
+        mcr     p15, 2, r0, c0, c0, 0
+        mrc     p15, 1, r0, c0, c0, 0
+        ldr     r1, =0x7fff
+        and     r2, r1, r0, lsr #13
+        ldr     r1, =0x3ff
+        and     r3, r1, r0, lsr #3      @ NumWays - 1
+        add     r2, r2, #1              @ NumSets
+        and     r0, r0, #0x7
+        add     r0, r0, #4      @ SetShift
+        clz     r1, r3          @ WayShift
+        add     r4, r3, #1      @ NumWays
+1:      sub     r2, r2, #1      @ NumSets--
+        mov     r3, r4          @ Temp = NumWays
+2:      subs    r3, r3, #1      @ Temp--
+        mov     r5, r3, lsl r1
+        mov     r6, r2, lsl r0
+        orr     r5, r5, r6      @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
+        mcr     p15, 0, r5, c7, c6, 2
+        bgt     2b
+        cmp     r2, #0
+        bgt     1b
+        dsb
+        isb
+        mov     pc, lr
+ENDPROC(v7_invalidate_l1)
+#ifdef CONFIG_SMP
+ENTRY(v7_secondary_startup)
+        bl      v7_invalidate_l1
+        b       secondary_startup
+ENDPROC(v7_secondary_startup)
+#endif
+/*
+ * The following code is located into the .data section.  This is to
+ * allow phys_l2x0_saved_regs to be accessed with a relative load
+ * as we are running on physical address here.
+ */
+        .data
+        .align
+        .macro  pl310_resume
+        ldr     r2, phys_l2x0_saved_regs
+        ldr     r0, [r2, #L2X0_R_PHY_BASE]      @ get physical base of l2x0
+        ldr     r1, [r2, #L2X0_R_AUX_CTRL]      @ get aux_ctrl value
+        str     r1, [r0, #L2X0_AUX_CTRL]        @ restore aux_ctrl
+        mov     r1, #0x1
+        str     r1, [r0, #L2X0_CTRL]            @ re-enable L2
+        .endm
+ENTRY(v7_cpu_resume)
+        bl      v7_invalidate_l1
+        pl310_resume
+        b       cpu_resume
+ENDPROC(v7_cpu_resume)
+        .globl  phys_l2x0_saved_regs
+phys_l2x0_saved_regs:
+        .long   0
diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c
new file mode 100644
index 000000000000..89493abd497c
--- /dev/null
+++ b/arch/arm/mach-imx/hotplug.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/errno.h>
+#include <asm/cacheflush.h>
+#include <mach/common.h>
+int platform_cpu_kill(unsigned int cpu)
+{
+        return 1;
+}
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void platform_cpu_die(unsigned int cpu)
+{
+        flush_cache_all();
+        imx_enable_cpu(cpu, false);
+        cpu_do_idle();
+        /* We should never return from idle */
+        panic("cpu %d unexpectedly exit from shutdown\n", cpu);
+}
+int platform_cpu_disable(unsigned int cpu)
+{
+        /*
+         * we don't allow CPU 0 to be shutdown (it is still too special
+         * e.g. clock tick interrupts)
+         */
+        return cpu == 0 ? -EPERM : 0;
+}
diff --git a/arch/arm/mach-imx/lluart.c b/arch/arm/mach-imx/lluart.c
new file mode 100644
index 000000000000..d4ab6f29a766
--- /dev/null
+++ b/arch/arm/mach-imx/lluart.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/init.h>
+#include <asm/page.h>
+#include <asm/sizes.h>
+#include <asm/mach/map.h>
+#include <mach/hardware.h>
+static struct map_desc imx_lluart_desc = {
+#ifdef CONFIG_DEBUG_IMX6Q_UART
+        .virtual        = MX6Q_IO_P2V(MX6Q_UART4_BASE_ADDR),
+        .pfn            = __phys_to_pfn(MX6Q_UART4_BASE_ADDR),
+        .length         = MX6Q_UART4_SIZE,
+        .type           = MT_DEVICE,
+#endif
+};
+void __init imx_lluart_map_io(void)
+{
+        if (imx_lluart_desc.virtual)
+                iotable_init(&imx_lluart_desc, 1);
+}
diff --git a/arch/arm/mach-imx/localtimer.c b/arch/arm/mach-imx/localtimer.c
new file mode 100644
index 000000000000..3a163515d41f
--- /dev/null
+++ b/arch/arm/mach-imx/localtimer.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/init.h>
+#include <linux/clockchips.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <asm/smp_twd.h>
+/*
+ * Setup the local clock events for a CPU.
+ */
+int __cpuinit local_timer_setup(struct clock_event_device *evt)
+{
+        struct device_node *np;
+        np = of_find_compatible_node(NULL, NULL, "arm,smp-twd");
+        if (!twd_base) {
+                twd_base = of_iomap(np, 0);
+                WARN_ON(!twd_base);
+        }
+        evt->irq = irq_of_parse_and_map(np, 0);
+        twd_timer_setup(evt);
+        return 0;
+}
diff --git a/arch/arm/mach-imx/mach-apf9328.c b/arch/arm/mach-imx/mach-apf9328.c
index a404c89485ca..1e486e67dabb 100644
--- a/arch/arm/mach-imx/mach-apf9328.c
+++ b/arch/arm/mach-imx/mach-apf9328.c
@@ -136,6 +136,7 @@ MACHINE_START(APF9328, "Armadeus APF9328")
        .map_io       = mx1_map_io,
        .init_early   = imx1_init_early,
        .init_irq     = mx1_init_irq,
+        .handle_irq   = imx1_handle_irq,
        .timer        = &apf9328_timer,
        .init_machine = apf9328_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c
index 215259083945..c9a9cf67755e 100644
--- a/arch/arm/mach-imx/mach-armadillo5x0.c
+++ b/arch/arm/mach-imx/mach-armadillo5x0.c
@@ -314,25 +314,19 @@ static struct mtd_partition armadillo5x0_nor_flash_partitions[] = {
        },
 };
-static struct physmap_flash_data armadillo5x0_nor_flash_pdata = {
+static const struct physmap_flash_data
+                armadillo5x0_nor_flash_pdata __initconst = {
        .width          = 2,
        .parts          = armadillo5x0_nor_flash_partitions,
        .nr_parts       = ARRAY_SIZE(armadillo5x0_nor_flash_partitions),
 };
-static struct resource armadillo5x0_nor_flash_resource = {
+static const struct resource armadillo5x0_nor_flash_resource __initconst = {
        .flags          = IORESOURCE_MEM,
        .start          = MX31_CS0_BASE_ADDR,
        .end            = MX31_CS0_BASE_ADDR + SZ_64M - 1,
 };
-static struct platform_device armadillo5x0_nor_flash = {
-        .name                   = "physmap-flash",
-        .id                     = -1,
-        .num_resources          = 1,
-        .resource               = &armadillo5x0_nor_flash_resource,
-};
 /*
 * FB support
 */
@@ -514,8 +508,10 @@ static void __init armadillo5x0_init(void)
        imx31_add_mx3_sdc_fb(&mx3fb_pdata);
        /* Register NOR Flash */
-        mxc_register_device(&armadillo5x0_nor_flash,
+        platform_device_register_resndata(NULL, "physmap-flash", -1,
-                            &armadillo5x0_nor_flash_pdata);
+                        &armadillo5x0_nor_flash_resource, 1,
+                        &armadillo5x0_nor_flash_pdata,
+                        sizeof(armadillo5x0_nor_flash_pdata));
        /* Register NAND Flash */
        imx31_add_mxc_nand(&armadillo5x0_nand_board_info);
@@ -562,6 +558,7 @@ MACHINE_START(ARMADILLO5X0, "Armadillo-500")
        .map_io = mx31_map_io,
        .init_early = imx31_init_early,
        .init_irq = mx31_init_irq,
+        .handle_irq = imx31_handle_irq,
        .timer = &armadillo5x0_timer,
        .init_machine = armadillo5x0_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-bug.c b/arch/arm/mach-imx/mach-bug.c
index f49470553bdf..313f62ddc1ef 100644
--- a/arch/arm/mach-imx/mach-bug.c
+++ b/arch/arm/mach-imx/mach-bug.c
@@ -62,6 +62,7 @@ MACHINE_START(BUG, "BugLabs BUGBase")
        .map_io = mx31_map_io,
        .init_early = imx31_init_early,
        .init_irq = mx31_init_irq,
+        .handle_irq = imx31_handle_irq,
        .timer = &bug_timer,
        .init_machine = bug_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index b1ec2cf53bb0..edb373052576 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -315,6 +315,7 @@ MACHINE_START(EUKREA_CPUIMX27, "EUKREA CPUIMX27")
        .map_io = mx27_map_io,
        .init_early = imx27_init_early,
        .init_irq = mx27_init_irq,
+        .handle_irq = imx27_handle_irq,
        .timer = &eukrea_cpuimx27_timer,
        .init_machine = eukrea_cpuimx27_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c
index 470b654b0e6e..66af2e8f7e57 100644
--- a/arch/arm/mach-imx/mach-cpuimx35.c
+++ b/arch/arm/mach-imx/mach-cpuimx35.c
@@ -66,7 +66,7 @@ static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
                I2C_BOARD_INFO("tsc2007", 0x48),
                .type           = "tsc2007",
                .platform_data  = &tsc2007_info,
-                .irq            = gpio_to_irq(TSC2007_IRQGPIO),
+                .irq            = IMX_GPIO_TO_IRQ(TSC2007_IRQGPIO),
        },
 };
@@ -198,6 +198,7 @@ MACHINE_START(EUKREA_CPUIMX35SD, "Eukrea CPUIMX35")
        .map_io = mx35_map_io,
        .init_early = imx35_init_early,
        .init_irq = mx35_init_irq,
+        .handle_irq = imx35_handle_irq,
        .timer = &eukrea_cpuimx35_timer,
        .init_machine = eukrea_cpuimx35_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
index 9163318e95a2..ab8fbcc472b5 100644
--- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
@@ -167,6 +167,7 @@ MACHINE_START(EUKREA_CPUIMX25SD, "Eukrea CPUIMX25")
        .map_io = mx25_map_io,
        .init_early = imx25_init_early,
        .init_irq = mx25_init_irq,
+        .handle_irq = imx25_handle_irq,
        .timer = &eukrea_cpuimx25_timer,
        .init_machine = eukrea_cpuimx25_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index 22306ce28658..38eb9e45110b 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -279,6 +279,7 @@ MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10")
        .map_io = mx27_map_io,
        .init_early = imx27_init_early,
        .init_irq = mx27_init_irq,
+        .handle_irq = imx27_handle_irq,
        .timer = &visstrim_m10_timer,
        .init_machine = visstrim_m10_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27ipcam.c b/arch/arm/mach-imx/mach-imx27ipcam.c
index 8da48b33fc53..7052155d0557 100644
--- a/arch/arm/mach-imx/mach-imx27ipcam.c
+++ b/arch/arm/mach-imx/mach-imx27ipcam.c
@@ -75,6 +75,7 @@ MACHINE_START(IMX27IPCAM, "Freescale IMX27IPCAM")
        .map_io = mx27_map_io,
        .init_early = imx27_init_early,
        .init_irq = mx27_init_irq,
+        .handle_irq = imx27_handle_irq,
        .timer = &mx27ipcam_timer,
        .init_machine = mx27ipcam_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c
index 21a14a20e2c3..8d6a63521f17 100644
--- a/arch/arm/mach-imx/mach-imx27lite.c
+++ b/arch/arm/mach-imx/mach-imx27lite.c
@@ -81,6 +81,7 @@ MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
        .map_io = mx27_map_io,
        .init_early = imx27_init_early,
        .init_irq = mx27_init_irq,
+        .handle_irq = imx27_handle_irq,
        .timer = &mx27lite_timer,
        .init_machine = mx27lite_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
new file mode 100644
index 000000000000..8bf5fa349484
--- /dev/null
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+static void __init imx6q_init_machine(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+        imx6q_pm_init();
+}
+static void __init imx6q_map_io(void)
+{
+        imx_lluart_map_io();
+        imx_scu_map_io();
+}
+static void __init imx6q_gpio_add_irq_domain(struct device_node *np,
+                                struct device_node *interrupt_parent)
+{
+        static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS -
+                                   32 * 7; /* imx6q gets 7 gpio ports */
+        irq_domain_add_simple(np, gpio_irq_base);
+        gpio_irq_base += 32;
+}
+static const struct of_device_id imx6q_irq_match[] __initconst = {
+        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+        { .compatible = "fsl,imx6q-gpio", .data = imx6q_gpio_add_irq_domain, },
+        { /* sentinel */ }
+};
+static void __init imx6q_init_irq(void)
+{
+        l2x0_of_init(0, ~0UL);
+        imx_src_init();
+        imx_gpc_init();
+        of_irq_init(imx6q_irq_match);
+}
+static void __init imx6q_timer_init(void)
+{
+        mx6q_clocks_init();
+}
+static struct sys_timer imx6q_timer = {
+        .init = imx6q_timer_init,
+};
+static const char *imx6q_dt_compat[] __initdata = {
+        "fsl,imx6q-sabreauto",
+        NULL,
+};
+DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad (Device Tree)")
+        .map_io         = imx6q_map_io,
+        .init_irq       = imx6q_init_irq,
+        .handle_irq     = imx6q_handle_irq,
+        .timer          = &imx6q_timer,
+        .init_machine   = imx6q_init_machine,
+        .dt_compat      = imx6q_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c
index 7c20e9e58006..5f37f89e40fa 100644
--- a/arch/arm/mach-imx/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-imx/mach-kzm_arm11_01.c
@@ -36,6 +36,7 @@
 #include <mach/clock.h>
 #include <mach/common.h>
+#include <mach/hardware.h>
 #include <mach/iomux-mx3.h>
 #include "devices-imx31.h"
@@ -275,6 +276,7 @@ MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
        .map_io = kzm_map_io,
        .init_early = imx31_init_early,
        .init_irq = mx31_init_irq,
+        .handle_irq = imx31_handle_irq,
        .timer = &kzm_timer,
        .init_machine = kzm_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index 530ea08dbafd..fc49785e7340 100644
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -68,23 +68,16 @@ static const struct imxuart_platform_data uart1_pdata __initconst = {
 * Physmap flash
 */
-static struct physmap_flash_data mx1ads_flash_data = {
+static const struct physmap_flash_data mx1ads_flash_data __initconst = {
        .width          = 4,            /* bankwidth in bytes */
 };
-static struct resource flash_resource = {
+static const struct resource flash_resource __initconst = {
        .start  = MX1_CS0_PHYS,
        .end    = MX1_CS0_PHYS + SZ_32M - 1,
        .flags  = IORESOURCE_MEM,
 };
-static struct platform_device flash_device = {
-        .name   = "physmap-flash",
-        .id     = 0,
-        .resource = &flash_resource,
-        .num_resources = 1,
-};
 /*
 * I2C
 */
@@ -125,7 +118,9 @@ static void __init mx1ads_init(void)
        imx1_add_imx_uart1(&uart1_pdata);
        /* Physmap flash */
-        mxc_register_device(&flash_device, &mx1ads_flash_data);
+        platform_device_register_resndata(NULL, "physmap-flash", 0,
+                        &flash_resource, 1,
+                        &mx1ads_flash_data, sizeof(mx1ads_flash_data));
        /* I2C */
        i2c_register_board_info(0, mx1ads_i2c_devices,
@@ -149,6 +144,7 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS")
        .map_io = mx1_map_io,
        .init_early = imx1_init_early,
        .init_irq = mx1_init_irq,
+        .handle_irq = imx1_handle_irq,
        .timer = &mx1ads_timer,
        .init_machine = mx1ads_init,
 MACHINE_END
@@ -158,6 +154,7 @@ MACHINE_START(MXLADS, "Freescale MXLADS")
        .map_io = mx1_map_io,
        .init_early = imx1_init_early,
        .init_irq = mx1_init_irq,
+        .handle_irq = imx1_handle_irq,
        .timer = &mx1ads_timer,
        .init_machine = mx1ads_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index e56828da26b2..25f84028d055 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -309,6 +309,7 @@ MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
        .map_io = mx21ads_map_io,
        .init_early = imx21_init_early,
        .init_irq = mx21_init_irq,
+        .handle_irq = imx21_handle_irq,
        .timer = &mx21ads_timer,
        .init_machine = mx21ads_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
index dd25ee82e70a..88dccf122243 100644
--- a/arch/arm/mach-imx/mach-mx25_3ds.c
+++ b/arch/arm/mach-imx/mach-mx25_3ds.c
@@ -43,6 +43,8 @@
 #include "devices-imx25.h"
+#define MX25PDK_CAN_PWDN        IMX_GPIO_NR(4, 6)
 static const struct imxuart_platform_data uart_pdata __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
@@ -108,6 +110,11 @@ static iomux_v3_cfg_t mx25pdk_pads[] = {
        /* I2C1 */
        MX25_PAD_I2C1_CLK__I2C1_CLK,
        MX25_PAD_I2C1_DAT__I2C1_DAT,
+        /* CAN1 */
+        MX25_PAD_GPIO_A__CAN1_TX,
+        MX25_PAD_GPIO_B__CAN1_RX,
+        MX25_PAD_D14__GPIO_4_6, /* CAN_PWDN */
 };
 static const struct fec_platform_data mx25_fec_pdata __initconst = {
@@ -240,6 +247,9 @@ static void __init mx25pdk_init(void)
        imx25_add_sdhci_esdhc_imx(0, &mx25pdk_esdhc_pdata);
        imx25_add_imx_i2c0(&mx25_3ds_i2c0_data);
+        gpio_request_one(MX25PDK_CAN_PWDN, GPIOF_OUT_INIT_LOW, "can-pwdn");
+        imx25_add_flexcan0(NULL);
 }
 static void __init mx25pdk_timer_init(void)
@@ -257,6 +267,7 @@ MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
        .map_io = mx25_map_io,
        .init_early = imx25_init_early,
        .init_irq = mx25_init_irq,
+        .handle_irq = imx25_handle_irq,
        .timer = &mx25pdk_timer,
        .init_machine = mx25pdk_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index 377230497dcc..cfa84178eb26 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -357,7 +357,7 @@ static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
                .bus_num        = 1,
                .chip_select    = 0, /* SS0 */
                .platform_data  = &mc13783_pdata,
-                .irq = gpio_to_irq(PMIC_INT),
+                .irq = IMX_GPIO_TO_IRQ(PMIC_INT),
                .mode = SPI_CS_HIGH,
        }, {
                .modalias       = "l4f00242t03",
@@ -423,6 +423,7 @@ MACHINE_START(MX27_3DS, "Freescale MX27PDK")
        .map_io = mx27_map_io,
        .init_early = imx27_init_early,
        .init_irq = mx27_init_irq,
+        .handle_irq = imx27_handle_irq,
        .timer = &mx27pdk_timer,
        .init_machine = mx27pdk_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index 635b0509068b..74dd5731eb61 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -348,6 +348,7 @@ MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
        .map_io = mx27ads_map_io,
        .init_early = imx27_init_early,
        .init_irq = mx27_init_irq,
+        .handle_irq = imx27_handle_irq,
        .timer = &mx27ads_timer,
        .init_machine = mx27ads_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index 6484db525bd7..60f1fda6ce97 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -540,7 +540,7 @@ static const struct mxc_nand_platform_data
 mx31_3ds_nand_board_info __initconst = {
        .width          = 1,
        .hw_ecc         = 1,
-#ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
+#ifdef CONFIG_MACH_MX31_3DS_MXC_NAND_USE_BBT
        .flash_bbt      = 1,
 #endif
 };
@@ -766,6 +766,7 @@ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
        .map_io = mx31_map_io,
        .init_early = imx31_init_early,
        .init_irq = mx31_init_irq,
+        .handle_irq = imx31_handle_irq,
        .timer = &mx31_3ds_timer,
        .init_machine = mx31_3ds_init,
        .reserve = mx31_3ds_reserve,
diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c
index 910c4561d35f..9cc1a49053bb 100644
--- a/arch/arm/mach-imx/mach-mx31ads.c
+++ b/arch/arm/mach-imx/mach-mx31ads.c
@@ -539,6 +539,7 @@ MACHINE_START(MX31ADS, "Freescale MX31ADS")
        .map_io = mx31ads_map_io,
        .init_early = imx31_init_early,
        .init_irq = mx31ads_init_irq,
+        .handle_irq = imx31_handle_irq,
        .timer = &mx31ads_timer,
        .init_machine = mx31ads_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31lilly.c b/arch/arm/mach-imx/mach-mx31lilly.c
index e92eaf91a7be..5defd8e70fc4 100644
--- a/arch/arm/mach-imx/mach-mx31lilly.c
+++ b/arch/arm/mach-imx/mach-mx31lilly.c
@@ -299,6 +299,7 @@ MACHINE_START(LILLY1131, "INCO startec LILLY-1131")
        .map_io = mx31_map_io,
        .init_early = imx31_init_early,
        .init_irq = mx31_init_irq,
+        .handle_irq = imx31_handle_irq,
        .timer = &mx31lilly_timer,
        .init_machine = mx31lilly_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c
index 5242cb78b563..c97c26d814ed 100644
--- a/arch/arm/mach-imx/mach-mx31lite.c
+++ b/arch/arm/mach-imx/mach-mx31lite.c
@@ -284,6 +284,7 @@ MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
        .map_io = mx31lite_map_io,
        .init_early = imx31_init_early,
        .init_irq = mx31_init_irq,
+        .handle_irq = imx31_handle_irq,
        .timer = &mx31lite_timer,
        .init_machine = mx31lite_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index 1d01ef28f25d..fff7791b7e7c 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -28,6 +28,9 @@
 #include <linux/spi/spi.h>
 #include <linux/types.h>
 #include <linux/memblock.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/err.h>
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
@@ -490,6 +493,18 @@ err:
 }
+static void mx31moboard_poweroff(void)
+{
+        struct clk *clk = clk_get_sys("imx2-wdt.0", NULL);
+        if (!IS_ERR(clk))
+                clk_enable(clk);
+        mxc_iomux_mode(MX31_PIN_WATCHDOG_RST__WATCHDOG_RST);
+        __raw_writew(1 << 6 | 1 << 2, MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
+}
 static int mx31moboard_baseboard;
 core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444);
@@ -528,6 +543,8 @@ static void __init mx31moboard_init(void)
        moboard_usbh2_init();
+        pm_power_off = mx31moboard_poweroff;
        switch (mx31moboard_baseboard) {
        case MX31NOBOARD:
                break;
@@ -572,6 +589,7 @@ MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
        .map_io = mx31_map_io,
        .init_early = imx31_init_early,
        .init_irq = mx31_init_irq,
+        .handle_irq = imx31_handle_irq,
        .timer = &mx31moboard_timer,
        .init_machine = mx31moboard_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index f2a873dc08ce..7a462025a0f7 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -221,6 +221,7 @@ MACHINE_START(MX35_3DS, "Freescale MX35PDK")
        .map_io = mx35_map_io,
        .init_early = imx35_init_early,
        .init_irq = mx35_init_irq,
+        .handle_irq = imx35_handle_irq,
        .timer = &mx35pdk_timer,
        .init_machine = mx35_3ds_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index 5ec3989704fd..125c19643b0f 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -271,6 +271,7 @@ MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60")
        .map_io = mx27_map_io,
        .init_early = imx27_init_early,
        .init_irq = mx27_init_irq,
+        .handle_irq = imx27_handle_irq,
        .timer = &mxt_td60_timer,
        .init_machine = mxt_td60_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index 0f6bd1199038..26072f4b02e3 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -439,6 +439,7 @@ MACHINE_START(PCA100, "phyCARD-i.MX27")
        .map_io = mx27_map_io,
        .init_early = imx27_init_early,
        .init_irq = mx27_init_irq,
+        .handle_irq = imx27_handle_irq,
        .init_machine = pca100_init,
        .timer = &pca100_timer,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
index 186d4eb90796..efd6b536ef6a 100644
--- a/arch/arm/mach-imx/mach-pcm037.c
+++ b/arch/arm/mach-imx/mach-pcm037.c
@@ -693,6 +693,7 @@ MACHINE_START(PCM037, "Phytec Phycore pcm037")
        .map_io = mx31_map_io,
        .init_early = imx31_init_early,
        .init_irq = mx31_init_irq,
+        .handle_irq = imx31_handle_irq,
        .timer = &pcm037_timer,
        .init_machine = pcm037_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 091bcf87e1a0..100bc733ce93 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -176,7 +176,9 @@ static struct platform_device *platform_devices[] __initdata = {
 * setup other stuffs to access the sram. */
 static void __init pcm038_init_sram(void)
 {
-        mx27_setup_weimcs(1, 0x0000d843, 0x22252521, 0x22220a00);
+        __raw_writel(0x0000d843, MX27_IO_ADDRESS(MX27_WEIM_CSCRxU(1)));
+        __raw_writel(0x22252521, MX27_IO_ADDRESS(MX27_WEIM_CSCRxL(1)));
+        __raw_writel(0x22220a00, MX27_IO_ADDRESS(MX27_WEIM_CSCRxA(1)));
 }
 static const struct imxi2c_platform_data pcm038_i2c1_data __initconst = {
@@ -353,6 +355,7 @@ MACHINE_START(PCM038, "phyCORE-i.MX27")
        .map_io = mx27_map_io,
        .init_early = imx27_init_early,
        .init_irq = mx27_init_irq,
+        .handle_irq = imx27_handle_irq,
        .timer = &pcm038_timer,
        .init_machine = pcm038_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index 0a4d31de7738..7366c2ae3ea5 100644
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -422,6 +422,7 @@ MACHINE_START(PCM043, "Phytec Phycore pcm043")
        .map_io = mx35_map_io,
        .init_early = imx35_init_early,
        .init_irq = mx35_init_irq,
+        .handle_irq = imx35_handle_irq,
        .timer = &pcm043_timer,
        .init_machine = pcm043_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-qong.c b/arch/arm/mach-imx/mach-qong.c
index 9e11359c324c..4ff5faf102a8 100644
--- a/arch/arm/mach-imx/mach-qong.c
+++ b/arch/arm/mach-imx/mach-qong.c
@@ -190,7 +190,10 @@ static struct platform_device qong_nand_device = {
 static void __init qong_init_nand_mtd(void)
 {
        /* init CS */
-        mx31_setup_weimcs(3, 0x00004f00, 0x20013b31, 0x00020800);
+        __raw_writel(0x00004f00, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(3)));
+        __raw_writel(0x20013b31, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(3)));
+        __raw_writel(0x00020800, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(3)));
        mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true);
        /* enable pin */
@@ -249,6 +252,7 @@ static void __init qong_init(void)
        mxc_init_imx_uart();
        qong_init_nor_mtd();
        qong_init_fpga();
+        imx31_add_imx2_wdt(NULL);
 }
 static void __init qong_timer_init(void)
@@ -266,6 +270,7 @@ MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
        .map_io = mx31_map_io,
        .init_early = imx31_init_early,
        .init_irq = mx31_init_irq,
+        .handle_irq = imx31_handle_irq,
        .timer = &qong_timer,
        .init_machine = qong_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
index 85d32845ee1e..bb6e5b25d8d0 100644
--- a/arch/arm/mach-imx/mach-scb9328.c
+++ b/arch/arm/mach-imx/mach-scb9328.c
@@ -141,6 +141,7 @@ MACHINE_START(SCB9328, "Synertronixx scb9328")
        .map_io = mx1_map_io,
        .init_early = imx1_init_early,
        .init_irq = mx1_init_irq,
+        .handle_irq = imx1_handle_irq,
        .timer = &scb9328_timer,
        .init_machine = scb9328_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c
index 7d8e012a6335..69092458f2d9 100644
--- a/arch/arm/mach-imx/mach-vpr200.c
+++ b/arch/arm/mach-imx/mach-vpr200.c
@@ -162,7 +162,7 @@ static struct i2c_board_info vpr200_i2c_devices[] = {
        }, {
                I2C_BOARD_INFO("mc13892", 0x08),
                .platform_data = &vpr200_pmic,
-                .irq = gpio_to_irq(GPIO_PMIC_INT),
+                .irq = IMX_GPIO_TO_IRQ(GPIO_PMIC_INT),
        }
 };
@@ -319,6 +319,7 @@ MACHINE_START(VPR200, "VPR200")
        .map_io = mx35_map_io,
        .init_early = imx35_init_early,
        .init_irq = mx35_init_irq,
+        .handle_irq = imx35_handle_irq,
        .timer = &vpr200_timer,
        .init_machine = vpr200_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
new file mode 100644
index 000000000000..9f0e82ec3398
--- /dev/null
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -0,0 +1,256 @@
+/*
+ *  Copyright (C) 1999,2000 Arm Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *    - add MX31 specific definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <asm/pgtable.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/mach/map.h>
+#include <mach/common.h>
+#include <mach/devices-common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-v3.h>
+#include <mach/irqs.h>
+static void imx3_idle(void)
+{
+        unsigned long reg = 0;
+        __asm__ __volatile__(
+                /* disable I and D cache */
+                "mrc p15, 0, %0, c1, c0, 0\n"
+                "bic %0, %0, #0x00001000\n"
+                "bic %0, %0, #0x00000004\n"
+                "mcr p15, 0, %0, c1, c0, 0\n"
+                /* invalidate I cache */
+                "mov %0, #0\n"
+                "mcr p15, 0, %0, c7, c5, 0\n"
+                /* clear and invalidate D cache */
+                "mov %0, #0\n"
+                "mcr p15, 0, %0, c7, c14, 0\n"
+                /* WFI */
+                "mov %0, #0\n"
+                "mcr p15, 0, %0, c7, c0, 4\n"
+                "nop\n" "nop\n" "nop\n" "nop\n"
+                "nop\n" "nop\n" "nop\n"
+                /* enable I and D cache */
+                "mrc p15, 0, %0, c1, c0, 0\n"
+                "orr %0, %0, #0x00001000\n"
+                "orr %0, %0, #0x00000004\n"
+                "mcr p15, 0, %0, c1, c0, 0\n"
+                : "=r" (reg));
+}
+static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
+                                  unsigned int mtype)
+{
+        if (mtype == MT_DEVICE) {
+                /*
+                 * Access all peripherals below 0x80000000 as nonshared device
+                 * on mx3, but leave l2cc alone.  Otherwise cache corruptions
+                 * can occur.
+                 */
+                if (phys_addr < 0x80000000 &&
+                                !addr_in_module(phys_addr, MX3x_L2CC))
+                        mtype = MT_DEVICE_NONSHARED;
+        }
+        return __arm_ioremap(phys_addr, size, mtype);
+}
+void imx3_init_l2x0(void)
+{
+        void __iomem *l2x0_base;
+        void __iomem *clkctl_base;
+/*
+ * First of all, we must repair broken chip settings. There are some
+ * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
+ * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
+ * Workaraound is to setup the correct register setting prior enabling the
+ * L2 cache. This should not hurt already working CPUs, as they are using the
+ * same value.
+ */
+#define L2_MEM_VAL 0x10
+        clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
+        if (clkctl_base != NULL) {
+                writel(0x00000515, clkctl_base + L2_MEM_VAL);
+                iounmap(clkctl_base);
+        } else {
+                pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
+        }
+        l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
+        if (IS_ERR(l2x0_base)) {
+                printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
+                                PTR_ERR(l2x0_base));
+                return;
+        }
+        l2x0_init(l2x0_base, 0x00030024, 0x00000000);
+}
+static struct map_desc mx31_io_desc[] __initdata = {
+        imx_map_entry(MX31, X_MEMC, MT_DEVICE),
+        imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
+        imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
+        imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
+        imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
+};
+/*
+ * This function initializes the memory map. It is called during the
+ * system startup to create static physical to virtual memory mappings
+ * for the IO modules.
+ */
+void __init mx31_map_io(void)
+{
+        iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
+}
+static struct map_desc mx35_io_desc[] __initdata = {
+        imx_map_entry(MX35, X_MEMC, MT_DEVICE),
+        imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
+        imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
+        imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
+        imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
+};
+void __init mx35_map_io(void)
+{
+        iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
+}
+void __init imx31_init_early(void)
+{
+        mxc_set_cpu_type(MXC_CPU_MX31);
+        mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
+        imx_idle = imx3_idle;
+        imx_ioremap = imx3_ioremap;
+}
+void __init imx35_init_early(void)
+{
+        mxc_set_cpu_type(MXC_CPU_MX35);
+        mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
+        mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
+        imx_idle = imx3_idle;
+        imx_ioremap = imx3_ioremap;
+}
+void __init mx31_init_irq(void)
+{
+        mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
+}
+void __init mx35_init_irq(void)
+{
+        mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
+}
+static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
+        .per_2_per_addr = 1677,
+};
+static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
+        .ap_2_ap_addr = 423,
+        .ap_2_bp_addr = 829,
+        .bp_2_ap_addr = 1029,
+};
+static struct sdma_platform_data imx31_sdma_pdata __initdata = {
+        .fw_name = "sdma-imx31-to2.bin",
+        .script_addrs = &imx31_to2_sdma_script,
+};
+void __init imx31_soc_init(void)
+{
+        int to_version = mx31_revision() >> 4;
+        imx3_init_l2x0();
+        mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
+        mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
+        mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
+        if (to_version == 1) {
+                strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
+                        strlen(imx31_sdma_pdata.fw_name));
+                imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
+        }
+        imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
+}
+static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
+        .ap_2_ap_addr = 642,
+        .uart_2_mcu_addr = 817,
+        .mcu_2_app_addr = 747,
+        .uartsh_2_mcu_addr = 1183,
+        .per_2_shp_addr = 1033,
+        .mcu_2_shp_addr = 961,
+        .ata_2_mcu_addr = 1333,
+        .mcu_2_ata_addr = 1252,
+        .app_2_mcu_addr = 683,
+        .shp_2_per_addr = 1111,
+        .shp_2_mcu_addr = 892,
+};
+static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
+        .ap_2_ap_addr = 729,
+        .uart_2_mcu_addr = 904,
+        .per_2_app_addr = 1597,
+        .mcu_2_app_addr = 834,
+        .uartsh_2_mcu_addr = 1270,
+        .per_2_shp_addr = 1120,
+        .mcu_2_shp_addr = 1048,
+        .ata_2_mcu_addr = 1429,
+        .mcu_2_ata_addr = 1339,
+        .app_2_per_addr = 1531,
+        .app_2_mcu_addr = 770,
+        .shp_2_per_addr = 1198,
+        .shp_2_mcu_addr = 979,
+};
+static struct sdma_platform_data imx35_sdma_pdata __initdata = {
+        .fw_name = "sdma-imx35-to2.bin",
+        .script_addrs = &imx35_to2_sdma_script,
+};
+void __init imx35_soc_init(void)
+{
+        int to_version = mx35_revision() >> 4;
+        imx3_init_l2x0();
+        /* i.mx35 has the i.mx31 type gpio */
+        mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
+        mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
+        mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
+        if (to_version == 1) {
+                strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
+                        strlen(imx35_sdma_pdata.fw_name));
+                imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
+        }
+        imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
+}
diff --git a/arch/arm/mach-imx/mm-imx31.c b/arch/arm/mach-imx/mm-imx31.c
deleted file mode 100644
index b7c55e7db000..000000000000
--- a/arch/arm/mach-imx/mm-imx31.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- *  Copyright (C) 1999,2000 Arm Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
- *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- *    - add MX31 specific definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <linux/err.h>
-#include <asm/pgtable.h>
-#include <asm/mach/map.h>
-#include <mach/common.h>
-#include <mach/devices-common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-v3.h>
-#include <mach/irqs.h>
-static struct map_desc mx31_io_desc[] __initdata = {
-        imx_map_entry(MX31, X_MEMC, MT_DEVICE),
-        imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
-        imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
-        imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
-        imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
-};
-/*
- * This function initializes the memory map. It is called during the
- * system startup to create static physical to virtual memory mappings
- * for the IO modules.
- */
-void __init mx31_map_io(void)
-{
-        iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
-}
-void __init imx31_init_early(void)
-{
-        mxc_set_cpu_type(MXC_CPU_MX31);
-        mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
-}
-void __init mx31_init_irq(void)
-{
-        mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
-}
-static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
-        .per_2_per_addr = 1677,
-};
-static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
-        .ap_2_ap_addr = 423,
-        .ap_2_bp_addr = 829,
-        .bp_2_ap_addr = 1029,
-};
-static struct sdma_platform_data imx31_sdma_pdata __initdata = {
-        .fw_name = "sdma-imx31-to2.bin",
-        .script_addrs = &imx31_to2_sdma_script,
-};
-void __init imx31_soc_init(void)
-{
-        int to_version = mx31_revision() >> 4;
-        mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
-        mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
-        mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
-        if (to_version == 1) {
-                strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
-                        strlen(imx31_sdma_pdata.fw_name));
-                imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
-        }
-        imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
-}
diff --git a/arch/arm/mach-imx/mm-imx35.c b/arch/arm/mach-imx/mm-imx35.c
deleted file mode 100644
index f49bac7a1ede..000000000000
--- a/arch/arm/mach-imx/mm-imx35.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- *  Copyright (C) 1999,2000 Arm Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
- *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- *    - add MX31 specific definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <linux/err.h>
-#include <asm/pgtable.h>
-#include <asm/mach/map.h>
-#include <asm/hardware/cache-l2x0.h>
-#include <mach/common.h>
-#include <mach/devices-common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-v3.h>
-#include <mach/irqs.h>
-static struct map_desc mx35_io_desc[] __initdata = {
-        imx_map_entry(MX35, X_MEMC, MT_DEVICE),
-        imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
-        imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
-        imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
-        imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
-};
-void __init mx35_map_io(void)
-{
-        iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
-}
-void __init imx35_init_early(void)
-{
-        mxc_set_cpu_type(MXC_CPU_MX35);
-        mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
-        mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
-}
-void __init mx35_init_irq(void)
-{
-        mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
-}
-static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
-        .ap_2_ap_addr = 642,
-        .uart_2_mcu_addr = 817,
-        .mcu_2_app_addr = 747,
-        .uartsh_2_mcu_addr = 1183,
-        .per_2_shp_addr = 1033,
-        .mcu_2_shp_addr = 961,
-        .ata_2_mcu_addr = 1333,
-        .mcu_2_ata_addr = 1252,
-        .app_2_mcu_addr = 683,
-        .shp_2_per_addr = 1111,
-        .shp_2_mcu_addr = 892,
-};
-static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
-        .ap_2_ap_addr = 729,
-        .uart_2_mcu_addr = 904,
-        .per_2_app_addr = 1597,
-        .mcu_2_app_addr = 834,
-        .uartsh_2_mcu_addr = 1270,
-        .per_2_shp_addr = 1120,
-        .mcu_2_shp_addr = 1048,
-        .ata_2_mcu_addr = 1429,
-        .mcu_2_ata_addr = 1339,
-        .app_2_per_addr = 1531,
-        .app_2_mcu_addr = 770,
-        .shp_2_per_addr = 1198,
-        .shp_2_mcu_addr = 979,
-};
-static struct sdma_platform_data imx35_sdma_pdata __initdata = {
-        .fw_name = "sdma-imx35-to2.bin",
-        .script_addrs = &imx35_to2_sdma_script,
-};
-void __init imx35_soc_init(void)
-{
-        int to_version = mx35_revision() >> 4;
-        /* i.mx35 has the i.mx31 type gpio */
-        mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
-        mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
-        mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
-        if (to_version == 1) {
-                strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
-                        strlen(imx35_sdma_pdata.fw_name));
-                imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
-        }
-        imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
-}
diff --git a/arch/arm/mach-imx/mmdc.c b/arch/arm/mach-imx/mmdc.c
new file mode 100644
index 000000000000..c461e98496c3
--- /dev/null
+++ b/arch/arm/mach-imx/mmdc.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#define MMDC_MAPSR              0x404
+#define BP_MMDC_MAPSR_PSD       0
+#define BP_MMDC_MAPSR_PSS       4
+static int __devinit imx_mmdc_probe(struct platform_device *pdev)
+{
+        struct device_node *np = pdev->dev.of_node;
+        void __iomem *mmdc_base, *reg;
+        u32 val;
+        int timeout = 0x400;
+        mmdc_base = of_iomap(np, 0);
+        WARN_ON(!mmdc_base);
+        reg = mmdc_base + MMDC_MAPSR;
+        /* Enable automatic power saving */
+        val = readl_relaxed(reg);
+        val &= ~(1 << BP_MMDC_MAPSR_PSD);
+        writel_relaxed(val, reg);
+        /* Ensure it's successfully enabled */
+        while (!(readl_relaxed(reg) & 1 << BP_MMDC_MAPSR_PSS) && --timeout)
+                cpu_relax();
+        if (unlikely(!timeout)) {
+                pr_warn("%s: failed to enable automatic power saving\n",
+                        __func__);
+                return -EBUSY;
+        }
+        return 0;
+}
+static struct of_device_id imx_mmdc_dt_ids[] = {
+        { .compatible = "fsl,imx6q-mmdc", },
+        { /* sentinel */ }
+};
+static struct platform_driver imx_mmdc_driver = {
+        .driver         = {
+                .name   = "imx-mmdc",
+                .owner  = THIS_MODULE,
+                .of_match_table = imx_mmdc_dt_ids,
+        },
+        .probe          = imx_mmdc_probe,
+};
+static int __init imx_mmdc_init(void)
+{
+        return platform_driver_register(&imx_mmdc_driver);
+}
+postcore_initcall(imx_mmdc_init);
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
new file mode 100644
index 000000000000..ab98c6fec9eb
--- /dev/null
+++ b/arch/arm/mach-imx/platsmp.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <asm/page.h>
+#include <asm/smp_scu.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach/map.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+static void __iomem *scu_base;
+static struct map_desc scu_io_desc __initdata = {
+        /* .virtual and .pfn are run-time assigned */
+        .length         = SZ_4K,
+        .type           = MT_DEVICE,
+};
+void __init imx_scu_map_io(void)
+{
+        unsigned long base;
+        /* Get SCU base */
+        asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
+        scu_io_desc.virtual = IMX_IO_P2V(base);
+        scu_io_desc.pfn = __phys_to_pfn(base);
+        iotable_init(&scu_io_desc, 1);
+        scu_base = IMX_IO_ADDRESS(base);
+}
+void __cpuinit platform_secondary_init(unsigned int cpu)
+{
+        /*
+         * if any interrupts are already enabled for the primary
+         * core (e.g. timer irq), then they will not have been enabled
+         * for us: do so
+         */
+        gic_secondary_init(0);
+}
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        imx_set_cpu_jump(cpu, v7_secondary_startup);
+        imx_enable_cpu(cpu, true);
+        return 0;
+}
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system.
+ */
+void __init smp_init_cpus(void)
+{
+        int i, ncores;
+        ncores = scu_get_core_count(scu_base);
+        for (i = 0; i < ncores; i++)
+                set_cpu_possible(i, true);
+        set_smp_cross_call(gic_raise_softirq);
+}
+void imx_smp_prepare(void)
+{
+        scu_enable(scu_base);
+}
+void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+{
+        imx_smp_prepare();
+}
diff --git a/arch/arm/mach-imx/pm-imx27.c b/arch/arm/mach-imx/pm-imx27.c
index acf17691d2cc..e455d2f855bf 100644
--- a/arch/arm/mach-imx/pm-imx27.c
+++ b/arch/arm/mach-imx/pm-imx27.c
@@ -11,7 +11,7 @@
 #include <linux/suspend.h>
 #include <linux/io.h>
 #include <mach/system.h>
-#include <mach/mx27.h>
+#include <mach/hardware.h>
 static int mx27_suspend_enter(suspend_state_t state)
 {
diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c
new file mode 100644
index 000000000000..f20f191d7cca
--- /dev/null
+++ b/arch/arm/mach-imx/pm-imx6q.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/suspend.h>
+#include <asm/cacheflush.h>
+#include <asm/proc-fns.h>
+#include <asm/suspend.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+extern unsigned long phys_l2x0_saved_regs;
+static int imx6q_suspend_finish(unsigned long val)
+{
+        cpu_do_idle();
+        return 0;
+}
+static int imx6q_pm_enter(suspend_state_t state)
+{
+        switch (state) {
+        case PM_SUSPEND_MEM:
+                imx6q_set_lpm(STOP_POWER_OFF);
+                imx_gpc_pre_suspend();
+                imx_set_cpu_jump(0, v7_cpu_resume);
+                /* Zzz ... */
+                cpu_suspend(0, imx6q_suspend_finish);
+                imx_smp_prepare();
+                imx_gpc_post_resume();
+                break;
+        default:
+                return -EINVAL;
+        }
+        return 0;
+}
+static const struct platform_suspend_ops imx6q_pm_ops = {
+        .enter = imx6q_pm_enter,
+        .valid = suspend_valid_only_mem,
+};
+void __init imx6q_pm_init(void)
+{
+        /*
+         * The l2x0 core code provides an infrastucture to save and restore
+         * l2x0 registers across suspend/resume cycle.  But because imx6q
+         * retains L2 content during suspend and needs to resume L2 before
+         * MMU is enabled, it can only utilize register saving support and
+         * have to take care of restoring on its own.  So we save physical
+         * address of the data structure used by l2x0 core to save registers,
+         * and later restore the necessary ones in imx6q resume entry.
+         */
+        phys_l2x0_saved_regs = __pa(&l2x0_saved_regs);
+        suspend_set_ops(&imx6q_pm_ops);
+}
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
new file mode 100644
index 000000000000..36cacbd0dcc2
--- /dev/null
+++ b/arch/arm/mach-imx/src.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <asm/unified.h>
+#define SRC_SCR                         0x000
+#define SRC_GPR1                        0x020
+#define BP_SRC_SCR_CORE1_RST            14
+#define BP_SRC_SCR_CORE1_ENABLE         22
+static void __iomem *src_base;
+void imx_enable_cpu(int cpu, bool enable)
+{
+        u32 mask, val;
+        mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1);
+        val = readl_relaxed(src_base + SRC_SCR);
+        val = enable ? val | mask : val & ~mask;
+        writel_relaxed(val, src_base + SRC_SCR);
+}
+void imx_set_cpu_jump(int cpu, void *jump_addr)
+{
+        writel_relaxed(BSYM(virt_to_phys(jump_addr)),
+                       src_base + SRC_GPR1 + cpu * 8);
+}
+void __init imx_src_init(void)
+{
+        struct device_node *np;
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-src");
+        src_base = of_iomap(np, 0);
+        WARN_ON(!src_base);
+}
diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
index 6f991c5ae863..fd5e7b6881bf 100644
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -179,6 +179,25 @@ config MACH_GTWX5715
                "High Speed" UART is n/c (as far as I can tell)
                20 Pin ARM/Xscale JTAG interface on J2
+config MACH_DEVIXP
+        bool "Omicron DEVIXP"
+        help
+          Say 'Y' here if you want your kernel to support the DEVIXP
+          board from OMICRON electronics GmbH.
+config MACH_MICCPT
+        bool "Omicron MICCPT"
+        select PCI
+        help
+          Say 'Y' here if you want your kernel to support the MICCPT
+          board from OMICRON electronics GmbH.
+config MACH_MIC256
+        bool "Omicron MIC256"
+        help
+          Say 'Y' here if you want your kernel to support the MIC256
+          board from OMICRON electronics GmbH.
 comment "IXP4xx Options"
 config IXP4XX_INDIRECT_PCI
diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile
index d807fc367dd3..eded94c96dd4 100644
--- a/arch/arm/mach-ixp4xx/Makefile
+++ b/arch/arm/mach-ixp4xx/Makefile
@@ -10,6 +10,7 @@ obj-pci-$(CONFIG_MACH_AVILA)		+= avila-pci.o
 obj-pci-$(CONFIG_MACH_IXDPG425)         += ixdpg425-pci.o
 obj-pci-$(CONFIG_ARCH_ADI_COYOTE)       += coyote-pci.o
 obj-pci-$(CONFIG_MACH_GTWX5715)         += gtwx5715-pci.o
+obj-pci-$(CONFIG_MACH_MICCPT)           += miccpt-pci.o
 obj-pci-$(CONFIG_MACH_NSLU2)            += nslu2-pci.o
 obj-pci-$(CONFIG_MACH_NAS100D)          += nas100d-pci.o
 obj-pci-$(CONFIG_MACH_DSMG600)          += dsmg600-pci.o
@@ -25,6 +26,9 @@ obj-$(CONFIG_MACH_AVILA)	+= avila-setup.o
 obj-$(CONFIG_MACH_IXDPG425)     += coyote-setup.o
 obj-$(CONFIG_ARCH_ADI_COYOTE)   += coyote-setup.o
 obj-$(CONFIG_MACH_GTWX5715)     += gtwx5715-setup.o
+obj-$(CONFIG_MACH_DEVIXP)       += omixp-setup.o
+obj-$(CONFIG_MACH_MICCPT)       += omixp-setup.o
+obj-$(CONFIG_MACH_MIC256)       += omixp-setup.o
 obj-$(CONFIG_MACH_NSLU2)        += nslu2-setup.o
 obj-$(CONFIG_MACH_NAS100D)      += nas100d-setup.o
 obj-$(CONFIG_MACH_DSMG600)      += dsmg600-setup.o
diff --git a/arch/arm/mach-ixp4xx/include/mach/uncompress.h b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
index 219d7c1dcdba..eb945a926d07 100644
--- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h
+++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
@@ -41,7 +41,8 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
         * Some boards are using UART2 as console
         */
        if (machine_is_adi_coyote() || machine_is_gtwx5715() ||
-                         machine_is_gateway7001() || machine_is_wg302v2())
+            machine_is_gateway7001() || machine_is_wg302v2() ||
+            machine_is_devixp() || machine_is_miccpt() || machine_is_mic256())
                uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
        else
                uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;
diff --git a/arch/arm/mach-ixp4xx/miccpt-pci.c b/arch/arm/mach-ixp4xx/miccpt-pci.c
new file mode 100644
index 000000000000..ca0bae7fca90
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/miccpt-pci.c
@@ -0,0 +1,78 @@
+/*
+ * arch/arm/mach-ixp4xx/miccpt-pci.c
+ *
+ * MICCPT board-level PCI initialization
+ *
+ * Copyright (C) 2002 Intel Corporation.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ * Copyright (C) 2006 OMICRON electronics GmbH
+ *
+ * Author: Michael Jochum <michael.jochum@omicron.at>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <asm/mach/pci.h>
+#include <asm/irq.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#define MAX_DEV         4
+#define IRQ_LINES       4
+/* PCI controller GPIO to IRQ pin mappings */
+#define INTA            1
+#define INTB            2
+#define INTC            3
+#define INTD            4
+void __init miccpt_pci_preinit(void)
+{
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
+        ixp4xx_pci_preinit();
+}
+static int __init miccpt_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        static int pci_irq_table[IRQ_LINES] = {
+                IXP4XX_GPIO_IRQ(INTA),
+                IXP4XX_GPIO_IRQ(INTB),
+                IXP4XX_GPIO_IRQ(INTC),
+                IXP4XX_GPIO_IRQ(INTD)
+        };
+        if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
+                return pci_irq_table[(slot + pin - 2) % 4];
+        return -1;
+}
+struct hw_pci miccpt_pci __initdata = {
+        .nr_controllers = 1,
+        .preinit        = miccpt_pci_preinit,
+        .swizzle        = pci_std_swizzle,
+        .setup          = ixp4xx_setup,
+        .scan           = ixp4xx_scan_bus,
+        .map_irq        = miccpt_map_irq,
+};
+int __init miccpt_pci_init(void)
+{
+        if (machine_is_miccpt())
+                pci_common_init(&miccpt_pci);
+        return 0;
+}
+subsys_initcall(miccpt_pci_init);
diff --git a/arch/arm/mach-ixp4xx/omixp-setup.c b/arch/arm/mach-ixp4xx/omixp-setup.c
new file mode 100644
index 000000000000..3b6a81a696fc
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/omixp-setup.c
@@ -0,0 +1,273 @@
+/*
+ * arch/arm/mach-ixp4xx/omixp-setup.c
+ *
+ * omicron ixp4xx board setup
+ *      Copyright (C) 2009 OMICRON electronics GmbH
+ *
+ * based nslu2-setup.c, ixdp425-setup.c:
+ *      Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/serial.h>
+#include <linux/serial_8250.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#ifdef CONFIG_LEDS_CLASS
+#include <linux/leds.h>
+#endif
+#include <asm/setup.h>
+#include <asm/memory.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+static struct resource omixp_flash_resources[] = {
+        {
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .flags  = IORESOURCE_MEM,
+        },
+};
+static struct mtd_partition omixp_partitions[] = {
+        {
+                .name =         "Recovery Bootloader",
+                .size =         0x00020000,
+                .offset =       0,
+        }, {
+                .name =         "Calibration Data",
+                .size =         0x00020000,
+                .offset =       0x00020000,
+        }, {
+                .name =         "Recovery FPGA",
+                .size =         0x00020000,
+                .offset =       0x00040000,
+        }, {
+                .name =         "Release Bootloader",
+                .size =         0x00020000,
+                .offset =       0x00060000,
+        }, {
+                .name =         "Release FPGA",
+                .size =         0x00020000,
+                .offset =       0x00080000,
+        }, {
+                .name =         "Kernel",
+                .size =         0x00160000,
+                .offset =       0x000a0000,
+        }, {
+                .name =         "Filesystem",
+                .size =         0x00C00000,
+                .offset =       0x00200000,
+        }, {
+                .name =         "Persistent Storage",
+                .size =         0x00200000,
+                .offset =       0x00E00000,
+        },
+};
+static struct flash_platform_data omixp_flash_data[] = {
+        {
+                .map_name       = "cfi_probe",
+                .parts          = omixp_partitions,
+                .nr_parts       = ARRAY_SIZE(omixp_partitions),
+        }, {
+                .map_name       = "cfi_probe",
+                .parts          = NULL,
+                .nr_parts       = 0,
+        },
+};
+static struct platform_device omixp_flash_device[] = {
+        {
+                .name           = "IXP4XX-Flash",
+                .id             = 0,
+                .dev = {
+                        .platform_data = &omixp_flash_data[0],
+                },
+                .resource = &omixp_flash_resources[0],
+                .num_resources = 1,
+        }, {
+                .name           = "IXP4XX-Flash",
+                .id             = 1,
+                .dev = {
+                        .platform_data = &omixp_flash_data[1],
+                },
+                .resource = &omixp_flash_resources[1],
+                .num_resources = 1,
+        },
+};
+/* Swap UART's - These boards have the console on UART2. The following
+ * configuration is used:
+ *      ttyS0 .. UART2
+ *      ttyS1 .. UART1
+ * This way standard images can be used with the kernel that expect
+ * the console on ttyS0.
+ */
+static struct resource omixp_uart_resources[] = {
+        {
+                .start          = IXP4XX_UART2_BASE_PHYS,
+                .end            = IXP4XX_UART2_BASE_PHYS + 0x0fff,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = IXP4XX_UART1_BASE_PHYS,
+                .end            = IXP4XX_UART1_BASE_PHYS + 0x0fff,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+static struct plat_serial8250_port omixp_uart_data[] = {
+        {
+                .mapbase        = IXP4XX_UART2_BASE_PHYS,
+                .membase        = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
+                .irq            = IRQ_IXP4XX_UART2,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = IXP4XX_UART_XTAL,
+        }, {
+                .mapbase        = IXP4XX_UART1_BASE_PHYS,
+                .membase        = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
+                .irq            = IRQ_IXP4XX_UART1,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = IXP4XX_UART_XTAL,
+        }, {
+                /* list termination */
+        }
+};
+static struct platform_device omixp_uart = {
+        .name                   = "serial8250",
+        .id                     = PLAT8250_DEV_PLATFORM,
+        .dev.platform_data      = omixp_uart_data,
+        .num_resources          = 2,
+        .resource               = omixp_uart_resources,
+};
+static struct gpio_led mic256_led_pins[] = {
+        {
+                .name           = "LED-A",
+                .gpio           = 7,
+        },
+};
+static struct gpio_led_platform_data mic256_led_data = {
+        .num_leds               = ARRAY_SIZE(mic256_led_pins),
+        .leds                   = mic256_led_pins,
+};
+static struct platform_device mic256_leds = {
+        .name                   = "leds-gpio",
+        .id                     = -1,
+        .dev.platform_data      = &mic256_led_data,
+};
+/* Built-in 10/100 Ethernet MAC interfaces */
+static struct eth_plat_info ixdp425_plat_eth[] = {
+        {
+                .phy            = 0,
+                .rxq            = 3,
+                .txreadyq       = 20,
+        }, {
+                .phy            = 1,
+                .rxq            = 4,
+                .txreadyq       = 21,
+        },
+};
+static struct platform_device ixdp425_eth[] = {
+        {
+                .name                   = "ixp4xx_eth",
+                .id                     = IXP4XX_ETH_NPEB,
+                .dev.platform_data      = ixdp425_plat_eth,
+        }, {
+                .name                   = "ixp4xx_eth",
+                .id                     = IXP4XX_ETH_NPEC,
+                .dev.platform_data      = ixdp425_plat_eth + 1,
+        },
+};
+static struct platform_device *devixp_pldev[] __initdata = {
+        &omixp_uart,
+        &omixp_flash_device[0],
+        &ixdp425_eth[0],
+        &ixdp425_eth[1],
+};
+static struct platform_device *mic256_pldev[] __initdata = {
+        &omixp_uart,
+        &omixp_flash_device[0],
+        &mic256_leds,
+        &ixdp425_eth[0],
+        &ixdp425_eth[1],
+};
+static struct platform_device *miccpt_pldev[] __initdata = {
+        &omixp_uart,
+        &omixp_flash_device[0],
+        &omixp_flash_device[1],
+        &ixdp425_eth[0],
+        &ixdp425_eth[1],
+};
+static void __init omixp_init(void)
+{
+        ixp4xx_sys_init();
+        /* 16MiB Boot Flash */
+        omixp_flash_resources[0].start = IXP4XX_EXP_BUS_BASE(0);
+        omixp_flash_resources[0].end   = IXP4XX_EXP_BUS_END(0);
+        /* 32 MiB Data Flash */
+        omixp_flash_resources[1].start = IXP4XX_EXP_BUS_BASE(2);
+        omixp_flash_resources[1].end   = IXP4XX_EXP_BUS_END(2);
+        if (machine_is_devixp())
+                platform_add_devices(devixp_pldev, ARRAY_SIZE(devixp_pldev));
+        else if (machine_is_miccpt())
+                platform_add_devices(miccpt_pldev, ARRAY_SIZE(miccpt_pldev));
+        else if (machine_is_mic256())
+                platform_add_devices(mic256_pldev, ARRAY_SIZE(mic256_pldev));
+}
+#ifdef CONFIG_MACH_DEVIXP
+MACHINE_START(DEVIXP, "Omicron DEVIXP")
+        .atag_offset    = 0x100,
+        .map_io         = ixp4xx_map_io,
+        .init_irq       = ixp4xx_init_irq,
+        .timer          = &ixp4xx_timer,
+        .init_machine   = omixp_init,
+MACHINE_END
+#endif
+#ifdef CONFIG_MACH_MICCPT
+MACHINE_START(MICCPT, "Omicron MICCPT")
+        .atag_offset    = 0x100,
+        .map_io         = ixp4xx_map_io,
+        .init_irq       = ixp4xx_init_irq,
+        .timer          = &ixp4xx_timer,
+        .init_machine   = omixp_init,
+#if defined(CONFIG_PCI)
+        .dma_zone_size  = SZ_64M,
+#endif
+MACHINE_END
+#endif
+#ifdef CONFIG_MACH_MIC256
+MACHINE_START(MIC256, "Omicron MIC256")
+        .atag_offset    = 0x100,
+        .map_io         = ixp4xx_map_io,
+        .init_irq       = ixp4xx_init_irq,
+        .timer          = &ixp4xx_timer,
+        .init_machine   = omixp_init,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 56ef5f6c8116..323d4c9e9f44 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -77,7 +77,7 @@ config MACH_TETON_BGA
          Say 'Y' here if you want to support the Marvell PXA168-based
          Teton BGA Development Board.
-config MACH_SHEEVAD
+config MACH_GPLUGD
        bool "Marvell's PXA168 GuruPlug Display (gplugD) Board"
        select CPU_PXA168
        help
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index b0ac942327aa..8f948f981646 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -19,4 +19,4 @@ obj-$(CONFIG_MACH_BROWNSTONE)	+= brownstone.o
 obj-$(CONFIG_MACH_FLINT)        += flint.o
 obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
 obj-$(CONFIG_MACH_TETON_BGA)    += teton_bga.o
-obj-$(CONFIG_MACH_SHEEVAD)      += gplugd.o
+obj-$(CONFIG_MACH_GPLUGD)       += gplugd.o
diff --git a/arch/arm/mach-mmp/clock.h b/arch/arm/mach-mmp/clock.h
index 3143e994e672..149b30cd1469 100644
--- a/arch/arm/mach-mmp/clock.h
+++ b/arch/arm/mach-mmp/clock.h
@@ -30,7 +30,7 @@ extern struct clkops apmu_clk_ops;
 #define APBC_CLK(_name, _reg, _fnclksel, _rate)                 \
 struct clk clk_##_name = {                                      \
-                .clk_rst        = (void __iomem *)APBC_##_reg,  \
+                .clk_rst        = APBC_##_reg,                  \
                .fnclksel       = _fnclksel,                    \
                .rate           = _rate,                        \
                .ops            = &apbc_clk_ops,                \
@@ -38,7 +38,7 @@ struct clk clk_##_name = {					\
 #define APBC_CLK_OPS(_name, _reg, _fnclksel, _rate, _ops)       \
 struct clk clk_##_name = {                                      \
-                .clk_rst        = (void __iomem *)APBC_##_reg,  \
+                .clk_rst        = APBC_##_reg,                  \
                .fnclksel       = _fnclksel,                    \
                .rate           = _rate,                        \
                .ops            = _ops,                         \
@@ -46,7 +46,7 @@ struct clk clk_##_name = {					\
 #define APMU_CLK(_name, _reg, _eval, _rate)                     \
 struct clk clk_##_name = {                                      \
-                .clk_rst        = (void __iomem *)APMU_##_reg,  \
+                .clk_rst        = APMU_##_reg,                  \
                .enable_val     = _eval,                        \
                .rate           = _rate,                        \
                .ops            = &apmu_clk_ops,                \
@@ -54,7 +54,7 @@ struct clk clk_##_name = {					\
 #define APMU_CLK_OPS(_name, _reg, _eval, _rate, _ops)           \
 struct clk clk_##_name = {                                      \
-                .clk_rst        = (void __iomem *)APMU_##_reg,  \
+                .clk_rst        = APMU_##_reg,                  \
                .enable_val     = _eval,                        \
                .rate           = _rate,                        \
                .ops            = _ops,                         \
diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c
index 0ec0ca80bb3e..5720674739f0 100644
--- a/arch/arm/mach-mmp/common.c
+++ b/arch/arm/mach-mmp/common.c
@@ -27,12 +27,12 @@ EXPORT_SYMBOL(mmp_chip_id);
 static struct map_desc standard_io_desc[] __initdata = {
        {
                .pfn            = __phys_to_pfn(APB_PHYS_BASE),
-                .virtual        = APB_VIRT_BASE,
+                .virtual        = (unsigned long)APB_VIRT_BASE,
                .length         = APB_PHYS_SIZE,
                .type           = MT_DEVICE,
        }, {
                .pfn            = __phys_to_pfn(AXI_PHYS_BASE),
-                .virtual        = AXI_VIRT_BASE,
+                .virtual        = (unsigned long)AXI_VIRT_BASE,
                .length         = AXI_PHYS_SIZE,
                .type           = MT_DEVICE,
        },
diff --git a/arch/arm/mach-mmp/gplugd.c b/arch/arm/mach-mmp/gplugd.c
index 32776f3739f1..69156568bc41 100644
--- a/arch/arm/mach-mmp/gplugd.c
+++ b/arch/arm/mach-mmp/gplugd.c
@@ -188,7 +188,7 @@ static void __init gplugd_init(void)
        pxa168_add_eth(&gplugd_eth_platform_data);
 }
-MACHINE_START(SHEEVAD, "PXA168-based GuruPlug Display (gplugD) Platform")
+MACHINE_START(GPLUGD, "PXA168-based GuruPlug Display (gplugD) Platform")
        .map_io         = mmp_map_io,
        .nr_irqs        = IRQ_BOARD_START,
        .init_irq       = pxa168_init_irq,
diff --git a/arch/arm/mach-mmp/include/mach/addr-map.h b/arch/arm/mach-mmp/include/mach/addr-map.h
index 3254089a644d..3e404acd6ff4 100644
--- a/arch/arm/mach-mmp/include/mach/addr-map.h
+++ b/arch/arm/mach-mmp/include/mach/addr-map.h
@@ -11,6 +11,12 @@
 #ifndef __ASM_MACH_ADDR_MAP_H
 #define __ASM_MACH_ADDR_MAP_H
+#ifndef __ASSEMBLER__
+#define IOMEM(x)        ((void __iomem *)(x))
+#else
+#define IOMEM(x)        (x)
+#endif
 /* APB - Application Subsystem Peripheral Bus
 *
 * NOTE: the DMA controller registers are actually on the AXI fabric #1
@@ -18,11 +24,11 @@
 * peripherals on APB, let's count it into the ABP mapping area.
 */
 #define APB_PHYS_BASE           0xd4000000
-#define APB_VIRT_BASE           0xfe000000
+#define APB_VIRT_BASE           IOMEM(0xfe000000)
 #define APB_PHYS_SIZE           0x00200000
 #define AXI_PHYS_BASE           0xd4200000
-#define AXI_VIRT_BASE           0xfe200000
+#define AXI_VIRT_BASE           IOMEM(0xfe200000)
 #define AXI_PHYS_SIZE           0x00200000
 /* Static Memory Controller - Chip Select 0 and 1 */
diff --git a/arch/arm/mach-mmp/include/mach/gpio-pxa.h b/arch/arm/mach-mmp/include/mach/gpio-pxa.h
index c017a983eced..d14eeaf16322 100644
--- a/arch/arm/mach-mmp/include/mach/gpio-pxa.h
+++ b/arch/arm/mach-mmp/include/mach/gpio-pxa.h
@@ -7,7 +7,7 @@
 #define GPIO_REGS_VIRT  (APB_VIRT_BASE + 0x19000)
 #define BANK_OFF(n)     (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
-#define GPIO_REG(x)     (*((volatile u32 *)(GPIO_REGS_VIRT + (x))))
+#define GPIO_REG(x)     (GPIO_REGS_VIRT + (x))
 #define NR_BUILTIN_GPIO         IRQ_GPIO_NUM
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index 65d8689e40c9..7a7e8e4dde41 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -86,7 +86,8 @@ static struct mfp_addr_map mmp2_addr_map[] __initdata = {
 void mmp2_clear_pmic_int(void)
 {
-        unsigned long mfpr_pmic, data;
+        void __iomem *mfpr_pmic;
+        unsigned long data;
        mfpr_pmic = APB_VIRT_BASE + 0x1e000 + 0x2c4;
        data = __raw_readl(mfpr_pmic);
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 106170fb1844..cf38e2284fa9 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2010, 2011, Code Aurora Forum. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
@@ -8,18 +8,16 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- *
 */
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
 #include <linux/memblock.h>
 #include <asm/mach-types.h>
@@ -70,6 +68,41 @@ static void __init msm8x60_init(void)
 {
 }
+#ifdef CONFIG_OF
+static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = {
+        {}
+};
+static struct of_device_id msm_dt_gic_match[] __initdata = {
+        { .compatible = "qcom,msm-8660-qgic", },
+        {}
+};
+static void __init msm8x60_dt_init(void)
+{
+        struct device_node *node;
+        node = of_find_matching_node_by_address(NULL, msm_dt_gic_match,
+                        MSM8X60_QGIC_DIST_PHYS);
+        if (node)
+                irq_domain_add_simple(node, GIC_SPI_START);
+        if (of_machine_is_compatible("qcom,msm8660-surf")) {
+                printk(KERN_INFO "Init surf UART registers\n");
+                msm8x60_init_uart12dm();
+        }
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        msm_auxdata_lookup, NULL);
+}
+static const char *msm8x60_fluid_match[] __initdata = {
+        "qcom,msm8660-fluid",
+        "qcom,msm8660-surf",
+        NULL
+};
+#endif /* CONFIG_OF */
 MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3")
        .fixup = msm8x60_fixup,
        .reserve = msm8x60_reserve,
@@ -105,3 +138,14 @@ MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA")
        .init_machine = msm8x60_init,
        .timer = &msm_timer,
 MACHINE_END
+#ifdef CONFIG_OF
+/* TODO: General device tree support for all MSM. */
+DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
+        .map_io = msm8x60_map_io,
+        .init_irq = msm8x60_init_irq,
+        .init_machine = msm8x60_dt_init,
+        .timer = &msm_timer,
+        .dt_compat = msm8x60_fluid_match,
+MACHINE_END
+#endif /* CONFIG_OF */
diff --git a/arch/arm/mach-msm/hotplug.c b/arch/arm/mach-msm/hotplug.c
index 5a31f70dfb8e..41c252de0215 100644
--- a/arch/arm/mach-msm/hotplug.c
+++ b/arch/arm/mach-msm/hotplug.c
@@ -37,7 +37,7 @@ static inline void platform_do_lowpower(unsigned int cpu)
                    :
                    : "memory", "cc");
-                if (pen_release == cpu) {
+                if (pen_release == cpu_logical_map(cpu)) {
                        /*
                         * OK, proper wakeup, we're done
                         */
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index 727659520912..fdec58aaa35c 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -117,7 +117,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
         * Note that "pen_release" is the hardware CPU ID, whereas
         * "cpu" is Linux's internal ID.
         */
-        pen_release = cpu;
+        pen_release = cpu_logical_map(cpu);
        __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
        outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index b4e7c58bbb38..af0c212e3c7b 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -1,8 +1,9 @@
-if ARCH_MX503 || ARCH_MX51
+if ARCH_MX5
 # ARCH_MX5/50/53 are left to mark places where prevent multi-soc in single
 # image. So for most time, SOC_IMX50/51/53 should be used.
-config ARCH_MX5
+config ARCH_MX51
        bool
 config ARCH_MX50
@@ -19,7 +20,6 @@ config SOC_IMX50
        select ARCH_MXC_IOMUX_V3
        select ARCH_MXC_AUDMUX_V2
        select ARCH_HAS_CPUFREQ
-        select ARCH_MX5
        select ARCH_MX50
 config  SOC_IMX51
@@ -30,7 +30,7 @@ config	SOC_IMX51
        select ARCH_MXC_IOMUX_V3
        select ARCH_MXC_AUDMUX_V2
        select ARCH_HAS_CPUFREQ
-        select ARCH_MX5
+        select ARCH_MX51
 config  SOC_IMX53
        bool
@@ -38,10 +38,8 @@ config	SOC_IMX53
        select ARM_L1_CACHE_SHIFT_6
        select MXC_TZIC
        select ARCH_MXC_IOMUX_V3
-        select ARCH_MX5
        select ARCH_MX53
-if ARCH_MX50_SUPPORTED
 #comment "i.MX50 machines:"
 config MACH_MX50_RDP
@@ -52,22 +50,29 @@ config MACH_MX50_RDP
        select IMX_HAVE_PLATFORM_IMX_UART
        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
        select IMX_HAVE_PLATFORM_SPI_IMX
-        select IMX_HAVE_PLATFORM_FEC
        help
          Include support for MX50 reference design platform (RDP) board. This
          includes specific configurations for the board and its peripherals.
-endif # ARCH_MX50_SUPPORTED
-if ARCH_MX51
 comment "i.MX51 machines:"
+config MACH_IMX51_DT
+        bool "Support i.MX51 platforms from device tree"
+        select SOC_IMX51
+        select USE_OF
+        select MACH_MX51_BABBAGE
+        help
+          Include support for Freescale i.MX51 based platforms
+          using the device tree for discovery
 config MACH_MX51_BABBAGE
        bool "Support MX51 BABBAGE platforms"
        select SOC_IMX51
+        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
        select IMX_HAVE_PLATFORM_IMX2_WDT
        select IMX_HAVE_PLATFORM_IMX_I2C
        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_EHCI
        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
        select IMX_HAVE_PLATFORM_SPI_IMX
        help
@@ -91,8 +96,10 @@ config MACH_MX51_3DS
 config MACH_EUKREA_CPUIMX51
        bool "Support Eukrea CPUIMX51 module"
        select SOC_IMX51
+        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
        select IMX_HAVE_PLATFORM_IMX_I2C
        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_EHCI
        select IMX_HAVE_PLATFORM_MXC_NAND
        select IMX_HAVE_PLATFORM_SPI_IMX
        help
@@ -119,10 +126,12 @@ endchoice
 config MACH_EUKREA_CPUIMX51SD
        bool "Support Eukrea CPUIMX51SD module"
        select SOC_IMX51
+        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_SPI_IMX
        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_EHCI
        select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_SPI_IMX
        help
          Include support for Eukrea CPUIMX51SD platform. This includes
          specific configurations for the module and its peripherals.
@@ -147,6 +156,8 @@ config MX51_EFIKA_COMMON
        bool
        select SOC_IMX51
        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_EHCI
+        select IMX_HAVE_PLATFORM_PATA_IMX
        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
        select IMX_HAVE_PLATFORM_SPI_IMX
        select MXC_ULPI if USB_ULPI
@@ -167,11 +178,20 @@ config MACH_MX51_EFIKASB
          Include support for Genesi Efika Smartbook. This includes specific
          configurations for the board and its peripherals.
-endif # ARCH_MX51
-if ARCH_MX53_SUPPORTED
 comment "i.MX53 machines:"
+config MACH_IMX53_DT
+        bool "Support i.MX53 platforms from device tree"
+        select SOC_IMX53
+        select USE_OF
+        select MACH_MX53_ARD
+        select MACH_MX53_EVK
+        select MACH_MX53_LOCO
+        select MACH_MX53_SMD
+        help
+          Include support for Freescale i.MX53 based platforms
+          using the device tree for discovery
 config MACH_MX53_EVK
        bool "Support MX53 EVK platforms"
        select SOC_IMX53
@@ -221,6 +241,4 @@ config MACH_MX53_ARD
          Include support for MX53 ARD platform. This includes specific
          configurations for the board and its peripherals.
-endif # ARCH_MX53_SUPPORTED
 endif
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index 383e7cd3fbcb..0fc60807fa2b 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -3,8 +3,7 @@
 #
 # Object file lists.
-obj-y   := cpu.o mm.o clock-mx51-mx53.o devices.o ehci.o system.o
+obj-y   := cpu.o mm.o clock-mx51-mx53.o ehci.o system.o
-obj-$(CONFIG_SOC_IMX50) += mm-mx50.o
 obj-$(CONFIG_PM) += pm-imx5.o
 obj-$(CONFIG_CPU_FREQ_IMX)    += cpu_op-mx51.o
@@ -22,3 +21,6 @@ obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o
 obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o
 obj-$(CONFIG_MACH_MX51_EFIKASB) += board-mx51_efikasb.o
 obj-$(CONFIG_MACH_MX50_RDP) += board-mx50_rdp.o
+obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
+obj-$(CONFIG_MACH_IMX53_DT) += imx53-dt.o
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
index e01af948e043..1fc110348040 100644
--- a/arch/arm/mach-mx5/board-cpuimx51.c
+++ b/arch/arm/mach-mx5/board-cpuimx51.c
@@ -22,21 +22,18 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/interrupt.h>
-#include <linux/irq.h>
 #include <mach/eukrea-baseboards.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-mx51.h>
-#include <asm/irq.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include "devices-imx51.h"
-#include "devices.h"
 #define CPUIMX51_USBH1_STP      IMX_GPIO_NR(1, 27)
 #define CPUIMX51_QUARTA_GPIO    IMX_GPIO_NR(3, 28)
@@ -57,7 +54,7 @@
 static struct plat_serial8250_port serial_platform_data[] = {
        {
                .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000),
-                .irq = gpio_to_irq(CPUIMX51_QUARTA_GPIO),
+                .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTA_GPIO),
                .irqflags = IRQF_TRIGGER_HIGH,
                .uartclk = CPUIMX51_QUART_XTAL,
                .regshift = CPUIMX51_QUART_REGSHIFT,
@@ -65,7 +62,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
                .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
        }, {
                .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000),
-                .irq = gpio_to_irq(CPUIMX51_QUARTB_GPIO),
+                .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTB_GPIO),
                .irqflags = IRQF_TRIGGER_HIGH,
                .uartclk = CPUIMX51_QUART_XTAL,
                .regshift = CPUIMX51_QUART_REGSHIFT,
@@ -73,7 +70,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
                .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
        }, {
                .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000),
-                .irq = gpio_to_irq(CPUIMX51_QUARTC_GPIO),
+                .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTC_GPIO),
                .irqflags = IRQF_TRIGGER_HIGH,
                .uartclk = CPUIMX51_QUART_XTAL,
                .regshift = CPUIMX51_QUART_REGSHIFT,
@@ -81,7 +78,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
                .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
        }, {
                .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000),
-                .irq = gpio_to_irq(CPUIMX51_QUARTD_GPIO),
+                .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTD_GPIO),
                .irqflags = IRQF_TRIGGER_HIGH,
                .uartclk = CPUIMX51_QUART_XTAL,
                .regshift = CPUIMX51_QUART_REGSHIFT,
@@ -167,7 +164,7 @@ static int initialize_otg_port(struct platform_device *pdev)
        void __iomem *usb_base;
        void __iomem *usbother_base;
-        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
        if (!usb_base)
                return -ENOMEM;
        usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
@@ -190,7 +187,7 @@ static int initialize_usbh1_port(struct platform_device *pdev)
        void __iomem *usb_base;
        void __iomem *usbother_base;
-        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
        if (!usb_base)
                return -ENOMEM;
        usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
@@ -206,17 +203,17 @@ static int initialize_usbh1_port(struct platform_device *pdev)
                        MXC_EHCI_ITC_NO_THRESHOLD);
 }
-static struct mxc_usbh_platform_data dr_utmi_config = {
+static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
        .init           = initialize_otg_port,
        .portsc = MXC_EHCI_UTMI_16BIT,
 };
-static struct fsl_usb2_platform_data usb_pdata = {
+static const struct fsl_usb2_platform_data usb_pdata __initconst = {
        .operating_mode = FSL_USB2_DR_DEVICE,
        .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
 };
-static struct mxc_usbh_platform_data usbh1_config = {
+static const struct mxc_usbh_platform_data usbh1_config __initconst = {
        .init           = initialize_usbh1_port,
        .portsc = MXC_EHCI_MODE_ULPI,
 };
@@ -270,12 +267,12 @@ static void __init eukrea_cpuimx51_init(void)
                                ARRAY_SIZE(eukrea_cpuimx51_i2c_devices));
        if (otg_mode_host)
-                mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
+                imx51_add_mxc_ehci_otg(&dr_utmi_config);
        else {
                initialize_otg_port(NULL);
-                mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
+                imx51_add_fsl_usb2_udc(&usb_pdata);
        }
-        mxc_register_device(&mxc_usbh1_device, &usbh1_config);
+        imx51_add_mxc_ehci_hs(1, &usbh1_config);
 #ifdef CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD
        eukrea_mbimx51_baseboard_init();
@@ -297,6 +294,7 @@ MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
        .map_io = mx51_map_io,
        .init_early = imx51_init_early,
        .init_irq = mx51_init_irq,
+        .handle_irq = imx51_handle_irq,
        .timer = &mxc_timer,
        .init_machine = eukrea_cpuimx51_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c
index b41fc274a425..52a11c1898e6 100644
--- a/arch/arm/mach-mx5/board-cpuimx51sd.c
+++ b/arch/arm/mach-mx5/board-cpuimx51sd.c
@@ -22,7 +22,6 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/interrupt.h>
-#include <linux/irq.h>
 #include <linux/i2c-gpio.h>
 #include <linux/spi/spi.h>
 #include <linux/can/platform/mcp251x.h>
@@ -32,14 +31,12 @@
 #include <mach/hardware.h>
 #include <mach/iomux-mx51.h>
-#include <asm/irq.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include "devices-imx51.h"
-#include "devices.h"
 #include "cpu_op-mx51.h"
 #define USBH1_RST               IMX_GPIO_NR(2, 28)
@@ -108,7 +105,7 @@ static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
        /* Touchscreen */
        /* IRQ */
-        _MX51_PAD_GPIO_NAND__GPIO_NAND | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
+        NEW_PAD_CTRL(MX51_PAD_GPIO_NAND__GPIO_NAND, PAD_CTL_PUS_22K_UP |
                        PAD_CTL_PKE | PAD_CTL_SRE_FAST |
                        PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
 };
@@ -129,7 +126,7 @@ static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
                I2C_BOARD_INFO("tsc2007", 0x49),
                .type           = "tsc2007",
                .platform_data  = &tsc2007_info,
-                .irq            = gpio_to_irq(TSC2007_IRQGPIO),
+                .irq            = IMX_GPIO_TO_IRQ(TSC2007_IRQGPIO),
        },
 };
@@ -149,7 +146,7 @@ static int initialize_otg_port(struct platform_device *pdev)
        void __iomem *usb_base;
        void __iomem *usbother_base;
-        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
        if (!usb_base)
                return -ENOMEM;
        usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
@@ -172,7 +169,7 @@ static int initialize_usbh1_port(struct platform_device *pdev)
        void __iomem *usb_base;
        void __iomem *usbother_base;
-        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
        if (!usb_base)
                return -ENOMEM;
        usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
@@ -189,17 +186,17 @@ static int initialize_usbh1_port(struct platform_device *pdev)
                        MXC_EHCI_ITC_NO_THRESHOLD);
 }
-static struct mxc_usbh_platform_data dr_utmi_config = {
+static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
        .init           = initialize_otg_port,
        .portsc = MXC_EHCI_UTMI_16BIT,
 };
-static struct fsl_usb2_platform_data usb_pdata = {
+static const struct fsl_usb2_platform_data usb_pdata __initconst = {
        .operating_mode = FSL_USB2_DR_DEVICE,
        .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
 };
-static struct mxc_usbh_platform_data usbh1_config = {
+static const struct mxc_usbh_platform_data usbh1_config __initconst = {
        .init           = initialize_usbh1_port,
        .portsc = MXC_EHCI_MODE_ULPI,
 };
@@ -245,7 +242,7 @@ static struct spi_board_info cpuimx51sd_spi_device[] = {
                .mode           = SPI_MODE_0,
                .chip_select     = 0,
                .platform_data   = &mcp251x_info,
-                .irq             = gpio_to_irq(CAN_IRQGPIO)
+                .irq             = IMX_GPIO_TO_IRQ(CAN_IRQGPIO)
        },
 };
@@ -303,17 +300,17 @@ static void __init eukrea_cpuimx51sd_init(void)
        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
        if (otg_mode_host)
-                mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
+                imx51_add_mxc_ehci_otg(&dr_utmi_config);
        else {
                initialize_otg_port(NULL);
-                mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
+                imx51_add_fsl_usb2_udc(&usb_pdata);
        }
        gpio_request(USBH1_RST, "usb_rst");
        gpio_direction_output(USBH1_RST, 0);
        msleep(20);
        gpio_set_value(USBH1_RST, 1);
-        mxc_register_device(&mxc_usbh1_device, &usbh1_config);
+        imx51_add_mxc_ehci_hs(1, &usbh1_config);
 #ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD
        eukrea_mbimxsd51_baseboard_init();
@@ -335,6 +332,7 @@ MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
        .map_io = mx51_map_io,
        .init_early = imx51_init_early,
        .init_irq = mx51_init_irq,
+        .handle_irq = imx51_handle_irq,
        .timer = &mxc_timer,
        .init_machine = eukrea_cpuimx51sd_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx50_rdp.c b/arch/arm/mach-mx5/board-mx50_rdp.c
index 7de25c6712eb..fc3621d90bde 100644
--- a/arch/arm/mach-mx5/board-mx50_rdp.c
+++ b/arch/arm/mach-mx5/board-mx50_rdp.c
@@ -219,6 +219,7 @@ MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform")
        .map_io = mx50_map_io,
        .init_early = imx50_init_early,
        .init_irq = mx50_init_irq,
+        .handle_irq = imx50_handle_irq,
        .timer = &mx50_rdp_timer,
        .init_machine = mx50_rdp_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
index a50174e69e2f..05783906db2b 100644
--- a/arch/arm/mach-mx5/board-mx51_3ds.c
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -25,7 +25,6 @@
 #include <mach/3ds_debugboard.h>
 #include "devices-imx51.h"
-#include "devices.h"
 #define EXPIO_PARENT_INT        gpio_to_irq(IMX_GPIO_NR(1, 6))
 #define MX51_3DS_ECSPI2_CS      (GPIO_PORTC + 28)
@@ -173,6 +172,7 @@ MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
        .map_io = mx51_map_io,
        .init_early = imx51_init_early,
        .init_irq = mx51_init_irq,
+        .handle_irq = imx51_handle_irq,
        .timer = &mx51_3ds_timer,
        .init_machine = mx51_3ds_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index 468926a48fe0..5c837603ff0f 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -24,14 +24,12 @@
 #include <mach/hardware.h>
 #include <mach/iomux-mx51.h>
-#include <asm/irq.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include "devices-imx51.h"
-#include "devices.h"
 #include "cpu_op-mx51.h"
 #define BABBAGE_USB_HUB_RESET   IMX_GPIO_NR(1, 7)
@@ -176,7 +174,7 @@ static const struct imxi2c_platform_data babbage_i2c_data __initconst = {
        .bitrate = 100000,
 };
-static struct imxi2c_platform_data babbage_hsi2c_data = {
+static const struct imxi2c_platform_data babbage_hsi2c_data __initconst = {
        .bitrate = 400000,
 };
@@ -249,7 +247,7 @@ static int initialize_otg_port(struct platform_device *pdev)
        void __iomem *usb_base;
        void __iomem *usbother_base;
-        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
        if (!usb_base)
                return -ENOMEM;
        usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
@@ -272,7 +270,7 @@ static int initialize_usbh1_port(struct platform_device *pdev)
        void __iomem *usb_base;
        void __iomem *usbother_base;
-        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
        if (!usb_base)
                return -ENOMEM;
        usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
@@ -288,17 +286,17 @@ static int initialize_usbh1_port(struct platform_device *pdev)
                        MXC_EHCI_ITC_NO_THRESHOLD);
 }
-static struct mxc_usbh_platform_data dr_utmi_config = {
+static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
        .init           = initialize_otg_port,
        .portsc = MXC_EHCI_UTMI_16BIT,
 };
-static struct fsl_usb2_platform_data usb_pdata = {
+static const struct fsl_usb2_platform_data usb_pdata __initconst = {
        .operating_mode = FSL_USB2_DR_DEVICE,
        .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
 };
-static struct mxc_usbh_platform_data usbh1_config = {
+static const struct mxc_usbh_platform_data usbh1_config __initconst = {
        .init           = initialize_usbh1_port,
        .portsc = MXC_EHCI_MODE_ULPI,
 };
@@ -351,22 +349,27 @@ static const struct esdhc_platform_data mx51_babbage_sd2_data __initconst = {
        .wp_type = ESDHC_WP_GPIO,
 };
+void __init imx51_babbage_common_init(void)
+{
+        mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
+                                         ARRAY_SIZE(mx51babbage_pads));
+}
 /*
 * Board specific initialization.
 */
 static void __init mx51_babbage_init(void)
 {
        iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
-        iomux_v3_cfg_t power_key = _MX51_PAD_EIM_A27__GPIO2_21 |
+        iomux_v3_cfg_t power_key = NEW_PAD_CTRL(MX51_PAD_EIM_A27__GPIO2_21,
-                MUX_PAD_CTRL(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP);
+                PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP);
        imx51_soc_init();
 #if defined(CONFIG_CPU_FREQ_IMX)
        get_cpu_op = mx51_get_cpu_op;
 #endif
-        mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
+        imx51_babbage_common_init();
-                                        ARRAY_SIZE(mx51babbage_pads));
        imx51_add_imx_uart(0, &uart_pdata);
        imx51_add_imx_uart(1, NULL);
@@ -381,17 +384,17 @@ static void __init mx51_babbage_init(void)
        imx51_add_imx_i2c(0, &babbage_i2c_data);
        imx51_add_imx_i2c(1, &babbage_i2c_data);
-        mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data);
+        imx51_add_hsi2c(&babbage_hsi2c_data);
        if (otg_mode_host)
-                mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
+                imx51_add_mxc_ehci_otg(&dr_utmi_config);
        else {
                initialize_otg_port(NULL);
-                mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
+                imx51_add_fsl_usb2_udc(&usb_pdata);
        }
        gpio_usbh1_active();
-        mxc_register_device(&mxc_usbh1_device, &usbh1_config);
+        imx51_add_mxc_ehci_hs(1, &usbh1_config);
        /* setback USBH1_STP to be function */
        mxc_iomux_v3_setup_pad(usbh1stp);
        babbage_usbhub_reset();
@@ -420,6 +423,7 @@ MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
        .map_io = mx51_map_io,
        .init_early = imx51_init_early,
        .init_irq = mx51_init_irq,
+        .handle_irq = imx51_handle_irq,
        .timer = &mx51_babbage_timer,
        .init_machine = mx51_babbage_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c
index c36880da03f0..a9e48662cf75 100644
--- a/arch/arm/mach-mx5/board-mx51_efikamx.c
+++ b/arch/arm/mach-mx5/board-mx51_efikamx.c
@@ -32,14 +32,12 @@
 #include <mach/hardware.h>
 #include <mach/iomux-mx51.h>
-#include <asm/irq.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include "devices-imx51.h"
-#include "devices.h"
 #include "efika.h"
 #define EFIKAMX_PCBID0          IMX_GPIO_NR(3, 16)
@@ -163,6 +161,11 @@ static const struct gpio_led_platform_data
        .num_leds = ARRAY_SIZE(mx51_efikamx_leds),
 };
+static struct esdhc_platform_data sd_pdata = {
+        .cd_type = ESDHC_CD_CONTROLLER,
+        .wp_type = ESDHC_WP_CONTROLLER,
+};
 static struct gpio_keys_button mx51_efikamx_powerkey[] = {
        {
                .code = KEY_POWER,
@@ -239,9 +242,11 @@ static void __init mx51_efikamx_init(void)
        /* on < 1.2 boards both SD controllers are used */
        if (system_rev < 0x12) {
-                imx51_add_sdhci_esdhc_imx(1, NULL);
+                imx51_add_sdhci_esdhc_imx(0, NULL);
+                imx51_add_sdhci_esdhc_imx(1, &sd_pdata);
                mx51_efikamx_leds[2].default_trigger = "mmc1";
-        }
+        } else
+                imx51_add_sdhci_esdhc_imx(0, &sd_pdata);
        gpio_led_register_device(-1, &mx51_efikamx_leds_data);
        imx_add_gpio_keys(&mx51_efikamx_powerkey_data);
@@ -284,6 +289,7 @@ MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop")
        .map_io = mx51_map_io,
        .init_early = imx51_init_early,
        .init_irq = mx51_init_irq,
+        .handle_irq = imx51_handle_irq,
        .timer = &mx51_efikamx_timer,
        .init_machine = mx51_efikamx_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_efikasb.c b/arch/arm/mach-mx5/board-mx51_efikasb.c
index ba5436a9fb1a..38c4a3e28d3c 100644
--- a/arch/arm/mach-mx5/board-mx51_efikasb.c
+++ b/arch/arm/mach-mx5/board-mx51_efikasb.c
@@ -35,14 +35,12 @@
 #include <mach/hardware.h>
 #include <mach/iomux-mx51.h>
-#include <asm/irq.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include "devices-imx51.h"
-#include "devices.h"
 #include "efika.h"
 #define EFIKASB_USBH2_STP       IMX_GPIO_NR(2, 20)
@@ -56,6 +54,7 @@
 #define EFIKASB_RFKILL          IMX_GPIO_NR(3, 1)
 #define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
+#define MX51_PAD_SD1_CD IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_ESDHC_PAD_CTRL)
 static iomux_v3_cfg_t mx51efikasb_pads[] = {
        /* USB HOST2 */
@@ -97,6 +96,8 @@ static iomux_v3_cfg_t mx51efikasb_pads[] = {
        /* BT */
        MX51_PAD_EIM_A17__GPIO2_11,
+        MX51_PAD_SD1_CD,
 };
 static int initialize_usbh2_port(struct platform_device *pdev)
@@ -119,7 +120,7 @@ static int initialize_usbh2_port(struct platform_device *pdev)
        return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
 }
-static struct mxc_usbh_platform_data usbh2_config = {
+static struct mxc_usbh_platform_data usbh2_config __initdata = {
        .init   = initialize_usbh2_port,
        .portsc = MXC_EHCI_MODE_ULPI,
 };
@@ -129,7 +130,7 @@ static void __init mx51_efikasb_usb(void)
        usbh2_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
                        ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
        if (usbh2_config.otg)
-                mxc_register_device(&mxc_usbh2_device, &usbh2_config);
+                imx51_add_mxc_ehci_hs(2, &usbh2_config);
 }
 static const struct gpio_led mx51_efikasb_leds[] __initconst = {
@@ -182,6 +183,18 @@ static const struct gpio_keys_platform_data mx51_efikasb_keys_data __initconst =
        .nbuttons = ARRAY_SIZE(mx51_efikasb_keys),
 };
+static struct esdhc_platform_data sd0_pdata = {
+#define EFIKASB_SD1_CD  IMX_GPIO_NR(2, 27)
+        .cd_gpio = EFIKASB_SD1_CD,
+        .cd_type = ESDHC_CD_GPIO,
+        .wp_type = ESDHC_WP_CONTROLLER,
+};
+static struct esdhc_platform_data sd1_pdata = {
+        .cd_type = ESDHC_CD_CONTROLLER,
+        .wp_type = ESDHC_WP_CONTROLLER,
+};
 static struct regulator *pwgt1, *pwgt2;
 static void mx51_efikasb_power_off(void)
@@ -250,7 +263,8 @@ static void __init efikasb_board_init(void)
        mx51_efikasb_board_id();
        mx51_efikasb_usb();
-        imx51_add_sdhci_esdhc_imx(1, NULL);
+        imx51_add_sdhci_esdhc_imx(0, &sd0_pdata);
+        imx51_add_sdhci_esdhc_imx(1, &sd1_pdata);
        gpio_led_register_device(-1, &mx51_efikasb_leds_data);
        imx_add_gpio_keys(&mx51_efikasb_keys_data);
@@ -270,6 +284,7 @@ MACHINE_START(MX51_EFIKASB, "Genesi Efika Smartbook")
        .map_io = mx51_map_io,
        .init_early = imx51_init_early,
        .init_irq = mx51_init_irq,
+        .handle_irq = imx51_handle_irq,
        .init_machine =  efikasb_board_init,
        .timer = &mx51_efikasb_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_ard.c b/arch/arm/mach-mx5/board-mx53_ard.c
index 76a67c4a2a0b..0d7f0fffb23a 100644
--- a/arch/arm/mach-mx5/board-mx53_ard.c
+++ b/arch/arm/mach-mx5/board-mx53_ard.c
@@ -134,8 +134,8 @@ static struct resource ard_smsc911x_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
-                .start =  gpio_to_irq(ARD_ETHERNET_INT_B),
+                .start =  IMX_GPIO_TO_IRQ(ARD_ETHERNET_INT_B),
-                .end =  gpio_to_irq(ARD_ETHERNET_INT_B),
+                .end =  IMX_GPIO_TO_IRQ(ARD_ETHERNET_INT_B),
                .flags = IORESOURCE_IRQ,
        },
 };
@@ -171,9 +171,6 @@ static struct imxi2c_platform_data mx53_ard_i2c3_data = {
 static void __init mx53_ard_io_init(void)
 {
-        mxc_iomux_v3_setup_multiple_pads(mx53_ard_pads,
-                                ARRAY_SIZE(mx53_ard_pads));
        gpio_request(ARD_ETHERNET_INT_B, "eth-int-b");
        gpio_direction_input(ARD_ETHERNET_INT_B);
@@ -216,6 +213,13 @@ static int weim_cs_config(void)
        return 0;
 }
+void __init imx53_ard_common_init(void)
+{
+        mxc_iomux_v3_setup_multiple_pads(mx53_ard_pads,
+                                         ARRAY_SIZE(mx53_ard_pads));
+        weim_cs_config();
+}
 static struct platform_device *devices[] __initdata = {
        &ard_smsc_lan9220_device,
 };
@@ -225,8 +229,8 @@ static void __init mx53_ard_board_init(void)
        imx53_soc_init();
        imx53_add_imx_uart(0, NULL);
+        imx53_ard_common_init();
        mx53_ard_io_init();
-        weim_cs_config();
        platform_add_devices(devices, ARRAY_SIZE(devices));
        imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data);
@@ -234,6 +238,7 @@ static void __init mx53_ard_board_init(void)
        imx53_add_imx_i2c(1, &mx53_ard_i2c2_data);
        imx53_add_imx_i2c(2, &mx53_ard_i2c3_data);
        imx_add_gpio_keys(&ard_button_data);
+        imx53_add_ahci_imx();
 }
 static void __init mx53_ard_timer_init(void)
@@ -249,6 +254,7 @@ MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board")
        .map_io = mx53_map_io,
        .init_early = imx53_init_early,
        .init_irq = mx53_init_irq,
+        .handle_irq = imx53_handle_irq,
        .timer = &mx53_ard_timer,
        .init_machine = mx53_ard_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c
index 1b417b06b736..6bea31ab8f85 100644
--- a/arch/arm/mach-mx5/board-mx53_evk.c
+++ b/arch/arm/mach-mx5/board-mx53_evk.c
@@ -131,12 +131,17 @@ static const struct spi_imx_master mx53_evk_spi_data __initconst = {
        .num_chipselect = ARRAY_SIZE(mx53_evk_spi_cs),
 };
+void __init imx53_evk_common_init(void)
+{
+        mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads,
+                                         ARRAY_SIZE(mx53_evk_pads));
+}
 static void __init mx53_evk_board_init(void)
 {
        imx53_soc_init();
+        imx53_evk_common_init();
-        mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads,
-                                        ARRAY_SIZE(mx53_evk_pads));
        mx53_evk_init_uart();
        mx53_evk_fec_reset();
        imx53_add_fec(&mx53_evk_fec_pdata);
@@ -167,6 +172,7 @@ MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board")
        .map_io = mx53_map_io,
        .init_early = imx53_init_early,
        .init_irq = mx53_init_irq,
+        .handle_irq = imx53_handle_irq,
        .timer = &mx53_evk_timer,
        .init_machine = mx53_evk_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c
index 4e1d51d252dc..7678f7734db6 100644
--- a/arch/arm/mach-mx5/board-mx53_loco.c
+++ b/arch/arm/mach-mx5/board-mx53_loco.c
@@ -22,6 +22,7 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/gpio.h>
+#include <linux/i2c.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
@@ -42,6 +43,7 @@
 #define LOCO_SD3_CD                     IMX_GPIO_NR(3, 11)
 #define LOCO_SD3_WP                     IMX_GPIO_NR(3, 12)
 #define LOCO_SD1_CD                     IMX_GPIO_NR(3, 13)
+#define LOCO_ACCEL_EN                   IMX_GPIO_NR(6, 14)
 static iomux_v3_cfg_t mx53_loco_pads[] = {
        /* FEC */
@@ -64,6 +66,10 @@ static iomux_v3_cfg_t mx53_loco_pads[] = {
        MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD,
        MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS,
        MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD,
+        /* I2C1 */
+        MX53_PAD_CSI0_DAT8__I2C1_SDA,
+        MX53_PAD_CSI0_DAT9__I2C1_SCL,
+        MX53_PAD_NANDF_CS1__GPIO6_14,   /* Accelerometer Enable */
        /* I2C2 */
        MX53_PAD_KEY_COL3__I2C2_SCL,
        MX53_PAD_KEY_ROW3__I2C2_SDA,
@@ -257,22 +263,42 @@ static const struct gpio_led_platform_data mx53loco_leds_data __initconst = {
        .num_leds       = ARRAY_SIZE(mx53loco_leds),
 };
+void __init imx53_qsb_common_init(void)
+{
+        mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
+                                         ARRAY_SIZE(mx53_loco_pads));
+}
+static struct i2c_board_info mx53loco_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("mma8450", 0x1C),
+        },
+};
 static void __init mx53_loco_board_init(void)
 {
+        int ret;
        imx53_soc_init();
+        imx53_qsb_common_init();
-        mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
-                                        ARRAY_SIZE(mx53_loco_pads));
        imx53_add_imx_uart(0, NULL);
        mx53_loco_fec_reset();
        imx53_add_fec(&mx53_loco_fec_data);
        imx53_add_imx2_wdt(0, NULL);
+        ret = gpio_request_one(LOCO_ACCEL_EN, GPIOF_OUT_INIT_HIGH, "accel_en");
+        if (ret)
+                pr_err("Cannot request ACCEL_EN pin: %d\n", ret);
+        i2c_register_board_info(0, mx53loco_i2c_devices,
+                                ARRAY_SIZE(mx53loco_i2c_devices));
        imx53_add_imx_i2c(0, &mx53_loco_i2c_data);
        imx53_add_imx_i2c(1, &mx53_loco_i2c_data);
        imx53_add_sdhci_esdhc_imx(0, &mx53_loco_sd1_data);
        imx53_add_sdhci_esdhc_imx(2, &mx53_loco_sd3_data);
        imx_add_gpio_keys(&loco_button_data);
        gpio_led_register_device(-1, &mx53loco_leds_data);
+        imx53_add_ahci_imx();
 }
 static void __init mx53_loco_timer_init(void)
@@ -288,6 +314,7 @@ MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board")
        .map_io = mx53_map_io,
        .init_early = imx53_init_early,
        .init_irq = mx53_init_irq,
+        .handle_irq = imx53_handle_irq,
        .timer = &mx53_loco_timer,
        .init_machine = mx53_loco_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c
index bc02894eafef..59c0845eb4a6 100644
--- a/arch/arm/mach-mx5/board-mx53_smd.c
+++ b/arch/arm/mach-mx5/board-mx53_smd.c
@@ -35,6 +35,7 @@
 #include "devices-imx53.h"
 #define SMD_FEC_PHY_RST         IMX_GPIO_NR(7, 6)
+#define MX53_SMD_SATA_PWR_EN    IMX_GPIO_NR(3, 3)
 static iomux_v3_cfg_t mx53_smd_pads[] = {
        MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
@@ -111,12 +112,30 @@ static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = {
        .bitrate = 100000,
 };
+static inline void mx53_smd_ahci_pwr_on(void)
+{
+        int ret;
+        /* Enable SATA PWR */
+        ret = gpio_request_one(MX53_SMD_SATA_PWR_EN,
+                        GPIOF_DIR_OUT | GPIOF_INIT_HIGH, "ahci-sata-pwr");
+        if (ret) {
+                pr_err("failed to enable SATA_PWR_EN: %d\n", ret);
+                return;
+        }
+}
+void __init imx53_smd_common_init(void)
+{
+        mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads,
+                                         ARRAY_SIZE(mx53_smd_pads));
+}
 static void __init mx53_smd_board_init(void)
 {
        imx53_soc_init();
+        imx53_smd_common_init();
-        mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads,
-                                        ARRAY_SIZE(mx53_smd_pads));
        mx53_smd_init_uart();
        mx53_smd_fec_reset();
        imx53_add_fec(&mx53_smd_fec_data);
@@ -125,6 +144,8 @@ static void __init mx53_smd_board_init(void)
        imx53_add_sdhci_esdhc_imx(0, NULL);
        imx53_add_sdhci_esdhc_imx(1, NULL);
        imx53_add_sdhci_esdhc_imx(2, NULL);
+        mx53_smd_ahci_pwr_on();
+        imx53_add_ahci_imx();
 }
 static void __init mx53_smd_timer_init(void)
@@ -140,6 +161,7 @@ MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board")
        .map_io = mx53_map_io,
        .init_early = imx53_init_early,
        .init_irq = mx53_init_irq,
+        .handle_irq = imx53_handle_irq,
        .timer = &mx53_smd_timer,
        .init_machine = mx53_smd_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index f7bf996f463b..2aacf41c48e7 100644
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -15,6 +15,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/clkdev.h>
+#include <linux/of.h>
 #include <asm/div64.h>
@@ -1401,6 +1402,22 @@ static struct clk esdhc4_mx53_clk = {
        .secondary = &esdhc4_ipg_clk,
 };
+static struct clk sata_clk = {
+        .parent = &ipg_clk,
+        .enable = _clk_max_enable,
+        .enable_reg = MXC_CCM_CCGR4,
+        .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
+        .disable = _clk_max_disable,
+};
+static struct clk ahci_phy_clk = {
+        .parent = &usb_phy1_clk,
+};
+static struct clk ahci_dma_clk = {
+        .parent = &ahb_clk,
+};
 DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk);
 DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk);
 DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk);
@@ -1418,6 +1435,10 @@ DEFINE_CLOCK(ipu_di0_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG5_OFFSET,
 DEFINE_CLOCK(ipu_di1_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG6_OFFSET,
                NULL, NULL, &pll3_sw_clk, NULL);
+/* PATA */
+DEFINE_CLOCK(pata_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG0_OFFSET,
+                NULL, NULL, &ipg_clk, &spba_clk);
 #define _REGISTER_CLOCK(d, n, c) \
       { \
                .dev_id = d, \
@@ -1474,6 +1495,7 @@ static struct clk_lookup mx51_lookups[] = {
        _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk)
        _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk)
        _REGISTER_CLOCK(NULL, "gpc_dvfs", gpc_dvfs_clk)
+        _REGISTER_CLOCK("pata_imx", NULL, pata_clk)
 };
 static struct clk_lookup mx53_lookups[] = {
@@ -1507,6 +1529,10 @@ static struct clk_lookup mx53_lookups[] = {
        _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
        _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk)
        _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk)
+        _REGISTER_CLOCK("pata_imx", NULL, pata_clk)
+        _REGISTER_CLOCK("imx53-ahci.0", "ahci", sata_clk)
+        _REGISTER_CLOCK("imx53-ahci.0", "ahci_phy", ahci_phy_clk)
+        _REGISTER_CLOCK("imx53-ahci.0", "ahci_dma", ahci_dma_clk)
 };
 static void clk_tree_init(void)
@@ -1548,9 +1574,8 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
        clk_enable(&main_bus_clk);
        clk_enable(&iim_clk);
-        mx51_revision();
+        imx_print_silicon_rev("i.MX51", mx51_revision());
        clk_disable(&iim_clk);
-        mx51_display_revision();
        /* move usb_phy_clk to 24MHz */
        clk_set_parent(&usb_phy1_clk, &osc_clk);
@@ -1568,7 +1593,7 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
        /* System timer */
        mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
-                MX51_MXC_INT_GPT);
+                MX51_INT_GPT);
        return 0;
 }
@@ -1592,9 +1617,8 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
        clk_enable(&main_bus_clk);
        clk_enable(&iim_clk);
-        mx53_revision();
+        imx_print_silicon_rev("i.MX53", mx53_revision());
        clk_disable(&iim_clk);
-        mx53_display_revision();
        /* Set SDHC parents to be PLL2 */
        clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
@@ -1609,3 +1633,41 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
                MX53_INT_GPT);
        return 0;
 }
+static void __init clk_get_freq_dt(unsigned long *ckil, unsigned long *osc,
+                                   unsigned long *ckih1, unsigned long *ckih2)
+{
+        struct device_node *np;
+        /* retrieve the freqency of fixed clocks from device tree */
+        for_each_compatible_node(np, NULL, "fixed-clock") {
+                u32 rate;
+                if (of_property_read_u32(np, "clock-frequency", &rate))
+                        continue;
+                if (of_device_is_compatible(np, "fsl,imx-ckil"))
+                        *ckil = rate;
+                else if (of_device_is_compatible(np, "fsl,imx-osc"))
+                        *osc = rate;
+                else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
+                        *ckih1 = rate;
+                else if (of_device_is_compatible(np, "fsl,imx-ckih2"))
+                        *ckih2 = rate;
+        }
+}
+int __init mx51_clocks_init_dt(void)
+{
+        unsigned long ckil, osc, ckih1, ckih2;
+        clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
+        return mx51_clocks_init(ckil, osc, ckih1, ckih2);
+}
+int __init mx53_clocks_init_dt(void)
+{
+        unsigned long ckil, osc, ckih1, ckih2;
+        clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
+        return mx53_clocks_init(ckil, osc, ckih1, ckih2);
+}
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
index 86f87da59c64..5c5328257dca 100644
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-mx5/cpu.c
@@ -18,7 +18,7 @@
 #include <mach/hardware.h>
 #include <asm/io.h>
-static int cpu_silicon_rev = -1;
+static int mx5_cpu_rev = -1;
 #define IIM_SREV 0x24
 #define MX50_HW_ADADIG_DIGPROG  0xB0
@@ -28,11 +28,14 @@ static int get_mx51_srev(void)
        void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR);
        u32 rev = readl(iim_base + IIM_SREV) & 0xff;
-        if (rev == 0x0)
+        switch (rev) {
+        case 0x0:
                return IMX_CHIP_REVISION_2_0;
-        else if (rev == 0x10)
+        case 0x10:
                return IMX_CHIP_REVISION_3_0;
-        return 0;
+        default:
+                return IMX_CHIP_REVISION_UNKNOWN;
+        }
 }
 /*
@@ -45,33 +48,13 @@ int mx51_revision(void)
        if (!cpu_is_mx51())
                return -EINVAL;
-        if (cpu_silicon_rev == -1)
+        if (mx5_cpu_rev == -1)
-                cpu_silicon_rev = get_mx51_srev();
+                mx5_cpu_rev = get_mx51_srev();
-        return cpu_silicon_rev;
+        return mx5_cpu_rev;
 }
 EXPORT_SYMBOL(mx51_revision);
-void mx51_display_revision(void)
-{
-        int rev;
-        char *srev;
-        rev = mx51_revision();
-        switch (rev) {
-        case IMX_CHIP_REVISION_2_0:
-                srev = IMX_CHIP_REVISION_2_0_STRING;
-                break;
-        case IMX_CHIP_REVISION_3_0:
-                srev = IMX_CHIP_REVISION_3_0_STRING;
-                break;
-        default:
-                srev = IMX_CHIP_REVISION_UNKNOWN_STRING;
-        }
-        printk(KERN_INFO "CPU identified as i.MX51, silicon rev %s\n", srev);
-}
-EXPORT_SYMBOL(mx51_display_revision);
 #ifdef CONFIG_NEON
 /*
@@ -121,10 +104,10 @@ int mx53_revision(void)
        if (!cpu_is_mx53())
                return -EINVAL;
-        if (cpu_silicon_rev == -1)
+        if (mx5_cpu_rev == -1)
-                cpu_silicon_rev = get_mx53_srev();
+                mx5_cpu_rev = get_mx53_srev();
-        return cpu_silicon_rev;
+        return mx5_cpu_rev;
 }
 EXPORT_SYMBOL(mx53_revision);
@@ -134,7 +117,7 @@ static int get_mx50_srev(void)
        u32 rev;
        if (!anatop) {
-                cpu_silicon_rev = -EINVAL;
+                mx5_cpu_rev = -EINVAL;
                return 0;
        }
@@ -159,36 +142,13 @@ int mx50_revision(void)
        if (!cpu_is_mx50())
                return -EINVAL;
-        if (cpu_silicon_rev == -1)
+        if (mx5_cpu_rev == -1)
-                cpu_silicon_rev = get_mx50_srev();
+                mx5_cpu_rev = get_mx50_srev();
-        return cpu_silicon_rev;
+        return mx5_cpu_rev;
 }
 EXPORT_SYMBOL(mx50_revision);
-void mx53_display_revision(void)
-{
-        int rev;
-        char *srev;
-        rev = mx53_revision();
-        switch (rev) {
-        case IMX_CHIP_REVISION_1_0:
-                srev = IMX_CHIP_REVISION_1_0_STRING;
-                break;
-        case IMX_CHIP_REVISION_2_0:
-                srev = IMX_CHIP_REVISION_2_0_STRING;
-                break;
-        case IMX_CHIP_REVISION_2_1:
-                srev = IMX_CHIP_REVISION_2_1_STRING;
-                break;
-        default:
-                srev = IMX_CHIP_REVISION_UNKNOWN_STRING;
-        }
-        printk(KERN_INFO "CPU identified as i.MX53, silicon rev %s\n", srev);
-}
-EXPORT_SYMBOL(mx53_display_revision);
 static int __init post_cpu_init(void)
 {
        unsigned int reg;
diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h
index e11bc0e0ec49..af488bc0e225 100644
--- a/arch/arm/mach-mx5/devices-imx51.h
+++ b/arch/arm/mach-mx5/devices-imx51.h
@@ -13,9 +13,15 @@ extern const struct imx_fec_data imx51_fec_data;
 #define imx51_add_fec(pdata)    \
        imx_add_fec(&imx51_fec_data, pdata)
+extern const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data;
+#define imx51_add_fsl_usb2_udc(pdata)   \
+        imx_add_fsl_usb2_udc(&imx51_fsl_usb2_udc_data, pdata)
 extern const struct imx_imx_i2c_data imx51_imx_i2c_data[];
 #define imx51_add_imx_i2c(id, pdata)    \
        imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata)
+#define imx51_add_hsi2c(pdata)  \
+        imx51_add_imx_i2c(2, pdata)
 extern const struct imx_imx_ssi_data imx51_imx_ssi_data[];
 #define imx51_add_imx_ssi(id, pdata)    \
@@ -25,6 +31,13 @@ extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[];
 #define imx51_add_imx_uart(id, pdata)   \
        imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata)
+extern const struct imx_mxc_ehci_data imx51_mxc_ehci_otg_data;
+#define imx51_add_mxc_ehci_otg(pdata)   \
+        imx_add_mxc_ehci(&imx51_mxc_ehci_otg_data, pdata)
+extern const struct imx_mxc_ehci_data imx51_mxc_ehci_hs_data[];
+#define imx51_add_mxc_ehci_hs(id, pdata)        \
+        imx_add_mxc_ehci(&imx51_mxc_ehci_hs_data[id - 1], pdata)
 extern const struct imx_mxc_nand_data imx51_mxc_nand_data;
 #define imx51_add_mxc_nand(pdata)       \
        imx_add_mxc_nand(&imx51_mxc_nand_data, pdata)
@@ -52,3 +65,7 @@ extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[];
 extern const struct imx_imx_keypad_data imx51_imx_keypad_data;
 #define imx51_add_imx_keypad(pdata)     \
        imx_add_imx_keypad(&imx51_imx_keypad_data, pdata)
+extern const struct imx_pata_imx_data imx51_pata_imx_data;
+#define imx51_add_pata_imx() \
+        imx_add_pata_imx(&imx51_pata_imx_data)
diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h
index c27fe8bb4762..6e1e5d1f8c3a 100644
--- a/arch/arm/mach-mx5/devices-imx53.h
+++ b/arch/arm/mach-mx5/devices-imx53.h
@@ -40,3 +40,9 @@ extern const struct imx_imx_ssi_data imx53_imx_ssi_data[];
 extern const struct imx_imx_keypad_data imx53_imx_keypad_data;
 #define imx53_add_imx_keypad(pdata)     \
        imx_add_imx_keypad(&imx53_imx_keypad_data, pdata)
+extern const struct imx_pata_imx_data imx53_pata_imx_data;
+#define imx53_add_pata_imx() \
+        imx_add_pata_imx(&imx53_pata_imx_data)
+extern struct platform_device *__init imx53_add_ahci_imx(void);
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
deleted file mode 100644
index 371ca8c8414c..000000000000
--- a/arch/arm/mach-mx5/devices.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Copyright 2009 Amit Kucheria <amit.kucheria@canonical.com>
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <mach/hardware.h>
-#include <mach/imx-uart.h>
-#include <mach/irqs.h>
-static struct resource mxc_hsi2c_resources[] = {
-        {
-                .start = MX51_HSI2C_DMA_BASE_ADDR,
-                .end = MX51_HSI2C_DMA_BASE_ADDR + SZ_16K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .start = MX51_MXC_INT_HS_I2C,
-                .end = MX51_MXC_INT_HS_I2C,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-struct platform_device mxc_hsi2c_device = {
-        .name = "imx-i2c",
-        .id = 2,
-        .num_resources = ARRAY_SIZE(mxc_hsi2c_resources),
-        .resource = mxc_hsi2c_resources
-};
-static u64 usb_dma_mask = DMA_BIT_MASK(32);
-static struct resource usbotg_resources[] = {
-        {
-                .start = MX51_OTG_BASE_ADDR,
-                .end = MX51_OTG_BASE_ADDR + 0x1ff,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .start = MX51_MXC_INT_USB_OTG,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-/* OTG gadget device */
-struct platform_device mxc_usbdr_udc_device = {
-        .name           = "fsl-usb2-udc",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(usbotg_resources),
-        .resource       = usbotg_resources,
-        .dev            = {
-                .dma_mask               = &usb_dma_mask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-};
-struct platform_device mxc_usbdr_host_device = {
-        .name = "mxc-ehci",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(usbotg_resources),
-        .resource = usbotg_resources,
-        .dev = {
-                .dma_mask = &usb_dma_mask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-};
-static struct resource usbh1_resources[] = {
-        {
-                .start = MX51_OTG_BASE_ADDR + 0x200,
-                .end = MX51_OTG_BASE_ADDR + 0x200 + 0x1ff,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .start = MX51_MXC_INT_USB_H1,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-struct platform_device mxc_usbh1_device = {
-        .name = "mxc-ehci",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(usbh1_resources),
-        .resource = usbh1_resources,
-        .dev = {
-                .dma_mask = &usb_dma_mask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-};
-static struct resource usbh2_resources[] = {
-        {
-                .start = MX51_OTG_BASE_ADDR + 0x400,
-                .end = MX51_OTG_BASE_ADDR + 0x400 + 0x1ff,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .start = MX51_MXC_INT_USB_H2,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-struct platform_device mxc_usbh2_device = {
-        .name = "mxc-ehci",
-        .id = 2,
-        .num_resources = ARRAY_SIZE(usbh2_resources),
-        .resource = usbh2_resources,
-        .dev = {
-                .dma_mask = &usb_dma_mask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-};
diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h
deleted file mode 100644
index 55a5129bc29f..000000000000
--- a/arch/arm/mach-mx5/devices.h
+++ /dev/null
@@ -1,5 +0,0 @@
-extern struct platform_device mxc_usbdr_host_device;
-extern struct platform_device mxc_usbh1_device;
-extern struct platform_device mxc_usbh2_device;
-extern struct platform_device mxc_usbdr_udc_device;
-extern struct platform_device mxc_hsi2c_device;
diff --git a/arch/arm/mach-mx5/ehci.c b/arch/arm/mach-mx5/ehci.c
index 7ce12c804a32..c17fa131728b 100644
--- a/arch/arm/mach-mx5/ehci.c
+++ b/arch/arm/mach-mx5/ehci.c
@@ -52,7 +52,7 @@ int mx51_initialize_usb_hw(int port, unsigned int flags)
        void __iomem *usbother_base;
        int ret = 0;
-        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
        if (!usb_base) {
                printk(KERN_ERR "%s(): ioremap failed\n", __func__);
                return -ENOMEM;
diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
index bbf4564bd050..a6a3ab8f1b1c 100644
--- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
+++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
@@ -28,7 +28,6 @@
 #include <asm/mach/arch.h>
 #include "devices-imx51.h"
-#include "devices.h"
 #define MBIMX51_TSC2007_GPIO    IMX_GPIO_NR(3, 30)
 #define MBIMX51_LED0            IMX_GPIO_NR(3, 5)
@@ -160,7 +159,7 @@ struct tsc2007_platform_data tsc2007_data = {
 static struct i2c_board_info mbimx51_i2c_devices[] = {
        {
                I2C_BOARD_INFO("tsc2007", 0x49),
-                .irq  = gpio_to_irq(MBIMX51_TSC2007_GPIO),
+                .irq  = IMX_GPIO_TO_IRQ(MBIMX51_TSC2007_GPIO),
                .platform_data = &tsc2007_data,
        }, {
                I2C_BOARD_INFO("tlv320aic23", 0x1a),
diff --git a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
index 261923997643..d817fc80b986 100644
--- a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
@@ -24,7 +24,6 @@
 #include <linux/gpio.h>
 #include <linux/interrupt.h>
-#include <linux/irq.h>
 #include <linux/leds.h>
 #include <linux/platform_device.h>
 #include <linux/input.h>
@@ -41,13 +40,12 @@
 #include <mach/audmux.h>
 #include "devices-imx51.h"
-#include "devices.h"
 static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
        /* LED */
        MX51_PAD_NANDF_D10__GPIO3_30,
        /* SWITCH */
-        _MX51_PAD_NANDF_D9__GPIO3_31 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
+        NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, PAD_CTL_PUS_22K_UP |
                        PAD_CTL_PKE | PAD_CTL_SRE_FAST |
                        PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
        /* UART2 */
@@ -66,7 +64,7 @@ static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
        MX51_PAD_SD1_DATA2__SD1_DATA2,
        MX51_PAD_SD1_DATA3__SD1_DATA3,
        /* SD1 CD */
-        _MX51_PAD_GPIO1_0__SD1_CD | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
+        NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_PUS_22K_UP |
                        PAD_CTL_PKE | PAD_CTL_SRE_FAST |
                        PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
 };
diff --git a/arch/arm/mach-mx5/imx51-dt.c b/arch/arm/mach-mx5/imx51-dt.c
new file mode 100644
index 000000000000..ccc61585659b
--- /dev/null
+++ b/arch/arm/mach-mx5/imx51-dt.c
@@ -0,0 +1,116 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/common.h>
+#include <mach/mx51.h>
+/*
+ * Lookup table for attaching a specific name and platform_data pointer to
+ * devices as they get created by of_platform_populate().  Ideally this table
+ * would not exist, but the current clock implementation depends on some devices
+ * having a specific name.
+ */
+static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = {
+        OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART1_BASE_ADDR, "imx21-uart.0", NULL),
+        OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART2_BASE_ADDR, "imx21-uart.1", NULL),
+        OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART3_BASE_ADDR, "imx21-uart.2", NULL),
+        OF_DEV_AUXDATA("fsl,imx51-fec", MX51_FEC_BASE_ADDR, "imx27-fec.0", NULL),
+        OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC1_BASE_ADDR, "sdhci-esdhc-imx51.0", NULL),
+        OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC2_BASE_ADDR, "sdhci-esdhc-imx51.1", NULL),
+        OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC3_BASE_ADDR, "sdhci-esdhc-imx51.2", NULL),
+        OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC4_BASE_ADDR, "sdhci-esdhc-imx51.3", NULL),
+        OF_DEV_AUXDATA("fsl,imx51-ecspi", MX51_ECSPI1_BASE_ADDR, "imx51-ecspi.0", NULL),
+        OF_DEV_AUXDATA("fsl,imx51-ecspi", MX51_ECSPI2_BASE_ADDR, "imx51-ecspi.1", NULL),
+        OF_DEV_AUXDATA("fsl,imx51-cspi", MX51_CSPI_BASE_ADDR, "imx35-cspi.0", NULL),
+        OF_DEV_AUXDATA("fsl,imx51-i2c", MX51_I2C1_BASE_ADDR, "imx-i2c.0", NULL),
+        OF_DEV_AUXDATA("fsl,imx51-i2c", MX51_I2C2_BASE_ADDR, "imx-i2c.1", NULL),
+        OF_DEV_AUXDATA("fsl,imx51-sdma", MX51_SDMA_BASE_ADDR, "imx35-sdma", NULL),
+        OF_DEV_AUXDATA("fsl,imx51-wdt", MX51_WDOG1_BASE_ADDR, "imx2-wdt.0", NULL),
+        { /* sentinel */ }
+};
+static void __init imx51_tzic_add_irq_domain(struct device_node *np,
+                                struct device_node *interrupt_parent)
+{
+        irq_domain_add_simple(np, 0);
+}
+static void __init imx51_gpio_add_irq_domain(struct device_node *np,
+                                struct device_node *interrupt_parent)
+{
+        static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS -
+                                   32 * 4; /* imx51 gets 4 gpio ports */
+        irq_domain_add_simple(np, gpio_irq_base);
+        gpio_irq_base += 32;
+}
+static const struct of_device_id imx51_irq_match[] __initconst = {
+        { .compatible = "fsl,imx51-tzic", .data = imx51_tzic_add_irq_domain, },
+        { .compatible = "fsl,imx51-gpio", .data = imx51_gpio_add_irq_domain, },
+        { /* sentinel */ }
+};
+static const struct of_device_id imx51_iomuxc_of_match[] __initconst = {
+        { .compatible = "fsl,imx51-iomuxc-babbage", .data = imx51_babbage_common_init, },
+        { /* sentinel */ }
+};
+static void __init imx51_dt_init(void)
+{
+        struct device_node *node;
+        const struct of_device_id *of_id;
+        void (*func)(void);
+        of_irq_init(imx51_irq_match);
+        node = of_find_matching_node(NULL, imx51_iomuxc_of_match);
+        if (node) {
+                of_id = of_match_node(imx51_iomuxc_of_match, node);
+                func = of_id->data;
+                func();
+                of_node_put(node);
+        }
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             imx51_auxdata_lookup, NULL);
+}
+static void __init imx51_timer_init(void)
+{
+        mx51_clocks_init_dt();
+}
+static struct sys_timer imx51_timer = {
+        .init = imx51_timer_init,
+};
+static const char *imx51_dt_board_compat[] __initdata = {
+        "fsl,imx51-babbage",
+        NULL
+};
+DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)")
+        .map_io         = mx51_map_io,
+        .init_early     = imx51_init_early,
+        .init_irq       = mx51_init_irq,
+        .handle_irq     = imx51_handle_irq,
+        .timer          = &imx51_timer,
+        .init_machine   = imx51_dt_init,
+        .dt_compat      = imx51_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-mx5/imx53-dt.c b/arch/arm/mach-mx5/imx53-dt.c
new file mode 100644
index 000000000000..ccaa0b81b768
--- /dev/null
+++ b/arch/arm/mach-mx5/imx53-dt.c
@@ -0,0 +1,126 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/common.h>
+#include <mach/mx53.h>
+/*
+ * Lookup table for attaching a specific name and platform_data pointer to
+ * devices as they get created by of_platform_populate().  Ideally this table
+ * would not exist, but the current clock implementation depends on some devices
+ * having a specific name.
+ */
+static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = {
+        OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART1_BASE_ADDR, "imx21-uart.0", NULL),
+        OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART2_BASE_ADDR, "imx21-uart.1", NULL),
+        OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART3_BASE_ADDR, "imx21-uart.2", NULL),
+        OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART4_BASE_ADDR, "imx21-uart.3", NULL),
+        OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART5_BASE_ADDR, "imx21-uart.4", NULL),
+        OF_DEV_AUXDATA("fsl,imx53-fec", MX53_FEC_BASE_ADDR, "imx25-fec.0", NULL),
+        OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC1_BASE_ADDR, "sdhci-esdhc-imx53.0", NULL),
+        OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC2_BASE_ADDR, "sdhci-esdhc-imx53.1", NULL),
+        OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC3_BASE_ADDR, "sdhci-esdhc-imx53.2", NULL),
+        OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC4_BASE_ADDR, "sdhci-esdhc-imx53.3", NULL),
+        OF_DEV_AUXDATA("fsl,imx53-ecspi", MX53_ECSPI1_BASE_ADDR, "imx51-ecspi.0", NULL),
+        OF_DEV_AUXDATA("fsl,imx53-ecspi", MX53_ECSPI2_BASE_ADDR, "imx51-ecspi.1", NULL),
+        OF_DEV_AUXDATA("fsl,imx53-cspi", MX53_CSPI_BASE_ADDR, "imx35-cspi.0", NULL),
+        OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C1_BASE_ADDR, "imx-i2c.0", NULL),
+        OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C2_BASE_ADDR, "imx-i2c.1", NULL),
+        OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C3_BASE_ADDR, "imx-i2c.2", NULL),
+        OF_DEV_AUXDATA("fsl,imx53-sdma", MX53_SDMA_BASE_ADDR, "imx35-sdma", NULL),
+        OF_DEV_AUXDATA("fsl,imx53-wdt", MX53_WDOG1_BASE_ADDR, "imx2-wdt.0", NULL),
+        { /* sentinel */ }
+};
+static void __init imx53_tzic_add_irq_domain(struct device_node *np,
+                                struct device_node *interrupt_parent)
+{
+        irq_domain_add_simple(np, 0);
+}
+static void __init imx53_gpio_add_irq_domain(struct device_node *np,
+                                struct device_node *interrupt_parent)
+{
+        static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS -
+                                   32 * 7; /* imx53 gets 7 gpio ports */
+        irq_domain_add_simple(np, gpio_irq_base);
+        gpio_irq_base += 32;
+}
+static const struct of_device_id imx53_irq_match[] __initconst = {
+        { .compatible = "fsl,imx53-tzic", .data = imx53_tzic_add_irq_domain, },
+        { .compatible = "fsl,imx53-gpio", .data = imx53_gpio_add_irq_domain, },
+        { /* sentinel */ }
+};
+static const struct of_device_id imx53_iomuxc_of_match[] __initconst = {
+        { .compatible = "fsl,imx53-iomuxc-ard", .data = imx53_ard_common_init, },
+        { .compatible = "fsl,imx53-iomuxc-evk", .data = imx53_evk_common_init, },
+        { .compatible = "fsl,imx53-iomuxc-qsb", .data = imx53_qsb_common_init, },
+        { .compatible = "fsl,imx53-iomuxc-smd", .data = imx53_smd_common_init, },
+        { /* sentinel */ }
+};
+static void __init imx53_dt_init(void)
+{
+        struct device_node *node;
+        const struct of_device_id *of_id;
+        void (*func)(void);
+        of_irq_init(imx53_irq_match);
+        node = of_find_matching_node(NULL, imx53_iomuxc_of_match);
+        if (node) {
+                of_id = of_match_node(imx53_iomuxc_of_match, node);
+                func = of_id->data;
+                func();
+                of_node_put(node);
+        }
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             imx53_auxdata_lookup, NULL);
+}
+static void __init imx53_timer_init(void)
+{
+        mx53_clocks_init_dt();
+}
+static struct sys_timer imx53_timer = {
+        .init = imx53_timer_init,
+};
+static const char *imx53_dt_board_compat[] __initdata = {
+        "fsl,imx53-ard",
+        "fsl,imx53-evk",
+        "fsl,imx53-qsb",
+        "fsl,imx53-smd",
+        NULL
+};
+DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)")
+        .map_io         = mx53_map_io,
+        .init_early     = imx53_init_early,
+        .init_irq       = mx53_init_irq,
+        .handle_irq     = imx53_handle_irq,
+        .timer          = &imx53_timer,
+        .init_machine   = imx53_dt_init,
+        .dt_compat      = imx53_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-mx5/mm-mx50.c b/arch/arm/mach-mx5/mm-mx50.c
deleted file mode 100644
index 77e374c726fa..000000000000
--- a/arch/arm/mach-mx5/mm-mx50.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Create static mapping between physical to virtual memory.
- */
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <asm/mach/map.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/iomux-v3.h>
-#include <mach/irqs.h>
-/*
- * Define the MX50 memory map.
- */
-static struct map_desc mx50_io_desc[] __initdata = {
-        imx_map_entry(MX50, TZIC, MT_DEVICE),
-        imx_map_entry(MX50, SPBA0, MT_DEVICE),
-        imx_map_entry(MX50, AIPS1, MT_DEVICE),
-        imx_map_entry(MX50, AIPS2, MT_DEVICE),
-};
-/*
- * This function initializes the memory map. It is called during the
- * system startup to create static physical to virtual memory mappings
- * for the IO modules.
- */
-void __init mx50_map_io(void)
-{
-        iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
-}
-void __init imx50_init_early(void)
-{
-        mxc_set_cpu_type(MXC_CPU_MX50);
-        mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
-        mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
-}
-void __init mx50_init_irq(void)
-{
-        tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
-}
-void __init imx50_soc_init(void)
-{
-        /* i.mx50 has the i.mx31 type gpio */
-        mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
-        mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
-        mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
-        mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
-        mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
-        mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
-}
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
index baea6e5cddd9..26eacc9d0d90 100644
--- a/arch/arm/mach-mx5/mm.c
+++ b/arch/arm/mach-mx5/mm.c
@@ -21,12 +21,27 @@
 #include <mach/devices-common.h>
 #include <mach/iomux-v3.h>
+static void imx5_idle(void)
+{
+        mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
+}
+/*
+ * Define the MX50 memory map.
+ */
+static struct map_desc mx50_io_desc[] __initdata = {
+        imx_map_entry(MX50, TZIC, MT_DEVICE),
+        imx_map_entry(MX50, SPBA0, MT_DEVICE),
+        imx_map_entry(MX50, AIPS1, MT_DEVICE),
+        imx_map_entry(MX50, AIPS2, MT_DEVICE),
+};
 /*
 * Define the MX51 memory map.
 */
 static struct map_desc mx51_io_desc[] __initdata = {
+        imx_map_entry(MX51, TZIC, MT_DEVICE),
        imx_map_entry(MX51, IRAM, MT_DEVICE),
-        imx_map_entry(MX51, DEBUG, MT_DEVICE),
        imx_map_entry(MX51, AIPS1, MT_DEVICE),
        imx_map_entry(MX51, SPBA0, MT_DEVICE),
        imx_map_entry(MX51, AIPS2, MT_DEVICE),
@@ -36,6 +51,7 @@ static struct map_desc mx51_io_desc[] __initdata = {
 * Define the MX53 memory map.
 */
 static struct map_desc mx53_io_desc[] __initdata = {
+        imx_map_entry(MX53, TZIC, MT_DEVICE),
        imx_map_entry(MX53, AIPS1, MT_DEVICE),
        imx_map_entry(MX53, SPBA0, MT_DEVICE),
        imx_map_entry(MX53, AIPS2, MT_DEVICE),
@@ -46,21 +62,34 @@ static struct map_desc mx53_io_desc[] __initdata = {
 * system startup to create static physical to virtual memory mappings
 * for the IO modules.
 */
+void __init mx50_map_io(void)
+{
+        iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
+}
 void __init mx51_map_io(void)
 {
        iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
 }
+void __init mx53_map_io(void)
+{
+        iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
+}
+void __init imx50_init_early(void)
+{
+        mxc_set_cpu_type(MXC_CPU_MX50);
+        mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
+        mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
+}
 void __init imx51_init_early(void)
 {
        mxc_set_cpu_type(MXC_CPU_MX51);
        mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
        mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
-}
+        imx_idle = imx5_idle;
-void __init mx53_map_io(void)
-{
-        iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
 }
 void __init imx53_init_early(void)
@@ -70,35 +99,19 @@ void __init imx53_init_early(void)
        mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
 }
-void __init mx51_init_irq(void)
+void __init mx50_init_irq(void)
 {
-        unsigned long tzic_addr;
+        tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
-        void __iomem *tzic_virt;
+}
-        if (mx51_revision() < IMX_CHIP_REVISION_2_0)
-                tzic_addr = MX51_TZIC_BASE_ADDR_TO1;
-        else
-                tzic_addr = MX51_TZIC_BASE_ADDR;
-        tzic_virt = ioremap(tzic_addr, SZ_16K);
-        if (!tzic_virt)
-                panic("unable to map TZIC interrupt controller\n");
-        tzic_init_irq(tzic_virt);
+void __init mx51_init_irq(void)
+{
+        tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
 }
 void __init mx53_init_irq(void)
 {
-        unsigned long tzic_addr;
+        tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR));
-        void __iomem *tzic_virt;
-        tzic_addr = MX53_TZIC_BASE_ADDR;
-        tzic_virt = ioremap(tzic_addr, SZ_16K);
-        if (!tzic_virt)
-                panic("unable to map TZIC interrupt controller\n");
-        tzic_init_irq(tzic_virt);
 }
 static struct sdma_script_start_addrs imx51_sdma_script __initdata = {
@@ -138,13 +151,24 @@ static struct sdma_platform_data imx53_sdma_pdata __initdata = {
        .script_addrs = &imx53_sdma_script,
 };
+void __init imx50_soc_init(void)
+{
+        /* i.mx50 has the i.mx31 type gpio */
+        mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
+        mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
+        mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
+        mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
+        mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
+        mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
+}
 void __init imx51_soc_init(void)
 {
        /* i.mx51 has the i.mx31 type gpio */
-        mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO1_LOW, MX51_MXC_INT_GPIO1_HIGH);
+        mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH);
-        mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO2_LOW, MX51_MXC_INT_GPIO2_HIGH);
+        mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH);
-        mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO3_LOW, MX51_MXC_INT_GPIO3_HIGH);
+        mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH);
-        mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO4_LOW, MX51_MXC_INT_GPIO4_HIGH);
+        mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH);
        /* i.mx51 has the i.mx35 type sdma */
        imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
diff --git a/arch/arm/mach-mx5/mx51_efika.c b/arch/arm/mach-mx5/mx51_efika.c
index c9209454807a..b004e178417d 100644
--- a/arch/arm/mach-mx5/mx51_efika.c
+++ b/arch/arm/mach-mx5/mx51_efika.c
@@ -34,14 +34,12 @@
 #include <linux/usb/ulpi.h>
 #include <mach/ulpi.h>
-#include <asm/irq.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include "devices-imx51.h"
-#include "devices.h"
 #include "efika.h"
 #include "cpu_op-mx51.h"
@@ -133,7 +131,7 @@ static int initialize_otg_port(struct platform_device *pdev)
        u32 v;
        void __iomem *usb_base;
        void __iomem *usbother_base;
-        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
        if (!usb_base)
                return -ENOMEM;
        usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
@@ -150,7 +148,7 @@ static int initialize_otg_port(struct platform_device *pdev)
        return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
 }
-static struct mxc_usbh_platform_data dr_utmi_config = {
+static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
        .init   = initialize_otg_port,
        .portsc = MXC_EHCI_UTMI_16BIT,
 };
@@ -170,7 +168,7 @@ static int initialize_usbh1_port(struct platform_device *pdev)
        gpio_set_value(EFIKAMX_USBH1_STP, 1);
        msleep(1);
-        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
        socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
        /* The clock for the USBH1 ULPI port will come externally */
@@ -189,7 +187,7 @@ static int initialize_usbh1_port(struct platform_device *pdev)
        return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
 }
-static struct mxc_usbh_platform_data usbh1_config = {
+static struct mxc_usbh_platform_data usbh1_config __initdata = {
        .init   = initialize_usbh1_port,
        .portsc = MXC_EHCI_MODE_ULPI,
 };
@@ -217,9 +215,9 @@ static void __init mx51_efika_usb(void)
        usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
                        ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
-        mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
+        imx51_add_mxc_ehci_otg(&dr_utmi_config);
        if (usbh1_config.otg)
-                mxc_register_device(&mxc_usbh1_device, &usbh1_config);
+                imx51_add_mxc_ehci_hs(1, &usbh1_config);
 }
 static struct mtd_partition mx51_efika_spi_nor_partitions[] = {
@@ -589,7 +587,7 @@ static struct spi_board_info mx51_efika_spi_board_info[] __initdata = {
                .bus_num = 0,
                .chip_select = 0,
                .platform_data = &mx51_efika_mc13892_data,
-                .irq = gpio_to_irq(EFIKAMX_PMIC),
+                .irq = IMX_GPIO_TO_IRQ(EFIKAMX_PMIC),
        },
 };
@@ -609,7 +607,6 @@ void __init efika_board_common_init(void)
                                        ARRAY_SIZE(mx51efika_pads));
        imx51_add_imx_uart(0, &uart_pdata);
        mx51_efika_usb();
-        imx51_add_sdhci_esdhc_imx(0, NULL);
        /* FIXME: comes from original code. check this. */
        if (mx51_revision() < IMX_CHIP_REVISION_2_0)
@@ -627,8 +624,9 @@ void __init efika_board_common_init(void)
                ARRAY_SIZE(mx51_efika_spi_board_info));
        imx51_add_ecspi(0, &mx51_efika_spi_pdata);
+        imx51_add_pata_imx();
 #if defined(CONFIG_CPU_FREQ_IMX)
        get_cpu_op = mx51_get_cpu_op;
 #endif
 }
diff --git a/arch/arm/mach-mx5/pm-imx5.c b/arch/arm/mach-mx5/pm-imx5.c
index e4529af0da72..98052fc852c7 100644
--- a/arch/arm/mach-mx5/pm-imx5.c
+++ b/arch/arm/mach-mx5/pm-imx5.c
@@ -14,14 +14,19 @@
 #include <linux/err.h>
 #include <asm/cacheflush.h>
 #include <asm/tlbflush.h>
-#include <mach/system.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
 #include "crm_regs.h"
 static struct clk *gpc_dvfs_clk;
+static int mx5_suspend_prepare(void)
+{
+        return clk_enable(gpc_dvfs_clk);
+}
 static int mx5_suspend_enter(suspend_state_t state)
 {
-        clk_enable(gpc_dvfs_clk);
        switch (state) {
        case PM_SUSPEND_MEM:
                mx5_cpu_lp_set(STOP_POWER_OFF);
@@ -42,11 +47,14 @@ static int mx5_suspend_enter(suspend_state_t state)
                __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR);
        }
        cpu_do_idle();
-        clk_disable(gpc_dvfs_clk);
        return 0;
 }
+static void mx5_suspend_finish(void)
+{
+        clk_disable(gpc_dvfs_clk);
+}
 static int mx5_pm_valid(suspend_state_t state)
 {
        return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX);
@@ -54,7 +62,9 @@ static int mx5_pm_valid(suspend_state_t state)
 static const struct platform_suspend_ops mx5_suspend_ops = {
        .valid = mx5_pm_valid,
+        .prepare = mx5_suspend_prepare,
        .enter = mx5_suspend_enter,
+        .finish = mx5_suspend_finish,
 };
 static int __init mx5_pm_init(void)
diff --git a/arch/arm/mach-mx5/system.c b/arch/arm/mach-mx5/system.c
index 76ae8dc33e00..144ebebc4a61 100644
--- a/arch/arm/mach-mx5/system.c
+++ b/arch/arm/mach-mx5/system.c
@@ -13,6 +13,7 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <mach/hardware.h>
+#include <mach/common.h>
 #include "crm_regs.h"
 /* set cpu low power mode before WFI instruction. This function is called
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 4cd0231ee539..cf00b3e3be85 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -23,6 +23,7 @@ config MACH_STMP378X_DEVB
        select MXS_HAVE_AMBA_DUART
        select MXS_HAVE_PLATFORM_AUART
        select MXS_HAVE_PLATFORM_MXS_MMC
+        select MXS_HAVE_PLATFORM_RTC_STMP3XXX
        help
          Include support for STMP378x-devb platform. This includes specific
          configurations for the board and its peripherals.
@@ -34,6 +35,7 @@ config MACH_MX23EVK
        select MXS_HAVE_PLATFORM_AUART
        select MXS_HAVE_PLATFORM_MXS_MMC
        select MXS_HAVE_PLATFORM_MXSFB
+        select MXS_HAVE_PLATFORM_RTC_STMP3XXX
        help
          Include support for MX23EVK platform. This includes specific
          configurations for the board and its peripherals.
@@ -48,6 +50,9 @@ config MACH_MX28EVK
        select MXS_HAVE_PLATFORM_FLEXCAN
        select MXS_HAVE_PLATFORM_MXS_MMC
        select MXS_HAVE_PLATFORM_MXSFB
+        select MXS_HAVE_PLATFORM_MXS_SAIF
+        select MXS_HAVE_PLATFORM_MXS_I2C
+        select MXS_HAVE_PLATFORM_RTC_STMP3XXX
        select MXS_OCOTP
        help
          Include support for MX28EVK platform. This includes specific
@@ -63,9 +68,27 @@ config MODULE_TX28
        select MXS_HAVE_PLATFORM_MXS_I2C
        select MXS_HAVE_PLATFORM_MXS_MMC
        select MXS_HAVE_PLATFORM_MXS_PWM
+        select MXS_HAVE_PLATFORM_RTC_STMP3XXX
+config MODULE_M28
+        bool
+        select SOC_IMX28
+        select LEDS_GPIO_REGISTER
+        select MXS_HAVE_AMBA_DUART
+        select MXS_HAVE_PLATFORM_AUART
+        select MXS_HAVE_PLATFORM_FEC
+        select MXS_HAVE_PLATFORM_FLEXCAN
+        select MXS_HAVE_PLATFORM_MXS_I2C
+        select MXS_HAVE_PLATFORM_MXS_MMC
+        select MXS_HAVE_PLATFORM_MXSFB
+        select MXS_OCOTP
 config MACH_TX28
        bool "Ka-Ro TX28 module"
        select MODULE_TX28
+config MACH_M28EVK
+        bool "Support DENX M28EVK Platform"
+        select MODULE_M28
 endif
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index 6c38262a3aaa..8c93b24896bf 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -1,15 +1,16 @@
 # Common support
-obj-y := clock.o devices.o icoll.o iomux.o system.o timer.o
+obj-y := clock.o devices.o icoll.o iomux.o system.o timer.o mm.o
 obj-$(CONFIG_MXS_OCOTP) += ocotp.o
 obj-$(CONFIG_PM) += pm.o
-obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o
+obj-$(CONFIG_SOC_IMX23) += clock-mx23.o
-obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o
+obj-$(CONFIG_SOC_IMX28) += clock-mx28.o
 obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
 obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
 obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
+obj-$(CONFIG_MACH_M28EVK)    += mach-m28evk.o
 obj-$(CONFIG_MODULE_TX28) += module-tx28.o
 obj-$(CONFIG_MACH_TX28)    += mach-tx28.o
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
index 5dcc59d5b9ec..229ae3494216 100644
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -349,7 +349,7 @@ static int name##_set_rate(struct clk *clk, unsigned long rate)		\
                                                                        \
                reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
                reg &= ~BM_CLKCTRL_##fr##_##fs##FRAC;                   \
-                reg |= frac;                                            \
+                reg |= frac << BP_CLKCTRL_##fr##_##fs##FRAC;            \
                __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
        }                                                               \
                                                                        \
@@ -640,6 +640,8 @@ static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK(NULL, "lradc", lradc_clk)
        _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
        _REGISTER_CLOCK("imx28-fb", NULL, lcdif_clk)
+        _REGISTER_CLOCK("mxs-saif.0", NULL, saif0_clk)
+        _REGISTER_CLOCK("mxs-saif.1", NULL, saif1_clk)
 };
 static int clk_misc_init(void)
@@ -708,11 +710,11 @@ static int clk_misc_init(void)
        /* SAIF has to use frac div for functional operation */
        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
-        reg &= ~BM_CLKCTRL_SAIF0_DIV_FRAC_EN;
+        reg |= BM_CLKCTRL_SAIF0_DIV_FRAC_EN;
        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
-        reg &= ~BM_CLKCTRL_SAIF1_DIV_FRAC_EN;
+        reg |= BM_CLKCTRL_SAIF1_DIV_FRAC_EN;
        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
        /*
@@ -738,11 +740,17 @@ static int clk_misc_init(void)
        __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
-        /* Extra fec clock setting */
+        /*
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
+         * Extra fec clock setting
-        reg &= ~BM_CLKCTRL_ENET_SLEEP;
+         * The DENX M28 uses an external clock source
-        reg |= BM_CLKCTRL_ENET_CLK_OUT_EN;
+         * and the clock output must not be enabled
-        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
+         */
+        if (!machine_is_m28evk()) {
+                reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
+                reg &= ~BM_CLKCTRL_ENET_SLEEP;
+                reg |= BM_CLKCTRL_ENET_CLK_OUT_EN;
+                __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
+        }
        /*
         * 480 MHz seems too high to be ssp clock source directly,
@@ -774,6 +782,8 @@ int __init mx28_clocks_init(void)
        clk_enable(&uart_clk);
        clk_set_parent(&lcdif_clk, &ref_pix_clk);
+        clk_set_parent(&saif0_clk, &pll0_clk);
+        clk_set_parent(&saif1_clk, &pll0_clk);
        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h
index c6f345febd39..3fa651d2c994 100644
--- a/arch/arm/mach-mxs/devices-mx23.h
+++ b/arch/arm/mach-mxs/devices-mx23.h
@@ -29,3 +29,5 @@ extern const struct mxs_mxs_mmc_data mx23_mxs_mmc_data[] __initconst;
 struct platform_device *__init mx23_add_mxsfb(
                const struct mxsfb_platform_data *pdata);
+struct platform_device *__init mx23_add_rtc_stmp3xxx(void);
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h
index 79b94523954a..c8887103f0e3 100644
--- a/arch/arm/mach-mxs/devices-mx28.h
+++ b/arch/arm/mach-mxs/devices-mx28.h
@@ -45,3 +45,8 @@ extern const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst;
 struct platform_device *__init mx28_add_mxsfb(
                const struct mxsfb_platform_data *pdata);
+extern const struct mxs_saif_data mx28_saif_data[] __initconst;
+#define mx28_add_saif(id)              mxs_add_saif(&mx28_saif_data[id])
+struct platform_device *__init mx28_add_rtc_stmp3xxx(void);
diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig
index acf9eea124c0..18b6bf526a27 100644
--- a/arch/arm/mach-mxs/devices/Kconfig
+++ b/arch/arm/mach-mxs/devices/Kconfig
@@ -23,3 +23,9 @@ config MXS_HAVE_PLATFORM_MXS_PWM
 config MXS_HAVE_PLATFORM_MXSFB
        bool
+config MXS_HAVE_PLATFORM_MXS_SAIF
+        bool
+config MXS_HAVE_PLATFORM_RTC_STMP3XXX
+        bool
diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile
index 351915c683ff..f52e3e53baec 100644
--- a/arch/arm/mach-mxs/devices/Makefile
+++ b/arch/arm/mach-mxs/devices/Makefile
@@ -8,3 +8,5 @@ obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_MMC) += platform-mxs-mmc.o
 obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o
 obj-y += platform-gpio-mxs.o
 obj-$(CONFIG_MXS_HAVE_PLATFORM_MXSFB) += platform-mxsfb.o
+obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_SAIF) += platform-mxs-saif.o
+obj-$(CONFIG_MXS_HAVE_PLATFORM_RTC_STMP3XXX) += platform-rtc-stmp3xxx.o
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-saif.c b/arch/arm/mach-mxs/devices/platform-mxs-saif.c
new file mode 100644
index 000000000000..1ec965e9fe92
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-mxs-saif.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <linux/compiler.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <mach/mx23.h>
+#include <mach/mx28.h>
+#include <mach/devices-common.h>
+#define mxs_saif_data_entry_single(soc, _id)                            \
+        {                                                               \
+                .id = _id,                                              \
+                .iobase = soc ## _SAIF ## _id ## _BASE_ADDR,            \
+                .irq = soc ## _INT_SAIF ## _id,                         \
+                .dma = soc ## _DMA_SAIF ## _id,                         \
+                .dmairq = soc ## _INT_SAIF ## _id ##_DMA,               \
+        }
+#define mxs_saif_data_entry(soc, _id)                                   \
+        [_id] = mxs_saif_data_entry_single(soc, _id)
+#ifdef CONFIG_SOC_IMX28
+const struct mxs_saif_data mx28_saif_data[] __initconst = {
+        mxs_saif_data_entry(MX28, 0),
+        mxs_saif_data_entry(MX28, 1),
+};
+#endif
+struct platform_device *__init mxs_add_saif(const struct mxs_saif_data *data)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + SZ_4K - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                }, {
+                        .start = data->dma,
+                        .end = data->dma,
+                        .flags = IORESOURCE_DMA,
+                }, {
+                        .start = data->dmairq,
+                        .end = data->dmairq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+        return mxs_add_platform_device("mxs-saif", data->id, res,
+                                        ARRAY_SIZE(res), NULL, 0);
+}
diff --git a/arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c b/arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c
new file mode 100644
index 000000000000..639eaee15553
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2011 Pengutronix, Wolfram Sang <w.sang@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <asm/sizes.h>
+#include <mach/mx23.h>
+#include <mach/mx28.h>
+#include <mach/devices-common.h>
+#ifdef CONFIG_SOC_IMX23
+struct platform_device *__init mx23_add_rtc_stmp3xxx(void)
+{
+        struct resource res[] = {
+                {
+                        .start = MX23_RTC_BASE_ADDR,
+                        .end = MX23_RTC_BASE_ADDR + SZ_8K - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = MX23_INT_RTC_ALARM,
+                        .end = MX23_INT_RTC_ALARM,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+        return mxs_add_platform_device("stmp3xxx-rtc", 0, res, ARRAY_SIZE(res),
+                                        NULL, 0);
+}
+#endif /* CONFIG_SOC_IMX23 */
+#ifdef CONFIG_SOC_IMX28
+struct platform_device *__init mx28_add_rtc_stmp3xxx(void)
+{
+        struct resource res[] = {
+                {
+                        .start = MX28_RTC_BASE_ADDR,
+                        .end = MX28_RTC_BASE_ADDR + SZ_8K - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = MX28_INT_RTC_ALARM,
+                        .end = MX28_INT_RTC_ALARM,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+        return mxs_add_platform_device("stmp3xxx-rtc", 0, res, ARRAY_SIZE(res),
+                                        NULL, 0);
+}
+#endif /* CONFIG_SOC_IMX28 */
diff --git a/arch/arm/mach-mxs/include/mach/debug-macro.S b/arch/arm/mach-mxs/include/mach/debug-macro.S
index 714570d83668..90c6b7836ad3 100644
--- a/arch/arm/mach-mxs/include/mach/debug-macro.S
+++ b/arch/arm/mach-mxs/include/mach/debug-macro.S
@@ -14,17 +14,9 @@
 #include <mach/mx23.h>
 #include <mach/mx28.h>
-#ifdef CONFIG_SOC_IMX23
+#ifdef CONFIG_DEBUG_IMX23_UART
-#ifdef UART_PADDR
-#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
-#endif
 #define UART_PADDR      MX23_DUART_BASE_ADDR
-#endif
+#elif defined (CONFIG_DEBUG_IMX28_UART)
-#ifdef CONFIG_SOC_IMX28
-#ifdef UART_PADDR
-#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
-#endif
 #define UART_PADDR      MX28_DUART_BASE_ADDR
 #endif
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h
index 812d7a813a78..a8080f44c03d 100644
--- a/arch/arm/mach-mxs/include/mach/devices-common.h
+++ b/arch/arm/mach-mxs/include/mach/devices-common.h
@@ -92,3 +92,15 @@ struct platform_device *__init mxs_add_mxs_mmc(
 /* pwm */
 struct platform_device *__init mxs_add_mxs_pwm(
                resource_size_t iobase, int id);
+/* saif */
+struct mxs_saif_data {
+        int id;
+        resource_size_t iobase;
+        resource_size_t irq;
+        resource_size_t dma;
+        resource_size_t dmairq;
+};
+struct platform_device *__init mxs_add_saif(
+                const struct mxs_saif_data *data);
diff --git a/arch/arm/mach-mxs/include/mach/gpio.h b/arch/arm/mach-mxs/include/mach/gpio.h
index bb11e63261e4..40a8c178f10d 100644
--- a/arch/arm/mach-mxs/include/mach/gpio.h
+++ b/arch/arm/mach-mxs/include/mach/gpio.h
@@ -1,27 +1 @@
-/*
+/* empty */
- * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA  02110-1301, USA.
- */
-#ifndef __MACH_MXS_GPIO_H__
-#define __MACH_MXS_GPIO_H__
-#define MXS_GPIO_NR(bank, nr)   ((bank) * 32 + (nr))
-#define irq_to_gpio(irq)        ((irq) - MXS_GPIO_IRQ_START)
-#endif /* __MACH_MXS_GPIO_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/mxs.h b/arch/arm/mach-mxs/include/mach/mxs.h
index 35a89dd27242..0d2d2b470998 100644
--- a/arch/arm/mach-mxs/include/mach/mxs.h
+++ b/arch/arm/mach-mxs/include/mach/mxs.h
@@ -33,6 +33,7 @@
                0)
 #define cpu_is_mx28()           (                                       \
                machine_is_mx28evk() ||                                 \
+                machine_is_m28evk() ||                                  \
                machine_is_tx28() ||                                    \
                0)
@@ -86,6 +87,8 @@
        .type = _type,                                                  \
 }
+#define MXS_GPIO_NR(bank, nr)   ((bank) * 32 + (nr))
 #define MXS_SET_ADDR            0x4
 #define MXS_CLR_ADDR            0x8
 #define MXS_TOG_ADDR            0xc
diff --git a/arch/arm/mach-mxs/include/mach/uncompress.h b/arch/arm/mach-mxs/include/mach/uncompress.h
index 7f8bf6539646..67776746f143 100644
--- a/arch/arm/mach-mxs/include/mach/uncompress.h
+++ b/arch/arm/mach-mxs/include/mach/uncompress.h
@@ -63,6 +63,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
                mxs_duart_base = MX23_DUART_BASE_ADDR;
                break;
        case MACH_TYPE_MX28EVK:
+        case MACH_TYPE_M28EVK:
        case MACH_TYPE_TX28:
                mxs_duart_base = MX28_DUART_BASE_ADDR;
                break;
diff --git a/arch/arm/mach-mxs/mach-m28evk.c b/arch/arm/mach-mxs/mach-m28evk.c
new file mode 100644
index 000000000000..3b1681e4f49a
--- /dev/null
+++ b/arch/arm/mach-mxs/mach-m28evk.c
@@ -0,0 +1,366 @@
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
+ *
+ * based on: mach-mx28_evk.c
+ * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/irq.h>
+#include <linux/clk.h>
+#include <linux/i2c.h>
+#include <linux/i2c/at24.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/common.h>
+#include <mach/iomux-mx28.h>
+#include "devices-mx28.h"
+#define M28EVK_GPIO_USERLED1    MXS_GPIO_NR(3, 16)
+#define M28EVK_GPIO_USERLED2    MXS_GPIO_NR(3, 17)
+#define MX28EVK_BL_ENABLE       MXS_GPIO_NR(3, 18)
+#define M28EVK_LCD_ENABLE       MXS_GPIO_NR(3, 28)
+#define MX28EVK_MMC0_WRITE_PROTECT      MXS_GPIO_NR(2, 12)
+#define MX28EVK_MMC1_WRITE_PROTECT      MXS_GPIO_NR(0, 28)
+static const iomux_cfg_t m28evk_pads[] __initconst = {
+        /* duart */
+        MX28_PAD_AUART0_CTS__DUART_RX | MXS_PAD_CTRL,
+        MX28_PAD_AUART0_RTS__DUART_TX | MXS_PAD_CTRL,
+        /* auart0 */
+        MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL,
+        MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL,
+        /* auart3 */
+        MX28_PAD_AUART3_RX__AUART3_RX | MXS_PAD_CTRL,
+        MX28_PAD_AUART3_TX__AUART3_TX | MXS_PAD_CTRL,
+        MX28_PAD_AUART3_CTS__AUART3_CTS | MXS_PAD_CTRL,
+        MX28_PAD_AUART3_RTS__AUART3_RTS | MXS_PAD_CTRL,
+#define MXS_PAD_FEC     (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP)
+        /* fec0 */
+        MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC,
+        MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC,
+        MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC,
+        MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC,
+        MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC,
+        MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC,
+        MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC,
+        MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC,
+        MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC,
+        /* fec1 */
+        MX28_PAD_ENET0_CRS__ENET1_RX_EN | MXS_PAD_FEC,
+        MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MXS_PAD_FEC,
+        MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MXS_PAD_FEC,
+        MX28_PAD_ENET0_COL__ENET1_TX_EN | MXS_PAD_FEC,
+        MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MXS_PAD_FEC,
+        MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MXS_PAD_FEC,
+        /* flexcan0 */
+        MX28_PAD_GPMI_RDY2__CAN0_TX,
+        MX28_PAD_GPMI_RDY3__CAN0_RX,
+        /* flexcan1 */
+        MX28_PAD_GPMI_CE2N__CAN1_TX,
+        MX28_PAD_GPMI_CE3N__CAN1_RX,
+        /* I2C */
+        MX28_PAD_I2C0_SCL__I2C0_SCL,
+        MX28_PAD_I2C0_SDA__I2C0_SDA,
+        /* mxsfb (lcdif) */
+        MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_ENABLE__LCD_ENABLE | MXS_PAD_CTRL,
+        MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MXS_PAD_CTRL,
+        /* mmc0 */
+        MX28_PAD_SSP0_DATA0__SSP0_D0 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA1__SSP0_D1 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA2__SSP0_D2 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA3__SSP0_D3 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA4__SSP0_D4 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA5__SSP0_D5 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA6__SSP0_D6 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA7__SSP0_D7 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_CMD__SSP0_CMD |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+        MX28_PAD_SSP0_SCK__SSP0_SCK |
+                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+        /* mmc1 */
+        MX28_PAD_GPMI_D00__SSP1_D0 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_GPMI_D01__SSP1_D1 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_GPMI_D02__SSP1_D2 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_GPMI_D03__SSP1_D3 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_GPMI_D04__SSP1_D4 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_GPMI_D05__SSP1_D5 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_GPMI_D06__SSP1_D6 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_GPMI_D07__SSP1_D7 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_GPMI_RDY1__SSP1_CMD |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+        MX28_PAD_GPMI_WRN__SSP1_SCK |
+                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+        /* write protect */
+        MX28_PAD_GPMI_RESETN__GPIO_0_28 |
+                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+        /* slot power enable */
+        MX28_PAD_PWM4__GPIO_3_29 |
+                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+        /* led */
+        MX28_PAD_PWM0__GPIO_3_16 | MXS_PAD_CTRL,
+        MX28_PAD_PWM1__GPIO_3_17 | MXS_PAD_CTRL,
+        /* nand */
+        MX28_PAD_GPMI_D00__GPMI_D0 |
+                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
+        MX28_PAD_GPMI_D01__GPMI_D1 |
+                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
+        MX28_PAD_GPMI_D02__GPMI_D2 |
+                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
+        MX28_PAD_GPMI_D03__GPMI_D3 |
+                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
+        MX28_PAD_GPMI_D04__GPMI_D4 |
+                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
+        MX28_PAD_GPMI_D05__GPMI_D5 |
+                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
+        MX28_PAD_GPMI_D06__GPMI_D6 |
+                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
+        MX28_PAD_GPMI_D07__GPMI_D7 |
+                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
+        MX28_PAD_GPMI_CE0N__GPMI_CE0N |
+                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
+        MX28_PAD_GPMI_RDY0__GPMI_READY0 |
+                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
+        MX28_PAD_GPMI_RDN__GPMI_RDN |
+                (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
+        MX28_PAD_GPMI_WRN__GPMI_WRN |
+                (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
+        MX28_PAD_GPMI_ALE__GPMI_ALE |
+                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
+        MX28_PAD_GPMI_CLE__GPMI_CLE |
+                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
+        MX28_PAD_GPMI_RESETN__GPMI_RESETN |
+                (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
+        /* Backlight */
+        MX28_PAD_PWM3__GPIO_3_28 | MXS_PAD_CTRL,
+};
+/* led */
+static const struct gpio_led m28evk_leds[] __initconst = {
+        {
+                .name = "user-led1",
+                .default_trigger = "heartbeat",
+                .gpio = M28EVK_GPIO_USERLED1,
+        },
+        {
+                .name = "user-led2",
+                .default_trigger = "heartbeat",
+                .gpio = M28EVK_GPIO_USERLED2,
+        },
+};
+static const struct gpio_led_platform_data m28evk_led_data __initconst = {
+        .leds = m28evk_leds,
+        .num_leds = ARRAY_SIZE(m28evk_leds),
+};
+static struct fec_platform_data mx28_fec_pdata[] __initdata = {
+        {
+                /* fec0 */
+                .phy = PHY_INTERFACE_MODE_RMII,
+        }, {
+                /* fec1 */
+                .phy = PHY_INTERFACE_MODE_RMII,
+        },
+};
+static int __init m28evk_fec_get_mac(void)
+{
+        int i;
+        u32 val;
+        const u32 *ocotp = mxs_get_ocotp();
+        if (!ocotp) {
+                pr_err("%s: timeout when reading fec mac from OCOTP\n",
+                        __func__);
+                return -ETIMEDOUT;
+        }
+        /*
+         * OCOTP only stores the last 4 octets for each mac address,
+         * so hard-code DENX OUI (C0:E5:4E) here.
+         */
+        for (i = 0; i < 2; i++) {
+                val = ocotp[i * 4];
+                mx28_fec_pdata[i].mac[0] = 0xC0;
+                mx28_fec_pdata[i].mac[1] = 0xE5;
+                mx28_fec_pdata[i].mac[2] = 0x4E;
+                mx28_fec_pdata[i].mac[3] = (val >> 16) & 0xff;
+                mx28_fec_pdata[i].mac[4] = (val >> 8) & 0xff;
+                mx28_fec_pdata[i].mac[5] = (val >> 0) & 0xff;
+        }
+        return 0;
+}
+/* mxsfb (lcdif) */
+static struct fb_videomode m28evk_video_modes[] = {
+        {
+                .name           = "Ampire AM-800480R2TMQW-T01H",
+                .refresh        = 60,
+                .xres           = 800,
+                .yres           = 480,
+                .pixclock       = 30066, /* picosecond (33.26 MHz) */
+                .left_margin    = 0,
+                .right_margin   = 256,
+                .upper_margin   = 0,
+                .lower_margin   = 45,
+                .hsync_len      = 1,
+                .vsync_len      = 1,
+                .sync           = FB_SYNC_DATA_ENABLE_HIGH_ACT,
+        },
+};
+static const struct mxsfb_platform_data m28evk_mxsfb_pdata __initconst = {
+        .mode_list      = m28evk_video_modes,
+        .mode_count     = ARRAY_SIZE(m28evk_video_modes),
+        .default_bpp    = 16,
+        .ld_intf_width  = STMLCDIF_18BIT,
+};
+static struct at24_platform_data m28evk_eeprom = {
+        .byte_len = 16384,
+        .page_size = 32,
+        .flags = AT24_FLAG_ADDR16,
+};
+static struct i2c_board_info m28_stk5v3_i2c_boardinfo[] __initdata = {
+        {
+                I2C_BOARD_INFO("at24", 0x51),   /* E0=1, E1=0, E2=0 */
+                .platform_data = &m28evk_eeprom,
+        },
+};
+static struct mxs_mmc_platform_data m28evk_mmc_pdata[] __initdata = {
+        {
+                /* mmc0 */
+                .wp_gpio = MX28EVK_MMC0_WRITE_PROTECT,
+                .flags = SLOTF_8_BIT_CAPABLE,
+        }, {
+                /* mmc1 */
+                .wp_gpio = MX28EVK_MMC1_WRITE_PROTECT,
+                .flags = SLOTF_8_BIT_CAPABLE,
+        },
+};
+static void __init m28evk_init(void)
+{
+        mxs_iomux_setup_multiple_pads(m28evk_pads, ARRAY_SIZE(m28evk_pads));
+        mx28_add_duart();
+        mx28_add_auart0();
+        mx28_add_auart3();
+        if (!m28evk_fec_get_mac()) {
+                mx28_add_fec(0, &mx28_fec_pdata[0]);
+                mx28_add_fec(1, &mx28_fec_pdata[1]);
+        }
+        mx28_add_flexcan(0, NULL);
+        mx28_add_flexcan(1, NULL);
+        mx28_add_mxsfb(&m28evk_mxsfb_pdata);
+        mx28_add_mxs_mmc(0, &m28evk_mmc_pdata[0]);
+        mx28_add_mxs_mmc(1, &m28evk_mmc_pdata[1]);
+        gpio_led_register_device(0, &m28evk_led_data);
+        /* I2C */
+        mx28_add_mxs_i2c(0);
+        i2c_register_board_info(0, m28_stk5v3_i2c_boardinfo,
+                        ARRAY_SIZE(m28_stk5v3_i2c_boardinfo));
+}
+static void __init m28evk_timer_init(void)
+{
+        mx28_clocks_init();
+}
+static struct sys_timer m28evk_timer = {
+        .init   = m28evk_timer_init,
+};
+MACHINE_START(M28EVK, "DENX M28 EVK")
+        .map_io         = mx28_map_io,
+        .init_irq       = mx28_init_irq,
+        .init_machine   = m28evk_init,
+        .timer          = &m28evk_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c
index 3c2de33803ab..c325fbe4e4c6 100644
--- a/arch/arm/mach-mxs/mach-mx23evk.c
+++ b/arch/arm/mach-mxs/mach-mx23evk.c
@@ -15,7 +15,6 @@
 #include <linux/delay.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
-#include <linux/irq.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -167,6 +166,7 @@ static void __init mx23evk_init(void)
                gpio_set_value(MX23EVK_BL_ENABLE, 1);
        mx23_add_mxsfb(&mx23evk_mxsfb_pdata);
+        mx23_add_rtc_stmp3xxx();
 }
 static void __init mx23evk_timer_init(void)
@@ -182,6 +182,6 @@ MACHINE_START(MX23EVK, "Freescale MX23 EVK")
        /* Maintainer: Freescale Semiconductor, Inc. */
        .map_io         = mx23_map_io,
        .init_irq       = mx23_init_irq,
-        .init_machine   = mx23evk_init,
        .timer          = &mx23evk_timer,
+        .init_machine   = mx23evk_init,
 MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
index eaaf6ff28990..ac2316d53d3c 100644
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ b/arch/arm/mach-mxs/mach-mx28evk.c
@@ -16,8 +16,10 @@
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
-#include <linux/irq.h>
 #include <linux/clk.h>
+#include <linux/i2c.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -183,6 +185,24 @@ static const iomux_cfg_t mx28evk_pads[] __initconst = {
        /* led */
        MX28_PAD_AUART1_TX__GPIO_3_5 | MXS_PAD_CTRL,
+        /* I2C */
+        MX28_PAD_I2C0_SCL__I2C0_SCL |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_I2C0_SDA__I2C0_SDA |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        /* saif0 & saif1 */
+        MX28_PAD_SAIF0_MCLK__SAIF0_MCLK |
+                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK |
+                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK |
+                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 |
+                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 |
+                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
 };
 /* led */
@@ -352,6 +372,55 @@ static struct mxs_mmc_platform_data mx28evk_mmc_pdata[] __initdata = {
        },
 };
+static struct i2c_board_info mxs_i2c0_board_info[] __initdata = {
+        {
+                I2C_BOARD_INFO("sgtl5000", 0x0a),
+        },
+};
+#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
+static struct regulator_consumer_supply mx28evk_audio_consumer_supplies[] = {
+        REGULATOR_SUPPLY("VDDA", "0-000a"),
+        REGULATOR_SUPPLY("VDDIO", "0-000a"),
+};
+static struct regulator_init_data mx28evk_vdd_reg_init_data = {
+        .constraints    = {
+                .name   = "3V3",
+                .always_on = 1,
+        },
+        .consumer_supplies = mx28evk_audio_consumer_supplies,
+        .num_consumer_supplies = ARRAY_SIZE(mx28evk_audio_consumer_supplies),
+};
+static struct fixed_voltage_config mx28evk_vdd_pdata = {
+        .supply_name    = "board-3V3",
+        .microvolts     = 3300000,
+        .gpio           = -EINVAL,
+        .enabled_at_boot = 1,
+        .init_data      = &mx28evk_vdd_reg_init_data,
+};
+static struct platform_device mx28evk_voltage_regulator = {
+        .name           = "reg-fixed-voltage",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &mx28evk_vdd_pdata,
+        },
+};
+static void __init mx28evk_add_regulators(void)
+{
+        platform_device_register(&mx28evk_voltage_regulator);
+}
+#else
+static void __init mx28evk_add_regulators(void) {}
+#endif
+static struct gpio mx28evk_lcd_gpios[] = {
+        { MX28EVK_LCD_ENABLE, GPIOF_OUT_INIT_HIGH, "lcd-enable" },
+        { MX28EVK_BL_ENABLE, GPIOF_OUT_INIT_HIGH, "bl-enable" },
+};
 static void __init mx28evk_init(void)
 {
        int ret;
@@ -378,19 +447,24 @@ static void __init mx28evk_init(void)
                mx28_add_flexcan(1, &mx28evk_flexcan_pdata[1]);
        }
-        ret = gpio_request_one(MX28EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable");
+        ret = gpio_request_array(mx28evk_lcd_gpios,
+                                 ARRAY_SIZE(mx28evk_lcd_gpios));
        if (ret)
-                pr_warn("failed to request gpio lcd-enable: %d\n", ret);
+                pr_warn("failed to request gpio pins for lcd: %d\n", ret);
        else
-                gpio_set_value(MX28EVK_LCD_ENABLE, 1);
+                mx28_add_mxsfb(&mx28evk_mxsfb_pdata);
-        ret = gpio_request_one(MX28EVK_BL_ENABLE, GPIOF_DIR_OUT, "bl-enable");
+        mx28_add_saif(0);
-        if (ret)
+        mx28_add_saif(1);
-                pr_warn("failed to request gpio bl-enable: %d\n", ret);
-        else
+        mx28_add_mxs_i2c(0);
-                gpio_set_value(MX28EVK_BL_ENABLE, 1);
+        i2c_register_board_info(0, mxs_i2c0_board_info,
+                                ARRAY_SIZE(mxs_i2c0_board_info));
-        mx28_add_mxsfb(&mx28evk_mxsfb_pdata);
+        mx28evk_add_regulators();
+        mxs_add_platform_device("mxs-sgtl5000", 0, NULL, 0,
+                        NULL, 0);
        /* power on mmc slot by writing 0 to the gpio */
        ret = gpio_request_one(MX28EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW,
@@ -403,7 +477,11 @@ static void __init mx28evk_init(void)
                               "mmc1-slot-power");
        if (ret)
                pr_warn("failed to request gpio mmc1-slot-power: %d\n", ret);
+        else
+                mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]);
        mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]);
+        mx28_add_rtc_stmp3xxx();
        gpio_led_register_device(0, &mx28evk_led_data);
 }
@@ -421,6 +499,6 @@ MACHINE_START(MX28EVK, "Freescale MX28 EVK")
        /* Maintainer: Freescale Semiconductor, Inc. */
        .map_io         = mx28_map_io,
        .init_irq       = mx28_init_irq,
-        .init_machine   = mx28evk_init,
        .timer          = &mx28evk_timer,
+        .init_machine   = mx28evk_init,
 MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-stmp378x_devb.c b/arch/arm/mach-mxs/mach-stmp378x_devb.c
index 7f38d82b69af..177e53123a02 100644
--- a/arch/arm/mach-mxs/mach-stmp378x_devb.c
+++ b/arch/arm/mach-mxs/mach-stmp378x_devb.c
@@ -19,7 +19,6 @@
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
-#include <linux/irq.h>
 #include <linux/spi/spi.h>
 #include <asm/mach-types.h>
@@ -91,6 +90,7 @@ static void __init stmp378x_dvb_init(void)
        mx23_add_duart();
        mx23_add_auart0();
+        mx23_add_rtc_stmp3xxx();
        /* power on mmc slot */
        ret = gpio_request_one(STMP378X_DEVB_MMC0_SLOT_POWER,
diff --git a/arch/arm/mach-mxs/mach-tx28.c b/arch/arm/mach-mxs/mach-tx28.c
index 515a423f82cd..9a1f0e7a338e 100644
--- a/arch/arm/mach-mxs/mach-tx28.c
+++ b/arch/arm/mach-mxs/mach-tx28.c
@@ -161,6 +161,7 @@ static void __init tx28_stk5v3_init(void)
        i2c_register_board_info(0, tx28_stk5v3_i2c_boardinfo,
                        ARRAY_SIZE(tx28_stk5v3_i2c_boardinfo));
        mx28_add_mxs_mmc(0, &tx28_mmc0_pdata);
+        mx28_add_rtc_stmp3xxx();
 }
 static void __init tx28_timer_init(void)
@@ -175,6 +176,6 @@ static struct sys_timer tx28_timer = {
 MACHINE_START(TX28, "Ka-Ro electronics TX28 module")
        .map_io = mx28_map_io,
        .init_irq = mx28_init_irq,
-        .init_machine = tx28_stk5v3_init,
        .timer = &tx28_timer,
+        .init_machine = tx28_stk5v3_init,
 MACHINE_END
diff --git a/arch/arm/mach-mxs/mm-mx28.c b/arch/arm/mach-mxs/mm-mx28.c
deleted file mode 100644
index b6e18ddb92c0..000000000000
--- a/arch/arm/mach-mxs/mm-mx28.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License.  You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- *
- * Create static mapping between physical to virtual memory.
- */
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <asm/mach/map.h>
-#include <mach/mx28.h>
-#include <mach/common.h>
-#include <mach/iomux.h>
-/*
- * Define the MX28 memory map.
- */
-static struct map_desc mx28_io_desc[] __initdata = {
-        mxs_map_entry(MX28, OCRAM, MT_DEVICE),
-        mxs_map_entry(MX28, IO, MT_DEVICE),
-};
-/*
- * This function initializes the memory map. It is called during the
- * system startup to create static physical to virtual memory mappings
- * for the IO modules.
- */
-void __init mx28_map_io(void)
-{
-        iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc));
-}
-void __init mx28_init_irq(void)
-{
-        icoll_init_irq();
-}
diff --git a/arch/arm/mach-mxs/mm-mx23.c b/arch/arm/mach-mxs/mm.c
index 1b2345ac1a87..50af5ceebf6d 100644
--- a/arch/arm/mach-mxs/mm-mx23.c
+++ b/arch/arm/mach-mxs/mm.c
@@ -17,6 +17,7 @@
 #include <asm/mach/map.h>
 #include <mach/mx23.h>
+#include <mach/mx28.h>
 #include <mach/common.h>
 #include <mach/iomux.h>
@@ -29,6 +30,14 @@ static struct map_desc mx23_io_desc[] __initdata = {
 };
 /*
+ * Define the MX28 memory map.
+ */
+static struct map_desc mx28_io_desc[] __initdata = {
+        mxs_map_entry(MX28, OCRAM, MT_DEVICE),
+        mxs_map_entry(MX28, IO, MT_DEVICE),
+};
+/*
 * This function initializes the memory map. It is called during the
 * system startup to create static physical to virtual memory mappings
 * for the IO modules.
@@ -42,3 +51,13 @@ void __init mx23_init_irq(void)
 {
        icoll_init_irq();
 }
+void __init mx28_map_io(void)
+{
+        iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc));
+}
+void __init mx28_init_irq(void)
+{
+        icoll_init_irq();
+}
diff --git a/arch/arm/mach-nuc93x/Kconfig b/arch/arm/mach-nuc93x/Kconfig
deleted file mode 100644
index 2bc40a280fad..000000000000
--- a/arch/arm/mach-nuc93x/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-if ARCH_NUC93X
-config CPU_NUC932
-        bool
-        help
-          Support for NUC932 of Nuvoton NUC93X CPUs.
-menu "NUC932 Machines"
-config MACH_NUC932EVB
-        bool "Nuvoton NUC932 Evaluation Board"
-        default y
-        select CPU_NUC932
-        help
-           Say Y here if you are using the Nuvoton NUC932EVB
-endmenu
-endif
diff --git a/arch/arm/mach-nuc93x/Makefile b/arch/arm/mach-nuc93x/Makefile
deleted file mode 100644
index 440e2dec6c8a..000000000000
--- a/arch/arm/mach-nuc93x/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-# Object file lists.
-obj-y                           := irq.o time.o dev.o cpu.o clock.o
-# NUC932 CPU support files
-obj-$(CONFIG_CPU_NUC932)        += nuc932.o
-# machine support
-obj-$(CONFIG_MACH_NUC932EVB)    += mach-nuc932evb.o
diff --git a/arch/arm/mach-nuc93x/Makefile.boot b/arch/arm/mach-nuc93x/Makefile.boot
deleted file mode 100644
index 6c3d421c2d11..000000000000
--- a/arch/arm/mach-nuc93x/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
-zreladdr-y      += 0x00008000
-params_phys-y   := 0x00000100
diff --git a/arch/arm/mach-nuc93x/clock.c b/arch/arm/mach-nuc93x/clock.c
deleted file mode 100644
index 0521efbc48c9..000000000000
--- a/arch/arm/mach-nuc93x/clock.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * linux/arch/arm/mach-nuc93x/clock.c
- *
- * Copyright (c) 2008 Nuvoton technology corporation
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License.
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/string.h>
-#include <linux/clk.h>
-#include <linux/spinlock.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include "clock.h"
-static DEFINE_SPINLOCK(clocks_lock);
-int clk_enable(struct clk *clk)
-{
-        unsigned long flags;
-        spin_lock_irqsave(&clocks_lock, flags);
-        if (clk->enabled++ == 0)
-                (clk->enable)(clk, 1);
-        spin_unlock_irqrestore(&clocks_lock, flags);
-        return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-void clk_disable(struct clk *clk)
-{
-        unsigned long flags;
-        WARN_ON(clk->enabled == 0);
-        spin_lock_irqsave(&clocks_lock, flags);
-        if (--clk->enabled == 0)
-                (clk->enable)(clk, 0);
-        spin_unlock_irqrestore(&clocks_lock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-unsigned long clk_get_rate(struct clk *clk)
-{
-        return 27000000;
-}
-EXPORT_SYMBOL(clk_get_rate);
-void nuc93x_clk_enable(struct clk *clk, int enable)
-{
-        unsigned int clocks = clk->cken;
-        unsigned long clken;
-        clken = __raw_readl(NUC93X_VA_CLKPWR);
-        if (enable)
-                clken |= clocks;
-        else
-                clken &= ~clocks;
-        __raw_writel(clken, NUC93X_VA_CLKPWR);
-}
-void clks_register(struct clk_lookup *clks, size_t num)
-{
-        int i;
-        for (i = 0; i < num; i++)
-                clkdev_add(&clks[i]);
-}
diff --git a/arch/arm/mach-nuc93x/clock.h b/arch/arm/mach-nuc93x/clock.h
deleted file mode 100644
index 4de1f1da9dc5..000000000000
--- a/arch/arm/mach-nuc93x/clock.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * linux/arch/arm/mach-nuc93x/clock.h
- *
- * Copyright (c) 2008 Nuvoton technology corporation
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License.
- */
-#include <linux/clkdev.h>
-void nuc93x_clk_enable(struct clk *clk, int enable);
-void clks_register(struct clk_lookup *clks, size_t num);
-struct clk {
-        unsigned long           cken;
-        unsigned int            enabled;
-        void                    (*enable)(struct clk *, int enable);
-};
-#define DEFINE_CLK(_name, _ctrlbit)                     \
-struct clk clk_##_name = {                              \
-                .enable = nuc93x_clk_enable,            \
-                .cken   = (1 << _ctrlbit),              \
-        }
-#define DEF_CLKLOOK(_clk, _devname, _conname)           \
-        {                                               \
-                .clk            = _clk,                 \
-                .dev_id         = _devname,             \
-                .con_id         = _conname,             \
-        }
diff --git a/arch/arm/mach-nuc93x/cpu.c b/arch/arm/mach-nuc93x/cpu.c
deleted file mode 100644
index f6ff5d87354c..000000000000
--- a/arch/arm/mach-nuc93x/cpu.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * linux/arch/arm/mach-nuc93x/cpu.c
- *
- * Copyright (c) 2009 Nuvoton corporation.
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * NUC93x series cpu common support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation;version 2 of the License.
- *
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/serial_8250.h>
-#include <linux/delay.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <asm/irq.h>
-#include <mach/hardware.h>
-#include <mach/regs-serial.h>
-#include <mach/regs-clock.h>
-#include <mach/regs-ebi.h>
-#include "cpu.h"
-#include "clock.h"
-/* Initial IO mappings */
-static struct map_desc nuc93x_iodesc[] __initdata = {
-        IODESC_ENT(IRQ),
-        IODESC_ENT(GCR),
-        IODESC_ENT(UART),
-        IODESC_ENT(TIMER),
-        IODESC_ENT(EBI),
-};
-/* Initial nuc932 clock declarations. */
-static DEFINE_CLK(audio, 2);
-static DEFINE_CLK(sd, 3);
-static DEFINE_CLK(jpg, 4);
-static DEFINE_CLK(video, 5);
-static DEFINE_CLK(vpost, 6);
-static DEFINE_CLK(2d, 7);
-static DEFINE_CLK(gpu, 8);
-static DEFINE_CLK(gdma, 9);
-static DEFINE_CLK(adc, 10);
-static DEFINE_CLK(uart, 11);
-static DEFINE_CLK(spi, 12);
-static DEFINE_CLK(pwm, 13);
-static DEFINE_CLK(timer, 14);
-static DEFINE_CLK(wdt, 15);
-static DEFINE_CLK(ac97, 16);
-static DEFINE_CLK(i2s, 16);
-static DEFINE_CLK(usbck, 17);
-static DEFINE_CLK(usb48, 18);
-static DEFINE_CLK(usbh, 19);
-static DEFINE_CLK(i2c, 20);
-static DEFINE_CLK(ext, 0);
-static struct clk_lookup nuc932_clkregs[] = {
-       DEF_CLKLOOK(&clk_audio, "nuc932-audio", NULL),
-       DEF_CLKLOOK(&clk_sd, "nuc932-sd", NULL),
-       DEF_CLKLOOK(&clk_jpg, "nuc932-jpg", "NULL"),
-       DEF_CLKLOOK(&clk_video, "nuc932-video", "NULL"),
-       DEF_CLKLOOK(&clk_vpost, "nuc932-vpost", NULL),
-       DEF_CLKLOOK(&clk_2d, "nuc932-2d", NULL),
-       DEF_CLKLOOK(&clk_gpu, "nuc932-gpu", NULL),
-       DEF_CLKLOOK(&clk_gdma, "nuc932-gdma", "NULL"),
-       DEF_CLKLOOK(&clk_adc, "nuc932-adc", NULL),
-       DEF_CLKLOOK(&clk_uart, NULL, "uart"),
-       DEF_CLKLOOK(&clk_spi, "nuc932-spi", NULL),
-       DEF_CLKLOOK(&clk_pwm, "nuc932-pwm", NULL),
-       DEF_CLKLOOK(&clk_timer, NULL, "timer"),
-       DEF_CLKLOOK(&clk_wdt, "nuc932-wdt", NULL),
-       DEF_CLKLOOK(&clk_ac97, "nuc932-ac97", NULL),
-       DEF_CLKLOOK(&clk_i2s, "nuc932-i2s", NULL),
-       DEF_CLKLOOK(&clk_usbck, "nuc932-usbck", NULL),
-       DEF_CLKLOOK(&clk_usb48, "nuc932-usb48", NULL),
-       DEF_CLKLOOK(&clk_usbh, "nuc932-usbh", NULL),
-       DEF_CLKLOOK(&clk_i2c, "nuc932-i2c", NULL),
-       DEF_CLKLOOK(&clk_ext, NULL, "ext"),
-};
-/* Initial serial platform data */
-struct plat_serial8250_port nuc93x_uart_data[] = {
-        NUC93X_8250PORT(UART0),
-        {},
-};
-struct platform_device nuc93x_serial_device = {
-        .name                   = "serial8250",
-        .id                     = PLAT8250_DEV_PLATFORM,
-        .dev                    = {
-                .platform_data  = nuc93x_uart_data,
-        },
-};
-/*Init NUC93x evb io*/
-void __init nuc93x_map_io(struct map_desc *mach_desc, int mach_size)
-{
-        unsigned long idcode = 0x0;
-        iotable_init(mach_desc, mach_size);
-        iotable_init(nuc93x_iodesc, ARRAY_SIZE(nuc93x_iodesc));
-        idcode = __raw_readl(NUC93XPDID);
-        if (idcode == NUC932_CPUID)
-                printk(KERN_INFO "CPU type 0x%08lx is NUC910\n", idcode);
-        else
-                printk(KERN_ERR "CPU type detect error!\n");
-}
-/*Init NUC93x clock*/
-void __init nuc93x_init_clocks(void)
-{
-        clks_register(nuc932_clkregs, ARRAY_SIZE(nuc932_clkregs));
-}
diff --git a/arch/arm/mach-nuc93x/cpu.h b/arch/arm/mach-nuc93x/cpu.h
deleted file mode 100644
index 9def28197bc9..000000000000
--- a/arch/arm/mach-nuc93x/cpu.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * arch/arm/mach-nuc93x/cpu.h
- *
- * Copyright (c) 2008 Nuvoton technology corporation
- * All rights reserved.
- *
- * Header file for NUC93X CPU support
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-#define IODESC_ENT(y)                                   \
-{                                                       \
-        .virtual = (unsigned long)NUC93X_VA_##y,        \
-        .pfn     = __phys_to_pfn(NUC93X_PA_##y),        \
-        .length  = NUC93X_SZ_##y,                       \
-        .type    = MT_DEVICE,                           \
-}
-#define NUC93X_8250PORT(name)                                   \
-{                                                               \
-        .membase        = name##_BA,                            \
-        .mapbase        = name##_PA,                            \
-        .irq            = IRQ_##name,                           \
-        .uartclk        = 57139200,                             \
-        .regshift       = 2,                                    \
-        .iotype         = UPIO_MEM,                             \
-        .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,    \
-}
-/*Cpu identifier register*/
-#define NUC93XPDID      NUC93X_VA_GCR
-#define NUC932_CPUID    0x29550091
-/* extern file from cpu.c */
-extern void nuc93x_clock_source(struct device *dev, unsigned char *src);
-extern void nuc93x_init_clocks(void);
-extern void nuc93x_map_io(struct map_desc *mach_desc, int mach_size);
-extern void nuc93x_board_init(struct platform_device **device, int size);
-extern struct platform_device nuc93x_serial_device;
diff --git a/arch/arm/mach-nuc93x/dev.c b/arch/arm/mach-nuc93x/dev.c
deleted file mode 100644
index a962ae9578d6..000000000000
--- a/arch/arm/mach-nuc93x/dev.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * linux/arch/arm/mach-nuc93x/dev.c
- *
- * Copyright (C) 2009 Nuvoton corporation.
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation;version 2 of the License.
- *
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <asm/mach-types.h>
-#include "cpu.h"
-/*Here should be your evb resourse,such as LCD*/
-static struct platform_device *nuc93x_public_dev[] __initdata = {
-        &nuc93x_serial_device,
-};
-/* Provide adding specific CPU platform devices API */
-void __init nuc93x_board_init(struct platform_device **device, int size)
-{
-        platform_add_devices(device, size);
-        platform_add_devices(nuc93x_public_dev, ARRAY_SIZE(nuc93x_public_dev));
-}
diff --git a/arch/arm/mach-nuc93x/include/mach/entry-macro.S b/arch/arm/mach-nuc93x/include/mach/entry-macro.S
deleted file mode 100644
index 1352cbda3797..000000000000
--- a/arch/arm/mach-nuc93x/include/mach/entry-macro.S
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * arch/arm/mach-nuc93x/include/mach/entry-macro.S
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
- */
-#include <mach/hardware.h>
-#include <mach/regs-irq.h>
-        .macro  get_irqnr_preamble, base, tmp
-        .endm
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                mov     \base, #AIC_BA
-                ldr     \irqnr, [ \base, #AIC_IPER]
-                ldr     \irqnr, [ \base, #AIC_ISNR]
-                cmp     \irqnr, #0
-        .endm
-        /* currently don't need an disable_fiq macro */
-        .macro  disable_fiq
-        .endm
diff --git a/arch/arm/mach-nuc93x/include/mach/hardware.h b/arch/arm/mach-nuc93x/include/mach/hardware.h
deleted file mode 100644
index fb5c6fcb142e..000000000000
--- a/arch/arm/mach-nuc93x/include/mach/hardware.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * arch/arm/mach-nuc93x/include/mach/hardware.h
- *
- * Copyright (c) 2008 Nuvoton technology corporation
- * All rights reserved.
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-#include <asm/sizes.h>
-#include <mach/map.h>
-#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/io.h b/arch/arm/mach-nuc93x/include/mach/io.h
deleted file mode 100644
index 72e5051c7534..000000000000
--- a/arch/arm/mach-nuc93x/include/mach/io.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * arch/arm/mach-nuc93x/include/mach/io.h
- *
- * Copyright (c) 2008 Nuvoton technology corporation
- * All rights reserved.
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-#define IO_SPACE_LIMIT  0xffffffff
-/*
- * 1:1 mapping for ioremapped regions.
- */
-#define __mem_pci(a)    (a)
-#define __io(a)         __typesafe_io(a)
-#endif
diff --git a/arch/arm/mach-nuc93x/include/mach/irqs.h b/arch/arm/mach-nuc93x/include/mach/irqs.h
deleted file mode 100644
index 7c4aa71edb44..000000000000
--- a/arch/arm/mach-nuc93x/include/mach/irqs.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * arch/arm/mach-nuc93x/include/mach/irqs.h
- *
- * Copyright (c) 2008 Nuvoton technology corporation.
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation;version 2 of the License.
- *
- */
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-#define NUC93X_IRQ(x)   (x)
-/* Main cpu interrupts */
-#define IRQ_WDT         NUC93X_IRQ(1)
-#define IRQ_IRQ0        NUC93X_IRQ(2)
-#define IRQ_IRQ1        NUC93X_IRQ(3)
-#define IRQ_IRQ2        NUC93X_IRQ(4)
-#define IRQ_IRQ3        NUC93X_IRQ(5)
-#define IRQ_USBH        NUC93X_IRQ(6)
-#define IRQ_APU         NUC93X_IRQ(7)
-#define IRQ_VPOST       NUC93X_IRQ(8)
-#define IRQ_ADC         NUC93X_IRQ(9)
-#define IRQ_UART0       NUC93X_IRQ(10)
-#define IRQ_TIMER0      NUC93X_IRQ(11)
-#define IRQ_GPU0        NUC93X_IRQ(12)
-#define IRQ_GPU1        NUC93X_IRQ(13)
-#define IRQ_GPU2        NUC93X_IRQ(14)
-#define IRQ_GPU3        NUC93X_IRQ(15)
-#define IRQ_GPU4        NUC93X_IRQ(16)
-#define IRQ_VIN         NUC93X_IRQ(17)
-#define IRQ_USBD        NUC93X_IRQ(18)
-#define IRQ_VRAMLD      NUC93X_IRQ(19)
-#define IRQ_GDMA0       NUC93X_IRQ(20)
-#define IRQ_GDMA1       NUC93X_IRQ(21)
-#define IRQ_SDIO        NUC93X_IRQ(22)
-#define IRQ_FMI         NUC93X_IRQ(22)
-#define IRQ_JPEG        NUC93X_IRQ(23)
-#define IRQ_SPI0        NUC93X_IRQ(24)
-#define IRQ_SPI1        NUC93X_IRQ(25)
-#define IRQ_RTC         NUC93X_IRQ(26)
-#define IRQ_PWM0        NUC93X_IRQ(27)
-#define IRQ_PWM1        NUC93X_IRQ(28)
-#define IRQ_PWM2        NUC93X_IRQ(29)
-#define IRQ_PWM3        NUC93X_IRQ(30)
-#define IRQ_I2SAC97     NUC93X_IRQ(31)
-#define IRQ_CAP0        IRQ_PWM0
-#define IRQ_CAP1        IRQ_PWM1
-#define IRQ_CAP2        IRQ_PWM2
-#define IRQ_CAP3        IRQ_PWM3
-#define NR_IRQS         (IRQ_I2SAC97 + 1)
-#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/map.h b/arch/arm/mach-nuc93x/include/mach/map.h
deleted file mode 100644
index fd0b5e89f0e7..000000000000
--- a/arch/arm/mach-nuc93x/include/mach/map.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * arch/arm/mach-nuc93x/include/mach/map.h
- *
- * Copyright (c) 2008 Nuvoton technology corporation.
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation;version 2 of the License.
- *
- */
-#ifndef __ASM_ARCH_MAP_H
-#define __ASM_ARCH_MAP_H
-#define MAP_OFFSET      (0xfff00000)
-#define CLK_OFFSET      (0x10)
-#ifndef __ASSEMBLY__
-#define NUC93X_ADDR(x)  ((void __iomem *)(0xF0000000 + ((x)&(~MAP_OFFSET))))
-#else
-#define NUC93X_ADDR(x)  (0xF0000000 + ((x)&(~MAP_OFFSET)))
-#endif
- /*
-  * nuc932 hardware register definition
-  */
-#define NUC93X_PA_IRQ           (0xFFF83000)
-#define NUC93X_PA_GCR           (0xFFF00000)
-#define NUC93X_PA_EBI           (0xFFF01000)
-#define NUC93X_PA_UART          (0xFFF80000)
-#define NUC93X_PA_TIMER         (0xFFF81000)
-#define NUC93X_PA_GPIO          (0xFFF84000)
-#define NUC93X_PA_GDMA          (0xFFF03000)
-#define NUC93X_PA_USBHOST       (0xFFF0d000)
-#define NUC93X_PA_I2C           (0xFFF89000)
-#define NUC93X_PA_LCD           (0xFFF06000)
-#define NUC93X_PA_GE            (0xFFF05000)
-#define NUC93X_PA_ADC           (0xFFF85000)
-#define NUC93X_PA_RTC           (0xFFF87000)
-#define NUC93X_PA_PWM           (0xFFF82000)
-#define NUC93X_PA_ACTL          (0xFFF0a000)
-#define NUC93X_PA_USBDEV        (0xFFF0C000)
-#define NUC93X_PA_JEPEG         (0xFFF0e000)
-#define NUC93X_PA_CACHE_T       (0xFFF60000)
-#define NUC93X_PA_VRAM          (0xFFF0b000)
-#define NUC93X_PA_DMAC          (0xFFF09000)
-#define NUC93X_PA_I2SM          (0xFFF08000)
-#define NUC93X_PA_CACHE         (0xFFF02000)
-#define NUC93X_PA_GPU           (0xFFF04000)
-#define NUC93X_PA_VIDEOIN       (0xFFF07000)
-#define NUC93X_PA_SPI0          (0xFFF86000)
-#define NUC93X_PA_SPI1          (0xFFF88000)
- /*
-  * nuc932 virtual address mapping.
-  * interrupt controller is the first thing we put in, to make
-  * the assembly code for the irq detection easier
-  */
-#define NUC93X_VA_IRQ           NUC93X_ADDR(0x00000000)
-#define NUC93X_SZ_IRQ           SZ_4K
-#define NUC93X_VA_GCR           NUC93X_ADDR(NUC93X_PA_IRQ)
-#define NUC93X_VA_CLKPWR        (NUC93X_VA_GCR+CLK_OFFSET)
-#define NUC93X_SZ_GCR           SZ_4K
-/* EBI management */
-#define NUC93X_VA_EBI           NUC93X_ADDR(NUC93X_PA_EBI)
-#define NUC93X_SZ_EBI           SZ_4K
-/* UARTs */
-#define NUC93X_VA_UART          NUC93X_ADDR(NUC93X_PA_UART)
-#define NUC93X_SZ_UART          SZ_4K
-/* Timers */
-#define NUC93X_VA_TIMER NUC93X_ADDR(NUC93X_PA_TIMER)
-#define NUC93X_SZ_TIMER SZ_4K
-/* GPIO ports */
-#define NUC93X_VA_GPIO          NUC93X_ADDR(NUC93X_PA_GPIO)
-#define NUC93X_SZ_GPIO          SZ_4K
-/* GDMA control */
-#define NUC93X_VA_GDMA          NUC93X_ADDR(NUC93X_PA_GDMA)
-#define NUC93X_SZ_GDMA          SZ_4K
-/* I2C hardware controller */
-#define NUC93X_VA_I2C           NUC93X_ADDR(NUC93X_PA_I2C)
-#define NUC93X_SZ_I2C           SZ_4K
-/* LCD controller*/
-#define NUC93X_VA_LCD           NUC93X_ADDR(NUC93X_PA_LCD)
-#define NUC93X_SZ_LCD           SZ_4K
-/* 2D controller*/
-#define NUC93X_VA_GE            NUC93X_ADDR(NUC93X_PA_GE)
-#define NUC93X_SZ_GE            SZ_4K
-/* ADC */
-#define NUC93X_VA_ADC           NUC93X_ADDR(NUC93X_PA_ADC)
-#define NUC93X_SZ_ADC           SZ_4K
-/* RTC */
-#define NUC93X_VA_RTC           NUC93X_ADDR(NUC93X_PA_RTC)
-#define NUC93X_SZ_RTC           SZ_4K
-/* Pulse Width Modulation(PWM) Registers */
-#define NUC93X_VA_PWM           NUC93X_ADDR(NUC93X_PA_PWM)
-#define NUC93X_SZ_PWM           SZ_4K
-/* Audio Controller controller */
-#define NUC93X_VA_ACTL          NUC93X_ADDR(NUC93X_PA_ACTL)
-#define NUC93X_SZ_ACTL          SZ_4K
-/* USB Device port */
-#define NUC93X_VA_USBDEV        NUC93X_ADDR(NUC93X_PA_USBDEV)
-#define NUC93X_SZ_USBDEV        SZ_4K
-/* USB host controller*/
-#define NUC93X_VA_USBHOST       NUC93X_ADDR(NUC93X_PA_USBHOST)
-#define NUC93X_SZ_USBHOST       SZ_4K
-#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/regs-clock.h b/arch/arm/mach-nuc93x/include/mach/regs-clock.h
deleted file mode 100644
index 5cb2954fbec2..000000000000
--- a/arch/arm/mach-nuc93x/include/mach/regs-clock.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * arch/arm/mach-nuc93x/include/mach/regs-clock.h
- *
- * Copyright (c) 2008 Nuvoton technology corporation.
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation;version 2 of the License.
- *
- */
-#ifndef __ASM_ARCH_REGS_CLOCK_H
-#define __ASM_ARCH_REGS_CLOCK_H
-/* Clock Control Registers  */
-#define CLK_BA          NUC93X_VA_CLKPWR
-#define REG_CLKEN       (CLK_BA + 0x00)
-#define REG_CLKSEL      (CLK_BA + 0x04)
-#define REG_CLKDIV      (CLK_BA + 0x08)
-#define REG_PLLCON0     (CLK_BA + 0x0C)
-#define REG_PLLCON1     (CLK_BA + 0x10)
-#define REG_PMCON       (CLK_BA + 0x14)
-#define REG_IRQWAKECON  (CLK_BA + 0x18)
-#define REG_IRQWAKEFLAG (CLK_BA + 0x1C)
-#define REG_IPSRST      (CLK_BA + 0x20)
-#define REG_CLKEN1      (CLK_BA + 0x24)
-#define REG_CLKDIV1     (CLK_BA + 0x28)
-/* Define PLL freq setting */
-#define PLL_DISABLE             0x12B63
-#define PLL_66MHZ               0x2B63
-#define PLL_100MHZ              0x4F64
-#define PLL_120MHZ              0x4F63
-#define PLL_166MHZ              0x4124
-#define PLL_200MHZ              0x4F24
-/* Define AHB:CPUFREQ ratio */
-#define AHB_CPUCLK_1_1          0x00
-#define AHB_CPUCLK_1_2          0x01
-#define AHB_CPUCLK_1_4          0x02
-#define AHB_CPUCLK_1_8          0x03
-/* Define APB:AHB ratio */
-#define APB_AHB_1_2             0x01
-#define APB_AHB_1_4             0x02
-#define APB_AHB_1_8             0x03
-/* Define clock skew */
-#define DEFAULTSKEW             0x48
-#endif /*  __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/regs-ebi.h b/arch/arm/mach-nuc93x/include/mach/regs-ebi.h
deleted file mode 100644
index 3c72550e28e4..000000000000
--- a/arch/arm/mach-nuc93x/include/mach/regs-ebi.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * arch/arm/mach-nuc93x/include/mach/regs-ebi.h
- *
- * Copyright (c) 2009 Nuvoton technology corporation.
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation;version 2 of the License.
- *
- */
-#ifndef __ASM_ARCH_REGS_EBI_H
-#define __ASM_ARCH_REGS_EBI_H
-/* EBI Control Registers */
-#define EBI_BA          NUC93X_VA_EBI
-#define REG_EBICON      (EBI_BA + 0x00)
-#define REG_ROMCON      (EBI_BA + 0x04)
-#define REG_SDCONF0     (EBI_BA + 0x08)
-#define REG_SDCONF1     (EBI_BA + 0x0C)
-#define REG_SDTIME0     (EBI_BA + 0x10)
-#define REG_SDTIME1     (EBI_BA + 0x14)
-#define REG_EXT0CON     (EBI_BA + 0x18)
-#define REG_EXT1CON     (EBI_BA + 0x1C)
-#define REG_EXT2CON     (EBI_BA + 0x20)
-#define REG_EXT3CON     (EBI_BA + 0x24)
-#define REG_EXT4CON     (EBI_BA + 0x28)
-#define REG_CKSKEW      (EBI_BA + 0x2C)
-#endif /*  __ASM_ARCH_REGS_EBI_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/regs-irq.h b/arch/arm/mach-nuc93x/include/mach/regs-irq.h
deleted file mode 100644
index 23021592de51..000000000000
--- a/arch/arm/mach-nuc93x/include/mach/regs-irq.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * arch/arm/mach-nuc93x/include/mach/regs-irq.h
- *
- * Copyright (c) 2008 Nuvoton technology corporation
- * All rights reserved.
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#ifndef ___ASM_ARCH_REGS_IRQ_H
-#define ___ASM_ARCH_REGS_IRQ_H
-/* Advance Interrupt Controller (AIC) Registers */
-#define AIC_BA                  NUC93X_VA_IRQ
-#define REG_AIC_IRQSC           (AIC_BA+0x80)
-#define REG_AIC_GEN             (AIC_BA+0x84)
-#define REG_AIC_GASR            (AIC_BA+0x88)
-#define REG_AIC_GSCR            (AIC_BA+0x8C)
-#define REG_AIC_IRSR            (AIC_BA+0x100)
-#define REG_AIC_IASR            (AIC_BA+0x104)
-#define REG_AIC_ISR             (AIC_BA+0x108)
-#define REG_AIC_IPER            (AIC_BA+0x10C)
-#define REG_AIC_ISNR            (AIC_BA+0x110)
-#define REG_AIC_IMR             (AIC_BA+0x114)
-#define REG_AIC_OISR            (AIC_BA+0x118)
-#define REG_AIC_MECR            (AIC_BA+0x120)
-#define REG_AIC_MDCR            (AIC_BA+0x124)
-#define REG_AIC_SSCR            (AIC_BA+0x128)
-#define REG_AIC_SCCR            (AIC_BA+0x12C)
-#define REG_AIC_EOSCR           (AIC_BA+0x130)
-#define AIC_IPER                (0x10C)
-#define AIC_ISNR                (0x110)
-#endif /* ___ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/regs-serial.h b/arch/arm/mach-nuc93x/include/mach/regs-serial.h
deleted file mode 100644
index 767a047a8bc2..000000000000
--- a/arch/arm/mach-nuc93x/include/mach/regs-serial.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * arch/arm/mach-nuc93x/include/mach/regs-serial.h
- *
- * Copyright (c) 2008 Nuvoton technology corporation
- * All rights reserved.
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#ifndef __ASM_ARM_REGS_SERIAL_H
-#define __ASM_ARM_REGS_SERIAL_H
-#define UART0_BA        NUC93X_VA_UART
-#define UART1_BA        (NUC93X_VA_UART+0x100)
-#define UART0_PA        NUC93X_PA_UART
-#define UART1_PA        (NUC93X_PA_UART+0x100)
-#ifndef __ASSEMBLY__
-struct nuc93x_uart_clksrc {
-        const char      *name;
-        unsigned int    divisor;
-        unsigned int    min_baud;
-        unsigned int    max_baud;
-};
-struct nuc93x_uartcfg {
-        unsigned char   hwport;
-        unsigned char   unused;
-        unsigned short  flags;
-        unsigned long   uart_flags;
-        unsigned long   ucon;
-        unsigned long   ulcon;
-        unsigned long   ufcon;
-        struct nuc93x_uart_clksrc *clocks;
-        unsigned int    clocks_size;
-};
-#endif /* __ASSEMBLY__ */
-#endif /* __ASM_ARM_REGS_SERIAL_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/regs-timer.h b/arch/arm/mach-nuc93x/include/mach/regs-timer.h
deleted file mode 100644
index 394be9614d36..000000000000
--- a/arch/arm/mach-nuc93x/include/mach/regs-timer.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * arch/arm/mach-nuc93x/include/mach/regs-timer.h
- *
- * Copyright (c) 2008 Nuvoton technology corporation
- * All rights reserved.
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#ifndef __ASM_ARCH_REGS_TIMER_H
-#define __ASM_ARCH_REGS_TIMER_H
-/* Timer Registers */
-#define TMR_BA                  NUC93X_VA_TIMER
-#define REG_TCSR0               (TMR_BA+0x00)
-#define REG_TICR0               (TMR_BA+0x08)
-#define REG_TDR0                (TMR_BA+0x10)
-#define REG_TISR                (TMR_BA+0x18)
-#define REG_WTCR                (TMR_BA+0x1C)
-#endif /*  __ASM_ARCH_REGS_TIMER_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/system.h b/arch/arm/mach-nuc93x/include/mach/system.h
deleted file mode 100644
index d26bd9a52844..000000000000
--- a/arch/arm/mach-nuc93x/include/mach/system.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * arch/arm/machnuc93x/include/mach/system.h
- *
- * Copyright (c) 2008 Nuvoton technology corporation
- * All rights reserved.
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * Based on arch/arm/mach-s3c2410/include/mach/system.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#include <asm/proc-fns.h>
-static void arch_idle(void)
-{
-}
-static void arch_reset(char mode, const char *cmd)
-{
-        cpu_reset(0);
-}
diff --git a/arch/arm/mach-nuc93x/include/mach/timex.h b/arch/arm/mach-nuc93x/include/mach/timex.h
deleted file mode 100644
index 0c719cc91aa9..000000000000
--- a/arch/arm/mach-nuc93x/include/mach/timex.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * arch/arm/mach-nuc93x/include/mach/timex.h
- *
- * Copyright (c) 2008 Nuvoton technology corporation
- * All rights reserved.
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * Based on arch/arm/mach-s3c2410/include/mach/timex.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#ifndef __ASM_ARCH_TIMEX_H
-#define __ASM_ARCH_TIMEX_H
-/* CLOCK_TICK_RATE Now, I don't use it. */
-#define CLOCK_TICK_RATE 27000000
-#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/uncompress.h b/arch/arm/mach-nuc93x/include/mach/uncompress.h
deleted file mode 100644
index 381cb9baadd5..000000000000
--- a/arch/arm/mach-nuc93x/include/mach/uncompress.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * arch/arm/mach-nuc93x/include/mach/uncompress.h
- *
- * Copyright (c) 2008 Nuvoton technology corporation
- * All rights reserved.
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * Based on arch/arm/mach-s3c2410/include/mach/uncompress.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-/* Defines for UART registers */
-#include <mach/regs-serial.h>
-#include <mach/map.h>
-#include <linux/serial_reg.h>
-#define arch_decomp_wdog()
-#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
-static u32 * const uart_base = (u32 *)UART0_PA;
-static void putc(int ch)
-{
-        /* Check THRE and TEMT bits before we transmit the character.
-         */
-        while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
-                barrier();
-        *uart_base = ch;
-}
-static inline void flush(void)
-{
-}
-static void arch_decomp_setup(void)
-{
-}
-#endif/* __ASM_NUC93X_UNCOMPRESS_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/vmalloc.h b/arch/arm/mach-nuc93x/include/mach/vmalloc.h
deleted file mode 100644
index 7d11a5f07696..000000000000
--- a/arch/arm/mach-nuc93x/include/mach/vmalloc.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * arch/arm/mach-nuc93x/include/mach/vmalloc.h
- *
- * Copyright (c) 2008 Nuvoton technology corporation
- * All rights reserved.
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * Based on arch/arm/mach-s3c2410/include/mach/vmalloc.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H
-#define VMALLOC_END       0xE0000000UL
-#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-nuc93x/irq.c b/arch/arm/mach-nuc93x/irq.c
deleted file mode 100644
index aa279f23e342..000000000000
--- a/arch/arm/mach-nuc93x/irq.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * linux/arch/arm/mach-nuc93x/irq.c
- *
- * Copyright (c) 2008 Nuvoton technology corporation.
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation;version 2 of the License.
- *
- */
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/ptrace.h>
-#include <linux/sysdev.h>
-#include <linux/io.h>
-#include <asm/irq.h>
-#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include <mach/regs-irq.h>
-static void nuc93x_irq_mask(struct irq_data *d)
-{
-        __raw_writel(1 << d->irq, REG_AIC_MDCR);
-}
-/*
- * By the w90p910 spec,any irq,only write 1
- * to REG_AIC_EOSCR for ACK
- */
-static void nuc93x_irq_ack(struct irq_data *d)
-{
-        __raw_writel(0x01, REG_AIC_EOSCR);
-}
-static void nuc93x_irq_unmask(struct irq_data *d)
-{
-        __raw_writel(1 << d->irq, REG_AIC_MECR);
-}
-static struct irq_chip nuc93x_irq_chip = {
-        .irq_ack        = nuc93x_irq_ack,
-        .irq_mask       = nuc93x_irq_mask,
-        .irq_unmask     = nuc93x_irq_unmask,
-};
-void __init nuc93x_init_irq(void)
-{
-        int irqno;
-        __raw_writel(0xFFFFFFFE, REG_AIC_MDCR);
-        for (irqno = IRQ_WDT; irqno <= NR_IRQS; irqno++) {
-                irq_set_chip_and_handler(irqno, &nuc93x_irq_chip,
-                                         handle_level_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-}
diff --git a/arch/arm/mach-nuc93x/mach-nuc932evb.c b/arch/arm/mach-nuc93x/mach-nuc932evb.c
deleted file mode 100644
index 1f741b1c1604..000000000000
--- a/arch/arm/mach-nuc93x/mach-nuc932evb.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * linux/arch/arm/mach-w90x900/mach-nuc910evb.c
- *
- * Based on mach-s3c2410/mach-smdk2410.c by Jonas Dietsche
- *
- * Copyright (C) 2008 Nuvoton technology corporation.
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation;version 2 of the License.
- *
- */
-#include <linux/platform_device.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach-types.h>
-#include <mach/map.h>
-#include "nuc932.h"
-static void __init nuc932evb_map_io(void)
-{
-        nuc932_map_io();
-        nuc932_init_clocks();
-        nuc932_init_uartclk();
-}
-static void __init nuc932evb_init(void)
-{
-        nuc932_board_init();
-}
-MACHINE_START(NUC932EVB, "NUC932EVB")
-        /* Maintainer: Wan ZongShun */
-        .map_io         = nuc932evb_map_io,
-        .init_irq       = nuc93x_init_irq,
-        .init_machine   = nuc932evb_init,
-        .timer          = &nuc93x_timer,
-MACHINE_END
diff --git a/arch/arm/mach-nuc93x/nuc932.c b/arch/arm/mach-nuc93x/nuc932.c
deleted file mode 100644
index 3966ead686fc..000000000000
--- a/arch/arm/mach-nuc93x/nuc932.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * linux/arch/arm/mach-nuc93x/nuc932.c
- *
- * Copyright (c) 2009 Nuvoton corporation.
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * NUC932 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation;version 2 of the License.
- *
- */
-#include <linux/platform_device.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <asm/mach/map.h>
-#include <mach/hardware.h>
-#include "cpu.h"
-#include "clock.h"
-/* define specific CPU platform device */
-static struct platform_device *nuc932_dev[] __initdata = {
-};
-/* define specific CPU platform io map */
-static struct map_desc nuc932evb_iodesc[] __initdata = {
-};
-/*Init NUC932 evb io*/
-void __init nuc932_map_io(void)
-{
-        nuc93x_map_io(nuc932evb_iodesc, ARRAY_SIZE(nuc932evb_iodesc));
-}
-/*Init NUC932 clock*/
-void __init nuc932_init_clocks(void)
-{
-        nuc93x_init_clocks();
-}
-/*enable NUC932 uart clock*/
-void __init nuc932_init_uartclk(void)
-{
-        struct clk *ck_uart = clk_get(NULL, "uart");
-        BUG_ON(IS_ERR(ck_uart));
-        clk_enable(ck_uart);
-}
-/*Init NUC932 board info*/
-void __init nuc932_board_init(void)
-{
-        nuc93x_board_init(nuc932_dev, ARRAY_SIZE(nuc932_dev));
-}
diff --git a/arch/arm/mach-nuc93x/nuc932.h b/arch/arm/mach-nuc93x/nuc932.h
deleted file mode 100644
index 9a66edd5338f..000000000000
--- a/arch/arm/mach-nuc93x/nuc932.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * arch/arm/mach-nuc93x/nuc932.h
- *
- * Copyright (c) 2008 Nuvoton corporation
- *
- * Header file for NUC93x CPU support
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-struct map_desc;
-struct sys_timer;
-/* core initialisation functions */
-extern void nuc93x_init_irq(void);
-extern struct sys_timer nuc93x_timer;
-/* extern file from nuc932.c */
-extern void nuc932_board_init(void);
-extern void nuc932_init_clocks(void);
-extern void nuc932_map_io(void);
-extern void nuc932_init_uartclk(void);
diff --git a/arch/arm/mach-nuc93x/time.c b/arch/arm/mach-nuc93x/time.c
deleted file mode 100644
index f9807c029ec5..000000000000
--- a/arch/arm/mach-nuc93x/time.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * linux/arch/arm/mach-nuc93x/time.c
- *
- * Copyright (c) 2009 Nuvoton technology corporation.
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/leds.h>
-#include <asm/mach-types.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/time.h>
-#include <mach/system.h>
-#include <mach/map.h>
-#include <mach/regs-timer.h>
-#define RESETINT        0x01
-#define PERIOD          (0x01 << 27)
-#define ONESHOT         (0x00 << 27)
-#define COUNTEN         (0x01 << 30)
-#define INTEN           (0x01 << 29)
-#define TICKS_PER_SEC   100
-#define PRESCALE        0x63 /* Divider = prescale + 1 */
-unsigned int timer0_load;
-static unsigned long nuc93x_gettimeoffset(void)
-{
-        return 0;
-}
-/*IRQ handler for the timer*/
-static irqreturn_t nuc93x_timer_interrupt(int irq, void *dev_id)
-{
-        timer_tick();
-        __raw_writel(0x01, REG_TISR); /* clear TIF0 */
-        return IRQ_HANDLED;
-}
-static struct irqaction nuc93x_timer_irq = {
-        .name           = "nuc93x Timer Tick",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = nuc93x_timer_interrupt,
-};
-/*Set up timer reg.*/
-static void nuc93x_timer_setup(void)
-{
-        struct clk *ck_ext = clk_get(NULL, "ext");
-        struct clk *ck_timer = clk_get(NULL, "timer");
-        unsigned int rate, val = 0;
-        BUG_ON(IS_ERR(ck_ext) || IS_ERR(ck_timer));
-        clk_enable(ck_timer);
-        rate = clk_get_rate(ck_ext);
-        clk_put(ck_ext);
-        rate = rate / (PRESCALE + 0x01);
-         /* set a known state */
-        __raw_writel(0x00, REG_TCSR0);
-        __raw_writel(RESETINT, REG_TISR);
-        timer0_load = (rate / TICKS_PER_SEC);
-        __raw_writel(timer0_load, REG_TICR0);
-        val |= (PERIOD | COUNTEN | INTEN | PRESCALE);
-        __raw_writel(val, REG_TCSR0);
-}
-static void __init nuc93x_timer_init(void)
-{
-        nuc93x_timer_setup();
-        setup_irq(IRQ_TIMER0, &nuc93x_timer_irq);
-}
-struct sys_timer nuc93x_timer = {
-        .init           = nuc93x_timer_init,
-        .offset         = nuc93x_gettimeoffset,
-        .resume         = nuc93x_timer_setup
-};
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 5b114d1558c8..11c85cd2731a 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -4,7 +4,7 @@
 # Common support
 obj-y := io.o id.o sram.o time.o irq.o mux.o flash.o serial.o devices.o dma.o
-obj-y += clock.o clock_data.o opp_data.o reset.o pm_bus.o
+obj-y += clock.o clock_data.o opp_data.o reset.o pm_bus.o timer.o
 obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index 4ea60e2038ea..1f1db76d704a 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -134,12 +134,6 @@ void ams_delta_latch2_write(u16 mask, u16 value)
        *(volatile __u16 *) AMS_DELTA_LATCH2_VIRT = ams_delta_latch2_reg;
 }
-static void __init ams_delta_init_irq(void)
-{
-        omap1_init_common_hw();
-        omap1_init_irq();
-}
 static struct map_desc ams_delta_io_desc[] __initdata = {
        /* AMS_DELTA_LATCH1 */
        {
@@ -378,17 +372,13 @@ static int __init ams_delta_modem_init(void)
 }
 arch_initcall(ams_delta_modem_init);
-static void __init ams_delta_map_io(void)
-{
-        omap1_map_common_io();
-}
 MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)")
        /* Maintainer: Jonathan McDowell <noodles@earth.li> */
        .atag_offset    = 0x100,
-        .map_io         = ams_delta_map_io,
+        .map_io         = omap15xx_map_io,
+        .init_early     = omap1_init_early,
        .reserve        = omap_reserve,
-        .init_irq       = ams_delta_init_irq,
+        .init_irq       = omap1_init_irq,
        .init_machine   = ams_delta_init,
        .timer          = &omap1_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 31e089b6f03f..23178275f96b 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -296,6 +296,39 @@ static struct omap_board_config_kernel fsample_config[] __initdata = {
 static void __init omap_fsample_init(void)
 {
+        /* Early, board-dependent init */
+        /*
+         * Hold GSM Reset until needed
+         */
+        omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL);
+        /*
+         * UARTs -> done automagically by 8250 driver
+         */
+        /*
+         * CSx timings, GPIO Mux ... setup
+         */
+        /* Flash: CS0 timings setup */
+        omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0);
+        omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0);
+        /*
+         * Ethernet support through the debug board
+         * CS1 timings setup
+         */
+        omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1);
+        omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1);
+        /*
+         * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
+         * It is used as the Ethernet controller interrupt
+         */
+        omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF,
+                        OMAP7XX_IO_CONF_9);
        fsample_init_smc91x();
        if (gpio_request(FSAMPLE_NAND_RB_GPIO_PIN, "NAND ready") < 0)
@@ -325,12 +358,6 @@ static void __init omap_fsample_init(void)
        omap_register_i2c_bus(1, 100, NULL, 0);
 }
-static void __init omap_fsample_init_irq(void)
-{
-        omap1_init_common_hw();
-        omap1_init_irq();
-}
 /* Only FPGA needs to be mapped here. All others are done with ioremap */
 static struct map_desc omap_fsample_io_desc[] __initdata = {
        {
@@ -349,49 +376,18 @@ static struct map_desc omap_fsample_io_desc[] __initdata = {
 static void __init omap_fsample_map_io(void)
 {
-        omap1_map_common_io();
+        omap15xx_map_io();
        iotable_init(omap_fsample_io_desc,
                     ARRAY_SIZE(omap_fsample_io_desc));
-        /* Early, board-dependent init */
-        /*
-         * Hold GSM Reset until needed
-         */
-        omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL);
-        /*
-         * UARTs -> done automagically by 8250 driver
-         */
-        /*
-         * CSx timings, GPIO Mux ... setup
-         */
-        /* Flash: CS0 timings setup */
-        omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0);
-        omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0);
-        /*
-         * Ethernet support through the debug board
-         * CS1 timings setup
-         */
-        omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1);
-        omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1);
-        /*
-         * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
-         * It is used as the Ethernet controller interrupt
-         */
-        omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF, OMAP7XX_IO_CONF_9);
 }
 MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
 /* Maintainer: Brian Swetland <swetland@google.com> */
        .atag_offset    = 0x100,
        .map_io         = omap_fsample_map_io,
+        .init_early     = omap1_init_early,
        .reserve        = omap_reserve,
-        .init_irq       = omap_fsample_init_irq,
+        .init_irq       = omap1_init_irq,
        .init_machine   = omap_fsample_init,
        .timer          = &omap1_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
index 05c6e9d858f3..dc5b75de531c 100644
--- a/arch/arm/mach-omap1/board-generic.c
+++ b/arch/arm/mach-omap1/board-generic.c
@@ -27,12 +27,6 @@
 #include <plat/board.h>
 #include <plat/common.h>
-static void __init omap_generic_init_irq(void)
-{
-        omap1_init_common_hw();
-        omap1_init_irq();
-}
 /* assume no Mini-AB port */
 #ifdef CONFIG_ARCH_OMAP15XX
@@ -86,17 +80,13 @@ static void __init omap_generic_init(void)
        omap_register_i2c_bus(1, 100, NULL, 0);
 }
-static void __init omap_generic_map_io(void)
-{
-        omap1_map_common_io();
-}
 MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710")
        /* Maintainer: Tony Lindgren <tony@atomide.com> */
        .atag_offset    = 0x100,
-        .map_io         = omap_generic_map_io,
+        .map_io         = omap16xx_map_io,
+        .init_early     = omap1_init_early,
        .reserve        = omap_reserve,
-        .init_irq       = omap_generic_init_irq,
+        .init_irq       = omap1_init_irq,
        .init_machine   = omap_generic_init,
        .timer          = &omap1_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index c2e279173d42..b334b1481678 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -372,12 +372,6 @@ static struct i2c_board_info __initdata h2_i2c_board_info[] = {
        },
 };
-static void __init h2_init_irq(void)
-{
-        omap1_init_common_hw();
-        omap1_init_irq();
-}
 static struct omap_usb_config h2_usb_config __initdata = {
        /* usb1 has a Mini-AB port and external isp1301 transceiver */
        .otg            = 2,
@@ -453,17 +447,13 @@ static void __init h2_init(void)
        h2_mmc_init();
 }
-static void __init h2_map_io(void)
-{
-        omap1_map_common_io();
-}
 MACHINE_START(OMAP_H2, "TI-H2")
        /* Maintainer: Imre Deak <imre.deak@nokia.com> */
        .atag_offset    = 0x100,
-        .map_io         = h2_map_io,
+        .map_io         = omap16xx_map_io,
+        .init_early     = omap1_init_early,
        .reserve        = omap_reserve,
-        .init_irq       = h2_init_irq,
+        .init_irq       = omap1_init_irq,
        .init_machine   = h2_init,
        .timer          = &omap1_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 8f5b6af7ed59..74ebe72c9848 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -435,23 +435,13 @@ static void __init h3_init(void)
        h3_mmc_init();
 }
-static void __init h3_init_irq(void)
-{
-        omap1_init_common_hw();
-        omap1_init_irq();
-}
-static void __init h3_map_io(void)
-{
-        omap1_map_common_io();
-}
 MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
        /* Maintainer: Texas Instruments, Inc. */
        .atag_offset    = 0x100,
-        .map_io         = h3_map_io,
+        .map_io         = omap16xx_map_io,
+        .init_early     = omap1_init_early,
        .reserve        = omap_reserve,
-        .init_irq       = h3_init_irq,
+        .init_irq       = omap1_init_irq,
        .init_machine   = h3_init,
        .timer          = &omap1_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index fcd1a3c31896..3e91baab1a89 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -499,7 +499,7 @@ static void __init htcherald_lcd_init(void)
 static void __init htcherald_map_io(void)
 {
-        omap1_map_common_io();
+        omap7xx_map_io();
        /*
         * The LCD panel must be disabled and DMA turned off here, as doing
@@ -600,20 +600,14 @@ static void __init htcherald_init(void)
 #endif
 }
-static void __init htcherald_init_irq(void)
-{
-        printk(KERN_INFO "htcherald_init_irq.\n");
-        omap1_init_common_hw();
-        omap1_init_irq();
-}
 MACHINE_START(HERALD, "HTC Herald")
        /* Maintainer: Cory Maccarrone <darkstar6262@gmail.com> */
        /* Maintainer: wing-linux.sourceforge.net */
        .atag_offset    = 0x100,
        .map_io         = htcherald_map_io,
+        .init_early     = omap1_init_early,
        .reserve        = omap_reserve,
-        .init_irq       = htcherald_init_irq,
+        .init_irq       = omap1_init_irq,
        .init_machine   = htcherald_init,
        .timer          = &omap1_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index c2234caf8a7a..273153dba15b 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -288,12 +288,6 @@ static void __init innovator_init_smc91x(void)
        }
 }
-static void __init innovator_init_irq(void)
-{
-        omap1_init_common_hw();
-        omap1_init_irq();
-}
 #ifdef CONFIG_ARCH_OMAP15XX
 static struct omap_usb_config innovator1510_usb_config __initdata = {
        /* for bundled non-standard host and peripheral cables */
@@ -438,30 +432,32 @@ static void __init innovator_init(void)
        innovator_mmc_init();
 }
+/*
+ * REVISIT: Assume 15xx for now, we don't want to do revision check
+ * until later on. The right way to fix this is to set up a different
+ * machine_id for 16xx Innovator, or use device tree.
+ */
 static void __init innovator_map_io(void)
 {
-        omap1_map_common_io();
+        omap15xx_map_io();
-#ifdef CONFIG_ARCH_OMAP15XX
+        iotable_init(innovator1510_io_desc, ARRAY_SIZE(innovator1510_io_desc));
-        if (cpu_is_omap1510()) {
+        udelay(10);     /* Delay needed for FPGA */
-                iotable_init(innovator1510_io_desc, ARRAY_SIZE(innovator1510_io_desc));
-                udelay(10);     /* Delay needed for FPGA */
+        /* Dump the Innovator FPGA rev early - useful info for support. */
+        pr_debug("Innovator FPGA Rev %d.%d Board Rev %d\n",
-                /* Dump the Innovator FPGA rev early - useful info for support. */
+                        fpga_read(OMAP1510_FPGA_REV_HIGH),
-                printk("Innovator FPGA Rev %d.%d Board Rev %d\n",
+                        fpga_read(OMAP1510_FPGA_REV_LOW),
-                       fpga_read(OMAP1510_FPGA_REV_HIGH),
+                        fpga_read(OMAP1510_FPGA_BOARD_REV));
-                       fpga_read(OMAP1510_FPGA_REV_LOW),
-                       fpga_read(OMAP1510_FPGA_BOARD_REV));
-        }
-#endif
 }
 MACHINE_START(OMAP_INNOVATOR, "TI-Innovator")
        /* Maintainer: MontaVista Software, Inc. */
        .atag_offset    = 0x100,
        .map_io         = innovator_map_io,
+        .init_early     = omap1_init_early,
        .reserve        = omap_reserve,
-        .init_irq       = innovator_init_irq,
+        .init_irq       = omap1_init_irq,
        .init_machine   = innovator_init,
        .timer          = &omap1_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index 02789c5d3703..6798b8488315 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -38,21 +38,6 @@
 #define ADS7846_PENDOWN_GPIO    15
-static void __init omap_nokia770_init_irq(void)
-{
-        /* On Nokia 770, the SleepX signal is masked with an
-         * MPUIO line by default.  It has to be unmasked for it
-         * to become functional */
-        /* SleepX mask direction */
-        omap_writew((omap_readw(0xfffb5008) & ~2), 0xfffb5008);
-        /* Unmask SleepX signal */
-        omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004);
-        omap1_init_common_hw();
-        omap1_init_irq();
-}
 static const unsigned int nokia770_keymap[] = {
        KEY(1, 0, GROUP_0 | KEY_UP),
        KEY(2, 0, GROUP_1 | KEY_F5),
@@ -245,6 +230,15 @@ static inline void nokia770_mmc_init(void)
 static void __init omap_nokia770_init(void)
 {
+        /* On Nokia 770, the SleepX signal is masked with an
+         * MPUIO line by default.  It has to be unmasked for it
+         * to become functional */
+        /* SleepX mask direction */
+        omap_writew((omap_readw(0xfffb5008) & ~2), 0xfffb5008);
+        /* Unmask SleepX signal */
+        omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004);
        platform_add_devices(nokia770_devices, ARRAY_SIZE(nokia770_devices));
        spi_register_board_info(nokia770_spi_board_info,
                                ARRAY_SIZE(nokia770_spi_board_info));
@@ -257,16 +251,12 @@ static void __init omap_nokia770_init(void)
        nokia770_mmc_init();
 }
-static void __init omap_nokia770_map_io(void)
-{
-        omap1_map_common_io();
-}
 MACHINE_START(NOKIA770, "Nokia 770")
        .atag_offset    = 0x100,
-        .map_io         = omap_nokia770_map_io,
+        .map_io         = omap16xx_map_io,
+        .init_early     = omap1_init_early,
        .reserve        = omap_reserve,
-        .init_irq       = omap_nokia770_init_irq,
+        .init_irq       = omap1_init_irq,
        .init_machine   = omap_nokia770_init,
        .timer          = &omap1_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index e4dca1deebb4..c3859278d257 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -278,12 +278,6 @@ static void __init osk_init_cf(void)
        irq_set_irq_type(gpio_to_irq(62), IRQ_TYPE_EDGE_FALLING);
 }
-static void __init osk_init_irq(void)
-{
-        omap1_init_common_hw();
-        omap1_init_irq();
-}
 static struct omap_usb_config osk_usb_config __initdata = {
        /* has usb host connector (A) ... for development it can also
         * be used, with a NONSTANDARD gender-bending cable/dongle, as
@@ -575,17 +569,13 @@ static void __init osk_init(void)
        osk_mistral_init();
 }
-static void __init osk_map_io(void)
-{
-        omap1_map_common_io();
-}
 MACHINE_START(OMAP_OSK, "TI-OSK")
        /* Maintainer: Dirk Behme <dirk.behme@de.bosch.com> */
        .atag_offset    = 0x100,
-        .map_io         = osk_map_io,
+        .map_io         = omap16xx_map_io,
+        .init_early     = omap1_init_early,
        .reserve        = omap_reserve,
-        .init_irq       = osk_init_irq,
+        .init_irq       = omap1_init_irq,
        .init_machine   = osk_init,
        .timer          = &omap1_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 50c4e398bcc8..f9c44cb15b47 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -58,12 +58,6 @@
 #define PALMTE_MMC2_GPIO        OMAP_MPUIO(7)
 #define PALMTE_MMC3_GPIO        OMAP_MPUIO(11)
-static void __init omap_palmte_init_irq(void)
-{
-        omap1_init_common_hw();
-        omap1_init_irq();
-}
 static const unsigned int palmte_keymap[] = {
        KEY(0, 0, KEY_F1),              /* Calendar */
        KEY(1, 0, KEY_F2),              /* Contacts */
@@ -268,16 +262,12 @@ static void __init omap_palmte_init(void)
        omap_register_i2c_bus(1, 100, NULL, 0);
 }
-static void __init omap_palmte_map_io(void)
-{
-        omap1_map_common_io();
-}
 MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E")
        .atag_offset    = 0x100,
-        .map_io         = omap_palmte_map_io,
+        .map_io         = omap15xx_map_io,
+        .init_early     = omap1_init_early,
        .reserve        = omap_reserve,
-        .init_irq       = omap_palmte_init_irq,
+        .init_irq       = omap1_init_irq,
        .init_machine   = omap_palmte_init,
        .timer          = &omap1_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index 273771cb1b61..11a98539f7bb 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -263,12 +263,6 @@ static struct spi_board_info __initdata palmtt_boardinfo[] = {
        }
 };
-static void __init omap_palmtt_init_irq(void)
-{
-        omap1_init_common_hw();
-        omap1_init_irq();
-}
 static struct omap_usb_config palmtt_usb_config __initdata = {
        .register_dev   = 1,
        .hmc_mode       = 0,
@@ -315,16 +309,12 @@ static void __init omap_palmtt_init(void)
        omap_register_i2c_bus(1, 100, NULL, 0);
 }
-static void __init omap_palmtt_map_io(void)
-{
-        omap1_map_common_io();
-}
 MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T")
        .atag_offset    = 0x100,
-        .map_io         = omap_palmtt_map_io,
+        .map_io         = omap15xx_map_io,
+        .init_early     = omap1_init_early,
        .reserve        = omap_reserve,
-        .init_irq       = omap_palmtt_init_irq,
+        .init_irq       = omap1_init_irq,
        .init_machine   = omap_palmtt_init,
        .timer          = &omap1_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index de36ade38ef7..c6fe61dfe856 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -57,13 +57,6 @@
 #define PALMZ71_SLIDER_GPIO     OMAP_MPUIO(3)
 #define PALMZ71_MMC_IN_GPIO     OMAP_MPUIO(4)
-static void __init
-omap_palmz71_init_irq(void)
-{
-        omap1_init_common_hw();
-        omap1_init_irq();
-}
 static const unsigned int palmz71_keymap[] = {
        KEY(0, 0, KEY_F1),
        KEY(1, 0, KEY_F2),
@@ -334,17 +327,12 @@ omap_palmz71_init(void)
        palmz71_gpio_setup(0);
 }
-static void __init
-omap_palmz71_map_io(void)
-{
-        omap1_map_common_io();
-}
 MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71")
        .atag_offset    = 0x100,
-        .map_io         = omap_palmz71_map_io,
+        .map_io         = omap15xx_map_io,
+        .init_early     = omap1_init_early,
        .reserve        = omap_reserve,
-        .init_irq       = omap_palmz71_init_irq,
+        .init_irq       = omap1_init_irq,
        .init_machine   = omap_palmz71_init,
        .timer          = &omap1_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index 04b1befaced6..203ae07550db 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -264,6 +264,39 @@ static void __init perseus2_init_smc91x(void)
 static void __init omap_perseus2_init(void)
 {
+        /* Early, board-dependent init */
+        /*
+         * Hold GSM Reset until needed
+         */
+        omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL);
+        /*
+         * UARTs -> done automagically by 8250 driver
+         */
+        /*
+         * CSx timings, GPIO Mux ... setup
+         */
+        /* Flash: CS0 timings setup */
+        omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0);
+        omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0);
+        /*
+         * Ethernet support through the debug board
+         * CS1 timings setup
+         */
+        omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1);
+        omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1);
+        /*
+         * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
+         * It is used as the Ethernet controller interrupt
+         */
+        omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF,
+                                OMAP7XX_IO_CONF_9);
        perseus2_init_smc91x();
        if (gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0)
@@ -293,11 +326,6 @@ static void __init omap_perseus2_init(void)
        omap_register_i2c_bus(1, 100, NULL, 0);
 }
-static void __init omap_perseus2_init_irq(void)
-{
-        omap1_init_common_hw();
-        omap1_init_irq();
-}
 /* Only FPGA needs to be mapped here. All others are done with ioremap */
 static struct map_desc omap_perseus2_io_desc[] __initdata = {
        {
@@ -310,49 +338,18 @@ static struct map_desc omap_perseus2_io_desc[] __initdata = {
 static void __init omap_perseus2_map_io(void)
 {
-        omap1_map_common_io();
+        omap7xx_map_io();
        iotable_init(omap_perseus2_io_desc,
                     ARRAY_SIZE(omap_perseus2_io_desc));
-        /* Early, board-dependent init */
-        /*
-         * Hold GSM Reset until needed
-         */
-        omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL);
-        /*
-         * UARTs -> done automagically by 8250 driver
-         */
-        /*
-         * CSx timings, GPIO Mux ... setup
-         */
-        /* Flash: CS0 timings setup */
-        omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0);
-        omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0);
-        /*
-         * Ethernet support through the debug board
-         * CS1 timings setup
-         */
-        omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1);
-        omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1);
-        /*
-         * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
-         * It is used as the Ethernet controller interrupt
-         */
-        omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF, OMAP7XX_IO_CONF_9);
 }
 MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
        /* Maintainer: Kevin Hilman <kjh@hilman.org> */
        .atag_offset    = 0x100,
        .map_io         = omap_perseus2_map_io,
+        .init_early     = omap1_init_early,
        .reserve        = omap_reserve,
-        .init_irq       = omap_perseus2_init_irq,
+        .init_irq       = omap1_init_irq,
        .init_machine   = omap_perseus2_init,
        .timer          = &omap1_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 2bea941741d5..667a7cbdb11c 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -406,24 +406,13 @@ static void __init omap_sx1_init(void)
        gpio_direction_output(11, 0);   /*A_SWITCH = 0 */
        gpio_direction_output(15, 0);   /*A_USB_ON = 0 */
 }
-/*----------------------------------------*/
-static void __init omap_sx1_init_irq(void)
-{
-        omap1_init_common_hw();
-        omap1_init_irq();
-}
-/*----------------------------------------*/
-static void __init omap_sx1_map_io(void)
-{
-        omap1_map_common_io();
-}
 MACHINE_START(SX1, "OMAP310 based Siemens SX1")
        .atag_offset    = 0x100,
-        .map_io         = omap_sx1_map_io,
+        .map_io         = omap15xx_map_io,
+        .init_early     = omap1_init_early,
        .reserve        = omap_reserve,
-        .init_irq       = omap_sx1_init_irq,
+        .init_irq       = omap1_init_irq,
        .init_machine   = omap_sx1_init,
        .timer          = &omap1_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 940faed82be2..2a6545ba61c4 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -159,17 +159,6 @@ static struct omap_usb_config voiceblue_usb_config __initdata = {
 static struct omap_board_config_kernel voiceblue_config[] = {
 };
-static void __init voiceblue_init_irq(void)
-{
-        omap1_init_common_hw();
-        omap1_init_irq();
-}
-static void __init voiceblue_map_io(void)
-{
-        omap1_map_common_io();
-}
 #define MACHINE_PANICED         1
 #define MACHINE_REBOOTING       2
 #define MACHINE_REBOOT          4
@@ -302,9 +291,10 @@ static void __init voiceblue_init(void)
 MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910")
        /* Maintainer: Ladislav Michl <michl@2n.cz> */
        .atag_offset    = 0x100,
-        .map_io         = voiceblue_map_io,
+        .map_io         = omap15xx_map_io,
+        .init_early     = omap1_init_early,
        .reserve        = omap_reserve,
-        .init_irq       = voiceblue_init_irq,
+        .init_irq       = omap1_init_irq,
        .init_machine   = voiceblue_init,
        .timer          = &omap1_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index 7c50ecf68123..48ef9888e820 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -22,6 +22,7 @@
 #include <mach/hardware.h>
 #include <asm/mach/map.h>
+#include <plat/common.h>
 #include <plat/tc.h>
 #include <plat/board.h>
 #include <plat/mux.h>
@@ -291,6 +292,8 @@ static int __init omap1_init_devices(void)
        if (!cpu_class_is_omap1())
                return -ENODEV;
+        omap_sram_init();
        /* please keep these calls, and their implementations above,
         * in alphabetical order so they're easier to sort through.
         */
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
index 1cfa1b6bb62b..7969cfda4454 100644
--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -21,7 +21,6 @@
 #include "clock.h"
 extern void omap_check_revision(void);
-extern void omap_sram_init(void);
 /*
 * The machine specific code may provide the extra mapping besides the
@@ -85,51 +84,45 @@ static struct map_desc omap16xx_io_desc[] __initdata = {
 #endif
 /*
- * Maps common IO regions for omap1. This should only get called from
+ * Maps common IO regions for omap1
- * board specific init.
 */
-void __init omap1_map_common_io(void)
+static void __init omap1_map_common_io(void)
 {
        iotable_init(omap_io_desc, ARRAY_SIZE(omap_io_desc));
+}
-        /* Normally devicemaps_init() would flush caches and tlb after
-         * mdesc->map_io(), but we must also do it here because of the CPU
-         * revision check below.
-         */
-        local_flush_tlb_all();
-        flush_cache_all();
-        /* We want to check CPU revision early for cpu_is_omapxxxx() macros.
-         * IO space mapping must be initialized before we can do that.
-         */
-        omap_check_revision();
 #if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
-        if (cpu_is_omap7xx()) {
+void __init omap7xx_map_io(void)
-                iotable_init(omap7xx_io_desc, ARRAY_SIZE(omap7xx_io_desc));
+{
-        }
+        omap1_map_common_io();
+        iotable_init(omap7xx_io_desc, ARRAY_SIZE(omap7xx_io_desc));
+}
 #endif
 #ifdef CONFIG_ARCH_OMAP15XX
-        if (cpu_is_omap15xx()) {
+void __init omap15xx_map_io(void)
-                iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc));
+{
-        }
+        omap1_map_common_io();
-#endif
+        iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc));
-#if defined(CONFIG_ARCH_OMAP16XX)
+}
-        if (cpu_is_omap16xx()) {
-                iotable_init(omap16xx_io_desc, ARRAY_SIZE(omap16xx_io_desc));
-        }
 #endif
-        omap_sram_init();
+#if defined(CONFIG_ARCH_OMAP16XX)
-        omap_init_consistent_dma_size();
+void __init omap16xx_map_io(void)
+{
+        omap1_map_common_io();
+        iotable_init(omap16xx_io_desc, ARRAY_SIZE(omap16xx_io_desc));
 }
+#endif
 /*
- * Common low-level hardware init for omap1. This should only get called from
+ * Common low-level hardware init for omap1.
- * board specific init.
 */
-void __init omap1_init_common_hw(void)
+void omap1_init_early(void)
 {
+        omap_check_revision();
+        omap_ioremap_init();
        /* REVISIT: Refer to OMAP5910 Errata, Advisory SYS_1: "Timeout Abort
         * on a Posted Write in the TIPB Bridge".
         */
@@ -139,8 +132,8 @@ void __init omap1_init_common_hw(void)
        /* Must init clocks early to assure that timer interrupt works
         */
        omap1_clk_init();
        omap1_mux_init();
+        omap_init_consistent_dma_size();
 }
 /*
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index ab7395d84bc8..91f9abbd3250 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -31,6 +31,7 @@
 static int dsp_use;
 static struct clk *api_clk;
 static struct clk *dsp_clk;
+static struct platform_device **omap_mcbsp_devices;
 static void omap1_mcbsp_request(unsigned int id)
 {
@@ -78,6 +79,17 @@ static struct omap_mcbsp_ops omap1_mcbsp_ops = {
        .free           = omap1_mcbsp_free,
 };
+#define OMAP7XX_MCBSP1_BASE     0xfffb1000
+#define OMAP7XX_MCBSP2_BASE     0xfffb1800
+#define OMAP1510_MCBSP1_BASE    0xe1011800
+#define OMAP1510_MCBSP2_BASE    0xfffb1000
+#define OMAP1510_MCBSP3_BASE    0xe1017000
+#define OMAP1610_MCBSP1_BASE    0xe1011800
+#define OMAP1610_MCBSP2_BASE    0xfffb1000
+#define OMAP1610_MCBSP3_BASE    0xe1017000
 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
 struct resource omap7xx_mcbsp_res[][6] = {
        {
@@ -369,6 +381,39 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
 #define OMAP16XX_MCBSP_COUNT            0
 #endif
+static void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
+                        struct omap_mcbsp_platform_data *config, int size)
+{
+        int i;
+        omap_mcbsp_devices = kzalloc(size * sizeof(struct platform_device *),
+                                     GFP_KERNEL);
+        if (!omap_mcbsp_devices) {
+                printk(KERN_ERR "Could not register McBSP devices\n");
+                return;
+        }
+        for (i = 0; i < size; i++) {
+                struct platform_device *new_mcbsp;
+                int ret;
+                new_mcbsp = platform_device_alloc("omap-mcbsp", i + 1);
+                if (!new_mcbsp)
+                        continue;
+                platform_device_add_resources(new_mcbsp, &res[i * res_count],
+                                        res_count);
+                config[i].reg_size = 2;
+                config[i].reg_step = 2;
+                new_mcbsp->dev.platform_data = &config[i];
+                ret = platform_device_add(new_mcbsp);
+                if (ret) {
+                        platform_device_put(new_mcbsp);
+                        continue;
+                }
+                omap_mcbsp_devices[i] = new_mcbsp;
+        }
+}
 static int __init omap1_mcbsp_init(void)
 {
        if (!cpu_class_is_omap1())
diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c
new file mode 100644
index 000000000000..6e90665a7c47
--- /dev/null
+++ b/arch/arm/mach-omap1/timer.c
@@ -0,0 +1,173 @@
+/**
+ * OMAP1 Dual-Mode Timers - platform device registration
+ *
+ * Contains first level initialization routines which internally
+ * generates timer device information and registers with linux
+ * device model. It also has low level function to chnage the timer
+ * input clock source.
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Tarun Kanti DebBarma <tarun.kanti@ti.com>
+ * Thara Gopinath <thara@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <mach/irqs.h>
+#include <plat/dmtimer.h>
+#define OMAP1610_GPTIMER1_BASE          0xfffb1400
+#define OMAP1610_GPTIMER2_BASE          0xfffb1c00
+#define OMAP1610_GPTIMER3_BASE          0xfffb2400
+#define OMAP1610_GPTIMER4_BASE          0xfffb2c00
+#define OMAP1610_GPTIMER5_BASE          0xfffb3400
+#define OMAP1610_GPTIMER6_BASE          0xfffb3c00
+#define OMAP1610_GPTIMER7_BASE          0xfffb7400
+#define OMAP1610_GPTIMER8_BASE          0xfffbd400
+#define OMAP1_DM_TIMER_COUNT            8
+static int omap1_dm_timer_set_src(struct platform_device *pdev,
+                                int source)
+{
+        int n = (pdev->id - 1) << 1;
+        u32 l;
+        l = __raw_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
+        l |= source << n;
+        __raw_writel(l, MOD_CONF_CTRL_1);
+        return 0;
+}
+int __init omap1_dm_timer_init(void)
+{
+        int i;
+        int ret;
+        struct dmtimer_platform_data *pdata;
+        struct platform_device *pdev;
+        if (!cpu_is_omap16xx())
+                return 0;
+        for (i = 1; i <= OMAP1_DM_TIMER_COUNT; i++) {
+                struct resource res[2];
+                u32 base, irq;
+                switch (i) {
+                case 1:
+                        base = OMAP1610_GPTIMER1_BASE;
+                        irq = INT_1610_GPTIMER1;
+                        break;
+                case 2:
+                        base = OMAP1610_GPTIMER2_BASE;
+                        irq = INT_1610_GPTIMER2;
+                        break;
+                case 3:
+                        base = OMAP1610_GPTIMER3_BASE;
+                        irq = INT_1610_GPTIMER3;
+                        break;
+                case 4:
+                        base = OMAP1610_GPTIMER4_BASE;
+                        irq = INT_1610_GPTIMER4;
+                        break;
+                case 5:
+                        base = OMAP1610_GPTIMER5_BASE;
+                        irq = INT_1610_GPTIMER5;
+                        break;
+                case 6:
+                        base = OMAP1610_GPTIMER6_BASE;
+                        irq = INT_1610_GPTIMER6;
+                        break;
+                case 7:
+                        base = OMAP1610_GPTIMER7_BASE;
+                        irq = INT_1610_GPTIMER7;
+                        break;
+                case 8:
+                        base = OMAP1610_GPTIMER8_BASE;
+                        irq = INT_1610_GPTIMER8;
+                        break;
+                default:
+                        /*
+                         * not supposed to reach here.
+                         * this is to remove warning.
+                         */
+                        return -EINVAL;
+                }
+                pdev = platform_device_alloc("omap_timer", i);
+                if (!pdev) {
+                        pr_err("%s: Failed to device alloc for dmtimer%d\n",
+                                __func__, i);
+                        return -ENOMEM;
+                }
+                memset(res, 0, 2 * sizeof(struct resource));
+                res[0].start = base;
+                res[0].end = base + 0x46;
+                res[0].flags = IORESOURCE_MEM;
+                res[1].start = irq;
+                res[1].end = irq;
+                res[1].flags = IORESOURCE_IRQ;
+                ret = platform_device_add_resources(pdev, res,
+                                ARRAY_SIZE(res));
+                if (ret) {
+                        dev_err(&pdev->dev, "%s: Failed to add resources.\n",
+                                __func__);
+                        goto err_free_pdev;
+                }
+                pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
+                if (!pdata) {
+                        dev_err(&pdev->dev, "%s: Failed to allocate pdata.\n",
+                                __func__);
+                        ret = -ENOMEM;
+                        goto err_free_pdata;
+                }
+                pdata->set_timer_src = omap1_dm_timer_set_src;
+                pdata->needs_manual_reset = 1;
+                ret = platform_device_add_data(pdev, pdata, sizeof(*pdata));
+                if (ret) {
+                        dev_err(&pdev->dev, "%s: Failed to add platform data.\n",
+                                __func__);
+                        goto err_free_pdata;
+                }
+                ret = platform_device_add(pdev);
+                if (ret) {
+                        dev_err(&pdev->dev, "%s: Failed to add platform device.\n",
+                                __func__);
+                        goto err_free_pdata;
+                }
+                dev_dbg(&pdev->dev, " Registered.\n");
+        }
+        return 0;
+err_free_pdata:
+        kfree(pdata);
+err_free_pdev:
+        platform_device_unregister(pdev);
+        return ret;
+}
+arch_initcall(omap1_dm_timer_init);
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 89bfb49389f2..497e9dc27958 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -108,9 +108,13 @@ comment "OMAP Board Type"
        depends on ARCH_OMAP2PLUS
 config MACH_OMAP_GENERIC
-        bool "Generic OMAP board"
+        bool "Generic OMAP2+ board"
-        depends on ARCH_OMAP2
+        depends on ARCH_OMAP2PLUS
+        select USE_OF
        default y
+        help
+          Support for generic TI OMAP2+ boards using Flattened Device Tree.
+          More information at Documentation/devicetree
 config MACH_OMAP2_TUSB6010
        bool
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 7317a2b39dd1..69ab1c069134 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -89,14 +89,13 @@ obj-$(CONFIG_ARCH_OMAP4)		+= prcm.o cm2xxx_3xxx.o cminst44xx.o \
                                           vp44xx_data.o
 # OMAP voltage domains
-ifeq ($(CONFIG_PM),y)
+voltagedomain-common                    := voltage.o vc.o vp.o
-voltagedomain-common                    := voltage.o
+obj-$(CONFIG_ARCH_OMAP2)                += $(voltagedomain-common) \
-obj-$(CONFIG_ARCH_OMAP2)                += $(voltagedomain-common)
+                                           voltagedomains2xxx_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += $(voltagedomain-common) \
                                           voltagedomains3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += $(voltagedomain-common) \
                                           voltagedomains44xx_data.o
-endif
 # OMAP powerdomain framework
 powerdomain-common                      += powerdomain.o powerdomain-common.o
@@ -116,9 +115,12 @@ obj-$(CONFIG_ARCH_OMAP4)		+= $(powerdomain-common) \
 obj-$(CONFIG_ARCH_OMAP2)                += clockdomain.o \
                                           clockdomain2xxx_3xxx.o \
                                           clockdomains2xxx_3xxx_data.o
+obj-$(CONFIG_SOC_OMAP2420)              += clockdomains2420_data.o
+obj-$(CONFIG_SOC_OMAP2430)              += clockdomains2430_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += clockdomain.o \
                                           clockdomain2xxx_3xxx.o \
-                                           clockdomains2xxx_3xxx_data.o
+                                           clockdomains2xxx_3xxx_data.o \
+                                           clockdomains3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += clockdomain.o \
                                           clockdomain44xx.o \
                                           clockdomains44xx_data.o
@@ -185,75 +187,62 @@ endif
 # Specific board support
 obj-$(CONFIG_MACH_OMAP_GENERIC)         += board-generic.o
 obj-$(CONFIG_MACH_OMAP_H4)              += board-h4.o
-obj-$(CONFIG_MACH_OMAP_2430SDP)         += board-2430sdp.o \
+obj-$(CONFIG_MACH_OMAP_2430SDP)         += board-2430sdp.o
-                                           hsmmc.o
 obj-$(CONFIG_MACH_OMAP_APOLLON)         += board-apollon.o
-obj-$(CONFIG_MACH_OMAP3_BEAGLE)         += board-omap3beagle.o \
+obj-$(CONFIG_MACH_OMAP3_BEAGLE)         += board-omap3beagle.o
-                                           hsmmc.o
+obj-$(CONFIG_MACH_DEVKIT8000)           += board-devkit8000.o
-obj-$(CONFIG_MACH_DEVKIT8000)           += board-devkit8000.o \
+obj-$(CONFIG_MACH_OMAP_LDP)             += board-ldp.o
-                                           hsmmc.o
+obj-$(CONFIG_MACH_OMAP3530_LV_SOM)      += board-omap3logic.o
-obj-$(CONFIG_MACH_OMAP_LDP)             += board-ldp.o \
+obj-$(CONFIG_MACH_OMAP3_TORPEDO)        += board-omap3logic.o
-                                           board-flash.o \
+obj-$(CONFIG_MACH_ENCORE)               += board-omap3encore.o
-                                           hsmmc.o
+obj-$(CONFIG_MACH_OVERO)                += board-overo.o
-obj-$(CONFIG_MACH_OMAP3530_LV_SOM)      += board-omap3logic.o \
+obj-$(CONFIG_MACH_OMAP3EVM)             += board-omap3evm.o
-                                           hsmmc.o
+obj-$(CONFIG_MACH_OMAP3_PANDORA)        += board-omap3pandora.o
-obj-$(CONFIG_MACH_OMAP3_TORPEDO)        += board-omap3logic.o \
+obj-$(CONFIG_MACH_OMAP_3430SDP)         += board-3430sdp.o
-                                           hsmmc.o
-obj-$(CONFIG_MACH_OVERO)                += board-overo.o \
-                                           hsmmc.o
-obj-$(CONFIG_MACH_OMAP3EVM)             += board-omap3evm.o \
-                                           hsmmc.o
-obj-$(CONFIG_MACH_OMAP3_PANDORA)        += board-omap3pandora.o \
-                                           hsmmc.o
-obj-$(CONFIG_MACH_OMAP_3430SDP)         += board-3430sdp.o \
-                                           hsmmc.o \
-                                           board-flash.o
 obj-$(CONFIG_MACH_NOKIA_N8X0)           += board-n8x0.o
 obj-$(CONFIG_MACH_NOKIA_RM680)          += board-rm680.o \
-                                           sdram-nokia.o \
+                                           sdram-nokia.o
-                                           hsmmc.o
 obj-$(CONFIG_MACH_NOKIA_RX51)           += board-rx51.o \
                                           sdram-nokia.o \
                                           board-rx51-peripherals.o \
-                                           board-rx51-video.o \
+                                           board-rx51-video.o
-                                           hsmmc.o
 obj-$(CONFIG_MACH_OMAP_ZOOM2)           += board-zoom.o \
                                           board-zoom-peripherals.o \
                                           board-zoom-display.o \
-                                           board-flash.o \
-                                           hsmmc.o \
                                           board-zoom-debugboard.o
 obj-$(CONFIG_MACH_OMAP_ZOOM3)           += board-zoom.o \
                                           board-zoom-peripherals.o \
                                           board-zoom-display.o \
-                                           board-flash.o \
-                                           hsmmc.o \
                                           board-zoom-debugboard.o
 obj-$(CONFIG_MACH_OMAP_3630SDP)         += board-3630sdp.o \
                                           board-zoom-peripherals.o \
-                                           board-zoom-display.o \
+                                           board-zoom-display.o
-                                           board-flash.o \
+obj-$(CONFIG_MACH_CM_T35)               += board-cm-t35.o
-                                           hsmmc.o
-obj-$(CONFIG_MACH_CM_T35)               += board-cm-t35.o \
-                                           hsmmc.o
 obj-$(CONFIG_MACH_CM_T3517)             += board-cm-t3517.o
-obj-$(CONFIG_MACH_IGEP0020)             += board-igep0020.o \
+obj-$(CONFIG_MACH_IGEP0020)             += board-igep0020.o
-                                           hsmmc.o
+obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK)      += board-omap3touchbook.o
-obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK)      += board-omap3touchbook.o \
+obj-$(CONFIG_MACH_OMAP_4430SDP)         += board-4430sdp.o
-                                           hsmmc.o
+obj-$(CONFIG_MACH_OMAP4_PANDA)          += board-omap4panda.o
-obj-$(CONFIG_MACH_OMAP_4430SDP)         += board-4430sdp.o \
-                                           hsmmc.o
+obj-$(CONFIG_MACH_PCM049)               += board-omap4pcm049.o
-obj-$(CONFIG_MACH_OMAP4_PANDA)          += board-omap4panda.o \
-                                           hsmmc.o
 obj-$(CONFIG_MACH_OMAP3517EVM)          += board-am3517evm.o
 obj-$(CONFIG_MACH_CRANEBOARD)           += board-am3517crane.o
-obj-$(CONFIG_MACH_SBC3530)              += board-omap3stalker.o \
+obj-$(CONFIG_MACH_SBC3530)              += board-omap3stalker.o
-                                           hsmmc.o
 obj-$(CONFIG_MACH_TI8168EVM)            += board-ti8168evm.o
 # Platform specific device init code
+omap-flash-$(CONFIG_MTD_NAND_OMAP2)     := board-flash.o
+omap-flash-$(CONFIG_MTD_ONENAND_OMAP2)  := board-flash.o
+obj-y                                   += $(omap-flash-y) $(omap-flash-m)
+omap-hsmmc-$(CONFIG_MMC_OMAP_HS)        := hsmmc.o
+obj-y                                   += $(omap-hsmmc-m) $(omap-hsmmc-y)
 usbfs-$(CONFIG_ARCH_OMAP_OTG)           := usb-fs.o
 obj-y                                   += $(usbfs-m) $(usbfs-y)
 obj-y                                   += usb-musb.o
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index f8ce84b69eb1..d704f0ac328d 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -192,12 +192,6 @@ static inline void board_smc91x_init(void)
 #endif
-static void __init omap_2430sdp_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
 static struct regulator_consumer_supply sdp2430_vmmc1_supplies[] = {
        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
 };
@@ -284,6 +278,7 @@ static void __init omap_2430sdp_init(void)
        platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices));
        omap_serial_init();
+        omap_sdrc_init(NULL, NULL);
        omap2_hsmmc_init(mmc);
        omap2_usbfs_init(&sdp2430_usb_config);
@@ -299,18 +294,12 @@ static void __init omap_2430sdp_init(void)
        sdp2430_display_init();
 }
-static void __init omap_2430sdp_map_io(void)
-{
-        omap2_set_globals_243x();
-        omap243x_map_common_io();
-}
 MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
        /* Maintainer: Syed Khasim - Texas Instruments Inc */
        .atag_offset    = 0x100,
        .reserve        = omap_reserve,
-        .map_io         = omap_2430sdp_map_io,
+        .map_io         = omap243x_map_io,
-        .init_early     = omap_2430sdp_init_early,
+        .init_early     = omap2430_init_early,
        .init_irq       = omap2_init_irq,
        .init_machine   = omap_2430sdp_init,
        .timer          = &omap2_timer,
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 204beddcb949..77142c13fa13 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -224,12 +224,6 @@ static struct omap_dss_board_info sdp3430_dss_data = {
 static struct omap_board_config_kernel sdp3430_config[] __initdata = {
 };
-static void __init omap_3430sdp_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL);
-}
 static struct omap2_hsmmc_info mmc[] = {
        {
                .mmc            = 1,
@@ -718,6 +712,7 @@ static void __init omap_3430sdp_init(void)
                gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV1;
        omap_ads7846_init(1, gpio_pendown, 310, NULL);
        board_serial_init();
+        omap_sdrc_init(hyb18m512160af6_sdrc_params, NULL);
        usb_musb_init(NULL);
        board_smc91x_init();
        board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
@@ -731,7 +726,7 @@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
        .atag_offset    = 0x100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = omap_3430sdp_init_early,
+        .init_early     = omap3430_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = omap_3430sdp_init,
        .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index 8b5b5aa751ed..f552305162fc 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -70,13 +70,6 @@ static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
 static struct omap_board_config_kernel sdp_config[] __initdata = {
 };
-static void __init omap_sdp_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params,
-                                  h8mbx00u0mer0em_sdrc_params);
-}
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
        { .reg_offset = OMAP_MUX_TERMINATOR },
@@ -207,6 +200,8 @@ static void __init omap_sdp_init(void)
        omap_board_config = sdp_config;
        omap_board_config_size = ARRAY_SIZE(sdp_config);
        zoom_peripherals_init();
+        omap_sdrc_init(h8mbx00u0mer0em_sdrc_params,
+                                  h8mbx00u0mer0em_sdrc_params);
        zoom_display_init();
        board_smc91x_init();
        board_flash_init(sdp_flash_partitions, chip_sel_sdp, NAND_BUSWIDTH_16);
@@ -218,7 +213,7 @@ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
        .atag_offset    = 0x100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = omap_sdp_init_early,
+        .init_early     = omap3630_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = omap_sdp_init,
        .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 484cec54882a..515646886b59 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -133,7 +133,7 @@ static const int sdp4430_keymap[] = {
        KEY(7, 6, KEY_OK),
        KEY(7, 7, KEY_DOWN),
 };
-static struct omap_device_pad keypad_pads[] __initdata = {
+static struct omap_device_pad keypad_pads[] = {
        {       .name   = "kpd_col1.kpd_col1",
                .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
        },
@@ -379,12 +379,6 @@ static struct platform_device *sdp4430_devices[] __initdata = {
        &sdp4430_vbat,
 };
-static void __init omap_4430sdp_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
 static struct omap_musb_board_data musb_board_data = {
        .interface_type         = MUSB_INTERFACE_UTMI,
        .mode                   = MUSB_OTG,
@@ -961,6 +955,7 @@ static void __init omap_4430sdp_init(void)
        omap_sfh7741prox_init();
        platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
        board_serial_init();
+        omap_sdrc_init(NULL, NULL);
        omap4_sdp4430_wifi_init();
        omap4_twl6030_hsmmc_init(mmc);
@@ -982,18 +977,12 @@ static void __init omap_4430sdp_init(void)
        omap_4430sdp_display_init();
 }
-static void __init omap_4430sdp_map_io(void)
-{
-        omap2_set_globals_443x();
-        omap44xx_map_common_io();
-}
 MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
        /* Maintainer: Santosh Shilimkar - Texas Instruments Inc */
        .atag_offset    = 0x100,
        .reserve        = omap_reserve,
-        .map_io         = omap_4430sdp_map_io,
+        .map_io         = omap4_map_io,
-        .init_early     = omap_4430sdp_init_early,
+        .init_early     = omap4430_init_early,
        .init_irq       = gic_init_irq,
        .init_machine   = omap_4430sdp_init,
        .timer          = &omap4_timer,
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index db110fdb8b2c..7834536ab416 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -47,12 +47,6 @@ static struct omap_board_mux board_mux[] __initdata = {
 };
 #endif
-static void __init am3517_crane_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
 static struct usbhs_omap_board_data usbhs_bdata __initdata = {
        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
@@ -70,6 +64,7 @@ static void __init am3517_crane_init(void)
        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
        omap_serial_init();
+        omap_sdrc_init(NULL, NULL);
        omap_board_config = am3517_crane_config;
        omap_board_config_size = ARRAY_SIZE(am3517_crane_config);
@@ -101,7 +96,7 @@ MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
        .atag_offset    = 0x100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = am3517_crane_init_early,
+        .init_early     = am35xx_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = am3517_crane_init,
        .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index ab10f75984d8..d314f033c9df 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -362,11 +362,6 @@ static struct omap_dss_board_info am3517_evm_dss_data = {
 /*
 * Board initialization
 */
-static void __init am3517_evm_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
 static struct omap_musb_board_data musb_board_data = {
        .interface_type         = MUSB_INTERFACE_ULPI,
@@ -469,6 +464,7 @@ static void __init am3517_evm_init(void)
        am3517_evm_i2c_init();
        omap_display_init(&am3517_evm_dss_data);
        omap_serial_init();
+        omap_sdrc_init(NULL, NULL);
        /* Configure GPIO for EHCI port */
        omap_mux_init_gpio(57, OMAP_PIN_OUTPUT);
@@ -493,7 +489,7 @@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
        .atag_offset    = 0x100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = am3517_evm_init_early,
+        .init_early     = am35xx_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = am3517_evm_init,
        .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index ad55351e0cab..de8134b7f580 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -284,12 +284,6 @@ static struct omap_dss_board_info apollon_dss_data = {
        .default_device = &apollon_lcd_device,
 };
-static void __init omap_apollon_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
 static struct gpio apollon_gpio_leds[] __initdata = {
        { LED0_GPIO13, GPIOF_OUT_INIT_LOW, "LED0" }, /* LED0 - AA10 */
        { LED1_GPIO14, GPIOF_OUT_INIT_LOW, "LED1" }, /* LED1 - AA6  */
@@ -349,22 +343,16 @@ static void __init omap_apollon_init(void)
         */
        platform_add_devices(apollon_devices, ARRAY_SIZE(apollon_devices));
        omap_serial_init();
+        omap_sdrc_init(NULL, NULL);
        omap_display_init(&apollon_dss_data);
 }
-static void __init omap_apollon_map_io(void)
-{
-        omap2_set_globals_242x();
-        omap242x_map_common_io();
-}
 MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
        /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
        .atag_offset    = 0x100,
        .reserve        = omap_reserve,
-        .map_io         = omap_apollon_map_io,
+        .map_io         = omap242x_map_io,
-        .init_early     = omap_apollon_init_early,
+        .init_early     = omap2420_init_early,
        .init_irq       = omap2_init_irq,
        .init_machine   = omap_apollon_init,
        .timer          = &omap2_timer,
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 6e0f0d2e39bc..bd1bcacb40f9 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -471,13 +471,6 @@ static void __init cm_t35_init_i2c(void)
        omap3_pmic_init("tps65930", &cm_t35_twldata);
 }
-static void __init cm_t35_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
-                             mt46h32m32lf6_sdrc_params);
-}
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
        /* nCS and IRQ for CM-T35 ethernet */
@@ -610,6 +603,8 @@ static void __init cm_t3x_common_init(void)
        omap_board_config_size = ARRAY_SIZE(cm_t35_config);
        omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
        omap_serial_init();
+        omap_sdrc_init(mt46h32m32lf6_sdrc_params,
+                             mt46h32m32lf6_sdrc_params);
        cm_t35_init_i2c();
        omap_ads7846_init(1, CM_T35_GPIO_PENDOWN, 0, NULL);
        cm_t35_init_ethernet();
@@ -637,7 +632,7 @@ MACHINE_START(CM_T35, "Compulab CM-T35")
        .atag_offset    = 0x100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = cm_t35_init_early,
+        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = cm_t35_init,
        .timer          = &omap3_timer,
@@ -647,7 +642,7 @@ MACHINE_START(CM_T3730, "Compulab CM-T3730")
        .atag_offset    = 0x100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = cm_t35_init_early,
+        .init_early     = omap3630_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = cm_t3730_init,
        .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index aed9c29f9fae..3f4dc6626845 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -251,12 +251,6 @@ static inline void cm_t3517_init_nand(void) {}
 static struct omap_board_config_kernel cm_t3517_config[] __initdata = {
 };
-static void __init cm_t3517_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
        /* GPIO186 - Green LED */
@@ -289,6 +283,7 @@ static void __init cm_t3517_init(void)
 {
        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
        omap_serial_init();
+        omap_sdrc_init(NULL, NULL);
        omap_board_config = cm_t3517_config;
        omap_board_config_size = ARRAY_SIZE(cm_t3517_config);
        cm_t3517_init_leds();
@@ -302,7 +297,7 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517")
        .atag_offset    = 0x100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = cm_t3517_init_early,
+        .init_early     = am35xx_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = cm_t3517_init,
        .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index d9bfe54917e4..42918940c530 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -397,19 +397,6 @@ static struct platform_device keys_gpio = {
        },
 };
-static void __init devkit8000_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
-                                  mt46h32m32lf6_sdrc_params);
-}
-static void __init devkit8000_init_irq(void)
-{
-        omap3_init_irq();
-}
 #define OMAP_DM9000_BASE        0x2c000000
 static struct resource omap_dm9000_resources[] = {
@@ -645,6 +632,8 @@ static void __init devkit8000_init(void)
 {
        omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
        omap_serial_init();
+        omap_sdrc_init(mt46h32m32lf6_sdrc_params,
+                                  mt46h32m32lf6_sdrc_params);
        omap_dm9000_init();
@@ -670,8 +659,8 @@ MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
        .atag_offset    = 0x100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = devkit8000_init_early,
+        .init_early     = omap35xx_init_early,
-        .init_irq       = devkit8000_init_irq,
+        .init_irq       = omap3_init_irq,
        .init_machine   = devkit8000_init,
        .timer          = &omap3_secure_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index aa1b0cbe19d2..30a6f527510c 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -148,11 +148,6 @@ __init board_nand_init(struct mtd_partition *nand_parts,
        board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs;
        gpmc_nand_init(&board_nand_data);
 }
-#else
-void
-__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs, int nand_type)
-{
-}
 #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
 /**
diff --git a/arch/arm/mach-omap2/board-flash.h b/arch/arm/mach-omap2/board-flash.h
index c240a3f8d163..d25503a98417 100644
--- a/arch/arm/mach-omap2/board-flash.h
+++ b/arch/arm/mach-omap2/board-flash.h
@@ -24,7 +24,26 @@ struct flash_partitions {
        int nr_parts;
 };
+#if defined(CONFIG_MTD_NAND_OMAP2) || \
+                defined(CONFIG_MTD_NAND_OMAP2_MODULE) || \
+                defined(CONFIG_MTD_ONENAND_OMAP2) || \
+                defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
 extern void board_flash_init(struct flash_partitions [],
                                char chip_sel[][GPMC_CS_NUM], int nand_type);
+#else
+static inline void board_flash_init(struct flash_partitions part[],
+                                char chip_sel[][GPMC_CS_NUM], int nand_type)
+{
+}
+#endif
+#if defined(CONFIG_MTD_NAND_OMAP2) || \
+                defined(CONFIG_MTD_NAND_OMAP2_MODULE)
 extern void board_nand_init(struct mtd_partition *nand_parts,
                                        u8 nr_parts, u8 cs, int nand_type);
+#else
+static inline void board_nand_init(struct mtd_partition *nand_parts,
+                                        u8 nr_parts, u8 cs, int nand_type)
+{
+}
+#endif
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 4431ad364565..0cc9094e5ee0 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -1,75 +1,157 @@
 /*
- * linux/arch/arm/mach-omap2/board-generic.c
- *
 * Copyright (C) 2005 Nokia Corporation
 * Author: Paul Mundt <paul.mundt@nokia.com>
 *
- * Modified from mach-omap/omap1/board-generic.c
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
 *
- * Code for generic OMAP2 board. Should work on many OMAP2 systems where
+ * Modified from the original mach-omap/omap2/board-generic.c did by Paul
- * the bootloader passes the board-specific data to the kernel.
+ * to support the OMAP2+ device tree boards with an unique board file.
- * Do not put any board specific code to this file; create a new machine
- * type if you need custom low-level initializations.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-#include <linux/gpio.h>
+#include <linux/io.h>
-#include <linux/kernel.h>
+#include <linux/of_platform.h>
-#include <linux/init.h>
+#include <linux/irqdomain.h>
-#include <linux/device.h>
+#include <linux/i2c/twl.h>
 #include <mach/hardware.h>
-#include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <plat/usb.h>
 #include <plat/board.h>
 #include <plat/common.h>
+#include <mach/omap4-common.h>
+#include "common-board-devices.h"
+/*
+ * XXX: Still needed to boot until the i2c & twl driver is adapted to
+ * device-tree
+ */
+static struct twl4030_platform_data sdp4430_twldata = {
+        .irq_base       = TWL6030_IRQ_BASE,
+        .irq_end        = TWL6030_IRQ_END,
+};
-static struct omap_board_config_kernel generic_config[] = {
+static void __init omap4_i2c_init(void)
+{
+        omap4_pmic_init("twl6030", &sdp4430_twldata);
+}
+static struct twl4030_platform_data beagle_twldata = {
+        .irq_base       = TWL4030_IRQ_BASE,
+        .irq_end        = TWL4030_IRQ_END,
 };
-static void __init omap_generic_init_early(void)
+static void __init omap3_i2c_init(void)
 {
-        omap2_init_common_infrastructure();
+        omap3_pmic_init("twl4030", &beagle_twldata);
-        omap2_init_common_devices(NULL, NULL);
 }
+static struct of_device_id omap_dt_match_table[] __initdata = {
+        { .compatible = "simple-bus", },
+        { .compatible = "ti,omap-infra", },
+        { }
+};
+static struct of_device_id intc_match[] __initdata = {
+        { .compatible = "ti,omap3-intc", },
+        { .compatible = "arm,cortex-a9-gic", },
+        { }
+};
 static void __init omap_generic_init(void)
 {
+        struct device_node *node = of_find_matching_node(NULL, intc_match);
+        if (node)
+                irq_domain_add_simple(node, 0);
        omap_serial_init();
-        omap_board_config = generic_config;
+        omap_sdrc_init(NULL, NULL);
-        omap_board_config_size = ARRAY_SIZE(generic_config);
+        of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
+}
+static void __init omap4_init(void)
+{
+        omap4_i2c_init();
+        omap_generic_init();
 }
-static void __init omap_generic_map_io(void)
+static void __init omap3_init(void)
 {
-        if (cpu_is_omap242x()) {
+        omap3_i2c_init();
-                omap2_set_globals_242x();
+        omap_generic_init();
-                omap242x_map_common_io();
-        } else if (cpu_is_omap243x()) {
-                omap2_set_globals_243x();
-                omap243x_map_common_io();
-        } else if (cpu_is_omap34xx()) {
-                omap2_set_globals_3xxx();
-                omap34xx_map_common_io();
-        } else if (cpu_is_omap44xx()) {
-                omap2_set_globals_443x();
-                omap44xx_map_common_io();
-        }
 }
-/* XXX This machine entry name should be updated */
+#if defined(CONFIG_SOC_OMAP2420)
-MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
+static const char *omap242x_boards_compat[] __initdata = {
-        /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
+        "ti,omap2420",
+        NULL,
+};
+DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
+        .atag_offset    = 0x100,
+        .reserve        = omap_reserve,
+        .map_io         = omap242x_map_io,
+        .init_early     = omap2420_init_early,
+        .init_irq       = omap2_init_irq,
+        .init_machine   = omap_generic_init,
+        .timer          = &omap2_timer,
+        .dt_compat      = omap242x_boards_compat,
+MACHINE_END
+#endif
+#if defined(CONFIG_SOC_OMAP2430)
+static const char *omap243x_boards_compat[] __initdata = {
+        "ti,omap2430",
+        NULL,
+};
+DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
        .atag_offset    = 0x100,
        .reserve        = omap_reserve,
-        .map_io         = omap_generic_map_io,
+        .map_io         = omap243x_map_io,
-        .init_early     = omap_generic_init_early,
+        .init_early     = omap2430_init_early,
        .init_irq       = omap2_init_irq,
        .init_machine   = omap_generic_init,
        .timer          = &omap2_timer,
+        .dt_compat      = omap243x_boards_compat,
+MACHINE_END
+#endif
+#if defined(CONFIG_ARCH_OMAP3)
+static const char *omap3_boards_compat[] __initdata = {
+        "ti,omap3",
+        NULL,
+};
+DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
+        .atag_offset    = 0x100,
+        .reserve        = omap_reserve,
+        .map_io         = omap3_map_io,
+        .init_early     = omap3430_init_early,
+        .init_irq       = omap3_init_irq,
+        .init_machine   = omap3_init,
+        .timer          = &omap3_timer,
+        .dt_compat      = omap3_boards_compat,
+MACHINE_END
+#endif
+#if defined(CONFIG_ARCH_OMAP4)
+static const char *omap4_boards_compat[] __initdata = {
+        "ti,omap4",
+        NULL,
+};
+DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
+        .atag_offset    = 0x100,
+        .reserve        = omap_reserve,
+        .map_io         = omap4_map_io,
+        .init_early     = omap4430_init_early,
+        .init_irq       = gic_init_irq,
+        .init_machine   = omap4_init,
+        .timer          = &omap4_timer,
+        .dt_compat      = omap4_boards_compat,
 MACHINE_END
+#endif
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 8fcf79628ca1..c12666ee7017 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -300,17 +300,6 @@ static struct omap_usb_config h4_usb_config __initdata = {
        .hmc_mode       = 0x00,         /* 0:dev|otg 1:disable 2:disable */
 };
-static void __init omap_h4_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
-static void __init omap_h4_init_irq(void)
-{
-        omap2_init_irq();
-}
 static struct at24_platform_data m24c01 = {
        .byte_len       = SZ_1K / 8,
        .page_size      = 16,
@@ -378,24 +367,19 @@ static void __init omap_h4_init(void)
        platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices));
        omap2_usbfs_init(&h4_usb_config);
        omap_serial_init();
+        omap_sdrc_init(NULL, NULL);
        h4_init_flash();
        omap_display_init(&h4_dss_data);
 }
-static void __init omap_h4_map_io(void)
-{
-        omap2_set_globals_242x();
-        omap242x_map_common_io();
-}
 MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
        /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
        .atag_offset    = 0x100,
        .reserve        = omap_reserve,
-        .map_io         = omap_h4_map_io,
+        .map_io         = omap242x_map_io,
-        .init_early     = omap_h4_init_early,
+        .init_early     = omap2420_init_early,
-        .init_irq       = omap_h4_init_irq,
+        .init_irq       = omap2_init_irq,
        .init_machine   = omap_h4_init,
        .timer          = &omap2_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 96f9ef34d2fb..d0a3f78a9b69 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -491,13 +491,6 @@ static struct platform_device *igep_devices[] __initdata = {
        &igep_vwlan_device,
 };
-static void __init igep_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(m65kxxxxam_sdrc_params,
-                                  m65kxxxxam_sdrc_params);
-}
 static int igep2_keymap[] = {
        KEY(0, 0, KEY_LEFT),
        KEY(0, 1, KEY_RIGHT),
@@ -650,6 +643,8 @@ static void __init igep_init(void)
        igep_i2c_init();
        platform_add_devices(igep_devices, ARRAY_SIZE(igep_devices));
        omap_serial_init();
+        omap_sdrc_init(m65kxxxxam_sdrc_params,
+                                  m65kxxxxam_sdrc_params);
        usb_musb_init(NULL);
        igep_flash_init();
@@ -675,7 +670,7 @@ MACHINE_START(IGEP0020, "IGEP v2 board")
        .atag_offset    = 0x100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = igep_init_early,
+        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = igep_init,
        .timer          = &omap3_timer,
@@ -685,7 +680,7 @@ MACHINE_START(IGEP0030, "IGEP OMAP3 module")
        .atag_offset    = 0x100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = igep_init_early,
+        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = igep_init,
        .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index f8f8a68a4899..e179da0c4da5 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -251,12 +251,6 @@ static void __init ldp_display_init(void)
        omap_display_init(&ldp_dss_data);
 }
-static void __init omap_ldp_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
 static int ldp_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio)
 {
        int r;
@@ -425,6 +419,7 @@ static void __init omap_ldp_init(void)
        platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices));
        omap_ads7846_init(1, 54, 310, NULL);
        omap_serial_init();
+        omap_sdrc_init(NULL, NULL);
        usb_musb_init(NULL);
        board_nand_init(ldp_nand_partitions,
                ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0);
@@ -437,7 +432,7 @@ MACHINE_START(OMAP_LDP, "OMAP LDP board")
        .atag_offset    = 0x100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = omap_ldp_init_early,
+        .init_early     = omap3430_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = omap_ldp_init,
        .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 6ce748154f24..e9d5f4a3d064 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -616,18 +616,6 @@ static struct i2c_board_info n810_i2c_board_info_2[] __initdata = {
        },
 };
-static void __init n8x0_map_io(void)
-{
-        omap2_set_globals_242x();
-        omap242x_map_common_io();
-}
-static void __init n8x0_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
        /* I2S codec port pins for McBSP block */
@@ -689,6 +677,7 @@ static void __init n8x0_init_machine(void)
                i2c_register_board_info(2, n810_i2c_board_info_2,
                                        ARRAY_SIZE(n810_i2c_board_info_2));
        board_serial_init();
+        omap_sdrc_init(NULL, NULL);
        gpmc_onenand_init(board_onenand_data);
        n8x0_mmc_init();
        n8x0_usb_init();
@@ -697,8 +686,8 @@ static void __init n8x0_init_machine(void)
 MACHINE_START(NOKIA_N800, "Nokia N800")
        .atag_offset    = 0x100,
        .reserve        = omap_reserve,
-        .map_io         = n8x0_map_io,
+        .map_io         = omap242x_map_io,
-        .init_early     = n8x0_init_early,
+        .init_early     = omap2420_init_early,
        .init_irq       = omap2_init_irq,
        .init_machine   = n8x0_init_machine,
        .timer          = &omap2_timer,
@@ -707,8 +696,8 @@ MACHINE_END
 MACHINE_START(NOKIA_N810, "Nokia N810")
        .atag_offset    = 0x100,
        .reserve        = omap_reserve,
-        .map_io         = n8x0_map_io,
+        .map_io         = omap242x_map_io,
-        .init_early     = n8x0_init_early,
+        .init_early     = omap2420_init_early,
        .init_irq       = omap2_init_irq,
        .init_machine   = n8x0_init_machine,
        .timer          = &omap2_timer,
@@ -717,8 +706,8 @@ MACHINE_END
 MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
        .atag_offset    = 0x100,
        .reserve        = omap_reserve,
-        .map_io         = n8x0_map_io,
+        .map_io         = omap242x_map_io,
-        .init_early     = n8x0_init_early,
+        .init_early     = omap2420_init_early,
        .init_irq       = omap2_init_irq,
        .init_machine   = n8x0_init_machine,
        .timer          = &omap2_timer,
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 928933ba28ce..70261bcda3f9 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -444,18 +444,6 @@ static struct platform_device keys_gpio = {
        },
 };
-static void __init omap3_beagle_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
-                                  mt46h32m32lf6_sdrc_params);
-}
-static void __init omap3_beagle_init_irq(void)
-{
-        omap3_init_irq();
-}
 static struct platform_device *omap3_beagle_devices[] __initdata = {
        &leds_gpio,
        &keys_gpio,
@@ -493,8 +481,8 @@ static void __init beagle_opp_init(void)
        if (cpu_is_omap3630()) {
                struct device *mpu_dev, *iva_dev;
-                mpu_dev = omap2_get_mpuss_device();
+                mpu_dev = omap_device_get_by_hwmod_name("mpu");
-                iva_dev = omap2_get_iva_device();
+                iva_dev = omap_device_get_by_hwmod_name("iva");
                if (!mpu_dev || !iva_dev) {
                        pr_err("%s: Aiee.. no mpu/dsp devices? %p %p\n",
@@ -534,6 +522,8 @@ static void __init omap3_beagle_init(void)
                        ARRAY_SIZE(omap3_beagle_devices));
        omap_display_init(&beagle_dss_data);
        omap_serial_init();
+        omap_sdrc_init(mt46h32m32lf6_sdrc_params,
+                                  mt46h32m32lf6_sdrc_params);
        omap_mux_init_gpio(170, OMAP_PIN_INPUT);
        /* REVISIT leave DVI powered down until it's needed ... */
@@ -560,8 +550,8 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
        .atag_offset    = 0x100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = omap3_beagle_init_early,
+        .init_early     = omap3_init_early,
-        .init_irq       = omap3_beagle_init_irq,
+        .init_irq       = omap3_init_irq,
        .init_machine   = omap3_beagle_init,
        .timer          = &omap3_secure_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 0d5a9e46a6af..2d24e287e8c1 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -519,12 +519,6 @@ static int __init omap3_evm_i2c_init(void)
 static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
 };
-static void __init omap3_evm_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);
-}
 static struct usbhs_omap_board_data usbhs_bdata __initdata = {
        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
@@ -639,6 +633,7 @@ static void __init omap3_evm_init(void)
        omap_display_init(&omap3_evm_dss_data);
        omap_serial_init();
+        omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL);
        /* OMAP3EVM uses ISP1504 phy and so register nop transceiver */
        usb_nop_xceiv_register();
@@ -683,7 +678,7 @@ MACHINE_START(OMAP3EVM, "OMAP3 EVM")
        .atag_offset    = 0x100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = omap3_evm_init_early,
+        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = omap3_evm_init,
        .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index 01354a214caf..7c0f193f246d 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -182,12 +182,6 @@ static inline void __init board_smsc911x_init(void)
        gpmc_smsc911x_init(&board_smsc911x_data);
 }
-static void __init omap3logic_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
        { .reg_offset = OMAP_MUX_TERMINATOR },
@@ -200,6 +194,7 @@ static void __init omap3logic_init(void)
        omap3torpedo_fix_pbias_voltage();
        omap3logic_i2c_init();
        omap_serial_init();
+        omap_sdrc_init(NULL, NULL);
        board_mmc_init();
        board_smsc911x_init();
@@ -211,7 +206,7 @@ static void __init omap3logic_init(void)
 MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
        .atag_offset    = 0x100,
        .map_io         = omap3_map_io,
-        .init_early     = omap3logic_init_early,
+        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = omap3logic_init,
        .timer          = &omap3_timer,
@@ -220,7 +215,7 @@ MACHINE_END
 MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
        .atag_offset    = 0x100,
        .map_io         = omap3_map_io,
-        .init_early     = omap3logic_init_early,
+        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = omap3logic_init,
        .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index cca523eb73b4..f7811f4cfc3d 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -525,13 +525,6 @@ static struct spi_board_info omap3pandora_spi_board_info[] __initdata = {
        }
 };
-static void __init omap3pandora_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
-                                  mt46h32m32lf6_sdrc_params);
-}
 static void __init pandora_wl1251_init(void)
 {
        struct wl12xx_platform_data pandora_wl1251_pdata;
@@ -593,6 +586,8 @@ static void __init omap3pandora_init(void)
                        ARRAY_SIZE(omap3pandora_devices));
        omap_display_init(&pandora_dss_data);
        omap_serial_init();
+        omap_sdrc_init(mt46h32m32lf6_sdrc_params,
+                                  mt46h32m32lf6_sdrc_params);
        spi_register_board_info(omap3pandora_spi_board_info,
                        ARRAY_SIZE(omap3pandora_spi_board_info));
        omap_ads7846_init(1, OMAP3_PANDORA_TS_GPIO, 0, NULL);
@@ -609,7 +604,7 @@ MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
        .atag_offset    = 0x100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = omap3pandora_init_early,
+        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = omap3pandora_init,
        .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index 4732589ad97e..ddb7d6663c6d 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -394,17 +394,6 @@ static int __init omap3_stalker_i2c_init(void)
 static struct omap_board_config_kernel omap3_stalker_config[] __initdata = {
 };
-static void __init omap3_stalker_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);
-}
-static void __init omap3_stalker_init_irq(void)
-{
-        omap3_init_irq();
-}
 static struct platform_device *omap3_stalker_devices[] __initdata = {
        &keys_gpio,
 };
@@ -444,6 +433,7 @@ static void __init omap3_stalker_init(void)
        omap_display_init(&omap3_stalker_dss_data);
        omap_serial_init();
+        omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL);
        usb_musb_init(NULL);
        usbhs_init(&usbhs_bdata);
        omap_ads7846_init(1, OMAP3_STALKER_TS_GPIO, 310, NULL);
@@ -462,8 +452,8 @@ MACHINE_START(SBC3530, "OMAP3 STALKER")
        /* Maintainer: Jason Lam -lzg@ema-tech.com */
        .atag_offset            = 0x100,
        .map_io                 = omap3_map_io,
-        .init_early             = omap3_stalker_init_early,
+        .init_early             = omap35xx_init_early,
-        .init_irq               = omap3_stalker_init_irq,
+        .init_irq               = omap3_init_irq,
        .init_machine           = omap3_stalker_init,
        .timer                  = &omap3_secure_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index abb68913e047..a2d0d1971e27 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -311,18 +311,6 @@ static struct omap_board_mux board_mux[] __initdata = {
 };
 #endif
-static void __init omap3_touchbook_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
-                                  mt46h32m32lf6_sdrc_params);
-}
-static void __init omap3_touchbook_init_irq(void)
-{
-        omap3_init_irq();
-}
 static struct platform_device *omap3_touchbook_devices[] __initdata = {
        &leds_gpio,
        &keys_gpio,
@@ -367,6 +355,8 @@ static void __init omap3_touchbook_init(void)
        platform_add_devices(omap3_touchbook_devices,
                        ARRAY_SIZE(omap3_touchbook_devices));
        omap_serial_init();
+        omap_sdrc_init(mt46h32m32lf6_sdrc_params,
+                                  mt46h32m32lf6_sdrc_params);
        omap_mux_init_gpio(170, OMAP_PIN_INPUT);
        /* REVISIT leave DVI powered down until it's needed ... */
@@ -389,8 +379,8 @@ MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
        .atag_offset    = 0x100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = omap3_touchbook_init_early,
+        .init_early     = omap3430_init_early,
-        .init_irq       = omap3_touchbook_init_irq,
+        .init_irq       = omap3_init_irq,
        .init_machine   = omap3_touchbook_init,
        .timer          = &omap3_secure_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index ed38d8fd090f..a8c2c4263e38 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -95,12 +95,6 @@ static struct platform_device *panda_devices[] __initdata = {
        &wl1271_device,
 };
-static void __init omap4_panda_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
 static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
@@ -569,24 +563,19 @@ static void __init omap4_panda_init(void)
        platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
        platform_device_register(&omap_vwlan_device);
        board_serial_init();
+        omap_sdrc_init(NULL, NULL);
        omap4_twl6030_hsmmc_init(mmc);
        omap4_ehci_init();
        usb_musb_init(&musb_board_data);
        omap4_panda_display_init();
 }
-static void __init omap4_panda_map_io(void)
-{
-        omap2_set_globals_443x();
-        omap44xx_map_common_io();
-}
 MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
        /* Maintainer: David Anders - Texas Instruments Inc */
        .atag_offset    = 0x100,
        .reserve        = omap_reserve,
-        .map_io         = omap4_panda_map_io,
+        .map_io         = omap4_map_io,
-        .init_early     = omap4_panda_init_early,
+        .init_early     = omap4430_init_early,
        .init_irq       = gic_init_irq,
        .init_machine   = omap4_panda_init,
        .timer          = &omap4_timer,
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index ec0f60c1cb7c..4cf7aeabab86 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -479,13 +479,6 @@ static int __init overo_spi_init(void)
        return 0;
 }
-static void __init overo_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
-                                  mt46h32m32lf6_sdrc_params);
-}
 static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
        .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
@@ -515,6 +508,8 @@ static void __init overo_init(void)
        overo_i2c_init();
        omap_display_init(&overo_dss_data);
        omap_serial_init();
+        omap_sdrc_init(mt46h32m32lf6_sdrc_params,
+                                  mt46h32m32lf6_sdrc_params);
        omap_nand_flash_init(0, overo_nand_partitions,
                             ARRAY_SIZE(overo_nand_partitions));
        usb_musb_init(NULL);
@@ -565,7 +560,7 @@ MACHINE_START(OVERO, "Gumstix Overo")
        .atag_offset    = 0x100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = overo_init_early,
+        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = overo_init,
        .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index 9a8ce239ba9e..616fb39763b0 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -123,15 +123,6 @@ static void __init rm680_peripherals_init(void)
        omap2_hsmmc_init(mmc);
 }
-static void __init rm680_init_early(void)
-{
-        struct omap_sdrc_params *sdrc_params;
-        omap2_init_common_infrastructure();
-        sdrc_params = nokia_get_sdram_timings();
-        omap2_init_common_devices(sdrc_params, sdrc_params);
-}
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
        { .reg_offset = OMAP_MUX_TERMINATOR },
@@ -140,23 +131,23 @@ static struct omap_board_mux board_mux[] __initdata = {
 static void __init rm680_init(void)
 {
+        struct omap_sdrc_params *sdrc_params;
        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
        omap_serial_init();
+        sdrc_params = nokia_get_sdram_timings();
+        omap_sdrc_init(sdrc_params, sdrc_params);
        usb_musb_init(NULL);
        rm680_peripherals_init();
 }
-static void __init rm680_map_io(void)
-{
-        omap2_set_globals_3xxx();
-        omap34xx_map_common_io();
-}
 MACHINE_START(NOKIA_RM680, "Nokia RM-680 board")
        .atag_offset    = 0x100,
        .reserve        = omap_reserve,
-        .map_io         = rm680_map_io,
+        .map_io         = omap3_map_io,
-        .init_early     = rm680_init_early,
+        .init_early     = omap3630_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = rm680_init,
        .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index faa2a8e28de5..4af7c4b2881a 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -79,15 +79,6 @@ static struct cpuidle_params rx51_cpuidle_params[] = {
        {7505 + 15274, 484329, 1},
 };
-static void __init rx51_init_early(void)
-{
-        struct omap_sdrc_params *sdrc_params;
-        omap2_init_common_infrastructure();
-        sdrc_params = nokia_get_sdram_timings();
-        omap2_init_common_devices(sdrc_params, sdrc_params);
-}
 extern void __init rx51_peripherals_init(void);
 #ifdef CONFIG_OMAP_MUX
@@ -104,9 +95,15 @@ static struct omap_musb_board_data musb_board_data = {
 static void __init rx51_init(void)
 {
+        struct omap_sdrc_params *sdrc_params;
        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
        omap3_pm_init_cpuidle(rx51_cpuidle_params);
        omap_serial_init();
+        sdrc_params = nokia_get_sdram_timings();
+        omap_sdrc_init(sdrc_params, sdrc_params);
        usb_musb_init(&musb_board_data);
        rx51_peripherals_init();
@@ -117,12 +114,6 @@ static void __init rx51_init(void)
        platform_device_register(&leds_gpio);
 }
-static void __init rx51_map_io(void)
-{
-        omap2_set_globals_3xxx();
-        omap34xx_map_common_io();
-}
 static void __init rx51_reserve(void)
 {
        rx51_video_mem_init();
@@ -133,8 +124,8 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
        /* Maintainer: Lauri Leukkunen <lauri.leukkunen@nokia.com> */
        .atag_offset    = 0x100,
        .reserve        = rx51_reserve,
-        .map_io         = rx51_map_io,
+        .map_io         = omap3_map_io,
-        .init_early     = rx51_init_early,
+        .init_early     = omap3430_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = rx51_init,
        .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
index e41958acb6b6..e6ee8842285c 100644
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -27,22 +27,16 @@
 static struct omap_board_config_kernel ti8168_evm_config[] __initdata = {
 };
-static void __init ti8168_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
 static void __init ti8168_evm_init(void)
 {
        omap_serial_init();
+        omap_sdrc_init(NULL, NULL);
        omap_board_config = ti8168_evm_config;
        omap_board_config_size = ARRAY_SIZE(ti8168_evm_config);
 }
 static void __init ti8168_evm_map_io(void)
 {
-        omap2_set_globals_ti816x();
        omapti816x_map_common_io();
 }
@@ -50,7 +44,7 @@ MACHINE_START(TI8168EVM, "ti8168evm")
        /* Maintainer: Texas Instruments */
        .atag_offset    = 0x100,
        .map_io         = ti8168_evm_map_io,
-        .init_early     = ti8168_init_early,
+        .init_early     = ti816x_init_early,
        .init_irq       = ti816x_init_irq,
        .timer          = &omap3_timer,
        .init_machine   = ti8168_evm_init,
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index 72f1db4863e5..be6684dc4f55 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -34,17 +34,6 @@
 #define ZOOM3_EHCI_RESET_GPIO           64
-static void __init omap_zoom_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        if (machine_is_omap_zoom2())
-                omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
-                                          mt46h32m32lf6_sdrc_params);
-        else if (machine_is_omap_zoom3())
-                omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params,
-                                          h8mbx00u0mer0em_sdrc_params);
-}
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
        /* WLAN IRQ - GPIO 162 */
@@ -129,6 +118,14 @@ static void __init omap_zoom_init(void)
                                                ZOOM_NAND_CS, NAND_BUSWIDTH_16);
        zoom_debugboard_init();
        zoom_peripherals_init();
+        if (machine_is_omap_zoom2())
+                omap_sdrc_init(mt46h32m32lf6_sdrc_params,
+                                          mt46h32m32lf6_sdrc_params);
+        else if (machine_is_omap_zoom3())
+                omap_sdrc_init(h8mbx00u0mer0em_sdrc_params,
+                                          h8mbx00u0mer0em_sdrc_params);
        zoom_display_init();
 }
@@ -136,7 +133,7 @@ MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
        .atag_offset    = 0x100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = omap_zoom_init_early,
+        .init_early     = omap3430_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = omap_zoom_init,
        .timer          = &omap3_timer,
@@ -146,7 +143,7 @@ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
        .atag_offset    = 0x100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = omap_zoom_init_early,
+        .init_early     = omap3630_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = omap_zoom_init,
        .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index debc040872f1..14a6277dd184 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -1898,6 +1898,54 @@ static struct omap_clk omap2420_clks[] = {
        CLK(NULL,       "pka_ick",      &pka_ick,       CK_242X),
        CLK(NULL,       "usb_fck",      &usb_fck,       CK_242X),
        CLK("musb-hdrc",        "fck",  &osc_ck,        CK_242X),
+        CLK("omap_timer.1",     "fck",  &gpt1_fck,      CK_242X),
+        CLK("omap_timer.2",     "fck",  &gpt2_fck,      CK_242X),
+        CLK("omap_timer.3",     "fck",  &gpt3_fck,      CK_242X),
+        CLK("omap_timer.4",     "fck",  &gpt4_fck,      CK_242X),
+        CLK("omap_timer.5",     "fck",  &gpt5_fck,      CK_242X),
+        CLK("omap_timer.6",     "fck",  &gpt6_fck,      CK_242X),
+        CLK("omap_timer.7",     "fck",  &gpt7_fck,      CK_242X),
+        CLK("omap_timer.8",     "fck",  &gpt8_fck,      CK_242X),
+        CLK("omap_timer.9",     "fck",  &gpt9_fck,      CK_242X),
+        CLK("omap_timer.10",    "fck",  &gpt10_fck,     CK_242X),
+        CLK("omap_timer.11",    "fck",  &gpt11_fck,     CK_242X),
+        CLK("omap_timer.12",    "fck",  &gpt12_fck,     CK_242X),
+        CLK("omap_timer.1",     "32k_ck",       &func_32k_ck,   CK_243X),
+        CLK("omap_timer.2",     "32k_ck",       &func_32k_ck,   CK_243X),
+        CLK("omap_timer.3",     "32k_ck",       &func_32k_ck,   CK_243X),
+        CLK("omap_timer.4",     "32k_ck",       &func_32k_ck,   CK_243X),
+        CLK("omap_timer.5",     "32k_ck",       &func_32k_ck,   CK_243X),
+        CLK("omap_timer.6",     "32k_ck",       &func_32k_ck,   CK_243X),
+        CLK("omap_timer.7",     "32k_ck",       &func_32k_ck,   CK_243X),
+        CLK("omap_timer.8",     "32k_ck",       &func_32k_ck,   CK_243X),
+        CLK("omap_timer.9",     "32k_ck",       &func_32k_ck,   CK_243X),
+        CLK("omap_timer.10",    "32k_ck",       &func_32k_ck,   CK_243X),
+        CLK("omap_timer.11",    "32k_ck",       &func_32k_ck,   CK_243X),
+        CLK("omap_timer.12",    "32k_ck",       &func_32k_ck,   CK_243X),
+        CLK("omap_timer.1",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.2",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.3",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.4",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.5",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.6",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.7",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.8",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.9",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.10",    "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.11",    "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.12",    "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.1",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.2",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.3",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.4",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.5",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.6",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.7",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.8",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.9",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.10",    "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.11",    "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.12",    "alt_ck",       &alt_ck,        CK_243X),
 };
 /*
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index 96a942e42db1..ea6717cfa3c8 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -1998,6 +1998,54 @@ static struct omap_clk omap2430_clks[] = {
        CLK(NULL,       "mdm_intc_ick", &mdm_intc_ick,  CK_243X),
        CLK("omap_hsmmc.0", "mmchsdb_fck",      &mmchsdb1_fck,  CK_243X),
        CLK("omap_hsmmc.1", "mmchsdb_fck",      &mmchsdb2_fck,  CK_243X),
+        CLK("omap_timer.1",     "fck",  &gpt1_fck,      CK_243X),
+        CLK("omap_timer.2",     "fck",  &gpt2_fck,      CK_243X),
+        CLK("omap_timer.3",     "fck",  &gpt3_fck,      CK_243X),
+        CLK("omap_timer.4",     "fck",  &gpt4_fck,      CK_243X),
+        CLK("omap_timer.5",     "fck",  &gpt5_fck,      CK_243X),
+        CLK("omap_timer.6",     "fck",  &gpt6_fck,      CK_243X),
+        CLK("omap_timer.7",     "fck",  &gpt7_fck,      CK_243X),
+        CLK("omap_timer.8",     "fck",  &gpt8_fck,      CK_243X),
+        CLK("omap_timer.9",     "fck",  &gpt9_fck,      CK_243X),
+        CLK("omap_timer.10",    "fck",  &gpt10_fck,     CK_243X),
+        CLK("omap_timer.11",    "fck",  &gpt11_fck,     CK_243X),
+        CLK("omap_timer.12",    "fck",  &gpt12_fck,     CK_243X),
+        CLK("omap_timer.1",     "32k_ck",  &func_32k_ck,   CK_243X),
+        CLK("omap_timer.2",     "32k_ck",  &func_32k_ck,   CK_243X),
+        CLK("omap_timer.3",     "32k_ck",  &func_32k_ck,   CK_243X),
+        CLK("omap_timer.4",     "32k_ck",  &func_32k_ck,   CK_243X),
+        CLK("omap_timer.5",     "32k_ck",  &func_32k_ck,   CK_243X),
+        CLK("omap_timer.6",     "32k_ck",  &func_32k_ck,   CK_243X),
+        CLK("omap_timer.7",     "32k_ck",  &func_32k_ck,   CK_243X),
+        CLK("omap_timer.8",     "32k_ck",  &func_32k_ck,   CK_243X),
+        CLK("omap_timer.9",     "32k_ck",  &func_32k_ck,   CK_243X),
+        CLK("omap_timer.10",    "32k_ck",  &func_32k_ck,   CK_243X),
+        CLK("omap_timer.11",    "32k_ck",  &func_32k_ck,   CK_243X),
+        CLK("omap_timer.12",    "32k_ck",  &func_32k_ck,   CK_243X),
+        CLK("omap_timer.1",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.2",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.3",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.4",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.5",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.6",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.7",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.8",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.9",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.10",    "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.11",    "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.12",    "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.1",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.2",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.3",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.4",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.5",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.6",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.7",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.8",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.9",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.10",    "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.11",    "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.12",    "alt_ck",       &alt_ck,        CK_243X),
 };
 /*
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index b9b844683147..65dd363163bc 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3464,6 +3464,42 @@ static struct omap_clk omap3xxx_clks[] = {
        CLK("musb-am35x",       "fck",          &hsotgusb_fck_am35xx,   CK_AM35XX),
        CLK(NULL,       "hecc_ck",      &hecc_ck,       CK_AM35XX),
        CLK(NULL,       "uart4_ick",    &uart4_ick_am35xx,      CK_AM35XX),
+        CLK("omap_timer.1",     "fck",  &gpt1_fck,      CK_3XXX),
+        CLK("omap_timer.2",     "fck",  &gpt2_fck,      CK_3XXX),
+        CLK("omap_timer.3",     "fck",  &gpt3_fck,      CK_3XXX),
+        CLK("omap_timer.4",     "fck",  &gpt4_fck,      CK_3XXX),
+        CLK("omap_timer.5",     "fck",  &gpt5_fck,      CK_3XXX),
+        CLK("omap_timer.6",     "fck",  &gpt6_fck,      CK_3XXX),
+        CLK("omap_timer.7",     "fck",  &gpt7_fck,      CK_3XXX),
+        CLK("omap_timer.8",     "fck",  &gpt8_fck,      CK_3XXX),
+        CLK("omap_timer.9",     "fck",  &gpt9_fck,      CK_3XXX),
+        CLK("omap_timer.10",    "fck",  &gpt10_fck,     CK_3XXX),
+        CLK("omap_timer.11",    "fck",  &gpt11_fck,     CK_3XXX),
+        CLK("omap_timer.12",    "fck",  &gpt12_fck,     CK_3XXX),
+        CLK("omap_timer.1",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
+        CLK("omap_timer.2",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
+        CLK("omap_timer.3",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
+        CLK("omap_timer.4",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
+        CLK("omap_timer.5",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
+        CLK("omap_timer.6",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
+        CLK("omap_timer.7",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
+        CLK("omap_timer.8",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
+        CLK("omap_timer.9",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
+        CLK("omap_timer.10",    "32k_ck",       &omap_32k_fck,  CK_3XXX),
+        CLK("omap_timer.11",    "32k_ck",       &omap_32k_fck,  CK_3XXX),
+        CLK("omap_timer.12",    "32k_ck",       &omap_32k_fck,  CK_3XXX),
+        CLK("omap_timer.1",     "sys_ck",       &sys_ck,        CK_3XXX),
+        CLK("omap_timer.2",     "sys_ck",       &sys_ck,        CK_3XXX),
+        CLK("omap_timer.3",     "sys_ck",       &sys_ck,        CK_3XXX),
+        CLK("omap_timer.4",     "sys_ck",       &sys_ck,        CK_3XXX),
+        CLK("omap_timer.5",     "sys_ck",       &sys_ck,        CK_3XXX),
+        CLK("omap_timer.6",     "sys_ck",       &sys_ck,        CK_3XXX),
+        CLK("omap_timer.7",     "sys_ck",       &sys_ck,        CK_3XXX),
+        CLK("omap_timer.8",     "sys_ck",       &sys_ck,        CK_3XXX),
+        CLK("omap_timer.9",     "sys_ck",       &sys_ck,        CK_3XXX),
+        CLK("omap_timer.10",    "sys_ck",       &sys_ck,        CK_3XXX),
+        CLK("omap_timer.11",    "sys_ck",       &sys_ck,        CK_3XXX),
+        CLK("omap_timer.12",    "sys_ck",       &sys_ck,        CK_3XXX),
 };
@@ -3472,7 +3508,16 @@ int __init omap3xxx_clk_init(void)
        struct omap_clk *c;
        u32 cpu_clkflg = 0;
-        if (cpu_is_omap3517()) {
+        /*
+         * 3505 must be tested before 3517, since 3517 returns true
+         * for both AM3517 chips and AM3517 family chips, which
+         * includes 3505.  Unfortunately there's no obvious family
+         * test for 3517/3505 :-(
+         */
+        if (cpu_is_omap3505()) {
+                cpu_mask = RATE_IN_34XX;
+                cpu_clkflg = CK_3505;
+        } else if (cpu_is_omap3517()) {
                cpu_mask = RATE_IN_34XX;
                cpu_clkflg = CK_3517;
        } else if (cpu_is_omap3505()) {
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index c0b6fbda3408..946bf04a956d 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -3363,6 +3363,39 @@ static struct omap_clk omap44xx_clks[] = {
        CLK("usbhs-omap.0",     "usbhost_ick",          &dummy_ck,              CK_443X),
        CLK("usbhs-omap.0",     "usbtll_fck",           &dummy_ck,      CK_443X),
        CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap_timer.1",     "fck",                  &timer1_fck,    CK_443X),
+        CLK("omap_timer.2",     "fck",                  &timer2_fck,    CK_443X),
+        CLK("omap_timer.3",     "fck",                  &timer3_fck,    CK_443X),
+        CLK("omap_timer.4",     "fck",                  &timer4_fck,    CK_443X),
+        CLK("omap_timer.5",     "fck",                  &timer5_fck,    CK_443X),
+        CLK("omap_timer.6",     "fck",                  &timer6_fck,    CK_443X),
+        CLK("omap_timer.7",     "fck",                  &timer7_fck,    CK_443X),
+        CLK("omap_timer.8",     "fck",                  &timer8_fck,    CK_443X),
+        CLK("omap_timer.9",     "fck",                  &timer9_fck,    CK_443X),
+        CLK("omap_timer.10",    "fck",                  &timer10_fck,   CK_443X),
+        CLK("omap_timer.11",    "fck",                  &timer11_fck,   CK_443X),
+        CLK("omap_timer.1",     "32k_ck",       &sys_32k_ck,    CK_443X),
+        CLK("omap_timer.2",     "32k_ck",       &sys_32k_ck,    CK_443X),
+        CLK("omap_timer.3",     "32k_ck",       &sys_32k_ck,    CK_443X),
+        CLK("omap_timer.4",     "32k_ck",       &sys_32k_ck,    CK_443X),
+        CLK("omap_timer.5",     "32k_ck",       &sys_32k_ck,    CK_443X),
+        CLK("omap_timer.6",     "32k_ck",       &sys_32k_ck,    CK_443X),
+        CLK("omap_timer.7",     "32k_ck",       &sys_32k_ck,    CK_443X),
+        CLK("omap_timer.8",     "32k_ck",       &sys_32k_ck,    CK_443X),
+        CLK("omap_timer.9",     "32k_ck",       &sys_32k_ck,    CK_443X),
+        CLK("omap_timer.10",    "32k_ck",       &sys_32k_ck,    CK_443X),
+        CLK("omap_timer.11",    "32k_ck",       &sys_32k_ck,    CK_443X),
+        CLK("omap_timer.1",     "sys_ck",       &sys_clkin_ck,  CK_443X),
+        CLK("omap_timer.2",     "sys_ck",       &sys_clkin_ck,  CK_443X),
+        CLK("omap_timer.3",     "sys_ck",       &sys_clkin_ck,  CK_443X),
+        CLK("omap_timer.4",     "sys_ck",       &sys_clkin_ck,  CK_443X),
+        CLK("omap_timer.9",     "sys_ck",       &sys_clkin_ck,  CK_443X),
+        CLK("omap_timer.10",    "sys_ck",       &sys_clkin_ck,  CK_443X),
+        CLK("omap_timer.11",    "sys_ck",       &sys_clkin_ck,  CK_443X),
+        CLK("omap_timer.5",     "sys_ck",       &syc_clk_div_ck,        CK_443X),
+        CLK("omap_timer.6",     "sys_ck",       &syc_clk_div_ck,        CK_443X),
+        CLK("omap_timer.7",     "sys_ck",       &syc_clk_div_ck,        CK_443X),
+        CLK("omap_timer.8",     "sys_ck",       &syc_clk_div_ck,        CK_443X),
 };
 int __init omap4xxx_clk_init(void)
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 8f0890685d7b..8480ee4344ea 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -73,9 +73,6 @@ static int _clkdm_register(struct clockdomain *clkdm)
        if (!clkdm || !clkdm->name)
                return -EINVAL;
-        if (!omap_chip_is(clkdm->omap_chip))
-                return -EINVAL;
        pwrdm = pwrdm_lookup(clkdm->pwrdm.name);
        if (!pwrdm) {
                pr_err("clockdomain: %s: powerdomain %s does not exist\n",
@@ -105,13 +102,10 @@ static struct clkdm_dep *_clkdm_deps_lookup(struct clockdomain *clkdm,
 {
        struct clkdm_dep *cd;
-        if (!clkdm || !deps || !omap_chip_is(clkdm->omap_chip))
+        if (!clkdm || !deps)
                return ERR_PTR(-EINVAL);
        for (cd = deps; cd->clkdm_name; cd++) {
-                if (!omap_chip_is(cd->omap_chip))
-                        continue;
                if (!cd->clkdm && cd->clkdm_name)
                        cd->clkdm = _clkdm_lookup(cd->clkdm_name);
@@ -148,9 +142,6 @@ static void _autodep_lookup(struct clkdm_autodep *autodep)
        if (!autodep)
                return;
-        if (!omap_chip_is(autodep->omap_chip))
-                return;
        clkdm = clkdm_lookup(autodep->clkdm.name);
        if (!clkdm) {
                pr_err("clockdomain: autodeps: clockdomain %s does not exist\n",
@@ -182,9 +173,6 @@ void _clkdm_add_autodeps(struct clockdomain *clkdm)
                if (IS_ERR(autodep->clkdm.ptr))
                        continue;
-                if (!omap_chip_is(autodep->omap_chip))
-                        continue;
                pr_debug("clockdomain: adding %s sleepdep/wkdep for "
                         "clkdm %s\n", autodep->clkdm.ptr->name,
                         clkdm->name);
@@ -216,9 +204,6 @@ void _clkdm_del_autodeps(struct clockdomain *clkdm)
                if (IS_ERR(autodep->clkdm.ptr))
                        continue;
-                if (!omap_chip_is(autodep->omap_chip))
-                        continue;
                pr_debug("clockdomain: removing %s sleepdep/wkdep for "
                         "clkdm %s\n", autodep->clkdm.ptr->name,
                         clkdm->name);
@@ -243,8 +228,6 @@ static void _resolve_clkdm_deps(struct clockdomain *clkdm,
        struct clkdm_dep *cd;
        for (cd = clkdm_deps; cd && cd->clkdm_name; cd++) {
-                if (!omap_chip_is(cd->omap_chip))
-                        continue;
                if (cd->clkdm)
                        continue;
                cd->clkdm = _clkdm_lookup(cd->clkdm_name);
@@ -257,43 +240,113 @@ static void _resolve_clkdm_deps(struct clockdomain *clkdm,
 /* Public functions */
 /**
- * clkdm_init - set up the clockdomain layer
+ * clkdm_register_platform_funcs - register clockdomain implementation fns
- * @clkdms: optional pointer to an array of clockdomains to register
+ * @co: func pointers for arch specific implementations
- * @init_autodeps: optional pointer to an array of autodeps to register
+ *
- * @custom_funcs: func pointers for arch specific implementations
+ * Register the list of function pointers used to implement the
- *
+ * clockdomain functions on different OMAP SoCs.  Should be called
- * Set up internal state.  If a pointer to an array of clockdomains
+ * before any other clkdm_register*() function.  Returns -EINVAL if
- * @clkdms was supplied, loop through the list of clockdomains,
+ * @co is null, -EEXIST if platform functions have already been
- * register all that are available on the current platform. Similarly,
+ * registered, or 0 upon success.
- * if a pointer to an array of clockdomain autodependencies
+ */
- * @init_autodeps was provided, register those.  No return value.
+int clkdm_register_platform_funcs(struct clkdm_ops *co)
+{
+        if (!co)
+                return -EINVAL;
+        if (arch_clkdm)
+                return -EEXIST;
+        arch_clkdm = co;
+        return 0;
+};
+/**
+ * clkdm_register_clkdms - register SoC clockdomains
+ * @cs: pointer to an array of struct clockdomain to register
+ *
+ * Register the clockdomains available on a particular OMAP SoC.  Must
+ * be called after clkdm_register_platform_funcs().  May be called
+ * multiple times.  Returns -EACCES if called before
+ * clkdm_register_platform_funcs(); -EINVAL if the argument @cs is
+ * null; or 0 upon success.
 */
-void clkdm_init(struct clockdomain **clkdms,
+int clkdm_register_clkdms(struct clockdomain **cs)
-                struct clkdm_autodep *init_autodeps,
-                struct clkdm_ops *custom_funcs)
 {
        struct clockdomain **c = NULL;
-        struct clockdomain *clkdm;
-        struct clkdm_autodep *autodep = NULL;
-        if (!custom_funcs)
+        if (!arch_clkdm)
-                WARN(1, "No custom clkdm functions registered\n");
+                return -EACCES;
-        else
-                arch_clkdm = custom_funcs;
+        if (!cs)
+                return -EINVAL;
+        for (c = cs; *c; c++)
+                _clkdm_register(*c);
+        return 0;
+}
+/**
+ * clkdm_register_autodeps - register autodeps (if required)
+ * @ia: pointer to a static array of struct clkdm_autodep to register
+ *
+ * Register clockdomain "automatic dependencies."  These are
+ * clockdomain wakeup and sleep dependencies that are automatically
+ * added whenever the first clock inside a clockdomain is enabled, and
+ * removed whenever the last clock inside a clockdomain is disabled.
+ * These are currently only used on OMAP3 devices, and are deprecated,
+ * since they waste energy.  However, until the OMAP2/3 IP block
+ * enable/disable sequence can be converted to match the OMAP4
+ * sequence, they are needed.
+ *
+ * Must be called only after all of the SoC clockdomains are
+ * registered, since the function will resolve autodep clockdomain
+ * names into clockdomain pointers.
+ *
+ * The struct clkdm_autodep @ia array must be static, as this function
+ * does not copy the array elements.
+ *
+ * Returns -EACCES if called before any clockdomains have been
+ * registered, -EINVAL if called with a null @ia argument, -EEXIST if
+ * autodeps have already been registered, or 0 upon success.
+ */
+int clkdm_register_autodeps(struct clkdm_autodep *ia)
+{
+        struct clkdm_autodep *a = NULL;
-        if (clkdms)
+        if (list_empty(&clkdm_list))
-                for (c = clkdms; *c; c++)
+                return -EACCES;
-                        _clkdm_register(*c);
+        if (!ia)
+                return -EINVAL;
-        autodeps = init_autodeps;
        if (autodeps)
-                for (autodep = autodeps; autodep->clkdm.ptr; autodep++)
+                return -EEXIST;
-                        _autodep_lookup(autodep);
+        autodeps = ia;
+        for (a = autodeps; a->clkdm.ptr; a++)
+                _autodep_lookup(a);
+        return 0;
+}
+/**
+ * clkdm_complete_init - set up the clockdomain layer
+ *
+ * Put all clockdomains into software-supervised mode; PM code should
+ * later enable hardware-supervised mode as appropriate.  Must be
+ * called after clkdm_register_clkdms().  Returns -EACCES if called
+ * before clkdm_register_clkdms(), or 0 upon success.
+ */
+int clkdm_complete_init(void)
+{
+        struct clockdomain *clkdm;
+        if (list_empty(&clkdm_list))
+                return -EACCES;
-        /*
-         * Put all clockdomains into software-supervised mode; PM code
-         * should later enable hardware-supervised mode as appropriate
-         */
        list_for_each_entry(clkdm, &clkdm_list, node) {
                if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
                        clkdm_wakeup(clkdm);
@@ -306,6 +359,8 @@ void clkdm_init(struct clockdomain **clkdms,
                _resolve_clkdm_deps(clkdm, clkdm->sleepdep_srcs);
                clkdm_clear_all_sleepdeps(clkdm);
        }
+        return 0;
 }
 /**
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 1e50c88b8a07..f7b58609bad8 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -45,7 +45,6 @@
 /**
 * struct clkdm_autodep - clkdm deps to add when entering/exiting hwsup mode
 * @clkdm: clockdomain to add wkdep+sleepdep on - set name member only
- * @omap_chip: OMAP chip types that this autodep is valid on
 *
 * A clockdomain that should have wkdeps and sleepdeps added when a
 * clockdomain should stay active in hwsup mode; and conversely,
@@ -60,14 +59,12 @@ struct clkdm_autodep {
                const char *name;
                struct clockdomain *ptr;
        } clkdm;
-        const struct omap_chip_id omap_chip;
 };
 /**
 * struct clkdm_dep - encode dependencies between clockdomains
 * @clkdm_name: clockdomain name
 * @clkdm: pointer to the struct clockdomain of @clkdm_name
- * @omap_chip: OMAP chip types that this dependency is valid on
 * @wkdep_usecount: Number of wakeup dependencies causing this clkdm to wake
 * @sleepdep_usecount: Number of sleep deps that could prevent clkdm from idle
 *
@@ -81,7 +78,6 @@ struct clkdm_dep {
        struct clockdomain *clkdm;
        atomic_t wkdep_usecount;
        atomic_t sleepdep_usecount;
-        const struct omap_chip_id omap_chip;
 };
 /* Possible flags for struct clockdomain._flags */
@@ -101,7 +97,6 @@ struct clkdm_dep {
 * @clkdm_offs: (OMAP4 only) CM clockdomain register offset
 * @wkdep_srcs: Clockdomains that can be told to wake this powerdomain up
 * @sleepdep_srcs: Clockdomains that can be told to keep this clkdm from inact
- * @omap_chip: OMAP chip types that this clockdomain is valid on
 * @usecount: Usecount tracking
 * @node: list_head to link all clockdomains together
 *
@@ -126,7 +121,6 @@ struct clockdomain {
        const u16 clkdm_offs;
        struct clkdm_dep *wkdep_srcs;
        struct clkdm_dep *sleepdep_srcs;
-        const struct omap_chip_id omap_chip;
        atomic_t usecount;
        struct list_head node;
        spinlock_t lock;
@@ -166,8 +160,11 @@ struct clkdm_ops {
        int     (*clkdm_clk_disable)(struct clockdomain *clkdm);
 };
-void clkdm_init(struct clockdomain **clkdms, struct clkdm_autodep *autodeps,
+int clkdm_register_platform_funcs(struct clkdm_ops *co);
-                        struct clkdm_ops *custom_funcs);
+int clkdm_register_autodeps(struct clkdm_autodep *ia);
+int clkdm_register_clkdms(struct clockdomain **c);
+int clkdm_complete_init(void);
 struct clockdomain *clkdm_lookup(const char *name);
 int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
@@ -195,7 +192,8 @@ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
 int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh);
 int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh);
-extern void __init omap2xxx_clockdomains_init(void);
+extern void __init omap242x_clockdomains_init(void);
+extern void __init omap243x_clockdomains_init(void);
 extern void __init omap3xxx_clockdomains_init(void);
 extern void __init omap44xx_clockdomains_init(void);
 extern void _clkdm_add_autodeps(struct clockdomain *clkdm);
@@ -205,4 +203,10 @@ extern struct clkdm_ops omap2_clkdm_operations;
 extern struct clkdm_ops omap3_clkdm_operations;
 extern struct clkdm_ops omap4_clkdm_operations;
+extern struct clkdm_dep gfx_24xx_wkdeps[];
+extern struct clkdm_dep dsp_24xx_wkdeps[];
+extern struct clockdomain wkup_common_clkdm;
+extern struct clockdomain prm_common_clkdm;
+extern struct clockdomain cm_common_clkdm;
 #endif
diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
index f740edb111f4..a0d68dbecfa3 100644
--- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
@@ -52,8 +52,6 @@ static int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
        u32 mask = 0;
        for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
-                if (!omap_chip_is(cd->omap_chip))
-                        continue;
                if (!cd->clkdm)
                        continue; /* only happens if data is erroneous */
@@ -98,8 +96,6 @@ static int omap3_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
        u32 mask = 0;
        for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
-                if (!omap_chip_is(cd->omap_chip))
-                        continue;
                if (!cd->clkdm)
                        continue; /* only happens if data is erroneous */
diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
index b43706aa08bd..935c7f03dab9 100644
--- a/arch/arm/mach-omap2/clockdomain44xx.c
+++ b/arch/arm/mach-omap2/clockdomain44xx.c
@@ -52,8 +52,6 @@ static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
        u32 mask = 0;
        for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
-                if (!omap_chip_is(cd->omap_chip))
-                        continue;
                if (!cd->clkdm)
                        continue; /* only happens if data is erroneous */
diff --git a/arch/arm/mach-omap2/clockdomains2420_data.c b/arch/arm/mach-omap2/clockdomains2420_data.c
new file mode 100644
index 000000000000..0ab8e46d5b2b
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains2420_data.c
@@ -0,0 +1,154 @@
+/*
+ * OMAP2420 clockdomains
+ *
+ * Copyright (C) 2008-2011 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
+ *
+ * Paul Walmsley, Jouni Högander
+ *
+ * This file contains clockdomains and clockdomain wakeup dependencies
+ * for OMAP2420 chips.  Some notes:
+ *
+ * A useful validation rule for struct clockdomain: Any clockdomain
+ * referenced by a wkdep_srcs must have a dep_bit assigned.  So
+ * wkdep_srcs are really just software-controllable dependencies.
+ * Non-software-controllable dependencies do exist, but they are not
+ * encoded below (yet).
+ *
+ * 24xx does not support programmable sleep dependencies (SLEEPDEP)
+ *
+ * The overly-specific dep_bit names are due to a bit name collision
+ * with CM_FCLKEN_{DSP,IVA2}.  The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
+ * value are the same for all powerdomains: 2
+ *
+ * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
+ * sanity check?
+ * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
+ */
+/*
+ * To-Do List
+ * -> Port the Sleep/Wakeup dependencies for the domains
+ *    from the Power domain framework
+ */
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include "clockdomain.h"
+#include "prm2xxx_3xxx.h"
+#include "cm2xxx_3xxx.h"
+#include "cm-regbits-24xx.h"
+#include "prm-regbits-24xx.h"
+/*
+ * Clockdomain dependencies for wkdeps
+ *
+ * XXX Hardware dependencies (e.g., dependencies that cannot be
+ * changed in software) are not included here yet, but should be.
+ */
+/* Wakeup dependency source arrays */
+/* 2420-specific possible wakeup dependencies */
+/* 2420 PM_WKDEP_MPU: CORE, DSP, WKUP */
+static struct clkdm_dep mpu_2420_wkdeps[] = {
+        { .clkdm_name = "core_l3_clkdm" },
+        { .clkdm_name = "core_l4_clkdm" },
+        { .clkdm_name = "dsp_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { NULL },
+};
+/* 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP */
+static struct clkdm_dep core_2420_wkdeps[] = {
+        { .clkdm_name = "dsp_clkdm" },
+        { .clkdm_name = "gfx_clkdm" },
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { NULL },
+};
+/*
+ * 2420-only clockdomains
+ */
+static struct clockdomain mpu_2420_clkdm = {
+        .name           = "mpu_clkdm",
+        .pwrdm          = { .name = "mpu_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP,
+        .wkdep_srcs     = mpu_2420_wkdeps,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
+};
+static struct clockdomain iva1_2420_clkdm = {
+        .name           = "iva1_clkdm",
+        .pwrdm          = { .name = "dsp_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .dep_bit        = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
+        .wkdep_srcs     = dsp_24xx_wkdeps,
+        .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
+};
+static struct clockdomain dsp_2420_clkdm = {
+        .name           = "dsp_clkdm",
+        .pwrdm          = { .name = "dsp_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
+};
+static struct clockdomain gfx_2420_clkdm = {
+        .name           = "gfx_clkdm",
+        .pwrdm          = { .name = "gfx_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .wkdep_srcs     = gfx_24xx_wkdeps,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
+};
+static struct clockdomain core_l3_2420_clkdm = {
+        .name           = "core_l3_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP,
+        .wkdep_srcs     = core_2420_wkdeps,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
+};
+static struct clockdomain core_l4_2420_clkdm = {
+        .name           = "core_l4_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP,
+        .wkdep_srcs     = core_2420_wkdeps,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
+};
+static struct clockdomain dss_2420_clkdm = {
+        .name           = "dss_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
+};
+static struct clockdomain *clockdomains_omap242x[] __initdata = {
+        &wkup_common_clkdm,
+        &cm_common_clkdm,
+        &prm_common_clkdm,
+        &mpu_2420_clkdm,
+        &iva1_2420_clkdm,
+        &dsp_2420_clkdm,
+        &gfx_2420_clkdm,
+        &core_l3_2420_clkdm,
+        &core_l4_2420_clkdm,
+        &dss_2420_clkdm,
+        NULL,
+};
+void __init omap242x_clockdomains_init(void)
+{
+        if (!cpu_is_omap242x())
+                return;
+        clkdm_register_platform_funcs(&omap2_clkdm_operations);
+        clkdm_register_clkdms(clockdomains_omap242x);
+        clkdm_complete_init();
+}
diff --git a/arch/arm/mach-omap2/clockdomains2430_data.c b/arch/arm/mach-omap2/clockdomains2430_data.c
new file mode 100644
index 000000000000..3645ed044890
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains2430_data.c
@@ -0,0 +1,181 @@
+/*
+ * OMAP2xxx clockdomains
+ *
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
+ *
+ * Paul Walmsley, Jouni Högander
+ *
+ * This file contains clockdomains and clockdomain wakeup dependencies
+ * for OMAP2xxx chips.  Some notes:
+ *
+ * A useful validation rule for struct clockdomain: Any clockdomain
+ * referenced by a wkdep_srcs must have a dep_bit assigned.  So
+ * wkdep_srcs are really just software-controllable dependencies.
+ * Non-software-controllable dependencies do exist, but they are not
+ * encoded below (yet).
+ *
+ * 24xx does not support programmable sleep dependencies (SLEEPDEP)
+ *
+ * The overly-specific dep_bit names are due to a bit name collision
+ * with CM_FCLKEN_{DSP,IVA2}.  The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
+ * value are the same for all powerdomains: 2
+ *
+ * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
+ * sanity check?
+ * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
+ */
+/*
+ * To-Do List
+ * -> Port the Sleep/Wakeup dependencies for the domains
+ *    from the Power domain framework
+ */
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include "clockdomain.h"
+#include "prm2xxx_3xxx.h"
+#include "cm2xxx_3xxx.h"
+#include "cm-regbits-24xx.h"
+#include "prm-regbits-24xx.h"
+/*
+ * Clockdomain dependencies for wkdeps
+ *
+ * XXX Hardware dependencies (e.g., dependencies that cannot be
+ * changed in software) are not included here yet, but should be.
+ */
+/* Wakeup dependency source arrays */
+/* 2430-specific possible wakeup dependencies */
+/* 2430 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP, MDM */
+static struct clkdm_dep core_2430_wkdeps[] = {
+        { .clkdm_name = "dsp_clkdm" },
+        { .clkdm_name = "gfx_clkdm" },
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { .clkdm_name = "mdm_clkdm" },
+        { NULL },
+};
+/* 2430 PM_WKDEP_MPU: CORE, DSP, WKUP, MDM */
+static struct clkdm_dep mpu_2430_wkdeps[] = {
+        { .clkdm_name = "core_l3_clkdm" },
+        { .clkdm_name = "core_l4_clkdm" },
+        { .clkdm_name = "dsp_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { .clkdm_name = "mdm_clkdm" },
+        { NULL },
+};
+/* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */
+static struct clkdm_dep mdm_2430_wkdeps[] = {
+        { .clkdm_name = "core_l3_clkdm" },
+        { .clkdm_name = "core_l4_clkdm" },
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { NULL },
+};
+/*
+ * 2430-only clockdomains
+ */
+static struct clockdomain mpu_2430_clkdm = {
+        .name           = "mpu_clkdm",
+        .pwrdm          = { .name = "mpu_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .wkdep_srcs     = mpu_2430_wkdeps,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
+};
+/* Another case of bit name collisions between several registers: EN_MDM */
+static struct clockdomain mdm_clkdm = {
+        .name           = "mdm_clkdm",
+        .pwrdm          = { .name = "mdm_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .dep_bit        = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
+        .wkdep_srcs     = mdm_2430_wkdeps,
+        .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
+};
+static struct clockdomain dsp_2430_clkdm = {
+        .name           = "dsp_clkdm",
+        .pwrdm          = { .name = "dsp_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .dep_bit        = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
+        .wkdep_srcs     = dsp_24xx_wkdeps,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
+};
+static struct clockdomain gfx_2430_clkdm = {
+        .name           = "gfx_clkdm",
+        .pwrdm          = { .name = "gfx_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .wkdep_srcs     = gfx_24xx_wkdeps,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
+};
+/*
+ * XXX add usecounting for clkdm dependencies, otherwise the presence
+ * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
+ * could cause trouble
+ */
+static struct clockdomain core_l3_2430_clkdm = {
+        .name           = "core_l3_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP,
+        .dep_bit        = OMAP24XX_EN_CORE_SHIFT,
+        .wkdep_srcs     = core_2430_wkdeps,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
+};
+/*
+ * XXX add usecounting for clkdm dependencies, otherwise the presence
+ * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
+ * could cause trouble
+ */
+static struct clockdomain core_l4_2430_clkdm = {
+        .name           = "core_l4_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP,
+        .dep_bit        = OMAP24XX_EN_CORE_SHIFT,
+        .wkdep_srcs     = core_2430_wkdeps,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
+};
+static struct clockdomain dss_2430_clkdm = {
+        .name           = "dss_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
+};
+static struct clockdomain *clockdomains_omap243x[] __initdata = {
+        &wkup_common_clkdm,
+        &cm_common_clkdm,
+        &prm_common_clkdm,
+        &mpu_2430_clkdm,
+        &mdm_clkdm,
+        &dsp_2430_clkdm,
+        &gfx_2430_clkdm,
+        &core_l3_2430_clkdm,
+        &core_l4_2430_clkdm,
+        &dss_2430_clkdm,
+        NULL,
+};
+void __init omap243x_clockdomains_init(void)
+{
+        if (!cpu_is_omap243x())
+                return;
+        clkdm_register_platform_funcs(&omap2_clkdm_operations);
+        clkdm_register_clkdms(clockdomains_omap243x);
+        clkdm_complete_init();
+}
diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
index 13bde95b6790..0a6a04897d89 100644
--- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
@@ -1,7 +1,7 @@
 /*
- * OMAP2/3 clockdomains
+ * OMAP2/3 clockdomain common data
 *
- * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ * Copyright (C) 2008-2011 Texas Instruments, Inc.
 * Copyright (C) 2008-2010 Nokia Corporation
 *
 * Paul Walmsley, Jouni Högander
@@ -51,374 +51,28 @@
 * changed in software) are not included here yet, but should be.
 */
-/* OMAP2/3-common wakeup dependencies */
-/*
- * 2420/2430 PM_WKDEP_GFX: CORE, MPU, WKUP
- * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
- * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
- * These can share data since they will never be present simultaneously
- * on the same device.
- */
-static struct clkdm_dep gfx_sgx_wkdeps[] = {
-        {
-                .clkdm_name = "core_l3_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "core_l4_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "iva2_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
-                                            CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "wkup_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
-                                            CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-/* 24XX-specific possible dependencies */
-#ifdef CONFIG_ARCH_OMAP2
 /* Wakeup dependency source arrays */
-/* 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP */
+/* 2xxx-specific possible dependencies */
-static struct clkdm_dep dsp_24xx_wkdeps[] = {
-        {
-                .clkdm_name = "core_l3_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "core_l4_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "wkup_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        { NULL },
-};
-/*
- * 2420 PM_WKDEP_MPU: CORE, DSP, WKUP
- * 2430 adds MDM
- */
-static struct clkdm_dep mpu_24xx_wkdeps[] = {
-        {
-                .clkdm_name = "core_l3_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "core_l4_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "dsp_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "wkup_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "mdm_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
-        },
-        { NULL },
-};
-/*
- * 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP
- * 2430 adds MDM
- */
-static struct clkdm_dep core_24xx_wkdeps[] = {
-        {
-                .clkdm_name = "dsp_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "gfx_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "wkup_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "mdm_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
-        },
-        { NULL },
-};
-#endif /* CONFIG_ARCH_OMAP2 */
-/* 2430-specific possible wakeup dependencies */
-#ifdef CONFIG_SOC_OMAP2430
+/* 2xxx PM_WKDEP_GFX: CORE, MPU, WKUP */
+struct clkdm_dep gfx_24xx_wkdeps[] = {
-/* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */
+        { .clkdm_name = "core_l3_clkdm" },
-static struct clkdm_dep mdm_2430_wkdeps[] = {
+        { .clkdm_name = "core_l4_clkdm" },
-        {
+        { .clkdm_name = "mpu_clkdm" },
-                .clkdm_name = "core_l3_clkdm",
+        { .clkdm_name = "wkup_clkdm" },
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "core_l4_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "wkup_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        { NULL },
-};
-#endif /* CONFIG_SOC_OMAP2430 */
-/* OMAP3-specific possible dependencies */
-#ifdef CONFIG_ARCH_OMAP3
-/* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */
-static struct clkdm_dep per_wkdeps[] = {
-        {
-                .clkdm_name = "core_l3_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "core_l4_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "iva2_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "wkup_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-/* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */
-static struct clkdm_dep usbhost_wkdeps[] = {
-        {
-                .clkdm_name = "core_l3_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "core_l4_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "iva2_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "wkup_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
        { NULL },
 };
-/* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */
+/* 2xxx PM_WKDEP_DSP: CORE, MPU, WKUP */
-static struct clkdm_dep mpu_3xxx_wkdeps[] = {
+struct clkdm_dep dsp_24xx_wkdeps[] = {
-        {
+        { .clkdm_name = "core_l3_clkdm" },
-                .clkdm_name = "core_l3_clkdm",
+        { .clkdm_name = "core_l4_clkdm" },
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        { .clkdm_name = "mpu_clkdm" },
-        },
+        { .clkdm_name = "wkup_clkdm" },
-        {
-                .clkdm_name = "core_l4_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "iva2_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "dss_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "per_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
        { NULL },
 };
-/* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */
-static struct clkdm_dep iva2_wkdeps[] = {
-        {
-                .clkdm_name = "core_l3_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "core_l4_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "wkup_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "dss_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "per_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-/* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */
-static struct clkdm_dep cam_wkdeps[] = {
-        {
-                .clkdm_name = "iva2_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "wkup_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-/* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */
-static struct clkdm_dep dss_wkdeps[] = {
-        {
-                .clkdm_name = "iva2_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "wkup_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-/* 3430: PM_WKDEP_NEON: MPU */
-static struct clkdm_dep neon_wkdeps[] = {
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-/* Sleep dependency source arrays for OMAP3-specific clkdms */
-/* 3430: CM_SLEEPDEP_DSS: MPU, IVA */
-static struct clkdm_dep dss_sleepdeps[] = {
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "iva2_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-/* 3430: CM_SLEEPDEP_PER: MPU, IVA */
-static struct clkdm_dep per_sleepdeps[] = {
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "iva2_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-/* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */
-static struct clkdm_dep usbhost_sleepdeps[] = {
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "iva2_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-/* 3430: CM_SLEEPDEP_CAM: MPU */
-static struct clkdm_dep cam_sleepdeps[] = {
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-/*
- * 3430ES1: CM_SLEEPDEP_GFX: MPU
- * 3430ES2: CM_SLEEPDEP_SGX: MPU
- * These can share data since they will never be present simultaneously
- * on the same device.
- */
-static struct clkdm_dep gfx_sgx_sleepdeps[] = {
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-#endif /* CONFIG_ARCH_OMAP3 */
 /*
 * OMAP2/3-common clockdomains
@@ -430,439 +84,18 @@ static struct clkdm_dep gfx_sgx_sleepdeps[] = {
 */
 /* This is an implicit clockdomain - it is never defined as such in TRM */
-static struct clockdomain wkup_clkdm = {
+struct clockdomain wkup_common_clkdm = {
        .name           = "wkup_clkdm",
        .pwrdm          = { .name = "wkup_pwrdm" },
        .dep_bit        = OMAP_EN_WKUP_SHIFT,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
 };
-static struct clockdomain prm_clkdm = {
+struct clockdomain prm_common_clkdm = {
        .name           = "prm_clkdm",
        .pwrdm          = { .name = "wkup_pwrdm" },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
 };
-static struct clockdomain cm_clkdm = {
+struct clockdomain cm_common_clkdm = {
        .name           = "cm_clkdm",
        .pwrdm          = { .name = "core_pwrdm" },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
 };
-/*
- * 2420-only clockdomains
- */
-#if defined(CONFIG_SOC_OMAP2420)
-static struct clockdomain mpu_2420_clkdm = {
-        .name           = "mpu_clkdm",
-        .pwrdm          = { .name = "mpu_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP,
-        .wkdep_srcs     = mpu_24xx_wkdeps,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
-};
-static struct clockdomain iva1_2420_clkdm = {
-        .name           = "iva1_clkdm",
-        .pwrdm          = { .name = "dsp_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .dep_bit        = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
-        .wkdep_srcs     = dsp_24xx_wkdeps,
-        .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
-};
-static struct clockdomain dsp_2420_clkdm = {
-        .name           = "dsp_clkdm",
-        .pwrdm          = { .name = "dsp_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
-};
-static struct clockdomain gfx_2420_clkdm = {
-        .name           = "gfx_clkdm",
-        .pwrdm          = { .name = "gfx_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .wkdep_srcs     = gfx_sgx_wkdeps,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
-};
-static struct clockdomain core_l3_2420_clkdm = {
-        .name           = "core_l3_clkdm",
-        .pwrdm          = { .name = "core_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP,
-        .wkdep_srcs     = core_24xx_wkdeps,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
-};
-static struct clockdomain core_l4_2420_clkdm = {
-        .name           = "core_l4_clkdm",
-        .pwrdm          = { .name = "core_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP,
-        .wkdep_srcs     = core_24xx_wkdeps,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
-};
-static struct clockdomain dss_2420_clkdm = {
-        .name           = "dss_clkdm",
-        .pwrdm          = { .name = "core_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
-};
-#endif   /* CONFIG_SOC_OMAP2420 */
-/*
- * 2430-only clockdomains
- */
-#if defined(CONFIG_SOC_OMAP2430)
-static struct clockdomain mpu_2430_clkdm = {
-        .name           = "mpu_clkdm",
-        .pwrdm          = { .name = "mpu_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .wkdep_srcs     = mpu_24xx_wkdeps,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
-};
-/* Another case of bit name collisions between several registers: EN_MDM */
-static struct clockdomain mdm_clkdm = {
-        .name           = "mdm_clkdm",
-        .pwrdm          = { .name = "mdm_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .dep_bit        = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
-        .wkdep_srcs     = mdm_2430_wkdeps,
-        .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
-};
-static struct clockdomain dsp_2430_clkdm = {
-        .name           = "dsp_clkdm",
-        .pwrdm          = { .name = "dsp_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .dep_bit        = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
-        .wkdep_srcs     = dsp_24xx_wkdeps,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
-};
-static struct clockdomain gfx_2430_clkdm = {
-        .name           = "gfx_clkdm",
-        .pwrdm          = { .name = "gfx_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .wkdep_srcs     = gfx_sgx_wkdeps,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
-};
-/*
- * XXX add usecounting for clkdm dependencies, otherwise the presence
- * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
- * could cause trouble
- */
-static struct clockdomain core_l3_2430_clkdm = {
-        .name           = "core_l3_clkdm",
-        .pwrdm          = { .name = "core_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP,
-        .dep_bit        = OMAP24XX_EN_CORE_SHIFT,
-        .wkdep_srcs     = core_24xx_wkdeps,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
-};
-/*
- * XXX add usecounting for clkdm dependencies, otherwise the presence
- * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
- * could cause trouble
- */
-static struct clockdomain core_l4_2430_clkdm = {
-        .name           = "core_l4_clkdm",
-        .pwrdm          = { .name = "core_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP,
-        .dep_bit        = OMAP24XX_EN_CORE_SHIFT,
-        .wkdep_srcs     = core_24xx_wkdeps,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
-};
-static struct clockdomain dss_2430_clkdm = {
-        .name           = "dss_clkdm",
-        .pwrdm          = { .name = "core_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
-};
-#endif    /* CONFIG_SOC_OMAP2430 */
-/*
- * OMAP3 clockdomains
- */
-#if defined(CONFIG_ARCH_OMAP3)
-static struct clockdomain mpu_3xxx_clkdm = {
-        .name           = "mpu_clkdm",
-        .pwrdm          = { .name = "mpu_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
-        .dep_bit        = OMAP3430_EN_MPU_SHIFT,
-        .wkdep_srcs     = mpu_3xxx_wkdeps,
-        .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-static struct clockdomain neon_clkdm = {
-        .name           = "neon_clkdm",
-        .pwrdm          = { .name = "neon_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .wkdep_srcs     = neon_wkdeps,
-        .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-static struct clockdomain iva2_clkdm = {
-        .name           = "iva2_clkdm",
-        .pwrdm          = { .name = "iva2_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .dep_bit        = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
-        .wkdep_srcs     = iva2_wkdeps,
-        .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-static struct clockdomain gfx_3430es1_clkdm = {
-        .name           = "gfx_clkdm",
-        .pwrdm          = { .name = "gfx_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .wkdep_srcs     = gfx_sgx_wkdeps,
-        .sleepdep_srcs  = gfx_sgx_sleepdeps,
-        .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
-};
-static struct clockdomain sgx_clkdm = {
-        .name           = "sgx_clkdm",
-        .pwrdm          = { .name = "sgx_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .wkdep_srcs     = gfx_sgx_wkdeps,
-        .sleepdep_srcs  = gfx_sgx_sleepdeps,
-        .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
-};
-/*
- * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
- * then that information was removed from the 34xx ES2+ TRM.  It is
- * unclear whether the core is still there, but the clockdomain logic
- * is there, and must be programmed to an appropriate state if the
- * CORE clockdomain is to become inactive.
- */
-static struct clockdomain d2d_clkdm = {
-        .name           = "d2d_clkdm",
-        .pwrdm          = { .name = "core_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-/*
- * XXX add usecounting for clkdm dependencies, otherwise the presence
- * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
- * could cause trouble
- */
-static struct clockdomain core_l3_3xxx_clkdm = {
-        .name           = "core_l3_clkdm",
-        .pwrdm          = { .name = "core_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP,
-        .dep_bit        = OMAP3430_EN_CORE_SHIFT,
-        .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-/*
- * XXX add usecounting for clkdm dependencies, otherwise the presence
- * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
- * could cause trouble
- */
-static struct clockdomain core_l4_3xxx_clkdm = {
-        .name           = "core_l4_clkdm",
-        .pwrdm          = { .name = "core_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP,
-        .dep_bit        = OMAP3430_EN_CORE_SHIFT,
-        .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-/* Another case of bit name collisions between several registers: EN_DSS */
-static struct clockdomain dss_3xxx_clkdm = {
-        .name           = "dss_clkdm",
-        .pwrdm          = { .name = "dss_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .dep_bit        = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
-        .wkdep_srcs     = dss_wkdeps,
-        .sleepdep_srcs  = dss_sleepdeps,
-        .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-static struct clockdomain cam_clkdm = {
-        .name           = "cam_clkdm",
-        .pwrdm          = { .name = "cam_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .wkdep_srcs     = cam_wkdeps,
-        .sleepdep_srcs  = cam_sleepdeps,
-        .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-static struct clockdomain usbhost_clkdm = {
-        .name           = "usbhost_clkdm",
-        .pwrdm          = { .name = "usbhost_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .wkdep_srcs     = usbhost_wkdeps,
-        .sleepdep_srcs  = usbhost_sleepdeps,
-        .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
-};
-static struct clockdomain per_clkdm = {
-        .name           = "per_clkdm",
-        .pwrdm          = { .name = "per_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .dep_bit        = OMAP3430_EN_PER_SHIFT,
-        .wkdep_srcs     = per_wkdeps,
-        .sleepdep_srcs  = per_sleepdeps,
-        .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-/*
- * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
- * switched of even if sdti is in use
- */
-static struct clockdomain emu_clkdm = {
-        .name           = "emu_clkdm",
-        .pwrdm          = { .name = "emu_pwrdm" },
-        .flags          = /* CLKDM_CAN_ENABLE_AUTO |  */CLKDM_CAN_SWSUP,
-        .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-static struct clockdomain dpll1_clkdm = {
-        .name           = "dpll1_clkdm",
-        .pwrdm          = { .name = "dpll1_pwrdm" },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-static struct clockdomain dpll2_clkdm = {
-        .name           = "dpll2_clkdm",
-        .pwrdm          = { .name = "dpll2_pwrdm" },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-static struct clockdomain dpll3_clkdm = {
-        .name           = "dpll3_clkdm",
-        .pwrdm          = { .name = "dpll3_pwrdm" },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-static struct clockdomain dpll4_clkdm = {
-        .name           = "dpll4_clkdm",
-        .pwrdm          = { .name = "dpll4_pwrdm" },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-static struct clockdomain dpll5_clkdm = {
-        .name           = "dpll5_clkdm",
-        .pwrdm          = { .name = "dpll5_pwrdm" },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
-};
-#endif   /* CONFIG_ARCH_OMAP3 */
-/*
- * Clockdomain hwsup dependencies (OMAP3 only)
- */
-static struct clkdm_autodep clkdm_autodeps[] = {
-        {
-                .clkdm     = { .name = "mpu_clkdm" },
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm     = { .name = "iva2_clkdm" },
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm     = { .name = NULL },
-        }
-};
-static struct clockdomain *clockdomains_omap2[] __initdata = {
-        &wkup_clkdm,
-        &cm_clkdm,
-        &prm_clkdm,
-#ifdef CONFIG_SOC_OMAP2420
-        &mpu_2420_clkdm,
-        &iva1_2420_clkdm,
-        &dsp_2420_clkdm,
-        &gfx_2420_clkdm,
-        &core_l3_2420_clkdm,
-        &core_l4_2420_clkdm,
-        &dss_2420_clkdm,
-#endif
-#ifdef CONFIG_SOC_OMAP2430
-        &mpu_2430_clkdm,
-        &mdm_clkdm,
-        &dsp_2430_clkdm,
-        &gfx_2430_clkdm,
-        &core_l3_2430_clkdm,
-        &core_l4_2430_clkdm,
-        &dss_2430_clkdm,
-#endif
-#ifdef CONFIG_ARCH_OMAP3
-        &mpu_3xxx_clkdm,
-        &neon_clkdm,
-        &iva2_clkdm,
-        &gfx_3430es1_clkdm,
-        &sgx_clkdm,
-        &d2d_clkdm,
-        &core_l3_3xxx_clkdm,
-        &core_l4_3xxx_clkdm,
-        &dss_3xxx_clkdm,
-        &cam_clkdm,
-        &usbhost_clkdm,
-        &per_clkdm,
-        &emu_clkdm,
-        &dpll1_clkdm,
-        &dpll2_clkdm,
-        &dpll3_clkdm,
-        &dpll4_clkdm,
-        &dpll5_clkdm,
-#endif
-        NULL,
-};
-void __init omap2xxx_clockdomains_init(void)
-{
-        clkdm_init(clockdomains_omap2, clkdm_autodeps, &omap2_clkdm_operations);
-}
-void __init omap3xxx_clockdomains_init(void)
-{
-        clkdm_init(clockdomains_omap2, clkdm_autodeps, &omap3_clkdm_operations);
-}
diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c
new file mode 100644
index 000000000000..b84e138d99c8
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c
@@ -0,0 +1,398 @@
+/*
+ * OMAP3xxx clockdomains
+ *
+ * Copyright (C) 2008-2011 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
+ *
+ * Paul Walmsley, Jouni Högander
+ *
+ * This file contains clockdomains and clockdomain wakeup/sleep
+ * dependencies for the OMAP3xxx chips.  Some notes:
+ *
+ * A useful validation rule for struct clockdomain: Any clockdomain
+ * referenced by a wkdep_srcs or sleepdep_srcs array must have a
+ * dep_bit assigned.  So wkdep_srcs/sleepdep_srcs are really just
+ * software-controllable dependencies.  Non-software-controllable
+ * dependencies do exist, but they are not encoded below (yet).
+ *
+ * The overly-specific dep_bit names are due to a bit name collision
+ * with CM_FCLKEN_{DSP,IVA2}.  The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
+ * value are the same for all powerdomains: 2
+ *
+ * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
+ * sanity check?
+ * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
+ */
+/*
+ * To-Do List
+ * -> Port the Sleep/Wakeup dependencies for the domains
+ *    from the Power domain framework
+ */
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include "clockdomain.h"
+#include "prm2xxx_3xxx.h"
+#include "cm2xxx_3xxx.h"
+#include "cm-regbits-34xx.h"
+#include "prm-regbits-34xx.h"
+/*
+ * Clockdomain dependencies for wkdeps/sleepdeps
+ *
+ * XXX Hardware dependencies (e.g., dependencies that cannot be
+ * changed in software) are not included here yet, but should be.
+ */
+/* OMAP3-specific possible dependencies */
+/*
+ * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
+ * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
+ */
+static struct clkdm_dep gfx_sgx_3xxx_wkdeps[] = {
+        { .clkdm_name = "iva2_clkdm", },
+        { .clkdm_name = "mpu_clkdm", },
+        { .clkdm_name = "wkup_clkdm", },
+        { NULL },
+};
+/* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */
+static struct clkdm_dep per_wkdeps[] = {
+        { .clkdm_name = "core_l3_clkdm" },
+        { .clkdm_name = "core_l4_clkdm" },
+        { .clkdm_name = "iva2_clkdm" },
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { NULL },
+};
+/* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */
+static struct clkdm_dep usbhost_wkdeps[] = {
+        { .clkdm_name = "core_l3_clkdm" },
+        { .clkdm_name = "core_l4_clkdm" },
+        { .clkdm_name = "iva2_clkdm" },
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { NULL },
+};
+/* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */
+static struct clkdm_dep mpu_3xxx_wkdeps[] = {
+        { .clkdm_name = "core_l3_clkdm" },
+        { .clkdm_name = "core_l4_clkdm" },
+        { .clkdm_name = "iva2_clkdm" },
+        { .clkdm_name = "dss_clkdm" },
+        { .clkdm_name = "per_clkdm" },
+        { NULL },
+};
+/* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */
+static struct clkdm_dep iva2_wkdeps[] = {
+        { .clkdm_name = "core_l3_clkdm" },
+        { .clkdm_name = "core_l4_clkdm" },
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { .clkdm_name = "dss_clkdm" },
+        { .clkdm_name = "per_clkdm" },
+        { NULL },
+};
+/* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */
+static struct clkdm_dep cam_wkdeps[] = {
+        { .clkdm_name = "iva2_clkdm" },
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { NULL },
+};
+/* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */
+static struct clkdm_dep dss_wkdeps[] = {
+        { .clkdm_name = "iva2_clkdm" },
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { NULL },
+};
+/* 3430: PM_WKDEP_NEON: MPU */
+static struct clkdm_dep neon_wkdeps[] = {
+        { .clkdm_name = "mpu_clkdm" },
+        { NULL },
+};
+/* Sleep dependency source arrays for OMAP3-specific clkdms */
+/* 3430: CM_SLEEPDEP_DSS: MPU, IVA */
+static struct clkdm_dep dss_sleepdeps[] = {
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "iva2_clkdm" },
+        { NULL },
+};
+/* 3430: CM_SLEEPDEP_PER: MPU, IVA */
+static struct clkdm_dep per_sleepdeps[] = {
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "iva2_clkdm" },
+        { NULL },
+};
+/* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */
+static struct clkdm_dep usbhost_sleepdeps[] = {
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "iva2_clkdm" },
+        { NULL },
+};
+/* 3430: CM_SLEEPDEP_CAM: MPU */
+static struct clkdm_dep cam_sleepdeps[] = {
+        { .clkdm_name = "mpu_clkdm" },
+        { NULL },
+};
+/*
+ * 3430ES1: CM_SLEEPDEP_GFX: MPU
+ * 3430ES2: CM_SLEEPDEP_SGX: MPU
+ * These can share data since they will never be present simultaneously
+ * on the same device.
+ */
+static struct clkdm_dep gfx_sgx_sleepdeps[] = {
+        { .clkdm_name = "mpu_clkdm" },
+        { NULL },
+};
+/*
+ * OMAP3 clockdomains
+ */
+static struct clockdomain mpu_3xxx_clkdm = {
+        .name           = "mpu_clkdm",
+        .pwrdm          = { .name = "mpu_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
+        .dep_bit        = OMAP3430_EN_MPU_SHIFT,
+        .wkdep_srcs     = mpu_3xxx_wkdeps,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
+};
+static struct clockdomain neon_clkdm = {
+        .name           = "neon_clkdm",
+        .pwrdm          = { .name = "neon_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .wkdep_srcs     = neon_wkdeps,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
+};
+static struct clockdomain iva2_clkdm = {
+        .name           = "iva2_clkdm",
+        .pwrdm          = { .name = "iva2_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .dep_bit        = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
+        .wkdep_srcs     = iva2_wkdeps,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
+};
+static struct clockdomain gfx_3430es1_clkdm = {
+        .name           = "gfx_clkdm",
+        .pwrdm          = { .name = "gfx_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .wkdep_srcs     = gfx_sgx_3xxx_wkdeps,
+        .sleepdep_srcs  = gfx_sgx_sleepdeps,
+        .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
+};
+static struct clockdomain sgx_clkdm = {
+        .name           = "sgx_clkdm",
+        .pwrdm          = { .name = "sgx_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .wkdep_srcs     = gfx_sgx_3xxx_wkdeps,
+        .sleepdep_srcs  = gfx_sgx_sleepdeps,
+        .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
+};
+/*
+ * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
+ * then that information was removed from the 34xx ES2+ TRM.  It is
+ * unclear whether the core is still there, but the clockdomain logic
+ * is there, and must be programmed to an appropriate state if the
+ * CORE clockdomain is to become inactive.
+ */
+static struct clockdomain d2d_clkdm = {
+        .name           = "d2d_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
+};
+/*
+ * XXX add usecounting for clkdm dependencies, otherwise the presence
+ * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
+ * could cause trouble
+ */
+static struct clockdomain core_l3_3xxx_clkdm = {
+        .name           = "core_l3_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP,
+        .dep_bit        = OMAP3430_EN_CORE_SHIFT,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
+};
+/*
+ * XXX add usecounting for clkdm dependencies, otherwise the presence
+ * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
+ * could cause trouble
+ */
+static struct clockdomain core_l4_3xxx_clkdm = {
+        .name           = "core_l4_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP,
+        .dep_bit        = OMAP3430_EN_CORE_SHIFT,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
+};
+/* Another case of bit name collisions between several registers: EN_DSS */
+static struct clockdomain dss_3xxx_clkdm = {
+        .name           = "dss_clkdm",
+        .pwrdm          = { .name = "dss_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .dep_bit        = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
+        .wkdep_srcs     = dss_wkdeps,
+        .sleepdep_srcs  = dss_sleepdeps,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
+};
+static struct clockdomain cam_clkdm = {
+        .name           = "cam_clkdm",
+        .pwrdm          = { .name = "cam_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .wkdep_srcs     = cam_wkdeps,
+        .sleepdep_srcs  = cam_sleepdeps,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
+};
+static struct clockdomain usbhost_clkdm = {
+        .name           = "usbhost_clkdm",
+        .pwrdm          = { .name = "usbhost_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .wkdep_srcs     = usbhost_wkdeps,
+        .sleepdep_srcs  = usbhost_sleepdeps,
+        .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
+};
+static struct clockdomain per_clkdm = {
+        .name           = "per_clkdm",
+        .pwrdm          = { .name = "per_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .dep_bit        = OMAP3430_EN_PER_SHIFT,
+        .wkdep_srcs     = per_wkdeps,
+        .sleepdep_srcs  = per_sleepdeps,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
+};
+/*
+ * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
+ * switched of even if sdti is in use
+ */
+static struct clockdomain emu_clkdm = {
+        .name           = "emu_clkdm",
+        .pwrdm          = { .name = "emu_pwrdm" },
+        .flags          = /* CLKDM_CAN_ENABLE_AUTO |  */CLKDM_CAN_SWSUP,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
+};
+static struct clockdomain dpll1_clkdm = {
+        .name           = "dpll1_clkdm",
+        .pwrdm          = { .name = "dpll1_pwrdm" },
+};
+static struct clockdomain dpll2_clkdm = {
+        .name           = "dpll2_clkdm",
+        .pwrdm          = { .name = "dpll2_pwrdm" },
+};
+static struct clockdomain dpll3_clkdm = {
+        .name           = "dpll3_clkdm",
+        .pwrdm          = { .name = "dpll3_pwrdm" },
+};
+static struct clockdomain dpll4_clkdm = {
+        .name           = "dpll4_clkdm",
+        .pwrdm          = { .name = "dpll4_pwrdm" },
+};
+static struct clockdomain dpll5_clkdm = {
+        .name           = "dpll5_clkdm",
+        .pwrdm          = { .name = "dpll5_pwrdm" },
+};
+/*
+ * Clockdomain hwsup dependencies
+ */
+static struct clkdm_autodep clkdm_autodeps[] = {
+        {
+                .clkdm = { .name = "mpu_clkdm" },
+        },
+        {
+                .clkdm = { .name = "iva2_clkdm" },
+        },
+        {
+                .clkdm = { .name = NULL },
+        }
+};
+/*
+ *
+ */
+static struct clockdomain *clockdomains_omap3430_common[] __initdata = {
+        &wkup_common_clkdm,
+        &cm_common_clkdm,
+        &prm_common_clkdm,
+        &mpu_3xxx_clkdm,
+        &neon_clkdm,
+        &iva2_clkdm,
+        &d2d_clkdm,
+        &core_l3_3xxx_clkdm,
+        &core_l4_3xxx_clkdm,
+        &dss_3xxx_clkdm,
+        &cam_clkdm,
+        &per_clkdm,
+        &emu_clkdm,
+        &dpll1_clkdm,
+        &dpll2_clkdm,
+        &dpll3_clkdm,
+        &dpll4_clkdm,
+        NULL
+};
+static struct clockdomain *clockdomains_omap3430es1[] __initdata = {
+        &gfx_3430es1_clkdm,
+        NULL,
+};
+static struct clockdomain *clockdomains_omap3430es2plus[] __initdata = {
+        &sgx_clkdm,
+        &dpll5_clkdm,
+        &usbhost_clkdm,
+        NULL,
+};
+void __init omap3xxx_clockdomains_init(void)
+{
+        struct clockdomain **sc;
+        if (!cpu_is_omap34xx())
+                return;
+        clkdm_register_platform_funcs(&omap3_clkdm_operations);
+        clkdm_register_clkdms(clockdomains_omap3430_common);
+        sc = (omap_rev() == OMAP3430_REV_ES1_0) ? clockdomains_omap3430es1 :
+                clockdomains_omap3430es2plus;
+        clkdm_register_clkdms(sc);
+        clkdm_register_autodeps(clkdm_autodeps);
+        clkdm_complete_init();
+}
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index dccc651fa0d0..9299ac291d28 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -34,350 +34,122 @@
 /* Static Dependencies for OMAP4 Clock Domains */
 static struct clkdm_dep d2d_wkup_sleep_deps[] = {
-        {
+        { .clkdm_name = "abe_clkdm" },
-                .clkdm_name      = "abe_clkdm",
+        { .clkdm_name = "ivahd_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l3_1_clkdm" },
-        },
+        { .clkdm_name = "l3_2_clkdm" },
-        {
+        { .clkdm_name = "l3_emif_clkdm" },
-                .clkdm_name      = "ivahd_clkdm",
+        { .clkdm_name = "l3_init_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l4_cfg_clkdm" },
-        },
+        { .clkdm_name = "l4_per_clkdm" },
-        {
-                .clkdm_name      = "l3_1_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_2_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_init_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_cfg_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_per_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
        { NULL },
 };
 static struct clkdm_dep ducati_wkup_sleep_deps[] = {
-        {
+        { .clkdm_name = "abe_clkdm" },
-                .clkdm_name      = "abe_clkdm",
+        { .clkdm_name = "ivahd_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l3_1_clkdm" },
-        },
+        { .clkdm_name = "l3_2_clkdm" },
-        {
+        { .clkdm_name = "l3_dss_clkdm" },
-                .clkdm_name      = "ivahd_clkdm",
+        { .clkdm_name = "l3_emif_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l3_gfx_clkdm" },
-        },
+        { .clkdm_name = "l3_init_clkdm" },
-        {
+        { .clkdm_name = "l4_cfg_clkdm" },
-                .clkdm_name      = "l3_1_clkdm",
+        { .clkdm_name = "l4_per_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l4_secure_clkdm" },
-        },
+        { .clkdm_name = "l4_wkup_clkdm" },
-        {
+        { .clkdm_name = "tesla_clkdm" },
-                .clkdm_name      = "l3_2_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_dss_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_gfx_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_init_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_cfg_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_per_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_secure_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_wkup_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "tesla_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
        { NULL },
 };
 static struct clkdm_dep iss_wkup_sleep_deps[] = {
-        {
+        { .clkdm_name = "ivahd_clkdm" },
-                .clkdm_name      = "ivahd_clkdm",
+        { .clkdm_name = "l3_1_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l3_emif_clkdm" },
-        },
-        {
-                .clkdm_name      = "l3_1_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
        { NULL },
 };
 static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
-        {
+        { .clkdm_name = "l3_1_clkdm" },
-                .clkdm_name      = "l3_1_clkdm",
+        { .clkdm_name = "l3_emif_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
        { NULL },
 };
 static struct clkdm_dep l3_dma_wkup_sleep_deps[] = {
-        {
+        { .clkdm_name = "abe_clkdm" },
-                .clkdm_name      = "abe_clkdm",
+        { .clkdm_name = "ducati_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "ivahd_clkdm" },
-        },
+        { .clkdm_name = "l3_1_clkdm" },
-        {
+        { .clkdm_name = "l3_dss_clkdm" },
-                .clkdm_name      = "ducati_clkdm",
+        { .clkdm_name = "l3_emif_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l3_init_clkdm" },
-        },
+        { .clkdm_name = "l4_cfg_clkdm" },
-        {
+        { .clkdm_name = "l4_per_clkdm" },
-                .clkdm_name      = "ivahd_clkdm",
+        { .clkdm_name = "l4_secure_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l4_wkup_clkdm" },
-        },
-        {
-                .clkdm_name      = "l3_1_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_dss_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_init_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_cfg_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_per_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_secure_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_wkup_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
        { NULL },
 };
 static struct clkdm_dep l3_dss_wkup_sleep_deps[] = {
-        {
+        { .clkdm_name = "ivahd_clkdm" },
-                .clkdm_name      = "ivahd_clkdm",
+        { .clkdm_name = "l3_2_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l3_emif_clkdm" },
-        },
-        {
-                .clkdm_name      = "l3_2_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
        { NULL },
 };
 static struct clkdm_dep l3_gfx_wkup_sleep_deps[] = {
-        {
+        { .clkdm_name = "ivahd_clkdm" },
-                .clkdm_name      = "ivahd_clkdm",
+        { .clkdm_name = "l3_1_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l3_emif_clkdm" },
-        },
-        {
-                .clkdm_name      = "l3_1_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
        { NULL },
 };
 static struct clkdm_dep l3_init_wkup_sleep_deps[] = {
-        {
+        { .clkdm_name = "abe_clkdm" },
-                .clkdm_name      = "abe_clkdm",
+        { .clkdm_name = "ivahd_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l3_emif_clkdm" },
-        },
+        { .clkdm_name = "l4_cfg_clkdm" },
-        {
+        { .clkdm_name = "l4_per_clkdm" },
-                .clkdm_name      = "ivahd_clkdm",
+        { .clkdm_name = "l4_secure_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l4_wkup_clkdm" },
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_cfg_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_per_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_secure_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_wkup_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
        { NULL },
 };
 static struct clkdm_dep l4_secure_wkup_sleep_deps[] = {
-        {
+        { .clkdm_name = "l3_1_clkdm" },
-                .clkdm_name      = "l3_1_clkdm",
+        { .clkdm_name = "l3_emif_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l4_per_clkdm" },
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_per_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
        { NULL },
 };
 static struct clkdm_dep mpu_wkup_sleep_deps[] = {
-        {
+        { .clkdm_name = "abe_clkdm" },
-                .clkdm_name      = "abe_clkdm",
+        { .clkdm_name = "ducati_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "ivahd_clkdm" },
-        },
+        { .clkdm_name = "l3_1_clkdm" },
-        {
+        { .clkdm_name = "l3_2_clkdm" },
-                .clkdm_name      = "ducati_clkdm",
+        { .clkdm_name = "l3_dss_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l3_emif_clkdm" },
-        },
+        { .clkdm_name = "l3_gfx_clkdm" },
-        {
+        { .clkdm_name = "l3_init_clkdm" },
-                .clkdm_name      = "ivahd_clkdm",
+        { .clkdm_name = "l4_cfg_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l4_per_clkdm" },
-        },
+        { .clkdm_name = "l4_secure_clkdm" },
-        {
+        { .clkdm_name = "l4_wkup_clkdm" },
-                .clkdm_name      = "l3_1_clkdm",
+        { .clkdm_name = "tesla_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_2_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_dss_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_gfx_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_init_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_cfg_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_per_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_secure_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_wkup_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "tesla_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
        { NULL },
 };
 static struct clkdm_dep tesla_wkup_sleep_deps[] = {
-        {
+        { .clkdm_name = "abe_clkdm" },
-                .clkdm_name      = "abe_clkdm",
+        { .clkdm_name = "ivahd_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l3_1_clkdm" },
-        },
+        { .clkdm_name = "l3_2_clkdm" },
-        {
+        { .clkdm_name = "l3_emif_clkdm" },
-                .clkdm_name      = "ivahd_clkdm",
+        { .clkdm_name = "l3_init_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l4_cfg_clkdm" },
-        },
+        { .clkdm_name = "l4_per_clkdm" },
-        {
+        { .clkdm_name = "l4_wkup_clkdm" },
-                .clkdm_name      = "l3_1_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_2_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_init_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_cfg_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_per_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_wkup_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
        { NULL },
 };
@@ -388,7 +160,6 @@ static struct clockdomain l4_cefuse_44xx_clkdm = {
        .cm_inst          = OMAP4430_CM2_CEFUSE_INST,
        .clkdm_offs       = OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS,
        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain l4_cfg_44xx_clkdm = {
@@ -399,7 +170,6 @@ static struct clockdomain l4_cfg_44xx_clkdm = {
        .clkdm_offs       = OMAP4430_CM2_CORE_L4CFG_CDOFFS,
        .dep_bit          = OMAP4430_L4CFG_STATDEP_SHIFT,
        .flags            = CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain tesla_44xx_clkdm = {
@@ -412,7 +182,6 @@ static struct clockdomain tesla_44xx_clkdm = {
        .wkdep_srcs       = tesla_wkup_sleep_deps,
        .sleepdep_srcs    = tesla_wkup_sleep_deps,
        .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain l3_gfx_44xx_clkdm = {
@@ -425,7 +194,6 @@ static struct clockdomain l3_gfx_44xx_clkdm = {
        .wkdep_srcs       = l3_gfx_wkup_sleep_deps,
        .sleepdep_srcs    = l3_gfx_wkup_sleep_deps,
        .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain ivahd_44xx_clkdm = {
@@ -438,7 +206,6 @@ static struct clockdomain ivahd_44xx_clkdm = {
        .wkdep_srcs       = ivahd_wkup_sleep_deps,
        .sleepdep_srcs    = ivahd_wkup_sleep_deps,
        .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain l4_secure_44xx_clkdm = {
@@ -451,7 +218,6 @@ static struct clockdomain l4_secure_44xx_clkdm = {
        .wkdep_srcs       = l4_secure_wkup_sleep_deps,
        .sleepdep_srcs    = l4_secure_wkup_sleep_deps,
        .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain l4_per_44xx_clkdm = {
@@ -462,7 +228,6 @@ static struct clockdomain l4_per_44xx_clkdm = {
        .clkdm_offs       = OMAP4430_CM2_L4PER_L4PER_CDOFFS,
        .dep_bit          = OMAP4430_L4PER_STATDEP_SHIFT,
        .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain abe_44xx_clkdm = {
@@ -473,7 +238,6 @@ static struct clockdomain abe_44xx_clkdm = {
        .clkdm_offs       = OMAP4430_CM1_ABE_ABE_CDOFFS,
        .dep_bit          = OMAP4430_ABE_STATDEP_SHIFT,
        .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain l3_instr_44xx_clkdm = {
@@ -482,7 +246,6 @@ static struct clockdomain l3_instr_44xx_clkdm = {
        .prcm_partition   = OMAP4430_CM2_PARTITION,
        .cm_inst          = OMAP4430_CM2_CORE_INST,
        .clkdm_offs       = OMAP4430_CM2_CORE_L3INSTR_CDOFFS,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain l3_init_44xx_clkdm = {
@@ -495,7 +258,6 @@ static struct clockdomain l3_init_44xx_clkdm = {
        .wkdep_srcs       = l3_init_wkup_sleep_deps,
        .sleepdep_srcs    = l3_init_wkup_sleep_deps,
        .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain d2d_44xx_clkdm = {
@@ -507,7 +269,6 @@ static struct clockdomain d2d_44xx_clkdm = {
        .wkdep_srcs       = d2d_wkup_sleep_deps,
        .sleepdep_srcs    = d2d_wkup_sleep_deps,
        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain mpu0_44xx_clkdm = {
@@ -517,7 +278,6 @@ static struct clockdomain mpu0_44xx_clkdm = {
        .cm_inst          = OMAP4430_PRCM_MPU_CPU0_INST,
        .clkdm_offs       = OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS,
        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain mpu1_44xx_clkdm = {
@@ -527,7 +287,6 @@ static struct clockdomain mpu1_44xx_clkdm = {
        .cm_inst          = OMAP4430_PRCM_MPU_CPU1_INST,
        .clkdm_offs       = OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS,
        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain l3_emif_44xx_clkdm = {
@@ -538,7 +297,6 @@ static struct clockdomain l3_emif_44xx_clkdm = {
        .clkdm_offs       = OMAP4430_CM2_CORE_MEMIF_CDOFFS,
        .dep_bit          = OMAP4430_MEMIF_STATDEP_SHIFT,
        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain l4_ao_44xx_clkdm = {
@@ -548,7 +306,6 @@ static struct clockdomain l4_ao_44xx_clkdm = {
        .cm_inst          = OMAP4430_CM2_ALWAYS_ON_INST,
        .clkdm_offs       = OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS,
        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain ducati_44xx_clkdm = {
@@ -561,7 +318,6 @@ static struct clockdomain ducati_44xx_clkdm = {
        .wkdep_srcs       = ducati_wkup_sleep_deps,
        .sleepdep_srcs    = ducati_wkup_sleep_deps,
        .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain mpu_44xx_clkdm = {
@@ -573,7 +329,6 @@ static struct clockdomain mpu_44xx_clkdm = {
        .wkdep_srcs       = mpu_wkup_sleep_deps,
        .sleepdep_srcs    = mpu_wkup_sleep_deps,
        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain l3_2_44xx_clkdm = {
@@ -584,7 +339,6 @@ static struct clockdomain l3_2_44xx_clkdm = {
        .clkdm_offs       = OMAP4430_CM2_CORE_L3_2_CDOFFS,
        .dep_bit          = OMAP4430_L3_2_STATDEP_SHIFT,
        .flags            = CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain l3_1_44xx_clkdm = {
@@ -595,7 +349,6 @@ static struct clockdomain l3_1_44xx_clkdm = {
        .clkdm_offs       = OMAP4430_CM2_CORE_L3_1_CDOFFS,
        .dep_bit          = OMAP4430_L3_1_STATDEP_SHIFT,
        .flags            = CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain iss_44xx_clkdm = {
@@ -607,7 +360,6 @@ static struct clockdomain iss_44xx_clkdm = {
        .wkdep_srcs       = iss_wkup_sleep_deps,
        .sleepdep_srcs    = iss_wkup_sleep_deps,
        .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain l3_dss_44xx_clkdm = {
@@ -620,7 +372,6 @@ static struct clockdomain l3_dss_44xx_clkdm = {
        .wkdep_srcs       = l3_dss_wkup_sleep_deps,
        .sleepdep_srcs    = l3_dss_wkup_sleep_deps,
        .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain l4_wkup_44xx_clkdm = {
@@ -631,7 +382,6 @@ static struct clockdomain l4_wkup_44xx_clkdm = {
        .clkdm_offs       = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS,
        .dep_bit          = OMAP4430_L4WKUP_STATDEP_SHIFT,
        .flags            = CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain emu_sys_44xx_clkdm = {
@@ -641,7 +391,6 @@ static struct clockdomain emu_sys_44xx_clkdm = {
        .cm_inst          = OMAP4430_PRM_EMU_CM_INST,
        .clkdm_offs       = OMAP4430_PRM_EMU_CM_EMU_CDOFFS,
        .flags            = CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain l3_dma_44xx_clkdm = {
@@ -653,7 +402,6 @@ static struct clockdomain l3_dma_44xx_clkdm = {
        .wkdep_srcs       = l3_dma_wkup_sleep_deps,
        .sleepdep_srcs    = l3_dma_wkup_sleep_deps,
        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* As clockdomains are added or removed above, this list must also be changed */
@@ -685,7 +433,10 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = {
        NULL
 };
 void __init omap44xx_clockdomains_init(void)
 {
-        clkdm_init(clockdomains_omap44xx, NULL, &omap4_clkdm_operations);
+        clkdm_register_platform_funcs(&omap4_clkdm_operations);
+        clkdm_register_clkdms(clockdomains_omap44xx);
+        clkdm_complete_init();
 }
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 3f20cbb9967b..110e5b9db145 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -45,17 +45,22 @@ static void __init __omap2_set_globals(struct omap_globals *omap2_globals)
 static struct omap_globals omap242x_globals = {
        .class  = OMAP242X_CLASS,
        .tap    = OMAP2_L4_IO_ADDRESS(0x48014000),
-        .sdrc   = OMAP2420_SDRC_BASE,
+        .sdrc   = OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
-        .sms    = OMAP2420_SMS_BASE,
+        .sms    = OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE),
-        .ctrl   = OMAP242X_CTRL_BASE,
+        .ctrl   = OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE),
-        .prm    = OMAP2420_PRM_BASE,
+        .prm    = OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE),
-        .cm     = OMAP2420_CM_BASE,
+        .cm     = OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE),
 };
 void __init omap2_set_globals_242x(void)
 {
        __omap2_set_globals(&omap242x_globals);
 }
+void __init omap242x_map_io(void)
+{
+        omap242x_map_common_io();
+}
 #endif
 #if defined(CONFIG_SOC_OMAP2430)
@@ -63,17 +68,22 @@ void __init omap2_set_globals_242x(void)
 static struct omap_globals omap243x_globals = {
        .class  = OMAP243X_CLASS,
        .tap    = OMAP2_L4_IO_ADDRESS(0x4900a000),
-        .sdrc   = OMAP243X_SDRC_BASE,
+        .sdrc   = OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
-        .sms    = OMAP243X_SMS_BASE,
+        .sms    = OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE),
-        .ctrl   = OMAP243X_CTRL_BASE,
+        .ctrl   = OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
-        .prm    = OMAP2430_PRM_BASE,
+        .prm    = OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE),
-        .cm     = OMAP2430_CM_BASE,
+        .cm     = OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE),
 };
 void __init omap2_set_globals_243x(void)
 {
        __omap2_set_globals(&omap243x_globals);
 }
+void __init omap243x_map_io(void)
+{
+        omap243x_map_common_io();
+}
 #endif
 #if defined(CONFIG_ARCH_OMAP3)
@@ -81,11 +91,11 @@ void __init omap2_set_globals_243x(void)
 static struct omap_globals omap3_globals = {
        .class  = OMAP343X_CLASS,
        .tap    = OMAP2_L4_IO_ADDRESS(0x4830A000),
-        .sdrc   = OMAP343X_SDRC_BASE,
+        .sdrc   = OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
-        .sms    = OMAP343X_SMS_BASE,
+        .sms    = OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE),
-        .ctrl   = OMAP343X_CTRL_BASE,
+        .ctrl   = OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
-        .prm    = OMAP3430_PRM_BASE,
+        .prm    = OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE),
-        .cm     = OMAP3430_CM_BASE,
+        .cm     = OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
 };
 void __init omap2_set_globals_3xxx(void)
@@ -95,7 +105,6 @@ void __init omap2_set_globals_3xxx(void)
 void __init omap3_map_io(void)
 {
-        omap2_set_globals_3xxx();
        omap34xx_map_common_io();
 }
@@ -110,9 +119,9 @@ void __init omap3_map_io(void)
 static struct omap_globals ti816x_globals = {
        .class  = OMAP343X_CLASS,
        .tap    = OMAP2_L4_IO_ADDRESS(TI816X_TAP_BASE),
-        .ctrl   = TI816X_CTRL_BASE,
+        .ctrl   = OMAP2_L4_IO_ADDRESS(TI816X_CTRL_BASE),
-        .prm    = TI816X_PRCM_BASE,
+        .prm    = OMAP2_L4_IO_ADDRESS(TI816X_PRCM_BASE),
-        .cm     = TI816X_PRCM_BASE,
+        .cm     = OMAP2_L4_IO_ADDRESS(TI816X_PRCM_BASE),
 };
 void __init omap2_set_globals_ti816x(void)
@@ -125,11 +134,11 @@ void __init omap2_set_globals_ti816x(void)
 static struct omap_globals omap4_globals = {
        .class  = OMAP443X_CLASS,
        .tap    = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
-        .ctrl   = OMAP443X_SCM_BASE,
+        .ctrl   = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
-        .ctrl_pad       = OMAP443X_CTRL_BASE,
+        .ctrl_pad       = OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE),
-        .prm    = OMAP4430_PRM_BASE,
+        .prm    = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE),
-        .cm     = OMAP4430_CM_BASE,
+        .cm     = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
-        .cm2    = OMAP4430_CM2_BASE,
+        .cm2    = OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE),
 };
 void __init omap2_set_globals_443x(void)
@@ -138,5 +147,10 @@ void __init omap2_set_globals_443x(void)
        omap2_set_globals_control(&omap4_globals);
        omap2_set_globals_prcm(&omap4_globals);
 }
+void __init omap4_map_io(void)
+{
+        omap44xx_map_common_io();
+}
 #endif
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index aab884fecc55..e34d27f8c49c 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -149,17 +149,11 @@ static struct omap3_control_regs control_context;
 void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
 {
-        /* Static mapping, never released */
+        if (omap2_globals->ctrl)
-        if (omap2_globals->ctrl) {
+                omap2_ctrl_base = omap2_globals->ctrl;
-                omap2_ctrl_base = ioremap(omap2_globals->ctrl, SZ_4K);
-                WARN_ON(!omap2_ctrl_base);
-        }
-        /* Static mapping, never released */
+        if (omap2_globals->ctrl_pad)
-        if (omap2_globals->ctrl_pad) {
+                omap4_ctrl_pad_base = omap2_globals->ctrl_pad;
-                omap4_ctrl_pad_base = ioremap(omap2_globals->ctrl_pad, SZ_4K);
-                WARN_ON(!omap4_ctrl_pad_base);
-        }
 }
 void __iomem *omap_ctrl_base_get(void)
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index ae8ea5b3b1a0..68ec03152d5f 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -16,6 +16,7 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/slab.h>
+#include <linux/of.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
@@ -43,7 +44,7 @@ static int __init omap3_l3_init(void)
 {
        int l;
        struct omap_hwmod *oh;
-        struct omap_device *od;
+        struct platform_device *pdev;
        char oh_name[L3_MODULES_MAX_LEN];
        /*
@@ -60,12 +61,12 @@ static int __init omap3_l3_init(void)
        if (!oh)
                pr_err("could not look up %s\n", oh_name);
-        od = omap_device_build("omap_l3_smx", 0, oh, NULL, 0,
+        pdev = omap_device_build("omap_l3_smx", 0, oh, NULL, 0,
                                                           NULL, 0, 0);
-        WARN(IS_ERR(od), "could not build omap_device for %s\n", oh_name);
+        WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
-        return IS_ERR(od) ? PTR_ERR(od) : 0;
+        return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
 }
 postcore_initcall(omap3_l3_init);
@@ -73,9 +74,13 @@ static int __init omap4_l3_init(void)
 {
        int l, i;
        struct omap_hwmod *oh[3];
-        struct omap_device *od;
+        struct platform_device *pdev;
        char oh_name[L3_MODULES_MAX_LEN];
+        /* If dtb is there, the devices will be created dynamically */
+        if (of_have_populated_dt())
+                return -ENODEV;
        /*
         * To avoid code running on other OMAPs in
         * multi-omap builds
@@ -91,12 +96,12 @@ static int __init omap4_l3_init(void)
                        pr_err("could not look up %s\n", oh_name);
        }
-        od = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL,
+        pdev = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL,
                                                     0, NULL, 0, 0);
-        WARN(IS_ERR(od), "could not build omap_device for %s\n", oh_name);
+        WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
-        return IS_ERR(od) ? PTR_ERR(od) : 0;
+        return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
 }
 postcore_initcall(omap4_l3_init);
@@ -220,18 +225,10 @@ static inline void omap_init_camera(void)
 #endif
 }
-struct omap_device_pm_latency omap_keyboard_latency[] = {
-        {
-                .deactivate_func = omap_device_idle_hwmods,
-                .activate_func   = omap_device_enable_hwmods,
-                .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
-        },
-};
 int __init omap4_keyboard_init(struct omap4_keypad_platform_data
                        *sdp4430_keypad_data, struct omap_board_data *bdata)
 {
-        struct omap_device *od;
+        struct platform_device *pdev;
        struct omap_hwmod *oh;
        struct omap4_keypad_platform_data *keypad_data;
        unsigned int id = -1;
@@ -246,15 +243,13 @@ int __init omap4_keyboard_init(struct omap4_keypad_platform_data
        keypad_data = sdp4430_keypad_data;
-        od = omap_device_build(name, id, oh, keypad_data,
+        pdev = omap_device_build(name, id, oh, keypad_data,
-                        sizeof(struct omap4_keypad_platform_data),
+                        sizeof(struct omap4_keypad_platform_data), NULL, 0, 0);
-                        omap_keyboard_latency,
-                        ARRAY_SIZE(omap_keyboard_latency), 0);
-        if (IS_ERR(od)) {
+        if (IS_ERR(pdev)) {
                WARN(1, "Can't build omap_device for %s:%s.\n",
                                                name, oh->name);
-                return PTR_ERR(od);
+                return PTR_ERR(pdev);
        }
        oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
@@ -262,18 +257,10 @@ int __init omap4_keyboard_init(struct omap4_keypad_platform_data
 }
 #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
-static struct omap_device_pm_latency mbox_latencies[] = {
-        [0] = {
-                .activate_func = omap_device_enable_hwmods,
-                .deactivate_func = omap_device_idle_hwmods,
-                .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
-        },
-};
 static inline void omap_init_mbox(void)
 {
        struct omap_hwmod *oh;
-        struct omap_device *od;
+        struct platform_device *pdev;
        oh = omap_hwmod_lookup("mailbox");
        if (!oh) {
@@ -281,10 +268,9 @@ static inline void omap_init_mbox(void)
                return;
        }
-        od = omap_device_build("omap-mailbox", -1, oh, NULL, 0,
+        pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0, NULL, 0, 0);
-                                mbox_latencies, ARRAY_SIZE(mbox_latencies), 0);
+        WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n",
-        WARN(IS_ERR(od), "%s: could not build device, err %ld\n",
+                                                __func__, PTR_ERR(pdev));
-                                                __func__, PTR_ERR(od));
 }
 #else
 static inline void omap_init_mbox(void) { }
@@ -365,17 +351,9 @@ static inline void omap_init_mcpdm(void) {}
 #include <plat/mcspi.h>
-struct omap_device_pm_latency omap_mcspi_latency[] = {
-        [0] = {
-                .deactivate_func = omap_device_idle_hwmods,
-                .activate_func   = omap_device_enable_hwmods,
-                .flags           = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
-        },
-};
 static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
 {
-        struct omap_device *od;
+        struct platform_device *pdev;
        char *name = "omap2_mcspi";
        struct omap2_mcspi_platform_config *pdata;
        static int spi_num;
@@ -402,10 +380,9 @@ static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
        }
        spi_num++;
-        od = omap_device_build(name, spi_num, oh, pdata,
+        pdev = omap_device_build(name, spi_num, oh, pdata,
-                                sizeof(*pdata), omap_mcspi_latency,
+                                sizeof(*pdata), NULL, 0, 0);
-                                ARRAY_SIZE(omap_mcspi_latency), 0);
+        WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s\n",
-        WARN(IS_ERR(od), "Can't build omap_device for %s:%s\n",
                                name, oh->name);
        kfree(pdata);
        return 0;
@@ -730,18 +707,10 @@ static int __init omap2_init_devices(void)
 arch_initcall(omap2_init_devices);
 #if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
-static struct omap_device_pm_latency omap_wdt_latency[] = {
-        [0] = {
-                .deactivate_func = omap_device_idle_hwmods,
-                .activate_func   = omap_device_enable_hwmods,
-                .flags           = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
-        },
-};
 static int __init omap_init_wdt(void)
 {
        int id = -1;
-        struct omap_device *od;
+        struct platform_device *pdev;
        struct omap_hwmod *oh;
        char *oh_name = "wd_timer2";
        char *dev_name = "omap_wdt";
@@ -755,10 +724,8 @@ static int __init omap_init_wdt(void)
                return -EINVAL;
        }
-        od = omap_device_build(dev_name, id, oh, NULL, 0,
+        pdev = omap_device_build(dev_name, id, oh, NULL, 0, NULL, 0, 0);
-                                omap_wdt_latency,
+        WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
-                                ARRAY_SIZE(omap_wdt_latency), 0);
-        WARN(IS_ERR(od), "Can't build omap_device for %s:%s.\n",
                                dev_name, oh->name);
        return 0;
 }
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 62510ec863c6..4036821a01f3 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -37,14 +37,6 @@ static struct platform_device omap_display_device = {
        },
 };
-static struct omap_device_pm_latency omap_dss_latency[] = {
-        [0] = {
-                .deactivate_func        = omap_device_idle_hwmods,
-                .activate_func          = omap_device_enable_hwmods,
-                .flags                  = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
-        },
-};
 struct omap_dss_hwmod_data {
        const char *oh_name;
        const char *dev_name;
@@ -127,7 +119,7 @@ int __init omap_display_init(struct omap_dss_board_info *board_data)
 {
        int r = 0;
        struct omap_hwmod *oh;
-        struct omap_device *od;
+        struct platform_device *pdev;
        int i, oh_count;
        struct omap_display_platform_data pdata;
        const struct omap_dss_hwmod_data *curr_dss_hwmod;
@@ -162,13 +154,12 @@ int __init omap_display_init(struct omap_dss_board_info *board_data)
                        return -ENODEV;
                }
-                od = omap_device_build(curr_dss_hwmod[i].dev_name,
+                pdev = omap_device_build(curr_dss_hwmod[i].dev_name,
                                curr_dss_hwmod[i].id, oh, &pdata,
                                sizeof(struct omap_display_platform_data),
-                                omap_dss_latency,
+                                NULL, 0, 0);
-                                ARRAY_SIZE(omap_dss_latency), 0);
-                if (WARN((IS_ERR(od)), "Could not build omap_device for %s\n",
+                if (WARN((IS_ERR(pdev)), "Could not build omap_device for %s\n",
                                curr_dss_hwmod[i].oh_name))
                        return -ENODEV;
        }
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index c9ff0e79703d..a59a45a0096e 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -87,14 +87,6 @@ static u16 reg_map[] = {
        [CCDN]                  = 0xd8,
 };
-static struct omap_device_pm_latency omap2_dma_latency[] = {
-        {
-                .deactivate_func = omap_device_idle_hwmods,
-                .activate_func   = omap_device_enable_hwmods,
-                .flags           = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
-        },
-};
 static void __iomem *dma_base;
 static inline void dma_write(u32 val, int reg, int lch)
 {
@@ -228,7 +220,7 @@ static u32 configure_dma_errata(void)
 /* One time initializations */
 static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
 {
-        struct omap_device                      *od;
+        struct platform_device                  *pdev;
        struct omap_system_dma_plat_info        *p;
        struct resource                         *mem;
        char                                    *name = "omap_dma_system";
@@ -258,23 +250,22 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
        p->errata               = configure_dma_errata();
-        od = omap_device_build(name, 0, oh, p, sizeof(*p),
+        pdev = omap_device_build(name, 0, oh, p, sizeof(*p), NULL, 0, 0);
-                        omap2_dma_latency, ARRAY_SIZE(omap2_dma_latency), 0);
        kfree(p);
-        if (IS_ERR(od)) {
+        if (IS_ERR(pdev)) {
                pr_err("%s: Can't build omap_device for %s:%s.\n",
                        __func__, name, oh->name);
-                return PTR_ERR(od);
+                return PTR_ERR(pdev);
        }
-        mem = platform_get_resource(&od->pdev, IORESOURCE_MEM, 0);
+        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        if (!mem) {
-                dev_err(&od->pdev.dev, "%s: no mem resource\n", __func__);
+                dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
                return -EINVAL;
        }
        dma_base = ioremap(mem->start, resource_size(mem));
        if (!dma_base) {
-                dev_err(&od->pdev.dev, "%s: ioremap fail\n", __func__);
+                dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
                return -ENOMEM;
        }
@@ -283,7 +274,7 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
                                        (d->lch_count), GFP_KERNEL);
        if (!d->chan) {
-                dev_err(&od->pdev.dev, "%s: kzalloc fail\n", __func__);
+                dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__);
                return -ENOMEM;
        }
        return 0;
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 2765cdc3152d..8cbfbc2918ce 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -24,17 +24,9 @@
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
-static struct omap_device_pm_latency omap_gpio_latency[] = {
-        [0] = {
-                .deactivate_func = omap_device_idle_hwmods,
-                .activate_func   = omap_device_enable_hwmods,
-                .flags           = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
-        },
-};
 static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 {
-        struct omap_device *od;
+        struct platform_device *pdev;
        struct omap_gpio_platform_data *pdata;
        struct omap_gpio_dev_attr *dev_attr;
        char *name = "omap_gpio";
@@ -107,19 +99,17 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
                return -EINVAL;
        }
-        od = omap_device_build(name, id - 1, oh, pdata,
+        pdev = omap_device_build(name, id - 1, oh, pdata,
-                                sizeof(*pdata), omap_gpio_latency,
+                                sizeof(*pdata), NULL, 0, false);
-                                ARRAY_SIZE(omap_gpio_latency),
-                                false);
        kfree(pdata);
-        if (IS_ERR(od)) {
+        if (IS_ERR(pdev)) {
                WARN(1, "Can't build omap_device for %s:%s.\n",
                                        name, oh->name);
-                return PTR_ERR(od);
+                return PTR_ERR(pdev);
        }
-        omap_device_disable_idle_on_suspend(od);
+        omap_device_disable_idle_on_suspend(pdev);
        gpio_bank_count++;
        return 0;
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 097a42d81e59..77085847e4e7 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -409,31 +409,17 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
        return 0;
 }
-static struct omap_device_pm_latency omap_hsmmc_latency[] = {
-        [0] = {
-                .deactivate_func = omap_device_idle_hwmods,
-                .activate_func   = omap_device_enable_hwmods,
-                .flags           = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
-        },
-        /*
-         * XXX There should also be an entry here to power off/on the
-         * MMC regulators/PBIAS cells, etc.
-         */
-};
 #define MAX_OMAP_MMC_HWMOD_NAME_LEN             16
 void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
 {
        struct omap_hwmod *oh;
-        struct omap_device *od;
+        struct platform_device *pdev;
-        struct omap_device_pm_latency *ohl;
        char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
        struct omap_mmc_platform_data *mmc_data;
        struct omap_mmc_dev_attr *mmc_dev_attr;
        char *name;
        int l;
-        int ohl_cnt = 0;
        mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
        if (!mmc_data) {
@@ -448,8 +434,6 @@ void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
        omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
        name = "omap_hsmmc";
-        ohl = omap_hsmmc_latency;
-        ohl_cnt = ARRAY_SIZE(omap_hsmmc_latency);
        l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
                     "mmc%d", ctrl_nr);
@@ -467,9 +451,9 @@ void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
                mmc_data->controller_flags = mmc_dev_attr->flags;
        }
-        od = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
+        pdev = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
-                sizeof(struct omap_mmc_platform_data), ohl, ohl_cnt, false);
+                sizeof(struct omap_mmc_platform_data), NULL, 0, false);
-        if (IS_ERR(od)) {
+        if (IS_ERR(pdev)) {
                WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name);
                kfree(mmc_data->slots[0].name);
                goto done;
@@ -478,7 +462,7 @@ void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
         * return device handle to board setup code
         * required to populate for regulator framework structure
         */
-        hsmmcinfo->dev = &od->pdev.dev;
+        hsmmcinfo->dev = &pdev->dev;
 done:
        kfree(mmc_data);
diff --git a/arch/arm/mach-omap2/hwspinlock.c b/arch/arm/mach-omap2/hwspinlock.c
index 06d4a80660a5..36e21091b06a 100644
--- a/arch/arm/mach-omap2/hwspinlock.c
+++ b/arch/arm/mach-omap2/hwspinlock.c
@@ -23,19 +23,11 @@
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
-struct omap_device_pm_latency omap_spinlock_latency[] = {
-        {
-                .deactivate_func = omap_device_idle_hwmods,
-                .activate_func   = omap_device_enable_hwmods,
-                .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
-        }
-};
 int __init hwspinlocks_init(void)
 {
        int retval = 0;
        struct omap_hwmod *oh;
-        struct omap_device *od;
+        struct platform_device *pdev;
        const char *oh_name = "spinlock";
        const char *dev_name = "omap_hwspinlock";
@@ -48,13 +40,11 @@ int __init hwspinlocks_init(void)
        if (oh == NULL)
                return -EINVAL;
-        od = omap_device_build(dev_name, 0, oh, NULL, 0,
+        pdev = omap_device_build(dev_name, 0, oh, NULL, 0, NULL, 0, false);
-                                omap_spinlock_latency,
+        if (IS_ERR(pdev)) {
-                                ARRAY_SIZE(omap_spinlock_latency), false);
-        if (IS_ERR(od)) {
                pr_err("Can't build omap_device for %s:%s\n", dev_name,
                                                                oh_name);
-                retval = PTR_ERR(od);
+                retval = PTR_ERR(pdev);
        }
        return retval;
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 37efb8696927..d27daf921c7e 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -28,7 +28,6 @@
 #include "control.h"
-static struct omap_chip_id omap_chip;
 static unsigned int omap_revision;
 u32 omap_features;
@@ -39,19 +38,6 @@ unsigned int omap_rev(void)
 }
 EXPORT_SYMBOL(omap_rev);
-/**
- * omap_chip_is - test whether currently running OMAP matches a chip type
- * @oc: omap_chip_t to test against
- *
- * Test whether the currently-running OMAP chip matches the supplied
- * chip type 'oc'.  Returns 1 upon a match; 0 upon failure.
- */
-int omap_chip_is(struct omap_chip_id oci)
-{
-        return (oci.oc & omap_chip.oc) ? 1 : 0;
-}
-EXPORT_SYMBOL(omap_chip_is);
 int omap_type(void)
 {
        u32 val = 0;
@@ -242,14 +228,12 @@ static void __init ti816x_check_features(void)
        omap_features = OMAP3_HAS_NEON;
 }
-static void __init omap3_check_revision(void)
+static void __init omap3_check_revision(const char **cpu_rev)
 {
        u32 cpuid, idcode;
        u16 hawkeye;
        u8 rev;
-        omap_chip.oc = CHIP_IS_OMAP3430;
        /*
         * We cannot access revision registers on ES1.0.
         * If the processor type is Cortex-A8 and the revision is 0x0
@@ -258,7 +242,7 @@ static void __init omap3_check_revision(void)
        cpuid = read_cpuid(CPUID_ID);
        if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
                omap_revision = OMAP3430_REV_ES1_0;
-                omap_chip.oc |= CHIP_IS_OMAP3430ES1;
+                *cpu_rev = "1.0";
                return;
        }
@@ -279,77 +263,85 @@ static void __init omap3_check_revision(void)
                case 0: /* Take care of early samples */
                case 1:
                        omap_revision = OMAP3430_REV_ES2_0;
-                        omap_chip.oc |= CHIP_IS_OMAP3430ES2;
+                        *cpu_rev = "2.0";
                        break;
                case 2:
                        omap_revision = OMAP3430_REV_ES2_1;
-                        omap_chip.oc |= CHIP_IS_OMAP3430ES2;
+                        *cpu_rev = "2.1";
                        break;
                case 3:
                        omap_revision = OMAP3430_REV_ES3_0;
-                        omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
+                        *cpu_rev = "3.0";
                        break;
                case 4:
                        omap_revision = OMAP3430_REV_ES3_1;
-                        omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
+                        *cpu_rev = "3.1";
                        break;
                case 7:
                /* FALLTHROUGH */
                default:
                        /* Use the latest known revision as default */
                        omap_revision = OMAP3430_REV_ES3_1_2;
+                        *cpu_rev = "3.1.2";
-                        /* REVISIT: Add CHIP_IS_OMAP3430ES3_1_2? */
-                        omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
                }
                break;
        case 0xb868:
-                /* Handle OMAP35xx/AM35xx devices
+                /*
+                 * Handle OMAP/AM 3505/3517 devices
                 *
-                 * Set the device to be OMAP3505 here. Actual device
+                 * Set the device to be OMAP3517 here. Actual device
                 * is identified later based on the features.
-                 *
-                 * REVISIT: AM3505/AM3517 should have their own CHIP_IS
                 */
-                omap_revision = OMAP3505_REV(rev);
+                switch (rev) {
-                omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
+                case 0:
+                        omap_revision = OMAP3517_REV_ES1_0;
+                        *cpu_rev = "1.0";
+                        break;
+                case 1:
+                /* FALLTHROUGH */
+                default:
+                        omap_revision = OMAP3517_REV_ES1_1;
+                        *cpu_rev = "1.1";
+                }
                break;
        case 0xb891:
                /* Handle 36xx devices */
-                omap_chip.oc |= CHIP_IS_OMAP3630ES1;
                switch(rev) {
                case 0: /* Take care of early samples */
                        omap_revision = OMAP3630_REV_ES1_0;
+                        *cpu_rev = "1.0";
                        break;
                case 1:
                        omap_revision = OMAP3630_REV_ES1_1;
-                        omap_chip.oc |= CHIP_IS_OMAP3630ES1_1;
+                        *cpu_rev = "1.1";
                        break;
                case 2:
+                /* FALLTHROUGH */
                default:
-                        omap_revision =  OMAP3630_REV_ES1_2;
+                        omap_revision = OMAP3630_REV_ES1_2;
-                        omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
+                        *cpu_rev = "1.2";
                }
                break;
        case 0xb81e:
-                omap_chip.oc = CHIP_IS_TI816X;
                switch (rev) {
                case 0:
                        omap_revision = TI8168_REV_ES1_0;
+                        *cpu_rev = "1.0";
                        break;
                case 1:
+                /* FALLTHROUGH */
+                default:
                        omap_revision = TI8168_REV_ES1_1;
+                        *cpu_rev = "1.1";
                        break;
-                default:
-                        omap_revision =  TI8168_REV_ES1_1;
                }
                break;
        default:
-                /* Unknown default to latest silicon rev as default*/
+                /* Unknown default to latest silicon rev as default */
-                omap_revision =  OMAP3630_REV_ES1_2;
+                omap_revision = OMAP3630_REV_ES1_2;
-                omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
+                *cpu_rev = "1.2";
+                pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
        }
 }
@@ -382,24 +374,20 @@ static void __init omap4_check_revision(void)
                switch (rev) {
                case 0:
                        omap_revision = OMAP4430_REV_ES1_0;
-                        omap_chip.oc |= CHIP_IS_OMAP4430ES1;
                        break;
                case 1:
                default:
                        omap_revision = OMAP4430_REV_ES2_0;
-                        omap_chip.oc |= CHIP_IS_OMAP4430ES2;
                }
                break;
        case 0xb95c:
                switch (rev) {
                case 3:
                        omap_revision = OMAP4430_REV_ES2_1;
-                        omap_chip.oc |= CHIP_IS_OMAP4430ES2_1;
                        break;
                case 4:
                default:
                        omap_revision = OMAP4430_REV_ES2_2;
-                        omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
                }
                break;
        case 0xb94e:
@@ -407,14 +395,12 @@ static void __init omap4_check_revision(void)
                case 0:
                default:
                        omap_revision = OMAP4460_REV_ES1_0;
-                        omap_chip.oc |= CHIP_IS_OMAP4460ES1_0;
                        break;
                }
                break;
        default:
                /* Unknown default to latest silicon rev as default */
                omap_revision = OMAP4430_REV_ES2_2;
-                omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
        }
        pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
@@ -425,94 +411,33 @@ static void __init omap4_check_revision(void)
        if (omap3_has_ ##feat())                \
                printk(#feat" ");
-static void __init omap3_cpuinfo(void)
+static void __init omap3_cpuinfo(const char *cpu_rev)
 {
-        u8 rev = GET_OMAP_REVISION();
+        const char *cpu_name;
-        char cpu_name[16], cpu_rev[16];
-        /* OMAP3430 and OMAP3530 are assumed to be same.
+        /*
+         * OMAP3430 and OMAP3530 are assumed to be same.
         *
         * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
         * on available features. Upon detection, update the CPU id
         * and CPU class bits.
         */
        if (cpu_is_omap3630()) {
-                strcpy(cpu_name, "OMAP3630");
+                cpu_name = "OMAP3630";
-        } else if (cpu_is_omap3505()) {
+        } else if (cpu_is_omap3517()) {
-                /*
+                /* AM35xx devices */
-                 * AM35xx devices
+                cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
-                 */
-                if (omap3_has_sgx()) {
-                        omap_revision = OMAP3517_REV(rev);
-                        strcpy(cpu_name, "AM3517");
-                } else {
-                        /* Already set in omap3_check_revision() */
-                        strcpy(cpu_name, "AM3505");
-                }
        } else if (cpu_is_ti816x()) {
-                strcpy(cpu_name, "TI816X");
+                cpu_name = "TI816X";
        } else if (omap3_has_iva() && omap3_has_sgx()) {
                /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
-                strcpy(cpu_name, "OMAP3430/3530");
+                cpu_name = "OMAP3430/3530";
        } else if (omap3_has_iva()) {
-                omap_revision = OMAP3525_REV(rev);
+                cpu_name = "OMAP3525";
-                strcpy(cpu_name, "OMAP3525");
        } else if (omap3_has_sgx()) {
-                omap_revision = OMAP3515_REV(rev);
+                cpu_name = "OMAP3515";
-                strcpy(cpu_name, "OMAP3515");
        } else {
-                omap_revision = OMAP3503_REV(rev);
+                cpu_name = "OMAP3503";
-                strcpy(cpu_name, "OMAP3503");
-        }
-        if (cpu_is_omap3630() || cpu_is_ti816x()) {
-                switch (rev) {
-                case OMAP_REVBITS_00:
-                        strcpy(cpu_rev, "1.0");
-                        break;
-                case OMAP_REVBITS_01:
-                        strcpy(cpu_rev, "1.1");
-                        break;
-                case OMAP_REVBITS_02:
-                        /* FALLTHROUGH */
-                default:
-                        /* Use the latest known revision as default */
-                        strcpy(cpu_rev, "1.2");
-                }
-        } else if (cpu_is_omap3505() || cpu_is_omap3517()) {
-                switch (rev) {
-                case OMAP_REVBITS_00:
-                        strcpy(cpu_rev, "1.0");
-                        break;
-                case OMAP_REVBITS_01:
-                        /* FALLTHROUGH */
-                default:
-                        /* Use the latest known revision as default */
-                        strcpy(cpu_rev, "1.1");
-                }
-        } else {
-                switch (rev) {
-                case OMAP_REVBITS_00:
-                        strcpy(cpu_rev, "1.0");
-                        break;
-                case OMAP_REVBITS_01:
-                        strcpy(cpu_rev, "2.0");
-                        break;
-                case OMAP_REVBITS_02:
-                        strcpy(cpu_rev, "2.1");
-                        break;
-                case OMAP_REVBITS_03:
-                        strcpy(cpu_rev, "3.0");
-                        break;
-                case OMAP_REVBITS_04:
-                        strcpy(cpu_rev, "3.1");
-                        break;
-                case OMAP_REVBITS_05:
-                        /* FALLTHROUGH */
-                default:
-                        /* Use the latest known revision as default */
-                        strcpy(cpu_rev, "3.1.2");
-                }
        }
        /* Print verbose information */
@@ -533,6 +458,8 @@ static void __init omap3_cpuinfo(void)
 */
 void __init omap2_check_revision(void)
 {
+        const char *cpu_rev;
        /*
         * At this point we have an idea about the processor revision set
         * earlier with omap2_set_globals_tap().
@@ -540,7 +467,7 @@ void __init omap2_check_revision(void)
        if (cpu_is_omap24xx()) {
                omap24xx_check_revision();
        } else if (cpu_is_omap34xx()) {
-                omap3_check_revision();
+                omap3_check_revision(&cpu_rev);
                /* TI816X doesn't have feature register */
                if (!cpu_is_ti816x())
@@ -548,7 +475,7 @@ void __init omap2_check_revision(void)
                else
                        ti816x_check_features();
-                omap3_cpuinfo();
+                omap3_cpuinfo(cpu_rev);
                return;
        } else if (cpu_is_omap44xx()) {
                omap4_check_revision();
@@ -557,22 +484,6 @@ void __init omap2_check_revision(void)
        } else {
                pr_err("OMAP revision unknown, please fix!\n");
        }
-        /*
-         * OK, now we know the exact revision. Initialize omap_chip bits
-         * for powerdowmain and clockdomain code.
-         */
-        if (cpu_is_omap243x()) {
-                /* Currently only supports 2430ES2.1 and 2430-all */
-                omap_chip.oc |= CHIP_IS_OMAP2430;
-                return;
-        } else if (cpu_is_omap242x()) {
-                /* Currently only supports 2420ES2.1.1 and 2420-all */
-                omap_chip.oc |= CHIP_IS_OMAP2420;
-                return;
-        }
-        pr_err("Uninitialized omap_chip, please fix!\n");
 }
 /*
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index d6d01cb7f28a..a5d8dce2a70b 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -34,14 +34,16 @@
 #include "clock2xxx.h"
 #include "clock3xxx.h"
 #include "clock44xx.h"
-#include "io.h"
+#include <plat/common.h>
 #include <plat/omap-pm.h>
+#include "voltage.h"
 #include "powerdomain.h"
 #include "clockdomain.h"
 #include <plat/omap_hwmod.h>
 #include <plat/multi.h>
+#include <plat/common.h>
 /*
 * The machine specific code may provide the extra mapping besides the
@@ -238,26 +240,11 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
 };
 #endif
-static void __init _omap2_map_common_io(void)
-{
-        /* Normally devicemaps_init() would flush caches and tlb after
-         * mdesc->map_io(), but we must also do it here because of the CPU
-         * revision check below.
-         */
-        local_flush_tlb_all();
-        flush_cache_all();
-        omap2_check_revision();
-        omap_sram_init();
-        omap_init_consistent_dma_size();
-}
 #ifdef CONFIG_SOC_OMAP2420
 void __init omap242x_map_common_io(void)
 {
        iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
        iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
-        _omap2_map_common_io();
 }
 #endif
@@ -266,7 +253,6 @@ void __init omap243x_map_common_io(void)
 {
        iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
        iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
-        _omap2_map_common_io();
 }
 #endif
@@ -274,7 +260,6 @@ void __init omap243x_map_common_io(void)
 void __init omap34xx_map_common_io(void)
 {
        iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
-        _omap2_map_common_io();
 }
 #endif
@@ -282,7 +267,6 @@ void __init omap34xx_map_common_io(void)
 void __init omapti816x_map_common_io(void)
 {
        iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc));
-        _omap2_map_common_io();
 }
 #endif
@@ -290,7 +274,6 @@ void __init omapti816x_map_common_io(void)
 void __init omap44xx_map_common_io(void)
 {
        iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
-        _omap2_map_common_io();
 }
 #endif
@@ -336,29 +319,16 @@ static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
 /* See irq.c, omap4-common.c and entry-macro.S */
 void __iomem *omap_irq_base;
-void __init omap2_init_common_infrastructure(void)
+static void __init omap_common_init_early(void)
 {
-        u8 postsetup_state;
+        omap2_check_revision();
+        omap_ioremap_init();
+        omap_init_consistent_dma_size();
+}
-        if (cpu_is_omap242x()) {
+static void __init omap_hwmod_init_postsetup(void)
-                omap2xxx_powerdomains_init();
+{
-                omap2xxx_clockdomains_init();
+        u8 postsetup_state;
-                omap2420_hwmod_init();
-        } else if (cpu_is_omap243x()) {
-                omap2xxx_powerdomains_init();
-                omap2xxx_clockdomains_init();
-                omap2430_hwmod_init();
-        } else if (cpu_is_omap34xx()) {
-                omap3xxx_powerdomains_init();
-                omap3xxx_clockdomains_init();
-                omap3xxx_hwmod_init();
-        } else if (cpu_is_omap44xx()) {
-                omap44xx_powerdomains_init();
-                omap44xx_clockdomains_init();
-                omap44xx_hwmod_init();
-        } else {
-                pr_err("Could not init hwmod data - unknown SoC\n");
-        }
        /* Set the default postsetup state for all hwmods */
 #ifdef CONFIG_PM_RUNTIME
@@ -376,7 +346,7 @@ void __init omap2_init_common_infrastructure(void)
         * omap_hwmod_late_init(), so boards that desire full watchdog
         * coverage of kernel initialization can reprogram the
         * postsetup_state between the calls to
-         * omap2_init_common_infra() and omap2_init_common_devices().
+         * omap2_init_common_infra() and omap_sdrc_init().
         *
         * XXX ideally we could detect whether the MPU WDT was currently
         * enabled here and make this conditional
@@ -387,27 +357,101 @@ void __init omap2_init_common_infrastructure(void)
                                     &postsetup_state);
        omap_pm_if_early_init();
+}
-        if (cpu_is_omap2420())
+void __init omap2420_init_early(void)
-                omap2420_clk_init();
+{
-        else if (cpu_is_omap2430())
+        omap2_set_globals_242x();
-                omap2430_clk_init();
+        omap_common_init_early();
-        else if (cpu_is_omap34xx())
+        omap2xxx_voltagedomains_init();
-                omap3xxx_clk_init();
+        omap242x_powerdomains_init();
-        else if (cpu_is_omap44xx())
+        omap242x_clockdomains_init();
-                omap4xxx_clk_init();
+        omap2420_hwmod_init();
-        else
+        omap_hwmod_init_postsetup();
-                pr_err("Could not init clock framework - unknown SoC\n");
+        omap2420_clk_init();
 }
-void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
+void __init omap2430_init_early(void)
+{
+        omap2_set_globals_243x();
+        omap_common_init_early();
+        omap2xxx_voltagedomains_init();
+        omap243x_powerdomains_init();
+        omap243x_clockdomains_init();
+        omap2430_hwmod_init();
+        omap_hwmod_init_postsetup();
+        omap2430_clk_init();
+}
+/*
+ * Currently only board-omap3beagle.c should call this because of the
+ * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
+ */
+void __init omap3_init_early(void)
+{
+        omap2_set_globals_3xxx();
+        omap_common_init_early();
+        omap3xxx_voltagedomains_init();
+        omap3xxx_powerdomains_init();
+        omap3xxx_clockdomains_init();
+        omap3xxx_hwmod_init();
+        omap_hwmod_init_postsetup();
+        omap3xxx_clk_init();
+}
+void __init omap3430_init_early(void)
+{
+        omap3_init_early();
+}
+void __init omap35xx_init_early(void)
+{
+        omap3_init_early();
+}
+void __init omap3630_init_early(void)
+{
+        omap3_init_early();
+}
+void __init am35xx_init_early(void)
+{
+        omap3_init_early();
+}
+void __init ti816x_init_early(void)
+{
+        omap2_set_globals_ti816x();
+        omap_common_init_early();
+        omap3xxx_voltagedomains_init();
+        omap3xxx_powerdomains_init();
+        omap3xxx_clockdomains_init();
+        omap3xxx_hwmod_init();
+        omap_hwmod_init_postsetup();
+        omap3xxx_clk_init();
+}
+void __init omap4430_init_early(void)
+{
+        omap2_set_globals_443x();
+        omap_common_init_early();
+        omap44xx_voltagedomains_init();
+        omap44xx_powerdomains_init();
+        omap44xx_clockdomains_init();
+        omap44xx_hwmod_init();
+        omap_hwmod_init_postsetup();
+        omap4xxx_clk_init();
+}
+void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
                                      struct omap_sdrc_params *sdrc_cs1)
 {
+        omap_sram_init();
        if (cpu_is_omap24xx() || omap3_has_sdrc()) {
                omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
                _omap2_init_reprogram_sdrc();
        }
 }
 /*
diff --git a/arch/arm/mach-omap2/io.h b/arch/arm/mach-omap2/io.h
index fd230c6cded5..e69de29bb2d1 100644
--- a/arch/arm/mach-omap2/io.h
+++ b/arch/arm/mach-omap2/io.h
@@ -1,7 +0,0 @@
-#ifndef __MACH_OMAP2_IO_H__
-#define __MACH_OMAP2_IO_H__
-extern int __init omap_sram_init(void);
-#endif /*  __MACH_OMAP2_IO_H__ */
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 3a12f7586a4c..65f1be6a182c 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -165,8 +165,8 @@ static void __init omap_init_irq(u32 base, int nr_irqs)
                omap_irq_bank_init_one(bank);
-                for (i = 0, j = 0; i < bank->nr_irqs; i += 32, j += 0x20)
+                for (j = 0; j < bank->nr_irqs; j += 32)
-                        omap_alloc_gc(bank->base_reg + j, i, 32);
+                        omap_alloc_gc(bank->base_reg + j, j, 32);
                nr_of_irqs += bank->nr_irqs;
                nr_banks++;
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 4a6ef6ab8458..292eee3be15f 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -27,66 +27,69 @@
 #include "control.h"
-/* McBSP internal signal muxing functions */
+/*
+ * FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle.
+ * Sidetone needs non-gated ICLK and sidetone autoidle is broken.
+ */
+#include "cm2xxx_3xxx.h"
+#include "cm-regbits-34xx.h"
-void omap2_mcbsp1_mux_clkr_src(u8 mux)
+/* McBSP internal signal muxing function */
+static int omap2_mcbsp1_mux_rx_clk(struct device *dev, const char *signal,
+                                   const char *src)
 {
        u32 v;
        v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-        if (mux == CLKR_SRC_CLKR)
-                v &= ~OMAP2_MCBSP1_CLKR_MASK;
-        else if (mux == CLKR_SRC_CLKX)
-                v |= OMAP2_MCBSP1_CLKR_MASK;
-        omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
-}
-EXPORT_SYMBOL(omap2_mcbsp1_mux_clkr_src);
-void omap2_mcbsp1_mux_fsr_src(u8 mux)
+        if (!strcmp(signal, "clkr")) {
-{
+                if (!strcmp(src, "clkr"))
-        u32 v;
+                        v &= ~OMAP2_MCBSP1_CLKR_MASK;
+                else if (!strcmp(src, "clkx"))
+                        v |= OMAP2_MCBSP1_CLKR_MASK;
+                else
+                        return -EINVAL;
+        } else if (!strcmp(signal, "fsr")) {
+                if (!strcmp(src, "fsr"))
+                        v &= ~OMAP2_MCBSP1_FSR_MASK;
+                else if (!strcmp(src, "fsx"))
+                        v |= OMAP2_MCBSP1_FSR_MASK;
+                else
+                        return -EINVAL;
+        } else {
+                return -EINVAL;
+        }
-        v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-        if (mux == FSR_SRC_FSR)
-                v &= ~OMAP2_MCBSP1_FSR_MASK;
-        else if (mux == FSR_SRC_FSX)
-                v |= OMAP2_MCBSP1_FSR_MASK;
        omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
+        return 0;
 }
-EXPORT_SYMBOL(omap2_mcbsp1_mux_fsr_src);
 /* McBSP CLKS source switching function */
+static int omap2_mcbsp_set_clk_src(struct device *dev, struct clk *clk,
-int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
+                                   const char *src)
 {
-        struct omap_mcbsp *mcbsp;
        struct clk *fck_src;
        char *fck_src_name;
        int r;
-        if (!omap_mcbsp_check_valid_id(id)) {
+        if (!strcmp(src, "clks_ext"))
-                pr_err("%s: Invalid id (%d)\n", __func__, id + 1);
-                return -EINVAL;
-        }
-        mcbsp = id_to_mcbsp_ptr(id);
-        if (fck_src_id == MCBSP_CLKS_PAD_SRC)
                fck_src_name = "pad_fck";
-        else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
+        else if (!strcmp(src, "clks_fclk"))
                fck_src_name = "prcm_fck";
        else
                return -EINVAL;
-        fck_src = clk_get(mcbsp->dev, fck_src_name);
+        fck_src = clk_get(dev, fck_src_name);
        if (IS_ERR_OR_NULL(fck_src)) {
                pr_err("omap-mcbsp: %s: could not clk_get() %s\n", "clks",
                       fck_src_name);
                return -EINVAL;
        }
-        pm_runtime_put_sync(mcbsp->dev);
+        pm_runtime_put_sync(dev);
-        r = clk_set_parent(mcbsp->fclk, fck_src);
+        r = clk_set_parent(clk, fck_src);
        if (IS_ERR_VALUE(r)) {
                pr_err("omap-mcbsp: %s: could not clk_set_parent() to %s\n",
                       "clks", fck_src_name);
@@ -94,21 +97,30 @@ int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
                return -EINVAL;
        }
-        pm_runtime_get_sync(mcbsp->dev);
+        pm_runtime_get_sync(dev);
        clk_put(fck_src);
        return 0;
 }
-EXPORT_SYMBOL(omap2_mcbsp_set_clks_src);
-struct omap_device_pm_latency omap2_mcbsp_latency[] = {
+static int omap3_enable_st_clock(unsigned int id, bool enable)
-        {
+{
-                .deactivate_func = omap_device_idle_hwmods,
+        unsigned int w;
-                .activate_func   = omap_device_enable_hwmods,
-                .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+        /*
-        },
+         * Sidetone uses McBSP ICLK - which must not idle when sidetones
-};
+         * are enabled or sidetones start sounding ugly.
+         */
+        w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
+        if (enable)
+                w &= ~(1 << (id - 2));
+        else
+                w |= 1 << (id - 2);
+        omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
+        return 0;
+}
 static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
 {
@@ -116,7 +128,7 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
        char *name = "omap-mcbsp";
        struct omap_hwmod *oh_device[2];
        struct omap_mcbsp_platform_data *pdata = NULL;
-        struct omap_device *od;
+        struct platform_device *pdev;
        sscanf(oh->name, "mcbsp%d", &id);
@@ -126,7 +138,13 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
                return -ENOMEM;
        }
-        pdata->mcbsp_config_type = oh->class->rev;
+        pdata->reg_step = 4;
+        if (oh->class->rev < MCBSP_CONFIG_TYPE2) {
+                pdata->reg_size = 2;
+        } else {
+                pdata->reg_size = 4;
+                pdata->has_ccr = true;
+        }
        if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
                if (id == 2)
@@ -137,22 +155,28 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
                        pdata->buffer_size = 0x80;
        }
+        if (oh->class->rev >= MCBSP_CONFIG_TYPE3)
+                pdata->has_wakeup = true;
        oh_device[0] = oh;
        if (oh->dev_attr) {
                oh_device[1] = omap_hwmod_lookup((
                (struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone);
+                pdata->enable_st_clock = omap3_enable_st_clock;
                count++;
        }
-        od = omap_device_build_ss(name, id, oh_device, count, pdata,
+        pdev = omap_device_build_ss(name, id, oh_device, count, pdata,
-                                sizeof(*pdata), omap2_mcbsp_latency,
+                                sizeof(*pdata), NULL, 0, false);
-                                ARRAY_SIZE(omap2_mcbsp_latency), false);
        kfree(pdata);
-        if (IS_ERR(od))  {
+        if (IS_ERR(pdev))  {
                pr_err("%s: Can't build omap_device for %s:%s.\n", __func__,
                                        name, oh->name);
-                return PTR_ERR(od);
+                return PTR_ERR(pdev);
        }
+        pdata->set_clk_src = omap2_mcbsp_set_clk_src;
+        if (id == 1)
+                pdata->mux_signal = omap2_mcbsp1_mux_rx_clk;
        omap_mcbsp_count++;
        return 0;
 }
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 889464dc7b2d..4412ddb7b3f6 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -102,8 +102,11 @@ void __init smp_init_cpus(void)
 {
        unsigned int i, ncores;
-        /* Never released */
+        /*
-        scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256);
+         * Currently we can't call ioremap here because
+         * SoC detection won't work until after init_early.
+         */
+        scu_base =  OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE);
        BUG_ON(!scu_base);
        ncores = scu_get_core_count(scu_base);
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 84cc0bdda3ae..d71380705080 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1954,9 +1954,6 @@ int __init omap_hwmod_register(struct omap_hwmod **ohs)
        i = 0;
        do {
-                if (!omap_chip_is(ohs[i]->omap_chip))
-                        continue;
                r = _register(ohs[i]);
                WARN(r, "omap_hwmod: %s: _register returned %d\n", ohs[i]->name,
                     r);
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index a015c69068f6..6d7206213525 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -100,7 +100,6 @@ static struct omap_hwmod omap2420_l3_main_hwmod = {
        .masters_cnt    = ARRAY_SIZE(omap2420_l3_main_masters),
        .slaves         = omap2420_l3_main_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_l3_main_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -206,7 +205,6 @@ static struct omap_hwmod omap2420_l4_core_hwmod = {
        .masters_cnt    = ARRAY_SIZE(omap2420_l4_core_masters),
        .slaves         = omap2420_l4_core_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_l4_core_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -227,7 +225,6 @@ static struct omap_hwmod omap2420_l4_wkup_hwmod = {
        .masters_cnt    = ARRAY_SIZE(omap2420_l4_wkup_masters),
        .slaves         = omap2420_l4_wkup_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_l4_wkup_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -243,7 +240,6 @@ static struct omap_hwmod omap2420_mpu_hwmod = {
        .main_clk       = "mpu_ck",
        .masters        = omap2420_mpu_masters,
        .masters_cnt    = ARRAY_SIZE(omap2420_mpu_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 /*
@@ -271,7 +267,16 @@ static struct omap_hwmod omap2420_iva_hwmod = {
        .class          = &iva_hwmod_class,
        .masters        = omap2420_iva_masters,
        .masters_cnt    = ARRAY_SIZE(omap2420_iva_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+/* always-on timers dev attribute */
+static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
+        .timer_capability       = OMAP_TIMER_ALWON,
+};
+/* pwm timers dev attribute */
+static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
+        .timer_capability       = OMAP_TIMER_HAS_PWM,
 };
 /* timer1 */
@@ -314,10 +319,10 @@ static struct omap_hwmod omap2420_timer1_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap2420_timer1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_timer1_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 /* timer2 */
@@ -351,10 +356,10 @@ static struct omap_hwmod omap2420_timer2_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap2420_timer2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_timer2_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 /* timer3 */
@@ -388,10 +393,10 @@ static struct omap_hwmod omap2420_timer3_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap2420_timer3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_timer3_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 /* timer4 */
@@ -425,10 +430,10 @@ static struct omap_hwmod omap2420_timer4_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap2420_timer4_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_timer4_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 /* timer5 */
@@ -462,10 +467,10 @@ static struct omap_hwmod omap2420_timer5_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap2420_timer5_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_timer5_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
@@ -500,10 +505,10 @@ static struct omap_hwmod omap2420_timer6_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap2420_timer6_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_timer6_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 /* timer7 */
@@ -537,10 +542,10 @@ static struct omap_hwmod omap2420_timer7_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap2420_timer7_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_timer7_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 /* timer8 */
@@ -574,10 +579,10 @@ static struct omap_hwmod omap2420_timer8_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap2420_timer8_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_timer8_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 /* timer9 */
@@ -611,10 +616,10 @@ static struct omap_hwmod omap2420_timer9_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
                },
        },
+        .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap2420_timer9_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_timer9_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 /* timer10 */
@@ -648,10 +653,10 @@ static struct omap_hwmod omap2420_timer10_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
                },
        },
+        .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap2420_timer10_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_timer10_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 /* timer11 */
@@ -685,10 +690,10 @@ static struct omap_hwmod omap2420_timer11_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
                },
        },
+        .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap2420_timer11_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_timer11_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 /* timer12 */
@@ -722,10 +727,10 @@ static struct omap_hwmod omap2420_timer12_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
                },
        },
+        .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap2420_timer12_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_timer12_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 /* l4_wkup -> wd_timer2 */
@@ -766,7 +771,6 @@ static struct omap_hwmod omap2420_wd_timer2_hwmod = {
        },
        .slaves         = omap2420_wd_timer2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_wd_timer2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 /* UART1 */
@@ -792,7 +796,6 @@ static struct omap_hwmod omap2420_uart1_hwmod = {
        .slaves         = omap2420_uart1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_uart1_slaves),
        .class          = &omap2_uart_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 /* UART2 */
@@ -818,7 +821,6 @@ static struct omap_hwmod omap2420_uart2_hwmod = {
        .slaves         = omap2420_uart2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_uart2_slaves),
        .class          = &omap2_uart_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 /* UART3 */
@@ -844,7 +846,6 @@ static struct omap_hwmod omap2420_uart3_hwmod = {
        .slaves         = omap2420_uart3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_uart3_slaves),
        .class          = &omap2_uart_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 /* dss */
@@ -898,7 +899,6 @@ static struct omap_hwmod omap2420_dss_core_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2420_dss_slaves),
        .masters        = omap2420_dss_masters,
        .masters_cnt    = ARRAY_SIZE(omap2420_dss_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -938,7 +938,6 @@ static struct omap_hwmod omap2420_dss_dispc_hwmod = {
        },
        .slaves         = omap2420_dss_dispc_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_dss_dispc_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -975,7 +974,6 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
        },
        .slaves         = omap2420_dss_rfbi_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_dss_rfbi_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -1013,7 +1011,6 @@ static struct omap_hwmod omap2420_dss_venc_hwmod = {
        },
        .slaves         = omap2420_dss_venc_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_dss_venc_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -1064,7 +1061,6 @@ static struct omap_hwmod omap2420_i2c1_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2420_i2c1_slaves),
        .class          = &i2c_class,
        .dev_attr       = &i2c_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
        .flags          = HWMOD_16BIT_REG,
 };
@@ -1092,7 +1088,6 @@ static struct omap_hwmod omap2420_i2c2_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2420_i2c2_slaves),
        .class          = &i2c_class,
        .dev_attr       = &i2c_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
        .flags          = HWMOD_16BIT_REG,
 };
@@ -1197,7 +1192,6 @@ static struct omap_hwmod omap2420_gpio1_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2420_gpio1_slaves),
        .class          = &omap2xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 /* gpio2 */
@@ -1223,7 +1217,6 @@ static struct omap_hwmod omap2420_gpio2_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2420_gpio2_slaves),
        .class          = &omap2xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 /* gpio3 */
@@ -1249,7 +1242,6 @@ static struct omap_hwmod omap2420_gpio3_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2420_gpio3_slaves),
        .class          = &omap2xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 /* gpio4 */
@@ -1275,7 +1267,6 @@ static struct omap_hwmod omap2420_gpio4_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2420_gpio4_slaves),
        .class          = &omap2xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 /* dma attributes */
@@ -1322,7 +1313,6 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
        .masters        = omap2420_dma_system_masters,
        .masters_cnt    = ARRAY_SIZE(omap2420_dma_system_masters),
        .dev_attr       = &dma_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -1363,7 +1353,6 @@ static struct omap_hwmod omap2420_mailbox_hwmod = {
        },
        .slaves         = omap2420_mailbox_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_mailbox_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 /* mcspi1 */
@@ -1393,7 +1382,6 @@ static struct omap_hwmod omap2420_mcspi1_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2420_mcspi1_slaves),
        .class          = &omap2xxx_mcspi_class,
        .dev_attr       = &omap_mcspi1_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 /* mcspi2 */
@@ -1423,7 +1411,6 @@ static struct omap_hwmod omap2420_mcspi2_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2420_mcspi2_slaves),
        .class          = &omap2xxx_mcspi_class,
        .dev_attr       = &omap_mcspi2_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 /*
@@ -1473,7 +1460,6 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
        },
        .slaves         = omap2420_mcbsp1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_mcbsp1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 /* mcbsp2 */
@@ -1514,7 +1500,6 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = {
        },
        .slaves         = omap2420_mcbsp2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_mcbsp2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 static __initdata struct omap_hwmod *omap2420_hwmods[] = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 408193d8e044..a2580d01c3ff 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -110,7 +110,6 @@ static struct omap_hwmod omap2430_l3_main_hwmod = {
        .masters_cnt    = ARRAY_SIZE(omap2430_l3_main_masters),
        .slaves         = omap2430_l3_main_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_l3_main_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -250,7 +249,6 @@ static struct omap_hwmod omap2430_l4_core_hwmod = {
        .masters_cnt    = ARRAY_SIZE(omap2430_l4_core_masters),
        .slaves         = omap2430_l4_core_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_l4_core_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -301,7 +299,6 @@ static struct omap_hwmod omap2430_l4_wkup_hwmod = {
        .masters_cnt    = ARRAY_SIZE(omap2430_l4_wkup_masters),
        .slaves         = omap2430_l4_wkup_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_l4_wkup_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -317,7 +314,6 @@ static struct omap_hwmod omap2430_mpu_hwmod = {
        .main_clk       = "mpu_ck",
        .masters        = omap2430_mpu_masters,
        .masters_cnt    = ARRAY_SIZE(omap2430_mpu_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /*
@@ -345,7 +341,16 @@ static struct omap_hwmod omap2430_iva_hwmod = {
        .class          = &iva_hwmod_class,
        .masters        = omap2430_iva_masters,
        .masters_cnt    = ARRAY_SIZE(omap2430_iva_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+/* always-on timers dev attribute */
+static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
+        .timer_capability       = OMAP_TIMER_ALWON,
+};
+/* pwm timers dev attribute */
+static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
+        .timer_capability       = OMAP_TIMER_HAS_PWM,
 };
 /* timer1 */
@@ -388,10 +393,10 @@ static struct omap_hwmod omap2430_timer1_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap2430_timer1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_timer1_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 /* timer2 */
@@ -425,10 +430,10 @@ static struct omap_hwmod omap2430_timer2_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap2430_timer2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_timer2_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 /* timer3 */
@@ -462,10 +467,10 @@ static struct omap_hwmod omap2430_timer3_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap2430_timer3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_timer3_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 /* timer4 */
@@ -499,10 +504,10 @@ static struct omap_hwmod omap2430_timer4_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap2430_timer4_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_timer4_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 /* timer5 */
@@ -536,10 +541,10 @@ static struct omap_hwmod omap2430_timer5_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap2430_timer5_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_timer5_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 /* timer6 */
@@ -573,10 +578,10 @@ static struct omap_hwmod omap2430_timer6_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap2430_timer6_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_timer6_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 /* timer7 */
@@ -610,10 +615,10 @@ static struct omap_hwmod omap2430_timer7_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap2430_timer7_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_timer7_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 /* timer8 */
@@ -647,10 +652,10 @@ static struct omap_hwmod omap2430_timer8_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap2430_timer8_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_timer8_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 /* timer9 */
@@ -684,10 +689,10 @@ static struct omap_hwmod omap2430_timer9_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
                },
        },
+        .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap2430_timer9_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_timer9_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 /* timer10 */
@@ -721,10 +726,10 @@ static struct omap_hwmod omap2430_timer10_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
                },
        },
+        .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap2430_timer10_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_timer10_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 /* timer11 */
@@ -758,10 +763,10 @@ static struct omap_hwmod omap2430_timer11_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
                },
        },
+        .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap2430_timer11_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_timer11_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 /* timer12 */
@@ -795,10 +800,10 @@ static struct omap_hwmod omap2430_timer12_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
                },
        },
+        .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap2430_timer12_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_timer12_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 /* l4_wkup -> wd_timer2 */
@@ -839,7 +844,6 @@ static struct omap_hwmod omap2430_wd_timer2_hwmod = {
        },
        .slaves         = omap2430_wd_timer2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_wd_timer2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* UART1 */
@@ -865,7 +869,6 @@ static struct omap_hwmod omap2430_uart1_hwmod = {
        .slaves         = omap2430_uart1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_uart1_slaves),
        .class          = &omap2_uart_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* UART2 */
@@ -891,7 +894,6 @@ static struct omap_hwmod omap2430_uart2_hwmod = {
        .slaves         = omap2430_uart2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_uart2_slaves),
        .class          = &omap2_uart_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* UART3 */
@@ -917,7 +919,6 @@ static struct omap_hwmod omap2430_uart3_hwmod = {
        .slaves         = omap2430_uart3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_uart3_slaves),
        .class          = &omap2_uart_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* dss */
@@ -965,7 +966,6 @@ static struct omap_hwmod omap2430_dss_core_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2430_dss_slaves),
        .masters        = omap2430_dss_masters,
        .masters_cnt    = ARRAY_SIZE(omap2430_dss_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -999,7 +999,6 @@ static struct omap_hwmod omap2430_dss_dispc_hwmod = {
        },
        .slaves         = omap2430_dss_dispc_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_dss_dispc_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -1030,7 +1029,6 @@ static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
        },
        .slaves         = omap2430_dss_rfbi_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_dss_rfbi_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -1062,7 +1060,6 @@ static struct omap_hwmod omap2430_dss_venc_hwmod = {
        },
        .slaves         = omap2430_dss_venc_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_dss_venc_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -1123,7 +1120,6 @@ static struct omap_hwmod omap2430_i2c1_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2430_i2c1_slaves),
        .class          = &i2c_class,
        .dev_attr       = &i2c_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* I2C2 */
@@ -1151,7 +1147,6 @@ static struct omap_hwmod omap2430_i2c2_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2430_i2c2_slaves),
        .class          = &i2c_class,
        .dev_attr       = &i2c_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* l4_wkup -> gpio1 */
@@ -1273,7 +1268,6 @@ static struct omap_hwmod omap2430_gpio1_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2430_gpio1_slaves),
        .class          = &omap2xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* gpio2 */
@@ -1299,7 +1293,6 @@ static struct omap_hwmod omap2430_gpio2_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2430_gpio2_slaves),
        .class          = &omap2xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* gpio3 */
@@ -1325,7 +1318,6 @@ static struct omap_hwmod omap2430_gpio3_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2430_gpio3_slaves),
        .class          = &omap2xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* gpio4 */
@@ -1351,7 +1343,6 @@ static struct omap_hwmod omap2430_gpio4_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2430_gpio4_slaves),
        .class          = &omap2xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* gpio5 */
@@ -1382,7 +1373,6 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2430_gpio5_slaves),
        .class          = &omap2xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* dma attributes */
@@ -1429,7 +1419,6 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
        .masters        = omap2430_dma_system_masters,
        .masters_cnt    = ARRAY_SIZE(omap2430_dma_system_masters),
        .dev_attr       = &dma_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -1469,7 +1458,6 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
        },
        .slaves         = omap2430_mailbox_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_mailbox_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* mcspi1 */
@@ -1499,7 +1487,6 @@ static struct omap_hwmod omap2430_mcspi1_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi1_slaves),
        .class          = &omap2xxx_mcspi_class,
        .dev_attr       = &omap_mcspi1_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* mcspi2 */
@@ -1529,7 +1516,6 @@ static struct omap_hwmod omap2430_mcspi2_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi2_slaves),
        .class          = &omap2xxx_mcspi_class,
        .dev_attr       = &omap_mcspi2_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* mcspi3 */
@@ -1572,7 +1558,6 @@ static struct omap_hwmod omap2430_mcspi3_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi3_slaves),
        .class          = &omap2xxx_mcspi_class,
        .dev_attr       = &omap_mcspi3_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /*
@@ -1628,7 +1613,6 @@ static struct omap_hwmod omap2430_usbhsotg_hwmod = {
         */
        .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
                                | HWMOD_SWSUP_MSTANDBY,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 /*
@@ -1689,7 +1673,6 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = {
        },
        .slaves         = omap2430_mcbsp1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* mcbsp2 */
@@ -1731,7 +1714,6 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = {
        },
        .slaves         = omap2430_mcbsp2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* mcbsp3 */
@@ -1783,7 +1765,6 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = {
        },
        .slaves         = omap2430_mcbsp3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp3_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* mcbsp4 */
@@ -1841,7 +1822,6 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = {
        },
        .slaves         = omap2430_mcbsp4_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp4_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* mcbsp5 */
@@ -1899,7 +1879,6 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod = {
        },
        .slaves         = omap2430_mcbsp5_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp5_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* MMC/SD/SDIO common */
@@ -1966,7 +1945,6 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
        .slaves         = omap2430_mmc1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_mmc1_slaves),
        .class          = &omap2430_mmc_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* MMC/SD/SDIO2 */
@@ -2010,7 +1988,6 @@ static struct omap_hwmod omap2430_mmc2_hwmod = {
        .slaves         = omap2430_mmc2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_mmc2_slaves),
        .class          = &omap2430_mmc_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 static __initdata struct omap_hwmod *omap2430_hwmods[] = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 25bf43b5a4ec..3008e1672c7a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -156,7 +156,6 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod = {
        .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
        .slaves         = omap3xxx_l3_main_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_l3_main_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -459,7 +458,6 @@ static struct omap_hwmod omap3xxx_l4_core_hwmod = {
        .class          = &l4_hwmod_class,
        .slaves         = omap3xxx_l4_core_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -474,7 +472,6 @@ static struct omap_hwmod omap3xxx_l4_per_hwmod = {
        .class          = &l4_hwmod_class,
        .slaves         = omap3xxx_l4_per_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -489,7 +486,6 @@ static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
        .class          = &l4_hwmod_class,
        .slaves         = omap3xxx_l4_wkup_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -505,7 +501,6 @@ static struct omap_hwmod omap3xxx_mpu_hwmod = {
        .main_clk       = "arm_fck",
        .masters        = omap3xxx_mpu_masters,
        .masters_cnt    = ARRAY_SIZE(omap3xxx_mpu_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /*
@@ -533,7 +528,6 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
        .class          = &iva_hwmod_class,
        .masters        = omap3xxx_iva_masters,
        .masters_cnt    = ARRAY_SIZE(omap3xxx_iva_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 /* timer class */
@@ -570,6 +564,21 @@ static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
        .rev =  OMAP_TIMER_IP_VERSION_1,
 };
+/* secure timers dev attribute */
+static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
+        .timer_capability       = OMAP_TIMER_SECURE,
+};
+/* always-on timers dev attribute */
+static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
+        .timer_capability       = OMAP_TIMER_ALWON,
+};
+/* pwm timers dev attribute */
+static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
+        .timer_capability       = OMAP_TIMER_HAS_PWM,
+};
 /* timer1 */
 static struct omap_hwmod omap3xxx_timer1_hwmod;
@@ -610,10 +619,10 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap3xxx_timer1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer1_slaves),
        .class          = &omap3xxx_timer_1ms_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 /* timer2 */
@@ -656,10 +665,10 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap3xxx_timer2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer2_slaves),
        .class          = &omap3xxx_timer_1ms_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 /* timer3 */
@@ -702,10 +711,10 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap3xxx_timer3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer3_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 /* timer4 */
@@ -748,10 +757,10 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap3xxx_timer4_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer4_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 /* timer5 */
@@ -794,10 +803,10 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap3xxx_timer5_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer5_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 /* timer6 */
@@ -840,10 +849,10 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap3xxx_timer6_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer6_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 /* timer7 */
@@ -886,10 +895,10 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap3xxx_timer7_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer7_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 /* timer8 */
@@ -932,10 +941,10 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
                },
        },
+        .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap3xxx_timer8_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer8_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 /* timer9 */
@@ -978,10 +987,10 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
                },
        },
+        .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap3xxx_timer9_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer9_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 /* timer10 */
@@ -1015,10 +1024,10 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
                },
        },
+        .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap3xxx_timer10_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer10_slaves),
        .class          = &omap3xxx_timer_1ms_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 /* timer11 */
@@ -1052,10 +1061,10 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
                },
        },
+        .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap3xxx_timer11_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer11_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 /* timer12*/
@@ -1102,10 +1111,10 @@ static struct omap_hwmod omap3xxx_timer12_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
                },
        },
+        .dev_attr       = &capability_secure_dev_attr,
        .slaves         = omap3xxx_timer12_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer12_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 /* l4_wkup -> wd_timer2 */
@@ -1182,7 +1191,6 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
        },
        .slaves         = omap3xxx_wd_timer2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
        /*
         * XXX: Use software supervised mode, HW supervised smartidle seems to
         * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
@@ -1213,7 +1221,6 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
        .slaves         = omap3xxx_uart1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
        .class          = &omap2_uart_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* UART2 */
@@ -1239,7 +1246,6 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
        .slaves         = omap3xxx_uart2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
        .class          = &omap2_uart_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* UART3 */
@@ -1265,7 +1271,6 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
        .slaves         = omap3xxx_uart3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
        .class          = &omap2_uart_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* UART4 */
@@ -1302,7 +1307,6 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = {
        .slaves         = omap3xxx_uart4_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
        .class          = &omap2_uart_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
 };
 static struct omap_hwmod_class i2c_class = {
@@ -1390,7 +1394,6 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap3430es1_dss_slaves),
        .masters        = omap3xxx_dss_masters,
        .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -1415,8 +1418,6 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_slaves),
        .masters        = omap3xxx_dss_masters,
        .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
-                                CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
 };
 /* l4_core -> dss_dispc */
@@ -1454,9 +1455,6 @@ static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
        },
        .slaves         = omap3xxx_dss_dispc_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
-                                CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
-                                CHIP_GE_OMAP3630ES1_1),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -1518,9 +1516,6 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
        },
        .slaves         = omap3xxx_dss_dsi1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
-                                CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
-                                CHIP_GE_OMAP3630ES1_1),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -1558,9 +1553,6 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
        },
        .slaves         = omap3xxx_dss_rfbi_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
-                                CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
-                                CHIP_GE_OMAP3630ES1_1),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -1599,9 +1591,6 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
        },
        .slaves         = omap3xxx_dss_venc_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
-                                CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
-                                CHIP_GE_OMAP3630ES1_1),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -1637,7 +1626,6 @@ static struct omap_hwmod omap3xxx_i2c1_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c1_slaves),
        .class          = &i2c_class,
        .dev_attr       = &i2c1_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* I2C2 */
@@ -1672,7 +1660,6 @@ static struct omap_hwmod omap3xxx_i2c2_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c2_slaves),
        .class          = &i2c_class,
        .dev_attr       = &i2c2_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* I2C3 */
@@ -1718,7 +1705,6 @@ static struct omap_hwmod omap3xxx_i2c3_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c3_slaves),
        .class          = &i2c_class,
        .dev_attr       = &i2c3_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* l4_wkup -> gpio1 */
@@ -1880,7 +1866,6 @@ static struct omap_hwmod omap3xxx_gpio1_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio1_slaves),
        .class          = &omap3xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* gpio2 */
@@ -1912,7 +1897,6 @@ static struct omap_hwmod omap3xxx_gpio2_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio2_slaves),
        .class          = &omap3xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* gpio3 */
@@ -1944,7 +1928,6 @@ static struct omap_hwmod omap3xxx_gpio3_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio3_slaves),
        .class          = &omap3xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* gpio4 */
@@ -1976,7 +1959,6 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio4_slaves),
        .class          = &omap3xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* gpio5 */
@@ -2013,7 +1995,6 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio5_slaves),
        .class          = &omap3xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* gpio6 */
@@ -2050,7 +2031,6 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio6_slaves),
        .class          = &omap3xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* dma_system -> L3 */
@@ -2134,7 +2114,6 @@ static struct omap_hwmod omap3xxx_dma_system_hwmod = {
        .masters        = omap3xxx_dma_system_masters,
        .masters_cnt    = ARRAY_SIZE(omap3xxx_dma_system_masters),
        .dev_attr       = &dma_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -2207,7 +2186,6 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
        },
        .slaves         = omap3xxx_mcbsp1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* mcbsp2 */
@@ -2264,7 +2242,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
        .slaves         = omap3xxx_mcbsp2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
        .dev_attr       = &omap34xx_mcbsp2_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* mcbsp3 */
@@ -2321,7 +2298,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
        .slaves         = omap3xxx_mcbsp3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
        .dev_attr       = &omap34xx_mcbsp3_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* mcbsp4 */
@@ -2379,7 +2355,6 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
        },
        .slaves         = omap3xxx_mcbsp4_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* mcbsp5 */
@@ -2437,7 +2412,6 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
        },
        .slaves         = omap3xxx_mcbsp5_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* 'mcbsp sidetone' class */
@@ -2498,7 +2472,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
        },
        .slaves         = omap3xxx_mcbsp2_sidetone_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* mcbsp3_sidetone */
@@ -2547,7 +2520,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
        },
        .slaves         = omap3xxx_mcbsp3_sidetone_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
@@ -2597,7 +2569,7 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
        .name           = "sr1_hwmod",
        .class          = &omap34xx_smartreflex_hwmod_class,
        .main_clk       = "sr1_fck",
-        .vdd_name       = "mpu",
+        .vdd_name       = "mpu_iva",
        .prcm           = {
                .omap2 = {
                        .prcm_reg_id = 1,
@@ -2609,9 +2581,6 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
        },
        .slaves         = omap3_sr1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
-                                        CHIP_IS_OMAP3430ES3_0 |
-                                        CHIP_IS_OMAP3430ES3_1),
        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
@@ -2619,7 +2588,7 @@ static struct omap_hwmod omap36xx_sr1_hwmod = {
        .name           = "sr1_hwmod",
        .class          = &omap36xx_smartreflex_hwmod_class,
        .main_clk       = "sr1_fck",
-        .vdd_name       = "mpu",
+        .vdd_name       = "mpu_iva",
        .prcm           = {
                .omap2 = {
                        .prcm_reg_id = 1,
@@ -2631,7 +2600,6 @@ static struct omap_hwmod omap36xx_sr1_hwmod = {
        },
        .slaves         = omap3_sr1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
 };
 /* SR2 */
@@ -2655,9 +2623,6 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
        },
        .slaves         = omap3_sr2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
-                                        CHIP_IS_OMAP3430ES3_0 |
-                                        CHIP_IS_OMAP3430ES3_1),
        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
@@ -2677,7 +2642,6 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
        },
        .slaves         = omap3_sr2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
 };
 /*
@@ -2745,7 +2709,6 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
        },
        .slaves         = omap3xxx_mailbox_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mailbox_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* l4 core -> mcspi1 interface */
@@ -2843,7 +2806,6 @@ static struct omap_hwmod omap34xx_mcspi1 = {
        .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi1_slaves),
        .class          = &omap34xx_mcspi_class,
        .dev_attr       = &omap_mcspi1_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* mcspi2 */
@@ -2873,7 +2835,6 @@ static struct omap_hwmod omap34xx_mcspi2 = {
        .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi2_slaves),
        .class          = &omap34xx_mcspi_class,
        .dev_attr       = &omap_mcspi2_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* mcspi3 */
@@ -2916,7 +2877,6 @@ static struct omap_hwmod omap34xx_mcspi3 = {
        .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi3_slaves),
        .class          = &omap34xx_mcspi_class,
        .dev_attr       = &omap_mcspi3_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* SPI4 */
@@ -2957,7 +2917,6 @@ static struct omap_hwmod omap34xx_mcspi4 = {
        .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi4_slaves),
        .class          = &omap34xx_mcspi_class,
        .dev_attr       = &omap_mcspi4_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /*
@@ -3014,7 +2973,6 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
         */
        .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
                                | HWMOD_SWSUP_MSTANDBY,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 /* usb_otg_hs */
@@ -3042,7 +3000,6 @@ static struct omap_hwmod am35xx_usbhsotg_hwmod = {
        .slaves         = am35xx_usbhsotg_slaves,
        .slaves_cnt     = ARRAY_SIZE(am35xx_usbhsotg_slaves),
        .class          = &am35xx_usbotg_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
 };
 /* MMC/SD/SDIO common */
@@ -3108,7 +3065,6 @@ static struct omap_hwmod omap3xxx_mmc1_hwmod = {
        .slaves         = omap3xxx_mmc1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
        .class          = &omap34xx_mmc_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* MMC/SD/SDIO2 */
@@ -3151,7 +3107,6 @@ static struct omap_hwmod omap3xxx_mmc2_hwmod = {
        .slaves         = omap3xxx_mmc2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
        .class          = &omap34xx_mmc_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* MMC/SD/SDIO3 */
@@ -3193,7 +3148,6 @@ static struct omap_hwmod omap3xxx_mmc3_hwmod = {
        .slaves         = omap3xxx_mmc3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc3_slaves),
        .class          = &omap34xx_mmc_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
@@ -3224,10 +3178,7 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
        &omap3xxx_uart1_hwmod,
        &omap3xxx_uart2_hwmod,
        &omap3xxx_uart3_hwmod,
-        &omap3xxx_uart4_hwmod,
        /* dss class */
-        &omap3430es1_dss_core_hwmod,
-        &omap3xxx_dss_core_hwmod,
        &omap3xxx_dss_dispc_hwmod,
        &omap3xxx_dss_dsi1_hwmod,
        &omap3xxx_dss_rfbi_hwmod,
@@ -3239,9 +3190,6 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
        &omap3xxx_i2c3_hwmod,
        &omap34xx_sr1_hwmod,
        &omap34xx_sr2_hwmod,
-        &omap36xx_sr1_hwmod,
-        &omap36xx_sr2_hwmod,
        /* gpio class */
        &omap3xxx_gpio1_hwmod,
@@ -3272,16 +3220,96 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
        &omap34xx_mcspi3,
        &omap34xx_mcspi4,
-        /* usbotg class */
+        NULL,
+};
+/* 3430ES1-only hwmods */
+static __initdata struct omap_hwmod *omap3430es1_hwmods[] = {
+        &omap3430es1_dss_core_hwmod,
+        NULL
+};
+/* 3430ES2+-only hwmods */
+static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = {
+        &omap3xxx_dss_core_hwmod,
        &omap3xxx_usbhsotg_hwmod,
+        NULL
+};
-        /* usbotg for am35x */
+/* 34xx-only hwmods (all ES revisions) */
-        &am35xx_usbhsotg_hwmod,
+static __initdata struct omap_hwmod *omap34xx_hwmods[] = {
+        &omap34xx_sr1_hwmod,
+        &omap34xx_sr2_hwmod,
+        NULL
+};
-        NULL,
+/* 36xx-only hwmods (all ES revisions) */
+static __initdata struct omap_hwmod *omap36xx_hwmods[] = {
+        &omap3xxx_uart4_hwmod,
+        &omap3xxx_dss_core_hwmod,
+        &omap36xx_sr1_hwmod,
+        &omap36xx_sr2_hwmod,
+        &omap3xxx_usbhsotg_hwmod,
+        NULL
+};
+static __initdata struct omap_hwmod *am35xx_hwmods[] = {
+        &omap3xxx_dss_core_hwmod, /* XXX ??? */
+        &am35xx_usbhsotg_hwmod,
+        NULL
 };
 int __init omap3xxx_hwmod_init(void)
 {
-        return omap_hwmod_register(omap3xxx_hwmods);
+        int r;
+        struct omap_hwmod **h = NULL;
+        unsigned int rev;
+        /* Register hwmods common to all OMAP3 */
+        r = omap_hwmod_register(omap3xxx_hwmods);
+        if (!r)
+                return r;
+        rev = omap_rev();
+        /*
+         * Register hwmods common to individual OMAP3 families, all
+         * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
+         * All possible revisions should be included in this conditional.
+         */
+        if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
+            rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
+            rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
+                h = omap34xx_hwmods;
+        } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) {
+                h = am35xx_hwmods;
+        } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
+                   rev == OMAP3630_REV_ES1_2) {
+                h = omap36xx_hwmods;
+        } else {
+                WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
+                return -EINVAL;
+        };
+        r = omap_hwmod_register(h);
+        if (!r)
+                return r;
+        /*
+         * Register hwmods specific to certain ES levels of a
+         * particular family of silicon (e.g., 34xx ES1.0)
+         */
+        h = NULL;
+        if (rev == OMAP3430_REV_ES1_0) {
+                h = omap3430es1_hwmods;
+        } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
+                   rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
+                   rev == OMAP3430_REV_ES3_1_2) {
+                h = omap3430es2plus_hwmods;
+        };
+        if (h)
+                r = omap_hwmod_register(h);
+        return r;
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 79325c65c23c..7695e5d43316 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -29,6 +29,7 @@
 #include <plat/mcbsp.h>
 #include <plat/mmc.h>
 #include <plat/i2c.h>
+#include <plat/dmtimer.h>
 #include "omap_hwmod_common_data.h"
@@ -133,7 +134,6 @@ static struct omap_hwmod omap44xx_dmm_hwmod = {
        .slaves         = omap44xx_dmm_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
        .mpu_irqs       = omap44xx_dmm_irqs,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -189,7 +189,6 @@ static struct omap_hwmod omap44xx_emif_fw_hwmod = {
        },
        .slaves         = omap44xx_emif_fw_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -236,7 +235,6 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = {
        },
        .slaves         = omap44xx_l3_instr_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* l3_main_1 */
@@ -336,7 +334,6 @@ static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
        },
        .slaves         = omap44xx_l3_main_1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* l3_main_2 */
@@ -438,7 +435,6 @@ static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
        },
        .slaves         = omap44xx_l3_main_2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* l3_main_3 */
@@ -496,7 +492,6 @@ static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
        },
        .slaves         = omap44xx_l3_main_3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -559,7 +554,6 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod = {
        },
        .slaves         = omap44xx_l4_abe_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* l4_cfg */
@@ -588,7 +582,6 @@ static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
        },
        .slaves         = omap44xx_l4_cfg_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* l4_per */
@@ -617,7 +610,6 @@ static struct omap_hwmod omap44xx_l4_per_hwmod = {
        },
        .slaves         = omap44xx_l4_per_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* l4_wkup */
@@ -646,7 +638,6 @@ static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
        },
        .slaves         = omap44xx_l4_wkup_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -677,7 +668,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
        .clkdm_name     = "mpuss_clkdm",
        .slaves         = omap44xx_mpu_private_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -828,7 +818,6 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap44xx_aess_slaves),
        .masters        = omap44xx_aess_masters,
        .masters_cnt    = ARRAY_SIZE(omap44xx_aess_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -856,7 +845,6 @@ static struct omap_hwmod omap44xx_bandgap_hwmod = {
        },
        .opt_clks       = bandgap_opt_clks,
        .opt_clks_cnt   = ARRAY_SIZE(bandgap_opt_clks),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -917,7 +905,6 @@ static struct omap_hwmod omap44xx_counter_32k_hwmod = {
        },
        .slaves         = omap44xx_counter_32k_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_counter_32k_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -1005,7 +992,6 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
        .masters        = omap44xx_dma_system_masters,
        .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -1098,7 +1084,6 @@ static struct omap_hwmod omap44xx_dmic_hwmod = {
        },
        .slaves         = omap44xx_dmic_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_dmic_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -1164,7 +1149,6 @@ static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
                        .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
                },
        },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct omap_hwmod omap44xx_dsp_hwmod = {
@@ -1187,7 +1171,6 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap44xx_dsp_slaves),
        .masters        = omap44xx_dsp_masters,
        .masters_cnt    = ARRAY_SIZE(omap44xx_dsp_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -1278,7 +1261,6 @@ static struct omap_hwmod omap44xx_dss_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_slaves),
        .masters        = omap44xx_dss_masters,
        .masters_cnt    = ARRAY_SIZE(omap44xx_dss_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -1381,7 +1363,6 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
        .opt_clks_cnt   = ARRAY_SIZE(dss_dispc_opt_clks),
        .slaves         = omap44xx_dss_dispc_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -1480,7 +1461,6 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
        .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
        .slaves         = omap44xx_dss_dsi1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* dss_dsi2 */
@@ -1558,7 +1538,6 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
        .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
        .slaves         = omap44xx_dss_dsi2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -1656,7 +1635,6 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
        .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
        .slaves         = omap44xx_dss_hdmi_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -1748,7 +1726,6 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
        .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
        .slaves         = omap44xx_dss_rfbi_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -1817,7 +1794,6 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
        },
        .slaves         = omap44xx_dss_venc_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_venc_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -1901,7 +1877,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
        .dev_attr       = &gpio_dev_attr,
        .slaves         = omap44xx_gpio1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* gpio2 */
@@ -1957,7 +1932,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
        .dev_attr       = &gpio_dev_attr,
        .slaves         = omap44xx_gpio2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* gpio3 */
@@ -2013,7 +1987,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
        .dev_attr       = &gpio_dev_attr,
        .slaves         = omap44xx_gpio3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* gpio4 */
@@ -2069,7 +2042,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
        .dev_attr       = &gpio_dev_attr,
        .slaves         = omap44xx_gpio4_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* gpio5 */
@@ -2125,7 +2097,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
        .dev_attr       = &gpio_dev_attr,
        .slaves         = omap44xx_gpio5_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* gpio6 */
@@ -2181,7 +2152,6 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
        .dev_attr       = &gpio_dev_attr,
        .slaves         = omap44xx_gpio6_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -2261,7 +2231,6 @@ static struct omap_hwmod omap44xx_hsi_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap44xx_hsi_slaves),
        .masters        = omap44xx_hsi_masters,
        .masters_cnt    = ARRAY_SIZE(omap44xx_hsi_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -2345,7 +2314,6 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
        .slaves         = omap44xx_i2c1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
        .dev_attr       = &i2c_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* i2c2 */
@@ -2402,7 +2370,6 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
        .slaves         = omap44xx_i2c2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
        .dev_attr       = &i2c_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* i2c3 */
@@ -2459,7 +2426,6 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
        .slaves         = omap44xx_i2c3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
        .dev_attr       = &i2c_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* i2c4 */
@@ -2516,7 +2482,6 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
        .slaves         = omap44xx_i2c4_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
        .dev_attr       = &i2c_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -2577,7 +2542,6 @@ static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
                        .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
                },
        },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* Pseudo hwmod for reset control purpose only */
@@ -2593,7 +2557,6 @@ static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
                        .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
                },
        },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct omap_hwmod omap44xx_ipu_hwmod = {
@@ -2616,7 +2579,6 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap44xx_ipu_slaves),
        .masters        = omap44xx_ipu_masters,
        .masters_cnt    = ARRAY_SIZE(omap44xx_ipu_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -2706,7 +2668,6 @@ static struct omap_hwmod omap44xx_iss_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap44xx_iss_slaves),
        .masters        = omap44xx_iss_masters,
        .masters_cnt    = ARRAY_SIZE(omap44xx_iss_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -2781,7 +2742,6 @@ static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
                        .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
                },
        },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* Pseudo hwmod for reset control purpose only */
@@ -2797,7 +2757,6 @@ static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
                        .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
                },
        },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct omap_hwmod omap44xx_iva_hwmod = {
@@ -2820,7 +2779,6 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap44xx_iva_slaves),
        .masters        = omap44xx_iva_masters,
        .masters_cnt    = ARRAY_SIZE(omap44xx_iva_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -2890,7 +2848,6 @@ static struct omap_hwmod omap44xx_kbd_hwmod = {
        },
        .slaves         = omap44xx_kbd_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_kbd_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -2956,7 +2913,6 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = {
        },
        .slaves         = omap44xx_mailbox_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_mailbox_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -3051,7 +3007,6 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
        },
        .slaves         = omap44xx_mcbsp1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* mcbsp2 */
@@ -3127,7 +3082,6 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
        },
        .slaves         = omap44xx_mcbsp2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* mcbsp3 */
@@ -3203,7 +3157,6 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
        },
        .slaves         = omap44xx_mcbsp3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* mcbsp4 */
@@ -3258,7 +3211,6 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
        },
        .slaves         = omap44xx_mcbsp4_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -3353,7 +3305,6 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
        },
        .slaves         = omap44xx_mcpdm_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcpdm_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -3442,7 +3393,6 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
        .dev_attr       = &mcspi1_dev_attr,
        .slaves         = omap44xx_mcspi1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* mcspi2 */
@@ -3505,7 +3455,6 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
        .dev_attr       = &mcspi2_dev_attr,
        .slaves         = omap44xx_mcspi2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* mcspi3 */
@@ -3568,7 +3517,6 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
        .dev_attr       = &mcspi3_dev_attr,
        .slaves         = omap44xx_mcspi3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi3_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* mcspi4 */
@@ -3629,7 +3577,6 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
        .dev_attr       = &mcspi4_dev_attr,
        .slaves         = omap44xx_mcspi4_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi4_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -3718,7 +3665,6 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc1_slaves),
        .masters        = omap44xx_mmc1_masters,
        .masters_cnt    = ARRAY_SIZE(omap44xx_mmc1_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* mmc2 */
@@ -3779,7 +3725,6 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc2_slaves),
        .masters        = omap44xx_mmc2_masters,
        .masters_cnt    = ARRAY_SIZE(omap44xx_mmc2_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* mmc3 */
@@ -3834,7 +3779,6 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
        },
        .slaves         = omap44xx_mmc3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc3_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* mmc4 */
@@ -3890,7 +3834,6 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
        },
        .slaves         = omap44xx_mmc4_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc4_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* mmc5 */
@@ -3945,7 +3888,6 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = {
        },
        .slaves         = omap44xx_mmc5_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc5_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -3987,7 +3929,6 @@ static struct omap_hwmod omap44xx_mpu_hwmod = {
        },
        .masters        = omap44xx_mpu_masters,
        .masters_cnt    = ARRAY_SIZE(omap44xx_mpu_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -4063,7 +4004,6 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
        },
        .slaves         = omap44xx_smartreflex_core_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* smartreflex_iva */
@@ -4112,7 +4052,6 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
        },
        .slaves         = omap44xx_smartreflex_iva_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* smartreflex_mpu */
@@ -4161,7 +4100,6 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
        },
        .slaves         = omap44xx_smartreflex_mpu_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -4224,7 +4162,6 @@ static struct omap_hwmod omap44xx_spinlock_hwmod = {
        },
        .slaves         = omap44xx_spinlock_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_spinlock_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -4265,6 +4202,16 @@ static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
        .sysc   = &omap44xx_timer_sysc,
 };
+/* always-on timers dev attribute */
+static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
+        .timer_capability       = OMAP_TIMER_ALWON,
+};
+/* pwm timers dev attribute */
+static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
+        .timer_capability       = OMAP_TIMER_HAS_PWM,
+};
 /* timer1 */
 static struct omap_hwmod omap44xx_timer1_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
@@ -4308,9 +4255,9 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap44xx_timer1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* timer2 */
@@ -4356,9 +4303,9 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap44xx_timer2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* timer3 */
@@ -4404,9 +4351,9 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap44xx_timer3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer3_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* timer4 */
@@ -4452,9 +4399,9 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap44xx_timer4_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer4_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* timer5 */
@@ -4519,9 +4466,9 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap44xx_timer5_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer5_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* timer6 */
@@ -4587,9 +4534,9 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap44xx_timer6_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer6_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* timer7 */
@@ -4654,9 +4601,9 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap44xx_timer7_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer7_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* timer8 */
@@ -4721,9 +4668,9 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
+        .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap44xx_timer8_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer8_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* timer9 */
@@ -4769,9 +4716,9 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
+        .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap44xx_timer9_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer9_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* timer10 */
@@ -4817,9 +4764,9 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
+        .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap44xx_timer10_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer10_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* timer11 */
@@ -4865,9 +4812,9 @@ static struct omap_hwmod omap44xx_timer11_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
+        .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap44xx_timer11_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer11_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -4944,7 +4891,6 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
        },
        .slaves         = omap44xx_uart1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_uart1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* uart2 */
@@ -4999,7 +4945,6 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
        },
        .slaves         = omap44xx_uart2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_uart2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* uart3 */
@@ -5055,7 +5000,6 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
        },
        .slaves         = omap44xx_uart3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_uart3_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* uart4 */
@@ -5110,7 +5054,6 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
        },
        .slaves         = omap44xx_uart4_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_uart4_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -5195,7 +5138,6 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
        .masters        = omap44xx_usb_otg_hs_masters,
        .masters_cnt    = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -5266,7 +5208,6 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
        },
        .slaves         = omap44xx_wd_timer2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* wd_timer3 */
@@ -5333,7 +5274,6 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
        },
        .slaves         = omap44xx_wd_timer3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
diff --git a/arch/arm/mach-omap2/omap_l3_noc.c b/arch/arm/mach-omap2/omap_l3_noc.c
index 7b9f1909ddb2..c8b1bef92e5a 100644
--- a/arch/arm/mach-omap2/omap_l3_noc.c
+++ b/arch/arm/mach-omap2/omap_l3_noc.c
@@ -1,25 +1,25 @@
 /*
-  * OMAP4XXX L3 Interconnect error handling driver
+ * OMAP4XXX L3 Interconnect error handling driver
-  *
+ *
-  * Copyright (C) 2011 Texas Corporation
+ * Copyright (C) 2011 Texas Corporation
-  *     Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
-  *     Sricharan <r.sricharan@ti.com>
+ *      Sricharan <r.sricharan@ti.com>
-  *
+ *
-  * This program is free software; you can redistribute it and/or modify
+ * This program is free software; you can redistribute it and/or modify
-  * it under the terms of the GNU General Public License as published by
+ * it under the terms of the GNU General Public License as published by
-  * the Free Software Foundation; either version 2 of the License, or
+ * the Free Software Foundation; either version 2 of the License, or
-  * (at your option) any later version.
+ * (at your option) any later version.
-  *
+ *
-  * This program is distributed in the hope that it will be useful,
+ * This program is distributed in the hope that it will be useful,
-  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-  * GNU General Public License for more details.
+ * GNU General Public License for more details.
-  *
+ *
-  * You should have received a copy of the GNU General Public License
+ * You should have received a copy of the GNU General Public License
-  * along with this program; if not, write to the Free Software
+ * along with this program; if not, write to the Free Software
-  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
-  * USA
+ * USA
-  */
+ */
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
@@ -55,12 +55,12 @@
 static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
 {
-        struct omap4_l3         *l3 = _l3;
+        struct omap4_l3 *l3 = _l3;
-        int inttype, i, j;
+        int inttype, i, k;
        int err_src = 0;
-        u32 std_err_main_addr, std_err_main, err_reg;
+        u32 std_err_main, err_reg, clear, masterid;
-        u32 base, slave_addr, clear;
+        void __iomem *base, *l3_targ_base;
-        char *source_name;
+        char *target_name, *master_name = "UN IDENTIFIED";
        /* Get the Type of interrupt */
        inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
@@ -70,43 +70,50 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
                 * Read the regerr register of the clock domain
                 * to determine the source
                 */
-                base = (u32)l3->l3_base[i];
+                base = l3->l3_base[i];
-                err_reg =  readl(base + l3_flagmux[i] + (inttype << 3));
+                err_reg = __raw_readl(base + l3_flagmux[i] +
+                                        + L3_FLAGMUX_REGERR0 + (inttype << 3));
                /* Get the corresponding error and analyse */
                if (err_reg) {
                        /* Identify the source from control status register */
-                        for (j = 0; !(err_reg & (1 << j)); j++)
+                        err_src = __ffs(err_reg);
-                                                                        ;
-                        err_src = j;
                        /* Read the stderrlog_main_source from clk domain */
-                        std_err_main_addr = base + *(l3_targ[i] + err_src);
+                        l3_targ_base = base + *(l3_targ[i] + err_src);
-                        std_err_main = readl(std_err_main_addr);
+                        std_err_main =  __raw_readl(l3_targ_base +
+                                        L3_TARG_STDERRLOG_MAIN);
+                        masterid = __raw_readl(l3_targ_base +
+                                        L3_TARG_STDERRLOG_MSTADDR);
                        switch (std_err_main & CUSTOM_ERROR) {
                        case STANDARD_ERROR:
-                                source_name =
+                                target_name =
-                                l3_targ_stderrlog_main_name[i][err_src];
+                                        l3_targ_inst_name[i][err_src];
+                                WARN(true, "L3 standard error: TARGET:%s at address 0x%x\n",
-                                slave_addr = std_err_main_addr +
+                                        target_name,
-                                                L3_SLAVE_ADDRESS_OFFSET;
+                                        __raw_readl(l3_targ_base +
-                                WARN(true, "L3 standard error: SOURCE:%s at address 0x%x\n",
+                                                L3_TARG_STDERRLOG_SLVOFSLSB));
-                                        source_name, readl(slave_addr));
                                /* clear the std error log*/
                                clear = std_err_main | CLEAR_STDERR_LOG;
-                                writel(clear, std_err_main_addr);
+                                writel(clear, l3_targ_base +
+                                        L3_TARG_STDERRLOG_MAIN);
                                break;
                        case CUSTOM_ERROR:
-                                source_name =
+                                target_name =
-                                l3_targ_stderrlog_main_name[i][err_src];
+                                        l3_targ_inst_name[i][err_src];
+                                for (k = 0; k < NUM_OF_L3_MASTERS; k++) {
-                                WARN(true, "CUSTOM SRESP error with SOURCE:%s\n",
+                                        if (masterid == l3_masters[k].id)
-                                                        source_name);
+                                                master_name =
+                                                        l3_masters[k].name;
+                                }
+                                WARN(true, "L3 custom error: MASTER:%s TARGET:%s\n",
+                                        master_name, target_name);
                                /* clear the std error log*/
                                clear = std_err_main | CLEAR_STDERR_LOG;
-                                writel(clear, std_err_main_addr);
+                                writel(clear, l3_targ_base +
+                                        L3_TARG_STDERRLOG_MAIN);
                                break;
                        default:
@@ -120,12 +127,11 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
        return IRQ_HANDLED;
 }
-static int __init omap4_l3_probe(struct platform_device *pdev)
+static int __devinit omap4_l3_probe(struct platform_device *pdev)
 {
-        static struct omap4_l3          *l3;
+        static struct omap4_l3 *l3;
-        struct resource         *res;
+        struct resource *res;
-        int                     ret;
+        int ret;
-        int                     irq;
        l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
        if (!l3)
@@ -177,27 +183,25 @@ static int __init omap4_l3_probe(struct platform_device *pdev)
        /*
         * Setup interrupt Handlers
         */
-        irq = platform_get_irq(pdev, 0);
+        l3->debug_irq = platform_get_irq(pdev, 0);
-        ret = request_irq(irq,
+        ret = request_irq(l3->debug_irq,
                        l3_interrupt_handler,
                        IRQF_DISABLED, "l3-dbg-irq", l3);
        if (ret) {
                pr_crit("L3: request_irq failed to register for 0x%x\n",
-                                         OMAP44XX_IRQ_L3_DBG);
+                                                OMAP44XX_IRQ_L3_DBG);
                goto err3;
        }
-        l3->debug_irq = irq;
-        irq = platform_get_irq(pdev, 1);
+        l3->app_irq = platform_get_irq(pdev, 1);
-        ret = request_irq(irq,
+        ret = request_irq(l3->app_irq,
                        l3_interrupt_handler,
                        IRQF_DISABLED, "l3-app-irq", l3);
        if (ret) {
                pr_crit("L3: request_irq failed to register for 0x%x\n",
-                                         OMAP44XX_IRQ_L3_APP);
+                                                OMAP44XX_IRQ_L3_APP);
                goto err4;
        }
-        l3->app_irq = irq;
        return 0;
@@ -214,9 +218,9 @@ err0:
        return ret;
 }
-static int __exit omap4_l3_remove(struct platform_device *pdev)
+static int __devexit omap4_l3_remove(struct platform_device *pdev)
 {
-        struct omap4_l3         *l3 = platform_get_drvdata(pdev);
+        struct omap4_l3 *l3 = platform_get_drvdata(pdev);
        free_irq(l3->app_irq, l3);
        free_irq(l3->debug_irq, l3);
@@ -228,16 +232,29 @@ static int __exit omap4_l3_remove(struct platform_device *pdev)
        return 0;
 }
+#if defined(CONFIG_OF)
+static const struct of_device_id l3_noc_match[] = {
+        {.compatible = "ti,omap4-l3-noc", },
+        {},
+}
+MODULE_DEVICE_TABLE(of, l3_noc_match);
+#else
+#define l3_noc_match NULL
+#endif
 static struct platform_driver omap4_l3_driver = {
-        .remove         = __exit_p(omap4_l3_remove),
+        .probe          = omap4_l3_probe,
+        .remove         = __devexit_p(omap4_l3_remove),
        .driver         = {
-        .name           = "omap_l3_noc",
+                .name           = "omap_l3_noc",
+                .owner          = THIS_MODULE,
+                .of_match_table = l3_noc_match,
        },
 };
 static int __init omap4_l3_init(void)
 {
-        return platform_driver_probe(&omap4_l3_driver, omap4_l3_probe);
+        return platform_driver_register(&omap4_l3_driver);
 }
 postcore_initcall_sync(omap4_l3_init);
diff --git a/arch/arm/mach-omap2/omap_l3_noc.h b/arch/arm/mach-omap2/omap_l3_noc.h
index 359b83348aed..90b50984cd2e 100644
--- a/arch/arm/mach-omap2/omap_l3_noc.h
+++ b/arch/arm/mach-omap2/omap_l3_noc.h
@@ -1,132 +1,162 @@
- /*
+/*
-  * OMAP4XXX L3 Interconnect  error handling driver header
+ * OMAP4XXX L3 Interconnect  error handling driver header
-  *
+ *
-  * Copyright (C) 2011 Texas Corporation
+ * Copyright (C) 2011 Texas Corporation
-  *     Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
-  *     sricharan <r.sricharan@ti.com>
+ *      sricharan <r.sricharan@ti.com>
-  *
+ *
-  * This program is free software; you can redistribute it and/or modify
+ * This program is free software; you can redistribute it and/or modify
-  * it under the terms of the GNU General Public License as published by
+ * it under the terms of the GNU General Public License as published by
-  * the Free Software Foundation; either version 2 of the License, or
+ * the Free Software Foundation; either version 2 of the License, or
-  * (at your option) any later version.
+ * (at your option) any later version.
-  *
+ *
-  * This program is distributed in the hope that it will be useful,
+ * This program is distributed in the hope that it will be useful,
-  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-  * GNU General Public License for more details.
+ * GNU General Public License for more details.
-  *
+ *
-  * You should have received a copy of the GNU General Public License
+ * You should have received a copy of the GNU General Public License
-  * along with this program; if not, write to the Free Software
+ * along with this program; if not, write to the Free Software
-  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
-  * USA
+ * USA
-  */
+ */
 #ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
 #define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
-/*
- * L3 register offsets
- */
 #define L3_MODULES                      3
 #define CLEAR_STDERR_LOG                (1 << 31)
 #define CUSTOM_ERROR                    0x2
 #define STANDARD_ERROR                  0x0
 #define INBAND_ERROR                    0x0
-#define EMIF_KERRLOG_OFFSET             0x10
-#define L3_SLAVE_ADDRESS_OFFSET         0x14
-#define LOGICAL_ADDR_ERRORLOG           0x4
 #define L3_APPLICATION_ERROR            0x0
 #define L3_DEBUG_ERROR                  0x1
-u32 l3_flagmux[L3_MODULES] = {
+/* L3 TARG register offsets */
-        0x50C,
+#define L3_TARG_STDERRLOG_MAIN          0x48
-        0x100C,
+#define L3_TARG_STDERRLOG_SLVOFSLSB     0x5c
-        0X020C
+#define L3_TARG_STDERRLOG_MSTADDR       0x68
+#define L3_FLAGMUX_REGERR0              0xc
+#define NUM_OF_L3_MASTERS       (sizeof(l3_masters)/sizeof(l3_masters[0]))
+static u32 l3_flagmux[L3_MODULES] = {
+        0x500,
+        0x1000,
+        0X0200
 };
-/*
+/* L3 Target standard Error register offsets */
- * L3 Target standard Error register offsets
+static u32 l3_targ_inst_clk1[] = {
- */
+        0x100, /* DMM1 */
-u32 l3_targ_stderrlog_main_clk1[] = {
+        0x200, /* DMM2 */
-        0x148, /* DMM1 */
+        0x300, /* ABE */
-        0x248, /* DMM2 */
+        0x400, /* L4CFG */
-        0x348, /* ABE */
+        0x600  /* CLK2 PWR DISC */
-        0x448, /* L4CFG */
-        0x648  /* CLK2 PWR DISC */
 };
-u32 l3_targ_stderrlog_main_clk2[] = {
+static u32 l3_targ_inst_clk2[] = {
-        0x548,          /* CORTEX M3 */
+        0x500, /* CORTEX M3 */
-        0x348,          /* DSS */
+        0x300, /* DSS */
-        0x148,          /* GPMC */
+        0x100, /* GPMC */
-        0x448,          /* ISS */
+        0x400, /* ISS */
-        0x748,          /* IVAHD */
+        0x700, /* IVAHD */
-        0xD48,          /* missing in TRM  corresponds to AES1*/
+        0xD00, /* missing in TRM  corresponds to AES1*/
-        0x948,          /* L4 PER0*/
+        0x900, /* L4 PER0*/
-        0x248,          /* OCMRAM */
+        0x200, /* OCMRAM */
-        0x148,          /* missing in TRM corresponds to GPMC sERROR*/
+        0x100, /* missing in TRM corresponds to GPMC sERROR*/
-        0x648,          /* SGX */
+        0x600, /* SGX */
-        0x848,          /* SL2 */
+        0x800, /* SL2 */
-        0x1648,         /* C2C */
+        0x1600, /* C2C */
-        0x1148,         /* missing in TRM corresponds PWR DISC CLK1*/
+        0x1100, /* missing in TRM corresponds PWR DISC CLK1*/
-        0xF48,          /* missing in TRM corrsponds to SHA1*/
+        0xF00, /* missing in TRM corrsponds to SHA1*/
-        0xE48,          /* missing in TRM corresponds to AES2*/
+        0xE00, /* missing in TRM corresponds to AES2*/
-        0xC48,          /* L4 PER3 */
+        0xC00, /* L4 PER3 */
-        0xA48,          /* L4 PER1*/
+        0xA00, /* L4 PER1*/
-        0xB48           /* L4 PER2*/
+        0xB00 /* L4 PER2*/
 };
-u32 l3_targ_stderrlog_main_clk3[] = {
+static u32 l3_targ_inst_clk3[] = {
-        0x0148  /* EMUSS */
+        0x0100  /* EMUSS */
 };
-char *l3_targ_stderrlog_main_name[L3_MODULES][18] = {
+static struct l3_masters_data {
+        u32 id;
+        char name[10];
+} l3_masters[] = {
+        { 0x0 , "MPU"},
+        { 0x10, "CS_ADP"},
+        { 0x14, "xxx"},
+        { 0x20, "DSP"},
+        { 0x30, "IVAHD"},
+        { 0x40, "ISS"},
+        { 0x44, "DucatiM3"},
+        { 0x48, "FaceDetect"},
+        { 0x50, "SDMA_Rd"},
+        { 0x54, "SDMA_Wr"},
+        { 0x58, "xxx"},
+        { 0x5C, "xxx"},
+        { 0x60, "SGX"},
+        { 0x70, "DSS"},
+        { 0x80, "C2C"},
+        { 0x88, "xxx"},
+        { 0x8C, "xxx"},
+        { 0x90, "HSI"},
+        { 0xA0, "MMC1"},
+        { 0xA4, "MMC2"},
+        { 0xA8, "MMC6"},
+        { 0xB0, "UNIPRO1"},
+        { 0xC0, "USBHOSTHS"},
+        { 0xC4, "USBOTGHS"},
+        { 0xC8, "USBHOSTFS"}
+};
+static char *l3_targ_inst_name[L3_MODULES][18] = {
        {
-        "DMM1",
+                "DMM1",
-        "DMM2",
+                "DMM2",
-        "ABE",
+                "ABE",
-        "L4CFG",
+                "L4CFG",
-        "CLK2 PWR DISC",
+                "CLK2 PWR DISC",
        },
        {
-        "CORTEX M3" ,
+                "CORTEX M3" ,
-        "DSS ",
+                "DSS ",
-        "GPMC ",
+                "GPMC ",
-        "ISS ",
+                "ISS ",
-        "IVAHD ",
+                "IVAHD ",
-        "AES1",
+                "AES1",
-        "L4 PER0",
+                "L4 PER0",
-        "OCMRAM ",
+                "OCMRAM ",
-        "GPMC sERROR",
+                "GPMC sERROR",
-        "SGX ",
+                "SGX ",
-        "SL2 ",
+                "SL2 ",
-        "C2C ",
+                "C2C ",
-        "PWR DISC CLK1",
+                "PWR DISC CLK1",
-        "SHA1",
+                "SHA1",
-        "AES2",
+                "AES2",
-        "L4 PER3",
+                "L4 PER3",
-        "L4 PER1",
+                "L4 PER1",
-        "L4 PER2",
+                "L4 PER2",
        },
        {
-        "EMUSS",
+                "EMUSS",
        },
 };
-u32 *l3_targ[L3_MODULES] = {
+static u32 *l3_targ[L3_MODULES] = {
-        l3_targ_stderrlog_main_clk1,
+        l3_targ_inst_clk1,
-        l3_targ_stderrlog_main_clk2,
+        l3_targ_inst_clk2,
-        l3_targ_stderrlog_main_clk3,
+        l3_targ_inst_clk3,
 };
 struct omap4_l3 {
-        struct device   *dev;
+        struct device *dev;
-        struct clk      *ick;
+        struct clk *ick;
        /* memory base */
-        void __iomem *l3_base[4];
+        void __iomem *l3_base[L3_MODULES];
-        int             debug_irq;
+        int debug_irq;
-        int             app_irq;
+        int app_irq;
 };
 #endif
diff --git a/arch/arm/mach-omap2/omap_l3_smx.c b/arch/arm/mach-omap2/omap_l3_smx.c
index 873c0e33b512..a05a62f9ee5b 100644
--- a/arch/arm/mach-omap2/omap_l3_smx.c
+++ b/arch/arm/mach-omap2/omap_l3_smx.c
@@ -1,26 +1,26 @@
- /*
+/*
-  * OMAP3XXX L3 Interconnect Driver
+ * OMAP3XXX L3 Interconnect Driver
-  *
+ *
-  * Copyright (C) 2011 Texas Corporation
+ * Copyright (C) 2011 Texas Corporation
-  *     Felipe Balbi <balbi@ti.com>
+ *      Felipe Balbi <balbi@ti.com>
-  *     Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
-  *     Sricharan <r.sricharan@ti.com>
+ *      Sricharan <r.sricharan@ti.com>
-  *
+ *
-  * This program is free software; you can redistribute it and/or modify
+ * This program is free software; you can redistribute it and/or modify
-  * it under the terms of the GNU General Public License as published by
+ * it under the terms of the GNU General Public License as published by
-  * the Free Software Foundation; either version 2 of the License, or
+ * the Free Software Foundation; either version 2 of the License, or
-  * (at your option) any later version.
+ * (at your option) any later version.
-  *
+ *
-  * This program is distributed in the hope that it will be useful,
+ * This program is distributed in the hope that it will be useful,
-  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-  * GNU General Public License for more details.
+ * GNU General Public License for more details.
-  *
+ *
-  * You should have received a copy of the GNU General Public License
+ * You should have received a copy of the GNU General Public License
-  * along with this program; if not, write to the Free Software
+ * along with this program; if not, write to the Free Software
-  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
-  * USA
+ * USA
-  */
+ */
 #include <linux/kernel.h>
 #include <linux/slab.h>
@@ -135,7 +135,7 @@ static char *omap3_l3_initiator_string(u8 initid)
        }
 }
-/**
+/*
 * omap3_l3_block_irq - handles a register block's irq
 * @l3: struct omap3_l3 *
 * @base: register block base address
@@ -150,30 +150,29 @@ static char *omap3_l3_initiator_string(u8 initid)
 static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3,
                                        u64 error, int error_addr)
 {
-        u8                      code = omap3_l3_decode_error_code(error);
+        u8 code = omap3_l3_decode_error_code(error);
-        u8                      initid = omap3_l3_decode_initid(error);
+        u8 initid = omap3_l3_decode_initid(error);
-        u8                      multi = error & L3_ERROR_LOG_MULTI;
+        u8 multi = error & L3_ERROR_LOG_MULTI;
-        u32                     address = omap3_l3_decode_addr(error_addr);
+        u32 address = omap3_l3_decode_addr(error_addr);
        WARN(true, "%s seen by %s %s at address %x\n",
-                                 omap3_l3_code_string(code),
+                        omap3_l3_code_string(code),
-                          omap3_l3_initiator_string(initid),
+                        omap3_l3_initiator_string(initid),
-                             multi ? "Multiple Errors" : "",
+                        multi ? "Multiple Errors" : "", address);
-                                                   address);
        return IRQ_HANDLED;
 }
 static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
 {
-        struct omap3_l3         *l3 = _l3;
+        struct omap3_l3 *l3 = _l3;
-        u64                     status, clear;
+        u64 status, clear;
-        u64                     error;
+        u64 error;
-        u64                     error_addr;
+        u64 error_addr;
-        u64                     err_source = 0;
+        u64 err_source = 0;
-        void                    __iomem *base;
+        void __iomem *base;
-        int                     int_type;
+        int int_type;
-        irqreturn_t             ret = IRQ_NONE;
+        irqreturn_t ret = IRQ_NONE;
        int_type = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
        if (!int_type) {
@@ -191,14 +190,12 @@ static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
        }
        /* identify the error source */
-        for (err_source = 0; !(status & (1 << err_source)); err_source++)
+        err_source = __ffs(status);
-                                                                        ;
-        base = l3->rt + *(omap3_l3_bases[int_type] + err_source);
+        base = l3->rt + omap3_l3_bases[int_type][err_source];
        error = omap3_l3_readll(base, L3_ERROR_LOG);
        if (error) {
                error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR);
                ret |= omap3_l3_block_irq(l3, error, error_addr);
        }
@@ -215,9 +212,9 @@ static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
 static int __init omap3_l3_probe(struct platform_device *pdev)
 {
-        struct omap3_l3         *l3;
+        struct omap3_l3 *l3;
-        struct resource         *res;
+        struct resource *res;
-        int                     ret;
+        int ret;
        l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
        if (!l3)
diff --git a/arch/arm/mach-omap2/omap_l3_smx.h b/arch/arm/mach-omap2/omap_l3_smx.h
index ba2ed9a850cc..4f3cebca4179 100644
--- a/arch/arm/mach-omap2/omap_l3_smx.h
+++ b/arch/arm/mach-omap2/omap_l3_smx.h
@@ -1,26 +1,26 @@
- /*
+/*
-  * OMAP3XXX L3 Interconnect Driver header
+ * OMAP3XXX L3 Interconnect Driver header
-  *
+ *
-  * Copyright (C) 2011 Texas Corporation
+ * Copyright (C) 2011 Texas Corporation
-  *     Felipe Balbi <balbi@ti.com>
+ *      Felipe Balbi <balbi@ti.com>
-  *     Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
-  *     sricharan <r.sricharan@ti.com>
+ *      sricharan <r.sricharan@ti.com>
-  *
+ *
-  * This program is free software; you can redistribute it and/or modify
+ * This program is free software; you can redistribute it and/or modify
-  * it under the terms of the GNU General Public License as published by
+ * it under the terms of the GNU General Public License as published by
-  * the Free Software Foundation; either version 2 of the License, or
+ * the Free Software Foundation; either version 2 of the License, or
-  * (at your option) any later version.
+ * (at your option) any later version.
-  *
+ *
-  * This program is distributed in the hope that it will be useful,
+ * This program is distributed in the hope that it will be useful,
-  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-  * GNU General Public License for more details.
+ * GNU General Public License for more details.
-  *
+ *
-  * You should have received a copy of the GNU General Public License
+ * You should have received a copy of the GNU General Public License
-  * along with this program; if not, write to the Free Software
+ * along with this program; if not, write to the Free Software
-  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
-  * USA
+ * USA
-  */
+ */
 #ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
 #define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
@@ -40,7 +40,7 @@
 #define L3_SI_CONTROL                   0x020
 #define L3_SI_FLAG_STATUS_0             0x510
-const u64 shift = 1;
+static const u64 shift = 1;
 #define L3_STATUS_0_MPUIA_BRST          (shift << 0)
 #define L3_STATUS_0_MPUIA_RSP           (shift << 1)
@@ -78,32 +78,32 @@ const u64 shift = 1;
 #define L3_STATUS_0_L4EMUTA_REQ         (shift << 60)
 #define L3_STATUS_0_MAD2DTA_REQ         (shift << 61)
-#define L3_STATUS_0_TIMEOUT_MASK        (L3_STATUS_0_MPUIA_BRST         \
+#define L3_STATUS_0_TIMEOUT_MASK        (L3_STATUS_0_MPUIA_BRST         \
-                                        | L3_STATUS_0_MPUIA_RSP         \
+                                        | L3_STATUS_0_MPUIA_RSP         \
-                                        | L3_STATUS_0_IVAIA_BRST        \
+                                        | L3_STATUS_0_IVAIA_BRST        \
-                                        | L3_STATUS_0_IVAIA_RSP         \
+                                        | L3_STATUS_0_IVAIA_RSP         \
-                                        | L3_STATUS_0_SGXIA_BRST        \
+                                        | L3_STATUS_0_SGXIA_BRST        \
-                                        | L3_STATUS_0_SGXIA_RSP         \
+                                        | L3_STATUS_0_SGXIA_RSP         \
-                                        | L3_STATUS_0_CAMIA_BRST        \
+                                        | L3_STATUS_0_CAMIA_BRST        \
-                                        | L3_STATUS_0_CAMIA_RSP         \
+                                        | L3_STATUS_0_CAMIA_RSP         \
-                                        | L3_STATUS_0_DISPIA_BRST       \
+                                        | L3_STATUS_0_DISPIA_BRST       \
-                                        | L3_STATUS_0_DISPIA_RSP        \
+                                        | L3_STATUS_0_DISPIA_RSP        \
-                                        | L3_STATUS_0_DMARDIA_BRST      \
+                                        | L3_STATUS_0_DMARDIA_BRST      \
-                                        | L3_STATUS_0_DMARDIA_RSP       \
+                                        | L3_STATUS_0_DMARDIA_RSP       \
-                                        | L3_STATUS_0_DMAWRIA_BRST      \
+                                        | L3_STATUS_0_DMAWRIA_BRST      \
-                                        | L3_STATUS_0_DMAWRIA_RSP       \
+                                        | L3_STATUS_0_DMAWRIA_RSP       \
-                                        | L3_STATUS_0_USBOTGIA_BRST     \
+                                        | L3_STATUS_0_USBOTGIA_BRST     \
-                                        | L3_STATUS_0_USBOTGIA_RSP      \
+                                        | L3_STATUS_0_USBOTGIA_RSP      \
-                                        | L3_STATUS_0_USBHOSTIA_BRST    \
+                                        | L3_STATUS_0_USBHOSTIA_BRST    \
-                                        | L3_STATUS_0_SMSTA_REQ         \
+                                        | L3_STATUS_0_SMSTA_REQ         \
-                                        | L3_STATUS_0_GPMCTA_REQ        \
+                                        | L3_STATUS_0_GPMCTA_REQ        \
-                                        | L3_STATUS_0_OCMRAMTA_REQ      \
+                                        | L3_STATUS_0_OCMRAMTA_REQ      \
-                                        | L3_STATUS_0_OCMROMTA_REQ      \
+                                        | L3_STATUS_0_OCMROMTA_REQ      \
-                                        | L3_STATUS_0_IVATA_REQ         \
+                                        | L3_STATUS_0_IVATA_REQ         \
-                                        | L3_STATUS_0_SGXTA_REQ         \
+                                        | L3_STATUS_0_SGXTA_REQ         \
-                                        | L3_STATUS_0_L4CORETA_REQ      \
+                                        | L3_STATUS_0_L4CORETA_REQ      \
-                                        | L3_STATUS_0_L4PERTA_REQ       \
+                                        | L3_STATUS_0_L4PERTA_REQ       \
-                                        | L3_STATUS_0_L4EMUTA_REQ       \
+                                        | L3_STATUS_0_L4EMUTA_REQ       \
                                        | L3_STATUS_0_MAD2DTA_REQ)
 #define L3_SI_FLAG_STATUS_1             0x530
@@ -137,19 +137,19 @@ const u64 shift = 1;
 enum omap3_l3_initiator_id {
        /* LCD has 1 ID */
-        OMAP_L3_LCD             = 29,
+        OMAP_L3_LCD = 29,
        /* SAD2D has 1 ID */
-        OMAP_L3_SAD2D           = 28,
+        OMAP_L3_SAD2D = 28,
        /* MPU has 5 IDs */
-        OMAP_L3_IA_MPU_SS_1     = 27,
+        OMAP_L3_IA_MPU_SS_1 = 27,
-        OMAP_L3_IA_MPU_SS_2     = 26,
+        OMAP_L3_IA_MPU_SS_2 = 26,
-        OMAP_L3_IA_MPU_SS_3     = 25,
+        OMAP_L3_IA_MPU_SS_3 = 25,
-        OMAP_L3_IA_MPU_SS_4     = 24,
+        OMAP_L3_IA_MPU_SS_4 = 24,
-        OMAP_L3_IA_MPU_SS_5     = 23,
+        OMAP_L3_IA_MPU_SS_5 = 23,
        /* IVA2.2 SS has 3 IDs*/
-        OMAP_L3_IA_IVA_SS_1     = 22,
+        OMAP_L3_IA_IVA_SS_1 = 22,
-        OMAP_L3_IA_IVA_SS_2     = 21,
+        OMAP_L3_IA_IVA_SS_2 = 21,
-        OMAP_L3_IA_IVA_SS_3     = 20,
+        OMAP_L3_IA_IVA_SS_3 = 20,
        /* IVA 2.2 SS DMA has 6 IDS */
        OMAP_L3_IA_IVA_SS_DMA_1 = 19,
        OMAP_L3_IA_IVA_SS_DMA_2 = 18,
@@ -158,25 +158,25 @@ enum omap3_l3_initiator_id {
        OMAP_L3_IA_IVA_SS_DMA_5 = 15,
        OMAP_L3_IA_IVA_SS_DMA_6 = 14,
        /* SGX has 1 ID */
-        OMAP_L3_IA_SGX          = 13,
+        OMAP_L3_IA_SGX = 13,
        /* CAM has 3 ID */
-        OMAP_L3_IA_CAM_1        = 12,
+        OMAP_L3_IA_CAM_1 = 12,
-        OMAP_L3_IA_CAM_2        = 11,
+        OMAP_L3_IA_CAM_2 = 11,
-        OMAP_L3_IA_CAM_3        = 10,
+        OMAP_L3_IA_CAM_3 = 10,
        /* DAP has 1 ID */
-        OMAP_L3_IA_DAP          = 9,
+        OMAP_L3_IA_DAP = 9,
        /* SDMA WR has 2 IDs */
-        OMAP_L3_SDMA_WR_1       = 8,
+        OMAP_L3_SDMA_WR_1 = 8,
-        OMAP_L3_SDMA_WR_2       = 7,
+        OMAP_L3_SDMA_WR_2 = 7,
        /* SDMA RD has 4 IDs */
-        OMAP_L3_SDMA_RD_1       = 6,
+        OMAP_L3_SDMA_RD_1 = 6,
-        OMAP_L3_SDMA_RD_2       = 5,
+        OMAP_L3_SDMA_RD_2 = 5,
-        OMAP_L3_SDMA_RD_3       = 4,
+        OMAP_L3_SDMA_RD_3 = 4,
-        OMAP_L3_SDMA_RD_4       = 3,
+        OMAP_L3_SDMA_RD_4 = 3,
        /* HSUSB OTG has 1 ID */
-        OMAP_L3_USBOTG          = 2,
+        OMAP_L3_USBOTG = 2,
        /* HSUSB HOST has 1 ID */
-        OMAP_L3_USBHOST         = 1,
+        OMAP_L3_USBHOST = 1,
 };
 enum omap3_l3_code {
@@ -192,21 +192,21 @@ enum omap3_l3_code {
 };
 struct omap3_l3 {
-        struct device   *dev;
+        struct device *dev;
-        struct clk      *ick;
+        struct clk *ick;
        /* memory base*/
-        void __iomem    *rt;
+        void __iomem *rt;
-        int             debug_irq;
+        int debug_irq;
-        int             app_irq;
+        int app_irq;
        /* true when and inband functional error occurs */
-        unsigned        inband:1;
+        unsigned inband:1;
 };
 /* offsets for l3 agents in order with the Flag status register */
-unsigned int __iomem omap3_l3_app_bases[] = {
+static unsigned int omap3_l3_app_bases[] = {
        /* MPU IA */
        0x1400,
        0x1400,
@@ -305,7 +305,7 @@ unsigned int __iomem omap3_l3_app_bases[] = {
        0,
 };
-unsigned int __iomem omap3_l3_debug_bases[] = {
+static unsigned int omap3_l3_debug_bases[] = {
        /* MPU DATA IA */
        0x1400,
        /* RESERVED */
@@ -321,7 +321,7 @@ unsigned int __iomem omap3_l3_debug_bases[] = {
        /* REST RESERVED */
 };
-u32 *omap3_l3_bases[] = {
+static u32 *omap3_l3_bases[] = {
        omap3_l3_app_bases,
        omap3_l3_debug_bases,
 };
diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
index 07d6140baa9d..f515a1a056d5 100644
--- a/arch/arm/mach-omap2/omap_twl.c
+++ b/arch/arm/mach-omap2/omap_twl.c
@@ -42,8 +42,11 @@
 #define OMAP4_SRI2C_SLAVE_ADDR          0x12
 #define OMAP4_VDD_MPU_SR_VOLT_REG       0x55
+#define OMAP4_VDD_MPU_SR_CMD_REG        0x56
 #define OMAP4_VDD_IVA_SR_VOLT_REG       0x5B
+#define OMAP4_VDD_IVA_SR_CMD_REG        0x5C
 #define OMAP4_VDD_CORE_SR_VOLT_REG      0x61
+#define OMAP4_VDD_CORE_SR_CMD_REG       0x62
 #define OMAP4_VP_CONFIG_ERROROFFSET     0x00
 #define OMAP4_VP_VSTEPMIN_VSTEPMIN      0x01
@@ -95,6 +98,8 @@ static unsigned long twl6030_vsel_to_uv(const u8 vsel)
                is_offset_valid = true;
        }
+        if (!vsel)
+                return 0;
        /*
         * There is no specific formula for voltage to vsel
         * conversion above 1.3V. There are special hardcoded
@@ -106,9 +111,9 @@ static unsigned long twl6030_vsel_to_uv(const u8 vsel)
                return 1350000;
        if (smps_offset & 0x8)
-                return ((((vsel - 1) * 125) + 7000)) * 100;
+                return ((((vsel - 1) * 1266) + 70900)) * 10;
        else
-                return ((((vsel - 1) * 125) + 6000)) * 100;
+                return ((((vsel - 1) * 1266) + 60770)) * 10;
 }
 static u8 twl6030_uv_to_vsel(unsigned long uv)
@@ -127,6 +132,8 @@ static u8 twl6030_uv_to_vsel(unsigned long uv)
                is_offset_valid = true;
        }
+        if (!uv)
+                return 0x00;
        /*
         * There is no specific formula for voltage to vsel
         * conversion above 1.3V. There are special hardcoded
@@ -134,16 +141,21 @@ static u8 twl6030_uv_to_vsel(unsigned long uv)
         * hardcoding only for 1.35 V which is used for 1GH OPP for
         * OMAP4430.
         */
-        if (uv == 1350000)
+        if (uv > twl6030_vsel_to_uv(0x39)) {
+                if (uv == 1350000)
+                        return 0x3A;
+                pr_err("%s:OUT OF RANGE! non mapped vsel for %ld Vs max %ld\n",
+                        __func__, uv, twl6030_vsel_to_uv(0x39));
                return 0x3A;
+        }
        if (smps_offset & 0x8)
-                return DIV_ROUND_UP(uv - 700000, 12500) + 1;
+                return DIV_ROUND_UP(uv - 709000, 12660) + 1;
        else
-                return DIV_ROUND_UP(uv - 600000, 12500) + 1;
+                return DIV_ROUND_UP(uv - 607700, 12660) + 1;
 }
-static struct omap_volt_pmic_info omap3_mpu_volt_info = {
+static struct omap_voltdm_pmic omap3_mpu_pmic = {
        .slew_rate              = 4000,
        .step_size              = 12500,
        .on_volt                = 1200000,
@@ -158,12 +170,13 @@ static struct omap_volt_pmic_info omap3_mpu_volt_info = {
        .vp_vddmax              = OMAP3430_VP1_VLIMITTO_VDDMAX,
        .vp_timeout_us          = OMAP3_VP_VLIMITTO_TIMEOUT_US,
        .i2c_slave_addr         = OMAP3_SRI2C_SLAVE_ADDR,
-        .pmic_reg               = OMAP3_VDD_MPU_SR_CONTROL_REG,
+        .volt_reg_addr          = OMAP3_VDD_MPU_SR_CONTROL_REG,
+        .i2c_high_speed         = true,
        .vsel_to_uv             = twl4030_vsel_to_uv,
        .uv_to_vsel             = twl4030_uv_to_vsel,
 };
-static struct omap_volt_pmic_info omap3_core_volt_info = {
+static struct omap_voltdm_pmic omap3_core_pmic = {
        .slew_rate              = 4000,
        .step_size              = 12500,
        .on_volt                = 1200000,
@@ -178,18 +191,19 @@ static struct omap_volt_pmic_info omap3_core_volt_info = {
        .vp_vddmax              = OMAP3430_VP2_VLIMITTO_VDDMAX,
        .vp_timeout_us          = OMAP3_VP_VLIMITTO_TIMEOUT_US,
        .i2c_slave_addr         = OMAP3_SRI2C_SLAVE_ADDR,
-        .pmic_reg               = OMAP3_VDD_CORE_SR_CONTROL_REG,
+        .volt_reg_addr          = OMAP3_VDD_CORE_SR_CONTROL_REG,
+        .i2c_high_speed         = true,
        .vsel_to_uv             = twl4030_vsel_to_uv,
        .uv_to_vsel             = twl4030_uv_to_vsel,
 };
-static struct omap_volt_pmic_info omap4_mpu_volt_info = {
+static struct omap_voltdm_pmic omap4_mpu_pmic = {
        .slew_rate              = 4000,
-        .step_size              = 12500,
+        .step_size              = 12660,
-        .on_volt                = 1350000,
+        .on_volt                = 1375000,
-        .onlp_volt              = 1350000,
+        .onlp_volt              = 1375000,
-        .ret_volt               = 837500,
+        .ret_volt               = 830000,
-        .off_volt               = 600000,
+        .off_volt               = 0,
        .volt_setup_time        = 0,
        .vp_erroroffset         = OMAP4_VP_CONFIG_ERROROFFSET,
        .vp_vstepmin            = OMAP4_VP_VSTEPMIN_VSTEPMIN,
@@ -198,18 +212,20 @@ static struct omap_volt_pmic_info omap4_mpu_volt_info = {
        .vp_vddmax              = OMAP4_VP_MPU_VLIMITTO_VDDMAX,
        .vp_timeout_us          = OMAP4_VP_VLIMITTO_TIMEOUT_US,
        .i2c_slave_addr         = OMAP4_SRI2C_SLAVE_ADDR,
-        .pmic_reg               = OMAP4_VDD_MPU_SR_VOLT_REG,
+        .volt_reg_addr          = OMAP4_VDD_MPU_SR_VOLT_REG,
+        .cmd_reg_addr           = OMAP4_VDD_MPU_SR_CMD_REG,
+        .i2c_high_speed         = true,
        .vsel_to_uv             = twl6030_vsel_to_uv,
        .uv_to_vsel             = twl6030_uv_to_vsel,
 };
-static struct omap_volt_pmic_info omap4_iva_volt_info = {
+static struct omap_voltdm_pmic omap4_iva_pmic = {
        .slew_rate              = 4000,
-        .step_size              = 12500,
+        .step_size              = 12660,
-        .on_volt                = 1100000,
+        .on_volt                = 1188000,
-        .onlp_volt              = 1100000,
+        .onlp_volt              = 1188000,
-        .ret_volt               = 837500,
+        .ret_volt               = 830000,
-        .off_volt               = 600000,
+        .off_volt               = 0,
        .volt_setup_time        = 0,
        .vp_erroroffset         = OMAP4_VP_CONFIG_ERROROFFSET,
        .vp_vstepmin            = OMAP4_VP_VSTEPMIN_VSTEPMIN,
@@ -218,18 +234,20 @@ static struct omap_volt_pmic_info omap4_iva_volt_info = {
        .vp_vddmax              = OMAP4_VP_IVA_VLIMITTO_VDDMAX,
        .vp_timeout_us          = OMAP4_VP_VLIMITTO_TIMEOUT_US,
        .i2c_slave_addr         = OMAP4_SRI2C_SLAVE_ADDR,
-        .pmic_reg               = OMAP4_VDD_IVA_SR_VOLT_REG,
+        .volt_reg_addr          = OMAP4_VDD_IVA_SR_VOLT_REG,
+        .cmd_reg_addr           = OMAP4_VDD_IVA_SR_CMD_REG,
+        .i2c_high_speed         = true,
        .vsel_to_uv             = twl6030_vsel_to_uv,
        .uv_to_vsel             = twl6030_uv_to_vsel,
 };
-static struct omap_volt_pmic_info omap4_core_volt_info = {
+static struct omap_voltdm_pmic omap4_core_pmic = {
        .slew_rate              = 4000,
-        .step_size              = 12500,
+        .step_size              = 12660,
-        .on_volt                = 1100000,
+        .on_volt                = 1200000,
-        .onlp_volt              = 1100000,
+        .onlp_volt              = 1200000,
-        .ret_volt               = 837500,
+        .ret_volt               = 830000,
-        .off_volt               = 600000,
+        .off_volt               = 0,
        .volt_setup_time        = 0,
        .vp_erroroffset         = OMAP4_VP_CONFIG_ERROROFFSET,
        .vp_vstepmin            = OMAP4_VP_VSTEPMIN_VSTEPMIN,
@@ -238,7 +256,8 @@ static struct omap_volt_pmic_info omap4_core_volt_info = {
        .vp_vddmax              = OMAP4_VP_CORE_VLIMITTO_VDDMAX,
        .vp_timeout_us          = OMAP4_VP_VLIMITTO_TIMEOUT_US,
        .i2c_slave_addr         = OMAP4_SRI2C_SLAVE_ADDR,
-        .pmic_reg               = OMAP4_VDD_CORE_SR_VOLT_REG,
+        .volt_reg_addr          = OMAP4_VDD_CORE_SR_VOLT_REG,
+        .cmd_reg_addr           = OMAP4_VDD_CORE_SR_CMD_REG,
        .vsel_to_uv             = twl6030_vsel_to_uv,
        .uv_to_vsel             = twl6030_uv_to_vsel,
 };
@@ -250,14 +269,14 @@ int __init omap4_twl_init(void)
        if (!cpu_is_omap44xx())
                return -ENODEV;
-        voltdm = omap_voltage_domain_lookup("mpu");
+        voltdm = voltdm_lookup("mpu");
-        omap_voltage_register_pmic(voltdm, &omap4_mpu_volt_info);
+        omap_voltage_register_pmic(voltdm, &omap4_mpu_pmic);
-        voltdm = omap_voltage_domain_lookup("iva");
+        voltdm = voltdm_lookup("iva");
-        omap_voltage_register_pmic(voltdm, &omap4_iva_volt_info);
+        omap_voltage_register_pmic(voltdm, &omap4_iva_pmic);
-        voltdm = omap_voltage_domain_lookup("core");
+        voltdm = voltdm_lookup("core");
-        omap_voltage_register_pmic(voltdm, &omap4_core_volt_info);
+        omap_voltage_register_pmic(voltdm, &omap4_core_pmic);
        return 0;
 }
@@ -270,10 +289,10 @@ int __init omap3_twl_init(void)
                return -ENODEV;
        if (cpu_is_omap3630()) {
-                omap3_mpu_volt_info.vp_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN;
+                omap3_mpu_pmic.vp_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN;
-                omap3_mpu_volt_info.vp_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX;
+                omap3_mpu_pmic.vp_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX;
-                omap3_core_volt_info.vp_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN;
+                omap3_core_pmic.vp_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN;
-                omap3_core_volt_info.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
+                omap3_core_pmic.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
        }
        /*
@@ -288,11 +307,11 @@ int __init omap3_twl_init(void)
        if (!twl_sr_enable_autoinit)
                omap3_twl_set_sr_bit(true);
-        voltdm = omap_voltage_domain_lookup("mpu");
+        voltdm = voltdm_lookup("mpu_iva");
-        omap_voltage_register_pmic(voltdm, &omap3_mpu_volt_info);
+        omap_voltage_register_pmic(voltdm, &omap3_mpu_pmic);
-        voltdm = omap_voltage_domain_lookup("core");
+        voltdm = voltdm_lookup("core");
-        omap_voltage_register_pmic(voltdm, &omap3_core_volt_info);
+        omap_voltage_register_pmic(voltdm, &omap3_core_pmic);
        return 0;
 }
diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c
index ab8b35b780b5..9262a6b47702 100644
--- a/arch/arm/mach-omap2/opp.c
+++ b/arch/arm/mach-omap2/opp.c
@@ -69,7 +69,7 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def,
                                opp_def->hwmod_name, i);
                        return -EINVAL;
                }
-                dev = &oh->od->pdev.dev;
+                dev = &oh->od->pdev->dev;
                r = opp_add(dev, opp_def->freq, opp_def->u_volt);
                if (r) {
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 472bf22d5e84..2ab7a9e17fe2 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -26,54 +26,21 @@
 static struct omap_device_pm_latency *pm_lats;
-static struct device *mpu_dev;
+static int _init_omap_device(char *name)
-static struct device *iva_dev;
-static struct device *l3_dev;
-static struct device *dsp_dev;
-struct device *omap2_get_mpuss_device(void)
-{
-        WARN_ON_ONCE(!mpu_dev);
-        return mpu_dev;
-}
-struct device *omap2_get_iva_device(void)
-{
-        WARN_ON_ONCE(!iva_dev);
-        return iva_dev;
-}
-struct device *omap2_get_l3_device(void)
-{
-        WARN_ON_ONCE(!l3_dev);
-        return l3_dev;
-}
-struct device *omap4_get_dsp_device(void)
-{
-        WARN_ON_ONCE(!dsp_dev);
-        return dsp_dev;
-}
-EXPORT_SYMBOL(omap4_get_dsp_device);
-/* static int _init_omap_device(struct omap_hwmod *oh, void *user) */
-static int _init_omap_device(char *name, struct device **new_dev)
 {
        struct omap_hwmod *oh;
-        struct omap_device *od;
+        struct platform_device *pdev;
        oh = omap_hwmod_lookup(name);
        if (WARN(!oh, "%s: could not find omap_hwmod for %s\n",
                 __func__, name))
                return -ENODEV;
-        od = omap_device_build(oh->name, 0, oh, NULL, 0, pm_lats, 0, false);
+        pdev = omap_device_build(oh->name, 0, oh, NULL, 0, pm_lats, 0, false);
-        if (WARN(IS_ERR(od), "%s: could not build omap_device for %s\n",
+        if (WARN(IS_ERR(pdev), "%s: could not build omap_device for %s\n",
                 __func__, name))
                return -ENODEV;
-        *new_dev = &od->pdev.dev;
        return 0;
 }
@@ -82,16 +49,16 @@ static int _init_omap_device(char *name, struct device **new_dev)
 */
 static void omap2_init_processor_devices(void)
 {
-        _init_omap_device("mpu", &mpu_dev);
+        _init_omap_device("mpu");
        if (omap3_has_iva())
-                _init_omap_device("iva", &iva_dev);
+                _init_omap_device("iva");
        if (cpu_is_omap44xx()) {
-                _init_omap_device("l3_main_1", &l3_dev);
+                _init_omap_device("l3_main_1");
-                _init_omap_device("dsp", &dsp_dev);
+                _init_omap_device("dsp");
-                _init_omap_device("iva", &iva_dev);
+                _init_omap_device("iva");
        } else {
-                _init_omap_device("l3_main", &l3_dev);
+                _init_omap_device("l3_main");
        }
 }
@@ -136,8 +103,8 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
        ret = pwrdm_set_next_pwrst(pwrdm, state);
        if (ret) {
-                printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
+                pr_err("%s: unable to set state of powerdomain: %s\n",
-                       pwrdm->name);
+                       __func__, pwrdm->name);
                goto err;
        }
@@ -161,37 +128,44 @@ err:
 }
 /*
- * This API is to be called during init to put the various voltage
+ * This API is to be called during init to set the various voltage
 * domains to the voltage as per the opp table. Typically we boot up
 * at the nominal voltage. So this function finds out the rate of
 * the clock associated with the voltage domain, finds out the correct
- * opp entry and puts the voltage domain to the voltage specifies
+ * opp entry and sets the voltage domain to the voltage specified
 * in the opp entry
 */
 static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
-                                                struct device *dev)
+                                         const char *oh_name)
 {
        struct voltagedomain *voltdm;
        struct clk *clk;
        struct opp *opp;
        unsigned long freq, bootup_volt;
+        struct device *dev;
+        if (!vdd_name || !clk_name || !oh_name) {
+                pr_err("%s: invalid parameters\n", __func__);
+                goto exit;
+        }
-        if (!vdd_name || !clk_name || !dev) {
+        dev = omap_device_get_by_hwmod_name(oh_name);
-                printk(KERN_ERR "%s: Invalid parameters!\n", __func__);
+        if (IS_ERR(dev)) {
+                pr_err("%s: Unable to get dev pointer for hwmod %s\n",
+                        __func__, oh_name);
                goto exit;
        }
-        voltdm = omap_voltage_domain_lookup(vdd_name);
+        voltdm = voltdm_lookup(vdd_name);
        if (IS_ERR(voltdm)) {
-                printk(KERN_ERR "%s: Unable to get vdd pointer for vdd_%s\n",
+                pr_err("%s: unable to get vdd pointer for vdd_%s\n",
                        __func__, vdd_name);
                goto exit;
        }
        clk =  clk_get(NULL, clk_name);
        if (IS_ERR(clk)) {
-                printk(KERN_ERR "%s: unable to get clk %s\n",
+                pr_err("%s: unable to get clk %s\n", __func__, clk_name);
-                        __func__, clk_name);
                goto exit;
        }
@@ -200,24 +174,23 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
        opp = opp_find_freq_ceil(dev, &freq);
        if (IS_ERR(opp)) {
-                printk(KERN_ERR "%s: unable to find boot up OPP for vdd_%s\n",
+                pr_err("%s: unable to find boot up OPP for vdd_%s\n",
                        __func__, vdd_name);
                goto exit;
        }
        bootup_volt = opp_get_voltage(opp);
        if (!bootup_volt) {
-                printk(KERN_ERR "%s: unable to find voltage corresponding"
+                pr_err("%s: unable to find voltage corresponding "
                        "to the bootup OPP for vdd_%s\n", __func__, vdd_name);
                goto exit;
        }
-        omap_voltage_scale_vdd(voltdm, bootup_volt);
+        voltdm_scale(voltdm, bootup_volt);
        return 0;
 exit:
-        printk(KERN_ERR "%s: Unable to put vdd_%s to its init voltage\n\n",
+        pr_err("%s: unable to set vdd_%s\n", __func__, vdd_name);
-                __func__, vdd_name);
        return -EINVAL;
 }
@@ -226,8 +199,8 @@ static void __init omap3_init_voltages(void)
        if (!cpu_is_omap34xx())
                return;
-        omap2_set_init_voltage("mpu", "dpll1_ck", mpu_dev);
+        omap2_set_init_voltage("mpu_iva", "dpll1_ck", "mpu");
-        omap2_set_init_voltage("core", "l3_ick", l3_dev);
+        omap2_set_init_voltage("core", "l3_ick", "l3_main");
 }
 static void __init omap4_init_voltages(void)
@@ -235,14 +208,15 @@ static void __init omap4_init_voltages(void)
        if (!cpu_is_omap44xx())
                return;
-        omap2_set_init_voltage("mpu", "dpll_mpu_ck", mpu_dev);
+        omap2_set_init_voltage("mpu", "dpll_mpu_ck", "mpu");
-        omap2_set_init_voltage("core", "l3_div_ck", l3_dev);
+        omap2_set_init_voltage("core", "l3_div_ck", "l3_main_1");
-        omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", iva_dev);
+        omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", "iva");
 }
 static int __init omap2_common_pm_init(void)
 {
-        omap2_init_processor_devices();
+        if (!of_have_populated_dt())
+                omap2_init_processor_devices();
        omap_pm_if_init();
        return 0;
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index bf089e743ed9..cf0c216132ab 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -53,8 +53,6 @@
 #include "powerdomain.h"
 #include "clockdomain.h"
-static int omap2_pm_debug;
 #ifdef CONFIG_SUSPEND
 static suspend_state_t suspend_state = PM_SUSPEND_ON;
 static inline bool is_suspending(void)
@@ -96,7 +94,6 @@ static int omap2_fclks_active(void)
 static void omap2_enter_full_retention(void)
 {
        u32 l;
-        struct timespec ts_preidle, ts_postidle, ts_idle;
        /* There is 1 reference hold for all children of the oscillator
         * clock, the following will remove it. If no one else uses the
@@ -124,10 +121,6 @@ static void omap2_enter_full_retention(void)
        omap2_gpio_prepare_for_idle(0);
-        if (omap2_pm_debug) {
-                getnstimeofday(&ts_preidle);
-        }
        /* One last check for pending IRQs to avoid extra latency due
         * to sleeping unnecessarily. */
        if (omap_irq_pending())
@@ -155,13 +148,6 @@ static void omap2_enter_full_retention(void)
                console_unlock();
 no_sleep:
-        if (omap2_pm_debug) {
-                unsigned long long tmp;
-                getnstimeofday(&ts_postidle);
-                ts_idle = timespec_sub(ts_postidle, ts_preidle);
-                tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
-        }
        omap2_gpio_resume_after_idle();
        clk_enable(osc_ck);
@@ -219,7 +205,6 @@ static int omap2_allow_mpu_retention(void)
 static void omap2_enter_mpu_retention(void)
 {
        int only_idle = 0;
-        struct timespec ts_preidle, ts_postidle, ts_idle;
        /* Putting MPU into the WFI state while a transfer is active
         * seems to cause the I2C block to timeout. Why? Good question. */
@@ -246,19 +231,7 @@ static void omap2_enter_mpu_retention(void)
                only_idle = 1;
        }
-        if (omap2_pm_debug) {
-                getnstimeofday(&ts_preidle);
-        }
        omap2_sram_idle();
-        if (omap2_pm_debug) {
-                unsigned long long tmp;
-                getnstimeofday(&ts_postidle);
-                ts_idle = timespec_sub(ts_postidle, ts_preidle);
-                tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
-        }
 }
 static int omap2_can_sleep(void)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 7255d9bce868..c8cbd00a41af 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -55,7 +55,7 @@
 static suspend_state_t suspend_state = PM_SUSPEND_ON;
 static inline bool is_suspending(void)
 {
-        return (suspend_state != PM_SUSPEND_ON);
+        return (suspend_state != PM_SUSPEND_ON) && console_suspend_enabled;
 }
 #else
 static inline bool is_suspending(void)
diff --git a/arch/arm/mach-omap2/powerdomain-common.c b/arch/arm/mach-omap2/powerdomain-common.c
index 171fccd208c7..f97afff68d6d 100644
--- a/arch/arm/mach-omap2/powerdomain-common.c
+++ b/arch/arm/mach-omap2/powerdomain-common.c
@@ -1,9 +1,8 @@
 /*
- *  linux/arch/arm/mach-omap2/powerdomain-common.c
+ * Common powerdomain framework functions
- *  Contains common powerdomain framework functions
 *
- *  Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2010-2011 Texas Instruments, Inc.
- *  Copyright (C) 2010 Nokia Corporation
+ * Copyright (C) 2010 Nokia Corporation
 *
 * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
 *
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index ef71fdd40fc4..5164d587ef52 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -1,7 +1,7 @@
 /*
 * OMAP powerdomain control
 *
- * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
 * Copyright (C) 2007-2011 Nokia Corporation
 *
 * Written by Paul Walmsley
@@ -77,13 +77,11 @@ static struct powerdomain *_pwrdm_lookup(const char *name)
 static int _pwrdm_register(struct powerdomain *pwrdm)
 {
        int i;
+        struct voltagedomain *voltdm;
        if (!pwrdm || !pwrdm->name)
                return -EINVAL;
-        if (!omap_chip_is(pwrdm->omap_chip))
-                return -EINVAL;
        if (cpu_is_omap44xx() &&
            pwrdm->prcm_partition == OMAP4430_INVALID_PRCM_PARTITION) {
                pr_err("powerdomain: %s: missing OMAP4 PRCM partition ID\n",
@@ -94,6 +92,16 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
        if (_pwrdm_lookup(pwrdm->name))
                return -EEXIST;
+        voltdm = voltdm_lookup(pwrdm->voltdm.name);
+        if (!voltdm) {
+                pr_err("powerdomain: %s: voltagedomain %s does not exist\n",
+                       pwrdm->name, pwrdm->voltdm.name);
+                return -EINVAL;
+        }
+        pwrdm->voltdm.ptr = voltdm;
+        INIT_LIST_HEAD(&pwrdm->voltdm_node);
+        voltdm_add_pwrdm(voltdm, pwrdm);
        list_add(&pwrdm->node, &pwrdm_list);
        /* Initialize the powerdomain's state counter */
@@ -194,36 +202,76 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused)
 /* Public functions */
 /**
- * pwrdm_init - set up the powerdomain layer
+ * pwrdm_register_platform_funcs - register powerdomain implementation fns
- * @pwrdms: array of struct powerdomain pointers to register
+ * @po: func pointers for arch specific implementations
- * @custom_funcs: func pointers for arch specific implementations
 *
- * Loop through the array of powerdomains @pwrdms, registering all
+ * Register the list of function pointers used to implement the
- * that are available on the current CPU.  Also, program all
+ * powerdomain functions on different OMAP SoCs.  Should be called
- * powerdomain target state as ON; this is to prevent domains from
+ * before any other pwrdm_register*() function.  Returns -EINVAL if
- * hitting low power states (if bootloader has target states set to
+ * @po is null, -EEXIST if platform functions have already been
- * something other than ON) and potentially even losing context while
+ * registered, or 0 upon success.
- * PM is not fully initialized.  The PM late init code can then program
- * the desired target state for all the power domains.  No return
- * value.
 */
-void pwrdm_init(struct powerdomain **pwrdms, struct pwrdm_ops *custom_funcs)
+int pwrdm_register_platform_funcs(struct pwrdm_ops *po)
+{
+        if (!po)
+                return -EINVAL;
+        if (arch_pwrdm)
+                return -EEXIST;
+        arch_pwrdm = po;
+        return 0;
+}
+/**
+ * pwrdm_register_pwrdms - register SoC powerdomains
+ * @ps: pointer to an array of struct powerdomain to register
+ *
+ * Register the powerdomains available on a particular OMAP SoC.  Must
+ * be called after pwrdm_register_platform_funcs().  May be called
+ * multiple times.  Returns -EACCES if called before
+ * pwrdm_register_platform_funcs(); -EINVAL if the argument @ps is
+ * null; or 0 upon success.
+ */
+int pwrdm_register_pwrdms(struct powerdomain **ps)
 {
        struct powerdomain **p = NULL;
-        struct powerdomain *temp_p;
-        if (!custom_funcs)
+        if (!arch_pwrdm)
-                WARN(1, "powerdomain: No custom pwrdm functions registered\n");
+                return -EEXIST;
-        else
-                arch_pwrdm = custom_funcs;
-        if (pwrdms) {
+        if (!ps)
-                for (p = pwrdms; *p; p++)
+                return -EINVAL;
-                        _pwrdm_register(*p);
-        }
+        for (p = ps; *p; p++)
+                _pwrdm_register(*p);
+        return 0;
+}
+/**
+ * pwrdm_complete_init - set up the powerdomain layer
+ *
+ * Do whatever is necessary to initialize registered powerdomains and
+ * powerdomain code.  Currently, this programs the next power state
+ * for each powerdomain to ON.  This prevents powerdomains from
+ * unexpectedly losing context or entering high wakeup latency modes
+ * with non-power-management-enabled kernels.  Must be called after
+ * pwrdm_register_pwrdms().  Returns -EACCES if called before
+ * pwrdm_register_pwrdms(), or 0 upon success.
+ */
+int pwrdm_complete_init(void)
+{
+        struct powerdomain *temp_p;
+        if (list_empty(&pwrdm_list))
+                return -EACCES;
        list_for_each_entry(temp_p, &pwrdm_list, node)
                pwrdm_set_next_pwrst(temp_p, PWRDM_POWER_ON);
+        return 0;
 }
 /**
@@ -390,6 +438,18 @@ int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
 }
 /**
+ * pwrdm_get_voltdm - return a ptr to the voltdm that this pwrdm resides in
+ * @pwrdm: struct powerdomain *
+ *
+ * Return a pointer to the struct voltageomain that the specified powerdomain
+ * @pwrdm exists in.
+ */
+struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm)
+{
+        return pwrdm->voltdm.ptr;
+}
+/**
 * pwrdm_get_mem_bank_count - get number of memory banks in this powerdomain
 * @pwrdm: struct powerdomain *
 *
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index d23d979b9c34..42e6dd8f2a78 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -24,6 +24,8 @@
 #include <plat/cpu.h>
+#include "voltage.h"
 /* Powerdomain basic power states */
 #define PWRDM_POWER_OFF         0x0
 #define PWRDM_POWER_RET         0x1
@@ -78,7 +80,7 @@ struct powerdomain;
 /**
 * struct powerdomain - OMAP powerdomain
 * @name: Powerdomain name
- * @omap_chip: represents the OMAP chip types containing this pwrdm
+ * @voltdm: voltagedomain containing this powerdomain
 * @prcm_offs: the address offset from CM_BASE/PRM_BASE
 * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs
 * @pwrsts: Possible powerdomain power states
@@ -89,6 +91,7 @@ struct powerdomain;
 * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
 * @pwrdm_clkdms: Clockdomains in this powerdomain
 * @node: list_head linking all powerdomains
+ * @voltdm_node: list_head linking all powerdomains in a voltagedomain
 * @state:
 * @state_counter:
 * @timer:
@@ -98,7 +101,10 @@ struct powerdomain;
 */
 struct powerdomain {
        const char *name;
-        const struct omap_chip_id omap_chip;
+        union {
+                const char *name;
+                struct voltagedomain *ptr;
+        } voltdm;
        const s16 prcm_offs;
        const u8 pwrsts;
        const u8 pwrsts_logic_ret;
@@ -109,6 +115,7 @@ struct powerdomain {
        const u8 prcm_partition;
        struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
        struct list_head node;
+        struct list_head voltdm_node;
        int state;
        unsigned state_counter[PWRDM_MAX_PWRSTS];
        unsigned ret_logic_off_counter;
@@ -162,7 +169,9 @@ struct pwrdm_ops {
        int     (*pwrdm_wait_transition)(struct powerdomain *pwrdm);
 };
-void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs);
+int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs);
+int pwrdm_register_pwrdms(struct powerdomain **pwrdm_list);
+int pwrdm_complete_init(void);
 struct powerdomain *pwrdm_lookup(const char *name);
@@ -176,6 +185,7 @@ int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
 int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
                         int (*fn)(struct powerdomain *pwrdm,
                                   struct clockdomain *clkdm));
+struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm);
 int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
@@ -210,7 +220,8 @@ int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
 u32 pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
 bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
-extern void omap2xxx_powerdomains_init(void);
+extern void omap242x_powerdomains_init(void);
+extern void omap243x_powerdomains_init(void);
 extern void omap3xxx_powerdomains_init(void);
 extern void omap44xx_powerdomains_init(void);
diff --git a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
index cf600e22bf8e..6a17e4ca1d79 100644
--- a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
@@ -1,7 +1,7 @@
 /*
 * OMAP2 and OMAP3 powerdomain control
 *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2011 Texas Instruments, Inc.
 * Copyright (C) 2007-2009 Nokia Corporation
 *
 * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
index 4210c3399769..d3a5399091ad 100644
--- a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
@@ -1,7 +1,7 @@
 /*
 * OMAP2/3 common powerdomain definitions
 *
- * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
 * Copyright (C) 2007-2011 Nokia Corporation
 *
 * Paul Walmsley, Jouni Högander
@@ -12,20 +12,6 @@
 */
 /*
- * To Do List
- * -> Move the Sleep/Wakeup dependencies from Power Domain framework to
- *    Clock Domain Framework
- */
-/*
- * This file contains all of the powerdomains that have some element
- * of software control for the OMAP24xx and OMAP34xx chips.
- *
- * This is not an exhaustive listing of powerdomains on the chips; only
- * powerdomains that can be controlled in software.
- */
-/*
 * The names for the DSP/IVA2 powerdomains are confusing.
 *
 * Most OMAP chips have an on-board DSP.
@@ -59,8 +45,6 @@
 struct powerdomain gfx_omap2_pwrdm = {
        .name             = "gfx_pwrdm",
        .prcm_offs        = GFX_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
-                                           CHIP_IS_OMAP3430ES1),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_RET,
        .banks            = 1,
@@ -70,11 +54,12 @@ struct powerdomain gfx_omap2_pwrdm = {
        .pwrsts_mem_on    = {
                [0] = PWRSTS_ON,  /* MEMONSTATE */
        },
+        .voltdm           = { .name = "core" },
 };
 struct powerdomain wkup_omap2_pwrdm = {
        .name           = "wkup_pwrdm",
        .prcm_offs      = WKUP_MOD,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
        .pwrsts         = PWRSTS_ON,
+        .voltdm         = { .name = "wakeup" },
 };
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_data.c
index cc389fb2005d..2385c1f009ee 100644
--- a/arch/arm/mach-omap2/powerdomains2xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains2xxx_data.c
@@ -1,7 +1,7 @@
 /*
 * OMAP2XXX powerdomain definitions
 *
- * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
 * Copyright (C) 2007-2011 Nokia Corporation
 *
 * Paul Walmsley, Jouni Högander
@@ -28,7 +28,6 @@
 static struct powerdomain dsp_pwrdm = {
        .name             = "dsp_pwrdm",
        .prcm_offs        = OMAP24XX_DSP_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_RET,
        .banks            = 1,
@@ -38,12 +37,12 @@ static struct powerdomain dsp_pwrdm = {
        .pwrsts_mem_on    = {
                [0] = PWRSTS_ON,
        },
+        .voltdm           = { .name = "core" },
 };
 static struct powerdomain mpu_24xx_pwrdm = {
        .name             = "mpu_pwrdm",
        .prcm_offs        = MPU_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF_RET,
        .banks            = 1,
@@ -53,12 +52,12 @@ static struct powerdomain mpu_24xx_pwrdm = {
        .pwrsts_mem_on    = {
                [0] = PWRSTS_ON,
        },
+        .voltdm           = { .name = "core" },
 };
 static struct powerdomain core_24xx_pwrdm = {
        .name             = "core_pwrdm",
        .prcm_offs        = CORE_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .banks            = 3,
        .pwrsts_mem_ret   = {
@@ -71,6 +70,7 @@ static struct powerdomain core_24xx_pwrdm = {
                [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
                [2] = PWRSTS_OFF_RET_ON, /* MEM3ONSTATE */
        },
+        .voltdm           = { .name = "core" },
 };
@@ -78,14 +78,11 @@ static struct powerdomain core_24xx_pwrdm = {
 * 2430-specific powerdomains
 */
-#ifdef CONFIG_SOC_OMAP2430
 /* XXX 2430 KILLDOMAINWKUP bit?  No current users apparently */
 static struct powerdomain mdm_pwrdm = {
        .name             = "mdm_pwrdm",
        .prcm_offs        = OMAP2430_MDM_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_RET,
        .banks            = 1,
@@ -95,29 +92,44 @@ static struct powerdomain mdm_pwrdm = {
        .pwrsts_mem_on    = {
                [0] = PWRSTS_ON,  /* MEMONSTATE */
        },
+        .voltdm           = { .name = "core" },
 };
-#endif     /* CONFIG_SOC_OMAP2430 */
+/*
+ *
-/* As powerdomains are added or removed above, this list must also be changed */
+ */
-static struct powerdomain *powerdomains_omap2xxx[] __initdata = {
+static struct powerdomain *powerdomains_omap24xx[] __initdata = {
        &wkup_omap2_pwrdm,
        &gfx_omap2_pwrdm,
-#ifdef CONFIG_ARCH_OMAP2
        &dsp_pwrdm,
        &mpu_24xx_pwrdm,
        &core_24xx_pwrdm,
-#endif
+        NULL
+};
-#ifdef CONFIG_SOC_OMAP2430
+static struct powerdomain *powerdomains_omap2430[] __initdata = {
        &mdm_pwrdm,
-#endif
        NULL
 };
-void __init omap2xxx_powerdomains_init(void)
+void __init omap242x_powerdomains_init(void)
+{
+        if (!cpu_is_omap2420())
+                return;
+        pwrdm_register_platform_funcs(&omap2_pwrdm_operations);
+        pwrdm_register_pwrdms(powerdomains_omap24xx);
+        pwrdm_complete_init();
+}
+void __init omap243x_powerdomains_init(void)
 {
-        pwrdm_init(powerdomains_omap2xxx, &omap2_pwrdm_operations);
+        if (!cpu_is_omap2430())
+                return;
+        pwrdm_register_platform_funcs(&omap2_pwrdm_operations);
+        pwrdm_register_pwrdms(powerdomains_omap24xx);
+        pwrdm_register_pwrdms(powerdomains_omap2430);
+        pwrdm_complete_init();
 }
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index 469a920a74dc..8ef26daeed68 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -1,7 +1,7 @@
 /*
 * OMAP3 powerdomain definitions
 *
- * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
 * Copyright (C) 2007-2011 Nokia Corporation
 *
 * Paul Walmsley, Jouni Högander
@@ -14,6 +14,8 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <plat/cpu.h>
 #include "powerdomain.h"
 #include "powerdomains2xxx_3xxx_data.h"
@@ -27,8 +29,6 @@
 * 34XX-specific powerdomains, dependencies
 */
-#ifdef CONFIG_ARCH_OMAP3
 /*
 * Powerdomains
 */
@@ -36,7 +36,6 @@
 static struct powerdomain iva2_pwrdm = {
        .name             = "iva2_pwrdm",
        .prcm_offs        = OMAP3430_IVA2_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF_RET,
        .banks            = 4,
@@ -52,12 +51,12 @@ static struct powerdomain iva2_pwrdm = {
                [2] = PWRSTS_OFF_ON,
                [3] = PWRSTS_ON,
        },
+        .voltdm           = { .name = "mpu_iva" },
 };
 static struct powerdomain mpu_3xxx_pwrdm = {
        .name             = "mpu_pwrdm",
        .prcm_offs        = MPU_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF_RET,
        .flags            = PWRDM_HAS_MPU_QUIRK,
@@ -68,6 +67,7 @@ static struct powerdomain mpu_3xxx_pwrdm = {
        .pwrsts_mem_on    = {
                [0] = PWRSTS_OFF_ON,
        },
+        .voltdm           = { .name = "mpu_iva" },
 };
 /*
@@ -83,10 +83,6 @@ static struct powerdomain mpu_3xxx_pwrdm = {
 static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
        .name             = "core_pwrdm",
        .prcm_offs        = CORE_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
-                                           CHIP_IS_OMAP3430ES2 |
-                                           CHIP_IS_OMAP3430ES3_0 |
-                                           CHIP_IS_OMAP3630ES1),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF_RET,
        .banks            = 2,
@@ -98,13 +94,12 @@ static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
                [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
                [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
        },
+        .voltdm           = { .name = "core" },
 };
 static struct powerdomain core_3xxx_es3_1_pwrdm = {
        .name             = "core_pwrdm",
        .prcm_offs        = CORE_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1 |
-                                          CHIP_GE_OMAP3630ES1_1),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF_RET,
        /*
@@ -121,11 +116,11 @@ static struct powerdomain core_3xxx_es3_1_pwrdm = {
                [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
                [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
        },
+        .voltdm           = { .name = "core" },
 };
 static struct powerdomain dss_pwrdm = {
        .name             = "dss_pwrdm",
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
        .prcm_offs        = OMAP3430_DSS_MOD,
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_RET,
@@ -136,6 +131,7 @@ static struct powerdomain dss_pwrdm = {
        .pwrsts_mem_on    = {
                [0] = PWRSTS_ON,  /* MEMONSTATE */
        },
+        .voltdm           = { .name = "core" },
 };
 /*
@@ -146,7 +142,6 @@ static struct powerdomain dss_pwrdm = {
 static struct powerdomain sgx_pwrdm = {
        .name             = "sgx_pwrdm",
        .prcm_offs        = OMAP3430ES2_SGX_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
        /* XXX This is accurate for 3430 SGX, but what about GFX? */
        .pwrsts           = PWRSTS_OFF_ON,
        .pwrsts_logic_ret = PWRSTS_RET,
@@ -157,11 +152,11 @@ static struct powerdomain sgx_pwrdm = {
        .pwrsts_mem_on    = {
                [0] = PWRSTS_ON,  /* MEMONSTATE */
        },
+        .voltdm           = { .name = "core" },
 };
 static struct powerdomain cam_pwrdm = {
        .name             = "cam_pwrdm",
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
        .prcm_offs        = OMAP3430_CAM_MOD,
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_RET,
@@ -172,12 +167,12 @@ static struct powerdomain cam_pwrdm = {
        .pwrsts_mem_on    = {
                [0] = PWRSTS_ON,  /* MEMONSTATE */
        },
+        .voltdm           = { .name = "core" },
 };
 static struct powerdomain per_pwrdm = {
        .name             = "per_pwrdm",
        .prcm_offs        = OMAP3430_PER_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF_RET,
        .banks            = 1,
@@ -187,26 +182,26 @@ static struct powerdomain per_pwrdm = {
        .pwrsts_mem_on    = {
                [0] = PWRSTS_ON,  /* MEMONSTATE */
        },
+        .voltdm           = { .name = "core" },
 };
 static struct powerdomain emu_pwrdm = {
        .name           = "emu_pwrdm",
        .prcm_offs      = OMAP3430_EMU_MOD,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+        .voltdm           = { .name = "core" },
 };
 static struct powerdomain neon_pwrdm = {
        .name             = "neon_pwrdm",
        .prcm_offs        = OMAP3430_NEON_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_RET,
+        .voltdm           = { .name = "mpu_iva" },
 };
 static struct powerdomain usbhost_pwrdm = {
        .name             = "usbhost_pwrdm",
        .prcm_offs        = OMAP3430ES2_USBHOST_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_RET,
        /*
@@ -223,65 +218,103 @@ static struct powerdomain usbhost_pwrdm = {
        .pwrsts_mem_on    = {
                [0] = PWRSTS_ON,  /* MEMONSTATE */
        },
+        .voltdm           = { .name = "core" },
 };
 static struct powerdomain dpll1_pwrdm = {
        .name           = "dpll1_pwrdm",
        .prcm_offs      = MPU_MOD,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+        .voltdm           = { .name = "mpu_iva" },
 };
 static struct powerdomain dpll2_pwrdm = {
        .name           = "dpll2_pwrdm",
        .prcm_offs      = OMAP3430_IVA2_MOD,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+        .voltdm           = { .name = "mpu_iva" },
 };
 static struct powerdomain dpll3_pwrdm = {
        .name           = "dpll3_pwrdm",
        .prcm_offs      = PLL_MOD,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+        .voltdm           = { .name = "core" },
 };
 static struct powerdomain dpll4_pwrdm = {
        .name           = "dpll4_pwrdm",
        .prcm_offs      = PLL_MOD,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+        .voltdm           = { .name = "core" },
 };
 static struct powerdomain dpll5_pwrdm = {
        .name           = "dpll5_pwrdm",
        .prcm_offs      = PLL_MOD,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
+        .voltdm           = { .name = "core" },
 };
 /* As powerdomains are added or removed above, this list must also be changed */
-static struct powerdomain *powerdomains_omap3xxx[] __initdata = {
+static struct powerdomain *powerdomains_omap3430_common[] __initdata = {
        &wkup_omap2_pwrdm,
-        &gfx_omap2_pwrdm,
        &iva2_pwrdm,
        &mpu_3xxx_pwrdm,
        &neon_pwrdm,
-        &core_3xxx_pre_es3_1_pwrdm,
-        &core_3xxx_es3_1_pwrdm,
        &cam_pwrdm,
        &dss_pwrdm,
        &per_pwrdm,
        &emu_pwrdm,
-        &sgx_pwrdm,
-        &usbhost_pwrdm,
        &dpll1_pwrdm,
        &dpll2_pwrdm,
        &dpll3_pwrdm,
        &dpll4_pwrdm,
+        NULL
+};
+static struct powerdomain *powerdomains_omap3430es1[] __initdata = {
+        &gfx_omap2_pwrdm,
+        &core_3xxx_pre_es3_1_pwrdm,
+        NULL
+};
+/* also includes 3630ES1.0 */
+static struct powerdomain *powerdomains_omap3430es2_es3_0[] __initdata = {
+        &core_3xxx_pre_es3_1_pwrdm,
+        &sgx_pwrdm,
+        &usbhost_pwrdm,
        &dpll5_pwrdm,
-#endif
        NULL
 };
+/* also includes 3630ES1.1+ */
+static struct powerdomain *powerdomains_omap3430es3_1plus[] __initdata = {
+        &core_3xxx_es3_1_pwrdm,
+        &sgx_pwrdm,
+        &usbhost_pwrdm,
+        &dpll5_pwrdm,
+        NULL
+};
 void __init omap3xxx_powerdomains_init(void)
 {
-        pwrdm_init(powerdomains_omap3xxx, &omap3_pwrdm_operations);
+        unsigned int rev;
+        if (!cpu_is_omap34xx())
+                return;
+        pwrdm_register_platform_funcs(&omap3_pwrdm_operations);
+        pwrdm_register_pwrdms(powerdomains_omap3430_common);
+        rev = omap_rev();
+        if (rev == OMAP3430_REV_ES1_0)
+                pwrdm_register_pwrdms(powerdomains_omap3430es1);
+        else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
+                 rev == OMAP3430_REV_ES3_0 || rev == OMAP3630_REV_ES1_0)
+                pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0);
+        else if (rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2 ||
+                 rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1 ||
+                 rev == OMAP3630_REV_ES1_1 || rev == OMAP3630_REV_ES1_2)
+                pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus);
+        else
+                WARN(1, "OMAP3 powerdomain init: unknown chip type\n");
+        pwrdm_complete_init();
 }
diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c
index 247e79495115..704664c0e259 100644
--- a/arch/arm/mach-omap2/powerdomains44xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains44xx_data.c
@@ -33,9 +33,9 @@
 /* core_44xx_pwrdm: CORE power domain */
 static struct powerdomain core_44xx_pwrdm = {
        .name             = "core_pwrdm",
+        .voltdm           = { .name = "core" },
        .prcm_offs        = OMAP4430_PRM_CORE_INST,
        .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF_RET,
        .banks            = 5,
@@ -59,9 +59,9 @@ static struct powerdomain core_44xx_pwrdm = {
 /* gfx_44xx_pwrdm: 3D accelerator power domain */
 static struct powerdomain gfx_44xx_pwrdm = {
        .name             = "gfx_pwrdm",
+        .voltdm           = { .name = "core" },
        .prcm_offs        = OMAP4430_PRM_GFX_INST,
        .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_OFF_ON,
        .banks            = 1,
        .pwrsts_mem_ret = {
@@ -76,9 +76,9 @@ static struct powerdomain gfx_44xx_pwrdm = {
 /* abe_44xx_pwrdm: Audio back end power domain */
 static struct powerdomain abe_44xx_pwrdm = {
        .name             = "abe_pwrdm",
+        .voltdm           = { .name = "iva" },
        .prcm_offs        = OMAP4430_PRM_ABE_INST,
        .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF,
        .banks            = 2,
@@ -96,9 +96,9 @@ static struct powerdomain abe_44xx_pwrdm = {
 /* dss_44xx_pwrdm: Display subsystem power domain */
 static struct powerdomain dss_44xx_pwrdm = {
        .name             = "dss_pwrdm",
+        .voltdm           = { .name = "core" },
        .prcm_offs        = OMAP4430_PRM_DSS_INST,
        .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF,
        .banks            = 1,
@@ -114,9 +114,9 @@ static struct powerdomain dss_44xx_pwrdm = {
 /* tesla_44xx_pwrdm: Tesla processor power domain */
 static struct powerdomain tesla_44xx_pwrdm = {
        .name             = "tesla_pwrdm",
+        .voltdm           = { .name = "iva" },
        .prcm_offs        = OMAP4430_PRM_TESLA_INST,
        .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF_RET,
        .banks            = 3,
@@ -136,9 +136,9 @@ static struct powerdomain tesla_44xx_pwrdm = {
 /* wkup_44xx_pwrdm: Wake-up power domain */
 static struct powerdomain wkup_44xx_pwrdm = {
        .name             = "wkup_pwrdm",
+        .voltdm           = { .name = "wakeup" },
        .prcm_offs        = OMAP4430_PRM_WKUP_INST,
        .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_ON,
        .banks            = 1,
        .pwrsts_mem_ret = {
@@ -152,9 +152,9 @@ static struct powerdomain wkup_44xx_pwrdm = {
 /* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
 static struct powerdomain cpu0_44xx_pwrdm = {
        .name             = "cpu0_pwrdm",
+        .voltdm           = { .name = "mpu" },
        .prcm_offs        = OMAP4430_PRCM_MPU_CPU0_INST,
        .prcm_partition   = OMAP4430_PRCM_MPU_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF_RET,
        .banks            = 1,
@@ -169,9 +169,9 @@ static struct powerdomain cpu0_44xx_pwrdm = {
 /* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
 static struct powerdomain cpu1_44xx_pwrdm = {
        .name             = "cpu1_pwrdm",
+        .voltdm           = { .name = "mpu" },
        .prcm_offs        = OMAP4430_PRCM_MPU_CPU1_INST,
        .prcm_partition   = OMAP4430_PRCM_MPU_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF_RET,
        .banks            = 1,
@@ -186,9 +186,9 @@ static struct powerdomain cpu1_44xx_pwrdm = {
 /* emu_44xx_pwrdm: Emulation power domain */
 static struct powerdomain emu_44xx_pwrdm = {
        .name             = "emu_pwrdm",
+        .voltdm           = { .name = "wakeup" },
        .prcm_offs        = OMAP4430_PRM_EMU_INST,
        .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_OFF_ON,
        .banks            = 1,
        .pwrsts_mem_ret = {
@@ -202,9 +202,9 @@ static struct powerdomain emu_44xx_pwrdm = {
 /* mpu_44xx_pwrdm: Modena processor and the Neon coprocessor power domain */
 static struct powerdomain mpu_44xx_pwrdm = {
        .name             = "mpu_pwrdm",
+        .voltdm           = { .name = "mpu" },
        .prcm_offs        = OMAP4430_PRM_MPU_INST,
        .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF_RET,
        .banks            = 3,
@@ -223,9 +223,9 @@ static struct powerdomain mpu_44xx_pwrdm = {
 /* ivahd_44xx_pwrdm: IVA-HD power domain */
 static struct powerdomain ivahd_44xx_pwrdm = {
        .name             = "ivahd_pwrdm",
+        .voltdm           = { .name = "iva" },
        .prcm_offs        = OMAP4430_PRM_IVAHD_INST,
        .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF,
        .banks            = 4,
@@ -247,9 +247,9 @@ static struct powerdomain ivahd_44xx_pwrdm = {
 /* cam_44xx_pwrdm: Camera subsystem power domain */
 static struct powerdomain cam_44xx_pwrdm = {
        .name             = "cam_pwrdm",
+        .voltdm           = { .name = "core" },
        .prcm_offs        = OMAP4430_PRM_CAM_INST,
        .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_OFF_ON,
        .banks            = 1,
        .pwrsts_mem_ret = {
@@ -264,9 +264,9 @@ static struct powerdomain cam_44xx_pwrdm = {
 /* l3init_44xx_pwrdm: L3 initators pheripherals power domain  */
 static struct powerdomain l3init_44xx_pwrdm = {
        .name             = "l3init_pwrdm",
+        .voltdm           = { .name = "core" },
        .prcm_offs        = OMAP4430_PRM_L3INIT_INST,
        .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF_RET,
        .banks            = 1,
@@ -282,9 +282,9 @@ static struct powerdomain l3init_44xx_pwrdm = {
 /* l4per_44xx_pwrdm: Target peripherals power domain */
 static struct powerdomain l4per_44xx_pwrdm = {
        .name             = "l4per_pwrdm",
+        .voltdm           = { .name = "core" },
        .prcm_offs        = OMAP4430_PRM_L4PER_INST,
        .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF_RET,
        .banks            = 2,
@@ -305,18 +305,18 @@ static struct powerdomain l4per_44xx_pwrdm = {
 */
 static struct powerdomain always_on_core_44xx_pwrdm = {
        .name             = "always_on_core_pwrdm",
+        .voltdm           = { .name = "core" },
        .prcm_offs        = OMAP4430_PRM_ALWAYS_ON_INST,
        .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_ON,
 };
 /* cefuse_44xx_pwrdm: Customer efuse controller power domain */
 static struct powerdomain cefuse_44xx_pwrdm = {
        .name             = "cefuse_pwrdm",
+        .voltdm           = { .name = "core" },
        .prcm_offs        = OMAP4430_PRM_CEFUSE_INST,
        .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_OFF_ON,
        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -352,5 +352,7 @@ static struct powerdomain *powerdomains_omap44xx[] __initdata = {
 void __init omap44xx_powerdomains_init(void)
 {
-        pwrdm_init(powerdomains_omap44xx, &omap4_pwrdm_operations);
+        pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
+        pwrdm_register_pwrdms(powerdomains_omap44xx);
+        pwrdm_complete_init();
 }
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 2e40a5cf0163..8db5f035eb0a 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -151,17 +151,10 @@ int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
 void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
 {
-        /* Static mapping, never released */
+        if (omap2_globals->prm)
-        if (omap2_globals->prm) {
+                prm_base = omap2_globals->prm;
-                prm_base = ioremap(omap2_globals->prm, SZ_8K);
+        if (omap2_globals->cm)
-                WARN_ON(!prm_base);
+                cm_base = omap2_globals->cm;
-        }
+        if (omap2_globals->cm2)
-        if (omap2_globals->cm) {
+                cm2_base = omap2_globals->cm2;
-                cm_base = ioremap(omap2_globals->cm, SZ_8K);
-                WARN_ON(!cm_base);
-        }
-        if (omap2_globals->cm2) {
-                cm2_base = ioremap(omap2_globals->cm2, SZ_8K);
-                WARN_ON(!cm2_base);
-        }
 }
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index 051213fbc346..f02d87f68e54 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -20,6 +20,8 @@
 #include <plat/cpu.h>
 #include <plat/prcm.h>
+#include "vp.h"
 #include "prm2xxx_3xxx.h"
 #include "cm2xxx_3xxx.h"
 #include "prm-regbits-24xx.h"
@@ -156,3 +158,57 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift)
        return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
 }
+/* PRM VP */
+/*
+ * struct omap3_vp - OMAP3 VP register access description.
+ * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
+ */
+struct omap3_vp {
+        u32 tranxdone_status;
+};
+static struct omap3_vp omap3_vp[] = {
+        [OMAP3_VP_VDD_MPU_ID] = {
+                .tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,
+        },
+        [OMAP3_VP_VDD_CORE_ID] = {
+                .tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,
+        },
+};
+#define MAX_VP_ID ARRAY_SIZE(omap3_vp);
+u32 omap3_prm_vp_check_txdone(u8 vp_id)
+{
+        struct omap3_vp *vp = &omap3_vp[vp_id];
+        u32 irqstatus;
+        irqstatus = omap2_prm_read_mod_reg(OCP_MOD,
+                                           OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+        return irqstatus & vp->tranxdone_status;
+}
+void omap3_prm_vp_clear_txdone(u8 vp_id)
+{
+        struct omap3_vp *vp = &omap3_vp[vp_id];
+        omap2_prm_write_mod_reg(vp->tranxdone_status,
+                                OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+}
+u32 omap3_prm_vcvp_read(u8 offset)
+{
+        return omap2_prm_read_mod_reg(OMAP3430_GR_MOD, offset);
+}
+void omap3_prm_vcvp_write(u32 val, u8 offset)
+{
+        omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset);
+}
+u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
+{
+        return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset);
+}
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
index a1fc62a39dbb..cef533df0861 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -303,7 +303,19 @@ extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
 extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
 extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift);
+/* OMAP3-specific VP functions */
+u32 omap3_prm_vp_check_txdone(u8 vp_id);
+void omap3_prm_vp_clear_txdone(u8 vp_id);
+/*
+ * OMAP3 access functions for voltage controller (VC) and
+ * voltage proccessor (VP) in the PRM.
+ */
+extern u32 omap3_prm_vcvp_read(u8 offset);
+extern void omap3_prm_vcvp_write(u32 val, u8 offset);
+extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
 #endif  /* CONFIG_ARCH_OMAP4 */
 #endif
 /*
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 00165558fc4d..495a31a7e8a7 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -21,8 +21,11 @@
 #include <plat/cpu.h>
 #include <plat/prcm.h>
+#include "vp.h"
 #include "prm44xx.h"
 #include "prm-regbits-44xx.h"
+#include "prcm44xx.h"
+#include "prminst44xx.h"
 /* PRM low-level functions */
@@ -50,3 +53,71 @@ u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
        return v;
 }
+/* PRM VP */
+/*
+ * struct omap4_vp - OMAP4 VP register access description.
+ * @irqstatus_mpu: offset to IRQSTATUS_MPU register for VP
+ * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
+ */
+struct omap4_vp {
+        u32 irqstatus_mpu;
+        u32 tranxdone_status;
+};
+static struct omap4_vp omap4_vp[] = {
+        [OMAP4_VP_VDD_MPU_ID] = {
+                .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,
+                .tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK,
+        },
+        [OMAP4_VP_VDD_IVA_ID] = {
+                .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
+                .tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK,
+        },
+        [OMAP4_VP_VDD_CORE_ID] = {
+                .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
+                .tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK,
+        },
+};
+u32 omap4_prm_vp_check_txdone(u8 vp_id)
+{
+        struct omap4_vp *vp = &omap4_vp[vp_id];
+        u32 irqstatus;
+        irqstatus = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
+                                                OMAP4430_PRM_OCP_SOCKET_INST,
+                                                vp->irqstatus_mpu);
+        return irqstatus & vp->tranxdone_status;
+}
+void omap4_prm_vp_clear_txdone(u8 vp_id)
+{
+        struct omap4_vp *vp = &omap4_vp[vp_id];
+        omap4_prminst_write_inst_reg(vp->tranxdone_status,
+                                     OMAP4430_PRM_PARTITION,
+                                     OMAP4430_PRM_OCP_SOCKET_INST,
+                                     vp->irqstatus_mpu);
+};
+u32 omap4_prm_vcvp_read(u8 offset)
+{
+        return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
+                                           OMAP4430_PRM_DEVICE_INST, offset);
+}
+void omap4_prm_vcvp_write(u32 val, u8 offset)
+{
+        omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION,
+                                     OMAP4430_PRM_DEVICE_INST, offset);
+}
+u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
+{
+        return omap4_prminst_rmw_inst_reg_bits(mask, bits,
+                                               OMAP4430_PRM_PARTITION,
+                                               OMAP4430_PRM_DEVICE_INST,
+                                               offset);
+}
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 7dfa379b625d..3d66ccd849d2 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -751,6 +751,18 @@ extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
 extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
 extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+/* OMAP4-specific VP functions */
+u32 omap4_prm_vp_check_txdone(u8 vp_id);
+void omap4_prm_vp_clear_txdone(u8 vp_id);
+/*
+ * OMAP4 access functions for voltage controller (VC) and
+ * voltage proccessor (VP) in the PRM.
+ */
+extern u32 omap4_prm_vcvp_read(u8 offset);
+extern void omap4_prm_vcvp_write(u32 val, u8 offset);
+extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
 # endif
 #endif
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
index da6f3a63b5d5..8f2782874771 100644
--- a/arch/arm/mach-omap2/sdrc.c
+++ b/arch/arm/mach-omap2/sdrc.c
@@ -117,15 +117,10 @@ int omap2_sdrc_get_params(unsigned long r,
 void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
 {
-        /* Static mapping, never released */
+        if (omap2_globals->sdrc)
-        if (omap2_globals->sdrc) {
+                omap2_sdrc_base = omap2_globals->sdrc;
-                omap2_sdrc_base = ioremap(omap2_globals->sdrc, SZ_64K);
+        if (omap2_globals->sms)
-                WARN_ON(!omap2_sdrc_base);
+                omap2_sms_base = omap2_globals->sms;
-        }
-        if (omap2_globals->sms) {
-                omap2_sms_base = ioremap(omap2_globals->sms, SZ_64K);
-                WARN_ON(!omap2_sms_base);
-        }
 }
 /**
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 466fc722fa0f..9992dbfdfdb3 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -107,28 +107,6 @@ struct omap_uart_state {
 static LIST_HEAD(uart_list);
 static u8 num_uarts;
-static int uart_idle_hwmod(struct omap_device *od)
-{
-        omap_hwmod_idle(od->hwmods[0]);
-        return 0;
-}
-static int uart_enable_hwmod(struct omap_device *od)
-{
-        omap_hwmod_enable(od->hwmods[0]);
-        return 0;
-}
-static struct omap_device_pm_latency omap_uart_latency[] = {
-        {
-                .deactivate_func = uart_idle_hwmod,
-                .activate_func   = uart_enable_hwmod,
-                .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
-        },
-};
 static inline unsigned int __serial_read_reg(struct uart_port *up,
                                             int offset)
 {
@@ -711,7 +689,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
 {
        struct omap_uart_state *uart;
        struct omap_hwmod *oh;
-        struct omap_device *od;
+        struct platform_device *pdev;
        void *pdata = NULL;
        u32 pdata_size = 0;
        char *name;
@@ -799,20 +777,19 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
        if (WARN_ON(!oh))
                return;
-        od = omap_device_build(name, uart->num, oh, pdata, pdata_size,
+        pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size,
-                               omap_uart_latency,
+                                 NULL, 0, false);
-                               ARRAY_SIZE(omap_uart_latency), false);
+        WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n",
-        WARN(IS_ERR(od), "Could not build omap_device for %s: %s.\n",
             name, oh->name);
-        omap_device_disable_idle_on_suspend(od);
+        omap_device_disable_idle_on_suspend(pdev);
        oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
        uart->irq = oh->mpu_irqs[0].irq;
        uart->regshift = 2;
        uart->mapbase = oh->slaves[0]->addr->pa_start;
        uart->membase = omap_hwmod_get_mpu_rt_va(oh);
-        uart->pdev = &od->pdev;
+        uart->pdev = pdev;
        oh->dev_attr = uart;
@@ -846,8 +823,8 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
        if ((cpu_is_omap34xx() && uart->padconf) ||
            (uart->wk_en && uart->wk_mask)) {
-                device_init_wakeup(&od->pdev.dev, true);
+                device_init_wakeup(&pdev->dev, true);
-                DEV_CREATE_FILE(&od->pdev.dev, &dev_attr_sleep_timeout);
+                DEV_CREATE_FILE(&pdev->dev, &dev_attr_sleep_timeout);
        }
        /* Enable the MDR1 errata for OMAP3 */
diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
index f438cf4d847b..53d9d0a5b39d 100644
--- a/arch/arm/mach-omap2/smartreflex-class3.c
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -15,7 +15,7 @@
 static int sr_class3_enable(struct voltagedomain *voltdm)
 {
-        unsigned long volt = omap_voltage_get_nom_volt(voltdm);
+        unsigned long volt = voltdm_get_voltage(voltdm);
        if (!volt) {
                pr_warning("%s: Curr voltage unknown. Cannot enable sr_%s\n",
@@ -32,7 +32,7 @@ static int sr_class3_disable(struct voltagedomain *voltdm, int is_volt_reset)
        omap_vp_disable(voltdm);
        sr_disable(voltdm);
        if (is_volt_reset)
-                omap_voltage_reset(voltdm);
+                voltdm_reset(voltdm);
        return 0;
 }
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index f49804f181d4..0347b93211e6 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -62,6 +62,7 @@ static LIST_HEAD(sr_list);
 static struct omap_sr_class_data *sr_class;
 static struct omap_sr_pmic_data *sr_pmic_data;
+static struct dentry            *sr_dbg_dir;
 static inline void sr_write_reg(struct omap_sr *sr, unsigned offset, u32 value)
 {
@@ -826,9 +827,10 @@ static int __init omap_sr_probe(struct platform_device *pdev)
        struct omap_sr *sr_info = kzalloc(sizeof(struct omap_sr), GFP_KERNEL);
        struct omap_sr_data *pdata = pdev->dev.platform_data;
        struct resource *mem, *irq;
-        struct dentry *vdd_dbg_dir, *nvalue_dir;
+        struct dentry *nvalue_dir;
        struct omap_volt_data *volt_data;
        int i, ret = 0;
+        char *name;
        if (!sr_info) {
                dev_err(&pdev->dev, "%s: unable to allocate sr_info\n",
@@ -899,18 +901,25 @@ static int __init omap_sr_probe(struct platform_device *pdev)
        }
        dev_info(&pdev->dev, "%s: SmartReflex driver initialized\n", __func__);
+        if (!sr_dbg_dir) {
+                sr_dbg_dir = debugfs_create_dir("smartreflex", NULL);
+                if (!sr_dbg_dir) {
+                        ret = PTR_ERR(sr_dbg_dir);
+                        pr_err("%s:sr debugfs dir creation failed(%d)\n",
+                                __func__, ret);
+                        goto err_iounmap;
+                }
+        }
-        /*
+        name = kasprintf(GFP_KERNEL, "sr_%s", sr_info->voltdm->name);
-         * If the voltage domain debugfs directory is not created, do
+        if (!name) {
-         * not try to create rest of the debugfs entries.
+                dev_err(&pdev->dev, "%s: Unable to alloc debugfs name\n",
-         */
+                        __func__);
-        vdd_dbg_dir = omap_voltage_get_dbgdir(sr_info->voltdm);
+                ret = -ENOMEM;
-        if (!vdd_dbg_dir) {
-                ret = -EINVAL;
                goto err_iounmap;
        }
+        sr_info->dbg_dir = debugfs_create_dir(name, sr_dbg_dir);
-        sr_info->dbg_dir = debugfs_create_dir("smartreflex", vdd_dbg_dir);
+        kfree(name);
        if (IS_ERR(sr_info->dbg_dir)) {
                dev_err(&pdev->dev, "%s: Unable to create debugfs directory\n",
                        __func__);
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index 10d3c5ee8018..9f43fcc05d3e 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -31,14 +31,6 @@
 static bool sr_enable_on_init;
-static struct omap_device_pm_latency omap_sr_latency[] = {
-        {
-                .deactivate_func = omap_device_idle_hwmods,
-                .activate_func   = omap_device_enable_hwmods,
-                .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST
-        },
-};
 /* Read EFUSE values from control registers for OMAP3430 */
 static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
                                struct omap_sr_data *sr_data)
@@ -80,7 +72,7 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
 static int sr_dev_init(struct omap_hwmod *oh, void *user)
 {
        struct omap_sr_data *sr_data;
-        struct omap_device *od;
+        struct platform_device *pdev;
        struct omap_volt_data *volt_data;
        char *name = "smartreflex";
        static int i;
@@ -102,7 +94,7 @@ static int sr_dev_init(struct omap_hwmod *oh, void *user)
        sr_data->senn_mod = 0x1;
        sr_data->senp_mod = 0x1;
-        sr_data->voltdm = omap_voltage_domain_lookup(oh->vdd_name);
+        sr_data->voltdm = voltdm_lookup(oh->vdd_name);
        if (IS_ERR(sr_data->voltdm)) {
                pr_err("%s: Unable to get voltage domain pointer for VDD %s\n",
                        __func__, oh->vdd_name);
@@ -120,10 +112,9 @@ static int sr_dev_init(struct omap_hwmod *oh, void *user)
        sr_data->enable_on_init = sr_enable_on_init;
-        od = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data),
+        pdev = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data),
-                               omap_sr_latency,
+                                 NULL, 0, 0);
-                               ARRAY_SIZE(omap_sr_latency), 0);
+        if (IS_ERR(pdev))
-        if (IS_ERR(od))
                pr_warning("%s: Could not build omap_device for %s: %s.\n\n",
                        __func__, name, oh->name);
 exit:
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index cf1de7d2630d..e49fc7be2229 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -35,6 +35,7 @@
 #include <linux/irq.h>
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
+#include <linux/slab.h>
 #include <asm/mach/time.h>
 #include <plat/dmtimer.h>
@@ -42,6 +43,10 @@
 #include <asm/sched_clock.h>
 #include <plat/common.h>
 #include <plat/omap_hwmod.h>
+#include <plat/omap_device.h>
+#include <plat/omap-pm.h>
+#include "powerdomain.h"
 /* Parent clocks, eventually these will come from the clock framework */
@@ -67,7 +72,7 @@
 /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
 #define MAX_GPTIMER_ID          12
-u32 sys_timer_reserved;
+static u32 sys_timer_reserved;
 /* Clockevent code */
@@ -78,7 +83,7 @@ static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
 {
        struct clock_event_device *evt = &clockevent_gpt;
-        __omap_dm_timer_write_status(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
+        __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
        evt->event_handler(evt);
        return IRQ_HANDLED;
@@ -93,7 +98,7 @@ static struct irqaction omap2_gp_timer_irq = {
 static int omap2_gp_timer_set_next_event(unsigned long cycles,
                                         struct clock_event_device *evt)
 {
-        __omap_dm_timer_load_start(clkev.io_base, OMAP_TIMER_CTRL_ST,
+        __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
                                                0xffffffff - cycles, 1);
        return 0;
@@ -104,16 +109,16 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
 {
        u32 period;
-        __omap_dm_timer_stop(clkev.io_base, 1, clkev.rate);
+        __omap_dm_timer_stop(&clkev, 1, clkev.rate);
        switch (mode) {
        case CLOCK_EVT_MODE_PERIODIC:
                period = clkev.rate / HZ;
                period -= 1;
                /* Looks like we need to first set the load value separately */
-                __omap_dm_timer_write(clkev.io_base, OMAP_TIMER_LOAD_REG,
+                __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
                                        0xffffffff - period, 1);
-                __omap_dm_timer_load_start(clkev.io_base,
+                __omap_dm_timer_load_start(&clkev,
                                        OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
                                                0xffffffff - period, 1);
                break;
@@ -189,7 +194,8 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
                        clk_put(src);
                }
        }
-        __omap_dm_timer_reset(timer->io_base, 1, 1);
+        __omap_dm_timer_init_regs(timer);
+        __omap_dm_timer_reset(timer, 1, 1);
        timer->posted = 1;
        timer->rate = clk_get_rate(timer->fclk);
@@ -210,7 +216,7 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
        omap2_gp_timer_irq.dev_id = (void *)&clkev;
        setup_irq(clkev.irq, &omap2_gp_timer_irq);
-        __omap_dm_timer_int_enable(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
+        __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
        clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
                                     clockevent_gpt.shift);
@@ -251,7 +257,7 @@ static struct omap_dm_timer clksrc;
 static DEFINE_CLOCK_DATA(cd);
 static cycle_t clocksource_read_cycles(struct clocksource *cs)
 {
-        return (cycle_t)__omap_dm_timer_read_counter(clksrc.io_base, 1);
+        return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1);
 }
 static struct clocksource clocksource_gpt = {
@@ -266,7 +272,7 @@ static void notrace dmtimer_update_sched_clock(void)
 {
        u32 cyc;
-        cyc = __omap_dm_timer_read_counter(clksrc.io_base, 1);
+        cyc = __omap_dm_timer_read_counter(&clksrc, 1);
        update_sched_clock(&cd, cyc, (u32)~0);
 }
@@ -276,7 +282,7 @@ unsigned long long notrace sched_clock(void)
        u32 cyc = 0;
        if (clksrc.reserved)
-                cyc = __omap_dm_timer_read_counter(clksrc.io_base, 1);
+                cyc = __omap_dm_timer_read_counter(&clksrc, 1);
        return cyc_to_sched_clock(&cd, cyc, (u32)~0);
 }
@@ -293,7 +299,7 @@ static void __init omap2_gp_clocksource_init(int gptimer_id,
        pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
                gptimer_id, clksrc.rate);
-        __omap_dm_timer_load_start(clksrc.io_base,
+        __omap_dm_timer_load_start(&clksrc,
                        OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
        init_sched_clock(&cd, dmtimer_update_sched_clock, 32, clksrc.rate);
@@ -341,3 +347,167 @@ static void __init omap4_timer_init(void)
 }
 OMAP_SYS_TIMER(4)
 #endif
+/**
+ * omap2_dm_timer_set_src - change the timer input clock source
+ * @pdev:       timer platform device pointer
+ * @source:     array index of parent clock source
+ */
+static int omap2_dm_timer_set_src(struct platform_device *pdev, int source)
+{
+        int ret;
+        struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
+        struct clk *fclk, *parent;
+        char *parent_name = NULL;
+        fclk = clk_get(&pdev->dev, "fck");
+        if (IS_ERR_OR_NULL(fclk)) {
+                dev_err(&pdev->dev, "%s: %d: clk_get() FAILED\n",
+                                __func__, __LINE__);
+                return -EINVAL;
+        }
+        switch (source) {
+        case OMAP_TIMER_SRC_SYS_CLK:
+                parent_name = "sys_ck";
+                break;
+        case OMAP_TIMER_SRC_32_KHZ:
+                parent_name = "32k_ck";
+                break;
+        case OMAP_TIMER_SRC_EXT_CLK:
+                if (pdata->timer_ip_version == OMAP_TIMER_IP_VERSION_1) {
+                        parent_name = "alt_ck";
+                        break;
+                }
+                dev_err(&pdev->dev, "%s: %d: invalid clk src.\n",
+                        __func__, __LINE__);
+                clk_put(fclk);
+                return -EINVAL;
+        }
+        parent = clk_get(&pdev->dev, parent_name);
+        if (IS_ERR_OR_NULL(parent)) {
+                dev_err(&pdev->dev, "%s: %d: clk_get() %s FAILED\n",
+                        __func__, __LINE__, parent_name);
+                clk_put(fclk);
+                return -EINVAL;
+        }
+        ret = clk_set_parent(fclk, parent);
+        if (IS_ERR_VALUE(ret)) {
+                dev_err(&pdev->dev, "%s: clk_set_parent() to %s FAILED\n",
+                        __func__, parent_name);
+                ret = -EINVAL;
+        }
+        clk_put(parent);
+        clk_put(fclk);
+        return ret;
+}
+struct omap_device_pm_latency omap2_dmtimer_latency[] = {
+        {
+                .deactivate_func = omap_device_idle_hwmods,
+                .activate_func   = omap_device_enable_hwmods,
+                .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+        },
+};
+/**
+ * omap_timer_init - build and register timer device with an
+ * associated timer hwmod
+ * @oh: timer hwmod pointer to be used to build timer device
+ * @user:       parameter that can be passed from calling hwmod API
+ *
+ * Called by omap_hwmod_for_each_by_class to register each of the timer
+ * devices present in the system. The number of timer devices is known
+ * by parsing through the hwmod database for a given class name. At the
+ * end of function call memory is allocated for timer device and it is
+ * registered to the framework ready to be proved by the driver.
+ */
+static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
+{
+        int id;
+        int ret = 0;
+        char *name = "omap_timer";
+        struct dmtimer_platform_data *pdata;
+        struct platform_device *pdev;
+        struct omap_timer_capability_dev_attr *timer_dev_attr;
+        struct powerdomain *pwrdm;
+        pr_debug("%s: %s\n", __func__, oh->name);
+        /* on secure device, do not register secure timer */
+        timer_dev_attr = oh->dev_attr;
+        if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
+                if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
+                        return ret;
+        pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
+        if (!pdata) {
+                pr_err("%s: No memory for [%s]\n", __func__, oh->name);
+                return -ENOMEM;
+        }
+        /*
+         * Extract the IDs from name field in hwmod database
+         * and use the same for constructing ids' for the
+         * timer devices. In a way, we are avoiding usage of
+         * static variable witin the function to do the same.
+         * CAUTION: We have to be careful and make sure the
+         * name in hwmod database does not change in which case
+         * we might either make corresponding change here or
+         * switch back static variable mechanism.
+         */
+        sscanf(oh->name, "timer%2d", &id);
+        pdata->set_timer_src = omap2_dm_timer_set_src;
+        pdata->timer_ip_version = oh->class->rev;
+        /* Mark clocksource and clockevent timers as reserved */
+        if ((sys_timer_reserved >> (id - 1)) & 0x1)
+                pdata->reserved = 1;
+        pwrdm = omap_hwmod_get_pwrdm(oh);
+        pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm);
+#ifdef CONFIG_PM
+        pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
+#endif
+        pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
+                        omap2_dmtimer_latency,
+                        ARRAY_SIZE(omap2_dmtimer_latency),
+                        0);
+        if (IS_ERR(pdev)) {
+                pr_err("%s: Can't build omap_device for %s: %s.\n",
+                        __func__, name, oh->name);
+                ret = -EINVAL;
+        }
+        kfree(pdata);
+        return ret;
+}
+/**
+ * omap2_dm_timer_init - top level regular device initialization
+ *
+ * Uses dedicated hwmod api to parse through hwmod database for
+ * given class name and then build and register the timer device.
+ */
+static int __init omap2_dm_timer_init(void)
+{
+        int ret;
+        ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
+        if (unlikely(ret)) {
+                pr_err("%s: device registration failed.\n", __func__);
+                return -EINVAL;
+        }
+        return 0;
+}
+arch_initcall(omap2_dm_timer_init);
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 19e4dac62a8c..47fb5d607630 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -60,14 +60,6 @@ static struct musb_hdrc_platform_data musb_plat = {
 static u64 musb_dmamask = DMA_BIT_MASK(32);
-static struct omap_device_pm_latency omap_musb_latency[] = {
-        {
-                .deactivate_func        = omap_device_idle_hwmods,
-                .activate_func          = omap_device_enable_hwmods,
-                .flags                  = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
-        },
-};
 static void usb_musb_mux_init(struct omap_musb_board_data *board_data)
 {
        switch (board_data->interface_type) {
@@ -115,7 +107,6 @@ static struct omap_musb_board_data musb_default_board_data = {
 void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
 {
        struct omap_hwmod               *oh;
-        struct omap_device              *od;
        struct platform_device          *pdev;
        struct device                   *dev;
        int                             bus_id = -1;
@@ -145,22 +136,19 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
                name = "musb-omap2430";
        }
-        oh = omap_hwmod_lookup(oh_name);
+        oh = omap_hwmod_lookup(oh_name);
-        if (!oh) {
+        if (WARN(!oh, "%s: could not find omap_hwmod for %s\n",
-                pr_err("Could not look up %s\n", oh_name);
+                 __func__, oh_name))
-                return;
+                return;
-        }
-        od = omap_device_build(name, bus_id, oh, &musb_plat,
+        pdev = omap_device_build(name, bus_id, oh, &musb_plat,
-                               sizeof(musb_plat), omap_musb_latency,
+                               sizeof(musb_plat), NULL, 0, false);
-                               ARRAY_SIZE(omap_musb_latency), false);
+        if (IS_ERR(pdev)) {
-        if (IS_ERR(od)) {
                pr_err("Could not build omap_device for %s %s\n",
                                                name, oh_name);
                return;
        }
-        pdev = &od->pdev;
        dev = &pdev->dev;
        get_device(dev);
        dev->dma_mask = &musb_dmamask;
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
new file mode 100644
index 000000000000..031d116fbf10
--- /dev/null
+++ b/arch/arm/mach-omap2/vc.c
@@ -0,0 +1,367 @@
+/*
+ * OMAP Voltage Controller (VC) interface
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <plat/cpu.h>
+#include "voltage.h"
+#include "vc.h"
+#include "prm-regbits-34xx.h"
+#include "prm-regbits-44xx.h"
+#include "prm44xx.h"
+/**
+ * struct omap_vc_channel_cfg - describe the cfg_channel bitfield
+ * @sa: bit for slave address
+ * @rav: bit for voltage configuration register
+ * @rac: bit for command configuration register
+ * @racen: enable bit for RAC
+ * @cmd: bit for command value set selection
+ *
+ * Channel configuration bits, common for OMAP3+
+ * OMAP3 register: PRM_VC_CH_CONF
+ * OMAP4 register: PRM_VC_CFG_CHANNEL
+ * OMAP5 register: PRM_VC_SMPS_<voltdm>_CONFIG
+ */
+struct omap_vc_channel_cfg {
+        u8 sa;
+        u8 rav;
+        u8 rac;
+        u8 racen;
+        u8 cmd;
+};
+static struct omap_vc_channel_cfg vc_default_channel_cfg = {
+        .sa    = BIT(0),
+        .rav   = BIT(1),
+        .rac   = BIT(2),
+        .racen = BIT(3),
+        .cmd   = BIT(4),
+};
+/*
+ * On OMAP3+, all VC channels have the above default bitfield
+ * configuration, except the OMAP4 MPU channel.  This appears
+ * to be a freak accident as every other VC channel has the
+ * default configuration, thus creating a mutant channel config.
+ */
+static struct omap_vc_channel_cfg vc_mutant_channel_cfg = {
+        .sa    = BIT(0),
+        .rav   = BIT(2),
+        .rac   = BIT(3),
+        .racen = BIT(4),
+        .cmd   = BIT(1),
+};
+static struct omap_vc_channel_cfg *vc_cfg_bits;
+#define CFG_CHANNEL_MASK 0x1f
+/**
+ * omap_vc_config_channel - configure VC channel to PMIC mappings
+ * @voltdm: pointer to voltagdomain defining the desired VC channel
+ *
+ * Configures the VC channel to PMIC mappings for the following
+ * PMIC settings
+ * - i2c slave address (SA)
+ * - voltage configuration address (RAV)
+ * - command configuration address (RAC) and enable bit (RACEN)
+ * - command values for ON, ONLP, RET and OFF (CMD)
+ *
+ * This function currently only allows flexible configuration of the
+ * non-default channel.  Starting with OMAP4, there are more than 2
+ * channels, with one defined as the default (on OMAP4, it's MPU.)
+ * Only the non-default channel can be configured.
+ */
+static int omap_vc_config_channel(struct voltagedomain *voltdm)
+{
+        struct omap_vc_channel *vc = voltdm->vc;
+        /*
+         * For default channel, the only configurable bit is RACEN.
+         * All others must stay at zero (see function comment above.)
+         */
+        if (vc->flags & OMAP_VC_CHANNEL_DEFAULT)
+                vc->cfg_channel &= vc_cfg_bits->racen;
+        voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift,
+                    vc->cfg_channel << vc->cfg_channel_sa_shift,
+                    vc->cfg_channel_reg);
+        return 0;
+}
+/* Voltage scale and accessory APIs */
+int omap_vc_pre_scale(struct voltagedomain *voltdm,
+                      unsigned long target_volt,
+                      u8 *target_vsel, u8 *current_vsel)
+{
+        struct omap_vc_channel *vc = voltdm->vc;
+        u32 vc_cmdval;
+        /* Check if sufficient pmic info is available for this vdd */
+        if (!voltdm->pmic) {
+                pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
+                        __func__, voltdm->name);
+                return -EINVAL;
+        }
+        if (!voltdm->pmic->uv_to_vsel) {
+                pr_err("%s: PMIC function to convert voltage in uV to"
+                        "vsel not registered. Hence unable to scale voltage"
+                        "for vdd_%s\n", __func__, voltdm->name);
+                return -ENODATA;
+        }
+        if (!voltdm->read || !voltdm->write) {
+                pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+                        __func__, voltdm->name);
+                return -EINVAL;
+        }
+        *target_vsel = voltdm->pmic->uv_to_vsel(target_volt);
+        *current_vsel = voltdm->pmic->uv_to_vsel(voltdm->nominal_volt);
+        /* Setting the ON voltage to the new target voltage */
+        vc_cmdval = voltdm->read(vc->cmdval_reg);
+        vc_cmdval &= ~vc->common->cmd_on_mask;
+        vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift);
+        voltdm->write(vc_cmdval, vc->cmdval_reg);
+        omap_vp_update_errorgain(voltdm, target_volt);
+        return 0;
+}
+void omap_vc_post_scale(struct voltagedomain *voltdm,
+                        unsigned long target_volt,
+                        u8 target_vsel, u8 current_vsel)
+{
+        u32 smps_steps = 0, smps_delay = 0;
+        smps_steps = abs(target_vsel - current_vsel);
+        /* SMPS slew rate / step size. 2us added as buffer. */
+        smps_delay = ((smps_steps * voltdm->pmic->step_size) /
+                        voltdm->pmic->slew_rate) + 2;
+        udelay(smps_delay);
+}
+/* vc_bypass_scale - VC bypass method of voltage scaling */
+int omap_vc_bypass_scale(struct voltagedomain *voltdm,
+                         unsigned long target_volt)
+{
+        struct omap_vc_channel *vc = voltdm->vc;
+        u32 loop_cnt = 0, retries_cnt = 0;
+        u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
+        u8 target_vsel, current_vsel;
+        int ret;
+        ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, &current_vsel);
+        if (ret)
+                return ret;
+        vc_valid = vc->common->valid;
+        vc_bypass_val_reg = vc->common->bypass_val_reg;
+        vc_bypass_value = (target_vsel << vc->common->data_shift) |
+                (vc->volt_reg_addr << vc->common->regaddr_shift) |
+                (vc->i2c_slave_addr << vc->common->slaveaddr_shift);
+        voltdm->write(vc_bypass_value, vc_bypass_val_reg);
+        voltdm->write(vc_bypass_value | vc_valid, vc_bypass_val_reg);
+        vc_bypass_value = voltdm->read(vc_bypass_val_reg);
+        /*
+         * Loop till the bypass command is acknowledged from the SMPS.
+         * NOTE: This is legacy code. The loop count and retry count needs
+         * to be revisited.
+         */
+        while (!(vc_bypass_value & vc_valid)) {
+                loop_cnt++;
+                if (retries_cnt > 10) {
+                        pr_warning("%s: Retry count exceeded\n", __func__);
+                        return -ETIMEDOUT;
+                }
+                if (loop_cnt > 50) {
+                        retries_cnt++;
+                        loop_cnt = 0;
+                        udelay(10);
+                }
+                vc_bypass_value = voltdm->read(vc_bypass_val_reg);
+        }
+        omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
+        return 0;
+}
+static void __init omap3_vfsm_init(struct voltagedomain *voltdm)
+{
+        /*
+         * Voltage Manager FSM parameters init
+         * XXX This data should be passed in from the board file
+         */
+        voltdm->write(OMAP3_CLKSETUP, OMAP3_PRM_CLKSETUP_OFFSET);
+        voltdm->write(OMAP3_VOLTOFFSET, OMAP3_PRM_VOLTOFFSET_OFFSET);
+        voltdm->write(OMAP3_VOLTSETUP2, OMAP3_PRM_VOLTSETUP2_OFFSET);
+}
+static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
+{
+        static bool is_initialized;
+        if (is_initialized)
+                return;
+        omap3_vfsm_init(voltdm);
+        is_initialized = true;
+}
+/* OMAP4 specific voltage init functions */
+static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
+{
+        static bool is_initialized;
+        u32 vc_val;
+        if (is_initialized)
+                return;
+        /* XXX These are magic numbers and do not belong! */
+        vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
+        voltdm->write(vc_val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
+        is_initialized = true;
+}
+/**
+ * omap_vc_i2c_init - initialize I2C interface to PMIC
+ * @voltdm: voltage domain containing VC data
+ *
+ * Use PMIC supplied seetings for I2C high-speed mode and
+ * master code (if set) and program the VC I2C configuration
+ * register.
+ *
+ * The VC I2C configuration is common to all VC channels,
+ * so this function only configures I2C for the first VC
+ * channel registers.  All other VC channels will use the
+ * same configuration.
+ */
+static void __init omap_vc_i2c_init(struct voltagedomain *voltdm)
+{
+        struct omap_vc_channel *vc = voltdm->vc;
+        static bool initialized;
+        static bool i2c_high_speed;
+        u8 mcode;
+        if (initialized) {
+                if (voltdm->pmic->i2c_high_speed != i2c_high_speed)
+                        pr_warn("%s: I2C config for all channels must match.",
+                                __func__);
+                return;
+        }
+        i2c_high_speed = voltdm->pmic->i2c_high_speed;
+        if (i2c_high_speed)
+                voltdm->rmw(vc->common->i2c_cfg_hsen_mask,
+                            vc->common->i2c_cfg_hsen_mask,
+                            vc->common->i2c_cfg_reg);
+        mcode = voltdm->pmic->i2c_mcode;
+        if (mcode)
+                voltdm->rmw(vc->common->i2c_mcode_mask,
+                            mcode << __ffs(vc->common->i2c_mcode_mask),
+                            vc->common->i2c_cfg_reg);
+        initialized = true;
+}
+void __init omap_vc_init_channel(struct voltagedomain *voltdm)
+{
+        struct omap_vc_channel *vc = voltdm->vc;
+        u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
+        u32 val;
+        if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) {
+                pr_err("%s: PMIC info requried to configure vc for"
+                        "vdd_%s not populated.Hence cannot initialize vc\n",
+                        __func__, voltdm->name);
+                return;
+        }
+        if (!voltdm->read || !voltdm->write) {
+                pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+                        __func__, voltdm->name);
+                return;
+        }
+        vc->cfg_channel = 0;
+        if (vc->flags & OMAP_VC_CHANNEL_CFG_MUTANT)
+                vc_cfg_bits = &vc_mutant_channel_cfg;
+        else
+                vc_cfg_bits = &vc_default_channel_cfg;
+        /* get PMIC/board specific settings */
+        vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr;
+        vc->volt_reg_addr = voltdm->pmic->volt_reg_addr;
+        vc->cmd_reg_addr = voltdm->pmic->cmd_reg_addr;
+        vc->setup_time = voltdm->pmic->volt_setup_time;
+        /* Configure the i2c slave address for this VC */
+        voltdm->rmw(vc->smps_sa_mask,
+                    vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
+                    vc->smps_sa_reg);
+        vc->cfg_channel |= vc_cfg_bits->sa;
+        /*
+         * Configure the PMIC register addresses.
+         */
+        voltdm->rmw(vc->smps_volra_mask,
+                    vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
+                    vc->smps_volra_reg);
+        vc->cfg_channel |= vc_cfg_bits->rav;
+        if (vc->cmd_reg_addr) {
+                voltdm->rmw(vc->smps_cmdra_mask,
+                            vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
+                            vc->smps_cmdra_reg);
+                vc->cfg_channel |= vc_cfg_bits->rac | vc_cfg_bits->racen;
+        }
+        /* Set up the on, inactive, retention and off voltage */
+        on_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->on_volt);
+        onlp_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->onlp_volt);
+        ret_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->ret_volt);
+        off_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->off_volt);
+        val = ((on_vsel << vc->common->cmd_on_shift) |
+               (onlp_vsel << vc->common->cmd_onlp_shift) |
+               (ret_vsel << vc->common->cmd_ret_shift) |
+               (off_vsel << vc->common->cmd_off_shift));
+        voltdm->write(val, vc->cmdval_reg);
+        vc->cfg_channel |= vc_cfg_bits->cmd;
+        /* Channel configuration */
+        omap_vc_config_channel(voltdm);
+        /* Configure the setup times */
+        voltdm->rmw(voltdm->vfsm->voltsetup_mask,
+                    vc->setup_time << __ffs(voltdm->vfsm->voltsetup_mask),
+                    voltdm->vfsm->voltsetup_reg);
+        omap_vc_i2c_init(voltdm);
+        if (cpu_is_omap34xx())
+                omap3_vc_init_channel(voltdm);
+        else if (cpu_is_omap44xx())
+                omap4_vc_init_channel(voltdm);
+}
diff --git a/arch/arm/mach-omap2/vc.h b/arch/arm/mach-omap2/vc.h
index e7767771de49..478bf6b432c4 100644
--- a/arch/arm/mach-omap2/vc.h
+++ b/arch/arm/mach-omap2/vc.h
@@ -19,12 +19,12 @@
 #include <linux/kernel.h>
+struct voltagedomain;
 /**
- * struct omap_vc_common_data - per-VC register/bitfield data
+ * struct omap_vc_common - per-VC register/bitfield data
 * @cmd_on_mask: ON bitmask in PRM_VC_CMD_VAL* register
 * @valid: VALID bitmask in PRM_VC_BYPASS_VAL register
- * @smps_sa_reg: Offset of PRM_VC_SMPS_SA reg from PRM start
- * @smps_volra_reg: Offset of PRM_VC_SMPS_VOL_RA reg from PRM start
 * @bypass_val_reg: Offset of PRM_VC_BYPASS_VAL reg from PRM start
 * @data_shift: DATA field shift in PRM_VC_BYPASS_VAL register
 * @slaveaddr_shift: SLAVEADDR field shift in PRM_VC_BYPASS_VAL register
@@ -33,15 +33,16 @@
 * @cmd_onlp_shift: ONLP field shift in PRM_VC_CMD_VAL_* register
 * @cmd_ret_shift: RET field shift in PRM_VC_CMD_VAL_* register
 * @cmd_off_shift: OFF field shift in PRM_VC_CMD_VAL_* register
+ * @i2c_cfg_reg: I2C configuration register offset
+ * @i2c_cfg_hsen_mask: high-speed mode bit field mask in I2C config register
+ * @i2c_mcode_mask: MCODE field mask for I2C config register
 *
 * XXX One of cmd_on_mask and cmd_on_shift are not needed
 * XXX VALID should probably be a shift, not a mask
 */
-struct omap_vc_common_data {
+struct omap_vc_common {
        u32 cmd_on_mask;
        u32 valid;
-        u8 smps_sa_reg;
-        u8 smps_volra_reg;
        u8 bypass_val_reg;
        u8 data_shift;
        u8 slaveaddr_shift;
@@ -50,34 +51,75 @@ struct omap_vc_common_data {
        u8 cmd_onlp_shift;
        u8 cmd_ret_shift;
        u8 cmd_off_shift;
+        u8 i2c_cfg_reg;
+        u8 i2c_cfg_hsen_mask;
+        u8 i2c_mcode_mask;
 };
+/* omap_vc_channel.flags values */
+#define OMAP_VC_CHANNEL_DEFAULT BIT(0)
+#define OMAP_VC_CHANNEL_CFG_MUTANT BIT(1)
 /**
- * struct omap_vc_instance_data - VC per-instance data
+ * struct omap_vc_channel - VC per-instance data
- * @vc_common: pointer to VC common data for this platform
+ * @i2c_slave_addr: I2C slave address of PMIC for this VC channel
- * @smps_sa_mask: SA* bitmask in the PRM_VC_SMPS_SA register
+ * @volt_reg_addr: voltage configuration register address
- * @smps_volra_mask: VOLRA* bitmask in the PRM_VC_VOL_RA register
+ * @cmd_reg_addr: command configuration register address
- * @smps_sa_shift: SA* field shift in the PRM_VC_SMPS_SA register
+ * @setup_time: setup time (in sys_clk cycles) of regulator for this channel
- * @smps_volra_shift: VOLRA* field shift in the PRM_VC_VOL_RA register
+ * @cfg_channel: current value of VC channel configuration register
+ * @i2c_high_speed: whether or not to use I2C high-speed mode
 *
- * XXX It is not necessary to have both a *_mask and a *_shift -
+ * @common: pointer to VC common data for this platform
- *     remove one
+ * @smps_sa_mask: i2c slave address bitmask in the PRM_VC_SMPS_SA register
+ * @smps_volra_mask: VOLRA* bitmask in the PRM_VC_VOL_RA register
+ * @smps_cmdra_mask: CMDRA* bitmask in the PRM_VC_CMD_RA register
+ * @cmdval_reg: register for on/ret/off voltage level values for this channel
+ * @smps_sa_reg: Offset of PRM_VC_SMPS_SA reg from PRM start
+ * @smps_volra_reg: Offset of PRM_VC_SMPS_VOL_RA reg from PRM start
+ * @smps_cmdra_reg: Offset of PRM_VC_SMPS_CMD_RA reg from PRM start
+ * @cfg_channel_reg: VC channel configuration register
+ * @cfg_channel_sa_shift: bit shift for slave address cfg_channel register
+ * @flags: VC channel-specific flags (optional)
 */
-struct omap_vc_instance_data {
+struct omap_vc_channel {
-        const struct omap_vc_common_data *vc_common;
+        /* channel state */
+        u16 i2c_slave_addr;
+        u16 volt_reg_addr;
+        u16 cmd_reg_addr;
+        u16 setup_time;
+        u8 cfg_channel;
+        bool i2c_high_speed;
+        /* register access data */
+        const struct omap_vc_common *common;
        u32 smps_sa_mask;
        u32 smps_volra_mask;
+        u32 smps_cmdra_mask;
        u8 cmdval_reg;
-        u8 smps_sa_shift;
+        u8 smps_sa_reg;
-        u8 smps_volra_shift;
+        u8 smps_volra_reg;
+        u8 smps_cmdra_reg;
+        u8 cfg_channel_reg;
+        u8 cfg_channel_sa_shift;
+        u8 flags;
 };
-extern struct omap_vc_instance_data omap3_vc1_data;
+extern struct omap_vc_channel omap3_vc_mpu;
-extern struct omap_vc_instance_data omap3_vc2_data;
+extern struct omap_vc_channel omap3_vc_core;
+extern struct omap_vc_channel omap4_vc_mpu;
+extern struct omap_vc_channel omap4_vc_iva;
+extern struct omap_vc_channel omap4_vc_core;
-extern struct omap_vc_instance_data omap4_vc_mpu_data;
+void omap_vc_init_channel(struct voltagedomain *voltdm);
-extern struct omap_vc_instance_data omap4_vc_iva_data;
+int omap_vc_pre_scale(struct voltagedomain *voltdm,
-extern struct omap_vc_instance_data omap4_vc_core_data;
+                      unsigned long target_volt,
+                      u8 *target_vsel, u8 *current_vsel);
+void omap_vc_post_scale(struct voltagedomain *voltdm,
+                        unsigned long target_volt,
+                        u8 target_vsel, u8 current_vsel);
+int omap_vc_bypass_scale(struct voltagedomain *voltdm,
+                         unsigned long target_volt);
 #endif
diff --git a/arch/arm/mach-omap2/vc3xxx_data.c b/arch/arm/mach-omap2/vc3xxx_data.c
index f37dc4bc379a..cfe348e1af0e 100644
--- a/arch/arm/mach-omap2/vc3xxx_data.c
+++ b/arch/arm/mach-omap2/vc3xxx_data.c
@@ -29,9 +29,7 @@
 * VC data common to 34xx/36xx chips
 * XXX This stuff presumably belongs in the vc3xxx.c or vc.c file.
 */
-static struct omap_vc_common_data omap3_vc_common = {
+static struct omap_vc_common omap3_vc_common = {
-        .smps_sa_reg     = OMAP3_PRM_VC_SMPS_SA_OFFSET,
-        .smps_volra_reg  = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET,
        .bypass_val_reg  = OMAP3_PRM_VC_BYPASS_VAL_OFFSET,
        .data_shift      = OMAP3430_DATA_SHIFT,
        .slaveaddr_shift = OMAP3430_SLAVEADDR_SHIFT,
@@ -42,22 +40,33 @@ static struct omap_vc_common_data omap3_vc_common = {
        .cmd_onlp_shift  = OMAP3430_VC_CMD_ONLP_SHIFT,
        .cmd_ret_shift   = OMAP3430_VC_CMD_RET_SHIFT,
        .cmd_off_shift   = OMAP3430_VC_CMD_OFF_SHIFT,
+        .i2c_cfg_hsen_mask = OMAP3430_HSEN_MASK,
+        .i2c_cfg_reg     = OMAP3_PRM_VC_I2C_CFG_OFFSET,
+        .i2c_mcode_mask  = OMAP3430_MCODE_MASK,
 };
-struct omap_vc_instance_data omap3_vc1_data = {
+struct omap_vc_channel omap3_vc_mpu = {
-        .vc_common = &omap3_vc_common,
+        .common = &omap3_vc_common,
+        .smps_sa_reg     = OMAP3_PRM_VC_SMPS_SA_OFFSET,
+        .smps_volra_reg  = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET,
+        .smps_cmdra_reg  = OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET,
+        .cfg_channel_reg = OMAP3_PRM_VC_CH_CONF_OFFSET,
        .cmdval_reg = OMAP3_PRM_VC_CMD_VAL_0_OFFSET,
-        .smps_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT,
        .smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA0_MASK,
-        .smps_volra_shift = OMAP3430_VOLRA0_SHIFT,
        .smps_volra_mask = OMAP3430_VOLRA0_MASK,
+        .smps_cmdra_mask = OMAP3430_CMDRA0_MASK,
+        .cfg_channel_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT,
 };
-struct omap_vc_instance_data omap3_vc2_data = {
+struct omap_vc_channel omap3_vc_core = {
-        .vc_common = &omap3_vc_common,
+        .common = &omap3_vc_common,
+        .smps_sa_reg     = OMAP3_PRM_VC_SMPS_SA_OFFSET,
+        .smps_volra_reg  = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET,
+        .smps_cmdra_reg  = OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET,
+        .cfg_channel_reg = OMAP3_PRM_VC_CH_CONF_OFFSET,
        .cmdval_reg = OMAP3_PRM_VC_CMD_VAL_1_OFFSET,
-        .smps_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT,
        .smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA1_MASK,
-        .smps_volra_shift = OMAP3430_VOLRA1_SHIFT,
        .smps_volra_mask = OMAP3430_VOLRA1_MASK,
+        .smps_cmdra_mask = OMAP3430_CMDRA1_MASK,
+        .cfg_channel_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT,
 };
diff --git a/arch/arm/mach-omap2/vc44xx_data.c b/arch/arm/mach-omap2/vc44xx_data.c
index a98da8ddec52..2740a968145e 100644
--- a/arch/arm/mach-omap2/vc44xx_data.c
+++ b/arch/arm/mach-omap2/vc44xx_data.c
@@ -30,9 +30,7 @@
 * VC data common to 44xx chips
 * XXX This stuff presumably belongs in the vc3xxx.c or vc.c file.
 */
-static const struct omap_vc_common_data omap4_vc_common = {
+static const struct omap_vc_common omap4_vc_common = {
-        .smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET,
-        .smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET,
        .bypass_val_reg = OMAP4_PRM_VC_VAL_BYPASS_OFFSET,
        .data_shift = OMAP4430_DATA_SHIFT,
        .slaveaddr_shift = OMAP4430_SLAVEADDR_SHIFT,
@@ -43,33 +41,49 @@ static const struct omap_vc_common_data omap4_vc_common = {
        .cmd_onlp_shift = OMAP4430_ONLP_SHIFT,
        .cmd_ret_shift = OMAP4430_RET_SHIFT,
        .cmd_off_shift = OMAP4430_OFF_SHIFT,
+        .i2c_cfg_reg = OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET,
+        .i2c_cfg_hsen_mask = OMAP4430_HSMODEEN_MASK,
+        .i2c_mcode_mask  = OMAP4430_HSMCODE_MASK,
 };
 /* VC instance data for each controllable voltage line */
-struct omap_vc_instance_data omap4_vc_mpu_data = {
+struct omap_vc_channel omap4_vc_mpu = {
-        .vc_common = &omap4_vc_common,
+        .flags = OMAP_VC_CHANNEL_DEFAULT | OMAP_VC_CHANNEL_CFG_MUTANT,
+        .common = &omap4_vc_common,
+        .smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET,
+        .smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET,
+        .smps_cmdra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET,
+        .cfg_channel_reg = OMAP4_PRM_VC_CFG_CHANNEL_OFFSET,
        .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET,
-        .smps_sa_shift = OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT,
        .smps_sa_mask = OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK,
-        .smps_volra_shift = OMAP4430_VOLRA_VDD_MPU_L_SHIFT,
        .smps_volra_mask = OMAP4430_VOLRA_VDD_MPU_L_MASK,
+        .smps_cmdra_mask = OMAP4430_CMDRA_VDD_MPU_L_MASK,
+        .cfg_channel_sa_shift = OMAP4430_SA_VDD_MPU_L_SHIFT,
 };
-struct omap_vc_instance_data omap4_vc_iva_data = {
+struct omap_vc_channel omap4_vc_iva = {
-        .vc_common = &omap4_vc_common,
+        .common = &omap4_vc_common,
+        .smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET,
+        .smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET,
+        .smps_cmdra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET,
+        .cfg_channel_reg = OMAP4_PRM_VC_CFG_CHANNEL_OFFSET,
        .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET,
-        .smps_sa_shift = OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT,
        .smps_sa_mask = OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK,
-        .smps_volra_shift = OMAP4430_VOLRA_VDD_IVA_L_SHIFT,
        .smps_volra_mask = OMAP4430_VOLRA_VDD_IVA_L_MASK,
+        .smps_cmdra_mask = OMAP4430_CMDRA_VDD_IVA_L_MASK,
+        .cfg_channel_sa_shift = OMAP4430_SA_VDD_IVA_L_SHIFT,
 };
-struct omap_vc_instance_data omap4_vc_core_data = {
+struct omap_vc_channel omap4_vc_core = {
-        .vc_common = &omap4_vc_common,
+        .common = &omap4_vc_common,
+        .smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET,
+        .smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET,
+        .smps_cmdra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET,
+        .cfg_channel_reg = OMAP4_PRM_VC_CFG_CHANNEL_OFFSET,
        .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET,
-        .smps_sa_shift = OMAP4430_SA_VDD_CORE_L_0_6_SHIFT,
        .smps_sa_mask = OMAP4430_SA_VDD_CORE_L_0_6_MASK,
-        .smps_volra_shift = OMAP4430_VOLRA_VDD_CORE_L_SHIFT,
        .smps_volra_mask = OMAP4430_VOLRA_VDD_CORE_L_MASK,
+        .smps_cmdra_mask = OMAP4430_CMDRA_VDD_CORE_L_MASK,
+        .cfg_channel_sa_shift = OMAP4430_SA_VDD_CORE_L_SHIFT,
 };
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index 9ef3789ded4b..64070ac1e761 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -21,10 +21,10 @@
 #include <linux/delay.h>
 #include <linux/io.h>
-#include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/debugfs.h>
 #include <linux/slab.h>
+#include <linux/clk.h>
 #include <plat/common.h>
@@ -36,839 +36,88 @@
 #include "control.h"
 #include "voltage.h"
+#include "powerdomain.h"
 #include "vc.h"
 #include "vp.h"
-#define VOLTAGE_DIR_SIZE        16
+static LIST_HEAD(voltdm_list);
-static struct omap_vdd_info **vdd_info;
-/*
- * Number of scalable voltage domains.
- */
-static int nr_scalable_vdd;
-/* XXX document */
-static s16 prm_mod_offs;
-static s16 prm_irqst_ocp_mod_offs;
-static struct dentry *voltage_dir;
-/* Init function pointers */
-static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
-                                        unsigned long target_volt);
-static u32 omap3_voltage_read_reg(u16 mod, u8 offset)
-{
-        return omap2_prm_read_mod_reg(mod, offset);
-}
-static void omap3_voltage_write_reg(u32 val, u16 mod, u8 offset)
-{
-        omap2_prm_write_mod_reg(val, mod, offset);
-}
-static u32 omap4_voltage_read_reg(u16 mod, u8 offset)
-{
-        return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
-                                        mod, offset);
-}
-static void omap4_voltage_write_reg(u32 val, u16 mod, u8 offset)
-{
-        omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION, mod, offset);
-}
-static int __init _config_common_vdd_data(struct omap_vdd_info *vdd)
-{
-        char *sys_ck_name;
-        struct clk *sys_ck;
-        u32 sys_clk_speed, timeout_val, waittime;
-        /*
-         * XXX Clockfw should handle this, or this should be in a
-         * struct record
-         */
-        if (cpu_is_omap24xx() || cpu_is_omap34xx())
-                sys_ck_name = "sys_ck";
-        else if (cpu_is_omap44xx())
-                sys_ck_name = "sys_clkin_ck";
-        else
-                return -EINVAL;
-        /*
-         * Sys clk rate is require to calculate vp timeout value and
-         * smpswaittimemin and smpswaittimemax.
-         */
-        sys_ck = clk_get(NULL, sys_ck_name);
-        if (IS_ERR(sys_ck)) {
-                pr_warning("%s: Could not get the sys clk to calculate"
-                        "various vdd_%s params\n", __func__, vdd->voltdm.name);
-                return -EINVAL;
-        }
-        sys_clk_speed = clk_get_rate(sys_ck);
-        clk_put(sys_ck);
-        /* Divide to avoid overflow */
-        sys_clk_speed /= 1000;
-        /* Generic voltage parameters */
-        vdd->volt_scale = vp_forceupdate_scale_voltage;
-        vdd->vp_enabled = false;
-        vdd->vp_rt_data.vpconfig_erroroffset =
-                (vdd->pmic_info->vp_erroroffset <<
-                 vdd->vp_data->vp_common->vpconfig_erroroffset_shift);
-        timeout_val = (sys_clk_speed * vdd->pmic_info->vp_timeout_us) / 1000;
-        vdd->vp_rt_data.vlimitto_timeout = timeout_val;
-        vdd->vp_rt_data.vlimitto_vddmin = vdd->pmic_info->vp_vddmin;
-        vdd->vp_rt_data.vlimitto_vddmax = vdd->pmic_info->vp_vddmax;
-        waittime = ((vdd->pmic_info->step_size / vdd->pmic_info->slew_rate) *
-                                sys_clk_speed) / 1000;
-        vdd->vp_rt_data.vstepmin_smpswaittimemin = waittime;
-        vdd->vp_rt_data.vstepmax_smpswaittimemax = waittime;
-        vdd->vp_rt_data.vstepmin_stepmin = vdd->pmic_info->vp_vstepmin;
-        vdd->vp_rt_data.vstepmax_stepmax = vdd->pmic_info->vp_vstepmax;
-        return 0;
-}
-/* Voltage debugfs support */
-static int vp_volt_debug_get(void *data, u64 *val)
-{
-        struct omap_vdd_info *vdd = (struct omap_vdd_info *) data;
-        u8 vsel;
-        if (!vdd) {
-                pr_warning("Wrong paramater passed\n");
-                return -EINVAL;
-        }
-        vsel = vdd->read_reg(prm_mod_offs, vdd->vp_data->voltage);
-        if (!vdd->pmic_info->vsel_to_uv) {
-                pr_warning("PMIC function to convert vsel to voltage"
-                        "in uV not registerd\n");
-                return -EINVAL;
-        }
-        *val = vdd->pmic_info->vsel_to_uv(vsel);
-        return 0;
-}
-static int nom_volt_debug_get(void *data, u64 *val)
-{
-        struct omap_vdd_info *vdd = (struct omap_vdd_info *) data;
-        if (!vdd) {
-                pr_warning("Wrong paramater passed\n");
-                return -EINVAL;
-        }
-        *val = omap_voltage_get_nom_volt(&vdd->voltdm);
-        return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(vp_volt_debug_fops, vp_volt_debug_get, NULL, "%llu\n");
-DEFINE_SIMPLE_ATTRIBUTE(nom_volt_debug_fops, nom_volt_debug_get, NULL,
-                                                                "%llu\n");
-static void vp_latch_vsel(struct omap_vdd_info *vdd)
-{
-        u32 vpconfig;
-        unsigned long uvdc;
-        char vsel;
-        uvdc = omap_voltage_get_nom_volt(&vdd->voltdm);
-        if (!uvdc) {
-                pr_warning("%s: unable to find current voltage for vdd_%s\n",
-                        __func__, vdd->voltdm.name);
-                return;
-        }
-        if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) {
-                pr_warning("%s: PMIC function to convert voltage in uV to"
-                        " vsel not registered\n", __func__);
-                return;
-        }
-        vsel = vdd->pmic_info->uv_to_vsel(uvdc);
-        vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig);
-        vpconfig &= ~(vdd->vp_data->vp_common->vpconfig_initvoltage_mask |
-                        vdd->vp_data->vp_common->vpconfig_initvdd);
-        vpconfig |= vsel << vdd->vp_data->vp_common->vpconfig_initvoltage_shift;
-        vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
-        /* Trigger initVDD value copy to voltage processor */
-        vdd->write_reg((vpconfig | vdd->vp_data->vp_common->vpconfig_initvdd),
-                       prm_mod_offs, vdd->vp_data->vpconfig);
-        /* Clear initVDD copy trigger bit */
-        vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
-}
-/* Generic voltage init functions */
-static void __init vp_init(struct omap_vdd_info *vdd)
-{
-        u32 vp_val;
-        if (!vdd->read_reg || !vdd->write_reg) {
-                pr_err("%s: No read/write API for accessing vdd_%s regs\n",
-                        __func__, vdd->voltdm.name);
-                return;
-        }
-        vp_val = vdd->vp_rt_data.vpconfig_erroroffset |
-                (vdd->vp_rt_data.vpconfig_errorgain <<
-                vdd->vp_data->vp_common->vpconfig_errorgain_shift) |
-                vdd->vp_data->vp_common->vpconfig_timeouten;
-        vdd->write_reg(vp_val, prm_mod_offs, vdd->vp_data->vpconfig);
-        vp_val = ((vdd->vp_rt_data.vstepmin_smpswaittimemin <<
-                vdd->vp_data->vp_common->vstepmin_smpswaittimemin_shift) |
-                (vdd->vp_rt_data.vstepmin_stepmin <<
-                vdd->vp_data->vp_common->vstepmin_stepmin_shift));
-        vdd->write_reg(vp_val, prm_mod_offs, vdd->vp_data->vstepmin);
-        vp_val = ((vdd->vp_rt_data.vstepmax_smpswaittimemax <<
-                vdd->vp_data->vp_common->vstepmax_smpswaittimemax_shift) |
-                (vdd->vp_rt_data.vstepmax_stepmax <<
-                vdd->vp_data->vp_common->vstepmax_stepmax_shift));
-        vdd->write_reg(vp_val, prm_mod_offs, vdd->vp_data->vstepmax);
-        vp_val = ((vdd->vp_rt_data.vlimitto_vddmax <<
-                vdd->vp_data->vp_common->vlimitto_vddmax_shift) |
-                (vdd->vp_rt_data.vlimitto_vddmin <<
-                vdd->vp_data->vp_common->vlimitto_vddmin_shift) |
-                (vdd->vp_rt_data.vlimitto_timeout <<
-                vdd->vp_data->vp_common->vlimitto_timeout_shift));
-        vdd->write_reg(vp_val, prm_mod_offs, vdd->vp_data->vlimitto);
-}
-static void __init vdd_debugfs_init(struct omap_vdd_info *vdd)
-{
-        char *name;
-        name = kzalloc(VOLTAGE_DIR_SIZE, GFP_KERNEL);
-        if (!name) {
-                pr_warning("%s: Unable to allocate memory for debugfs"
-                        " directory name for vdd_%s",
-                        __func__, vdd->voltdm.name);
-                return;
-        }
-        strcpy(name, "vdd_");
-        strcat(name, vdd->voltdm.name);
-        vdd->debug_dir = debugfs_create_dir(name, voltage_dir);
-        kfree(name);
-        if (IS_ERR(vdd->debug_dir)) {
-                pr_warning("%s: Unable to create debugfs directory for"
-                        " vdd_%s\n", __func__, vdd->voltdm.name);
-                vdd->debug_dir = NULL;
-                return;
-        }
-        (void) debugfs_create_x16("vp_errorgain", S_IRUGO, vdd->debug_dir,
-                                &(vdd->vp_rt_data.vpconfig_errorgain));
-        (void) debugfs_create_x16("vp_smpswaittimemin", S_IRUGO,
-                                vdd->debug_dir,
-                                &(vdd->vp_rt_data.vstepmin_smpswaittimemin));
-        (void) debugfs_create_x8("vp_stepmin", S_IRUGO, vdd->debug_dir,
-                                &(vdd->vp_rt_data.vstepmin_stepmin));
-        (void) debugfs_create_x16("vp_smpswaittimemax", S_IRUGO,
-                                vdd->debug_dir,
-                                &(vdd->vp_rt_data.vstepmax_smpswaittimemax));
-        (void) debugfs_create_x8("vp_stepmax", S_IRUGO, vdd->debug_dir,
-                                &(vdd->vp_rt_data.vstepmax_stepmax));
-        (void) debugfs_create_x8("vp_vddmax", S_IRUGO, vdd->debug_dir,
-                                &(vdd->vp_rt_data.vlimitto_vddmax));
-        (void) debugfs_create_x8("vp_vddmin", S_IRUGO, vdd->debug_dir,
-                                &(vdd->vp_rt_data.vlimitto_vddmin));
-        (void) debugfs_create_x16("vp_timeout", S_IRUGO, vdd->debug_dir,
-                                &(vdd->vp_rt_data.vlimitto_timeout));
-        (void) debugfs_create_file("curr_vp_volt", S_IRUGO, vdd->debug_dir,
-                                (void *) vdd, &vp_volt_debug_fops);
-        (void) debugfs_create_file("curr_nominal_volt", S_IRUGO,
-                                vdd->debug_dir, (void *) vdd,
-                                &nom_volt_debug_fops);
-}
-/* Voltage scale and accessory APIs */
-static int _pre_volt_scale(struct omap_vdd_info *vdd,
-                unsigned long target_volt, u8 *target_vsel, u8 *current_vsel)
-{
-        struct omap_volt_data *volt_data;
-        const struct omap_vc_common_data *vc_common;
-        const struct omap_vp_common_data *vp_common;
-        u32 vc_cmdval, vp_errgain_val;
-        vc_common = vdd->vc_data->vc_common;
-        vp_common = vdd->vp_data->vp_common;
-        /* Check if suffiecient pmic info is available for this vdd */
-        if (!vdd->pmic_info) {
-                pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
-                        __func__, vdd->voltdm.name);
-                return -EINVAL;
-        }
-        if (!vdd->pmic_info->uv_to_vsel) {
-                pr_err("%s: PMIC function to convert voltage in uV to"
-                        "vsel not registered. Hence unable to scale voltage"
-                        "for vdd_%s\n", __func__, vdd->voltdm.name);
-                return -ENODATA;
-        }
-        if (!vdd->read_reg || !vdd->write_reg) {
-                pr_err("%s: No read/write API for accessing vdd_%s regs\n",
-                        __func__, vdd->voltdm.name);
-                return -EINVAL;
-        }
-        /* Get volt_data corresponding to target_volt */
-        volt_data = omap_voltage_get_voltdata(&vdd->voltdm, target_volt);
-        if (IS_ERR(volt_data))
-                volt_data = NULL;
-        *target_vsel = vdd->pmic_info->uv_to_vsel(target_volt);
-        *current_vsel = vdd->read_reg(prm_mod_offs, vdd->vp_data->voltage);
-        /* Setting the ON voltage to the new target voltage */
-        vc_cmdval = vdd->read_reg(prm_mod_offs, vdd->vc_data->cmdval_reg);
-        vc_cmdval &= ~vc_common->cmd_on_mask;
-        vc_cmdval |= (*target_vsel << vc_common->cmd_on_shift);
-        vdd->write_reg(vc_cmdval, prm_mod_offs, vdd->vc_data->cmdval_reg);
-        /* Setting vp errorgain based on the voltage */
-        if (volt_data) {
-                vp_errgain_val = vdd->read_reg(prm_mod_offs,
-                                               vdd->vp_data->vpconfig);
-                vdd->vp_rt_data.vpconfig_errorgain = volt_data->vp_errgain;
-                vp_errgain_val &= ~vp_common->vpconfig_errorgain_mask;
-                vp_errgain_val |= vdd->vp_rt_data.vpconfig_errorgain <<
-                        vp_common->vpconfig_errorgain_shift;
-                vdd->write_reg(vp_errgain_val, prm_mod_offs,
-                               vdd->vp_data->vpconfig);
-        }
-        return 0;
-}
-static void _post_volt_scale(struct omap_vdd_info *vdd,
-                unsigned long target_volt, u8 target_vsel, u8 current_vsel)
-{
-        u32 smps_steps = 0, smps_delay = 0;
-        smps_steps = abs(target_vsel - current_vsel);
-        /* SMPS slew rate / step size. 2us added as buffer. */
-        smps_delay = ((smps_steps * vdd->pmic_info->step_size) /
-                        vdd->pmic_info->slew_rate) + 2;
-        udelay(smps_delay);
-        vdd->curr_volt = target_volt;
-}
-/* vc_bypass_scale_voltage - VC bypass method of voltage scaling */
-static int vc_bypass_scale_voltage(struct omap_vdd_info *vdd,
-                unsigned long target_volt)
-{
-        u32 loop_cnt = 0, retries_cnt = 0;
-        u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
-        u8 target_vsel, current_vsel;
-        int ret;
-        ret = _pre_volt_scale(vdd, target_volt, &target_vsel, &current_vsel);
-        if (ret)
-                return ret;
-        vc_valid = vdd->vc_data->vc_common->valid;
-        vc_bypass_val_reg = vdd->vc_data->vc_common->bypass_val_reg;
-        vc_bypass_value = (target_vsel << vdd->vc_data->vc_common->data_shift) |
-                        (vdd->pmic_info->pmic_reg <<
-                        vdd->vc_data->vc_common->regaddr_shift) |
-                        (vdd->pmic_info->i2c_slave_addr <<
-                        vdd->vc_data->vc_common->slaveaddr_shift);
-        vdd->write_reg(vc_bypass_value, prm_mod_offs, vc_bypass_val_reg);
-        vdd->write_reg(vc_bypass_value | vc_valid, prm_mod_offs,
-                       vc_bypass_val_reg);
-        vc_bypass_value = vdd->read_reg(prm_mod_offs, vc_bypass_val_reg);
-        /*
-         * Loop till the bypass command is acknowledged from the SMPS.
-         * NOTE: This is legacy code. The loop count and retry count needs
-         * to be revisited.
-         */
-        while (!(vc_bypass_value & vc_valid)) {
-                loop_cnt++;
-                if (retries_cnt > 10) {
-                        pr_warning("%s: Retry count exceeded\n", __func__);
-                        return -ETIMEDOUT;
-                }
-                if (loop_cnt > 50) {
-                        retries_cnt++;
-                        loop_cnt = 0;
-                        udelay(10);
-                }
-                vc_bypass_value = vdd->read_reg(prm_mod_offs,
-                                                vc_bypass_val_reg);
-        }
-        _post_volt_scale(vdd, target_volt, target_vsel, current_vsel);
-        return 0;
-}
-/* VP force update method of voltage scaling */
-static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
-                unsigned long target_volt)
-{
-        u32 vpconfig;
-        u8 target_vsel, current_vsel, prm_irqst_reg;
-        int ret, timeout = 0;
-        ret = _pre_volt_scale(vdd, target_volt, &target_vsel, &current_vsel);
-        if (ret)
-                return ret;
-        prm_irqst_reg = vdd->vp_data->prm_irqst_data->prm_irqst_reg;
-        /*
-         * Clear all pending TransactionDone interrupt/status. Typical latency
-         * is <3us
-         */
-        while (timeout++ < VP_TRANXDONE_TIMEOUT) {
-                vdd->write_reg(vdd->vp_data->prm_irqst_data->tranxdone_status,
-                               prm_irqst_ocp_mod_offs, prm_irqst_reg);
-                if (!(vdd->read_reg(prm_irqst_ocp_mod_offs, prm_irqst_reg) &
-                      vdd->vp_data->prm_irqst_data->tranxdone_status))
-                        break;
-                udelay(1);
-        }
-        if (timeout >= VP_TRANXDONE_TIMEOUT) {
-                pr_warning("%s: vdd_%s TRANXDONE timeout exceeded."
-                        "Voltage change aborted", __func__, vdd->voltdm.name);
-                return -ETIMEDOUT;
-        }
-        /* Configure for VP-Force Update */
-        vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig);
-        vpconfig &= ~(vdd->vp_data->vp_common->vpconfig_initvdd |
-                        vdd->vp_data->vp_common->vpconfig_forceupdate |
-                        vdd->vp_data->vp_common->vpconfig_initvoltage_mask);
-        vpconfig |= ((target_vsel <<
-                        vdd->vp_data->vp_common->vpconfig_initvoltage_shift));
-        vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
-        /* Trigger initVDD value copy to voltage processor */
-        vpconfig |= vdd->vp_data->vp_common->vpconfig_initvdd;
-        vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
-        /* Force update of voltage */
-        vpconfig |= vdd->vp_data->vp_common->vpconfig_forceupdate;
-        vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
-        /*
-         * Wait for TransactionDone. Typical latency is <200us.
-         * Depends on SMPSWAITTIMEMIN/MAX and voltage change
-         */
-        timeout = 0;
-        omap_test_timeout((vdd->read_reg(prm_irqst_ocp_mod_offs, prm_irqst_reg) &
-                           vdd->vp_data->prm_irqst_data->tranxdone_status),
-                          VP_TRANXDONE_TIMEOUT, timeout);
-        if (timeout >= VP_TRANXDONE_TIMEOUT)
-                pr_err("%s: vdd_%s TRANXDONE timeout exceeded."
-                        "TRANXDONE never got set after the voltage update\n",
-                        __func__, vdd->voltdm.name);
-        _post_volt_scale(vdd, target_volt, target_vsel, current_vsel);
-        /*
-         * Disable TransactionDone interrupt , clear all status, clear
-         * control registers
-         */
-        timeout = 0;
-        while (timeout++ < VP_TRANXDONE_TIMEOUT) {
-                vdd->write_reg(vdd->vp_data->prm_irqst_data->tranxdone_status,
-                               prm_irqst_ocp_mod_offs, prm_irqst_reg);
-                if (!(vdd->read_reg(prm_irqst_ocp_mod_offs, prm_irqst_reg) &
-                      vdd->vp_data->prm_irqst_data->tranxdone_status))
-                        break;
-                udelay(1);
-        }
-        if (timeout >= VP_TRANXDONE_TIMEOUT)
-                pr_warning("%s: vdd_%s TRANXDONE timeout exceeded while trying"
-                        "to clear the TRANXDONE status\n",
-                        __func__, vdd->voltdm.name);
-        vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig);
-        /* Clear initVDD copy trigger bit */
-        vpconfig &= ~vdd->vp_data->vp_common->vpconfig_initvdd;
-        vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
-        /* Clear force bit */
-        vpconfig &= ~vdd->vp_data->vp_common->vpconfig_forceupdate;
-        vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
-        return 0;
-}
-static void __init omap3_vfsm_init(struct omap_vdd_info *vdd)
-{
-        /*
-         * Voltage Manager FSM parameters init
-         * XXX This data should be passed in from the board file
-         */
-        vdd->write_reg(OMAP3_CLKSETUP, prm_mod_offs, OMAP3_PRM_CLKSETUP_OFFSET);
-        vdd->write_reg(OMAP3_VOLTOFFSET, prm_mod_offs,
-                       OMAP3_PRM_VOLTOFFSET_OFFSET);
-        vdd->write_reg(OMAP3_VOLTSETUP2, prm_mod_offs,
-                       OMAP3_PRM_VOLTSETUP2_OFFSET);
-}
-static void __init omap3_vc_init(struct omap_vdd_info *vdd)
-{
-        static bool is_initialized;
-        u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
-        u32 vc_val;
-        if (is_initialized)
-                return;
-        /* Set up the on, inactive, retention and off voltage */
-        on_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->on_volt);
-        onlp_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->onlp_volt);
-        ret_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->ret_volt);
-        off_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->off_volt);
-        vc_val  = ((on_vsel << vdd->vc_data->vc_common->cmd_on_shift) |
-                (onlp_vsel << vdd->vc_data->vc_common->cmd_onlp_shift) |
-                (ret_vsel << vdd->vc_data->vc_common->cmd_ret_shift) |
-                (off_vsel << vdd->vc_data->vc_common->cmd_off_shift));
-        vdd->write_reg(vc_val, prm_mod_offs, vdd->vc_data->cmdval_reg);
-        /*
-         * Generic VC parameters init
-         * XXX This data should be abstracted out
-         */
-        vdd->write_reg(OMAP3430_CMD1_MASK | OMAP3430_RAV1_MASK, prm_mod_offs,
-                        OMAP3_PRM_VC_CH_CONF_OFFSET);
-        vdd->write_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK, prm_mod_offs,
-                        OMAP3_PRM_VC_I2C_CFG_OFFSET);
-        omap3_vfsm_init(vdd);
-        is_initialized = true;
-}
-/* OMAP4 specific voltage init functions */
-static void __init omap4_vc_init(struct omap_vdd_info *vdd)
-{
-        static bool is_initialized;
-        u32 vc_val;
-        if (is_initialized)
-                return;
-        /* TODO: Configure setup times and CMD_VAL values*/
-        /*
-         * Generic VC parameters init
-         * XXX This data should be abstracted out
-         */
-        vc_val = (OMAP4430_RAV_VDD_MPU_L_MASK | OMAP4430_CMD_VDD_MPU_L_MASK |
-                  OMAP4430_RAV_VDD_IVA_L_MASK | OMAP4430_CMD_VDD_IVA_L_MASK |
-                  OMAP4430_RAV_VDD_CORE_L_MASK | OMAP4430_CMD_VDD_CORE_L_MASK);
-        vdd->write_reg(vc_val, prm_mod_offs, OMAP4_PRM_VC_CFG_CHANNEL_OFFSET);
-        /* XXX These are magic numbers and do not belong! */
-        vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
-        vdd->write_reg(vc_val, prm_mod_offs, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
-        is_initialized = true;
-}
-static void __init omap_vc_init(struct omap_vdd_info *vdd)
-{
-        u32 vc_val;
-        if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) {
-                pr_err("%s: PMIC info requried to configure vc for"
-                        "vdd_%s not populated.Hence cannot initialize vc\n",
-                        __func__, vdd->voltdm.name);
-                return;
-        }
-        if (!vdd->read_reg || !vdd->write_reg) {
-                pr_err("%s: No read/write API for accessing vdd_%s regs\n",
-                        __func__, vdd->voltdm.name);
-                return;
-        }
-        /* Set up the SMPS_SA(i2c slave address in VC */
-        vc_val = vdd->read_reg(prm_mod_offs,
-                               vdd->vc_data->vc_common->smps_sa_reg);
-        vc_val &= ~vdd->vc_data->smps_sa_mask;
-        vc_val |= vdd->pmic_info->i2c_slave_addr << vdd->vc_data->smps_sa_shift;
-        vdd->write_reg(vc_val, prm_mod_offs,
-                       vdd->vc_data->vc_common->smps_sa_reg);
-        /* Setup the VOLRA(pmic reg addr) in VC */
-        vc_val = vdd->read_reg(prm_mod_offs,
-                               vdd->vc_data->vc_common->smps_volra_reg);
-        vc_val &= ~vdd->vc_data->smps_volra_mask;
-        vc_val |= vdd->pmic_info->pmic_reg << vdd->vc_data->smps_volra_shift;
-        vdd->write_reg(vc_val, prm_mod_offs,
-                       vdd->vc_data->vc_common->smps_volra_reg);
-        /* Configure the setup times */
-        vc_val = vdd->read_reg(prm_mod_offs, vdd->vfsm->voltsetup_reg);
-        vc_val &= ~vdd->vfsm->voltsetup_mask;
-        vc_val |= vdd->pmic_info->volt_setup_time <<
-                        vdd->vfsm->voltsetup_shift;
-        vdd->write_reg(vc_val, prm_mod_offs, vdd->vfsm->voltsetup_reg);
-        if (cpu_is_omap34xx())
-                omap3_vc_init(vdd);
-        else if (cpu_is_omap44xx())
-                omap4_vc_init(vdd);
-}
-static int __init omap_vdd_data_configure(struct omap_vdd_info *vdd)
-{
-        int ret = -EINVAL;
-        if (!vdd->pmic_info) {
-                pr_err("%s: PMIC info requried to configure vdd_%s not"
-                        "populated.Hence cannot initialize vdd_%s\n",
-                        __func__, vdd->voltdm.name, vdd->voltdm.name);
-                goto ovdc_out;
-        }
-        if (IS_ERR_VALUE(_config_common_vdd_data(vdd)))
-                goto ovdc_out;
-        if (cpu_is_omap34xx()) {
-                vdd->read_reg = omap3_voltage_read_reg;
-                vdd->write_reg = omap3_voltage_write_reg;
-                ret = 0;
-        } else if (cpu_is_omap44xx()) {
-                vdd->read_reg = omap4_voltage_read_reg;
-                vdd->write_reg = omap4_voltage_write_reg;
-                ret = 0;
-        }
-ovdc_out:
-        return ret;
-}
 /* Public functions */
 /**
- * omap_voltage_get_nom_volt() - Gets the current non-auto-compensated voltage
+ * voltdm_get_voltage() - Gets the current non-auto-compensated voltage
- * @voltdm:     pointer to the VDD for which current voltage info is needed
+ * @voltdm:     pointer to the voltdm for which current voltage info is needed
 *
- * API to get the current non-auto-compensated voltage for a VDD.
+ * API to get the current non-auto-compensated voltage for a voltage domain.
- * Returns 0 in case of error else returns the current voltage for the VDD.
+ * Returns 0 in case of error else returns the current voltage.
 */
-unsigned long omap_voltage_get_nom_volt(struct voltagedomain *voltdm)
+unsigned long voltdm_get_voltage(struct voltagedomain *voltdm)
 {
-        struct omap_vdd_info *vdd;
        if (!voltdm || IS_ERR(voltdm)) {
                pr_warning("%s: VDD specified does not exist!\n", __func__);
                return 0;
        }
-        vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
+        return voltdm->nominal_volt;
-        return vdd->curr_volt;
 }
 /**
- * omap_vp_get_curr_volt() - API to get the current vp voltage.
+ * voltdm_scale() - API to scale voltage of a particular voltage domain.
- * @voltdm:     pointer to the VDD.
+ * @voltdm: pointer to the voltage domain which is to be scaled.
- *
+ * @target_volt: The target voltage of the voltage domain
- * This API returns the current voltage for the specified voltage processor
- */
-unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm)
-{
-        struct omap_vdd_info *vdd;
-        u8 curr_vsel;
-        if (!voltdm || IS_ERR(voltdm)) {
-                pr_warning("%s: VDD specified does not exist!\n", __func__);
-                return 0;
-        }
-        vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
-        if (!vdd->read_reg) {
-                pr_err("%s: No read API for reading vdd_%s regs\n",
-                        __func__, voltdm->name);
-                return 0;
-        }
-        curr_vsel = vdd->read_reg(prm_mod_offs, vdd->vp_data->voltage);
-        if (!vdd->pmic_info || !vdd->pmic_info->vsel_to_uv) {
-                pr_warning("%s: PMIC function to convert vsel to voltage"
-                        "in uV not registerd\n", __func__);
-                return 0;
-        }
-        return vdd->pmic_info->vsel_to_uv(curr_vsel);
-}
-/**
- * omap_vp_enable() - API to enable a particular VP
- * @voltdm:     pointer to the VDD whose VP is to be enabled.
- *
- * This API enables a particular voltage processor. Needed by the smartreflex
- * class drivers.
- */
-void omap_vp_enable(struct voltagedomain *voltdm)
-{
-        struct omap_vdd_info *vdd;
-        u32 vpconfig;
-        if (!voltdm || IS_ERR(voltdm)) {
-                pr_warning("%s: VDD specified does not exist!\n", __func__);
-                return;
-        }
-        vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
-        if (!vdd->read_reg || !vdd->write_reg) {
-                pr_err("%s: No read/write API for accessing vdd_%s regs\n",
-                        __func__, voltdm->name);
-                return;
-        }
-        /* If VP is already enabled, do nothing. Return */
-        if (vdd->vp_enabled)
-                return;
-        vp_latch_vsel(vdd);
-        /* Enable VP */
-        vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig);
-        vpconfig |= vdd->vp_data->vp_common->vpconfig_vpenable;
-        vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
-        vdd->vp_enabled = true;
-}
-/**
- * omap_vp_disable() - API to disable a particular VP
- * @voltdm:     pointer to the VDD whose VP is to be disabled.
- *
- * This API disables a particular voltage processor. Needed by the smartreflex
- * class drivers.
- */
-void omap_vp_disable(struct voltagedomain *voltdm)
-{
-        struct omap_vdd_info *vdd;
-        u32 vpconfig;
-        int timeout;
-        if (!voltdm || IS_ERR(voltdm)) {
-                pr_warning("%s: VDD specified does not exist!\n", __func__);
-                return;
-        }
-        vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
-        if (!vdd->read_reg || !vdd->write_reg) {
-                pr_err("%s: No read/write API for accessing vdd_%s regs\n",
-                        __func__, voltdm->name);
-                return;
-        }
-        /* If VP is already disabled, do nothing. Return */
-        if (!vdd->vp_enabled) {
-                pr_warning("%s: Trying to disable VP for vdd_%s when"
-                        "it is already disabled\n", __func__, voltdm->name);
-                return;
-        }
-        /* Disable VP */
-        vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig);
-        vpconfig &= ~vdd->vp_data->vp_common->vpconfig_vpenable;
-        vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
-        /*
-         * Wait for VP idle Typical latency is <2us. Maximum latency is ~100us
-         */
-        omap_test_timeout((vdd->read_reg(prm_mod_offs, vdd->vp_data->vstatus)),
-                                VP_IDLE_TIMEOUT, timeout);
-        if (timeout >= VP_IDLE_TIMEOUT)
-                pr_warning("%s: vdd_%s idle timedout\n",
-                        __func__, voltdm->name);
-        vdd->vp_enabled = false;
-        return;
-}
-/**
- * omap_voltage_scale_vdd() - API to scale voltage of a particular
- *                              voltage domain.
- * @voltdm:     pointer to the VDD which is to be scaled.
- * @target_volt:        The target voltage of the voltage domain
 *
 * This API should be called by the kernel to do the voltage scaling
- * for a particular voltage domain during dvfs or any other situation.
+ * for a particular voltage domain during DVFS.
 */
-int omap_voltage_scale_vdd(struct voltagedomain *voltdm,
+int voltdm_scale(struct voltagedomain *voltdm,
-                unsigned long target_volt)
+                 unsigned long target_volt)
 {
-        struct omap_vdd_info *vdd;
+        int ret;
        if (!voltdm || IS_ERR(voltdm)) {
                pr_warning("%s: VDD specified does not exist!\n", __func__);
                return -EINVAL;
        }
-        vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
+        if (!voltdm->scale) {
-        if (!vdd->volt_scale) {
                pr_err("%s: No voltage scale API registered for vdd_%s\n",
                        __func__, voltdm->name);
                return -ENODATA;
        }
-        return vdd->volt_scale(vdd, target_volt);
+        ret = voltdm->scale(voltdm, target_volt);
+        if (!ret)
+                voltdm->nominal_volt = target_volt;
+        return ret;
 }
 /**
- * omap_voltage_reset() - Resets the voltage of a particular voltage domain
+ * voltdm_reset() - Resets the voltage of a particular voltage domain
- *                      to that of the current OPP.
+ *                  to that of the current OPP.
- * @voltdm:     pointer to the VDD whose voltage is to be reset.
+ * @voltdm: pointer to the voltage domain whose voltage is to be reset.
 *
 * This API finds out the correct voltage the voltage domain is supposed
 * to be at and resets the voltage to that level. Should be used especially
 * while disabling any voltage compensation modules.
 */
-void omap_voltage_reset(struct voltagedomain *voltdm)
+void voltdm_reset(struct voltagedomain *voltdm)
 {
-        unsigned long target_uvdc;
+        unsigned long target_volt;
        if (!voltdm || IS_ERR(voltdm)) {
                pr_warning("%s: VDD specified does not exist!\n", __func__);
                return;
        }
-        target_uvdc = omap_voltage_get_nom_volt(voltdm);
+        target_volt = voltdm_get_voltage(voltdm);
-        if (!target_uvdc) {
+        if (!target_volt) {
                pr_err("%s: unable to find current voltage for vdd_%s\n",
                        __func__, voltdm->name);
                return;
        }
-        omap_voltage_scale_vdd(voltdm, target_uvdc);
+        voltdm_scale(voltdm, target_volt);
 }
 /**
@@ -884,18 +133,14 @@ void omap_voltage_reset(struct voltagedomain *voltdm)
 *
 */
 void omap_voltage_get_volttable(struct voltagedomain *voltdm,
-                struct omap_volt_data **volt_data)
+                                struct omap_volt_data **volt_data)
 {
-        struct omap_vdd_info *vdd;
        if (!voltdm || IS_ERR(voltdm)) {
                pr_warning("%s: VDD specified does not exist!\n", __func__);
                return;
        }
-        vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
+        *volt_data = voltdm->volt_data;
-        *volt_data = vdd->volt_data;
 }
 /**
@@ -914,9 +159,8 @@ void omap_voltage_get_volttable(struct voltagedomain *voltdm,
 * domain or if there is no matching entry.
 */
 struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
-                unsigned long volt)
+                                                 unsigned long volt)
 {
-        struct omap_vdd_info *vdd;
        int i;
        if (!voltdm || IS_ERR(voltdm)) {
@@ -924,17 +168,15 @@ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
                return ERR_PTR(-EINVAL);
        }
-        vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
+        if (!voltdm->volt_data) {
-        if (!vdd->volt_data) {
                pr_warning("%s: voltage table does not exist for vdd_%s\n",
                        __func__, voltdm->name);
                return ERR_PTR(-ENODATA);
        }
-        for (i = 0; vdd->volt_data[i].volt_nominal != 0; i++) {
+        for (i = 0; voltdm->volt_data[i].volt_nominal != 0; i++) {
-                if (vdd->volt_data[i].volt_nominal == volt)
+                if (voltdm->volt_data[i].volt_nominal == volt)
-                        return &vdd->volt_data[i];
+                        return &voltdm->volt_data[i];
        }
        pr_notice("%s: Unable to match the current voltage with the voltage"
@@ -947,54 +189,25 @@ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
 * omap_voltage_register_pmic() - API to register PMIC specific data
 * @voltdm:     pointer to the VDD for which the PMIC specific data is
 *              to be registered
- * @pmic_info:  the structure containing pmic info
+ * @pmic:       the structure containing pmic info
 *
 * This API is to be called by the SOC/PMIC file to specify the
- * pmic specific info as present in omap_volt_pmic_info structure.
+ * pmic specific info as present in omap_voltdm_pmic structure.
 */
 int omap_voltage_register_pmic(struct voltagedomain *voltdm,
-                struct omap_volt_pmic_info *pmic_info)
+                               struct omap_voltdm_pmic *pmic)
 {
-        struct omap_vdd_info *vdd;
        if (!voltdm || IS_ERR(voltdm)) {
                pr_warning("%s: VDD specified does not exist!\n", __func__);
                return -EINVAL;
        }
-        vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
+        voltdm->pmic = pmic;
-        vdd->pmic_info = pmic_info;
        return 0;
 }
 /**
- * omap_voltage_get_dbgdir() - API to get pointer to the debugfs directory
- *                              corresponding to a voltage domain.
- *
- * @voltdm:     pointer to the VDD whose debug directory is required.
- *
- * This API returns pointer to the debugfs directory corresponding
- * to the voltage domain. Should be used by drivers requiring to
- * add any debug entry for a particular voltage domain. Returns NULL
- * in case of error.
- */
-struct dentry *omap_voltage_get_dbgdir(struct voltagedomain *voltdm)
-{
-        struct omap_vdd_info *vdd;
-        if (!voltdm || IS_ERR(voltdm)) {
-                pr_warning("%s: VDD specified does not exist!\n", __func__);
-                return NULL;
-        }
-        vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
-        return vdd->debug_dir;
-}
-/**
 * omap_change_voltscale_method() - API to change the voltage scaling method.
 * @voltdm:     pointer to the VDD whose voltage scaling method
 *              has to be changed.
@@ -1005,23 +218,19 @@ struct dentry *omap_voltage_get_dbgdir(struct voltagedomain *voltdm)
 * defined in voltage.h
 */
 void omap_change_voltscale_method(struct voltagedomain *voltdm,
-                int voltscale_method)
+                                  int voltscale_method)
 {
-        struct omap_vdd_info *vdd;
        if (!voltdm || IS_ERR(voltdm)) {
                pr_warning("%s: VDD specified does not exist!\n", __func__);
                return;
        }
-        vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
        switch (voltscale_method) {
        case VOLTSCALE_VPFORCEUPDATE:
-                vdd->volt_scale = vp_forceupdate_scale_voltage;
+                voltdm->scale = omap_vp_forceupdate_scale;
                return;
        case VOLTSCALE_VCBYPASS:
-                vdd->volt_scale = vc_bypass_scale_voltage;
+                voltdm->scale = omap_vc_bypass_scale;
                return;
        default:
                pr_warning("%s: Trying to change the method of voltage scaling"
@@ -1030,77 +239,192 @@ void omap_change_voltscale_method(struct voltagedomain *voltdm,
 }
 /**
- * omap_voltage_domain_lookup() - API to get the voltage domain pointer
+ * omap_voltage_late_init() - Init the various voltage parameters
- * @name:       Name of the voltage domain
 *
- * This API looks up in the global vdd_info struct for the
+ * This API is to be called in the later stages of the
- * existence of voltage domain <name>. If it exists, the API returns
+ * system boot to init the voltage controller and
- * a pointer to the voltage domain structure corresponding to the
+ * voltage processors.
- * VDD<name>. Else retuns error pointer.
 */
-struct voltagedomain *omap_voltage_domain_lookup(char *name)
+int __init omap_voltage_late_init(void)
 {
-        int i;
+        struct voltagedomain *voltdm;
-        if (!vdd_info) {
+        if (list_empty(&voltdm_list)) {
-                pr_err("%s: Voltage driver init not yet happened.Faulting!\n",
+                pr_err("%s: Voltage driver support not added\n",
                        __func__);
-                return ERR_PTR(-EINVAL);
+                return -EINVAL;
        }
-        if (!name) {
+        list_for_each_entry(voltdm, &voltdm_list, node) {
-                pr_err("%s: No name to get the votage domain!\n", __func__);
+                struct clk *sys_ck;
-                return ERR_PTR(-EINVAL);
+                if (!voltdm->scalable)
+                        continue;
+                sys_ck = clk_get(NULL, voltdm->sys_clk.name);
+                if (IS_ERR(sys_ck)) {
+                        pr_warning("%s: Could not get sys clk.\n", __func__);
+                        return -EINVAL;
+                }
+                voltdm->sys_clk.rate = clk_get_rate(sys_ck);
+                WARN_ON(!voltdm->sys_clk.rate);
+                clk_put(sys_ck);
+                if (voltdm->vc) {
+                        voltdm->scale = omap_vc_bypass_scale;
+                        omap_vc_init_channel(voltdm);
+                }
+                if (voltdm->vp) {
+                        voltdm->scale = omap_vp_forceupdate_scale;
+                        omap_vp_init(voltdm);
+                }
        }
-        for (i = 0; i < nr_scalable_vdd; i++) {
+        return 0;
-                if (!(strcmp(name, vdd_info[i]->voltdm.name)))
+}
-                        return &vdd_info[i]->voltdm;
+static struct voltagedomain *_voltdm_lookup(const char *name)
+{
+        struct voltagedomain *voltdm, *temp_voltdm;
+        voltdm = NULL;
+        list_for_each_entry(temp_voltdm, &voltdm_list, node) {
+                if (!strcmp(name, temp_voltdm->name)) {
+                        voltdm = temp_voltdm;
+                        break;
+                }
        }
-        return ERR_PTR(-EINVAL);
+        return voltdm;
 }
 /**
- * omap_voltage_late_init() - Init the various voltage parameters
+ * voltdm_add_pwrdm - add a powerdomain to a voltagedomain
+ * @voltdm: struct voltagedomain * to add the powerdomain to
+ * @pwrdm: struct powerdomain * to associate with a voltagedomain
 *
- * This API is to be called in the later stages of the
+ * Associate the powerdomain @pwrdm with a voltagedomain @voltdm.  This
- * system boot to init the voltage controller and
+ * enables the use of voltdm_for_each_pwrdm().  Returns -EINVAL if
- * voltage processors.
+ * presented with invalid pointers; -ENOMEM if memory could not be allocated;
+ * or 0 upon success.
 */
-int __init omap_voltage_late_init(void)
+int voltdm_add_pwrdm(struct voltagedomain *voltdm, struct powerdomain *pwrdm)
 {
-        int i;
+        if (!voltdm || !pwrdm)
+                return -EINVAL;
-        if (!vdd_info) {
+        pr_debug("voltagedomain: associating powerdomain %s with voltagedomain "
-                pr_err("%s: Voltage driver support not added\n",
+                 "%s\n", pwrdm->name, voltdm->name);
-                        __func__);
+        list_add(&pwrdm->voltdm_node, &voltdm->pwrdm_list);
+        return 0;
+}
+/**
+ * voltdm_for_each_pwrdm - call function for each pwrdm in a voltdm
+ * @voltdm: struct voltagedomain * to iterate over
+ * @fn: callback function *
+ *
+ * Call the supplied function @fn for each powerdomain in the
+ * voltagedomain @voltdm.  Returns -EINVAL if presented with invalid
+ * pointers; or passes along the last return value of the callback
+ * function, which should be 0 for success or anything else to
+ * indicate failure.
+ */
+int voltdm_for_each_pwrdm(struct voltagedomain *voltdm,
+                          int (*fn)(struct voltagedomain *voltdm,
+                                    struct powerdomain *pwrdm))
+{
+        struct powerdomain *pwrdm;
+        int ret = 0;
+        if (!fn)
                return -EINVAL;
-        }
-        voltage_dir = debugfs_create_dir("voltage", NULL);
+        list_for_each_entry(pwrdm, &voltdm->pwrdm_list, voltdm_node)
-        if (IS_ERR(voltage_dir))
+                ret = (*fn)(voltdm, pwrdm);
-                pr_err("%s: Unable to create voltage debugfs main dir\n",
-                        __func__);
+        return ret;
-        for (i = 0; i < nr_scalable_vdd; i++) {
+}
-                if (omap_vdd_data_configure(vdd_info[i]))
-                        continue;
+/**
-                omap_vc_init(vdd_info[i]);
+ * voltdm_for_each - call function on each registered voltagedomain
-                vp_init(vdd_info[i]);
+ * @fn: callback function *
-                vdd_debugfs_init(vdd_info[i]);
+ *
+ * Call the supplied function @fn for each registered voltagedomain.
+ * The callback function @fn can return anything but 0 to bail out
+ * early from the iterator.  Returns the last return value of the
+ * callback function, which should be 0 for success or anything else
+ * to indicate failure; or -EINVAL if the function pointer is null.
+ */
+int voltdm_for_each(int (*fn)(struct voltagedomain *voltdm, void *user),
+                    void *user)
+{
+        struct voltagedomain *temp_voltdm;
+        int ret = 0;
+        if (!fn)
+                return -EINVAL;
+        list_for_each_entry(temp_voltdm, &voltdm_list, node) {
+                ret = (*fn)(temp_voltdm, user);
+                if (ret)
+                        break;
        }
-        return 0;
+        return ret;
 }
-/* XXX document */
+static int _voltdm_register(struct voltagedomain *voltdm)
-int __init omap_voltage_early_init(s16 prm_mod, s16 prm_irqst_ocp_mod,
-                                   struct omap_vdd_info *omap_vdd_array[],
-                                   u8 omap_vdd_count)
 {
-        prm_mod_offs = prm_mod;
+        if (!voltdm || !voltdm->name)
-        prm_irqst_ocp_mod_offs = prm_irqst_ocp_mod;
+                return -EINVAL;
-        vdd_info = omap_vdd_array;
-        nr_scalable_vdd = omap_vdd_count;
+        INIT_LIST_HEAD(&voltdm->pwrdm_list);
+        list_add(&voltdm->node, &voltdm_list);
+        pr_debug("voltagedomain: registered %s\n", voltdm->name);
        return 0;
 }
+/**
+ * voltdm_lookup - look up a voltagedomain by name, return a pointer
+ * @name: name of voltagedomain
+ *
+ * Find a registered voltagedomain by its name @name.  Returns a pointer
+ * to the struct voltagedomain if found, or NULL otherwise.
+ */
+struct voltagedomain *voltdm_lookup(const char *name)
+{
+        struct voltagedomain *voltdm ;
+        if (!name)
+                return NULL;
+        voltdm = _voltdm_lookup(name);
+        return voltdm;
+}
+/**
+ * voltdm_init - set up the voltagedomain layer
+ * @voltdm_list: array of struct voltagedomain pointers to register
+ *
+ * Loop through the array of voltagedomains @voltdm_list, registering all
+ * that are available on the current CPU. If voltdm_list is supplied
+ * and not null, all of the referenced voltagedomains will be
+ * registered.  No return value.
+ */
+void voltdm_init(struct voltagedomain **voltdms)
+{
+        struct voltagedomain **v;
+        if (voltdms) {
+                for (v = voltdms; *v; v++)
+                        _voltdm_register(*v);
+        }
+}
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index e9f5408244e0..16a1b092cf36 100644
--- a/arch/arm/mach-omap2/voltage.h
+++ b/arch/arm/mach-omap2/voltage.h
@@ -19,6 +19,8 @@
 #include "vc.h"
 #include "vp.h"
+struct powerdomain;
 /* XXX document */
 #define VOLTSCALE_VPFORCEUPDATE         1
 #define VOLTSCALE_VCBYPASS              2
@@ -32,29 +34,60 @@
 #define OMAP3_VOLTSETUP2        0xff
 /**
- * struct omap_vfsm_instance_data - per-voltage manager FSM register/bitfield
+ * struct omap_vfsm_instance - per-voltage manager FSM register/bitfield
 * data
 * @voltsetup_mask: SETUP_TIME* bitmask in the PRM_VOLTSETUP* register
 * @voltsetup_reg: register offset of PRM_VOLTSETUP from PRM base
- * @voltsetup_shift: SETUP_TIME* field shift in the PRM_VOLTSETUP* register
 *
 * XXX What about VOLTOFFSET/VOLTCTRL?
- * XXX It is not necessary to have both a _mask and a _shift for the same
- *     bitfield - remove one!
 */
-struct omap_vfsm_instance_data {
+struct omap_vfsm_instance {
        u32 voltsetup_mask;
        u8 voltsetup_reg;
-        u8 voltsetup_shift;
 };
 /**
 * struct voltagedomain - omap voltage domain global structure.
- * @name:       Name of the voltage domain which can be used as a unique
+ * @name: Name of the voltage domain which can be used as a unique identifier.
- *              identifier.
+ * @scalable: Whether or not this voltage domain is scalable
+ * @node: list_head linking all voltage domains
+ * @pwrdm_list: list_head linking all powerdomains in this voltagedomain
+ * @vc: pointer to VC channel associated with this voltagedomain
+ * @vp: pointer to VP associated with this voltagedomain
+ * @read: read a VC/VP register
+ * @write: write a VC/VP register
+ * @read: read-modify-write a VC/VP register
+ * @sys_clk: system clock name/frequency, used for various timing calculations
+ * @scale: function used to scale the voltage of the voltagedomain
+ * @nominal_volt: current nominal voltage for this voltage domain
+ * @volt_data: voltage table having the distinct voltages supported
+ *             by the domain and other associated per voltage data.
 */
 struct voltagedomain {
        char *name;
+        bool scalable;
+        struct list_head node;
+        struct list_head pwrdm_list;
+        struct omap_vc_channel *vc;
+        const struct omap_vfsm_instance *vfsm;
+        struct omap_vp_instance *vp;
+        struct omap_voltdm_pmic *pmic;
+        /* VC/VP register access functions: SoC specific */
+        u32 (*read) (u8 offset);
+        void (*write) (u32 val, u8 offset);
+        u32 (*rmw)(u32 mask, u32 bits, u8 offset);
+        union {
+                const char *name;
+                u32 rate;
+        } sys_clk;
+        int (*scale) (struct voltagedomain *voltdm,
+                      unsigned long target_volt);
+        u32 nominal_volt;
+        struct omap_volt_data *volt_data;
 };
 /**
@@ -77,13 +110,18 @@ struct omap_volt_data {
 };
 /**
- * struct omap_volt_pmic_info - PMIC specific data required by voltage driver.
+ * struct omap_voltdm_pmic - PMIC specific data required by voltage driver.
 * @slew_rate:  PMIC slew rate (in uv/us)
 * @step_size:  PMIC voltage step size (in uv)
+ * @i2c_slave_addr: I2C slave address of PMIC
+ * @volt_reg_addr: voltage configuration register address
+ * @cmd_reg_addr: command (on, on-LP, ret, off) configuration register address
+ * @i2c_high_speed: whether VC uses I2C high-speed mode to PMIC
+ * @i2c_mcode: master code value for I2C high-speed preamble transmission
 * @vsel_to_uv: PMIC API to convert vsel value to actual voltage in uV.
 * @uv_to_vsel: PMIC API to convert voltage in uV to vsel value.
 */
-struct omap_volt_pmic_info {
+struct omap_voltdm_pmic {
        int slew_rate;
        int step_size;
        u32 on_volt;
@@ -91,94 +129,44 @@ struct omap_volt_pmic_info {
        u32 ret_volt;
        u32 off_volt;
        u16 volt_setup_time;
+        u16 i2c_slave_addr;
+        u16 volt_reg_addr;
+        u16 cmd_reg_addr;
        u8 vp_erroroffset;
        u8 vp_vstepmin;
        u8 vp_vstepmax;
        u8 vp_vddmin;
        u8 vp_vddmax;
        u8 vp_timeout_us;
-        u8 i2c_slave_addr;
+        bool i2c_high_speed;
-        u8 pmic_reg;
+        u8 i2c_mcode;
        unsigned long (*vsel_to_uv) (const u8 vsel);
        u8 (*uv_to_vsel) (unsigned long uV);
 };
-/**
- * omap_vdd_info - Per Voltage Domain info
- *
- * @volt_data           : voltage table having the distinct voltages supported
- *                        by the domain and other associated per voltage data.
- * @pmic_info           : pmic specific parameters which should be populted by
- *                        the pmic drivers.
- * @vp_data             : the register values, shifts, masks for various
- *                        vp registers
- * @vp_rt_data          : VP data derived at runtime, not predefined
- * @vc_data             : structure containing various various vc registers,
- *                        shifts, masks etc.
- * @vfsm                : voltage manager FSM data
- * @voltdm              : pointer to the voltage domain structure
- * @debug_dir           : debug directory for this voltage domain.
- * @curr_volt           : current voltage for this vdd.
- * @vp_enabled          : flag to keep track of whether vp is enabled or not
- * @volt_scale          : API to scale the voltage of the vdd.
- */
-struct omap_vdd_info {
-        struct omap_volt_data *volt_data;
-        struct omap_volt_pmic_info *pmic_info;
-        struct omap_vp_instance_data *vp_data;
-        struct omap_vp_runtime_data vp_rt_data;
-        struct omap_vc_instance_data *vc_data;
-        const struct omap_vfsm_instance_data *vfsm;
-        struct voltagedomain voltdm;
-        struct dentry *debug_dir;
-        u32 curr_volt;
-        bool vp_enabled;
-        u32 (*read_reg) (u16 mod, u8 offset);
-        void (*write_reg) (u32 val, u16 mod, u8 offset);
-        int (*volt_scale) (struct omap_vdd_info *vdd,
-                unsigned long target_volt);
-};
-unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm);
-void omap_vp_enable(struct voltagedomain *voltdm);
-void omap_vp_disable(struct voltagedomain *voltdm);
-int omap_voltage_scale_vdd(struct voltagedomain *voltdm,
-                unsigned long target_volt);
-void omap_voltage_reset(struct voltagedomain *voltdm);
 void omap_voltage_get_volttable(struct voltagedomain *voltdm,
                struct omap_volt_data **volt_data);
 struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
                unsigned long volt);
-unsigned long omap_voltage_get_nom_volt(struct voltagedomain *voltdm);
-struct dentry *omap_voltage_get_dbgdir(struct voltagedomain *voltdm);
-int __init omap_voltage_early_init(s16 prm_mod, s16 prm_irqst_mod,
-                                   struct omap_vdd_info *omap_vdd_array[],
-                                   u8 omap_vdd_count);
-#ifdef CONFIG_PM
 int omap_voltage_register_pmic(struct voltagedomain *voltdm,
-                struct omap_volt_pmic_info *pmic_info);
+                               struct omap_voltdm_pmic *pmic);
 void omap_change_voltscale_method(struct voltagedomain *voltdm,
                int voltscale_method);
-/* API to get the voltagedomain pointer */
-struct voltagedomain *omap_voltage_domain_lookup(char *name);
 int omap_voltage_late_init(void);
-#else
-static inline int omap_voltage_register_pmic(struct voltagedomain *voltdm,
-                struct omap_volt_pmic_info *pmic_info)
-{
-        return -EINVAL;
-}
-static inline  void omap_change_voltscale_method(struct voltagedomain *voltdm,
-                int voltscale_method) {}
-static inline int omap_voltage_late_init(void)
-{
-        return -EINVAL;
-}
-static inline struct voltagedomain *omap_voltage_domain_lookup(char *name)
-{
-        return ERR_PTR(-EINVAL);
-}
-#endif
+extern void omap2xxx_voltagedomains_init(void);
+extern void omap3xxx_voltagedomains_init(void);
+extern void omap44xx_voltagedomains_init(void);
+struct voltagedomain *voltdm_lookup(const char *name);
+void voltdm_init(struct voltagedomain **voltdm_list);
+int voltdm_add_pwrdm(struct voltagedomain *voltdm, struct powerdomain *pwrdm);
+int voltdm_for_each(int (*fn)(struct voltagedomain *voltdm, void *user),
+                    void *user);
+int voltdm_for_each_pwrdm(struct voltagedomain *voltdm,
+                          int (*fn)(struct voltagedomain *voltdm,
+                                    struct powerdomain *pwrdm));
+int voltdm_scale(struct voltagedomain *voltdm, unsigned long target_volt);
+void voltdm_reset(struct voltagedomain *voltdm);
+unsigned long voltdm_get_voltage(struct voltagedomain *voltdm);
 #endif
diff --git a/arch/arm/mach-omap2/voltagedomains2xxx_data.c b/arch/arm/mach-omap2/voltagedomains2xxx_data.c
new file mode 100644
index 000000000000..7a41349981e5
--- /dev/null
+++ b/arch/arm/mach-omap2/voltagedomains2xxx_data.c
@@ -0,0 +1,32 @@
+/*
+ * OMAP3 voltage domain data
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include "voltage.h"
+static struct voltagedomain omap2_voltdm_core = {
+        .name = "core",
+};
+static struct voltagedomain omap2_voltdm_wkup = {
+        .name = "wakeup",
+};
+static struct voltagedomain *voltagedomains_omap2[] __initdata = {
+        &omap2_voltdm_core,
+        &omap2_voltdm_wkup,
+        NULL,
+};
+void __init omap2xxx_voltagedomains_init(void)
+{
+        voltdm_init(voltagedomains_omap2);
+}
diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
index def230fd2fde..071101debbbc 100644
--- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
@@ -31,65 +31,70 @@
 * VDD data
 */
-static const struct omap_vfsm_instance_data omap3_vdd1_vfsm_data = {
+static const struct omap_vfsm_instance omap3_vdd1_vfsm = {
        .voltsetup_reg = OMAP3_PRM_VOLTSETUP1_OFFSET,
-        .voltsetup_shift = OMAP3430_SETUP_TIME1_SHIFT,
        .voltsetup_mask = OMAP3430_SETUP_TIME1_MASK,
 };
-static struct omap_vdd_info omap3_vdd1_info = {
+static const struct omap_vfsm_instance omap3_vdd2_vfsm = {
-        .vp_data = &omap3_vp1_data,
-        .vc_data = &omap3_vc1_data,
-        .vfsm = &omap3_vdd1_vfsm_data,
-        .voltdm = {
-                .name = "mpu",
-        },
-};
-static const struct omap_vfsm_instance_data omap3_vdd2_vfsm_data = {
        .voltsetup_reg = OMAP3_PRM_VOLTSETUP1_OFFSET,
-        .voltsetup_shift = OMAP3430_SETUP_TIME2_SHIFT,
        .voltsetup_mask = OMAP3430_SETUP_TIME2_MASK,
 };
-static struct omap_vdd_info omap3_vdd2_info = {
+static struct voltagedomain omap3_voltdm_mpu = {
-        .vp_data = &omap3_vp2_data,
+        .name = "mpu_iva",
-        .vc_data = &omap3_vc2_data,
+        .scalable = true,
-        .vfsm = &omap3_vdd2_vfsm_data,
+        .read = omap3_prm_vcvp_read,
-        .voltdm = {
+        .write = omap3_prm_vcvp_write,
-                .name = "core",
+        .rmw = omap3_prm_vcvp_rmw,
-        },
+        .vc = &omap3_vc_mpu,
+        .vfsm = &omap3_vdd1_vfsm,
+        .vp = &omap3_vp_mpu,
 };
-/* OMAP3 VDD structures */
+static struct voltagedomain omap3_voltdm_core = {
-static struct omap_vdd_info *omap3_vdd_info[] = {
+        .name = "core",
-        &omap3_vdd1_info,
+        .scalable = true,
-        &omap3_vdd2_info,
+        .read = omap3_prm_vcvp_read,
+        .write = omap3_prm_vcvp_write,
+        .rmw = omap3_prm_vcvp_rmw,
+        .vc = &omap3_vc_core,
+        .vfsm = &omap3_vdd2_vfsm,
+        .vp = &omap3_vp_core,
 };
-/* OMAP3 specific voltage init functions */
+static struct voltagedomain omap3_voltdm_wkup = {
-static int __init omap3xxx_voltage_early_init(void)
+        .name = "wakeup",
-{
+};
-        s16 prm_mod = OMAP3430_GR_MOD;
-        s16 prm_irqst_ocp_mod = OCP_MOD;
-        if (!cpu_is_omap34xx())
+static struct voltagedomain *voltagedomains_omap3[] __initdata = {
-                return 0;
+        &omap3_voltdm_mpu,
+        &omap3_voltdm_core,
+        &omap3_voltdm_wkup,
+        NULL,
+};
+static const char *sys_clk_name __initdata = "sys_ck";
+void __init omap3xxx_voltagedomains_init(void)
+{
+        struct voltagedomain *voltdm;
+        int i;
        /*
         * XXX Will depend on the process, validation, and binning
         * for the currently-running IC
         */
        if (cpu_is_omap3630()) {
-                omap3_vdd1_info.volt_data = omap36xx_vddmpu_volt_data;
+                omap3_voltdm_mpu.volt_data = omap36xx_vddmpu_volt_data;
-                omap3_vdd2_info.volt_data = omap36xx_vddcore_volt_data;
+                omap3_voltdm_core.volt_data = omap36xx_vddcore_volt_data;
        } else {
-                omap3_vdd1_info.volt_data = omap34xx_vddmpu_volt_data;
+                omap3_voltdm_mpu.volt_data = omap34xx_vddmpu_volt_data;
-                omap3_vdd2_info.volt_data = omap34xx_vddcore_volt_data;
+                omap3_voltdm_core.volt_data = omap34xx_vddcore_volt_data;
        }
-        return omap_voltage_early_init(prm_mod, prm_irqst_ocp_mod,
+        for (i = 0; voltdm = voltagedomains_omap3[i], voltdm; i++)
-                                       omap3_vdd_info,
+                voltdm->sys_clk.name = sys_clk_name;
-                                       ARRAY_SIZE(omap3_vdd_info));
+        voltdm_init(voltagedomains_omap3);
 };
-core_initcall(omap3xxx_voltage_early_init);
diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c
index cb64996de0e1..c4584e9ac717 100644
--- a/arch/arm/mach-omap2/voltagedomains44xx_data.c
+++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c
@@ -32,71 +32,80 @@
 #include "vc.h"
 #include "vp.h"
-static const struct omap_vfsm_instance_data omap4_vdd_mpu_vfsm_data = {
+static const struct omap_vfsm_instance omap4_vdd_mpu_vfsm = {
        .voltsetup_reg = OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET,
 };
-static struct omap_vdd_info omap4_vdd_mpu_info = {
+static const struct omap_vfsm_instance omap4_vdd_iva_vfsm = {
-        .vp_data = &omap4_vp_mpu_data,
+        .voltsetup_reg = OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET,
-        .vc_data = &omap4_vc_mpu_data,
-        .vfsm = &omap4_vdd_mpu_vfsm_data,
-        .voltdm = {
-                .name = "mpu",
-        },
 };
-static const struct omap_vfsm_instance_data omap4_vdd_iva_vfsm_data = {
+static const struct omap_vfsm_instance omap4_vdd_core_vfsm = {
-        .voltsetup_reg = OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET,
+        .voltsetup_reg = OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET,
 };
-static struct omap_vdd_info omap4_vdd_iva_info = {
+static struct voltagedomain omap4_voltdm_mpu = {
-        .vp_data = &omap4_vp_iva_data,
+        .name = "mpu",
-        .vc_data = &omap4_vc_iva_data,
+        .scalable = true,
-        .vfsm = &omap4_vdd_iva_vfsm_data,
+        .read = omap4_prm_vcvp_read,
-        .voltdm = {
+        .write = omap4_prm_vcvp_write,
-                .name = "iva",
+        .rmw = omap4_prm_vcvp_rmw,
-        },
+        .vc = &omap4_vc_mpu,
+        .vfsm = &omap4_vdd_mpu_vfsm,
+        .vp = &omap4_vp_mpu,
 };
-static const struct omap_vfsm_instance_data omap4_vdd_core_vfsm_data = {
+static struct voltagedomain omap4_voltdm_iva = {
-        .voltsetup_reg = OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET,
+        .name = "iva",
+        .scalable = true,
+        .read = omap4_prm_vcvp_read,
+        .write = omap4_prm_vcvp_write,
+        .rmw = omap4_prm_vcvp_rmw,
+        .vc = &omap4_vc_iva,
+        .vfsm = &omap4_vdd_iva_vfsm,
+        .vp = &omap4_vp_iva,
 };
-static struct omap_vdd_info omap4_vdd_core_info = {
+static struct voltagedomain omap4_voltdm_core = {
-        .vp_data = &omap4_vp_core_data,
+        .name = "core",
-        .vc_data = &omap4_vc_core_data,
+        .scalable = true,
-        .vfsm = &omap4_vdd_core_vfsm_data,
+        .read = omap4_prm_vcvp_read,
-        .voltdm = {
+        .write = omap4_prm_vcvp_write,
-                .name = "core",
+        .rmw = omap4_prm_vcvp_rmw,
-        },
+        .vc = &omap4_vc_core,
+        .vfsm = &omap4_vdd_core_vfsm,
+        .vp = &omap4_vp_core,
 };
-/* OMAP4 VDD structures */
+static struct voltagedomain omap4_voltdm_wkup = {
-static struct omap_vdd_info *omap4_vdd_info[] = {
+        .name = "wakeup",
-        &omap4_vdd_mpu_info,
-        &omap4_vdd_iva_info,
-        &omap4_vdd_core_info,
 };
-/* OMAP4 specific voltage init functions */
+static struct voltagedomain *voltagedomains_omap4[] __initdata = {
-static int __init omap44xx_voltage_early_init(void)
+        &omap4_voltdm_mpu,
-{
+        &omap4_voltdm_iva,
-        s16 prm_mod = OMAP4430_PRM_DEVICE_INST;
+        &omap4_voltdm_core,
-        s16 prm_irqst_ocp_mod = OMAP4430_PRM_OCP_SOCKET_INST;
+        &omap4_voltdm_wkup,
+        NULL,
+};
+static const char *sys_clk_name __initdata = "sys_clkin_ck";
-        if (!cpu_is_omap44xx())
+void __init omap44xx_voltagedomains_init(void)
-                return 0;
+{
+        struct voltagedomain *voltdm;
+        int i;
        /*
         * XXX Will depend on the process, validation, and binning
         * for the currently-running IC
         */
-        omap4_vdd_mpu_info.volt_data = omap44xx_vdd_mpu_volt_data;
+        omap4_voltdm_mpu.volt_data = omap44xx_vdd_mpu_volt_data;
-        omap4_vdd_iva_info.volt_data = omap44xx_vdd_iva_volt_data;
+        omap4_voltdm_iva.volt_data = omap44xx_vdd_iva_volt_data;
-        omap4_vdd_core_info.volt_data = omap44xx_vdd_core_volt_data;
+        omap4_voltdm_core.volt_data = omap44xx_vdd_core_volt_data;
+        for (i = 0; voltdm = voltagedomains_omap4[i], voltdm; i++)
+                voltdm->sys_clk.name = sys_clk_name;
-        return omap_voltage_early_init(prm_mod, prm_irqst_ocp_mod,
+        voltdm_init(voltagedomains_omap4);
-                                       omap4_vdd_info,
-                                       ARRAY_SIZE(omap4_vdd_info));
 };
-core_initcall(omap44xx_voltage_early_init);
diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c
new file mode 100644
index 000000000000..66bd700a2b98
--- /dev/null
+++ b/arch/arm/mach-omap2/vp.c
@@ -0,0 +1,278 @@
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <plat/common.h>
+#include "voltage.h"
+#include "vp.h"
+#include "prm-regbits-34xx.h"
+#include "prm-regbits-44xx.h"
+#include "prm44xx.h"
+static u32 _vp_set_init_voltage(struct voltagedomain *voltdm, u32 volt)
+{
+        struct omap_vp_instance *vp = voltdm->vp;
+        u32 vpconfig;
+        char vsel;
+        vsel = voltdm->pmic->uv_to_vsel(volt);
+        vpconfig = voltdm->read(vp->vpconfig);
+        vpconfig &= ~(vp->common->vpconfig_initvoltage_mask |
+                      vp->common->vpconfig_forceupdate |
+                      vp->common->vpconfig_initvdd);
+        vpconfig |= vsel << __ffs(vp->common->vpconfig_initvoltage_mask);
+        voltdm->write(vpconfig, vp->vpconfig);
+        /* Trigger initVDD value copy to voltage processor */
+        voltdm->write((vpconfig | vp->common->vpconfig_initvdd),
+                       vp->vpconfig);
+        /* Clear initVDD copy trigger bit */
+        voltdm->write(vpconfig, vp->vpconfig);
+        return vpconfig;
+}
+/* Generic voltage init functions */
+void __init omap_vp_init(struct voltagedomain *voltdm)
+{
+        struct omap_vp_instance *vp = voltdm->vp;
+        u32 val, sys_clk_rate, timeout, waittime;
+        u32 vddmin, vddmax, vstepmin, vstepmax;
+        if (!voltdm->read || !voltdm->write) {
+                pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+                        __func__, voltdm->name);
+                return;
+        }
+        vp->enabled = false;
+        /* Divide to avoid overflow */
+        sys_clk_rate = voltdm->sys_clk.rate / 1000;
+        timeout = (sys_clk_rate * voltdm->pmic->vp_timeout_us) / 1000;
+        vddmin = voltdm->pmic->vp_vddmin;
+        vddmax = voltdm->pmic->vp_vddmax;
+        waittime = ((voltdm->pmic->step_size / voltdm->pmic->slew_rate) *
+                    sys_clk_rate) / 1000;
+        vstepmin = voltdm->pmic->vp_vstepmin;
+        vstepmax = voltdm->pmic->vp_vstepmax;
+        /*
+         * VP_CONFIG: error gain is not set here, it will be updated
+         * on each scale, based on OPP.
+         */
+        val = (voltdm->pmic->vp_erroroffset <<
+               __ffs(voltdm->vp->common->vpconfig_erroroffset_mask)) |
+                vp->common->vpconfig_timeouten;
+        voltdm->write(val, vp->vpconfig);
+        /* VSTEPMIN */
+        val = (waittime << vp->common->vstepmin_smpswaittimemin_shift) |
+                (vstepmin <<  vp->common->vstepmin_stepmin_shift);
+        voltdm->write(val, vp->vstepmin);
+        /* VSTEPMAX */
+        val = (vstepmax << vp->common->vstepmax_stepmax_shift) |
+                (waittime << vp->common->vstepmax_smpswaittimemax_shift);
+        voltdm->write(val, vp->vstepmax);
+        /* VLIMITTO */
+        val = (vddmax << vp->common->vlimitto_vddmax_shift) |
+                (vddmin << vp->common->vlimitto_vddmin_shift) |
+                (timeout <<  vp->common->vlimitto_timeout_shift);
+        voltdm->write(val, vp->vlimitto);
+}
+int omap_vp_update_errorgain(struct voltagedomain *voltdm,
+                             unsigned long target_volt)
+{
+        struct omap_volt_data *volt_data;
+        if (!voltdm->vp)
+                return -EINVAL;
+        /* Get volt_data corresponding to target_volt */
+        volt_data = omap_voltage_get_voltdata(voltdm, target_volt);
+        if (IS_ERR(volt_data))
+                return -EINVAL;
+        /* Setting vp errorgain based on the voltage */
+        voltdm->rmw(voltdm->vp->common->vpconfig_errorgain_mask,
+                    volt_data->vp_errgain <<
+                    __ffs(voltdm->vp->common->vpconfig_errorgain_mask),
+                    voltdm->vp->vpconfig);
+        return 0;
+}
+/* VP force update method of voltage scaling */
+int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
+                              unsigned long target_volt)
+{
+        struct omap_vp_instance *vp = voltdm->vp;
+        u32 vpconfig;
+        u8 target_vsel, current_vsel;
+        int ret, timeout = 0;
+        ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, &current_vsel);
+        if (ret)
+                return ret;
+        /*
+         * Clear all pending TransactionDone interrupt/status. Typical latency
+         * is <3us
+         */
+        while (timeout++ < VP_TRANXDONE_TIMEOUT) {
+                vp->common->ops->clear_txdone(vp->id);
+                if (!vp->common->ops->check_txdone(vp->id))
+                        break;
+                udelay(1);
+        }
+        if (timeout >= VP_TRANXDONE_TIMEOUT) {
+                pr_warning("%s: vdd_%s TRANXDONE timeout exceeded."
+                        "Voltage change aborted", __func__, voltdm->name);
+                return -ETIMEDOUT;
+        }
+        vpconfig = _vp_set_init_voltage(voltdm, target_volt);
+        /* Force update of voltage */
+        voltdm->write(vpconfig | vp->common->vpconfig_forceupdate,
+                      voltdm->vp->vpconfig);
+        /*
+         * Wait for TransactionDone. Typical latency is <200us.
+         * Depends on SMPSWAITTIMEMIN/MAX and voltage change
+         */
+        timeout = 0;
+        omap_test_timeout(vp->common->ops->check_txdone(vp->id),
+                          VP_TRANXDONE_TIMEOUT, timeout);
+        if (timeout >= VP_TRANXDONE_TIMEOUT)
+                pr_err("%s: vdd_%s TRANXDONE timeout exceeded."
+                        "TRANXDONE never got set after the voltage update\n",
+                        __func__, voltdm->name);
+        omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
+        /*
+         * Disable TransactionDone interrupt , clear all status, clear
+         * control registers
+         */
+        timeout = 0;
+        while (timeout++ < VP_TRANXDONE_TIMEOUT) {
+                vp->common->ops->clear_txdone(vp->id);
+                if (!vp->common->ops->check_txdone(vp->id))
+                        break;
+                udelay(1);
+        }
+        if (timeout >= VP_TRANXDONE_TIMEOUT)
+                pr_warning("%s: vdd_%s TRANXDONE timeout exceeded while trying"
+                        "to clear the TRANXDONE status\n",
+                        __func__, voltdm->name);
+        /* Clear force bit */
+        voltdm->write(vpconfig, vp->vpconfig);
+        return 0;
+}
+/**
+ * omap_vp_enable() - API to enable a particular VP
+ * @voltdm:     pointer to the VDD whose VP is to be enabled.
+ *
+ * This API enables a particular voltage processor. Needed by the smartreflex
+ * class drivers.
+ */
+void omap_vp_enable(struct voltagedomain *voltdm)
+{
+        struct omap_vp_instance *vp;
+        u32 vpconfig, volt;
+        if (!voltdm || IS_ERR(voltdm)) {
+                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                return;
+        }
+        vp = voltdm->vp;
+        if (!voltdm->read || !voltdm->write) {
+                pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+                        __func__, voltdm->name);
+                return;
+        }
+        /* If VP is already enabled, do nothing. Return */
+        if (vp->enabled)
+                return;
+        volt = voltdm_get_voltage(voltdm);
+        if (!volt) {
+                pr_warning("%s: unable to find current voltage for %s\n",
+                           __func__, voltdm->name);
+                return;
+        }
+        vpconfig = _vp_set_init_voltage(voltdm, volt);
+        /* Enable VP */
+        vpconfig |= vp->common->vpconfig_vpenable;
+        voltdm->write(vpconfig, vp->vpconfig);
+        vp->enabled = true;
+}
+/**
+ * omap_vp_disable() - API to disable a particular VP
+ * @voltdm:     pointer to the VDD whose VP is to be disabled.
+ *
+ * This API disables a particular voltage processor. Needed by the smartreflex
+ * class drivers.
+ */
+void omap_vp_disable(struct voltagedomain *voltdm)
+{
+        struct omap_vp_instance *vp;
+        u32 vpconfig;
+        int timeout;
+        if (!voltdm || IS_ERR(voltdm)) {
+                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                return;
+        }
+        vp = voltdm->vp;
+        if (!voltdm->read || !voltdm->write) {
+                pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+                        __func__, voltdm->name);
+                return;
+        }
+        /* If VP is already disabled, do nothing. Return */
+        if (!vp->enabled) {
+                pr_warning("%s: Trying to disable VP for vdd_%s when"
+                        "it is already disabled\n", __func__, voltdm->name);
+                return;
+        }
+        /* Disable VP */
+        vpconfig = voltdm->read(vp->vpconfig);
+        vpconfig &= ~vp->common->vpconfig_vpenable;
+        voltdm->write(vpconfig, vp->vpconfig);
+        /*
+         * Wait for VP idle Typical latency is <2us. Maximum latency is ~100us
+         */
+        omap_test_timeout((voltdm->read(vp->vstatus)),
+                          VP_IDLE_TIMEOUT, timeout);
+        if (timeout >= VP_IDLE_TIMEOUT)
+                pr_warning("%s: vdd_%s idle timedout\n",
+                        __func__, voltdm->name);
+        vp->enabled = false;
+        return;
+}
diff --git a/arch/arm/mach-omap2/vp.h b/arch/arm/mach-omap2/vp.h
index 7ce134f7de79..7c155d248aa3 100644
--- a/arch/arm/mach-omap2/vp.h
+++ b/arch/arm/mach-omap2/vp.h
@@ -19,44 +19,60 @@
 #include <linux/kernel.h>
+struct voltagedomain;
+/*
+ * Voltage Processor (VP) identifiers
+ */
+#define OMAP3_VP_VDD_MPU_ID 0
+#define OMAP3_VP_VDD_CORE_ID 1
+#define OMAP4_VP_VDD_CORE_ID 0
+#define OMAP4_VP_VDD_IVA_ID 1
+#define OMAP4_VP_VDD_MPU_ID 2
 /* XXX document */
 #define VP_IDLE_TIMEOUT         200
 #define VP_TRANXDONE_TIMEOUT    300
+/**
+ * struct omap_vp_ops - per-VP operations
+ * @check_txdone: check for VP transaction done
+ * @clear_txdone: clear VP transaction done status
+ */
+struct omap_vp_ops {
+        u32 (*check_txdone)(u8 vp_id);
+        void (*clear_txdone)(u8 vp_id);
+};
 /**
- * struct omap_vp_common_data - register data common to all VDDs
+ * struct omap_vp_common - register data common to all VDDs
+ * @vpconfig_erroroffset_mask: ERROROFFSET bitmask in the PRM_VP*_CONFIG reg
 * @vpconfig_errorgain_mask: ERRORGAIN bitmask in the PRM_VP*_CONFIG reg
 * @vpconfig_initvoltage_mask: INITVOLTAGE bitmask in the PRM_VP*_CONFIG reg
- * @vpconfig_timeouten_mask: TIMEOUT bitmask in the PRM_VP*_CONFIG reg
+ * @vpconfig_timeouten: TIMEOUT bitmask in the PRM_VP*_CONFIG reg
 * @vpconfig_initvdd: INITVDD bitmask in the PRM_VP*_CONFIG reg
 * @vpconfig_forceupdate: FORCEUPDATE bitmask in the PRM_VP*_CONFIG reg
 * @vpconfig_vpenable: VPENABLE bitmask in the PRM_VP*_CONFIG reg
 * @vpconfig_erroroffset_shift: ERROROFFSET field shift in PRM_VP*_CONFIG reg
 * @vpconfig_errorgain_shift: ERRORGAIN field shift in PRM_VP*_CONFIG reg
 * @vpconfig_initvoltage_shift: INITVOLTAGE field shift in PRM_VP*_CONFIG reg
- * @vpconfig_stepmin_shift: VSTEPMIN field shift in the PRM_VP*_VSTEPMIN reg
+ * @vstepmin_stepmin_shift: VSTEPMIN field shift in the PRM_VP*_VSTEPMIN reg
- * @vpconfig_smpswaittimemin_shift: SMPSWAITTIMEMIN field shift in PRM_VP*_VSTEPMIN reg
+ * @vstepmin_smpswaittimemin_shift: SMPSWAITTIMEMIN field shift in PRM_VP*_VSTEPMIN reg
- * @vpconfig_stepmax_shift: VSTEPMAX field shift in the PRM_VP*_VSTEPMAX reg
+ * @vstepmax_stepmax_shift: VSTEPMAX field shift in the PRM_VP*_VSTEPMAX reg
- * @vpconfig_smpswaittimemax_shift: SMPSWAITTIMEMAX field shift in PRM_VP*_VSTEPMAX reg
+ * @vstepmax_smpswaittimemax_shift: SMPSWAITTIMEMAX field shift in PRM_VP*_VSTEPMAX reg
- * @vpconfig_vlimitto_vddmin_shift: VDDMIN field shift in PRM_VP*_VLIMITTO reg
+ * @vlimitto_vddmin_shift: VDDMIN field shift in PRM_VP*_VLIMITTO reg
- * @vpconfig_vlimitto_vddmax_shift: VDDMAX field shift in PRM_VP*_VLIMITTO reg
+ * @vlimitto_vddmax_shift: VDDMAX field shift in PRM_VP*_VLIMITTO reg
- * @vpconfig_vlimitto_timeout_shift: TIMEOUT field shift in PRM_VP*_VLIMITTO reg
+ * @vlimitto_timeout_shift: TIMEOUT field shift in PRM_VP*_VLIMITTO reg
- *
+ * @vpvoltage_mask: VPVOLTAGE field mask in PRM_VP*_VOLTAGE reg
- * XXX It it not necessary to have both a mask and a shift for the same
- *     bitfield - remove one
- * XXX Many of these fields are wrongly named -- e.g., vpconfig_smps* -- fix!
 */
-struct omap_vp_common_data {
+struct omap_vp_common {
+        u32 vpconfig_erroroffset_mask;
        u32 vpconfig_errorgain_mask;
        u32 vpconfig_initvoltage_mask;
-        u32 vpconfig_timeouten;
+        u8 vpconfig_timeouten;
-        u32 vpconfig_initvdd;
+        u8 vpconfig_initvdd;
-        u32 vpconfig_forceupdate;
+        u8 vpconfig_forceupdate;
-        u32 vpconfig_vpenable;
+        u8 vpconfig_vpenable;
-        u8 vpconfig_erroroffset_shift;
-        u8 vpconfig_errorgain_shift;
-        u8 vpconfig_initvoltage_shift;
        u8 vstepmin_stepmin_shift;
        u8 vstepmin_smpswaittimemin_shift;
        u8 vstepmax_stepmax_shift;
@@ -64,80 +80,49 @@ struct omap_vp_common_data {
        u8 vlimitto_vddmin_shift;
        u8 vlimitto_vddmax_shift;
        u8 vlimitto_timeout_shift;
-};
+        u8 vpvoltage_mask;
-/**
+        const struct omap_vp_ops *ops;
- * struct omap_vp_prm_irqst_data - PRM_IRQSTATUS_MPU.VP_TRANXDONE_ST data
- * @prm_irqst_reg: reg offset for PRM_IRQSTATUS_MPU from top of PRM
- * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
- *
- * XXX prm_irqst_reg does not belong here
- * XXX Note that on OMAP3, VP_TRANXDONE interrupt may not work due to a
- *     hardware bug
- * XXX This structure is probably not needed
- */
-struct omap_vp_prm_irqst_data {
-        u8 prm_irqst_reg;
-        u32 tranxdone_status;
 };
 /**
- * struct omap_vp_instance_data - VP register offsets (per-VDD)
+ * struct omap_vp_instance - VP register offsets (per-VDD)
- * @vp_common: pointer to struct omap_vp_common_data * for this SoC
+ * @common: pointer to struct omap_vp_common * for this SoC
- * @prm_irqst_data: pointer to struct omap_vp_prm_irqst_data for this VDD
 * @vpconfig: PRM_VP*_CONFIG reg offset from PRM start
 * @vstepmin: PRM_VP*_VSTEPMIN reg offset from PRM start
 * @vlimitto: PRM_VP*_VLIMITTO reg offset from PRM start
 * @vstatus: PRM_VP*_VSTATUS reg offset from PRM start
 * @voltage: PRM_VP*_VOLTAGE reg offset from PRM start
+ * @id: Unique identifier for VP instance.
+ * @enabled: flag to keep track of whether vp is enabled or not
 *
 * XXX vp_common is probably not needed since it is per-SoC
 */
-struct omap_vp_instance_data {
+struct omap_vp_instance {
-        const struct omap_vp_common_data *vp_common;
+        const struct omap_vp_common *common;
-        const struct omap_vp_prm_irqst_data *prm_irqst_data;
        u8 vpconfig;
        u8 vstepmin;
        u8 vstepmax;
        u8 vlimitto;
        u8 vstatus;
        u8 voltage;
+        u8 id;
+        bool enabled;
 };
-/**
+extern struct omap_vp_instance omap3_vp_mpu;
- * struct omap_vp_runtime_data - VP data populated at runtime by code
+extern struct omap_vp_instance omap3_vp_core;
- * @vpconfig_erroroffset: value of ERROROFFSET bitfield in PRM_VP*_CONFIG
- * @vpconfig_errorgain: value of ERRORGAIN bitfield in PRM_VP*_CONFIG
- * @vstepmin_smpswaittimemin: value of SMPSWAITTIMEMIN bitfield in PRM_VP*_VSTEPMIN
- * @vstepmax_smpswaittimemax: value of SMPSWAITTIMEMAX bitfield in PRM_VP*_VSTEPMAX
- * @vlimitto_timeout: value of TIMEOUT bitfield in PRM_VP*_VLIMITTO
- * @vstepmin_stepmin: value of VSTEPMIN bitfield in PRM_VP*_VSTEPMIN
- * @vstepmax_stepmax: value of VSTEPMAX bitfield in PRM_VP*_VSTEPMAX
- * @vlimitto_vddmin: value of VDDMIN bitfield in PRM_VP*_VLIMITTO
- * @vlimitto_vddmax: value of VDDMAX bitfield in PRM_VP*_VLIMITTO
- *
- * XXX Is this structure really needed?  Why not just program the
- * device directly?  They are in PRM space, therefore in the WKUP
- * powerdomain, so register contents should not be lost in off-mode.
- * XXX Some of these fields are incorrectly named, e.g., vstep*
- */
-struct omap_vp_runtime_data {
-        u32 vpconfig_erroroffset;
-        u16 vpconfig_errorgain;
-        u16 vstepmin_smpswaittimemin;
-        u16 vstepmax_smpswaittimemax;
-        u16 vlimitto_timeout;
-        u8 vstepmin_stepmin;
-        u8 vstepmax_stepmax;
-        u8 vlimitto_vddmin;
-        u8 vlimitto_vddmax;
-};
-extern struct omap_vp_instance_data omap3_vp1_data;
+extern struct omap_vp_instance omap4_vp_mpu;
-extern struct omap_vp_instance_data omap3_vp2_data;
+extern struct omap_vp_instance omap4_vp_iva;
+extern struct omap_vp_instance omap4_vp_core;
-extern struct omap_vp_instance_data omap4_vp_mpu_data;
+void omap_vp_init(struct voltagedomain *voltdm);
-extern struct omap_vp_instance_data omap4_vp_iva_data;
+void omap_vp_enable(struct voltagedomain *voltdm);
-extern struct omap_vp_instance_data omap4_vp_core_data;
+void omap_vp_disable(struct voltagedomain *voltdm);
+int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
+                              unsigned long target_volt);
+int omap_vp_update_errorgain(struct voltagedomain *voltdm,
+                             unsigned long target_volt);
 #endif
diff --git a/arch/arm/mach-omap2/vp3xxx_data.c b/arch/arm/mach-omap2/vp3xxx_data.c
index 645217094e51..260c554b1547 100644
--- a/arch/arm/mach-omap2/vp3xxx_data.c
+++ b/arch/arm/mach-omap2/vp3xxx_data.c
@@ -25,16 +25,20 @@
 #include "voltage.h"
 #include "vp.h"
+#include "prm2xxx_3xxx.h"
+static const struct omap_vp_ops omap3_vp_ops = {
+        .check_txdone = omap3_prm_vp_check_txdone,
+        .clear_txdone = omap3_prm_vp_clear_txdone,
+};
 /*
 * VP data common to 34xx/36xx chips
 * XXX This stuff presumably belongs in the vp3xxx.c or vp.c file.
 */
-static const struct omap_vp_common_data omap3_vp_common = {
+static const struct omap_vp_common omap3_vp_common = {
-        .vpconfig_erroroffset_shift = OMAP3430_ERROROFFSET_SHIFT,
+        .vpconfig_erroroffset_mask = OMAP3430_ERROROFFSET_MASK,
        .vpconfig_errorgain_mask = OMAP3430_ERRORGAIN_MASK,
-        .vpconfig_errorgain_shift = OMAP3430_ERRORGAIN_SHIFT,
-        .vpconfig_initvoltage_shift = OMAP3430_INITVOLTAGE_SHIFT,
        .vpconfig_initvoltage_mask = OMAP3430_INITVOLTAGE_MASK,
        .vpconfig_timeouten = OMAP3430_TIMEOUTEN_MASK,
        .vpconfig_initvdd = OMAP3430_INITVDD_MASK,
@@ -47,36 +51,29 @@ static const struct omap_vp_common_data omap3_vp_common = {
        .vlimitto_vddmin_shift = OMAP3430_VDDMIN_SHIFT,
        .vlimitto_vddmax_shift = OMAP3430_VDDMAX_SHIFT,
        .vlimitto_timeout_shift = OMAP3430_TIMEOUT_SHIFT,
-};
+        .vpvoltage_mask = OMAP3430_VPVOLTAGE_MASK,
-static const struct omap_vp_prm_irqst_data omap3_vp1_prm_irqst_data = {
+        .ops = &omap3_vp_ops,
-        .prm_irqst_reg = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
-        .tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,
 };
-struct omap_vp_instance_data omap3_vp1_data = {
+struct omap_vp_instance omap3_vp_mpu = {
-        .vp_common = &omap3_vp_common,
+        .id = OMAP3_VP_VDD_MPU_ID,
+        .common = &omap3_vp_common,
        .vpconfig = OMAP3_PRM_VP1_CONFIG_OFFSET,
        .vstepmin = OMAP3_PRM_VP1_VSTEPMIN_OFFSET,
        .vstepmax = OMAP3_PRM_VP1_VSTEPMAX_OFFSET,
        .vlimitto = OMAP3_PRM_VP1_VLIMITTO_OFFSET,
        .vstatus = OMAP3_PRM_VP1_STATUS_OFFSET,
        .voltage = OMAP3_PRM_VP1_VOLTAGE_OFFSET,
-        .prm_irqst_data = &omap3_vp1_prm_irqst_data,
-};
-static const struct omap_vp_prm_irqst_data omap3_vp2_prm_irqst_data = {
-        .prm_irqst_reg = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
-        .tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,
 };
-struct omap_vp_instance_data omap3_vp2_data = {
+struct omap_vp_instance omap3_vp_core = {
-        .vp_common = &omap3_vp_common,
+        .id = OMAP3_VP_VDD_CORE_ID,
+        .common = &omap3_vp_common,
        .vpconfig = OMAP3_PRM_VP2_CONFIG_OFFSET,
        .vstepmin = OMAP3_PRM_VP2_VSTEPMIN_OFFSET,
        .vstepmax = OMAP3_PRM_VP2_VSTEPMAX_OFFSET,
        .vlimitto = OMAP3_PRM_VP2_VLIMITTO_OFFSET,
        .vstatus = OMAP3_PRM_VP2_STATUS_OFFSET,
        .voltage = OMAP3_PRM_VP2_VOLTAGE_OFFSET,
-        .prm_irqst_data = &omap3_vp2_prm_irqst_data,
 };
diff --git a/arch/arm/mach-omap2/vp44xx_data.c b/arch/arm/mach-omap2/vp44xx_data.c
index 65d1ad63800a..b4e77044891e 100644
--- a/arch/arm/mach-omap2/vp44xx_data.c
+++ b/arch/arm/mach-omap2/vp44xx_data.c
@@ -27,15 +27,18 @@
 #include "vp.h"
+static const struct omap_vp_ops omap4_vp_ops = {
+        .check_txdone = omap4_prm_vp_check_txdone,
+        .clear_txdone = omap4_prm_vp_clear_txdone,
+};
 /*
 * VP data common to 44xx chips
 * XXX This stuff presumably belongs in the vp44xx.c or vp.c file.
 */
-static const struct omap_vp_common_data omap4_vp_common = {
+static const struct omap_vp_common omap4_vp_common = {
-        .vpconfig_erroroffset_shift = OMAP4430_ERROROFFSET_SHIFT,
+        .vpconfig_erroroffset_mask = OMAP4430_ERROROFFSET_MASK,
        .vpconfig_errorgain_mask = OMAP4430_ERRORGAIN_MASK,
-        .vpconfig_errorgain_shift = OMAP4430_ERRORGAIN_SHIFT,
-        .vpconfig_initvoltage_shift = OMAP4430_INITVOLTAGE_SHIFT,
        .vpconfig_initvoltage_mask = OMAP4430_INITVOLTAGE_MASK,
        .vpconfig_timeouten = OMAP4430_TIMEOUTEN_MASK,
        .vpconfig_initvdd = OMAP4430_INITVDD_MASK,
@@ -48,53 +51,39 @@ static const struct omap_vp_common_data omap4_vp_common = {
        .vlimitto_vddmin_shift = OMAP4430_VDDMIN_SHIFT,
        .vlimitto_vddmax_shift = OMAP4430_VDDMAX_SHIFT,
        .vlimitto_timeout_shift = OMAP4430_TIMEOUT_SHIFT,
+        .vpvoltage_mask = OMAP4430_VPVOLTAGE_MASK,
+        .ops = &omap4_vp_ops,
 };
-static const struct omap_vp_prm_irqst_data omap4_vp_mpu_prm_irqst_data = {
+struct omap_vp_instance omap4_vp_mpu = {
-        .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,
+        .id = OMAP4_VP_VDD_MPU_ID,
-        .tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK,
+        .common = &omap4_vp_common,
-};
-struct omap_vp_instance_data omap4_vp_mpu_data = {
-        .vp_common = &omap4_vp_common,
        .vpconfig = OMAP4_PRM_VP_MPU_CONFIG_OFFSET,
        .vstepmin = OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET,
        .vstepmax = OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET,
        .vlimitto = OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET,
        .vstatus = OMAP4_PRM_VP_MPU_STATUS_OFFSET,
        .voltage = OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET,
-        .prm_irqst_data = &omap4_vp_mpu_prm_irqst_data,
 };
-static const struct omap_vp_prm_irqst_data omap4_vp_iva_prm_irqst_data = {
+struct omap_vp_instance omap4_vp_iva = {
-        .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
+        .id = OMAP4_VP_VDD_IVA_ID,
-        .tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK,
+        .common = &omap4_vp_common,
-};
-struct omap_vp_instance_data omap4_vp_iva_data = {
-        .vp_common = &omap4_vp_common,
        .vpconfig = OMAP4_PRM_VP_IVA_CONFIG_OFFSET,
        .vstepmin = OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET,
        .vstepmax = OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET,
        .vlimitto = OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET,
        .vstatus = OMAP4_PRM_VP_IVA_STATUS_OFFSET,
        .voltage = OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET,
-        .prm_irqst_data = &omap4_vp_iva_prm_irqst_data,
-};
-static const struct omap_vp_prm_irqst_data omap4_vp_core_prm_irqst_data = {
-        .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
-        .tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK,
 };
-struct omap_vp_instance_data omap4_vp_core_data = {
+struct omap_vp_instance omap4_vp_core = {
-        .vp_common = &omap4_vp_common,
+        .id = OMAP4_VP_VDD_CORE_ID,
+        .common = &omap4_vp_common,
        .vpconfig = OMAP4_PRM_VP_CORE_CONFIG_OFFSET,
        .vstepmin = OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET,
        .vstepmax = OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET,
        .vlimitto = OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET,
        .vstatus = OMAP4_PRM_VP_CORE_STATUS_OFFSET,
        .voltage = OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET,
-        .prm_irqst_data = &omap4_vp_core_prm_irqst_data,
 };
diff --git a/arch/arm/mach-picoxcell/Makefile b/arch/arm/mach-picoxcell/Makefile
new file mode 100644
index 000000000000..c550b6363488
--- /dev/null
+++ b/arch/arm/mach-picoxcell/Makefile
@@ -0,0 +1,3 @@
+obj-y   := common.o
+obj-y   += time.o
+obj-y   += io.o
diff --git a/arch/arm/mach-picoxcell/Makefile.boot b/arch/arm/mach-picoxcell/Makefile.boot
new file mode 100644
index 000000000000..b3271754e9fd
--- /dev/null
+++ b/arch/arm/mach-picoxcell/Makefile.boot
@@ -0,0 +1 @@
+zreladdr-y := 0x00008000
diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c
new file mode 100644
index 000000000000..34d08347be5f
--- /dev/null
+++ b/arch/arm/mach-picoxcell/common.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * All enquiries to support@picochip.com
+ */
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/hardware/vic.h>
+#include <mach/map.h>
+#include <mach/picoxcell_soc.h>
+#include "common.h"
+static void __init picoxcell_init_machine(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+static const char *picoxcell_dt_match[] = {
+        "picochip,pc3x2",
+        "picochip,pc3x3",
+        NULL
+};
+static const struct of_device_id vic_of_match[] __initconst = {
+        { .compatible = "arm,pl192-vic" },
+        { /* Sentinel */ }
+};
+static void __init picoxcell_init_irq(void)
+{
+        vic_init(IO_ADDRESS(PICOXCELL_VIC0_BASE), 0, ~0, 0);
+        vic_init(IO_ADDRESS(PICOXCELL_VIC1_BASE), 32, ~0, 0);
+        irq_domain_generate_simple(vic_of_match, PICOXCELL_VIC0_BASE, 0);
+        irq_domain_generate_simple(vic_of_match, PICOXCELL_VIC1_BASE, 32);
+}
+DT_MACHINE_START(PICOXCELL, "Picochip picoXcell")
+        .map_io         = picoxcell_map_io,
+        .nr_irqs        = ARCH_NR_IRQS,
+        .init_irq       = picoxcell_init_irq,
+        .timer          = &picoxcell_timer,
+        .init_machine   = picoxcell_init_machine,
+        .dt_compat      = picoxcell_dt_match,
+MACHINE_END
diff --git a/arch/arm/mach-picoxcell/common.h b/arch/arm/mach-picoxcell/common.h
new file mode 100644
index 000000000000..5263f0fa095c
--- /dev/null
+++ b/arch/arm/mach-picoxcell/common.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * All enquiries to support@picochip.com
+ */
+#ifndef __PICOXCELL_COMMON_H__
+#define __PICOXCELL_COMMON_H__
+#include <asm/mach/time.h>
+extern struct sys_timer picoxcell_timer;
+extern void picoxcell_map_io(void);
+#endif /* __PICOXCELL_COMMON_H__ */
diff --git a/arch/arm/mach-picoxcell/include/mach/debug-macro.S b/arch/arm/mach-picoxcell/include/mach/debug-macro.S
new file mode 100644
index 000000000000..8f2c234ed9d9
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/debug-macro.S
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Derived from arch/arm/mach-davinci/include/mach/debug-macro.S to use 32-bit
+ * accesses to the 8250.
+ */
+#include <linux/serial_reg.h>
+#include <mach/hardware.h>
+#include <mach/map.h>
+#define UART_SHIFT 2
+                .macro  addruart, rp, rv
+                ldr     \rv, =PHYS_TO_IO(PICOXCELL_UART1_BASE)
+                ldr     \rp, =PICOXCELL_UART1_BASE
+                .endm
+                .macro  senduart,rd,rx
+                str     \rd, [\rx, #UART_TX << UART_SHIFT]
+                .endm
+                .macro  busyuart,rd,rx
+1002:           ldr     \rd, [\rx, #UART_LSR << UART_SHIFT]
+                and     \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
+                teq     \rd, #UART_LSR_TEMT | UART_LSR_THRE
+                bne     1002b
+                .endm
+                /* The UART's don't have any flow control IO's wired up. */
+                .macro  waituart,rd,rx
+                .endm
diff --git a/arch/arm/mach-picoxcell/include/mach/entry-macro.S b/arch/arm/mach-picoxcell/include/mach/entry-macro.S
new file mode 100644
index 000000000000..a6b09f75d9df
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/entry-macro.S
@@ -0,0 +1,19 @@
+/*
+ * entry-macro.S
+ *
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * Low-level IRQ helper macros for picoXcell platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <mach/map.h>
+#define VA_VIC0         IO_ADDRESS(PICOXCELL_VIC0_BASE)
+#define VA_VIC1         IO_ADDRESS(PICOXCELL_VIC1_BASE)
+#include <asm/entry-macro-vic2.S>
diff --git a/arch/arm/mach-picoxcell/include/mach/gpio.h b/arch/arm/mach-picoxcell/include/mach/gpio.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/gpio.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/arch/arm/mach-picoxcell/include/mach/hardware.h b/arch/arm/mach-picoxcell/include/mach/hardware.h
new file mode 100644
index 000000000000..70ff58192ec9
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/hardware.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This file contains the hardware definitions of the picoXcell SoC devices.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+#include <mach/picoxcell_soc.h>
+#endif
diff --git a/arch/arm/mach-picoxcell/include/mach/io.h b/arch/arm/mach-picoxcell/include/mach/io.h
new file mode 100644
index 000000000000..7573ec7d10a3
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/io.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+/* No ioports, but needed for driver compatibility. */
+#define __io(a)                 __typesafe_io(a)
+/* No PCI possible on picoxcell. */
+#define __mem_pci(a)            (a)
+#endif /* __ASM_ARM_ARCH_IO_H */
diff --git a/arch/arm/mach-picoxcell/include/mach/irqs.h b/arch/arm/mach-picoxcell/include/mach/irqs.h
new file mode 100644
index 000000000000..4d13ed970919
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/irqs.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This file contains the hardware definitions of the picoXcell SoC devices.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __MACH_IRQS_H
+#define __MACH_IRQS_H
+#define ARCH_NR_IRQS                    64
+#define NR_IRQS                         (128 + ARCH_NR_IRQS)
+#define IRQ_VIC0_BASE                   0
+#define IRQ_VIC1_BASE                   32
+#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-picoxcell/include/mach/map.h b/arch/arm/mach-picoxcell/include/mach/map.h
new file mode 100644
index 000000000000..c06afad218bb
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/map.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __PICOXCELL_MAP_H__
+#define __PICOXCELL_MAP_H__
+#define PHYS_TO_IO(x)           (((x) & 0x00ffffff) | 0xfe000000)
+#ifdef __ASSEMBLY__
+#define IO_ADDRESS(x)           PHYS_TO_IO((x))
+#else
+#define IO_ADDRESS(x)           (void __iomem __force *)(PHYS_TO_IO((x)))
+#endif
+#endif /* __PICOXCELL_MAP_H__ */
diff --git a/arch/arm/mach-picoxcell/include/mach/memory.h b/arch/arm/mach-picoxcell/include/mach/memory.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/memory.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/arch/arm/mach-picoxcell/include/mach/picoxcell_soc.h b/arch/arm/mach-picoxcell/include/mach/picoxcell_soc.h
new file mode 100644
index 000000000000..5566fc88ddbc
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/picoxcell_soc.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This file contains the hardware definitions of the picoXcell SoC devices.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __PICOXCELL_SOC_H__
+#define __PICOXCELL_SOC_H__
+#define PICOXCELL_UART1_BASE            0x80230000
+#define PICOXCELL_PERIPH_BASE           0x80000000
+#define PICOXCELL_PERIPH_LENGTH         SZ_4M
+#define PICOXCELL_VIC0_BASE             0x80060000
+#define PICOXCELL_VIC1_BASE             0x80064000
+#endif /* __PICOXCELL_SOC_H__ */
diff --git a/arch/arm/mach-picoxcell/include/mach/system.h b/arch/arm/mach-picoxcell/include/mach/system.h
new file mode 100644
index 000000000000..67c589b0c1bc
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/system.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+static inline void arch_idle(void)
+{
+        /*
+         * This should do all the clock switching and wait for interrupt
+         * tricks.
+         */
+        cpu_do_idle();
+}
+static inline void arch_reset(int mode, const char *cmd)
+{
+        /* Watchdog reset to go here. */
+}
+#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-picoxcell/include/mach/timex.h b/arch/arm/mach-picoxcell/include/mach/timex.h
new file mode 100644
index 000000000000..6c540a69f405
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/timex.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __TIMEX_H__
+#define __TIMEX_H__
+/* Bogus value to allow the kernel to compile. */
+#define CLOCK_TICK_RATE         1000000
+#endif /* __TIMEX_H__ */
diff --git a/arch/arm/mach-picoxcell/include/mach/uncompress.h b/arch/arm/mach-picoxcell/include/mach/uncompress.h
new file mode 100644
index 000000000000..b60b19d1d739
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/uncompress.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#define putc(c)
+#define flush()
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-picoxcell/include/mach/vmalloc.h b/arch/arm/mach-picoxcell/include/mach/vmalloc.h
new file mode 100644
index 000000000000..0216cc4b1f0b
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/vmalloc.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#define VMALLOC_END     0xfe000000UL
diff --git a/arch/arm/mach-picoxcell/io.c b/arch/arm/mach-picoxcell/io.c
new file mode 100644
index 000000000000..39e9b9e8cc37
--- /dev/null
+++ b/arch/arm/mach-picoxcell/io.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * All enquiries to support@picochip.com
+ */
+#include <linux/io.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <asm/mach/map.h>
+#include <mach/map.h>
+#include <mach/picoxcell_soc.h>
+#include "common.h"
+void __init picoxcell_map_io(void)
+{
+        struct map_desc io_map = {
+                .virtual        = PHYS_TO_IO(PICOXCELL_PERIPH_BASE),
+                .pfn            = __phys_to_pfn(PICOXCELL_PERIPH_BASE),
+                .length         = PICOXCELL_PERIPH_LENGTH,
+                .type           = MT_DEVICE,
+        };
+        iotable_init(&io_map, 1);
+}
diff --git a/arch/arm/mach-picoxcell/time.c b/arch/arm/mach-picoxcell/time.c
new file mode 100644
index 000000000000..90a554ff4499
--- /dev/null
+++ b/arch/arm/mach-picoxcell/time.c
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * All enquiries to support@picochip.com
+ */
+#include <linux/dw_apb_timer.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/sched.h>
+#include <asm/mach/time.h>
+#include <asm/sched_clock.h>
+#include "common.h"
+static void timer_get_base_and_rate(struct device_node *np,
+                                    void __iomem **base, u32 *rate)
+{
+        *base = of_iomap(np, 0);
+        if (!*base)
+                panic("Unable to map regs for %s", np->name);
+        if (of_property_read_u32(np, "clock-freq", rate))
+                panic("No clock-freq property for %s", np->name);
+}
+static void picoxcell_add_clockevent(struct device_node *event_timer)
+{
+        void __iomem *iobase;
+        struct dw_apb_clock_event_device *ced;
+        u32 irq, rate;
+        irq = irq_of_parse_and_map(event_timer, 0);
+        if (irq == NO_IRQ)
+                panic("No IRQ for clock event timer");
+        timer_get_base_and_rate(event_timer, &iobase, &rate);
+        ced = dw_apb_clockevent_init(0, event_timer->name, 300, iobase, irq,
+                                     rate);
+        if (!ced)
+                panic("Unable to initialise clockevent device");
+        dw_apb_clockevent_register(ced);
+}
+static void picoxcell_add_clocksource(struct device_node *source_timer)
+{
+        void __iomem *iobase;
+        struct dw_apb_clocksource *cs;
+        u32 rate;
+        timer_get_base_and_rate(source_timer, &iobase, &rate);
+        cs = dw_apb_clocksource_init(300, source_timer->name, iobase, rate);
+        if (!cs)
+                panic("Unable to initialise clocksource device");
+        dw_apb_clocksource_start(cs);
+        dw_apb_clocksource_register(cs);
+}
+static DEFINE_CLOCK_DATA(cd);
+static void __iomem *sched_io_base;
+unsigned long long notrace sched_clock(void)
+{
+        cycle_t cyc = sched_io_base ? __raw_readl(sched_io_base) : 0;
+        return cyc_to_sched_clock(&cd, cyc, (u32)~0);
+}
+static void notrace picoxcell_update_sched_clock(void)
+{
+        cycle_t cyc = sched_io_base ? __raw_readl(sched_io_base) : 0;
+        update_sched_clock(&cd, cyc, (u32)~0);
+}
+static const struct of_device_id picoxcell_rtc_ids[] __initconst = {
+        { .compatible = "picochip,pc3x2-rtc" },
+        { /* Sentinel */ },
+};
+static void picoxcell_init_sched_clock(void)
+{
+        struct device_node *sched_timer;
+        u32 rate;
+        sched_timer = of_find_matching_node(NULL, picoxcell_rtc_ids);
+        if (!sched_timer)
+                panic("No RTC for sched clock to use");
+        timer_get_base_and_rate(sched_timer, &sched_io_base, &rate);
+        of_node_put(sched_timer);
+        init_sched_clock(&cd, picoxcell_update_sched_clock, 32, rate);
+}
+static const struct of_device_id picoxcell_timer_ids[] __initconst = {
+        { .compatible = "picochip,pc3x2-timer" },
+        {},
+};
+static void __init picoxcell_timer_init(void)
+{
+        struct device_node *event_timer, *source_timer;
+        event_timer = of_find_matching_node(NULL, picoxcell_timer_ids);
+        if (!event_timer)
+                panic("No timer for clockevent");
+        picoxcell_add_clockevent(event_timer);
+        source_timer = of_find_matching_node(event_timer, picoxcell_timer_ids);
+        if (!source_timer)
+                panic("No timer for clocksource");
+        picoxcell_add_clocksource(source_timer);
+        of_node_put(source_timer);
+        picoxcell_init_sched_clock();
+}
+struct sys_timer picoxcell_timer = {
+        .init = picoxcell_timer_init,
+};
diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile
index 7af7fc05d565..13dd1604d951 100644
--- a/arch/arm/mach-prima2/Makefile
+++ b/arch/arm/mach-prima2/Makefile
@@ -3,5 +3,7 @@ obj-y += irq.o
 obj-y += clock.o
 obj-y += rstc.o
 obj-y += prima2.o
+obj-y += rtciobrg.o
 obj-$(CONFIG_DEBUG_LL) += lluart.o
 obj-$(CONFIG_CACHE_L2X0) += l2x0.o
+obj-$(CONFIG_SUSPEND) += pm.o sleep.o
diff --git a/arch/arm/mach-prima2/clock.c b/arch/arm/mach-prima2/clock.c
index 615a4e75ceab..aebad7e565cf 100644
--- a/arch/arm/mach-prima2/clock.c
+++ b/arch/arm/mach-prima2/clock.c
@@ -350,10 +350,10 @@ static struct clk_lookup onchip_clks[] = {
                .clk = &clk_mem,
        }, {
                .dev_id = "sys",
-                        .clk = &clk_sys,
+                .clk = &clk_sys,
        }, {
                .dev_id = "io",
-                        .clk = &clk_io,
+                .clk = &clk_io,
        },
 };
diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-prima2/irq.c
index 7af254d046ba..d93ceef4a50a 100644
--- a/arch/arm/mach-prima2/irq.c
+++ b/arch/arm/mach-prima2/irq.c
@@ -13,6 +13,8 @@
 #include <asm/mach/irq.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/irqdomain.h>
+#include <linux/syscore_ops.h>
 #define SIRFSOC_INT_RISC_MASK0          0x0018
 #define SIRFSOC_INT_RISC_MASK1          0x001C
@@ -66,7 +68,48 @@ void __init sirfsoc_of_irq_init(void)
        if (!sirfsoc_intc_base)
                panic("unable to map intc cpu registers\n");
+        irq_domain_add_simple(np, 0);
        of_node_put(np);
        sirfsoc_irq_init();
 }
+struct sirfsoc_irq_status {
+        u32 mask0;
+        u32 mask1;
+        u32 level0;
+        u32 level1;
+};
+static struct sirfsoc_irq_status sirfsoc_irq_st;
+static int sirfsoc_irq_suspend(void)
+{
+        sirfsoc_irq_st.mask0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
+        sirfsoc_irq_st.mask1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
+        sirfsoc_irq_st.level0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
+        sirfsoc_irq_st.level1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
+        return 0;
+}
+static void sirfsoc_irq_resume(void)
+{
+        writel_relaxed(sirfsoc_irq_st.mask0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
+        writel_relaxed(sirfsoc_irq_st.mask1, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
+        writel_relaxed(sirfsoc_irq_st.level0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
+        writel_relaxed(sirfsoc_irq_st.level1, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
+}
+static struct syscore_ops sirfsoc_irq_syscore_ops = {
+        .suspend        = sirfsoc_irq_suspend,
+        .resume         = sirfsoc_irq_resume,
+};
+static int __init sirfsoc_irq_pm_init(void)
+{
+        register_syscore_ops(&sirfsoc_irq_syscore_ops);
+        return 0;
+}
+device_initcall(sirfsoc_irq_pm_init);
diff --git a/arch/arm/mach-prima2/l2x0.c b/arch/arm/mach-prima2/l2x0.c
index 66c6387e5a04..c99837797d76 100644
--- a/arch/arm/mach-prima2/l2x0.c
+++ b/arch/arm/mach-prima2/l2x0.c
@@ -8,51 +8,24 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/errno.h>
 #include <linux/of.h>
-#include <linux/of_address.h>
 #include <asm/hardware/cache-l2x0.h>
-#define L2X0_ADDR_FILTERING_START       0xC00
+static struct of_device_id prima2_l2x0_ids[]  = {
-#define L2X0_ADDR_FILTERING_END         0xC04
+        { .compatible = "sirf,prima2-pl310-cache" },
+        {},
-static struct of_device_id l2x_ids[]  = {
-        { .compatible = "arm,pl310-cache" },
 };
-static int __init sirfsoc_of_l2x_init(void)
+static int __init sirfsoc_l2x0_init(void)
 {
        struct device_node *np;
-        void __iomem *sirfsoc_l2x_base;
-        np = of_find_matching_node(NULL, l2x_ids);
-        if (!np)
-                panic("unable to find compatible l2x node in dtb\n");
-        sirfsoc_l2x_base = of_iomap(np, 0);
-        if (!sirfsoc_l2x_base)
-                panic("unable to map l2x cpu registers\n");
-        of_node_put(np);
-        if (!(readl_relaxed(sirfsoc_l2x_base + L2X0_CTRL) & 1)) {
-                /*
-                 * set the physical memory windows L2 cache will cover
-                 */
-                writel_relaxed(PHYS_OFFSET + 1024 * 1024 * 1024,
-                        sirfsoc_l2x_base + L2X0_ADDR_FILTERING_END);
-                writel_relaxed(PHYS_OFFSET | 0x1,
-                        sirfsoc_l2x_base + L2X0_ADDR_FILTERING_START);
-                writel_relaxed(0,
+        np = of_find_matching_node(NULL, prima2_l2x0_ids);
-                        sirfsoc_l2x_base + L2X0_TAG_LATENCY_CTRL);
+        if (np) {
-                writel_relaxed(0,
+                pr_info("Initializing prima2 L2 cache\n");
-                        sirfsoc_l2x_base + L2X0_DATA_LATENCY_CTRL);
+                return l2x0_of_init(0x40000, 0);
        }
-        l2x0_init((void __iomem *)sirfsoc_l2x_base, 0x00040000,
-                0x00000000);
        return 0;
 }
-early_initcall(sirfsoc_of_l2x_init);
+early_initcall(sirfsoc_l2x0_init);
diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-prima2/pm.c
new file mode 100644
index 000000000000..cb53160f6c5d
--- /dev/null
+++ b/arch/arm/mach-prima2/pm.c
@@ -0,0 +1,150 @@
+/*
+ * power management entry for CSR SiRFprimaII
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+#include <linux/kernel.h>
+#include <linux/suspend.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/io.h>
+#include <linux/rtc/sirfsoc_rtciobrg.h>
+#include <asm/suspend.h>
+#include <asm/hardware/cache-l2x0.h>
+#include "pm.h"
+/*
+ * suspend asm codes will access these to make DRAM become self-refresh and
+ * system sleep
+ */
+u32 sirfsoc_pwrc_base;
+void __iomem *sirfsoc_memc_base;
+static void sirfsoc_set_wakeup_source(void)
+{
+        u32 pwr_trigger_en_reg;
+        pwr_trigger_en_reg = sirfsoc_rtc_iobrg_readl(sirfsoc_pwrc_base +
+                SIRFSOC_PWRC_TRIGGER_EN);
+#define X_ON_KEY_B (1 << 0)
+        sirfsoc_rtc_iobrg_writel(pwr_trigger_en_reg | X_ON_KEY_B,
+                sirfsoc_pwrc_base + SIRFSOC_PWRC_TRIGGER_EN);
+}
+static void sirfsoc_set_sleep_mode(u32 mode)
+{
+        u32 sleep_mode = sirfsoc_rtc_iobrg_readl(sirfsoc_pwrc_base +
+                SIRFSOC_PWRC_PDN_CTRL);
+        sleep_mode &= ~(SIRFSOC_SLEEP_MODE_MASK << 1);
+        sleep_mode |= mode << 1;
+        sirfsoc_rtc_iobrg_writel(sleep_mode, sirfsoc_pwrc_base +
+                SIRFSOC_PWRC_PDN_CTRL);
+}
+static int sirfsoc_pre_suspend_power_off(void)
+{
+        u32 wakeup_entry = virt_to_phys(cpu_resume);
+        sirfsoc_rtc_iobrg_writel(wakeup_entry, sirfsoc_pwrc_base +
+                SIRFSOC_PWRC_SCRATCH_PAD1);
+        sirfsoc_set_wakeup_source();
+        sirfsoc_set_sleep_mode(SIRFSOC_DEEP_SLEEP_MODE);
+        return 0;
+}
+static int sirfsoc_pm_enter(suspend_state_t state)
+{
+        switch (state) {
+        case PM_SUSPEND_MEM:
+                sirfsoc_pre_suspend_power_off();
+                outer_flush_all();
+                outer_disable();
+                /* go zzz */
+                cpu_suspend(0, sirfsoc_finish_suspend);
+                outer_resume();
+                break;
+        default:
+                return -EINVAL;
+        }
+        return 0;
+}
+static const struct platform_suspend_ops sirfsoc_pm_ops = {
+        .enter = sirfsoc_pm_enter,
+        .valid = suspend_valid_only_mem,
+};
+static int __init sirfsoc_pm_init(void)
+{
+        suspend_set_ops(&sirfsoc_pm_ops);
+        return 0;
+}
+late_initcall(sirfsoc_pm_init);
+static const struct of_device_id pwrc_ids[] = {
+        { .compatible = "sirf,prima2-pwrc" },
+        {}
+};
+static int __init sirfsoc_of_pwrc_init(void)
+{
+        struct device_node *np;
+        np = of_find_matching_node(NULL, pwrc_ids);
+        if (!np)
+                panic("unable to find compatible pwrc node in dtb\n");
+        /*
+         * pwrc behind rtciobrg is not located in memory space
+         * though the property is named reg. reg only means base
+         * offset for pwrc. then of_iomap is not suitable here.
+         */
+        if (of_property_read_u32(np, "reg", &sirfsoc_pwrc_base))
+                panic("unable to find base address of pwrc node in dtb\n");
+        of_node_put(np);
+        return 0;
+}
+postcore_initcall(sirfsoc_of_pwrc_init);
+static const struct of_device_id memc_ids[] = {
+        { .compatible = "sirf,prima2-memc" },
+        {}
+};
+static int __devinit sirfsoc_memc_probe(struct platform_device *op)
+{
+        struct device_node *np = op->dev.of_node;
+        sirfsoc_memc_base = of_iomap(np, 0);
+        if (!sirfsoc_memc_base)
+                panic("unable to map memc registers\n");
+        return 0;
+}
+static struct platform_driver sirfsoc_memc_driver = {
+        .probe          = sirfsoc_memc_probe,
+        .driver = {
+                .name = "sirfsoc-memc",
+                .owner = THIS_MODULE,
+                .of_match_table = memc_ids,
+        },
+};
+static int __init sirfsoc_memc_init(void)
+{
+        return platform_driver_register(&sirfsoc_memc_driver);
+}
+postcore_initcall(sirfsoc_memc_init);
diff --git a/arch/arm/mach-prima2/pm.h b/arch/arm/mach-prima2/pm.h
new file mode 100644
index 000000000000..bae6d77e01ab
--- /dev/null
+++ b/arch/arm/mach-prima2/pm.h
@@ -0,0 +1,29 @@
+/*
+ * arch/arm/mach-prima2/pm.h
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+#ifndef _MACH_PRIMA2_PM_H_
+#define _MACH_PRIMA2_PM_H_
+#define SIRFSOC_PWR_SLEEPFORCE          0x01
+#define SIRFSOC_SLEEP_MODE_MASK         0x3
+#define SIRFSOC_DEEP_SLEEP_MODE         0x1
+#define SIRFSOC_PWRC_PDN_CTRL           0x0
+#define SIRFSOC_PWRC_PON_OFF            0x4
+#define SIRFSOC_PWRC_TRIGGER_EN         0x8
+#define SIRFSOC_PWRC_PIN_STATUS         0x14
+#define SIRFSOC_PWRC_SCRATCH_PAD1       0x18
+#define SIRFSOC_PWRC_SCRATCH_PAD2       0x1C
+#ifndef __ASSEMBLY__
+extern int sirfsoc_finish_suspend(unsigned long);
+#endif
+#endif
diff --git a/arch/arm/mach-prima2/prima2.c b/arch/arm/mach-prima2/prima2.c
index ee33c3d458f5..ef555c041962 100644
--- a/arch/arm/mach-prima2/prima2.c
+++ b/arch/arm/mach-prima2/prima2.c
@@ -1,5 +1,5 @@
 /*
- * Defines machines for CSR SiRFprimaII 
+ * Defines machines for CSR SiRFprimaII
 *
 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
 *
diff --git a/arch/arm/mach-prima2/rtciobrg.c b/arch/arm/mach-prima2/rtciobrg.c
new file mode 100644
index 000000000000..9d80f1e20a98
--- /dev/null
+++ b/arch/arm/mach-prima2/rtciobrg.c
@@ -0,0 +1,139 @@
+/*
+ * RTC I/O Bridge interfaces for CSR SiRFprimaII
+ * ARM access the registers of SYSRTC, GPSRTC and PWRC through this module
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#define SIRFSOC_CPUIOBRG_CTRL           0x00
+#define SIRFSOC_CPUIOBRG_WRBE           0x04
+#define SIRFSOC_CPUIOBRG_ADDR           0x08
+#define SIRFSOC_CPUIOBRG_DATA           0x0c
+/*
+ * suspend asm codes will access this address to make system deepsleep
+ * after DRAM becomes self-refresh
+ */
+void __iomem *sirfsoc_rtciobrg_base;
+static DEFINE_SPINLOCK(rtciobrg_lock);
+/*
+ * symbols without lock are only used by suspend asm codes
+ * and these symbols are not exported too
+ */
+void sirfsoc_rtc_iobrg_wait_sync(void)
+{
+        while (readl_relaxed(sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_CTRL))
+                cpu_relax();
+}
+void sirfsoc_rtc_iobrg_besyncing(void)
+{
+        unsigned long flags;
+        spin_lock_irqsave(&rtciobrg_lock, flags);
+        sirfsoc_rtc_iobrg_wait_sync();
+        spin_unlock_irqrestore(&rtciobrg_lock, flags);
+}
+EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_besyncing);
+u32 __sirfsoc_rtc_iobrg_readl(u32 addr)
+{
+        sirfsoc_rtc_iobrg_wait_sync();
+        writel_relaxed(0x00, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_WRBE);
+        writel_relaxed(addr, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_ADDR);
+        writel_relaxed(0x01, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_CTRL);
+        sirfsoc_rtc_iobrg_wait_sync();
+        return readl_relaxed(sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_DATA);
+}
+u32 sirfsoc_rtc_iobrg_readl(u32 addr)
+{
+        unsigned long flags, val;
+        spin_lock_irqsave(&rtciobrg_lock, flags);
+        val = __sirfsoc_rtc_iobrg_readl(addr);
+        spin_unlock_irqrestore(&rtciobrg_lock, flags);
+        return val;
+}
+EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_readl);
+void sirfsoc_rtc_iobrg_pre_writel(u32 val, u32 addr)
+{
+        sirfsoc_rtc_iobrg_wait_sync();
+        writel_relaxed(0xf1, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_WRBE);
+        writel_relaxed(addr, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_ADDR);
+        writel_relaxed(val, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_DATA);
+}
+void sirfsoc_rtc_iobrg_writel(u32 val, u32 addr)
+{
+        unsigned long flags;
+        spin_lock_irqsave(&rtciobrg_lock, flags);
+        sirfsoc_rtc_iobrg_pre_writel(val, addr);
+        writel_relaxed(0x01, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_CTRL);
+        sirfsoc_rtc_iobrg_wait_sync();
+        spin_unlock_irqrestore(&rtciobrg_lock, flags);
+}
+EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_writel);
+static const struct of_device_id rtciobrg_ids[] = {
+        { .compatible = "sirf,prima2-rtciobg" },
+        {}
+};
+static int __devinit sirfsoc_rtciobrg_probe(struct platform_device *op)
+{
+        struct device_node *np = op->dev.of_node;
+        sirfsoc_rtciobrg_base = of_iomap(np, 0);
+        if (!sirfsoc_rtciobrg_base)
+                panic("unable to map rtc iobrg registers\n");
+        return 0;
+}
+static struct platform_driver sirfsoc_rtciobrg_driver = {
+        .probe          = sirfsoc_rtciobrg_probe,
+        .driver = {
+                .name = "sirfsoc-rtciobrg",
+                .owner = THIS_MODULE,
+                .of_match_table = rtciobrg_ids,
+        },
+};
+static int __init sirfsoc_rtciobrg_init(void)
+{
+        return platform_driver_register(&sirfsoc_rtciobrg_driver);
+}
+postcore_initcall(sirfsoc_rtciobrg_init);
+MODULE_AUTHOR("Zhiwu Song <zhiwu.song@csr.com>, "
+                "Barry Song <baohua.song@csr.com>");
+MODULE_DESCRIPTION("CSR SiRFprimaII rtc io bridge");
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-prima2/sleep.S b/arch/arm/mach-prima2/sleep.S
new file mode 100644
index 000000000000..0745abc365fc
--- /dev/null
+++ b/arch/arm/mach-prima2/sleep.S
@@ -0,0 +1,64 @@
+/*
+ * sleep mode for CSR SiRFprimaII
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+#include <linux/linkage.h>
+#include <asm/ptrace.h>
+#include <asm/assembler.h>
+#include "pm.h"
+#define DENALI_CTL_22_OFF       0x58
+#define DENALI_CTL_112_OFF      0x1c0
+        .text
+ENTRY(sirfsoc_finish_suspend)
+        @ r5:   mem controller
+        ldr     r0, =sirfsoc_memc_base
+        ldr     r5, [r0]
+        @ r6:   pwrc base offset
+        ldr     r0, =sirfsoc_pwrc_base
+        ldr     r6, [r0]
+        @ r7:   rtc iobrg controller
+        ldr     r0, =sirfsoc_rtciobrg_base
+        ldr     r7, [r0]
+        @ Read the power control register and set the
+        @ sleep force bit.
+        add     r0, r6, #SIRFSOC_PWRC_PDN_CTRL
+        bl      __sirfsoc_rtc_iobrg_readl
+        orr     r0,r0,#SIRFSOC_PWR_SLEEPFORCE
+        add     r1, r6, #SIRFSOC_PWRC_PDN_CTRL
+        bl      sirfsoc_rtc_iobrg_pre_writel
+        mov     r1, #0x1
+        @ read the MEM ctl register and set the self
+        @ refresh bit
+        ldr     r2, [r5, #DENALI_CTL_22_OFF]
+        orr     r2, r2, #0x1
+        @ Following code has to run from cache since
+        @ the RAM is going to self refresh mode
+        .align 5
+        str     r2, [r5, #DENALI_CTL_22_OFF]
+1:
+        ldr     r4, [r5, #DENALI_CTL_112_OFF]
+        tst     r4, #0x1
+        bne     1b
+        @ write SLEEPFORCE through rtc iobridge
+        str     r1, [r7]
+        @ wait rtc io bridge sync
+1:
+        ldr     r3, [r7]
+        tst     r3, #0x01
+        bne     1b
+        b .
diff --git a/arch/arm/mach-prima2/timer.c b/arch/arm/mach-prima2/timer.c
index ed7ec48d11da..b7a6091ce791 100644
--- a/arch/arm/mach-prima2/timer.c
+++ b/arch/arm/mach-prima2/timer.c
@@ -40,6 +40,17 @@
 #define SIRFSOC_TIMER_LATCH_BIT  BIT(0)
+#define SIRFSOC_TIMER_REG_CNT 11
+static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
+        SIRFSOC_TIMER_MATCH_0, SIRFSOC_TIMER_MATCH_1, SIRFSOC_TIMER_MATCH_2,
+        SIRFSOC_TIMER_MATCH_3, SIRFSOC_TIMER_MATCH_4, SIRFSOC_TIMER_MATCH_5,
+        SIRFSOC_TIMER_INT_EN, SIRFSOC_TIMER_WATCHDOG_EN, SIRFSOC_TIMER_DIV,
+        SIRFSOC_TIMER_LATCHED_LO, SIRFSOC_TIMER_LATCHED_HI,
+};
+static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
 static void __iomem *sirfsoc_timer_base;
 static void __init sirfsoc_of_timer_map(void);
@@ -106,6 +117,27 @@ static void sirfsoc_timer_set_mode(enum clock_event_mode mode,
        }
 }
+static void sirfsoc_clocksource_suspend(struct clocksource *cs)
+{
+        int i;
+        writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
+        for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
+                sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
+}
+static void sirfsoc_clocksource_resume(struct clocksource *cs)
+{
+        int i;
+        for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
+                writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
+        writel_relaxed(sirfsoc_timer_reg_val[i - 2], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
+        writel_relaxed(sirfsoc_timer_reg_val[i - 1], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
+}
 static struct clock_event_device sirfsoc_clockevent = {
        .name = "sirfsoc_clockevent",
        .rating = 200,
@@ -120,6 +152,8 @@ static struct clocksource sirfsoc_clocksource = {
        .mask = CLOCKSOURCE_MASK(64),
        .flags = CLOCK_SOURCE_IS_CONTINUOUS,
        .read = sirfsoc_timer_read,
+        .suspend = sirfsoc_clocksource_suspend,
+        .resume = sirfsoc_clocksource_resume,
 };
 static struct irqaction sirfsoc_timer_irq = {
@@ -133,14 +167,14 @@ static struct irqaction sirfsoc_timer_irq = {
 /* Overwrite weak default sched_clock with more precise one */
 unsigned long long notrace sched_clock(void)
 {
-        static int is_mapped = 0;
+        static int is_mapped;
        /*
         * sched_clock is called earlier than .init of sys_timer
         * if we map timer memory in .init of sys_timer, system
         * will panic due to illegal memory access
         */
-        if(!is_mapped) {
+        if (!is_mapped) {
                sirfsoc_of_timer_map();
                is_mapped = 1;
        }
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index cd19309fd3b8..61d3c72ded84 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -2,6 +2,27 @@ if ARCH_PXA
 menu "Intel PXA2xx/PXA3xx Implementations"
+config ARCH_PXA_V7
+        bool "ARMv7 (PXA95x) based systems"
+if ARCH_PXA_V7
+comment "Marvell Dev Platforms (sorted by hardware release time)"
+config MACH_TAVOREVB3
+        bool "PXA95x Development Platform (aka TavorEVB III)"
+        select CPU_PXA955
+config MACH_SAARB
+        bool "PXA955 Handheld Platform (aka SAARB)"
+        select CPU_PXA955
+endif
+config PXA_V7_MACH_AUTO
+        def_bool y
+        depends on ARCH_PXA_V7
+        depends on !MACH_SAARB
+        select MACH_TAVOREVB3
+if !ARCH_PXA_V7
 comment "Intel/Marvell Dev Platforms (sorted by hardware release time)"
 config ARCH_LUBBOCK
@@ -41,19 +62,11 @@ config MACH_TAVOREVB
        select PXA3xx
        select CPU_PXA930
-config MACH_TAVOREVB3
-        bool "PXA95x Development Platform (aka TavorEVB III)"
-        select CPU_PXA950
 config MACH_SAAR
        bool "PXA930 Handheld Platform (aka SAAR)"
        select PXA3xx
        select CPU_PXA930
-config MACH_SAARB
-        bool "PXA955 Handheld Platform (aka SAARB)"
-        select CPU_PXA955
 comment "Third Party Dev Platforms (sorted by vendor name)"
 config ARCH_PXA_IDP
@@ -414,6 +427,7 @@ config MACH_CENTRO
        bool "Palm Centro 685 (GSM)"
        default y
        depends on ARCH_PXA_PALM
+        select MACH_PALM27X
        select PXA27x
        select IWMMXT
        select PALM_TREO
@@ -425,6 +439,7 @@ config MACH_TREO680
        bool "Palm Treo 680"
        default y
        depends on ARCH_PXA_PALM
+        select MACH_PALM27X
        select PXA27x
        select IWMMXT
        select PALM_TREO
@@ -436,15 +451,18 @@ config MACH_RAUMFELD_RC
        bool "Raumfeld Controller"
        select PXA3xx
        select CPU_PXA300
+        select POWER_SUPPLY
        select HAVE_PWM
 config MACH_RAUMFELD_CONNECTOR
        bool "Raumfeld Connector"
+        select POWER_SUPPLY
        select PXA3xx
        select CPU_PXA300
 config MACH_RAUMFELD_SPEAKER
        bool "Raumfeld Speaker"
+        select POWER_SUPPLY
        select PXA3xx
        select CPU_PXA300
@@ -598,7 +616,7 @@ config MACH_ZIPIT2
        bool "Zipit Z2 Handheld"
        select PXA27x
        select HAVE_PWM
+endif
 endmenu
 config PXA25x
@@ -688,6 +706,8 @@ config SHARPSL_PM
 config SHARPSL_PM_MAX1111
        bool
        select HWMON
+        select SPI
+        select SPI_MASTER
        select SENSORS_MAX1111
 config PXA_HAVE_ISA_IRQS
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index cc39d17b2e07..be0f7df8685c 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -19,7 +19,7 @@ endif
 obj-$(CONFIG_PXA25x)            += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa25x.o
 obj-$(CONFIG_PXA27x)            += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa27x.o
 obj-$(CONFIG_PXA3xx)            += mfp-pxa3xx.o clock-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o
-obj-$(CONFIG_PXA95x)            += mfp-pxa3xx.o clock-pxa3xx.o pxa95x.o smemc.o
+obj-$(CONFIG_PXA95x)            += mfp-pxa3xx.o clock-pxa3xx.o pxa3xx.o pxa95x.o smemc.o
 obj-$(CONFIG_CPU_PXA300)        += pxa300.o
 obj-$(CONFIG_CPU_PXA320)        += pxa320.o
 obj-$(CONFIG_CPU_PXA930)        += pxa930.o
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c
index 7765d677adbb..fc0b8544e174 100644
--- a/arch/arm/mach-pxa/balloon3.c
+++ b/arch/arm/mach-pxa/balloon3.c
@@ -591,7 +591,7 @@ static void balloon3_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ct
                                BALLOON3_NAND_CONTROL_REG);
                if (balloon3_ctl_set)
                        __raw_writel(balloon3_ctl_set,
-                                BALLOON3_NAND_CONTROL_REG |
+                                BALLOON3_NAND_CONTROL_REG +
                                BALLOON3_FPGA_SETnCLR);
        }
@@ -608,7 +608,7 @@ static void balloon3_nand_select_chip(struct mtd_info *mtd, int chip)
        __raw_writew(
                BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 |
                BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3,
-                BALLOON3_NAND_CONTROL_REG | BALLOON3_FPGA_SETnCLR);
+                BALLOON3_NAND_CONTROL_REG + BALLOON3_FPGA_SETnCLR);
        /* Deassert correct nCE line */
        __raw_writew(BALLOON3_NAND_CONTROL_FLCE0 << chip,
@@ -626,7 +626,7 @@ static int balloon3_nand_probe(struct platform_device *pdev)
        int ret;
        __raw_writew(BALLOON3_NAND_CONTROL2_16BIT,
-                BALLOON3_NAND_CONTROL2_REG | BALLOON3_FPGA_SETnCLR);
+                BALLOON3_NAND_CONTROL2_REG + BALLOON3_FPGA_SETnCLR);
        ver = __raw_readw(BALLOON3_FPGA_VER);
        if (ver < 0x4f08)
@@ -649,7 +649,7 @@ static int balloon3_nand_probe(struct platform_device *pdev)
                BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 |
                BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3 |
                BALLOON3_NAND_CONTROL_FLWP,
-                BALLOON3_NAND_CONTROL_REG | BALLOON3_FPGA_SETnCLR);
+                BALLOON3_NAND_CONTROL_REG + BALLOON3_FPGA_SETnCLR);
        return 0;
 err2:
@@ -807,7 +807,7 @@ static void __init balloon3_init(void)
 static struct map_desc balloon3_io_desc[] __initdata = {
        {       /* CPLD/FPGA */
-                .virtual        =  BALLOON3_FPGA_VIRT,
+                .virtual        = (unsigned long)BALLOON3_FPGA_VIRT,
                .pfn            = __phys_to_pfn(BALLOON3_FPGA_PHYS),
                .length         = BALLOON3_FPGA_LENGTH,
                .type           = MT_DEVICE,
diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.c b/arch/arm/mach-pxa/cm-x2xx-pci.c
index 6bf479d9b5ac..ebd9259f5ac9 100644
--- a/arch/arm/mach-pxa/cm-x2xx-pci.c
+++ b/arch/arm/mach-pxa/cm-x2xx-pci.c
@@ -26,7 +26,7 @@
 #include <asm/hardware/it8152.h>
-unsigned long it8152_base_address;
+void __iomem *it8152_base_address;
 static int cmx2xx_it8152_irq_gpio;
 static void cmx2xx_it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c
index 349896c53abd..f2e4190080cb 100644
--- a/arch/arm/mach-pxa/cm-x2xx.c
+++ b/arch/arm/mach-pxa/cm-x2xx.c
@@ -39,7 +39,7 @@ extern void cmx270_init(void);
 #define CMX2XX_NR_IRQS          (IRQ_BOARD_START + 40)
 /* virtual addresses for statically mapped regions */
-#define CMX2XX_VIRT_BASE        (0xe8000000)
+#define CMX2XX_VIRT_BASE        (void __iomem *)(0xe8000000)
 #define CMX2XX_IT8152_VIRT      (CMX2XX_VIRT_BASE)
 /* physical address if local-bus attached devices */
@@ -482,7 +482,7 @@ static void __init cmx2xx_init_irq(void)
 /* Map PCI companion statically */
 static struct map_desc cmx2xx_io_desc[] __initdata = {
        [0] = { /* PCI bridge */
-                .virtual        = CMX2XX_IT8152_VIRT,
+                .virtual        = (unsigned long)CMX2XX_IT8152_VIRT,
                .pfn            = __phys_to_pfn(PXA_CS4_PHYS),
                .length         = SZ_64M,
                .type           = MT_DEVICE
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index d2da301619f0..3a7387f93c38 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -775,7 +775,6 @@ static struct gpio cm_x300_wi2wi_gpios[] __initdata = {
 static void __init cm_x300_init_wi2wi(void)
 {
-        int bt_reset, wlan_en;
        int err;
        if (system_rev < 130) {
@@ -791,12 +790,11 @@ static void __init cm_x300_init_wi2wi(void)
        }
        udelay(10);
-        gpio_set_value(bt_reset, 0);
+        gpio_set_value(cm_x300_wi2wi_gpios[1].gpio, 0);
        udelay(10);
-        gpio_set_value(bt_reset, 1);
+        gpio_set_value(cm_x300_wi2wi_gpios[1].gpio, 1);
-        gpio_free(wlan_en);
+        gpio_free_array(ARRAY_AND_SIZE(cm_x300_wi2wi_gpios));
-        gpio_free(bt_reset);
 }
 /* MFP */
diff --git a/arch/arm/mach-pxa/include/mach/addr-map.h b/arch/arm/mach-pxa/include/mach/addr-map.h
index f4c03659168c..bbf9df37ad4b 100644
--- a/arch/arm/mach-pxa/include/mach/addr-map.h
+++ b/arch/arm/mach-pxa/include/mach/addr-map.h
@@ -20,7 +20,7 @@
 * Peripheral Bus
 */
 #define PERIPH_PHYS             0x40000000
-#define PERIPH_VIRT             0xf2000000
+#define PERIPH_VIRT             IOMEM(0xf2000000)
 #define PERIPH_SIZE             0x02000000
 /*
@@ -28,21 +28,21 @@
 */
 #define PXA2XX_SMEMC_PHYS       0x48000000
 #define PXA3XX_SMEMC_PHYS       0x4a000000
-#define SMEMC_VIRT              0xf6000000
+#define SMEMC_VIRT              IOMEM(0xf6000000)
 #define SMEMC_SIZE              0x00100000
 /*
 * Dynamic Memory Controller (only on PXA3xx)
 */
 #define DMEMC_PHYS              0x48100000
-#define DMEMC_VIRT              0xf6100000
+#define DMEMC_VIRT              IOMEM(0xf6100000)
 #define DMEMC_SIZE              0x00100000
 /*
 * Internal Memory Controller (PXA27x and later)
 */
 #define IMEMC_PHYS              0x58000000
-#define IMEMC_VIRT              0xfe000000
+#define IMEMC_VIRT              IOMEM(0xfe000000)
 #define IMEMC_SIZE              0x00100000
 #endif /* __ASM_MACH_ADDR_MAP_H */
diff --git a/arch/arm/mach-pxa/include/mach/balloon3.h b/arch/arm/mach-pxa/include/mach/balloon3.h
index 7074e76146c9..6d7eab3d0867 100644
--- a/arch/arm/mach-pxa/include/mach/balloon3.h
+++ b/arch/arm/mach-pxa/include/mach/balloon3.h
@@ -23,7 +23,7 @@ enum balloon3_features {
 };
 #define BALLOON3_FPGA_PHYS      PXA_CS4_PHYS
-#define BALLOON3_FPGA_VIRT      (0xf1000000)    /* as per balloon2 */
+#define BALLOON3_FPGA_VIRT      IOMEM(0xf1000000)       /* as per balloon2 */
 #define BALLOON3_FPGA_LENGTH    0x01000000
 #define BALLOON3_FPGA_SETnCLR           (0x1000)
diff --git a/arch/arm/mach-pxa/include/mach/gpio-pxa.h b/arch/arm/mach-pxa/include/mach/gpio-pxa.h
index 41b4c93a96c2..576868f8b8c5 100644
--- a/arch/arm/mach-pxa/include/mach/gpio-pxa.h
+++ b/arch/arm/mach-pxa/include/mach/gpio-pxa.h
@@ -25,7 +25,7 @@
 #define GPIO_REGS_VIRT  io_p2v(0x40E00000)
 #define BANK_OFF(n)     (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
-#define GPIO_REG(x)     (*(volatile u32 *)(GPIO_REGS_VIRT + (x)))
+#define GPIO_REG(x)     (GPIO_REGS_VIRT + (x))
 /* GPIO Pin Level Registers */
 #define GPLR0           GPIO_REG(BANK_OFF(0) + 0x00)
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
index de63ca3016b4..8184669dde28 100644
--- a/arch/arm/mach-pxa/include/mach/hardware.h
+++ b/arch/arm/mach-pxa/include/mach/hardware.h
@@ -36,22 +36,23 @@
 * Note that not all PXA2xx chips implement all those addresses, and the
 * kernel only maps the minimum needed range of this mapping.
 */
-#define io_p2v(x) (0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
 #define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
+#define io_p2v(x) IOMEM(0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
 #ifndef __ASSEMBLY__
+# define IOMEM(x) ((void __iomem *)(x))
-# define __REG(x)       (*((volatile u32 *)io_p2v(x)))
+# define __REG(x)       (*((volatile u32 __iomem *)io_p2v(x)))
 /* With indexed regs we don't want to feed the index through io_p2v()
   especially if it is a variable, otherwise horrible code will result. */
 # define __REG2(x,y)    \
-        (*(volatile u32 *)((u32)&__REG(x) + (y)))
+        (*(volatile u32 __iomem*)((u32)&__REG(x) + (y)))
 # define __PREG(x)      (io_v2p((u32)&(x)))
 #else
+# define IOMEM(x)       x 
 # define __REG(x)       io_p2v(x)
 # define __PREG(x)      io_v2p(x)
diff --git a/arch/arm/mach-pxa/include/mach/lpd270.h b/arch/arm/mach-pxa/include/mach/lpd270.h
index cd070092b6eb..4edc712a2de8 100644
--- a/arch/arm/mach-pxa/include/mach/lpd270.h
+++ b/arch/arm/mach-pxa/include/mach/lpd270.h
@@ -13,13 +13,13 @@
 #define __ASM_ARCH_LPD270_H
 #define LPD270_CPLD_PHYS        PXA_CS2_PHYS
-#define LPD270_CPLD_VIRT        0xf0000000
+#define LPD270_CPLD_VIRT        IOMEM(0xf0000000)
 #define LPD270_CPLD_SIZE        0x00100000
 #define LPD270_ETH_PHYS         (PXA_CS2_PHYS + 0x01000000)
 /* CPLD registers  */
-#define LPD270_CPLD_REG(x)      ((unsigned long)(LPD270_CPLD_VIRT + (x)))
+#define LPD270_CPLD_REG(x)      (LPD270_CPLD_VIRT + (x))
 #define LPD270_CONTROL          LPD270_CPLD_REG(0x00)
 #define LPD270_PERIPHERAL0      LPD270_CPLD_REG(0x04)
 #define LPD270_PERIPHERAL1      LPD270_CPLD_REG(0x08)
diff --git a/arch/arm/mach-pxa/include/mach/mtd-xip.h b/arch/arm/mach-pxa/include/mach/mtd-xip.h
index 297387ec3618..990d2bf2fb45 100644
--- a/arch/arm/mach-pxa/include/mach/mtd-xip.h
+++ b/arch/arm/mach-pxa/include/mach/mtd-xip.h
@@ -16,7 +16,6 @@
 #define __ARCH_PXA_MTD_XIP_H__
 #include <mach/regs-ost.h>
-#include <mach/regs-intc.h>
 #define xip_irqpending()        (ICIP & ICMR)
diff --git a/arch/arm/mach-pxa/include/mach/palm27x.h b/arch/arm/mach-pxa/include/mach/palm27x.h
index 0a5e5eadebf5..f80bbe246afe 100644
--- a/arch/arm/mach-pxa/include/mach/palm27x.h
+++ b/arch/arm/mach-pxa/include/mach/palm27x.h
@@ -34,7 +34,7 @@ extern struct pxafb_mode_info palm_320x320_new_lcd_mode;
 extern void __init palm27x_lcd_init(int power,
                                        struct pxafb_mode_info *mode);
 #else
-static inline void palm27x_lcd_init(int power, struct pxafb_mode_info *mode) {}
+#define palm27x_lcd_init(power, mode)   do {} while (0)
 #endif
 #if     defined(CONFIG_USB_GADGET_PXA27X) || \
diff --git a/arch/arm/mach-pxa/include/mach/palmtx.h b/arch/arm/mach-pxa/include/mach/palmtx.h
index 10abc4f2e8e4..7074a6ed46c6 100644
--- a/arch/arm/mach-pxa/include/mach/palmtx.h
+++ b/arch/arm/mach-pxa/include/mach/palmtx.h
@@ -71,7 +71,7 @@
 /* Various addresses  */
 #define PALMTX_PCMCIA_PHYS      0x28000000
-#define PALMTX_PCMCIA_VIRT      0xf0000000
+#define PALMTX_PCMCIA_VIRT      IOMEM(0xf0000000)
 #define PALMTX_PCMCIA_SIZE      0x100000
 #define PALMTX_PHYS_RAM_START   0xa0000000
@@ -84,8 +84,8 @@
 #define PALMTX_NAND_ALE_PHYS    (PALMTX_PHYS_NAND_START | (1 << 24))
 #define PALMTX_NAND_CLE_PHYS    (PALMTX_PHYS_NAND_START | (1 << 25))
-#define PALMTX_NAND_ALE_VIRT    0xff100000
+#define PALMTX_NAND_ALE_VIRT    IOMEM(0xff100000)
-#define PALMTX_NAND_CLE_VIRT    0xff200000
+#define PALMTX_NAND_CLE_VIRT    IOMEM(0xff200000)
 /* TOUCHSCREEN */
 #define AC97_LINK_FRAME                 21
diff --git a/arch/arm/mach-pxa/include/mach/pxa27x.h b/arch/arm/mach-pxa/include/mach/pxa27x.h
index b9b1bdc4bacc..7cff640582b8 100644
--- a/arch/arm/mach-pxa/include/mach/pxa27x.h
+++ b/arch/arm/mach-pxa/include/mach/pxa27x.h
@@ -1,6 +1,7 @@
 #ifndef __MACH_PXA27x_H
 #define __MACH_PXA27x_H
+#include <linux/suspend.h>
 #include <mach/hardware.h>
 #include <mach/pxa2xx-regs.h>
 #include <mach/mfp-pxa27x.h>
@@ -21,6 +22,7 @@
 extern void __init pxa27x_map_io(void);
 extern void __init pxa27x_init_irq(void);
 extern int __init pxa27x_set_pwrmode(unsigned int mode);
+extern void pxa27x_cpu_pm_enter(suspend_state_t state);
 #define pxa27x_handle_irq       ichp_handle_irq
diff --git a/arch/arm/mach-pxa/include/mach/pxa95x.h b/arch/arm/mach-pxa/include/mach/pxa95x.h
new file mode 100644
index 000000000000..cbb097c4cb1f
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/pxa95x.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_PXA95X_H
+#define __MACH_PXA95X_H
+#include <mach/pxa3xx.h>
+#include <mach/mfp-pxa930.h>
+#endif /* __MACH_PXA95X_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxafb.h b/arch/arm/mach-pxa/include/mach/pxafb.h
index 01a45ac48114..486b4c519ae2 100644
--- a/arch/arm/mach-pxa/include/mach/pxafb.h
+++ b/arch/arm/mach-pxa/include/mach/pxafb.h
@@ -158,5 +158,18 @@ struct pxafb_mach_info {
 void pxa_set_fb_info(struct device *, struct pxafb_mach_info *);
 unsigned long pxafb_get_hsync_time(struct device *dev);
+#ifdef CONFIG_FB_PXA_SMARTPANEL
 extern int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int);
 extern int pxafb_smart_flush(struct fb_info *info);
+#else
+static inline int pxafb_smart_queue(struct fb_info *info,
+                                    uint16_t *cmds, int n)
+{
+        return 0;
+}
+static inline int pxafb_smart_flush(struct fb_info *info)
+{
+        return 0;
+}
+#endif
diff --git a/arch/arm/mach-pxa/include/mach/smemc.h b/arch/arm/mach-pxa/include/mach/smemc.h
index 654adc90c9a0..b7de471b273a 100644
--- a/arch/arm/mach-pxa/include/mach/smemc.h
+++ b/arch/arm/mach-pxa/include/mach/smemc.h
@@ -13,7 +13,7 @@
 #define PXA2XX_SMEMC_BASE       0x48000000
 #define PXA3XX_SMEMC_BASE       0x4a000000
-#define SMEMC_VIRT              0xf6000000
+#define SMEMC_VIRT              IOMEM(0xf6000000)
 #define MDCNFG          (SMEMC_VIRT + 0x00)  /* SDRAM Configuration Register 0 */
 #define MDREFR          (SMEMC_VIRT + 0x04)  /* SDRAM Refresh Control Register */
diff --git a/arch/arm/mach-pxa/include/mach/zeus.h b/arch/arm/mach-pxa/include/mach/zeus.h
index 0641f31a56b7..56024f81d57e 100644
--- a/arch/arm/mach-pxa/include/mach/zeus.h
+++ b/arch/arm/mach-pxa/include/mach/zeus.h
@@ -68,7 +68,7 @@
 * Be gentle, and remap that over 32kB...
 */
-#define ZEUS_CPLD               (0xf0000000)
+#define ZEUS_CPLD               IOMEM(0xf0000000)
 #define ZEUS_CPLD_VERSION       (ZEUS_CPLD + 0x0000)
 #define ZEUS_CPLD_ISA_IRQ       (ZEUS_CPLD + 0x1000)
 #define ZEUS_CPLD_CONTROL       (ZEUS_CPLD + 0x2000)
@@ -76,7 +76,7 @@
 /* CPLD register bits */
 #define ZEUS_CPLD_CONTROL_CF_RST        0x01
-#define ZEUS_PC104IO            (0xf1000000)
+#define ZEUS_PC104IO            IOMEM(0xf1000000)
 #define ZEUS_SRAM_SIZE          (256 * 1024)
diff --git a/arch/arm/mach-pxa/include/mach/zylonite.h b/arch/arm/mach-pxa/include/mach/zylonite.h
index ea24998b923c..ecca976f03d2 100644
--- a/arch/arm/mach-pxa/include/mach/zylonite.h
+++ b/arch/arm/mach-pxa/include/mach/zylonite.h
@@ -19,7 +19,7 @@ extern int wm9713_irq;
 extern int lcd_id;
 extern int lcd_orientation;
-#ifdef CONFIG_CPU_PXA300
+#ifdef CONFIG_MACH_ZYLONITE300
 extern void zylonite_pxa300_init(void);
 #else
 static inline void zylonite_pxa300_init(void)
@@ -29,7 +29,7 @@ static inline void zylonite_pxa300_init(void)
 }
 #endif
-#ifdef CONFIG_CPU_PXA320
+#ifdef CONFIG_MACH_ZYLONITE320
 extern void zylonite_pxa320_init(void);
 #else
 static inline void zylonite_pxa320_init(void)
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 8d9200f92268..532c5d3a97d2 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -26,7 +26,7 @@
 #include "generic.h"
-#define IRQ_BASE                (void __iomem *)io_p2v(0x40d00000)
+#define IRQ_BASE                io_p2v(0x40d00000)
 #define ICIP                    (0x000)
 #define ICMR                    (0x004)
@@ -64,7 +64,7 @@ static inline void __iomem *irq_base(int i)
                0x40d00130,
        };
-        return (void __iomem *)io_p2v(phys_base[i]);
+        return io_p2v(phys_base[i]);
 }
 void pxa_mask_irq(struct irq_data *d)
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index 64540d908958..1dd530279e0b 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -479,7 +479,7 @@ static void __init lpd270_init(void)
 static struct map_desc lpd270_io_desc[] __initdata = {
        {
-                .virtual        = LPD270_CPLD_VIRT,
+                .virtual        = (unsigned long)LPD270_CPLD_VIRT,
                .pfn            = __phys_to_pfn(LPD270_CPLD_PHYS),
                .length         = LPD270_CPLD_SIZE,
                .type           = MT_DEVICE,
diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c
index 7346fbfa8101..94e9708b349d 100644
--- a/arch/arm/mach-pxa/palmtreo.c
+++ b/arch/arm/mach-pxa/palmtreo.c
@@ -423,6 +423,7 @@ static void __init palmphone_common_init(void)
        palmtreo_leds_init();
 }
+#ifdef CONFIG_MACH_TREO680
 static void __init treo680_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(treo680_pin_config));
@@ -430,7 +431,9 @@ static void __init treo680_init(void)
        palm27x_mmc_init(GPIO_NR_TREO_SD_DETECT_N, GPIO_NR_TREO680_SD_READONLY,
                        GPIO_NR_TREO680_SD_POWER, 0);
 }
+#endif
+#ifdef CONFIG_MACH_CENTRO
 static void __init centro_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(centro685_pin_config));
@@ -438,7 +441,9 @@ static void __init centro_init(void)
        palm27x_mmc_init(GPIO_NR_TREO_SD_DETECT_N, -1,
                        GPIO_NR_CENTRO_SD_POWER, 1);
 }
+#endif
+#ifdef CONFIG_MACH_TREO680
 MACHINE_START(TREO680, "Palm Treo 680")
        .atag_offset    = 0x100,
        .map_io         = pxa27x_map_io,
@@ -448,7 +453,9 @@ MACHINE_START(TREO680, "Palm Treo 680")
        .timer          = &pxa_timer,
        .init_machine   = treo680_init,
 MACHINE_END
+#endif
+#ifdef CONFIG_MACH_CENTRO
 MACHINE_START(CENTRO, "Palm Centro 685")
        .atag_offset    = 0x100,
        .map_io         = pxa27x_map_io,
@@ -458,3 +465,4 @@ MACHINE_START(CENTRO, "Palm Centro 685")
        .timer          = &pxa_timer,
        .init_machine   = centro_init,
 MACHINE_END
+#endif
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
index 2b9e76fc2c90..4e3e45927e95 100644
--- a/arch/arm/mach-pxa/palmtx.c
+++ b/arch/arm/mach-pxa/palmtx.c
@@ -247,7 +247,7 @@ static void palmtx_nand_cmd_ctl(struct mtd_info *mtd, int cmd,
                                 unsigned int ctrl)
 {
        struct nand_chip *this = mtd->priv;
-        unsigned long nandaddr = (unsigned long)this->IO_ADDR_W;
+        char __iomem *nandaddr = this->IO_ADDR_W;
        if (cmd == NAND_CMD_NONE)
                return;
@@ -315,17 +315,17 @@ static inline void palmtx_nand_init(void) {}
 ******************************************************************************/
 static struct map_desc palmtx_io_desc[] __initdata = {
 {
-        .virtual        = PALMTX_PCMCIA_VIRT,
+        .virtual        = (unsigned long)PALMTX_PCMCIA_VIRT,
        .pfn            = __phys_to_pfn(PALMTX_PCMCIA_PHYS),
        .length         = PALMTX_PCMCIA_SIZE,
        .type           = MT_DEVICE,
 }, {
-        .virtual        = PALMTX_NAND_ALE_VIRT,
+        .virtual        = (unsigned long)PALMTX_NAND_ALE_VIRT,
        .pfn            = __phys_to_pfn(PALMTX_NAND_ALE_PHYS),
        .length         = SZ_1M,
        .type           = MT_DEVICE,
 }, {
-        .virtual        = PALMTX_NAND_CLE_VIRT,
+        .virtual        = (unsigned long)PALMTX_NAND_CLE_VIRT,
        .pfn            = __phys_to_pfn(PALMTX_NAND_CLE_PHYS),
        .length         = SZ_1M,
        .type           = MT_DEVICE,
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 8746e1090b6e..f05f9486b0cb 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -325,7 +325,7 @@ void __init pxa26x_init_irq(void)
 static struct map_desc pxa25x_io_desc[] __initdata = {
        {       /* Mem Ctl */
-                .virtual        = SMEMC_VIRT,
+                .virtual        = (unsigned long)SMEMC_VIRT,
                .pfn            = __phys_to_pfn(PXA2XX_SMEMC_BASE),
                .length         = 0x00200000,
                .type           = MT_DEVICE
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 2bb5cf8ba6ec..bc5a98ebaa72 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -391,7 +391,7 @@ void __init pxa27x_init_irq(void)
 static struct map_desc pxa27x_io_desc[] __initdata = {
        {       /* Mem Ctl */
-                .virtual        = SMEMC_VIRT,
+                .virtual        = (unsigned long)SMEMC_VIRT,
                .pfn            = __phys_to_pfn(PXA2XX_SMEMC_BASE),
                .length         = 0x00200000,
                .type           = MT_DEVICE
diff --git a/arch/arm/mach-pxa/pxa3xx-ulpi.c b/arch/arm/mach-pxa/pxa3xx-ulpi.c
index ce7168b233e2..e28dfb88827f 100644
--- a/arch/arm/mach-pxa/pxa3xx-ulpi.c
+++ b/arch/arm/mach-pxa/pxa3xx-ulpi.c
@@ -265,6 +265,7 @@ int pxa3xx_u2d_start_hc(struct usb_bus *host)
        return err;
 }
+EXPORT_SYMBOL_GPL(pxa3xx_u2d_start_hc);
 void pxa3xx_u2d_stop_hc(struct usb_bus *host)
 {
@@ -277,6 +278,7 @@ void pxa3xx_u2d_stop_hc(struct usb_bus *host)
        clk_disable(u2d->clk);
 }
+EXPORT_SYMBOL_GPL(pxa3xx_u2d_stop_hc);
 static int pxa3xx_u2d_probe(struct platform_device *pdev)
 {
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index f940a1345531..0737c59b88ae 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -393,7 +393,7 @@ void __init pxa3xx_init_irq(void)
 static struct map_desc pxa3xx_io_desc[] __initdata = {
        {       /* Mem Ctl */
-                .virtual        = SMEMC_VIRT,
+                .virtual        = (unsigned long)SMEMC_VIRT,
                .pfn            = __phys_to_pfn(PXA3XX_SMEMC_BASE),
                .length         = 0x00200000,
                .type           = MT_DEVICE
diff --git a/arch/arm/mach-pxa/saarb.c b/arch/arm/mach-pxa/saarb.c
index 3c988b6f718f..3e999e308a2d 100644
--- a/arch/arm/mach-pxa/saarb.c
+++ b/arch/arm/mach-pxa/saarb.c
@@ -24,6 +24,7 @@
 #include <mach/hardware.h>
 #include <mach/mfp.h>
 #include <mach/mfp-pxa930.h>
+#include <mach/pxa95x.h>
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
index 84ed72de53b5..ead32c90fec1 100644
--- a/arch/arm/mach-pxa/z2.c
+++ b/arch/arm/mach-pxa/z2.c
@@ -686,7 +686,8 @@ static void z2_power_off(void)
         */
        PSPR = 0x0;
        local_irq_disable();
-        pxa27x_cpu_suspend(PWRMODE_DEEPSLEEP, PHYS_OFFSET - PAGE_OFFSET);
+        pxa27x_set_pwrmode(PWRMODE_DEEPSLEEP);
+        pxa27x_cpu_pm_enter(PM_SUSPEND_MEM);
 }
 #else
 #define z2_power_off   NULL
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index c424e7d85ce3..498b83b089f3 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -860,25 +860,25 @@ static void __init zeus_init(void)
 static struct map_desc zeus_io_desc[] __initdata = {
        {
-                .virtual = ZEUS_CPLD_VERSION,
+                .virtual = (unsigned long)ZEUS_CPLD_VERSION,
                .pfn     = __phys_to_pfn(ZEUS_CPLD_VERSION_PHYS),
                .length  = 0x1000,
                .type    = MT_DEVICE,
        },
        {
-                .virtual = ZEUS_CPLD_ISA_IRQ,
+                .virtual = (unsigned long)ZEUS_CPLD_ISA_IRQ,
                .pfn     = __phys_to_pfn(ZEUS_CPLD_ISA_IRQ_PHYS),
                .length  = 0x1000,
                .type    = MT_DEVICE,
        },
        {
-                .virtual = ZEUS_CPLD_CONTROL,
+                .virtual = (unsigned long)ZEUS_CPLD_CONTROL,
                .pfn     = __phys_to_pfn(ZEUS_CPLD_CONTROL_PHYS),
                .length  = 0x1000,
                .type    = MT_DEVICE,
        },
        {
-                .virtual = ZEUS_PC104IO,
+                .virtual = (unsigned long)ZEUS_PC104IO,
                .pfn     = __phys_to_pfn(ZEUS_PC104IO_PHYS),
                .length  = 0x00800000,
                .type    = MT_DEVICE,
diff --git a/arch/arm/mach-realview/hotplug.c b/arch/arm/mach-realview/hotplug.c
index a87523d095e6..ac1aed2a8da4 100644
--- a/arch/arm/mach-realview/hotplug.c
+++ b/arch/arm/mach-realview/hotplug.c
@@ -69,7 +69,7 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
                    :
                    : "memory", "cc");
-                if (pen_release == cpu) {
+                if (pen_release == cpu_logical_map(cpu)) {
                        /*
                         * OK, proper wakeup, we're done
                         */
diff --git a/arch/arm/mach-realview/include/mach/debug-macro.S b/arch/arm/mach-realview/include/mach/debug-macro.S
index fb4901c4ef04..8cc372dc66a8 100644
--- a/arch/arm/mach-realview/include/mach/debug-macro.S
+++ b/arch/arm/mach-realview/include/mach/debug-macro.S
@@ -10,23 +10,10 @@
 * published by the Free Software Foundation.
 */
-#if defined(CONFIG_MACH_REALVIEW_EB) || \
+#ifdef CONFIG_DEBUG_REALVIEW_STD_PORT
-    defined(CONFIG_MACH_REALVIEW_PB11MP) || \
-    defined(CONFIG_MACH_REALVIEW_PBA8) || \
-    defined(CONFIG_MACH_REALVIEW_PBX)
-#ifndef DEBUG_LL_UART_OFFSET
 #define DEBUG_LL_UART_OFFSET    0x00009000
-#elif DEBUG_LL_UART_OFFSET != 0x00009000
+#elif defined(CONFIG_DEBUG_REALVIEW_PB1176_PORT)
-#warning "DEBUG_LL_UART_OFFSET already defined to a different value"
-#endif
-#endif
-#ifdef CONFIG_MACH_REALVIEW_PB1176
-#ifndef DEBUG_LL_UART_OFFSET
 #define DEBUG_LL_UART_OFFSET    0x0010c000
-#elif DEBUG_LL_UART_OFFSET != 0x0010c000
-#warning "DEBUG_LL_UART_OFFSET already defined to a different value"
-#endif
 #endif
 #ifndef DEBUG_LL_UART_OFFSET
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index 7245a55795dc..3700cf32af0f 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -8,7 +8,6 @@ config CPU_S3C2410
        select CPU_ARM920T
        select S3C_GPIO_PULL_UP
        select S3C2410_CLOCK
-        select S3C2410_GPIO
        select CPU_LLSERIAL_S3C2410
        select S3C2410_PM if PM
        select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX
@@ -28,11 +27,6 @@ config S3C2410_PM
        help
          Power Management code common to S3C2410 and better
-config S3C2410_GPIO
-        bool
-        help
-          GPIO code for S3C2410 and similar processors
 config SIMTEC_NOR
        bool
        help
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile
index 81695353d8f4..782fd81144e9 100644
--- a/arch/arm/mach-s3c2410/Makefile
+++ b/arch/arm/mach-s3c2410/Makefile
@@ -13,7 +13,6 @@ obj-$(CONFIG_CPU_S3C2410)	+= s3c2410.o
 obj-$(CONFIG_CPU_S3C2410_DMA)   += dma.o
 obj-$(CONFIG_CPU_S3C2410_DMA)   += dma.o
 obj-$(CONFIG_S3C2410_PM)        += pm.o sleep.o
-obj-$(CONFIG_S3C2410_GPIO)      += gpio.o
 obj-$(CONFIG_S3C2410_CPUFREQ)   += cpu-freq.o
 obj-$(CONFIG_S3C2410_PLLTABLE)  += pll.o
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c
index 0d8e043804c2..dbe43df8cfec 100644
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c2410/dma.c
@@ -47,38 +47,26 @@ static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
                .channels[0]    = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
                .channels[2]    = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
                .channels[3]    = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_IIS + S3C2410_IISFIFO,
-                .hw_addr.from   = S3C2410_PA_IIS + S3C2410_IISFIFO,
        },
        [DMACH_SPI0] = {
                .name           = "spi0",
                .channels[1]    = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_SPI + S3C2410_SPTDAT,
-                .hw_addr.from   = S3C2410_PA_SPI + S3C2410_SPRDAT,
        },
        [DMACH_SPI1] = {
                .name           = "spi1",
                .channels[3]    = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
-                .hw_addr.from   = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
        },
        [DMACH_UART0] = {
                .name           = "uart0",
                .channels[0]    = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_UART0 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART0 + S3C2410_URXH,
        },
        [DMACH_UART1] = {
                .name           = "uart1",
                .channels[1]    = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_UART1 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART1 + S3C2410_URXH,
        },
        [DMACH_UART2] = {
                .name           = "uart2",
                .channels[3]    = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_UART2 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART2 + S3C2410_URXH,
        },
        [DMACH_TIMER] = {
                .name           = "timer",
@@ -90,12 +78,10 @@ static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
                .name           = "i2s-sdi",
                .channels[1]    = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
                .channels[2]    = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
-                .hw_addr.from   = S3C2410_PA_IIS + S3C2410_IISFIFO,
        },
        [DMACH_I2S_OUT] = {
                .name           = "i2s-sdo",
                .channels[2]    = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_IIS + S3C2410_IISFIFO,
        },
        [DMACH_USB_EP1] = {
                .name           = "usb-ep1",
diff --git a/arch/arm/mach-s3c2410/gpio.c b/arch/arm/mach-s3c2410/gpio.c
deleted file mode 100644
index 9664e011dae2..000000000000
--- a/arch/arm/mach-s3c2410/gpio.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/* linux/arch/arm/mach-s3c2410/gpio.c
- *
- * Copyright (c) 2004-2006 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 GPIO support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/gpio-fns.h>
-#include <asm/irq.h>
-#include <mach/regs-gpio.h>
-int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
-                           unsigned int config)
-{
-        void __iomem *reg = S3C24XX_EINFLT0;
-        unsigned long flags;
-        unsigned long val;
-        if (pin < S3C2410_GPG(8) || pin > S3C2410_GPG(15))
-                return -EINVAL;
-        config &= 0xff;
-        pin -= S3C2410_GPG(8);
-        reg += pin & ~3;
-        local_irq_save(flags);
-        /* update filter width and clock source */
-        val = __raw_readl(reg);
-        val &= ~(0xff << ((pin & 3) * 8));
-        val |= config << ((pin & 3) * 8);
-        __raw_writel(val, reg);
-        /* update filter enable */
-        val = __raw_readl(S3C24XX_EXTINT2);
-        val &= ~(1 << ((pin * 4) + 3));
-        val |= on << ((pin * 4) + 3);
-        __raw_writel(val, S3C24XX_EXTINT2);
-        local_irq_restore(flags);
-        return 0;
-}
-EXPORT_SYMBOL(s3c2410_gpio_irqfilter);
diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h
index 425552d84b60..4cf495f813a7 100644
--- a/arch/arm/mach-s3c2410/include/mach/map.h
+++ b/arch/arm/mach-s3c2410/include/mach/map.h
@@ -14,9 +14,53 @@
 #define __ASM_ARCH_MAP_H
 #include <plat/map-base.h>
-#include <plat/map.h>
-#define S3C2410_ADDR(x)         S3C_ADDR(x)
+/*
+ * S3C2410 UART offset is 0x4000 but the other SoCs are 0x400.
+ * So need to define it, and here is to avoid redefinition warning.
+ */
+#define S3C_UART_OFFSET         (0x4000)
+#include <plat/map-s3c.h>
+/*
+ * interrupt controller is the first thing we put in, to make
+ * the assembly code for the irq detection easier
+ */
+#define S3C2410_PA_IRQ          (0x4A000000)
+#define S3C24XX_SZ_IRQ          SZ_1M
+/* memory controller registers */
+#define S3C2410_PA_MEMCTRL      (0x48000000)
+#define S3C24XX_SZ_MEMCTRL      SZ_1M
+/* UARTs */
+#define S3C_VA_UARTx(uart)      (S3C_VA_UART + ((uart * S3C_UART_OFFSET)))
+/* Timers */
+#define S3C2410_PA_TIMER        (0x51000000)
+#define S3C24XX_SZ_TIMER        SZ_1M
+/* Clock and Power management */
+#define S3C24XX_SZ_CLKPWR       SZ_1M
+/* USB Device port */
+#define S3C2410_PA_USBDEV       (0x52000000)
+#define S3C24XX_SZ_USBDEV       SZ_1M
+/* Watchdog */
+#define S3C2410_PA_WATCHDOG     (0x53000000)
+#define S3C24XX_SZ_WATCHDOG     SZ_1M
+/* Standard size definitions for peripheral blocks. */
+#define S3C24XX_SZ_UART         SZ_1M
+#define S3C24XX_SZ_IIS          SZ_1M
+#define S3C24XX_SZ_ADC          SZ_1M
+#define S3C24XX_SZ_SPI          SZ_1M
+#define S3C24XX_SZ_SDI          SZ_1M
+#define S3C24XX_SZ_NAND         SZ_1M
+#define S3C24XX_SZ_GPIO         SZ_1M
 /* USB host controller */
 #define S3C2410_PA_USBHOST (0x49000000)
@@ -75,10 +119,8 @@
 /* S3C2412 memory and IO controls */
 #define S3C2412_PA_SSMC (0x4F000000)
-#define S3C2412_VA_SSMC S3C_ADDR_CPU(0x00000000)
 #define S3C2412_PA_EBI  (0x48800000)
-#define S3C2412_VA_EBI  S3C_ADDR_CPU(0x00010000)
 /* physical addresses of all the chip-select areas */
@@ -100,12 +142,10 @@
 #define S3C24XX_PA_DMA      S3C2410_PA_DMA
 #define S3C24XX_PA_CLKPWR   S3C2410_PA_CLKPWR
 #define S3C24XX_PA_LCD      S3C2410_PA_LCD
-#define S3C24XX_PA_UART     S3C2410_PA_UART
 #define S3C24XX_PA_TIMER    S3C2410_PA_TIMER
 #define S3C24XX_PA_USBDEV   S3C2410_PA_USBDEV
 #define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
 #define S3C24XX_PA_IIS      S3C2410_PA_IIS
-#define S3C24XX_PA_GPIO     S3C2410_PA_GPIO
 #define S3C24XX_PA_RTC      S3C2410_PA_RTC
 #define S3C24XX_PA_ADC      S3C2410_PA_ADC
 #define S3C24XX_PA_SPI      S3C2410_PA_SPI
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
index c2cf4e569989..b8b9029e9f2d 100644
--- a/arch/arm/mach-s3c2412/Kconfig
+++ b/arch/arm/mach-s3c2412/Kconfig
@@ -9,7 +9,6 @@ config CPU_S3C2412
        select CPU_LLSERIAL_S3C2440
        select S3C2412_PM if PM
        select S3C2412_DMA if S3C2410_DMA
-        select S3C2410_GPIO
        help
          Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line
diff --git a/arch/arm/mach-s3c2412/Makefile b/arch/arm/mach-s3c2412/Makefile
index 6c48a91ea39e..7e4d95fa8a97 100644
--- a/arch/arm/mach-s3c2412/Makefile
+++ b/arch/arm/mach-s3c2412/Makefile
@@ -12,7 +12,6 @@ obj-				:=
 obj-$(CONFIG_CPU_S3C2412)       += s3c2412.o
 obj-$(CONFIG_CPU_S3C2412)       += irq.o
 obj-$(CONFIG_CPU_S3C2412)       += clock.o
-obj-$(CONFIG_CPU_S3C2412)       += gpio.o
 obj-$(CONFIG_S3C2412_DMA)       += dma.o
 obj-$(CONFIG_S3C2412_PM)        += pm.o
 obj-$(CONFIG_S3C2412_PM_SLEEP)  += sleep.o
diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c
index 7abecfca0b7e..c61e3261615d 100644
--- a/arch/arm/mach-s3c2412/dma.c
+++ b/arch/arm/mach-s3c2412/dma.c
@@ -50,64 +50,46 @@ static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
                .name           = "sdi",
                .channels       = MAP(S3C2412_DMAREQSEL_SDI),
                .channels_rx    = MAP(S3C2412_DMAREQSEL_SDI),
-                .hw_addr.to     = S3C2410_PA_SDI + S3C2410_SDIDATA,
-                .hw_addr.from   = S3C2410_PA_SDI + S3C2410_SDIDATA,
        },
        [DMACH_SPI0] = {
                .name           = "spi0",
                .channels       = MAP(S3C2412_DMAREQSEL_SPI0TX),
                .channels_rx    = MAP(S3C2412_DMAREQSEL_SPI0RX),
-                .hw_addr.to     = S3C2410_PA_SPI + S3C2410_SPTDAT,
-                .hw_addr.from   = S3C2410_PA_SPI + S3C2410_SPRDAT,
        },
        [DMACH_SPI1] = {
                .name           = "spi1",
                .channels       = MAP(S3C2412_DMAREQSEL_SPI1TX),
                .channels_rx    = MAP(S3C2412_DMAREQSEL_SPI1RX),
-                .hw_addr.to     = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPTDAT,
-                .hw_addr.from   = S3C2410_PA_SPI + S3C2412_SPI1  + S3C2410_SPRDAT,
        },
        [DMACH_UART0] = {
                .name           = "uart0",
                .channels       = MAP(S3C2412_DMAREQSEL_UART0_0),
                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART0_0),
-                .hw_addr.to     = S3C2410_PA_UART0 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART0 + S3C2410_URXH,
        },
        [DMACH_UART1] = {
                .name           = "uart1",
                .channels       = MAP(S3C2412_DMAREQSEL_UART1_0),
                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART1_0),
-                .hw_addr.to     = S3C2410_PA_UART1 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART1 + S3C2410_URXH,
        },
        [DMACH_UART2] = {
                .name           = "uart2",
                .channels       = MAP(S3C2412_DMAREQSEL_UART2_0),
                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART2_0),
-                .hw_addr.to     = S3C2410_PA_UART2 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART2 + S3C2410_URXH,
        },
        [DMACH_UART0_SRC2] = {
                .name           = "uart0",
                .channels       = MAP(S3C2412_DMAREQSEL_UART0_1),
                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART0_1),
-                .hw_addr.to     = S3C2410_PA_UART0 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART0 + S3C2410_URXH,
        },
        [DMACH_UART1_SRC2] = {
                .name           = "uart1",
                .channels       = MAP(S3C2412_DMAREQSEL_UART1_1),
                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART1_1),
-                .hw_addr.to     = S3C2410_PA_UART1 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART1 + S3C2410_URXH,
        },
        [DMACH_UART2_SRC2] = {
                .name           = "uart2",
                .channels       = MAP(S3C2412_DMAREQSEL_UART2_1),
                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART2_1),
-                .hw_addr.to     = S3C2410_PA_UART2 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART2 + S3C2410_URXH,
        },
        [DMACH_TIMER] = {
                .name           = "timer",
diff --git a/arch/arm/mach-s3c2412/gpio.c b/arch/arm/mach-s3c2412/gpio.c
deleted file mode 100644
index 3404a876b33e..000000000000
--- a/arch/arm/mach-s3c2412/gpio.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* linux/arch/arm/mach-s3c2412/gpio.c
- *
- * Copyright (c) 2007 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * http://armlinux.simtec.co.uk/.
- *
- * S3C2412/S3C2413 specific GPIO support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <mach/regs-gpio.h>
-#include <mach/hardware.h>
-#include <plat/gpio-core.h>
-int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state)
-{
-        struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
-        unsigned long offs = pin - chip->chip.base;
-        unsigned long flags;
-        unsigned long slpcon;
-        offs *= 2;
-        if (pin < S3C2410_GPB(0))
-                return -EINVAL;
-        if (pin >= S3C2410_GPF(0) &&
-            pin <= S3C2410_GPG(16))
-                return -EINVAL;
-        if (pin > S3C2410_GPH(16))
-                return -EINVAL;
-        local_irq_save(flags);
-        slpcon = __raw_readl(chip->base + 0x0C);
-        slpcon &= ~(3 << offs);
-        slpcon |= state << offs;
-        __raw_writel(slpcon, chip->base + 0x0C);
-        local_irq_restore(flags);
-        return 0;
-}
-EXPORT_SYMBOL(s3c2412_gpio_set_sleepcfg);
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
index 50825a3f91cc..c461fb8e15c0 100644
--- a/arch/arm/mach-s3c2440/Kconfig
+++ b/arch/arm/mach-s3c2440/Kconfig
@@ -8,7 +8,6 @@ config CPU_S3C2440
        select S3C_GPIO_PULL_UP
        select S3C2410_CLOCK
        select S3C2410_PM if PM
-        select S3C2410_GPIO
        select S3C2440_DMA if S3C2410_DMA
        select CPU_S3C244X
        select CPU_LLSERIAL_S3C2440
@@ -20,7 +19,6 @@ config CPU_S3C2442
        select CPU_ARM920T
        select S3C_GPIO_PULL_DOWN
        select S3C2410_CLOCK
-        select S3C2410_GPIO
        select S3C2410_PM if PM
        select CPU_S3C244X
        select CPU_LLSERIAL_S3C2440
diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c2440/dma.c
index 3b0529f54e9c..0e73f8f9d132 100644
--- a/arch/arm/mach-s3c2440/dma.c
+++ b/arch/arm/mach-s3c2440/dma.c
@@ -48,38 +48,26 @@ static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
                .channels[1]    = S3C2440_DCON_CH1_SDI | DMA_CH_VALID,
                .channels[2]    = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
                .channels[3]    = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_IIS + S3C2410_IISFIFO,
-                .hw_addr.from   = S3C2410_PA_IIS + S3C2410_IISFIFO,
        },
        [DMACH_SPI0] = {
                .name           = "spi0",
                .channels[1]    = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_SPI + S3C2410_SPTDAT,
-                .hw_addr.from   = S3C2410_PA_SPI + S3C2410_SPRDAT,
        },
        [DMACH_SPI1] = {
                .name           = "spi1",
                .channels[3]    = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
-                .hw_addr.from   = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
        },
        [DMACH_UART0] = {
                .name           = "uart0",
                .channels[0]    = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_UART0 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART0 + S3C2410_URXH,
        },
        [DMACH_UART1] = {
                .name           = "uart1",
                .channels[1]    = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_UART1 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART1 + S3C2410_URXH,
        },
        [DMACH_UART2] = {
                .name           = "uart2",
                .channels[3]    = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_UART2 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART2 + S3C2410_URXH,
        },
        [DMACH_TIMER] = {
                .name           = "timer",
@@ -91,31 +79,26 @@ static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
                .name           = "i2s-sdi",
                .channels[1]    = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
                .channels[2]    = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
-                .hw_addr.from   = S3C2410_PA_IIS + S3C2410_IISFIFO,
        },
        [DMACH_I2S_OUT] = {
                .name           = "i2s-sdo",
                .channels[0]    = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID,
                .channels[2]    = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_IIS + S3C2410_IISFIFO,
        },
        [DMACH_PCM_IN] = {
                .name           = "pcm-in",
                .channels[0]    = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID,
                .channels[2]    = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID,
-                .hw_addr.from   = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
        },
        [DMACH_PCM_OUT] = {
                .name           = "pcm-out",
                .channels[1]    = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID,
                .channels[3]    = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID,
-                .hw_addr.to     = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
        },
        [DMACH_MIC_IN] = {
                .name           = "mic-in",
                .channels[2]    = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID,
                .channels[3]    = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID,
-                .hw_addr.from   = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
        },
        [DMACH_USB_EP1] = {
                .name           = "usb-ep1",
diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c2443/dma.c
index 3f658685ec16..fe52151d2e84 100644
--- a/arch/arm/mach-s3c2443/dma.c
+++ b/arch/arm/mach-s3c2443/dma.c
@@ -54,68 +54,46 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
        [DMACH_SDI] = {
                .name           = "sdi",
                .channels       = MAP(S3C2443_DMAREQSEL_SDI),
-                .hw_addr.to     = S3C2410_PA_IIS + S3C2410_IISFIFO,
-                .hw_addr.from   = S3C2410_PA_IIS + S3C2410_IISFIFO,
        },
        [DMACH_SPI0] = {
                .name           = "spi0",
                .channels       = MAP(S3C2443_DMAREQSEL_SPI0TX),
-                .hw_addr.to     = S3C2410_PA_SPI + S3C2410_SPTDAT,
-                .hw_addr.from   = S3C2410_PA_SPI + S3C2410_SPRDAT,
        },
        [DMACH_SPI1] = {
                .name           = "spi1",
                .channels       = MAP(S3C2443_DMAREQSEL_SPI1TX),
-                .hw_addr.to     = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
-                .hw_addr.from   = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
        },
        [DMACH_UART0] = {
                .name           = "uart0",
                .channels       = MAP(S3C2443_DMAREQSEL_UART0_0),
-                .hw_addr.to     = S3C2410_PA_UART0 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART0 + S3C2410_URXH,
        },
        [DMACH_UART1] = {
                .name           = "uart1",
                .channels       = MAP(S3C2443_DMAREQSEL_UART1_0),
-                .hw_addr.to     = S3C2410_PA_UART1 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART1 + S3C2410_URXH,
        },
        [DMACH_UART2] = {
                .name           = "uart2",
                .channels       = MAP(S3C2443_DMAREQSEL_UART2_0),
-                .hw_addr.to     = S3C2410_PA_UART2 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART2 + S3C2410_URXH,
        },
        [DMACH_UART3] = {
                .name           = "uart3",
                .channels       = MAP(S3C2443_DMAREQSEL_UART3_0),
-                .hw_addr.to     = S3C2443_PA_UART3 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2443_PA_UART3 + S3C2410_URXH,
        },
        [DMACH_UART0_SRC2] = {
                .name           = "uart0",
                .channels       = MAP(S3C2443_DMAREQSEL_UART0_1),
-                .hw_addr.to     = S3C2410_PA_UART0 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART0 + S3C2410_URXH,
        },
        [DMACH_UART1_SRC2] = {
                .name           = "uart1",
                .channels       = MAP(S3C2443_DMAREQSEL_UART1_1),
-                .hw_addr.to     = S3C2410_PA_UART1 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART1 + S3C2410_URXH,
        },
        [DMACH_UART2_SRC2] = {
                .name           = "uart2",
                .channels       = MAP(S3C2443_DMAREQSEL_UART2_1),
-                .hw_addr.to     = S3C2410_PA_UART2 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART2 + S3C2410_URXH,
        },
        [DMACH_UART3_SRC2] = {
                .name           = "uart3",
                .channels       = MAP(S3C2443_DMAREQSEL_UART3_1),
-                .hw_addr.to     = S3C2443_PA_UART3 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2443_PA_UART3 + S3C2410_URXH,
        },
        [DMACH_TIMER] = {
                .name           = "timer",
@@ -124,27 +102,22 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
        [DMACH_I2S_IN] = {
                .name           = "i2s-sdi",
                .channels       = MAP(S3C2443_DMAREQSEL_I2SRX),
-                .hw_addr.from   = S3C2410_PA_IIS + S3C2410_IISFIFO,
        },
        [DMACH_I2S_OUT] = {
                .name           = "i2s-sdo",
                .channels       = MAP(S3C2443_DMAREQSEL_I2STX),
-                .hw_addr.to     = S3C2410_PA_IIS + S3C2410_IISFIFO,
        },
        [DMACH_PCM_IN] = {
                .name           = "pcm-in",
                .channels       = MAP(S3C2443_DMAREQSEL_PCMIN),
-                .hw_addr.from   = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
        },
        [DMACH_PCM_OUT] = {
                .name           = "pcm-out",
                .channels       = MAP(S3C2443_DMAREQSEL_PCMOUT),
-                .hw_addr.to     = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
        },
        [DMACH_MIC_IN] = {
                .name           = "mic-in",
                .channels       = MAP(S3C2443_DMAREQSEL_MICIN),
-                .hw_addr.from   = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
        },
 };
diff --git a/arch/arm/mach-s3c64xx/cpu.c b/arch/arm/mach-s3c64xx/cpu.c
index 8dc05763a7eb..c7047838e112 100644
--- a/arch/arm/mach-s3c64xx/cpu.c
+++ b/arch/arm/mach-s3c64xx/cpu.c
@@ -44,16 +44,16 @@ static const char name_s3c6410[] = "S3C6410";
 static struct cpu_table cpu_ids[] __initdata = {
        {
-                .idcode         = 0x36400000,
+                .idcode         = S3C6400_CPU_ID,
-                .idmask         = 0xfffff000,
+                .idmask         = S3C64XX_CPU_MASK,
                .map_io         = s3c6400_map_io,
                .init_clocks    = s3c6400_init_clocks,
                .init_uarts     = s3c6400_init_uarts,
                .init           = s3c6400_init,
                .name           = name_s3c6400,
        }, {
-                .idcode         = 0x36410100,
+                .idcode         = S3C6410_CPU_ID,
-                .idmask         = 0xffffff00,
+                .idmask         = S3C64XX_CPU_MASK,
                .map_io         = s3c6410_map_io,
                .init_clocks    = s3c6410_init_clocks,
                .init_uarts     = s3c6410_init_uarts,
@@ -141,23 +141,15 @@ void __init s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
 {
-        unsigned long idcode;
        /* initialise the io descriptors we need for initialisation */
        iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
        iotable_init(mach_desc, size);
        init_consistent_dma_size(SZ_8M);
-        idcode = __raw_readl(S3C_VA_SYS + 0x118);
+        /* detect cpu id */
-        if (!idcode) {
+        s3c64xx_init_cpu();
-                /* S3C6400 has the ID register in a different place,
-                 * and needs a write before it can be read. */
-                __raw_writel(0x0, S3C_VA_SYS + 0xA1C);
-                idcode = __raw_readl(S3C_VA_SYS + 0xA1C);
-        }
-        s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
+        s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 }
 static __init int s3c64xx_sysdev_init(void)
diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h
index a1f13f02c841..23a1d71e4d53 100644
--- a/arch/arm/mach-s3c64xx/include/mach/map.h
+++ b/arch/arm/mach-s3c64xx/include/mach/map.h
@@ -16,6 +16,7 @@
 #define __ASM_ARCH_MAP_H __FILE__
 #include <plat/map-base.h>
+#include <plat/map-s3c.h>
 /*
 * Post-mux Chip Select Regions Xm0CSn_
@@ -83,7 +84,6 @@
 #define S3C64XX_PA_IIC1         (0x7F00F000)
 #define S3C64XX_PA_GPIO         (0x7F008000)
-#define S3C64XX_VA_GPIO         S3C_ADDR_CPU(0x00000000)
 #define S3C64XX_SZ_GPIO         SZ_4K
 #define S3C64XX_PA_SDRAM        (0x50000000)
@@ -94,16 +94,10 @@
 #define S3C64XX_PA_VIC1         (0x71300000)
 #define S3C64XX_PA_MODEM        (0x74108000)
-#define S3C64XX_VA_MODEM        S3C_ADDR_CPU(0x00100000)
 #define S3C64XX_PA_USBHOST      (0x74300000)
 #define S3C64XX_PA_USB_HSPHY    (0x7C100000)
-#define S3C64XX_VA_USB_HSPHY    S3C_ADDR_CPU(0x00200000)
-/* place VICs close together */
-#define VA_VIC0                 (S3C_VA_IRQ + 0x00)
-#define VA_VIC1                 (S3C_VA_IRQ + 0x10000)
 /* compatibiltiy defines. */
 #define S3C_PA_TIMER            S3C64XX_PA_TIMER
@@ -119,7 +113,6 @@
 #define S3C_PA_FB               S3C64XX_PA_FB
 #define S3C_PA_USBHOST          S3C64XX_PA_USBHOST
 #define S3C_PA_USB_HSOTG        S3C64XX_PA_USB_HSOTG
-#define S3C_VA_USB_HSPHY        S3C64XX_VA_USB_HSPHY
 #define S3C_PA_RTC              S3C64XX_PA_RTC
 #define S3C_PA_WDT              S3C64XX_PA_WATCHDOG
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 4c76e08423fb..806580388f30 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -329,9 +329,6 @@ static struct platform_device *crag6410_devices[] __initdata = {
        &s3c_device_fb,
        &s3c_device_ohci,
        &s3c_device_usb_hsotg,
-        &s3c_device_adc,
-        &s3c_device_rtc,
-        &s3c_device_ts,
        &s3c_device_timer[0],
        &s3c64xx_device_iis0,
        &s3c64xx_device_iis1,
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index e91f63f7a490..fb8969aa412e 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -205,12 +205,6 @@ static struct platform_device mini6410_lcd_powerdev = {
        .dev.platform_data      = &mini6410_lcd_power_data,
 };
-static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
-        .delay                  = 10000,
-        .presc                  = 49,
-        .oversampling_shift     = 2,
-};
 static struct platform_device *mini6410_devices[] __initdata = {
        &mini6410_device_eth,
        &s3c_device_hsmmc0,
@@ -319,7 +313,7 @@ static void __init mini6410_machine_init(void)
        s3c_nand_set_platdata(&mini6410_nand_info);
        s3c_fb_set_platdata(&mini6410_lcd_pdata);
-        s3c24xx_ts_set_platdata(&s3c_ts_platform);
+        s3c24xx_ts_set_platdata(NULL);
        /* configure nCS1 width to 16 bits */
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index 10870cb5b39e..93170d4834e7 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -198,12 +198,6 @@ static struct platform_device *real6410_devices[] __initdata = {
        &s3c_device_ohci,
 };
-static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
-        .delay                  = 10000,
-        .presc                  = 49,
-        .oversampling_shift     = 2,
-};
 static void __init real6410_map_io(void)
 {
        u32 tmp;
@@ -300,7 +294,7 @@ static void __init real6410_machine_init(void)
        s3c_fb_set_platdata(&real6410_lcd_pdata);
        s3c_nand_set_platdata(&real6410_nand_info);
-        s3c24xx_ts_set_platdata(&s3c_ts_platform);
+        s3c24xx_ts_set_platdata(NULL);
        /* configure nCS1 width to 16 bits */
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index 7b66ede9fbcd..5f147c33edad 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -619,12 +619,6 @@ static struct i2c_board_info i2c_devs1[] __initdata = {
        { I2C_BOARD_INFO("24c128", 0x57), },    /* Samsung S524AD0XD1 */
 };
-static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
-        .delay                  = 10000,
-        .presc                  = 49,
-        .oversampling_shift     = 2,
-};
 /* LCD Backlight data */
 static struct samsung_bl_gpio_info smdk6410_bl_gpio_info = {
        .no = S3C64XX_GPF(15),
@@ -666,7 +660,7 @@ static void __init smdk6410_machine_init(void)
        samsung_keypad_set_platdata(&smdk6410_keypad_data);
-        s3c24xx_ts_set_platdata(&s3c_ts_platform);
+        s3c24xx_ts_set_platdata(NULL);
        /* configure nCS1 width to 16 bits */
diff --git a/arch/arm/mach-s5p64x0/dev-spi.c b/arch/arm/mach-s5p64x0/dev-spi.c
index ac825e826326..1fd9c79c7dbc 100644
--- a/arch/arm/mach-s5p64x0/dev-spi.c
+++ b/arch/arm/mach-s5p64x0/dev-spi.c
@@ -21,6 +21,7 @@
 #include <mach/regs-clock.h>
 #include <mach/spi-clocks.h>
+#include <plat/cpu.h>
 #include <plat/s3c64xx-spi.h>
 #include <plat/gpio-cfg.h>
@@ -185,11 +186,8 @@ struct platform_device s5p64x0_device_spi1 = {
 void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
 {
-        unsigned int id;
        struct s3c64xx_spi_info *pd;
-        id = __raw_readl(S5P64X0_SYS_ID) & 0xFF000;
        /* Reject invalid configuration */
        if (!num_cs || src_clk_nr < 0
                        || src_clk_nr > S5P64X0_SPI_SRCCLK_SCLK) {
@@ -199,7 +197,7 @@ void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
        switch (cntrlr) {
        case 0:
-                if (id == 0x50000)
+                if (soc_is_s5p6450())
                        pd = &s5p6450_spi0_pdata;
                else
                        pd = &s5p6440_spi0_pdata;
@@ -207,7 +205,7 @@ void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
                s5p64x0_device_spi0.dev.platform_data = pd;
                break;
        case 1:
-                if (id == 0x50000)
+                if (soc_is_s5p6450())
                        pd = &s5p6450_spi1_pdata;
                else
                        pd = &s5p6440_spi1_pdata;
diff --git a/arch/arm/mach-s5p64x0/dma.c b/arch/arm/mach-s5p64x0/dma.c
index d7ad944b3475..0e5b3e63e5b3 100644
--- a/arch/arm/mach-s5p64x0/dma.c
+++ b/arch/arm/mach-s5p64x0/dma.c
@@ -28,6 +28,7 @@
 #include <mach/irqs.h>
 #include <mach/regs-clock.h>
+#include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/s3c-pl330-pdata.h>
@@ -133,11 +134,7 @@ static struct platform_device s5p64x0_device_pdma = {
 static int __init s5p64x0_dma_init(void)
 {
-        unsigned int id;
+        if (soc_is_s5p6450())
-        id = __raw_readl(S5P64X0_SYS_ID) & 0xFF000;
-        if (id == 0x50000)
                s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata;
        else
                s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata;
diff --git a/arch/arm/mach-s5p64x0/gpiolib.c b/arch/arm/mach-s5p64x0/gpiolib.c
index e7fb3b004e77..700dac6c43f3 100644
--- a/arch/arm/mach-s5p64x0/gpiolib.c
+++ b/arch/arm/mach-s5p64x0/gpiolib.c
@@ -19,6 +19,7 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-clock.h>
+#include <plat/cpu.h>
 #include <plat/gpio-core.h>
 #include <plat/gpio-cfg.h>
 #include <plat/gpio-cfg-helpers.h>
@@ -473,14 +474,10 @@ static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
 static int __init s5p64x0_gpiolib_init(void)
 {
-        unsigned int chipid;
-        chipid = __raw_readl(S5P64X0_SYS_ID);
        s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs,
                                ARRAY_SIZE(s5p64x0_gpio_cfgs));
-        if ((chipid & 0xff000) == 0x50000) {
+        if (soc_is_s5p6450()) {
                samsung_gpiolib_add_2bit_chips(s5p6450_gpio_2bit,
                                        ARRAY_SIZE(s5p6450_gpio_2bit));
diff --git a/arch/arm/mach-s5p64x0/irq-eint.c b/arch/arm/mach-s5p64x0/irq-eint.c
index fe7380f5c3cd..494e1a8f6f6d 100644
--- a/arch/arm/mach-s5p64x0/irq-eint.c
+++ b/arch/arm/mach-s5p64x0/irq-eint.c
@@ -17,6 +17,7 @@
 #include <linux/irq.h>
 #include <linux/io.h>
+#include <plat/cpu.h>
 #include <plat/regs-irqtype.h>
 #include <plat/gpio-cfg.h>
@@ -67,7 +68,7 @@ static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
        __raw_writel(ctrl, S5P64X0_EINT0CON0);
        /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
-        if (0x50000 == (__raw_readl(S5P64X0_SYS_ID) & 0xFF000))
+        if (soc_is_s5p6450())
                s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
        else
                s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 3b84e9bfd073..88857f5a49f7 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -129,12 +129,6 @@ static struct i2c_board_info smdk6440_i2c_devs1[] __initdata = {
        /* To be populated */
 };
-static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
-        .delay                  = 10000,
-        .presc                  = 49,
-        .oversampling_shift     = 2,
-};
 /* LCD Backlight data */
 static struct samsung_bl_gpio_info smdk6440_bl_gpio_info = {
        .no = S5P6440_GPF(15),
@@ -155,7 +149,7 @@ static void __init smdk6440_map_io(void)
 static void __init smdk6440_machine_init(void)
 {
-        s3c24xx_ts_set_platdata(&s3c_ts_platform);
+        s3c24xx_ts_set_platdata(NULL);
        s3c_i2c0_set_platdata(&s5p6440_i2c0_data);
        s3c_i2c1_set_platdata(&s5p6440_i2c1_data);
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index d99d29b5558e..e1b277b94610 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -148,12 +148,6 @@ static struct i2c_board_info smdk6450_i2c_devs1[] __initdata = {
        { I2C_BOARD_INFO("24c128", 0x57), },/* Samsung S524AD0XD1 EEPROM */
 };
-static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
-        .delay                  = 10000,
-        .presc                  = 49,
-        .oversampling_shift     = 2,
-};
 /* LCD Backlight data */
 static struct samsung_bl_gpio_info smdk6450_bl_gpio_info = {
        .no = S5P6450_GPF(15),
@@ -174,7 +168,7 @@ static void __init smdk6450_map_io(void)
 static void __init smdk6450_machine_init(void)
 {
-        s3c24xx_ts_set_platdata(&s3c_ts_platform);
+        s3c24xx_ts_set_platdata(NULL);
        s3c_i2c0_set_platdata(&s5p6450_i2c0_data);
        s3c_i2c1_set_platdata(&s5p6450_i2c1_data);
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 688f45b7cd00..26f5c91c9427 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -203,12 +203,6 @@ static struct platform_device *smdkc100_devices[] __initdata = {
        &s5pc100_device_spdif,
 };
-static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
-        .delay                  = 10000,
-        .presc                  = 49,
-        .oversampling_shift     = 2,
-};
 /* LCD Backlight data */
 static struct samsung_bl_gpio_info smdkc100_bl_gpio_info = {
        .no = S5PC100_GPD(0),
@@ -228,7 +222,7 @@ static void __init smdkc100_map_io(void)
 static void __init smdkc100_machine_init(void)
 {
-        s3c24xx_ts_set_platdata(&s3c_ts_platform);
+        s3c24xx_ts_set_platdata(NULL);
        /* I2C */
        s3c_i2c0_set_platdata(NULL);
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 69dd87cd8e22..aaeb44a73716 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -14,7 +14,6 @@ config CPU_S5PV210
        select S3C_PL330_DMA
        select S5P_EXT_INT
        select S5P_HRT
-        select S5PV210_PM if PM
        help
          Enable S5PV210 CPU support
@@ -169,9 +168,4 @@ config MACH_TORBRECK
 endmenu
-config S5PV210_PM
-        bool
-        help
-          Power Management code common to S5PV210
 endif
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 599a3c0e8f6c..ef7e4668d670 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -14,7 +14,7 @@ obj-				:=
 obj-$(CONFIG_CPU_S5PV210)       += cpu.o init.o clock.o dma.o
 obj-$(CONFIG_CPU_S5PV210)       += setup-i2c0.o
-obj-$(CONFIG_S5PV210_PM)        += pm.o sleep.o
+obj-$(CONFIG_PM)                += pm.o sleep.o
 # machine support
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index e73e3b6d41b5..a9106c392398 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -265,12 +265,6 @@ static struct i2c_board_info smdkv210_i2c_devs2[] __initdata = {
        /* To Be Updated */
 };
-static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
-        .delay                  = 10000,
-        .presc                  = 49,
-        .oversampling_shift     = 2,
-};
 /* LCD Backlight data */
 static struct samsung_bl_gpio_info smdkv210_bl_gpio_info = {
        .no = S5PV210_GPD0(3),
@@ -296,7 +290,7 @@ static void __init smdkv210_machine_init(void)
        smdkv210_dm9000_init();
        samsung_keypad_set_platdata(&smdkv210_keypad_data);
-        s3c24xx_ts_set_platdata(&s3c_ts_platform);
+        s3c24xx_ts_set_platdata(NULL);
        s3c_i2c0_set_platdata(NULL);
        s3c_i2c1_set_platdata(NULL);
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index 3ffdbc92ba82..be1ade76ccc8 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -74,6 +74,8 @@ void __cpuinit sh73a0_secondary_init(unsigned int cpu)
 int __cpuinit sh73a0_boot_secondary(unsigned int cpu)
 {
+        cpu = cpu_logical_map(cpu);
        /* enable cache coherency */
        modify_scu_cpu_psr(0, 3 << (cpu * 8));
@@ -87,6 +89,8 @@ int __cpuinit sh73a0_boot_secondary(unsigned int cpu)
 void __init sh73a0_smp_prepare_cpus(void)
 {
+        int cpu = cpu_logical_map(0);
        scu_enable(scu_base_addr());
        /* Map the reset vector (in headsmp.S) */
@@ -94,5 +98,5 @@ void __init sh73a0_smp_prepare_cpus(void)
        __raw_writel(__pa(shmobile_secondary_vector), __io(SBAR));
        /* enable cache coherency on CPU0 */
-        modify_scu_cpu_psr(0, 3 << (0 * 8));
+        modify_scu_cpu_psr(0, 3 << (cpu * 8));
 }
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index d82ebab50e11..91aff7cb8284 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -69,6 +69,12 @@ config MACH_WARIO
       help
         Support for the Wario version of Seaboard
+config MACH_VENTANA
+       bool "Ventana board"
+       select MACH_TEGRA_DT
+       help
+         Support for the nVidia Ventana development platform
 choice
        prompt "Low-level debug console UART"
        default TEGRA_DEBUG_UART_NONE
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index f11b9100114a..91a07e187208 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -31,6 +31,7 @@ obj-${CONFIG_MACH_SEABOARD}             += board-seaboard-pinmux.o
 obj-${CONFIG_MACH_TEGRA_DT}             += board-dt.o
 obj-${CONFIG_MACH_TEGRA_DT}             += board-harmony-pinmux.o
+obj-${CONFIG_MACH_TEGRA_DT}             += board-seaboard-pinmux.o
 obj-${CONFIG_MACH_TRIMSLICE}            += board-trimslice.o
 obj-${CONFIG_MACH_TRIMSLICE}            += board-trimslice-pinmux.o
diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot
index 5e870d29eca1..bd12c9fb81e8 100644
--- a/arch/arm/mach-tegra/Makefile.boot
+++ b/arch/arm/mach-tegra/Makefile.boot
@@ -4,3 +4,4 @@ initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC)	:= 0x00800000
 dtb-$(CONFIG_MACH_HARMONY) += tegra-harmony.dtb
 dtb-$(CONFIG_MACH_SEABOARD) += tegra-seaboard.dtb
+dtb-$(CONFIG_MACH_VENTANA) += tegra-ventana.dtb
diff --git a/arch/arm/mach-tegra/board-dt.c b/arch/arm/mach-tegra/board-dt.c
index 9f47e04446f3..d368f8dafcfd 100644
--- a/arch/arm/mach-tegra/board-dt.c
+++ b/arch/arm/mach-tegra/board-dt.c
@@ -47,7 +47,7 @@
 void harmony_pinmux_init(void);
 void seaboard_pinmux_init(void);
+void ventana_pinmux_init(void);
 struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
        OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
@@ -80,9 +80,19 @@ static struct of_device_id tegra_dt_gic_match[] __initdata = {
        {}
 };
+static struct {
+        char *machine;
+        void (*init)(void);
+} pinmux_configs[] = {
+        { "nvidia,harmony", harmony_pinmux_init },
+        { "nvidia,seaboard", seaboard_pinmux_init },
+        { "nvidia,ventana", ventana_pinmux_init },
+};
 static void __init tegra_dt_init(void)
 {
        struct device_node *node;
+        int i;
        node = of_find_matching_node_by_address(NULL, tegra_dt_gic_match,
                                                TEGRA_ARM_INT_DIST_BASE);
@@ -91,10 +101,15 @@ static void __init tegra_dt_init(void)
        tegra_clk_init_from_table(tegra_dt_clk_init_table);
-        if (of_machine_is_compatible("nvidia,harmony"))
+        for (i = 0; i < ARRAY_SIZE(pinmux_configs); i++) {
-                harmony_pinmux_init();
+                if (of_machine_is_compatible(pinmux_configs[i].machine)) {
-        else if (of_machine_is_compatible("nvidia,seaboard"))
+                        pinmux_configs[i].init();
-                seaboard_pinmux_init();
+                        break;
+                }
+        }
+        WARN(i == ARRAY_SIZE(pinmux_configs),
+                "Unknown platform! Pinmuxing not initialized\n");
        /*
         * Finished with the static registrations now; fill in the missing
@@ -106,6 +121,7 @@ static void __init tegra_dt_init(void)
 static const char * tegra_dt_board_compat[] = {
        "nvidia,harmony",
        "nvidia,seaboard",
+        "nvidia,ventana",
        NULL
 };
diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c
index 4d63e2e97a8d..e99b45618cd0 100644
--- a/arch/arm/mach-tegra/board-harmony-pinmux.c
+++ b/arch/arm/mach-tegra/board-harmony-pinmux.c
@@ -20,6 +20,7 @@
 #include "gpio-names.h"
 #include "board-harmony.h"
+#include "devices.h"
 static struct tegra_pingroup_config harmony_pinmux[] = {
        {TEGRA_PINGROUP_ATA,   TEGRA_MUX_IDE,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
@@ -140,6 +141,11 @@ static struct tegra_pingroup_config harmony_pinmux[] = {
        {TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 };
+static struct platform_device *pinmux_devices[] = {
+        &tegra_gpio_device,
+        &tegra_pinmux_device,
+};
 static struct tegra_gpio_table gpio_table[] = {
        { .gpio = TEGRA_GPIO_SD2_CD,            .enable = true  },
        { .gpio = TEGRA_GPIO_SD2_WP,            .enable = true  },
@@ -155,6 +161,8 @@ static struct tegra_gpio_table gpio_table[] = {
 void harmony_pinmux_init(void)
 {
+        platform_add_devices(pinmux_devices, ARRAY_SIZE(pinmux_devices));
        tegra_pinmux_config_table(harmony_pinmux, ARRAY_SIZE(harmony_pinmux));
        tegra_gpio_config(gpio_table, ARRAY_SIZE(gpio_table));
diff --git a/arch/arm/mach-tegra/board-harmony-power.c b/arch/arm/mach-tegra/board-harmony-power.c
index 5ad8b2f94f8d..21d1285731b3 100644
--- a/arch/arm/mach-tegra/board-harmony-power.c
+++ b/arch/arm/mach-tegra/board-harmony-power.c
@@ -18,10 +18,11 @@
 #include <linux/i2c.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
+#include <linux/io.h>
 #include <linux/regulator/machine.h>
 #include <linux/mfd/tps6586x.h>
+#include <mach/iomap.h>
 #include <mach/irqs.h>
 #include "board-harmony.h"
@@ -113,6 +114,16 @@ static struct i2c_board_info __initdata harmony_regulators[] = {
 int __init harmony_regulator_init(void)
 {
+        void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
+        u32 pmc_ctrl;
+        /*
+         * Configure the power management controller to trigger PMU
+         * interrupts when low
+         */
+        pmc_ctrl = readl(pmc + PMC_CTRL);
+        writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
        i2c_register_board_info(3, harmony_regulators, 1);
        return 0;
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
index 93c793f48caf..f0bdc5e3fe52 100644
--- a/arch/arm/mach-tegra/board-harmony.c
+++ b/arch/arm/mach-tegra/board-harmony.c
@@ -49,7 +49,8 @@ static struct plat_serial8250_port debug_uart_platform_data[] = {
                .membase        = IO_ADDRESS(TEGRA_UARTD_BASE),
                .mapbase        = TEGRA_UARTD_BASE,
                .irq            = INT_UARTD,
-                .flags          = UPF_BOOT_AUTOCONF,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
+                .type           = PORT_TEGRA,
                .iotype         = UPIO_MEM,
                .regshift       = 2,
                .uartclk        = 216000000,
@@ -117,6 +118,7 @@ static struct platform_device *harmony_devices[] __initdata = {
        &tegra_sdhci_device1,
        &tegra_sdhci_device2,
        &tegra_sdhci_device4,
+        &tegra_ehci3_device,
        &tegra_i2s_device1,
        &tegra_das_device,
        &tegra_pcm_device,
@@ -140,6 +142,7 @@ static __initdata struct tegra_clk_init_table harmony_clk_init_table[] = {
        { "pll_a_out0", "pll_a",        11289600,       true },
        { "cdev1",      NULL,           0,              true },
        { "i2s1",       "pll_a_out0",   11289600,       false},
+        { "usb3",       "clk_m",        12000000,       true },
        { NULL,         NULL,           0,              0},
 };
diff --git a/arch/arm/mach-tegra/board-paz00-pinmux.c b/arch/arm/mach-tegra/board-paz00-pinmux.c
index bdd2627dd87b..fb20894862b0 100644
--- a/arch/arm/mach-tegra/board-paz00-pinmux.c
+++ b/arch/arm/mach-tegra/board-paz00-pinmux.c
@@ -20,6 +20,7 @@
 #include "gpio-names.h"
 #include "board-paz00.h"
+#include "devices.h"
 static struct tegra_pingroup_config paz00_pinmux[] = {
        {TEGRA_PINGROUP_ATA,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
@@ -140,15 +141,25 @@ static struct tegra_pingroup_config paz00_pinmux[] = {
        {TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 };
+static struct platform_device *pinmux_devices[] = {
+        &tegra_gpio_device,
+        &tegra_pinmux_device,
+};
 static struct tegra_gpio_table gpio_table[] = {
        { .gpio = TEGRA_GPIO_SD1_CD,    .enable = true },
        { .gpio = TEGRA_GPIO_SD1_WP,    .enable = true },
        { .gpio = TEGRA_GPIO_SD1_POWER, .enable = true },
        { .gpio = TEGRA_ULPI_RST,       .enable = true },
+        { .gpio = TEGRA_WIFI_PWRN,      .enable = true },
+        { .gpio = TEGRA_WIFI_RST,       .enable = true },
+        { .gpio = TEGRA_WIFI_LED,       .enable = true },
 };
 void paz00_pinmux_init(void)
 {
+        platform_add_devices(pinmux_devices, ARRAY_SIZE(pinmux_devices));
        tegra_pinmux_config_table(paz00_pinmux, ARRAY_SIZE(paz00_pinmux));
        tegra_gpio_config(gpio_table, ARRAY_SIZE(gpio_table));
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index fbc9e0ed926e..55c55ba89f1e 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -26,6 +26,8 @@
 #include <linux/pda_power.h>
 #include <linux/io.h>
 #include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/rfkill-gpio.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -35,7 +37,6 @@
 #include <mach/iomap.h>
 #include <mach/irqs.h>
 #include <mach/sdhci.h>
-#include <mach/gpio.h>
 #include "board.h"
 #include "board-paz00.h"
@@ -45,10 +46,22 @@
 static struct plat_serial8250_port debug_uart_platform_data[] = {
        {
+                /* serial port on JP1 */
+                .membase        = IO_ADDRESS(TEGRA_UARTA_BASE),
+                .mapbase        = TEGRA_UARTA_BASE,
+                .irq            = INT_UARTA,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
+                .type           = PORT_TEGRA,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = 216000000,
+        }, {
+                /* serial port on mini-pcie */
                .membase        = IO_ADDRESS(TEGRA_UARTD_BASE),
                .mapbase        = TEGRA_UARTD_BASE,
                .irq            = INT_UARTD,
-                .flags          = UPF_BOOT_AUTOCONF,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
+                .type           = PORT_TEGRA,
                .iotype         = UPIO_MEM,
                .regshift       = 2,
                .uartclk        = 216000000,
@@ -65,10 +78,48 @@ static struct platform_device debug_uart = {
        },
 };
+static struct rfkill_gpio_platform_data wifi_rfkill_platform_data = {
+        .name           = "wifi_rfkill",
+        .reset_gpio     = TEGRA_WIFI_RST,
+        .shutdown_gpio  = TEGRA_WIFI_PWRN,
+        .type   = RFKILL_TYPE_WLAN,
+};
+static struct platform_device wifi_rfkill_device = {
+        .name   = "rfkill_gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &wifi_rfkill_platform_data,
+        },
+};
+static struct gpio_led gpio_leds[] = {
+        {
+                .name                   = "wifi-led",
+                .default_trigger        = "rfkill0",
+                .gpio                   = TEGRA_WIFI_LED,
+        },
+};
+static struct gpio_led_platform_data gpio_led_info = {
+        .leds           = gpio_leds,
+        .num_leds       = ARRAY_SIZE(gpio_leds),
+};
+static struct platform_device leds_gpio = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &gpio_led_info,
+        },
+};
 static struct platform_device *paz00_devices[] __initdata = {
        &debug_uart,
-        &tegra_sdhci_device1,
        &tegra_sdhci_device4,
+        &tegra_sdhci_device1,
+        &wifi_rfkill_device,
+        &leds_gpio,
 };
 static void paz00_i2c_init(void)
@@ -94,7 +145,14 @@ static void __init tegra_paz00_fixup(struct tag *tags, char **cmdline,
 static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = {
        /* name         parent          rate            enabled */
+        { "uarta",      "pll_p",        216000000,      true },
        { "uartd",      "pll_p",        216000000,      true },
+        { "pll_p_out4", "pll_p",        24000000,       true },
+        { "usbd",       "clk_m",        12000000,       false },
+        { "usb2",       "clk_m",        12000000,       false },
+        { "usb3",       "clk_m",        12000000,       false },
        { NULL,         NULL,           0,              0},
 };
diff --git a/arch/arm/mach-tegra/board-paz00.h b/arch/arm/mach-tegra/board-paz00.h
index 42ce8639b90c..8aff06eb58c3 100644
--- a/arch/arm/mach-tegra/board-paz00.h
+++ b/arch/arm/mach-tegra/board-paz00.h
@@ -19,11 +19,19 @@
 #include <mach/gpio-tegra.h>
+/* SDCARD */
 #define TEGRA_GPIO_SD1_CD               TEGRA_GPIO_PV5
 #define TEGRA_GPIO_SD1_WP               TEGRA_GPIO_PH1
 #define TEGRA_GPIO_SD1_POWER            TEGRA_GPIO_PT3
+/* ULPI */
 #define TEGRA_ULPI_RST                  TEGRA_GPIO_PV0
+/* WIFI */
+#define TEGRA_WIFI_PWRN                 TEGRA_GPIO_PK5
+#define TEGRA_WIFI_RST                  TEGRA_GPIO_PD1
+#define TEGRA_WIFI_LED                  TEGRA_GPIO_PD0
 void paz00_pinmux_init(void);
 #endif
diff --git a/arch/arm/mach-tegra/board-seaboard-pinmux.c b/arch/arm/mach-tegra/board-seaboard-pinmux.c
index 0bda495e9742..fbce31daa3c9 100644
--- a/arch/arm/mach-tegra/board-seaboard-pinmux.c
+++ b/arch/arm/mach-tegra/board-seaboard-pinmux.c
@@ -1,5 +1,6 @@
 /*
- * Copyright (C) 2010 NVIDIA Corporation
+ * Copyright (C) 2010,2011 NVIDIA Corporation
+ * Copyright (C) 2011 Google, Inc.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
@@ -21,6 +22,7 @@
 #include "gpio-names.h"
 #include "board-seaboard.h"
+#include "devices.h"
 #define DEFAULT_DRIVE(_name)                                    \
        {                                                       \
@@ -49,7 +51,7 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
        {TEGRA_PINGROUP_CRTP,  TEGRA_MUX_CRT,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
        {TEGRA_PINGROUP_CSUS,  TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
        {TEGRA_PINGROUP_DAP1,  TEGRA_MUX_DAP1,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DAP2,  TEGRA_MUX_DAP2,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_DAP2,  TEGRA_MUX_DAP2,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
        {TEGRA_PINGROUP_DAP3,  TEGRA_MUX_DAP3,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
        {TEGRA_PINGROUP_DAP4,  TEGRA_MUX_DAP4,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
        {TEGRA_PINGROUP_DDC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
@@ -133,7 +135,7 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
        {TEGRA_PINGROUP_SPDO,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
        {TEGRA_PINGROUP_SPIA,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
        {TEGRA_PINGROUP_SPIB,  TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIC,  TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_SPIC,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
        {TEGRA_PINGROUP_SPID,  TEGRA_MUX_SPI1,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
        {TEGRA_PINGROUP_SPIE,  TEGRA_MUX_SPI1,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
        {TEGRA_PINGROUP_SPIF,  TEGRA_MUX_SPI1,          TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
@@ -157,24 +159,83 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
        {TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 };
+static __initdata struct tegra_pingroup_config ventana_pinmux[] = {
+        {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3,     TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_DDC,  TEGRA_MUX_RSVD2,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        {TEGRA_PINGROUP_DTA,  TEGRA_MUX_VI,       TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        {TEGRA_PINGROUP_DTB,  TEGRA_MUX_VI,       TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        {TEGRA_PINGROUP_DTC,  TEGRA_MUX_VI,       TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        {TEGRA_PINGROUP_DTD,  TEGRA_MUX_VI,       TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        {TEGRA_PINGROUP_GMD,  TEGRA_MUX_SFLASH,   TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_LPW0, TEGRA_MUX_RSVD4,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        {TEGRA_PINGROUP_LPW2, TEGRA_MUX_RSVD4,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        {TEGRA_PINGROUP_LSC1, TEGRA_MUX_RSVD4,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        {TEGRA_PINGROUP_LSCK, TEGRA_MUX_RSVD4,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_LSDA, TEGRA_MUX_RSVD4,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_PTA,  TEGRA_MUX_RSVD2,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SDIO3,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        {TEGRA_PINGROUP_SLXK, TEGRA_MUX_SDIO3,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+};
+static struct platform_device *pinmux_devices[] = {
+        &tegra_gpio_device,
+        &tegra_pinmux_device,
+};
+static struct tegra_gpio_table common_gpio_table[] = {
-static struct tegra_gpio_table gpio_table[] = {
        { .gpio = TEGRA_GPIO_SD2_CD,            .enable = true },
        { .gpio = TEGRA_GPIO_SD2_WP,            .enable = true },
        { .gpio = TEGRA_GPIO_SD2_POWER,         .enable = true },
        { .gpio = TEGRA_GPIO_LIDSWITCH,         .enable = true },
        { .gpio = TEGRA_GPIO_POWERKEY,          .enable = true },
        { .gpio = TEGRA_GPIO_ISL29018_IRQ,      .enable = true },
+        { .gpio = TEGRA_GPIO_CDC_IRQ,           .enable = true },
+        { .gpio = TEGRA_GPIO_USB1,              .enable = true },
 };
-void __init seaboard_pinmux_init(void)
+static void __init update_pinmux(struct tegra_pingroup_config *newtbl, int size)
+{
+        int i, j;
+        struct tegra_pingroup_config *new_pingroup, *base_pingroup;
+        /* Update base seaboard pinmux table with secondary board
+         * specific pinmux table table.
+         */
+        for (i = 0; i < size; i++) {
+                new_pingroup = &newtbl[i];
+                for (j = 0; j < ARRAY_SIZE(seaboard_pinmux); j++) {
+                        base_pingroup = &seaboard_pinmux[j];
+                        if (new_pingroup->pingroup == base_pingroup->pingroup) {
+                                *base_pingroup = *new_pingroup;
+                                break;
+                        }
+                }
+        }
+}
+void __init seaboard_common_pinmux_init(void)
 {
+        platform_add_devices(pinmux_devices, ARRAY_SIZE(pinmux_devices));
        tegra_pinmux_config_table(seaboard_pinmux, ARRAY_SIZE(seaboard_pinmux));
        tegra_drive_pinmux_config_table(seaboard_drive_pinmux,
                                        ARRAY_SIZE(seaboard_drive_pinmux));
-        tegra_gpio_config(gpio_table, ARRAY_SIZE(gpio_table));
+        tegra_gpio_config(common_gpio_table, ARRAY_SIZE(common_gpio_table));
+}
+void __init seaboard_pinmux_init(void)
+{
+        seaboard_common_pinmux_init();
 }
+void __init ventana_pinmux_init(void)
+{
+        update_pinmux(ventana_pinmux, ARRAY_SIZE(ventana_pinmux));
+        seaboard_common_pinmux_init();
+}
diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c
index 9e98ac706f40..bf13ea355efc 100644
--- a/arch/arm/mach-tegra/board-seaboard.c
+++ b/arch/arm/mach-tegra/board-seaboard.c
@@ -25,9 +25,12 @@
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
+#include <sound/wm8903.h>
 #include <mach/iomap.h>
 #include <mach/irqs.h>
 #include <mach/sdhci.h>
+#include <mach/tegra_wm8903_pdata.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -41,7 +44,8 @@
 static struct plat_serial8250_port debug_uart_platform_data[] = {
        {
                /* Memory and IRQ filled in before registration */
-                .flags          = UPF_BOOT_AUTOCONF,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
+                .type           = PORT_TEGRA,
                .iotype         = UPIO_MEM,
                .regshift       = 2,
                .uartclk        = 216000000,
@@ -62,6 +66,12 @@ static __initdata struct tegra_clk_init_table seaboard_clk_init_table[] = {
        /* name         parent          rate            enabled */
        { "uartb",      "pll_p",        216000000,      true},
        { "uartd",      "pll_p",        216000000,      true},
+        { "pll_a",      "pll_p_out1",   56448000,       true },
+        { "pll_a_out0", "pll_a",        11289600,       true },
+        { "cdev1",      NULL,           0,              true },
+        { "i2s1",       "pll_a_out0",   11289600,       false},
+        { "usbd",       "clk_m",        12000000,       true},
+        { "usb3",       "clk_m",        12000000,       true},
        { NULL,         NULL,           0,              0},
 };
@@ -117,6 +127,22 @@ static struct tegra_sdhci_platform_data sdhci_pdata4 = {
        .is_8bit        = 1,
 };
+static struct tegra_wm8903_platform_data seaboard_audio_pdata = {
+        .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
+        .gpio_hp_det            = TEGRA_GPIO_HP_DET,
+        .gpio_hp_mute           = -1,
+        .gpio_int_mic_en        = -1,
+        .gpio_ext_mic_en        = -1,
+};
+static struct platform_device seaboard_audio_device = {
+        .name   = "tegra-snd-wm8903",
+        .id     = 0,
+        .dev    = {
+                .platform_data  = &seaboard_audio_pdata,
+        },
+};
 static struct platform_device *seaboard_devices[] __initdata = {
        &debug_uart,
        &tegra_pmu_device,
@@ -124,6 +150,10 @@ static struct platform_device *seaboard_devices[] __initdata = {
        &tegra_sdhci_device3,
        &tegra_sdhci_device1,
        &seaboard_gpio_keys_device,
+        &tegra_i2s_device1,
+        &tegra_das_device,
+        &tegra_pcm_device,
+        &seaboard_audio_device,
 };
 static struct i2c_board_info __initdata isl29018_device = {
@@ -135,12 +165,56 @@ static struct i2c_board_info __initdata adt7461_device = {
        I2C_BOARD_INFO("adt7461", 0x4c),
 };
+static struct wm8903_platform_data wm8903_pdata = {
+        .irq_active_low = 0,
+        .micdet_cfg = 0,
+        .micdet_delay = 100,
+        .gpio_base = SEABOARD_GPIO_WM8903(0),
+        .gpio_cfg = {
+                WM8903_GPIO_NO_CONFIG,
+                WM8903_GPIO_NO_CONFIG,
+                0,
+                WM8903_GPIO_NO_CONFIG,
+                WM8903_GPIO_NO_CONFIG,
+        },
+};
+static struct i2c_board_info __initdata wm8903_device = {
+        I2C_BOARD_INFO("wm8903", 0x1a),
+        .platform_data = &wm8903_pdata,
+        .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
+};
+static int seaboard_ehci_init(void)
+{
+        int gpio_status;
+        gpio_status = gpio_request(TEGRA_GPIO_USB1, "VBUS_USB1");
+        if (gpio_status < 0) {
+                pr_err("VBUS_USB1 request GPIO FAILED\n");
+                WARN_ON(1);
+        }
+        gpio_status = gpio_direction_output(TEGRA_GPIO_USB1, 1);
+        if (gpio_status < 0) {
+                pr_err("VBUS_USB1 request GPIO DIRECTION FAILED\n");
+                WARN_ON(1);
+        }
+        gpio_set_value(TEGRA_GPIO_USB1, 1);
+        platform_device_register(&tegra_ehci1_device);
+        platform_device_register(&tegra_ehci3_device);
+        return 0;
+}
 static void __init seaboard_i2c_init(void)
 {
        gpio_request(TEGRA_GPIO_ISL29018_IRQ, "isl29018");
        gpio_direction_input(TEGRA_GPIO_ISL29018_IRQ);
        i2c_register_board_info(0, &isl29018_device, 1);
+        i2c_register_board_info(0, &wm8903_device, 1);
        i2c_register_board_info(3, &adt7461_device, 1);
@@ -161,6 +235,8 @@ static void __init seaboard_common_init(void)
        tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
        platform_add_devices(seaboard_devices, ARRAY_SIZE(seaboard_devices));
+        seaboard_ehci_init();
 }
 static void __init tegra_seaboard_init(void)
@@ -182,6 +258,9 @@ static void __init tegra_kaen_init(void)
        debug_uart_platform_data[0].mapbase = TEGRA_UARTB_BASE;
        debug_uart_platform_data[0].irq = INT_UARTB;
+        seaboard_audio_pdata.gpio_hp_mute = TEGRA_GPIO_KAEN_HP_MUTE;
+        tegra_gpio_enable(TEGRA_GPIO_KAEN_HP_MUTE);
        seaboard_common_init();
        seaboard_i2c_init();
diff --git a/arch/arm/mach-tegra/board-seaboard.h b/arch/arm/mach-tegra/board-seaboard.h
index 15b6c57361be..4c45d4ca3c49 100644
--- a/arch/arm/mach-tegra/board-seaboard.h
+++ b/arch/arm/mach-tegra/board-seaboard.h
@@ -19,6 +19,9 @@
 #include <mach/gpio-tegra.h>
+#define SEABOARD_GPIO_TPS6586X(_x_)     (TEGRA_NR_GPIOS + (_x_))
+#define SEABOARD_GPIO_WM8903(_x_)       (SEABOARD_GPIO_TPS6586X(4) + (_x_))
 #define TEGRA_GPIO_SD2_CD               TEGRA_GPIO_PI5
 #define TEGRA_GPIO_SD2_WP               TEGRA_GPIO_PH1
 #define TEGRA_GPIO_SD2_POWER            TEGRA_GPIO_PI6
@@ -33,10 +36,11 @@
 #define TEGRA_GPIO_MAGNETOMETER         TEGRA_GPIO_PN5
 #define TEGRA_GPIO_ISL29018_IRQ         TEGRA_GPIO_PZ2
 #define TEGRA_GPIO_AC_ONLINE            TEGRA_GPIO_PV3
+#define TEGRA_GPIO_WWAN_PWR             SEABOARD_GPIO_TPS6586X(2)
-#define TPS_GPIO_BASE                   TEGRA_NR_GPIOS
+#define TEGRA_GPIO_CDC_IRQ              TEGRA_GPIO_PX3
+#define TEGRA_GPIO_SPKR_EN              SEABOARD_GPIO_WM8903(2)
-#define TPS_GPIO_WWAN_PWR               (TPS_GPIO_BASE + 2)
+#define TEGRA_GPIO_HP_DET               TEGRA_GPIO_PX1
+#define TEGRA_GPIO_KAEN_HP_MUTE         TEGRA_GPIO_PA5
 void seaboard_pinmux_init(void);
diff --git a/arch/arm/mach-tegra/board-trimslice-pinmux.c b/arch/arm/mach-tegra/board-trimslice-pinmux.c
index bcb1916e68b9..4969dd28a04c 100644
--- a/arch/arm/mach-tegra/board-trimslice-pinmux.c
+++ b/arch/arm/mach-tegra/board-trimslice-pinmux.c
@@ -21,6 +21,7 @@
 #include "gpio-names.h"
 #include "board-trimslice.h"
+#include "devices.h"
 static __initdata struct tegra_pingroup_config trimslice_pinmux[] = {
        {TEGRA_PINGROUP_ATA,   TEGRA_MUX_IDE,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
@@ -141,6 +142,11 @@ static __initdata struct tegra_pingroup_config trimslice_pinmux[] = {
        {TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
 };
+static struct platform_device *pinmux_devices[] = {
+        &tegra_gpio_device,
+        &tegra_pinmux_device,
+};
 static struct tegra_gpio_table gpio_table[] = {
        { .gpio = TRIMSLICE_GPIO_SD4_CD, .enable = true }, /* mmc4 cd */
        { .gpio = TRIMSLICE_GPIO_SD4_WP, .enable = true }, /* mmc4 wp */
@@ -151,6 +157,7 @@ static struct tegra_gpio_table gpio_table[] = {
 void __init trimslice_pinmux_init(void)
 {
+        platform_add_devices(pinmux_devices, ARRAY_SIZE(pinmux_devices));
        tegra_pinmux_config_table(trimslice_pinmux, ARRAY_SIZE(trimslice_pinmux));
        tegra_gpio_config(gpio_table, ARRAY_SIZE(gpio_table));
 }
diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
index e3d9ec2f0fe1..1a6617b7806f 100644
--- a/arch/arm/mach-tegra/board-trimslice.c
+++ b/arch/arm/mach-tegra/board-trimslice.c
@@ -32,7 +32,6 @@
 #include <mach/iomap.h>
 #include <mach/sdhci.h>
-#include <mach/gpio.h>
 #include "board.h"
 #include "clock.h"
@@ -46,7 +45,8 @@ static struct plat_serial8250_port debug_uart_platform_data[] = {
                .membase        = IO_ADDRESS(TEGRA_UARTA_BASE),
                .mapbase        = TEGRA_UARTA_BASE,
                .irq            = INT_UARTA,
-                .flags          = UPF_BOOT_AUTOCONF,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
+                .type           = PORT_TEGRA,
                .iotype         = UPIO_MEM,
                .regshift       = 2,
                .uartclk        = 216000000,
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index d5e3f89b05af..690b888be506 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -61,7 +61,7 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
        { NULL,         NULL,           0,              0},
 };
-void __init tegra_init_cache(void)
+static void __init tegra_init_cache(void)
 {
 #ifdef CONFIG_CACHE_L2X0
        void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c
index 0e0fd4d889bd..bb5ce39b733b 100644
--- a/arch/arm/mach-tegra/cpu-tegra.c
+++ b/arch/arm/mach-tegra/cpu-tegra.c
@@ -56,12 +56,12 @@ static unsigned long target_cpu_speed[NUM_CPUS];
 static DEFINE_MUTEX(tegra_cpu_lock);
 static bool is_suspended;
-int tegra_verify_speed(struct cpufreq_policy *policy)
+static int tegra_verify_speed(struct cpufreq_policy *policy)
 {
        return cpufreq_frequency_table_verify(policy, freq_table);
 }
-unsigned int tegra_getspeed(unsigned int cpu)
+static unsigned int tegra_getspeed(unsigned int cpu)
 {
        unsigned long rate;
@@ -129,7 +129,7 @@ static int tegra_target(struct cpufreq_policy *policy,
                       unsigned int target_freq,
                       unsigned int relation)
 {
-        int idx;
+        unsigned int idx;
        unsigned int freq;
        int ret = 0;
diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
index 57e35d20c24c..7a2a02dbd632 100644
--- a/arch/arm/mach-tegra/devices.c
+++ b/arch/arm/mach-tegra/devices.c
@@ -29,7 +29,93 @@
 #include <mach/iomap.h>
 #include <mach/dma.h>
 #include <mach/usb_phy.h>
 #include "gpio-names.h"
+#include "devices.h"
+static struct resource gpio_resource[] = {
+        [0] = {
+                .start  = TEGRA_GPIO_BASE,
+                .end    = TEGRA_GPIO_BASE + TEGRA_GPIO_SIZE-1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = INT_GPIO1,
+                .end    = INT_GPIO1,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = INT_GPIO2,
+                .end    = INT_GPIO2,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = INT_GPIO3,
+                .end    = INT_GPIO3,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [4] = {
+                .start  = INT_GPIO4,
+                .end    = INT_GPIO4,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [5] = {
+                .start  = INT_GPIO5,
+                .end    = INT_GPIO5,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [6] = {
+                .start  = INT_GPIO6,
+                .end    = INT_GPIO6,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [7] = {
+                .start  = INT_GPIO7,
+                .end    = INT_GPIO7,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+struct platform_device tegra_gpio_device = {
+        .name           = "tegra-gpio",
+        .id             = -1,
+        .resource       = gpio_resource,
+        .num_resources  = ARRAY_SIZE(gpio_resource),
+};
+static struct resource pinmux_resource[] = {
+        [0] = {
+                /* Tri-state registers */
+                .start  = TEGRA_APB_MISC_BASE + 0x14,
+                .end    = TEGRA_APB_MISC_BASE + 0x20 + 3,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* Mux registers */
+                .start  = TEGRA_APB_MISC_BASE + 0x80,
+                .end    = TEGRA_APB_MISC_BASE + 0x9c + 3,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2] = {
+                /* Pull-up/down registers */
+                .start  = TEGRA_APB_MISC_BASE + 0xa0,
+                .end    = TEGRA_APB_MISC_BASE + 0xb0 + 3,
+                .flags  = IORESOURCE_MEM,
+        },
+        [3] = {
+                /* Pad control registers */
+                .start  = TEGRA_APB_MISC_BASE + 0x868,
+                .end    = TEGRA_APB_MISC_BASE + 0x90c + 3,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+struct platform_device tegra_pinmux_device = {
+        .name           = "tegra-pinmux",
+        .id             = -1,
+        .resource       = pinmux_resource,
+        .num_resources  = ARRAY_SIZE(pinmux_resource),
+};
 static struct resource i2c_resource1[] = {
        [0] = {
diff --git a/arch/arm/mach-tegra/devices.h b/arch/arm/mach-tegra/devices.h
index 4a7dc0a097d6..873ecb2f8ae6 100644
--- a/arch/arm/mach-tegra/devices.h
+++ b/arch/arm/mach-tegra/devices.h
@@ -21,6 +21,8 @@
 #include <linux/platform_device.h>
+extern struct platform_device tegra_gpio_device;
+extern struct platform_device tegra_pinmux_device;
 extern struct platform_device tegra_sdhci_device1;
 extern struct platform_device tegra_sdhci_device2;
 extern struct platform_device tegra_sdhci_device3;
diff --git a/arch/arm/mach-tegra/dma.c b/arch/arm/mach-tegra/dma.c
index f4ef5eb317bd..c0cf967e47d3 100644
--- a/arch/arm/mach-tegra/dma.c
+++ b/arch/arm/mach-tegra/dma.c
@@ -105,13 +105,17 @@
 #define NV_DMA_MAX_TRASFER_SIZE 0x10000
-const unsigned int ahb_addr_wrap_table[8] = {
+static const unsigned int ahb_addr_wrap_table[8] = {
        0, 32, 64, 128, 256, 512, 1024, 2048
 };
-const unsigned int apb_addr_wrap_table[8] = {0, 1, 2, 4, 8, 16, 32, 64};
+static const unsigned int apb_addr_wrap_table[8] = {
+        0, 1, 2, 4, 8, 16, 32, 64
+};
-const unsigned int bus_width_table[5] = {8, 16, 32, 64, 128};
+static const unsigned int bus_width_table[5] = {
+        8, 16, 32, 64, 128
+};
 #define TEGRA_DMA_NAME_SIZE 16
 struct tegra_dma_channel {
@@ -157,7 +161,7 @@ void tegra_dma_dequeue(struct tegra_dma_channel *ch)
        return;
 }
-void tegra_dma_stop(struct tegra_dma_channel *ch)
+static void tegra_dma_stop(struct tegra_dma_channel *ch)
 {
        u32 csr;
        u32 status;
@@ -174,7 +178,7 @@ void tegra_dma_stop(struct tegra_dma_channel *ch)
                writel(status, ch->addr + APB_DMA_CHAN_STA);
 }
-int tegra_dma_cancel(struct tegra_dma_channel *ch)
+static int tegra_dma_cancel(struct tegra_dma_channel *ch)
 {
        u32 csr;
        unsigned long irq_flags;
diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h
index 4cea2230c8dc..35a011fbc42d 100644
--- a/arch/arm/mach-tegra/include/mach/io.h
+++ b/arch/arm/mach-tegra/include/mach/io.h
@@ -33,20 +33,26 @@
 *
 */
+#ifdef __ASSEMBLY__
+#define IOMEM(x)        (x)
+#else
+#define IOMEM(x)        ((void __force __iomem *)(x))
+#endif
 #define IO_IRAM_PHYS    0x40000000
-#define IO_IRAM_VIRT    0xFE400000
+#define IO_IRAM_VIRT    IOMEM(0xFE400000)
 #define IO_IRAM_SIZE    SZ_256K
 #define IO_CPU_PHYS     0x50040000
-#define IO_CPU_VIRT     0xFE000000
+#define IO_CPU_VIRT     IOMEM(0xFE000000)
 #define IO_CPU_SIZE     SZ_16K
 #define IO_PPSB_PHYS    0x60000000
-#define IO_PPSB_VIRT    0xFE200000
+#define IO_PPSB_VIRT    IOMEM(0xFE200000)
 #define IO_PPSB_SIZE    SZ_1M
 #define IO_APB_PHYS     0x70000000
-#define IO_APB_VIRT     0xFE300000
+#define IO_APB_VIRT     IOMEM(0xFE300000)
 #define IO_APB_SIZE     SZ_1M
 #define IO_TO_VIRT_BETWEEN(p, st, sz)   ((p) >= (st) && (p) < ((st) + (sz)))
@@ -61,7 +67,7 @@
                IO_TO_VIRT_XLATE((n), IO_CPU_PHYS, IO_CPU_VIRT) :       \
        IO_TO_VIRT_BETWEEN((n), IO_IRAM_PHYS, IO_IRAM_SIZE) ?           \
                IO_TO_VIRT_XLATE((n), IO_IRAM_PHYS, IO_IRAM_VIRT) :     \
-        0)
+        NULL)
 #ifndef __ASSEMBLER__
@@ -71,7 +77,7 @@
 void __iomem *tegra_ioremap(unsigned long phys, size_t size, unsigned int type);
 void tegra_iounmap(volatile void __iomem *addr);
-#define IO_ADDRESS(n) ((void __iomem *) IO_TO_VIRT(n))
+#define IO_ADDRESS(n) (IO_TO_VIRT(n))
 #ifdef CONFIG_TEGRA_PCI
 extern void __iomem *tegra_pcie_io_base;
diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h
index defd8775defa..bb7dfdb61205 100644
--- a/arch/arm/mach-tegra/include/mach/pinmux.h
+++ b/arch/arm/mach-tegra/include/mach/pinmux.h
@@ -199,6 +199,7 @@ struct tegra_drive_pingroup_config {
 struct tegra_drive_pingroup_desc {
        const char *name;
+        s16 reg_bank;
        s16 reg;
 };
@@ -207,6 +208,9 @@ struct tegra_pingroup_desc {
        int funcs[4];
        int func_safe;
        int vddio;
+        s16 tri_bank;   /* Register bank the tri_reg exists within */
+        s16 mux_bank;   /* Register bank the mux_reg exists within */
+        s16 pupd_bank;  /* Register bank the pupd_reg exists within */
        s16 tri_reg;    /* offset into the TRISTATE_REG_* register bank */
        s16 mux_reg;    /* offset into the PIN_MUX_CTL_* register bank */
        s16 pupd_reg;   /* offset into the PULL_UPDOWN_REG_* register bank */
diff --git a/arch/arm/mach-tegra/include/mach/powergate.h b/arch/arm/mach-tegra/include/mach/powergate.h
index 401d1b725291..39c396d2ddb0 100644
--- a/arch/arm/mach-tegra/include/mach/powergate.h
+++ b/arch/arm/mach-tegra/include/mach/powergate.h
@@ -31,7 +31,6 @@
 int tegra_powergate_power_on(int id);
 int tegra_powergate_power_off(int id);
-bool tegra_powergate_is_powered(int id);
 int tegra_powergate_remove_clamping(int id);
 /* Must be called with clk disabled, and returns with clk enabled */
diff --git a/arch/arm/mach-tegra/io.c b/arch/arm/mach-tegra/io.c
index ea50fe28cf6a..5489f8b5d6ad 100644
--- a/arch/arm/mach-tegra/io.c
+++ b/arch/arm/mach-tegra/io.c
@@ -31,25 +31,25 @@
 static struct map_desc tegra_io_desc[] __initdata = {
        {
-                .virtual = IO_PPSB_VIRT,
+                .virtual = (unsigned long)IO_PPSB_VIRT,
                .pfn = __phys_to_pfn(IO_PPSB_PHYS),
                .length = IO_PPSB_SIZE,
                .type = MT_DEVICE,
        },
        {
-                .virtual = IO_APB_VIRT,
+                .virtual = (unsigned long)IO_APB_VIRT,
                .pfn = __phys_to_pfn(IO_APB_PHYS),
                .length = IO_APB_SIZE,
                .type = MT_DEVICE,
        },
        {
-                .virtual = IO_CPU_VIRT,
+                .virtual = (unsigned long)IO_CPU_VIRT,
                .pfn = __phys_to_pfn(IO_CPU_PHYS),
                .length = IO_CPU_SIZE,
                .type = MT_DEVICE,
        },
        {
-                .virtual = IO_IRAM_VIRT,
+                .virtual = (unsigned long)IO_IRAM_VIRT,
                .pfn = __phys_to_pfn(IO_IRAM_PHYS),
                .length = IO_IRAM_SIZE,
                .type = MT_DEVICE,
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index f1f699d86c32..f5aa173c26b3 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -41,6 +41,8 @@
 #include <mach/clk.h>
 #include <mach/powergate.h>
+#include "board.h"
 /* register definitions */
 #define AFI_OFFSET      0x3800
 #define PADS_OFFSET     0x3000
@@ -150,9 +152,9 @@
 static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
 #define pmc_writel(value, reg) \
-        __raw_writel(value, (u32)reg_pmc_base + (reg))
+        __raw_writel(value, reg_pmc_base + (reg))
 #define pmc_readl(reg) \
-        __raw_readl((u32)reg_pmc_base + (reg))
+        __raw_readl(reg_pmc_base + (reg))
 /*
 * Tegra2 defines 1GB in the AXI address map for PCIe.
@@ -460,7 +462,7 @@ static struct pci_bus __init *tegra_pcie_scan_bus(int nr,
        struct tegra_pcie_port *pp;
        if (nr >= tegra_pcie.num_ports)
-                return 0;
+                return NULL;
        pp = tegra_pcie.port + nr;
        pp->root_bus_nr = sys->busnr;
diff --git a/arch/arm/mach-tegra/pinmux-t2-tables.c b/arch/arm/mach-tegra/pinmux-t2-tables.c
index a475367befa3..a0dc2bc28ed3 100644
--- a/arch/arm/mach-tegra/pinmux-t2-tables.c
+++ b/arch/arm/mach-tegra/pinmux-t2-tables.c
@@ -31,10 +31,16 @@
 #include <mach/pinmux.h>
 #include <mach/suspend.h>
+#define TRISTATE_REG_A          0x14
+#define PIN_MUX_CTL_REG_A       0x80
+#define PULLUPDOWN_REG_A        0xa0
+#define PINGROUP_REG_A          0x868
 #define DRIVE_PINGROUP(pg_name, r)                              \
        [TEGRA_DRIVE_PINGROUP_ ## pg_name] = {                  \
                .name = #pg_name,                               \
-                .reg = r                                        \
+                .reg_bank = 3,                                  \
+                .reg = ((r) - PINGROUP_REG_A)                   \
        }
 const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
@@ -90,11 +96,14 @@ const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE
                        TEGRA_MUX_ ## f3,                       \
                },                                              \
                .func_safe = TEGRA_MUX_ ## f_safe,              \
-                .tri_reg = tri_r,                               \
+                .tri_bank = 0,                                  \
+                .tri_reg = ((tri_r) - TRISTATE_REG_A),          \
                .tri_bit = tri_b,                               \
-                .mux_reg = mux_r,                               \
+                .mux_bank = 1,                                  \
+                .mux_reg = ((mux_r) - PIN_MUX_CTL_REG_A),       \
                .mux_bit = mux_b,                               \
-                .pupd_reg = pupd_r,                             \
+                .pupd_bank = 2,                         \
+                .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A),      \
                .pupd_bit = pupd_b,                             \
        }
@@ -217,62 +226,3 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
        PINGROUP(XM2C,  DDR,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xA8, 30),
        PINGROUP(XM2D,  DDR,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xA8, 28),
 };
-#ifdef CONFIG_PM
-#define TRISTATE_REG_A         0x14
-#define TRISTATE_REG_NUM       4
-#define PIN_MUX_CTL_REG_A      0x80
-#define PIN_MUX_CTL_REG_NUM    8
-#define PULLUPDOWN_REG_A       0xa0
-#define PULLUPDOWN_REG_NUM     5
-static u32 pinmux_reg[TRISTATE_REG_NUM + PIN_MUX_CTL_REG_NUM +
-                      PULLUPDOWN_REG_NUM +
-                      ARRAY_SIZE(tegra_soc_drive_pingroups)];
-static inline unsigned long pg_readl(unsigned long offset)
-{
-        return readl(IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset));
-}
-static inline void pg_writel(unsigned long value, unsigned long offset)
-{
-        writel(value, IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset));
-}
-void tegra_pinmux_suspend(void)
-{
-        unsigned int i;
-        u32 *ctx = pinmux_reg;
-        for (i = 0; i < PIN_MUX_CTL_REG_NUM; i++)
-                *ctx++ = pg_readl(PIN_MUX_CTL_REG_A + i*4);
-        for (i = 0; i < PULLUPDOWN_REG_NUM; i++)
-                *ctx++ = pg_readl(PULLUPDOWN_REG_A + i*4);
-        for (i = 0; i < TRISTATE_REG_NUM; i++)
-                *ctx++ = pg_readl(TRISTATE_REG_A + i*4);
-        for (i = 0; i < ARRAY_SIZE(tegra_soc_drive_pingroups); i++)
-                *ctx++ = pg_readl(tegra_soc_drive_pingroups[i].reg);
-}
-void tegra_pinmux_resume(void)
-{
-        unsigned int i;
-        u32 *ctx = pinmux_reg;
-        for (i = 0; i < PIN_MUX_CTL_REG_NUM; i++)
-                pg_writel(*ctx++, PIN_MUX_CTL_REG_A + i*4);
-        for (i = 0; i < PULLUPDOWN_REG_NUM; i++)
-                pg_writel(*ctx++, PULLUPDOWN_REG_A + i*4);
-        for (i = 0; i < TRISTATE_REG_NUM; i++)
-                pg_writel(*ctx++, TRISTATE_REG_A + i*4);
-        for (i = 0; i < ARRAY_SIZE(tegra_soc_drive_pingroups); i++)
-                pg_writel(*ctx++, tegra_soc_drive_pingroups[i].reg);
-}
-#endif
diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c
index f80d507671bc..1d201650d7a4 100644
--- a/arch/arm/mach-tegra/pinmux.c
+++ b/arch/arm/mach-tegra/pinmux.c
@@ -20,6 +20,7 @@
 #include <linux/errno.h>
 #include <linux/spinlock.h>
 #include <linux/io.h>
+#include <linux/platform_device.h>
 #include <mach/iomap.h>
 #include <mach/pinmux.h>
@@ -169,15 +170,17 @@ static const char *pupd_name(unsigned long val)
        }
 }
+static int nbanks;
+static void __iomem **regs;
-static inline unsigned long pg_readl(unsigned long offset)
+static inline u32 pg_readl(u32 bank, u32 reg)
 {
-        return readl(IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset));
+        return readl(regs[bank] + reg);
 }
-static inline void pg_writel(unsigned long value, unsigned long offset)
+static inline void pg_writel(u32 val, u32 bank, u32 reg)
 {
-        writel(value, IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset));
+        writel(val, regs[bank] + reg);
 }
 static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
@@ -217,10 +220,10 @@ static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
        spin_lock_irqsave(&mux_lock, flags);
-        reg = pg_readl(pingroups[pg].mux_reg);
+        reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
        reg &= ~(0x3 << pingroups[pg].mux_bit);
        reg |= mux << pingroups[pg].mux_bit;
-        pg_writel(reg, pingroups[pg].mux_reg);
+        pg_writel(reg, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
        spin_unlock_irqrestore(&mux_lock, flags);
@@ -241,11 +244,11 @@ int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
        spin_lock_irqsave(&mux_lock, flags);
-        reg = pg_readl(pingroups[pg].tri_reg);
+        reg = pg_readl(pingroups[pg].tri_bank, pingroups[pg].tri_reg);
        reg &= ~(0x1 << pingroups[pg].tri_bit);
        if (tristate)
                reg |= 1 << pingroups[pg].tri_bit;
-        pg_writel(reg, pingroups[pg].tri_reg);
+        pg_writel(reg, pingroups[pg].tri_bank, pingroups[pg].tri_reg);
        spin_unlock_irqrestore(&mux_lock, flags);
@@ -272,10 +275,10 @@ int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
        spin_lock_irqsave(&mux_lock, flags);
-        reg = pg_readl(pingroups[pg].pupd_reg);
+        reg = pg_readl(pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
        reg &= ~(0x3 << pingroups[pg].pupd_bit);
        reg |= pupd << pingroups[pg].pupd_bit;
-        pg_writel(reg, pingroups[pg].pupd_reg);
+        pg_writel(reg, pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
        spin_unlock_irqrestore(&mux_lock, flags);
@@ -362,12 +365,12 @@ static int tegra_drive_pinmux_set_hsm(enum tegra_drive_pingroup pg,
        spin_lock_irqsave(&mux_lock, flags);
-        reg = pg_readl(drive_pingroups[pg].reg);
+        reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
        if (hsm == TEGRA_HSM_ENABLE)
                reg |= (1 << 2);
        else
                reg &= ~(1 << 2);
-        pg_writel(reg, drive_pingroups[pg].reg);
+        pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
        spin_unlock_irqrestore(&mux_lock, flags);
@@ -387,12 +390,12 @@ static int tegra_drive_pinmux_set_schmitt(enum tegra_drive_pingroup pg,
        spin_lock_irqsave(&mux_lock, flags);
-        reg = pg_readl(drive_pingroups[pg].reg);
+        reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
        if (schmitt == TEGRA_SCHMITT_ENABLE)
                reg |= (1 << 3);
        else
                reg &= ~(1 << 3);
-        pg_writel(reg, drive_pingroups[pg].reg);
+        pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
        spin_unlock_irqrestore(&mux_lock, flags);
@@ -412,10 +415,10 @@ static int tegra_drive_pinmux_set_drive(enum tegra_drive_pingroup pg,
        spin_lock_irqsave(&mux_lock, flags);
-        reg = pg_readl(drive_pingroups[pg].reg);
+        reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
        reg &= ~(0x3 << 4);
        reg |= drive << 4;
-        pg_writel(reg, drive_pingroups[pg].reg);
+        pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
        spin_unlock_irqrestore(&mux_lock, flags);
@@ -435,10 +438,10 @@ static int tegra_drive_pinmux_set_pull_down(enum tegra_drive_pingroup pg,
        spin_lock_irqsave(&mux_lock, flags);
-        reg = pg_readl(drive_pingroups[pg].reg);
+        reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
        reg &= ~(0x1f << 12);
        reg |= pull_down << 12;
-        pg_writel(reg, drive_pingroups[pg].reg);
+        pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
        spin_unlock_irqrestore(&mux_lock, flags);
@@ -458,10 +461,10 @@ static int tegra_drive_pinmux_set_pull_up(enum tegra_drive_pingroup pg,
        spin_lock_irqsave(&mux_lock, flags);
-        reg = pg_readl(drive_pingroups[pg].reg);
+        reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
        reg &= ~(0x1f << 12);
        reg |= pull_up << 12;
-        pg_writel(reg, drive_pingroups[pg].reg);
+        pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
        spin_unlock_irqrestore(&mux_lock, flags);
@@ -481,10 +484,10 @@ static int tegra_drive_pinmux_set_slew_rising(enum tegra_drive_pingroup pg,
        spin_lock_irqsave(&mux_lock, flags);
-        reg = pg_readl(drive_pingroups[pg].reg);
+        reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
        reg &= ~(0x3 << 28);
        reg |= slew_rising << 28;
-        pg_writel(reg, drive_pingroups[pg].reg);
+        pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
        spin_unlock_irqrestore(&mux_lock, flags);
@@ -504,10 +507,10 @@ static int tegra_drive_pinmux_set_slew_falling(enum tegra_drive_pingroup pg,
        spin_lock_irqsave(&mux_lock, flags);
-        reg = pg_readl(drive_pingroups[pg].reg);
+        reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
        reg &= ~(0x3 << 30);
        reg |= slew_falling << 30;
-        pg_writel(reg, drive_pingroups[pg].reg);
+        pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
        spin_unlock_irqrestore(&mux_lock, flags);
@@ -665,6 +668,99 @@ void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *co
        }
 }
+static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
+{
+        struct resource *res;
+        int i;
+        int config_bad = 0;
+        for (i = 0; ; i++) {
+                res = platform_get_resource(pdev, IORESOURCE_MEM, i);
+                if (!res)
+                        break;
+        }
+        nbanks = i;
+        for (i = 0; i < TEGRA_MAX_PINGROUP; i++) {
+                if (pingroups[i].tri_bank >= nbanks) {
+                        dev_err(&pdev->dev, "pingroup %d: bad tri_bank\n", i);
+                        config_bad = 1;
+                }
+                if (pingroups[i].mux_bank >= nbanks) {
+                        dev_err(&pdev->dev, "pingroup %d: bad mux_bank\n", i);
+                        config_bad = 1;
+                }
+                if (pingroups[i].pupd_bank >= nbanks) {
+                        dev_err(&pdev->dev, "pingroup %d: bad pupd_bank\n", i);
+                        config_bad = 1;
+                }
+        }
+        for (i = 0; i < TEGRA_MAX_DRIVE_PINGROUP; i++) {
+                if (drive_pingroups[i].reg_bank >= nbanks) {
+                        dev_err(&pdev->dev,
+                                "drive pingroup %d: bad reg_bank\n", i);
+                        config_bad = 1;
+                }
+        }
+        if (config_bad)
+                return -ENODEV;
+        regs = devm_kzalloc(&pdev->dev, nbanks * sizeof(*regs), GFP_KERNEL);
+        if (!regs) {
+                dev_err(&pdev->dev, "Can't alloc regs pointer\n");
+                return -ENODEV;
+        }
+        for (i = 0; i < nbanks; i++) {
+                res = platform_get_resource(pdev, IORESOURCE_MEM, i);
+                if (!res) {
+                        dev_err(&pdev->dev, "Missing MEM resource\n");
+                        return -ENODEV;
+                }
+                if (!devm_request_mem_region(&pdev->dev, res->start,
+                                            resource_size(res),
+                                            dev_name(&pdev->dev))) {
+                        dev_err(&pdev->dev,
+                                "Couldn't request MEM resource %d\n", i);
+                        return -ENODEV;
+                }
+                regs[i] = devm_ioremap(&pdev->dev, res->start,
+                                        resource_size(res));
+                if (!regs) {
+                        dev_err(&pdev->dev, "Couldn't ioremap regs %d\n", i);
+                        return -ENODEV;
+                }
+        }
+        return 0;
+}
+static struct of_device_id tegra_pinmux_of_match[] __devinitdata = {
+        { .compatible = "nvidia,tegra20-pinmux", },
+        { },
+};
+static struct platform_driver tegra_pinmux_driver = {
+        .driver         = {
+                .name   = "tegra-pinmux",
+                .owner  = THIS_MODULE,
+                .of_match_table = tegra_pinmux_of_match,
+        },
+        .probe          = tegra_pinmux_probe,
+};
+static int __init tegra_pinmux_init(void)
+{
+        return platform_driver_register(&tegra_pinmux_driver);
+}
+postcore_initcall(tegra_pinmux_init);
 #ifdef  CONFIG_DEBUG_FS
 #include <linux/debugfs.h>
@@ -684,6 +780,7 @@ static int dbg_pinmux_show(struct seq_file *s, void *unused)
        int len;
        for (i = 0; i < TEGRA_MAX_PINGROUP; i++) {
+                unsigned long reg;
                unsigned long tri;
                unsigned long mux;
                unsigned long pupd;
@@ -696,8 +793,9 @@ static int dbg_pinmux_show(struct seq_file *s, void *unused)
                        seq_printf(s, "TEGRA_MUX_NONE");
                        len = strlen("NONE");
                } else {
-                        mux = (pg_readl(pingroups[i].mux_reg) >>
+                        reg = pg_readl(pingroups[i].mux_bank,
-                               pingroups[i].mux_bit) & 0x3;
+                                        pingroups[i].mux_reg);
+                        mux = (reg >> pingroups[i].mux_bit) & 0x3;
                        if (pingroups[i].funcs[mux] == TEGRA_MUX_RSVD) {
                                seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux+1);
                                len = 5;
@@ -713,8 +811,9 @@ static int dbg_pinmux_show(struct seq_file *s, void *unused)
                        seq_printf(s, "TEGRA_PUPD_NORMAL");
                        len = strlen("NORMAL");
                } else {
-                        pupd = (pg_readl(pingroups[i].pupd_reg) >>
+                        reg = pg_readl(pingroups[i].pupd_bank,
-                                pingroups[i].pupd_bit) & 0x3;
+                                        pingroups[i].pupd_reg);
+                        pupd = (reg >> pingroups[i].pupd_bit) & 0x3;
                        seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd));
                        len = strlen(pupd_name(pupd));
                }
@@ -723,8 +822,9 @@ static int dbg_pinmux_show(struct seq_file *s, void *unused)
                if (pingroups[i].tri_reg < 0) {
                        seq_printf(s, "TEGRA_TRI_NORMAL");
                } else {
-                        tri = (pg_readl(pingroups[i].tri_reg) >>
+                        reg = pg_readl(pingroups[i].tri_bank,
-                               pingroups[i].tri_bit) & 0x1;
+                                        pingroups[i].tri_reg);
+                        tri = (reg >> pingroups[i].tri_bit) & 0x1;
                        seq_printf(s, "TEGRA_TRI_%s", tri_name(tri));
                }
@@ -759,7 +859,8 @@ static int dbg_drive_pinmux_show(struct seq_file *s, void *unused)
                dbg_pad_field(s, 7 - len);
-                reg = pg_readl(drive_pingroups[i].reg);
+                reg = pg_readl(drive_pingroups[i].reg_bank,
+                                drive_pingroups[i].reg);
                if (HSM_EN(reg)) {
                        seq_printf(s, "TEGRA_HSM_ENABLE");
                        len = 16;
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index 3cee9aa1f2c8..948306491a59 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -89,12 +89,11 @@ int tegra_powergate_power_off(int id)
        return tegra_powergate_set(id, false);
 }
-bool tegra_powergate_is_powered(int id)
+static bool tegra_powergate_is_powered(int id)
 {
        u32 status;
-        if (id < 0 || id >= TEGRA_NUM_POWERGATE)
+        WARN_ON(id < 0 || id >= TEGRA_NUM_POWERGATE);
-                return -EINVAL;
        status = pmc_read(PWRGATE_STATUS) & (1 << id);
        return !!status;
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 0fe9b3ee2947..371869d8ea01 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -166,13 +166,13 @@ static DEFINE_SPINLOCK(clock_register_lock);
 static int tegra_periph_clk_enable_refcount[3 * 32];
 #define clk_writel(value, reg) \
-        __raw_writel(value, (u32)reg_clk_base + (reg))
+        __raw_writel(value, reg_clk_base + (reg))
 #define clk_readl(reg) \
-        __raw_readl((u32)reg_clk_base + (reg))
+        __raw_readl(reg_clk_base + (reg))
 #define pmc_writel(value, reg) \
-        __raw_writel(value, (u32)reg_pmc_base + (reg))
+        __raw_writel(value, reg_pmc_base + (reg))
 #define pmc_readl(reg) \
-        __raw_readl((u32)reg_pmc_base + (reg))
+        __raw_readl(reg_pmc_base + (reg))
 unsigned long clk_measure_input_freq(void)
 {
@@ -918,7 +918,7 @@ static struct clk_ops tegra_pll_div_ops = {
 static void tegra2_periph_clk_init(struct clk *c)
 {
        u32 val = clk_readl(c->reg);
-        const struct clk_mux_sel *mux = 0;
+        const struct clk_mux_sel *mux = NULL;
        const struct clk_mux_sel *sel;
        if (c->flags & MUX) {
                for (sel = c->inputs; sel->input != NULL; sel++) {
@@ -1459,7 +1459,7 @@ static struct clk tegra_pll_s = {
 static struct clk_mux_sel tegra_clk_m_sel[] = {
        { .input = &tegra_clk_32k, .value = 0},
        { .input = &tegra_pll_s,  .value = 1},
-        { 0, 0},
+        { NULL , 0},
 };
 static struct clk tegra_clk_m = {
@@ -1861,7 +1861,7 @@ static const struct audio_sources {
        { .name = "ext_audio_clk1", .value = 6 },
        { .name = "ext_vimclk", .value = 7 },
 #endif
-        { 0, 0 }
+        { NULL, 0 }
 };
 static struct clk tegra_clk_audio = {
@@ -1885,7 +1885,7 @@ static struct clk tegra_clk_audio_2x = {
        },
 };
-struct clk_lookup tegra_audio_clk_lookups[] = {
+static struct clk_lookup tegra_audio_clk_lookups[] = {
        { .con_id = "audio", .clk = &tegra_clk_audio },
        { .con_id = "audio_2x", .clk = &tegra_clk_audio_2x }
 };
@@ -1926,7 +1926,7 @@ static struct clk_mux_sel mux_cclk[] = {
        { .input = &tegra_pll_p_out3,   .value = 6},
        { .input = &tegra_clk_d,        .value = 7},
        { .input = &tegra_pll_x,        .value = 8},
-        { 0, 0},
+        { NULL, 0},
 };
 static struct clk_mux_sel mux_sclk[] = {
@@ -1938,7 +1938,7 @@ static struct clk_mux_sel mux_sclk[] = {
        { .input = &tegra_clk_d,        .value = 5},
        { .input = &tegra_clk_32k,      .value = 6},
        { .input = &tegra_pll_m_out1,   .value = 7},
-        { 0, 0},
+        { NULL, 0},
 };
 static struct clk tegra_clk_cclk = {
@@ -2009,7 +2009,7 @@ static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
        { .input = &tegra_pll_c, .value = 1},
        { .input = &tegra_pll_p, .value = 2},
        { .input = &tegra_pll_a_out0, .value = 3},
-        { 0, 0},
+        { NULL, 0},
 };
 static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
@@ -2017,7 +2017,7 @@ static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
        { .input = &tegra_pll_c, .value = 1},
        { .input = &tegra_pll_p, .value = 2},
        { .input = &tegra_clk_m, .value = 3},
-        { 0, 0},
+        { NULL, 0},
 };
 static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
@@ -2025,7 +2025,7 @@ static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
        { .input = &tegra_pll_c, .value = 1},
        { .input = &tegra_pll_m, .value = 2},
        { .input = &tegra_clk_m, .value = 3},
-        { 0, 0},
+        { NULL, 0},
 };
 static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = {
@@ -2033,7 +2033,7 @@ static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = {
        {.input = &tegra_clk_audio_2x, .value = 1},
        {.input = &tegra_pll_p, .value = 2},
        {.input = &tegra_clk_m, .value = 3},
-        { 0, 0},
+        { NULL, 0},
 };
 static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
@@ -2041,7 +2041,7 @@ static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
        {.input = &tegra_pll_d_out0, .value = 1},
        {.input = &tegra_pll_c, .value = 2},
        {.input = &tegra_clk_m, .value = 3},
-        { 0, 0},
+        { NULL, 0},
 };
 static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
@@ -2050,39 +2050,39 @@ static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
        {.input = &tegra_clk_audio,     .value = 2},
        {.input = &tegra_clk_m,     .value = 3},
        {.input = &tegra_clk_32k,   .value = 4},
-        { 0, 0},
+        { NULL, 0},
 };
 static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
        {.input = &tegra_pll_p,     .value = 0},
        {.input = &tegra_pll_c,     .value = 1},
        {.input = &tegra_pll_m,     .value = 2},
-        { 0, 0},
+        { NULL, 0},
 };
 static struct clk_mux_sel mux_clk_m[] = {
        { .input = &tegra_clk_m, .value = 0},
-        { 0, 0},
+        { NULL, 0},
 };
 static struct clk_mux_sel mux_pllp_out3[] = {
        { .input = &tegra_pll_p_out3, .value = 0},
-        { 0, 0},
+        { NULL, 0},
 };
 static struct clk_mux_sel mux_plld[] = {
        { .input = &tegra_pll_d, .value = 0},
-        { 0, 0},
+        { NULL, 0},
 };
 static struct clk_mux_sel mux_clk_32k[] = {
        { .input = &tegra_clk_32k, .value = 0},
-        { 0, 0},
+        { NULL, 0},
 };
 static struct clk_mux_sel mux_pclk[] = {
        { .input = &tegra_clk_pclk, .value = 0},
-        { 0, 0},
+        { NULL, 0},
 };
 static struct clk tegra_clk_emc = {
@@ -2125,7 +2125,7 @@ static struct clk tegra_clk_emc = {
                .parent = _parent,                      \
        }
-struct clk tegra_list_clks[] = {
+static struct clk tegra_list_clks[] = {
        PERIPH_CLK("apbdma",    "tegra-dma",            NULL,   34,     0,      108000000, mux_pclk,                    0),
        PERIPH_CLK("rtc",       "rtc-tegra",            NULL,   4,      0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET),
        PERIPH_CLK("timer",     "timer",                NULL,   5,      0,      26000000,  mux_clk_m,                   0),
@@ -2221,7 +2221,7 @@ struct clk tegra_list_clks[] = {
 * configuration.  List those here to register them twice in the clock lookup
 * table under two names.
 */
-struct clk_duplicate tegra_clk_duplicates[] = {
+static struct clk_duplicate tegra_clk_duplicates[] = {
        CLK_DUPLICATE("uarta",  "tegra_uart.0", NULL),
        CLK_DUPLICATE("uartb",  "tegra_uart.1", NULL),
        CLK_DUPLICATE("uartc",  "tegra_uart.2", NULL),
@@ -2252,7 +2252,7 @@ struct clk_duplicate tegra_clk_duplicates[] = {
                .clk = ck,      \
        }
-struct clk *tegra_ptr_clks[] = {
+static struct clk *tegra_ptr_clks[] = {
        &tegra_clk_32k,
        &tegra_pll_s,
        &tegra_clk_m,
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c
index 90350420c4e9..e2272d263a83 100644
--- a/arch/arm/mach-tegra/timer.c
+++ b/arch/arm/mach-tegra/timer.c
@@ -62,9 +62,9 @@ static struct timespec persistent_ts;
 static u64 persistent_ms, last_persistent_ms;
 #define timer_writel(value, reg) \
-        __raw_writel(value, (u32)timer_reg_base + (reg))
+        __raw_writel(value, timer_reg_base + (reg))
 #define timer_readl(reg) \
-        __raw_readl((u32)timer_reg_base + (reg))
+        __raw_readl(timer_reg_base + (reg))
 static int tegra_timer_set_next_event(unsigned long cycles,
                                         struct clock_event_device *evt)
@@ -133,7 +133,7 @@ static void notrace tegra_update_sched_clock(void)
 * tegra_rtc driver could be executing to avoid race conditions
 * on the RTC shadow register
 */
-u64 tegra_rtc_read_ms(void)
+static u64 tegra_rtc_read_ms(void)
 {
        u32 ms = readl(rtc_base + RTC_MILLISECONDS);
        u32 s = readl(rtc_base + RTC_SHADOW_SECONDS);
diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig
index d6e5d306557b..1cbcd4fc1e17 100644
--- a/arch/arm/mach-u300/Kconfig
+++ b/arch/arm/mach-u300/Kconfig
@@ -51,39 +51,12 @@ config MACH_U300_BS365
 endchoice
-choice
-        prompt "Memory configuration"
-        default MACH_U300_SINGLE_RAM
-        ---help---
-        You have to config the kernel according to the physical memory
-        configuration.
-config MACH_U300_SINGLE_RAM
-        bool "Single RAM"
-        help
-                Select this if you want support for Single RAM phones.
-config MACH_U300_DUAL_RAM
-        bool "Dual RAM"
-        help
-                Select this if you want support for Dual RAM phones.
-                This is two RAM memories on different EMIFs.
-endchoice
 config U300_DEBUG
        bool "Debug support for U300"
        depends on PM
        help
                Debug support for U300 in sysfs, procfs etc.
-config MACH_U300_SEMI_IS_SHARED
-        bool "The SEMI is used by both the access and application side"
-        depends on MACH_U300
-        help
-                This makes it possible to use the SEMI (Shared External
-                Memory Interface) from both from access and application
-                side.
 config MACH_U300_SPIDUMMY
        bool "SSP/SPI dummy chip"
        select SPI
@@ -96,25 +69,6 @@ config MACH_U300_SPIDUMMY
                you don't need it. Selecting this will activate the
                SPI framework and ARM PL022 support.
-comment "All the settings below must match the bootloader's settings"
-config MACH_U300_ACCESS_MEM_SIZE
-       int "Access CPU memory allocation"
-       range 7 25
-       depends on MACH_U300_SINGLE_RAM
-       default 13
-       help
-                How much memory in MiB that the Access side CPU has allocated
-config MACH_U300_2MB_ALIGNMENT_FIX
-       bool "2MiB alignment fix"
-       depends on MACH_U300_SINGLE_RAM
-       default y
-       help
-                If yes and the Access side CPU has allocated an odd size in
-                MiB, this fix gives you one MiB extra that would otherwise be
-                lost due to Linux 2 MiB alignment policy.
 endmenu
 endif
diff --git a/arch/arm/mach-u300/Makefile.boot b/arch/arm/mach-u300/Makefile.boot
index 69357affbd77..87811de0bd94 100644
--- a/arch/arm/mach-u300/Makefile.boot
+++ b/arch/arm/mach-u300/Makefile.boot
@@ -1,15 +1,4 @@
-# Note: the following conditions must always be true:
+   zreladdr-y   += 0x48008000
-#   ZRELADDR == virt_to_phys(TEXTADDR)
+params_phys-y   := 0x48000100
-#   PARAMS_PHYS must be within 4MB of ZRELADDR
-#   INITRD_PHYS must be in RAM
-ifdef CONFIG_MACH_U300_SINGLE_RAM
-     zreladdr-y += 0x28E08000
-  params_phys-y := 0x28E00100
-else
-     zreladdr-y += 0x48008000
-  params_phys-y := 0x48000100
-endif
 # This isn't used.
-#initrd_phys-y  := 0x29800000
+#initrd_phys-y  := 0x48800000
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index f4ad6d2e26f3..ac0791e924bc 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -72,25 +72,6 @@ static struct map_desc u300_io_desc[] __initdata = {
                .length         = SZ_32K,
                .type           = MT_DEVICE,
        },
-        {
-                .virtual        = 0xffff2000, /* TCM memory */
-                .pfn            = __phys_to_pfn(0xffff2000),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        },
-        /*
-         * This overlaps with the IRQ vectors etc at 0xffff0000, so these
-         * may have to be moved to 0x00000000 in order to use the ROM.
-         */
-        /*
-        {
-                .virtual        = U300_BOOTROM_VIRT_BASE,
-                .pfn            = __phys_to_pfn(U300_BOOTROM_PHYS_BASE),
-                .length         = SZ_64K,
-                .type           = MT_ROM,
-        },
-        */
 };
 void __init u300_map_io(void)
@@ -367,51 +348,6 @@ static struct resource wdog_resources[] = {
        }
 };
-/* TODO: These should be protected by suitable #ifdef's */
-static struct resource ave_resources[] = {
-        {
-                .name  = "AVE3e I/O Area",
-                .start = U300_VIDEOENC_BASE,
-                .end   = U300_VIDEOENC_BASE + SZ_512K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name  = "AVE3e IRQ0",
-                .start = IRQ_U300_VIDEO_ENC_0,
-                .end   = IRQ_U300_VIDEO_ENC_0,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name  = "AVE3e IRQ1",
-                .start = IRQ_U300_VIDEO_ENC_1,
-                .end   = IRQ_U300_VIDEO_ENC_1,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name  = "AVE3e Physmem Area",
-                .start = 0, /* 0 will be remapped to reserved memory */
-                .end   = SZ_1M - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        /*
-         * The AVE3e requires two regions of 256MB that it considers
-         * "invisible". The hardware will not be able to access these
-         * addresses, so they should never point to system RAM.
-         */
-        {
-                .name  = "AVE3e Reserved 0",
-                .start = 0xd0000000,
-                .end   = 0xd0000000 + SZ_256M - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name  = "AVE3e Reserved 1",
-                .start = 0xe0000000,
-                .end   = 0xe0000000 + SZ_256M - 1,
-                .flags = IORESOURCE_MEM,
-        },
-};
 static struct resource dma_resource[] = {
        {
                .start = U300_DMAC_BASE,
@@ -1650,13 +1586,6 @@ static struct platform_device nand_device = {
        },
 };
-static struct platform_device ave_device = {
-        .name = "video_enc",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(ave_resources),
-        .resource = ave_resources,
-};
 static struct platform_device dma_device = {
        .name           = "coh901318",
        .id             = -1,
@@ -1747,7 +1676,6 @@ static struct platform_device *platform_devs[] __initdata = {
        &gpio_device,
        &nand_device,
        &wdog_device,
-        &ave_device,
        &pinmux_device,
 };
@@ -1945,17 +1873,10 @@ void __init u300_init_devices(void)
        /* Register subdevices on the SPI bus */
        u300_spi_register_board_devices();
-#ifndef CONFIG_MACH_U300_SEMI_IS_SHARED
+        /* Enable SEMI self refresh */
-        /*
-         * Enable SEMI self refresh. Self-refresh of the SDRAM is entered when
-         * both subsystems are requesting this mode.
-         * If we not share the Acc SDRAM, this is never the case. Therefore
-         * enable it here from the App side.
-         */
        val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
                U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
        writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
-#endif /* CONFIG_MACH_U300_SEMI_IS_SHARED */
 }
 static int core_module_init(void)
diff --git a/arch/arm/mach-u300/include/mach/memory.h b/arch/arm/mach-u300/include/mach/memory.h
index 7034bae95de6..c808f347a081 100644
--- a/arch/arm/mach-u300/include/mach/memory.h
+++ b/arch/arm/mach-u300/include/mach/memory.h
@@ -13,25 +13,7 @@
 #ifndef __MACH_MEMORY_H
 #define __MACH_MEMORY_H
-#ifdef CONFIG_MACH_U300_DUAL_RAM
+#define PLAT_PHYS_OFFSET        UL(0x48000000)
+#define BOOT_PARAMS_OFFSET      0x100
-#define PLAT_PHYS_OFFSET                UL(0x48000000)
-#define BOOT_PARAMS_OFFSET              0x100
-#else
-#ifdef CONFIG_MACH_U300_2MB_ALIGNMENT_FIX
-#define PLAT_PHYS_OFFSET (0x28000000 + \
-             (CONFIG_MACH_U300_ACCESS_MEM_SIZE - \
-             (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024)
-#define BOOT_PARAMS_OFFSET (0x100 + \
-             (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1)*1024*1024*2)
-#else
-#define PLAT_PHYS_OFFSET (0x28000000 + \
-             (CONFIG_MACH_U300_ACCESS_MEM_SIZE +        \
-             (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024)
-#define BOOT_PARAMS_OFFSET 0x100
-#endif
-#endif
 #endif
diff --git a/arch/arm/mach-u300/u300.c b/arch/arm/mach-u300/u300.c
index 80e7305589c6..89422ee7f3a8 100644
--- a/arch/arm/mach-u300/u300.c
+++ b/arch/arm/mach-u300/u300.c
@@ -23,21 +23,6 @@
 #include <asm/mach/arch.h>
 #include <asm/memory.h>
-static void __init u300_reserve(void)
-{
-        /*
-         * U300 - This platform family can share physical memory
-         * between two ARM cpus, one running Linux and the other
-         * running another OS.
-         */
-#ifdef CONFIG_MACH_U300_SINGLE_RAM
-#if ((CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1) == 1) && \
-        CONFIG_MACH_U300_2MB_ALIGNMENT_FIX
-        memblock_reserve(PHYS_OFFSET, 0x00100000);
-#endif
-#endif
-}
 static void __init u300_init_machine(void)
 {
        u300_init_devices();
@@ -63,7 +48,6 @@ MACHINE_START(U300, MACH_U300_STRING)
        /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
        .atag_offset    = BOOT_PARAMS_OFFSET,
        .map_io         = u300_map_io,
-        .reserve        = u300_reserve,
        .init_irq       = u300_init_irq,
        .timer          = &u300_timer,
        .init_machine   = u300_init_machine,
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 1694916e6822..6bd2f451c185 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -3,7 +3,8 @@
 #
 obj-y                           := clock.o cpu.o devices.o devices-common.o \
-                                   id.o usb.o
+                                   id.o usb.o timer.o
+obj-$(CONFIG_CACHE_L2X0)        += cache-l2x0.o
 obj-$(CONFIG_UX500_SOC_DB5500)  += cpu-db5500.o dma-db5500.o
 obj-$(CONFIG_UX500_SOC_DB8500)  += cpu-db8500.o devices-db8500.o
 obj-$(CONFIG_MACH_U8500)        += board-mop500.o board-mop500-sdi.o \
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index 15b23e4bd488..74bfcff2bdf3 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -153,7 +153,7 @@ static pin_cfg_t mop500_pins_default[] = {
        GPIO7_U1_RTSn   | PIN_OUTPUT_HIGH,
 };
-static pin_cfg_t mop500_pins_hrefv60[] = {
+static pin_cfg_t hrefv60_pins[] = {
        /* WLAN */
        GPIO4_GPIO              | PIN_INPUT_PULLUP,/* WLAN_IRQ */
        GPIO85_GPIO             | PIN_OUTPUT_LOW,/* WLAN_ENA */
@@ -279,14 +279,26 @@ static pin_cfg_t snowball_pins[] = {
 void __init mop500_pins_init(void)
 {
        nmk_config_pins(mop500_pins_common,
-                                ARRAY_SIZE(mop500_pins_common));
+                        ARRAY_SIZE(mop500_pins_common));
-        if (machine_is_hrefv60())
-                nmk_config_pins(mop500_pins_hrefv60,
+        nmk_config_pins(mop500_pins_default,
-                                ARRAY_SIZE(mop500_pins_hrefv60));
+                        ARRAY_SIZE(mop500_pins_default));
-        else if (machine_is_snowball())
+}
-                nmk_config_pins(snowball_pins,
-                                ARRAY_SIZE(snowball_pins));
+void __init snowball_pins_init(void)
-        else
+{
-                nmk_config_pins(mop500_pins_default,
+        nmk_config_pins(mop500_pins_common,
-                                ARRAY_SIZE(mop500_pins_default));
+                        ARRAY_SIZE(mop500_pins_common));
+        nmk_config_pins(snowball_pins,
+                        ARRAY_SIZE(snowball_pins));
+}
+void __init hrefv60_pins_init(void)
+{
+        nmk_config_pins(mop500_pins_common,
+                        ARRAY_SIZE(mop500_pins_common));
+        nmk_config_pins(hrefv60_pins,
+                        ARRAY_SIZE(hrefv60_pins));
 }
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index d0cb9e5eb87c..6826faeecc68 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -216,30 +216,48 @@ void __init mop500_sdi_init(void)
        /* PoP:ed eMMC on top of DB8500 v1.0 has problems with high speed */
        if (!cpu_is_u8500v10())
                mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
-        /* sdi2 on snowball is in ATL_B mode for FSMC (LAN) */
-        if (!machine_is_snowball())
+        db8500_add_sdi2(&mop500_sdi2_data, periphid);
-                db8500_add_sdi2(&mop500_sdi2_data, periphid);
        /* On-board eMMC */
        db8500_add_sdi4(&mop500_sdi4_data, periphid);
-        if (machine_is_hrefv60() || machine_is_snowball()) {
-                if (machine_is_hrefv60()) {
-                        mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO;
-                        sdi0_en = HREFV60_SDMMC_EN_GPIO;
-                        sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO;
-                } else if (machine_is_snowball()) {
-                        mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO;
-                        mop500_sdi0_data.cd_invert = true;
-                        sdi0_en = SNOWBALL_SDMMC_EN_GPIO;
-                        sdi0_vsel = SNOWBALL_SDMMC_1V8_3V_GPIO;
-                }
-                sdi0_configure();
-        }
        /*
         * On boards with the TC35892 GPIO expander, sdi0 will finally
         * be added when the TC35892 initializes and calls
         * mop500_sdi_tc35892_init() above.
         */
 }
+void __init snowball_sdi_init(void)
+{
+        u32 periphid = 0x10480180;
+        mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
+        /* On-board eMMC */
+        db8500_add_sdi4(&mop500_sdi4_data, periphid);
+        mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO;
+        mop500_sdi0_data.cd_invert = true;
+        sdi0_en = SNOWBALL_SDMMC_EN_GPIO;
+        sdi0_vsel = SNOWBALL_SDMMC_1V8_3V_GPIO;
+        sdi0_configure();
+}
+void __init hrefv60_sdi_init(void)
+{
+        u32 periphid = 0x10480180;
+        mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
+        db8500_add_sdi2(&mop500_sdi2_data, periphid);
+        /* On-board eMMC */
+        db8500_add_sdi4(&mop500_sdi4_data, periphid);
+        mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO;
+        sdi0_en = HREFV60_SDMMC_EN_GPIO;
+        sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO;
+        sdi0_configure();
+}
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index f67b83dd9010..bdd7b80dd7ad 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -604,28 +604,72 @@ static void __init mop500_init_machine(void)
 {
        int i2c0_devs;
+        mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
+        u8500_init_devices();
+        mop500_pins_init();
+        platform_add_devices(mop500_platform_devs,
+                        ARRAY_SIZE(mop500_platform_devs));
+        mop500_i2c_init();
+        mop500_sdi_init();
+        mop500_spi_init();
+        mop500_uart_init();
+        i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
+        i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
+        i2c_register_board_info(2, mop500_i2c2_devices,
+                                ARRAY_SIZE(mop500_i2c2_devices));
+        /* This board has full regulator constraints */
+        regulator_has_full_constraints();
+}
+static void __init snowball_init_machine(void)
+{
+        int i2c0_devs;
+        u8500_init_devices();
+        snowball_pins_init();
+        platform_add_devices(snowball_platform_devs,
+                        ARRAY_SIZE(snowball_platform_devs));
+        mop500_i2c_init();
+        snowball_sdi_init();
+        mop500_spi_init();
+        mop500_uart_init();
+        i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
+        i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
+        i2c_register_board_info(2, mop500_i2c2_devices,
+                                ARRAY_SIZE(mop500_i2c2_devices));
+        /* This board has full regulator constraints */
+        regulator_has_full_constraints();
+}
+static void __init hrefv60_init_machine(void)
+{
+        int i2c0_devs;
        /*
         * The HREFv60 board removed a GPIO expander and routed
         * all these GPIO pins to the internal GPIO controller
         * instead.
         */
-        if (!machine_is_snowball()) {
+        mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
-                if (machine_is_hrefv60())
-                        mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
-                else
-                        mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
-        }
        u8500_init_devices();
-        mop500_pins_init();
+        hrefv60_pins_init();
-        if (machine_is_snowball())
+        platform_add_devices(mop500_platform_devs,
-                platform_add_devices(snowball_platform_devs,
+                        ARRAY_SIZE(mop500_platform_devs));
-                                        ARRAY_SIZE(snowball_platform_devs));
-        else
-                platform_add_devices(mop500_platform_devs,
-                                        ARRAY_SIZE(mop500_platform_devs));
        mop500_i2c_init();
        mop500_sdi_init();
@@ -633,8 +677,8 @@ static void __init mop500_init_machine(void)
        mop500_uart_init();
        i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
-        if (machine_is_hrefv60())
-                i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
+        i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
        i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
        i2c_register_board_info(2, mop500_i2c2_devices,
@@ -659,7 +703,7 @@ MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+")
        .map_io         = u8500_map_io,
        .init_irq       = ux500_init_irq,
        .timer          = &ux500_timer,
-        .init_machine   = mop500_init_machine,
+        .init_machine   = hrefv60_init_machine,
 MACHINE_END
 MACHINE_START(SNOWBALL, "Calao Systems Snowball platform")
@@ -668,5 +712,5 @@ MACHINE_START(SNOWBALL, "Calao Systems Snowball platform")
        .init_irq       = ux500_init_irq,
        /* we re-use nomadik timer here */
        .timer          = &ux500_timer,
-        .init_machine   = mop500_init_machine,
+        .init_machine   = snowball_init_machine,
 MACHINE_END
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index ee77a8970c33..de18a2a23e6e 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -40,10 +40,13 @@
 struct i2c_board_info;
 extern void mop500_sdi_init(void);
+extern void snowball_sdi_init(void);
 extern void mop500_sdi_tc35892_init(void);
 void __init mop500_u8500uib_init(void);
 void __init mop500_stuib_init(void);
 void __init mop500_pins_init(void);
+void __init hrefv60_pins_init(void);
+void __init snowball_pins_init(void);
 void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
                unsigned n);
diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
new file mode 100644
index 000000000000..122ddde00ba7
--- /dev/null
+++ b/arch/arm/mach-ux500/cache-l2x0.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2011
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+#include <linux/io.h>
+#include <asm/cacheflush.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <mach/hardware.h>
+#include <mach/id.h>
+static void __iomem *l2x0_base;
+static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask)
+{
+        /* wait for the operation to complete */
+        while (readl_relaxed(reg) & mask)
+                cpu_relax();
+}
+static inline void ux500_cache_sync(void)
+{
+        writel_relaxed(0, l2x0_base + L2X0_CACHE_SYNC);
+        ux500_cache_wait(l2x0_base + L2X0_CACHE_SYNC, 1);
+}
+/*
+ * The L2 cache cannot be turned off in the non-secure world.
+ * Dummy until a secure service is in place.
+ */
+static void ux500_l2x0_disable(void)
+{
+}
+/*
+ * This is only called when doing a kexec, just after turning off the L2
+ * and L1 cache, and it is surrounded by a spinlock in the generic version.
+ * However, we're not really turning off the L2 cache right now and the
+ * PL310 does not support exclusive accesses (used to implement the spinlock).
+ * So, the invalidation needs to be done without the spinlock.
+ */
+static void ux500_l2x0_inv_all(void)
+{
+        uint32_t l2x0_way_mask = (1<<16) - 1;   /* Bitmask of active ways */
+        /* invalidate all ways */
+        writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
+        ux500_cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
+        ux500_cache_sync();
+}
+static int __init ux500_l2x0_unlock(void)
+{
+        int i;
+        /*
+         * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions
+         * apparently locks both caches before jumping to the kernel. The
+         * l2x0 core will not touch the unlock registers if the l2x0 is
+         * already enabled, so we do it right here instead. The PL310 has
+         * 8 sets of registers, one per possible CPU.
+         */
+        for (i = 0; i < 8; i++) {
+                writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
+                               i * L2X0_LOCKDOWN_STRIDE);
+                writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
+                               i * L2X0_LOCKDOWN_STRIDE);
+        }
+        return 0;
+}
+static int __init ux500_l2x0_init(void)
+{
+        if (cpu_is_u5500())
+                l2x0_base = __io_address(U5500_L2CC_BASE);
+        else if (cpu_is_u8500())
+                l2x0_base = __io_address(U8500_L2CC_BASE);
+        else
+                ux500_unknown_soc();
+        /* Unlock before init */
+        ux500_l2x0_unlock();
+        /* 64KB way size, 8 way associativity, force WA */
+        l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
+        /* Override invalidate function */
+        outer_cache.disable = ux500_l2x0_disable;
+        outer_cache.inv_all = ux500_l2x0_inv_all;
+        return 0;
+}
+early_initcall(ux500_l2x0_init);
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 1da23bb87c16..1405d0eb7edb 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -10,14 +10,12 @@
 #include <linux/clk.h>
 #include <linux/mfd/db8500-prcmu.h>
 #include <linux/mfd/db5500-prcmu.h>
+#include <linux/clksrc-dbx500-prcmu.h>
-#include <asm/cacheflush.h>
-#include <asm/hardware/cache-l2x0.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach/map.h>
 #include <asm/localtimer.h>
-#include <plat/mtu.h>
 #include <mach/hardware.h>
 #include <mach/setup.h>
 #include <mach/devices.h>
@@ -26,10 +24,6 @@
 void __iomem *_PRCMU_BASE;
-#ifdef CONFIG_CACHE_L2X0
-static void __iomem *l2x0_base;
-#endif
 void __init ux500_init_irq(void)
 {
        void __iomem *dist_base;
@@ -56,93 +50,3 @@ void __init ux500_init_irq(void)
                prcmu_early_init();
        clk_init();
 }
-#ifdef CONFIG_CACHE_L2X0
-static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask)
-{
-        /* wait for the operation to complete */
-        while (readl_relaxed(reg) & mask)
-                ;
-}
-static inline void ux500_cache_sync(void)
-{
-        void __iomem *base = l2x0_base;
-        writel_relaxed(0, base + L2X0_CACHE_SYNC);
-        ux500_cache_wait(base + L2X0_CACHE_SYNC, 1);
-}
-/*
- * The L2 cache cannot be turned off in the non-secure world.
- * Dummy until a secure service is in place.
- */
-static void ux500_l2x0_disable(void)
-{
-}
-/*
- * This is only called when doing a kexec, just after turning off the L2
- * and L1 cache, and it is surrounded by a spinlock in the generic version.
- * However, we're not really turning off the L2 cache right now and the
- * PL310 does not support exclusive accesses (used to implement the spinlock).
- * So, the invalidation needs to be done without the spinlock.
- */
-static void ux500_l2x0_inv_all(void)
-{
-        void __iomem *base = l2x0_base;
-        uint32_t l2x0_way_mask = (1<<16) - 1;   /* Bitmask of active ways */
-        /* invalidate all ways */
-        writel_relaxed(l2x0_way_mask, base + L2X0_INV_WAY);
-        ux500_cache_wait(base + L2X0_INV_WAY, l2x0_way_mask);
-        ux500_cache_sync();
-}
-static int ux500_l2x0_init(void)
-{
-        if (cpu_is_u5500())
-                l2x0_base = __io_address(U5500_L2CC_BASE);
-        else if (cpu_is_u8500())
-                l2x0_base = __io_address(U8500_L2CC_BASE);
-        else
-                ux500_unknown_soc();
-        /* 64KB way size, 8 way associativity, force WA */
-        l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
-        /* Override invalidate function */
-        outer_cache.disable = ux500_l2x0_disable;
-        outer_cache.inv_all = ux500_l2x0_inv_all;
-        return 0;
-}
-early_initcall(ux500_l2x0_init);
-#endif
-static void __init ux500_timer_init(void)
-{
-#ifdef CONFIG_LOCAL_TIMERS
-        /* Setup the local timer base */
-        if (cpu_is_u5500())
-                twd_base = __io_address(U5500_TWD_BASE);
-        else if (cpu_is_u8500())
-                twd_base = __io_address(U8500_TWD_BASE);
-        else
-                ux500_unknown_soc();
-#endif
-        if (cpu_is_u5500())
-                mtu_base = __io_address(U5500_MTU0_BASE);
-        else if (cpu_is_u8500ed())
-                mtu_base = __io_address(U8500_MTU0_BASE_ED);
-        else if (cpu_is_u8500())
-                mtu_base = __io_address(U8500_MTU0_BASE);
-        else
-                ux500_unknown_soc();
-        nmdk_timer_init();
-}
-struct sys_timer ux500_timer = {
-        .init   = ux500_timer_init,
-};
diff --git a/arch/arm/mach-ux500/hotplug.c b/arch/arm/mach-ux500/hotplug.c
index dd8037ebccf8..572015e57cd9 100644
--- a/arch/arm/mach-ux500/hotplug.c
+++ b/arch/arm/mach-ux500/hotplug.c
@@ -24,7 +24,7 @@ static inline void platform_do_lowpower(unsigned int cpu)
        for (;;) {
                __asm__ __volatile__("dsb\n\t" "wfi\n\t"
                                : : : "memory");
-                if (pen_release == cpu) {
+                if (pen_release == cpu_logical_map(cpu)) {
                        /*
                         * OK, proper wakeup, we're done
                         */
diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h
index 6ad983294103..994b5fe6f85a 100644
--- a/arch/arm/mach-ux500/include/mach/db5500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h
@@ -61,6 +61,8 @@
 #define U5500_SCR_BASE          (U5500_PER4_BASE + 0x5000)
 #define U5500_DMC_BASE          (U5500_PER4_BASE + 0x6000)
 #define U5500_PRCMU_BASE        (U5500_PER4_BASE + 0x7000)
+#define U5500_PRCMU_TIMER_3_BASE (U5500_PER4_BASE + 0x07338)
+#define U5500_PRCMU_TIMER_4_BASE (U5500_PER4_BASE + 0x07450)
 #define U5500_MSP1_BASE         (U5500_PER4_BASE + 0x9000)
 #define U5500_GPIO2_BASE        (U5500_PER4_BASE + 0xA000)
 #define U5500_CDETECT_BASE      (U5500_PER4_BASE + 0xF000)
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h
index 049997109cf9..751b0e6938d4 100644
--- a/arch/arm/mach-ux500/include/mach/db8500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h
@@ -102,10 +102,13 @@
 #define U8500_SCR_BASE          (U8500_PER4_BASE + 0x05000)
 #define U8500_DMC_BASE          (U8500_PER4_BASE + 0x06000)
 #define U8500_PRCMU_BASE        (U8500_PER4_BASE + 0x07000)
+#define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338)
+#define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450)
 #define U8500_PRCMU_TCDM_BASE_V1 (U8500_PER4_BASE + 0x0f000)
 #define U8500_PRCMU_TCDM_BASE   (U8500_PER4_BASE + 0x68000)
 #define U8500_PRCMU_TCPM_BASE   (U8500_PER4_BASE + 0x60000)
 /* per3 base addresses */
 #define U8500_FSMC_BASE         (U8500_PER3_BASE + 0x0000)
 #define U8500_SSP0_BASE         (U8500_PER3_BASE + 0x2000)
diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h
index 7dd08074c37b..6fb3c4b0105d 100644
--- a/arch/arm/mach-ux500/include/mach/uncompress.h
+++ b/arch/arm/mach-ux500/include/mach/uncompress.h
@@ -51,15 +51,9 @@ static void flush(void)
 static inline void arch_decomp_setup(void)
 {
        /* Check in run time if we run on an U8500 or U5500 */
-        if (machine_is_u8500() ||
+        if (machine_is_u5500())
-            machine_is_svp8500v1() ||
-            machine_is_svp8500v2() ||
-            machine_is_hrefv60()   ||
-            machine_is_snowball())
-                ux500_uart_base = U8500_UART2_BASE;
-        else if (machine_is_u5500())
                ux500_uart_base = U5500_UART0_BASE;
-        else /* not much can be done to help here */
+        else
                ux500_uart_base = U8500_UART2_BASE;
 }
diff --git a/arch/arm/mach-ux500/pins-db8500.h b/arch/arm/mach-ux500/pins-db8500.h
index f923764ee16c..8b1d1a7a679e 100644
--- a/arch/arm/mach-ux500/pins-db8500.h
+++ b/arch/arm/mach-ux500/pins-db8500.h
@@ -35,40 +35,40 @@
 #define GPIO4_GPIO              PIN_CFG(4, GPIO)
 #define GPIO4_U1_RXD            PIN_CFG(4, ALT_A)
-#define GPIO4_I2C4_SCL          PIN_CFG_PULL(4, ALT_B, UP)
+#define GPIO4_I2C4_SCL          PIN_CFG_INPUT(4, ALT_B, PULLUP)
 #define GPIO4_IP_TRSTn          PIN_CFG(4, ALT_C)
 #define GPIO5_GPIO              PIN_CFG(5, GPIO)
 #define GPIO5_U1_TXD            PIN_CFG(5, ALT_A)
-#define GPIO5_I2C4_SDA          PIN_CFG_PULL(5, ALT_B, UP)
+#define GPIO5_I2C4_SDA          PIN_CFG_INPUT(5, ALT_B, PULLUP)
 #define GPIO5_IP_GPIO6          PIN_CFG(5, ALT_C)
 #define GPIO6_GPIO              PIN_CFG(6, GPIO)
 #define GPIO6_U1_CTSn           PIN_CFG(6, ALT_A)
-#define GPIO6_I2C1_SCL          PIN_CFG_PULL(6, ALT_B, UP)
+#define GPIO6_I2C1_SCL          PIN_CFG_INPUT(6, ALT_B, PULLUP)
 #define GPIO6_IP_GPIO0          PIN_CFG(6, ALT_C)
 #define GPIO7_GPIO              PIN_CFG(7, GPIO)
 #define GPIO7_U1_RTSn           PIN_CFG(7, ALT_A)
-#define GPIO7_I2C1_SDA          PIN_CFG_PULL(7, ALT_B, UP)
+#define GPIO7_I2C1_SDA          PIN_CFG_INPUT(7, ALT_B, PULLUP)
 #define GPIO7_IP_GPIO1          PIN_CFG(7, ALT_C)
 #define GPIO8_GPIO              PIN_CFG(8, GPIO)
-#define GPIO8_IPI2C_SDA         PIN_CFG_PULL(8, ALT_A, UP)
+#define GPIO8_IPI2C_SDA         PIN_CFG_INPUT(8, ALT_A, PULLUP)
-#define GPIO8_I2C2_SDA          PIN_CFG_PULL(8, ALT_B, UP)
+#define GPIO8_I2C2_SDA          PIN_CFG_INPUT(8, ALT_B, PULLUP)
 #define GPIO9_GPIO              PIN_CFG(9, GPIO)
-#define GPIO9_IPI2C_SCL         PIN_CFG_PULL(9, ALT_A, UP)
+#define GPIO9_IPI2C_SCL         PIN_CFG_INPUT(9, ALT_A, PULLUP)
-#define GPIO9_I2C2_SCL          PIN_CFG_PULL(9, ALT_B, UP)
+#define GPIO9_I2C2_SCL          PIN_CFG_INPUT(9, ALT_B, PULLUP)
 #define GPIO10_GPIO             PIN_CFG(10, GPIO)
-#define GPIO10_IPI2C_SDA        PIN_CFG_PULL(10, ALT_A, UP)
+#define GPIO10_IPI2C_SDA        PIN_CFG_INPUT(10, ALT_A, PULLUP)
-#define GPIO10_I2C2_SDA         PIN_CFG_PULL(10, ALT_B, UP)
+#define GPIO10_I2C2_SDA         PIN_CFG_INPUT(10, ALT_B, PULLUP)
 #define GPIO10_IP_GPIO3         PIN_CFG(10, ALT_C)
 #define GPIO11_GPIO             PIN_CFG(11, GPIO)
-#define GPIO11_IPI2C_SCL        PIN_CFG_PULL(11, ALT_A, UP)
+#define GPIO11_IPI2C_SCL        PIN_CFG_INPUT(11, ALT_A, PULLUP)
-#define GPIO11_I2C2_SCL         PIN_CFG_PULL(11, ALT_B, UP)
+#define GPIO11_I2C2_SCL         PIN_CFG_INPUT(11, ALT_B, PULLUP)
 #define GPIO11_IP_GPIO2         PIN_CFG(11, ALT_C)
 #define GPIO12_GPIO             PIN_CFG(12, GPIO)
@@ -87,66 +87,66 @@
 #define GPIO16_GPIO             PIN_CFG(16, GPIO)
 #define GPIO16_MSP0_RFS         PIN_CFG(16, ALT_A)
-#define GPIO16_I2C1_SCL         PIN_CFG_PULL(16, ALT_B, UP)
+#define GPIO16_I2C1_SCL         PIN_CFG_INPUT(16, ALT_B, PULLUP)
 #define GPIO16_SLIM0_DAT        PIN_CFG(16, ALT_C)
 #define GPIO17_GPIO             PIN_CFG(17, GPIO)
 #define GPIO17_MSP0_RCK         PIN_CFG(17, ALT_A)
-#define GPIO17_I2C1_SDA         PIN_CFG_PULL(17, ALT_B, UP)
+#define GPIO17_I2C1_SDA         PIN_CFG_INPUT(17, ALT_B, PULLUP)
 #define GPIO17_SLIM0_CLK        PIN_CFG(17, ALT_C)
 #define GPIO18_GPIO             PIN_CFG(18, GPIO)
-#define GPIO18_MC0_CMDDIR       PIN_CFG_PULL(18, ALT_A, UP)
+#define GPIO18_MC0_CMDDIR       PIN_CFG_INPUT(18, ALT_A, PULLUP)
 #define GPIO18_U2_RXD           PIN_CFG(18, ALT_B)
 #define GPIO18_MS_IEP           PIN_CFG(18, ALT_C)
 #define GPIO19_GPIO             PIN_CFG(19, GPIO)
-#define GPIO19_MC0_DAT0DIR      PIN_CFG_PULL(19, ALT_A, UP)
+#define GPIO19_MC0_DAT0DIR      PIN_CFG_INPUT(19, ALT_A, PULLUP)
 #define GPIO19_U2_TXD           PIN_CFG(19, ALT_B)
 #define GPIO19_MS_DAT0DIR       PIN_CFG(19, ALT_C)
 #define GPIO20_GPIO             PIN_CFG(20, GPIO)
-#define GPIO20_MC0_DAT2DIR      PIN_CFG_PULL(20, ALT_A, UP)
+#define GPIO20_MC0_DAT2DIR      PIN_CFG_INPUT(20, ALT_A, PULLUP)
 #define GPIO20_UARTMOD_TXD      PIN_CFG(20, ALT_B)
 #define GPIO20_IP_TRIGOUT       PIN_CFG(20, ALT_C)
 #define GPIO21_GPIO             PIN_CFG(21, GPIO)
-#define GPIO21_MC0_DAT31DIR     PIN_CFG_PULL(21, ALT_A, UP)
+#define GPIO21_MC0_DAT31DIR     PIN_CFG_INPUT(21, ALT_A, PULLUP)
 #define GPIO21_MSP0_SCK         PIN_CFG(21, ALT_B)
 #define GPIO21_MS_DAT31DIR      PIN_CFG(21, ALT_C)
 #define GPIO22_GPIO             PIN_CFG(22, GPIO)
-#define GPIO22_MC0_FBCLK        PIN_CFG_PULL(22, ALT_A, UP)
+#define GPIO22_MC0_FBCLK        PIN_CFG_INPUT(22, ALT_A, PULLUP)
 #define GPIO22_UARTMOD_RXD      PIN_CFG(22, ALT_B)
 #define GPIO22_MS_FBCLK         PIN_CFG(22, ALT_C)
 #define GPIO23_GPIO             PIN_CFG(23, GPIO)
-#define GPIO23_MC0_CLK          PIN_CFG_PULL(23, ALT_A, UP)
+#define GPIO23_MC0_CLK          PIN_CFG_INPUT(23, ALT_A, PULLUP)
 #define GPIO23_STMMOD_CLK       PIN_CFG(23, ALT_B)
 #define GPIO23_MS_CLK           PIN_CFG(23, ALT_C)
 #define GPIO24_GPIO             PIN_CFG(24, GPIO)
-#define GPIO24_MC0_CMD          PIN_CFG_PULL(24, ALT_A, UP)
+#define GPIO24_MC0_CMD          PIN_CFG_INPUT(24, ALT_A, PULLUP)
 #define GPIO24_UARTMOD_RXD      PIN_CFG(24, ALT_B)
 #define GPIO24_MS_BS            PIN_CFG(24, ALT_C)
 #define GPIO25_GPIO             PIN_CFG(25, GPIO)
-#define GPIO25_MC0_DAT0         PIN_CFG_PULL(25, ALT_A, UP)
+#define GPIO25_MC0_DAT0         PIN_CFG_INPUT(25, ALT_A, PULLUP)
 #define GPIO25_STMMOD_DAT0      PIN_CFG(25, ALT_B)
 #define GPIO25_MS_DAT0          PIN_CFG(25, ALT_C)
 #define GPIO26_GPIO             PIN_CFG(26, GPIO)
-#define GPIO26_MC0_DAT1         PIN_CFG_PULL(26, ALT_A, UP)
+#define GPIO26_MC0_DAT1         PIN_CFG_INPUT(26, ALT_A, PULLUP)
 #define GPIO26_STMMOD_DAT1      PIN_CFG(26, ALT_B)
 #define GPIO26_MS_DAT1          PIN_CFG(26, ALT_C)
 #define GPIO27_GPIO             PIN_CFG(27, GPIO)
-#define GPIO27_MC0_DAT2         PIN_CFG_PULL(27, ALT_A, UP)
+#define GPIO27_MC0_DAT2         PIN_CFG_INPUT(27, ALT_A, PULLUP)
 #define GPIO27_STMMOD_DAT2      PIN_CFG(27, ALT_B)
 #define GPIO27_MS_DAT2          PIN_CFG(27, ALT_C)
 #define GPIO28_GPIO             PIN_CFG(28, GPIO)
-#define GPIO28_MC0_DAT3         PIN_CFG_PULL(28, ALT_A, UP)
+#define GPIO28_MC0_DAT3         PIN_CFG_INPUT(28, ALT_A, PULLUP)
 #define GPIO28_STMMOD_DAT3      PIN_CFG(28, ALT_B)
 #define GPIO28_MS_DAT3          PIN_CFG(28, ALT_C)
@@ -357,48 +357,48 @@
 #define GPIO97_MC5_DAT7         PIN_CFG(97, ALT_C)
 #define GPIO128_GPIO            PIN_CFG(128, GPIO)
-#define GPIO128_MC2_CLK         PIN_CFG_PULL(128, ALT_A, UP)
+#define GPIO128_MC2_CLK         PIN_CFG_INPUT(128, ALT_A, PULLUP)
 #define GPIO128_SM_CKO          PIN_CFG(128, ALT_B)
 #define GPIO129_GPIO            PIN_CFG(129, GPIO)
-#define GPIO129_MC2_CMD         PIN_CFG_PULL(129, ALT_A, UP)
+#define GPIO129_MC2_CMD         PIN_CFG_INPUT(129, ALT_A, PULLUP)
 #define GPIO129_SM_WAIT0n       PIN_CFG(129, ALT_B)
 #define GPIO130_GPIO            PIN_CFG(130, GPIO)
-#define GPIO130_MC2_FBCLK       PIN_CFG_PULL(130, ALT_A, UP)
+#define GPIO130_MC2_FBCLK       PIN_CFG_INPUT(130, ALT_A, PULLUP)
 #define GPIO130_SM_FBCLK        PIN_CFG(130, ALT_B)
 #define GPIO130_MC2_RSTN        PIN_CFG(130, ALT_C)
 #define GPIO131_GPIO            PIN_CFG(131, GPIO)
-#define GPIO131_MC2_DAT0        PIN_CFG_PULL(131, ALT_A, UP)
+#define GPIO131_MC2_DAT0        PIN_CFG_INPUT(131, ALT_A, PULLUP)
 #define GPIO131_SM_ADQ8         PIN_CFG(131, ALT_B)
 #define GPIO132_GPIO            PIN_CFG(132, GPIO)
-#define GPIO132_MC2_DAT1        PIN_CFG_PULL(132, ALT_A, UP)
+#define GPIO132_MC2_DAT1        PIN_CFG_INPUT(132, ALT_A, PULLUP)
 #define GPIO132_SM_ADQ9         PIN_CFG(132, ALT_B)
 #define GPIO133_GPIO            PIN_CFG(133, GPIO)
-#define GPIO133_MC2_DAT2        PIN_CFG_PULL(133, ALT_A, UP)
+#define GPIO133_MC2_DAT2        PIN_CFG_INPUT(133, ALT_A, PULLUP)
 #define GPIO133_SM_ADQ10        PIN_CFG(133, ALT_B)
 #define GPIO134_GPIO            PIN_CFG(134, GPIO)
-#define GPIO134_MC2_DAT3        PIN_CFG_PULL(134, ALT_A, UP)
+#define GPIO134_MC2_DAT3        PIN_CFG_INPUT(134, ALT_A, PULLUP)
 #define GPIO134_SM_ADQ11        PIN_CFG(134, ALT_B)
 #define GPIO135_GPIO            PIN_CFG(135, GPIO)
-#define GPIO135_MC2_DAT4        PIN_CFG_PULL(135, ALT_A, UP)
+#define GPIO135_MC2_DAT4        PIN_CFG_INPUT(135, ALT_A, PULLUP)
 #define GPIO135_SM_ADQ12        PIN_CFG(135, ALT_B)
 #define GPIO136_GPIO            PIN_CFG(136, GPIO)
-#define GPIO136_MC2_DAT5        PIN_CFG_PULL(136, ALT_A, UP)
+#define GPIO136_MC2_DAT5        PIN_CFG_INPUT(136, ALT_A, PULLUP)
 #define GPIO136_SM_ADQ13        PIN_CFG(136, ALT_B)
 #define GPIO137_GPIO            PIN_CFG(137, GPIO)
-#define GPIO137_MC2_DAT6        PIN_CFG_PULL(137, ALT_A, UP)
+#define GPIO137_MC2_DAT6        PIN_CFG_INPUT(137, ALT_A, PULLUP)
 #define GPIO137_SM_ADQ14        PIN_CFG(137, ALT_B)
 #define GPIO138_GPIO            PIN_CFG(138, GPIO)
-#define GPIO138_MC2_DAT7        PIN_CFG_PULL(138, ALT_A, UP)
+#define GPIO138_MC2_DAT7        PIN_CFG_INPUT(138, ALT_A, PULLUP)
 #define GPIO138_SM_ADQ15        PIN_CFG(138, ALT_B)
 #define GPIO139_GPIO            PIN_CFG(139, GPIO)
@@ -434,10 +434,10 @@
 #define GPIO146_SSP0_TXD        PIN_CFG(146, ALT_A)
 #define GPIO147_GPIO            PIN_CFG(147, GPIO)
-#define GPIO147_I2C0_SCL        PIN_CFG_PULL(147, ALT_A, UP)
+#define GPIO147_I2C0_SCL        PIN_CFG_INPUT(147, ALT_A, PULLUP)
 #define GPIO148_GPIO            PIN_CFG(148, GPIO)
-#define GPIO148_I2C0_SDA        PIN_CFG_PULL(148, ALT_A, UP)
+#define GPIO148_I2C0_SDA        PIN_CFG_INPUT(148, ALT_A, PULLUP)
 #define GPIO149_GPIO            PIN_CFG(149, GPIO)
 #define GPIO149_IP_GPIO0        PIN_CFG(149, ALT_A)
@@ -459,82 +459,82 @@
 #define GPIO152_KP_O9           PIN_CFG(152, ALT_C)
 #define GPIO153_GPIO            PIN_CFG(153, GPIO)
-#define GPIO153_KP_I7           PIN_CFG_PULL(153, ALT_A, DOWN)
+#define GPIO153_KP_I7           PIN_CFG_INPUT(153, ALT_A, PULLDOWN)
 #define GPIO153_LCD_D24         PIN_CFG(153, ALT_B)
 #define GPIO153_U2_RXD          PIN_CFG(153, ALT_C)
 #define GPIO154_GPIO            PIN_CFG(154, GPIO)
-#define GPIO154_KP_I6           PIN_CFG_PULL(154, ALT_A, DOWN)
+#define GPIO154_KP_I6           PIN_CFG_INPUT(154, ALT_A, PULLDOWN)
 #define GPIO154_LCD_D25         PIN_CFG(154, ALT_B)
 #define GPIO154_U2_TXD          PIN_CFG(154, ALT_C)
 #define GPIO155_GPIO            PIN_CFG(155, GPIO)
-#define GPIO155_KP_I5           PIN_CFG_PULL(155, ALT_A, DOWN)
+#define GPIO155_KP_I5           PIN_CFG_INPUT(155, ALT_A, PULLDOWN)
 #define GPIO155_LCD_D26         PIN_CFG(155, ALT_B)
 #define GPIO155_STMAPE_CLK      PIN_CFG(155, ALT_C)
 #define GPIO156_GPIO            PIN_CFG(156, GPIO)
-#define GPIO156_KP_I4           PIN_CFG_PULL(156, ALT_A, DOWN)
+#define GPIO156_KP_I4           PIN_CFG_INPUT(156, ALT_A, PULLDOWN)
 #define GPIO156_LCD_D27         PIN_CFG(156, ALT_B)
 #define GPIO156_STMAPE_DAT3     PIN_CFG(156, ALT_C)
 #define GPIO157_GPIO            PIN_CFG(157, GPIO)
-#define GPIO157_KP_O7           PIN_CFG_PULL(157, ALT_A, UP)
+#define GPIO157_KP_O7           PIN_CFG_INPUT(157, ALT_A, PULLUP)
 #define GPIO157_LCD_D28         PIN_CFG(157, ALT_B)
 #define GPIO157_STMAPE_DAT2     PIN_CFG(157, ALT_C)
 #define GPIO158_GPIO            PIN_CFG(158, GPIO)
-#define GPIO158_KP_O6           PIN_CFG_PULL(158, ALT_A, UP)
+#define GPIO158_KP_O6           PIN_CFG_INPUT(158, ALT_A, PULLUP)
 #define GPIO158_LCD_D29         PIN_CFG(158, ALT_B)
 #define GPIO158_STMAPE_DAT1     PIN_CFG(158, ALT_C)
 #define GPIO159_GPIO            PIN_CFG(159, GPIO)
-#define GPIO159_KP_O5           PIN_CFG_PULL(159, ALT_A, UP)
+#define GPIO159_KP_O5           PIN_CFG_INPUT(159, ALT_A, PULLUP)
 #define GPIO159_LCD_D30         PIN_CFG(159, ALT_B)
 #define GPIO159_STMAPE_DAT0     PIN_CFG(159, ALT_C)
 #define GPIO160_GPIO            PIN_CFG(160, GPIO)
-#define GPIO160_KP_O4           PIN_CFG_PULL(160, ALT_A, UP)
+#define GPIO160_KP_O4           PIN_CFG_INPUT(160, ALT_A, PULLUP)
 #define GPIO160_LCD_D31         PIN_CFG(160, ALT_B)
 #define GPIO160_NONE            PIN_CFG(160, ALT_C)
 #define GPIO161_GPIO            PIN_CFG(161, GPIO)
-#define GPIO161_KP_I3           PIN_CFG_PULL(161, ALT_A, DOWN)
+#define GPIO161_KP_I3           PIN_CFG_INPUT(161, ALT_A, PULLDOWN)
 #define GPIO161_LCD_D32         PIN_CFG(161, ALT_B)
 #define GPIO161_UARTMOD_RXD     PIN_CFG(161, ALT_C)
 #define GPIO162_GPIO            PIN_CFG(162, GPIO)
-#define GPIO162_KP_I2           PIN_CFG_PULL(162, ALT_A, DOWN)
+#define GPIO162_KP_I2           PIN_CFG_INPUT(162, ALT_A, PULLDOWN)
 #define GPIO162_LCD_D33         PIN_CFG(162, ALT_B)
 #define GPIO162_UARTMOD_TXD     PIN_CFG(162, ALT_C)
 #define GPIO163_GPIO            PIN_CFG(163, GPIO)
-#define GPIO163_KP_I1           PIN_CFG_PULL(163, ALT_A, DOWN)
+#define GPIO163_KP_I1           PIN_CFG_INPUT(163, ALT_A, PULLDOWN)
 #define GPIO163_LCD_D34         PIN_CFG(163, ALT_B)
 #define GPIO163_STMMOD_CLK      PIN_CFG(163, ALT_C)
 #define GPIO164_GPIO            PIN_CFG(164, GPIO)
-#define GPIO164_KP_I0           PIN_CFG_PULL(164, ALT_A, UP)
+#define GPIO164_KP_I0           PIN_CFG_INPUT(164, ALT_A, PULLUP)
 #define GPIO164_LCD_D35         PIN_CFG(164, ALT_B)
 #define GPIO164_STMMOD_DAT3     PIN_CFG(164, ALT_C)
 #define GPIO165_GPIO            PIN_CFG(165, GPIO)
-#define GPIO165_KP_O3           PIN_CFG_PULL(165, ALT_A, UP)
+#define GPIO165_KP_O3           PIN_CFG_INPUT(165, ALT_A, PULLUP)
 #define GPIO165_LCD_D36         PIN_CFG(165, ALT_B)
 #define GPIO165_STMMOD_DAT2     PIN_CFG(165, ALT_C)
 #define GPIO166_GPIO            PIN_CFG(166, GPIO)
-#define GPIO166_KP_O2           PIN_CFG_PULL(166, ALT_A, UP)
+#define GPIO166_KP_O2           PIN_CFG_INPUT(166, ALT_A, PULLUP)
 #define GPIO166_LCD_D37         PIN_CFG(166, ALT_B)
 #define GPIO166_STMMOD_DAT1     PIN_CFG(166, ALT_C)
 #define GPIO167_GPIO            PIN_CFG(167, GPIO)
-#define GPIO167_KP_O1           PIN_CFG_PULL(167, ALT_A, UP)
+#define GPIO167_KP_O1           PIN_CFG_INPUT(167, ALT_A, PULLUP)
 #define GPIO167_LCD_D38         PIN_CFG(167, ALT_B)
 #define GPIO167_STMMOD_DAT0     PIN_CFG(167, ALT_C)
 #define GPIO168_GPIO            PIN_CFG(168, GPIO)
-#define GPIO168_KP_O0           PIN_CFG_PULL(168, ALT_A, UP)
+#define GPIO168_KP_O0           PIN_CFG_INPUT(168, ALT_A, PULLUP)
 #define GPIO168_LCD_D39         PIN_CFG(168, ALT_B)
 #define GPIO168_NONE            PIN_CFG(168, ALT_C)
@@ -569,39 +569,39 @@
 #define GPIO196_MSP2_RXD        PIN_CFG(196, ALT_A)
 #define GPIO197_GPIO            PIN_CFG(197, GPIO)
-#define GPIO197_MC4_DAT3        PIN_CFG_PULL(197, ALT_A, UP)
+#define GPIO197_MC4_DAT3        PIN_CFG_INPUT(197, ALT_A, PULLUP)
 #define GPIO198_GPIO            PIN_CFG(198, GPIO)
-#define GPIO198_MC4_DAT2        PIN_CFG_PULL(198, ALT_A, UP)
+#define GPIO198_MC4_DAT2        PIN_CFG_INPUT(198, ALT_A, PULLUP)
 #define GPIO199_GPIO            PIN_CFG(199, GPIO)
-#define GPIO199_MC4_DAT1        PIN_CFG_PULL(199, ALT_A, UP)
+#define GPIO199_MC4_DAT1        PIN_CFG_INPUT(199, ALT_A, PULLUP)
 #define GPIO200_GPIO            PIN_CFG(200, GPIO)
-#define GPIO200_MC4_DAT0        PIN_CFG_PULL(200, ALT_A, UP)
+#define GPIO200_MC4_DAT0        PIN_CFG_INPUT(200, ALT_A, PULLUP)
 #define GPIO201_GPIO            PIN_CFG(201, GPIO)
-#define GPIO201_MC4_CMD         PIN_CFG_PULL(201, ALT_A, UP)
+#define GPIO201_MC4_CMD         PIN_CFG_INPUT(201, ALT_A, PULLUP)
 #define GPIO202_GPIO            PIN_CFG(202, GPIO)
-#define GPIO202_MC4_FBCLK       PIN_CFG_PULL(202, ALT_A, UP)
+#define GPIO202_MC4_FBCLK       PIN_CFG_INPUT(202, ALT_A, PULLUP)
 #define GPIO202_PWL             PIN_CFG(202, ALT_B)
 #define GPIO202_MC4_RSTN        PIN_CFG(202, ALT_C)
 #define GPIO203_GPIO            PIN_CFG(203, GPIO)
-#define GPIO203_MC4_CLK         PIN_CFG_PULL(203, ALT_A, UP)
+#define GPIO203_MC4_CLK         PIN_CFG_INPUT(203, ALT_A, PULLUP)
 #define GPIO204_GPIO            PIN_CFG(204, GPIO)
-#define GPIO204_MC4_DAT7        PIN_CFG_PULL(204, ALT_A, UP)
+#define GPIO204_MC4_DAT7        PIN_CFG_INPUT(204, ALT_A, PULLUP)
 #define GPIO205_GPIO            PIN_CFG(205, GPIO)
-#define GPIO205_MC4_DAT6        PIN_CFG_PULL(205, ALT_A, UP)
+#define GPIO205_MC4_DAT6        PIN_CFG_INPUT(205, ALT_A, PULLUP)
 #define GPIO206_GPIO            PIN_CFG(206, GPIO)
-#define GPIO206_MC4_DAT5        PIN_CFG_PULL(206, ALT_A, UP)
+#define GPIO206_MC4_DAT5        PIN_CFG_INPUT(206, ALT_A, PULLUP)
 #define GPIO207_GPIO            PIN_CFG(207, GPIO)
-#define GPIO207_MC4_DAT4        PIN_CFG_PULL(207, ALT_A, UP)
+#define GPIO207_MC4_DAT4        PIN_CFG_INPUT(207, ALT_A, PULLUP)
 #define GPIO208_GPIO            PIN_CFG(208, GPIO)
 #define GPIO208_MC1_CLK         PIN_CFG(208, ALT_A)
@@ -632,21 +632,25 @@
 #define GPIO215_MC1_CMDDIR      PIN_CFG(215, ALT_A)
 #define GPIO215_MC3_DAT2DIR     PIN_CFG(215, ALT_B)
 #define GPIO215_CLKOUT1         PIN_CFG(215, ALT_C)
+#define GPIO215_SPI2_TXD        PIN_CFG(215, ALT_C)
 #define GPIO216_GPIO            PIN_CFG(216, GPIO)
 #define GPIO216_MC1_DAT2DIR     PIN_CFG(216, ALT_A)
 #define GPIO216_MC3_CMDDIR      PIN_CFG(216, ALT_B)
-#define GPIO216_I2C3_SDA        PIN_CFG_PULL(216, ALT_C, UP)
+#define GPIO216_I2C3_SDA        PIN_CFG_INPUT(216, ALT_C, PULLUP)
+#define GPIO216_SPI2_FRM        PIN_CFG(216, ALT_C)
 #define GPIO217_GPIO            PIN_CFG(217, GPIO)
 #define GPIO217_MC1_DAT0DIR     PIN_CFG(217, ALT_A)
 #define GPIO217_MC3_DAT31DIR    PIN_CFG(217, ALT_B)
 #define GPIO217_CLKOUT2         PIN_CFG(217, ALT_C)
+#define GPIO217_SPI2_CLK        PIN_CFG(217, ALT_C)
 #define GPIO218_GPIO            PIN_CFG(218, GPIO)
 #define GPIO218_MC1_DAT31DIR    PIN_CFG(218, ALT_A)
 #define GPIO218_MC3_DAT0DIR     PIN_CFG(218, ALT_B)
-#define GPIO218_I2C3_SCL        PIN_CFG_PULL(218, ALT_C, UP)
+#define GPIO218_I2C3_SCL        PIN_CFG_INPUT(218, ALT_C, PULLUP)
+#define GPIO218_SPI2_RXD        PIN_CFG(218, ALT_C)
 #define GPIO219_GPIO            PIN_CFG(219, GPIO)
 #define GPIO219_HSIR_FLA0       PIN_CFG(219, ALT_A)
@@ -694,12 +698,12 @@
 #define GPIO229_GPIO            PIN_CFG(229, GPIO)
 #define GPIO229_CLKOUT1         PIN_CFG(229, ALT_A)
 #define GPIO229_PWL             PIN_CFG(229, ALT_B)
-#define GPIO229_I2C3_SDA        PIN_CFG_PULL(229, ALT_C, UP)
+#define GPIO229_I2C3_SDA        PIN_CFG_INPUT(229, ALT_C, PULLUP)
 #define GPIO230_GPIO            PIN_CFG(230, GPIO)
 #define GPIO230_CLKOUT2         PIN_CFG(230, ALT_A)
 #define GPIO230_PWL             PIN_CFG(230, ALT_B)
-#define GPIO230_I2C3_SCL        PIN_CFG_PULL(230, ALT_C, UP)
+#define GPIO230_I2C3_SCL        PIN_CFG_INPUT(230, ALT_C, PULLUP)
 #define GPIO256_GPIO            PIN_CFG(256, GPIO)
 #define GPIO256_USB_NXT         PIN_CFG(256, ALT_A)
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index eb5199102cfa..a19e398dade3 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -96,7 +96,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
         * the holding pen - release it, then wait for it to flag
         * that it has been released by resetting pen_release.
         */
-        write_pen_release(cpu);
+        write_pen_release(cpu_logical_map(cpu));
        gic_raise_softirq(cpumask_of(cpu), 1);
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
new file mode 100644
index 000000000000..aea467d04ff7
--- /dev/null
+++ b/arch/arm/mach-ux500/timer.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2011
+ *
+ * License Terms: GNU General Public License v2
+ * Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson
+ */
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/clksrc-dbx500-prcmu.h>
+#include <asm/localtimer.h>
+#include <plat/mtu.h>
+#include <mach/setup.h>
+#include <mach/hardware.h>
+static void __init ux500_timer_init(void)
+{
+        void __iomem *prcmu_timer_base;
+        if (cpu_is_u5500()) {
+#ifdef CONFIG_LOCAL_TIMERS
+                twd_base = __io_address(U5500_TWD_BASE);
+#endif
+                mtu_base = __io_address(U5500_MTU0_BASE);
+                prcmu_timer_base = __io_address(U5500_PRCMU_TIMER_3_BASE);
+        } else if (cpu_is_u8500()) {
+#ifdef CONFIG_LOCAL_TIMERS
+                twd_base = __io_address(U8500_TWD_BASE);
+#endif
+                mtu_base = __io_address(U8500_MTU0_BASE);
+                prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE);
+        } else {
+                ux500_unknown_soc();
+        }
+        /*
+         * Here we register the timerblocks active in the system.
+         * Localtimers (twd) is started when both cpu is up and running.
+         * MTU register a clocksource, clockevent and sched_clock.
+         * Since the MTU is located in the VAPE power domain
+         * it will be cleared in sleep which makes it unsuitable.
+         * We however need it as a timer tick (clockevent)
+         * during boot to calibrate delay until twd is started.
+         * RTC-RTT have problems as timer tick during boot since it is
+         * depending on delay which is not yet calibrated. RTC-RTT is in the
+         * always-on powerdomain and is used as clockevent instead of twd when
+         * sleeping.
+         * The PRCMU timer 4(3 for DB5500) register a clocksource and
+         * sched_clock with higher rating then MTU since is always-on.
+         *
+         */
+        nmdk_timer_init();
+        clksrc_dbx500_prcmu_init(prcmu_timer_base);
+}
+static void ux500_timer_reset(void)
+{
+        nmdk_clkevt_reset();
+        nmdk_clksrc_reset();
+}
+struct sys_timer ux500_timer = {
+        .init           = ux500_timer_init,
+        .resume         = ux500_timer_reset,
+};
diff --git a/arch/arm/mach-vexpress/hotplug.c b/arch/arm/mach-vexpress/hotplug.c
index 3668cf91d2de..813ee08f96e6 100644
--- a/arch/arm/mach-vexpress/hotplug.c
+++ b/arch/arm/mach-vexpress/hotplug.c
@@ -65,7 +65,7 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
        for (;;) {
                wfi();
-                if (pen_release == cpu) {
+                if (pen_release == cpu_logical_map(cpu)) {
                        /*
                         * OK, proper wakeup, we're done
                         */
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 88633fe01a5d..67f75a0b66d6 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -819,10 +819,10 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
 config CACHE_L2X0
        bool "Enable the L2x0 outer cache controller"
        depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
-                   REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \
+                   REALVIEW_EB_A9MP || ARCH_IMX_V6_V7 || MACH_REALVIEW_PBX || \
                   ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
                   ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || \
-                   ARCH_PRIMA2 || ARCH_ZYNQ || ARCH_CNS3XXX
+                   ARCH_PRIMA2 || ARCH_ZYNQ || ARCH_CNS3XXX || ARCH_HIGHBANK
        default y
        select OUTER_CACHE
        select OUTER_CACHE_SYNC
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 4c8fdbcc9467..a08a95107a63 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -4,50 +4,34 @@ source "arch/arm/plat-mxc/devices/Kconfig"
 menu "Freescale MXC Implementations"
-config ARCH_MX50_SUPPORTED
-        bool
-config ARCH_MX53_SUPPORTED
-        bool
 choice
        prompt "Freescale CPU family:"
-        default ARCH_MX3
+        default ARCH_IMX_V6_V7
-config ARCH_MX1
-        bool "MX1-based"
-        help
-          This enables support for systems based on the Freescale i.MX1 family
-config ARCH_MX2
-        bool "MX2-based"
-        help
-          This enables support for systems based on the Freescale i.MX2 family
-config ARCH_MX25
+config ARCH_IMX_V4_V5
-        bool "MX25-based"
+        bool "i.MX1, i.MX21, i.MX25, i.MX27"
+        select AUTO_ZRELADDR
+        select ARM_PATCH_PHYS_VIRT
        help
-          This enables support for systems based on the Freescale i.MX25 family
+          This enables support for systems based on the Freescale i.MX ARMv4
+          and ARMv5 SoCs
-config ARCH_MX3
+config ARCH_IMX_V6_V7
-        bool "MX3-based"
+        bool "i.MX3, i.MX6"
+        select AUTO_ZRELADDR if !ZBOOT_ROM
+        select ARM_PATCH_PHYS_VIRT
        help
-          This enables support for systems based on the Freescale i.MX3 family
+          This enables support for systems based on the Freescale i.MX3 and i.MX6
+          family.
-config ARCH_MX503
+config ARCH_MX5
-        bool "i.MX50 + i.MX53"
+        bool "i.MX50, i.MX51, i.MX53"
-        select ARCH_MX50_SUPPORTED
+        select AUTO_ZRELADDR
-        select ARCH_MX53_SUPPORTED
+        select ARM_PATCH_PHYS_VIRT
        help
          This enables support for machines using Freescale's i.MX50 and i.MX53
          processors.
-config ARCH_MX51
-        bool "i.MX51"
-        select ARCH_MX51_SUPPORTED
-        help
-          This enables support for systems based on the Freescale i.MX51 family
 endchoice
 source "arch/arm/mach-imx/Kconfig"
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index d53c35fe2ea7..b9f0f5f499a4 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -5,7 +5,7 @@
 # Common support
 obj-y := clock.o time.o devices.o cpu.o system.o irq-common.o
-# MX51 uses the TZIC interrupt controller, older platforms use AVIC
+obj-$(CONFIG_ARM_GIC) += gic.o
 obj-$(CONFIG_MXC_TZIC) += tzic.o
 obj-$(CONFIG_MXC_AVIC) += avic.o
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c
index 175e3647bb27..8cced35009bd 100644
--- a/arch/arm/plat-mxc/audmux-v2.c
+++ b/arch/arm/plat-mxc/audmux-v2.c
@@ -187,18 +187,11 @@ EXPORT_SYMBOL_GPL(mxc_audmux_v2_configure_port);
 static int mxc_audmux_v2_init(void)
 {
        int ret;
-#if defined(CONFIG_ARCH_MX5)
        if (cpu_is_mx51()) {
                audmux_base = MX51_IO_ADDRESS(MX51_AUDMUX_BASE_ADDR);
-                ret = 0;
+        } else if (cpu_is_mx31()) {
-                return ret;
-        }
-#endif
-#if defined(CONFIG_ARCH_MX3)
-        if (cpu_is_mx31())
                audmux_base = MX31_IO_ADDRESS(MX31_AUDMUX_BASE_ADDR);
+        } else if (cpu_is_mx35()) {
-        else if (cpu_is_mx35()) {
                audmux_clk = clk_get(NULL, "audmux");
                if (IS_ERR(audmux_clk)) {
                        ret = PTR_ERR(audmux_clk);
@@ -207,10 +200,7 @@ static int mxc_audmux_v2_init(void)
                        return ret;
                }
                audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR);
-        }
+        } else if (cpu_is_mx25()) {
-#endif
-#if defined(CONFIG_SOC_IMX25)
-        if (cpu_is_mx25()) {
                audmux_clk = clk_get(NULL, "audmux");
                if (IS_ERR(audmux_clk)) {
                        ret = PTR_ERR(audmux_clk);
@@ -220,7 +210,7 @@ static int mxc_audmux_v2_init(void)
                }
                audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR);
        }
-#endif /* if defined(CONFIG_SOC_IMX25) */
        audmux_debugfs_init();
        return 0;
diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c
index 55d2534ec727..8875fb415f68 100644
--- a/arch/arm/plat-mxc/avic.c
+++ b/arch/arm/plat-mxc/avic.c
@@ -50,6 +50,8 @@
 void __iomem *avic_base;
+static u32 avic_saved_mask_reg[2];
 #ifdef CONFIG_MXC_IRQ_PRIOR
 static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
 {
@@ -90,24 +92,8 @@ static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
 }
 #endif /* CONFIG_FIQ */
-/* Disable interrupt number "irq" in the AVIC */
-static void mxc_mask_irq(struct irq_data *d)
-{
-        __raw_writel(d->irq, avic_base + AVIC_INTDISNUM);
-}
-/* Enable interrupt number "irq" in the AVIC */
+static struct mxc_extra_irq avic_extra_irq = {
-static void mxc_unmask_irq(struct irq_data *d)
-{
-        __raw_writel(d->irq, avic_base + AVIC_INTENNUM);
-}
-static struct mxc_irq_chip mxc_avic_chip = {
-        .base = {
-                .irq_ack = mxc_mask_irq,
-                .irq_mask = mxc_mask_irq,
-                .irq_unmask = mxc_unmask_irq,
-        },
 #ifdef CONFIG_MXC_IRQ_PRIOR
        .set_priority = avic_irq_set_priority,
 #endif
@@ -116,6 +102,68 @@ static struct mxc_irq_chip mxc_avic_chip = {
 #endif
 };
+#ifdef CONFIG_PM
+static void avic_irq_suspend(struct irq_data *d)
+{
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        struct irq_chip_type *ct = gc->chip_types;
+        int idx = gc->irq_base >> 5;
+        avic_saved_mask_reg[idx] = __raw_readl(avic_base + ct->regs.mask);
+        __raw_writel(gc->wake_active, avic_base + ct->regs.mask);
+}
+static void avic_irq_resume(struct irq_data *d)
+{
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        struct irq_chip_type *ct = gc->chip_types;
+        int idx = gc->irq_base >> 5;
+        __raw_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);
+}
+#else
+#define avic_irq_suspend NULL
+#define avic_irq_resume NULL
+#endif
+static __init void avic_init_gc(unsigned int irq_start)
+{
+        struct irq_chip_generic *gc;
+        struct irq_chip_type *ct;
+        int idx = irq_start >> 5;
+        gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base,
+                                    handle_level_irq);
+        gc->private = &avic_extra_irq;
+        gc->wake_enabled = IRQ_MSK(32);
+        ct = gc->chip_types;
+        ct->chip.irq_mask = irq_gc_mask_clr_bit;
+        ct->chip.irq_unmask = irq_gc_mask_set_bit;
+        ct->chip.irq_ack = irq_gc_mask_clr_bit;
+        ct->chip.irq_set_wake = irq_gc_set_wake;
+        ct->chip.irq_suspend = avic_irq_suspend;
+        ct->chip.irq_resume = avic_irq_resume;
+        ct->regs.mask = !idx ? AVIC_INTENABLEL : AVIC_INTENABLEH;
+        ct->regs.ack = ct->regs.mask;
+        irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
+}
+asmlinkage void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
+{
+        u32 nivector;
+        do {
+                nivector = __raw_readl(avic_base + AVIC_NIVECSR) >> 16;
+                if (nivector == 0xffff)
+                        break;
+                handle_IRQ(nivector, regs);
+        } while (1);
+}
 /*
 * This function initializes the AVIC hardware and disables all the
 * interrupts. It registers the interrupt enable and disable functions
@@ -140,11 +188,9 @@ void __init mxc_init_irq(void __iomem *irqbase)
        /* all IRQ no FIQ */
        __raw_writel(0, avic_base + AVIC_INTTYPEH);
        __raw_writel(0, avic_base + AVIC_INTTYPEL);
-        for (i = 0; i < AVIC_NUM_IRQS; i++) {
-                irq_set_chip_and_handler(i, &mxc_avic_chip.base,
+        for (i = 0; i < AVIC_NUM_IRQS; i += 32)
-                                         handle_level_irq);
+                avic_init_gc(i);
-                set_irq_flags(i, IRQF_VALID);
-        }
        /* Set default priority value (0) for all IRQ's */
        for (i = 0; i < 8; i++)
@@ -157,4 +203,3 @@ void __init mxc_init_irq(void __iomem *irqbase)
        printk(KERN_INFO "MXC IRQ initialized\n");
 }
diff --git a/arch/arm/plat-mxc/cpu.c b/arch/arm/plat-mxc/cpu.c
index 386e0d52cf58..f5b7e0fa237f 100644
--- a/arch/arm/plat-mxc/cpu.c
+++ b/arch/arm/plat-mxc/cpu.c
@@ -1,5 +1,6 @@
 #include <linux/module.h>
+#include <mach/hardware.h>
 unsigned int __mxc_cpu_type;
 EXPORT_SYMBOL(__mxc_cpu_type);
@@ -9,3 +10,11 @@ void mxc_set_cpu_type(unsigned int type)
        __mxc_cpu_type = type;
 }
+void imx_print_silicon_rev(const char *cpu, int srev)
+{
+        if (srev == IMX_CHIP_REVISION_UNKNOWN)
+                pr_info("CPU identified as %s, unknown revision\n", cpu);
+        else
+                pr_info("CPU identified as %s, silicon rev %d.%d\n",
+                                cpu, (srev >> 4) & 0xf, srev & 0xf);
+}
diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c
index a34b2ae895f2..4d55a7a26e98 100644
--- a/arch/arm/plat-mxc/devices.c
+++ b/arch/arm/plat-mxc/devices.c
@@ -23,20 +23,6 @@
 #include <linux/platform_device.h>
 #include <mach/common.h>
-int __init mxc_register_device(struct platform_device *pdev, void *data)
-{
-        int ret;
-        pdev->dev.platform_data = data;
-        ret = platform_device_register(pdev);
-        if (ret)
-                pr_debug("Unable to register platform device '%s': %d\n",
-                         pdev->name, ret);
-        return ret;
-}
 struct device mxc_aips_bus = {
        .init_name      = "mxc_aips",
        .parent         = &platform_bus,
diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig
index bd294add932c..cb3e3eef55c0 100644
--- a/arch/arm/plat-mxc/devices/Kconfig
+++ b/arch/arm/plat-mxc/devices/Kconfig
@@ -1,6 +1,6 @@
 config IMX_HAVE_PLATFORM_FEC
        bool
-        default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX51 || SOC_IMX53
+        default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX50 || SOC_IMX51 || SOC_IMX53
 config IMX_HAVE_PLATFORM_FLEXCAN
        select HAVE_CAN_FLEXCAN if CAN
@@ -31,6 +31,9 @@ config IMX_HAVE_PLATFORM_IMX_I2C
 config IMX_HAVE_PLATFORM_IMX_KEYPAD
        bool
+config IMX_HAVE_PLATFORM_PATA_IMX
+        bool
 config IMX_HAVE_PLATFORM_IMX_SSI
        bool
@@ -76,3 +79,7 @@ config IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
 config IMX_HAVE_PLATFORM_SPI_IMX
        bool
+config IMX_HAVE_PLATFORM_AHCI
+        bool
+        default y if ARCH_MX53
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
index b41bf972b54b..c11ac8472beb 100644
--- a/arch/arm/plat-mxc/devices/Makefile
+++ b/arch/arm/plat-mxc/devices/Makefile
@@ -10,6 +10,7 @@ obj-y += platform-imx-dma.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD) += platform-imx-keypad.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_PATA_IMX) += platform-pata_imx.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o
@@ -25,3 +26,4 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RTC) += platform-mxc_rtc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) +=  platform-spi_imx.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_AHCI) +=  platform-ahci-imx.o
diff --git a/arch/arm/plat-mxc/devices/platform-ahci-imx.c b/arch/arm/plat-mxc/devices/platform-ahci-imx.c
new file mode 100644
index 000000000000..d8a56aee521b
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-ahci-imx.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <asm/sizes.h>
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+#define imx_ahci_imx_data_entry_single(soc, _devid)             \
+        {                                                               \
+                .devid = _devid,                                        \
+                .iobase = soc ## _SATA_BASE_ADDR,                       \
+                .irq = soc ## _INT_SATA,                                \
+        }
+#ifdef CONFIG_SOC_IMX53
+const struct imx_ahci_imx_data imx53_ahci_imx_data __initconst =
+        imx_ahci_imx_data_entry_single(MX53, "imx53-ahci");
+#endif
+enum {
+        HOST_CAP = 0x00,
+        HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
+        HOST_PORTS_IMPL = 0x0c,
+        HOST_TIMER1MS = 0xe0, /* Timer 1-ms */
+};
+static struct clk *sata_clk, *sata_ref_clk;
+/* AHCI module Initialization, if return 0, initialization is successful. */
+static int imx_sata_init(struct device *dev, void __iomem *addr)
+{
+        u32 tmpdata;
+        int ret = 0;
+        struct clk *clk;
+        sata_clk = clk_get(dev, "ahci");
+        if (IS_ERR(sata_clk)) {
+                dev_err(dev, "no sata clock.\n");
+                return PTR_ERR(sata_clk);
+        }
+        ret = clk_enable(sata_clk);
+        if (ret) {
+                dev_err(dev, "can't enable sata clock.\n");
+                goto put_sata_clk;
+        }
+        /* Get the AHCI SATA PHY CLK */
+        sata_ref_clk = clk_get(dev, "ahci_phy");
+        if (IS_ERR(sata_ref_clk)) {
+                dev_err(dev, "no sata ref clock.\n");
+                ret = PTR_ERR(sata_ref_clk);
+                goto release_sata_clk;
+        }
+        ret = clk_enable(sata_ref_clk);
+        if (ret) {
+                dev_err(dev, "can't enable sata ref clock.\n");
+                goto put_sata_ref_clk;
+        }
+        /* Get the AHB clock rate, and configure the TIMER1MS reg later */
+        clk = clk_get(dev, "ahci_dma");
+        if (IS_ERR(clk)) {
+                dev_err(dev, "no dma clock.\n");
+                ret = PTR_ERR(clk);
+                goto release_sata_ref_clk;
+        }
+        tmpdata = clk_get_rate(clk) / 1000;
+        clk_put(clk);
+        writel(tmpdata, addr + HOST_TIMER1MS);
+        tmpdata = readl(addr + HOST_CAP);
+        if (!(tmpdata & HOST_CAP_SSS)) {
+                tmpdata |= HOST_CAP_SSS;
+                writel(tmpdata, addr + HOST_CAP);
+        }
+        if (!(readl(addr + HOST_PORTS_IMPL) & 0x1))
+                writel((readl(addr + HOST_PORTS_IMPL) | 0x1),
+                        addr + HOST_PORTS_IMPL);
+        return 0;
+release_sata_ref_clk:
+        clk_disable(sata_ref_clk);
+put_sata_ref_clk:
+        clk_put(sata_ref_clk);
+release_sata_clk:
+        clk_disable(sata_clk);
+put_sata_clk:
+        clk_put(sata_clk);
+        return ret;
+}
+static void imx_sata_exit(struct device *dev)
+{
+        clk_disable(sata_ref_clk);
+        clk_put(sata_ref_clk);
+        clk_disable(sata_clk);
+        clk_put(sata_clk);
+}
+struct platform_device *__init imx_add_ahci_imx(
+                const struct imx_ahci_imx_data *data,
+                const struct ahci_platform_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + SZ_4K - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+        return imx_add_platform_device_dmamask(data->devid, 0,
+                        res, ARRAY_SIZE(res),
+                        pdata, sizeof(*pdata),  DMA_BIT_MASK(32));
+}
+struct platform_device *__init imx53_add_ahci_imx(void)
+{
+        struct ahci_platform_data pdata = {
+                .init = imx_sata_init,
+                .exit = imx_sata_exit,
+        };
+        return imx_add_ahci_imx(&imx53_ahci_imx_data, &pdata);
+}
diff --git a/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c
index 23ce08e6ffd2..848038f301fd 100644
--- a/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c
+++ b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c
@@ -36,6 +36,11 @@ const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst =
        imx_fsl_usb2_udc_data_entry_single(MX35);
 #endif /* ifdef CONFIG_SOC_IMX35 */
+#ifdef CONFIG_SOC_IMX51
+const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data __initconst =
+        imx_fsl_usb2_udc_data_entry_single(MX51);
+#endif
 struct platform_device *__init imx_add_fsl_usb2_udc(
                const struct imx_fsl_usb2_udc_data *data,
                const struct fsl_usb2_platform_data *pdata)
diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
index afe60f7244a8..19ad580c0be3 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
@@ -85,6 +85,12 @@ const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = {
        imx_imx_i2c_data_entry(MX51, _id, _hwid, SZ_4K)
        imx51_imx_i2c_data_entry(0, 1),
        imx51_imx_i2c_data_entry(1, 2),
+        {
+                .id = 2,
+                .iobase = MX51_HSI2C_DMA_BASE_ADDR,
+                .iosize = SZ_16K,
+                .irq = MX51_INT_HS_I2C,
+        },
 };
 #endif /* ifdef CONFIG_SOC_IMX51 */
diff --git a/arch/arm/plat-mxc/devices/platform-mxc-ehci.c b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c
index e1763e03e7cb..35851d889aca 100644
--- a/arch/arm/plat-mxc/devices/platform-mxc-ehci.c
+++ b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c
@@ -49,6 +49,15 @@ const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst =
        imx_mxc_ehci_data_entry_single(MX35, 1, HS);
 #endif /* ifdef CONFIG_SOC_IMX35 */
+#ifdef CONFIG_SOC_IMX51
+const struct imx_mxc_ehci_data imx51_mxc_ehci_otg_data __initconst =
+        imx_mxc_ehci_data_entry_single(MX51, 0, OTG);
+const struct imx_mxc_ehci_data imx51_mxc_ehci_hs_data[] __initconst = {
+        imx_mxc_ehci_data_entry_single(MX51, 1, HS1),
+        imx_mxc_ehci_data_entry_single(MX51, 2, HS2),
+};
+#endif /* ifdef CONFIG_SOC_IMX51 */
 struct platform_device *__init imx_add_mxc_ehci(
                const struct imx_mxc_ehci_data *data,
                const struct mxc_usbh_platform_data *pdata)
diff --git a/arch/arm/plat-mxc/devices/platform-pata_imx.c b/arch/arm/plat-mxc/devices/platform-pata_imx.c
new file mode 100644
index 000000000000..70e2f2a44714
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-pata_imx.c
@@ -0,0 +1,59 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+#define imx_pata_imx_data_entry_single(soc, _size)                      \
+        {                                                               \
+                .iobase = soc ## _ATA_BASE_ADDR,                        \
+                .iosize = _size,                                        \
+                .irq = soc ## _INT_ATA,                                 \
+        }
+#ifdef CONFIG_SOC_IMX27
+const struct imx_pata_imx_data imx27_pata_imx_data __initconst =
+        imx_pata_imx_data_entry_single(MX27, SZ_4K);
+#endif /* ifdef CONFIG_SOC_IMX27 */
+#ifdef CONFIG_SOC_IMX31
+const struct imx_pata_imx_data imx31_pata_imx_data __initconst =
+        imx_pata_imx_data_entry_single(MX31, SZ_16K);
+#endif /* ifdef CONFIG_SOC_IMX31 */
+#ifdef CONFIG_SOC_IMX35
+const struct imx_pata_imx_data imx35_pata_imx_data __initconst =
+        imx_pata_imx_data_entry_single(MX35, SZ_16K);
+#endif /* ifdef CONFIG_SOC_IMX35 */
+#ifdef CONFIG_SOC_IMX51
+const struct imx_pata_imx_data imx51_pata_imx_data __initconst =
+        imx_pata_imx_data_entry_single(MX51, SZ_16K);
+#endif /* ifdef CONFIG_SOC_IMX51 */
+#ifdef CONFIG_SOC_IMX53
+const struct imx_pata_imx_data imx53_pata_imx_data __initconst =
+        imx_pata_imx_data_entry_single(MX53, SZ_16K);
+#endif /* ifdef CONFIG_SOC_IMX53 */
+struct platform_device *__init imx_add_pata_imx(
+                const struct imx_pata_imx_data *data)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + data->iosize - 1,
+                        .flags = IORESOURCE_MEM,
+                },
+                {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+        return imx_add_platform_device("pata_imx", -1,
+                        res, ARRAY_SIZE(res), NULL, 0);
+}
diff --git a/arch/arm/plat-mxc/gic.c b/arch/arm/plat-mxc/gic.c
new file mode 100644
index 000000000000..b3b8eed263b8
--- /dev/null
+++ b/arch/arm/plat-mxc/gic.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/io.h>
+#include <asm/exception.h>
+#include <asm/localtimer.h>
+#include <asm/hardware/gic.h>
+#ifdef CONFIG_SMP
+#include <asm/smp.h>
+#endif
+asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
+{
+        u32 irqstat, irqnr;
+        do {
+                irqstat = readl_relaxed(gic_cpu_base_addr + GIC_CPU_INTACK);
+                irqnr = irqstat & 0x3ff;
+                if (irqnr == 1023)
+                        break;
+                if (irqnr > 29 && irqnr < 1021)
+                        handle_IRQ(irqnr, regs);
+#ifdef CONFIG_SMP
+                else if (irqnr < 16) {
+                        writel_relaxed(irqstat, gic_cpu_base_addr +
+                                                GIC_CPU_EOI);
+                        handle_IPI(irqnr, regs);
+                }
+#endif
+#ifdef CONFIG_LOCAL_TIMERS
+                else if (irqnr == 29) {
+                        writel_relaxed(irqstat, gic_cpu_base_addr +
+                                                GIC_CPU_EOI);
+                        handle_local_timer(regs);
+                }
+#endif
+        } while (1);
+}
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 4e3d97890d69..83b745a5e1b7 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -13,6 +13,7 @@
 struct platform_device;
 struct clk;
+enum mxc_cpu_pwr_mode;
 extern void mx1_map_io(void);
 extern void mx21_map_io(void);
@@ -64,12 +65,72 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
                        unsigned long ckih1, unsigned long ckih2);
 extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
                        unsigned long ckih1, unsigned long ckih2);
+extern int mx51_clocks_init_dt(void);
+extern int mx53_clocks_init_dt(void);
+extern int mx6q_clocks_init(void);
 extern struct platform_device *mxc_register_gpio(char *name, int id,
        resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
-extern int mxc_register_device(struct platform_device *pdev, void *data);
 extern void mxc_set_cpu_type(unsigned int type);
 extern void mxc_arch_reset_init(void __iomem *);
 extern void mx51_efikamx_reset(void);
 extern int mx53_revision(void);
 extern int mx53_display_revision(void);
+enum mxc_cpu_pwr_mode {
+        WAIT_CLOCKED,           /* wfi only */
+        WAIT_UNCLOCKED,         /* WAIT */
+        WAIT_UNCLOCKED_POWER_OFF,       /* WAIT + SRPG */
+        STOP_POWER_ON,          /* just STOP */
+        STOP_POWER_OFF,         /* STOP + SRPG */
+};
+extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
+extern void (*imx_idle)(void);
+extern void imx_print_silicon_rev(const char *cpu, int srev);
+void avic_handle_irq(struct pt_regs *);
+void tzic_handle_irq(struct pt_regs *);
+void gic_handle_irq(struct pt_regs *);
+#define imx1_handle_irq avic_handle_irq
+#define imx21_handle_irq avic_handle_irq
+#define imx25_handle_irq avic_handle_irq
+#define imx27_handle_irq avic_handle_irq
+#define imx31_handle_irq avic_handle_irq
+#define imx35_handle_irq avic_handle_irq
+#define imx50_handle_irq tzic_handle_irq
+#define imx51_handle_irq tzic_handle_irq
+#define imx53_handle_irq tzic_handle_irq
+#define imx6q_handle_irq gic_handle_irq
+extern void imx_enable_cpu(int cpu, bool enable);
+extern void imx_set_cpu_jump(int cpu, void *jump_addr);
+#ifdef CONFIG_DEBUG_LL
+extern void imx_lluart_map_io(void);
+#else
+static inline void imx_lluart_map_io(void) {}
+#endif
+extern void v7_cpu_resume(void);
+extern u32 *pl310_get_save_ptr(void);
+#ifdef CONFIG_SMP
+extern void v7_secondary_startup(void);
+extern void imx_scu_map_io(void);
+extern void imx_smp_prepare(void);
+#else
+static inline void imx_scu_map_io(void) {}
+static inline void imx_smp_prepare(void) {}
+#endif
+extern void imx_enable_cpu(int cpu, bool enable);
+extern void imx_set_cpu_jump(int cpu, void *jump_addr);
+extern void imx_src_init(void);
+extern void imx_gpc_init(void);
+extern void imx_gpc_pre_suspend(void);
+extern void imx_gpc_post_resume(void);
+extern void imx51_babbage_common_init(void);
+extern void imx53_ard_common_init(void);
+extern void imx53_evk_common_init(void);
+extern void imx53_qsb_common_init(void);
+extern void imx53_smd_common_init(void);
+extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
+extern void imx6q_pm_init(void);
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index a3045937fc2f..6e192c4a391a 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -12,44 +12,20 @@
 */
 #include <mach/hardware.h>
-#ifdef CONFIG_SOC_IMX1
+#ifdef CONFIG_DEBUG_IMX1_UART
 #define UART_PADDR      MX1_UART1_BASE_ADDR
-#endif
+#elif defined (CONFIG_DEBUG_IMX25_UART)
-#ifdef CONFIG_SOC_IMX25
-#ifdef UART_PADDR
-#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
-#endif
 #define UART_PADDR      MX25_UART1_BASE_ADDR
-#endif
+#elif defined (CONFIG_DEBUG_IMX21_IMX27_UART)
-#if defined(CONFIG_SOC_IMX21) || defined (CONFIG_SOC_IMX27)
-#ifdef UART_PADDR
-#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
-#endif
 #define UART_PADDR      MX2x_UART1_BASE_ADDR
-#endif
+#elif defined (CONFIG_DEBUG_IMX31_IMX35_UART)
-#if defined(CONFIG_SOC_IMX31) || defined(CONFIG_SOC_IMX35)
-#ifdef UART_PADDR
-#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
-#endif
 #define UART_PADDR      MX3x_UART1_BASE_ADDR
-#endif
+#elif defined (CONFIG_DEBUG_IMX51_UART)
-#ifdef CONFIG_SOC_IMX51
-#ifdef UART_PADDR
-#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
-#endif
 #define UART_PADDR      MX51_UART1_BASE_ADDR
-#endif
+#elif defined (CONFIG_DEBUG_IMX50_IMX53_UART)
-/* iMX50/53 have same addresses, but not iMX51 */
-#if defined(CONFIG_SOC_IMX50) || defined(CONFIG_SOC_IMX53)
-#ifdef UART_PADDR
-#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
-#endif
 #define UART_PADDR      MX53_UART1_BASE_ADDR
+#elif defined (CONFIG_DEBUG_IMX6Q_UART)
+#define UART_PADDR      MX6Q_UART4_BASE_ADDR
 #endif
 #define UART_VADDR      IMX_IO_ADDRESS(UART_PADDR)
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index 543525d76a60..def9ba53e23a 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -263,6 +263,14 @@ struct platform_device *__init imx_add_mxc_nand(
                const struct imx_mxc_nand_data *data,
                const struct mxc_nand_platform_data *pdata);
+struct imx_pata_imx_data {
+        resource_size_t iobase;
+        resource_size_t iosize;
+        resource_size_t irq;
+};
+struct platform_device *__init imx_add_pata_imx(
+                const struct imx_pata_imx_data *data);
 struct imx_mxc_pwm_data {
        int id;
        resource_size_t iobase;
@@ -313,3 +321,13 @@ struct platform_device *__init imx_add_spi_imx(
 struct platform_device *imx_add_imx_dma(void);
 struct platform_device *imx_add_imx_sdma(char *name,
        resource_size_t iobase, int irq, struct sdma_platform_data *pdata);
+#include <linux/ahci_platform.h>
+struct imx_ahci_imx_data {
+        const char *devid;
+        resource_size_t iobase;
+        resource_size_t irq;
+};
+struct platform_device *__init imx_add_ahci_imx(
+                const struct imx_ahci_imx_data *data,
+                const struct ahci_platform_data *pdata);
diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
index 066d464d322d..9fe0dfcf4e7e 100644
--- a/arch/arm/plat-mxc/include/mach/entry-macro.S
+++ b/arch/arm/plat-mxc/include/mach/entry-macro.S
@@ -9,72 +9,22 @@
 * published by the Free Software Foundation.
 */
-#include <mach/hardware.h>
+/* Unused, we use CONFIG_MULTI_IRQ_HANDLER */
-#define AVIC_NIMASK     0x04
-        @ this macro disables fast irq (not implemented)
        .macro  disable_fiq
        .endm
        .macro  get_irqnr_preamble, base, tmp
-#ifndef CONFIG_MXC_TZIC
-        ldr     \base, =avic_base
-        ldr     \base, [\base]
-#ifdef CONFIG_MXC_IRQ_PRIOR
-        ldr     r4, [\base, #AVIC_NIMASK]
-#endif
-#elif defined CONFIG_MXC_TZIC
-        ldr     \base, =tzic_base
-        ldr     \base, [\base]
-#endif /* CONFIG_MXC_TZIC */
        .endm
        .macro  arch_ret_to_user, tmp1, tmp2
        .endm
-        @ this macro checks which interrupt occurred
-        @ and returns its number in irqnr
-        @ and returns if an interrupt occurred in irqstat
        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-#ifndef CONFIG_MXC_TZIC
+        .endm
-        @ Load offset & priority of the highest priority
-        @ interrupt pending from AVIC_NIVECSR
+        .macro test_for_ipi, irqnr, irqstat, base, tmp
-        ldr     \irqstat, [\base, #0x40]
+        .endm
-        @ Shift to get the decoded IRQ number, using ASR so
-        @ 'no interrupt pending' becomes 0xffffffff
+        .macro test_for_ltirq, irqnr, irqstat, base, tmp
-        mov     \irqnr, \irqstat, asr #16
-        @ set zero flag if IRQ + 1 == 0
-        adds    \tmp, \irqnr, #1
-#ifdef CONFIG_MXC_IRQ_PRIOR
-        bicne   \tmp, \irqstat, #0xFFFFFFE0
-        strne   \tmp, [\base, #AVIC_NIMASK]
-        streq   r4, [\base, #AVIC_NIMASK]
-#endif
-#elif defined CONFIG_MXC_TZIC
-        @ Load offset & priority of the highest priority
-        @ interrupt pending.
-        @ 0x080 is INTSEC0 register
-        @ 0xD80 is HIPND0 register
-        mov     \irqnr, #0
-1000:   add     \irqstat, \base, \irqnr, lsr #3
-        ldr     \tmp, [\irqstat, #0xd80]
-        ldr     \irqstat, [\irqstat, #0x080]
-        ands    \tmp, \tmp, \irqstat
-        bne     1001f
-        add     \irqnr, \irqnr, #32
-        cmp     \irqnr, #128
-        blo     1000b
-        b       2001f
-1001:   mov     \irqstat, #1
-1002:   tst     \tmp, \irqstat
-        bne     2002f
-        movs    \tmp, \tmp, lsr #1
-        addne   \irqnr, \irqnr, #1
-        bne     1002b
-2001:
-        mov  \irqnr, #0
-2002:
-        movs \irqnr, \irqnr
-#endif
        .endm
diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h
index 3e1ffc8b8f0c..40a8c178f10d 100644
--- a/arch/arm/plat-mxc/include/mach/gpio.h
+++ b/arch/arm/plat-mxc/include/mach/gpio.h
@@ -1,33 +1 @@
-/*
+/* empty */
- * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- */
-#ifndef __ASM_ARCH_MXC_GPIO_H__
-#define __ASM_ARCH_MXC_GPIO_H__
-#include <linux/spinlock.h>
-#include <mach/hardware.h>
-/* There's a off-by-one betweem the gpio bank number and the gpiochip */
-/* range e.g. GPIO_1_5 is gpio 5 under linux */
-#define IMX_GPIO_NR(bank, nr)           (((bank) - 1) * 32 + (nr))
-#define gpio_to_irq(gpio)       (MXC_GPIO_IRQ_START + (gpio))
-#define irq_to_gpio(irq)        ((irq) - MXC_GPIO_IRQ_START)
-#endif
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index a8bfd565dcad..a599f01f8b92 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -81,11 +81,21 @@
 *      AIPS1   0x53f00000+0x100000     ->      0xf5700000+0x100000
 *      AIPS2   0x63f00000+0x100000     ->      0xf5300000+0x100000
 * mx51:
+ *      TZIC    0xe0000000+0x004000     ->      0xf5000000+0x004000
 *      IRAM    0x1ffe0000+0x020000     ->      0xf4fe0000+0x020000
- *      DEBUG   0x60000000+0x100000     ->      0xf5000000+0x100000
 *      SPBA0   0x70000000+0x100000     ->      0xf5400000+0x100000
 *      AIPS1   0x73f00000+0x100000     ->      0xf5700000+0x100000
 *      AIPS2   0x83f00000+0x100000     ->      0xf4300000+0x100000
+ * mx53:
+ *      TZIC    0x0fffc000+0x004000     ->      0xf4bfc000+0x004000
+ *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
+ *      AIPS1   0x53f00000+0x100000     ->      0xf5700000+0x100000
+ *      AIPS2   0x63f00000+0x100000     ->      0xf5300000+0x100000
+ * mx6q:
+ *      SCU     0x00a00000+0x001000     ->      0xf4000000+0x001000
+ *      CCM     0x020c4000+0x004000     ->      0xf42c4000+0x004000
+ *      ANATOP  0x020c8000+0x001000     ->      0xf42c8000+0x001000
+ *      UART4   0x021f0000+0x004000     ->      0xf42f0000+0x004000
 */
 #define IMX_IO_P2V(x)   (                                               \
                        0xf4000000 +                                    \
@@ -97,6 +107,7 @@
 #include <mach/mxc.h>
+#include <mach/mx6q.h>
 #include <mach/mx50.h>
 #include <mach/mx51.h>
 #include <mach/mx53.h>
@@ -116,4 +127,10 @@
        .type = _type,                                                  \
 }
+/* There's a off-by-one betweem the gpio bank number and the gpiochip */
+/* range e.g. GPIO_1_5 is gpio 5 under linux */
+#define IMX_GPIO_NR(bank, nr)           (((bank) - 1) * 32 + (nr))
+#define IMX_GPIO_TO_IRQ(gpio)   (MXC_GPIO_IRQ_START + (gpio))
 #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/io.h b/arch/arm/plat-mxc/include/mach/io.h
index 4347a87d2bb0..338300b18b00 100644
--- a/arch/arm/plat-mxc/include/mach/io.h
+++ b/arch/arm/plat-mxc/include/mach/io.h
@@ -14,32 +14,22 @@
 /* Allow IO space to be anywhere in the memory */
 #define IO_SPACE_LIMIT 0xffffffff
-#if defined(CONFIG_SOC_IMX31) || defined(CONFIG_SOC_IMX35)
-#include <mach/hardware.h>
 #define __arch_ioremap __imx_ioremap
 #define __arch_iounmap __iounmap
 #define addr_in_module(addr, mod) \
        ((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE)
+extern void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int);
 static inline void __iomem *
 __imx_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
 {
-        if (mtype == MT_DEVICE && (cpu_is_mx31() || cpu_is_mx35())) {
+        if (imx_ioremap != NULL)
-                /*
+                return imx_ioremap(phys_addr, size, mtype);
-                 * Access all peripherals below 0x80000000 as nonshared device
+        else
-                 * on mx3, but leave l2cc alone.  Otherwise cache corruptions
+                return __arm_ioremap(phys_addr, size, mtype);
-                 * can occur.
-                 */
-                if (phys_addr < 0x80000000 &&
-                                !addr_in_module(phys_addr, MX3x_L2CC))
-                        mtype = MT_DEVICE_NONSHARED;
-        }
-        return __arm_ioremap(phys_addr, size, mtype);
 }
-#endif
 /* io address mapping macro */
 #define __io(a)         __typesafe_io(a)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index c92f0b1f216f..63f22a009a65 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -735,6 +735,7 @@ enum iomux_pins {
 #define MX31_PIN_KEY_COL5_KEY_COL5      IOMUX_MODE(MX31_PIN_KEY_COL5, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_KEY_COL6_KEY_COL6      IOMUX_MODE(MX31_PIN_KEY_COL6, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_KEY_COL7_KEY_COL7      IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_WATCHDOG_RST__WATCHDOG_RST     IOMUX_MODE(MX31_PIN_WATCHDOG_RST, IOMUX_CONFIG_FUNC)
 /*
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index df6acc066fb1..c7f5169a6a54 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -14,6 +14,8 @@
 #define __MACH_IOMUX_MX51_H__
 #include <mach/iomux-v3.h>
+#define __NA_   0x000
 /* Pad control groupings */
 #define MX51_UART_PAD_CTRL      (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \
@@ -47,1521 +49,765 @@
 /* Raw pin modes without pad control */
 /*                                                        PAD    MUX ALT INPSE PATH PADCTRL */
-#define _MX51_PAD_EIM_D16__AUD4_RXFS            IOMUX_PAD(0x3f0, 0x5c, 5, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D16__AUD5_TXD             IOMUX_PAD(0x3f0, 0x5c, 7, 0x08d8, 0, 0)
-#define _MX51_PAD_EIM_D16__EIM_D16              IOMUX_PAD(0x3f0, 0x5c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D16__GPIO2_0              IOMUX_PAD(0x3f0, 0x5c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D16__I2C1_SDA             IOMUX_PAD(0x3f0, 0x5c, 0x14, 0x09b4, 0, 0)
-#define _MX51_PAD_EIM_D16__UART2_CTS            IOMUX_PAD(0x3f0, 0x5c, 3, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D16__USBH2_DATA0          IOMUX_PAD(0x3f0, 0x5c, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D17__AUD5_RXD             IOMUX_PAD(0x3f4, 0x60, 7, 0x08d4, 0, 0)
-#define _MX51_PAD_EIM_D17__EIM_D17              IOMUX_PAD(0x3f4, 0x60, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D17__GPIO2_1              IOMUX_PAD(0x3f4, 0x60, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D17__UART2_RXD            IOMUX_PAD(0x3f4, 0x60, 3, 0x09ec, 0, 0)
-#define _MX51_PAD_EIM_D17__UART3_CTS            IOMUX_PAD(0x3f4, 0x60, 4, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D17__USBH2_DATA1          IOMUX_PAD(0x3f4, 0x60, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D18__AUD5_TXC             IOMUX_PAD(0x3f8, 0x64, 7, 0x08e4, 0, 0)
-#define _MX51_PAD_EIM_D18__EIM_D18              IOMUX_PAD(0x3f8, 0x64, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D18__GPIO2_2              IOMUX_PAD(0x3f8, 0x64, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D18__UART2_TXD            IOMUX_PAD(0x3f8, 0x64, 3, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D18__UART3_RTS            IOMUX_PAD(0x3f8, 0x64, 4, 0x09f0, 1, 0)
-#define _MX51_PAD_EIM_D18__USBH2_DATA2          IOMUX_PAD(0x3f8, 0x64, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D19__AUD4_RXC             IOMUX_PAD(0x3fc, 0x68, 5, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D19__AUD5_TXFS            IOMUX_PAD(0x3fc, 0x68, 7, 0x08e8, 0, 0)
-#define _MX51_PAD_EIM_D19__EIM_D19              IOMUX_PAD(0x3fc, 0x68, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D19__GPIO2_3              IOMUX_PAD(0x3fc, 0x68, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D19__I2C1_SCL             IOMUX_PAD(0x3fc, 0x68, 0x14, 0x09b0, 0, 0)
-#define _MX51_PAD_EIM_D19__UART2_RTS            IOMUX_PAD(0x3fc, 0x68, 3, 0x09e8, 1, 0)
-#define _MX51_PAD_EIM_D19__USBH2_DATA3          IOMUX_PAD(0x3fc, 0x68, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D20__AUD4_TXD             IOMUX_PAD(0x400, 0x6c, 5, 0x08c8, 0, 0)
-#define _MX51_PAD_EIM_D20__EIM_D20              IOMUX_PAD(0x400, 0x6c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D20__GPIO2_4              IOMUX_PAD(0x400, 0x6c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D20__SRTC_ALARM_DEB       IOMUX_PAD(0x400, 0x6c, 4, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D20__USBH2_DATA4          IOMUX_PAD(0x400, 0x6c, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D21__AUD4_RXD             IOMUX_PAD(0x404, 0x70, 5, 0x08c4, 0, 0)
-#define _MX51_PAD_EIM_D21__EIM_D21              IOMUX_PAD(0x404, 0x70, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D21__GPIO2_5              IOMUX_PAD(0x404, 0x70, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D21__SRTC_ALARM_DEB       IOMUX_PAD(0x404, 0x70, 3, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D21__USBH2_DATA5          IOMUX_PAD(0x404, 0x70, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D22__AUD4_TXC             IOMUX_PAD(0x408, 0x74, 5, 0x08cc, 0, 0)
-#define _MX51_PAD_EIM_D22__EIM_D22              IOMUX_PAD(0x408, 0x74, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D22__GPIO2_6              IOMUX_PAD(0x408, 0x74, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D22__USBH2_DATA6          IOMUX_PAD(0x408, 0x74, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D23__AUD4_TXFS            IOMUX_PAD(0x40c, 0x78, 5, 0x08d0, 0, 0)
-#define _MX51_PAD_EIM_D23__EIM_D23              IOMUX_PAD(0x40c, 0x78, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D23__GPIO2_7              IOMUX_PAD(0x40c, 0x78, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D23__SPDIF_OUT1           IOMUX_PAD(0x40c, 0x78, 4, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D23__USBH2_DATA7          IOMUX_PAD(0x40c, 0x78, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D24__AUD6_RXFS            IOMUX_PAD(0x410, 0x7c, 5, 0x08f8, 0, 0)
-#define _MX51_PAD_EIM_D24__EIM_D24              IOMUX_PAD(0x410, 0x7c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D24__GPIO2_8              IOMUX_PAD(0x410, 0x7c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D24__I2C2_SDA             IOMUX_PAD(0x410, 0x7c, 0x14, 0x09bc, 0, 0)
-#define _MX51_PAD_EIM_D24__UART3_CTS            IOMUX_PAD(0x410, 0x7c, 3, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D24__USBOTG_DATA0         IOMUX_PAD(0x410, 0x7c, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D25__EIM_D25              IOMUX_PAD(0x414, 0x80, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D25__KEY_COL6             IOMUX_PAD(0x414, 0x80, 1, 0x09c8, 0, 0)
-#define _MX51_PAD_EIM_D25__UART2_CTS            IOMUX_PAD(0x414, 0x80, 4, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D25__UART3_RXD            IOMUX_PAD(0x414, 0x80, 3, 0x09f4, 0, 0)
-#define _MX51_PAD_EIM_D25__USBOTG_DATA1         IOMUX_PAD(0x414, 0x80, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D26__EIM_D26              IOMUX_PAD(0x418, 0x84, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D26__KEY_COL7             IOMUX_PAD(0x418, 0x84, 1, 0x09cc, 0, 0)
-#define _MX51_PAD_EIM_D26__UART2_RTS            IOMUX_PAD(0x418, 0x84, 4, 0x09e8, 3, 0)
-#define _MX51_PAD_EIM_D26__UART3_TXD            IOMUX_PAD(0x418, 0x84, 3, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D26__USBOTG_DATA2         IOMUX_PAD(0x418, 0x84, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D27__AUD6_RXC             IOMUX_PAD(0x41c, 0x88, 5, 0x08f4, 0, 0)
-#define _MX51_PAD_EIM_D27__EIM_D27              IOMUX_PAD(0x41c, 0x88, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D27__GPIO2_9              IOMUX_PAD(0x41c, 0x88, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D27__I2C2_SCL             IOMUX_PAD(0x41c, 0x88, 0x14, 0x09b8, 0, 0)
-#define _MX51_PAD_EIM_D27__UART3_RTS            IOMUX_PAD(0x41c, 0x88, 3, 0x09f0, 3, 0)
-#define _MX51_PAD_EIM_D27__USBOTG_DATA3         IOMUX_PAD(0x41c, 0x88, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D28__AUD6_TXD             IOMUX_PAD(0x420, 0x8c, 5, 0x08f0, 0, 0)
-#define _MX51_PAD_EIM_D28__EIM_D28              IOMUX_PAD(0x420, 0x8c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D28__KEY_ROW4             IOMUX_PAD(0x420, 0x8c, 1, 0x09d0, 0, 0)
-#define _MX51_PAD_EIM_D28__USBOTG_DATA4         IOMUX_PAD(0x420, 0x8c, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D29__AUD6_RXD             IOMUX_PAD(0x424, 0x90, 5, 0x08ec, 0, 0)
-#define _MX51_PAD_EIM_D29__EIM_D29              IOMUX_PAD(0x424, 0x90, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D29__KEY_ROW5             IOMUX_PAD(0x424, 0x90, 1, 0x09d4, 0, 0)
-#define _MX51_PAD_EIM_D29__USBOTG_DATA5         IOMUX_PAD(0x424, 0x90, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D30__AUD6_TXC             IOMUX_PAD(0x428, 0x94, 5, 0x08fc, 0, 0)
-#define _MX51_PAD_EIM_D30__EIM_D30              IOMUX_PAD(0x428, 0x94, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D30__KEY_ROW6             IOMUX_PAD(0x428, 0x94, 1, 0x09d8, 0, 0)
-#define _MX51_PAD_EIM_D30__USBOTG_DATA6         IOMUX_PAD(0x428, 0x94, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D31__AUD6_TXFS            IOMUX_PAD(0x42c, 0x98, 5, 0x0900, 0, 0)
-#define _MX51_PAD_EIM_D31__EIM_D31              IOMUX_PAD(0x42c, 0x98, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_D31__KEY_ROW7             IOMUX_PAD(0x42c, 0x98, 1, 0x09dc, 0, 0)
-#define _MX51_PAD_EIM_D31__USBOTG_DATA7         IOMUX_PAD(0x42c, 0x98, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A16__EIM_A16              IOMUX_PAD(0x430, 0x9c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A16__GPIO2_10             IOMUX_PAD(0x430, 0x9c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A16__OSC_FREQ_SEL0        IOMUX_PAD(0x430, 0x9c, 7, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A17__EIM_A17              IOMUX_PAD(0x434, 0xa0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A17__GPIO2_11             IOMUX_PAD(0x434, 0xa0, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A17__OSC_FREQ_SEL1        IOMUX_PAD(0x434, 0xa0, 7, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A18__BOOT_LPB0            IOMUX_PAD(0x438, 0xa4, 7, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A18__EIM_A18              IOMUX_PAD(0x438, 0xa4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A18__GPIO2_12             IOMUX_PAD(0x438, 0xa4, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A19__BOOT_LPB1            IOMUX_PAD(0x43c, 0xa8, 7, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A19__EIM_A19              IOMUX_PAD(0x43c, 0xa8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A19__GPIO2_13             IOMUX_PAD(0x43c, 0xa8, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A20__BOOT_UART_SRC0       IOMUX_PAD(0x440, 0xac, 7, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A20__EIM_A20              IOMUX_PAD(0x440, 0xac, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A20__GPIO2_14             IOMUX_PAD(0x440, 0xac, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A21__BOOT_UART_SRC1       IOMUX_PAD(0x444, 0xb0, 7, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A21__EIM_A21              IOMUX_PAD(0x444, 0xb0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A21__GPIO2_15             IOMUX_PAD(0x444, 0xb0, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A22__EIM_A22              IOMUX_PAD(0x448, 0xb4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A22__GPIO2_16             IOMUX_PAD(0x448, 0xb4, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A23__BOOT_HPN_EN          IOMUX_PAD(0x44c, 0xb8, 7, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A23__EIM_A23              IOMUX_PAD(0x44c, 0xb8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A23__GPIO2_17             IOMUX_PAD(0x44c, 0xb8, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A24__EIM_A24              IOMUX_PAD(0x450, 0xbc, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A24__GPIO2_18             IOMUX_PAD(0x450, 0xbc, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A24__USBH2_CLK            IOMUX_PAD(0x450, 0xbc, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A25__DISP1_PIN4           IOMUX_PAD(0x454, 0xc0, 6, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A25__EIM_A25              IOMUX_PAD(0x454, 0xc0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A25__GPIO2_19             IOMUX_PAD(0x454, 0xc0, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A25__USBH2_DIR            IOMUX_PAD(0x454, 0xc0, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A26__CSI1_DATA_EN         IOMUX_PAD(0x458, 0xc4, 5, 0x09a0, 0, 0)
-#define _MX51_PAD_EIM_A26__DISP2_EXT_CLK        IOMUX_PAD(0x458, 0xc4, 6, 0x0908, 0, 0)
-#define _MX51_PAD_EIM_A26__EIM_A26              IOMUX_PAD(0x458, 0xc4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A26__GPIO2_20             IOMUX_PAD(0x458, 0xc4, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A26__USBH2_STP            IOMUX_PAD(0x458, 0xc4, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A27__CSI2_DATA_EN         IOMUX_PAD(0x45c, 0xc8, 5, 0x099c, 0, 0)
-#define _MX51_PAD_EIM_A27__DISP1_PIN1           IOMUX_PAD(0x45c, 0xc8, 6, 0x09a4, 0, 0)
-#define _MX51_PAD_EIM_A27__EIM_A27              IOMUX_PAD(0x45c, 0xc8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A27__GPIO2_21             IOMUX_PAD(0x45c, 0xc8, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_A27__USBH2_NXT            IOMUX_PAD(0x45c, 0xc8, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_EB0__EIM_EB0              IOMUX_PAD(0x460, 0xcc, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_EB1__EIM_EB1              IOMUX_PAD(0x464, 0xd0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_EB2__AUD5_RXFS            IOMUX_PAD(0x468, 0xd4, 6, 0x08e0, 0, 0)
-#define _MX51_PAD_EIM_EB2__CSI1_D2              IOMUX_PAD(0x468, 0xd4, 5, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_EB2__EIM_EB2              IOMUX_PAD(0x468, 0xd4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_EB2__FEC_MDIO             IOMUX_PAD(0x468, 0xd4, 3, 0x0954, 0, 0)
-#define _MX51_PAD_EIM_EB2__GPIO2_22             IOMUX_PAD(0x468, 0xd4, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_EB2__GPT_CMPOUT1          IOMUX_PAD(0x468, 0xd4, 7, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_EB3__AUD5_RXC             IOMUX_PAD(0x46c, 0xd8, 6, 0x08dc, 0, 0)
-#define _MX51_PAD_EIM_EB3__CSI1_D3              IOMUX_PAD(0x46c, 0xd8, 5, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_EB3__EIM_EB3              IOMUX_PAD(0x46c, 0xd8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_EB3__FEC_RDATA1           IOMUX_PAD(0x46c, 0xd8, 3, 0x095c, 0, 0)
-#define _MX51_PAD_EIM_EB3__GPIO2_23             IOMUX_PAD(0x46c, 0xd8, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_EB3__GPT_CMPOUT2          IOMUX_PAD(0x46c, 0xd8, 7, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_OE__EIM_OE                IOMUX_PAD(0x470, 0xdc, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_OE__GPIO2_24              IOMUX_PAD(0x470, 0xdc, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS0__EIM_CS0              IOMUX_PAD(0x474, 0xe0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS0__GPIO2_25             IOMUX_PAD(0x474, 0xe0, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS1__EIM_CS1              IOMUX_PAD(0x478, 0xe4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS1__GPIO2_26             IOMUX_PAD(0x478, 0xe4, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS2__AUD5_TXD             IOMUX_PAD(0x47c, 0xe8, 6, 0x08d8, 1, 0)
-#define _MX51_PAD_EIM_CS2__CSI1_D4              IOMUX_PAD(0x47c, 0xe8, 5, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS2__EIM_CS2              IOMUX_PAD(0x47c, 0xe8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS2__FEC_RDATA2           IOMUX_PAD(0x47c, 0xe8, 3, 0x0960, 0, 0)
-#define _MX51_PAD_EIM_CS2__GPIO2_27             IOMUX_PAD(0x47c, 0xe8, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS2__USBOTG_STP           IOMUX_PAD(0x47c, 0xe8, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS3__AUD5_RXD             IOMUX_PAD(0x480, 0xec, 6, 0x08d4, 1, 0)
-#define _MX51_PAD_EIM_CS3__CSI1_D5              IOMUX_PAD(0x480, 0xec, 5, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS3__EIM_CS3              IOMUX_PAD(0x480, 0xec, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS3__FEC_RDATA3           IOMUX_PAD(0x480, 0xec, 3, 0x0964, 0, 0)
-#define _MX51_PAD_EIM_CS3__GPIO2_28             IOMUX_PAD(0x480, 0xec, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS3__USBOTG_NXT           IOMUX_PAD(0x480, 0xec, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS4__AUD5_TXC             IOMUX_PAD(0x484, 0xf0, 6, 0x08e4, 1, 0)
-#define _MX51_PAD_EIM_CS4__CSI1_D6              IOMUX_PAD(0x484, 0xf0, 5, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS4__EIM_CS4              IOMUX_PAD(0x484, 0xf0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS4__FEC_RX_ER            IOMUX_PAD(0x484, 0xf0, 3, 0x0970, 0, 0)
-#define _MX51_PAD_EIM_CS4__GPIO2_29             IOMUX_PAD(0x484, 0xf0, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS4__USBOTG_CLK           IOMUX_PAD(0x484, 0xf0, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS5__AUD5_TXFS            IOMUX_PAD(0x488, 0xf4, 6, 0x08e8, 1, 0)
-#define _MX51_PAD_EIM_CS5__CSI1_D7              IOMUX_PAD(0x488, 0xf4, 5, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS5__DISP1_EXT_CLK        IOMUX_PAD(0x488, 0xf4, 4, 0x0904, 0, 0)
-#define _MX51_PAD_EIM_CS5__EIM_CS5              IOMUX_PAD(0x488, 0xf4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS5__FEC_CRS              IOMUX_PAD(0x488, 0xf4, 3, 0x0950, 0, 0)
-#define _MX51_PAD_EIM_CS5__GPIO2_30             IOMUX_PAD(0x488, 0xf4, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CS5__USBOTG_DIR           IOMUX_PAD(0x488, 0xf4, 2, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DTACK__EIM_DTACK          IOMUX_PAD(0x48c, 0xf8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DTACK__GPIO2_31           IOMUX_PAD(0x48c, 0xf8, 1, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_LBA__EIM_LBA              IOMUX_PAD(0x494, 0xfc, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_LBA__GPIO3_1              IOMUX_PAD(0x494, 0xfc, 1, 0x0978, 0, 0)
-#define _MX51_PAD_EIM_CRE__EIM_CRE              IOMUX_PAD(0x4a0, 0x100, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_CRE__GPIO3_2              IOMUX_PAD(0x4a0, 0x100, 1, 0x097c, 0, 0)
-#define _MX51_PAD_DRAM_CS1__DRAM_CS1            IOMUX_PAD(0x4d0, 0x104, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_WE_B__GPIO3_3           IOMUX_PAD(0x4e4, 0x108, 3, 0x0980, 0, 0)
-#define _MX51_PAD_NANDF_WE_B__NANDF_WE_B        IOMUX_PAD(0x4e4, 0x108, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_WE_B__PATA_DIOW         IOMUX_PAD(0x4e4, 0x108, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_WE_B__SD3_DATA0         IOMUX_PAD(0x4e4, 0x108, 2, 0x093c, 0, 0)
-#define _MX51_PAD_NANDF_RE_B__GPIO3_4           IOMUX_PAD(0x4e8, 0x10c, 3, 0x0984, 0, 0)
-#define _MX51_PAD_NANDF_RE_B__NANDF_RE_B        IOMUX_PAD(0x4e8, 0x10c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RE_B__PATA_DIOR         IOMUX_PAD(0x4e8, 0x10c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RE_B__SD3_DATA1         IOMUX_PAD(0x4e8, 0x10c, 2, 0x0940, 0, 0)
-#define _MX51_PAD_NANDF_ALE__GPIO3_5            IOMUX_PAD(0x4ec, 0x110, 3, 0x0988, 0, 0)
-#define _MX51_PAD_NANDF_ALE__NANDF_ALE          IOMUX_PAD(0x4ec, 0x110, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_ALE__PATA_BUFFER_EN     IOMUX_PAD(0x4ec, 0x110, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CLE__GPIO3_6            IOMUX_PAD(0x4f0, 0x114, 3, 0x098c, 0, 0)
-#define _MX51_PAD_NANDF_CLE__NANDF_CLE          IOMUX_PAD(0x4f0, 0x114, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CLE__PATA_RESET_B       IOMUX_PAD(0x4f0, 0x114, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_WP_B__GPIO3_7           IOMUX_PAD(0x4f4, 0x118, 3, 0x0990, 0, 0)
-#define _MX51_PAD_NANDF_WP_B__NANDF_WP_B        IOMUX_PAD(0x4f4, 0x118, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_WP_B__PATA_DMACK        IOMUX_PAD(0x4f4, 0x118, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_WP_B__SD3_DATA2         IOMUX_PAD(0x4f4, 0x118, 2, 0x0944, 0, 0)
-#define _MX51_PAD_NANDF_RB0__ECSPI2_SS1         IOMUX_PAD(0x4f8, 0x11c, 5, 0x0930, 0, 0)
-#define _MX51_PAD_NANDF_RB0__GPIO3_8            IOMUX_PAD(0x4f8, 0x11c, 3, 0x0994, 0, 0)
-#define _MX51_PAD_NANDF_RB0__NANDF_RB0          IOMUX_PAD(0x4f8, 0x11c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RB0__PATA_DMARQ         IOMUX_PAD(0x4f8, 0x11c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RB0__SD3_DATA3          IOMUX_PAD(0x4f8, 0x11c, 2, 0x0948, 0, 0)
-#define _MX51_PAD_NANDF_RB1__CSPI_MOSI          IOMUX_PAD(0x4fc, 0x120, 6, 0x091c, 0, 0)
-#define _MX51_PAD_NANDF_RB1__ECSPI2_RDY         IOMUX_PAD(0x4fc, 0x120, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RB1__GPIO3_9            IOMUX_PAD(0x4fc, 0x120, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RB1__NANDF_RB1          IOMUX_PAD(0x4fc, 0x120, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RB1__PATA_IORDY         IOMUX_PAD(0x4fc, 0x120, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RB1__SD4_CMD            IOMUX_PAD(0x4fc, 0x120, 5, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RB2__DISP2_WAIT         IOMUX_PAD(0x500, 0x124, 5, 0x09a8, 0, 0)
-#define _MX51_PAD_NANDF_RB2__ECSPI2_SCLK        IOMUX_PAD(0x500, 0x124, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RB2__FEC_COL            IOMUX_PAD(0x500, 0x124, 1, 0x094c, 0, 0)
-#define _MX51_PAD_NANDF_RB2__GPIO3_10           IOMUX_PAD(0x500, 0x124, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RB2__NANDF_RB2          IOMUX_PAD(0x500, 0x124, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RB2__USBH3_H3_DP        IOMUX_PAD(0x500, 0x124, 7, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RB2__USBH3_NXT          IOMUX_PAD(0x500, 0x124, 6, 0x0a20, 0, 0)
-#define _MX51_PAD_NANDF_RB3__DISP1_WAIT         IOMUX_PAD(0x504, 0x128, 5, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RB3__ECSPI2_MISO        IOMUX_PAD(0x504, 0x128, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RB3__FEC_RX_CLK         IOMUX_PAD(0x504, 0x128, 1, 0x0968, 0, 0)
-#define _MX51_PAD_NANDF_RB3__GPIO3_11           IOMUX_PAD(0x504, 0x128, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RB3__NANDF_RB3          IOMUX_PAD(0x504, 0x128, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RB3__USBH3_CLK          IOMUX_PAD(0x504, 0x128, 6, 0x09f8, 0, 0)
-#define _MX51_PAD_NANDF_RB3__USBH3_H3_DM        IOMUX_PAD(0x504, 0x128, 7, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO_NAND__GPIO_NAND          IOMUX_PAD(0x514, 0x12c, 0, 0x0998, 0, 0)
-#define _MX51_PAD_GPIO_NAND__PATA_INTRQ         IOMUX_PAD(0x514, 0x12c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS0__GPIO3_16           IOMUX_PAD(0x518, 0x130, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS0__NANDF_CS0          IOMUX_PAD(0x518, 0x130, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS1__GPIO3_17           IOMUX_PAD(0x51c, 0x134, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS1__NANDF_CS1          IOMUX_PAD(0x51c, 0x134, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS2__CSPI_SCLK          IOMUX_PAD(0x520, 0x138, 6, 0x0914, 0, 0)
-#define _MX51_PAD_NANDF_CS2__FEC_TX_ER          IOMUX_PAD(0x520, 0x138, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS2__GPIO3_18           IOMUX_PAD(0x520, 0x138, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS2__NANDF_CS2          IOMUX_PAD(0x520, 0x138, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS2__PATA_CS_0          IOMUX_PAD(0x520, 0x138, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS2__SD4_CLK            IOMUX_PAD(0x520, 0x138, 5, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS2__USBH3_H1_DP        IOMUX_PAD(0x520, 0x138, 7, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS3__FEC_MDC            IOMUX_PAD(0x524, 0x13c, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS3__GPIO3_19           IOMUX_PAD(0x524, 0x13c, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS3__NANDF_CS3          IOMUX_PAD(0x524, 0x13c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS3__PATA_CS_1          IOMUX_PAD(0x524, 0x13c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS3__SD4_DAT0           IOMUX_PAD(0x524, 0x13c, 5, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS3__USBH3_H1_DM        IOMUX_PAD(0x524, 0x13c, 7, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS4__FEC_TDATA1         IOMUX_PAD(0x528, 0x140, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS4__GPIO3_20           IOMUX_PAD(0x528, 0x140, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS4__NANDF_CS4          IOMUX_PAD(0x528, 0x140, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS4__PATA_DA_0          IOMUX_PAD(0x528, 0x140, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS4__SD4_DAT1           IOMUX_PAD(0x528, 0x140, 5, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS4__USBH3_STP          IOMUX_PAD(0x528, 0x140, 7, 0x0a24, 0, 0)
-#define _MX51_PAD_NANDF_CS5__FEC_TDATA2         IOMUX_PAD(0x52c, 0x144, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS5__GPIO3_21           IOMUX_PAD(0x52c, 0x144, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS5__NANDF_CS5          IOMUX_PAD(0x52c, 0x144, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS5__PATA_DA_1          IOMUX_PAD(0x52c, 0x144, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS5__SD4_DAT2           IOMUX_PAD(0x52c, 0x144, 5, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS5__USBH3_DIR          IOMUX_PAD(0x52c, 0x144, 7, 0x0a1c, 0, 0)
-#define _MX51_PAD_NANDF_CS6__CSPI_SS3           IOMUX_PAD(0x530, 0x148, 7, 0x0928, 0, 0)
-#define _MX51_PAD_NANDF_CS6__FEC_TDATA3         IOMUX_PAD(0x530, 0x148, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS6__GPIO3_22           IOMUX_PAD(0x530, 0x148, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS6__NANDF_CS6          IOMUX_PAD(0x530, 0x148, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS6__PATA_DA_2          IOMUX_PAD(0x530, 0x148, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS6__SD4_DAT3           IOMUX_PAD(0x530, 0x148, 5, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS7__FEC_TX_EN          IOMUX_PAD(0x534, 0x14c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS7__GPIO3_23           IOMUX_PAD(0x534, 0x14c, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS7__NANDF_CS7          IOMUX_PAD(0x534, 0x14c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_CS7__SD3_CLK            IOMUX_PAD(0x534, 0x14c, 5, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0     IOMUX_PAD(0x538, 0x150, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK     IOMUX_PAD(0x538, 0x150, 1, 0x0974, 0, 0)
-#define _MX51_PAD_NANDF_RDY_INT__GPIO3_24       IOMUX_PAD(0x538, 0x150, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT  IOMUX_PAD(0x538, 0x150, 0, 0x0938, 0, 0)
-#define _MX51_PAD_NANDF_RDY_INT__SD3_CMD        IOMUX_PAD(0x538, 0x150, 5, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D15__ECSPI2_MOSI        IOMUX_PAD(0x53c, 0x154, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D15__GPIO3_25           IOMUX_PAD(0x53c, 0x154, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D15__NANDF_D15          IOMUX_PAD(0x53c, 0x154, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D15__PATA_DATA15        IOMUX_PAD(0x53c, 0x154, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D15__SD3_DAT7           IOMUX_PAD(0x53c, 0x154, 5, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D14__ECSPI2_SS3         IOMUX_PAD(0x540, 0x158, 2, 0x0934, 0, 0)
-#define _MX51_PAD_NANDF_D14__GPIO3_26           IOMUX_PAD(0x540, 0x158, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D14__NANDF_D14          IOMUX_PAD(0x540, 0x158, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D14__PATA_DATA14        IOMUX_PAD(0x540, 0x158, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D14__SD3_DAT6           IOMUX_PAD(0x540, 0x158, 5, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D13__ECSPI2_SS2         IOMUX_PAD(0x544, 0x15c, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D13__GPIO3_27           IOMUX_PAD(0x544, 0x15c, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D13__NANDF_D13          IOMUX_PAD(0x544, 0x15c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D13__PATA_DATA13        IOMUX_PAD(0x544, 0x15c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D13__SD3_DAT5           IOMUX_PAD(0x544, 0x15c, 5, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D12__ECSPI2_SS1         IOMUX_PAD(0x548, 0x160, 2, 0x0930, 1, 0)
-#define _MX51_PAD_NANDF_D12__GPIO3_28           IOMUX_PAD(0x548, 0x160, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D12__NANDF_D12          IOMUX_PAD(0x548, 0x160, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D12__PATA_DATA12        IOMUX_PAD(0x548, 0x160, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D12__SD3_DAT4           IOMUX_PAD(0x548, 0x160, 5, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D11__FEC_RX_DV          IOMUX_PAD(0x54c, 0x164, 2, 0x096c, 0, 0)
-#define _MX51_PAD_NANDF_D11__GPIO3_29           IOMUX_PAD(0x54c, 0x164, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D11__NANDF_D11          IOMUX_PAD(0x54c, 0x164, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D11__PATA_DATA11        IOMUX_PAD(0x54c, 0x164, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D11__SD3_DATA3          IOMUX_PAD(0x54c, 0x164, 5, 0x0948, 1, 0)
-#define _MX51_PAD_NANDF_D10__GPIO3_30           IOMUX_PAD(0x550, 0x168, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D10__NANDF_D10          IOMUX_PAD(0x550, 0x168, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D10__PATA_DATA10        IOMUX_PAD(0x550, 0x168, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D10__SD3_DATA2          IOMUX_PAD(0x550, 0x168, 5, 0x0944, 1, 0)
-#define _MX51_PAD_NANDF_D9__FEC_RDATA0          IOMUX_PAD(0x554, 0x16c, 0x12, 0x0958, 0, 0)
-#define _MX51_PAD_NANDF_D9__GPIO3_31            IOMUX_PAD(0x554, 0x16c, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D9__NANDF_D9            IOMUX_PAD(0x554, 0x16c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D9__PATA_DATA9          IOMUX_PAD(0x554, 0x16c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D9__SD3_DATA1           IOMUX_PAD(0x554, 0x16c, 5, 0x0940, 1, 0)
-#define _MX51_PAD_NANDF_D8__FEC_TDATA0          IOMUX_PAD(0x558, 0x170, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D8__GPIO4_0             IOMUX_PAD(0x558, 0x170, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D8__NANDF_D8            IOMUX_PAD(0x558, 0x170, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D8__PATA_DATA8          IOMUX_PAD(0x558, 0x170, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D8__SD3_DATA0           IOMUX_PAD(0x558, 0x170, 5, 0x093c, 1, 0)
-#define _MX51_PAD_NANDF_D7__GPIO4_1             IOMUX_PAD(0x55c, 0x174, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D7__NANDF_D7            IOMUX_PAD(0x55c, 0x174, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D7__PATA_DATA7          IOMUX_PAD(0x55c, 0x174, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D7__USBH3_DATA0         IOMUX_PAD(0x55c, 0x174, 5, 0x09fc, 0, 0)
-#define _MX51_PAD_NANDF_D6__GPIO4_2             IOMUX_PAD(0x560, 0x178, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D6__NANDF_D6            IOMUX_PAD(0x560, 0x178, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D6__PATA_DATA6          IOMUX_PAD(0x560, 0x178, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D6__SD4_LCTL            IOMUX_PAD(0x560, 0x178, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D6__USBH3_DATA1         IOMUX_PAD(0x560, 0x178, 5, 0x0a00, 0, 0)
-#define _MX51_PAD_NANDF_D5__GPIO4_3             IOMUX_PAD(0x564, 0x17c, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D5__NANDF_D5            IOMUX_PAD(0x564, 0x17c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D5__PATA_DATA5          IOMUX_PAD(0x564, 0x17c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D5__SD4_WP              IOMUX_PAD(0x564, 0x17c, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D5__USBH3_DATA2         IOMUX_PAD(0x564, 0x17c, 5, 0x0a04, 0, 0)
-#define _MX51_PAD_NANDF_D4__GPIO4_4             IOMUX_PAD(0x568, 0x180, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D4__NANDF_D4            IOMUX_PAD(0x568, 0x180, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D4__PATA_DATA4          IOMUX_PAD(0x568, 0x180, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D4__SD4_CD              IOMUX_PAD(0x568, 0x180, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D4__USBH3_DATA3         IOMUX_PAD(0x568, 0x180, 5, 0x0a08, 0, 0)
-#define _MX51_PAD_NANDF_D3__GPIO4_5             IOMUX_PAD(0x56c, 0x184, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D3__NANDF_D3            IOMUX_PAD(0x56c, 0x184, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D3__PATA_DATA3          IOMUX_PAD(0x56c, 0x184, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D3__SD4_DAT4            IOMUX_PAD(0x56c, 0x184, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D3__USBH3_DATA4         IOMUX_PAD(0x56c, 0x184, 5, 0x0a0c, 0, 0)
-#define _MX51_PAD_NANDF_D2__GPIO4_6             IOMUX_PAD(0x570, 0x188, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D2__NANDF_D2            IOMUX_PAD(0x570, 0x188, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D2__PATA_DATA2          IOMUX_PAD(0x570, 0x188, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D2__SD4_DAT5            IOMUX_PAD(0x570, 0x188, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D2__USBH3_DATA5         IOMUX_PAD(0x570, 0x188, 5, 0x0a10, 0, 0)
-#define _MX51_PAD_NANDF_D1__GPIO4_7             IOMUX_PAD(0x574, 0x18c, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D1__NANDF_D1            IOMUX_PAD(0x574, 0x18c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D1__PATA_DATA1          IOMUX_PAD(0x574, 0x18c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D1__SD4_DAT6            IOMUX_PAD(0x574, 0x18c, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D1__USBH3_DATA6         IOMUX_PAD(0x574, 0x18c, 5, 0x0a14, 0, 0)
-#define _MX51_PAD_NANDF_D0__GPIO4_8             IOMUX_PAD(0x578, 0x190, 3, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D0__NANDF_D0            IOMUX_PAD(0x578, 0x190, 0, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D0__PATA_DATA0          IOMUX_PAD(0x578, 0x190, 1, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D0__SD4_DAT7            IOMUX_PAD(0x578, 0x190, 2, 0x0000, 0, 0)
-#define _MX51_PAD_NANDF_D0__USBH3_DATA7         IOMUX_PAD(0x578, 0x190, 5, 0x0a18, 0, 0)
-#define _MX51_PAD_CSI1_D8__CSI1_D8              IOMUX_PAD(0x57c, 0x194, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_D8__GPIO3_12             IOMUX_PAD(0x57c, 0x194, 3, 0x0998, 1, 0)
-#define _MX51_PAD_CSI1_D9__CSI1_D9              IOMUX_PAD(0x580, 0x198, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_D9__GPIO3_13             IOMUX_PAD(0x580, 0x198, 3, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_D10__CSI1_D10            IOMUX_PAD(0x584, 0x19c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_D11__CSI1_D11            IOMUX_PAD(0x588, 0x1a0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_D12__CSI1_D12            IOMUX_PAD(0x58c, 0x1a4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_D13__CSI1_D13            IOMUX_PAD(0x590, 0x1a8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_D14__CSI1_D14            IOMUX_PAD(0x594, 0x1ac, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_D15__CSI1_D15            IOMUX_PAD(0x598, 0x1b0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_D16__CSI1_D16            IOMUX_PAD(0x59c, 0x1b4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_D17__CSI1_D17            IOMUX_PAD(0x5a0, 0x1b8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_D18__CSI1_D18            IOMUX_PAD(0x5a4, 0x1bc, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_D19__CSI1_D19            IOMUX_PAD(0x5a8, 0x1c0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_VSYNC__CSI1_VSYNC        IOMUX_PAD(0x5ac, 0x1c4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_VSYNC__GPIO3_14          IOMUX_PAD(0x5ac, 0x1c4, 3, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_HSYNC__CSI1_HSYNC        IOMUX_PAD(0x5b0, 0x1c8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_HSYNC__GPIO3_15          IOMUX_PAD(0x5b0, 0x1c8, 3, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK      IOMUX_PAD(0x5b4, 0x000, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI1_MCLK__CSI1_MCLK          IOMUX_PAD(0x5b8, 0x000, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_D12__CSI2_D12            IOMUX_PAD(0x5bc, 0x1cc, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_D12__GPIO4_9             IOMUX_PAD(0x5bc, 0x1cc, 3, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_D13__CSI2_D13            IOMUX_PAD(0x5c0, 0x1d0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_D13__GPIO4_10            IOMUX_PAD(0x5c0, 0x1d0, 3, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_D14__CSI2_D14            IOMUX_PAD(0x5c4, 0x1d4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_D15__CSI2_D15            IOMUX_PAD(0x5c8, 0x1d8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_D16__CSI2_D16            IOMUX_PAD(0x5cc, 0x1dc, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_D17__CSI2_D17            IOMUX_PAD(0x5d0, 0x1e0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_D18__CSI2_D18            IOMUX_PAD(0x5d4, 0x1e4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_D18__GPIO4_11            IOMUX_PAD(0x5d4, 0x1e4, 3, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_D19__CSI2_D19            IOMUX_PAD(0x5d8, 0x1e8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_D19__GPIO4_12            IOMUX_PAD(0x5d8, 0x1e8, 3, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_VSYNC__CSI2_VSYNC        IOMUX_PAD(0x5dc, 0x1ec, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_VSYNC__GPIO4_13          IOMUX_PAD(0x5dc, 0x1ec, 3, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_HSYNC__CSI2_HSYNC        IOMUX_PAD(0x5e0, 0x1f0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_HSYNC__GPIO4_14          IOMUX_PAD(0x5e0, 0x1f0, 3, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK      IOMUX_PAD(0x5e4, 0x1f4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSI2_PIXCLK__GPIO4_15         IOMUX_PAD(0x5e4, 0x1f4, 3, 0x0000, 0, 0)
-#define _MX51_PAD_I2C1_CLK__GPIO4_16            IOMUX_PAD(0x5e8, 0x1f8, 3, 0x0000, 0, 0)
-#define _MX51_PAD_I2C1_CLK__I2C1_CLK            IOMUX_PAD(0x5e8, 0x1f8, 0x10, 0x0000, 0, 0)
-#define _MX51_PAD_I2C1_DAT__GPIO4_17            IOMUX_PAD(0x5ec, 0x1fc, 3, 0x0000, 0, 0)
-#define _MX51_PAD_I2C1_DAT__I2C1_DAT            IOMUX_PAD(0x5ec, 0x1fc, 0x10, 0x0000, 0, 0)
-#define _MX51_PAD_AUD3_BB_TXD__AUD3_TXD         IOMUX_PAD(0x5f0, 0x200, 0, 0x0000, 0, 0)
-#define _MX51_PAD_AUD3_BB_TXD__GPIO4_18         IOMUX_PAD(0x5f0, 0x200, 3, 0x0000, 0, 0)
-#define _MX51_PAD_AUD3_BB_RXD__AUD3_RXD         IOMUX_PAD(0x5f4, 0x204, 0, 0x0000, 0, 0)
-#define _MX51_PAD_AUD3_BB_RXD__GPIO4_19         IOMUX_PAD(0x5f4, 0x204, 3, 0x0000, 0, 0)
-#define _MX51_PAD_AUD3_BB_RXD__UART3_RXD        IOMUX_PAD(0x5f4, 0x204, 1, 0x09f4, 2, 0)
-#define _MX51_PAD_AUD3_BB_CK__AUD3_TXC          IOMUX_PAD(0x5f8, 0x208, 0, 0x0000, 0, 0)
-#define _MX51_PAD_AUD3_BB_CK__GPIO4_20          IOMUX_PAD(0x5f8, 0x208, 3, 0x0000, 0, 0)
-#define _MX51_PAD_AUD3_BB_FS__AUD3_TXFS         IOMUX_PAD(0x5fc, 0x20c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_AUD3_BB_FS__GPIO4_21          IOMUX_PAD(0x5fc, 0x20c, 3, 0x0000, 0, 0)
-#define _MX51_PAD_AUD3_BB_FS__UART3_TXD         IOMUX_PAD(0x5fc, 0x20c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI       IOMUX_PAD(0x600, 0x210, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSPI1_MOSI__GPIO4_22          IOMUX_PAD(0x600, 0x210, 3, 0x0000, 0, 0)
-#define _MX51_PAD_CSPI1_MOSI__I2C1_SDA          IOMUX_PAD(0x600, 0x210, 0x11, 0x09b4, 1, 0)
-#define _MX51_PAD_CSPI1_MISO__AUD4_RXD          IOMUX_PAD(0x604, 0x214, 1, 0x08c4, 1, 0)
-#define _MX51_PAD_CSPI1_MISO__ECSPI1_MISO       IOMUX_PAD(0x604, 0x214, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSPI1_MISO__GPIO4_23          IOMUX_PAD(0x604, 0x214, 3, 0x0000, 0, 0)
-#define _MX51_PAD_CSPI1_SS0__AUD4_TXC           IOMUX_PAD(0x608, 0x218, 1, 0x08cc, 1, 0)
-#define _MX51_PAD_CSPI1_SS0__ECSPI1_SS0         IOMUX_PAD(0x608, 0x218, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSPI1_SS0__GPIO4_24           IOMUX_PAD(0x608, 0x218, 3, 0x0000, 0, 0)
-#define _MX51_PAD_CSPI1_SS1__AUD4_TXD           IOMUX_PAD(0x60c, 0x21c, 1, 0x08c8, 1, 0)
-#define _MX51_PAD_CSPI1_SS1__ECSPI1_SS1         IOMUX_PAD(0x60c, 0x21c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSPI1_SS1__GPIO4_25           IOMUX_PAD(0x60c, 0x21c, 3, 0x0000, 0, 0)
-#define _MX51_PAD_CSPI1_RDY__AUD4_TXFS          IOMUX_PAD(0x610, 0x220, 1, 0x08d0, 1, 0)
-#define _MX51_PAD_CSPI1_RDY__ECSPI1_RDY         IOMUX_PAD(0x610, 0x220, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSPI1_RDY__GPIO4_26           IOMUX_PAD(0x610, 0x220, 3, 0x0000, 0, 0)
-#define _MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK       IOMUX_PAD(0x614, 0x224, 0, 0x0000, 0, 0)
-#define _MX51_PAD_CSPI1_SCLK__GPIO4_27          IOMUX_PAD(0x614, 0x224, 3, 0x0000, 0, 0)
-#define _MX51_PAD_CSPI1_SCLK__I2C1_SCL          IOMUX_PAD(0x614, 0x224, 0x11, 0x09b0, 1, 0)
-#define _MX51_PAD_UART1_RXD__GPIO4_28           IOMUX_PAD(0x618, 0x228, 3, 0x0000, 0, 0)
-#define _MX51_PAD_UART1_RXD__UART1_RXD          IOMUX_PAD(0x618, 0x228, 0, 0x09e4, 0, 0)
-#define _MX51_PAD_UART1_TXD__GPIO4_29           IOMUX_PAD(0x61c, 0x22c, 3, 0x0000, 0, 0)
-#define _MX51_PAD_UART1_TXD__PWM2_PWMO          IOMUX_PAD(0x61c, 0x22c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_UART1_TXD__UART1_TXD          IOMUX_PAD(0x61c, 0x22c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_UART1_RTS__GPIO4_30           IOMUX_PAD(0x620, 0x230, 3, 0x0000, 0, 0)
-#define _MX51_PAD_UART1_RTS__UART1_RTS          IOMUX_PAD(0x620, 0x230, 0, 0x09e0, 0, 0)
-#define _MX51_PAD_UART1_CTS__GPIO4_31           IOMUX_PAD(0x624, 0x234, 3, 0x0000, 0, 0)
-#define _MX51_PAD_UART1_CTS__UART1_CTS          IOMUX_PAD(0x624, 0x234, 0, 0x0000, 0, 0)
-#define _MX51_PAD_UART2_RXD__FIRI_TXD           IOMUX_PAD(0x628, 0x238, 1, 0x0000, 0, 0)
-#define _MX51_PAD_UART2_RXD__GPIO1_20           IOMUX_PAD(0x628, 0x238, 3, 0x0000, 0, 0)
-#define _MX51_PAD_UART2_RXD__UART2_RXD          IOMUX_PAD(0x628, 0x238, 0, 0x09ec, 2, 0)
-#define _MX51_PAD_UART2_TXD__FIRI_RXD           IOMUX_PAD(0x62c, 0x23c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_UART2_TXD__GPIO1_21           IOMUX_PAD(0x62c, 0x23c, 3, 0x0000, 0, 0)
-#define _MX51_PAD_UART2_TXD__UART2_TXD          IOMUX_PAD(0x62c, 0x23c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_UART3_RXD__CSI1_D0            IOMUX_PAD(0x630, 0x240, 2, 0x0000, 0, 0)
-#define _MX51_PAD_UART3_RXD__GPIO1_22           IOMUX_PAD(0x630, 0x240, 3, 0x0000, 0, 0)
-#define _MX51_PAD_UART3_RXD__UART1_DTR          IOMUX_PAD(0x630, 0x240, 0, 0x0000, 0, 0)
-#define _MX51_PAD_UART3_RXD__UART3_RXD          IOMUX_PAD(0x630, 0x240, 1, 0x09f4, 4, 0)
-#define _MX51_PAD_UART3_TXD__CSI1_D1            IOMUX_PAD(0x634, 0x244, 2, 0x0000, 0, 0)
-#define _MX51_PAD_UART3_TXD__GPIO1_23           IOMUX_PAD(0x634, 0x244, 3, 0x0000, 0, 0)
-#define _MX51_PAD_UART3_TXD__UART1_DSR          IOMUX_PAD(0x634, 0x244, 0, 0x0000, 0, 0)
-#define _MX51_PAD_UART3_TXD__UART3_TXD          IOMUX_PAD(0x634, 0x244, 1, 0x0000, 0, 0)
-#define _MX51_PAD_OWIRE_LINE__GPIO1_24          IOMUX_PAD(0x638, 0x248, 3, 0x0000, 0, 0)
-#define _MX51_PAD_OWIRE_LINE__OWIRE_LINE        IOMUX_PAD(0x638, 0x248, 0, 0x0000, 0, 0)
-#define _MX51_PAD_OWIRE_LINE__SPDIF_OUT         IOMUX_PAD(0x638, 0x248, 6, 0x0000, 0, 0)
-#define _MX51_PAD_KEY_ROW0__KEY_ROW0            IOMUX_PAD(0x63c, 0x24c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_KEY_ROW1__KEY_ROW1            IOMUX_PAD(0x640, 0x250, 0, 0x0000, 0, 0)
-#define _MX51_PAD_KEY_ROW2__KEY_ROW2            IOMUX_PAD(0x644, 0x254, 0, 0x0000, 0, 0)
-#define _MX51_PAD_KEY_ROW3__KEY_ROW3            IOMUX_PAD(0x648, 0x258, 0, 0x0000, 0, 0)
-#define _MX51_PAD_KEY_COL0__KEY_COL0            IOMUX_PAD(0x64c, 0x25c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_KEY_COL0__PLL1_BYP            IOMUX_PAD(0x64c, 0x25c, 7, 0x090c, 0, 0)
-#define _MX51_PAD_KEY_COL1__KEY_COL1            IOMUX_PAD(0x650, 0x260, 0, 0x0000, 0, 0)
-#define _MX51_PAD_KEY_COL1__PLL2_BYP            IOMUX_PAD(0x650, 0x260, 7, 0x0910, 0, 0)
-#define _MX51_PAD_KEY_COL2__KEY_COL2            IOMUX_PAD(0x654, 0x264, 0, 0x0000, 0, 0)
-#define _MX51_PAD_KEY_COL2__PLL3_BYP            IOMUX_PAD(0x654, 0x264, 7, 0x0000, 0, 0)
-#define _MX51_PAD_KEY_COL3__KEY_COL3            IOMUX_PAD(0x658, 0x268, 0, 0x0000, 0, 0)
-#define _MX51_PAD_KEY_COL4__I2C2_SCL            IOMUX_PAD(0x65c, 0x26c, 0x13, 0x09b8, 1, 0)
-#define _MX51_PAD_KEY_COL4__KEY_COL4            IOMUX_PAD(0x65c, 0x26c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_KEY_COL4__SPDIF_OUT1          IOMUX_PAD(0x65c, 0x26c, 6, 0x0000, 0, 0)
-#define _MX51_PAD_KEY_COL4__UART1_RI            IOMUX_PAD(0x65c, 0x26c, 1, 0x0000, 0, 0)
-#define _MX51_PAD_KEY_COL4__UART3_RTS           IOMUX_PAD(0x65c, 0x26c, 2, 0x09f0, 4, 0)
-#define _MX51_PAD_KEY_COL5__I2C2_SDA            IOMUX_PAD(0x660, 0x270, 0x13, 0x09bc, 1, 0)
-#define _MX51_PAD_KEY_COL5__KEY_COL5            IOMUX_PAD(0x660, 0x270, 0, 0x0000, 0, 0)
-#define _MX51_PAD_KEY_COL5__UART1_DCD           IOMUX_PAD(0x660, 0x270, 1, 0x0000, 0, 0)
-#define _MX51_PAD_KEY_COL5__UART3_CTS           IOMUX_PAD(0x660, 0x270, 2, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_CLK__CSPI_SCLK          IOMUX_PAD(0x678, 0x278, 1, 0x0914, 1, 0)
-#define _MX51_PAD_USBH1_CLK__GPIO1_25           IOMUX_PAD(0x678, 0x278, 2, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_CLK__I2C2_SCL           IOMUX_PAD(0x678, 0x278, 0x15, 0x09b8, 2, 0)
-#define _MX51_PAD_USBH1_CLK__USBH1_CLK          IOMUX_PAD(0x678, 0x278, 0, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DIR__CSPI_MOSI          IOMUX_PAD(0x67c, 0x27c, 1, 0x091c, 1, 0)
-#define _MX51_PAD_USBH1_DIR__GPIO1_26           IOMUX_PAD(0x67c, 0x27c, 2, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DIR__I2C2_SDA           IOMUX_PAD(0x67c, 0x27c, 0x15, 0x09bc, 2, 0)
-#define _MX51_PAD_USBH1_DIR__USBH1_DIR          IOMUX_PAD(0x67c, 0x27c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_STP__CSPI_RDY           IOMUX_PAD(0x680, 0x280, 1, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_STP__GPIO1_27           IOMUX_PAD(0x680, 0x280, 2, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_STP__UART3_RXD          IOMUX_PAD(0x680, 0x280, 5, 0x09f4, 6, 0)
-#define _MX51_PAD_USBH1_STP__USBH1_STP          IOMUX_PAD(0x680, 0x280, 0, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_NXT__CSPI_MISO          IOMUX_PAD(0x684, 0x284, 1, 0x0918, 0, 0)
-#define _MX51_PAD_USBH1_NXT__GPIO1_28           IOMUX_PAD(0x684, 0x284, 2, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_NXT__UART3_TXD          IOMUX_PAD(0x684, 0x284, 5, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_NXT__USBH1_NXT          IOMUX_PAD(0x684, 0x284, 0, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA0__GPIO1_11         IOMUX_PAD(0x688, 0x288, 2, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA0__UART2_CTS        IOMUX_PAD(0x688, 0x288, 1, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA0__USBH1_DATA0      IOMUX_PAD(0x688, 0x288, 0, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA1__GPIO1_12         IOMUX_PAD(0x68c, 0x28c, 2, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA1__UART2_RXD        IOMUX_PAD(0x68c, 0x28c, 1, 0x09ec, 4, 0)
-#define _MX51_PAD_USBH1_DATA1__USBH1_DATA1      IOMUX_PAD(0x68c, 0x28c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA2__GPIO1_13         IOMUX_PAD(0x690, 0x290, 2, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA2__UART2_TXD        IOMUX_PAD(0x690, 0x290, 1, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA2__USBH1_DATA2      IOMUX_PAD(0x690, 0x290, 0, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA3__GPIO1_14         IOMUX_PAD(0x694, 0x294, 2, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA3__UART2_RTS        IOMUX_PAD(0x694, 0x294, 1, 0x09e8, 5, 0)
-#define _MX51_PAD_USBH1_DATA3__USBH1_DATA3      IOMUX_PAD(0x694, 0x294, 0, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA4__CSPI_SS0         IOMUX_PAD(0x698, 0x298, 1, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA4__GPIO1_15         IOMUX_PAD(0x698, 0x298, 2, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA4__USBH1_DATA4      IOMUX_PAD(0x698, 0x298, 0, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA5__CSPI_SS1         IOMUX_PAD(0x69c, 0x29c, 1, 0x0920, 0, 0)
-#define _MX51_PAD_USBH1_DATA5__GPIO1_16         IOMUX_PAD(0x69c, 0x29c, 2, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA5__USBH1_DATA5      IOMUX_PAD(0x69c, 0x29c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA6__CSPI_SS3         IOMUX_PAD(0x6a0, 0x2a0, 1, 0x0928, 1, 0)
-#define _MX51_PAD_USBH1_DATA6__GPIO1_17         IOMUX_PAD(0x6a0, 0x2a0, 2, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA6__USBH1_DATA6      IOMUX_PAD(0x6a0, 0x2a0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA7__ECSPI1_SS3       IOMUX_PAD(0x6a4, 0x2a4, 1, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA7__ECSPI2_SS3       IOMUX_PAD(0x6a4, 0x2a4, 5, 0x0934, 1, 0)
-#define _MX51_PAD_USBH1_DATA7__GPIO1_18         IOMUX_PAD(0x6a4, 0x2a4, 2, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA7__USBH1_DATA7      IOMUX_PAD(0x6a4, 0x2a4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DI1_PIN11__DI1_PIN11          IOMUX_PAD(0x6a8, 0x2a8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DI1_PIN11__ECSPI1_SS2         IOMUX_PAD(0x6a8, 0x2a8, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DI1_PIN11__GPIO3_0            IOMUX_PAD(0x6a8, 0x2a8, 4, 0x0000, 0, 0)
-#define _MX51_PAD_DI1_PIN12__DI1_PIN12          IOMUX_PAD(0x6ac, 0x2ac, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DI1_PIN12__GPIO3_1            IOMUX_PAD(0x6ac, 0x2ac, 4, 0x0978, 1, 0)
-#define _MX51_PAD_DI1_PIN13__DI1_PIN13          IOMUX_PAD(0x6b0, 0x2b0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DI1_PIN13__GPIO3_2            IOMUX_PAD(0x6b0, 0x2b0, 4, 0x097c, 1, 0)
-#define _MX51_PAD_DI1_D0_CS__DI1_D0_CS          IOMUX_PAD(0x6b4, 0x2b4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DI1_D0_CS__GPIO3_3            IOMUX_PAD(0x6b4, 0x2b4, 4, 0x0980, 1, 0)
-#define _MX51_PAD_DI1_D1_CS__DI1_D1_CS          IOMUX_PAD(0x6b8, 0x2b8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DI1_D1_CS__DISP1_PIN14        IOMUX_PAD(0x6b8, 0x2b8, 2, 0x0000, 0, 0)
-#define _MX51_PAD_DI1_D1_CS__DISP1_PIN5         IOMUX_PAD(0x6b8, 0x2b8, 3, 0x0000, 0, 0)
-#define _MX51_PAD_DI1_D1_CS__GPIO3_4            IOMUX_PAD(0x6b8, 0x2b8, 4, 0x0984, 1, 0)
-#define _MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1    IOMUX_PAD(0x6bc, 0x2bc, 2, 0x09a4, 1, 0)
-#define _MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN        IOMUX_PAD(0x6bc, 0x2bc, 0, 0x09c4, 0, 0)
-#define _MX51_PAD_DISPB2_SER_DIN__GPIO3_5       IOMUX_PAD(0x6bc, 0x2bc, 4, 0x0988, 1, 0)
-#define _MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6    IOMUX_PAD(0x6c0, 0x2c0, 3, 0x0000, 0, 0)
-#define _MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO        IOMUX_PAD(0x6c0, 0x2c0, 0, 0x09c4, 1, 0)
-#define _MX51_PAD_DISPB2_SER_DIO__GPIO3_6       IOMUX_PAD(0x6c0, 0x2c0, 4, 0x098c, 1, 0)
-#define _MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17   IOMUX_PAD(0x6c4, 0x2c4, 2, 0x0000, 0, 0)
-#define _MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7    IOMUX_PAD(0x6c4, 0x2c4, 3, 0x0000, 0, 0)
-#define _MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK        IOMUX_PAD(0x6c4, 0x2c4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISPB2_SER_CLK__GPIO3_7       IOMUX_PAD(0x6c4, 0x2c4, 4, 0x0990, 1, 0)
-#define _MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK  IOMUX_PAD(0x6c8, 0x2c8, 2, 0x0000, 0, 0)
-#define _MX51_PAD_DISPB2_SER_RS__DISP1_PIN16    IOMUX_PAD(0x6c8, 0x2c8, 2, 0x0000, 0, 0)
-#define _MX51_PAD_DISPB2_SER_RS__DISP1_PIN8     IOMUX_PAD(0x6c8, 0x2c8, 3, 0x0000, 0, 0)
-#define _MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS  IOMUX_PAD(0x6c8, 0x2c8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS  IOMUX_PAD(0x6c8, 0x2c8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISPB2_SER_RS__GPIO3_8        IOMUX_PAD(0x6c8, 0x2c8, 4, 0x0994, 1, 0)
-#define _MX51_PAD_DISP1_DAT0__DISP1_DAT0        IOMUX_PAD(0x6cc, 0x2cc, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT1__DISP1_DAT1        IOMUX_PAD(0x6d0, 0x2d0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT2__DISP1_DAT2        IOMUX_PAD(0x6d4, 0x2d4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT3__DISP1_DAT3        IOMUX_PAD(0x6d8, 0x2d8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT4__DISP1_DAT4        IOMUX_PAD(0x6dc, 0x2dc, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT5__DISP1_DAT5        IOMUX_PAD(0x6e0, 0x2e0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT6__BOOT_USB_SRC      IOMUX_PAD(0x6e4, 0x2e4, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT6__DISP1_DAT6        IOMUX_PAD(0x6e4, 0x2e4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG   IOMUX_PAD(0x6e8, 0x2e8, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT7__DISP1_DAT7        IOMUX_PAD(0x6e8, 0x2e8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT8__BOOT_SRC0         IOMUX_PAD(0x6ec, 0x2ec, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT8__DISP1_DAT8        IOMUX_PAD(0x6ec, 0x2ec, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT9__BOOT_SRC1         IOMUX_PAD(0x6f0, 0x2f0, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT9__DISP1_DAT9        IOMUX_PAD(0x6f0, 0x2f0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE  IOMUX_PAD(0x6f4, 0x2f4, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT10__DISP1_DAT10      IOMUX_PAD(0x6f4, 0x2f4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2   IOMUX_PAD(0x6f8, 0x2f8, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT11__DISP1_DAT11      IOMUX_PAD(0x6f8, 0x2f8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL     IOMUX_PAD(0x6fc, 0x2fc, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT12__DISP1_DAT12      IOMUX_PAD(0x6fc, 0x2fc, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0    IOMUX_PAD(0x700, 0x300, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT13__DISP1_DAT13      IOMUX_PAD(0x700, 0x300, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1    IOMUX_PAD(0x704, 0x304, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT14__DISP1_DAT14      IOMUX_PAD(0x704, 0x304, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH   IOMUX_PAD(0x708, 0x308, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT15__DISP1_DAT15      IOMUX_PAD(0x708, 0x308, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0  IOMUX_PAD(0x70c, 0x30c, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT16__DISP1_DAT16      IOMUX_PAD(0x70c, 0x30c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1  IOMUX_PAD(0x710, 0x310, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT17__DISP1_DAT17      IOMUX_PAD(0x710, 0x310, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 IOMUX_PAD(0x714, 0x314, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT18__DISP1_DAT18      IOMUX_PAD(0x714, 0x314, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT18__DISP2_PIN11      IOMUX_PAD(0x714, 0x314, 5, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT18__DISP2_PIN5       IOMUX_PAD(0x714, 0x314, 4, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 IOMUX_PAD(0x718, 0x318, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT19__DISP1_DAT19      IOMUX_PAD(0x718, 0x318, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT19__DISP2_PIN12      IOMUX_PAD(0x718, 0x318, 5, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT19__DISP2_PIN6       IOMUX_PAD(0x718, 0x318, 4, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0   IOMUX_PAD(0x71c, 0x31c, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT20__DISP1_DAT20      IOMUX_PAD(0x71c, 0x31c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT20__DISP2_PIN13      IOMUX_PAD(0x71c, 0x31c, 5, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT20__DISP2_PIN7       IOMUX_PAD(0x71c, 0x31c, 4, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1   IOMUX_PAD(0x720, 0x320, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT21__DISP1_DAT21      IOMUX_PAD(0x720, 0x320, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT21__DISP2_PIN14      IOMUX_PAD(0x720, 0x320, 5, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT21__DISP2_PIN8       IOMUX_PAD(0x720, 0x320, 4, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0   IOMUX_PAD(0x724, 0x324, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT22__DISP1_DAT22      IOMUX_PAD(0x724, 0x324, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT22__DISP2_D0_CS      IOMUX_PAD(0x724, 0x324, 6, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT22__DISP2_DAT16      IOMUX_PAD(0x724, 0x324, 5, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1   IOMUX_PAD(0x728, 0x328, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT23__DISP1_DAT23      IOMUX_PAD(0x728, 0x328, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT23__DISP2_D1_CS      IOMUX_PAD(0x728, 0x328, 6, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT23__DISP2_DAT17      IOMUX_PAD(0x728, 0x328, 5, 0x0000, 0, 0)
-#define _MX51_PAD_DISP1_DAT23__DISP2_SER_CS     IOMUX_PAD(0x728, 0x328, 4, 0x0000, 0, 0)
-#define _MX51_PAD_DI1_PIN3__DI1_PIN3            IOMUX_PAD(0x72c, 0x32c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DI1_PIN2__DI1_PIN2            IOMUX_PAD(0x734, 0x330, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DI_GP2__DISP1_SER_CLK         IOMUX_PAD(0x740, 0x338, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DI_GP2__DISP2_WAIT            IOMUX_PAD(0x740, 0x338, 2, 0x09a8, 1, 0)
-#define _MX51_PAD_DI_GP3__CSI1_DATA_EN          IOMUX_PAD(0x744, 0x33c, 3, 0x09a0, 1, 0)
-#define _MX51_PAD_DI_GP3__DISP1_SER_DIO         IOMUX_PAD(0x744, 0x33c, 0, 0x09c0, 0, 0)
-#define _MX51_PAD_DI_GP3__FEC_TX_ER             IOMUX_PAD(0x744, 0x33c, 2, 0x0000, 0, 0)
-#define _MX51_PAD_DI2_PIN4__CSI2_DATA_EN        IOMUX_PAD(0x748, 0x340, 3, 0x099c, 1, 0)
-#define _MX51_PAD_DI2_PIN4__DI2_PIN4            IOMUX_PAD(0x748, 0x340, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DI2_PIN4__FEC_CRS             IOMUX_PAD(0x748, 0x340, 2, 0x0950, 1, 0)
-#define _MX51_PAD_DI2_PIN2__DI2_PIN2            IOMUX_PAD(0x74c, 0x344, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DI2_PIN2__FEC_MDC             IOMUX_PAD(0x74c, 0x344, 2, 0x0000, 0, 0)
-#define _MX51_PAD_DI2_PIN3__DI2_PIN3            IOMUX_PAD(0x750, 0x348, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DI2_PIN3__FEC_MDIO            IOMUX_PAD(0x750, 0x348, 2, 0x0954, 1, 0)
-#define _MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK    IOMUX_PAD(0x754, 0x34c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DI2_DISP_CLK__FEC_RDATA1      IOMUX_PAD(0x754, 0x34c, 2, 0x095c, 1, 0)
-#define _MX51_PAD_DI_GP4__DI2_PIN15             IOMUX_PAD(0x758, 0x350, 4, 0x0000, 0, 0)
-#define _MX51_PAD_DI_GP4__DISP1_SER_DIN         IOMUX_PAD(0x758, 0x350, 0, 0x09c0, 1, 0)
-#define _MX51_PAD_DI_GP4__DISP2_PIN1            IOMUX_PAD(0x758, 0x350, 3, 0x0000, 0, 0)
-#define _MX51_PAD_DI_GP4__FEC_RDATA2            IOMUX_PAD(0x758, 0x350, 2, 0x0960, 1, 0)
-#define _MX51_PAD_DISP2_DAT0__DISP2_DAT0        IOMUX_PAD(0x75c, 0x354, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT0__FEC_RDATA3        IOMUX_PAD(0x75c, 0x354, 2, 0x0964, 1, 0)
-#define _MX51_PAD_DISP2_DAT0__KEY_COL6          IOMUX_PAD(0x75c, 0x354, 4, 0x09c8, 1, 0)
-#define _MX51_PAD_DISP2_DAT0__UART3_RXD         IOMUX_PAD(0x75c, 0x354, 5, 0x09f4, 8, 0)
-#define _MX51_PAD_DISP2_DAT0__USBH3_CLK         IOMUX_PAD(0x75c, 0x354, 3, 0x09f8, 1, 0)
-#define _MX51_PAD_DISP2_DAT1__DISP2_DAT1        IOMUX_PAD(0x760, 0x358, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT1__FEC_RX_ER         IOMUX_PAD(0x760, 0x358, 2, 0x0970, 1, 0)
-#define _MX51_PAD_DISP2_DAT1__KEY_COL7          IOMUX_PAD(0x760, 0x358, 4, 0x09cc, 1, 0)
-#define _MX51_PAD_DISP2_DAT1__UART3_TXD         IOMUX_PAD(0x760, 0x358, 5, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT1__USBH3_DIR         IOMUX_PAD(0x760, 0x358, 3, 0x0a1c, 1, 0)
-#define _MX51_PAD_DISP2_DAT2__DISP2_DAT2        IOMUX_PAD(0x764, 0x35c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT3__DISP2_DAT3        IOMUX_PAD(0x768, 0x360, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT4__DISP2_DAT4        IOMUX_PAD(0x76c, 0x364, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT5__DISP2_DAT5        IOMUX_PAD(0x770, 0x368, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT6__DISP2_DAT6        IOMUX_PAD(0x774, 0x36c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT6__FEC_TDATA1        IOMUX_PAD(0x774, 0x36c, 2, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT6__GPIO1_19          IOMUX_PAD(0x774, 0x36c, 5, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT6__KEY_ROW4          IOMUX_PAD(0x774, 0x36c, 4, 0x09d0, 1, 0)
-#define _MX51_PAD_DISP2_DAT6__USBH3_STP         IOMUX_PAD(0x774, 0x36c, 3, 0x0a24, 1, 0)
-#define _MX51_PAD_DISP2_DAT7__DISP2_DAT7        IOMUX_PAD(0x778, 0x370, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT7__FEC_TDATA2        IOMUX_PAD(0x778, 0x370, 2, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT7__GPIO1_29          IOMUX_PAD(0x778, 0x370, 5, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT7__KEY_ROW5          IOMUX_PAD(0x778, 0x370, 4, 0x09d4, 1, 0)
-#define _MX51_PAD_DISP2_DAT7__USBH3_NXT         IOMUX_PAD(0x778, 0x370, 3, 0x0a20, 1, 0)
-#define _MX51_PAD_DISP2_DAT8__DISP2_DAT8        IOMUX_PAD(0x77c, 0x374, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT8__FEC_TDATA3        IOMUX_PAD(0x77c, 0x374, 2, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT8__GPIO1_30          IOMUX_PAD(0x77c, 0x374, 5, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT8__KEY_ROW6          IOMUX_PAD(0x77c, 0x374, 4, 0x09d8, 1, 0)
-#define _MX51_PAD_DISP2_DAT8__USBH3_DATA0       IOMUX_PAD(0x77c, 0x374, 3, 0x09fc, 1, 0)
-#define _MX51_PAD_DISP2_DAT9__AUD6_RXC          IOMUX_PAD(0x780, 0x378, 4, 0x08f4, 1, 0)
-#define _MX51_PAD_DISP2_DAT9__DISP2_DAT9        IOMUX_PAD(0x780, 0x378, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT9__FEC_TX_EN         IOMUX_PAD(0x780, 0x378, 2, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT9__GPIO1_31          IOMUX_PAD(0x780, 0x378, 5, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT9__USBH3_DATA1       IOMUX_PAD(0x780, 0x378, 3, 0x0a00, 1, 0)
-#define _MX51_PAD_DISP2_DAT10__DISP2_DAT10      IOMUX_PAD(0x784, 0x37c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT10__DISP2_SER_CS     IOMUX_PAD(0x784, 0x37c, 5, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT10__FEC_COL          IOMUX_PAD(0x784, 0x37c, 2, 0x094c, 1, 0)
-#define _MX51_PAD_DISP2_DAT10__KEY_ROW7         IOMUX_PAD(0x784, 0x37c, 4, 0x09dc, 1, 0)
-#define _MX51_PAD_DISP2_DAT10__USBH3_DATA2      IOMUX_PAD(0x784, 0x37c, 3, 0x0a04, 1, 0)
-#define _MX51_PAD_DISP2_DAT11__AUD6_TXD         IOMUX_PAD(0x788, 0x380, 4, 0x08f0, 1, 0)
-#define _MX51_PAD_DISP2_DAT11__DISP2_DAT11      IOMUX_PAD(0x788, 0x380, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT11__FEC_RX_CLK       IOMUX_PAD(0x788, 0x380, 2, 0x0968, 1, 0)
-#define _MX51_PAD_DISP2_DAT11__GPIO1_10         IOMUX_PAD(0x788, 0x380, 7, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT11__USBH3_DATA3      IOMUX_PAD(0x788, 0x380, 3, 0x0a08, 1, 0)
-#define _MX51_PAD_DISP2_DAT12__AUD6_RXD         IOMUX_PAD(0x78c, 0x384, 4, 0x08ec, 1, 0)
-#define _MX51_PAD_DISP2_DAT12__DISP2_DAT12      IOMUX_PAD(0x78c, 0x384, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT12__FEC_RX_DV        IOMUX_PAD(0x78c, 0x384, 2, 0x096c, 1, 0)
-#define _MX51_PAD_DISP2_DAT12__USBH3_DATA4      IOMUX_PAD(0x78c, 0x384, 3, 0x0a0c, 1, 0)
-#define _MX51_PAD_DISP2_DAT13__AUD6_TXC         IOMUX_PAD(0x790, 0x388, 4, 0x08fc, 1, 0)
-#define _MX51_PAD_DISP2_DAT13__DISP2_DAT13      IOMUX_PAD(0x790, 0x388, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT13__FEC_TX_CLK       IOMUX_PAD(0x790, 0x388, 2, 0x0974, 1, 0)
-#define _MX51_PAD_DISP2_DAT13__USBH3_DATA5      IOMUX_PAD(0x790, 0x388, 3, 0x0a10, 1, 0)
-#define _MX51_PAD_DISP2_DAT14__AUD6_TXFS        IOMUX_PAD(0x794, 0x38c, 4, 0x0900, 1, 0)
-#define _MX51_PAD_DISP2_DAT14__DISP2_DAT14      IOMUX_PAD(0x794, 0x38c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT14__FEC_RDATA0       IOMUX_PAD(0x794, 0x38c, 2, 0x0958, 1, 0)
-#define _MX51_PAD_DISP2_DAT14__USBH3_DATA6      IOMUX_PAD(0x794, 0x38c, 3, 0x0a14, 1, 0)
-#define _MX51_PAD_DISP2_DAT15__AUD6_RXFS        IOMUX_PAD(0x798, 0x390, 4, 0x08f8, 1, 0)
-#define _MX51_PAD_DISP2_DAT15__DISP1_SER_CS     IOMUX_PAD(0x798, 0x390, 5, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT15__DISP2_DAT15      IOMUX_PAD(0x798, 0x390, 0, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT15__FEC_TDATA0       IOMUX_PAD(0x798, 0x390, 2, 0x0000, 0, 0)
-#define _MX51_PAD_DISP2_DAT15__USBH3_DATA7      IOMUX_PAD(0x798, 0x390, 3, 0x0a18, 1, 0)
-#define _MX51_PAD_SD1_CMD__AUD5_RXFS            IOMUX_PAD(0x79c, 0x394, 1, 0x08e0, 1, 0)
-#define _MX51_PAD_SD1_CMD__CSPI_MOSI            IOMUX_PAD(0x79c, 0x394, 2, 0x091c, 2, 0)
-#define _MX51_PAD_SD1_CMD__SD1_CMD              IOMUX_PAD(0x79c, 0x394, 0x10, 0x0000, 0, 0)
-#define _MX51_PAD_SD1_CLK__AUD5_RXC             IOMUX_PAD(0x7a0, 0x398, 1, 0x08dc, 1, 0)
-#define _MX51_PAD_SD1_CLK__CSPI_SCLK            IOMUX_PAD(0x7a0, 0x398, 2, 0x0914, 2, 0)
-#define _MX51_PAD_SD1_CLK__SD1_CLK              IOMUX_PAD(0x7a0, 0x398, 0x10, 0x0000, 0, 0)
-#define _MX51_PAD_SD1_DATA0__AUD5_TXD           IOMUX_PAD(0x7a4, 0x39c, 1, 0x08d8, 2, 0)
-#define _MX51_PAD_SD1_DATA0__CSPI_MISO          IOMUX_PAD(0x7a4, 0x39c, 2, 0x0918, 1, 0)
-#define _MX51_PAD_SD1_DATA0__SD1_DATA0          IOMUX_PAD(0x7a4, 0x39c, 0x10, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DA0__EIM_DA0              IOMUX_PAD(0x000, 0x01c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DA1__EIM_DA1              IOMUX_PAD(0x000, 0x020, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DA2__EIM_DA2              IOMUX_PAD(0x000, 0x024, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DA3__EIM_DA3              IOMUX_PAD(0x000, 0x028, 0, 0x0000, 0, 0)
-#define _MX51_PAD_SD1_DATA1__AUD5_RXD           IOMUX_PAD(0x7a8, 0x3a0, 1, 0x08d4, 2, 0)
-#define _MX51_PAD_SD1_DATA1__SD1_DATA1          IOMUX_PAD(0x7a8, 0x3a0, 0x10, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DA4__EIM_DA4              IOMUX_PAD(0x000, 0x02c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DA5__EIM_DA5              IOMUX_PAD(0x000, 0x030, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DA6__EIM_DA6              IOMUX_PAD(0x000, 0x034, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DA7__EIM_DA7              IOMUX_PAD(0x000, 0x038, 0, 0x0000, 0, 0)
-#define _MX51_PAD_SD1_DATA2__AUD5_TXC           IOMUX_PAD(0x7ac, 0x3a4, 1, 0x08e4, 2, 0)
-#define _MX51_PAD_SD1_DATA2__SD1_DATA2          IOMUX_PAD(0x7ac, 0x3a4, 0x10, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DA10__EIM_DA10            IOMUX_PAD(0x000, 0x044, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DA11__EIM_DA11            IOMUX_PAD(0x000, 0x048, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DA8__EIM_DA8              IOMUX_PAD(0x000, 0x03c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DA9__EIM_DA9              IOMUX_PAD(0x000, 0x040, 0, 0x0000, 0, 0)
-#define _MX51_PAD_SD1_DATA3__AUD5_TXFS          IOMUX_PAD(0x7b0, 0x3a8, 1, 0x08e8, 2, 0)
-#define _MX51_PAD_SD1_DATA3__CSPI_SS1           IOMUX_PAD(0x7b0, 0x3a8, 2, 0x0920, 1, 0)
-#define _MX51_PAD_SD1_DATA3__SD1_DATA3          IOMUX_PAD(0x7b0, 0x3a8, 0x10, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_0__CSPI_SS2             IOMUX_PAD(0x7b4, 0x3ac, 2, 0x0924, 0, 0)
-#define _MX51_PAD_GPIO1_0__GPIO1_0              IOMUX_PAD(0x7b4, 0x3ac, 1, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_0__SD1_CD               IOMUX_PAD(0x7b4, 0x3ac, 0, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_1__CSPI_MISO            IOMUX_PAD(0x7b8, 0x3b0, 2, 0x0918, 2, 0)
-#define _MX51_PAD_GPIO1_1__GPIO1_1              IOMUX_PAD(0x7b8, 0x3b0, 1, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_1__SD1_WP               IOMUX_PAD(0x7b8, 0x3b0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DA12__EIM_DA12            IOMUX_PAD(0x000, 0x04c, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DA13__EIM_DA13            IOMUX_PAD(0x000, 0x050, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DA14__EIM_DA14            IOMUX_PAD(0x000, 0x054, 0, 0x0000, 0, 0)
-#define _MX51_PAD_EIM_DA15__EIM_DA15            IOMUX_PAD(0x000, 0x058, 0, 0x0000, 0, 0)
-#define _MX51_PAD_SD2_CMD__CSPI_MOSI            IOMUX_PAD(0x000, 0x3b4, 2, 0x091c, 3, 0)
-#define _MX51_PAD_SD2_CMD__I2C1_SCL             IOMUX_PAD(0x7bc, 0x3b4, 0x11, 0x09b0, 2, 0)
-#define _MX51_PAD_SD2_CMD__SD2_CMD              IOMUX_PAD(0x7bc, 0x3b4, 0x10, 0x0000, 0, 0)
-#define _MX51_PAD_SD2_CLK__CSPI_SCLK            IOMUX_PAD(0x7c0, 0x3b8, 2, 0x0914, 3, 0)
-#define _MX51_PAD_SD2_CLK__I2C1_SDA             IOMUX_PAD(0x7c0, 0x3b8, 0x11, 0x09b4, 2, 0)
-#define _MX51_PAD_SD2_CLK__SD2_CLK              IOMUX_PAD(0x7c0, 0x3b8, 0x10, 0x0000, 0, 0)
-#define _MX51_PAD_SD2_DATA0__CSPI_MISO          IOMUX_PAD(0x7c4, 0x3bc, 2, 0x0918, 3, 0)
-#define _MX51_PAD_SD2_DATA0__SD1_DAT4           IOMUX_PAD(0x7c4, 0x3bc, 1, 0x0000, 0, 0)
-#define _MX51_PAD_SD2_DATA0__SD2_DATA0          IOMUX_PAD(0x7c4, 0x3bc, 0x10, 0x0000, 0, 0)
-#define _MX51_PAD_SD2_DATA1__SD1_DAT5           IOMUX_PAD(0x7c8, 0x3c0, 1, 0x0000, 0, 0)
-#define _MX51_PAD_SD2_DATA1__SD2_DATA1          IOMUX_PAD(0x7c8, 0x3c0, 0x10, 0x0000, 0, 0)
-#define _MX51_PAD_SD2_DATA1__USBH3_H2_DP        IOMUX_PAD(0x7c8, 0x3c0, 2, 0x0000, 0, 0)
-#define _MX51_PAD_SD2_DATA2__SD1_DAT6           IOMUX_PAD(0x7cc, 0x3c4, 1, 0x0000, 0, 0)
-#define _MX51_PAD_SD2_DATA2__SD2_DATA2          IOMUX_PAD(0x7cc, 0x3c4, 0x10, 0x0000, 0, 0)
-#define _MX51_PAD_SD2_DATA2__USBH3_H2_DM        IOMUX_PAD(0x7cc, 0x3c4, 2, 0x0000, 0, 0)
-#define _MX51_PAD_SD2_DATA3__CSPI_SS2           IOMUX_PAD(0x7d0, 0x3c8, 2, 0x0924, 1, 0)
-#define _MX51_PAD_SD2_DATA3__SD1_DAT7           IOMUX_PAD(0x7d0, 0x3c8, 1, 0x0000, 0, 0)
-#define _MX51_PAD_SD2_DATA3__SD2_DATA3          IOMUX_PAD(0x7d0, 0x3c8, 0x10, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_2__CCM_OUT_2            IOMUX_PAD(0x7d4, 0x3cc, 5, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_2__GPIO1_2              IOMUX_PAD(0x7d4, 0x3cc, 0, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_2__I2C2_SCL             IOMUX_PAD(0x7d4, 0x3cc, 0x12, 0x09b8, 3, 0)
-#define _MX51_PAD_GPIO1_2__PLL1_BYP             IOMUX_PAD(0x7d4, 0x3cc, 7, 0x090c, 1, 0)
-#define _MX51_PAD_GPIO1_2__PWM1_PWMO            IOMUX_PAD(0x7d4, 0x3cc, 1, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_3__GPIO1_3              IOMUX_PAD(0x7d8, 0x3d0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_3__I2C2_SDA             IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x09bc, 3, 0)
-#define _MX51_PAD_GPIO1_3__PLL2_BYP             IOMUX_PAD(0x7d8, 0x3d0, 7, 0x0910, 1, 0)
-#define _MX51_PAD_GPIO1_3__PWM2_PWMO            IOMUX_PAD(0x7d8, 0x3d0, 1, 0x0000, 0, 0)
-#define _MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ    IOMUX_PAD(0x7fc, 0x3d4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B  IOMUX_PAD(0x7fc, 0x3d4, 1, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_4__DISP2_EXT_CLK        IOMUX_PAD(0x804, 0x3d8, 4, 0x0908, 1, 0)
-#define _MX51_PAD_GPIO1_4__EIM_RDY              IOMUX_PAD(0x804, 0x3d8, 3, 0x0938, 1, 0)
-#define _MX51_PAD_GPIO1_4__GPIO1_4              IOMUX_PAD(0x804, 0x3d8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_4__WDOG1_WDOG_B         IOMUX_PAD(0x804, 0x3d8, 2, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_5__CSI2_MCLK            IOMUX_PAD(0x808, 0x3dc, 6, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_5__DISP2_PIN16          IOMUX_PAD(0x808, 0x3dc, 3, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_5__GPIO1_5              IOMUX_PAD(0x808, 0x3dc, 0, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_5__WDOG2_WDOG_B         IOMUX_PAD(0x808, 0x3dc, 2, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_6__DISP2_PIN17          IOMUX_PAD(0x80c, 0x3e0, 4, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_6__GPIO1_6              IOMUX_PAD(0x80c, 0x3e0, 0, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_6__REF_EN_B             IOMUX_PAD(0x80c, 0x3e0, 3, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_7__CCM_OUT_0            IOMUX_PAD(0x810, 0x3e4, 3, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_7__GPIO1_7              IOMUX_PAD(0x810, 0x3e4, 0, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_7__SD2_WP               IOMUX_PAD(0x810, 0x3e4, 6, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_7__SPDIF_OUT1           IOMUX_PAD(0x810, 0x3e4, 2, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_8__CSI2_DATA_EN         IOMUX_PAD(0x814, 0x3e8, 2, 0x099c, 2, 0)
-#define _MX51_PAD_GPIO1_8__GPIO1_8              IOMUX_PAD(0x814, 0x3e8, 0, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_8__SD2_CD               IOMUX_PAD(0x814, 0x3e8, 6, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_8__USBH3_PWR            IOMUX_PAD(0x814, 0x3e8, 1, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_9__CCM_OUT_1            IOMUX_PAD(0x818, 0x3ec, 3, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_9__DISP2_D1_CS          IOMUX_PAD(0x818, 0x3ec, 2, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_9__DISP2_SER_CS         IOMUX_PAD(0x818, 0x3ec, 7, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_9__GPIO1_9              IOMUX_PAD(0x818, 0x3ec, 0, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_9__SD2_LCTL             IOMUX_PAD(0x818, 0x3ec, 6, 0x0000, 0, 0)
-#define _MX51_PAD_GPIO1_9__USBH3_OC             IOMUX_PAD(0x818, 0x3ec, 1, 0x0000, 0, 0)
 /* The same pins as above but with the default pad control values applied */
-#define MX51_PAD_EIM_D16__AUD4_RXFS             (_MX51_PAD_EIM_D16__AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D16__AUD4_RXFS             IOMUX_PAD(0x3f0, 0x05c, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D16__AUD5_TXD              (_MX51_PAD_EIM_D16__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D16__AUD5_TXD              IOMUX_PAD(0x3f0, 0x05c, 7, 0x8d8, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D16__EIM_D16               (_MX51_PAD_EIM_D16__EIM_D16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D16__EIM_D16               IOMUX_PAD(0x3f0, 0x05c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D16__GPIO2_0               (_MX51_PAD_EIM_D16__GPIO2_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_D16__GPIO2_0               IOMUX_PAD(0x3f0, 0x05c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D16__I2C1_SDA              (_MX51_PAD_EIM_D16__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
+#define MX51_PAD_EIM_D16__I2C1_SDA              IOMUX_PAD(0x3f0, 0x05c, 0x14, 0x9b4, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_EIM_D16__UART2_CTS             (_MX51_PAD_EIM_D16__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_EIM_D16__UART2_CTS             IOMUX_PAD(0x3f0, 0x05c, 3, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D16__USBH2_DATA0           (_MX51_PAD_EIM_D16__USBH2_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D16__USBH2_DATA0           IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D17__AUD5_RXD              (_MX51_PAD_EIM_D17__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D17__AUD5_RXD              IOMUX_PAD(0x3f4, 0x060, 7, 0x8d4, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D17__EIM_D17               (_MX51_PAD_EIM_D17__EIM_D17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D17__EIM_D17               IOMUX_PAD(0x3f4, 0x060, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D17__GPIO2_1               (_MX51_PAD_EIM_D17__GPIO2_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_D17__GPIO2_1               IOMUX_PAD(0x3f4, 0x060, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D17__UART2_RXD             (_MX51_PAD_EIM_D17__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_EIM_D17__UART2_RXD             IOMUX_PAD(0x3f4, 0x060, 3, 0x9ec, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D17__UART3_CTS             (_MX51_PAD_EIM_D17__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_EIM_D17__UART3_CTS             IOMUX_PAD(0x3f4, 0x060, 4, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D17__USBH2_DATA1           (_MX51_PAD_EIM_D17__USBH2_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D17__USBH2_DATA1           IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D18__AUD5_TXC              (_MX51_PAD_EIM_D18__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D18__AUD5_TXC              IOMUX_PAD(0x3f8, 0x064, 7, 0x8e4, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D18__EIM_D18               (_MX51_PAD_EIM_D18__EIM_D18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D18__EIM_D18               IOMUX_PAD(0x3f8, 0x064, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D18__GPIO2_2               (_MX51_PAD_EIM_D18__GPIO2_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_D18__GPIO2_2               IOMUX_PAD(0x3f8, 0x064, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D18__UART2_TXD             (_MX51_PAD_EIM_D18__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_EIM_D18__UART2_TXD             IOMUX_PAD(0x3f8, 0x064, 3, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D18__UART3_RTS             (_MX51_PAD_EIM_D18__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_EIM_D18__UART3_RTS             IOMUX_PAD(0x3f8, 0x064, 4, 0x9f0, 1, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D18__USBH2_DATA2           (_MX51_PAD_EIM_D18__USBH2_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D18__USBH2_DATA2           IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D19__AUD4_RXC              (_MX51_PAD_EIM_D19__AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D19__AUD4_RXC              IOMUX_PAD(0x3fc, 0x068, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D19__AUD5_TXFS             (_MX51_PAD_EIM_D19__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D19__AUD5_TXFS             IOMUX_PAD(0x3fc, 0x068, 7, 0x8e8, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D19__EIM_D19               (_MX51_PAD_EIM_D19__EIM_D19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D19__EIM_D19               IOMUX_PAD(0x3fc, 0x068, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D19__GPIO2_3               (_MX51_PAD_EIM_D19__GPIO2_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_D19__GPIO2_3               IOMUX_PAD(0x3fc, 0x068, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D19__I2C1_SCL              (_MX51_PAD_EIM_D19__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
+#define MX51_PAD_EIM_D19__I2C1_SCL              IOMUX_PAD(0x3fc, 0x068, 0x14, 0x9b0, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_EIM_D19__UART2_RTS             (_MX51_PAD_EIM_D19__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_EIM_D19__UART2_RTS             IOMUX_PAD(0x3fc, 0x068, 3, 0x9e8, 1, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D19__USBH2_DATA3           (_MX51_PAD_EIM_D19__USBH2_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D19__USBH2_DATA3           IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D20__AUD4_TXD              (_MX51_PAD_EIM_D20__AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D20__AUD4_TXD              IOMUX_PAD(0x400, 0x06c, 5, 0x8c8, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D20__EIM_D20               (_MX51_PAD_EIM_D20__EIM_D20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D20__EIM_D20               IOMUX_PAD(0x400, 0x06c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D20__GPIO2_4               (_MX51_PAD_EIM_D20__GPIO2_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_D20__GPIO2_4               IOMUX_PAD(0x400, 0x06c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB        (_MX51_PAD_EIM_D20__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB        IOMUX_PAD(0x400, 0x06c, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D20__USBH2_DATA4           (_MX51_PAD_EIM_D20__USBH2_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D20__USBH2_DATA4           IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__AUD4_RXD              (_MX51_PAD_EIM_D21__AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D21__AUD4_RXD              IOMUX_PAD(0x404, 0x070, 5, 0x8c4, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__EIM_D21               (_MX51_PAD_EIM_D21__EIM_D21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D21__EIM_D21               IOMUX_PAD(0x404, 0x070, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__GPIO2_5               (_MX51_PAD_EIM_D21__GPIO2_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_D21__GPIO2_5               IOMUX_PAD(0x404, 0x070, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB        (_MX51_PAD_EIM_D21__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB        IOMUX_PAD(0x404, 0x070, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__USBH2_DATA5           (_MX51_PAD_EIM_D21__USBH2_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D21__USBH2_DATA5           IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D22__AUD4_TXC              (_MX51_PAD_EIM_D22__AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D22__AUD4_TXC              IOMUX_PAD(0x408, 0x074, 5, 0x8cc, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D22__EIM_D22               (_MX51_PAD_EIM_D22__EIM_D22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D22__EIM_D22               IOMUX_PAD(0x408, 0x074, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D22__GPIO2_6               (_MX51_PAD_EIM_D22__GPIO2_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_D22__GPIO2_6               IOMUX_PAD(0x408, 0x074, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D22__USBH2_DATA6           (_MX51_PAD_EIM_D22__USBH2_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D22__USBH2_DATA6           IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D23__AUD4_TXFS             (_MX51_PAD_EIM_D23__AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D23__AUD4_TXFS             IOMUX_PAD(0x40c, 0x078, 5, 0x8d0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D23__EIM_D23               (_MX51_PAD_EIM_D23__EIM_D23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D23__EIM_D23               IOMUX_PAD(0x40c, 0x078, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D23__GPIO2_7               (_MX51_PAD_EIM_D23__GPIO2_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_D23__GPIO2_7               IOMUX_PAD(0x40c, 0x078, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D23__SPDIF_OUT1            (_MX51_PAD_EIM_D23__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D23__SPDIF_OUT1            IOMUX_PAD(0x40c, 0x078, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D23__USBH2_DATA7           (_MX51_PAD_EIM_D23__USBH2_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D23__USBH2_DATA7           IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D24__AUD6_RXFS             (_MX51_PAD_EIM_D24__AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D24__AUD6_RXFS             IOMUX_PAD(0x410, 0x07c, 5, 0x8f8, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D24__EIM_D24               (_MX51_PAD_EIM_D24__EIM_D24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D24__EIM_D24               IOMUX_PAD(0x410, 0x07c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D24__GPIO2_8               (_MX51_PAD_EIM_D24__GPIO2_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_D24__GPIO2_8               IOMUX_PAD(0x410, 0x07c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D24__I2C2_SDA              (_MX51_PAD_EIM_D24__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
+#define MX51_PAD_EIM_D24__I2C2_SDA              IOMUX_PAD(0x410, 0x07c, 0x14, 0x9bc, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_EIM_D24__UART3_CTS             (_MX51_PAD_EIM_D24__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_EIM_D24__UART3_CTS             IOMUX_PAD(0x410, 0x07c, 3, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D24__USBOTG_DATA0          (_MX51_PAD_EIM_D24__USBOTG_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D24__USBOTG_DATA0          IOMUX_PAD(0x410, 0x07c, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D25__EIM_D25               (_MX51_PAD_EIM_D25__EIM_D25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D25__EIM_D25               IOMUX_PAD(0x414, 0x080, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D25__KEY_COL6              (_MX51_PAD_EIM_D25__KEY_COL6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D25__KEY_COL6              IOMUX_PAD(0x414, 0x080, 1, 0x9c8, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D25__UART2_CTS             (_MX51_PAD_EIM_D25__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_EIM_D25__UART2_CTS             IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D25__UART3_RXD             (_MX51_PAD_EIM_D25__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_EIM_D25__UART3_RXD             IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D25__USBOTG_DATA1          (_MX51_PAD_EIM_D25__USBOTG_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D25__USBOTG_DATA1          IOMUX_PAD(0x414, 0x080, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D26__EIM_D26               (_MX51_PAD_EIM_D26__EIM_D26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D26__EIM_D26               IOMUX_PAD(0x418, 0x084, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D26__KEY_COL7              (_MX51_PAD_EIM_D26__KEY_COL7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D26__KEY_COL7              IOMUX_PAD(0x418, 0x084, 1, 0x9cc, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D26__UART2_RTS             (_MX51_PAD_EIM_D26__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_EIM_D26__UART2_RTS             IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D26__UART3_TXD             (_MX51_PAD_EIM_D26__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_EIM_D26__UART3_TXD             IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D26__USBOTG_DATA2          (_MX51_PAD_EIM_D26__USBOTG_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D26__USBOTG_DATA2          IOMUX_PAD(0x418, 0x084, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D27__AUD6_RXC              (_MX51_PAD_EIM_D27__AUD6_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D27__AUD6_RXC              IOMUX_PAD(0x41c, 0x088, 5, 0x8f4, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D27__EIM_D27               (_MX51_PAD_EIM_D27__EIM_D27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D27__EIM_D27               IOMUX_PAD(0x41c, 0x088, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D27__GPIO2_9               (_MX51_PAD_EIM_D27__GPIO2_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_D27__GPIO2_9               IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D27__I2C2_SCL              (_MX51_PAD_EIM_D27__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
+#define MX51_PAD_EIM_D27__I2C2_SCL              IOMUX_PAD(0x41c, 0x088, 0x14, 0x9b8, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_EIM_D27__UART3_RTS             (_MX51_PAD_EIM_D27__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_EIM_D27__UART3_RTS             IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D27__USBOTG_DATA3          (_MX51_PAD_EIM_D27__USBOTG_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D27__USBOTG_DATA3          IOMUX_PAD(0x41c, 0x088, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D28__AUD6_TXD              (_MX51_PAD_EIM_D28__AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D28__AUD6_TXD              IOMUX_PAD(0x420, 0x08c, 5, 0x8f0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D28__EIM_D28               (_MX51_PAD_EIM_D28__EIM_D28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D28__EIM_D28               IOMUX_PAD(0x420, 0x08c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D28__KEY_ROW4              (_MX51_PAD_EIM_D28__KEY_ROW4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D28__KEY_ROW4              IOMUX_PAD(0x420, 0x08c, 1, 0x9d0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D28__USBOTG_DATA4          (_MX51_PAD_EIM_D28__USBOTG_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D28__USBOTG_DATA4          IOMUX_PAD(0x420, 0x08c, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D29__AUD6_RXD              (_MX51_PAD_EIM_D29__AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D29__AUD6_RXD              IOMUX_PAD(0x424, 0x090, 5, 0x8ec, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D29__EIM_D29               (_MX51_PAD_EIM_D29__EIM_D29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D29__EIM_D29               IOMUX_PAD(0x424, 0x090, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D29__KEY_ROW5              (_MX51_PAD_EIM_D29__KEY_ROW5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D29__KEY_ROW5              IOMUX_PAD(0x424, 0x090, 1, 0x9d4, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D29__USBOTG_DATA5          (_MX51_PAD_EIM_D29__USBOTG_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D29__USBOTG_DATA5          IOMUX_PAD(0x424, 0x090, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D30__AUD6_TXC              (_MX51_PAD_EIM_D30__AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D30__AUD6_TXC              IOMUX_PAD(0x428, 0x094, 5, 0x8fc, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D30__EIM_D30               (_MX51_PAD_EIM_D30__EIM_D30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D30__EIM_D30               IOMUX_PAD(0x428, 0x094, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D30__KEY_ROW6              (_MX51_PAD_EIM_D30__KEY_ROW6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D30__KEY_ROW6              IOMUX_PAD(0x428, 0x094, 1, 0x9d8, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D30__USBOTG_DATA6          (_MX51_PAD_EIM_D30__USBOTG_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D30__USBOTG_DATA6          IOMUX_PAD(0x428, 0x094, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D31__AUD6_TXFS             (_MX51_PAD_EIM_D31__AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D31__AUD6_TXFS             IOMUX_PAD(0x42c, 0x098, 5, 0x900, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D31__EIM_D31               (_MX51_PAD_EIM_D31__EIM_D31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D31__EIM_D31               IOMUX_PAD(0x42c, 0x098, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D31__KEY_ROW7              (_MX51_PAD_EIM_D31__KEY_ROW7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D31__KEY_ROW7              IOMUX_PAD(0x42c, 0x098, 1, 0x9dc, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D31__USBOTG_DATA7          (_MX51_PAD_EIM_D31__USBOTG_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D31__USBOTG_DATA7          IOMUX_PAD(0x42c, 0x098, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A16__EIM_A16               (_MX51_PAD_EIM_A16__EIM_A16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A16__EIM_A16               IOMUX_PAD(0x430, 0x09c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A16__GPIO2_10              (_MX51_PAD_EIM_A16__GPIO2_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_A16__GPIO2_10              IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0         (_MX51_PAD_EIM_A16__OSC_FREQ_SEL0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0         IOMUX_PAD(0x430, 0x09c, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A17__EIM_A17               (_MX51_PAD_EIM_A17__EIM_A17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A17__EIM_A17               IOMUX_PAD(0x434, 0x0a0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A17__GPIO2_11              (_MX51_PAD_EIM_A17__GPIO2_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_A17__GPIO2_11              IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1         (_MX51_PAD_EIM_A17__OSC_FREQ_SEL1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1         IOMUX_PAD(0x434, 0x0a0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A18__BOOT_LPB0             (_MX51_PAD_EIM_A18__BOOT_LPB0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A18__BOOT_LPB0             IOMUX_PAD(0x438, 0x0a4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A18__EIM_A18               (_MX51_PAD_EIM_A18__EIM_A18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A18__EIM_A18               IOMUX_PAD(0x438, 0x0a4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A18__GPIO2_12              (_MX51_PAD_EIM_A18__GPIO2_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_A18__GPIO2_12              IOMUX_PAD(0x438, 0x0a4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A19__BOOT_LPB1             (_MX51_PAD_EIM_A19__BOOT_LPB1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A19__BOOT_LPB1             IOMUX_PAD(0x43c, 0x0a8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A19__EIM_A19               (_MX51_PAD_EIM_A19__EIM_A19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A19__EIM_A19               IOMUX_PAD(0x43c, 0x0a8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A19__GPIO2_13              (_MX51_PAD_EIM_A19__GPIO2_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_A19__GPIO2_13              IOMUX_PAD(0x43c, 0x0a8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A20__BOOT_UART_SRC0        (_MX51_PAD_EIM_A20__BOOT_UART_SRC0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A20__BOOT_UART_SRC0        IOMUX_PAD(0x440, 0x0ac, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A20__EIM_A20               (_MX51_PAD_EIM_A20__EIM_A20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A20__EIM_A20               IOMUX_PAD(0x440, 0x0ac, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A20__GPIO2_14              (_MX51_PAD_EIM_A20__GPIO2_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_A20__GPIO2_14              IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A21__BOOT_UART_SRC1        (_MX51_PAD_EIM_A21__BOOT_UART_SRC1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A21__BOOT_UART_SRC1        IOMUX_PAD(0x444, 0x0b0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A21__EIM_A21               (_MX51_PAD_EIM_A21__EIM_A21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A21__EIM_A21               IOMUX_PAD(0x444, 0x0b0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A21__GPIO2_15              (_MX51_PAD_EIM_A21__GPIO2_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_A21__GPIO2_15              IOMUX_PAD(0x444, 0x0b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A22__EIM_A22               (_MX51_PAD_EIM_A22__EIM_A22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A22__EIM_A22               IOMUX_PAD(0x448, 0x0b4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A22__GPIO2_16              (_MX51_PAD_EIM_A22__GPIO2_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_A22__GPIO2_16              IOMUX_PAD(0x448, 0x0b4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A23__BOOT_HPN_EN           (_MX51_PAD_EIM_A23__BOOT_HPN_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A23__BOOT_HPN_EN           IOMUX_PAD(0x44c, 0x0b8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A23__EIM_A23               (_MX51_PAD_EIM_A23__EIM_A23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A23__EIM_A23               IOMUX_PAD(0x44c, 0x0b8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A23__GPIO2_17              (_MX51_PAD_EIM_A23__GPIO2_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_A23__GPIO2_17              IOMUX_PAD(0x44c, 0x0b8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A24__EIM_A24               (_MX51_PAD_EIM_A24__EIM_A24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A24__EIM_A24               IOMUX_PAD(0x450, 0x0bc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A24__GPIO2_18              (_MX51_PAD_EIM_A24__GPIO2_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_A24__GPIO2_18              IOMUX_PAD(0x450, 0x0bc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A24__USBH2_CLK             (_MX51_PAD_EIM_A24__USBH2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A24__USBH2_CLK             IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A25__DISP1_PIN4            (_MX51_PAD_EIM_A25__DISP1_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A25__DISP1_PIN4            IOMUX_PAD(0x454, 0x0c0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A25__EIM_A25               (_MX51_PAD_EIM_A25__EIM_A25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A25__EIM_A25               IOMUX_PAD(0x454, 0x0c0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A25__GPIO2_19              (_MX51_PAD_EIM_A25__GPIO2_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_A25__GPIO2_19              IOMUX_PAD(0x454, 0x0c0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A25__USBH2_DIR             (_MX51_PAD_EIM_A25__USBH2_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A25__USBH2_DIR             IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A26__CSI1_DATA_EN          (_MX51_PAD_EIM_A26__CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A26__CSI1_DATA_EN          IOMUX_PAD(0x458, 0x0c4, 5, 0x9a0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A26__DISP2_EXT_CLK         (_MX51_PAD_EIM_A26__DISP2_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A26__DISP2_EXT_CLK         IOMUX_PAD(0x458, 0x0c4, 6, 0x908, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A26__EIM_A26               (_MX51_PAD_EIM_A26__EIM_A26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A26__EIM_A26               IOMUX_PAD(0x458, 0x0c4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A26__GPIO2_20              (_MX51_PAD_EIM_A26__GPIO2_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_A26__GPIO2_20              IOMUX_PAD(0x458, 0x0c4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A26__USBH2_STP             (_MX51_PAD_EIM_A26__USBH2_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A26__USBH2_STP             IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A27__CSI2_DATA_EN          (_MX51_PAD_EIM_A27__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A27__CSI2_DATA_EN          IOMUX_PAD(0x45c, 0x0c8, 5, 0x99c, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A27__DISP1_PIN1            (_MX51_PAD_EIM_A27__DISP1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A27__DISP1_PIN1            IOMUX_PAD(0x45c, 0x0c8, 6, 0x9a4, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A27__EIM_A27               (_MX51_PAD_EIM_A27__EIM_A27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A27__EIM_A27               IOMUX_PAD(0x45c, 0x0c8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A27__GPIO2_21              (_MX51_PAD_EIM_A27__GPIO2_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_A27__GPIO2_21              IOMUX_PAD(0x45c, 0x0c8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A27__USBH2_NXT             (_MX51_PAD_EIM_A27__USBH2_NXT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A27__USBH2_NXT             IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB0__EIM_EB0               (_MX51_PAD_EIM_EB0__EIM_EB0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_EB0__EIM_EB0               IOMUX_PAD(0x460, 0x0cc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB1__EIM_EB1               (_MX51_PAD_EIM_EB1__EIM_EB1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_EB1__EIM_EB1               IOMUX_PAD(0x464, 0x0d0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB2__AUD5_RXFS             (_MX51_PAD_EIM_EB2__AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_EB2__AUD5_RXFS             IOMUX_PAD(0x468, 0x0d4, 6, 0x8e0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB2__CSI1_D2               (_MX51_PAD_EIM_EB2__CSI1_D2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_EB2__CSI1_D2               IOMUX_PAD(0x468, 0x0d4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB2__EIM_EB2               (_MX51_PAD_EIM_EB2__EIM_EB2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_EB2__EIM_EB2               IOMUX_PAD(0x468, 0x0d4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB2__FEC_MDIO              (_MX51_PAD_EIM_EB2__FEC_MDIO | \
+#define MX51_PAD_EIM_EB2__FEC_MDIO              (IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, 0) | \
                MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | PAD_CTL_PKE | PAD_CTL_SRE_FAST | \
                PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS))
-#define MX51_PAD_EIM_EB2__GPIO2_22              (_MX51_PAD_EIM_EB2__GPIO2_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_EB2__GPIO2_22              IOMUX_PAD(0x468, 0x0d4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_EB2__GPT_CMPOUT1           (_MX51_PAD_EIM_EB2__GPT_CMPOUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_EB2__GPT_CMPOUT1           IOMUX_PAD(0x468, 0x0d4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB3__AUD5_RXC              (_MX51_PAD_EIM_EB3__AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_EB3__AUD5_RXC              IOMUX_PAD(0x46c, 0x0d8, 6, 0x8dc, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB3__CSI1_D3               (_MX51_PAD_EIM_EB3__CSI1_D3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_EB3__CSI1_D3               IOMUX_PAD(0x46c, 0x0d8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB3__EIM_EB3               (_MX51_PAD_EIM_EB3__EIM_EB3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_EB3__EIM_EB3               IOMUX_PAD(0x46c, 0x0d8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB3__FEC_RDATA1            (_MX51_PAD_EIM_EB3__FEC_RDATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_EB3__FEC_RDATA1            IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB3__GPIO2_23              (_MX51_PAD_EIM_EB3__GPIO2_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_EB3__GPIO2_23              IOMUX_PAD(0x46c, 0x0d8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_EB3__GPT_CMPOUT2           (_MX51_PAD_EIM_EB3__GPT_CMPOUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_EB3__GPT_CMPOUT2           IOMUX_PAD(0x46c, 0x0d8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_OE__EIM_OE                 (_MX51_PAD_EIM_OE__EIM_OE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_OE__EIM_OE                 IOMUX_PAD(0x470, 0x0dc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_OE__GPIO2_24               (_MX51_PAD_EIM_OE__GPIO2_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_OE__GPIO2_24               IOMUX_PAD(0x470, 0x0dc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS0__EIM_CS0               (_MX51_PAD_EIM_CS0__EIM_CS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS0__EIM_CS0               IOMUX_PAD(0x474, 0x0e0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS0__GPIO2_25              (_MX51_PAD_EIM_CS0__GPIO2_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_CS0__GPIO2_25              IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS1__EIM_CS1               (_MX51_PAD_EIM_CS1__EIM_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS1__EIM_CS1               IOMUX_PAD(0x478, 0x0e4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS1__GPIO2_26              (_MX51_PAD_EIM_CS1__GPIO2_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_CS1__GPIO2_26              IOMUX_PAD(0x478, 0x0e4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__AUD5_TXD              (_MX51_PAD_EIM_CS2__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS2__AUD5_TXD              IOMUX_PAD(0x47c, 0x0e8, 6, 0x8d8, 1, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__CSI1_D4               (_MX51_PAD_EIM_CS2__CSI1_D4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS2__CSI1_D4               IOMUX_PAD(0x47c, 0x0e8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__EIM_CS2               (_MX51_PAD_EIM_CS2__EIM_CS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS2__EIM_CS2               IOMUX_PAD(0x47c, 0x0e8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__FEC_RDATA2            (_MX51_PAD_EIM_CS2__FEC_RDATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS2__FEC_RDATA2            IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__GPIO2_27              (_MX51_PAD_EIM_CS2__GPIO2_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_CS2__GPIO2_27              IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__USBOTG_STP            (_MX51_PAD_EIM_CS2__USBOTG_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS2__USBOTG_STP            IOMUX_PAD(0x47c, 0x0e8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS3__AUD5_RXD              (_MX51_PAD_EIM_CS3__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS3__AUD5_RXD              IOMUX_PAD(0x480, 0x0ec, 6, 0x8d4, 1, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS3__CSI1_D5               (_MX51_PAD_EIM_CS3__CSI1_D5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS3__CSI1_D5               IOMUX_PAD(0x480, 0x0ec, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS3__EIM_CS3               (_MX51_PAD_EIM_CS3__EIM_CS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS3__EIM_CS3               IOMUX_PAD(0x480, 0x0ec, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS3__FEC_RDATA3            (_MX51_PAD_EIM_CS3__FEC_RDATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS3__FEC_RDATA3            IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS3__GPIO2_28              (_MX51_PAD_EIM_CS3__GPIO2_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_CS3__GPIO2_28              IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS3__USBOTG_NXT            (_MX51_PAD_EIM_CS3__USBOTG_NXT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS3__USBOTG_NXT            IOMUX_PAD(0x480, 0x0ec, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS4__AUD5_TXC              (_MX51_PAD_EIM_CS4__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS4__AUD5_TXC              IOMUX_PAD(0x484, 0x0f0, 6, 0x8e4, 1, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS4__CSI1_D6               (_MX51_PAD_EIM_CS4__CSI1_D6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS4__CSI1_D6               IOMUX_PAD(0x484, 0x0f0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS4__EIM_CS4               (_MX51_PAD_EIM_CS4__EIM_CS4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS4__EIM_CS4               IOMUX_PAD(0x484, 0x0f0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS4__FEC_RX_ER             (_MX51_PAD_EIM_CS4__FEC_RX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_2))
+#define MX51_PAD_EIM_CS4__FEC_RX_ER             IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2)
-#define MX51_PAD_EIM_CS4__GPIO2_29              (_MX51_PAD_EIM_CS4__GPIO2_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_CS4__GPIO2_29              IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS4__USBOTG_CLK            (_MX51_PAD_EIM_CS4__USBOTG_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS4__USBOTG_CLK            IOMUX_PAD(0x484, 0x0f0, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS5__AUD5_TXFS             (_MX51_PAD_EIM_CS5__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS5__AUD5_TXFS             IOMUX_PAD(0x488, 0x0f4, 6, 0x8e8, 1, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS5__CSI1_D7               (_MX51_PAD_EIM_CS5__CSI1_D7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS5__CSI1_D7               IOMUX_PAD(0x488, 0x0f4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK         (_MX51_PAD_EIM_CS5__DISP1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK         IOMUX_PAD(0x488, 0x0f4, 4, 0x904, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS5__EIM_CS5               (_MX51_PAD_EIM_CS5__EIM_CS5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS5__EIM_CS5               IOMUX_PAD(0x488, 0x0f4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS5__FEC_CRS               (_MX51_PAD_EIM_CS5__FEC_CRS | MUX_PAD_CTRL(MX51_PAD_CTRL_2))
+#define MX51_PAD_EIM_CS5__FEC_CRS               IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2)
-#define MX51_PAD_EIM_CS5__GPIO2_30              (_MX51_PAD_EIM_CS5__GPIO2_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_CS5__GPIO2_30              IOMUX_PAD(0x488, 0x0f4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS5__USBOTG_DIR            (_MX51_PAD_EIM_CS5__USBOTG_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS5__USBOTG_DIR            IOMUX_PAD(0x488, 0x0f4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DTACK__EIM_DTACK           (_MX51_PAD_EIM_DTACK__EIM_DTACK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DTACK__EIM_DTACK           IOMUX_PAD(0x48c, 0x0f8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DTACK__GPIO2_31            (_MX51_PAD_EIM_DTACK__GPIO2_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_DTACK__GPIO2_31            IOMUX_PAD(0x48c, 0x0f8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_LBA__EIM_LBA               (_MX51_PAD_EIM_LBA__EIM_LBA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_LBA__EIM_LBA               IOMUX_PAD(0x494, 0x0fc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_LBA__GPIO3_1               (_MX51_PAD_EIM_LBA__GPIO3_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_LBA__GPIO3_1               IOMUX_PAD(0x494, 0x0fc, 1, 0x978, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CRE__EIM_CRE               (_MX51_PAD_EIM_CRE__EIM_CRE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CRE__EIM_CRE               IOMUX_PAD(0x4a0, 0x100, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CRE__GPIO3_2               (_MX51_PAD_EIM_CRE__GPIO3_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_CRE__GPIO3_2               IOMUX_PAD(0x4a0, 0x100, 1, 0x97c, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DRAM_CS1__DRAM_CS1             (_MX51_PAD_DRAM_CS1__DRAM_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DRAM_CS1__DRAM_CS1             IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WE_B__GPIO3_3            (_MX51_PAD_NANDF_WE_B__GPIO3_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_WE_B__GPIO3_3            IOMUX_PAD(0x4e4, 0x108, 3, 0x980, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_WE_B__NANDF_WE_B         (_MX51_PAD_NANDF_WE_B__NANDF_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_WE_B__NANDF_WE_B         IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WE_B__PATA_DIOW          (_MX51_PAD_NANDF_WE_B__PATA_DIOW | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_WE_B__PATA_DIOW          IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WE_B__SD3_DATA0          (_MX51_PAD_NANDF_WE_B__SD3_DATA0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
+#define MX51_PAD_NANDF_WE_B__SD3_DATA0          IOMUX_PAD(0x4e4, 0x108, 2, 0x93c, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_RE_B__GPIO3_4            (_MX51_PAD_NANDF_RE_B__GPIO3_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_RE_B__GPIO3_4            IOMUX_PAD(0x4e8, 0x10c, 3, 0x984, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_RE_B__NANDF_RE_B         (_MX51_PAD_NANDF_RE_B__NANDF_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RE_B__NANDF_RE_B         IOMUX_PAD(0x4e8, 0x10c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RE_B__PATA_DIOR          (_MX51_PAD_NANDF_RE_B__PATA_DIOR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RE_B__PATA_DIOR          IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RE_B__SD3_DATA1          (_MX51_PAD_NANDF_RE_B__SD3_DATA1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
+#define MX51_PAD_NANDF_RE_B__SD3_DATA1          IOMUX_PAD(0x4e8, 0x10c, 2, 0x940, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_ALE__GPIO3_5             (_MX51_PAD_NANDF_ALE__GPIO3_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_ALE__GPIO3_5             IOMUX_PAD(0x4ec, 0x110, 3, 0x988, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_ALE__NANDF_ALE           (_MX51_PAD_NANDF_ALE__NANDF_ALE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_ALE__NANDF_ALE           IOMUX_PAD(0x4ec, 0x110, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN      (_MX51_PAD_NANDF_ALE__PATA_BUFFER_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN      IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CLE__GPIO3_6             (_MX51_PAD_NANDF_CLE__GPIO3_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_CLE__GPIO3_6             IOMUX_PAD(0x4f0, 0x114, 3, 0x98c, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CLE__NANDF_CLE           (_MX51_PAD_NANDF_CLE__NANDF_CLE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CLE__NANDF_CLE           IOMUX_PAD(0x4f0, 0x114, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CLE__PATA_RESET_B        (_MX51_PAD_NANDF_CLE__PATA_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CLE__PATA_RESET_B        IOMUX_PAD(0x4f0, 0x114, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WP_B__GPIO3_7            (_MX51_PAD_NANDF_WP_B__GPIO3_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_WP_B__GPIO3_7            IOMUX_PAD(0x4f4, 0x118, 3, 0x990, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_WP_B__NANDF_WP_B         (_MX51_PAD_NANDF_WP_B__NANDF_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_WP_B__NANDF_WP_B         IOMUX_PAD(0x4f4, 0x118, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WP_B__PATA_DMACK         (_MX51_PAD_NANDF_WP_B__PATA_DMACK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_WP_B__PATA_DMACK         IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WP_B__SD3_DATA2          (_MX51_PAD_NANDF_WP_B__SD3_DATA2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
+#define MX51_PAD_NANDF_WP_B__SD3_DATA2          IOMUX_PAD(0x4f4, 0x118, 2, 0x944, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB0__ECSPI2_SS1          (_MX51_PAD_NANDF_RB0__ECSPI2_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_NANDF_RB0__ECSPI2_SS1          IOMUX_PAD(0x4f8, 0x11c, 5, 0x930, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB0__GPIO3_8             (_MX51_PAD_NANDF_RB0__GPIO3_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB0__GPIO3_8             IOMUX_PAD(0x4f8, 0x11c, 3, 0x994, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB0__NANDF_RB0           (_MX51_PAD_NANDF_RB0__NANDF_RB0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB0__NANDF_RB0           IOMUX_PAD(0x4f8, 0x11c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB0__PATA_DMARQ          (_MX51_PAD_NANDF_RB0__PATA_DMARQ | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB0__PATA_DMARQ          IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB0__SD3_DATA3           (_MX51_PAD_NANDF_RB0__SD3_DATA3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
+#define MX51_PAD_NANDF_RB0__SD3_DATA3           IOMUX_PAD(0x4f8, 0x11c, 2, 0x948, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__CSPI_MOSI           (_MX51_PAD_NANDF_RB1__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_NANDF_RB1__CSPI_MOSI           IOMUX_PAD(0x4fc, 0x120, 6, 0x91c, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__ECSPI2_RDY          (_MX51_PAD_NANDF_RB1__ECSPI2_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_NANDF_RB1__ECSPI2_RDY          IOMUX_PAD(0x4fc, 0x120, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__GPIO3_9             (_MX51_PAD_NANDF_RB1__GPIO3_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB1__GPIO3_9             IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__NANDF_RB1           (_MX51_PAD_NANDF_RB1__NANDF_RB1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB1__NANDF_RB1           IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__PATA_IORDY          (_MX51_PAD_NANDF_RB1__PATA_IORDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB1__PATA_IORDY          IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__SD4_CMD             (_MX51_PAD_NANDF_RB1__SD4_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
+#define MX51_PAD_NANDF_RB1__SD4_CMD             IOMUX_PAD(0x4fc, 0x120, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__DISP2_WAIT          (_MX51_PAD_NANDF_RB2__DISP2_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB2__DISP2_WAIT          IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK         (_MX51_PAD_NANDF_RB2__ECSPI2_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK         IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__FEC_COL             (_MX51_PAD_NANDF_RB2__FEC_COL | MUX_PAD_CTRL(MX51_PAD_CTRL_2))
+#define MX51_PAD_NANDF_RB2__FEC_COL             IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2)
-#define MX51_PAD_NANDF_RB2__GPIO3_10            (_MX51_PAD_NANDF_RB2__GPIO3_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB2__GPIO3_10            IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__NANDF_RB2           (_MX51_PAD_NANDF_RB2__NANDF_RB2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB2__NANDF_RB2           IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__USBH3_H3_DP         (_MX51_PAD_NANDF_RB2__USBH3_H3_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB2__USBH3_H3_DP         IOMUX_PAD(0x500, 0x124, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__USBH3_NXT           (_MX51_PAD_NANDF_RB2__USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB2__USBH3_NXT           IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__DISP1_WAIT          (_MX51_PAD_NANDF_RB3__DISP1_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB3__DISP1_WAIT          IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__ECSPI2_MISO         (_MX51_PAD_NANDF_RB3__ECSPI2_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_NANDF_RB3__ECSPI2_MISO         IOMUX_PAD(0x504, 0x128, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__FEC_RX_CLK          (_MX51_PAD_NANDF_RB3__FEC_RX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_2))
+#define MX51_PAD_NANDF_RB3__FEC_RX_CLK          IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2)
-#define MX51_PAD_NANDF_RB3__GPIO3_11            (_MX51_PAD_NANDF_RB3__GPIO3_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB3__GPIO3_11            IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__NANDF_RB3           (_MX51_PAD_NANDF_RB3__NANDF_RB3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB3__NANDF_RB3           IOMUX_PAD(0x504, 0x128, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__USBH3_CLK           (_MX51_PAD_NANDF_RB3__USBH3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB3__USBH3_CLK           IOMUX_PAD(0x504, 0x128, 6, 0x9f8, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__USBH3_H3_DM         (_MX51_PAD_NANDF_RB3__USBH3_H3_DM | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB3__USBH3_H3_DM         IOMUX_PAD(0x504, 0x128, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_NAND__GPIO_NAND           (_MX51_PAD_GPIO_NAND__GPIO_NAND | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_GPIO_NAND__GPIO_NAND           IOMUX_PAD(0x514, 0x12c, 0, 0x998, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_NAND__PATA_INTRQ          (_MX51_PAD_GPIO_NAND__PATA_INTRQ | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO_NAND__PATA_INTRQ          IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS0__GPIO3_16            (_MX51_PAD_NANDF_CS0__GPIO3_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS0__GPIO3_16            IOMUX_PAD(0x518, 0x130, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS0__NANDF_CS0           (_MX51_PAD_NANDF_CS0__NANDF_CS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS0__NANDF_CS0           IOMUX_PAD(0x518, 0x130, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS1__GPIO3_17            (_MX51_PAD_NANDF_CS1__GPIO3_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS1__GPIO3_17            IOMUX_PAD(0x51c, 0x134, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS1__NANDF_CS1           (_MX51_PAD_NANDF_CS1__NANDF_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS1__NANDF_CS1           IOMUX_PAD(0x51c, 0x134, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS2__CSPI_SCLK           (_MX51_PAD_NANDF_CS2__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_NANDF_CS2__CSPI_SCLK           IOMUX_PAD(0x520, 0x138, 6, 0x914, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_CS2__FEC_TX_ER           (_MX51_PAD_NANDF_CS2__FEC_TX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
+#define MX51_PAD_NANDF_CS2__FEC_TX_ER           IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS2__GPIO3_18            (_MX51_PAD_NANDF_CS2__GPIO3_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS2__GPIO3_18            IOMUX_PAD(0x520, 0x138, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS2__NANDF_CS2           (_MX51_PAD_NANDF_CS2__NANDF_CS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS2__NANDF_CS2           IOMUX_PAD(0x520, 0x138, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS2__PATA_CS_0           (_MX51_PAD_NANDF_CS2__PATA_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS2__PATA_CS_0           IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS2__SD4_CLK             (_MX51_PAD_NANDF_CS2__SD4_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS))
+#define MX51_PAD_NANDF_CS2__SD4_CLK             IOMUX_PAD(0x520, 0x138, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
-#define MX51_PAD_NANDF_CS2__USBH3_H1_DP         (_MX51_PAD_NANDF_CS2__USBH3_H1_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS2__USBH3_H1_DP         IOMUX_PAD(0x520, 0x138, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS3__FEC_MDC             (_MX51_PAD_NANDF_CS3__FEC_MDC | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
+#define MX51_PAD_NANDF_CS3__FEC_MDC             IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS3__GPIO3_19            (_MX51_PAD_NANDF_CS3__GPIO3_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS3__GPIO3_19            IOMUX_PAD(0x524, 0x13c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS3__NANDF_CS3           (_MX51_PAD_NANDF_CS3__NANDF_CS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS3__NANDF_CS3           IOMUX_PAD(0x524, 0x13c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS3__PATA_CS_1           (_MX51_PAD_NANDF_CS3__PATA_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS3__PATA_CS_1           IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS3__SD4_DAT0            (_MX51_PAD_NANDF_CS3__SD4_DAT0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
+#define MX51_PAD_NANDF_CS3__SD4_DAT0            IOMUX_PAD(0x524, 0x13c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_CS3__USBH3_H1_DM         (_MX51_PAD_NANDF_CS3__USBH3_H1_DM | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS3__USBH3_H1_DM         IOMUX_PAD(0x524, 0x13c, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS4__FEC_TDATA1          (_MX51_PAD_NANDF_CS4__FEC_TDATA1 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
+#define MX51_PAD_NANDF_CS4__FEC_TDATA1          IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS4__GPIO3_20            (_MX51_PAD_NANDF_CS4__GPIO3_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS4__GPIO3_20            IOMUX_PAD(0x528, 0x140, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS4__NANDF_CS4           (_MX51_PAD_NANDF_CS4__NANDF_CS4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS4__NANDF_CS4           IOMUX_PAD(0x528, 0x140, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS4__PATA_DA_0           (_MX51_PAD_NANDF_CS4__PATA_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS4__PATA_DA_0           IOMUX_PAD(0x528, 0x140, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS4__SD4_DAT1            (_MX51_PAD_NANDF_CS4__SD4_DAT1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
+#define MX51_PAD_NANDF_CS4__SD4_DAT1            IOMUX_PAD(0x528, 0x140, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_CS4__USBH3_STP           (_MX51_PAD_NANDF_CS4__USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS4__USBH3_STP           IOMUX_PAD(0x528, 0x140, 7, 0xa24, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS5__FEC_TDATA2          (_MX51_PAD_NANDF_CS5__FEC_TDATA2 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
+#define MX51_PAD_NANDF_CS5__FEC_TDATA2          IOMUX_PAD(0x52c, 0x144, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS5__GPIO3_21            (_MX51_PAD_NANDF_CS5__GPIO3_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS5__GPIO3_21            IOMUX_PAD(0x52c, 0x144, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS5__NANDF_CS5           (_MX51_PAD_NANDF_CS5__NANDF_CS5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS5__NANDF_CS5           IOMUX_PAD(0x52c, 0x144, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS5__PATA_DA_1           (_MX51_PAD_NANDF_CS5__PATA_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS5__PATA_DA_1           IOMUX_PAD(0x52c, 0x144, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS5__SD4_DAT2            (_MX51_PAD_NANDF_CS5__SD4_DAT2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
+#define MX51_PAD_NANDF_CS5__SD4_DAT2            IOMUX_PAD(0x52c, 0x144, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_CS5__USBH3_DIR           (_MX51_PAD_NANDF_CS5__USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS5__USBH3_DIR           IOMUX_PAD(0x52c, 0x144, 7, 0xa1c, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS6__CSPI_SS3            (_MX51_PAD_NANDF_CS6__CSPI_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_NANDF_CS6__CSPI_SS3            IOMUX_PAD(0x530, 0x148, 7, 0x928, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_CS6__FEC_TDATA3          (_MX51_PAD_NANDF_CS6__FEC_TDATA3 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
+#define MX51_PAD_NANDF_CS6__FEC_TDATA3          IOMUX_PAD(0x530, 0x148, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS6__GPIO3_22            (_MX51_PAD_NANDF_CS6__GPIO3_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS6__GPIO3_22            IOMUX_PAD(0x530, 0x148, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS6__NANDF_CS6           (_MX51_PAD_NANDF_CS6__NANDF_CS6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS6__NANDF_CS6           IOMUX_PAD(0x530, 0x148, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS6__PATA_DA_2           (_MX51_PAD_NANDF_CS6__PATA_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS6__PATA_DA_2           IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS6__SD4_DAT3            (_MX51_PAD_NANDF_CS6__SD4_DAT3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
+#define MX51_PAD_NANDF_CS6__SD4_DAT3            IOMUX_PAD(0x530, 0x148, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_CS7__FEC_TX_EN           (_MX51_PAD_NANDF_CS7__FEC_TX_EN | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
+#define MX51_PAD_NANDF_CS7__FEC_TX_EN           IOMUX_PAD(0x534, 0x14c, 1, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS7__GPIO3_23            (_MX51_PAD_NANDF_CS7__GPIO3_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS7__GPIO3_23            IOMUX_PAD(0x534, 0x14c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS7__NANDF_CS7           (_MX51_PAD_NANDF_CS7__NANDF_CS7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS7__NANDF_CS7           IOMUX_PAD(0x534, 0x14c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS7__SD3_CLK             (_MX51_PAD_NANDF_CS7__SD3_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS))
+#define MX51_PAD_NANDF_CS7__SD3_CLK             IOMUX_PAD(0x534, 0x14c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
-#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0      (_MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0      IOMUX_PAD(0x538, 0x150, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK      (_MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_4))
+#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK      IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4)
-#define MX51_PAD_NANDF_RDY_INT__GPIO3_24        (_MX51_PAD_NANDF_RDY_INT__GPIO3_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_RDY_INT__GPIO3_24        IOMUX_PAD(0x538, 0x150, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT   (_MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT   IOMUX_PAD(0x538, 0x150, 0, 0x938, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RDY_INT__SD3_CMD         (_MX51_PAD_NANDF_RDY_INT__SD3_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
+#define MX51_PAD_NANDF_RDY_INT__SD3_CMD         IOMUX_PAD(0x538, 0x150, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_D15__ECSPI2_MOSI         (_MX51_PAD_NANDF_D15__ECSPI2_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_NANDF_D15__ECSPI2_MOSI         IOMUX_PAD(0x53c, 0x154, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_D15__GPIO3_25            (_MX51_PAD_NANDF_D15__GPIO3_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_D15__GPIO3_25            IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D15__NANDF_D15           (_MX51_PAD_NANDF_D15__NANDF_D15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D15__NANDF_D15           IOMUX_PAD(0x53c, 0x154, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D15__PATA_DATA15         (_MX51_PAD_NANDF_D15__PATA_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D15__PATA_DATA15         IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D15__SD3_DAT7            (_MX51_PAD_NANDF_D15__SD3_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D15__SD3_DAT7            IOMUX_PAD(0x53c, 0x154, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D14__ECSPI2_SS3          (_MX51_PAD_NANDF_D14__ECSPI2_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_NANDF_D14__ECSPI2_SS3          IOMUX_PAD(0x540, 0x158, 2, 0x934, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_D14__GPIO3_26            (_MX51_PAD_NANDF_D14__GPIO3_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_D14__GPIO3_26            IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D14__NANDF_D14           (_MX51_PAD_NANDF_D14__NANDF_D14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D14__NANDF_D14           IOMUX_PAD(0x540, 0x158, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D14__PATA_DATA14         (_MX51_PAD_NANDF_D14__PATA_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D14__PATA_DATA14         IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D14__SD3_DAT6            (_MX51_PAD_NANDF_D14__SD3_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D14__SD3_DAT6            IOMUX_PAD(0x540, 0x158, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D13__ECSPI2_SS2          (_MX51_PAD_NANDF_D13__ECSPI2_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_NANDF_D13__ECSPI2_SS2          IOMUX_PAD(0x544, 0x15c, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_D13__GPIO3_27            (_MX51_PAD_NANDF_D13__GPIO3_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_D13__GPIO3_27            IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D13__NANDF_D13           (_MX51_PAD_NANDF_D13__NANDF_D13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D13__NANDF_D13           IOMUX_PAD(0x544, 0x15c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D13__PATA_DATA13         (_MX51_PAD_NANDF_D13__PATA_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D13__PATA_DATA13         IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D13__SD3_DAT5            (_MX51_PAD_NANDF_D13__SD3_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D13__SD3_DAT5            IOMUX_PAD(0x544, 0x15c, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D12__ECSPI2_SS1          (_MX51_PAD_NANDF_D12__ECSPI2_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_NANDF_D12__ECSPI2_SS1          IOMUX_PAD(0x548, 0x160, 2, 0x930, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_D12__GPIO3_28            (_MX51_PAD_NANDF_D12__GPIO3_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_D12__GPIO3_28            IOMUX_PAD(0x548, 0x160, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D12__NANDF_D12           (_MX51_PAD_NANDF_D12__NANDF_D12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D12__NANDF_D12           IOMUX_PAD(0x548, 0x160, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D12__PATA_DATA12         (_MX51_PAD_NANDF_D12__PATA_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D12__PATA_DATA12         IOMUX_PAD(0x548, 0x160, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D12__SD3_DAT4            (_MX51_PAD_NANDF_D12__SD3_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D12__SD3_DAT4            IOMUX_PAD(0x548, 0x160, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D11__FEC_RX_DV           (_MX51_PAD_NANDF_D11__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D11__FEC_RX_DV           IOMUX_PAD(0x54c, 0x164, 2, 0x96c, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D11__GPIO3_29            (_MX51_PAD_NANDF_D11__GPIO3_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_D11__GPIO3_29            IOMUX_PAD(0x54c, 0x164, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D11__NANDF_D11           (_MX51_PAD_NANDF_D11__NANDF_D11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D11__NANDF_D11           IOMUX_PAD(0x54c, 0x164, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D11__PATA_DATA11         (_MX51_PAD_NANDF_D11__PATA_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D11__PATA_DATA11         IOMUX_PAD(0x54c, 0x164, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D11__SD3_DATA3           (_MX51_PAD_NANDF_D11__SD3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D11__SD3_DATA3           IOMUX_PAD(0x54c, 0x164, 5, 0x948, 1, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D10__GPIO3_30            (_MX51_PAD_NANDF_D10__GPIO3_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_D10__GPIO3_30            IOMUX_PAD(0x550, 0x168, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D10__NANDF_D10           (_MX51_PAD_NANDF_D10__NANDF_D10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D10__NANDF_D10           IOMUX_PAD(0x550, 0x168, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D10__PATA_DATA10         (_MX51_PAD_NANDF_D10__PATA_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D10__PATA_DATA10         IOMUX_PAD(0x550, 0x168, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D10__SD3_DATA2           (_MX51_PAD_NANDF_D10__SD3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D10__SD3_DATA2           IOMUX_PAD(0x550, 0x168, 5, 0x944, 1, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D9__FEC_RDATA0           (_MX51_PAD_NANDF_D9__FEC_RDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_4))
+#define MX51_PAD_NANDF_D9__FEC_RDATA0           IOMUX_PAD(0x554, 0x16c, 0x12, 0x958, 0, MX51_PAD_CTRL_4)
-#define MX51_PAD_NANDF_D9__GPIO3_31             (_MX51_PAD_NANDF_D9__GPIO3_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_D9__GPIO3_31             IOMUX_PAD(0x554, 0x16c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D9__NANDF_D9             (_MX51_PAD_NANDF_D9__NANDF_D9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D9__NANDF_D9             IOMUX_PAD(0x554, 0x16c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D9__PATA_DATA9           (_MX51_PAD_NANDF_D9__PATA_DATA9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D9__PATA_DATA9           IOMUX_PAD(0x554, 0x16c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D9__SD3_DATA1            (_MX51_PAD_NANDF_D9__SD3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D9__SD3_DATA1            IOMUX_PAD(0x554, 0x16c, 5, 0x940, 1, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D8__FEC_TDATA0           (_MX51_PAD_NANDF_D8__FEC_TDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
+#define MX51_PAD_NANDF_D8__FEC_TDATA0           IOMUX_PAD(0x558, 0x170, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_D8__GPIO4_0              (_MX51_PAD_NANDF_D8__GPIO4_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_D8__GPIO4_0              IOMUX_PAD(0x558, 0x170, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D8__NANDF_D8             (_MX51_PAD_NANDF_D8__NANDF_D8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D8__NANDF_D8             IOMUX_PAD(0x558, 0x170, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D8__PATA_DATA8           (_MX51_PAD_NANDF_D8__PATA_DATA8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D8__PATA_DATA8           IOMUX_PAD(0x558, 0x170, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D8__SD3_DATA0            (_MX51_PAD_NANDF_D8__SD3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D8__SD3_DATA0            IOMUX_PAD(0x558, 0x170, 5, 0x93c, 1, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D7__GPIO4_1              (_MX51_PAD_NANDF_D7__GPIO4_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_D7__GPIO4_1              IOMUX_PAD(0x55c, 0x174, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D7__NANDF_D7             (_MX51_PAD_NANDF_D7__NANDF_D7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D7__NANDF_D7             IOMUX_PAD(0x55c, 0x174, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D7__PATA_DATA7           (_MX51_PAD_NANDF_D7__PATA_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D7__PATA_DATA7           IOMUX_PAD(0x55c, 0x174, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D7__USBH3_DATA0          (_MX51_PAD_NANDF_D7__USBH3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D7__USBH3_DATA0          IOMUX_PAD(0x55c, 0x174, 5, 0x9fc, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D6__GPIO4_2              (_MX51_PAD_NANDF_D6__GPIO4_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_D6__GPIO4_2              IOMUX_PAD(0x560, 0x178, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D6__NANDF_D6             (_MX51_PAD_NANDF_D6__NANDF_D6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D6__NANDF_D6             IOMUX_PAD(0x560, 0x178, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D6__PATA_DATA6           (_MX51_PAD_NANDF_D6__PATA_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D6__PATA_DATA6           IOMUX_PAD(0x560, 0x178, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D6__SD4_LCTL             (_MX51_PAD_NANDF_D6__SD4_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D6__SD4_LCTL             IOMUX_PAD(0x560, 0x178, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D6__USBH3_DATA1          (_MX51_PAD_NANDF_D6__USBH3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D6__USBH3_DATA1          IOMUX_PAD(0x560, 0x178, 5, 0xa00, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D5__GPIO4_3              (_MX51_PAD_NANDF_D5__GPIO4_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_D5__GPIO4_3              IOMUX_PAD(0x564, 0x17c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D5__NANDF_D5             (_MX51_PAD_NANDF_D5__NANDF_D5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D5__NANDF_D5             IOMUX_PAD(0x564, 0x17c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D5__PATA_DATA5           (_MX51_PAD_NANDF_D5__PATA_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D5__PATA_DATA5           IOMUX_PAD(0x564, 0x17c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D5__SD4_WP               (_MX51_PAD_NANDF_D5__SD4_WP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D5__SD4_WP               IOMUX_PAD(0x564, 0x17c, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D5__USBH3_DATA2          (_MX51_PAD_NANDF_D5__USBH3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D5__USBH3_DATA2          IOMUX_PAD(0x564, 0x17c, 5, 0xa04, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D4__GPIO4_4              (_MX51_PAD_NANDF_D4__GPIO4_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_D4__GPIO4_4              IOMUX_PAD(0x568, 0x180, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D4__NANDF_D4             (_MX51_PAD_NANDF_D4__NANDF_D4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D4__NANDF_D4             IOMUX_PAD(0x568, 0x180, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D4__PATA_DATA4           (_MX51_PAD_NANDF_D4__PATA_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D4__PATA_DATA4           IOMUX_PAD(0x568, 0x180, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D4__SD4_CD               (_MX51_PAD_NANDF_D4__SD4_CD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D4__SD4_CD               IOMUX_PAD(0x568, 0x180, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D4__USBH3_DATA3          (_MX51_PAD_NANDF_D4__USBH3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D4__USBH3_DATA3          IOMUX_PAD(0x568, 0x180, 5, 0xa08, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D3__GPIO4_5              (_MX51_PAD_NANDF_D3__GPIO4_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_D3__GPIO4_5              IOMUX_PAD(0x56c, 0x184, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D3__NANDF_D3             (_MX51_PAD_NANDF_D3__NANDF_D3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D3__NANDF_D3             IOMUX_PAD(0x56c, 0x184, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D3__PATA_DATA3           (_MX51_PAD_NANDF_D3__PATA_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D3__PATA_DATA3           IOMUX_PAD(0x56c, 0x184, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D3__SD4_DAT4             (_MX51_PAD_NANDF_D3__SD4_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D3__SD4_DAT4             IOMUX_PAD(0x56c, 0x184, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D3__USBH3_DATA4          (_MX51_PAD_NANDF_D3__USBH3_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D3__USBH3_DATA4          IOMUX_PAD(0x56c, 0x184, 5, 0xa0c, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D2__GPIO4_6              (_MX51_PAD_NANDF_D2__GPIO4_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_D2__GPIO4_6              IOMUX_PAD(0x570, 0x188, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D2__NANDF_D2             (_MX51_PAD_NANDF_D2__NANDF_D2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D2__NANDF_D2             IOMUX_PAD(0x570, 0x188, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D2__PATA_DATA2           (_MX51_PAD_NANDF_D2__PATA_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D2__PATA_DATA2           IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D2__SD4_DAT5             (_MX51_PAD_NANDF_D2__SD4_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D2__SD4_DAT5             IOMUX_PAD(0x570, 0x188, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D2__USBH3_DATA5          (_MX51_PAD_NANDF_D2__USBH3_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D2__USBH3_DATA5          IOMUX_PAD(0x570, 0x188, 5, 0xa10, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D1__GPIO4_7              (_MX51_PAD_NANDF_D1__GPIO4_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_D1__GPIO4_7              IOMUX_PAD(0x574, 0x18c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D1__NANDF_D1             (_MX51_PAD_NANDF_D1__NANDF_D1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D1__NANDF_D1             IOMUX_PAD(0x574, 0x18c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D1__PATA_DATA1           (_MX51_PAD_NANDF_D1__PATA_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D1__PATA_DATA1           IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D1__SD4_DAT6             (_MX51_PAD_NANDF_D1__SD4_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D1__SD4_DAT6             IOMUX_PAD(0x574, 0x18c, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D1__USBH3_DATA6          (_MX51_PAD_NANDF_D1__USBH3_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D1__USBH3_DATA6          IOMUX_PAD(0x574, 0x18c, 5, 0xa14, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D0__GPIO4_8              (_MX51_PAD_NANDF_D0__GPIO4_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_D0__GPIO4_8              IOMUX_PAD(0x578, 0x190, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D0__NANDF_D0             (_MX51_PAD_NANDF_D0__NANDF_D0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D0__NANDF_D0             IOMUX_PAD(0x578, 0x190, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D0__PATA_DATA0           (_MX51_PAD_NANDF_D0__PATA_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D0__PATA_DATA0           IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D0__SD4_DAT7             (_MX51_PAD_NANDF_D0__SD4_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D0__SD4_DAT7             IOMUX_PAD(0x578, 0x190, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D0__USBH3_DATA7          (_MX51_PAD_NANDF_D0__USBH3_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D0__USBH3_DATA7          IOMUX_PAD(0x578, 0x190, 5, 0xa18, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D8__CSI1_D8               (_MX51_PAD_CSI1_D8__CSI1_D8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI1_D8__CSI1_D8               IOMUX_PAD(0x57c, 0x194, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D8__GPIO3_12              (_MX51_PAD_CSI1_D8__GPIO3_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSI1_D8__GPIO3_12              IOMUX_PAD(0x57c, 0x194, 3, 0x998, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI1_D9__CSI1_D9               (_MX51_PAD_CSI1_D9__CSI1_D9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI1_D9__CSI1_D9               IOMUX_PAD(0x580, 0x198, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D9__GPIO3_13              (_MX51_PAD_CSI1_D9__GPIO3_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSI1_D9__GPIO3_13              IOMUX_PAD(0x580, 0x198, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI1_D10__CSI1_D10             (_MX51_PAD_CSI1_D10__CSI1_D10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI1_D10__CSI1_D10             IOMUX_PAD(0x584, 0x19c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D11__CSI1_D11             (_MX51_PAD_CSI1_D11__CSI1_D11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI1_D11__CSI1_D11             IOMUX_PAD(0x588, 0x1a0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D12__CSI1_D12             (_MX51_PAD_CSI1_D12__CSI1_D12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI1_D12__CSI1_D12             IOMUX_PAD(0x58c, 0x1a4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D13__CSI1_D13             (_MX51_PAD_CSI1_D13__CSI1_D13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI1_D13__CSI1_D13             IOMUX_PAD(0x590, 0x1a8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D14__CSI1_D14             (_MX51_PAD_CSI1_D14__CSI1_D14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI1_D14__CSI1_D14             IOMUX_PAD(0x594, 0x1ac, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D15__CSI1_D15             (_MX51_PAD_CSI1_D15__CSI1_D15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI1_D15__CSI1_D15             IOMUX_PAD(0x598, 0x1b0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D16__CSI1_D16             (_MX51_PAD_CSI1_D16__CSI1_D16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI1_D16__CSI1_D16             IOMUX_PAD(0x59c, 0x1b4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D17__CSI1_D17             (_MX51_PAD_CSI1_D17__CSI1_D17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI1_D17__CSI1_D17             IOMUX_PAD(0x5a0, 0x1b8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D18__CSI1_D18             (_MX51_PAD_CSI1_D18__CSI1_D18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI1_D18__CSI1_D18             IOMUX_PAD(0x5a4, 0x1bc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D19__CSI1_D19             (_MX51_PAD_CSI1_D19__CSI1_D19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI1_D19__CSI1_D19             IOMUX_PAD(0x5a8, 0x1c0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC         (_MX51_PAD_CSI1_VSYNC__CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC         IOMUX_PAD(0x5ac, 0x1c4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_VSYNC__GPIO3_14           (_MX51_PAD_CSI1_VSYNC__GPIO3_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSI1_VSYNC__GPIO3_14           IOMUX_PAD(0x5ac, 0x1c4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC         (_MX51_PAD_CSI1_HSYNC__CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC         IOMUX_PAD(0x5b0, 0x1c8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_HSYNC__GPIO3_15           (_MX51_PAD_CSI1_HSYNC__GPIO3_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSI1_HSYNC__GPIO3_15           IOMUX_PAD(0x5b0, 0x1c8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK       (_MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK       IOMUX_PAD(0x5b4, __NA_, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_MCLK__CSI1_MCLK           (_MX51_PAD_CSI1_MCLK__CSI1_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI1_MCLK__CSI1_MCLK           IOMUX_PAD(0x5b8, __NA_, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D12__CSI2_D12             (_MX51_PAD_CSI2_D12__CSI2_D12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI2_D12__CSI2_D12             IOMUX_PAD(0x5bc, 0x1cc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D12__GPIO4_9              (_MX51_PAD_CSI2_D12__GPIO4_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSI2_D12__GPIO4_9              IOMUX_PAD(0x5bc, 0x1cc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI2_D13__CSI2_D13             (_MX51_PAD_CSI2_D13__CSI2_D13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI2_D13__CSI2_D13             IOMUX_PAD(0x5c0, 0x1d0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D13__GPIO4_10             (_MX51_PAD_CSI2_D13__GPIO4_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSI2_D13__GPIO4_10             IOMUX_PAD(0x5c0, 0x1d0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI2_D14__CSI2_D14             (_MX51_PAD_CSI2_D14__CSI2_D14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI2_D14__CSI2_D14             IOMUX_PAD(0x5c4, 0x1d4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D15__CSI2_D15             (_MX51_PAD_CSI2_D15__CSI2_D15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI2_D15__CSI2_D15             IOMUX_PAD(0x5c8, 0x1d8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D16__CSI2_D16             (_MX51_PAD_CSI2_D16__CSI2_D16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI2_D16__CSI2_D16             IOMUX_PAD(0x5cc, 0x1dc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D17__CSI2_D17             (_MX51_PAD_CSI2_D17__CSI2_D17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI2_D17__CSI2_D17             IOMUX_PAD(0x5d0, 0x1e0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D18__CSI2_D18             (_MX51_PAD_CSI2_D18__CSI2_D18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI2_D18__CSI2_D18             IOMUX_PAD(0x5d4, 0x1e4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D18__GPIO4_11             (_MX51_PAD_CSI2_D18__GPIO4_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSI2_D18__GPIO4_11             IOMUX_PAD(0x5d4, 0x1e4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI2_D19__CSI2_D19             (_MX51_PAD_CSI2_D19__CSI2_D19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI2_D19__CSI2_D19             IOMUX_PAD(0x5d8, 0x1e8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D19__GPIO4_12             (_MX51_PAD_CSI2_D19__GPIO4_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSI2_D19__GPIO4_12             IOMUX_PAD(0x5d8, 0x1e8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC         (_MX51_PAD_CSI2_VSYNC__CSI2_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC         IOMUX_PAD(0x5dc, 0x1ec, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_VSYNC__GPIO4_13           (_MX51_PAD_CSI2_VSYNC__GPIO4_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSI2_VSYNC__GPIO4_13           IOMUX_PAD(0x5dc, 0x1ec, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC         (_MX51_PAD_CSI2_HSYNC__CSI2_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC         IOMUX_PAD(0x5e0, 0x1f0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_HSYNC__GPIO4_14           (_MX51_PAD_CSI2_HSYNC__GPIO4_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSI2_HSYNC__GPIO4_14           IOMUX_PAD(0x5e0, 0x1f0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK       (_MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK       IOMUX_PAD(0x5e4, 0x1f4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_PIXCLK__GPIO4_15          (_MX51_PAD_CSI2_PIXCLK__GPIO4_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSI2_PIXCLK__GPIO4_15          IOMUX_PAD(0x5e4, 0x1f4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_I2C1_CLK__GPIO4_16             (_MX51_PAD_I2C1_CLK__GPIO4_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_I2C1_CLK__GPIO4_16             IOMUX_PAD(0x5e8, 0x1f8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_I2C1_CLK__I2C1_CLK             (_MX51_PAD_I2C1_CLK__I2C1_CLK | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
+#define MX51_PAD_I2C1_CLK__I2C1_CLK             IOMUX_PAD(0x5e8, 0x1f8, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_I2C1_DAT__GPIO4_17             (_MX51_PAD_I2C1_DAT__GPIO4_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_I2C1_DAT__GPIO4_17             IOMUX_PAD(0x5ec, 0x1fc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_I2C1_DAT__I2C1_DAT             (_MX51_PAD_I2C1_DAT__I2C1_DAT | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
+#define MX51_PAD_I2C1_DAT__I2C1_DAT             IOMUX_PAD(0x5ec, 0x1fc, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD          (_MX51_PAD_AUD3_BB_TXD__AUD3_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD          IOMUX_PAD(0x5f0, 0x200, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_TXD__GPIO4_18          (_MX51_PAD_AUD3_BB_TXD__GPIO4_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_AUD3_BB_TXD__GPIO4_18          IOMUX_PAD(0x5f0, 0x200, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD          (_MX51_PAD_AUD3_BB_RXD__AUD3_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD          IOMUX_PAD(0x5f4, 0x204, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_RXD__GPIO4_19          (_MX51_PAD_AUD3_BB_RXD__GPIO4_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_AUD3_BB_RXD__GPIO4_19          IOMUX_PAD(0x5f4, 0x204, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_RXD__UART3_RXD         (_MX51_PAD_AUD3_BB_RXD__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_AUD3_BB_RXD__UART3_RXD         IOMUX_PAD(0x5f4, 0x204, 1, 0x9f4, 2, MX51_UART_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_CK__AUD3_TXC           (_MX51_PAD_AUD3_BB_CK__AUD3_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_AUD3_BB_CK__AUD3_TXC           IOMUX_PAD(0x5f8, 0x208, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_CK__GPIO4_20           (_MX51_PAD_AUD3_BB_CK__GPIO4_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_AUD3_BB_CK__GPIO4_20           IOMUX_PAD(0x5f8, 0x208, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS          (_MX51_PAD_AUD3_BB_FS__AUD3_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS          IOMUX_PAD(0x5fc, 0x20c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_FS__GPIO4_21           (_MX51_PAD_AUD3_BB_FS__GPIO4_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_AUD3_BB_FS__GPIO4_21           IOMUX_PAD(0x5fc, 0x20c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_FS__UART3_TXD          (_MX51_PAD_AUD3_BB_FS__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_AUD3_BB_FS__UART3_TXD          IOMUX_PAD(0x5fc, 0x20c, 1, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI        (_MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI        IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_MOSI__GPIO4_22           (_MX51_PAD_CSPI1_MOSI__GPIO4_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSPI1_MOSI__GPIO4_22           IOMUX_PAD(0x600, 0x210, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSPI1_MOSI__I2C1_SDA           (_MX51_PAD_CSPI1_MOSI__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
+#define MX51_PAD_CSPI1_MOSI__I2C1_SDA           IOMUX_PAD(0x600, 0x210, 0x11, 0x9b4, 1, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_CSPI1_MISO__AUD4_RXD           (_MX51_PAD_CSPI1_MISO__AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSPI1_MISO__AUD4_RXD           IOMUX_PAD(0x604, 0x214, 1, 0x8c4, 1, NO_PAD_CTRL)
-#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO        (_MX51_PAD_CSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO        IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_MISO__GPIO4_23           (_MX51_PAD_CSPI1_MISO__GPIO4_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSPI1_MISO__GPIO4_23           IOMUX_PAD(0x604, 0x214, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS0__AUD4_TXC            (_MX51_PAD_CSPI1_SS0__AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSPI1_SS0__AUD4_TXC            IOMUX_PAD(0x608, 0x218, 1, 0x8cc, 1, NO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0          (_MX51_PAD_CSPI1_SS0__ECSPI1_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0          IOMUX_PAD(0x608, 0x218, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS0__GPIO4_24            (_MX51_PAD_CSPI1_SS0__GPIO4_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSPI1_SS0__GPIO4_24            IOMUX_PAD(0x608, 0x218, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS1__AUD4_TXD            (_MX51_PAD_CSPI1_SS1__AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSPI1_SS1__AUD4_TXD            IOMUX_PAD(0x60c, 0x21c, 1, 0x8c8, 1, NO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1          (_MX51_PAD_CSPI1_SS1__ECSPI1_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1          IOMUX_PAD(0x60c, 0x21c, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS1__GPIO4_25            (_MX51_PAD_CSPI1_SS1__GPIO4_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSPI1_SS1__GPIO4_25            IOMUX_PAD(0x60c, 0x21c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSPI1_RDY__AUD4_TXFS           (_MX51_PAD_CSPI1_RDY__AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSPI1_RDY__AUD4_TXFS           IOMUX_PAD(0x610, 0x220, 1, 0x8d0, 1, NO_PAD_CTRL)
-#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY          (_MX51_PAD_CSPI1_RDY__ECSPI1_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY          IOMUX_PAD(0x610, 0x220, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_RDY__GPIO4_26            (_MX51_PAD_CSPI1_RDY__GPIO4_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSPI1_RDY__GPIO4_26            IOMUX_PAD(0x610, 0x220, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK        (_MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK        IOMUX_PAD(0x614, 0x224, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_SCLK__GPIO4_27           (_MX51_PAD_CSPI1_SCLK__GPIO4_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSPI1_SCLK__GPIO4_27           IOMUX_PAD(0x614, 0x224, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SCLK__I2C1_SCL           (_MX51_PAD_CSPI1_SCLK__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
+#define MX51_PAD_CSPI1_SCLK__I2C1_SCL           IOMUX_PAD(0x614, 0x224, 0x11, 0x9b0, 1, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_UART1_RXD__GPIO4_28            (_MX51_PAD_UART1_RXD__GPIO4_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_UART1_RXD__GPIO4_28            IOMUX_PAD(0x618, 0x228, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART1_RXD__UART1_RXD           (_MX51_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_UART1_RXD__UART1_RXD           IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART1_TXD__GPIO4_29            (_MX51_PAD_UART1_TXD__GPIO4_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_UART1_TXD__GPIO4_29            IOMUX_PAD(0x61c, 0x22c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART1_TXD__PWM2_PWMO           (_MX51_PAD_UART1_TXD__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_UART1_TXD__PWM2_PWMO           IOMUX_PAD(0x61c, 0x22c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART1_TXD__UART1_TXD           (_MX51_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_UART1_TXD__UART1_TXD           IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART1_RTS__GPIO4_30            (_MX51_PAD_UART1_RTS__GPIO4_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_UART1_RTS__GPIO4_30            IOMUX_PAD(0x620, 0x230, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART1_RTS__UART1_RTS           (_MX51_PAD_UART1_RTS__UART1_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_UART1_RTS__UART1_RTS           IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART1_CTS__GPIO4_31            (_MX51_PAD_UART1_CTS__GPIO4_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_UART1_CTS__GPIO4_31            IOMUX_PAD(0x624, 0x234, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART1_CTS__UART1_CTS           (_MX51_PAD_UART1_CTS__UART1_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_UART1_CTS__UART1_CTS           IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART2_RXD__FIRI_TXD            (_MX51_PAD_UART2_RXD__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_UART2_RXD__FIRI_TXD            IOMUX_PAD(0x628, 0x238, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART2_RXD__GPIO1_20            (_MX51_PAD_UART2_RXD__GPIO1_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_UART2_RXD__GPIO1_20            IOMUX_PAD(0x628, 0x238, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART2_RXD__UART2_RXD           (_MX51_PAD_UART2_RXD__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_UART2_RXD__UART2_RXD           IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART2_TXD__FIRI_RXD            (_MX51_PAD_UART2_TXD__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_UART2_TXD__FIRI_RXD            IOMUX_PAD(0x62c, 0x23c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART2_TXD__GPIO1_21            (_MX51_PAD_UART2_TXD__GPIO1_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_UART2_TXD__GPIO1_21            IOMUX_PAD(0x62c, 0x23c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART2_TXD__UART2_TXD           (_MX51_PAD_UART2_TXD__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_UART2_TXD__UART2_TXD           IOMUX_PAD(0x62c, 0x23c, 0, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART3_RXD__CSI1_D0             (_MX51_PAD_UART3_RXD__CSI1_D0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_UART3_RXD__CSI1_D0             IOMUX_PAD(0x630, 0x240, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART3_RXD__GPIO1_22            (_MX51_PAD_UART3_RXD__GPIO1_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_UART3_RXD__GPIO1_22            IOMUX_PAD(0x630, 0x240, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART3_RXD__UART1_DTR           (_MX51_PAD_UART3_RXD__UART1_DTR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_UART3_RXD__UART1_DTR           IOMUX_PAD(0x630, 0x240, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART3_RXD__UART3_RXD           (_MX51_PAD_UART3_RXD__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_UART3_RXD__UART3_RXD           IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART3_TXD__CSI1_D1             (_MX51_PAD_UART3_TXD__CSI1_D1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_UART3_TXD__CSI1_D1             IOMUX_PAD(0x634, 0x244, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART3_TXD__GPIO1_23            (_MX51_PAD_UART3_TXD__GPIO1_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_UART3_TXD__GPIO1_23            IOMUX_PAD(0x634, 0x244, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART3_TXD__UART1_DSR           (_MX51_PAD_UART3_TXD__UART1_DSR | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_UART3_TXD__UART1_DSR           IOMUX_PAD(0x634, 0x244, 0, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART3_TXD__UART3_TXD           (_MX51_PAD_UART3_TXD__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_UART3_TXD__UART3_TXD           IOMUX_PAD(0x634, 0x244, 1, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_OWIRE_LINE__GPIO1_24           (_MX51_PAD_OWIRE_LINE__GPIO1_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_OWIRE_LINE__GPIO1_24           IOMUX_PAD(0x638, 0x248, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_OWIRE_LINE__OWIRE_LINE         (_MX51_PAD_OWIRE_LINE__OWIRE_LINE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_OWIRE_LINE__OWIRE_LINE         IOMUX_PAD(0x638, 0x248, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_OWIRE_LINE__SPDIF_OUT          (_MX51_PAD_OWIRE_LINE__SPDIF_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_OWIRE_LINE__SPDIF_OUT          IOMUX_PAD(0x638, 0x248, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW0__KEY_ROW0             (_MX51_PAD_KEY_ROW0__KEY_ROW0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_KEY_ROW0__KEY_ROW0             IOMUX_PAD(0x63c, 0x24c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW1__KEY_ROW1             (_MX51_PAD_KEY_ROW1__KEY_ROW1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_KEY_ROW1__KEY_ROW1             IOMUX_PAD(0x640, 0x250, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW2__KEY_ROW2             (_MX51_PAD_KEY_ROW2__KEY_ROW2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_KEY_ROW2__KEY_ROW2             IOMUX_PAD(0x644, 0x254, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW3__KEY_ROW3             (_MX51_PAD_KEY_ROW3__KEY_ROW3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_KEY_ROW3__KEY_ROW3             IOMUX_PAD(0x648, 0x258, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL0__KEY_COL0             (_MX51_PAD_KEY_COL0__KEY_COL0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_KEY_COL0__KEY_COL0             IOMUX_PAD(0x64c, 0x25c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL0__PLL1_BYP             (_MX51_PAD_KEY_COL0__PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_KEY_COL0__PLL1_BYP             IOMUX_PAD(0x64c, 0x25c, 7, 0x90c, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL1__KEY_COL1             (_MX51_PAD_KEY_COL1__KEY_COL1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_KEY_COL1__KEY_COL1             IOMUX_PAD(0x650, 0x260, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL1__PLL2_BYP             (_MX51_PAD_KEY_COL1__PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_KEY_COL1__PLL2_BYP             IOMUX_PAD(0x650, 0x260, 7, 0x910, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL2__KEY_COL2             (_MX51_PAD_KEY_COL2__KEY_COL2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_KEY_COL2__KEY_COL2             IOMUX_PAD(0x654, 0x264, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL2__PLL3_BYP             (_MX51_PAD_KEY_COL2__PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_KEY_COL2__PLL3_BYP             IOMUX_PAD(0x654, 0x264, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL3__KEY_COL3             (_MX51_PAD_KEY_COL3__KEY_COL3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_KEY_COL3__KEY_COL3             IOMUX_PAD(0x658, 0x268, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__I2C2_SCL             (_MX51_PAD_KEY_COL4__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
+#define MX51_PAD_KEY_COL4__I2C2_SCL             IOMUX_PAD(0x65c, 0x26c, 0x13, 0x9b8, 1, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__KEY_COL4             (_MX51_PAD_KEY_COL4__KEY_COL4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_KEY_COL4__KEY_COL4             IOMUX_PAD(0x65c, 0x26c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__SPDIF_OUT1           (_MX51_PAD_KEY_COL4__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_KEY_COL4__SPDIF_OUT1           IOMUX_PAD(0x65c, 0x26c, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__UART1_RI             (_MX51_PAD_KEY_COL4__UART1_RI | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_KEY_COL4__UART1_RI             IOMUX_PAD(0x65c, 0x26c, 1, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__UART3_RTS            (_MX51_PAD_KEY_COL4__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_KEY_COL4__UART3_RTS            IOMUX_PAD(0x65c, 0x26c, 2, 0x9f0, 4, MX51_UART_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__I2C2_SDA             (_MX51_PAD_KEY_COL5__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
+#define MX51_PAD_KEY_COL5__I2C2_SDA             IOMUX_PAD(0x660, 0x270, 0x13, 0x9bc, 1, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__KEY_COL5             (_MX51_PAD_KEY_COL5__KEY_COL5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_KEY_COL5__KEY_COL5             IOMUX_PAD(0x660, 0x270, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__UART1_DCD            (_MX51_PAD_KEY_COL5__UART1_DCD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_KEY_COL5__UART1_DCD            IOMUX_PAD(0x660, 0x270, 1, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__UART3_CTS            (_MX51_PAD_KEY_COL5__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_KEY_COL5__UART3_CTS            IOMUX_PAD(0x660, 0x270, 2, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_CLK__CSPI_SCLK           (_MX51_PAD_USBH1_CLK__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_USBH1_CLK__CSPI_SCLK           IOMUX_PAD(0x678, 0x278, 1, 0x914, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_CLK__GPIO1_25            (_MX51_PAD_USBH1_CLK__GPIO1_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_USBH1_CLK__GPIO1_25            IOMUX_PAD(0x678, 0x278, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_CLK__I2C2_SCL            (_MX51_PAD_USBH1_CLK__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
+#define MX51_PAD_USBH1_CLK__I2C2_SCL            IOMUX_PAD(0x678, 0x278, 0x15, 0x9b8, 2, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_USBH1_CLK__USBH1_CLK           (_MX51_PAD_USBH1_CLK__USBH1_CLK | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
+#define MX51_PAD_USBH1_CLK__USBH1_CLK           IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DIR__CSPI_MOSI           (_MX51_PAD_USBH1_DIR__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_USBH1_DIR__CSPI_MOSI           IOMUX_PAD(0x67c, 0x27c, 1, 0x91c, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_DIR__GPIO1_26            (_MX51_PAD_USBH1_DIR__GPIO1_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_USBH1_DIR__GPIO1_26            IOMUX_PAD(0x67c, 0x27c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DIR__I2C2_SDA            (_MX51_PAD_USBH1_DIR__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
+#define MX51_PAD_USBH1_DIR__I2C2_SDA            IOMUX_PAD(0x67c, 0x27c, 0x15, 0x9bc, 2, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_USBH1_DIR__USBH1_DIR           (_MX51_PAD_USBH1_DIR__USBH1_DIR | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
+#define MX51_PAD_USBH1_DIR__USBH1_DIR           IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__CSPI_RDY            (_MX51_PAD_USBH1_STP__CSPI_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_USBH1_STP__CSPI_RDY            IOMUX_PAD(0x680, 0x280, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__GPIO1_27            (_MX51_PAD_USBH1_STP__GPIO1_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_USBH1_STP__GPIO1_27            IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__UART3_RXD           (_MX51_PAD_USBH1_STP__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_USBH1_STP__UART3_RXD           IOMUX_PAD(0x680, 0x280, 5, 0x9f4, 6, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__USBH1_STP           (_MX51_PAD_USBH1_STP__USBH1_STP | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
+#define MX51_PAD_USBH1_STP__USBH1_STP           IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_NXT__CSPI_MISO           (_MX51_PAD_USBH1_NXT__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_USBH1_NXT__CSPI_MISO           IOMUX_PAD(0x684, 0x284, 1, 0x918, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_NXT__GPIO1_28            (_MX51_PAD_USBH1_NXT__GPIO1_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_USBH1_NXT__GPIO1_28            IOMUX_PAD(0x684, 0x284, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_NXT__UART3_TXD           (_MX51_PAD_USBH1_NXT__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_USBH1_NXT__UART3_TXD           IOMUX_PAD(0x684, 0x284, 5, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_NXT__USBH1_NXT           (_MX51_PAD_USBH1_NXT__USBH1_NXT | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
+#define MX51_PAD_USBH1_NXT__USBH1_NXT           IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA0__GPIO1_11          (_MX51_PAD_USBH1_DATA0__GPIO1_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA0__GPIO1_11          IOMUX_PAD(0x688, 0x288, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA0__UART2_CTS         (_MX51_PAD_USBH1_DATA0__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA0__UART2_CTS         IOMUX_PAD(0x688, 0x288, 1, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA0__USBH1_DATA0       (_MX51_PAD_USBH1_DATA0__USBH1_DATA0 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA0__USBH1_DATA0       IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA1__GPIO1_12          (_MX51_PAD_USBH1_DATA1__GPIO1_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA1__GPIO1_12          IOMUX_PAD(0x68c, 0x28c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA1__UART2_RXD         (_MX51_PAD_USBH1_DATA1__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA1__UART2_RXD         IOMUX_PAD(0x68c, 0x28c, 1, 0x9ec, 4, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA1__USBH1_DATA1       (_MX51_PAD_USBH1_DATA1__USBH1_DATA1 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA1__USBH1_DATA1       IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA2__GPIO1_13          (_MX51_PAD_USBH1_DATA2__GPIO1_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA2__GPIO1_13          IOMUX_PAD(0x690, 0x290, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA2__UART2_TXD         (_MX51_PAD_USBH1_DATA2__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA2__UART2_TXD         IOMUX_PAD(0x690, 0x290, 1, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA2__USBH1_DATA2       (_MX51_PAD_USBH1_DATA2__USBH1_DATA2 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA2__USBH1_DATA2       IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA3__GPIO1_14          (_MX51_PAD_USBH1_DATA3__GPIO1_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA3__GPIO1_14          IOMUX_PAD(0x694, 0x294, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA3__UART2_RTS         (_MX51_PAD_USBH1_DATA3__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA3__UART2_RTS         IOMUX_PAD(0x694, 0x294, 1, 0x9e8, 5, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA3__USBH1_DATA3       (_MX51_PAD_USBH1_DATA3__USBH1_DATA3 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA3__USBH1_DATA3       IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA4__CSPI_SS0          (_MX51_PAD_USBH1_DATA4__CSPI_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA4__CSPI_SS0          IOMUX_PAD(0x698, 0x298, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA4__GPIO1_15          (_MX51_PAD_USBH1_DATA4__GPIO1_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA4__GPIO1_15          IOMUX_PAD(0x698, 0x298, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA4__USBH1_DATA4       (_MX51_PAD_USBH1_DATA4__USBH1_DATA4 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA4__USBH1_DATA4       IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA5__CSPI_SS1          (_MX51_PAD_USBH1_DATA5__CSPI_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA5__CSPI_SS1          IOMUX_PAD(0x69c, 0x29c, 1, 0x920, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA5__GPIO1_16          (_MX51_PAD_USBH1_DATA5__GPIO1_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA5__GPIO1_16          IOMUX_PAD(0x69c, 0x29c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA5__USBH1_DATA5       (_MX51_PAD_USBH1_DATA5__USBH1_DATA5 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA5__USBH1_DATA5       IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA6__CSPI_SS3          (_MX51_PAD_USBH1_DATA6__CSPI_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA6__CSPI_SS3          IOMUX_PAD(0x6a0, 0x2a0, 1, 0x928, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA6__GPIO1_17          (_MX51_PAD_USBH1_DATA6__GPIO1_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA6__GPIO1_17          IOMUX_PAD(0x6a0, 0x2a0, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA6__USBH1_DATA6       (_MX51_PAD_USBH1_DATA6__USBH1_DATA6 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA6__USBH1_DATA6       IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3        (_MX51_PAD_USBH1_DATA7__ECSPI1_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3        IOMUX_PAD(0x6a4, 0x2a4, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3        (_MX51_PAD_USBH1_DATA7__ECSPI2_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3        IOMUX_PAD(0x6a4, 0x2a4, 5, 0x934, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA7__GPIO1_18          (_MX51_PAD_USBH1_DATA7__GPIO1_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA7__GPIO1_18          IOMUX_PAD(0x6a4, 0x2a4, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA7__USBH1_DATA7       (_MX51_PAD_USBH1_DATA7__USBH1_DATA7 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA7__USBH1_DATA7       IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_DI1_PIN11__DI1_PIN11           (_MX51_PAD_DI1_PIN11__DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI1_PIN11__DI1_PIN11           IOMUX_PAD(0x6a8, 0x2a8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN11__ECSPI1_SS2          (_MX51_PAD_DI1_PIN11__ECSPI1_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_DI1_PIN11__ECSPI1_SS2          IOMUX_PAD(0x6a8, 0x2a8, 7, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_DI1_PIN11__GPIO3_0             (_MX51_PAD_DI1_PIN11__GPIO3_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_DI1_PIN11__GPIO3_0             IOMUX_PAD(0x6a8, 0x2a8, 4, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN12__DI1_PIN12           (_MX51_PAD_DI1_PIN12__DI1_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI1_PIN12__DI1_PIN12           IOMUX_PAD(0x6ac, 0x2ac, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN12__GPIO3_1             (_MX51_PAD_DI1_PIN12__GPIO3_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_DI1_PIN12__GPIO3_1             IOMUX_PAD(0x6ac, 0x2ac, 4, 0x978, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN13__DI1_PIN13           (_MX51_PAD_DI1_PIN13__DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI1_PIN13__DI1_PIN13           IOMUX_PAD(0x6b0, 0x2b0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN13__GPIO3_2             (_MX51_PAD_DI1_PIN13__GPIO3_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_DI1_PIN13__GPIO3_2             IOMUX_PAD(0x6b0, 0x2b0, 4, 0x97c, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DI1_D0_CS__DI1_D0_CS           (_MX51_PAD_DI1_D0_CS__DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI1_D0_CS__DI1_D0_CS           IOMUX_PAD(0x6b4, 0x2b4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_D0_CS__GPIO3_3             (_MX51_PAD_DI1_D0_CS__GPIO3_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_DI1_D0_CS__GPIO3_3             IOMUX_PAD(0x6b4, 0x2b4, 4, 0x980, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DI1_D1_CS__DI1_D1_CS           (_MX51_PAD_DI1_D1_CS__DI1_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI1_D1_CS__DI1_D1_CS           IOMUX_PAD(0x6b8, 0x2b8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_D1_CS__DISP1_PIN14         (_MX51_PAD_DI1_D1_CS__DISP1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI1_D1_CS__DISP1_PIN14         IOMUX_PAD(0x6b8, 0x2b8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_D1_CS__DISP1_PIN5          (_MX51_PAD_DI1_D1_CS__DISP1_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI1_D1_CS__DISP1_PIN5          IOMUX_PAD(0x6b8, 0x2b8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_D1_CS__GPIO3_4             (_MX51_PAD_DI1_D1_CS__GPIO3_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_DI1_D1_CS__GPIO3_4             IOMUX_PAD(0x6b8, 0x2b8, 4, 0x984, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1     (_MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1     IOMUX_PAD(0x6bc, 0x2bc, 2, 0x9a4, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN (_MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN IOMUX_PAD(0x6bc, 0x2bc, 0, 0x9c4, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5        (_MX51_PAD_DISPB2_SER_DIN__GPIO3_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5        IOMUX_PAD(0x6bc, 0x2bc, 4, 0x988, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6     (_MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6     IOMUX_PAD(0x6c0, 0x2c0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO (_MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO IOMUX_PAD(0x6c0, 0x2c0, 0, 0x9c4, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6        (_MX51_PAD_DISPB2_SER_DIO__GPIO3_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6        IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17    (_MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17    IOMUX_PAD(0x6c4, 0x2c4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7     (_MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7     IOMUX_PAD(0x6c4, 0x2c4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK (_MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK IOMUX_PAD(0x6c4, 0x2c4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7        (_MX51_PAD_DISPB2_SER_CLK__GPIO3_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7        IOMUX_PAD(0x6c4, 0x2c4, 4, 0x990, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK   (_MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK   IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16     (_MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16     IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8      (_MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8      IOMUX_PAD(0x6c8, 0x2c8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS   (_MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS   IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS   (_MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS   IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__GPIO3_8         (_MX51_PAD_DISPB2_SER_RS__GPIO3_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_DISPB2_SER_RS__GPIO3_8         IOMUX_PAD(0x6c8, 0x2c8, 4, 0x994, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT0__DISP1_DAT0         (_MX51_PAD_DISP1_DAT0__DISP1_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT0__DISP1_DAT0         IOMUX_PAD(0x6cc, 0x2cc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT1__DISP1_DAT1         (_MX51_PAD_DISP1_DAT1__DISP1_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT1__DISP1_DAT1         IOMUX_PAD(0x6d0, 0x2d0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT2__DISP1_DAT2         (_MX51_PAD_DISP1_DAT2__DISP1_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT2__DISP1_DAT2         IOMUX_PAD(0x6d4, 0x2d4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT3__DISP1_DAT3         (_MX51_PAD_DISP1_DAT3__DISP1_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT3__DISP1_DAT3         IOMUX_PAD(0x6d8, 0x2d8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT4__DISP1_DAT4         (_MX51_PAD_DISP1_DAT4__DISP1_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT4__DISP1_DAT4         IOMUX_PAD(0x6dc, 0x2dc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT5__DISP1_DAT5         (_MX51_PAD_DISP1_DAT5__DISP1_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT5__DISP1_DAT5         IOMUX_PAD(0x6e0, 0x2e0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC       (_MX51_PAD_DISP1_DAT6__BOOT_USB_SRC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC       IOMUX_PAD(0x6e4, 0x2e4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT6__DISP1_DAT6         (_MX51_PAD_DISP1_DAT6__DISP1_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT6__DISP1_DAT6         IOMUX_PAD(0x6e4, 0x2e4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG    (_MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG    IOMUX_PAD(0x6e8, 0x2e8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT7__DISP1_DAT7         (_MX51_PAD_DISP1_DAT7__DISP1_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT7__DISP1_DAT7         IOMUX_PAD(0x6e8, 0x2e8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT8__BOOT_SRC0          (_MX51_PAD_DISP1_DAT8__BOOT_SRC0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT8__BOOT_SRC0          IOMUX_PAD(0x6ec, 0x2ec, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT8__DISP1_DAT8         (_MX51_PAD_DISP1_DAT8__DISP1_DAT8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT8__DISP1_DAT8         IOMUX_PAD(0x6ec, 0x2ec, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT9__BOOT_SRC1          (_MX51_PAD_DISP1_DAT9__BOOT_SRC1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT9__BOOT_SRC1          IOMUX_PAD(0x6f0, 0x2f0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT9__DISP1_DAT9         (_MX51_PAD_DISP1_DAT9__DISP1_DAT9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT9__DISP1_DAT9         IOMUX_PAD(0x6f0, 0x2f0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE   (_MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE   IOMUX_PAD(0x6f4, 0x2f4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT10__DISP1_DAT10       (_MX51_PAD_DISP1_DAT10__DISP1_DAT10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT10__DISP1_DAT10       IOMUX_PAD(0x6f4, 0x2f4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2    (_MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2    IOMUX_PAD(0x6f8, 0x2f8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT11__DISP1_DAT11       (_MX51_PAD_DISP1_DAT11__DISP1_DAT11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT11__DISP1_DAT11       IOMUX_PAD(0x6f8, 0x2f8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL      (_MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL      IOMUX_PAD(0x6fc, 0x2fc, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT12__DISP1_DAT12       (_MX51_PAD_DISP1_DAT12__DISP1_DAT12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT12__DISP1_DAT12       IOMUX_PAD(0x6fc, 0x2fc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0     (_MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0     IOMUX_PAD(0x700, 0x300, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT13__DISP1_DAT13       (_MX51_PAD_DISP1_DAT13__DISP1_DAT13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT13__DISP1_DAT13       IOMUX_PAD(0x700, 0x300, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1     (_MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1     IOMUX_PAD(0x704, 0x304, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT14__DISP1_DAT14       (_MX51_PAD_DISP1_DAT14__DISP1_DAT14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT14__DISP1_DAT14       IOMUX_PAD(0x704, 0x304, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH    (_MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH    IOMUX_PAD(0x708, 0x308, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT15__DISP1_DAT15       (_MX51_PAD_DISP1_DAT15__DISP1_DAT15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT15__DISP1_DAT15       IOMUX_PAD(0x708, 0x308, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0   (_MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0   IOMUX_PAD(0x70c, 0x30c, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT16__DISP1_DAT16       (_MX51_PAD_DISP1_DAT16__DISP1_DAT16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT16__DISP1_DAT16       IOMUX_PAD(0x70c, 0x30c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1   (_MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1   IOMUX_PAD(0x710, 0x310, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT17__DISP1_DAT17       (_MX51_PAD_DISP1_DAT17__DISP1_DAT17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT17__DISP1_DAT17       IOMUX_PAD(0x710, 0x310, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0  (_MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0  IOMUX_PAD(0x714, 0x314, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT18__DISP1_DAT18       (_MX51_PAD_DISP1_DAT18__DISP1_DAT18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT18__DISP1_DAT18       IOMUX_PAD(0x714, 0x314, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT18__DISP2_PIN11       (_MX51_PAD_DISP1_DAT18__DISP2_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT18__DISP2_PIN11       IOMUX_PAD(0x714, 0x314, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT18__DISP2_PIN5        (_MX51_PAD_DISP1_DAT18__DISP2_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT18__DISP2_PIN5        IOMUX_PAD(0x714, 0x314, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1  (_MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1  IOMUX_PAD(0x718, 0x318, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT19__DISP1_DAT19       (_MX51_PAD_DISP1_DAT19__DISP1_DAT19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT19__DISP1_DAT19       IOMUX_PAD(0x718, 0x318, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT19__DISP2_PIN12       (_MX51_PAD_DISP1_DAT19__DISP2_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT19__DISP2_PIN12       IOMUX_PAD(0x718, 0x318, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT19__DISP2_PIN6        (_MX51_PAD_DISP1_DAT19__DISP2_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT19__DISP2_PIN6        IOMUX_PAD(0x718, 0x318, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0    (_MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0    IOMUX_PAD(0x71c, 0x31c, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT20__DISP1_DAT20       (_MX51_PAD_DISP1_DAT20__DISP1_DAT20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT20__DISP1_DAT20       IOMUX_PAD(0x71c, 0x31c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT20__DISP2_PIN13       (_MX51_PAD_DISP1_DAT20__DISP2_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT20__DISP2_PIN13       IOMUX_PAD(0x71c, 0x31c, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT20__DISP2_PIN7        (_MX51_PAD_DISP1_DAT20__DISP2_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT20__DISP2_PIN7        IOMUX_PAD(0x71c, 0x31c, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1    (_MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1    IOMUX_PAD(0x720, 0x320, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT21__DISP1_DAT21       (_MX51_PAD_DISP1_DAT21__DISP1_DAT21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT21__DISP1_DAT21       IOMUX_PAD(0x720, 0x320, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT21__DISP2_PIN14       (_MX51_PAD_DISP1_DAT21__DISP2_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT21__DISP2_PIN14       IOMUX_PAD(0x720, 0x320, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT21__DISP2_PIN8        (_MX51_PAD_DISP1_DAT21__DISP2_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT21__DISP2_PIN8        IOMUX_PAD(0x720, 0x320, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0    (_MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0    IOMUX_PAD(0x724, 0x324, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT22__DISP1_DAT22       (_MX51_PAD_DISP1_DAT22__DISP1_DAT22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT22__DISP1_DAT22       IOMUX_PAD(0x724, 0x324, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS       (_MX51_PAD_DISP1_DAT22__DISP2_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS       IOMUX_PAD(0x724, 0x324, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT22__DISP2_DAT16       (_MX51_PAD_DISP1_DAT22__DISP2_DAT16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT22__DISP2_DAT16       IOMUX_PAD(0x724, 0x324, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1    (_MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1    IOMUX_PAD(0x728, 0x328, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__DISP1_DAT23       (_MX51_PAD_DISP1_DAT23__DISP1_DAT23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT23__DISP1_DAT23       IOMUX_PAD(0x728, 0x328, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS       (_MX51_PAD_DISP1_DAT23__DISP2_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS       IOMUX_PAD(0x728, 0x328, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__DISP2_DAT17       (_MX51_PAD_DISP1_DAT23__DISP2_DAT17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT23__DISP2_DAT17       IOMUX_PAD(0x728, 0x328, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS      (_MX51_PAD_DISP1_DAT23__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS      IOMUX_PAD(0x728, 0x328, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN3__DI1_PIN3             (_MX51_PAD_DI1_PIN3__DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI1_PIN3__DI1_PIN3             IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN2__DI1_PIN2             (_MX51_PAD_DI1_PIN2__DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI1_PIN2__DI1_PIN2             IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP2__DISP1_SER_CLK          (_MX51_PAD_DI_GP2__DISP1_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI_GP2__DISP1_SER_CLK          IOMUX_PAD(0x740, 0x338, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP2__DISP2_WAIT             (_MX51_PAD_DI_GP2__DISP2_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI_GP2__DISP2_WAIT             IOMUX_PAD(0x740, 0x338, 2, 0x9a8, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP3__CSI1_DATA_EN           (_MX51_PAD_DI_GP3__CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI_GP3__CSI1_DATA_EN           IOMUX_PAD(0x744, 0x33c, 3, 0x9a0, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP3__DISP1_SER_DIO          (_MX51_PAD_DI_GP3__DISP1_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI_GP3__DISP1_SER_DIO          IOMUX_PAD(0x744, 0x33c, 0, 0x9c0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP3__FEC_TX_ER              (_MX51_PAD_DI_GP3__FEC_TX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
+#define MX51_PAD_DI_GP3__FEC_TX_ER              IOMUX_PAD(0x744, 0x33c, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN         (_MX51_PAD_DI2_PIN4__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN         IOMUX_PAD(0x748, 0x340, 3, 0x99c, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN4__DI2_PIN4             (_MX51_PAD_DI2_PIN4__DI2_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI2_PIN4__DI2_PIN4             IOMUX_PAD(0x748, 0x340, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN4__FEC_CRS              (_MX51_PAD_DI2_PIN4__FEC_CRS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI2_PIN4__FEC_CRS              IOMUX_PAD(0x748, 0x340, 2, 0x950, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN2__DI2_PIN2             (_MX51_PAD_DI2_PIN2__DI2_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI2_PIN2__DI2_PIN2             IOMUX_PAD(0x74c, 0x344, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN2__FEC_MDC              (_MX51_PAD_DI2_PIN2__FEC_MDC | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
+#define MX51_PAD_DI2_PIN2__FEC_MDC              IOMUX_PAD(0x74c, 0x344, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DI2_PIN3__DI2_PIN3             (_MX51_PAD_DI2_PIN3__DI2_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI2_PIN3__DI2_PIN3             IOMUX_PAD(0x750, 0x348, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN3__FEC_MDIO             (_MX51_PAD_DI2_PIN3__FEC_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI2_PIN3__FEC_MDIO             IOMUX_PAD(0x750, 0x348, 2, 0x954, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK     (_MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK     IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1       (_MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1       IOMUX_PAD(0x754, 0x34c, 2, 0x95c, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP4__DI2_PIN15              (_MX51_PAD_DI_GP4__DI2_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI_GP4__DI2_PIN15              IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP4__DISP1_SER_DIN          (_MX51_PAD_DI_GP4__DISP1_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI_GP4__DISP1_SER_DIN          IOMUX_PAD(0x758, 0x350, 0, 0x9c0, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP4__DISP2_PIN1             (_MX51_PAD_DI_GP4__DISP2_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI_GP4__DISP2_PIN1             IOMUX_PAD(0x758, 0x350, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP4__FEC_RDATA2             (_MX51_PAD_DI_GP4__FEC_RDATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI_GP4__FEC_RDATA2             IOMUX_PAD(0x758, 0x350, 2, 0x960, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__DISP2_DAT0         (_MX51_PAD_DISP2_DAT0__DISP2_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT0__DISP2_DAT0         IOMUX_PAD(0x75c, 0x354, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__FEC_RDATA3         (_MX51_PAD_DISP2_DAT0__FEC_RDATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT0__FEC_RDATA3         IOMUX_PAD(0x75c, 0x354, 2, 0x964, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__KEY_COL6           (_MX51_PAD_DISP2_DAT0__KEY_COL6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT0__KEY_COL6           IOMUX_PAD(0x75c, 0x354, 4, 0x9c8, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__UART3_RXD          (_MX51_PAD_DISP2_DAT0__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT0__UART3_RXD          IOMUX_PAD(0x75c, 0x354, 5, 0x9f4, 8, MX51_UART_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__USBH3_CLK          (_MX51_PAD_DISP2_DAT0__USBH3_CLK | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT0__USBH3_CLK          IOMUX_PAD(0x75c, 0x354, 3, 0x9f8, 1, MX51_UART_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__DISP2_DAT1         (_MX51_PAD_DISP2_DAT1__DISP2_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT1__DISP2_DAT1         IOMUX_PAD(0x760, 0x358, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__FEC_RX_ER          (_MX51_PAD_DISP2_DAT1__FEC_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT1__FEC_RX_ER          IOMUX_PAD(0x760, 0x358, 2, 0x970, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__KEY_COL7           (_MX51_PAD_DISP2_DAT1__KEY_COL7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT1__KEY_COL7           IOMUX_PAD(0x760, 0x358, 4, 0x9cc, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__UART3_TXD          (_MX51_PAD_DISP2_DAT1__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT1__UART3_TXD          IOMUX_PAD(0x760, 0x358, 5, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__USBH3_DIR          (_MX51_PAD_DISP2_DAT1__USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT1__USBH3_DIR          IOMUX_PAD(0x760, 0x358, 3, 0xa1c, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT2__DISP2_DAT2         (_MX51_PAD_DISP2_DAT2__DISP2_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT2__DISP2_DAT2         IOMUX_PAD(0x764, 0x35c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT3__DISP2_DAT3         (_MX51_PAD_DISP2_DAT3__DISP2_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT3__DISP2_DAT3         IOMUX_PAD(0x768, 0x360, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT4__DISP2_DAT4         (_MX51_PAD_DISP2_DAT4__DISP2_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT4__DISP2_DAT4         IOMUX_PAD(0x76c, 0x364, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT5__DISP2_DAT5         (_MX51_PAD_DISP2_DAT5__DISP2_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT5__DISP2_DAT5         IOMUX_PAD(0x770, 0x368, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT6__DISP2_DAT6         (_MX51_PAD_DISP2_DAT6__DISP2_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT6__DISP2_DAT6         IOMUX_PAD(0x774, 0x36c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT6__FEC_TDATA1         (_MX51_PAD_DISP2_DAT6__FEC_TDATA1 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
+#define MX51_PAD_DISP2_DAT6__FEC_TDATA1         IOMUX_PAD(0x774, 0x36c, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DISP2_DAT6__GPIO1_19           (_MX51_PAD_DISP2_DAT6__GPIO1_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT6__GPIO1_19           IOMUX_PAD(0x774, 0x36c, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT6__KEY_ROW4           (_MX51_PAD_DISP2_DAT6__KEY_ROW4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT6__KEY_ROW4           IOMUX_PAD(0x774, 0x36c, 4, 0x9d0, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT6__USBH3_STP          (_MX51_PAD_DISP2_DAT6__USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT6__USBH3_STP          IOMUX_PAD(0x774, 0x36c, 3, 0xa24, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT7__DISP2_DAT7         (_MX51_PAD_DISP2_DAT7__DISP2_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT7__DISP2_DAT7         IOMUX_PAD(0x778, 0x370, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT7__FEC_TDATA2         (_MX51_PAD_DISP2_DAT7__FEC_TDATA2 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
+#define MX51_PAD_DISP2_DAT7__FEC_TDATA2         IOMUX_PAD(0x778, 0x370, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DISP2_DAT7__GPIO1_29           (_MX51_PAD_DISP2_DAT7__GPIO1_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT7__GPIO1_29           IOMUX_PAD(0x778, 0x370, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT7__KEY_ROW5           (_MX51_PAD_DISP2_DAT7__KEY_ROW5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT7__KEY_ROW5           IOMUX_PAD(0x778, 0x370, 4, 0x9d4, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT7__USBH3_NXT          (_MX51_PAD_DISP2_DAT7__USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT7__USBH3_NXT          IOMUX_PAD(0x778, 0x370, 3, 0xa20, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT8__DISP2_DAT8         (_MX51_PAD_DISP2_DAT8__DISP2_DAT8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT8__DISP2_DAT8         IOMUX_PAD(0x77c, 0x374, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT8__FEC_TDATA3         (_MX51_PAD_DISP2_DAT8__FEC_TDATA3 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
+#define MX51_PAD_DISP2_DAT8__FEC_TDATA3         IOMUX_PAD(0x77c, 0x374, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DISP2_DAT8__GPIO1_30           (_MX51_PAD_DISP2_DAT8__GPIO1_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT8__GPIO1_30           IOMUX_PAD(0x77c, 0x374, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT8__KEY_ROW6           (_MX51_PAD_DISP2_DAT8__KEY_ROW6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT8__KEY_ROW6           IOMUX_PAD(0x77c, 0x374, 4, 0x9d8, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT8__USBH3_DATA0        (_MX51_PAD_DISP2_DAT8__USBH3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT8__USBH3_DATA0        IOMUX_PAD(0x77c, 0x374, 3, 0x9fc, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT9__AUD6_RXC           (_MX51_PAD_DISP2_DAT9__AUD6_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT9__AUD6_RXC           IOMUX_PAD(0x780, 0x378, 4, 0x8f4, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT9__DISP2_DAT9         (_MX51_PAD_DISP2_DAT9__DISP2_DAT9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT9__DISP2_DAT9         IOMUX_PAD(0x780, 0x378, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT9__FEC_TX_EN          (_MX51_PAD_DISP2_DAT9__FEC_TX_EN | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
+#define MX51_PAD_DISP2_DAT9__FEC_TX_EN          IOMUX_PAD(0x780, 0x378, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DISP2_DAT9__GPIO1_31           (_MX51_PAD_DISP2_DAT9__GPIO1_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT9__GPIO1_31           IOMUX_PAD(0x780, 0x378, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT9__USBH3_DATA1        (_MX51_PAD_DISP2_DAT9__USBH3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT9__USBH3_DATA1        IOMUX_PAD(0x780, 0x378, 3, 0xa00, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__DISP2_DAT10       (_MX51_PAD_DISP2_DAT10__DISP2_DAT10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT10__DISP2_DAT10       IOMUX_PAD(0x784, 0x37c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS      (_MX51_PAD_DISP2_DAT10__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS      IOMUX_PAD(0x784, 0x37c, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__FEC_COL           (_MX51_PAD_DISP2_DAT10__FEC_COL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT10__FEC_COL           IOMUX_PAD(0x784, 0x37c, 2, 0x94c, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__KEY_ROW7          (_MX51_PAD_DISP2_DAT10__KEY_ROW7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT10__KEY_ROW7          IOMUX_PAD(0x784, 0x37c, 4, 0x9dc, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__USBH3_DATA2       (_MX51_PAD_DISP2_DAT10__USBH3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT10__USBH3_DATA2       IOMUX_PAD(0x784, 0x37c, 3, 0xa04, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__AUD6_TXD          (_MX51_PAD_DISP2_DAT11__AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT11__AUD6_TXD          IOMUX_PAD(0x788, 0x380, 4, 0x8f0, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__DISP2_DAT11       (_MX51_PAD_DISP2_DAT11__DISP2_DAT11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT11__DISP2_DAT11       IOMUX_PAD(0x788, 0x380, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK        (_MX51_PAD_DISP2_DAT11__FEC_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK        IOMUX_PAD(0x788, 0x380, 2, 0x968, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__GPIO1_10          (_MX51_PAD_DISP2_DAT11__GPIO1_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT11__GPIO1_10          IOMUX_PAD(0x788, 0x380, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__USBH3_DATA3       (_MX51_PAD_DISP2_DAT11__USBH3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT11__USBH3_DATA3       IOMUX_PAD(0x788, 0x380, 3, 0xa08, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT12__AUD6_RXD          (_MX51_PAD_DISP2_DAT12__AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT12__AUD6_RXD          IOMUX_PAD(0x78c, 0x384, 4, 0x8ec, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT12__DISP2_DAT12       (_MX51_PAD_DISP2_DAT12__DISP2_DAT12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT12__DISP2_DAT12       IOMUX_PAD(0x78c, 0x384, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT12__FEC_RX_DV         (_MX51_PAD_DISP2_DAT12__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT12__FEC_RX_DV         IOMUX_PAD(0x78c, 0x384, 2, 0x96c, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT12__USBH3_DATA4       (_MX51_PAD_DISP2_DAT12__USBH3_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT12__USBH3_DATA4       IOMUX_PAD(0x78c, 0x384, 3, 0xa0c, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT13__AUD6_TXC          (_MX51_PAD_DISP2_DAT13__AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT13__AUD6_TXC          IOMUX_PAD(0x790, 0x388, 4, 0x8fc, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT13__DISP2_DAT13       (_MX51_PAD_DISP2_DAT13__DISP2_DAT13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT13__DISP2_DAT13       IOMUX_PAD(0x790, 0x388, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK        (_MX51_PAD_DISP2_DAT13__FEC_TX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_4))
+#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK        IOMUX_PAD(0x790, 0x388, 2, 0x974, 1, MX51_PAD_CTRL_4)
-#define MX51_PAD_DISP2_DAT13__USBH3_DATA5       (_MX51_PAD_DISP2_DAT13__USBH3_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT13__USBH3_DATA5       IOMUX_PAD(0x790, 0x388, 3, 0xa10, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT14__AUD6_TXFS         (_MX51_PAD_DISP2_DAT14__AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT14__AUD6_TXFS         IOMUX_PAD(0x794, 0x38c, 4, 0x900, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT14__DISP2_DAT14       (_MX51_PAD_DISP2_DAT14__DISP2_DAT14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT14__DISP2_DAT14       IOMUX_PAD(0x794, 0x38c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT14__FEC_RDATA0        (_MX51_PAD_DISP2_DAT14__FEC_RDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_4))
+#define MX51_PAD_DISP2_DAT14__FEC_RDATA0        IOMUX_PAD(0x794, 0x38c, 2, 0x958, 1, MX51_PAD_CTRL_4)
-#define MX51_PAD_DISP2_DAT14__USBH3_DATA6       (_MX51_PAD_DISP2_DAT14__USBH3_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT14__USBH3_DATA6       IOMUX_PAD(0x794, 0x38c, 3, 0xa14, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT15__AUD6_RXFS         (_MX51_PAD_DISP2_DAT15__AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT15__AUD6_RXFS         IOMUX_PAD(0x798, 0x390, 4, 0x8f8, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS      (_MX51_PAD_DISP2_DAT15__DISP1_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS      IOMUX_PAD(0x798, 0x390, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT15__DISP2_DAT15       (_MX51_PAD_DISP2_DAT15__DISP2_DAT15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT15__DISP2_DAT15       IOMUX_PAD(0x798, 0x390, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT15__FEC_TDATA0        (_MX51_PAD_DISP2_DAT15__FEC_TDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
+#define MX51_PAD_DISP2_DAT15__FEC_TDATA0        IOMUX_PAD(0x798, 0x390, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DISP2_DAT15__USBH3_DATA7       (_MX51_PAD_DISP2_DAT15__USBH3_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT15__USBH3_DATA7       IOMUX_PAD(0x798, 0x390, 3, 0xa18, 1, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CMD__AUD5_RXFS             (_MX51_PAD_SD1_CMD__AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD1_CMD__AUD5_RXFS             IOMUX_PAD(0x79c, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CMD__CSPI_MOSI             (_MX51_PAD_SD1_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD1_CMD__CSPI_MOSI             IOMUX_PAD(0x79c, 0x394, 2, 0x91c, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CMD__SD1_CMD               (_MX51_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
+#define MX51_PAD_SD1_CMD__SD1_CMD               IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD1_CLK__AUD5_RXC              (_MX51_PAD_SD1_CLK__AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD1_CLK__AUD5_RXC              IOMUX_PAD(0x7a0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CLK__CSPI_SCLK             (_MX51_PAD_SD1_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD1_CLK__CSPI_SCLK             IOMUX_PAD(0x7a0, 0x398, 2, 0x914, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CLK__SD1_CLK               (_MX51_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS))
+#define MX51_PAD_SD1_CLK__SD1_CLK               IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
-#define MX51_PAD_SD1_DATA0__AUD5_TXD            (_MX51_PAD_SD1_DATA0__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD1_DATA0__AUD5_TXD            IOMUX_PAD(0x7a4, 0x39c, 1, 0x8d8, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA0__CSPI_MISO           (_MX51_PAD_SD1_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_SD1_DATA0__CSPI_MISO           IOMUX_PAD(0x7a4, 0x39c, 2, 0x918, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_SD1_DATA0__SD1_DATA0           (_MX51_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
+#define MX51_PAD_SD1_DATA0__SD1_DATA0           IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_EIM_DA0__EIM_DA0               (_MX51_PAD_EIM_DA0__EIM_DA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DA0__EIM_DA0               IOMUX_PAD(__NA_, 0x01c, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA1__EIM_DA1               (_MX51_PAD_EIM_DA1__EIM_DA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DA1__EIM_DA1               IOMUX_PAD(__NA_, 0x020, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA2__EIM_DA2               (_MX51_PAD_EIM_DA2__EIM_DA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DA2__EIM_DA2               IOMUX_PAD(__NA_, 0x024, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA3__EIM_DA3               (_MX51_PAD_EIM_DA3__EIM_DA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DA3__EIM_DA3               IOMUX_PAD(__NA_, 0x028, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA1__AUD5_RXD            (_MX51_PAD_SD1_DATA1__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD1_DATA1__AUD5_RXD            IOMUX_PAD(0x7a8, 0x3a0, 1, 0x8d4, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA1__SD1_DATA1           (_MX51_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
+#define MX51_PAD_SD1_DATA1__SD1_DATA1           IOMUX_PAD(0x7a8, 0x3a0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_EIM_DA4__EIM_DA4               (_MX51_PAD_EIM_DA4__EIM_DA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DA4__EIM_DA4               IOMUX_PAD(__NA_, 0x02c, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA5__EIM_DA5               (_MX51_PAD_EIM_DA5__EIM_DA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DA5__EIM_DA5               IOMUX_PAD(__NA_, 0x030, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA6__EIM_DA6               (_MX51_PAD_EIM_DA6__EIM_DA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DA6__EIM_DA6               IOMUX_PAD(__NA_, 0x034, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA7__EIM_DA7               (_MX51_PAD_EIM_DA7__EIM_DA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DA7__EIM_DA7               IOMUX_PAD(__NA_, 0x038, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA2__AUD5_TXC            (_MX51_PAD_SD1_DATA2__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD1_DATA2__AUD5_TXC            IOMUX_PAD(0x7ac, 0x3a4, 1, 0x8e4, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA2__SD1_DATA2           (_MX51_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
+#define MX51_PAD_SD1_DATA2__SD1_DATA2           IOMUX_PAD(0x7ac, 0x3a4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_EIM_DA10__EIM_DA10             (_MX51_PAD_EIM_DA10__EIM_DA10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DA10__EIM_DA10             IOMUX_PAD(__NA_, 0x044, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA11__EIM_DA11             (_MX51_PAD_EIM_DA11__EIM_DA11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DA11__EIM_DA11             IOMUX_PAD(__NA_, 0x048, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA8__EIM_DA8               (_MX51_PAD_EIM_DA8__EIM_DA8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DA8__EIM_DA8               IOMUX_PAD(__NA_, 0x03c, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA9__EIM_DA9               (_MX51_PAD_EIM_DA9__EIM_DA9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DA9__EIM_DA9               IOMUX_PAD(__NA_, 0x040, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA3__AUD5_TXFS           (_MX51_PAD_SD1_DATA3__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD1_DATA3__AUD5_TXFS           IOMUX_PAD(0x7b0, 0x3a8, 1, 0x8e8, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA3__CSPI_SS1            (_MX51_PAD_SD1_DATA3__CSPI_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_SD1_DATA3__CSPI_SS1            IOMUX_PAD(0x7b0, 0x3a8, 2, 0x920, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_SD1_DATA3__SD1_DATA3           (_MX51_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
+#define MX51_PAD_SD1_DATA3__SD1_DATA3           IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_GPIO1_0__CSPI_SS2              (_MX51_PAD_GPIO1_0__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_GPIO1_0__CSPI_SS2              IOMUX_PAD(0x7b4, 0x3ac, 2, 0x924, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_GPIO1_0__GPIO1_0               (_MX51_PAD_GPIO1_0__GPIO1_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_0__GPIO1_0               IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_0__SD1_CD                (_MX51_PAD_GPIO1_0__SD1_CD | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL))
+#define MX51_PAD_GPIO1_0__SD1_CD                IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL)
-#define MX51_PAD_GPIO1_1__CSPI_MISO             (_MX51_PAD_GPIO1_1__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_GPIO1_1__CSPI_MISO             IOMUX_PAD(0x7b8, 0x3b0, 2, 0x918, 2, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_GPIO1_1__GPIO1_1               (_MX51_PAD_GPIO1_1__GPIO1_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_1__GPIO1_1               IOMUX_PAD(0x7b8, 0x3b0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_1__SD1_WP                (_MX51_PAD_GPIO1_1__SD1_WP | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL))
+#define MX51_PAD_GPIO1_1__SD1_WP                IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL)
-#define MX51_PAD_EIM_DA12__EIM_DA12             (_MX51_PAD_EIM_DA12__EIM_DA12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DA12__EIM_DA12             IOMUX_PAD(__NA_, 0x04c, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA13__EIM_DA13             (_MX51_PAD_EIM_DA13__EIM_DA13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DA13__EIM_DA13             IOMUX_PAD(__NA_, 0x050, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA14__EIM_DA14             (_MX51_PAD_EIM_DA14__EIM_DA14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DA14__EIM_DA14             IOMUX_PAD(__NA_, 0x054, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA15__EIM_DA15             (_MX51_PAD_EIM_DA15__EIM_DA15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DA15__EIM_DA15             IOMUX_PAD(__NA_, 0x058, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_CMD__CSPI_MOSI             (_MX51_PAD_SD2_CMD__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_SD2_CMD__CSPI_MOSI             IOMUX_PAD(__NA_, 0x3b4, 2, 0x91c, 3, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_SD2_CMD__I2C1_SCL              (_MX51_PAD_SD2_CMD__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
+#define MX51_PAD_SD2_CMD__I2C1_SCL              IOMUX_PAD(0x7bc, 0x3b4, 0x11, 0x9b0, 2, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_SD2_CMD__SD2_CMD               (_MX51_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
+#define MX51_PAD_SD2_CMD__SD2_CMD               IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD2_CLK__CSPI_SCLK             (_MX51_PAD_SD2_CLK__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_SD2_CLK__CSPI_SCLK             IOMUX_PAD(0x7c0, 0x3b8, 2, 0x914, 3, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_SD2_CLK__I2C1_SDA              (_MX51_PAD_SD2_CLK__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
+#define MX51_PAD_SD2_CLK__I2C1_SDA              IOMUX_PAD(0x7c0, 0x3b8, 0x11, 0x9b4, 2, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_SD2_CLK__SD2_CLK               (_MX51_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS))
+#define MX51_PAD_SD2_CLK__SD2_CLK               IOMUX_PAD(0x7c0, 0x3b8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
-#define MX51_PAD_SD2_DATA0__CSPI_MISO           (_MX51_PAD_SD2_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_SD2_DATA0__CSPI_MISO           IOMUX_PAD(0x7c4, 0x3bc, 2, 0x918, 3, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA0__SD1_DAT4            (_MX51_PAD_SD2_DATA0__SD1_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD2_DATA0__SD1_DAT4            IOMUX_PAD(0x7c4, 0x3bc, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA0__SD2_DATA0           (_MX51_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
+#define MX51_PAD_SD2_DATA0__SD2_DATA0           IOMUX_PAD(0x7c4, 0x3bc, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA1__SD1_DAT5            (_MX51_PAD_SD2_DATA1__SD1_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD2_DATA1__SD1_DAT5            IOMUX_PAD(0x7c8, 0x3c0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA1__SD2_DATA1           (_MX51_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
+#define MX51_PAD_SD2_DATA1__SD2_DATA1           IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA1__USBH3_H2_DP         (_MX51_PAD_SD2_DATA1__USBH3_H2_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD2_DATA1__USBH3_H2_DP         IOMUX_PAD(0x7c8, 0x3c0, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA2__SD1_DAT6            (_MX51_PAD_SD2_DATA2__SD1_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD2_DATA2__SD1_DAT6            IOMUX_PAD(0x7cc, 0x3c4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA2__SD2_DATA2           (_MX51_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
+#define MX51_PAD_SD2_DATA2__SD2_DATA2           IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA2__USBH3_H2_DM         (_MX51_PAD_SD2_DATA2__USBH3_H2_DM | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD2_DATA2__USBH3_H2_DM         IOMUX_PAD(0x7cc, 0x3c4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA3__CSPI_SS2            (_MX51_PAD_SD2_DATA3__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_SD2_DATA3__CSPI_SS2            IOMUX_PAD(0x7d0, 0x3c8, 2, 0x924, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA3__SD1_DAT7            (_MX51_PAD_SD2_DATA3__SD1_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD2_DATA3__SD1_DAT7            IOMUX_PAD(0x7d0, 0x3c8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA3__SD2_DATA3           (_MX51_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
+#define MX51_PAD_SD2_DATA3__SD2_DATA3           IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_GPIO1_2__CCM_OUT_2             (_MX51_PAD_GPIO1_2__CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_2__CCM_OUT_2             IOMUX_PAD(0x7d4, 0x3cc, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_2__GPIO1_2               (_MX51_PAD_GPIO1_2__GPIO1_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_2__GPIO1_2               IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_2__I2C2_SCL              (_MX51_PAD_GPIO1_2__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
+#define MX51_PAD_GPIO1_2__I2C2_SCL              IOMUX_PAD(0x7d4, 0x3cc, 0x12, 0x9b8, 3, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_GPIO1_2__PLL1_BYP              (_MX51_PAD_GPIO1_2__PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_2__PLL1_BYP              IOMUX_PAD(0x7d4, 0x3cc, 7, 0x90c, 1, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_2__PWM1_PWMO             (_MX51_PAD_GPIO1_2__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_2__PWM1_PWMO             IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_3__GPIO1_3               (_MX51_PAD_GPIO1_3__GPIO1_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_3__GPIO1_3               IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_3__I2C2_SDA              (_MX51_PAD_GPIO1_3__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
+#define MX51_PAD_GPIO1_3__I2C2_SDA              IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_GPIO1_3__PLL2_BYP              (_MX51_PAD_GPIO1_3__PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_3__PLL2_BYP              IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_3__PWM2_PWMO             (_MX51_PAD_GPIO1_3__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_3__PWM2_PWMO             IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ     (_MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ     IOMUX_PAD(0x7fc, 0x3d4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B   (_MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B   IOMUX_PAD(0x7fc, 0x3d4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK         (_MX51_PAD_GPIO1_4__DISP2_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK         IOMUX_PAD(0x804, 0x3d8, 4, 0x908, 1, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_4__EIM_RDY               (_MX51_PAD_GPIO1_4__EIM_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_4__EIM_RDY               IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_4__GPIO1_4               (_MX51_PAD_GPIO1_4__GPIO1_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_4__GPIO1_4               IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B          (_MX51_PAD_GPIO1_4__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B          IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_5__CSI2_MCLK             (_MX51_PAD_GPIO1_5__CSI2_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_5__CSI2_MCLK             IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_5__DISP2_PIN16           (_MX51_PAD_GPIO1_5__DISP2_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_5__DISP2_PIN16           IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_5__GPIO1_5               (_MX51_PAD_GPIO1_5__GPIO1_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_5__GPIO1_5               IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B          (_MX51_PAD_GPIO1_5__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B          IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_6__DISP2_PIN17           (_MX51_PAD_GPIO1_6__DISP2_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_6__DISP2_PIN17           IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_6__GPIO1_6               (_MX51_PAD_GPIO1_6__GPIO1_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_6__GPIO1_6               IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_6__REF_EN_B              (_MX51_PAD_GPIO1_6__REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_6__REF_EN_B              IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_7__CCM_OUT_0             (_MX51_PAD_GPIO1_7__CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_7__CCM_OUT_0             IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_7__GPIO1_7               (_MX51_PAD_GPIO1_7__GPIO1_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_7__GPIO1_7               IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_7__SD2_WP                (_MX51_PAD_GPIO1_7__SD2_WP | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL))
+#define MX51_PAD_GPIO1_7__SD2_WP                IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL)
-#define MX51_PAD_GPIO1_7__SPDIF_OUT1            (_MX51_PAD_GPIO1_7__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_7__SPDIF_OUT1            IOMUX_PAD(0x810, 0x3e4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_8__CSI2_DATA_EN          (_MX51_PAD_GPIO1_8__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_8__CSI2_DATA_EN          IOMUX_PAD(0x814, 0x3e8, 2, 0x99c, 2, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_8__GPIO1_8               (_MX51_PAD_GPIO1_8__GPIO1_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_8__GPIO1_8               IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_8__SD2_CD                (_MX51_PAD_GPIO1_8__SD2_CD | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL))
+#define MX51_PAD_GPIO1_8__SD2_CD                IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL)
-#define MX51_PAD_GPIO1_8__USBH3_PWR             (_MX51_PAD_GPIO1_8__USBH3_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_8__USBH3_PWR             IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__CCM_OUT_1             (_MX51_PAD_GPIO1_9__CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_9__CCM_OUT_1             IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__DISP2_D1_CS           (_MX51_PAD_GPIO1_9__DISP2_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_9__DISP2_D1_CS           IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__DISP2_SER_CS          (_MX51_PAD_GPIO1_9__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_9__DISP2_SER_CS          IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__GPIO1_9               (_MX51_PAD_GPIO1_9__GPIO1_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_9__GPIO1_9               IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__SD2_LCTL              (_MX51_PAD_GPIO1_9__SD2_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_9__SD2_LCTL              IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__USBH3_OC              (_MX51_PAD_GPIO1_9__USBH3_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_9__USBH3_OC              IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL)
 #endif /* __MACH_IOMUX_MX51_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
index 5408fd1fc736..527f8fe3e31b 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx53.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
@@ -23,2359 +23,1197 @@
 /* These 2 defines are for pins that may not have a mux register, but could
 * have a pad setting register, and vice-versa. */
-#define NON_PAD_I       0x00
+#define __NA_   0x00
 #define MX53_UART_PAD_CTRL              (PAD_CTL_PKE | PAD_CTL_PUE |    \
                PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
 #define MX53_SDHC_PAD_CTRL      (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
                                PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \
                                PAD_CTL_SRE_FAST)
-#define PAD_CTRL_I2C    (PAD_CTL_SRE_FAST | PAD_CTL_ODE | PAD_CTL_PKE | \
-                        PAD_CTL_PUE | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP \
-                        | PAD_CTL_HYS)
-#define _MX53_PAD_GPIO_19__KPP_COL_5            IOMUX_PAD(0x348, 0x20, 0, 0x840, 0, 0)
-#define _MX53_PAD_GPIO_19__GPIO4_5              IOMUX_PAD(0x348, 0x20, 1, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_19__CCM_CLKO             IOMUX_PAD(0x348, 0x20, 2, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_19__SPDIF_OUT1   IOMUX_PAD(0x348, 0x20, 3, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 IOMUX_PAD(0x348, 0x20, 4, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_19__ECSPI1_RDY   IOMUX_PAD(0x348, 0x20, 5, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_19__FEC_TDATA_3  IOMUX_PAD(0x348, 0x20, 6, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_19__SRC_INT_BOOT IOMUX_PAD(0x348, 0x20,7, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL0__KPP_COL_0   IOMUX_PAD(0x34C, 0x24, 0, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL0__GPIO4_6             IOMUX_PAD(0x34C, 0x24, 1, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC     IOMUX_PAD(0x34C, 0x24, 2, 0x758, 0, 0)
-#define _MX53_PAD_KEY_COL0__UART4_TXD_MUX       IOMUX_PAD(0x34C, 0x24, 4, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL0__ECSPI1_SCLK IOMUX_PAD(0x34C, 0x24, 5, 0x79C, 0, 0)
-#define _MX53_PAD_KEY_COL0__FEC_RDATA_3 IOMUX_PAD(0x34C, 0x24, 6, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL0__SRC_ANY_PU_RST      IOMUX_PAD(0x34C, 0x24, 7, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW0__KPP_ROW_0   IOMUX_PAD(0x350, 0x28, 0, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW0__GPIO4_7             IOMUX_PAD(0x350, 0x28, 1, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD     IOMUX_PAD(0x350, 0x28, 2, 0x74C, 0, 0)
-#define _MX53_PAD_KEY_ROW0__UART4_RXD_MUX       IOMUX_PAD(0x350, 0x28, 4, 0x890, 1, 0)
-#define _MX53_PAD_KEY_ROW0__ECSPI1_MOSI IOMUX_PAD(0x350, 0x28, 5, 0x7A4, 0, 0)
-#define _MX53_PAD_KEY_ROW0__FEC_TX_ER   IOMUX_PAD(0x350, 0x28, 6, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL1__KPP_COL_1   IOMUX_PAD(0x354, 0x2C, 0, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL1__GPIO4_8             IOMUX_PAD(0x354, 0x2C, 1, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS    IOMUX_PAD(0x354, 0x2C, 2, 0x75C, 0, 0)
-#define _MX53_PAD_KEY_COL1__UART5_TXD_MUX       IOMUX_PAD(0x354, 0x2C, 4, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL1__ECSPI1_MISO IOMUX_PAD(0x354, 0x2C, 5, 0x7A0, 0, 0)
-#define _MX53_PAD_KEY_COL1__FEC_RX_CLK  IOMUX_PAD(0x354, 0x2C, 6, 0x808, 0, 0)
-#define _MX53_PAD_KEY_COL1__USBPHY1_TXREADY     IOMUX_PAD(0x354, 0x2C, 7, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW1__KPP_ROW_1   IOMUX_PAD(0x358, 0x30, 0, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW1__GPIO4_9             IOMUX_PAD(0x358, 0x30, 1, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD     IOMUX_PAD(0x358, 0x30, 2, 0x748, 0, 0)
-#define _MX53_PAD_KEY_ROW1__UART5_RXD_MUX       IOMUX_PAD(0x358, 0x30, 4, 0x898, 1, 0)
-#define _MX53_PAD_KEY_ROW1__ECSPI1_SS0  IOMUX_PAD(0x358, 0x30, 5, 0x7A8, 0, 0)
-#define _MX53_PAD_KEY_ROW1__FEC_COL             IOMUX_PAD(0x358, 0x30, 6, 0x800, 0, 0)
-#define _MX53_PAD_KEY_ROW1__USBPHY1_RXVALID     IOMUX_PAD(0x358, 0x30, 7, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL2__KPP_COL_2   IOMUX_PAD(0x35C, 0x34, 0, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL2__GPIO4_10            IOMUX_PAD(0x35C, 0x34, 1, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL2__CAN1_TXCAN  IOMUX_PAD(0x35C, 0x34, 2, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL2__FEC_MDIO            IOMUX_PAD(0x35C, 0x34, 4, 0x804, 0, 0)
-#define _MX53_PAD_KEY_COL2__ECSPI1_SS1  IOMUX_PAD(0x35C, 0x34, 5, 0x7AC, 0, 0)
-#define _MX53_PAD_KEY_COL2__FEC_RDATA_2 IOMUX_PAD(0x35C, 0x34, 6, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE    IOMUX_PAD(0x35C, 0x34, 7, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW2__KPP_ROW_2   IOMUX_PAD(0x360, 0x38, 0, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW2__GPIO4_11    IOMUX_PAD(0x360, 0x38, 1, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW2__CAN1_RXCAN  IOMUX_PAD(0x360, 0x38, 2, 0x760, 0, 0)
-#define _MX53_PAD_KEY_ROW2__FEC_MDC             IOMUX_PAD(0x360, 0x38, 4, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW2__ECSPI1_SS2  IOMUX_PAD(0x360, 0x38, 5, 0x7B0, 0, 0)
-#define _MX53_PAD_KEY_ROW2__FEC_TDATA_2 IOMUX_PAD(0x360, 0x38, 6, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW2__USBPHY1_RXERROR     IOMUX_PAD(0x360, 0x38, 7, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL3__KPP_COL_3   IOMUX_PAD(0x364, 0x3C, 0, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL3__GPIO4_12            IOMUX_PAD(0x364, 0x3C, 1, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL3__USBOH3_H2_DP        IOMUX_PAD(0x364, 0x3C, 2, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL3__SPDIF_IN1   IOMUX_PAD(0x364, 0x3C, 3, 0x870, 0, 0)
-#define _MX53_PAD_KEY_COL3__I2C2_SCL            IOMUX_PAD(0x364, 0x3C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, 0)
-#define _MX53_PAD_KEY_COL3__ECSPI1_SS3  IOMUX_PAD(0x364, 0x3C, 5, 0x7B4, 0, 0)
-#define _MX53_PAD_KEY_COL3__FEC_CRS             IOMUX_PAD(0x364, 0x3C, 6, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK    IOMUX_PAD(0x364, 0x3C, 7, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW3__KPP_ROW_3   IOMUX_PAD(0x368, 0x40, 0, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW3__GPIO4_13    IOMUX_PAD(0x368, 0x40, 1, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW3__USBOH3_H2_DM        IOMUX_PAD(0x368, 0x40, 2, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK    IOMUX_PAD(0x368, 0x40, 3, 0x768, 0, 0)
-#define _MX53_PAD_KEY_ROW3__I2C2_SDA    IOMUX_PAD(0x368, 0x40, 4 | IOMUX_CONFIG_SION, 0x820, 0, 0)
-#define _MX53_PAD_KEY_ROW3__OSC32K_32K_OUT      IOMUX_PAD(0x368, 0x40, 5, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW3__CCM_PLL4_BYP        IOMUX_PAD(0x368, 0x40, 6, 0x77C, 0, 0)
-#define _MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 IOMUX_PAD(0x368, 0x40, 7, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL4__KPP_COL_4   IOMUX_PAD(0x36C, 0x44, 0, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL4__GPIO4_14            IOMUX_PAD(0x36C, 0x44, 1, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL4__CAN2_TXCAN  IOMUX_PAD(0x36C, 0x44, 2, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL4__IPU_SISG_4  IOMUX_PAD(0x36C, 0x44, 3, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL4__UART5_RTS   IOMUX_PAD(0x36C, 0x44, 4, 0x894, 0, 0)
-#define _MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC    IOMUX_PAD(0x36C, 0x44, 5, 0x89C, 0, 0)
-#define _MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 IOMUX_PAD(0x36C, 0x44, 7, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW4__KPP_ROW_4   IOMUX_PAD(0x370, 0x48, 0, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW4__GPIO4_15    IOMUX_PAD(0x370, 0x48, 1, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW4__CAN2_RXCAN  IOMUX_PAD(0x370, 0x48, 2, 0x764, 0, 0)
-#define _MX53_PAD_KEY_ROW4__IPU_SISG_5  IOMUX_PAD(0x370, 0x48, 3, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW4__UART5_CTS   IOMUX_PAD(0x370, 0x48, 4, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR   IOMUX_PAD(0x370, 0x48, 5, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID   IOMUX_PAD(0x370, 0x48, 7, 0x0, 0, 0)
-#define _MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK        IOMUX_PAD(0x378, 0x4C, 0, 0x0, 0, 0)
-#define _MX53_PAD_DI0_DISP_CLK__GPIO4_16                IOMUX_PAD(0x378, 0x4C, 1, 0x0, 0, 0)
-#define _MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR        IOMUX_PAD(0x378, 0x4C, 2, 0x0, 0, 0)
-#define _MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 IOMUX_PAD(0x378, 0x4C, 5, 0x0, 0, 0)
-#define _MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 IOMUX_PAD(0x378, 0x4C, 6, 0x0, 0, 0)
-#define _MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID  IOMUX_PAD(0x378, 0x4C, 7, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN15__IPU_DI0_PIN15              IOMUX_PAD(0x37C, 0x50, 0, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN15__GPIO4_17           IOMUX_PAD(0x37C, 0x50, 1, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC    IOMUX_PAD(0x37C, 0x50, 2, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1    IOMUX_PAD(0x37C, 0x50, 5, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1    IOMUX_PAD(0x37C, 0x50, 6, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN15__USBPHY1_BVALID             IOMUX_PAD(0x37C, 0x50, 7, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN2__IPU_DI0_PIN2                IOMUX_PAD(0x380, 0x54, 0, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN2__GPIO4_18                    IOMUX_PAD(0x380, 0x54, 1, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD     IOMUX_PAD(0x380, 0x54, 2, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2     IOMUX_PAD(0x380, 0x54, 5, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2             IOMUX_PAD(0x380, 0x54, 6, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION  IOMUX_PAD(0x380, 0x54, 7, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN3__IPU_DI0_PIN3                IOMUX_PAD(0x384, 0x58, 0, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN3__GPIO4_19                    IOMUX_PAD(0x384, 0x58, 1, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS    IOMUX_PAD(0x384, 0x58, 2, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3     IOMUX_PAD(0x384, 0x58, 5, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3             IOMUX_PAD(0x384, 0x58, 6, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN3__USBPHY1_IDDIG               IOMUX_PAD(0x384, 0x58, 7, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN4__IPU_DI0_PIN4                IOMUX_PAD(0x388, 0x5C, 0, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN4__GPIO4_20                    IOMUX_PAD(0x388, 0x5C, 1, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD     IOMUX_PAD(0x388, 0x5C, 2, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN4__ESDHC1_WP           IOMUX_PAD(0x388, 0x5C, 3, 0x7FC, 0, 0)
-#define _MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD    IOMUX_PAD(0x388, 0x5C, 5, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4             IOMUX_PAD(0x388, 0x5C, 6, 0x0, 0, 0)
-#define _MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT      IOMUX_PAD(0x388, 0x5C, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0   IOMUX_PAD(0x38C, 0x60, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT0__GPIO4_21          IOMUX_PAD(0x38C, 0x60, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT0__CSPI_SCLK         IOMUX_PAD(0x38C, 0x60, 2, 0x780, 0, 0)
-#define _MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0       IOMUX_PAD(0x38C, 0x60, 3, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN       IOMUX_PAD(0x38C, 0x60, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5   IOMUX_PAD(0x38C, 0x60, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY   IOMUX_PAD(0x38C, 0x60, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1   IOMUX_PAD(0x390, 0x64, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT1__GPIO4_22          IOMUX_PAD(0x390, 0x64, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT1__CSPI_MOSI         IOMUX_PAD(0x390, 0x64, 2, 0x788, 0, 0)
-#define _MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1       IOMUX_PAD(0x390, 0x64, 3, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL      IOMUX_PAD(0x390, 0x64, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6   IOMUX_PAD(0x390, 0x64, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID   IOMUX_PAD(0x390, 0x64, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2   IOMUX_PAD(0x394, 0x68, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT2__GPIO4_23          IOMUX_PAD(0x394, 0x68, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT2__CSPI_MISO         IOMUX_PAD(0x394, 0x68, 2, 0x784, 0, 0)
-#define _MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2       IOMUX_PAD(0x394, 0x68, 3, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE   IOMUX_PAD(0x394, 0x68, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7   IOMUX_PAD(0x394, 0x68, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE  IOMUX_PAD(0x394, 0x68, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3   IOMUX_PAD(0x398, 0x6C, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT3__GPIO4_24          IOMUX_PAD(0x398, 0x6C, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT3__CSPI_SS0          IOMUX_PAD(0x398, 0x6C, 2, 0x78C, 0, 0)
-#define _MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3       IOMUX_PAD(0x398, 0x6C, 3, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR      IOMUX_PAD(0x398, 0x6C, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8   IOMUX_PAD(0x398, 0x6C, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR   IOMUX_PAD(0x398, 0x6C, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4   IOMUX_PAD(0x39C, 0x70, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT4__GPIO4_25          IOMUX_PAD(0x39C, 0x70, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT4__CSPI_SS1          IOMUX_PAD(0x39C, 0x70, 2, 0x790, 0, 0)
-#define _MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4       IOMUX_PAD(0x39C, 0x70, 3, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB        IOMUX_PAD(0x39C, 0x70, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9   IOMUX_PAD(0x39C, 0x70, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK  IOMUX_PAD(0x39C, 0x70, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5   IOMUX_PAD(0x3A0, 0x74, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT5__GPIO4_26          IOMUX_PAD(0x3A0, 0x74, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT5__CSPI_SS2          IOMUX_PAD(0x3A0, 0x74, 2, 0x794, 0, 0)
-#define _MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5       IOMUX_PAD(0x3A0, 0x74, 3, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS  IOMUX_PAD(0x3A0, 0x74, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10  IOMUX_PAD(0x3A0, 0x74, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0       IOMUX_PAD(0x3A0, 0x74, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6   IOMUX_PAD(0x3A4, 0x78, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT6__GPIO4_27          IOMUX_PAD(0x3A4, 0x78, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT6__CSPI_SS3          IOMUX_PAD(0x3A4, 0x78, 2, 0x798, 0, 0)
-#define _MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6       IOMUX_PAD(0x3A4, 0x78, 3, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE IOMUX_PAD(0x3A4, 0x78, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11  IOMUX_PAD(0x3A4, 0x78, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1       IOMUX_PAD(0x3A4, 0x78, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7   IOMUX_PAD(0x3A8, 0x7C, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT7__GPIO4_28          IOMUX_PAD(0x3A8, 0x7C, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT7__CSPI_RDY          IOMUX_PAD(0x3A8, 0x7C, 2, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7       IOMUX_PAD(0x3A8, 0x7C, 3, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0        IOMUX_PAD(0x3A8, 0x7C, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12  IOMUX_PAD(0x3A8, 0x7C, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID IOMUX_PAD(0x3A8, 0x7C, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8   IOMUX_PAD(0x3AC, 0x80, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT8__GPIO4_29          IOMUX_PAD(0x3AC, 0x80, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT8__PWM1_PWMO         IOMUX_PAD(0x3AC, 0x80, 2, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B      IOMUX_PAD(0x3AC, 0x80, 3, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1        IOMUX_PAD(0x3AC, 0x80, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13  IOMUX_PAD(0x3AC, 0x80, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT8__USBPHY2_AVALID    IOMUX_PAD(0x3AC, 0x80, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9   IOMUX_PAD(0x3B0, 0x84, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT9__GPIO4_30          IOMUX_PAD(0x3B0, 0x84, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT9__PWM2_PWMO         IOMUX_PAD(0x3B0, 0x84, 2, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B      IOMUX_PAD(0x3B0, 0x84, 3, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2                IOMUX_PAD(0x3B0, 0x84, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14  IOMUX_PAD(0x3B0, 0x84, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 IOMUX_PAD(0x3B0, 0x84, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 IOMUX_PAD(0x3B4, 0x88, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT10__GPIO4_31         IOMUX_PAD(0x3B4, 0x88, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP IOMUX_PAD(0x3B4, 0x88, 2, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3       IOMUX_PAD(0x3B4, 0x88, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 IOMUX_PAD(0x3B4, 0x88, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1        IOMUX_PAD(0x3B4, 0x88, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 IOMUX_PAD(0x3B8, 0x8C, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT11__GPIO5_5          IOMUX_PAD(0x3B8, 0x8C, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT IOMUX_PAD(0x3B8, 0x8C, 2, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4       IOMUX_PAD(0x3B8, 0x8C, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 IOMUX_PAD(0x3B8, 0x8C, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2        IOMUX_PAD(0x3B8, 0x8C, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 IOMUX_PAD(0x3BC, 0x90, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT12__GPIO5_6          IOMUX_PAD(0x3BC, 0x90, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK IOMUX_PAD(0x3BC, 0x90, 2, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5       IOMUX_PAD(0x3BC, 0x90, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 IOMUX_PAD(0x3BC, 0x90, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3        IOMUX_PAD(0x3BC, 0x90, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 IOMUX_PAD(0x3C0, 0x94, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT13__GPIO5_7          IOMUX_PAD(0x3C0, 0x94, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS IOMUX_PAD(0x3C0, 0x94, 3, 0x754, 0, 0)
-#define _MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0       IOMUX_PAD(0x3C0, 0x94, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 IOMUX_PAD(0x3C0, 0x94, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4        IOMUX_PAD(0x3C0, 0x94, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 IOMUX_PAD(0x3C4, 0x98, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT14__GPIO5_8          IOMUX_PAD(0x3C4, 0x98, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC  IOMUX_PAD(0x3C4, 0x98, 3, 0x750, 0, 0)
-#define _MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1       IOMUX_PAD(0x3C4, 0x98, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 IOMUX_PAD(0x3C4, 0x98, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5        IOMUX_PAD(0x3C4, 0x98, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 IOMUX_PAD(0x3C8, 0x9C, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT15__GPIO5_9          IOMUX_PAD(0x3C8, 0x9C, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT15__ECSPI1_SS1               IOMUX_PAD(0x3C8, 0x9C, 2, 0x7AC, 1, 0)
-#define _MX53_PAD_DISP0_DAT15__ECSPI2_SS1               IOMUX_PAD(0x3C8, 0x9C, 3, 0x7C8, 0, 0)
-#define _MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2       IOMUX_PAD(0x3C8, 0x9C, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 IOMUX_PAD(0x3C8, 0x9C, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6        IOMUX_PAD(0x3C8, 0x9C, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 IOMUX_PAD(0x3CC, 0xA0, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT16__GPIO5_10         IOMUX_PAD(0x3CC, 0xA0, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT16__ECSPI2_MOSI              IOMUX_PAD(0x3CC, 0xA0, 2, 0x7C0, 0, 0)
-#define _MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC  IOMUX_PAD(0x3CC, 0xA0, 3, 0x758, 1, 0)
-#define _MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 IOMUX_PAD(0x3CC, 0xA0, 4, 0x868, 0, 0)
-#define _MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3       IOMUX_PAD(0x3CC, 0xA0, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 IOMUX_PAD(0x3CC, 0xA0, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7        IOMUX_PAD(0x3CC, 0xA0, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 IOMUX_PAD(0x3D0, 0xA4, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT17__GPIO5_11         IOMUX_PAD(0x3D0, 0xA4, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT17__ECSPI2_MISO              IOMUX_PAD(0x3D0, 0xA4, 2, 0x7BC, 0, 0)
-#define _MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD  IOMUX_PAD(0x3D0, 0xA4, 3, 0x74C, 1, 0)
-#define _MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 IOMUX_PAD(0x3D0, 0xA4, 4, 0x86C, 0, 0)
-#define _MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4       IOMUX_PAD(0x3D0, 0xA4, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 IOMUX_PAD(0x3D0, 0xA4, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 IOMUX_PAD(0x3D4, 0xA8, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT18__GPIO5_12         IOMUX_PAD(0x3D4, 0xA8, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT18__ECSPI2_SS0               IOMUX_PAD(0x3D4, 0xA8, 2, 0x7C4, 0, 0)
-#define _MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS IOMUX_PAD(0x3D4, 0xA8, 3, 0x75C, 1, 0)
-#define _MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS IOMUX_PAD(0x3D4, 0xA8, 4, 0x73C, 0, 0)
-#define _MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5       IOMUX_PAD(0x3D4, 0xA8, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 IOMUX_PAD(0x3D4, 0xA8, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2    IOMUX_PAD(0x3D4, 0xA8, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 IOMUX_PAD(0x3D8, 0xAC, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT19__GPIO5_13         IOMUX_PAD(0x3D8, 0xAC, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT19__ECSPI2_SCLK              IOMUX_PAD(0x3D8, 0xAC, 2, 0x7B8, 0, 0)
-#define _MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD  IOMUX_PAD(0x3D8, 0xAC, 3, 0x748, 1, 0)
-#define _MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC  IOMUX_PAD(0x3D8, 0xAC, 4, 0x738, 0, 0)
-#define _MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6       IOMUX_PAD(0x3D8, 0xAC, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 IOMUX_PAD(0x3D8, 0xAC, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3    IOMUX_PAD(0x3D8, 0xAC, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 IOMUX_PAD(0x3DC, 0xB0, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT20__GPIO5_14         IOMUX_PAD(0x3DC, 0xB0, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT20__ECSPI1_SCLK              IOMUX_PAD(0x3DC, 0xB0, 2, 0x79C, 1, 0)
-#define _MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC  IOMUX_PAD(0x3DC, 0xB0, 3, 0x740, 0, 0)
-#define _MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7       IOMUX_PAD(0x3DC, 0xB0, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 IOMUX_PAD(0x3DC, 0xB0, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT20__SATA_PHY_TDI             IOMUX_PAD(0x3DC, 0xB0, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 IOMUX_PAD(0x3E0, 0xB4, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT21__GPIO5_15         IOMUX_PAD(0x3E0, 0xB4, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT21__ECSPI1_MOSI              IOMUX_PAD(0x3E0, 0xB4, 2, 0x7A4, 1, 0)
-#define _MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD  IOMUX_PAD(0x3E0, 0xB4, 3, 0x734, 0, 0)
-#define _MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0  IOMUX_PAD(0x3E0, 0xB4, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 IOMUX_PAD(0x3E0, 0xB4, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT21__SATA_PHY_TDO     IOMUX_PAD(0x3E0, 0xB4, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 IOMUX_PAD(0x3E4, 0xB8, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT22__GPIO5_16         IOMUX_PAD(0x3E4, 0xB8, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT22__ECSPI1_MISO              IOMUX_PAD(0x3E4, 0xB8, 2, 0x7A0, 1, 0)
-#define _MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS IOMUX_PAD(0x3E4, 0xB8, 3, 0x744, 0, 0)
-#define _MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1  IOMUX_PAD(0x3E4, 0xB8, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 IOMUX_PAD(0x3E4, 0xB8, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT22__SATA_PHY_TCK     IOMUX_PAD(0x3E4, 0xB8, 7, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 IOMUX_PAD(0x3E8, 0xBC, 0, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT23__GPIO5_17         IOMUX_PAD(0x3E8, 0xBC, 1, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT23__ECSPI1_SS0               IOMUX_PAD(0x3E8, 0xBC, 2, 0x7A8, 1, 0)
-#define _MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD  IOMUX_PAD(0x3E8, 0xBC, 3, 0x730, 0, 0)
-#define _MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2  IOMUX_PAD(0x3E8, 0xBC, 5, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 IOMUX_PAD(0x3E8, 0xBC, 6, 0x0, 0, 0)
-#define _MX53_PAD_DISP0_DAT23__SATA_PHY_TMS     IOMUX_PAD(0x3E8, 0xBC, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK  IOMUX_PAD(0x3EC, 0xC0, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_PIXCLK__GPIO5_18         IOMUX_PAD(0x3EC, 0xC0, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0  IOMUX_PAD(0x3EC, 0xC0, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 IOMUX_PAD(0x3EC, 0xC0, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC             IOMUX_PAD(0x3F0, 0xC4, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_MCLK__GPIO5_19           IOMUX_PAD(0x3F0, 0xC4, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK              IOMUX_PAD(0x3F0, 0xC4, 2, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1    IOMUX_PAD(0x3F0, 0xC4, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30   IOMUX_PAD(0x3F0, 0xC4, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_MCLK__TPIU_TRCTL         IOMUX_PAD(0x3F0, 0xC4, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN        IOMUX_PAD(0x3F4, 0xC8, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DATA_EN__GPIO5_20                IOMUX_PAD(0x3F4, 0xC8, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 IOMUX_PAD(0x3F4, 0xC8, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31        IOMUX_PAD(0x3F4, 0xC8, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK              IOMUX_PAD(0x3F4, 0xC8, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC    IOMUX_PAD(0x3F8, 0xCC, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_VSYNC__GPIO5_21          IOMUX_PAD(0x3F8, 0xCC, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3   IOMUX_PAD(0x3F8, 0xCC, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32  IOMUX_PAD(0x3F8, 0xCC, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0              IOMUX_PAD(0x3F8, 0xCC, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4               IOMUX_PAD(0x3FC, 0xD0, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT4__GPIO5_22           IOMUX_PAD(0x3FC, 0xD0, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT4__KPP_COL_5          IOMUX_PAD(0x3FC, 0xD0, 2, 0x840, 1, 0)
-#define _MX53_PAD_CSI0_DAT4__ECSPI1_SCLK                IOMUX_PAD(0x3FC, 0xD0, 3, 0x79C, 2, 0)
-#define _MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP   IOMUX_PAD(0x3FC, 0xD0, 4, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC    IOMUX_PAD(0x3FC, 0xD0, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33   IOMUX_PAD(0x3FC, 0xD0, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT4__TPIU_TRACE_1               IOMUX_PAD(0x3FC, 0xD0, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5               IOMUX_PAD(0x400, 0xD4, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT5__GPIO5_23           IOMUX_PAD(0x400, 0xD4, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT5__KPP_ROW_5          IOMUX_PAD(0x400, 0xD4, 2, 0x84C, 0, 0)
-#define _MX53_PAD_CSI0_DAT5__ECSPI1_MOSI                IOMUX_PAD(0x400, 0xD4, 3, 0x7A4, 2, 0)
-#define _MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT   IOMUX_PAD(0x400, 0xD4, 4, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD    IOMUX_PAD(0x400, 0xD4, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34   IOMUX_PAD(0x400, 0xD4, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT5__TPIU_TRACE_2               IOMUX_PAD(0x400, 0xD4, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6               IOMUX_PAD(0x404, 0xD8, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT6__GPIO5_24           IOMUX_PAD(0x404, 0xD8, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT6__KPP_COL_6          IOMUX_PAD(0x404, 0xD8, 2, 0x844, 0, 0)
-#define _MX53_PAD_CSI0_DAT6__ECSPI1_MISO                IOMUX_PAD(0x404, 0xD8, 3, 0x7A0, 2, 0)
-#define _MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK   IOMUX_PAD(0x404, 0xD8, 4, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS   IOMUX_PAD(0x404, 0xD8, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35   IOMUX_PAD(0x404, 0xD8, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT6__TPIU_TRACE_3               IOMUX_PAD(0x404, 0xD8, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7               IOMUX_PAD(0x408, 0xDC, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT7__GPIO5_25           IOMUX_PAD(0x408, 0xDC, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT7__KPP_ROW_6          IOMUX_PAD(0x408, 0xDC, 2, 0x850, 0, 0)
-#define _MX53_PAD_CSI0_DAT7__ECSPI1_SS0         IOMUX_PAD(0x408, 0xDC, 3, 0x7A8, 2, 0)
-#define _MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR   IOMUX_PAD(0x408, 0xDC, 4, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD    IOMUX_PAD(0x408, 0xDC, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36   IOMUX_PAD(0x408, 0xDC, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT7__TPIU_TRACE_4               IOMUX_PAD(0x408, 0xDC, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8               IOMUX_PAD(0x40C, 0xE0, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT8__GPIO5_26           IOMUX_PAD(0x40C, 0xE0, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT8__KPP_COL_7          IOMUX_PAD(0x40C, 0xE0, 2, 0x848, 0, 0)
-#define _MX53_PAD_CSI0_DAT8__ECSPI2_SCLK                IOMUX_PAD(0x40C, 0xE0, 3, 0x7B8, 1, 0)
-#define _MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC    IOMUX_PAD(0x40C, 0xE0, 4, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT8__I2C1_SDA           IOMUX_PAD(0x40C, 0xE0, 5 | IOMUX_CONFIG_SION, 0x818, 0, 0)
-#define _MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37   IOMUX_PAD(0x40C, 0xE0, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT8__TPIU_TRACE_5               IOMUX_PAD(0x40C, 0xE0, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9               IOMUX_PAD(0x410, 0xE4, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT9__GPIO5_27           IOMUX_PAD(0x410, 0xE4, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT9__KPP_ROW_7          IOMUX_PAD(0x410, 0xE4, 2, 0x854, 0, 0)
-#define _MX53_PAD_CSI0_DAT9__ECSPI2_MOSI                IOMUX_PAD(0x410, 0xE4, 3, 0x7C0, 1, 0)
-#define _MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR   IOMUX_PAD(0x410, 0xE4, 4, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT9__I2C1_SCL           IOMUX_PAD(0x410, 0xE4, 5 | IOMUX_CONFIG_SION, 0x814, 0, 0)
-#define _MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38   IOMUX_PAD(0x410, 0xE4, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT9__TPIU_TRACE_6               IOMUX_PAD(0x410, 0xE4, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10             IOMUX_PAD(0x414, 0xE8, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT10__GPIO5_28          IOMUX_PAD(0x414, 0xE8, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT10__UART1_TXD_MUX     IOMUX_PAD(0x414, 0xE8, 2, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT10__ECSPI2_MISO               IOMUX_PAD(0x414, 0xE8, 3, 0x7BC, 1, 0)
-#define _MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC   IOMUX_PAD(0x414, 0xE8, 4, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4   IOMUX_PAD(0x414, 0xE8, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39  IOMUX_PAD(0x414, 0xE8, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT10__TPIU_TRACE_7              IOMUX_PAD(0x414, 0xE8, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11             IOMUX_PAD(0x418, 0xEC, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT11__GPIO5_29          IOMUX_PAD(0x418, 0xEC, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT11__UART1_RXD_MUX     IOMUX_PAD(0x418, 0xEC, 2, 0x878, 1, 0)
-#define _MX53_PAD_CSI0_DAT11__ECSPI2_SS0                IOMUX_PAD(0x418, 0xEC, 3, 0x7C4, 1, 0)
-#define _MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS  IOMUX_PAD(0x418, 0xEC, 4, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5   IOMUX_PAD(0x418, 0xEC, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40  IOMUX_PAD(0x418, 0xEC, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT11__TPIU_TRACE_8              IOMUX_PAD(0x418, 0xEC, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12             IOMUX_PAD(0x41C, 0xF0, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT12__GPIO5_30          IOMUX_PAD(0x41C, 0xF0, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT12__UART4_TXD_MUX     IOMUX_PAD(0x41C, 0xF0, 2, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0       IOMUX_PAD(0x41C, 0xF0, 4, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6   IOMUX_PAD(0x41C, 0xF0, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41  IOMUX_PAD(0x41C, 0xF0, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT12__TPIU_TRACE_9              IOMUX_PAD(0x41C, 0xF0, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13             IOMUX_PAD(0x420, 0xF4, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT13__GPIO5_31          IOMUX_PAD(0x420, 0xF4, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT13__UART4_RXD_MUX     IOMUX_PAD(0x420, 0xF4, 2, 0x890, 3, 0)
-#define _MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1       IOMUX_PAD(0x420, 0xF4, 4, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7   IOMUX_PAD(0x420, 0xF4, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42  IOMUX_PAD(0x420, 0xF4, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT13__TPIU_TRACE_10             IOMUX_PAD(0x420, 0xF4, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14             IOMUX_PAD(0x424, 0xF8, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT14__GPIO6_0           IOMUX_PAD(0x424, 0xF8, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT14__UART5_TXD_MUX     IOMUX_PAD(0x424, 0xF8, 2, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2       IOMUX_PAD(0x424, 0xF8, 4, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8   IOMUX_PAD(0x424, 0xF8, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43  IOMUX_PAD(0x424, 0xF8, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT14__TPIU_TRACE_11             IOMUX_PAD(0x424, 0xF8, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15             IOMUX_PAD(0x428, 0xFC, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT15__GPIO6_1           IOMUX_PAD(0x428, 0xFC, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT15__UART5_RXD_MUX     IOMUX_PAD(0x428, 0xFC, 2, 0x898, 3, 0)
-#define _MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3       IOMUX_PAD(0x428, 0xFC, 4, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9   IOMUX_PAD(0x428, 0xFC, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44  IOMUX_PAD(0x428, 0xFC, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT15__TPIU_TRACE_12             IOMUX_PAD(0x428, 0xFC, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16             IOMUX_PAD(0x42C, 0x100, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT16__GPIO6_2           IOMUX_PAD(0x42C, 0x100, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT16__UART4_RTS         IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, 0)
-#define _MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4       IOMUX_PAD(0x42C, 0x100, 4, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10  IOMUX_PAD(0x42C, 0x100, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45  IOMUX_PAD(0x42C, 0x100, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT16__TPIU_TRACE_13             IOMUX_PAD(0x42C, 0x100, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17             IOMUX_PAD(0x430, 0x104, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT17__GPIO6_3           IOMUX_PAD(0x430, 0x104, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT17__UART4_CTS         IOMUX_PAD(0x430, 0x104, 2, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5       IOMUX_PAD(0x430, 0x104, 4, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11  IOMUX_PAD(0x430, 0x104, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46  IOMUX_PAD(0x430, 0x104, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT17__TPIU_TRACE_14             IOMUX_PAD(0x430, 0x104, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18             IOMUX_PAD(0x434, 0x108, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT18__GPIO6_4           IOMUX_PAD(0x434, 0x108, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT18__UART5_RTS         IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, 0)
-#define _MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6       IOMUX_PAD(0x434, 0x108, 4, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12  IOMUX_PAD(0x434, 0x108, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47  IOMUX_PAD(0x434, 0x108, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT18__TPIU_TRACE_15             IOMUX_PAD(0x434, 0x108, 7, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19             IOMUX_PAD(0x438, 0x10C, 0, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT19__GPIO6_5           IOMUX_PAD(0x438, 0x10C, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT19__UART5_CTS         IOMUX_PAD(0x438, 0x10C, 2, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7       IOMUX_PAD(0x438, 0x10C, 4, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13  IOMUX_PAD(0x438, 0x10C, 5, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48  IOMUX_PAD(0x438, 0x10C, 6, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK    IOMUX_PAD(0x438, 0x10C, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A25__EMI_WEIM_A_25                IOMUX_PAD(0x458, 0x110, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A25__GPIO5_2                      IOMUX_PAD(0x458, 0x110, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A25__ECSPI2_RDY           IOMUX_PAD(0x458, 0x110, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A25__IPU_DI1_PIN12                IOMUX_PAD(0x458, 0x110, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A25__CSPI_SS1                     IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, 0)
-#define _MX53_PAD_EIM_A25__IPU_DI0_D1_CS                IOMUX_PAD(0x458, 0x110, 6, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A25__USBPHY1_BISTOK               IOMUX_PAD(0x458, 0x110, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB2__EMI_WEIM_EB_2                IOMUX_PAD(0x45C, 0x114, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB2__GPIO2_30                     IOMUX_PAD(0x45C, 0x114, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK              IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, 0)
-#define _MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS             IOMUX_PAD(0x45C, 0x114, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB2__ECSPI1_SS0           IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, 0)
-#define _MX53_PAD_EIM_EB2__I2C2_SCL                     IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, 0)
-#define _MX53_PAD_EIM_D16__EMI_WEIM_D_16                IOMUX_PAD(0x460, 0x118, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D16__GPIO3_16                     IOMUX_PAD(0x460, 0x118, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D16__IPU_DI0_PIN5         IOMUX_PAD(0x460, 0x118, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK   IOMUX_PAD(0x460, 0x118, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D16__ECSPI1_SCLK          IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, 0)
-#define _MX53_PAD_EIM_D16__I2C2_SDA                     IOMUX_PAD(0x460, 0x118, 5 | IOMUX_CONFIG_SION, 0x820, 1, 0)
-#define _MX53_PAD_EIM_D17__EMI_WEIM_D_17                IOMUX_PAD(0x464, 0x11C, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D17__GPIO3_17                     IOMUX_PAD(0x464, 0x11C, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D17__IPU_DI0_PIN6         IOMUX_PAD(0x464, 0x11C, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN   IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, 0)
-#define _MX53_PAD_EIM_D17__ECSPI1_MISO          IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, 0)
-#define _MX53_PAD_EIM_D17__I2C3_SCL                     IOMUX_PAD(0x464, 0x11C, 5 | IOMUX_CONFIG_SION, 0x824, 0, 0)
-#define _MX53_PAD_EIM_D18__EMI_WEIM_D_18                IOMUX_PAD(0x468, 0x120, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D18__GPIO3_18                     IOMUX_PAD(0x468, 0x120, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D18__IPU_DI0_PIN7         IOMUX_PAD(0x468, 0x120, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO   IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, 0)
-#define _MX53_PAD_EIM_D18__ECSPI1_MOSI          IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, 0)
-#define _MX53_PAD_EIM_D18__I2C3_SDA                     IOMUX_PAD(0x468, 0x120, 5 | IOMUX_CONFIG_SION, 0x828, 0, 0)
-#define _MX53_PAD_EIM_D18__IPU_DI1_D0_CS                IOMUX_PAD(0x468, 0x120, 6, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D19__EMI_WEIM_D_19                IOMUX_PAD(0x46C, 0x124, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D19__GPIO3_19                     IOMUX_PAD(0x46C, 0x124, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D19__IPU_DI0_PIN8         IOMUX_PAD(0x46C, 0x124, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS    IOMUX_PAD(0x46C, 0x124, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D19__ECSPI1_SS1           IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, 0)
-#define _MX53_PAD_EIM_D19__EPIT1_EPITO          IOMUX_PAD(0x46C, 0x124, 5, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D19__UART1_CTS                    IOMUX_PAD(0x46C, 0x124, 6, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D19__USBOH3_USBH2_OC              IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, 0)
-#define _MX53_PAD_EIM_D20__EMI_WEIM_D_20                IOMUX_PAD(0x470, 0x128, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D20__GPIO3_20                     IOMUX_PAD(0x470, 0x128, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D20__IPU_DI0_PIN16                IOMUX_PAD(0x470, 0x128, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D20__IPU_SER_DISP0_CS             IOMUX_PAD(0x470, 0x128, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D20__CSPI_SS0                     IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, 0)
-#define _MX53_PAD_EIM_D20__EPIT2_EPITO          IOMUX_PAD(0x470, 0x128, 5, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D20__UART1_RTS                    IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, 0)
-#define _MX53_PAD_EIM_D20__USBOH3_USBH2_PWR     IOMUX_PAD(0x470, 0x128, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D21__EMI_WEIM_D_21                IOMUX_PAD(0x474, 0x12C, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D21__GPIO3_21                     IOMUX_PAD(0x474, 0x12C, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D21__IPU_DI0_PIN17                IOMUX_PAD(0x474, 0x12C, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK   IOMUX_PAD(0x474, 0x12C, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D21__CSPI_SCLK                    IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, 0)
-#define _MX53_PAD_EIM_D21__I2C1_SCL                     IOMUX_PAD(0x474, 0x12C, 5 | IOMUX_CONFIG_SION, 0x814, 1, 0)
-#define _MX53_PAD_EIM_D21__USBOH3_USBOTG_OC     IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, 0)
-#define _MX53_PAD_EIM_D22__EMI_WEIM_D_22                IOMUX_PAD(0x478, 0x130, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D22__GPIO3_22                     IOMUX_PAD(0x478, 0x130, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D22__IPU_DI0_PIN1         IOMUX_PAD(0x478, 0x130, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN   IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, 0)
-#define _MX53_PAD_EIM_D22__CSPI_MISO                    IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, 0)
-#define _MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR    IOMUX_PAD(0x478, 0x130, 6, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D23__EMI_WEIM_D_23                IOMUX_PAD(0x47C, 0x134, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D23__GPIO3_23                     IOMUX_PAD(0x47C, 0x134, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D23__UART3_CTS                    IOMUX_PAD(0x47C, 0x134, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D23__UART1_DCD            IOMUX_PAD(0x47C, 0x134, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D23__IPU_DI0_D0_CS                IOMUX_PAD(0x47C, 0x134, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D23__IPU_DI1_PIN2         IOMUX_PAD(0x47C, 0x134, 5, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN             IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, 0)
-#define _MX53_PAD_EIM_D23__IPU_DI1_PIN14                IOMUX_PAD(0x47C, 0x134, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB3__EMI_WEIM_EB_3                IOMUX_PAD(0x480, 0x138, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB3__GPIO2_31                     IOMUX_PAD(0x480, 0x138, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB3__UART3_RTS                    IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, 0)
-#define _MX53_PAD_EIM_EB3__UART1_RI                     IOMUX_PAD(0x480, 0x138, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB3__IPU_DI1_PIN3         IOMUX_PAD(0x480, 0x138, 5, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC               IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, 0)
-#define _MX53_PAD_EIM_EB3__IPU_DI1_PIN16                IOMUX_PAD(0x480, 0x138, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D24__EMI_WEIM_D_24                IOMUX_PAD(0x484, 0x13C, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D24__GPIO3_24                     IOMUX_PAD(0x484, 0x13C, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D24__UART3_TXD_MUX                IOMUX_PAD(0x484, 0x13C, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D24__ECSPI1_SS2           IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, 0)
-#define _MX53_PAD_EIM_D24__CSPI_SS2                     IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, 0)
-#define _MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS     IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, 0)
-#define _MX53_PAD_EIM_D24__ECSPI2_SS2           IOMUX_PAD(0x484, 0x13C, 6, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D24__UART1_DTR            IOMUX_PAD(0x484, 0x13C, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D25__EMI_WEIM_D_25                IOMUX_PAD(0x488, 0x140, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D25__GPIO3_25                     IOMUX_PAD(0x488, 0x140, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D25__UART3_RXD_MUX                IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, 0)
-#define _MX53_PAD_EIM_D25__ECSPI1_SS3           IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, 0)
-#define _MX53_PAD_EIM_D25__CSPI_SS3                     IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, 0)
-#define _MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC              IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, 0)
-#define _MX53_PAD_EIM_D25__ECSPI2_SS3           IOMUX_PAD(0x488, 0x140, 6, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D25__UART1_DSR            IOMUX_PAD(0x488, 0x140, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D26__EMI_WEIM_D_26                IOMUX_PAD(0x48C, 0x144, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D26__GPIO3_26                     IOMUX_PAD(0x48C, 0x144, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D26__UART2_TXD_MUX                IOMUX_PAD(0x48C, 0x144, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D26__FIRI_RXD                     IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, 0)
-#define _MX53_PAD_EIM_D26__IPU_CSI0_D_1         IOMUX_PAD(0x48C, 0x144, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D26__IPU_DI1_PIN11                IOMUX_PAD(0x48C, 0x144, 5, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D26__IPU_SISG_2           IOMUX_PAD(0x48C, 0x144, 6, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D26__IPU_DISP1_DAT_22             IOMUX_PAD(0x48C, 0x144, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D27__EMI_WEIM_D_27                IOMUX_PAD(0x490, 0x148, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D27__GPIO3_27                     IOMUX_PAD(0x490, 0x148, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D27__UART2_RXD_MUX                IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, 0)
-#define _MX53_PAD_EIM_D27__FIRI_TXD                     IOMUX_PAD(0x490, 0x148, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D27__IPU_CSI0_D_0         IOMUX_PAD(0x490, 0x148, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D27__IPU_DI1_PIN13                IOMUX_PAD(0x490, 0x148, 5, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D27__IPU_SISG_3           IOMUX_PAD(0x490, 0x148, 6, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D27__IPU_DISP1_DAT_23             IOMUX_PAD(0x490, 0x148, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D28__EMI_WEIM_D_28                IOMUX_PAD(0x494, 0x14C, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D28__GPIO3_28                     IOMUX_PAD(0x494, 0x14C, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D28__UART2_CTS                    IOMUX_PAD(0x494, 0x14C, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO   IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, 0)
-#define _MX53_PAD_EIM_D28__CSPI_MOSI                    IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, 0)
-#define _MX53_PAD_EIM_D28__I2C1_SDA                     IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, 0)
-#define _MX53_PAD_EIM_D28__IPU_EXT_TRIG         IOMUX_PAD(0x494, 0x14C, 6, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D28__IPU_DI0_PIN13                IOMUX_PAD(0x494, 0x14C, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D29__EMI_WEIM_D_29                IOMUX_PAD(0x498, 0x150, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D29__GPIO3_29                     IOMUX_PAD(0x498, 0x150, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D29__UART2_RTS                    IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, 0)
-#define _MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS    IOMUX_PAD(0x498, 0x150, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D29__CSPI_SS0                     IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, 0)
-#define _MX53_PAD_EIM_D29__IPU_DI1_PIN15                IOMUX_PAD(0x498, 0x150, 5, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D29__IPU_CSI1_VSYNC               IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, 0)
-#define _MX53_PAD_EIM_D29__IPU_DI0_PIN14                IOMUX_PAD(0x498, 0x150, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D30__EMI_WEIM_D_30                IOMUX_PAD(0x49C, 0x154, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D30__GPIO3_30                     IOMUX_PAD(0x49C, 0x154, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D30__UART3_CTS                    IOMUX_PAD(0x49C, 0x154, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D30__IPU_CSI0_D_3         IOMUX_PAD(0x49C, 0x154, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D30__IPU_DI0_PIN11                IOMUX_PAD(0x49C, 0x154, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D30__IPU_DISP1_DAT_21             IOMUX_PAD(0x49C, 0x154, 5, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D30__USBOH3_USBH1_OC              IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, 0)
-#define _MX53_PAD_EIM_D30__USBOH3_USBH2_OC              IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, 0)
-#define _MX53_PAD_EIM_D31__EMI_WEIM_D_31                IOMUX_PAD(0x4A0, 0x158, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D31__GPIO3_31                     IOMUX_PAD(0x4A0, 0x158, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D31__UART3_RTS                    IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, 0)
-#define _MX53_PAD_EIM_D31__IPU_CSI0_D_2         IOMUX_PAD(0x4A0, 0x158, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D31__IPU_DI0_PIN12                IOMUX_PAD(0x4A0, 0x158, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D31__IPU_DISP1_DAT_20             IOMUX_PAD(0x4A0, 0x158, 5, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D31__USBOH3_USBH1_PWR     IOMUX_PAD(0x4A0, 0x158, 6, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D31__USBOH3_USBH2_PWR     IOMUX_PAD(0x4A0, 0x158, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A24__EMI_WEIM_A_24                IOMUX_PAD(0x4A8, 0x15C, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A24__GPIO5_4                      IOMUX_PAD(0x4A8, 0x15C, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A24__IPU_DISP1_DAT_19             IOMUX_PAD(0x4A8, 0x15C, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A24__IPU_CSI1_D_19                IOMUX_PAD(0x4A8, 0x15C, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A24__IPU_SISG_2           IOMUX_PAD(0x4A8, 0x15C, 6, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A24__USBPHY2_BVALID               IOMUX_PAD(0x4A8, 0x15C, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A23__EMI_WEIM_A_23                IOMUX_PAD(0x4AC, 0x160, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A23__GPIO6_6                      IOMUX_PAD(0x4AC, 0x160, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A23__IPU_DISP1_DAT_18             IOMUX_PAD(0x4AC, 0x160, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A23__IPU_CSI1_D_18                IOMUX_PAD(0x4AC, 0x160, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A23__IPU_SISG_3           IOMUX_PAD(0x4AC, 0x160, 6, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A23__USBPHY2_ENDSESSION   IOMUX_PAD(0x4AC, 0x160, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A22__EMI_WEIM_A_22                IOMUX_PAD(0x4B0, 0x164, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A22__GPIO2_16                     IOMUX_PAD(0x4B0, 0x164, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A22__IPU_DISP1_DAT_17             IOMUX_PAD(0x4B0, 0x164, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A22__IPU_CSI1_D_17                IOMUX_PAD(0x4B0, 0x164, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A22__SRC_BT_CFG1_7                IOMUX_PAD(0x4B0, 0x164, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A21__EMI_WEIM_A_21                IOMUX_PAD(0x4B4, 0x168, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A21__GPIO2_17                     IOMUX_PAD(0x4B4, 0x168, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A21__IPU_DISP1_DAT_16             IOMUX_PAD(0x4B4, 0x168, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A21__IPU_CSI1_D_16                IOMUX_PAD(0x4B4, 0x168, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A21__SRC_BT_CFG1_6                IOMUX_PAD(0x4B4, 0x168, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A20__EMI_WEIM_A_20                IOMUX_PAD(0x4B8, 0x16C, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A20__GPIO2_18                     IOMUX_PAD(0x4B8, 0x16C, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A20__IPU_DISP1_DAT_15             IOMUX_PAD(0x4B8, 0x16C, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A20__IPU_CSI1_D_15                IOMUX_PAD(0x4B8, 0x16C, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A20__SRC_BT_CFG1_5                IOMUX_PAD(0x4B8, 0x16C, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A19__EMI_WEIM_A_19                IOMUX_PAD(0x4BC, 0x170, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A19__GPIO2_19                     IOMUX_PAD(0x4BC, 0x170, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A19__IPU_DISP1_DAT_14             IOMUX_PAD(0x4BC, 0x170, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A19__IPU_CSI1_D_14                IOMUX_PAD(0x4BC, 0x170, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A19__SRC_BT_CFG1_4                IOMUX_PAD(0x4BC, 0x170, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A18__EMI_WEIM_A_18                IOMUX_PAD(0x4C0, 0x174, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A18__GPIO2_20                     IOMUX_PAD(0x4C0, 0x174, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A18__IPU_DISP1_DAT_13             IOMUX_PAD(0x4C0, 0x174, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A18__IPU_CSI1_D_13                IOMUX_PAD(0x4C0, 0x174, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A18__SRC_BT_CFG1_3                IOMUX_PAD(0x4C0, 0x174, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A17__EMI_WEIM_A_17                IOMUX_PAD(0x4C4, 0x178, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A17__GPIO2_21                     IOMUX_PAD(0x4C4, 0x178, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A17__IPU_DISP1_DAT_12             IOMUX_PAD(0x4C4, 0x178, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A17__IPU_CSI1_D_12                IOMUX_PAD(0x4C4, 0x178, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A17__SRC_BT_CFG1_2                IOMUX_PAD(0x4C4, 0x178, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A16__EMI_WEIM_A_16                IOMUX_PAD(0x4C8, 0x17C, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A16__GPIO2_22                     IOMUX_PAD(0x4C8, 0x17C, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK             IOMUX_PAD(0x4C8, 0x17C, 2, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK              IOMUX_PAD(0x4C8, 0x17C, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_A16__SRC_BT_CFG1_1                IOMUX_PAD(0x4C8, 0x17C, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_CS0__EMI_WEIM_CS_0                IOMUX_PAD(0x4CC, 0x180, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_CS0__GPIO2_23                     IOMUX_PAD(0x4CC, 0x180, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_CS0__ECSPI2_SCLK          IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, 0)
-#define _MX53_PAD_EIM_CS0__IPU_DI1_PIN5         IOMUX_PAD(0x4CC, 0x180, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_CS1__EMI_WEIM_CS_1                IOMUX_PAD(0x4D0, 0x184, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_CS1__GPIO2_24                     IOMUX_PAD(0x4D0, 0x184, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_CS1__ECSPI2_MOSI          IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, 0)
-#define _MX53_PAD_EIM_CS1__IPU_DI1_PIN6         IOMUX_PAD(0x4D0, 0x184, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_OE__EMI_WEIM_OE           IOMUX_PAD(0x4D4, 0x188, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_OE__GPIO2_25                      IOMUX_PAD(0x4D4, 0x188, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_OE__ECSPI2_MISO           IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, 0)
-#define _MX53_PAD_EIM_OE__IPU_DI1_PIN7          IOMUX_PAD(0x4D4, 0x188, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_OE__USBPHY2_IDDIG         IOMUX_PAD(0x4D4, 0x188, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_RW__EMI_WEIM_RW           IOMUX_PAD(0x4D8, 0x18C, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_RW__GPIO2_26                      IOMUX_PAD(0x4D8, 0x18C, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_RW__ECSPI2_SS0                    IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, 0)
-#define _MX53_PAD_EIM_RW__IPU_DI1_PIN8          IOMUX_PAD(0x4D8, 0x18C, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT        IOMUX_PAD(0x4D8, 0x18C, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_LBA__EMI_WEIM_LBA         IOMUX_PAD(0x4DC, 0x190, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_LBA__GPIO2_27                     IOMUX_PAD(0x4DC, 0x190, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_LBA__ECSPI2_SS1           IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, 0)
-#define _MX53_PAD_EIM_LBA__IPU_DI1_PIN17                IOMUX_PAD(0x4DC, 0x190, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_LBA__SRC_BT_CFG1_0                IOMUX_PAD(0x4DC, 0x190, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB0__EMI_WEIM_EB_0                IOMUX_PAD(0x4E4, 0x194, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB0__GPIO2_28                     IOMUX_PAD(0x4E4, 0x194, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11             IOMUX_PAD(0x4E4, 0x194, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB0__IPU_CSI1_D_11                IOMUX_PAD(0x4E4, 0x194, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB0__GPC_PMIC_RDY         IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, 0)
-#define _MX53_PAD_EIM_EB0__SRC_BT_CFG2_7                IOMUX_PAD(0x4E4, 0x194, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB1__EMI_WEIM_EB_1                IOMUX_PAD(0x4E8, 0x198, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB1__GPIO2_29                     IOMUX_PAD(0x4E8, 0x198, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10             IOMUX_PAD(0x4E8, 0x198, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB1__IPU_CSI1_D_10                IOMUX_PAD(0x4E8, 0x198, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_EB1__SRC_BT_CFG2_6                IOMUX_PAD(0x4E8, 0x198, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0   IOMUX_PAD(0x4EC, 0x19C, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA0__GPIO3_0                      IOMUX_PAD(0x4EC, 0x19C, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9              IOMUX_PAD(0x4EC, 0x19C, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA0__IPU_CSI1_D_9         IOMUX_PAD(0x4EC, 0x19C, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA0__SRC_BT_CFG2_5                IOMUX_PAD(0x4EC, 0x19C, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1   IOMUX_PAD(0x4F0, 0x1A0, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA1__GPIO3_1                      IOMUX_PAD(0x4F0, 0x1A0, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8              IOMUX_PAD(0x4F0, 0x1A0, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA1__IPU_CSI1_D_8         IOMUX_PAD(0x4F0, 0x1A0, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA1__SRC_BT_CFG2_4                IOMUX_PAD(0x4F0, 0x1A0, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2   IOMUX_PAD(0x4F4, 0x1A4, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA2__GPIO3_2                      IOMUX_PAD(0x4F4, 0x1A4, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7              IOMUX_PAD(0x4F4, 0x1A4, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA2__IPU_CSI1_D_7         IOMUX_PAD(0x4F4, 0x1A4, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA2__SRC_BT_CFG2_3                IOMUX_PAD(0x4F4, 0x1A4, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3   IOMUX_PAD(0x4F8, 0x1A8, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA3__GPIO3_3                      IOMUX_PAD(0x4F8, 0x1A8, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6              IOMUX_PAD(0x4F8, 0x1A8, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA3__IPU_CSI1_D_6         IOMUX_PAD(0x4F8, 0x1A8, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA3__SRC_BT_CFG2_2                IOMUX_PAD(0x4F8, 0x1A8, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4   IOMUX_PAD(0x4FC, 0x1AC, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA4__GPIO3_4                      IOMUX_PAD(0x4FC, 0x1AC, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5              IOMUX_PAD(0x4FC, 0x1AC, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA4__IPU_CSI1_D_5         IOMUX_PAD(0x4FC, 0x1AC, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA4__SRC_BT_CFG3_7                IOMUX_PAD(0x4FC, 0x1AC, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5   IOMUX_PAD(0x500, 0x1B0, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA5__GPIO3_5                      IOMUX_PAD(0x500, 0x1B0, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4              IOMUX_PAD(0x500, 0x1B0, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA5__IPU_CSI1_D_4         IOMUX_PAD(0x500, 0x1B0, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA5__SRC_BT_CFG3_6                IOMUX_PAD(0x500, 0x1B0, 7 | IOMUX_CONFIG_SION, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6   IOMUX_PAD(0x504, 0x1B4, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA6__GPIO3_6                      IOMUX_PAD(0x504, 0x1B4, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3              IOMUX_PAD(0x504, 0x1B4, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA6__IPU_CSI1_D_3         IOMUX_PAD(0x504, 0x1B4, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA6__SRC_BT_CFG3_5                IOMUX_PAD(0x504, 0x1B4, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7   IOMUX_PAD(0x508, 0x1B8, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA7__GPIO3_7                      IOMUX_PAD(0x508, 0x1B8, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2              IOMUX_PAD(0x508, 0x1B8, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA7__IPU_CSI1_D_2         IOMUX_PAD(0x508, 0x1B8, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA7__SRC_BT_CFG3_4                IOMUX_PAD(0x508, 0x1B8, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8   IOMUX_PAD(0x50C, 0x1BC, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA8__GPIO3_8                      IOMUX_PAD(0x50C, 0x1BC, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1              IOMUX_PAD(0x50C, 0x1BC, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA8__IPU_CSI1_D_1         IOMUX_PAD(0x50C, 0x1BC, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA8__SRC_BT_CFG3_3                IOMUX_PAD(0x50C, 0x1BC, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9   IOMUX_PAD(0x510, 0x1C0, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA9__GPIO3_9                      IOMUX_PAD(0x510, 0x1C0, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0              IOMUX_PAD(0x510, 0x1C0, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA9__IPU_CSI1_D_0         IOMUX_PAD(0x510, 0x1C0, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA9__SRC_BT_CFG3_2                IOMUX_PAD(0x510, 0x1C0, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 IOMUX_PAD(0x514, 0x1C4, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA10__GPIO3_10                    IOMUX_PAD(0x514, 0x1C4, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA10__IPU_DI1_PIN15               IOMUX_PAD(0x514, 0x1C4, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN    IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, 0)
-#define _MX53_PAD_EIM_DA10__SRC_BT_CFG3_1               IOMUX_PAD(0x514, 0x1C4, 7, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 IOMUX_PAD(0x518, 0x1C8, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA11__GPIO3_11                    IOMUX_PAD(0x518, 0x1C8, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA11__IPU_DI1_PIN2                IOMUX_PAD(0x518, 0x1C8, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC              IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, 0)
-#define _MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 IOMUX_PAD(0x51C, 0x1CC, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA12__GPIO3_12                    IOMUX_PAD(0x51C, 0x1CC, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA12__IPU_DI1_PIN3                IOMUX_PAD(0x51C, 0x1CC, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC              IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, 0)
-#define _MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 IOMUX_PAD(0x520, 0x1D0, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA13__GPIO3_13                    IOMUX_PAD(0x520, 0x1D0, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA13__IPU_DI1_D0_CS               IOMUX_PAD(0x520, 0x1D0, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK             IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, 0)
-#define _MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 IOMUX_PAD(0x524, 0x1D4, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA14__GPIO3_14                    IOMUX_PAD(0x524, 0x1D4, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA14__IPU_DI1_D1_CS               IOMUX_PAD(0x524, 0x1D4, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK             IOMUX_PAD(0x524, 0x1D4, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 IOMUX_PAD(0x528, 0x1D8, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA15__GPIO3_15                    IOMUX_PAD(0x528, 0x1D8, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA15__IPU_DI1_PIN1                IOMUX_PAD(0x528, 0x1D8, 3, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA15__IPU_DI1_PIN4                IOMUX_PAD(0x528, 0x1D8, 4, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B    IOMUX_PAD(0x52C, 0x1DC, 0, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_WE_B__GPIO6_12          IOMUX_PAD(0x52C, 0x1DC, 1, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B    IOMUX_PAD(0x530, 0x1E0, 0, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_RE_B__GPIO6_13          IOMUX_PAD(0x530, 0x1E0, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT               IOMUX_PAD(0x534, 0x1E4, 0, 0x0, 0, 0)
-#define _MX53_PAD_EIM_WAIT__GPIO5_0                     IOMUX_PAD(0x534, 0x1E4, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B    IOMUX_PAD(0x534, 0x1E4, 2, 0x0, 0, 0)
-#define _MX53_PAD_LVDS1_TX3_P__GPIO6_22         IOMUX_PAD(NON_PAD_I, 0x1EC, 0, 0x0, 0, 0)
-#define _MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3    IOMUX_PAD(NON_PAD_I, 0x1EC, 1, 0x0, 0, 0)
-#define _MX53_PAD_LVDS1_TX2_P__GPIO6_24         IOMUX_PAD(NON_PAD_I, 0x1F0, 0, 0x0, 0, 0)
-#define _MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2    IOMUX_PAD(NON_PAD_I, 0x1F0, 1, 0x0, 0, 0)
-#define _MX53_PAD_LVDS1_CLK_P__GPIO6_26         IOMUX_PAD(NON_PAD_I, 0x1F4, 0, 0x0, 0, 0)
-#define _MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK    IOMUX_PAD(NON_PAD_I, 0x1F4, 1, 0x0, 0, 0)
-#define _MX53_PAD_LVDS1_TX1_P__GPIO6_28         IOMUX_PAD(NON_PAD_I, 0x1F8, 0, 0x0, 0, 0)
-#define _MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1    IOMUX_PAD(NON_PAD_I, 0x1F8, 1, 0x0, 0, 0)
-#define _MX53_PAD_LVDS1_TX0_P__GPIO6_30         IOMUX_PAD(NON_PAD_I, 0x1FC, 0, 0x0, 0, 0)
-#define _MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0    IOMUX_PAD(NON_PAD_I, 0x1FC, 1, 0x0, 0, 0)
-#define _MX53_PAD_LVDS0_TX3_P__GPIO7_22         IOMUX_PAD(NON_PAD_I, 0x200, 0, 0x0, 0, 0)
-#define _MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3    IOMUX_PAD(NON_PAD_I, 0x200, 1, 0x0, 0, 0)
-#define _MX53_PAD_LVDS0_CLK_P__GPIO7_24         IOMUX_PAD(NON_PAD_I, 0x204, 0, 0x0, 0, 0)
-#define _MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK    IOMUX_PAD(NON_PAD_I, 0x204, 1, 0x0, 0, 0)
-#define _MX53_PAD_LVDS0_TX2_P__GPIO7_26         IOMUX_PAD(NON_PAD_I, 0x208, 0, 0x0, 0, 0)
-#define _MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2    IOMUX_PAD(NON_PAD_I, 0x208, 1, 0x0, 0, 0)
-#define _MX53_PAD_LVDS0_TX1_P__GPIO7_28         IOMUX_PAD(NON_PAD_I, 0x20C, 0, 0x0, 0, 0)
-#define _MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1    IOMUX_PAD(NON_PAD_I, 0x20C, 1, 0x0, 0, 0)
-#define _MX53_PAD_LVDS0_TX0_P__GPIO7_30         IOMUX_PAD(NON_PAD_I, 0x210, 0, 0x0, 0, 0)
-#define _MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0    IOMUX_PAD(NON_PAD_I, 0x210, 1, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_10__GPIO4_0                      IOMUX_PAD(0x540, 0x214, 0, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_10__OSC32k_32K_OUT               IOMUX_PAD(0x540, 0x214, 1, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_11__GPIO4_1                      IOMUX_PAD(0x544, 0x218, 0, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_12__GPIO4_2                      IOMUX_PAD(0x548, 0x21C, 0, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_13__GPIO4_3                      IOMUX_PAD(0x54C, 0x220, 0, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_14__GPIO4_4                      IOMUX_PAD(0x550, 0x224, 0, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CLE__EMI_NANDF_CLE              IOMUX_PAD(0x5A0, 0x228, 0, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CLE__GPIO6_7                    IOMUX_PAD(0x5A0, 0x228, 1, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0  IOMUX_PAD(0x5A0, 0x228, 7, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_ALE__EMI_NANDF_ALE              IOMUX_PAD(0x5A4, 0x22C, 0, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_ALE__GPIO6_8            IOMUX_PAD(0x5A4, 0x22C, 1, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1  IOMUX_PAD(0x5A4, 0x22C, 7, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B    IOMUX_PAD(0x5A8, 0x230, 0, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_WP_B__GPIO6_9           IOMUX_PAD(0x5A8, 0x230, 1, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 IOMUX_PAD(0x5A8, 0x230, 7, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0     IOMUX_PAD(0x5AC, 0x234, 0, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_RB0__GPIO6_10           IOMUX_PAD(0x5AC, 0x234, 1, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3  IOMUX_PAD(0x5AC, 0x234, 7, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0     IOMUX_PAD(0x5B0, 0x238, 0, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS0__GPIO6_11           IOMUX_PAD(0x5B0, 0x238, 1, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4  IOMUX_PAD(0x5B0, 0x238, 7, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1     IOMUX_PAD(0x5B4, 0x23C, 0, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS1__GPIO6_14           IOMUX_PAD(0x5B4, 0x23C, 1, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS1__MLB_MLBCLK         IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, 0)
-#define _MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5  IOMUX_PAD(0x5B4, 0x23C, 7, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2     IOMUX_PAD(0x5B8, 0x240, 0, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS2__GPIO6_15           IOMUX_PAD(0x5B8, 0x240, 1, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS2__IPU_SISG_0         IOMUX_PAD(0x5B8, 0x240, 2, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS2__ESAI1_TX0          IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, 0)
-#define _MX53_PAD_NANDF_CS2__EMI_WEIM_CRE               IOMUX_PAD(0x5B8, 0x240, 4, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK              IOMUX_PAD(0x5B8, 0x240, 5, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS2__MLB_MLBSIG         IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, 0)
-#define _MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6  IOMUX_PAD(0x5B8, 0x240, 7, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3     IOMUX_PAD(0x5BC, 0x244, 0, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS3__GPIO6_16           IOMUX_PAD(0x5BC, 0x244, 1, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS3__IPU_SISG_1         IOMUX_PAD(0x5BC, 0x244, 2, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS3__ESAI1_TX1          IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, 0)
-#define _MX53_PAD_NANDF_CS3__EMI_WEIM_A_26              IOMUX_PAD(0x5BC, 0x244, 4, 0x0, 0, 0)
-#define _MX53_PAD_NANDF_CS3__MLB_MLBDAT         IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, 0)
-#define _MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7  IOMUX_PAD(0x5BC, 0x244, 7, 0x0, 0, 0)
-#define _MX53_PAD_FEC_MDIO__FEC_MDIO            IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, 0)
-#define _MX53_PAD_FEC_MDIO__GPIO1_22                    IOMUX_PAD(0x5C4, 0x248, 1, 0x0, 0, 0)
-#define _MX53_PAD_FEC_MDIO__ESAI1_SCKR          IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, 0)
-#define _MX53_PAD_FEC_MDIO__FEC_COL                     IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, 0)
-#define _MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2              IOMUX_PAD(0x5C4, 0x248, 4, 0x0, 0, 0)
-#define _MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3     IOMUX_PAD(0x5C4, 0x248, 5, 0x0, 0, 0)
-#define _MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49    IOMUX_PAD(0x5C4, 0x248, 6, 0x0, 0, 0)
-#define _MX53_PAD_FEC_REF_CLK__FEC_TX_CLK               IOMUX_PAD(0x5C8, 0x24C, 0, 0x0, 0, 0)
-#define _MX53_PAD_FEC_REF_CLK__GPIO1_23         IOMUX_PAD(0x5C8, 0x24C, 1, 0x0, 0, 0)
-#define _MX53_PAD_FEC_REF_CLK__ESAI1_FSR                IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, 0)
-#define _MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4  IOMUX_PAD(0x5C8, 0x24C, 5, 0x0, 0, 0)
-#define _MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 IOMUX_PAD(0x5C8, 0x24C, 6, 0x0, 0, 0)
-#define _MX53_PAD_FEC_RX_ER__FEC_RX_ER          IOMUX_PAD(0x5CC, 0x250, 0, 0x0, 0, 0)
-#define _MX53_PAD_FEC_RX_ER__GPIO1_24           IOMUX_PAD(0x5CC, 0x250, 1, 0x0, 0, 0)
-#define _MX53_PAD_FEC_RX_ER__ESAI1_HCKR         IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, 0)
-#define _MX53_PAD_FEC_RX_ER__FEC_RX_CLK         IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, 0)
-#define _MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3             IOMUX_PAD(0x5CC, 0x250, 4, 0x0, 0, 0)
-#define _MX53_PAD_FEC_CRS_DV__FEC_RX_DV         IOMUX_PAD(0x5D0, 0x254, 0, 0x0, 0, 0)
-#define _MX53_PAD_FEC_CRS_DV__GPIO1_25          IOMUX_PAD(0x5D0, 0x254, 1, 0x0, 0, 0)
-#define _MX53_PAD_FEC_CRS_DV__ESAI1_SCKT                IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, 0)
-#define _MX53_PAD_FEC_RXD1__FEC_RDATA_1         IOMUX_PAD(0x5D4, 0x258, 0, 0x0, 0, 0)
-#define _MX53_PAD_FEC_RXD1__GPIO1_26                    IOMUX_PAD(0x5D4, 0x258, 1, 0x0, 0, 0)
-#define _MX53_PAD_FEC_RXD1__ESAI1_FST           IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, 0)
-#define _MX53_PAD_FEC_RXD1__MLB_MLBSIG          IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, 0)
-#define _MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1              IOMUX_PAD(0x5D4, 0x258, 4, 0x0, 0, 0)
-#define _MX53_PAD_FEC_RXD0__FEC_RDATA_0         IOMUX_PAD(0x5D8, 0x25C, 0, 0x0, 0, 0)
-#define _MX53_PAD_FEC_RXD0__GPIO1_27                    IOMUX_PAD(0x5D8, 0x25C, 1, 0x0, 0, 0)
-#define _MX53_PAD_FEC_RXD0__ESAI1_HCKT          IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, 0)
-#define _MX53_PAD_FEC_RXD0__OSC32k_32K_OUT              IOMUX_PAD(0x5D8, 0x25C, 3, 0x0, 0, 0)
-#define _MX53_PAD_FEC_TX_EN__FEC_TX_EN          IOMUX_PAD(0x5DC, 0x260, 0, 0x0, 0, 0)
-#define _MX53_PAD_FEC_TX_EN__GPIO1_28           IOMUX_PAD(0x5DC, 0x260, 1, 0x0, 0, 0)
-#define _MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2              IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, 0)
-#define _MX53_PAD_FEC_TXD1__FEC_TDATA_1         IOMUX_PAD(0x5E0, 0x264, 0, 0x0, 0, 0)
-#define _MX53_PAD_FEC_TXD1__GPIO1_29                    IOMUX_PAD(0x5E0, 0x264, 1, 0x0, 0, 0)
-#define _MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3               IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, 0)
-#define _MX53_PAD_FEC_TXD1__MLB_MLBCLK          IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, 0)
-#define _MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK IOMUX_PAD(0x5E0, 0x264, 4, 0x0, 0, 0)
-#define _MX53_PAD_FEC_TXD0__FEC_TDATA_0         IOMUX_PAD(0x5E4, 0x268, 0, 0x0, 0, 0)
-#define _MX53_PAD_FEC_TXD0__GPIO1_30                    IOMUX_PAD(0x5E4, 0x268, 1, 0x0, 0, 0)
-#define _MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1               IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, 0)
-#define _MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0   IOMUX_PAD(0x5E4, 0x268, 7, 0x0, 0, 0)
-#define _MX53_PAD_FEC_MDC__FEC_MDC                      IOMUX_PAD(0x5E8, 0x26C, 0, 0x0, 0, 0)
-#define _MX53_PAD_FEC_MDC__GPIO1_31                     IOMUX_PAD(0x5E8, 0x26C, 1, 0x0, 0, 0)
-#define _MX53_PAD_FEC_MDC__ESAI1_TX5_RX0                IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, 0)
-#define _MX53_PAD_FEC_MDC__MLB_MLBDAT           IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, 0)
-#define _MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG       IOMUX_PAD(0x5E8, 0x26C, 4, 0x0, 0, 0)
-#define _MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1    IOMUX_PAD(0x5E8, 0x26C, 7, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DIOW__PATA_DIOW          IOMUX_PAD(0x5F0, 0x270, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DIOW__GPIO6_17           IOMUX_PAD(0x5F0, 0x270, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DIOW__UART1_TXD_MUX      IOMUX_PAD(0x5F0, 0x270, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2  IOMUX_PAD(0x5F0, 0x270, 7, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DMACK__PATA_DMACK                IOMUX_PAD(0x5F4, 0x274, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DMACK__GPIO6_18          IOMUX_PAD(0x5F4, 0x274, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DMACK__UART1_RXD_MUX     IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, 0)
-#define _MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 IOMUX_PAD(0x5F4, 0x274, 7, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DMARQ__PATA_DMARQ                IOMUX_PAD(0x5F8, 0x278, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DMARQ__GPIO7_0           IOMUX_PAD(0x5F8, 0x278, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DMARQ__UART2_TXD_MUX     IOMUX_PAD(0x5F8, 0x278, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0     IOMUX_PAD(0x5F8, 0x278, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 IOMUX_PAD(0x5F8, 0x278, 7, 0x0, 0, 0)
-#define _MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN        IOMUX_PAD(0x5FC, 0x27C, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_BUFFER_EN__GPIO7_1               IOMUX_PAD(0x5FC, 0x27C, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, 0)
-#define _MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 IOMUX_PAD(0x5FC, 0x27C, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5     IOMUX_PAD(0x5FC, 0x27C, 7, 0x0, 0, 0)
-#define _MX53_PAD_PATA_INTRQ__PATA_INTRQ                IOMUX_PAD(0x600, 0x280, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_INTRQ__GPIO7_2           IOMUX_PAD(0x600, 0x280, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_INTRQ__UART2_CTS         IOMUX_PAD(0x600, 0x280, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_INTRQ__CAN1_TXCAN                IOMUX_PAD(0x600, 0x280, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2     IOMUX_PAD(0x600, 0x280, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 IOMUX_PAD(0x600, 0x280, 7, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DIOR__PATA_DIOR          IOMUX_PAD(0x604, 0x284, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DIOR__GPIO7_3                    IOMUX_PAD(0x604, 0x284, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DIOR__UART2_RTS          IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, 0)
-#define _MX53_PAD_PATA_DIOR__CAN1_RXCAN         IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, 0)
-#define _MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7  IOMUX_PAD(0x604, 0x284, 7, 0x0, 0, 0)
-#define _MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B       IOMUX_PAD(0x608, 0x288, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_RESET_B__GPIO7_4         IOMUX_PAD(0x608, 0x288, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_RESET_B__ESDHC3_CMD              IOMUX_PAD(0x608, 0x288, 2, 0x0, 0, 0)
-#define _MX53_PAD_PATA_RESET_B__UART1_CTS               IOMUX_PAD(0x608, 0x288, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_RESET_B__CAN2_TXCAN              IOMUX_PAD(0x608, 0x288, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0       IOMUX_PAD(0x608, 0x288, 7, 0x0, 0, 0)
-#define _MX53_PAD_PATA_IORDY__PATA_IORDY                IOMUX_PAD(0x60C, 0x28C, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_IORDY__GPIO7_5           IOMUX_PAD(0x60C, 0x28C, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_IORDY__ESDHC3_CLK                IOMUX_PAD(0x60C, 0x28C, 2, 0x0, 0, 0)
-#define _MX53_PAD_PATA_IORDY__UART1_RTS         IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, 0)
-#define _MX53_PAD_PATA_IORDY__CAN2_RXCAN                IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, 0)
-#define _MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 IOMUX_PAD(0x60C, 0x28C, 7, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DA_0__PATA_DA_0          IOMUX_PAD(0x610, 0x290, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DA_0__GPIO7_6            IOMUX_PAD(0x610, 0x290, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DA_0__ESDHC3_RST         IOMUX_PAD(0x610, 0x290, 2, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DA_0__OWIRE_LINE         IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, 0)
-#define _MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2  IOMUX_PAD(0x610, 0x290, 7, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DA_1__PATA_DA_1          IOMUX_PAD(0x614, 0x294, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DA_1__GPIO7_7            IOMUX_PAD(0x614, 0x294, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DA_1__ESDHC4_CMD         IOMUX_PAD(0x614, 0x294, 2, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DA_1__UART3_CTS          IOMUX_PAD(0x614, 0x294, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3  IOMUX_PAD(0x614, 0x294, 7, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DA_2__PATA_DA_2          IOMUX_PAD(0x618, 0x298, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DA_2__GPIO7_8            IOMUX_PAD(0x618, 0x298, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DA_2__ESDHC4_CLK         IOMUX_PAD(0x618, 0x298, 2, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DA_2__UART3_RTS          IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, 0)
-#define _MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4  IOMUX_PAD(0x618, 0x298, 7, 0x0, 0, 0)
-#define _MX53_PAD_PATA_CS_0__PATA_CS_0          IOMUX_PAD(0x61C, 0x29C, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_CS_0__GPIO7_9                    IOMUX_PAD(0x61C, 0x29C, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_CS_0__UART3_TXD_MUX              IOMUX_PAD(0x61C, 0x29C, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5  IOMUX_PAD(0x61C, 0x29C, 7, 0x0, 0, 0)
-#define _MX53_PAD_PATA_CS_1__PATA_CS_1          IOMUX_PAD(0x620, 0x2A0, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_CS_1__GPIO7_10           IOMUX_PAD(0x620, 0x2A0, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_CS_1__UART3_RXD_MUX              IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, 0)
-#define _MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6  IOMUX_PAD(0x620, 0x2A0, 7, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA0__PATA_DATA_0               IOMUX_PAD(0x628, 0x2A4, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA0__GPIO2_0           IOMUX_PAD(0x628, 0x2A4, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA0__EMI_NANDF_D_0     IOMUX_PAD(0x628, 0x2A4, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA0__ESDHC3_DAT4               IOMUX_PAD(0x628, 0x2A4, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0     IOMUX_PAD(0x628, 0x2A4, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0    IOMUX_PAD(0x628, 0x2A4, 6, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 IOMUX_PAD(0x628, 0x2A4, 7, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA1__PATA_DATA_1               IOMUX_PAD(0x62C, 0x2A8, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA1__GPIO2_1           IOMUX_PAD(0x62C, 0x2A8, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA1__EMI_NANDF_D_1     IOMUX_PAD(0x62C, 0x2A8, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA1__ESDHC3_DAT5               IOMUX_PAD(0x62C, 0x2A8, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1     IOMUX_PAD(0x62C, 0x2A8, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1    IOMUX_PAD(0x62C, 0x2A8, 6, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA2__PATA_DATA_2               IOMUX_PAD(0x630, 0x2AC, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA2__GPIO2_2           IOMUX_PAD(0x630, 0x2AC, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA2__EMI_NANDF_D_2     IOMUX_PAD(0x630, 0x2AC, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA2__ESDHC3_DAT6               IOMUX_PAD(0x630, 0x2AC, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2     IOMUX_PAD(0x630, 0x2AC, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2    IOMUX_PAD(0x630, 0x2AC, 6, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA3__PATA_DATA_3               IOMUX_PAD(0x634, 0x2B0, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA3__GPIO2_3           IOMUX_PAD(0x634, 0x2B0, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA3__EMI_NANDF_D_3     IOMUX_PAD(0x634, 0x2B0, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA3__ESDHC3_DAT7               IOMUX_PAD(0x634, 0x2B0, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3     IOMUX_PAD(0x634, 0x2B0, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3    IOMUX_PAD(0x634, 0x2B0, 6, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA4__PATA_DATA_4               IOMUX_PAD(0x638, 0x2B4, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA4__GPIO2_4           IOMUX_PAD(0x638, 0x2B4, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA4__EMI_NANDF_D_4     IOMUX_PAD(0x638, 0x2B4, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA4__ESDHC4_DAT4               IOMUX_PAD(0x638, 0x2B4, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4     IOMUX_PAD(0x638, 0x2B4, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4    IOMUX_PAD(0x638, 0x2B4, 6, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA5__PATA_DATA_5       IOMUX_PAD(0x63C, 0x2B8, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA5__GPIO2_5           IOMUX_PAD(0x63C, 0x2B8, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA5__EMI_NANDF_D_5     IOMUX_PAD(0x63C, 0x2B8, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA5__ESDHC4_DAT5               IOMUX_PAD(0x63C, 0x2B8, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5     IOMUX_PAD(0x63C, 0x2B8, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5    IOMUX_PAD(0x63C, 0x2B8, 6, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA6__PATA_DATA_6       IOMUX_PAD(0x640, 0x2BC, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA6__GPIO2_6           IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA6__EMI_NANDF_D_6     IOMUX_PAD(0x640, 0x2BC, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA6__ESDHC4_DAT6               IOMUX_PAD(0x640, 0x2BC, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6     IOMUX_PAD(0x640, 0x2BC, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6    IOMUX_PAD(0x640, 0x2BC, 6, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA7__PATA_DATA_7               IOMUX_PAD(0x644, 0x2C0, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA7__GPIO2_7           IOMUX_PAD(0x644, 0x2C0, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA7__EMI_NANDF_D_7     IOMUX_PAD(0x644, 0x2C0, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA7__ESDHC4_DAT7               IOMUX_PAD(0x644, 0x2C0, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7     IOMUX_PAD(0x644, 0x2C0, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7    IOMUX_PAD(0x644, 0x2C0, 6, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA8__PATA_DATA_8               IOMUX_PAD(0x648, 0x2C4, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA8__GPIO2_8           IOMUX_PAD(0x648, 0x2C4, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA8__ESDHC1_DAT4               IOMUX_PAD(0x648, 0x2C4, 2, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA8__EMI_NANDF_D_8     IOMUX_PAD(0x648, 0x2C4, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA8__ESDHC3_DAT0               IOMUX_PAD(0x648, 0x2C4, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8     IOMUX_PAD(0x648, 0x2C4, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8    IOMUX_PAD(0x648, 0x2C4, 6, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA9__PATA_DATA_9               IOMUX_PAD(0x64C, 0x2C8, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA9__GPIO2_9           IOMUX_PAD(0x64C, 0x2C8, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA9__ESDHC1_DAT5               IOMUX_PAD(0x64C, 0x2C8, 2, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA9__EMI_NANDF_D_9     IOMUX_PAD(0x64C, 0x2C8, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA9__ESDHC3_DAT1               IOMUX_PAD(0x64C, 0x2C8, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9     IOMUX_PAD(0x64C, 0x2C8, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9    IOMUX_PAD(0x64C, 0x2C8, 6, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA10__PATA_DATA_10     IOMUX_PAD(0x650, 0x2CC, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA10__GPIO2_10         IOMUX_PAD(0x650, 0x2CC, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA10__ESDHC1_DAT6              IOMUX_PAD(0x650, 0x2CC, 2, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA10__EMI_NANDF_D_10   IOMUX_PAD(0x650, 0x2CC, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA10__ESDHC3_DAT2              IOMUX_PAD(0x650, 0x2CC, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10   IOMUX_PAD(0x650, 0x2CC, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10  IOMUX_PAD(0x650, 0x2CC, 6, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA11__PATA_DATA_11     IOMUX_PAD(0x654, 0x2D0, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA11__GPIO2_11         IOMUX_PAD(0x654, 0x2D0, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA11__ESDHC1_DAT7              IOMUX_PAD(0x654, 0x2D0, 2, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA11__EMI_NANDF_D_11   IOMUX_PAD(0x654, 0x2D0, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA11__ESDHC3_DAT3              IOMUX_PAD(0x654, 0x2D0, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11   IOMUX_PAD(0x654, 0x2D0, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11  IOMUX_PAD(0x654, 0x2D0, 6, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA12__PATA_DATA_12     IOMUX_PAD(0x658, 0x2D4, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA12__GPIO2_12         IOMUX_PAD(0x658, 0x2D4, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA12__ESDHC2_DAT4              IOMUX_PAD(0x658, 0x2D4, 2, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA12__EMI_NANDF_D_12   IOMUX_PAD(0x658, 0x2D4, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA12__ESDHC4_DAT0              IOMUX_PAD(0x658, 0x2D4, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12   IOMUX_PAD(0x658, 0x2D4, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12  IOMUX_PAD(0x658, 0x2D4, 6, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA13__PATA_DATA_13     IOMUX_PAD(0x65C, 0x2D8, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA13__GPIO2_13         IOMUX_PAD(0x65C, 0x2D8, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA13__ESDHC2_DAT5              IOMUX_PAD(0x65C, 0x2D8, 2, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA13__EMI_NANDF_D_13   IOMUX_PAD(0x65C, 0x2D8, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA13__ESDHC4_DAT1              IOMUX_PAD(0x65C, 0x2D8, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13   IOMUX_PAD(0x65C, 0x2D8, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13  IOMUX_PAD(0x65C, 0x2D8, 6, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA14__PATA_DATA_14     IOMUX_PAD(0x660, 0x2DC, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA14__GPIO2_14         IOMUX_PAD(0x660, 0x2DC, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA14__ESDHC2_DAT6              IOMUX_PAD(0x660, 0x2DC, 2, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA14__EMI_NANDF_D_14   IOMUX_PAD(0x660, 0x2DC, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA14__ESDHC4_DAT2              IOMUX_PAD(0x660, 0x2DC, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14   IOMUX_PAD(0x660, 0x2DC, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14  IOMUX_PAD(0x660, 0x2DC, 6, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA15__PATA_DATA_15     IOMUX_PAD(0x664, 0x2E0, 0, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA15__GPIO2_15         IOMUX_PAD(0x664, 0x2E0, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA15__ESDHC2_DAT7              IOMUX_PAD(0x664, 0x2E0, 2, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA15__EMI_NANDF_D_15   IOMUX_PAD(0x664, 0x2E0, 3, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA15__ESDHC4_DAT3              IOMUX_PAD(0x664, 0x2E0, 4, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15   IOMUX_PAD(0x664, 0x2E0, 5, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15  IOMUX_PAD(0x664, 0x2E0, 6, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA0__ESDHC1_DAT0        IOMUX_PAD(0x66C, 0x2E4, 0, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA0__GPIO1_16   IOMUX_PAD(0x66C, 0x2E4, 1, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA0__GPT_CAPIN1 IOMUX_PAD(0x66C, 0x2E4, 3, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA0__CSPI_MISO  IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, 0)
-#define _MX53_PAD_SD1_DATA0__CCM_PLL3_BYP       IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, 0)
-#define _MX53_PAD_SD1_DATA1__ESDHC1_DAT1        IOMUX_PAD(0x670, 0x2E8, 0, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA1__GPIO1_17   IOMUX_PAD(0x670, 0x2E8, 1, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA1__GPT_CAPIN2 IOMUX_PAD(0x670, 0x2E8, 3, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA1__CSPI_SS0   IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, 0)
-#define _MX53_PAD_SD1_DATA1__CCM_PLL4_BYP       IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, 0)
-#define _MX53_PAD_SD1_CMD__ESDHC1_CMD   IOMUX_PAD(0x674, 0x2EC, IOMUX_CONFIG_SION, 0x0, 0, 0)
-#define _MX53_PAD_SD1_CMD__GPIO1_18             IOMUX_PAD(0x674, 0x2EC, 1, 0x0, 0, 0)
-#define _MX53_PAD_SD1_CMD__GPT_CMPOUT1  IOMUX_PAD(0x674, 0x2EC, 3, 0x0, 0, 0)
-#define _MX53_PAD_SD1_CMD__CSPI_MOSI            IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, 0)
-#define _MX53_PAD_SD1_CMD__CCM_PLL1_BYP IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, 0)
-#define _MX53_PAD_SD1_DATA2__ESDHC1_DAT2                IOMUX_PAD(0x678, 0x2F0, 0, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA2__GPIO1_19           IOMUX_PAD(0x678, 0x2F0, 1, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA2__GPT_CMPOUT2                IOMUX_PAD(0x678, 0x2F0, 2, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA2__PWM2_PWMO          IOMUX_PAD(0x678, 0x2F0, 3, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA2__WDOG1_WDOG_B               IOMUX_PAD(0x678, 0x2F0, 4, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA2__CSPI_SS1           IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, 0)
-#define _MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB       IOMUX_PAD(0x678, 0x2F0, 6, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA2__CCM_PLL2_BYP               IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, 0)
-#define _MX53_PAD_SD1_CLK__ESDHC1_CLK   IOMUX_PAD(0x67C, 0x2F4, 0, 0x0, 0, 0)
-#define _MX53_PAD_SD1_CLK__GPIO1_20             IOMUX_PAD(0x67C, 0x2F4, 1, 0x0, 0, 0)
-#define _MX53_PAD_SD1_CLK__OSC32k_32K_OUT       IOMUX_PAD(0x67C, 0x2F4, 2, 0x0, 0, 0)
-#define _MX53_PAD_SD1_CLK__GPT_CLKIN            IOMUX_PAD(0x67C, 0x2F4, 3, 0x0, 0, 0)
-#define _MX53_PAD_SD1_CLK__CSPI_SCLK            IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, 0)
-#define _MX53_PAD_SD1_CLK__SATA_PHY_DTB_0       IOMUX_PAD(0x67C, 0x2F4, 7, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA3__ESDHC1_DAT3        IOMUX_PAD(0x680, 0x2F8, 0, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA3__GPIO1_21   IOMUX_PAD(0x680, 0x2F8, 1, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA3__GPT_CMPOUT3        IOMUX_PAD(0x680, 0x2F8, 2, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA3__PWM1_PWMO  IOMUX_PAD(0x680, 0x2F8, 3, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA3__WDOG2_WDOG_B       IOMUX_PAD(0x680, 0x2F8, 4, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA3__CSPI_SS2   IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, 0)
-#define _MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB       IOMUX_PAD(0x680, 0x2F8, 6, 0x0, 0, 0)
-#define _MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1     IOMUX_PAD(0x680, 0x2F8, 7, 0x0, 0, 0)
-#define _MX53_PAD_SD2_CLK__ESDHC2_CLK   IOMUX_PAD(0x688, 0x2FC, 0, 0x0, 0, 0)
-#define _MX53_PAD_SD2_CLK__GPIO1_10             IOMUX_PAD(0x688, 0x2FC, 1, 0x0, 0, 0)
-#define _MX53_PAD_SD2_CLK__KPP_COL_5            IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, 0)
-#define _MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS     IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, 0)
-#define _MX53_PAD_SD2_CLK__CSPI_SCLK            IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, 0)
-#define _MX53_PAD_SD2_CLK__SCC_RANDOM_V IOMUX_PAD(0x688, 0x2FC, 7, 0x0, 0, 0)
-#define _MX53_PAD_SD2_CMD__ESDHC2_CMD   IOMUX_PAD(0x68C, 0x300, 0, 0x0, 0, 0)
-#define _MX53_PAD_SD2_CMD__GPIO1_11             IOMUX_PAD(0x68C, 0x300, 1, 0x0, 0, 0)
-#define _MX53_PAD_SD2_CMD__KPP_ROW_5    IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, 0)
-#define _MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC      IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, 0)
-#define _MX53_PAD_SD2_CMD__CSPI_MOSI            IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, 0)
-#define _MX53_PAD_SD2_CMD__SCC_RANDOM   IOMUX_PAD(0x68C, 0x300, 7, 0x0, 0, 0)
-#define _MX53_PAD_SD2_DATA3__ESDHC2_DAT3        IOMUX_PAD(0x690, 0x304, 0, 0x0, 0, 0)
-#define _MX53_PAD_SD2_DATA3__GPIO1_12   IOMUX_PAD(0x690, 0x304, 1, 0x0, 0, 0)
-#define _MX53_PAD_SD2_DATA3__KPP_COL_6  IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, 0)
-#define _MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC    IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, 0)
-#define _MX53_PAD_SD2_DATA3__CSPI_SS2   IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, 0)
-#define _MX53_PAD_SD2_DATA3__SJC_DONE   IOMUX_PAD(0x690, 0x304, 7, 0x0, 0, 0)
-#define _MX53_PAD_SD2_DATA2__ESDHC2_DAT2        IOMUX_PAD(0x694, 0x308, 0, 0x0, 0, 0)
-#define _MX53_PAD_SD2_DATA2__GPIO1_13   IOMUX_PAD(0x694, 0x308, 1, 0x0, 0, 0)
-#define _MX53_PAD_SD2_DATA2__KPP_ROW_6  IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, 0)
-#define _MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD    IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, 0)
-#define _MX53_PAD_SD2_DATA2__CSPI_SS1   IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, 0)
-#define _MX53_PAD_SD2_DATA2__SJC_FAIL   IOMUX_PAD(0x694, 0x308, 7, 0x0, 0, 0)
-#define _MX53_PAD_SD2_DATA1__ESDHC2_DAT1        IOMUX_PAD(0x698, 0x30C, 0, 0x0, 0, 0)
-#define _MX53_PAD_SD2_DATA1__GPIO1_14   IOMUX_PAD(0x698, 0x30C, 1, 0x0, 0, 0)
-#define _MX53_PAD_SD2_DATA1__KPP_COL_7  IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, 0)
-#define _MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS   IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, 0)
-#define _MX53_PAD_SD2_DATA1__CSPI_SS0   IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, 0)
-#define _MX53_PAD_SD2_DATA1__RTIC_SEC_VIO       IOMUX_PAD(0x698, 0x30C, 7, 0x0, 0, 0)
-#define _MX53_PAD_SD2_DATA0__ESDHC2_DAT0        IOMUX_PAD(0x69C, 0x310, 0, 0x0, 0, 0)
-#define _MX53_PAD_SD2_DATA0__GPIO1_15   IOMUX_PAD(0x69C, 0x310, 1, 0x0, 0, 0)
-#define _MX53_PAD_SD2_DATA0__KPP_ROW_7  IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, 0)
-#define _MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD    IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, 0)
-#define _MX53_PAD_SD2_DATA0__CSPI_MISO  IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, 0)
-#define _MX53_PAD_SD2_DATA0__RTIC_DONE_INT      IOMUX_PAD(0x69C, 0x310, 7, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_0__CCM_CLKO              IOMUX_PAD(0x6A4, 0x314, 0, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_0__GPIO1_0               IOMUX_PAD(0x6A4, 0x314, 1, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_0__KPP_COL_5             IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, 0)
-#define _MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK      IOMUX_PAD(0x6A4, 0x314, 3, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_0__EPIT1_EPITO   IOMUX_PAD(0x6A4, 0x314, 4, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_0__SRTC_ALARM_DEB        IOMUX_PAD(0x6A4, 0x314, 5, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_0__USBOH3_USBH1_PWR      IOMUX_PAD(0x6A4, 0x314, 6, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_0__CSU_TD                IOMUX_PAD(0x6A4, 0x314, 7, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_1__ESAI1_SCKR            IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, 0)
-#define _MX53_PAD_GPIO_1__GPIO1_1               IOMUX_PAD(0x6A8, 0x318, 1, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_1__KPP_ROW_5             IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, 0)
-#define _MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK      IOMUX_PAD(0x6A8, 0x318, 3, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_1__PWM2_PWMO     IOMUX_PAD(0x6A8, 0x318, 4, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_1__WDOG2_WDOG_B  IOMUX_PAD(0x6A8, 0x318, 5, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_1__ESDHC1_CD             IOMUX_PAD(0x6A8, 0x318, 6, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_1__SRC_TESTER_ACK        IOMUX_PAD(0x6A8, 0x318, 7, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_9__ESAI1_FSR             IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, 0)
-#define _MX53_PAD_GPIO_9__GPIO1_9               IOMUX_PAD(0x6AC, 0x31C, 1, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_9__KPP_COL_6             IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, 0)
-#define _MX53_PAD_GPIO_9__CCM_REF_EN_B  IOMUX_PAD(0x6AC, 0x31C, 3, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_9__PWM1_PWMO     IOMUX_PAD(0x6AC, 0x31C, 4, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_9__WDOG1_WDOG_B  IOMUX_PAD(0x6AC, 0x31C, 5, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_9__ESDHC1_WP             IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, 0)
-#define _MX53_PAD_GPIO_9__SCC_FAIL_STATE        IOMUX_PAD(0x6AC, 0x31C, 7, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_3__ESAI1_HCKR            IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, 0)
-#define _MX53_PAD_GPIO_3__GPIO1_3               IOMUX_PAD(0x6B0, 0x320, 1, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_3__I2C3_SCL              IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, 0)
-#define _MX53_PAD_GPIO_3__DPLLIP1_TOG_EN        IOMUX_PAD(0x6B0, 0x320, 3, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_3__CCM_CLKO2             IOMUX_PAD(0x6B0, 0x320, 4, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0    IOMUX_PAD(0x6B0, 0x320, 5, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_3__USBOH3_USBH1_OC       IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, 0)
-#define _MX53_PAD_GPIO_3__MLB_MLBCLK            IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, 0)
-#define _MX53_PAD_GPIO_6__ESAI1_SCKT            IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, 0)
-#define _MX53_PAD_GPIO_6__GPIO1_6               IOMUX_PAD(0x6B4, 0x324, 1, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_6__I2C3_SDA              IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, 0)
-#define _MX53_PAD_GPIO_6__CCM_CCM_OUT_0 IOMUX_PAD(0x6B4, 0x324, 3, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_6__CSU_CSU_INT_DEB       IOMUX_PAD(0x6B4, 0x324, 4, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1    IOMUX_PAD(0x6B4, 0x324, 5, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_6__ESDHC2_LCTL   IOMUX_PAD(0x6B4, 0x324, 6, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_6__MLB_MLBSIG            IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, 0)
-#define _MX53_PAD_GPIO_2__ESAI1_FST             IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, 0)
-#define _MX53_PAD_GPIO_2__GPIO1_2               IOMUX_PAD(0x6B8, 0x328, 1, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_2__KPP_ROW_6             IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, 0)
-#define _MX53_PAD_GPIO_2__CCM_CCM_OUT_1 IOMUX_PAD(0x6B8, 0x328, 3, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0   IOMUX_PAD(0x6B8, 0x328, 4, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2    IOMUX_PAD(0x6B8, 0x328, 5, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_2__ESDHC2_WP             IOMUX_PAD(0x6B8, 0x328, 6, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_2__MLB_MLBDAT    IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, 0)
-#define _MX53_PAD_GPIO_4__ESAI1_HCKT            IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, 0)
-#define _MX53_PAD_GPIO_4__GPIO1_4               IOMUX_PAD(0x6BC, 0x32C, 1, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_4__KPP_COL_7             IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, 0)
-#define _MX53_PAD_GPIO_4__CCM_CCM_OUT_2 IOMUX_PAD(0x6BC, 0x32C, 3, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1   IOMUX_PAD(0x6BC, 0x32C, 4, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3    IOMUX_PAD(0x6BC, 0x32C, 5, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_4__ESDHC2_CD             IOMUX_PAD(0x6BC, 0x32C, 6, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_4__SCC_SEC_STATE IOMUX_PAD(0x6BC, 0x32C, 7, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_5__ESAI1_TX2_RX3 IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, 0)
-#define _MX53_PAD_GPIO_5__GPIO1_5               IOMUX_PAD(0x6C0, 0x330, 1, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_5__KPP_ROW_7             IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, 0)
-#define _MX53_PAD_GPIO_5__CCM_CLKO              IOMUX_PAD(0x6C0, 0x330, 3, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2   IOMUX_PAD(0x6C0, 0x330, 4, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4    IOMUX_PAD(0x6C0, 0x330, 5, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_5__I2C3_SCL              IOMUX_PAD(0x6C0, 0x330, 6 | IOMUX_CONFIG_SION, 0x824, 2, 0)
-#define _MX53_PAD_GPIO_5__CCM_PLL1_BYP  IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, 0)
-#define _MX53_PAD_GPIO_7__ESAI1_TX4_RX1 IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, 0)
-#define _MX53_PAD_GPIO_7__GPIO1_7               IOMUX_PAD(0x6C4, 0x334, 1, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_7__EPIT1_EPITO   IOMUX_PAD(0x6C4, 0x334, 2, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_7__CAN1_TXCAN    IOMUX_PAD(0x6C4, 0x334, 3, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_7__UART2_TXD_MUX IOMUX_PAD(0x6C4, 0x334, 4, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_7__FIRI_RXD              IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, 0)
-#define _MX53_PAD_GPIO_7__SPDIF_PLOCK   IOMUX_PAD(0x6C4, 0x334, 6, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_7__CCM_PLL2_BYP  IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, 0)
-#define _MX53_PAD_GPIO_8__ESAI1_TX5_RX0 IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, 0)
-#define _MX53_PAD_GPIO_8__GPIO1_8               IOMUX_PAD(0x6C8, 0x338, 1, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_8__EPIT2_EPITO   IOMUX_PAD(0x6C8, 0x338, 2, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_8__CAN1_RXCAN    IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 3, 0)
-#define _MX53_PAD_GPIO_8__UART2_RXD_MUX IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, 0)
-#define _MX53_PAD_GPIO_8__FIRI_TXD              IOMUX_PAD(0x6C8, 0x338, 5, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_8__SPDIF_SRCLK   IOMUX_PAD(0x6C8, 0x338, 6, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_8__CCM_PLL3_BYP  IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, 0)
-#define _MX53_PAD_GPIO_16__ESAI1_TX3_RX2        IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, 0)
-#define _MX53_PAD_GPIO_16__GPIO7_11             IOMUX_PAD(0x6CC, 0x33C, 1, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT     IOMUX_PAD(0x6CC, 0x33C, 2, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 IOMUX_PAD(0x6CC, 0x33C, 4, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_16__SPDIF_IN1            IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, 0)
-#define _MX53_PAD_GPIO_16__I2C3_SDA             IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, 0)
-#define _MX53_PAD_GPIO_16__SJC_DE_B             IOMUX_PAD(0x6CC, 0x33C, 7, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_17__ESAI1_TX0            IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, 0)
-#define _MX53_PAD_GPIO_17__GPIO7_12             IOMUX_PAD(0x6D0, 0x340, 1, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0     IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, 0)
-#define _MX53_PAD_GPIO_17__GPC_PMIC_RDY IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, 0)
-#define _MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG  IOMUX_PAD(0x6D0, 0x340, 4, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_17__SPDIF_OUT1   IOMUX_PAD(0x6D0, 0x340, 5, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_17__IPU_SNOOP2   IOMUX_PAD(0x6D0, 0x340, 6, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_17__SJC_JTAG_ACT IOMUX_PAD(0x6D0, 0x340, 7, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_18__ESAI1_TX1            IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, 0)
-#define _MX53_PAD_GPIO_18__GPIO7_13             IOMUX_PAD(0x6D4, 0x344, 1, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1     IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, 0)
-#define _MX53_PAD_GPIO_18__OWIRE_LINE   IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, 0)
-#define _MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG       IOMUX_PAD(0x6D4, 0x344, 4, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK     IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, 0)
-#define _MX53_PAD_GPIO_18__ESDHC1_LCTL  IOMUX_PAD(0x6D4, 0x344, 6, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_18__SRC_SYSTEM_RST       IOMUX_PAD(0x6D4, 0x344, 7, 0x0, 0, 0)
-#define MX53_PAD_GPIO_19__KPP_COL_5             (_MX53_PAD_GPIO_19__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_19__KPP_COL_5                     IOMUX_PAD(0x348, 0x020, 0, 0x840, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__GPIO4_5               (_MX53_PAD_GPIO_19__GPIO4_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_19__GPIO4_5                       IOMUX_PAD(0x348, 0x020, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__CCM_CLKO              (_MX53_PAD_GPIO_19__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_19__CCM_CLKO                      IOMUX_PAD(0x348, 0x020, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__SPDIF_OUT1            (_MX53_PAD_GPIO_19__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_19__SPDIF_OUT1                    IOMUX_PAD(0x348, 0x020, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2          (_MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2          IOMUX_PAD(0x348, 0x020, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__ECSPI1_RDY            (_MX53_PAD_GPIO_19__ECSPI1_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_19__ECSPI1_RDY                    IOMUX_PAD(0x348, 0x020, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__FEC_TDATA_3           (_MX53_PAD_GPIO_19__FEC_TDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_19__FEC_TDATA_3                   IOMUX_PAD(0x348, 0x020, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__SRC_INT_BOOT          (_MX53_PAD_GPIO_19__SRC_INT_BOOT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_19__SRC_INT_BOOT                  IOMUX_PAD(0x348, 0x020, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__KPP_COL_0            (_MX53_PAD_KEY_COL0__KPP_COL_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL0__KPP_COL_0                    IOMUX_PAD(0x34C, 0x024, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__GPIO4_6              (_MX53_PAD_KEY_COL0__GPIO4_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL0__GPIO4_6                      IOMUX_PAD(0x34C, 0x024, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC              (_MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC              IOMUX_PAD(0x34C, 0x024, 2, 0x758, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__UART4_TXD_MUX                (_MX53_PAD_KEY_COL0__UART4_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_KEY_COL0__UART4_TXD_MUX                IOMUX_PAD(0x34C, 0x024, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__ECSPI1_SCLK          (_MX53_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL0__ECSPI1_SCLK                  IOMUX_PAD(0x34C, 0x024, 5, 0x79C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__FEC_RDATA_3          (_MX53_PAD_KEY_COL0__FEC_RDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL0__FEC_RDATA_3                  IOMUX_PAD(0x34C, 0x024, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST               (_MX53_PAD_KEY_COL0__SRC_ANY_PU_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST               IOMUX_PAD(0x34C, 0x024, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__KPP_ROW_0            (_MX53_PAD_KEY_ROW0__KPP_ROW_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW0__KPP_ROW_0                    IOMUX_PAD(0x350, 0x028, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__GPIO4_7              (_MX53_PAD_KEY_ROW0__GPIO4_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW0__GPIO4_7                      IOMUX_PAD(0x350, 0x028, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD              (_MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD              IOMUX_PAD(0x350, 0x028, 2, 0x74C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX                (_MX53_PAD_KEY_ROW0__UART4_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX                IOMUX_PAD(0x350, 0x028, 4, 0x890, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI          (_MX53_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI                  IOMUX_PAD(0x350, 0x028, 5, 0x7A4, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__FEC_TX_ER            (_MX53_PAD_KEY_ROW0__FEC_TX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW0__FEC_TX_ER                    IOMUX_PAD(0x350, 0x028, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__KPP_COL_1            (_MX53_PAD_KEY_COL1__KPP_COL_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL1__KPP_COL_1                    IOMUX_PAD(0x354, 0x02C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__GPIO4_8              (_MX53_PAD_KEY_COL1__GPIO4_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL1__GPIO4_8                      IOMUX_PAD(0x354, 0x02C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS             (_MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS             IOMUX_PAD(0x354, 0x02C, 2, 0x75C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__UART5_TXD_MUX                (_MX53_PAD_KEY_COL1__UART5_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_KEY_COL1__UART5_TXD_MUX                IOMUX_PAD(0x354, 0x02C, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__ECSPI1_MISO          (_MX53_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL1__ECSPI1_MISO                  IOMUX_PAD(0x354, 0x02C, 5, 0x7A0, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__FEC_RX_CLK           (_MX53_PAD_KEY_COL1__FEC_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL1__FEC_RX_CLK                   IOMUX_PAD(0x354, 0x02C, 6, 0x808, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY              (_MX53_PAD_KEY_COL1__USBPHY1_TXREADY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY              IOMUX_PAD(0x354, 0x02C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__KPP_ROW_1            (_MX53_PAD_KEY_ROW1__KPP_ROW_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW1__KPP_ROW_1                    IOMUX_PAD(0x358, 0x030, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__GPIO4_9              (_MX53_PAD_KEY_ROW1__GPIO4_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW1__GPIO4_9                      IOMUX_PAD(0x358, 0x030, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD              (_MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD              IOMUX_PAD(0x358, 0x030, 2, 0x748, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX                (_MX53_PAD_KEY_ROW1__UART5_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX                IOMUX_PAD(0x358, 0x030, 4, 0x898, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__ECSPI1_SS0           (_MX53_PAD_KEY_ROW1__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW1__ECSPI1_SS0                   IOMUX_PAD(0x358, 0x030, 5, 0x7A8, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__FEC_COL              (_MX53_PAD_KEY_ROW1__FEC_COL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW1__FEC_COL                      IOMUX_PAD(0x358, 0x030, 6, 0x800, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID              (_MX53_PAD_KEY_ROW1__USBPHY1_RXVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID              IOMUX_PAD(0x358, 0x030, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__KPP_COL_2            (_MX53_PAD_KEY_COL2__KPP_COL_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL2__KPP_COL_2                    IOMUX_PAD(0x35C, 0x034, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__GPIO4_10             (_MX53_PAD_KEY_COL2__GPIO4_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL2__GPIO4_10                     IOMUX_PAD(0x35C, 0x034, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__CAN1_TXCAN           (_MX53_PAD_KEY_COL2__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL2__CAN1_TXCAN                   IOMUX_PAD(0x35C, 0x034, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__FEC_MDIO             (_MX53_PAD_KEY_COL2__FEC_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL2__FEC_MDIO                     IOMUX_PAD(0x35C, 0x034, 4, 0x804, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__ECSPI1_SS1           (_MX53_PAD_KEY_COL2__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL2__ECSPI1_SS1                   IOMUX_PAD(0x35C, 0x034, 5, 0x7AC, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__FEC_RDATA_2          (_MX53_PAD_KEY_COL2__FEC_RDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL2__FEC_RDATA_2                  IOMUX_PAD(0x35C, 0x034, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE             (_MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE             IOMUX_PAD(0x35C, 0x034, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__KPP_ROW_2            (_MX53_PAD_KEY_ROW2__KPP_ROW_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW2__KPP_ROW_2                    IOMUX_PAD(0x360, 0x038, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__GPIO4_11             (_MX53_PAD_KEY_ROW2__GPIO4_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW2__GPIO4_11                     IOMUX_PAD(0x360, 0x038, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__CAN1_RXCAN           (_MX53_PAD_KEY_ROW2__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW2__CAN1_RXCAN                   IOMUX_PAD(0x360, 0x038, 2, 0x760, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__FEC_MDC              (_MX53_PAD_KEY_ROW2__FEC_MDC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW2__FEC_MDC                      IOMUX_PAD(0x360, 0x038, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__ECSPI1_SS2           (_MX53_PAD_KEY_ROW2__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW2__ECSPI1_SS2                   IOMUX_PAD(0x360, 0x038, 5, 0x7B0, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__FEC_TDATA_2          (_MX53_PAD_KEY_ROW2__FEC_TDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW2__FEC_TDATA_2                  IOMUX_PAD(0x360, 0x038, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR              (_MX53_PAD_KEY_ROW2__USBPHY1_RXERROR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR              IOMUX_PAD(0x360, 0x038, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__KPP_COL_3            (_MX53_PAD_KEY_COL3__KPP_COL_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL3__KPP_COL_3                    IOMUX_PAD(0x364, 0x03C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__GPIO4_12             (_MX53_PAD_KEY_COL3__GPIO4_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL3__GPIO4_12                     IOMUX_PAD(0x364, 0x03C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__USBOH3_H2_DP         (_MX53_PAD_KEY_COL3__USBOH3_H2_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL3__USBOH3_H2_DP                 IOMUX_PAD(0x364, 0x03C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__SPDIF_IN1            (_MX53_PAD_KEY_COL3__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL3__SPDIF_IN1                    IOMUX_PAD(0x364, 0x03C, 3, 0x870, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__I2C2_SCL             (_MX53_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C))
+#define MX53_PAD_KEY_COL3__I2C2_SCL                     IOMUX_PAD(0x364, 0x03C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__ECSPI1_SS3           (_MX53_PAD_KEY_COL3__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL3__ECSPI1_SS3                   IOMUX_PAD(0x364, 0x03C, 5, 0x7B4, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__FEC_CRS              (_MX53_PAD_KEY_COL3__FEC_CRS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL3__FEC_CRS                      IOMUX_PAD(0x364, 0x03C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK             (_MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK             IOMUX_PAD(0x364, 0x03C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__KPP_ROW_3            (_MX53_PAD_KEY_ROW3__KPP_ROW_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW3__KPP_ROW_3                    IOMUX_PAD(0x368, 0x040, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__GPIO4_13             (_MX53_PAD_KEY_ROW3__GPIO4_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW3__GPIO4_13                     IOMUX_PAD(0x368, 0x040, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM         (_MX53_PAD_KEY_ROW3__USBOH3_H2_DM | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM                 IOMUX_PAD(0x368, 0x040, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK             (_MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK             IOMUX_PAD(0x368, 0x040, 3, 0x768, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__I2C2_SDA             (_MX53_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C))
+#define MX53_PAD_KEY_ROW3__I2C2_SDA                     IOMUX_PAD(0x368, 0x040, 4 | IOMUX_CONFIG_SION, 0x820, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT               (_MX53_PAD_KEY_ROW3__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT               IOMUX_PAD(0x368, 0x040, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP         (_MX53_PAD_KEY_ROW3__CCM_PLL4_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP                 IOMUX_PAD(0x368, 0x040, 6, 0x77C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0          (_MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0          IOMUX_PAD(0x368, 0x040, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__KPP_COL_4            (_MX53_PAD_KEY_COL4__KPP_COL_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL4__KPP_COL_4                    IOMUX_PAD(0x36C, 0x044, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__GPIO4_14             (_MX53_PAD_KEY_COL4__GPIO4_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL4__GPIO4_14                     IOMUX_PAD(0x36C, 0x044, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__CAN2_TXCAN           (_MX53_PAD_KEY_COL4__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL4__CAN2_TXCAN                   IOMUX_PAD(0x36C, 0x044, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__IPU_SISG_4           (_MX53_PAD_KEY_COL4__IPU_SISG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL4__IPU_SISG_4                   IOMUX_PAD(0x36C, 0x044, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__UART5_RTS            (_MX53_PAD_KEY_COL4__UART5_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_KEY_COL4__UART5_RTS                    IOMUX_PAD(0x36C, 0x044, 4, 0x894, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC             (_MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC             IOMUX_PAD(0x36C, 0x044, 5, 0x89C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1          (_MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1          IOMUX_PAD(0x36C, 0x044, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__KPP_ROW_4            (_MX53_PAD_KEY_ROW4__KPP_ROW_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW4__KPP_ROW_4                    IOMUX_PAD(0x370, 0x048, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__GPIO4_15             (_MX53_PAD_KEY_ROW4__GPIO4_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW4__GPIO4_15                     IOMUX_PAD(0x370, 0x048, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__CAN2_RXCAN           (_MX53_PAD_KEY_ROW4__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW4__CAN2_RXCAN                   IOMUX_PAD(0x370, 0x048, 2, 0x764, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__IPU_SISG_5           (_MX53_PAD_KEY_ROW4__IPU_SISG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW4__IPU_SISG_5                   IOMUX_PAD(0x370, 0x048, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__UART5_CTS            (_MX53_PAD_KEY_ROW4__UART5_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_KEY_ROW4__UART5_CTS                    IOMUX_PAD(0x370, 0x048, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR            (_MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR            IOMUX_PAD(0x370, 0x048, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID            (_MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID            IOMUX_PAD(0x370, 0x048, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK         (_MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK         IOMUX_PAD(0x378, 0x04C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__GPIO4_16         (_MX53_PAD_DI0_DISP_CLK__GPIO4_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_DISP_CLK__GPIO4_16                 IOMUX_PAD(0x378, 0x04C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR         (_MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR         IOMUX_PAD(0x378, 0x04C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0          (_MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0  IOMUX_PAD(0x378, 0x04C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0          (_MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0          IOMUX_PAD(0x378, 0x04C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID           (_MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID           IOMUX_PAD(0x378, 0x04C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15               (_MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15               IOMUX_PAD(0x37C, 0x050, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__GPIO4_17            (_MX53_PAD_DI0_PIN15__GPIO4_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN15__GPIO4_17                    IOMUX_PAD(0x37C, 0x050, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC             (_MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC             IOMUX_PAD(0x37C, 0x050, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1             (_MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1     IOMUX_PAD(0x37C, 0x050, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1             (_MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1             IOMUX_PAD(0x37C, 0x050, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID              (_MX53_PAD_DI0_PIN15__USBPHY1_BVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID              IOMUX_PAD(0x37C, 0x050, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2         (_MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2                 IOMUX_PAD(0x380, 0x054, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__GPIO4_18             (_MX53_PAD_DI0_PIN2__GPIO4_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN2__GPIO4_18                     IOMUX_PAD(0x380, 0x054, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD              (_MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD              IOMUX_PAD(0x380, 0x054, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2              (_MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2      IOMUX_PAD(0x380, 0x054, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2              (_MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2              IOMUX_PAD(0x380, 0x054, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION           (_MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION           IOMUX_PAD(0x380, 0x054, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3         (_MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3                 IOMUX_PAD(0x384, 0x058, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__GPIO4_19             (_MX53_PAD_DI0_PIN3__GPIO4_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN3__GPIO4_19                     IOMUX_PAD(0x384, 0x058, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS             (_MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS             IOMUX_PAD(0x384, 0x058, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3              (_MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3      IOMUX_PAD(0x384, 0x058, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3              (_MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3              IOMUX_PAD(0x384, 0x058, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG                (_MX53_PAD_DI0_PIN3__USBPHY1_IDDIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG                IOMUX_PAD(0x384, 0x058, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4         (_MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4                 IOMUX_PAD(0x388, 0x05C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__GPIO4_20             (_MX53_PAD_DI0_PIN4__GPIO4_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN4__GPIO4_20                     IOMUX_PAD(0x388, 0x05C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD              (_MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD              IOMUX_PAD(0x388, 0x05C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__ESDHC1_WP            (_MX53_PAD_DI0_PIN4__ESDHC1_WP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN4__ESDHC1_WP                    IOMUX_PAD(0x388, 0x05C, 3, 0x7FC, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD             (_MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD             IOMUX_PAD(0x388, 0x05C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4              (_MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4              IOMUX_PAD(0x388, 0x05C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT               (_MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT       IOMUX_PAD(0x388, 0x05C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0            (_MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0            IOMUX_PAD(0x38C, 0x060, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__GPIO4_21           (_MX53_PAD_DISP0_DAT0__GPIO4_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT0__GPIO4_21                   IOMUX_PAD(0x38C, 0x060, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__CSPI_SCLK          (_MX53_PAD_DISP0_DAT0__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT0__CSPI_SCLK                  IOMUX_PAD(0x38C, 0x060, 2, 0x780, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0                (_MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0        IOMUX_PAD(0x38C, 0x060, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN                (_MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN        IOMUX_PAD(0x38C, 0x060, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5            (_MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5            IOMUX_PAD(0x38C, 0x060, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY            (_MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY            IOMUX_PAD(0x38C, 0x060, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1            (_MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1            IOMUX_PAD(0x390, 0x064, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__GPIO4_22           (_MX53_PAD_DISP0_DAT1__GPIO4_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT1__GPIO4_22                   IOMUX_PAD(0x390, 0x064, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__CSPI_MOSI          (_MX53_PAD_DISP0_DAT1__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT1__CSPI_MOSI                  IOMUX_PAD(0x390, 0x064, 2, 0x788, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1                (_MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1        IOMUX_PAD(0x390, 0x064, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL               (_MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL       \
-#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6            (_MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+                                                        IOMUX_PAD(0x390, 0x064, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID            (_MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6            IOMUX_PAD(0x390, 0x064, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2            (_MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID            IOMUX_PAD(0x390, 0x064, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__GPIO4_23           (_MX53_PAD_DISP0_DAT2__GPIO4_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2            IOMUX_PAD(0x394, 0x068, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__CSPI_MISO          (_MX53_PAD_DISP0_DAT2__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT2__GPIO4_23                   IOMUX_PAD(0x394, 0x068, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2                (_MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT2__CSPI_MISO                  IOMUX_PAD(0x394, 0x068, 2, 0x784, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE            (_MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2        IOMUX_PAD(0x394, 0x068, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7            (_MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE            IOMUX_PAD(0x394, 0x068, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE           (_MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7            IOMUX_PAD(0x394, 0x068, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3            (_MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE           IOMUX_PAD(0x394, 0x068, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__GPIO4_24           (_MX53_PAD_DISP0_DAT3__GPIO4_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3            IOMUX_PAD(0x398, 0x06C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__CSPI_SS0           (_MX53_PAD_DISP0_DAT3__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT3__GPIO4_24                   IOMUX_PAD(0x398, 0x06C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3                (_MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT3__CSPI_SS0                   IOMUX_PAD(0x398, 0x06C, 2, 0x78C, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR               (_MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3        IOMUX_PAD(0x398, 0x06C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8            (_MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR       IOMUX_PAD(0x398, 0x06C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR            (_MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8            IOMUX_PAD(0x398, 0x06C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4            (_MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR            IOMUX_PAD(0x398, 0x06C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__GPIO4_25           (_MX53_PAD_DISP0_DAT4__GPIO4_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4            IOMUX_PAD(0x39C, 0x070, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__CSPI_SS1           (_MX53_PAD_DISP0_DAT4__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT4__GPIO4_25                   IOMUX_PAD(0x39C, 0x070, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4                (_MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT4__CSPI_SS1                   IOMUX_PAD(0x39C, 0x070, 2, 0x790, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB         (_MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4        IOMUX_PAD(0x39C, 0x070, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9            (_MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB         IOMUX_PAD(0x39C, 0x070, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK           (_MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9            IOMUX_PAD(0x39C, 0x070, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5            (_MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK           IOMUX_PAD(0x39C, 0x070, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__GPIO4_26           (_MX53_PAD_DISP0_DAT5__GPIO4_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5            IOMUX_PAD(0x3A0, 0x074, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__CSPI_SS2           (_MX53_PAD_DISP0_DAT5__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT5__GPIO4_26                   IOMUX_PAD(0x3A0, 0x074, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5                (_MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT5__CSPI_SS2                   IOMUX_PAD(0x3A0, 0x074, 2, 0x794, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS           (_MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5        IOMUX_PAD(0x3A0, 0x074, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10           (_MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS   IOMUX_PAD(0x3A0, 0x074, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0                (_MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10           IOMUX_PAD(0x3A0, 0x074, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6            (_MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0        IOMUX_PAD(0x3A0, 0x074, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__GPIO4_27           (_MX53_PAD_DISP0_DAT6__GPIO4_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6            IOMUX_PAD(0x3A4, 0x078, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__CSPI_SS3           (_MX53_PAD_DISP0_DAT6__CSPI_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT6__GPIO4_27                   IOMUX_PAD(0x3A4, 0x078, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6                (_MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT6__CSPI_SS3                   IOMUX_PAD(0x3A4, 0x078, 2, 0x798, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE          (_MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6        IOMUX_PAD(0x3A4, 0x078, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11           (_MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE  IOMUX_PAD(0x3A4, 0x078, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1                (_MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11           IOMUX_PAD(0x3A4, 0x078, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7            (_MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1        IOMUX_PAD(0x3A4, 0x078, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__GPIO4_28           (_MX53_PAD_DISP0_DAT7__GPIO4_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7            IOMUX_PAD(0x3A8, 0x07C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__CSPI_RDY           (_MX53_PAD_DISP0_DAT7__CSPI_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT7__GPIO4_28                   IOMUX_PAD(0x3A8, 0x07C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7                (_MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT7__CSPI_RDY                   IOMUX_PAD(0x3A8, 0x07C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0         (_MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7        IOMUX_PAD(0x3A8, 0x07C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12           (_MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 IOMUX_PAD(0x3A8, 0x07C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID          (_MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12           IOMUX_PAD(0x3A8, 0x07C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8            (_MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID          IOMUX_PAD(0x3A8, 0x07C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__GPIO4_29           (_MX53_PAD_DISP0_DAT8__GPIO4_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8            IOMUX_PAD(0x3AC, 0x080, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__PWM1_PWMO          (_MX53_PAD_DISP0_DAT8__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT8__GPIO4_29                   IOMUX_PAD(0x3AC, 0x080, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B               (_MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT8__PWM1_PWMO                  IOMUX_PAD(0x3AC, 0x080, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1         (_MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B               IOMUX_PAD(0x3AC, 0x080, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13           (_MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 IOMUX_PAD(0x3AC, 0x080, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID             (_MX53_PAD_DISP0_DAT8__USBPHY2_AVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13           IOMUX_PAD(0x3AC, 0x080, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9            (_MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID             IOMUX_PAD(0x3AC, 0x080, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__GPIO4_30           (_MX53_PAD_DISP0_DAT9__GPIO4_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9            IOMUX_PAD(0x3B0, 0x084, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__PWM2_PWMO          (_MX53_PAD_DISP0_DAT9__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT9__GPIO4_30                   IOMUX_PAD(0x3B0, 0x084, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B               (_MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT9__PWM2_PWMO                  IOMUX_PAD(0x3B0, 0x084, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2         (_MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B               IOMUX_PAD(0x3B0, 0x084, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14           (_MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 IOMUX_PAD(0x3B0, 0x084, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0          (_MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14           IOMUX_PAD(0x3B0, 0x084, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10          (_MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0          IOMUX_PAD(0x3B0, 0x084, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__GPIO4_31          (_MX53_PAD_DISP0_DAT10__GPIO4_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10          IOMUX_PAD(0x3B4, 0x088, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP          (_MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT10__GPIO4_31                  IOMUX_PAD(0x3B4, 0x088, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3                (_MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP          IOMUX_PAD(0x3B4, 0x088, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15          (_MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3        \
-#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1         (_MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+                                                        IOMUX_PAD(0x3B4, 0x088, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11          (_MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15          IOMUX_PAD(0x3B4, 0x088, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__GPIO5_5           (_MX53_PAD_DISP0_DAT11__GPIO5_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1         IOMUX_PAD(0x3B4, 0x088, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT          (_MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11          IOMUX_PAD(0x3B8, 0x08C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4                (_MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT11__GPIO5_5                   IOMUX_PAD(0x3B8, 0x08C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16          (_MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT          IOMUX_PAD(0x3B8, 0x08C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2         (_MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4        \
-#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12          (_MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+                                                        IOMUX_PAD(0x3B8, 0x08C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__GPIO5_6           (_MX53_PAD_DISP0_DAT12__GPIO5_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16          IOMUX_PAD(0x3B8, 0x08C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK          (_MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2         IOMUX_PAD(0x3B8, 0x08C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5                (_MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12          IOMUX_PAD(0x3BC, 0x090, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17          (_MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT12__GPIO5_6                   IOMUX_PAD(0x3BC, 0x090, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3         (_MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK          IOMUX_PAD(0x3BC, 0x090, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13          (_MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5        \
-#define MX53_PAD_DISP0_DAT13__GPIO5_7           (_MX53_PAD_DISP0_DAT13__GPIO5_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+                                                        IOMUX_PAD(0x3BC, 0x090, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS          (_MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17          IOMUX_PAD(0x3BC, 0x090, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0                (_MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3         IOMUX_PAD(0x3BC, 0x090, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18          (_MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13          IOMUX_PAD(0x3C0, 0x094, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4         (_MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT13__GPIO5_7                   IOMUX_PAD(0x3C0, 0x094, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14          (_MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS          IOMUX_PAD(0x3C0, 0x094, 3, 0x754, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__GPIO5_8           (_MX53_PAD_DISP0_DAT14__GPIO5_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0        \
-#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC           (_MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+                                                        IOMUX_PAD(0x3C0, 0x094, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1                (_MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18          IOMUX_PAD(0x3C0, 0x094, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19          (_MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4         IOMUX_PAD(0x3C0, 0x094, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5         (_MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14          IOMUX_PAD(0x3C4, 0x098, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15          (_MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT14__GPIO5_8                   IOMUX_PAD(0x3C4, 0x098, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__GPIO5_9           (_MX53_PAD_DISP0_DAT15__GPIO5_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC           IOMUX_PAD(0x3C4, 0x098, 3, 0x750, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1                (_MX53_PAD_DISP0_DAT15__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1        \
-#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1                (_MX53_PAD_DISP0_DAT15__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+                                                        IOMUX_PAD(0x3C4, 0x098, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2                (_MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19          IOMUX_PAD(0x3C4, 0x098, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20          (_MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5         IOMUX_PAD(0x3C4, 0x098, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6         (_MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15          IOMUX_PAD(0x3C8, 0x09C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16          (_MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT15__GPIO5_9                   IOMUX_PAD(0x3C8, 0x09C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__GPIO5_10          (_MX53_PAD_DISP0_DAT16__GPIO5_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1                IOMUX_PAD(0x3C8, 0x09C, 2, 0x7AC, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI               (_MX53_PAD_DISP0_DAT16__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1                IOMUX_PAD(0x3C8, 0x09C, 3, 0x7C8, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC           (_MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2        \
-#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0          (_MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+                                                        IOMUX_PAD(0x3C8, 0x09C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3                (_MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20          IOMUX_PAD(0x3C8, 0x09C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21          (_MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6         IOMUX_PAD(0x3C8, 0x09C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7         (_MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16          IOMUX_PAD(0x3CC, 0x0A0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17          (_MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT16__GPIO5_10                  IOMUX_PAD(0x3CC, 0x0A0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__GPIO5_11          (_MX53_PAD_DISP0_DAT17__GPIO5_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI               IOMUX_PAD(0x3CC, 0x0A0, 2, 0x7C0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO               (_MX53_PAD_DISP0_DAT17__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC           IOMUX_PAD(0x3CC, 0x0A0, 3, 0x758, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD           (_MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0          IOMUX_PAD(0x3CC, 0x0A0, 4, 0x868, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1          (_MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3        \
-#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4                (_MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+                                                        IOMUX_PAD(0x3CC, 0x0A0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22          (_MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21          IOMUX_PAD(0x3CC, 0x0A0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18          (_MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7         IOMUX_PAD(0x3CC, 0x0A0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__GPIO5_12          (_MX53_PAD_DISP0_DAT18__GPIO5_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17          IOMUX_PAD(0x3D0, 0x0A4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0                (_MX53_PAD_DISP0_DAT18__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT17__GPIO5_11                  IOMUX_PAD(0x3D0, 0x0A4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS          (_MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO               IOMUX_PAD(0x3D0, 0x0A4, 2, 0x7BC, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS          (_MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD           IOMUX_PAD(0x3D0, 0x0A4, 3, 0x74C, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5                (_MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1          IOMUX_PAD(0x3D0, 0x0A4, 4, 0x86C, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23          (_MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4        \
-#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2             (_MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+                                                        IOMUX_PAD(0x3D0, 0x0A4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19          (_MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22          IOMUX_PAD(0x3D0, 0x0A4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__GPIO5_13          (_MX53_PAD_DISP0_DAT19__GPIO5_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18          IOMUX_PAD(0x3D4, 0x0A8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK               (_MX53_PAD_DISP0_DAT19__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT18__GPIO5_12                  IOMUX_PAD(0x3D4, 0x0A8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD           (_MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0                IOMUX_PAD(0x3D4, 0x0A8, 2, 0x7C4, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC           (_MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS          IOMUX_PAD(0x3D4, 0x0A8, 3, 0x75C, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6                (_MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS          IOMUX_PAD(0x3D4, 0x0A8, 4, 0x73C, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24          (_MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5        \
-#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3             (_MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+                                                        IOMUX_PAD(0x3D4, 0x0A8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20          (_MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23          IOMUX_PAD(0x3D4, 0x0A8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__GPIO5_14          (_MX53_PAD_DISP0_DAT20__GPIO5_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2             IOMUX_PAD(0x3D4, 0x0A8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK               (_MX53_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19          IOMUX_PAD(0x3D8, 0x0AC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC           (_MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT19__GPIO5_13                  IOMUX_PAD(0x3D8, 0x0AC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7                (_MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK               IOMUX_PAD(0x3D8, 0x0AC, 2, 0x7B8, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25          (_MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD           IOMUX_PAD(0x3D8, 0x0AC, 3, 0x748, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI              (_MX53_PAD_DISP0_DAT20__SATA_PHY_TDI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC           IOMUX_PAD(0x3D8, 0x0AC, 4, 0x738, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21          (_MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6        \
-#define MX53_PAD_DISP0_DAT21__GPIO5_15          (_MX53_PAD_DISP0_DAT21__GPIO5_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+                                                        IOMUX_PAD(0x3D8, 0x0AC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI               (_MX53_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24          IOMUX_PAD(0x3D8, 0x0AC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD           (_MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3             IOMUX_PAD(0x3D8, 0x0AC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0           (_MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20          IOMUX_PAD(0x3DC, 0x0B0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26          (_MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT20__GPIO5_14                  IOMUX_PAD(0x3DC, 0x0B0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO              (_MX53_PAD_DISP0_DAT21__SATA_PHY_TDO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK               IOMUX_PAD(0x3DC, 0x0B0, 2, 0x79C, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22          (_MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC           IOMUX_PAD(0x3DC, 0x0B0, 3, 0x740, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__GPIO5_16          (_MX53_PAD_DISP0_DAT22__GPIO5_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7        \
-#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO               (_MX53_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+                                                        IOMUX_PAD(0x3DC, 0x0B0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS          (_MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25          IOMUX_PAD(0x3DC, 0x0B0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1           (_MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI              IOMUX_PAD(0x3DC, 0x0B0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27          (_MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21          IOMUX_PAD(0x3E0, 0x0B4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK              (_MX53_PAD_DISP0_DAT22__SATA_PHY_TCK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT21__GPIO5_15                  IOMUX_PAD(0x3E0, 0x0B4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23          (_MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI               IOMUX_PAD(0x3E0, 0x0B4, 2, 0x7A4, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__GPIO5_17          (_MX53_PAD_DISP0_DAT23__GPIO5_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD           IOMUX_PAD(0x3E0, 0x0B4, 3, 0x734, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0                (_MX53_PAD_DISP0_DAT23__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0   IOMUX_PAD(0x3E0, 0x0B4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD           (_MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26          IOMUX_PAD(0x3E0, 0x0B4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2           (_MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO              IOMUX_PAD(0x3E0, 0x0B4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28          (_MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22          IOMUX_PAD(0x3E4, 0x0B8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS              (_MX53_PAD_DISP0_DAT23__SATA_PHY_TMS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT22__GPIO5_16                  IOMUX_PAD(0x3E4, 0x0B8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK           (_MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO               IOMUX_PAD(0x3E4, 0x0B8, 2, 0x7A0, 1, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_PIXCLK__GPIO5_18          (_MX53_PAD_CSI0_PIXCLK__GPIO5_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS          IOMUX_PAD(0x3E4, 0x0B8, 3, 0x744, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0           (_MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1   IOMUX_PAD(0x3E4, 0x0B8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29          (_MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27          IOMUX_PAD(0x3E4, 0x0B8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC              (_MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK              IOMUX_PAD(0x3E4, 0x0B8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__GPIO5_19            (_MX53_PAD_CSI0_MCLK__GPIO5_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23          IOMUX_PAD(0x3E8, 0x0BC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK               (_MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT23__GPIO5_17                  IOMUX_PAD(0x3E8, 0x0BC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1             (_MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0                IOMUX_PAD(0x3E8, 0x0BC, 2, 0x7A8, 1, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30            (_MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD           IOMUX_PAD(0x3E8, 0x0BC, 3, 0x730, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL          (_MX53_PAD_CSI0_MCLK__TPIU_TRCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2   IOMUX_PAD(0x3E8, 0x0BC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN         (_MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28          IOMUX_PAD(0x3E8, 0x0BC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DATA_EN__GPIO5_20         (_MX53_PAD_CSI0_DATA_EN__GPIO5_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS              IOMUX_PAD(0x3E8, 0x0BC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2          (_MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK           IOMUX_PAD(0x3EC, 0x0C0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31         (_MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_PIXCLK__GPIO5_18                  IOMUX_PAD(0x3EC, 0x0C0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK               (_MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0           IOMUX_PAD(0x3EC, 0x0C0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC             (_MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29          IOMUX_PAD(0x3EC, 0x0C0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_VSYNC__GPIO5_21           (_MX53_PAD_CSI0_VSYNC__GPIO5_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC              IOMUX_PAD(0x3F0, 0x0C4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3            (_MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_MCLK__GPIO5_19                    IOMUX_PAD(0x3F0, 0x0C4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32           (_MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK               IOMUX_PAD(0x3F0, 0x0C4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0               (_MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1             IOMUX_PAD(0x3F0, 0x0C4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4                (_MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30            IOMUX_PAD(0x3F0, 0x0C4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__GPIO5_22            (_MX53_PAD_CSI0_DAT4__GPIO5_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL                  IOMUX_PAD(0x3F0, 0x0C4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__KPP_COL_5           (_MX53_PAD_CSI0_DAT4__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN         IOMUX_PAD(0x3F4, 0x0C8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK         (_MX53_PAD_CSI0_DAT4__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DATA_EN__GPIO5_20                 IOMUX_PAD(0x3F4, 0x0C8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP            (_MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2          IOMUX_PAD(0x3F4, 0x0C8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC             (_MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31         IOMUX_PAD(0x3F4, 0x0C8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33            (_MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK               IOMUX_PAD(0x3F4, 0x0C8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1                (_MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC             IOMUX_PAD(0x3F8, 0x0CC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5                (_MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_VSYNC__GPIO5_21                   IOMUX_PAD(0x3F8, 0x0CC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__GPIO5_23            (_MX53_PAD_CSI0_DAT5__GPIO5_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3            IOMUX_PAD(0x3F8, 0x0CC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__KPP_ROW_5           (_MX53_PAD_CSI0_DAT5__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32           IOMUX_PAD(0x3F8, 0x0CC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI         (_MX53_PAD_CSI0_DAT5__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0               IOMUX_PAD(0x3F8, 0x0CC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT            (_MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4                IOMUX_PAD(0x3FC, 0x0D0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD             (_MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT4__GPIO5_22                    IOMUX_PAD(0x3FC, 0x0D0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34            (_MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT4__KPP_COL_5                   IOMUX_PAD(0x3FC, 0x0D0, 2, 0x840, 1, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2                (_MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK                 IOMUX_PAD(0x3FC, 0x0D0, 3, 0x79C, 2, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6                (_MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP            IOMUX_PAD(0x3FC, 0x0D0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__GPIO5_24            (_MX53_PAD_CSI0_DAT6__GPIO5_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC             IOMUX_PAD(0x3FC, 0x0D0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__KPP_COL_6           (_MX53_PAD_CSI0_DAT6__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33            IOMUX_PAD(0x3FC, 0x0D0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO         (_MX53_PAD_CSI0_DAT6__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1                IOMUX_PAD(0x3FC, 0x0D0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK            (_MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5                IOMUX_PAD(0x400, 0x0D4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS            (_MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT5__GPIO5_23                    IOMUX_PAD(0x400, 0x0D4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35            (_MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT5__KPP_ROW_5                   IOMUX_PAD(0x400, 0x0D4, 2, 0x84C, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3                (_MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI                 IOMUX_PAD(0x400, 0x0D4, 3, 0x7A4, 2, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7                (_MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT            IOMUX_PAD(0x400, 0x0D4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__GPIO5_25            (_MX53_PAD_CSI0_DAT7__GPIO5_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD             IOMUX_PAD(0x400, 0x0D4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__KPP_ROW_6           (_MX53_PAD_CSI0_DAT7__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34            IOMUX_PAD(0x400, 0x0D4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0          (_MX53_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2                IOMUX_PAD(0x400, 0x0D4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR            (_MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6                IOMUX_PAD(0x404, 0x0D8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD             (_MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT6__GPIO5_24                    IOMUX_PAD(0x404, 0x0D8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36            (_MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT6__KPP_COL_6                   IOMUX_PAD(0x404, 0x0D8, 2, 0x844, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4                (_MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO                 IOMUX_PAD(0x404, 0x0D8, 3, 0x7A0, 2, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8                (_MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK            IOMUX_PAD(0x404, 0x0D8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__GPIO5_26            (_MX53_PAD_CSI0_DAT8__GPIO5_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS            IOMUX_PAD(0x404, 0x0D8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__KPP_COL_7           (_MX53_PAD_CSI0_DAT8__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35            IOMUX_PAD(0x404, 0x0D8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK         (_MX53_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3                IOMUX_PAD(0x404, 0x0D8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC             (_MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7                IOMUX_PAD(0x408, 0x0DC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__I2C1_SDA            (_MX53_PAD_CSI0_DAT8__I2C1_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C))
+#define MX53_PAD_CSI0_DAT7__GPIO5_25                    IOMUX_PAD(0x408, 0x0DC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37            (_MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT7__KPP_ROW_6                   IOMUX_PAD(0x408, 0x0DC, 2, 0x850, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5                (_MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0                  IOMUX_PAD(0x408, 0x0DC, 3, 0x7A8, 2, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9                (_MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR            IOMUX_PAD(0x408, 0x0DC, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__GPIO5_27            (_MX53_PAD_CSI0_DAT9__GPIO5_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD             IOMUX_PAD(0x408, 0x0DC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__KPP_ROW_7           (_MX53_PAD_CSI0_DAT9__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36            IOMUX_PAD(0x408, 0x0DC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI         (_MX53_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4                IOMUX_PAD(0x408, 0x0DC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR            (_MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8                IOMUX_PAD(0x40C, 0x0E0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__I2C1_SCL            (_MX53_PAD_CSI0_DAT9__I2C1_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C))
+#define MX53_PAD_CSI0_DAT8__GPIO5_26                    IOMUX_PAD(0x40C, 0x0E0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38            (_MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT8__KPP_COL_7                   IOMUX_PAD(0x40C, 0x0E0, 2, 0x848, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6                (_MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK                 IOMUX_PAD(0x40C, 0x0E0, 3, 0x7B8, 1, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10              (_MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC             IOMUX_PAD(0x40C, 0x0E0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__GPIO5_28           (_MX53_PAD_CSI0_DAT10__GPIO5_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT8__I2C1_SDA                    IOMUX_PAD(0x40C, 0x0E0, 5 | IOMUX_CONFIG_SION, 0x818, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX              (_MX53_PAD_CSI0_DAT10__UART1_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37            IOMUX_PAD(0x40C, 0x0E0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO                (_MX53_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5                IOMUX_PAD(0x40C, 0x0E0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC            (_MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9                IOMUX_PAD(0x410, 0x0E4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4            (_MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT9__GPIO5_27                    IOMUX_PAD(0x410, 0x0E4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39           (_MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT9__KPP_ROW_7                   IOMUX_PAD(0x410, 0x0E4, 2, 0x854, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7               (_MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI                 IOMUX_PAD(0x410, 0x0E4, 3, 0x7C0, 1, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11              (_MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR            IOMUX_PAD(0x410, 0x0E4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__GPIO5_29           (_MX53_PAD_CSI0_DAT11__GPIO5_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT9__I2C1_SCL                    IOMUX_PAD(0x410, 0x0E4, 5 | IOMUX_CONFIG_SION, 0x814, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX              (_MX53_PAD_CSI0_DAT11__UART1_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38            IOMUX_PAD(0x410, 0x0E4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0         (_MX53_PAD_CSI0_DAT11__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6                IOMUX_PAD(0x410, 0x0E4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS           (_MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10              IOMUX_PAD(0x414, 0x0E8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5            (_MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT10__GPIO5_28                   IOMUX_PAD(0x414, 0x0E8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40           (_MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX              IOMUX_PAD(0x414, 0x0E8, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8               (_MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO                IOMUX_PAD(0x414, 0x0E8, 3, 0x7BC, 1, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12              (_MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC            IOMUX_PAD(0x414, 0x0E8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__GPIO5_30           (_MX53_PAD_CSI0_DAT12__GPIO5_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4            IOMUX_PAD(0x414, 0x0E8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX              (_MX53_PAD_CSI0_DAT12__UART4_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39           IOMUX_PAD(0x414, 0x0E8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0                (_MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7               IOMUX_PAD(0x414, 0x0E8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6            (_MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11              IOMUX_PAD(0x418, 0x0EC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41           (_MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT11__GPIO5_29                   IOMUX_PAD(0x418, 0x0EC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9               (_MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX              IOMUX_PAD(0x418, 0x0EC, 2, 0x878, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13              (_MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0                 IOMUX_PAD(0x418, 0x0EC, 3, 0x7C4, 1, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__GPIO5_31           (_MX53_PAD_CSI0_DAT13__GPIO5_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS           IOMUX_PAD(0x418, 0x0EC, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX              (_MX53_PAD_CSI0_DAT13__UART4_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5            IOMUX_PAD(0x418, 0x0EC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1                (_MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40           IOMUX_PAD(0x418, 0x0EC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7            (_MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8               IOMUX_PAD(0x418, 0x0EC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42           (_MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12              IOMUX_PAD(0x41C, 0x0F0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10              (_MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT12__GPIO5_30                   IOMUX_PAD(0x41C, 0x0F0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14              (_MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX              IOMUX_PAD(0x41C, 0x0F0, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__GPIO6_0            (_MX53_PAD_CSI0_DAT14__GPIO6_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0        IOMUX_PAD(0x41C, 0x0F0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX              (_MX53_PAD_CSI0_DAT14__UART5_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6            IOMUX_PAD(0x41C, 0x0F0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2                (_MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41           IOMUX_PAD(0x41C, 0x0F0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8            (_MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9               IOMUX_PAD(0x41C, 0x0F0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43           (_MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13              IOMUX_PAD(0x420, 0x0F4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11              (_MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT13__GPIO5_31                   IOMUX_PAD(0x420, 0x0F4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15              (_MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX              IOMUX_PAD(0x420, 0x0F4, 2, 0x890, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__GPIO6_1            (_MX53_PAD_CSI0_DAT15__GPIO6_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1        IOMUX_PAD(0x420, 0x0F4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX              (_MX53_PAD_CSI0_DAT15__UART5_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7            IOMUX_PAD(0x420, 0x0F4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3                (_MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42           IOMUX_PAD(0x420, 0x0F4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9            (_MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10              IOMUX_PAD(0x420, 0x0F4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44           (_MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14              IOMUX_PAD(0x424, 0x0F8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12              (_MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT14__GPIO6_0                    IOMUX_PAD(0x424, 0x0F8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16              (_MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX              IOMUX_PAD(0x424, 0x0F8, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__GPIO6_2            (_MX53_PAD_CSI0_DAT16__GPIO6_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2        IOMUX_PAD(0x424, 0x0F8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__UART4_RTS          (_MX53_PAD_CSI0_DAT16__UART4_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8            IOMUX_PAD(0x424, 0x0F8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4                (_MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43           IOMUX_PAD(0x424, 0x0F8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10           (_MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11              IOMUX_PAD(0x424, 0x0F8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45           (_MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15              IOMUX_PAD(0x428, 0x0FC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13              (_MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT15__GPIO6_1                    IOMUX_PAD(0x428, 0x0FC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17              (_MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX              IOMUX_PAD(0x428, 0x0FC, 2, 0x898, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__GPIO6_3            (_MX53_PAD_CSI0_DAT17__GPIO6_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3        IOMUX_PAD(0x428, 0x0FC, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__UART4_CTS          (_MX53_PAD_CSI0_DAT17__UART4_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9            IOMUX_PAD(0x428, 0x0FC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5                (_MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44           IOMUX_PAD(0x428, 0x0FC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11           (_MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12              IOMUX_PAD(0x428, 0x0FC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46           (_MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16              IOMUX_PAD(0x42C, 0x100, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14              (_MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT16__GPIO6_2                    IOMUX_PAD(0x42C, 0x100, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18              (_MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT16__UART4_RTS                  IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__GPIO6_4            (_MX53_PAD_CSI0_DAT18__GPIO6_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4        IOMUX_PAD(0x42C, 0x100, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__UART5_RTS          (_MX53_PAD_CSI0_DAT18__UART5_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10           IOMUX_PAD(0x42C, 0x100, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6                (_MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45           IOMUX_PAD(0x42C, 0x100, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12           (_MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13              IOMUX_PAD(0x42C, 0x100, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47           (_MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17              IOMUX_PAD(0x430, 0x104, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15              (_MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT17__GPIO6_3                    IOMUX_PAD(0x430, 0x104, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19              (_MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT17__UART4_CTS                  IOMUX_PAD(0x430, 0x104, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__GPIO6_5            (_MX53_PAD_CSI0_DAT19__GPIO6_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5        IOMUX_PAD(0x430, 0x104, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__UART5_CTS          (_MX53_PAD_CSI0_DAT19__UART5_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11           IOMUX_PAD(0x430, 0x104, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7                (_MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46           IOMUX_PAD(0x430, 0x104, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13           (_MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14              IOMUX_PAD(0x430, 0x104, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48           (_MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18              IOMUX_PAD(0x434, 0x108, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK             (_MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT18__GPIO6_4                    IOMUX_PAD(0x434, 0x108, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__EMI_WEIM_A_25         (_MX53_PAD_EIM_A25__EMI_WEIM_A_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT18__UART5_RTS                  IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_A25__GPIO5_2               (_MX53_PAD_EIM_A25__GPIO5_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6        IOMUX_PAD(0x434, 0x108, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__ECSPI2_RDY            (_MX53_PAD_EIM_A25__ECSPI2_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12           IOMUX_PAD(0x434, 0x108, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__IPU_DI1_PIN12         (_MX53_PAD_EIM_A25__IPU_DI1_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47           IOMUX_PAD(0x434, 0x108, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__CSPI_SS1              (_MX53_PAD_EIM_A25__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15              IOMUX_PAD(0x434, 0x108, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS         (_MX53_PAD_EIM_A25__IPU_DI0_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19              IOMUX_PAD(0x438, 0x10C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__USBPHY1_BISTOK                (_MX53_PAD_EIM_A25__USBPHY1_BISTOK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT19__GPIO6_5                    IOMUX_PAD(0x438, 0x10C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2         (_MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT19__UART5_CTS                  IOMUX_PAD(0x438, 0x10C, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__GPIO2_30              (_MX53_PAD_EIM_EB2__GPIO2_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7        IOMUX_PAD(0x438, 0x10C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK               (_MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13           IOMUX_PAD(0x438, 0x10C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS              (_MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48           IOMUX_PAD(0x438, 0x10C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__ECSPI1_SS0            (_MX53_PAD_EIM_EB2__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK             IOMUX_PAD(0x438, 0x10C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__I2C2_SCL              (_MX53_PAD_EIM_EB2__I2C2_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C))
+#define MX53_PAD_EIM_A25__EMI_WEIM_A_25                 IOMUX_PAD(0x458, 0x110, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__EMI_WEIM_D_16         (_MX53_PAD_EIM_D16__EMI_WEIM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A25__GPIO5_2                       IOMUX_PAD(0x458, 0x110, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__GPIO3_16              (_MX53_PAD_EIM_D16__GPIO3_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A25__ECSPI2_RDY                    IOMUX_PAD(0x458, 0x110, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__IPU_DI0_PIN5          (_MX53_PAD_EIM_D16__IPU_DI0_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A25__IPU_DI1_PIN12                 IOMUX_PAD(0x458, 0x110, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK            (_MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A25__CSPI_SS1                      IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__ECSPI1_SCLK           (_MX53_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS                 IOMUX_PAD(0x458, 0x110, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__I2C2_SDA              (_MX53_PAD_EIM_D16__I2C2_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C))
+#define MX53_PAD_EIM_A25__USBPHY1_BISTOK                IOMUX_PAD(0x458, 0x110, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__EMI_WEIM_D_17         (_MX53_PAD_EIM_D17__EMI_WEIM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2                 IOMUX_PAD(0x45C, 0x114, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__GPIO3_17              (_MX53_PAD_EIM_D17__GPIO3_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB2__GPIO2_30                      IOMUX_PAD(0x45C, 0x114, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__IPU_DI0_PIN6          (_MX53_PAD_EIM_D17__IPU_DI0_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK               IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN            (_MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS              IOMUX_PAD(0x45C, 0x114, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__ECSPI1_MISO           (_MX53_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB2__ECSPI1_SS0                    IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__I2C3_SCL              (_MX53_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C))
+#define MX53_PAD_EIM_EB2__I2C2_SCL                      IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__EMI_WEIM_D_18         (_MX53_PAD_EIM_D18__EMI_WEIM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D16__EMI_WEIM_D_16                 IOMUX_PAD(0x460, 0x118, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__GPIO3_18              (_MX53_PAD_EIM_D18__GPIO3_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D16__GPIO3_16                      IOMUX_PAD(0x460, 0x118, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__IPU_DI0_PIN7          (_MX53_PAD_EIM_D18__IPU_DI0_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D16__IPU_DI0_PIN5                  IOMUX_PAD(0x460, 0x118, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO            (_MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK            IOMUX_PAD(0x460, 0x118, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__ECSPI1_MOSI           (_MX53_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D16__ECSPI1_SCLK                   IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__I2C3_SDA              (_MX53_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C))
+#define MX53_PAD_EIM_D16__I2C2_SDA                      IOMUX_PAD(0x460, 0x118, 5 | IOMUX_CONFIG_SION, 0x820, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS         (_MX53_PAD_EIM_D18__IPU_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D17__EMI_WEIM_D_17                 IOMUX_PAD(0x464, 0x11C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__EMI_WEIM_D_19         (_MX53_PAD_EIM_D19__EMI_WEIM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D17__GPIO3_17                      IOMUX_PAD(0x464, 0x11C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__GPIO3_19              (_MX53_PAD_EIM_D19__GPIO3_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D17__IPU_DI0_PIN6                  IOMUX_PAD(0x464, 0x11C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__IPU_DI0_PIN8          (_MX53_PAD_EIM_D19__IPU_DI0_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN            IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS             (_MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D17__ECSPI1_MISO                   IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__ECSPI1_SS1            (_MX53_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D17__I2C3_SCL                      IOMUX_PAD(0x464, 0x11C, 5 | IOMUX_CONFIG_SION, 0x824, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__EPIT1_EPITO           (_MX53_PAD_EIM_D19__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D18__EMI_WEIM_D_18                 IOMUX_PAD(0x468, 0x120, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__UART1_CTS             (_MX53_PAD_EIM_D19__UART1_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_EIM_D18__GPIO3_18                      IOMUX_PAD(0x468, 0x120, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC               (_MX53_PAD_EIM_D19__USBOH3_USBH2_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D18__IPU_DI0_PIN7                  IOMUX_PAD(0x468, 0x120, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__EMI_WEIM_D_20         (_MX53_PAD_EIM_D20__EMI_WEIM_D_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO            IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__GPIO3_20              (_MX53_PAD_EIM_D20__GPIO3_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D18__ECSPI1_MOSI                   IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__IPU_DI0_PIN16         (_MX53_PAD_EIM_D20__IPU_DI0_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D18__I2C3_SDA                      IOMUX_PAD(0x468, 0x120, 5 | IOMUX_CONFIG_SION, 0x828, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS              (_MX53_PAD_EIM_D20__IPU_SER_DISP0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS                 IOMUX_PAD(0x468, 0x120, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__CSPI_SS0              (_MX53_PAD_EIM_D20__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D19__EMI_WEIM_D_19                 IOMUX_PAD(0x46C, 0x124, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__EPIT2_EPITO           (_MX53_PAD_EIM_D20__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D19__GPIO3_19                      IOMUX_PAD(0x46C, 0x124, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__UART1_RTS             (_MX53_PAD_EIM_D20__UART1_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_EIM_D19__IPU_DI0_PIN8                  IOMUX_PAD(0x46C, 0x124, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR              (_MX53_PAD_EIM_D20__USBOH3_USBH2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS             IOMUX_PAD(0x46C, 0x124, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__EMI_WEIM_D_21         (_MX53_PAD_EIM_D21__EMI_WEIM_D_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D19__ECSPI1_SS1                    IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__GPIO3_21              (_MX53_PAD_EIM_D21__GPIO3_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D19__EPIT1_EPITO                   IOMUX_PAD(0x46C, 0x124, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__IPU_DI0_PIN17         (_MX53_PAD_EIM_D21__IPU_DI0_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D19__UART1_CTS                     IOMUX_PAD(0x46C, 0x124, 6, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK            (_MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC               IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__CSPI_SCLK             (_MX53_PAD_EIM_D21__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D20__EMI_WEIM_D_20                 IOMUX_PAD(0x470, 0x128, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__I2C1_SCL              (_MX53_PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C))
+#define MX53_PAD_EIM_D20__GPIO3_20                      IOMUX_PAD(0x470, 0x128, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC              (_MX53_PAD_EIM_D21__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D20__IPU_DI0_PIN16                 IOMUX_PAD(0x470, 0x128, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__EMI_WEIM_D_22         (_MX53_PAD_EIM_D22__EMI_WEIM_D_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS              IOMUX_PAD(0x470, 0x128, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__GPIO3_22              (_MX53_PAD_EIM_D22__GPIO3_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D20__CSPI_SS0                      IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__IPU_DI0_PIN1          (_MX53_PAD_EIM_D22__IPU_DI0_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D20__EPIT2_EPITO                   IOMUX_PAD(0x470, 0x128, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN            (_MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D20__UART1_RTS                     IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D22__CSPI_MISO             (_MX53_PAD_EIM_D22__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR              IOMUX_PAD(0x470, 0x128, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR             (_MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D21__EMI_WEIM_D_21                 IOMUX_PAD(0x474, 0x12C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__EMI_WEIM_D_23         (_MX53_PAD_EIM_D23__EMI_WEIM_D_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D21__GPIO3_21                      IOMUX_PAD(0x474, 0x12C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__GPIO3_23              (_MX53_PAD_EIM_D23__GPIO3_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D21__IPU_DI0_PIN17                 IOMUX_PAD(0x474, 0x12C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__UART3_CTS             (_MX53_PAD_EIM_D23__UART3_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK            IOMUX_PAD(0x474, 0x12C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__UART1_DCD             (_MX53_PAD_EIM_D23__UART1_DCD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D21__CSPI_SCLK                     IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS         (_MX53_PAD_EIM_D23__IPU_DI0_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D21__I2C1_SCL                      IOMUX_PAD(0x474, 0x12C, 5 | IOMUX_CONFIG_SION, 0x814, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__IPU_DI1_PIN2          (_MX53_PAD_EIM_D23__IPU_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC              IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN              (_MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D22__EMI_WEIM_D_22                 IOMUX_PAD(0x478, 0x130, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__IPU_DI1_PIN14         (_MX53_PAD_EIM_D23__IPU_DI1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D22__GPIO3_22                      IOMUX_PAD(0x478, 0x130, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3         (_MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D22__IPU_DI0_PIN1                  IOMUX_PAD(0x478, 0x130, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__GPIO2_31              (_MX53_PAD_EIM_EB3__GPIO2_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN            IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__UART3_RTS             (_MX53_PAD_EIM_EB3__UART3_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_EIM_D22__CSPI_MISO                     IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__UART1_RI              (_MX53_PAD_EIM_EB3__UART1_RI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR             IOMUX_PAD(0x478, 0x130, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3          (_MX53_PAD_EIM_EB3__IPU_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D23__EMI_WEIM_D_23                 IOMUX_PAD(0x47C, 0x134, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC                (_MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D23__GPIO3_23                      IOMUX_PAD(0x47C, 0x134, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16         (_MX53_PAD_EIM_EB3__IPU_DI1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D23__UART3_CTS                     IOMUX_PAD(0x47C, 0x134, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D24__EMI_WEIM_D_24         (_MX53_PAD_EIM_D24__EMI_WEIM_D_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D23__UART1_DCD                     IOMUX_PAD(0x47C, 0x134, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__GPIO3_24              (_MX53_PAD_EIM_D24__GPIO3_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS                 IOMUX_PAD(0x47C, 0x134, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__UART3_TXD_MUX         (_MX53_PAD_EIM_D24__UART3_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_EIM_D23__IPU_DI1_PIN2                  IOMUX_PAD(0x47C, 0x134, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__ECSPI1_SS2            (_MX53_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN              IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__CSPI_SS2              (_MX53_PAD_EIM_D24__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D23__IPU_DI1_PIN14                 IOMUX_PAD(0x47C, 0x134, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS              (_MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3                 IOMUX_PAD(0x480, 0x138, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__ECSPI2_SS2            (_MX53_PAD_EIM_D24__ECSPI2_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB3__GPIO2_31                      IOMUX_PAD(0x480, 0x138, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__UART1_DTR             (_MX53_PAD_EIM_D24__UART1_DTR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB3__UART3_RTS                     IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D25__EMI_WEIM_D_25         (_MX53_PAD_EIM_D25__EMI_WEIM_D_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB3__UART1_RI                      IOMUX_PAD(0x480, 0x138, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__GPIO3_25              (_MX53_PAD_EIM_D25__GPIO3_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3                  IOMUX_PAD(0x480, 0x138, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__UART3_RXD_MUX         (_MX53_PAD_EIM_D25__UART3_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC                IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__ECSPI1_SS3            (_MX53_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16                 IOMUX_PAD(0x480, 0x138, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__CSPI_SS3              (_MX53_PAD_EIM_D25__CSPI_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D24__EMI_WEIM_D_24                 IOMUX_PAD(0x484, 0x13C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC               (_MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D24__GPIO3_24                      IOMUX_PAD(0x484, 0x13C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__ECSPI2_SS3            (_MX53_PAD_EIM_D25__ECSPI2_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D24__UART3_TXD_MUX                 IOMUX_PAD(0x484, 0x13C, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D25__UART1_DSR             (_MX53_PAD_EIM_D25__UART1_DSR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D24__ECSPI1_SS2                    IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__EMI_WEIM_D_26         (_MX53_PAD_EIM_D26__EMI_WEIM_D_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D24__CSPI_SS2                      IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__GPIO3_26              (_MX53_PAD_EIM_D26__GPIO3_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS              IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__UART2_TXD_MUX         (_MX53_PAD_EIM_D26__UART2_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_EIM_D24__ECSPI2_SS2                    IOMUX_PAD(0x484, 0x13C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__FIRI_RXD              (_MX53_PAD_EIM_D26__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D24__UART1_DTR                     IOMUX_PAD(0x484, 0x13C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__IPU_CSI0_D_1          (_MX53_PAD_EIM_D26__IPU_CSI0_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D25__EMI_WEIM_D_25                 IOMUX_PAD(0x488, 0x140, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__IPU_DI1_PIN11         (_MX53_PAD_EIM_D26__IPU_DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D25__GPIO3_25                      IOMUX_PAD(0x488, 0x140, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__IPU_SISG_2            (_MX53_PAD_EIM_D26__IPU_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D25__UART3_RXD_MUX                 IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22              (_MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D25__ECSPI1_SS3                    IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__EMI_WEIM_D_27         (_MX53_PAD_EIM_D27__EMI_WEIM_D_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D25__CSPI_SS3                      IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__GPIO3_27              (_MX53_PAD_EIM_D27__GPIO3_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC               IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__UART2_RXD_MUX         (_MX53_PAD_EIM_D27__UART2_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_EIM_D25__ECSPI2_SS3                    IOMUX_PAD(0x488, 0x140, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__FIRI_TXD              (_MX53_PAD_EIM_D27__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D25__UART1_DSR                     IOMUX_PAD(0x488, 0x140, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__IPU_CSI0_D_0          (_MX53_PAD_EIM_D27__IPU_CSI0_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D26__EMI_WEIM_D_26                 IOMUX_PAD(0x48C, 0x144, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__IPU_DI1_PIN13         (_MX53_PAD_EIM_D27__IPU_DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D26__GPIO3_26                      IOMUX_PAD(0x48C, 0x144, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__IPU_SISG_3            (_MX53_PAD_EIM_D27__IPU_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D26__UART2_TXD_MUX                 IOMUX_PAD(0x48C, 0x144, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23              (_MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D26__FIRI_RXD                      IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__EMI_WEIM_D_28         (_MX53_PAD_EIM_D28__EMI_WEIM_D_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D26__IPU_CSI0_D_1                  IOMUX_PAD(0x48C, 0x144, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__GPIO3_28              (_MX53_PAD_EIM_D28__GPIO3_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D26__IPU_DI1_PIN11                 IOMUX_PAD(0x48C, 0x144, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__UART2_CTS             (_MX53_PAD_EIM_D28__UART2_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_EIM_D26__IPU_SISG_2                    IOMUX_PAD(0x48C, 0x144, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO            (_MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22              IOMUX_PAD(0x48C, 0x144, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__CSPI_MOSI             (_MX53_PAD_EIM_D28__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D27__EMI_WEIM_D_27                 IOMUX_PAD(0x490, 0x148, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__I2C1_SDA              (_MX53_PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C))
+#define MX53_PAD_EIM_D27__GPIO3_27                      IOMUX_PAD(0x490, 0x148, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__IPU_EXT_TRIG          (_MX53_PAD_EIM_D28__IPU_EXT_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D27__UART2_RXD_MUX                 IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D28__IPU_DI0_PIN13         (_MX53_PAD_EIM_D28__IPU_DI0_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D27__FIRI_TXD                      IOMUX_PAD(0x490, 0x148, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__EMI_WEIM_D_29         (_MX53_PAD_EIM_D29__EMI_WEIM_D_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D27__IPU_CSI0_D_0                  IOMUX_PAD(0x490, 0x148, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__GPIO3_29              (_MX53_PAD_EIM_D29__GPIO3_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D27__IPU_DI1_PIN13                 IOMUX_PAD(0x490, 0x148, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__UART2_RTS             (_MX53_PAD_EIM_D29__UART2_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_EIM_D27__IPU_SISG_3                    IOMUX_PAD(0x490, 0x148, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS             (_MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23              IOMUX_PAD(0x490, 0x148, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__CSPI_SS0              (_MX53_PAD_EIM_D29__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D28__EMI_WEIM_D_28                 IOMUX_PAD(0x494, 0x14C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__IPU_DI1_PIN15         (_MX53_PAD_EIM_D29__IPU_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D28__GPIO3_28                      IOMUX_PAD(0x494, 0x14C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC                (_MX53_PAD_EIM_D29__IPU_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D28__UART2_CTS                     IOMUX_PAD(0x494, 0x14C, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D29__IPU_DI0_PIN14         (_MX53_PAD_EIM_D29__IPU_DI0_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO            IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__EMI_WEIM_D_30         (_MX53_PAD_EIM_D30__EMI_WEIM_D_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D28__CSPI_MOSI                     IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__GPIO3_30              (_MX53_PAD_EIM_D30__GPIO3_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D28__I2C1_SDA                      IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, PAD_CTRL_I2C)
-#define MX53_PAD_EIM_D30__UART3_CTS             (_MX53_PAD_EIM_D30__UART3_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_EIM_D28__IPU_EXT_TRIG                  IOMUX_PAD(0x494, 0x14C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__IPU_CSI0_D_3          (_MX53_PAD_EIM_D30__IPU_CSI0_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D28__IPU_DI0_PIN13                 IOMUX_PAD(0x494, 0x14C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__IPU_DI0_PIN11         (_MX53_PAD_EIM_D30__IPU_DI0_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D29__EMI_WEIM_D_29                 IOMUX_PAD(0x498, 0x150, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21              (_MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D29__GPIO3_29                      IOMUX_PAD(0x498, 0x150, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC               (_MX53_PAD_EIM_D30__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D29__UART2_RTS                     IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC               (_MX53_PAD_EIM_D30__USBOH3_USBH2_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS             IOMUX_PAD(0x498, 0x150, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__EMI_WEIM_D_31         (_MX53_PAD_EIM_D31__EMI_WEIM_D_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D29__CSPI_SS0                      IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__GPIO3_31              (_MX53_PAD_EIM_D31__GPIO3_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D29__IPU_DI1_PIN15                 IOMUX_PAD(0x498, 0x150, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__UART3_RTS             (_MX53_PAD_EIM_D31__UART3_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC                IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__IPU_CSI0_D_2          (_MX53_PAD_EIM_D31__IPU_CSI0_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D29__IPU_DI0_PIN14                 IOMUX_PAD(0x498, 0x150, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__IPU_DI0_PIN12         (_MX53_PAD_EIM_D31__IPU_DI0_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D30__EMI_WEIM_D_30                 IOMUX_PAD(0x49C, 0x154, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20              (_MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D30__GPIO3_30                      IOMUX_PAD(0x49C, 0x154, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR              (_MX53_PAD_EIM_D31__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D30__UART3_CTS                     IOMUX_PAD(0x49C, 0x154, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR              (_MX53_PAD_EIM_D31__USBOH3_USBH2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D30__IPU_CSI0_D_3                  IOMUX_PAD(0x49C, 0x154, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__EMI_WEIM_A_24         (_MX53_PAD_EIM_A24__EMI_WEIM_A_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D30__IPU_DI0_PIN11                 IOMUX_PAD(0x49C, 0x154, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__GPIO5_4               (_MX53_PAD_EIM_A24__GPIO5_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21              IOMUX_PAD(0x49C, 0x154, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19              (_MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC               IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__IPU_CSI1_D_19         (_MX53_PAD_EIM_A24__IPU_CSI1_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC               IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__IPU_SISG_2            (_MX53_PAD_EIM_A24__IPU_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D31__EMI_WEIM_D_31                 IOMUX_PAD(0x4A0, 0x158, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__USBPHY2_BVALID                (_MX53_PAD_EIM_A24__USBPHY2_BVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D31__GPIO3_31                      IOMUX_PAD(0x4A0, 0x158, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__EMI_WEIM_A_23         (_MX53_PAD_EIM_A23__EMI_WEIM_A_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D31__UART3_RTS                     IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_A23__GPIO6_6               (_MX53_PAD_EIM_A23__GPIO6_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D31__IPU_CSI0_D_2                  IOMUX_PAD(0x4A0, 0x158, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18              (_MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D31__IPU_DI0_PIN12                 IOMUX_PAD(0x4A0, 0x158, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__IPU_CSI1_D_18         (_MX53_PAD_EIM_A23__IPU_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20              IOMUX_PAD(0x4A0, 0x158, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__IPU_SISG_3            (_MX53_PAD_EIM_A23__IPU_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR              IOMUX_PAD(0x4A0, 0x158, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION            (_MX53_PAD_EIM_A23__USBPHY2_ENDSESSION | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR              IOMUX_PAD(0x4A0, 0x158, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A22__EMI_WEIM_A_22         (_MX53_PAD_EIM_A22__EMI_WEIM_A_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A24__EMI_WEIM_A_24                 IOMUX_PAD(0x4A8, 0x15C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A22__GPIO2_16              (_MX53_PAD_EIM_A22__GPIO2_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A24__GPIO5_4                       IOMUX_PAD(0x4A8, 0x15C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17              (_MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19              IOMUX_PAD(0x4A8, 0x15C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A22__IPU_CSI1_D_17         (_MX53_PAD_EIM_A22__IPU_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A24__IPU_CSI1_D_19                 IOMUX_PAD(0x4A8, 0x15C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7         (_MX53_PAD_EIM_A22__SRC_BT_CFG1_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A24__IPU_SISG_2                    IOMUX_PAD(0x4A8, 0x15C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A21__EMI_WEIM_A_21         (_MX53_PAD_EIM_A21__EMI_WEIM_A_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A24__USBPHY2_BVALID                IOMUX_PAD(0x4A8, 0x15C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A21__GPIO2_17              (_MX53_PAD_EIM_A21__GPIO2_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A23__EMI_WEIM_A_23                 IOMUX_PAD(0x4AC, 0x160, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16              (_MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A23__GPIO6_6                       IOMUX_PAD(0x4AC, 0x160, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A21__IPU_CSI1_D_16         (_MX53_PAD_EIM_A21__IPU_CSI1_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18              IOMUX_PAD(0x4AC, 0x160, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6         (_MX53_PAD_EIM_A21__SRC_BT_CFG1_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A23__IPU_CSI1_D_18                 IOMUX_PAD(0x4AC, 0x160, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A20__EMI_WEIM_A_20         (_MX53_PAD_EIM_A20__EMI_WEIM_A_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A23__IPU_SISG_3                    IOMUX_PAD(0x4AC, 0x160, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A20__GPIO2_18              (_MX53_PAD_EIM_A20__GPIO2_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION            IOMUX_PAD(0x4AC, 0x160, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15              (_MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A22__EMI_WEIM_A_22                 IOMUX_PAD(0x4B0, 0x164, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A20__IPU_CSI1_D_15         (_MX53_PAD_EIM_A20__IPU_CSI1_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A22__GPIO2_16                      IOMUX_PAD(0x4B0, 0x164, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5         (_MX53_PAD_EIM_A20__SRC_BT_CFG1_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17              IOMUX_PAD(0x4B0, 0x164, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A19__EMI_WEIM_A_19         (_MX53_PAD_EIM_A19__EMI_WEIM_A_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A22__IPU_CSI1_D_17                 IOMUX_PAD(0x4B0, 0x164, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A19__GPIO2_19              (_MX53_PAD_EIM_A19__GPIO2_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7                 IOMUX_PAD(0x4B0, 0x164, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14              (_MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A21__EMI_WEIM_A_21                 IOMUX_PAD(0x4B4, 0x168, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A19__IPU_CSI1_D_14         (_MX53_PAD_EIM_A19__IPU_CSI1_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A21__GPIO2_17                      IOMUX_PAD(0x4B4, 0x168, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4         (_MX53_PAD_EIM_A19__SRC_BT_CFG1_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16              IOMUX_PAD(0x4B4, 0x168, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A18__EMI_WEIM_A_18         (_MX53_PAD_EIM_A18__EMI_WEIM_A_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A21__IPU_CSI1_D_16                 IOMUX_PAD(0x4B4, 0x168, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A18__GPIO2_20              (_MX53_PAD_EIM_A18__GPIO2_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6                 IOMUX_PAD(0x4B4, 0x168, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13              (_MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A20__EMI_WEIM_A_20                 IOMUX_PAD(0x4B8, 0x16C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A18__IPU_CSI1_D_13         (_MX53_PAD_EIM_A18__IPU_CSI1_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A20__GPIO2_18                      IOMUX_PAD(0x4B8, 0x16C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3         (_MX53_PAD_EIM_A18__SRC_BT_CFG1_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15              IOMUX_PAD(0x4B8, 0x16C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A17__EMI_WEIM_A_17         (_MX53_PAD_EIM_A17__EMI_WEIM_A_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A20__IPU_CSI1_D_15                 IOMUX_PAD(0x4B8, 0x16C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A17__GPIO2_21              (_MX53_PAD_EIM_A17__GPIO2_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5                 IOMUX_PAD(0x4B8, 0x16C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12              (_MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A19__EMI_WEIM_A_19                 IOMUX_PAD(0x4BC, 0x170, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A17__IPU_CSI1_D_12         (_MX53_PAD_EIM_A17__IPU_CSI1_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A19__GPIO2_19                      IOMUX_PAD(0x4BC, 0x170, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2         (_MX53_PAD_EIM_A17__SRC_BT_CFG1_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14              IOMUX_PAD(0x4BC, 0x170, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A16__EMI_WEIM_A_16         (_MX53_PAD_EIM_A16__EMI_WEIM_A_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A19__IPU_CSI1_D_14                 IOMUX_PAD(0x4BC, 0x170, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A16__GPIO2_22              (_MX53_PAD_EIM_A16__GPIO2_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4                 IOMUX_PAD(0x4BC, 0x170, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK              (_MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A18__EMI_WEIM_A_18                 IOMUX_PAD(0x4C0, 0x174, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK               (_MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A18__GPIO2_20                      IOMUX_PAD(0x4C0, 0x174, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1         (_MX53_PAD_EIM_A16__SRC_BT_CFG1_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13              IOMUX_PAD(0x4C0, 0x174, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0         (_MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A18__IPU_CSI1_D_13                 IOMUX_PAD(0x4C0, 0x174, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS0__GPIO2_23              (_MX53_PAD_EIM_CS0__GPIO2_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3                 IOMUX_PAD(0x4C0, 0x174, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS0__ECSPI2_SCLK           (_MX53_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A17__EMI_WEIM_A_17                 IOMUX_PAD(0x4C4, 0x178, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5          (_MX53_PAD_EIM_CS0__IPU_DI1_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A17__GPIO2_21                      IOMUX_PAD(0x4C4, 0x178, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1         (_MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12              IOMUX_PAD(0x4C4, 0x178, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS1__GPIO2_24              (_MX53_PAD_EIM_CS1__GPIO2_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A17__IPU_CSI1_D_12                 IOMUX_PAD(0x4C4, 0x178, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS1__ECSPI2_MOSI           (_MX53_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2                 IOMUX_PAD(0x4C4, 0x178, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6          (_MX53_PAD_EIM_CS1__IPU_DI1_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A16__EMI_WEIM_A_16                 IOMUX_PAD(0x4C8, 0x17C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_OE__EMI_WEIM_OE            (_MX53_PAD_EIM_OE__EMI_WEIM_OE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A16__GPIO2_22                      IOMUX_PAD(0x4C8, 0x17C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_OE__GPIO2_25               (_MX53_PAD_EIM_OE__GPIO2_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK              IOMUX_PAD(0x4C8, 0x17C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_OE__ECSPI2_MISO            (_MX53_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK               IOMUX_PAD(0x4C8, 0x17C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_OE__IPU_DI1_PIN7           (_MX53_PAD_EIM_OE__IPU_DI1_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1                 IOMUX_PAD(0x4C8, 0x17C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_OE__USBPHY2_IDDIG          (_MX53_PAD_EIM_OE__USBPHY2_IDDIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0                 IOMUX_PAD(0x4CC, 0x180, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_RW__EMI_WEIM_RW            (_MX53_PAD_EIM_RW__EMI_WEIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_CS0__GPIO2_23                      IOMUX_PAD(0x4CC, 0x180, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_RW__GPIO2_26               (_MX53_PAD_EIM_RW__GPIO2_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_CS0__ECSPI2_SCLK                   IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_RW__ECSPI2_SS0             (_MX53_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5                  IOMUX_PAD(0x4CC, 0x180, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_RW__IPU_DI1_PIN8           (_MX53_PAD_EIM_RW__IPU_DI1_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1                 IOMUX_PAD(0x4D0, 0x184, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT         (_MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_CS1__GPIO2_24                      IOMUX_PAD(0x4D0, 0x184, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA          (_MX53_PAD_EIM_LBA__EMI_WEIM_LBA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_CS1__ECSPI2_MOSI                   IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_LBA__GPIO2_27              (_MX53_PAD_EIM_LBA__GPIO2_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6                  IOMUX_PAD(0x4D0, 0x184, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_LBA__ECSPI2_SS1            (_MX53_PAD_EIM_LBA__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_OE__EMI_WEIM_OE                    IOMUX_PAD(0x4D4, 0x188, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17         (_MX53_PAD_EIM_LBA__IPU_DI1_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_OE__GPIO2_25                       IOMUX_PAD(0x4D4, 0x188, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0         (_MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_OE__ECSPI2_MISO                    IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0         (_MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_OE__IPU_DI1_PIN7                   IOMUX_PAD(0x4D4, 0x188, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__GPIO2_28              (_MX53_PAD_EIM_EB0__GPIO2_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_OE__USBPHY2_IDDIG                  IOMUX_PAD(0x4D4, 0x188, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11              (_MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_RW__EMI_WEIM_RW                    IOMUX_PAD(0x4D8, 0x18C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11         (_MX53_PAD_EIM_EB0__IPU_CSI1_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_RW__GPIO2_26                       IOMUX_PAD(0x4D8, 0x18C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY          (_MX53_PAD_EIM_EB0__GPC_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_RW__ECSPI2_SS0                     IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7         (_MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_RW__IPU_DI1_PIN8                   IOMUX_PAD(0x4D8, 0x18C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1         (_MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT         IOMUX_PAD(0x4D8, 0x18C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB1__GPIO2_29              (_MX53_PAD_EIM_EB1__GPIO2_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA                  IOMUX_PAD(0x4DC, 0x190, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10              (_MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_LBA__GPIO2_27                      IOMUX_PAD(0x4DC, 0x190, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10         (_MX53_PAD_EIM_EB1__IPU_CSI1_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_LBA__ECSPI2_SS1                    IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6         (_MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17                 IOMUX_PAD(0x4DC, 0x190, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0            (_MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0                 IOMUX_PAD(0x4DC, 0x190, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA0__GPIO3_0               (_MX53_PAD_EIM_DA0__GPIO3_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0                 IOMUX_PAD(0x4E4, 0x194, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9               (_MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB0__GPIO2_28                      IOMUX_PAD(0x4E4, 0x194, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9          (_MX53_PAD_EIM_DA0__IPU_CSI1_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11              IOMUX_PAD(0x4E4, 0x194, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5         (_MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11                 IOMUX_PAD(0x4E4, 0x194, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1            (_MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY                  IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA1__GPIO3_1               (_MX53_PAD_EIM_DA1__GPIO3_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7                 IOMUX_PAD(0x4E4, 0x194, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8               (_MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1                 IOMUX_PAD(0x4E8, 0x198, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8          (_MX53_PAD_EIM_DA1__IPU_CSI1_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB1__GPIO2_29                      IOMUX_PAD(0x4E8, 0x198, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4         (_MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10              IOMUX_PAD(0x4E8, 0x198, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2            (_MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10                 IOMUX_PAD(0x4E8, 0x198, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA2__GPIO3_2               (_MX53_PAD_EIM_DA2__GPIO3_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6                 IOMUX_PAD(0x4E8, 0x198, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7               (_MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0            IOMUX_PAD(0x4EC, 0x19C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7          (_MX53_PAD_EIM_DA2__IPU_CSI1_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA0__GPIO3_0                       IOMUX_PAD(0x4EC, 0x19C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3         (_MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9               IOMUX_PAD(0x4EC, 0x19C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3            (_MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9                  IOMUX_PAD(0x4EC, 0x19C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA3__GPIO3_3               (_MX53_PAD_EIM_DA3__GPIO3_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5                 IOMUX_PAD(0x4EC, 0x19C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6               (_MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1            IOMUX_PAD(0x4F0, 0x1A0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6          (_MX53_PAD_EIM_DA3__IPU_CSI1_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA1__GPIO3_1                       IOMUX_PAD(0x4F0, 0x1A0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2         (_MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8               IOMUX_PAD(0x4F0, 0x1A0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4            (_MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8                  IOMUX_PAD(0x4F0, 0x1A0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA4__GPIO3_4               (_MX53_PAD_EIM_DA4__GPIO3_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4                 IOMUX_PAD(0x4F0, 0x1A0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5               (_MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2            IOMUX_PAD(0x4F4, 0x1A4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5          (_MX53_PAD_EIM_DA4__IPU_CSI1_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA2__GPIO3_2                       IOMUX_PAD(0x4F4, 0x1A4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7         (_MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7               IOMUX_PAD(0x4F4, 0x1A4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5            (_MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7                  IOMUX_PAD(0x4F4, 0x1A4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA5__GPIO3_5               (_MX53_PAD_EIM_DA5__GPIO3_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3                 IOMUX_PAD(0x4F4, 0x1A4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4               (_MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3            IOMUX_PAD(0x4F8, 0x1A8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4          (_MX53_PAD_EIM_DA5__IPU_CSI1_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA3__GPIO3_3                       IOMUX_PAD(0x4F8, 0x1A8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6         (_MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6               IOMUX_PAD(0x4F8, 0x1A8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6            (_MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6                  IOMUX_PAD(0x4F8, 0x1A8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA6__GPIO3_6               (_MX53_PAD_EIM_DA6__GPIO3_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2                 IOMUX_PAD(0x4F8, 0x1A8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3               (_MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4            IOMUX_PAD(0x4FC, 0x1AC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3          (_MX53_PAD_EIM_DA6__IPU_CSI1_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA4__GPIO3_4                       IOMUX_PAD(0x4FC, 0x1AC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5         (_MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5               IOMUX_PAD(0x4FC, 0x1AC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7            (_MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5                  IOMUX_PAD(0x4FC, 0x1AC, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA7__GPIO3_7               (_MX53_PAD_EIM_DA7__GPIO3_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7                 IOMUX_PAD(0x4FC, 0x1AC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2               (_MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5            IOMUX_PAD(0x500, 0x1B0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2          (_MX53_PAD_EIM_DA7__IPU_CSI1_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA5__GPIO3_5                       IOMUX_PAD(0x500, 0x1B0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4         (_MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4               IOMUX_PAD(0x500, 0x1B0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8            (_MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4                  IOMUX_PAD(0x500, 0x1B0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA8__GPIO3_8               (_MX53_PAD_EIM_DA8__GPIO3_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6                 IOMUX_PAD(0x500, 0x1B0, 7 | IOMUX_CONFIG_SION, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1               (_MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6            IOMUX_PAD(0x504, 0x1B4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1          (_MX53_PAD_EIM_DA8__IPU_CSI1_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA6__GPIO3_6                       IOMUX_PAD(0x504, 0x1B4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3         (_MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3               IOMUX_PAD(0x504, 0x1B4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9            (_MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3                  IOMUX_PAD(0x504, 0x1B4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA9__GPIO3_9               (_MX53_PAD_EIM_DA9__GPIO3_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5                 IOMUX_PAD(0x504, 0x1B4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0               (_MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7            IOMUX_PAD(0x508, 0x1B8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0          (_MX53_PAD_EIM_DA9__IPU_CSI1_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA7__GPIO3_7                       IOMUX_PAD(0x508, 0x1B8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2         (_MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2               IOMUX_PAD(0x508, 0x1B8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10          (_MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2                  IOMUX_PAD(0x508, 0x1B8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA10__GPIO3_10             (_MX53_PAD_EIM_DA10__GPIO3_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4                 IOMUX_PAD(0x508, 0x1B8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15                (_MX53_PAD_EIM_DA10__IPU_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8            IOMUX_PAD(0x50C, 0x1BC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN             (_MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA8__GPIO3_8                       IOMUX_PAD(0x50C, 0x1BC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1                (_MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1               IOMUX_PAD(0x50C, 0x1BC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11          (_MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1                  IOMUX_PAD(0x50C, 0x1BC, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA11__GPIO3_11             (_MX53_PAD_EIM_DA11__GPIO3_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3                 IOMUX_PAD(0x50C, 0x1BC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2         (_MX53_PAD_EIM_DA11__IPU_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9            IOMUX_PAD(0x510, 0x1C0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC               (_MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA9__GPIO3_9                       IOMUX_PAD(0x510, 0x1C0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12          (_MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0               IOMUX_PAD(0x510, 0x1C0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA12__GPIO3_12             (_MX53_PAD_EIM_DA12__GPIO3_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0                  IOMUX_PAD(0x510, 0x1C0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3         (_MX53_PAD_EIM_DA12__IPU_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2                 IOMUX_PAD(0x510, 0x1C0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC               (_MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10          IOMUX_PAD(0x514, 0x1C4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13          (_MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA10__GPIO3_10                     IOMUX_PAD(0x514, 0x1C4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA13__GPIO3_13             (_MX53_PAD_EIM_DA13__GPIO3_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15                IOMUX_PAD(0x514, 0x1C4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS                (_MX53_PAD_EIM_DA13__IPU_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN             IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK              (_MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1                IOMUX_PAD(0x514, 0x1C4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14          (_MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11          IOMUX_PAD(0x518, 0x1C8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA14__GPIO3_14             (_MX53_PAD_EIM_DA14__GPIO3_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA11__GPIO3_11                     IOMUX_PAD(0x518, 0x1C8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS                (_MX53_PAD_EIM_DA14__IPU_DI1_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2                 IOMUX_PAD(0x518, 0x1C8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK              (_MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC               IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15          (_MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12          IOMUX_PAD(0x51C, 0x1CC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA15__GPIO3_15             (_MX53_PAD_EIM_DA15__GPIO3_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA12__GPIO3_12                     IOMUX_PAD(0x51C, 0x1CC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1         (_MX53_PAD_EIM_DA15__IPU_DI1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3                 IOMUX_PAD(0x51C, 0x1CC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4         (_MX53_PAD_EIM_DA15__IPU_DI1_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC               IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B             (_MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13          IOMUX_PAD(0x520, 0x1D0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_WE_B__GPIO6_12           (_MX53_PAD_NANDF_WE_B__GPIO6_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA13__GPIO3_13                     IOMUX_PAD(0x520, 0x1D0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B             (_MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS                IOMUX_PAD(0x520, 0x1D0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_RE_B__GPIO6_13           (_MX53_PAD_NANDF_RE_B__GPIO6_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK              IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT                (_MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14          IOMUX_PAD(0x524, 0x1D4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_WAIT__GPIO5_0              (_MX53_PAD_EIM_WAIT__GPIO5_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA14__GPIO3_14                     IOMUX_PAD(0x524, 0x1D4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B             (_MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS                IOMUX_PAD(0x524, 0x1D4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX3_P__GPIO6_22          (_MX53_PAD_LVDS1_TX3_P__GPIO6_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK              IOMUX_PAD(0x524, 0x1D4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3             (_MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15          IOMUX_PAD(0x528, 0x1D8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX2_P__GPIO6_24          (_MX53_PAD_LVDS1_TX2_P__GPIO6_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA15__GPIO3_15                     IOMUX_PAD(0x528, 0x1D8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2             (_MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1                 IOMUX_PAD(0x528, 0x1D8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_CLK_P__GPIO6_26          (_MX53_PAD_LVDS1_CLK_P__GPIO6_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4                 IOMUX_PAD(0x528, 0x1D8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK             (_MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B             IOMUX_PAD(0x52C, 0x1DC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX1_P__GPIO6_28          (_MX53_PAD_LVDS1_TX1_P__GPIO6_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_WE_B__GPIO6_12                   IOMUX_PAD(0x52C, 0x1DC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1             (_MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B             IOMUX_PAD(0x530, 0x1E0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX0_P__GPIO6_30          (_MX53_PAD_LVDS1_TX0_P__GPIO6_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_RE_B__GPIO6_13                   IOMUX_PAD(0x530, 0x1E0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0             (_MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT                IOMUX_PAD(0x534, 0x1E4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX3_P__GPIO7_22          (_MX53_PAD_LVDS0_TX3_P__GPIO7_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_WAIT__GPIO5_0                      IOMUX_PAD(0x534, 0x1E4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3             (_MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B             IOMUX_PAD(0x534, 0x1E4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_CLK_P__GPIO7_24          (_MX53_PAD_LVDS0_CLK_P__GPIO7_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS1_TX3_P__GPIO6_22                  IOMUX_PAD(__NA_, 0x1EC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK             (_MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3             IOMUX_PAD(__NA_, 0x1EC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX2_P__GPIO7_26          (_MX53_PAD_LVDS0_TX2_P__GPIO7_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS1_TX2_P__GPIO6_24                  IOMUX_PAD(__NA_, 0x1F0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2             (_MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2             IOMUX_PAD(__NA_, 0x1F0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX1_P__GPIO7_28          (_MX53_PAD_LVDS0_TX1_P__GPIO7_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS1_CLK_P__GPIO6_26                  IOMUX_PAD(__NA_, 0x1F4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1             (_MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK             IOMUX_PAD(__NA_, 0x1F4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX0_P__GPIO7_30          (_MX53_PAD_LVDS0_TX0_P__GPIO7_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS1_TX1_P__GPIO6_28                  IOMUX_PAD(__NA_, 0x1F8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0             (_MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1             IOMUX_PAD(__NA_, 0x1F8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_10__GPIO4_0               (_MX53_PAD_GPIO_10__GPIO4_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS1_TX0_P__GPIO6_30                  IOMUX_PAD(__NA_, 0x1FC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_10__OSC32k_32K_OUT                (_MX53_PAD_GPIO_10__OSC32k_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0             IOMUX_PAD(__NA_, 0x1FC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_11__GPIO4_1               (_MX53_PAD_GPIO_11__GPIO4_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS0_TX3_P__GPIO7_22                  IOMUX_PAD(__NA_, 0x200, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_12__GPIO4_2               (_MX53_PAD_GPIO_12__GPIO4_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3             IOMUX_PAD(__NA_, 0x200, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_13__GPIO4_3               (_MX53_PAD_GPIO_13__GPIO4_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS0_CLK_P__GPIO7_24                  IOMUX_PAD(__NA_, 0x204, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_14__GPIO4_4               (_MX53_PAD_GPIO_14__GPIO4_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK             IOMUX_PAD(__NA_, 0x204, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE               (_MX53_PAD_NANDF_CLE__EMI_NANDF_CLE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS0_TX2_P__GPIO7_26                  IOMUX_PAD(__NA_, 0x208, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CLE__GPIO6_7             (_MX53_PAD_NANDF_CLE__GPIO6_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2             IOMUX_PAD(__NA_, 0x208, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0           (_MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS0_TX1_P__GPIO7_28                  IOMUX_PAD(__NA_, 0x20C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE               (_MX53_PAD_NANDF_ALE__EMI_NANDF_ALE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1             IOMUX_PAD(__NA_, 0x20C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_ALE__GPIO6_8             (_MX53_PAD_NANDF_ALE__GPIO6_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS0_TX0_P__GPIO7_30                  IOMUX_PAD(__NA_, 0x210, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1           (_MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0             IOMUX_PAD(__NA_, 0x210, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B             (_MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_10__GPIO4_0                       IOMUX_PAD(0x540, 0x214, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_WP_B__GPIO6_9            (_MX53_PAD_NANDF_WP_B__GPIO6_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_10__OSC32k_32K_OUT                IOMUX_PAD(0x540, 0x214, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2          (_MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_11__GPIO4_1                       IOMUX_PAD(0x544, 0x218, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0              (_MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_12__GPIO4_2                       IOMUX_PAD(0x548, 0x21C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_RB0__GPIO6_10            (_MX53_PAD_NANDF_RB0__GPIO6_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_13__GPIO4_3                       IOMUX_PAD(0x54C, 0x220, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3           (_MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_14__GPIO4_4                       IOMUX_PAD(0x550, 0x224, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0              (_MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE               IOMUX_PAD(0x5A0, 0x228, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS0__GPIO6_11            (_MX53_PAD_NANDF_CS0__GPIO6_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CLE__GPIO6_7                     IOMUX_PAD(0x5A0, 0x228, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4           (_MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0           IOMUX_PAD(0x5A0, 0x228, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1              (_MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE               IOMUX_PAD(0x5A4, 0x22C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS1__GPIO6_14            (_MX53_PAD_NANDF_CS1__GPIO6_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_ALE__GPIO6_8                     IOMUX_PAD(0x5A4, 0x22C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS1__MLB_MLBCLK          (_MX53_PAD_NANDF_CS1__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1           IOMUX_PAD(0x5A4, 0x22C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5           (_MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B             IOMUX_PAD(0x5A8, 0x230, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2              (_MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_WP_B__GPIO6_9                    IOMUX_PAD(0x5A8, 0x230, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__GPIO6_15            (_MX53_PAD_NANDF_CS2__GPIO6_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2          IOMUX_PAD(0x5A8, 0x230, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__IPU_SISG_0          (_MX53_PAD_NANDF_CS2__IPU_SISG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0              IOMUX_PAD(0x5AC, 0x234, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__ESAI1_TX0           (_MX53_PAD_NANDF_CS2__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_RB0__GPIO6_10                    IOMUX_PAD(0x5AC, 0x234, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE                (_MX53_PAD_NANDF_CS2__EMI_WEIM_CRE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3           IOMUX_PAD(0x5AC, 0x234, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK               (_MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0              IOMUX_PAD(0x5B0, 0x238, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__MLB_MLBSIG          (_MX53_PAD_NANDF_CS2__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS0__GPIO6_11                    IOMUX_PAD(0x5B0, 0x238, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6           (_MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4           IOMUX_PAD(0x5B0, 0x238, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3              (_MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1              IOMUX_PAD(0x5B4, 0x23C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__GPIO6_16            (_MX53_PAD_NANDF_CS3__GPIO6_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS1__GPIO6_14                    IOMUX_PAD(0x5B4, 0x23C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__IPU_SISG_1          (_MX53_PAD_NANDF_CS3__IPU_SISG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS1__MLB_MLBCLK                  IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__ESAI1_TX1           (_MX53_PAD_NANDF_CS3__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5           IOMUX_PAD(0x5B4, 0x23C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26               (_MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2              IOMUX_PAD(0x5B8, 0x240, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__MLB_MLBDAT          (_MX53_PAD_NANDF_CS3__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS2__GPIO6_15                    IOMUX_PAD(0x5B8, 0x240, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7           (_MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS2__IPU_SISG_0                  IOMUX_PAD(0x5B8, 0x240, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__FEC_MDIO             (_MX53_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS2__ESAI1_TX0                   IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__GPIO1_22             (_MX53_PAD_FEC_MDIO__GPIO1_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE                IOMUX_PAD(0x5B8, 0x240, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__ESAI1_SCKR           (_MX53_PAD_FEC_MDIO__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK               IOMUX_PAD(0x5B8, 0x240, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__FEC_COL              (_MX53_PAD_FEC_MDIO__FEC_COL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS2__MLB_MLBSIG                  IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2               (_MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6           IOMUX_PAD(0x5B8, 0x240, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3              (_MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3              IOMUX_PAD(0x5BC, 0x244, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49             (_MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS3__GPIO6_16                    IOMUX_PAD(0x5BC, 0x244, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK                (_MX53_PAD_FEC_REF_CLK__FEC_TX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS3__IPU_SISG_1                  IOMUX_PAD(0x5BC, 0x244, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_REF_CLK__GPIO1_23          (_MX53_PAD_FEC_REF_CLK__GPIO1_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS3__ESAI1_TX1                   IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR         (_MX53_PAD_FEC_REF_CLK__ESAI1_FSR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26               IOMUX_PAD(0x5BC, 0x244, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4           (_MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS3__MLB_MLBDAT                  IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50          (_MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7           IOMUX_PAD(0x5BC, 0x244, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RX_ER__FEC_RX_ER           (_MX53_PAD_FEC_RX_ER__FEC_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDIO__FEC_MDIO                     IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RX_ER__GPIO1_24            (_MX53_PAD_FEC_RX_ER__GPIO1_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDIO__GPIO1_22                     IOMUX_PAD(0x5C4, 0x248, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR          (_MX53_PAD_FEC_RX_ER__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDIO__ESAI1_SCKR                   IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK          (_MX53_PAD_FEC_RX_ER__FEC_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDIO__FEC_COL                      IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3              (_MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2               IOMUX_PAD(0x5C4, 0x248, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV          (_MX53_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3      IOMUX_PAD(0x5C4, 0x248, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_CRS_DV__GPIO1_25           (_MX53_PAD_FEC_CRS_DV__GPIO1_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49             IOMUX_PAD(0x5C4, 0x248, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT         (_MX53_PAD_FEC_CRS_DV__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK                IOMUX_PAD(0x5C8, 0x24C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD1__FEC_RDATA_1          (_MX53_PAD_FEC_RXD1__FEC_RDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_REF_CLK__GPIO1_23                  IOMUX_PAD(0x5C8, 0x24C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD1__GPIO1_26             (_MX53_PAD_FEC_RXD1__GPIO1_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR                 IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD1__ESAI1_FST            (_MX53_PAD_FEC_RXD1__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4   IOMUX_PAD(0x5C8, 0x24C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD1__MLB_MLBSIG           (_MX53_PAD_FEC_RXD1__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50          IOMUX_PAD(0x5C8, 0x24C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1               (_MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RX_ER__FEC_RX_ER                   IOMUX_PAD(0x5CC, 0x250, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD0__FEC_RDATA_0          (_MX53_PAD_FEC_RXD0__FEC_RDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RX_ER__GPIO1_24                    IOMUX_PAD(0x5CC, 0x250, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD0__GPIO1_27             (_MX53_PAD_FEC_RXD0__GPIO1_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR                  IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD0__ESAI1_HCKT           (_MX53_PAD_FEC_RXD0__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK                  IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT               (_MX53_PAD_FEC_RXD0__OSC32k_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3              IOMUX_PAD(0x5CC, 0x250, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TX_EN__FEC_TX_EN           (_MX53_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV                  IOMUX_PAD(0x5D0, 0x254, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TX_EN__GPIO1_28            (_MX53_PAD_FEC_TX_EN__GPIO1_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_CRS_DV__GPIO1_25                   IOMUX_PAD(0x5D0, 0x254, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2               (_MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT                 IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD1__FEC_TDATA_1          (_MX53_PAD_FEC_TXD1__FEC_TDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RXD1__FEC_RDATA_1                  IOMUX_PAD(0x5D4, 0x258, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD1__GPIO1_29             (_MX53_PAD_FEC_TXD1__GPIO1_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RXD1__GPIO1_26                     IOMUX_PAD(0x5D4, 0x258, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3                (_MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RXD1__ESAI1_FST                    IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD1__MLB_MLBCLK           (_MX53_PAD_FEC_TXD1__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RXD1__MLB_MLBSIG                   IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK          (_MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1               IOMUX_PAD(0x5D4, 0x258, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD0__FEC_TDATA_0          (_MX53_PAD_FEC_TXD0__FEC_TDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RXD0__FEC_RDATA_0                  IOMUX_PAD(0x5D8, 0x25C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD0__GPIO1_30             (_MX53_PAD_FEC_TXD0__GPIO1_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RXD0__GPIO1_27                     IOMUX_PAD(0x5D8, 0x25C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1                (_MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RXD0__ESAI1_HCKT                   IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0            (_MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT               IOMUX_PAD(0x5D8, 0x25C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__FEC_MDC               (_MX53_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TX_EN__FEC_TX_EN                   IOMUX_PAD(0x5DC, 0x260, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__GPIO1_31              (_MX53_PAD_FEC_MDC__GPIO1_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TX_EN__GPIO1_28                    IOMUX_PAD(0x5DC, 0x260, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0         (_MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2               IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__MLB_MLBDAT            (_MX53_PAD_FEC_MDC__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TXD1__FEC_TDATA_1                  IOMUX_PAD(0x5E0, 0x264, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG                (_MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TXD1__GPIO1_29                     IOMUX_PAD(0x5E0, 0x264, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1             (_MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3                IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOW__PATA_DIOW           (_MX53_PAD_PATA_DIOW__PATA_DIOW | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TXD1__MLB_MLBCLK                   IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOW__GPIO6_17            (_MX53_PAD_PATA_DIOW__GPIO6_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK          IOMUX_PAD(0x5E0, 0x264, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX               (_MX53_PAD_PATA_DIOW__UART1_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_FEC_TXD0__FEC_TDATA_0                  IOMUX_PAD(0x5E4, 0x268, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2           (_MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TXD0__GPIO1_30                     IOMUX_PAD(0x5E4, 0x268, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMACK__PATA_DMACK         (_MX53_PAD_PATA_DMACK__PATA_DMACK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1                IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMACK__GPIO6_18           (_MX53_PAD_PATA_DMACK__GPIO6_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0            IOMUX_PAD(0x5E4, 0x268, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX              (_MX53_PAD_PATA_DMACK__UART1_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_FEC_MDC__FEC_MDC                       IOMUX_PAD(0x5E8, 0x26C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3          (_MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDC__GPIO1_31                      IOMUX_PAD(0x5E8, 0x26C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMARQ__PATA_DMARQ         (_MX53_PAD_PATA_DMARQ__PATA_DMARQ | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0                 IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMARQ__GPIO7_0            (_MX53_PAD_PATA_DMARQ__GPIO7_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDC__MLB_MLBDAT                    IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX              (_MX53_PAD_PATA_DMARQ__UART2_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG        IOMUX_PAD(0x5E8, 0x26C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0              (_MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1             IOMUX_PAD(0x5E8, 0x26C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4          (_MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DIOW__PATA_DIOW                   IOMUX_PAD(0x5F0, 0x270, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN         (_MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DIOW__GPIO6_17                    IOMUX_PAD(0x5F0, 0x270, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1                (_MX53_PAD_PATA_BUFFER_EN__GPIO7_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX               IOMUX_PAD(0x5F0, 0x270, 3, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX          (_MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2           IOMUX_PAD(0x5F0, 0x270, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1          (_MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DMACK__PATA_DMACK                 IOMUX_PAD(0x5F4, 0x274, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5              (_MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DMACK__GPIO6_18                   IOMUX_PAD(0x5F4, 0x274, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__PATA_INTRQ         (_MX53_PAD_PATA_INTRQ__PATA_INTRQ | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX              IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__GPIO7_2            (_MX53_PAD_PATA_INTRQ__GPIO7_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3          IOMUX_PAD(0x5F4, 0x274, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__UART2_CTS          (_MX53_PAD_PATA_INTRQ__UART2_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_PATA_DMARQ__PATA_DMARQ                 IOMUX_PAD(0x5F8, 0x278, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN         (_MX53_PAD_PATA_INTRQ__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DMARQ__GPIO7_0                    IOMUX_PAD(0x5F8, 0x278, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2              (_MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX              IOMUX_PAD(0x5F8, 0x278, 3, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6          (_MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0              IOMUX_PAD(0x5F8, 0x278, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOR__PATA_DIOR           (_MX53_PAD_PATA_DIOR__PATA_DIOR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4          IOMUX_PAD(0x5F8, 0x278, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOR__GPIO7_3             (_MX53_PAD_PATA_DIOR__GPIO7_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN         IOMUX_PAD(0x5FC, 0x27C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOR__UART2_RTS           (_MX53_PAD_PATA_DIOR__UART2_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1                IOMUX_PAD(0x5FC, 0x27C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOR__CAN1_RXCAN          (_MX53_PAD_PATA_DIOR__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX          IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7           (_MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1          IOMUX_PAD(0x5FC, 0x27C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B                (_MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5      IOMUX_PAD(0x5FC, 0x27C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__GPIO7_4          (_MX53_PAD_PATA_RESET_B__GPIO7_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_INTRQ__PATA_INTRQ                 IOMUX_PAD(0x600, 0x280, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD               (_MX53_PAD_PATA_RESET_B__ESDHC3_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_INTRQ__GPIO7_2                    IOMUX_PAD(0x600, 0x280, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__UART1_CTS                (_MX53_PAD_PATA_RESET_B__UART1_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_PATA_INTRQ__UART2_CTS                  IOMUX_PAD(0x600, 0x280, 3, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN               (_MX53_PAD_PATA_RESET_B__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN                 IOMUX_PAD(0x600, 0x280, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0                (_MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2              IOMUX_PAD(0x600, 0x280, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__PATA_IORDY         (_MX53_PAD_PATA_IORDY__PATA_IORDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6          IOMUX_PAD(0x600, 0x280, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__GPIO7_5            (_MX53_PAD_PATA_IORDY__GPIO7_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DIOR__PATA_DIOR                   IOMUX_PAD(0x604, 0x284, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__ESDHC3_CLK         (_MX53_PAD_PATA_IORDY__ESDHC3_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DIOR__GPIO7_3                     IOMUX_PAD(0x604, 0x284, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__UART1_RTS          (_MX53_PAD_PATA_IORDY__UART1_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_PATA_DIOR__UART2_RTS                   IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__CAN2_RXCAN         (_MX53_PAD_PATA_IORDY__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DIOR__CAN1_RXCAN                  IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, NO_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1          (_MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7           IOMUX_PAD(0x604, 0x284, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_0__PATA_DA_0           (_MX53_PAD_PATA_DA_0__PATA_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B        IOMUX_PAD(0x608, 0x288, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_0__GPIO7_6             (_MX53_PAD_PATA_DA_0__GPIO7_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_RESET_B__GPIO7_4                  IOMUX_PAD(0x608, 0x288, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_0__ESDHC3_RST          (_MX53_PAD_PATA_DA_0__ESDHC3_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD               IOMUX_PAD(0x608, 0x288, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DA_0__OWIRE_LINE          (_MX53_PAD_PATA_DA_0__OWIRE_LINE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_RESET_B__UART1_CTS                IOMUX_PAD(0x608, 0x288, 3, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2           (_MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN               IOMUX_PAD(0x608, 0x288, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_1__PATA_DA_1           (_MX53_PAD_PATA_DA_1__PATA_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0        IOMUX_PAD(0x608, 0x288, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_1__GPIO7_7             (_MX53_PAD_PATA_DA_1__GPIO7_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_IORDY__PATA_IORDY                 IOMUX_PAD(0x60C, 0x28C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_1__ESDHC4_CMD          (_MX53_PAD_PATA_DA_1__ESDHC4_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_IORDY__GPIO7_5                    IOMUX_PAD(0x60C, 0x28C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_1__UART3_CTS           (_MX53_PAD_PATA_DA_1__UART3_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_PATA_IORDY__ESDHC3_CLK                 IOMUX_PAD(0x60C, 0x28C, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3           (_MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_IORDY__UART1_RTS                  IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DA_2__PATA_DA_2           (_MX53_PAD_PATA_DA_2__PATA_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_IORDY__CAN2_RXCAN                 IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_2__GPIO7_8             (_MX53_PAD_PATA_DA_2__GPIO7_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1          IOMUX_PAD(0x60C, 0x28C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_2__ESDHC4_CLK          (_MX53_PAD_PATA_DA_2__ESDHC4_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DA_0__PATA_DA_0                   IOMUX_PAD(0x610, 0x290, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_2__UART3_RTS           (_MX53_PAD_PATA_DA_2__UART3_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_PATA_DA_0__GPIO7_6                     IOMUX_PAD(0x610, 0x290, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4           (_MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DA_0__ESDHC3_RST                  IOMUX_PAD(0x610, 0x290, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_0__PATA_CS_0           (_MX53_PAD_PATA_CS_0__PATA_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DA_0__OWIRE_LINE                  IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_0__GPIO7_9             (_MX53_PAD_PATA_CS_0__GPIO7_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2           IOMUX_PAD(0x610, 0x290, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX               (_MX53_PAD_PATA_CS_0__UART3_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_PATA_DA_1__PATA_DA_1                   IOMUX_PAD(0x614, 0x294, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5           (_MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DA_1__GPIO7_7                     IOMUX_PAD(0x614, 0x294, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_1__PATA_CS_1           (_MX53_PAD_PATA_CS_1__PATA_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DA_1__ESDHC4_CMD                  IOMUX_PAD(0x614, 0x294, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_CS_1__GPIO7_10            (_MX53_PAD_PATA_CS_1__GPIO7_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DA_1__UART3_CTS                   IOMUX_PAD(0x614, 0x294, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX               (_MX53_PAD_PATA_CS_1__UART3_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3           IOMUX_PAD(0x614, 0x294, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6           (_MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DA_2__PATA_DA_2                   IOMUX_PAD(0x618, 0x298, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__PATA_DATA_0                (_MX53_PAD_PATA_DATA0__PATA_DATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DA_2__GPIO7_8                     IOMUX_PAD(0x618, 0x298, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__GPIO2_0            (_MX53_PAD_PATA_DATA0__GPIO2_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DA_2__ESDHC4_CLK                  IOMUX_PAD(0x618, 0x298, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0              (_MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DA_2__UART3_RTS                   IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4                (_MX53_PAD_PATA_DATA0__ESDHC3_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4           IOMUX_PAD(0x618, 0x298, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0              (_MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_CS_0__PATA_CS_0                   IOMUX_PAD(0x61C, 0x29C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0             (_MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_CS_0__GPIO7_9                     IOMUX_PAD(0x61C, 0x29C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7          (_MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX               IOMUX_PAD(0x61C, 0x29C, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__PATA_DATA_1                (_MX53_PAD_PATA_DATA1__PATA_DATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5           IOMUX_PAD(0x61C, 0x29C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__GPIO2_1            (_MX53_PAD_PATA_DATA1__GPIO2_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_CS_1__PATA_CS_1                   IOMUX_PAD(0x620, 0x2A0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1              (_MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_CS_1__GPIO7_10                    IOMUX_PAD(0x620, 0x2A0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5                (_MX53_PAD_PATA_DATA1__ESDHC3_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX               IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1              (_MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6           IOMUX_PAD(0x620, 0x2A0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1             (_MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA0__PATA_DATA_0                IOMUX_PAD(0x628, 0x2A4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__PATA_DATA_2                (_MX53_PAD_PATA_DATA2__PATA_DATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA0__GPIO2_0                    IOMUX_PAD(0x628, 0x2A4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__GPIO2_2            (_MX53_PAD_PATA_DATA2__GPIO2_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0              IOMUX_PAD(0x628, 0x2A4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2              (_MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4                IOMUX_PAD(0x628, 0x2A4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6                (_MX53_PAD_PATA_DATA2__ESDHC3_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0      IOMUX_PAD(0x628, 0x2A4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2              (_MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0             IOMUX_PAD(0x628, 0x2A4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2             (_MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7          IOMUX_PAD(0x628, 0x2A4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__PATA_DATA_3                (_MX53_PAD_PATA_DATA3__PATA_DATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA1__PATA_DATA_1                IOMUX_PAD(0x62C, 0x2A8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__GPIO2_3            (_MX53_PAD_PATA_DATA3__GPIO2_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA1__GPIO2_1                    IOMUX_PAD(0x62C, 0x2A8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3              (_MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1              IOMUX_PAD(0x62C, 0x2A8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7                (_MX53_PAD_PATA_DATA3__ESDHC3_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5                IOMUX_PAD(0x62C, 0x2A8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3              (_MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1      IOMUX_PAD(0x62C, 0x2A8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3             (_MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1             IOMUX_PAD(0x62C, 0x2A8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__PATA_DATA_4                (_MX53_PAD_PATA_DATA4__PATA_DATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA2__PATA_DATA_2                IOMUX_PAD(0x630, 0x2AC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__GPIO2_4            (_MX53_PAD_PATA_DATA4__GPIO2_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA2__GPIO2_2                    IOMUX_PAD(0x630, 0x2AC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4              (_MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2              IOMUX_PAD(0x630, 0x2AC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4                (_MX53_PAD_PATA_DATA4__ESDHC4_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6                IOMUX_PAD(0x630, 0x2AC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4              (_MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2      IOMUX_PAD(0x630, 0x2AC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4             (_MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2             IOMUX_PAD(0x630, 0x2AC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__PATA_DATA_5                (_MX53_PAD_PATA_DATA5__PATA_DATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA3__PATA_DATA_3                IOMUX_PAD(0x634, 0x2B0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__GPIO2_5            (_MX53_PAD_PATA_DATA5__GPIO2_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA3__GPIO2_3                    IOMUX_PAD(0x634, 0x2B0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5              (_MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3              IOMUX_PAD(0x634, 0x2B0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5                (_MX53_PAD_PATA_DATA5__ESDHC4_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7                IOMUX_PAD(0x634, 0x2B0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5              (_MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3      IOMUX_PAD(0x634, 0x2B0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5             (_MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3             IOMUX_PAD(0x634, 0x2B0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__PATA_DATA_6                (_MX53_PAD_PATA_DATA6__PATA_DATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA4__PATA_DATA_4                IOMUX_PAD(0x638, 0x2B4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__GPIO2_6            (_MX53_PAD_PATA_DATA6__GPIO2_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA4__GPIO2_4                    IOMUX_PAD(0x638, 0x2B4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6              (_MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4              IOMUX_PAD(0x638, 0x2B4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6                (_MX53_PAD_PATA_DATA6__ESDHC4_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4                IOMUX_PAD(0x638, 0x2B4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6              (_MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4      IOMUX_PAD(0x638, 0x2B4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6             (_MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4             IOMUX_PAD(0x638, 0x2B4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__PATA_DATA_7                (_MX53_PAD_PATA_DATA7__PATA_DATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA5__PATA_DATA_5                IOMUX_PAD(0x63C, 0x2B8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__GPIO2_7            (_MX53_PAD_PATA_DATA7__GPIO2_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA5__GPIO2_5                    IOMUX_PAD(0x63C, 0x2B8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7              (_MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5              IOMUX_PAD(0x63C, 0x2B8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7                (_MX53_PAD_PATA_DATA7__ESDHC4_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5                IOMUX_PAD(0x63C, 0x2B8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7              (_MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5      IOMUX_PAD(0x63C, 0x2B8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7             (_MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5             IOMUX_PAD(0x63C, 0x2B8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__PATA_DATA_8                (_MX53_PAD_PATA_DATA8__PATA_DATA_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA6__PATA_DATA_6                IOMUX_PAD(0x640, 0x2BC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__GPIO2_8            (_MX53_PAD_PATA_DATA8__GPIO2_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA6__GPIO2_6                    IOMUX_PAD(0x640, 0x2BC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4                (_MX53_PAD_PATA_DATA8__ESDHC1_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6              IOMUX_PAD(0x640, 0x2BC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8              (_MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6                IOMUX_PAD(0x640, 0x2BC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0                (_MX53_PAD_PATA_DATA8__ESDHC3_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6      IOMUX_PAD(0x640, 0x2BC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8              (_MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6             IOMUX_PAD(0x640, 0x2BC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8             (_MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA7__PATA_DATA_7                IOMUX_PAD(0x644, 0x2C0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__PATA_DATA_9                (_MX53_PAD_PATA_DATA9__PATA_DATA_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA7__GPIO2_7                    IOMUX_PAD(0x644, 0x2C0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__GPIO2_9            (_MX53_PAD_PATA_DATA9__GPIO2_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7              IOMUX_PAD(0x644, 0x2C0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5                (_MX53_PAD_PATA_DATA9__ESDHC1_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7                IOMUX_PAD(0x644, 0x2C0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9              (_MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7      IOMUX_PAD(0x644, 0x2C0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1                (_MX53_PAD_PATA_DATA9__ESDHC3_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7             IOMUX_PAD(0x644, 0x2C0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9              (_MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA8__PATA_DATA_8                IOMUX_PAD(0x648, 0x2C4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9             (_MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA8__GPIO2_8                    IOMUX_PAD(0x648, 0x2C4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__PATA_DATA_10              (_MX53_PAD_PATA_DATA10__PATA_DATA_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4                IOMUX_PAD(0x648, 0x2C4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__GPIO2_10          (_MX53_PAD_PATA_DATA10__GPIO2_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8              IOMUX_PAD(0x648, 0x2C4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6               (_MX53_PAD_PATA_DATA10__ESDHC1_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0                IOMUX_PAD(0x648, 0x2C4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10            (_MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8      IOMUX_PAD(0x648, 0x2C4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2               (_MX53_PAD_PATA_DATA10__ESDHC3_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8             IOMUX_PAD(0x648, 0x2C4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10            (_MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA9__PATA_DATA_9                IOMUX_PAD(0x64C, 0x2C8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10           (_MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA9__GPIO2_9                    IOMUX_PAD(0x64C, 0x2C8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__PATA_DATA_11              (_MX53_PAD_PATA_DATA11__PATA_DATA_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5                IOMUX_PAD(0x64C, 0x2C8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__GPIO2_11          (_MX53_PAD_PATA_DATA11__GPIO2_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9              IOMUX_PAD(0x64C, 0x2C8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7               (_MX53_PAD_PATA_DATA11__ESDHC1_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1                IOMUX_PAD(0x64C, 0x2C8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11            (_MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9      IOMUX_PAD(0x64C, 0x2C8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3               (_MX53_PAD_PATA_DATA11__ESDHC3_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9             IOMUX_PAD(0x64C, 0x2C8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11            (_MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA10__PATA_DATA_10              IOMUX_PAD(0x650, 0x2CC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11           (_MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA10__GPIO2_10                  IOMUX_PAD(0x650, 0x2CC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__PATA_DATA_12              (_MX53_PAD_PATA_DATA12__PATA_DATA_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6               IOMUX_PAD(0x650, 0x2CC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__GPIO2_12          (_MX53_PAD_PATA_DATA12__GPIO2_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10            IOMUX_PAD(0x650, 0x2CC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4               (_MX53_PAD_PATA_DATA12__ESDHC2_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2               IOMUX_PAD(0x650, 0x2CC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12            (_MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10    IOMUX_PAD(0x650, 0x2CC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0               (_MX53_PAD_PATA_DATA12__ESDHC4_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10           IOMUX_PAD(0x650, 0x2CC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12            (_MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA11__PATA_DATA_11              IOMUX_PAD(0x654, 0x2D0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12           (_MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA11__GPIO2_11                  IOMUX_PAD(0x654, 0x2D0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__PATA_DATA_13              (_MX53_PAD_PATA_DATA13__PATA_DATA_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7               IOMUX_PAD(0x654, 0x2D0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__GPIO2_13          (_MX53_PAD_PATA_DATA13__GPIO2_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11            IOMUX_PAD(0x654, 0x2D0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5               (_MX53_PAD_PATA_DATA13__ESDHC2_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3               IOMUX_PAD(0x654, 0x2D0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13            (_MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11    IOMUX_PAD(0x654, 0x2D0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1               (_MX53_PAD_PATA_DATA13__ESDHC4_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11           IOMUX_PAD(0x654, 0x2D0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13            (_MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA12__PATA_DATA_12              IOMUX_PAD(0x658, 0x2D4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13           (_MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA12__GPIO2_12                  IOMUX_PAD(0x658, 0x2D4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__PATA_DATA_14              (_MX53_PAD_PATA_DATA14__PATA_DATA_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4               IOMUX_PAD(0x658, 0x2D4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__GPIO2_14          (_MX53_PAD_PATA_DATA14__GPIO2_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12            IOMUX_PAD(0x658, 0x2D4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6               (_MX53_PAD_PATA_DATA14__ESDHC2_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0               IOMUX_PAD(0x658, 0x2D4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14            (_MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12    IOMUX_PAD(0x658, 0x2D4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2               (_MX53_PAD_PATA_DATA14__ESDHC4_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12           IOMUX_PAD(0x658, 0x2D4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14            (_MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA13__PATA_DATA_13              IOMUX_PAD(0x65C, 0x2D8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14           (_MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA13__GPIO2_13                  IOMUX_PAD(0x65C, 0x2D8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__PATA_DATA_15              (_MX53_PAD_PATA_DATA15__PATA_DATA_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5               IOMUX_PAD(0x65C, 0x2D8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__GPIO2_15          (_MX53_PAD_PATA_DATA15__GPIO2_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13            IOMUX_PAD(0x65C, 0x2D8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7               (_MX53_PAD_PATA_DATA15__ESDHC2_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1               IOMUX_PAD(0x65C, 0x2D8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15            (_MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13    IOMUX_PAD(0x65C, 0x2D8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3               (_MX53_PAD_PATA_DATA15__ESDHC4_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13           IOMUX_PAD(0x65C, 0x2D8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15            (_MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA14__PATA_DATA_14              IOMUX_PAD(0x660, 0x2DC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15           (_MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA14__GPIO2_14                  IOMUX_PAD(0x660, 0x2DC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0         (_MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6               IOMUX_PAD(0x660, 0x2DC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_DATA0__GPIO1_16            (_MX53_PAD_SD1_DATA0__GPIO1_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14            IOMUX_PAD(0x660, 0x2DC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA0__GPT_CAPIN1          (_MX53_PAD_SD1_DATA0__GPT_CAPIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2               IOMUX_PAD(0x660, 0x2DC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_DATA0__CSPI_MISO           (_MX53_PAD_SD1_DATA0__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14    IOMUX_PAD(0x660, 0x2DC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP                (_MX53_PAD_SD1_DATA0__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14           IOMUX_PAD(0x660, 0x2DC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1         (_MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA15__PATA_DATA_15              IOMUX_PAD(0x664, 0x2E0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA1__GPIO1_17            (_MX53_PAD_SD1_DATA1__GPIO1_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA15__GPIO2_15                  IOMUX_PAD(0x664, 0x2E0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA1__GPT_CAPIN2          (_MX53_PAD_SD1_DATA1__GPT_CAPIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7               IOMUX_PAD(0x664, 0x2E0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_DATA1__CSPI_SS0            (_MX53_PAD_SD1_DATA1__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15            IOMUX_PAD(0x664, 0x2E0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP                (_MX53_PAD_SD1_DATA1__CCM_PLL4_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3               IOMUX_PAD(0x664, 0x2E0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_CMD__ESDHC1_CMD            (_MX53_PAD_SD1_CMD__ESDHC1_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15    IOMUX_PAD(0x664, 0x2E0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CMD__GPIO1_18              (_MX53_PAD_SD1_CMD__GPIO1_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15           IOMUX_PAD(0x664, 0x2E0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CMD__GPT_CMPOUT1           (_MX53_PAD_SD1_CMD__GPT_CMPOUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0                 IOMUX_PAD(0x66C, 0x2E4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_CMD__CSPI_MOSI             (_MX53_PAD_SD1_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA0__GPIO1_16                    IOMUX_PAD(0x66C, 0x2E4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP          (_MX53_PAD_SD1_CMD__CCM_PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA0__GPT_CAPIN1                  IOMUX_PAD(0x66C, 0x2E4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2         (_MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD1_DATA0__CSPI_MISO                   IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__GPIO1_19            (_MX53_PAD_SD1_DATA2__GPIO1_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP                IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2         (_MX53_PAD_SD1_DATA2__GPT_CMPOUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1                 IOMUX_PAD(0x670, 0x2E8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__PWM2_PWMO           (_MX53_PAD_SD1_DATA2__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA1__GPIO1_17                    IOMUX_PAD(0x670, 0x2E8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B                (_MX53_PAD_SD1_DATA2__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA1__GPT_CAPIN2                  IOMUX_PAD(0x670, 0x2E8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__CSPI_SS1            (_MX53_PAD_SD1_DATA2__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA1__CSPI_SS0                    IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB                (_MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP                IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP                (_MX53_PAD_SD1_DATA2__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_CMD__ESDHC1_CMD                    IOMUX_PAD(0x674, 0x2EC, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__ESDHC1_CLK            (_MX53_PAD_SD1_CLK__ESDHC1_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD1_CMD__GPIO1_18                      IOMUX_PAD(0x674, 0x2EC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__GPIO1_20              (_MX53_PAD_SD1_CLK__GPIO1_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_CMD__GPT_CMPOUT1                   IOMUX_PAD(0x674, 0x2EC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT                (_MX53_PAD_SD1_CLK__OSC32k_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_CMD__CSPI_MOSI                     IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__GPT_CLKIN             (_MX53_PAD_SD1_CLK__GPT_CLKIN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP                  IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__CSPI_SCLK             (_MX53_PAD_SD1_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2                 IOMUX_PAD(0x678, 0x2F0, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0                (_MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA2__GPIO1_19                    IOMUX_PAD(0x678, 0x2F0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3         (_MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2                 IOMUX_PAD(0x678, 0x2F0, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__GPIO1_21            (_MX53_PAD_SD1_DATA3__GPIO1_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA2__PWM2_PWMO                   IOMUX_PAD(0x678, 0x2F0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3         (_MX53_PAD_SD1_DATA3__GPT_CMPOUT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B                IOMUX_PAD(0x678, 0x2F0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__PWM1_PWMO           (_MX53_PAD_SD1_DATA3__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA2__CSPI_SS1                    IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B                (_MX53_PAD_SD1_DATA3__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB        IOMUX_PAD(0x678, 0x2F0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__CSPI_SS2            (_MX53_PAD_SD1_DATA3__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP                IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB                (_MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_CLK__ESDHC1_CLK                    IOMUX_PAD(0x67C, 0x2F4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1              (_MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_CLK__GPIO1_20                      IOMUX_PAD(0x67C, 0x2F4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__ESDHC2_CLK            (_MX53_PAD_SD2_CLK__ESDHC2_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT                IOMUX_PAD(0x67C, 0x2F4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__GPIO1_10              (_MX53_PAD_SD2_CLK__GPIO1_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_CLK__GPT_CLKIN                     IOMUX_PAD(0x67C, 0x2F4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__KPP_COL_5             (_MX53_PAD_SD2_CLK__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_CLK__CSPI_SCLK                     IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS              (_MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0                IOMUX_PAD(0x67C, 0x2F4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__CSPI_SCLK             (_MX53_PAD_SD2_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3                 IOMUX_PAD(0x680, 0x2F8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__SCC_RANDOM_V          (_MX53_PAD_SD2_CLK__SCC_RANDOM_V | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA3__GPIO1_21                    IOMUX_PAD(0x680, 0x2F8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__ESDHC2_CMD            (_MX53_PAD_SD2_CMD__ESDHC2_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3                 IOMUX_PAD(0x680, 0x2F8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__GPIO1_11              (_MX53_PAD_SD2_CMD__GPIO1_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA3__PWM1_PWMO                   IOMUX_PAD(0x680, 0x2F8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__KPP_ROW_5             (_MX53_PAD_SD2_CMD__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B                IOMUX_PAD(0x680, 0x2F8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC               (_MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA3__CSPI_SS2                    IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__CSPI_MOSI             (_MX53_PAD_SD2_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB        IOMUX_PAD(0x680, 0x2F8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__SCC_RANDOM            (_MX53_PAD_SD2_CMD__SCC_RANDOM | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1              IOMUX_PAD(0x680, 0x2F8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3         (_MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD2_CLK__ESDHC2_CLK                    IOMUX_PAD(0x688, 0x2FC, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__GPIO1_12            (_MX53_PAD_SD2_DATA3__GPIO1_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_CLK__GPIO1_10                      IOMUX_PAD(0x688, 0x2FC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__KPP_COL_6           (_MX53_PAD_SD2_DATA3__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_CLK__KPP_COL_5                     IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC             (_MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS              IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__CSPI_SS2            (_MX53_PAD_SD2_DATA3__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_CLK__CSPI_SCLK                     IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__SJC_DONE            (_MX53_PAD_SD2_DATA3__SJC_DONE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_CLK__SCC_RANDOM_V                  IOMUX_PAD(0x688, 0x2FC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2         (_MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD2_CMD__ESDHC2_CMD                    IOMUX_PAD(0x68C, 0x300, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__GPIO1_13            (_MX53_PAD_SD2_DATA2__GPIO1_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_CMD__GPIO1_11                      IOMUX_PAD(0x68C, 0x300, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__KPP_ROW_6           (_MX53_PAD_SD2_DATA2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_CMD__KPP_ROW_5                     IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD             (_MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC               IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__CSPI_SS1            (_MX53_PAD_SD2_DATA2__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_CMD__CSPI_MOSI                     IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__SJC_FAIL            (_MX53_PAD_SD2_DATA2__SJC_FAIL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_CMD__SCC_RANDOM                    IOMUX_PAD(0x68C, 0x300, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1         (_MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3                 IOMUX_PAD(0x690, 0x304, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__GPIO1_14            (_MX53_PAD_SD2_DATA1__GPIO1_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA3__GPIO1_12                    IOMUX_PAD(0x690, 0x304, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__KPP_COL_7           (_MX53_PAD_SD2_DATA1__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA3__KPP_COL_6                   IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS            (_MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC             IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__CSPI_SS0            (_MX53_PAD_SD2_DATA1__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA3__CSPI_SS2                    IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO                (_MX53_PAD_SD2_DATA1__RTIC_SEC_VIO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA3__SJC_DONE                    IOMUX_PAD(0x690, 0x304, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0         (_MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2                 IOMUX_PAD(0x694, 0x308, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__GPIO1_15            (_MX53_PAD_SD2_DATA0__GPIO1_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA2__GPIO1_13                    IOMUX_PAD(0x694, 0x308, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__KPP_ROW_7           (_MX53_PAD_SD2_DATA0__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA2__KPP_ROW_6                   IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD             (_MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD             IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__CSPI_MISO           (_MX53_PAD_SD2_DATA0__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA2__CSPI_SS1                    IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT               (_MX53_PAD_SD2_DATA0__RTIC_DONE_INT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA2__SJC_FAIL                    IOMUX_PAD(0x694, 0x308, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__CCM_CLKO               (_MX53_PAD_GPIO_0__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1                 IOMUX_PAD(0x698, 0x30C, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_GPIO_0__GPIO1_0                (_MX53_PAD_GPIO_0__GPIO1_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA1__GPIO1_14                    IOMUX_PAD(0x698, 0x30C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__KPP_COL_5              (_MX53_PAD_GPIO_0__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA1__KPP_COL_7                   IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK               (_MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS            IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__EPIT1_EPITO            (_MX53_PAD_GPIO_0__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA1__CSPI_SS0                    IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB         (_MX53_PAD_GPIO_0__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO                IOMUX_PAD(0x698, 0x30C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR               (_MX53_PAD_GPIO_0__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0                 IOMUX_PAD(0x69C, 0x310, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_GPIO_0__CSU_TD         (_MX53_PAD_GPIO_0__CSU_TD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA0__GPIO1_15                    IOMUX_PAD(0x69C, 0x310, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__ESAI1_SCKR             (_MX53_PAD_GPIO_1__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA0__KPP_ROW_7                   IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__GPIO1_1                (_MX53_PAD_GPIO_1__GPIO1_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD             IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__KPP_ROW_5              (_MX53_PAD_GPIO_1__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA0__CSPI_MISO                   IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK               (_MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT               IOMUX_PAD(0x69C, 0x310, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__PWM2_PWMO              (_MX53_PAD_GPIO_1__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_0__CCM_CLKO                       IOMUX_PAD(0x6A4, 0x314, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__WDOG2_WDOG_B           (_MX53_PAD_GPIO_1__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_0__GPIO1_0                        IOMUX_PAD(0x6A4, 0x314, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__ESDHC1_CD              (_MX53_PAD_GPIO_1__ESDHC1_CD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_0__KPP_COL_5                      IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__SRC_TESTER_ACK         (_MX53_PAD_GPIO_1__SRC_TESTER_ACK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK               IOMUX_PAD(0x6A4, 0x314, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__ESAI1_FSR              (_MX53_PAD_GPIO_9__ESAI1_FSR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_0__EPIT1_EPITO                    IOMUX_PAD(0x6A4, 0x314, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__GPIO1_9                (_MX53_PAD_GPIO_9__GPIO1_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB                 IOMUX_PAD(0x6A4, 0x314, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__KPP_COL_6              (_MX53_PAD_GPIO_9__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR               IOMUX_PAD(0x6A4, 0x314, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__CCM_REF_EN_B           (_MX53_PAD_GPIO_9__CCM_REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_0__CSU_TD                         IOMUX_PAD(0x6A4, 0x314, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__PWM1_PWMO              (_MX53_PAD_GPIO_9__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_1__ESAI1_SCKR                     IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__WDOG1_WDOG_B           (_MX53_PAD_GPIO_9__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_1__GPIO1_1                        IOMUX_PAD(0x6A8, 0x318, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__ESDHC1_WP              (_MX53_PAD_GPIO_9__ESDHC1_WP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_1__KPP_ROW_5                      IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__SCC_FAIL_STATE         (_MX53_PAD_GPIO_9__SCC_FAIL_STATE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK               IOMUX_PAD(0x6A8, 0x318, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__ESAI1_HCKR             (_MX53_PAD_GPIO_3__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_1__PWM2_PWMO                      IOMUX_PAD(0x6A8, 0x318, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__GPIO1_3                (_MX53_PAD_GPIO_3__GPIO1_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_1__WDOG2_WDOG_B                   IOMUX_PAD(0x6A8, 0x318, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__I2C3_SCL               (_MX53_PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C))
+#define MX53_PAD_GPIO_1__ESDHC1_CD                      IOMUX_PAD(0x6A8, 0x318, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN         (_MX53_PAD_GPIO_3__DPLLIP1_TOG_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_1__SRC_TESTER_ACK                 IOMUX_PAD(0x6A8, 0x318, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__CCM_CLKO2              (_MX53_PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_9__ESAI1_FSR                      IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0             (_MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_9__GPIO1_9                        IOMUX_PAD(0x6AC, 0x31C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC                (_MX53_PAD_GPIO_3__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_9__KPP_COL_6                      IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__MLB_MLBCLK             (_MX53_PAD_GPIO_3__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_9__CCM_REF_EN_B                   IOMUX_PAD(0x6AC, 0x31C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__ESAI1_SCKT             (_MX53_PAD_GPIO_6__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_9__PWM1_PWMO                      IOMUX_PAD(0x6AC, 0x31C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__GPIO1_6                (_MX53_PAD_GPIO_6__GPIO1_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_9__WDOG1_WDOG_B                   IOMUX_PAD(0x6AC, 0x31C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__I2C3_SDA               (_MX53_PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C))
+#define MX53_PAD_GPIO_9__ESDHC1_WP                      IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0          (_MX53_PAD_GPIO_6__CCM_CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_9__SCC_FAIL_STATE                 IOMUX_PAD(0x6AC, 0x31C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB                (_MX53_PAD_GPIO_6__CSU_CSU_INT_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_3__ESAI1_HCKR                     IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1             (_MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_3__GPIO1_3                        IOMUX_PAD(0x6B0, 0x320, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__ESDHC2_LCTL            (_MX53_PAD_GPIO_6__ESDHC2_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_3__I2C3_SCL                       IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__MLB_MLBSIG             (_MX53_PAD_GPIO_6__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN                 IOMUX_PAD(0x6B0, 0x320, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__ESAI1_FST              (_MX53_PAD_GPIO_2__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_3__CCM_CLKO2                      IOMUX_PAD(0x6B0, 0x320, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__GPIO1_2                (_MX53_PAD_GPIO_2__GPIO1_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0     IOMUX_PAD(0x6B0, 0x320, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__KPP_ROW_6              (_MX53_PAD_GPIO_2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC                IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1          (_MX53_PAD_GPIO_2__CCM_CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_3__MLB_MLBCLK                     IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0            (_MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_6__ESAI1_SCKT                     IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2             (_MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_6__GPIO1_6                        IOMUX_PAD(0x6B4, 0x324, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__ESDHC2_WP              (_MX53_PAD_GPIO_2__ESDHC2_WP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_6__I2C3_SDA                       IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__MLB_MLBDAT             (_MX53_PAD_GPIO_2__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0                  IOMUX_PAD(0x6B4, 0x324, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__ESAI1_HCKT             (_MX53_PAD_GPIO_4__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB                IOMUX_PAD(0x6B4, 0x324, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__GPIO1_4                (_MX53_PAD_GPIO_4__GPIO1_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1     IOMUX_PAD(0x6B4, 0x324, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__KPP_COL_7              (_MX53_PAD_GPIO_4__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_6__ESDHC2_LCTL                    IOMUX_PAD(0x6B4, 0x324, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2          (_MX53_PAD_GPIO_4__CCM_CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_6__MLB_MLBSIG                     IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1            (_MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_2__ESAI1_FST                      IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3             (_MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_2__GPIO1_2                        IOMUX_PAD(0x6B8, 0x328, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__ESDHC2_CD              (_MX53_PAD_GPIO_4__ESDHC2_CD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_2__KPP_ROW_6                      IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__SCC_SEC_STATE          (_MX53_PAD_GPIO_4__SCC_SEC_STATE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1                  IOMUX_PAD(0x6B8, 0x328, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3          (_MX53_PAD_GPIO_5__ESAI1_TX2_RX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0            IOMUX_PAD(0x6B8, 0x328, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__GPIO1_5                (_MX53_PAD_GPIO_5__GPIO1_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2     IOMUX_PAD(0x6B8, 0x328, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__KPP_ROW_7              (_MX53_PAD_GPIO_5__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_2__ESDHC2_WP                      IOMUX_PAD(0x6B8, 0x328, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__CCM_CLKO               (_MX53_PAD_GPIO_5__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_2__MLB_MLBDAT                     IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2            (_MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_4__ESAI1_HCKT                     IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4             (_MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_4__GPIO1_4                        IOMUX_PAD(0x6BC, 0x32C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__I2C3_SCL               (_MX53_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C))
+#define MX53_PAD_GPIO_4__KPP_COL_7                      IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__CCM_PLL1_BYP           (_MX53_PAD_GPIO_5__CCM_PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2                  IOMUX_PAD(0x6BC, 0x32C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1          (_MX53_PAD_GPIO_7__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1            IOMUX_PAD(0x6BC, 0x32C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__GPIO1_7                (_MX53_PAD_GPIO_7__GPIO1_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3     IOMUX_PAD(0x6BC, 0x32C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__EPIT1_EPITO            (_MX53_PAD_GPIO_7__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_4__ESDHC2_CD                      IOMUX_PAD(0x6BC, 0x32C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__CAN1_TXCAN             (_MX53_PAD_GPIO_7__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_4__SCC_SEC_STATE                  IOMUX_PAD(0x6BC, 0x32C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__UART2_TXD_MUX          (_MX53_PAD_GPIO_7__UART2_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3                  IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__FIRI_RXD               (_MX53_PAD_GPIO_7__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_5__GPIO1_5                        IOMUX_PAD(0x6C0, 0x330, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__SPDIF_PLOCK            (_MX53_PAD_GPIO_7__SPDIF_PLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_5__KPP_ROW_7                      IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__CCM_PLL2_BYP           (_MX53_PAD_GPIO_7__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_5__CCM_CLKO                       IOMUX_PAD(0x6C0, 0x330, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0          (_MX53_PAD_GPIO_8__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2            IOMUX_PAD(0x6C0, 0x330, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__GPIO1_8                (_MX53_PAD_GPIO_8__GPIO1_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4     IOMUX_PAD(0x6C0, 0x330, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__EPIT2_EPITO            (_MX53_PAD_GPIO_8__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_5__I2C3_SCL                       IOMUX_PAD(0x6C0, 0x330, 6 | IOMUX_CONFIG_SION, 0x824, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__CAN1_RXCAN             (_MX53_PAD_GPIO_8__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_5__CCM_PLL1_BYP                   IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__UART2_RXD_MUX          (_MX53_PAD_GPIO_8__UART2_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1                  IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__FIRI_TXD               (_MX53_PAD_GPIO_8__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_7__GPIO1_7                        IOMUX_PAD(0x6C4, 0x334, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__SPDIF_SRCLK            (_MX53_PAD_GPIO_8__SPDIF_SRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_7__EPIT1_EPITO                    IOMUX_PAD(0x6C4, 0x334, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__CCM_PLL3_BYP           (_MX53_PAD_GPIO_8__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_7__CAN1_TXCAN                     IOMUX_PAD(0x6C4, 0x334, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2         (_MX53_PAD_GPIO_16__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_7__UART2_TXD_MUX                  IOMUX_PAD(0x6C4, 0x334, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_GPIO_16__GPIO7_11              (_MX53_PAD_GPIO_16__GPIO7_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_7__FIRI_RXD                       IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT              (_MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_7__SPDIF_PLOCK                    IOMUX_PAD(0x6C4, 0x334, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1          (_MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_7__CCM_PLL2_BYP                   IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__SPDIF_IN1             (_MX53_PAD_GPIO_16__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0                  IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__I2C3_SDA              (_MX53_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C))
+#define MX53_PAD_GPIO_8__GPIO1_8                        IOMUX_PAD(0x6C8, 0x338, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__SJC_DE_B              (_MX53_PAD_GPIO_16__SJC_DE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_8__EPIT2_EPITO                    IOMUX_PAD(0x6C8, 0x338, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__ESAI1_TX0             (_MX53_PAD_GPIO_17__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_8__CAN1_RXCAN                     IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 3, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__GPIO7_12              (_MX53_PAD_GPIO_17__GPIO7_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_8__UART2_RXD_MUX                  IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, MX53_UART_PAD_CTRL)
-#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0              (_MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_8__FIRI_TXD                       IOMUX_PAD(0x6C8, 0x338, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__GPC_PMIC_RDY          (_MX53_PAD_GPIO_17__GPC_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_8__SPDIF_SRCLK                    IOMUX_PAD(0x6C8, 0x338, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG           (_MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_8__CCM_PLL3_BYP                   IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__SPDIF_OUT1            (_MX53_PAD_GPIO_17__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2                 IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__IPU_SNOOP2            (_MX53_PAD_GPIO_17__IPU_SNOOP2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_16__GPIO7_11                      IOMUX_PAD(0x6CC, 0x33C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__SJC_JTAG_ACT          (_MX53_PAD_GPIO_17__SJC_JTAG_ACT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT              IOMUX_PAD(0x6CC, 0x33C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__ESAI1_TX1             (_MX53_PAD_GPIO_18__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1          IOMUX_PAD(0x6CC, 0x33C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__GPIO7_13              (_MX53_PAD_GPIO_18__GPIO7_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_16__SPDIF_IN1                     IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1              (_MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_16__I2C3_SDA                      IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__OWIRE_LINE            (_MX53_PAD_GPIO_18__OWIRE_LINE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_16__SJC_DE_B                      IOMUX_PAD(0x6CC, 0x33C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG                (_MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_17__ESAI1_TX0                     IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK              (_MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_17__GPIO7_12                      IOMUX_PAD(0x6D0, 0x340, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__ESDHC1_LCTL           (_MX53_PAD_GPIO_18__ESDHC1_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0              IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST                (_MX53_PAD_GPIO_18__SRC_SYSTEM_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_17__GPC_PMIC_RDY                  IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG           IOMUX_PAD(0x6D0, 0x340, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_17__SPDIF_OUT1                    IOMUX_PAD(0x6D0, 0x340, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_17__IPU_SNOOP2                    IOMUX_PAD(0x6D0, 0x340, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_17__SJC_JTAG_ACT                  IOMUX_PAD(0x6D0, 0x340, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__ESAI1_TX1                     IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__GPIO7_13                      IOMUX_PAD(0x6D4, 0x344, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1              IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__OWIRE_LINE                    IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG        IOMUX_PAD(0x6D4, 0x344, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK              IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__ESDHC1_LCTL                   IOMUX_PAD(0x6D4, 0x344, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST                IOMUX_PAD(0x6D4, 0x344, 7, __NA_, 0, NO_PAD_CTRL)
 #endif  /* __MACH_IOMUX_MX53_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index ebbce33097a7..2fa3b5430102 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -80,6 +80,7 @@ typedef u64 iomux_v3_cfg_t;
                ((iomux_v3_cfg_t)(_sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT) | \
                ((iomux_v3_cfg_t)(_sel_input) << MUX_SEL_INPUT_SHIFT))
+#define NEW_PAD_CTRL(cfg, pad)  (((cfg) & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(pad))
 /*
 * Use to set PAD control
 */
@@ -89,11 +90,11 @@ typedef u64 iomux_v3_cfg_t;
 #define PAD_CTL_HYS                     (1 << 8)
 #define PAD_CTL_PKE                     (1 << 7)
-#define PAD_CTL_PUE                     (1 << 6)
+#define PAD_CTL_PUE                     (1 << 6 | PAD_CTL_PKE)
-#define PAD_CTL_PUS_100K_DOWN           (0 << 4)
+#define PAD_CTL_PUS_100K_DOWN           (0 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_47K_UP              (1 << 4)
+#define PAD_CTL_PUS_47K_UP              (1 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_100K_UP             (2 << 4)
+#define PAD_CTL_PUS_100K_UP             (2 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_22K_UP              (3 << 4)
+#define PAD_CTL_PUS_22K_UP              (3 << 4 | PAD_CTL_PUE)
 #define PAD_CTL_ODE                     (1 << 3)
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index 00e812bbd81d..fd9efb044656 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -14,9 +14,15 @@
 #include <asm-generic/gpio.h>
 /*
- * SoCs with TZIC interrupt controller have 128 IRQs, those with AVIC have 64
+ * SoCs with GIC interrupt controller have 160 IRQs, those with TZIC
+ * have 128 IRQs, and those with AVIC have 64.
+ *
+ * To support single image, the biggest number should be defined on
+ * top of the list.
 */
-#ifdef CONFIG_MXC_TZIC
+#if defined CONFIG_ARM_GIC
+#define MXC_INTERNAL_IRQS       160
+#elif defined CONFIG_MXC_TZIC
 #define MXC_INTERNAL_IRQS       128
 #else
 #define MXC_INTERNAL_IRQS       64
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index 087cd7ac8d52..ccebf5ba12f0 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -41,6 +41,7 @@
 #define MX25_SSI2_BASE_ADDR             0x50014000
 #define MX25_SSI1_BASE_ADDR             0x50034000
 #define MX25_NFC_BASE_ADDR              0xbb000000
+#define MX25_IIM_BASE_ADDR              0x53ff0000
 #define MX25_DRYICE_BASE_ADDR           0x53ffc000
 #define MX25_ESDHC1_BASE_ADDR           0x53fb4000
 #define MX25_ESDHC2_BASE_ADDR           0x53fb8000
@@ -104,4 +105,8 @@
 #define MX25_DMA_REQ_SSI1_RX0   28
 #define MX25_DMA_REQ_SSI1_TX0   29
+#ifndef __ASSEMBLY__
+extern int mx25_revision(void);
+#endif
 #endif /* ifndef __MACH_MX25_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index 1dc1c522601b..6265357284d7 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -24,10 +24,6 @@
 #ifndef __MACH_MX27_H__
 #define __MACH_MX27_H__
-#ifndef __ASSEMBLER__
-#include <linux/io.h>
-#endif
 #define MX27_AIPI_BASE_ADDR             0x10000000
 #define MX27_AIPI_SIZE                  SZ_1M
 #define MX27_DMA_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x01000)
@@ -131,16 +127,6 @@
 #define MX27_IO_P2V(x)                  IMX_IO_P2V(x)
 #define MX27_IO_ADDRESS(x)              IOMEM(MX27_IO_P2V(x))
-#ifndef __ASSEMBLER__
-static inline void mx27_setup_weimcs(size_t cs,
-                unsigned upper, unsigned lower, unsigned addional)
-{
-        __raw_writel(upper, MX27_IO_ADDRESS(MX27_WEIM_CSCRxU(cs)));
-        __raw_writel(lower, MX27_IO_ADDRESS(MX27_WEIM_CSCRxL(cs)));
-        __raw_writel(addional, MX27_IO_ADDRESS(MX27_WEIM_CSCRxA(cs)));
-}
-#endif
 /* fixed interrupt numbers */
 #define MX27_INT_I2C2           1
 #define MX27_INT_GPT6           2
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index 79e7fc01bb59..e27619e442c0 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -1,10 +1,6 @@
 #ifndef __MACH_MX31_H__
 #define __MACH_MX31_H__
-#ifndef __ASSEMBLER__
-#include <linux/io.h>
-#endif
 /*
 * IRAM
 */
@@ -122,16 +118,6 @@
 #define MX31_IO_P2V(x)                  IMX_IO_P2V(x)
 #define MX31_IO_ADDRESS(x)              IOMEM(MX31_IO_P2V(x))
-#ifndef __ASSEMBLER__
-static inline void mx31_setup_weimcs(size_t cs,
-                unsigned upper, unsigned lower, unsigned addional)
-{
-        __raw_writel(upper, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(cs)));
-        __raw_writel(lower, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(cs)));
-        __raw_writel(addional, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(cs)));
-}
-#endif
 #define MX31_INT_I2C3           3
 #define MX31_INT_I2C2           4
 #define MX31_INT_MPEG4_ENCODER  5
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index d13dbfeef08a..80965a99aa55 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -36,7 +36,7 @@
 #define MX35_UART3_BASE_ADDR                    (MX35_SPBA0_BASE_ADDR + 0x0c000)
 #define MX35_CSPI2_BASE_ADDR                    (MX35_SPBA0_BASE_ADDR + 0x10000)
 #define MX35_SSI2_BASE_ADDR                     (MX35_SPBA0_BASE_ADDR + 0x14000)
-#define MX35_ATA_DMA_BASE_ADDR                  (MX35_SPBA0_BASE_ADDR + 0x20000)
+#define MX35_ATA_BASE_ADDR                      (MX35_SPBA0_BASE_ADDR + 0x20000)
 #define MX35_MSHC1_BASE_ADDR                    (MX35_SPBA0_BASE_ADDR + 0x24000)
 #define MX35_FEC_BASE_ADDR              0x50038000
 #define MX35_SPBA_CTRL_BASE_ADDR                (MX35_SPBA0_BASE_ADDR + 0x3c000)
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
index 388a407d72d6..30dbf424583e 100644
--- a/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -187,22 +187,8 @@
 /* Mandatory defines used globally */
 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
+extern int mx35_revision(void);
-extern unsigned int mx31_cpu_rev;
+extern int mx31_revision(void);
-extern void mx31_read_cpu_rev(void);
-static inline int mx31_revision(void)
-{
-        return mx31_cpu_rev;
-}
-extern unsigned int mx35_cpu_rev;
-extern void mx35_read_cpu_rev(void);
-static inline int mx35_revision(void)
-{
-        return mx35_cpu_rev;
-}
 #endif
 #endif /* ifndef __MACH_MX3x_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index dede19a766ff..cdf07c65ec1e 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -18,18 +18,6 @@
 #define MX51_GPU_CTRL_BASE_ADDR         0x30000000
 #define MX51_IPU_CTRL_BASE_ADDR         0x40000000
-#define MX51_DEBUG_BASE_ADDR            0x60000000
-#define MX51_DEBUG_SIZE                 SZ_1M
-#define MX51_ETB_BASE_ADDR              (MX51_DEBUG_BASE_ADDR + 0x01000)
-#define MX51_ETM_BASE_ADDR              (MX51_DEBUG_BASE_ADDR + 0x02000)
-#define MX51_TPIU_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x03000)
-#define MX51_CTI0_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x04000)
-#define MX51_CTI1_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x05000)
-#define MX51_CTI2_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x06000)
-#define MX51_CTI3_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x07000)
-#define MX51_CORTEX_DBG_BASE_ADDR       (MX51_DEBUG_BASE_ADDR + 0x08000)
 /*
 * SPBA global module enabled #0
 */
@@ -55,7 +43,10 @@
 #define MX51_AIPS1_BASE_ADDR            0x73f00000
 #define MX51_AIPS1_SIZE                 SZ_1M
-#define MX51_OTG_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0x80000)
+#define MX51_USB_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0x80000)
+#define MX51_USB_OTG_BASE_ADDR          (MX51_USB_BASE_ADDR + 0x0000)
+#define MX51_USB_HS1_BASE_ADDR          (MX51_USB_BASE_ADDR + 0x0200)
+#define MX51_USB_HS2_BASE_ADDR          (MX51_USB_BASE_ADDR + 0x0400)
 #define MX51_GPIO1_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x84000)
 #define MX51_GPIO2_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x88000)
 #define MX51_GPIO3_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x8c000)
@@ -132,6 +123,7 @@
 #define MX51_GPU2D_BASE_ADDR            0xd0000000
 #define MX51_TZIC_BASE_ADDR             0xe0000000
+#define MX51_TZIC_SIZE                  SZ_16K
 #define MX51_IO_P2V(x)                  IMX_IO_P2V(x)
 #define MX51_IO_ADDRESS(x)              IOMEM(MX51_IO_P2V(x))
@@ -240,117 +232,114 @@
 /*
 * Interrupt numbers
 */
-#define MX51_MXC_INT_BASE               0
+#define MX51_INT_BASE                   0
-#define MX51_MXC_INT_RESV0              0
+#define MX51_INT_RESV0                  0
 #define MX51_INT_ESDHC1                 1
 #define MX51_INT_ESDHC2                 2
 #define MX51_INT_ESDHC3                 3
 #define MX51_INT_ESDHC4                 4
-#define MX51_MXC_INT_RESV5              5
+#define MX51_INT_RESV5                  5
 #define MX51_INT_SDMA                   6
-#define MX51_MXC_INT_IOMUX              7
+#define MX51_INT_IOMUX                  7
 #define MX51_INT_NFC                    8
-#define MX51_MXC_INT_VPU                9
+#define MX51_INT_VPU                    9
 #define MX51_INT_IPU_ERR                10
 #define MX51_INT_IPU_SYN                11
-#define MX51_MXC_INT_GPU                12
+#define MX51_INT_GPU                    12
-#define MX51_MXC_INT_RESV13             13
+#define MX51_INT_RESV13                 13
-#define MX51_MXC_INT_USB_H1             14
+#define MX51_INT_USB_HS1                14
-#define MX51_MXC_INT_EMI                15
+#define MX51_INT_EMI                    15
-#define MX51_MXC_INT_USB_H2             16
+#define MX51_INT_USB_HS2                16
-#define MX51_MXC_INT_USB_H3             17
+#define MX51_INT_USB_HS3                17
-#define MX51_MXC_INT_USB_OTG            18
+#define MX51_INT_USB_OTG                18
-#define MX51_MXC_INT_SAHARA_H0          19
+#define MX51_INT_SAHARA_H0              19
-#define MX51_MXC_INT_SAHARA_H1          20
+#define MX51_INT_SAHARA_H1              20
-#define MX51_MXC_INT_SCC_SMN            21
+#define MX51_INT_SCC_SMN                21
-#define MX51_MXC_INT_SCC_STZ            22
+#define MX51_INT_SCC_STZ                22
-#define MX51_MXC_INT_SCC_SCM            23
+#define MX51_INT_SCC_SCM                23
-#define MX51_MXC_INT_SRTC_NTZ           24
+#define MX51_INT_SRTC_NTZ               24
-#define MX51_MXC_INT_SRTC_TZ            25
+#define MX51_INT_SRTC_TZ                25
-#define MX51_MXC_INT_RTIC               26
+#define MX51_INT_RTIC                   26
-#define MX51_MXC_INT_CSU                27
+#define MX51_INT_CSU                    27
-#define MX51_MXC_INT_SLIM_B             28
+#define MX51_INT_SLIM_B                 28
 #define MX51_INT_SSI1                   29
 #define MX51_INT_SSI2                   30
 #define MX51_INT_UART1                  31
 #define MX51_INT_UART2                  32
 #define MX51_INT_UART3                  33
-#define MX51_MXC_INT_RESV34             34
+#define MX51_INT_RESV34                 34
-#define MX51_MXC_INT_RESV35             35
+#define MX51_INT_RESV35                 35
 #define MX51_INT_ECSPI1                 36
 #define MX51_INT_ECSPI2                 37
 #define MX51_INT_CSPI                   38
-#define MX51_MXC_INT_GPT                39
+#define MX51_INT_GPT                    39
-#define MX51_MXC_INT_EPIT1              40
+#define MX51_INT_EPIT1                  40
-#define MX51_MXC_INT_EPIT2              41
+#define MX51_INT_EPIT2                  41
-#define MX51_MXC_INT_GPIO1_INT7         42
+#define MX51_INT_GPIO1_INT7             42
-#define MX51_MXC_INT_GPIO1_INT6         43
+#define MX51_INT_GPIO1_INT6             43
-#define MX51_MXC_INT_GPIO1_INT5         44
+#define MX51_INT_GPIO1_INT5             44
-#define MX51_MXC_INT_GPIO1_INT4         45
+#define MX51_INT_GPIO1_INT4             45
-#define MX51_MXC_INT_GPIO1_INT3         46
+#define MX51_INT_GPIO1_INT3             46
-#define MX51_MXC_INT_GPIO1_INT2         47
+#define MX51_INT_GPIO1_INT2             47
-#define MX51_MXC_INT_GPIO1_INT1         48
+#define MX51_INT_GPIO1_INT1             48
-#define MX51_MXC_INT_GPIO1_INT0         49
+#define MX51_INT_GPIO1_INT0             49
-#define MX51_MXC_INT_GPIO1_LOW          50
+#define MX51_INT_GPIO1_LOW              50
-#define MX51_MXC_INT_GPIO1_HIGH         51
+#define MX51_INT_GPIO1_HIGH             51
-#define MX51_MXC_INT_GPIO2_LOW          52
+#define MX51_INT_GPIO2_LOW              52
-#define MX51_MXC_INT_GPIO2_HIGH         53
+#define MX51_INT_GPIO2_HIGH             53
-#define MX51_MXC_INT_GPIO3_LOW          54
+#define MX51_INT_GPIO3_LOW              54
-#define MX51_MXC_INT_GPIO3_HIGH         55
+#define MX51_INT_GPIO3_HIGH             55
-#define MX51_MXC_INT_GPIO4_LOW          56
+#define MX51_INT_GPIO4_LOW              56
-#define MX51_MXC_INT_GPIO4_HIGH         57
+#define MX51_INT_GPIO4_HIGH             57
-#define MX51_MXC_INT_WDOG1              58
+#define MX51_INT_WDOG1                  58
-#define MX51_MXC_INT_WDOG2              59
+#define MX51_INT_WDOG2                  59
 #define MX51_INT_KPP                    60
 #define MX51_INT_PWM1                   61
 #define MX51_INT_I2C1                   62
 #define MX51_INT_I2C2                   63
-#define MX51_MXC_INT_HS_I2C             64
+#define MX51_INT_HS_I2C                 64
-#define MX51_MXC_INT_RESV65             65
+#define MX51_INT_RESV65                 65
-#define MX51_MXC_INT_RESV66             66
+#define MX51_INT_RESV66                 66
-#define MX51_MXC_INT_SIM_IPB            67
+#define MX51_INT_SIM_IPB                67
-#define MX51_MXC_INT_SIM_DAT            68
+#define MX51_INT_SIM_DAT                68
-#define MX51_MXC_INT_IIM                69
+#define MX51_INT_IIM                    69
-#define MX51_MXC_INT_ATA                70
+#define MX51_INT_ATA                    70
-#define MX51_MXC_INT_CCM1               71
+#define MX51_INT_CCM1                   71
-#define MX51_MXC_INT_CCM2               72
+#define MX51_INT_CCM2                   72
-#define MX51_MXC_INT_GPC1               73
+#define MX51_INT_GPC1                           73
-#define MX51_MXC_INT_GPC2               74
+#define MX51_INT_GPC2                   74
-#define MX51_MXC_INT_SRC                75
+#define MX51_INT_SRC                    75
-#define MX51_MXC_INT_NM                 76
+#define MX51_INT_NM                     76
-#define MX51_MXC_INT_PMU                77
+#define MX51_INT_PMU                    77
-#define MX51_MXC_INT_CTI_IRQ            78
+#define MX51_INT_CTI_IRQ                78
-#define MX51_MXC_INT_CTI1_TG0           79
+#define MX51_INT_CTI1_TG0               79
-#define MX51_MXC_INT_CTI1_TG1           80
+#define MX51_INT_CTI1_TG1               80
-#define MX51_MXC_INT_MCG_ERR            81
+#define MX51_INT_MCG_ERR                81
-#define MX51_MXC_INT_MCG_TMR            82
+#define MX51_INT_MCG_TMR                82
-#define MX51_MXC_INT_MCG_FUNC           83
+#define MX51_INT_MCG_FUNC               83
-#define MX51_MXC_INT_GPU2_IRQ           84
+#define MX51_INT_GPU2_IRQ               84
-#define MX51_MXC_INT_GPU2_BUSY          85
+#define MX51_INT_GPU2_BUSY              85
-#define MX51_MXC_INT_RESV86             86
+#define MX51_INT_RESV86                 86
 #define MX51_INT_FEC                    87
-#define MX51_MXC_INT_OWIRE              88
+#define MX51_INT_OWIRE                  88
-#define MX51_MXC_INT_CTI1_TG2           89
+#define MX51_INT_CTI1_TG2               89
-#define MX51_MXC_INT_SJC                90
+#define MX51_INT_SJC                    90
-#define MX51_MXC_INT_SPDIF              91
+#define MX51_INT_SPDIF                  91
-#define MX51_MXC_INT_TVE                92
+#define MX51_INT_TVE                    92
-#define MX51_MXC_INT_FIRI               93
+#define MX51_INT_FIRI                   93
 #define MX51_INT_PWM2                   94
-#define MX51_MXC_INT_SLIM_EXP           95
+#define MX51_INT_SLIM_EXP               95
 #define MX51_INT_SSI3                   96
-#define MX51_MXC_INT_EMI_BOOT           97
+#define MX51_INT_EMI_BOOT               97
-#define MX51_MXC_INT_CTI1_TG3           98
+#define MX51_INT_CTI1_TG3               98
-#define MX51_MXC_INT_SMC_RX             99
+#define MX51_INT_SMC_RX                 99
-#define MX51_MXC_INT_VPU_IDLE           100
+#define MX51_INT_VPU_IDLE               100
-#define MX51_MXC_INT_EMI_NFC            101
+#define MX51_INT_EMI_NFC                101
-#define MX51_MXC_INT_GPU_IDLE           102
+#define MX51_INT_GPU_IDLE               102
 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
 extern int mx51_revision(void);
 extern void mx51_display_revision(void);
 #endif
-/* tape-out 1 defines */
-#define MX51_TZIC_BASE_ADDR_TO1         0x8fffc000
 #endif  /* ifndef __MACH_MX51_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h
index 5e3c3236ebf3..a37e8c353994 100644
--- a/arch/arm/plat-mxc/include/mach/mx53.h
+++ b/arch/arm/plat-mxc/include/mach/mx53.h
@@ -9,6 +9,7 @@
 /* TZIC */
 #define MX53_TZIC_BASE_ADDR             0x0FFFC000
+#define MX53_TZIC_SIZE                  SZ_16K
 /*
 * AHCI SATA
diff --git a/arch/arm/plat-mxc/include/mach/mx6q.h b/arch/arm/plat-mxc/include/mach/mx6q.h
new file mode 100644
index 000000000000..254a561a2799
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx6q.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __MACH_MX6Q_H__
+#define __MACH_MX6Q_H__
+#define MX6Q_IO_P2V(x)                  IMX_IO_P2V(x)
+#define MX6Q_IO_ADDRESS(x)              IOMEM(MX6Q_IO_P2V(x))
+/*
+ * The following are the blocks that need to be statically mapped.
+ * For other blocks, the base address really should be retrieved from
+ * device tree.
+ */
+#define MX6Q_SCU_BASE_ADDR              0x00a00000
+#define MX6Q_SCU_SIZE                   0x1000
+#define MX6Q_CCM_BASE_ADDR              0x020c4000
+#define MX6Q_CCM_SIZE                   0x4000
+#define MX6Q_ANATOP_BASE_ADDR           0x020c8000
+#define MX6Q_ANATOP_SIZE                0x1000
+#define MX6Q_UART4_BASE_ADDR            0x021f0000
+#define MX6Q_UART4_SIZE                 0x4000
+#endif  /* __MACH_MX6Q_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 09879235a9f5..00a78193c681 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -183,13 +183,6 @@ struct cpu_op {
 };
 int tzic_enable_wake(int is_idle);
-enum mxc_cpu_pwr_mode {
-        WAIT_CLOCKED,           /* wfi only */
-        WAIT_UNCLOCKED,         /* WAIT */
-        WAIT_UNCLOCKED_POWER_OFF,       /* WAIT + SRPG */
-        STOP_POWER_ON,          /* just STOP */
-        STOP_POWER_OFF,         /* STOP + SRPG */
-};
 extern struct cpu_op *(*get_cpu_op)(int *op);
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
index 51f02a9d41a3..cf88b3593fba 100644
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -17,41 +17,12 @@
 #ifndef __ASM_ARCH_MXC_SYSTEM_H__
 #define __ASM_ARCH_MXC_SYSTEM_H__
-#include <mach/hardware.h>
+extern void (*imx_idle)(void);
-#include <mach/common.h>
-extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
 static inline void arch_idle(void)
 {
-        /* fix i.MX31 errata TLSbo65953 and i.MX35 errata ENGcm09472 */
+        if (imx_idle != NULL)
-        if (cpu_is_mx31() || cpu_is_mx35()) {
+                (imx_idle)();
-                unsigned long reg = 0;
-                __asm__ __volatile__(
-                        /* disable I and D cache */
-                        "mrc p15, 0, %0, c1, c0, 0\n"
-                        "bic %0, %0, #0x00001000\n"
-                        "bic %0, %0, #0x00000004\n"
-                        "mcr p15, 0, %0, c1, c0, 0\n"
-                        /* invalidate I cache */
-                        "mov %0, #0\n"
-                        "mcr p15, 0, %0, c7, c5, 0\n"
-                        /* clear and invalidate D cache */
-                        "mov %0, #0\n"
-                        "mcr p15, 0, %0, c7, c14, 0\n"
-                        /* WFI */
-                        "mov %0, #0\n"
-                        "mcr p15, 0, %0, c7, c0, 4\n"
-                        "nop\n" "nop\n" "nop\n" "nop\n"
-                        "nop\n" "nop\n" "nop\n"
-                        /* enable I and D cache */
-                        "mrc p15, 0, %0, c1, c0, 0\n"
-                        "orr %0, %0, #0x00001000\n"
-                        "orr %0, %0, #0x00000004\n"
-                        "mcr p15, 0, %0, c1, c0, 0\n"
-                        : "=r" (reg));
-        } else if (cpu_is_mx51())
-                mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
        else
                cpu_do_idle();
 }
diff --git a/arch/arm/plat-mxc/irq-common.c b/arch/arm/plat-mxc/irq-common.c
index 96953e2e4f11..b6e11458e5ae 100644
--- a/arch/arm/plat-mxc/irq-common.c
+++ b/arch/arm/plat-mxc/irq-common.c
@@ -23,17 +23,17 @@
 int imx_irq_set_priority(unsigned char irq, unsigned char prio)
 {
-        struct mxc_irq_chip *chip;
+        struct irq_chip_generic *gc;
-        struct irq_chip *base;
+        struct mxc_extra_irq *exirq;
        int ret;
        ret = -ENOSYS;
-        base = irq_get_chip(irq);
+        gc = irq_get_chip_data(irq);
-        if (base) {
+        if (gc && gc->private) {
-                chip = container_of(base, struct mxc_irq_chip, base);
+                exirq = gc->private;
-                if (chip->set_priority)
+                if (exirq->set_priority)
-                        ret = chip->set_priority(irq, prio);
+                        ret = exirq->set_priority(irq, prio);
        }
        return ret;
@@ -43,15 +43,16 @@ EXPORT_SYMBOL(imx_irq_set_priority);
 int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
 {
        struct irq_chip_generic *gc;
-        int (*set_irq_fiq)(unsigned int, unsigned int);
+        struct mxc_extra_irq *exirq;
        int ret;
        ret = -ENOSYS;
        gc = irq_get_chip_data(irq);
        if (gc && gc->private) {
-                set_irq_fiq = gc->private;
+                exirq = gc->private;
-                ret = set_irq_fiq(irq, type);
+                if (exirq->set_irq_fiq)
+                        ret = exirq->set_irq_fiq(irq, type);
        }
        return ret;
diff --git a/arch/arm/plat-mxc/irq-common.h b/arch/arm/plat-mxc/irq-common.h
index 7203543fb1b3..6ccb3a14c693 100644
--- a/arch/arm/plat-mxc/irq-common.h
+++ b/arch/arm/plat-mxc/irq-common.h
@@ -19,9 +19,8 @@
 #ifndef __PLAT_MXC_IRQ_COMMON_H__
 #define __PLAT_MXC_IRQ_COMMON_H__
-struct mxc_irq_chip
+struct mxc_extra_irq
 {
-        struct irq_chip base;
        int (*set_priority)(unsigned char irq, unsigned char prio);
        int (*set_irq_fiq)(unsigned int irq, unsigned int type);
 };
diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c
index 761c3c940a68..42d74ea59084 100644
--- a/arch/arm/plat-mxc/pwm.c
+++ b/arch/arm/plat-mxc/pwm.c
@@ -57,7 +57,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
        if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
                return -EINVAL;
-        if (cpu_is_mx27() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) {
+        if (!(cpu_is_mx1() || cpu_is_mx21())) {
                unsigned long long c;
                unsigned long period_cycles, duty_cycles, prescale;
                u32 cr;
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 8024f2ac177c..9dad8dcc2ea9 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -28,6 +28,9 @@
 #include <asm/system.h>
 #include <asm/mach-types.h>
+void (*imx_idle)(void) = NULL;
+void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int) = NULL;
 static void __iomem *wdog_base;
 /*
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index f257fccdc394..e993a184189a 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -42,7 +42,7 @@
 #define TZIC_SRCCLAR0   0x0280  /* Source Clear Register 0 */
 #define TZIC_PRIORITY0  0x0400  /* Priority Register 0 */
 #define TZIC_PND0       0x0D00  /* Pending Register 0 */
-#define TZIC_HIPND0     0x0D80  /* High Priority Pending Register */
+#define TZIC_HIPND(i)   (0x0D80+ ((i) << 2))    /* High Priority Pending Register */
 #define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2))   /* Wakeup Config Register */
 #define TZIC_SWINT      0x0F00  /* Software Interrupt Rigger Register */
 #define TZIC_ID0        0x0FD0  /* Indentification Register 0 */
@@ -74,6 +74,12 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
 static unsigned int *wakeup_intr[4];
+static struct mxc_extra_irq tzic_extra_irq = {
+#ifdef CONFIG_FIQ
+        .set_irq_fiq = tzic_set_irq_fiq,
+#endif
+};
 static __init void tzic_init_gc(unsigned int irq_start)
 {
        struct irq_chip_generic *gc;
@@ -82,7 +88,7 @@ static __init void tzic_init_gc(unsigned int irq_start)
        gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base,
                                    handle_level_irq);
-        gc->private = tzic_set_irq_fiq;
+        gc->private = &tzic_extra_irq;
        gc->wake_enabled = IRQ_MSK(32);
        wakeup_intr[idx] = &gc->wake_active;
@@ -96,6 +102,28 @@ static __init void tzic_init_gc(unsigned int irq_start)
        irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
 }
+asmlinkage void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
+{
+        u32 stat;
+        int i, irqofs, handled;
+        do {
+                handled = 0;
+                for (i = 0; i < 4; i++) {
+                        stat = __raw_readl(tzic_base + TZIC_HIPND(i)) &
+                                __raw_readl(tzic_base + TZIC_INTSEC0(i));
+                        while (stat) {
+                                handled = 1;
+                                irqofs = fls(stat) - 1;
+                                handle_IRQ(irqofs + i * 32, regs);
+                                stat &= ~(1 << irqofs);
+                        }
+                }
+        } while (handled);
+}
 /*
 * This function initializes the TZIC hardware and disables all the
 * interrupts. It registers the interrupt enable and disable functions
diff --git a/arch/arm/plat-nomadik/Kconfig b/arch/arm/plat-nomadik/Kconfig
index ce659015535e..bca4914b4b9d 100644
--- a/arch/arm/plat-nomadik/Kconfig
+++ b/arch/arm/plat-nomadik/Kconfig
@@ -15,10 +15,16 @@ if PLAT_NOMADIK
 config HAS_MTU
        bool
-        select HAVE_SCHED_CLOCK
        help
          Support for Multi Timer Unit. MTU provides access
          to multiple interrupt generating programmable
          32-bit free running decrementing counters.
+config NOMADIK_MTU_SCHED_CLOCK
+        bool
+        depends on HAS_MTU
+        select HAVE_SCHED_CLOCK
+        help
+          Use the Multi Timer Unit as the sched_clock.
 endif
diff --git a/arch/arm/plat-nomadik/include/plat/mtu.h b/arch/arm/plat-nomadik/include/plat/mtu.h
index 65704a3d4241..6508e7694a4b 100644
--- a/arch/arm/plat-nomadik/include/plat/mtu.h
+++ b/arch/arm/plat-nomadik/include/plat/mtu.h
@@ -1,54 +1,11 @@
 #ifndef __PLAT_MTU_H
 #define __PLAT_MTU_H
-/*
- * Guaranteed runtime conversion range in seconds for
- * the clocksource and clockevent.
- */
-#define MTU_MIN_RANGE 4
 /* should be set by the platform code */
 extern void __iomem *mtu_base;
-/*
+void nmdk_clkevt_reset(void);
- * The MTU device hosts four different counters, with 4 set of
+void nmdk_clksrc_reset(void);
- * registers. These are register names.
- */
-#define MTU_IMSC        0x00    /* Interrupt mask set/clear */
-#define MTU_RIS         0x04    /* Raw interrupt status */
-#define MTU_MIS         0x08    /* Masked interrupt status */
-#define MTU_ICR         0x0C    /* Interrupt clear register */
-/* per-timer registers take 0..3 as argument */
-#define MTU_LR(x)       (0x10 + 0x10 * (x) + 0x00)      /* Load value */
-#define MTU_VAL(x)      (0x10 + 0x10 * (x) + 0x04)      /* Current value */
-#define MTU_CR(x)       (0x10 + 0x10 * (x) + 0x08)      /* Control reg */
-#define MTU_BGLR(x)     (0x10 + 0x10 * (x) + 0x0c)      /* At next overflow */
-/* bits for the control register */
-#define MTU_CRn_ENA             0x80
-#define MTU_CRn_PERIODIC        0x40    /* if 0 = free-running */
-#define MTU_CRn_PRESCALE_MASK   0x0c
-#define MTU_CRn_PRESCALE_1              0x00
-#define MTU_CRn_PRESCALE_16             0x04
-#define MTU_CRn_PRESCALE_256            0x08
-#define MTU_CRn_32BITS          0x02
-#define MTU_CRn_ONESHOT         0x01    /* if 0 = wraps reloading from BGLR*/
-/* Other registers are usual amba/primecell registers, currently not used */
-#define MTU_ITCR        0xff0
-#define MTU_ITOP        0xff4
-#define MTU_PERIPH_ID0  0xfe0
-#define MTU_PERIPH_ID1  0xfe4
-#define MTU_PERIPH_ID2  0xfe8
-#define MTU_PERIPH_ID3  0xfeC
-#define MTU_PCELL0      0xff0
-#define MTU_PCELL1      0xff4
-#define MTU_PCELL2      0xff8
-#define MTU_PCELL3      0xffC
 #endif /* __PLAT_MTU_H */
diff --git a/arch/arm/plat-nomadik/include/plat/pincfg.h b/arch/arm/plat-nomadik/include/plat/pincfg.h
index 05a3936ae6d1..22cb97d2d8ad 100644
--- a/arch/arm/plat-nomadik/include/plat/pincfg.h
+++ b/arch/arm/plat-nomadik/include/plat/pincfg.h
@@ -37,7 +37,6 @@
 *                   SLPM value = same as normal
 *
 * PIN_CFG         - default config with alternate function
- * PIN_CFG_PULL    - default config with alternate function and pull up/down
 */
 typedef unsigned long pin_cfg_t;
@@ -133,10 +132,6 @@ typedef unsigned long pin_cfg_t;
        (PIN_CFG_DEFAULT |\
         (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
-#define PIN_CFG_PULL(num, alt, pull)    \
-        ((PIN_CFG_DEFAULT & ~PIN_PULL_MASK) |\
-         (PIN_NUM(num) | PIN_##alt | PIN_PULL_##pull))
 extern int nmk_config_pin(pin_cfg_t cfg, bool sleep);
 extern int nmk_config_pins(pin_cfg_t *cfgs, int num);
 extern int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num);
diff --git a/arch/arm/plat-nomadik/timer.c b/arch/arm/plat-nomadik/timer.c
index ef74e157a9d5..30b6433d910d 100644
--- a/arch/arm/plat-nomadik/timer.c
+++ b/arch/arm/plat-nomadik/timer.c
@@ -21,10 +21,59 @@
 #include <asm/mach/time.h>
 #include <asm/sched_clock.h>
-#include <plat/mtu.h>
+/*
+ * Guaranteed runtime conversion range in seconds for
+ * the clocksource and clockevent.
+ */
+#define MTU_MIN_RANGE 4
+/*
+ * The MTU device hosts four different counters, with 4 set of
+ * registers. These are register names.
+ */
+#define MTU_IMSC        0x00    /* Interrupt mask set/clear */
+#define MTU_RIS         0x04    /* Raw interrupt status */
+#define MTU_MIS         0x08    /* Masked interrupt status */
+#define MTU_ICR         0x0C    /* Interrupt clear register */
+/* per-timer registers take 0..3 as argument */
+#define MTU_LR(x)       (0x10 + 0x10 * (x) + 0x00)      /* Load value */
+#define MTU_VAL(x)      (0x10 + 0x10 * (x) + 0x04)      /* Current value */
+#define MTU_CR(x)       (0x10 + 0x10 * (x) + 0x08)      /* Control reg */
+#define MTU_BGLR(x)     (0x10 + 0x10 * (x) + 0x0c)      /* At next overflow */
+/* bits for the control register */
+#define MTU_CRn_ENA             0x80
+#define MTU_CRn_PERIODIC        0x40    /* if 0 = free-running */
+#define MTU_CRn_PRESCALE_MASK   0x0c
+#define MTU_CRn_PRESCALE_1              0x00
+#define MTU_CRn_PRESCALE_16             0x04
+#define MTU_CRn_PRESCALE_256            0x08
+#define MTU_CRn_32BITS          0x02
+#define MTU_CRn_ONESHOT         0x01    /* if 0 = wraps reloading from BGLR*/
+/* Other registers are usual amba/primecell registers, currently not used */
+#define MTU_ITCR        0xff0
+#define MTU_ITOP        0xff4
+#define MTU_PERIPH_ID0  0xfe0
+#define MTU_PERIPH_ID1  0xfe4
+#define MTU_PERIPH_ID2  0xfe8
+#define MTU_PERIPH_ID3  0xfeC
+#define MTU_PCELL0      0xff0
+#define MTU_PCELL1      0xff4
+#define MTU_PCELL2      0xff8
+#define MTU_PCELL3      0xffC
+static bool clkevt_periodic;
+static u32 clk_prescale;
+static u32 nmdk_cycle;          /* write-once */
 void __iomem *mtu_base; /* Assigned by machine code */
+#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
 /*
 * Override the global weak sched_clock symbol with this
 * local implementation which uses the clocksource to get some
@@ -48,32 +97,56 @@ static void notrace nomadik_update_sched_clock(void)
        u32 cyc = -readl(mtu_base + MTU_VAL(0));
        update_sched_clock(&cd, cyc, (u32)~0);
 }
+#endif
 /* Clockevent device: use one-shot mode */
+static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
+{
+        writel(1 << 1, mtu_base + MTU_IMSC);
+        writel(evt, mtu_base + MTU_LR(1));
+        /* Load highest value, enable device, enable interrupts */
+        writel(MTU_CRn_ONESHOT | clk_prescale |
+               MTU_CRn_32BITS | MTU_CRn_ENA,
+               mtu_base + MTU_CR(1));
+        return 0;
+}
+void nmdk_clkevt_reset(void)
+{
+        if (clkevt_periodic) {
+                /* Timer: configure load and background-load, and fire it up */
+                writel(nmdk_cycle, mtu_base + MTU_LR(1));
+                writel(nmdk_cycle, mtu_base + MTU_BGLR(1));
+                writel(MTU_CRn_PERIODIC | clk_prescale |
+                       MTU_CRn_32BITS | MTU_CRn_ENA,
+                       mtu_base + MTU_CR(1));
+                writel(1 << 1, mtu_base + MTU_IMSC);
+        } else {
+                /* Generate an interrupt to start the clockevent again */
+                (void) nmdk_clkevt_next(nmdk_cycle, NULL);
+        }
+}
 static void nmdk_clkevt_mode(enum clock_event_mode mode,
                             struct clock_event_device *dev)
 {
-        u32 cr;
        switch (mode) {
        case CLOCK_EVT_MODE_PERIODIC:
-                pr_err("%s: periodic mode not supported\n", __func__);
+                clkevt_periodic = true;
+                nmdk_clkevt_reset();
                break;
        case CLOCK_EVT_MODE_ONESHOT:
-                /* Load highest value, enable device, enable interrupts */
+                clkevt_periodic = false;
-                cr = readl(mtu_base + MTU_CR(1));
-                writel(0, mtu_base + MTU_LR(1));
-                writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(1));
-                writel(1 << 1, mtu_base + MTU_IMSC);
                break;
        case CLOCK_EVT_MODE_SHUTDOWN:
        case CLOCK_EVT_MODE_UNUSED:
-                /* disable irq */
                writel(0, mtu_base + MTU_IMSC);
                /* disable timer */
-                cr = readl(mtu_base + MTU_CR(1));
+                writel(0, mtu_base + MTU_CR(1));
-                cr &= ~MTU_CRn_ENA;
-                writel(cr, mtu_base + MTU_CR(1));
                /* load some high default value */
                writel(0xffffffff, mtu_base + MTU_LR(1));
                break;
@@ -82,16 +155,9 @@ static void nmdk_clkevt_mode(enum clock_event_mode mode,
        }
 }
-static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
-{
-        /* writing the value has immediate effect */
-        writel(evt, mtu_base + MTU_LR(1));
-        return 0;
-}
 static struct clock_event_device nmdk_clkevt = {
        .name           = "mtu_1",
-        .features       = CLOCK_EVT_FEAT_ONESHOT,
+        .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
        .rating         = 200,
        .set_mode       = nmdk_clkevt_mode,
        .set_next_event = nmdk_clkevt_next,
@@ -116,11 +182,23 @@ static struct irqaction nmdk_timer_irq = {
        .dev_id         = &nmdk_clkevt,
 };
+void nmdk_clksrc_reset(void)
+{
+        /* Disable */
+        writel(0, mtu_base + MTU_CR(0));
+        /* ClockSource: configure load and background-load, and fire it up */
+        writel(nmdk_cycle, mtu_base + MTU_LR(0));
+        writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
+        writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA,
+               mtu_base + MTU_CR(0));
+}
 void __init nmdk_timer_init(void)
 {
        unsigned long rate;
        struct clk *clk0;
-        u32 cr = MTU_CRn_32BITS;
        clk0 = clk_get_sys("mtu0", NULL);
        BUG_ON(IS_ERR(clk0));
@@ -138,30 +216,28 @@ void __init nmdk_timer_init(void)
        rate = clk_get_rate(clk0);
        if (rate > 32000000) {
                rate /= 16;
-                cr |= MTU_CRn_PRESCALE_16;
+                clk_prescale = MTU_CRn_PRESCALE_16;
        } else {
-                cr |= MTU_CRn_PRESCALE_1;
+                clk_prescale = MTU_CRn_PRESCALE_1;
        }
+        nmdk_cycle = (rate + HZ/2) / HZ;
        /* Timer 0 is the free running clocksource */
-        writel(cr, mtu_base + MTU_CR(0));
+        nmdk_clksrc_reset();
-        writel(0, mtu_base + MTU_LR(0));
-        writel(0, mtu_base + MTU_BGLR(0));
-        writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0));
        if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",
                        rate, 200, 32, clocksource_mmio_readl_down))
                pr_err("timer: failed to initialize clock source %s\n",
                       "mtu_0");
+#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
        init_sched_clock(&cd, nomadik_update_sched_clock, 32, rate);
+#endif
        /* Timer 1 is used for events */
        clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE);
-        writel(cr | MTU_CRn_ONESHOT, mtu_base + MTU_CR(1)); /* off, currently */
        nmdk_clkevt.max_delta_ns =
                clockevent_delta2ns(0xffffffff, &nmdk_clkevt);
        nmdk_clkevt.min_delta_ns =
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index c46c47afa090..19719329a47b 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -25,54 +25,8 @@
 #include <plat/board.h>
 #include <plat/mmc.h>
 #include <plat/menelaus.h>
-#include <plat/mcbsp.h>
 #include <plat/omap44xx.h>
-/*-------------------------------------------------------------------------*/
-#if defined(CONFIG_OMAP_MCBSP) || defined(CONFIG_OMAP_MCBSP_MODULE)
-static struct platform_device **omap_mcbsp_devices;
-void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
-                        struct omap_mcbsp_platform_data *config, int size)
-{
-        int i;
-        omap_mcbsp_devices = kzalloc(size * sizeof(struct platform_device *),
-                                     GFP_KERNEL);
-        if (!omap_mcbsp_devices) {
-                printk(KERN_ERR "Could not register McBSP devices\n");
-                return;
-        }
-        for (i = 0; i < size; i++) {
-                struct platform_device *new_mcbsp;
-                int ret;
-                new_mcbsp = platform_device_alloc("omap-mcbsp", i + 1);
-                if (!new_mcbsp)
-                        continue;
-                platform_device_add_resources(new_mcbsp, &res[i * res_count],
-                                        res_count);
-                new_mcbsp->dev.platform_data = &config[i];
-                ret = platform_device_add(new_mcbsp);
-                if (ret) {
-                        platform_device_put(new_mcbsp);
-                        continue;
-                }
-                omap_mcbsp_devices[i] = new_mcbsp;
-        }
-}
-#else
-void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
-                        struct omap_mcbsp_platform_data *config, int size)
-{  }
-#endif
-/*-------------------------------------------------------------------------*/
 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
        defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 75a847dd776a..2def4e1990ed 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -3,6 +3,12 @@
 *
 * OMAP Dual-Mode Timers
 *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Tarun Kanti DebBarma <tarun.kanti@ti.com>
+ * Thara Gopinath <thara@ti.com>
+ *
+ * dmtimer adaptation to platform_driver.
+ *
 * Copyright (C) 2005 Nokia Corporation
 * OMAP2 support by Juha Yrjola
 * API improvements and OMAP2 clock framework support by Timo Teras
@@ -29,168 +35,80 @@
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/errno.h>
-#include <linux/list.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
 #include <linux/io.h>
-#include <linux/module.h>
+#include <linux/slab.h>
-#include <mach/hardware.h>
+#include <linux/err.h>
-#include <plat/dmtimer.h>
+#include <linux/pm_runtime.h>
-#include <mach/irqs.h>
-static int dm_timer_count;
-#ifdef CONFIG_ARCH_OMAP1
-static struct omap_dm_timer omap1_dm_timers[] = {
-        { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
-        { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
-        { .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 },
-        { .phys_base = 0xfffb2c00, .irq = INT_1610_GPTIMER4 },
-        { .phys_base = 0xfffb3400, .irq = INT_1610_GPTIMER5 },
-        { .phys_base = 0xfffb3c00, .irq = INT_1610_GPTIMER6 },
-        { .phys_base = 0xfffb7400, .irq = INT_1610_GPTIMER7 },
-        { .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 },
-};
-static const int omap1_dm_timer_count = ARRAY_SIZE(omap1_dm_timers);
-#else
-#define omap1_dm_timers                 NULL
-#define omap1_dm_timer_count            0
-#endif  /* CONFIG_ARCH_OMAP1 */
-#ifdef CONFIG_ARCH_OMAP2
-static struct omap_dm_timer omap2_dm_timers[] = {
-        { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
-        { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 },
-        { .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 },
-        { .phys_base = 0x4807a000, .irq = INT_24XX_GPTIMER4 },
-        { .phys_base = 0x4807c000, .irq = INT_24XX_GPTIMER5 },
-        { .phys_base = 0x4807e000, .irq = INT_24XX_GPTIMER6 },
-        { .phys_base = 0x48080000, .irq = INT_24XX_GPTIMER7 },
-        { .phys_base = 0x48082000, .irq = INT_24XX_GPTIMER8 },
-        { .phys_base = 0x48084000, .irq = INT_24XX_GPTIMER9 },
-        { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
-        { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
-        { .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 },
-};
-static const char *omap2_dm_source_names[] __initdata = {
-        "sys_ck",
-        "func_32k_ck",
-        "alt_ck",
-        NULL
-};
-static struct clk *omap2_dm_source_clocks[3];
-static const int omap2_dm_timer_count = ARRAY_SIZE(omap2_dm_timers);
-#else
-#define omap2_dm_timers                 NULL
-#define omap2_dm_timer_count            0
-#define omap2_dm_source_names           NULL
-#define omap2_dm_source_clocks          NULL
-#endif  /* CONFIG_ARCH_OMAP2 */
-#ifdef CONFIG_ARCH_OMAP3
-static struct omap_dm_timer omap3_dm_timers[] = {
-        { .phys_base = 0x48318000, .irq = INT_24XX_GPTIMER1 },
-        { .phys_base = 0x49032000, .irq = INT_24XX_GPTIMER2 },
-        { .phys_base = 0x49034000, .irq = INT_24XX_GPTIMER3 },
-        { .phys_base = 0x49036000, .irq = INT_24XX_GPTIMER4 },
-        { .phys_base = 0x49038000, .irq = INT_24XX_GPTIMER5 },
-        { .phys_base = 0x4903A000, .irq = INT_24XX_GPTIMER6 },
-        { .phys_base = 0x4903C000, .irq = INT_24XX_GPTIMER7 },
-        { .phys_base = 0x4903E000, .irq = INT_24XX_GPTIMER8 },
-        { .phys_base = 0x49040000, .irq = INT_24XX_GPTIMER9 },
-        { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
-        { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
-        { .phys_base = 0x48304000, .irq = INT_34XX_GPT12_IRQ },
-};
-static const char *omap3_dm_source_names[] __initdata = {
-        "sys_ck",
-        "omap_32k_fck",
-        NULL
-};
-static struct clk *omap3_dm_source_clocks[2];
-static const int omap3_dm_timer_count = ARRAY_SIZE(omap3_dm_timers);
-#else
+#include <plat/dmtimer.h>
-#define omap3_dm_timers                 NULL
-#define omap3_dm_timer_count            0
-#define omap3_dm_source_names           NULL
-#define omap3_dm_source_clocks          NULL
-#endif  /* CONFIG_ARCH_OMAP3 */
-#ifdef CONFIG_ARCH_OMAP4
-static struct omap_dm_timer omap4_dm_timers[] = {
-        { .phys_base = 0x4a318000, .irq = OMAP44XX_IRQ_GPT1 },
-        { .phys_base = 0x48032000, .irq = OMAP44XX_IRQ_GPT2 },
-        { .phys_base = 0x48034000, .irq = OMAP44XX_IRQ_GPT3 },
-        { .phys_base = 0x48036000, .irq = OMAP44XX_IRQ_GPT4 },
-        { .phys_base = 0x40138000, .irq = OMAP44XX_IRQ_GPT5 },
-        { .phys_base = 0x4013a000, .irq = OMAP44XX_IRQ_GPT6 },
-        { .phys_base = 0x4013a000, .irq = OMAP44XX_IRQ_GPT7 },
-        { .phys_base = 0x4013e000, .irq = OMAP44XX_IRQ_GPT8 },
-        { .phys_base = 0x4803e000, .irq = OMAP44XX_IRQ_GPT9 },
-        { .phys_base = 0x48086000, .irq = OMAP44XX_IRQ_GPT10 },
-        { .phys_base = 0x48088000, .irq = OMAP44XX_IRQ_GPT11 },
-        { .phys_base = 0x4a320000, .irq = OMAP44XX_IRQ_GPT12 },
-};
-static const char *omap4_dm_source_names[] __initdata = {
-        "sys_clkin_ck",
-        "sys_32k_ck",
-        NULL
-};
-static struct clk *omap4_dm_source_clocks[2];
-static const int omap4_dm_timer_count = ARRAY_SIZE(omap4_dm_timers);
-#else
-#define omap4_dm_timers                 NULL
-#define omap4_dm_timer_count            0
-#define omap4_dm_source_names           NULL
-#define omap4_dm_source_clocks          NULL
-#endif  /* CONFIG_ARCH_OMAP4 */
-static struct omap_dm_timer *dm_timers;
-static const char **dm_source_names;
-static struct clk **dm_source_clocks;
-static spinlock_t dm_timer_lock;
+static LIST_HEAD(omap_timer_list);
+static DEFINE_SPINLOCK(dm_timer_lock);
-/*
+/**
- * Reads timer registers in posted and non-posted mode. The posted mode bit
+ * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode
- * is encoded in reg. Note that in posted mode write pending bit must be
+ * @timer:      timer pointer over which read operation to perform
- * checked. Otherwise a read of a non completed write will produce an error.
+ * @reg:        lowest byte holds the register offset
+ *
+ * The posted mode bit is encoded in reg. Note that in posted mode write
+ * pending bit must be checked. Otherwise a read of a non completed write
+ * will produce an error.
 */
 static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
 {
-        return __omap_dm_timer_read(timer->io_base, reg, timer->posted);
+        WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
+        return __omap_dm_timer_read(timer, reg, timer->posted);
 }
-/*
+/**
- * Writes timer registers in posted and non-posted mode. The posted mode bit
+ * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode
- * is encoded in reg. Note that in posted mode the write pending bit must be
+ * @timer:      timer pointer over which write operation is to perform
- * checked. Otherwise a write on a register which has a pending write will be
+ * @reg:        lowest byte holds the register offset
- * lost.
+ * @value:      data to write into the register
+ *
+ * The posted mode bit is encoded in reg. Note that in posted mode the write
+ * pending bit must be checked. Otherwise a write on a register which has a
+ * pending write will be lost.
 */
 static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
                                                u32 value)
 {
-        __omap_dm_timer_write(timer->io_base, reg, value, timer->posted);
+        WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
+        __omap_dm_timer_write(timer, reg, value, timer->posted);
+}
+static void omap_timer_restore_context(struct omap_dm_timer *timer)
+{
+        omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_OFFSET,
+                                timer->context.tiocp_cfg);
+        if (timer->revision > 1)
+                __raw_writel(timer->context.tistat, timer->sys_stat);
+        __raw_writel(timer->context.tisr, timer->irq_stat);
+        omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG,
+                                timer->context.twer);
+        omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG,
+                                timer->context.tcrr);
+        omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG,
+                                timer->context.tldr);
+        omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG,
+                                timer->context.tmar);
+        omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
+                                timer->context.tsicr);
+        __raw_writel(timer->context.tier, timer->irq_ena);
+        omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG,
+                                timer->context.tclr);
 }
 static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
 {
        int c;
+        if (!timer->sys_stat)
+                return;
        c = 0;
-        while (!(omap_dm_timer_read_reg(timer, OMAP_TIMER_SYS_STAT_REG) & 1)) {
+        while (!(__raw_readl(timer->sys_stat) & 1)) {
                c++;
                if (c > 100000) {
                        printk(KERN_ERR "Timer failed to reset\n");
@@ -201,53 +119,65 @@ static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
 static void omap_dm_timer_reset(struct omap_dm_timer *timer)
 {
-        int autoidle = 0, wakeup = 0;
+        omap_dm_timer_enable(timer);
+        if (timer->pdev->id != 1) {
-        if (!cpu_class_is_omap2() || timer != &dm_timers[0]) {
                omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
                omap_dm_timer_wait_for_reset(timer);
        }
-        omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
-        /* Enable autoidle on OMAP2+ */
-        if (cpu_class_is_omap2())
-                autoidle = 1;
-        /*
-         * Enable wake-up on OMAP2 CPUs.
-         */
-        if (cpu_class_is_omap2())
-                wakeup = 1;
-        __omap_dm_timer_reset(timer->io_base, autoidle, wakeup);
+        __omap_dm_timer_reset(timer, 0, 0);
+        omap_dm_timer_disable(timer);
        timer->posted = 1;
 }
-void omap_dm_timer_prepare(struct omap_dm_timer *timer)
+int omap_dm_timer_prepare(struct omap_dm_timer *timer)
 {
-        omap_dm_timer_enable(timer);
+        struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
-        omap_dm_timer_reset(timer);
+        int ret;
+        timer->fclk = clk_get(&timer->pdev->dev, "fck");
+        if (WARN_ON_ONCE(IS_ERR_OR_NULL(timer->fclk))) {
+                timer->fclk = NULL;
+                dev_err(&timer->pdev->dev, ": No fclk handle.\n");
+                return -EINVAL;
+        }
+        if (pdata->needs_manual_reset)
+                omap_dm_timer_reset(timer);
+        ret = omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
+        timer->posted = 1;
+        return ret;
 }
 struct omap_dm_timer *omap_dm_timer_request(void)
 {
-        struct omap_dm_timer *timer = NULL;
+        struct omap_dm_timer *timer = NULL, *t;
        unsigned long flags;
-        int i;
+        int ret = 0;
        spin_lock_irqsave(&dm_timer_lock, flags);
-        for (i = 0; i < dm_timer_count; i++) {
+        list_for_each_entry(t, &omap_timer_list, node) {
-                if (dm_timers[i].reserved)
+                if (t->reserved)
                        continue;
-                timer = &dm_timers[i];
+                timer = t;
                timer->reserved = 1;
                break;
        }
+        if (timer) {
+                ret = omap_dm_timer_prepare(timer);
+                if (ret) {
+                        timer->reserved = 0;
+                        timer = NULL;
+                }
+        }
        spin_unlock_irqrestore(&dm_timer_lock, flags);
-        if (timer != NULL)
+        if (!timer)
-                omap_dm_timer_prepare(timer);
+                pr_debug("%s: timer request failed!\n", __func__);
        return timer;
 }
@@ -255,74 +185,65 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_request);
 struct omap_dm_timer *omap_dm_timer_request_specific(int id)
 {
-        struct omap_dm_timer *timer;
+        struct omap_dm_timer *timer = NULL, *t;
        unsigned long flags;
+        int ret = 0;
        spin_lock_irqsave(&dm_timer_lock, flags);
-        if (id <= 0 || id > dm_timer_count || dm_timers[id-1].reserved) {
+        list_for_each_entry(t, &omap_timer_list, node) {
-                spin_unlock_irqrestore(&dm_timer_lock, flags);
+                if (t->pdev->id == id && !t->reserved) {
-                printk("BUG: warning at %s:%d/%s(): unable to get timer %d\n",
+                        timer = t;
-                       __FILE__, __LINE__, __func__, id);
+                        timer->reserved = 1;
-                dump_stack();
+                        break;
-                return NULL;
+                }
        }
-        timer = &dm_timers[id-1];
+        if (timer) {
-        timer->reserved = 1;
+                ret = omap_dm_timer_prepare(timer);
+                if (ret) {
+                        timer->reserved = 0;
+                        timer = NULL;
+                }
+        }
        spin_unlock_irqrestore(&dm_timer_lock, flags);
-        omap_dm_timer_prepare(timer);
+        if (!timer)
+                pr_debug("%s: timer%d request failed!\n", __func__, id);
        return timer;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific);
-void omap_dm_timer_free(struct omap_dm_timer *timer)
+int omap_dm_timer_free(struct omap_dm_timer *timer)
 {
-        omap_dm_timer_enable(timer);
+        if (unlikely(!timer))
-        omap_dm_timer_reset(timer);
+                return -EINVAL;
-        omap_dm_timer_disable(timer);
+        clk_put(timer->fclk);
        WARN_ON(!timer->reserved);
        timer->reserved = 0;
+        return 0;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_free);
 void omap_dm_timer_enable(struct omap_dm_timer *timer)
 {
-        if (timer->enabled)
+        pm_runtime_get_sync(&timer->pdev->dev);
-                return;
-#ifdef CONFIG_ARCH_OMAP2PLUS
-        if (cpu_class_is_omap2()) {
-                clk_enable(timer->fclk);
-                clk_enable(timer->iclk);
-        }
-#endif
-        timer->enabled = 1;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_enable);
 void omap_dm_timer_disable(struct omap_dm_timer *timer)
 {
-        if (!timer->enabled)
+        pm_runtime_put(&timer->pdev->dev);
-                return;
-#ifdef CONFIG_ARCH_OMAP2PLUS
-        if (cpu_class_is_omap2()) {
-                clk_disable(timer->iclk);
-                clk_disable(timer->fclk);
-        }
-#endif
-        timer->enabled = 0;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_disable);
 int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
 {
-        return timer->irq;
+        if (timer)
+                return timer->irq;
+        return -EINVAL;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq);
@@ -334,24 +255,29 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq);
 */
 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 {
-        int i;
+        int i = 0;
+        struct omap_dm_timer *timer = NULL;
+        unsigned long flags;
        /* If ARMXOR cannot be idled this function call is unnecessary */
        if (!(inputmask & (1 << 1)))
                return inputmask;
        /* If any active timer is using ARMXOR return modified mask */
-        for (i = 0; i < dm_timer_count; i++) {
+        spin_lock_irqsave(&dm_timer_lock, flags);
+        list_for_each_entry(timer, &omap_timer_list, node) {
                u32 l;
-                l = omap_dm_timer_read_reg(&dm_timers[i], OMAP_TIMER_CTRL_REG);
+                l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
                if (l & OMAP_TIMER_CTRL_ST) {
                        if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
                                inputmask &= ~(1 << 1);
                        else
                                inputmask &= ~(1 << 2);
                }
+                i++;
        }
+        spin_unlock_irqrestore(&dm_timer_lock, flags);
        return inputmask;
 }
@@ -361,7 +287,9 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
 {
-        return timer->fclk;
+        if (timer)
+                return timer->fclk;
+        return NULL;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk);
@@ -375,70 +303,91 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
 #endif
-void omap_dm_timer_trigger(struct omap_dm_timer *timer)
+int omap_dm_timer_trigger(struct omap_dm_timer *timer)
 {
+        if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
+                pr_err("%s: timer not available or enabled.\n", __func__);
+                return -EINVAL;
+        }
        omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
+        return 0;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_trigger);
-void omap_dm_timer_start(struct omap_dm_timer *timer)
+int omap_dm_timer_start(struct omap_dm_timer *timer)
 {
        u32 l;
+        if (unlikely(!timer))
+                return -EINVAL;
+        omap_dm_timer_enable(timer);
+        if (timer->loses_context) {
+                u32 ctx_loss_cnt_after =
+                        timer->get_context_loss_count(&timer->pdev->dev);
+                if (ctx_loss_cnt_after != timer->ctx_loss_count)
+                        omap_timer_restore_context(timer);
+        }
        l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
        if (!(l & OMAP_TIMER_CTRL_ST)) {
                l |= OMAP_TIMER_CTRL_ST;
                omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
        }
+        /* Save the context */
+        timer->context.tclr = l;
+        return 0;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_start);
-void omap_dm_timer_stop(struct omap_dm_timer *timer)
+int omap_dm_timer_stop(struct omap_dm_timer *timer)
 {
        unsigned long rate = 0;
+        struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
-#ifdef CONFIG_ARCH_OMAP2PLUS
+        if (unlikely(!timer))
-        rate = clk_get_rate(timer->fclk);
+                return -EINVAL;
-#endif
-        __omap_dm_timer_stop(timer->io_base, timer->posted, rate);
+        if (!pdata->needs_manual_reset)
+                rate = clk_get_rate(timer->fclk);
+        __omap_dm_timer_stop(timer, timer->posted, rate);
+        return 0;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
-#ifdef CONFIG_ARCH_OMAP1
 int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
 {
-        int n = (timer - dm_timers) << 1;
+        int ret;
-        u32 l;
+        struct dmtimer_platform_data *pdata;
-        l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
-        l |= source << n;
-        omap_writel(l, MOD_CONF_CTRL_1);
-        return 0;
+        if (unlikely(!timer))
-}
+                return -EINVAL;
-EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
-#else
+        pdata = timer->pdev->dev.platform_data;
-int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
-{
        if (source < 0 || source >= 3)
                return -EINVAL;
-        return __omap_dm_timer_set_source(timer->fclk,
+        ret = pdata->set_timer_src(timer->pdev, source);
-                                                dm_source_clocks[source]);
+        return ret;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
-#endif
+int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
-void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
                            unsigned int load)
 {
        u32 l;
+        if (unlikely(!timer))
+                return -EINVAL;
+        omap_dm_timer_enable(timer);
        l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
        if (autoreload)
                l |= OMAP_TIMER_CTRL_AR;
@@ -448,15 +397,32 @@ void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
        omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
        omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
+        /* Save the context */
+        timer->context.tclr = l;
+        timer->context.tldr = load;
+        omap_dm_timer_disable(timer);
+        return 0;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_set_load);
 /* Optimized set_load which removes costly spin wait in timer_start */
-void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
+int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
                            unsigned int load)
 {
        u32 l;
+        if (unlikely(!timer))
+                return -EINVAL;
+        omap_dm_timer_enable(timer);
+        if (timer->loses_context) {
+                u32 ctx_loss_cnt_after =
+                        timer->get_context_loss_count(&timer->pdev->dev);
+                if (ctx_loss_cnt_after != timer->ctx_loss_count)
+                        omap_timer_restore_context(timer);
+        }
        l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
        if (autoreload) {
                l |= OMAP_TIMER_CTRL_AR;
@@ -466,15 +432,25 @@ void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
        }
        l |= OMAP_TIMER_CTRL_ST;
-        __omap_dm_timer_load_start(timer->io_base, l, load, timer->posted);
+        __omap_dm_timer_load_start(timer, l, load, timer->posted);
+        /* Save the context */
+        timer->context.tclr = l;
+        timer->context.tldr = load;
+        timer->context.tcrr = load;
+        return 0;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start);
-void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
+int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
                             unsigned int match)
 {
        u32 l;
+        if (unlikely(!timer))
+                return -EINVAL;
+        omap_dm_timer_enable(timer);
        l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
        if (enable)
                l |= OMAP_TIMER_CTRL_CE;
@@ -482,14 +458,24 @@ void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
                l &= ~OMAP_TIMER_CTRL_CE;
        omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
        omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
+        /* Save the context */
+        timer->context.tclr = l;
+        timer->context.tmar = match;
+        omap_dm_timer_disable(timer);
+        return 0;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_set_match);
-void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
+int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
                           int toggle, int trigger)
 {
        u32 l;
+        if (unlikely(!timer))
+                return -EINVAL;
+        omap_dm_timer_enable(timer);
        l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
        l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
               OMAP_TIMER_CTRL_PT | (0x03 << 10));
@@ -499,13 +485,22 @@ void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
                l |= OMAP_TIMER_CTRL_PT;
        l |= trigger << 10;
        omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
+        /* Save the context */
+        timer->context.tclr = l;
+        omap_dm_timer_disable(timer);
+        return 0;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_set_pwm);
-void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
+int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
 {
        u32 l;
+        if (unlikely(!timer))
+                return -EINVAL;
+        omap_dm_timer_enable(timer);
        l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
        l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
        if (prescaler >= 0x00 && prescaler <= 0x07) {
@@ -513,13 +508,28 @@ void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
                l |= prescaler << 2;
        }
        omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
+        /* Save the context */
+        timer->context.tclr = l;
+        omap_dm_timer_disable(timer);
+        return 0;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler);
-void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
+int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
                                  unsigned int value)
 {
-        __omap_dm_timer_int_enable(timer->io_base, value);
+        if (unlikely(!timer))
+                return -EINVAL;
+        omap_dm_timer_enable(timer);
+        __omap_dm_timer_int_enable(timer, value);
+        /* Save the context */
+        timer->context.tier = value;
+        timer->context.twer = value;
+        omap_dm_timer_disable(timer);
+        return 0;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable);
@@ -527,40 +537,61 @@ unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
 {
        unsigned int l;
-        l = omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG);
+        if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
+                pr_err("%s: timer not available or enabled.\n", __func__);
+                return 0;
+        }
+        l = __raw_readl(timer->irq_stat);
        return l;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_read_status);
-void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
+int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
 {
-        __omap_dm_timer_write_status(timer->io_base, value);
+        if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev)))
+                return -EINVAL;
+        __omap_dm_timer_write_status(timer, value);
+        /* Save the context */
+        timer->context.tisr = value;
+        return 0;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_write_status);
 unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
 {
-        return __omap_dm_timer_read_counter(timer->io_base, timer->posted);
+        if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
+                pr_err("%s: timer not iavailable or enabled.\n", __func__);
+                return 0;
+        }
+        return __omap_dm_timer_read_counter(timer, timer->posted);
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter);
-void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
+int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
 {
+        if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
+                pr_err("%s: timer not available or enabled.\n", __func__);
+                return -EINVAL;
+        }
        omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
+        /* Save the context */
+        timer->context.tcrr = value;
+        return 0;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter);
 int omap_dm_timers_active(void)
 {
-        int i;
+        struct omap_dm_timer *timer;
-        for (i = 0; i < dm_timer_count; i++) {
-                struct omap_dm_timer *timer;
-                timer = &dm_timers[i];
-                if (!timer->enabled)
+        list_for_each_entry(timer, &omap_timer_list, node) {
+                if (!timer->reserved)
                        continue;
                if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
@@ -572,69 +603,147 @@ int omap_dm_timers_active(void)
 }
 EXPORT_SYMBOL_GPL(omap_dm_timers_active);
-static int __init omap_dm_timer_init(void)
+/**
+ * omap_dm_timer_probe - probe function called for every registered device
+ * @pdev:       pointer to current timer platform device
+ *
+ * Called by driver framework at the end of device registration for all
+ * timer devices.
+ */
+static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
 {
+        int ret;
+        unsigned long flags;
        struct omap_dm_timer *timer;
-        int i, map_size = SZ_8K;        /* Module 4KB + L4 4KB except on omap1 */
+        struct resource *mem, *irq, *ioarea;
+        struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
-        if (!(cpu_is_omap16xx() || cpu_class_is_omap2()))
+        if (!pdata) {
+                dev_err(&pdev->dev, "%s: no platform data.\n", __func__);
                return -ENODEV;
+        }
-        spin_lock_init(&dm_timer_lock);
+        irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+        if (unlikely(!irq)) {
-        if (cpu_class_is_omap1()) {
+                dev_err(&pdev->dev, "%s: no IRQ resource.\n", __func__);
-                dm_timers = omap1_dm_timers;
+                return -ENODEV;
-                dm_timer_count = omap1_dm_timer_count;
-                map_size = SZ_2K;
-        } else if (cpu_is_omap24xx()) {
-                dm_timers = omap2_dm_timers;
-                dm_timer_count = omap2_dm_timer_count;
-                dm_source_names = omap2_dm_source_names;
-                dm_source_clocks = omap2_dm_source_clocks;
-        } else if (cpu_is_omap34xx()) {
-                dm_timers = omap3_dm_timers;
-                dm_timer_count = omap3_dm_timer_count;
-                dm_source_names = omap3_dm_source_names;
-                dm_source_clocks = omap3_dm_source_clocks;
-        } else if (cpu_is_omap44xx()) {
-                dm_timers = omap4_dm_timers;
-                dm_timer_count = omap4_dm_timer_count;
-                dm_source_names = omap4_dm_source_names;
-                dm_source_clocks = omap4_dm_source_clocks;
        }
-        if (cpu_class_is_omap2())
+        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-                for (i = 0; dm_source_names[i] != NULL; i++)
+        if (unlikely(!mem)) {
-                        dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]);
+                dev_err(&pdev->dev, "%s: no memory resource.\n", __func__);
+                return -ENODEV;
+        }
-        if (cpu_is_omap243x())
+        ioarea = request_mem_region(mem->start, resource_size(mem),
-                dm_timers[0].phys_base = 0x49018000;
+                        pdev->name);
+        if (!ioarea) {
+                dev_err(&pdev->dev, "%s: region already claimed.\n", __func__);
+                return -EBUSY;
+        }
-        for (i = 0; i < dm_timer_count; i++) {
+        timer = kzalloc(sizeof(struct omap_dm_timer), GFP_KERNEL);
-                timer = &dm_timers[i];
+        if (!timer) {
+                dev_err(&pdev->dev, "%s: no memory for omap_dm_timer.\n",
+                        __func__);
+                ret = -ENOMEM;
+                goto err_free_ioregion;
+        }
-                /* Static mapping, never released */
+        timer->io_base = ioremap(mem->start, resource_size(mem));
-                timer->io_base = ioremap(timer->phys_base, map_size);
+        if (!timer->io_base) {
-                BUG_ON(!timer->io_base);
+                dev_err(&pdev->dev, "%s: ioremap failed.\n", __func__);
+                ret = -ENOMEM;
+                goto err_free_mem;
+        }
-#ifdef CONFIG_ARCH_OMAP2PLUS
+        timer->id = pdev->id;
-                if (cpu_class_is_omap2()) {
+        timer->irq = irq->start;
-                        char clk_name[16];
+        timer->reserved = pdata->reserved;
-                        sprintf(clk_name, "gpt%d_ick", i + 1);
+        timer->pdev = pdev;
-                        timer->iclk = clk_get(NULL, clk_name);
+        timer->loses_context = pdata->loses_context;
-                        sprintf(clk_name, "gpt%d_fck", i + 1);
+        timer->get_context_loss_count = pdata->get_context_loss_count;
-                        timer->fclk = clk_get(NULL, clk_name);
-                }
+        /* Skip pm_runtime_enable for OMAP1 */
+        if (!pdata->needs_manual_reset) {
+                pm_runtime_enable(&pdev->dev);
+                pm_runtime_irq_safe(&pdev->dev);
+        }
-                /* One or two timers may be set up early for sys_timer */
+        if (!timer->reserved) {
-                if (sys_timer_reserved & (1  << i)) {
+                pm_runtime_get_sync(&pdev->dev);
-                        timer->reserved = 1;
+                __omap_dm_timer_init_regs(timer);
-                        timer->posted = 1;
+                pm_runtime_put(&pdev->dev);
-                }
-#endif
        }
+        /* add the timer element to the list */
+        spin_lock_irqsave(&dm_timer_lock, flags);
+        list_add_tail(&timer->node, &omap_timer_list);
+        spin_unlock_irqrestore(&dm_timer_lock, flags);
+        dev_dbg(&pdev->dev, "Device Probed.\n");
        return 0;
+err_free_mem:
+        kfree(timer);
+err_free_ioregion:
+        release_mem_region(mem->start, resource_size(mem));
+        return ret;
 }
-arch_initcall(omap_dm_timer_init);
+/**
+ * omap_dm_timer_remove - cleanup a registered timer device
+ * @pdev:       pointer to current timer platform device
+ *
+ * Called by driver framework whenever a timer device is unregistered.
+ * In addition to freeing platform resources it also deletes the timer
+ * entry from the local list.
+ */
+static int __devexit omap_dm_timer_remove(struct platform_device *pdev)
+{
+        struct omap_dm_timer *timer;
+        unsigned long flags;
+        int ret = -EINVAL;
+        spin_lock_irqsave(&dm_timer_lock, flags);
+        list_for_each_entry(timer, &omap_timer_list, node)
+                if (timer->pdev->id == pdev->id) {
+                        list_del(&timer->node);
+                        kfree(timer);
+                        ret = 0;
+                        break;
+                }
+        spin_unlock_irqrestore(&dm_timer_lock, flags);
+        return ret;
+}
+static struct platform_driver omap_dm_timer_driver = {
+        .probe  = omap_dm_timer_probe,
+        .remove = __devexit_p(omap_dm_timer_remove),
+        .driver = {
+                .name   = "omap_timer",
+        },
+};
+static int __init omap_dm_timer_driver_init(void)
+{
+        return platform_driver_register(&omap_dm_timer_driver);
+}
+static void __exit omap_dm_timer_driver_exit(void)
+{
+        platform_driver_unregister(&omap_dm_timer_driver);
+}
+early_platform_init("earlytimer", &omap_dm_timer_driver);
+module_init(omap_dm_timer_driver_init);
+module_exit(omap_dm_timer_driver_exit);
+MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRIVER_NAME);
+MODULE_AUTHOR("Texas Instruments Inc");
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index 2388b8eebaaa..679cbd49c019 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -139,19 +139,11 @@ static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t)
        omap_pm_set_max_mpu_wakeup_lat(dev, t);
 }
-static struct omap_device_pm_latency omap_i2c_latency[] = {
-        [0] = {
-                .deactivate_func        = omap_device_idle_hwmods,
-                .activate_func          = omap_device_enable_hwmods,
-                .flags                  = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
-        },
-};
 static inline int omap2_i2c_add_bus(int bus_id)
 {
        int l;
        struct omap_hwmod *oh;
-        struct omap_device *od;
+        struct platform_device *pdev;
        char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN];
        struct omap_i2c_bus_platform_data *pdata;
        struct omap_i2c_dev_attr *dev_attr;
@@ -187,12 +179,12 @@ static inline int omap2_i2c_add_bus(int bus_id)
         */
        if (cpu_is_omap34xx())
                pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
-        od = omap_device_build(name, bus_id, oh, pdata,
+        pdev = omap_device_build(name, bus_id, oh, pdata,
                        sizeof(struct omap_i2c_bus_platform_data),
-                        omap_i2c_latency, ARRAY_SIZE(omap_i2c_latency), 0);
+                        NULL, 0, 0);
-        WARN(IS_ERR(od), "Could not build omap_device for %s\n", name);
+        WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", name);
-        return PTR_ERR(od);
+        return PTR_ERR(pdev);
 }
 #else
 static inline int omap2_i2c_add_bus(int bus_id)
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index df4b9683f17f..197ca03c3f7d 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -80,8 +80,6 @@ struct clkops {
 *
 * @div is the divisor that should be applied to the parent clock's rate
 * to produce the current clock's rate.
- *
- * XXX @flags probably should be replaced with an struct omap_chip.
 */
 struct clksel_rate {
        u32                     val;
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 4564cc697d7f..c50df4814f6f 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -45,6 +45,18 @@ extern unsigned long long notrace omap_32k_sched_clock(void);
 extern void omap_reserve(void);
+void omap2420_init_early(void);
+void omap2430_init_early(void);
+void omap3430_init_early(void);
+void omap35xx_init_early(void);
+void omap3630_init_early(void);
+void omap3_init_early(void);    /* Do not use this one */
+void am35xx_init_early(void);
+void ti816x_init_early(void);
+void omap4430_init_early(void);
+void omap_sram_init(void);
 /*
 * IO bases for various OMAP processors
 * Except the tap base, rest all the io bases
@@ -53,13 +65,13 @@ extern void omap_reserve(void);
 struct omap_globals {
        u32             class;          /* OMAP class to detect */
        void __iomem    *tap;           /* Control module ID code */
-        unsigned long   sdrc;           /* SDRAM Controller */
+        void __iomem    *sdrc;           /* SDRAM Controller */
-        unsigned long   sms;            /* SDRAM Memory Scheduler */
+        void __iomem    *sms;            /* SDRAM Memory Scheduler */
-        unsigned long   ctrl;           /* System Control Module */
+        void __iomem    *ctrl;           /* System Control Module */
-        unsigned long   ctrl_pad;       /* PAD Control Module */
+        void __iomem    *ctrl_pad;      /* PAD Control Module */
-        unsigned long   prm;            /* Power and Reset Management */
+        void __iomem    *prm;            /* Power and Reset Management */
-        unsigned long   cm;             /* Clock Management */
+        void __iomem    *cm;             /* Clock Management */
-        unsigned long   cm2;
+        void __iomem    *cm2;
 };
 void omap2_set_globals_242x(void);
@@ -74,7 +86,11 @@ void omap2_set_globals_sdrc(struct omap_globals *);
 void omap2_set_globals_control(struct omap_globals *);
 void omap2_set_globals_prcm(struct omap_globals *);
+void omap242x_map_io(void);
+void omap243x_map_io(void);
 void omap3_map_io(void);
+void omap4_map_io(void);
 /**
 * omap_test_timeout - busy-loop, testing a condition
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 67b3d75884cd..2f9026942229 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -44,13 +44,6 @@
 int omap_type(void);
-struct omap_chip_id {
-        u16 oc;
-        u8 type;
-};
-#define OMAP_CHIP_INIT(x)       { .oc = x }
 /*
 * omap_rev bits:
 * CPU id bits  (0730, 1510, 1710, 2422...)     [31:16]
@@ -60,19 +53,6 @@ struct omap_chip_id {
 unsigned int omap_rev(void);
 /*
- * Define CPU revision bits
- *
- * Verbose meaning of the revision bits may be different for a silicon
- * family. This difference can be handled separately.
- */
-#define OMAP_REVBITS_00         0x00
-#define OMAP_REVBITS_01         0x01
-#define OMAP_REVBITS_02         0x02
-#define OMAP_REVBITS_03         0x03
-#define OMAP_REVBITS_04         0x04
-#define OMAP_REVBITS_05         0x05
-/*
 * Get the CPU revision for OMAP devices
 */
 #define GET_OMAP_REVISION()     ((omap_rev() >> 8) & 0xff)
@@ -262,7 +242,7 @@ IS_OMAP_TYPE(2422, 0x2422)
 IS_OMAP_TYPE(2423, 0x2423)
 IS_OMAP_TYPE(2430, 0x2430)
 IS_OMAP_TYPE(3430, 0x3430)
-IS_OMAP_TYPE(3505, 0x3505)
+IS_OMAP_TYPE(3505, 0x3517)
 IS_OMAP_TYPE(3517, 0x3517)
 #define cpu_is_omap310()                0
@@ -354,8 +334,9 @@ IS_OMAP_TYPE(3517, 0x3517)
                                                (!omap3_has_sgx()) &&   \
                                                (omap3_has_iva()))
 # define cpu_is_omap3530()              (cpu_is_omap3430())
-# define cpu_is_omap3505()              is_omap3505()
 # define cpu_is_omap3517()              is_omap3517()
+# define cpu_is_omap3505()              (cpu_is_omap3517() &&           \
+                                                !omap3_has_sgx())
 # undef cpu_is_omap3630
 # define cpu_is_omap3630()              is_omap363x()
 # define cpu_is_ti816x()                is_ti816x()
@@ -379,35 +360,31 @@ IS_OMAP_TYPE(3517, 0x3517)
 /* Various silicon revisions for omap2 */
 #define OMAP242X_CLASS          0x24200024
 #define OMAP2420_REV_ES1_0      OMAP242X_CLASS
-#define OMAP2420_REV_ES2_0      (OMAP242X_CLASS | (OMAP_REVBITS_01 << 8))
+#define OMAP2420_REV_ES2_0      (OMAP242X_CLASS | (0x1 << 8))
 #define OMAP243X_CLASS          0x24300024
 #define OMAP2430_REV_ES1_0      OMAP243X_CLASS
 #define OMAP343X_CLASS          0x34300034
 #define OMAP3430_REV_ES1_0      OMAP343X_CLASS
-#define OMAP3430_REV_ES2_0      (OMAP343X_CLASS | (OMAP_REVBITS_01 << 8))
+#define OMAP3430_REV_ES2_0      (OMAP343X_CLASS | (0x1 << 8))
-#define OMAP3430_REV_ES2_1      (OMAP343X_CLASS | (OMAP_REVBITS_02 << 8))
+#define OMAP3430_REV_ES2_1      (OMAP343X_CLASS | (0x2 << 8))
-#define OMAP3430_REV_ES3_0      (OMAP343X_CLASS | (OMAP_REVBITS_03 << 8))
+#define OMAP3430_REV_ES3_0      (OMAP343X_CLASS | (0x3 << 8))
-#define OMAP3430_REV_ES3_1      (OMAP343X_CLASS | (OMAP_REVBITS_04 << 8))
+#define OMAP3430_REV_ES3_1      (OMAP343X_CLASS | (0x4 << 8))
-#define OMAP3430_REV_ES3_1_2    (OMAP343X_CLASS | (OMAP_REVBITS_05 << 8))
+#define OMAP3430_REV_ES3_1_2    (OMAP343X_CLASS | (0x5 << 8))
 #define OMAP363X_CLASS          0x36300034
 #define OMAP3630_REV_ES1_0      OMAP363X_CLASS
-#define OMAP3630_REV_ES1_1      (OMAP363X_CLASS | (OMAP_REVBITS_01 << 8))
+#define OMAP3630_REV_ES1_1      (OMAP363X_CLASS | (0x1 << 8))
-#define OMAP3630_REV_ES1_2      (OMAP363X_CLASS | (OMAP_REVBITS_02 << 8))
+#define OMAP3630_REV_ES1_2      (OMAP363X_CLASS | (0x2 << 8))
-#define OMAP35XX_CLASS          0x35000034
+#define OMAP3517_CLASS          0x35170034
-#define OMAP3503_REV(v)         (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8))
+#define OMAP3517_REV_ES1_0      OMAP3517_CLASS
-#define OMAP3515_REV(v)         (OMAP35XX_CLASS | (0x3515 << 16) | (v << 8))
+#define OMAP3517_REV_ES1_1      (OMAP3517_CLASS | (0x1 << 8))
-#define OMAP3525_REV(v)         (OMAP35XX_CLASS | (0x3525 << 16) | (v << 8))
-#define OMAP3530_REV(v)         (OMAP35XX_CLASS | (0x3530 << 16) | (v << 8))
-#define OMAP3505_REV(v)         (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8))
-#define OMAP3517_REV(v)         (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8))
 #define TI816X_CLASS            0x81600034
 #define TI8168_REV_ES1_0        TI816X_CLASS
-#define TI8168_REV_ES1_1        (TI816X_CLASS | (OMAP_REVBITS_01 << 8))
+#define TI8168_REV_ES1_1        (TI816X_CLASS | (0x1 << 8))
 #define OMAP443X_CLASS          0x44300044
 #define OMAP4430_REV_ES1_0      (OMAP443X_CLASS | (0x10 << 8))
@@ -418,61 +395,6 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define OMAP446X_CLASS          0x44600044
 #define OMAP4460_REV_ES1_0      (OMAP446X_CLASS | (0x10 << 8))
-/*
- * omap_chip bits
- *
- * CHIP_IS_OMAP{2420,2430,3430} indicate that a particular structure is
- * valid on all chips of that type.  CHIP_IS_OMAP3430ES{1,2} indicates
- * something that is only valid on that particular ES revision.
- *
- * These bits may be ORed together to indicate structures that are
- * available on multiple chip types.
- *
- * To test whether a particular structure matches the current OMAP chip type,
- * use omap_chip_is().
- *
- */
-#define CHIP_IS_OMAP2420                (1 << 0)
-#define CHIP_IS_OMAP2430                (1 << 1)
-#define CHIP_IS_OMAP3430                (1 << 2)
-#define CHIP_IS_OMAP3430ES1             (1 << 3)
-#define CHIP_IS_OMAP3430ES2             (1 << 4)
-#define CHIP_IS_OMAP3430ES3_0           (1 << 5)
-#define CHIP_IS_OMAP3430ES3_1           (1 << 6)
-#define CHIP_IS_OMAP3630ES1             (1 << 7)
-#define CHIP_IS_OMAP4430ES1             (1 << 8)
-#define CHIP_IS_OMAP3630ES1_1           (1 << 9)
-#define CHIP_IS_OMAP3630ES1_2           (1 << 10)
-#define CHIP_IS_OMAP4430ES2             (1 << 11)
-#define CHIP_IS_OMAP4430ES2_1           (1 << 12)
-#define CHIP_IS_OMAP4430ES2_2           (1 << 13)
-#define CHIP_IS_TI816X                  (1 << 14)
-#define CHIP_IS_OMAP4460ES1_0           (1 << 15)
-#define CHIP_IS_OMAP24XX                (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
-#define CHIP_IS_OMAP4430                (CHIP_IS_OMAP4430ES1 |          \
-                                         CHIP_IS_OMAP4430ES2 |          \
-                                         CHIP_IS_OMAP4430ES2_1 |        \
-                                         CHIP_IS_OMAP4430ES2_2 |        \
-                                         CHIP_IS_OMAP4460ES1_0)
-/*
- * "GE" here represents "greater than or equal to" in terms of ES
- * levels.  So CHIP_GE_OMAP3430ES2 is intended to match all OMAP3430
- * chips at ES2 and beyond, but not, for example, any OMAP lines after
- * OMAP3.
- */
-#define CHIP_GE_OMAP3430ES2             (CHIP_IS_OMAP3430ES2 | \
-                                         CHIP_IS_OMAP3430ES3_0 | \
-                                         CHIP_GE_OMAP3430ES3_1)
-#define CHIP_GE_OMAP3430ES3_1           (CHIP_IS_OMAP3430ES3_1 | \
-                                         CHIP_IS_OMAP3630ES1 | \
-                                         CHIP_GE_OMAP3630ES1_1)
-#define CHIP_GE_OMAP3630ES1_1           (CHIP_IS_OMAP3630ES1_1 | \
-                                         CHIP_IS_OMAP3630ES1_2)
-int omap_chip_is(struct omap_chip_id oci);
 void omap2_check_revision(void);
 /*
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index eb5d16c60cd9..d11025e6e7a4 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -1,5 +1,5 @@
 /*
- * arch/arm/plat-omap/include/mach/dmtimer.h
+ * arch/arm/plat-omap/include/plat/dmtimer.h
 *
 * OMAP Dual-Mode Timers
 *
@@ -35,6 +35,7 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/io.h>
+#include <linux/platform_device.h>
 #ifndef __ASM_ARCH_DMTIMER_H
 #define __ASM_ARCH_DMTIMER_H
@@ -59,12 +60,56 @@
 * in OMAP4 can be distinguished.
 */
 #define OMAP_TIMER_IP_VERSION_1                        0x1
+/* timer capabilities used in hwmod database */
+#define OMAP_TIMER_SECURE                               0x80000000
+#define OMAP_TIMER_ALWON                                0x40000000
+#define OMAP_TIMER_HAS_PWM                              0x20000000
+struct omap_timer_capability_dev_attr {
+        u32 timer_capability;
+};
 struct omap_dm_timer;
 struct clk;
+struct timer_regs {
+        u32 tidr;
+        u32 tiocp_cfg;
+        u32 tistat;
+        u32 tisr;
+        u32 tier;
+        u32 twer;
+        u32 tclr;
+        u32 tcrr;
+        u32 tldr;
+        u32 ttrg;
+        u32 twps;
+        u32 tmar;
+        u32 tcar1;
+        u32 tsicr;
+        u32 tcar2;
+        u32 tpir;
+        u32 tnir;
+        u32 tcvr;
+        u32 tocr;
+        u32 towr;
+};
+struct dmtimer_platform_data {
+        int (*set_timer_src)(struct platform_device *pdev, int source);
+        int timer_ip_version;
+        u32 needs_manual_reset:1;
+        bool reserved;
+        bool loses_context;
+        u32 (*get_context_loss_count)(struct device *dev);
+};
 struct omap_dm_timer *omap_dm_timer_request(void);
 struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
-void omap_dm_timer_free(struct omap_dm_timer *timer);
+int omap_dm_timer_free(struct omap_dm_timer *timer);
 void omap_dm_timer_enable(struct omap_dm_timer *timer);
 void omap_dm_timer_disable(struct omap_dm_timer *timer);
@@ -73,23 +118,23 @@ int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
 u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
-void omap_dm_timer_trigger(struct omap_dm_timer *timer);
+int omap_dm_timer_trigger(struct omap_dm_timer *timer);
-void omap_dm_timer_start(struct omap_dm_timer *timer);
+int omap_dm_timer_start(struct omap_dm_timer *timer);
-void omap_dm_timer_stop(struct omap_dm_timer *timer);
+int omap_dm_timer_stop(struct omap_dm_timer *timer);
 int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
-void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
+int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
-void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
+int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
-void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
+int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
-void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
+int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
-void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
+int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
-void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
+int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
 unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
-void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
+int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
 unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
-void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
+int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
 int omap_dm_timers_active(void);
@@ -98,12 +143,30 @@ int omap_dm_timers_active(void);
 * used by dmtimer.c and sys_timer related code.
 */
-/* register offsets */
+/*
-#define _OMAP_TIMER_ID_OFFSET           0x00
+ * The interrupt registers are different between v1 and v2 ip.
-#define _OMAP_TIMER_OCP_CFG_OFFSET      0x10
+ * These registers are offsets from timer->iobase.
-#define _OMAP_TIMER_SYS_STAT_OFFSET     0x14
+ */
-#define _OMAP_TIMER_STAT_OFFSET         0x18
+#define OMAP_TIMER_ID_OFFSET            0x00
-#define _OMAP_TIMER_INT_EN_OFFSET       0x1c
+#define OMAP_TIMER_OCP_CFG_OFFSET       0x10
+#define OMAP_TIMER_V1_SYS_STAT_OFFSET   0x14
+#define OMAP_TIMER_V1_STAT_OFFSET       0x18
+#define OMAP_TIMER_V1_INT_EN_OFFSET     0x1c
+#define OMAP_TIMER_V2_IRQSTATUS_RAW     0x24
+#define OMAP_TIMER_V2_IRQSTATUS         0x28
+#define OMAP_TIMER_V2_IRQENABLE_SET     0x2c
+#define OMAP_TIMER_V2_IRQENABLE_CLR     0x30
+/*
+ * The functional registers have a different base on v1 and v2 ip.
+ * These registers are offsets from timer->func_base. The func_base
+ * is samae as io_base for v1 and io_base + 0x14 for v2 ip.
+ *
+ */
+#define OMAP_TIMER_V2_FUNC_OFFSET               0x14
 #define _OMAP_TIMER_WAKEUP_EN_OFFSET    0x20
 #define _OMAP_TIMER_CTRL_OFFSET         0x24
 #define         OMAP_TIMER_CTRL_GPOCFG          (1 << 14)
@@ -147,21 +210,6 @@ int omap_dm_timers_active(void);
 /* register offsets with the write pending bit encoded */
 #define WPSHIFT                                 16
-#define OMAP_TIMER_ID_REG                       (_OMAP_TIMER_ID_OFFSET \
-                                                        | (WP_NONE << WPSHIFT))
-#define OMAP_TIMER_OCP_CFG_REG                  (_OMAP_TIMER_OCP_CFG_OFFSET \
-                                                        | (WP_NONE << WPSHIFT))
-#define OMAP_TIMER_SYS_STAT_REG                 (_OMAP_TIMER_SYS_STAT_OFFSET \
-                                                        | (WP_NONE << WPSHIFT))
-#define OMAP_TIMER_STAT_REG                     (_OMAP_TIMER_STAT_OFFSET \
-                                                        | (WP_NONE << WPSHIFT))
-#define OMAP_TIMER_INT_EN_REG                   (_OMAP_TIMER_INT_EN_OFFSET \
-                                                        | (WP_NONE << WPSHIFT))
 #define OMAP_TIMER_WAKEUP_EN_REG                (_OMAP_TIMER_WAKEUP_EN_OFFSET \
                                                        | (WP_NONE << WPSHIFT))
@@ -209,49 +257,88 @@ int omap_dm_timers_active(void);
 struct omap_dm_timer {
        unsigned long phys_base;
+        int id;
        int irq;
-#ifdef CONFIG_ARCH_OMAP2PLUS
        struct clk *iclk, *fclk;
-#endif
-        void __iomem *io_base;
+        void __iomem    *io_base;
+        void __iomem    *sys_stat;      /* TISTAT timer status */
+        void __iomem    *irq_stat;      /* TISR/IRQSTATUS interrupt status */
+        void __iomem    *irq_ena;       /* irq enable */
+        void __iomem    *irq_dis;       /* irq disable, only on v2 ip */
+        void __iomem    *pend;          /* write pending */
+        void __iomem    *func_base;     /* function register base */
        unsigned long rate;
        unsigned reserved:1;
-        unsigned enabled:1;
        unsigned posted:1;
+        struct timer_regs context;
+        bool loses_context;
+        int ctx_loss_count;
+        int revision;
+        struct platform_device *pdev;
+        struct list_head node;
+        u32 (*get_context_loss_count)(struct device *dev);
 };
-extern u32 sys_timer_reserved;
+int omap_dm_timer_prepare(struct omap_dm_timer *timer);
-void omap_dm_timer_prepare(struct omap_dm_timer *timer);
-static inline u32 __omap_dm_timer_read(void __iomem *base, u32 reg,
+static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
                                                int posted)
 {
        if (posted)
-                while (__raw_readl(base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
+                while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
-                                & (reg >> WPSHIFT))
                        cpu_relax();
-        return __raw_readl(base + (reg & 0xff));
+        return __raw_readl(timer->func_base + (reg & 0xff));
 }
-static inline void __omap_dm_timer_write(void __iomem *base, u32 reg, u32 val,
+static inline void __omap_dm_timer_write(struct omap_dm_timer *timer,
-                                                int posted)
+                                        u32 reg, u32 val, int posted)
 {
        if (posted)
-                while (__raw_readl(base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
+                while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
-                                & (reg >> WPSHIFT))
                        cpu_relax();
-        __raw_writel(val, base + (reg & 0xff));
+        __raw_writel(val, timer->func_base + (reg & 0xff));
+}
+static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
+{
+        u32 tidr;
+        /* Assume v1 ip if bits [31:16] are zero */
+        tidr = __raw_readl(timer->io_base);
+        if (!(tidr >> 16)) {
+                timer->revision = 1;
+                timer->sys_stat = timer->io_base +
+                                OMAP_TIMER_V1_SYS_STAT_OFFSET;
+                timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
+                timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
+                timer->irq_dis = 0;
+                timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
+                timer->func_base = timer->io_base;
+        } else {
+                timer->revision = 2;
+                timer->sys_stat = 0;
+                timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
+                timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
+                timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;
+                timer->pend = timer->io_base +
+                        _OMAP_TIMER_WRITE_PEND_OFFSET +
+                                OMAP_TIMER_V2_FUNC_OFFSET;
+                timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET;
+        }
 }
 /* Assumes the source clock has been set by caller */
-static inline void __omap_dm_timer_reset(void __iomem *base, int autoidle,
+static inline void __omap_dm_timer_reset(struct omap_dm_timer *timer,
-                                                int wakeup)
+                                        int autoidle, int wakeup)
 {
        u32 l;
-        l = __omap_dm_timer_read(base, OMAP_TIMER_OCP_CFG_REG, 0);
+        l = __raw_readl(timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
        l |= 0x02 << 3;  /* Set to smart-idle mode */
        l |= 0x2 << 8;   /* Set clock activity to perserve f-clock on idle */
@@ -261,10 +348,10 @@ static inline void __omap_dm_timer_reset(void __iomem *base, int autoidle,
        if (wakeup)
                l |= 1 << 2;
-        __omap_dm_timer_write(base, OMAP_TIMER_OCP_CFG_REG, l, 0);
+        __raw_writel(l, timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
        /* Match hardware reset default of posted mode */
-        __omap_dm_timer_write(base, OMAP_TIMER_IF_CTRL_REG,
+        __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
                                        OMAP_TIMER_CTRL_POSTED, 0);
 }
@@ -286,18 +373,18 @@ static inline int __omap_dm_timer_set_source(struct clk *timer_fck,
        return ret;
 }
-static inline void __omap_dm_timer_stop(void __iomem *base, int posted,
+static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
-                                                unsigned long rate)
+                                        int posted, unsigned long rate)
 {
        u32 l;
-        l = __omap_dm_timer_read(base, OMAP_TIMER_CTRL_REG, posted);
+        l = __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
        if (l & OMAP_TIMER_CTRL_ST) {
                l &= ~0x1;
-                __omap_dm_timer_write(base, OMAP_TIMER_CTRL_REG, l, posted);
+                __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted);
 #ifdef CONFIG_ARCH_OMAP2PLUS
                /* Readback to make sure write has completed */
-                __omap_dm_timer_read(base, OMAP_TIMER_CTRL_REG, posted);
+                __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
                /*
                 * Wait for functional clock period x 3.5 to make sure that
                 * timer is stopped
@@ -307,34 +394,34 @@ static inline void __omap_dm_timer_stop(void __iomem *base, int posted,
        }
        /* Ack possibly pending interrupt */
-        __omap_dm_timer_write(base, OMAP_TIMER_STAT_REG,
+        __raw_writel(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat);
-                                        OMAP_TIMER_INT_OVERFLOW, 0);
 }
-static inline void __omap_dm_timer_load_start(void __iomem *base, u32 ctrl,
+static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer,
-                                                unsigned int load, int posted)
+                                                u32 ctrl, unsigned int load,
+                                                int posted)
 {
-        __omap_dm_timer_write(base, OMAP_TIMER_COUNTER_REG, load, posted);
+        __omap_dm_timer_write(timer, OMAP_TIMER_COUNTER_REG, load, posted);
-        __omap_dm_timer_write(base, OMAP_TIMER_CTRL_REG, ctrl, posted);
+        __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, ctrl, posted);
 }
-static inline void __omap_dm_timer_int_enable(void __iomem *base,
+static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer,
                                                unsigned int value)
 {
-        __omap_dm_timer_write(base, OMAP_TIMER_INT_EN_REG, value, 0);
+        __raw_writel(value, timer->irq_ena);
-        __omap_dm_timer_write(base, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
+        __omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
 }
-static inline unsigned int __omap_dm_timer_read_counter(void __iomem *base,
+static inline unsigned int
-                                                        int posted)
+__omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted)
 {
-        return __omap_dm_timer_read(base, OMAP_TIMER_COUNTER_REG, posted);
+        return __omap_dm_timer_read(timer, OMAP_TIMER_COUNTER_REG, posted);
 }
-static inline void __omap_dm_timer_write_status(void __iomem *base,
+static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
                                                unsigned int value)
 {
-        __omap_dm_timer_write(base, OMAP_TIMER_STAT_REG, value, 0);
+        __raw_writel(value, timer->irq_stat);
 }
 #endif /* __ASM_ARCH_DMTIMER_H */
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
index ebe67ea8d068..7f2969eadb85 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -228,13 +228,13 @@
 #define OMAP44XX_EMIF2_PHYS     OMAP44XX_EMIF2_BASE
                                                /* 0x4d000000 --> 0xfd200000 */
-#define OMAP44XX_EMIF2_VIRT     (OMAP44XX_EMIF2_PHYS + OMAP4_L3_PER_IO_OFFSET)
 #define OMAP44XX_EMIF2_SIZE     SZ_1M
+#define OMAP44XX_EMIF2_VIRT     (OMAP44XX_EMIF1_VIRT + OMAP44XX_EMIF1_SIZE)
 #define OMAP44XX_DMM_PHYS       OMAP44XX_DMM_BASE
                                                /* 0x4e000000 --> 0xfd300000 */
-#define OMAP44XX_DMM_VIRT       (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET)
 #define OMAP44XX_DMM_SIZE       SZ_1M
+#define OMAP44XX_DMM_VIRT       (OMAP44XX_EMIF2_VIRT + OMAP44XX_EMIF2_SIZE)
 /*
 * ----------------------------------------------------------------------------
 * Omap specific register access
@@ -247,6 +247,8 @@
 * NOTE: Please use ioremap + __raw_read/write where possible instead of these
 */
+void omap_ioremap_init(void);
 extern u8 omap_readb(u32 pa);
 extern u16 omap_readw(u32 pa);
 extern u32 omap_readl(u32 pa);
@@ -256,8 +258,31 @@ extern void omap_writel(u32 v, u32 pa);
 struct omap_sdrc_params;
-extern void omap1_map_common_io(void);
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-extern void omap1_init_common_hw(void);
+void omap7xx_map_io(void);
+#else
+static inline void omap_map_io(void)
+{
+}
+#endif
+#ifdef CONFIG_ARCH_OMAP15XX
+void omap15xx_map_io(void);
+#else
+static inline void omap15xx_map_io(void)
+{
+}
+#endif
+#ifdef CONFIG_ARCH_OMAP16XX
+void omap16xx_map_io(void);
+#else
+static inline void omap16xx_map_io(void)
+{
+}
+#endif
+void omap1_init_early(void);
 #ifdef CONFIG_SOC_OMAP2420
 extern void omap242x_map_common_io(void);
@@ -300,7 +325,7 @@ static inline void omap44xx_map_common_io(void)
 #endif
 extern void omap2_init_common_infrastructure(void);
-extern void omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
+extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
                                      struct omap_sdrc_params *sdrc_cs1);
 #define __arch_ioremap  omap_ioremap
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index 9882c657b2d4..8fa74e2c9d6e 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -25,9 +25,7 @@
 #define __ASM_ARCH_OMAP_MCBSP_H
 #include <linux/spinlock.h>
+#include <linux/clk.h>
-#include <mach/hardware.h>
-#include <plat/clock.h>
 /* macro for building platform_device for McBSP ports */
 #define OMAP_MCBSP_PLATFORM_DEVICE(port_nr)             \
@@ -40,104 +38,60 @@ static struct platform_device omap_mcbsp##port_nr = {	\
 #define MCBSP_CONFIG_TYPE3      0x3
 #define MCBSP_CONFIG_TYPE4      0x4
-#define OMAP7XX_MCBSP1_BASE     0xfffb1000
+/* McBSP register numbers. Register address offset = num * reg_step */
-#define OMAP7XX_MCBSP2_BASE     0xfffb1800
+enum {
+        /* Common registers */
-#define OMAP1510_MCBSP1_BASE    0xe1011800
+        OMAP_MCBSP_REG_SPCR2 = 4,
-#define OMAP1510_MCBSP2_BASE    0xfffb1000
+        OMAP_MCBSP_REG_SPCR1,
-#define OMAP1510_MCBSP3_BASE    0xe1017000
+        OMAP_MCBSP_REG_RCR2,
+        OMAP_MCBSP_REG_RCR1,
-#define OMAP1610_MCBSP1_BASE    0xe1011800
+        OMAP_MCBSP_REG_XCR2,
-#define OMAP1610_MCBSP2_BASE    0xfffb1000
+        OMAP_MCBSP_REG_XCR1,
-#define OMAP1610_MCBSP3_BASE    0xe1017000
+        OMAP_MCBSP_REG_SRGR2,
+        OMAP_MCBSP_REG_SRGR1,
-#ifdef CONFIG_ARCH_OMAP1
+        OMAP_MCBSP_REG_MCR2,
+        OMAP_MCBSP_REG_MCR1,
-#define OMAP_MCBSP_REG_DRR2     0x00
+        OMAP_MCBSP_REG_RCERA,
-#define OMAP_MCBSP_REG_DRR1     0x02
+        OMAP_MCBSP_REG_RCERB,
-#define OMAP_MCBSP_REG_DXR2     0x04
+        OMAP_MCBSP_REG_XCERA,
-#define OMAP_MCBSP_REG_DXR1     0x06
+        OMAP_MCBSP_REG_XCERB,
-#define OMAP_MCBSP_REG_DRR      0x02
+        OMAP_MCBSP_REG_PCR0,
-#define OMAP_MCBSP_REG_DXR      0x06
+        OMAP_MCBSP_REG_RCERC,
-#define OMAP_MCBSP_REG_SPCR2    0x08
+        OMAP_MCBSP_REG_RCERD,
-#define OMAP_MCBSP_REG_SPCR1    0x0a
+        OMAP_MCBSP_REG_XCERC,
-#define OMAP_MCBSP_REG_RCR2     0x0c
+        OMAP_MCBSP_REG_XCERD,
-#define OMAP_MCBSP_REG_RCR1     0x0e
+        OMAP_MCBSP_REG_RCERE,
-#define OMAP_MCBSP_REG_XCR2     0x10
+        OMAP_MCBSP_REG_RCERF,
-#define OMAP_MCBSP_REG_XCR1     0x12
+        OMAP_MCBSP_REG_XCERE,
-#define OMAP_MCBSP_REG_SRGR2    0x14
+        OMAP_MCBSP_REG_XCERF,
-#define OMAP_MCBSP_REG_SRGR1    0x16
+        OMAP_MCBSP_REG_RCERG,
-#define OMAP_MCBSP_REG_MCR2     0x18
+        OMAP_MCBSP_REG_RCERH,
-#define OMAP_MCBSP_REG_MCR1     0x1a
+        OMAP_MCBSP_REG_XCERG,
-#define OMAP_MCBSP_REG_RCERA    0x1c
+        OMAP_MCBSP_REG_XCERH,
-#define OMAP_MCBSP_REG_RCERB    0x1e
-#define OMAP_MCBSP_REG_XCERA    0x20
+        /* OMAP1-OMAP2420 registers */
-#define OMAP_MCBSP_REG_XCERB    0x22
+        OMAP_MCBSP_REG_DRR2 = 0,
-#define OMAP_MCBSP_REG_PCR0     0x24
+        OMAP_MCBSP_REG_DRR1,
-#define OMAP_MCBSP_REG_RCERC    0x26
+        OMAP_MCBSP_REG_DXR2,
-#define OMAP_MCBSP_REG_RCERD    0x28
+        OMAP_MCBSP_REG_DXR1,
-#define OMAP_MCBSP_REG_XCERC    0x2A
-#define OMAP_MCBSP_REG_XCERD    0x2C
+        /* OMAP2430 and onwards */
-#define OMAP_MCBSP_REG_RCERE    0x2E
+        OMAP_MCBSP_REG_DRR = 0,
-#define OMAP_MCBSP_REG_RCERF    0x30
+        OMAP_MCBSP_REG_DXR = 2,
-#define OMAP_MCBSP_REG_XCERE    0x32
+        OMAP_MCBSP_REG_SYSCON = 35,
-#define OMAP_MCBSP_REG_XCERF    0x34
+        OMAP_MCBSP_REG_THRSH2,
-#define OMAP_MCBSP_REG_RCERG    0x36
+        OMAP_MCBSP_REG_THRSH1,
-#define OMAP_MCBSP_REG_RCERH    0x38
+        OMAP_MCBSP_REG_IRQST = 40,
-#define OMAP_MCBSP_REG_XCERG    0x3A
+        OMAP_MCBSP_REG_IRQEN,
-#define OMAP_MCBSP_REG_XCERH    0x3C
+        OMAP_MCBSP_REG_WAKEUPEN,
+        OMAP_MCBSP_REG_XCCR,
-/* Dummy defines, these are not available on omap1 */
+        OMAP_MCBSP_REG_RCCR,
-#define OMAP_MCBSP_REG_XCCR     0x00
+        OMAP_MCBSP_REG_XBUFFSTAT,
-#define OMAP_MCBSP_REG_RCCR     0x00
+        OMAP_MCBSP_REG_RBUFFSTAT,
+        OMAP_MCBSP_REG_SSELCR,
-#else
+};
-#define OMAP_MCBSP_REG_DRR2     0x00
-#define OMAP_MCBSP_REG_DRR1     0x04
-#define OMAP_MCBSP_REG_DXR2     0x08
-#define OMAP_MCBSP_REG_DXR1     0x0C
-#define OMAP_MCBSP_REG_DRR      0x00
-#define OMAP_MCBSP_REG_DXR      0x08
-#define OMAP_MCBSP_REG_SPCR2    0x10
-#define OMAP_MCBSP_REG_SPCR1    0x14
-#define OMAP_MCBSP_REG_RCR2     0x18
-#define OMAP_MCBSP_REG_RCR1     0x1C
-#define OMAP_MCBSP_REG_XCR2     0x20
-#define OMAP_MCBSP_REG_XCR1     0x24
-#define OMAP_MCBSP_REG_SRGR2    0x28
-#define OMAP_MCBSP_REG_SRGR1    0x2C
-#define OMAP_MCBSP_REG_MCR2     0x30
-#define OMAP_MCBSP_REG_MCR1     0x34
-#define OMAP_MCBSP_REG_RCERA    0x38
-#define OMAP_MCBSP_REG_RCERB    0x3C
-#define OMAP_MCBSP_REG_XCERA    0x40
-#define OMAP_MCBSP_REG_XCERB    0x44
-#define OMAP_MCBSP_REG_PCR0     0x48
-#define OMAP_MCBSP_REG_RCERC    0x4C
-#define OMAP_MCBSP_REG_RCERD    0x50
-#define OMAP_MCBSP_REG_XCERC    0x54
-#define OMAP_MCBSP_REG_XCERD    0x58
-#define OMAP_MCBSP_REG_RCERE    0x5C
-#define OMAP_MCBSP_REG_RCERF    0x60
-#define OMAP_MCBSP_REG_XCERE    0x64
-#define OMAP_MCBSP_REG_XCERF    0x68
-#define OMAP_MCBSP_REG_RCERG    0x6C
-#define OMAP_MCBSP_REG_RCERH    0x70
-#define OMAP_MCBSP_REG_XCERG    0x74
-#define OMAP_MCBSP_REG_XCERH    0x78
-#define OMAP_MCBSP_REG_SYSCON   0x8C
-#define OMAP_MCBSP_REG_THRSH2   0x90
-#define OMAP_MCBSP_REG_THRSH1   0x94
-#define OMAP_MCBSP_REG_IRQST    0xA0
-#define OMAP_MCBSP_REG_IRQEN    0xA4
-#define OMAP_MCBSP_REG_WAKEUPEN 0xA8
-#define OMAP_MCBSP_REG_XCCR     0xAC
-#define OMAP_MCBSP_REG_RCCR     0xB0
-#define OMAP_MCBSP_REG_XBUFFSTAT        0xB4
-#define OMAP_MCBSP_REG_RBUFFSTAT        0xB8
-#define OMAP_MCBSP_REG_SSELCR   0xBC
+/* OMAP3 sidetone control registers */
 #define OMAP_ST_REG_REV         0x00
 #define OMAP_ST_REG_SYSCONFIG   0x10
 #define OMAP_ST_REG_IRQSTATUS   0x18
@@ -146,8 +100,6 @@ static struct platform_device omap_mcbsp##port_nr = {	\
 #define OMAP_ST_REG_SFIRCR      0x28
 #define OMAP_ST_REG_SSELCR      0x2C
-#endif
 /************************** McBSP SPCR1 bit definitions ***********************/
 #define RRST                    0x0001
 #define RRDY                    0x0002
@@ -344,20 +296,20 @@ typedef enum {
 struct omap_mcbsp_ops {
        void (*request)(unsigned int);
        void (*free)(unsigned int);
-        int (*set_clks_src)(u8, u8);
 };
 struct omap_mcbsp_platform_data {
-        unsigned long phys_base;
-        u8 dma_rx_sync, dma_tx_sync;
-        u16 rx_irq, tx_irq;
        struct omap_mcbsp_ops *ops;
-#ifdef CONFIG_ARCH_OMAP3
-        /* Sidetone block for McBSP 2 and 3 */
-        unsigned long phys_base_st;
-#endif
        u16 buffer_size;
-        unsigned int mcbsp_config_type;
+        u8 reg_size;
+        u8 reg_step;
+        /* McBSP platform and instance specific features */
+        bool has_wakeup; /* Wakeup capability */
+        bool has_ccr; /* Transceiver has configuration control registers */
+        int (*enable_st_clock)(unsigned int, bool);
+        int (*set_clk_src)(struct device *dev, struct clk *clk, const char *src);
+        int (*mux_signal)(struct device *dev, const char *signal, const char *src);
 };
 struct omap_mcbsp_st_data {
@@ -389,14 +341,12 @@ struct omap_mcbsp {
        spinlock_t lock;
        struct omap_mcbsp_platform_data *pdata;
        struct clk *fclk;
-#ifdef CONFIG_ARCH_OMAP3
        struct omap_mcbsp_st_data *st_data;
        int dma_op_mode;
        u16 max_tx_thres;
        u16 max_rx_thres;
-#endif
        void *reg_cache;
-        unsigned int mcbsp_config_type;
+        int reg_cache_size;
 };
 /**
@@ -408,16 +358,10 @@ struct omap_mcbsp_dev_attr {
 };
 extern struct omap_mcbsp **mcbsp_ptr;
-extern int omap_mcbsp_count, omap_mcbsp_cache_size;
+extern int omap_mcbsp_count;
-#define omap_mcbsp_check_valid_id(id)   (id < omap_mcbsp_count)
-#define id_to_mcbsp_ptr(id)             mcbsp_ptr[id];
 int omap_mcbsp_init(void);
-void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
-                        struct omap_mcbsp_platform_data *config, int size);
 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
-#ifdef CONFIG_ARCH_OMAP3
 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
@@ -426,18 +370,6 @@ u16 omap_mcbsp_get_fifo_size(unsigned int id);
 u16 omap_mcbsp_get_tx_delay(unsigned int id);
 u16 omap_mcbsp_get_rx_delay(unsigned int id);
 int omap_mcbsp_get_dma_op_mode(unsigned int id);
-#else
-static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
-{ }
-static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
-{ }
-static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
-static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
-static inline u16 omap_mcbsp_get_fifo_size(unsigned int id) { return 0; }
-static inline u16 omap_mcbsp_get_tx_delay(unsigned int id) { return 0; }
-static inline u16 omap_mcbsp_get_rx_delay(unsigned int id) { return 0; }
-static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
-#endif
 int omap_mcbsp_request(unsigned int id);
 void omap_mcbsp_free(unsigned int id);
 void omap_mcbsp_start(unsigned int id, int tx, int rx);
@@ -453,21 +385,11 @@ void omap2_mcbsp1_mux_fsr_src(u8 mux);
 int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream);
 int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream);
-#ifdef CONFIG_ARCH_OMAP3
 /* Sidetone specific API */
 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
 int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain);
 int omap_st_enable(unsigned int id);
 int omap_st_disable(unsigned int id);
 int omap_st_is_enabled(unsigned int id);
-#else
-static inline int omap_st_set_chgain(unsigned int id, int channel,
-                                     s16 chgain) { return 0; }
-static inline int omap_st_get_chgain(unsigned int id, int channel,
-                                     s16 *chgain) { return 0; }
-static inline int omap_st_enable(unsigned int id) { return 0; }
-static inline int omap_st_disable(unsigned int id) { return 0; }
-static inline int omap_st_is_enabled(unsigned int id) {  return 0; }
-#endif
 #endif
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index ee405b36df4b..12c5b0c345bf 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -68,7 +68,7 @@ extern struct device omap_device_parent;
 *
 */
 struct omap_device {
-        struct platform_device          pdev;
+        struct platform_device          *pdev;
        struct omap_hwmod               **hwmods;
        struct omap_device_pm_latency   *pm_lats;
        u32                             dev_wakeup_lat;
@@ -88,25 +88,20 @@ int omap_device_shutdown(struct platform_device *pdev);
 /* Core code interface */
-int omap_device_count_resources(struct omap_device *od);
+struct platform_device *omap_device_build(const char *pdev_name, int pdev_id,
-int omap_device_fill_resources(struct omap_device *od, struct resource *res);
-struct omap_device *omap_device_build(const char *pdev_name, int pdev_id,
                                      struct omap_hwmod *oh, void *pdata,
                                      int pdata_len,
                                      struct omap_device_pm_latency *pm_lats,
                                      int pm_lats_cnt, int is_early_device);
-struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
+struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
                                         struct omap_hwmod **oh, int oh_cnt,
                                         void *pdata, int pdata_len,
                                         struct omap_device_pm_latency *pm_lats,
                                         int pm_lats_cnt, int is_early_device);
-int omap_device_register(struct omap_device *od);
-int omap_early_device_register(struct omap_device *od);
 void __iomem *omap_device_get_rt_va(struct omap_device *od);
+struct device *omap_device_get_by_hwmod_name(const char *oh_name);
 /* OMAP PM interface */
 int omap_device_align_pm_lat(struct platform_device *pdev,
@@ -122,11 +117,6 @@ int omap_device_enable_hwmods(struct omap_device *od);
 int omap_device_disable_clocks(struct omap_device *od);
 int omap_device_enable_clocks(struct omap_device *od);
-static inline void omap_device_disable_idle_on_suspend(struct omap_device *od)
-{
-        od->flags |= OMAP_DEVICE_NO_IDLE_ON_SUSPEND;
-}
 /*
 * Entries should be kept in latency order ascending
 *
@@ -157,6 +147,17 @@ struct omap_device_pm_latency {
 #define OMAP_DEVICE_LATENCY_AUTO_ADJUST BIT(1)
 /* Get omap_device pointer from platform_device pointer */
-#define to_omap_device(x) container_of((x), struct omap_device, pdev)
+static inline struct omap_device *to_omap_device(struct platform_device *pdev)
+{
+        return pdev ? pdev->archdata.od : NULL;
+}
+static inline
+void omap_device_disable_idle_on_suspend(struct platform_device *pdev)
+{
+        struct omap_device *od = to_omap_device(pdev);
+        od->flags |= OMAP_DEVICE_NO_IDLE_ON_SUSPEND;
+}
 #endif
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 0e329ca88a70..5419f1a2aaa4 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -496,7 +496,6 @@ struct omap_hwmod_class {
 * @_state: internal-use hwmod state
 * @_postsetup_state: internal-use state to leave the hwmod in after _setup()
 * @flags: hwmod flags (documented below)
- * @omap_chip: OMAP chips this hwmod is present on
 * @_lock: spinlock serializing operations on this hwmod
 * @node: list node for hwmod list (internal use)
 *
@@ -526,7 +525,6 @@ struct omap_hwmod {
        char                            *clkdm_name;
        struct clockdomain              *clkdm;
        char                            *vdd_name;
-        struct voltagedomain            *voltdm;
        struct omap_hwmod_ocp_if        **masters; /* connect to *_IA */
        struct omap_hwmod_ocp_if        **slaves;  /* connect to *_TA */
        void                            *dev_attr;
@@ -545,7 +543,6 @@ struct omap_hwmod {
        u8                              _int_flags;
        u8                              _state;
        u8                              _postsetup_state;
-        const struct omap_chip_id       omap_chip;
 };
 int omap_hwmod_register(struct omap_hwmod **ohs);
diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h
new file mode 100644
index 000000000000..0a6a482ec014
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/voltage.h
@@ -0,0 +1,20 @@
+/*
+ * OMAP Voltage Management Routines
+ *
+ * Copyright (C) 2011, Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ARM_OMAP_VOLTAGE_H
+#define __ARCH_ARM_OMAP_VOLTAGE_H
+struct voltagedomain;
+struct voltagedomain *voltdm_lookup(const char *name);
+int voltdm_scale(struct voltagedomain *voltdm, unsigned long target_volt);
+unsigned long voltdm_get_voltage(struct voltagedomain *voltdm);
+#endif
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
index e9b0e23edd0a..333871f59995 100644
--- a/arch/arm/plat-omap/io.c
+++ b/arch/arm/plat-omap/io.c
@@ -24,11 +24,16 @@
 #define BETWEEN(p,st,sz)        ((p) >= (st) && (p) < ((st) + (sz)))
 #define XLATE(p,pst,vst)        ((void __iomem *)((p) - (pst) + (vst)))
+static int initialized;
 /*
 * Intercept ioremap() requests for addresses in our fixed mapping regions.
 */
 void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
 {
+        WARN(!initialized, "Do not use ioremap before init_early\n");
 #ifdef CONFIG_ARCH_OMAP1
        if (cpu_class_is_omap1()) {
                if (BETWEEN(p, OMAP1_IO_PHYS, OMAP1_IO_SIZE))
@@ -147,3 +152,8 @@ void __init omap_init_consistent_dma_size(void)
        init_consistent_dma_size(CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE << 20);
 #endif
 }
+void __init omap_ioremap_init(void)
+{
+        initialized++;
+}
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 6c62af108710..4b15cd7926d7 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -24,45 +24,40 @@
 #include <linux/slab.h>
 #include <plat/mcbsp.h>
-#include <plat/omap_device.h>
 #include <linux/pm_runtime.h>
-/* XXX These "sideways" includes are a sign that something is wrong */
-#include "../mach-omap2/cm2xxx_3xxx.h"
-#include "../mach-omap2/cm-regbits-34xx.h"
 struct omap_mcbsp **mcbsp_ptr;
-int omap_mcbsp_count, omap_mcbsp_cache_size;
+int omap_mcbsp_count;
+#define omap_mcbsp_check_valid_id(id)   (id < omap_mcbsp_count)
+#define id_to_mcbsp_ptr(id)             mcbsp_ptr[id];
 static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
 {
-        if (cpu_class_is_omap1()) {
+        void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
-                ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val;
-                __raw_writew((u16)val, mcbsp->io_base + reg);
+        if (mcbsp->pdata->reg_size == 2) {
-        } else if (cpu_is_omap2420()) {
+                ((u16 *)mcbsp->reg_cache)[reg] = (u16)val;
-                ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val;
+                __raw_writew((u16)val, addr);
-                __raw_writew((u16)val, mcbsp->io_base + reg);
        } else {
-                ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val;
+                ((u32 *)mcbsp->reg_cache)[reg] = val;
-                __raw_writel(val, mcbsp->io_base + reg);
+                __raw_writel(val, addr);
        }
 }
 static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
 {
-        if (cpu_class_is_omap1()) {
+        void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
-                return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
-                                ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)];
+        if (mcbsp->pdata->reg_size == 2) {
-        } else if (cpu_is_omap2420()) {
+                return !from_cache ? __raw_readw(addr) :
-                return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
+                                     ((u16 *)mcbsp->reg_cache)[reg];
-                                ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)];
        } else {
-                return !from_cache ? __raw_readl(mcbsp->io_base + reg) :
+                return !from_cache ? __raw_readl(addr) :
-                                ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)];
+                                     ((u32 *)mcbsp->reg_cache)[reg];
        }
 }
-#ifdef CONFIG_ARCH_OMAP3
 static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
 {
        __raw_writel(val, mcbsp->st_data->io_base_st + reg);
@@ -72,7 +67,6 @@ static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
 {
        return __raw_readl(mcbsp->st_data->io_base_st + reg);
 }
-#endif
 #define MCBSP_READ(mcbsp, reg) \
                omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
@@ -187,7 +181,7 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
        MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
        MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
        MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
-        if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
+        if (mcbsp->pdata->has_ccr) {
                MCBSP_WRITE(mcbsp, XCCR, config->xccr);
                MCBSP_WRITE(mcbsp, RCCR, config->rccr);
        }
@@ -239,46 +233,28 @@ int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream)
        }
        mcbsp = id_to_mcbsp_ptr(id);
-        data_reg = mcbsp->phys_dma_base;
+        if (mcbsp->pdata->reg_size == 2) {
-        if (mcbsp->mcbsp_config_type < MCBSP_CONFIG_TYPE2) {
                if (stream)
-                        data_reg += OMAP_MCBSP_REG_DRR1;
+                        data_reg = OMAP_MCBSP_REG_DRR1;
                else
-                        data_reg += OMAP_MCBSP_REG_DXR1;
+                        data_reg = OMAP_MCBSP_REG_DXR1;
        } else {
                if (stream)
-                        data_reg += OMAP_MCBSP_REG_DRR;
+                        data_reg = OMAP_MCBSP_REG_DRR;
                else
-                        data_reg += OMAP_MCBSP_REG_DXR;
+                        data_reg = OMAP_MCBSP_REG_DXR;
        }
-        return data_reg;
+        return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
 }
 EXPORT_SYMBOL(omap_mcbsp_dma_reg_params);
-#ifdef CONFIG_ARCH_OMAP3
-static struct omap_device *find_omap_device_by_dev(struct device *dev)
-{
-        struct platform_device *pdev = container_of(dev,
-                                        struct platform_device, dev);
-        return container_of(pdev, struct omap_device, pdev);
-}
 static void omap_st_on(struct omap_mcbsp *mcbsp)
 {
        unsigned int w;
-        struct omap_device *od;
-        od = find_omap_device_by_dev(mcbsp->dev);
+        if (mcbsp->pdata->enable_st_clock)
+                mcbsp->pdata->enable_st_clock(mcbsp->id, 1);
-        /*
-         * Sidetone uses McBSP ICLK - which must not idle when sidetones
-         * are enabled or sidetones start sounding ugly.
-         */
-        w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
-        w &= ~(1 << (mcbsp->id - 2));
-        omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
        /* Enable McBSP Sidetone */
        w = MCBSP_READ(mcbsp, SSELCR);
@@ -292,9 +268,6 @@ static void omap_st_on(struct omap_mcbsp *mcbsp)
 static void omap_st_off(struct omap_mcbsp *mcbsp)
 {
        unsigned int w;
-        struct omap_device *od;
-        od = find_omap_device_by_dev(mcbsp->dev);
        w = MCBSP_ST_READ(mcbsp, SSELCR);
        MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
@@ -302,17 +275,13 @@ static void omap_st_off(struct omap_mcbsp *mcbsp)
        w = MCBSP_READ(mcbsp, SSELCR);
        MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
-        w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
+        if (mcbsp->pdata->enable_st_clock)
-        w |= 1 << (mcbsp->id - 2);
+                mcbsp->pdata->enable_st_clock(mcbsp->id, 0);
-        omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
 }
 static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
 {
        u16 val, i;
-        struct omap_device *od;
-        od = find_omap_device_by_dev(mcbsp->dev);
        val = MCBSP_ST_READ(mcbsp, SSELCR);
@@ -340,9 +309,6 @@ static void omap_st_chgain(struct omap_mcbsp *mcbsp)
 {
        u16 w;
        struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
-        struct omap_device *od;
-        od = find_omap_device_by_dev(mcbsp->dev);
        w = MCBSP_ST_READ(mcbsp, SSELCR);
@@ -525,14 +491,13 @@ void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
 {
        struct omap_mcbsp *mcbsp;
-        if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
-                return;
        if (!omap_mcbsp_check_valid_id(id)) {
                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
                return;
        }
        mcbsp = id_to_mcbsp_ptr(id);
+        if (mcbsp->pdata->buffer_size == 0)
+                return;
        if (threshold && threshold <= mcbsp->max_tx_thres)
                MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
@@ -548,14 +513,13 @@ void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
 {
        struct omap_mcbsp *mcbsp;
-        if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
-                return;
        if (!omap_mcbsp_check_valid_id(id)) {
                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
                return;
        }
        mcbsp = id_to_mcbsp_ptr(id);
+        if (mcbsp->pdata->buffer_size == 0)
+                return;
        if (threshold && threshold <= mcbsp->max_rx_thres)
                MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
@@ -625,6 +589,8 @@ u16 omap_mcbsp_get_tx_delay(unsigned int id)
                return -ENODEV;
        }
        mcbsp = id_to_mcbsp_ptr(id);
+        if (mcbsp->pdata->buffer_size == 0)
+                return 0;
        /* Returns the number of free locations in the buffer */
        buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
@@ -648,6 +614,8 @@ u16 omap_mcbsp_get_rx_delay(unsigned int id)
                return -ENODEV;
        }
        mcbsp = id_to_mcbsp_ptr(id);
+        if (mcbsp->pdata->buffer_size == 0)
+                return 0;
        /* Returns the number of used locations in the buffer */
        buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
@@ -683,46 +651,6 @@ int omap_mcbsp_get_dma_op_mode(unsigned int id)
 }
 EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
-static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
-{
-        struct omap_device *od;
-        od = find_omap_device_by_dev(mcbsp->dev);
-        /*
-         * Enable wakup behavior, smart idle and all wakeups
-         * REVISIT: some wakeups may be unnecessary
-         */
-        if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
-                MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
-        }
-}
-static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
-{
-        struct omap_device *od;
-        od = find_omap_device_by_dev(mcbsp->dev);
-        /*
-         * Disable wakup behavior, smart idle and all wakeups
-         */
-        if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
-                /*
-                 * HW bug workaround - If no_idle mode is taken, we need to
-                 * go to smart_idle before going to always_idle, or the
-                 * device will not hit retention anymore.
-                 */
-                MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
-        }
-}
-#else
-static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
-static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
-static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
-static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
-#endif
 int omap_mcbsp_request(unsigned int id)
 {
        struct omap_mcbsp *mcbsp;
@@ -735,7 +663,7 @@ int omap_mcbsp_request(unsigned int id)
        }
        mcbsp = id_to_mcbsp_ptr(id);
-        reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL);
+        reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL);
        if (!reg_cache) {
                return -ENOMEM;
        }
@@ -757,8 +685,9 @@ int omap_mcbsp_request(unsigned int id)
        pm_runtime_get_sync(mcbsp->dev);
-        /* Do procedure specific to omap34xx arch, if applicable */
+        /* Enable wakeup behavior */
-        omap34xx_mcbsp_request(mcbsp);
+        if (mcbsp->pdata->has_wakeup)
+                MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
        /*
         * Make sure that transmitter, receiver and sample-rate generator are
@@ -795,8 +724,9 @@ err_clk_disable:
        if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
                mcbsp->pdata->ops->free(id);
-        /* Do procedure specific to omap34xx arch, if applicable */
+        /* Disable wakeup behavior */
-        omap34xx_mcbsp_free(mcbsp);
+        if (mcbsp->pdata->has_wakeup)
+                MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
        pm_runtime_put_sync(mcbsp->dev);
@@ -825,8 +755,9 @@ void omap_mcbsp_free(unsigned int id)
        if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
                mcbsp->pdata->ops->free(id);
-        /* Do procedure specific to omap34xx arch, if applicable */
+        /* Disable wakeup behavior */
-        omap34xx_mcbsp_free(mcbsp);
+        if (mcbsp->pdata->has_wakeup)
+                MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
        pm_runtime_put_sync(mcbsp->dev);
@@ -866,7 +797,7 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx)
        }
        mcbsp = id_to_mcbsp_ptr(id);
-        if (cpu_is_omap34xx())
+        if (mcbsp->st_data)
                omap_st_start(mcbsp);
        /* Only enable SRG, if McBSP is master */
@@ -904,7 +835,7 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx)
                MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
        }
-        if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
+        if (mcbsp->pdata->has_ccr) {
                /* Release the transmitter and receiver */
                w = MCBSP_READ_CACHE(mcbsp, XCCR);
                w &= ~(tx ? XDISABLE : 0);
@@ -934,7 +865,7 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
        /* Reset transmitter */
        tx &= 1;
-        if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
+        if (mcbsp->pdata->has_ccr) {
                w = MCBSP_READ_CACHE(mcbsp, XCCR);
                w |= (tx ? XDISABLE : 0);
                MCBSP_WRITE(mcbsp, XCCR, w);
@@ -944,7 +875,7 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
        /* Reset receiver */
        rx &= 1;
-        if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
+        if (mcbsp->pdata->has_ccr) {
                w = MCBSP_READ_CACHE(mcbsp, RCCR);
                w |= (rx ? RDISABLE : 0);
                MCBSP_WRITE(mcbsp, RCCR, w);
@@ -961,39 +892,72 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
                MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
        }
-        if (cpu_is_omap34xx())
+        if (mcbsp->st_data)
                omap_st_stop(mcbsp);
 }
 EXPORT_SYMBOL(omap_mcbsp_stop);
-/*
- * The following functions are only required on an OMAP1-only build.
- * mach-omap2/mcbsp.c contains the real functions
- */
-#ifndef CONFIG_ARCH_OMAP2PLUS
 int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
 {
-        WARN(1, "%s: should never be called on an OMAP1-only kernel\n",
+        struct omap_mcbsp *mcbsp;
-             __func__);
+        const char *src;
-        return -EINVAL;
+        if (!omap_mcbsp_check_valid_id(id)) {
+                pr_err("%s: Invalid id (%d)\n", __func__, id + 1);
+                return -EINVAL;
+        }
+        mcbsp = id_to_mcbsp_ptr(id);
+        if (fck_src_id == MCBSP_CLKS_PAD_SRC)
+                src = "clks_ext";
+        else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
+                src = "clks_fclk";
+        else
+                return -EINVAL;
+        if (mcbsp->pdata->set_clk_src)
+                return mcbsp->pdata->set_clk_src(mcbsp->dev, mcbsp->fclk, src);
+        else
+                return -EINVAL;
 }
+EXPORT_SYMBOL(omap2_mcbsp_set_clks_src);
 void omap2_mcbsp1_mux_clkr_src(u8 mux)
 {
-        WARN(1, "%s: should never be called on an OMAP1-only kernel\n",
+        struct omap_mcbsp *mcbsp;
-             __func__);
+        const char *src;
-        return;
+        if (mux == CLKR_SRC_CLKR)
+                src = "clkr";
+        else if (mux == CLKR_SRC_CLKX)
+                src = "clkx";
+        else
+                return;
+        mcbsp = id_to_mcbsp_ptr(0);
+        if (mcbsp->pdata->mux_signal)
+                mcbsp->pdata->mux_signal(mcbsp->dev, "clkr", src);
 }
+EXPORT_SYMBOL(omap2_mcbsp1_mux_clkr_src);
 void omap2_mcbsp1_mux_fsr_src(u8 mux)
 {
-        WARN(1, "%s: should never be called on an OMAP1-only kernel\n",
+        struct omap_mcbsp *mcbsp;
-             __func__);
+        const char *src;
-        return;
+        if (mux == FSR_SRC_FSR)
+                src = "fsr";
+        else if (mux == FSR_SRC_FSX)
+                src = "fsx";
+        else
+                return;
+        mcbsp = id_to_mcbsp_ptr(0);
+        if (mcbsp->pdata->mux_signal)
+                mcbsp->pdata->mux_signal(mcbsp->dev, "fsr", src);
 }
-#endif
+EXPORT_SYMBOL(omap2_mcbsp1_mux_fsr_src);
-#ifdef CONFIG_ARCH_OMAP3
 #define max_thres(m)                    (mcbsp->pdata->buffer_size)
 #define valid_threshold(m, val)         ((val) <= max_thres(m))
 #define THRESHOLD_PROP_BUILDER(prop)                                    \
@@ -1084,6 +1048,17 @@ unlock:
 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
+static const struct attribute *additional_attrs[] = {
+        &dev_attr_max_tx_thres.attr,
+        &dev_attr_max_rx_thres.attr,
+        &dev_attr_dma_op_mode.attr,
+        NULL,
+};
+static const struct attribute_group additional_attr_group = {
+        .attrs = (struct attribute **)additional_attrs,
+};
 static ssize_t st_taps_show(struct device *dev,
                            struct device_attribute *attr, char *buf)
 {
@@ -1142,27 +1117,6 @@ out:
 static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
-static const struct attribute *additional_attrs[] = {
-        &dev_attr_max_tx_thres.attr,
-        &dev_attr_max_rx_thres.attr,
-        &dev_attr_dma_op_mode.attr,
-        NULL,
-};
-static const struct attribute_group additional_attr_group = {
-        .attrs = (struct attribute **)additional_attrs,
-};
-static inline int __devinit omap_additional_add(struct device *dev)
-{
-        return sysfs_create_group(&dev->kobj, &additional_attr_group);
-}
-static inline void __devexit omap_additional_remove(struct device *dev)
-{
-        sysfs_remove_group(&dev->kobj, &additional_attr_group);
-}
 static const struct attribute *sidetone_attrs[] = {
        &dev_attr_st_taps.attr,
        NULL,
@@ -1172,10 +1126,9 @@ static const struct attribute_group sidetone_attr_group = {
        .attrs = (struct attribute **)sidetone_attrs,
 };
-static int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
+static int __devinit omap_st_add(struct omap_mcbsp *mcbsp,
+                                 struct resource *res)
 {
-        struct platform_device *pdev;
-        struct resource *res;
        struct omap_mcbsp_st_data *st_data;
        int err;
@@ -1185,9 +1138,6 @@ static int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
                goto err1;
        }
-        pdev = container_of(mcbsp->dev, struct platform_device, dev);
-        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
        st_data->io_base_st = ioremap(res->start, resource_size(res));
        if (!st_data->io_base_st) {
                err = -ENOMEM;
@@ -1214,59 +1164,10 @@ static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
 {
        struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
-        if (st_data) {
+        sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
-                sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
+        iounmap(st_data->io_base_st);
-                iounmap(st_data->io_base_st);
+        kfree(st_data);
-                kfree(st_data);
-        }
-}
-static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
-{
-        mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
-        if (cpu_is_omap34xx()) {
-                /*
-                 * Initially configure the maximum thresholds to a safe value.
-                 * The McBSP FIFO usage with these values should not go under
-                 * 16 locations.
-                 * If the whole FIFO without safety buffer is used, than there
-                 * is a possibility that the DMA will be not able to push the
-                 * new data on time, causing channel shifts in runtime.
-                 */
-                mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
-                mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
-                /*
-                 * REVISIT: Set dmap_op_mode to THRESHOLD as default
-                 * for mcbsp2 instances.
-                 */
-                if (omap_additional_add(mcbsp->dev))
-                        dev_warn(mcbsp->dev,
-                                "Unable to create additional controls\n");
-                if (mcbsp->id == 2 || mcbsp->id == 3)
-                        if (omap_st_add(mcbsp))
-                                dev_warn(mcbsp->dev,
-                                 "Unable to create sidetone controls\n");
-        } else {
-                mcbsp->max_tx_thres = -EINVAL;
-                mcbsp->max_rx_thres = -EINVAL;
-        }
-}
-static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
-{
-        if (cpu_is_omap34xx()) {
-                omap_additional_remove(mcbsp->dev);
-                if (mcbsp->id == 2 || mcbsp->id == 3)
-                        omap_st_remove(mcbsp);
-        }
 }
-#else
-static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
-static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
-#endif /* CONFIG_ARCH_OMAP3 */
 /*
 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
@@ -1316,7 +1217,7 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
                }
        }
        mcbsp->phys_base = res->start;
-        omap_mcbsp_cache_size = resource_size(res);
+        mcbsp->reg_cache_size = resource_size(res);
        mcbsp->io_base = ioremap(res->start, resource_size(res));
        if (!mcbsp->io_base) {
                ret = -ENOMEM;
@@ -1364,15 +1265,52 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
        mcbsp->pdata = pdata;
        mcbsp->dev = &pdev->dev;
        mcbsp_ptr[id] = mcbsp;
-        mcbsp->mcbsp_config_type = pdata->mcbsp_config_type;
        platform_set_drvdata(pdev, mcbsp);
        pm_runtime_enable(mcbsp->dev);
-        /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
+        mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
-        omap34xx_device_init(mcbsp);
+        if (mcbsp->pdata->buffer_size) {
+                /*
+                 * Initially configure the maximum thresholds to a safe value.
+                 * The McBSP FIFO usage with these values should not go under
+                 * 16 locations.
+                 * If the whole FIFO without safety buffer is used, than there
+                 * is a possibility that the DMA will be not able to push the
+                 * new data on time, causing channel shifts in runtime.
+                 */
+                mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
+                mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
+                ret = sysfs_create_group(&mcbsp->dev->kobj,
+                                         &additional_attr_group);
+                if (ret) {
+                        dev_err(mcbsp->dev,
+                                "Unable to create additional controls\n");
+                        goto err_thres;
+                }
+        } else {
+                mcbsp->max_tx_thres = -EINVAL;
+                mcbsp->max_rx_thres = -EINVAL;
+        }
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
+        if (res) {
+                ret = omap_st_add(mcbsp, res);
+                if (ret) {
+                        dev_err(mcbsp->dev,
+                                "Unable to create sidetone controls\n");
+                        goto err_st;
+                }
+        }
        return 0;
+err_st:
+        if (mcbsp->pdata->buffer_size)
+                sysfs_remove_group(&mcbsp->dev->kobj,
+                                   &additional_attr_group);
+err_thres:
+        clk_put(mcbsp->fclk);
 err_res:
        iounmap(mcbsp->io_base);
 err_ioremap:
@@ -1392,7 +1330,12 @@ static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
                                mcbsp->pdata->ops->free)
                        mcbsp->pdata->ops->free(mcbsp->id);
-                omap34xx_device_exit(mcbsp);
+                if (mcbsp->pdata->buffer_size)
+                        sysfs_remove_group(&mcbsp->dev->kobj,
+                                           &additional_attr_group);
+                if (mcbsp->st_data)
+                        omap_st_remove(mcbsp);
                clk_put(mcbsp->fclk);
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index 02609eee0562..cd90bedd9306 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -85,6 +85,8 @@
 #include <linux/clk.h>
 #include <linux/clkdev.h>
 #include <linux/pm_runtime.h>
+#include <linux/of.h>
+#include <linux/notifier.h>
 #include <plat/omap_device.h>
 #include <plat/omap_hwmod.h>
@@ -94,6 +96,23 @@
 #define USE_WAKEUP_LAT                  0
 #define IGNORE_WAKEUP_LAT               1
+static int omap_device_register(struct platform_device *pdev);
+static int omap_early_device_register(struct platform_device *pdev);
+static struct omap_device *omap_device_alloc(struct platform_device *pdev,
+                                      struct omap_hwmod **ohs, int oh_cnt,
+                                      struct omap_device_pm_latency *pm_lats,
+                                      int pm_lats_cnt);
+static void omap_device_delete(struct omap_device *od);
+static struct omap_device_pm_latency omap_default_latency[] = {
+        {
+                .deactivate_func = omap_device_idle_hwmods,
+                .activate_func   = omap_device_enable_hwmods,
+                .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+        }
+};
 /* Private functions */
 /**
@@ -114,7 +133,7 @@ static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
 {
        struct timespec a, b, c;
-        pr_debug("omap_device: %s: activating\n", od->pdev.name);
+        dev_dbg(&od->pdev->dev, "omap_device: activating\n");
        while (od->pm_lat_level > 0) {
                struct omap_device_pm_latency *odpl;
@@ -138,25 +157,24 @@ static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
                c = timespec_sub(b, a);
                act_lat = timespec_to_ns(&c);
-                pr_debug("omap_device: %s: pm_lat %d: activate: elapsed time "
+                dev_dbg(&od->pdev->dev,
-                         "%llu nsec\n", od->pdev.name, od->pm_lat_level,
+                        "omap_device: pm_lat %d: activate: elapsed time "
-                         act_lat);
+                        "%llu nsec\n", od->pm_lat_level, act_lat);
                if (act_lat > odpl->activate_lat) {
                        odpl->activate_lat_worst = act_lat;
                        if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
                                odpl->activate_lat = act_lat;
-                                pr_warning("omap_device: %s.%d: new worst case "
+                                dev_dbg(&od->pdev->dev,
-                                           "activate latency %d: %llu\n",
+                                        "new worst case activate latency "
-                                           od->pdev.name, od->pdev.id,
+                                        "%d: %llu\n",
-                                           od->pm_lat_level, act_lat);
+                                        od->pm_lat_level, act_lat);
                        } else
-                                pr_warning("omap_device: %s.%d: activate "
+                                dev_warn(&od->pdev->dev,
-                                           "latency %d higher than exptected. "
+                                         "activate latency %d "
-                                           "(%llu > %d)\n",
+                                         "higher than exptected. (%llu > %d)\n",
-                                           od->pdev.name, od->pdev.id,
+                                         od->pm_lat_level, act_lat,
-                                           od->pm_lat_level, act_lat,
+                                         odpl->activate_lat);
-                                           odpl->activate_lat);
                }
                od->dev_wakeup_lat -= odpl->activate_lat;
@@ -183,7 +201,7 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
 {
        struct timespec a, b, c;
-        pr_debug("omap_device: %s: deactivating\n", od->pdev.name);
+        dev_dbg(&od->pdev->dev, "omap_device: deactivating\n");
        while (od->pm_lat_level < od->pm_lats_cnt) {
                struct omap_device_pm_latency *odpl;
@@ -206,28 +224,26 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
                c = timespec_sub(b, a);
                deact_lat = timespec_to_ns(&c);
-                pr_debug("omap_device: %s: pm_lat %d: deactivate: elapsed time "
+                dev_dbg(&od->pdev->dev,
-                         "%llu nsec\n", od->pdev.name, od->pm_lat_level,
+                        "omap_device: pm_lat %d: deactivate: elapsed time "
-                         deact_lat);
+                        "%llu nsec\n", od->pm_lat_level, deact_lat);
                if (deact_lat > odpl->deactivate_lat) {
                        odpl->deactivate_lat_worst = deact_lat;
                        if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
                                odpl->deactivate_lat = deact_lat;
-                                pr_warning("omap_device: %s.%d: new worst case "
+                                dev_dbg(&od->pdev->dev,
-                                           "deactivate latency %d: %llu\n",
+                                        "new worst case deactivate latency "
-                                           od->pdev.name, od->pdev.id,
+                                        "%d: %llu\n",
-                                           od->pm_lat_level, deact_lat);
+                                        od->pm_lat_level, deact_lat);
                        } else
-                                pr_warning("omap_device: %s.%d: deactivate "
+                                dev_warn(&od->pdev->dev,
-                                           "latency %d higher than exptected. "
+                                         "deactivate latency %d "
-                                           "(%llu > %d)\n",
+                                         "higher than exptected. (%llu > %d)\n",
-                                           od->pdev.name, od->pdev.id,
+                                         od->pm_lat_level, deact_lat,
-                                           od->pm_lat_level, deact_lat,
+                                         odpl->deactivate_lat);
-                                           odpl->deactivate_lat);
                }
                od->dev_wakeup_lat += odpl->activate_lat;
                od->pm_lat_level++;
@@ -245,28 +261,27 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias,
        if (!clk_alias || !clk_name)
                return;
-        pr_debug("omap_device: %s: Creating %s -> %s\n",
+        dev_dbg(&od->pdev->dev, "Creating %s -> %s\n", clk_alias, clk_name);
-                 dev_name(&od->pdev.dev), clk_alias, clk_name);
-        r = clk_get_sys(dev_name(&od->pdev.dev), clk_alias);
+        r = clk_get_sys(dev_name(&od->pdev->dev), clk_alias);
        if (!IS_ERR(r)) {
-                pr_warning("omap_device: %s: alias %s already exists\n",
+                dev_warn(&od->pdev->dev,
-                           dev_name(&od->pdev.dev), clk_alias);
+                         "alias %s already exists\n", clk_alias);
                clk_put(r);
                return;
        }
        r = omap_clk_get_by_name(clk_name);
        if (IS_ERR(r)) {
-                pr_err("omap_device: %s: omap_clk_get_by_name for %s failed\n",
+                dev_err(&od->pdev->dev,
-                       dev_name(&od->pdev.dev), clk_name);
+                        "omap_clk_get_by_name for %s failed\n", clk_name);
                return;
        }
-        l = clkdev_alloc(r, clk_alias, dev_name(&od->pdev.dev));
+        l = clkdev_alloc(r, clk_alias, dev_name(&od->pdev->dev));
        if (!l) {
-                pr_err("omap_device: %s: clkdev_alloc for %s failed\n",
+                dev_err(&od->pdev->dev,
-                       dev_name(&od->pdev.dev), clk_alias);
+                        "clkdev_alloc for %s failed\n", clk_alias);
                return;
        }
@@ -304,6 +319,96 @@ static void _add_hwmod_clocks_clkdev(struct omap_device *od,
 }
+static struct dev_pm_domain omap_device_pm_domain;
+/**
+ * omap_device_build_from_dt - build an omap_device with multiple hwmods
+ * @pdev_name: name of the platform_device driver to use
+ * @pdev_id: this platform_device's connection ID
+ * @oh: ptr to the single omap_hwmod that backs this omap_device
+ * @pdata: platform_data ptr to associate with the platform_device
+ * @pdata_len: amount of memory pointed to by @pdata
+ * @pm_lats: pointer to a omap_device_pm_latency array for this device
+ * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
+ * @is_early_device: should the device be registered as an early device or not
+ *
+ * Function for building an omap_device already registered from device-tree
+ *
+ * Returns 0 or PTR_ERR() on error.
+ */
+static int omap_device_build_from_dt(struct platform_device *pdev)
+{
+        struct omap_hwmod **hwmods;
+        struct omap_device *od;
+        struct omap_hwmod *oh;
+        struct device_node *node = pdev->dev.of_node;
+        const char *oh_name;
+        int oh_cnt, i, ret = 0;
+        oh_cnt = of_property_count_strings(node, "ti,hwmods");
+        if (!oh_cnt || IS_ERR_VALUE(oh_cnt)) {
+                dev_warn(&pdev->dev, "No 'hwmods' to build omap_device\n");
+                return -ENODEV;
+        }
+        hwmods = kzalloc(sizeof(struct omap_hwmod *) * oh_cnt, GFP_KERNEL);
+        if (!hwmods) {
+                ret = -ENOMEM;
+                goto odbfd_exit;
+        }
+        for (i = 0; i < oh_cnt; i++) {
+                of_property_read_string_index(node, "ti,hwmods", i, &oh_name);
+                oh = omap_hwmod_lookup(oh_name);
+                if (!oh) {
+                        dev_err(&pdev->dev, "Cannot lookup hwmod '%s'\n",
+                                oh_name);
+                        ret = -EINVAL;
+                        goto odbfd_exit1;
+                }
+                hwmods[i] = oh;
+        }
+        od = omap_device_alloc(pdev, hwmods, oh_cnt, NULL, 0);
+        if (!od) {
+                dev_err(&pdev->dev, "Cannot allocate omap_device for :%s\n",
+                        oh_name);
+                ret = PTR_ERR(od);
+                goto odbfd_exit1;
+        }
+        if (of_get_property(node, "ti,no_idle_on_suspend", NULL))
+                omap_device_disable_idle_on_suspend(pdev);
+        pdev->dev.pm_domain = &omap_device_pm_domain;
+odbfd_exit1:
+        kfree(hwmods);
+odbfd_exit:
+        return ret;
+}
+static int _omap_device_notifier_call(struct notifier_block *nb,
+                                      unsigned long event, void *dev)
+{
+        struct platform_device *pdev = to_platform_device(dev);
+        switch (event) {
+        case BUS_NOTIFY_ADD_DEVICE:
+                if (pdev->dev.of_node)
+                        omap_device_build_from_dt(pdev);
+                break;
+        case BUS_NOTIFY_DEL_DEVICE:
+                if (pdev->archdata.od)
+                        omap_device_delete(pdev->archdata.od);
+                break;
+        }
+        return NOTIFY_DONE;
+}
 /* Public functions for use by core code */
 /**
@@ -343,7 +448,7 @@ u32 omap_device_get_context_loss_count(struct platform_device *pdev)
 * much memory to allocate before calling
 * omap_device_fill_resources().  Returns the count.
 */
-int omap_device_count_resources(struct omap_device *od)
+static int omap_device_count_resources(struct omap_device *od)
 {
        int c = 0;
        int i;
@@ -352,7 +457,7 @@ int omap_device_count_resources(struct omap_device *od)
                c += omap_hwmod_count_resources(od->hwmods[i]);
        pr_debug("omap_device: %s: counted %d total resources across %d "
-                 "hwmods\n", od->pdev.name, c, od->hwmods_cnt);
+                 "hwmods\n", od->pdev->name, c, od->hwmods_cnt);
        return c;
 }
@@ -374,7 +479,8 @@ int omap_device_count_resources(struct omap_device *od)
 * functions to get device resources.  Hacking around the existing
 * platform_device code wastes memory.  Returns 0.
 */
-int omap_device_fill_resources(struct omap_device *od, struct resource *res)
+static int omap_device_fill_resources(struct omap_device *od,
+                                      struct resource *res)
 {
        int c = 0;
        int i, r;
@@ -389,6 +495,113 @@ int omap_device_fill_resources(struct omap_device *od, struct resource *res)
 }
 /**
+ * omap_device_alloc - allocate an omap_device
+ * @pdev: platform_device that will be included in this omap_device
+ * @oh: ptr to the single omap_hwmod that backs this omap_device
+ * @pdata: platform_data ptr to associate with the platform_device
+ * @pdata_len: amount of memory pointed to by @pdata
+ * @pm_lats: pointer to a omap_device_pm_latency array for this device
+ * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
+ *
+ * Convenience function for allocating an omap_device structure and filling
+ * hwmods, resources and pm_latency attributes.
+ *
+ * Returns an struct omap_device pointer or ERR_PTR() on error;
+ */
+static struct omap_device *omap_device_alloc(struct platform_device *pdev,
+                                        struct omap_hwmod **ohs, int oh_cnt,
+                                        struct omap_device_pm_latency *pm_lats,
+                                        int pm_lats_cnt)
+{
+        int ret = -ENOMEM;
+        struct omap_device *od;
+        struct resource *res = NULL;
+        int i, res_count;
+        struct omap_hwmod **hwmods;
+        od = kzalloc(sizeof(struct omap_device), GFP_KERNEL);
+        if (!od) {
+                ret = -ENOMEM;
+                goto oda_exit1;
+        }
+        od->hwmods_cnt = oh_cnt;
+        hwmods = kmemdup(ohs, sizeof(struct omap_hwmod *) * oh_cnt, GFP_KERNEL);
+        if (!hwmods)
+                goto oda_exit2;
+        od->hwmods = hwmods;
+        od->pdev = pdev;
+        /*
+         * HACK: Ideally the resources from DT should match, and hwmod
+         * should just add the missing ones. Since the name is not
+         * properly populated by DT, stick to hwmod resources only.
+         */
+        if (pdev->num_resources && pdev->resource)
+                dev_warn(&pdev->dev, "%s(): resources already allocated %d\n",
+                        __func__, pdev->num_resources);
+        res_count = omap_device_count_resources(od);
+        if (res_count > 0) {
+                dev_dbg(&pdev->dev, "%s(): resources allocated from hwmod %d\n",
+                        __func__, res_count);
+                res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL);
+                if (!res)
+                        goto oda_exit3;
+                omap_device_fill_resources(od, res);
+                ret = platform_device_add_resources(pdev, res, res_count);
+                kfree(res);
+                if (ret)
+                        goto oda_exit3;
+        }
+        if (!pm_lats) {
+                pm_lats = omap_default_latency;
+                pm_lats_cnt = ARRAY_SIZE(omap_default_latency);
+        }
+        od->pm_lats_cnt = pm_lats_cnt;
+        od->pm_lats = kmemdup(pm_lats,
+                        sizeof(struct omap_device_pm_latency) * pm_lats_cnt,
+                        GFP_KERNEL);
+        if (!od->pm_lats)
+                goto oda_exit3;
+        pdev->archdata.od = od;
+        for (i = 0; i < oh_cnt; i++) {
+                hwmods[i]->od = od;
+                _add_hwmod_clocks_clkdev(od, hwmods[i]);
+        }
+        return od;
+oda_exit3:
+        kfree(hwmods);
+oda_exit2:
+        kfree(od);
+oda_exit1:
+        dev_err(&pdev->dev, "omap_device: build failed (%d)\n", ret);
+        return ERR_PTR(ret);
+}
+static void omap_device_delete(struct omap_device *od)
+{
+        if (!od)
+                return;
+        od->pdev->archdata.od = NULL;
+        kfree(od->pm_lats);
+        kfree(od->hwmods);
+        kfree(od);
+}
+/**
 * omap_device_build - build and register an omap_device with one omap_hwmod
 * @pdev_name: name of the platform_device driver to use
 * @pdev_id: this platform_device's connection ID
@@ -405,7 +618,7 @@ int omap_device_fill_resources(struct omap_device *od, struct resource *res)
 * information.  Returns ERR_PTR(-EINVAL) if @oh is NULL; otherwise,
 * passes along the return value of omap_device_build_ss().
 */
-struct omap_device *omap_device_build(const char *pdev_name, int pdev_id,
+struct platform_device *omap_device_build(const char *pdev_name, int pdev_id,
                                      struct omap_hwmod *oh, void *pdata,
                                      int pdata_len,
                                      struct omap_device_pm_latency *pm_lats,
@@ -438,18 +651,15 @@ struct omap_device *omap_device_build(const char *pdev_name, int pdev_id,
 * platform_device record.  Returns an ERR_PTR() on error, or passes
 * along the return value of omap_device_register().
 */
-struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
+struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
                                         struct omap_hwmod **ohs, int oh_cnt,
                                         void *pdata, int pdata_len,
                                         struct omap_device_pm_latency *pm_lats,
                                         int pm_lats_cnt, int is_early_device)
 {
        int ret = -ENOMEM;
+        struct platform_device *pdev;
        struct omap_device *od;
-        char *pdev_name2;
-        struct resource *res = NULL;
-        int i, res_count;
-        struct omap_hwmod **hwmods;
        if (!ohs || oh_cnt == 0 || !pdev_name)
                return ERR_PTR(-EINVAL);
@@ -457,72 +667,40 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
        if (!pdata && pdata_len > 0)
                return ERR_PTR(-EINVAL);
-        pr_debug("omap_device: %s: building with %d hwmods\n", pdev_name,
+        pdev = platform_device_alloc(pdev_name, pdev_id);
-                 oh_cnt);
+        if (!pdev) {
+                ret = -ENOMEM;
-        od = kzalloc(sizeof(struct omap_device), GFP_KERNEL);
+                goto odbs_exit;
-        if (!od)
+        }
-                return ERR_PTR(-ENOMEM);
-        od->hwmods_cnt = oh_cnt;
+        /* Set the dev_name early to allow dev_xxx in omap_device_alloc */
+        if (pdev->id != -1)
+                dev_set_name(&pdev->dev, "%s.%d", pdev->name,  pdev->id);
+        else
+                dev_set_name(&pdev->dev, "%s", pdev->name);
-        hwmods = kzalloc(sizeof(struct omap_hwmod *) * oh_cnt,
+        od = omap_device_alloc(pdev, ohs, oh_cnt, pm_lats, pm_lats_cnt);
-                         GFP_KERNEL);
+        if (!od)
-        if (!hwmods)
                goto odbs_exit1;
-        memcpy(hwmods, ohs, sizeof(struct omap_hwmod *) * oh_cnt);
+        ret = platform_device_add_data(pdev, pdata, pdata_len);
-        od->hwmods = hwmods;
-        pdev_name2 = kzalloc(strlen(pdev_name) + 1, GFP_KERNEL);
-        if (!pdev_name2)
-                goto odbs_exit2;
-        strcpy(pdev_name2, pdev_name);
-        od->pdev.name = pdev_name2;
-        od->pdev.id = pdev_id;
-        res_count = omap_device_count_resources(od);
-        if (res_count > 0) {
-                res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL);
-                if (!res)
-                        goto odbs_exit3;
-        }
-        omap_device_fill_resources(od, res);
-        od->pdev.num_resources = res_count;
-        od->pdev.resource = res;
-        ret = platform_device_add_data(&od->pdev, pdata, pdata_len);
        if (ret)
-                goto odbs_exit4;
+                goto odbs_exit2;
-        od->pm_lats = pm_lats;
-        od->pm_lats_cnt = pm_lats_cnt;
        if (is_early_device)
-                ret = omap_early_device_register(od);
+                ret = omap_early_device_register(pdev);
        else
-                ret = omap_device_register(od);
+                ret = omap_device_register(pdev);
-        for (i = 0; i < oh_cnt; i++) {
-                hwmods[i]->od = od;
-                _add_hwmod_clocks_clkdev(od, hwmods[i]);
-        }
        if (ret)
-                goto odbs_exit4;
+                goto odbs_exit2;
-        return od;
+        return pdev;
-odbs_exit4:
-        kfree(res);
-odbs_exit3:
-        kfree(pdev_name2);
 odbs_exit2:
-        kfree(hwmods);
+        omap_device_delete(od);
 odbs_exit1:
-        kfree(od);
+        platform_device_put(pdev);
+odbs_exit:
        pr_err("omap_device: %s: build failed (%d)\n", pdev_name, ret);
@@ -538,11 +716,11 @@ odbs_exit1:
 * platform_early_add_device() on the underlying platform_device.
 * Returns 0 by default.
 */
-int omap_early_device_register(struct omap_device *od)
+static int omap_early_device_register(struct platform_device *pdev)
 {
        struct platform_device *devices[1];
-        devices[0] = &(od->pdev);
+        devices[0] = pdev;
        early_platform_add_devices(devices, 1);
        return 0;
 }
@@ -638,13 +816,13 @@ static struct dev_pm_domain omap_device_pm_domain = {
 * platform_device_register() on the underlying platform_device.
 * Returns the return value of platform_device_register().
 */
-int omap_device_register(struct omap_device *od)
+static int omap_device_register(struct platform_device *pdev)
 {
-        pr_debug("omap_device: %s: registering\n", od->pdev.name);
+        pr_debug("omap_device: %s: registering\n", pdev->name);
-        od->pdev.dev.parent = &omap_device_parent;
+        pdev->dev.parent = &omap_device_parent;
-        od->pdev.dev.pm_domain = &omap_device_pm_domain;
+        pdev->dev.pm_domain = &omap_device_pm_domain;
-        return platform_device_register(&od->pdev);
+        return platform_device_add(pdev);
 }
@@ -671,8 +849,9 @@ int omap_device_enable(struct platform_device *pdev)
        od = to_omap_device(pdev);
        if (od->_state == OMAP_DEVICE_STATE_ENABLED) {
-                WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n",
+                dev_warn(&pdev->dev,
-                     od->pdev.name, od->pdev.id, __func__, od->_state);
+                         "omap_device: %s() called from invalid state %d\n",
+                         __func__, od->_state);
                return -EINVAL;
        }
@@ -710,8 +889,9 @@ int omap_device_idle(struct platform_device *pdev)
        od = to_omap_device(pdev);
        if (od->_state != OMAP_DEVICE_STATE_ENABLED) {
-                WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n",
+                dev_warn(&pdev->dev,
-                     od->pdev.name, od->pdev.id, __func__, od->_state);
+                         "omap_device: %s() called from invalid state %d\n",
+                         __func__, od->_state);
                return -EINVAL;
        }
@@ -742,8 +922,9 @@ int omap_device_shutdown(struct platform_device *pdev)
        if (od->_state != OMAP_DEVICE_STATE_ENABLED &&
            od->_state != OMAP_DEVICE_STATE_IDLE) {
-                WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n",
+                dev_warn(&pdev->dev,
-                     od->pdev.name, od->pdev.id, __func__, od->_state);
+                         "omap_device: %s() called from invalid state %d\n",
+                         __func__, od->_state);
                return -EINVAL;
        }
@@ -837,6 +1018,42 @@ void __iomem *omap_device_get_rt_va(struct omap_device *od)
        return omap_hwmod_get_mpu_rt_va(od->hwmods[0]);
 }
+/**
+ * omap_device_get_by_hwmod_name() - convert a hwmod name to
+ * device pointer.
+ * @oh_name: name of the hwmod device
+ *
+ * Returns back a struct device * pointer associated with a hwmod
+ * device represented by a hwmod_name
+ */
+struct device *omap_device_get_by_hwmod_name(const char *oh_name)
+{
+        struct omap_hwmod *oh;
+        if (!oh_name) {
+                WARN(1, "%s: no hwmod name!\n", __func__);
+                return ERR_PTR(-EINVAL);
+        }
+        oh = omap_hwmod_lookup(oh_name);
+        if (IS_ERR_OR_NULL(oh)) {
+                WARN(1, "%s: no hwmod for %s\n", __func__,
+                        oh_name);
+                return ERR_PTR(oh ? PTR_ERR(oh) : -ENODEV);
+        }
+        if (IS_ERR_OR_NULL(oh->od)) {
+                WARN(1, "%s: no omap_device for %s\n", __func__,
+                        oh_name);
+                return ERR_PTR(oh->od ? PTR_ERR(oh->od) : -ENODEV);
+        }
+        if (IS_ERR_OR_NULL(oh->od->pdev))
+                return ERR_PTR(oh->od->pdev ? PTR_ERR(oh->od->pdev) : -ENODEV);
+        return &oh->od->pdev->dev;
+}
+EXPORT_SYMBOL(omap_device_get_by_hwmod_name);
 /*
 * Public functions intended for use in omap_device_pm_latency
 * .activate_func and .deactivate_func function pointers
@@ -917,8 +1134,13 @@ struct device omap_device_parent = {
        .parent         = &platform_bus,
 };
+static struct notifier_block platform_nb = {
+        .notifier_call = _omap_device_notifier_call,
+};
 static int __init omap_device_init(void)
 {
+        bus_register_notifier(&platform_bus_type, &platform_nb);
        return device_register(&omap_device_parent);
 }
 core_initcall(omap_device_init);
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 363c91e44efb..8b28664d1c62 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -19,7 +19,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
-#include <linux/omapfb.h>
 #include <asm/tlb.h>
 #include <asm/cacheflush.h>
@@ -29,10 +28,8 @@
 #include <plat/sram.h>
 #include <plat/board.h>
 #include <plat/cpu.h>
-#include <plat/vram.h>
 #include "sram.h"
-#include "fb.h"
 /* XXX These "sideways" includes are a sign that something is wrong */
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
@@ -41,16 +38,9 @@
 #endif
 #define OMAP1_SRAM_PA           0x20000000
-#define OMAP1_SRAM_VA           VMALLOC_END
 #define OMAP2_SRAM_PUB_PA       (OMAP2_SRAM_PA + 0xf800)
-#define OMAP2_SRAM_VA           0xfe400000
-#define OMAP2_SRAM_PUB_VA       (OMAP2_SRAM_VA + 0x800)
-#define OMAP3_SRAM_VA           0xfe400000
 #define OMAP3_SRAM_PUB_PA       (OMAP3_SRAM_PA + 0x8000)
-#define OMAP3_SRAM_PUB_VA       (OMAP3_SRAM_VA + 0x8000)
-#define OMAP4_SRAM_VA           0xfe400000
 #define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
-#define OMAP4_SRAM_PUB_VA       (OMAP4_SRAM_VA + 0x4000)
 #if defined(CONFIG_ARCH_OMAP2PLUS)
 #define SRAM_BOOTLOADER_SZ      0x00
@@ -73,9 +63,9 @@
 #define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
 static unsigned long omap_sram_start;
-static unsigned long omap_sram_base;
+static void __iomem *omap_sram_base;
 static unsigned long omap_sram_size;
-static unsigned long omap_sram_ceil;
+static void __iomem *omap_sram_ceil;
 /*
 * Depending on the target RAMFS firewall setup, the public usable amount of
@@ -112,12 +102,9 @@ static int is_sram_locked(void)
 */
 static void __init omap_detect_sram(void)
 {
-        unsigned long reserved;
        if (cpu_class_is_omap2()) {
                if (is_sram_locked()) {
                        if (cpu_is_omap34xx()) {
-                                omap_sram_base = OMAP3_SRAM_PUB_VA;
                                omap_sram_start = OMAP3_SRAM_PUB_PA;
                                if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
                                    (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
@@ -126,25 +113,20 @@ static void __init omap_detect_sram(void)
                                        omap_sram_size = 0x8000; /* 32K */
                                }
                        } else if (cpu_is_omap44xx()) {
-                                omap_sram_base = OMAP4_SRAM_PUB_VA;
                                omap_sram_start = OMAP4_SRAM_PUB_PA;
                                omap_sram_size = 0xa000; /* 40K */
                        } else {
-                                omap_sram_base = OMAP2_SRAM_PUB_VA;
                                omap_sram_start = OMAP2_SRAM_PUB_PA;
                                omap_sram_size = 0x800; /* 2K */
                        }
                } else {
                        if (cpu_is_omap34xx()) {
-                                omap_sram_base = OMAP3_SRAM_VA;
                                omap_sram_start = OMAP3_SRAM_PA;
                                omap_sram_size = 0x10000; /* 64K */
                        } else if (cpu_is_omap44xx()) {
-                                omap_sram_base = OMAP4_SRAM_VA;
                                omap_sram_start = OMAP4_SRAM_PA;
                                omap_sram_size = 0xe000; /* 56K */
                        } else {
-                                omap_sram_base = OMAP2_SRAM_VA;
                                omap_sram_start = OMAP2_SRAM_PA;
                                if (cpu_is_omap242x())
                                        omap_sram_size = 0xa0000; /* 640K */
@@ -153,7 +135,6 @@ static void __init omap_detect_sram(void)
                        }
                }
        } else {
-                omap_sram_base = OMAP1_SRAM_VA;
                omap_sram_start = OMAP1_SRAM_PA;
                if (cpu_is_omap7xx())
@@ -170,35 +151,14 @@ static void __init omap_detect_sram(void)
                        omap_sram_size = 0x4000;
                }
        }
-        reserved = omapfb_reserve_sram(omap_sram_start, omap_sram_base,
-                                       omap_sram_size,
-                                       omap_sram_start + SRAM_BOOTLOADER_SZ,
-                                       omap_sram_size - SRAM_BOOTLOADER_SZ);
-        omap_sram_size -= reserved;
-        reserved = omap_vram_reserve_sram(omap_sram_start, omap_sram_base,
-                        omap_sram_size,
-                        omap_sram_start + SRAM_BOOTLOADER_SZ,
-                        omap_sram_size - SRAM_BOOTLOADER_SZ);
-        omap_sram_size -= reserved;
-        omap_sram_ceil = omap_sram_base + omap_sram_size;
 }
-static struct map_desc omap_sram_io_desc[] __initdata = {
-        {       /* .length gets filled in at runtime */
-                .virtual        = OMAP1_SRAM_VA,
-                .pfn            = __phys_to_pfn(OMAP1_SRAM_PA),
-                .type           = MT_MEMORY
-        }
-};
 /*
 * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
 */
 static void __init omap_map_sram(void)
 {
-        unsigned long base;
+        int cached = 1;
        if (omap_sram_size == 0)
                return;
@@ -211,28 +171,18 @@ static void __init omap_map_sram(void)
                 * the ARM may attempt to write cache lines back to SDRAM
                 * which will cause the system to hang.
                 */
-                omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED;
+                cached = 0;
        }
-        omap_sram_io_desc[0].virtual = omap_sram_base;
+        omap_sram_start = ROUND_DOWN(omap_sram_start, PAGE_SIZE);
-        base = omap_sram_start;
+        omap_sram_base = __arm_ioremap_exec(omap_sram_start, omap_sram_size,
-        base = ROUND_DOWN(base, PAGE_SIZE);
+                                                cached);
-        omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
+        if (!omap_sram_base) {
-        omap_sram_io_desc[0].length = ROUND_DOWN(omap_sram_size, PAGE_SIZE);
+                pr_err("SRAM: Could not map\n");
-        iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
+                return;
+        }
-        pr_info("SRAM: Mapped pa 0x%08llx to va 0x%08lx size: 0x%lx\n",
-                (long long) __pfn_to_phys(omap_sram_io_desc[0].pfn),
-                omap_sram_io_desc[0].virtual,
-                omap_sram_io_desc[0].length);
-        /*
+        omap_sram_ceil = omap_sram_base + omap_sram_size;
-         * Normally devicemaps_init() would flush caches and tlb after
-         * mdesc->map_io(), but since we're called from map_io(), we
-         * must do it here.
-         */
-        local_flush_tlb_all();
-        flush_cache_all();
        /*
         * Looks like we need to preserve some bootloader code at the
@@ -251,13 +201,18 @@ static void __init omap_map_sram(void)
 */
 void *omap_sram_push_address(unsigned long size)
 {
-        if (size > (omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ))) {
+        unsigned long available, new_ceil = (unsigned long)omap_sram_ceil;
+        available = omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ);
+        if (size > available) {
                pr_err("Not enough space in SRAM\n");
                return NULL;
        }
-        omap_sram_ceil -= size;
+        new_ceil -= size;
-        omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, FNCPY_ALIGN);
+        new_ceil = ROUND_DOWN(new_ceil, FNCPY_ALIGN);
+        omap_sram_ceil = IOMEM(new_ceil);
        return (void *)omap_sram_ceil;
 }
diff --git a/arch/arm/plat-pxa/include/plat/mfp.h b/arch/arm/plat-pxa/include/plat/mfp.h
index 89e68e07b0a8..5c79c29f2833 100644
--- a/arch/arm/plat-pxa/include/plat/mfp.h
+++ b/arch/arm/plat-pxa/include/plat/mfp.h
@@ -456,7 +456,7 @@ struct mfp_addr_map {
 #define MFP_ADDR_END    { MFP_PIN_INVALID, 0 }
-void __init mfp_init_base(unsigned long mfpr_base);
+void __init mfp_init_base(void __iomem *mfpr_base);
 void __init mfp_init_addr(struct mfp_addr_map *map);
 /*
diff --git a/arch/arm/plat-pxa/mfp.c b/arch/arm/plat-pxa/mfp.c
index be12eadcce20..2c4dbb1f4236 100644
--- a/arch/arm/plat-pxa/mfp.c
+++ b/arch/arm/plat-pxa/mfp.c
@@ -229,7 +229,7 @@ void mfp_write(int mfp, unsigned long val)
        spin_unlock_irqrestore(&mfp_spin_lock, flags);
 }
-void __init mfp_init_base(unsigned long mfpr_base)
+void __init mfp_init_base(void __iomem *mfpr_base)
 {
        int i;
@@ -237,7 +237,7 @@ void __init mfp_init_base(unsigned long mfpr_base)
        for (i = 0; i < ARRAY_SIZE(mfp_table); i++)
                mfp_table[i].config = -1;
-        mfpr_mmio_base = (void __iomem *)mfpr_base;
+        mfpr_mmio_base = mfpr_base;
 }
 void __init mfp_init_addr(struct mfp_addr_map *map)
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index c1fc6c6fac72..3c6335307fb1 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -215,19 +215,18 @@ static void s3c24xx_pm_restart(char mode, const char *cmd)
 void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
 {
-        unsigned long idcode = 0x0;
        /* initialise the io descriptors we need for initialisation */
        iotable_init(mach_desc, size);
        iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
        if (cpu_architecture() >= CPU_ARCH_ARMv5) {
-                idcode = s3c24xx_read_idcode_v5();
+                samsung_cpu_id = s3c24xx_read_idcode_v5();
        } else {
-                idcode = s3c24xx_read_idcode_v4();
+                samsung_cpu_id = s3c24xx_read_idcode_v4();
        }
+        s3c24xx_init_cpu();
        arm_pm_restart = s3c24xx_pm_restart;
-        s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
+        s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 }
diff --git a/arch/arm/plat-s3c24xx/include/plat/map.h b/arch/arm/plat-s3c24xx/include/plat/map.h
deleted file mode 100644
index bd534d32b993..000000000000
--- a/arch/arm/plat-s3c24xx/include/plat/map.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/map.h
- *
- * Copyright (c) 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C24XX - Memory map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_PLAT_S3C24XX_MAP_H
-#define __ASM_PLAT_S3C24XX_MAP_H
-/* interrupt controller is the first thing we put in, to make
- * the assembly code for the irq detection easier
- */
-#define S3C24XX_VA_IRQ     S3C_VA_IRQ
-#define S3C2410_PA_IRQ     (0x4A000000)
-#define S3C24XX_SZ_IRQ     SZ_1M
-/* memory controller registers */
-#define S3C24XX_VA_MEMCTRL S3C_VA_MEM
-#define S3C2410_PA_MEMCTRL (0x48000000)
-#define S3C24XX_SZ_MEMCTRL SZ_1M
-/* UARTs */
-#define S3C24XX_VA_UART    S3C_VA_UART
-#define S3C2410_PA_UART    (0x50000000)
-#define S3C24XX_SZ_UART    SZ_1M
-#define S3C_UART_OFFSET    (0x4000)
-#define S3C_VA_UARTx(uart) (S3C_VA_UART + ((uart * S3C_UART_OFFSET)))
-/* Timers */
-#define S3C24XX_VA_TIMER   S3C_VA_TIMER
-#define S3C2410_PA_TIMER   (0x51000000)
-#define S3C24XX_SZ_TIMER   SZ_1M
-/* Clock and Power management */
-#define S3C24XX_VA_CLKPWR  S3C_VA_SYS
-#define S3C24XX_SZ_CLKPWR  SZ_1M
-/* USB Device port */
-#define S3C2410_PA_USBDEV  (0x52000000)
-#define S3C24XX_SZ_USBDEV  SZ_1M
-/* Watchdog */
-#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG
-#define S3C2410_PA_WATCHDOG (0x53000000)
-#define S3C24XX_SZ_WATCHDOG SZ_1M
-/* Standard size definitions for peripheral blocks. */
-#define S3C24XX_SZ_IIS          SZ_1M
-#define S3C24XX_SZ_ADC          SZ_1M
-#define S3C24XX_SZ_SPI          SZ_1M
-#define S3C24XX_SZ_SDI          SZ_1M
-#define S3C24XX_SZ_NAND         SZ_1M
-/* GPIO ports */
-/* the calculation for the VA of this must ensure that
- * it is the same distance apart from the UART in the
- * phsyical address space, as the initial mapping for the IO
- * is done as a 1:1 mapping. This puts it (currently) at
- * 0xFA800000, which is not in the way of any current mapping
- * by the base system.
-*/
-#define S3C2410_PA_GPIO    (0x56000000)
-#define S3C24XX_VA_GPIO    ((S3C24XX_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
-#define S3C24XX_SZ_GPIO    SZ_1M
-/* ISA style IO, for each machine to sort out mappings for, if it
- * implements it. We reserve two 16M regions for ISA.
- */
-#define S3C24XX_VA_ISA_WORD  S3C2410_ADDR(0x02000000)
-#define S3C24XX_VA_ISA_BYTE  S3C2410_ADDR(0x03000000)
-/* deal with the registers that move under the 2412/2413 */
-#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
-#ifndef __ASSEMBLY__
-extern void __iomem *s3c24xx_va_gpio2;
-#endif
-#ifdef CONFIG_CPU_S3C2412_ONLY
-#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
-#else
-#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
-#endif
-#else
-#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
-#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
-#endif
-#endif /* __ASM_PLAT_S3C24XX_MAP_H */
diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
index bbc2aa7449ca..7b0a28f73a68 100644
--- a/arch/arm/plat-s5p/cpu.c
+++ b/arch/arm/plat-s5p/cpu.c
@@ -33,48 +33,66 @@ static const char name_s5p6450[] = "S5P6450";
 static const char name_s5pc100[] = "S5PC100";
 static const char name_s5pv210[] = "S5PV210/S5PC110";
 static const char name_exynos4210[] = "EXYNOS4210";
+static const char name_exynos4212[] = "EXYNOS4212";
+static const char name_exynos4412[] = "EXYNOS4412";
 static struct cpu_table cpu_ids[] __initdata = {
        {
-                .idcode         = 0x56440100,
+                .idcode         = S5P6440_CPU_ID,
-                .idmask         = 0xfffff000,
+                .idmask         = S5P64XX_CPU_MASK,
                .map_io         = s5p6440_map_io,
                .init_clocks    = s5p6440_init_clocks,
                .init_uarts     = s5p6440_init_uarts,
                .init           = s5p64x0_init,
                .name           = name_s5p6440,
        }, {
-                .idcode         = 0x36450000,
+                .idcode         = S5P6450_CPU_ID,
-                .idmask         = 0xfffff000,
+                .idmask         = S5P64XX_CPU_MASK,
                .map_io         = s5p6450_map_io,
                .init_clocks    = s5p6450_init_clocks,
                .init_uarts     = s5p6450_init_uarts,
                .init           = s5p64x0_init,
                .name           = name_s5p6450,
        }, {
-                .idcode         = 0x43100000,
+                .idcode         = S5PC100_CPU_ID,
-                .idmask         = 0xfffff000,
+                .idmask         = S5PC100_CPU_MASK,
                .map_io         = s5pc100_map_io,
                .init_clocks    = s5pc100_init_clocks,
                .init_uarts     = s5pc100_init_uarts,
                .init           = s5pc100_init,
                .name           = name_s5pc100,
        }, {
-                .idcode         = 0x43110000,
+                .idcode         = S5PV210_CPU_ID,
-                .idmask         = 0xfffff000,
+                .idmask         = S5PV210_CPU_MASK,
                .map_io         = s5pv210_map_io,
                .init_clocks    = s5pv210_init_clocks,
                .init_uarts     = s5pv210_init_uarts,
                .init           = s5pv210_init,
                .name           = name_s5pv210,
        }, {
-                .idcode         = 0x43210000,
+                .idcode         = EXYNOS4210_CPU_ID,
-                .idmask         = 0xfffe0000,
+                .idmask         = EXYNOS4_CPU_MASK,
                .map_io         = exynos4_map_io,
                .init_clocks    = exynos4_init_clocks,
                .init_uarts     = exynos4_init_uarts,
                .init           = exynos4_init,
                .name           = name_exynos4210,
+        }, {
+                .idcode         = EXYNOS4212_CPU_ID,
+                .idmask         = EXYNOS4_CPU_MASK,
+                .map_io         = exynos4_map_io,
+                .init_clocks    = exynos4_init_clocks,
+                .init_uarts     = exynos4_init_uarts,
+                .init           = exynos4_init,
+                .name           = name_exynos4212,
+        }, {
+                .idcode         = EXYNOS4412_CPU_ID,
+                .idmask         = EXYNOS4_CPU_MASK,
+                .map_io         = exynos4_map_io,
+                .init_clocks    = exynos4_init_clocks,
+                .init_uarts     = exynos4_init_uarts,
+                .init           = exynos4_init,
+                .name           = name_exynos4412,
        },
 };
@@ -114,13 +132,13 @@ static struct map_desc s5p_iodesc[] __initdata = {
 void __init s5p_init_io(struct map_desc *mach_desc,
                        int size, void __iomem *cpuid_addr)
 {
-        unsigned long idcode;
        /* initialize the io descriptors we need for initialization */
        iotable_init(s5p_iodesc, ARRAY_SIZE(s5p_iodesc));
        if (mach_desc)
                iotable_init(mach_desc, size);
-        idcode = __raw_readl(cpuid_addr);
+        /* detect cpu id and rev. */
-        s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
+        s5p_init_cpu(cpuid_addr);
+        s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 }
diff --git a/arch/arm/plat-s5p/include/plat/exynos4.h b/arch/arm/plat-s5p/include/plat/exynos4.h
index 907caab53dcf..f680a143e38c 100644
--- a/arch/arm/plat-s5p/include/plat/exynos4.h
+++ b/arch/arm/plat-s5p/include/plat/exynos4.h
@@ -14,10 +14,11 @@
 extern void exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void exynos4_register_clocks(void);
+extern void exynos4210_register_clocks(void);
+extern void exynos4212_register_clocks(void);
 extern void exynos4_setup_clocks(void);
-#ifdef CONFIG_CPU_EXYNOS4210
+#ifdef CONFIG_ARCH_EXYNOS4
 extern  int exynos4_init(void);
 extern void exynos4_init_irq(void);
 extern void exynos4_map_io(void);
diff --git a/arch/arm/plat-s5p/include/plat/pll.h b/arch/arm/plat-s5p/include/plat/pll.h
index bf28fadee7ae..3e21b9444cc5 100644
--- a/arch/arm/plat-s5p/include/plat/pll.h
+++ b/arch/arm/plat-s5p/include/plat/pll.h
@@ -12,6 +12,59 @@
 * published by the Free Software Foundation.
 */
+#include <asm/div64.h>
+#define PLL35XX_MDIV_MASK       (0x3FF)
+#define PLL35XX_PDIV_MASK       (0x3F)
+#define PLL35XX_SDIV_MASK       (0x7)
+#define PLL35XX_MDIV_SHIFT      (16)
+#define PLL35XX_PDIV_SHIFT      (8)
+#define PLL35XX_SDIV_SHIFT      (0)
+static inline unsigned long s5p_get_pll35xx(unsigned long baseclk, u32 pll_con)
+{
+        u32 mdiv, pdiv, sdiv;
+        u64 fvco = baseclk;
+        mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
+        pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
+        sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
+        fvco *= mdiv;
+        do_div(fvco, (pdiv << sdiv));
+        return (unsigned long)fvco;
+}
+#define PLL36XX_KDIV_MASK       (0xFFFF)
+#define PLL36XX_MDIV_MASK       (0x1FF)
+#define PLL36XX_PDIV_MASK       (0x3F)
+#define PLL36XX_SDIV_MASK       (0x7)
+#define PLL36XX_MDIV_SHIFT      (16)
+#define PLL36XX_PDIV_SHIFT      (8)
+#define PLL36XX_SDIV_SHIFT      (0)
+static inline unsigned long s5p_get_pll36xx(unsigned long baseclk,
+                                            u32 pll_con0, u32 pll_con1)
+{
+        unsigned long result;
+        u32 mdiv, pdiv, sdiv, kdiv;
+        u64 tmp;
+        mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
+        pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
+        sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
+        kdiv = pll_con1 & PLL36XX_KDIV_MASK;
+        tmp = baseclk;
+        tmp *= (mdiv << 16) + kdiv;
+        do_div(tmp, (pdiv << sdiv));
+        result = tmp >> 16;
+        return result;
+}
 #define PLL45XX_MDIV_MASK       (0x3FF)
 #define PLL45XX_PDIV_MASK       (0x3F)
 #define PLL45XX_SDIV_MASK       (0x7)
@@ -19,8 +72,6 @@
 #define PLL45XX_PDIV_SHIFT      (8)
 #define PLL45XX_SDIV_SHIFT      (0)
-#include <asm/div64.h>
 enum pll45xx_type_t {
        pll_4500,
        pll_4502,
@@ -72,7 +123,6 @@ static inline unsigned long s5p_get_pll46xx(unsigned long baseclk,
        mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
        pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
        sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
-        kdiv = pll_con1 & PLL46XX_KDIV_MASK;
        if (pll_type == pll_4650c)
                kdiv = pll_con1 & PLL4650C_KDIV_MASK;
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index dffa37bc4a0b..3895f9aff0dc 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -362,4 +362,11 @@ config SAMSUNG_PD
        help
          Say Y here if you want to control Power Domain by Runtime PM.
+config DEBUG_S3C_UART
+        depends on PLAT_SAMSUNG
+        int
+        default "0" if DEBUG_S3C_UART0
+        default "1" if DEBUG_S3C_UART1
+        default "2" if DEBUG_S3C_UART2
 endif
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 1105922342fe..09adb84f2718 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -11,7 +11,7 @@ obj-				:=
 # Objects we always build independent of SoC choice
-obj-y                           += init.o
+obj-y                           += init.o cpu.o
 obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET)   += time.o
 obj-y                           += clock.o
 obj-y                           += pwm-clock.o
diff --git a/arch/arm/plat-samsung/cpu.c b/arch/arm/plat-samsung/cpu.c
new file mode 100644
index 000000000000..81c06d44c11e
--- /dev/null
+++ b/arch/arm/plat-samsung/cpu.c
@@ -0,0 +1,58 @@
+/* linux/arch/arm/plat-samsung/cpu.c
+ *
+ * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Samsung CPU Support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <asm/system.h>
+#include <mach/map.h>
+#include <plat/cpu.h>
+unsigned long samsung_cpu_id;
+static unsigned int samsung_cpu_rev;
+unsigned int samsung_rev(void)
+{
+        return samsung_cpu_rev;
+}
+EXPORT_SYMBOL(samsung_rev);
+void __init s3c24xx_init_cpu(void)
+{
+        /* nothing here yet */
+        samsung_cpu_rev = 0;
+}
+void __init s3c64xx_init_cpu(void)
+{
+        samsung_cpu_id = __raw_readl(S3C_VA_SYS + 0x118);
+        if (!samsung_cpu_id) {
+                /*
+                 * S3C6400 has the ID register in a different place,
+                 * and needs a write before it can be read.
+                 */
+                __raw_writel(0x0, S3C_VA_SYS + 0xA1C);
+                samsung_cpu_id = __raw_readl(S3C_VA_SYS + 0xA1C);
+        }
+        samsung_cpu_rev = 0;
+}
+void __init s5p_init_cpu(void __iomem *cpuid_addr)
+{
+        samsung_cpu_id = __raw_readl(cpuid_addr);
+        samsung_cpu_rev = samsung_cpu_id & 0xFF;
+}
diff --git a/arch/arm/plat-samsung/dev-hsmmc.c b/arch/arm/plat-samsung/dev-hsmmc.c
index db7a65c7f127..06825c4276de 100644
--- a/arch/arm/plat-samsung/dev-hsmmc.c
+++ b/arch/arm/plat-samsung/dev-hsmmc.c
@@ -58,22 +58,5 @@ struct platform_device s3c_device_hsmmc0 = {
 void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
 {
-        struct s3c_sdhci_platdata *set = &s3c_hsmmc0_def_platdata;
+        s3c_sdhci_set_platdata(pd, &s3c_hsmmc0_def_platdata);
-        set->cd_type = pd->cd_type;
-        set->ext_cd_init = pd->ext_cd_init;
-        set->ext_cd_cleanup = pd->ext_cd_cleanup;
-        set->ext_cd_gpio = pd->ext_cd_gpio;
-        set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
-        if (pd->max_width)
-                set->max_width = pd->max_width;
-        if (pd->cfg_gpio)
-                set->cfg_gpio = pd->cfg_gpio;
-        if (pd->cfg_card)
-                set->cfg_card = pd->cfg_card;
-        if (pd->host_caps)
-                set->host_caps |= pd->host_caps;
-        if (pd->clk_type)
-                set->clk_type = pd->clk_type;
 }
diff --git a/arch/arm/plat-samsung/dev-hsmmc1.c b/arch/arm/plat-samsung/dev-hsmmc1.c
index 2497321f08d7..4524ef440010 100644
--- a/arch/arm/plat-samsung/dev-hsmmc1.c
+++ b/arch/arm/plat-samsung/dev-hsmmc1.c
@@ -58,22 +58,5 @@ struct platform_device s3c_device_hsmmc1 = {
 void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
 {
-        struct s3c_sdhci_platdata *set = &s3c_hsmmc1_def_platdata;
+        s3c_sdhci_set_platdata(pd, &s3c_hsmmc1_def_platdata);
-        set->cd_type = pd->cd_type;
-        set->ext_cd_init = pd->ext_cd_init;
-        set->ext_cd_cleanup = pd->ext_cd_cleanup;
-        set->ext_cd_gpio = pd->ext_cd_gpio;
-        set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
-        if (pd->max_width)
-                set->max_width = pd->max_width;
-        if (pd->cfg_gpio)
-                set->cfg_gpio = pd->cfg_gpio;
-        if (pd->cfg_card)
-                set->cfg_card = pd->cfg_card;
-        if (pd->host_caps)
-                set->host_caps |= pd->host_caps;
-        if (pd->clk_type)
-                set->clk_type = pd->clk_type;
 }
diff --git a/arch/arm/plat-samsung/dev-hsmmc2.c b/arch/arm/plat-samsung/dev-hsmmc2.c
index f60aedba417c..9cede9615e48 100644
--- a/arch/arm/plat-samsung/dev-hsmmc2.c
+++ b/arch/arm/plat-samsung/dev-hsmmc2.c
@@ -59,22 +59,5 @@ struct platform_device s3c_device_hsmmc2 = {
 void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
 {
-        struct s3c_sdhci_platdata *set = &s3c_hsmmc2_def_platdata;
+        s3c_sdhci_set_platdata(pd, &s3c_hsmmc2_def_platdata);
-        set->cd_type = pd->cd_type;
-        set->ext_cd_init = pd->ext_cd_init;
-        set->ext_cd_cleanup = pd->ext_cd_cleanup;
-        set->ext_cd_gpio = pd->ext_cd_gpio;
-        set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
-        if (pd->max_width)
-                set->max_width = pd->max_width;
-        if (pd->cfg_gpio)
-                set->cfg_gpio = pd->cfg_gpio;
-        if (pd->cfg_card)
-                set->cfg_card = pd->cfg_card;
-        if (pd->host_caps)
-                set->host_caps |= pd->host_caps;
-        if (pd->clk_type)
-                set->clk_type = pd->clk_type;
 }
diff --git a/arch/arm/plat-samsung/dev-hsmmc3.c b/arch/arm/plat-samsung/dev-hsmmc3.c
index ede776f20e62..0358ef4a8f66 100644
--- a/arch/arm/plat-samsung/dev-hsmmc3.c
+++ b/arch/arm/plat-samsung/dev-hsmmc3.c
@@ -62,22 +62,5 @@ struct platform_device s3c_device_hsmmc3 = {
 void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd)
 {
-        struct s3c_sdhci_platdata *set = &s3c_hsmmc3_def_platdata;
+        s3c_sdhci_set_platdata(pd, &s3c_hsmmc3_def_platdata);
-        set->cd_type = pd->cd_type;
-        set->ext_cd_init = pd->ext_cd_init;
-        set->ext_cd_cleanup = pd->ext_cd_cleanup;
-        set->ext_cd_gpio = pd->ext_cd_gpio;
-        set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
-        if (pd->max_width)
-                set->max_width = pd->max_width;
-        if (pd->cfg_gpio)
-                set->cfg_gpio = pd->cfg_gpio;
-        if (pd->cfg_card)
-                set->cfg_card = pd->cfg_card;
-        if (pd->host_caps)
-                set->host_caps |= pd->host_caps;
-        if (pd->clk_type)
-                set->clk_type = pd->clk_type;
 }
diff --git a/arch/arm/plat-samsung/dev-ts.c b/arch/arm/plat-samsung/dev-ts.c
index 82543f0248ac..5f3d46a9bd88 100644
--- a/arch/arm/plat-samsung/dev-ts.c
+++ b/arch/arm/plat-samsung/dev-ts.c
@@ -43,8 +43,17 @@ struct platform_device s3c_device_ts = {
        .resource       = s3c_ts_resource,
 };
+static struct s3c2410_ts_mach_info default_ts_data __initdata = {
+        .delay                  = 10000,
+        .presc                  = 49,
+        .oversampling_shift     = 2,
+};
 void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd)
 {
+        if (!pd)
+                pd = &default_ts_data;
        s3c_set_platdata(pd, sizeof(struct s3c2410_ts_mach_info),
                         &s3c_device_ts);
 }
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index c0a5741b23e6..54f370f0fc07 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -1,9 +1,12 @@
 /* linux/arch/arm/plat-samsung/include/plat/cpu.h
 *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
 * Copyright (c) 2004-2005 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
- * Header file for S3C24XX CPU support
+ * Header file for Samsung CPU support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
@@ -15,6 +18,108 @@
 #ifndef __SAMSUNG_PLAT_CPU_H
 #define __SAMSUNG_PLAT_CPU_H
+extern unsigned long samsung_cpu_id;
+#define S3C24XX_CPU_ID          0x32400000
+#define S3C24XX_CPU_MASK        0xFFF00000
+#define S3C6400_CPU_ID          0x36400000
+#define S3C6410_CPU_ID          0x36410000
+#define S3C64XX_CPU_ID          (S3C6400_CPU_ID & S3C6410_CPU_ID)
+#define S3C64XX_CPU_MASK        0xFFFFF000
+#define S5P6440_CPU_ID          0x56440000
+#define S5P6450_CPU_ID          0x36450000
+#define S5P64XX_CPU_MASK        0xFFFFF000
+#define S5PC100_CPU_ID          0x43100000
+#define S5PC100_CPU_MASK        0xFFFFF000
+#define S5PV210_CPU_ID          0x43110000
+#define S5PV210_CPU_MASK        0xFFFFF000
+#define EXYNOS4210_CPU_ID       0x43210000
+#define EXYNOS4212_CPU_ID       0x43220000
+#define EXYNOS4412_CPU_ID       0xE4412200
+#define EXYNOS4_CPU_MASK        0xFFFE0000
+#define IS_SAMSUNG_CPU(name, id, mask)          \
+static inline int is_samsung_##name(void)       \
+{                                               \
+        return ((samsung_cpu_id & mask) == (id & mask));        \
+}
+IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK)
+IS_SAMSUNG_CPU(s3c64xx, S3C64XX_CPU_ID, S3C64XX_CPU_MASK)
+IS_SAMSUNG_CPU(s5p6440, S5P6440_CPU_ID, S5P64XX_CPU_MASK)
+IS_SAMSUNG_CPU(s5p6450, S5P6450_CPU_ID, S5P64XX_CPU_MASK)
+IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK)
+IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
+IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
+IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
+IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
+#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
+    defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
+    defined(CONFIG_CPU_S3C2442) || defined(CONFIG_CPU_S3C244X) || \
+    defined(CONFIG_CPU_S3C2443)
+# define soc_is_s3c24xx()       is_samsung_s3c24xx()
+#else
+# define soc_is_s3c24xx()       0
+#endif
+#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
+# define soc_is_s3c64xx()       is_samsung_s3c64xx()
+#else
+# define soc_is_s3c64xx()       0
+#endif
+#if defined(CONFIG_CPU_S5P6440)
+# define soc_is_s5p6440()       is_samsung_s5p6440()
+#else
+# define soc_is_s5p6440()       0
+#endif
+#if defined(CONFIG_CPU_S5P6450)
+# define soc_is_s5p6450()       is_samsung_s5p6450()
+#else
+# define soc_is_s5p6450()       0
+#endif
+#if defined(CONFIG_CPU_S5PC100)
+# define soc_is_s5pc100()       is_samsung_s5pc100()
+#else
+# define soc_is_s5pc100()       0
+#endif
+#if defined(CONFIG_CPU_S5PV210)
+# define soc_is_s5pv210()       is_samsung_s5pv210()
+#else
+# define soc_is_s5pv210()       0
+#endif
+#if defined(CONFIG_CPU_EXYNOS4210)
+# define soc_is_exynos4210()    is_samsung_exynos4210()
+#else
+# define soc_is_exynos4210()    0
+#endif
+#if defined(CONFIG_SOC_EXYNOS4212)
+# define soc_is_exynos4212()    is_samsung_exynos4212()
+#else
+# define soc_is_exynos4212()    0
+#endif
+#if defined(CONFIG_SOC_EXYNOS4412)
+# define soc_is_exynos4412()    is_samsung_exynos4412()
+#else
+# define soc_is_exynos4412()    0
+#endif
+#define EXYNOS4210_REV_0        (0x0)
+#define EXYNOS4210_REV_1_0      (0x10)
+#define EXYNOS4210_REV_1_1      (0x11)
 #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
 #ifndef MHZ
@@ -55,6 +160,12 @@ extern void s3c64xx_init_io(struct map_desc *mach_desc, int size);
 extern void s5p_init_io(struct map_desc *mach_desc,
                        int size, void __iomem *cpuid_addr);
+extern void s3c24xx_init_cpu(void);
+extern void s3c64xx_init_cpu(void);
+extern void s5p_init_cpu(void __iomem *cpuid_addr);
+extern unsigned int samsung_rev(void);
 extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c24xx_init_clocks(int xtal);
diff --git a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
index 336d5ac02035..ab9bce637cbd 100644
--- a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
+++ b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
@@ -18,11 +18,6 @@ extern struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
 #define DMA_CH_VALID            (1<<31)
 #define DMA_CH_NEVER            (1<<30)
-struct s3c24xx_dma_addr {
-        unsigned long           from;
-        unsigned long           to;
-};
 /* struct s3c24xx_dma_map
 *
 * this holds the mapping information for the channel selected
@@ -31,7 +26,6 @@ struct s3c24xx_dma_addr {
 struct s3c24xx_dma_map {
        const char              *name;
-        struct s3c24xx_dma_addr  hw_addr;
        unsigned long            channels[S3C_DMA_CHANNELS];
        unsigned long            channels_rx[S3C_DMA_CHANNELS];
diff --git a/arch/arm/plat-samsung/include/plat/map-s3c.h b/arch/arm/plat-samsung/include/plat/map-s3c.h
new file mode 100644
index 000000000000..7d048759b772
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/map-s3c.h
@@ -0,0 +1,84 @@
+/* linux/arch/arm/plat-samsung/include/plat/map-s3c.h
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __ASM_PLAT_MAP_S3C_H
+#define __ASM_PLAT_MAP_S3C_H __FILE__
+#define S3C24XX_VA_IRQ          S3C_VA_IRQ
+#define S3C24XX_VA_MEMCTRL      S3C_VA_MEM
+#define S3C24XX_VA_UART         S3C_VA_UART
+#define S3C24XX_VA_TIMER        S3C_VA_TIMER
+#define S3C24XX_VA_CLKPWR       S3C_VA_SYS
+#define S3C24XX_VA_WATCHDOG     S3C_VA_WATCHDOG
+#define S3C2412_VA_SSMC         S3C_ADDR_CPU(0x00000000)
+#define S3C2412_VA_EBI          S3C_ADDR_CPU(0x00010000)
+#define S3C2410_PA_UART         (0x50000000)
+#define S3C24XX_PA_UART         S3C2410_PA_UART
+#ifndef S3C_UART_OFFSET
+#define S3C_UART_OFFSET         (0x400)
+#endif
+/*
+ * GPIO ports
+ *
+ * the calculation for the VA of this must ensure that
+ * it is the same distance apart from the UART in the
+ * phsyical address space, as the initial mapping for the IO
+ * is done as a 1:1 mapping. This puts it (currently) at
+ * 0xFA800000, which is not in the way of any current mapping
+ * by the base system.
+*/
+#define S3C2410_PA_GPIO         (0x56000000)
+#define S3C24XX_PA_GPIO         S3C2410_PA_GPIO
+#define S3C24XX_VA_GPIO         ((S3C24XX_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
+#define S3C64XX_VA_GPIO         S3C_ADDR_CPU(0x00000000)
+#define S3C64XX_VA_MODEM        S3C_ADDR_CPU(0x00100000)
+#define S3C64XX_VA_USB_HSPHY    S3C_ADDR_CPU(0x00200000)
+#define S3C_VA_USB_HSPHY        S3C64XX_VA_USB_HSPHY
+/*
+ * ISA style IO, for each machine to sort out mappings for,
+ * if it implements it. We reserve two 16M regions for ISA.
+ */
+#define S3C2410_ADDR(x)         S3C_ADDR(x)
+#define S3C24XX_VA_ISA_WORD     S3C2410_ADDR(0x02000000)
+#define S3C24XX_VA_ISA_BYTE     S3C2410_ADDR(0x03000000)
+/* deal with the registers that move under the 2412/2413 */
+#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
+#ifndef __ASSEMBLY__
+extern void __iomem *s3c24xx_va_gpio2;
+#endif
+#ifdef CONFIG_CPU_S3C2412_ONLY
+#define S3C24XX_VA_GPIO2        (S3C24XX_VA_GPIO + 0x10)
+#else
+#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
+#endif
+#else
+#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
+#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
+#endif
+#include <plat/map-s5p.h>
+#endif /* __ASM_PLAT_MAP_S3C_H */
diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-samsung/include/plat/map-s5p.h
index 36d3551173b2..c2d7bdae5891 100644
--- a/arch/arm/plat-s5p/include/plat/map-s5p.h
+++ b/arch/arm/plat-samsung/include/plat/map-s5p.h
@@ -1,4 +1,4 @@
-/* linux/arch/arm/plat-s5p/include/plat/map-s5p.h
+/* linux/arch/arm/plat-samsung/include/plat/map-s5p.h
 *
 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
 *              http://www.samsung.com/
@@ -40,8 +40,6 @@
 #define S5P_VA_GIC_CPU          S3C_ADDR(0x02810000)
 #define S5P_VA_GIC_DIST         S3C_ADDR(0x02820000)
-#define S3C_VA_USB_HSPHY        S3C_ADDR(0x02900000)
 #define VA_VIC(x)               (S3C_VA_IRQ + ((x) * 0x10000))
 #define VA_VIC0                 VA_VIC(0)
 #define VA_VIC1                 VA_VIC(1)
@@ -58,4 +56,6 @@
 #define S3C_UART_OFFSET         (0x400)
 #endif
+#include <plat/map-s3c.h>
 #endif /* __ASM_PLAT_MAP_S5P_H */
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 058e09654fe8..4a6552066c7e 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -86,6 +86,13 @@ struct s3c_sdhci_platdata {
                            struct mmc_card *card);
 };
+/* s3c_sdhci_set_platdata() - common helper for setting SDHCI platform data
+ * @pd: The default platform data for this device.
+ * @set: Pointer to the platform data to fill in.
+ */
+extern void s3c_sdhci_set_platdata(struct s3c_sdhci_platdata *pd,
+                                    struct s3c_sdhci_platdata *set);
 /**
 * s3c_sdhci0_set_platdata - Set platform data for S3C SDHCI device.
 * @pd: Platform data to register to device.
diff --git a/arch/arm/plat-samsung/platformdata.c b/arch/arm/plat-samsung/platformdata.c
index 7cf2e1e3b20f..6de1a3825927 100644
--- a/arch/arm/plat-samsung/platformdata.c
+++ b/arch/arm/plat-samsung/platformdata.c
@@ -14,6 +14,7 @@
 #include <linux/platform_device.h>
 #include <plat/devs.h>
+#include <plat/sdhci.h>
 void __init *s3c_set_platdata(void *pd, size_t pdsize,
                              struct platform_device *pdev)
@@ -35,3 +36,24 @@ void __init *s3c_set_platdata(void *pd, size_t pdsize,
        pdev->dev.platform_data = npd;
        return npd;
 }
+void s3c_sdhci_set_platdata(struct s3c_sdhci_platdata *pd,
+                             struct s3c_sdhci_platdata *set)
+{
+        set->cd_type = pd->cd_type;
+        set->ext_cd_init = pd->ext_cd_init;
+        set->ext_cd_cleanup = pd->ext_cd_cleanup;
+        set->ext_cd_gpio = pd->ext_cd_gpio;
+        set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
+        if (pd->max_width)
+                set->max_width = pd->max_width;
+        if (pd->cfg_gpio)
+                set->cfg_gpio = pd->cfg_gpio;
+        if (pd->cfg_card)
+                set->cfg_card = pd->cfg_card;
+        if (pd->host_caps)
+                set->host_caps |= pd->host_caps;
+        if (pd->clk_type)
+                set->clk_type = pd->clk_type;
+}
diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c
index 51ecfea09b27..92f18d372b69 100644
--- a/arch/arm/plat-versatile/platsmp.c
+++ b/arch/arm/plat-versatile/platsmp.c
@@ -77,7 +77,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
         * since we haven't sent them a soft interrupt, they shouldn't
         * be there.
         */
-        write_pen_release(cpu);
+        write_pen_release(cpu_logical_map(cpu));
        /*
         * Send the secondary CPU a soft interrupt, thereby causing
diff --git a/arch/s390/hypfs/inode.c b/arch/s390/hypfs/inode.c
index 6fe874fc5f8e..481f4f76f664 100644
--- a/arch/s390/hypfs/inode.c
+++ b/arch/s390/hypfs/inode.c
@@ -108,9 +108,7 @@ static struct inode *hypfs_make_inode(struct super_block *sb, int mode)
                ret->i_gid = hypfs_info->gid;
                ret->i_atime = ret->i_mtime = ret->i_ctime = CURRENT_TIME;
                if (mode & S_IFDIR)
-                        ret->i_nlink = 2;
+                        set_nlink(ret, 2);
-                else
-                        ret->i_nlink = 1;
        }
        return ret;
 }
@@ -361,7 +359,7 @@ static struct dentry *hypfs_create_file(struct super_block *sb,
        } else if (mode & S_IFDIR) {
                inode->i_op = &simple_dir_inode_operations;
                inode->i_fop = &simple_dir_operations;
-                parent->d_inode->i_nlink++;
+                inc_nlink(parent->d_inode);
        } else
                BUG();
        inode->i_private = data;
diff --git a/arch/um/Kconfig.char b/arch/um/Kconfig.char
index 70dabd1e0652..b9d7c4276682 100644
--- a/arch/um/Kconfig.char
+++ b/arch/um/Kconfig.char
@@ -1,5 +1,4 @@
+menu "UML Character Devices"
-menu "Character Devices"
 config STDERR_CONSOLE
        bool "stderr console"
@@ -105,92 +104,6 @@ config SSL_CHAN
          this if you expect the UML that you build to be run in environments
          which don't have a set of /dev/pty* devices.
-config UNIX98_PTYS
-        bool "Unix98 PTY support"
-        help
-          A pseudo terminal (PTY) is a software device consisting of two
-          halves: a master and a slave. The slave device behaves identical to
-          a physical terminal; the master device is used by a process to
-          read data from and write data to the slave, thereby emulating a
-          terminal. Typical programs for the master side are telnet servers
-          and xterms.
-          Linux has traditionally used the BSD-like names /dev/ptyxx for
-          masters and /dev/ttyxx for slaves of pseudo terminals. This scheme
-          has a number of problems. The GNU C library glibc 2.1 and later,
-          however, supports the Unix98 naming standard: in order to acquire a
-          pseudo terminal, a process opens /dev/ptmx; the number of the pseudo
-          terminal is then made available to the process and the pseudo
-          terminal slave can be accessed as /dev/pts/<number>. What was
-          traditionally /dev/ttyp2 will then be /dev/pts/2, for example.
-          All modern Linux systems use the Unix98 ptys.  Say Y unless
-          you're on an embedded system and want to conserve memory.
-config LEGACY_PTYS
-        bool "Legacy (BSD) PTY support"
-        default y
-        help
-          A pseudo terminal (PTY) is a software device consisting of two
-          halves: a master and a slave. The slave device behaves identical to
-          a physical terminal; the master device is used by a process to
-          read data from and write data to the slave, thereby emulating a
-          terminal. Typical programs for the master side are telnet servers
-          and xterms.
-          Linux has traditionally used the BSD-like names /dev/ptyxx
-          for masters and /dev/ttyxx for slaves of pseudo
-          terminals. This scheme has a number of problems, including
-          security.  This option enables these legacy devices; on most
-          systems, it is safe to say N.
-config RAW_DRIVER
-        tristate "RAW driver (/dev/raw/rawN)"
-        depends on BLOCK
-        help
-          The raw driver permits block devices to be bound to /dev/raw/rawN.
-          Once bound, I/O against /dev/raw/rawN uses efficient zero-copy I/O.
-          See the raw(8) manpage for more details.
-          Applications should preferably open the device (eg /dev/hda1)
-          with the O_DIRECT flag.
-config MAX_RAW_DEVS
-        int "Maximum number of RAW devices to support (1-8192)"
-        depends on RAW_DRIVER
-        default "256"
-        help
-          The maximum number of RAW devices that are supported.
-          Default is 256. Increase this number in case you need lots of
-          raw devices.
-config LEGACY_PTY_COUNT
-        int "Maximum number of legacy PTY in use"
-        depends on LEGACY_PTYS
-        default "256"
-        help
-          The maximum number of legacy PTYs that can be used at any one time.
-          The default is 256, and should be more than enough.  Embedded
-          systems may want to reduce this to save memory.
-          When not in use, each legacy PTY occupies 12 bytes on 32-bit
-          architectures and 24 bytes on 64-bit architectures.
-config WATCHDOG
-        bool "Watchdog Timer Support"
-config WATCHDOG_NOWAYOUT
-        bool "Disable watchdog shutdown on close"
-        depends on WATCHDOG
-config SOFT_WATCHDOG
-        tristate "Software Watchdog"
-        depends on WATCHDOG
-config UML_WATCHDOG
-        tristate "UML watchdog"
-        depends on WATCHDOG
 config UML_SOUND
        tristate "Sound support"
        help
@@ -211,29 +124,4 @@ config HOSTAUDIO
        tristate
        default UML_SOUND
-#It is selected elsewhere, so kconfig would warn without this.
-config HW_RANDOM
-        tristate
-        default n
-config UML_RANDOM
-        tristate "Hardware random number generator"
-        help
-          This option enables UML's "hardware" random number generator.  It
-          attaches itself to the host's /dev/random, supplying as much entropy
-          as the host has, rather than the small amount the UML gets from its
-          own drivers.  It registers itself as a standard hardware random number
-          generator, major 10, minor 183, and the canonical device name is
-          /dev/hwrng.
-          The way to make use of this is to install the rng-tools package
-          (check your distro, or download from
-          http://sourceforge.net/projects/gkernel/).  rngd periodically reads
-          /dev/hwrng and injects the entropy into /dev/random.
-config MMAPPER
-        tristate "iomem emulation driver"
-        help
-          This driver allows a host file to be used as emulated IO memory inside
-          UML.
 endmenu
diff --git a/arch/um/Kconfig.rest b/arch/um/Kconfig.rest
index 0ccad0ff6d6e..567eb5fc21df 100644
--- a/arch/um/Kconfig.rest
+++ b/arch/um/Kconfig.rest
@@ -2,20 +2,14 @@ source "init/Kconfig"
 source "kernel/Kconfig.freezer"
-source "drivers/block/Kconfig"
 source "arch/um/Kconfig.char"
-source "drivers/base/Kconfig"
+source "drivers/Kconfig"
 source "net/Kconfig"
 source "arch/um/Kconfig.net"
-source "drivers/net/Kconfig"
-source "drivers/connector/Kconfig"
 source "fs/Kconfig"
 source "security/Kconfig"
@@ -24,19 +18,4 @@ source "crypto/Kconfig"
 source "lib/Kconfig"
-source "drivers/scsi/Kconfig"
-source "drivers/md/Kconfig"
-if BROKEN
-        source "drivers/mtd/Kconfig"
-endif
-source "drivers/leds/Kconfig"
-#This is just to shut up some Kconfig warnings, so no prompt.
-config INPUT
-        tristate
-        default n
 source "arch/um/Kconfig.debug"
diff --git a/arch/um/Kconfig.um b/arch/um/Kconfig.um
index b5e675e370c6..70fd690964e4 100644
--- a/arch/um/Kconfig.um
+++ b/arch/um/Kconfig.um
@@ -148,5 +148,11 @@ config KERNEL_STACK_ORDER
          be 1 << order pages.  The default is OK unless you're running Valgrind
          on UML, in which case, set this to 3.
+config MMAPPER
+        tristate "iomem emulation driver"
+        help
+          This driver allows a host file to be used as emulated IO memory inside
+          UML.
 config NO_DMA
        def_bool y
diff --git a/arch/um/Makefile b/arch/um/Makefile
index c0f712cc7c5f..7730af6ec13f 100644
--- a/arch/um/Makefile
+++ b/arch/um/Makefile
@@ -20,15 +20,27 @@ core-y			+= $(ARCH_DIR)/kernel/		\
 MODE_INCLUDE    += -I$(srctree)/$(ARCH_DIR)/include/shared/skas
+HEADER_ARCH     := $(SUBARCH)
+# Additional ARCH settings for x86
+ifeq ($(SUBARCH),i386)
+        HEADER_ARCH := x86
+endif
+ifeq ($(SUBARCH),x86_64)
+        HEADER_ARCH := x86
+endif
+HOST_DIR := arch/$(HEADER_ARCH)
 include $(srctree)/$(ARCH_DIR)/Makefile-skas
+include $(srctree)/$(HOST_DIR)/Makefile.um
+core-y += $(HOST_DIR)/um/
 SHARED_HEADERS  := $(ARCH_DIR)/include/shared
 ARCH_INCLUDE    := -I$(srctree)/$(SHARED_HEADERS)
-ARCH_INCLUDE    += -I$(srctree)/$(ARCH_DIR)/sys-$(SUBARCH)/shared
+ARCH_INCLUDE    += -I$(srctree)/$(HOST_DIR)/um/shared
-ifneq ($(KBUILD_SRC),)
+KBUILD_CPPFLAGS += -I$(srctree)/$(HOST_DIR)/um
-ARCH_INCLUDE    += -I$(SHARED_HEADERS)
-endif
-KBUILD_CPPFLAGS += -I$(srctree)/$(ARCH_DIR)/sys-$(SUBARCH)
 # -Dvmap=kernel_vmap prevents anything from referencing the libpcap.o symbol so
 # named - it's a common symbol in libpcap, so we get a binary which crashes.
@@ -47,14 +59,12 @@ KBUILD_AFLAGS += $(ARCH_INCLUDE)
 USER_CFLAGS = $(patsubst $(KERNEL_DEFINES),,$(patsubst -D__KERNEL__,,\
        $(patsubst -I%,,$(KBUILD_CFLAGS)))) $(ARCH_INCLUDE) $(MODE_INCLUDE) \
-        $(filter -I%,$(CFLAGS)) -D_FILE_OFFSET_BITS=64
+        $(filter -I%,$(CFLAGS)) -D_FILE_OFFSET_BITS=64 -idirafter include
-include $(srctree)/$(ARCH_DIR)/Makefile-$(SUBARCH)
 #This will adjust *FLAGS accordingly to the platform.
 include $(srctree)/$(ARCH_DIR)/Makefile-os-$(OS)
-KBUILD_CPPFLAGS += -I$(srctree)/arch/$(HEADER_ARCH)/include
+KBUILD_CPPFLAGS += -I$(srctree)/$(HOST_DIR)/include
 # -Derrno=kernel_errno - This turns all kernel references to errno into
 # kernel_errno to separate them from the libc errno.  This allows -fno-common
@@ -84,10 +94,9 @@ define archhelp
  echo '                   find in the kernel root.'
 endef
-KBUILD_KCONFIG := arch/um/Kconfig.$(HEADER_ARCH)
+KBUILD_KCONFIG := $(HOST_DIR)/um/Kconfig
-archprepare: $(SHARED_HEADERS)/user_constants.h
+archprepare: include/generated/user_constants.h
-archprepare: $(SHARED_HEADERS)/kern_constants.h
 LINK-$(CONFIG_LD_SCRIPT_STATIC) += -static
 LINK-$(CONFIG_LD_SCRIPT_DYN) += -Wl,-rpath,/lib
@@ -118,9 +127,7 @@ endef
 # When cleaning we don't include .config, so we don't include
 # TT or skas makefiles and don't clean skas_ptregs.h.
-CLEAN_FILES += linux x.i gmon.out \
+CLEAN_FILES += linux x.i gmon.out
-        $(SHARED_HEADERS)/user_constants.h \
-        $(SHARED_HEADERS)/kern_constants.h
 archclean:
        @find . \( -name '*.bb' -o -name '*.bbg' -o -name '*.da' \
@@ -128,8 +135,8 @@ archclean:
 # Generated files
-$(ARCH_DIR)/sys-$(SUBARCH)/user-offsets.s: FORCE
+$(HOST_DIR)/um/user-offsets.s: FORCE
-        $(Q)$(MAKE) $(build)=$(ARCH_DIR)/sys-$(SUBARCH) $@
+        $(Q)$(MAKE) $(build)=$(HOST_DIR)/um $@
 define filechk_gen-asm-offsets
        (set -e; \
@@ -144,11 +151,7 @@ define filechk_gen-asm-offsets
         echo ""; )
 endef
-$(SHARED_HEADERS)/user_constants.h: $(ARCH_DIR)/sys-$(SUBARCH)/user-offsets.s
+include/generated/user_constants.h: $(HOST_DIR)/um/user-offsets.s
        $(call filechk,gen-asm-offsets)
-$(SHARED_HEADERS)/kern_constants.h:
+export SUBARCH USER_CFLAGS CFLAGS_NO_HARDENING OS DEV_NULL_PATH
-        $(Q)mkdir -p $(dir $@)
-        $(Q)echo '#include "../../../../include/generated/asm-offsets.h"' >$@
-export SUBARCH USER_CFLAGS CFLAGS_NO_HARDENING OS HEADER_ARCH DEV_NULL_PATH
diff --git a/arch/um/Makefile-x86_64 b/arch/um/Makefile-x86_64
deleted file mode 100644
index a9cd7e77a7ab..000000000000
--- a/arch/um/Makefile-x86_64
+++ /dev/null
@@ -1,26 +0,0 @@
-# Copyright 2003 - 2004 Pathscale, Inc
-# Released under the GPL
-core-y += arch/um/sys-x86_64/ arch/x86/crypto/
-START := 0x60000000
-_extra_flags_ = -fno-builtin -m64
-KBUILD_CFLAGS += $(_extra_flags_)
-CHECKFLAGS  += -m64 -D__x86_64__
-KBUILD_AFLAGS += -m64
-LDFLAGS += -m elf_x86_64
-KBUILD_CPPFLAGS += -m64
-ELF_ARCH := i386:x86-64
-ELF_FORMAT := elf64-x86-64
-HEADER_ARCH := x86
-# Not on all 64-bit distros /lib is a symlink to /lib64. PLD is an example.
-LINK-$(CONFIG_LD_SCRIPT_DYN) += -Wl,-rpath,/lib64
-LINK-y += -m64
-# Do unit-at-a-time unconditionally on x86_64, following the host
-KBUILD_CFLAGS += $(call cc-option,-funit-at-a-time)
diff --git a/arch/um/include/shared/chan_kern.h b/arch/um/drivers/chan.h
index 1e651457e049..8df0fd9024dc 100644
--- a/arch/um/include/shared/chan_kern.h
+++ b/arch/um/drivers/chan.h
@@ -6,9 +6,9 @@
 #ifndef __CHAN_KERN_H__
 #define __CHAN_KERN_H__
-#include "linux/tty.h"
+#include <linux/tty.h>
-#include "linux/list.h"
+#include <linux/list.h>
-#include "linux/console.h"
+#include <linux/console.h>
 #include "chan_user.h"
 #include "line.h"
diff --git a/arch/um/drivers/chan_kern.c b/arch/um/drivers/chan_kern.c
index d4191fe1cede..420e2c800799 100644
--- a/arch/um/drivers/chan_kern.c
+++ b/arch/um/drivers/chan_kern.c
@@ -6,7 +6,7 @@
 #include <linux/slab.h>
 #include <linux/tty.h>
 #include <linux/tty_flip.h>
-#include "chan_kern.h"
+#include "chan.h"
 #include "os.h"
 #ifdef CONFIG_NOCONFIG_CHAN
@@ -358,11 +358,11 @@ int chan_window_size(struct list_head *chans, unsigned short *rows_out,
        return 0;
 }
-static void free_one_chan(struct chan *chan, int delay_free_irq)
+static void free_one_chan(struct chan *chan)
 {
        list_del(&chan->list);
-        close_one_chan(chan, delay_free_irq);
+        close_one_chan(chan, 0);
        if (chan->ops->free != NULL)
                (*chan->ops->free)(chan->data);
@@ -372,14 +372,14 @@ static void free_one_chan(struct chan *chan, int delay_free_irq)
        kfree(chan);
 }
-static void free_chan(struct list_head *chans, int delay_free_irq)
+static void free_chan(struct list_head *chans)
 {
        struct list_head *ele, *next;
        struct chan *chan;
        list_for_each_safe(ele, next, chans) {
                chan = list_entry(ele, struct chan, list);
-                free_one_chan(chan, delay_free_irq);
+                free_one_chan(chan);
        }
 }
@@ -547,7 +547,7 @@ int parse_chan_pair(char *str, struct line *line, int device,
        char *in, *out;
        if (!list_empty(chans)) {
-                free_chan(chans, 0);
+                free_chan(chans);
                INIT_LIST_HEAD(chans);
        }
diff --git a/arch/um/drivers/chan_user.c b/arch/um/drivers/chan_user.c
index cfeb3f4a44af..f180813ce2c7 100644
--- a/arch/um/drivers/chan_user.c
+++ b/arch/um/drivers/chan_user.c
@@ -11,10 +11,8 @@
 #include <termios.h>
 #include <sys/ioctl.h>
 #include "chan_user.h"
-#include "kern_constants.h"
 #include "os.h"
 #include "um_malloc.h"
-#include "user.h"
 void generic_close(int fd, void *unused)
 {
@@ -283,7 +281,12 @@ void register_winch(int fd, struct tty_struct *tty)
                return;
        pid = tcgetpgrp(fd);
-        if (!is_skas_winch(pid, fd, tty) && (pid == -1)) {
+        if (is_skas_winch(pid, fd, tty)) {
+                register_winch_irq(-1, fd, -1, tty, 0);
+                return;
+        }
+        if (pid == -1) {
                thread = winch_tramp(fd, tty, &thread_fd, &stack);
                if (thread < 0)
                        return;
diff --git a/arch/um/include/shared/chan_user.h b/arch/um/drivers/chan_user.h
index 9b9ced85b703..9b9ced85b703 100644
--- a/arch/um/include/shared/chan_user.h
+++ b/arch/um/drivers/chan_user.h
diff --git a/arch/um/drivers/cow_sys.h b/arch/um/drivers/cow_sys.h
index f5701fd2ef90..7f2ed0b8824a 100644
--- a/arch/um/drivers/cow_sys.h
+++ b/arch/um/drivers/cow_sys.h
@@ -3,7 +3,6 @@
 #include "kern_util.h"
 #include "os.h"
-#include "user.h"
 #include "um_malloc.h"
 static inline void *cow_malloc(int size)
diff --git a/arch/um/drivers/daemon_user.c b/arch/um/drivers/daemon_user.c
index f8e85e0bdace..a4fd7bc14af7 100644
--- a/arch/um/drivers/daemon_user.c
+++ b/arch/um/drivers/daemon_user.c
@@ -17,7 +17,6 @@
 #include "net_user.h"
 #include "os.h"
 #include "um_malloc.h"
-#include "user.h"
 enum request_type { REQ_NEW_CONTROL };
diff --git a/arch/um/drivers/fd.c b/arch/um/drivers/fd.c
index f5a981a16240..5b81d2574415 100644
--- a/arch/um/drivers/fd.c
+++ b/arch/um/drivers/fd.c
@@ -9,10 +9,8 @@
 #include <errno.h>
 #include <termios.h>
 #include "chan_user.h"
-#include "kern_constants.h"
 #include "os.h"
 #include "um_malloc.h"
-#include "user.h"
 struct fd_chan {
        int fd;
diff --git a/arch/um/drivers/harddog_user.c b/arch/um/drivers/harddog_user.c
index 84dce3fc590c..0345d6206d40 100644
--- a/arch/um/drivers/harddog_user.c
+++ b/arch/um/drivers/harddog_user.c
@@ -7,7 +7,6 @@
 #include <unistd.h>
 #include <errno.h>
 #include "os.h"
-#include "user.h"
 struct dog_data {
        int stdin;
diff --git a/arch/um/drivers/line.c b/arch/um/drivers/line.c
index 364c8a15c4c3..c1cf2206b84b 100644
--- a/arch/um/drivers/line.c
+++ b/arch/um/drivers/line.c
@@ -7,7 +7,7 @@
 #include "linux/kd.h"
 #include "linux/sched.h"
 #include "linux/slab.h"
-#include "chan_kern.h"
+#include "chan.h"
 #include "irq_kern.h"
 #include "irq_user.h"
 #include "kern_util.h"
diff --git a/arch/um/include/shared/line.h b/arch/um/drivers/line.h
index 63df3ca02ac2..63df3ca02ac2 100644
--- a/arch/um/include/shared/line.h
+++ b/arch/um/drivers/line.h
diff --git a/arch/um/include/shared/mconsole.h b/arch/um/drivers/mconsole.h
index c139ae1d6826..c139ae1d6826 100644
--- a/arch/um/include/shared/mconsole.h
+++ b/arch/um/drivers/mconsole.h
diff --git a/arch/um/include/shared/mconsole_kern.h b/arch/um/drivers/mconsole_kern.h
index d2fe07e78958..d2fe07e78958 100644
--- a/arch/um/include/shared/mconsole_kern.h
+++ b/arch/um/drivers/mconsole_kern.h
diff --git a/arch/um/drivers/mconsole_user.c b/arch/um/drivers/mconsole_user.c
index f8cf4c8bedef..99209826adb1 100644
--- a/arch/um/drivers/mconsole_user.c
+++ b/arch/um/drivers/mconsole_user.c
@@ -10,9 +10,7 @@
 #include <sys/socket.h>
 #include <sys/uio.h>
 #include <sys/un.h>
-#include "kern_constants.h"
 #include "mconsole.h"
-#include "user.h"
 static struct mconsole_command commands[] = {
        /*
diff --git a/arch/um/drivers/net_user.c b/arch/um/drivers/net_user.c
index 520118888f16..05090c37fa84 100644
--- a/arch/um/drivers/net_user.c
+++ b/arch/um/drivers/net_user.c
@@ -12,10 +12,8 @@
 #include <sys/socket.h>
 #include <sys/wait.h>
 #include "net_user.h"
-#include "kern_constants.h"
 #include "os.h"
 #include "um_malloc.h"
-#include "user.h"
 int tap_open_common(void *dev, char *gate_addr)
 {
diff --git a/arch/um/drivers/pcap_user.c b/arch/um/drivers/pcap_user.c
index 5f903587d69e..702a75b190ee 100644
--- a/arch/um/drivers/pcap_user.c
+++ b/arch/um/drivers/pcap_user.c
@@ -9,9 +9,7 @@
 #include <asm/types.h>
 #include "net_user.h"
 #include "pcap_user.h"
-#include "kern_constants.h"
 #include "um_malloc.h"
-#include "user.h"
 #define PCAP_FD(p) (*(int *)(p))
diff --git a/arch/um/drivers/port_user.c b/arch/um/drivers/port_user.c
index b49bf56a56aa..7b010b76ddf0 100644
--- a/arch/um/drivers/port_user.c
+++ b/arch/um/drivers/port_user.c
@@ -10,11 +10,9 @@
 #include <unistd.h>
 #include <netinet/in.h>
 #include "chan_user.h"
-#include "kern_constants.h"
 #include "os.h"
 #include "port.h"
 #include "um_malloc.h"
-#include "user.h"
 struct port_chan {
        int raw;
diff --git a/arch/um/drivers/pty.c b/arch/um/drivers/pty.c
index 1113911dcb2b..cff2b75d31fd 100644
--- a/arch/um/drivers/pty.c
+++ b/arch/um/drivers/pty.c
@@ -12,10 +12,8 @@
 #include <termios.h>
 #include <sys/stat.h>
 #include "chan_user.h"
-#include "kern_constants.h"
 #include "os.h"
 #include "um_malloc.h"
-#include "user.h"
 struct pty_chan {
        void (*announce)(char *dev_name, int dev);
diff --git a/arch/um/drivers/slip_user.c b/arch/um/drivers/slip_user.c
index cbacfc4e63e6..932b4d69bec2 100644
--- a/arch/um/drivers/slip_user.c
+++ b/arch/um/drivers/slip_user.c
@@ -11,12 +11,10 @@
 #include <string.h>
 #include <sys/termios.h>
 #include <sys/wait.h>
-#include "kern_constants.h"
 #include "net_user.h"
 #include "os.h"
 #include "slip.h"
 #include "um_malloc.h"
-#include "user.h"
 static int slip_user_init(void *data, void *dev)
 {
diff --git a/arch/um/drivers/slirp_user.c b/arch/um/drivers/slirp_user.c
index a0ada8fec72a..db4adb639ff8 100644
--- a/arch/um/drivers/slirp_user.c
+++ b/arch/um/drivers/slirp_user.c
@@ -7,11 +7,9 @@
 #include <errno.h>
 #include <string.h>
 #include <sys/wait.h>
-#include "kern_constants.h"
 #include "net_user.h"
 #include "os.h"
 #include "slirp.h"
-#include "user.h"
 static int slirp_user_init(void *data, void *dev)
 {
diff --git a/arch/um/drivers/ssl.c b/arch/um/drivers/ssl.c
index f1786e64607f..9d8c20af6f80 100644
--- a/arch/um/drivers/ssl.c
+++ b/arch/um/drivers/ssl.c
@@ -12,10 +12,8 @@
 #include "linux/console.h"
 #include "asm/termbits.h"
 #include "asm/irq.h"
-#include "line.h"
 #include "ssl.h"
-#include "chan_kern.h"
+#include "chan.h"
-#include "kern.h"
 #include "init.h"
 #include "irq_user.h"
 #include "mconsole_kern.h"
diff --git a/arch/um/drivers/stdio_console.c b/arch/um/drivers/stdio_console.c
index 49266f6108c4..088776f01908 100644
--- a/arch/um/drivers/stdio_console.c
+++ b/arch/um/drivers/stdio_console.c
@@ -20,8 +20,7 @@
 #include "asm/current.h"
 #include "asm/irq.h"
 #include "stdio_console.h"
-#include "line.h"
+#include "chan.h"
-#include "chan_kern.h"
 #include "irq_user.h"
 #include "mconsole_kern.h"
 #include "init.h"
diff --git a/arch/um/drivers/tty.c b/arch/um/drivers/tty.c
index 495858a090e4..a97391f9ec54 100644
--- a/arch/um/drivers/tty.c
+++ b/arch/um/drivers/tty.c
@@ -7,10 +7,8 @@
 #include <fcntl.h>
 #include <termios.h>
 #include "chan_user.h"
-#include "kern_constants.h"
 #include "os.h"
 #include "um_malloc.h"
-#include "user.h"
 struct tty_chan {
        char *dev;
diff --git a/arch/um/drivers/ubd_kern.c b/arch/um/drivers/ubd_kern.c
index 620f5b70957d..944453a3ec99 100644
--- a/arch/um/drivers/ubd_kern.c
+++ b/arch/um/drivers/ubd_kern.c
@@ -46,7 +46,6 @@
 #include "asm/tlbflush.h"
 #include "mem_user.h"
 #include "kern_util.h"
-#include "kern.h"
 #include "mconsole_kern.h"
 #include "init.h"
 #include "irq_user.h"
@@ -54,7 +53,6 @@
 #include "ubd_user.h"
 #include "os.h"
 #include "mem.h"
-#include "mem_kern.h"
 #include "cow.h"
 enum ubd_req { UBD_READ, UBD_WRITE };
@@ -513,8 +511,37 @@ __uml_exitcall(kill_io_thread);
 static inline int ubd_file_size(struct ubd *ubd_dev, __u64 *size_out)
 {
        char *file;
+        int fd;
+        int err;
+        __u32 version;
+        __u32 align;
+        char *backing_file;
+        time_t mtime;
+        unsigned long long size;
+        int sector_size;
+        int bitmap_offset;
+        if (ubd_dev->file && ubd_dev->cow.file) {
+                file = ubd_dev->cow.file;
+                goto out;
+        }
-        file = ubd_dev->cow.file ? ubd_dev->cow.file : ubd_dev->file;
+        fd = os_open_file(ubd_dev->file, global_openflags, 0);
+        if (fd < 0)
+                return fd;
+        err = read_cow_header(file_reader, &fd, &version, &backing_file, \
+                &mtime, &size, &sector_size, &align, &bitmap_offset);
+        os_close_file(fd);
+        if(err == -EINVAL)
+                file = ubd_dev->file;
+        else
+                file = backing_file;
+out:
        return os_file_size(file, size_out);
 }
diff --git a/arch/um/drivers/ubd_user.c b/arch/um/drivers/ubd_user.c
index b591bb9c41dd..007b94d97726 100644
--- a/arch/um/drivers/ubd_user.c
+++ b/arch/um/drivers/ubd_user.c
@@ -16,7 +16,6 @@
 #include <sys/mman.h>
 #include <sys/param.h>
 #include "asm/types.h"
-#include "user.h"
 #include "ubd_user.h"
 #include "os.h"
 #include "cow.h"
diff --git a/arch/um/include/shared/ubd_user.h b/arch/um/drivers/ubd_user.h
index 3845051f1b10..3845051f1b10 100644
--- a/arch/um/include/shared/ubd_user.h
+++ b/arch/um/drivers/ubd_user.h
diff --git a/arch/um/drivers/umcast_user.c b/arch/um/drivers/umcast_user.c
index 59c56fd6f52a..010fa2d849ec 100644
--- a/arch/um/drivers/umcast_user.c
+++ b/arch/um/drivers/umcast_user.c
@@ -15,11 +15,9 @@
 #include <unistd.h>
 #include <errno.h>
 #include <netinet/in.h>
-#include "kern_constants.h"
 #include "umcast.h"
 #include "net_user.h"
 #include "um_malloc.h"
-#include "user.h"
 static struct sockaddr_in *new_addr(char *addr, unsigned short port)
 {
diff --git a/arch/um/drivers/vde_user.c b/arch/um/drivers/vde_user.c
index c5c43253e6ce..b8c286748d3d 100644
--- a/arch/um/drivers/vde_user.c
+++ b/arch/um/drivers/vde_user.c
@@ -6,10 +6,8 @@
 #include <stddef.h>
 #include <errno.h>
 #include <libvdeplug.h>
-#include "kern_constants.h"
 #include "net_user.h"
 #include "um_malloc.h"
-#include "user.h"
 #include "vde.h"
 static int vde_user_init(void *data, void *dev)
diff --git a/arch/um/drivers/xterm.c b/arch/um/drivers/xterm.c
index 2e1de5728604..969110e56487 100644
--- a/arch/um/drivers/xterm.c
+++ b/arch/um/drivers/xterm.c
@@ -11,10 +11,8 @@
 #include <string.h>
 #include <termios.h>
 #include "chan_user.h"
-#include "kern_constants.h"
 #include "os.h"
 #include "um_malloc.h"
-#include "user.h"
 #include "xterm.h"
 struct xterm_chan {
diff --git a/arch/um/include/asm/Kbuild b/arch/um/include/asm/Kbuild
new file mode 100644
index 000000000000..451f4517b334
--- /dev/null
+++ b/arch/um/include/asm/Kbuild
@@ -0,0 +1,3 @@
+generic-y += bug.h cputime.h device.h emergency-restart.h futex.h hardirq.h
+generic-y += hw_irq.h irq_regs.h kdebug.h percpu.h sections.h topology.h xor.h
+generic-y += ftrace.h
diff --git a/arch/um/include/asm/bug.h b/arch/um/include/asm/bug.h
deleted file mode 100644
index 9e33b864c359..000000000000
--- a/arch/um/include/asm/bug.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_BUG_H
-#define __UM_BUG_H
-#include <asm-generic/bug.h>
-#endif
diff --git a/arch/um/include/asm/checksum.h b/arch/um/include/asm/checksum.h
deleted file mode 100644
index 5b501361e361..000000000000
--- a/arch/um/include/asm/checksum.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_CHECKSUM_H
-#define __UM_CHECKSUM_H
-#include "sysdep/checksum.h"
-#endif
diff --git a/arch/um/include/asm/cputime.h b/arch/um/include/asm/cputime.h
deleted file mode 100644
index c84acbadfa2f..000000000000
--- a/arch/um/include/asm/cputime.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_CPUTIME_H
-#define __UM_CPUTIME_H
-#include <asm-generic/cputime.h>
-#endif /* __UM_CPUTIME_H */
diff --git a/arch/um/include/asm/device.h b/arch/um/include/asm/device.h
deleted file mode 100644
index d8f9872b0e2d..000000000000
--- a/arch/um/include/asm/device.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * Arch specific extensions to struct device
- *
- * This file is released under the GPLv2
- */
-#include <asm-generic/device.h>
diff --git a/arch/um/include/asm/emergency-restart.h b/arch/um/include/asm/emergency-restart.h
deleted file mode 100644
index 108d8c48e42e..000000000000
--- a/arch/um/include/asm/emergency-restart.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_EMERGENCY_RESTART_H
-#define _ASM_EMERGENCY_RESTART_H
-#include <asm-generic/emergency-restart.h>
-#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/arch/um/include/asm/futex.h b/arch/um/include/asm/futex.h
deleted file mode 100644
index 6a332a9f099c..000000000000
--- a/arch/um/include/asm/futex.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_FUTEX_H
-#define _ASM_FUTEX_H
-#include <asm-generic/futex.h>
-#endif
diff --git a/arch/um/include/asm/hardirq.h b/arch/um/include/asm/hardirq.h
deleted file mode 100644
index fb3c05a0cbbf..000000000000
--- a/arch/um/include/asm/hardirq.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/hardirq.h>
diff --git a/arch/um/include/asm/hw_irq.h b/arch/um/include/asm/hw_irq.h
deleted file mode 100644
index 1cf84cf5f21a..000000000000
--- a/arch/um/include/asm/hw_irq.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef _ASM_UM_HW_IRQ_H
-#define _ASM_UM_HW_IRQ_H
-#include "asm/irq.h"
-#include "asm/archparam.h"
-#endif
diff --git a/arch/um/include/asm/irq_regs.h b/arch/um/include/asm/irq_regs.h
deleted file mode 100644
index 3dd9c0b70270..000000000000
--- a/arch/um/include/asm/irq_regs.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/irq_regs.h>
diff --git a/arch/um/include/asm/irqflags.h b/arch/um/include/asm/irqflags.h
index 659b9abdfdba..c780d8a16773 100644
--- a/arch/um/include/asm/irqflags.h
+++ b/arch/um/include/asm/irqflags.h
@@ -1,6 +1,42 @@
 #ifndef __UM_IRQFLAGS_H
 #define __UM_IRQFLAGS_H
-/* Empty for now */
+extern int get_signals(void);
+extern int set_signals(int enable);
+extern void block_signals(void);
+extern void unblock_signals(void);
+static inline unsigned long arch_local_save_flags(void)
+{
+        return get_signals();
+}
+static inline void arch_local_irq_restore(unsigned long flags)
+{
+        set_signals(flags);
+}
+static inline void arch_local_irq_enable(void)
+{
+        unblock_signals();
+}
+static inline void arch_local_irq_disable(void)
+{
+        block_signals();
+}
+static inline unsigned long arch_local_irq_save(void)
+{
+        unsigned long flags;
+        flags = arch_local_save_flags();
+        arch_local_irq_disable();
+        return flags;
+}
+static inline bool arch_irqs_disabled(void)
+{
+        return arch_local_save_flags() == 0;
+}
 #endif
diff --git a/arch/um/include/asm/kdebug.h b/arch/um/include/asm/kdebug.h
deleted file mode 100644
index 6ece1b037665..000000000000
--- a/arch/um/include/asm/kdebug.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/kdebug.h>
diff --git a/arch/um/include/asm/mmu.h b/arch/um/include/asm/mmu.h
index cf259de51531..30509b9f37fd 100644
--- a/arch/um/include/asm/mmu.h
+++ b/arch/um/include/asm/mmu.h
@@ -1,12 +1,24 @@
 /* 
- * Copyright (C) 2002 Jeff Dike (jdike@karaya.com)
+ * Copyright (C) 2002 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
 * Licensed under the GPL
 */
-#ifndef __MMU_H
+#ifndef __ARCH_UM_MMU_H
-#define __MMU_H
+#define __ARCH_UM_MMU_H
-#include "um_mmu.h"
+#include "mm_id.h"
+#include <asm/mm_context.h>
-#endif
+typedef struct mm_context {
+        struct mm_id id;
+        struct uml_arch_mm_context arch;
+        struct page **stub_pages;
+} mm_context_t;
+extern void __switch_mm(struct mm_id * mm_idp);
+/* Avoid tangled inclusion with asm/ldt.h */
+extern long init_new_ldt(struct mm_context *to_mm, struct mm_context *from_mm);
+extern void free_ldt(struct mm_context *mm);
+#endif
diff --git a/arch/um/include/asm/mmu_context.h b/arch/um/include/asm/mmu_context.h
index 34d813011b7a..591b3d8d7614 100644
--- a/arch/um/include/asm/mmu_context.h
+++ b/arch/um/include/asm/mmu_context.h
@@ -6,15 +6,12 @@
 #ifndef __UM_MMU_CONTEXT_H
 #define __UM_MMU_CONTEXT_H
-#include "linux/sched.h"
+#include <linux/sched.h>
-#include "um_mmu.h"
+#include <asm/mmu.h>
 extern void arch_dup_mmap(struct mm_struct *oldmm, struct mm_struct *mm);
 extern void arch_exit_mmap(struct mm_struct *mm);
-#define get_mmu_context(task) do ; while(0)
-#define activate_context(tsk) do ; while(0)
 #define deactivate_mm(tsk,mm)   do { } while (0)
 extern void force_flush_all(void);
diff --git a/arch/um/include/asm/page.h b/arch/um/include/asm/page.h
index 4cc9b6cf480a..7cfc3cedce84 100644
--- a/arch/um/include/asm/page.h
+++ b/arch/um/include/asm/page.h
@@ -19,7 +19,7 @@
 struct page;
 #include <linux/types.h>
-#include <sysdep/vm-flags.h>
+#include <asm/vm-flags.h>
 /*
 * These are used to make use of C type-checking..
diff --git a/arch/um/include/asm/page_offset.h b/arch/um/include/asm/page_offset.h
deleted file mode 100644
index 1c168dfbf359..000000000000
--- a/arch/um/include/asm/page_offset.h
+++ /dev/null
@@ -1 +0,0 @@
-#define PAGE_OFFSET_RAW (uml_physmem)
diff --git a/arch/um/include/asm/pda.h b/arch/um/include/asm/pda.h
deleted file mode 100644
index ddcd774fc2a0..000000000000
--- a/arch/um/include/asm/pda.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Copyright 2003 PathScale, Inc.
- *
- * Licensed under the GPL
- */
-#ifndef __UM_PDA_X86_64_H
-#define __UM_PDA_X86_64_H
-/* XXX */
-struct foo {
-        unsigned int __softirq_pending;
-        unsigned int __nmi_count;
-};
-extern struct foo me;
-#define read_pda(me) (&me)
-#endif
diff --git a/arch/um/include/asm/percpu.h b/arch/um/include/asm/percpu.h
deleted file mode 100644
index efe7508d8abd..000000000000
--- a/arch/um/include/asm/percpu.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_PERCPU_H
-#define __UM_PERCPU_H
-#include <asm-generic/percpu.h>
-#endif /* __UM_PERCPU_H */
diff --git a/arch/um/include/asm/ptrace-generic.h b/arch/um/include/asm/ptrace-generic.h
index 1a7d2757fe05..f605d3c4844c 100644
--- a/arch/um/include/asm/ptrace-generic.h
+++ b/arch/um/include/asm/ptrace-generic.h
@@ -23,17 +23,10 @@ struct pt_regs {
 #define PT_REGS_IP(r) UPT_IP(&(r)->regs)
 #define PT_REGS_SP(r) UPT_SP(&(r)->regs)
-#define PT_REG(r, reg) UPT_REG(&(r)->regs, reg)
-#define PT_REGS_SET(r, reg, val) UPT_SET(&(r)->regs, reg, val)
-#define PT_REGS_SET_SYSCALL_RETURN(r, res) \
-        UPT_SET_SYSCALL_RETURN(&(r)->regs, res)
 #define PT_REGS_RESTART_SYSCALL(r) UPT_RESTART_SYSCALL(&(r)->regs)
 #define PT_REGS_SYSCALL_NR(r) UPT_SYSCALL_NR(&(r)->regs)
-#define PT_REGS_SC(r) UPT_SC(&(r)->regs)
 #define instruction_pointer(regs) PT_REGS_IP(regs)
 struct task_struct;
diff --git a/arch/um/include/asm/sections.h b/arch/um/include/asm/sections.h
deleted file mode 100644
index 6b0231eefea8..000000000000
--- a/arch/um/include/asm/sections.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef _UM_SECTIONS_H
-#define _UM_SECTIONS_H
-/* nothing to see, move along */
-#include <asm-generic/sections.h>
-#endif
diff --git a/arch/um/include/asm/system.h b/arch/um/include/asm/system.h
deleted file mode 100644
index 68a90ecd1450..000000000000
--- a/arch/um/include/asm/system.h
+++ /dev/null
@@ -1,47 +0,0 @@
-#ifndef __UM_SYSTEM_GENERIC_H
-#define __UM_SYSTEM_GENERIC_H
-#include "sysdep/system.h"
-extern int get_signals(void);
-extern int set_signals(int enable);
-extern void block_signals(void);
-extern void unblock_signals(void);
-static inline unsigned long arch_local_save_flags(void)
-{
-        return get_signals();
-}
-static inline void arch_local_irq_restore(unsigned long flags)
-{
-        set_signals(flags);
-}
-static inline void arch_local_irq_enable(void)
-{
-        unblock_signals();
-}
-static inline void arch_local_irq_disable(void)
-{
-        block_signals();
-}
-static inline unsigned long arch_local_irq_save(void)
-{
-        unsigned long flags;
-        flags = arch_local_save_flags();
-        arch_local_irq_disable();
-        return flags;
-}
-static inline bool arch_irqs_disabled(void)
-{
-        return arch_local_save_flags() == 0;
-}
-extern void *_switch_to(void *prev, void *next, void *last);
-#define switch_to(prev, next, last) prev = _switch_to(prev, next, last)
-#endif
diff --git a/arch/um/include/asm/topology.h b/arch/um/include/asm/topology.h
deleted file mode 100644
index 0905e4f21d42..000000000000
--- a/arch/um/include/asm/topology.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_UM_TOPOLOGY_H
-#define _ASM_UM_TOPOLOGY_H
-#include <asm-generic/topology.h>
-#endif
diff --git a/arch/um/include/asm/uaccess.h b/arch/um/include/asm/uaccess.h
index b9a895d6fa1d..3f22fbf7ca1d 100644
--- a/arch/um/include/asm/uaccess.h
+++ b/arch/um/include/asm/uaccess.h
@@ -6,15 +6,15 @@
 #ifndef __UM_UACCESS_H
 #define __UM_UACCESS_H
-#include <asm/errno.h>
-#include <asm/processor.h>
 /* thread_info has a mm_segment_t in it, so put the definition up here */
 typedef struct {
        unsigned long seg;
 } mm_segment_t;
-#include "linux/thread_info.h"
+#include <linux/thread_info.h>
+#include <linux/errno.h>
+#include <asm/processor.h>
+#include <asm/elf.h>
 #define VERIFY_READ 0
 #define VERIFY_WRITE 1
@@ -38,7 +38,86 @@ typedef struct {
 #define segment_eq(a, b) ((a).seg == (b).seg)
-#include "um_uaccess.h"
+#define __under_task_size(addr, size) \
+        (((unsigned long) (addr) < TASK_SIZE) && \
+         (((unsigned long) (addr) + (size)) < TASK_SIZE))
+#define __access_ok_vsyscall(type, addr, size) \
+         ((type == VERIFY_READ) && \
+          ((unsigned long) (addr) >= FIXADDR_USER_START) && \
+          ((unsigned long) (addr) + (size) <= FIXADDR_USER_END) && \
+          ((unsigned long) (addr) + (size) >= (unsigned long)(addr)))
+#define __addr_range_nowrap(addr, size) \
+        ((unsigned long) (addr) <= ((unsigned long) (addr) + (size)))
+#define access_ok(type, addr, size) \
+        (__addr_range_nowrap(addr, size) && \
+         (__under_task_size(addr, size) || \
+          __access_ok_vsyscall(type, addr, size) || \
+          segment_eq(get_fs(), KERNEL_DS)))
+extern int copy_from_user(void *to, const void __user *from, int n);
+extern int copy_to_user(void __user *to, const void *from, int n);
+/*
+ * strncpy_from_user: - Copy a NUL terminated string from userspace.
+ * @dst:   Destination address, in kernel space.  This buffer must be at
+ *         least @count bytes long.
+ * @src:   Source address, in user space.
+ * @count: Maximum number of bytes to copy, including the trailing NUL.
+ *
+ * Copies a NUL-terminated string from userspace to kernel space.
+ *
+ * On success, returns the length of the string (not including the trailing
+ * NUL).
+ *
+ * If access to userspace fails, returns -EFAULT (some data may have been
+ * copied).
+ *
+ * If @count is smaller than the length of the string, copies @count bytes
+ * and returns @count.
+ */
+extern int strncpy_from_user(char *dst, const char __user *src, int count);
+/*
+ * __clear_user: - Zero a block of memory in user space, with less checking.
+ * @to:   Destination address, in user space.
+ * @n:    Number of bytes to zero.
+ *
+ * Zero a block of memory in user space.  Caller must check
+ * the specified block with access_ok() before calling this function.
+ *
+ * Returns number of bytes that could not be cleared.
+ * On success, this will be zero.
+ */
+extern int __clear_user(void __user *mem, int len);
+/*
+ * clear_user: - Zero a block of memory in user space.
+ * @to:   Destination address, in user space.
+ * @n:    Number of bytes to zero.
+ *
+ * Zero a block of memory in user space.
+ *
+ * Returns number of bytes that could not be cleared.
+ * On success, this will be zero.
+ */
+extern int clear_user(void __user *mem, int len);
+/*
+ * strlen_user: - Get the size of a string in user space.
+ * @str: The string to measure.
+ * @n:   The maximum valid length
+ *
+ * Get the size of a NUL-terminated string in user space.
+ *
+ * Returns the size of the string INCLUDING the terminating NUL.
+ * On exception, returns 0.
+ * If the string is too long, returns a value greater than @n.
+ */
+extern int strnlen_user(const void __user *str, int len);
 #define __copy_from_user(to, from, n) copy_from_user(to, from, n)
diff --git a/arch/um/include/asm/xor.h b/arch/um/include/asm/xor.h
deleted file mode 100644
index a19db3e17241..000000000000
--- a/arch/um/include/asm/xor.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_XOR_H
-#define __UM_XOR_H
-#include "asm-generic/xor.h"
-#endif
diff --git a/arch/um/include/shared/as-layout.h b/arch/um/include/shared/as-layout.h
index a92b678503cf..896e16602176 100644
--- a/arch/um/include/shared/as-layout.h
+++ b/arch/um/include/shared/as-layout.h
@@ -6,7 +6,7 @@
 #ifndef __START_H__
 #define __START_H__
-#include "kern_constants.h"
+#include <generated/asm-offsets.h>
 /*
 * Stolen from linux/const.h, which can't be directly included since
diff --git a/arch/um/include/shared/common-offsets.h b/arch/um/include/shared/common-offsets.h
index 72009c7e3210..d7fe563aa7e7 100644
--- a/arch/um/include/shared/common-offsets.h
+++ b/arch/um/include/shared/common-offsets.h
@@ -2,7 +2,6 @@
 DEFINE(KERNEL_MADV_REMOVE, MADV_REMOVE);
-OFFSET(HOST_TASK_REGS, task_struct, thread.regs);
 OFFSET(HOST_TASK_PID, task_struct, pid);
 DEFINE(UM_KERN_PAGE_SIZE, PAGE_SIZE);
diff --git a/arch/um/include/shared/initrd.h b/arch/um/include/shared/initrd.h
deleted file mode 100644
index 22673bcc273d..000000000000
--- a/arch/um/include/shared/initrd.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Copyright (C) 2000 Jeff Dike (jdike@karaya.com)
- * Licensed under the GPL
- */
-#ifndef __INITRD_USER_H__
-#define __INITRD_USER_H__
-extern int load_initrd(char *filename, void *buf, int size);
-#endif
diff --git a/arch/um/include/shared/kern.h b/arch/um/include/shared/kern.h
index 4ce3fc650e57..6cd01240bbf0 100644
--- a/arch/um/include/shared/kern.h
+++ b/arch/um/include/shared/kern.h
@@ -13,28 +13,10 @@
 * includes.
 */
-extern int errno;
-extern int clone(int (*proc)(void *), void *sp, int flags, void *data);
-extern int sleep(int);
 extern int printf(const char *fmt, ...);
-extern char *strerror(int errnum);
-extern char *ptsname(int __fd);
-extern int munmap(void *, int);
 extern void *sbrk(int increment);
-extern void *malloc(int size);
-extern void perror(char *err);
-extern int kill(int pid, int sig);
-extern int getuid(void);
-extern int getgid(void);
 extern int pause(void);
-extern int write(int, const void *, int);
 extern void exit(int);
-extern int close(int);
-extern int read(unsigned int, char *, int);
-extern int pipe(int *);
-extern int sched_yield(void);
-extern int ptrace(int op, int pid, long addr, long data);
 #endif
diff --git a/arch/um/include/shared/kern_util.h b/arch/um/include/shared/kern_util.h
index 3c341222d252..0f1483852460 100644
--- a/arch/um/include/shared/kern_util.h
+++ b/arch/um/include/shared/kern_util.h
@@ -21,7 +21,6 @@ extern unsigned long alloc_stack(int order, int atomic);
 extern void free_stack(unsigned long stack, int order);
 extern int do_signal(void);
-extern void copy_sc(struct uml_pt_regs *regs, void *from);
 extern void interrupt_end(void);
 extern void relay_signal(int sig, struct uml_pt_regs *regs);
diff --git a/arch/um/include/shared/ldt.h b/arch/um/include/shared/ldt.h
deleted file mode 100644
index a7f999a58774..000000000000
--- a/arch/um/include/shared/ldt.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright (C) 2004 Fujitsu Siemens Computers GmbH
- * Licensed under the GPL
- *
- * Author: Bodo Stroesser <bstroesser@fujitsu-siemens.com>
- */
-#ifndef __ASM_LDT_H
-#define __ASM_LDT_H
-#include <linux/mutex.h>
-#include <sysdep/host_ldt.h>
-extern void ldt_host_info(void);
-#define LDT_PAGES_MAX \
-        ((LDT_ENTRIES * LDT_ENTRY_SIZE)/PAGE_SIZE)
-#define LDT_ENTRIES_PER_PAGE \
-        (PAGE_SIZE/LDT_ENTRY_SIZE)
-#define LDT_DIRECT_ENTRIES \
-        ((LDT_PAGES_MAX*sizeof(void *))/LDT_ENTRY_SIZE)
-struct ldt_entry {
-        __u32 a;
-        __u32 b;
-};
-typedef struct uml_ldt {
-        int entry_count;
-        struct mutex lock;
-        union {
-                struct ldt_entry * pages[LDT_PAGES_MAX];
-                struct ldt_entry entries[LDT_DIRECT_ENTRIES];
-        } u;
-} uml_ldt_t;
-#endif
diff --git a/arch/um/include/shared/mem_kern.h b/arch/um/include/shared/mem_kern.h
deleted file mode 100644
index 69be0fd0ce4b..000000000000
--- a/arch/um/include/shared/mem_kern.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Copyright (C) 2003 Jeff Dike (jdike@addtoit.com)
- * Licensed under the GPL
- */
-#ifndef __MEM_KERN_H__
-#define __MEM_KERN_H__
-#include "linux/list.h"
-#include "linux/types.h"
-struct remapper {
-        struct list_head list;
-        int (*proc)(int, unsigned long, int, __u64);
-};
-extern void register_remapper(struct remapper *info);
-#endif
diff --git a/arch/um/include/shared/os.h b/arch/um/include/shared/os.h
index 83c7c2ecd614..89b686c1a3ea 100644
--- a/arch/um/include/shared/os.h
+++ b/arch/um/include/shared/os.h
@@ -10,7 +10,6 @@
 #include "irq_user.h"
 #include "longjmp.h"
 #include "mm_id.h"
-#include "sysdep/tls.h"
 #define CATCH_EINTR(expr) while ((errno = 0, ((expr) < 0)) && (errno == EINTR))
@@ -203,12 +202,6 @@ extern int os_drop_memory(void *addr, int length);
 extern int can_drop_memory(void);
 extern void os_flush_stdout(void);
-/* uaccess.c */
-extern unsigned long __do_user_copy(void *to, const void *from, int n,
-                                    void **fault_addr, jmp_buf **fault_catcher,
-                                    void (*op)(void *to, const void *from,
-                                               int n), int *faulted_out);
 /* execvp.c */
 extern int execvp_noalloc(char *buf, const char *file, char *const argv[]);
 /* helper.c */
@@ -218,10 +211,6 @@ extern int run_helper_thread(int (*proc)(void *), void *arg,
 extern int helper_wait(int pid);
-/* tls.c */
-extern int os_set_thread_area(user_desc_t *info, int pid);
-extern int os_get_thread_area(user_desc_t *info, int pid);
 /* umid.c */
 extern int umid_file_name(char *name, char *buf, int len);
 extern int set_umid(char *name);
@@ -231,7 +220,7 @@ extern char *get_umid(void);
 extern void timer_init(void);
 extern void set_sigstack(void *sig_stack, int size);
 extern void remove_sigstack(void);
-extern void set_handler(int sig, void (*handler)(int), int flags, ...);
+extern void set_handler(int sig);
 extern int change_sig(int signal, int on);
 extern void block_signals(void);
 extern void unblock_signals(void);
diff --git a/arch/um/include/shared/process.h b/arch/um/include/shared/process.h
deleted file mode 100644
index bb873a51262e..000000000000
--- a/arch/um/include/shared/process.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* 
- * Copyright (C) 2000 - 2008 Jeff Dike (jdike@{addtoit,linux.intel}.com)
- * Licensed under the GPL
- */
-#ifndef __PROCESS_H__
-#define __PROCESS_H__
-#include <signal.h>
-/* Copied from linux/compiler-gcc.h since we can't include it directly */
-#define barrier() __asm__ __volatile__("": : :"memory")
-extern void sig_handler(int sig, struct sigcontext *sc);
-extern void alarm_handler(int sig, struct sigcontext *sc);
-#endif
diff --git a/arch/um/include/shared/ptrace_user.h b/arch/um/include/shared/ptrace_user.h
index 7fd8539bc19a..56b2f284b108 100644
--- a/arch/um/include/shared/ptrace_user.h
+++ b/arch/um/include/shared/ptrace_user.h
@@ -6,7 +6,8 @@
 #ifndef __PTRACE_USER_H__
 #define __PTRACE_USER_H__
-#include "sysdep/ptrace_user.h"
+#include <sys/ptrace.h>
+#include <sysdep/ptrace_user.h>
 extern int ptrace_getregs(long pid, unsigned long *regs_out);
 extern int ptrace_setregs(long pid, unsigned long *regs_in);
diff --git a/arch/um/include/shared/skas_ptregs.h b/arch/um/include/shared/skas_ptregs.h
deleted file mode 100644
index 73db19e9c077..000000000000
--- a/arch/um/include/shared/skas_ptregs.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __SKAS_PT_REGS_
-#define __SKAS_PT_REGS_
-#include <user_constants.h>
-#endif
diff --git a/arch/um/include/shared/syscall.h b/arch/um/include/shared/syscall.h
deleted file mode 100644
index dda1df901a08..000000000000
--- a/arch/um/include/shared/syscall.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Copyright (C) 2002 Jeff Dike (jdike@karaya.com)
- * Licensed under the GPL
- */
-#ifndef __SYSCALL_USER_H
-#define __SYSCALL_USER_H
-extern int record_syscall_start(int syscall);
-extern void record_syscall_end(int index, long result);
-#endif
diff --git a/arch/um/include/shared/task.h b/arch/um/include/shared/task.h
deleted file mode 100644
index 3fe726b3cf48..000000000000
--- a/arch/um/include/shared/task.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef __TASK_H
-#define __TASK_H
-#include <kern_constants.h>
-#define TASK_REGS(task) ((struct uml_pt_regs *) &(((char *) (task))[HOST_TASK_REGS]))
-#define TASK_PID(task) *((int *) &(((char *) (task))[HOST_TASK_PID]))
-#endif
diff --git a/arch/um/include/shared/tlb.h b/arch/um/include/shared/tlb.h
deleted file mode 100644
index ecd2265b301b..000000000000
--- a/arch/um/include/shared/tlb.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* 
- * Copyright (C) 2002 Jeff Dike (jdike@karaya.com)
- * Licensed under the GPL
- */
-#ifndef __TLB_H__
-#define __TLB_H__
-#include "um_mmu.h"
-extern void force_flush_all(void);
-extern int flush_tlb_kernel_range_common(unsigned long start,
-                                         unsigned long end);
-#endif
diff --git a/arch/um/include/shared/um_malloc.h b/arch/um/include/shared/um_malloc.h
index c554d706d106..6395fef6b69b 100644
--- a/arch/um/include/shared/um_malloc.h
+++ b/arch/um/include/shared/um_malloc.h
@@ -6,7 +6,7 @@
 #ifndef __UM_MALLOC_H__
 #define __UM_MALLOC_H__
-#include "kern_constants.h"
+#include <generated/asm-offsets.h>
 extern void *uml_kmalloc(int size, int flags);
 extern void kfree(const void *ptr);
diff --git a/arch/um/include/shared/um_mmu.h b/arch/um/include/shared/um_mmu.h
deleted file mode 100644
index b1a7e47d1027..000000000000
--- a/arch/um/include/shared/um_mmu.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* 
- * Copyright (C) 2002 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
- * Licensed under the GPL
- */
-#ifndef __ARCH_UM_MMU_H
-#define __ARCH_UM_MMU_H
-#include "mm_id.h"
-#include "ldt.h"
-typedef struct mm_context {
-        struct mm_id id;
-        struct uml_ldt ldt;
-        struct page **stub_pages;
-} mm_context_t;
-extern void __switch_mm(struct mm_id * mm_idp);
-/* Avoid tangled inclusion with asm/ldt.h */
-extern long init_new_ldt(struct mm_context *to_mm, struct mm_context *from_mm);
-extern void free_ldt(struct mm_context *mm);
-#endif
diff --git a/arch/um/include/shared/um_uaccess.h b/arch/um/include/shared/um_uaccess.h
deleted file mode 100644
index 45c04999d670..000000000000
--- a/arch/um/include/shared/um_uaccess.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/* 
- * Copyright (C) 2002 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
- * Licensed under the GPL
- */
-#ifndef __ARCH_UM_UACCESS_H
-#define __ARCH_UM_UACCESS_H
-#include <asm/elf.h>
-#include <asm/fixmap.h>
-#include "sysdep/archsetjmp.h"
-#define __under_task_size(addr, size) \
-        (((unsigned long) (addr) < TASK_SIZE) && \
-         (((unsigned long) (addr) + (size)) < TASK_SIZE))
-#define __access_ok_vsyscall(type, addr, size) \
-         ((type == VERIFY_READ) && \
-          ((unsigned long) (addr) >= FIXADDR_USER_START) && \
-          ((unsigned long) (addr) + (size) <= FIXADDR_USER_END) && \
-          ((unsigned long) (addr) + (size) >= (unsigned long)(addr)))
-#define __addr_range_nowrap(addr, size) \
-        ((unsigned long) (addr) <= ((unsigned long) (addr) + (size)))
-#define access_ok(type, addr, size) \
-        (__addr_range_nowrap(addr, size) && \
-         (__under_task_size(addr, size) || \
-          __access_ok_vsyscall(type, addr, size) || \
-          segment_eq(get_fs(), KERNEL_DS)))
-extern int copy_from_user(void *to, const void __user *from, int n);
-extern int copy_to_user(void __user *to, const void *from, int n);
-extern int __do_copy_to_user(void *to, const void *from, int n,
-                             void **fault_addr, jmp_buf **fault_catcher);
-/*
- * strncpy_from_user: - Copy a NUL terminated string from userspace.
- * @dst:   Destination address, in kernel space.  This buffer must be at
- *         least @count bytes long.
- * @src:   Source address, in user space.
- * @count: Maximum number of bytes to copy, including the trailing NUL.
- *
- * Copies a NUL-terminated string from userspace to kernel space.
- *
- * On success, returns the length of the string (not including the trailing
- * NUL).
- *
- * If access to userspace fails, returns -EFAULT (some data may have been
- * copied).
- *
- * If @count is smaller than the length of the string, copies @count bytes
- * and returns @count.
- */
-extern int strncpy_from_user(char *dst, const char __user *src, int count);
-/*
- * __clear_user: - Zero a block of memory in user space, with less checking.
- * @to:   Destination address, in user space.
- * @n:    Number of bytes to zero.
- *
- * Zero a block of memory in user space.  Caller must check
- * the specified block with access_ok() before calling this function.
- *
- * Returns number of bytes that could not be cleared.
- * On success, this will be zero.
- */
-extern int __clear_user(void __user *mem, int len);
-/*
- * clear_user: - Zero a block of memory in user space.
- * @to:   Destination address, in user space.
- * @n:    Number of bytes to zero.
- *
- * Zero a block of memory in user space.
- *
- * Returns number of bytes that could not be cleared.
- * On success, this will be zero.
- */
-extern int clear_user(void __user *mem, int len);
-/*
- * strlen_user: - Get the size of a string in user space.
- * @str: The string to measure.
- * @n:   The maximum valid length
- *
- * Get the size of a NUL-terminated string in user space.
- *
- * Returns the size of the string INCLUDING the terminating NUL.
- * On exception, returns 0.
- * If the string is too long, returns a value greater than @n.
- */
-extern int strnlen_user(const void __user *str, int len);
-#endif
diff --git a/arch/um/include/shared/user.h b/arch/um/include/shared/user.h
index 293f7c794faa..4fa82c055aab 100644
--- a/arch/um/include/shared/user.h
+++ b/arch/um/include/shared/user.h
@@ -6,7 +6,7 @@
 #ifndef __USER_H__
 #define __USER_H__
-#include "kern_constants.h"
+#include <generated/asm-offsets.h>
 /*
 * The usual definition - copied here because the kernel provides its own,
@@ -36,10 +36,11 @@ static inline int printk(const char *fmt, ...)
 }
 #endif
-extern void schedule(void);
 extern int in_aton(char *str);
-extern int open_gdb_chan(void);
 extern size_t strlcpy(char *, const char *, size_t);
 extern size_t strlcat(char *, const char *, size_t);
+/* Copied from linux/compiler-gcc.h since we can't include it directly */
+#define barrier() __asm__ __volatile__("": : :"memory")
 #endif
diff --git a/arch/um/kernel/Makefile b/arch/um/kernel/Makefile
index c4491c15afb2..bc494741b1f3 100644
--- a/arch/um/kernel/Makefile
+++ b/arch/um/kernel/Makefile
@@ -11,7 +11,7 @@ clean-files :=
 obj-y = config.o exec.o exitcode.o init_task.o irq.o ksyms.o mem.o \
        physmem.o process.o ptrace.o reboot.o sigio.o \
-        signal.o smp.o syscall.o sysrq.o time.o tlb.o trap.o uaccess.o \
+        signal.o smp.o syscall.o sysrq.o time.o tlb.o trap.o \
        um_arch.o umid.o skas/
 obj-$(CONFIG_BLK_DEV_INITRD) += initrd.o
diff --git a/arch/um/kernel/exec.c b/arch/um/kernel/exec.c
index 939a4a67f0fd..6cade9366364 100644
--- a/arch/um/kernel/exec.c
+++ b/arch/um/kernel/exec.c
@@ -3,14 +3,15 @@
 * Licensed under the GPL
 */
-#include "linux/stddef.h"
+#include <linux/stddef.h>
-#include "linux/fs.h"
+#include <linux/module.h>
-#include "linux/ptrace.h"
+#include <linux/fs.h>
-#include "linux/sched.h"
+#include <linux/ptrace.h>
-#include "linux/slab.h"
+#include <linux/sched.h>
-#include "asm/current.h"
+#include <linux/slab.h>
-#include "asm/processor.h"
+#include <asm/current.h>
-#include "asm/uaccess.h"
+#include <asm/processor.h>
+#include <asm/uaccess.h>
 #include "as-layout.h"
 #include "mem_user.h"
 #include "skas.h"
@@ -41,6 +42,7 @@ void start_thread(struct pt_regs *regs, unsigned long eip, unsigned long esp)
        PT_REGS_IP(regs) = eip;
        PT_REGS_SP(regs) = esp;
 }
+EXPORT_SYMBOL(start_thread);
 static long execve1(const char *file,
                    const char __user *const __user *argv,
diff --git a/arch/um/kernel/gmon_syms.c b/arch/um/kernel/gmon_syms.c
index 72eccd2a4113..e9bcf247bcee 100644
--- a/arch/um/kernel/gmon_syms.c
+++ b/arch/um/kernel/gmon_syms.c
@@ -7,18 +7,3 @@
 extern void __bb_init_func(void *)  __attribute__((weak));
 EXPORT_SYMBOL(__bb_init_func);
-/*
- * This is defined (and referred to in profiling stub code) only by some GCC
- * versions in libgcov.
- *
- * Since SuSE backported the fix, we cannot handle it depending on GCC version.
- * So, unconditionally export it. But also give it a weak declaration, which
- * will be overridden by any other one.
- */
-extern void __gcov_init(void *) __attribute__((weak));
-EXPORT_SYMBOL(__gcov_init);
-extern void __gcov_merge_add(void *) __attribute__((weak));
-EXPORT_SYMBOL(__gcov_merge_add);
diff --git a/arch/um/kernel/initrd.c b/arch/um/kernel/initrd.c
index d386c75c88eb..10cc18f729fd 100644
--- a/arch/um/kernel/initrd.c
+++ b/arch/um/kernel/initrd.c
@@ -7,12 +7,12 @@
 #include "linux/bootmem.h"
 #include "linux/initrd.h"
 #include "asm/types.h"
-#include "initrd.h"
 #include "init.h"
 #include "os.h"
 /* Changed by uml_initrd_setup, which is a setup */
 static char *initrd __initdata = NULL;
+static int load_initrd(char *filename, void *buf, int size);
 static int __init read_initrd(void)
 {
@@ -62,7 +62,7 @@ __uml_setup("initrd=", uml_initrd_setup,
 "    name of the file containing the image.\n\n"
 );
-int load_initrd(char *filename, void *buf, int size)
+static int load_initrd(char *filename, void *buf, int size)
 {
        int fd, n;
diff --git a/arch/um/kernel/irq.c b/arch/um/kernel/irq.c
index 9e485c770308..71b8c947e5ef 100644
--- a/arch/um/kernel/irq.c
+++ b/arch/um/kernel/irq.c
@@ -258,6 +258,7 @@ void deactivate_fd(int fd, int irqnum)
        ignore_sigio_fd(fd);
 }
+EXPORT_SYMBOL(deactivate_fd);
 /*
 * Called just before shutdown in order to provide a clean exec
diff --git a/arch/um/kernel/ksyms.c b/arch/um/kernel/ksyms.c
index 0ae0dfcfbffb..e17bea0b22e1 100644
--- a/arch/um/kernel/ksyms.c
+++ b/arch/um/kernel/ksyms.c
@@ -3,33 +3,11 @@
 * Licensed under the GPL
 */
-#include "linux/module.h"
+#include <linux/module.h>
-#include "linux/syscalls.h"
-#include "asm/tlbflush.h"
-#include "asm/uaccess.h"
-#include "as-layout.h"
-#include "kern_util.h"
-#include "mem_user.h"
 #include "os.h"
-EXPORT_SYMBOL(uml_physmem);
 EXPORT_SYMBOL(set_signals);
 EXPORT_SYMBOL(get_signals);
-EXPORT_SYMBOL(kernel_thread);
-EXPORT_SYMBOL(sys_waitpid);
-EXPORT_SYMBOL(flush_tlb_range);
-EXPORT_SYMBOL(high_physmem);
-EXPORT_SYMBOL(empty_zero_page);
-EXPORT_SYMBOL(handle_page_fault);
-EXPORT_SYMBOL(find_iomem);
-EXPORT_SYMBOL(strnlen_user);
-EXPORT_SYMBOL(strncpy_from_user);
-EXPORT_SYMBOL(copy_to_user);
-EXPORT_SYMBOL(copy_from_user);
-EXPORT_SYMBOL(clear_user);
-EXPORT_SYMBOL(uml_strdup);
 EXPORT_SYMBOL(os_stat_fd);
 EXPORT_SYMBOL(os_stat_file);
@@ -57,24 +35,10 @@ EXPORT_SYMBOL(os_connect_socket);
 EXPORT_SYMBOL(os_accept_connection);
 EXPORT_SYMBOL(os_rcv_fd);
 EXPORT_SYMBOL(run_helper);
-EXPORT_SYMBOL(start_thread);
 EXPORT_SYMBOL(os_major);
 EXPORT_SYMBOL(os_minor);
 EXPORT_SYMBOL(os_makedev);
 EXPORT_SYMBOL(add_sigio_fd);
 EXPORT_SYMBOL(ignore_sigio_fd);
-EXPORT_SYMBOL(deactivate_fd);
 EXPORT_SYMBOL(sigio_broken);
-#ifdef CONFIG_SMP
-/* required for SMP */
-extern void __write_lock_failed(rwlock_t *rw);
-EXPORT_SYMBOL(__write_lock_failed);
-extern void __read_lock_failed(rwlock_t *rw);
-EXPORT_SYMBOL(__read_lock_failed);
-#endif
diff --git a/arch/um/kernel/mem.c b/arch/um/kernel/mem.c
index 8137ccc9635b..ebb86b218445 100644
--- a/arch/um/kernel/mem.c
+++ b/arch/um/kernel/mem.c
@@ -4,6 +4,7 @@
 */
 #include <linux/stddef.h>
+#include <linux/module.h>
 #include <linux/bootmem.h>
 #include <linux/highmem.h>
 #include <linux/mm.h>
@@ -20,6 +21,7 @@
 /* allocated in paging_init, zeroed in mem_init, and unchanged thereafter */
 unsigned long *empty_zero_page = NULL;
+EXPORT_SYMBOL(empty_zero_page);
 /* allocated in paging_init and unchanged thereafter */
 static unsigned long *empty_bad_page = NULL;
diff --git a/arch/um/kernel/physmem.c b/arch/um/kernel/physmem.c
index a1a9090254c2..f116db15d402 100644
--- a/arch/um/kernel/physmem.c
+++ b/arch/um/kernel/physmem.c
@@ -3,20 +3,22 @@
 * Licensed under the GPL
 */
-#include "linux/bootmem.h"
+#include <linux/module.h>
-#include "linux/mm.h"
+#include <linux/bootmem.h>
-#include "linux/pfn.h"
+#include <linux/mm.h>
-#include "asm/page.h"
+#include <linux/pfn.h>
-#include "as-layout.h"
+#include <asm/page.h>
-#include "init.h"
+#include <as-layout.h>
-#include "kern.h"
+#include <init.h>
-#include "mem_user.h"
+#include <kern.h>
-#include "os.h"
+#include <mem_user.h>
+#include <os.h>
 static int physmem_fd = -1;
 /* Changed during early boot */
 unsigned long high_physmem;
+EXPORT_SYMBOL(high_physmem);
 extern unsigned long long physmem_size;
@@ -184,6 +186,7 @@ unsigned long find_iomem(char *driver, unsigned long *len_out)
        return 0;
 }
+EXPORT_SYMBOL(find_iomem);
 static int setup_iomem(void)
 {
diff --git a/arch/um/kernel/process.c b/arch/um/kernel/process.c
index 21c1ae7c3d75..c5338351aecd 100644
--- a/arch/um/kernel/process.c
+++ b/arch/um/kernel/process.c
@@ -20,12 +20,12 @@
 #include <linux/threads.h>
 #include <asm/current.h>
 #include <asm/pgtable.h>
+#include <asm/mmu_context.h>
 #include <asm/uaccess.h>
 #include "as-layout.h"
 #include "kern_util.h"
 #include "os.h"
 #include "skas.h"
-#include "tlb.h"
 /*
 * This is a per-cpu array.  A processor only modifies its entry and it only
@@ -78,6 +78,7 @@ int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
                      &current->thread.regs, 0, NULL, NULL);
        return pid;
 }
+EXPORT_SYMBOL(kernel_thread);
 static inline void set_current(struct task_struct *task)
 {
@@ -286,6 +287,7 @@ char *uml_strdup(const char *string)
 {
        return kstrdup(string, GFP_KERNEL);
 }
+EXPORT_SYMBOL(uml_strdup);
 int copy_to_user_proc(void __user *to, void *from, int size)
 {
diff --git a/arch/um/kernel/signal.c b/arch/um/kernel/signal.c
index b5c094c4ade4..e8b889d3bce7 100644
--- a/arch/um/kernel/signal.c
+++ b/arch/um/kernel/signal.c
@@ -11,7 +11,6 @@
 #include <asm/unistd.h>
 #include "frame_kern.h"
 #include "kern_util.h"
-#include <sysdep/sigcontext.h>
 EXPORT_SYMBOL(block_signals);
 EXPORT_SYMBOL(unblock_signals);
diff --git a/arch/um/kernel/skas/clone.c b/arch/um/kernel/skas/clone.c
index 2c8583c1a344..e1fd066a3525 100644
--- a/arch/um/kernel/skas/clone.c
+++ b/arch/um/kernel/skas/clone.c
@@ -8,7 +8,6 @@
 #include <asm/unistd.h>
 #include <sys/time.h>
 #include "as-layout.h"
-#include "kern_constants.h"
 #include "ptrace_user.h"
 #include "stub-data.h"
 #include "sysdep/stub.h"
diff --git a/arch/um/kernel/skas/uaccess.c b/arch/um/kernel/skas/uaccess.c
index 696634214dc6..9fefd924fb49 100644
--- a/arch/um/kernel/skas/uaccess.c
+++ b/arch/um/kernel/skas/uaccess.c
@@ -6,6 +6,7 @@
 #include <linux/err.h>
 #include <linux/highmem.h>
 #include <linux/mm.h>
+#include <linux/module.h>
 #include <linux/sched.h>
 #include <asm/current.h>
 #include <asm/page.h>
@@ -149,6 +150,7 @@ int copy_from_user(void *to, const void __user *from, int n)
               buffer_op((unsigned long) from, n, 0, copy_chunk_from_user, &to):
               n;
 }
+EXPORT_SYMBOL(copy_from_user);
 static int copy_chunk_to_user(unsigned long to, int len, void *arg)
 {
@@ -170,6 +172,7 @@ int copy_to_user(void __user *to, const void *from, int n)
               buffer_op((unsigned long) to, n, 1, copy_chunk_to_user, &from) :
               n;
 }
+EXPORT_SYMBOL(copy_to_user);
 static int strncpy_chunk_from_user(unsigned long from, int len, void *arg)
 {
@@ -204,6 +207,7 @@ int strncpy_from_user(char *dst, const char __user *src, int count)
                return -EFAULT;
        return strnlen(dst, count);
 }
+EXPORT_SYMBOL(strncpy_from_user);
 static int clear_chunk(unsigned long addr, int len, void *unused)
 {
@@ -226,6 +230,7 @@ int clear_user(void __user *mem, int len)
        return access_ok(VERIFY_WRITE, mem, len) ?
               buffer_op((unsigned long) mem, len, 1, clear_chunk, NULL) : len;
 }
+EXPORT_SYMBOL(clear_user);
 static int strnlen_chunk(unsigned long str, int len, void *arg)
 {
@@ -251,3 +256,4 @@ int strnlen_user(const void __user *str, int len)
                return count + 1;
        return -EFAULT;
 }
+EXPORT_SYMBOL(strnlen_user);
diff --git a/arch/um/kernel/tlb.c b/arch/um/kernel/tlb.c
index d175d0566af0..7f3d4d86431a 100644
--- a/arch/um/kernel/tlb.c
+++ b/arch/um/kernel/tlb.c
@@ -4,6 +4,7 @@
 */
 #include <linux/mm.h>
+#include <linux/module.h>
 #include <linux/sched.h>
 #include <asm/pgtable.h>
 #include <asm/tlbflush.h>
@@ -11,7 +12,6 @@
 #include "mem_user.h"
 #include "os.h"
 #include "skas.h"
-#include "tlb.h"
 struct host_vm_change {
        struct host_vm_op {
@@ -287,7 +287,7 @@ void fix_range_common(struct mm_struct *mm, unsigned long start_addr,
        }
 }
-int flush_tlb_kernel_range_common(unsigned long start, unsigned long end)
+static int flush_tlb_kernel_range_common(unsigned long start, unsigned long end)
 {
        struct mm_struct *mm;
        pgd_t *pgd;
@@ -499,6 +499,7 @@ void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
                flush_tlb_kernel_range_common(start, end);
        else fix_range(vma->vm_mm, start, end, 0);
 }
+EXPORT_SYMBOL(flush_tlb_range);
 void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
                        unsigned long end)
diff --git a/arch/um/kernel/trap.c b/arch/um/kernel/trap.c
index 8c7b8823d1f0..dafc94715950 100644
--- a/arch/um/kernel/trap.c
+++ b/arch/um/kernel/trap.c
@@ -6,6 +6,7 @@
 #include <linux/mm.h>
 #include <linux/sched.h>
 #include <linux/hardirq.h>
+#include <linux/module.h>
 #include <asm/current.h>
 #include <asm/pgtable.h>
 #include <asm/tlbflush.h>
@@ -14,7 +15,6 @@
 #include "kern_util.h"
 #include "os.h"
 #include "skas.h"
-#include "sysdep/sigcontext.h"
 /*
 * Note this is constrained to return 0, -EFAULT, -EACCESS, -ENOMEM by
@@ -112,6 +112,7 @@ out_of_memory:
        pagefault_out_of_memory();
        return 0;
 }
+EXPORT_SYMBOL(handle_page_fault);
 static void show_segv_info(struct uml_pt_regs *regs)
 {
diff --git a/arch/um/kernel/uaccess.c b/arch/um/kernel/uaccess.c
deleted file mode 100644
index dd33f040c526..000000000000
--- a/arch/um/kernel/uaccess.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright (C) 2001 Chris Emerson (cemerson@chiark.greenend.org.uk)
- * Copyright (C) 2001 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
- * Licensed under the GPL
- */
-/*
- * These are here rather than tt/uaccess.c because skas mode needs them in
- * order to do SIGBUS recovery when a tmpfs mount runs out of room.
- */
-#include <linux/string.h>
-#include "os.h"
-static void __do_copy(void *to, const void *from, int n)
-{
-        memcpy(to, from, n);
-}
-int __do_copy_to_user(void *to, const void *from, int n,
-                      void **fault_addr, jmp_buf **fault_catcher)
-{
-        unsigned long fault;
-        int faulted;
-        fault = __do_user_copy(to, from, n, fault_addr, fault_catcher,
-                               __do_copy, &faulted);
-        if (!faulted)
-                return 0;
-        else
-                return n - (fault - (unsigned long) to);
-}
diff --git a/arch/um/kernel/um_arch.c b/arch/um/kernel/um_arch.c
index 8d84250324b3..ba00eae45aad 100644
--- a/arch/um/kernel/um_arch.c
+++ b/arch/um/kernel/um_arch.c
@@ -102,6 +102,8 @@ const struct seq_operations cpuinfo_op = {
 /* Set in linux_main */
 unsigned long uml_physmem;
+EXPORT_SYMBOL(uml_physmem);
 unsigned long uml_reserved; /* Also modified in mem_init */
 unsigned long start_vm;
 unsigned long end_vm;
diff --git a/arch/um/os-Linux/Makefile b/arch/um/os-Linux/Makefile
index b33f4dfe7ae5..dd764101e488 100644
--- a/arch/um/os-Linux/Makefile
+++ b/arch/um/os-Linux/Makefile
@@ -4,14 +4,14 @@
 #
 obj-y = aio.o execvp.o file.o helper.o irq.o main.o mem.o process.o \
-        registers.o sigio.o signal.o start_up.o time.o tty.o uaccess.o \
+        registers.o sigio.o signal.o start_up.o time.o tty.o \
-        umid.o tls.o user_syms.o util.o drivers/ sys-$(SUBARCH)/ skas/
+        umid.o user_syms.o util.o drivers/ skas/
 obj-$(CONFIG_ARCH_REUSE_HOST_VSYSCALL_AREA) += elf_aux.o
 USER_OBJS := $(user-objs-y) aio.o elf_aux.o execvp.o file.o helper.o irq.o \
        main.o mem.o process.o registers.o sigio.o signal.o start_up.o time.o \
-        tty.o tls.o uaccess.o umid.o util.o
+        tty.o umid.o util.o
 CFLAGS_user_syms.o += -DSUBARCH_$(SUBARCH)
diff --git a/arch/um/os-Linux/aio.c b/arch/um/os-Linux/aio.c
index 57e3d46c989c..c5d039e1ff3b 100644
--- a/arch/um/os-Linux/aio.c
+++ b/arch/um/os-Linux/aio.c
@@ -11,10 +11,8 @@
 #include <asm/unistd.h>
 #include "aio.h"
 #include "init.h"
-#include "kern_constants.h"
 #include "kern_util.h"
 #include "os.h"
-#include "user.h"
 struct aio_thread_req {
        enum aio_type type;
diff --git a/arch/um/os-Linux/drivers/ethertap_user.c b/arch/um/os-Linux/drivers/ethertap_user.c
index cc72cb2c1af6..db3d6481375a 100644
--- a/arch/um/os-Linux/drivers/ethertap_user.c
+++ b/arch/um/os-Linux/drivers/ethertap_user.c
@@ -13,11 +13,9 @@
 #include <sys/socket.h>
 #include <sys/wait.h>
 #include "etap.h"
-#include "kern_constants.h"
 #include "os.h"
 #include "net_user.h"
 #include "um_malloc.h"
-#include "user.h"
 #define MAX_PACKET ETH_MAX_PACKET
diff --git a/arch/um/os-Linux/drivers/tuntap_user.c b/arch/um/os-Linux/drivers/tuntap_user.c
index 2448be03fd7a..a2aacffdd907 100644
--- a/arch/um/os-Linux/drivers/tuntap_user.c
+++ b/arch/um/os-Linux/drivers/tuntap_user.c
@@ -13,11 +13,9 @@
 #include <sys/socket.h>
 #include <sys/wait.h>
 #include <sys/uio.h>
-#include "kern_constants.h"
 #include "kern_util.h"
 #include "os.h"
 #include "tuntap.h"
-#include "user.h"
 static int tuntap_user_init(void *data, void *dev)
 {
diff --git a/arch/um/os-Linux/elf_aux.c b/arch/um/os-Linux/elf_aux.c
index 953323799381..d895271ad6f7 100644
--- a/arch/um/os-Linux/elf_aux.c
+++ b/arch/um/os-Linux/elf_aux.c
@@ -12,7 +12,6 @@
 #include "init.h"
 #include "elf_user.h"
 #include "mem_user.h"
-#include <kern_constants.h>
 typedef Elf32_auxv_t elf_auxv_t;
diff --git a/arch/um/os-Linux/file.c b/arch/um/os-Linux/file.c
index 140e587bc0ad..b049a63bb74b 100644
--- a/arch/um/os-Linux/file.c
+++ b/arch/um/os-Linux/file.c
@@ -13,9 +13,7 @@
 #include <sys/socket.h>
 #include <sys/stat.h>
 #include <sys/un.h>
-#include "kern_constants.h"
 #include "os.h"
-#include "user.h"
 static void copy_stat(struct uml_stat *dst, const struct stat64 *src)
 {
diff --git a/arch/um/os-Linux/helper.c b/arch/um/os-Linux/helper.c
index feff22d64672..cf26c4a9a43a 100644
--- a/arch/um/os-Linux/helper.c
+++ b/arch/um/os-Linux/helper.c
@@ -10,11 +10,9 @@
 #include <linux/limits.h>
 #include <sys/socket.h>
 #include <sys/wait.h>
-#include "kern_constants.h"
 #include "kern_util.h"
 #include "os.h"
 #include "um_malloc.h"
-#include "user.h"
 struct helper_data {
        void (*pre_exec)(void*);
diff --git a/arch/um/os-Linux/internal.h b/arch/um/os-Linux/internal.h
new file mode 100644
index 000000000000..2c3c3ecd8c01
--- /dev/null
+++ b/arch/um/os-Linux/internal.h
@@ -0,0 +1 @@
+void alarm_handler(int, mcontext_t *);
diff --git a/arch/um/os-Linux/irq.c b/arch/um/os-Linux/irq.c
index 0348b975e81c..9a49908b576c 100644
--- a/arch/um/os-Linux/irq.c
+++ b/arch/um/os-Linux/irq.c
@@ -9,11 +9,8 @@
 #include <signal.h>
 #include <string.h>
 #include "irq_user.h"
-#include "kern_constants.h"
 #include "os.h"
-#include "process.h"
 #include "um_malloc.h"
-#include "user.h"
 /*
 * Locked by irq_lock in arch/um/kernel/irq.c.  Changed by os_create_pollfd
diff --git a/arch/um/os-Linux/main.c b/arch/um/os-Linux/main.c
index 8471b817d94f..7a86dd516eb1 100644
--- a/arch/um/os-Linux/main.c
+++ b/arch/um/os-Linux/main.c
@@ -12,7 +12,6 @@
 #include <sys/resource.h>
 #include "as-layout.h"
 #include "init.h"
-#include "kern_constants.h"
 #include "kern_util.h"
 #include "os.h"
 #include "um_malloc.h"
diff --git a/arch/um/os-Linux/mem.c b/arch/um/os-Linux/mem.c
index 62878cf1d33f..8e421e1d6d36 100644
--- a/arch/um/os-Linux/mem.c
+++ b/arch/um/os-Linux/mem.c
@@ -14,9 +14,7 @@
 #include <sys/mman.h>
 #include <sys/param.h>
 #include "init.h"
-#include "kern_constants.h"
 #include "os.h"
-#include "user.h"
 /* Modified by which_tmpdir, which is called during early boot */
 static char *default_tmpdir = "/tmp";
diff --git a/arch/um/os-Linux/process.c b/arch/um/os-Linux/process.c
index 0c45dc8efb05..307f173e7f82 100644
--- a/arch/um/os-Linux/process.c
+++ b/arch/um/os-Linux/process.c
@@ -13,12 +13,9 @@
 #include <sys/wait.h>
 #include <asm/unistd.h>
 #include "init.h"
-#include "kern_constants.h"
 #include "longjmp.h"
 #include "os.h"
-#include "process.h"
 #include "skas_ptrace.h"
-#include "user.h"
 #define ARBITRARY_ADDR -1
 #define FAILURE_PID    -1
@@ -237,21 +234,13 @@ out:
 void init_new_thread_signals(void)
 {
-        set_handler(SIGSEGV, (__sighandler_t) sig_handler, SA_ONSTACK,
+        set_handler(SIGSEGV);
-                    SIGUSR1, SIGIO, SIGWINCH, SIGVTALRM, -1);
+        set_handler(SIGTRAP);
-        set_handler(SIGTRAP, (__sighandler_t) sig_handler, SA_ONSTACK,
+        set_handler(SIGFPE);
-                    SIGUSR1, SIGIO, SIGWINCH, SIGVTALRM, -1);
+        set_handler(SIGILL);
-        set_handler(SIGFPE, (__sighandler_t) sig_handler, SA_ONSTACK,
+        set_handler(SIGBUS);
-                    SIGUSR1, SIGIO, SIGWINCH, SIGVTALRM, -1);
-        set_handler(SIGILL, (__sighandler_t) sig_handler, SA_ONSTACK,
-                    SIGUSR1, SIGIO, SIGWINCH, SIGVTALRM, -1);
-        set_handler(SIGBUS, (__sighandler_t) sig_handler, SA_ONSTACK,
-                    SIGUSR1, SIGIO, SIGWINCH, SIGVTALRM, -1);
        signal(SIGHUP, SIG_IGN);
+        set_handler(SIGIO);
-        set_handler(SIGIO, (__sighandler_t) sig_handler,
-                    SA_ONSTACK | SA_RESTART, SIGUSR1, SIGIO, SIGWINCH, SIGALRM,
-                    SIGVTALRM, -1);
        signal(SIGWINCH, SIG_IGN);
        signal(SIGTERM, SIG_DFL);
 }
diff --git a/arch/um/os-Linux/sigio.c b/arch/um/os-Linux/sigio.c
index 63d299df152b..3c161218c671 100644
--- a/arch/um/os-Linux/sigio.c
+++ b/arch/um/os-Linux/sigio.c
@@ -11,14 +11,11 @@
 #include <sched.h>
 #include <signal.h>
 #include <string.h>
-#include "kern_constants.h"
 #include "kern_util.h"
 #include "init.h"
 #include "os.h"
-#include "process.h"
 #include "sigio.h"
 #include "um_malloc.h"
-#include "user.h"
 /*
 * Protected by sigio_lock(), also used by sigio_cleanup, which is an
diff --git a/arch/um/os-Linux/signal.c b/arch/um/os-Linux/signal.c
index 6ae180703a63..2d22f1fcd8e2 100644
--- a/arch/um/os-Linux/signal.c
+++ b/arch/um/os-Linux/signal.c
@@ -12,13 +12,7 @@
 #include "as-layout.h"
 #include "kern_util.h"
 #include "os.h"
-#include "process.h"
+#include "sysdep/mcontext.h"
-#include "sysdep/barrier.h"
-#include "sysdep/sigcontext.h"
-#include "user.h"
-/* Copied from linux/compiler-gcc.h since we can't include it directly */
-#define barrier() __asm__ __volatile__("": : :"memory")
 void (*sig_info[NSIG])(int, struct uml_pt_regs *) = {
        [SIGTRAP]       = relay_signal,
@@ -30,7 +24,7 @@ void (*sig_info[NSIG])(int, struct uml_pt_regs *) = {
        [SIGIO]         = sigio_handler,
        [SIGVTALRM]     = timer_handler };
-static void sig_handler_common(int sig, struct sigcontext *sc)
+static void sig_handler_common(int sig, mcontext_t *mc)
 {
        struct uml_pt_regs r;
        int save_errno = errno;
@@ -38,8 +32,8 @@ static void sig_handler_common(int sig, struct sigcontext *sc)
        r.is_user = 0;
        if (sig == SIGSEGV) {
                /* For segfaults, we want the data from the sigcontext. */
-                copy_sc(&r, sc);
+                get_regs_from_mc(&r, mc);
-                GET_FAULTINFO_FROM_SC(r.faultinfo, sc);
+                GET_FAULTINFO_FROM_MC(r.faultinfo, mc);
        }
        /* enable signals if sig isn't IRQ signal */
@@ -66,7 +60,7 @@ static void sig_handler_common(int sig, struct sigcontext *sc)
 static int signals_enabled;
 static unsigned int signals_pending;
-void sig_handler(int sig, struct sigcontext *sc)
+void sig_handler(int sig, mcontext_t *mc)
 {
        int enabled;
@@ -78,23 +72,23 @@ void sig_handler(int sig, struct sigcontext *sc)
        block_signals();
-        sig_handler_common(sig, sc);
+        sig_handler_common(sig, mc);
        set_signals(enabled);
 }
-static void real_alarm_handler(struct sigcontext *sc)
+static void real_alarm_handler(mcontext_t *mc)
 {
        struct uml_pt_regs regs;
-        if (sc != NULL)
+        if (mc != NULL)
-                copy_sc(&regs, sc);
+                get_regs_from_mc(&regs, mc);
        regs.is_user = 0;
        unblock_signals();
        timer_handler(SIGVTALRM, &regs);
 }
-void alarm_handler(int sig, struct sigcontext *sc)
+void alarm_handler(int sig, mcontext_t *mc)
 {
        int enabled;
@@ -106,14 +100,13 @@ void alarm_handler(int sig, struct sigcontext *sc)
        block_signals();
-        real_alarm_handler(sc);
+        real_alarm_handler(mc);
        set_signals(enabled);
 }
 void timer_init(void)
 {
-        set_handler(SIGVTALRM, (__sighandler_t) alarm_handler,
+        set_handler(SIGVTALRM);
-                    SA_ONSTACK | SA_RESTART, SIGUSR1, SIGIO, SIGWINCH, -1);
 }
 void set_sigstack(void *sig_stack, int size)
@@ -126,10 +119,23 @@ void set_sigstack(void *sig_stack, int size)
                panic("enabling signal stack failed, errno = %d\n", errno);
 }
-static void (*handlers[_NSIG])(int sig, struct sigcontext *sc);
+static void (*handlers[_NSIG])(int sig, mcontext_t *mc) = {
+        [SIGSEGV] = sig_handler,
+        [SIGBUS] = sig_handler,
+        [SIGILL] = sig_handler,
+        [SIGFPE] = sig_handler,
+        [SIGTRAP] = sig_handler,
+        [SIGIO] = sig_handler,
+        [SIGWINCH] = sig_handler,
+        [SIGVTALRM] = alarm_handler
+};
-void handle_signal(int sig, struct sigcontext *sc)
+static void hard_handler(int sig, siginfo_t *info, void *p)
 {
+        struct ucontext *uc = p;
+        mcontext_t *mc = &uc->uc_mcontext;
        unsigned long pending = 1UL << sig;
        do {
@@ -155,7 +161,7 @@ void handle_signal(int sig, struct sigcontext *sc)
                while ((sig = ffs(pending)) != 0){
                        sig--;
                        pending &= ~(1 << sig);
-                        (*handlers[sig])(sig, sc);
+                        (*handlers[sig])(sig, mc);
                }
                /*
@@ -169,28 +175,26 @@ void handle_signal(int sig, struct sigcontext *sc)
        } while (pending);
 }
-extern void hard_handler(int sig);
+void set_handler(int sig)
-void set_handler(int sig, void (*handler)(int), int flags, ...)
 {
        struct sigaction action;
-        va_list ap;
+        int flags = SA_SIGINFO | SA_ONSTACK;
        sigset_t sig_mask;
-        int mask;
-        handlers[sig] = (void (*)(int, struct sigcontext *)) handler;
+        action.sa_sigaction = hard_handler;
-        action.sa_handler = hard_handler;
+        /* block irq ones */
        sigemptyset(&action.sa_mask);
+        sigaddset(&action.sa_mask, SIGVTALRM);
-        va_start(ap, flags);
+        sigaddset(&action.sa_mask, SIGIO);
-        while ((mask = va_arg(ap, int)) != -1)
+        sigaddset(&action.sa_mask, SIGWINCH);
-                sigaddset(&action.sa_mask, mask);
-        va_end(ap);
        if (sig == SIGSEGV)
                flags |= SA_NODEFER;
+        if (sigismember(&action.sa_mask, sig))
+                flags |= SA_RESTART; /* if it's an irq signal */
        action.sa_flags = flags;
        action.sa_restorer = NULL;
        if (sigaction(sig, &action, NULL) < 0)
diff --git a/arch/um/os-Linux/skas/mem.c b/arch/um/os-Linux/skas/mem.c
index e771398be5f3..c0afff7af4bd 100644
--- a/arch/um/os-Linux/skas/mem.c
+++ b/arch/um/os-Linux/skas/mem.c
@@ -9,7 +9,6 @@
 #include <string.h>
 #include <sys/mman.h>
 #include "init.h"
-#include "kern_constants.h"
 #include "as-layout.h"
 #include "mm_id.h"
 #include "os.h"
@@ -17,7 +16,6 @@
 #include "ptrace_user.h"
 #include "registers.h"
 #include "skas.h"
-#include "user.h"
 #include "sysdep/ptrace.h"
 #include "sysdep/stub.h"
diff --git a/arch/um/os-Linux/skas/process.c b/arch/um/os-Linux/skas/process.c
index dee0e8cf8ad0..cd65727854eb 100644
--- a/arch/um/os-Linux/skas/process.c
+++ b/arch/um/os-Linux/skas/process.c
@@ -9,31 +9,23 @@
 #include <errno.h>
 #include <string.h>
 #include <sys/mman.h>
-#include <sys/ptrace.h>
 #include <sys/wait.h>
 #include <asm/unistd.h>
 #include "as-layout.h"
-#include "chan_user.h"
+#include "init.h"
-#include "kern_constants.h"
 #include "kern_util.h"
 #include "mem.h"
 #include "os.h"
-#include "process.h"
 #include "proc_mm.h"
 #include "ptrace_user.h"
 #include "registers.h"
 #include "skas.h"
 #include "skas_ptrace.h"
-#include "user.h"
 #include "sysdep/stub.h"
 int is_skas_winch(int pid, int fd, void *data)
 {
-        if (pid != getpgrp())
+        return pid == getpgrp();
-                return 0;
-        register_winch_irq(-1, fd, -1, data, 0);
-        return 1;
 }
 static int ptrace_dump_regs(int pid)
@@ -169,7 +161,7 @@ static void handle_trap(int pid, struct uml_pt_regs *regs,
        if (!local_using_sysemu)
        {
-                err = ptrace(PTRACE_POKEUSR, pid, PT_SYSCALL_NR_OFFSET,
+                err = ptrace(PTRACE_POKEUSER, pid, PT_SYSCALL_NR_OFFSET,
                             __NR_getpid);
                if (err < 0) {
                        printk(UM_KERN_ERR "handle_trap - nullifying syscall "
@@ -257,8 +249,8 @@ static int userspace_tramp(void *stack)
                set_sigstack((void *) STUB_DATA, UM_KERN_PAGE_SIZE);
                sigemptyset(&sa.sa_mask);
-                sa.sa_flags = SA_ONSTACK | SA_NODEFER;
+                sa.sa_flags = SA_ONSTACK | SA_NODEFER | SA_SIGINFO;
-                sa.sa_handler = (void *) v;
+                sa.sa_sigaction = (void *) v;
                sa.sa_restorer = NULL;
                if (sigaction(SIGSEGV, &sa, NULL) < 0) {
                        printk(UM_KERN_ERR "userspace_tramp - setting SIGSEGV "
@@ -661,8 +653,7 @@ int start_idle_thread(void *stack, jmp_buf *switch_buf)
 {
        int n;
-        set_handler(SIGWINCH, (__sighandler_t) sig_handler,
+        set_handler(SIGWINCH);
-                    SA_ONSTACK | SA_RESTART, SIGUSR1, SIGIO, SIGVTALRM, -1);
        /*
         * Can't use UML_SETJMP or UML_LONGJMP here because they save
diff --git a/arch/um/os-Linux/start_up.c b/arch/um/os-Linux/start_up.c
index 02ee9adff54a..425162e22af5 100644
--- a/arch/um/os-Linux/start_up.c
+++ b/arch/um/os-Linux/start_up.c
@@ -13,12 +13,10 @@
 #include <signal.h>
 #include <string.h>
 #include <sys/mman.h>
-#include <sys/ptrace.h>
 #include <sys/stat.h>
 #include <sys/wait.h>
 #include <asm/unistd.h>
 #include "init.h"
-#include "kern_constants.h"
 #include "os.h"
 #include "mem_user.h"
 #include "ptrace_user.h"
@@ -225,7 +223,7 @@ static void __init check_sysemu(void)
                goto fail;
        }
-        n = ptrace(PTRACE_POKEUSR, pid, PT_SYSCALL_RET_OFFSET, os_getpid());
+        n = ptrace(PTRACE_POKEUSER, pid, PT_SYSCALL_RET_OFFSET, os_getpid());
        if (n < 0) {
                non_fatal("check_sysemu : failed to modify system call "
                          "return");
@@ -261,7 +259,7 @@ static void __init check_sysemu(void)
                                          "doesn't singlestep");
                                goto fail;
                        }
-                        n = ptrace(PTRACE_POKEUSR, pid, PT_SYSCALL_RET_OFFSET,
+                        n = ptrace(PTRACE_POKEUSER, pid, PT_SYSCALL_RET_OFFSET,
                                   os_getpid());
                        if (n < 0)
                                fatal_perror("check_sysemu : failed to modify "
@@ -317,10 +315,10 @@ static void __init check_ptrace(void)
                        fatal("check_ptrace : expected (SIGTRAP|0x80), "
                               "got status = %d", status);
-                syscall = ptrace(PTRACE_PEEKUSR, pid, PT_SYSCALL_NR_OFFSET,
+                syscall = ptrace(PTRACE_PEEKUSER, pid, PT_SYSCALL_NR_OFFSET,
                                 0);
                if (syscall == __NR_getpid) {
-                        n = ptrace(PTRACE_POKEUSR, pid, PT_SYSCALL_NR_OFFSET,
+                        n = ptrace(PTRACE_POKEUSER, pid, PT_SYSCALL_NR_OFFSET,
                                   __NR_getppid);
                        if (n < 0)
                                fatal_perror("check_ptrace : failed to modify "
diff --git a/arch/um/os-Linux/sys-i386/signal.c b/arch/um/os-Linux/sys-i386/signal.c
deleted file mode 100644
index f311609f93da..000000000000
--- a/arch/um/os-Linux/sys-i386/signal.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright (C) 2006 Jeff Dike (jdike@{addtoit,linux.intel}.com)
- * Licensed under the GPL
- */
-#include <signal.h>
-extern void handle_signal(int sig, struct sigcontext *sc);
-void hard_handler(int sig)
-{
-        handle_signal(sig, (struct sigcontext *) (&sig + 1));
-}
diff --git a/arch/um/os-Linux/sys-x86_64/Makefile b/arch/um/os-Linux/sys-x86_64/Makefile
deleted file mode 100644
index a44a47f8f57b..000000000000
--- a/arch/um/os-Linux/sys-x86_64/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Copyright (C) 2000 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
-# Licensed under the GPL
-#
-obj-y = registers.o prctl.o signal.o task_size.o
-USER_OBJS := $(obj-y)
-include arch/um/scripts/Makefile.rules
diff --git a/arch/um/os-Linux/sys-x86_64/registers.c b/arch/um/os-Linux/sys-x86_64/registers.c
deleted file mode 100644
index 594d97ad02b3..000000000000
--- a/arch/um/os-Linux/sys-x86_64/registers.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright (C) 2006 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
- * Licensed under the GPL
- */
-#include <errno.h>
-#include <sys/ptrace.h>
-#define __FRAME_OFFSETS
-#include <asm/ptrace.h>
-#include "kern_constants.h"
-#include "longjmp.h"
-#include "user.h"
-int save_fp_registers(int pid, unsigned long *fp_regs)
-{
-        if (ptrace(PTRACE_GETFPREGS, pid, 0, fp_regs) < 0)
-                return -errno;
-        return 0;
-}
-int restore_fp_registers(int pid, unsigned long *fp_regs)
-{
-        if (ptrace(PTRACE_SETFPREGS, pid, 0, fp_regs) < 0)
-                return -errno;
-        return 0;
-}
-unsigned long get_thread_reg(int reg, jmp_buf *buf)
-{
-        switch (reg) {
-        case RIP:
-                return buf[0]->__rip;
-        case RSP:
-                return buf[0]->__rsp;
-        case RBP:
-                return buf[0]->__rbp;
-        default:
-                printk(UM_KERN_ERR "get_thread_regs - unknown register %d\n",
-                       reg);
-                return 0;
-        }
-}
-int get_fp_registers(int pid, unsigned long *regs)
-{
-        return save_fp_registers(pid, regs);
-}
-int put_fp_registers(int pid, unsigned long *regs)
-{
-        return restore_fp_registers(pid, regs);
-}
diff --git a/arch/um/os-Linux/sys-x86_64/signal.c b/arch/um/os-Linux/sys-x86_64/signal.c
deleted file mode 100644
index 82a388822cd3..000000000000
--- a/arch/um/os-Linux/sys-x86_64/signal.c
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * Copyright (C) 2006 Jeff Dike (jdike@{addtoit,linux.intel}.com)
- * Licensed under the GPL
- */
-#include <signal.h>
-extern void handle_signal(int sig, struct sigcontext *sc);
-void hard_handler(int sig)
-{
-        struct ucontext *uc;
-        asm("movq %%rdx, %0" : "=r" (uc));
-        handle_signal(sig, (struct sigcontext *) &uc->uc_mcontext);
-}
diff --git a/arch/um/os-Linux/sys-x86_64/task_size.c b/arch/um/os-Linux/sys-x86_64/task_size.c
deleted file mode 100644
index 26a0dd1f349c..000000000000
--- a/arch/um/os-Linux/sys-x86_64/task_size.c
+++ /dev/null
@@ -1,5 +0,0 @@
-unsigned long os_get_top_address(unsigned long shift)
-{
-        /* The old value of CONFIG_TOP_ADDR */
-        return 0x7fc0000000;
-}
diff --git a/arch/um/os-Linux/time.c b/arch/um/os-Linux/time.c
index 6e3359d6a839..910499d76a67 100644
--- a/arch/um/os-Linux/time.c
+++ b/arch/um/os-Linux/time.c
@@ -8,11 +8,9 @@
 #include <signal.h>
 #include <time.h>
 #include <sys/time.h>
-#include "kern_constants.h"
 #include "kern_util.h"
 #include "os.h"
-#include "process.h"
+#include "internal.h"
-#include "user.h"
 int set_interval(void)
 {
diff --git a/arch/um/os-Linux/tls.c b/arch/um/os-Linux/tls.c
deleted file mode 100644
index 73277801ef14..000000000000
--- a/arch/um/os-Linux/tls.c
+++ /dev/null
@@ -1,35 +0,0 @@
-#include <errno.h>
-#include <sys/ptrace.h>
-#include "sysdep/tls.h"
-/* TLS support - we basically rely on the host's one.*/
-#ifndef PTRACE_GET_THREAD_AREA
-#define PTRACE_GET_THREAD_AREA 25
-#endif
-#ifndef PTRACE_SET_THREAD_AREA
-#define PTRACE_SET_THREAD_AREA 26
-#endif
-int os_set_thread_area(user_desc_t *info, int pid)
-{
-        int ret;
-        ret = ptrace(PTRACE_SET_THREAD_AREA, pid, info->entry_number,
-                     (unsigned long) info);
-        if (ret < 0)
-                ret = -errno;
-        return ret;
-}
-int os_get_thread_area(user_desc_t *info, int pid)
-{
-        int ret;
-        ret = ptrace(PTRACE_GET_THREAD_AREA, pid, info->entry_number,
-                     (unsigned long) info);
-        if (ret < 0)
-                ret = -errno;
-        return ret;
-}
diff --git a/arch/um/os-Linux/tty.c b/arch/um/os-Linux/tty.c
index b09ff66a77ee..dd12b99dcb59 100644
--- a/arch/um/os-Linux/tty.c
+++ b/arch/um/os-Linux/tty.c
@@ -7,10 +7,8 @@
 #include <unistd.h>
 #include <errno.h>
 #include <fcntl.h>
-#include "kern_constants.h"
 #include "kern_util.h"
 #include "os.h"
-#include "user.h"
 struct grantpt_info {
        int fd;
diff --git a/arch/um/os-Linux/uaccess.c b/arch/um/os-Linux/uaccess.c
deleted file mode 100644
index 087ed74ffca5..000000000000
--- a/arch/um/os-Linux/uaccess.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright (C) 2001 Chris Emerson (cemerson@chiark.greenend.org.uk)
- * Copyright (C) 2001 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
- * Licensed under the GPL
- */
-#include <stddef.h>
-#include "longjmp.h"
-unsigned long __do_user_copy(void *to, const void *from, int n,
-                             void **fault_addr, jmp_buf **fault_catcher,
-                             void (*op)(void *to, const void *from,
-                                        int n), int *faulted_out)
-{
-        unsigned long *faddrp = (unsigned long *) fault_addr, ret;
-        jmp_buf jbuf;
-        *fault_catcher = &jbuf;
-        if (UML_SETJMP(&jbuf) == 0) {
-                (*op)(to, from, n);
-                ret = 0;
-                *faulted_out = 0;
-        }
-        else {
-                ret = *faddrp;
-                *faulted_out = 1;
-        }
-        *fault_addr = NULL;
-        *fault_catcher = NULL;
-        return ret;
-}
diff --git a/arch/um/os-Linux/umid.c b/arch/um/os-Linux/umid.c
index a27defb81884..4832eb519f8d 100644
--- a/arch/um/os-Linux/umid.c
+++ b/arch/um/os-Linux/umid.c
@@ -13,9 +13,7 @@
 #include <unistd.h>
 #include <sys/stat.h>
 #include "init.h"
-#include "kern_constants.h"
 #include "os.h"
-#include "user.h"
 #define UML_DIR "~/.uml/"
diff --git a/arch/um/os-Linux/util.c b/arch/um/os-Linux/util.c
index 5803b1887672..9e3b43bb84c9 100644
--- a/arch/um/os-Linux/util.c
+++ b/arch/um/os-Linux/util.c
@@ -13,9 +13,7 @@
 #include <wait.h>
 #include <sys/mman.h>
 #include <sys/utsname.h>
-#include "kern_constants.h"
 #include "os.h"
-#include "user.h"
 void stack_protections(unsigned long address)
 {
diff --git a/arch/um/scripts/Makefile.rules b/arch/um/scripts/Makefile.rules
index 61107b68e05b..2eb2843b0634 100644
--- a/arch/um/scripts/Makefile.rules
+++ b/arch/um/scripts/Makefile.rules
@@ -8,7 +8,7 @@ USER_OBJS += $(filter %_user.o,$(obj-y) $(obj-m)  $(USER_SINGLE_OBJS))
 USER_OBJS := $(foreach file,$(USER_OBJS),$(obj)/$(file))
 $(USER_OBJS:.o=.%): \
-        c_flags = -Wp,-MD,$(depfile) $(USER_CFLAGS) $(CFLAGS_$(basetarget).o)
+        c_flags = -Wp,-MD,$(depfile) $(USER_CFLAGS) -include user.h $(CFLAGS_$(basetarget).o)
 $(USER_OBJS) : CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ \
        -Dunix -D__unix__ -D__$(SUBARCH)__ $(CF)
@@ -25,8 +25,3 @@ $(UNPROFILE_OBJS) : CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ \
 define unprofile
        $(patsubst -pg,,$(patsubst -fprofile-arcs -ftest-coverage,,$(1)))
 endef
-ifdef subarch-obj-y
-obj-y += subarch.o
-subarch-y = $(addprefix ../../$(HEADER_ARCH)/,$(subarch-obj-y))
-endif
diff --git a/arch/um/sys-i386/Makefile b/arch/um/sys-i386/Makefile
deleted file mode 100644
index 3923cfb87649..000000000000
--- a/arch/um/sys-i386/Makefile
+++ /dev/null
@@ -1,24 +0,0 @@
-#
-# Copyright (C) 2002 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
-#
-obj-y = bug.o bugs.o checksum.o delay.o fault.o ksyms.o ldt.o ptrace.o \
-        ptrace_user.o setjmp.o signal.o stub.o stub_segv.o syscalls.o sysrq.o \
-        sys_call_table.o tls.o atomic64_cx8_32.o mem.o
-obj-$(CONFIG_BINFMT_ELF) += elfcore.o
-subarch-obj-y = lib/string_32.o
-subarch-obj-$(CONFIG_RWSEM_XCHGADD_ALGORITHM) += lib/rwsem.o
-subarch-obj-$(CONFIG_HIGHMEM) += mm/highmem_32.o
-subarch-obj-$(CONFIG_MODULES) += kernel/module.o
-USER_OBJS := bugs.o ptrace_user.o fault.o
-USER_OBJS += user-offsets.s
-extra-y += user-offsets.s
-UNPROFILE_OBJS := stub_segv.o
-CFLAGS_stub_segv.o := $(CFLAGS_NO_HARDENING)
-include arch/um/scripts/Makefile.rules
diff --git a/arch/um/sys-i386/asm/elf.h b/arch/um/sys-i386/asm/elf.h
deleted file mode 100644
index 42305551d204..000000000000
--- a/arch/um/sys-i386/asm/elf.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * Copyright (C) 2000 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
- * Licensed under the GPL
- */
-#ifndef __UM_ELF_I386_H
-#define __UM_ELF_I386_H
-#include <asm/user.h>
-#include "skas.h"
-#define R_386_NONE      0
-#define R_386_32        1
-#define R_386_PC32      2
-#define R_386_GOT32     3
-#define R_386_PLT32     4
-#define R_386_COPY      5
-#define R_386_GLOB_DAT  6
-#define R_386_JMP_SLOT  7
-#define R_386_RELATIVE  8
-#define R_386_GOTOFF    9
-#define R_386_GOTPC     10
-#define R_386_NUM       11
-typedef unsigned long elf_greg_t;
-#define ELF_NGREG (sizeof (struct user_regs_struct) / sizeof(elf_greg_t))
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-typedef struct user_i387_struct elf_fpregset_t;
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x) \
-        (((x)->e_machine == EM_386) || ((x)->e_machine == EM_486))
-#define ELF_CLASS       ELFCLASS32
-#define ELF_DATA        ELFDATA2LSB
-#define ELF_ARCH        EM_386
-#define ELF_PLAT_INIT(regs, load_addr) do { \
-        PT_REGS_EBX(regs) = 0; \
-        PT_REGS_ECX(regs) = 0; \
-        PT_REGS_EDX(regs) = 0; \
-        PT_REGS_ESI(regs) = 0; \
-        PT_REGS_EDI(regs) = 0; \
-        PT_REGS_EBP(regs) = 0; \
-        PT_REGS_EAX(regs) = 0; \
-} while (0)
-#define ELF_EXEC_PAGESIZE 4096
-#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3)
-/* Shamelessly stolen from include/asm-i386/elf.h */
-#define ELF_CORE_COPY_REGS(pr_reg, regs) do {   \
-        pr_reg[0] = PT_REGS_EBX(regs);          \
-        pr_reg[1] = PT_REGS_ECX(regs);          \
-        pr_reg[2] = PT_REGS_EDX(regs);          \
-        pr_reg[3] = PT_REGS_ESI(regs);          \
-        pr_reg[4] = PT_REGS_EDI(regs);          \
-        pr_reg[5] = PT_REGS_EBP(regs);          \
-        pr_reg[6] = PT_REGS_EAX(regs);          \
-        pr_reg[7] = PT_REGS_DS(regs);           \
-        pr_reg[8] = PT_REGS_ES(regs);           \
-        /* fake once used fs and gs selectors? */       \
-        pr_reg[9] = PT_REGS_DS(regs);           \
-        pr_reg[10] = PT_REGS_DS(regs);          \
-        pr_reg[11] = PT_REGS_SYSCALL_NR(regs);  \
-        pr_reg[12] = PT_REGS_IP(regs);          \
-        pr_reg[13] = PT_REGS_CS(regs);          \
-        pr_reg[14] = PT_REGS_EFLAGS(regs);      \
-        pr_reg[15] = PT_REGS_SP(regs);          \
-        pr_reg[16] = PT_REGS_SS(regs);          \
-} while (0);
-#define task_pt_regs(t) (&(t)->thread.regs)
-struct task_struct;
-extern int elf_core_copy_fpregs(struct task_struct *t, elf_fpregset_t *fpu);
-#define ELF_CORE_COPY_FPREGS(t, fpu) elf_core_copy_fpregs(t, fpu)
-extern long elf_aux_hwcap;
-#define ELF_HWCAP (elf_aux_hwcap)
-extern char * elf_aux_platform;
-#define ELF_PLATFORM (elf_aux_platform)
-#define SET_PERSONALITY(ex) do { } while (0)
-extern unsigned long vsyscall_ehdr;
-extern unsigned long vsyscall_end;
-extern unsigned long __kernel_vsyscall;
-#define VSYSCALL_BASE vsyscall_ehdr
-#define VSYSCALL_END vsyscall_end
-/*
- * This is the range that is readable by user mode, and things
- * acting like user mode such as get_user_pages.
- */
-#define FIXADDR_USER_START      VSYSCALL_BASE
-#define FIXADDR_USER_END        VSYSCALL_END
-#define __HAVE_ARCH_GATE_AREA 1
-/*
- * Architecture-neutral AT_ values in 0-17, leave some room
- * for more of them, start the x86-specific ones at 32.
- */
-#define AT_SYSINFO              32
-#define AT_SYSINFO_EHDR         33
-#define ARCH_DLINFO                                             \
-do {                                                            \
-        if ( vsyscall_ehdr ) {                                  \
-                NEW_AUX_ENT(AT_SYSINFO, __kernel_vsyscall);     \
-                NEW_AUX_ENT(AT_SYSINFO_EHDR, vsyscall_ehdr);    \
-        }                                                       \
-} while (0)
-#endif
diff --git a/arch/um/sys-i386/asm/module.h b/arch/um/sys-i386/asm/module.h
deleted file mode 100644
index 5ead4a0b2e35..000000000000
--- a/arch/um/sys-i386/asm/module.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __UM_MODULE_I386_H
-#define __UM_MODULE_I386_H
-/* UML is simple */
-struct mod_arch_specific
-{
-};
-#define Elf_Shdr Elf32_Shdr
-#define Elf_Sym Elf32_Sym
-#define Elf_Ehdr Elf32_Ehdr
-#endif
diff --git a/arch/um/sys-i386/atomic64_cx8_32.S b/arch/um/sys-i386/atomic64_cx8_32.S
deleted file mode 100644
index 1e901d3d4a95..000000000000
--- a/arch/um/sys-i386/atomic64_cx8_32.S
+++ /dev/null
@@ -1,225 +0,0 @@
-/*
- * atomic64_t for 586+
- *
- * Copied from arch/x86/lib/atomic64_cx8_32.S
- *
- * Copyright © 2010  Luca Barbieri
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#include <linux/linkage.h>
-#include <asm/alternative-asm.h>
-#include <asm/dwarf2.h>
-.macro SAVE reg
-        pushl_cfi %\reg
-        CFI_REL_OFFSET \reg, 0
-.endm
-.macro RESTORE reg
-        popl_cfi %\reg
-        CFI_RESTORE \reg
-.endm
-.macro read64 reg
-        movl %ebx, %eax
-        movl %ecx, %edx
-/* we need LOCK_PREFIX since otherwise cmpxchg8b always does the write */
-        LOCK_PREFIX
-        cmpxchg8b (\reg)
-.endm
-ENTRY(atomic64_read_cx8)
-        CFI_STARTPROC
-        read64 %ecx
-        ret
-        CFI_ENDPROC
-ENDPROC(atomic64_read_cx8)
-ENTRY(atomic64_set_cx8)
-        CFI_STARTPROC
-1:
-/* we don't need LOCK_PREFIX since aligned 64-bit writes
- * are atomic on 586 and newer */
-        cmpxchg8b (%esi)
-        jne 1b
-        ret
-        CFI_ENDPROC
-ENDPROC(atomic64_set_cx8)
-ENTRY(atomic64_xchg_cx8)
-        CFI_STARTPROC
-        movl %ebx, %eax
-        movl %ecx, %edx
-1:
-        LOCK_PREFIX
-        cmpxchg8b (%esi)
-        jne 1b
-        ret
-        CFI_ENDPROC
-ENDPROC(atomic64_xchg_cx8)
-.macro addsub_return func ins insc
-ENTRY(atomic64_\func\()_return_cx8)
-        CFI_STARTPROC
-        SAVE ebp
-        SAVE ebx
-        SAVE esi
-        SAVE edi
-        movl %eax, %esi
-        movl %edx, %edi
-        movl %ecx, %ebp
-        read64 %ebp
-1:
-        movl %eax, %ebx
-        movl %edx, %ecx
-        \ins\()l %esi, %ebx
-        \insc\()l %edi, %ecx
-        LOCK_PREFIX
-        cmpxchg8b (%ebp)
-        jne 1b
-10:
-        movl %ebx, %eax
-        movl %ecx, %edx
-        RESTORE edi
-        RESTORE esi
-        RESTORE ebx
-        RESTORE ebp
-        ret
-        CFI_ENDPROC
-ENDPROC(atomic64_\func\()_return_cx8)
-.endm
-addsub_return add add adc
-addsub_return sub sub sbb
-.macro incdec_return func ins insc
-ENTRY(atomic64_\func\()_return_cx8)
-        CFI_STARTPROC
-        SAVE ebx
-        read64 %esi
-1:
-        movl %eax, %ebx
-        movl %edx, %ecx
-        \ins\()l $1, %ebx
-        \insc\()l $0, %ecx
-        LOCK_PREFIX
-        cmpxchg8b (%esi)
-        jne 1b
-10:
-        movl %ebx, %eax
-        movl %ecx, %edx
-        RESTORE ebx
-        ret
-        CFI_ENDPROC
-ENDPROC(atomic64_\func\()_return_cx8)
-.endm
-incdec_return inc add adc
-incdec_return dec sub sbb
-ENTRY(atomic64_dec_if_positive_cx8)
-        CFI_STARTPROC
-        SAVE ebx
-        read64 %esi
-1:
-        movl %eax, %ebx
-        movl %edx, %ecx
-        subl $1, %ebx
-        sbb $0, %ecx
-        js 2f
-        LOCK_PREFIX
-        cmpxchg8b (%esi)
-        jne 1b
-2:
-        movl %ebx, %eax
-        movl %ecx, %edx
-        RESTORE ebx
-        ret
-        CFI_ENDPROC
-ENDPROC(atomic64_dec_if_positive_cx8)
-ENTRY(atomic64_add_unless_cx8)
-        CFI_STARTPROC
-        SAVE ebp
-        SAVE ebx
-/* these just push these two parameters on the stack */
-        SAVE edi
-        SAVE esi
-        movl %ecx, %ebp
-        movl %eax, %esi
-        movl %edx, %edi
-        read64 %ebp
-1:
-        cmpl %eax, 0(%esp)
-        je 4f
-2:
-        movl %eax, %ebx
-        movl %edx, %ecx
-        addl %esi, %ebx
-        adcl %edi, %ecx
-        LOCK_PREFIX
-        cmpxchg8b (%ebp)
-        jne 1b
-        movl $1, %eax
-3:
-        addl $8, %esp
-        CFI_ADJUST_CFA_OFFSET -8
-        RESTORE ebx
-        RESTORE ebp
-        ret
-4:
-        cmpl %edx, 4(%esp)
-        jne 2b
-        xorl %eax, %eax
-        jmp 3b
-        CFI_ENDPROC
-ENDPROC(atomic64_add_unless_cx8)
-ENTRY(atomic64_inc_not_zero_cx8)
-        CFI_STARTPROC
-        SAVE ebx
-        read64 %esi
-1:
-        testl %eax, %eax
-        je 4f
-2:
-        movl %eax, %ebx
-        movl %edx, %ecx
-        addl $1, %ebx
-        adcl $0, %ecx
-        LOCK_PREFIX
-        cmpxchg8b (%esi)
-        jne 1b
-        movl $1, %eax
-3:
-        RESTORE ebx
-        ret
-4:
-        testl %edx, %edx
-        jne 2b
-        jmp 3b
-        CFI_ENDPROC
-ENDPROC(atomic64_inc_not_zero_cx8)
diff --git a/arch/um/sys-i386/bug.c b/arch/um/sys-i386/bug.c
deleted file mode 100644
index 8d4f273f1219..000000000000
--- a/arch/um/sys-i386/bug.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Copyright (C) 2006 Jeff Dike (jdike@addtoit.com)
- * Licensed under the GPL V2
- */
-#include <linux/uaccess.h>
-#include <asm/errno.h>
-/* Mostly copied from i386/x86_86 - eliminated the eip < PAGE_OFFSET because
- * that's not relevant in skas mode.
- */
-int is_valid_bugaddr(unsigned long eip)
-{
-        unsigned short ud2;
-        if (probe_kernel_address((unsigned short __user *)eip, ud2))
-                return 0;
-        return ud2 == 0x0b0f;
-}
diff --git a/arch/um/sys-i386/ksyms.c b/arch/um/sys-i386/ksyms.c
deleted file mode 100644
index bfbefd30db8f..000000000000
--- a/arch/um/sys-i386/ksyms.c
+++ /dev/null
@@ -1,5 +0,0 @@
-#include "linux/module.h"
-#include "asm/checksum.h"
-/* Networking helper routines. */
-EXPORT_SYMBOL(csum_partial);
diff --git a/arch/um/sys-i386/shared/sysdep/barrier.h b/arch/um/sys-i386/shared/sysdep/barrier.h
deleted file mode 100644
index b58d52c5b2f4..000000000000
--- a/arch/um/sys-i386/shared/sysdep/barrier.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef __SYSDEP_I386_BARRIER_H
-#define __SYSDEP_I386_BARRIER_H
-/* Copied from include/asm-i386 for use by userspace.  i386 has the option
- * of using mfence, but I'm just using this, which works everywhere, for now.
- */
-#define mb() asm volatile("lock; addl $0,0(%esp)")
-#endif
diff --git a/arch/um/sys-i386/shared/sysdep/host_ldt.h b/arch/um/sys-i386/shared/sysdep/host_ldt.h
deleted file mode 100644
index 0953cc4df652..000000000000
--- a/arch/um/sys-i386/shared/sysdep/host_ldt.h
+++ /dev/null
@@ -1,34 +0,0 @@
-#ifndef __ASM_HOST_LDT_I386_H
-#define __ASM_HOST_LDT_I386_H
-#include <asm/ldt.h>
-/*
- * macros stolen from include/asm-i386/desc.h
- */
-#define LDT_entry_a(info) \
-        ((((info)->base_addr & 0x0000ffff) << 16) | ((info)->limit & 0x0ffff))
-#define LDT_entry_b(info) \
-        (((info)->base_addr & 0xff000000) | \
-        (((info)->base_addr & 0x00ff0000) >> 16) | \
-        ((info)->limit & 0xf0000) | \
-        (((info)->read_exec_only ^ 1) << 9) | \
-        ((info)->contents << 10) | \
-        (((info)->seg_not_present ^ 1) << 15) | \
-        ((info)->seg_32bit << 22) | \
-        ((info)->limit_in_pages << 23) | \
-        ((info)->useable << 20) | \
-        0x7000)
-#define LDT_empty(info) (\
-        (info)->base_addr       == 0    && \
-        (info)->limit           == 0    && \
-        (info)->contents        == 0    && \
-        (info)->read_exec_only  == 1    && \
-        (info)->seg_32bit       == 0    && \
-        (info)->limit_in_pages  == 0    && \
-        (info)->seg_not_present == 1    && \
-        (info)->useable         == 0    )
-#endif
diff --git a/arch/um/sys-i386/shared/sysdep/ptrace_user.h b/arch/um/sys-i386/shared/sysdep/ptrace_user.h
deleted file mode 100644
index ef56247e4143..000000000000
--- a/arch/um/sys-i386/shared/sysdep/ptrace_user.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* 
- * Copyright (C) 2002 Jeff Dike (jdike@karaya.com)
- * Licensed under the GPL
- */
-#ifndef __SYSDEP_I386_PTRACE_USER_H__
-#define __SYSDEP_I386_PTRACE_USER_H__
-#include <sys/ptrace.h>
-#include <linux/ptrace.h>
-#include <asm/ptrace.h>
-#include "user_constants.h"
-#define PT_OFFSET(r) ((r) * sizeof(long))
-#define PT_SYSCALL_NR(regs) ((regs)[ORIG_EAX])
-#define PT_SYSCALL_NR_OFFSET PT_OFFSET(ORIG_EAX)
-#define PT_SYSCALL_ARG1_OFFSET PT_OFFSET(EBX)
-#define PT_SYSCALL_ARG2_OFFSET PT_OFFSET(ECX)
-#define PT_SYSCALL_ARG3_OFFSET PT_OFFSET(EDX)
-#define PT_SYSCALL_ARG4_OFFSET PT_OFFSET(ESI)
-#define PT_SYSCALL_ARG5_OFFSET PT_OFFSET(EDI)
-#define PT_SYSCALL_ARG6_OFFSET PT_OFFSET(EBP)
-#define PT_SYSCALL_RET_OFFSET PT_OFFSET(EAX)
-#define REGS_SYSCALL_NR EAX /* This is used before a system call */
-#define REGS_SYSCALL_ARG1 EBX
-#define REGS_SYSCALL_ARG2 ECX
-#define REGS_SYSCALL_ARG3 EDX
-#define REGS_SYSCALL_ARG4 ESI
-#define REGS_SYSCALL_ARG5 EDI
-#define REGS_SYSCALL_ARG6 EBP
-#define REGS_IP_INDEX EIP
-#define REGS_SP_INDEX UESP
-#define PT_IP_OFFSET PT_OFFSET(EIP)
-#define PT_IP(regs) ((regs)[EIP])
-#define PT_SP_OFFSET PT_OFFSET(UESP)
-#define PT_SP(regs) ((regs)[UESP])
-#define FP_SIZE ((HOST_FPX_SIZE > HOST_FP_SIZE) ? HOST_FPX_SIZE : HOST_FP_SIZE)
-#ifndef FRAME_SIZE
-#define FRAME_SIZE (17)
-#endif
-#endif
diff --git a/arch/um/sys-i386/shared/sysdep/sc.h b/arch/um/sys-i386/shared/sysdep/sc.h
deleted file mode 100644
index c57d1780ad37..000000000000
--- a/arch/um/sys-i386/shared/sysdep/sc.h
+++ /dev/null
@@ -1,44 +0,0 @@
-#ifndef __SYSDEP_I386_SC_H
-#define __SYSDEP_I386_SC_H
-#include <user_constants.h>
-#define SC_OFFSET(sc, field) \
-        *((unsigned long *) &(((char *) (sc))[HOST_##field]))
-#define SC_FP_OFFSET(sc, field) \
-        *((unsigned long *) &(((char *) (SC_FPSTATE(sc)))[HOST_##field]))
-#define SC_FP_OFFSET_PTR(sc, field, type) \
-        ((type *) &(((char *) (SC_FPSTATE(sc)))[HOST_##field]))
-#define SC_IP(sc) SC_OFFSET(sc, SC_IP)
-#define SC_SP(sc) SC_OFFSET(sc, SC_SP)
-#define SC_FS(sc) SC_OFFSET(sc, SC_FS)
-#define SC_GS(sc) SC_OFFSET(sc, SC_GS)
-#define SC_DS(sc) SC_OFFSET(sc, SC_DS)
-#define SC_ES(sc) SC_OFFSET(sc, SC_ES)
-#define SC_SS(sc) SC_OFFSET(sc, SC_SS)
-#define SC_CS(sc) SC_OFFSET(sc, SC_CS)
-#define SC_EFLAGS(sc) SC_OFFSET(sc, SC_EFLAGS)
-#define SC_EAX(sc) SC_OFFSET(sc, SC_EAX)
-#define SC_EBX(sc) SC_OFFSET(sc, SC_EBX)
-#define SC_ECX(sc) SC_OFFSET(sc, SC_ECX)
-#define SC_EDX(sc) SC_OFFSET(sc, SC_EDX)
-#define SC_EDI(sc) SC_OFFSET(sc, SC_EDI)
-#define SC_ESI(sc) SC_OFFSET(sc, SC_ESI)
-#define SC_EBP(sc) SC_OFFSET(sc, SC_EBP)
-#define SC_TRAPNO(sc) SC_OFFSET(sc, SC_TRAPNO)
-#define SC_ERR(sc) SC_OFFSET(sc, SC_ERR)
-#define SC_CR2(sc) SC_OFFSET(sc, SC_CR2)
-#define SC_FPSTATE(sc) SC_OFFSET(sc, SC_FPSTATE)
-#define SC_SIGMASK(sc) SC_OFFSET(sc, SC_SIGMASK)
-#define SC_FP_CW(sc) SC_FP_OFFSET(sc, SC_FP_CW)
-#define SC_FP_SW(sc) SC_FP_OFFSET(sc, SC_FP_SW)
-#define SC_FP_TAG(sc) SC_FP_OFFSET(sc, SC_FP_TAG)
-#define SC_FP_IPOFF(sc) SC_FP_OFFSET(sc, SC_FP_IPOFF)
-#define SC_FP_CSSEL(sc) SC_FP_OFFSET(sc, SC_FP_CSSEL)
-#define SC_FP_DATAOFF(sc) SC_FP_OFFSET(sc, SC_FP_DATAOFF)
-#define SC_FP_DATASEL(sc) SC_FP_OFFSET(sc, SC_FP_DATASEL)
-#define SC_FP_ST(sc) SC_FP_OFFSET_PTR(sc, SC_FP_ST, struct _fpstate)
-#define SC_FXSR_ENV(sc) SC_FP_OFFSET_PTR(sc, SC_FXSR_ENV, void)
-#endif
diff --git a/arch/um/sys-i386/shared/sysdep/sigcontext.h b/arch/um/sys-i386/shared/sysdep/sigcontext.h
deleted file mode 100644
index f583c87111a0..000000000000
--- a/arch/um/sys-i386/shared/sysdep/sigcontext.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* 
- * Copyright (C) 2000 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
- * Licensed under the GPL
- */
-#ifndef __SYS_SIGCONTEXT_I386_H
-#define __SYS_SIGCONTEXT_I386_H
-#include "sysdep/sc.h"
-#define IP_RESTART_SYSCALL(ip) ((ip) -= 2)
-#define GET_FAULTINFO_FROM_SC(fi, sc) \
-        { \
-                (fi).cr2 = SC_CR2(sc); \
-                (fi).error_code = SC_ERR(sc); \
-                (fi).trap_no = SC_TRAPNO(sc); \
-        }
-/* This is Page Fault */
-#define SEGV_IS_FIXABLE(fi)     ((fi)->trap_no == 14)
-/* SKAS3 has no trap_no on i386, but get_skas_faultinfo() sets it to 0. */
-#define SEGV_MAYBE_FIXABLE(fi)  ((fi)->trap_no == 0 && ptrace_faultinfo)
-#endif
diff --git a/arch/um/sys-i386/shared/sysdep/system.h b/arch/um/sys-i386/shared/sysdep/system.h
deleted file mode 100644
index d1b93c436200..000000000000
--- a/arch/um/sys-i386/shared/sysdep/system.h
+++ /dev/null
@@ -1,132 +0,0 @@
-#ifndef _ASM_X86_SYSTEM_H_
-#define _ASM_X86_SYSTEM_H_
-#include <asm/asm.h>
-#include <asm/segment.h>
-#include <asm/cpufeature.h>
-#include <asm/cmpxchg.h>
-#include <asm/nops.h>
-#include <linux/kernel.h>
-#include <linux/irqflags.h>
-/* entries in ARCH_DLINFO: */
-#ifdef CONFIG_IA32_EMULATION
-# define AT_VECTOR_SIZE_ARCH 2
-#else
-# define AT_VECTOR_SIZE_ARCH 1
-#endif
-extern unsigned long arch_align_stack(unsigned long sp);
-void default_idle(void);
-/*
- * Force strict CPU ordering.
- * And yes, this is required on UP too when we're talking
- * to devices.
- */
-#ifdef CONFIG_X86_32
-/*
- * Some non-Intel clones support out of order store. wmb() ceases to be a
- * nop for these.
- */
-#define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
-#define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
-#define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
-#else
-#define mb()    asm volatile("mfence":::"memory")
-#define rmb()   asm volatile("lfence":::"memory")
-#define wmb()   asm volatile("sfence" ::: "memory")
-#endif
-/**
- * read_barrier_depends - Flush all pending reads that subsequents reads
- * depend on.
- *
- * No data-dependent reads from memory-like regions are ever reordered
- * over this barrier.  All reads preceding this primitive are guaranteed
- * to access memory (but not necessarily other CPUs' caches) before any
- * reads following this primitive that depend on the data return by
- * any of the preceding reads.  This primitive is much lighter weight than
- * rmb() on most CPUs, and is never heavier weight than is
- * rmb().
- *
- * These ordering constraints are respected by both the local CPU
- * and the compiler.
- *
- * Ordering is not guaranteed by anything other than these primitives,
- * not even by data dependencies.  See the documentation for
- * memory_barrier() for examples and URLs to more information.
- *
- * For example, the following code would force ordering (the initial
- * value of "a" is zero, "b" is one, and "p" is "&a"):
- *
- * <programlisting>
- *      CPU 0                           CPU 1
- *
- *      b = 2;
- *      memory_barrier();
- *      p = &b;                         q = p;
- *                                      read_barrier_depends();
- *                                      d = *q;
- * </programlisting>
- *
- * because the read of "*q" depends on the read of "p" and these
- * two reads are separated by a read_barrier_depends().  However,
- * the following code, with the same initial values for "a" and "b":
- *
- * <programlisting>
- *      CPU 0                           CPU 1
- *
- *      a = 2;
- *      memory_barrier();
- *      b = 3;                          y = b;
- *                                      read_barrier_depends();
- *                                      x = a;
- * </programlisting>
- *
- * does not enforce ordering, since there is no data dependency between
- * the read of "a" and the read of "b".  Therefore, on some CPUs, such
- * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
- * in cases like this where there are no data dependencies.
- **/
-#define read_barrier_depends()  do { } while (0)
-#ifdef CONFIG_SMP
-#define smp_mb()        mb()
-#ifdef CONFIG_X86_PPRO_FENCE
-# define smp_rmb()      rmb()
-#else
-# define smp_rmb()      barrier()
-#endif
-#ifdef CONFIG_X86_OOSTORE
-# define smp_wmb()      wmb()
-#else
-# define smp_wmb()      barrier()
-#endif
-#define smp_read_barrier_depends()      read_barrier_depends()
-#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
-#else
-#define smp_mb()        barrier()
-#define smp_rmb()       barrier()
-#define smp_wmb()       barrier()
-#define smp_read_barrier_depends()      do { } while (0)
-#define set_mb(var, value) do { var = value; barrier(); } while (0)
-#endif
-/*
- * Stop RDTSC speculation. This is needed when you need to use RDTSC
- * (or get_cycles or vread that possibly accesses the TSC) in a defined
- * code region.
- *
- * (Could use an alternative three way for this if there was one.)
- */
-static inline void rdtsc_barrier(void)
-{
-        alternative(ASM_NOP3, "mfence", X86_FEATURE_MFENCE_RDTSC);
-        alternative(ASM_NOP3, "lfence", X86_FEATURE_LFENCE_RDTSC);
-}
-#endif
diff --git a/arch/um/sys-i386/shared/sysdep/vm-flags.h b/arch/um/sys-i386/shared/sysdep/vm-flags.h
deleted file mode 100644
index e0d24c568dbc..000000000000
--- a/arch/um/sys-i386/shared/sysdep/vm-flags.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (C) 2004 Jeff Dike (jdike@addtoit.com)
- * Licensed under the GPL
- */
-#ifndef __VM_FLAGS_I386_H
-#define __VM_FLAGS_I386_H
-#define VM_DATA_DEFAULT_FLAGS \
-        (VM_READ | VM_WRITE | \
-        ((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0 ) | \
-                 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
-#endif
diff --git a/arch/um/sys-i386/stub_segv.c b/arch/um/sys-i386/stub_segv.c
deleted file mode 100644
index 28ccf737a79f..000000000000
--- a/arch/um/sys-i386/stub_segv.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (C) 2004 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
- * Licensed under the GPL
- */
-#include "sysdep/stub.h"
-#include "sysdep/sigcontext.h"
-void __attribute__ ((__section__ (".__syscall_stub")))
-stub_segv_handler(int sig)
-{
-        struct sigcontext *sc = (struct sigcontext *) (&sig + 1);
-        GET_FAULTINFO_FROM_SC(*((struct faultinfo *) STUB_DATA), sc);
-        trap_myself();
-}
diff --git a/arch/um/sys-i386/user-offsets.c b/arch/um/sys-i386/user-offsets.c
deleted file mode 100644
index 5f883bfe773f..000000000000
--- a/arch/um/sys-i386/user-offsets.c
+++ /dev/null
@@ -1,53 +0,0 @@
-#include <stdio.h>
-#include <stddef.h>
-#include <signal.h>
-#include <sys/poll.h>
-#include <sys/user.h>
-#include <sys/mman.h>
-#include <asm/ptrace.h>
-#define DEFINE(sym, val) \
-        asm volatile("\n->" #sym " %0 " #val : : "i" (val))
-#define DEFINE_LONGS(sym, val) \
-        asm volatile("\n->" #sym " %0 " #val : : "i" (val/sizeof(unsigned long)))
-#define OFFSET(sym, str, mem) \
-        DEFINE(sym, offsetof(struct str, mem));
-void foo(void)
-{
-        OFFSET(HOST_SC_TRAPNO, sigcontext, trapno);
-        OFFSET(HOST_SC_ERR, sigcontext, err);
-        OFFSET(HOST_SC_CR2, sigcontext, cr2);
-        DEFINE_LONGS(HOST_FP_SIZE, sizeof(struct user_fpregs_struct));
-        DEFINE_LONGS(HOST_FPX_SIZE, sizeof(struct user_fpxregs_struct));
-        DEFINE(HOST_IP, EIP);
-        DEFINE(HOST_SP, UESP);
-        DEFINE(HOST_EFLAGS, EFL);
-        DEFINE(HOST_EAX, EAX);
-        DEFINE(HOST_EBX, EBX);
-        DEFINE(HOST_ECX, ECX);
-        DEFINE(HOST_EDX, EDX);
-        DEFINE(HOST_ESI, ESI);
-        DEFINE(HOST_EDI, EDI);
-        DEFINE(HOST_EBP, EBP);
-        DEFINE(HOST_CS, CS);
-        DEFINE(HOST_SS, SS);
-        DEFINE(HOST_DS, DS);
-        DEFINE(HOST_FS, FS);
-        DEFINE(HOST_ES, ES);
-        DEFINE(HOST_GS, GS);
-        DEFINE(UM_FRAME_SIZE, sizeof(struct user_regs_struct));
-        /* XXX Duplicated between i386 and x86_64 */
-        DEFINE(UM_POLLIN, POLLIN);
-        DEFINE(UM_POLLPRI, POLLPRI);
-        DEFINE(UM_POLLOUT, POLLOUT);
-        DEFINE(UM_PROT_READ, PROT_READ);
-        DEFINE(UM_PROT_WRITE, PROT_WRITE);
-        DEFINE(UM_PROT_EXEC, PROT_EXEC);
-}
diff --git a/arch/um/sys-x86_64/Makefile b/arch/um/sys-x86_64/Makefile
deleted file mode 100644
index bd4d1d3ba919..000000000000
--- a/arch/um/sys-x86_64/Makefile
+++ /dev/null
@@ -1,27 +0,0 @@
-#
-# Copyright 2003 PathScale, Inc.
-#
-# Licensed under the GPL
-#
-obj-y = bug.o bugs.o delay.o fault.o ldt.o ptrace.o ptrace_user.o mem.o \
-        setjmp.o signal.o stub.o stub_segv.o syscalls.o syscall_table.o \
-        sysrq.o ksyms.o tls.o
-obj-y += vdso/
-subarch-obj-y = lib/csum-partial_64.o lib/memcpy_64.o lib/thunk_64.o \
-                lib/rwsem.o
-subarch-obj-$(CONFIG_MODULES) += kernel/module.o
-ldt-y = ../sys-i386/ldt.o
-USER_OBJS := ptrace_user.o
-USER_OBJS += user-offsets.s
-extra-y += user-offsets.s
-UNPROFILE_OBJS := stub_segv.o
-CFLAGS_stub_segv.o := $(CFLAGS_NO_HARDENING)
-include arch/um/scripts/Makefile.rules
diff --git a/arch/um/sys-x86_64/asm/archparam.h b/arch/um/sys-x86_64/asm/archparam.h
deleted file mode 100644
index 6c083663b8d9..000000000000
--- a/arch/um/sys-x86_64/asm/archparam.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * Copyright 2003 PathScale, Inc.
- *
- * Licensed under the GPL
- */
-#ifndef __UM_ARCHPARAM_X86_64_H
-#define __UM_ARCHPARAM_X86_64_H
-/* No user-accessible fixmap addresses, i.e. vsyscall */
-#define FIXADDR_USER_START      0
-#define FIXADDR_USER_END        0
-#endif
diff --git a/arch/um/sys-x86_64/asm/module.h b/arch/um/sys-x86_64/asm/module.h
deleted file mode 100644
index 8eb79c2d07d5..000000000000
--- a/arch/um/sys-x86_64/asm/module.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Copyright 2003 PathScale, Inc.
- *
- * Licensed under the GPL
- */
-#ifndef __UM_MODULE_X86_64_H
-#define __UM_MODULE_X86_64_H
-/* UML is simple */
-struct mod_arch_specific
-{
-};
-#define Elf_Shdr Elf64_Shdr
-#define Elf_Sym Elf64_Sym
-#define Elf_Ehdr Elf64_Ehdr
-#endif
diff --git a/arch/um/sys-x86_64/delay.c b/arch/um/sys-x86_64/delay.c
deleted file mode 100644
index f3fe1a688f7e..000000000000
--- a/arch/um/sys-x86_64/delay.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright (C) 2011 Richard Weinberger <richrd@nod.at>
- * Mostly copied from arch/x86/lib/delay.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <asm/param.h>
-void __delay(unsigned long loops)
-{
-        asm volatile(
-                "test %0,%0\n"
-                "jz 3f\n"
-                "jmp 1f\n"
-                ".align 16\n"
-                "1: jmp 2f\n"
-                ".align 16\n"
-                "2: dec %0\n"
-                " jnz 2b\n"
-                "3: dec %0\n"
-                : /* we don't need output */
-                : "a" (loops)
-        );
-}
-EXPORT_SYMBOL(__delay);
-inline void __const_udelay(unsigned long xloops)
-{
-        int d0;
-        xloops *= 4;
-        asm("mull %%edx"
-                : "=d" (xloops), "=&a" (d0)
-                : "1" (xloops), "0"
-                (loops_per_jiffy * (HZ/4)));
-        __delay(++xloops);
-}
-EXPORT_SYMBOL(__const_udelay);
-void __udelay(unsigned long usecs)
-{
-        __const_udelay(usecs * 0x000010c7); /* 2**32 / 1000000 (rounded up) */
-}
-EXPORT_SYMBOL(__udelay);
-void __ndelay(unsigned long nsecs)
-{
-        __const_udelay(nsecs * 0x00005); /* 2**32 / 1000000000 (rounded up) */
-}
-EXPORT_SYMBOL(__ndelay);
diff --git a/arch/um/sys-x86_64/fault.c b/arch/um/sys-x86_64/fault.c
deleted file mode 100644
index ce85117fc64e..000000000000
--- a/arch/um/sys-x86_64/fault.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright 2003 PathScale, Inc.
- *
- * Licensed under the GPL
- */
-#include "sysdep/ptrace.h"
-/* These two are from asm-um/uaccess.h and linux/module.h, check them. */
-struct exception_table_entry
-{
-        unsigned long insn;
-        unsigned long fixup;
-};
-const struct exception_table_entry *search_exception_tables(unsigned long add);
-int arch_fixup(unsigned long address, struct uml_pt_regs *regs)
-{
-        const struct exception_table_entry *fixup;
-        fixup = search_exception_tables(address);
-        if (fixup != 0) {
-                UPT_IP(regs) = fixup->fixup;
-                return 1;
-        }
-        return 0;
-}
diff --git a/arch/um/sys-x86_64/ptrace_user.c b/arch/um/sys-x86_64/ptrace_user.c
deleted file mode 100644
index c57a496d3f5b..000000000000
--- a/arch/um/sys-x86_64/ptrace_user.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright 2003 PathScale, Inc.
- *
- * Licensed under the GPL
- */
-#include <errno.h>
-#include "ptrace_user.h"
-int ptrace_getregs(long pid, unsigned long *regs_out)
-{
-        if (ptrace(PTRACE_GETREGS, pid, 0, regs_out) < 0)
-                return -errno;
-        return(0);
-}
-int ptrace_setregs(long pid, unsigned long *regs_out)
-{
-        if (ptrace(PTRACE_SETREGS, pid, 0, regs_out) < 0)
-                return -errno;
-        return(0);
-}
diff --git a/arch/um/sys-x86_64/shared/sysdep/barrier.h b/arch/um/sys-x86_64/shared/sysdep/barrier.h
deleted file mode 100644
index 7b610befdc8f..000000000000
--- a/arch/um/sys-x86_64/shared/sysdep/barrier.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __SYSDEP_X86_64_BARRIER_H
-#define __SYSDEP_X86_64_BARRIER_H
-/* Copied from include/asm-x86_64 for use by userspace. */
-#define mb()    asm volatile("mfence":::"memory")
-#endif
diff --git a/arch/um/sys-x86_64/shared/sysdep/host_ldt.h b/arch/um/sys-x86_64/shared/sysdep/host_ldt.h
deleted file mode 100644
index e8b1be1e154f..000000000000
--- a/arch/um/sys-x86_64/shared/sysdep/host_ldt.h
+++ /dev/null
@@ -1,38 +0,0 @@
-#ifndef __ASM_HOST_LDT_X86_64_H
-#define __ASM_HOST_LDT_X86_64_H
-#include <asm/ldt.h>
-/*
- * macros stolen from include/asm-x86_64/desc.h
- */
-#define LDT_entry_a(info) \
-        ((((info)->base_addr & 0x0000ffff) << 16) | ((info)->limit & 0x0ffff))
-/* Don't allow setting of the lm bit. It is useless anyways because
- * 64bit system calls require __USER_CS. */
-#define LDT_entry_b(info) \
-        (((info)->base_addr & 0xff000000) | \
-        (((info)->base_addr & 0x00ff0000) >> 16) | \
-        ((info)->limit & 0xf0000) | \
-        (((info)->read_exec_only ^ 1) << 9) | \
-        ((info)->contents << 10) | \
-        (((info)->seg_not_present ^ 1) << 15) | \
-        ((info)->seg_32bit << 22) | \
-        ((info)->limit_in_pages << 23) | \
-        ((info)->useable << 20) | \
-        /* ((info)->lm << 21) | */ \
-        0x7000)
-#define LDT_empty(info) (\
-        (info)->base_addr       == 0    && \
-        (info)->limit           == 0    && \
-        (info)->contents        == 0    && \
-        (info)->read_exec_only  == 1    && \
-        (info)->seg_32bit       == 0    && \
-        (info)->limit_in_pages  == 0    && \
-        (info)->seg_not_present == 1    && \
-        (info)->useable         == 0    && \
-        (info)->lm              == 0)
-#endif
diff --git a/arch/um/sys-x86_64/shared/sysdep/kernel-offsets.h b/arch/um/sys-x86_64/shared/sysdep/kernel-offsets.h
deleted file mode 100644
index a307237b7964..000000000000
--- a/arch/um/sys-x86_64/shared/sysdep/kernel-offsets.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#include <linux/stddef.h>
-#include <linux/sched.h>
-#include <linux/time.h>
-#include <linux/elf.h>
-#include <linux/crypto.h>
-#include <asm/page.h>
-#include <asm/mman.h>
-#define DEFINE(sym, val) \
-        asm volatile("\n->" #sym " %0 " #val : : "i" (val))
-#define DEFINE_STR1(x) #x
-#define DEFINE_STR(sym, val) asm volatile("\n->" #sym " " DEFINE_STR1(val) " " #val: : )
-#define BLANK() asm volatile("\n->" : : )
-#define OFFSET(sym, str, mem) \
-        DEFINE(sym, offsetof(struct str, mem));
-void foo(void)
-{
-#include <common-offsets.h>
-}
diff --git a/arch/um/sys-x86_64/shared/sysdep/ptrace_user.h b/arch/um/sys-x86_64/shared/sysdep/ptrace_user.h
deleted file mode 100644
index 4dbccdb58f48..000000000000
--- a/arch/um/sys-x86_64/shared/sysdep/ptrace_user.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright 2003 PathScale, Inc.
- *
- * Licensed under the GPL
- */
-#ifndef __SYSDEP_X86_64_PTRACE_USER_H__
-#define __SYSDEP_X86_64_PTRACE_USER_H__
-#define __FRAME_OFFSETS
-#include <sys/ptrace.h>
-#include <linux/ptrace.h>
-#include <asm/ptrace.h>
-#undef __FRAME_OFFSETS
-#include "user_constants.h"
-#define PT_INDEX(off) ((off) / sizeof(unsigned long))
-#define PT_SYSCALL_NR(regs) ((regs)[PT_INDEX(ORIG_RAX)])
-#define PT_SYSCALL_NR_OFFSET (ORIG_RAX)
-#define PT_SYSCALL_ARG1(regs) (((unsigned long *) (regs))[PT_INDEX(RDI)])
-#define PT_SYSCALL_ARG1_OFFSET (RDI)
-#define PT_SYSCALL_ARG2(regs) (((unsigned long *) (regs))[PT_INDEX(RSI)])
-#define PT_SYSCALL_ARG2_OFFSET (RSI)
-#define PT_SYSCALL_ARG3(regs) (((unsigned long *) (regs))[PT_INDEX(RDX)])
-#define PT_SYSCALL_ARG3_OFFSET (RDX)
-#define PT_SYSCALL_ARG4(regs) (((unsigned long *) (regs))[PT_INDEX(RCX)])
-#define PT_SYSCALL_ARG4_OFFSET (RCX)
-#define PT_SYSCALL_ARG5(regs) (((unsigned long *) (regs))[PT_INDEX(R8)])
-#define PT_SYSCALL_ARG5_OFFSET (R8)
-#define PT_SYSCALL_ARG6(regs) (((unsigned long *) (regs))[PT_INDEX(R9)])
-#define PT_SYSCALL_ARG6_OFFSET (R9)
-#define PT_SYSCALL_RET_OFFSET (RAX)
-#define PT_IP_OFFSET (RIP)
-#define PT_IP(regs) ((regs)[PT_INDEX(RIP)])
-#define PT_SP_OFFSET (RSP)
-#define PT_SP(regs) ((regs)[PT_INDEX(RSP)])
-#define PT_ORIG_RAX_OFFSET (ORIG_RAX)
-#define PT_ORIG_RAX(regs) ((regs)[PT_INDEX(ORIG_RAX)])
-/*
- * x86_64 FC3 doesn't define this in /usr/include/linux/ptrace.h even though
- * it's defined in the kernel's include/linux/ptrace.h. Additionally, use the
- * 2.4 name and value for 2.4 host compatibility.
- */
-#ifndef PTRACE_OLDSETOPTIONS
-#define PTRACE_OLDSETOPTIONS 21
-#endif
-/*
- * These are before the system call, so the system call number is RAX
- * rather than ORIG_RAX, and arg4 is R10 rather than RCX
- */
-#define REGS_SYSCALL_NR PT_INDEX(RAX)
-#define REGS_SYSCALL_ARG1 PT_INDEX(RDI)
-#define REGS_SYSCALL_ARG2 PT_INDEX(RSI)
-#define REGS_SYSCALL_ARG3 PT_INDEX(RDX)
-#define REGS_SYSCALL_ARG4 PT_INDEX(R10)
-#define REGS_SYSCALL_ARG5 PT_INDEX(R8)
-#define REGS_SYSCALL_ARG6 PT_INDEX(R9)
-#define REGS_IP_INDEX PT_INDEX(RIP)
-#define REGS_SP_INDEX PT_INDEX(RSP)
-#define FP_SIZE (HOST_FP_SIZE)
-#endif
diff --git a/arch/um/sys-x86_64/shared/sysdep/sc.h b/arch/um/sys-x86_64/shared/sysdep/sc.h
deleted file mode 100644
index 8aee45b07434..000000000000
--- a/arch/um/sys-x86_64/shared/sysdep/sc.h
+++ /dev/null
@@ -1,45 +0,0 @@
-#ifndef __SYSDEP_X86_64_SC_H
-#define __SYSDEP_X86_64_SC_H
-/* Copyright (C) 2003 - 2004 PathScale, Inc
- * Released under the GPL
- */
-#include <user_constants.h>
-#define SC_OFFSET(sc, field) \
-         *((unsigned long *) &(((char *) (sc))[HOST_##field]))
-#define SC_RBX(sc) SC_OFFSET(sc, SC_RBX)
-#define SC_RCX(sc) SC_OFFSET(sc, SC_RCX)
-#define SC_RDX(sc) SC_OFFSET(sc, SC_RDX)
-#define SC_RSI(sc) SC_OFFSET(sc, SC_RSI)
-#define SC_RDI(sc) SC_OFFSET(sc, SC_RDI)
-#define SC_RBP(sc) SC_OFFSET(sc, SC_RBP)
-#define SC_RAX(sc) SC_OFFSET(sc, SC_RAX)
-#define SC_R8(sc) SC_OFFSET(sc, SC_R8)
-#define SC_R9(sc) SC_OFFSET(sc, SC_R9)
-#define SC_R10(sc) SC_OFFSET(sc, SC_R10)
-#define SC_R11(sc) SC_OFFSET(sc, SC_R11)
-#define SC_R12(sc) SC_OFFSET(sc, SC_R12)
-#define SC_R13(sc) SC_OFFSET(sc, SC_R13)
-#define SC_R14(sc) SC_OFFSET(sc, SC_R14)
-#define SC_R15(sc) SC_OFFSET(sc, SC_R15)
-#define SC_IP(sc) SC_OFFSET(sc, SC_IP)
-#define SC_SP(sc) SC_OFFSET(sc, SC_SP)
-#define SC_CR2(sc) SC_OFFSET(sc, SC_CR2)
-#define SC_ERR(sc) SC_OFFSET(sc, SC_ERR)
-#define SC_TRAPNO(sc) SC_OFFSET(sc, SC_TRAPNO)
-#define SC_CS(sc) SC_OFFSET(sc, SC_CS)
-#define SC_FS(sc) SC_OFFSET(sc, SC_FS)
-#define SC_GS(sc) SC_OFFSET(sc, SC_GS)
-#define SC_EFLAGS(sc) SC_OFFSET(sc, SC_EFLAGS)
-#define SC_SIGMASK(sc) SC_OFFSET(sc, SC_SIGMASK)
-#define SC_SS(sc) SC_OFFSET(sc, SC_SS)
-#if 0
-#define SC_ORIG_RAX(sc) SC_OFFSET(sc, SC_ORIG_RAX)
-#define SC_DS(sc) SC_OFFSET(sc, SC_DS)
-#define SC_ES(sc) SC_OFFSET(sc, SC_ES)
-#endif
-#endif
diff --git a/arch/um/sys-x86_64/shared/sysdep/sigcontext.h b/arch/um/sys-x86_64/shared/sysdep/sigcontext.h
deleted file mode 100644
index 0155133b1458..000000000000
--- a/arch/um/sys-x86_64/shared/sysdep/sigcontext.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright 2003 PathScale, Inc.
- *
- * Licensed under the GPL
- */
-#ifndef __SYSDEP_X86_64_SIGCONTEXT_H
-#define __SYSDEP_X86_64_SIGCONTEXT_H
-#include <sysdep/sc.h>
-#define IP_RESTART_SYSCALL(ip) ((ip) -= 2)
-#define GET_FAULTINFO_FROM_SC(fi, sc) \
-        { \
-                (fi).cr2 = SC_CR2(sc); \
-                (fi).error_code = SC_ERR(sc); \
-                (fi).trap_no = SC_TRAPNO(sc); \
-        }
-/* This is Page Fault */
-#define SEGV_IS_FIXABLE(fi)     ((fi)->trap_no == 14)
-/* No broken SKAS API, which doesn't pass trap_no, here. */
-#define SEGV_MAYBE_FIXABLE(fi)  0
-#endif
diff --git a/arch/um/sys-x86_64/shared/sysdep/skas_ptrace.h b/arch/um/sys-x86_64/shared/sysdep/skas_ptrace.h
deleted file mode 100644
index 95db4be786e4..000000000000
--- a/arch/um/sys-x86_64/shared/sysdep/skas_ptrace.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (C) 2000, 2001, 2002 Jeff Dike (jdike@karaya.com)
- * Licensed under the GPL
- */
-#ifndef __SYSDEP_X86_64_SKAS_PTRACE_H
-#define __SYSDEP_X86_64_SKAS_PTRACE_H
-struct ptrace_faultinfo {
-        int is_write;
-        unsigned long addr;
-};
-struct ptrace_ldt {
-        int func;
-        void *ptr;
-        unsigned long bytecount;
-};
-#define PTRACE_LDT 54
-#endif
diff --git a/arch/um/sys-x86_64/shared/sysdep/tls.h b/arch/um/sys-x86_64/shared/sysdep/tls.h
deleted file mode 100644
index 18c000d0357a..000000000000
--- a/arch/um/sys-x86_64/shared/sysdep/tls.h
+++ /dev/null
@@ -1,29 +0,0 @@
-#ifndef _SYSDEP_TLS_H
-#define _SYSDEP_TLS_H
-# ifndef __KERNEL__
-/* Change name to avoid conflicts with the original one from <asm/ldt.h>, which
- * may be named user_desc (but in 2.4 and in header matching its API was named
- * modify_ldt_ldt_s). */
-typedef struct um_dup_user_desc {
-        unsigned int  entry_number;
-        unsigned int  base_addr;
-        unsigned int  limit;
-        unsigned int  seg_32bit:1;
-        unsigned int  contents:2;
-        unsigned int  read_exec_only:1;
-        unsigned int  limit_in_pages:1;
-        unsigned int  seg_not_present:1;
-        unsigned int  useable:1;
-        unsigned int  lm:1;
-} user_desc_t;
-# else /* __KERNEL__ */
-#  include <ldt.h>
-typedef struct user_desc user_desc_t;
-# endif /* __KERNEL__ */
-#endif /* _SYSDEP_TLS_H */
diff --git a/arch/um/sys-x86_64/signal.c b/arch/um/sys-x86_64/signal.c
deleted file mode 100644
index b6b65c7c7a7d..000000000000
--- a/arch/um/sys-x86_64/signal.c
+++ /dev/null
@@ -1,290 +0,0 @@
-/*
- * Copyright (C) 2003 PathScale, Inc.
- * Copyright (C) 2003 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
- * Licensed under the GPL
- */
-#include <linux/personality.h>
-#include <linux/ptrace.h>
-#include <linux/kernel.h>
-#include <asm/unistd.h>
-#include <asm/uaccess.h>
-#include <asm/ucontext.h>
-#include "frame_kern.h"
-#include "skas.h"
-void copy_sc(struct uml_pt_regs *regs, void *from)
-{
-        struct sigcontext *sc = from;
-#define GETREG(regs, regno, sc, regname)                                \
-        (regs)->gp[(regno) / sizeof(unsigned long)] = (sc)->regname
-        GETREG(regs, R8, sc, r8);
-        GETREG(regs, R9, sc, r9);
-        GETREG(regs, R10, sc, r10);
-        GETREG(regs, R11, sc, r11);
-        GETREG(regs, R12, sc, r12);
-        GETREG(regs, R13, sc, r13);
-        GETREG(regs, R14, sc, r14);
-        GETREG(regs, R15, sc, r15);
-        GETREG(regs, RDI, sc, di);
-        GETREG(regs, RSI, sc, si);
-        GETREG(regs, RBP, sc, bp);
-        GETREG(regs, RBX, sc, bx);
-        GETREG(regs, RDX, sc, dx);
-        GETREG(regs, RAX, sc, ax);
-        GETREG(regs, RCX, sc, cx);
-        GETREG(regs, RSP, sc, sp);
-        GETREG(regs, RIP, sc, ip);
-        GETREG(regs, EFLAGS, sc, flags);
-        GETREG(regs, CS, sc, cs);
-#undef GETREG
-}
-static int copy_sc_from_user(struct pt_regs *regs,
-                             struct sigcontext __user *from,
-                             struct _fpstate __user *fpp)
-{
-        struct user_i387_struct fp;
-        int err = 0;
-#define GETREG(regs, regno, sc, regname)                                \
-        __get_user((regs)->regs.gp[(regno) / sizeof(unsigned long)],    \
-                   &(sc)->regname)
-        err |= GETREG(regs, R8, from, r8);
-        err |= GETREG(regs, R9, from, r9);
-        err |= GETREG(regs, R10, from, r10);
-        err |= GETREG(regs, R11, from, r11);
-        err |= GETREG(regs, R12, from, r12);
-        err |= GETREG(regs, R13, from, r13);
-        err |= GETREG(regs, R14, from, r14);
-        err |= GETREG(regs, R15, from, r15);
-        err |= GETREG(regs, RDI, from, di);
-        err |= GETREG(regs, RSI, from, si);
-        err |= GETREG(regs, RBP, from, bp);
-        err |= GETREG(regs, RBX, from, bx);
-        err |= GETREG(regs, RDX, from, dx);
-        err |= GETREG(regs, RAX, from, ax);
-        err |= GETREG(regs, RCX, from, cx);
-        err |= GETREG(regs, RSP, from, sp);
-        err |= GETREG(regs, RIP, from, ip);
-        err |= GETREG(regs, EFLAGS, from, flags);
-        err |= GETREG(regs, CS, from, cs);
-        if (err)
-                return 1;
-#undef GETREG
-        err = copy_from_user(&fp, fpp, sizeof(struct user_i387_struct));
-        if (err)
-                return 1;
-        err = restore_fp_registers(userspace_pid[current_thread_info()->cpu],
-                                   (unsigned long *) &fp);
-        if (err < 0) {
-                printk(KERN_ERR "copy_sc_from_user - "
-                       "restore_fp_registers failed, errno = %d\n",
-                       -err);
-                return 1;
-        }
-        return 0;
-}
-static int copy_sc_to_user(struct sigcontext __user *to,
-                           struct _fpstate __user *to_fp, struct pt_regs *regs,
-                           unsigned long mask, unsigned long sp)
-{
-        struct faultinfo * fi = &current->thread.arch.faultinfo;
-        struct user_i387_struct fp;
-        int err = 0;
-        err |= __put_user(0, &to->gs);
-        err |= __put_user(0, &to->fs);
-#define PUTREG(regs, regno, sc, regname)                                \
-        __put_user((regs)->regs.gp[(regno) / sizeof(unsigned long)],    \
-                   &(sc)->regname)
-        err |= PUTREG(regs, RDI, to, di);
-        err |= PUTREG(regs, RSI, to, si);
-        err |= PUTREG(regs, RBP, to, bp);
-        /*
-         * Must use original RSP, which is passed in, rather than what's in
-         * the pt_regs, because that's already been updated to point at the
-         * signal frame.
-         */
-        err |= __put_user(sp, &to->sp);
-        err |= PUTREG(regs, RBX, to, bx);
-        err |= PUTREG(regs, RDX, to, dx);
-        err |= PUTREG(regs, RCX, to, cx);
-        err |= PUTREG(regs, RAX, to, ax);
-        err |= PUTREG(regs, R8, to, r8);
-        err |= PUTREG(regs, R9, to, r9);
-        err |= PUTREG(regs, R10, to, r10);
-        err |= PUTREG(regs, R11, to, r11);
-        err |= PUTREG(regs, R12, to, r12);
-        err |= PUTREG(regs, R13, to, r13);
-        err |= PUTREG(regs, R14, to, r14);
-        err |= PUTREG(regs, R15, to, r15);
-        err |= PUTREG(regs, CS, to, cs); /* XXX x86_64 doesn't do this */
-        err |= __put_user(fi->cr2, &to->cr2);
-        err |= __put_user(fi->error_code, &to->err);
-        err |= __put_user(fi->trap_no, &to->trapno);
-        err |= PUTREG(regs, RIP, to, ip);
-        err |= PUTREG(regs, EFLAGS, to, flags);
-#undef PUTREG
-        err |= __put_user(mask, &to->oldmask);
-        if (err)
-                return 1;
-        err = save_fp_registers(userspace_pid[current_thread_info()->cpu],
-                                (unsigned long *) &fp);
-        if (err < 0) {
-                printk(KERN_ERR "copy_sc_from_user - restore_fp_registers "
-                       "failed, errno = %d\n", -err);
-                return 1;
-        }
-        if (copy_to_user(to_fp, &fp, sizeof(struct user_i387_struct)))
-                return 1;
-        return err;
-}
-struct rt_sigframe
-{
-        char __user *pretcode;
-        struct ucontext uc;
-        struct siginfo info;
-        struct _fpstate fpstate;
-};
-int setup_signal_stack_si(unsigned long stack_top, int sig,
-                          struct k_sigaction *ka, struct pt_regs * regs,
-                          siginfo_t *info, sigset_t *set)
-{
-        struct rt_sigframe __user *frame;
-        unsigned long save_sp = PT_REGS_RSP(regs);
-        int err = 0;
-        struct task_struct *me = current;
-        frame = (struct rt_sigframe __user *)
-                round_down(stack_top - sizeof(struct rt_sigframe), 16);
-        /* Subtract 128 for a red zone and 8 for proper alignment */
-        frame = (struct rt_sigframe __user *) ((unsigned long) frame - 128 - 8);
-        if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
-                goto out;
-        if (ka->sa.sa_flags & SA_SIGINFO) {
-                err |= copy_siginfo_to_user(&frame->info, info);
-                if (err)
-                        goto out;
-        }
-        /*
-         * Update SP now because the page fault handler refuses to extend
-         * the stack if the faulting address is too far below the current
-         * SP, which frame now certainly is.  If there's an error, the original
-         * value is restored on the way out.
-         * When writing the sigcontext to the stack, we have to write the
-         * original value, so that's passed to copy_sc_to_user, which does
-         * the right thing with it.
-         */
-        PT_REGS_RSP(regs) = (unsigned long) frame;
-        /* Create the ucontext.  */
-        err |= __put_user(0, &frame->uc.uc_flags);
-        err |= __put_user(0, &frame->uc.uc_link);
-        err |= __put_user(me->sas_ss_sp, &frame->uc.uc_stack.ss_sp);
-        err |= __put_user(sas_ss_flags(save_sp),
-                          &frame->uc.uc_stack.ss_flags);
-        err |= __put_user(me->sas_ss_size, &frame->uc.uc_stack.ss_size);
-        err |= copy_sc_to_user(&frame->uc.uc_mcontext, &frame->fpstate, regs,
-                               set->sig[0], save_sp);
-        err |= __put_user(&frame->fpstate, &frame->uc.uc_mcontext.fpstate);
-        if (sizeof(*set) == 16) {
-                __put_user(set->sig[0], &frame->uc.uc_sigmask.sig[0]);
-                __put_user(set->sig[1], &frame->uc.uc_sigmask.sig[1]);
-        }
-        else
-                err |= __copy_to_user(&frame->uc.uc_sigmask, set,
-                                      sizeof(*set));
-        /*
-         * Set up to return from userspace.  If provided, use a stub
-         * already in userspace.
-         */
-        /* x86-64 should always use SA_RESTORER. */
-        if (ka->sa.sa_flags & SA_RESTORER)
-                err |= __put_user(ka->sa.sa_restorer, &frame->pretcode);
-        else
-                /* could use a vstub here */
-                goto restore_sp;
-        if (err)
-                goto restore_sp;
-        /* Set up registers for signal handler */
-        {
-                struct exec_domain *ed = current_thread_info()->exec_domain;
-                if (unlikely(ed && ed->signal_invmap && sig < 32))
-                        sig = ed->signal_invmap[sig];
-        }
-        PT_REGS_RDI(regs) = sig;
-        /* In case the signal handler was declared without prototypes */
-        PT_REGS_RAX(regs) = 0;
-        /*
-         * This also works for non SA_SIGINFO handlers because they expect the
-         * next argument after the signal number on the stack.
-         */
-        PT_REGS_RSI(regs) = (unsigned long) &frame->info;
-        PT_REGS_RDX(regs) = (unsigned long) &frame->uc;
-        PT_REGS_RIP(regs) = (unsigned long) ka->sa.sa_handler;
- out:
-        return err;
-restore_sp:
-        PT_REGS_RSP(regs) = save_sp;
-        return err;
-}
-long sys_rt_sigreturn(struct pt_regs *regs)
-{
-        unsigned long sp = PT_REGS_SP(&current->thread.regs);
-        struct rt_sigframe __user *frame =
-                (struct rt_sigframe __user *)(sp - 8);
-        struct ucontext __user *uc = &frame->uc;
-        sigset_t set;
-        if (copy_from_user(&set, &uc->uc_sigmask, sizeof(set)))
-                goto segfault;
-        sigdelsetmask(&set, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
-        current->blocked = set;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
-        if (copy_sc_from_user(&current->thread.regs, &uc->uc_mcontext,
-                              &frame->fpstate))
-                goto segfault;
-        /* Avoid ERESTART handling */
-        PT_REGS_SYSCALL_NR(&current->thread.regs) = -1;
-        return PT_REGS_SYSCALL_RET(&current->thread.regs);
- segfault:
-        force_sig(SIGSEGV, current);
-        return 0;
-}
diff --git a/arch/um/Makefile-i386 b/arch/x86/Makefile.um
index 302cbe504543..36ddec6a41c9 100644
--- a/arch/um/Makefile-i386
+++ b/arch/x86/Makefile.um
@@ -1,14 +1,11 @@
-core-y += arch/um/sys-i386/ arch/x86/crypto/
+core-y += arch/x86/crypto/
-TOP_ADDR := $(CONFIG_TOP_ADDR)
+ifeq ($(CONFIG_X86_32),y)
 START := 0x8048000
 LDFLAGS                 += -m elf_i386
-ELF_ARCH                := $(SUBARCH)
+ELF_ARCH                := i386
-ELF_FORMAT              := elf32-$(SUBARCH)
+ELF_FORMAT              := elf32-i386
-OBJCOPYFLAGS            := -O binary -R .note -R .comment -S
-HEADER_ARCH             := x86
 CHECKFLAGS      += -D__i386__
 ifeq ("$(origin SUBARCH)", "command line")
@@ -16,9 +13,8 @@ ifneq ("$(shell uname -m | sed -e s/i.86/i386/)", "$(SUBARCH)")
 KBUILD_CFLAGS           += $(call cc-option,-m32)
 KBUILD_AFLAGS           += $(call cc-option,-m32)
 LINK-y                  += $(call cc-option,-m32)
-UML_OBJCOPYFLAGS        += -F $(ELF_FORMAT)
-export LDFLAGS HOSTCFLAGS HOSTLDFLAGS UML_OBJCOPYFLAGS
+export LDFLAGS
 endif
 endif
@@ -40,3 +36,26 @@ KBUILD_CFLAGS += $(shell if [ $(call cc-version) -lt 0400 ] ; then \
                        else echo $(call cc-option,-funit-at-a-time); fi ;)
 KBUILD_CFLAGS += $(cflags-y)
+else
+START := 0x60000000
+KBUILD_CFLAGS += -fno-builtin -m64 
+CHECKFLAGS  += -m64 -D__x86_64__
+KBUILD_AFLAGS += -m64
+LDFLAGS += -m elf_x86_64
+KBUILD_CPPFLAGS += -m64
+ELF_ARCH := i386:x86-64
+ELF_FORMAT := elf64-x86-64
+# Not on all 64-bit distros /lib is a symlink to /lib64. PLD is an example.
+LINK-$(CONFIG_LD_SCRIPT_DYN) += -Wl,-rpath,/lib64
+LINK-y += -m64
+# Do unit-at-a-time unconditionally on x86_64, following the host
+KBUILD_CFLAGS += $(call cc-option,-funit-at-a-time)
+endif
diff --git a/arch/um/Kconfig.x86 b/arch/x86/um/Kconfig
index 21bebe63df66..21bebe63df66 100644
--- a/arch/um/Kconfig.x86
+++ b/arch/x86/um/Kconfig
diff --git a/arch/x86/um/Makefile b/arch/x86/um/Makefile
new file mode 100644
index 000000000000..8fb58400e415
--- /dev/null
+++ b/arch/x86/um/Makefile
@@ -0,0 +1,45 @@
+#
+# Copyright (C) 2002 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
+#
+ifeq ($(CONFIG_X86_32),y)
+        BITS := 32
+else
+        BITS := 64
+endif
+obj-y = bug.o bugs_$(BITS).o delay.o fault.o ksyms.o ldt.o \
+        ptrace_$(BITS).o ptrace_user.o setjmp_$(BITS).o signal.o \
+        stub_$(BITS).o stub_segv.o syscalls_$(BITS).o \
+        sys_call_table_$(BITS).o sysrq_$(BITS).o tls_$(BITS).o \
+        mem_$(BITS).o subarch.o os-$(OS)/
+ifeq ($(CONFIG_X86_32),y)
+obj-y += checksum_32.o
+obj-$(CONFIG_BINFMT_ELF) += elfcore.o
+subarch-y = ../lib/string_32.o ../lib/atomic64_32.o ../lib/atomic64_cx8_32.o
+subarch-$(CONFIG_RWSEM_XCHGADD_ALGORITHM) += ../lib/rwsem.o
+subarch-$(CONFIG_HIGHMEM) += ../mm/highmem_32.o
+else
+obj-y += vdso/
+subarch-y = ../lib/csum-partial_64.o ../lib/memcpy_64.o ../lib/thunk_64.o \
+                ../lib/rwsem.o
+endif
+subarch-$(CONFIG_MODULES) += ../kernel/module.o
+USER_OBJS := bugs_$(BITS).o ptrace_user.o fault.o
+extra-y += user-offsets.s
+$(obj)/user-offsets.s: c_flags = -Wp,-MD,$(depfile) $(USER_CFLAGS)
+UNPROFILE_OBJS := stub_segv.o
+CFLAGS_stub_segv.o := $(CFLAGS_NO_HARDENING)
+include arch/um/scripts/Makefile.rules
diff --git a/arch/um/include/asm/apic.h b/arch/x86/um/asm/apic.h
index 876dee84ab11..876dee84ab11 100644
--- a/arch/um/include/asm/apic.h
+++ b/arch/x86/um/asm/apic.h
diff --git a/arch/um/include/asm/arch_hweight.h b/arch/x86/um/asm/arch_hweight.h
index c656cf443f4a..c656cf443f4a 100644
--- a/arch/um/include/asm/arch_hweight.h
+++ b/arch/x86/um/asm/arch_hweight.h
diff --git a/arch/um/sys-i386/asm/archparam.h b/arch/x86/um/asm/archparam.h
index 2a18a884ca1b..c17cf68dda0f 100644
--- a/arch/um/sys-i386/asm/archparam.h
+++ b/arch/x86/um/asm/archparam.h
@@ -1,10 +1,13 @@
 /* 
 * Copyright (C) 2000 - 2003 Jeff Dike (jdike@addtoit.com)
+ * Copyright 2003 PathScale, Inc.
 * Licensed under the GPL
 */
-#ifndef __UM_ARCHPARAM_I386_H
+#ifndef __UM_ARCHPARAM_H
-#define __UM_ARCHPARAM_I386_H
+#define __UM_ARCHPARAM_H
+#ifdef CONFIG_X86_32
 #ifdef CONFIG_X86_PAE
 #define LAST_PKMAP 512
@@ -14,3 +17,4 @@
 #endif
+#endif
diff --git a/arch/x86/um/asm/checksum.h b/arch/x86/um/asm/checksum.h
new file mode 100644
index 000000000000..b6efe2381b5d
--- /dev/null
+++ b/arch/x86/um/asm/checksum.h
@@ -0,0 +1,10 @@
+#ifndef __UM_CHECKSUM_H
+#define __UM_CHECKSUM_H
+#ifdef CONFIG_X86_32
+# include "checksum_32.h"
+#else
+# include "checksum_64.h"
+#endif
+#endif
diff --git a/arch/um/sys-i386/shared/sysdep/checksum.h b/arch/x86/um/asm/checksum_32.h
index ed47445f3905..caab74252e27 100644
--- a/arch/um/sys-i386/shared/sysdep/checksum.h
+++ b/arch/x86/um/asm/checksum_32.h
@@ -1,4 +1,4 @@
-/* 
+/*
 * Licensed under the GPL
 */
diff --git a/arch/um/sys-x86_64/shared/sysdep/checksum.h b/arch/x86/um/asm/checksum_64.h
index a5be9031ea85..a5be9031ea85 100644
--- a/arch/um/sys-x86_64/shared/sysdep/checksum.h
+++ b/arch/x86/um/asm/checksum_64.h
diff --git a/arch/um/include/asm/desc.h b/arch/x86/um/asm/desc.h
index 4ec34a51b62c..4ec34a51b62c 100644
--- a/arch/um/include/asm/desc.h
+++ b/arch/x86/um/asm/desc.h
diff --git a/arch/um/sys-x86_64/asm/elf.h b/arch/x86/um/asm/elf.h
index 11a2bfb38859..f3b0633b69a1 100644
--- a/arch/um/sys-x86_64/asm/elf.h
+++ b/arch/x86/um/asm/elf.h
@@ -1,15 +1,103 @@
 /*
- * Copyright 2003 PathScale, Inc.
+ * Copyright (C) 2000 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
- * Copyright (C) 2003 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
- *
 * Licensed under the GPL
 */
-#ifndef __UM_ELF_X86_64_H
+#ifndef __UM_ELF_X86_H
-#define __UM_ELF_X86_64_H
+#define __UM_ELF_X86_H
 #include <asm/user.h>
 #include "skas.h"
+#ifdef CONFIG_X86_32
+#define R_386_NONE      0
+#define R_386_32        1
+#define R_386_PC32      2
+#define R_386_GOT32     3
+#define R_386_PLT32     4
+#define R_386_COPY      5
+#define R_386_GLOB_DAT  6
+#define R_386_JMP_SLOT  7
+#define R_386_RELATIVE  8
+#define R_386_GOTOFF    9
+#define R_386_GOTPC     10
+#define R_386_NUM       11
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch(x) \
+        (((x)->e_machine == EM_386) || ((x)->e_machine == EM_486))
+#define ELF_CLASS       ELFCLASS32
+#define ELF_DATA        ELFDATA2LSB
+#define ELF_ARCH        EM_386
+#define ELF_PLAT_INIT(regs, load_addr) do { \
+        PT_REGS_EBX(regs) = 0; \
+        PT_REGS_ECX(regs) = 0; \
+        PT_REGS_EDX(regs) = 0; \
+        PT_REGS_ESI(regs) = 0; \
+        PT_REGS_EDI(regs) = 0; \
+        PT_REGS_EBP(regs) = 0; \
+        PT_REGS_EAX(regs) = 0; \
+} while (0)
+/* Shamelessly stolen from include/asm-i386/elf.h */
+#define ELF_CORE_COPY_REGS(pr_reg, regs) do {   \
+        pr_reg[0] = PT_REGS_EBX(regs);          \
+        pr_reg[1] = PT_REGS_ECX(regs);          \
+        pr_reg[2] = PT_REGS_EDX(regs);          \
+        pr_reg[3] = PT_REGS_ESI(regs);          \
+        pr_reg[4] = PT_REGS_EDI(regs);          \
+        pr_reg[5] = PT_REGS_EBP(regs);          \
+        pr_reg[6] = PT_REGS_EAX(regs);          \
+        pr_reg[7] = PT_REGS_DS(regs);           \
+        pr_reg[8] = PT_REGS_ES(regs);           \
+        /* fake once used fs and gs selectors? */       \
+        pr_reg[9] = PT_REGS_DS(regs);           \
+        pr_reg[10] = PT_REGS_DS(regs);          \
+        pr_reg[11] = PT_REGS_SYSCALL_NR(regs);  \
+        pr_reg[12] = PT_REGS_IP(regs);          \
+        pr_reg[13] = PT_REGS_CS(regs);          \
+        pr_reg[14] = PT_REGS_EFLAGS(regs);      \
+        pr_reg[15] = PT_REGS_SP(regs);          \
+        pr_reg[16] = PT_REGS_SS(regs);          \
+} while (0);
+extern char * elf_aux_platform;
+#define ELF_PLATFORM (elf_aux_platform)
+extern unsigned long vsyscall_ehdr;
+extern unsigned long vsyscall_end;
+extern unsigned long __kernel_vsyscall;
+/*
+ * This is the range that is readable by user mode, and things
+ * acting like user mode such as get_user_pages.
+ */
+#define FIXADDR_USER_START      vsyscall_ehdr
+#define FIXADDR_USER_END        vsyscall_end
+/*
+ * Architecture-neutral AT_ values in 0-17, leave some room
+ * for more of them, start the x86-specific ones at 32.
+ */
+#define AT_SYSINFO              32
+#define AT_SYSINFO_EHDR         33
+#define ARCH_DLINFO                                             \
+do {                                                            \
+        if ( vsyscall_ehdr ) {                                  \
+                NEW_AUX_ENT(AT_SYSINFO, __kernel_vsyscall);     \
+                NEW_AUX_ENT(AT_SYSINFO_EHDR, vsyscall_ehdr);    \
+        }                                                       \
+} while (0)
+#else
 /* x86-64 relocation types, taken from asm-x86_64/elf.h */
 #define R_X86_64_NONE           0       /* No reloc */
 #define R_X86_64_64             1       /* Direct 64 bit  */
@@ -31,13 +119,6 @@
 #define R_X86_64_NUM            16
-typedef unsigned long elf_greg_t;
-#define ELF_NGREG (sizeof (struct user_regs_struct) / sizeof(elf_greg_t))
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-typedef struct user_i387_struct elf_fpregset_t;
 /*
 * This is used to ensure we don't load something for the wrong architecture.
 */
@@ -95,6 +176,30 @@ typedef struct user_i387_struct elf_fpregset_t;
        (pr_reg)[25] = 0;                                       \
        (pr_reg)[26] = 0;
+#define ELF_PLATFORM "x86_64"
+/* No user-accessible fixmap addresses, i.e. vsyscall */
+#define FIXADDR_USER_START      0
+#define FIXADDR_USER_END        0
+#define ARCH_HAS_SETUP_ADDITIONAL_PAGES 1
+struct linux_binprm;
+extern int arch_setup_additional_pages(struct linux_binprm *bprm,
+        int uses_interp);
+extern unsigned long um_vdso_addr;
+#define AT_SYSINFO_EHDR 33
+#define ARCH_DLINFO     NEW_AUX_ENT(AT_SYSINFO_EHDR, um_vdso_addr)
+#endif
+typedef unsigned long elf_greg_t;
+#define ELF_NGREG (sizeof (struct user_regs_struct) / sizeof(elf_greg_t))
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];
+typedef struct user_i387_struct elf_fpregset_t;
 #define task_pt_regs(t) (&(t)->thread.regs)
 struct task_struct;
@@ -103,11 +208,6 @@ extern int elf_core_copy_fpregs(struct task_struct *t, elf_fpregset_t *fpu);
 #define ELF_CORE_COPY_FPREGS(t, fpu) elf_core_copy_fpregs(t, fpu)
-#ifdef TIF_IA32 /* XXX */
-#error XXX, indeed
-        clear_thread_flag(TIF_IA32);
-#endif
 #define ELF_EXEC_PAGESIZE 4096
 #define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3)
@@ -115,18 +215,7 @@ extern int elf_core_copy_fpregs(struct task_struct *t, elf_fpregset_t *fpu);
 extern long elf_aux_hwcap;
 #define ELF_HWCAP (elf_aux_hwcap)
-#define ELF_PLATFORM "x86_64"
 #define SET_PERSONALITY(ex) do ; while(0)
 #define __HAVE_ARCH_GATE_AREA 1
-#define ARCH_HAS_SETUP_ADDITIONAL_PAGES 1
-struct linux_binprm;
-extern int arch_setup_additional_pages(struct linux_binprm *bprm,
-        int uses_interp);
-extern unsigned long um_vdso_addr;
-#define AT_SYSINFO_EHDR 33
-#define ARCH_DLINFO     NEW_AUX_ENT(AT_SYSINFO_EHDR, um_vdso_addr)
 #endif
diff --git a/arch/um/include/asm/irq_vectors.h b/arch/x86/um/asm/irq_vectors.h
index 272a81e0ce14..272a81e0ce14 100644
--- a/arch/um/include/asm/irq_vectors.h
+++ b/arch/x86/um/asm/irq_vectors.h
diff --git a/arch/x86/um/asm/mm_context.h b/arch/x86/um/asm/mm_context.h
new file mode 100644
index 000000000000..4a73d63e4760
--- /dev/null
+++ b/arch/x86/um/asm/mm_context.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2004 Fujitsu Siemens Computers GmbH
+ * Licensed under the GPL
+ *
+ * Author: Bodo Stroesser <bstroesser@fujitsu-siemens.com>
+ */
+#ifndef __ASM_LDT_H
+#define __ASM_LDT_H
+#include <linux/mutex.h>
+#include <asm/ldt.h>
+extern void ldt_host_info(void);
+#define LDT_PAGES_MAX \
+        ((LDT_ENTRIES * LDT_ENTRY_SIZE)/PAGE_SIZE)
+#define LDT_ENTRIES_PER_PAGE \
+        (PAGE_SIZE/LDT_ENTRY_SIZE)
+#define LDT_DIRECT_ENTRIES \
+        ((LDT_PAGES_MAX*sizeof(void *))/LDT_ENTRY_SIZE)
+struct ldt_entry {
+        __u32 a;
+        __u32 b;
+};
+typedef struct uml_ldt {
+        int entry_count;
+        struct mutex lock;
+        union {
+                struct ldt_entry * pages[LDT_PAGES_MAX];
+                struct ldt_entry entries[LDT_DIRECT_ENTRIES];
+        } u;
+} uml_ldt_t;
+#define LDT_entry_a(info) \
+        ((((info)->base_addr & 0x0000ffff) << 16) | ((info)->limit & 0x0ffff))
+#define LDT_entry_b(info) \
+        (((info)->base_addr & 0xff000000) | \
+        (((info)->base_addr & 0x00ff0000) >> 16) | \
+        ((info)->limit & 0xf0000) | \
+        (((info)->read_exec_only ^ 1) << 9) | \
+        ((info)->contents << 10) | \
+        (((info)->seg_not_present ^ 1) << 15) | \
+        ((info)->seg_32bit << 22) | \
+        ((info)->limit_in_pages << 23) | \
+        ((info)->useable << 20) | \
+        0x7000)
+#define _LDT_empty(info) (\
+        (info)->base_addr       == 0    && \
+        (info)->limit           == 0    && \
+        (info)->contents        == 0    && \
+        (info)->read_exec_only  == 1    && \
+        (info)->seg_32bit       == 0    && \
+        (info)->limit_in_pages  == 0    && \
+        (info)->seg_not_present == 1    && \
+        (info)->useable         == 0    )
+#ifdef CONFIG_X86_64
+#define LDT_empty(info) (_LDT_empty(info) && ((info)->lm == 0))
+#else
+#define LDT_empty(info) (_LDT_empty(info))
+#endif
+struct uml_arch_mm_context {
+        uml_ldt_t ldt;
+};
+#endif
diff --git a/arch/x86/um/asm/module.h b/arch/x86/um/asm/module.h
new file mode 100644
index 000000000000..61af80e932eb
--- /dev/null
+++ b/arch/x86/um/asm/module.h
@@ -0,0 +1,23 @@
+#ifndef __UM_MODULE_H
+#define __UM_MODULE_H
+/* UML is simple */
+struct mod_arch_specific
+{
+};
+#ifdef CONFIG_X86_32
+#define Elf_Shdr Elf32_Shdr
+#define Elf_Sym Elf32_Sym
+#define Elf_Ehdr Elf32_Ehdr
+#else
+#define Elf_Shdr Elf64_Shdr
+#define Elf_Sym Elf64_Sym
+#define Elf_Ehdr Elf64_Ehdr
+#endif
+#endif
diff --git a/arch/x86/um/asm/processor.h b/arch/x86/um/asm/processor.h
new file mode 100644
index 000000000000..118c143a9cb4
--- /dev/null
+++ b/arch/x86/um/asm/processor.h
@@ -0,0 +1,22 @@
+#ifndef __UM_PROCESSOR_H
+#define __UM_PROCESSOR_H
+/* include faultinfo structure */
+#include <sysdep/faultinfo.h>
+#ifdef CONFIG_X86_32
+# include "processor_32.h"
+#else
+# include "processor_64.h"
+#endif
+#define KSTK_EIP(tsk) KSTK_REG(tsk, HOST_IP)
+#define KSTK_ESP(tsk) KSTK_REG(tsk, HOST_IP)
+#define KSTK_EBP(tsk) KSTK_REG(tsk, HOST_BP)
+#define ARCH_IS_STACKGROW(address) \
+       (address + 65536 + 32 * sizeof(unsigned long) >= UPT_SP(&current->thread.regs.regs))
+#include <asm/processor-generic.h>
+#endif
diff --git a/arch/um/sys-i386/asm/processor.h b/arch/x86/um/asm/processor_32.h
index 82a9061ab5be..018f732704dd 100644
--- a/arch/um/sys-i386/asm/processor.h
+++ b/arch/x86/um/asm/processor_32.h
@@ -6,15 +6,12 @@
 #ifndef __UM_PROCESSOR_I386_H
 #define __UM_PROCESSOR_I386_H
-#include "linux/string.h"
+#include <linux/string.h>
-#include <sysdep/host_ldt.h>
+#include <asm/segment.h>
-#include "asm/segment.h"
+#include <asm/ldt.h>
 extern int host_has_cmov;
-/* include faultinfo structure */
-#include "sysdep/faultinfo.h"
 struct uml_tls_struct {
        struct user_desc tls;
        unsigned flushed:1;
@@ -66,13 +63,4 @@ static inline void rep_nop(void)
 #define current_text_addr() \
        ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
-#define ARCH_IS_STACKGROW(address) \
-       (address + 32 >= UPT_SP(&current->thread.regs.regs))
-#define KSTK_EIP(tsk) KSTK_REG(tsk, EIP)
-#define KSTK_ESP(tsk) KSTK_REG(tsk, UESP)
-#define KSTK_EBP(tsk) KSTK_REG(tsk, EBP)
-#include "asm/processor-generic.h"
 #endif
diff --git a/arch/um/sys-x86_64/asm/processor.h b/arch/x86/um/asm/processor_64.h
index 875a26a62614..61de92d916c3 100644
--- a/arch/um/sys-x86_64/asm/processor.h
+++ b/arch/x86/um/asm/processor_64.h
@@ -7,9 +7,6 @@
 #ifndef __UM_PROCESSOR_X86_64_H
 #define __UM_PROCESSOR_X86_64_H
-/* include faultinfo structure */
-#include "sysdep/faultinfo.h"
 struct arch_thread {
        unsigned long debugregs[8];
        int debugregs_seq;
@@ -45,12 +42,4 @@ static inline void arch_copy_thread(struct arch_thread *from,
 #define current_text_addr() \
        ({ void *pc; __asm__("movq $1f,%0\n1:":"=g" (pc)); pc; })
-#define ARCH_IS_STACKGROW(address) \
-        (address + 128 >= UPT_SP(&current->thread.regs.regs))
-#define KSTK_EIP(tsk) KSTK_REG(tsk, RIP)
-#define KSTK_ESP(tsk) KSTK_REG(tsk, RSP)
-#include "asm/processor-generic.h"
 #endif
diff --git a/arch/x86/um/asm/ptrace.h b/arch/x86/um/asm/ptrace.h
new file mode 100644
index 000000000000..c8aca8c501b0
--- /dev/null
+++ b/arch/x86/um/asm/ptrace.h
@@ -0,0 +1,5 @@
+#ifdef CONFIG_X86_32
+# include "ptrace_32.h"
+#else
+# include "ptrace_64.h"
+#endif
diff --git a/arch/um/sys-i386/asm/ptrace.h b/arch/x86/um/asm/ptrace_32.h
index 5d2a59112537..5d2a59112537 100644
--- a/arch/um/sys-i386/asm/ptrace.h
+++ b/arch/x86/um/asm/ptrace_32.h
diff --git a/arch/um/sys-x86_64/asm/ptrace.h b/arch/x86/um/asm/ptrace_64.h
index 83d8c473b905..706a0d80545c 100644
--- a/arch/um/sys-x86_64/asm/ptrace.h
+++ b/arch/x86/um/asm/ptrace_64.h
@@ -40,7 +40,7 @@
 #define PT_REGS_ORIG_RAX(r) UPT_ORIG_RAX(&(r)->regs)
 #define PT_REGS_RIP(r) UPT_IP(&(r)->regs)
-#define PT_REGS_RSP(r) UPT_SP(&(r)->regs)
+#define PT_REGS_SP(r) UPT_SP(&(r)->regs)
 #define PT_REGS_EFLAGS(r) UPT_EFLAGS(&(r)->regs)
diff --git a/arch/um/include/asm/required-features.h b/arch/x86/um/asm/required-features.h
index dfb967b2d2f3..dfb967b2d2f3 100644
--- a/arch/um/include/asm/required-features.h
+++ b/arch/x86/um/asm/required-features.h
diff --git a/arch/um/include/asm/segment.h b/arch/x86/um/asm/segment.h
index 45183fcd10b6..45183fcd10b6 100644
--- a/arch/um/include/asm/segment.h
+++ b/arch/x86/um/asm/segment.h
diff --git a/arch/um/sys-x86_64/shared/sysdep/system.h b/arch/x86/um/asm/system.h
index d1b93c436200..a459fd9b7598 100644
--- a/arch/um/sys-x86_64/shared/sysdep/system.h
+++ b/arch/x86/um/asm/system.h
@@ -129,4 +129,7 @@ static inline void rdtsc_barrier(void)
        alternative(ASM_NOP3, "lfence", X86_FEATURE_LFENCE_RDTSC);
 }
+extern void *_switch_to(void *prev, void *next, void *last);
+#define switch_to(prev, next, last) prev = _switch_to(prev, next, last)
 #endif
diff --git a/arch/um/sys-x86_64/shared/sysdep/vm-flags.h b/arch/x86/um/asm/vm-flags.h
index 3978e55132d2..7c297e9e2413 100644
--- a/arch/um/sys-x86_64/shared/sysdep/vm-flags.h
+++ b/arch/x86/um/asm/vm-flags.h
@@ -4,8 +4,17 @@
 * Licensed under the GPL
 */
-#ifndef __VM_FLAGS_X86_64_H
+#ifndef __VM_FLAGS_X86_H
-#define __VM_FLAGS_X86_64_H
+#define __VM_FLAGS_X86_H
+#ifdef CONFIG_X86_32
+#define VM_DATA_DEFAULT_FLAGS \
+        (VM_READ | VM_WRITE | \
+        ((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0 ) | \
+                 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
+#else
 #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
        VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
@@ -13,3 +22,4 @@
        VM_EXEC | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
 #endif
+#endif
diff --git a/arch/um/sys-x86_64/bug.c b/arch/x86/um/bug.c
index e8034e363d83..e8034e363d83 100644
--- a/arch/um/sys-x86_64/bug.c
+++ b/arch/x86/um/bug.c
diff --git a/arch/um/sys-i386/bugs.c b/arch/x86/um/bugs_32.c
index 2c6d0d731c12..a1fba5fb9dbe 100644
--- a/arch/um/sys-i386/bugs.c
+++ b/arch/x86/um/bugs_32.c
@@ -4,17 +4,17 @@
 */
 #include <signal.h>
-#include "kern_constants.h"
 #include "kern_util.h"
 #include "longjmp.h"
-#include "task.h"
-#include "user.h"
 #include "sysdep/ptrace.h"
+#include <generated/asm-offsets.h>
 /* Set during early boot */
 static int host_has_cmov = 1;
 static jmp_buf cmov_test_return;
+#define TASK_PID(task) *((int *) &(((char *) (task))[HOST_TASK_PID]))
 static void cmov_sigill_test_handler(int sig)
 {
        host_has_cmov = 0;
diff --git a/arch/um/sys-x86_64/bugs.c b/arch/x86/um/bugs_64.c
index 44e02ba2a265..44e02ba2a265 100644
--- a/arch/um/sys-x86_64/bugs.c
+++ b/arch/x86/um/bugs_64.c
diff --git a/arch/um/sys-i386/checksum.S b/arch/x86/um/checksum_32.S
index f058d2f82e18..f058d2f82e18 100644
--- a/arch/um/sys-i386/checksum.S
+++ b/arch/x86/um/checksum_32.S
diff --git a/arch/um/sys-i386/delay.c b/arch/x86/um/delay.c
index f3fe1a688f7e..f3fe1a688f7e 100644
--- a/arch/um/sys-i386/delay.c
+++ b/arch/x86/um/delay.c
diff --git a/arch/um/sys-i386/elfcore.c b/arch/x86/um/elfcore.c
index 6bb49b687c97..6bb49b687c97 100644
--- a/arch/um/sys-i386/elfcore.c
+++ b/arch/x86/um/elfcore.c
diff --git a/arch/um/sys-i386/fault.c b/arch/x86/um/fault.c
index d670f68532f4..d670f68532f4 100644
--- a/arch/um/sys-i386/fault.c
+++ b/arch/x86/um/fault.c
diff --git a/arch/um/sys-x86_64/ksyms.c b/arch/x86/um/ksyms.c
index 1db2fce00948..2e8f43ec6214 100644
--- a/arch/um/sys-x86_64/ksyms.c
+++ b/arch/x86/um/ksyms.c
@@ -2,10 +2,12 @@
 #include <asm/string.h>
 #include <asm/checksum.h>
+#ifndef CONFIG_X86_32
 /*XXX: we need them because they would be exported by x86_64 */
 #if (__GNUC__ == 4 && __GNUC_MINOR__ >= 3) || __GNUC__ > 4
 EXPORT_SYMBOL(memcpy);
 #else
 EXPORT_SYMBOL(__memcpy);
 #endif
+#endif
 EXPORT_SYMBOL(csum_partial);
diff --git a/arch/um/sys-i386/ldt.c b/arch/x86/um/ldt.c
index 3f2bf208d884..26b0e39d2ce9 100644
--- a/arch/um/sys-i386/ldt.c
+++ b/arch/x86/um/ldt.c
@@ -137,7 +137,7 @@ static int read_ldt(void __user * ptr, unsigned long bytecount)
 {
        int i, err = 0;
        unsigned long size;
-        uml_ldt_t * ldt = &current->mm->context.ldt;
+        uml_ldt_t *ldt = &current->mm->context.arch.ldt;
        if (!ldt->entry_count)
                goto out;
@@ -205,7 +205,7 @@ static int read_default_ldt(void __user * ptr, unsigned long bytecount)
 static int write_ldt(void __user * ptr, unsigned long bytecount, int func)
 {
-        uml_ldt_t * ldt = &current->mm->context.ldt;
+        uml_ldt_t *ldt = &current->mm->context.arch.ldt;
        struct mm_id * mm_idp = &current->mm->context.id;
        int i, err;
        struct user_desc ldt_info;
@@ -397,7 +397,7 @@ long init_new_ldt(struct mm_context *new_mm, struct mm_context *from_mm)
        if (!ptrace_ldt)
-                mutex_init(&new_mm->ldt.lock);
+                mutex_init(&new_mm->arch.ldt.lock);
        if (!from_mm) {
                memset(&desc, 0, sizeof(desc));
@@ -429,7 +429,7 @@ long init_new_ldt(struct mm_context *new_mm, struct mm_context *from_mm)
                                        break;
                        }
                }
-                new_mm->ldt.entry_count = 0;
+                new_mm->arch.ldt.entry_count = 0;
                goto out;
        }
@@ -457,26 +457,26 @@ long init_new_ldt(struct mm_context *new_mm, struct mm_context *from_mm)
                 * i.e., we have to use the stub for modify_ldt, which
                 * can't handle the big read buffer of up to 64kB.
                 */
-                mutex_lock(&from_mm->ldt.lock);
+                mutex_lock(&from_mm->arch.ldt.lock);
-                if (from_mm->ldt.entry_count <= LDT_DIRECT_ENTRIES)
+                if (from_mm->arch.ldt.entry_count <= LDT_DIRECT_ENTRIES)
-                        memcpy(new_mm->ldt.u.entries, from_mm->ldt.u.entries,
+                        memcpy(new_mm->arch.ldt.u.entries, from_mm->arch.ldt.u.entries,
-                               sizeof(new_mm->ldt.u.entries));
+                               sizeof(new_mm->arch.ldt.u.entries));
                else {
-                        i = from_mm->ldt.entry_count / LDT_ENTRIES_PER_PAGE;
+                        i = from_mm->arch.ldt.entry_count / LDT_ENTRIES_PER_PAGE;
                        while (i-->0) {
                                page = __get_free_page(GFP_KERNEL|__GFP_ZERO);
                                if (!page) {
                                        err = -ENOMEM;
                                        break;
                                }
-                                new_mm->ldt.u.pages[i] =
+                                new_mm->arch.ldt.u.pages[i] =
                                        (struct ldt_entry *) page;
-                                memcpy(new_mm->ldt.u.pages[i],
+                                memcpy(new_mm->arch.ldt.u.pages[i],
-                                       from_mm->ldt.u.pages[i], PAGE_SIZE);
+                                       from_mm->arch.ldt.u.pages[i], PAGE_SIZE);
                        }
                }
-                new_mm->ldt.entry_count = from_mm->ldt.entry_count;
+                new_mm->arch.ldt.entry_count = from_mm->arch.ldt.entry_count;
-                mutex_unlock(&from_mm->ldt.lock);
+                mutex_unlock(&from_mm->arch.ldt.lock);
        }
    out:
@@ -488,12 +488,12 @@ void free_ldt(struct mm_context *mm)
 {
        int i;
-        if (!ptrace_ldt && mm->ldt.entry_count > LDT_DIRECT_ENTRIES) {
+        if (!ptrace_ldt && mm->arch.ldt.entry_count > LDT_DIRECT_ENTRIES) {
-                i = mm->ldt.entry_count / LDT_ENTRIES_PER_PAGE;
+                i = mm->arch.ldt.entry_count / LDT_ENTRIES_PER_PAGE;
                while (i-- > 0)
-                        free_page((long) mm->ldt.u.pages[i]);
+                        free_page((long) mm->arch.ldt.u.pages[i]);
        }
-        mm->ldt.entry_count = 0;
+        mm->arch.ldt.entry_count = 0;
 }
 int sys_modify_ldt(int func, void __user *ptr, unsigned long bytecount)
diff --git a/arch/um/sys-i386/mem.c b/arch/x86/um/mem_32.c
index 639900a6fde9..639900a6fde9 100644
--- a/arch/um/sys-i386/mem.c
+++ b/arch/x86/um/mem_32.c
diff --git a/arch/um/sys-x86_64/mem.c b/arch/x86/um/mem_64.c
index 546518727a73..546518727a73 100644
--- a/arch/um/sys-x86_64/mem.c
+++ b/arch/x86/um/mem_64.c
diff --git a/arch/um/os-Linux/sys-i386/Makefile b/arch/x86/um/os-Linux/Makefile
index b4bc6ac4f30b..253bfb8cb702 100644
--- a/arch/um/os-Linux/sys-i386/Makefile
+++ b/arch/x86/um/os-Linux/Makefile
@@ -3,7 +3,10 @@
 # Licensed under the GPL
 #
-obj-y = registers.o signal.o task_size.o tls.o
+obj-y = registers.o task_size.o mcontext.o
+obj-$(CONFIG_X86_32) += tls.o
+obj-$(CONFIG_64BIT) += prctl.o
 USER_OBJS := $(obj-y)
diff --git a/arch/x86/um/os-Linux/mcontext.c b/arch/x86/um/os-Linux/mcontext.c
new file mode 100644
index 000000000000..1d33d72c6284
--- /dev/null
+++ b/arch/x86/um/os-Linux/mcontext.c
@@ -0,0 +1,31 @@
+#include <sys/ucontext.h>
+#define __FRAME_OFFSETS
+#include <asm/ptrace.h>
+#include <sysdep/ptrace.h>
+void get_regs_from_mc(struct uml_pt_regs *regs, mcontext_t *mc)
+{
+#ifdef __i386__
+#define COPY2(X,Y) regs->gp[X] = mc->gregs[REG_##Y]
+#define COPY(X) regs->gp[X] = mc->gregs[REG_##X]
+#define COPY_SEG(X) regs->gp[X] = mc->gregs[REG_##X] & 0xffff;
+#define COPY_SEG_CPL3(X) regs->gp[X] = (mc->gregs[REG_##X] & 0xffff) | 3;
+        COPY_SEG(GS); COPY_SEG(FS); COPY_SEG(ES); COPY_SEG(DS);
+        COPY(EDI); COPY(ESI); COPY(EBP);
+        COPY2(UESP, ESP); /* sic */
+        COPY(EBX); COPY(EDX); COPY(ECX); COPY(EAX);
+        COPY(EIP); COPY_SEG_CPL3(CS); COPY(EFL); COPY_SEG_CPL3(SS);
+#else
+#define COPY2(X,Y) regs->gp[X/sizeof(unsigned long)] = mc->gregs[REG_##Y]
+#define COPY(X) regs->gp[X/sizeof(unsigned long)] = mc->gregs[REG_##X]
+        COPY(R8); COPY(R9); COPY(R10); COPY(R11);
+        COPY(R12); COPY(R13); COPY(R14); COPY(R15);
+        COPY(RDI); COPY(RSI); COPY(RBP); COPY(RBX);
+        COPY(RDX); COPY(RAX); COPY(RCX); COPY(RSP);
+        COPY(RIP);
+        COPY2(EFLAGS, EFL);
+        COPY2(CS, CSGSFS);
+        regs->gp[CS / sizeof(unsigned long)] &= 0xffff;
+        regs->gp[CS / sizeof(unsigned long)] |= 3;
+#endif
+}
diff --git a/arch/um/os-Linux/sys-x86_64/prctl.c b/arch/x86/um/os-Linux/prctl.c
index 9d34eddb517f..9d34eddb517f 100644
--- a/arch/um/os-Linux/sys-x86_64/prctl.c
+++ b/arch/x86/um/os-Linux/prctl.c
diff --git a/arch/um/os-Linux/sys-i386/registers.c b/arch/x86/um/os-Linux/registers.c
index 229f7a53d8da..0cdbb86b012b 100644
--- a/arch/um/os-Linux/sys-i386/registers.c
+++ b/arch/x86/um/os-Linux/registers.c
@@ -6,10 +6,10 @@
 #include <errno.h>
 #include <sys/ptrace.h>
+#ifdef __i386__
 #include <sys/user.h>
-#include "kern_constants.h"
+#endif
 #include "longjmp.h"
-#include "user.h"
 #include "sysdep/ptrace_user.h"
 int save_fp_registers(int pid, unsigned long *fp_regs)
@@ -26,6 +26,8 @@ int restore_fp_registers(int pid, unsigned long *fp_regs)
        return 0;
 }
+#ifdef __i386__
+int have_fpx_regs = 1;
 int save_fpx_registers(int pid, unsigned long *fp_regs)
 {
        if (ptrace(PTRACE_GETFPXREGS, pid, 0, fp_regs) < 0)
@@ -40,24 +42,6 @@ int restore_fpx_registers(int pid, unsigned long *fp_regs)
        return 0;
 }
-unsigned long get_thread_reg(int reg, jmp_buf *buf)
-{
-        switch (reg) {
-        case EIP:
-                return buf[0]->__eip;
-        case UESP:
-                return buf[0]->__esp;
-        case EBP:
-                return buf[0]->__ebp;
-        default:
-                printk(UM_KERN_ERR "get_thread_regs - unknown register %d\n",
-                       reg);
-                return 0;
-        }
-}
-int have_fpx_regs = 1;
 int get_fp_registers(int pid, unsigned long *regs)
 {
        if (have_fpx_regs)
@@ -89,3 +73,41 @@ void arch_init_registers(int pid)
        have_fpx_regs = 0;
 }
+#else
+int get_fp_registers(int pid, unsigned long *regs)
+{
+        return save_fp_registers(pid, regs);
+}
+int put_fp_registers(int pid, unsigned long *regs)
+{
+        return restore_fp_registers(pid, regs);
+}
+#endif
+unsigned long get_thread_reg(int reg, jmp_buf *buf)
+{
+        switch (reg) {
+#ifdef __i386__
+        case HOST_IP:
+                return buf[0]->__eip;
+        case HOST_SP:
+                return buf[0]->__esp;
+        case HOST_BP:
+                return buf[0]->__ebp;
+#else
+        case HOST_IP:
+                return buf[0]->__rip;
+        case HOST_SP:
+                return buf[0]->__rsp;
+        case HOST_BP:
+                return buf[0]->__rbp;
+#endif
+        default:
+                printk(UM_KERN_ERR "get_thread_regs - unknown register %d\n",
+                       reg);
+                return 0;
+        }
+}
diff --git a/arch/um/os-Linux/sys-i386/task_size.c b/arch/x86/um/os-Linux/task_size.c
index be04c1e183bf..efb16c5c9bcf 100644
--- a/arch/um/os-Linux/sys-i386/task_size.c
+++ b/arch/x86/um/os-Linux/task_size.c
@@ -3,7 +3,8 @@
 #include <signal.h>
 #include <sys/mman.h>
 #include "longjmp.h"
-#include "kern_constants.h"
+#ifdef __i386__
 static jmp_buf buf;
@@ -137,3 +138,13 @@ out:
        return top;
 }
+#else
+unsigned long os_get_top_address(void)
+{
+        /* The old value of CONFIG_TOP_ADDR */
+        return 0x7fc0000000;
+}
+#endif
diff --git a/arch/um/os-Linux/sys-i386/tls.c b/arch/x86/um/os-Linux/tls.c
index 32ed41ec1a3d..82276b6071af 100644
--- a/arch/um/os-Linux/sys-i386/tls.c
+++ b/arch/x86/um/os-Linux/tls.c
@@ -1,16 +1,25 @@
 #include <errno.h>
 #include <linux/unistd.h>
+#include <sys/ptrace.h>
 #include <sys/syscall.h>
 #include <unistd.h>
 #include "sysdep/tls.h"
-#include "user.h"
+#ifndef PTRACE_GET_THREAD_AREA
+#define PTRACE_GET_THREAD_AREA 25
+#endif
+#ifndef PTRACE_SET_THREAD_AREA
+#define PTRACE_SET_THREAD_AREA 26
+#endif
 /* Checks whether host supports TLS, and sets *tls_min according to the value
 * valid on the host.
 * i386 host have it == 6; x86_64 host have it == 12, for i386 emulation. */
-void check_host_supports_tls(int *supports_tls, int *tls_min) {
+void check_host_supports_tls(int *supports_tls, int *tls_min)
+{
        /* Values for x86 and x86_64.*/
        int val[] = {GDT_ENTRY_TLS_MIN_I386, GDT_ENTRY_TLS_MIN_X86_64};
        int i;
@@ -34,3 +43,25 @@ void check_host_supports_tls(int *supports_tls, int *tls_min) {
        *supports_tls = 0;
 }
+int os_set_thread_area(user_desc_t *info, int pid)
+{
+        int ret;
+        ret = ptrace(PTRACE_SET_THREAD_AREA, pid, info->entry_number,
+                     (unsigned long) info);
+        if (ret < 0)
+                ret = -errno;
+        return ret;
+}
+int os_get_thread_area(user_desc_t *info, int pid)
+{
+        int ret;
+        ret = ptrace(PTRACE_GET_THREAD_AREA, pid, info->entry_number,
+                     (unsigned long) info);
+        if (ret < 0)
+                ret = -errno;
+        return ret;
+}
diff --git a/arch/um/sys-i386/ptrace.c b/arch/x86/um/ptrace_32.c
index 3375c2717851..3b949daa095c 100644
--- a/arch/um/sys-i386/ptrace.c
+++ b/arch/x86/um/ptrace_32.c
@@ -50,20 +50,47 @@ int is_syscall(unsigned long addr)
 /* 1 = access 0 = no access */
 #define FLAG_MASK 0x00044dd5
+static const int reg_offsets[] = {
+        [EBX] = HOST_BX,
+        [ECX] = HOST_CX,
+        [EDX] = HOST_DX,
+        [ESI] = HOST_SI,
+        [EDI] = HOST_DI,
+        [EBP] = HOST_BP,
+        [EAX] = HOST_AX,
+        [DS] = HOST_DS,
+        [ES] = HOST_ES,
+        [FS] = HOST_FS,
+        [GS] = HOST_GS,
+        [EIP] = HOST_IP,
+        [CS] = HOST_CS,
+        [EFL] = HOST_EFLAGS,
+        [UESP] = HOST_SP,
+        [SS] = HOST_SS,
+};
 int putreg(struct task_struct *child, int regno, unsigned long value)
 {
        regno >>= 2;
        switch (regno) {
+        case EBX:
+        case ECX:
+        case EDX:
+        case ESI:
+        case EDI:
+        case EBP:
+        case EAX:
+        case EIP:
+        case UESP:
+                break;
        case FS:
                if (value && (value & 3) != 3)
                        return -EIO;
-                PT_REGS_FS(&child->thread.regs) = value;
+                break;
-                return 0;
        case GS:
                if (value && (value & 3) != 3)
                        return -EIO;
-                PT_REGS_GS(&child->thread.regs) = value;
+                break;
-                return 0;
        case DS:
        case ES:
                if (value && (value & 3) != 3)
@@ -78,10 +105,15 @@ int putreg(struct task_struct *child, int regno, unsigned long value)
                break;
        case EFL:
                value &= FLAG_MASK;
-                value |= PT_REGS_EFLAGS(&child->thread.regs);
+                child->thread.regs.regs.gp[HOST_EFLAGS] |= value;
-                break;
+                return 0;
+        case ORIG_EAX:
+                child->thread.regs.regs.syscall = value;
+                return 0;
+        default :
+                panic("Bad register in putreg() : %d\n", regno);
        }
-        PT_REGS_SET(&child->thread.regs, regno, value);
+        child->thread.regs.regs.gp[reg_offsets[regno]] = value;
        return 0;
 }
@@ -106,22 +138,35 @@ int poke_user(struct task_struct *child, long addr, long data)
 unsigned long getreg(struct task_struct *child, int regno)
 {
-        unsigned long retval = ~0UL;
+        unsigned long mask = ~0UL;
        regno >>= 2;
        switch (regno) {
+        case ORIG_EAX:
+                return child->thread.regs.regs.syscall;
        case FS:
        case GS:
        case DS:
        case ES:
        case SS:
        case CS:
-                retval = 0xffff;
+                mask = 0xffff;
-                /* fall through */
+                break;
+        case EIP:
+        case UESP:
+        case EAX:
+        case EBX:
+        case ECX:
+        case EDX:
+        case ESI:
+        case EDI:
+        case EBP:
+        case EFL:
+                break;
        default:
-                retval &= PT_REG(&child->thread.regs, regno);
+                panic("Bad register in getreg() : %d\n", regno);
        }
-        return retval;
+        return mask & child->thread.regs.regs.gp[reg_offsets[regno]];
 }
 /* read the word at location addr in the USER area. */
diff --git a/arch/um/sys-x86_64/ptrace.c b/arch/x86/um/ptrace_64.c
index 4005506834fd..3b52bf0b418a 100644
--- a/arch/um/sys-x86_64/ptrace.c
+++ b/arch/x86/um/ptrace_64.c
@@ -18,10 +18,39 @@
 */
 #define FLAG_MASK 0x44dd5UL
-int putreg(struct task_struct *child, int regno, unsigned long value)
+static const int reg_offsets[] =
 {
-        unsigned long tmp;
+        [R8 >> 3] = HOST_R8,
+        [R9 >> 3] = HOST_R9,
+        [R10 >> 3] = HOST_R10,
+        [R11 >> 3] = HOST_R11,
+        [R12 >> 3] = HOST_R12,
+        [R13 >> 3] = HOST_R13,
+        [R14 >> 3] = HOST_R14,
+        [R15 >> 3] = HOST_R15,
+        [RIP >> 3] = HOST_IP,
+        [RSP >> 3] = HOST_SP,
+        [RAX >> 3] = HOST_AX,
+        [RBX >> 3] = HOST_BX,
+        [RCX >> 3] = HOST_CX,
+        [RDX >> 3] = HOST_DX,
+        [RSI >> 3] = HOST_SI,
+        [RDI >> 3] = HOST_DI,
+        [RBP >> 3] = HOST_BP,
+        [CS >> 3] = HOST_CS,
+        [SS >> 3] = HOST_SS,
+        [FS_BASE >> 3] = HOST_FS_BASE,
+        [GS_BASE >> 3] = HOST_GS_BASE,
+        [DS >> 3] = HOST_DS,
+        [ES >> 3] = HOST_ES,
+        [FS >> 3] = HOST_FS,
+        [GS >> 3] = HOST_GS,
+        [EFLAGS >> 3] = HOST_EFLAGS,
+        [ORIG_RAX >> 3] = HOST_ORIG_AX,
+};
+int putreg(struct task_struct *child, int regno, unsigned long value)
+{
 #ifdef TIF_IA32
        /*
         * Some code in the 64bit emulation may not be 64bit clean.
@@ -31,6 +60,26 @@ int putreg(struct task_struct *child, int regno, unsigned long value)
                value &= 0xffffffff;
 #endif
        switch (regno) {
+        case R8:
+        case R9:
+        case R10:
+        case R11:
+        case R12:
+        case R13:
+        case R14:
+        case R15:
+        case RIP:
+        case RSP:
+        case RAX:
+        case RBX:
+        case RCX:
+        case RDX:
+        case RSI:
+        case RDI:
+        case RBP:
+        case ORIG_RAX:
+                break;
        case FS:
        case GS:
        case DS:
@@ -50,12 +99,14 @@ int putreg(struct task_struct *child, int regno, unsigned long value)
        case EFLAGS:
                value &= FLAG_MASK;
-                tmp = PT_REGS_EFLAGS(&child->thread.regs) & ~FLAG_MASK;
+                child->thread.regs.regs.gp[HOST_EFLAGS] |= value;
-                value |= tmp;
+                return 0;
-                break;
+        default:
+                panic("Bad register in putreg(): %d\n", regno);
        }
-        PT_REGS_SET(&child->thread.regs, regno, value);
+        child->thread.regs.regs.gp[reg_offsets[regno >> 3]] = value;
        return 0;
 }
@@ -80,24 +131,46 @@ int poke_user(struct task_struct *child, long addr, long data)
 unsigned long getreg(struct task_struct *child, int regno)
 {
-        unsigned long retval = ~0UL;
+        unsigned long mask = ~0UL;
+#ifdef TIF_IA32
+        if (test_tsk_thread_flag(child, TIF_IA32))
+                mask = 0xffffffff;
+#endif
        switch (regno) {
+        case R8:
+        case R9:
+        case R10:
+        case R11:
+        case R12:
+        case R13:
+        case R14:
+        case R15:
+        case RIP:
+        case RSP:
+        case RAX:
+        case RBX:
+        case RCX:
+        case RDX:
+        case RSI:
+        case RDI:
+        case RBP:
+        case ORIG_RAX:
+        case EFLAGS:
+        case FS_BASE:
+        case GS_BASE:
+                break;
        case FS:
        case GS:
        case DS:
        case ES:
        case SS:
        case CS:
-                retval = 0xffff;
+                mask = 0xffff;
-                /* fall through */
+                break;
        default:
-                retval &= PT_REG(&child->thread.regs, regno);
+                panic("Bad register in getreg: %d\n", regno);
-#ifdef TIF_IA32
-                if (test_tsk_thread_flag(child, TIF_IA32))
-                        retval &= 0xffffffff;
-#endif
        }
-        return retval;
+        return mask & child->thread.regs.regs.gp[reg_offsets[regno >> 3]];
 }
 int peek_user(struct task_struct *child, long addr, long data)
diff --git a/arch/um/sys-i386/ptrace_user.c b/arch/x86/um/ptrace_user.c
index 0b10c3e74028..3960ca1dd35a 100644
--- a/arch/um/sys-i386/ptrace_user.c
+++ b/arch/x86/um/ptrace_user.c
@@ -4,7 +4,7 @@
 */
 #include <errno.h>
-#include <sys/ptrace.h>
+#include "ptrace_user.h"
 int ptrace_getregs(long pid, unsigned long *regs_out)
 {
diff --git a/arch/um/sys-i386/setjmp.S b/arch/x86/um/setjmp_32.S
index b766792c9933..b766792c9933 100644
--- a/arch/um/sys-i386/setjmp.S
+++ b/arch/x86/um/setjmp_32.S
diff --git a/arch/um/sys-x86_64/setjmp.S b/arch/x86/um/setjmp_64.S
index 45f547b4043e..45f547b4043e 100644
--- a/arch/um/sys-x86_64/setjmp.S
+++ b/arch/x86/um/setjmp_64.S
diff --git a/arch/x86/um/shared/sysdep/archsetjmp.h b/arch/x86/um/shared/sysdep/archsetjmp.h
new file mode 100644
index 000000000000..ff7766d28226
--- /dev/null
+++ b/arch/x86/um/shared/sysdep/archsetjmp.h
@@ -0,0 +1,5 @@
+#ifdef __i386__
+#include "archsetjmp_32.h"
+#else
+#include "archsetjmp_64.h"
+#endif
diff --git a/arch/um/sys-i386/shared/sysdep/archsetjmp.h b/arch/x86/um/shared/sysdep/archsetjmp_32.h
index 0f312085ce1d..0f312085ce1d 100644
--- a/arch/um/sys-i386/shared/sysdep/archsetjmp.h
+++ b/arch/x86/um/shared/sysdep/archsetjmp_32.h
diff --git a/arch/um/sys-x86_64/shared/sysdep/archsetjmp.h b/arch/x86/um/shared/sysdep/archsetjmp_64.h
index 2af8f12ca161..2af8f12ca161 100644
--- a/arch/um/sys-x86_64/shared/sysdep/archsetjmp.h
+++ b/arch/x86/um/shared/sysdep/archsetjmp_64.h
diff --git a/arch/x86/um/shared/sysdep/faultinfo.h b/arch/x86/um/shared/sysdep/faultinfo.h
new file mode 100644
index 000000000000..862ecb1c7781
--- /dev/null
+++ b/arch/x86/um/shared/sysdep/faultinfo.h
@@ -0,0 +1,5 @@
+#ifdef __i386__
+#include "faultinfo_32.h"
+#else
+#include "faultinfo_64.h"
+#endif
diff --git a/arch/um/sys-i386/shared/sysdep/faultinfo.h b/arch/x86/um/shared/sysdep/faultinfo_32.h
index db437cc373bc..a26086b8a800 100644
--- a/arch/um/sys-i386/shared/sysdep/faultinfo.h
+++ b/arch/x86/um/shared/sysdep/faultinfo_32.h
@@ -24,6 +24,12 @@ struct faultinfo {
 #define FAULT_WRITE(fi) ((fi).error_code & 2)
 #define FAULT_ADDRESS(fi) ((fi).cr2)
+/* This is Page Fault */
+#define SEGV_IS_FIXABLE(fi)     ((fi)->trap_no == 14)
+/* SKAS3 has no trap_no on i386, but get_skas_faultinfo() sets it to 0. */
+#define SEGV_MAYBE_FIXABLE(fi)  ((fi)->trap_no == 0 && ptrace_faultinfo)
 #define PTRACE_FULL_FAULTINFO 0
 #endif
diff --git a/arch/um/sys-x86_64/shared/sysdep/faultinfo.h b/arch/x86/um/shared/sysdep/faultinfo_64.h
index cb917b0d5660..f811cbe15d62 100644
--- a/arch/um/sys-x86_64/shared/sysdep/faultinfo.h
+++ b/arch/x86/um/shared/sysdep/faultinfo_64.h
@@ -24,6 +24,12 @@ struct faultinfo {
 #define FAULT_WRITE(fi) ((fi).error_code & 2)
 #define FAULT_ADDRESS(fi) ((fi).cr2)
+/* This is Page Fault */
+#define SEGV_IS_FIXABLE(fi)     ((fi)->trap_no == 14)
+/* No broken SKAS API, which doesn't pass trap_no, here. */
+#define SEGV_MAYBE_FIXABLE(fi)  0
 #define PTRACE_FULL_FAULTINFO 1
 #endif
diff --git a/arch/um/sys-i386/shared/sysdep/kernel-offsets.h b/arch/x86/um/shared/sysdep/kernel-offsets.h
index 5868526b5eef..5868526b5eef 100644
--- a/arch/um/sys-i386/shared/sysdep/kernel-offsets.h
+++ b/arch/x86/um/shared/sysdep/kernel-offsets.h
diff --git a/arch/x86/um/shared/sysdep/mcontext.h b/arch/x86/um/shared/sysdep/mcontext.h
new file mode 100644
index 000000000000..b724c54da316
--- /dev/null
+++ b/arch/x86/um/shared/sysdep/mcontext.h
@@ -0,0 +1,31 @@
+/* 
+ * Copyright (C) 2000 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
+ * Licensed under the GPL
+ */
+#ifndef __SYS_SIGCONTEXT_X86_H
+#define __SYS_SIGCONTEXT_X86_H
+extern void get_regs_from_mc(struct uml_pt_regs *, mcontext_t *);
+#ifdef __i386__
+#define GET_FAULTINFO_FROM_MC(fi, mc) \
+        { \
+                (fi).cr2 = (mc)->cr2; \
+                (fi).error_code = (mc)->gregs[REG_ERR]; \
+                (fi).trap_no = (mc)->gregs[REG_TRAPNO]; \
+        }
+#else
+#define GET_FAULTINFO_FROM_MC(fi, mc) \
+        { \
+                (fi).cr2 = (mc)->gregs[REG_CR2]; \
+                (fi).error_code = (mc)->gregs[REG_ERR]; \
+                (fi).trap_no = (mc)->gregs[REG_TRAPNO]; \
+        }
+#endif
+#endif
diff --git a/arch/x86/um/shared/sysdep/ptrace.h b/arch/x86/um/shared/sysdep/ptrace.h
new file mode 100644
index 000000000000..711b1621747f
--- /dev/null
+++ b/arch/x86/um/shared/sysdep/ptrace.h
@@ -0,0 +1,5 @@
+#ifdef __i386__
+#include "ptrace_32.h"
+#else
+#include "ptrace_64.h"
+#endif
diff --git a/arch/um/sys-i386/shared/sysdep/ptrace.h b/arch/x86/um/shared/sysdep/ptrace_32.h
index c398a5076111..befd1df32ed0 100644
--- a/arch/um/sys-i386/shared/sysdep/ptrace.h
+++ b/arch/x86/um/shared/sysdep/ptrace_32.h
@@ -6,7 +6,7 @@
 #ifndef __SYSDEP_I386_PTRACE_H
 #define __SYSDEP_I386_PTRACE_H
-#include "user_constants.h"
+#include <generated/user_constants.h>
 #include "sysdep/faultinfo.h"
 #define MAX_REG_NR (UM_FRAME_SIZE / sizeof(unsigned long))
@@ -24,18 +24,16 @@ void set_using_sysemu(int value);
 int get_using_sysemu(void);
 extern int sysemu_supported;
-#include "skas_ptregs.h"
 #define REGS_IP(r) ((r)[HOST_IP])
 #define REGS_SP(r) ((r)[HOST_SP])
 #define REGS_EFLAGS(r) ((r)[HOST_EFLAGS])
-#define REGS_EAX(r) ((r)[HOST_EAX])
+#define REGS_EAX(r) ((r)[HOST_AX])
-#define REGS_EBX(r) ((r)[HOST_EBX])
+#define REGS_EBX(r) ((r)[HOST_BX])
-#define REGS_ECX(r) ((r)[HOST_ECX])
+#define REGS_ECX(r) ((r)[HOST_CX])
-#define REGS_EDX(r) ((r)[HOST_EDX])
+#define REGS_EDX(r) ((r)[HOST_DX])
-#define REGS_ESI(r) ((r)[HOST_ESI])
+#define REGS_ESI(r) ((r)[HOST_SI])
-#define REGS_EDI(r) ((r)[HOST_EDI])
+#define REGS_EDI(r) ((r)[HOST_DI])
-#define REGS_EBP(r) ((r)[HOST_EBP])
+#define REGS_EBP(r) ((r)[HOST_BP])
 #define REGS_CS(r) ((r)[HOST_CS])
 #define REGS_SS(r) ((r)[HOST_SS])
 #define REGS_DS(r) ((r)[HOST_DS])
@@ -45,6 +43,7 @@ extern int sysemu_supported;
 #define REGS_SET_SYSCALL_RETURN(r, res) REGS_EAX(r) = (res)
+#define IP_RESTART_SYSCALL(ip) ((ip) -= 2)
 #define REGS_RESTART_SYSCALL(r) IP_RESTART_SYSCALL(REGS_IP(r))
 #ifndef PTRACE_SYSEMU_SINGLESTEP
@@ -102,62 +101,6 @@ struct syscall_args {
                                     UPT_SYSCALL_ARG5(r),       \
                                     UPT_SYSCALL_ARG6(r) } } )
-#define UPT_REG(regs, reg) \
-        ({      unsigned long val; \
-                switch(reg){ \
-                case EIP: val = UPT_IP(regs); break; \
-                case UESP: val = UPT_SP(regs); break; \
-                case EAX: val = UPT_EAX(regs); break; \
-                case EBX: val = UPT_EBX(regs); break; \
-                case ECX: val = UPT_ECX(regs); break; \
-                case EDX: val = UPT_EDX(regs); break; \
-                case ESI: val = UPT_ESI(regs); break; \
-                case EDI: val = UPT_EDI(regs); break; \
-                case EBP: val = UPT_EBP(regs); break; \
-                case ORIG_EAX: val = UPT_ORIG_EAX(regs); break; \
-                case CS: val = UPT_CS(regs); break; \
-                case SS: val = UPT_SS(regs); break; \
-                case DS: val = UPT_DS(regs); break; \
-                case ES: val = UPT_ES(regs); break; \
-                case FS: val = UPT_FS(regs); break; \
-                case GS: val = UPT_GS(regs); break; \
-                case EFL: val = UPT_EFLAGS(regs); break; \
-                default :  \
-                        panic("Bad register in UPT_REG : %d\n", reg);  \
-                        val = -1; \
-                } \
-                val; \
-        })
-#define UPT_SET(regs, reg, val) \
-        do { \
-                switch(reg){ \
-                case EIP: UPT_IP(regs) = val; break; \
-                case UESP: UPT_SP(regs) = val; break; \
-                case EAX: UPT_EAX(regs) = val; break; \
-                case EBX: UPT_EBX(regs) = val; break; \
-                case ECX: UPT_ECX(regs) = val; break; \
-                case EDX: UPT_EDX(regs) = val; break; \
-                case ESI: UPT_ESI(regs) = val; break; \
-                case EDI: UPT_EDI(regs) = val; break; \
-                case EBP: UPT_EBP(regs) = val; break; \
-                case ORIG_EAX: UPT_ORIG_EAX(regs) = val; break; \
-                case CS: UPT_CS(regs) = val; break; \
-                case SS: UPT_SS(regs) = val; break; \
-                case DS: UPT_DS(regs) = val; break; \
-                case ES: UPT_ES(regs) = val; break; \
-                case FS: UPT_FS(regs) = val; break; \
-                case GS: UPT_GS(regs) = val; break; \
-                case EFL: UPT_EFLAGS(regs) = val; break; \
-                default :  \
-                        panic("Bad register in UPT_SET : %d\n", reg);  \
-                        break; \
-                } \
-        } while (0)
-#define UPT_SET_SYSCALL_RETURN(r, res) \
-        REGS_SET_SYSCALL_RETURN((r)->regs, (res))
 #define UPT_RESTART_SYSCALL(r) REGS_RESTART_SYSCALL((r)->gp)
 #define UPT_ORIG_SYSCALL(r) UPT_EAX(r)
diff --git a/arch/um/sys-x86_64/shared/sysdep/ptrace.h b/arch/x86/um/shared/sysdep/ptrace_64.h
index 8ee8f8e12af1..031edc53ac57 100644
--- a/arch/um/sys-x86_64/shared/sysdep/ptrace.h
+++ b/arch/x86/um/shared/sysdep/ptrace_64.h
@@ -8,24 +8,22 @@
 #ifndef __SYSDEP_X86_64_PTRACE_H
 #define __SYSDEP_X86_64_PTRACE_H
-#include "user_constants.h"
+#include <generated/user_constants.h>
 #include "sysdep/faultinfo.h"
 #define MAX_REG_OFFSET (UM_FRAME_SIZE)
 #define MAX_REG_NR ((MAX_REG_OFFSET) / sizeof(unsigned long))
-#include "skas_ptregs.h"
 #define REGS_IP(r) ((r)[HOST_IP])
 #define REGS_SP(r) ((r)[HOST_SP])
-#define REGS_RBX(r) ((r)[HOST_RBX])
+#define REGS_RBX(r) ((r)[HOST_BX])
-#define REGS_RCX(r) ((r)[HOST_RCX])
+#define REGS_RCX(r) ((r)[HOST_CX])
-#define REGS_RDX(r) ((r)[HOST_RDX])
+#define REGS_RDX(r) ((r)[HOST_DX])
-#define REGS_RSI(r) ((r)[HOST_RSI])
+#define REGS_RSI(r) ((r)[HOST_SI])
-#define REGS_RDI(r) ((r)[HOST_RDI])
+#define REGS_RDI(r) ((r)[HOST_DI])
-#define REGS_RBP(r) ((r)[HOST_RBP])
+#define REGS_RBP(r) ((r)[HOST_BP])
-#define REGS_RAX(r) ((r)[HOST_RAX])
+#define REGS_RAX(r) ((r)[HOST_AX])
 #define REGS_R8(r) ((r)[HOST_R8])
 #define REGS_R9(r) ((r)[HOST_R9])
 #define REGS_R10(r) ((r)[HOST_R10])
@@ -67,14 +65,13 @@
 #define REGS_FS(r) ((r)[HOST_FS])
 #define REGS_GS(r) ((r)[HOST_GS])
-#define REGS_ORIG_RAX(r) ((r)[HOST_ORIG_RAX])
+#define REGS_ORIG_RAX(r) ((r)[HOST_ORIG_AX])
 #define REGS_SET_SYSCALL_RETURN(r, res) REGS_RAX(r) = (res)
+#define IP_RESTART_SYSCALL(ip) ((ip) -= 2)
 #define REGS_RESTART_SYSCALL(r) IP_RESTART_SYSCALL(REGS_IP(r))
-#define REGS_SEGV_IS_FIXABLE(r) SEGV_IS_FIXABLE((r)->trap_type)
 #define REGS_FAULT_ADDR(r) ((r)->fault_addr)
 #define REGS_FAULT_WRITE(r) FAULT_WRITE((r)->fault_type)
@@ -149,88 +146,8 @@ struct syscall_args {
                                     UPT_SYSCALL_ARG5(r),        \
                                     UPT_SYSCALL_ARG6(r) } } )
-#define UPT_REG(regs, reg) \
-        ({      unsigned long val;              \
-                switch(reg){                                            \
-                case R8: val = UPT_R8(regs); break;                     \
-                case R9: val = UPT_R9(regs); break;                     \
-                case R10: val = UPT_R10(regs); break;                   \
-                case R11: val = UPT_R11(regs); break;                   \
-                case R12: val = UPT_R12(regs); break;                   \
-                case R13: val = UPT_R13(regs); break;                   \
-                case R14: val = UPT_R14(regs); break;                   \
-                case R15: val = UPT_R15(regs); break;                   \
-                case RIP: val = UPT_IP(regs); break;                    \
-                case RSP: val = UPT_SP(regs); break;                    \
-                case RAX: val = UPT_RAX(regs); break;                   \
-                case RBX: val = UPT_RBX(regs); break;                   \
-                case RCX: val = UPT_RCX(regs); break;                   \
-                case RDX: val = UPT_RDX(regs); break;                   \
-                case RSI: val = UPT_RSI(regs); break;                   \
-                case RDI: val = UPT_RDI(regs); break;                   \
-                case RBP: val = UPT_RBP(regs); break;                   \
-                case ORIG_RAX: val = UPT_ORIG_RAX(regs); break;         \
-                case CS: val = UPT_CS(regs); break;                     \
-                case SS: val = UPT_SS(regs); break;                     \
-                case FS_BASE: val = UPT_FS_BASE(regs); break;           \
-                case GS_BASE: val = UPT_GS_BASE(regs); break;           \
-                case DS: val = UPT_DS(regs); break;                     \
-                case ES: val = UPT_ES(regs); break;                     \
-                case FS : val = UPT_FS (regs); break;                   \
-                case GS: val = UPT_GS(regs); break;                     \
-                case EFLAGS: val = UPT_EFLAGS(regs); break;             \
-                default :                                               \
-                        panic("Bad register in UPT_REG : %d\n", reg);   \
-                        val = -1;                                       \
-                }                                                       \
-                val;                                                    \
-        })
-#define UPT_SET(regs, reg, val) \
-        ({      unsigned long __upt_val = val;  \
-                switch(reg){                                            \
-                case R8: UPT_R8(regs) = __upt_val; break;               \
-                case R9: UPT_R9(regs) = __upt_val; break;               \
-                case R10: UPT_R10(regs) = __upt_val; break;             \
-                case R11: UPT_R11(regs) = __upt_val; break;             \
-                case R12: UPT_R12(regs) = __upt_val; break;             \
-                case R13: UPT_R13(regs) = __upt_val; break;             \
-                case R14: UPT_R14(regs) = __upt_val; break;             \
-                case R15: UPT_R15(regs) = __upt_val; break;             \
-                case RIP: UPT_IP(regs) = __upt_val; break;              \
-                case RSP: UPT_SP(regs) = __upt_val; break;              \
-                case RAX: UPT_RAX(regs) = __upt_val; break;             \
-                case RBX: UPT_RBX(regs) = __upt_val; break;             \
-                case RCX: UPT_RCX(regs) = __upt_val; break;             \
-                case RDX: UPT_RDX(regs) = __upt_val; break;             \
-                case RSI: UPT_RSI(regs) = __upt_val; break;             \
-                case RDI: UPT_RDI(regs) = __upt_val; break;             \
-                case RBP: UPT_RBP(regs) = __upt_val; break;             \
-                case ORIG_RAX: UPT_ORIG_RAX(regs) = __upt_val; break;   \
-                case CS: UPT_CS(regs) = __upt_val; break;               \
-                case SS: UPT_SS(regs) = __upt_val; break;               \
-                case FS_BASE: UPT_FS_BASE(regs) = __upt_val; break;     \
-                case GS_BASE: UPT_GS_BASE(regs) = __upt_val; break;     \
-                case DS: UPT_DS(regs) = __upt_val; break;               \
-                case ES: UPT_ES(regs) = __upt_val; break;               \
-                case FS: UPT_FS(regs) = __upt_val; break;               \
-                case GS: UPT_GS(regs) = __upt_val; break;               \
-                case EFLAGS: UPT_EFLAGS(regs) = __upt_val; break;       \
-                default :                                               \
-                        panic("Bad register in UPT_SET : %d\n", reg);   \
-                        break;                                          \
-                }                                                       \
-                __upt_val;                                              \
-        })
-#define UPT_SET_SYSCALL_RETURN(r, res) \
-        REGS_SET_SYSCALL_RETURN((r)->regs, (res))
 #define UPT_RESTART_SYSCALL(r) REGS_RESTART_SYSCALL((r)->gp)
-#define UPT_SEGV_IS_FIXABLE(r) REGS_SEGV_IS_FIXABLE(&r->skas)
 #define UPT_FAULTINFO(r) (&(r)->faultinfo)
 static inline void arch_init_registers(int pid)
diff --git a/arch/x86/um/shared/sysdep/ptrace_user.h b/arch/x86/um/shared/sysdep/ptrace_user.h
new file mode 100644
index 000000000000..16cd6b5e71f7
--- /dev/null
+++ b/arch/x86/um/shared/sysdep/ptrace_user.h
@@ -0,0 +1,27 @@
+#include <generated/user_constants.h>
+#define PT_OFFSET(r) ((r) * sizeof(long))
+#define PT_SYSCALL_NR(regs) ((regs)[HOST_ORIG_AX])
+#define PT_SYSCALL_NR_OFFSET PT_OFFSET(HOST_ORIG_AX)
+#define PT_SYSCALL_RET_OFFSET PT_OFFSET(HOST_AX)
+#define REGS_IP_INDEX HOST_IP
+#define REGS_SP_INDEX HOST_SP
+#ifdef __i386__
+#define FP_SIZE ((HOST_FPX_SIZE > HOST_FP_SIZE) ? HOST_FPX_SIZE : HOST_FP_SIZE)
+#else
+#define FP_SIZE HOST_FP_SIZE
+/*
+ * x86_64 FC3 doesn't define this in /usr/include/linux/ptrace.h even though
+ * it's defined in the kernel's include/linux/ptrace.h. Additionally, use the
+ * 2.4 name and value for 2.4 host compatibility.
+ */
+#ifndef PTRACE_OLDSETOPTIONS
+#define PTRACE_OLDSETOPTIONS 21
+#endif
+#endif
diff --git a/arch/um/sys-i386/shared/sysdep/skas_ptrace.h b/arch/x86/um/shared/sysdep/skas_ptrace.h
index e27b8a791773..453febe98993 100644
--- a/arch/um/sys-i386/shared/sysdep/skas_ptrace.h
+++ b/arch/x86/um/shared/sysdep/skas_ptrace.h
@@ -3,8 +3,8 @@
 * Licensed under the GPL
 */
-#ifndef __SYSDEP_I386_SKAS_PTRACE_H
+#ifndef __SYSDEP_X86_SKAS_PTRACE_H
-#define __SYSDEP_I386_SKAS_PTRACE_H
+#define __SYSDEP_X86_SKAS_PTRACE_H
 struct ptrace_faultinfo {
        int is_write;
diff --git a/arch/x86/um/shared/sysdep/stub.h b/arch/x86/um/shared/sysdep/stub.h
new file mode 100644
index 000000000000..bd161e300102
--- /dev/null
+++ b/arch/x86/um/shared/sysdep/stub.h
@@ -0,0 +1,14 @@
+#include <asm/unistd.h>
+#include <sys/mman.h>
+#include <signal.h>
+#include "as-layout.h"
+#include "stub-data.h"
+#ifdef __i386__
+#include "stub_32.h"
+#else
+#include "stub_64.h"
+#endif
+extern void stub_segv_handler(int, siginfo_t *, void *);
+extern void stub_clone_handler(void);
diff --git a/arch/um/sys-i386/shared/sysdep/stub.h b/arch/x86/um/shared/sysdep/stub_32.h
index 977dedd9221b..51fd256c75f0 100644
--- a/arch/um/sys-i386/shared/sysdep/stub.h
+++ b/arch/x86/um/shared/sysdep/stub_32.h
@@ -6,15 +6,7 @@
 #ifndef __SYSDEP_STUB_H
 #define __SYSDEP_STUB_H
-#include <sys/mman.h>
 #include <asm/ptrace.h>
-#include <asm/unistd.h>
-#include "as-layout.h"
-#include "stub-data.h"
-#include "kern_constants.h"
-extern void stub_segv_handler(int sig);
-extern void stub_clone_handler(void);
 #define STUB_SYSCALL_RET EAX
 #define STUB_MMAP_NR __NR_mmap2
diff --git a/arch/um/sys-x86_64/shared/sysdep/stub.h b/arch/x86/um/shared/sysdep/stub_64.h
index 3432aa249970..994df93c5ed3 100644
--- a/arch/um/sys-x86_64/shared/sysdep/stub.h
+++ b/arch/x86/um/shared/sysdep/stub_64.h
@@ -6,15 +6,7 @@
 #ifndef __SYSDEP_STUB_H
 #define __SYSDEP_STUB_H
-#include <sys/mman.h>
-#include <asm/unistd.h>
 #include <sysdep/ptrace_user.h>
-#include "as-layout.h"
-#include "stub-data.h"
-#include "kern_constants.h"
-extern void stub_segv_handler(int sig);
-extern void stub_clone_handler(void);
 #define STUB_SYSCALL_RET PT_INDEX(RAX)
 #define STUB_MMAP_NR __NR_mmap
diff --git a/arch/x86/um/shared/sysdep/syscalls.h b/arch/x86/um/shared/sysdep/syscalls.h
new file mode 100644
index 000000000000..bd9a89b67e41
--- /dev/null
+++ b/arch/x86/um/shared/sysdep/syscalls.h
@@ -0,0 +1,5 @@
+#ifdef __i386__
+#include "syscalls_32.h"
+#else
+#include "syscalls_64.h"
+#endif
diff --git a/arch/um/sys-i386/shared/sysdep/syscalls.h b/arch/x86/um/shared/sysdep/syscalls_32.h
index 05cb796aecb5..05cb796aecb5 100644
--- a/arch/um/sys-i386/shared/sysdep/syscalls.h
+++ b/arch/x86/um/shared/sysdep/syscalls_32.h
diff --git a/arch/um/sys-x86_64/shared/sysdep/syscalls.h b/arch/x86/um/shared/sysdep/syscalls_64.h
index 7cfb0b085655..8a7d5e1da98e 100644
--- a/arch/um/sys-x86_64/shared/sysdep/syscalls.h
+++ b/arch/x86/um/shared/sysdep/syscalls_64.h
@@ -9,7 +9,6 @@
 #include <linux/msg.h>
 #include <linux/shm.h>
-#include <kern_constants.h>
 typedef long syscall_handler_t(void);
diff --git a/arch/um/sys-i386/shared/sysdep/tls.h b/arch/x86/um/shared/sysdep/tls.h
index 34550755b2a1..27cce00c6b30 100644
--- a/arch/um/sys-i386/shared/sysdep/tls.h
+++ b/arch/x86/um/shared/sysdep/tls.h
@@ -17,16 +17,23 @@ typedef struct um_dup_user_desc {
        unsigned int  limit_in_pages:1;
        unsigned int  seg_not_present:1;
        unsigned int  useable:1;
+#ifdef __x86_64__
+        unsigned int  lm:1;
+#endif
 } user_desc_t;
 # else /* __KERNEL__ */
-#  include <ldt.h>
 typedef struct user_desc user_desc_t;
 # endif /* __KERNEL__ */
+extern int os_set_thread_area(user_desc_t *info, int pid);
+extern int os_get_thread_area(user_desc_t *info, int pid);
+#ifdef __i386__
 #define GDT_ENTRY_TLS_MIN_I386 6
 #define GDT_ENTRY_TLS_MIN_X86_64 12
+#endif
 #endif /* _SYSDEP_TLS_H */
diff --git a/arch/um/sys-i386/signal.c b/arch/x86/um/signal.c
index 89a46626bfd8..4883b9546016 100644
--- a/arch/um/sys-i386/signal.c
+++ b/arch/x86/um/signal.c
@@ -1,36 +1,20 @@
 /*
- * Copyright (C) 2004 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
+ * Copyright (C) 2003 PathScale, Inc.
+ * Copyright (C) 2003 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
 * Licensed under the GPL
 */
+#include <linux/personality.h>
 #include <linux/ptrace.h>
+#include <linux/kernel.h>
 #include <asm/unistd.h>
 #include <asm/uaccess.h>
 #include <asm/ucontext.h>
 #include "frame_kern.h"
 #include "skas.h"
-void copy_sc(struct uml_pt_regs *regs, void *from)
+#ifdef CONFIG_X86_32
-{
-        struct sigcontext *sc = from;
-        REGS_GS(regs->gp) = sc->gs;
-        REGS_FS(regs->gp) = sc->fs;
-        REGS_ES(regs->gp) = sc->es;
-        REGS_DS(regs->gp) = sc->ds;
-        REGS_EDI(regs->gp) = sc->di;
-        REGS_ESI(regs->gp) = sc->si;
-        REGS_EBP(regs->gp) = sc->bp;
-        REGS_SP(regs->gp) = sc->sp;
-        REGS_EBX(regs->gp) = sc->bx;
-        REGS_EDX(regs->gp) = sc->dx;
-        REGS_ECX(regs->gp) = sc->cx;
-        REGS_EAX(regs->gp) = sc->ax;
-        REGS_IP(regs->gp) = sc->ip;
-        REGS_CS(regs->gp) = sc->cs;
-        REGS_EFLAGS(regs->gp) = sc->flags;
-        REGS_SS(regs->gp) = sc->ss;
-}
 /*
 * FPU tag word conversions.
@@ -164,6 +148,8 @@ static int convert_fxsr_from_user(struct user_fxsr_struct *fxsave,
 extern int have_fpx_regs;
+#endif
 static int copy_sc_from_user(struct pt_regs *regs,
                             struct sigcontext __user *from)
 {
@@ -174,8 +160,45 @@ static int copy_sc_from_user(struct pt_regs *regs,
        if (err)
                return err;
+#define GETREG(regno, regname) regs->regs.gp[HOST_##regno] = sc.regname
+#ifdef CONFIG_X86_32
+        GETREG(GS, gs);
+        GETREG(FS, fs);
+        GETREG(ES, es);
+        GETREG(DS, ds);
+#endif
+        GETREG(DI, di);
+        GETREG(SI, si);
+        GETREG(BP, bp);
+        GETREG(SP, sp);
+        GETREG(BX, bx);
+        GETREG(DX, dx);
+        GETREG(CX, cx);
+        GETREG(AX, ax);
+        GETREG(IP, ip);
+#ifdef CONFIG_X86_64
+        GETREG(R8, r8);
+        GETREG(R9, r9);
+        GETREG(R10, r10);
+        GETREG(R11, r11);
+        GETREG(R12, r12);
+        GETREG(R13, r13);
+        GETREG(R14, r14);
+        GETREG(R15, r15);
+#endif
+        GETREG(CS, cs);
+        GETREG(EFLAGS, flags);
+#ifdef CONFIG_X86_32
+        GETREG(SS, ss);
+#endif
+#undef GETREG
        pid = userspace_pid[current_thread_info()->cpu];
-        copy_sc(&regs->regs, &sc);
+#ifdef CONFIG_X86_32
        if (have_fpx_regs) {
                struct user_fxsr_struct fpx;
@@ -196,8 +219,9 @@ static int copy_sc_from_user(struct pt_regs *regs,
                               -err);
                        return 1;
                }
-        }
+        } else
-        else {
+#endif
+        {
                struct user_i387_struct fp;
                err = copy_from_user(&fp, sc.fpstate,
@@ -213,43 +237,66 @@ static int copy_sc_from_user(struct pt_regs *regs,
                        return 1;
                }
        }
        return 0;
 }
 static int copy_sc_to_user(struct sigcontext __user *to,
                           struct _fpstate __user *to_fp, struct pt_regs *regs,
-                           unsigned long sp)
+                           unsigned long mask)
 {
        struct sigcontext sc;
        struct faultinfo * fi = &current->thread.arch.faultinfo;
        int err, pid;
+        memset(&sc, 0, sizeof(struct sigcontext));
+#define PUTREG(regno, regname) sc.regname = regs->regs.gp[HOST_##regno]
+#ifdef CONFIG_X86_32
+        PUTREG(GS, gs);
+        PUTREG(FS, fs);
+        PUTREG(ES, es);
+        PUTREG(DS, ds);
+#endif
+        PUTREG(DI, di);
+        PUTREG(SI, si);
+        PUTREG(BP, bp);
+        PUTREG(SP, sp);
+        PUTREG(BX, bx);
+        PUTREG(DX, dx);
+        PUTREG(CX, cx);
+        PUTREG(AX, ax);
+#ifdef CONFIG_X86_64
+        PUTREG(R8, r8);
+        PUTREG(R9, r9);
+        PUTREG(R10, r10);
+        PUTREG(R11, r11);
+        PUTREG(R12, r12);
+        PUTREG(R13, r13);
+        PUTREG(R14, r14);
+        PUTREG(R15, r15);
+#endif
-        sc.gs = REGS_GS(regs->regs.gp);
-        sc.fs = REGS_FS(regs->regs.gp);
-        sc.es = REGS_ES(regs->regs.gp);
-        sc.ds = REGS_DS(regs->regs.gp);
-        sc.di = REGS_EDI(regs->regs.gp);
-        sc.si = REGS_ESI(regs->regs.gp);
-        sc.bp = REGS_EBP(regs->regs.gp);
-        sc.sp = sp;
-        sc.bx = REGS_EBX(regs->regs.gp);
-        sc.dx = REGS_EDX(regs->regs.gp);
-        sc.cx = REGS_ECX(regs->regs.gp);
-        sc.ax = REGS_EAX(regs->regs.gp);
-        sc.ip = REGS_IP(regs->regs.gp);
-        sc.cs = REGS_CS(regs->regs.gp);
-        sc.flags = REGS_EFLAGS(regs->regs.gp);
-        sc.sp_at_signal = regs->regs.gp[UESP];
-        sc.ss = regs->regs.gp[SS];
        sc.cr2 = fi->cr2;
        sc.err = fi->error_code;
        sc.trapno = fi->trap_no;
+        PUTREG(IP, ip);
-        to_fp = (to_fp ? to_fp : (struct _fpstate __user *) (to + 1));
+        PUTREG(CS, cs);
+        PUTREG(EFLAGS, flags);
+#ifdef CONFIG_X86_32
+        PUTREG(SP, sp_at_signal);
+        PUTREG(SS, ss);
+#endif
+#undef PUTREG
+        sc.oldmask = mask;
        sc.fpstate = to_fp;
+        err = copy_to_user(to, &sc, sizeof(struct sigcontext));
+        if (err)
+                return 1;
        pid = userspace_pid[current_thread_info()->cpu];
+#ifdef CONFIG_X86_32
        if (have_fpx_regs) {
                struct user_fxsr_struct fpx;
@@ -272,8 +319,9 @@ static int copy_sc_to_user(struct sigcontext __user *to,
                if (copy_to_user(&to_fp->_fxsr_env[0], &fpx,
                                 sizeof(struct user_fxsr_struct)))
                        return 1;
-        }
+        } else
-        else {
+#endif
+        {
                struct user_i387_struct fp;
                err = save_fp_registers(pid, (unsigned long *) &fp);
@@ -281,9 +329,10 @@ static int copy_sc_to_user(struct sigcontext __user *to,
                        return 1;
        }
-        return copy_to_user(to, &sc, sizeof(sc));
+        return 0;
 }
+#ifdef CONFIG_X86_32
 static int copy_ucontext_to_user(struct ucontext __user *uc,
                                 struct _fpstate __user *fp, sigset_t *set,
                                 unsigned long sp)
@@ -293,7 +342,7 @@ static int copy_ucontext_to_user(struct ucontext __user *uc,
        err |= put_user(current->sas_ss_sp, &uc->uc_stack.ss_sp);
        err |= put_user(sas_ss_flags(sp), &uc->uc_stack.ss_flags);
        err |= put_user(current->sas_ss_size, &uc->uc_stack.ss_size);
-        err |= copy_sc_to_user(&uc->uc_mcontext, fp, &current->thread.regs, sp);
+        err |= copy_sc_to_user(&uc->uc_mcontext, fp, &current->thread.regs, 0);
        err |= copy_to_user(&uc->uc_sigmask, set, sizeof(*set));
        return err;
 }
@@ -326,7 +375,6 @@ int setup_signal_stack_sc(unsigned long stack_top, int sig,
 {
        struct sigframe __user *frame;
        void __user *restorer;
-        unsigned long save_sp = PT_REGS_SP(regs);
        int err = 0;
        /* This is the same calculation as i386 - ((sp + 4) & 15) == 0 */
@@ -339,20 +387,9 @@ int setup_signal_stack_sc(unsigned long stack_top, int sig,
        if (ka->sa.sa_flags & SA_RESTORER)
                restorer = ka->sa.sa_restorer;
-        /* Update SP now because the page fault handler refuses to extend
-         * the stack if the faulting address is too far below the current
-         * SP, which frame now certainly is.  If there's an error, the original
-         * value is restored on the way out.
-         * When writing the sigcontext to the stack, we have to write the
-         * original value, so that's passed to copy_sc_to_user, which does
-         * the right thing with it.
-         */
-        PT_REGS_SP(regs) = (unsigned long) frame;
        err |= __put_user(restorer, &frame->pretcode);
        err |= __put_user(sig, &frame->sig);
-        err |= copy_sc_to_user(&frame->sc, NULL, regs, save_sp);
+        err |= copy_sc_to_user(&frame->sc, &frame->fpstate, regs, mask->sig[0]);
-        err |= __put_user(mask->sig[0], &frame->sc.oldmask);
        if (_NSIG_WORDS > 1)
                err |= __copy_to_user(&frame->extramask, &mask->sig[1],
                                      sizeof(frame->extramask));
@@ -369,7 +406,7 @@ int setup_signal_stack_sc(unsigned long stack_top, int sig,
        err |= __put_user(0x80cd, (short __user *)(frame->retcode+6));
        if (err)
-                goto err;
+                return err;
        PT_REGS_SP(regs) = (unsigned long) frame;
        PT_REGS_IP(regs) = (unsigned long) ka->sa.sa_handler;
@@ -380,10 +417,6 @@ int setup_signal_stack_sc(unsigned long stack_top, int sig,
        if ((current->ptrace & PT_DTRACE) && (current->ptrace & PT_PTRACED))
                ptrace_notify(SIGTRAP);
        return 0;
-err:
-        PT_REGS_SP(regs) = save_sp;
-        return err;
 }
 int setup_signal_stack_si(unsigned long stack_top, int sig,
@@ -392,7 +425,6 @@ int setup_signal_stack_si(unsigned long stack_top, int sig,
 {
        struct rt_sigframe __user *frame;
        void __user *restorer;
-        unsigned long save_sp = PT_REGS_SP(regs);
        int err = 0;
        stack_top &= -8UL;
@@ -404,16 +436,13 @@ int setup_signal_stack_si(unsigned long stack_top, int sig,
        if (ka->sa.sa_flags & SA_RESTORER)
                restorer = ka->sa.sa_restorer;
-        /* See comment above about why this is here */
-        PT_REGS_SP(regs) = (unsigned long) frame;
        err |= __put_user(restorer, &frame->pretcode);
        err |= __put_user(sig, &frame->sig);
        err |= __put_user(&frame->info, &frame->pinfo);
        err |= __put_user(&frame->uc, &frame->puc);
        err |= copy_siginfo_to_user(&frame->info, info);
        err |= copy_ucontext_to_user(&frame->uc, &frame->fpstate, mask,
-                                     save_sp);
+                                        PT_REGS_SP(regs));
        /*
         * This is movl $,%eax ; int $0x80
@@ -427,8 +456,9 @@ int setup_signal_stack_si(unsigned long stack_top, int sig,
        err |= __put_user(0x80cd, (short __user *)(frame->retcode+5));
        if (err)
-                goto err;
+                return err;
+        PT_REGS_SP(regs) = (unsigned long) frame;
        PT_REGS_IP(regs) = (unsigned long) ka->sa.sa_handler;
        PT_REGS_EAX(regs) = (unsigned long) sig;
        PT_REGS_EDX(regs) = (unsigned long) &frame->info;
@@ -437,13 +467,9 @@ int setup_signal_stack_si(unsigned long stack_top, int sig,
        if ((current->ptrace & PT_DTRACE) && (current->ptrace & PT_PTRACED))
                ptrace_notify(SIGTRAP);
        return 0;
-err:
-        PT_REGS_SP(regs) = save_sp;
-        return err;
 }
-long sys_sigreturn(struct pt_regs regs)
+long sys_sigreturn(struct pt_regs *regs)
 {
        unsigned long sp = PT_REGS_SP(&current->thread.regs);
        struct sigframe __user *frame = (struct sigframe __user *)(sp - 8);
@@ -458,11 +484,7 @@ long sys_sigreturn(struct pt_regs regs)
                goto segfault;
        sigdelsetmask(&set, ~_BLOCKABLE);
+        set_current_blocked(&set);
-        spin_lock_irq(&current->sighand->siglock);
-        current->blocked = set;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
        if (copy_sc_from_user(&current->thread.regs, sc))
                goto segfault;
@@ -476,24 +498,107 @@ long sys_sigreturn(struct pt_regs regs)
        return 0;
 }
-long sys_rt_sigreturn(struct pt_regs regs)
+#else
+struct rt_sigframe
+{
+        char __user *pretcode;
+        struct ucontext uc;
+        struct siginfo info;
+        struct _fpstate fpstate;
+};
+int setup_signal_stack_si(unsigned long stack_top, int sig,
+                          struct k_sigaction *ka, struct pt_regs * regs,
+                          siginfo_t *info, sigset_t *set)
+{
+        struct rt_sigframe __user *frame;
+        int err = 0;
+        struct task_struct *me = current;
+        frame = (struct rt_sigframe __user *)
+                round_down(stack_top - sizeof(struct rt_sigframe), 16);
+        /* Subtract 128 for a red zone and 8 for proper alignment */
+        frame = (struct rt_sigframe __user *) ((unsigned long) frame - 128 - 8);
+        if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
+                goto out;
+        if (ka->sa.sa_flags & SA_SIGINFO) {
+                err |= copy_siginfo_to_user(&frame->info, info);
+                if (err)
+                        goto out;
+        }
+        /* Create the ucontext.  */
+        err |= __put_user(0, &frame->uc.uc_flags);
+        err |= __put_user(0, &frame->uc.uc_link);
+        err |= __put_user(me->sas_ss_sp, &frame->uc.uc_stack.ss_sp);
+        err |= __put_user(sas_ss_flags(PT_REGS_SP(regs)),
+                          &frame->uc.uc_stack.ss_flags);
+        err |= __put_user(me->sas_ss_size, &frame->uc.uc_stack.ss_size);
+        err |= copy_sc_to_user(&frame->uc.uc_mcontext, &frame->fpstate, regs,
+                               set->sig[0]);
+        err |= __put_user(&frame->fpstate, &frame->uc.uc_mcontext.fpstate);
+        if (sizeof(*set) == 16) {
+                __put_user(set->sig[0], &frame->uc.uc_sigmask.sig[0]);
+                __put_user(set->sig[1], &frame->uc.uc_sigmask.sig[1]);
+        }
+        else
+                err |= __copy_to_user(&frame->uc.uc_sigmask, set,
+                                      sizeof(*set));
+        /*
+         * Set up to return from userspace.  If provided, use a stub
+         * already in userspace.
+         */
+        /* x86-64 should always use SA_RESTORER. */
+        if (ka->sa.sa_flags & SA_RESTORER)
+                err |= __put_user(ka->sa.sa_restorer, &frame->pretcode);
+        else
+                /* could use a vstub here */
+                return err;
+        if (err)
+                return err;
+        /* Set up registers for signal handler */
+        {
+                struct exec_domain *ed = current_thread_info()->exec_domain;
+                if (unlikely(ed && ed->signal_invmap && sig < 32))
+                        sig = ed->signal_invmap[sig];
+        }
+        PT_REGS_SP(regs) = (unsigned long) frame;
+        PT_REGS_RDI(regs) = sig;
+        /* In case the signal handler was declared without prototypes */
+        PT_REGS_RAX(regs) = 0;
+        /*
+         * This also works for non SA_SIGINFO handlers because they expect the
+         * next argument after the signal number on the stack.
+         */
+        PT_REGS_RSI(regs) = (unsigned long) &frame->info;
+        PT_REGS_RDX(regs) = (unsigned long) &frame->uc;
+        PT_REGS_RIP(regs) = (unsigned long) ka->sa.sa_handler;
+ out:
+        return err;
+}
+#endif
+long sys_rt_sigreturn(struct pt_regs *regs)
 {
        unsigned long sp = PT_REGS_SP(&current->thread.regs);
        struct rt_sigframe __user *frame =
-                (struct rt_sigframe __user *) (sp - 4);
+                (struct rt_sigframe __user *)(sp - sizeof(long));
-        sigset_t set;
        struct ucontext __user *uc = &frame->uc;
-        int sig_size = _NSIG_WORDS * sizeof(unsigned long);
+        sigset_t set;
-        if (copy_from_user(&set, &uc->uc_sigmask, sig_size))
+        if (copy_from_user(&set, &uc->uc_sigmask, sizeof(set)))
                goto segfault;
        sigdelsetmask(&set, ~_BLOCKABLE);
+        set_current_blocked(&set);
-        spin_lock_irq(&current->sighand->siglock);
-        current->blocked = set;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
        if (copy_sc_from_user(&current->thread.regs, &uc->uc_mcontext))
                goto segfault;
@@ -506,3 +611,14 @@ long sys_rt_sigreturn(struct pt_regs regs)
        force_sig(SIGSEGV, current);
        return 0;
 }
+#ifdef CONFIG_X86_32
+long ptregs_sigreturn(void)
+{
+        return sys_sigreturn(NULL);
+}
+long ptregs_rt_sigreturn(void)
+{
+        return sys_rt_sigreturn(NULL);
+}
+#endif
diff --git a/arch/um/sys-i386/stub.S b/arch/x86/um/stub_32.S
index 54a36ec20cb7..54a36ec20cb7 100644
--- a/arch/um/sys-i386/stub.S
+++ b/arch/x86/um/stub_32.S
diff --git a/arch/um/sys-x86_64/stub.S b/arch/x86/um/stub_64.S
index 20e4a96a6dcb..20e4a96a6dcb 100644
--- a/arch/um/sys-x86_64/stub.S
+++ b/arch/x86/um/stub_64.S
diff --git a/arch/um/sys-x86_64/stub_segv.c b/arch/x86/um/stub_segv.c
index ced051afc705..b7450bd22e7d 100644
--- a/arch/um/sys-x86_64/stub_segv.c
+++ b/arch/x86/um/stub_segv.c
@@ -3,19 +3,16 @@
 * Licensed under the GPL
 */
-#include <signal.h>
-#include "as-layout.h"
 #include "sysdep/stub.h"
 #include "sysdep/faultinfo.h"
-#include "sysdep/sigcontext.h"
+#include "sysdep/mcontext.h"
 void __attribute__ ((__section__ (".__syscall_stub")))
-stub_segv_handler(int sig)
+stub_segv_handler(int sig, siginfo_t *info, void *p)
 {
-        struct ucontext *uc;
+        struct ucontext *uc = p;
-        __asm__ __volatile__("movq %%rdx, %0" : "=g" (uc) :);
+        GET_FAULTINFO_FROM_MC(*((struct faultinfo *) STUB_DATA),
-        GET_FAULTINFO_FROM_SC(*((struct faultinfo *) STUB_DATA),
                              &uc->uc_mcontext);
        trap_myself();
 }
diff --git a/arch/um/sys-i386/sys_call_table.S b/arch/x86/um/sys_call_table_32.S
index de274071455d..a7ca80d2dceb 100644
--- a/arch/um/sys-i386/sys_call_table.S
+++ b/arch/x86/um/sys_call_table_32.S
@@ -13,16 +13,14 @@
 #define ptregs_execve sys_execve
 #define ptregs_iopl sys_iopl
 #define ptregs_vm86old sys_vm86old
-#define ptregs_sigreturn sys_sigreturn
 #define ptregs_clone sys_clone
 #define ptregs_vm86 sys_vm86
-#define ptregs_rt_sigreturn sys_rt_sigreturn
 #define ptregs_sigaltstack sys_sigaltstack
 #define ptregs_vfork sys_vfork
 .section .rodata,"a"
-#include "../../x86/kernel/syscall_table_32.S"
+#include "../kernel/syscall_table_32.S"
 ENTRY(syscall_table_size)
 .long .-sys_call_table
diff --git a/arch/um/sys-x86_64/syscall_table.c b/arch/x86/um/sys_call_table_64.c
index 47d469e7e7ce..99522f78b162 100644
--- a/arch/um/sys-x86_64/syscall_table.c
+++ b/arch/x86/um/sys_call_table_64.c
@@ -6,7 +6,6 @@
 #include <linux/linkage.h>
 #include <linux/sys.h>
 #include <linux/cache.h>
-#include <kern_constants.h>
 #define __NO_STUBS
@@ -59,7 +58,7 @@ extern void sys_ni_syscall(void);
 */
 sys_call_ptr_t sys_call_table[] __cacheline_aligned = {
-#include "../../x86/include/asm/unistd_64.h"
+#include <asm/unistd_64.h>
 };
 int syscall_table_size = sizeof(sys_call_table);
diff --git a/arch/um/sys-i386/syscalls.c b/arch/x86/um/syscalls_32.c
index 70ca357393b8..70ca357393b8 100644
--- a/arch/um/sys-i386/syscalls.c
+++ b/arch/x86/um/syscalls_32.c
diff --git a/arch/um/sys-x86_64/syscalls.c b/arch/x86/um/syscalls_64.c
index f3d82bb6e15a..f3d82bb6e15a 100644
--- a/arch/um/sys-x86_64/syscalls.c
+++ b/arch/x86/um/syscalls_64.c
diff --git a/arch/um/sys-i386/sysrq.c b/arch/x86/um/sysrq_32.c
index 171b3e9dc867..171b3e9dc867 100644
--- a/arch/um/sys-i386/sysrq.c
+++ b/arch/x86/um/sysrq_32.c
diff --git a/arch/um/sys-x86_64/sysrq.c b/arch/x86/um/sysrq_64.c
index f4f82beb3508..e8913436d7dc 100644
--- a/arch/um/sys-x86_64/sysrq.c
+++ b/arch/x86/um/sysrq_64.c
@@ -20,7 +20,7 @@ void __show_regs(struct pt_regs *regs)
                current->comm, print_tainted(), init_utsname()->release);
        printk(KERN_INFO "RIP: %04lx:[<%016lx>]\n", PT_REGS_CS(regs) & 0xffff,
               PT_REGS_RIP(regs));
-        printk(KERN_INFO "RSP: %016lx  EFLAGS: %08lx\n", PT_REGS_RSP(regs),
+        printk(KERN_INFO "RSP: %016lx  EFLAGS: %08lx\n", PT_REGS_SP(regs),
               PT_REGS_EFLAGS(regs));
        printk(KERN_INFO "RAX: %016lx RBX: %016lx RCX: %016lx\n",
               PT_REGS_RAX(regs), PT_REGS_RBX(regs), PT_REGS_RCX(regs));
diff --git a/arch/um/sys-i386/tls.c b/arch/x86/um/tls_32.c
index c6c7131e563b..c6c7131e563b 100644
--- a/arch/um/sys-i386/tls.c
+++ b/arch/x86/um/tls_32.c
diff --git a/arch/um/sys-x86_64/tls.c b/arch/x86/um/tls_64.c
index f7ba46200ecd..f7ba46200ecd 100644
--- a/arch/um/sys-x86_64/tls.c
+++ b/arch/x86/um/tls_64.c
diff --git a/arch/um/sys-x86_64/user-offsets.c b/arch/x86/um/user-offsets.c
index 973585414a66..ca49be8ddd0c 100644
--- a/arch/um/sys-x86_64/user-offsets.c
+++ b/arch/x86/um/user-offsets.c
@@ -9,28 +9,43 @@
 #include <asm/types.h>
 #define DEFINE(sym, val) \
-        asm volatile("\n->" #sym " %0 " #val : : "i" (val))
+        asm volatile("\n->" #sym " %0 " #val : : "i" (val))
 #define DEFINE_LONGS(sym, val) \
-        asm volatile("\n->" #sym " %0 " #val : : "i" (val/sizeof(unsigned long)))
+        asm volatile("\n->" #sym " %0 " #val : : "i" (val/sizeof(unsigned long)))
-#define OFFSET(sym, str, mem) \
-        DEFINE(sym, offsetof(struct str, mem));
 void foo(void)
 {
-        OFFSET(HOST_SC_CR2, sigcontext, cr2);
+#ifdef __i386__
-        OFFSET(HOST_SC_ERR, sigcontext, err);
+        DEFINE_LONGS(HOST_FP_SIZE, sizeof(struct user_fpregs_struct));
-        OFFSET(HOST_SC_TRAPNO, sigcontext, trapno);
+        DEFINE_LONGS(HOST_FPX_SIZE, sizeof(struct user_fpxregs_struct));
+        DEFINE(HOST_IP, EIP);
+        DEFINE(HOST_SP, UESP);
+        DEFINE(HOST_EFLAGS, EFL);
+        DEFINE(HOST_AX, EAX);
+        DEFINE(HOST_BX, EBX);
+        DEFINE(HOST_CX, ECX);
+        DEFINE(HOST_DX, EDX);
+        DEFINE(HOST_SI, ESI);
+        DEFINE(HOST_DI, EDI);
+        DEFINE(HOST_BP, EBP);
+        DEFINE(HOST_CS, CS);
+        DEFINE(HOST_SS, SS);
+        DEFINE(HOST_DS, DS);
+        DEFINE(HOST_FS, FS);
+        DEFINE(HOST_ES, ES);
+        DEFINE(HOST_GS, GS);
+        DEFINE(HOST_ORIG_AX, ORIG_EAX);
+#else
        DEFINE(HOST_FP_SIZE, sizeof(struct _fpstate) / sizeof(unsigned long));
-        DEFINE_LONGS(HOST_RBX, RBX);
+        DEFINE_LONGS(HOST_BX, RBX);
-        DEFINE_LONGS(HOST_RCX, RCX);
+        DEFINE_LONGS(HOST_CX, RCX);
-        DEFINE_LONGS(HOST_RDI, RDI);
+        DEFINE_LONGS(HOST_DI, RDI);
-        DEFINE_LONGS(HOST_RSI, RSI);
+        DEFINE_LONGS(HOST_SI, RSI);
-        DEFINE_LONGS(HOST_RDX, RDX);
+        DEFINE_LONGS(HOST_DX, RDX);
-        DEFINE_LONGS(HOST_RBP, RBP);
+        DEFINE_LONGS(HOST_BP, RBP);
-        DEFINE_LONGS(HOST_RAX, RAX);
+        DEFINE_LONGS(HOST_AX, RAX);
        DEFINE_LONGS(HOST_R8, R8);
        DEFINE_LONGS(HOST_R9, R9);
        DEFINE_LONGS(HOST_R10, R10);
@@ -39,7 +54,7 @@ void foo(void)
        DEFINE_LONGS(HOST_R13, R13);
        DEFINE_LONGS(HOST_R14, R14);
        DEFINE_LONGS(HOST_R15, R15);
-        DEFINE_LONGS(HOST_ORIG_RAX, ORIG_RAX);
+        DEFINE_LONGS(HOST_ORIG_AX, ORIG_RAX);
        DEFINE_LONGS(HOST_CS, CS);
        DEFINE_LONGS(HOST_SS, SS);
        DEFINE_LONGS(HOST_EFLAGS, EFLAGS);
@@ -52,9 +67,9 @@ void foo(void)
        DEFINE_LONGS(HOST_IP, RIP);
        DEFINE_LONGS(HOST_SP, RSP);
-        DEFINE(UM_FRAME_SIZE, sizeof(struct user_regs_struct));
+#endif
-        /* XXX Duplicated between i386 and x86_64 */
+        DEFINE(UM_FRAME_SIZE, sizeof(struct user_regs_struct));
        DEFINE(UM_POLLIN, POLLIN);
        DEFINE(UM_POLLPRI, POLLPRI);
        DEFINE(UM_POLLOUT, POLLOUT);
diff --git a/arch/um/sys-x86_64/vdso/Makefile b/arch/x86/um/vdso/Makefile
index 5dffe6d46686..6c803ca49b5d 100644
--- a/arch/um/sys-x86_64/vdso/Makefile
+++ b/arch/x86/um/vdso/Makefile
@@ -46,8 +46,8 @@ $(vobjs): KBUILD_CFLAGS += $(CFL)
 #
 # vDSO code runs in userspace and -pg doesn't help with profiling anyway.
 #
-CFLAGS_REMOVE_vdso-note.o = -pg
+CFLAGS_REMOVE_vdso-note.o = -pg -fprofile-arcs -ftest-coverage
-CFLAGS_REMOVE_um_vdso.o = -pg
+CFLAGS_REMOVE_um_vdso.o = -pg -fprofile-arcs -ftest-coverage
 targets += vdso-syms.lds
 obj-$(VDSO64-y)                 += vdso-syms.lds
diff --git a/arch/um/sys-x86_64/vdso/checkundef.sh b/arch/x86/um/vdso/checkundef.sh
index 7ee90a9b549d..7ee90a9b549d 100644
--- a/arch/um/sys-x86_64/vdso/checkundef.sh
+++ b/arch/x86/um/vdso/checkundef.sh
diff --git a/arch/um/sys-x86_64/vdso/um_vdso.c b/arch/x86/um/vdso/um_vdso.c
index 7c441b59d375..7c441b59d375 100644
--- a/arch/um/sys-x86_64/vdso/um_vdso.c
+++ b/arch/x86/um/vdso/um_vdso.c
diff --git a/arch/um/sys-x86_64/vdso/vdso-layout.lds.S b/arch/x86/um/vdso/vdso-layout.lds.S
index 634a2cf62046..634a2cf62046 100644
--- a/arch/um/sys-x86_64/vdso/vdso-layout.lds.S
+++ b/arch/x86/um/vdso/vdso-layout.lds.S
diff --git a/arch/um/sys-x86_64/vdso/vdso-note.S b/arch/x86/um/vdso/vdso-note.S
index 79a071e4357e..79a071e4357e 100644
--- a/arch/um/sys-x86_64/vdso/vdso-note.S
+++ b/arch/x86/um/vdso/vdso-note.S
diff --git a/arch/um/sys-x86_64/vdso/vdso.S b/arch/x86/um/vdso/vdso.S
index ec82c1686bd6..1cb468adacbb 100644
--- a/arch/um/sys-x86_64/vdso/vdso.S
+++ b/arch/x86/um/vdso/vdso.S
@@ -4,7 +4,7 @@ __INITDATA
        .globl vdso_start, vdso_end
 vdso_start:
-        .incbin "arch/um/sys-x86_64/vdso/vdso.so"
+        .incbin "arch/x86/um/vdso/vdso.so"
 vdso_end:
 __FINIT
diff --git a/arch/um/sys-x86_64/vdso/vdso.lds.S b/arch/x86/um/vdso/vdso.lds.S
index b96b2677cad8..b96b2677cad8 100644
--- a/arch/um/sys-x86_64/vdso/vdso.lds.S
+++ b/arch/x86/um/vdso/vdso.lds.S
diff --git a/arch/um/sys-x86_64/vdso/vma.c b/arch/x86/um/vdso/vma.c
index 9495c8d0ce37..91f4ec9a0a56 100644
--- a/arch/um/sys-x86_64/vdso/vma.c
+++ b/arch/x86/um/vdso/vma.c
@@ -28,7 +28,7 @@ static int __init init_vdso(void)
        um_vdso_addr = task_size - PAGE_SIZE;
-        vdsop = kmalloc(GFP_KERNEL, sizeof(struct page *));
+        vdsop = kmalloc(sizeof(struct page *), GFP_KERNEL);
        if (!vdsop)
                goto oom;
diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
index 423fd56bf612..43643033a3ae 100644
--- a/drivers/char/Kconfig
+++ b/drivers/char/Kconfig
@@ -298,7 +298,7 @@ if RTC_LIB=n
 config RTC
        tristate "Enhanced Real Time Clock Support (legacy PC RTC driver)"
        depends on !PPC && !PARISC && !IA64 && !M68K && !SPARC && !FRV \
-                        && !ARM && !SUPERH && !S390 && !AVR32 && !BLACKFIN
+                        && !ARM && !SUPERH && !S390 && !AVR32 && !BLACKFIN && !UML
        ---help---
          If you say Y here and create a character special file /dev/rtc with
          major number 10 and minor number 135 using mknod ("man mknod"), you
@@ -346,7 +346,7 @@ config JS_RTC
 config GEN_RTC
        tristate "Generic /dev/rtc emulation"
-        depends on RTC!=y && !IA64 && !ARM && !M32R && !MIPS && !SPARC && !FRV && !S390 && !SUPERH && !AVR32 && !BLACKFIN
+        depends on RTC!=y && !IA64 && !ARM && !M32R && !MIPS && !SPARC && !FRV && !S390 && !SUPERH && !AVR32 && !BLACKFIN && !UML
        ---help---
          If you say Y here and create a character special file /dev/rtc with
          major number 10 and minor number 135 using mknod ("man mknod"), you
@@ -490,7 +490,7 @@ config SCx200_GPIO
 config PC8736x_GPIO
        tristate "NatSemi PC8736x GPIO Support"
-        depends on X86_32
+        depends on X86_32 && !UML
        default SCx200_GPIO     # mostly N
        select NSC_GPIO         # needed for support routines
        help
diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
index 1d2ebc7a4947..0689bf6b0183 100644
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
@@ -60,6 +60,19 @@ config HW_RANDOM_AMD
          If unsure, say Y.
+config HW_RANDOM_ATMEL
+        tristate "Atmel Random Number Generator support"
+        depends on HW_RANDOM && ARCH_AT91SAM9G45
+        default HW_RANDOM
+        ---help---
+          This driver provides kernel-side support for the Random Number
+          Generator hardware found on Atmel AT91 devices.
+          To compile this driver as a module, choose M here: the
+          module will be called atmel-rng.
+          If unsure, say Y.
 config HW_RANDOM_GEODE
        tristate "AMD Geode HW Random Number Generator support"
        depends on HW_RANDOM && X86_32 && PCI
@@ -222,3 +235,18 @@ config HW_RANDOM_PPC4XX
         module will be called ppc4xx-rng.
         If unsure, say N.
+config UML_RANDOM
+        depends on UML
+        tristate "Hardware random number generator"
+        help
+          This option enables UML's "hardware" random number generator.  It
+          attaches itself to the host's /dev/random, supplying as much entropy
+          as the host has, rather than the small amount the UML gets from its
+          own drivers.  It registers itself as a standard hardware random number
+          generator, major 10, minor 183, and the canonical device name is
+          /dev/hwrng.
+          The way to make use of this is to install the rng-tools package
+          (check your distro, or download from
+          http://sourceforge.net/projects/gkernel/).  rngd periodically reads
+          /dev/hwrng and injects the entropy into /dev/random.
diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
index c88f244c8a71..b2ff5265a996 100644
--- a/drivers/char/hw_random/Makefile
+++ b/drivers/char/hw_random/Makefile
@@ -7,6 +7,7 @@ rng-core-y := core.o
 obj-$(CONFIG_HW_RANDOM_TIMERIOMEM) += timeriomem-rng.o
 obj-$(CONFIG_HW_RANDOM_INTEL) += intel-rng.o
 obj-$(CONFIG_HW_RANDOM_AMD) += amd-rng.o
+obj-$(CONFIG_HW_RANDOM_ATMEL) += atmel-rng.o
 obj-$(CONFIG_HW_RANDOM_GEODE) += geode-rng.o
 obj-$(CONFIG_HW_RANDOM_N2RNG) += n2-rng.o
 n2-rng-y := n2-drv.o n2-asm.o
diff --git a/drivers/char/hw_random/atmel-rng.c b/drivers/char/hw_random/atmel-rng.c
new file mode 100644
index 000000000000..241df2e76aba
--- /dev/null
+++ b/drivers/char/hw_random/atmel-rng.c
@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2011 Peter Korsgaard <jacmet@sunsite.dk>
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/hw_random.h>
+#include <linux/platform_device.h>
+#define TRNG_CR         0x00
+#define TRNG_ISR        0x1c
+#define TRNG_ODATA      0x50
+#define TRNG_KEY        0x524e4700 /* RNG */
+struct atmel_trng {
+        struct clk *clk;
+        void __iomem *base;
+        struct hwrng rng;
+};
+static int atmel_trng_read(struct hwrng *rng, void *buf, size_t max,
+                           bool wait)
+{
+        struct atmel_trng *trng = container_of(rng, struct atmel_trng, rng);
+        u32 *data = buf;
+        /* data ready? */
+        if (readl(trng->base + TRNG_ODATA) & 1) {
+                *data = readl(trng->base + TRNG_ODATA);
+                return 4;
+        } else
+                return 0;
+}
+static int atmel_trng_probe(struct platform_device *pdev)
+{
+        struct atmel_trng *trng;
+        struct resource *res;
+        int ret;
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res)
+                return -EINVAL;
+        trng = devm_kzalloc(&pdev->dev, sizeof(*trng), GFP_KERNEL);
+        if (!trng)
+                return -ENOMEM;
+        if (!devm_request_mem_region(&pdev->dev, res->start,
+                                     resource_size(res), pdev->name))
+                return -EBUSY;
+        trng->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+        if (!trng->base)
+                return -EBUSY;
+        trng->clk = clk_get(&pdev->dev, NULL);
+        if (IS_ERR(trng->clk))
+                return PTR_ERR(trng->clk);
+        ret = clk_enable(trng->clk);
+        if (ret)
+                goto err_enable;
+        writel(TRNG_KEY | 1, trng->base + TRNG_CR);
+        trng->rng.name = pdev->name;
+        trng->rng.read = atmel_trng_read;
+        ret = hwrng_register(&trng->rng);
+        if (ret)
+                goto err_register;
+        platform_set_drvdata(pdev, trng);
+        return 0;
+err_register:
+        clk_disable(trng->clk);
+err_enable:
+        clk_put(trng->clk);
+        return ret;
+}
+static int __devexit atmel_trng_remove(struct platform_device *pdev)
+{
+        struct atmel_trng *trng = platform_get_drvdata(pdev);
+        hwrng_unregister(&trng->rng);
+        writel(TRNG_KEY, trng->base + TRNG_CR);
+        clk_disable(trng->clk);
+        clk_put(trng->clk);
+        platform_set_drvdata(pdev, NULL);
+        return 0;
+}
+#ifdef CONFIG_PM
+static int atmel_trng_suspend(struct device *dev)
+{
+        struct atmel_trng *trng = dev_get_drvdata(dev);
+        clk_disable(trng->clk);
+        return 0;
+}
+static int atmel_trng_resume(struct device *dev)
+{
+        struct atmel_trng *trng = dev_get_drvdata(dev);
+        return clk_enable(trng->clk);
+}
+static const struct dev_pm_ops atmel_trng_pm_ops = {
+        .suspend        = atmel_trng_suspend,
+        .resume         = atmel_trng_resume,
+};
+#endif /* CONFIG_PM */
+static struct platform_driver atmel_trng_driver = {
+        .probe          = atmel_trng_probe,
+        .remove         = __devexit_p(atmel_trng_remove),
+        .driver         = {
+                .name   = "atmel-trng",
+                .owner  = THIS_MODULE,
+#ifdef CONFIG_PM
+                .pm     = &atmel_trng_pm_ops,
+#endif /* CONFIG_PM */
+        },
+};
+static int __init atmel_trng_init(void)
+{
+        return platform_driver_register(&atmel_trng_driver);
+}
+module_init(atmel_trng_init);
+static void __exit atmel_trng_exit(void)
+{
+        platform_driver_unregister(&atmel_trng_driver);
+}
+module_exit(atmel_trng_exit);
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
+MODULE_DESCRIPTION("Atmel true random number generator driver");
diff --git a/drivers/char/ttyprintk.c b/drivers/char/ttyprintk.c
index a1f68af4ccf4..f22861511909 100644
--- a/drivers/char/ttyprintk.c
+++ b/drivers/char/ttyprintk.c
@@ -170,7 +170,7 @@ static const struct tty_operations ttyprintk_ops = {
        .ioctl = tpk_ioctl,
 };
-struct tty_port_operations null_ops = { };
+static struct tty_port_operations null_ops = { };
 static struct tty_driver *ttyprintk_driver;
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 34e9c4f88926..999d6a03e436 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -15,3 +15,18 @@ config CLKSRC_MMIO
 config DW_APB_TIMER
        bool
+config CLKSRC_DBX500_PRCMU
+        bool "Clocksource PRCMU Timer"
+        depends on UX500_SOC_DB5500 || UX500_SOC_DB8500
+        default y
+        help
+          Use the always on PRCMU Timer as clocksource
+config CLKSRC_DBX500_PRCMU_SCHED_CLOCK
+        bool "Clocksource PRCMU Timer sched_clock"
+        depends on (CLKSRC_DBX500_PRCMU && !NOMADIK_MTU_SCHED_CLOCK)
+        select HAVE_SCHED_CLOCK
+        default y
+        help
+          Use the always on PRCMU Timer as sched_clock
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 85ad1646a7b7..8d81a1d32653 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_SH_TIMER_TMU)	+= sh_tmu.o
 obj-$(CONFIG_CLKBLD_I8253)      += i8253.o
 obj-$(CONFIG_CLKSRC_MMIO)       += mmio.o
 obj-$(CONFIG_DW_APB_TIMER)      += dw_apb_timer.o
+obj-$(CONFIG_CLKSRC_DBX500_PRCMU)       += clksrc-dbx500-prcmu.o
+\ No newline at end of file
diff --git a/drivers/clocksource/clksrc-dbx500-prcmu.c b/drivers/clocksource/clksrc-dbx500-prcmu.c
new file mode 100644
index 000000000000..59feefe0e3e6
--- /dev/null
+++ b/drivers/clocksource/clksrc-dbx500-prcmu.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2011
+ *
+ * License Terms: GNU General Public License v2
+ * Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson
+ * Author: Sundar Iyer for ST-Ericsson
+ * sched_clock implementation is based on:
+ * plat-nomadik/timer.c Linus Walleij <linus.walleij@stericsson.com>
+ *
+ * DBx500-PRCMU Timer
+ * The PRCMU has 5 timers which are available in a always-on
+ * power domain.  We use the Timer 4 for our always-on clock
+ * source on DB8500 and Timer 3 on DB5500.
+ */
+#include <linux/clockchips.h>
+#include <linux/clksrc-dbx500-prcmu.h>
+#include <asm/sched_clock.h>
+#include <mach/setup.h>
+#include <mach/hardware.h>
+#define RATE_32K                32768
+#define TIMER_MODE_CONTINOUS    0x1
+#define TIMER_DOWNCOUNT_VAL     0xffffffff
+#define PRCMU_TIMER_REF         0
+#define PRCMU_TIMER_DOWNCOUNT   0x4
+#define PRCMU_TIMER_MODE        0x8
+#define SCHED_CLOCK_MIN_WRAP 131072 /* 2^32 / 32768 */
+static void __iomem *clksrc_dbx500_timer_base;
+static cycle_t clksrc_dbx500_prcmu_read(struct clocksource *cs)
+{
+        u32 count, count2;
+        do {
+                count = readl(clksrc_dbx500_timer_base +
+                              PRCMU_TIMER_DOWNCOUNT);
+                count2 = readl(clksrc_dbx500_timer_base +
+                               PRCMU_TIMER_DOWNCOUNT);
+        } while (count2 != count);
+        /* Negate because the timer is a decrementing counter */
+        return ~count;
+}
+static struct clocksource clocksource_dbx500_prcmu = {
+        .name           = "dbx500-prcmu-timer",
+        .rating         = 300,
+        .read           = clksrc_dbx500_prcmu_read,
+        .shift          = 10,
+        .mask           = CLOCKSOURCE_MASK(32),
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+#ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK
+static DEFINE_CLOCK_DATA(cd);
+unsigned long long notrace sched_clock(void)
+{
+        u32 cyc;
+        if (unlikely(!clksrc_dbx500_timer_base))
+                return 0;
+        cyc = clksrc_dbx500_prcmu_read(&clocksource_dbx500_prcmu);
+        return cyc_to_sched_clock(&cd, cyc, (u32)~0);
+}
+static void notrace clksrc_dbx500_prcmu_update_sched_clock(void)
+{
+        u32 cyc = clksrc_dbx500_prcmu_read(&clocksource_dbx500_prcmu);
+        update_sched_clock(&cd, cyc, (u32)~0);
+}
+#endif
+void __init clksrc_dbx500_prcmu_init(void __iomem *base)
+{
+        clksrc_dbx500_timer_base = base;
+        /*
+         * The A9 sub system expects the timer to be configured as
+         * a continous looping timer.
+         * The PRCMU should configure it but if it for some reason
+         * don't we do it here.
+         */
+        if (readl(clksrc_dbx500_timer_base + PRCMU_TIMER_MODE) !=
+            TIMER_MODE_CONTINOUS) {
+                writel(TIMER_MODE_CONTINOUS,
+                       clksrc_dbx500_timer_base + PRCMU_TIMER_MODE);
+                writel(TIMER_DOWNCOUNT_VAL,
+                       clksrc_dbx500_timer_base + PRCMU_TIMER_REF);
+        }
+#ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK
+        init_sched_clock(&cd, clksrc_dbx500_prcmu_update_sched_clock,
+                         32, RATE_32K);
+#endif
+        clocksource_calc_mult_shift(&clocksource_dbx500_prcmu,
+                                    RATE_32K, SCHED_CLOCK_MIN_WRAP);
+        clocksource_register(&clocksource_dbx500_prcmu);
+}
diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c
index 82f7b65baf72..b81c98992114 100644
--- a/drivers/gpio/gpio-mxc.c
+++ b/drivers/gpio/gpio-mxc.c
@@ -32,6 +32,8 @@
 #include <asm-generic/bug.h>
 #include <asm/mach/irq.h>
+#define irq_to_gpio(irq)        ((irq) - MXC_GPIO_IRQ_START)
 enum mxc_gpio_hwtype {
        IMX1_GPIO,      /* runs on i.mx1 */
        IMX21_GPIO,     /* runs on i.mx21 and i.mx27 */
@@ -343,6 +345,15 @@ static void __devinit mxc_gpio_get_hw(struct platform_device *pdev)
        mxc_gpio_hwtype = hwtype;
 }
+static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
+{
+        struct bgpio_chip *bgc = to_bgpio_chip(gc);
+        struct mxc_gpio_port *port =
+                container_of(bgc, struct mxc_gpio_port, bgc);
+        return port->virtual_irq_start + offset;
+}
 static int __devinit mxc_gpio_probe(struct platform_device *pdev)
 {
        struct device_node *np = pdev->dev.of_node;
@@ -409,6 +420,7 @@ static int __devinit mxc_gpio_probe(struct platform_device *pdev)
        if (err)
                goto out_iounmap;
+        port->bgc.gc.to_irq = mxc_gpio_to_irq;
        port->bgc.gc.base = pdev->id * 32;
        port->bgc.dir = port->bgc.read_reg(port->bgc.reg_dir);
        port->bgc.data = port->bgc.read_reg(port->bgc.reg_set);
diff --git a/drivers/gpio/gpio-mxs.c b/drivers/gpio/gpio-mxs.c
index af55a8577c2e..292b50481db9 100644
--- a/drivers/gpio/gpio-mxs.c
+++ b/drivers/gpio/gpio-mxs.c
@@ -49,6 +49,8 @@
 #define GPIO_INT_LEV_MASK       (1 << 0)
 #define GPIO_INT_POL_MASK       (1 << 1)
+#define irq_to_gpio(irq)        ((irq) - MXS_GPIO_IRQ_START)
 struct mxs_gpio_port {
        void __iomem *base;
        int id;
diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
index 9052925c6fa2..ee137712f9db 100644
--- a/drivers/gpio/gpio-pxa.c
+++ b/drivers/gpio/gpio-pxa.c
@@ -122,7 +122,7 @@ static int __init pxa_init_gpio_chip(int gpio_end)
                struct gpio_chip *c = &chips[i].chip;
                sprintf(chips[i].label, "gpio-%d", i);
-                chips[i].regbase = (void __iomem *)GPIO_BANK(i);
+                chips[i].regbase = GPIO_BANK(i);
                c->base  = gpio;
                c->label = chips[i].label;
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index 6b65207c8106..61044c889f7f 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -20,10 +20,11 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
 #include <asm/mach/irq.h>
@@ -35,9 +36,7 @@
 #define GPIO_PORT(x)            (((x) >> 3) & 0x3)
 #define GPIO_BIT(x)             ((x) & 0x7)
-#define GPIO_REG(x)             (IO_TO_VIRT(TEGRA_GPIO_BASE) +  \
+#define GPIO_REG(x)             (GPIO_BANK(x) * 0x80 + GPIO_PORT(x) * 4)
-                                 GPIO_BANK(x) * 0x80 +          \
-                                 GPIO_PORT(x) * 4)
 #define GPIO_CNF(x)             (GPIO_REG(x) + 0x00)
 #define GPIO_OE(x)              (GPIO_REG(x) + 0x10)
@@ -76,15 +75,18 @@ struct tegra_gpio_bank {
 };
-static struct tegra_gpio_bank tegra_gpio_banks[] = {
+static void __iomem *regs;
-        {.bank = 0, .irq = INT_GPIO1},
+static struct tegra_gpio_bank tegra_gpio_banks[7];
-        {.bank = 1, .irq = INT_GPIO2},
-        {.bank = 2, .irq = INT_GPIO3},
+static inline void tegra_gpio_writel(u32 val, u32 reg)
-        {.bank = 3, .irq = INT_GPIO4},
+{
-        {.bank = 4, .irq = INT_GPIO5},
+        __raw_writel(val, regs + reg);
-        {.bank = 5, .irq = INT_GPIO6},
+}
-        {.bank = 6, .irq = INT_GPIO7},
-};
+static inline u32 tegra_gpio_readl(u32 reg)
+{
+        return __raw_readl(regs + reg);
+}
 static int tegra_gpio_compose(int bank, int port, int bit)
 {
@@ -98,7 +100,7 @@ static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
        val = 0x100 << GPIO_BIT(gpio);
        if (value)
                val |= 1 << GPIO_BIT(gpio);
-        __raw_writel(val, reg);
+        tegra_gpio_writel(val, reg);
 }
 void tegra_gpio_enable(int gpio)
@@ -118,7 +120,7 @@ static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
 {
-        return (__raw_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
+        return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
 }
 static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
@@ -155,7 +157,7 @@ static void tegra_gpio_irq_ack(struct irq_data *d)
 {
        int gpio = d->irq - INT_GPIO_BASE;
-        __raw_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
+        tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
 }
 static void tegra_gpio_irq_mask(struct irq_data *d)
@@ -208,10 +210,10 @@ static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
        spin_lock_irqsave(&bank->lvl_lock[port], flags);
-        val = __raw_readl(GPIO_INT_LVL(gpio));
+        val = tegra_gpio_readl(GPIO_INT_LVL(gpio));
        val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
        val |= lvl_type << GPIO_BIT(gpio);
-        __raw_writel(val, GPIO_INT_LVL(gpio));
+        tegra_gpio_writel(val, GPIO_INT_LVL(gpio));
        spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
@@ -237,12 +239,12 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
        for (port = 0; port < 4; port++) {
                int gpio = tegra_gpio_compose(bank->bank, port, 0);
-                unsigned long sta = __raw_readl(GPIO_INT_STA(gpio)) &
+                unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) &
-                        __raw_readl(GPIO_INT_ENB(gpio));
+                        tegra_gpio_readl(GPIO_INT_ENB(gpio));
-                u32 lvl = __raw_readl(GPIO_INT_LVL(gpio));
+                u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio));
                for_each_set_bit(pin, &sta, 8) {
-                        __raw_writel(1 << pin, GPIO_INT_CLR(gpio));
+                        tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio));
                        /* if gpio is edge triggered, clear condition
                         * before executing the hander so that we don't
@@ -276,11 +278,11 @@ void tegra_gpio_resume(void)
                for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
                        unsigned int gpio = (b<<5) | (p<<3);
-                        __raw_writel(bank->cnf[p], GPIO_CNF(gpio));
+                        tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio));
-                        __raw_writel(bank->out[p], GPIO_OUT(gpio));
+                        tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio));
-                        __raw_writel(bank->oe[p], GPIO_OE(gpio));
+                        tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio));
-                        __raw_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
+                        tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
-                        __raw_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
+                        tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
                }
        }
@@ -299,11 +301,11 @@ void tegra_gpio_suspend(void)
                for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
                        unsigned int gpio = (b<<5) | (p<<3);
-                        bank->cnf[p] = __raw_readl(GPIO_CNF(gpio));
+                        bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio));
-                        bank->out[p] = __raw_readl(GPIO_OUT(gpio));
+                        bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio));
-                        bank->oe[p] = __raw_readl(GPIO_OE(gpio));
+                        bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
-                        bank->int_enb[p] = __raw_readl(GPIO_INT_ENB(gpio));
+                        bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
-                        bank->int_lvl[p] = __raw_readl(GPIO_INT_LVL(gpio));
+                        bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));
                }
        }
        local_irq_restore(flags);
@@ -333,28 +335,55 @@ static struct irq_chip tegra_gpio_irq_chip = {
 */
 static struct lock_class_key gpio_lock_class;
-static int __init tegra_gpio_init(void)
+static int __devinit tegra_gpio_probe(struct platform_device *pdev)
 {
+        struct resource *res;
        struct tegra_gpio_bank *bank;
        int gpio;
        int i;
        int j;
+        for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
+                res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
+                if (!res) {
+                        dev_err(&pdev->dev, "Missing IRQ resource\n");
+                        return -ENODEV;
+                }
+                bank = &tegra_gpio_banks[i];
+                bank->bank = i;
+                bank->irq = res->start;
+        }
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                dev_err(&pdev->dev, "Missing MEM resource\n");
+                return -ENODEV;
+        }
+        if (!devm_request_mem_region(&pdev->dev, res->start,
+                                     resource_size(res),
+                                     dev_name(&pdev->dev))) {
+                dev_err(&pdev->dev, "Couldn't request MEM resource\n");
+                return -ENODEV;
+        }
+        regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+        if (!regs) {
+                dev_err(&pdev->dev, "Couldn't ioremap regs\n");
+                return -ENODEV;
+        }
        for (i = 0; i < 7; i++) {
                for (j = 0; j < 4; j++) {
                        int gpio = tegra_gpio_compose(i, j, 0);
-                        __raw_writel(0x00, GPIO_INT_ENB(gpio));
+                        tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio));
                }
        }
 #ifdef CONFIG_OF_GPIO
-        /*
+        tegra_gpio_chip.of_node = pdev->dev.of_node;
-         * This isn't ideal, but it gets things hooked up until this
+#endif
-         * driver is converted into a platform_device
-         */
-        tegra_gpio_chip.of_node = of_find_compatible_node(NULL, NULL,
-                                                "nvidia,tegra20-gpio");
-#endif /* CONFIG_OF_GPIO */
        gpiochip_add(&tegra_gpio_chip);
@@ -384,6 +413,24 @@ static int __init tegra_gpio_init(void)
        return 0;
 }
+static struct of_device_id tegra_gpio_of_match[] __devinitdata = {
+        { .compatible = "nvidia,tegra20-gpio", },
+        { },
+};
+static struct platform_driver tegra_gpio_driver = {
+        .driver         = {
+                .name   = "tegra-gpio",
+                .owner  = THIS_MODULE,
+                .of_match_table = tegra_gpio_of_match,
+        },
+        .probe          = tegra_gpio_probe,
+};
+static int __init tegra_gpio_init(void)
+{
+        return platform_driver_register(&tegra_gpio_driver);
+}
 postcore_initcall(tegra_gpio_init);
 void __init tegra_gpio_config(struct tegra_gpio_table *table, int num)
@@ -416,13 +463,13 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
                        seq_printf(s,
                                "%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
                                i, j,
-                                __raw_readl(GPIO_CNF(gpio)),
+                                tegra_gpio_readl(GPIO_CNF(gpio)),
-                                __raw_readl(GPIO_OE(gpio)),
+                                tegra_gpio_readl(GPIO_OE(gpio)),
-                                __raw_readl(GPIO_OUT(gpio)),
+                                tegra_gpio_readl(GPIO_OUT(gpio)),
-                                __raw_readl(GPIO_IN(gpio)),
+                                tegra_gpio_readl(GPIO_IN(gpio)),
-                                __raw_readl(GPIO_INT_STA(gpio)),
+                                tegra_gpio_readl(GPIO_INT_STA(gpio)),
-                                __raw_readl(GPIO_INT_ENB(gpio)),
+                                tegra_gpio_readl(GPIO_INT_ENB(gpio)),
-                                __raw_readl(GPIO_INT_LVL(gpio)));
+                                tegra_gpio_readl(GPIO_INT_LVL(gpio)));
                }
        }
        return 0;
diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig
index 23e82e46656d..001b147c7f95 100644
--- a/drivers/input/Kconfig
+++ b/drivers/input/Kconfig
@@ -3,7 +3,7 @@
 #
 menu "Input device support"
-        depends on !S390
+        depends on !S390 && !UML
 config INPUT
        tristate "Generic input layer (needed for keyboard, mouse, ...)" if EXPERT
diff --git a/drivers/isdn/Kconfig b/drivers/isdn/Kconfig
index 4fb601670de3..a233ed53913a 100644
--- a/drivers/isdn/Kconfig
+++ b/drivers/isdn/Kconfig
@@ -5,7 +5,7 @@
 menuconfig ISDN
        bool "ISDN support"
        depends on NET
-        depends on !S390
+        depends on !S390 && !UML
        ---help---
          ISDN ("Integrated Services Digital Network", called RNIS in France)
          is a fully digital telephone service that can be used for voice and
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 50d5f27f09d0..d593878d66d0 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -63,7 +63,7 @@ config AD525X_DPOT_SPI
 config ATMEL_PWM
        tristate "Atmel AT32/AT91 PWM support"
-        depends on AVR32 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9
+        depends on HAVE_CLK
        help
          This option enables device driver support for the PWM channels
          on certain Atmel processors.  Pulse Width Modulation is used for
diff --git a/drivers/mmc/host/davinci_mmc.c b/drivers/mmc/host/davinci_mmc.c
index 0076c7448fe6..64a8325a4a8a 100644
--- a/drivers/mmc/host/davinci_mmc.c
+++ b/drivers/mmc/host/davinci_mmc.c
@@ -807,12 +807,25 @@ static void calculate_clk_divider(struct mmc_host *mmc, struct mmc_ios *ios)
 static void mmc_davinci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 {
        struct mmc_davinci_host *host = mmc_priv(mmc);
+        struct platform_device *pdev = to_platform_device(mmc->parent);
+        struct davinci_mmc_config *config = pdev->dev.platform_data;
        dev_dbg(mmc_dev(host->mmc),
                "clock %dHz busmode %d powermode %d Vdd %04x\n",
                ios->clock, ios->bus_mode, ios->power_mode,
                ios->vdd);
+        switch (ios->power_mode) {
+        case MMC_POWER_OFF:
+                if (config && config->set_power)
+                        config->set_power(pdev->id, false);
+                break;
+        case MMC_POWER_UP:
+                if (config && config->set_power)
+                        config->set_power(pdev->id, true);
+                break;
+        }
        switch (ios->bus_width) {
        case MMC_BUS_WIDTH_8:
                dev_dbg(mmc_dev(host->mmc), "Enabling 8 bit mode\n");
diff --git a/drivers/mmc/host/mxcmmc.c b/drivers/mmc/host/mxcmmc.c
index f48743de4673..325ea61e12d3 100644
--- a/drivers/mmc/host/mxcmmc.c
+++ b/drivers/mmc/host/mxcmmc.c
@@ -40,6 +40,7 @@
 #include <mach/mmc.h>
 #include <mach/dma.h>
+#include <mach/hardware.h>
 #define DRIVER_NAME "mxc-mmc"
diff --git a/drivers/mtd/mtdchar.c b/drivers/mtd/mtdchar.c
index f1af2228a1b1..61086ea3cc6b 100644
--- a/drivers/mtd/mtdchar.c
+++ b/drivers/mtd/mtdchar.c
@@ -1144,7 +1144,7 @@ static void mtdchar_notify_remove(struct mtd_info *mtd)
        if (mtd_ino) {
                /* Destroy the inode if it exists */
-                mtd_ino->i_nlink = 0;
+                clear_nlink(mtd_ino);
                iput(mtd_ino);
        }
 }
diff --git a/drivers/net/wireless/ath/Kconfig b/drivers/net/wireless/ath/Kconfig
index 073548836413..09602241901b 100644
--- a/drivers/net/wireless/ath/Kconfig
+++ b/drivers/net/wireless/ath/Kconfig
@@ -1,6 +1,6 @@
 menuconfig ATH_COMMON
        tristate "Atheros Wireless Cards"
-        depends on CFG80211
+        depends on CFG80211 && (!UML || BROKEN)
        ---help---
          This will enable the support for the Atheros wireless drivers.
          ath5k, ath9k, ath9k_htc and ar9170 drivers share some common code, this option
diff --git a/drivers/net/wireless/rtlwifi/Kconfig b/drivers/net/wireless/rtlwifi/Kconfig
index 45e14760c16e..d6c42e69bdbd 100644
--- a/drivers/net/wireless/rtlwifi/Kconfig
+++ b/drivers/net/wireless/rtlwifi/Kconfig
@@ -12,7 +12,7 @@ config RTL8192CE
 config RTL8192SE
        tristate "Realtek RTL8192SE/RTL8191SE PCIe Wireless Network Adapter"
-        depends on MAC80211 && EXPERIMENTAL
+        depends on MAC80211 && EXPERIMENTAL && PCI
        select FW_LOADER
        select RTLWIFI
        ---help---
@@ -23,7 +23,7 @@ config RTL8192SE
 config RTL8192DE
        tristate "Realtek RTL8192DE/RTL8188DE PCIe Wireless Network Adapter"
-        depends on MAC80211 && EXPERIMENTAL
+        depends on MAC80211 && EXPERIMENTAL && PCI
        select FW_LOADER
        select RTLWIFI
        ---help---
diff --git a/drivers/of/base.c b/drivers/of/base.c
index b970562e0111..9b6588ef0673 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -716,6 +716,90 @@ int of_property_read_string(struct device_node *np, const char *propname,
 EXPORT_SYMBOL_GPL(of_property_read_string);
 /**
+ * of_property_read_string_index - Find and read a string from a multiple
+ * strings property.
+ * @np:         device node from which the property value is to be read.
+ * @propname:   name of the property to be searched.
+ * @index:      index of the string in the list of strings
+ * @out_string: pointer to null terminated return string, modified only if
+ *              return value is 0.
+ *
+ * Search for a property in a device tree node and retrieve a null
+ * terminated string value (pointer to data, not a copy) in the list of strings
+ * contained in that property.
+ * Returns 0 on success, -EINVAL if the property does not exist, -ENODATA if
+ * property does not have a value, and -EILSEQ if the string is not
+ * null-terminated within the length of the property data.
+ *
+ * The out_string pointer is modified only if a valid string can be decoded.
+ */
+int of_property_read_string_index(struct device_node *np, const char *propname,
+                                  int index, const char **output)
+{
+        struct property *prop = of_find_property(np, propname, NULL);
+        int i = 0;
+        size_t l = 0, total = 0;
+        const char *p;
+        if (!prop)
+                return -EINVAL;
+        if (!prop->value)
+                return -ENODATA;
+        if (strnlen(prop->value, prop->length) >= prop->length)
+                return -EILSEQ;
+        p = prop->value;
+        for (i = 0; total < prop->length; total += l, p += l) {
+                l = strlen(p) + 1;
+                if ((*p != 0) && (i++ == index)) {
+                        *output = p;
+                        return 0;
+                }
+        }
+        return -ENODATA;
+}
+EXPORT_SYMBOL_GPL(of_property_read_string_index);
+/**
+ * of_property_count_strings - Find and return the number of strings from a
+ * multiple strings property.
+ * @np:         device node from which the property value is to be read.
+ * @propname:   name of the property to be searched.
+ *
+ * Search for a property in a device tree node and retrieve the number of null
+ * terminated string contain in it. Returns the number of strings on
+ * success, -EINVAL if the property does not exist, -ENODATA if property
+ * does not have a value, and -EILSEQ if the string is not null-terminated
+ * within the length of the property data.
+ */
+int of_property_count_strings(struct device_node *np, const char *propname)
+{
+        struct property *prop = of_find_property(np, propname, NULL);
+        int i = 0;
+        size_t l = 0, total = 0;
+        const char *p;
+        if (!prop)
+                return -EINVAL;
+        if (!prop->value)
+                return -ENODATA;
+        if (strnlen(prop->value, prop->length) >= prop->length)
+                return -EILSEQ;
+        p = prop->value;
+        for (i = 0; total < prop->length; total += l, p += l) {
+                l = strlen(p) + 1;
+                if (*p != 0)
+                        i++;
+        }
+        return i;
+}
+EXPORT_SYMBOL_GPL(of_property_count_strings);
+/**
 * of_parse_phandle - Resolve a phandle property to a device_node pointer
 * @np: Pointer to device node holding phandle property
 * @phandle_name: Name of property holding a phandle value
diff --git a/drivers/of/irq.c b/drivers/of/irq.c
index 6a5b5e777dd2..6d3dd3988d0f 100644
--- a/drivers/of/irq.c
+++ b/drivers/of/irq.c
@@ -19,10 +19,12 @@
 */
 #include <linux/errno.h>
+#include <linux/list.h>
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/of_irq.h>
 #include <linux/string.h>
+#include <linux/slab.h>
 /* For archs that don't support NO_IRQ (such as x86), provide a dummy value */
 #ifndef NO_IRQ
@@ -386,3 +388,108 @@ int of_irq_to_resource_table(struct device_node *dev, struct resource *res,
        return i;
 }
+struct intc_desc {
+        struct list_head        list;
+        struct device_node      *dev;
+        struct device_node      *interrupt_parent;
+};
+/**
+ * of_irq_init - Scan and init matching interrupt controllers in DT
+ * @matches: 0 terminated array of nodes to match and init function to call
+ *
+ * This function scans the device tree for matching interrupt controller nodes,
+ * and calls their initialization functions in order with parents first.
+ */
+void __init of_irq_init(const struct of_device_id *matches)
+{
+        struct device_node *np, *parent = NULL;
+        struct intc_desc *desc, *temp_desc;
+        struct list_head intc_desc_list, intc_parent_list;
+        INIT_LIST_HEAD(&intc_desc_list);
+        INIT_LIST_HEAD(&intc_parent_list);
+        for_each_matching_node(np, matches) {
+                if (!of_find_property(np, "interrupt-controller", NULL))
+                        continue;
+                /*
+                 * Here, we allocate and populate an intc_desc with the node
+                 * pointer, interrupt-parent device_node etc.
+                 */
+                desc = kzalloc(sizeof(*desc), GFP_KERNEL);
+                if (WARN_ON(!desc))
+                        goto err;
+                desc->dev = np;
+                desc->interrupt_parent = of_irq_find_parent(np);
+                list_add_tail(&desc->list, &intc_desc_list);
+        }
+        /*
+         * The root irq controller is the one without an interrupt-parent.
+         * That one goes first, followed by the controllers that reference it,
+         * followed by the ones that reference the 2nd level controllers, etc.
+         */
+        while (!list_empty(&intc_desc_list)) {
+                /*
+                 * Process all controllers with the current 'parent'.
+                 * First pass will be looking for NULL as the parent.
+                 * The assumption is that NULL parent means a root controller.
+                 */
+                list_for_each_entry_safe(desc, temp_desc, &intc_desc_list, list) {
+                        const struct of_device_id *match;
+                        int ret;
+                        of_irq_init_cb_t irq_init_cb;
+                        if (desc->interrupt_parent != parent)
+                                continue;
+                        list_del(&desc->list);
+                        match = of_match_node(matches, desc->dev);
+                        if (WARN(!match->data,
+                            "of_irq_init: no init function for %s\n",
+                            match->compatible)) {
+                                kfree(desc);
+                                continue;
+                        }
+                        pr_debug("of_irq_init: init %s @ %p, parent %p\n",
+                                 match->compatible,
+                                 desc->dev, desc->interrupt_parent);
+                        irq_init_cb = match->data;
+                        ret = irq_init_cb(desc->dev, desc->interrupt_parent);
+                        if (ret) {
+                                kfree(desc);
+                                continue;
+                        }
+                        /*
+                         * This one is now set up; add it to the parent list so
+                         * its children can get processed in a subsequent pass.
+                         */
+                        list_add_tail(&desc->list, &intc_parent_list);
+                }
+                /* Get the next pending parent that might have children */
+                desc = list_first_entry(&intc_parent_list, typeof(*desc), list);
+                if (list_empty(&intc_parent_list) || !desc) {
+                        pr_err("of_irq_init: children remain, but no parents\n");
+                        break;
+                }
+                list_del(&desc->list);
+                parent = desc->dev;
+                kfree(desc);
+        }
+        list_for_each_entry_safe(desc, temp_desc, &intc_parent_list, list) {
+                list_del(&desc->list);
+                kfree(desc);
+        }
+err:
+        list_for_each_entry_safe(desc, temp_desc, &intc_desc_list, list) {
+                list_del(&desc->list);
+                kfree(desc);
+        }
+}
diff --git a/drivers/pcmcia/pxa2xx_balloon3.c b/drivers/pcmcia/pxa2xx_balloon3.c
index f56d7de7c751..22a75e610f12 100644
--- a/drivers/pcmcia/pxa2xx_balloon3.c
+++ b/drivers/pcmcia/pxa2xx_balloon3.c
@@ -97,7 +97,7 @@ static void balloon3_pcmcia_socket_state(struct soc_pcmcia_socket *skt,
 static int balloon3_pcmcia_configure_socket(struct soc_pcmcia_socket *skt,
                                       const socket_state_t *state)
 {
-        __raw_writew(BALLOON3_CF_RESET, BALLOON3_CF_CONTROL_REG |
+        __raw_writew(BALLOON3_CF_RESET, BALLOON3_CF_CONTROL_REG +
                        ((state->flags & SS_RESET) ?
                        BALLOON3_FPGA_SETnCLR : 0));
        return 0;
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 57de051a74b3..9f88641e67f9 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -70,6 +70,7 @@ config BATTERY_DS2760
 config BATTERY_DS2780
        tristate "DS2780 battery driver"
+        depends on HAS_IOMEM
        select W1
        select W1_SLAVE_DS2780
        help
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 5a538fc1cc85..53eb4e55b289 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -8,7 +8,7 @@ config RTC_LIB
 menuconfig RTC_CLASS
        bool "Real Time Clock"
        default n
-        depends on !S390
+        depends on !S390 && !UML
        select RTC_LIB
        help
          Generic RTC class support. If you say yes here, you will
diff --git a/drivers/staging/pohmelfs/inode.c b/drivers/staging/pohmelfs/inode.c
index f3c6060c96b8..7a1955583b7d 100644
--- a/drivers/staging/pohmelfs/inode.c
+++ b/drivers/staging/pohmelfs/inode.c
@@ -1197,7 +1197,7 @@ const struct inode_operations pohmelfs_file_inode_operations = {
 void pohmelfs_fill_inode(struct inode *inode, struct netfs_inode_info *info)
 {
        inode->i_mode = info->mode;
-        inode->i_nlink = info->nlink;
+        set_nlink(inode, info->nlink);
        inode->i_uid = info->uid;
        inode->i_gid = info->gid;
        inode->i_blocks = info->blocks;
diff --git a/drivers/tty/Kconfig b/drivers/tty/Kconfig
index 8816f53e004d..b3d17416d86a 100644
--- a/drivers/tty/Kconfig
+++ b/drivers/tty/Kconfig
@@ -1,6 +1,6 @@
 config VT
        bool "Virtual terminal" if EXPERT
-        depends on !S390
+        depends on !S390 && !UML
        select INPUT
        default y
        ---help---
diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
index 29cbfd8c4e7c..8131e2c28015 100644
--- a/drivers/tty/serial/msm_serial.c
+++ b/drivers/tty/serial/msm_serial.c
@@ -19,6 +19,7 @@
 # define SUPPORT_SYSRQ
 #endif
+#include <linux/atomic.h>
 #include <linux/hrtimer.h>
 #include <linux/module.h>
 #include <linux/io.h>
@@ -33,6 +34,8 @@
 #include <linux/clk.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
 #include "msm_serial.h"
@@ -589,9 +592,8 @@ static void msm_release_port(struct uart_port *port)
                iowrite32(GSBI_PROTOCOL_IDLE, msm_port->gsbi_base +
                          GSBI_CONTROL);
-                gsbi_resource = platform_get_resource_byname(pdev,
+                gsbi_resource = platform_get_resource(pdev,
-                                                             IORESOURCE_MEM,
+                                                        IORESOURCE_MEM, 1);
-                                                             "gsbi_resource");
                if (unlikely(!gsbi_resource))
                        return;
@@ -612,8 +614,7 @@ static int msm_request_port(struct uart_port *port)
        resource_size_t size;
        int ret;
-        uart_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+        uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-                                                     "uart_resource");
        if (unlikely(!uart_resource))
                return -ENXIO;
@@ -628,8 +629,7 @@ static int msm_request_port(struct uart_port *port)
                goto fail_release_port;
        }
-        gsbi_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+        gsbi_resource = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-                                                     "gsbi_resource");
        /* Is this a GSBI-based port? */
        if (gsbi_resource) {
                size = resource_size(gsbi_resource);
@@ -857,6 +857,8 @@ static struct uart_driver msm_uart_driver = {
        .cons = MSM_CONSOLE,
 };
+static atomic_t msm_uart_next_id = ATOMIC_INIT(0);
 static int __init msm_serial_probe(struct platform_device *pdev)
 {
        struct msm_port *msm_port;
@@ -864,6 +866,9 @@ static int __init msm_serial_probe(struct platform_device *pdev)
        struct uart_port *port;
        int irq;
+        if (pdev->id == -1)
+                pdev->id = atomic_inc_return(&msm_uart_next_id) - 1;
        if (unlikely(pdev->id < 0 || pdev->id >= UART_NR))
                return -ENXIO;
@@ -873,7 +878,7 @@ static int __init msm_serial_probe(struct platform_device *pdev)
        port->dev = &pdev->dev;
        msm_port = UART_TO_MSM(port);
-        if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "gsbi_resource"))
+        if (platform_get_resource(pdev, IORESOURCE_MEM, 1))
                msm_port->is_uartdm = 1;
        else
                msm_port->is_uartdm = 0;
@@ -897,8 +902,7 @@ static int __init msm_serial_probe(struct platform_device *pdev)
        printk(KERN_INFO "uartclk = %d\n", port->uartclk);
-        resource = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+        resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-                                                     "uart_resource");
        if (unlikely(!resource))
                return -ENXIO;
        port->mapbase = resource->start;
@@ -922,11 +926,17 @@ static int __devexit msm_serial_remove(struct platform_device *pdev)
        return 0;
 }
+static struct of_device_id msm_match_table[] = {
+        { .compatible = "qcom,msm-uart" },
+        {}
+};
 static struct platform_driver msm_platform_driver = {
        .remove = msm_serial_remove,
        .driver = {
                .name = "msm_serial",
                .owner = THIS_MODULE,
+                .of_match_table = msm_match_table,
        },
 };
diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
index 944291e10f97..ba3a46b78b75 100644
--- a/drivers/usb/host/ohci-at91.c
+++ b/drivers/usb/host/ohci-at91.c
@@ -35,8 +35,7 @@ extern int usb_disabled(void);
 static void at91_start_clock(void)
 {
-        if (cpu_is_at91sam9261() || cpu_is_at91sam9g10())
+        clk_enable(hclk);
-                clk_enable(hclk);
        clk_enable(iclk);
        clk_enable(fclk);
        clocked = 1;
@@ -46,8 +45,7 @@ static void at91_stop_clock(void)
 {
        clk_disable(fclk);
        clk_disable(iclk);
-        if (cpu_is_at91sam9261() || cpu_is_at91sam9g10())
+        clk_disable(hclk);
-                clk_disable(hclk);
        clocked = 0;
 }
@@ -142,8 +140,7 @@ static int usb_hcd_at91_probe(const struct hc_driver *driver,
        iclk = clk_get(&pdev->dev, "ohci_clk");
        fclk = clk_get(&pdev->dev, "uhpck");
-        if (cpu_is_at91sam9261() || cpu_is_at91sam9g10())
+        hclk = clk_get(&pdev->dev, "hclk");
-                hclk = clk_get(&pdev->dev, "hck0");
        at91_start_hc(pdev);
        ohci_hcd_init(hcd_to_ohci(hcd));
@@ -155,8 +152,7 @@ static int usb_hcd_at91_probe(const struct hc_driver *driver,
        /* Error handling */
        at91_stop_hc(pdev);
-        if (cpu_is_at91sam9261() || cpu_is_at91sam9g10())
+        clk_put(hclk);
-                clk_put(hclk);
        clk_put(fclk);
        clk_put(iclk);
@@ -192,8 +188,7 @@ static void usb_hcd_at91_remove(struct usb_hcd *hcd,
        release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
        usb_put_hcd(hcd);
-        if (cpu_is_at91sam9261() || cpu_is_at91sam9g10())
+        clk_put(hclk);
-                clk_put(hclk);
        clk_put(fclk);
        clk_put(iclk);
        fclk = iclk = hclk = NULL;
@@ -223,6 +218,156 @@ ohci_at91_start (struct usb_hcd *hcd)
        return 0;
 }
+static void ohci_at91_usb_set_power(struct at91_usbh_data *pdata, int port, int enable)
+{
+        if (port < 0 || port >= 2)
+                return;
+        gpio_set_value(pdata->vbus_pin[port], !pdata->vbus_pin_inverted ^ enable);
+}
+static int ohci_at91_usb_get_power(struct at91_usbh_data *pdata, int port)
+{
+        if (port < 0 || port >= 2)
+                return -EINVAL;
+        return gpio_get_value(pdata->vbus_pin[port]) ^ !pdata->vbus_pin_inverted;
+}
+/*
+ * Update the status data from the hub with the over-current indicator change.
+ */
+static int ohci_at91_hub_status_data(struct usb_hcd *hcd, char *buf)
+{
+        struct at91_usbh_data *pdata = hcd->self.controller->platform_data;
+        int length = ohci_hub_status_data(hcd, buf);
+        int port;
+        for (port = 0; port < ARRAY_SIZE(pdata->overcurrent_pin); port++) {
+                if (pdata->overcurrent_changed[port]) {
+                        if (! length)
+                                length = 1;
+                        buf[0] |= 1 << (port + 1);
+                }
+        }
+        return length;
+}
+/*
+ * Look at the control requests to the root hub and see if we need to override.
+ */
+static int ohci_at91_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+                                 u16 wIndex, char *buf, u16 wLength)
+{
+        struct at91_usbh_data *pdata = hcd->self.controller->platform_data;
+        struct usb_hub_descriptor *desc;
+        int ret = -EINVAL;
+        u32 *data = (u32 *)buf;
+        dev_dbg(hcd->self.controller,
+                "ohci_at91_hub_control(%p,0x%04x,0x%04x,0x%04x,%p,%04x)\n",
+                hcd, typeReq, wValue, wIndex, buf, wLength);
+        switch (typeReq) {
+        case SetPortFeature:
+                if (wValue == USB_PORT_FEAT_POWER) {
+                        dev_dbg(hcd->self.controller, "SetPortFeat: POWER\n");
+                        ohci_at91_usb_set_power(pdata, wIndex - 1, 1);
+                        goto out;
+                }
+                break;
+        case ClearPortFeature:
+                switch (wValue) {
+                case USB_PORT_FEAT_C_OVER_CURRENT:
+                        dev_dbg(hcd->self.controller,
+                                "ClearPortFeature: C_OVER_CURRENT\n");
+                        if (wIndex == 1 || wIndex == 2) {
+                                pdata->overcurrent_changed[wIndex-1] = 0;
+                                pdata->overcurrent_status[wIndex-1] = 0;
+                        }
+                        goto out;
+                case USB_PORT_FEAT_OVER_CURRENT:
+                        dev_dbg(hcd->self.controller,
+                                "ClearPortFeature: OVER_CURRENT\n");
+                        if (wIndex == 1 || wIndex == 2) {
+                                pdata->overcurrent_status[wIndex-1] = 0;
+                        }
+                        goto out;
+                case USB_PORT_FEAT_POWER:
+                        dev_dbg(hcd->self.controller,
+                                "ClearPortFeature: POWER\n");
+                        if (wIndex == 1 || wIndex == 2) {
+                                ohci_at91_usb_set_power(pdata, wIndex - 1, 0);
+                                return 0;
+                        }
+                }
+                break;
+        }
+        ret = ohci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
+        if (ret)
+                goto out;
+        switch (typeReq) {
+        case GetHubDescriptor:
+                /* update the hub's descriptor */
+                desc = (struct usb_hub_descriptor *)buf;
+                dev_dbg(hcd->self.controller, "wHubCharacteristics 0x%04x\n",
+                        desc->wHubCharacteristics);
+                /* remove the old configurations for power-switching, and
+                 * over-current protection, and insert our new configuration
+                 */
+                desc->wHubCharacteristics &= ~cpu_to_le16(HUB_CHAR_LPSM);
+                desc->wHubCharacteristics |= cpu_to_le16(0x0001);
+                if (pdata->overcurrent_supported) {
+                        desc->wHubCharacteristics &= ~cpu_to_le16(HUB_CHAR_OCPM);
+                        desc->wHubCharacteristics |=  cpu_to_le16(0x0008|0x0001);
+                }
+                dev_dbg(hcd->self.controller, "wHubCharacteristics after 0x%04x\n",
+                        desc->wHubCharacteristics);
+                return ret;
+        case GetPortStatus:
+                /* check port status */
+                dev_dbg(hcd->self.controller, "GetPortStatus(%d)\n", wIndex);
+                if (wIndex == 1 || wIndex == 2) {
+                        if (! ohci_at91_usb_get_power(pdata, wIndex-1)) {
+                                *data &= ~cpu_to_le32(RH_PS_PPS);
+                        }
+                        if (pdata->overcurrent_changed[wIndex-1]) {
+                                *data |= cpu_to_le32(RH_PS_OCIC);
+                        }
+                        if (pdata->overcurrent_status[wIndex-1]) {
+                                *data |= cpu_to_le32(RH_PS_POCI);
+                        }
+                }
+        }
+ out:
+        return ret;
+}
 /*-------------------------------------------------------------------------*/
 static const struct hc_driver ohci_at91_hc_driver = {
@@ -258,8 +403,8 @@ static const struct hc_driver ohci_at91_hc_driver = {
        /*
         * root hub support
         */
-        .hub_status_data =      ohci_hub_status_data,
+        .hub_status_data =      ohci_at91_hub_status_data,
-        .hub_control =          ohci_hub_control,
+        .hub_control =          ohci_at91_hub_control,
 #ifdef CONFIG_PM
        .bus_suspend =          ohci_bus_suspend,
        .bus_resume =           ohci_bus_resume,
@@ -269,22 +414,71 @@ static const struct hc_driver ohci_at91_hc_driver = {
 /*-------------------------------------------------------------------------*/
+static irqreturn_t ohci_hcd_at91_overcurrent_irq(int irq, void *data)
+{
+        struct platform_device *pdev = data;
+        struct at91_usbh_data *pdata = pdev->dev.platform_data;
+        int val, gpio, port;
+        /* From the GPIO notifying the over-current situation, find
+         * out the corresponding port */
+        gpio = irq_to_gpio(irq);
+        for (port = 0; port < ARRAY_SIZE(pdata->overcurrent_pin); port++) {
+                if (pdata->overcurrent_pin[port] == gpio)
+                        break;
+        }
+        if (port == ARRAY_SIZE(pdata->overcurrent_pin)) {
+                dev_err(& pdev->dev, "overcurrent interrupt from unknown GPIO\n");
+                return IRQ_HANDLED;
+        }
+        val = gpio_get_value(gpio);
+        /* When notified of an over-current situation, disable power
+           on the corresponding port, and mark this port in
+           over-current. */
+        if (! val) {
+                ohci_at91_usb_set_power(pdata, port, 0);
+                pdata->overcurrent_status[port]  = 1;
+                pdata->overcurrent_changed[port] = 1;
+        }
+        dev_dbg(& pdev->dev, "overcurrent situation %s\n",
+                val ? "exited" : "notified");
+        return IRQ_HANDLED;
+}
+/*-------------------------------------------------------------------------*/
 static int ohci_hcd_at91_drv_probe(struct platform_device *pdev)
 {
        struct at91_usbh_data   *pdata = pdev->dev.platform_data;
        int                     i;
        if (pdata) {
-                /* REVISIT make the driver support per-port power switching,
-                 * and also overcurrent detection.  Here we assume the ports
-                 * are always powered while this driver is active, and use
-                 * active-low power switches.
-                 */
                for (i = 0; i < ARRAY_SIZE(pdata->vbus_pin); i++) {
                        if (pdata->vbus_pin[i] <= 0)
                                continue;
                        gpio_request(pdata->vbus_pin[i], "ohci_vbus");
-                        gpio_direction_output(pdata->vbus_pin[i], 0);
+                        ohci_at91_usb_set_power(pdata, i, 1);
+                }
+                for (i = 0; i < ARRAY_SIZE(pdata->overcurrent_pin); i++) {
+                        int ret;
+                        if (pdata->overcurrent_pin[i] <= 0)
+                                continue;
+                        gpio_request(pdata->overcurrent_pin[i], "ohci_overcurrent");
+                        ret = request_irq(gpio_to_irq(pdata->overcurrent_pin[i]),
+                                          ohci_hcd_at91_overcurrent_irq,
+                                          IRQF_SHARED, "ohci_overcurrent", pdev);
+                        if (ret) {
+                                gpio_free(pdata->overcurrent_pin[i]);
+                                dev_warn(& pdev->dev, "cannot get GPIO IRQ for overcurrent\n");
+                        }
                }
        }
@@ -301,9 +495,16 @@ static int ohci_hcd_at91_drv_remove(struct platform_device *pdev)
                for (i = 0; i < ARRAY_SIZE(pdata->vbus_pin); i++) {
                        if (pdata->vbus_pin[i] <= 0)
                                continue;
-                        gpio_direction_output(pdata->vbus_pin[i], 1);
+                        ohci_at91_usb_set_power(pdata, i, 0);
                        gpio_free(pdata->vbus_pin[i]);
                }
+                for (i = 0; i < ARRAY_SIZE(pdata->overcurrent_pin); i++) {
+                        if (pdata->overcurrent_pin[i] <= 0)
+                                continue;
+                        free_irq(gpio_to_irq(pdata->overcurrent_pin[i]), pdev);
+                        gpio_free(pdata->overcurrent_pin[i]);
+                }
        }
        device_init_wakeup(&pdev->dev, 0);
diff --git a/drivers/video/mbx/mbxfb.c b/drivers/video/mbx/mbxfb.c
index afea9abbd678..6ce34160da78 100644
--- a/drivers/video/mbx/mbxfb.c
+++ b/drivers/video/mbx/mbxfb.c
@@ -34,7 +34,7 @@
 #include "regs.h"
 #include "reg_bits.h"
-static unsigned long virt_base_2700;
+static void __iomem *virt_base_2700;
 #define write_reg(val, reg) do { writel((val), (reg)); } while(0)
@@ -850,7 +850,7 @@ static int mbxfb_suspend(struct platform_device *dev, pm_message_t state)
 {
        /* make frame buffer memory enter self-refresh mode */
        write_reg_dly(LMPWR_MC_PWR_SRM, LMPWR);
-        while (LMPWRSTAT != LMPWRSTAT_MC_PWR_SRM)
+        while (readl(LMPWRSTAT) != LMPWRSTAT_MC_PWR_SRM)
                ; /* empty statement */
        /* reset the device, since it's initial state is 'mostly sleeping' */
@@ -946,7 +946,7 @@ static int __devinit mbxfb_probe(struct platform_device *dev)
                ret = -EINVAL;
                goto err3;
        }
-        virt_base_2700 = (unsigned long)mfbi->reg_virt_addr;
+        virt_base_2700 = mfbi->reg_virt_addr;
        mfbi->fb_virt_addr = ioremap_nocache(mfbi->fb_phys_addr,
                                             res_size(mfbi->fb_req));
diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c
index e89778f4081f..1d1e4f175e78 100644
--- a/drivers/video/pxafb.c
+++ b/drivers/video/pxafb.c
@@ -1309,16 +1309,6 @@ static int pxafb_smart_init(struct pxafb_info *fbi)
        return 0;
 }
 #else
-int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
-{
-        return 0;
-}
-int pxafb_smart_flush(struct fb_info *info)
-{
-        return 0;
-}
 static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; }
 #endif /* CONFIG_FB_PXA_SMARTPANEL */
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 86b0735e6aa0..64c6752ea2c6 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -726,7 +726,7 @@ config SBC8360_WDT
 config SBC7240_WDT
        tristate "SBC Nano 7240 Watchdog Timer"
-        depends on X86_32
+        depends on X86_32 && !UML
        ---help---
          This is the driver for the hardware watchdog found on the IEI
          single board computers EPIC Nano 7240 (and likely others). This
@@ -1174,6 +1174,10 @@ config XEN_WDT
          by Xen 4.0 and newer.  The watchdog timeout period is normally one
          minute but can be changed with a boot-time parameter.
+config UML_WATCHDOG
+        tristate "UML watchdog"
+        depends on UML
 #
 # ISA-based Watchdog Cards
 #
diff --git a/fs/9p/vfs_inode.c b/fs/9p/vfs_inode.c
index b5a1076aaa6c..879ed8851737 100644
--- a/fs/9p/vfs_inode.c
+++ b/fs/9p/vfs_inode.c
@@ -1138,7 +1138,7 @@ v9fs_stat2inode(struct p9_wstat *stat, struct inode *inode,
        struct v9fs_session_info *v9ses = sb->s_fs_info;
        struct v9fs_inode *v9inode = V9FS_I(inode);
-        inode->i_nlink = 1;
+        set_nlink(inode, 1);
        inode->i_atime.tv_sec = stat->atime;
        inode->i_mtime.tv_sec = stat->mtime;
@@ -1164,7 +1164,7 @@ v9fs_stat2inode(struct p9_wstat *stat, struct inode *inode,
                        /* HARDLINKCOUNT %u */
                        sscanf(ext, "%13s %u", tag_name, &i_nlink);
                        if (!strncmp(tag_name, "HARDLINKCOUNT", 13))
-                                inode->i_nlink = i_nlink;
+                                set_nlink(inode, i_nlink);
                }
        }
        mode = stat->mode & S_IALLUGO;
diff --git a/fs/9p/vfs_inode_dotl.c b/fs/9p/vfs_inode_dotl.c
index aded79fcd5cf..0b5745e21946 100644
--- a/fs/9p/vfs_inode_dotl.c
+++ b/fs/9p/vfs_inode_dotl.c
@@ -606,7 +606,7 @@ v9fs_stat2inode_dotl(struct p9_stat_dotl *stat, struct inode *inode)
                inode->i_ctime.tv_nsec = stat->st_ctime_nsec;
                inode->i_uid = stat->st_uid;
                inode->i_gid = stat->st_gid;
-                inode->i_nlink = stat->st_nlink;
+                set_nlink(inode, stat->st_nlink);
                mode = stat->st_mode & S_IALLUGO;
                mode |= inode->i_mode & ~S_IALLUGO;
@@ -632,7 +632,7 @@ v9fs_stat2inode_dotl(struct p9_stat_dotl *stat, struct inode *inode)
                if (stat->st_result_mask & P9_STATS_GID)
                        inode->i_gid = stat->st_gid;
                if (stat->st_result_mask & P9_STATS_NLINK)
-                        inode->i_nlink = stat->st_nlink;
+                        set_nlink(inode, stat->st_nlink);
                if (stat->st_result_mask & P9_STATS_MODE) {
                        inode->i_mode = stat->st_mode;
                        if ((S_ISBLK(inode->i_mode)) ||
diff --git a/fs/adfs/inode.c b/fs/adfs/inode.c
index d5250c5aae21..1dab6a174d6a 100644
--- a/fs/adfs/inode.c
+++ b/fs/adfs/inode.c
@@ -247,7 +247,7 @@ adfs_iget(struct super_block *sb, struct object_info *obj)
        inode->i_gid     = ADFS_SB(sb)->s_gid;
        inode->i_ino     = obj->file_id;
        inode->i_size    = obj->size;
-        inode->i_nlink   = 2;
+        set_nlink(inode, 2);
        inode->i_blocks  = (inode->i_size + sb->s_blocksize - 1) >>
                            sb->s_blocksize_bits;
diff --git a/fs/affs/amigaffs.c b/fs/affs/amigaffs.c
index 3a4557e8325c..de37ec842340 100644
--- a/fs/affs/amigaffs.c
+++ b/fs/affs/amigaffs.c
@@ -215,7 +215,7 @@ affs_remove_link(struct dentry *dentry)
                                break;
                        default:
                                if (!AFFS_TAIL(sb, bh)->link_chain)
-                                        inode->i_nlink = 1;
+                                        set_nlink(inode, 1);
                        }
                        affs_free_block(sb, link_ino);
                        goto done;
@@ -316,7 +316,7 @@ affs_remove_header(struct dentry *dentry)
        if (inode->i_nlink > 1)
                retval = affs_remove_link(dentry);
        else
-                inode->i_nlink = 0;
+                clear_nlink(inode);
        affs_unlock_link(inode);
        inode->i_ctime = CURRENT_TIME_SEC;
        mark_inode_dirty(inode);
diff --git a/fs/affs/inode.c b/fs/affs/inode.c
index 5d828903ac69..88a4b0b50058 100644
--- a/fs/affs/inode.c
+++ b/fs/affs/inode.c
@@ -54,7 +54,7 @@ struct inode *affs_iget(struct super_block *sb, unsigned long ino)
        prot = be32_to_cpu(tail->protect);
        inode->i_size = 0;
-        inode->i_nlink = 1;
+        set_nlink(inode, 1);
        inode->i_mode = 0;
        AFFS_I(inode)->i_extcnt = 1;
        AFFS_I(inode)->i_ext_last = ~1;
@@ -137,7 +137,7 @@ struct inode *affs_iget(struct super_block *sb, unsigned long ino)
                                               sbi->s_hashsize + 1;
                }
                if (tail->link_chain)
-                        inode->i_nlink = 2;
+                        set_nlink(inode, 2);
                inode->i_mapping->a_ops = (sbi->s_flags & SF_OFS) ? &affs_aops_ofs : &affs_aops;
                inode->i_op = &affs_file_inode_operations;
                inode->i_fop = &affs_file_operations;
@@ -304,7 +304,7 @@ affs_new_inode(struct inode *dir)
        inode->i_uid     = current_fsuid();
        inode->i_gid     = current_fsgid();
        inode->i_ino     = block;
-        inode->i_nlink   = 1;
+        set_nlink(inode, 1);
        inode->i_mtime   = inode->i_atime = inode->i_ctime = CURRENT_TIME_SEC;
        atomic_set(&AFFS_I(inode)->i_opencnt, 0);
        AFFS_I(inode)->i_blkcnt = 0;
@@ -387,7 +387,7 @@ affs_add_entry(struct inode *dir, struct inode *inode, struct dentry *dentry, s3
                AFFS_TAIL(sb, inode_bh)->link_chain = cpu_to_be32(block);
                affs_adjust_checksum(inode_bh, block - be32_to_cpu(chain));
                mark_buffer_dirty_inode(inode_bh, inode);
-                inode->i_nlink = 2;
+                set_nlink(inode, 2);
                ihold(inode);
        }
        affs_fix_checksum(sb, bh);
diff --git a/fs/affs/namei.c b/fs/affs/namei.c
index e3e9efc1fdd8..780a11dc6318 100644
--- a/fs/affs/namei.c
+++ b/fs/affs/namei.c
@@ -277,7 +277,7 @@ affs_create(struct inode *dir, struct dentry *dentry, int mode, struct nameidata
        inode->i_mapping->a_ops = (AFFS_SB(sb)->s_flags & SF_OFS) ? &affs_aops_ofs : &affs_aops;
        error = affs_add_entry(dir, inode, dentry, ST_FILE);
        if (error) {
-                inode->i_nlink = 0;
+                clear_nlink(inode);
                iput(inode);
                return error;
        }
@@ -305,7 +305,7 @@ affs_mkdir(struct inode *dir, struct dentry *dentry, int mode)
        error = affs_add_entry(dir, inode, dentry, ST_USERDIR);
        if (error) {
-                inode->i_nlink = 0;
+                clear_nlink(inode);
                mark_inode_dirty(inode);
                iput(inode);
                return error;
@@ -392,7 +392,7 @@ affs_symlink(struct inode *dir, struct dentry *dentry, const char *symname)
        return 0;
 err:
-        inode->i_nlink = 0;
+        clear_nlink(inode);
        mark_inode_dirty(inode);
        iput(inode);
        return error;
diff --git a/fs/afs/fsclient.c b/fs/afs/fsclient.c
index 346e3289abd7..2f213d109c21 100644
--- a/fs/afs/fsclient.c
+++ b/fs/afs/fsclient.c
@@ -90,7 +90,7 @@ static void xdr_decode_AFSFetchStatus(const __be32 **_bp,
                        vnode->vfs_inode.i_uid = status->owner;
                        vnode->vfs_inode.i_gid = status->group;
                        vnode->vfs_inode.i_generation = vnode->fid.unique;
-                        vnode->vfs_inode.i_nlink = status->nlink;
+                        set_nlink(&vnode->vfs_inode, status->nlink);
                        mode = vnode->vfs_inode.i_mode;
                        mode &= ~S_IALLUGO;
diff --git a/fs/afs/inode.c b/fs/afs/inode.c
index 0fdab6e03d87..d890ae3b2ce6 100644
--- a/fs/afs/inode.c
+++ b/fs/afs/inode.c
@@ -67,7 +67,7 @@ static int afs_inode_map_status(struct afs_vnode *vnode, struct key *key)
                fscache_attr_changed(vnode->cache);
 #endif
-        inode->i_nlink          = vnode->status.nlink;
+        set_nlink(inode, vnode->status.nlink);
        inode->i_uid            = vnode->status.owner;
        inode->i_gid            = 0;
        inode->i_size           = vnode->status.size;
@@ -174,7 +174,7 @@ struct inode *afs_iget_autocell(struct inode *dir, const char *dev_name,
        inode->i_size           = 0;
        inode->i_mode           = S_IFDIR | S_IRUGO | S_IXUGO;
        inode->i_op             = &afs_autocell_inode_operations;
-        inode->i_nlink          = 2;
+        set_nlink(inode, 2);
        inode->i_uid            = 0;
        inode->i_gid            = 0;
        inode->i_ctime.tv_sec   = get_seconds();
diff --git a/fs/autofs4/inode.c b/fs/autofs4/inode.c
index 180fa2425e49..8179f1ab8175 100644
--- a/fs/autofs4/inode.c
+++ b/fs/autofs4/inode.c
@@ -342,7 +342,7 @@ struct inode *autofs4_get_inode(struct super_block *sb, mode_t mode)
        inode->i_ino = get_next_ino();
        if (S_ISDIR(mode)) {
-                inode->i_nlink = 2;
+                set_nlink(inode, 2);
                inode->i_op = &autofs4_dir_inode_operations;
                inode->i_fop = &autofs4_dir_operations;
        } else if (S_ISLNK(mode)) {
diff --git a/fs/befs/linuxvfs.c b/fs/befs/linuxvfs.c
index 720d885e8dca..8342ca67abcd 100644
--- a/fs/befs/linuxvfs.c
+++ b/fs/befs/linuxvfs.c
@@ -357,7 +357,7 @@ static struct inode *befs_iget(struct super_block *sb, unsigned long ino)
        inode->i_gid = befs_sb->mount_opts.use_gid ?
            befs_sb->mount_opts.gid : (gid_t) fs32_to_cpu(sb, raw_inode->gid);
-        inode->i_nlink = 1;
+        set_nlink(inode, 1);
        /*
         * BEFS's time is 64 bits, but current VFS is 32 bits...
diff --git a/fs/bfs/dir.c b/fs/bfs/dir.c
index b14cebfd9047..9cc074019479 100644
--- a/fs/bfs/dir.c
+++ b/fs/bfs/dir.c
@@ -199,7 +199,7 @@ static int bfs_unlink(struct inode *dir, struct dentry *dentry)
                printf("unlinking non-existent file %s:%lu (nlink=%d)\n",
                                        inode->i_sb->s_id, inode->i_ino,
                                        inode->i_nlink);
-                inode->i_nlink = 1;
+                set_nlink(inode, 1);
        }
        de->ino = 0;
        mark_buffer_dirty_inode(bh, dir);
diff --git a/fs/bfs/inode.c b/fs/bfs/inode.c
index a8e37f81d097..697af5bf70b3 100644
--- a/fs/bfs/inode.c
+++ b/fs/bfs/inode.c
@@ -78,7 +78,7 @@ struct inode *bfs_iget(struct super_block *sb, unsigned long ino)
        BFS_I(inode)->i_dsk_ino = le16_to_cpu(di->i_ino);
        inode->i_uid =  le32_to_cpu(di->i_uid);
        inode->i_gid =  le32_to_cpu(di->i_gid);
-        inode->i_nlink =  le32_to_cpu(di->i_nlink);
+        set_nlink(inode, le32_to_cpu(di->i_nlink));
        inode->i_size = BFS_FILESIZE(di);
        inode->i_blocks = BFS_FILEBLOCKS(di);
        inode->i_atime.tv_sec =  le32_to_cpu(di->i_atime);
diff --git a/fs/binfmt_misc.c b/fs/binfmt_misc.c
index ba1a1ae4a18a..1e9edbdeda7e 100644
--- a/fs/binfmt_misc.c
+++ b/fs/binfmt_misc.c
@@ -521,7 +521,7 @@ static void kill_node(Node *e)
        write_unlock(&entries_lock);
        if (dentry) {
-                dentry->d_inode->i_nlink--;
+                drop_nlink(dentry->d_inode);
                d_drop(dentry);
                dput(dentry);
                simple_release_fs(&bm_mnt, &entry_count);
diff --git a/fs/btrfs/delayed-inode.c b/fs/btrfs/delayed-inode.c
index b52c672f4c18..ae4d9cd10961 100644
--- a/fs/btrfs/delayed-inode.c
+++ b/fs/btrfs/delayed-inode.c
@@ -1641,7 +1641,7 @@ int btrfs_fill_inode(struct inode *inode, u32 *rdev)
        inode->i_gid = btrfs_stack_inode_gid(inode_item);
        btrfs_i_size_write(inode, btrfs_stack_inode_size(inode_item));
        inode->i_mode = btrfs_stack_inode_mode(inode_item);
-        inode->i_nlink = btrfs_stack_inode_nlink(inode_item);
+        set_nlink(inode, btrfs_stack_inode_nlink(inode_item));
        inode_set_bytes(inode, btrfs_stack_inode_nbytes(inode_item));
        BTRFS_I(inode)->generation = btrfs_stack_inode_generation(inode_item);
        BTRFS_I(inode)->sequence = btrfs_stack_inode_sequence(inode_item);
diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c
index 07b3ac662e19..07ea91879a91 100644
--- a/fs/btrfs/disk-io.c
+++ b/fs/btrfs/disk-io.c
@@ -1705,7 +1705,7 @@ struct btrfs_root *open_ctree(struct super_block *sb,
        sb->s_bdi = &fs_info->bdi;
        fs_info->btree_inode->i_ino = BTRFS_BTREE_INODE_OBJECTID;
-        fs_info->btree_inode->i_nlink = 1;
+        set_nlink(fs_info->btree_inode, 1);
        /*
         * we set the i_size on the btree inode to the max possible int.
         * the real end of the address space is determined by all of
diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c
index b2d004ad66a0..75686a61bd45 100644
--- a/fs/btrfs/inode.c
+++ b/fs/btrfs/inode.c
@@ -2534,7 +2534,7 @@ static void btrfs_read_locked_inode(struct inode *inode)
        inode_item = btrfs_item_ptr(leaf, path->slots[0],
                                    struct btrfs_inode_item);
        inode->i_mode = btrfs_inode_mode(leaf, inode_item);
-        inode->i_nlink = btrfs_inode_nlink(leaf, inode_item);
+        set_nlink(inode, btrfs_inode_nlink(leaf, inode_item));
        inode->i_uid = btrfs_inode_uid(leaf, inode_item);
        inode->i_gid = btrfs_inode_gid(leaf, inode_item);
        btrfs_i_size_write(inode, btrfs_inode_size(leaf, inode_item));
@@ -6728,7 +6728,7 @@ int btrfs_create_subvol_root(struct btrfs_trans_handle *trans,
        inode->i_op = &btrfs_dir_inode_operations;
        inode->i_fop = &btrfs_dir_file_operations;
-        inode->i_nlink = 1;
+        set_nlink(inode, 1);
        btrfs_i_size_write(inode, 0);
        err = btrfs_update_inode(trans, new_root, inode);
diff --git a/fs/btrfs/tree-log.c b/fs/btrfs/tree-log.c
index 786639fca067..0618aa39740b 100644
--- a/fs/btrfs/tree-log.c
+++ b/fs/btrfs/tree-log.c
@@ -1030,7 +1030,7 @@ static noinline int fixup_inode_link_count(struct btrfs_trans_handle *trans,
        }
        btrfs_release_path(path);
        if (nlink != inode->i_nlink) {
-                inode->i_nlink = nlink;
+                set_nlink(inode, nlink);
                btrfs_update_inode(trans, root, inode);
        }
        BTRFS_I(inode)->index_cnt = (u64)-1;
diff --git a/fs/ceph/caps.c b/fs/ceph/caps.c
index b8731bf3ef1f..15b21e35078a 100644
--- a/fs/ceph/caps.c
+++ b/fs/ceph/caps.c
@@ -2363,7 +2363,7 @@ static void handle_cap_grant(struct inode *inode, struct ceph_mds_caps *grant,
        }
        if ((issued & CEPH_CAP_LINK_EXCL) == 0)
-                inode->i_nlink = le32_to_cpu(grant->nlink);
+                set_nlink(inode, le32_to_cpu(grant->nlink));
        if ((issued & CEPH_CAP_XATTR_EXCL) == 0 && grant->xattr_len) {
                int len = le32_to_cpu(grant->xattr_len);
diff --git a/fs/ceph/inode.c b/fs/ceph/inode.c
index 5dde7d51dc11..1616a0d37cbd 100644
--- a/fs/ceph/inode.c
+++ b/fs/ceph/inode.c
@@ -618,7 +618,7 @@ static int fill_inode(struct inode *inode,
        }
        if ((issued & CEPH_CAP_LINK_EXCL) == 0)
-                inode->i_nlink = le32_to_cpu(info->nlink);
+                set_nlink(inode, le32_to_cpu(info->nlink));
        /* be careful with mtime, atime, size */
        ceph_decode_timespec(&atime, &info->atime);
diff --git a/fs/cifs/inode.c b/fs/cifs/inode.c
index 2c50bd2f65d1..e851d5b8931e 100644
--- a/fs/cifs/inode.c
+++ b/fs/cifs/inode.c
@@ -132,7 +132,7 @@ cifs_fattr_to_inode(struct inode *inode, struct cifs_fattr *fattr)
        inode->i_mtime = fattr->cf_mtime;
        inode->i_ctime = fattr->cf_ctime;
        inode->i_rdev = fattr->cf_rdev;
-        inode->i_nlink = fattr->cf_nlink;
+        set_nlink(inode, fattr->cf_nlink);
        inode->i_uid = fattr->cf_uid;
        inode->i_gid = fattr->cf_gid;
@@ -905,7 +905,7 @@ struct inode *cifs_root_iget(struct super_block *sb)
        if (rc && tcon->ipc) {
                cFYI(1, "ipc connection - fake read inode");
                inode->i_mode |= S_IFDIR;
-                inode->i_nlink = 2;
+                set_nlink(inode, 2);
                inode->i_op = &cifs_ipc_inode_ops;
                inode->i_fop = &simple_dir_operations;
                inode->i_uid = cifs_sb->mnt_uid;
@@ -1367,7 +1367,7 @@ mkdir_get_info:
                 /* setting nlink not necessary except in cases where we
                  * failed to get it from the server or was set bogus */
                if ((direntry->d_inode) && (direntry->d_inode->i_nlink < 2))
-                                direntry->d_inode->i_nlink = 2;
+                        set_nlink(direntry->d_inode, 2);
                mode &= ~current_umask();
                /* must turn on setgid bit if parent dir has it */
diff --git a/fs/cifs/link.c b/fs/cifs/link.c
index 8693b5d0e180..6b0e06434391 100644
--- a/fs/cifs/link.c
+++ b/fs/cifs/link.c
@@ -433,7 +433,7 @@ cifs_hardlink(struct dentry *old_file, struct inode *inode,
        if (old_file->d_inode) {
                cifsInode = CIFS_I(old_file->d_inode);
                if (rc == 0) {
-                        old_file->d_inode->i_nlink++;
+                        inc_nlink(old_file->d_inode);
 /* BB should we make this contingent on superblock flag NOATIME? */
 /*                      old_file->d_inode->i_ctime = CURRENT_TIME;*/
                        /* parent dir timestamps will update from srv
diff --git a/fs/coda/coda_linux.c b/fs/coda/coda_linux.c
index 2bdbcc11b373..854ace712685 100644
--- a/fs/coda/coda_linux.c
+++ b/fs/coda/coda_linux.c
@@ -104,7 +104,7 @@ void coda_vattr_to_iattr(struct inode *inode, struct coda_vattr *attr)
        if (attr->va_gid != -1)
                inode->i_gid = (gid_t) attr->va_gid;
        if (attr->va_nlink != -1)
-                inode->i_nlink = attr->va_nlink;
+                set_nlink(inode, attr->va_nlink);
        if (attr->va_size != -1)
                inode->i_size = attr->va_size;
        if (attr->va_size != -1)
diff --git a/fs/coda/dir.c b/fs/coda/dir.c
index 0239433f50cb..28e7e135cfab 100644
--- a/fs/coda/dir.c
+++ b/fs/coda/dir.c
@@ -340,7 +340,7 @@ static int coda_rmdir(struct inode *dir, struct dentry *de)
        if (!error) {
                /* VFS may delete the child */
                if (de->d_inode)
-                    de->d_inode->i_nlink = 0;
+                        clear_nlink(de->d_inode);
                /* fix the link count of the parent */
                coda_dir_drop_nlink(dir);
diff --git a/fs/dcache.c b/fs/dcache.c
index a88948b8bd17..274f13e2f094 100644
--- a/fs/dcache.c
+++ b/fs/dcache.c
@@ -225,7 +225,7 @@ static void dentry_unlink_inode(struct dentry * dentry)
 }
 /*
- * dentry_lru_(add|del|move_tail) must be called with d_lock held.
+ * dentry_lru_(add|del|prune|move_tail) must be called with d_lock held.
 */
 static void dentry_lru_add(struct dentry *dentry)
 {
@@ -245,6 +245,9 @@ static void __dentry_lru_del(struct dentry *dentry)
        dentry_stat.nr_unused--;
 }
+/*
+ * Remove a dentry with references from the LRU.
+ */
 static void dentry_lru_del(struct dentry *dentry)
 {
        if (!list_empty(&dentry->d_lru)) {
@@ -254,6 +257,23 @@ static void dentry_lru_del(struct dentry *dentry)
        }
 }
+/*
+ * Remove a dentry that is unreferenced and about to be pruned
+ * (unhashed and destroyed) from the LRU, and inform the file system.
+ * This wrapper should be called _prior_ to unhashing a victim dentry.
+ */
+static void dentry_lru_prune(struct dentry *dentry)
+{
+        if (!list_empty(&dentry->d_lru)) {
+                if (dentry->d_flags & DCACHE_OP_PRUNE)
+                        dentry->d_op->d_prune(dentry);
+                spin_lock(&dcache_lru_lock);
+                __dentry_lru_del(dentry);
+                spin_unlock(&dcache_lru_lock);
+        }
+}
 static void dentry_lru_move_tail(struct dentry *dentry)
 {
        spin_lock(&dcache_lru_lock);
@@ -403,8 +423,12 @@ relock:
        if (ref)
                dentry->d_count--;
-        /* if dentry was on the d_lru list delete it from there */
+        /*
-        dentry_lru_del(dentry);
+         * if dentry was on the d_lru list delete it from there.
+         * inform the fs via d_prune that this dentry is about to be
+         * unhashed and destroyed.
+         */
+        dentry_lru_prune(dentry);
        /* if it was on the hash then remove it */
        __d_drop(dentry);
        return d_kill(dentry, parent);
@@ -854,8 +878,12 @@ static void shrink_dcache_for_umount_subtree(struct dentry *dentry)
                do {
                        struct inode *inode;
-                        /* detach from the system */
+                        /*
-                        dentry_lru_del(dentry);
+                         * remove the dentry from the lru, and inform
+                         * the fs that this dentry is about to be
+                         * unhashed and destroyed.
+                         */
+                        dentry_lru_prune(dentry);
                        __d_shrink(dentry);
                        if (dentry->d_count != 0) {
@@ -1283,6 +1311,8 @@ void d_set_d_op(struct dentry *dentry, const struct dentry_operations *op)
                dentry->d_flags |= DCACHE_OP_REVALIDATE;
        if (op->d_delete)
                dentry->d_flags |= DCACHE_OP_DELETE;
+        if (op->d_prune)
+                dentry->d_flags |= DCACHE_OP_PRUNE;
 }
 EXPORT_SYMBOL(d_set_d_op);
diff --git a/fs/devpts/inode.c b/fs/devpts/inode.c
index 2f27e578d466..d5d5297efe97 100644
--- a/fs/devpts/inode.c
+++ b/fs/devpts/inode.c
@@ -307,7 +307,7 @@ devpts_fill_super(struct super_block *s, void *data, int silent)
        inode->i_mode = S_IFDIR | S_IRUGO | S_IXUGO | S_IWUSR;
        inode->i_op = &simple_dir_inode_operations;
        inode->i_fop = &simple_dir_operations;
-        inode->i_nlink = 2;
+        set_nlink(inode, 2);
        s->s_root = d_alloc_root(inode);
        if (s->s_root)
@@ -549,7 +549,7 @@ void devpts_pty_kill(struct tty_struct *tty)
        dentry = d_find_alias(inode);
-        inode->i_nlink--;
+        drop_nlink(inode);
        d_delete(dentry);
        dput(dentry);   /* d_alloc_name() in devpts_pty_new() */
        dput(dentry);           /* d_find_alias above */
diff --git a/fs/ecryptfs/inode.c b/fs/ecryptfs/inode.c
index 11f8582d7218..a36d327f1521 100644
--- a/fs/ecryptfs/inode.c
+++ b/fs/ecryptfs/inode.c
@@ -474,8 +474,8 @@ static int ecryptfs_link(struct dentry *old_dentry, struct inode *dir,
                goto out_lock;
        fsstack_copy_attr_times(dir, lower_dir_dentry->d_inode);
        fsstack_copy_inode_size(dir, lower_dir_dentry->d_inode);
-        old_dentry->d_inode->i_nlink =
+        set_nlink(old_dentry->d_inode,
-                ecryptfs_inode_to_lower(old_dentry->d_inode)->i_nlink;
+                  ecryptfs_inode_to_lower(old_dentry->d_inode)->i_nlink);
        i_size_write(new_dentry->d_inode, file_size_save);
 out_lock:
        unlock_dir(lower_dir_dentry);
@@ -499,8 +499,8 @@ static int ecryptfs_unlink(struct inode *dir, struct dentry *dentry)
                goto out_unlock;
        }
        fsstack_copy_attr_times(dir, lower_dir_inode);
-        dentry->d_inode->i_nlink =
+        set_nlink(dentry->d_inode,
-                ecryptfs_inode_to_lower(dentry->d_inode)->i_nlink;
+                  ecryptfs_inode_to_lower(dentry->d_inode)->i_nlink);
        dentry->d_inode->i_ctime = dir->i_ctime;
        d_drop(dentry);
 out_unlock:
@@ -565,7 +565,7 @@ static int ecryptfs_mkdir(struct inode *dir, struct dentry *dentry, int mode)
                goto out;
        fsstack_copy_attr_times(dir, lower_dir_dentry->d_inode);
        fsstack_copy_inode_size(dir, lower_dir_dentry->d_inode);
-        dir->i_nlink = lower_dir_dentry->d_inode->i_nlink;
+        set_nlink(dir, lower_dir_dentry->d_inode->i_nlink);
 out:
        unlock_dir(lower_dir_dentry);
        if (!dentry->d_inode)
@@ -588,7 +588,7 @@ static int ecryptfs_rmdir(struct inode *dir, struct dentry *dentry)
        if (!rc && dentry->d_inode)
                clear_nlink(dentry->d_inode);
        fsstack_copy_attr_times(dir, lower_dir_dentry->d_inode);
-        dir->i_nlink = lower_dir_dentry->d_inode->i_nlink;
+        set_nlink(dir, lower_dir_dentry->d_inode->i_nlink);
        unlock_dir(lower_dir_dentry);
        if (!rc)
                d_drop(dentry);
diff --git a/fs/efs/inode.c b/fs/efs/inode.c
index 9c13412e6c99..bc84f365d75c 100644
--- a/fs/efs/inode.c
+++ b/fs/efs/inode.c
@@ -96,7 +96,7 @@ struct inode *efs_iget(struct super_block *super, unsigned long ino)
        efs_inode = (struct efs_dinode *) (bh->b_data + offset);
    
        inode->i_mode  = be16_to_cpu(efs_inode->di_mode);
-        inode->i_nlink = be16_to_cpu(efs_inode->di_nlink);
+        set_nlink(inode, be16_to_cpu(efs_inode->di_nlink));
        inode->i_uid   = (uid_t)be16_to_cpu(efs_inode->di_uid);
        inode->i_gid   = (gid_t)be16_to_cpu(efs_inode->di_gid);
        inode->i_size  = be32_to_cpu(efs_inode->di_size);
diff --git a/fs/exofs/inode.c b/fs/exofs/inode.c
index 3e5f3a6be90a..f6dbf7768ce6 100644
--- a/fs/exofs/inode.c
+++ b/fs/exofs/inode.c
@@ -1165,7 +1165,7 @@ struct inode *exofs_iget(struct super_block *sb, unsigned long ino)
        inode->i_mode = le16_to_cpu(fcb.i_mode);
        inode->i_uid = le32_to_cpu(fcb.i_uid);
        inode->i_gid = le32_to_cpu(fcb.i_gid);
-        inode->i_nlink = le16_to_cpu(fcb.i_links_count);
+        set_nlink(inode, le16_to_cpu(fcb.i_links_count));
        inode->i_ctime.tv_sec = (signed)le32_to_cpu(fcb.i_ctime);
        inode->i_atime.tv_sec = (signed)le32_to_cpu(fcb.i_atime);
        inode->i_mtime.tv_sec = (signed)le32_to_cpu(fcb.i_mtime);
diff --git a/fs/ext2/balloc.c b/fs/ext2/balloc.c
index 8f44cef1b3ef..a8cbe1bc6ad4 100644
--- a/fs/ext2/balloc.c
+++ b/fs/ext2/balloc.c
@@ -421,7 +421,7 @@ static inline int rsv_is_empty(struct ext2_reserve_window *rsv)
 void ext2_init_block_alloc_info(struct inode *inode)
 {
        struct ext2_inode_info *ei = EXT2_I(inode);
-        struct ext2_block_alloc_info *block_i = ei->i_block_alloc_info;
+        struct ext2_block_alloc_info *block_i;
        struct super_block *sb = inode->i_sb;
        block_i = kmalloc(sizeof(*block_i), GFP_NOFS);
diff --git a/fs/ext2/ialloc.c b/fs/ext2/ialloc.c
index ee9ed31948e1..c4e81dfb74ba 100644
--- a/fs/ext2/ialloc.c
+++ b/fs/ext2/ialloc.c
@@ -601,7 +601,7 @@ fail_free_drop:
 fail_drop:
        dquot_drop(inode);
        inode->i_flags |= S_NOQUOTA;
-        inode->i_nlink = 0;
+        clear_nlink(inode);
        unlock_new_inode(inode);
        iput(inode);
        return ERR_PTR(err);
diff --git a/fs/ext2/inode.c b/fs/ext2/inode.c
index a8a58f63f07c..91a6945af6d8 100644
--- a/fs/ext2/inode.c
+++ b/fs/ext2/inode.c
@@ -1321,7 +1321,7 @@ struct inode *ext2_iget (struct super_block *sb, unsigned long ino)
                inode->i_uid |= le16_to_cpu(raw_inode->i_uid_high) << 16;
                inode->i_gid |= le16_to_cpu(raw_inode->i_gid_high) << 16;
        }
-        inode->i_nlink = le16_to_cpu(raw_inode->i_links_count);
+        set_nlink(inode, le16_to_cpu(raw_inode->i_links_count));
        inode->i_size = le32_to_cpu(raw_inode->i_size);
        inode->i_atime.tv_sec = (signed)le32_to_cpu(raw_inode->i_atime);
        inode->i_ctime.tv_sec = (signed)le32_to_cpu(raw_inode->i_ctime);
diff --git a/fs/ext2/super.c b/fs/ext2/super.c
index 1dd62ed35b85..bd8ac164a3bf 100644
--- a/fs/ext2/super.c
+++ b/fs/ext2/super.c
@@ -327,10 +327,10 @@ static struct inode *ext2_nfs_get_inode(struct super_block *sb,
        if (ino > le32_to_cpu(EXT2_SB(sb)->s_es->s_inodes_count))
                return ERR_PTR(-ESTALE);
-        /* iget isn't really right if the inode is currently unallocated!!
+        /*
-         * ext2_read_inode currently does appropriate checks, but
+         * ext2_iget isn't quite right if the inode is currently unallocated!
-         * it might be "neater" to call ext2_get_inode first and check
+         * However ext2_iget currently does appropriate checks to handle stale
-         * if the inode is valid.....
+         * inodes so everything is OK.
         */
        inode = ext2_iget(sb, ino);
        if (IS_ERR(inode))
diff --git a/fs/ext3/balloc.c b/fs/ext3/balloc.c
index 6386d76f44a7..a2038928f9a3 100644
--- a/fs/ext3/balloc.c
+++ b/fs/ext3/balloc.c
@@ -427,7 +427,7 @@ static inline int rsv_is_empty(struct ext3_reserve_window *rsv)
 void ext3_init_block_alloc_info(struct inode *inode)
 {
        struct ext3_inode_info *ei = EXT3_I(inode);
-        struct ext3_block_alloc_info *block_i = ei->i_block_alloc_info;
+        struct ext3_block_alloc_info *block_i;
        struct super_block *sb = inode->i_sb;
        block_i = kmalloc(sizeof(*block_i), GFP_NOFS);
@@ -1440,14 +1440,14 @@ out:
 *
 * Check if filesystem has at least 1 free block available for allocation.
 */
-static int ext3_has_free_blocks(struct ext3_sb_info *sbi)
+static int ext3_has_free_blocks(struct ext3_sb_info *sbi, int use_reservation)
 {
        ext3_fsblk_t free_blocks, root_blocks;
        free_blocks = percpu_counter_read_positive(&sbi->s_freeblocks_counter);
        root_blocks = le32_to_cpu(sbi->s_es->s_r_blocks_count);
        if (free_blocks < root_blocks + 1 && !capable(CAP_SYS_RESOURCE) &&
-                sbi->s_resuid != current_fsuid() &&
+                !use_reservation && sbi->s_resuid != current_fsuid() &&
                (sbi->s_resgid == 0 || !in_group_p (sbi->s_resgid))) {
                return 0;
        }
@@ -1468,7 +1468,7 @@ static int ext3_has_free_blocks(struct ext3_sb_info *sbi)
 */
 int ext3_should_retry_alloc(struct super_block *sb, int *retries)
 {
-        if (!ext3_has_free_blocks(EXT3_SB(sb)) || (*retries)++ > 3)
+        if (!ext3_has_free_blocks(EXT3_SB(sb), 0) || (*retries)++ > 3)
                return 0;
        jbd_debug(1, "%s: retrying operation after ENOSPC\n", sb->s_id);
@@ -1546,7 +1546,7 @@ ext3_fsblk_t ext3_new_blocks(handle_t *handle, struct inode *inode,
        if (block_i && ((windowsz = block_i->rsv_window_node.rsv_goal_size) > 0))
                my_rsv = &block_i->rsv_window_node;
-        if (!ext3_has_free_blocks(sbi)) {
+        if (!ext3_has_free_blocks(sbi, IS_NOQUOTA(inode))) {
                *errp = -ENOSPC;
                goto out;
        }
@@ -1924,9 +1924,10 @@ unsigned long ext3_bg_num_gdb(struct super_block *sb, int group)
 * reaches any used block. Then issue a TRIM command on this extent and free
 * the extent in the block bitmap. This is done until whole group is scanned.
 */
-ext3_grpblk_t ext3_trim_all_free(struct super_block *sb, unsigned int group,
+static ext3_grpblk_t ext3_trim_all_free(struct super_block *sb,
-                                ext3_grpblk_t start, ext3_grpblk_t max,
+                                        unsigned int group,
-                                ext3_grpblk_t minblocks)
+                                        ext3_grpblk_t start, ext3_grpblk_t max,
+                                        ext3_grpblk_t minblocks)
 {
        handle_t *handle;
        ext3_grpblk_t next, free_blocks, bit, freed, count = 0;
diff --git a/fs/ext3/fsync.c b/fs/ext3/fsync.c
index d494c554c6e6..1860ed356323 100644
--- a/fs/ext3/fsync.c
+++ b/fs/ext3/fsync.c
@@ -61,13 +61,6 @@ int ext3_sync_file(struct file *file, loff_t start, loff_t end, int datasync)
        if (ret)
                goto out;
-        /*
-         * Taking the mutex here just to keep consistent with how fsync was
-         * called previously, however it looks like we don't need to take
-         * i_mutex at all.
-         */
-        mutex_lock(&inode->i_mutex);
        J_ASSERT(ext3_journal_current_handle() == NULL);
        /*
@@ -85,7 +78,6 @@ int ext3_sync_file(struct file *file, loff_t start, loff_t end, int datasync)
         *  safe in-journal, which is all fsync() needs to ensure.
         */
        if (ext3_should_journal_data(inode)) {
-                mutex_unlock(&inode->i_mutex);
                ret = ext3_force_commit(inode->i_sb);
                goto out;
        }
@@ -108,8 +100,6 @@ int ext3_sync_file(struct file *file, loff_t start, loff_t end, int datasync)
         */
        if (needs_barrier)
                blkdev_issue_flush(inode->i_sb->s_bdev, GFP_KERNEL, NULL);
-        mutex_unlock(&inode->i_mutex);
 out:
        trace_ext3_sync_file_exit(inode, ret);
        return ret;
diff --git a/fs/ext3/ialloc.c b/fs/ext3/ialloc.c
index bf09cbf938cc..5c866e06e7ab 100644
--- a/fs/ext3/ialloc.c
+++ b/fs/ext3/ialloc.c
@@ -178,42 +178,6 @@ error_return:
 }
 /*
- * There are two policies for allocating an inode.  If the new inode is
- * a directory, then a forward search is made for a block group with both
- * free space and a low directory-to-inode ratio; if that fails, then of
- * the groups with above-average free space, that group with the fewest
- * directories already is chosen.
- *
- * For other inodes, search forward from the parent directory\'s block
- * group to find a free inode.
- */
-static int find_group_dir(struct super_block *sb, struct inode *parent)
-{
-        int ngroups = EXT3_SB(sb)->s_groups_count;
-        unsigned int freei, avefreei;
-        struct ext3_group_desc *desc, *best_desc = NULL;
-        int group, best_group = -1;
-        freei = percpu_counter_read_positive(&EXT3_SB(sb)->s_freeinodes_counter);
-        avefreei = freei / ngroups;
-        for (group = 0; group < ngroups; group++) {
-                desc = ext3_get_group_desc (sb, group, NULL);
-                if (!desc || !desc->bg_free_inodes_count)
-                        continue;
-                if (le16_to_cpu(desc->bg_free_inodes_count) < avefreei)
-                        continue;
-                if (!best_desc ||
-                    (le16_to_cpu(desc->bg_free_blocks_count) >
-                     le16_to_cpu(best_desc->bg_free_blocks_count))) {
-                        best_group = group;
-                        best_desc = desc;
-                }
-        }
-        return best_group;
-}
-/*
 * Orlov's allocator for directories.
 *
 * We always try to spread first-level directories.
@@ -436,12 +400,9 @@ struct inode *ext3_new_inode(handle_t *handle, struct inode * dir,
        sbi = EXT3_SB(sb);
        es = sbi->s_es;
-        if (S_ISDIR(mode)) {
+        if (S_ISDIR(mode))
-                if (test_opt (sb, OLDALLOC))
+                group = find_group_orlov(sb, dir);
-                        group = find_group_dir(sb, dir);
+        else
-                else
-                        group = find_group_orlov(sb, dir);
-        } else
                group = find_group_other(sb, dir);
        err = -ENOSPC;
@@ -621,7 +582,7 @@ fail_free_drop:
 fail_drop:
        dquot_drop(inode);
        inode->i_flags |= S_NOQUOTA;
-        inode->i_nlink = 0;
+        clear_nlink(inode);
        unlock_new_inode(inode);
        iput(inode);
        brelse(bitmap_bh);
diff --git a/fs/ext3/inode.c b/fs/ext3/inode.c
index 12661e1deedd..85fe655fe3e0 100644
--- a/fs/ext3/inode.c
+++ b/fs/ext3/inode.c
@@ -2899,7 +2899,7 @@ struct inode *ext3_iget(struct super_block *sb, unsigned long ino)
                inode->i_uid |= le16_to_cpu(raw_inode->i_uid_high) << 16;
                inode->i_gid |= le16_to_cpu(raw_inode->i_gid_high) << 16;
        }
-        inode->i_nlink = le16_to_cpu(raw_inode->i_links_count);
+        set_nlink(inode, le16_to_cpu(raw_inode->i_links_count));
        inode->i_size = le32_to_cpu(raw_inode->i_size);
        inode->i_atime.tv_sec = (signed)le32_to_cpu(raw_inode->i_atime);
        inode->i_ctime.tv_sec = (signed)le32_to_cpu(raw_inode->i_ctime);
diff --git a/fs/ext3/ioctl.c b/fs/ext3/ioctl.c
index c7f43944f160..ba1b54e23cae 100644
--- a/fs/ext3/ioctl.c
+++ b/fs/ext3/ioctl.c
@@ -150,30 +150,6 @@ setversion_out:
                mnt_drop_write(filp->f_path.mnt);
                return err;
        }
-#ifdef CONFIG_JBD_DEBUG
-        case EXT3_IOC_WAIT_FOR_READONLY:
-                /*
-                 * This is racy - by the time we're woken up and running,
-                 * the superblock could be released.  And the module could
-                 * have been unloaded.  So sue me.
-                 *
-                 * Returns 1 if it slept, else zero.
-                 */
-                {
-                        struct super_block *sb = inode->i_sb;
-                        DECLARE_WAITQUEUE(wait, current);
-                        int ret = 0;
-                        set_current_state(TASK_INTERRUPTIBLE);
-                        add_wait_queue(&EXT3_SB(sb)->ro_wait_queue, &wait);
-                        if (timer_pending(&EXT3_SB(sb)->turn_ro_timer)) {
-                                schedule();
-                                ret = 1;
-                        }
-                        remove_wait_queue(&EXT3_SB(sb)->ro_wait_queue, &wait);
-                        return ret;
-                }
-#endif
        case EXT3_IOC_GETRSVSZ:
                if (test_opt(inode->i_sb, RESERVATION)
                        && S_ISREG(inode->i_mode)
diff --git a/fs/ext3/namei.c b/fs/ext3/namei.c
index 0629e09f6511..642dc6d66dfd 100644
--- a/fs/ext3/namei.c
+++ b/fs/ext3/namei.c
@@ -1821,7 +1821,7 @@ retry:
        de->name_len = 2;
        strcpy (de->name, "..");
        ext3_set_de_type(dir->i_sb, de, S_IFDIR);
-        inode->i_nlink = 2;
+        set_nlink(inode, 2);
        BUFFER_TRACE(dir_block, "call ext3_journal_dirty_metadata");
        err = ext3_journal_dirty_metadata(handle, dir_block);
        if (err)
@@ -1833,7 +1833,7 @@ retry:
        if (err) {
 out_clear_inode:
-                inode->i_nlink = 0;
+                clear_nlink(inode);
                unlock_new_inode(inode);
                ext3_mark_inode_dirty(handle, inode);
                iput (inode);
@@ -2170,7 +2170,7 @@ static int ext3_unlink(struct inode * dir, struct dentry *dentry)
                ext3_warning (inode->i_sb, "ext3_unlink",
                              "Deleting nonexistent file (%lu), %d",
                              inode->i_ino, inode->i_nlink);
-                inode->i_nlink = 1;
+                set_nlink(inode, 1);
        }
        retval = ext3_delete_entry(handle, dir, de, bh);
        if (retval)
diff --git a/fs/ext3/super.c b/fs/ext3/super.c
index 7beb69ae0015..922d289aeeb3 100644
--- a/fs/ext3/super.c
+++ b/fs/ext3/super.c
@@ -652,8 +652,6 @@ static int ext3_show_options(struct seq_file *seq, struct vfsmount *vfs)
                seq_puts(seq, ",nouid32");
        if (test_opt(sb, DEBUG))
                seq_puts(seq, ",debug");
-        if (test_opt(sb, OLDALLOC))
-                seq_puts(seq, ",oldalloc");
 #ifdef CONFIG_EXT3_FS_XATTR
        if (test_opt(sb, XATTR_USER))
                seq_puts(seq, ",user_xattr");
@@ -1049,10 +1047,12 @@ static int parse_options (char *options, struct super_block *sb,
                        set_opt (sbi->s_mount_opt, DEBUG);
                        break;
                case Opt_oldalloc:
-                        set_opt (sbi->s_mount_opt, OLDALLOC);
+                        ext3_msg(sb, KERN_WARNING,
+                                "Ignoring deprecated oldalloc option");
                        break;
                case Opt_orlov:
-                        clear_opt (sbi->s_mount_opt, OLDALLOC);
+                        ext3_msg(sb, KERN_WARNING,
+                                "Ignoring deprecated orlov option");
                        break;
 #ifdef CONFIG_EXT3_FS_XATTR
                case Opt_user_xattr:
@@ -2669,13 +2669,13 @@ static int ext3_remount (struct super_block * sb, int * flags, char * data)
                        /*
                         * If we have an unprocessed orphan list hanging
                         * around from a previously readonly bdev mount,
-                         * require a full umount/remount for now.
+                         * require a full umount & mount for now.
                         */
                        if (es->s_last_orphan) {
                                ext3_msg(sb, KERN_WARNING, "warning: couldn't "
                                       "remount RDWR because of unprocessed "
                                       "orphan inode list.  Please "
-                                       "umount/remount instead.");
+                                       "umount & mount instead.");
                                err = -EINVAL;
                                goto restore_opts;
                        }
diff --git a/fs/ext4/balloc.c b/fs/ext4/balloc.c
index f8224adf496e..f6dba4505f1c 100644
--- a/fs/ext4/balloc.c
+++ b/fs/ext4/balloc.c
@@ -28,7 +28,8 @@
 */
 /*
- * Calculate the block group number and offset, given a block number
+ * Calculate the block group number and offset into the block/cluster
+ * allocation bitmap, given a block number
 */
 void ext4_get_group_no_and_offset(struct super_block *sb, ext4_fsblk_t blocknr,
                ext4_group_t *blockgrpp, ext4_grpblk_t *offsetp)
@@ -37,7 +38,8 @@ void ext4_get_group_no_and_offset(struct super_block *sb, ext4_fsblk_t blocknr,
        ext4_grpblk_t offset;
        blocknr = blocknr - le32_to_cpu(es->s_first_data_block);
-        offset = do_div(blocknr, EXT4_BLOCKS_PER_GROUP(sb));
+        offset = do_div(blocknr, EXT4_BLOCKS_PER_GROUP(sb)) >>
+                EXT4_SB(sb)->s_cluster_bits;
        if (offsetp)
                *offsetp = offset;
        if (blockgrpp)
@@ -55,130 +57,169 @@ static int ext4_block_in_group(struct super_block *sb, ext4_fsblk_t block,
        return 0;
 }
-static int ext4_group_used_meta_blocks(struct super_block *sb,
+/* Return the number of clusters used for file system metadata; this
-                                       ext4_group_t block_group,
+ * represents the overhead needed by the file system.
-                                       struct ext4_group_desc *gdp)
+ */
+unsigned ext4_num_overhead_clusters(struct super_block *sb,
+                                    ext4_group_t block_group,
+                                    struct ext4_group_desc *gdp)
 {
-        ext4_fsblk_t tmp;
+        unsigned num_clusters;
+        int block_cluster = -1, inode_cluster = -1, itbl_cluster = -1, i, c;
+        ext4_fsblk_t start = ext4_group_first_block_no(sb, block_group);
+        ext4_fsblk_t itbl_blk;
        struct ext4_sb_info *sbi = EXT4_SB(sb);
-        /* block bitmap, inode bitmap, and inode table blocks */
-        int used_blocks = sbi->s_itb_per_group + 2;
-        if (EXT4_HAS_INCOMPAT_FEATURE(sb, EXT4_FEATURE_INCOMPAT_FLEX_BG)) {
+        /* This is the number of clusters used by the superblock,
-                if (!ext4_block_in_group(sb, ext4_block_bitmap(sb, gdp),
+         * block group descriptors, and reserved block group
-                                        block_group))
+         * descriptor blocks */
-                        used_blocks--;
+        num_clusters = ext4_num_base_meta_clusters(sb, block_group);
-                if (!ext4_block_in_group(sb, ext4_inode_bitmap(sb, gdp),
+        /*
-                                        block_group))
+         * For the allocation bitmaps and inode table, we first need
-                        used_blocks--;
+         * to check to see if the block is in the block group.  If it
+         * is, then check to see if the cluster is already accounted
-                tmp = ext4_inode_table(sb, gdp);
+         * for in the clusters used for the base metadata cluster, or
-                for (; tmp < ext4_inode_table(sb, gdp) +
+         * if we can increment the base metadata cluster to include
-                                sbi->s_itb_per_group; tmp++) {
+         * that block.  Otherwise, we will have to track the cluster
-                        if (!ext4_block_in_group(sb, tmp, block_group))
+         * used for the allocation bitmap or inode table explicitly.
-                                used_blocks -= 1;
+         * Normally all of these blocks are contiguous, so the special
+         * case handling shouldn't be necessary except for *very*
+         * unusual file system layouts.
+         */
+        if (ext4_block_in_group(sb, ext4_block_bitmap(sb, gdp), block_group)) {
+                block_cluster = EXT4_B2C(sbi, (start -
+                                               ext4_block_bitmap(sb, gdp)));
+                if (block_cluster < num_clusters)
+                        block_cluster = -1;
+                else if (block_cluster == num_clusters) {
+                        num_clusters++;
+                        block_cluster = -1;
                }
        }
-        return used_blocks;
-}
-/* Initializes an uninitialized block bitmap if given, and returns the
+        if (ext4_block_in_group(sb, ext4_inode_bitmap(sb, gdp), block_group)) {
- * number of blocks free in the group. */
+                inode_cluster = EXT4_B2C(sbi,
-unsigned ext4_init_block_bitmap(struct super_block *sb, struct buffer_head *bh,
+                                         start - ext4_inode_bitmap(sb, gdp));
-                 ext4_group_t block_group, struct ext4_group_desc *gdp)
+                if (inode_cluster < num_clusters)
-{
+                        inode_cluster = -1;
-        int bit, bit_max;
+                else if (inode_cluster == num_clusters) {
-        ext4_group_t ngroups = ext4_get_groups_count(sb);
+                        num_clusters++;
-        unsigned free_blocks, group_blocks;
+                        inode_cluster = -1;
-        struct ext4_sb_info *sbi = EXT4_SB(sb);
-        if (bh) {
-                J_ASSERT_BH(bh, buffer_locked(bh));
-                /* If checksum is bad mark all blocks used to prevent allocation
-                 * essentially implementing a per-group read-only flag. */
-                if (!ext4_group_desc_csum_verify(sbi, block_group, gdp)) {
-                        ext4_error(sb, "Checksum bad for group %u",
-                                        block_group);
-                        ext4_free_blks_set(sb, gdp, 0);
-                        ext4_free_inodes_set(sb, gdp, 0);
-                        ext4_itable_unused_set(sb, gdp, 0);
-                        memset(bh->b_data, 0xff, sb->s_blocksize);
-                        return 0;
                }
-                memset(bh->b_data, 0, sb->s_blocksize);
        }
-        /* Check for superblock and gdt backups in this group */
+        itbl_blk = ext4_inode_table(sb, gdp);
-        bit_max = ext4_bg_has_super(sb, block_group);
+        for (i = 0; i < sbi->s_itb_per_group; i++) {
+                if (ext4_block_in_group(sb, itbl_blk + i, block_group)) {
-        if (!EXT4_HAS_INCOMPAT_FEATURE(sb, EXT4_FEATURE_INCOMPAT_META_BG) ||
+                        c = EXT4_B2C(sbi, start - itbl_blk + i);
-            block_group < le32_to_cpu(sbi->s_es->s_first_meta_bg) *
+                        if ((c < num_clusters) || (c == inode_cluster) ||
-                          sbi->s_desc_per_block) {
+                            (c == block_cluster) || (c == itbl_cluster))
-                if (bit_max) {
+                                continue;
-                        bit_max += ext4_bg_num_gdb(sb, block_group);
+                        if (c == num_clusters) {
-                        bit_max +=
+                                num_clusters++;
-                                le16_to_cpu(sbi->s_es->s_reserved_gdt_blocks);
+                                continue;
+                        }
+                        num_clusters++;
+                        itbl_cluster = c;
                }
-        } else { /* For META_BG_BLOCK_GROUPS */
-                bit_max += ext4_bg_num_gdb(sb, block_group);
        }
-        if (block_group == ngroups - 1) {
+        if (block_cluster != -1)
+                num_clusters++;
+        if (inode_cluster != -1)
+                num_clusters++;
+        return num_clusters;
+}
+static unsigned int num_clusters_in_group(struct super_block *sb,
+                                          ext4_group_t block_group)
+{
+        unsigned int blocks;
+        if (block_group == ext4_get_groups_count(sb) - 1) {
                /*
-                 * Even though mke2fs always initialize first and last group
+                 * Even though mke2fs always initializes the first and
-                 * if some other tool enabled the EXT4_BG_BLOCK_UNINIT we need
+                 * last group, just in case some other tool was used,
-                 * to make sure we calculate the right free blocks
+                 * we need to make sure we calculate the right free
+                 * blocks.
                 */
-                group_blocks = ext4_blocks_count(sbi->s_es) -
+                blocks = ext4_blocks_count(EXT4_SB(sb)->s_es) -
-                        ext4_group_first_block_no(sb, ngroups - 1);
+                        ext4_group_first_block_no(sb, block_group);
-        } else {
+        } else
-                group_blocks = EXT4_BLOCKS_PER_GROUP(sb);
+                blocks = EXT4_BLOCKS_PER_GROUP(sb);
-        }
+        return EXT4_NUM_B2C(EXT4_SB(sb), blocks);
+}
-        free_blocks = group_blocks - bit_max;
+/* Initializes an uninitialized block bitmap */
+void ext4_init_block_bitmap(struct super_block *sb, struct buffer_head *bh,
+                            ext4_group_t block_group,
+                            struct ext4_group_desc *gdp)
+{
+        unsigned int bit, bit_max;
+        struct ext4_sb_info *sbi = EXT4_SB(sb);
+        ext4_fsblk_t start, tmp;
+        int flex_bg = 0;
+        J_ASSERT_BH(bh, buffer_locked(bh));
+        /* If checksum is bad mark all blocks used to prevent allocation
+         * essentially implementing a per-group read-only flag. */
+        if (!ext4_group_desc_csum_verify(sbi, block_group, gdp)) {
+                ext4_error(sb, "Checksum bad for group %u", block_group);
+                ext4_free_group_clusters_set(sb, gdp, 0);
+                ext4_free_inodes_set(sb, gdp, 0);
+                ext4_itable_unused_set(sb, gdp, 0);
+                memset(bh->b_data, 0xff, sb->s_blocksize);
+                return;
+        }
+        memset(bh->b_data, 0, sb->s_blocksize);
-        if (bh) {
+        bit_max = ext4_num_base_meta_clusters(sb, block_group);
-                ext4_fsblk_t start, tmp;
+        for (bit = 0; bit < bit_max; bit++)
-                int flex_bg = 0;
+                ext4_set_bit(bit, bh->b_data);
-                for (bit = 0; bit < bit_max; bit++)
+        start = ext4_group_first_block_no(sb, block_group);
-                        ext4_set_bit(bit, bh->b_data);
-                start = ext4_group_first_block_no(sb, block_group);
+        if (EXT4_HAS_INCOMPAT_FEATURE(sb, EXT4_FEATURE_INCOMPAT_FLEX_BG))
+                flex_bg = 1;
-                if (EXT4_HAS_INCOMPAT_FEATURE(sb,
+        /* Set bits for block and inode bitmaps, and inode table */
-                                              EXT4_FEATURE_INCOMPAT_FLEX_BG))
+        tmp = ext4_block_bitmap(sb, gdp);
-                        flex_bg = 1;
+        if (!flex_bg || ext4_block_in_group(sb, tmp, block_group))
+                ext4_set_bit(EXT4_B2C(sbi, tmp - start), bh->b_data);
-                /* Set bits for block and inode bitmaps, and inode table */
+        tmp = ext4_inode_bitmap(sb, gdp);
-                tmp = ext4_block_bitmap(sb, gdp);
+        if (!flex_bg || ext4_block_in_group(sb, tmp, block_group))
-                if (!flex_bg || ext4_block_in_group(sb, tmp, block_group))
+                ext4_set_bit(EXT4_B2C(sbi, tmp - start), bh->b_data);
-                        ext4_set_bit(tmp - start, bh->b_data);
-                tmp = ext4_inode_bitmap(sb, gdp);
+        tmp = ext4_inode_table(sb, gdp);
+        for (; tmp < ext4_inode_table(sb, gdp) +
+                     sbi->s_itb_per_group; tmp++) {
                if (!flex_bg || ext4_block_in_group(sb, tmp, block_group))
-                        ext4_set_bit(tmp - start, bh->b_data);
+                        ext4_set_bit(EXT4_B2C(sbi, tmp - start), bh->b_data);
-                tmp = ext4_inode_table(sb, gdp);
-                for (; tmp < ext4_inode_table(sb, gdp) +
-                                sbi->s_itb_per_group; tmp++) {
-                        if (!flex_bg ||
-                                ext4_block_in_group(sb, tmp, block_group))
-                                ext4_set_bit(tmp - start, bh->b_data);
-                }
-                /*
-                 * Also if the number of blocks within the group is
-                 * less than the blocksize * 8 ( which is the size
-                 * of bitmap ), set rest of the block bitmap to 1
-                 */
-                ext4_mark_bitmap_end(group_blocks, sb->s_blocksize * 8,
-                                     bh->b_data);
        }
-        return free_blocks - ext4_group_used_meta_blocks(sb, block_group, gdp);
+        /*
+         * Also if the number of blocks within the group is less than
+         * the blocksize * 8 ( which is the size of bitmap ), set rest
+         * of the block bitmap to 1
+         */
+        ext4_mark_bitmap_end(num_clusters_in_group(sb, block_group),
+                             sb->s_blocksize * 8, bh->b_data);
 }
+/* Return the number of free blocks in a block group.  It is used when
+ * the block bitmap is uninitialized, so we can't just count the bits
+ * in the bitmap. */
+unsigned ext4_free_clusters_after_init(struct super_block *sb,
+                                       ext4_group_t block_group,
+                                       struct ext4_group_desc *gdp)
+{
+        return num_clusters_in_group(sb, block_group) - 
+                ext4_num_overhead_clusters(sb, block_group, gdp);
+}
 /*
 * The free blocks are managed by bitmaps.  A file system contains several
@@ -362,53 +403,54 @@ ext4_read_block_bitmap(struct super_block *sb, ext4_group_t block_group)
 }
 /**
- * ext4_has_free_blocks()
+ * ext4_has_free_clusters()
 * @sbi:        in-core super block structure.
- * @nblocks:    number of needed blocks
+ * @nclusters:  number of needed blocks
+ * @flags:      flags from ext4_mb_new_blocks()
 *
- * Check if filesystem has nblocks free & available for allocation.
+ * Check if filesystem has nclusters free & available for allocation.
 * On success return 1, return 0 on failure.
 */
-static int ext4_has_free_blocks(struct ext4_sb_info *sbi,
+static int ext4_has_free_clusters(struct ext4_sb_info *sbi,
-                                s64 nblocks, unsigned int flags)
+                                  s64 nclusters, unsigned int flags)
 {
-        s64 free_blocks, dirty_blocks, root_blocks;
+        s64 free_clusters, dirty_clusters, root_clusters;
-        struct percpu_counter *fbc = &sbi->s_freeblocks_counter;
+        struct percpu_counter *fcc = &sbi->s_freeclusters_counter;
-        struct percpu_counter *dbc = &sbi->s_dirtyblocks_counter;
+        struct percpu_counter *dcc = &sbi->s_dirtyclusters_counter;
-        free_blocks  = percpu_counter_read_positive(fbc);
+        free_clusters  = percpu_counter_read_positive(fcc);
-        dirty_blocks = percpu_counter_read_positive(dbc);
+        dirty_clusters = percpu_counter_read_positive(dcc);
-        root_blocks = ext4_r_blocks_count(sbi->s_es);
+        root_clusters = EXT4_B2C(sbi, ext4_r_blocks_count(sbi->s_es));
-        if (free_blocks - (nblocks + root_blocks + dirty_blocks) <
+        if (free_clusters - (nclusters + root_clusters + dirty_clusters) <
-                                                EXT4_FREEBLOCKS_WATERMARK) {
+                                        EXT4_FREECLUSTERS_WATERMARK) {
-                free_blocks  = percpu_counter_sum_positive(fbc);
+                free_clusters  = EXT4_C2B(sbi, percpu_counter_sum_positive(fcc));
-                dirty_blocks = percpu_counter_sum_positive(dbc);
+                dirty_clusters = percpu_counter_sum_positive(dcc);
        }
-        /* Check whether we have space after
+        /* Check whether we have space after accounting for current
-         * accounting for current dirty blocks & root reserved blocks.
+         * dirty clusters & root reserved clusters.
         */
-        if (free_blocks >= ((root_blocks + nblocks) + dirty_blocks))
+        if (free_clusters >= ((root_clusters + nclusters) + dirty_clusters))
                return 1;
-        /* Hm, nope.  Are (enough) root reserved blocks available? */
+        /* Hm, nope.  Are (enough) root reserved clusters available? */
        if (sbi->s_resuid == current_fsuid() ||
            ((sbi->s_resgid != 0) && in_group_p(sbi->s_resgid)) ||
            capable(CAP_SYS_RESOURCE) ||
                (flags & EXT4_MB_USE_ROOT_BLOCKS)) {
-                if (free_blocks >= (nblocks + dirty_blocks))
+                if (free_clusters >= (nclusters + dirty_clusters))
                        return 1;
        }
        return 0;
 }
-int ext4_claim_free_blocks(struct ext4_sb_info *sbi,
+int ext4_claim_free_clusters(struct ext4_sb_info *sbi,
-                           s64 nblocks, unsigned int flags)
+                             s64 nclusters, unsigned int flags)
 {
-        if (ext4_has_free_blocks(sbi, nblocks, flags)) {
+        if (ext4_has_free_clusters(sbi, nclusters, flags)) {
-                percpu_counter_add(&sbi->s_dirtyblocks_counter, nblocks);
+                percpu_counter_add(&sbi->s_dirtyclusters_counter, nclusters);
                return 0;
        } else
                return -ENOSPC;
@@ -428,7 +470,7 @@ int ext4_claim_free_blocks(struct ext4_sb_info *sbi,
 */
 int ext4_should_retry_alloc(struct super_block *sb, int *retries)
 {
-        if (!ext4_has_free_blocks(EXT4_SB(sb), 1, 0) ||
+        if (!ext4_has_free_clusters(EXT4_SB(sb), 1, 0) ||
            (*retries)++ > 3 ||
            !EXT4_SB(sb)->s_journal)
                return 0;
@@ -444,7 +486,7 @@ int ext4_should_retry_alloc(struct super_block *sb, int *retries)
 * @handle:             handle to this transaction
 * @inode:              file inode
 * @goal:               given target block(filesystem wide)
- * @count:              pointer to total number of blocks needed
+ * @count:              pointer to total number of clusters needed
 * @errp:               error code
 *
 * Return 1st allocated block number on success, *count stores total account
@@ -476,18 +518,19 @@ ext4_fsblk_t ext4_new_meta_blocks(handle_t *handle, struct inode *inode,
                spin_lock(&EXT4_I(inode)->i_block_reservation_lock);
                EXT4_I(inode)->i_allocated_meta_blocks += ar.len;
                spin_unlock(&EXT4_I(inode)->i_block_reservation_lock);
-                dquot_alloc_block_nofail(inode, ar.len);
+                dquot_alloc_block_nofail(inode,
+                                EXT4_C2B(EXT4_SB(inode->i_sb), ar.len));
        }
        return ret;
 }
 /**
- * ext4_count_free_blocks() -- count filesystem free blocks
+ * ext4_count_free_clusters() -- count filesystem free clusters
 * @sb:         superblock
 *
- * Adds up the number of free blocks from each block group.
+ * Adds up the number of free clusters from each block group.
 */
-ext4_fsblk_t ext4_count_free_blocks(struct super_block *sb)
+ext4_fsblk_t ext4_count_free_clusters(struct super_block *sb)
 {
        ext4_fsblk_t desc_count;
        struct ext4_group_desc *gdp;
@@ -508,7 +551,7 @@ ext4_fsblk_t ext4_count_free_blocks(struct super_block *sb)
                gdp = ext4_get_group_desc(sb, i, NULL);
                if (!gdp)
                        continue;
-                desc_count += ext4_free_blks_count(sb, gdp);
+                desc_count += ext4_free_group_clusters(sb, gdp);
                brelse(bitmap_bh);
                bitmap_bh = ext4_read_block_bitmap(sb, i);
                if (bitmap_bh == NULL)
@@ -516,12 +559,13 @@ ext4_fsblk_t ext4_count_free_blocks(struct super_block *sb)
                x = ext4_count_free(bitmap_bh, sb->s_blocksize);
                printk(KERN_DEBUG "group %u: stored = %d, counted = %u\n",
-                        i, ext4_free_blks_count(sb, gdp), x);
+                        i, ext4_free_group_clusters(sb, gdp), x);
                bitmap_count += x;
        }
        brelse(bitmap_bh);
-        printk(KERN_DEBUG "ext4_count_free_blocks: stored = %llu"
+        printk(KERN_DEBUG "ext4_count_free_clusters: stored = %llu"
-                ", computed = %llu, %llu\n", ext4_free_blocks_count(es),
+               ", computed = %llu, %llu\n",
+               EXT4_B2C(sbi, ext4_free_blocks_count(es)),
               desc_count, bitmap_count);
        return bitmap_count;
 #else
@@ -530,7 +574,7 @@ ext4_fsblk_t ext4_count_free_blocks(struct super_block *sb)
                gdp = ext4_get_group_desc(sb, i, NULL);
                if (!gdp)
                        continue;
-                desc_count += ext4_free_blks_count(sb, gdp);
+                desc_count += ext4_free_group_clusters(sb, gdp);
        }
        return desc_count;
@@ -620,6 +664,31 @@ unsigned long ext4_bg_num_gdb(struct super_block *sb, ext4_group_t group)
 }
+/*
+ * This function returns the number of file system metadata clusters at
+ * the beginning of a block group, including the reserved gdt blocks.
+ */
+unsigned ext4_num_base_meta_clusters(struct super_block *sb,
+                                     ext4_group_t block_group)
+{
+        struct ext4_sb_info *sbi = EXT4_SB(sb);
+        unsigned num;
+        /* Check for superblock and gdt backups in this group */
+        num = ext4_bg_has_super(sb, block_group);
+        if (!EXT4_HAS_INCOMPAT_FEATURE(sb, EXT4_FEATURE_INCOMPAT_META_BG) ||
+            block_group < le32_to_cpu(sbi->s_es->s_first_meta_bg) *
+                          sbi->s_desc_per_block) {
+                if (num) {
+                        num += ext4_bg_num_gdb(sb, block_group);
+                        num += le16_to_cpu(sbi->s_es->s_reserved_gdt_blocks);
+                }
+        } else { /* For META_BG_BLOCK_GROUPS */
+                num += ext4_bg_num_gdb(sb, block_group);
+        }
+        return EXT4_NUM_B2C(sbi, num);
+}
 /**
 *      ext4_inode_to_goal_block - return a hint for block allocation
 *      @inode: inode for block allocation
diff --git a/fs/ext4/ext4.h b/fs/ext4/ext4.h
index cec3145e532c..5b0e26a1272d 100644
--- a/fs/ext4/ext4.h
+++ b/fs/ext4/ext4.h
@@ -144,9 +144,17 @@ struct ext4_allocation_request {
 #define EXT4_MAP_UNWRITTEN      (1 << BH_Unwritten)
 #define EXT4_MAP_BOUNDARY       (1 << BH_Boundary)
 #define EXT4_MAP_UNINIT         (1 << BH_Uninit)
+/* Sometimes (in the bigalloc case, from ext4_da_get_block_prep) the caller of
+ * ext4_map_blocks wants to know whether or not the underlying cluster has
+ * already been accounted for. EXT4_MAP_FROM_CLUSTER conveys to the caller that
+ * the requested mapping was from previously mapped (or delayed allocated)
+ * cluster. We use BH_AllocFromCluster only for this flag. BH_AllocFromCluster
+ * should never appear on buffer_head's state flags.
+ */
+#define EXT4_MAP_FROM_CLUSTER   (1 << BH_AllocFromCluster)
 #define EXT4_MAP_FLAGS          (EXT4_MAP_NEW | EXT4_MAP_MAPPED |\
                                 EXT4_MAP_UNWRITTEN | EXT4_MAP_BOUNDARY |\
-                                 EXT4_MAP_UNINIT)
+                                 EXT4_MAP_UNINIT | EXT4_MAP_FROM_CLUSTER)
 struct ext4_map_blocks {
        ext4_fsblk_t m_pblk;
@@ -239,8 +247,11 @@ struct ext4_io_submit {
 # define EXT4_BLOCK_SIZE(s)             (EXT4_MIN_BLOCK_SIZE << (s)->s_log_block_size)
 #endif
 #define EXT4_ADDR_PER_BLOCK(s)          (EXT4_BLOCK_SIZE(s) / sizeof(__u32))
+#define EXT4_CLUSTER_SIZE(s)            (EXT4_BLOCK_SIZE(s) << \
+                                         EXT4_SB(s)->s_cluster_bits)
 #ifdef __KERNEL__
 # define EXT4_BLOCK_SIZE_BITS(s)        ((s)->s_blocksize_bits)
+# define EXT4_CLUSTER_BITS(s)           (EXT4_SB(s)->s_cluster_bits)
 #else
 # define EXT4_BLOCK_SIZE_BITS(s)        ((s)->s_log_block_size + 10)
 #endif
@@ -258,6 +269,14 @@ struct ext4_io_submit {
 #endif
 #define EXT4_BLOCK_ALIGN(size, blkbits)         ALIGN((size), (1 << (blkbits)))
+/* Translate a block number to a cluster number */
+#define EXT4_B2C(sbi, blk)      ((blk) >> (sbi)->s_cluster_bits)
+/* Translate a cluster number to a block number */
+#define EXT4_C2B(sbi, cluster)  ((cluster) << (sbi)->s_cluster_bits)
+/* Translate # of blks to # of clusters */
+#define EXT4_NUM_B2C(sbi, blks) (((blks) + (sbi)->s_cluster_ratio - 1) >> \
+                                 (sbi)->s_cluster_bits)
 /*
 * Structure of a blocks group descriptor
 */
@@ -289,7 +308,7 @@ struct ext4_group_desc
 struct flex_groups {
        atomic_t free_inodes;
-        atomic_t free_blocks;
+        atomic_t free_clusters;
        atomic_t used_dirs;
 };
@@ -306,6 +325,7 @@ struct flex_groups {
 #define EXT4_DESC_SIZE(s)               (EXT4_SB(s)->s_desc_size)
 #ifdef __KERNEL__
 # define EXT4_BLOCKS_PER_GROUP(s)       (EXT4_SB(s)->s_blocks_per_group)
+# define EXT4_CLUSTERS_PER_GROUP(s)     (EXT4_SB(s)->s_clusters_per_group)
 # define EXT4_DESC_PER_BLOCK(s)         (EXT4_SB(s)->s_desc_per_block)
 # define EXT4_INODES_PER_GROUP(s)       (EXT4_SB(s)->s_inodes_per_group)
 # define EXT4_DESC_PER_BLOCK_BITS(s)    (EXT4_SB(s)->s_desc_per_block_bits)
@@ -358,8 +378,7 @@ struct flex_groups {
 /* Flags that should be inherited by new inodes from their parent. */
 #define EXT4_FL_INHERITED (EXT4_SECRM_FL | EXT4_UNRM_FL | EXT4_COMPR_FL |\
-                           EXT4_SYNC_FL | EXT4_IMMUTABLE_FL | EXT4_APPEND_FL |\
+                           EXT4_SYNC_FL | EXT4_NODUMP_FL | EXT4_NOATIME_FL |\
-                           EXT4_NODUMP_FL | EXT4_NOATIME_FL |\
                           EXT4_NOCOMPR_FL | EXT4_JOURNAL_DATA_FL |\
                           EXT4_NOTAIL_FL | EXT4_DIRSYNC_FL)
@@ -520,6 +539,8 @@ struct ext4_new_group_data {
 #define EXT4_GET_BLOCKS_PUNCH_OUT_EXT           0x0020
        /* Don't normalize allocation size (used for fallocate) */
 #define EXT4_GET_BLOCKS_NO_NORMALIZE            0x0040
+        /* Request will not result in inode size update (user for fallocate) */
+#define EXT4_GET_BLOCKS_KEEP_SIZE               0x0080
 /*
 * Flags used by ext4_free_blocks
@@ -528,6 +549,13 @@ struct ext4_new_group_data {
 #define EXT4_FREE_BLOCKS_FORGET         0x0002
 #define EXT4_FREE_BLOCKS_VALIDATED      0x0004
 #define EXT4_FREE_BLOCKS_NO_QUOT_UPDATE 0x0008
+#define EXT4_FREE_BLOCKS_NOFREE_FIRST_CLUSTER   0x0010
+#define EXT4_FREE_BLOCKS_NOFREE_LAST_CLUSTER    0x0020
+/*
+ * Flags used by ext4_discard_partial_page_buffers
+ */
+#define EXT4_DISCARD_PARTIAL_PG_ZERO_UNMAPPED   0x0001
 /*
 * ioctl commands
@@ -538,9 +566,6 @@ struct ext4_new_group_data {
 #define EXT4_IOC_SETVERSION             _IOW('f', 4, long)
 #define EXT4_IOC_GETVERSION_OLD         FS_IOC_GETVERSION
 #define EXT4_IOC_SETVERSION_OLD         FS_IOC_SETVERSION
-#ifdef CONFIG_JBD2_DEBUG
-#define EXT4_IOC_WAIT_FOR_READONLY      _IOR('f', 99, long)
-#endif
 #define EXT4_IOC_GETRSVSZ               _IOR('f', 5, long)
 #define EXT4_IOC_SETRSVSZ               _IOW('f', 6, long)
 #define EXT4_IOC_GROUP_EXTEND           _IOW('f', 7, unsigned long)
@@ -563,9 +588,6 @@ struct ext4_new_group_data {
 #define EXT4_IOC32_SETRSVSZ             _IOW('f', 6, int)
 #define EXT4_IOC32_GROUP_EXTEND         _IOW('f', 7, unsigned int)
 #define EXT4_IOC32_GROUP_ADD            _IOW('f', 8, struct compat_ext4_new_group_input)
-#ifdef CONFIG_JBD2_DEBUG
-#define EXT4_IOC32_WAIT_FOR_READONLY    _IOR('f', 99, int)
-#endif
 #define EXT4_IOC32_GETVERSION_OLD       FS_IOC32_GETVERSION
 #define EXT4_IOC32_SETVERSION_OLD       FS_IOC32_SETVERSION
 #endif
@@ -837,6 +859,7 @@ struct ext4_inode_info {
        ext4_group_t    i_last_alloc_group;
        /* allocation reservation info for delalloc */
+        /* In case of bigalloc, these refer to clusters rather than blocks */
        unsigned int i_reserved_data_blocks;
        unsigned int i_reserved_meta_blocks;
        unsigned int i_allocated_meta_blocks;
@@ -886,7 +909,6 @@ struct ext4_inode_info {
 /*
 * Mount flags
 */
-#define EXT4_MOUNT_OLDALLOC             0x00002  /* Don't use the new Orlov allocator */
 #define EXT4_MOUNT_GRPID                0x00004 /* Create files with directory's group */
 #define EXT4_MOUNT_DEBUG                0x00008 /* Some debugging messages */
 #define EXT4_MOUNT_ERRORS_CONT          0x00010 /* Continue on errors */
@@ -918,6 +940,9 @@ struct ext4_inode_info {
 #define EXT4_MOUNT_DISCARD              0x40000000 /* Issue DISCARD requests */
 #define EXT4_MOUNT_INIT_INODE_TABLE     0x80000000 /* Initialize uninitialized itables */
+#define EXT4_MOUNT2_EXPLICIT_DELALLOC   0x00000001 /* User explicitly
+                                                      specified delalloc */
 #define clear_opt(sb, opt)              EXT4_SB(sb)->s_mount_opt &= \
                                                ~EXT4_MOUNT_##opt
 #define set_opt(sb, opt)                EXT4_SB(sb)->s_mount_opt |= \
@@ -968,9 +993,9 @@ struct ext4_super_block {
 /*10*/  __le32  s_free_inodes_count;    /* Free inodes count */
        __le32  s_first_data_block;     /* First Data Block */
        __le32  s_log_block_size;       /* Block size */
-        __le32  s_obso_log_frag_size;   /* Obsoleted fragment size */
+        __le32  s_log_cluster_size;     /* Allocation cluster size */
 /*20*/  __le32  s_blocks_per_group;     /* # Blocks per group */
-        __le32  s_obso_frags_per_group; /* Obsoleted fragments per group */
+        __le32  s_clusters_per_group;   /* # Clusters per group */
        __le32  s_inodes_per_group;     /* # Inodes per group */
        __le32  s_mtime;                /* Mount time */
 /*30*/  __le32  s_wtime;                /* Write time */
@@ -1066,7 +1091,10 @@ struct ext4_super_block {
        __u8    s_last_error_func[32];  /* function where the error happened */
 #define EXT4_S_ERR_END offsetof(struct ext4_super_block, s_mount_opts)
        __u8    s_mount_opts[64];
-        __le32  s_reserved[112];        /* Padding to the end of the block */
+        __le32  s_usr_quota_inum;       /* inode for tracking user quota */
+        __le32  s_grp_quota_inum;       /* inode for tracking group quota */
+        __le32  s_overhead_clusters;    /* overhead blocks/clusters in fs */
+        __le32  s_reserved[109];        /* Padding to the end of the block */
 };
 #define EXT4_S_ERR_LEN (EXT4_S_ERR_END - EXT4_S_ERR_START)
@@ -1086,6 +1114,7 @@ struct ext4_sb_info {
        unsigned long s_desc_size;      /* Size of a group descriptor in bytes */
        unsigned long s_inodes_per_block;/* Number of inodes per block */
        unsigned long s_blocks_per_group;/* Number of blocks in a group */
+        unsigned long s_clusters_per_group; /* Number of clusters in a group */
        unsigned long s_inodes_per_group;/* Number of inodes in a group */
        unsigned long s_itb_per_group;  /* Number of inode table blocks per group */
        unsigned long s_gdb_count;      /* Number of group descriptor blocks */
@@ -1094,6 +1123,8 @@ struct ext4_sb_info {
        ext4_group_t s_blockfile_groups;/* Groups acceptable for non-extent files */
        unsigned long s_overhead_last;  /* Last calculated overhead */
        unsigned long s_blocks_last;    /* Last seen block count */
+        unsigned int s_cluster_ratio;   /* Number of blocks per cluster */
+        unsigned int s_cluster_bits;    /* log2 of s_cluster_ratio */
        loff_t s_bitmap_maxbytes;       /* max bytes for bitmap files */
        struct buffer_head * s_sbh;     /* Buffer containing the super block */
        struct ext4_super_block *s_es;  /* Pointer to the super block in the buffer */
@@ -1117,10 +1148,10 @@ struct ext4_sb_info {
        u32 s_hash_seed[4];
        int s_def_hash_version;
        int s_hash_unsigned;    /* 3 if hash should be signed, 0 if not */
-        struct percpu_counter s_freeblocks_counter;
+        struct percpu_counter s_freeclusters_counter;
        struct percpu_counter s_freeinodes_counter;
        struct percpu_counter s_dirs_counter;
-        struct percpu_counter s_dirtyblocks_counter;
+        struct percpu_counter s_dirtyclusters_counter;
        struct blockgroup_lock *s_blockgroup_lock;
        struct proc_dir_entry *s_proc;
        struct kobject s_kobj;
@@ -1136,10 +1167,6 @@ struct ext4_sb_info {
        u32 s_max_batch_time;
        u32 s_min_batch_time;
        struct block_device *journal_bdev;
-#ifdef CONFIG_JBD2_DEBUG
-        struct timer_list turn_ro_timer;        /* For turning read-only (crash simulation) */
-        wait_queue_head_t ro_wait_queue;        /* For people waiting for the fs to go read-only */
-#endif
 #ifdef CONFIG_QUOTA
        char *s_qf_names[MAXQUOTAS];            /* Names of quota files with journalled quota */
        int s_jquota_fmt;                       /* Format of quota to use */
@@ -1248,6 +1275,15 @@ static inline int ext4_valid_inum(struct super_block *sb, unsigned long ino)
                 ino <= le32_to_cpu(EXT4_SB(sb)->s_es->s_inodes_count));
 }
+static inline void ext4_set_io_unwritten_flag(struct inode *inode,
+                                              struct ext4_io_end *io_end)
+{
+        if (!(io_end->flag & EXT4_IO_END_UNWRITTEN)) {
+                io_end->flag |= EXT4_IO_END_UNWRITTEN;
+                atomic_inc(&EXT4_I(inode)->i_aiodio_unwritten);
+        }
+}
 /*
 * Inode dynamic state flags
 */
@@ -1360,6 +1396,7 @@ static inline void ext4_clear_state_flags(struct ext4_inode_info *ei)
 #define EXT4_FEATURE_RO_COMPAT_DIR_NLINK        0x0020
 #define EXT4_FEATURE_RO_COMPAT_EXTRA_ISIZE      0x0040
 #define EXT4_FEATURE_RO_COMPAT_QUOTA            0x0100
+#define EXT4_FEATURE_RO_COMPAT_BIGALLOC         0x0200
 #define EXT4_FEATURE_INCOMPAT_COMPRESSION       0x0001
 #define EXT4_FEATURE_INCOMPAT_FILETYPE          0x0002
@@ -1402,7 +1439,8 @@ static inline void ext4_clear_state_flags(struct ext4_inode_info *ei)
                                         EXT4_FEATURE_RO_COMPAT_DIR_NLINK | \
                                         EXT4_FEATURE_RO_COMPAT_EXTRA_ISIZE | \
                                         EXT4_FEATURE_RO_COMPAT_BTREE_DIR |\
-                                         EXT4_FEATURE_RO_COMPAT_HUGE_FILE)
+                                         EXT4_FEATURE_RO_COMPAT_HUGE_FILE |\
+                                         EXT4_FEATURE_RO_COMPAT_BIGALLOC)
 /*
 * Default values for user and/or group using reserved blocks
@@ -1735,9 +1773,9 @@ extern ext4_fsblk_t ext4_new_meta_blocks(handle_t *handle, struct inode *inode,
                                         unsigned int flags,
                                         unsigned long *count,
                                         int *errp);
-extern int ext4_claim_free_blocks(struct ext4_sb_info *sbi,
+extern int ext4_claim_free_clusters(struct ext4_sb_info *sbi,
-                                  s64 nblocks, unsigned int flags);
+                                    s64 nclusters, unsigned int flags);
-extern ext4_fsblk_t ext4_count_free_blocks(struct super_block *);
+extern ext4_fsblk_t ext4_count_free_clusters(struct super_block *);
 extern void ext4_check_blocks_bitmap(struct super_block *);
 extern struct ext4_group_desc * ext4_get_group_desc(struct super_block * sb,
                                                    ext4_group_t block_group,
@@ -1745,12 +1783,18 @@ extern struct ext4_group_desc * ext4_get_group_desc(struct super_block * sb,
 extern int ext4_should_retry_alloc(struct super_block *sb, int *retries);
 struct buffer_head *ext4_read_block_bitmap(struct super_block *sb,
                                      ext4_group_t block_group);
-extern unsigned ext4_init_block_bitmap(struct super_block *sb,
+extern void ext4_init_block_bitmap(struct super_block *sb,
-                                       struct buffer_head *bh,
+                                   struct buffer_head *bh,
-                                       ext4_group_t group,
+                                   ext4_group_t group,
-                                       struct ext4_group_desc *desc);
+                                   struct ext4_group_desc *desc);
-#define ext4_free_blocks_after_init(sb, group, desc)                    \
+extern unsigned ext4_free_clusters_after_init(struct super_block *sb,
-                ext4_init_block_bitmap(sb, NULL, group, desc)
+                                              ext4_group_t block_group,
+                                              struct ext4_group_desc *gdp);
+extern unsigned ext4_num_base_meta_clusters(struct super_block *sb,
+                                            ext4_group_t block_group);
+extern unsigned ext4_num_overhead_clusters(struct super_block *sb,
+                                           ext4_group_t block_group,
+                                           struct ext4_group_desc *gdp);
 ext4_fsblk_t ext4_inode_to_goal_block(struct inode *);
 /* dir.c */
@@ -1776,7 +1820,8 @@ extern int ext4fs_dirhash(const char *name, int len, struct
 /* ialloc.c */
 extern struct inode *ext4_new_inode(handle_t *, struct inode *, int,
-                                    const struct qstr *qstr, __u32 goal);
+                                    const struct qstr *qstr, __u32 goal,
+                                    uid_t *owner);
 extern void ext4_free_inode(handle_t *, struct inode *);
 extern struct inode * ext4_orphan_get(struct super_block *, unsigned long);
 extern unsigned long ext4_count_free_inodes(struct super_block *);
@@ -1839,6 +1884,12 @@ extern int ext4_block_truncate_page(handle_t *handle,
                struct address_space *mapping, loff_t from);
 extern int ext4_block_zero_page_range(handle_t *handle,
                struct address_space *mapping, loff_t from, loff_t length);
+extern int ext4_discard_partial_page_buffers(handle_t *handle,
+                struct address_space *mapping, loff_t from,
+                loff_t length, int flags);
+extern int ext4_discard_partial_page_buffers_no_lock(handle_t *handle,
+                struct inode *inode, struct page *page, loff_t from,
+                loff_t length, int flags);
 extern int ext4_page_mkwrite(struct vm_area_struct *vma, struct vm_fault *vmf);
 extern qsize_t *ext4_get_reserved_space(struct inode *inode);
 extern void ext4_da_update_reserve_space(struct inode *inode,
@@ -1927,8 +1978,8 @@ extern ext4_fsblk_t ext4_inode_bitmap(struct super_block *sb,
                                      struct ext4_group_desc *bg);
 extern ext4_fsblk_t ext4_inode_table(struct super_block *sb,
                                     struct ext4_group_desc *bg);
-extern __u32 ext4_free_blks_count(struct super_block *sb,
+extern __u32 ext4_free_group_clusters(struct super_block *sb,
-                                struct ext4_group_desc *bg);
+                                      struct ext4_group_desc *bg);
 extern __u32 ext4_free_inodes_count(struct super_block *sb,
                                 struct ext4_group_desc *bg);
 extern __u32 ext4_used_dirs_count(struct super_block *sb,
@@ -1941,8 +1992,9 @@ extern void ext4_inode_bitmap_set(struct super_block *sb,
                                  struct ext4_group_desc *bg, ext4_fsblk_t blk);
 extern void ext4_inode_table_set(struct super_block *sb,
                                 struct ext4_group_desc *bg, ext4_fsblk_t blk);
-extern void ext4_free_blks_set(struct super_block *sb,
+extern void ext4_free_group_clusters_set(struct super_block *sb,
-                               struct ext4_group_desc *bg, __u32 count);
+                                         struct ext4_group_desc *bg,
+                                         __u32 count);
 extern void ext4_free_inodes_set(struct super_block *sb,
                                struct ext4_group_desc *bg, __u32 count);
 extern void ext4_used_dirs_set(struct super_block *sb,
@@ -2051,13 +2103,13 @@ do {								\
 } while (0)
 #ifdef CONFIG_SMP
-/* Each CPU can accumulate percpu_counter_batch blocks in their local
+/* Each CPU can accumulate percpu_counter_batch clusters in their local
- * counters. So we need to make sure we have free blocks more
+ * counters. So we need to make sure we have free clusters more
 * than percpu_counter_batch  * nr_cpu_ids. Also add a window of 4 times.
 */
-#define EXT4_FREEBLOCKS_WATERMARK (4 * (percpu_counter_batch * nr_cpu_ids))
+#define EXT4_FREECLUSTERS_WATERMARK (4 * (percpu_counter_batch * nr_cpu_ids))
 #else
-#define EXT4_FREEBLOCKS_WATERMARK 0
+#define EXT4_FREECLUSTERS_WATERMARK 0
 #endif
 static inline void ext4_update_i_disksize(struct inode *inode, loff_t newsize)
@@ -2243,10 +2295,19 @@ extern int ext4_multi_mount_protect(struct super_block *, ext4_fsblk_t);
 enum ext4_state_bits {
        BH_Uninit       /* blocks are allocated but uninitialized on disk */
          = BH_JBDPrivateStart,
+        BH_AllocFromCluster,    /* allocated blocks were part of already
+                                 * allocated cluster. Note that this flag will
+                                 * never, ever appear in a buffer_head's state
+                                 * flag. See EXT4_MAP_FROM_CLUSTER to see where
+                                 * this is used. */
+        BH_Da_Mapped,   /* Delayed allocated block that now has a mapping. This
+                         * flag is set when ext4_map_blocks is called on a
+                         * delayed allocated block to get its real mapping. */
 };
 BUFFER_FNS(Uninit, uninit)
 TAS_BUFFER_FNS(Uninit, uninit)
+BUFFER_FNS(Da_Mapped, da_mapped)
 /*
 * Add new method to test wether block and inode bitmaps are properly
@@ -2282,4 +2343,6 @@ extern void ext4_resize_end(struct super_block *sb);
 #endif  /* __KERNEL__ */
+#include "ext4_extents.h"
 #endif  /* _EXT4_H */
diff --git a/fs/ext4/ext4_extents.h b/fs/ext4/ext4_extents.h
index 095c36f3b612..a52db3a69a30 100644
--- a/fs/ext4/ext4_extents.h
+++ b/fs/ext4/ext4_extents.h
@@ -290,5 +290,7 @@ extern struct ext4_ext_path *ext4_ext_find_extent(struct inode *, ext4_lblk_t,
                                                        struct ext4_ext_path *);
 extern void ext4_ext_drop_refs(struct ext4_ext_path *);
 extern int ext4_ext_check_inode(struct inode *inode);
+extern int ext4_find_delalloc_cluster(struct inode *inode, ext4_lblk_t lblk,
+                                      int search_hint_reverse);
 #endif /* _EXT4_EXTENTS */
diff --git a/fs/ext4/ext4_jbd2.c b/fs/ext4/ext4_jbd2.c
index f5240aa15601..aca179017582 100644
--- a/fs/ext4/ext4_jbd2.c
+++ b/fs/ext4/ext4_jbd2.c
@@ -109,9 +109,11 @@ int __ext4_handle_dirty_metadata(const char *where, unsigned int line,
        if (ext4_handle_valid(handle)) {
                err = jbd2_journal_dirty_metadata(handle, bh);
-                if (err)
+                if (err) {
-                        ext4_journal_abort_handle(where, line, __func__,
+                        /* Errors can only happen if there is a bug */
-                                                  bh, handle, err);
+                        handle->h_err = err;
+                        __ext4_journal_stop(where, line, handle);
+                }
        } else {
                if (inode)
                        mark_buffer_dirty_inode(bh, inode);
diff --git a/fs/ext4/extents.c b/fs/ext4/extents.c
index 57cf568a98ab..61fa9e1614af 100644
--- a/fs/ext4/extents.c
+++ b/fs/ext4/extents.c
@@ -42,7 +42,6 @@
 #include <asm/uaccess.h>
 #include <linux/fiemap.h>
 #include "ext4_jbd2.h"
-#include "ext4_extents.h"
 #include <trace/events/ext4.h>
@@ -96,13 +95,17 @@ static int ext4_ext_get_access(handle_t *handle, struct inode *inode,
 *  - ENOMEM
 *  - EIO
 */
-static int ext4_ext_dirty(handle_t *handle, struct inode *inode,
+#define ext4_ext_dirty(handle, inode, path) \
-                                struct ext4_ext_path *path)
+                __ext4_ext_dirty(__func__, __LINE__, (handle), (inode), (path))
+static int __ext4_ext_dirty(const char *where, unsigned int line,
+                            handle_t *handle, struct inode *inode,
+                            struct ext4_ext_path *path)
 {
        int err;
        if (path->p_bh) {
                /* path points to block */
-                err = ext4_handle_dirty_metadata(handle, inode, path->p_bh);
+                err = __ext4_handle_dirty_metadata(where, line, handle,
+                                                   inode, path->p_bh);
        } else {
                /* path points to leaf/index in inode body */
                err = ext4_mark_inode_dirty(handle, inode);
@@ -114,11 +117,9 @@ static ext4_fsblk_t ext4_ext_find_goal(struct inode *inode,
                              struct ext4_ext_path *path,
                              ext4_lblk_t block)
 {
-        int depth;
        if (path) {
+                int depth = path->p_depth;
                struct ext4_extent *ex;
-                depth = path->p_depth;
                /*
                 * Try to predict block placement assuming that we are
@@ -180,12 +181,10 @@ static inline int ext4_ext_space_block(struct inode *inode, int check)
        size = (inode->i_sb->s_blocksize - sizeof(struct ext4_extent_header))
                        / sizeof(struct ext4_extent);
-        if (!check) {
 #ifdef AGGRESSIVE_TEST
-                if (size > 6)
+        if (!check && size > 6)
-                        size = 6;
+                size = 6;
 #endif
-        }
        return size;
 }
@@ -195,12 +194,10 @@ static inline int ext4_ext_space_block_idx(struct inode *inode, int check)
        size = (inode->i_sb->s_blocksize - sizeof(struct ext4_extent_header))
                        / sizeof(struct ext4_extent_idx);
-        if (!check) {
 #ifdef AGGRESSIVE_TEST
-                if (size > 5)
+        if (!check && size > 5)
-                        size = 5;
+                size = 5;
 #endif
-        }
        return size;
 }
@@ -211,12 +208,10 @@ static inline int ext4_ext_space_root(struct inode *inode, int check)
        size = sizeof(EXT4_I(inode)->i_data);
        size -= sizeof(struct ext4_extent_header);
        size /= sizeof(struct ext4_extent);
-        if (!check) {
 #ifdef AGGRESSIVE_TEST
-                if (size > 3)
+        if (!check && size > 3)
-                        size = 3;
+                size = 3;
 #endif
-        }
        return size;
 }
@@ -227,12 +222,10 @@ static inline int ext4_ext_space_root_idx(struct inode *inode, int check)
        size = sizeof(EXT4_I(inode)->i_data);
        size -= sizeof(struct ext4_extent_header);
        size /= sizeof(struct ext4_extent_idx);
-        if (!check) {
 #ifdef AGGRESSIVE_TEST
-                if (size > 4)
+        if (!check && size > 4)
-                        size = 4;
+                size = 4;
 #endif
-        }
        return size;
 }
@@ -244,7 +237,7 @@ static inline int ext4_ext_space_root_idx(struct inode *inode, int check)
 int ext4_ext_calc_metadata_amount(struct inode *inode, ext4_lblk_t lblock)
 {
        struct ext4_inode_info *ei = EXT4_I(inode);
-        int idxs, num = 0;
+        int idxs;
        idxs = ((inode->i_sb->s_blocksize - sizeof(struct ext4_extent_header))
                / sizeof(struct ext4_extent_idx));
@@ -259,6 +252,8 @@ int ext4_ext_calc_metadata_amount(struct inode *inode, ext4_lblk_t lblock)
         */
        if (ei->i_da_metadata_calc_len &&
            ei->i_da_metadata_calc_last_lblock+1 == lblock) {
+                int num = 0;
                if ((ei->i_da_metadata_calc_len % idxs) == 0)
                        num++;
                if ((ei->i_da_metadata_calc_len % (idxs*idxs)) == 0)
@@ -321,8 +316,6 @@ static int ext4_valid_extent_entries(struct inode *inode,
                                struct ext4_extent_header *eh,
                                int depth)
 {
-        struct ext4_extent *ext;
-        struct ext4_extent_idx *ext_idx;
        unsigned short entries;
        if (eh->eh_entries == 0)
                return 1;
@@ -331,7 +324,7 @@ static int ext4_valid_extent_entries(struct inode *inode,
        if (depth == 0) {
                /* leaf entries */
-                ext = EXT_FIRST_EXTENT(eh);
+                struct ext4_extent *ext = EXT_FIRST_EXTENT(eh);
                while (entries) {
                        if (!ext4_valid_extent(inode, ext))
                                return 0;
@@ -339,7 +332,7 @@ static int ext4_valid_extent_entries(struct inode *inode,
                        entries--;
                }
        } else {
-                ext_idx = EXT_FIRST_INDEX(eh);
+                struct ext4_extent_idx *ext_idx = EXT_FIRST_INDEX(eh);
                while (entries) {
                        if (!ext4_valid_extent_idx(inode, ext_idx))
                                return 0;
@@ -751,31 +744,30 @@ static int ext4_ext_insert_index(handle_t *handle, struct inode *inode,
                return -EIO;
        }
-        len = EXT_MAX_INDEX(curp->p_hdr) - curp->p_idx;
        if (logical > le32_to_cpu(curp->p_idx->ei_block)) {
                /* insert after */
-                if (curp->p_idx != EXT_LAST_INDEX(curp->p_hdr)) {
+                ext_debug("insert new index %d after: %llu\n", logical, ptr);
-                        len = (len - 1) * sizeof(struct ext4_extent_idx);
-                        len = len < 0 ? 0 : len;
-                        ext_debug("insert new index %d after: %llu. "
-                                        "move %d from 0x%p to 0x%p\n",
-                                        logical, ptr, len,
-                                        (curp->p_idx + 1), (curp->p_idx + 2));
-                        memmove(curp->p_idx + 2, curp->p_idx + 1, len);
-                }
                ix = curp->p_idx + 1;
        } else {
                /* insert before */
-                len = len * sizeof(struct ext4_extent_idx);
+                ext_debug("insert new index %d before: %llu\n", logical, ptr);
-                len = len < 0 ? 0 : len;
-                ext_debug("insert new index %d before: %llu. "
-                                "move %d from 0x%p to 0x%p\n",
-                                logical, ptr, len,
-                                curp->p_idx, (curp->p_idx + 1));
-                memmove(curp->p_idx + 1, curp->p_idx, len);
                ix = curp->p_idx;
        }
+        len = EXT_LAST_INDEX(curp->p_hdr) - ix + 1;
+        BUG_ON(len < 0);
+        if (len > 0) {
+                ext_debug("insert new index %d: "
+                                "move %d indices from 0x%p to 0x%p\n",
+                                logical, len, ix, ix + 1);
+                memmove(ix + 1, ix, len * sizeof(struct ext4_extent_idx));
+        }
+        if (unlikely(ix > EXT_MAX_INDEX(curp->p_hdr))) {
+                EXT4_ERROR_INODE(inode, "ix > EXT_MAX_INDEX!");
+                return -EIO;
+        }
        ix->ei_block = cpu_to_le32(logical);
        ext4_idx_store_pblock(ix, ptr);
        le16_add_cpu(&curp->p_hdr->eh_entries, 1);
@@ -1042,16 +1034,14 @@ cleanup:
 */
 static int ext4_ext_grow_indepth(handle_t *handle, struct inode *inode,
                                 unsigned int flags,
-                                 struct ext4_ext_path *path,
                                 struct ext4_extent *newext)
 {
-        struct ext4_ext_path *curp = path;
        struct ext4_extent_header *neh;
        struct buffer_head *bh;
        ext4_fsblk_t newblock;
        int err = 0;
-        newblock = ext4_ext_new_meta_block(handle, inode, path,
+        newblock = ext4_ext_new_meta_block(handle, inode, NULL,
                newext, &err, flags);
        if (newblock == 0)
                return err;
@@ -1071,7 +1061,8 @@ static int ext4_ext_grow_indepth(handle_t *handle, struct inode *inode,
        }
        /* move top-level index/leaf into new block */
-        memmove(bh->b_data, curp->p_hdr, sizeof(EXT4_I(inode)->i_data));
+        memmove(bh->b_data, EXT4_I(inode)->i_data,
+                sizeof(EXT4_I(inode)->i_data));
        /* set size of new block */
        neh = ext_block_hdr(bh);
@@ -1089,32 +1080,23 @@ static int ext4_ext_grow_indepth(handle_t *handle, struct inode *inode,
        if (err)
                goto out;
-        /* create index in new top-level index: num,max,pointer */
+        /* Update top-level index: num,max,pointer */
-        err = ext4_ext_get_access(handle, inode, curp);
-        if (err)
-                goto out;
-        curp->p_hdr->eh_magic = EXT4_EXT_MAGIC;
-        curp->p_hdr->eh_max = cpu_to_le16(ext4_ext_space_root_idx(inode, 0));
-        curp->p_hdr->eh_entries = cpu_to_le16(1);
-        curp->p_idx = EXT_FIRST_INDEX(curp->p_hdr);
-        if (path[0].p_hdr->eh_depth)
-                curp->p_idx->ei_block =
-                        EXT_FIRST_INDEX(path[0].p_hdr)->ei_block;
-        else
-                curp->p_idx->ei_block =
-                        EXT_FIRST_EXTENT(path[0].p_hdr)->ee_block;
-        ext4_idx_store_pblock(curp->p_idx, newblock);
        neh = ext_inode_hdr(inode);
+        neh->eh_entries = cpu_to_le16(1);
+        ext4_idx_store_pblock(EXT_FIRST_INDEX(neh), newblock);
+        if (neh->eh_depth == 0) {
+                /* Root extent block becomes index block */
+                neh->eh_max = cpu_to_le16(ext4_ext_space_root_idx(inode, 0));
+                EXT_FIRST_INDEX(neh)->ei_block =
+                        EXT_FIRST_EXTENT(neh)->ee_block;
+        }
        ext_debug("new root: num %d(%d), lblock %d, ptr %llu\n",
                  le16_to_cpu(neh->eh_entries), le16_to_cpu(neh->eh_max),
                  le32_to_cpu(EXT_FIRST_INDEX(neh)->ei_block),
                  ext4_idx_pblock(EXT_FIRST_INDEX(neh)));
-        neh->eh_depth = cpu_to_le16(path->p_depth + 1);
+        neh->eh_depth = cpu_to_le16(neh->eh_depth + 1);
-        err = ext4_ext_dirty(handle, inode, curp);
+        ext4_mark_inode_dirty(handle, inode);
 out:
        brelse(bh);
@@ -1162,8 +1144,7 @@ repeat:
                        err = PTR_ERR(path);
        } else {
                /* tree is full, time to grow in depth */
-                err = ext4_ext_grow_indepth(handle, inode, flags,
+                err = ext4_ext_grow_indepth(handle, inode, flags, newext);
-                                            path, newext);
                if (err)
                        goto out;
@@ -1235,9 +1216,9 @@ static int ext4_ext_search_left(struct inode *inode,
                        if (unlikely(ix != EXT_FIRST_INDEX(path[depth].p_hdr))) {
                                EXT4_ERROR_INODE(inode,
                                  "ix (%d) != EXT_FIRST_INDEX (%d) (depth %d)!",
-                                  ix != NULL ? ix->ei_block : 0,
+                                  ix != NULL ? le32_to_cpu(ix->ei_block) : 0,
                                  EXT_FIRST_INDEX(path[depth].p_hdr) != NULL ?
-                                    EXT_FIRST_INDEX(path[depth].p_hdr)->ei_block : 0,
+                le32_to_cpu(EXT_FIRST_INDEX(path[depth].p_hdr)->ei_block) : 0,
                                  depth);
                                return -EIO;
                        }
@@ -1260,13 +1241,14 @@ static int ext4_ext_search_left(struct inode *inode,
 /*
 * search the closest allocated block to the right for *logical
 * and returns it at @logical + it's physical address at @phys
- * if *logical is the smallest allocated block, the function
+ * if *logical is the largest allocated block, the function
 * returns 0 at @phys
 * return value contains 0 (success) or error code
 */
 static int ext4_ext_search_right(struct inode *inode,
                                 struct ext4_ext_path *path,
-                                 ext4_lblk_t *logical, ext4_fsblk_t *phys)
+                                 ext4_lblk_t *logical, ext4_fsblk_t *phys,
+                                 struct ext4_extent **ret_ex)
 {
        struct buffer_head *bh = NULL;
        struct ext4_extent_header *eh;
@@ -1308,9 +1290,7 @@ static int ext4_ext_search_right(struct inode *inode,
                                return -EIO;
                        }
                }
-                *logical = le32_to_cpu(ex->ee_block);
+                goto found_extent;
-                *phys = ext4_ext_pblock(ex);
-                return 0;
        }
        if (unlikely(*logical < (le32_to_cpu(ex->ee_block) + ee_len))) {
@@ -1323,9 +1303,7 @@ static int ext4_ext_search_right(struct inode *inode,
        if (ex != EXT_LAST_EXTENT(path[depth].p_hdr)) {
                /* next allocated block in this leaf */
                ex++;
-                *logical = le32_to_cpu(ex->ee_block);
+                goto found_extent;
-                *phys = ext4_ext_pblock(ex);
-                return 0;
        }
        /* go up and search for index to the right */
@@ -1368,9 +1346,12 @@ got_index:
                return -EIO;
        }
        ex = EXT_FIRST_EXTENT(eh);
+found_extent:
        *logical = le32_to_cpu(ex->ee_block);
        *phys = ext4_ext_pblock(ex);
-        put_bh(bh);
+        *ret_ex = ex;
+        if (bh)
+                put_bh(bh);
        return 0;
 }
@@ -1395,7 +1376,8 @@ ext4_ext_next_allocated_block(struct ext4_ext_path *path)
        while (depth >= 0) {
                if (depth == path->p_depth) {
                        /* leaf */
-                        if (path[depth].p_ext !=
+                        if (path[depth].p_ext &&
+                                path[depth].p_ext !=
                                        EXT_LAST_EXTENT(path[depth].p_hdr))
                          return le32_to_cpu(path[depth].p_ext[1].ee_block);
                } else {
@@ -1623,7 +1605,8 @@ static int ext4_ext_try_to_merge(struct inode *inode,
 * such that there will be no overlap, and then returns 1.
 * If there is no overlap found, it returns 0.
 */
-static unsigned int ext4_ext_check_overlap(struct inode *inode,
+static unsigned int ext4_ext_check_overlap(struct ext4_sb_info *sbi,
+                                           struct inode *inode,
                                           struct ext4_extent *newext,
                                           struct ext4_ext_path *path)
 {
@@ -1637,6 +1620,7 @@ static unsigned int ext4_ext_check_overlap(struct inode *inode,
        if (!path[depth].p_ext)
                goto out;
        b2 = le32_to_cpu(path[depth].p_ext->ee_block);
+        b2 &= ~(sbi->s_cluster_ratio - 1);
        /*
         * get the next allocated block if the extent in the path
@@ -1646,6 +1630,7 @@ static unsigned int ext4_ext_check_overlap(struct inode *inode,
                b2 = ext4_ext_next_allocated_block(path);
                if (b2 == EXT_MAX_BLOCKS)
                        goto out;
+                b2 &= ~(sbi->s_cluster_ratio - 1);
        }
        /* check for wrap through zero on extent logical start block*/
@@ -1697,7 +1682,7 @@ int ext4_ext_insert_extent(handle_t *handle, struct inode *inode,
        /* try to insert block into found extent and return */
        if (ex && !(flag & EXT4_GET_BLOCKS_PRE_IO)
                && ext4_can_extents_be_merged(inode, ex, newext)) {
-                ext_debug("append [%d]%d block to %d:[%d]%d (from %llu)\n",
+                ext_debug("append [%d]%d block to %u:[%d]%d (from %llu)\n",
                          ext4_ext_is_uninitialized(newext),
                          ext4_ext_get_actual_len(newext),
                          le32_to_cpu(ex->ee_block),
@@ -1735,7 +1720,7 @@ int ext4_ext_insert_extent(handle_t *handle, struct inode *inode,
        if (le32_to_cpu(newext->ee_block) > le32_to_cpu(fex->ee_block))
                next = ext4_ext_next_leaf_block(path);
        if (next != EXT_MAX_BLOCKS) {
-                ext_debug("next leaf block - %d\n", next);
+                ext_debug("next leaf block - %u\n", next);
                BUG_ON(npath != NULL);
                npath = ext4_ext_find_extent(inode, next, NULL);
                if (IS_ERR(npath))
@@ -1773,46 +1758,51 @@ has_space:
        if (!nearex) {
                /* there is no extent in this leaf, create first one */
-                ext_debug("first extent in the leaf: %d:%llu:[%d]%d\n",
+                ext_debug("first extent in the leaf: %u:%llu:[%d]%d\n",
                                le32_to_cpu(newext->ee_block),
                                ext4_ext_pblock(newext),
                                ext4_ext_is_uninitialized(newext),
                                ext4_ext_get_actual_len(newext));
-                path[depth].p_ext = EXT_FIRST_EXTENT(eh);
+                nearex = EXT_FIRST_EXTENT(eh);
-        } else if (le32_to_cpu(newext->ee_block)
+        } else {
+                if (le32_to_cpu(newext->ee_block)
                           > le32_to_cpu(nearex->ee_block)) {
-/*              BUG_ON(newext->ee_block == nearex->ee_block); */
+                        /* Insert after */
-                if (nearex != EXT_LAST_EXTENT(eh)) {
+                        ext_debug("insert %u:%llu:[%d]%d before: "
-                        len = EXT_MAX_EXTENT(eh) - nearex;
+                                        "nearest %p\n",
-                        len = (len - 1) * sizeof(struct ext4_extent);
-                        len = len < 0 ? 0 : len;
-                        ext_debug("insert %d:%llu:[%d]%d after: nearest 0x%p, "
-                                        "move %d from 0x%p to 0x%p\n",
                                        le32_to_cpu(newext->ee_block),
                                        ext4_ext_pblock(newext),
                                        ext4_ext_is_uninitialized(newext),
                                        ext4_ext_get_actual_len(newext),
-                                        nearex, len, nearex + 1, nearex + 2);
+                                        nearex);
-                        memmove(nearex + 2, nearex + 1, len);
+                        nearex++;
+                } else {
+                        /* Insert before */
+                        BUG_ON(newext->ee_block == nearex->ee_block);
+                        ext_debug("insert %u:%llu:[%d]%d after: "
+                                        "nearest %p\n",
+                                        le32_to_cpu(newext->ee_block),
+                                        ext4_ext_pblock(newext),
+                                        ext4_ext_is_uninitialized(newext),
+                                        ext4_ext_get_actual_len(newext),
+                                        nearex);
+                }
+                len = EXT_LAST_EXTENT(eh) - nearex + 1;
+                if (len > 0) {
+                        ext_debug("insert %u:%llu:[%d]%d: "
+                                        "move %d extents from 0x%p to 0x%p\n",
+                                        le32_to_cpu(newext->ee_block),
+                                        ext4_ext_pblock(newext),
+                                        ext4_ext_is_uninitialized(newext),
+                                        ext4_ext_get_actual_len(newext),
+                                        len, nearex, nearex + 1);
+                        memmove(nearex + 1, nearex,
+                                len * sizeof(struct ext4_extent));
                }
-                path[depth].p_ext = nearex + 1;
-        } else {
-                BUG_ON(newext->ee_block == nearex->ee_block);
-                len = (EXT_MAX_EXTENT(eh) - nearex) * sizeof(struct ext4_extent);
-                len = len < 0 ? 0 : len;
-                ext_debug("insert %d:%llu:[%d]%d before: nearest 0x%p, "
-                                "move %d from 0x%p to 0x%p\n",
-                                le32_to_cpu(newext->ee_block),
-                                ext4_ext_pblock(newext),
-                                ext4_ext_is_uninitialized(newext),
-                                ext4_ext_get_actual_len(newext),
-                                nearex, len, nearex, nearex + 1);
-                memmove(nearex + 1, nearex, len);
-                path[depth].p_ext = nearex;
        }
        le16_add_cpu(&eh->eh_entries, 1);
-        nearex = path[depth].p_ext;
+        path[depth].p_ext = nearex;
        nearex->ee_block = newext->ee_block;
        ext4_ext_store_pblock(nearex, ext4_ext_pblock(newext));
        nearex->ee_len = newext->ee_len;
@@ -1962,6 +1952,7 @@ ext4_ext_put_in_cache(struct inode *inode, ext4_lblk_t block,
        struct ext4_ext_cache *cex;
        BUG_ON(len == 0);
        spin_lock(&EXT4_I(inode)->i_block_reservation_lock);
+        trace_ext4_ext_put_in_cache(inode, block, len, start);
        cex = &EXT4_I(inode)->i_cached_extent;
        cex->ec_block = block;
        cex->ec_len = len;
@@ -2063,6 +2054,7 @@ errout:
                sbi->extent_cache_misses++;
        else
                sbi->extent_cache_hits++;
+        trace_ext4_ext_in_cache(inode, block, ret);
        spin_unlock(&EXT4_I(inode)->i_block_reservation_lock);
        return ret;
 }
@@ -2130,6 +2122,8 @@ static int ext4_ext_rm_idx(handle_t *handle, struct inode *inode,
        if (err)
                return err;
        ext_debug("index is empty, remove it, free block %llu\n", leaf);
+        trace_ext4_ext_rm_idx(inode, leaf);
        ext4_free_blocks(handle, inode, NULL, leaf, 1,
                         EXT4_FREE_BLOCKS_METADATA | EXT4_FREE_BLOCKS_FORGET);
        return err;
@@ -2158,7 +2152,7 @@ int ext4_ext_calc_credits_for_single_extent(struct inode *inode, int nrblocks,
                         *  need to account for leaf block credit
                         *
                         *  bitmaps and block group descriptor blocks
-                         *  and other metadat blocks still need to be
+                         *  and other metadata blocks still need to be
                         *  accounted.
                         */
                        /* 1 bitmap, 1 block group descriptor */
@@ -2195,14 +2189,40 @@ int ext4_ext_index_trans_blocks(struct inode *inode, int nrblocks, int chunk)
 }
 static int ext4_remove_blocks(handle_t *handle, struct inode *inode,
-                                struct ext4_extent *ex,
+                              struct ext4_extent *ex,
-                                ext4_lblk_t from, ext4_lblk_t to)
+                              ext4_fsblk_t *partial_cluster,
+                              ext4_lblk_t from, ext4_lblk_t to)
 {
+        struct ext4_sb_info *sbi = EXT4_SB(inode->i_sb);
        unsigned short ee_len =  ext4_ext_get_actual_len(ex);
+        ext4_fsblk_t pblk;
        int flags = EXT4_FREE_BLOCKS_FORGET;
        if (S_ISDIR(inode->i_mode) || S_ISLNK(inode->i_mode))
                flags |= EXT4_FREE_BLOCKS_METADATA;
+        /*
+         * For bigalloc file systems, we never free a partial cluster
+         * at the beginning of the extent.  Instead, we make a note
+         * that we tried freeing the cluster, and check to see if we
+         * need to free it on a subsequent call to ext4_remove_blocks,
+         * or at the end of the ext4_truncate() operation.
+         */
+        flags |= EXT4_FREE_BLOCKS_NOFREE_FIRST_CLUSTER;
+        trace_ext4_remove_blocks(inode, ex, from, to, *partial_cluster);
+        /*
+         * If we have a partial cluster, and it's different from the
+         * cluster of the last block, we need to explicitly free the
+         * partial cluster here.
+         */
+        pblk = ext4_ext_pblock(ex) + ee_len - 1;
+        if (*partial_cluster && (EXT4_B2C(sbi, pblk) != *partial_cluster)) {
+                ext4_free_blocks(handle, inode, NULL,
+                                 EXT4_C2B(sbi, *partial_cluster),
+                                 sbi->s_cluster_ratio, flags);
+                *partial_cluster = 0;
+        }
 #ifdef EXTENTS_STATS
        {
                struct ext4_sb_info *sbi = EXT4_SB(inode->i_sb);
@@ -2222,12 +2242,24 @@ static int ext4_remove_blocks(handle_t *handle, struct inode *inode,
            && to == le32_to_cpu(ex->ee_block) + ee_len - 1) {
                /* tail removal */
                ext4_lblk_t num;
-                ext4_fsblk_t start;
                num = le32_to_cpu(ex->ee_block) + ee_len - from;
-                start = ext4_ext_pblock(ex) + ee_len - num;
+                pblk = ext4_ext_pblock(ex) + ee_len - num;
-                ext_debug("free last %u blocks starting %llu\n", num, start);
+                ext_debug("free last %u blocks starting %llu\n", num, pblk);
-                ext4_free_blocks(handle, inode, NULL, start, num, flags);
+                ext4_free_blocks(handle, inode, NULL, pblk, num, flags);
+                /*
+                 * If the block range to be freed didn't start at the
+                 * beginning of a cluster, and we removed the entire
+                 * extent, save the partial cluster here, since we
+                 * might need to delete if we determine that the
+                 * truncate operation has removed all of the blocks in
+                 * the cluster.
+                 */
+                if (pblk & (sbi->s_cluster_ratio - 1) &&
+                    (ee_len == num))
+                        *partial_cluster = EXT4_B2C(sbi, pblk);
+                else
+                        *partial_cluster = 0;
        } else if (from == le32_to_cpu(ex->ee_block)
                   && to <= le32_to_cpu(ex->ee_block) + ee_len - 1) {
                /* head removal */
@@ -2238,7 +2270,7 @@ static int ext4_remove_blocks(handle_t *handle, struct inode *inode,
                start = ext4_ext_pblock(ex);
                ext_debug("free first %u blocks starting %llu\n", num, start);
-                ext4_free_blocks(handle, inode, 0, start, num, flags);
+                ext4_free_blocks(handle, inode, NULL, start, num, flags);
        } else {
                printk(KERN_INFO "strange request: removal(2) "
@@ -2262,19 +2294,19 @@ static int ext4_remove_blocks(handle_t *handle, struct inode *inode,
 */
 static int
 ext4_ext_rm_leaf(handle_t *handle, struct inode *inode,
-                struct ext4_ext_path *path, ext4_lblk_t start,
+                 struct ext4_ext_path *path, ext4_fsblk_t *partial_cluster,
-                ext4_lblk_t end)
+                 ext4_lblk_t start, ext4_lblk_t end)
 {
+        struct ext4_sb_info *sbi = EXT4_SB(inode->i_sb);
        int err = 0, correct_index = 0;
        int depth = ext_depth(inode), credits;
        struct ext4_extent_header *eh;
-        ext4_lblk_t a, b, block;
+        ext4_lblk_t a, b;
        unsigned num;
        ext4_lblk_t ex_ee_block;
        unsigned short ex_ee_len;
        unsigned uninitialized = 0;
        struct ext4_extent *ex;
-        struct ext4_map_blocks map;
        /* the header must be checked already in ext4_ext_remove_space() */
        ext_debug("truncate since %u in leaf\n", start);
@@ -2291,6 +2323,8 @@ ext4_ext_rm_leaf(handle_t *handle, struct inode *inode,
        ex_ee_block = le32_to_cpu(ex->ee_block);
        ex_ee_len = ext4_ext_get_actual_len(ex);
+        trace_ext4_ext_rm_leaf(inode, start, ex, *partial_cluster);
        while (ex >= EXT_FIRST_EXTENT(eh) &&
                        ex_ee_block + ex_ee_len > start) {
@@ -2315,86 +2349,18 @@ ext4_ext_rm_leaf(handle_t *handle, struct inode *inode,
                        ex_ee_block = le32_to_cpu(ex->ee_block);
                        ex_ee_len = ext4_ext_get_actual_len(ex);
                        continue;
-                } else if (a != ex_ee_block &&
+                } else if (b != ex_ee_block + ex_ee_len - 1) {
-                        b != ex_ee_block + ex_ee_len - 1) {
+                        EXT4_ERROR_INODE(inode,"  bad truncate %u:%u\n",
-                        /*
+                                         start, end);
-                         * If this is a truncate, then this condition should
+                        err = -EIO;
-                         * never happen because at least one of the end points
+                        goto out;
-                         * needs to be on the edge of the extent.
-                         */
-                        if (end == EXT_MAX_BLOCKS - 1) {
-                                ext_debug("  bad truncate %u:%u\n",
-                                                start, end);
-                                block = 0;
-                                num = 0;
-                                err = -EIO;
-                                goto out;
-                        }
-                        /*
-                         * else this is a hole punch, so the extent needs to
-                         * be split since neither edge of the hole is on the
-                         * extent edge
-                         */
-                        else{
-                                map.m_pblk = ext4_ext_pblock(ex);
-                                map.m_lblk = ex_ee_block;
-                                map.m_len = b - ex_ee_block;
-                                err = ext4_split_extent(handle,
-                                        inode, path, &map, 0,
-                                        EXT4_GET_BLOCKS_PUNCH_OUT_EXT |
-                                        EXT4_GET_BLOCKS_PRE_IO);
-                                if (err < 0)
-                                        goto out;
-                                ex_ee_len = ext4_ext_get_actual_len(ex);
-                                b = ex_ee_block+ex_ee_len - 1 < end ?
-                                        ex_ee_block+ex_ee_len - 1 : end;
-                                /* Then remove tail of this extent */
-                                block = ex_ee_block;
-                                num = a - block;
-                        }
                } else if (a != ex_ee_block) {
                        /* remove tail of the extent */
-                        block = ex_ee_block;
+                        num = a - ex_ee_block;
-                        num = a - block;
-                } else if (b != ex_ee_block + ex_ee_len - 1) {
-                        /* remove head of the extent */
-                        block = b;
-                        num =  ex_ee_block + ex_ee_len - b;
-                        /*
-                         * If this is a truncate, this condition
-                         * should never happen
-                         */
-                        if (end == EXT_MAX_BLOCKS - 1) {
-                                ext_debug("  bad truncate %u:%u\n",
-                                        start, end);
-                                err = -EIO;
-                                goto out;
-                        }
                } else {
                        /* remove whole extent: excellent! */
-                        block = ex_ee_block;
                        num = 0;
-                        if (a != ex_ee_block) {
-                                ext_debug("  bad truncate %u:%u\n",
-                                        start, end);
-                                err = -EIO;
-                                goto out;
-                        }
-                        if (b != ex_ee_block + ex_ee_len - 1) {
-                                ext_debug("  bad truncate %u:%u\n",
-                                        start, end);
-                                err = -EIO;
-                                goto out;
-                        }
                }
                /*
                 * 3 for leaf, sb, and inode plus 2 (bmap and group
                 * descriptor) for each block group; assume two block
@@ -2416,23 +2382,15 @@ ext4_ext_rm_leaf(handle_t *handle, struct inode *inode,
                if (err)
                        goto out;
-                err = ext4_remove_blocks(handle, inode, ex, a, b);
+                err = ext4_remove_blocks(handle, inode, ex, partial_cluster,
+                                         a, b);
                if (err)
                        goto out;
-                if (num == 0) {
+                if (num == 0)
                        /* this extent is removed; mark slot entirely unused */
                        ext4_ext_store_pblock(ex, 0);
-                } else if (block != ex_ee_block) {
-                        /*
-                         * If this was a head removal, then we need to update
-                         * the physical block since it is now at a different
-                         * location
-                         */
-                        ext4_ext_store_pblock(ex, ext4_ext_pblock(ex) + (b-a));
-                }
-                ex->ee_block = cpu_to_le32(block);
                ex->ee_len = cpu_to_le16(num);
                /*
                 * Do not mark uninitialized if all the blocks in the
@@ -2440,11 +2398,6 @@ ext4_ext_rm_leaf(handle_t *handle, struct inode *inode,
                 */
                if (uninitialized && num)
                        ext4_ext_mark_uninitialized(ex);
-                err = ext4_ext_dirty(handle, inode, path + depth);
-                if (err)
-                        goto out;
                /*
                 * If the extent was completely released,
                 * we need to remove it from the leaf
@@ -2464,9 +2417,14 @@ ext4_ext_rm_leaf(handle_t *handle, struct inode *inode,
                                        sizeof(struct ext4_extent));
                        }
                        le16_add_cpu(&eh->eh_entries, -1);
-                }
+                } else
+                        *partial_cluster = 0;
-                ext_debug("new extent: %u:%u:%llu\n", block, num,
+                err = ext4_ext_dirty(handle, inode, path + depth);
+                if (err)
+                        goto out;
+                ext_debug("new extent: %u:%u:%llu\n", ex_ee_block, num,
                                ext4_ext_pblock(ex));
                ex--;
                ex_ee_block = le32_to_cpu(ex->ee_block);
@@ -2476,6 +2434,25 @@ ext4_ext_rm_leaf(handle_t *handle, struct inode *inode,
        if (correct_index && eh->eh_entries)
                err = ext4_ext_correct_indexes(handle, inode, path);
+        /*
+         * If there is still a entry in the leaf node, check to see if
+         * it references the partial cluster.  This is the only place
+         * where it could; if it doesn't, we can free the cluster.
+         */
+        if (*partial_cluster && ex >= EXT_FIRST_EXTENT(eh) &&
+            (EXT4_B2C(sbi, ext4_ext_pblock(ex) + ex_ee_len - 1) !=
+             *partial_cluster)) {
+                int flags = EXT4_FREE_BLOCKS_FORGET;
+                if (S_ISDIR(inode->i_mode) || S_ISLNK(inode->i_mode))
+                        flags |= EXT4_FREE_BLOCKS_METADATA;
+                ext4_free_blocks(handle, inode, NULL,
+                                 EXT4_C2B(sbi, *partial_cluster),
+                                 sbi->s_cluster_ratio, flags);
+                *partial_cluster = 0;
+        }
        /* if this leaf is free, then we should
         * remove it from index block above */
        if (err == 0 && eh->eh_entries == 0 && path[depth].p_bh != NULL)
@@ -2511,6 +2488,7 @@ static int ext4_ext_remove_space(struct inode *inode, ext4_lblk_t start)
        struct super_block *sb = inode->i_sb;
        int depth = ext_depth(inode);
        struct ext4_ext_path *path;
+        ext4_fsblk_t partial_cluster = 0;
        handle_t *handle;
        int i, err;
@@ -2524,6 +2502,8 @@ static int ext4_ext_remove_space(struct inode *inode, ext4_lblk_t start)
 again:
        ext4_ext_invalidate_cache(inode);
+        trace_ext4_ext_remove_space(inode, start, depth);
        /*
         * We start scanning from right side, freeing all the blocks
         * after i_size and walking into the tree depth-wise.
@@ -2546,7 +2526,8 @@ again:
                if (i == depth) {
                        /* this is leaf block */
                        err = ext4_ext_rm_leaf(handle, inode, path,
-                                        start, EXT_MAX_BLOCKS - 1);
+                                               &partial_cluster, start,
+                                               EXT_MAX_BLOCKS - 1);
                        /* root level has p_bh == NULL, brelse() eats this */
                        brelse(path[i].p_bh);
                        path[i].p_bh = NULL;
@@ -2618,6 +2599,24 @@ again:
                }
        }
+        trace_ext4_ext_remove_space_done(inode, start, depth, partial_cluster,
+                        path->p_hdr->eh_entries);
+        /* If we still have something in the partial cluster and we have removed
+         * even the first extent, then we should free the blocks in the partial
+         * cluster as well. */
+        if (partial_cluster && path->p_hdr->eh_entries == 0) {
+                int flags = EXT4_FREE_BLOCKS_FORGET;
+                if (S_ISDIR(inode->i_mode) || S_ISLNK(inode->i_mode))
+                        flags |= EXT4_FREE_BLOCKS_METADATA;
+                ext4_free_blocks(handle, inode, NULL,
+                                 EXT4_C2B(EXT4_SB(sb), partial_cluster),
+                                 EXT4_SB(sb)->s_cluster_ratio, flags);
+                partial_cluster = 0;
+        }
        /* TODO: flexible tree reduction should be here */
        if (path->p_hdr->eh_entries == 0) {
                /*
@@ -2909,17 +2908,29 @@ out:
 *   a> There is no split required: Entire extent should be initialized
 *   b> Splits in two extents: Write is happening at either end of the extent
 *   c> Splits in three extents: Somone is writing in middle of the extent
+ *
+ * Pre-conditions:
+ *  - The extent pointed to by 'path' is uninitialized.
+ *  - The extent pointed to by 'path' contains a superset
+ *    of the logical span [map->m_lblk, map->m_lblk + map->m_len).
+ *
+ * Post-conditions on success:
+ *  - the returned value is the number of blocks beyond map->l_lblk
+ *    that are allocated and initialized.
+ *    It is guaranteed to be >= map->m_len.
 */
 static int ext4_ext_convert_to_initialized(handle_t *handle,
                                           struct inode *inode,
                                           struct ext4_map_blocks *map,
                                           struct ext4_ext_path *path)
 {
+        struct ext4_extent_header *eh;
        struct ext4_map_blocks split_map;
        struct ext4_extent zero_ex;
        struct ext4_extent *ex;
        ext4_lblk_t ee_block, eof_block;
-        unsigned int allocated, ee_len, depth;
+        unsigned int ee_len, depth;
+        int allocated;
        int err = 0;
        int split_flag = 0;
@@ -2933,11 +2944,93 @@ static int ext4_ext_convert_to_initialized(handle_t *handle,
                eof_block = map->m_lblk + map->m_len;
        depth = ext_depth(inode);
+        eh = path[depth].p_hdr;
        ex = path[depth].p_ext;
        ee_block = le32_to_cpu(ex->ee_block);
        ee_len = ext4_ext_get_actual_len(ex);
        allocated = ee_len - (map->m_lblk - ee_block);
+        trace_ext4_ext_convert_to_initialized_enter(inode, map, ex);
+        /* Pre-conditions */
+        BUG_ON(!ext4_ext_is_uninitialized(ex));
+        BUG_ON(!in_range(map->m_lblk, ee_block, ee_len));
+        BUG_ON(map->m_lblk + map->m_len > ee_block + ee_len);
+        /*
+         * Attempt to transfer newly initialized blocks from the currently
+         * uninitialized extent to its left neighbor. This is much cheaper
+         * than an insertion followed by a merge as those involve costly
+         * memmove() calls. This is the common case in steady state for
+         * workloads doing fallocate(FALLOC_FL_KEEP_SIZE) followed by append
+         * writes.
+         *
+         * Limitations of the current logic:
+         *  - L1: we only deal with writes at the start of the extent.
+         *    The approach could be extended to writes at the end
+         *    of the extent but this scenario was deemed less common.
+         *  - L2: we do not deal with writes covering the whole extent.
+         *    This would require removing the extent if the transfer
+         *    is possible.
+         *  - L3: we only attempt to merge with an extent stored in the
+         *    same extent tree node.
+         */
+        if ((map->m_lblk == ee_block) &&        /*L1*/
+                (map->m_len < ee_len) &&        /*L2*/
+                (ex > EXT_FIRST_EXTENT(eh))) {  /*L3*/
+                struct ext4_extent *prev_ex;
+                ext4_lblk_t prev_lblk;
+                ext4_fsblk_t prev_pblk, ee_pblk;
+                unsigned int prev_len, write_len;
+                prev_ex = ex - 1;
+                prev_lblk = le32_to_cpu(prev_ex->ee_block);
+                prev_len = ext4_ext_get_actual_len(prev_ex);
+                prev_pblk = ext4_ext_pblock(prev_ex);
+                ee_pblk = ext4_ext_pblock(ex);
+                write_len = map->m_len;
+                /*
+                 * A transfer of blocks from 'ex' to 'prev_ex' is allowed
+                 * upon those conditions:
+                 * - C1: prev_ex is initialized,
+                 * - C2: prev_ex is logically abutting ex,
+                 * - C3: prev_ex is physically abutting ex,
+                 * - C4: prev_ex can receive the additional blocks without
+                 *   overflowing the (initialized) length limit.
+                 */
+                if ((!ext4_ext_is_uninitialized(prev_ex)) &&            /*C1*/
+                        ((prev_lblk + prev_len) == ee_block) &&         /*C2*/
+                        ((prev_pblk + prev_len) == ee_pblk) &&          /*C3*/
+                        (prev_len < (EXT_INIT_MAX_LEN - write_len))) {  /*C4*/
+                        err = ext4_ext_get_access(handle, inode, path + depth);
+                        if (err)
+                                goto out;
+                        trace_ext4_ext_convert_to_initialized_fastpath(inode,
+                                map, ex, prev_ex);
+                        /* Shift the start of ex by 'write_len' blocks */
+                        ex->ee_block = cpu_to_le32(ee_block + write_len);
+                        ext4_ext_store_pblock(ex, ee_pblk + write_len);
+                        ex->ee_len = cpu_to_le16(ee_len - write_len);
+                        ext4_ext_mark_uninitialized(ex); /* Restore the flag */
+                        /* Extend prev_ex by 'write_len' blocks */
+                        prev_ex->ee_len = cpu_to_le16(prev_len + write_len);
+                        /* Mark the block containing both extents as dirty */
+                        ext4_ext_dirty(handle, inode, path + depth);
+                        /* Update path to point to the right extent */
+                        path[depth].p_ext = prev_ex;
+                        /* Result: number of initialized blocks past m_lblk */
+                        allocated = write_len;
+                        goto out;
+                }
+        }
        WARN_ON(map->m_lblk < ee_block);
        /*
         * It is safe to convert extent to initialized via explicit
@@ -3165,6 +3258,192 @@ static int check_eofblocks_fl(handle_t *handle, struct inode *inode,
        return ext4_mark_inode_dirty(handle, inode);
 }
+/**
+ * ext4_find_delalloc_range: find delayed allocated block in the given range.
+ *
+ * Goes through the buffer heads in the range [lblk_start, lblk_end] and returns
+ * whether there are any buffers marked for delayed allocation. It returns '1'
+ * on the first delalloc'ed buffer head found. If no buffer head in the given
+ * range is marked for delalloc, it returns 0.
+ * lblk_start should always be <= lblk_end.
+ * search_hint_reverse is to indicate that searching in reverse from lblk_end to
+ * lblk_start might be more efficient (i.e., we will likely hit the delalloc'ed
+ * block sooner). This is useful when blocks are truncated sequentially from
+ * lblk_start towards lblk_end.
+ */
+static int ext4_find_delalloc_range(struct inode *inode,
+                                    ext4_lblk_t lblk_start,
+                                    ext4_lblk_t lblk_end,
+                                    int search_hint_reverse)
+{
+        struct address_space *mapping = inode->i_mapping;
+        struct buffer_head *head, *bh = NULL;
+        struct page *page;
+        ext4_lblk_t i, pg_lblk;
+        pgoff_t index;
+        /* reverse search wont work if fs block size is less than page size */
+        if (inode->i_blkbits < PAGE_CACHE_SHIFT)
+                search_hint_reverse = 0;
+        if (search_hint_reverse)
+                i = lblk_end;
+        else
+                i = lblk_start;
+        index = i >> (PAGE_CACHE_SHIFT - inode->i_blkbits);
+        while ((i >= lblk_start) && (i <= lblk_end)) {
+                page = find_get_page(mapping, index);
+                if (!page)
+                        goto nextpage;
+                if (!page_has_buffers(page))
+                        goto nextpage;
+                head = page_buffers(page);
+                if (!head)
+                        goto nextpage;
+                bh = head;
+                pg_lblk = index << (PAGE_CACHE_SHIFT -
+                                                inode->i_blkbits);
+                do {
+                        if (unlikely(pg_lblk < lblk_start)) {
+                                /*
+                                 * This is possible when fs block size is less
+                                 * than page size and our cluster starts/ends in
+                                 * middle of the page. So we need to skip the
+                                 * initial few blocks till we reach the 'lblk'
+                                 */
+                                pg_lblk++;
+                                continue;
+                        }
+                        /* Check if the buffer is delayed allocated and that it
+                         * is not yet mapped. (when da-buffers are mapped during
+                         * their writeout, their da_mapped bit is set.)
+                         */
+                        if (buffer_delay(bh) && !buffer_da_mapped(bh)) {
+                                page_cache_release(page);
+                                trace_ext4_find_delalloc_range(inode,
+                                                lblk_start, lblk_end,
+                                                search_hint_reverse,
+                                                1, i);
+                                return 1;
+                        }
+                        if (search_hint_reverse)
+                                i--;
+                        else
+                                i++;
+                } while ((i >= lblk_start) && (i <= lblk_end) &&
+                                ((bh = bh->b_this_page) != head));
+nextpage:
+                if (page)
+                        page_cache_release(page);
+                /*
+                 * Move to next page. 'i' will be the first lblk in the next
+                 * page.
+                 */
+                if (search_hint_reverse)
+                        index--;
+                else
+                        index++;
+                i = index << (PAGE_CACHE_SHIFT - inode->i_blkbits);
+        }
+        trace_ext4_find_delalloc_range(inode, lblk_start, lblk_end,
+                                        search_hint_reverse, 0, 0);
+        return 0;
+}
+int ext4_find_delalloc_cluster(struct inode *inode, ext4_lblk_t lblk,
+                               int search_hint_reverse)
+{
+        struct ext4_sb_info *sbi = EXT4_SB(inode->i_sb);
+        ext4_lblk_t lblk_start, lblk_end;
+        lblk_start = lblk & (~(sbi->s_cluster_ratio - 1));
+        lblk_end = lblk_start + sbi->s_cluster_ratio - 1;
+        return ext4_find_delalloc_range(inode, lblk_start, lblk_end,
+                                        search_hint_reverse);
+}
+/**
+ * Determines how many complete clusters (out of those specified by the 'map')
+ * are under delalloc and were reserved quota for.
+ * This function is called when we are writing out the blocks that were
+ * originally written with their allocation delayed, but then the space was
+ * allocated using fallocate() before the delayed allocation could be resolved.
+ * The cases to look for are:
+ * ('=' indicated delayed allocated blocks
+ *  '-' indicates non-delayed allocated blocks)
+ * (a) partial clusters towards beginning and/or end outside of allocated range
+ *     are not delalloc'ed.
+ *      Ex:
+ *      |----c---=|====c====|====c====|===-c----|
+ *               |++++++ allocated ++++++|
+ *      ==> 4 complete clusters in above example
+ *
+ * (b) partial cluster (outside of allocated range) towards either end is
+ *     marked for delayed allocation. In this case, we will exclude that
+ *     cluster.
+ *      Ex:
+ *      |----====c========|========c========|
+ *           |++++++ allocated ++++++|
+ *      ==> 1 complete clusters in above example
+ *
+ *      Ex:
+ *      |================c================|
+ *            |++++++ allocated ++++++|
+ *      ==> 0 complete clusters in above example
+ *
+ * The ext4_da_update_reserve_space will be called only if we
+ * determine here that there were some "entire" clusters that span
+ * this 'allocated' range.
+ * In the non-bigalloc case, this function will just end up returning num_blks
+ * without ever calling ext4_find_delalloc_range.
+ */
+static unsigned int
+get_reserved_cluster_alloc(struct inode *inode, ext4_lblk_t lblk_start,
+                           unsigned int num_blks)
+{
+        struct ext4_sb_info *sbi = EXT4_SB(inode->i_sb);
+        ext4_lblk_t alloc_cluster_start, alloc_cluster_end;
+        ext4_lblk_t lblk_from, lblk_to, c_offset;
+        unsigned int allocated_clusters = 0;
+        alloc_cluster_start = EXT4_B2C(sbi, lblk_start);
+        alloc_cluster_end = EXT4_B2C(sbi, lblk_start + num_blks - 1);
+        /* max possible clusters for this allocation */
+        allocated_clusters = alloc_cluster_end - alloc_cluster_start + 1;
+        trace_ext4_get_reserved_cluster_alloc(inode, lblk_start, num_blks);
+        /* Check towards left side */
+        c_offset = lblk_start & (sbi->s_cluster_ratio - 1);
+        if (c_offset) {
+                lblk_from = lblk_start & (~(sbi->s_cluster_ratio - 1));
+                lblk_to = lblk_from + c_offset - 1;
+                if (ext4_find_delalloc_range(inode, lblk_from, lblk_to, 0))
+                        allocated_clusters--;
+        }
+        /* Now check towards right. */
+        c_offset = (lblk_start + num_blks) & (sbi->s_cluster_ratio - 1);
+        if (allocated_clusters && c_offset) {
+                lblk_from = lblk_start + num_blks;
+                lblk_to = lblk_from + (sbi->s_cluster_ratio - c_offset) - 1;
+                if (ext4_find_delalloc_range(inode, lblk_from, lblk_to, 0))
+                        allocated_clusters--;
+        }
+        return allocated_clusters;
+}
 static int
 ext4_ext_handle_uninitialized_extents(handle_t *handle, struct inode *inode,
                        struct ext4_map_blocks *map,
@@ -3181,6 +3460,9 @@ ext4_ext_handle_uninitialized_extents(handle_t *handle, struct inode *inode,
                  flags, allocated);
        ext4_ext_show_leaf(inode, path);
+        trace_ext4_ext_handle_uninitialized_extents(inode, map, allocated,
+                                                    newblock);
        /* get_block() before submit the IO, split the extent */
        if ((flags & EXT4_GET_BLOCKS_PRE_IO)) {
                ret = ext4_split_unwritten_extents(handle, inode, map,
@@ -3190,10 +3472,9 @@ ext4_ext_handle_uninitialized_extents(handle_t *handle, struct inode *inode,
                 * that this IO needs to conversion to written when IO is
                 * completed
                 */
-                if (io && !(io->flag & EXT4_IO_END_UNWRITTEN)) {
+                if (io)
-                        io->flag = EXT4_IO_END_UNWRITTEN;
+                        ext4_set_io_unwritten_flag(inode, io);
-                        atomic_inc(&EXT4_I(inode)->i_aiodio_unwritten);
+                else
-                } else
                        ext4_set_inode_state(inode, EXT4_STATE_DIO_UNWRITTEN);
                if (ext4_should_dioread_nolock(inode))
                        map->m_flags |= EXT4_MAP_UNINIT;
@@ -3234,14 +3515,8 @@ ext4_ext_handle_uninitialized_extents(handle_t *handle, struct inode *inode,
        /* buffered write, writepage time, convert*/
        ret = ext4_ext_convert_to_initialized(handle, inode, map, path);
-        if (ret >= 0) {
+        if (ret >= 0)
                ext4_update_inode_fsync_trans(handle, inode, 1);
-                err = check_eofblocks_fl(handle, inode, map->m_lblk, path,
-                                         map->m_len);
-                if (err < 0)
-                        goto out2;
-        }
 out:
        if (ret <= 0) {
                err = ret;
@@ -3270,11 +3545,24 @@ out:
         * But fallocate would have already updated quota and block
         * count for this offset. So cancel these reservation
         */
-        if (flags & EXT4_GET_BLOCKS_DELALLOC_RESERVE)
+        if (flags & EXT4_GET_BLOCKS_DELALLOC_RESERVE) {
-                ext4_da_update_reserve_space(inode, allocated, 0);
+                unsigned int reserved_clusters;
+                reserved_clusters = get_reserved_cluster_alloc(inode,
+                                map->m_lblk, map->m_len);
+                if (reserved_clusters)
+                        ext4_da_update_reserve_space(inode,
+                                                     reserved_clusters,
+                                                     0);
+        }
 map_out:
        map->m_flags |= EXT4_MAP_MAPPED;
+        if ((flags & EXT4_GET_BLOCKS_KEEP_SIZE) == 0) {
+                err = check_eofblocks_fl(handle, inode, map->m_lblk, path,
+                                         map->m_len);
+                if (err < 0)
+                        goto out2;
+        }
 out1:
        if (allocated > map->m_len)
                allocated = map->m_len;
@@ -3290,6 +3578,111 @@ out2:
 }
 /*
+ * get_implied_cluster_alloc - check to see if the requested
+ * allocation (in the map structure) overlaps with a cluster already
+ * allocated in an extent.
+ *      @sb     The filesystem superblock structure
+ *      @map    The requested lblk->pblk mapping
+ *      @ex     The extent structure which might contain an implied
+ *                      cluster allocation
+ *
+ * This function is called by ext4_ext_map_blocks() after we failed to
+ * find blocks that were already in the inode's extent tree.  Hence,
+ * we know that the beginning of the requested region cannot overlap
+ * the extent from the inode's extent tree.  There are three cases we
+ * want to catch.  The first is this case:
+ *
+ *               |--- cluster # N--|
+ *    |--- extent ---|  |---- requested region ---|
+ *                      |==========|
+ *
+ * The second case that we need to test for is this one:
+ *
+ *   |--------- cluster # N ----------------|
+ *         |--- requested region --|   |------- extent ----|
+ *         |=======================|
+ *
+ * The third case is when the requested region lies between two extents
+ * within the same cluster:
+ *          |------------- cluster # N-------------|
+ * |----- ex -----|                  |---- ex_right ----|
+ *                  |------ requested region ------|
+ *                  |================|
+ *
+ * In each of the above cases, we need to set the map->m_pblk and
+ * map->m_len so it corresponds to the return the extent labelled as
+ * "|====|" from cluster #N, since it is already in use for data in
+ * cluster EXT4_B2C(sbi, map->m_lblk).  We will then return 1 to
+ * signal to ext4_ext_map_blocks() that map->m_pblk should be treated
+ * as a new "allocated" block region.  Otherwise, we will return 0 and
+ * ext4_ext_map_blocks() will then allocate one or more new clusters
+ * by calling ext4_mb_new_blocks().
+ */
+static int get_implied_cluster_alloc(struct super_block *sb,
+                                     struct ext4_map_blocks *map,
+                                     struct ext4_extent *ex,
+                                     struct ext4_ext_path *path)
+{
+        struct ext4_sb_info *sbi = EXT4_SB(sb);
+        ext4_lblk_t c_offset = map->m_lblk & (sbi->s_cluster_ratio-1);
+        ext4_lblk_t ex_cluster_start, ex_cluster_end;
+        ext4_lblk_t rr_cluster_start, rr_cluster_end;
+        ext4_lblk_t ee_block = le32_to_cpu(ex->ee_block);
+        ext4_fsblk_t ee_start = ext4_ext_pblock(ex);
+        unsigned short ee_len = ext4_ext_get_actual_len(ex);
+        /* The extent passed in that we are trying to match */
+        ex_cluster_start = EXT4_B2C(sbi, ee_block);
+        ex_cluster_end = EXT4_B2C(sbi, ee_block + ee_len - 1);
+        /* The requested region passed into ext4_map_blocks() */
+        rr_cluster_start = EXT4_B2C(sbi, map->m_lblk);
+        rr_cluster_end = EXT4_B2C(sbi, map->m_lblk + map->m_len - 1);
+        if ((rr_cluster_start == ex_cluster_end) ||
+            (rr_cluster_start == ex_cluster_start)) {
+                if (rr_cluster_start == ex_cluster_end)
+                        ee_start += ee_len - 1;
+                map->m_pblk = (ee_start & ~(sbi->s_cluster_ratio - 1)) +
+                        c_offset;
+                map->m_len = min(map->m_len,
+                                 (unsigned) sbi->s_cluster_ratio - c_offset);
+                /*
+                 * Check for and handle this case:
+                 *
+                 *   |--------- cluster # N-------------|
+                 *                     |------- extent ----|
+                 *         |--- requested region ---|
+                 *         |===========|
+                 */
+                if (map->m_lblk < ee_block)
+                        map->m_len = min(map->m_len, ee_block - map->m_lblk);
+                /*
+                 * Check for the case where there is already another allocated
+                 * block to the right of 'ex' but before the end of the cluster.
+                 *
+                 *          |------------- cluster # N-------------|
+                 * |----- ex -----|                  |---- ex_right ----|
+                 *                  |------ requested region ------|
+                 *                  |================|
+                 */
+                if (map->m_lblk > ee_block) {
+                        ext4_lblk_t next = ext4_ext_next_allocated_block(path);
+                        map->m_len = min(map->m_len, next - map->m_lblk);
+                }
+                trace_ext4_get_implied_cluster_alloc_exit(sb, map, 1);
+                return 1;
+        }
+        trace_ext4_get_implied_cluster_alloc_exit(sb, map, 0);
+        return 0;
+}
+/*
 * Block allocation/map/preallocation routine for extents based files
 *
 *
@@ -3311,15 +3704,17 @@ int ext4_ext_map_blocks(handle_t *handle, struct inode *inode,
                        struct ext4_map_blocks *map, int flags)
 {
        struct ext4_ext_path *path = NULL;
-        struct ext4_extent newex, *ex;
+        struct ext4_extent newex, *ex, *ex2;
+        struct ext4_sb_info *sbi = EXT4_SB(inode->i_sb);
        ext4_fsblk_t newblock = 0;
-        int err = 0, depth, ret;
+        int free_on_err = 0, err = 0, depth, ret;
-        unsigned int allocated = 0;
+        unsigned int allocated = 0, offset = 0;
+        unsigned int allocated_clusters = 0;
        unsigned int punched_out = 0;
        unsigned int result = 0;
        struct ext4_allocation_request ar;
        ext4_io_end_t *io = EXT4_I(inode)->cur_aio_dio;
-        struct ext4_map_blocks punch_map;
+        ext4_lblk_t cluster_offset;
        ext_debug("blocks %u/%u requested for inode %lu\n",
                  map->m_lblk, map->m_len, inode->i_ino);
@@ -3329,6 +3724,10 @@ int ext4_ext_map_blocks(handle_t *handle, struct inode *inode,
        if (!(flags & EXT4_GET_BLOCKS_PUNCH_OUT_EXT) &&
                ext4_ext_in_cache(inode, map->m_lblk, &newex)) {
                if (!newex.ee_start_lo && !newex.ee_start_hi) {
+                        if ((sbi->s_cluster_ratio > 1) &&
+                            ext4_find_delalloc_cluster(inode, map->m_lblk, 0))
+                                map->m_flags |= EXT4_MAP_FROM_CLUSTER;
                        if ((flags & EXT4_GET_BLOCKS_CREATE) == 0) {
                                /*
                                 * block isn't allocated yet and
@@ -3339,6 +3738,8 @@ int ext4_ext_map_blocks(handle_t *handle, struct inode *inode,
                        /* we should allocate requested block */
                } else {
                        /* block is already allocated */
+                        if (sbi->s_cluster_ratio > 1)
+                                map->m_flags |= EXT4_MAP_FROM_CLUSTER;
                        newblock = map->m_lblk
                                   - le32_to_cpu(newex.ee_block)
                                   + ext4_ext_pblock(&newex);
@@ -3384,8 +3785,14 @@ int ext4_ext_map_blocks(handle_t *handle, struct inode *inode,
                 * we split out initialized portions during a write.
                 */
                ee_len = ext4_ext_get_actual_len(ex);
+                trace_ext4_ext_show_extent(inode, ee_block, ee_start, ee_len);
                /* if found extent covers block, simply return it */
                if (in_range(map->m_lblk, ee_block, ee_len)) {
+                        struct ext4_map_blocks punch_map;
+                        ext4_fsblk_t partial_cluster = 0;
                        newblock = map->m_lblk - ee_block + ee_start;
                        /* number of remaining blocks in the extent */
                        allocated = ee_len - (map->m_lblk - ee_block);
@@ -3469,7 +3876,8 @@ int ext4_ext_map_blocks(handle_t *handle, struct inode *inode,
                        ext4_ext_invalidate_cache(inode);
                        err = ext4_ext_rm_leaf(handle, inode, path,
-                                map->m_lblk, map->m_lblk + punched_out);
+                                               &partial_cluster, map->m_lblk,
+                                               map->m_lblk + punched_out);
                        if (!err && path->p_hdr->eh_entries == 0) {
                                /*
@@ -3492,6 +3900,10 @@ int ext4_ext_map_blocks(handle_t *handle, struct inode *inode,
                }
        }
+        if ((sbi->s_cluster_ratio > 1) &&
+            ext4_find_delalloc_cluster(inode, map->m_lblk, 0))
+                map->m_flags |= EXT4_MAP_FROM_CLUSTER;
        /*
         * requested block isn't allocated yet;
         * we couldn't try to create block if create flag is zero
@@ -3504,9 +3916,25 @@ int ext4_ext_map_blocks(handle_t *handle, struct inode *inode,
                ext4_ext_put_gap_in_cache(inode, path, map->m_lblk);
                goto out2;
        }
        /*
         * Okay, we need to do block allocation.
         */
+        map->m_flags &= ~EXT4_MAP_FROM_CLUSTER;
+        newex.ee_block = cpu_to_le32(map->m_lblk);
+        cluster_offset = map->m_lblk & (sbi->s_cluster_ratio-1);
+        /*
+         * If we are doing bigalloc, check to see if the extent returned
+         * by ext4_ext_find_extent() implies a cluster we can use.
+         */
+        if (cluster_offset && ex &&
+            get_implied_cluster_alloc(inode->i_sb, map, ex, path)) {
+                ar.len = allocated = map->m_len;
+                newblock = map->m_pblk;
+                map->m_flags |= EXT4_MAP_FROM_CLUSTER;
+                goto got_allocated_blocks;
+        }
        /* find neighbour allocated blocks */
        ar.lleft = map->m_lblk;
@@ -3514,10 +3942,21 @@ int ext4_ext_map_blocks(handle_t *handle, struct inode *inode,
        if (err)
                goto out2;
        ar.lright = map->m_lblk;
-        err = ext4_ext_search_right(inode, path, &ar.lright, &ar.pright);
+        ex2 = NULL;
+        err = ext4_ext_search_right(inode, path, &ar.lright, &ar.pright, &ex2);
        if (err)
                goto out2;
+        /* Check if the extent after searching to the right implies a
+         * cluster we can use. */
+        if ((sbi->s_cluster_ratio > 1) && ex2 &&
+            get_implied_cluster_alloc(inode->i_sb, map, ex2, path)) {
+                ar.len = allocated = map->m_len;
+                newblock = map->m_pblk;
+                map->m_flags |= EXT4_MAP_FROM_CLUSTER;
+                goto got_allocated_blocks;
+        }
        /*
         * See if request is beyond maximum number of blocks we can have in
         * a single extent. For an initialized extent this limit is
@@ -3532,9 +3971,8 @@ int ext4_ext_map_blocks(handle_t *handle, struct inode *inode,
                map->m_len = EXT_UNINIT_MAX_LEN;
        /* Check if we can really insert (m_lblk)::(m_lblk + m_len) extent */
-        newex.ee_block = cpu_to_le32(map->m_lblk);
        newex.ee_len = cpu_to_le16(map->m_len);
-        err = ext4_ext_check_overlap(inode, &newex, path);
+        err = ext4_ext_check_overlap(sbi, inode, &newex, path);
        if (err)
                allocated = ext4_ext_get_actual_len(&newex);
        else
@@ -3544,7 +3982,18 @@ int ext4_ext_map_blocks(handle_t *handle, struct inode *inode,
        ar.inode = inode;
        ar.goal = ext4_ext_find_goal(inode, path, map->m_lblk);
        ar.logical = map->m_lblk;
-        ar.len = allocated;
+        /*
+         * We calculate the offset from the beginning of the cluster
+         * for the logical block number, since when we allocate a
+         * physical cluster, the physical block should start at the
+         * same offset from the beginning of the cluster.  This is
+         * needed so that future calls to get_implied_cluster_alloc()
+         * work correctly.
+         */
+        offset = map->m_lblk & (sbi->s_cluster_ratio - 1);
+        ar.len = EXT4_NUM_B2C(sbi, offset+allocated);
+        ar.goal -= offset;
+        ar.logical -= offset;
        if (S_ISREG(inode->i_mode))
                ar.flags = EXT4_MB_HINT_DATA;
        else
@@ -3557,9 +4006,15 @@ int ext4_ext_map_blocks(handle_t *handle, struct inode *inode,
                goto out2;
        ext_debug("allocate new block: goal %llu, found %llu/%u\n",
                  ar.goal, newblock, allocated);
+        free_on_err = 1;
+        allocated_clusters = ar.len;
+        ar.len = EXT4_C2B(sbi, ar.len) - offset;
+        if (ar.len > allocated)
+                ar.len = allocated;
+got_allocated_blocks:
        /* try to insert new extent into found leaf and return */
-        ext4_ext_store_pblock(&newex, newblock);
+        ext4_ext_store_pblock(&newex, newblock + offset);
        newex.ee_len = cpu_to_le16(ar.len);
        /* Mark uninitialized */
        if (flags & EXT4_GET_BLOCKS_UNINIT_EXT){
@@ -3572,10 +4027,9 @@ int ext4_ext_map_blocks(handle_t *handle, struct inode *inode,
                 * that we need to perform conversion when IO is done.
                 */
                if ((flags & EXT4_GET_BLOCKS_PRE_IO)) {
-                        if (io && !(io->flag & EXT4_IO_END_UNWRITTEN)) {
+                        if (io)
-                                io->flag = EXT4_IO_END_UNWRITTEN;
+                                ext4_set_io_unwritten_flag(inode, io);
-                                atomic_inc(&EXT4_I(inode)->i_aiodio_unwritten);
+                        else
-                        } else
                                ext4_set_inode_state(inode,
                                                     EXT4_STATE_DIO_UNWRITTEN);
                }
@@ -3583,11 +4037,14 @@ int ext4_ext_map_blocks(handle_t *handle, struct inode *inode,
                        map->m_flags |= EXT4_MAP_UNINIT;
        }
-        err = check_eofblocks_fl(handle, inode, map->m_lblk, path, ar.len);
+        err = 0;
+        if ((flags & EXT4_GET_BLOCKS_KEEP_SIZE) == 0)
+                err = check_eofblocks_fl(handle, inode, map->m_lblk,
+                                         path, ar.len);
        if (!err)
                err = ext4_ext_insert_extent(handle, inode, path,
                                             &newex, flags);
-        if (err) {
+        if (err && free_on_err) {
                int fb_flags = flags & EXT4_GET_BLOCKS_DELALLOC_RESERVE ?
                        EXT4_FREE_BLOCKS_NO_QUOT_UPDATE : 0;
                /* free data blocks we just allocated */
@@ -3610,8 +4067,82 @@ int ext4_ext_map_blocks(handle_t *handle, struct inode *inode,
         * Update reserved blocks/metadata blocks after successful
         * block allocation which had been deferred till now.
         */
-        if (flags & EXT4_GET_BLOCKS_DELALLOC_RESERVE)
+        if (flags & EXT4_GET_BLOCKS_DELALLOC_RESERVE) {
-                ext4_da_update_reserve_space(inode, allocated, 1);
+                unsigned int reserved_clusters;
+                /*
+                 * Check how many clusters we had reserved this allocated range
+                 */
+                reserved_clusters = get_reserved_cluster_alloc(inode,
+                                                map->m_lblk, allocated);
+                if (map->m_flags & EXT4_MAP_FROM_CLUSTER) {
+                        if (reserved_clusters) {
+                                /*
+                                 * We have clusters reserved for this range.
+                                 * But since we are not doing actual allocation
+                                 * and are simply using blocks from previously
+                                 * allocated cluster, we should release the
+                                 * reservation and not claim quota.
+                                 */
+                                ext4_da_update_reserve_space(inode,
+                                                reserved_clusters, 0);
+                        }
+                } else {
+                        BUG_ON(allocated_clusters < reserved_clusters);
+                        /* We will claim quota for all newly allocated blocks.*/
+                        ext4_da_update_reserve_space(inode, allocated_clusters,
+                                                        1);
+                        if (reserved_clusters < allocated_clusters) {
+                                struct ext4_inode_info *ei = EXT4_I(inode);
+                                int reservation = allocated_clusters -
+                                                  reserved_clusters;
+                                /*
+                                 * It seems we claimed few clusters outside of
+                                 * the range of this allocation. We should give
+                                 * it back to the reservation pool. This can
+                                 * happen in the following case:
+                                 *
+                                 * * Suppose s_cluster_ratio is 4 (i.e., each
+                                 *   cluster has 4 blocks. Thus, the clusters
+                                 *   are [0-3],[4-7],[8-11]...
+                                 * * First comes delayed allocation write for
+                                 *   logical blocks 10 & 11. Since there were no
+                                 *   previous delayed allocated blocks in the
+                                 *   range [8-11], we would reserve 1 cluster
+                                 *   for this write.
+                                 * * Next comes write for logical blocks 3 to 8.
+                                 *   In this case, we will reserve 2 clusters
+                                 *   (for [0-3] and [4-7]; and not for [8-11] as
+                                 *   that range has a delayed allocated blocks.
+                                 *   Thus total reserved clusters now becomes 3.
+                                 * * Now, during the delayed allocation writeout
+                                 *   time, we will first write blocks [3-8] and
+                                 *   allocate 3 clusters for writing these
+                                 *   blocks. Also, we would claim all these
+                                 *   three clusters above.
+                                 * * Now when we come here to writeout the
+                                 *   blocks [10-11], we would expect to claim
+                                 *   the reservation of 1 cluster we had made
+                                 *   (and we would claim it since there are no
+                                 *   more delayed allocated blocks in the range
+                                 *   [8-11]. But our reserved cluster count had
+                                 *   already gone to 0.
+                                 *
+                                 *   Thus, at the step 4 above when we determine
+                                 *   that there are still some unwritten delayed
+                                 *   allocated blocks outside of our current
+                                 *   block range, we should increment the
+                                 *   reserved clusters count so that when the
+                                 *   remaining blocks finally gets written, we
+                                 *   could claim them.
+                                 */
+                                dquot_reserve_block(inode,
+                                                EXT4_C2B(sbi, reservation));
+                                spin_lock(&ei->i_block_reservation_lock);
+                                ei->i_reserved_data_blocks += reservation;
+                                spin_unlock(&ei->i_block_reservation_lock);
+                        }
+                }
+        }
        /*
         * Cache the extent and update transaction to commit on fdatasync only
@@ -3634,12 +4165,12 @@ out2:
                ext4_ext_drop_refs(path);
                kfree(path);
        }
-        trace_ext4_ext_map_blocks_exit(inode, map->m_lblk,
-                newblock, map->m_len, err ? err : allocated);
        result = (flags & EXT4_GET_BLOCKS_PUNCH_OUT_EXT) ?
                        punched_out : allocated;
+        trace_ext4_ext_map_blocks_exit(inode, map->m_lblk,
+                newblock, map->m_len, err ? err : result);
        return err ? err : result;
 }
@@ -3649,6 +4180,7 @@ void ext4_ext_truncate(struct inode *inode)
        struct super_block *sb = inode->i_sb;
        ext4_lblk_t last_block;
        handle_t *handle;
+        loff_t page_len;
        int err = 0;
        /*
@@ -3665,8 +4197,16 @@ void ext4_ext_truncate(struct inode *inode)
        if (IS_ERR(handle))
                return;
-        if (inode->i_size & (sb->s_blocksize - 1))
+        if (inode->i_size % PAGE_CACHE_SIZE != 0) {
-                ext4_block_truncate_page(handle, mapping, inode->i_size);
+                page_len = PAGE_CACHE_SIZE -
+                        (inode->i_size & (PAGE_CACHE_SIZE - 1));
+                err = ext4_discard_partial_page_buffers(handle,
+                        mapping, inode->i_size, page_len, 0);
+                if (err)
+                        goto out_stop;
+        }
        if (ext4_orphan_add(handle, inode))
                goto out_stop;
@@ -3760,6 +4300,7 @@ long ext4_fallocate(struct file *file, int mode, loff_t offset, loff_t len)
        int ret = 0;
        int ret2 = 0;
        int retries = 0;
+        int flags;
        struct ext4_map_blocks map;
        unsigned int credits, blkbits = inode->i_blkbits;
@@ -3796,6 +4337,16 @@ long ext4_fallocate(struct file *file, int mode, loff_t offset, loff_t len)
                trace_ext4_fallocate_exit(inode, offset, max_blocks, ret);
                return ret;
        }
+        flags = EXT4_GET_BLOCKS_CREATE_UNINIT_EXT;
+        if (mode & FALLOC_FL_KEEP_SIZE)
+                flags |= EXT4_GET_BLOCKS_KEEP_SIZE;
+        /*
+         * Don't normalize the request if it can fit in one extent so
+         * that it doesn't get unnecessarily split into multiple
+         * extents.
+         */
+        if (len <= EXT_UNINIT_MAX_LEN << blkbits)
+                flags |= EXT4_GET_BLOCKS_NO_NORMALIZE;
 retry:
        while (ret >= 0 && ret < max_blocks) {
                map.m_lblk = map.m_lblk + ret;
@@ -3805,9 +4356,7 @@ retry:
                        ret = PTR_ERR(handle);
                        break;
                }
-                ret = ext4_map_blocks(handle, inode, &map,
+                ret = ext4_map_blocks(handle, inode, &map, flags);
-                                      EXT4_GET_BLOCKS_CREATE_UNINIT_EXT |
-                                      EXT4_GET_BLOCKS_NO_NORMALIZE);
                if (ret <= 0) {
 #ifdef EXT4FS_DEBUG
                        WARN_ON(ret <= 0);
@@ -4102,7 +4651,6 @@ found_delayed_extent:
                return EXT_BREAK;
        return EXT_CONTINUE;
 }
 /* fiemap flags we can handle specified here */
 #define EXT4_FIEMAP_FLAGS       (FIEMAP_FLAG_SYNC|FIEMAP_FLAG_XATTR)
@@ -4162,17 +4710,28 @@ int ext4_ext_punch_hole(struct file *file, loff_t offset, loff_t length)
        struct address_space *mapping = inode->i_mapping;
        struct ext4_map_blocks map;
        handle_t *handle;
-        loff_t first_block_offset, last_block_offset, block_len;
+        loff_t first_page, last_page, page_len;
-        loff_t first_page, last_page, first_page_offset, last_page_offset;
+        loff_t first_page_offset, last_page_offset;
        int ret, credits, blocks_released, err = 0;
+        /* No need to punch hole beyond i_size */
+        if (offset >= inode->i_size)
+                return 0;
+        /*
+         * If the hole extends beyond i_size, set the hole
+         * to end after the page that contains i_size
+         */
+        if (offset + length > inode->i_size) {
+                length = inode->i_size +
+                   PAGE_CACHE_SIZE - (inode->i_size & (PAGE_CACHE_SIZE - 1)) -
+                   offset;
+        }
        first_block = (offset + sb->s_blocksize - 1) >>
                EXT4_BLOCK_SIZE_BITS(sb);
        last_block = (offset + length) >> EXT4_BLOCK_SIZE_BITS(sb);
-        first_block_offset = first_block << EXT4_BLOCK_SIZE_BITS(sb);
-        last_block_offset = last_block << EXT4_BLOCK_SIZE_BITS(sb);
        first_page = (offset + PAGE_CACHE_SIZE - 1) >> PAGE_CACHE_SHIFT;
        last_page = (offset + length) >> PAGE_CACHE_SHIFT;
@@ -4185,11 +4744,10 @@ int ext4_ext_punch_hole(struct file *file, loff_t offset, loff_t length)
         */
        if (mapping->nrpages && mapping_tagged(mapping, PAGECACHE_TAG_DIRTY)) {
                err = filemap_write_and_wait_range(mapping,
-                        first_page_offset == 0 ? 0 : first_page_offset-1,
+                        offset, offset + length - 1);
-                        last_page_offset);
-                        if (err)
+                if (err)
-                                return err;
+                        return err;
        }
        /* Now release the pages */
@@ -4211,24 +4769,64 @@ int ext4_ext_punch_hole(struct file *file, loff_t offset, loff_t length)
                goto out;
        /*
-         * Now we need to zero out the un block aligned data.
+         * Now we need to zero out the non-page-aligned data in the
-         * If the file is smaller than a block, just
+         * pages at the start and tail of the hole, and unmap the buffer
-         * zero out the middle
+         * heads for the block aligned regions of the page that were
+         * completely zeroed.
         */
-        if (first_block > last_block)
+        if (first_page > last_page) {
-                ext4_block_zero_page_range(handle, mapping, offset, length);
+                /*
-        else {
+                 * If the file space being truncated is contained within a page
-                /* zero out the head of the hole before the first block */
+                 * just zero out and unmap the middle of that page
-                block_len  = first_block_offset - offset;
+                 */
-                if (block_len > 0)
+                err = ext4_discard_partial_page_buffers(handle,
-                        ext4_block_zero_page_range(handle, mapping,
+                        mapping, offset, length, 0);
-                                                   offset, block_len);
+                if (err)
-                /* zero out the tail of the hole after the last block */
+                        goto out;
-                block_len = offset + length - last_block_offset;
+        } else {
-                if (block_len > 0) {
+                /*
-                        ext4_block_zero_page_range(handle, mapping,
+                 * zero out and unmap the partial page that contains
-                                        last_block_offset, block_len);
+                 * the start of the hole
+                 */
+                page_len  = first_page_offset - offset;
+                if (page_len > 0) {
+                        err = ext4_discard_partial_page_buffers(handle, mapping,
+                                                   offset, page_len, 0);
+                        if (err)
+                                goto out;
+                }
+                /*
+                 * zero out and unmap the partial page that contains
+                 * the end of the hole
+                 */
+                page_len = offset + length - last_page_offset;
+                if (page_len > 0) {
+                        err = ext4_discard_partial_page_buffers(handle, mapping,
+                                        last_page_offset, page_len, 0);
+                        if (err)
+                                goto out;
+                }
+        }
+        /*
+         * If i_size is contained in the last page, we need to
+         * unmap and zero the partial page after i_size
+         */
+        if (inode->i_size >> PAGE_CACHE_SHIFT == last_page &&
+           inode->i_size % PAGE_CACHE_SIZE != 0) {
+                page_len = PAGE_CACHE_SIZE -
+                        (inode->i_size & (PAGE_CACHE_SIZE - 1));
+                if (page_len > 0) {
+                        err = ext4_discard_partial_page_buffers(handle,
+                          mapping, inode->i_size, page_len, 0);
+                        if (err)
+                                goto out;
                }
        }
diff --git a/fs/ext4/file.c b/fs/ext4/file.c
index b9548f477bb8..cb70f1812a70 100644
--- a/fs/ext4/file.c
+++ b/fs/ext4/file.c
@@ -181,8 +181,8 @@ static int ext4_file_open(struct inode * inode, struct file * filp)
                path.dentry = mnt->mnt_root;
                cp = d_path(&path, buf, sizeof(buf));
                if (!IS_ERR(cp)) {
-                        memcpy(sbi->s_es->s_last_mounted, cp,
+                        strlcpy(sbi->s_es->s_last_mounted, cp,
-                               sizeof(sbi->s_es->s_last_mounted));
+                                sizeof(sbi->s_es->s_last_mounted));
                        ext4_mark_super_dirty(sb);
                }
        }
diff --git a/fs/ext4/fsync.c b/fs/ext4/fsync.c
index 036f78f7a1ef..00a2cb753efd 100644
--- a/fs/ext4/fsync.c
+++ b/fs/ext4/fsync.c
@@ -75,7 +75,7 @@ static void dump_completed_IO(struct inode * inode)
 * to written.
 * The function return the number of pending IOs on success.
 */
-extern int ext4_flush_completed_IO(struct inode *inode)
+int ext4_flush_completed_IO(struct inode *inode)
 {
        ext4_io_end_t *io;
        struct ext4_inode_info *ei = EXT4_I(inode);
@@ -83,14 +83,12 @@ extern int ext4_flush_completed_IO(struct inode *inode)
        int ret = 0;
        int ret2 = 0;
-        if (list_empty(&ei->i_completed_io_list))
-                return ret;
        dump_completed_IO(inode);
        spin_lock_irqsave(&ei->i_completed_io_lock, flags);
        while (!list_empty(&ei->i_completed_io_list)){
                io = list_entry(ei->i_completed_io_list.next,
                                ext4_io_end_t, list);
+                list_del_init(&io->list);
                /*
                 * Calling ext4_end_io_nolock() to convert completed
                 * IO to written.
@@ -107,11 +105,9 @@ extern int ext4_flush_completed_IO(struct inode *inode)
                 */
                spin_unlock_irqrestore(&ei->i_completed_io_lock, flags);
                ret = ext4_end_io_nolock(io);
-                spin_lock_irqsave(&ei->i_completed_io_lock, flags);
                if (ret < 0)
                        ret2 = ret;
-                else
+                spin_lock_irqsave(&ei->i_completed_io_lock, flags);
-                        list_del_init(&io->list);
        }
        spin_unlock_irqrestore(&ei->i_completed_io_lock, flags);
        return (ret2 < 0) ? ret2 : 0;
diff --git a/fs/ext4/ialloc.c b/fs/ext4/ialloc.c
index 9c63f273b550..00beb4f9cc4f 100644
--- a/fs/ext4/ialloc.c
+++ b/fs/ext4/ialloc.c
@@ -78,7 +78,7 @@ static unsigned ext4_init_inode_bitmap(struct super_block *sb,
         * allocation, essentially implementing a per-group read-only flag. */
        if (!ext4_group_desc_csum_verify(sbi, block_group, gdp)) {
                ext4_error(sb, "Checksum bad for group %u", block_group);
-                ext4_free_blks_set(sb, gdp, 0);
+                ext4_free_group_clusters_set(sb, gdp, 0);
                ext4_free_inodes_set(sb, gdp, 0);
                ext4_itable_unused_set(sb, gdp, 0);
                memset(bh->b_data, 0xff, sb->s_blocksize);
@@ -293,121 +293,9 @@ error_return:
        ext4_std_error(sb, fatal);
 }
-/*
- * There are two policies for allocating an inode.  If the new inode is
- * a directory, then a forward search is made for a block group with both
- * free space and a low directory-to-inode ratio; if that fails, then of
- * the groups with above-average free space, that group with the fewest
- * directories already is chosen.
- *
- * For other inodes, search forward from the parent directory\'s block
- * group to find a free inode.
- */
-static int find_group_dir(struct super_block *sb, struct inode *parent,
-                                ext4_group_t *best_group)
-{
-        ext4_group_t ngroups = ext4_get_groups_count(sb);
-        unsigned int freei, avefreei;
-        struct ext4_group_desc *desc, *best_desc = NULL;
-        ext4_group_t group;
-        int ret = -1;
-        freei = percpu_counter_read_positive(&EXT4_SB(sb)->s_freeinodes_counter);
-        avefreei = freei / ngroups;
-        for (group = 0; group < ngroups; group++) {
-                desc = ext4_get_group_desc(sb, group, NULL);
-                if (!desc || !ext4_free_inodes_count(sb, desc))
-                        continue;
-                if (ext4_free_inodes_count(sb, desc) < avefreei)
-                        continue;
-                if (!best_desc ||
-                    (ext4_free_blks_count(sb, desc) >
-                     ext4_free_blks_count(sb, best_desc))) {
-                        *best_group = group;
-                        best_desc = desc;
-                        ret = 0;
-                }
-        }
-        return ret;
-}
-#define free_block_ratio 10
-static int find_group_flex(struct super_block *sb, struct inode *parent,
-                           ext4_group_t *best_group)
-{
-        struct ext4_sb_info *sbi = EXT4_SB(sb);
-        struct ext4_group_desc *desc;
-        struct flex_groups *flex_group = sbi->s_flex_groups;
-        ext4_group_t parent_group = EXT4_I(parent)->i_block_group;
-        ext4_group_t parent_fbg_group = ext4_flex_group(sbi, parent_group);
-        ext4_group_t ngroups = ext4_get_groups_count(sb);
-        int flex_size = ext4_flex_bg_size(sbi);
-        ext4_group_t best_flex = parent_fbg_group;
-        int blocks_per_flex = sbi->s_blocks_per_group * flex_size;
-        int flexbg_free_blocks;
-        int flex_freeb_ratio;
-        ext4_group_t n_fbg_groups;
-        ext4_group_t i;
-        n_fbg_groups = (ngroups + flex_size - 1) >>
-                sbi->s_log_groups_per_flex;
-find_close_to_parent:
-        flexbg_free_blocks = atomic_read(&flex_group[best_flex].free_blocks);
-        flex_freeb_ratio = flexbg_free_blocks * 100 / blocks_per_flex;
-        if (atomic_read(&flex_group[best_flex].free_inodes) &&
-            flex_freeb_ratio > free_block_ratio)
-                goto found_flexbg;
-        if (best_flex && best_flex == parent_fbg_group) {
-                best_flex--;
-                goto find_close_to_parent;
-        }
-        for (i = 0; i < n_fbg_groups; i++) {
-                if (i == parent_fbg_group || i == parent_fbg_group - 1)
-                        continue;
-                flexbg_free_blocks = atomic_read(&flex_group[i].free_blocks);
-                flex_freeb_ratio = flexbg_free_blocks * 100 / blocks_per_flex;
-                if (flex_freeb_ratio > free_block_ratio &&
-                    (atomic_read(&flex_group[i].free_inodes))) {
-                        best_flex = i;
-                        goto found_flexbg;
-                }
-                if ((atomic_read(&flex_group[best_flex].free_inodes) == 0) ||
-                    ((atomic_read(&flex_group[i].free_blocks) >
-                      atomic_read(&flex_group[best_flex].free_blocks)) &&
-                     atomic_read(&flex_group[i].free_inodes)))
-                        best_flex = i;
-        }
-        if (!atomic_read(&flex_group[best_flex].free_inodes) ||
-            !atomic_read(&flex_group[best_flex].free_blocks))
-                return -1;
-found_flexbg:
-        for (i = best_flex * flex_size; i < ngroups &&
-                     i < (best_flex + 1) * flex_size; i++) {
-                desc = ext4_get_group_desc(sb, i, NULL);
-                if (ext4_free_inodes_count(sb, desc)) {
-                        *best_group = i;
-                        goto out;
-                }
-        }
-        return -1;
-out:
-        return 0;
-}
 struct orlov_stats {
        __u32 free_inodes;
-        __u32 free_blocks;
+        __u32 free_clusters;
        __u32 used_dirs;
 };
@@ -424,7 +312,7 @@ static void get_orlov_stats(struct super_block *sb, ext4_group_t g,
        if (flex_size > 1) {
                stats->free_inodes = atomic_read(&flex_group[g].free_inodes);
-                stats->free_blocks = atomic_read(&flex_group[g].free_blocks);
+                stats->free_clusters = atomic_read(&flex_group[g].free_clusters);
                stats->used_dirs = atomic_read(&flex_group[g].used_dirs);
                return;
        }
@@ -432,11 +320,11 @@ static void get_orlov_stats(struct super_block *sb, ext4_group_t g,
        desc = ext4_get_group_desc(sb, g, NULL);
        if (desc) {
                stats->free_inodes = ext4_free_inodes_count(sb, desc);
-                stats->free_blocks = ext4_free_blks_count(sb, desc);
+                stats->free_clusters = ext4_free_group_clusters(sb, desc);
                stats->used_dirs = ext4_used_dirs_count(sb, desc);
        } else {
                stats->free_inodes = 0;
-                stats->free_blocks = 0;
+                stats->free_clusters = 0;
                stats->used_dirs = 0;
        }
 }
@@ -471,10 +359,10 @@ static int find_group_orlov(struct super_block *sb, struct inode *parent,
        ext4_group_t real_ngroups = ext4_get_groups_count(sb);
        int inodes_per_group = EXT4_INODES_PER_GROUP(sb);
        unsigned int freei, avefreei;
-        ext4_fsblk_t freeb, avefreeb;
+        ext4_fsblk_t freeb, avefreec;
        unsigned int ndirs;
        int max_dirs, min_inodes;
-        ext4_grpblk_t min_blocks;
+        ext4_grpblk_t min_clusters;
        ext4_group_t i, grp, g, ngroups;
        struct ext4_group_desc *desc;
        struct orlov_stats stats;
@@ -490,9 +378,10 @@ static int find_group_orlov(struct super_block *sb, struct inode *parent,
        freei = percpu_counter_read_positive(&sbi->s_freeinodes_counter);
        avefreei = freei / ngroups;
-        freeb = percpu_counter_read_positive(&sbi->s_freeblocks_counter);
+        freeb = EXT4_C2B(sbi,
-        avefreeb = freeb;
+                percpu_counter_read_positive(&sbi->s_freeclusters_counter));
-        do_div(avefreeb, ngroups);
+        avefreec = freeb;
+        do_div(avefreec, ngroups);
        ndirs = percpu_counter_read_positive(&sbi->s_dirs_counter);
        if (S_ISDIR(mode) &&
@@ -518,7 +407,7 @@ static int find_group_orlov(struct super_block *sb, struct inode *parent,
                                continue;
                        if (stats.free_inodes < avefreei)
                                continue;
-                        if (stats.free_blocks < avefreeb)
+                        if (stats.free_clusters < avefreec)
                                continue;
                        grp = g;
                        ret = 0;
@@ -556,7 +445,7 @@ static int find_group_orlov(struct super_block *sb, struct inode *parent,
        min_inodes = avefreei - inodes_per_group*flex_size / 4;
        if (min_inodes < 1)
                min_inodes = 1;
-        min_blocks = avefreeb - EXT4_BLOCKS_PER_GROUP(sb)*flex_size / 4;
+        min_clusters = avefreec - EXT4_CLUSTERS_PER_GROUP(sb)*flex_size / 4;
        /*
         * Start looking in the flex group where we last allocated an
@@ -575,7 +464,7 @@ static int find_group_orlov(struct super_block *sb, struct inode *parent,
                        continue;
                if (stats.free_inodes < min_inodes)
                        continue;
-                if (stats.free_blocks < min_blocks)
+                if (stats.free_clusters < min_clusters)
                        continue;
                goto found_flex_bg;
        }
@@ -659,7 +548,7 @@ static int find_group_other(struct super_block *sb, struct inode *parent,
        *group = parent_group;
        desc = ext4_get_group_desc(sb, *group, NULL);
        if (desc && ext4_free_inodes_count(sb, desc) &&
-                        ext4_free_blks_count(sb, desc))
+            ext4_free_group_clusters(sb, desc))
                return 0;
        /*
@@ -683,7 +572,7 @@ static int find_group_other(struct super_block *sb, struct inode *parent,
                        *group -= ngroups;
                desc = ext4_get_group_desc(sb, *group, NULL);
                if (desc && ext4_free_inodes_count(sb, desc) &&
-                                ext4_free_blks_count(sb, desc))
+                    ext4_free_group_clusters(sb, desc))
                        return 0;
        }
@@ -802,7 +691,7 @@ err_ret:
 * group to find a free inode.
 */
 struct inode *ext4_new_inode(handle_t *handle, struct inode *dir, int mode,
-                             const struct qstr *qstr, __u32 goal)
+                             const struct qstr *qstr, __u32 goal, uid_t *owner)
 {
        struct super_block *sb;
        struct buffer_head *inode_bitmap_bh = NULL;
@@ -816,8 +705,6 @@ struct inode *ext4_new_inode(handle_t *handle, struct inode *dir, int mode,
        int ret2, err = 0;
        struct inode *ret;
        ext4_group_t i;
-        int free = 0;
-        static int once = 1;
        ext4_group_t flex_group;
        /* Cannot create files in a deleted directory */
@@ -843,26 +730,9 @@ struct inode *ext4_new_inode(handle_t *handle, struct inode *dir, int mode,
                goto got_group;
        }
-        if (sbi->s_log_groups_per_flex && test_opt(sb, OLDALLOC)) {
+        if (S_ISDIR(mode))
-                ret2 = find_group_flex(sb, dir, &group);
+                ret2 = find_group_orlov(sb, dir, &group, mode, qstr);
-                if (ret2 == -1) {
+        else
-                        ret2 = find_group_other(sb, dir, &group, mode);
-                        if (ret2 == 0 && once) {
-                                once = 0;
-                                printk(KERN_NOTICE "ext4: find_group_flex "
-                                       "failed, fallback succeeded dir %lu\n",
-                                       dir->i_ino);
-                        }
-                }
-                goto got_group;
-        }
-        if (S_ISDIR(mode)) {
-                if (test_opt(sb, OLDALLOC))
-                        ret2 = find_group_dir(sb, dir, &group);
-                else
-                        ret2 = find_group_orlov(sb, dir, &group, mode, qstr);
-        } else
                ret2 = find_group_other(sb, dir, &group, mode);
 got_group:
@@ -950,26 +820,21 @@ got:
                        goto fail;
                }
-                free = 0;
+                BUFFER_TRACE(block_bitmap_bh, "dirty block bitmap");
-                ext4_lock_group(sb, group);
+                err = ext4_handle_dirty_metadata(handle, NULL, block_bitmap_bh);
+                brelse(block_bitmap_bh);
                /* recheck and clear flag under lock if we still need to */
+                ext4_lock_group(sb, group);
                if (gdp->bg_flags & cpu_to_le16(EXT4_BG_BLOCK_UNINIT)) {
-                        free = ext4_free_blocks_after_init(sb, group, gdp);
                        gdp->bg_flags &= cpu_to_le16(~EXT4_BG_BLOCK_UNINIT);
-                        ext4_free_blks_set(sb, gdp, free);
+                        ext4_free_group_clusters_set(sb, gdp,
+                                ext4_free_clusters_after_init(sb, group, gdp));
                        gdp->bg_checksum = ext4_group_desc_csum(sbi, group,
                                                                gdp);
                }
                ext4_unlock_group(sb, group);
-                /* Don't need to dirty bitmap block if we didn't change it */
-                if (free) {
-                        BUFFER_TRACE(block_bitmap_bh, "dirty block bitmap");
-                        err = ext4_handle_dirty_metadata(handle,
-                                                        NULL, block_bitmap_bh);
-                }
-                brelse(block_bitmap_bh);
                if (err)
                        goto fail;
        }
@@ -987,8 +852,11 @@ got:
                flex_group = ext4_flex_group(sbi, group);
                atomic_dec(&sbi->s_flex_groups[flex_group].free_inodes);
        }
+        if (owner) {
-        if (test_opt(sb, GRPID)) {
+                inode->i_mode = mode;
+                inode->i_uid = owner[0];
+                inode->i_gid = owner[1];
+        } else if (test_opt(sb, GRPID)) {
                inode->i_mode = mode;
                inode->i_uid = current_fsuid();
                inode->i_gid = dir->i_gid;
@@ -1005,11 +873,7 @@ got:
        ei->i_dir_start_lookup = 0;
        ei->i_disksize = 0;
-        /*
+        /* Don't inherit extent flag from directory, amongst others. */
-         * Don't inherit extent flag from directory, amongst others. We set
-         * extent flag on newly created directory and file only if -o extent
-         * mount option is specified
-         */
        ei->i_flags =
                ext4_mask_flags(mode, EXT4_I(dir)->i_flags & EXT4_FL_INHERITED);
        ei->i_file_acl = 0;
@@ -1084,7 +948,7 @@ fail_free_drop:
 fail_drop:
        dquot_drop(inode);
        inode->i_flags |= S_NOQUOTA;
-        inode->i_nlink = 0;
+        clear_nlink(inode);
        unlock_new_inode(inode);
        iput(inode);
        brelse(inode_bitmap_bh);
@@ -1235,7 +1099,7 @@ unsigned long ext4_count_dirs(struct super_block * sb)
 * inode allocation from the current group, so we take alloc_sem lock, to
 * block ext4_claim_inode until we are finished.
 */
-extern int ext4_init_inode_table(struct super_block *sb, ext4_group_t group,
+int ext4_init_inode_table(struct super_block *sb, ext4_group_t group,
                                 int barrier)
 {
        struct ext4_group_info *grp = ext4_get_group_info(sb, group);
diff --git a/fs/ext4/indirect.c b/fs/ext4/indirect.c
index 0962642119c0..3cfc73fbca8e 100644
--- a/fs/ext4/indirect.c
+++ b/fs/ext4/indirect.c
@@ -699,6 +699,13 @@ int ext4_ind_map_blocks(handle_t *handle, struct inode *inode,
        /*
         * Okay, we need to do block allocation.
        */
+        if (EXT4_HAS_RO_COMPAT_FEATURE(inode->i_sb,
+                                       EXT4_FEATURE_RO_COMPAT_BIGALLOC)) {
+                EXT4_ERROR_INODE(inode, "Can't allocate blocks for "
+                                 "non-extent mapped inodes with bigalloc");
+                return -ENOSPC;
+        }
        goal = ext4_find_goal(inode, map->m_lblk, partial);
        /* the number of blocks need to allocate for [d,t]indirect blocks */
@@ -1343,7 +1350,9 @@ void ext4_ind_truncate(struct inode *inode)
        __le32 nr = 0;
        int n = 0;
        ext4_lblk_t last_block, max_block;
+        loff_t page_len;
        unsigned blocksize = inode->i_sb->s_blocksize;
+        int err;
        handle = start_transaction(inode);
        if (IS_ERR(handle))
@@ -1354,9 +1363,16 @@ void ext4_ind_truncate(struct inode *inode)
        max_block = (EXT4_SB(inode->i_sb)->s_bitmap_maxbytes + blocksize-1)
                                        >> EXT4_BLOCK_SIZE_BITS(inode->i_sb);
-        if (inode->i_size & (blocksize - 1))
+        if (inode->i_size % PAGE_CACHE_SIZE != 0) {
-                if (ext4_block_truncate_page(handle, mapping, inode->i_size))
+                page_len = PAGE_CACHE_SIZE -
+                        (inode->i_size & (PAGE_CACHE_SIZE - 1));
+                err = ext4_discard_partial_page_buffers(handle,
+                        mapping, inode->i_size, page_len, 0);
+                if (err)
                        goto out_stop;
+        }
        if (last_block != max_block) {
                n = ext4_block_to_path(inode, last_block, offsets, NULL);
diff --git a/fs/ext4/inode.c b/fs/ext4/inode.c
index 0defe0bfe019..cc5a6da030a1 100644
--- a/fs/ext4/inode.c
+++ b/fs/ext4/inode.c
@@ -42,7 +42,6 @@
 #include "ext4_jbd2.h"
 #include "xattr.h"
 #include "acl.h"
-#include "ext4_extents.h"
 #include "truncate.h"
 #include <trace/events/ext4.h>
@@ -268,7 +267,7 @@ void ext4_da_update_reserve_space(struct inode *inode,
        struct ext4_inode_info *ei = EXT4_I(inode);
        spin_lock(&ei->i_block_reservation_lock);
-        trace_ext4_da_update_reserve_space(inode, used);
+        trace_ext4_da_update_reserve_space(inode, used, quota_claim);
        if (unlikely(used > ei->i_reserved_data_blocks)) {
                ext4_msg(inode->i_sb, KERN_NOTICE, "%s: ino %lu, used %d "
                         "with only %d reserved data blocks\n",
@@ -281,7 +280,7 @@ void ext4_da_update_reserve_space(struct inode *inode,
        /* Update per-inode reservations */
        ei->i_reserved_data_blocks -= used;
        ei->i_reserved_meta_blocks -= ei->i_allocated_meta_blocks;
-        percpu_counter_sub(&sbi->s_dirtyblocks_counter,
+        percpu_counter_sub(&sbi->s_dirtyclusters_counter,
                           used + ei->i_allocated_meta_blocks);
        ei->i_allocated_meta_blocks = 0;
@@ -291,7 +290,7 @@ void ext4_da_update_reserve_space(struct inode *inode,
                 * only when we have written all of the delayed
                 * allocation blocks.
                 */
-                percpu_counter_sub(&sbi->s_dirtyblocks_counter,
+                percpu_counter_sub(&sbi->s_dirtyclusters_counter,
                                   ei->i_reserved_meta_blocks);
                ei->i_reserved_meta_blocks = 0;
                ei->i_da_metadata_calc_len = 0;
@@ -300,14 +299,14 @@ void ext4_da_update_reserve_space(struct inode *inode,
        /* Update quota subsystem for data blocks */
        if (quota_claim)
-                dquot_claim_block(inode, used);
+                dquot_claim_block(inode, EXT4_C2B(sbi, used));
        else {
                /*
                 * We did fallocate with an offset that is already delayed
                 * allocated. So on delayed allocated writeback we should
                 * not re-claim the quota for fallocated blocks.
                 */
-                dquot_release_reservation_block(inode, used);
+                dquot_release_reservation_block(inode, EXT4_C2B(sbi, used));
        }
        /*
@@ -399,6 +398,49 @@ static pgoff_t ext4_num_dirty_pages(struct inode *inode, pgoff_t idx,
 }
 /*
+ * Sets the BH_Da_Mapped bit on the buffer heads corresponding to the given map.
+ */
+static void set_buffers_da_mapped(struct inode *inode,
+                                   struct ext4_map_blocks *map)
+{
+        struct address_space *mapping = inode->i_mapping;
+        struct pagevec pvec;
+        int i, nr_pages;
+        pgoff_t index, end;
+        index = map->m_lblk >> (PAGE_CACHE_SHIFT - inode->i_blkbits);
+        end = (map->m_lblk + map->m_len - 1) >>
+                (PAGE_CACHE_SHIFT - inode->i_blkbits);
+        pagevec_init(&pvec, 0);
+        while (index <= end) {
+                nr_pages = pagevec_lookup(&pvec, mapping, index,
+                                          min(end - index + 1,
+                                              (pgoff_t)PAGEVEC_SIZE));
+                if (nr_pages == 0)
+                        break;
+                for (i = 0; i < nr_pages; i++) {
+                        struct page *page = pvec.pages[i];
+                        struct buffer_head *bh, *head;
+                        if (unlikely(page->mapping != mapping) ||
+                            !PageDirty(page))
+                                break;
+                        if (page_has_buffers(page)) {
+                                bh = head = page_buffers(page);
+                                do {
+                                        set_buffer_da_mapped(bh);
+                                        bh = bh->b_this_page;
+                                } while (bh != head);
+                        }
+                        index++;
+                }
+                pagevec_release(&pvec);
+        }
+}
+/*
 * The ext4_map_blocks() function tries to look up the requested blocks,
 * and returns if the blocks are already mapped.
 *
@@ -416,7 +458,7 @@ static pgoff_t ext4_num_dirty_pages(struct inode *inode, pgoff_t idx,
 * the buffer head is mapped.
 *
 * It returns 0 if plain look up failed (blocks have not been allocated), in
- * that casem, buffer head is unmapped
+ * that case, buffer head is unmapped
 *
 * It returns the error in case of allocation failure.
 */
@@ -435,9 +477,11 @@ int ext4_map_blocks(handle_t *handle, struct inode *inode,
         */
        down_read((&EXT4_I(inode)->i_data_sem));
        if (ext4_test_inode_flag(inode, EXT4_INODE_EXTENTS)) {
-                retval = ext4_ext_map_blocks(handle, inode, map, 0);
+                retval = ext4_ext_map_blocks(handle, inode, map, flags &
+                                             EXT4_GET_BLOCKS_KEEP_SIZE);
        } else {
-                retval = ext4_ind_map_blocks(handle, inode, map, 0);
+                retval = ext4_ind_map_blocks(handle, inode, map, flags &
+                                             EXT4_GET_BLOCKS_KEEP_SIZE);
        }
        up_read((&EXT4_I(inode)->i_data_sem));
@@ -455,7 +499,7 @@ int ext4_map_blocks(handle_t *handle, struct inode *inode,
         * Returns if the blocks have already allocated
         *
         * Note that if blocks have been preallocated
-         * ext4_ext_get_block() returns th create = 0
+         * ext4_ext_get_block() returns the create = 0
         * with buffer head unmapped.
         */
        if (retval > 0 && map->m_flags & EXT4_MAP_MAPPED)
@@ -517,9 +561,17 @@ int ext4_map_blocks(handle_t *handle, struct inode *inode,
                        (flags & EXT4_GET_BLOCKS_DELALLOC_RESERVE))
                        ext4_da_update_reserve_space(inode, retval, 1);
        }
-        if (flags & EXT4_GET_BLOCKS_DELALLOC_RESERVE)
+        if (flags & EXT4_GET_BLOCKS_DELALLOC_RESERVE) {
                ext4_clear_inode_state(inode, EXT4_STATE_DELALLOC_RESERVED);
+                /* If we have successfully mapped the delayed allocated blocks,
+                 * set the BH_Da_Mapped bit on them. Its important to do this
+                 * under the protection of i_data_sem.
+                 */
+                if (retval > 0 && map->m_flags & EXT4_MAP_MAPPED)
+                        set_buffers_da_mapped(inode, map);
+        }
        up_write((&EXT4_I(inode)->i_data_sem));
        if (retval > 0 && map->m_flags & EXT4_MAP_MAPPED) {
                int ret = check_block_validity(inode, map);
@@ -909,7 +961,11 @@ static int ext4_ordered_write_end(struct file *file,
                        ext4_orphan_add(handle, inode);
                if (ret2 < 0)
                        ret = ret2;
+        } else {
+                unlock_page(page);
+                page_cache_release(page);
        }
        ret2 = ext4_journal_stop(handle);
        if (!ret)
                ret = ret2;
@@ -1037,14 +1093,14 @@ static int ext4_journalled_write_end(struct file *file,
 }
 /*
- * Reserve a single block located at lblock
+ * Reserve a single cluster located at lblock
 */
 static int ext4_da_reserve_space(struct inode *inode, ext4_lblk_t lblock)
 {
        int retries = 0;
        struct ext4_sb_info *sbi = EXT4_SB(inode->i_sb);
        struct ext4_inode_info *ei = EXT4_I(inode);
-        unsigned long md_needed;
+        unsigned int md_needed;
        int ret;
        /*
@@ -1054,7 +1110,8 @@ static int ext4_da_reserve_space(struct inode *inode, ext4_lblk_t lblock)
         */
 repeat:
        spin_lock(&ei->i_block_reservation_lock);
-        md_needed = ext4_calc_metadata_amount(inode, lblock);
+        md_needed = EXT4_NUM_B2C(sbi,
+                                 ext4_calc_metadata_amount(inode, lblock));
        trace_ext4_da_reserve_space(inode, md_needed);
        spin_unlock(&ei->i_block_reservation_lock);
@@ -1063,15 +1120,15 @@ repeat:
         * us from metadata over-estimation, though we may go over by
         * a small amount in the end.  Here we just reserve for data.
         */
-        ret = dquot_reserve_block(inode, 1);
+        ret = dquot_reserve_block(inode, EXT4_C2B(sbi, 1));
        if (ret)
                return ret;
        /*
         * We do still charge estimated metadata to the sb though;
         * we cannot afford to run out of free blocks.
         */
-        if (ext4_claim_free_blocks(sbi, md_needed + 1, 0)) {
+        if (ext4_claim_free_clusters(sbi, md_needed + 1, 0)) {
-                dquot_release_reservation_block(inode, 1);
+                dquot_release_reservation_block(inode, EXT4_C2B(sbi, 1));
                if (ext4_should_retry_alloc(inode->i_sb, &retries)) {
                        yield();
                        goto repeat;
@@ -1118,19 +1175,21 @@ static void ext4_da_release_space(struct inode *inode, int to_free)
                 * We can release all of the reserved metadata blocks
                 * only when we have written all of the delayed
                 * allocation blocks.
+                 * Note that in case of bigalloc, i_reserved_meta_blocks,
+                 * i_reserved_data_blocks, etc. refer to number of clusters.
                 */
-                percpu_counter_sub(&sbi->s_dirtyblocks_counter,
+                percpu_counter_sub(&sbi->s_dirtyclusters_counter,
                                   ei->i_reserved_meta_blocks);
                ei->i_reserved_meta_blocks = 0;
                ei->i_da_metadata_calc_len = 0;
        }
        /* update fs dirty data blocks counter */
-        percpu_counter_sub(&sbi->s_dirtyblocks_counter, to_free);
+        percpu_counter_sub(&sbi->s_dirtyclusters_counter, to_free);
        spin_unlock(&EXT4_I(inode)->i_block_reservation_lock);
-        dquot_release_reservation_block(inode, to_free);
+        dquot_release_reservation_block(inode, EXT4_C2B(sbi, to_free));
 }
 static void ext4_da_page_release_reservation(struct page *page,
@@ -1139,6 +1198,9 @@ static void ext4_da_page_release_reservation(struct page *page,
        int to_release = 0;
        struct buffer_head *head, *bh;
        unsigned int curr_off = 0;
+        struct inode *inode = page->mapping->host;
+        struct ext4_sb_info *sbi = EXT4_SB(inode->i_sb);
+        int num_clusters;
        head = page_buffers(page);
        bh = head;
@@ -1148,10 +1210,24 @@ static void ext4_da_page_release_reservation(struct page *page,
                if ((offset <= curr_off) && (buffer_delay(bh))) {
                        to_release++;
                        clear_buffer_delay(bh);
+                        clear_buffer_da_mapped(bh);
                }
                curr_off = next_off;
        } while ((bh = bh->b_this_page) != head);
-        ext4_da_release_space(page->mapping->host, to_release);
+        /* If we have released all the blocks belonging to a cluster, then we
+         * need to release the reserved space for that cluster. */
+        num_clusters = EXT4_NUM_B2C(sbi, to_release);
+        while (num_clusters > 0) {
+                ext4_fsblk_t lblk;
+                lblk = (page->index << (PAGE_CACHE_SHIFT - inode->i_blkbits)) +
+                        ((num_clusters - 1) << sbi->s_cluster_bits);
+                if (sbi->s_cluster_ratio == 1 ||
+                    !ext4_find_delalloc_cluster(inode, lblk, 1))
+                        ext4_da_release_space(inode, 1);
+                num_clusters--;
+        }
 }
 /*
@@ -1253,6 +1329,8 @@ static int mpage_da_submit_io(struct mpage_da_data *mpd,
                                                clear_buffer_delay(bh);
                                                bh->b_blocknr = pblock;
                                        }
+                                        if (buffer_da_mapped(bh))
+                                                clear_buffer_da_mapped(bh);
                                        if (buffer_unwritten(bh) ||
                                            buffer_mapped(bh))
                                                BUG_ON(bh->b_blocknr != pblock);
@@ -1346,12 +1424,15 @@ static void ext4_print_free_blocks(struct inode *inode)
 {
        struct ext4_sb_info *sbi = EXT4_SB(inode->i_sb);
        printk(KERN_CRIT "Total free blocks count %lld\n",
-               ext4_count_free_blocks(inode->i_sb));
+               EXT4_C2B(EXT4_SB(inode->i_sb),
+                        ext4_count_free_clusters(inode->i_sb)));
        printk(KERN_CRIT "Free/Dirty block details\n");
        printk(KERN_CRIT "free_blocks=%lld\n",
-               (long long) percpu_counter_sum(&sbi->s_freeblocks_counter));
+               (long long) EXT4_C2B(EXT4_SB(inode->i_sb),
+                percpu_counter_sum(&sbi->s_freeclusters_counter)));
        printk(KERN_CRIT "dirty_blocks=%lld\n",
-               (long long) percpu_counter_sum(&sbi->s_dirtyblocks_counter));
+               (long long) EXT4_C2B(EXT4_SB(inode->i_sb),
+                percpu_counter_sum(&sbi->s_dirtyclusters_counter)));
        printk(KERN_CRIT "Block reservation details\n");
        printk(KERN_CRIT "i_reserved_data_blocks=%u\n",
               EXT4_I(inode)->i_reserved_data_blocks);
@@ -1430,8 +1511,7 @@ static void mpage_da_map_and_submit(struct mpage_da_data *mpd)
                if (err == -EAGAIN)
                        goto submit_io;
-                if (err == -ENOSPC &&
+                if (err == -ENOSPC && ext4_count_free_clusters(sb)) {
-                    ext4_count_free_blocks(sb)) {
                        mpd->retval = err;
                        goto submit_io;
                }
@@ -1471,13 +1551,15 @@ static void mpage_da_map_and_submit(struct mpage_da_data *mpd)
                for (i = 0; i < map.m_len; i++)
                        unmap_underlying_metadata(bdev, map.m_pblk + i);
-        }
-        if (ext4_should_order_data(mpd->inode)) {
+                if (ext4_should_order_data(mpd->inode)) {
-                err = ext4_jbd2_file_inode(handle, mpd->inode);
+                        err = ext4_jbd2_file_inode(handle, mpd->inode);
-                if (err)
+                        if (err) {
-                        /* This only happens if the journal is aborted */
+                                /* Only if the journal is aborted */
-                        return;
+                                mpd->retval = err;
+                                goto submit_io;
+                        }
+                }
        }
        /*
@@ -1584,6 +1666,66 @@ static int ext4_bh_delay_or_unwritten(handle_t *handle, struct buffer_head *bh)
 }
 /*
+ * This function is grabs code from the very beginning of
+ * ext4_map_blocks, but assumes that the caller is from delayed write
+ * time. This function looks up the requested blocks and sets the
+ * buffer delay bit under the protection of i_data_sem.
+ */
+static int ext4_da_map_blocks(struct inode *inode, sector_t iblock,
+                              struct ext4_map_blocks *map,
+                              struct buffer_head *bh)
+{
+        int retval;
+        sector_t invalid_block = ~((sector_t) 0xffff);
+        if (invalid_block < ext4_blocks_count(EXT4_SB(inode->i_sb)->s_es))
+                invalid_block = ~0;
+        map->m_flags = 0;
+        ext_debug("ext4_da_map_blocks(): inode %lu, max_blocks %u,"
+                  "logical block %lu\n", inode->i_ino, map->m_len,
+                  (unsigned long) map->m_lblk);
+        /*
+         * Try to see if we can get the block without requesting a new
+         * file system block.
+         */
+        down_read((&EXT4_I(inode)->i_data_sem));
+        if (ext4_test_inode_flag(inode, EXT4_INODE_EXTENTS))
+                retval = ext4_ext_map_blocks(NULL, inode, map, 0);
+        else
+                retval = ext4_ind_map_blocks(NULL, inode, map, 0);
+        if (retval == 0) {
+                /*
+                 * XXX: __block_prepare_write() unmaps passed block,
+                 * is it OK?
+                 */
+                /* If the block was allocated from previously allocated cluster,
+                 * then we dont need to reserve it again. */
+                if (!(map->m_flags & EXT4_MAP_FROM_CLUSTER)) {
+                        retval = ext4_da_reserve_space(inode, iblock);
+                        if (retval)
+                                /* not enough space to reserve */
+                                goto out_unlock;
+                }
+                /* Clear EXT4_MAP_FROM_CLUSTER flag since its purpose is served
+                 * and it should not appear on the bh->b_state.
+                 */
+                map->m_flags &= ~EXT4_MAP_FROM_CLUSTER;
+                map_bh(bh, inode->i_sb, invalid_block);
+                set_buffer_new(bh);
+                set_buffer_delay(bh);
+        }
+out_unlock:
+        up_read((&EXT4_I(inode)->i_data_sem));
+        return retval;
+}
+/*
 * This is a special get_blocks_t callback which is used by
 * ext4_da_write_begin().  It will either return mapped block or
 * reserve space for a single block.
@@ -1600,10 +1742,6 @@ static int ext4_da_get_block_prep(struct inode *inode, sector_t iblock,
 {
        struct ext4_map_blocks map;
        int ret = 0;
-        sector_t invalid_block = ~((sector_t) 0xffff);
-        if (invalid_block < ext4_blocks_count(EXT4_SB(inode->i_sb)->s_es))
-                invalid_block = ~0;
        BUG_ON(create == 0);
        BUG_ON(bh->b_size != inode->i_sb->s_blocksize);
@@ -1616,25 +1754,9 @@ static int ext4_da_get_block_prep(struct inode *inode, sector_t iblock,
         * preallocated blocks are unmapped but should treated
         * the same as allocated blocks.
         */
-        ret = ext4_map_blocks(NULL, inode, &map, 0);
+        ret = ext4_da_map_blocks(inode, iblock, &map, bh);
-        if (ret < 0)
+        if (ret <= 0)
                return ret;
-        if (ret == 0) {
-                if (buffer_delay(bh))
-                        return 0; /* Not sure this could or should happen */
-                /*
-                 * XXX: __block_write_begin() unmaps passed block, is it OK?
-                 */
-                ret = ext4_da_reserve_space(inode, iblock);
-                if (ret)
-                        /* not enough space to reserve */
-                        return ret;
-                map_bh(bh, inode->i_sb, invalid_block);
-                set_buffer_new(bh);
-                set_buffer_delay(bh);
-                return 0;
-        }
        map_bh(bh, inode->i_sb, map.m_pblk);
        bh->b_state = (bh->b_state & ~EXT4_MAP_FLAGS) | map.m_flags;
@@ -2050,6 +2172,7 @@ static int ext4_da_writepages(struct address_space *mapping,
        struct ext4_sb_info *sbi = EXT4_SB(mapping->host->i_sb);
        pgoff_t done_index = 0;
        pgoff_t end;
+        struct blk_plug plug;
        trace_ext4_da_writepages(inode, wbc);
@@ -2128,6 +2251,7 @@ retry:
        if (wbc->sync_mode == WB_SYNC_ALL || wbc->tagged_writepages)
                tag_pages_for_writeback(mapping, index, end);
+        blk_start_plug(&plug);
        while (!ret && wbc->nr_to_write > 0) {
                /*
@@ -2178,11 +2302,12 @@ retry:
                        ret = 0;
                } else if (ret == MPAGE_DA_EXTENT_TAIL) {
                        /*
-                         * got one extent now try with
+                         * Got one extent now try with rest of the pages.
-                         * rest of the pages
+                         * If mpd.retval is set -EIO, journal is aborted.
+                         * So we don't need to write any more.
                         */
                        pages_written += mpd.pages_written;
-                        ret = 0;
+                        ret = mpd.retval;
                        io_done = 1;
                } else if (wbc->nr_to_write)
                        /*
@@ -2192,6 +2317,7 @@ retry:
                         */
                        break;
        }
+        blk_finish_plug(&plug);
        if (!io_done && !cycled) {
                cycled = 1;
                index = 0;
@@ -2230,10 +2356,11 @@ static int ext4_nonda_switch(struct super_block *sb)
         * Delalloc need an accurate free block accounting. So switch
         * to non delalloc when we are near to error range.
         */
-        free_blocks  = percpu_counter_read_positive(&sbi->s_freeblocks_counter);
+        free_blocks  = EXT4_C2B(sbi,
-        dirty_blocks = percpu_counter_read_positive(&sbi->s_dirtyblocks_counter);
+                percpu_counter_read_positive(&sbi->s_freeclusters_counter));
+        dirty_blocks = percpu_counter_read_positive(&sbi->s_dirtyclusters_counter);
        if (2 * free_blocks < 3 * dirty_blocks ||
-                free_blocks < (dirty_blocks + EXT4_FREEBLOCKS_WATERMARK)) {
+                free_blocks < (dirty_blocks + EXT4_FREECLUSTERS_WATERMARK)) {
                /*
                 * free block count is less than 150% of dirty blocks
                 * or free blocks is less than watermark
@@ -2259,6 +2386,7 @@ static int ext4_da_write_begin(struct file *file, struct address_space *mapping,
        pgoff_t index;
        struct inode *inode = mapping->host;
        handle_t *handle;
+        loff_t page_len;
        index = pos >> PAGE_CACHE_SHIFT;
@@ -2305,6 +2433,13 @@ retry:
                 */
                if (pos + len > inode->i_size)
                        ext4_truncate_failed_write(inode);
+        } else {
+                page_len = pos & (PAGE_CACHE_SIZE - 1);
+                if (page_len > 0) {
+                        ret = ext4_discard_partial_page_buffers_no_lock(handle,
+                                inode, page, pos - page_len, page_len,
+                                EXT4_DISCARD_PARTIAL_PG_ZERO_UNMAPPED);
+                }
        }
        if (ret == -ENOSPC && ext4_should_retry_alloc(inode->i_sb, &retries))
@@ -2347,6 +2482,7 @@ static int ext4_da_write_end(struct file *file,
        loff_t new_i_size;
        unsigned long start, end;
        int write_mode = (int)(unsigned long)fsdata;
+        loff_t page_len;
        if (write_mode == FALL_BACK_TO_NONDELALLOC) {
                if (ext4_should_order_data(inode)) {
@@ -2395,6 +2531,16 @@ static int ext4_da_write_end(struct file *file,
        }
        ret2 = generic_write_end(file, mapping, pos, len, copied,
                                                        page, fsdata);
+        page_len = PAGE_CACHE_SIZE -
+                        ((pos + copied - 1) & (PAGE_CACHE_SIZE - 1));
+        if (page_len > 0) {
+                ret = ext4_discard_partial_page_buffers_no_lock(handle,
+                        inode, page, pos + copied - 1, page_len,
+                        EXT4_DISCARD_PARTIAL_PG_ZERO_UNMAPPED);
+        }
        copied = ret2;
        if (ret2 < 0)
                ret = ret2;
@@ -2689,10 +2835,7 @@ static void ext4_end_io_buffer_write(struct buffer_head *bh, int uptodate)
         * but being more careful is always safe for the future change.
         */
        inode = io_end->inode;
-        if (!(io_end->flag & EXT4_IO_END_UNWRITTEN)) {
+        ext4_set_io_unwritten_flag(inode, io_end);
-                io_end->flag |= EXT4_IO_END_UNWRITTEN;
-                atomic_inc(&EXT4_I(inode)->i_aiodio_unwritten);
-        }
        /* Add the io_end to per-inode completed io list*/
        spin_lock_irqsave(&EXT4_I(inode)->i_completed_io_lock, flags);
@@ -2858,6 +3001,12 @@ static ssize_t ext4_direct_IO(int rw, struct kiocb *iocb,
        struct inode *inode = file->f_mapping->host;
        ssize_t ret;
+        /*
+         * If we are doing data journalling we don't support O_DIRECT
+         */
+        if (ext4_should_journal_data(inode))
+                return 0;
        trace_ext4_direct_IO_enter(inode, offset, iov_length(iov, nr_segs), rw);
        if (ext4_test_inode_flag(inode, EXT4_INODE_EXTENTS))
                ret = ext4_ext_direct_IO(rw, iocb, iov, offset, nr_segs);
@@ -2927,6 +3076,7 @@ static const struct address_space_operations ext4_journalled_aops = {
        .bmap                   = ext4_bmap,
        .invalidatepage         = ext4_invalidatepage,
        .releasepage            = ext4_releasepage,
+        .direct_IO              = ext4_direct_IO,
        .is_partially_uptodate  = block_is_partially_uptodate,
        .error_remove_page      = generic_error_remove_page,
 };
@@ -2963,6 +3113,227 @@ void ext4_set_aops(struct inode *inode)
                inode->i_mapping->a_ops = &ext4_journalled_aops;
 }
+/*
+ * ext4_discard_partial_page_buffers()
+ * Wrapper function for ext4_discard_partial_page_buffers_no_lock.
+ * This function finds and locks the page containing the offset
+ * "from" and passes it to ext4_discard_partial_page_buffers_no_lock.
+ * Calling functions that already have the page locked should call
+ * ext4_discard_partial_page_buffers_no_lock directly.
+ */
+int ext4_discard_partial_page_buffers(handle_t *handle,
+                struct address_space *mapping, loff_t from,
+                loff_t length, int flags)
+{
+        struct inode *inode = mapping->host;
+        struct page *page;
+        int err = 0;
+        page = find_or_create_page(mapping, from >> PAGE_CACHE_SHIFT,
+                                   mapping_gfp_mask(mapping) & ~__GFP_FS);
+        if (!page)
+                return -ENOMEM;
+        err = ext4_discard_partial_page_buffers_no_lock(handle, inode, page,
+                from, length, flags);
+        unlock_page(page);
+        page_cache_release(page);
+        return err;
+}
+/*
+ * ext4_discard_partial_page_buffers_no_lock()
+ * Zeros a page range of length 'length' starting from offset 'from'.
+ * Buffer heads that correspond to the block aligned regions of the
+ * zeroed range will be unmapped.  Unblock aligned regions
+ * will have the corresponding buffer head mapped if needed so that
+ * that region of the page can be updated with the partial zero out.
+ *
+ * This function assumes that the page has already been  locked.  The
+ * The range to be discarded must be contained with in the given page.
+ * If the specified range exceeds the end of the page it will be shortened
+ * to the end of the page that corresponds to 'from'.  This function is
+ * appropriate for updating a page and it buffer heads to be unmapped and
+ * zeroed for blocks that have been either released, or are going to be
+ * released.
+ *
+ * handle: The journal handle
+ * inode:  The files inode
+ * page:   A locked page that contains the offset "from"
+ * from:   The starting byte offset (from the begining of the file)
+ *         to begin discarding
+ * len:    The length of bytes to discard
+ * flags:  Optional flags that may be used:
+ *
+ *         EXT4_DISCARD_PARTIAL_PG_ZERO_UNMAPPED
+ *         Only zero the regions of the page whose buffer heads
+ *         have already been unmapped.  This flag is appropriate
+ *         for updateing the contents of a page whose blocks may
+ *         have already been released, and we only want to zero
+ *         out the regions that correspond to those released blocks.
+ *
+ * Returns zero on sucess or negative on failure.
+ */
+int ext4_discard_partial_page_buffers_no_lock(handle_t *handle,
+                struct inode *inode, struct page *page, loff_t from,
+                loff_t length, int flags)
+{
+        ext4_fsblk_t index = from >> PAGE_CACHE_SHIFT;
+        unsigned int offset = from & (PAGE_CACHE_SIZE-1);
+        unsigned int blocksize, max, pos;
+        ext4_lblk_t iblock;
+        struct buffer_head *bh;
+        int err = 0;
+        blocksize = inode->i_sb->s_blocksize;
+        max = PAGE_CACHE_SIZE - offset;
+        if (index != page->index)
+                return -EINVAL;
+        /*
+         * correct length if it does not fall between
+         * 'from' and the end of the page
+         */
+        if (length > max || length < 0)
+                length = max;
+        iblock = index << (PAGE_CACHE_SHIFT - inode->i_sb->s_blocksize_bits);
+        if (!page_has_buffers(page)) {
+                /*
+                 * If the range to be discarded covers a partial block
+                 * we need to get the page buffers.  This is because
+                 * partial blocks cannot be released and the page needs
+                 * to be updated with the contents of the block before
+                 * we write the zeros on top of it.
+                 */
+                if ((from & (blocksize - 1)) ||
+                    ((from + length) & (blocksize - 1))) {
+                        create_empty_buffers(page, blocksize, 0);
+                } else {
+                        /*
+                         * If there are no partial blocks,
+                         * there is nothing to update,
+                         * so we can return now
+                         */
+                        return 0;
+                }
+        }
+        /* Find the buffer that contains "offset" */
+        bh = page_buffers(page);
+        pos = blocksize;
+        while (offset >= pos) {
+                bh = bh->b_this_page;
+                iblock++;
+                pos += blocksize;
+        }
+        pos = offset;
+        while (pos < offset + length) {
+                unsigned int end_of_block, range_to_discard;
+                err = 0;
+                /* The length of space left to zero and unmap */
+                range_to_discard = offset + length - pos;
+                /* The length of space until the end of the block */
+                end_of_block = blocksize - (pos & (blocksize-1));
+                /*
+                 * Do not unmap or zero past end of block
+                 * for this buffer head
+                 */
+                if (range_to_discard > end_of_block)
+                        range_to_discard = end_of_block;
+                /*
+                 * Skip this buffer head if we are only zeroing unampped
+                 * regions of the page
+                 */
+                if (flags & EXT4_DISCARD_PARTIAL_PG_ZERO_UNMAPPED &&
+                        buffer_mapped(bh))
+                                goto next;
+                /* If the range is block aligned, unmap */
+                if (range_to_discard == blocksize) {
+                        clear_buffer_dirty(bh);
+                        bh->b_bdev = NULL;
+                        clear_buffer_mapped(bh);
+                        clear_buffer_req(bh);
+                        clear_buffer_new(bh);
+                        clear_buffer_delay(bh);
+                        clear_buffer_unwritten(bh);
+                        clear_buffer_uptodate(bh);
+                        zero_user(page, pos, range_to_discard);
+                        BUFFER_TRACE(bh, "Buffer discarded");
+                        goto next;
+                }
+                /*
+                 * If this block is not completely contained in the range
+                 * to be discarded, then it is not going to be released. Because
+                 * we need to keep this block, we need to make sure this part
+                 * of the page is uptodate before we modify it by writeing
+                 * partial zeros on it.
+                 */
+                if (!buffer_mapped(bh)) {
+                        /*
+                         * Buffer head must be mapped before we can read
+                         * from the block
+                         */
+                        BUFFER_TRACE(bh, "unmapped");
+                        ext4_get_block(inode, iblock, bh, 0);
+                        /* unmapped? It's a hole - nothing to do */
+                        if (!buffer_mapped(bh)) {
+                                BUFFER_TRACE(bh, "still unmapped");
+                                goto next;
+                        }
+                }
+                /* Ok, it's mapped. Make sure it's up-to-date */
+                if (PageUptodate(page))
+                        set_buffer_uptodate(bh);
+                if (!buffer_uptodate(bh)) {
+                        err = -EIO;
+                        ll_rw_block(READ, 1, &bh);
+                        wait_on_buffer(bh);
+                        /* Uhhuh. Read error. Complain and punt.*/
+                        if (!buffer_uptodate(bh))
+                                goto next;
+                }
+                if (ext4_should_journal_data(inode)) {
+                        BUFFER_TRACE(bh, "get write access");
+                        err = ext4_journal_get_write_access(handle, bh);
+                        if (err)
+                                goto next;
+                }
+                zero_user(page, pos, range_to_discard);
+                err = 0;
+                if (ext4_should_journal_data(inode)) {
+                        err = ext4_handle_dirty_metadata(handle, inode, bh);
+                } else
+                        mark_buffer_dirty(bh);
+                BUFFER_TRACE(bh, "Partial buffer zeroed");
+next:
+                bh = bh->b_this_page;
+                iblock++;
+                pos += range_to_discard;
+        }
+        return err;
+}
 /*
 * ext4_block_truncate_page() zeroes out a mapping from file offset `from'
 * up to the end of the block which corresponds to `from'.
@@ -3005,7 +3376,7 @@ int ext4_block_zero_page_range(handle_t *handle,
        page = find_or_create_page(mapping, from >> PAGE_CACHE_SHIFT,
                                   mapping_gfp_mask(mapping) & ~__GFP_FS);
        if (!page)
-                return -EINVAL;
+                return -ENOMEM;
        blocksize = inode->i_sb->s_blocksize;
        max = blocksize - (offset & (blocksize - 1));
@@ -3074,11 +3445,8 @@ int ext4_block_zero_page_range(handle_t *handle,
        err = 0;
        if (ext4_should_journal_data(inode)) {
                err = ext4_handle_dirty_metadata(handle, inode, bh);
-        } else {
+        } else
-                if (ext4_should_order_data(inode) && EXT4_I(inode)->jinode)
-                        err = ext4_jbd2_file_inode(handle, inode);
                mark_buffer_dirty(bh);
-        }
 unlock:
        unlock_page(page);
@@ -3119,6 +3487,11 @@ int ext4_punch_hole(struct file *file, loff_t offset, loff_t length)
                return -ENOTSUPP;
        }
+        if (EXT4_SB(inode->i_sb)->s_cluster_ratio > 1) {
+                /* TODO: Add support for bigalloc file systems */
+                return -ENOTSUPP;
+        }
        return ext4_ext_punch_hole(file, offset, length);
 }
@@ -3418,7 +3791,7 @@ struct inode *ext4_iget(struct super_block *sb, unsigned long ino)
                inode->i_uid |= le16_to_cpu(raw_inode->i_uid_high) << 16;
                inode->i_gid |= le16_to_cpu(raw_inode->i_gid_high) << 16;
        }
-        inode->i_nlink = le16_to_cpu(raw_inode->i_links_count);
+        set_nlink(inode, le16_to_cpu(raw_inode->i_links_count));
        ext4_clear_state_flags(ei);     /* Only relevant on 32-bit archs */
        ei->i_dir_start_lookup = 0;
@@ -4420,6 +4793,7 @@ retry_alloc:
                          PAGE_CACHE_SIZE, NULL, do_journal_get_write_access)) {
                        unlock_page(page);
                        ret = VM_FAULT_SIGBUS;
+                        ext4_journal_stop(handle);
                        goto out;
                }
                ext4_set_inode_state(inode, EXT4_STATE_JDATA);
diff --git a/fs/ext4/ioctl.c b/fs/ext4/ioctl.c
index f18bfe37aff8..a56796814d6a 100644
--- a/fs/ext4/ioctl.c
+++ b/fs/ext4/ioctl.c
@@ -21,6 +21,7 @@
 long ext4_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
 {
        struct inode *inode = filp->f_dentry->d_inode;
+        struct super_block *sb = inode->i_sb;
        struct ext4_inode_info *ei = EXT4_I(inode);
        unsigned int flags;
@@ -173,33 +174,8 @@ setversion_out:
                mnt_drop_write(filp->f_path.mnt);
                return err;
        }
-#ifdef CONFIG_JBD2_DEBUG
-        case EXT4_IOC_WAIT_FOR_READONLY:
-                /*
-                 * This is racy - by the time we're woken up and running,
-                 * the superblock could be released.  And the module could
-                 * have been unloaded.  So sue me.
-                 *
-                 * Returns 1 if it slept, else zero.
-                 */
-                {
-                        struct super_block *sb = inode->i_sb;
-                        DECLARE_WAITQUEUE(wait, current);
-                        int ret = 0;
-                        set_current_state(TASK_INTERRUPTIBLE);
-                        add_wait_queue(&EXT4_SB(sb)->ro_wait_queue, &wait);
-                        if (timer_pending(&EXT4_SB(sb)->turn_ro_timer)) {
-                                schedule();
-                                ret = 1;
-                        }
-                        remove_wait_queue(&EXT4_SB(sb)->ro_wait_queue, &wait);
-                        return ret;
-                }
-#endif
        case EXT4_IOC_GROUP_EXTEND: {
                ext4_fsblk_t n_blocks_count;
-                struct super_block *sb = inode->i_sb;
                int err, err2=0;
                err = ext4_resize_begin(sb);
@@ -209,6 +185,13 @@ setversion_out:
                if (get_user(n_blocks_count, (__u32 __user *)arg))
                        return -EFAULT;
+                if (EXT4_HAS_RO_COMPAT_FEATURE(sb,
+                               EXT4_FEATURE_RO_COMPAT_BIGALLOC)) {
+                        ext4_msg(sb, KERN_ERR,
+                                 "Online resizing not supported with bigalloc");
+                        return -EOPNOTSUPP;
+                }
                err = mnt_want_write(filp->f_path.mnt);
                if (err)
                        return err;
@@ -250,6 +233,13 @@ setversion_out:
                        goto mext_out;
                }
+                if (EXT4_HAS_RO_COMPAT_FEATURE(sb,
+                               EXT4_FEATURE_RO_COMPAT_BIGALLOC)) {
+                        ext4_msg(sb, KERN_ERR,
+                                 "Online defrag not supported with bigalloc");
+                        return -EOPNOTSUPP;
+                }
                err = mnt_want_write(filp->f_path.mnt);
                if (err)
                        goto mext_out;
@@ -270,7 +260,6 @@ mext_out:
        case EXT4_IOC_GROUP_ADD: {
                struct ext4_new_group_data input;
-                struct super_block *sb = inode->i_sb;
                int err, err2=0;
                err = ext4_resize_begin(sb);
@@ -281,6 +270,13 @@ mext_out:
                                sizeof(input)))
                        return -EFAULT;
+                if (EXT4_HAS_RO_COMPAT_FEATURE(sb,
+                               EXT4_FEATURE_RO_COMPAT_BIGALLOC)) {
+                        ext4_msg(sb, KERN_ERR,
+                                 "Online resizing not supported with bigalloc");
+                        return -EOPNOTSUPP;
+                }
                err = mnt_want_write(filp->f_path.mnt);
                if (err)
                        return err;
@@ -337,7 +333,6 @@ mext_out:
        case FITRIM:
        {
-                struct super_block *sb = inode->i_sb;
                struct request_queue *q = bdev_get_queue(sb->s_bdev);
                struct fstrim_range range;
                int ret = 0;
@@ -348,7 +343,14 @@ mext_out:
                if (!blk_queue_discard(q))
                        return -EOPNOTSUPP;
-                if (copy_from_user(&range, (struct fstrim_range *)arg,
+                if (EXT4_HAS_RO_COMPAT_FEATURE(sb,
+                               EXT4_FEATURE_RO_COMPAT_BIGALLOC)) {
+                        ext4_msg(sb, KERN_ERR,
+                                 "FITRIM not supported with bigalloc");
+                        return -EOPNOTSUPP;
+                }
+                if (copy_from_user(&range, (struct fstrim_range __user *)arg,
                    sizeof(range)))
                        return -EFAULT;
@@ -358,7 +360,7 @@ mext_out:
                if (ret < 0)
                        return ret;
-                if (copy_to_user((struct fstrim_range *)arg, &range,
+                if (copy_to_user((struct fstrim_range __user *)arg, &range,
                    sizeof(range)))
                        return -EFAULT;
@@ -396,11 +398,6 @@ long ext4_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
        case EXT4_IOC32_SETVERSION_OLD:
                cmd = EXT4_IOC_SETVERSION_OLD;
                break;
-#ifdef CONFIG_JBD2_DEBUG
-        case EXT4_IOC32_WAIT_FOR_READONLY:
-                cmd = EXT4_IOC_WAIT_FOR_READONLY;
-                break;
-#endif
        case EXT4_IOC32_GETRSVSZ:
                cmd = EXT4_IOC_GETRSVSZ;
                break;
diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c
index 17a5a57c415a..e2d8be8f28bf 100644
--- a/fs/ext4/mballoc.c
+++ b/fs/ext4/mballoc.c
@@ -70,8 +70,8 @@
 *
 * pa_lstart -> the logical start block for this prealloc space
 * pa_pstart -> the physical start block for this prealloc space
- * pa_len    -> length for this prealloc space
+ * pa_len    -> length for this prealloc space (in clusters)
- * pa_free   ->  free space available in this prealloc space
+ * pa_free   ->  free space available in this prealloc space (in clusters)
 *
 * The inode preallocation space is used looking at the _logical_ start
 * block. If only the logical file block falls within the range of prealloc
@@ -126,7 +126,8 @@
 * list. In case of inode preallocation we follow a list of heuristics
 * based on file size. This can be found in ext4_mb_normalize_request. If
 * we are doing a group prealloc we try to normalize the request to
- * sbi->s_mb_group_prealloc. Default value of s_mb_group_prealloc is
+ * sbi->s_mb_group_prealloc.  The default value of s_mb_group_prealloc is
+ * dependent on the cluster size; for non-bigalloc file systems, it is
 * 512 blocks. This can be tuned via
 * /sys/fs/ext4/<partition>/mb_group_prealloc. The value is represented in
 * terms of number of blocks. If we have mounted the file system with -O
@@ -459,7 +460,7 @@ static void mb_free_blocks_double(struct inode *inode, struct ext4_buddy *e4b,
                        ext4_fsblk_t blocknr;
                        blocknr = ext4_group_first_block_no(sb, e4b->bd_group);
-                        blocknr += first + i;
+                        blocknr += EXT4_C2B(EXT4_SB(sb), first + i);
                        ext4_grp_locked_error(sb, e4b->bd_group,
                                              inode ? inode->i_ino : 0,
                                              blocknr,
@@ -580,7 +581,7 @@ static int __mb_check_buddy(struct ext4_buddy *e4b, char *file,
                                continue;
                        }
-                        /* both bits in buddy2 must be 0 */
+                        /* both bits in buddy2 must be 1 */
                        MB_CHECK_ASSERT(mb_test_bit(i << 1, buddy2));
                        MB_CHECK_ASSERT(mb_test_bit((i << 1) + 1, buddy2));
@@ -653,7 +654,7 @@ static void ext4_mb_mark_free_simple(struct super_block *sb,
        ext4_grpblk_t chunk;
        unsigned short border;
-        BUG_ON(len > EXT4_BLOCKS_PER_GROUP(sb));
+        BUG_ON(len > EXT4_CLUSTERS_PER_GROUP(sb));
        border = 2 << sb->s_blocksize_bits;
@@ -705,7 +706,7 @@ void ext4_mb_generate_buddy(struct super_block *sb,
                                void *buddy, void *bitmap, ext4_group_t group)
 {
        struct ext4_group_info *grp = ext4_get_group_info(sb, group);
-        ext4_grpblk_t max = EXT4_BLOCKS_PER_GROUP(sb);
+        ext4_grpblk_t max = EXT4_CLUSTERS_PER_GROUP(sb);
        ext4_grpblk_t i = 0;
        ext4_grpblk_t first;
        ext4_grpblk_t len;
@@ -734,7 +735,7 @@ void ext4_mb_generate_buddy(struct super_block *sb,
        if (free != grp->bb_free) {
                ext4_grp_locked_error(sb, group, 0, 0,
-                                      "%u blocks in bitmap, %u in gd",
+                                      "%u clusters in bitmap, %u in gd",
                                      free, grp->bb_free);
                /*
                 * If we intent to continue, we consider group descritor
@@ -1339,7 +1340,7 @@ static void mb_free_blocks(struct inode *inode, struct ext4_buddy *e4b,
                        ext4_fsblk_t blocknr;
                        blocknr = ext4_group_first_block_no(sb, e4b->bd_group);
-                        blocknr += block;
+                        blocknr += EXT4_C2B(EXT4_SB(sb), block);
                        ext4_grp_locked_error(sb, e4b->bd_group,
                                              inode ? inode->i_ino : 0,
                                              blocknr,
@@ -1390,7 +1391,6 @@ static int mb_find_extent(struct ext4_buddy *e4b, int order, int block,
 {
        int next = block;
        int max;
-        int ord;
        void *buddy;
        assert_spin_locked(ext4_group_lock_ptr(e4b->bd_sb, e4b->bd_group));
@@ -1432,9 +1432,8 @@ static int mb_find_extent(struct ext4_buddy *e4b, int order, int block,
                if (mb_test_bit(next, EXT4_MB_BITMAP(e4b)))
                        break;
-                ord = mb_find_order_for_block(e4b, next);
+                order = mb_find_order_for_block(e4b, next);
-                order = ord;
                block = next >> order;
                ex->fe_len += 1 << order;
        }
@@ -1624,8 +1623,8 @@ static void ext4_mb_measure_extent(struct ext4_allocation_context *ac,
        struct ext4_free_extent *gex = &ac->ac_g_ex;
        BUG_ON(ex->fe_len <= 0);
-        BUG_ON(ex->fe_len > EXT4_BLOCKS_PER_GROUP(ac->ac_sb));
+        BUG_ON(ex->fe_len > EXT4_CLUSTERS_PER_GROUP(ac->ac_sb));
-        BUG_ON(ex->fe_start >= EXT4_BLOCKS_PER_GROUP(ac->ac_sb));
+        BUG_ON(ex->fe_start >= EXT4_CLUSTERS_PER_GROUP(ac->ac_sb));
        BUG_ON(ac->ac_status != AC_STATUS_CONTINUE);
        ac->ac_found++;
@@ -1823,15 +1822,15 @@ void ext4_mb_complex_scan_group(struct ext4_allocation_context *ac,
        while (free && ac->ac_status == AC_STATUS_CONTINUE) {
                i = mb_find_next_zero_bit(bitmap,
-                                                EXT4_BLOCKS_PER_GROUP(sb), i);
+                                                EXT4_CLUSTERS_PER_GROUP(sb), i);
-                if (i >= EXT4_BLOCKS_PER_GROUP(sb)) {
+                if (i >= EXT4_CLUSTERS_PER_GROUP(sb)) {
                        /*
                         * IF we have corrupt bitmap, we won't find any
                         * free blocks even though group info says we
                         * we have free blocks
                         */
                        ext4_grp_locked_error(sb, e4b->bd_group, 0, 0,
-                                        "%d free blocks as per "
+                                        "%d free clusters as per "
                                        "group info. But bitmap says 0",
                                        free);
                        break;
@@ -1841,7 +1840,7 @@ void ext4_mb_complex_scan_group(struct ext4_allocation_context *ac,
                BUG_ON(ex.fe_len <= 0);
                if (free < ex.fe_len) {
                        ext4_grp_locked_error(sb, e4b->bd_group, 0, 0,
-                                        "%d free blocks as per "
+                                        "%d free clusters as per "
                                        "group info. But got %d blocks",
                                        free, ex.fe_len);
                        /*
@@ -1887,7 +1886,7 @@ void ext4_mb_scan_aligned(struct ext4_allocation_context *ac,
        do_div(a, sbi->s_stripe);
        i = (a * sbi->s_stripe) - first_group_block;
-        while (i < EXT4_BLOCKS_PER_GROUP(sb)) {
+        while (i < EXT4_CLUSTERS_PER_GROUP(sb)) {
                if (!mb_test_bit(i, bitmap)) {
                        max = mb_find_extent(e4b, 0, i, sbi->s_stripe, &ex);
                        if (max >= sbi->s_stripe) {
@@ -2252,10 +2251,10 @@ int ext4_mb_add_groupinfo(struct super_block *sb, ext4_group_t group,
         */
        if (desc->bg_flags & cpu_to_le16(EXT4_BG_BLOCK_UNINIT)) {
                meta_group_info[i]->bb_free =
-                        ext4_free_blocks_after_init(sb, group, desc);
+                        ext4_free_clusters_after_init(sb, group, desc);
        } else {
                meta_group_info[i]->bb_free =
-                        ext4_free_blks_count(sb, desc);
+                        ext4_free_group_clusters(sb, desc);
        }
        INIT_LIST_HEAD(&meta_group_info[i]->bb_prealloc_list);
@@ -2473,7 +2472,20 @@ int ext4_mb_init(struct super_block *sb, int needs_recovery)
        sbi->s_mb_stats = MB_DEFAULT_STATS;
        sbi->s_mb_stream_request = MB_DEFAULT_STREAM_THRESHOLD;
        sbi->s_mb_order2_reqs = MB_DEFAULT_ORDER2_REQS;
-        sbi->s_mb_group_prealloc = MB_DEFAULT_GROUP_PREALLOC;
+        /*
+         * The default group preallocation is 512, which for 4k block
+         * sizes translates to 2 megabytes.  However for bigalloc file
+         * systems, this is probably too big (i.e, if the cluster size
+         * is 1 megabyte, then group preallocation size becomes half a
+         * gigabyte!).  As a default, we will keep a two megabyte
+         * group pralloc size for cluster sizes up to 64k, and after
+         * that, we will force a minimum group preallocation size of
+         * 32 clusters.  This translates to 8 megs when the cluster
+         * size is 256k, and 32 megs when the cluster size is 1 meg,
+         * which seems reasonable as a default.
+         */
+        sbi->s_mb_group_prealloc = max(MB_DEFAULT_GROUP_PREALLOC >>
+                                       sbi->s_cluster_bits, 32);
        /*
         * If there is a s_stripe > 1, then we set the s_mb_group_prealloc
         * to the lowest multiple of s_stripe which is bigger than
@@ -2490,7 +2502,7 @@ int ext4_mb_init(struct super_block *sb, int needs_recovery)
        sbi->s_locality_groups = alloc_percpu(struct ext4_locality_group);
        if (sbi->s_locality_groups == NULL) {
                ret = -ENOMEM;
-                goto out;
+                goto out_free_groupinfo_slab;
        }
        for_each_possible_cpu(i) {
                struct ext4_locality_group *lg;
@@ -2503,9 +2515,8 @@ int ext4_mb_init(struct super_block *sb, int needs_recovery)
        /* init file for buddy data */
        ret = ext4_mb_init_backend(sb);
-        if (ret != 0) {
+        if (ret != 0)
-                goto out;
+                goto out_free_locality_groups;
-        }
        if (sbi->s_proc)
                proc_create_data("mb_groups", S_IRUGO, sbi->s_proc,
@@ -2513,11 +2524,19 @@ int ext4_mb_init(struct super_block *sb, int needs_recovery)
        if (sbi->s_journal)
                sbi->s_journal->j_commit_callback = release_blocks_on_commit;
+        return 0;
+out_free_locality_groups:
+        free_percpu(sbi->s_locality_groups);
+        sbi->s_locality_groups = NULL;
+out_free_groupinfo_slab:
+        ext4_groupinfo_destroy_slabs();
 out:
-        if (ret) {
+        kfree(sbi->s_mb_offsets);
-                kfree(sbi->s_mb_offsets);
+        sbi->s_mb_offsets = NULL;
-                kfree(sbi->s_mb_maxs);
+        kfree(sbi->s_mb_maxs);
-        }
+        sbi->s_mb_maxs = NULL;
        return ret;
 }
@@ -2602,11 +2621,13 @@ int ext4_mb_release(struct super_block *sb)
 }
 static inline int ext4_issue_discard(struct super_block *sb,
-                ext4_group_t block_group, ext4_grpblk_t block, int count)
+                ext4_group_t block_group, ext4_grpblk_t cluster, int count)
 {
        ext4_fsblk_t discard_block;
-        discard_block = block + ext4_group_first_block_no(sb, block_group);
+        discard_block = (EXT4_C2B(EXT4_SB(sb), cluster) +
+                         ext4_group_first_block_no(sb, block_group));
+        count = EXT4_C2B(EXT4_SB(sb), count);
        trace_ext4_discard_blocks(sb,
                        (unsigned long long) discard_block, count);
        return sb_issue_discard(sb, discard_block, count, GFP_NOFS, 0);
@@ -2633,7 +2654,7 @@ static void release_blocks_on_commit(journal_t *journal, transaction_t *txn)
                if (test_opt(sb, DISCARD))
                        ext4_issue_discard(sb, entry->group,
-                                           entry->start_blk, entry->count);
+                                           entry->start_cluster, entry->count);
                err = ext4_mb_load_buddy(sb, entry->group, &e4b);
                /* we expect to find existing buddy because it's pinned */
@@ -2646,7 +2667,7 @@ static void release_blocks_on_commit(journal_t *journal, transaction_t *txn)
                ext4_lock_group(sb, entry->group);
                /* Take it out of per group rb tree */
                rb_erase(&entry->node, &(db->bb_free_root));
-                mb_free_blocks(NULL, &e4b, entry->start_blk, entry->count);
+                mb_free_blocks(NULL, &e4b, entry->start_cluster, entry->count);
                /*
                 * Clear the trimmed flag for the group so that the next
@@ -2752,7 +2773,7 @@ void ext4_exit_mballoc(void)
 */
 static noinline_for_stack int
 ext4_mb_mark_diskspace_used(struct ext4_allocation_context *ac,
-                                handle_t *handle, unsigned int reserv_blks)
+                                handle_t *handle, unsigned int reserv_clstrs)
 {
        struct buffer_head *bitmap_bh = NULL;
        struct ext4_group_desc *gdp;
@@ -2783,7 +2804,7 @@ ext4_mb_mark_diskspace_used(struct ext4_allocation_context *ac,
                goto out_err;
        ext4_debug("using block group %u(%d)\n", ac->ac_b_ex.fe_group,
-                        ext4_free_blks_count(sb, gdp));
+                        ext4_free_group_clusters(sb, gdp));
        err = ext4_journal_get_write_access(handle, gdp_bh);
        if (err)
@@ -2791,7 +2812,7 @@ ext4_mb_mark_diskspace_used(struct ext4_allocation_context *ac,
        block = ext4_grp_offs_to_block(sb, &ac->ac_b_ex);
-        len = ac->ac_b_ex.fe_len;
+        len = EXT4_C2B(sbi, ac->ac_b_ex.fe_len);
        if (!ext4_data_block_valid(sbi, block, len)) {
                ext4_error(sb, "Allocating blocks %llu-%llu which overlap "
                           "fs metadata\n", block, block+len);
@@ -2823,28 +2844,29 @@ ext4_mb_mark_diskspace_used(struct ext4_allocation_context *ac,
                      ac->ac_b_ex.fe_len);
        if (gdp->bg_flags & cpu_to_le16(EXT4_BG_BLOCK_UNINIT)) {
                gdp->bg_flags &= cpu_to_le16(~EXT4_BG_BLOCK_UNINIT);
-                ext4_free_blks_set(sb, gdp,
+                ext4_free_group_clusters_set(sb, gdp,
-                                        ext4_free_blocks_after_init(sb,
+                                             ext4_free_clusters_after_init(sb,
-                                        ac->ac_b_ex.fe_group, gdp));
+                                                ac->ac_b_ex.fe_group, gdp));
        }
-        len = ext4_free_blks_count(sb, gdp) - ac->ac_b_ex.fe_len;
+        len = ext4_free_group_clusters(sb, gdp) - ac->ac_b_ex.fe_len;
-        ext4_free_blks_set(sb, gdp, len);
+        ext4_free_group_clusters_set(sb, gdp, len);
        gdp->bg_checksum = ext4_group_desc_csum(sbi, ac->ac_b_ex.fe_group, gdp);
        ext4_unlock_group(sb, ac->ac_b_ex.fe_group);
-        percpu_counter_sub(&sbi->s_freeblocks_counter, ac->ac_b_ex.fe_len);
+        percpu_counter_sub(&sbi->s_freeclusters_counter, ac->ac_b_ex.fe_len);
        /*
         * Now reduce the dirty block count also. Should not go negative
         */
        if (!(ac->ac_flags & EXT4_MB_DELALLOC_RESERVED))
                /* release all the reserved blocks if non delalloc */
-                percpu_counter_sub(&sbi->s_dirtyblocks_counter, reserv_blks);
+                percpu_counter_sub(&sbi->s_dirtyclusters_counter,
+                                   reserv_clstrs);
        if (sbi->s_log_groups_per_flex) {
                ext4_group_t flex_group = ext4_flex_group(sbi,
                                                          ac->ac_b_ex.fe_group);
                atomic_sub(ac->ac_b_ex.fe_len,
-                           &sbi->s_flex_groups[flex_group].free_blocks);
+                           &sbi->s_flex_groups[flex_group].free_clusters);
        }
        err = ext4_handle_dirty_metadata(handle, NULL, bitmap_bh);
@@ -2886,6 +2908,7 @@ static noinline_for_stack void
 ext4_mb_normalize_request(struct ext4_allocation_context *ac,
                                struct ext4_allocation_request *ar)
 {
+        struct ext4_sb_info *sbi = EXT4_SB(ac->ac_sb);
        int bsbits, max;
        ext4_lblk_t end;
        loff_t size, orig_size, start_off;
@@ -2916,7 +2939,7 @@ ext4_mb_normalize_request(struct ext4_allocation_context *ac,
        /* first, let's learn actual file size
         * given current request is allocated */
-        size = ac->ac_o_ex.fe_logical + ac->ac_o_ex.fe_len;
+        size = ac->ac_o_ex.fe_logical + EXT4_C2B(sbi, ac->ac_o_ex.fe_len);
        size = size << bsbits;
        if (size < i_size_read(ac->ac_inode))
                size = i_size_read(ac->ac_inode);
@@ -2988,7 +3011,8 @@ ext4_mb_normalize_request(struct ext4_allocation_context *ac,
                        continue;
                }
-                pa_end = pa->pa_lstart + pa->pa_len;
+                pa_end = pa->pa_lstart + EXT4_C2B(EXT4_SB(ac->ac_sb),
+                                                  pa->pa_len);
                /* PA must not overlap original request */
                BUG_ON(!(ac->ac_o_ex.fe_logical >= pa_end ||
@@ -3018,9 +3042,11 @@ ext4_mb_normalize_request(struct ext4_allocation_context *ac,
        rcu_read_lock();
        list_for_each_entry_rcu(pa, &ei->i_prealloc_list, pa_inode_list) {
                ext4_lblk_t pa_end;
                spin_lock(&pa->pa_lock);
                if (pa->pa_deleted == 0) {
-                        pa_end = pa->pa_lstart + pa->pa_len;
+                        pa_end = pa->pa_lstart + EXT4_C2B(EXT4_SB(ac->ac_sb),
+                                                          pa->pa_len);
                        BUG_ON(!(start >= pa_end || end <= pa->pa_lstart));
                }
                spin_unlock(&pa->pa_lock);
@@ -3036,14 +3062,14 @@ ext4_mb_normalize_request(struct ext4_allocation_context *ac,
        }
        BUG_ON(start + size <= ac->ac_o_ex.fe_logical &&
                        start > ac->ac_o_ex.fe_logical);
-        BUG_ON(size <= 0 || size > EXT4_BLOCKS_PER_GROUP(ac->ac_sb));
+        BUG_ON(size <= 0 || size > EXT4_CLUSTERS_PER_GROUP(ac->ac_sb));
        /* now prepare goal request */
        /* XXX: is it better to align blocks WRT to logical
         * placement or satisfy big request as is */
        ac->ac_g_ex.fe_logical = start;
-        ac->ac_g_ex.fe_len = size;
+        ac->ac_g_ex.fe_len = EXT4_NUM_B2C(sbi, size);
        /* define goal start in order to merge */
        if (ar->pright && (ar->lright == (start + size))) {
@@ -3112,14 +3138,16 @@ static void ext4_discard_allocated_blocks(struct ext4_allocation_context *ac)
 static void ext4_mb_use_inode_pa(struct ext4_allocation_context *ac,
                                struct ext4_prealloc_space *pa)
 {
+        struct ext4_sb_info *sbi = EXT4_SB(ac->ac_sb);
        ext4_fsblk_t start;
        ext4_fsblk_t end;
        int len;
        /* found preallocated blocks, use them */
        start = pa->pa_pstart + (ac->ac_o_ex.fe_logical - pa->pa_lstart);
-        end = min(pa->pa_pstart + pa->pa_len, start + ac->ac_o_ex.fe_len);
+        end = min(pa->pa_pstart + EXT4_C2B(sbi, pa->pa_len),
-        len = end - start;
+                  start + EXT4_C2B(sbi, ac->ac_o_ex.fe_len));
+        len = EXT4_NUM_B2C(sbi, end - start);
        ext4_get_group_no_and_offset(ac->ac_sb, start, &ac->ac_b_ex.fe_group,
                                        &ac->ac_b_ex.fe_start);
        ac->ac_b_ex.fe_len = len;
@@ -3127,7 +3155,7 @@ static void ext4_mb_use_inode_pa(struct ext4_allocation_context *ac,
        ac->ac_pa = pa;
        BUG_ON(start < pa->pa_pstart);
-        BUG_ON(start + len > pa->pa_pstart + pa->pa_len);
+        BUG_ON(end > pa->pa_pstart + EXT4_C2B(sbi, pa->pa_len));
        BUG_ON(pa->pa_free < len);
        pa->pa_free -= len;
@@ -3193,6 +3221,7 @@ ext4_mb_check_group_pa(ext4_fsblk_t goal_block,
 static noinline_for_stack int
 ext4_mb_use_preallocated(struct ext4_allocation_context *ac)
 {
+        struct ext4_sb_info *sbi = EXT4_SB(ac->ac_sb);
        int order, i;
        struct ext4_inode_info *ei = EXT4_I(ac->ac_inode);
        struct ext4_locality_group *lg;
@@ -3210,12 +3239,14 @@ ext4_mb_use_preallocated(struct ext4_allocation_context *ac)
                /* all fields in this condition don't change,
                 * so we can skip locking for them */
                if (ac->ac_o_ex.fe_logical < pa->pa_lstart ||
-                        ac->ac_o_ex.fe_logical >= pa->pa_lstart + pa->pa_len)
+                    ac->ac_o_ex.fe_logical >= (pa->pa_lstart +
+                                               EXT4_C2B(sbi, pa->pa_len)))
                        continue;
                /* non-extent files can't have physical blocks past 2^32 */
                if (!(ext4_test_inode_flag(ac->ac_inode, EXT4_INODE_EXTENTS)) &&
-                        pa->pa_pstart + pa->pa_len > EXT4_MAX_BLOCK_FILE_PHYS)
+                    (pa->pa_pstart + EXT4_C2B(sbi, pa->pa_len) >
+                     EXT4_MAX_BLOCK_FILE_PHYS))
                        continue;
                /* found preallocated blocks, use them */
@@ -3291,7 +3322,7 @@ static void ext4_mb_generate_from_freelist(struct super_block *sb, void *bitmap,
        while (n) {
                entry = rb_entry(n, struct ext4_free_data, node);
-                ext4_set_bits(bitmap, entry->start_blk, entry->count);
+                ext4_set_bits(bitmap, entry->start_cluster, entry->count);
                n = rb_next(n);
        }
        return;
@@ -3312,7 +3343,6 @@ void ext4_mb_generate_from_pa(struct super_block *sb, void *bitmap,
        ext4_group_t groupnr;
        ext4_grpblk_t start;
        int preallocated = 0;
-        int count = 0;
        int len;
        /* all form of preallocation discards first load group,
@@ -3335,7 +3365,6 @@ void ext4_mb_generate_from_pa(struct super_block *sb, void *bitmap,
                BUG_ON(groupnr != group);
                ext4_set_bits(bitmap, start, len);
                preallocated += len;
-                count++;
        }
        mb_debug(1, "prellocated %u for group %u\n", preallocated, group);
 }
@@ -3412,6 +3441,7 @@ static noinline_for_stack int
 ext4_mb_new_inode_pa(struct ext4_allocation_context *ac)
 {
        struct super_block *sb = ac->ac_sb;
+        struct ext4_sb_info *sbi = EXT4_SB(sb);
        struct ext4_prealloc_space *pa;
        struct ext4_group_info *grp;
        struct ext4_inode_info *ei;
@@ -3443,16 +3473,18 @@ ext4_mb_new_inode_pa(struct ext4_allocation_context *ac)
                winl = ac->ac_o_ex.fe_logical - ac->ac_g_ex.fe_logical;
                /* also, we should cover whole original request */
-                wins = ac->ac_b_ex.fe_len - ac->ac_o_ex.fe_len;
+                wins = EXT4_C2B(sbi, ac->ac_b_ex.fe_len - ac->ac_o_ex.fe_len);
                /* the smallest one defines real window */
                win = min(winl, wins);
-                offs = ac->ac_o_ex.fe_logical % ac->ac_b_ex.fe_len;
+                offs = ac->ac_o_ex.fe_logical %
+                        EXT4_C2B(sbi, ac->ac_b_ex.fe_len);
                if (offs && offs < win)
                        win = offs;
-                ac->ac_b_ex.fe_logical = ac->ac_o_ex.fe_logical - win;
+                ac->ac_b_ex.fe_logical = ac->ac_o_ex.fe_logical -
+                        EXT4_B2C(sbi, win);
                BUG_ON(ac->ac_o_ex.fe_logical < ac->ac_b_ex.fe_logical);
                BUG_ON(ac->ac_o_ex.fe_len > ac->ac_b_ex.fe_len);
        }
@@ -3477,7 +3509,7 @@ ext4_mb_new_inode_pa(struct ext4_allocation_context *ac)
        trace_ext4_mb_new_inode_pa(ac, pa);
        ext4_mb_use_inode_pa(ac, pa);
-        atomic_add(pa->pa_free, &EXT4_SB(sb)->s_mb_preallocated);
+        atomic_add(pa->pa_free, &sbi->s_mb_preallocated);
        ei = EXT4_I(ac->ac_inode);
        grp = ext4_get_group_info(sb, ac->ac_b_ex.fe_group);
@@ -3592,7 +3624,7 @@ ext4_mb_release_inode_pa(struct ext4_buddy *e4b, struct buffer_head *bitmap_bh,
        BUG_ON(pa->pa_deleted == 0);
        ext4_get_group_no_and_offset(sb, pa->pa_pstart, &group, &bit);
-        grp_blk_start = pa->pa_pstart - bit;
+        grp_blk_start = pa->pa_pstart - EXT4_C2B(sbi, bit);
        BUG_ON(group != e4b->bd_group && pa->pa_len != 0);
        end = bit + pa->pa_len;
@@ -3607,7 +3639,8 @@ ext4_mb_release_inode_pa(struct ext4_buddy *e4b, struct buffer_head *bitmap_bh,
                free += next - bit;
                trace_ext4_mballoc_discard(sb, NULL, group, bit, next - bit);
-                trace_ext4_mb_release_inode_pa(pa, grp_blk_start + bit,
+                trace_ext4_mb_release_inode_pa(pa, (grp_blk_start +
+                                                    EXT4_C2B(sbi, bit)),
                                               next - bit);
                mb_free_blocks(pa->pa_inode, e4b, bit, next - bit);
                bit = next + 1;
@@ -3690,7 +3723,7 @@ ext4_mb_discard_group_preallocations(struct super_block *sb,
        }
        if (needed == 0)
-                needed = EXT4_BLOCKS_PER_GROUP(sb) + 1;
+                needed = EXT4_CLUSTERS_PER_GROUP(sb) + 1;
        INIT_LIST_HEAD(&list);
 repeat:
@@ -3958,7 +3991,7 @@ static void ext4_mb_group_or_file(struct ext4_allocation_context *ac)
        if (unlikely(ac->ac_flags & EXT4_MB_HINT_GOAL_ONLY))
                return;
-        size = ac->ac_o_ex.fe_logical + ac->ac_o_ex.fe_len;
+        size = ac->ac_o_ex.fe_logical + EXT4_C2B(sbi, ac->ac_o_ex.fe_len);
        isize = (i_size_read(ac->ac_inode) + ac->ac_sb->s_blocksize - 1)
                >> bsbits;
@@ -3969,6 +4002,11 @@ static void ext4_mb_group_or_file(struct ext4_allocation_context *ac)
                return;
        }
+        if (sbi->s_mb_group_prealloc <= 0) {
+                ac->ac_flags |= EXT4_MB_STREAM_ALLOC;
+                return;
+        }
        /* don't use group allocation for large files */
        size = max(size, isize);
        if (size > sbi->s_mb_stream_request) {
@@ -4007,8 +4045,8 @@ ext4_mb_initialize_context(struct ext4_allocation_context *ac,
        len = ar->len;
        /* just a dirty hack to filter too big requests  */
-        if (len >= EXT4_BLOCKS_PER_GROUP(sb) - 10)
+        if (len >= EXT4_CLUSTERS_PER_GROUP(sb) - 10)
-                len = EXT4_BLOCKS_PER_GROUP(sb) - 10;
+                len = EXT4_CLUSTERS_PER_GROUP(sb) - 10;
        /* start searching from the goal */
        goal = ar->goal;
@@ -4019,18 +4057,15 @@ ext4_mb_initialize_context(struct ext4_allocation_context *ac,
        /* set up allocation goals */
        memset(ac, 0, sizeof(struct ext4_allocation_context));
-        ac->ac_b_ex.fe_logical = ar->logical;
+        ac->ac_b_ex.fe_logical = ar->logical & ~(sbi->s_cluster_ratio - 1);
        ac->ac_status = AC_STATUS_CONTINUE;
        ac->ac_sb = sb;
        ac->ac_inode = ar->inode;
-        ac->ac_o_ex.fe_logical = ar->logical;
+        ac->ac_o_ex.fe_logical = ac->ac_b_ex.fe_logical;
        ac->ac_o_ex.fe_group = group;
        ac->ac_o_ex.fe_start = block;
        ac->ac_o_ex.fe_len = len;
-        ac->ac_g_ex.fe_logical = ar->logical;
+        ac->ac_g_ex = ac->ac_o_ex;
-        ac->ac_g_ex.fe_group = group;
-        ac->ac_g_ex.fe_start = block;
-        ac->ac_g_ex.fe_len = len;
        ac->ac_flags = ar->flags;
        /* we have to define context: we'll we work with a file or
@@ -4182,13 +4217,14 @@ static void ext4_mb_add_n_trim(struct ext4_allocation_context *ac)
 */
 static int ext4_mb_release_context(struct ext4_allocation_context *ac)
 {
+        struct ext4_sb_info *sbi = EXT4_SB(ac->ac_sb);
        struct ext4_prealloc_space *pa = ac->ac_pa;
        if (pa) {
                if (pa->pa_type == MB_GROUP_PA) {
                        /* see comment in ext4_mb_use_group_pa() */
                        spin_lock(&pa->pa_lock);
-                        pa->pa_pstart += ac->ac_b_ex.fe_len;
+                        pa->pa_pstart += EXT4_C2B(sbi, ac->ac_b_ex.fe_len);
-                        pa->pa_lstart += ac->ac_b_ex.fe_len;
+                        pa->pa_lstart += EXT4_C2B(sbi, ac->ac_b_ex.fe_len);
                        pa->pa_free -= ac->ac_b_ex.fe_len;
                        pa->pa_len -= ac->ac_b_ex.fe_len;
                        spin_unlock(&pa->pa_lock);
@@ -4249,13 +4285,17 @@ ext4_fsblk_t ext4_mb_new_blocks(handle_t *handle,
        struct super_block *sb;
        ext4_fsblk_t block = 0;
        unsigned int inquota = 0;
-        unsigned int reserv_blks = 0;
+        unsigned int reserv_clstrs = 0;
        sb = ar->inode->i_sb;
        sbi = EXT4_SB(sb);
        trace_ext4_request_blocks(ar);
+        /* Allow to use superuser reservation for quota file */
+        if (IS_NOQUOTA(ar->inode))
+                ar->flags |= EXT4_MB_USE_ROOT_BLOCKS;
        /*
         * For delayed allocation, we could skip the ENOSPC and
         * EDQUOT check, as blocks and quotas have been already
@@ -4269,7 +4309,7 @@ ext4_fsblk_t ext4_mb_new_blocks(handle_t *handle,
                 * and verify allocation doesn't exceed the quota limits.
                 */
                while (ar->len &&
-                        ext4_claim_free_blocks(sbi, ar->len, ar->flags)) {
+                        ext4_claim_free_clusters(sbi, ar->len, ar->flags)) {
                        /* let others to free the space */
                        yield();
@@ -4279,12 +4319,14 @@ ext4_fsblk_t ext4_mb_new_blocks(handle_t *handle,
                        *errp = -ENOSPC;
                        return 0;
                }
-                reserv_blks = ar->len;
+                reserv_clstrs = ar->len;
                if (ar->flags & EXT4_MB_USE_ROOT_BLOCKS) {
-                        dquot_alloc_block_nofail(ar->inode, ar->len);
+                        dquot_alloc_block_nofail(ar->inode,
+                                                 EXT4_C2B(sbi, ar->len));
                } else {
                        while (ar->len &&
-                                dquot_alloc_block(ar->inode, ar->len)) {
+                                dquot_alloc_block(ar->inode,
+                                                  EXT4_C2B(sbi, ar->len))) {
                                ar->flags |= EXT4_MB_HINT_NOPREALLOC;
                                ar->len--;
@@ -4328,7 +4370,7 @@ repeat:
                        ext4_mb_new_preallocation(ac);
        }
        if (likely(ac->ac_status == AC_STATUS_FOUND)) {
-                *errp = ext4_mb_mark_diskspace_used(ac, handle, reserv_blks);
+                *errp = ext4_mb_mark_diskspace_used(ac, handle, reserv_clstrs);
                if (*errp == -EAGAIN) {
                        /*
                         * drop the reference that we took
@@ -4364,13 +4406,13 @@ out:
        if (ac)
                kmem_cache_free(ext4_ac_cachep, ac);
        if (inquota && ar->len < inquota)
-                dquot_free_block(ar->inode, inquota - ar->len);
+                dquot_free_block(ar->inode, EXT4_C2B(sbi, inquota - ar->len));
        if (!ar->len) {
                if (!ext4_test_inode_state(ar->inode,
                                           EXT4_STATE_DELALLOC_RESERVED))
                        /* release all the reserved blocks if non delalloc */
-                        percpu_counter_sub(&sbi->s_dirtyblocks_counter,
+                        percpu_counter_sub(&sbi->s_dirtyclusters_counter,
-                                                reserv_blks);
+                                                reserv_clstrs);
        }
        trace_ext4_allocate_blocks(ar, (unsigned long long)block);
@@ -4388,7 +4430,7 @@ static int can_merge(struct ext4_free_data *entry1,
 {
        if ((entry1->t_tid == entry2->t_tid) &&
            (entry1->group == entry2->group) &&
-            ((entry1->start_blk + entry1->count) == entry2->start_blk))
+            ((entry1->start_cluster + entry1->count) == entry2->start_cluster))
                return 1;
        return 0;
 }
@@ -4398,7 +4440,7 @@ ext4_mb_free_metadata(handle_t *handle, struct ext4_buddy *e4b,
                      struct ext4_free_data *new_entry)
 {
        ext4_group_t group = e4b->bd_group;
-        ext4_grpblk_t block;
+        ext4_grpblk_t cluster;
        struct ext4_free_data *entry;
        struct ext4_group_info *db = e4b->bd_info;
        struct super_block *sb = e4b->bd_sb;
@@ -4411,7 +4453,7 @@ ext4_mb_free_metadata(handle_t *handle, struct ext4_buddy *e4b,
        BUG_ON(e4b->bd_buddy_page == NULL);
        new_node = &new_entry->node;
-        block = new_entry->start_blk;
+        cluster = new_entry->start_cluster;
        if (!*n) {
                /* first free block exent. We need to
@@ -4425,13 +4467,14 @@ ext4_mb_free_metadata(handle_t *handle, struct ext4_buddy *e4b,
        while (*n) {
                parent = *n;
                entry = rb_entry(parent, struct ext4_free_data, node);
-                if (block < entry->start_blk)
+                if (cluster < entry->start_cluster)
                        n = &(*n)->rb_left;
-                else if (block >= (entry->start_blk + entry->count))
+                else if (cluster >= (entry->start_cluster + entry->count))
                        n = &(*n)->rb_right;
                else {
                        ext4_grp_locked_error(sb, group, 0,
-                                ext4_group_first_block_no(sb, group) + block,
+                                ext4_group_first_block_no(sb, group) +
+                                EXT4_C2B(sbi, cluster),
                                "Block already on to-be-freed list");
                        return 0;
                }
@@ -4445,7 +4488,7 @@ ext4_mb_free_metadata(handle_t *handle, struct ext4_buddy *e4b,
        if (node) {
                entry = rb_entry(node, struct ext4_free_data, node);
                if (can_merge(entry, new_entry)) {
-                        new_entry->start_blk = entry->start_blk;
+                        new_entry->start_cluster = entry->start_cluster;
                        new_entry->count += entry->count;
                        rb_erase(node, &(db->bb_free_root));
                        spin_lock(&sbi->s_md_lock);
@@ -4496,6 +4539,7 @@ void ext4_free_blocks(handle_t *handle, struct inode *inode,
        ext4_group_t block_group;
        struct ext4_sb_info *sbi;
        struct ext4_buddy e4b;
+        unsigned int count_clusters;
        int err = 0;
        int ret;
@@ -4544,6 +4588,38 @@ void ext4_free_blocks(handle_t *handle, struct inode *inode,
        if (!ext4_should_writeback_data(inode))
                flags |= EXT4_FREE_BLOCKS_METADATA;
+        /*
+         * If the extent to be freed does not begin on a cluster
+         * boundary, we need to deal with partial clusters at the
+         * beginning and end of the extent.  Normally we will free
+         * blocks at the beginning or the end unless we are explicitly
+         * requested to avoid doing so.
+         */
+        overflow = block & (sbi->s_cluster_ratio - 1);
+        if (overflow) {
+                if (flags & EXT4_FREE_BLOCKS_NOFREE_FIRST_CLUSTER) {
+                        overflow = sbi->s_cluster_ratio - overflow;
+                        block += overflow;
+                        if (count > overflow)
+                                count -= overflow;
+                        else
+                                return;
+                } else {
+                        block -= overflow;
+                        count += overflow;
+                }
+        }
+        overflow = count & (sbi->s_cluster_ratio - 1);
+        if (overflow) {
+                if (flags & EXT4_FREE_BLOCKS_NOFREE_LAST_CLUSTER) {
+                        if (count > overflow)
+                                count -= overflow;
+                        else
+                                return;
+                } else
+                        count += sbi->s_cluster_ratio - overflow;
+        }
 do_more:
        overflow = 0;
        ext4_get_group_no_and_offset(sb, block, &block_group, &bit);
@@ -4552,10 +4628,12 @@ do_more:
         * Check to see if we are freeing blocks across a group
         * boundary.
         */
-        if (bit + count > EXT4_BLOCKS_PER_GROUP(sb)) {
+        if (EXT4_C2B(sbi, bit) + count > EXT4_BLOCKS_PER_GROUP(sb)) {
-                overflow = bit + count - EXT4_BLOCKS_PER_GROUP(sb);
+                overflow = EXT4_C2B(sbi, bit) + count -
+                        EXT4_BLOCKS_PER_GROUP(sb);
                count -= overflow;
        }
+        count_clusters = EXT4_B2C(sbi, count);
        bitmap_bh = ext4_read_block_bitmap(sb, block_group);
        if (!bitmap_bh) {
                err = -EIO;
@@ -4570,9 +4648,9 @@ do_more:
        if (in_range(ext4_block_bitmap(sb, gdp), block, count) ||
            in_range(ext4_inode_bitmap(sb, gdp), block, count) ||
            in_range(block, ext4_inode_table(sb, gdp),
-                      EXT4_SB(sb)->s_itb_per_group) ||
+                     EXT4_SB(sb)->s_itb_per_group) ||
            in_range(block + count - 1, ext4_inode_table(sb, gdp),
-                      EXT4_SB(sb)->s_itb_per_group)) {
+                     EXT4_SB(sb)->s_itb_per_group)) {
                ext4_error(sb, "Freeing blocks in system zone - "
                           "Block = %llu, count = %lu", block, count);
@@ -4597,11 +4675,11 @@ do_more:
 #ifdef AGGRESSIVE_CHECK
        {
                int i;
-                for (i = 0; i < count; i++)
+                for (i = 0; i < count_clusters; i++)
                        BUG_ON(!mb_test_bit(bit + i, bitmap_bh->b_data));
        }
 #endif
-        trace_ext4_mballoc_free(sb, inode, block_group, bit, count);
+        trace_ext4_mballoc_free(sb, inode, block_group, bit, count_clusters);
        err = ext4_mb_load_buddy(sb, block_group, &e4b);
        if (err)
@@ -4618,13 +4696,13 @@ do_more:
                        err = -ENOMEM;
                        goto error_return;
                }
-                new_entry->start_blk = bit;
+                new_entry->start_cluster = bit;
                new_entry->group  = block_group;
-                new_entry->count = count;
+                new_entry->count = count_clusters;
                new_entry->t_tid = handle->h_transaction->t_tid;
                ext4_lock_group(sb, block_group);
-                mb_clear_bits(bitmap_bh->b_data, bit, count);
+                mb_clear_bits(bitmap_bh->b_data, bit, count_clusters);
                ext4_mb_free_metadata(handle, &e4b, new_entry);
        } else {
                /* need to update group_info->bb_free and bitmap
@@ -4632,25 +4710,29 @@ do_more:
                 * them with group lock_held
                 */
                ext4_lock_group(sb, block_group);
-                mb_clear_bits(bitmap_bh->b_data, bit, count);
+                mb_clear_bits(bitmap_bh->b_data, bit, count_clusters);
-                mb_free_blocks(inode, &e4b, bit, count);
+                mb_free_blocks(inode, &e4b, bit, count_clusters);
        }
-        ret = ext4_free_blks_count(sb, gdp) + count;
+        ret = ext4_free_group_clusters(sb, gdp) + count_clusters;
-        ext4_free_blks_set(sb, gdp, ret);
+        ext4_free_group_clusters_set(sb, gdp, ret);
        gdp->bg_checksum = ext4_group_desc_csum(sbi, block_group, gdp);
        ext4_unlock_group(sb, block_group);
-        percpu_counter_add(&sbi->s_freeblocks_counter, count);
+        percpu_counter_add(&sbi->s_freeclusters_counter, count_clusters);
        if (sbi->s_log_groups_per_flex) {
                ext4_group_t flex_group = ext4_flex_group(sbi, block_group);
-                atomic_add(count, &sbi->s_flex_groups[flex_group].free_blocks);
+                atomic_add(count_clusters,
+                           &sbi->s_flex_groups[flex_group].free_clusters);
        }
        ext4_mb_unload_buddy(&e4b);
        freed += count;
+        if (!(flags & EXT4_FREE_BLOCKS_NO_QUOT_UPDATE))
+                dquot_free_block(inode, EXT4_C2B(sbi, count_clusters));
        /* We dirtied the bitmap block */
        BUFFER_TRACE(bitmap_bh, "dirtied bitmap block");
        err = ext4_handle_dirty_metadata(handle, NULL, bitmap_bh);
@@ -4669,8 +4751,6 @@ do_more:
        }
        ext4_mark_super_dirty(sb);
 error_return:
-        if (freed && !(flags & EXT4_FREE_BLOCKS_NO_QUOT_UPDATE))
-                dquot_free_block(inode, freed);
        brelse(bitmap_bh);
        ext4_std_error(sb, err);
        return;
@@ -4778,16 +4858,17 @@ int ext4_group_add_blocks(handle_t *handle, struct super_block *sb,
        ext4_lock_group(sb, block_group);
        mb_clear_bits(bitmap_bh->b_data, bit, count);
        mb_free_blocks(NULL, &e4b, bit, count);
-        blk_free_count = blocks_freed + ext4_free_blks_count(sb, desc);
+        blk_free_count = blocks_freed + ext4_free_group_clusters(sb, desc);
-        ext4_free_blks_set(sb, desc, blk_free_count);
+        ext4_free_group_clusters_set(sb, desc, blk_free_count);
        desc->bg_checksum = ext4_group_desc_csum(sbi, block_group, desc);
        ext4_unlock_group(sb, block_group);
-        percpu_counter_add(&sbi->s_freeblocks_counter, blocks_freed);
+        percpu_counter_add(&sbi->s_freeclusters_counter,
+                           EXT4_B2C(sbi, blocks_freed));
        if (sbi->s_log_groups_per_flex) {
                ext4_group_t flex_group = ext4_flex_group(sbi, block_group);
-                atomic_add(blocks_freed,
+                atomic_add(EXT4_B2C(sbi, blocks_freed),
-                           &sbi->s_flex_groups[flex_group].free_blocks);
+                           &sbi->s_flex_groups[flex_group].free_clusters);
        }
        ext4_mb_unload_buddy(&e4b);
@@ -4948,7 +5029,7 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range)
        struct ext4_group_info *grp;
        ext4_group_t first_group, last_group;
        ext4_group_t group, ngroups = ext4_get_groups_count(sb);
-        ext4_grpblk_t cnt = 0, first_block, last_block;
+        ext4_grpblk_t cnt = 0, first_cluster, last_cluster;
        uint64_t start, len, minlen, trimmed = 0;
        ext4_fsblk_t first_data_blk =
                        le32_to_cpu(EXT4_SB(sb)->s_es->s_first_data_block);
@@ -4958,7 +5039,7 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range)
        len = range->len >> sb->s_blocksize_bits;
        minlen = range->minlen >> sb->s_blocksize_bits;
-        if (unlikely(minlen > EXT4_BLOCKS_PER_GROUP(sb)))
+        if (unlikely(minlen > EXT4_CLUSTERS_PER_GROUP(sb)))
                return -EINVAL;
        if (start + len <= first_data_blk)
                goto out;
@@ -4969,11 +5050,11 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range)
        /* Determine first and last group to examine based on start and len */
        ext4_get_group_no_and_offset(sb, (ext4_fsblk_t) start,
-                                     &first_group, &first_block);
+                                     &first_group, &first_cluster);
        ext4_get_group_no_and_offset(sb, (ext4_fsblk_t) (start + len),
-                                     &last_group, &last_block);
+                                     &last_group, &last_cluster);
        last_group = (last_group > ngroups - 1) ? ngroups - 1 : last_group;
-        last_block = EXT4_BLOCKS_PER_GROUP(sb);
+        last_cluster = EXT4_CLUSTERS_PER_GROUP(sb);
        if (first_group > last_group)
                return -EINVAL;
@@ -4993,20 +5074,20 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range)
                 * change it for the last group in which case start +
                 * len < EXT4_BLOCKS_PER_GROUP(sb).
                 */
-                if (first_block + len < EXT4_BLOCKS_PER_GROUP(sb))
+                if (first_cluster + len < EXT4_CLUSTERS_PER_GROUP(sb))
-                        last_block = first_block + len;
+                        last_cluster = first_cluster + len;
-                len -= last_block - first_block;
+                len -= last_cluster - first_cluster;
                if (grp->bb_free >= minlen) {
-                        cnt = ext4_trim_all_free(sb, group, first_block,
+                        cnt = ext4_trim_all_free(sb, group, first_cluster,
-                                                last_block, minlen);
+                                                last_cluster, minlen);
                        if (cnt < 0) {
                                ret = cnt;
                                break;
                        }
                }
                trimmed += cnt;
-                first_block = 0;
+                first_cluster = 0;
        }
        range->len = trimmed * sb->s_blocksize;
diff --git a/fs/ext4/mballoc.h b/fs/ext4/mballoc.h
index 9d4a636b546c..47705f3285e3 100644
--- a/fs/ext4/mballoc.h
+++ b/fs/ext4/mballoc.h
@@ -106,7 +106,7 @@ struct ext4_free_data {
        ext4_group_t group;
        /* free block extent */
-        ext4_grpblk_t start_blk;
+        ext4_grpblk_t start_cluster;
        ext4_grpblk_t count;
        /* transaction which freed this extent */
@@ -139,9 +139,9 @@ enum {
 struct ext4_free_extent {
        ext4_lblk_t fe_logical;
-        ext4_grpblk_t fe_start;
+        ext4_grpblk_t fe_start; /* In cluster units */
        ext4_group_t fe_group;
-        ext4_grpblk_t fe_len;
+        ext4_grpblk_t fe_len;   /* In cluster units */
 };
 /*
@@ -175,7 +175,7 @@ struct ext4_allocation_context {
        /* the best found extent */
        struct ext4_free_extent ac_b_ex;
-        /* copy of the bext found extent taken before preallocation efforts */
+        /* copy of the best found extent taken before preallocation efforts */
        struct ext4_free_extent ac_f_ex;
        /* number of iterations done. we have to track to limit searching */
@@ -216,6 +216,7 @@ struct ext4_buddy {
 static inline ext4_fsblk_t ext4_grp_offs_to_block(struct super_block *sb,
                                        struct ext4_free_extent *fex)
 {
-        return ext4_group_first_block_no(sb, fex->fe_group) + fex->fe_start;
+        return ext4_group_first_block_no(sb, fex->fe_group) +
+                (fex->fe_start << EXT4_SB(sb)->s_cluster_bits);
 }
 #endif
diff --git a/fs/ext4/migrate.c b/fs/ext4/migrate.c
index b57b98fb44d1..16ac228dbec6 100644
--- a/fs/ext4/migrate.c
+++ b/fs/ext4/migrate.c
@@ -15,19 +15,18 @@
 #include <linux/module.h>
 #include <linux/slab.h>
 #include "ext4_jbd2.h"
-#include "ext4_extents.h"
 /*
 * The contiguous blocks details which can be
 * represented by a single extent
 */
-struct list_blocks_struct {
+struct migrate_struct {
-        ext4_lblk_t first_block, last_block;
+        ext4_lblk_t first_block, last_block, curr_block;
        ext4_fsblk_t first_pblock, last_pblock;
 };
 static int finish_range(handle_t *handle, struct inode *inode,
-                                struct list_blocks_struct *lb)
+                                struct migrate_struct *lb)
 {
        int retval = 0, needed;
@@ -87,8 +86,7 @@ err_out:
 }
 static int update_extent_range(handle_t *handle, struct inode *inode,
-                                ext4_fsblk_t pblock, ext4_lblk_t blk_num,
+                               ext4_fsblk_t pblock, struct migrate_struct *lb)
-                                struct list_blocks_struct *lb)
 {
        int retval;
        /*
@@ -96,9 +94,10 @@ static int update_extent_range(handle_t *handle, struct inode *inode,
         */
        if (lb->first_pblock &&
                (lb->last_pblock+1 == pblock) &&
-                (lb->last_block+1 == blk_num)) {
+                (lb->last_block+1 == lb->curr_block)) {
                lb->last_pblock = pblock;
-                lb->last_block = blk_num;
+                lb->last_block = lb->curr_block;
+                lb->curr_block++;
                return 0;
        }
        /*
@@ -106,64 +105,49 @@ static int update_extent_range(handle_t *handle, struct inode *inode,
         */
        retval = finish_range(handle, inode, lb);
        lb->first_pblock = lb->last_pblock = pblock;
-        lb->first_block = lb->last_block = blk_num;
+        lb->first_block = lb->last_block = lb->curr_block;
+        lb->curr_block++;
        return retval;
 }
 static int update_ind_extent_range(handle_t *handle, struct inode *inode,
-                                   ext4_fsblk_t pblock, ext4_lblk_t *blk_nump,
+                                   ext4_fsblk_t pblock,
-                                   struct list_blocks_struct *lb)
+                                   struct migrate_struct *lb)
 {
        struct buffer_head *bh;
        __le32 *i_data;
        int i, retval = 0;
-        ext4_lblk_t blk_count = *blk_nump;
        unsigned long max_entries = inode->i_sb->s_blocksize >> 2;
-        if (!pblock) {
-                /* Only update the file block number */
-                *blk_nump += max_entries;
-                return 0;
-        }
        bh = sb_bread(inode->i_sb, pblock);
        if (!bh)
                return -EIO;
        i_data = (__le32 *)bh->b_data;
-        for (i = 0; i < max_entries; i++, blk_count++) {
+        for (i = 0; i < max_entries; i++) {
                if (i_data[i]) {
                        retval = update_extent_range(handle, inode,
-                                                le32_to_cpu(i_data[i]),
+                                                le32_to_cpu(i_data[i]), lb);
-                                                blk_count, lb);
                        if (retval)
                                break;
+                } else {
+                        lb->curr_block++;
                }
        }
-        /* Update the file block number */
-        *blk_nump = blk_count;
        put_bh(bh);
        return retval;
 }
 static int update_dind_extent_range(handle_t *handle, struct inode *inode,
-                                    ext4_fsblk_t pblock, ext4_lblk_t *blk_nump,
+                                    ext4_fsblk_t pblock,
-                                    struct list_blocks_struct *lb)
+                                    struct migrate_struct *lb)
 {
        struct buffer_head *bh;
        __le32 *i_data;
        int i, retval = 0;
-        ext4_lblk_t blk_count = *blk_nump;
        unsigned long max_entries = inode->i_sb->s_blocksize >> 2;
-        if (!pblock) {
-                /* Only update the file block number */
-                *blk_nump += max_entries * max_entries;
-                return 0;
-        }
        bh = sb_bread(inode->i_sb, pblock);
        if (!bh)
                return -EIO;
@@ -172,38 +156,28 @@ static int update_dind_extent_range(handle_t *handle, struct inode *inode,
        for (i = 0; i < max_entries; i++) {
                if (i_data[i]) {
                        retval = update_ind_extent_range(handle, inode,
-                                                le32_to_cpu(i_data[i]),
+                                                le32_to_cpu(i_data[i]), lb);
-                                                &blk_count, lb);
                        if (retval)
                                break;
                } else {
                        /* Only update the file block number */
-                        blk_count += max_entries;
+                        lb->curr_block += max_entries;
                }
        }
-        /* Update the file block number */
-        *blk_nump = blk_count;
        put_bh(bh);
        return retval;
 }
 static int update_tind_extent_range(handle_t *handle, struct inode *inode,
-                                     ext4_fsblk_t pblock, ext4_lblk_t *blk_nump,
+                                    ext4_fsblk_t pblock,
-                                     struct list_blocks_struct *lb)
+                                    struct migrate_struct *lb)
 {
        struct buffer_head *bh;
        __le32 *i_data;
        int i, retval = 0;
-        ext4_lblk_t blk_count = *blk_nump;
        unsigned long max_entries = inode->i_sb->s_blocksize >> 2;
-        if (!pblock) {
-                /* Only update the file block number */
-                *blk_nump += max_entries * max_entries * max_entries;
-                return 0;
-        }
        bh = sb_bread(inode->i_sb, pblock);
        if (!bh)
                return -EIO;
@@ -212,16 +186,14 @@ static int update_tind_extent_range(handle_t *handle, struct inode *inode,
        for (i = 0; i < max_entries; i++) {
                if (i_data[i]) {
                        retval = update_dind_extent_range(handle, inode,
-                                                le32_to_cpu(i_data[i]),
+                                                le32_to_cpu(i_data[i]), lb);
-                                                &blk_count, lb);
                        if (retval)
                                break;
-                } else
+                } else {
                        /* Only update the file block number */
-                        blk_count += max_entries * max_entries;
+                        lb->curr_block += max_entries * max_entries;
+                }
        }
-        /* Update the file block number */
-        *blk_nump = blk_count;
        put_bh(bh);
        return retval;
@@ -462,12 +434,12 @@ int ext4_ext_migrate(struct inode *inode)
        handle_t *handle;
        int retval = 0, i;
        __le32 *i_data;
-        ext4_lblk_t blk_count = 0;
        struct ext4_inode_info *ei;
        struct inode *tmp_inode = NULL;
-        struct list_blocks_struct lb;
+        struct migrate_struct lb;
        unsigned long max_entries;
        __u32 goal;
+        uid_t owner[2];
        /*
         * If the filesystem does not support extents, or the inode
@@ -495,10 +467,12 @@ int ext4_ext_migrate(struct inode *inode)
        }
        goal = (((inode->i_ino - 1) / EXT4_INODES_PER_GROUP(inode->i_sb)) *
                EXT4_INODES_PER_GROUP(inode->i_sb)) + 1;
+        owner[0] = inode->i_uid;
+        owner[1] = inode->i_gid;
        tmp_inode = ext4_new_inode(handle, inode->i_sb->s_root->d_inode,
-                                   S_IFREG, NULL, goal);
+                                   S_IFREG, NULL, goal, owner);
        if (IS_ERR(tmp_inode)) {
-                retval = -ENOMEM;
+                retval = PTR_ERR(inode);
                ext4_journal_stop(handle);
                return retval;
        }
@@ -507,7 +481,7 @@ int ext4_ext_migrate(struct inode *inode)
         * Set the i_nlink to zero so it will be deleted later
         * when we drop inode reference.
         */
-        tmp_inode->i_nlink = 0;
+        clear_nlink(tmp_inode);
        ext4_ext_tree_init(handle, tmp_inode);
        ext4_orphan_add(handle, tmp_inode);
@@ -551,35 +525,32 @@ int ext4_ext_migrate(struct inode *inode)
        /* 32 bit block address 4 bytes */
        max_entries = inode->i_sb->s_blocksize >> 2;
-        for (i = 0; i < EXT4_NDIR_BLOCKS; i++, blk_count++) {
+        for (i = 0; i < EXT4_NDIR_BLOCKS; i++) {
                if (i_data[i]) {
                        retval = update_extent_range(handle, tmp_inode,
-                                                le32_to_cpu(i_data[i]),
+                                                le32_to_cpu(i_data[i]), &lb);
-                                                blk_count, &lb);
                        if (retval)
                                goto err_out;
-                }
+                } else
+                        lb.curr_block++;
        }
        if (i_data[EXT4_IND_BLOCK]) {
                retval = update_ind_extent_range(handle, tmp_inode,
-                                        le32_to_cpu(i_data[EXT4_IND_BLOCK]),
+                                le32_to_cpu(i_data[EXT4_IND_BLOCK]), &lb);
-                                        &blk_count, &lb);
                        if (retval)
                                goto err_out;
        } else
-                blk_count +=  max_entries;
+                lb.curr_block += max_entries;
        if (i_data[EXT4_DIND_BLOCK]) {
                retval = update_dind_extent_range(handle, tmp_inode,
-                                        le32_to_cpu(i_data[EXT4_DIND_BLOCK]),
+                                le32_to_cpu(i_data[EXT4_DIND_BLOCK]), &lb);
-                                        &blk_count, &lb);
                        if (retval)
                                goto err_out;
        } else
-                blk_count += max_entries * max_entries;
+                lb.curr_block += max_entries * max_entries;
        if (i_data[EXT4_TIND_BLOCK]) {
                retval = update_tind_extent_range(handle, tmp_inode,
-                                        le32_to_cpu(i_data[EXT4_TIND_BLOCK]),
+                                le32_to_cpu(i_data[EXT4_TIND_BLOCK]), &lb);
-                                        &blk_count, &lb);
                        if (retval)
                                goto err_out;
        }
diff --git a/fs/ext4/mmp.c b/fs/ext4/mmp.c
index 9bdef3f537c5..7ea4ba4eff2a 100644
--- a/fs/ext4/mmp.c
+++ b/fs/ext4/mmp.c
@@ -109,7 +109,7 @@ static int kmmpd(void *data)
        mmp->mmp_check_interval = cpu_to_le16(mmp_check_interval);
        bdevname(bh->b_bdev, mmp->mmp_bdevname);
-        memcpy(mmp->mmp_nodename, init_utsname()->sysname,
+        memcpy(mmp->mmp_nodename, init_utsname()->nodename,
               sizeof(mmp->mmp_nodename));
        while (!kthread_should_stop()) {
@@ -125,8 +125,9 @@ static int kmmpd(void *data)
                 * Don't spew too many error messages. Print one every
                 * (s_mmp_update_interval * 60) seconds.
                 */
-                if (retval && (failed_writes % 60) == 0) {
+                if (retval) {
-                        ext4_error(sb, "Error writing to MMP block");
+                        if ((failed_writes % 60) == 0)
+                                ext4_error(sb, "Error writing to MMP block");
                        failed_writes++;
                }
@@ -295,7 +296,8 @@ skip:
        /*
         * write a new random sequence number.
         */
-        mmp->mmp_seq = seq = cpu_to_le32(mmp_new_seq());
+        seq = mmp_new_seq();
+        mmp->mmp_seq = cpu_to_le32(seq);
        retval = write_mmp_block(bh);
        if (retval)
diff --git a/fs/ext4/move_extent.c b/fs/ext4/move_extent.c
index f57455a1b1b2..c5826c623e7a 100644
--- a/fs/ext4/move_extent.c
+++ b/fs/ext4/move_extent.c
@@ -17,7 +17,6 @@
 #include <linux/quotaops.h>
 #include <linux/slab.h>
 #include "ext4_jbd2.h"
-#include "ext4_extents.h"
 #include "ext4.h"
 /**
diff --git a/fs/ext4/namei.c b/fs/ext4/namei.c
index 1c924faeb6c8..aa4c782c9dd7 100644
--- a/fs/ext4/namei.c
+++ b/fs/ext4/namei.c
@@ -1586,7 +1586,7 @@ static int ext4_dx_add_entry(handle_t *handle, struct dentry *dentry,
                        dxtrace(dx_show_index("node", frames[1].entries));
                        dxtrace(dx_show_index("node",
                               ((struct dx_node *) bh2->b_data)->entries));
-                        err = ext4_handle_dirty_metadata(handle, inode, bh2);
+                        err = ext4_handle_dirty_metadata(handle, dir, bh2);
                        if (err)
                                goto journal_error;
                        brelse (bh2);
@@ -1612,7 +1612,7 @@ static int ext4_dx_add_entry(handle_t *handle, struct dentry *dentry,
                        if (err)
                                goto journal_error;
                }
-                err = ext4_handle_dirty_metadata(handle, inode, frames[0].bh);
+                err = ext4_handle_dirty_metadata(handle, dir, frames[0].bh);
                if (err) {
                        ext4_std_error(inode->i_sb, err);
                        goto cleanup;
@@ -1694,7 +1694,7 @@ static void ext4_inc_count(handle_t *handle, struct inode *inode)
        if (is_dx(inode) && inode->i_nlink > 1) {
                /* limit is 16-bit i_links_count */
                if (inode->i_nlink >= EXT4_LINK_MAX || inode->i_nlink == 2) {
-                        inode->i_nlink = 1;
+                        set_nlink(inode, 1);
                        EXT4_SET_RO_COMPAT_FEATURE(inode->i_sb,
                                              EXT4_FEATURE_RO_COMPAT_DIR_NLINK);
                }
@@ -1707,9 +1707,8 @@ static void ext4_inc_count(handle_t *handle, struct inode *inode)
 */
 static void ext4_dec_count(handle_t *handle, struct inode *inode)
 {
-        drop_nlink(inode);
+        if (!S_ISDIR(inode->i_mode) || inode->i_nlink > 2)
-        if (S_ISDIR(inode->i_mode) && inode->i_nlink == 0)
+                drop_nlink(inode);
-                inc_nlink(inode);
 }
@@ -1756,7 +1755,7 @@ retry:
        if (IS_DIRSYNC(dir))
                ext4_handle_sync(handle);
-        inode = ext4_new_inode(handle, dir, mode, &dentry->d_name, 0);
+        inode = ext4_new_inode(handle, dir, mode, &dentry->d_name, 0, NULL);
        err = PTR_ERR(inode);
        if (!IS_ERR(inode)) {
                inode->i_op = &ext4_file_inode_operations;
@@ -1792,7 +1791,7 @@ retry:
        if (IS_DIRSYNC(dir))
                ext4_handle_sync(handle);
-        inode = ext4_new_inode(handle, dir, mode, &dentry->d_name, 0);
+        inode = ext4_new_inode(handle, dir, mode, &dentry->d_name, 0, NULL);
        err = PTR_ERR(inode);
        if (!IS_ERR(inode)) {
                init_special_inode(inode, inode->i_mode, rdev);
@@ -1832,7 +1831,7 @@ retry:
                ext4_handle_sync(handle);
        inode = ext4_new_inode(handle, dir, S_IFDIR | mode,
-                               &dentry->d_name, 0);
+                               &dentry->d_name, 0, NULL);
        err = PTR_ERR(inode);
        if (IS_ERR(inode))
                goto out_stop;
@@ -1861,9 +1860,9 @@ retry:
        de->name_len = 2;
        strcpy(de->name, "..");
        ext4_set_de_type(dir->i_sb, de, S_IFDIR);
-        inode->i_nlink = 2;
+        set_nlink(inode, 2);
        BUFFER_TRACE(dir_block, "call ext4_handle_dirty_metadata");
-        err = ext4_handle_dirty_metadata(handle, dir, dir_block);
+        err = ext4_handle_dirty_metadata(handle, inode, dir_block);
        if (err)
                goto out_clear_inode;
        err = ext4_mark_inode_dirty(handle, inode);
@@ -2214,7 +2213,7 @@ static int ext4_unlink(struct inode *dir, struct dentry *dentry)
                ext4_warning(inode->i_sb,
                             "Deleting nonexistent file (%lu), %d",
                             inode->i_ino, inode->i_nlink);
-                inode->i_nlink = 1;
+                set_nlink(inode, 1);
        }
        retval = ext4_delete_entry(handle, dir, de, bh);
        if (retval)
@@ -2279,7 +2278,7 @@ retry:
                ext4_handle_sync(handle);
        inode = ext4_new_inode(handle, dir, S_IFLNK|S_IRWXUGO,
-                               &dentry->d_name, 0);
+                               &dentry->d_name, 0, NULL);
        err = PTR_ERR(inode);
        if (IS_ERR(inode))
                goto out_stop;
@@ -2530,7 +2529,7 @@ static int ext4_rename(struct inode *old_dir, struct dentry *old_dentry,
                PARENT_INO(dir_bh->b_data, new_dir->i_sb->s_blocksize) =
                                                cpu_to_le32(new_dir->i_ino);
                BUFFER_TRACE(dir_bh, "call ext4_handle_dirty_metadata");
-                retval = ext4_handle_dirty_metadata(handle, old_dir, dir_bh);
+                retval = ext4_handle_dirty_metadata(handle, old_inode, dir_bh);
                if (retval) {
                        ext4_std_error(old_dir->i_sb, retval);
                        goto end_rename;
@@ -2539,7 +2538,7 @@ static int ext4_rename(struct inode *old_dir, struct dentry *old_dentry,
                if (new_inode) {
                        /* checked empty_dir above, can't have another parent,
                         * ext4_dec_count() won't work for many-linked dirs */
-                        new_inode->i_nlink = 0;
+                        clear_nlink(new_inode);
                } else {
                        ext4_inc_count(handle, new_dir);
                        ext4_update_dx_flag(new_dir);
diff --git a/fs/ext4/page-io.c b/fs/ext4/page-io.c
index 92f38ee13f8a..7ce1d0b19c94 100644
--- a/fs/ext4/page-io.c
+++ b/fs/ext4/page-io.c
@@ -70,7 +70,6 @@ static void put_io_page(struct ext4_io_page *io_page)
 void ext4_free_io_end(ext4_io_end_t *io)
 {
        int i;
-        wait_queue_head_t *wq;
        BUG_ON(!io);
        if (io->page)
@@ -78,56 +77,43 @@ void ext4_free_io_end(ext4_io_end_t *io)
        for (i = 0; i < io->num_io_pages; i++)
                put_io_page(io->pages[i]);
        io->num_io_pages = 0;
-        wq = ext4_ioend_wq(io->inode);
+        if (atomic_dec_and_test(&EXT4_I(io->inode)->i_ioend_count))
-        if (atomic_dec_and_test(&EXT4_I(io->inode)->i_ioend_count) &&
+                wake_up_all(ext4_ioend_wq(io->inode));
-            waitqueue_active(wq))
-                wake_up_all(wq);
        kmem_cache_free(io_end_cachep, io);
 }
 /*
 * check a range of space and convert unwritten extents to written.
+ *
+ * Called with inode->i_mutex; we depend on this when we manipulate
+ * io->flag, since we could otherwise race with ext4_flush_completed_IO()
 */
 int ext4_end_io_nolock(ext4_io_end_t *io)
 {
        struct inode *inode = io->inode;
        loff_t offset = io->offset;
        ssize_t size = io->size;
-        wait_queue_head_t *wq;
        int ret = 0;
        ext4_debug("ext4_end_io_nolock: io 0x%p from inode %lu,list->next 0x%p,"
                   "list->prev 0x%p\n",
                   io, inode->i_ino, io->list.next, io->list.prev);
-        if (list_empty(&io->list))
-                return ret;
-        if (!(io->flag & EXT4_IO_END_UNWRITTEN))
-                return ret;
        ret = ext4_convert_unwritten_extents(inode, offset, size);
        if (ret < 0) {
-                printk(KERN_EMERG "%s: failed to convert unwritten "
+                ext4_msg(inode->i_sb, KERN_EMERG,
-                        "extents to written extents, error is %d "
+                         "failed to convert unwritten extents to written "
-                        "io is still on inode %lu aio dio list\n",
+                         "extents -- potential data loss!  "
-                       __func__, ret, inode->i_ino);
+                         "(inode %lu, offset %llu, size %zd, error %d)",
-                return ret;
+                         inode->i_ino, offset, size, ret);
        }
        if (io->iocb)
                aio_complete(io->iocb, io->result, 0);
-        /* clear the DIO AIO unwritten flag */
-        if (io->flag & EXT4_IO_END_UNWRITTEN) {
-                io->flag &= ~EXT4_IO_END_UNWRITTEN;
-                /* Wake up anyone waiting on unwritten extent conversion */
-                wq = ext4_ioend_wq(io->inode);
-                if (atomic_dec_and_test(&EXT4_I(inode)->i_aiodio_unwritten) &&
-                    waitqueue_active(wq)) {
-                        wake_up_all(wq);
-                }
-        }
+        /* Wake up anyone waiting on unwritten extent conversion */
+        if (atomic_dec_and_test(&EXT4_I(inode)->i_aiodio_unwritten))
+                wake_up_all(ext4_ioend_wq(io->inode));
        return ret;
 }
@@ -140,9 +126,15 @@ static void ext4_end_io_work(struct work_struct *work)
        struct inode            *inode = io->inode;
        struct ext4_inode_info  *ei = EXT4_I(inode);
        unsigned long           flags;
-        int                     ret;
+        spin_lock_irqsave(&ei->i_completed_io_lock, flags);
+        if (list_empty(&io->list)) {
+                spin_unlock_irqrestore(&ei->i_completed_io_lock, flags);
+                goto free;
+        }
        if (!mutex_trylock(&inode->i_mutex)) {
+                spin_unlock_irqrestore(&ei->i_completed_io_lock, flags);
                /*
                 * Requeue the work instead of waiting so that the work
                 * items queued after this can be processed.
@@ -159,17 +151,11 @@ static void ext4_end_io_work(struct work_struct *work)
                io->flag |= EXT4_IO_END_QUEUED;
                return;
        }
-        ret = ext4_end_io_nolock(io);
+        list_del_init(&io->list);
-        if (ret < 0) {
-                mutex_unlock(&inode->i_mutex);
-                return;
-        }
-        spin_lock_irqsave(&ei->i_completed_io_lock, flags);
-        if (!list_empty(&io->list))
-                list_del_init(&io->list);
        spin_unlock_irqrestore(&ei->i_completed_io_lock, flags);
+        (void) ext4_end_io_nolock(io);
        mutex_unlock(&inode->i_mutex);
+free:
        ext4_free_io_end(io);
 }
@@ -350,10 +336,8 @@ submit_and_retry:
        if ((io_end->num_io_pages >= MAX_IO_PAGES) &&
            (io_end->pages[io_end->num_io_pages-1] != io_page))
                goto submit_and_retry;
-        if (buffer_uninit(bh) && !(io_end->flag & EXT4_IO_END_UNWRITTEN)) {
+        if (buffer_uninit(bh))
-                io_end->flag |= EXT4_IO_END_UNWRITTEN;
+                ext4_set_io_unwritten_flag(inode, io_end);
-                atomic_inc(&EXT4_I(inode)->i_aiodio_unwritten);
-        }
        io->io_end->size += bh->b_size;
        io->io_next_block++;
        ret = bio_add_page(io->io_bio, bh->b_page, bh->b_size, bh_offset(bh));
diff --git a/fs/ext4/resize.c b/fs/ext4/resize.c
index 707d3f16f7ce..996780ab4f4e 100644
--- a/fs/ext4/resize.c
+++ b/fs/ext4/resize.c
@@ -875,7 +875,7 @@ int ext4_group_add(struct super_block *sb, struct ext4_new_group_data *input)
        ext4_block_bitmap_set(sb, gdp, input->block_bitmap); /* LV FIXME */
        ext4_inode_bitmap_set(sb, gdp, input->inode_bitmap); /* LV FIXME */
        ext4_inode_table_set(sb, gdp, input->inode_table); /* LV FIXME */
-        ext4_free_blks_set(sb, gdp, input->free_blocks_count);
+        ext4_free_group_clusters_set(sb, gdp, input->free_blocks_count);
        ext4_free_inodes_set(sb, gdp, EXT4_INODES_PER_GROUP(sb));
        gdp->bg_flags = cpu_to_le16(EXT4_BG_INODE_ZEROED);
        gdp->bg_checksum = ext4_group_desc_csum(sbi, input->group, gdp);
@@ -937,8 +937,8 @@ int ext4_group_add(struct super_block *sb, struct ext4_new_group_data *input)
                input->reserved_blocks);
        /* Update the free space counts */
-        percpu_counter_add(&sbi->s_freeblocks_counter,
+        percpu_counter_add(&sbi->s_freeclusters_counter,
-                           input->free_blocks_count);
+                           EXT4_B2C(sbi, input->free_blocks_count));
        percpu_counter_add(&sbi->s_freeinodes_counter,
                           EXT4_INODES_PER_GROUP(sb));
@@ -946,8 +946,8 @@ int ext4_group_add(struct super_block *sb, struct ext4_new_group_data *input)
            sbi->s_log_groups_per_flex) {
                ext4_group_t flex_group;
                flex_group = ext4_flex_group(sbi, input->group);
-                atomic_add(input->free_blocks_count,
+                atomic_add(EXT4_B2C(sbi, input->free_blocks_count),
-                           &sbi->s_flex_groups[flex_group].free_blocks);
+                           &sbi->s_flex_groups[flex_group].free_clusters);
                atomic_add(EXT4_INODES_PER_GROUP(sb),
                           &sbi->s_flex_groups[flex_group].free_inodes);
        }
diff --git a/fs/ext4/super.c b/fs/ext4/super.c
index 44d0c8db2239..9953d80145ad 100644
--- a/fs/ext4/super.c
+++ b/fs/ext4/super.c
@@ -45,6 +45,7 @@
 #include <linux/freezer.h>
 #include "ext4.h"
+#include "ext4_extents.h"
 #include "ext4_jbd2.h"
 #include "xattr.h"
 #include "acl.h"
@@ -163,8 +164,8 @@ ext4_fsblk_t ext4_inode_table(struct super_block *sb,
                 (ext4_fsblk_t)le32_to_cpu(bg->bg_inode_table_hi) << 32 : 0);
 }
-__u32 ext4_free_blks_count(struct super_block *sb,
+__u32 ext4_free_group_clusters(struct super_block *sb,
-                              struct ext4_group_desc *bg)
+                               struct ext4_group_desc *bg)
 {
        return le16_to_cpu(bg->bg_free_blocks_count_lo) |
                (EXT4_DESC_SIZE(sb) >= EXT4_MIN_DESC_SIZE_64BIT ?
@@ -219,8 +220,8 @@ void ext4_inode_table_set(struct super_block *sb,
                bg->bg_inode_table_hi = cpu_to_le32(blk >> 32);
 }
-void ext4_free_blks_set(struct super_block *sb,
+void ext4_free_group_clusters_set(struct super_block *sb,
-                          struct ext4_group_desc *bg, __u32 count)
+                                  struct ext4_group_desc *bg, __u32 count)
 {
        bg->bg_free_blocks_count_lo = cpu_to_le16((__u16)count);
        if (EXT4_DESC_SIZE(sb) >= EXT4_MIN_DESC_SIZE_64BIT)
@@ -414,6 +415,22 @@ static void save_error_info(struct super_block *sb, const char *func,
        ext4_commit_super(sb, 1);
 }
+/*
+ * The del_gendisk() function uninitializes the disk-specific data
+ * structures, including the bdi structure, without telling anyone
+ * else.  Once this happens, any attempt to call mark_buffer_dirty()
+ * (for example, by ext4_commit_super), will cause a kernel OOPS.
+ * This is a kludge to prevent these oops until we can put in a proper
+ * hook in del_gendisk() to inform the VFS and file system layers.
+ */
+static int block_device_ejected(struct super_block *sb)
+{
+        struct inode *bd_inode = sb->s_bdev->bd_inode;
+        struct backing_dev_info *bdi = bd_inode->i_mapping->backing_dev_info;
+        return bdi->dev == NULL;
+}
 /* Deal with the reporting of failure conditions on a filesystem such as
 * inconsistencies detected or read IO failures.
@@ -821,10 +838,10 @@ static void ext4_put_super(struct super_block *sb)
                brelse(sbi->s_group_desc[i]);
        ext4_kvfree(sbi->s_group_desc);
        ext4_kvfree(sbi->s_flex_groups);
-        percpu_counter_destroy(&sbi->s_freeblocks_counter);
+        percpu_counter_destroy(&sbi->s_freeclusters_counter);
        percpu_counter_destroy(&sbi->s_freeinodes_counter);
        percpu_counter_destroy(&sbi->s_dirs_counter);
-        percpu_counter_destroy(&sbi->s_dirtyblocks_counter);
+        percpu_counter_destroy(&sbi->s_dirtyclusters_counter);
        brelse(sbi->s_sbh);
 #ifdef CONFIG_QUOTA
        for (i = 0; i < MAXQUOTAS; i++)
@@ -1057,8 +1074,6 @@ static int ext4_show_options(struct seq_file *seq, struct vfsmount *vfs)
                seq_puts(seq, ",nouid32");
        if (test_opt(sb, DEBUG) && !(def_mount_opts & EXT4_DEFM_DEBUG))
                seq_puts(seq, ",debug");
-        if (test_opt(sb, OLDALLOC))
-                seq_puts(seq, ",oldalloc");
 #ifdef CONFIG_EXT4_FS_XATTR
        if (test_opt(sb, XATTR_USER))
                seq_puts(seq, ",user_xattr");
@@ -1567,10 +1582,12 @@ static int parse_options(char *options, struct super_block *sb,
                        set_opt(sb, DEBUG);
                        break;
                case Opt_oldalloc:
-                        set_opt(sb, OLDALLOC);
+                        ext4_msg(sb, KERN_WARNING,
+                                 "Ignoring deprecated oldalloc option");
                        break;
                case Opt_orlov:
-                        clear_opt(sb, OLDALLOC);
+                        ext4_msg(sb, KERN_WARNING,
+                                 "Ignoring deprecated orlov option");
                        break;
 #ifdef CONFIG_EXT4_FS_XATTR
                case Opt_user_xattr:
@@ -1801,6 +1818,7 @@ set_qf_format:
                        break;
                case Opt_nodelalloc:
                        clear_opt(sb, DELALLOC);
+                        clear_opt2(sb, EXPLICIT_DELALLOC);
                        break;
                case Opt_mblk_io_submit:
                        set_opt(sb, MBLK_IO_SUBMIT);
@@ -1817,6 +1835,7 @@ set_qf_format:
                        break;
                case Opt_delalloc:
                        set_opt(sb, DELALLOC);
+                        set_opt2(sb, EXPLICIT_DELALLOC);
                        break;
                case Opt_block_validity:
                        set_opt(sb, BLOCK_VALIDITY);
@@ -1935,7 +1954,7 @@ static int ext4_setup_super(struct super_block *sb, struct ext4_super_block *es,
                res = MS_RDONLY;
        }
        if (read_only)
-                return res;
+                goto done;
        if (!(sbi->s_mount_state & EXT4_VALID_FS))
                ext4_msg(sb, KERN_WARNING, "warning: mounting unchecked fs, "
                         "running e2fsck is recommended");
@@ -1966,6 +1985,7 @@ static int ext4_setup_super(struct super_block *sb, struct ext4_super_block *es,
                EXT4_SET_INCOMPAT_FEATURE(sb, EXT4_FEATURE_INCOMPAT_RECOVER);
        ext4_commit_super(sb, 1);
+done:
        if (test_opt(sb, DEBUG))
                printk(KERN_INFO "[EXT4 FS bs=%lu, gc=%u, "
                                "bpg=%lu, ipg=%lu, mo=%04x, mo2=%04x]\n",
@@ -2015,8 +2035,8 @@ static int ext4_fill_flex_info(struct super_block *sb)
                flex_group = ext4_flex_group(sbi, i);
                atomic_add(ext4_free_inodes_count(sb, gdp),
                           &sbi->s_flex_groups[flex_group].free_inodes);
-                atomic_add(ext4_free_blks_count(sb, gdp),
+                atomic_add(ext4_free_group_clusters(sb, gdp),
-                           &sbi->s_flex_groups[flex_group].free_blocks);
+                           &sbi->s_flex_groups[flex_group].free_clusters);
                atomic_add(ext4_used_dirs_count(sb, gdp),
                           &sbi->s_flex_groups[flex_group].used_dirs);
        }
@@ -2134,7 +2154,8 @@ static int ext4_check_descriptors(struct super_block *sb,
        if (NULL != first_not_zeroed)
                *first_not_zeroed = grp;
-        ext4_free_blocks_count_set(sbi->s_es, ext4_count_free_blocks(sb));
+        ext4_free_blocks_count_set(sbi->s_es,
+                                   EXT4_C2B(sbi, ext4_count_free_clusters(sb)));
        sbi->s_es->s_free_inodes_count =cpu_to_le32(ext4_count_free_inodes(sb));
        return 1;
 }
@@ -2454,7 +2475,8 @@ static ssize_t delayed_allocation_blocks_show(struct ext4_attr *a,
                                              char *buf)
 {
        return snprintf(buf, PAGE_SIZE, "%llu\n",
-                        (s64) percpu_counter_sum(&sbi->s_dirtyblocks_counter));
+                (s64) EXT4_C2B(sbi,
+                        percpu_counter_sum(&sbi->s_dirtyclusters_counter)));
 }
 static ssize_t session_write_kbytes_show(struct ext4_attr *a,
@@ -2682,6 +2704,13 @@ static int ext4_feature_set_ok(struct super_block *sb, int readonly)
                        return 0;
                }
        }
+        if (EXT4_HAS_RO_COMPAT_FEATURE(sb, EXT4_FEATURE_RO_COMPAT_BIGALLOC) &&
+            !EXT4_HAS_INCOMPAT_FEATURE(sb, EXT4_FEATURE_INCOMPAT_EXTENTS)) {
+                ext4_msg(sb, KERN_ERR,
+                         "Can't support bigalloc feature without "
+                         "extents feature\n");
+                return 0;
+        }
        return 1;
 }
@@ -3087,10 +3116,10 @@ static int ext4_fill_super(struct super_block *sb, void *data, int silent)
        char *cp;
        const char *descr;
        int ret = -ENOMEM;
-        int blocksize;
+        int blocksize, clustersize;
        unsigned int db_count;
        unsigned int i;
-        int needs_recovery, has_huge_files;
+        int needs_recovery, has_huge_files, has_bigalloc;
        __u64 blocks_count;
        int err;
        unsigned int journal_ioprio = DEFAULT_JOURNAL_IOPRIO;
@@ -3224,6 +3253,33 @@ static int ext4_fill_super(struct super_block *sb, void *data, int silent)
                           &journal_ioprio, NULL, 0))
                goto failed_mount;
+        if (test_opt(sb, DATA_FLAGS) == EXT4_MOUNT_JOURNAL_DATA) {
+                printk_once(KERN_WARNING "EXT4-fs: Warning: mounting "
+                            "with data=journal disables delayed "
+                            "allocation and O_DIRECT support!\n");
+                if (test_opt2(sb, EXPLICIT_DELALLOC)) {
+                        ext4_msg(sb, KERN_ERR, "can't mount with "
+                                 "both data=journal and delalloc");
+                        goto failed_mount;
+                }
+                if (test_opt(sb, DIOREAD_NOLOCK)) {
+                        ext4_msg(sb, KERN_ERR, "can't mount with "
+                                 "both data=journal and delalloc");
+                        goto failed_mount;
+                }
+                if (test_opt(sb, DELALLOC))
+                        clear_opt(sb, DELALLOC);
+        }
+        blocksize = BLOCK_SIZE << le32_to_cpu(es->s_log_block_size);
+        if (test_opt(sb, DIOREAD_NOLOCK)) {
+                if (blocksize < PAGE_SIZE) {
+                        ext4_msg(sb, KERN_ERR, "can't mount with "
+                                 "dioread_nolock if block size != PAGE_SIZE");
+                        goto failed_mount;
+                }
+        }
        sb->s_flags = (sb->s_flags & ~MS_POSIXACL) |
                (test_opt(sb, POSIX_ACL) ? MS_POSIXACL : 0);
@@ -3265,8 +3321,6 @@ static int ext4_fill_super(struct super_block *sb, void *data, int silent)
        if (!ext4_feature_set_ok(sb, (sb->s_flags & MS_RDONLY)))
                goto failed_mount;
-        blocksize = BLOCK_SIZE << le32_to_cpu(es->s_log_block_size);
        if (blocksize < EXT4_MIN_BLOCK_SIZE ||
            blocksize > EXT4_MAX_BLOCK_SIZE) {
                ext4_msg(sb, KERN_ERR,
@@ -3369,12 +3423,53 @@ static int ext4_fill_super(struct super_block *sb, void *data, int silent)
                sb->s_dirt = 1;
        }
-        if (sbi->s_blocks_per_group > blocksize * 8) {
+        /* Handle clustersize */
-                ext4_msg(sb, KERN_ERR,
+        clustersize = BLOCK_SIZE << le32_to_cpu(es->s_log_cluster_size);
-                       "#blocks per group too big: %lu",
+        has_bigalloc = EXT4_HAS_RO_COMPAT_FEATURE(sb,
-                       sbi->s_blocks_per_group);
+                                EXT4_FEATURE_RO_COMPAT_BIGALLOC);
-                goto failed_mount;
+        if (has_bigalloc) {
+                if (clustersize < blocksize) {
+                        ext4_msg(sb, KERN_ERR,
+                                 "cluster size (%d) smaller than "
+                                 "block size (%d)", clustersize, blocksize);
+                        goto failed_mount;
+                }
+                sbi->s_cluster_bits = le32_to_cpu(es->s_log_cluster_size) -
+                        le32_to_cpu(es->s_log_block_size);
+                sbi->s_clusters_per_group =
+                        le32_to_cpu(es->s_clusters_per_group);
+                if (sbi->s_clusters_per_group > blocksize * 8) {
+                        ext4_msg(sb, KERN_ERR,
+                                 "#clusters per group too big: %lu",
+                                 sbi->s_clusters_per_group);
+                        goto failed_mount;
+                }
+                if (sbi->s_blocks_per_group !=
+                    (sbi->s_clusters_per_group * (clustersize / blocksize))) {
+                        ext4_msg(sb, KERN_ERR, "blocks per group (%lu) and "
+                                 "clusters per group (%lu) inconsistent",
+                                 sbi->s_blocks_per_group,
+                                 sbi->s_clusters_per_group);
+                        goto failed_mount;
+                }
+        } else {
+                if (clustersize != blocksize) {
+                        ext4_warning(sb, "fragment/cluster size (%d) != "
+                                     "block size (%d)", clustersize,
+                                     blocksize);
+                        clustersize = blocksize;
+                }
+                if (sbi->s_blocks_per_group > blocksize * 8) {
+                        ext4_msg(sb, KERN_ERR,
+                                 "#blocks per group too big: %lu",
+                                 sbi->s_blocks_per_group);
+                        goto failed_mount;
+                }
+                sbi->s_clusters_per_group = sbi->s_blocks_per_group;
+                sbi->s_cluster_bits = 0;
        }
+        sbi->s_cluster_ratio = clustersize / blocksize;
        if (sbi->s_inodes_per_group > blocksize * 8) {
                ext4_msg(sb, KERN_ERR,
                       "#inodes per group too big: %lu",
@@ -3446,10 +3541,8 @@ static int ext4_fill_super(struct super_block *sb, void *data, int silent)
                goto failed_mount;
        }
-#ifdef CONFIG_PROC_FS
        if (ext4_proc_root)
                sbi->s_proc = proc_mkdir(sb->s_id, ext4_proc_root);
-#endif
        bgl_lock_init(sbi->s_blockgroup_lock);
@@ -3483,8 +3576,8 @@ static int ext4_fill_super(struct super_block *sb, void *data, int silent)
        sbi->s_err_report.function = print_daily_error_info;
        sbi->s_err_report.data = (unsigned long) sb;
-        err = percpu_counter_init(&sbi->s_freeblocks_counter,
+        err = percpu_counter_init(&sbi->s_freeclusters_counter,
-                        ext4_count_free_blocks(sb));
+                        ext4_count_free_clusters(sb));
        if (!err) {
                err = percpu_counter_init(&sbi->s_freeinodes_counter,
                                ext4_count_free_inodes(sb));
@@ -3494,7 +3587,7 @@ static int ext4_fill_super(struct super_block *sb, void *data, int silent)
                                ext4_count_dirs(sb));
        }
        if (!err) {
-                err = percpu_counter_init(&sbi->s_dirtyblocks_counter, 0);
+                err = percpu_counter_init(&sbi->s_dirtyclusters_counter, 0);
        }
        if (err) {
                ext4_msg(sb, KERN_ERR, "insufficient memory");
@@ -3609,13 +3702,13 @@ static int ext4_fill_super(struct super_block *sb, void *data, int silent)
         * The journal may have updated the bg summary counts, so we
         * need to update the global counters.
         */
-        percpu_counter_set(&sbi->s_freeblocks_counter,
+        percpu_counter_set(&sbi->s_freeclusters_counter,
-                           ext4_count_free_blocks(sb));
+                           ext4_count_free_clusters(sb));
        percpu_counter_set(&sbi->s_freeinodes_counter,
                           ext4_count_free_inodes(sb));
        percpu_counter_set(&sbi->s_dirs_counter,
                           ext4_count_dirs(sb));
-        percpu_counter_set(&sbi->s_dirtyblocks_counter, 0);
+        percpu_counter_set(&sbi->s_dirtyclusters_counter, 0);
 no_journal:
        /*
@@ -3679,25 +3772,6 @@ no_journal:
                         "available");
        }
-        if (test_opt(sb, DELALLOC) &&
-            (test_opt(sb, DATA_FLAGS) == EXT4_MOUNT_JOURNAL_DATA)) {
-                ext4_msg(sb, KERN_WARNING, "Ignoring delalloc option - "
-                         "requested data journaling mode");
-                clear_opt(sb, DELALLOC);
-        }
-        if (test_opt(sb, DIOREAD_NOLOCK)) {
-                if (test_opt(sb, DATA_FLAGS) == EXT4_MOUNT_JOURNAL_DATA) {
-                        ext4_msg(sb, KERN_WARNING, "Ignoring dioread_nolock "
-                                "option - requested data journaling mode");
-                        clear_opt(sb, DIOREAD_NOLOCK);
-                }
-                if (sb->s_blocksize < PAGE_SIZE) {
-                        ext4_msg(sb, KERN_WARNING, "Ignoring dioread_nolock "
-                                "option - block size is too small");
-                        clear_opt(sb, DIOREAD_NOLOCK);
-                }
-        }
        err = ext4_setup_system_zone(sb);
        if (err) {
                ext4_msg(sb, KERN_ERR, "failed to initialize system "
@@ -3710,22 +3784,19 @@ no_journal:
        if (err) {
                ext4_msg(sb, KERN_ERR, "failed to initialize mballoc (%d)",
                         err);
-                goto failed_mount4;
+                goto failed_mount5;
        }
        err = ext4_register_li_request(sb, first_not_zeroed);
        if (err)
-                goto failed_mount4;
+                goto failed_mount6;
        sbi->s_kobj.kset = ext4_kset;
        init_completion(&sbi->s_kobj_unregister);
        err = kobject_init_and_add(&sbi->s_kobj, &ext4_ktype, NULL,
                                   "%s", sb->s_id);
-        if (err) {
+        if (err)
-                ext4_mb_release(sb);
+                goto failed_mount7;
-                ext4_ext_release(sb);
-                goto failed_mount4;
-        };
        EXT4_SB(sb)->s_mount_state |= EXT4_ORPHAN_FS;
        ext4_orphan_cleanup(sb, es);
@@ -3759,13 +3830,19 @@ cantfind_ext4:
                ext4_msg(sb, KERN_ERR, "VFS: Can't find ext4 filesystem");
        goto failed_mount;
+failed_mount7:
+        ext4_unregister_li_request(sb);
+failed_mount6:
+        ext4_ext_release(sb);
+failed_mount5:
+        ext4_mb_release(sb);
+        ext4_release_system_zone(sb);
 failed_mount4:
        iput(root);
        sb->s_root = NULL;
        ext4_msg(sb, KERN_ERR, "mount failed");
        destroy_workqueue(EXT4_SB(sb)->dio_unwritten_wq);
 failed_mount_wq:
-        ext4_release_system_zone(sb);
        if (sbi->s_journal) {
                jbd2_journal_destroy(sbi->s_journal);
                sbi->s_journal = NULL;
@@ -3774,10 +3851,10 @@ failed_mount3:
        del_timer(&sbi->s_err_report);
        if (sbi->s_flex_groups)
                ext4_kvfree(sbi->s_flex_groups);
-        percpu_counter_destroy(&sbi->s_freeblocks_counter);
+        percpu_counter_destroy(&sbi->s_freeclusters_counter);
        percpu_counter_destroy(&sbi->s_freeinodes_counter);
        percpu_counter_destroy(&sbi->s_dirs_counter);
-        percpu_counter_destroy(&sbi->s_dirtyblocks_counter);
+        percpu_counter_destroy(&sbi->s_dirtyclusters_counter);
        if (sbi->s_mmp_tsk)
                kthread_stop(sbi->s_mmp_tsk);
 failed_mount2:
@@ -4064,7 +4141,7 @@ static int ext4_commit_super(struct super_block *sb, int sync)
        struct buffer_head *sbh = EXT4_SB(sb)->s_sbh;
        int error = 0;
-        if (!sbh)
+        if (!sbh || block_device_ejected(sb))
                return error;
        if (buffer_write_io_error(sbh)) {
                /*
@@ -4100,8 +4177,9 @@ static int ext4_commit_super(struct super_block *sb, int sync)
        else
                es->s_kbytes_written =
                        cpu_to_le64(EXT4_SB(sb)->s_kbytes_written);
-        ext4_free_blocks_count_set(es, percpu_counter_sum_positive(
+        ext4_free_blocks_count_set(es,
-                                           &EXT4_SB(sb)->s_freeblocks_counter));
+                        EXT4_C2B(EXT4_SB(sb), percpu_counter_sum_positive(
+                                &EXT4_SB(sb)->s_freeclusters_counter)));
        es->s_free_inodes_count =
                cpu_to_le32(percpu_counter_sum_positive(
                                &EXT4_SB(sb)->s_freeinodes_counter));
@@ -4506,16 +4584,34 @@ restore_opts:
        return err;
 }
+/*
+ * Note: calculating the overhead so we can be compatible with
+ * historical BSD practice is quite difficult in the face of
+ * clusters/bigalloc.  This is because multiple metadata blocks from
+ * different block group can end up in the same allocation cluster.
+ * Calculating the exact overhead in the face of clustered allocation
+ * requires either O(all block bitmaps) in memory or O(number of block
+ * groups**2) in time.  We will still calculate the superblock for
+ * older file systems --- and if we come across with a bigalloc file
+ * system with zero in s_overhead_clusters the estimate will be close to
+ * correct especially for very large cluster sizes --- but for newer
+ * file systems, it's better to calculate this figure once at mkfs
+ * time, and store it in the superblock.  If the superblock value is
+ * present (even for non-bigalloc file systems), we will use it.
+ */
 static int ext4_statfs(struct dentry *dentry, struct kstatfs *buf)
 {
        struct super_block *sb = dentry->d_sb;
        struct ext4_sb_info *sbi = EXT4_SB(sb);
        struct ext4_super_block *es = sbi->s_es;
+        struct ext4_group_desc *gdp;
        u64 fsid;
        s64 bfree;
        if (test_opt(sb, MINIX_DF)) {
                sbi->s_overhead_last = 0;
+        } else if (es->s_overhead_clusters) {
+                sbi->s_overhead_last = le32_to_cpu(es->s_overhead_clusters);
        } else if (sbi->s_blocks_last != ext4_blocks_count(es)) {
                ext4_group_t i, ngroups = ext4_get_groups_count(sb);
                ext4_fsblk_t overhead = 0;
@@ -4530,24 +4626,16 @@ static int ext4_statfs(struct dentry *dentry, struct kstatfs *buf)
                 * All of the blocks before first_data_block are
                 * overhead
                 */
-                overhead = le32_to_cpu(es->s_first_data_block);
+                overhead = EXT4_B2C(sbi, le32_to_cpu(es->s_first_data_block));
                /*
-                 * Add the overhead attributed to the superblock and
+                 * Add the overhead found in each block group
-                 * block group descriptors.  If the sparse superblocks
-                 * feature is turned on, then not all groups have this.
                 */
                for (i = 0; i < ngroups; i++) {
-                        overhead += ext4_bg_has_super(sb, i) +
+                        gdp = ext4_get_group_desc(sb, i, NULL);
-                                ext4_bg_num_gdb(sb, i);
+                        overhead += ext4_num_overhead_clusters(sb, i, gdp);
                        cond_resched();
                }
-                /*
-                 * Every block group has an inode bitmap, a block
-                 * bitmap, and an inode table.
-                 */
-                overhead += ngroups * (2 + sbi->s_itb_per_group);
                sbi->s_overhead_last = overhead;
                smp_wmb();
                sbi->s_blocks_last = ext4_blocks_count(es);
@@ -4555,11 +4643,12 @@ static int ext4_statfs(struct dentry *dentry, struct kstatfs *buf)
        buf->f_type = EXT4_SUPER_MAGIC;
        buf->f_bsize = sb->s_blocksize;
-        buf->f_blocks = ext4_blocks_count(es) - sbi->s_overhead_last;
+        buf->f_blocks = (ext4_blocks_count(es) -
-        bfree = percpu_counter_sum_positive(&sbi->s_freeblocks_counter) -
+                         EXT4_C2B(sbi, sbi->s_overhead_last));
-                       percpu_counter_sum_positive(&sbi->s_dirtyblocks_counter);
+        bfree = percpu_counter_sum_positive(&sbi->s_freeclusters_counter) -
+                percpu_counter_sum_positive(&sbi->s_dirtyclusters_counter);
        /* prevent underflow in case that few free space is available */
-        buf->f_bfree = max_t(s64, bfree, 0);
+        buf->f_bfree = EXT4_C2B(sbi, max_t(s64, bfree, 0));
        buf->f_bavail = buf->f_bfree - ext4_r_blocks_count(es);
        if (buf->f_bfree < ext4_r_blocks_count(es))
                buf->f_bavail = 0;
@@ -4980,13 +5069,11 @@ static int __init ext4_init_fs(void)
                return err;
        err = ext4_init_system_zone();
        if (err)
-                goto out7;
+                goto out6;
        ext4_kset = kset_create_and_add("ext4", NULL, fs_kobj);
        if (!ext4_kset)
-                goto out6;
-        ext4_proc_root = proc_mkdir("fs/ext4", NULL);
-        if (!ext4_proc_root)
                goto out5;
+        ext4_proc_root = proc_mkdir("fs/ext4", NULL);
        err = ext4_init_feat_adverts();
        if (err)
@@ -5022,12 +5109,12 @@ out2:
 out3:
        ext4_exit_feat_adverts();
 out4:
-        remove_proc_entry("fs/ext4", NULL);
+        if (ext4_proc_root)
-out5:
+                remove_proc_entry("fs/ext4", NULL);
        kset_unregister(ext4_kset);
-out6:
+out5:
        ext4_exit_system_zone();
-out7:
+out6:
        ext4_exit_pageio();
        return err;
 }
diff --git a/fs/ext4/xattr.c b/fs/ext4/xattr.c
index c757adc97250..93a00d89a220 100644
--- a/fs/ext4/xattr.c
+++ b/fs/ext4/xattr.c
@@ -820,8 +820,14 @@ inserted:
                        if (!(ext4_test_inode_flag(inode, EXT4_INODE_EXTENTS)))
                                goal = goal & EXT4_MAX_BLOCK_FILE_PHYS;
+                        /*
+                         * take i_data_sem because we will test
+                         * i_delalloc_reserved_flag in ext4_mb_new_blocks
+                         */
+                        down_read((&EXT4_I(inode)->i_data_sem));
                        block = ext4_new_meta_blocks(handle, inode, goal, 0,
                                                     NULL, &error);
+                        up_read((&EXT4_I(inode)->i_data_sem));
                        if (error)
                                goto cleanup;
@@ -985,11 +991,7 @@ ext4_xattr_set_handle(handle_t *handle, struct inode *inode, int name_index,
        no_expand = ext4_test_inode_state(inode, EXT4_STATE_NO_EXPAND);
        ext4_set_inode_state(inode, EXT4_STATE_NO_EXPAND);
-        error = ext4_get_inode_loc(inode, &is.iloc);
+        error = ext4_reserve_inode_write(handle, inode, &is.iloc);
-        if (error)
-                goto cleanup;
-        error = ext4_journal_get_write_access(handle, is.iloc.bh);
        if (error)
                goto cleanup;
diff --git a/fs/fat/inode.c b/fs/fat/inode.c
index 1726d7303047..808cac7edcfb 100644
--- a/fs/fat/inode.c
+++ b/fs/fat/inode.c
@@ -379,7 +379,7 @@ static int fat_fill_inode(struct inode *inode, struct msdos_dir_entry *de)
                        return error;
                MSDOS_I(inode)->mmu_private = inode->i_size;
-                inode->i_nlink = fat_subdirs(inode);
+                set_nlink(inode, fat_subdirs(inode));
        } else { /* not a directory */
                inode->i_generation |= 1;
                inode->i_mode = fat_make_mode(sbi, de->attr,
@@ -1233,7 +1233,7 @@ static int fat_read_root(struct inode *inode)
        fat_save_attrs(inode, ATTR_DIR);
        inode->i_mtime.tv_sec = inode->i_atime.tv_sec = inode->i_ctime.tv_sec = 0;
        inode->i_mtime.tv_nsec = inode->i_atime.tv_nsec = inode->i_ctime.tv_nsec = 0;
-        inode->i_nlink = fat_subdirs(inode)+2;
+        set_nlink(inode, fat_subdirs(inode)+2);
        return 0;
 }
diff --git a/fs/fat/namei_msdos.c b/fs/fat/namei_msdos.c
index 66e83b845455..216b419f30e2 100644
--- a/fs/fat/namei_msdos.c
+++ b/fs/fat/namei_msdos.c
@@ -387,7 +387,7 @@ static int msdos_mkdir(struct inode *dir, struct dentry *dentry, int mode)
                /* the directory was completed, just return a error */
                goto out;
        }
-        inode->i_nlink = 2;
+        set_nlink(inode, 2);
        inode->i_mtime = inode->i_atime = inode->i_ctime = ts;
        /* timestamp is already written, so mark_inode_dirty() is unneeded. */
diff --git a/fs/fat/namei_vfat.c b/fs/fat/namei_vfat.c
index bb3f29c3557b..a87a65663c25 100644
--- a/fs/fat/namei_vfat.c
+++ b/fs/fat/namei_vfat.c
@@ -900,7 +900,7 @@ static int vfat_mkdir(struct inode *dir, struct dentry *dentry, int mode)
                goto out;
        }
        inode->i_version++;
-        inode->i_nlink = 2;
+        set_nlink(inode, 2);
        inode->i_mtime = inode->i_atime = inode->i_ctime = ts;
        /* timestamp is already written, so mark_inode_dirty() is unneeded. */
diff --git a/fs/freevxfs/vxfs_inode.c b/fs/freevxfs/vxfs_inode.c
index 1a4311437a8b..7b2af5abe2fa 100644
--- a/fs/freevxfs/vxfs_inode.c
+++ b/fs/freevxfs/vxfs_inode.c
@@ -227,7 +227,7 @@ vxfs_iinit(struct inode *ip, struct vxfs_inode_info *vip)
        ip->i_uid = (uid_t)vip->vii_uid;
        ip->i_gid = (gid_t)vip->vii_gid;
-        ip->i_nlink = vip->vii_nlink;
+        set_nlink(ip, vip->vii_nlink);
        ip->i_size = vip->vii_size;
        ip->i_atime.tv_sec = vip->vii_atime;
diff --git a/fs/fuse/control.c b/fs/fuse/control.c
index 85542a7daf40..42593c587d48 100644
--- a/fs/fuse/control.c
+++ b/fs/fuse/control.c
@@ -231,7 +231,7 @@ static struct dentry *fuse_ctl_add_dentry(struct dentry *parent,
        if (iop)
                inode->i_op = iop;
        inode->i_fop = fop;
-        inode->i_nlink = nlink;
+        set_nlink(inode, nlink);
        inode->i_private = fc;
        d_add(dentry, inode);
        return dentry;
diff --git a/fs/fuse/inode.c b/fs/fuse/inode.c
index add96f6ffda5..3e6d72756479 100644
--- a/fs/fuse/inode.c
+++ b/fs/fuse/inode.c
@@ -151,7 +151,7 @@ void fuse_change_attributes_common(struct inode *inode, struct fuse_attr *attr,
        inode->i_ino     = attr->ino;
        inode->i_mode    = (inode->i_mode & S_IFMT) | (attr->mode & 07777);
-        inode->i_nlink   = attr->nlink;
+        set_nlink(inode, attr->nlink);
        inode->i_uid     = attr->uid;
        inode->i_gid     = attr->gid;
        inode->i_blocks  = attr->blocks;
diff --git a/fs/gfs2/glops.c b/fs/gfs2/glops.c
index 78418b4fa857..1656df7aacd2 100644
--- a/fs/gfs2/glops.c
+++ b/fs/gfs2/glops.c
@@ -299,7 +299,7 @@ static void gfs2_set_nlink(struct inode *inode, u32 nlink)
                if (nlink == 0)
                        clear_nlink(inode);
                else
-                        inode->i_nlink = nlink;
+                        set_nlink(inode, nlink);
        }
 }
diff --git a/fs/hfs/dir.c b/fs/hfs/dir.c
index b4d70b13be92..bce4eef91a06 100644
--- a/fs/hfs/dir.c
+++ b/fs/hfs/dir.c
@@ -198,7 +198,7 @@ static int hfs_create(struct inode *dir, struct dentry *dentry, int mode,
        res = hfs_cat_create(inode->i_ino, dir, &dentry->d_name, inode);
        if (res) {
-                inode->i_nlink = 0;
+                clear_nlink(inode);
                hfs_delete_inode(inode);
                iput(inode);
                return res;
@@ -227,7 +227,7 @@ static int hfs_mkdir(struct inode *dir, struct dentry *dentry, int mode)
        res = hfs_cat_create(inode->i_ino, dir, &dentry->d_name, inode);
        if (res) {
-                inode->i_nlink = 0;
+                clear_nlink(inode);
                hfs_delete_inode(inode);
                iput(inode);
                return res;
diff --git a/fs/hfs/inode.c b/fs/hfs/inode.c
index 96a1b625fc74..a1a9fdcd2a00 100644
--- a/fs/hfs/inode.c
+++ b/fs/hfs/inode.c
@@ -183,7 +183,7 @@ struct inode *hfs_new_inode(struct inode *dir, struct qstr *name, int mode)
        inode->i_mode = mode;
        inode->i_uid = current_fsuid();
        inode->i_gid = current_fsgid();
-        inode->i_nlink = 1;
+        set_nlink(inode, 1);
        inode->i_mtime = inode->i_atime = inode->i_ctime = CURRENT_TIME_SEC;
        HFS_I(inode)->flags = 0;
        HFS_I(inode)->rsrc_inode = NULL;
@@ -313,7 +313,7 @@ static int hfs_read_inode(struct inode *inode, void *data)
        /* Initialize the inode */
        inode->i_uid = hsb->s_uid;
        inode->i_gid = hsb->s_gid;
-        inode->i_nlink = 1;
+        set_nlink(inode, 1);
        if (idata->key)
                HFS_I(inode)->cat_key = *idata->key;
diff --git a/fs/hfsplus/dir.c b/fs/hfsplus/dir.c
index 25b2443a004c..4536cd3f15ae 100644
--- a/fs/hfsplus/dir.c
+++ b/fs/hfsplus/dir.c
@@ -415,7 +415,7 @@ static int hfsplus_symlink(struct inode *dir, struct dentry *dentry,
        goto out;
 out_err:
-        inode->i_nlink = 0;
+        clear_nlink(inode);
        hfsplus_delete_inode(inode);
        iput(inode);
 out:
@@ -440,7 +440,7 @@ static int hfsplus_mknod(struct inode *dir, struct dentry *dentry,
        res = hfsplus_create_cat(inode->i_ino, dir, &dentry->d_name, inode);
        if (res) {
-                inode->i_nlink = 0;
+                clear_nlink(inode);
                hfsplus_delete_inode(inode);
                iput(inode);
                goto out;
diff --git a/fs/hfsplus/inode.c b/fs/hfsplus/inode.c
index 4cc1e3a36ec7..40e1413be4cf 100644
--- a/fs/hfsplus/inode.c
+++ b/fs/hfsplus/inode.c
@@ -391,7 +391,7 @@ struct inode *hfsplus_new_inode(struct super_block *sb, int mode)
        inode->i_mode = mode;
        inode->i_uid = current_fsuid();
        inode->i_gid = current_fsgid();
-        inode->i_nlink = 1;
+        set_nlink(inode, 1);
        inode->i_mtime = inode->i_atime = inode->i_ctime = CURRENT_TIME_SEC;
        hip = HFSPLUS_I(inode);
@@ -512,7 +512,7 @@ int hfsplus_cat_read_inode(struct inode *inode, struct hfs_find_data *fd)
                hfs_bnode_read(fd->bnode, &entry, fd->entryoffset,
                                        sizeof(struct hfsplus_cat_folder));
                hfsplus_get_perms(inode, &folder->permissions, 1);
-                inode->i_nlink = 1;
+                set_nlink(inode, 1);
                inode->i_size = 2 + be32_to_cpu(folder->valence);
                inode->i_atime = hfsp_mt2ut(folder->access_date);
                inode->i_mtime = hfsp_mt2ut(folder->content_mod_date);
@@ -532,11 +532,11 @@ int hfsplus_cat_read_inode(struct inode *inode, struct hfs_find_data *fd)
                hfsplus_inode_read_fork(inode, HFSPLUS_IS_RSRC(inode) ?
                                        &file->rsrc_fork : &file->data_fork);
                hfsplus_get_perms(inode, &file->permissions, 0);
-                inode->i_nlink = 1;
+                set_nlink(inode, 1);
                if (S_ISREG(inode->i_mode)) {
                        if (file->permissions.dev)
-                                inode->i_nlink =
+                                set_nlink(inode,
-                                        be32_to_cpu(file->permissions.dev);
+                                          be32_to_cpu(file->permissions.dev));
                        inode->i_op = &hfsplus_file_inode_operations;
                        inode->i_fop = &hfsplus_file_operations;
                        inode->i_mapping->a_ops = &hfsplus_aops;
diff --git a/fs/hostfs/hostfs_kern.c b/fs/hostfs/hostfs_kern.c
index 0d22afdd4611..2f72da5ae686 100644
--- a/fs/hostfs/hostfs_kern.c
+++ b/fs/hostfs/hostfs_kern.c
@@ -541,7 +541,7 @@ static int read_name(struct inode *ino, char *name)
        ino->i_ino = st.ino;
        ino->i_mode = st.mode;
-        ino->i_nlink = st.nlink;
+        set_nlink(ino, st.nlink);
        ino->i_uid = st.uid;
        ino->i_gid = st.gid;
        ino->i_atime = st.atime;
diff --git a/fs/hostfs/hostfs_user.c b/fs/hostfs/hostfs_user.c
index d51a98384bc0..dd7bc38a3825 100644
--- a/fs/hostfs/hostfs_user.c
+++ b/fs/hostfs/hostfs_user.c
@@ -16,7 +16,6 @@
 #include <sys/vfs.h>
 #include "hostfs.h"
 #include "os.h"
-#include "user.h"
 #include <utime.h>
 static void stat64_to_hostfs(const struct stat64 *buf, struct hostfs_stat *p)
diff --git a/fs/hpfs/dir.c b/fs/hpfs/dir.c
index 96a8ed91cedd..2fa0089a02a8 100644
--- a/fs/hpfs/dir.c
+++ b/fs/hpfs/dir.c
@@ -247,7 +247,7 @@ struct dentry *hpfs_lookup(struct inode *dir, struct dentry *dentry, struct name
                        result->i_mode &= ~0111;
                        result->i_op = &hpfs_file_iops;
                        result->i_fop = &hpfs_file_ops;
-                        result->i_nlink = 1;
+                        set_nlink(result, 1);
                }
                unlock_new_inode(result);
        }
diff --git a/fs/hpfs/inode.c b/fs/hpfs/inode.c
index 338cd8368451..3b2cec29972b 100644
--- a/fs/hpfs/inode.c
+++ b/fs/hpfs/inode.c
@@ -53,7 +53,7 @@ void hpfs_read_inode(struct inode *i)
                i->i_mode &= ~0111;
                i->i_op = &hpfs_file_iops;
                i->i_fop = &hpfs_file_ops;
-                i->i_nlink = 0;*/
+                clear_nlink(i);*/
                make_bad_inode(i);
                return;
        }
@@ -77,7 +77,7 @@ void hpfs_read_inode(struct inode *i)
                        i->i_mode = S_IFLNK | 0777;
                        i->i_op = &page_symlink_inode_operations;
                        i->i_data.a_ops = &hpfs_symlink_aops;
-                        i->i_nlink = 1;
+                        set_nlink(i, 1);
                        i->i_size = ea_size;
                        i->i_blocks = 1;
                        brelse(bh);
@@ -101,7 +101,7 @@ void hpfs_read_inode(struct inode *i)
                        }
                        if (S_ISBLK(mode) || S_ISCHR(mode) || S_ISFIFO(mode) || S_ISSOCK(mode)) {
                                brelse(bh);
-                                i->i_nlink = 1;
+                                set_nlink(i, 1);
                                i->i_size = 0;
                                i->i_blocks = 1;
                                init_special_inode(i, mode,
@@ -125,13 +125,13 @@ void hpfs_read_inode(struct inode *i)
                hpfs_count_dnodes(i->i_sb, hpfs_inode->i_dno, &n_dnodes, &n_subdirs, NULL);
                i->i_blocks = 4 * n_dnodes;
                i->i_size = 2048 * n_dnodes;
-                i->i_nlink = 2 + n_subdirs;
+                set_nlink(i, 2 + n_subdirs);
        } else {
                i->i_mode |= S_IFREG;
                if (!hpfs_inode->i_ea_mode) i->i_mode &= ~0111;
                i->i_op = &hpfs_file_iops;
                i->i_fop = &hpfs_file_ops;
-                i->i_nlink = 1;
+                set_nlink(i, 1);
                i->i_size = le32_to_cpu(fnode->file_size);
                i->i_blocks = ((i->i_size + 511) >> 9) + 1;
                i->i_data.a_ops = &hpfs_aops;
diff --git a/fs/hpfs/namei.c b/fs/hpfs/namei.c
index 2df69e2f07cf..ea91fcb0ef9b 100644
--- a/fs/hpfs/namei.c
+++ b/fs/hpfs/namei.c
@@ -56,7 +56,7 @@ static int hpfs_mkdir(struct inode *dir, struct dentry *dentry, int mode)
        result->i_fop = &hpfs_dir_ops;
        result->i_blocks = 4;
        result->i_size = 2048;
-        result->i_nlink = 2;
+        set_nlink(result, 2);
        if (dee.read_only)
                result->i_mode &= ~0222;
@@ -150,7 +150,7 @@ static int hpfs_create(struct inode *dir, struct dentry *dentry, int mode, struc
        result->i_mode &= ~0111;
        result->i_op = &hpfs_file_iops;
        result->i_fop = &hpfs_file_ops;
-        result->i_nlink = 1;
+        set_nlink(result, 1);
        hpfs_i(result)->i_parent_dir = dir->i_ino;
        result->i_ctime.tv_sec = result->i_mtime.tv_sec = result->i_atime.tv_sec = local_to_gmt(dir->i_sb, le32_to_cpu(dee.creation_date));
        result->i_ctime.tv_nsec = 0;
@@ -242,7 +242,7 @@ static int hpfs_mknod(struct inode *dir, struct dentry *dentry, int mode, dev_t
        hpfs_i(result)->i_ea_size = 0;
        result->i_uid = current_fsuid();
        result->i_gid = current_fsgid();
-        result->i_nlink = 1;
+        set_nlink(result, 1);
        result->i_size = 0;
        result->i_blocks = 1;
        init_special_inode(result, mode, rdev);
@@ -318,7 +318,7 @@ static int hpfs_symlink(struct inode *dir, struct dentry *dentry, const char *sy
        result->i_uid = current_fsuid();
        result->i_gid = current_fsgid();
        result->i_blocks = 1;
-        result->i_nlink = 1;
+        set_nlink(result, 1);
        result->i_size = strlen(symlink);
        result->i_op = &page_symlink_inode_operations;
        result->i_data.a_ops = &hpfs_symlink_aops;
diff --git a/fs/hppfs/hppfs.c b/fs/hppfs/hppfs.c
index 970ea987b3f6..f590b1160c6c 100644
--- a/fs/hppfs/hppfs.c
+++ b/fs/hppfs/hppfs.c
@@ -702,7 +702,7 @@ static struct inode *get_inode(struct super_block *sb, struct dentry *dentry)
        inode->i_ctime = proc_ino->i_ctime;
        inode->i_ino = proc_ino->i_ino;
        inode->i_mode = proc_ino->i_mode;
-        inode->i_nlink = proc_ino->i_nlink;
+        set_nlink(inode, proc_ino->i_nlink);
        inode->i_size = proc_ino->i_size;
        inode->i_blocks = proc_ino->i_blocks;
diff --git a/fs/hugetlbfs/inode.c b/fs/hugetlbfs/inode.c
index ec889538e5a6..0be5a78598d0 100644
--- a/fs/hugetlbfs/inode.c
+++ b/fs/hugetlbfs/inode.c
@@ -970,7 +970,7 @@ struct file *hugetlb_file_setup(const char *name, size_t size,
        d_instantiate(path.dentry, inode);
        inode->i_size = size;
-        inode->i_nlink = 0;
+        clear_nlink(inode);
        error = -ENFILE;
        file = alloc_file(&path, FMODE_WRITE | FMODE_READ,
diff --git a/fs/inode.c b/fs/inode.c
index ecbb68dc7e2a..ee4e66b998f4 100644
--- a/fs/inode.c
+++ b/fs/inode.c
@@ -142,7 +142,7 @@ int inode_init_always(struct super_block *sb, struct inode *inode)
        atomic_set(&inode->i_count, 1);
        inode->i_op = &empty_iops;
        inode->i_fop = &empty_fops;
-        inode->i_nlink = 1;
+        inode->__i_nlink = 1;
        inode->i_opflags = 0;
        inode->i_uid = 0;
        inode->i_gid = 0;
diff --git a/fs/isofs/inode.c b/fs/isofs/inode.c
index a5d03672d04e..562adabef985 100644
--- a/fs/isofs/inode.c
+++ b/fs/isofs/inode.c
@@ -1319,7 +1319,7 @@ static int isofs_read_inode(struct inode *inode)
                        inode->i_mode = S_IFDIR | sbi->s_dmode;
                else
                        inode->i_mode = S_IFDIR | S_IRUGO | S_IXUGO;
-                inode->i_nlink = 1;     /*
+                set_nlink(inode, 1);    /*
                                         * Set to 1.  We know there are 2, but
                                         * the find utility tries to optimize
                                         * if it is 2, and it screws up.  It is
@@ -1337,7 +1337,7 @@ static int isofs_read_inode(struct inode *inode)
                         */
                        inode->i_mode = S_IFREG | S_IRUGO | S_IXUGO;
                }
-                inode->i_nlink = 1;
+                set_nlink(inode, 1);
        }
        inode->i_uid = sbi->s_uid;
        inode->i_gid = sbi->s_gid;
diff --git a/fs/isofs/rock.c b/fs/isofs/rock.c
index 1fbc7de88f50..70e79d0c756a 100644
--- a/fs/isofs/rock.c
+++ b/fs/isofs/rock.c
@@ -363,7 +363,7 @@ repeat:
                        break;
                case SIG('P', 'X'):
                        inode->i_mode = isonum_733(rr->u.PX.mode);
-                        inode->i_nlink = isonum_733(rr->u.PX.n_links);
+                        set_nlink(inode, isonum_733(rr->u.PX.n_links));
                        inode->i_uid = isonum_733(rr->u.PX.uid);
                        inode->i_gid = isonum_733(rr->u.PX.gid);
                        break;
@@ -496,7 +496,7 @@ repeat:
                                goto out;
                        }
                        inode->i_mode = reloc->i_mode;
-                        inode->i_nlink = reloc->i_nlink;
+                        set_nlink(inode, reloc->i_nlink);
                        inode->i_uid = reloc->i_uid;
                        inode->i_gid = reloc->i_gid;
                        inode->i_rdev = reloc->i_rdev;
diff --git a/fs/jbd/journal.c b/fs/jbd/journal.c
index 9fe061fb8779..fea8dd661d2b 100644
--- a/fs/jbd/journal.c
+++ b/fs/jbd/journal.c
@@ -1135,6 +1135,14 @@ static int journal_get_superblock(journal_t *journal)
                goto out;
        }
+        if (be32_to_cpu(sb->s_first) == 0 ||
+            be32_to_cpu(sb->s_first) >= journal->j_maxlen) {
+                printk(KERN_WARNING
+                        "JBD: Invalid start block of journal: %u\n",
+                        be32_to_cpu(sb->s_first));
+                goto out;
+        }
        return 0;
 out:
diff --git a/fs/jbd2/commit.c b/fs/jbd2/commit.c
index eef6979821a4..68d704db787f 100644
--- a/fs/jbd2/commit.c
+++ b/fs/jbd2/commit.c
@@ -352,7 +352,7 @@ void jbd2_journal_commit_transaction(journal_t *journal)
        J_ASSERT(commit_transaction->t_state == T_RUNNING);
        trace_jbd2_start_commit(journal, commit_transaction);
-        jbd_debug(1, "JBD: starting commit of transaction %d\n",
+        jbd_debug(1, "JBD2: starting commit of transaction %d\n",
                        commit_transaction->t_tid);
        write_lock(&journal->j_state_lock);
@@ -427,7 +427,7 @@ void jbd2_journal_commit_transaction(journal_t *journal)
        __jbd2_journal_clean_checkpoint_list(journal);
        spin_unlock(&journal->j_list_lock);
-        jbd_debug (3, "JBD: commit phase 1\n");
+        jbd_debug(3, "JBD2: commit phase 1\n");
        /*
         * Switch to a new revoke table.
@@ -447,7 +447,7 @@ void jbd2_journal_commit_transaction(journal_t *journal)
        wake_up(&journal->j_wait_transaction_locked);
        write_unlock(&journal->j_state_lock);
-        jbd_debug (3, "JBD: commit phase 2\n");
+        jbd_debug(3, "JBD2: commit phase 2\n");
        /*
         * Now start flushing things to disk, in the order they appear
@@ -462,7 +462,7 @@ void jbd2_journal_commit_transaction(journal_t *journal)
                                          WRITE_SYNC);
        blk_finish_plug(&plug);
-        jbd_debug(3, "JBD: commit phase 2\n");
+        jbd_debug(3, "JBD2: commit phase 2\n");
        /*
         * Way to go: we have now written out all of the data for a
@@ -522,7 +522,7 @@ void jbd2_journal_commit_transaction(journal_t *journal)
                        J_ASSERT (bufs == 0);
-                        jbd_debug(4, "JBD: get descriptor\n");
+                        jbd_debug(4, "JBD2: get descriptor\n");
                        descriptor = jbd2_journal_get_descriptor_buffer(journal);
                        if (!descriptor) {
@@ -531,7 +531,7 @@ void jbd2_journal_commit_transaction(journal_t *journal)
                        }
                        bh = jh2bh(descriptor);
-                        jbd_debug(4, "JBD: got buffer %llu (%p)\n",
+                        jbd_debug(4, "JBD2: got buffer %llu (%p)\n",
                                (unsigned long long)bh->b_blocknr, bh->b_data);
                        header = (journal_header_t *)&bh->b_data[0];
                        header->h_magic     = cpu_to_be32(JBD2_MAGIC_NUMBER);
@@ -625,7 +625,7 @@ void jbd2_journal_commit_transaction(journal_t *journal)
                    commit_transaction->t_buffers == NULL ||
                    space_left < tag_bytes + 16) {
-                        jbd_debug(4, "JBD: Submit %d IOs\n", bufs);
+                        jbd_debug(4, "JBD2: Submit %d IOs\n", bufs);
                        /* Write an end-of-descriptor marker before
                           submitting the IOs.  "tag" still points to
@@ -707,7 +707,7 @@ start_journal_io:
           so we incur less scheduling load.
        */
-        jbd_debug(3, "JBD: commit phase 3\n");
+        jbd_debug(3, "JBD2: commit phase 3\n");
        /*
         * akpm: these are BJ_IO, and j_list_lock is not needed.
@@ -771,7 +771,7 @@ wait_for_iobuf:
        J_ASSERT (commit_transaction->t_shadow_list == NULL);
-        jbd_debug(3, "JBD: commit phase 4\n");
+        jbd_debug(3, "JBD2: commit phase 4\n");
        /* Here we wait for the revoke record and descriptor record buffers */
 wait_for_ctlbuf:
@@ -801,7 +801,7 @@ wait_for_iobuf:
        if (err)
                jbd2_journal_abort(journal, err);
-        jbd_debug(3, "JBD: commit phase 5\n");
+        jbd_debug(3, "JBD2: commit phase 5\n");
        write_lock(&journal->j_state_lock);
        J_ASSERT(commit_transaction->t_state == T_COMMIT_DFLUSH);
        commit_transaction->t_state = T_COMMIT_JFLUSH;
@@ -830,7 +830,7 @@ wait_for_iobuf:
           transaction can be removed from any checkpoint list it was on
           before. */
-        jbd_debug(3, "JBD: commit phase 6\n");
+        jbd_debug(3, "JBD2: commit phase 6\n");
        J_ASSERT(list_empty(&commit_transaction->t_inode_list));
        J_ASSERT(commit_transaction->t_buffers == NULL);
@@ -964,7 +964,7 @@ restart_loop:
        /* Done with this transaction! */
-        jbd_debug(3, "JBD: commit phase 7\n");
+        jbd_debug(3, "JBD2: commit phase 7\n");
        J_ASSERT(commit_transaction->t_state == T_COMMIT_JFLUSH);
@@ -1039,7 +1039,7 @@ restart_loop:
                journal->j_commit_callback(journal, commit_transaction);
        trace_jbd2_end_commit(journal, commit_transaction);
-        jbd_debug(1, "JBD: commit %d complete, head %d\n",
+        jbd_debug(1, "JBD2: commit %d complete, head %d\n",
                  journal->j_commit_sequence, journal->j_tail_sequence);
        if (to_free)
                kfree(commit_transaction);
diff --git a/fs/jbd2/journal.c b/fs/jbd2/journal.c
index f24df13adc4e..0fa0123151d3 100644
--- a/fs/jbd2/journal.c
+++ b/fs/jbd2/journal.c
@@ -491,7 +491,7 @@ int __jbd2_log_start_commit(journal_t *journal, tid_t target)
                 */
                journal->j_commit_request = target;
-                jbd_debug(1, "JBD: requesting commit %d/%d\n",
+                jbd_debug(1, "JBD2: requesting commit %d/%d\n",
                          journal->j_commit_request,
                          journal->j_commit_sequence);
                wake_up(&journal->j_wait_commit);
@@ -500,7 +500,7 @@ int __jbd2_log_start_commit(journal_t *journal, tid_t target)
                /* This should never happen, but if it does, preserve
                   the evidence before kjournald goes into a loop and
                   increments j_commit_sequence beyond all recognition. */
-                WARN_ONCE(1, "jbd: bad log_start_commit: %u %u %u %u\n",
+                WARN_ONCE(1, "JBD2: bad log_start_commit: %u %u %u %u\n",
                          journal->j_commit_request,
                          journal->j_commit_sequence,
                          target, journal->j_running_transaction ? 
@@ -645,7 +645,7 @@ int jbd2_log_wait_commit(journal_t *journal, tid_t tid)
        }
 #endif
        while (tid_gt(tid, journal->j_commit_sequence)) {
-                jbd_debug(1, "JBD: want %d, j_commit_sequence=%d\n",
+                jbd_debug(1, "JBD2: want %d, j_commit_sequence=%d\n",
                                  tid, journal->j_commit_sequence);
                wake_up(&journal->j_wait_commit);
                read_unlock(&journal->j_state_lock);
@@ -1093,7 +1093,7 @@ static int journal_reset(journal_t *journal)
        first = be32_to_cpu(sb->s_first);
        last = be32_to_cpu(sb->s_maxlen);
        if (first + JBD2_MIN_JOURNAL_BLOCKS > last + 1) {
-                printk(KERN_ERR "JBD: Journal too short (blocks %llu-%llu).\n",
+                printk(KERN_ERR "JBD2: Journal too short (blocks %llu-%llu).\n",
                       first, last);
                journal_fail_superblock(journal);
                return -EINVAL;
@@ -1139,7 +1139,7 @@ void jbd2_journal_update_superblock(journal_t *journal, int wait)
         */
        if (sb->s_start == 0 && journal->j_tail_sequence ==
                                journal->j_transaction_sequence) {
-                jbd_debug(1,"JBD: Skipping superblock update on recovered sb "
+                jbd_debug(1, "JBD2: Skipping superblock update on recovered sb "
                        "(start %ld, seq %d, errno %d)\n",
                        journal->j_tail, journal->j_tail_sequence,
                        journal->j_errno);
@@ -1163,7 +1163,7 @@ void jbd2_journal_update_superblock(journal_t *journal, int wait)
        }
        read_lock(&journal->j_state_lock);
-        jbd_debug(1,"JBD: updating superblock (start %ld, seq %d, errno %d)\n",
+        jbd_debug(1, "JBD2: updating superblock (start %ld, seq %d, errno %d)\n",
                  journal->j_tail, journal->j_tail_sequence, journal->j_errno);
        sb->s_sequence = cpu_to_be32(journal->j_tail_sequence);
@@ -1216,8 +1216,8 @@ static int journal_get_superblock(journal_t *journal)
                ll_rw_block(READ, 1, &bh);
                wait_on_buffer(bh);
                if (!buffer_uptodate(bh)) {
-                        printk (KERN_ERR
+                        printk(KERN_ERR
-                                "JBD: IO error reading journal superblock\n");
+                                "JBD2: IO error reading journal superblock\n");
                        goto out;
                }
        }
@@ -1228,7 +1228,7 @@ static int journal_get_superblock(journal_t *journal)
        if (sb->s_header.h_magic != cpu_to_be32(JBD2_MAGIC_NUMBER) ||
            sb->s_blocksize != cpu_to_be32(journal->j_blocksize)) {
-                printk(KERN_WARNING "JBD: no valid journal superblock found\n");
+                printk(KERN_WARNING "JBD2: no valid journal superblock found\n");
                goto out;
        }
@@ -1240,14 +1240,22 @@ static int journal_get_superblock(journal_t *journal)
                journal->j_format_version = 2;
                break;
        default:
-                printk(KERN_WARNING "JBD: unrecognised superblock format ID\n");
+                printk(KERN_WARNING "JBD2: unrecognised superblock format ID\n");
                goto out;
        }
        if (be32_to_cpu(sb->s_maxlen) < journal->j_maxlen)
                journal->j_maxlen = be32_to_cpu(sb->s_maxlen);
        else if (be32_to_cpu(sb->s_maxlen) > journal->j_maxlen) {
-                printk (KERN_WARNING "JBD: journal file too short\n");
+                printk(KERN_WARNING "JBD2: journal file too short\n");
+                goto out;
+        }
+        if (be32_to_cpu(sb->s_first) == 0 ||
+            be32_to_cpu(sb->s_first) >= journal->j_maxlen) {
+                printk(KERN_WARNING
+                        "JBD2: Invalid start block of journal: %u\n",
+                        be32_to_cpu(sb->s_first));
                goto out;
        }
@@ -1310,8 +1318,8 @@ int jbd2_journal_load(journal_t *journal)
                     ~cpu_to_be32(JBD2_KNOWN_ROCOMPAT_FEATURES)) ||
                    (sb->s_feature_incompat &
                     ~cpu_to_be32(JBD2_KNOWN_INCOMPAT_FEATURES))) {
-                        printk (KERN_WARNING
+                        printk(KERN_WARNING
-                                "JBD: Unrecognised features on journal\n");
+                                "JBD2: Unrecognised features on journal\n");
                        return -EINVAL;
                }
        }
@@ -1346,7 +1354,7 @@ int jbd2_journal_load(journal_t *journal)
        return 0;
 recovery_error:
-        printk (KERN_WARNING "JBD: recovery failed\n");
+        printk(KERN_WARNING "JBD2: recovery failed\n");
        return -EIO;
 }
@@ -1577,7 +1585,7 @@ static int journal_convert_superblock_v1(journal_t *journal,
        struct buffer_head *bh;
        printk(KERN_WARNING
-                "JBD: Converting superblock from version 1 to 2.\n");
+                "JBD2: Converting superblock from version 1 to 2.\n");
        /* Pre-initialise new fields to zero */
        offset = ((char *) &(sb->s_feature_compat)) - ((char *) sb);
@@ -1694,7 +1702,7 @@ int jbd2_journal_wipe(journal_t *journal, int write)
        if (!journal->j_tail)
                goto no_recovery;
-        printk (KERN_WARNING "JBD: %s recovery information on journal\n",
+        printk(KERN_WARNING "JBD2: %s recovery information on journal\n",
                write ? "Clearing" : "Ignoring");
        err = jbd2_journal_skip_recovery(journal);
@@ -2020,7 +2028,7 @@ static int journal_init_jbd2_journal_head_cache(void)
        retval = 0;
        if (!jbd2_journal_head_cache) {
                retval = -ENOMEM;
-                printk(KERN_EMERG "JBD: no memory for journal_head cache\n");
+                printk(KERN_EMERG "JBD2: no memory for journal_head cache\n");
        }
        return retval;
 }
@@ -2383,7 +2391,7 @@ static void __exit journal_exit(void)
 #ifdef CONFIG_JBD2_DEBUG
        int n = atomic_read(&nr_journal_heads);
        if (n)
-                printk(KERN_EMERG "JBD: leaked %d journal_heads!\n", n);
+                printk(KERN_EMERG "JBD2: leaked %d journal_heads!\n", n);
 #endif
        jbd2_remove_debugfs_entry();
        jbd2_remove_jbd_stats_proc_entry();
diff --git a/fs/jbd2/recovery.c b/fs/jbd2/recovery.c
index 1cad869494f0..da6d7baf1390 100644
--- a/fs/jbd2/recovery.c
+++ b/fs/jbd2/recovery.c
@@ -89,7 +89,7 @@ static int do_readahead(journal_t *journal, unsigned int start)
                err = jbd2_journal_bmap(journal, next, &blocknr);
                if (err) {
-                        printk (KERN_ERR "JBD: bad block at offset %u\n",
+                        printk(KERN_ERR "JBD2: bad block at offset %u\n",
                                next);
                        goto failed;
                }
@@ -138,14 +138,14 @@ static int jread(struct buffer_head **bhp, journal_t *journal,
        *bhp = NULL;
        if (offset >= journal->j_maxlen) {
-                printk(KERN_ERR "JBD: corrupted journal superblock\n");
+                printk(KERN_ERR "JBD2: corrupted journal superblock\n");
                return -EIO;
        }
        err = jbd2_journal_bmap(journal, offset, &blocknr);
        if (err) {
-                printk (KERN_ERR "JBD: bad block at offset %u\n",
+                printk(KERN_ERR "JBD2: bad block at offset %u\n",
                        offset);
                return err;
        }
@@ -163,7 +163,7 @@ static int jread(struct buffer_head **bhp, journal_t *journal,
        }
        if (!buffer_uptodate(bh)) {
-                printk (KERN_ERR "JBD: Failed to read block at offset %u\n",
+                printk(KERN_ERR "JBD2: Failed to read block at offset %u\n",
                        offset);
                brelse(bh);
                return -EIO;
@@ -251,10 +251,10 @@ int jbd2_journal_recover(journal_t *journal)
        if (!err)
                err = do_one_pass(journal, &info, PASS_REPLAY);
-        jbd_debug(1, "JBD: recovery, exit status %d, "
+        jbd_debug(1, "JBD2: recovery, exit status %d, "
                  "recovered transactions %u to %u\n",
                  err, info.start_transaction, info.end_transaction);
-        jbd_debug(1, "JBD: Replayed %d and revoked %d/%d blocks\n",
+        jbd_debug(1, "JBD2: Replayed %d and revoked %d/%d blocks\n",
                  info.nr_replays, info.nr_revoke_hits, info.nr_revokes);
        /* Restart the log at the next transaction ID, thus invalidating
@@ -293,14 +293,14 @@ int jbd2_journal_skip_recovery(journal_t *journal)
        err = do_one_pass(journal, &info, PASS_SCAN);
        if (err) {
-                printk(KERN_ERR "JBD: error %d scanning journal\n", err);
+                printk(KERN_ERR "JBD2: error %d scanning journal\n", err);
                ++journal->j_transaction_sequence;
        } else {
 #ifdef CONFIG_JBD2_DEBUG
                int dropped = info.end_transaction - 
                        be32_to_cpu(journal->j_superblock->s_sequence);
                jbd_debug(1,
-                          "JBD: ignoring %d transaction%s from the journal.\n",
+                          "JBD2: ignoring %d transaction%s from the journal.\n",
                          dropped, (dropped == 1) ? "" : "s");
 #endif
                journal->j_transaction_sequence = ++info.end_transaction;
@@ -338,7 +338,7 @@ static int calc_chksums(journal_t *journal, struct buffer_head *bh,
                wrap(journal, *next_log_block);
                err = jread(&obh, journal, io_block);
                if (err) {
-                        printk(KERN_ERR "JBD: IO error %d recovering block "
+                        printk(KERN_ERR "JBD2: IO error %d recovering block "
                                "%lu in log\n", err, io_block);
                        return 1;
                } else {
@@ -411,7 +411,7 @@ static int do_one_pass(journal_t *journal,
                 * either the next descriptor block or the final commit
                 * record. */
-                jbd_debug(3, "JBD: checking block %ld\n", next_log_block);
+                jbd_debug(3, "JBD2: checking block %ld\n", next_log_block);
                err = jread(&bh, journal, next_log_block);
                if (err)
                        goto failed;
@@ -491,8 +491,8 @@ static int do_one_pass(journal_t *journal,
                                        /* Recover what we can, but
                                         * report failure at the end. */
                                        success = err;
-                                        printk (KERN_ERR
+                                        printk(KERN_ERR
-                                                "JBD: IO error %d recovering "
+                                                "JBD2: IO error %d recovering "
                                                "block %ld in log\n",
                                                err, io_block);
                                } else {
@@ -520,7 +520,7 @@ static int do_one_pass(journal_t *journal,
                                                        journal->j_blocksize);
                                        if (nbh == NULL) {
                                                printk(KERN_ERR
-                                                       "JBD: Out of memory "
+                                                       "JBD2: Out of memory "
                                                       "during recovery.\n");
                                                err = -ENOMEM;
                                                brelse(bh);
@@ -689,7 +689,7 @@ static int do_one_pass(journal_t *journal,
                /* It's really bad news if different passes end up at
                 * different places (but possible due to IO errors). */
                if (info->end_transaction != next_commit_ID) {
-                        printk (KERN_ERR "JBD: recovery pass %d ended at "
+                        printk(KERN_ERR "JBD2: recovery pass %d ended at "
                                "transaction %u, expected %u\n",
                                pass, next_commit_ID, info->end_transaction);
                        if (!success)
diff --git a/fs/jbd2/transaction.c b/fs/jbd2/transaction.c
index 2d7109414cdd..a0e41a4c080e 100644
--- a/fs/jbd2/transaction.c
+++ b/fs/jbd2/transaction.c
@@ -27,6 +27,7 @@
 #include <linux/highmem.h>
 #include <linux/hrtimer.h>
 #include <linux/backing-dev.h>
+#include <linux/bug.h>
 #include <linux/module.h>
 static void __jbd2_journal_temp_unlink_buffer(struct journal_head *jh);
@@ -115,7 +116,7 @@ static inline void update_t_max_wait(transaction_t *transaction,
 */
 static int start_this_handle(journal_t *journal, handle_t *handle,
-                             int gfp_mask)
+                             gfp_t gfp_mask)
 {
        transaction_t   *transaction, *new_transaction = NULL;
        tid_t           tid;
@@ -124,7 +125,7 @@ static int start_this_handle(journal_t *journal, handle_t *handle,
        unsigned long ts = jiffies;
        if (nblocks > journal->j_max_transaction_buffers) {
-                printk(KERN_ERR "JBD: %s wants too many credits (%d > %d)\n",
+                printk(KERN_ERR "JBD2: %s wants too many credits (%d > %d)\n",
                       current->comm, nblocks,
                       journal->j_max_transaction_buffers);
                return -ENOSPC;
@@ -320,7 +321,7 @@ static handle_t *new_handle(int nblocks)
 * Return a pointer to a newly allocated handle, or an ERR_PTR() value
 * on failure.
 */
-handle_t *jbd2__journal_start(journal_t *journal, int nblocks, int gfp_mask)
+handle_t *jbd2__journal_start(journal_t *journal, int nblocks, gfp_t gfp_mask)
 {
        handle_t *handle = journal_current_handle();
        int err;
@@ -443,7 +444,7 @@ out:
 * transaction capabable of guaranteeing the requested number of
 * credits.
 */
-int jbd2__journal_restart(handle_t *handle, int nblocks, int gfp_mask)
+int jbd2__journal_restart(handle_t *handle, int nblocks, gfp_t gfp_mask)
 {
        transaction_t *transaction = handle->h_transaction;
        journal_t *journal = transaction->t_journal;
@@ -563,7 +564,7 @@ static void warn_dirty_buffer(struct buffer_head *bh)
        char b[BDEVNAME_SIZE];
        printk(KERN_WARNING
-               "JBD: Spotted dirty metadata buffer (dev = %s, blocknr = %llu). "
+               "JBD2: Spotted dirty metadata buffer (dev = %s, blocknr = %llu). "
               "There's a risk of filesystem corruption in case of system "
               "crash.\n",
               bdevname(bh->b_bdev, b), (unsigned long long)bh->b_blocknr);
@@ -1049,6 +1050,10 @@ void jbd2_buffer_abort_trigger(struct journal_head *jh,
 * mark dirty metadata which needs to be journaled as part of the current
 * transaction.
 *
+ * The buffer must have previously had jbd2_journal_get_write_access()
+ * called so that it has a valid journal_head attached to the buffer
+ * head.
+ *
 * The buffer is placed on the transaction's metadata list and is marked
 * as belonging to the transaction.
 *
@@ -1065,11 +1070,16 @@ int jbd2_journal_dirty_metadata(handle_t *handle, struct buffer_head *bh)
        transaction_t *transaction = handle->h_transaction;
        journal_t *journal = transaction->t_journal;
        struct journal_head *jh = bh2jh(bh);
+        int ret = 0;
        jbd_debug(5, "journal_head %p\n", jh);
        JBUFFER_TRACE(jh, "entry");
        if (is_handle_aborted(handle))
                goto out;
+        if (!buffer_jbd(bh)) {
+                ret = -EUCLEAN;
+                goto out;
+        }
        jbd_lock_bh_state(bh);
@@ -1093,8 +1103,20 @@ int jbd2_journal_dirty_metadata(handle_t *handle, struct buffer_head *bh)
         */
        if (jh->b_transaction == transaction && jh->b_jlist == BJ_Metadata) {
                JBUFFER_TRACE(jh, "fastpath");
-                J_ASSERT_JH(jh, jh->b_transaction ==
+                if (unlikely(jh->b_transaction !=
-                                        journal->j_running_transaction);
+                             journal->j_running_transaction)) {
+                        printk(KERN_EMERG "JBD: %s: "
+                               "jh->b_transaction (%llu, %p, %u) != "
+                               "journal->j_running_transaction (%p, %u)",
+                               journal->j_devname,
+                               (unsigned long long) bh->b_blocknr,
+                               jh->b_transaction,
+                               jh->b_transaction ? jh->b_transaction->t_tid : 0,
+                               journal->j_running_transaction,
+                               journal->j_running_transaction ?
+                               journal->j_running_transaction->t_tid : 0);
+                        ret = -EINVAL;
+                }
                goto out_unlock_bh;
        }
@@ -1108,9 +1130,32 @@ int jbd2_journal_dirty_metadata(handle_t *handle, struct buffer_head *bh)
         */
        if (jh->b_transaction != transaction) {
                JBUFFER_TRACE(jh, "already on other transaction");
-                J_ASSERT_JH(jh, jh->b_transaction ==
+                if (unlikely(jh->b_transaction !=
-                                        journal->j_committing_transaction);
+                             journal->j_committing_transaction)) {
-                J_ASSERT_JH(jh, jh->b_next_transaction == transaction);
+                        printk(KERN_EMERG "JBD: %s: "
+                               "jh->b_transaction (%llu, %p, %u) != "
+                               "journal->j_committing_transaction (%p, %u)",
+                               journal->j_devname,
+                               (unsigned long long) bh->b_blocknr,
+                               jh->b_transaction,
+                               jh->b_transaction ? jh->b_transaction->t_tid : 0,
+                               journal->j_committing_transaction,
+                               journal->j_committing_transaction ?
+                               journal->j_committing_transaction->t_tid : 0);
+                        ret = -EINVAL;
+                }
+                if (unlikely(jh->b_next_transaction != transaction)) {
+                        printk(KERN_EMERG "JBD: %s: "
+                               "jh->b_next_transaction (%llu, %p, %u) != "
+                               "transaction (%p, %u)",
+                               journal->j_devname,
+                               (unsigned long long) bh->b_blocknr,
+                               jh->b_next_transaction,
+                               jh->b_next_transaction ?
+                               jh->b_next_transaction->t_tid : 0,
+                               transaction, transaction->t_tid);
+                        ret = -EINVAL;
+                }
                /* And this case is illegal: we can't reuse another
                 * transaction's data buffer, ever. */
                goto out_unlock_bh;
@@ -1127,7 +1172,8 @@ out_unlock_bh:
        jbd_unlock_bh_state(bh);
 out:
        JBUFFER_TRACE(jh, "exit");
-        return 0;
+        WARN_ON(ret);   /* All errors are bugs, so dump the stack */
+        return ret;
 }
 /*
diff --git a/fs/jffs2/dir.c b/fs/jffs2/dir.c
index 9659b7c00468..be6169bd8acd 100644
--- a/fs/jffs2/dir.c
+++ b/fs/jffs2/dir.c
@@ -245,7 +245,7 @@ static int jffs2_unlink(struct inode *dir_i, struct dentry *dentry)
        ret = jffs2_do_unlink(c, dir_f, dentry->d_name.name,
                              dentry->d_name.len, dead_f, now);
        if (dead_f->inocache)
-                dentry->d_inode->i_nlink = dead_f->inocache->pino_nlink;
+                set_nlink(dentry->d_inode, dead_f->inocache->pino_nlink);
        if (!ret)
                dir_i->i_mtime = dir_i->i_ctime = ITIME(now);
        return ret;
@@ -278,7 +278,7 @@ static int jffs2_link (struct dentry *old_dentry, struct inode *dir_i, struct de
        if (!ret) {
                mutex_lock(&f->sem);
-                old_dentry->d_inode->i_nlink = ++f->inocache->pino_nlink;
+                set_nlink(old_dentry->d_inode, ++f->inocache->pino_nlink);
                mutex_unlock(&f->sem);
                d_instantiate(dentry, old_dentry->d_inode);
                dir_i->i_mtime = dir_i->i_ctime = ITIME(now);
@@ -497,7 +497,7 @@ static int jffs2_mkdir (struct inode *dir_i, struct dentry *dentry, int mode)
        f = JFFS2_INODE_INFO(inode);
        /* Directories get nlink 2 at start */
-        inode->i_nlink = 2;
+        set_nlink(inode, 2);
        /* but ic->pino_nlink is the parent ino# */
        f->inocache->pino_nlink = dir_i->i_ino;
diff --git a/fs/jffs2/fs.c b/fs/jffs2/fs.c
index bbcb9755dd2b..7286e44ac665 100644
--- a/fs/jffs2/fs.c
+++ b/fs/jffs2/fs.c
@@ -278,7 +278,7 @@ struct inode *jffs2_iget(struct super_block *sb, unsigned long ino)
        inode->i_mtime = ITIME(je32_to_cpu(latest_node.mtime));
        inode->i_ctime = ITIME(je32_to_cpu(latest_node.ctime));
-        inode->i_nlink = f->inocache->pino_nlink;
+        set_nlink(inode, f->inocache->pino_nlink);
        inode->i_blocks = (inode->i_size + 511) >> 9;
@@ -291,7 +291,7 @@ struct inode *jffs2_iget(struct super_block *sb, unsigned long ino)
        case S_IFDIR:
        {
                struct jffs2_full_dirent *fd;
-                inode->i_nlink = 2; /* parent and '.' */
+                set_nlink(inode, 2); /* parent and '.' */
                for (fd=f->dents; fd; fd = fd->next) {
                        if (fd->type == DT_DIR && fd->ino)
@@ -453,7 +453,7 @@ struct inode *jffs2_new_inode (struct inode *dir_i, umode_t mode, struct jffs2_r
                iput(inode);
                return ERR_PTR(ret);
        }
-        inode->i_nlink = 1;
+        set_nlink(inode, 1);
        inode->i_ino = je32_to_cpu(ri->ino);
        inode->i_mode = jemode_to_cpu(ri->mode);
        inode->i_gid = je16_to_cpu(ri->gid);
diff --git a/fs/jfs/jfs_imap.c b/fs/jfs/jfs_imap.c
index b78b2f978f04..1b6f15f191b3 100644
--- a/fs/jfs/jfs_imap.c
+++ b/fs/jfs/jfs_imap.c
@@ -457,7 +457,7 @@ struct inode *diReadSpecial(struct super_block *sb, ino_t inum, int secondary)
        /* read the page of fixed disk inode (AIT) in raw mode */
        mp = read_metapage(ip, address << sbi->l2nbperpage, PSIZE, 1);
        if (mp == NULL) {
-                ip->i_nlink = 1;        /* Don't want iput() deleting it */
+                set_nlink(ip, 1);       /* Don't want iput() deleting it */
                iput(ip);
                return (NULL);
        }
@@ -469,7 +469,7 @@ struct inode *diReadSpecial(struct super_block *sb, ino_t inum, int secondary)
        /* copy on-disk inode to in-memory inode */
        if ((copy_from_dinode(dp, ip)) != 0) {
                /* handle bad return by returning NULL for ip */
-                ip->i_nlink = 1;        /* Don't want iput() deleting it */
+                set_nlink(ip, 1);       /* Don't want iput() deleting it */
                iput(ip);
                /* release the page */
                release_metapage(mp);
@@ -3076,7 +3076,7 @@ static int copy_from_dinode(struct dinode * dip, struct inode *ip)
                                ip->i_mode |= 0001;
                }
        }
-        ip->i_nlink = le32_to_cpu(dip->di_nlink);
+        set_nlink(ip, le32_to_cpu(dip->di_nlink));
        jfs_ip->saved_uid = le32_to_cpu(dip->di_uid);
        if (sbi->uid == -1)
diff --git a/fs/jfs/jfs_inode.c b/fs/jfs/jfs_inode.c
index 2686531e235a..c1a3e603279c 100644
--- a/fs/jfs/jfs_inode.c
+++ b/fs/jfs/jfs_inode.c
@@ -157,7 +157,7 @@ fail_drop:
        dquot_drop(inode);
        inode->i_flags |= S_NOQUOTA;
 fail_unlock:
-        inode->i_nlink = 0;
+        clear_nlink(inode);
        unlock_new_inode(inode);
 fail_put:
        iput(inode);
diff --git a/fs/jfs/namei.c b/fs/jfs/namei.c
index e17545e15664..a112ad96e474 100644
--- a/fs/jfs/namei.c
+++ b/fs/jfs/namei.c
@@ -172,7 +172,7 @@ static int jfs_create(struct inode *dip, struct dentry *dentry, int mode,
        mutex_unlock(&JFS_IP(dip)->commit_mutex);
        if (rc) {
                free_ea_wmap(ip);
-                ip->i_nlink = 0;
+                clear_nlink(ip);
                unlock_new_inode(ip);
                iput(ip);
        } else {
@@ -292,7 +292,7 @@ static int jfs_mkdir(struct inode *dip, struct dentry *dentry, int mode)
                goto out3;
        }
-        ip->i_nlink = 2;        /* for '.' */
+        set_nlink(ip, 2);       /* for '.' */
        ip->i_op = &jfs_dir_inode_operations;
        ip->i_fop = &jfs_dir_operations;
@@ -311,7 +311,7 @@ static int jfs_mkdir(struct inode *dip, struct dentry *dentry, int mode)
        mutex_unlock(&JFS_IP(dip)->commit_mutex);
        if (rc) {
                free_ea_wmap(ip);
-                ip->i_nlink = 0;
+                clear_nlink(ip);
                unlock_new_inode(ip);
                iput(ip);
        } else {
@@ -844,7 +844,7 @@ static int jfs_link(struct dentry *old_dentry,
        rc = txCommit(tid, 2, &iplist[0], 0);
        if (rc) {
-                ip->i_nlink--; /* never instantiated */
+                drop_nlink(ip); /* never instantiated */
                iput(ip);
        } else
                d_instantiate(dentry, ip);
@@ -1048,7 +1048,7 @@ static int jfs_symlink(struct inode *dip, struct dentry *dentry,
        mutex_unlock(&JFS_IP(dip)->commit_mutex);
        if (rc) {
                free_ea_wmap(ip);
-                ip->i_nlink = 0;
+                clear_nlink(ip);
                unlock_new_inode(ip);
                iput(ip);
        } else {
@@ -1433,7 +1433,7 @@ static int jfs_mknod(struct inode *dir, struct dentry *dentry,
        mutex_unlock(&JFS_IP(dir)->commit_mutex);
        if (rc) {
                free_ea_wmap(ip);
-                ip->i_nlink = 0;
+                clear_nlink(ip);
                unlock_new_inode(ip);
                iput(ip);
        } else {
diff --git a/fs/jfs/super.c b/fs/jfs/super.c
index 06c8a67cbe76..a44eff076c17 100644
--- a/fs/jfs/super.c
+++ b/fs/jfs/super.c
@@ -485,7 +485,6 @@ static int jfs_fill_super(struct super_block *sb, void *data, int silent)
                goto out_unload;
        }
        inode->i_ino = 0;
-        inode->i_nlink = 1;
        inode->i_size = sb->s_bdev->bd_inode->i_size;
        inode->i_mapping->a_ops = &jfs_metapage_aops;
        insert_inode_hash(inode);
diff --git a/fs/libfs.c b/fs/libfs.c
index c18e9a1235b6..f6d411eef1e7 100644
--- a/fs/libfs.c
+++ b/fs/libfs.c
@@ -490,7 +490,7 @@ int simple_fill_super(struct super_block *s, unsigned long magic,
        inode->i_atime = inode->i_mtime = inode->i_ctime = CURRENT_TIME;
        inode->i_op = &simple_dir_inode_operations;
        inode->i_fop = &simple_dir_operations;
-        inode->i_nlink = 2;
+        set_nlink(inode, 2);
        root = d_alloc_root(inode);
        if (!root) {
                iput(inode);
@@ -510,8 +510,10 @@ int simple_fill_super(struct super_block *s, unsigned long magic,
                if (!dentry)
                        goto out;
                inode = new_inode(s);
-                if (!inode)
+                if (!inode) {
+                        dput(dentry);
                        goto out;
+                }
                inode->i_mode = S_IFREG | files->mode;
                inode->i_atime = inode->i_mtime = inode->i_ctime = CURRENT_TIME;
                inode->i_fop = files->ops;
diff --git a/fs/logfs/dir.c b/fs/logfs/dir.c
index b3ff3d894165..b7d7f67cee5a 100644
--- a/fs/logfs/dir.c
+++ b/fs/logfs/dir.c
@@ -197,7 +197,7 @@ static int logfs_remove_inode(struct inode *inode)
 {
        int ret;
-        inode->i_nlink--;
+        drop_nlink(inode);
        ret = write_inode(inode);
        LOGFS_BUG_ON(ret, inode->i_sb);
        return ret;
@@ -433,7 +433,7 @@ static int __logfs_create(struct inode *dir, struct dentry *dentry,
        ta = kzalloc(sizeof(*ta), GFP_KERNEL);
        if (!ta) {
-                inode->i_nlink--;
+                drop_nlink(inode);
                iput(inode);
                return -ENOMEM;
        }
@@ -456,7 +456,7 @@ static int __logfs_create(struct inode *dir, struct dentry *dentry,
                abort_transaction(inode, ta);
                li->li_flags |= LOGFS_IF_STILLBORN;
                /* FIXME: truncate symlink */
-                inode->i_nlink--;
+                drop_nlink(inode);
                iput(inode);
                goto out;
        }
@@ -563,7 +563,7 @@ static int logfs_link(struct dentry *old_dentry, struct inode *dir,
        inode->i_ctime = dir->i_ctime = dir->i_mtime = CURRENT_TIME;
        ihold(inode);
-        inode->i_nlink++;
+        inc_nlink(inode);
        mark_inode_dirty_sync(inode);
        return __logfs_create(dir, dentry, inode, NULL, 0);
diff --git a/fs/logfs/inode.c b/fs/logfs/inode.c
index edfea7a3a747..7e441ad5f792 100644
--- a/fs/logfs/inode.c
+++ b/fs/logfs/inode.c
@@ -93,7 +93,7 @@ static struct inode *__logfs_iget(struct super_block *sb, ino_t ino)
                /* inode->i_nlink == 0 can be true when called from
                 * block validator */
                /* set i_nlink to 0 to prevent caching */
-                inode->i_nlink = 0;
+                clear_nlink(inode);
                logfs_inode(inode)->li_flags |= LOGFS_IF_ZOMBIE;
                iget_failed(inode);
                if (!err)
@@ -199,7 +199,6 @@ static void logfs_init_inode(struct super_block *sb, struct inode *inode)
        inode->i_blocks = 0;
        inode->i_ctime  = CURRENT_TIME;
        inode->i_mtime  = CURRENT_TIME;
-        inode->i_nlink  = 1;
        li->li_refcount = 1;
        INIT_LIST_HEAD(&li->li_freeing_list);
diff --git a/fs/logfs/readwrite.c b/fs/logfs/readwrite.c
index d8d09380c7de..2ac4217b7901 100644
--- a/fs/logfs/readwrite.c
+++ b/fs/logfs/readwrite.c
@@ -126,7 +126,7 @@ static void logfs_disk_to_inode(struct logfs_disk_inode *di, struct inode*inode)
        inode->i_atime  = be64_to_timespec(di->di_atime);
        inode->i_ctime  = be64_to_timespec(di->di_ctime);
        inode->i_mtime  = be64_to_timespec(di->di_mtime);
-        inode->i_nlink  = be32_to_cpu(di->di_refcount);
+        set_nlink(inode, be32_to_cpu(di->di_refcount));
        inode->i_generation = be32_to_cpu(di->di_generation);
        switch (inode->i_mode & S_IFMT) {
diff --git a/fs/minix/inode.c b/fs/minix/inode.c
index e7d23e25bf1d..64cdcd662ffc 100644
--- a/fs/minix/inode.c
+++ b/fs/minix/inode.c
@@ -446,7 +446,7 @@ static struct inode *V1_minix_iget(struct inode *inode)
        inode->i_mode = raw_inode->i_mode;
        inode->i_uid = (uid_t)raw_inode->i_uid;
        inode->i_gid = (gid_t)raw_inode->i_gid;
-        inode->i_nlink = raw_inode->i_nlinks;
+        set_nlink(inode, raw_inode->i_nlinks);
        inode->i_size = raw_inode->i_size;
        inode->i_mtime.tv_sec = inode->i_atime.tv_sec = inode->i_ctime.tv_sec = raw_inode->i_time;
        inode->i_mtime.tv_nsec = 0;
@@ -479,7 +479,7 @@ static struct inode *V2_minix_iget(struct inode *inode)
        inode->i_mode = raw_inode->i_mode;
        inode->i_uid = (uid_t)raw_inode->i_uid;
        inode->i_gid = (gid_t)raw_inode->i_gid;
-        inode->i_nlink = raw_inode->i_nlinks;
+        set_nlink(inode, raw_inode->i_nlinks);
        inode->i_size = raw_inode->i_size;
        inode->i_mtime.tv_sec = raw_inode->i_mtime;
        inode->i_atime.tv_sec = raw_inode->i_atime;
diff --git a/fs/namei.c b/fs/namei.c
index 7657be4352bf..ac6d214da827 100644
--- a/fs/namei.c
+++ b/fs/namei.c
@@ -137,7 +137,7 @@ static int do_getname(const char __user *filename, char *page)
        return retval;
 }
-static char *getname_flags(const char __user * filename, int flags)
+static char *getname_flags(const char __user *filename, int flags, int *empty)
 {
        char *tmp, *result;
@@ -148,6 +148,8 @@ static char *getname_flags(const char __user * filename, int flags)
                result = tmp;
                if (retval < 0) {
+                        if (retval == -ENOENT && empty)
+                                *empty = 1;
                        if (retval != -ENOENT || !(flags & LOOKUP_EMPTY)) {
                                __putname(tmp);
                                result = ERR_PTR(retval);
@@ -160,7 +162,7 @@ static char *getname_flags(const char __user * filename, int flags)
 char *getname(const char __user * filename)
 {
-        return getname_flags(filename, 0);
+        return getname_flags(filename, 0, 0);
 }
 #ifdef CONFIG_AUDITSYSCALL
@@ -1798,11 +1800,11 @@ struct dentry *lookup_one_len(const char *name, struct dentry *base, int len)
        return __lookup_hash(&this, base, NULL);
 }
-int user_path_at(int dfd, const char __user *name, unsigned flags,
+int user_path_at_empty(int dfd, const char __user *name, unsigned flags,
-                 struct path *path)
+                 struct path *path, int *empty)
 {
        struct nameidata nd;
-        char *tmp = getname_flags(name, flags);
+        char *tmp = getname_flags(name, flags, empty);
        int err = PTR_ERR(tmp);
        if (!IS_ERR(tmp)) {
@@ -1816,6 +1818,12 @@ int user_path_at(int dfd, const char __user *name, unsigned flags,
        return err;
 }
+int user_path_at(int dfd, const char __user *name, unsigned flags,
+                 struct path *path)
+{
+        return user_path_at_empty(dfd, name, flags, path, 0);
+}
 static int user_path_parent(int dfd, const char __user *path,
                        struct nameidata *nd, char **name)
 {
diff --git a/fs/ncpfs/inode.c b/fs/ncpfs/inode.c
index 202f370526a7..5b5fa33b6b9d 100644
--- a/fs/ncpfs/inode.c
+++ b/fs/ncpfs/inode.c
@@ -228,7 +228,7 @@ static void ncp_set_attr(struct inode *inode, struct ncp_entry_info *nwinfo)
        DDPRINTK("ncp_read_inode: inode->i_mode = %u\n", inode->i_mode);
-        inode->i_nlink = 1;
+        set_nlink(inode, 1);
        inode->i_uid = server->m.uid;
        inode->i_gid = server->m.gid;
diff --git a/fs/nfs/inode.c b/fs/nfs/inode.c
index 4dc6d078f108..c07a55aec838 100644
--- a/fs/nfs/inode.c
+++ b/fs/nfs/inode.c
@@ -320,7 +320,7 @@ nfs_fhget(struct super_block *sb, struct nfs_fh *fh, struct nfs_fattr *fattr)
                memset(&inode->i_ctime, 0, sizeof(inode->i_ctime));
                inode->i_version = 0;
                inode->i_size = 0;
-                inode->i_nlink = 0;
+                clear_nlink(inode);
                inode->i_uid = -2;
                inode->i_gid = -2;
                inode->i_blocks = 0;
@@ -355,7 +355,7 @@ nfs_fhget(struct super_block *sb, struct nfs_fh *fh, struct nfs_fattr *fattr)
                                | NFS_INO_INVALID_DATA
                                | NFS_INO_REVAL_PAGECACHE;
                if (fattr->valid & NFS_ATTR_FATTR_NLINK)
-                        inode->i_nlink = fattr->nlink;
+                        set_nlink(inode, fattr->nlink);
                else if (nfs_server_capable(inode, NFS_CAP_NLINK))
                        nfsi->cache_validity |= NFS_INO_INVALID_ATTR;
                if (fattr->valid & NFS_ATTR_FATTR_OWNER)
@@ -1361,7 +1361,7 @@ static int nfs_update_inode(struct inode *inode, struct nfs_fattr *fattr)
                        invalid |= NFS_INO_INVALID_ATTR;
                        if (S_ISDIR(inode->i_mode))
                                invalid |= NFS_INO_INVALID_DATA;
-                        inode->i_nlink = fattr->nlink;
+                        set_nlink(inode, fattr->nlink);
                }
        } else if (server->caps & NFS_CAP_NLINK)
                invalid |= save_cache_validity & (NFS_INO_INVALID_ATTR
diff --git a/fs/nilfs2/inode.c b/fs/nilfs2/inode.c
index 666628b395f1..b50ffb72e5b3 100644
--- a/fs/nilfs2/inode.c
+++ b/fs/nilfs2/inode.c
@@ -354,7 +354,7 @@ struct inode *nilfs_new_inode(struct inode *dir, int mode)
 failed_acl:
 failed_bmap:
-        inode->i_nlink = 0;
+        clear_nlink(inode);
        iput(inode);  /* raw_inode will be deleted through
                         generic_delete_inode() */
        goto failed;
@@ -396,7 +396,7 @@ int nilfs_read_inode_common(struct inode *inode,
        inode->i_mode = le16_to_cpu(raw_inode->i_mode);
        inode->i_uid = (uid_t)le32_to_cpu(raw_inode->i_uid);
        inode->i_gid = (gid_t)le32_to_cpu(raw_inode->i_gid);
-        inode->i_nlink = le16_to_cpu(raw_inode->i_links_count);
+        set_nlink(inode, le16_to_cpu(raw_inode->i_links_count));
        inode->i_size = le64_to_cpu(raw_inode->i_size);
        inode->i_atime.tv_sec = le64_to_cpu(raw_inode->i_mtime);
        inode->i_ctime.tv_sec = le64_to_cpu(raw_inode->i_ctime);
diff --git a/fs/nilfs2/namei.c b/fs/nilfs2/namei.c
index a3141990061e..768982de10e4 100644
--- a/fs/nilfs2/namei.c
+++ b/fs/nilfs2/namei.c
@@ -289,7 +289,7 @@ static int nilfs_do_unlink(struct inode *dir, struct dentry *dentry)
                nilfs_warning(inode->i_sb, __func__,
                              "deleting nonexistent file (%lu), %d\n",
                              inode->i_ino, inode->i_nlink);
-                inode->i_nlink = 1;
+                set_nlink(inode, 1);
        }
        err = nilfs_delete_entry(de, page);
        if (err)
diff --git a/fs/ntfs/inode.c b/fs/ntfs/inode.c
index 1371487da955..97e2dacbc867 100644
--- a/fs/ntfs/inode.c
+++ b/fs/ntfs/inode.c
@@ -612,7 +612,7 @@ static int ntfs_read_locked_inode(struct inode *vi)
         * might be tricky due to vfs interactions. Need to think about this
         * some more when implementing the unlink command.
         */
-        vi->i_nlink = le16_to_cpu(m->link_count);
+        set_nlink(vi, le16_to_cpu(m->link_count));
        /*
         * FIXME: Reparse points can have the directory bit set even though
         * they would be S_IFLNK. Need to deal with this further below when we
@@ -634,7 +634,7 @@ static int ntfs_read_locked_inode(struct inode *vi)
                vi->i_mode &= ~vol->dmask;
                /* Things break without this kludge! */
                if (vi->i_nlink > 1)
-                        vi->i_nlink = 1;
+                        set_nlink(vi, 1);
        } else {
                vi->i_mode |= S_IFREG;
                /* Apply the file permissions mask set in the mount options. */
@@ -1242,7 +1242,7 @@ static int ntfs_read_locked_attr_inode(struct inode *base_vi, struct inode *vi)
        vi->i_version   = base_vi->i_version;
        vi->i_uid       = base_vi->i_uid;
        vi->i_gid       = base_vi->i_gid;
-        vi->i_nlink     = base_vi->i_nlink;
+        set_nlink(vi, base_vi->i_nlink);
        vi->i_mtime     = base_vi->i_mtime;
        vi->i_ctime     = base_vi->i_ctime;
        vi->i_atime     = base_vi->i_atime;
@@ -1508,7 +1508,7 @@ static int ntfs_read_locked_index_inode(struct inode *base_vi, struct inode *vi)
        vi->i_version   = base_vi->i_version;
        vi->i_uid       = base_vi->i_uid;
        vi->i_gid       = base_vi->i_gid;
-        vi->i_nlink     = base_vi->i_nlink;
+        set_nlink(vi, base_vi->i_nlink);
        vi->i_mtime     = base_vi->i_mtime;
        vi->i_ctime     = base_vi->i_ctime;
        vi->i_atime     = base_vi->i_atime;
diff --git a/fs/ocfs2/dir.c b/fs/ocfs2/dir.c
index 8582e3f4f120..e2878b5895fb 100644
--- a/fs/ocfs2/dir.c
+++ b/fs/ocfs2/dir.c
@@ -2292,7 +2292,7 @@ static int ocfs2_fill_new_dir_id(struct ocfs2_super *osb,
        ocfs2_journal_dirty(handle, di_bh);
        i_size_write(inode, size);
-        inode->i_nlink = 2;
+        set_nlink(inode, 2);
        inode->i_blocks = ocfs2_inode_sector_count(inode);
        ret = ocfs2_mark_inode_dirty(handle, inode, di_bh);
@@ -2354,7 +2354,7 @@ static int ocfs2_fill_new_dir_el(struct ocfs2_super *osb,
        ocfs2_journal_dirty(handle, new_bh);
        i_size_write(inode, inode->i_sb->s_blocksize);
-        inode->i_nlink = 2;
+        set_nlink(inode, 2);
        inode->i_blocks = ocfs2_inode_sector_count(inode);
        status = ocfs2_mark_inode_dirty(handle, inode, fe_bh);
        if (status < 0) {
diff --git a/fs/ocfs2/dlmglue.c b/fs/ocfs2/dlmglue.c
index 7642d7ca73e5..e1ed5e502ff2 100644
--- a/fs/ocfs2/dlmglue.c
+++ b/fs/ocfs2/dlmglue.c
@@ -2092,7 +2092,7 @@ static void ocfs2_refresh_inode_from_lvb(struct inode *inode)
        inode->i_uid     = be32_to_cpu(lvb->lvb_iuid);
        inode->i_gid     = be32_to_cpu(lvb->lvb_igid);
        inode->i_mode    = be16_to_cpu(lvb->lvb_imode);
-        inode->i_nlink   = be16_to_cpu(lvb->lvb_inlink);
+        set_nlink(inode, be16_to_cpu(lvb->lvb_inlink));
        ocfs2_unpack_timespec(&inode->i_atime,
                              be64_to_cpu(lvb->lvb_iatime_packed));
        ocfs2_unpack_timespec(&inode->i_mtime,
diff --git a/fs/ocfs2/inode.c b/fs/ocfs2/inode.c
index b4c8bb6b8d28..a22d2c098890 100644
--- a/fs/ocfs2/inode.c
+++ b/fs/ocfs2/inode.c
@@ -291,7 +291,7 @@ void ocfs2_populate_inode(struct inode *inode, struct ocfs2_dinode *fe,
                     (unsigned long long)OCFS2_I(inode)->ip_blkno,
                     (unsigned long long)le64_to_cpu(fe->i_blkno));
-        inode->i_nlink = ocfs2_read_links_count(fe);
+        set_nlink(inode, ocfs2_read_links_count(fe));
        trace_ocfs2_populate_inode(OCFS2_I(inode)->ip_blkno,
                                   le32_to_cpu(fe->i_flags));
@@ -1290,7 +1290,7 @@ void ocfs2_refresh_inode(struct inode *inode,
        OCFS2_I(inode)->ip_dyn_features = le16_to_cpu(fe->i_dyn_features);
        ocfs2_set_inode_flags(inode);
        i_size_write(inode, le64_to_cpu(fe->i_size));
-        inode->i_nlink = ocfs2_read_links_count(fe);
+        set_nlink(inode, ocfs2_read_links_count(fe));
        inode->i_uid = le32_to_cpu(fe->i_uid);
        inode->i_gid = le32_to_cpu(fe->i_gid);
        inode->i_mode = le16_to_cpu(fe->i_mode);
diff --git a/fs/ocfs2/namei.c b/fs/ocfs2/namei.c
index 53aa41ed7bf3..a8b2bfea574e 100644
--- a/fs/ocfs2/namei.c
+++ b/fs/ocfs2/namei.c
@@ -199,9 +199,7 @@ static struct inode *ocfs2_get_init_inode(struct inode *dir, int mode)
         * these are used by the support functions here and in
         * callers. */
        if (S_ISDIR(mode))
-                inode->i_nlink = 2;
+                set_nlink(inode, 2);
-        else
-                inode->i_nlink = 1;
        inode_init_owner(inode, dir, mode);
        dquot_initialize(inode);
        return inode;
@@ -1379,7 +1377,7 @@ static int ocfs2_rename(struct inode *old_dir,
        }
        if (new_inode) {
-                new_inode->i_nlink--;
+                drop_nlink(new_inode);
                new_inode->i_ctime = CURRENT_TIME;
        }
        old_dir->i_ctime = old_dir->i_mtime = CURRENT_TIME;
@@ -1387,9 +1385,9 @@ static int ocfs2_rename(struct inode *old_dir,
        if (update_dot_dot) {
                status = ocfs2_update_entry(old_inode, handle,
                                            &old_inode_dot_dot_res, new_dir);
-                old_dir->i_nlink--;
+                drop_nlink(old_dir);
                if (new_inode) {
-                        new_inode->i_nlink--;
+                        drop_nlink(new_inode);
                } else {
                        inc_nlink(new_dir);
                        mark_inode_dirty(new_dir);
@@ -2018,7 +2016,7 @@ static int ocfs2_orphan_add(struct ocfs2_super *osb,
        orphan_fe = (struct ocfs2_dinode *) orphan_dir_bh->b_data;
        if (S_ISDIR(inode->i_mode))
                ocfs2_add_links_count(orphan_fe, 1);
-        orphan_dir_inode->i_nlink = ocfs2_read_links_count(orphan_fe);
+        set_nlink(orphan_dir_inode, ocfs2_read_links_count(orphan_fe));
        ocfs2_journal_dirty(handle, orphan_dir_bh);
        status = __ocfs2_add_entry(handle, orphan_dir_inode, name,
@@ -2116,7 +2114,7 @@ int ocfs2_orphan_del(struct ocfs2_super *osb,
        orphan_fe = (struct ocfs2_dinode *) orphan_dir_bh->b_data;
        if (S_ISDIR(inode->i_mode))
                ocfs2_add_links_count(orphan_fe, -1);
-        orphan_dir_inode->i_nlink = ocfs2_read_links_count(orphan_fe);
+        set_nlink(orphan_dir_inode, ocfs2_read_links_count(orphan_fe));
        ocfs2_journal_dirty(handle, orphan_dir_bh);
 leave:
@@ -2282,7 +2280,7 @@ int ocfs2_create_inode_in_orphan(struct inode *dir,
                goto leave;
        }
-        inode->i_nlink = 0;
+        clear_nlink(inode);
        /* do the real work now. */
        status = __ocfs2_mknod_locked(dir, inode,
                                      0, &new_di_bh, parent_di_bh, handle,
@@ -2437,7 +2435,7 @@ int ocfs2_mv_orphaned_inode_to_new(struct inode *dir,
        di = (struct ocfs2_dinode *)di_bh->b_data;
        le32_add_cpu(&di->i_flags, -OCFS2_ORPHANED_FL);
        di->i_orphaned_slot = 0;
-        inode->i_nlink = 1;
+        set_nlink(inode, 1);
        ocfs2_set_links_count(di, inode->i_nlink);
        ocfs2_journal_dirty(handle, di_bh);
diff --git a/fs/openpromfs/inode.c b/fs/openpromfs/inode.c
index a2a5bff774e3..e4e0ff7962e2 100644
--- a/fs/openpromfs/inode.c
+++ b/fs/openpromfs/inode.c
@@ -242,7 +242,7 @@ found:
                inode->i_mode = S_IFDIR | S_IRUGO | S_IXUGO;
                inode->i_op = &openprom_inode_operations;
                inode->i_fop = &openprom_operations;
-                inode->i_nlink = 2;
+                set_nlink(inode, 2);
                break;
        case op_inode_prop:
                if (!strcmp(dp->name, "options") && (len == 17) &&
@@ -251,7 +251,7 @@ found:
                else
                        inode->i_mode = S_IFREG | S_IRUGO;
                inode->i_fop = &openpromfs_prop_ops;
-                inode->i_nlink = 1;
+                set_nlink(inode, 1);
                inode->i_size = ent_oi->u.prop->length;
                break;
        }
diff --git a/fs/proc/base.c b/fs/proc/base.c
index 8f0087e20e16..851ba3dcdc29 100644
--- a/fs/proc/base.c
+++ b/fs/proc/base.c
@@ -2248,7 +2248,7 @@ static struct dentry *proc_pident_instantiate(struct inode *dir,
        ei = PROC_I(inode);
        inode->i_mode = p->mode;
        if (S_ISDIR(inode->i_mode))
-                inode->i_nlink = 2;     /* Use getattr to fix if necessary */
+                set_nlink(inode, 2);    /* Use getattr to fix if necessary */
        if (p->iop)
                inode->i_op = p->iop;
        if (p->fop)
@@ -2642,7 +2642,7 @@ static struct dentry *proc_base_instantiate(struct inode *dir,
        inode->i_mode = p->mode;
        if (S_ISDIR(inode->i_mode))
-                inode->i_nlink = 2;
+                set_nlink(inode, 2);
        if (S_ISLNK(inode->i_mode))
                inode->i_size = 64;
        if (p->iop)
@@ -2981,8 +2981,8 @@ static struct dentry *proc_pid_instantiate(struct inode *dir,
        inode->i_fop = &proc_tgid_base_operations;
        inode->i_flags|=S_IMMUTABLE;
-        inode->i_nlink = 2 + pid_entry_count_dirs(tgid_base_stuff,
+        set_nlink(inode, 2 + pid_entry_count_dirs(tgid_base_stuff,
-                ARRAY_SIZE(tgid_base_stuff));
+                                                  ARRAY_SIZE(tgid_base_stuff)));
        d_set_d_op(dentry, &pid_dentry_operations);
@@ -3233,8 +3233,8 @@ static struct dentry *proc_task_instantiate(struct inode *dir,
        inode->i_fop = &proc_tid_base_operations;
        inode->i_flags|=S_IMMUTABLE;
-        inode->i_nlink = 2 + pid_entry_count_dirs(tid_base_stuff,
+        set_nlink(inode, 2 + pid_entry_count_dirs(tid_base_stuff,
-                ARRAY_SIZE(tid_base_stuff));
+                                                  ARRAY_SIZE(tid_base_stuff)));
        d_set_d_op(dentry, &pid_dentry_operations);
diff --git a/fs/proc/generic.c b/fs/proc/generic.c
index 9d99131d0d65..10090d9c7ad5 100644
--- a/fs/proc/generic.c
+++ b/fs/proc/generic.c
@@ -283,7 +283,7 @@ static int proc_getattr(struct vfsmount *mnt, struct dentry *dentry,
        struct inode *inode = dentry->d_inode;
        struct proc_dir_entry *de = PROC_I(inode)->pde;
        if (de && de->nlink)
-                inode->i_nlink = de->nlink;
+                set_nlink(inode, de->nlink);
        generic_fillattr(inode, stat);
        return 0;
diff --git a/fs/proc/inode.c b/fs/proc/inode.c
index 7ed72d6c1c6f..7737c5468a40 100644
--- a/fs/proc/inode.c
+++ b/fs/proc/inode.c
@@ -445,7 +445,7 @@ struct inode *proc_get_inode(struct super_block *sb, struct proc_dir_entry *de)
                if (de->size)
                        inode->i_size = de->size;
                if (de->nlink)
-                        inode->i_nlink = de->nlink;
+                        set_nlink(inode, de->nlink);
                if (de->proc_iops)
                        inode->i_op = de->proc_iops;
                if (de->proc_fops) {
diff --git a/fs/proc/proc_sysctl.c b/fs/proc/proc_sysctl.c
index 1a77dbef226f..b44113279e30 100644
--- a/fs/proc/proc_sysctl.c
+++ b/fs/proc/proc_sysctl.c
@@ -39,7 +39,7 @@ static struct inode *proc_sys_make_inode(struct super_block *sb,
                inode->i_fop = &proc_sys_file_operations;
        } else {
                inode->i_mode |= S_IFDIR;
-                inode->i_nlink = 0;
+                clear_nlink(inode);
                inode->i_op = &proc_sys_dir_operations;
                inode->i_fop = &proc_sys_dir_file_operations;
        }
diff --git a/fs/qnx4/inode.c b/fs/qnx4/inode.c
index 2b0646613f5a..3bdd21418432 100644
--- a/fs/qnx4/inode.c
+++ b/fs/qnx4/inode.c
@@ -379,7 +379,7 @@ struct inode *qnx4_iget(struct super_block *sb, unsigned long ino)
        inode->i_mode    = le16_to_cpu(raw_inode->di_mode);
        inode->i_uid     = (uid_t)le16_to_cpu(raw_inode->di_uid);
        inode->i_gid     = (gid_t)le16_to_cpu(raw_inode->di_gid);
-        inode->i_nlink   = le16_to_cpu(raw_inode->di_nlink);
+        set_nlink(inode, le16_to_cpu(raw_inode->di_nlink));
        inode->i_size    = le32_to_cpu(raw_inode->di_size);
        inode->i_mtime.tv_sec   = le32_to_cpu(raw_inode->di_mtime);
        inode->i_mtime.tv_nsec = 0;
diff --git a/fs/quota/quota.c b/fs/quota/quota.c
index 10b6be3ca280..aae0edb95c6c 100644
--- a/fs/quota/quota.c
+++ b/fs/quota/quota.c
@@ -363,12 +363,15 @@ SYSCALL_DEFINE4(quotactl, unsigned int, cmd, const char __user *, special,
        }
        sb = quotactl_block(special);
-        if (IS_ERR(sb))
+        if (IS_ERR(sb)) {
-                return PTR_ERR(sb);
+                ret = PTR_ERR(sb);
+                goto out;
+        }
        ret = do_quotactl(sb, type, cmds, id, addr, pathp);
        drop_super(sb);
+out:
        if (pathp && !IS_ERR(pathp))
                path_put(pathp);
        return ret;
diff --git a/fs/reiserfs/inode.c b/fs/reiserfs/inode.c
index 9b0d4b78b4fb..950f13af0951 100644
--- a/fs/reiserfs/inode.c
+++ b/fs/reiserfs/inode.c
@@ -1154,7 +1154,7 @@ static void init_inode(struct inode *inode, struct treepath *path)
                set_inode_item_key_version(inode, KEY_FORMAT_3_5);
                set_inode_sd_version(inode, STAT_DATA_V1);
                inode->i_mode = sd_v1_mode(sd);
-                inode->i_nlink = sd_v1_nlink(sd);
+                set_nlink(inode, sd_v1_nlink(sd));
                inode->i_uid = sd_v1_uid(sd);
                inode->i_gid = sd_v1_gid(sd);
                inode->i_size = sd_v1_size(sd);
@@ -1199,7 +1199,7 @@ static void init_inode(struct inode *inode, struct treepath *path)
                struct stat_data *sd = (struct stat_data *)B_I_PITEM(bh, ih);
                inode->i_mode = sd_v2_mode(sd);
-                inode->i_nlink = sd_v2_nlink(sd);
+                set_nlink(inode, sd_v2_nlink(sd));
                inode->i_uid = sd_v2_uid(sd);
                inode->i_size = sd_v2_size(sd);
                inode->i_gid = sd_v2_gid(sd);
@@ -1444,7 +1444,7 @@ void reiserfs_read_locked_inode(struct inode *inode,
                /* a stale NFS handle can trigger this without it being an error */
                pathrelse(&path_to_sd);
                reiserfs_make_bad_inode(inode);
-                inode->i_nlink = 0;
+                clear_nlink(inode);
                return;
        }
@@ -1832,7 +1832,7 @@ int reiserfs_new_inode(struct reiserfs_transaction_handle *th,
 #endif
        /* fill stat data */
-        inode->i_nlink = (S_ISDIR(mode) ? 2 : 1);
+        set_nlink(inode, (S_ISDIR(mode) ? 2 : 1));
        /* uid and gid must already be set by the caller for quota init */
@@ -1987,7 +1987,7 @@ int reiserfs_new_inode(struct reiserfs_transaction_handle *th,
        make_bad_inode(inode);
      out_inserted_sd:
-        inode->i_nlink = 0;
+        clear_nlink(inode);
        th->t_trans_id = 0;     /* so the caller can't use this handle later */
        unlock_new_inode(inode); /* OK to do even if we hadn't locked it */
        iput(inode);
diff --git a/fs/reiserfs/namei.c b/fs/reiserfs/namei.c
index ef392324bbf1..80058e8ce361 100644
--- a/fs/reiserfs/namei.c
+++ b/fs/reiserfs/namei.c
@@ -19,7 +19,7 @@
 #include <linux/reiserfs_xattr.h>
 #include <linux/quotaops.h>
-#define INC_DIR_INODE_NLINK(i) if (i->i_nlink != 1) { inc_nlink(i); if (i->i_nlink >= REISERFS_LINK_MAX) i->i_nlink=1; }
+#define INC_DIR_INODE_NLINK(i) if (i->i_nlink != 1) { inc_nlink(i); if (i->i_nlink >= REISERFS_LINK_MAX) set_nlink(i, 1); }
 #define DEC_DIR_INODE_NLINK(i) if (i->i_nlink != 1) drop_nlink(i);
 // directory item contains array of entry headers. This performs
@@ -622,7 +622,7 @@ static int reiserfs_create(struct inode *dir, struct dentry *dentry, int mode,
                               dentry->d_name.len, inode, 1 /*visible */ );
        if (retval) {
                int err;
-                inode->i_nlink--;
+                drop_nlink(inode);
                reiserfs_update_sd(&th, inode);
                err = journal_end(&th, dir->i_sb, jbegin_count);
                if (err)
@@ -702,7 +702,7 @@ static int reiserfs_mknod(struct inode *dir, struct dentry *dentry, int mode,
                               dentry->d_name.len, inode, 1 /*visible */ );
        if (retval) {
                int err;
-                inode->i_nlink--;
+                drop_nlink(inode);
                reiserfs_update_sd(&th, inode);
                err = journal_end(&th, dir->i_sb, jbegin_count);
                if (err)
@@ -787,7 +787,7 @@ static int reiserfs_mkdir(struct inode *dir, struct dentry *dentry, int mode)
                               dentry->d_name.len, inode, 1 /*visible */ );
        if (retval) {
                int err;
-                inode->i_nlink = 0;
+                clear_nlink(inode);
                DEC_DIR_INODE_NLINK(dir);
                reiserfs_update_sd(&th, inode);
                err = journal_end(&th, dir->i_sb, jbegin_count);
@@ -964,7 +964,7 @@ static int reiserfs_unlink(struct inode *dir, struct dentry *dentry)
                reiserfs_warning(inode->i_sb, "reiserfs-7042",
                                 "deleting nonexistent file (%lu), %d",
                                 inode->i_ino, inode->i_nlink);
-                inode->i_nlink = 1;
+                set_nlink(inode, 1);
        }
        drop_nlink(inode);
@@ -1086,7 +1086,7 @@ static int reiserfs_symlink(struct inode *parent_dir,
                                    dentry->d_name.len, inode, 1 /*visible */ );
        if (retval) {
                int err;
-                inode->i_nlink--;
+                drop_nlink(inode);
                reiserfs_update_sd(&th, inode);
                err = journal_end(&th, parent_dir->i_sb, jbegin_count);
                if (err)
@@ -1129,7 +1129,7 @@ static int reiserfs_link(struct dentry *old_dentry, struct inode *dir,
        retval = journal_begin(&th, dir->i_sb, jbegin_count);
        if (retval) {
-                inode->i_nlink--;
+                drop_nlink(inode);
                reiserfs_write_unlock(dir->i_sb);
                return retval;
        }
@@ -1144,7 +1144,7 @@ static int reiserfs_link(struct dentry *old_dentry, struct inode *dir,
        if (retval) {
                int err;
-                inode->i_nlink--;
+                drop_nlink(inode);
                err = journal_end(&th, dir->i_sb, jbegin_count);
                reiserfs_write_unlock(dir->i_sb);
                return err ? err : retval;
diff --git a/fs/romfs/super.c b/fs/romfs/super.c
index 2305e3121cb1..8b4089f30408 100644
--- a/fs/romfs/super.c
+++ b/fs/romfs/super.c
@@ -337,7 +337,7 @@ static struct inode *romfs_iget(struct super_block *sb, unsigned long pos)
        inode->i_metasize = (ROMFH_SIZE + nlen + 1 + ROMFH_PAD) & ROMFH_MASK;
        inode->i_dataoffset = pos + inode->i_metasize;
-        i->i_nlink = 1;         /* Hard to decide.. */
+        set_nlink(i, 1);                /* Hard to decide.. */
        i->i_size = be32_to_cpu(ri.size);
        i->i_mtime.tv_sec = i->i_atime.tv_sec = i->i_ctime.tv_sec = 0;
        i->i_mtime.tv_nsec = i->i_atime.tv_nsec = i->i_ctime.tv_nsec = 0;
diff --git a/fs/squashfs/inode.c b/fs/squashfs/inode.c
index 04bebcaa2373..fd7b3b3bda13 100644
--- a/fs/squashfs/inode.c
+++ b/fs/squashfs/inode.c
@@ -159,7 +159,7 @@ int squashfs_read_inode(struct inode *inode, long long ino)
                        frag_offset = 0;
                }
-                inode->i_nlink = 1;
+                set_nlink(inode, 1);
                inode->i_size = le32_to_cpu(sqsh_ino->file_size);
                inode->i_fop = &generic_ro_fops;
                inode->i_mode |= S_IFREG;
@@ -203,7 +203,7 @@ int squashfs_read_inode(struct inode *inode, long long ino)
                }
                xattr_id = le32_to_cpu(sqsh_ino->xattr);
-                inode->i_nlink = le32_to_cpu(sqsh_ino->nlink);
+                set_nlink(inode, le32_to_cpu(sqsh_ino->nlink));
                inode->i_size = le64_to_cpu(sqsh_ino->file_size);
                inode->i_op = &squashfs_inode_ops;
                inode->i_fop = &generic_ro_fops;
@@ -232,7 +232,7 @@ int squashfs_read_inode(struct inode *inode, long long ino)
                if (err < 0)
                        goto failed_read;
-                inode->i_nlink = le32_to_cpu(sqsh_ino->nlink);
+                set_nlink(inode, le32_to_cpu(sqsh_ino->nlink));
                inode->i_size = le16_to_cpu(sqsh_ino->file_size);
                inode->i_op = &squashfs_dir_inode_ops;
                inode->i_fop = &squashfs_dir_ops;
@@ -257,7 +257,7 @@ int squashfs_read_inode(struct inode *inode, long long ino)
                        goto failed_read;
                xattr_id = le32_to_cpu(sqsh_ino->xattr);
-                inode->i_nlink = le32_to_cpu(sqsh_ino->nlink);
+                set_nlink(inode, le32_to_cpu(sqsh_ino->nlink));
                inode->i_size = le32_to_cpu(sqsh_ino->file_size);
                inode->i_op = &squashfs_dir_inode_ops;
                inode->i_fop = &squashfs_dir_ops;
@@ -284,7 +284,7 @@ int squashfs_read_inode(struct inode *inode, long long ino)
                if (err < 0)
                        goto failed_read;
-                inode->i_nlink = le32_to_cpu(sqsh_ino->nlink);
+                set_nlink(inode, le32_to_cpu(sqsh_ino->nlink));
                inode->i_size = le32_to_cpu(sqsh_ino->symlink_size);
                inode->i_op = &squashfs_symlink_inode_ops;
                inode->i_data.a_ops = &squashfs_symlink_aops;
@@ -325,7 +325,7 @@ int squashfs_read_inode(struct inode *inode, long long ino)
                        inode->i_mode |= S_IFCHR;
                else
                        inode->i_mode |= S_IFBLK;
-                inode->i_nlink = le32_to_cpu(sqsh_ino->nlink);
+                set_nlink(inode, le32_to_cpu(sqsh_ino->nlink));
                rdev = le32_to_cpu(sqsh_ino->rdev);
                init_special_inode(inode, inode->i_mode, new_decode_dev(rdev));
@@ -349,7 +349,7 @@ int squashfs_read_inode(struct inode *inode, long long ino)
                        inode->i_mode |= S_IFBLK;
                xattr_id = le32_to_cpu(sqsh_ino->xattr);
                inode->i_op = &squashfs_inode_ops;
-                inode->i_nlink = le32_to_cpu(sqsh_ino->nlink);
+                set_nlink(inode, le32_to_cpu(sqsh_ino->nlink));
                rdev = le32_to_cpu(sqsh_ino->rdev);
                init_special_inode(inode, inode->i_mode, new_decode_dev(rdev));
@@ -370,7 +370,7 @@ int squashfs_read_inode(struct inode *inode, long long ino)
                        inode->i_mode |= S_IFIFO;
                else
                        inode->i_mode |= S_IFSOCK;
-                inode->i_nlink = le32_to_cpu(sqsh_ino->nlink);
+                set_nlink(inode, le32_to_cpu(sqsh_ino->nlink));
                init_special_inode(inode, inode->i_mode, 0);
                break;
        }
@@ -389,7 +389,7 @@ int squashfs_read_inode(struct inode *inode, long long ino)
                        inode->i_mode |= S_IFSOCK;
                xattr_id = le32_to_cpu(sqsh_ino->xattr);
                inode->i_op = &squashfs_inode_ops;
-                inode->i_nlink = le32_to_cpu(sqsh_ino->nlink);
+                set_nlink(inode, le32_to_cpu(sqsh_ino->nlink));
                init_special_inode(inode, inode->i_mode, 0);
                break;
        }
diff --git a/fs/stack.c b/fs/stack.c
index b4f2ab48a61f..9c11519245a6 100644
--- a/fs/stack.c
+++ b/fs/stack.c
@@ -71,6 +71,6 @@ void fsstack_copy_attr_all(struct inode *dest, const struct inode *src)
        dest->i_ctime = src->i_ctime;
        dest->i_blkbits = src->i_blkbits;
        dest->i_flags = src->i_flags;
-        dest->i_nlink = src->i_nlink;
+        set_nlink(dest, src->i_nlink);
 }
 EXPORT_SYMBOL_GPL(fsstack_copy_attr_all);
diff --git a/fs/stat.c b/fs/stat.c
index 78a3aa83c7ea..8806b8997d2e 100644
--- a/fs/stat.c
+++ b/fs/stat.c
@@ -294,15 +294,16 @@ SYSCALL_DEFINE4(readlinkat, int, dfd, const char __user *, pathname,
 {
        struct path path;
        int error;
+        int empty = 0;
        if (bufsiz <= 0)
                return -EINVAL;
-        error = user_path_at(dfd, pathname, LOOKUP_EMPTY, &path);
+        error = user_path_at_empty(dfd, pathname, LOOKUP_EMPTY, &path, &empty);
        if (!error) {
                struct inode *inode = path.dentry->d_inode;
-                error = -EINVAL;
+                error = empty ? -ENOENT : -EINVAL;
                if (inode->i_op->readlink) {
                        error = security_inode_readlink(path.dentry);
                        if (!error) {
diff --git a/fs/super.c b/fs/super.c
index 32a81f3467e0..afd0f1ad45e0 100644
--- a/fs/super.c
+++ b/fs/super.c
@@ -727,8 +727,13 @@ int do_remount_sb(struct super_block *sb, int flags, void *data, int force)
        if (sb->s_op->remount_fs) {
                retval = sb->s_op->remount_fs(sb, &flags, data);
-                if (retval)
+                if (retval) {
-                        return retval;
+                        if (!force)
+                                return retval;
+                        /* If forced remount, go ahead despite any errors */
+                        WARN(1, "forced remount of a %s fs returned %i\n",
+                             sb->s_type->name, retval);
+                }
        }
        sb->s_flags = (sb->s_flags & ~MS_RMT_MASK) | (flags & MS_RMT_MASK);
diff --git a/fs/sysfs/inode.c b/fs/sysfs/inode.c
index e23f28894a3a..c81b22f3ace1 100644
--- a/fs/sysfs/inode.c
+++ b/fs/sysfs/inode.c
@@ -218,7 +218,7 @@ static void sysfs_refresh_inode(struct sysfs_dirent *sd, struct inode *inode)
        }
        if (sysfs_type(sd) == SYSFS_DIR)
-                inode->i_nlink = sd->s_dir.subdirs + 2;
+                set_nlink(inode, sd->s_dir.subdirs + 2);
 }
 int sysfs_getattr(struct vfsmount *mnt, struct dentry *dentry, struct kstat *stat)
diff --git a/fs/sysv/inode.c b/fs/sysv/inode.c
index 0630eb969a28..25ffb3e9a3f8 100644
--- a/fs/sysv/inode.c
+++ b/fs/sysv/inode.c
@@ -219,7 +219,7 @@ struct inode *sysv_iget(struct super_block *sb, unsigned int ino)
        inode->i_mode = fs16_to_cpu(sbi, raw_inode->i_mode);
        inode->i_uid = (uid_t)fs16_to_cpu(sbi, raw_inode->i_uid);
        inode->i_gid = (gid_t)fs16_to_cpu(sbi, raw_inode->i_gid);
-        inode->i_nlink = fs16_to_cpu(sbi, raw_inode->i_nlink);
+        set_nlink(inode, fs16_to_cpu(sbi, raw_inode->i_nlink));
        inode->i_size = fs32_to_cpu(sbi, raw_inode->i_size);
        inode->i_atime.tv_sec = fs32_to_cpu(sbi, raw_inode->i_atime);
        inode->i_mtime.tv_sec = fs32_to_cpu(sbi, raw_inode->i_mtime);
diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c
index b28121278d46..20403dc5d437 100644
--- a/fs/ubifs/super.c
+++ b/fs/ubifs/super.c
@@ -129,7 +129,7 @@ struct inode *ubifs_iget(struct super_block *sb, unsigned long inum)
                goto out_ino;
        inode->i_flags |= (S_NOCMTIME | S_NOATIME);
-        inode->i_nlink = le32_to_cpu(ino->nlink);
+        set_nlink(inode, le32_to_cpu(ino->nlink));
        inode->i_uid   = le32_to_cpu(ino->uid);
        inode->i_gid   = le32_to_cpu(ino->gid);
        inode->i_atime.tv_sec  = (int64_t)le64_to_cpu(ino->atime_sec);
diff --git a/fs/ubifs/xattr.c b/fs/ubifs/xattr.c
index 16f19f55e63f..bf18f7a04544 100644
--- a/fs/ubifs/xattr.c
+++ b/fs/ubifs/xattr.c
@@ -558,10 +558,10 @@ int ubifs_removexattr(struct dentry *dentry, const char *name)
        }
        ubifs_assert(inode->i_nlink == 1);
-        inode->i_nlink = 0;
+        clear_nlink(inode);
        err = remove_xattr(c, host, inode, &nm);
        if (err)
-                inode->i_nlink = 1;
+                set_nlink(inode, 1);
        /* If @i_nlink is 0, 'iput()' will delete the inode */
        iput(inode);
diff --git a/fs/udf/balloc.c b/fs/udf/balloc.c
index 95518a9f589e..987585bb0a1d 100644
--- a/fs/udf/balloc.c
+++ b/fs/udf/balloc.c
@@ -59,8 +59,8 @@ static int __load_block_bitmap(struct super_block *sb,
        int nr_groups = bitmap->s_nr_groups;
        if (block_group >= nr_groups) {
-                udf_debug("block_group (%d) > nr_groups (%d)\n", block_group,
+                udf_debug("block_group (%d) > nr_groups (%d)\n",
-                          nr_groups);
+                          block_group, nr_groups);
        }
        if (bitmap->s_block_bitmap[block_group]) {
@@ -126,8 +126,9 @@ static void udf_bitmap_free_blocks(struct super_block *sb,
        if (bloc->logicalBlockNum + count < count ||
            (bloc->logicalBlockNum + count) > partmap->s_partition_len) {
                udf_debug("%d < %d || %d + %d > %d\n",
-                          bloc->logicalBlockNum, 0, bloc->logicalBlockNum,
+                          bloc->logicalBlockNum, 0,
-                          count, partmap->s_partition_len);
+                          bloc->logicalBlockNum, count,
+                          partmap->s_partition_len);
                goto error_return;
        }
@@ -155,7 +156,7 @@ static void udf_bitmap_free_blocks(struct super_block *sb,
                        if (udf_set_bit(bit + i, bh->b_data)) {
                                udf_debug("bit %ld already set\n", bit + i);
                                udf_debug("byte=%2x\n",
-                                        ((char *)bh->b_data)[(bit + i) >> 3]);
+                                          ((char *)bh->b_data)[(bit + i) >> 3]);
                        }
                }
                udf_add_free_space(sb, sbi->s_partition, count);
@@ -369,7 +370,8 @@ static void udf_table_free_blocks(struct super_block *sb,
        if (bloc->logicalBlockNum + count < count ||
            (bloc->logicalBlockNum + count) > partmap->s_partition_len) {
                udf_debug("%d < %d || %d + %d > %d\n",
-                          bloc->logicalBlockNum, 0, bloc->logicalBlockNum, count,
+                          bloc->logicalBlockNum, 0,
+                          bloc->logicalBlockNum, count,
                          partmap->s_partition_len);
                goto error_return;
        }
diff --git a/fs/udf/directory.c b/fs/udf/directory.c
index 2ffdb6733af1..3e44f575fb9c 100644
--- a/fs/udf/directory.c
+++ b/fs/udf/directory.c
@@ -162,8 +162,8 @@ struct fileIdentDesc *udf_get_fileident(void *buffer, int bufsize, int *offset)
        int padlen;
        if ((!buffer) || (!offset)) {
-                udf_debug("invalidparms\n, buffer=%p, offset=%p\n", buffer,
+                udf_debug("invalidparms, buffer=%p, offset=%p\n",
-                          offset);
+                          buffer, offset);
                return NULL;
        }
@@ -201,7 +201,7 @@ struct short_ad *udf_get_fileshortad(uint8_t *ptr, int maxoffset, uint32_t *offs
        struct short_ad *sa;
        if ((!ptr) || (!offset)) {
-                printk(KERN_ERR "udf: udf_get_fileshortad() invalidparms\n");
+                pr_err("%s: invalidparms\n", __func__);
                return NULL;
        }
@@ -223,7 +223,7 @@ struct long_ad *udf_get_filelongad(uint8_t *ptr, int maxoffset, uint32_t *offset
        struct long_ad *la;
        if ((!ptr) || (!offset)) {
-                printk(KERN_ERR "udf: udf_get_filelongad() invalidparms\n");
+                pr_err("%s: invalidparms\n", __func__);
                return NULL;
        }
diff --git a/fs/udf/inode.c b/fs/udf/inode.c
index 1d1358ed80c1..4fd1d809738c 100644
--- a/fs/udf/inode.c
+++ b/fs/udf/inode.c
@@ -37,6 +37,7 @@
 #include <linux/writeback.h>
 #include <linux/slab.h>
 #include <linux/crc-itu-t.h>
+#include <linux/mpage.h>
 #include "udf_i.h"
 #include "udf_sb.h"
@@ -83,12 +84,10 @@ void udf_evict_inode(struct inode *inode)
        end_writeback(inode);
        if (iinfo->i_alloc_type != ICBTAG_FLAG_AD_IN_ICB &&
            inode->i_size != iinfo->i_lenExtents) {
-                printk(KERN_WARNING "UDF-fs (%s): Inode %lu (mode %o) has "
+                udf_warn(inode->i_sb, "Inode %lu (mode %o) has inode size %llu different from extent length %llu. Filesystem need not be standards compliant.\n",
-                        "inode size %llu different from extent length %llu. "
+                         inode->i_ino, inode->i_mode,
-                        "Filesystem need not be standards compliant.\n",
+                         (unsigned long long)inode->i_size,
-                        inode->i_sb->s_id, inode->i_ino, inode->i_mode,
+                         (unsigned long long)iinfo->i_lenExtents);
-                        (unsigned long long)inode->i_size,
-                        (unsigned long long)iinfo->i_lenExtents);
        }
        kfree(iinfo->i_ext.i_data);
        iinfo->i_ext.i_data = NULL;
@@ -104,7 +103,13 @@ static int udf_writepage(struct page *page, struct writeback_control *wbc)
 static int udf_readpage(struct file *file, struct page *page)
 {
-        return block_read_full_page(page, udf_get_block);
+        return mpage_readpage(page, udf_get_block);
+}
+static int udf_readpages(struct file *file, struct address_space *mapping,
+                        struct list_head *pages, unsigned nr_pages)
+{
+        return mpage_readpages(mapping, pages, nr_pages, udf_get_block);
 }
 static int udf_write_begin(struct file *file, struct address_space *mapping,
@@ -139,6 +144,7 @@ static sector_t udf_bmap(struct address_space *mapping, sector_t block)
 const struct address_space_operations udf_aops = {
        .readpage       = udf_readpage,
+        .readpages      = udf_readpages,
        .writepage      = udf_writepage,
        .write_begin            = udf_write_begin,
        .write_end              = generic_write_end,
@@ -1169,16 +1175,15 @@ static void __udf_read_inode(struct inode *inode)
         */
        bh = udf_read_ptagged(inode->i_sb, &iinfo->i_location, 0, &ident);
        if (!bh) {
-                printk(KERN_ERR "udf: udf_read_inode(ino %ld) failed !bh\n",
+                udf_err(inode->i_sb, "(ino %ld) failed !bh\n", inode->i_ino);
-                       inode->i_ino);
                make_bad_inode(inode);
                return;
        }
        if (ident != TAG_IDENT_FE && ident != TAG_IDENT_EFE &&
            ident != TAG_IDENT_USE) {
-                printk(KERN_ERR "udf: udf_read_inode(ino %ld) "
+                udf_err(inode->i_sb, "(ino %ld) failed ident=%d\n",
-                                "failed ident=%d\n", inode->i_ino, ident);
+                        inode->i_ino, ident);
                brelse(bh);
                make_bad_inode(inode);
                return;
@@ -1218,8 +1223,8 @@ static void __udf_read_inode(struct inode *inode)
                }
                brelse(ibh);
        } else if (fe->icbTag.strategyType != cpu_to_le16(4)) {
-                printk(KERN_ERR "udf: unsupported strategy type: %d\n",
+                udf_err(inode->i_sb, "unsupported strategy type: %d\n",
-                       le16_to_cpu(fe->icbTag.strategyType));
+                        le16_to_cpu(fe->icbTag.strategyType));
                brelse(bh);
                make_bad_inode(inode);
                return;
@@ -1236,6 +1241,7 @@ static void udf_fill_inode(struct inode *inode, struct buffer_head *bh)
        int offset;
        struct udf_sb_info *sbi = UDF_SB(inode->i_sb);
        struct udf_inode_info *iinfo = UDF_I(inode);
+        unsigned int link_count;
        fe = (struct fileEntry *)bh->b_data;
        efe = (struct extendedFileEntry *)bh->b_data;
@@ -1318,9 +1324,10 @@ static void udf_fill_inode(struct inode *inode, struct buffer_head *bh)
        inode->i_mode &= ~sbi->s_umask;
        read_unlock(&sbi->s_cred_lock);
-        inode->i_nlink = le16_to_cpu(fe->fileLinkCount);
+        link_count = le16_to_cpu(fe->fileLinkCount);
-        if (!inode->i_nlink)
+        if (!link_count)
-                inode->i_nlink = 1;
+                link_count = 1;
+        set_nlink(inode, link_count);
        inode->i_size = le64_to_cpu(fe->informationLength);
        iinfo->i_lenExtents = inode->i_size;
@@ -1413,9 +1420,8 @@ static void udf_fill_inode(struct inode *inode, struct buffer_head *bh)
                udf_debug("METADATA BITMAP FILE-----\n");
                break;
        default:
-                printk(KERN_ERR "udf: udf_fill_inode(ino %ld) failed unknown "
+                udf_err(inode->i_sb, "(ino %ld) failed unknown file type=%d\n",
-                                "file type=%d\n", inode->i_ino,
+                        inode->i_ino, fe->icbTag.fileType);
-                                fe->icbTag.fileType);
                make_bad_inode(inode);
                return;
        }
@@ -1438,8 +1444,8 @@ static int udf_alloc_i_data(struct inode *inode, size_t size)
        iinfo->i_ext.i_data = kmalloc(size, GFP_KERNEL);
        if (!iinfo->i_ext.i_data) {
-                printk(KERN_ERR "udf:udf_alloc_i_data (ino %ld) "
+                udf_err(inode->i_sb, "(ino %ld) no free memory\n",
-                                "no free memory\n", inode->i_ino);
+                        inode->i_ino);
                return -ENOMEM;
        }
@@ -1689,9 +1695,8 @@ out:
        if (do_sync) {
                sync_dirty_buffer(bh);
                if (buffer_write_io_error(bh)) {
-                        printk(KERN_WARNING "IO error syncing udf inode "
+                        udf_warn(inode->i_sb, "IO error syncing udf inode [%08lx]\n",
-                                "[%s:%08lx]\n", inode->i_sb->s_id,
+                                 inode->i_ino);
-                                inode->i_ino);
                        err = -EIO;
                }
        }
@@ -1982,8 +1987,7 @@ int8_t udf_current_aext(struct inode *inode, struct extent_position *epos,
                *elen = le32_to_cpu(lad->extLength) & UDF_EXTENT_LENGTH_MASK;
                break;
        default:
-                udf_debug("alloc_type = %d unsupported\n",
+                udf_debug("alloc_type = %d unsupported\n", iinfo->i_alloc_type);
-                                iinfo->i_alloc_type);
                return -1;
        }
diff --git a/fs/udf/lowlevel.c b/fs/udf/lowlevel.c
index 43e24a3b8e10..6583fe9b0645 100644
--- a/fs/udf/lowlevel.c
+++ b/fs/udf/lowlevel.c
@@ -38,7 +38,7 @@ unsigned int udf_get_last_session(struct super_block *sb)
        if (i == 0) {
                udf_debug("XA disk: %s, vol_desc_start=%d\n",
-                          (ms_info.xa_flag ? "yes" : "no"), ms_info.addr.lba);
+                          ms_info.xa_flag ? "yes" : "no", ms_info.addr.lba);
                if (ms_info.xa_flag) /* necessary for a valid ms_info.addr */
                        vol_desc_start = ms_info.addr.lba;
        } else {
diff --git a/fs/udf/misc.c b/fs/udf/misc.c
index 9215700c00a4..c175b4dabc14 100644
--- a/fs/udf/misc.c
+++ b/fs/udf/misc.c
@@ -204,6 +204,7 @@ struct buffer_head *udf_read_tagged(struct super_block *sb, uint32_t block,
 {
        struct tag *tag_p;
        struct buffer_head *bh = NULL;
+        u8 checksum;
        /* Read the block */
        if (block == 0xFFFFFFFF)
@@ -211,8 +212,8 @@ struct buffer_head *udf_read_tagged(struct super_block *sb, uint32_t block,
        bh = udf_tread(sb, block);
        if (!bh) {
-                udf_debug("block=%d, location=%d: read failed\n",
+                udf_err(sb, "read failed, block=%u, location=%d\n",
-                          block, location);
+                        block, location);
                return NULL;
        }
@@ -227,16 +228,18 @@ struct buffer_head *udf_read_tagged(struct super_block *sb, uint32_t block,
        }
        /* Verify the tag checksum */
-        if (udf_tag_checksum(tag_p) != tag_p->tagChecksum) {
+        checksum = udf_tag_checksum(tag_p);
-                printk(KERN_ERR "udf: tag checksum failed block %d\n", block);
+        if (checksum != tag_p->tagChecksum) {
+                udf_err(sb, "tag checksum failed, block %u: 0x%02x != 0x%02x\n",
+                        block, checksum, tag_p->tagChecksum);
                goto error_out;
        }
        /* Verify the tag version */
        if (tag_p->descVersion != cpu_to_le16(0x0002U) &&
            tag_p->descVersion != cpu_to_le16(0x0003U)) {
-                udf_debug("tag version 0x%04x != 0x0002 || 0x0003 block %d\n",
+                udf_err(sb, "tag version 0x%04x != 0x0002 || 0x0003, block %u\n",
-                          le16_to_cpu(tag_p->descVersion), block);
+                        le16_to_cpu(tag_p->descVersion), block);
                goto error_out;
        }
@@ -248,8 +251,8 @@ struct buffer_head *udf_read_tagged(struct super_block *sb, uint32_t block,
                return bh;
        udf_debug("Crc failure block %d: crc = %d, crclen = %d\n", block,
-            le16_to_cpu(tag_p->descCRC), le16_to_cpu(tag_p->descCRCLength));
+                  le16_to_cpu(tag_p->descCRC),
+                  le16_to_cpu(tag_p->descCRCLength));
 error_out:
        brelse(bh);
        return NULL;
diff --git a/fs/udf/namei.c b/fs/udf/namei.c
index f1dce848ef96..4639e137222f 100644
--- a/fs/udf/namei.c
+++ b/fs/udf/namei.c
@@ -577,8 +577,7 @@ static int udf_create(struct inode *dir, struct dentry *dentry, int mode,
        fi = udf_add_entry(dir, dentry, &fibh, &cfi, &err);
        if (!fi) {
-                inode->i_nlink--;
+                inode_dec_link_count(inode);
-                mark_inode_dirty(inode);
                iput(inode);
                return err;
        }
@@ -618,8 +617,7 @@ static int udf_mknod(struct inode *dir, struct dentry *dentry, int mode,
        init_special_inode(inode, mode, rdev);
        fi = udf_add_entry(dir, dentry, &fibh, &cfi, &err);
        if (!fi) {
-                inode->i_nlink--;
+                inode_dec_link_count(inode);
-                mark_inode_dirty(inode);
                iput(inode);
                return err;
        }
@@ -665,12 +663,11 @@ static int udf_mkdir(struct inode *dir, struct dentry *dentry, int mode)
        inode->i_fop = &udf_dir_operations;
        fi = udf_add_entry(inode, NULL, &fibh, &cfi, &err);
        if (!fi) {
-                inode->i_nlink--;
+                inode_dec_link_count(inode);
-                mark_inode_dirty(inode);
                iput(inode);
                goto out;
        }
-        inode->i_nlink = 2;
+        set_nlink(inode, 2);
        cfi.icb.extLength = cpu_to_le32(inode->i_sb->s_blocksize);
        cfi.icb.extLocation = cpu_to_lelb(dinfo->i_location);
        *(__le32 *)((struct allocDescImpUse *)cfi.icb.impUse)->impUse =
@@ -683,7 +680,7 @@ static int udf_mkdir(struct inode *dir, struct dentry *dentry, int mode)
        fi = udf_add_entry(dir, dentry, &fibh, &cfi, &err);
        if (!fi) {
-                inode->i_nlink = 0;
+                clear_nlink(inode);
                mark_inode_dirty(inode);
                iput(inode);
                goto out;
@@ -799,9 +796,8 @@ static int udf_rmdir(struct inode *dir, struct dentry *dentry)
        if (retval)
                goto end_rmdir;
        if (inode->i_nlink != 2)
-                udf_warning(inode->i_sb, "udf_rmdir",
+                udf_warn(inode->i_sb, "empty directory has nlink != 2 (%d)\n",
-                            "empty directory has nlink != 2 (%d)",
+                         inode->i_nlink);
-                            inode->i_nlink);
        clear_nlink(inode);
        inode->i_size = 0;
        inode_dec_link_count(dir);
@@ -840,7 +836,7 @@ static int udf_unlink(struct inode *dir, struct dentry *dentry)
        if (!inode->i_nlink) {
                udf_debug("Deleting nonexistent file (%lu), %d\n",
                          inode->i_ino, inode->i_nlink);
-                inode->i_nlink = 1;
+                set_nlink(inode, 1);
        }
        retval = udf_delete_entry(dir, fi, &fibh, &cfi);
        if (retval)
diff --git a/fs/udf/partition.c b/fs/udf/partition.c
index a71090ea0e07..d6caf01a2097 100644
--- a/fs/udf/partition.c
+++ b/fs/udf/partition.c
@@ -33,8 +33,8 @@ uint32_t udf_get_pblock(struct super_block *sb, uint32_t block,
        struct udf_sb_info *sbi = UDF_SB(sb);
        struct udf_part_map *map;
        if (partition >= sbi->s_partitions) {
-                udf_debug("block=%d, partition=%d, offset=%d: "
+                udf_debug("block=%d, partition=%d, offset=%d: invalid partition\n",
-                          "invalid partition\n", block, partition, offset);
+                          block, partition, offset);
                return 0xFFFFFFFF;
        }
        map = &sbi->s_partmaps[partition];
@@ -60,8 +60,8 @@ uint32_t udf_get_pblock_virt15(struct super_block *sb, uint32_t block,
        vdata = &map->s_type_specific.s_virtual;
        if (block > vdata->s_num_entries) {
-                udf_debug("Trying to access block beyond end of VAT "
+                udf_debug("Trying to access block beyond end of VAT (%d max %d)\n",
-                          "(%d max %d)\n", block, vdata->s_num_entries);
+                          block, vdata->s_num_entries);
                return 0xFFFFFFFF;
        }
@@ -321,9 +321,14 @@ uint32_t udf_get_pblock_meta25(struct super_block *sb, uint32_t block,
        /* We shouldn't mount such media... */
        BUG_ON(!inode);
        retblk = udf_try_read_meta(inode, block, partition, offset);
-        if (retblk == 0xFFFFFFFF) {
+        if (retblk == 0xFFFFFFFF && mdata->s_metadata_fe) {
-                udf_warning(sb, __func__, "error reading from METADATA, "
+                udf_warn(sb, "error reading from METADATA, trying to read from MIRROR\n");
-                        "trying to read from MIRROR");
+                if (!(mdata->s_flags & MF_MIRROR_FE_LOADED)) {
+                        mdata->s_mirror_fe = udf_find_metadata_inode_efe(sb,
+                                mdata->s_mirror_file_loc, map->s_partition_num);
+                        mdata->s_flags |= MF_MIRROR_FE_LOADED;
+                }
                inode = mdata->s_mirror_fe;
                if (!inode)
                        return 0xFFFFFFFF;
diff --git a/fs/udf/super.c b/fs/udf/super.c
index 7b27b063ff6d..e185253470df 100644
--- a/fs/udf/super.c
+++ b/fs/udf/super.c
@@ -75,8 +75,6 @@
 #define UDF_DEFAULT_BLOCKSIZE 2048
-static char error_buf[1024];
 /* These are the "meat" - everything else is stuffing */
 static int udf_fill_super(struct super_block *, void *, int);
 static void udf_put_super(struct super_block *);
@@ -92,8 +90,6 @@ static void udf_close_lvid(struct super_block *);
 static unsigned int udf_count_free(struct super_block *);
 static int udf_statfs(struct dentry *, struct kstatfs *);
 static int udf_show_options(struct seq_file *, struct vfsmount *);
-static void udf_error(struct super_block *sb, const char *function,
-                      const char *fmt, ...);
 struct logicalVolIntegrityDescImpUse *udf_sb_lvidiu(struct udf_sb_info *sbi)
 {
@@ -244,9 +240,8 @@ static int udf_sb_alloc_partition_maps(struct super_block *sb, u32 count)
        sbi->s_partmaps = kcalloc(count, sizeof(struct udf_part_map),
                                  GFP_KERNEL);
        if (!sbi->s_partmaps) {
-                udf_error(sb, __func__,
+                udf_err(sb, "Unable to allocate space for %d partition maps\n",
-                          "Unable to allocate space for %d partition maps",
+                        count);
-                          count);
                sbi->s_partitions = 0;
                return -ENOMEM;
        }
@@ -550,8 +545,7 @@ static int udf_parse_options(char *options, struct udf_options *uopt,
                        uopt->dmode = option & 0777;
                        break;
                default:
-                        printk(KERN_ERR "udf: bad mount option \"%s\" "
+                        pr_err("bad mount option \"%s\" or missing value\n", p);
-                               "or missing value\n", p);
                        return 0;
                }
        }
@@ -645,20 +639,16 @@ static loff_t udf_check_vsd(struct super_block *sb)
                                udf_debug("ISO9660 Boot Record found\n");
                                break;
                        case 1:
-                                udf_debug("ISO9660 Primary Volume Descriptor "
+                                udf_debug("ISO9660 Primary Volume Descriptor found\n");
-                                          "found\n");
                                break;
                        case 2:
-                                udf_debug("ISO9660 Supplementary Volume "
+                                udf_debug("ISO9660 Supplementary Volume Descriptor found\n");
-                                          "Descriptor found\n");
                                break;
                        case 3:
-                                udf_debug("ISO9660 Volume Partition Descriptor "
+                                udf_debug("ISO9660 Volume Partition Descriptor found\n");
-                                          "found\n");
                                break;
                        case 255:
-                                udf_debug("ISO9660 Volume Descriptor Set "
+                                udf_debug("ISO9660 Volume Descriptor Set Terminator found\n");
-                                          "Terminator found\n");
                                break;
                        default:
                                udf_debug("ISO9660 VRS (%u) found\n",
@@ -809,8 +799,7 @@ static int udf_load_pvoldesc(struct super_block *sb, sector_t block)
                              pvoldesc->recordingDateAndTime)) {
 #ifdef UDFFS_DEBUG
                struct timestamp *ts = &pvoldesc->recordingDateAndTime;
-                udf_debug("recording time %04u/%02u/%02u"
+                udf_debug("recording time %04u/%02u/%02u %02u:%02u (%x)\n",
-                          " %02u:%02u (%x)\n",
                          le16_to_cpu(ts->year), ts->month, ts->day, ts->hour,
                          ts->minute, le16_to_cpu(ts->typeAndTimezone));
 #endif
@@ -821,7 +810,7 @@ static int udf_load_pvoldesc(struct super_block *sb, sector_t block)
                        strncpy(UDF_SB(sb)->s_volume_ident, outstr->u_name,
                                outstr->u_len > 31 ? 31 : outstr->u_len);
                        udf_debug("volIdent[] = '%s'\n",
-                                        UDF_SB(sb)->s_volume_ident);
+                                  UDF_SB(sb)->s_volume_ident);
                }
        if (!udf_build_ustr(instr, pvoldesc->volSetIdent, 128))
@@ -837,64 +826,57 @@ out1:
        return ret;
 }
+struct inode *udf_find_metadata_inode_efe(struct super_block *sb,
+                                        u32 meta_file_loc, u32 partition_num)
+{
+        struct kernel_lb_addr addr;
+        struct inode *metadata_fe;
+        addr.logicalBlockNum = meta_file_loc;
+        addr.partitionReferenceNum = partition_num;
+        metadata_fe = udf_iget(sb, &addr);
+        if (metadata_fe == NULL)
+                udf_warn(sb, "metadata inode efe not found\n");
+        else if (UDF_I(metadata_fe)->i_alloc_type != ICBTAG_FLAG_AD_SHORT) {
+                udf_warn(sb, "metadata inode efe does not have short allocation descriptors!\n");
+                iput(metadata_fe);
+                metadata_fe = NULL;
+        }
+        return metadata_fe;
+}
 static int udf_load_metadata_files(struct super_block *sb, int partition)
 {
        struct udf_sb_info *sbi = UDF_SB(sb);
        struct udf_part_map *map;
        struct udf_meta_data *mdata;
        struct kernel_lb_addr addr;
-        int fe_error = 0;
        map = &sbi->s_partmaps[partition];
        mdata = &map->s_type_specific.s_metadata;
        /* metadata address */
-        addr.logicalBlockNum =  mdata->s_meta_file_loc;
-        addr.partitionReferenceNum = map->s_partition_num;
        udf_debug("Metadata file location: block = %d part = %d\n",
-                          addr.logicalBlockNum, addr.partitionReferenceNum);
+                  mdata->s_meta_file_loc, map->s_partition_num);
-        mdata->s_metadata_fe = udf_iget(sb, &addr);
+        mdata->s_metadata_fe = udf_find_metadata_inode_efe(sb,
+                mdata->s_meta_file_loc, map->s_partition_num);
        if (mdata->s_metadata_fe == NULL) {
-                udf_warning(sb, __func__, "metadata inode efe not found, "
+                /* mirror file entry */
-                                "will try mirror inode.");
+                udf_debug("Mirror metadata file location: block = %d part = %d\n",
-                fe_error = 1;
+                          mdata->s_mirror_file_loc, map->s_partition_num);
-        } else if (UDF_I(mdata->s_metadata_fe)->i_alloc_type !=
-                 ICBTAG_FLAG_AD_SHORT) {
-                udf_warning(sb, __func__, "metadata inode efe does not have "
-                        "short allocation descriptors!");
-                fe_error = 1;
-                iput(mdata->s_metadata_fe);
-                mdata->s_metadata_fe = NULL;
-        }
-        /* mirror file entry */
+                mdata->s_mirror_fe = udf_find_metadata_inode_efe(sb,
-        addr.logicalBlockNum = mdata->s_mirror_file_loc;
+                        mdata->s_mirror_file_loc, map->s_partition_num);
-        addr.partitionReferenceNum = map->s_partition_num;
-        udf_debug("Mirror metadata file location: block = %d part = %d\n",
-                          addr.logicalBlockNum, addr.partitionReferenceNum);
-        mdata->s_mirror_fe = udf_iget(sb, &addr);
+                if (mdata->s_mirror_fe == NULL) {
+                        udf_err(sb, "Both metadata and mirror metadata inode efe can not found\n");
-        if (mdata->s_mirror_fe == NULL) {
-                if (fe_error) {
-                        udf_error(sb, __func__, "mirror inode efe not found "
-                        "and metadata inode is missing too, exiting...");
-                        goto error_exit;
-                } else
-                        udf_warning(sb, __func__, "mirror inode efe not found,"
-                                        " but metadata inode is OK");
-        } else if (UDF_I(mdata->s_mirror_fe)->i_alloc_type !=
-                 ICBTAG_FLAG_AD_SHORT) {
-                udf_warning(sb, __func__, "mirror inode efe does not have "
-                        "short allocation descriptors!");
-                iput(mdata->s_mirror_fe);
-                mdata->s_mirror_fe = NULL;
-                if (fe_error)
                        goto error_exit;
+                }
        }
        /*
@@ -907,18 +889,15 @@ static int udf_load_metadata_files(struct super_block *sb, int partition)
                addr.partitionReferenceNum = map->s_partition_num;
                udf_debug("Bitmap file location: block = %d part = %d\n",
-                        addr.logicalBlockNum, addr.partitionReferenceNum);
+                          addr.logicalBlockNum, addr.partitionReferenceNum);
                mdata->s_bitmap_fe = udf_iget(sb, &addr);
                if (mdata->s_bitmap_fe == NULL) {
                        if (sb->s_flags & MS_RDONLY)
-                                udf_warning(sb, __func__, "bitmap inode efe "
+                                udf_warn(sb, "bitmap inode efe not found but it's ok since the disc is mounted read-only\n");
-                                        "not found but it's ok since the disc"
-                                        " is mounted read-only");
                        else {
-                                udf_error(sb, __func__, "bitmap inode efe not "
+                                udf_err(sb, "bitmap inode efe not found and attempted read-write mount\n");
-                                        "found and attempted read-write mount");
                                goto error_exit;
                        }
                }
@@ -971,9 +950,8 @@ static struct udf_bitmap *udf_sb_alloc_bitmap(struct super_block *sb, u32 index)
                bitmap = vzalloc(size); /* TODO: get rid of vzalloc */
        if (bitmap == NULL) {
-                udf_error(sb, __func__,
+                udf_err(sb, "Unable to allocate space for bitmap and %d buffer_head pointers\n",
-                          "Unable to allocate space for bitmap "
+                        nr_groups);
-                          "and %d buffer_head pointers", nr_groups);
                return NULL;
        }
@@ -1003,10 +981,9 @@ static int udf_fill_partdesc_info(struct super_block *sb,
        if (p->accessType == cpu_to_le32(PD_ACCESS_TYPE_OVERWRITABLE))
                map->s_partition_flags |= UDF_PART_FLAG_OVERWRITABLE;
-        udf_debug("Partition (%d type %x) starts at physical %d, "
+        udf_debug("Partition (%d type %x) starts at physical %d, block length %d\n",
-                  "block length %d\n", p_index,
+                  p_index, map->s_partition_type,
-                  map->s_partition_type, map->s_partition_root,
+                  map->s_partition_root, map->s_partition_len);
-                  map->s_partition_len);
        if (strcmp(p->partitionContents.ident, PD_PARTITION_CONTENTS_NSR02) &&
            strcmp(p->partitionContents.ident, PD_PARTITION_CONTENTS_NSR03))
@@ -1023,12 +1000,12 @@ static int udf_fill_partdesc_info(struct super_block *sb,
                map->s_uspace.s_table = udf_iget(sb, &loc);
                if (!map->s_uspace.s_table) {
                        udf_debug("cannot load unallocSpaceTable (part %d)\n",
-                                        p_index);
+                                  p_index);
                        return 1;
                }
                map->s_partition_flags |= UDF_PART_FLAG_UNALLOC_TABLE;
                udf_debug("unallocSpaceTable (part %d) @ %ld\n",
-                                p_index, map->s_uspace.s_table->i_ino);
+                          p_index, map->s_uspace.s_table->i_ino);
        }
        if (phd->unallocSpaceBitmap.extLength) {
@@ -1041,8 +1018,8 @@ static int udf_fill_partdesc_info(struct super_block *sb,
                bitmap->s_extPosition = le32_to_cpu(
                                phd->unallocSpaceBitmap.extPosition);
                map->s_partition_flags |= UDF_PART_FLAG_UNALLOC_BITMAP;
-                udf_debug("unallocSpaceBitmap (part %d) @ %d\n", p_index,
+                udf_debug("unallocSpaceBitmap (part %d) @ %d\n",
-                                                bitmap->s_extPosition);
+                          p_index, bitmap->s_extPosition);
        }
        if (phd->partitionIntegrityTable.extLength)
@@ -1058,13 +1035,13 @@ static int udf_fill_partdesc_info(struct super_block *sb,
                map->s_fspace.s_table = udf_iget(sb, &loc);
                if (!map->s_fspace.s_table) {
                        udf_debug("cannot load freedSpaceTable (part %d)\n",
-                                p_index);
+                                  p_index);
                        return 1;
                }
                map->s_partition_flags |= UDF_PART_FLAG_FREED_TABLE;
                udf_debug("freedSpaceTable (part %d) @ %ld\n",
-                                p_index, map->s_fspace.s_table->i_ino);
+                          p_index, map->s_fspace.s_table->i_ino);
        }
        if (phd->freedSpaceBitmap.extLength) {
@@ -1077,8 +1054,8 @@ static int udf_fill_partdesc_info(struct super_block *sb,
                bitmap->s_extPosition = le32_to_cpu(
                                phd->freedSpaceBitmap.extPosition);
                map->s_partition_flags |= UDF_PART_FLAG_FREED_BITMAP;
-                udf_debug("freedSpaceBitmap (part %d) @ %d\n", p_index,
+                udf_debug("freedSpaceBitmap (part %d) @ %d\n",
-                                        bitmap->s_extPosition);
+                          p_index, bitmap->s_extPosition);
        }
        return 0;
 }
@@ -1118,11 +1095,9 @@ static int udf_load_vat(struct super_block *sb, int p_index, int type1_index)
        udf_find_vat_block(sb, p_index, type1_index, sbi->s_last_block);
        if (!sbi->s_vat_inode &&
            sbi->s_last_block != blocks - 1) {
-                printk(KERN_NOTICE "UDF-fs: Failed to read VAT inode from the"
+                pr_notice("Failed to read VAT inode from the last recorded block (%lu), retrying with the last block of the device (%lu).\n",
-                       " last recorded block (%lu), retrying with the last "
+                          (unsigned long)sbi->s_last_block,
-                       "block of the device (%lu).\n",
+                          (unsigned long)blocks - 1);
-                       (unsigned long)sbi->s_last_block,
-                       (unsigned long)blocks - 1);
                udf_find_vat_block(sb, p_index, type1_index, blocks - 1);
        }
        if (!sbi->s_vat_inode)
@@ -1220,8 +1195,8 @@ static int udf_load_partdesc(struct super_block *sb, sector_t block)
        if (map->s_partition_type == UDF_METADATA_MAP25) {
                ret = udf_load_metadata_files(sb, i);
                if (ret) {
-                        printk(KERN_ERR "UDF-fs: error loading MetaData "
+                        udf_err(sb, "error loading MetaData partition map %d\n",
-                        "partition map %d\n", i);
+                                i);
                        goto out_bh;
                }
        } else {
@@ -1234,9 +1209,7 @@ static int udf_load_partdesc(struct super_block *sb, sector_t block)
                 * overwrite blocks instead of relocating them).
                 */
                sb->s_flags |= MS_RDONLY;
-                printk(KERN_NOTICE "UDF-fs: Filesystem marked read-only "
+                pr_notice("Filesystem marked read-only because writing to pseudooverwrite partition is not implemented\n");
-                        "because writing to pseudooverwrite partition is "
-                        "not implemented.\n");
        }
 out_bh:
        /* In case loading failed, we handle cleanup in udf_fill_super */
@@ -1344,9 +1317,8 @@ static int udf_load_logicalvol(struct super_block *sb, sector_t block,
                                struct metadataPartitionMap *mdm =
                                                (struct metadataPartitionMap *)
                                                &(lvd->partitionMaps[offset]);
-                                udf_debug("Parsing Logical vol part %d "
+                                udf_debug("Parsing Logical vol part %d type %d  id=%s\n",
-                                        "type %d  id=%s\n", i, type,
+                                          i, type, UDF_ID_METADATA);
-                                        UDF_ID_METADATA);
                                map->s_partition_type = UDF_METADATA_MAP25;
                                map->s_partition_func = udf_get_pblock_meta25;
@@ -1361,25 +1333,24 @@ static int udf_load_logicalvol(struct super_block *sb, sector_t block,
                                        le32_to_cpu(mdm->allocUnitSize);
                                mdata->s_align_unit_size =
                                        le16_to_cpu(mdm->alignUnitSize);
-                                mdata->s_dup_md_flag     =
+                                if (mdm->flags & 0x01)
-                                        mdm->flags & 0x01;
+                                        mdata->s_flags |= MF_DUPLICATE_MD;
                                udf_debug("Metadata Ident suffix=0x%x\n",
-                                        (le16_to_cpu(
+                                          le16_to_cpu(*(__le16 *)
-                                         ((__le16 *)
+                                                      mdm->partIdent.identSuffix));
-                                              mdm->partIdent.identSuffix)[0])));
                                udf_debug("Metadata part num=%d\n",
-                                        le16_to_cpu(mdm->partitionNum));
+                                          le16_to_cpu(mdm->partitionNum));
                                udf_debug("Metadata part alloc unit size=%d\n",
-                                        le32_to_cpu(mdm->allocUnitSize));
+                                          le32_to_cpu(mdm->allocUnitSize));
                                udf_debug("Metadata file loc=%d\n",
-                                        le32_to_cpu(mdm->metadataFileLoc));
+                                          le32_to_cpu(mdm->metadataFileLoc));
                                udf_debug("Mirror file loc=%d\n",
-                                       le32_to_cpu(mdm->metadataMirrorFileLoc));
+                                          le32_to_cpu(mdm->metadataMirrorFileLoc));
                                udf_debug("Bitmap file loc=%d\n",
-                                       le32_to_cpu(mdm->metadataBitmapFileLoc));
+                                          le32_to_cpu(mdm->metadataBitmapFileLoc));
-                                udf_debug("Duplicate Flag: %d %d\n",
+                                udf_debug("Flags: %d %d\n",
-                                        mdata->s_dup_md_flag, mdm->flags);
+                                          mdata->s_flags, mdm->flags);
                        } else {
                                udf_debug("Unknown ident: %s\n",
                                          upm2->partIdent.ident);
@@ -1389,16 +1360,15 @@ static int udf_load_logicalvol(struct super_block *sb, sector_t block,
                        map->s_partition_num = le16_to_cpu(upm2->partitionNum);
                }
                udf_debug("Partition (%d:%d) type %d on volume %d\n",
-                          i, map->s_partition_num, type,
+                          i, map->s_partition_num, type, map->s_volumeseqnum);
-                          map->s_volumeseqnum);
        }
        if (fileset) {
                struct long_ad *la = (struct long_ad *)&(lvd->logicalVolContentsUse[0]);
                *fileset = lelb_to_cpu(la->extLocation);
-                udf_debug("FileSet found in LogicalVolDesc at block=%d, "
+                udf_debug("FileSet found in LogicalVolDesc at block=%d, partition=%d\n",
-                          "partition=%d\n", fileset->logicalBlockNum,
+                          fileset->logicalBlockNum,
                          fileset->partitionReferenceNum);
        }
        if (lvd->integritySeqExt.extLength)
@@ -1478,9 +1448,9 @@ static noinline int udf_process_sequence(struct super_block *sb, long block,
                bh = udf_read_tagged(sb, block, block, &ident);
                if (!bh) {
-                        printk(KERN_ERR "udf: Block %Lu of volume descriptor "
+                        udf_err(sb,
-                               "sequence is corrupted or we could not read "
+                                "Block %llu of volume descriptor sequence is corrupted or we could not read it\n",
-                               "it.\n", (unsigned long long)block);
+                                (unsigned long long)block);
                        return 1;
                }
@@ -1553,7 +1523,7 @@ static noinline int udf_process_sequence(struct super_block *sb, long block,
         * in a suitable order
         */
        if (!vds[VDS_POS_PRIMARY_VOL_DESC].block) {
-                printk(KERN_ERR "udf: Primary Volume Descriptor not found!\n");
+                udf_err(sb, "Primary Volume Descriptor not found!\n");
                return 1;
        }
        if (udf_load_pvoldesc(sb, vds[VDS_POS_PRIMARY_VOL_DESC].block))
@@ -1740,7 +1710,7 @@ static int udf_load_vrs(struct super_block *sb, struct udf_options *uopt,
        if (!sb_set_blocksize(sb, uopt->blocksize)) {
                if (!silent)
-                        printk(KERN_WARNING "UDF-fs: Bad block size\n");
+                        udf_warn(sb, "Bad block size\n");
                return 0;
        }
        sbi->s_last_block = uopt->lastblock;
@@ -1749,12 +1719,11 @@ static int udf_load_vrs(struct super_block *sb, struct udf_options *uopt,
                nsr_off = udf_check_vsd(sb);
                if (!nsr_off) {
                        if (!silent)
-                                printk(KERN_WARNING "UDF-fs: No VRS found\n");
+                                udf_warn(sb, "No VRS found\n");
                        return 0;
                }
                if (nsr_off == -1)
-                        udf_debug("Failed to read byte 32768. Assuming open "
+                        udf_debug("Failed to read byte 32768. Assuming open disc. Skipping validity check\n");
-                                  "disc. Skipping validity check\n");
                if (!sbi->s_last_block)
                        sbi->s_last_block = udf_get_last_block(sb);
        } else {
@@ -1765,7 +1734,7 @@ static int udf_load_vrs(struct super_block *sb, struct udf_options *uopt,
        sbi->s_anchor = uopt->anchor;
        if (!udf_find_anchor(sb, fileset)) {
                if (!silent)
-                        printk(KERN_WARNING "UDF-fs: No anchor found\n");
+                        udf_warn(sb, "No anchor found\n");
                return 0;
        }
        return 1;
@@ -1937,8 +1906,7 @@ static int udf_fill_super(struct super_block *sb, void *options, int silent)
        if (uopt.flags & (1 << UDF_FLAG_UTF8) &&
            uopt.flags & (1 << UDF_FLAG_NLS_MAP)) {
-                udf_error(sb, "udf_read_super",
+                udf_err(sb, "utf8 cannot be combined with iocharset\n");
-                          "utf8 cannot be combined with iocharset\n");
                goto error_out;
        }
 #ifdef CONFIG_UDF_NLS
@@ -1987,15 +1955,14 @@ static int udf_fill_super(struct super_block *sb, void *options, int silent)
                ret = udf_load_vrs(sb, &uopt, silent, &fileset);
                if (!ret && uopt.blocksize != UDF_DEFAULT_BLOCKSIZE) {
                        if (!silent)
-                                printk(KERN_NOTICE
+                                pr_notice("Rescanning with blocksize %d\n",
-                                       "UDF-fs: Rescanning with blocksize "
+                                          UDF_DEFAULT_BLOCKSIZE);
-                                       "%d\n", UDF_DEFAULT_BLOCKSIZE);
                        uopt.blocksize = UDF_DEFAULT_BLOCKSIZE;
                        ret = udf_load_vrs(sb, &uopt, silent, &fileset);
                }
        }
        if (!ret) {
-                printk(KERN_WARNING "UDF-fs: No partition found (1)\n");
+                udf_warn(sb, "No partition found (1)\n");
                goto error_out;
        }
@@ -2010,10 +1977,9 @@ static int udf_fill_super(struct super_block *sb, void *options, int silent)
                                le16_to_cpu(lvidiu->maxUDFWriteRev); */
                if (minUDFReadRev > UDF_MAX_READ_VERSION) {
-                        printk(KERN_ERR "UDF-fs: minUDFReadRev=%x "
+                        udf_err(sb, "minUDFReadRev=%x (max is %x)\n",
-                                        "(max is %x)\n",
+                                le16_to_cpu(lvidiu->minUDFReadRev),
-                               le16_to_cpu(lvidiu->minUDFReadRev),
+                                UDF_MAX_READ_VERSION);
-                               UDF_MAX_READ_VERSION);
                        goto error_out;
                } else if (minUDFWriteRev > UDF_MAX_WRITE_VERSION)
                        sb->s_flags |= MS_RDONLY;
@@ -2027,28 +1993,27 @@ static int udf_fill_super(struct super_block *sb, void *options, int silent)
        }
        if (!sbi->s_partitions) {
-                printk(KERN_WARNING "UDF-fs: No partition found (2)\n");
+                udf_warn(sb, "No partition found (2)\n");
                goto error_out;
        }
        if (sbi->s_partmaps[sbi->s_partition].s_partition_flags &
                        UDF_PART_FLAG_READ_ONLY) {
-                printk(KERN_NOTICE "UDF-fs: Partition marked readonly; "
+                pr_notice("Partition marked readonly; forcing readonly mount\n");
-                                   "forcing readonly mount\n");
                sb->s_flags |= MS_RDONLY;
        }
        if (udf_find_fileset(sb, &fileset, &rootdir)) {
-                printk(KERN_WARNING "UDF-fs: No fileset found\n");
+                udf_warn(sb, "No fileset found\n");
                goto error_out;
        }
        if (!silent) {
                struct timestamp ts;
                udf_time_to_disk_stamp(&ts, sbi->s_record_time);
-                udf_info("UDF: Mounting volume '%s', "
+                udf_info("Mounting volume '%s', timestamp %04u/%02u/%02u %02u:%02u (%x)\n",
-                         "timestamp %04u/%02u/%02u %02u:%02u (%x)\n",
+                         sbi->s_volume_ident,
-                         sbi->s_volume_ident, le16_to_cpu(ts.year), ts.month, ts.day,
+                         le16_to_cpu(ts.year), ts.month, ts.day,
                         ts.hour, ts.minute, le16_to_cpu(ts.typeAndTimezone));
        }
        if (!(sb->s_flags & MS_RDONLY))
@@ -2059,8 +2024,7 @@ static int udf_fill_super(struct super_block *sb, void *options, int silent)
        /* perhaps it's not extensible enough, but for now ... */
        inode = udf_iget(sb, &rootdir);
        if (!inode) {
-                printk(KERN_ERR "UDF-fs: Error in udf_iget, block=%d, "
+                udf_err(sb, "Error in udf_iget, block=%d, partition=%d\n",
-                                "partition=%d\n",
                       rootdir.logicalBlockNum, rootdir.partitionReferenceNum);
                goto error_out;
        }
@@ -2068,7 +2032,7 @@ static int udf_fill_super(struct super_block *sb, void *options, int silent)
        /* Allocate a dentry for the root inode */
        sb->s_root = d_alloc_root(inode);
        if (!sb->s_root) {
-                printk(KERN_ERR "UDF-fs: Couldn't allocate root dentry\n");
+                udf_err(sb, "Couldn't allocate root dentry\n");
                iput(inode);
                goto error_out;
        }
@@ -2096,32 +2060,40 @@ error_out:
        return -EINVAL;
 }
-static void udf_error(struct super_block *sb, const char *function,
+void _udf_err(struct super_block *sb, const char *function,
-                      const char *fmt, ...)
+              const char *fmt, ...)
 {
+        struct va_format vaf;
        va_list args;
-        if (!(sb->s_flags & MS_RDONLY)) {
+        /* mark sb error */
-                /* mark sb error */
+        if (!(sb->s_flags & MS_RDONLY))
                sb->s_dirt = 1;
-        }
        va_start(args, fmt);
-        vsnprintf(error_buf, sizeof(error_buf), fmt, args);
+        vaf.fmt = fmt;
+        vaf.va = &args;
+        pr_err("error (device %s): %s: %pV", sb->s_id, function, &vaf);
        va_end(args);
-        printk(KERN_CRIT "UDF-fs error (device %s): %s: %s\n",
-                sb->s_id, function, error_buf);
 }
-void udf_warning(struct super_block *sb, const char *function,
+void _udf_warn(struct super_block *sb, const char *function,
-                 const char *fmt, ...)
+               const char *fmt, ...)
 {
+        struct va_format vaf;
        va_list args;
        va_start(args, fmt);
-        vsnprintf(error_buf, sizeof(error_buf), fmt, args);
+        vaf.fmt = fmt;
+        vaf.va = &args;
+        pr_warn("warning (device %s): %s: %pV", sb->s_id, function, &vaf);
        va_end(args);
-        printk(KERN_WARNING "UDF-fs warning (device %s): %s: %s\n",
-               sb->s_id, function, error_buf);
 }
 static void udf_put_super(struct super_block *sb)
@@ -2213,11 +2185,11 @@ static unsigned int udf_count_free_bitmap(struct super_block *sb,
        bh = udf_read_ptagged(sb, &loc, 0, &ident);
        if (!bh) {
-                printk(KERN_ERR "udf: udf_count_free failed\n");
+                udf_err(sb, "udf_count_free failed\n");
                goto out;
        } else if (ident != TAG_IDENT_SBD) {
                brelse(bh);
-                printk(KERN_ERR "udf: udf_count_free failed\n");
+                udf_err(sb, "udf_count_free failed\n");
                goto out;
        }
diff --git a/fs/udf/truncate.c b/fs/udf/truncate.c
index 8424308db4b4..4b98fee8e161 100644
--- a/fs/udf/truncate.c
+++ b/fs/udf/truncate.c
@@ -95,23 +95,21 @@ void udf_truncate_tail_extent(struct inode *inode)
                lbcount += elen;
                if (lbcount > inode->i_size) {
                        if (lbcount - inode->i_size >= inode->i_sb->s_blocksize)
-                                printk(KERN_WARNING
+                                udf_warn(inode->i_sb,
-                                       "udf_truncate_tail_extent(): Too long "
+                                         "Too long extent after EOF in inode %u: i_size: %lld lbcount: %lld extent %u+%u\n",
-                                       "extent after EOF in inode %u: i_size: "
+                                         (unsigned)inode->i_ino,
-                                       "%Ld lbcount: %Ld extent %u+%u\n",
+                                         (long long)inode->i_size,
-                                       (unsigned)inode->i_ino,
+                                         (long long)lbcount,
-                                       (long long)inode->i_size,
+                                         (unsigned)eloc.logicalBlockNum,
-                                       (long long)lbcount,
+                                         (unsigned)elen);
-                                       (unsigned)eloc.logicalBlockNum,
-                                       (unsigned)elen);
                        nelen = elen - (lbcount - inode->i_size);
                        epos.offset -= adsize;
                        extent_trunc(inode, &epos, &eloc, etype, elen, nelen);
                        epos.offset += adsize;
                        if (udf_next_aext(inode, &epos, &eloc, &elen, 1) != -1)
-                                printk(KERN_ERR "udf_truncate_tail_extent(): "
+                                udf_err(inode->i_sb,
-                                       "Extent after EOF in inode %u.\n",
+                                        "Extent after EOF in inode %u\n",
-                                       (unsigned)inode->i_ino);
+                                        (unsigned)inode->i_ino);
                        break;
                }
        }
diff --git a/fs/udf/udf_sb.h b/fs/udf/udf_sb.h
index 4858c191242b..5142a82e3276 100644
--- a/fs/udf/udf_sb.h
+++ b/fs/udf/udf_sb.h
@@ -54,13 +54,16 @@
 #pragma pack(1) /* XXX(hch): Why?  This file just defines in-core structures */
+#define MF_DUPLICATE_MD         0x01
+#define MF_MIRROR_FE_LOADED     0x02
 struct udf_meta_data {
        __u32   s_meta_file_loc;
        __u32   s_mirror_file_loc;
        __u32   s_bitmap_file_loc;
        __u32   s_alloc_unit_size;
        __u16   s_align_unit_size;
-        __u8    s_dup_md_flag;
+        int     s_flags;
        struct inode *s_metadata_fe;
        struct inode *s_mirror_fe;
        struct inode *s_bitmap_fe;
diff --git a/fs/udf/udfdecl.h b/fs/udf/udfdecl.h
index dc8a8dcc5ae1..f34e6fc0cdaa 100644
--- a/fs/udf/udfdecl.h
+++ b/fs/udf/udfdecl.h
@@ -1,6 +1,8 @@
 #ifndef __UDF_DECL_H
 #define __UDF_DECL_H
+#define pr_fmt(fmt) "UDF-fs: " fmt
 #include "ecma_167.h"
 #include "osta_udf.h"
@@ -16,23 +18,30 @@
 #define UDF_PREALLOCATE
 #define UDF_DEFAULT_PREALLOC_BLOCKS     8
+extern __printf(3, 4) void _udf_err(struct super_block *sb,
+                const char *function, const char *fmt, ...);
+#define udf_err(sb, fmt, ...)                                   \
+        _udf_err(sb, __func__, fmt, ##__VA_ARGS__)
+extern __printf(3, 4) void _udf_warn(struct super_block *sb,
+                const char *function, const char *fmt, ...);
+#define udf_warn(sb, fmt, ...)                                  \
+        _udf_warn(sb, __func__, fmt, ##__VA_ARGS__)
+#define udf_info(fmt, ...)                                      \
+        pr_info("INFO " fmt, ##__VA_ARGS__)
 #undef UDFFS_DEBUG
 #ifdef UDFFS_DEBUG
-#define udf_debug(f, a...) \
+#define udf_debug(fmt, ...)                                     \
-do { \
+        printk(KERN_DEBUG pr_fmt("%s:%d:%s: " fmt),             \
-        printk(KERN_DEBUG "UDF-fs DEBUG %s:%d:%s: ", \
+               __FILE__, __LINE__, __func__, ##__VA_ARGS__)
-                __FILE__, __LINE__, __func__); \
-        printk(f, ##a); \
-} while (0)
 #else
-#define udf_debug(f, a...) /**/
+#define udf_debug(fmt, ...)                                     \
+        no_printk(fmt, ##__VA_ARGS__)
 #endif
-#define udf_info(f, a...) \
-        printk(KERN_INFO "UDF-fs INFO " f, ##a);
 #define udf_fixed_to_variable(x) ( ( ( (x) >> 5 ) * 39 ) + ( (x) & 0x0000001F ) )
 #define udf_variable_to_fixed(x) ( ( ( (x) / 39 ) << 5 ) + ( (x) % 39 ) )
@@ -112,8 +121,6 @@ struct extent_position {
 /* super.c */
-extern __printf(3, 4) void udf_warning(struct super_block *, const char *,
-                                        const char *, ...);
 static inline void udf_updated_lvid(struct super_block *sb)
 {
        struct buffer_head *bh = UDF_SB(sb)->s_lvid_bh;
@@ -126,6 +133,8 @@ static inline void udf_updated_lvid(struct super_block *sb)
        UDF_SB(sb)->s_lvid_dirty = 1;
 }
 extern u64 lvid_get_unique_id(struct super_block *sb);
+struct inode *udf_find_metadata_inode_efe(struct super_block *sb,
+                                        u32 meta_file_loc, u32 partition_num);
 /* namei.c */
 extern int udf_write_fi(struct inode *inode, struct fileIdentDesc *,
diff --git a/fs/udf/udftime.c b/fs/udf/udftime.c
index b8c828c4d200..1f11483eba6a 100644
--- a/fs/udf/udftime.c
+++ b/fs/udf/udftime.c
@@ -34,9 +34,10 @@
 * http://www.boulder.nist.gov/timefreq/pubs/bulletin/leapsecond.htm
 */
+#include "udfdecl.h"
 #include <linux/types.h>
 #include <linux/kernel.h>
-#include "udfdecl.h"
 #define EPOCH_YEAR 1970
diff --git a/fs/udf/unicode.c b/fs/udf/unicode.c
index d03a90b6ad69..44b815e57f94 100644
--- a/fs/udf/unicode.c
+++ b/fs/udf/unicode.c
@@ -114,7 +114,7 @@ int udf_CS0toUTF8(struct ustr *utf_o, const struct ustr *ocu_i)
        cmp_id = ocu_i->u_cmpID;
        if (cmp_id != 8 && cmp_id != 16) {
                memset(utf_o, 0, sizeof(struct ustr));
-                printk(KERN_ERR "udf: unknown compression code (%d) stri=%s\n",
+                pr_err("unknown compression code (%d) stri=%s\n",
                       cmp_id, ocu_i->u_name);
                return 0;
        }
@@ -242,7 +242,7 @@ try_again:
        if (utf_cnt) {
 error_out:
                ocu[++u_len] = '?';
-                printk(KERN_DEBUG "udf: bad UTF-8 character\n");
+                printk(KERN_DEBUG pr_fmt("bad UTF-8 character\n"));
        }
        ocu[length - 1] = (uint8_t)u_len + 1;
@@ -267,7 +267,7 @@ static int udf_CS0toNLS(struct nls_table *nls, struct ustr *utf_o,
        cmp_id = ocu_i->u_cmpID;
        if (cmp_id != 8 && cmp_id != 16) {
                memset(utf_o, 0, sizeof(struct ustr));
-                printk(KERN_ERR "udf: unknown compression code (%d) stri=%s\n",
+                pr_err("unknown compression code (%d) stri=%s\n",
                       cmp_id, ocu_i->u_name);
                return 0;
        }
diff --git a/fs/ufs/ialloc.c b/fs/ufs/ialloc.c
index 2eabf04af3de..78a4c70d46b5 100644
--- a/fs/ufs/ialloc.c
+++ b/fs/ufs/ialloc.c
@@ -341,7 +341,7 @@ cg_found:
 fail_remove_inode:
        unlock_super(sb);
-        inode->i_nlink = 0;
+        clear_nlink(inode);
        iput(inode);
        UFSD("EXIT (FAILED): err %d\n", err);
        return ERR_PTR(err);
diff --git a/fs/ufs/inode.c b/fs/ufs/inode.c
index b4d791a83207..879b13436fa4 100644
--- a/fs/ufs/inode.c
+++ b/fs/ufs/inode.c
@@ -589,7 +589,7 @@ static int ufs1_read_inode(struct inode *inode, struct ufs_inode *ufs_inode)
         * Copy data to the in-core inode.
         */
        inode->i_mode = mode = fs16_to_cpu(sb, ufs_inode->ui_mode);
-        inode->i_nlink = fs16_to_cpu(sb, ufs_inode->ui_nlink);
+        set_nlink(inode, fs16_to_cpu(sb, ufs_inode->ui_nlink));
        if (inode->i_nlink == 0) {
                ufs_error (sb, "ufs_read_inode", "inode %lu has zero nlink\n", inode->i_ino);
                return -1;
@@ -637,7 +637,7 @@ static int ufs2_read_inode(struct inode *inode, struct ufs2_inode *ufs2_inode)
         * Copy data to the in-core inode.
         */
        inode->i_mode = mode = fs16_to_cpu(sb, ufs2_inode->ui_mode);
-        inode->i_nlink = fs16_to_cpu(sb, ufs2_inode->ui_nlink);
+        set_nlink(inode, fs16_to_cpu(sb, ufs2_inode->ui_nlink));
        if (inode->i_nlink == 0) {
                ufs_error (sb, "ufs_read_inode", "inode %lu has zero nlink\n", inode->i_ino);
                return -1;
diff --git a/fs/xfs/xfs_iops.c b/fs/xfs/xfs_iops.c
index 9ba2a07b7343..23ce927973a4 100644
--- a/fs/xfs/xfs_iops.c
+++ b/fs/xfs/xfs_iops.c
@@ -1153,7 +1153,7 @@ xfs_setup_inode(
        hlist_add_fake(&inode->i_hash);
        inode->i_mode   = ip->i_d.di_mode;
-        inode->i_nlink  = ip->i_d.di_nlink;
+        set_nlink(inode, ip->i_d.di_nlink);
        inode->i_uid    = ip->i_d.di_uid;
        inode->i_gid    = ip->i_d.di_gid;
diff --git a/include/linux/clksrc-dbx500-prcmu.h b/include/linux/clksrc-dbx500-prcmu.h
new file mode 100644
index 000000000000..4fb8119c49e4
--- /dev/null
+++ b/include/linux/clksrc-dbx500-prcmu.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2011
+ *
+ * License Terms: GNU General Public License v2
+ * Author: Mattias Wallin <mattias.wallin@stericsson.com>
+ *
+ */
+#ifndef __CLKSRC_DBX500_PRCMU_H
+#define __CLKSRC_DBX500_PRCMU_H
+#include <linux/init.h>
+#include <linux/io.h>
+#ifdef CONFIG_CLKSRC_DBX500_PRCMU
+void __init clksrc_dbx500_prcmu_init(void __iomem *base);
+#else
+static inline void __init clksrc_dbx500_prcmu_init(void __iomem *base) {}
+#endif
+#endif
diff --git a/include/linux/dcache.h b/include/linux/dcache.h
index 62157c03caf7..4df926199369 100644
--- a/include/linux/dcache.h
+++ b/include/linux/dcache.h
@@ -165,6 +165,7 @@ struct dentry_operations {
                        unsigned int, const char *, const struct qstr *);
        int (*d_delete)(const struct dentry *);
        void (*d_release)(struct dentry *);
+        void (*d_prune)(struct dentry *);
        void (*d_iput)(struct dentry *, struct inode *);
        char *(*d_dname)(struct dentry *, char *, int);
        struct vfsmount *(*d_automount)(struct path *);
@@ -184,8 +185,9 @@ struct dentry_operations {
 #define DCACHE_OP_COMPARE       0x0002
 #define DCACHE_OP_REVALIDATE    0x0004
 #define DCACHE_OP_DELETE        0x0008
+#define DCACHE_OP_PRUNE         0x0010
-#define DCACHE_DISCONNECTED     0x0010
+#define DCACHE_DISCONNECTED     0x0020
     /* This dentry is possibly not currently connected to the dcache tree, in
      * which case its parent will either be itself, or will have this flag as
      * well.  nfsd will not use a dentry with this bit set, but will first
@@ -196,8 +198,8 @@ struct dentry_operations {
      * dentry into place and return that dentry rather than the passed one,
      * typically using d_splice_alias. */
-#define DCACHE_REFERENCED       0x0020  /* Recently used, don't discard. */
+#define DCACHE_REFERENCED       0x0040  /* Recently used, don't discard. */
-#define DCACHE_RCUACCESS        0x0040  /* Entry has ever been RCU-visible */
+#define DCACHE_RCUACCESS        0x0080  /* Entry has ever been RCU-visible */
 #define DCACHE_CANT_MOUNT       0x0100
 #define DCACHE_GENOCIDE         0x0200
diff --git a/include/linux/ext2_fs.h b/include/linux/ext2_fs.h
index 53792bf36c71..ce1b719e8bd4 100644
--- a/include/linux/ext2_fs.h
+++ b/include/linux/ext2_fs.h
@@ -197,8 +197,8 @@ struct ext2_group_desc
 /* Flags that should be inherited by new inodes from their parent. */
 #define EXT2_FL_INHERITED (EXT2_SECRM_FL | EXT2_UNRM_FL | EXT2_COMPR_FL |\
-                           EXT2_SYNC_FL | EXT2_IMMUTABLE_FL | EXT2_APPEND_FL |\
+                           EXT2_SYNC_FL | EXT2_NODUMP_FL |\
-                           EXT2_NODUMP_FL | EXT2_NOATIME_FL | EXT2_COMPRBLK_FL|\
+                           EXT2_NOATIME_FL | EXT2_COMPRBLK_FL |\
                           EXT2_NOCOMP_FL | EXT2_JOURNAL_DATA_FL |\
                           EXT2_NOTAIL_FL | EXT2_DIRSYNC_FL)
diff --git a/include/linux/ext3_fs.h b/include/linux/ext3_fs.h
index 81965cce6bfa..dec99116a0e4 100644
--- a/include/linux/ext3_fs.h
+++ b/include/linux/ext3_fs.h
@@ -180,8 +180,8 @@ struct ext3_group_desc
 /* Flags that should be inherited by new inodes from their parent. */
 #define EXT3_FL_INHERITED (EXT3_SECRM_FL | EXT3_UNRM_FL | EXT3_COMPR_FL |\
-                           EXT3_SYNC_FL | EXT3_IMMUTABLE_FL | EXT3_APPEND_FL |\
+                           EXT3_SYNC_FL | EXT3_NODUMP_FL |\
-                           EXT3_NODUMP_FL | EXT3_NOATIME_FL | EXT3_COMPRBLK_FL|\
+                           EXT3_NOATIME_FL | EXT3_COMPRBLK_FL |\
                           EXT3_NOCOMPR_FL | EXT3_JOURNAL_DATA_FL |\
                           EXT3_NOTAIL_FL | EXT3_DIRSYNC_FL)
@@ -381,7 +381,7 @@ struct ext3_inode {
 * Mount flags
 */
 #define EXT3_MOUNT_CHECK                0x00001 /* Do mount-time checks */
-#define EXT3_MOUNT_OLDALLOC             0x00002  /* Don't use the new Orlov allocator */
+/* EXT3_MOUNT_OLDALLOC was there */
 #define EXT3_MOUNT_GRPID                0x00004 /* Create files with directory's group */
 #define EXT3_MOUNT_DEBUG                0x00008 /* Some debugging messages */
 #define EXT3_MOUNT_ERRORS_CONT          0x00010 /* Continue on errors */
diff --git a/include/linux/ext3_fs_sb.h b/include/linux/ext3_fs_sb.h
index 258088ab3c6b..64365252f1b0 100644
--- a/include/linux/ext3_fs_sb.h
+++ b/include/linux/ext3_fs_sb.h
@@ -76,10 +76,6 @@ struct ext3_sb_info {
        struct mutex s_resize_lock;
        unsigned long s_commit_interval;
        struct block_device *journal_bdev;
-#ifdef CONFIG_JBD_DEBUG
-        struct timer_list turn_ro_timer;        /* For turning read-only (crash simulation) */
-        wait_queue_head_t ro_wait_queue;        /* For people waiting for the fs to go read-only */
-#endif
 #ifdef CONFIG_QUOTA
        char *s_qf_names[MAXQUOTAS];            /* Names of quota files with journalled quota */
        int s_jquota_fmt;                       /* Format of quota to use */
diff --git a/include/linux/fs.h b/include/linux/fs.h
index 7a049fd2aa4c..0c4df261af7e 100644
--- a/include/linux/fs.h
+++ b/include/linux/fs.h
@@ -768,14 +768,25 @@ struct inode {
        /* Stat data, not accessed from path walking */
        unsigned long           i_ino;
-        unsigned int            i_nlink;
+        /*
+         * Filesystems may only read i_nlink directly.  They shall use the
+         * following functions for modification:
+         *
+         *    (set|clear|inc|drop)_nlink
+         *    inode_(inc|dec)_link_count
+         */
+        union {
+                const unsigned int i_nlink;
+                unsigned int __i_nlink;
+        };
        dev_t                   i_rdev;
-        loff_t                  i_size;
        struct timespec         i_atime;
        struct timespec         i_mtime;
        struct timespec         i_ctime;
-        unsigned int            i_blkbits;
+        spinlock_t              i_lock; /* i_blocks, i_bytes, maybe i_size */
+        unsigned short          i_bytes;
        blkcnt_t                i_blocks;
+        loff_t                  i_size;
 #ifdef __NEED_I_SIZE_ORDERED
        seqcount_t              i_size_seqcount;
@@ -783,7 +794,6 @@ struct inode {
        /* Misc */
        unsigned long           i_state;
-        spinlock_t              i_lock; /* i_blocks, i_bytes, maybe i_size */
        struct mutex            i_mutex;
        unsigned long           dirtied_when;   /* jiffies of first dirtying */
@@ -797,9 +807,10 @@ struct inode {
                struct rcu_head         i_rcu;
        };
        atomic_t                i_count;
+        unsigned int            i_blkbits;
        u64                     i_version;
-        unsigned short          i_bytes;
        atomic_t                i_dio_count;
+        atomic_t                i_writecount;
        const struct file_operations    *i_fop; /* former ->i_op->default_file_ops */
        struct file_lock        *i_flock;
        struct address_space    i_data;
@@ -823,7 +834,6 @@ struct inode {
 #ifdef CONFIG_IMA
        atomic_t                i_readcount; /* struct files open RO */
 #endif
-        atomic_t                i_writecount;
        void                    *i_private; /* fs or device private pointer */
 };
@@ -1755,6 +1765,19 @@ static inline void mark_inode_dirty_sync(struct inode *inode)
 }
 /**
+ * set_nlink - directly set an inode's link count
+ * @inode: inode
+ * @nlink: new nlink (should be non-zero)
+ *
+ * This is a low-level filesystem helper to replace any
+ * direct filesystem manipulation of i_nlink.
+ */
+static inline void set_nlink(struct inode *inode, unsigned int nlink)
+{
+        inode->__i_nlink = nlink;
+}
+/**
 * inc_nlink - directly increment an inode's link count
 * @inode: inode
 *
@@ -1764,7 +1787,7 @@ static inline void mark_inode_dirty_sync(struct inode *inode)
 */
 static inline void inc_nlink(struct inode *inode)
 {
-        inode->i_nlink++;
+        inode->__i_nlink++;
 }
 static inline void inode_inc_link_count(struct inode *inode)
@@ -1786,7 +1809,7 @@ static inline void inode_inc_link_count(struct inode *inode)
 */
 static inline void drop_nlink(struct inode *inode)
 {
-        inode->i_nlink--;
+        inode->__i_nlink--;
 }
 /**
@@ -1799,7 +1822,7 @@ static inline void drop_nlink(struct inode *inode)
 */
 static inline void clear_nlink(struct inode *inode)
 {
-        inode->i_nlink = 0;
+        inode->__i_nlink = 0;
 }
 static inline void inode_dec_link_count(struct inode *inode)
diff --git a/include/linux/irqdomain.h b/include/linux/irqdomain.h
index 3ad553e8eae2..99834e581b9e 100644
--- a/include/linux/irqdomain.h
+++ b/include/linux/irqdomain.h
@@ -47,6 +47,7 @@ struct irq_domain_ops {
 *            of the irq_domain is responsible for allocating the array of
 *            irq_desc structures.
 * @nr_irq: Number of irqs managed by the irq domain
+ * @hwirq_base: Starting number for hwirqs managed by the irq domain
 * @ops: pointer to irq_domain methods
 * @priv: private data pointer for use by owner.  Not touched by irq_domain
 *        core code.
@@ -57,6 +58,7 @@ struct irq_domain {
        struct list_head list;
        unsigned int irq_base;
        unsigned int nr_irq;
+        unsigned int hwirq_base;
        const struct irq_domain_ops *ops;
        void *priv;
        struct device_node *of_node;
@@ -72,9 +74,21 @@ struct irq_domain {
 static inline unsigned int irq_domain_to_irq(struct irq_domain *d,
                                             unsigned long hwirq)
 {
-        return d->ops->to_irq ? d->ops->to_irq(d, hwirq) : d->irq_base + hwirq;
+        if (d->ops->to_irq)
+                return d->ops->to_irq(d, hwirq);
+        if (WARN_ON(hwirq < d->hwirq_base))
+                return 0;
+        return d->irq_base + hwirq - d->hwirq_base;
 }
+#define irq_domain_for_each_hwirq(d, hw) \
+        for (hw = d->hwirq_base; hw < d->hwirq_base + d->nr_irq; hw++)
+#define irq_domain_for_each_irq(d, hw, irq) \
+        for (hw = d->hwirq_base, irq = irq_domain_to_irq(d, hw); \
+             hw < d->hwirq_base + d->nr_irq; \
+             hw++, irq = irq_domain_to_irq(d, hw))
 extern void irq_domain_add(struct irq_domain *domain);
 extern void irq_domain_del(struct irq_domain *domain);
 #endif /* CONFIG_IRQ_DOMAIN */
diff --git a/include/linux/jbd.h b/include/linux/jbd.h
index e6a5e34bed4f..c7acdde3243d 100644
--- a/include/linux/jbd.h
+++ b/include/linux/jbd.h
@@ -244,6 +244,7 @@ typedef struct journal_superblock_s
 #include <linux/fs.h>
 #include <linux/sched.h>
+#include <linux/jbd_common.h>
 #define J_ASSERT(assert)        BUG_ON(!(assert))
@@ -270,69 +271,6 @@ typedef struct journal_superblock_s
 #define J_EXPECT_JH(jh, expr, why...)   __journal_expect(expr, ## why)
 #endif
-enum jbd_state_bits {
-        BH_JBD                  /* Has an attached ext3 journal_head */
-          = BH_PrivateStart,
-        BH_JWrite,              /* Being written to log (@@@ DEBUGGING) */
-        BH_Freed,               /* Has been freed (truncated) */
-        BH_Revoked,             /* Has been revoked from the log */
-        BH_RevokeValid,         /* Revoked flag is valid */
-        BH_JBDDirty,            /* Is dirty but journaled */
-        BH_State,               /* Pins most journal_head state */
-        BH_JournalHead,         /* Pins bh->b_private and jh->b_bh */
-        BH_Unshadow,            /* Dummy bit, for BJ_Shadow wakeup filtering */
-};
-BUFFER_FNS(JBD, jbd)
-BUFFER_FNS(JWrite, jwrite)
-BUFFER_FNS(JBDDirty, jbddirty)
-TAS_BUFFER_FNS(JBDDirty, jbddirty)
-BUFFER_FNS(Revoked, revoked)
-TAS_BUFFER_FNS(Revoked, revoked)
-BUFFER_FNS(RevokeValid, revokevalid)
-TAS_BUFFER_FNS(RevokeValid, revokevalid)
-BUFFER_FNS(Freed, freed)
-static inline struct buffer_head *jh2bh(struct journal_head *jh)
-{
-        return jh->b_bh;
-}
-static inline struct journal_head *bh2jh(struct buffer_head *bh)
-{
-        return bh->b_private;
-}
-static inline void jbd_lock_bh_state(struct buffer_head *bh)
-{
-        bit_spin_lock(BH_State, &bh->b_state);
-}
-static inline int jbd_trylock_bh_state(struct buffer_head *bh)
-{
-        return bit_spin_trylock(BH_State, &bh->b_state);
-}
-static inline int jbd_is_locked_bh_state(struct buffer_head *bh)
-{
-        return bit_spin_is_locked(BH_State, &bh->b_state);
-}
-static inline void jbd_unlock_bh_state(struct buffer_head *bh)
-{
-        bit_spin_unlock(BH_State, &bh->b_state);
-}
-static inline void jbd_lock_bh_journal_head(struct buffer_head *bh)
-{
-        bit_spin_lock(BH_JournalHead, &bh->b_state);
-}
-static inline void jbd_unlock_bh_journal_head(struct buffer_head *bh)
-{
-        bit_spin_unlock(BH_JournalHead, &bh->b_state);
-}
 struct jbd_revoke_table_s;
 /**
diff --git a/include/linux/jbd2.h b/include/linux/jbd2.h
index 38f307b8c334..2092ea21e469 100644
--- a/include/linux/jbd2.h
+++ b/include/linux/jbd2.h
@@ -275,6 +275,7 @@ typedef struct journal_superblock_s
 #include <linux/fs.h>
 #include <linux/sched.h>
+#include <linux/jbd_common.h>
 #define J_ASSERT(assert)        BUG_ON(!(assert))
@@ -302,70 +303,6 @@ typedef struct journal_superblock_s
 #define J_EXPECT_JH(jh, expr, why...)   __journal_expect(expr, ## why)
 #endif
-enum jbd_state_bits {
-        BH_JBD                  /* Has an attached ext3 journal_head */
-          = BH_PrivateStart,
-        BH_JWrite,              /* Being written to log (@@@ DEBUGGING) */
-        BH_Freed,               /* Has been freed (truncated) */
-        BH_Revoked,             /* Has been revoked from the log */
-        BH_RevokeValid,         /* Revoked flag is valid */
-        BH_JBDDirty,            /* Is dirty but journaled */
-        BH_State,               /* Pins most journal_head state */
-        BH_JournalHead,         /* Pins bh->b_private and jh->b_bh */
-        BH_Unshadow,            /* Dummy bit, for BJ_Shadow wakeup filtering */
-        BH_JBDPrivateStart,     /* First bit available for private use by FS */
-};
-BUFFER_FNS(JBD, jbd)
-BUFFER_FNS(JWrite, jwrite)
-BUFFER_FNS(JBDDirty, jbddirty)
-TAS_BUFFER_FNS(JBDDirty, jbddirty)
-BUFFER_FNS(Revoked, revoked)
-TAS_BUFFER_FNS(Revoked, revoked)
-BUFFER_FNS(RevokeValid, revokevalid)
-TAS_BUFFER_FNS(RevokeValid, revokevalid)
-BUFFER_FNS(Freed, freed)
-static inline struct buffer_head *jh2bh(struct journal_head *jh)
-{
-        return jh->b_bh;
-}
-static inline struct journal_head *bh2jh(struct buffer_head *bh)
-{
-        return bh->b_private;
-}
-static inline void jbd_lock_bh_state(struct buffer_head *bh)
-{
-        bit_spin_lock(BH_State, &bh->b_state);
-}
-static inline int jbd_trylock_bh_state(struct buffer_head *bh)
-{
-        return bit_spin_trylock(BH_State, &bh->b_state);
-}
-static inline int jbd_is_locked_bh_state(struct buffer_head *bh)
-{
-        return bit_spin_is_locked(BH_State, &bh->b_state);
-}
-static inline void jbd_unlock_bh_state(struct buffer_head *bh)
-{
-        bit_spin_unlock(BH_State, &bh->b_state);
-}
-static inline void jbd_lock_bh_journal_head(struct buffer_head *bh)
-{
-        bit_spin_lock(BH_JournalHead, &bh->b_state);
-}
-static inline void jbd_unlock_bh_journal_head(struct buffer_head *bh)
-{
-        bit_spin_unlock(BH_JournalHead, &bh->b_state);
-}
 /* Flags in jbd_inode->i_flags */
 #define __JI_COMMIT_RUNNING 0
 /* Commit of the inode data in progress. We use this flag to protect us from
@@ -1106,9 +1043,9 @@ static inline handle_t *journal_current_handle(void)
 */
 extern handle_t *jbd2_journal_start(journal_t *, int nblocks);
-extern handle_t *jbd2__journal_start(journal_t *, int nblocks, int gfp_mask);
+extern handle_t *jbd2__journal_start(journal_t *, int nblocks, gfp_t gfp_mask);
 extern int       jbd2_journal_restart(handle_t *, int nblocks);
-extern int       jbd2__journal_restart(handle_t *, int nblocks, int gfp_mask);
+extern int       jbd2__journal_restart(handle_t *, int nblocks, gfp_t gfp_mask);
 extern int       jbd2_journal_extend (handle_t *, int nblocks);
 extern int       jbd2_journal_get_write_access(handle_t *, struct buffer_head *);
 extern int       jbd2_journal_get_create_access (handle_t *, struct buffer_head *);
diff --git a/include/linux/jbd_common.h b/include/linux/jbd_common.h
new file mode 100644
index 000000000000..6230f8556a4e
--- /dev/null
+++ b/include/linux/jbd_common.h
@@ -0,0 +1,68 @@
+#ifndef _LINUX_JBD_STATE_H
+#define _LINUX_JBD_STATE_H
+enum jbd_state_bits {
+        BH_JBD                  /* Has an attached ext3 journal_head */
+          = BH_PrivateStart,
+        BH_JWrite,              /* Being written to log (@@@ DEBUGGING) */
+        BH_Freed,               /* Has been freed (truncated) */
+        BH_Revoked,             /* Has been revoked from the log */
+        BH_RevokeValid,         /* Revoked flag is valid */
+        BH_JBDDirty,            /* Is dirty but journaled */
+        BH_State,               /* Pins most journal_head state */
+        BH_JournalHead,         /* Pins bh->b_private and jh->b_bh */
+        BH_Unshadow,            /* Dummy bit, for BJ_Shadow wakeup filtering */
+        BH_JBDPrivateStart,     /* First bit available for private use by FS */
+};
+BUFFER_FNS(JBD, jbd)
+BUFFER_FNS(JWrite, jwrite)
+BUFFER_FNS(JBDDirty, jbddirty)
+TAS_BUFFER_FNS(JBDDirty, jbddirty)
+BUFFER_FNS(Revoked, revoked)
+TAS_BUFFER_FNS(Revoked, revoked)
+BUFFER_FNS(RevokeValid, revokevalid)
+TAS_BUFFER_FNS(RevokeValid, revokevalid)
+BUFFER_FNS(Freed, freed)
+static inline struct buffer_head *jh2bh(struct journal_head *jh)
+{
+        return jh->b_bh;
+}
+static inline struct journal_head *bh2jh(struct buffer_head *bh)
+{
+        return bh->b_private;
+}
+static inline void jbd_lock_bh_state(struct buffer_head *bh)
+{
+        bit_spin_lock(BH_State, &bh->b_state);
+}
+static inline int jbd_trylock_bh_state(struct buffer_head *bh)
+{
+        return bit_spin_trylock(BH_State, &bh->b_state);
+}
+static inline int jbd_is_locked_bh_state(struct buffer_head *bh)
+{
+        return bit_spin_is_locked(BH_State, &bh->b_state);
+}
+static inline void jbd_unlock_bh_state(struct buffer_head *bh)
+{
+        bit_spin_unlock(BH_State, &bh->b_state);
+}
+static inline void jbd_lock_bh_journal_head(struct buffer_head *bh)
+{
+        bit_spin_lock(BH_JournalHead, &bh->b_state);
+}
+static inline void jbd_unlock_bh_journal_head(struct buffer_head *bh)
+{
+        bit_spin_unlock(BH_JournalHead, &bh->b_state);
+}
+#endif
diff --git a/include/linux/namei.h b/include/linux/namei.h
index 409328d1cbbb..ffc02135c483 100644
--- a/include/linux/namei.h
+++ b/include/linux/namei.h
@@ -67,6 +67,7 @@ enum {LAST_NORM, LAST_ROOT, LAST_DOT, LAST_DOTDOT, LAST_BIND};
 #define LOOKUP_EMPTY            0x4000
 extern int user_path_at(int, const char __user *, unsigned, struct path *);
+extern int user_path_at_empty(int, const char __user *, unsigned, struct path *, int *empty);
 #define user_path(name, path) user_path_at(AT_FDCWD, name, LOOKUP_FOLLOW, path)
 #define user_lpath(name, path) user_path_at(AT_FDCWD, name, 0, path)
diff --git a/include/linux/of.h b/include/linux/of.h
index 5dbe263462a9..f01ba8a209c0 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -207,6 +207,11 @@ extern int of_property_read_u64(const struct device_node *np,
 extern int of_property_read_string(struct device_node *np,
                                   const char *propname,
                                   const char **out_string);
+extern int of_property_read_string_index(struct device_node *np,
+                                         const char *propname,
+                                         int index, const char **output);
+extern int of_property_count_strings(struct device_node *np,
+                                     const char *propname);
 extern int of_device_is_compatible(const struct device_node *device,
                                   const char *);
 extern int of_device_is_available(const struct device_node *device);
@@ -283,6 +288,19 @@ static inline int of_property_read_string(struct device_node *np,
        return -ENOSYS;
 }
+static inline int of_property_read_string_index(struct device_node *np,
+                                                const char *propname, int index,
+                                                const char **out_string)
+{
+        return -ENOSYS;
+}
+static inline int of_property_count_strings(struct device_node *np,
+                                            const char *propname)
+{
+        return -ENOSYS;
+}
 static inline const void *of_get_property(const struct device_node *node,
                                const char *name,
                                int *lenp)
diff --git a/include/linux/of_irq.h b/include/linux/of_irq.h
index cd2e61ce4e83..d0307eed20c9 100644
--- a/include/linux/of_irq.h
+++ b/include/linux/of_irq.h
@@ -33,6 +33,8 @@ struct of_irq {
        u32 specifier[OF_MAX_IRQ_SPEC]; /* Specifier copy */
 };
+typedef int (*of_irq_init_cb_t)(struct device_node *, struct device_node *);
 /*
 * Workarounds only applied to 32bit powermac machines
 */
@@ -73,6 +75,7 @@ extern int of_irq_to_resource_table(struct device_node *dev,
                struct resource *res, int nr_irqs);
 extern struct device_node *of_irq_find_parent(struct device_node *child);
+extern void of_irq_init(const struct of_device_id *matches);
 #endif /* CONFIG_OF_IRQ */
 #endif /* CONFIG_OF */
diff --git a/include/linux/rtc/sirfsoc_rtciobrg.h b/include/linux/rtc/sirfsoc_rtciobrg.h
new file mode 100644
index 000000000000..2c92e1c8e055
--- /dev/null
+++ b/include/linux/rtc/sirfsoc_rtciobrg.h
@@ -0,0 +1,18 @@
+/*
+ * RTC I/O Bridge interfaces for CSR SiRFprimaII
+ * ARM access the registers of SYSRTC, GPSRTC and PWRC through this module
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+#ifndef _SIRFSOC_RTC_IOBRG_H_
+#define _SIRFSOC_RTC_IOBRG_H_
+extern void sirfsoc_rtc_iobrg_besyncing(void);
+extern u32 sirfsoc_rtc_iobrg_readl(u32 addr);
+extern void sirfsoc_rtc_iobrg_writel(u32 val, u32 addr);
+#endif
diff --git a/include/trace/events/ext4.h b/include/trace/events/ext4.h
index b50a54736242..748ff7cbe555 100644
--- a/include/trace/events/ext4.h
+++ b/include/trace/events/ext4.h
@@ -9,9 +9,12 @@
 struct ext4_allocation_context;
 struct ext4_allocation_request;
+struct ext4_extent;
 struct ext4_prealloc_space;
 struct ext4_inode_info;
 struct mpage_da_data;
+struct ext4_map_blocks;
+struct ext4_extent;
 #define EXT4_I(inode) (container_of(inode, struct ext4_inode_info, vfs_inode))
@@ -1032,9 +1035,9 @@ TRACE_EVENT(ext4_forget,
 );
 TRACE_EVENT(ext4_da_update_reserve_space,
-        TP_PROTO(struct inode *inode, int used_blocks),
+        TP_PROTO(struct inode *inode, int used_blocks, int quota_claim),
-        TP_ARGS(inode, used_blocks),
+        TP_ARGS(inode, used_blocks, quota_claim),
        TP_STRUCT__entry(
                __field(        dev_t,  dev                     )
@@ -1045,6 +1048,7 @@ TRACE_EVENT(ext4_da_update_reserve_space,
                __field(        int,    reserved_data_blocks    )
                __field(        int,    reserved_meta_blocks    )
                __field(        int,    allocated_meta_blocks   )
+                __field(        int,    quota_claim             )
        ),
        TP_fast_assign(
@@ -1053,19 +1057,24 @@ TRACE_EVENT(ext4_da_update_reserve_space,
                __entry->mode   = inode->i_mode;
                __entry->i_blocks = inode->i_blocks;
                __entry->used_blocks = used_blocks;
-                __entry->reserved_data_blocks = EXT4_I(inode)->i_reserved_data_blocks;
+                __entry->reserved_data_blocks =
-                __entry->reserved_meta_blocks = EXT4_I(inode)->i_reserved_meta_blocks;
+                                EXT4_I(inode)->i_reserved_data_blocks;
-                __entry->allocated_meta_blocks = EXT4_I(inode)->i_allocated_meta_blocks;
+                __entry->reserved_meta_blocks =
+                                EXT4_I(inode)->i_reserved_meta_blocks;
+                __entry->allocated_meta_blocks =
+                                EXT4_I(inode)->i_allocated_meta_blocks;
+                __entry->quota_claim = quota_claim;
        ),
        TP_printk("dev %d,%d ino %lu mode 0%o i_blocks %llu used_blocks %d "
                  "reserved_data_blocks %d reserved_meta_blocks %d "
-                  "allocated_meta_blocks %d",
+                  "allocated_meta_blocks %d quota_claim %d",
                  MAJOR(__entry->dev), MINOR(__entry->dev),
                  (unsigned long) __entry->ino,
                  __entry->mode, __entry->i_blocks,
                  __entry->used_blocks, __entry->reserved_data_blocks,
-                  __entry->reserved_meta_blocks, __entry->allocated_meta_blocks)
+                  __entry->reserved_meta_blocks, __entry->allocated_meta_blocks,
+                  __entry->quota_claim)
 );
 TRACE_EVENT(ext4_da_reserve_space,
@@ -1386,6 +1395,87 @@ DEFINE_EVENT(ext4__truncate, ext4_truncate_exit,
        TP_ARGS(inode)
 );
+/* 'ux' is the uninitialized extent. */
+TRACE_EVENT(ext4_ext_convert_to_initialized_enter,
+        TP_PROTO(struct inode *inode, struct ext4_map_blocks *map,
+                 struct ext4_extent *ux),
+        TP_ARGS(inode, map, ux),
+        TP_STRUCT__entry(
+                __field(        ino_t,          ino     )
+                __field(        dev_t,          dev     )
+                __field(        ext4_lblk_t,    m_lblk  )
+                __field(        unsigned,       m_len   )
+                __field(        ext4_lblk_t,    u_lblk  )
+                __field(        unsigned,       u_len   )
+                __field(        ext4_fsblk_t,   u_pblk  )
+        ),
+        TP_fast_assign(
+                __entry->ino            = inode->i_ino;
+                __entry->dev            = inode->i_sb->s_dev;
+                __entry->m_lblk         = map->m_lblk;
+                __entry->m_len          = map->m_len;
+                __entry->u_lblk         = le32_to_cpu(ux->ee_block);
+                __entry->u_len          = ext4_ext_get_actual_len(ux);
+                __entry->u_pblk         = ext4_ext_pblock(ux);
+        ),
+        TP_printk("dev %d,%d ino %lu m_lblk %u m_len %u u_lblk %u u_len %u "
+                  "u_pblk %llu",
+                  MAJOR(__entry->dev), MINOR(__entry->dev),
+                  (unsigned long) __entry->ino,
+                  __entry->m_lblk, __entry->m_len,
+                  __entry->u_lblk, __entry->u_len, __entry->u_pblk)
+);
+/*
+ * 'ux' is the uninitialized extent.
+ * 'ix' is the initialized extent to which blocks are transferred.
+ */
+TRACE_EVENT(ext4_ext_convert_to_initialized_fastpath,
+        TP_PROTO(struct inode *inode, struct ext4_map_blocks *map,
+                 struct ext4_extent *ux, struct ext4_extent *ix),
+        TP_ARGS(inode, map, ux, ix),
+        TP_STRUCT__entry(
+                __field(        ino_t,          ino     )
+                __field(        dev_t,          dev     )
+                __field(        ext4_lblk_t,    m_lblk  )
+                __field(        unsigned,       m_len   )
+                __field(        ext4_lblk_t,    u_lblk  )
+                __field(        unsigned,       u_len   )
+                __field(        ext4_fsblk_t,   u_pblk  )
+                __field(        ext4_lblk_t,    i_lblk  )
+                __field(        unsigned,       i_len   )
+                __field(        ext4_fsblk_t,   i_pblk  )
+        ),
+        TP_fast_assign(
+                __entry->ino            = inode->i_ino;
+                __entry->dev            = inode->i_sb->s_dev;
+                __entry->m_lblk         = map->m_lblk;
+                __entry->m_len          = map->m_len;
+                __entry->u_lblk         = le32_to_cpu(ux->ee_block);
+                __entry->u_len          = ext4_ext_get_actual_len(ux);
+                __entry->u_pblk         = ext4_ext_pblock(ux);
+                __entry->i_lblk         = le32_to_cpu(ix->ee_block);
+                __entry->i_len          = ext4_ext_get_actual_len(ix);
+                __entry->i_pblk         = ext4_ext_pblock(ix);
+        ),
+        TP_printk("dev %d,%d ino %lu m_lblk %u m_len %u "
+                  "u_lblk %u u_len %u u_pblk %llu "
+                  "i_lblk %u i_len %u i_pblk %llu ",
+                  MAJOR(__entry->dev), MINOR(__entry->dev),
+                  (unsigned long) __entry->ino,
+                  __entry->m_lblk, __entry->m_len,
+                  __entry->u_lblk, __entry->u_len, __entry->u_pblk,
+                  __entry->i_lblk, __entry->i_len, __entry->i_pblk)
+);
 DECLARE_EVENT_CLASS(ext4__map_blocks_enter,
        TP_PROTO(struct inode *inode, ext4_lblk_t lblk,
                 unsigned int len, unsigned int flags),
@@ -1589,6 +1679,382 @@ DEFINE_EVENT(ext4__trim, ext4_trim_all_free,
        TP_ARGS(sb, group, start, len)
 );
+TRACE_EVENT(ext4_ext_handle_uninitialized_extents,
+        TP_PROTO(struct inode *inode, struct ext4_map_blocks *map,
+                 unsigned int allocated, ext4_fsblk_t newblock),
+        TP_ARGS(inode, map, allocated, newblock),
+        TP_STRUCT__entry(
+                __field(        ino_t,          ino             )
+                __field(        dev_t,          dev             )
+                __field(        ext4_lblk_t,    lblk            )
+                __field(        ext4_fsblk_t,   pblk            )
+                __field(        unsigned int,   len             )
+                __field(        int,            flags           )
+                __field(        unsigned int,   allocated       )
+                __field(        ext4_fsblk_t,   newblk          )
+        ),
+        TP_fast_assign(
+                __entry->ino            = inode->i_ino;
+                __entry->dev            = inode->i_sb->s_dev;
+                __entry->lblk           = map->m_lblk;
+                __entry->pblk           = map->m_pblk;
+                __entry->len            = map->m_len;
+                __entry->flags          = map->m_flags;
+                __entry->allocated      = allocated;
+                __entry->newblk         = newblock;
+        ),
+        TP_printk("dev %d,%d ino %lu m_lblk %u m_pblk %llu m_len %u flags %d"
+                  "allocated %d newblock %llu",
+                  MAJOR(__entry->dev), MINOR(__entry->dev),
+                  (unsigned long) __entry->ino,
+                  (unsigned) __entry->lblk, (unsigned long long) __entry->pblk,
+                  __entry->len, __entry->flags,
+                  (unsigned int) __entry->allocated,
+                  (unsigned long long) __entry->newblk)
+);
+TRACE_EVENT(ext4_get_implied_cluster_alloc_exit,
+        TP_PROTO(struct super_block *sb, struct ext4_map_blocks *map, int ret),
+        TP_ARGS(sb, map, ret),
+        TP_STRUCT__entry(
+                __field(        dev_t,          dev     )
+                __field(        ext4_lblk_t,    lblk    )
+                __field(        ext4_fsblk_t,   pblk    )
+                __field(        unsigned int,   len     )
+                __field(        unsigned int,   flags   )
+                __field(        int,            ret     )
+        ),
+        TP_fast_assign(
+                __entry->dev    = sb->s_dev;
+                __entry->lblk   = map->m_lblk;
+                __entry->pblk   = map->m_pblk;
+                __entry->len    = map->m_len;
+                __entry->flags  = map->m_flags;
+                __entry->ret    = ret;
+        ),
+        TP_printk("dev %d,%d m_lblk %u m_pblk %llu m_len %u m_flags %u ret %d",
+                  MAJOR(__entry->dev), MINOR(__entry->dev),
+                  __entry->lblk, (unsigned long long) __entry->pblk,
+                  __entry->len, __entry->flags, __entry->ret)
+);
+TRACE_EVENT(ext4_ext_put_in_cache,
+        TP_PROTO(struct inode *inode, ext4_lblk_t lblk, unsigned int len,
+                 ext4_fsblk_t start),
+        TP_ARGS(inode, lblk, len, start),
+        TP_STRUCT__entry(
+                __field(        ino_t,          ino     )
+                __field(        dev_t,          dev     )
+                __field(        ext4_lblk_t,    lblk    )
+                __field(        unsigned int,   len     )
+                __field(        ext4_fsblk_t,   start   )
+        ),
+        TP_fast_assign(
+                __entry->ino    = inode->i_ino;
+                __entry->dev    = inode->i_sb->s_dev;
+                __entry->lblk   = lblk;
+                __entry->len    = len;
+                __entry->start  = start;
+        ),
+        TP_printk("dev %d,%d ino %lu lblk %u len %u start %llu",
+                  MAJOR(__entry->dev), MINOR(__entry->dev),
+                  (unsigned long) __entry->ino,
+                  (unsigned) __entry->lblk,
+                  __entry->len,
+                  (unsigned long long) __entry->start)
+);
+TRACE_EVENT(ext4_ext_in_cache,
+        TP_PROTO(struct inode *inode, ext4_lblk_t lblk, int ret),
+        TP_ARGS(inode, lblk, ret),
+        TP_STRUCT__entry(
+                __field(        ino_t,          ino     )
+                __field(        dev_t,          dev     )
+                __field(        ext4_lblk_t,    lblk    )
+                __field(        int,            ret     )
+        ),
+        TP_fast_assign(
+                __entry->ino    = inode->i_ino;
+                __entry->dev    = inode->i_sb->s_dev;
+                __entry->lblk   = lblk;
+                __entry->ret    = ret;
+        ),
+        TP_printk("dev %d,%d ino %lu lblk %u ret %d",
+                  MAJOR(__entry->dev), MINOR(__entry->dev),
+                  (unsigned long) __entry->ino,
+                  (unsigned) __entry->lblk,
+                  __entry->ret)
+);
+TRACE_EVENT(ext4_find_delalloc_range,
+        TP_PROTO(struct inode *inode, ext4_lblk_t from, ext4_lblk_t to,
+                int reverse, int found, ext4_lblk_t found_blk),
+        TP_ARGS(inode, from, to, reverse, found, found_blk),
+        TP_STRUCT__entry(
+                __field(        ino_t,          ino             )
+                __field(        dev_t,          dev             )
+                __field(        ext4_lblk_t,    from            )
+                __field(        ext4_lblk_t,    to              )
+                __field(        int,            reverse         )
+                __field(        int,            found           )
+                __field(        ext4_lblk_t,    found_blk       )
+        ),
+        TP_fast_assign(
+                __entry->ino            = inode->i_ino;
+                __entry->dev            = inode->i_sb->s_dev;
+                __entry->from           = from;
+                __entry->to             = to;
+                __entry->reverse        = reverse;
+                __entry->found          = found;
+                __entry->found_blk      = found_blk;
+        ),
+        TP_printk("dev %d,%d ino %lu from %u to %u reverse %d found %d "
+                  "(blk = %u)",
+                  MAJOR(__entry->dev), MINOR(__entry->dev),
+                  (unsigned long) __entry->ino,
+                  (unsigned) __entry->from, (unsigned) __entry->to,
+                  __entry->reverse, __entry->found,
+                  (unsigned) __entry->found_blk)
+);
+TRACE_EVENT(ext4_get_reserved_cluster_alloc,
+        TP_PROTO(struct inode *inode, ext4_lblk_t lblk, unsigned int len),
+        TP_ARGS(inode, lblk, len),
+        TP_STRUCT__entry(
+                __field(        ino_t,          ino     )
+                __field(        dev_t,          dev     )
+                __field(        ext4_lblk_t,    lblk    )
+                __field(        unsigned int,   len     )
+        ),
+        TP_fast_assign(
+                __entry->ino    = inode->i_ino;
+                __entry->dev    = inode->i_sb->s_dev;
+                __entry->lblk   = lblk;
+                __entry->len    = len;
+        ),
+        TP_printk("dev %d,%d ino %lu lblk %u len %u",
+                  MAJOR(__entry->dev), MINOR(__entry->dev),
+                  (unsigned long) __entry->ino,
+                  (unsigned) __entry->lblk,
+                  __entry->len)
+);
+TRACE_EVENT(ext4_ext_show_extent,
+        TP_PROTO(struct inode *inode, ext4_lblk_t lblk, ext4_fsblk_t pblk,
+                 unsigned short len),
+        TP_ARGS(inode, lblk, pblk, len),
+        TP_STRUCT__entry(
+                __field(        ino_t,          ino     )
+                __field(        dev_t,          dev     )
+                __field(        ext4_lblk_t,    lblk    )
+                __field(        ext4_fsblk_t,   pblk    )
+                __field(        unsigned short, len     )
+        ),
+        TP_fast_assign(
+                __entry->ino    = inode->i_ino;
+                __entry->dev    = inode->i_sb->s_dev;
+                __entry->lblk   = lblk;
+                __entry->pblk   = pblk;
+                __entry->len    = len;
+        ),
+        TP_printk("dev %d,%d ino %lu lblk %u pblk %llu len %u",
+                  MAJOR(__entry->dev), MINOR(__entry->dev),
+                  (unsigned long) __entry->ino,
+                  (unsigned) __entry->lblk,
+                  (unsigned long long) __entry->pblk,
+                  (unsigned short) __entry->len)
+);
+TRACE_EVENT(ext4_remove_blocks,
+            TP_PROTO(struct inode *inode, struct ext4_extent *ex,
+                ext4_lblk_t from, ext4_fsblk_t to,
+                ext4_fsblk_t partial_cluster),
+        TP_ARGS(inode, ex, from, to, partial_cluster),
+        TP_STRUCT__entry(
+                __field(        ino_t,          ino     )
+                __field(        dev_t,          dev     )
+                __field(        ext4_lblk_t,    ee_lblk )
+                __field(        ext4_fsblk_t,   ee_pblk )
+                __field(        unsigned short, ee_len  )
+                __field(        ext4_lblk_t,    from    )
+                __field(        ext4_lblk_t,    to      )
+                __field(        ext4_fsblk_t,   partial )
+        ),
+        TP_fast_assign(
+                __entry->ino            = inode->i_ino;
+                __entry->dev            = inode->i_sb->s_dev;
+                __entry->ee_lblk        = cpu_to_le32(ex->ee_block);
+                __entry->ee_pblk        = ext4_ext_pblock(ex);
+                __entry->ee_len         = ext4_ext_get_actual_len(ex);
+                __entry->from           = from;
+                __entry->to             = to;
+                __entry->partial        = partial_cluster;
+        ),
+        TP_printk("dev %d,%d ino %lu extent [%u(%llu), %u]"
+                  "from %u to %u partial_cluster %u",
+                  MAJOR(__entry->dev), MINOR(__entry->dev),
+                  (unsigned long) __entry->ino,
+                  (unsigned) __entry->ee_lblk,
+                  (unsigned long long) __entry->ee_pblk,
+                  (unsigned short) __entry->ee_len,
+                  (unsigned) __entry->from,
+                  (unsigned) __entry->to,
+                  (unsigned) __entry->partial)
+);
+TRACE_EVENT(ext4_ext_rm_leaf,
+        TP_PROTO(struct inode *inode, ext4_lblk_t start,
+                 struct ext4_extent *ex, ext4_fsblk_t partial_cluster),
+        TP_ARGS(inode, start, ex, partial_cluster),
+        TP_STRUCT__entry(
+                __field(        ino_t,          ino     )
+                __field(        dev_t,          dev     )
+                __field(        ext4_lblk_t,    start   )
+                __field(        ext4_lblk_t,    ee_lblk )
+                __field(        ext4_fsblk_t,   ee_pblk )
+                __field(        short,          ee_len  )
+                __field(        ext4_fsblk_t,   partial )
+        ),
+        TP_fast_assign(
+                __entry->ino            = inode->i_ino;
+                __entry->dev            = inode->i_sb->s_dev;
+                __entry->start          = start;
+                __entry->ee_lblk        = le32_to_cpu(ex->ee_block);
+                __entry->ee_pblk        = ext4_ext_pblock(ex);
+                __entry->ee_len         = ext4_ext_get_actual_len(ex);
+                __entry->partial        = partial_cluster;
+        ),
+        TP_printk("dev %d,%d ino %lu start_lblk %u last_extent [%u(%llu), %u]"
+                  "partial_cluster %u",
+                  MAJOR(__entry->dev), MINOR(__entry->dev),
+                  (unsigned long) __entry->ino,
+                  (unsigned) __entry->start,
+                  (unsigned) __entry->ee_lblk,
+                  (unsigned long long) __entry->ee_pblk,
+                  (unsigned short) __entry->ee_len,
+                  (unsigned) __entry->partial)
+);
+TRACE_EVENT(ext4_ext_rm_idx,
+        TP_PROTO(struct inode *inode, ext4_fsblk_t pblk),
+        TP_ARGS(inode, pblk),
+        TP_STRUCT__entry(
+                __field(        ino_t,          ino     )
+                __field(        dev_t,          dev     )
+                __field(        ext4_fsblk_t,   pblk    )
+        ),
+        TP_fast_assign(
+                __entry->ino    = inode->i_ino;
+                __entry->dev    = inode->i_sb->s_dev;
+                __entry->pblk   = pblk;
+        ),
+        TP_printk("dev %d,%d ino %lu index_pblk %llu",
+                  MAJOR(__entry->dev), MINOR(__entry->dev),
+                  (unsigned long) __entry->ino,
+                  (unsigned long long) __entry->pblk)
+);
+TRACE_EVENT(ext4_ext_remove_space,
+        TP_PROTO(struct inode *inode, ext4_lblk_t start, int depth),
+        TP_ARGS(inode, start, depth),
+        TP_STRUCT__entry(
+                __field(        ino_t,          ino     )
+                __field(        dev_t,          dev     )
+                __field(        ext4_lblk_t,    start   )
+                __field(        int,            depth   )
+        ),
+        TP_fast_assign(
+                __entry->ino    = inode->i_ino;
+                __entry->dev    = inode->i_sb->s_dev;
+                __entry->start  = start;
+                __entry->depth  = depth;
+        ),
+        TP_printk("dev %d,%d ino %lu since %u depth %d",
+                  MAJOR(__entry->dev), MINOR(__entry->dev),
+                  (unsigned long) __entry->ino,
+                  (unsigned) __entry->start,
+                  __entry->depth)
+);
+TRACE_EVENT(ext4_ext_remove_space_done,
+        TP_PROTO(struct inode *inode, ext4_lblk_t start, int depth,
+                ext4_lblk_t partial, unsigned short eh_entries),
+        TP_ARGS(inode, start, depth, partial, eh_entries),
+        TP_STRUCT__entry(
+                __field(        ino_t,          ino             )
+                __field(        dev_t,          dev             )
+                __field(        ext4_lblk_t,    start           )
+                __field(        int,            depth           )
+                __field(        ext4_lblk_t,    partial         )
+                __field(        unsigned short, eh_entries      )
+        ),
+        TP_fast_assign(
+                __entry->ino            = inode->i_ino;
+                __entry->dev            = inode->i_sb->s_dev;
+                __entry->start          = start;
+                __entry->depth          = depth;
+                __entry->partial        = partial;
+                __entry->eh_entries     = eh_entries;
+        ),
+        TP_printk("dev %d,%d ino %lu since %u depth %d partial %u "
+                  "remaining_entries %u",
+                  MAJOR(__entry->dev), MINOR(__entry->dev),
+                  (unsigned long) __entry->ino,
+                  (unsigned) __entry->start,
+                  __entry->depth,
+                  (unsigned) __entry->partial,
+                  (unsigned short) __entry->eh_entries)
+);
 #endif /* _TRACE_EXT4_H */
 /* This part must be outside protection */
diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c
index b57a3776de44..200ce832c585 100644
--- a/kernel/irq/irqdomain.c
+++ b/kernel/irq/irqdomain.c
@@ -20,15 +20,15 @@ static DEFINE_MUTEX(irq_domain_mutex);
 void irq_domain_add(struct irq_domain *domain)
 {
        struct irq_data *d;
-        int hwirq;
+        int hwirq, irq;
        /*
         * This assumes that the irq_domain owner has already allocated
         * the irq_descs.  This block will be removed when support for dynamic
         * allocation of irq_descs is added to irq_domain.
         */
-        for (hwirq = 0; hwirq < domain->nr_irq; hwirq++) {
+        irq_domain_for_each_irq(domain, hwirq, irq) {
-                d = irq_get_irq_data(irq_domain_to_irq(domain, hwirq));
+                d = irq_get_irq_data(irq);
                if (!d) {
                        WARN(1, "error: assigning domain to non existant irq_desc");
                        return;
@@ -54,15 +54,15 @@ void irq_domain_add(struct irq_domain *domain)
 void irq_domain_del(struct irq_domain *domain)
 {
        struct irq_data *d;
-        int hwirq;
+        int hwirq, irq;
        mutex_lock(&irq_domain_mutex);
        list_del(&domain->list);
        mutex_unlock(&irq_domain_mutex);
        /* Clear the irq_domain assignments */
-        for (hwirq = 0; hwirq < domain->nr_irq; hwirq++) {
+        irq_domain_for_each_irq(domain, hwirq, irq) {
-                d = irq_get_irq_data(irq_domain_to_irq(domain, hwirq));
+                d = irq_get_irq_data(irq);
                d->domain = NULL;
        }
 }
diff --git a/mm/shmem.c b/mm/shmem.c
index fa4fa6ce13bc..45b9acb575f9 100644
--- a/mm/shmem.c
+++ b/mm/shmem.c
@@ -2503,7 +2503,7 @@ struct file *shmem_file_setup(const char *name, loff_t size, unsigned long flags
        d_instantiate(path.dentry, inode);
        inode->i_size = size;
-        inode->i_nlink = 0;     /* It is unlinked */
+        clear_nlink(inode);     /* It is unlinked */
 #ifndef CONFIG_MMU
        error = ramfs_nommu_expand_for_mapping(inode, size);
        if (error)
diff --git a/security/integrity/ima/Kconfig b/security/integrity/ima/Kconfig
index 19c053b82303..4f554f20dc97 100644
--- a/security/integrity/ima/Kconfig
+++ b/security/integrity/ima/Kconfig
@@ -9,7 +9,7 @@ config IMA
        select CRYPTO_HMAC
        select CRYPTO_MD5
        select CRYPTO_SHA1
-        select TCG_TPM if !S390
+        select TCG_TPM if !S390 && !UML
        select TCG_TIS if TCG_TPM
        help
          The Trusted Computing Group(TCG) runtime Integrity
diff --git a/sound/Kconfig b/sound/Kconfig
index 1fef141ef8e7..261a03c8a209 100644
--- a/sound/Kconfig
+++ b/sound/Kconfig
@@ -59,7 +59,7 @@ config SOUND_OSS_CORE_PRECLAIM
 source "sound/oss/dmasound/Kconfig"
-if !M68K
+if !M68K && !UML
 menuconfig SND
        tristate "Advanced Linux Sound Architecture"