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-rw-r--r--Documentation/arm/Samsung-S3C24XX/Overview.txt41
-rw-r--r--arch/arm/Kconfig9
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/configs/ixp4xx_defconfig2
-rw-r--r--arch/arm/lib/Makefile22
-rw-r--r--arch/arm/lib/clear_user.S52
-rw-r--r--arch/arm/lib/copy_from_user.S101
-rw-r--r--arch/arm/lib/copy_template.S255
-rw-r--r--arch/arm/lib/copy_to_user.S101
-rw-r--r--arch/arm/lib/memcpy.S410
-rw-r--r--arch/arm/lib/memmove.S206
-rw-r--r--arch/arm/lib/uaccess.S38
-rw-r--r--arch/arm/mach-ebsa110/core.c26
-rw-r--r--arch/arm/mach-ixp2000/Makefile2
-rw-r--r--arch/arm/mach-ixp2000/core.c33
-rw-r--r--arch/arm/mach-ixp2000/enp2611.c31
-rw-r--r--arch/arm/mach-ixp2000/ixdp2x00.c4
-rw-r--r--arch/arm/mach-ixp2000/ixdp2x01.c9
-rw-r--r--arch/arm/mach-ixp2000/pci.c6
-rw-r--r--arch/arm/mach-ixp2000/uengine.c474
-rw-r--r--arch/arm/mach-pxa/lubbock.c63
-rw-r--r--arch/arm/mach-realview/Kconfig11
-rw-r--r--arch/arm/mach-realview/Makefile6
-rw-r--r--arch/arm/mach-realview/Makefile.boot4
-rw-r--r--arch/arm/mach-realview/clock.c145
-rw-r--r--arch/arm/mach-realview/clock.h25
-rw-r--r--arch/arm/mach-realview/core.c605
-rw-r--r--arch/arm/mach-realview/core.h118
-rw-r--r--arch/arm/mach-realview/realview_eb.c142
-rw-r--r--arch/arm/mach-s3c2410/mach-rx3715.c70
-rw-r--r--arch/arm/mm/Kconfig6
-rw-r--r--drivers/i2c/busses/i2c-iop3xx.c9
-rw-r--r--drivers/net/arm/am79c961a.c41
-rw-r--r--drivers/net/arm/am79c961a.h2
-rw-r--r--include/asm-arm/arch-ixp2000/enp2611.h16
-rw-r--r--include/asm-arm/arch-ixp2000/ixp2000-regs.h7
-rw-r--r--include/asm-arm/arch-ixp2000/system.h23
-rw-r--r--include/asm-arm/arch-ixp2000/uengine.h62
-rw-r--r--include/asm-arm/arch-realview/debug-macro.S38
-rw-r--r--include/asm-arm/arch-realview/dma.h27
-rw-r--r--include/asm-arm/arch-realview/entry-macro.S49
-rw-r--r--include/asm-arm/arch-realview/hardware.h31
-rw-r--r--include/asm-arm/arch-realview/io.h34
-rw-r--r--include/asm-arm/arch-realview/irqs.h103
-rw-r--r--include/asm-arm/arch-realview/memory.h38
-rw-r--r--include/asm-arm/arch-realview/param.h19
-rw-r--r--include/asm-arm/arch-realview/platform.h395
-rw-r--r--include/asm-arm/arch-realview/system.h51
-rw-r--r--include/asm-arm/arch-realview/timex.h23
-rw-r--r--include/asm-arm/arch-realview/uncompress.h54
-rw-r--r--include/asm-arm/arch-realview/vmalloc.h21
-rw-r--r--include/asm-arm/arch-s3c2410/regs-iis.h1
-rw-r--r--include/asm-arm/hardware/amba_clcd.h2
53 files changed, 3573 insertions, 491 deletions
diff --git a/Documentation/arm/Samsung-S3C24XX/Overview.txt b/Documentation/arm/Samsung-S3C24XX/Overview.txt
index 3af4d29a8938..89aa89d526ac 100644
--- a/Documentation/arm/Samsung-S3C24XX/Overview.txt
+++ b/Documentation/arm/Samsung-S3C24XX/Overview.txt
@@ -81,7 +81,8 @@ Adding New Machines
81 81
82 Any large scale modifications, or new drivers should be discussed 82 Any large scale modifications, or new drivers should be discussed
83 on the ARM kernel mailing list (linux-arm-kernel) before being 83 on the ARM kernel mailing list (linux-arm-kernel) before being
84 attempted. 84 attempted. See http://www.arm.linux.org.uk/mailinglists/ for the
85 mailing list information.
85 86
86 87
87NAND 88NAND
@@ -120,6 +121,43 @@ Clock Management
120 various clock units 121 various clock units
121 122
122 123
124Platform Data
125-------------
126
127 Whenever a device has platform specific data that is specified
128 on a per-machine basis, care should be taken to ensure the
129 following:
130
131 1) that default data is not left in the device to confuse the
132 driver if a machine does not set it at startup
133
134 2) the data should (if possible) be marked as __initdata,
135 to ensure that the data is thrown away if the machine is
136 not the one currently in use.
137
138 The best way of doing this is to make a function that
139 kmalloc()s an area of memory, and copies the __initdata
140 and then sets the relevant device's platform data. Making
141 the function `__init` takes care of ensuring it is discarded
142 with the rest of the initialisation code
143
144 static __init void s3c24xx_xxx_set_platdata(struct xxx_data *pd)
145 {
146 struct s3c2410_xxx_mach_info *npd;
147
148 npd = kmalloc(sizeof(struct s3c2410_xxx_mach_info), GFP_KERNEL);
149 if (npd) {
150 memcpy(npd, pd, sizeof(struct s3c2410_xxx_mach_info));
151 s3c_device_xxx.dev.platform_data = npd;
152 } else {
153 printk(KERN_ERR "no memory for xxx platform data\n");
154 }
155 }
156
157 Note, since the code is marked as __init, it should not be
158 exported outside arch/arm/mach-s3c2410/, or exported to
159 modules via EXPORT_SYMBOL() and related functions.
160
123Port Contributors 161Port Contributors
124----------------- 162-----------------
125 163
@@ -149,6 +187,7 @@ Document Changes
149 06 Mar 2005 - BJD - Added Christer Weinigel 187 06 Mar 2005 - BJD - Added Christer Weinigel
150 08 Mar 2005 - BJD - Added LCVR to list of people, updated introduction 188 08 Mar 2005 - BJD - Added LCVR to list of people, updated introduction
151 08 Mar 2005 - BJD - Added section on adding machines 189 08 Mar 2005 - BJD - Added section on adding machines
190 09 Sep 2005 - BJD - Added section on platform data
152 191
153Document Author 192Document Author
154--------------- 193---------------
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 682367bd0f65..dc6d8342e5e6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -194,6 +194,13 @@ config ARCH_VERSATILE
194 help 194 help
195 This enables support for ARM Ltd Versatile board. 195 This enables support for ARM Ltd Versatile board.
196 196
197config ARCH_REALVIEW
198 bool "RealView"
199 select ARM_AMBA
200 select ICST307
201 help
202 This enables support for ARM Ltd RealView boards.
203
197config ARCH_IMX 204config ARCH_IMX
198 bool "IMX" 205 bool "IMX"
199 206
@@ -244,6 +251,8 @@ source "arch/arm/mach-versatile/Kconfig"
244 251
245source "arch/arm/mach-aaec2000/Kconfig" 252source "arch/arm/mach-aaec2000/Kconfig"
246 253
254source "arch/arm/mach-realview/Kconfig"
255
247# Definitions to make life easier 256# Definitions to make life easier
248config ARCH_ACORN 257config ARCH_ACORN
249 bool 258 bool
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 64cf480b0b02..d80749ae2a7e 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -99,6 +99,7 @@ textaddr-$(CONFIG_ARCH_FORTUNET) := 0xc0008000
99 machine-$(CONFIG_ARCH_IMX) := imx 99 machine-$(CONFIG_ARCH_IMX) := imx
100 machine-$(CONFIG_ARCH_H720X) := h720x 100 machine-$(CONFIG_ARCH_H720X) := h720x
101 machine-$(CONFIG_ARCH_AAEC2000) := aaec2000 101 machine-$(CONFIG_ARCH_AAEC2000) := aaec2000
102 machine-$(CONFIG_ARCH_REALVIEW) := realview
102 103
103ifeq ($(CONFIG_ARCH_EBSA110),y) 104ifeq ($(CONFIG_ARCH_EBSA110),y)
104# This is what happens if you forget the IOCS16 line. 105# This is what happens if you forget the IOCS16 line.
diff --git a/arch/arm/configs/ixp4xx_defconfig b/arch/arm/configs/ixp4xx_defconfig
index c279e41ed10e..f74c926beb42 100644
--- a/arch/arm/configs/ixp4xx_defconfig
+++ b/arch/arm/configs/ixp4xx_defconfig
@@ -104,7 +104,7 @@ CONFIG_ARCH_IXCDP1100=y
104CONFIG_ARCH_PRPMC1100=y 104CONFIG_ARCH_PRPMC1100=y
105CONFIG_ARCH_IXDP4XX=y 105CONFIG_ARCH_IXDP4XX=y
106CONFIG_CPU_IXP46X=y 106CONFIG_CPU_IXP46X=y
107CONFIG_MACH_GTWX5715=y 107# CONFIG_MACH_GTWX5715 is not set
108 108
109# 109#
110# IXP4xx Options 110# IXP4xx Options
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 71e5b99e519e..391f3ab3ff32 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -7,13 +7,27 @@
7lib-y := backtrace.o changebit.o csumipv6.o csumpartial.o \ 7lib-y := backtrace.o changebit.o csumipv6.o csumpartial.o \
8 csumpartialcopy.o csumpartialcopyuser.o clearbit.o \ 8 csumpartialcopy.o csumpartialcopyuser.o clearbit.o \
9 copy_page.o delay.o findbit.o memchr.o memcpy.o \ 9 copy_page.o delay.o findbit.o memchr.o memcpy.o \
10 memset.o memzero.o setbit.o strncpy_from_user.o \ 10 memmove.o memset.o memzero.o setbit.o \
11 strnlen_user.o strchr.o strrchr.o testchangebit.o \ 11 strncpy_from_user.o strnlen_user.o \
12 testclearbit.o testsetbit.o uaccess.o getuser.o \ 12 strchr.o strrchr.o \
13 putuser.o ashldi3.o ashrdi3.o lshrdi3.o muldi3.o \ 13 testchangebit.o testclearbit.o testsetbit.o \
14 getuser.o putuser.o clear_user.o \
15 ashldi3.o ashrdi3.o lshrdi3.o muldi3.o \
14 ucmpdi2.o lib1funcs.o div64.o sha1.o \ 16 ucmpdi2.o lib1funcs.o div64.o sha1.o \
15 io-readsb.o io-writesb.o io-readsl.o io-writesl.o 17 io-readsb.o io-writesb.o io-readsl.o io-writesl.o
16 18
19# the code in uaccess.S is not preemption safe and
20# probably faster on ARMv3 only
21ifeq ($CONFIG_PREEMPT,y)
22 lib-y += copy_from_user.o copy_to_user.o
23else
24ifneq ($(CONFIG_CPU_32v3),y)
25 lib-y += copy_from_user.o copy_to_user.o
26else
27 lib-y += uaccess.o
28endif
29endif
30
17ifeq ($(CONFIG_CPU_32v3),y) 31ifeq ($(CONFIG_CPU_32v3),y)
18 lib-y += io-readsw-armv3.o io-writesw-armv3.o 32 lib-y += io-readsw-armv3.o io-writesw-armv3.o
19else 33else
diff --git a/arch/arm/lib/clear_user.S b/arch/arm/lib/clear_user.S
new file mode 100644
index 000000000000..7ff9f831b3f9
--- /dev/null
+++ b/arch/arm/lib/clear_user.S
@@ -0,0 +1,52 @@
1/*
2 * linux/arch/arm/lib/clear_user.S
3 *
4 * Copyright (C) 1995, 1996,1997,1998 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/linkage.h>
11#include <asm/assembler.h>
12
13 .text
14
15/* Prototype: int __arch_clear_user(void *addr, size_t sz)
16 * Purpose : clear some user memory
17 * Params : addr - user memory address to clear
18 * : sz - number of bytes to clear
19 * Returns : number of bytes NOT cleared
20 */
21ENTRY(__arch_clear_user)
22 stmfd sp!, {r1, lr}
23 mov r2, #0
24 cmp r1, #4
25 blt 2f
26 ands ip, r0, #3
27 beq 1f
28 cmp ip, #2
29USER( strbt r2, [r0], #1)
30USER( strlebt r2, [r0], #1)
31USER( strltbt r2, [r0], #1)
32 rsb ip, ip, #4
33 sub r1, r1, ip @ 7 6 5 4 3 2 1
341: subs r1, r1, #8 @ -1 -2 -3 -4 -5 -6 -7
35USER( strplt r2, [r0], #4)
36USER( strplt r2, [r0], #4)
37 bpl 1b
38 adds r1, r1, #4 @ 3 2 1 0 -1 -2 -3
39USER( strplt r2, [r0], #4)
402: tst r1, #2 @ 1x 1x 0x 0x 1x 1x 0x
41USER( strnebt r2, [r0], #1)
42USER( strnebt r2, [r0], #1)
43 tst r1, #1 @ x1 x0 x1 x0 x1 x0 x1
44USER( strnebt r2, [r0], #1)
45 mov r0, #0
46 LOADREGS(fd,sp!, {r1, pc})
47
48 .section .fixup,"ax"
49 .align 0
509001: LOADREGS(fd,sp!, {r0, pc})
51 .previous
52
diff --git a/arch/arm/lib/copy_from_user.S b/arch/arm/lib/copy_from_user.S
new file mode 100644
index 000000000000..7497393a0e81
--- /dev/null
+++ b/arch/arm/lib/copy_from_user.S
@@ -0,0 +1,101 @@
1/*
2 * linux/arch/arm/lib/copy_from_user.S
3 *
4 * Author: Nicolas Pitre
5 * Created: Sep 29, 2005
6 * Copyright: MontaVista Software, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/linkage.h>
14#include <asm/assembler.h>
15
16/*
17 * Prototype:
18 *
19 * size_t __arch_copy_from_user(void *to, const void *from, size_t n)
20 *
21 * Purpose:
22 *
23 * copy a block to kernel memory from user memory
24 *
25 * Params:
26 *
27 * to = kernel memory
28 * from = user memory
29 * n = number of bytes to copy
30 *
31 * Return value:
32 *
33 * Number of bytes NOT copied.
34 */
35
36 .macro ldr1w ptr reg abort
37100: ldrt \reg, [\ptr], #4
38 .section __ex_table, "a"
39 .long 100b, \abort
40 .previous
41 .endm
42
43 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
44 ldr1w \ptr, \reg1, \abort
45 ldr1w \ptr, \reg2, \abort
46 ldr1w \ptr, \reg3, \abort
47 ldr1w \ptr, \reg4, \abort
48 .endm
49
50 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
51 ldr4w \ptr, \reg1, \reg2, \reg3, \reg4, \abort
52 ldr4w \ptr, \reg5, \reg6, \reg7, \reg8, \abort
53 .endm
54
55 .macro ldr1b ptr reg cond=al abort
56100: ldr\cond\()bt \reg, [\ptr], #1
57 .section __ex_table, "a"
58 .long 100b, \abort
59 .previous
60 .endm
61
62 .macro str1w ptr reg abort
63 str \reg, [\ptr], #4
64 .endm
65
66 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
67 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
68 .endm
69
70 .macro str1b ptr reg cond=al abort
71 str\cond\()b \reg, [\ptr], #1
72 .endm
73
74 .macro enter reg1 reg2
75 mov r3, #0
76 stmdb sp!, {r0, r2, r3, \reg1, \reg2}
77 .endm
78
79 .macro exit reg1 reg2
80 add sp, sp, #8
81 ldmfd sp!, {r0, \reg1, \reg2}
82 .endm
83
84 .text
85
86ENTRY(__arch_copy_from_user)
87
88#include "copy_template.S"
89
90 .section .fixup,"ax"
91 .align 0
92 copy_abort_preamble
93 ldmfd sp!, {r1, r2}
94 sub r3, r0, r1
95 rsb r1, r3, r2
96 str r1, [sp]
97 bl __memzero
98 ldr r0, [sp], #4
99 copy_abort_end
100 .previous
101
diff --git a/arch/arm/lib/copy_template.S b/arch/arm/lib/copy_template.S
new file mode 100644
index 000000000000..838e435e4922
--- /dev/null
+++ b/arch/arm/lib/copy_template.S
@@ -0,0 +1,255 @@
1/*
2 * linux/arch/arm/lib/copy_template.s
3 *
4 * Code template for optimized memory copy functions
5 *
6 * Author: Nicolas Pitre
7 * Created: Sep 28, 2005
8 * Copyright: MontaVista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15/*
16 * This can be used to enable code to cacheline align the source pointer.
17 * Experiments on tested architectures (StrongARM and XScale) didn't show
18 * this a worthwhile thing to do. That might be different in the future.
19 */
20//#define CALGN(code...) code
21#define CALGN(code...)
22
23/*
24 * Theory of operation
25 * -------------------
26 *
27 * This file provides the core code for a forward memory copy used in
28 * the implementation of memcopy(), copy_to_user() and copy_from_user().
29 *
30 * The including file must define the following accessor macros
31 * according to the need of the given function:
32 *
33 * ldr1w ptr reg abort
34 *
35 * This loads one word from 'ptr', stores it in 'reg' and increments
36 * 'ptr' to the next word. The 'abort' argument is used for fixup tables.
37 *
38 * ldr4w ptr reg1 reg2 reg3 reg4 abort
39 * ldr8w ptr, reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
40 *
41 * This loads four or eight words starting from 'ptr', stores them
42 * in provided registers and increments 'ptr' past those words.
43 * The'abort' argument is used for fixup tables.
44 *
45 * ldr1b ptr reg cond abort
46 *
47 * Similar to ldr1w, but it loads a byte and increments 'ptr' one byte.
48 * It also must apply the condition code if provided, otherwise the
49 * "al" condition is assumed by default.
50 *
51 * str1w ptr reg abort
52 * str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
53 * str1b ptr reg cond abort
54 *
55 * Same as their ldr* counterparts, but data is stored to 'ptr' location
56 * rather than being loaded.
57 *
58 * enter reg1 reg2
59 *
60 * Preserve the provided registers on the stack plus any additional
61 * data as needed by the implementation including this code. Called
62 * upon code entry.
63 *
64 * exit reg1 reg2
65 *
66 * Restore registers with the values previously saved with the
67 * 'preserv' macro. Called upon code termination.
68 */
69
70
71 enter r4, lr
72
73 subs r2, r2, #4
74 blt 8f
75 ands ip, r0, #3
76 PLD( pld [r1, #0] )
77 bne 9f
78 ands ip, r1, #3
79 bne 10f
80
811: subs r2, r2, #(28)
82 stmfd sp!, {r5 - r8}
83 blt 5f
84
85 CALGN( ands ip, r1, #31 )
86 CALGN( rsb r3, ip, #32 )
87 CALGN( sbcnes r4, r3, r2 ) @ C is always set here
88 CALGN( bcs 2f )
89 CALGN( adr r4, 6f )
90 CALGN( subs r2, r2, r3 ) @ C gets set
91 CALGN( add pc, r4, ip )
92
93 PLD( pld [r1, #0] )
942: PLD( subs r2, r2, #96 )
95 PLD( pld [r1, #28] )
96 PLD( blt 4f )
97 PLD( pld [r1, #60] )
98 PLD( pld [r1, #92] )
99
1003: PLD( pld [r1, #124] )
1014: ldr8w r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
102 subs r2, r2, #32
103 str8w r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
104 bge 3b
105 PLD( cmn r2, #96 )
106 PLD( bge 4b )
107
1085: ands ip, r2, #28
109 rsb ip, ip, #32
110 addne pc, pc, ip @ C is always clear here
111 b 7f
1126: nop
113 ldr1w r1, r3, abort=20f
114 ldr1w r1, r4, abort=20f
115 ldr1w r1, r5, abort=20f
116 ldr1w r1, r6, abort=20f
117 ldr1w r1, r7, abort=20f
118 ldr1w r1, r8, abort=20f
119 ldr1w r1, lr, abort=20f
120
121 add pc, pc, ip
122 nop
123 nop
124 str1w r0, r3, abort=20f
125 str1w r0, r4, abort=20f
126 str1w r0, r5, abort=20f
127 str1w r0, r6, abort=20f
128 str1w r0, r7, abort=20f
129 str1w r0, r8, abort=20f
130 str1w r0, lr, abort=20f
131
132 CALGN( bcs 2b )
133
1347: ldmfd sp!, {r5 - r8}
135
1368: movs r2, r2, lsl #31
137 ldr1b r1, r3, ne, abort=21f
138 ldr1b r1, r4, cs, abort=21f
139 ldr1b r1, ip, cs, abort=21f
140 str1b r0, r3, ne, abort=21f
141 str1b r0, r4, cs, abort=21f
142 str1b r0, ip, cs, abort=21f
143
144 exit r4, pc
145
1469: rsb ip, ip, #4
147 cmp ip, #2
148 ldr1b r1, r3, gt, abort=21f
149 ldr1b r1, r4, ge, abort=21f
150 ldr1b r1, lr, abort=21f
151 str1b r0, r3, gt, abort=21f
152 str1b r0, r4, ge, abort=21f
153 subs r2, r2, ip
154 str1b r0, lr, abort=21f
155 blt 8b
156 ands ip, r1, #3
157 beq 1b
158
15910: bic r1, r1, #3
160 cmp ip, #2
161 ldr1w r1, lr, abort=21f
162 beq 17f
163 bgt 18f
164
165
166 .macro forward_copy_shift pull push
167
168 subs r2, r2, #28
169 blt 14f
170
171 CALGN( ands ip, r1, #31 )
172 CALGN( rsb ip, ip, #32 )
173 CALGN( sbcnes r4, ip, r2 ) @ C is always set here
174 CALGN( subcc r2, r2, ip )
175 CALGN( bcc 15f )
176
17711: stmfd sp!, {r5 - r9}
178
179 PLD( pld [r1, #0] )
180 PLD( subs r2, r2, #96 )
181 PLD( pld [r1, #28] )
182 PLD( blt 13f )
183 PLD( pld [r1, #60] )
184 PLD( pld [r1, #92] )
185
18612: PLD( pld [r1, #124] )
18713: ldr4w r1, r4, r5, r6, r7, abort=19f
188 mov r3, lr, pull #\pull
189 subs r2, r2, #32
190 ldr4w r1, r8, r9, ip, lr, abort=19f
191 orr r3, r3, r4, push #\push
192 mov r4, r4, pull #\pull
193 orr r4, r4, r5, push #\push
194 mov r5, r5, pull #\pull
195 orr r5, r5, r6, push #\push
196 mov r6, r6, pull #\pull
197 orr r6, r6, r7, push #\push
198 mov r7, r7, pull #\pull
199 orr r7, r7, r8, push #\push
200 mov r8, r8, pull #\pull
201 orr r8, r8, r9, push #\push
202 mov r9, r9, pull #\pull
203 orr r9, r9, ip, push #\push
204 mov ip, ip, pull #\pull
205 orr ip, ip, lr, push #\push
206 str8w r0, r3, r4, r5, r6, r7, r8, r9, ip, , abort=19f
207 bge 12b
208 PLD( cmn r2, #96 )
209 PLD( bge 13b )
210
211 ldmfd sp!, {r5 - r9}
212
21314: ands ip, r2, #28
214 beq 16f
215
21615: mov r3, lr, pull #\pull
217 ldr1w r1, lr, abort=21f
218 subs ip, ip, #4
219 orr r3, r3, lr, push #\push
220 str1w r0, r3, abort=21f
221 bgt 15b
222 CALGN( cmp r2, #0 )
223 CALGN( bge 11b )
224
22516: sub r1, r1, #(\push / 8)
226 b 8b
227
228 .endm
229
230
231 forward_copy_shift pull=8 push=24
232
23317: forward_copy_shift pull=16 push=16
234
23518: forward_copy_shift pull=24 push=8
236
237
238/*
239 * Abort preanble and completion macros.
240 * If a fixup handler is required then those macros must surround it.
241 * It is assumed that the fixup code will handle the private part of
242 * the exit macro.
243 */
244
245 .macro copy_abort_preamble
24619: ldmfd sp!, {r5 - r9}
247 b 21f
24820: ldmfd sp!, {r5 - r8}
24921:
250 .endm
251
252 .macro copy_abort_end
253 ldmfd sp!, {r4, pc}
254 .endm
255
diff --git a/arch/arm/lib/copy_to_user.S b/arch/arm/lib/copy_to_user.S
new file mode 100644
index 000000000000..4a6d8ea14022
--- /dev/null
+++ b/arch/arm/lib/copy_to_user.S
@@ -0,0 +1,101 @@
1/*
2 * linux/arch/arm/lib/copy_to_user.S
3 *
4 * Author: Nicolas Pitre
5 * Created: Sep 29, 2005
6 * Copyright: MontaVista Software, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/linkage.h>
14#include <asm/assembler.h>
15
16/*
17 * Prototype:
18 *
19 * size_t __arch_copy_to_user(void *to, const void *from, size_t n)
20 *
21 * Purpose:
22 *
23 * copy a block to user memory from kernel memory
24 *
25 * Params:
26 *
27 * to = user memory
28 * from = kernel memory
29 * n = number of bytes to copy
30 *
31 * Return value:
32 *
33 * Number of bytes NOT copied.
34 */
35
36 .macro ldr1w ptr reg abort
37 ldr \reg, [\ptr], #4
38 .endm
39
40 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
41 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
42 .endm
43
44 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
45 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
46 .endm
47
48 .macro ldr1b ptr reg cond=al abort
49 ldr\cond\()b \reg, [\ptr], #1
50 .endm
51
52 .macro str1w ptr reg abort
53100: strt \reg, [\ptr], #4
54 .section __ex_table, "a"
55 .long 100b, \abort
56 .previous
57 .endm
58
59 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
60 str1w \ptr, \reg1, \abort
61 str1w \ptr, \reg2, \abort
62 str1w \ptr, \reg3, \abort
63 str1w \ptr, \reg4, \abort
64 str1w \ptr, \reg5, \abort
65 str1w \ptr, \reg6, \abort
66 str1w \ptr, \reg7, \abort
67 str1w \ptr, \reg8, \abort
68 .endm
69
70 .macro str1b ptr reg cond=al abort
71100: str\cond\()bt \reg, [\ptr], #1
72 .section __ex_table, "a"
73 .long 100b, \abort
74 .previous
75 .endm
76
77 .macro enter reg1 reg2
78 mov r3, #0
79 stmdb sp!, {r0, r2, r3, \reg1, \reg2}
80 .endm
81
82 .macro exit reg1 reg2
83 add sp, sp, #8
84 ldmfd sp!, {r0, \reg1, \reg2}
85 .endm
86
87 .text
88
89ENTRY(__arch_copy_to_user)
90
91#include "copy_template.S"
92
93 .section .fixup,"ax"
94 .align 0
95 copy_abort_preamble
96 ldmfd sp!, {r1, r2, r3}
97 sub r0, r0, r1
98 rsb r0, r0, r2
99 copy_abort_end
100 .previous
101
diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S
index f5a593ceb8cc..7e71d6708a8d 100644
--- a/arch/arm/lib/memcpy.S
+++ b/arch/arm/lib/memcpy.S
@@ -1,393 +1,59 @@
1/* 1/*
2 * linux/arch/arm/lib/memcpy.S 2 * linux/arch/arm/lib/memcpy.S
3 * 3 *
4 * Copyright (C) 1995-1999 Russell King 4 * Author: Nicolas Pitre
5 * Created: Sep 28, 2005
6 * Copyright: MontaVista Software, Inc.
5 * 7 *
6 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
9 *
10 * ASM optimised string functions
11 */ 11 */
12
12#include <linux/linkage.h> 13#include <linux/linkage.h>
13#include <asm/assembler.h> 14#include <asm/assembler.h>
14 15
15 .text 16 .macro ldr1w ptr reg abort
16 17 ldr \reg, [\ptr], #4
17#define ENTER \ 18 .endm
18 mov ip,sp ;\
19 stmfd sp!,{r0,r4-r9,fp,ip,lr,pc} ;\
20 sub fp,ip,#4
21
22#define EXIT \
23 LOADREGS(ea, fp, {r0, r4 - r9, fp, sp, pc})
24
25#define EXITEQ \
26 LOADREGS(eqea, fp, {r0, r4 - r9, fp, sp, pc})
27
28/*
29 * Prototype: void memcpy(void *to,const void *from,unsigned long n);
30 */
31ENTRY(memcpy)
32ENTRY(memmove)
33 ENTER
34 cmp r1, r0
35 bcc 23f
36 subs r2, r2, #4
37 blt 6f
38 PLD( pld [r1, #0] )
39 ands ip, r0, #3
40 bne 7f
41 ands ip, r1, #3
42 bne 8f
43 19
441: subs r2, r2, #8 20 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
45 blt 5f 21 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
46 subs r2, r2, #20 22 .endm
47 blt 4f
48 PLD( pld [r1, #28] )
49 PLD( subs r2, r2, #64 )
50 PLD( blt 3f )
512: PLD( pld [r1, #60] )
52 PLD( pld [r1, #92] )
53 ldmia r1!, {r3 - r9, ip}
54 subs r2, r2, #32
55 stmgeia r0!, {r3 - r9, ip}
56 ldmgeia r1!, {r3 - r9, ip}
57 subges r2, r2, #32
58 stmia r0!, {r3 - r9, ip}
59 bge 2b
603: PLD( ldmia r1!, {r3 - r9, ip} )
61 PLD( adds r2, r2, #32 )
62 PLD( stmgeia r0!, {r3 - r9, ip} )
63 PLD( ldmgeia r1!, {r3 - r9, ip} )
64 PLD( subges r2, r2, #32 )
65 PLD( stmia r0!, {r3 - r9, ip} )
664: cmn r2, #16
67 ldmgeia r1!, {r3 - r6}
68 subge r2, r2, #16
69 stmgeia r0!, {r3 - r6}
70 adds r2, r2, #20
71 ldmgeia r1!, {r3 - r5}
72 subge r2, r2, #12
73 stmgeia r0!, {r3 - r5}
745: adds r2, r2, #8
75 blt 6f
76 subs r2, r2, #4
77 ldrlt r3, [r1], #4
78 ldmgeia r1!, {r4, r5}
79 subge r2, r2, #4
80 strlt r3, [r0], #4
81 stmgeia r0!, {r4, r5}
82 23
836: adds r2, r2, #4 24 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
84 EXITEQ 25 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
85 cmp r2, #2 26 .endm
86 ldrb r3, [r1], #1
87 ldrgeb r4, [r1], #1
88 ldrgtb r5, [r1], #1
89 strb r3, [r0], #1
90 strgeb r4, [r0], #1
91 strgtb r5, [r0], #1
92 EXIT
93 27
947: rsb ip, ip, #4 28 .macro ldr1b ptr reg cond=al abort
95 cmp ip, #2 29 ldr\cond\()b \reg, [\ptr], #1
96 ldrb r3, [r1], #1 30 .endm
97 ldrgeb r4, [r1], #1
98 ldrgtb r5, [r1], #1
99 strb r3, [r0], #1
100 strgeb r4, [r0], #1
101 strgtb r5, [r0], #1
102 subs r2, r2, ip
103 blt 6b
104 ands ip, r1, #3
105 beq 1b
106 31
1078: bic r1, r1, #3 32 .macro str1w ptr reg abort
108 ldr r7, [r1], #4 33 str \reg, [\ptr], #4
109 cmp ip, #2 34 .endm
110 bgt 18f
111 beq 13f
112 cmp r2, #12
113 blt 11f
114 PLD( pld [r1, #12] )
115 sub r2, r2, #12
116 PLD( subs r2, r2, #32 )
117 PLD( blt 10f )
118 PLD( pld [r1, #28] )
1199: PLD( pld [r1, #44] )
12010: mov r3, r7, pull #8
121 ldmia r1!, {r4 - r7}
122 subs r2, r2, #16
123 orr r3, r3, r4, push #24
124 mov r4, r4, pull #8
125 orr r4, r4, r5, push #24
126 mov r5, r5, pull #8
127 orr r5, r5, r6, push #24
128 mov r6, r6, pull #8
129 orr r6, r6, r7, push #24
130 stmia r0!, {r3 - r6}
131 bge 9b
132 PLD( cmn r2, #32 )
133 PLD( bge 10b )
134 PLD( add r2, r2, #32 )
135 adds r2, r2, #12
136 blt 12f
13711: mov r3, r7, pull #8
138 ldr r7, [r1], #4
139 subs r2, r2, #4
140 orr r3, r3, r7, push #24
141 str r3, [r0], #4
142 bge 11b
14312: sub r1, r1, #3
144 b 6b
145 35
14613: cmp r2, #12 36 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
147 blt 16f 37 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
148 PLD( pld [r1, #12] ) 38 .endm
149 sub r2, r2, #12
150 PLD( subs r2, r2, #32 )
151 PLD( blt 15f )
152 PLD( pld [r1, #28] )
15314: PLD( pld [r1, #44] )
15415: mov r3, r7, pull #16
155 ldmia r1!, {r4 - r7}
156 subs r2, r2, #16
157 orr r3, r3, r4, push #16
158 mov r4, r4, pull #16
159 orr r4, r4, r5, push #16
160 mov r5, r5, pull #16
161 orr r5, r5, r6, push #16
162 mov r6, r6, pull #16
163 orr r6, r6, r7, push #16
164 stmia r0!, {r3 - r6}
165 bge 14b
166 PLD( cmn r2, #32 )
167 PLD( bge 15b )
168 PLD( add r2, r2, #32 )
169 adds r2, r2, #12
170 blt 17f
17116: mov r3, r7, pull #16
172 ldr r7, [r1], #4
173 subs r2, r2, #4
174 orr r3, r3, r7, push #16
175 str r3, [r0], #4
176 bge 16b
17717: sub r1, r1, #2
178 b 6b
179 39
18018: cmp r2, #12 40 .macro str1b ptr reg cond=al abort
181 blt 21f 41 str\cond\()b \reg, [\ptr], #1
182 PLD( pld [r1, #12] ) 42 .endm
183 sub r2, r2, #12
184 PLD( subs r2, r2, #32 )
185 PLD( blt 20f )
186 PLD( pld [r1, #28] )
18719: PLD( pld [r1, #44] )
18820: mov r3, r7, pull #24
189 ldmia r1!, {r4 - r7}
190 subs r2, r2, #16
191 orr r3, r3, r4, push #8
192 mov r4, r4, pull #24
193 orr r4, r4, r5, push #8
194 mov r5, r5, pull #24
195 orr r5, r5, r6, push #8
196 mov r6, r6, pull #24
197 orr r6, r6, r7, push #8
198 stmia r0!, {r3 - r6}
199 bge 19b
200 PLD( cmn r2, #32 )
201 PLD( bge 20b )
202 PLD( add r2, r2, #32 )
203 adds r2, r2, #12
204 blt 22f
20521: mov r3, r7, pull #24
206 ldr r7, [r1], #4
207 subs r2, r2, #4
208 orr r3, r3, r7, push #8
209 str r3, [r0], #4
210 bge 21b
21122: sub r1, r1, #1
212 b 6b
213 43
44 .macro enter reg1 reg2
45 stmdb sp!, {r0, \reg1, \reg2}
46 .endm
214 47
21523: add r1, r1, r2 48 .macro exit reg1 reg2
216 add r0, r0, r2 49 ldmfd sp!, {r0, \reg1, \reg2}
217 subs r2, r2, #4 50 .endm
218 blt 29f
219 PLD( pld [r1, #-4] )
220 ands ip, r0, #3
221 bne 30f
222 ands ip, r1, #3
223 bne 31f
224 51
22524: subs r2, r2, #8 52 .text
226 blt 28f
227 subs r2, r2, #20
228 blt 27f
229 PLD( pld [r1, #-32] )
230 PLD( subs r2, r2, #64 )
231 PLD( blt 26f )
23225: PLD( pld [r1, #-64] )
233 PLD( pld [r1, #-96] )
234 ldmdb r1!, {r3 - r9, ip}
235 subs r2, r2, #32
236 stmgedb r0!, {r3 - r9, ip}
237 ldmgedb r1!, {r3 - r9, ip}
238 subges r2, r2, #32
239 stmdb r0!, {r3 - r9, ip}
240 bge 25b
24126: PLD( ldmdb r1!, {r3 - r9, ip} )
242 PLD( adds r2, r2, #32 )
243 PLD( stmgedb r0!, {r3 - r9, ip} )
244 PLD( ldmgedb r1!, {r3 - r9, ip} )
245 PLD( subges r2, r2, #32 )
246 PLD( stmdb r0!, {r3 - r9, ip} )
24727: cmn r2, #16
248 ldmgedb r1!, {r3 - r6}
249 subge r2, r2, #16
250 stmgedb r0!, {r3 - r6}
251 adds r2, r2, #20
252 ldmgedb r1!, {r3 - r5}
253 subge r2, r2, #12
254 stmgedb r0!, {r3 - r5}
25528: adds r2, r2, #8
256 blt 29f
257 subs r2, r2, #4
258 ldrlt r3, [r1, #-4]!
259 ldmgedb r1!, {r4, r5}
260 subge r2, r2, #4
261 strlt r3, [r0, #-4]!
262 stmgedb r0!, {r4, r5}
263 53
26429: adds r2, r2, #4 54/* Prototype: void *memcpy(void *dest, const void *src, size_t n); */
265 EXITEQ
266 cmp r2, #2
267 ldrb r3, [r1, #-1]!
268 ldrgeb r4, [r1, #-1]!
269 ldrgtb r5, [r1, #-1]!
270 strb r3, [r0, #-1]!
271 strgeb r4, [r0, #-1]!
272 strgtb r5, [r0, #-1]!
273 EXIT
274 55
27530: cmp ip, #2 56ENTRY(memcpy)
276 ldrb r3, [r1, #-1]!
277 ldrgeb r4, [r1, #-1]!
278 ldrgtb r5, [r1, #-1]!
279 strb r3, [r0, #-1]!
280 strgeb r4, [r0, #-1]!
281 strgtb r5, [r0, #-1]!
282 subs r2, r2, ip
283 blt 29b
284 ands ip, r1, #3
285 beq 24b
286
28731: bic r1, r1, #3
288 ldr r3, [r1], #0
289 cmp ip, #2
290 blt 41f
291 beq 36f
292 cmp r2, #12
293 blt 34f
294 PLD( pld [r1, #-16] )
295 sub r2, r2, #12
296 PLD( subs r2, r2, #32 )
297 PLD( blt 33f )
298 PLD( pld [r1, #-32] )
29932: PLD( pld [r1, #-48] )
30033: mov r7, r3, push #8
301 ldmdb r1!, {r3, r4, r5, r6}
302 subs r2, r2, #16
303 orr r7, r7, r6, pull #24
304 mov r6, r6, push #8
305 orr r6, r6, r5, pull #24
306 mov r5, r5, push #8
307 orr r5, r5, r4, pull #24
308 mov r4, r4, push #8
309 orr r4, r4, r3, pull #24
310 stmdb r0!, {r4, r5, r6, r7}
311 bge 32b
312 PLD( cmn r2, #32 )
313 PLD( bge 33b )
314 PLD( add r2, r2, #32 )
315 adds r2, r2, #12
316 blt 35f
31734: mov ip, r3, push #8
318 ldr r3, [r1, #-4]!
319 subs r2, r2, #4
320 orr ip, ip, r3, pull #24
321 str ip, [r0, #-4]!
322 bge 34b
32335: add r1, r1, #3
324 b 29b
325
32636: cmp r2, #12
327 blt 39f
328 PLD( pld [r1, #-16] )
329 sub r2, r2, #12
330 PLD( subs r2, r2, #32 )
331 PLD( blt 38f )
332 PLD( pld [r1, #-32] )
33337: PLD( pld [r1, #-48] )
33438: mov r7, r3, push #16
335 ldmdb r1!, {r3, r4, r5, r6}
336 subs r2, r2, #16
337 orr r7, r7, r6, pull #16
338 mov r6, r6, push #16
339 orr r6, r6, r5, pull #16
340 mov r5, r5, push #16
341 orr r5, r5, r4, pull #16
342 mov r4, r4, push #16
343 orr r4, r4, r3, pull #16
344 stmdb r0!, {r4, r5, r6, r7}
345 bge 37b
346 PLD( cmn r2, #32 )
347 PLD( bge 38b )
348 PLD( add r2, r2, #32 )
349 adds r2, r2, #12
350 blt 40f
35139: mov ip, r3, push #16
352 ldr r3, [r1, #-4]!
353 subs r2, r2, #4
354 orr ip, ip, r3, pull #16
355 str ip, [r0, #-4]!
356 bge 39b
35740: add r1, r1, #2
358 b 29b
359 57
36041: cmp r2, #12 58#include "copy_template.S"
361 blt 44f
362 PLD( pld [r1, #-16] )
363 sub r2, r2, #12
364 PLD( subs r2, r2, #32 )
365 PLD( blt 43f )
366 PLD( pld [r1, #-32] )
36742: PLD( pld [r1, #-48] )
36843: mov r7, r3, push #24
369 ldmdb r1!, {r3, r4, r5, r6}
370 subs r2, r2, #16
371 orr r7, r7, r6, pull #8
372 mov r6, r6, push #24
373 orr r6, r6, r5, pull #8
374 mov r5, r5, push #24
375 orr r5, r5, r4, pull #8
376 mov r4, r4, push #24
377 orr r4, r4, r3, pull #8
378 stmdb r0!, {r4, r5, r6, r7}
379 bge 42b
380 PLD( cmn r2, #32 )
381 PLD( bge 43b )
382 PLD( add r2, r2, #32 )
383 adds r2, r2, #12
384 blt 45f
38544: mov ip, r3, push #24
386 ldr r3, [r1, #-4]!
387 subs r2, r2, #4
388 orr ip, ip, r3, pull #8
389 str ip, [r0, #-4]!
390 bge 44b
39145: add r1, r1, #1
392 b 29b
393 59
diff --git a/arch/arm/lib/memmove.S b/arch/arm/lib/memmove.S
new file mode 100644
index 000000000000..ef7fddc14ac9
--- /dev/null
+++ b/arch/arm/lib/memmove.S
@@ -0,0 +1,206 @@
1/*
2 * linux/arch/arm/lib/memmove.S
3 *
4 * Author: Nicolas Pitre
5 * Created: Sep 28, 2005
6 * Copyright: (C) MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/linkage.h>
14#include <asm/assembler.h>
15
16/*
17 * This can be used to enable code to cacheline align the source pointer.
18 * Experiments on tested architectures (StrongARM and XScale) didn't show
19 * this a worthwhile thing to do. That might be different in the future.
20 */
21//#define CALGN(code...) code
22#define CALGN(code...)
23
24 .text
25
26/*
27 * Prototype: void *memmove(void *dest, const void *src, size_t n);
28 *
29 * Note:
30 *
31 * If the memory regions don't overlap, we simply branch to memcpy which is
32 * normally a bit faster. Otherwise the copy is done going downwards. This
33 * is a transposition of the code from copy_template.S but with the copy
34 * occurring in the opposite direction.
35 */
36
37ENTRY(memmove)
38
39 subs ip, r0, r1
40 cmphi r2, ip
41 bls memcpy
42
43 stmfd sp!, {r0, r4, lr}
44 add r1, r1, r2
45 add r0, r0, r2
46 subs r2, r2, #4
47 blt 8f
48 ands ip, r0, #3
49 PLD( pld [r1, #-4] )
50 bne 9f
51 ands ip, r1, #3
52 bne 10f
53
541: subs r2, r2, #(28)
55 stmfd sp!, {r5 - r8}
56 blt 5f
57
58 CALGN( ands ip, r1, #31 )
59 CALGN( sbcnes r4, ip, r2 ) @ C is always set here
60 CALGN( bcs 2f )
61 CALGN( adr r4, 6f )
62 CALGN( subs r2, r2, ip ) @ C is set here
63 CALGN( add pc, r4, ip )
64
65 PLD( pld [r1, #-4] )
662: PLD( subs r2, r2, #96 )
67 PLD( pld [r1, #-32] )
68 PLD( blt 4f )
69 PLD( pld [r1, #-64] )
70 PLD( pld [r1, #-96] )
71
723: PLD( pld [r1, #-128] )
734: ldmdb r1!, {r3, r4, r5, r6, r7, r8, ip, lr}
74 subs r2, r2, #32
75 stmdb r0!, {r3, r4, r5, r6, r7, r8, ip, lr}
76 bge 3b
77 PLD( cmn r2, #96 )
78 PLD( bge 4b )
79
805: ands ip, r2, #28
81 rsb ip, ip, #32
82 addne pc, pc, ip @ C is always clear here
83 b 7f
846: nop
85 ldr r3, [r1, #-4]!
86 ldr r4, [r1, #-4]!
87 ldr r5, [r1, #-4]!
88 ldr r6, [r1, #-4]!
89 ldr r7, [r1, #-4]!
90 ldr r8, [r1, #-4]!
91 ldr lr, [r1, #-4]!
92
93 add pc, pc, ip
94 nop
95 nop
96 str r3, [r0, #-4]!
97 str r4, [r0, #-4]!
98 str r5, [r0, #-4]!
99 str r6, [r0, #-4]!
100 str r7, [r0, #-4]!
101 str r8, [r0, #-4]!
102 str lr, [r0, #-4]!
103
104 CALGN( bcs 2b )
105
1067: ldmfd sp!, {r5 - r8}
107
1088: movs r2, r2, lsl #31
109 ldrneb r3, [r1, #-1]!
110 ldrcsb r4, [r1, #-1]!
111 ldrcsb ip, [r1, #-1]
112 strneb r3, [r0, #-1]!
113 strcsb r4, [r0, #-1]!
114 strcsb ip, [r0, #-1]
115 ldmfd sp!, {r0, r4, pc}
116
1179: cmp ip, #2
118 ldrgtb r3, [r1, #-1]!
119 ldrgeb r4, [r1, #-1]!
120 ldrb lr, [r1, #-1]!
121 strgtb r3, [r0, #-1]!
122 strgeb r4, [r0, #-1]!
123 subs r2, r2, ip
124 strb lr, [r0, #-1]!
125 blt 8b
126 ands ip, r1, #3
127 beq 1b
128
12910: bic r1, r1, #3
130 cmp ip, #2
131 ldr r3, [r1, #0]
132 beq 17f
133 blt 18f
134
135
136 .macro backward_copy_shift push pull
137
138 subs r2, r2, #28
139 blt 14f
140
141 CALGN( ands ip, r1, #31 )
142 CALGN( rsb ip, ip, #32 )
143 CALGN( sbcnes r4, ip, r2 ) @ C is always set here
144 CALGN( subcc r2, r2, ip )
145 CALGN( bcc 15f )
146
14711: stmfd sp!, {r5 - r9}
148
149 PLD( pld [r1, #-4] )
150 PLD( subs r2, r2, #96 )
151 PLD( pld [r1, #-32] )
152 PLD( blt 13f )
153 PLD( pld [r1, #-64] )
154 PLD( pld [r1, #-96] )
155
15612: PLD( pld [r1, #-128] )
15713: ldmdb r1!, {r7, r8, r9, ip}
158 mov lr, r3, push #\push
159 subs r2, r2, #32
160 ldmdb r1!, {r3, r4, r5, r6}
161 orr lr, lr, ip, pull #\pull
162 mov ip, ip, push #\push
163 orr ip, ip, r9, pull #\pull
164 mov r9, r9, push #\push
165 orr r9, r9, r8, pull #\pull
166 mov r8, r8, push #\push
167 orr r8, r8, r7, pull #\pull
168 mov r7, r7, push #\push
169 orr r7, r7, r6, pull #\pull
170 mov r6, r6, push #\push
171 orr r6, r6, r5, pull #\pull
172 mov r5, r5, push #\push
173 orr r5, r5, r4, pull #\pull
174 mov r4, r4, push #\push
175 orr r4, r4, r3, pull #\pull
176 stmdb r0!, {r4 - r9, ip, lr}
177 bge 12b
178 PLD( cmn r2, #96 )
179 PLD( bge 13b )
180
181 ldmfd sp!, {r5 - r9}
182
18314: ands ip, r2, #28
184 beq 16f
185
18615: mov lr, r3, push #\push
187 ldr r3, [r1, #-4]!
188 subs ip, ip, #4
189 orr lr, lr, r3, pull #\pull
190 str lr, [r0, #-4]!
191 bgt 15b
192 CALGN( cmp r2, #0 )
193 CALGN( bge 11b )
194
19516: add r1, r1, #(\pull / 8)
196 b 8b
197
198 .endm
199
200
201 backward_copy_shift push=8 pull=24
202
20317: backward_copy_shift push=16 pull=16
204
20518: backward_copy_shift push=24 pull=8
206
diff --git a/arch/arm/lib/uaccess.S b/arch/arm/lib/uaccess.S
index d3ed0636c008..c28449157bea 100644
--- a/arch/arm/lib/uaccess.S
+++ b/arch/arm/lib/uaccess.S
@@ -657,41 +657,3 @@ USER( ldrgtbt r3, [r1], #1) @ May fault
657 LOADREGS(fd,sp!, {r4 - r7, pc}) 657 LOADREGS(fd,sp!, {r4 - r7, pc})
658 .previous 658 .previous
659 659
660/* Prototype: int __arch_clear_user(void *addr, size_t sz)
661 * Purpose : clear some user memory
662 * Params : addr - user memory address to clear
663 * : sz - number of bytes to clear
664 * Returns : number of bytes NOT cleared
665 */
666ENTRY(__arch_clear_user)
667 stmfd sp!, {r1, lr}
668 mov r2, #0
669 cmp r1, #4
670 blt 2f
671 ands ip, r0, #3
672 beq 1f
673 cmp ip, #2
674USER( strbt r2, [r0], #1)
675USER( strlebt r2, [r0], #1)
676USER( strltbt r2, [r0], #1)
677 rsb ip, ip, #4
678 sub r1, r1, ip @ 7 6 5 4 3 2 1
6791: subs r1, r1, #8 @ -1 -2 -3 -4 -5 -6 -7
680USER( strplt r2, [r0], #4)
681USER( strplt r2, [r0], #4)
682 bpl 1b
683 adds r1, r1, #4 @ 3 2 1 0 -1 -2 -3
684USER( strplt r2, [r0], #4)
6852: tst r1, #2 @ 1x 1x 0x 0x 1x 1x 0x
686USER( strnebt r2, [r0], #1)
687USER( strnebt r2, [r0], #1)
688 tst r1, #1 @ x1 x0 x1 x0 x1 x0 x1
689USER( strnebt r2, [r0], #1)
690 mov r0, #0
691 LOADREGS(fd,sp!, {r1, pc})
692
693 .section .fixup,"ax"
694 .align 0
6959001: LOADREGS(fd,sp!, {r0, pc})
696 .previous
697
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index 15261646dcdd..ed4614983adb 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -251,9 +251,33 @@ static struct platform_device serial_device = {
251 }, 251 },
252}; 252};
253 253
254static struct resource am79c961_resources[] = {
255 {
256 .start = 0x220,
257 .end = 0x238,
258 .flags = IORESOURCE_IO,
259 }, {
260 .start = IRQ_EBSA110_ETHERNET,
261 .end = IRQ_EBSA110_ETHERNET,
262 .flags = IORESOURCE_IRQ,
263 },
264};
265
266static struct platform_device am79c961_device = {
267 .name = "am79c961",
268 .id = -1,
269 .num_resources = ARRAY_SIZE(am79c961_resources),
270 .resource = am79c961_resources,
271};
272
273static struct platform_device *ebsa110_devices[] = {
274 &serial_device,
275 &am79c961_device,
276};
277
254static int __init ebsa110_init(void) 278static int __init ebsa110_init(void)
255{ 279{
256 return platform_device_register(&serial_device); 280 return platform_add_devices(ebsa110_devices, ARRAY_SIZE(ebsa110_devices));
257} 281}
258 282
259arch_initcall(ebsa110_init); 283arch_initcall(ebsa110_init);
diff --git a/arch/arm/mach-ixp2000/Makefile b/arch/arm/mach-ixp2000/Makefile
index 1e6139d42a92..9621aeb61f46 100644
--- a/arch/arm/mach-ixp2000/Makefile
+++ b/arch/arm/mach-ixp2000/Makefile
@@ -1,7 +1,7 @@
1# 1#
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4obj-y := core.o pci.o 4obj-y := core.o pci.o uengine.o
5obj-m := 5obj-m :=
6obj-n := 6obj-n :=
7obj- := 7obj- :=
diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c
index 01c393c504d0..c93a98b2a32c 100644
--- a/arch/arm/mach-ixp2000/core.c
+++ b/arch/arm/mach-ixp2000/core.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * arch/arm/mach-ixp2000/common.c 2 * arch/arm/mach-ixp2000/core.c
3 * 3 *
4 * Common routines used by all IXP2400/2800 based platforms. 4 * Common routines used by all IXP2400/2800 based platforms.
5 * 5 *
@@ -49,7 +49,6 @@ static unsigned long ixp2000_slowport_irq_flags;
49 *************************************************************************/ 49 *************************************************************************/
50void ixp2000_acquire_slowport(struct slowport_cfg *new_cfg, struct slowport_cfg *old_cfg) 50void ixp2000_acquire_slowport(struct slowport_cfg *new_cfg, struct slowport_cfg *old_cfg)
51{ 51{
52
53 spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags); 52 spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags);
54 53
55 old_cfg->CCR = *IXP2000_SLOWPORT_CCR; 54 old_cfg->CCR = *IXP2000_SLOWPORT_CCR;
@@ -62,7 +61,7 @@ void ixp2000_acquire_slowport(struct slowport_cfg *new_cfg, struct slowport_cfg
62 ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC); 61 ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC);
63 ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC); 62 ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC);
64 ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR); 63 ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR);
65 ixp2000_reg_write(IXP2000_SLOWPORT_ADC, new_cfg->ADC); 64 ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, new_cfg->ADC);
66} 65}
67 66
68void ixp2000_release_slowport(struct slowport_cfg *old_cfg) 67void ixp2000_release_slowport(struct slowport_cfg *old_cfg)
@@ -71,7 +70,7 @@ void ixp2000_release_slowport(struct slowport_cfg *old_cfg)
71 ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC); 70 ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC);
72 ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC); 71 ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC);
73 ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR); 72 ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR);
74 ixp2000_reg_write(IXP2000_SLOWPORT_ADC, old_cfg->ADC); 73 ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, old_cfg->ADC);
75 74
76 spin_unlock_irqrestore(&ixp2000_slowport_lock, 75 spin_unlock_irqrestore(&ixp2000_slowport_lock,
77 ixp2000_slowport_irq_flags); 76 ixp2000_slowport_irq_flags);
@@ -145,7 +144,7 @@ void __init ixp2000_map_io(void)
145 iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc)); 144 iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));
146 145
147 /* Set slowport to 8-bit mode. */ 146 /* Set slowport to 8-bit mode. */
148 ixp2000_reg_write(IXP2000_SLOWPORT_FRM, 1); 147 ixp2000_reg_wrb(IXP2000_SLOWPORT_FRM, 1);
149} 148}
150 149
151 150
@@ -209,7 +208,7 @@ static int ixp2000_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
209 write_seqlock(&xtime_lock); 208 write_seqlock(&xtime_lock);
210 209
211 /* clear timer 1 */ 210 /* clear timer 1 */
212 ixp2000_reg_write(IXP2000_T1_CLR, 1); 211 ixp2000_reg_wrb(IXP2000_T1_CLR, 1);
213 212
214 while ((next_jiffy_time - *missing_jiffy_timer_csr) > ticks_per_jiffy) { 213 while ((next_jiffy_time - *missing_jiffy_timer_csr) > ticks_per_jiffy) {
215 timer_tick(regs); 214 timer_tick(regs);
@@ -252,12 +251,12 @@ void __init ixp2000_init_time(unsigned long tick_rate)
252 251
253 ixp2000_reg_write(IXP2000_T4_CLR, 0); 252 ixp2000_reg_write(IXP2000_T4_CLR, 0);
254 ixp2000_reg_write(IXP2000_T4_CLD, -1); 253 ixp2000_reg_write(IXP2000_T4_CLD, -1);
255 ixp2000_reg_write(IXP2000_T4_CTL, (1 << 7)); 254 ixp2000_reg_wrb(IXP2000_T4_CTL, (1 << 7));
256 missing_jiffy_timer_csr = IXP2000_T4_CSR; 255 missing_jiffy_timer_csr = IXP2000_T4_CSR;
257 } else { 256 } else {
258 ixp2000_reg_write(IXP2000_T2_CLR, 0); 257 ixp2000_reg_write(IXP2000_T2_CLR, 0);
259 ixp2000_reg_write(IXP2000_T2_CLD, -1); 258 ixp2000_reg_write(IXP2000_T2_CLD, -1);
260 ixp2000_reg_write(IXP2000_T2_CTL, (1 << 7)); 259 ixp2000_reg_wrb(IXP2000_T2_CTL, (1 << 7));
261 missing_jiffy_timer_csr = IXP2000_T2_CSR; 260 missing_jiffy_timer_csr = IXP2000_T2_CSR;
262 } 261 }
263 next_jiffy_time = 0xffffffff; 262 next_jiffy_time = 0xffffffff;
@@ -279,7 +278,7 @@ static void update_gpio_int_csrs(void)
279 ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge); 278 ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge);
280 ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge); 279 ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge);
281 ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low); 280 ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low);
282 ixp2000_reg_write(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high); 281 ixp2000_reg_wrb(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high);
283} 282}
284 283
285void gpio_line_config(int line, int direction) 284void gpio_line_config(int line, int direction)
@@ -297,9 +296,9 @@ void gpio_line_config(int line, int direction)
297 GPIO_IRQ_level_high &= ~(1 << line); 296 GPIO_IRQ_level_high &= ~(1 << line);
298 update_gpio_int_csrs(); 297 update_gpio_int_csrs();
299 298
300 ixp2000_reg_write(IXP2000_GPIO_PDSR, 1 << line); 299 ixp2000_reg_wrb(IXP2000_GPIO_PDSR, 1 << line);
301 } else if (direction == GPIO_IN) { 300 } else if (direction == GPIO_IN) {
302 ixp2000_reg_write(IXP2000_GPIO_PDCR, 1 << line); 301 ixp2000_reg_wrb(IXP2000_GPIO_PDCR, 1 << line);
303 } 302 }
304 local_irq_restore(flags); 303 local_irq_restore(flags);
305} 304}
@@ -365,12 +364,12 @@ static void ixp2000_GPIO_irq_mask_ack(unsigned int irq)
365 364
366 ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0))); 365 ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
367 ixp2000_reg_write(IXP2000_GPIO_LDSR, (1 << (irq - IRQ_IXP2000_GPIO0))); 366 ixp2000_reg_write(IXP2000_GPIO_LDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
368 ixp2000_reg_write(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0))); 367 ixp2000_reg_wrb(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0)));
369} 368}
370 369
371static void ixp2000_GPIO_irq_mask(unsigned int irq) 370static void ixp2000_GPIO_irq_mask(unsigned int irq)
372{ 371{
373 ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0))); 372 ixp2000_reg_wrb(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
374} 373}
375 374
376static void ixp2000_GPIO_irq_unmask(unsigned int irq) 375static void ixp2000_GPIO_irq_unmask(unsigned int irq)
@@ -389,9 +388,9 @@ static void ixp2000_pci_irq_mask(unsigned int irq)
389{ 388{
390 unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE; 389 unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
391 if (irq == IRQ_IXP2000_PCIA) 390 if (irq == IRQ_IXP2000_PCIA)
392 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26))); 391 ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26)));
393 else if (irq == IRQ_IXP2000_PCIB) 392 else if (irq == IRQ_IXP2000_PCIB)
394 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27))); 393 ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27)));
395} 394}
396 395
397static void ixp2000_pci_irq_unmask(unsigned int irq) 396static void ixp2000_pci_irq_unmask(unsigned int irq)
@@ -411,7 +410,7 @@ static struct irqchip ixp2000_pci_irq_chip = {
411 410
412static void ixp2000_irq_mask(unsigned int irq) 411static void ixp2000_irq_mask(unsigned int irq)
413{ 412{
414 ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, (1 << irq)); 413 ixp2000_reg_wrb(IXP2000_IRQ_ENABLE_CLR, (1 << irq));
415} 414}
416 415
417static void ixp2000_irq_unmask(unsigned int irq) 416static void ixp2000_irq_unmask(unsigned int irq)
@@ -443,7 +442,7 @@ void __init ixp2000_init_irq(void)
443 ixp2000_reg_write(IXP2000_GPIO_INCR, -1); 442 ixp2000_reg_write(IXP2000_GPIO_INCR, -1);
444 443
445 /* clear PCI interrupt sources */ 444 /* clear PCI interrupt sources */
446 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, 0); 445 ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, 0);
447 446
448 /* 447 /*
449 * Certain bits in the IRQ status register of the 448 * Certain bits in the IRQ status register of the
diff --git a/arch/arm/mach-ixp2000/enp2611.c b/arch/arm/mach-ixp2000/enp2611.c
index 643f5e1c3d93..7719c478aa84 100644
--- a/arch/arm/mach-ixp2000/enp2611.c
+++ b/arch/arm/mach-ixp2000/enp2611.c
@@ -64,6 +64,35 @@ static struct sys_timer enp2611_timer = {
64 64
65 65
66/************************************************************************* 66/*************************************************************************
67 * ENP-2611 I/O
68 *************************************************************************/
69static struct map_desc enp2611_io_desc[] __initdata = {
70 {
71 .virtual = ENP2611_CALEB_VIRT_BASE,
72 .physical = ENP2611_CALEB_PHYS_BASE,
73 .length = ENP2611_CALEB_SIZE,
74 .type = MT_IXP2000_DEVICE
75 }, {
76 .virtual = ENP2611_PM3386_0_VIRT_BASE,
77 .physical = ENP2611_PM3386_0_PHYS_BASE,
78 .length = ENP2611_PM3386_0_SIZE,
79 .type = MT_IXP2000_DEVICE
80 }, {
81 .virtual = ENP2611_PM3386_1_VIRT_BASE,
82 .physical = ENP2611_PM3386_1_PHYS_BASE,
83 .length = ENP2611_PM3386_1_SIZE,
84 .type = MT_IXP2000_DEVICE
85 }
86};
87
88void __init enp2611_map_io(void)
89{
90 ixp2000_map_io();
91 iotable_init(enp2611_io_desc, ARRAY_SIZE(enp2611_io_desc));
92}
93
94
95/*************************************************************************
67 * ENP-2611 PCI 96 * ENP-2611 PCI
68 *************************************************************************/ 97 *************************************************************************/
69static int enp2611_pci_setup(int nr, struct pci_sys_data *sys) 98static int enp2611_pci_setup(int nr, struct pci_sys_data *sys)
@@ -229,7 +258,7 @@ MACHINE_START(ENP2611, "Radisys ENP-2611 PCI network processor board")
229 .phys_io = IXP2000_UART_PHYS_BASE, 258 .phys_io = IXP2000_UART_PHYS_BASE,
230 .io_pg_offst = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc, 259 .io_pg_offst = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
231 .boot_params = 0x00000100, 260 .boot_params = 0x00000100,
232 .map_io = ixp2000_map_io, 261 .map_io = enp2611_map_io,
233 .init_irq = ixp2000_init_irq, 262 .init_irq = ixp2000_init_irq,
234 .timer = &enp2611_timer, 263 .timer = &enp2611_timer,
235 .init_machine = enp2611_init_machine, 264 .init_machine = enp2611_init_machine,
diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c
index 05dfcb48c2b6..d628da56b4bc 100644
--- a/arch/arm/mach-ixp2000/ixdp2x00.c
+++ b/arch/arm/mach-ixp2000/ixdp2x00.c
@@ -81,7 +81,7 @@ static void ixdp2x00_irq_mask(unsigned int irq)
81 81
82 dummy = *board_irq_mask; 82 dummy = *board_irq_mask;
83 dummy |= IXP2000_BOARD_IRQ_MASK(irq); 83 dummy |= IXP2000_BOARD_IRQ_MASK(irq);
84 ixp2000_reg_write(board_irq_mask, dummy); 84 ixp2000_reg_wrb(board_irq_mask, dummy);
85 85
86#ifdef CONFIG_ARCH_IXDP2400 86#ifdef CONFIG_ARCH_IXDP2400
87 if (machine_is_ixdp2400()) 87 if (machine_is_ixdp2400())
@@ -101,7 +101,7 @@ static void ixdp2x00_irq_unmask(unsigned int irq)
101 101
102 dummy = *board_irq_mask; 102 dummy = *board_irq_mask;
103 dummy &= ~IXP2000_BOARD_IRQ_MASK(irq); 103 dummy &= ~IXP2000_BOARD_IRQ_MASK(irq);
104 ixp2000_reg_write(board_irq_mask, dummy); 104 ixp2000_reg_wrb(board_irq_mask, dummy);
105 105
106 if (machine_is_ixdp2400()) 106 if (machine_is_ixdp2400())
107 ixp2000_release_slowport(&old_cfg); 107 ixp2000_release_slowport(&old_cfg);
diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c
index b21249908ae4..e6a882f35da2 100644
--- a/arch/arm/mach-ixp2000/ixdp2x01.c
+++ b/arch/arm/mach-ixp2000/ixdp2x01.c
@@ -51,7 +51,7 @@
51 *************************************************************************/ 51 *************************************************************************/
52static void ixdp2x01_irq_mask(unsigned int irq) 52static void ixdp2x01_irq_mask(unsigned int irq)
53{ 53{
54 ixp2000_reg_write(IXDP2X01_INT_MASK_SET_REG, 54 ixp2000_reg_wrb(IXDP2X01_INT_MASK_SET_REG,
55 IXP2000_BOARD_IRQ_MASK(irq)); 55 IXP2000_BOARD_IRQ_MASK(irq));
56} 56}
57 57
@@ -114,7 +114,7 @@ void __init ixdp2x01_init_irq(void)
114 114
115 /* Mask all interrupts from CPLD, disable simulation */ 115 /* Mask all interrupts from CPLD, disable simulation */
116 ixp2000_reg_write(IXDP2X01_INT_MASK_SET_REG, 0xffffffff); 116 ixp2000_reg_write(IXDP2X01_INT_MASK_SET_REG, 0xffffffff);
117 ixp2000_reg_write(IXDP2X01_INT_SIM_REG, 0); 117 ixp2000_reg_wrb(IXDP2X01_INT_SIM_REG, 0);
118 118
119 for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) { 119 for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) {
120 if (irq & valid_irq_mask) { 120 if (irq & valid_irq_mask) {
@@ -299,7 +299,6 @@ struct hw_pci ixdp2x01_pci __initdata = {
299 299
300int __init ixdp2x01_pci_init(void) 300int __init ixdp2x01_pci_init(void)
301{ 301{
302
303 pci_common_init(&ixdp2x01_pci); 302 pci_common_init(&ixdp2x01_pci);
304 return 0; 303 return 0;
305} 304}
@@ -316,7 +315,7 @@ static struct flash_platform_data ixdp2x01_flash_platform_data = {
316 315
317static unsigned long ixdp2x01_flash_bank_setup(unsigned long ofs) 316static unsigned long ixdp2x01_flash_bank_setup(unsigned long ofs)
318{ 317{
319 ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG, 318 ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG,
320 ((ofs >> IXDP2X01_FLASH_WINDOW_BITS) | IXDP2X01_CPLD_FLASH_INTERN)); 319 ((ofs >> IXDP2X01_FLASH_WINDOW_BITS) | IXDP2X01_CPLD_FLASH_INTERN));
321 return (ofs & IXDP2X01_FLASH_WINDOW_MASK); 320 return (ofs & IXDP2X01_FLASH_WINDOW_MASK);
322} 321}
@@ -363,7 +362,7 @@ static struct platform_device *ixdp2x01_devices[] __initdata = {
363 362
364static void __init ixdp2x01_init_machine(void) 363static void __init ixdp2x01_init_machine(void)
365{ 364{
366 ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG, 365 ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG,
367 (IXDP2X01_CPLD_FLASH_BANK_MASK | IXDP2X01_CPLD_FLASH_INTERN)); 366 (IXDP2X01_CPLD_FLASH_BANK_MASK | IXDP2X01_CPLD_FLASH_INTERN));
368 367
369 ixdp2x01_flash_data.nr_banks = 368 ixdp2x01_flash_data.nr_banks =
diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c
index 522205acb316..d4bf1e1c0031 100644
--- a/arch/arm/mach-ixp2000/pci.c
+++ b/arch/arm/mach-ixp2000/pci.c
@@ -148,7 +148,7 @@ int ixp2000_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_re
148 local_irq_save(flags); 148 local_irq_save(flags);
149 temp = *(IXP2000_PCI_CONTROL); 149 temp = *(IXP2000_PCI_CONTROL);
150 if (temp & ((1 << 8) | (1 << 5))) { 150 if (temp & ((1 << 8) | (1 << 5))) {
151 ixp2000_reg_write(IXP2000_PCI_CONTROL, temp); 151 ixp2000_reg_wrb(IXP2000_PCI_CONTROL, temp);
152 } 152 }
153 153
154 temp = *(IXP2000_PCI_CMDSTAT); 154 temp = *(IXP2000_PCI_CMDSTAT);
@@ -178,8 +178,8 @@ clear_master_aborts(void)
178 178
179 local_irq_save(flags); 179 local_irq_save(flags);
180 temp = *(IXP2000_PCI_CONTROL); 180 temp = *(IXP2000_PCI_CONTROL);
181 if (temp & ((1 << 8) | (1 << 5))) { 181 if (temp & ((1 << 8) | (1 << 5))) {
182 ixp2000_reg_write(IXP2000_PCI_CONTROL, temp); 182 ixp2000_reg_wrb(IXP2000_PCI_CONTROL, temp);
183 } 183 }
184 184
185 temp = *(IXP2000_PCI_CMDSTAT); 185 temp = *(IXP2000_PCI_CMDSTAT);
diff --git a/arch/arm/mach-ixp2000/uengine.c b/arch/arm/mach-ixp2000/uengine.c
new file mode 100644
index 000000000000..43e234349d4a
--- /dev/null
+++ b/arch/arm/mach-ixp2000/uengine.c
@@ -0,0 +1,474 @@
1/*
2 * Generic library functions for the microengines found on the Intel
3 * IXP2000 series of network processors.
4 *
5 * Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org>
6 * Dedicated to Marija Kulikova.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU Lesser General Public License as
10 * published by the Free Software Foundation; either version 2.1 of the
11 * License, or (at your option) any later version.
12 */
13
14#include <linux/config.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/slab.h>
18#include <linux/module.h>
19#include <linux/string.h>
20#include <asm/hardware.h>
21#include <asm/arch/ixp2000-regs.h>
22#include <asm/arch/uengine.h>
23#include <asm/io.h>
24
25#define USTORE_ADDRESS 0x000
26#define USTORE_DATA_LOWER 0x004
27#define USTORE_DATA_UPPER 0x008
28#define CTX_ENABLES 0x018
29#define CC_ENABLE 0x01c
30#define CSR_CTX_POINTER 0x020
31#define INDIRECT_CTX_STS 0x040
32#define ACTIVE_CTX_STS 0x044
33#define INDIRECT_CTX_SIG_EVENTS 0x048
34#define INDIRECT_CTX_WAKEUP_EVENTS 0x050
35#define NN_PUT 0x080
36#define NN_GET 0x084
37#define TIMESTAMP_LOW 0x0c0
38#define TIMESTAMP_HIGH 0x0c4
39#define T_INDEX_BYTE_INDEX 0x0f4
40#define LOCAL_CSR_STATUS 0x180
41
42u32 ixp2000_uengine_mask;
43
44static void *ixp2000_uengine_csr_area(int uengine)
45{
46 return ((void *)IXP2000_UENGINE_CSR_VIRT_BASE) + (uengine << 10);
47}
48
49/*
50 * LOCAL_CSR_STATUS=1 after a read or write to a microengine's CSR
51 * space means that the microengine we tried to access was also trying
52 * to access its own CSR space on the same clock cycle as we did. When
53 * this happens, we lose the arbitration process by default, and the
54 * read or write we tried to do was not actually performed, so we try
55 * again until it succeeds.
56 */
57u32 ixp2000_uengine_csr_read(int uengine, int offset)
58{
59 void *uebase;
60 u32 *local_csr_status;
61 u32 *reg;
62 u32 value;
63
64 uebase = ixp2000_uengine_csr_area(uengine);
65
66 local_csr_status = (u32 *)(uebase + LOCAL_CSR_STATUS);
67 reg = (u32 *)(uebase + offset);
68 do {
69 value = ixp2000_reg_read(reg);
70 } while (ixp2000_reg_read(local_csr_status) & 1);
71
72 return value;
73}
74EXPORT_SYMBOL(ixp2000_uengine_csr_read);
75
76void ixp2000_uengine_csr_write(int uengine, int offset, u32 value)
77{
78 void *uebase;
79 u32 *local_csr_status;
80 u32 *reg;
81
82 uebase = ixp2000_uengine_csr_area(uengine);
83
84 local_csr_status = (u32 *)(uebase + LOCAL_CSR_STATUS);
85 reg = (u32 *)(uebase + offset);
86 do {
87 ixp2000_reg_write(reg, value);
88 } while (ixp2000_reg_read(local_csr_status) & 1);
89}
90EXPORT_SYMBOL(ixp2000_uengine_csr_write);
91
92void ixp2000_uengine_reset(u32 uengine_mask)
93{
94 ixp2000_reg_write(IXP2000_RESET1, uengine_mask & ixp2000_uengine_mask);
95 ixp2000_reg_write(IXP2000_RESET1, 0);
96}
97EXPORT_SYMBOL(ixp2000_uengine_reset);
98
99void ixp2000_uengine_set_mode(int uengine, u32 mode)
100{
101 /*
102 * CTL_STR_PAR_EN: unconditionally enable parity checking on
103 * control store.
104 */
105 mode |= 0x10000000;
106 ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mode);
107
108 /*
109 * Enable updating of condition codes.
110 */
111 ixp2000_uengine_csr_write(uengine, CC_ENABLE, 0x00002000);
112
113 /*
114 * Initialise other per-microengine registers.
115 */
116 ixp2000_uengine_csr_write(uengine, NN_PUT, 0x00);
117 ixp2000_uengine_csr_write(uengine, NN_GET, 0x00);
118 ixp2000_uengine_csr_write(uengine, T_INDEX_BYTE_INDEX, 0);
119}
120EXPORT_SYMBOL(ixp2000_uengine_set_mode);
121
122static int make_even_parity(u32 x)
123{
124 return hweight32(x) & 1;
125}
126
127static void ustore_write(int uengine, u64 insn)
128{
129 /*
130 * Generate even parity for top and bottom 20 bits.
131 */
132 insn |= (u64)make_even_parity((insn >> 20) & 0x000fffff) << 41;
133 insn |= (u64)make_even_parity(insn & 0x000fffff) << 40;
134
135 /*
136 * Write to microstore. The second write auto-increments
137 * the USTORE_ADDRESS index register.
138 */
139 ixp2000_uengine_csr_write(uengine, USTORE_DATA_LOWER, (u32)insn);
140 ixp2000_uengine_csr_write(uengine, USTORE_DATA_UPPER, (u32)(insn >> 32));
141}
142
143void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns)
144{
145 int i;
146
147 /*
148 * Start writing to microstore at address 0.
149 */
150 ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x80000000);
151 for (i = 0; i < insns; i++) {
152 u64 insn;
153
154 insn = (((u64)ucode[0]) << 32) |
155 (((u64)ucode[1]) << 24) |
156 (((u64)ucode[2]) << 16) |
157 (((u64)ucode[3]) << 8) |
158 ((u64)ucode[4]);
159 ucode += 5;
160
161 ustore_write(uengine, insn);
162 }
163
164 /*
165 * Pad with a few NOPs at the end (to avoid the microengine
166 * aborting as it prefetches beyond the last instruction), unless
167 * we run off the end of the instruction store first, at which
168 * point the address register will wrap back to zero.
169 */
170 for (i = 0; i < 4; i++) {
171 u32 addr;
172
173 addr = ixp2000_uengine_csr_read(uengine, USTORE_ADDRESS);
174 if (addr == 0x80000000)
175 break;
176 ustore_write(uengine, 0xf0000c0300ULL);
177 }
178
179 /*
180 * End programming.
181 */
182 ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x00000000);
183}
184EXPORT_SYMBOL(ixp2000_uengine_load_microcode);
185
186void ixp2000_uengine_init_context(int uengine, int context, int pc)
187{
188 /*
189 * Select the right context for indirect access.
190 */
191 ixp2000_uengine_csr_write(uengine, CSR_CTX_POINTER, context);
192
193 /*
194 * Initialise signal masks to immediately go to Ready state.
195 */
196 ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_SIG_EVENTS, 1);
197 ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_WAKEUP_EVENTS, 1);
198
199 /*
200 * Set program counter.
201 */
202 ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_STS, pc);
203}
204EXPORT_SYMBOL(ixp2000_uengine_init_context);
205
206void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask)
207{
208 u32 mask;
209
210 /*
211 * Enable the specified context to go to Executing state.
212 */
213 mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES);
214 mask |= ctx_mask << 8;
215 ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask);
216}
217EXPORT_SYMBOL(ixp2000_uengine_start_contexts);
218
219void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask)
220{
221 u32 mask;
222
223 /*
224 * Disable the Ready->Executing transition. Note that this
225 * does not stop the context until it voluntarily yields.
226 */
227 mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES);
228 mask &= ~(ctx_mask << 8);
229 ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask);
230}
231EXPORT_SYMBOL(ixp2000_uengine_stop_contexts);
232
233static int check_ixp_type(struct ixp2000_uengine_code *c)
234{
235 u32 product_id;
236 u32 rev;
237
238 product_id = ixp2000_reg_read(IXP2000_PRODUCT_ID);
239 if (((product_id >> 16) & 0x1f) != 0)
240 return 0;
241
242 switch ((product_id >> 8) & 0xff) {
243 case 0: /* IXP2800 */
244 if (!(c->cpu_model_bitmask & 4))
245 return 0;
246 break;
247
248 case 1: /* IXP2850 */
249 if (!(c->cpu_model_bitmask & 8))
250 return 0;
251 break;
252
253 case 2: /* IXP2400 */
254 if (!(c->cpu_model_bitmask & 2))
255 return 0;
256 break;
257
258 default:
259 return 0;
260 }
261
262 rev = product_id & 0xff;
263 if (rev < c->cpu_min_revision || rev > c->cpu_max_revision)
264 return 0;
265
266 return 1;
267}
268
269static void generate_ucode(u8 *ucode, u32 *gpr_a, u32 *gpr_b)
270{
271 int offset;
272 int i;
273
274 offset = 0;
275
276 for (i = 0; i < 128; i++) {
277 u8 b3;
278 u8 b2;
279 u8 b1;
280 u8 b0;
281
282 b3 = (gpr_a[i] >> 24) & 0xff;
283 b2 = (gpr_a[i] >> 16) & 0xff;
284 b1 = (gpr_a[i] >> 8) & 0xff;
285 b0 = gpr_a[i] & 0xff;
286
287 // immed[@ai, (b1 << 8) | b0]
288 // 11110000 0000VVVV VVVV11VV VVVVVV00 1IIIIIII
289 ucode[offset++] = 0xf0;
290 ucode[offset++] = (b1 >> 4);
291 ucode[offset++] = (b1 << 4) | 0x0c | (b0 >> 6);
292 ucode[offset++] = (b0 << 2);
293 ucode[offset++] = 0x80 | i;
294
295 // immed_w1[@ai, (b3 << 8) | b2]
296 // 11110100 0100VVVV VVVV11VV VVVVVV00 1IIIIIII
297 ucode[offset++] = 0xf4;
298 ucode[offset++] = 0x40 | (b3 >> 4);
299 ucode[offset++] = (b3 << 4) | 0x0c | (b2 >> 6);
300 ucode[offset++] = (b2 << 2);
301 ucode[offset++] = 0x80 | i;
302 }
303
304 for (i = 0; i < 128; i++) {
305 u8 b3;
306 u8 b2;
307 u8 b1;
308 u8 b0;
309
310 b3 = (gpr_b[i] >> 24) & 0xff;
311 b2 = (gpr_b[i] >> 16) & 0xff;
312 b1 = (gpr_b[i] >> 8) & 0xff;
313 b0 = gpr_b[i] & 0xff;
314
315 // immed[@bi, (b1 << 8) | b0]
316 // 11110000 0000VVVV VVVV001I IIIIII11 VVVVVVVV
317 ucode[offset++] = 0xf0;
318 ucode[offset++] = (b1 >> 4);
319 ucode[offset++] = (b1 << 4) | 0x02 | (i >> 6);
320 ucode[offset++] = (i << 2) | 0x03;
321 ucode[offset++] = b0;
322
323 // immed_w1[@bi, (b3 << 8) | b2]
324 // 11110100 0100VVVV VVVV001I IIIIII11 VVVVVVVV
325 ucode[offset++] = 0xf4;
326 ucode[offset++] = 0x40 | (b3 >> 4);
327 ucode[offset++] = (b3 << 4) | 0x02 | (i >> 6);
328 ucode[offset++] = (i << 2) | 0x03;
329 ucode[offset++] = b2;
330 }
331
332 // ctx_arb[kill]
333 ucode[offset++] = 0xe0;
334 ucode[offset++] = 0x00;
335 ucode[offset++] = 0x01;
336 ucode[offset++] = 0x00;
337 ucode[offset++] = 0x00;
338}
339
340static int set_initial_registers(int uengine, struct ixp2000_uengine_code *c)
341{
342 int per_ctx_regs;
343 u32 *gpr_a;
344 u32 *gpr_b;
345 u8 *ucode;
346 int i;
347
348 gpr_a = kmalloc(128 * sizeof(u32), GFP_KERNEL);
349 gpr_b = kmalloc(128 * sizeof(u32), GFP_KERNEL);
350 ucode = kmalloc(513 * 5, GFP_KERNEL);
351 if (gpr_a == NULL || gpr_b == NULL || ucode == NULL) {
352 kfree(ucode);
353 kfree(gpr_b);
354 kfree(gpr_a);
355 return 1;
356 }
357
358 per_ctx_regs = 16;
359 if (c->uengine_parameters & IXP2000_UENGINE_4_CONTEXTS)
360 per_ctx_regs = 32;
361
362 memset(gpr_a, 0, sizeof(gpr_a));
363 memset(gpr_b, 0, sizeof(gpr_b));
364 for (i = 0; i < 256; i++) {
365 struct ixp2000_reg_value *r = c->initial_reg_values + i;
366 u32 *bank;
367 int inc;
368 int j;
369
370 if (r->reg == -1)
371 break;
372
373 bank = (r->reg & 0x400) ? gpr_b : gpr_a;
374 inc = (r->reg & 0x80) ? 128 : per_ctx_regs;
375
376 j = r->reg & 0x7f;
377 while (j < 128) {
378 bank[j] = r->value;
379 j += inc;
380 }
381 }
382
383 generate_ucode(ucode, gpr_a, gpr_b);
384 ixp2000_uengine_load_microcode(uengine, ucode, 513);
385 ixp2000_uengine_init_context(uengine, 0, 0);
386 ixp2000_uengine_start_contexts(uengine, 0x01);
387 for (i = 0; i < 100; i++) {
388 u32 status;
389
390 status = ixp2000_uengine_csr_read(uengine, ACTIVE_CTX_STS);
391 if (!(status & 0x80000000))
392 break;
393 }
394 ixp2000_uengine_stop_contexts(uengine, 0x01);
395
396 kfree(ucode);
397 kfree(gpr_b);
398 kfree(gpr_a);
399
400 return !!(i == 100);
401}
402
403int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c)
404{
405 int ctx;
406
407 if (!check_ixp_type(c))
408 return 1;
409
410 if (!(ixp2000_uengine_mask & (1 << uengine)))
411 return 1;
412
413 ixp2000_uengine_reset(1 << uengine);
414 ixp2000_uengine_set_mode(uengine, c->uengine_parameters);
415 if (set_initial_registers(uengine, c))
416 return 1;
417 ixp2000_uengine_load_microcode(uengine, c->insns, c->num_insns);
418
419 for (ctx = 0; ctx < 8; ctx++)
420 ixp2000_uengine_init_context(uengine, ctx, 0);
421
422 return 0;
423}
424EXPORT_SYMBOL(ixp2000_uengine_load);
425
426
427static int __init ixp2000_uengine_init(void)
428{
429 int uengine;
430 u32 value;
431
432 /*
433 * Determine number of microengines present.
434 */
435 switch ((ixp2000_reg_read(IXP2000_PRODUCT_ID) >> 8) & 0x1fff) {
436 case 0: /* IXP2800 */
437 case 1: /* IXP2850 */
438 ixp2000_uengine_mask = 0x00ff00ff;
439 break;
440
441 case 2: /* IXP2400 */
442 ixp2000_uengine_mask = 0x000f000f;
443 break;
444
445 default:
446 printk(KERN_INFO "Detected unknown IXP2000 model (%.8x)\n",
447 (unsigned int)ixp2000_reg_read(IXP2000_PRODUCT_ID));
448 ixp2000_uengine_mask = 0x00000000;
449 break;
450 }
451
452 /*
453 * Reset microengines.
454 */
455 ixp2000_reg_write(IXP2000_RESET1, ixp2000_uengine_mask);
456 ixp2000_reg_write(IXP2000_RESET1, 0);
457
458 /*
459 * Synchronise timestamp counters across all microengines.
460 */
461 value = ixp2000_reg_read(IXP2000_MISC_CONTROL);
462 ixp2000_reg_write(IXP2000_MISC_CONTROL, value & ~0x80);
463 for (uengine = 0; uengine < 32; uengine++) {
464 if (ixp2000_uengine_mask & (1 << uengine)) {
465 ixp2000_uengine_csr_write(uengine, TIMESTAMP_LOW, 0);
466 ixp2000_uengine_csr_write(uengine, TIMESTAMP_HIGH, 0);
467 }
468 }
469 ixp2000_reg_write(IXP2000_MISC_CONTROL, value | 0x80);
470
471 return 0;
472}
473
474subsys_initcall(ixp2000_uengine_init);
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 1f6857d7747d..9c6e77faec5b 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -175,7 +175,7 @@ static struct platform_device sa1111_device = {
175static struct resource smc91x_resources[] = { 175static struct resource smc91x_resources[] = {
176 [0] = { 176 [0] = {
177 .name = "smc91x-regs", 177 .name = "smc91x-regs",
178 .start = 0x0c000000, 178 .start = 0x0c000c00,
179 .end = 0x0c0fffff, 179 .end = 0x0c0fffff,
180 .flags = IORESOURCE_MEM, 180 .flags = IORESOURCE_MEM,
181 }, 181 },
@@ -224,18 +224,75 @@ static struct pxafb_mach_info sharp_lm8v31 __initdata = {
224 .lccr3 = LCCR3_PCP | LCCR3_Acb(255), 224 .lccr3 = LCCR3_PCP | LCCR3_Acb(255),
225}; 225};
226 226
227static int lubbock_mci_init(struct device *dev, irqreturn_t (*lubbock_detect_int)(int, void *, struct pt_regs *), void *data) 227#define MMC_POLL_RATE msecs_to_jiffies(1000)
228
229static void lubbock_mmc_poll(unsigned long);
230static irqreturn_t (*mmc_detect_int)(int, void *, struct pt_regs *);
231
232static struct timer_list mmc_timer = {
233 .function = lubbock_mmc_poll,
234};
235
236static void lubbock_mmc_poll(unsigned long data)
237{
238 unsigned long flags;
239
240 /* clear any previous irq state, then ... */
241 local_irq_save(flags);
242 LUB_IRQ_SET_CLR &= ~(1 << 0);
243 local_irq_restore(flags);
244
245 /* poll until mmc/sd card is removed */
246 if (LUB_IRQ_SET_CLR & (1 << 0))
247 mod_timer(&mmc_timer, jiffies + MMC_POLL_RATE);
248 else {
249 (void) mmc_detect_int(LUBBOCK_SD_IRQ, (void *)data, NULL);
250 enable_irq(LUBBOCK_SD_IRQ);
251 }
252}
253
254static irqreturn_t lubbock_detect_int(int irq, void *data, struct pt_regs *regs)
255{
256 /* IRQ is level triggered; disable, and poll for removal */
257 disable_irq(irq);
258 mod_timer(&mmc_timer, jiffies + MMC_POLL_RATE);
259
260 return mmc_detect_int(irq, data, regs);
261}
262
263static int lubbock_mci_init(struct device *dev,
264 irqreturn_t (*detect_int)(int, void *, struct pt_regs *),
265 void *data)
228{ 266{
229 /* setup GPIO for PXA25x MMC controller */ 267 /* setup GPIO for PXA25x MMC controller */
230 pxa_gpio_mode(GPIO6_MMCCLK_MD); 268 pxa_gpio_mode(GPIO6_MMCCLK_MD);
231 pxa_gpio_mode(GPIO8_MMCCS0_MD); 269 pxa_gpio_mode(GPIO8_MMCCS0_MD);
232 270
233 return 0; 271 /* detect card insert/eject */
272 mmc_detect_int = detect_int;
273 init_timer(&mmc_timer);
274 mmc_timer.data = (unsigned long) data;
275 return request_irq(LUBBOCK_SD_IRQ, lubbock_detect_int,
276 SA_SAMPLE_RANDOM, "lubbock-sd-detect", data);
277}
278
279static int lubbock_mci_get_ro(struct device *dev)
280{
281 return (LUB_MISC_RD & (1 << 2)) != 0;
282}
283
284static void lubbock_mci_exit(struct device *dev, void *data)
285{
286 free_irq(LUBBOCK_SD_IRQ, data);
287 del_timer_sync(&mmc_timer);
234} 288}
235 289
236static struct pxamci_platform_data lubbock_mci_platform_data = { 290static struct pxamci_platform_data lubbock_mci_platform_data = {
237 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, 291 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
292 .detect_delay = 1,
238 .init = lubbock_mci_init, 293 .init = lubbock_mci_init,
294 .get_ro = lubbock_mci_get_ro,
295 .exit = lubbock_mci_exit,
239}; 296};
240 297
241static void lubbock_irda_transceiver_mode(struct device *dev, int mode) 298static void lubbock_irda_transceiver_mode(struct device *dev, int mode)
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
new file mode 100644
index 000000000000..4b63dc9eabfe
--- /dev/null
+++ b/arch/arm/mach-realview/Kconfig
@@ -0,0 +1,11 @@
1menu "RealView platform type"
2 depends on ARCH_REALVIEW
3
4config MACH_REALVIEW_EB
5 bool "Support RealView/EB platform"
6 default n
7 select ARM_GIC
8 help
9 Include support for the ARM(R) RealView Emulation Baseboard platform.
10
11endmenu
diff --git a/arch/arm/mach-realview/Makefile b/arch/arm/mach-realview/Makefile
new file mode 100644
index 000000000000..8d37ea1605fd
--- /dev/null
+++ b/arch/arm/mach-realview/Makefile
@@ -0,0 +1,6 @@
1#
2# Makefile for the linux kernel.
3#
4
5obj-y := core.o clock.o
6obj-$(CONFIG_MACH_REALVIEW_EB) += realview_eb.o
diff --git a/arch/arm/mach-realview/Makefile.boot b/arch/arm/mach-realview/Makefile.boot
new file mode 100644
index 000000000000..c7e75acfe6c9
--- /dev/null
+++ b/arch/arm/mach-realview/Makefile.boot
@@ -0,0 +1,4 @@
1 zreladdr-y := 0x00008000
2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000
4
diff --git a/arch/arm/mach-realview/clock.c b/arch/arm/mach-realview/clock.c
new file mode 100644
index 000000000000..002635c97bb6
--- /dev/null
+++ b/arch/arm/mach-realview/clock.c
@@ -0,0 +1,145 @@
1/*
2 * linux/arch/arm/mach-realview/clock.c
3 *
4 * Copyright (C) 2004 ARM Limited.
5 * Written by Deep Blue Solutions Limited.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/list.h>
14#include <linux/errno.h>
15#include <linux/err.h>
16
17#include <asm/semaphore.h>
18#include <asm/hardware/clock.h>
19#include <asm/hardware/icst307.h>
20
21#include "clock.h"
22
23static LIST_HEAD(clocks);
24static DECLARE_MUTEX(clocks_sem);
25
26struct clk *clk_get(struct device *dev, const char *id)
27{
28 struct clk *p, *clk = ERR_PTR(-ENOENT);
29
30 down(&clocks_sem);
31 list_for_each_entry(p, &clocks, node) {
32 if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
33 clk = p;
34 break;
35 }
36 }
37 up(&clocks_sem);
38
39 return clk;
40}
41EXPORT_SYMBOL(clk_get);
42
43void clk_put(struct clk *clk)
44{
45 module_put(clk->owner);
46}
47EXPORT_SYMBOL(clk_put);
48
49int clk_enable(struct clk *clk)
50{
51 return 0;
52}
53EXPORT_SYMBOL(clk_enable);
54
55void clk_disable(struct clk *clk)
56{
57}
58EXPORT_SYMBOL(clk_disable);
59
60int clk_use(struct clk *clk)
61{
62 return 0;
63}
64EXPORT_SYMBOL(clk_use);
65
66void clk_unuse(struct clk *clk)
67{
68}
69EXPORT_SYMBOL(clk_unuse);
70
71unsigned long clk_get_rate(struct clk *clk)
72{
73 return clk->rate;
74}
75EXPORT_SYMBOL(clk_get_rate);
76
77long clk_round_rate(struct clk *clk, unsigned long rate)
78{
79 return rate;
80}
81EXPORT_SYMBOL(clk_round_rate);
82
83int clk_set_rate(struct clk *clk, unsigned long rate)
84{
85 int ret = -EIO;
86
87 if (clk->setvco) {
88 struct icst307_vco vco;
89
90 vco = icst307_khz_to_vco(clk->params, rate / 1000);
91 clk->rate = icst307_khz(clk->params, vco) * 1000;
92
93 printk("Clock %s: setting VCO reg params: S=%d R=%d V=%d\n",
94 clk->name, vco.s, vco.r, vco.v);
95
96 clk->setvco(clk, vco);
97 ret = 0;
98 }
99 return ret;
100}
101EXPORT_SYMBOL(clk_set_rate);
102
103/*
104 * These are fixed clocks.
105 */
106static struct clk kmi_clk = {
107 .name = "KMIREFCLK",
108 .rate = 24000000,
109};
110
111static struct clk uart_clk = {
112 .name = "UARTCLK",
113 .rate = 24000000,
114};
115
116static struct clk mmci_clk = {
117 .name = "MCLK",
118 .rate = 33000000,
119};
120
121int clk_register(struct clk *clk)
122{
123 down(&clocks_sem);
124 list_add(&clk->node, &clocks);
125 up(&clocks_sem);
126 return 0;
127}
128EXPORT_SYMBOL(clk_register);
129
130void clk_unregister(struct clk *clk)
131{
132 down(&clocks_sem);
133 list_del(&clk->node);
134 up(&clocks_sem);
135}
136EXPORT_SYMBOL(clk_unregister);
137
138static int __init clk_init(void)
139{
140 clk_register(&kmi_clk);
141 clk_register(&uart_clk);
142 clk_register(&mmci_clk);
143 return 0;
144}
145arch_initcall(clk_init);
diff --git a/arch/arm/mach-realview/clock.h b/arch/arm/mach-realview/clock.h
new file mode 100644
index 000000000000..dadba695e181
--- /dev/null
+++ b/arch/arm/mach-realview/clock.h
@@ -0,0 +1,25 @@
1/*
2 * linux/arch/arm/mach-realview/clock.h
3 *
4 * Copyright (C) 2004 ARM Limited.
5 * Written by Deep Blue Solutions Limited.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11struct module;
12struct icst307_params;
13
14struct clk {
15 struct list_head node;
16 unsigned long rate;
17 struct module *owner;
18 const char *name;
19 const struct icst307_params *params;
20 void *data;
21 void (*setvco)(struct clk *, struct icst307_vco vco);
22};
23
24int clk_register(struct clk *clk);
25void clk_unregister(struct clk *clk);
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
new file mode 100644
index 000000000000..482eb512ebe8
--- /dev/null
+++ b/arch/arm/mach-realview/core.c
@@ -0,0 +1,605 @@
1/*
2 * linux/arch/arm/mach-realview/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/config.h>
22#include <linux/init.h>
23#include <linux/platform_device.h>
24#include <linux/dma-mapping.h>
25#include <linux/sysdev.h>
26#include <linux/interrupt.h>
27
28#include <asm/system.h>
29#include <asm/hardware.h>
30#include <asm/io.h>
31#include <asm/irq.h>
32#include <asm/leds.h>
33#include <asm/mach-types.h>
34#include <asm/hardware/amba.h>
35#include <asm/hardware/amba_clcd.h>
36#include <asm/hardware/arm_timer.h>
37#include <asm/hardware/icst307.h>
38
39#include <asm/mach/arch.h>
40#include <asm/mach/flash.h>
41#include <asm/mach/irq.h>
42#include <asm/mach/time.h>
43#include <asm/mach/map.h>
44#include <asm/mach/mmc.h>
45
46#include <asm/hardware/gic.h>
47
48#include "core.h"
49#include "clock.h"
50
51#define REALVIEW_REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
52
53/*
54 * This is the RealView sched_clock implementation. This has
55 * a resolution of 41.7ns, and a maximum value of about 179s.
56 */
57unsigned long long sched_clock(void)
58{
59 unsigned long long v;
60
61 v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
62 do_div(v, 3);
63
64 return v;
65}
66
67
68#define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
69
70static int realview_flash_init(void)
71{
72 u32 val;
73
74 val = __raw_readl(REALVIEW_FLASHCTRL);
75 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
76 __raw_writel(val, REALVIEW_FLASHCTRL);
77
78 return 0;
79}
80
81static void realview_flash_exit(void)
82{
83 u32 val;
84
85 val = __raw_readl(REALVIEW_FLASHCTRL);
86 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
87 __raw_writel(val, REALVIEW_FLASHCTRL);
88}
89
90static void realview_flash_set_vpp(int on)
91{
92 u32 val;
93
94 val = __raw_readl(REALVIEW_FLASHCTRL);
95 if (on)
96 val |= REALVIEW_FLASHPROG_FLVPPEN;
97 else
98 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
99 __raw_writel(val, REALVIEW_FLASHCTRL);
100}
101
102static struct flash_platform_data realview_flash_data = {
103 .map_name = "cfi_probe",
104 .width = 4,
105 .init = realview_flash_init,
106 .exit = realview_flash_exit,
107 .set_vpp = realview_flash_set_vpp,
108};
109
110static struct resource realview_flash_resource = {
111 .start = REALVIEW_FLASH_BASE,
112 .end = REALVIEW_FLASH_BASE + REALVIEW_FLASH_SIZE,
113 .flags = IORESOURCE_MEM,
114};
115
116struct platform_device realview_flash_device = {
117 .name = "armflash",
118 .id = 0,
119 .dev = {
120 .platform_data = &realview_flash_data,
121 },
122 .num_resources = 1,
123 .resource = &realview_flash_resource,
124};
125
126static struct resource realview_smc91x_resources[] = {
127 [0] = {
128 .start = REALVIEW_ETH_BASE,
129 .end = REALVIEW_ETH_BASE + SZ_64K - 1,
130 .flags = IORESOURCE_MEM,
131 },
132 [1] = {
133 .start = IRQ_ETH,
134 .end = IRQ_ETH,
135 .flags = IORESOURCE_IRQ,
136 },
137};
138
139struct platform_device realview_smc91x_device = {
140 .name = "smc91x",
141 .id = 0,
142 .num_resources = ARRAY_SIZE(realview_smc91x_resources),
143 .resource = realview_smc91x_resources,
144};
145
146#define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
147
148static unsigned int realview_mmc_status(struct device *dev)
149{
150 struct amba_device *adev = container_of(dev, struct amba_device, dev);
151 u32 mask;
152
153 if (adev->res.start == REALVIEW_MMCI0_BASE)
154 mask = 1;
155 else
156 mask = 2;
157
158 return readl(REALVIEW_SYSMCI) & mask;
159}
160
161struct mmc_platform_data realview_mmc0_plat_data = {
162 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
163 .status = realview_mmc_status,
164};
165
166struct mmc_platform_data realview_mmc1_plat_data = {
167 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
168 .status = realview_mmc_status,
169};
170
171/*
172 * Clock handling
173 */
174static const struct icst307_params realview_oscvco_params = {
175 .ref = 24000,
176 .vco_max = 200000,
177 .vd_min = 4 + 8,
178 .vd_max = 511 + 8,
179 .rd_min = 1 + 2,
180 .rd_max = 127 + 2,
181};
182
183static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco)
184{
185 void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
186 void __iomem *sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC1_OFFSET;
187 u32 val;
188
189 val = readl(sys_osc) & ~0x7ffff;
190 val |= vco.v | (vco.r << 9) | (vco.s << 16);
191
192 writel(0xa05f, sys_lock);
193 writel(val, sys_osc);
194 writel(0, sys_lock);
195}
196
197struct clk realview_clcd_clk = {
198 .name = "CLCDCLK",
199 .params = &realview_oscvco_params,
200 .setvco = realview_oscvco_set,
201};
202
203/*
204 * CLCD support.
205 */
206#define SYS_CLCD_MODE_MASK (3 << 0)
207#define SYS_CLCD_MODE_888 (0 << 0)
208#define SYS_CLCD_MODE_5551 (1 << 0)
209#define SYS_CLCD_MODE_565_RLSB (2 << 0)
210#define SYS_CLCD_MODE_565_BLSB (3 << 0)
211#define SYS_CLCD_NLCDIOON (1 << 2)
212#define SYS_CLCD_VDDPOSSWITCH (1 << 3)
213#define SYS_CLCD_PWR3V5SWITCH (1 << 4)
214#define SYS_CLCD_ID_MASK (0x1f << 8)
215#define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
216#define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
217#define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
218#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
219#define SYS_CLCD_ID_VGA (0x1f << 8)
220
221static struct clcd_panel vga = {
222 .mode = {
223 .name = "VGA",
224 .refresh = 60,
225 .xres = 640,
226 .yres = 480,
227 .pixclock = 39721,
228 .left_margin = 40,
229 .right_margin = 24,
230 .upper_margin = 32,
231 .lower_margin = 11,
232 .hsync_len = 96,
233 .vsync_len = 2,
234 .sync = 0,
235 .vmode = FB_VMODE_NONINTERLACED,
236 },
237 .width = -1,
238 .height = -1,
239 .tim2 = TIM2_BCD | TIM2_IPC,
240 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
241 .bpp = 16,
242};
243
244static struct clcd_panel sanyo_3_8_in = {
245 .mode = {
246 .name = "Sanyo QVGA",
247 .refresh = 116,
248 .xres = 320,
249 .yres = 240,
250 .pixclock = 100000,
251 .left_margin = 6,
252 .right_margin = 6,
253 .upper_margin = 5,
254 .lower_margin = 5,
255 .hsync_len = 6,
256 .vsync_len = 6,
257 .sync = 0,
258 .vmode = FB_VMODE_NONINTERLACED,
259 },
260 .width = -1,
261 .height = -1,
262 .tim2 = TIM2_BCD,
263 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
264 .bpp = 16,
265};
266
267static struct clcd_panel sanyo_2_5_in = {
268 .mode = {
269 .name = "Sanyo QVGA Portrait",
270 .refresh = 116,
271 .xres = 240,
272 .yres = 320,
273 .pixclock = 100000,
274 .left_margin = 20,
275 .right_margin = 10,
276 .upper_margin = 2,
277 .lower_margin = 2,
278 .hsync_len = 10,
279 .vsync_len = 2,
280 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
281 .vmode = FB_VMODE_NONINTERLACED,
282 },
283 .width = -1,
284 .height = -1,
285 .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC,
286 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
287 .bpp = 16,
288};
289
290static struct clcd_panel epson_2_2_in = {
291 .mode = {
292 .name = "Epson QCIF",
293 .refresh = 390,
294 .xres = 176,
295 .yres = 220,
296 .pixclock = 62500,
297 .left_margin = 3,
298 .right_margin = 2,
299 .upper_margin = 1,
300 .lower_margin = 0,
301 .hsync_len = 3,
302 .vsync_len = 2,
303 .sync = 0,
304 .vmode = FB_VMODE_NONINTERLACED,
305 },
306 .width = -1,
307 .height = -1,
308 .tim2 = TIM2_BCD | TIM2_IPC,
309 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
310 .bpp = 16,
311};
312
313/*
314 * Detect which LCD panel is connected, and return the appropriate
315 * clcd_panel structure. Note: we do not have any information on
316 * the required timings for the 8.4in panel, so we presently assume
317 * VGA timings.
318 */
319static struct clcd_panel *realview_clcd_panel(void)
320{
321 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
322 struct clcd_panel *panel = &vga;
323 u32 val;
324
325 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
326 if (val == SYS_CLCD_ID_SANYO_3_8)
327 panel = &sanyo_3_8_in;
328 else if (val == SYS_CLCD_ID_SANYO_2_5)
329 panel = &sanyo_2_5_in;
330 else if (val == SYS_CLCD_ID_EPSON_2_2)
331 panel = &epson_2_2_in;
332 else if (val == SYS_CLCD_ID_VGA)
333 panel = &vga;
334 else {
335 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
336 val);
337 panel = &vga;
338 }
339
340 return panel;
341}
342
343/*
344 * Disable all display connectors on the interface module.
345 */
346static void realview_clcd_disable(struct clcd_fb *fb)
347{
348 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
349 u32 val;
350
351 val = readl(sys_clcd);
352 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
353 writel(val, sys_clcd);
354}
355
356/*
357 * Enable the relevant connector on the interface module.
358 */
359static void realview_clcd_enable(struct clcd_fb *fb)
360{
361 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
362 u32 val;
363
364 val = readl(sys_clcd);
365 val &= ~SYS_CLCD_MODE_MASK;
366
367 switch (fb->fb.var.green.length) {
368 case 5:
369 val |= SYS_CLCD_MODE_5551;
370 break;
371 case 6:
372 val |= SYS_CLCD_MODE_565_RLSB;
373 break;
374 case 8:
375 val |= SYS_CLCD_MODE_888;
376 break;
377 }
378
379 /*
380 * Set the MUX
381 */
382 writel(val, sys_clcd);
383
384 /*
385 * And now enable the PSUs
386 */
387 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
388 writel(val, sys_clcd);
389}
390
391static unsigned long framesize = SZ_1M;
392
393static int realview_clcd_setup(struct clcd_fb *fb)
394{
395 dma_addr_t dma;
396
397 fb->panel = realview_clcd_panel();
398
399 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
400 &dma, GFP_KERNEL);
401 if (!fb->fb.screen_base) {
402 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
403 return -ENOMEM;
404 }
405
406 fb->fb.fix.smem_start = dma;
407 fb->fb.fix.smem_len = framesize;
408
409 return 0;
410}
411
412static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
413{
414 return dma_mmap_writecombine(&fb->dev->dev, vma,
415 fb->fb.screen_base,
416 fb->fb.fix.smem_start,
417 fb->fb.fix.smem_len);
418}
419
420static void realview_clcd_remove(struct clcd_fb *fb)
421{
422 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
423 fb->fb.screen_base, fb->fb.fix.smem_start);
424}
425
426struct clcd_board clcd_plat_data = {
427 .name = "RealView",
428 .check = clcdfb_check,
429 .decode = clcdfb_decode,
430 .disable = realview_clcd_disable,
431 .enable = realview_clcd_enable,
432 .setup = realview_clcd_setup,
433 .mmap = realview_clcd_mmap,
434 .remove = realview_clcd_remove,
435};
436
437#ifdef CONFIG_LEDS
438#define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
439
440void realview_leds_event(led_event_t ledevt)
441{
442 unsigned long flags;
443 u32 val;
444
445 local_irq_save(flags);
446 val = readl(VA_LEDS_BASE);
447
448 switch (ledevt) {
449 case led_idle_start:
450 val = val & ~REALVIEW_SYS_LED0;
451 break;
452
453 case led_idle_end:
454 val = val | REALVIEW_SYS_LED0;
455 break;
456
457 case led_timer:
458 val = val ^ REALVIEW_SYS_LED1;
459 break;
460
461 case led_halted:
462 val = 0;
463 break;
464
465 default:
466 break;
467 }
468
469 writel(val, VA_LEDS_BASE);
470 local_irq_restore(flags);
471}
472#endif /* CONFIG_LEDS */
473
474/*
475 * Where is the timer (VA)?
476 */
477#define TIMER0_VA_BASE __io_address(REALVIEW_TIMER0_1_BASE)
478#define TIMER1_VA_BASE (__io_address(REALVIEW_TIMER0_1_BASE) + 0x20)
479#define TIMER2_VA_BASE __io_address(REALVIEW_TIMER2_3_BASE)
480#define TIMER3_VA_BASE (__io_address(REALVIEW_TIMER2_3_BASE) + 0x20)
481
482/*
483 * How long is the timer interval?
484 */
485#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
486#if TIMER_INTERVAL >= 0x100000
487#define TIMER_RELOAD (TIMER_INTERVAL >> 8)
488#define TIMER_DIVISOR (TIMER_CTRL_DIV256)
489#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
490#elif TIMER_INTERVAL >= 0x10000
491#define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
492#define TIMER_DIVISOR (TIMER_CTRL_DIV16)
493#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
494#else
495#define TIMER_RELOAD (TIMER_INTERVAL)
496#define TIMER_DIVISOR (TIMER_CTRL_DIV1)
497#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
498#endif
499
500/*
501 * Returns number of ms since last clock interrupt. Note that interrupts
502 * will have been disabled by do_gettimeoffset()
503 */
504static unsigned long realview_gettimeoffset(void)
505{
506 unsigned long ticks1, ticks2, status;
507
508 /*
509 * Get the current number of ticks. Note that there is a race
510 * condition between us reading the timer and checking for
511 * an interrupt. We get around this by ensuring that the
512 * counter has not reloaded between our two reads.
513 */
514 ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
515 do {
516 ticks1 = ticks2;
517 status = __raw_readl(__io_address(REALVIEW_GIC_DIST_BASE + GIC_DIST_PENDING_SET)
518 + ((IRQ_TIMERINT0_1 >> 5) << 2));
519 ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
520 } while (ticks2 > ticks1);
521
522 /*
523 * Number of ticks since last interrupt.
524 */
525 ticks1 = TIMER_RELOAD - ticks2;
526
527 /*
528 * Interrupt pending? If so, we've reloaded once already.
529 *
530 * FIXME: Need to check this is effectively timer 0 that expires
531 */
532 if (status & IRQMASK_TIMERINT0_1)
533 ticks1 += TIMER_RELOAD;
534
535 /*
536 * Convert the ticks to usecs
537 */
538 return TICKS2USECS(ticks1);
539}
540
541/*
542 * IRQ handler for the timer
543 */
544static irqreturn_t realview_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
545{
546 write_seqlock(&xtime_lock);
547
548 // ...clear the interrupt
549 writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
550
551 timer_tick(regs);
552
553 write_sequnlock(&xtime_lock);
554
555 return IRQ_HANDLED;
556}
557
558static struct irqaction realview_timer_irq = {
559 .name = "RealView Timer Tick",
560 .flags = SA_INTERRUPT | SA_TIMER,
561 .handler = realview_timer_interrupt,
562};
563
564/*
565 * Set up timer interrupt, and return the current time in seconds.
566 */
567static void __init realview_timer_init(void)
568{
569 u32 val;
570
571 /*
572 * set clock frequency:
573 * REALVIEW_REFCLK is 32KHz
574 * REALVIEW_TIMCLK is 1MHz
575 */
576 val = readl(__io_address(REALVIEW_SCTL_BASE));
577 writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
578 (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
579 (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
580 (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
581 __io_address(REALVIEW_SCTL_BASE));
582
583 /*
584 * Initialise to a known state (all timers off)
585 */
586 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
587 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
588 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
589 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
590
591 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
592 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_VALUE);
593 writel(TIMER_DIVISOR | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC |
594 TIMER_CTRL_IE, TIMER0_VA_BASE + TIMER_CTRL);
595
596 /*
597 * Make irqs happen for the system timer
598 */
599 setup_irq(IRQ_TIMERINT0_1, &realview_timer_irq);
600}
601
602struct sys_timer realview_timer = {
603 .init = realview_timer_init,
604 .offset = realview_gettimeoffset,
605};
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h
new file mode 100644
index 000000000000..575599db74db
--- /dev/null
+++ b/arch/arm/mach-realview/core.h
@@ -0,0 +1,118 @@
1/*
2 * linux/arch/arm/mach-realview/core.h
3 *
4 * Copyright (C) 2004 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#ifndef __ASM_ARCH_REALVIEW_H
23#define __ASM_ARCH_REALVIEW_H
24
25#include <asm/hardware/amba.h>
26#include <asm/io.h>
27
28#define __io_address(n) __io(IO_ADDRESS(n))
29
30extern struct sys_timer realview_timer;
31
32#define AMBA_DEVICE(name,busid,base,plat) \
33static struct amba_device name##_device = { \
34 .dev = { \
35 .coherent_dma_mask = ~0, \
36 .bus_id = busid, \
37 .platform_data = plat, \
38 }, \
39 .res = { \
40 .start = REALVIEW_##base##_BASE, \
41 .end = (REALVIEW_##base##_BASE) + SZ_4K - 1,\
42 .flags = IORESOURCE_MEM, \
43 }, \
44 .dma_mask = ~0, \
45 .irq = base##_IRQ, \
46 /* .dma = base##_DMA,*/ \
47}
48
49/*
50 * These devices are connected via the core APB bridge
51 */
52#define GPIO2_IRQ { IRQ_GPIOINT2, NO_IRQ }
53#define GPIO2_DMA { 0, 0 }
54#define GPIO3_IRQ { IRQ_GPIOINT3, NO_IRQ }
55#define GPIO3_DMA { 0, 0 }
56
57#define AACI_IRQ { IRQ_AACI, NO_IRQ }
58#define AACI_DMA { 0x80, 0x81 }
59#define MMCI0_IRQ { IRQ_MMCI0A,IRQ_MMCI0B }
60#define MMCI0_DMA { 0x84, 0 }
61#define KMI0_IRQ { IRQ_KMI0, NO_IRQ }
62#define KMI0_DMA { 0, 0 }
63#define KMI1_IRQ { IRQ_KMI1, NO_IRQ }
64#define KMI1_DMA { 0, 0 }
65
66/*
67 * These devices are connected directly to the multi-layer AHB switch
68 */
69#define SMC_IRQ { NO_IRQ, NO_IRQ }
70#define SMC_DMA { 0, 0 }
71#define MPMC_IRQ { NO_IRQ, NO_IRQ }
72#define MPMC_DMA { 0, 0 }
73#define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ }
74#define CLCD_DMA { 0, 0 }
75#define DMAC_IRQ { IRQ_DMAINT, NO_IRQ }
76#define DMAC_DMA { 0, 0 }
77
78/*
79 * These devices are connected via the core APB bridge
80 */
81#define SCTL_IRQ { NO_IRQ, NO_IRQ }
82#define SCTL_DMA { 0, 0 }
83#define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ }
84#define WATCHDOG_DMA { 0, 0 }
85#define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ }
86#define GPIO0_DMA { 0, 0 }
87#define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ }
88#define GPIO1_DMA { 0, 0 }
89#define RTC_IRQ { IRQ_RTCINT, NO_IRQ }
90#define RTC_DMA { 0, 0 }
91
92/*
93 * These devices are connected via the DMA APB bridge
94 */
95#define SCI_IRQ { IRQ_SCIINT, NO_IRQ }
96#define SCI_DMA { 7, 6 }
97#define UART0_IRQ { IRQ_UARTINT0, NO_IRQ }
98#define UART0_DMA { 15, 14 }
99#define UART1_IRQ { IRQ_UARTINT1, NO_IRQ }
100#define UART1_DMA { 13, 12 }
101#define UART2_IRQ { IRQ_UARTINT2, NO_IRQ }
102#define UART2_DMA { 11, 10 }
103#define UART3_IRQ { IRQ_UART3, NO_IRQ }
104#define UART3_DMA { 0x86, 0x87 }
105#define SSP_IRQ { IRQ_SSPINT, NO_IRQ }
106#define SSP_DMA { 9, 8 }
107
108
109extern struct platform_device realview_flash_device;
110extern struct platform_device realview_smc91x_device;
111extern struct mmc_platform_data realview_mmc0_plat_data;
112extern struct mmc_platform_data realview_mmc1_plat_data;
113extern struct clk realview_clcd_clk;
114extern struct clcd_board clcd_plat_data;
115
116extern void realview_leds_event(led_event_t ledevt);
117
118#endif
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
new file mode 100644
index 000000000000..01b264be5029
--- /dev/null
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -0,0 +1,142 @@
1/*
2 * linux/arch/arm/mach-realview/realview_eb.c
3 *
4 * Copyright (C) 2004 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/config.h>
23#include <linux/init.h>
24#include <linux/platform_device.h>
25#include <linux/sysdev.h>
26
27#include <asm/hardware.h>
28#include <asm/io.h>
29#include <asm/irq.h>
30#include <asm/leds.h>
31#include <asm/mach-types.h>
32#include <asm/hardware/gic.h>
33#include <asm/hardware/amba.h>
34#include <asm/hardware/icst307.h>
35
36#include <asm/mach/arch.h>
37#include <asm/mach/map.h>
38#include <asm/mach/mmc.h>
39
40#include <asm/arch/irqs.h>
41
42#include "core.h"
43#include "clock.h"
44
45static struct map_desc realview_eb_io_desc[] __initdata = {
46 { IO_ADDRESS(REALVIEW_SYS_BASE), REALVIEW_SYS_BASE, SZ_4K, MT_DEVICE },
47 { IO_ADDRESS(REALVIEW_GIC_CPU_BASE), REALVIEW_GIC_CPU_BASE, SZ_4K, MT_DEVICE },
48 { IO_ADDRESS(REALVIEW_GIC_DIST_BASE), REALVIEW_GIC_DIST_BASE, SZ_4K, MT_DEVICE },
49 { IO_ADDRESS(REALVIEW_SCTL_BASE), REALVIEW_SCTL_BASE, SZ_4K, MT_DEVICE },
50 { IO_ADDRESS(REALVIEW_TIMER0_1_BASE), REALVIEW_TIMER0_1_BASE, SZ_4K, MT_DEVICE },
51 { IO_ADDRESS(REALVIEW_TIMER2_3_BASE), REALVIEW_TIMER2_3_BASE, SZ_4K, MT_DEVICE },
52#ifdef CONFIG_DEBUG_LL
53 { IO_ADDRESS(REALVIEW_UART0_BASE), REALVIEW_UART0_BASE, SZ_4K, MT_DEVICE },
54#endif
55};
56
57static void __init realview_eb_map_io(void)
58{
59 iotable_init(realview_eb_io_desc, ARRAY_SIZE(realview_eb_io_desc));
60}
61
62/* FPGA Primecells */
63AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
64AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &realview_mmc0_plat_data);
65AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL);
66AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
67AMBA_DEVICE(uart3, "fpga:09", UART3, NULL);
68
69/* DevChip Primecells */
70AMBA_DEVICE(smc, "dev:00", SMC, NULL);
71AMBA_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
72AMBA_DEVICE(dmac, "dev:30", DMAC, NULL);
73AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL);
74AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
75AMBA_DEVICE(gpio0, "dev:e4", GPIO0, NULL);
76AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL);
77AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL);
78AMBA_DEVICE(rtc, "dev:e8", RTC, NULL);
79AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
80AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
81AMBA_DEVICE(uart1, "dev:f2", UART1, NULL);
82AMBA_DEVICE(uart2, "dev:f3", UART2, NULL);
83AMBA_DEVICE(ssp0, "dev:f4", SSP, NULL);
84
85static struct amba_device *amba_devs[] __initdata = {
86 &dmac_device,
87 &uart0_device,
88 &uart1_device,
89 &uart2_device,
90 &uart3_device,
91 &smc_device,
92 &clcd_device,
93 &sctl_device,
94 &wdog_device,
95 &gpio0_device,
96 &gpio1_device,
97 &gpio2_device,
98 &rtc_device,
99 &sci0_device,
100 &ssp0_device,
101 &aaci_device,
102 &mmc0_device,
103 &kmi0_device,
104 &kmi1_device,
105};
106
107static void __init gic_init_irq(void)
108{
109 gic_dist_init(__io_address(REALVIEW_GIC_DIST_BASE));
110 gic_cpu_init(__io_address(REALVIEW_GIC_CPU_BASE));
111}
112
113static void __init realview_eb_init(void)
114{
115 int i;
116
117 clk_register(&realview_clcd_clk);
118
119 platform_device_register(&realview_flash_device);
120 platform_device_register(&realview_smc91x_device);
121
122 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
123 struct amba_device *d = amba_devs[i];
124 amba_device_register(d, &iomem_resource);
125 }
126
127#ifdef CONFIG_LEDS
128 leds_event = realview_leds_event;
129#endif
130}
131
132MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
133 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
134 .phys_ram = 0x00000000,
135 .phys_io = REALVIEW_UART0_BASE,
136 .io_pg_offst = (IO_ADDRESS(REALVIEW_UART0_BASE) >> 18) & 0xfffc,
137 .boot_params = 0x00000100,
138 .map_io = realview_eb_map_io,
139 .init_irq = gic_init_irq,
140 .timer = &realview_timer,
141 .init_machine = realview_eb_init,
142MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-rx3715.c b/arch/arm/mach-s3c2410/mach-rx3715.c
index 8f2a90bf940b..24d69019a843 100644
--- a/arch/arm/mach-s3c2410/mach-rx3715.c
+++ b/arch/arm/mach-s3c2410/mach-rx3715.c
@@ -17,6 +17,7 @@
17 * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA 17 * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
18 * 14-Mar-2005 BJD Fixed __iomem warnings 18 * 14-Mar-2005 BJD Fixed __iomem warnings
19 * 20-Sep-2005 BJD Added static to non-exported items 19 * 20-Sep-2005 BJD Added static to non-exported items
20 * 31-Oct-2005 BJD Added LCD setup for framebuffer
20*/ 21*/
21 22
22#include <linux/kernel.h> 23#include <linux/kernel.h>
@@ -43,6 +44,9 @@
43 44
44#include <asm/arch/regs-serial.h> 45#include <asm/arch/regs-serial.h>
45#include <asm/arch/regs-gpio.h> 46#include <asm/arch/regs-gpio.h>
47#include <asm/arch/regs-lcd.h>
48
49#include <asm/arch/fb.h>
46 50
47#include "clock.h" 51#include "clock.h"
48#include "devs.h" 52#include "devs.h"
@@ -97,6 +101,66 @@ static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
97 } 101 }
98}; 102};
99 103
104/* framebuffer lcd controller information */
105
106static struct s3c2410fb_mach_info rx3715_lcdcfg __initdata = {
107 .regs = {
108 .lcdcon1 = S3C2410_LCDCON1_TFT16BPP | \
109 S3C2410_LCDCON1_TFT | \
110 S3C2410_LCDCON1_CLKVAL(0x0C),
111
112 .lcdcon2 = S3C2410_LCDCON2_VBPD(5) | \
113 S3C2410_LCDCON2_LINEVAL(319) | \
114 S3C2410_LCDCON2_VFPD(6) | \
115 S3C2410_LCDCON2_VSPW(2),
116
117 .lcdcon3 = S3C2410_LCDCON3_HBPD(35) | \
118 S3C2410_LCDCON3_HOZVAL(239) | \
119 S3C2410_LCDCON3_HFPD(35),
120
121 .lcdcon4 = S3C2410_LCDCON4_MVAL(0) | \
122 S3C2410_LCDCON4_HSPW(7),
123
124 .lcdcon5 = S3C2410_LCDCON5_INVVLINE |
125 S3C2410_LCDCON5_FRM565 |
126 S3C2410_LCDCON5_HWSWP,
127 },
128
129 .lpcsel = 0xf82,
130
131 .gpccon = 0xaa955699,
132 .gpccon_mask = 0xffc003cc,
133 .gpcup = 0x0000ffff,
134 .gpcup_mask = 0xffffffff,
135
136 .gpdcon = 0xaa95aaa1,
137 .gpdcon_mask = 0xffc0fff0,
138 .gpdup = 0x0000faff,
139 .gpdup_mask = 0xffffffff,
140
141 .fixed_syncs = 1,
142 .width = 240,
143 .height = 320,
144
145 .xres = {
146 .min = 240,
147 .max = 240,
148 .defval = 240,
149 },
150
151 .yres = {
152 .max = 320,
153 .min = 320,
154 .defval = 320,
155 },
156
157 .bpp = {
158 .min = 16,
159 .max = 16,
160 .defval = 16,
161 },
162};
163
100static struct platform_device *rx3715_devices[] __initdata = { 164static struct platform_device *rx3715_devices[] __initdata = {
101 &s3c_device_usb, 165 &s3c_device_usb,
102 &s3c_device_lcd, 166 &s3c_device_lcd,
@@ -123,14 +187,12 @@ static void __init rx3715_init_irq(void)
123 s3c24xx_init_irq(); 187 s3c24xx_init_irq();
124} 188}
125 189
126#ifdef CONFIG_PM
127static void __init rx3715_init_machine(void) 190static void __init rx3715_init_machine(void)
128{ 191{
129 s3c2410_pm_init(); 192 s3c2410_pm_init();
193 s3c24xx_fb_set_platdata(&rx3715_lcdcfg);
130} 194}
131#else 195
132#define rx3715_init_machine NULL
133#endif
134 196
135MACHINE_START(RX3715, "IPAQ-RX3715") 197MACHINE_START(RX3715, "IPAQ-RX3715")
136 /* Maintainer: Ben Dooks <ben@fluff.org> */ 198 /* Maintainer: Ben Dooks <ben@fluff.org> */
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index c54e04c995ee..5568403e984d 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -120,8 +120,8 @@ config CPU_ARM925T
120 120
121# ARM926T 121# ARM926T
122config CPU_ARM926T 122config CPU_ARM926T
123 bool "Support ARM926T processor" if ARCH_INTEGRATOR 123 bool "Support ARM926T processor"
124 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX 124 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB
125 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX 125 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX
126 select CPU_32v5 126 select CPU_32v5
127 select CPU_ABRT_EV5TJ 127 select CPU_ABRT_EV5TJ
@@ -242,7 +242,7 @@ config CPU_XSCALE
242# ARMv6 242# ARMv6
243config CPU_V6 243config CPU_V6
244 bool "Support ARM V6 processor" 244 bool "Support ARM V6 processor"
245 depends on ARCH_INTEGRATOR 245 depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB
246 select CPU_32v6 246 select CPU_32v6
247 select CPU_ABRT_EV6 247 select CPU_ABRT_EV6
248 select CPU_CACHE_V6 248 select CPU_CACHE_V6
diff --git a/drivers/i2c/busses/i2c-iop3xx.c b/drivers/i2c/busses/i2c-iop3xx.c
index 13752bcb2afd..cfae4ad00fae 100644
--- a/drivers/i2c/busses/i2c-iop3xx.c
+++ b/drivers/i2c/busses/i2c-iop3xx.c
@@ -11,7 +11,7 @@
11 * 11 *
12 * Copyright (C) 1995-1997 Simon G. Vogl, 1998-2000 Hans Berglund 12 * Copyright (C) 1995-1997 Simon G. Vogl, 1998-2000 Hans Berglund
13 * 13 *
14 * And which acknowledged Kyösti Mälkki <kmalkki@cc.hut.fi>, 14 * And which acknowledged Kyösti Mälkki <kmalkki@cc.hut.fi>,
15 * Frodo Looijaard <frodol@dds.nl>, Martin Bailey<mbailey@littlefeet-inc.com> 15 * Frodo Looijaard <frodol@dds.nl>, Martin Bailey<mbailey@littlefeet-inc.com>
16 * 16 *
17 * Major cleanup by Deepak Saxena <dsaxena@plexity.net>, 01/2005: 17 * Major cleanup by Deepak Saxena <dsaxena@plexity.net>, 01/2005:
@@ -184,7 +184,7 @@ iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap,
184 do { 184 do {
185 interrupted = wait_event_interruptible_timeout ( 185 interrupted = wait_event_interruptible_timeout (
186 iop3xx_adap->waitq, 186 iop3xx_adap->waitq,
187 (done = compare( sr = iop3xx_i2c_get_srstat(iop3xx_adap) ,flags )), 187 (done = compare( sr = iop3xx_i2c_get_srstat(iop3xx_adap) ,flags )),
188 1 * HZ; 188 1 * HZ;
189 ); 189 );
190 if ((rc = iop3xx_i2c_error(sr)) < 0) { 190 if ((rc = iop3xx_i2c_error(sr)) < 0) {
@@ -472,9 +472,10 @@ iop3xx_i2c_probe(struct device *dev)
472 goto release_region; 472 goto release_region;
473 } 473 }
474 474
475 res = request_irq(platform_get_irq(pdev, 0), iop3xx_i2c_irq_handler, 0, 475 ret = request_irq(platform_get_irq(pdev, 0), iop3xx_i2c_irq_handler, 0,
476 pdev->name, adapter_data); 476 pdev->name, adapter_data);
477 if (res) { 477
478 if (ret) {
478 ret = -EIO; 479 ret = -EIO;
479 goto unmap; 480 goto unmap;
480 } 481 }
diff --git a/drivers/net/arm/am79c961a.c b/drivers/net/arm/am79c961a.c
index 3d50e953faaa..877891a29aaa 100644
--- a/drivers/net/arm/am79c961a.c
+++ b/drivers/net/arm/am79c961a.c
@@ -26,11 +26,11 @@
26#include <linux/init.h> 26#include <linux/init.h>
27#include <linux/crc32.h> 27#include <linux/crc32.h>
28#include <linux/bitops.h> 28#include <linux/bitops.h>
29#include <linux/platform_device.h>
29 30
30#include <asm/system.h>
31#include <asm/irq.h>
32#include <asm/hardware.h> 31#include <asm/hardware.h>
33#include <asm/io.h> 32#include <asm/io.h>
33#include <asm/system.h>
34 34
35#define TX_BUFFERS 15 35#define TX_BUFFERS 15
36#define RX_BUFFERS 25 36#define RX_BUFFERS 25
@@ -280,10 +280,13 @@ static void am79c961_timer(unsigned long data)
280 lnkstat = read_ireg(dev->base_addr, ISALED0) & ISALED0_LNKST; 280 lnkstat = read_ireg(dev->base_addr, ISALED0) & ISALED0_LNKST;
281 carrier = netif_carrier_ok(dev); 281 carrier = netif_carrier_ok(dev);
282 282
283 if (lnkstat && !carrier) 283 if (lnkstat && !carrier) {
284 netif_carrier_on(dev); 284 netif_carrier_on(dev);
285 else if (!lnkstat && carrier) 285 printk("%s: link up\n", dev->name);
286 } else if (!lnkstat && carrier) {
286 netif_carrier_off(dev); 287 netif_carrier_off(dev);
288 printk("%s: link down\n", dev->name);
289 }
287 290
288 mod_timer(&priv->timer, jiffies + msecs_to_jiffies(500)); 291 mod_timer(&priv->timer, jiffies + msecs_to_jiffies(500));
289} 292}
@@ -665,17 +668,25 @@ static void __init am79c961_banner(void)
665 printk(KERN_INFO "%s", version); 668 printk(KERN_INFO "%s", version);
666} 669}
667 670
668static int __init am79c961_init(void) 671static int __init am79c961_probe(struct device *_dev)
669{ 672{
673 struct platform_device *pdev = to_platform_device(_dev);
674 struct resource *res;
670 struct net_device *dev; 675 struct net_device *dev;
671 struct dev_priv *priv; 676 struct dev_priv *priv;
672 int i, ret; 677 int i, ret;
673 678
679 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
680 if (!res)
681 return -ENODEV;
682
674 dev = alloc_etherdev(sizeof(struct dev_priv)); 683 dev = alloc_etherdev(sizeof(struct dev_priv));
675 ret = -ENOMEM; 684 ret = -ENOMEM;
676 if (!dev) 685 if (!dev)
677 goto out; 686 goto out;
678 687
688 SET_NETDEV_DEV(dev, &pdev->dev);
689
679 priv = netdev_priv(dev); 690 priv = netdev_priv(dev);
680 691
681 /* 692 /*
@@ -683,8 +694,8 @@ static int __init am79c961_init(void)
683 * The PNP initialisation should have been 694 * The PNP initialisation should have been
684 * done by the ether bootp loader. 695 * done by the ether bootp loader.
685 */ 696 */
686 dev->base_addr = 0x220; 697 dev->base_addr = res->start;
687 dev->irq = IRQ_EBSA110_ETHERNET; 698 dev->irq = platform_get_irq(pdev, 0);
688 699
689 ret = -ENODEV; 700 ret = -ENODEV;
690 if (!request_region(dev->base_addr, 0x18, dev->name)) 701 if (!request_region(dev->base_addr, 0x18, dev->name))
@@ -705,11 +716,11 @@ static int __init am79c961_init(void)
705 inb(dev->base_addr + 4) != 0x2b) 716 inb(dev->base_addr + 4) != 0x2b)
706 goto release; 717 goto release;
707 718
708 am79c961_banner();
709
710 for (i = 0; i < 6; i++) 719 for (i = 0; i < 6; i++)
711 dev->dev_addr[i] = inb(dev->base_addr + i * 2) & 0xff; 720 dev->dev_addr[i] = inb(dev->base_addr + i * 2) & 0xff;
712 721
722 am79c961_banner();
723
713 spin_lock_init(&priv->chip_lock); 724 spin_lock_init(&priv->chip_lock);
714 init_timer(&priv->timer); 725 init_timer(&priv->timer);
715 priv->timer.data = (unsigned long)dev; 726 priv->timer.data = (unsigned long)dev;
@@ -732,6 +743,7 @@ static int __init am79c961_init(void)
732 if (ret == 0) { 743 if (ret == 0) {
733 printk(KERN_INFO "%s: ether address ", dev->name); 744 printk(KERN_INFO "%s: ether address ", dev->name);
734 745
746 /* Retrive and print the ethernet address. */
735 for (i = 0; i < 6; i++) 747 for (i = 0; i < 6; i++)
736 printk (i == 5 ? "%02x\n" : "%02x:", dev->dev_addr[i]); 748 printk (i == 5 ? "%02x\n" : "%02x:", dev->dev_addr[i]);
737 749
@@ -746,4 +758,15 @@ out:
746 return ret; 758 return ret;
747} 759}
748 760
761static struct device_driver am79c961_driver = {
762 .name = "am79c961",
763 .bus = &platform_bus_type,
764 .probe = am79c961_probe,
765};
766
767static int __init am79c961_init(void)
768{
769 return driver_register(&am79c961_driver);
770}
771
749__initcall(am79c961_init); 772__initcall(am79c961_init);
diff --git a/drivers/net/arm/am79c961a.h b/drivers/net/arm/am79c961a.h
index 1e9b05050cbe..6a49ac7f6d46 100644
--- a/drivers/net/arm/am79c961a.h
+++ b/drivers/net/arm/am79c961a.h
@@ -143,6 +143,4 @@ struct dev_priv {
143 struct timer_list timer; 143 struct timer_list timer;
144}; 144};
145 145
146extern int am79c961_probe (struct net_device *dev);
147
148#endif 146#endif
diff --git a/include/asm-arm/arch-ixp2000/enp2611.h b/include/asm-arm/arch-ixp2000/enp2611.h
index 31ae88674968..95128d9f5026 100644
--- a/include/asm-arm/arch-ixp2000/enp2611.h
+++ b/include/asm-arm/arch-ixp2000/enp2611.h
@@ -21,8 +21,20 @@
21#ifndef __ENP2611_H 21#ifndef __ENP2611_H
22#define __ENP2611_H 22#define __ENP2611_H
23 23
24#define ENP2611_GPIO_SCL 0x07 24#define ENP2611_CALEB_PHYS_BASE 0xc5000000
25#define ENP2611_GPIO_SDA 0x06 25#define ENP2611_CALEB_VIRT_BASE 0xfe000000
26#define ENP2611_CALEB_SIZE 0x00100000
27
28#define ENP2611_PM3386_0_PHYS_BASE 0xc6000000
29#define ENP2611_PM3386_0_VIRT_BASE 0xfe100000
30#define ENP2611_PM3386_0_SIZE 0x00100000
31
32#define ENP2611_PM3386_1_PHYS_BASE 0xc6400000
33#define ENP2611_PM3386_1_VIRT_BASE 0xfe200000
34#define ENP2611_PM3386_1_SIZE 0x00100000
35
36#define ENP2611_GPIO_SCL 7
37#define ENP2611_GPIO_SDA 6
26 38
27 39
28#endif 40#endif
diff --git a/include/asm-arm/arch-ixp2000/ixp2000-regs.h b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
index def089d693d2..fc5ac6aec4f2 100644
--- a/include/asm-arm/arch-ixp2000/ixp2000-regs.h
+++ b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
@@ -59,14 +59,15 @@
59#define IXP2000_CAP_SIZE 0x00100000 59#define IXP2000_CAP_SIZE 0x00100000
60 60
61/* 61/*
62 * Addresses for specific on-chip peripherals 62 * Addresses for specific on-chip peripherals.
63 */ 63 */
64#define IXP2000_SLOWPORT_CSR_VIRT_BASE 0xfef80000 64#define IXP2000_SLOWPORT_CSR_VIRT_BASE 0xfef80000
65#define IXP2000_GLOBAL_REG_VIRT_BASE 0xfef04000 65#define IXP2000_GLOBAL_REG_VIRT_BASE 0xfef04000
66#define IXP2000_UART_PHYS_BASE 0xc0030000 66#define IXP2000_UART_PHYS_BASE 0xc0030000
67#define IXP2000_UART_VIRT_BASE 0xfef30000 67#define IXP2000_UART_VIRT_BASE 0xfef30000
68#define IXP2000_TIMER_VIRT_BASE 0xfef20000 68#define IXP2000_TIMER_VIRT_BASE 0xfef20000
69#define IXP2000_GPIO_VIRT_BASE 0Xfef10000 69#define IXP2000_UENGINE_CSR_VIRT_BASE 0xfef18000
70#define IXP2000_GPIO_VIRT_BASE 0xfef10000
70 71
71/* 72/*
72 * Devices outside of the 0xc0000000 -> 0xc0100000 range. The virtual 73 * Devices outside of the 0xc0000000 -> 0xc0100000 range. The virtual
@@ -252,7 +253,7 @@
252#define IXP2000_PCI_XSCALE_INT_ENABLE IXP2000_PCI_CSR(0x15C) 253#define IXP2000_PCI_XSCALE_INT_ENABLE IXP2000_PCI_CSR(0x15C)
253 254
254#define IXP2000_PCICNTL_PNR (1<<17) /* PCI not Reset bit of PCI_CONTROL */ 255#define IXP2000_PCICNTL_PNR (1<<17) /* PCI not Reset bit of PCI_CONTROL */
255#define IXP2000_PCICNTL_PCF (1<<28) /* PCI Centrolfunction bit */ 256#define IXP2000_PCICNTL_PCF (1<<28) /* PCI Central function bit */
256#define IXP2000_XSCALE_INT (1<<1) /* Interrupt from XScale to PCI */ 257#define IXP2000_XSCALE_INT (1<<1) /* Interrupt from XScale to PCI */
257 258
258/* These are from the IRQ register in the PCI ISR register */ 259/* These are from the IRQ register in the PCI ISR register */
diff --git a/include/asm-arm/arch-ixp2000/system.h b/include/asm-arm/arch-ixp2000/system.h
index 4f489cc0dfa5..ddbbb34b5f95 100644
--- a/include/asm-arm/arch-ixp2000/system.h
+++ b/include/asm-arm/arch-ixp2000/system.h
@@ -26,29 +26,24 @@ static inline void arch_reset(char mode)
26 * RedBoot bank. 26 * RedBoot bank.
27 */ 27 */
28 if (machine_is_ixdp2401()) { 28 if (machine_is_ixdp2401()) {
29 *IXDP2X01_CPLD_FLASH_REG = ((0 >> IXDP2X01_FLASH_WINDOW_BITS) 29 ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG,
30 | IXDP2X01_CPLD_FLASH_INTERN); 30 ((0 >> IXDP2X01_FLASH_WINDOW_BITS)
31 *IXDP2X01_CPLD_RESET_REG = 0xffffffff; 31 | IXDP2X01_CPLD_FLASH_INTERN));
32 ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0xffffffff);
32 } 33 }
33 34
34 /* 35 /*
35 * On IXDP2801 we need to write this magic sequence to the CPLD 36 * On IXDP2801 we need to write this magic sequence to the CPLD
36 * to cause a complete reset of the CPU and all external devices 37 * to cause a complete reset of the CPU and all external devices
37 * and moves the flash bank register back to 0. 38 * and move the flash bank register back to 0.
38 */ 39 */
39 if (machine_is_ixdp2801()) { 40 if (machine_is_ixdp2801()) {
40 unsigned long reset_reg = *IXDP2X01_CPLD_RESET_REG; 41 unsigned long reset_reg = *IXDP2X01_CPLD_RESET_REG;
42
41 reset_reg = 0x55AA0000 | (reset_reg & 0x0000FFFF); 43 reset_reg = 0x55AA0000 | (reset_reg & 0x0000FFFF);
42 *IXDP2X01_CPLD_RESET_REG = reset_reg; 44 ixp2000_reg_write(IXDP2X01_CPLD_RESET_REG, reset_reg);
43 mb(); 45 ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0x80000000);
44 *IXDP2X01_CPLD_RESET_REG = 0x80000000;
45 } 46 }
46 47
47 /* 48 ixp2000_reg_wrb(IXP2000_RESET0, RSTALL);
48 * We do a reset all if we are PCI master. We could be a slave and we
49 * don't want to do anything funky on the PCI bus.
50 */
51 if (*IXP2000_STRAP_OPTIONS & CFG_PCI_BOOT_HOST) {
52 *(IXP2000_RESET0) |= (RSTALL);
53 }
54} 49}
diff --git a/include/asm-arm/arch-ixp2000/uengine.h b/include/asm-arm/arch-ixp2000/uengine.h
new file mode 100644
index 000000000000..b442d65c6593
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/uengine.h
@@ -0,0 +1,62 @@
1/*
2 * Generic library functions for the microengines found on the Intel
3 * IXP2000 series of network processors.
4 *
5 * Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org>
6 * Dedicated to Marija Kulikova.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU Lesser General Public License as
10 * published by the Free Software Foundation; either version 2.1 of the
11 * License, or (at your option) any later version.
12 */
13
14#ifndef __IXP2000_UENGINE_H
15#define __IXP2000_UENGINE_H
16
17extern u32 ixp2000_uengine_mask;
18
19struct ixp2000_uengine_code
20{
21 u32 cpu_model_bitmask;
22 u8 cpu_min_revision;
23 u8 cpu_max_revision;
24
25 u32 uengine_parameters;
26
27 struct ixp2000_reg_value {
28 int reg;
29 u32 value;
30 } *initial_reg_values;
31
32 int num_insns;
33 u8 *insns;
34};
35
36u32 ixp2000_uengine_csr_read(int uengine, int offset);
37void ixp2000_uengine_csr_write(int uengine, int offset, u32 value);
38void ixp2000_uengine_reset(u32 uengine_mask);
39void ixp2000_uengine_set_mode(int uengine, u32 mode);
40void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns);
41void ixp2000_uengine_init_context(int uengine, int context, int pc);
42void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask);
43void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask);
44int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c);
45
46#define IXP2000_UENGINE_8_CONTEXTS 0x00000000
47#define IXP2000_UENGINE_4_CONTEXTS 0x80000000
48#define IXP2000_UENGINE_PRN_UPDATE_EVERY 0x40000000
49#define IXP2000_UENGINE_PRN_UPDATE_ON_ACCESS 0x00000000
50#define IXP2000_UENGINE_NN_FROM_SELF 0x00100000
51#define IXP2000_UENGINE_NN_FROM_PREVIOUS 0x00000000
52#define IXP2000_UENGINE_ASSERT_EMPTY_AT_3 0x000c0000
53#define IXP2000_UENGINE_ASSERT_EMPTY_AT_2 0x00080000
54#define IXP2000_UENGINE_ASSERT_EMPTY_AT_1 0x00040000
55#define IXP2000_UENGINE_ASSERT_EMPTY_AT_0 0x00000000
56#define IXP2000_UENGINE_LM_ADDR1_GLOBAL 0x00020000
57#define IXP2000_UENGINE_LM_ADDR1_PER_CONTEXT 0x00000000
58#define IXP2000_UENGINE_LM_ADDR0_GLOBAL 0x00010000
59#define IXP2000_UENGINE_LM_ADDR0_PER_CONTEXT 0x00000000
60
61
62#endif
diff --git a/include/asm-arm/arch-realview/debug-macro.S b/include/asm-arm/arch-realview/debug-macro.S
new file mode 100644
index 000000000000..ed28bd012236
--- /dev/null
+++ b/include/asm-arm/arch-realview/debug-macro.S
@@ -0,0 +1,38 @@
1/* linux/include/asm-arm/arch-realview/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#include <asm/hardware/amba_serial.h>
15
16 .macro addruart,rx
17 mrc p15, 0, \rx, c1, c0
18 tst \rx, #1 @ MMU enabled?
19 moveq \rx, #0x10000000
20 movne \rx, #0xf1000000 @ virtual base
21 orr \rx, \rx, #0x00009000
22 .endm
23
24 .macro senduart,rd,rx
25 strb \rd, [\rx, #UART01x_DR]
26 .endm
27
28 .macro waituart,rd,rx
291001: ldr \rd, [\rx, #0x18] @ UARTFLG
30 tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full
31 bne 1001b
32 .endm
33
34 .macro busyuart,rd,rx
351001: ldr \rd, [\rx, #0x18] @ UARTFLG
36 tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy
37 bne 1001b
38 .endm
diff --git a/include/asm-arm/arch-realview/dma.h b/include/asm-arm/arch-realview/dma.h
new file mode 100644
index 000000000000..744491a74bd9
--- /dev/null
+++ b/include/asm-arm/arch-realview/dma.h
@@ -0,0 +1,27 @@
1/*
2 * linux/include/asm-arm/arch-realview/dma.h
3 *
4 * Copyright (C) 2003 ARM Limited.
5 * Copyright (C) 1997,1998 Russell King
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef __ASM_ARCH_DMA_H
22#define __ASM_ARCH_DMA_H
23
24#define MAX_DMA_ADDRESS 0xffffffff
25#define MAX_DMA_CHANNELS 0
26
27#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-realview/entry-macro.S b/include/asm-arm/arch-realview/entry-macro.S
new file mode 100644
index 000000000000..2712ba77bb3a
--- /dev/null
+++ b/include/asm-arm/arch-realview/entry-macro.S
@@ -0,0 +1,49 @@
1/*
2 * include/asm-arm/arch-realview/entry-macro.S
3 *
4 * Low-level IRQ helper macros for RealView platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <asm/hardware/gic.h>
12
13 .macro disable_fiq
14 .endm
15
16 /*
17 * The interrupt numbering scheme is defined in the
18 * interrupt controller spec. To wit:
19 *
20 * Interrupts 0-15 are IPI
21 * 16-28 are reserved
22 * 29-31 are local. We allow 30 to be used for the watchdog.
23 * 32-1020 are global
24 * 1021-1022 are reserved
25 * 1023 is "spurious" (no interrupt)
26 *
27 * For now, we ignore all local interrupts so only return an interrupt if it's
28 * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
29 *
30 * A simple read from the controller will tell us the number of the highest
31 * priority enabled interrupt. We then just need to check whether it is in the
32 * valid range for an IRQ (30-1020 inclusive).
33 */
34
35 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
36
37 ldr \base, =IO_ADDRESS(REALVIEW_GIC_CPU_BASE)
38 ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
39
40 ldr \tmp, =1021
41
42 bic \irqnr, \irqstat, #0x1c00
43
44 cmp \irqnr, #29
45 cmpcc \irqnr, \irqnr
46 cmpne \irqnr, \tmp
47 cmpcs \irqnr, \irqnr
48
49 .endm
diff --git a/include/asm-arm/arch-realview/hardware.h b/include/asm-arm/arch-realview/hardware.h
new file mode 100644
index 000000000000..67879cdb6ef2
--- /dev/null
+++ b/include/asm-arm/arch-realview/hardware.h
@@ -0,0 +1,31 @@
1/*
2 * linux/include/asm-arm/arch-realview/hardware.h
3 *
4 * This file contains the hardware definitions of the RealView boards.
5 *
6 * Copyright (C) 2003 ARM Limited.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22#ifndef __ASM_ARCH_HARDWARE_H
23#define __ASM_ARCH_HARDWARE_H
24
25#include <asm/sizes.h>
26#include <asm/arch/platform.h>
27
28/* macro to get at IO space when running virtually */
29#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
30
31#endif
diff --git a/include/asm-arm/arch-realview/io.h b/include/asm-arm/arch-realview/io.h
new file mode 100644
index 000000000000..d444a68ac330
--- /dev/null
+++ b/include/asm-arm/arch-realview/io.h
@@ -0,0 +1,34 @@
1/*
2 * linux/include/asm-arm/arch-realview/io.h
3 *
4 * Copyright (C) 2003 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __ASM_ARM_ARCH_IO_H
21#define __ASM_ARM_ARCH_IO_H
22
23#define IO_SPACE_LIMIT 0xffffffff
24
25static inline void __iomem *__io(unsigned long addr)
26{
27 return (void __iomem *)addr;
28}
29
30#define __io(a) __io(a)
31#define __mem_pci(a) (a)
32#define __mem_isa(a) (a)
33
34#endif
diff --git a/include/asm-arm/arch-realview/irqs.h b/include/asm-arm/arch-realview/irqs.h
new file mode 100644
index 000000000000..ff376494e5b1
--- /dev/null
+++ b/include/asm-arm/arch-realview/irqs.h
@@ -0,0 +1,103 @@
1/*
2 * linux/include/asm-arm/arch-realview/irqs.h
3 *
4 * Copyright (C) 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <asm/arch/platform.h>
23
24/*
25 * IRQ interrupts definitions are the same the INT definitions
26 * held within platform.h
27 */
28#define IRQ_GIC_START 32
29#define IRQ_WDOGINT (IRQ_GIC_START + INT_WDOGINT)
30#define IRQ_SOFTINT (IRQ_GIC_START + INT_SOFTINT)
31#define IRQ_COMMRx (IRQ_GIC_START + INT_COMMRx)
32#define IRQ_COMMTx (IRQ_GIC_START + INT_COMMTx)
33#define IRQ_TIMERINT0_1 (IRQ_GIC_START + INT_TIMERINT0_1)
34#define IRQ_TIMERINT2_3 (IRQ_GIC_START + INT_TIMERINT2_3)
35#define IRQ_GPIOINT0 (IRQ_GIC_START + INT_GPIOINT0)
36#define IRQ_GPIOINT1 (IRQ_GIC_START + INT_GPIOINT1)
37#define IRQ_GPIOINT2 (IRQ_GIC_START + INT_GPIOINT2)
38#define IRQ_GPIOINT3 (IRQ_GIC_START + INT_GPIOINT3)
39#define IRQ_RTCINT (IRQ_GIC_START + INT_RTCINT)
40#define IRQ_SSPINT (IRQ_GIC_START + INT_SSPINT)
41#define IRQ_UARTINT0 (IRQ_GIC_START + INT_UARTINT0)
42#define IRQ_UARTINT1 (IRQ_GIC_START + INT_UARTINT1)
43#define IRQ_UARTINT2 (IRQ_GIC_START + INT_UARTINT2)
44#define IRQ_UART3 (IRQ_GIC_START + INT_UARTINT3)
45#define IRQ_SCIINT (IRQ_GIC_START + INT_SCIINT)
46#define IRQ_CLCDINT (IRQ_GIC_START + INT_CLCDINT)
47#define IRQ_DMAINT (IRQ_GIC_START + INT_DMAINT)
48#define IRQ_PWRFAILINT (IRQ_GIC_START + INT_PWRFAILINT)
49#define IRQ_MBXINT (IRQ_GIC_START + INT_MBXINT)
50#define IRQ_GNDINT (IRQ_GIC_START + INT_GNDINT)
51#define IRQ_MMCI0B (IRQ_GIC_START + INT_MMCI0B)
52#define IRQ_MMCI1B (IRQ_GIC_START + INT_MMCI1B)
53#define IRQ_KMI0 (IRQ_GIC_START + INT_KMI0)
54#define IRQ_KMI1 (IRQ_GIC_START + INT_KMI1)
55#define IRQ_SCI3 (IRQ_GIC_START + INT_SCI3)
56#define IRQ_CLCD (IRQ_GIC_START + INT_CLCD)
57#define IRQ_TOUCH (IRQ_GIC_START + INT_TOUCH)
58#define IRQ_KEYPAD (IRQ_GIC_START + INT_KEYPAD)
59#define IRQ_DoC (IRQ_GIC_START + INT_DoC)
60#define IRQ_MMCI0A (IRQ_GIC_START + INT_MMCI0A)
61#define IRQ_MMCI1A (IRQ_GIC_START + INT_MMCI1A)
62#define IRQ_AACI (IRQ_GIC_START + INT_AACI)
63#define IRQ_ETH (IRQ_GIC_START + INT_ETH)
64#define IRQ_USB (IRQ_GIC_START + INT_USB)
65
66#define IRQMASK_WDOGINT INTMASK_WDOGINT
67#define IRQMASK_SOFTINT INTMASK_SOFTINT
68#define IRQMASK_COMMRx INTMASK_COMMRx
69#define IRQMASK_COMMTx INTMASK_COMMTx
70#define IRQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1
71#define IRQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3
72#define IRQMASK_GPIOINT0 INTMASK_GPIOINT0
73#define IRQMASK_GPIOINT1 INTMASK_GPIOINT1
74#define IRQMASK_GPIOINT2 INTMASK_GPIOINT2
75#define IRQMASK_GPIOINT3 INTMASK_GPIOINT3
76#define IRQMASK_RTCINT INTMASK_RTCINT
77#define IRQMASK_SSPINT INTMASK_SSPINT
78#define IRQMASK_UARTINT0 INTMASK_UARTINT0
79#define IRQMASK_UARTINT1 INTMASK_UARTINT1
80#define IRQMASK_UARTINT2 INTMASK_UARTINT2
81#define IRQMASK_SCIINT INTMASK_SCIINT
82#define IRQMASK_CLCDINT INTMASK_CLCDINT
83#define IRQMASK_DMAINT INTMASK_DMAINT
84#define IRQMASK_PWRFAILINT INTMASK_PWRFAILINT
85#define IRQMASK_MBXINT INTMASK_MBXINT
86#define IRQMASK_GNDINT INTMASK_GNDINT
87#define IRQMASK_MMCI0B INTMASK_MMCI0B
88#define IRQMASK_MMCI1B INTMASK_MMCI1B
89#define IRQMASK_KMI0 INTMASK_KMI0
90#define IRQMASK_KMI1 INTMASK_KMI1
91#define IRQMASK_SCI3 INTMASK_SCI3
92#define IRQMASK_UART3 INTMASK_UART3
93#define IRQMASK_CLCD INTMASK_CLCD
94#define IRQMASK_TOUCH INTMASK_TOUCH
95#define IRQMASK_KEYPAD INTMASK_KEYPAD
96#define IRQMASK_DoC INTMASK_DoC
97#define IRQMASK_MMCI0A INTMASK_MMCI0A
98#define IRQMASK_MMCI1A INTMASK_MMCI1A
99#define IRQMASK_AACI INTMASK_AACI
100#define IRQMASK_ETH INTMASK_ETH
101#define IRQMASK_USB INTMASK_USB
102
103#define NR_IRQS (IRQ_GIC_START + 64)
diff --git a/include/asm-arm/arch-realview/memory.h b/include/asm-arm/arch-realview/memory.h
new file mode 100644
index 000000000000..99667d5cc617
--- /dev/null
+++ b/include/asm-arm/arch-realview/memory.h
@@ -0,0 +1,38 @@
1/*
2 * linux/include/asm-arm/arch-realview/memory.h
3 *
4 * Copyright (C) 2003 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __ASM_ARCH_MEMORY_H
21#define __ASM_ARCH_MEMORY_H
22
23/*
24 * Physical DRAM offset.
25 */
26#define PHYS_OFFSET (0x00000000UL)
27
28/*
29 * Virtual view <-> DMA view memory address translations
30 * virt_to_bus: Used to translate the virtual address to an
31 * address suitable to be passed to set_dma_addr
32 * bus_to_virt: Used to convert an address for DMA operations
33 * to an address that the kernel can use.
34 */
35#define __virt_to_bus(x) ((x) - PAGE_OFFSET)
36#define __bus_to_virt(x) ((x) + PAGE_OFFSET)
37
38#endif
diff --git a/include/asm-arm/arch-realview/param.h b/include/asm-arm/arch-realview/param.h
new file mode 100644
index 000000000000..89b1235d32bd
--- /dev/null
+++ b/include/asm-arm/arch-realview/param.h
@@ -0,0 +1,19 @@
1/*
2 * linux/include/asm-arm/arch-realview/param.h
3 *
4 * Copyright (C) 2002 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
diff --git a/include/asm-arm/arch-realview/platform.h b/include/asm-arm/arch-realview/platform.h
new file mode 100644
index 000000000000..4b6de13a6b9a
--- /dev/null
+++ b/include/asm-arm/arch-realview/platform.h
@@ -0,0 +1,395 @@
1/*
2 * linux/include/asm-arm/arch-realview/platform.h
3 *
4 * Copyright (c) ARM Limited 2003. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __address_h
22#define __address_h 1
23
24/*
25 * Memory definitions
26 */
27#define REALVIEW_BOOT_ROM_LO 0x30000000 /* DoC Base (64Mb)...*/
28#define REALVIEW_BOOT_ROM_HI 0x30000000
29#define REALVIEW_BOOT_ROM_BASE REALVIEW_BOOT_ROM_HI /* Normal position */
30#define REALVIEW_BOOT_ROM_SIZE SZ_64M
31
32#define REALVIEW_SSRAM_BASE /* REALVIEW_SSMC_BASE ? */
33#define REALVIEW_SSRAM_SIZE SZ_2M
34
35#define REALVIEW_FLASH_BASE 0x40000000
36#define REALVIEW_FLASH_SIZE SZ_64M
37
38/*
39 * SDRAM
40 */
41#define REALVIEW_SDRAM_BASE 0x00000000
42
43/*
44 * Logic expansion modules
45 *
46 */
47
48
49/* ------------------------------------------------------------------------
50 * RealView Registers
51 * ------------------------------------------------------------------------
52 *
53 */
54#define REALVIEW_SYS_ID_OFFSET 0x00
55#define REALVIEW_SYS_SW_OFFSET 0x04
56#define REALVIEW_SYS_LED_OFFSET 0x08
57#define REALVIEW_SYS_OSC0_OFFSET 0x0C
58
59#define REALVIEW_SYS_OSC1_OFFSET 0x10
60#define REALVIEW_SYS_OSC2_OFFSET 0x14
61#define REALVIEW_SYS_OSC3_OFFSET 0x18
62#define REALVIEW_SYS_OSC4_OFFSET 0x1C /* OSC1 for RealView/AB */
63
64#define REALVIEW_SYS_LOCK_OFFSET 0x20
65#define REALVIEW_SYS_100HZ_OFFSET 0x24
66#define REALVIEW_SYS_CFGDATA1_OFFSET 0x28
67#define REALVIEW_SYS_CFGDATA2_OFFSET 0x2C
68#define REALVIEW_SYS_FLAGS_OFFSET 0x30
69#define REALVIEW_SYS_FLAGSSET_OFFSET 0x30
70#define REALVIEW_SYS_FLAGSCLR_OFFSET 0x34
71#define REALVIEW_SYS_NVFLAGS_OFFSET 0x38
72#define REALVIEW_SYS_NVFLAGSSET_OFFSET 0x38
73#define REALVIEW_SYS_NVFLAGSCLR_OFFSET 0x3C
74#define REALVIEW_SYS_RESETCTL_OFFSET 0x40
75#define REALVIEW_SYS_PCICTL_OFFSET 0x44
76#define REALVIEW_SYS_MCI_OFFSET 0x48
77#define REALVIEW_SYS_FLASH_OFFSET 0x4C
78#define REALVIEW_SYS_CLCD_OFFSET 0x50
79#define REALVIEW_SYS_CLCDSER_OFFSET 0x54
80#define REALVIEW_SYS_BOOTCS_OFFSET 0x58
81#define REALVIEW_SYS_24MHz_OFFSET 0x5C
82#define REALVIEW_SYS_MISC_OFFSET 0x60
83#define REALVIEW_SYS_IOSEL_OFFSET 0x70
84#define REALVIEW_SYS_TEST_OSC0_OFFSET 0x80
85#define REALVIEW_SYS_TEST_OSC1_OFFSET 0x84
86#define REALVIEW_SYS_TEST_OSC2_OFFSET 0x88
87#define REALVIEW_SYS_TEST_OSC3_OFFSET 0x8C
88#define REALVIEW_SYS_TEST_OSC4_OFFSET 0x90
89
90#define REALVIEW_SYS_BASE 0x10000000
91#define REALVIEW_SYS_ID (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET)
92#define REALVIEW_SYS_SW (REALVIEW_SYS_BASE + REALVIEW_SYS_SW_OFFSET)
93#define REALVIEW_SYS_LED (REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET)
94#define REALVIEW_SYS_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC0_OFFSET)
95#define REALVIEW_SYS_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC1_OFFSET)
96
97#define REALVIEW_SYS_LOCK (REALVIEW_SYS_BASE + REALVIEW_SYS_LOCK_OFFSET)
98#define REALVIEW_SYS_100HZ (REALVIEW_SYS_BASE + REALVIEW_SYS_100HZ_OFFSET)
99#define REALVIEW_SYS_CFGDATA1 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA1_OFFSET)
100#define REALVIEW_SYS_CFGDATA2 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA2_OFFSET)
101#define REALVIEW_SYS_FLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGS_OFFSET)
102#define REALVIEW_SYS_FLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSSET_OFFSET)
103#define REALVIEW_SYS_FLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSCLR_OFFSET)
104#define REALVIEW_SYS_NVFLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGS_OFFSET)
105#define REALVIEW_SYS_NVFLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSSET_OFFSET)
106#define REALVIEW_SYS_NVFLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSCLR_OFFSET)
107#define REALVIEW_SYS_RESETCTL (REALVIEW_SYS_BASE + REALVIEW_SYS_RESETCTL_OFFSET)
108#define REALVIEW_SYS_PCICTL (REALVIEW_SYS_BASE + REALVIEW_SYS_PCICTL_OFFSET)
109#define REALVIEW_SYS_MCI (REALVIEW_SYS_BASE + REALVIEW_SYS_MCI_OFFSET)
110#define REALVIEW_SYS_FLASH (REALVIEW_SYS_BASE + REALVIEW_SYS_FLASH_OFFSET)
111#define REALVIEW_SYS_CLCD (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCD_OFFSET)
112#define REALVIEW_SYS_CLCDSER (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCDSER_OFFSET)
113#define REALVIEW_SYS_BOOTCS (REALVIEW_SYS_BASE + REALVIEW_SYS_BOOTCS_OFFSET)
114#define REALVIEW_SYS_24MHz (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET)
115#define REALVIEW_SYS_MISC (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET)
116#define REALVIEW_SYS_IOSEL (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET)
117#define REALVIEW_SYS_TEST_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET)
118#define REALVIEW_SYS_TEST_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET)
119#define REALVIEW_SYS_TEST_OSC2 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET)
120#define REALVIEW_SYS_TEST_OSC3 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC3_OFFSET)
121#define REALVIEW_SYS_TEST_OSC4 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC4_OFFSET)
122
123/*
124 * Values for REALVIEW_SYS_RESET_CTRL
125 */
126#define REALVIEW_SYS_CTRL_RESET_CONFIGCLR 0x01
127#define REALVIEW_SYS_CTRL_RESET_CONFIGINIT 0x02
128#define REALVIEW_SYS_CTRL_RESET_DLLRESET 0x03
129#define REALVIEW_SYS_CTRL_RESET_PLLRESET 0x04
130#define REALVIEW_SYS_CTRL_RESET_POR 0x05
131#define REALVIEW_SYS_CTRL_RESET_DoC 0x06
132
133#define REALVIEW_SYS_CTRL_LED (1 << 0)
134
135
136/* ------------------------------------------------------------------------
137 * RealView control registers
138 * ------------------------------------------------------------------------
139 */
140
141/*
142 * REALVIEW_IDFIELD
143 *
144 * 31:24 = manufacturer (0x41 = ARM)
145 * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus)
146 * 15:12 = FPGA (0x3 = XVC600 or XVC600E)
147 * 11:4 = build value
148 * 3:0 = revision number (0x1 = rev B (AHB))
149 */
150
151/*
152 * REALVIEW_SYS_LOCK
153 * control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL,
154 * SYS_CLD, SYS_BOOTCS
155 */
156#define REALVIEW_SYS_LOCK_LOCKED (1 << 16)
157#define REALVIEW_SYS_LOCKVAL_MASK 0xFFFF /* write 0xA05F to enable write access */
158
159/*
160 * REALVIEW_SYS_FLASH
161 */
162#define REALVIEW_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */
163
164/*
165 * REALVIEW_INTREG
166 * - used to acknowledge and control MMCI and UART interrupts
167 */
168#define REALVIEW_INTREG_WPROT 0x00 /* MMC protection status (no interrupt generated) */
169#define REALVIEW_INTREG_RI0 0x01 /* Ring indicator UART0 is asserted, */
170#define REALVIEW_INTREG_CARDIN 0x08 /* MMCI card in detect */
171 /* write 1 to acknowledge and clear */
172#define REALVIEW_INTREG_RI1 0x02 /* Ring indicator UART1 is asserted, */
173#define REALVIEW_INTREG_CARDINSERT 0x03 /* Signal insertion of MMC card */
174
175/*
176 * REALVIEW peripheral addresses
177 */
178#define REALVIEW_SCTL_BASE 0x10001000 /* System controller */
179#define REALVIEW_I2C_BASE 0x10002000 /* I2C control */
180 /* Reserved 0x10003000 */
181#define REALVIEW_AACI_BASE 0x10004000 /* Audio */
182#define REALVIEW_MMCI0_BASE 0x10005000 /* MMC interface */
183#define REALVIEW_KMI0_BASE 0x10006000 /* KMI interface */
184#define REALVIEW_KMI1_BASE 0x10007000 /* KMI 2nd interface */
185#define REALVIEW_CHAR_LCD_BASE 0x10008000 /* Character LCD */
186#define REALVIEW_UART0_BASE 0x10009000 /* UART 0 */
187#define REALVIEW_UART1_BASE 0x1000A000 /* UART 1 */
188#define REALVIEW_UART2_BASE 0x1000B000 /* UART 2 */
189#define REALVIEW_UART3_BASE 0x1000C000 /* UART 3 */
190#define REALVIEW_SSP_BASE 0x1000D000 /* Synchronous Serial Port */
191#define REALVIEW_SCI_BASE 0x1000E000 /* Smart card controller */
192 /* Reserved 0x1000F000 */
193#define REALVIEW_WATCHDOG_BASE 0x10010000 /* watchdog interface */
194#define REALVIEW_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */
195#define REALVIEW_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */
196#define REALVIEW_GPIO0_BASE 0x10013000 /* GPIO port 0 */
197#define REALVIEW_GPIO1_BASE 0x10014000 /* GPIO port 1 */
198#define REALVIEW_GPIO2_BASE 0x10015000 /* GPIO port 2 */
199 /* Reserved 0x10016000 */
200#define REALVIEW_RTC_BASE 0x10017000 /* Real Time Clock */
201#define REALVIEW_DMC_BASE 0x10018000 /* DMC configuration */
202#define REALVIEW_PCI_CORE_BASE 0x10019000 /* PCI configuration */
203 /* Reserved 0x1001A000 - 0x1001FFFF */
204#define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */
205#define REALVIEW_DMAC_BASE 0x10030000 /* DMA controller */
206#define REALVIEW_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */
207#define REALVIEW_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */
208#define REALVIEW_SMC_BASE 0x10080000 /* SMC */
209 /* Reserved 0x10090000 - 0x100EFFFF */
210
211#define REALVIEW_ETH_BASE 0x4E000000 /* Ethernet */
212
213/* PCI space */
214#define REALVIEW_PCI_BASE 0x41000000 /* PCI Interface */
215#define REALVIEW_PCI_CFG_BASE 0x42000000
216#define REALVIEW_PCI_MEM_BASE0 0x44000000
217#define REALVIEW_PCI_MEM_BASE1 0x50000000
218#define REALVIEW_PCI_MEM_BASE2 0x60000000
219/* Sizes of above maps */
220#define REALVIEW_PCI_BASE_SIZE 0x01000000
221#define REALVIEW_PCI_CFG_BASE_SIZE 0x02000000
222#define REALVIEW_PCI_MEM_BASE0_SIZE 0x0c000000 /* 32Mb */
223#define REALVIEW_PCI_MEM_BASE1_SIZE 0x10000000 /* 256Mb */
224#define REALVIEW_PCI_MEM_BASE2_SIZE 0x10000000 /* 256Mb */
225
226#define REALVIEW_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */
227#define REALVIEW_LT_BASE 0x80000000 /* Logic Tile expansion */
228
229/*
230 * Disk on Chip
231 */
232#define REALVIEW_DOC_BASE 0x2C000000
233#define REALVIEW_DOC_SIZE (16 << 20)
234#define REALVIEW_DOC_PAGE_SIZE 512
235#define REALVIEW_DOC_TOTAL_PAGES (DOC_SIZE / PAGE_SIZE)
236
237#define ERASE_UNIT_PAGES 32
238#define START_PAGE 0x80
239
240/*
241 * LED settings, bits [7:0]
242 */
243#define REALVIEW_SYS_LED0 (1 << 0)
244#define REALVIEW_SYS_LED1 (1 << 1)
245#define REALVIEW_SYS_LED2 (1 << 2)
246#define REALVIEW_SYS_LED3 (1 << 3)
247#define REALVIEW_SYS_LED4 (1 << 4)
248#define REALVIEW_SYS_LED5 (1 << 5)
249#define REALVIEW_SYS_LED6 (1 << 6)
250#define REALVIEW_SYS_LED7 (1 << 7)
251
252#define ALL_LEDS 0xFF
253
254#define LED_BANK REALVIEW_SYS_LED
255
256/*
257 * Control registers
258 */
259#define REALVIEW_IDFIELD_OFFSET 0x0 /* RealView build information */
260#define REALVIEW_FLASHPROG_OFFSET 0x4 /* Flash devices */
261#define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */
262#define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */
263
264/* ------------------------------------------------------------------------
265 * Interrupts - bit assignment (primary)
266 * ------------------------------------------------------------------------
267 */
268#define INT_WDOGINT 0 /* Watchdog timer */
269#define INT_SOFTINT 1 /* Software interrupt */
270#define INT_COMMRx 2 /* Debug Comm Rx interrupt */
271#define INT_COMMTx 3 /* Debug Comm Tx interrupt */
272#define INT_TIMERINT0_1 4 /* Timer 0 and 1 */
273#define INT_TIMERINT2_3 5 /* Timer 2 and 3 */
274#define INT_GPIOINT0 6 /* GPIO 0 */
275#define INT_GPIOINT1 7 /* GPIO 1 */
276#define INT_GPIOINT2 8 /* GPIO 2 */
277/* 9 reserved */
278#define INT_RTCINT 10 /* Real Time Clock */
279#define INT_SSPINT 11 /* Synchronous Serial Port */
280#define INT_UARTINT0 12 /* UART 0 on development chip */
281#define INT_UARTINT1 13 /* UART 1 on development chip */
282#define INT_UARTINT2 14 /* UART 2 on development chip */
283#define INT_UARTINT3 15 /* UART 3 on development chip */
284#define INT_SCIINT 16 /* Smart Card Interface */
285#define INT_MMCI0A 17 /* Multimedia Card 0A */
286#define INT_MMCI0B 18 /* Multimedia Card 0B */
287#define INT_AACI 19 /* Audio Codec */
288#define INT_KMI0 20 /* Keyboard/Mouse port 0 */
289#define INT_KMI1 21 /* Keyboard/Mouse port 1 */
290#define INT_CHARLCD 22 /* Character LCD */
291#define INT_CLCDINT 23 /* CLCD controller */
292#define INT_DMAINT 24 /* DMA controller */
293#define INT_PWRFAILINT 25 /* Power failure */
294#define INT_PISMO 26
295#define INT_DoC 27 /* Disk on Chip memory controller */
296#define INT_ETH 28 /* Ethernet controller */
297#define INT_USB 29 /* USB controller */
298#define INT_TSPENINT 30 /* Touchscreen pen */
299#define INT_TSKPADINT 31 /* Touchscreen keypad */
300
301/*
302 * Interrupt bit positions
303 *
304 */
305#define INTMASK_WDOGINT (1 << INT_WDOGINT)
306#define INTMASK_SOFTINT (1 << INT_SOFTINT)
307#define INTMASK_COMMRx (1 << INT_COMMRx)
308#define INTMASK_COMMTx (1 << INT_COMMTx)
309#define INTMASK_TIMERINT0_1 (1 << INT_TIMERINT0_1)
310#define INTMASK_TIMERINT2_3 (1 << INT_TIMERINT2_3)
311#define INTMASK_GPIOINT0 (1 << INT_GPIOINT0)
312#define INTMASK_GPIOINT1 (1 << INT_GPIOINT1)
313#define INTMASK_GPIOINT2 (1 << INT_GPIOINT2)
314#define INTMASK_RTCINT (1 << INT_RTCINT)
315#define INTMASK_SSPINT (1 << INT_SSPINT)
316#define INTMASK_UARTINT0 (1 << INT_UARTINT0)
317#define INTMASK_UARTINT1 (1 << INT_UARTINT1)
318#define INTMASK_UARTINT2 (1 << INT_UARTINT2)
319#define INTMASK_UARTINT3 (1 << INT_UARTINT3)
320#define INTMASK_SCIINT (1 << INT_SCIINT)
321#define INTMASK_MMCI0A (1 << INT_MMCI0A)
322#define INTMASK_MMCI0B (1 << INT_MMCI0B)
323#define INTMASK_AACI (1 << INT_AACI)
324#define INTMASK_KMI0 (1 << INT_KMI0)
325#define INTMASK_KMI1 (1 << INT_KMI1)
326#define INTMASK_CHARLCD (1 << INT_CHARLCD)
327#define INTMASK_CLCDINT (1 << INT_CLCDINT)
328#define INTMASK_DMAINT (1 << INT_DMAINT)
329#define INTMASK_PWRFAILINT (1 << INT_PWRFAILINT)
330#define INTMASK_PISMO (1 << INT_PISMO)
331#define INTMASK_DoC (1 << INT_DoC)
332#define INTMASK_ETH (1 << INT_ETH)
333#define INTMASK_USB (1 << INT_USB)
334#define INTMASK_TSPENINT (1 << INT_TSPENINT)
335#define INTMASK_TSKPADINT (1 << INT_TSKPADINT)
336
337#define MAXIRQNUM 31
338#define MAXFIQNUM 31
339#define MAXSWINUM 31
340
341/*
342 * Application Flash
343 *
344 */
345#define FLASH_BASE REALVIEW_FLASH_BASE
346#define FLASH_SIZE REALVIEW_FLASH_SIZE
347#define FLASH_END (FLASH_BASE + FLASH_SIZE - 1)
348#define FLASH_BLOCK_SIZE SZ_128K
349
350/*
351 * Boot Flash
352 *
353 */
354#define EPROM_BASE REALVIEW_BOOT_ROM_HI
355#define EPROM_SIZE REALVIEW_BOOT_ROM_SIZE
356#define EPROM_END (EPROM_BASE + EPROM_SIZE - 1)
357
358/*
359 * Clean base - dummy
360 *
361 */
362#define CLEAN_BASE EPROM_BASE
363
364/*
365 * System controller bit assignment
366 */
367#define REALVIEW_REFCLK 0
368#define REALVIEW_TIMCLK 1
369
370#define REALVIEW_TIMER1_EnSel 15
371#define REALVIEW_TIMER2_EnSel 17
372#define REALVIEW_TIMER3_EnSel 19
373#define REALVIEW_TIMER4_EnSel 21
374
375
376#define MAX_TIMER 2
377#define MAX_PERIOD 699050
378#define TICKS_PER_uSEC 1
379
380/*
381 * These are useconds NOT ticks.
382 *
383 */
384#define mSEC_1 1000
385#define mSEC_5 (mSEC_1 * 5)
386#define mSEC_10 (mSEC_1 * 10)
387#define mSEC_25 (mSEC_1 * 25)
388#define SEC_1 (mSEC_1 * 1000)
389
390#define REALVIEW_CSR_BASE 0x10000000
391#define REALVIEW_CSR_SIZE 0x10000000
392
393#endif
394
395/* END */
diff --git a/include/asm-arm/arch-realview/system.h b/include/asm-arm/arch-realview/system.h
new file mode 100644
index 000000000000..9f8fcbca0869
--- /dev/null
+++ b/include/asm-arm/arch-realview/system.h
@@ -0,0 +1,51 @@
1/*
2 * linux/include/asm-arm/arch-realview/system.h
3 *
4 * Copyright (C) 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef __ASM_ARCH_SYSTEM_H
22#define __ASM_ARCH_SYSTEM_H
23
24#include <asm/hardware.h>
25#include <asm/io.h>
26#include <asm/arch/platform.h>
27
28static inline void arch_idle(void)
29{
30 /*
31 * This should do all the clock switching
32 * and wait for interrupt tricks
33 */
34 cpu_do_idle();
35}
36
37static inline void arch_reset(char mode)
38{
39 unsigned int hdr_ctrl = (IO_ADDRESS(REALVIEW_SYS_BASE) + REALVIEW_SYS_RESETCTL_OFFSET);
40 unsigned int val;
41
42 /*
43 * To reset, we hit the on-board reset register
44 * in the system FPGA
45 */
46 val = __raw_readl(hdr_ctrl);
47 val |= REALVIEW_SYS_CTRL_RESET_CONFIGCLR;
48 __raw_writel(val, hdr_ctrl);
49}
50
51#endif
diff --git a/include/asm-arm/arch-realview/timex.h b/include/asm-arm/arch-realview/timex.h
new file mode 100644
index 000000000000..5b9d82d0a5e0
--- /dev/null
+++ b/include/asm-arm/arch-realview/timex.h
@@ -0,0 +1,23 @@
1/*
2 * linux/include/asm-arm/arch-realview/timex.h
3 *
4 * RealView architecture timex specifications
5 *
6 * Copyright (C) 2003 ARM Limited
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#define CLOCK_TICK_RATE (50000000 / 16)
diff --git a/include/asm-arm/arch-realview/uncompress.h b/include/asm-arm/arch-realview/uncompress.h
new file mode 100644
index 000000000000..b5e4d360665b
--- /dev/null
+++ b/include/asm-arm/arch-realview/uncompress.h
@@ -0,0 +1,54 @@
1/*
2 * linux/include/asm-arm/arch-realview/uncompress.h
3 *
4 * Copyright (C) 2003 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include <asm/hardware.h>
21
22#define AMBA_UART_DR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x00))
23#define AMBA_UART_LCRH (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x2c))
24#define AMBA_UART_CR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x30))
25#define AMBA_UART_FR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x18))
26
27/*
28 * This does not append a newline
29 */
30static void putstr(const char *s)
31{
32 while (*s) {
33 while (AMBA_UART_FR & (1 << 5))
34 barrier();
35
36 AMBA_UART_DR = *s;
37
38 if (*s == '\n') {
39 while (AMBA_UART_FR & (1 << 5))
40 barrier();
41
42 AMBA_UART_DR = '\r';
43 }
44 s++;
45 }
46 while (AMBA_UART_FR & (1 << 3))
47 barrier();
48}
49
50/*
51 * nothing to do
52 */
53#define arch_decomp_setup()
54#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-realview/vmalloc.h b/include/asm-arm/arch-realview/vmalloc.h
new file mode 100644
index 000000000000..0ad49af186af
--- /dev/null
+++ b/include/asm-arm/arch-realview/vmalloc.h
@@ -0,0 +1,21 @@
1/*
2 * linux/include/asm-arm/arch-realview/vmalloc.h
3 *
4 * Copyright (C) 2003 ARM Limited
5 * Copyright (C) 2000 Russell King.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define VMALLOC_END (PAGE_OFFSET + 0x18000000)
diff --git a/include/asm-arm/arch-s3c2410/regs-iis.h b/include/asm-arm/arch-s3c2410/regs-iis.h
index fdd62e8cd6cb..7fdde9b91cb4 100644
--- a/include/asm-arm/arch-s3c2410/regs-iis.h
+++ b/include/asm-arm/arch-s3c2410/regs-iis.h
@@ -55,6 +55,7 @@
55#define S3C2410_IISMOD_16FS (0<<0) 55#define S3C2410_IISMOD_16FS (0<<0)
56#define S3C2410_IISMOD_32FS (1<<0) 56#define S3C2410_IISMOD_32FS (1<<0)
57#define S3C2410_IISMOD_48FS (2<<0) 57#define S3C2410_IISMOD_48FS (2<<0)
58#define S3C2410_IISMOD_FS_MASK (3<<0)
58 59
59#define S3C2410_IISPSR (0x08) 60#define S3C2410_IISPSR (0x08)
60#define S3C2410_IISPSR_INTMASK (31<<5) 61#define S3C2410_IISPSR_INTMASK (31<<5)
diff --git a/include/asm-arm/hardware/amba_clcd.h b/include/asm-arm/hardware/amba_clcd.h
index ce4cf5c1c05d..6b8d73dc1ab0 100644
--- a/include/asm-arm/hardware/amba_clcd.h
+++ b/include/asm-arm/hardware/amba_clcd.h
@@ -22,7 +22,7 @@
22#define CLCD_UBAS 0x00000010 22#define CLCD_UBAS 0x00000010
23#define CLCD_LBAS 0x00000014 23#define CLCD_LBAS 0x00000014
24 24
25#ifndef CONFIG_ARCH_VERSATILE 25#if !defined(CONFIG_ARCH_VERSATILE) && !defined(CONFIG_ARCH_REALVIEW)
26#define CLCD_IENB 0x00000018 26#define CLCD_IENB 0x00000018
27#define CLCD_CNTL 0x0000001c 27#define CLCD_CNTL 0x0000001c
28#else 28#else
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 04:00:38 -0500