diff options
| -rw-r--r-- | arch/arm/mach-exynos/dma.c | 38 | ||||
| -rw-r--r-- | arch/arm/mach-s5p64x0/dma.c | 22 | ||||
| -rw-r--r-- | arch/arm/mach-s5pc100/dma.c | 38 | ||||
| -rw-r--r-- | arch/arm/mach-s5pv210/dma.c | 38 |
4 files changed, 23 insertions, 113 deletions
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c index 8d681bf8e1fa..91370def4a70 100644 --- a/arch/arm/mach-exynos/dma.c +++ b/arch/arm/mach-exynos/dma.c | |||
| @@ -74,21 +74,8 @@ struct dma_pl330_platdata exynos4_pdma0_pdata = { | |||
| 74 | .peri_id = pdma0_peri, | 74 | .peri_id = pdma0_peri, |
| 75 | }; | 75 | }; |
| 76 | 76 | ||
| 77 | struct amba_device exynos4_device_pdma0 = { | 77 | AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330, EXYNOS4_PA_PDMA0, |
| 78 | .dev = { | 78 | {IRQ_PDMA0}, &exynos4_pdma0_pdata); |
| 79 | .init_name = "dma-pl330.0", | ||
| 80 | .dma_mask = &dma_dmamask, | ||
| 81 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 82 | .platform_data = &exynos4_pdma0_pdata, | ||
| 83 | }, | ||
| 84 | .res = { | ||
| 85 | .start = EXYNOS4_PA_PDMA0, | ||
| 86 | .end = EXYNOS4_PA_PDMA0 + SZ_4K, | ||
| 87 | .flags = IORESOURCE_MEM, | ||
| 88 | }, | ||
| 89 | .irq = {IRQ_PDMA0}, | ||
| 90 | .periphid = 0x00041330, | ||
| 91 | }; | ||
| 92 | 79 | ||
| 93 | u8 pdma1_peri[] = { | 80 | u8 pdma1_peri[] = { |
| 94 | DMACH_PCM0_RX, | 81 | DMACH_PCM0_RX, |
| @@ -123,21 +110,8 @@ struct dma_pl330_platdata exynos4_pdma1_pdata = { | |||
| 123 | .peri_id = pdma1_peri, | 110 | .peri_id = pdma1_peri, |
| 124 | }; | 111 | }; |
| 125 | 112 | ||
| 126 | struct amba_device exynos4_device_pdma1 = { | 113 | AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330, EXYNOS4_PA_PDMA1, |
| 127 | .dev = { | 114 | {IRQ_PDMA1}, &exynos4_pdma1_pdata); |
| 128 | .init_name = "dma-pl330.1", | ||
| 129 | .dma_mask = &dma_dmamask, | ||
| 130 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 131 | .platform_data = &exynos4_pdma1_pdata, | ||
| 132 | }, | ||
| 133 | .res = { | ||
| 134 | .start = EXYNOS4_PA_PDMA1, | ||
| 135 | .end = EXYNOS4_PA_PDMA1 + SZ_4K, | ||
| 136 | .flags = IORESOURCE_MEM, | ||
| 137 | }, | ||
| 138 | .irq = {IRQ_PDMA1}, | ||
| 139 | .periphid = 0x00041330, | ||
| 140 | }; | ||
| 141 | 115 | ||
| 142 | static int __init exynos4_dma_init(void) | 116 | static int __init exynos4_dma_init(void) |
| 143 | { | 117 | { |
| @@ -146,11 +120,11 @@ static int __init exynos4_dma_init(void) | |||
| 146 | 120 | ||
| 147 | dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask); | 121 | dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask); |
| 148 | dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask); | 122 | dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask); |
| 149 | amba_device_register(&exynos4_device_pdma0, &iomem_resource); | 123 | amba_device_register(&exynos4_pdma0_device, &iomem_resource); |
| 150 | 124 | ||
| 151 | dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask); | 125 | dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask); |
| 152 | dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask); | 126 | dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask); |
| 153 | amba_device_register(&exynos4_device_pdma1, &iomem_resource); | 127 | amba_device_register(&exynos4_pdma1_device, &iomem_resource); |
| 154 | 128 | ||
| 155 | return 0; | 129 | return 0; |
| 156 | } | 130 | } |
diff --git a/arch/arm/mach-s5p64x0/dma.c b/arch/arm/mach-s5p64x0/dma.c index 99049aa11e93..f7f68ad77910 100644 --- a/arch/arm/mach-s5p64x0/dma.c +++ b/arch/arm/mach-s5p64x0/dma.c | |||
| @@ -108,34 +108,22 @@ struct dma_pl330_platdata s5p6450_pdma_pdata = { | |||
| 108 | .peri_id = s5p6450_pdma_peri, | 108 | .peri_id = s5p6450_pdma_peri, |
| 109 | }; | 109 | }; |
| 110 | 110 | ||
| 111 | struct amba_device s5p64x0_device_pdma = { | 111 | AMBA_AHB_DEVICE(s5p64x0_pdma, "dma-pl330", 0x00041330, S5P64X0_PA_PDMA, |
| 112 | .dev = { | 112 | {IRQ_DMA0}, NULL); |
| 113 | .init_name = "dma-pl330", | ||
| 114 | .dma_mask = &dma_dmamask, | ||
| 115 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 116 | }, | ||
| 117 | .res = { | ||
| 118 | .start = S5P64X0_PA_PDMA, | ||
| 119 | .end = S5P64X0_PA_PDMA + SZ_4K, | ||
| 120 | .flags = IORESOURCE_MEM, | ||
| 121 | }, | ||
| 122 | .irq = {IRQ_DMA0}, | ||
| 123 | .periphid = 0x00041330, | ||
| 124 | }; | ||
| 125 | 113 | ||
| 126 | static int __init s5p64x0_dma_init(void) | 114 | static int __init s5p64x0_dma_init(void) |
| 127 | { | 115 | { |
| 128 | if (soc_is_s5p6450()) { | 116 | if (soc_is_s5p6450()) { |
| 129 | dma_cap_set(DMA_SLAVE, s5p6450_pdma_pdata.cap_mask); | 117 | dma_cap_set(DMA_SLAVE, s5p6450_pdma_pdata.cap_mask); |
| 130 | dma_cap_set(DMA_CYCLIC, s5p6450_pdma_pdata.cap_mask); | 118 | dma_cap_set(DMA_CYCLIC, s5p6450_pdma_pdata.cap_mask); |
| 131 | s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata; | 119 | s5p64x0_pdma_device.dev.platform_data = &s5p6450_pdma_pdata; |
| 132 | } else { | 120 | } else { |
| 133 | dma_cap_set(DMA_SLAVE, s5p6440_pdma_pdata.cap_mask); | 121 | dma_cap_set(DMA_SLAVE, s5p6440_pdma_pdata.cap_mask); |
| 134 | dma_cap_set(DMA_CYCLIC, s5p6440_pdma_pdata.cap_mask); | 122 | dma_cap_set(DMA_CYCLIC, s5p6440_pdma_pdata.cap_mask); |
| 135 | s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata; | 123 | s5p64x0_pdma_device.dev.platform_data = &s5p6440_pdma_pdata; |
| 136 | } | 124 | } |
| 137 | 125 | ||
| 138 | amba_device_register(&s5p64x0_device_pdma, &iomem_resource); | 126 | amba_device_register(&s5p64x0_pdma_device, &iomem_resource); |
| 139 | 127 | ||
| 140 | return 0; | 128 | return 0; |
| 141 | } | 129 | } |
diff --git a/arch/arm/mach-s5pc100/dma.c b/arch/arm/mach-s5pc100/dma.c index ac08d7eddee0..96b1ab3dcd48 100644 --- a/arch/arm/mach-s5pc100/dma.c +++ b/arch/arm/mach-s5pc100/dma.c | |||
| @@ -73,21 +73,8 @@ struct dma_pl330_platdata s5pc100_pdma0_pdata = { | |||
| 73 | .peri_id = pdma0_peri, | 73 | .peri_id = pdma0_peri, |
| 74 | }; | 74 | }; |
| 75 | 75 | ||
| 76 | struct amba_device s5pc100_device_pdma0 = { | 76 | AMBA_AHB_DEVICE(s5pc100_pdma0, "dma-pl330.0", 0x00041330, S5PC100_PA_PDMA0, |
| 77 | .dev = { | 77 | {IRQ_PDMA0}, &s5pc100_pdma0_pdata); |
| 78 | .init_name = "dma-pl330.0", | ||
| 79 | .dma_mask = &dma_dmamask, | ||
| 80 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 81 | .platform_data = &s5pc100_pdma0_pdata, | ||
| 82 | }, | ||
| 83 | .res = { | ||
| 84 | .start = S5PC100_PA_PDMA0, | ||
| 85 | .end = S5PC100_PA_PDMA0 + SZ_4K, | ||
| 86 | .flags = IORESOURCE_MEM, | ||
| 87 | }, | ||
| 88 | .irq = {IRQ_PDMA0}, | ||
| 89 | .periphid = 0x00041330, | ||
| 90 | }; | ||
| 91 | 78 | ||
| 92 | u8 pdma1_peri[] = { | 79 | u8 pdma1_peri[] = { |
| 93 | DMACH_UART0_RX, | 80 | DMACH_UART0_RX, |
| @@ -127,31 +114,18 @@ struct dma_pl330_platdata s5pc100_pdma1_pdata = { | |||
| 127 | .peri_id = pdma1_peri, | 114 | .peri_id = pdma1_peri, |
| 128 | }; | 115 | }; |
| 129 | 116 | ||
| 130 | struct amba_device s5pc100_device_pdma1 = { | 117 | AMBA_AHB_DEVICE(s5pc100_pdma1, "dma-pl330.1", 0x00041330, S5PC100_PA_PDMA1, |
| 131 | .dev = { | 118 | {IRQ_PDMA1}, &s5pc100_pdma1_pdata); |
| 132 | .init_name = "dma-pl330.1", | ||
| 133 | .dma_mask = &dma_dmamask, | ||
| 134 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 135 | .platform_data = &s5pc100_pdma1_pdata, | ||
| 136 | }, | ||
| 137 | .res = { | ||
| 138 | .start = S5PC100_PA_PDMA1, | ||
| 139 | .end = S5PC100_PA_PDMA1 + SZ_4K, | ||
| 140 | .flags = IORESOURCE_MEM, | ||
| 141 | }, | ||
| 142 | .irq = {IRQ_PDMA1}, | ||
| 143 | .periphid = 0x00041330, | ||
| 144 | }; | ||
| 145 | 119 | ||
| 146 | static int __init s5pc100_dma_init(void) | 120 | static int __init s5pc100_dma_init(void) |
| 147 | { | 121 | { |
| 148 | dma_cap_set(DMA_SLAVE, s5pc100_pdma0_pdata.cap_mask); | 122 | dma_cap_set(DMA_SLAVE, s5pc100_pdma0_pdata.cap_mask); |
| 149 | dma_cap_set(DMA_CYCLIC, s5pc100_pdma0_pdata.cap_mask); | 123 | dma_cap_set(DMA_CYCLIC, s5pc100_pdma0_pdata.cap_mask); |
| 150 | amba_device_register(&s5pc100_device_pdma0, &iomem_resource); | 124 | amba_device_register(&s5pc100_pdma0_device, &iomem_resource); |
| 151 | 125 | ||
| 152 | dma_cap_set(DMA_SLAVE, s5pc100_pdma1_pdata.cap_mask); | 126 | dma_cap_set(DMA_SLAVE, s5pc100_pdma1_pdata.cap_mask); |
| 153 | dma_cap_set(DMA_CYCLIC, s5pc100_pdma1_pdata.cap_mask); | 127 | dma_cap_set(DMA_CYCLIC, s5pc100_pdma1_pdata.cap_mask); |
| 154 | amba_device_register(&s5pc100_device_pdma1, &iomem_resource); | 128 | amba_device_register(&s5pc100_pdma1_device, &iomem_resource); |
| 155 | 129 | ||
| 156 | return 0; | 130 | return 0; |
| 157 | } | 131 | } |
diff --git a/arch/arm/mach-s5pv210/dma.c b/arch/arm/mach-s5pv210/dma.c index 8602fa51a942..f6885d247d14 100644 --- a/arch/arm/mach-s5pv210/dma.c +++ b/arch/arm/mach-s5pv210/dma.c | |||
| @@ -71,21 +71,8 @@ struct dma_pl330_platdata s5pv210_pdma0_pdata = { | |||
| 71 | .peri_id = pdma0_peri, | 71 | .peri_id = pdma0_peri, |
| 72 | }; | 72 | }; |
| 73 | 73 | ||
| 74 | struct amba_device s5pv210_device_pdma0 = { | 74 | AMBA_AHB_DEVICE(s5pv210_pdma0, "dma-pl330.0", 0x00041330, S5PV210_PA_PDMA0, |
| 75 | .dev = { | 75 | {IRQ_PDMA0}, &s5pv210_pdma0_pdata); |
| 76 | .init_name = "dma-pl330.0", | ||
| 77 | .dma_mask = &dma_dmamask, | ||
| 78 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 79 | .platform_data = &s5pv210_pdma0_pdata, | ||
| 80 | }, | ||
| 81 | .res = { | ||
| 82 | .start = S5PV210_PA_PDMA0, | ||
| 83 | .end = S5PV210_PA_PDMA0 + SZ_4K, | ||
| 84 | .flags = IORESOURCE_MEM, | ||
| 85 | }, | ||
| 86 | .irq = {IRQ_PDMA0}, | ||
| 87 | .periphid = 0x00041330, | ||
| 88 | }; | ||
| 89 | 76 | ||
| 90 | u8 pdma1_peri[] = { | 77 | u8 pdma1_peri[] = { |
| 91 | DMACH_UART0_RX, | 78 | DMACH_UART0_RX, |
| @@ -127,31 +114,18 @@ struct dma_pl330_platdata s5pv210_pdma1_pdata = { | |||
| 127 | .peri_id = pdma1_peri, | 114 | .peri_id = pdma1_peri, |
| 128 | }; | 115 | }; |
| 129 | 116 | ||
| 130 | struct amba_device s5pv210_device_pdma1 = { | 117 | AMBA_AHB_DEVICE(s5pv210_pdma1, "dma-pl330.1", 0x00041330, S5PV210_PA_PDMA1, |
| 131 | .dev = { | 118 | {IRQ_PDMA1}, &s5pv210_pdma1_pdata); |
| 132 | .init_name = "dma-pl330.1", | ||
| 133 | .dma_mask = &dma_dmamask, | ||
| 134 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 135 | .platform_data = &s5pv210_pdma1_pdata, | ||
| 136 | }, | ||
| 137 | .res = { | ||
| 138 | .start = S5PV210_PA_PDMA1, | ||
| 139 | .end = S5PV210_PA_PDMA1 + SZ_4K, | ||
| 140 | .flags = IORESOURCE_MEM, | ||
| 141 | }, | ||
| 142 | .irq = {IRQ_PDMA1}, | ||
| 143 | .periphid = 0x00041330, | ||
| 144 | }; | ||
| 145 | 119 | ||
| 146 | static int __init s5pv210_dma_init(void) | 120 | static int __init s5pv210_dma_init(void) |
| 147 | { | 121 | { |
| 148 | dma_cap_set(DMA_SLAVE, s5pv210_pdma0_pdata.cap_mask); | 122 | dma_cap_set(DMA_SLAVE, s5pv210_pdma0_pdata.cap_mask); |
| 149 | dma_cap_set(DMA_CYCLIC, s5pv210_pdma0_pdata.cap_mask); | 123 | dma_cap_set(DMA_CYCLIC, s5pv210_pdma0_pdata.cap_mask); |
| 150 | amba_device_register(&s5pv210_device_pdma0, &iomem_resource); | 124 | amba_device_register(&s5pv210_pdma0_device, &iomem_resource); |
| 151 | 125 | ||
| 152 | dma_cap_set(DMA_SLAVE, s5pv210_pdma1_pdata.cap_mask); | 126 | dma_cap_set(DMA_SLAVE, s5pv210_pdma1_pdata.cap_mask); |
| 153 | dma_cap_set(DMA_CYCLIC, s5pv210_pdma1_pdata.cap_mask); | 127 | dma_cap_set(DMA_CYCLIC, s5pv210_pdma1_pdata.cap_mask); |
| 154 | amba_device_register(&s5pv210_device_pdma1, &iomem_resource); | 128 | amba_device_register(&s5pv210_pdma1_device, &iomem_resource); |
| 155 | 129 | ||
| 156 | return 0; | 130 | return 0; |
| 157 | } | 131 | } |
