diff options
377 files changed, 9282 insertions, 11482 deletions
diff --git a/Documentation/block/00-INDEX b/Documentation/block/00-INDEX index d111e3b23db0..d18ecd827c40 100644 --- a/Documentation/block/00-INDEX +++ b/Documentation/block/00-INDEX | |||
| @@ -3,15 +3,21 @@ | |||
| 3 | biodoc.txt | 3 | biodoc.txt |
| 4 | - Notes on the Generic Block Layer Rewrite in Linux 2.5 | 4 | - Notes on the Generic Block Layer Rewrite in Linux 2.5 |
| 5 | capability.txt | 5 | capability.txt |
| 6 | - Generic Block Device Capability (/sys/block/<disk>/capability) | 6 | - Generic Block Device Capability (/sys/block/<device>/capability) |
| 7 | cfq-iosched.txt | ||
| 8 | - CFQ IO scheduler tunables | ||
| 9 | data-integrity.txt | ||
| 10 | - Block data integrity | ||
| 7 | deadline-iosched.txt | 11 | deadline-iosched.txt |
| 8 | - Deadline IO scheduler tunables | 12 | - Deadline IO scheduler tunables |
| 9 | ioprio.txt | 13 | ioprio.txt |
| 10 | - Block io priorities (in CFQ scheduler) | 14 | - Block io priorities (in CFQ scheduler) |
| 15 | queue-sysfs.txt | ||
| 16 | - Queue's sysfs entries | ||
| 11 | request.txt | 17 | request.txt |
| 12 | - The members of struct request (in include/linux/blkdev.h) | 18 | - The members of struct request (in include/linux/blkdev.h) |
| 13 | stat.txt | 19 | stat.txt |
| 14 | - Block layer statistics in /sys/block/<dev>/stat | 20 | - Block layer statistics in /sys/block/<device>/stat |
| 15 | switching-sched.txt | 21 | switching-sched.txt |
| 16 | - Switching I/O schedulers at runtime | 22 | - Switching I/O schedulers at runtime |
| 17 | writeback_cache_control.txt | 23 | writeback_cache_control.txt |
diff --git a/Documentation/block/cfq-iosched.txt b/Documentation/block/cfq-iosched.txt index 6d670f570451..d89b4fe724d7 100644 --- a/Documentation/block/cfq-iosched.txt +++ b/Documentation/block/cfq-iosched.txt | |||
| @@ -1,3 +1,14 @@ | |||
| 1 | CFQ (Complete Fairness Queueing) | ||
| 2 | =============================== | ||
| 3 | |||
| 4 | The main aim of CFQ scheduler is to provide a fair allocation of the disk | ||
| 5 | I/O bandwidth for all the processes which requests an I/O operation. | ||
| 6 | |||
| 7 | CFQ maintains the per process queue for the processes which request I/O | ||
| 8 | operation(syncronous requests). In case of asynchronous requests, all the | ||
| 9 | requests from all the processes are batched together according to their | ||
| 10 | process's I/O priority. | ||
| 11 | |||
| 1 | CFQ ioscheduler tunables | 12 | CFQ ioscheduler tunables |
| 2 | ======================== | 13 | ======================== |
| 3 | 14 | ||
| @@ -25,6 +36,72 @@ there are multiple spindles behind single LUN (Host based hardware RAID | |||
| 25 | controller or for storage arrays), setting slice_idle=0 might end up in better | 36 | controller or for storage arrays), setting slice_idle=0 might end up in better |
| 26 | throughput and acceptable latencies. | 37 | throughput and acceptable latencies. |
| 27 | 38 | ||
| 39 | back_seek_max | ||
| 40 | ------------- | ||
| 41 | This specifies, given in Kbytes, the maximum "distance" for backward seeking. | ||
| 42 | The distance is the amount of space from the current head location to the | ||
| 43 | sectors that are backward in terms of distance. | ||
| 44 | |||
| 45 | This parameter allows the scheduler to anticipate requests in the "backward" | ||
| 46 | direction and consider them as being the "next" if they are within this | ||
| 47 | distance from the current head location. | ||
| 48 | |||
| 49 | back_seek_penalty | ||
| 50 | ----------------- | ||
| 51 | This parameter is used to compute the cost of backward seeking. If the | ||
| 52 | backward distance of request is just 1/back_seek_penalty from a "front" | ||
| 53 | request, then the seeking cost of two requests is considered equivalent. | ||
| 54 | |||
| 55 | So scheduler will not bias toward one or the other request (otherwise scheduler | ||
| 56 | will bias toward front request). Default value of back_seek_penalty is 2. | ||
| 57 | |||
| 58 | fifo_expire_async | ||
| 59 | ----------------- | ||
| 60 | This parameter is used to set the timeout of asynchronous requests. Default | ||
| 61 | value of this is 248ms. | ||
| 62 | |||
| 63 | fifo_expire_sync | ||
| 64 | ---------------- | ||
| 65 | This parameter is used to set the timeout of synchronous requests. Default | ||
| 66 | value of this is 124ms. In case to favor synchronous requests over asynchronous | ||
| 67 | one, this value should be decreased relative to fifo_expire_async. | ||
| 68 | |||
| 69 | slice_async | ||
| 70 | ----------- | ||
| 71 | This parameter is same as of slice_sync but for asynchronous queue. The | ||
| 72 | default value is 40ms. | ||
| 73 | |||
| 74 | slice_async_rq | ||
| 75 | -------------- | ||
| 76 | This parameter is used to limit the dispatching of asynchronous request to | ||
| 77 | device request queue in queue's slice time. The maximum number of request that | ||
| 78 | are allowed to be dispatched also depends upon the io priority. Default value | ||
| 79 | for this is 2. | ||
| 80 | |||
| 81 | slice_sync | ||
| 82 | ---------- | ||
| 83 | When a queue is selected for execution, the queues IO requests are only | ||
| 84 | executed for a certain amount of time(time_slice) before switching to another | ||
| 85 | queue. This parameter is used to calculate the time slice of synchronous | ||
| 86 | queue. | ||
| 87 | |||
| 88 | time_slice is computed using the below equation:- | ||
| 89 | time_slice = slice_sync + (slice_sync/5 * (4 - prio)). To increase the | ||
| 90 | time_slice of synchronous queue, increase the value of slice_sync. Default | ||
| 91 | value is 100ms. | ||
| 92 | |||
| 93 | quantum | ||
| 94 | ------- | ||
| 95 | This specifies the number of request dispatched to the device queue. In a | ||
| 96 | queue's time slice, a request will not be dispatched if the number of request | ||
| 97 | in the device exceeds this parameter. This parameter is used for synchronous | ||
| 98 | request. | ||
| 99 | |||
| 100 | In case of storage with several disk, this setting can limit the parallel | ||
| 101 | processing of request. Therefore, increasing the value can imporve the | ||
| 102 | performace although this can cause the latency of some I/O to increase due | ||
| 103 | to more number of requests. | ||
| 104 | |||
| 28 | CFQ IOPS Mode for group scheduling | 105 | CFQ IOPS Mode for group scheduling |
| 29 | =================================== | 106 | =================================== |
| 30 | Basic CFQ design is to provide priority based time slices. Higher priority | 107 | Basic CFQ design is to provide priority based time slices. Higher priority |
diff --git a/Documentation/block/queue-sysfs.txt b/Documentation/block/queue-sysfs.txt index 6518a55273e7..e54ac1d53403 100644 --- a/Documentation/block/queue-sysfs.txt +++ b/Documentation/block/queue-sysfs.txt | |||
| @@ -9,20 +9,71 @@ These files are the ones found in the /sys/block/xxx/queue/ directory. | |||
| 9 | Files denoted with a RO postfix are readonly and the RW postfix means | 9 | Files denoted with a RO postfix are readonly and the RW postfix means |
| 10 | read-write. | 10 | read-write. |
| 11 | 11 | ||
| 12 | add_random (RW) | ||
| 13 | ---------------- | ||
| 14 | This file allows to trun off the disk entropy contribution. Default | ||
| 15 | value of this file is '1'(on). | ||
| 16 | |||
| 17 | discard_granularity (RO) | ||
| 18 | ----------------------- | ||
| 19 | This shows the size of internal allocation of the device in bytes, if | ||
| 20 | reported by the device. A value of '0' means device does not support | ||
| 21 | the discard functionality. | ||
| 22 | |||
| 23 | discard_max_bytes (RO) | ||
| 24 | ---------------------- | ||
| 25 | Devices that support discard functionality may have internal limits on | ||
| 26 | the number of bytes that can be trimmed or unmapped in a single operation. | ||
| 27 | The discard_max_bytes parameter is set by the device driver to the maximum | ||
| 28 | number of bytes that can be discarded in a single operation. Discard | ||
| 29 | requests issued to the device must not exceed this limit. A discard_max_bytes | ||
| 30 | value of 0 means that the device does not support discard functionality. | ||
| 31 | |||
| 32 | discard_zeroes_data (RO) | ||
| 33 | ------------------------ | ||
| 34 | When read, this file will show if the discarded block are zeroed by the | ||
| 35 | device or not. If its value is '1' the blocks are zeroed otherwise not. | ||
| 36 | |||
| 12 | hw_sector_size (RO) | 37 | hw_sector_size (RO) |
| 13 | ------------------- | 38 | ------------------- |
| 14 | This is the hardware sector size of the device, in bytes. | 39 | This is the hardware sector size of the device, in bytes. |
| 15 | 40 | ||
| 41 | iostats (RW) | ||
| 42 | ------------- | ||
| 43 | This file is used to control (on/off) the iostats accounting of the | ||
| 44 | disk. | ||
| 45 | |||
| 46 | logical_block_size (RO) | ||
| 47 | ----------------------- | ||
| 48 | This is the logcal block size of the device, in bytes. | ||
| 49 | |||
| 16 | max_hw_sectors_kb (RO) | 50 | max_hw_sectors_kb (RO) |
| 17 | ---------------------- | 51 | ---------------------- |
| 18 | This is the maximum number of kilobytes supported in a single data transfer. | 52 | This is the maximum number of kilobytes supported in a single data transfer. |
| 19 | 53 | ||
| 54 | max_integrity_segments (RO) | ||
| 55 | --------------------------- | ||
| 56 | When read, this file shows the max limit of integrity segments as | ||
| 57 | set by block layer which a hardware controller can handle. | ||
| 58 | |||
| 20 | max_sectors_kb (RW) | 59 | max_sectors_kb (RW) |
| 21 | ------------------- | 60 | ------------------- |
| 22 | This is the maximum number of kilobytes that the block layer will allow | 61 | This is the maximum number of kilobytes that the block layer will allow |
| 23 | for a filesystem request. Must be smaller than or equal to the maximum | 62 | for a filesystem request. Must be smaller than or equal to the maximum |
| 24 | size allowed by the hardware. | 63 | size allowed by the hardware. |
| 25 | 64 | ||
| 65 | max_segments (RO) | ||
| 66 | ----------------- | ||
| 67 | Maximum number of segments of the device. | ||
| 68 | |||
| 69 | max_segment_size (RO) | ||
| 70 | --------------------- | ||
| 71 | Maximum segment size of the device. | ||
| 72 | |||
| 73 | minimum_io_size (RO) | ||
| 74 | -------------------- | ||
| 75 | This is the smallest preferred io size reported by the device. | ||
| 76 | |||
| 26 | nomerges (RW) | 77 | nomerges (RW) |
| 27 | ------------- | 78 | ------------- |
| 28 | This enables the user to disable the lookup logic involved with IO | 79 | This enables the user to disable the lookup logic involved with IO |
| @@ -45,11 +96,24 @@ per-block-cgroup request pool. IOW, if there are N block cgroups, | |||
| 45 | each request queue may have upto N request pools, each independently | 96 | each request queue may have upto N request pools, each independently |
| 46 | regulated by nr_requests. | 97 | regulated by nr_requests. |
| 47 | 98 | ||
| 99 | optimal_io_size (RO) | ||
| 100 | -------------------- | ||
| 101 | This is the optimal io size reported by the device. | ||
| 102 | |||
| 103 | physical_block_size (RO) | ||
| 104 | ------------------------ | ||
| 105 | This is the physical block size of device, in bytes. | ||
| 106 | |||
| 48 | read_ahead_kb (RW) | 107 | read_ahead_kb (RW) |
| 49 | ------------------ | 108 | ------------------ |
| 50 | Maximum number of kilobytes to read-ahead for filesystems on this block | 109 | Maximum number of kilobytes to read-ahead for filesystems on this block |
| 51 | device. | 110 | device. |
| 52 | 111 | ||
| 112 | rotational (RW) | ||
| 113 | --------------- | ||
| 114 | This file is used to stat if the device is of rotational type or | ||
| 115 | non-rotational type. | ||
| 116 | |||
| 53 | rq_affinity (RW) | 117 | rq_affinity (RW) |
| 54 | ---------------- | 118 | ---------------- |
| 55 | If this option is '1', the block layer will migrate request completions to the | 119 | If this option is '1', the block layer will migrate request completions to the |
diff --git a/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt b/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt new file mode 100644 index 000000000000..31af1cbb60bd --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt | |||
| @@ -0,0 +1,17 @@ | |||
| 1 | * Marvell Tauros2 Cache | ||
| 2 | |||
| 3 | Required properties: | ||
| 4 | - compatible : Should be "marvell,tauros2-cache". | ||
| 5 | - marvell,tauros2-cache-features : Specify the features supported for the | ||
| 6 | tauros2 cache. | ||
| 7 | The features including | ||
| 8 | CACHE_TAUROS2_PREFETCH_ON (1 << 0) | ||
| 9 | CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1) | ||
| 10 | The definition can be found at | ||
| 11 | arch/arm/include/asm/hardware/cache-tauros2.h | ||
| 12 | |||
| 13 | Example: | ||
| 14 | L2: l2-cache { | ||
| 15 | compatible = "marvell,tauros2-cache"; | ||
| 16 | marvell,tauros2-cache-features = <0x3>; | ||
| 17 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/imx23-clock.txt b/Documentation/devicetree/bindings/clock/imx23-clock.txt new file mode 100644 index 000000000000..a0b867ef8d96 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx23-clock.txt | |||
| @@ -0,0 +1,76 @@ | |||
| 1 | * Clock bindings for Freescale i.MX23 | ||
| 2 | |||
| 3 | Required properties: | ||
| 4 | - compatible: Should be "fsl,imx23-clkctrl" | ||
| 5 | - reg: Address and length of the register set | ||
| 6 | - #clock-cells: Should be <1> | ||
| 7 | |||
| 8 | The clock consumer should specify the desired clock by having the clock | ||
| 9 | ID in its "clocks" phandle cell. The following is a full list of i.MX23 | ||
| 10 | clocks and IDs. | ||
| 11 | |||
| 12 | Clock ID | ||
| 13 | ------------------ | ||
| 14 | ref_xtal 0 | ||
| 15 | pll 1 | ||
| 16 | ref_cpu 2 | ||
| 17 | ref_emi 3 | ||
| 18 | ref_pix 4 | ||
| 19 | ref_io 5 | ||
| 20 | saif_sel 6 | ||
| 21 | lcdif_sel 7 | ||
| 22 | gpmi_sel 8 | ||
| 23 | ssp_sel 9 | ||
| 24 | emi_sel 10 | ||
| 25 | cpu 11 | ||
| 26 | etm_sel 12 | ||
| 27 | cpu_pll 13 | ||
| 28 | cpu_xtal 14 | ||
| 29 | hbus 15 | ||
| 30 | xbus 16 | ||
| 31 | lcdif_div 17 | ||
| 32 | ssp_div 18 | ||
| 33 | gpmi_div 19 | ||
| 34 | emi_pll 20 | ||
| 35 | emi_xtal 21 | ||
| 36 | etm_div 22 | ||
| 37 | saif_div 23 | ||
| 38 | clk32k_div 24 | ||
| 39 | rtc 25 | ||
| 40 | adc 26 | ||
| 41 | spdif_div 27 | ||
| 42 | clk32k 28 | ||
| 43 | dri 29 | ||
| 44 | pwm 30 | ||
| 45 | filt 31 | ||
| 46 | uart 32 | ||
| 47 | ssp 33 | ||
| 48 | gpmi 34 | ||
| 49 | spdif 35 | ||
| 50 | emi 36 | ||
| 51 | saif 37 | ||
| 52 | lcdif 38 | ||
| 53 | etm 39 | ||
| 54 | usb 40 | ||
| 55 | usb_pwr 41 | ||
| 56 | |||
| 57 | Examples: | ||
| 58 | |||
| 59 | clks: clkctrl@80040000 { | ||
| 60 | compatible = "fsl,imx23-clkctrl"; | ||
| 61 | reg = <0x80040000 0x2000>; | ||
| 62 | #clock-cells = <1>; | ||
| 63 | clock-output-names = | ||
| 64 | ... | ||
| 65 | "uart", /* 32 */ | ||
| 66 | ... | ||
| 67 | "end_of_list"; | ||
| 68 | }; | ||
| 69 | |||
| 70 | auart0: serial@8006c000 { | ||
| 71 | compatible = "fsl,imx23-auart"; | ||
| 72 | reg = <0x8006c000 0x2000>; | ||
| 73 | interrupts = <24 25 23>; | ||
| 74 | clocks = <&clks 32>; | ||
| 75 | status = "disabled"; | ||
| 76 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/imx28-clock.txt b/Documentation/devicetree/bindings/clock/imx28-clock.txt new file mode 100644 index 000000000000..aa2af2866fe8 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx28-clock.txt | |||
| @@ -0,0 +1,99 @@ | |||
| 1 | * Clock bindings for Freescale i.MX28 | ||
| 2 | |||
| 3 | Required properties: | ||
| 4 | - compatible: Should be "fsl,imx28-clkctrl" | ||
| 5 | - reg: Address and length of the register set | ||
| 6 | - #clock-cells: Should be <1> | ||
| 7 | |||
| 8 | The clock consumer should specify the desired clock by having the clock | ||
| 9 | ID in its "clocks" phandle cell. The following is a full list of i.MX28 | ||
| 10 | clocks and IDs. | ||
| 11 | |||
| 12 | Clock ID | ||
| 13 | ------------------ | ||
| 14 | ref_xtal 0 | ||
| 15 | pll0 1 | ||
| 16 | pll1 2 | ||
| 17 | pll2 3 | ||
| 18 | ref_cpu 4 | ||
| 19 | ref_emi 5 | ||
| 20 | ref_io0 6 | ||
| 21 | ref_io1 7 | ||
| 22 | ref_pix 8 | ||
| 23 | ref_hsadc 9 | ||
| 24 | ref_gpmi 10 | ||
| 25 | saif0_sel 11 | ||
| 26 | saif1_sel 12 | ||
| 27 | gpmi_sel 13 | ||
| 28 | ssp0_sel 14 | ||
| 29 | ssp1_sel 15 | ||
| 30 | ssp2_sel 16 | ||
| 31 | ssp3_sel 17 | ||
| 32 | emi_sel 18 | ||
| 33 | etm_sel 19 | ||
| 34 | lcdif_sel 20 | ||
| 35 | cpu 21 | ||
| 36 | ptp_sel 22 | ||
| 37 | cpu_pll 23 | ||
| 38 | cpu_xtal 24 | ||
| 39 | hbus 25 | ||
| 40 | xbus 26 | ||
| 41 | ssp0_div 27 | ||
| 42 | ssp1_div 28 | ||
| 43 | ssp2_div 29 | ||
| 44 | ssp3_div 30 | ||
| 45 | gpmi_div 31 | ||
| 46 | emi_pll 32 | ||
| 47 | emi_xtal 33 | ||
| 48 | lcdif_div 34 | ||
| 49 | etm_div 35 | ||
| 50 | ptp 36 | ||
| 51 | saif0_div 37 | ||
| 52 | saif1_div 38 | ||
| 53 | clk32k_div 39 | ||
| 54 | rtc 40 | ||
| 55 | lradc 41 | ||
| 56 | spdif_div 42 | ||
| 57 | clk32k 43 | ||
| 58 | pwm 44 | ||
| 59 | uart 45 | ||
| 60 | ssp0 46 | ||
| 61 | ssp1 47 | ||
| 62 | ssp2 48 | ||
| 63 | ssp3 49 | ||
| 64 | gpmi 50 | ||
| 65 | spdif 51 | ||
| 66 | emi 52 | ||
| 67 | saif0 53 | ||
| 68 | saif1 54 | ||
| 69 | lcdif 55 | ||
| 70 | etm 56 | ||
| 71 | fec 57 | ||
| 72 | can0 58 | ||
| 73 | can1 59 | ||
| 74 | usb0 60 | ||
| 75 | usb1 61 | ||
| 76 | usb0_pwr 62 | ||
| 77 | usb1_pwr 63 | ||
| 78 | enet_out 64 | ||
| 79 | |||
| 80 | Examples: | ||
| 81 | |||
| 82 | clks: clkctrl@80040000 { | ||
| 83 | compatible = "fsl,imx28-clkctrl"; | ||
| 84 | reg = <0x80040000 0x2000>; | ||
| 85 | #clock-cells = <1>; | ||
| 86 | clock-output-names = | ||
| 87 | ... | ||
| 88 | "uart", /* 45 */ | ||
| 89 | ... | ||
| 90 | "end_of_list"; | ||
| 91 | }; | ||
| 92 | |||
| 93 | auart0: serial@8006a000 { | ||
| 94 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; | ||
| 95 | reg = <0x8006a000 0x2000>; | ||
| 96 | interrupts = <112 70 71>; | ||
| 97 | clocks = <&clks 45>; | ||
| 98 | status = "disabled"; | ||
| 99 | }; | ||
diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt index 70cd49b1caa8..1dd622546d06 100644 --- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt +++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt | |||
| @@ -10,8 +10,8 @@ Required properties: | |||
| 10 | - compatible : Should be "fsl,<chip>-esdhc" | 10 | - compatible : Should be "fsl,<chip>-esdhc" |
| 11 | 11 | ||
| 12 | Optional properties: | 12 | Optional properties: |
| 13 | - fsl,cd-internal : Indicate to use controller internal card detection | 13 | - fsl,cd-controller : Indicate to use controller internal card detection |
| 14 | - fsl,wp-internal : Indicate to use controller internal write protection | 14 | - fsl,wp-controller : Indicate to use controller internal write protection |
| 15 | 15 | ||
| 16 | Examples: | 16 | Examples: |
| 17 | 17 | ||
| @@ -19,8 +19,8 @@ esdhc@70004000 { | |||
| 19 | compatible = "fsl,imx51-esdhc"; | 19 | compatible = "fsl,imx51-esdhc"; |
| 20 | reg = <0x70004000 0x4000>; | 20 | reg = <0x70004000 0x4000>; |
| 21 | interrupts = <1>; | 21 | interrupts = <1>; |
| 22 | fsl,cd-internal; | 22 | fsl,cd-controller; |
| 23 | fsl,wp-internal; | 23 | fsl,wp-controller; |
| 24 | }; | 24 | }; |
| 25 | 25 | ||
| 26 | esdhc@70008000 { | 26 | esdhc@70008000 { |
diff --git a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt new file mode 100644 index 000000000000..f1421e2bbab7 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt | |||
| @@ -0,0 +1,31 @@ | |||
| 1 | PXA3xx NAND DT bindings | ||
| 2 | |||
| 3 | Required properties: | ||
| 4 | |||
| 5 | - compatible: Should be "marvell,pxa3xx-nand" | ||
| 6 | - reg: The register base for the controller | ||
| 7 | - interrupts: The interrupt to map | ||
| 8 | - #address-cells: Set to <1> if the node includes partitions | ||
| 9 | |||
| 10 | Optional properties: | ||
| 11 | |||
| 12 | - marvell,nand-enable-arbiter: Set to enable the bus arbiter | ||
| 13 | - marvell,nand-keep-config: Set to keep the NAND controller config as set | ||
| 14 | by the bootloader | ||
| 15 | - num-cs: Number of chipselect lines to usw | ||
| 16 | |||
| 17 | Example: | ||
| 18 | |||
| 19 | nand0: nand@43100000 { | ||
| 20 | compatible = "marvell,pxa3xx-nand"; | ||
| 21 | reg = <0x43100000 90>; | ||
| 22 | interrupts = <45>; | ||
| 23 | #address-cells = <1>; | ||
| 24 | |||
| 25 | marvell,nand-enable-arbiter; | ||
| 26 | marvell,nand-keep-config; | ||
| 27 | num-cs = <1>; | ||
| 28 | |||
| 29 | /* partitions (optional) */ | ||
| 30 | }; | ||
| 31 | |||
diff --git a/Documentation/devicetree/bindings/rtc/pxa-rtc.txt b/Documentation/devicetree/bindings/rtc/pxa-rtc.txt new file mode 100644 index 000000000000..8c6672a1b7d7 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/pxa-rtc.txt | |||
| @@ -0,0 +1,14 @@ | |||
| 1 | * PXA RTC | ||
| 2 | |||
| 3 | PXA specific RTC driver. | ||
| 4 | |||
| 5 | Required properties: | ||
| 6 | - compatible : Should be "marvell,pxa-rtc" | ||
| 7 | |||
| 8 | Examples: | ||
| 9 | |||
| 10 | rtc@40900000 { | ||
| 11 | compatible = "marvell,pxa-rtc"; | ||
| 12 | reg = <0x40900000 0x3c>; | ||
| 13 | interrupts = <30 31>; | ||
| 14 | }; | ||
diff --git a/Documentation/watchdog/src/watchdog-test.c b/Documentation/watchdog/src/watchdog-test.c index 73ff5cc93e05..3da822967ee0 100644 --- a/Documentation/watchdog/src/watchdog-test.c +++ b/Documentation/watchdog/src/watchdog-test.c | |||
| @@ -31,7 +31,7 @@ static void keep_alive(void) | |||
| 31 | * or "-e" to enable the card. | 31 | * or "-e" to enable the card. |
| 32 | */ | 32 | */ |
| 33 | 33 | ||
| 34 | void term(int sig) | 34 | static void term(int sig) |
| 35 | { | 35 | { |
| 36 | close(fd); | 36 | close(fd); |
| 37 | fprintf(stderr, "Stopping watchdog ticks...\n"); | 37 | fprintf(stderr, "Stopping watchdog ticks...\n"); |
| @@ -1,7 +1,7 @@ | |||
| 1 | VERSION = 3 | 1 | VERSION = 3 |
| 2 | PATCHLEVEL = 6 | 2 | PATCHLEVEL = 6 |
| 3 | SUBLEVEL = 0 | 3 | SUBLEVEL = 0 |
| 4 | EXTRAVERSION = -rc3 | 4 | EXTRAVERSION = -rc4 |
| 5 | NAME = Saber-toothed Squirrel | 5 | NAME = Saber-toothed Squirrel |
| 6 | 6 | ||
| 7 | # *DOCUMENTATION* | 7 | # *DOCUMENTATION* |
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6d6e18fee9fe..93d2fab25b30 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
| @@ -273,7 +273,7 @@ config ARCH_INTEGRATOR | |||
| 273 | select ARM_AMBA | 273 | select ARM_AMBA |
| 274 | select ARCH_HAS_CPUFREQ | 274 | select ARCH_HAS_CPUFREQ |
| 275 | select COMMON_CLK | 275 | select COMMON_CLK |
| 276 | select CLK_VERSATILE | 276 | select COMMON_CLK_VERSATILE |
| 277 | select HAVE_TCM | 277 | select HAVE_TCM |
| 278 | select ICST | 278 | select ICST |
| 279 | select GENERIC_CLOCKEVENTS | 279 | select GENERIC_CLOCKEVENTS |
| @@ -289,13 +289,12 @@ config ARCH_INTEGRATOR | |||
| 289 | config ARCH_REALVIEW | 289 | config ARCH_REALVIEW |
| 290 | bool "ARM Ltd. RealView family" | 290 | bool "ARM Ltd. RealView family" |
| 291 | select ARM_AMBA | 291 | select ARM_AMBA |
| 292 | select CLKDEV_LOOKUP | 292 | select COMMON_CLK |
| 293 | select HAVE_MACH_CLKDEV | 293 | select COMMON_CLK_VERSATILE |
| 294 | select ICST | 294 | select ICST |
| 295 | select GENERIC_CLOCKEVENTS | 295 | select GENERIC_CLOCKEVENTS |
| 296 | select ARCH_WANT_OPTIONAL_GPIOLIB | 296 | select ARCH_WANT_OPTIONAL_GPIOLIB |
| 297 | select PLAT_VERSATILE | 297 | select PLAT_VERSATILE |
| 298 | select PLAT_VERSATILE_CLOCK | ||
| 299 | select PLAT_VERSATILE_CLCD | 298 | select PLAT_VERSATILE_CLCD |
| 300 | select ARM_TIMER_SP804 | 299 | select ARM_TIMER_SP804 |
| 301 | select GPIO_PL061 if GPIOLIB | 300 | select GPIO_PL061 if GPIOLIB |
| @@ -413,7 +412,7 @@ config ARCH_PRIMA2 | |||
| 413 | select NO_IOPORT | 412 | select NO_IOPORT |
| 414 | select ARCH_REQUIRE_GPIOLIB | 413 | select ARCH_REQUIRE_GPIOLIB |
| 415 | select GENERIC_CLOCKEVENTS | 414 | select GENERIC_CLOCKEVENTS |
| 416 | select CLKDEV_LOOKUP | 415 | select COMMON_CLK |
| 417 | select GENERIC_IRQ_CHIP | 416 | select GENERIC_IRQ_CHIP |
| 418 | select MIGHT_HAVE_CACHE_L2X0 | 417 | select MIGHT_HAVE_CACHE_L2X0 |
| 419 | select PINCTRL | 418 | select PINCTRL |
| @@ -2144,6 +2143,7 @@ source "drivers/cpufreq/Kconfig" | |||
| 2144 | config CPU_FREQ_IMX | 2143 | config CPU_FREQ_IMX |
| 2145 | tristate "CPUfreq driver for i.MX CPUs" | 2144 | tristate "CPUfreq driver for i.MX CPUs" |
| 2146 | depends on ARCH_MXC && CPU_FREQ | 2145 | depends on ARCH_MXC && CPU_FREQ |
| 2146 | select CPU_FREQ_TABLE | ||
| 2147 | help | 2147 | help |
| 2148 | This enables the CPUfreq driver for i.MX CPUs. | 2148 | This enables the CPUfreq driver for i.MX CPUs. |
| 2149 | 2149 | ||
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 59509c48d7e5..bd0cff3f808c 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi | |||
| @@ -154,5 +154,10 @@ | |||
| 154 | #size-cells = <0>; | 154 | #size-cells = <0>; |
| 155 | ti,hwmods = "i2c3"; | 155 | ti,hwmods = "i2c3"; |
| 156 | }; | 156 | }; |
| 157 | |||
| 158 | wdt2: wdt@44e35000 { | ||
| 159 | compatible = "ti,omap3-wdt"; | ||
| 160 | ti,hwmods = "wd_timer2"; | ||
| 161 | }; | ||
| 157 | }; | 162 | }; |
| 158 | }; | 163 | }; |
diff --git a/arch/arm/boot/dts/ea3250.dts b/arch/arm/boot/dts/ea3250.dts index d79b28d9c963..a4ba31b23c88 100644 --- a/arch/arm/boot/dts/ea3250.dts +++ b/arch/arm/boot/dts/ea3250.dts | |||
| @@ -166,9 +166,116 @@ | |||
| 166 | #size-cells = <0>; | 166 | #size-cells = <0>; |
| 167 | autorepeat; | 167 | autorepeat; |
| 168 | button@21 { | 168 | button@21 { |
| 169 | label = "GPIO Key UP"; | 169 | label = "Interrupt Key"; |
| 170 | linux,code = <103>; | 170 | linux,code = <103>; |
| 171 | gpios = <&gpio 4 1 0>; /* GPI_P3 1 */ | 171 | gpios = <&gpio 4 1 0>; /* GPI_P3 1 */ |
| 172 | }; | 172 | }; |
| 173 | key1 { | ||
| 174 | label = "KEY1"; | ||
| 175 | linux,code = <1>; | ||
| 176 | gpios = <&pca9532 0 0>; | ||
| 177 | }; | ||
| 178 | key2 { | ||
| 179 | label = "KEY2"; | ||
| 180 | linux,code = <2>; | ||
| 181 | gpios = <&pca9532 1 0>; | ||
| 182 | }; | ||
| 183 | key3 { | ||
| 184 | label = "KEY3"; | ||
| 185 | linux,code = <3>; | ||
| 186 | gpios = <&pca9532 2 0>; | ||
| 187 | }; | ||
| 188 | key4 { | ||
| 189 | label = "KEY4"; | ||
| 190 | linux,code = <4>; | ||
| 191 | gpios = <&pca9532 3 0>; | ||
| 192 | }; | ||
| 193 | joy0 { | ||
| 194 | label = "Joystick Key 0"; | ||
| 195 | linux,code = <10>; | ||
| 196 | gpios = <&gpio 2 0 0>; /* P2.0 */ | ||
| 197 | }; | ||
| 198 | joy1 { | ||
| 199 | label = "Joystick Key 1"; | ||
| 200 | linux,code = <11>; | ||
| 201 | gpios = <&gpio 2 1 0>; /* P2.1 */ | ||
| 202 | }; | ||
| 203 | joy2 { | ||
| 204 | label = "Joystick Key 2"; | ||
| 205 | linux,code = <12>; | ||
| 206 | gpios = <&gpio 2 2 0>; /* P2.2 */ | ||
| 207 | }; | ||
| 208 | joy3 { | ||
| 209 | label = "Joystick Key 3"; | ||
| 210 | linux,code = <13>; | ||
| 211 | gpios = <&gpio 2 3 0>; /* P2.3 */ | ||
| 212 | }; | ||
| 213 | joy4 { | ||
| 214 | label = "Joystick Key 4"; | ||
| 215 | linux,code = <14>; | ||
| 216 | gpios = <&gpio 2 4 0>; /* P2.4 */ | ||
| 217 | }; | ||
| 218 | }; | ||
| 219 | |||
| 220 | leds { | ||
| 221 | compatible = "gpio-leds"; | ||
| 222 | |||
| 223 | /* LEDs on OEM Board */ | ||
| 224 | |||
| 225 | led1 { | ||
| 226 | gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */ | ||
| 227 | linux,default-trigger = "timer"; | ||
| 228 | default-state = "off"; | ||
| 229 | }; | ||
| 230 | |||
| 231 | led2 { | ||
| 232 | gpios = <&gpio 2 10 1>; /* P2.10, active low */ | ||
| 233 | default-state = "off"; | ||
| 234 | }; | ||
| 235 | |||
| 236 | led3 { | ||
| 237 | gpios = <&gpio 2 11 1>; /* P2.11, active low */ | ||
| 238 | default-state = "off"; | ||
| 239 | }; | ||
| 240 | |||
| 241 | led4 { | ||
| 242 | gpios = <&gpio 2 12 1>; /* P2.12, active low */ | ||
| 243 | default-state = "off"; | ||
| 244 | }; | ||
| 245 | |||
| 246 | /* LEDs on Base Board */ | ||
| 247 | |||
| 248 | lede1 { | ||
| 249 | gpios = <&pca9532 8 0>; | ||
| 250 | default-state = "off"; | ||
| 251 | }; | ||
| 252 | lede2 { | ||
| 253 | gpios = <&pca9532 9 0>; | ||
| 254 | default-state = "off"; | ||
| 255 | }; | ||
| 256 | lede3 { | ||
| 257 | gpios = <&pca9532 10 0>; | ||
| 258 | default-state = "off"; | ||
| 259 | }; | ||
| 260 | lede4 { | ||
| 261 | gpios = <&pca9532 11 0>; | ||
| 262 | default-state = "off"; | ||
| 263 | }; | ||
| 264 | lede5 { | ||
| 265 | gpios = <&pca9532 12 0>; | ||
| 266 | default-state = "off"; | ||
| 267 | }; | ||
| 268 | lede6 { | ||
| 269 | gpios = <&pca9532 13 0>; | ||
| 270 | default-state = "off"; | ||
| 271 | }; | ||
| 272 | lede7 { | ||
| 273 | gpios = <&pca9532 14 0>; | ||
| 274 | default-state = "off"; | ||
| 275 | }; | ||
| 276 | lede8 { | ||
| 277 | gpios = <&pca9532 15 0>; | ||
| 278 | default-state = "off"; | ||
| 279 | }; | ||
| 173 | }; | 280 | }; |
| 174 | }; | 281 | }; |
diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts index e3486f486b40..035c13f9d3c0 100644 --- a/arch/arm/boot/dts/imx23-evk.dts +++ b/arch/arm/boot/dts/imx23-evk.dts | |||
| @@ -42,12 +42,13 @@ | |||
| 42 | pinctrl-names = "default"; | 42 | pinctrl-names = "default"; |
| 43 | pinctrl-0 = <&hog_pins_a>; | 43 | pinctrl-0 = <&hog_pins_a>; |
| 44 | 44 | ||
| 45 | hog_pins_a: hog-gpios@0 { | 45 | hog_pins_a: hog@0 { |
| 46 | reg = <0>; | 46 | reg = <0>; |
| 47 | fsl,pinmux-ids = < | 47 | fsl,pinmux-ids = < |
| 48 | 0x1123 /* MX23_PAD_LCD_RESET__GPIO_1_18 */ | 48 | 0x1123 /* MX23_PAD_LCD_RESET__GPIO_1_18 */ |
| 49 | 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */ | 49 | 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */ |
| 50 | 0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */ | 50 | 0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */ |
| 51 | 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */ | ||
| 51 | >; | 52 | >; |
| 52 | fsl,drive-strength = <0>; | 53 | fsl,drive-strength = <0>; |
| 53 | fsl,voltage = <1>; | 54 | fsl,voltage = <1>; |
diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts index 20912b1d8893..711dcf5742b6 100644 --- a/arch/arm/boot/dts/imx23-olinuxino.dts +++ b/arch/arm/boot/dts/imx23-olinuxino.dts | |||
| @@ -31,6 +31,21 @@ | |||
| 31 | bus-width = <4>; | 31 | bus-width = <4>; |
| 32 | status = "okay"; | 32 | status = "okay"; |
| 33 | }; | 33 | }; |
| 34 | |||
| 35 | pinctrl@80018000 { | ||
| 36 | pinctrl-names = "default"; | ||
| 37 | pinctrl-0 = <&hog_pins_a>; | ||
| 38 | |||
| 39 | hog_pins_a: hog@0 { | ||
| 40 | reg = <0>; | ||
| 41 | fsl,pinmux-ids = < | ||
| 42 | 0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */ | ||
| 43 | >; | ||
| 44 | fsl,drive-strength = <0>; | ||
| 45 | fsl,voltage = <1>; | ||
| 46 | fsl,pull-up = <0>; | ||
| 47 | }; | ||
| 48 | }; | ||
| 34 | }; | 49 | }; |
| 35 | 50 | ||
| 36 | apbx@80040000 { | 51 | apbx@80040000 { |
| @@ -39,6 +54,22 @@ | |||
| 39 | pinctrl-0 = <&duart_pins_a>; | 54 | pinctrl-0 = <&duart_pins_a>; |
| 40 | status = "okay"; | 55 | status = "okay"; |
| 41 | }; | 56 | }; |
| 57 | |||
| 58 | auart0: serial@8006c000 { | ||
| 59 | pinctrl-names = "default"; | ||
| 60 | pinctrl-0 = <&auart0_2pins_a>; | ||
| 61 | status = "okay"; | ||
| 62 | }; | ||
| 63 | }; | ||
| 64 | }; | ||
| 65 | |||
| 66 | leds { | ||
| 67 | compatible = "gpio-leds"; | ||
| 68 | |||
| 69 | user { | ||
| 70 | label = "green"; | ||
| 71 | gpios = <&gpio2 1 0>; | ||
| 72 | linux,default-trigger = "default-on"; | ||
| 42 | }; | 73 | }; |
| 43 | }; | 74 | }; |
| 44 | }; | 75 | }; |
diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/imx23-stmp378x_devb.dts index 757a327ff3e8..85c3864b6a56 100644 --- a/arch/arm/boot/dts/imx23-stmp378x_devb.dts +++ b/arch/arm/boot/dts/imx23-stmp378x_devb.dts | |||
| @@ -36,7 +36,7 @@ | |||
| 36 | pinctrl-names = "default"; | 36 | pinctrl-names = "default"; |
| 37 | pinctrl-0 = <&hog_pins_a>; | 37 | pinctrl-0 = <&hog_pins_a>; |
| 38 | 38 | ||
| 39 | hog_pins_a: hog-gpios@0 { | 39 | hog_pins_a: hog@0 { |
| 40 | reg = <0>; | 40 | reg = <0>; |
| 41 | fsl,pinmux-ids = < | 41 | fsl,pinmux-ids = < |
| 42 | 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */ | 42 | 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */ |
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index e6138310e5ce..9d0e803e3eca 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi | |||
| @@ -52,6 +52,7 @@ | |||
| 52 | dma-apbh@80004000 { | 52 | dma-apbh@80004000 { |
| 53 | compatible = "fsl,imx23-dma-apbh"; | 53 | compatible = "fsl,imx23-dma-apbh"; |
| 54 | reg = <0x80004000 0x2000>; | 54 | reg = <0x80004000 0x2000>; |
| 55 | clocks = <&clks 15>; | ||
| 55 | }; | 56 | }; |
| 56 | 57 | ||
| 57 | ecc@80008000 { | 58 | ecc@80008000 { |
| @@ -67,6 +68,7 @@ | |||
| 67 | reg-names = "gpmi-nand", "bch"; | 68 | reg-names = "gpmi-nand", "bch"; |
| 68 | interrupts = <13>, <56>; | 69 | interrupts = <13>, <56>; |
| 69 | interrupt-names = "gpmi-dma", "bch"; | 70 | interrupt-names = "gpmi-dma", "bch"; |
| 71 | clocks = <&clks 34>; | ||
| 70 | fsl,gpmi-dma-channel = <4>; | 72 | fsl,gpmi-dma-channel = <4>; |
| 71 | status = "disabled"; | 73 | status = "disabled"; |
| 72 | }; | 74 | }; |
| @@ -74,6 +76,7 @@ | |||
| 74 | ssp0: ssp@80010000 { | 76 | ssp0: ssp@80010000 { |
| 75 | reg = <0x80010000 0x2000>; | 77 | reg = <0x80010000 0x2000>; |
| 76 | interrupts = <15 14>; | 78 | interrupts = <15 14>; |
| 79 | clocks = <&clks 33>; | ||
| 77 | fsl,ssp-dma-channel = <1>; | 80 | fsl,ssp-dma-channel = <1>; |
| 78 | status = "disabled"; | 81 | status = "disabled"; |
| 79 | }; | 82 | }; |
| @@ -140,6 +143,17 @@ | |||
| 140 | fsl,pull-up = <0>; | 143 | fsl,pull-up = <0>; |
| 141 | }; | 144 | }; |
| 142 | 145 | ||
| 146 | auart0_2pins_a: auart0-2pins@0 { | ||
| 147 | reg = <0>; | ||
| 148 | fsl,pinmux-ids = < | ||
| 149 | 0x01e2 /* MX23_PAD_I2C_SCL__AUART1_TX */ | ||
| 150 | 0x01f2 /* MX23_PAD_I2C_SDA__AUART1_RX */ | ||
| 151 | >; | ||
| 152 | fsl,drive-strength = <0>; | ||
| 153 | fsl,voltage = <1>; | ||
| 154 | fsl,pull-up = <0>; | ||
| 155 | }; | ||
| 156 | |||
| 143 | gpmi_pins_a: gpmi-nand@0 { | 157 | gpmi_pins_a: gpmi-nand@0 { |
| 144 | reg = <0>; | 158 | reg = <0>; |
| 145 | fsl,pinmux-ids = < | 159 | fsl,pinmux-ids = < |
| @@ -183,7 +197,6 @@ | |||
| 183 | 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */ | 197 | 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */ |
| 184 | 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */ | 198 | 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */ |
| 185 | 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */ | 199 | 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */ |
| 186 | 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */ | ||
| 187 | 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */ | 200 | 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */ |
| 188 | >; | 201 | >; |
| 189 | fsl,drive-strength = <1>; | 202 | fsl,drive-strength = <1>; |
| @@ -280,6 +293,7 @@ | |||
| 280 | dma-apbx@80024000 { | 293 | dma-apbx@80024000 { |
| 281 | compatible = "fsl,imx23-dma-apbx"; | 294 | compatible = "fsl,imx23-dma-apbx"; |
| 282 | reg = <0x80024000 0x2000>; | 295 | reg = <0x80024000 0x2000>; |
| 296 | clocks = <&clks 16>; | ||
| 283 | }; | 297 | }; |
| 284 | 298 | ||
| 285 | dcp@80028000 { | 299 | dcp@80028000 { |
| @@ -306,12 +320,14 @@ | |||
| 306 | compatible = "fsl,imx23-lcdif"; | 320 | compatible = "fsl,imx23-lcdif"; |
| 307 | reg = <0x80030000 2000>; | 321 | reg = <0x80030000 2000>; |
| 308 | interrupts = <46 45>; | 322 | interrupts = <46 45>; |
| 323 | clocks = <&clks 38>; | ||
| 309 | status = "disabled"; | 324 | status = "disabled"; |
| 310 | }; | 325 | }; |
| 311 | 326 | ||
| 312 | ssp1: ssp@80034000 { | 327 | ssp1: ssp@80034000 { |
| 313 | reg = <0x80034000 0x2000>; | 328 | reg = <0x80034000 0x2000>; |
| 314 | interrupts = <2 20>; | 329 | interrupts = <2 20>; |
| 330 | clocks = <&clks 33>; | ||
| 315 | fsl,ssp-dma-channel = <2>; | 331 | fsl,ssp-dma-channel = <2>; |
| 316 | status = "disabled"; | 332 | status = "disabled"; |
| 317 | }; | 333 | }; |
| @@ -329,9 +345,10 @@ | |||
| 329 | reg = <0x80040000 0x40000>; | 345 | reg = <0x80040000 0x40000>; |
| 330 | ranges; | 346 | ranges; |
| 331 | 347 | ||
| 332 | clkctl@80040000 { | 348 | clks: clkctrl@80040000 { |
| 349 | compatible = "fsl,imx23-clkctrl"; | ||
| 333 | reg = <0x80040000 0x2000>; | 350 | reg = <0x80040000 0x2000>; |
| 334 | status = "disabled"; | 351 | #clock-cells = <1>; |
| 335 | }; | 352 | }; |
| 336 | 353 | ||
| 337 | saif0: saif@80042000 { | 354 | saif0: saif@80042000 { |
| @@ -383,6 +400,7 @@ | |||
| 383 | pwm: pwm@80064000 { | 400 | pwm: pwm@80064000 { |
| 384 | compatible = "fsl,imx23-pwm"; | 401 | compatible = "fsl,imx23-pwm"; |
| 385 | reg = <0x80064000 0x2000>; | 402 | reg = <0x80064000 0x2000>; |
| 403 | clocks = <&clks 30>; | ||
| 386 | #pwm-cells = <2>; | 404 | #pwm-cells = <2>; |
| 387 | fsl,pwm-number = <5>; | 405 | fsl,pwm-number = <5>; |
| 388 | status = "disabled"; | 406 | status = "disabled"; |
| @@ -397,6 +415,7 @@ | |||
| 397 | compatible = "fsl,imx23-auart"; | 415 | compatible = "fsl,imx23-auart"; |
| 398 | reg = <0x8006c000 0x2000>; | 416 | reg = <0x8006c000 0x2000>; |
| 399 | interrupts = <24 25 23>; | 417 | interrupts = <24 25 23>; |
| 418 | clocks = <&clks 32>; | ||
| 400 | status = "disabled"; | 419 | status = "disabled"; |
| 401 | }; | 420 | }; |
| 402 | 421 | ||
| @@ -404,6 +423,7 @@ | |||
| 404 | compatible = "fsl,imx23-auart"; | 423 | compatible = "fsl,imx23-auart"; |
| 405 | reg = <0x8006e000 0x2000>; | 424 | reg = <0x8006e000 0x2000>; |
| 406 | interrupts = <59 60 58>; | 425 | interrupts = <59 60 58>; |
| 426 | clocks = <&clks 32>; | ||
| 407 | status = "disabled"; | 427 | status = "disabled"; |
| 408 | }; | 428 | }; |
| 409 | 429 | ||
| @@ -411,6 +431,8 @@ | |||
| 411 | compatible = "arm,pl011", "arm,primecell"; | 431 | compatible = "arm,pl011", "arm,primecell"; |
| 412 | reg = <0x80070000 0x2000>; | 432 | reg = <0x80070000 0x2000>; |
| 413 | interrupts = <0>; | 433 | interrupts = <0>; |
| 434 | clocks = <&clks 32>, <&clks 16>; | ||
| 435 | clock-names = "uart", "apb_pclk"; | ||
| 414 | status = "disabled"; | 436 | status = "disabled"; |
| 415 | }; | 437 | }; |
| 416 | 438 | ||
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts index 2b0ff60247a4..777caa33cd85 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore.dts | |||
| @@ -23,10 +23,6 @@ | |||
| 23 | soc { | 23 | soc { |
| 24 | aipi@10000000 { /* aipi */ | 24 | aipi@10000000 { /* aipi */ |
| 25 | 25 | ||
| 26 | wdog@10002000 { | ||
| 27 | status = "okay"; | ||
| 28 | }; | ||
| 29 | |||
| 30 | serial@1000a000 { | 26 | serial@1000a000 { |
| 31 | fsl,uart-has-rtscts; | 27 | fsl,uart-has-rtscts; |
| 32 | status = "okay"; | 28 | status = "okay"; |
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index 5303ab680a34..3e54f1498841 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi | |||
| @@ -62,7 +62,6 @@ | |||
| 62 | compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; | 62 | compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; |
| 63 | reg = <0x10002000 0x4000>; | 63 | reg = <0x10002000 0x4000>; |
| 64 | interrupts = <27>; | 64 | interrupts = <27>; |
| 65 | status = "disabled"; | ||
| 66 | }; | 65 | }; |
| 67 | 66 | ||
| 68 | uart1: serial@1000a000 { | 67 | uart1: serial@1000a000 { |
diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts index b383417a558f..5171667a7763 100644 --- a/arch/arm/boot/dts/imx28-apx4devkit.dts +++ b/arch/arm/boot/dts/imx28-apx4devkit.dts | |||
| @@ -37,7 +37,7 @@ | |||
| 37 | pinctrl-names = "default"; | 37 | pinctrl-names = "default"; |
| 38 | pinctrl-0 = <&hog_pins_a>; | 38 | pinctrl-0 = <&hog_pins_a>; |
| 39 | 39 | ||
| 40 | hog_pins_a: hog-gpios@0 { | 40 | hog_pins_a: hog@0 { |
| 41 | reg = <0>; | 41 | reg = <0>; |
| 42 | fsl,pinmux-ids = < | 42 | fsl,pinmux-ids = < |
| 43 | 0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */ | 43 | 0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */ |
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts new file mode 100644 index 000000000000..05c892e931e3 --- /dev/null +++ b/arch/arm/boot/dts/imx28-cfa10049.dts | |||
| @@ -0,0 +1,99 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2012 Free Electrons | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | /* | ||
| 13 | * The CFA-10049 is an expansion board for the CFA-10036 module, thus we | ||
| 14 | * need to include the CFA-10036 DTS. | ||
| 15 | */ | ||
| 16 | /include/ "imx28-cfa10036.dts" | ||
| 17 | |||
| 18 | / { | ||
| 19 | model = "Crystalfontz CFA-10049 Board"; | ||
| 20 | compatible = "crystalfontz,cfa10049", "crystalfontz,cfa10036", "fsl,imx28"; | ||
| 21 | |||
| 22 | apb@80000000 { | ||
| 23 | apbh@80000000 { | ||
| 24 | pinctrl@80018000 { | ||
| 25 | spi3_pins_cfa10049: spi3-cfa10049@0 { | ||
| 26 | reg = <0>; | ||
| 27 | fsl,pinmux-ids = < | ||
| 28 | 0x0181 /* MX28_PAD_GPMI_RDN__SSP3_SCK */ | ||
| 29 | 0x01c1 /* MX28_PAD_GPMI_RESETN__SSP3_CMD */ | ||
| 30 | 0x0111 /* MX28_PAD_GPMI_CE1N__SSP3_D3 */ | ||
| 31 | 0x01a2 /* MX28_PAD_GPMI_ALE__SSP3_D4 */ | ||
| 32 | >; | ||
| 33 | fsl,drive-strength = <1>; | ||
| 34 | fsl,voltage = <1>; | ||
| 35 | fsl,pull-up = <1>; | ||
| 36 | }; | ||
| 37 | }; | ||
| 38 | |||
| 39 | ssp3: ssp@80016000 { | ||
| 40 | compatible = "fsl,imx28-spi"; | ||
| 41 | pinctrl-names = "default"; | ||
| 42 | pinctrl-0 = <&spi3_pins_cfa10049>; | ||
| 43 | status = "okay"; | ||
| 44 | |||
| 45 | gpio5: gpio5@0 { | ||
| 46 | compatible = "fairchild,74hc595"; | ||
| 47 | gpio-controller; | ||
| 48 | #gpio-cells = <2>; | ||
| 49 | reg = <0>; | ||
| 50 | registers-number = <2>; | ||
| 51 | spi-max-frequency = <100000>; | ||
| 52 | }; | ||
| 53 | |||
| 54 | gpio6: gpio6@1 { | ||
| 55 | compatible = "fairchild,74hc595"; | ||
| 56 | gpio-controller; | ||
| 57 | #gpio-cells = <2>; | ||
| 58 | reg = <1>; | ||
| 59 | registers-number = <4>; | ||
| 60 | spi-max-frequency = <100000>; | ||
| 61 | }; | ||
| 62 | |||
| 63 | }; | ||
| 64 | }; | ||
| 65 | |||
| 66 | apbx@80040000 { | ||
| 67 | i2c1: i2c@8005a000 { | ||
| 68 | pinctrl-names = "default"; | ||
| 69 | pinctrl-0 = <&i2c1_pins_a>; | ||
| 70 | status = "okay"; | ||
| 71 | }; | ||
| 72 | |||
| 73 | usbphy1: usbphy@8007e000 { | ||
| 74 | status = "okay"; | ||
| 75 | }; | ||
| 76 | }; | ||
| 77 | }; | ||
| 78 | |||
| 79 | ahb@80080000 { | ||
| 80 | usb1: usb@80090000 { | ||
| 81 | vbus-supply = <®_usb1_vbus>; | ||
| 82 | pinctrl-0 = <&usbphy1_pins_a>; | ||
| 83 | pinctrl-names = "default"; | ||
| 84 | status = "okay"; | ||
| 85 | }; | ||
| 86 | }; | ||
| 87 | |||
| 88 | regulators { | ||
| 89 | compatible = "simple-bus"; | ||
| 90 | |||
| 91 | reg_usb1_vbus: usb1_vbus { | ||
| 92 | compatible = "regulator-fixed"; | ||
| 93 | regulator-name = "usb1_vbus"; | ||
| 94 | regulator-min-microvolt = <5000000>; | ||
| 95 | regulator-max-microvolt = <5000000>; | ||
| 96 | gpio = <&gpio0 7 1>; | ||
| 97 | }; | ||
| 98 | }; | ||
| 99 | }; | ||
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index 773c0e84d1fb..a0ad71ca3a44 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts | |||
| @@ -46,11 +46,28 @@ | |||
| 46 | wp-gpios = <&gpio0 28 0>; | 46 | wp-gpios = <&gpio0 28 0>; |
| 47 | }; | 47 | }; |
| 48 | 48 | ||
| 49 | ssp2: ssp@80014000 { | ||
| 50 | #address-cells = <1>; | ||
| 51 | #size-cells = <0>; | ||
| 52 | compatible = "fsl,imx28-spi"; | ||
| 53 | pinctrl-names = "default"; | ||
| 54 | pinctrl-0 = <&spi2_pins_a>; | ||
| 55 | status = "okay"; | ||
| 56 | |||
| 57 | flash: m25p80@0 { | ||
| 58 | #address-cells = <1>; | ||
| 59 | #size-cells = <1>; | ||
| 60 | compatible = "sst,sst25vf016b"; | ||
| 61 | spi-max-frequency = <40000000>; | ||
| 62 | reg = <0>; | ||
| 63 | }; | ||
| 64 | }; | ||
| 65 | |||
| 49 | pinctrl@80018000 { | 66 | pinctrl@80018000 { |
| 50 | pinctrl-names = "default"; | 67 | pinctrl-names = "default"; |
| 51 | pinctrl-0 = <&hog_pins_a>; | 68 | pinctrl-0 = <&hog_pins_a>; |
| 52 | 69 | ||
| 53 | hog_pins_a: hog-gpios@0 { | 70 | hog_pins_a: hog@0 { |
| 54 | reg = <0>; | 71 | reg = <0>; |
| 55 | fsl,pinmux-ids = < | 72 | fsl,pinmux-ids = < |
| 56 | 0x20d3 /* MX28_PAD_SSP1_CMD__GPIO_2_13 */ | 73 | 0x20d3 /* MX28_PAD_SSP1_CMD__GPIO_2_13 */ |
| @@ -128,6 +145,10 @@ | |||
| 128 | status = "okay"; | 145 | status = "okay"; |
| 129 | }; | 146 | }; |
| 130 | 147 | ||
| 148 | lradc@80050000 { | ||
| 149 | status = "okay"; | ||
| 150 | }; | ||
| 151 | |||
| 131 | i2c0: i2c@80058000 { | 152 | i2c0: i2c@80058000 { |
| 132 | pinctrl-names = "default"; | 153 | pinctrl-names = "default"; |
| 133 | pinctrl-0 = <&i2c0_pins_a>; | 154 | pinctrl-0 = <&i2c0_pins_a>; |
| @@ -140,6 +161,12 @@ | |||
| 140 | VDDIO-supply = <®_3p3v>; | 161 | VDDIO-supply = <®_3p3v>; |
| 141 | 162 | ||
| 142 | }; | 163 | }; |
| 164 | |||
| 165 | at24@51 { | ||
| 166 | compatible = "at24,24c32"; | ||
| 167 | pagesize = <32>; | ||
| 168 | reg = <0x51>; | ||
| 169 | }; | ||
| 143 | }; | 170 | }; |
| 144 | 171 | ||
| 145 | pwm: pwm@80064000 { | 172 | pwm: pwm@80064000 { |
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts index 183a3fd2d859..3bab6b00c52d 100644 --- a/arch/arm/boot/dts/imx28-m28evk.dts +++ b/arch/arm/boot/dts/imx28-m28evk.dts | |||
| @@ -23,6 +23,8 @@ | |||
| 23 | apb@80000000 { | 23 | apb@80000000 { |
| 24 | apbh@80000000 { | 24 | apbh@80000000 { |
| 25 | gpmi-nand@8000c000 { | 25 | gpmi-nand@8000c000 { |
| 26 | #address-cells = <1>; | ||
| 27 | #size-cells = <1>; | ||
| 26 | pinctrl-names = "default"; | 28 | pinctrl-names = "default"; |
| 27 | pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; | 29 | pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; |
| 28 | status = "okay"; | 30 | status = "okay"; |
| @@ -61,19 +63,40 @@ | |||
| 61 | &mmc0_cd_cfg | 63 | &mmc0_cd_cfg |
| 62 | &mmc0_sck_cfg>; | 64 | &mmc0_sck_cfg>; |
| 63 | bus-width = <8>; | 65 | bus-width = <8>; |
| 64 | wp-gpios = <&gpio3 10 1>; | 66 | wp-gpios = <&gpio3 10 0>; |
| 67 | vmmc-supply = <®_vddio_sd0>; | ||
| 65 | status = "okay"; | 68 | status = "okay"; |
| 66 | }; | 69 | }; |
| 67 | 70 | ||
| 71 | ssp2: ssp@80014000 { | ||
| 72 | #address-cells = <1>; | ||
| 73 | #size-cells = <0>; | ||
| 74 | compatible = "fsl,imx28-spi"; | ||
| 75 | pinctrl-names = "default"; | ||
| 76 | pinctrl-0 = <&spi2_pins_a>; | ||
| 77 | status = "okay"; | ||
| 78 | |||
| 79 | flash: m25p80@0 { | ||
| 80 | #address-cells = <1>; | ||
| 81 | #size-cells = <1>; | ||
| 82 | compatible = "m25p80"; | ||
| 83 | spi-max-frequency = <40000000>; | ||
| 84 | reg = <0>; | ||
| 85 | }; | ||
| 86 | }; | ||
| 87 | |||
| 68 | pinctrl@80018000 { | 88 | pinctrl@80018000 { |
| 69 | pinctrl-names = "default"; | 89 | pinctrl-names = "default"; |
| 70 | pinctrl-0 = <&hog_pins_a>; | 90 | pinctrl-0 = <&hog_pins_a>; |
| 71 | 91 | ||
| 72 | hog_pins_a: hog-gpios@0 { | 92 | hog_pins_a: hog@0 { |
| 73 | reg = <0>; | 93 | reg = <0>; |
| 74 | fsl,pinmux-ids = < | 94 | fsl,pinmux-ids = < |
| 95 | 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */ | ||
| 75 | 0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */ | 96 | 0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */ |
| 76 | 0x30b3 /* MX28_PAD_AUART2_RTS__GPIO_3_11 */ | 97 | 0x30b3 /* MX28_PAD_AUART2_RTS__GPIO_3_11 */ |
| 98 | 0x30c3 /* MX28_PAD_AUART3_RX__GPIO_3_12 */ | ||
| 99 | 0x30d3 /* MX28_PAD_AUART3_TX__GPIO_3_13 */ | ||
| 77 | >; | 100 | >; |
| 78 | fsl,drive-strength = <0>; | 101 | fsl,drive-strength = <0>; |
| 79 | fsl,voltage = <1>; | 102 | fsl,voltage = <1>; |
| @@ -129,6 +152,7 @@ | |||
| 129 | i2c0: i2c@80058000 { | 152 | i2c0: i2c@80058000 { |
| 130 | pinctrl-names = "default"; | 153 | pinctrl-names = "default"; |
| 131 | pinctrl-0 = <&i2c0_pins_a>; | 154 | pinctrl-0 = <&i2c0_pins_a>; |
| 155 | clock-frequency = <400000>; | ||
| 132 | status = "okay"; | 156 | status = "okay"; |
| 133 | 157 | ||
| 134 | sgtl5000: codec@0a { | 158 | sgtl5000: codec@0a { |
| @@ -151,32 +175,51 @@ | |||
| 151 | }; | 175 | }; |
| 152 | }; | 176 | }; |
| 153 | 177 | ||
| 178 | lradc@80050000 { | ||
| 179 | status = "okay"; | ||
| 180 | }; | ||
| 181 | |||
| 154 | duart: serial@80074000 { | 182 | duart: serial@80074000 { |
| 155 | pinctrl-names = "default"; | 183 | pinctrl-names = "default"; |
| 156 | pinctrl-0 = <&duart_pins_a>; | 184 | pinctrl-0 = <&duart_pins_a>; |
| 157 | status = "okay"; | 185 | status = "okay"; |
| 158 | }; | 186 | }; |
| 159 | 187 | ||
| 160 | auart0: serial@8006a000 { | 188 | usbphy0: usbphy@8007c000 { |
| 161 | pinctrl-names = "default"; | ||
| 162 | pinctrl-0 = <&auart0_2pins_a>; | ||
| 163 | status = "okay"; | 189 | status = "okay"; |
| 164 | }; | 190 | }; |
| 165 | 191 | ||
| 166 | auart3: serial@80070000 { | 192 | usbphy1: usbphy@8007e000 { |
| 193 | status = "okay"; | ||
| 194 | }; | ||
| 195 | |||
| 196 | auart0: serial@8006a000 { | ||
| 167 | pinctrl-names = "default"; | 197 | pinctrl-names = "default"; |
| 168 | pinctrl-0 = <&auart3_pins_a>; | 198 | pinctrl-0 = <&auart0_2pins_a>; |
| 169 | status = "okay"; | 199 | status = "okay"; |
| 170 | }; | 200 | }; |
| 171 | }; | 201 | }; |
| 172 | }; | 202 | }; |
| 173 | 203 | ||
| 174 | ahb@80080000 { | 204 | ahb@80080000 { |
| 205 | usb0: usb@80080000 { | ||
| 206 | vbus-supply = <®_usb0_vbus>; | ||
| 207 | pinctrl-names = "default"; | ||
| 208 | pinctrl-0 = <&usbphy0_pins_a>; | ||
| 209 | status = "okay"; | ||
| 210 | }; | ||
| 211 | |||
| 212 | usb1: usb@80090000 { | ||
| 213 | vbus-supply = <®_usb1_vbus>; | ||
| 214 | pinctrl-names = "default"; | ||
| 215 | pinctrl-0 = <&usbphy1_pins_a>; | ||
| 216 | status = "okay"; | ||
| 217 | }; | ||
| 218 | |||
| 175 | mac0: ethernet@800f0000 { | 219 | mac0: ethernet@800f0000 { |
| 176 | phy-mode = "rmii"; | 220 | phy-mode = "rmii"; |
| 177 | pinctrl-names = "default"; | 221 | pinctrl-names = "default"; |
| 178 | pinctrl-0 = <&mac0_pins_a>; | 222 | pinctrl-0 = <&mac0_pins_a>; |
| 179 | phy-reset-gpios = <&gpio3 11 0>; | ||
| 180 | status = "okay"; | 223 | status = "okay"; |
| 181 | }; | 224 | }; |
| 182 | 225 | ||
| @@ -198,6 +241,30 @@ | |||
| 198 | regulator-max-microvolt = <3300000>; | 241 | regulator-max-microvolt = <3300000>; |
| 199 | regulator-always-on; | 242 | regulator-always-on; |
| 200 | }; | 243 | }; |
| 244 | |||
| 245 | reg_vddio_sd0: vddio-sd0 { | ||
| 246 | compatible = "regulator-fixed"; | ||
| 247 | regulator-name = "vddio-sd0"; | ||
| 248 | regulator-min-microvolt = <3300000>; | ||
| 249 | regulator-max-microvolt = <3300000>; | ||
| 250 | gpio = <&gpio3 28 0>; | ||
| 251 | }; | ||
| 252 | |||
| 253 | reg_usb0_vbus: usb0_vbus { | ||
| 254 | compatible = "regulator-fixed"; | ||
| 255 | regulator-name = "usb0_vbus"; | ||
| 256 | regulator-min-microvolt = <5000000>; | ||
| 257 | regulator-max-microvolt = <5000000>; | ||
| 258 | gpio = <&gpio3 12 0>; | ||
| 259 | }; | ||
| 260 | |||
| 261 | reg_usb1_vbus: usb1_vbus { | ||
| 262 | compatible = "regulator-fixed"; | ||
| 263 | regulator-name = "usb1_vbus"; | ||
| 264 | regulator-min-microvolt = <5000000>; | ||
| 265 | regulator-max-microvolt = <5000000>; | ||
| 266 | gpio = <&gpio3 13 0>; | ||
| 267 | }; | ||
| 201 | }; | 268 | }; |
| 202 | 269 | ||
| 203 | sound { | 270 | sound { |
diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts index 62bf767409a6..37be532f0055 100644 --- a/arch/arm/boot/dts/imx28-tx28.dts +++ b/arch/arm/boot/dts/imx28-tx28.dts | |||
| @@ -25,7 +25,7 @@ | |||
| 25 | pinctrl-names = "default"; | 25 | pinctrl-names = "default"; |
| 26 | pinctrl-0 = <&hog_pins_a>; | 26 | pinctrl-0 = <&hog_pins_a>; |
| 27 | 27 | ||
| 28 | hog_pins_a: hog-gpios@0 { | 28 | hog_pins_a: hog@0 { |
| 29 | reg = <0>; | 29 | reg = <0>; |
| 30 | fsl,pinmux-ids = < | 30 | fsl,pinmux-ids = < |
| 31 | 0x40a3 /* MX28_PAD_ENET0_RXD3__GPIO_4_10 */ | 31 | 0x40a3 /* MX28_PAD_ENET0_RXD3__GPIO_4_10 */ |
| @@ -34,6 +34,24 @@ | |||
| 34 | fsl,voltage = <1>; | 34 | fsl,voltage = <1>; |
| 35 | fsl,pull-up = <0>; | 35 | fsl,pull-up = <0>; |
| 36 | }; | 36 | }; |
| 37 | |||
| 38 | mac0_pins_gpio: mac0-gpio-mode@0 { | ||
| 39 | reg = <0>; | ||
| 40 | fsl,pinmux-ids = < | ||
| 41 | 0x4003 /* MX28_PAD_ENET0_MDC__GPIO_4_0 */ | ||
| 42 | 0x4013 /* MX28_PAD_ENET0_MDIO__GPIO_4_1 */ | ||
| 43 | 0x4023 /* MX28_PAD_ENET0_RX_EN__GPIO_4_2 */ | ||
| 44 | 0x4033 /* MX28_PAD_ENET0_RXD0__GPIO_4_3 */ | ||
| 45 | 0x4043 /* MX28_PAD_ENET0_RXD1__GPIO_4_4 */ | ||
| 46 | 0x4063 /* MX28_PAD_ENET0_TX_EN__GPIO_4_6 */ | ||
| 47 | 0x4073 /* MX28_PAD_ENET0_TXD0__GPIO_4_7 */ | ||
| 48 | 0x4083 /* MX28_PAD_ENET0_TXD1__GPIO_4_8 */ | ||
| 49 | 0x4103 /* MX28_PAD_ENET_CLK__GPIO_4_16 */ | ||
| 50 | >; | ||
| 51 | fsl,drive-strength = <0>; | ||
| 52 | fsl,voltage = <1>; | ||
| 53 | fsl,pull-up = <0>; | ||
| 54 | }; | ||
| 37 | }; | 55 | }; |
| 38 | }; | 56 | }; |
| 39 | 57 | ||
| @@ -72,8 +90,9 @@ | |||
| 72 | ahb@80080000 { | 90 | ahb@80080000 { |
| 73 | mac0: ethernet@800f0000 { | 91 | mac0: ethernet@800f0000 { |
| 74 | phy-mode = "rmii"; | 92 | phy-mode = "rmii"; |
| 75 | pinctrl-names = "default"; | 93 | pinctrl-names = "default", "gpio_mode"; |
| 76 | pinctrl-0 = <&mac0_pins_a>; | 94 | pinctrl-0 = <&mac0_pins_a>; |
| 95 | pinctrl-1 = <&mac0_pins_gpio>; | ||
| 77 | status = "okay"; | 96 | status = "okay"; |
| 78 | }; | 97 | }; |
| 79 | }; | 98 | }; |
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 3fa6d190fab4..03e0fef8e7a7 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi | |||
| @@ -65,6 +65,7 @@ | |||
| 65 | dma-apbh@80004000 { | 65 | dma-apbh@80004000 { |
| 66 | compatible = "fsl,imx28-dma-apbh"; | 66 | compatible = "fsl,imx28-dma-apbh"; |
| 67 | reg = <0x80004000 0x2000>; | 67 | reg = <0x80004000 0x2000>; |
| 68 | clocks = <&clks 25>; | ||
| 68 | }; | 69 | }; |
| 69 | 70 | ||
| 70 | perfmon@80006000 { | 71 | perfmon@80006000 { |
| @@ -81,34 +82,47 @@ | |||
| 81 | reg-names = "gpmi-nand", "bch"; | 82 | reg-names = "gpmi-nand", "bch"; |
| 82 | interrupts = <88>, <41>; | 83 | interrupts = <88>, <41>; |
| 83 | interrupt-names = "gpmi-dma", "bch"; | 84 | interrupt-names = "gpmi-dma", "bch"; |
| 85 | clocks = <&clks 50>; | ||
| 84 | fsl,gpmi-dma-channel = <4>; | 86 | fsl,gpmi-dma-channel = <4>; |
| 85 | status = "disabled"; | 87 | status = "disabled"; |
| 86 | }; | 88 | }; |
| 87 | 89 | ||
| 88 | ssp0: ssp@80010000 { | 90 | ssp0: ssp@80010000 { |
| 91 | #address-cells = <1>; | ||
| 92 | #size-cells = <0>; | ||
| 89 | reg = <0x80010000 0x2000>; | 93 | reg = <0x80010000 0x2000>; |
| 90 | interrupts = <96 82>; | 94 | interrupts = <96 82>; |
| 95 | clocks = <&clks 46>; | ||
| 91 | fsl,ssp-dma-channel = <0>; | 96 | fsl,ssp-dma-channel = <0>; |
| 92 | status = "disabled"; | 97 | status = "disabled"; |
| 93 | }; | 98 | }; |
| 94 | 99 | ||
| 95 | ssp1: ssp@80012000 { | 100 | ssp1: ssp@80012000 { |
| 101 | #address-cells = <1>; | ||
| 102 | #size-cells = <0>; | ||
| 96 | reg = <0x80012000 0x2000>; | 103 | reg = <0x80012000 0x2000>; |
| 97 | interrupts = <97 83>; | 104 | interrupts = <97 83>; |
| 105 | clocks = <&clks 47>; | ||
| 98 | fsl,ssp-dma-channel = <1>; | 106 | fsl,ssp-dma-channel = <1>; |
| 99 | status = "disabled"; | 107 | status = "disabled"; |
| 100 | }; | 108 | }; |
| 101 | 109 | ||
| 102 | ssp2: ssp@80014000 { | 110 | ssp2: ssp@80014000 { |
| 111 | #address-cells = <1>; | ||
| 112 | #size-cells = <0>; | ||
| 103 | reg = <0x80014000 0x2000>; | 113 | reg = <0x80014000 0x2000>; |
| 104 | interrupts = <98 84>; | 114 | interrupts = <98 84>; |
| 115 | clocks = <&clks 48>; | ||
| 105 | fsl,ssp-dma-channel = <2>; | 116 | fsl,ssp-dma-channel = <2>; |
| 106 | status = "disabled"; | 117 | status = "disabled"; |
| 107 | }; | 118 | }; |
| 108 | 119 | ||
| 109 | ssp3: ssp@80016000 { | 120 | ssp3: ssp@80016000 { |
| 121 | #address-cells = <1>; | ||
| 122 | #size-cells = <0>; | ||
| 110 | reg = <0x80016000 0x2000>; | 123 | reg = <0x80016000 0x2000>; |
| 111 | interrupts = <99 85>; | 124 | interrupts = <99 85>; |
| 125 | clocks = <&clks 49>; | ||
| 112 | fsl,ssp-dma-channel = <3>; | 126 | fsl,ssp-dma-channel = <3>; |
| 113 | status = "disabled"; | 127 | status = "disabled"; |
| 114 | }; | 128 | }; |
| @@ -410,6 +424,28 @@ | |||
| 410 | fsl,pull-up = <1>; | 424 | fsl,pull-up = <1>; |
| 411 | }; | 425 | }; |
| 412 | 426 | ||
| 427 | i2c0_pins_b: i2c0@1 { | ||
| 428 | reg = <1>; | ||
| 429 | fsl,pinmux-ids = < | ||
| 430 | 0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */ | ||
| 431 | 0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */ | ||
| 432 | >; | ||
| 433 | fsl,drive-strength = <1>; | ||
| 434 | fsl,voltage = <1>; | ||
| 435 | fsl,pull-up = <1>; | ||
| 436 | }; | ||
| 437 | |||
| 438 | i2c1_pins_a: i2c1@0 { | ||
| 439 | reg = <0>; | ||
| 440 | fsl,pinmux-ids = < | ||
| 441 | 0x3101 /* MX28_PAD_PWM0__I2C1_SCL */ | ||
| 442 | 0x3111 /* MX28_PAD_PWM1__I2C1_SDA */ | ||
| 443 | >; | ||
| 444 | fsl,drive-strength = <1>; | ||
| 445 | fsl,voltage = <1>; | ||
| 446 | fsl,pull-up = <1>; | ||
| 447 | }; | ||
| 448 | |||
| 413 | saif0_pins_a: saif0@0 { | 449 | saif0_pins_a: saif0@0 { |
| 414 | reg = <0>; | 450 | reg = <0>; |
| 415 | fsl,pinmux-ids = < | 451 | fsl,pinmux-ids = < |
| @@ -453,6 +489,16 @@ | |||
| 453 | fsl,pull-up = <0>; | 489 | fsl,pull-up = <0>; |
| 454 | }; | 490 | }; |
| 455 | 491 | ||
| 492 | pwm4_pins_a: pwm4@0 { | ||
| 493 | reg = <0>; | ||
| 494 | fsl,pinmux-ids = < | ||
| 495 | 0x31d0 /* MX28_PAD_PWM4__PWM_4 */ | ||
| 496 | >; | ||
| 497 | fsl,drive-strength = <0>; | ||
| 498 | fsl,voltage = <1>; | ||
| 499 | fsl,pull-up = <0>; | ||
| 500 | }; | ||
| 501 | |||
| 456 | lcdif_24bit_pins_a: lcdif-24bit@0 { | 502 | lcdif_24bit_pins_a: lcdif-24bit@0 { |
| 457 | reg = <0>; | 503 | reg = <0>; |
| 458 | fsl,pinmux-ids = < | 504 | fsl,pinmux-ids = < |
| @@ -507,6 +553,49 @@ | |||
| 507 | fsl,voltage = <1>; | 553 | fsl,voltage = <1>; |
| 508 | fsl,pull-up = <0>; | 554 | fsl,pull-up = <0>; |
| 509 | }; | 555 | }; |
| 556 | |||
| 557 | spi2_pins_a: spi2@0 { | ||
| 558 | reg = <0>; | ||
| 559 | fsl,pinmux-ids = < | ||
| 560 | 0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */ | ||
| 561 | 0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */ | ||
| 562 | 0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */ | ||
| 563 | 0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */ | ||
| 564 | >; | ||
| 565 | fsl,drive-strength = <1>; | ||
| 566 | fsl,voltage = <1>; | ||
| 567 | fsl,pull-up = <1>; | ||
| 568 | }; | ||
| 569 | |||
| 570 | usbphy0_pins_a: usbphy0@0 { | ||
| 571 | reg = <0>; | ||
| 572 | fsl,pinmux-ids = < | ||
| 573 | 0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */ | ||
| 574 | >; | ||
| 575 | fsl,drive-strength = <2>; | ||
| 576 | fsl,voltage = <1>; | ||
| 577 | fsl,pull-up = <0>; | ||
| 578 | }; | ||
| 579 | |||
| 580 | usbphy0_pins_b: usbphy0@1 { | ||
| 581 | reg = <1>; | ||
| 582 | fsl,pinmux-ids = < | ||
| 583 | 0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */ | ||
| 584 | >; | ||
| 585 | fsl,drive-strength = <2>; | ||
| 586 | fsl,voltage = <1>; | ||
| 587 | fsl,pull-up = <0>; | ||
| 588 | }; | ||
| 589 | |||
| 590 | usbphy1_pins_a: usbphy1@0 { | ||
| 591 | reg = <0>; | ||
| 592 | fsl,pinmux-ids = < | ||
| 593 | 0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */ | ||
| 594 | >; | ||
| 595 | fsl,drive-strength = <2>; | ||
| 596 | fsl,voltage = <1>; | ||
| 597 | fsl,pull-up = <0>; | ||
| 598 | }; | ||
| 510 | }; | 599 | }; |
| 511 | 600 | ||
| 512 | digctl@8001c000 { | 601 | digctl@8001c000 { |
| @@ -523,6 +612,7 @@ | |||
| 523 | dma-apbx@80024000 { | 612 | dma-apbx@80024000 { |
| 524 | compatible = "fsl,imx28-dma-apbx"; | 613 | compatible = "fsl,imx28-dma-apbx"; |
| 525 | reg = <0x80024000 0x2000>; | 614 | reg = <0x80024000 0x2000>; |
| 615 | clocks = <&clks 26>; | ||
| 526 | }; | 616 | }; |
| 527 | 617 | ||
| 528 | dcp@80028000 { | 618 | dcp@80028000 { |
| @@ -551,6 +641,7 @@ | |||
| 551 | compatible = "fsl,imx28-lcdif"; | 641 | compatible = "fsl,imx28-lcdif"; |
| 552 | reg = <0x80030000 0x2000>; | 642 | reg = <0x80030000 0x2000>; |
| 553 | interrupts = <38 86>; | 643 | interrupts = <38 86>; |
| 644 | clocks = <&clks 55>; | ||
| 554 | status = "disabled"; | 645 | status = "disabled"; |
| 555 | }; | 646 | }; |
| 556 | 647 | ||
| @@ -558,6 +649,8 @@ | |||
| 558 | compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; | 649 | compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; |
| 559 | reg = <0x80032000 0x2000>; | 650 | reg = <0x80032000 0x2000>; |
| 560 | interrupts = <8>; | 651 | interrupts = <8>; |
| 652 | clocks = <&clks 58>, <&clks 58>; | ||
| 653 | clock-names = "ipg", "per"; | ||
| 561 | status = "disabled"; | 654 | status = "disabled"; |
| 562 | }; | 655 | }; |
| 563 | 656 | ||
| @@ -565,6 +658,8 @@ | |||
| 565 | compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; | 658 | compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; |
| 566 | reg = <0x80034000 0x2000>; | 659 | reg = <0x80034000 0x2000>; |
| 567 | interrupts = <9>; | 660 | interrupts = <9>; |
| 661 | clocks = <&clks 59>, <&clks 59>; | ||
| 662 | clock-names = "ipg", "per"; | ||
| 568 | status = "disabled"; | 663 | status = "disabled"; |
| 569 | }; | 664 | }; |
| 570 | 665 | ||
| @@ -611,15 +706,17 @@ | |||
| 611 | reg = <0x80040000 0x40000>; | 706 | reg = <0x80040000 0x40000>; |
| 612 | ranges; | 707 | ranges; |
| 613 | 708 | ||
| 614 | clkctl@80040000 { | 709 | clks: clkctrl@80040000 { |
| 710 | compatible = "fsl,imx28-clkctrl"; | ||
| 615 | reg = <0x80040000 0x2000>; | 711 | reg = <0x80040000 0x2000>; |
| 616 | status = "disabled"; | 712 | #clock-cells = <1>; |
| 617 | }; | 713 | }; |
| 618 | 714 | ||
| 619 | saif0: saif@80042000 { | 715 | saif0: saif@80042000 { |
| 620 | compatible = "fsl,imx28-saif"; | 716 | compatible = "fsl,imx28-saif"; |
| 621 | reg = <0x80042000 0x2000>; | 717 | reg = <0x80042000 0x2000>; |
| 622 | interrupts = <59 80>; | 718 | interrupts = <59 80>; |
| 719 | clocks = <&clks 53>; | ||
| 623 | fsl,saif-dma-channel = <4>; | 720 | fsl,saif-dma-channel = <4>; |
| 624 | status = "disabled"; | 721 | status = "disabled"; |
| 625 | }; | 722 | }; |
| @@ -633,12 +730,16 @@ | |||
| 633 | compatible = "fsl,imx28-saif"; | 730 | compatible = "fsl,imx28-saif"; |
| 634 | reg = <0x80046000 0x2000>; | 731 | reg = <0x80046000 0x2000>; |
| 635 | interrupts = <58 81>; | 732 | interrupts = <58 81>; |
| 733 | clocks = <&clks 54>; | ||
| 636 | fsl,saif-dma-channel = <5>; | 734 | fsl,saif-dma-channel = <5>; |
| 637 | status = "disabled"; | 735 | status = "disabled"; |
| 638 | }; | 736 | }; |
| 639 | 737 | ||
| 640 | lradc@80050000 { | 738 | lradc@80050000 { |
| 739 | compatible = "fsl,imx28-lradc"; | ||
| 641 | reg = <0x80050000 0x2000>; | 740 | reg = <0x80050000 0x2000>; |
| 741 | interrupts = <10 14 15 16 17 18 19 | ||
| 742 | 20 21 22 23 24 25>; | ||
| 642 | status = "disabled"; | 743 | status = "disabled"; |
| 643 | }; | 744 | }; |
| 644 | 745 | ||
| @@ -677,6 +778,7 @@ | |||
| 677 | pwm: pwm@80064000 { | 778 | pwm: pwm@80064000 { |
| 678 | compatible = "fsl,imx28-pwm", "fsl,imx23-pwm"; | 779 | compatible = "fsl,imx28-pwm", "fsl,imx23-pwm"; |
| 679 | reg = <0x80064000 0x2000>; | 780 | reg = <0x80064000 0x2000>; |
| 781 | clocks = <&clks 44>; | ||
| 680 | #pwm-cells = <2>; | 782 | #pwm-cells = <2>; |
| 681 | fsl,pwm-number = <8>; | 783 | fsl,pwm-number = <8>; |
| 682 | status = "disabled"; | 784 | status = "disabled"; |
| @@ -691,6 +793,7 @@ | |||
| 691 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; | 793 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
| 692 | reg = <0x8006a000 0x2000>; | 794 | reg = <0x8006a000 0x2000>; |
| 693 | interrupts = <112 70 71>; | 795 | interrupts = <112 70 71>; |
| 796 | clocks = <&clks 45>; | ||
| 694 | status = "disabled"; | 797 | status = "disabled"; |
| 695 | }; | 798 | }; |
| 696 | 799 | ||
| @@ -698,6 +801,7 @@ | |||
| 698 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; | 801 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
| 699 | reg = <0x8006c000 0x2000>; | 802 | reg = <0x8006c000 0x2000>; |
| 700 | interrupts = <113 72 73>; | 803 | interrupts = <113 72 73>; |
| 804 | clocks = <&clks 45>; | ||
| 701 | status = "disabled"; | 805 | status = "disabled"; |
| 702 | }; | 806 | }; |
| 703 | 807 | ||
| @@ -705,6 +809,7 @@ | |||
| 705 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; | 809 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
| 706 | reg = <0x8006e000 0x2000>; | 810 | reg = <0x8006e000 0x2000>; |
| 707 | interrupts = <114 74 75>; | 811 | interrupts = <114 74 75>; |
| 812 | clocks = <&clks 45>; | ||
| 708 | status = "disabled"; | 813 | status = "disabled"; |
| 709 | }; | 814 | }; |
| 710 | 815 | ||
| @@ -712,6 +817,7 @@ | |||
| 712 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; | 817 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
| 713 | reg = <0x80070000 0x2000>; | 818 | reg = <0x80070000 0x2000>; |
| 714 | interrupts = <115 76 77>; | 819 | interrupts = <115 76 77>; |
| 820 | clocks = <&clks 45>; | ||
| 715 | status = "disabled"; | 821 | status = "disabled"; |
| 716 | }; | 822 | }; |
| 717 | 823 | ||
| @@ -719,6 +825,7 @@ | |||
| 719 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; | 825 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
| 720 | reg = <0x80072000 0x2000>; | 826 | reg = <0x80072000 0x2000>; |
| 721 | interrupts = <116 78 79>; | 827 | interrupts = <116 78 79>; |
| 828 | clocks = <&clks 45>; | ||
| 722 | status = "disabled"; | 829 | status = "disabled"; |
| 723 | }; | 830 | }; |
| 724 | 831 | ||
| @@ -726,18 +833,22 @@ | |||
| 726 | compatible = "arm,pl011", "arm,primecell"; | 833 | compatible = "arm,pl011", "arm,primecell"; |
| 727 | reg = <0x80074000 0x1000>; | 834 | reg = <0x80074000 0x1000>; |
| 728 | interrupts = <47>; | 835 | interrupts = <47>; |
| 836 | clocks = <&clks 45>, <&clks 26>; | ||
| 837 | clock-names = "uart", "apb_pclk"; | ||
| 729 | status = "disabled"; | 838 | status = "disabled"; |
| 730 | }; | 839 | }; |
| 731 | 840 | ||
| 732 | usbphy0: usbphy@8007c000 { | 841 | usbphy0: usbphy@8007c000 { |
| 733 | compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; | 842 | compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; |
| 734 | reg = <0x8007c000 0x2000>; | 843 | reg = <0x8007c000 0x2000>; |
| 844 | clocks = <&clks 62>; | ||
| 735 | status = "disabled"; | 845 | status = "disabled"; |
| 736 | }; | 846 | }; |
| 737 | 847 | ||
| 738 | usbphy1: usbphy@8007e000 { | 848 | usbphy1: usbphy@8007e000 { |
| 739 | compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; | 849 | compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; |
| 740 | reg = <0x8007e000 0x2000>; | 850 | reg = <0x8007e000 0x2000>; |
| 851 | clocks = <&clks 63>; | ||
| 741 | status = "disabled"; | 852 | status = "disabled"; |
| 742 | }; | 853 | }; |
| 743 | }; | 854 | }; |
| @@ -754,6 +865,7 @@ | |||
| 754 | compatible = "fsl,imx28-usb", "fsl,imx27-usb"; | 865 | compatible = "fsl,imx28-usb", "fsl,imx27-usb"; |
| 755 | reg = <0x80080000 0x10000>; | 866 | reg = <0x80080000 0x10000>; |
| 756 | interrupts = <93>; | 867 | interrupts = <93>; |
| 868 | clocks = <&clks 60>; | ||
| 757 | fsl,usbphy = <&usbphy0>; | 869 | fsl,usbphy = <&usbphy0>; |
| 758 | status = "disabled"; | 870 | status = "disabled"; |
| 759 | }; | 871 | }; |
| @@ -762,6 +874,7 @@ | |||
| 762 | compatible = "fsl,imx28-usb", "fsl,imx27-usb"; | 874 | compatible = "fsl,imx28-usb", "fsl,imx27-usb"; |
| 763 | reg = <0x80090000 0x10000>; | 875 | reg = <0x80090000 0x10000>; |
| 764 | interrupts = <92>; | 876 | interrupts = <92>; |
| 877 | clocks = <&clks 61>; | ||
| 765 | fsl,usbphy = <&usbphy1>; | 878 | fsl,usbphy = <&usbphy1>; |
| 766 | status = "disabled"; | 879 | status = "disabled"; |
| 767 | }; | 880 | }; |
| @@ -775,6 +888,8 @@ | |||
| 775 | compatible = "fsl,imx28-fec"; | 888 | compatible = "fsl,imx28-fec"; |
| 776 | reg = <0x800f0000 0x4000>; | 889 | reg = <0x800f0000 0x4000>; |
| 777 | interrupts = <101>; | 890 | interrupts = <101>; |
| 891 | clocks = <&clks 57>, <&clks 57>; | ||
| 892 | clock-names = "ipg", "ahb"; | ||
| 778 | status = "disabled"; | 893 | status = "disabled"; |
| 779 | }; | 894 | }; |
| 780 | 895 | ||
| @@ -782,6 +897,8 @@ | |||
| 782 | compatible = "fsl,imx28-fec"; | 897 | compatible = "fsl,imx28-fec"; |
| 783 | reg = <0x800f4000 0x4000>; | 898 | reg = <0x800f4000 0x4000>; |
| 784 | interrupts = <102>; | 899 | interrupts = <102>; |
| 900 | clocks = <&clks 57>, <&clks 57>; | ||
| 901 | clock-names = "ipg", "ahb"; | ||
| 785 | status = "disabled"; | 902 | status = "disabled"; |
| 786 | }; | 903 | }; |
| 787 | 904 | ||
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index cd86177a3ea2..cbd2b1c7487b 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts | |||
| @@ -25,23 +25,31 @@ | |||
| 25 | aips@70000000 { /* aips-1 */ | 25 | aips@70000000 { /* aips-1 */ |
| 26 | spba@70000000 { | 26 | spba@70000000 { |
| 27 | esdhc@70004000 { /* ESDHC1 */ | 27 | esdhc@70004000 { /* ESDHC1 */ |
| 28 | fsl,cd-internal; | 28 | pinctrl-names = "default"; |
| 29 | fsl,wp-internal; | 29 | pinctrl-0 = <&pinctrl_esdhc1_1>; |
| 30 | fsl,cd-controller; | ||
| 31 | fsl,wp-controller; | ||
| 30 | status = "okay"; | 32 | status = "okay"; |
| 31 | }; | 33 | }; |
| 32 | 34 | ||
| 33 | esdhc@70008000 { /* ESDHC2 */ | 35 | esdhc@70008000 { /* ESDHC2 */ |
| 36 | pinctrl-names = "default"; | ||
| 37 | pinctrl-0 = <&pinctrl_esdhc2_1>; | ||
| 34 | cd-gpios = <&gpio1 6 0>; | 38 | cd-gpios = <&gpio1 6 0>; |
| 35 | wp-gpios = <&gpio1 5 0>; | 39 | wp-gpios = <&gpio1 5 0>; |
| 36 | status = "okay"; | 40 | status = "okay"; |
| 37 | }; | 41 | }; |
| 38 | 42 | ||
| 39 | uart3: serial@7000c000 { | 43 | uart3: serial@7000c000 { |
| 44 | pinctrl-names = "default"; | ||
| 45 | pinctrl-0 = <&pinctrl_uart3_1>; | ||
| 40 | fsl,uart-has-rtscts; | 46 | fsl,uart-has-rtscts; |
| 41 | status = "okay"; | 47 | status = "okay"; |
| 42 | }; | 48 | }; |
| 43 | 49 | ||
| 44 | ecspi@70010000 { /* ECSPI1 */ | 50 | ecspi@70010000 { /* ECSPI1 */ |
| 51 | pinctrl-names = "default"; | ||
| 52 | pinctrl-0 = <&pinctrl_ecspi1_1>; | ||
| 45 | fsl,spi-num-chipselects = <2>; | 53 | fsl,spi-num-chipselects = <2>; |
| 46 | cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>; | 54 | cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>; |
| 47 | status = "okay"; | 55 | status = "okay"; |
| @@ -169,31 +177,43 @@ | |||
| 169 | }; | 177 | }; |
| 170 | }; | 178 | }; |
| 171 | 179 | ||
| 172 | wdog@73f98000 { /* WDOG1 */ | ||
| 173 | status = "okay"; | ||
| 174 | }; | ||
| 175 | |||
| 176 | iomuxc@73fa8000 { | 180 | iomuxc@73fa8000 { |
| 177 | compatible = "fsl,imx51-iomuxc-babbage"; | 181 | pinctrl-names = "default"; |
| 178 | reg = <0x73fa8000 0x4000>; | 182 | pinctrl-0 = <&pinctrl_hog>; |
| 183 | |||
| 184 | hog { | ||
| 185 | pinctrl_hog: hoggrp { | ||
| 186 | fsl,pins = < | ||
| 187 | 694 0x20d5 /* MX51_PAD_GPIO1_0__SD1_CD */ | ||
| 188 | 697 0x20d5 /* MX51_PAD_GPIO1_1__SD1_WP */ | ||
| 189 | 737 0x100 /* MX51_PAD_GPIO1_5__GPIO1_5 */ | ||
| 190 | 740 0x100 /* MX51_PAD_GPIO1_6__GPIO1_6 */ | ||
| 191 | 121 0x5 /* MX51_PAD_EIM_A27__GPIO2_21 */ | ||
| 192 | 402 0x85 /* MX51_PAD_CSPI1_SS0__GPIO4_24 */ | ||
| 193 | 405 0x85 /* MX51_PAD_CSPI1_SS1__GPIO4_25 */ | ||
| 194 | >; | ||
| 195 | }; | ||
| 196 | }; | ||
| 179 | }; | 197 | }; |
| 180 | 198 | ||
| 181 | uart1: serial@73fbc000 { | 199 | uart1: serial@73fbc000 { |
| 200 | pinctrl-names = "default"; | ||
| 201 | pinctrl-0 = <&pinctrl_uart1_1>; | ||
| 182 | fsl,uart-has-rtscts; | 202 | fsl,uart-has-rtscts; |
| 183 | status = "okay"; | 203 | status = "okay"; |
| 184 | }; | 204 | }; |
| 185 | 205 | ||
| 186 | uart2: serial@73fc0000 { | 206 | uart2: serial@73fc0000 { |
| 207 | pinctrl-names = "default"; | ||
| 208 | pinctrl-0 = <&pinctrl_uart2_1>; | ||
| 187 | status = "okay"; | 209 | status = "okay"; |
| 188 | }; | 210 | }; |
| 189 | }; | 211 | }; |
| 190 | 212 | ||
| 191 | aips@80000000 { /* aips-2 */ | 213 | aips@80000000 { /* aips-2 */ |
| 192 | sdma@83fb0000 { | ||
| 193 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; | ||
| 194 | }; | ||
| 195 | |||
| 196 | i2c@83fc4000 { /* I2C2 */ | 214 | i2c@83fc4000 { /* I2C2 */ |
| 215 | pinctrl-names = "default"; | ||
| 216 | pinctrl-0 = <&pinctrl_i2c2_1>; | ||
| 197 | status = "okay"; | 217 | status = "okay"; |
| 198 | 218 | ||
| 199 | sgtl5000: codec@0a { | 219 | sgtl5000: codec@0a { |
| @@ -206,10 +226,14 @@ | |||
| 206 | }; | 226 | }; |
| 207 | 227 | ||
| 208 | audmux@83fd0000 { | 228 | audmux@83fd0000 { |
| 229 | pinctrl-names = "default"; | ||
| 230 | pinctrl-0 = <&pinctrl_audmux_1>; | ||
| 209 | status = "okay"; | 231 | status = "okay"; |
| 210 | }; | 232 | }; |
| 211 | 233 | ||
| 212 | ethernet@83fec000 { | 234 | ethernet@83fec000 { |
| 235 | pinctrl-names = "default"; | ||
| 236 | pinctrl-0 = <&pinctrl_fec_1>; | ||
| 213 | phy-mode = "mii"; | 237 | phy-mode = "mii"; |
| 214 | status = "okay"; | 238 | status = "okay"; |
| 215 | }; | 239 | }; |
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index aba28dc87fc8..2f71a91ca98e 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi | |||
| @@ -130,6 +130,34 @@ | |||
| 130 | }; | 130 | }; |
| 131 | }; | 131 | }; |
| 132 | 132 | ||
| 133 | usb@73f80000 { | ||
| 134 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; | ||
| 135 | reg = <0x73f80000 0x0200>; | ||
| 136 | interrupts = <18>; | ||
| 137 | status = "disabled"; | ||
| 138 | }; | ||
| 139 | |||
| 140 | usb@73f80200 { | ||
| 141 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; | ||
| 142 | reg = <0x73f80200 0x0200>; | ||
| 143 | interrupts = <14>; | ||
| 144 | status = "disabled"; | ||
| 145 | }; | ||
| 146 | |||
| 147 | usb@73f80400 { | ||
| 148 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; | ||
| 149 | reg = <0x73f80400 0x0200>; | ||
| 150 | interrupts = <16>; | ||
| 151 | status = "disabled"; | ||
| 152 | }; | ||
| 153 | |||
| 154 | usb@73f80600 { | ||
| 155 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; | ||
| 156 | reg = <0x73f80600 0x0200>; | ||
| 157 | interrupts = <17>; | ||
| 158 | status = "disabled"; | ||
| 159 | }; | ||
| 160 | |||
| 133 | gpio1: gpio@73f84000 { | 161 | gpio1: gpio@73f84000 { |
| 134 | compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; | 162 | compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; |
| 135 | reg = <0x73f84000 0x4000>; | 163 | reg = <0x73f84000 0x4000>; |
| @@ -174,7 +202,6 @@ | |||
| 174 | compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; | 202 | compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; |
| 175 | reg = <0x73f98000 0x4000>; | 203 | reg = <0x73f98000 0x4000>; |
| 176 | interrupts = <58>; | 204 | interrupts = <58>; |
| 177 | status = "disabled"; | ||
| 178 | }; | 205 | }; |
| 179 | 206 | ||
| 180 | wdog@73f9c000 { /* WDOG2 */ | 207 | wdog@73f9c000 { /* WDOG2 */ |
| @@ -184,6 +211,122 @@ | |||
| 184 | status = "disabled"; | 211 | status = "disabled"; |
| 185 | }; | 212 | }; |
| 186 | 213 | ||
| 214 | iomuxc@73fa8000 { | ||
| 215 | compatible = "fsl,imx51-iomuxc"; | ||
| 216 | reg = <0x73fa8000 0x4000>; | ||
| 217 | |||
| 218 | audmux { | ||
| 219 | pinctrl_audmux_1: audmuxgrp-1 { | ||
| 220 | fsl,pins = < | ||
| 221 | 384 0x80000000 /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */ | ||
| 222 | 386 0x80000000 /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */ | ||
| 223 | 389 0x80000000 /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */ | ||
| 224 | 391 0x80000000 /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */ | ||
| 225 | >; | ||
| 226 | }; | ||
| 227 | }; | ||
| 228 | |||
| 229 | fec { | ||
| 230 | pinctrl_fec_1: fecgrp-1 { | ||
| 231 | fsl,pins = < | ||
| 232 | 128 0x80000000 /* MX51_PAD_EIM_EB2__FEC_MDIO */ | ||
| 233 | 134 0x80000000 /* MX51_PAD_EIM_EB3__FEC_RDATA1 */ | ||
| 234 | 146 0x80000000 /* MX51_PAD_EIM_CS2__FEC_RDATA2 */ | ||
| 235 | 152 0x80000000 /* MX51_PAD_EIM_CS3__FEC_RDATA3 */ | ||
| 236 | 158 0x80000000 /* MX51_PAD_EIM_CS4__FEC_RX_ER */ | ||
| 237 | 165 0x80000000 /* MX51_PAD_EIM_CS5__FEC_CRS */ | ||
| 238 | 206 0x80000000 /* MX51_PAD_NANDF_RB2__FEC_COL */ | ||
| 239 | 213 0x80000000 /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */ | ||
| 240 | 293 0x80000000 /* MX51_PAD_NANDF_D9__FEC_RDATA0 */ | ||
| 241 | 298 0x80000000 /* MX51_PAD_NANDF_D8__FEC_TDATA0 */ | ||
| 242 | 225 0x80000000 /* MX51_PAD_NANDF_CS2__FEC_TX_ER */ | ||
| 243 | 231 0x80000000 /* MX51_PAD_NANDF_CS3__FEC_MDC */ | ||
| 244 | 237 0x80000000 /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */ | ||
| 245 | 243 0x80000000 /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */ | ||
| 246 | 250 0x80000000 /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */ | ||
| 247 | 255 0x80000000 /* MX51_PAD_NANDF_CS7__FEC_TX_EN */ | ||
| 248 | 260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */ | ||
| 249 | >; | ||
| 250 | }; | ||
| 251 | }; | ||
| 252 | |||
| 253 | ecspi1 { | ||
| 254 | pinctrl_ecspi1_1: ecspi1grp-1 { | ||
| 255 | fsl,pins = < | ||
| 256 | 398 0x185 /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */ | ||
| 257 | 394 0x185 /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */ | ||
| 258 | 409 0x185 /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */ | ||
| 259 | >; | ||
| 260 | }; | ||
| 261 | }; | ||
| 262 | |||
| 263 | esdhc1 { | ||
| 264 | pinctrl_esdhc1_1: esdhc1grp-1 { | ||
| 265 | fsl,pins = < | ||
| 266 | 666 0x400020d5 /* MX51_PAD_SD1_CMD__SD1_CMD */ | ||
| 267 | 669 0x20d5 /* MX51_PAD_SD1_CLK__SD1_CLK */ | ||
| 268 | 672 0x20d5 /* MX51_PAD_SD1_DATA0__SD1_DATA0 */ | ||
| 269 | 678 0x20d5 /* MX51_PAD_SD1_DATA1__SD1_DATA1 */ | ||
| 270 | 684 0x20d5 /* MX51_PAD_SD1_DATA2__SD1_DATA2 */ | ||
| 271 | 691 0x20d5 /* MX51_PAD_SD1_DATA3__SD1_DATA3 */ | ||
| 272 | >; | ||
| 273 | }; | ||
| 274 | }; | ||
| 275 | |||
| 276 | esdhc2 { | ||
| 277 | pinctrl_esdhc2_1: esdhc2grp-1 { | ||
| 278 | fsl,pins = < | ||
| 279 | 704 0x400020d5 /* MX51_PAD_SD2_CMD__SD2_CMD */ | ||
| 280 | 707 0x20d5 /* MX51_PAD_SD2_CLK__SD2_CLK */ | ||
| 281 | 710 0x20d5 /* MX51_PAD_SD2_DATA0__SD2_DATA0 */ | ||
| 282 | 712 0x20d5 /* MX51_PAD_SD2_DATA1__SD2_DATA1 */ | ||
| 283 | 715 0x20d5 /* MX51_PAD_SD2_DATA2__SD2_DATA2 */ | ||
| 284 | 719 0x20d5 /* MX51_PAD_SD2_DATA3__SD2_DATA3 */ | ||
| 285 | >; | ||
| 286 | }; | ||
| 287 | }; | ||
| 288 | |||
| 289 | i2c2 { | ||
| 290 | pinctrl_i2c2_1: i2c2grp-1 { | ||
| 291 | fsl,pins = < | ||
| 292 | 449 0x400001ed /* MX51_PAD_KEY_COL4__I2C2_SCL */ | ||
| 293 | 454 0x400001ed /* MX51_PAD_KEY_COL5__I2C2_SDA */ | ||
| 294 | >; | ||
| 295 | }; | ||
| 296 | }; | ||
| 297 | |||
| 298 | uart1 { | ||
| 299 | pinctrl_uart1_1: uart1grp-1 { | ||
| 300 | fsl,pins = < | ||
| 301 | 413 0x1c5 /* MX51_PAD_UART1_RXD__UART1_RXD */ | ||
| 302 | 416 0x1c5 /* MX51_PAD_UART1_TXD__UART1_TXD */ | ||
| 303 | 418 0x1c5 /* MX51_PAD_UART1_RTS__UART1_RTS */ | ||
| 304 | 420 0x1c5 /* MX51_PAD_UART1_CTS__UART1_CTS */ | ||
| 305 | >; | ||
| 306 | }; | ||
| 307 | }; | ||
| 308 | |||
| 309 | uart2 { | ||
| 310 | pinctrl_uart2_1: uart2grp-1 { | ||
| 311 | fsl,pins = < | ||
| 312 | 423 0x1c5 /* MX51_PAD_UART2_RXD__UART2_RXD */ | ||
| 313 | 426 0x1c5 /* MX51_PAD_UART2_TXD__UART2_TXD */ | ||
| 314 | >; | ||
| 315 | }; | ||
| 316 | }; | ||
| 317 | |||
| 318 | uart3 { | ||
| 319 | pinctrl_uart3_1: uart3grp-1 { | ||
| 320 | fsl,pins = < | ||
| 321 | 54 0x1c5 /* MX51_PAD_EIM_D25__UART3_RXD */ | ||
| 322 | 59 0x1c5 /* MX51_PAD_EIM_D26__UART3_TXD */ | ||
| 323 | 65 0x1c5 /* MX51_PAD_EIM_D27__UART3_RTS */ | ||
| 324 | 49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */ | ||
| 325 | >; | ||
| 326 | }; | ||
| 327 | }; | ||
| 328 | }; | ||
| 329 | |||
| 187 | uart1: serial@73fbc000 { | 330 | uart1: serial@73fbc000 { |
| 188 | compatible = "fsl,imx51-uart", "fsl,imx21-uart"; | 331 | compatible = "fsl,imx51-uart", "fsl,imx21-uart"; |
| 189 | reg = <0x73fbc000 0x4000>; | 332 | reg = <0x73fbc000 0x4000>; |
| @@ -219,6 +362,7 @@ | |||
| 219 | compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; | 362 | compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; |
| 220 | reg = <0x83fb0000 0x4000>; | 363 | reg = <0x83fb0000 0x4000>; |
| 221 | interrupts = <6>; | 364 | interrupts = <6>; |
| 365 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; | ||
| 222 | }; | 366 | }; |
| 223 | 367 | ||
| 224 | cspi@83fc0000 { | 368 | cspi@83fc0000 { |
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts index da895e93a999..4be76f223526 100644 --- a/arch/arm/boot/dts/imx53-ard.dts +++ b/arch/arm/boot/dts/imx53-ard.dts | |||
| @@ -25,31 +25,66 @@ | |||
| 25 | aips@50000000 { /* AIPS1 */ | 25 | aips@50000000 { /* AIPS1 */ |
| 26 | spba@50000000 { | 26 | spba@50000000 { |
| 27 | esdhc@50004000 { /* ESDHC1 */ | 27 | esdhc@50004000 { /* ESDHC1 */ |
| 28 | pinctrl-names = "default"; | ||
| 29 | pinctrl-0 = <&pinctrl_esdhc1_2>; | ||
| 28 | cd-gpios = <&gpio1 1 0>; | 30 | cd-gpios = <&gpio1 1 0>; |
| 29 | wp-gpios = <&gpio1 9 0>; | 31 | wp-gpios = <&gpio1 9 0>; |
| 30 | status = "okay"; | 32 | status = "okay"; |
| 31 | }; | 33 | }; |
| 32 | }; | 34 | }; |
| 33 | 35 | ||
| 34 | wdog@53f98000 { /* WDOG1 */ | ||
| 35 | status = "okay"; | ||
| 36 | }; | ||
| 37 | |||
| 38 | iomuxc@53fa8000 { | 36 | iomuxc@53fa8000 { |
| 39 | compatible = "fsl,imx53-iomuxc-ard"; | 37 | pinctrl-names = "default"; |
| 40 | reg = <0x53fa8000 0x4000>; | 38 | pinctrl-0 = <&pinctrl_hog>; |
| 39 | |||
| 40 | hog { | ||
| 41 | pinctrl_hog: hoggrp { | ||
| 42 | fsl,pins = < | ||
| 43 | 1077 0x80000000 /* MX53_PAD_GPIO_1__GPIO1_1 */ | ||
| 44 | 1085 0x80000000 /* MX53_PAD_GPIO_9__GPIO1_9 */ | ||
| 45 | 486 0x80000000 /* MX53_PAD_EIM_EB3__GPIO2_31 */ | ||
| 46 | 739 0x80000000 /* MX53_PAD_GPIO_10__GPIO4_0 */ | ||
| 47 | 218 0x80000000 /* MX53_PAD_DISP0_DAT16__GPIO5_10 */ | ||
| 48 | 226 0x80000000 /* MX53_PAD_DISP0_DAT17__GPIO5_11 */ | ||
| 49 | 233 0x80000000 /* MX53_PAD_DISP0_DAT18__GPIO5_12 */ | ||
| 50 | 241 0x80000000 /* MX53_PAD_DISP0_DAT19__GPIO5_13 */ | ||
| 51 | 429 0x80000000 /* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */ | ||
| 52 | 435 0x80000000 /* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */ | ||
| 53 | 441 0x80000000 /* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */ | ||
| 54 | 448 0x80000000 /* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */ | ||
| 55 | 456 0x80000000 /* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */ | ||
| 56 | 464 0x80000000 /* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */ | ||
| 57 | 471 0x80000000 /* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */ | ||
| 58 | 477 0x80000000 /* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */ | ||
| 59 | 492 0x80000000 /* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */ | ||
| 60 | 500 0x80000000 /* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */ | ||
| 61 | 508 0x80000000 /* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */ | ||
| 62 | 516 0x80000000 /* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */ | ||
| 63 | 524 0x80000000 /* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */ | ||
| 64 | 532 0x80000000 /* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */ | ||
| 65 | 540 0x80000000 /* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */ | ||
| 66 | 548 0x80000000 /* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */ | ||
| 67 | 637 0x80000000 /* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */ | ||
| 68 | 642 0x80000000 /* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */ | ||
| 69 | 647 0x80000000 /* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */ | ||
| 70 | 652 0x80000000 /* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */ | ||
| 71 | 657 0x80000000 /* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */ | ||
| 72 | 662 0x80000000 /* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */ | ||
| 73 | 667 0x80000000 /* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */ | ||
| 74 | 611 0x80000000 /* MX53_PAD_EIM_OE__EMI_WEIM_OE */ | ||
| 75 | 616 0x80000000 /* MX53_PAD_EIM_RW__EMI_WEIM_RW */ | ||
| 76 | 607 0x80000000 /* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */ | ||
| 77 | >; | ||
| 78 | }; | ||
| 79 | }; | ||
| 41 | }; | 80 | }; |
| 42 | 81 | ||
| 43 | uart1: serial@53fbc000 { | 82 | uart1: serial@53fbc000 { |
| 83 | pinctrl-names = "default"; | ||
| 84 | pinctrl-0 = <&pinctrl_uart1_2>; | ||
| 44 | status = "okay"; | 85 | status = "okay"; |
| 45 | }; | 86 | }; |
| 46 | }; | 87 | }; |
| 47 | |||
| 48 | aips@60000000 { /* AIPS2 */ | ||
| 49 | sdma@63fb0000 { | ||
| 50 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; | ||
| 51 | }; | ||
| 52 | }; | ||
| 53 | }; | 88 | }; |
| 54 | 89 | ||
| 55 | eim-cs1@f4000000 { | 90 | eim-cs1@f4000000 { |
diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts index 9c798034675e..a124d1e25258 100644 --- a/arch/arm/boot/dts/imx53-evk.dts +++ b/arch/arm/boot/dts/imx53-evk.dts | |||
| @@ -25,12 +25,16 @@ | |||
| 25 | aips@50000000 { /* AIPS1 */ | 25 | aips@50000000 { /* AIPS1 */ |
| 26 | spba@50000000 { | 26 | spba@50000000 { |
| 27 | esdhc@50004000 { /* ESDHC1 */ | 27 | esdhc@50004000 { /* ESDHC1 */ |
| 28 | pinctrl-names = "default"; | ||
| 29 | pinctrl-0 = <&pinctrl_esdhc1_1>; | ||
| 28 | cd-gpios = <&gpio3 13 0>; | 30 | cd-gpios = <&gpio3 13 0>; |
| 29 | wp-gpios = <&gpio3 14 0>; | 31 | wp-gpios = <&gpio3 14 0>; |
| 30 | status = "okay"; | 32 | status = "okay"; |
| 31 | }; | 33 | }; |
| 32 | 34 | ||
| 33 | ecspi@50010000 { /* ECSPI1 */ | 35 | ecspi@50010000 { /* ECSPI1 */ |
| 36 | pinctrl-names = "default"; | ||
| 37 | pinctrl-0 = <&pinctrl_ecspi1_1>; | ||
| 34 | fsl,spi-num-chipselects = <2>; | 38 | fsl,spi-num-chipselects = <2>; |
| 35 | cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; | 39 | cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; |
| 36 | status = "okay"; | 40 | status = "okay"; |
| @@ -56,32 +60,45 @@ | |||
| 56 | }; | 60 | }; |
| 57 | 61 | ||
| 58 | esdhc@50020000 { /* ESDHC3 */ | 62 | esdhc@50020000 { /* ESDHC3 */ |
| 63 | pinctrl-names = "default"; | ||
| 64 | pinctrl-0 = <&pinctrl_esdhc3_1>; | ||
| 59 | cd-gpios = <&gpio3 11 0>; | 65 | cd-gpios = <&gpio3 11 0>; |
| 60 | wp-gpios = <&gpio3 12 0>; | 66 | wp-gpios = <&gpio3 12 0>; |
| 61 | status = "okay"; | 67 | status = "okay"; |
| 62 | }; | 68 | }; |
| 63 | }; | 69 | }; |
| 64 | 70 | ||
| 65 | wdog@53f98000 { /* WDOG1 */ | ||
| 66 | status = "okay"; | ||
| 67 | }; | ||
| 68 | |||
| 69 | iomuxc@53fa8000 { | 71 | iomuxc@53fa8000 { |
| 70 | compatible = "fsl,imx53-iomuxc-evk"; | 72 | pinctrl-names = "default"; |
| 71 | reg = <0x53fa8000 0x4000>; | 73 | pinctrl-0 = <&pinctrl_hog>; |
| 74 | |||
| 75 | hog { | ||
| 76 | pinctrl_hog: hoggrp { | ||
| 77 | fsl,pins = < | ||
| 78 | 424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */ | ||
| 79 | 449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */ | ||
| 80 | 693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */ | ||
| 81 | 697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */ | ||
| 82 | 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */ | ||
| 83 | 705 0x80000000 /* MX53_PAD_EIM_DA14__GPIO3_14 */ | ||
| 84 | 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */ | ||
| 85 | 873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */ | ||
| 86 | >; | ||
| 87 | }; | ||
| 88 | }; | ||
| 72 | }; | 89 | }; |
| 73 | 90 | ||
| 74 | uart1: serial@53fbc000 { | 91 | uart1: serial@53fbc000 { |
| 92 | pinctrl-names = "default"; | ||
| 93 | pinctrl-0 = <&pinctrl_uart1_1>; | ||
| 75 | status = "okay"; | 94 | status = "okay"; |
| 76 | }; | 95 | }; |
| 77 | }; | 96 | }; |
| 78 | 97 | ||
| 79 | aips@60000000 { /* AIPS2 */ | 98 | aips@60000000 { /* AIPS2 */ |
| 80 | sdma@63fb0000 { | ||
| 81 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; | ||
| 82 | }; | ||
| 83 | |||
| 84 | i2c@63fc4000 { /* I2C2 */ | 99 | i2c@63fc4000 { /* I2C2 */ |
| 100 | pinctrl-names = "default"; | ||
| 101 | pinctrl-0 = <&pinctrl_i2c2_1>; | ||
| 85 | status = "okay"; | 102 | status = "okay"; |
| 86 | 103 | ||
| 87 | pmic: mc13892@08 { | 104 | pmic: mc13892@08 { |
| @@ -96,6 +113,8 @@ | |||
| 96 | }; | 113 | }; |
| 97 | 114 | ||
| 98 | ethernet@63fec000 { | 115 | ethernet@63fec000 { |
| 116 | pinctrl-names = "default"; | ||
| 117 | pinctrl-0 = <&pinctrl_fec_1>; | ||
| 99 | phy-mode = "rmii"; | 118 | phy-mode = "rmii"; |
| 100 | phy-reset-gpios = <&gpio7 6 0>; | 119 | phy-reset-gpios = <&gpio7 6 0>; |
| 101 | status = "okay"; | 120 | status = "okay"; |
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts index 2d803a9a6949..08948af86d1a 100644 --- a/arch/arm/boot/dts/imx53-qsb.dts +++ b/arch/arm/boot/dts/imx53-qsb.dts | |||
| @@ -25,6 +25,8 @@ | |||
| 25 | aips@50000000 { /* AIPS1 */ | 25 | aips@50000000 { /* AIPS1 */ |
| 26 | spba@50000000 { | 26 | spba@50000000 { |
| 27 | esdhc@50004000 { /* ESDHC1 */ | 27 | esdhc@50004000 { /* ESDHC1 */ |
| 28 | pinctrl-names = "default"; | ||
| 29 | pinctrl-0 = <&pinctrl_esdhc1_1>; | ||
| 28 | cd-gpios = <&gpio3 13 0>; | 30 | cd-gpios = <&gpio3 13 0>; |
| 29 | status = "okay"; | 31 | status = "okay"; |
| 30 | }; | 32 | }; |
| @@ -35,32 +37,46 @@ | |||
| 35 | }; | 37 | }; |
| 36 | 38 | ||
| 37 | esdhc@50020000 { /* ESDHC3 */ | 39 | esdhc@50020000 { /* ESDHC3 */ |
| 40 | pinctrl-names = "default"; | ||
| 41 | pinctrl-0 = <&pinctrl_esdhc3_1>; | ||
| 38 | cd-gpios = <&gpio3 11 0>; | 42 | cd-gpios = <&gpio3 11 0>; |
| 39 | wp-gpios = <&gpio3 12 0>; | 43 | wp-gpios = <&gpio3 12 0>; |
| 40 | status = "okay"; | 44 | status = "okay"; |
| 41 | }; | 45 | }; |
| 42 | }; | 46 | }; |
| 43 | 47 | ||
| 44 | wdog@53f98000 { /* WDOG1 */ | ||
| 45 | status = "okay"; | ||
| 46 | }; | ||
| 47 | |||
| 48 | iomuxc@53fa8000 { | 48 | iomuxc@53fa8000 { |
| 49 | compatible = "fsl,imx53-iomuxc-qsb"; | 49 | pinctrl-names = "default"; |
| 50 | reg = <0x53fa8000 0x4000>; | 50 | pinctrl-0 = <&pinctrl_hog>; |
| 51 | |||
| 52 | hog { | ||
| 53 | pinctrl_hog: hoggrp { | ||
| 54 | fsl,pins = < | ||
| 55 | 1071 0x80000000 /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */ | ||
| 56 | 1141 0x80000000 /* MX53_PAD_GPIO_8__GPIO1_8 */ | ||
| 57 | 982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */ | ||
| 58 | 989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */ | ||
| 59 | 693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */ | ||
| 60 | 697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */ | ||
| 61 | 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */ | ||
| 62 | 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */ | ||
| 63 | 873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */ | ||
| 64 | >; | ||
| 65 | }; | ||
| 66 | }; | ||
| 51 | }; | 67 | }; |
| 52 | 68 | ||
| 53 | uart1: serial@53fbc000 { | 69 | uart1: serial@53fbc000 { |
| 70 | pinctrl-names = "default"; | ||
| 71 | pinctrl-0 = <&pinctrl_uart1_1>; | ||
| 54 | status = "okay"; | 72 | status = "okay"; |
| 55 | }; | 73 | }; |
| 56 | }; | 74 | }; |
| 57 | 75 | ||
| 58 | aips@60000000 { /* AIPS2 */ | 76 | aips@60000000 { /* AIPS2 */ |
| 59 | sdma@63fb0000 { | ||
| 60 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; | ||
| 61 | }; | ||
| 62 | |||
| 63 | i2c@63fc4000 { /* I2C2 */ | 77 | i2c@63fc4000 { /* I2C2 */ |
| 78 | pinctrl-names = "default"; | ||
| 79 | pinctrl-0 = <&pinctrl_i2c2_1>; | ||
| 64 | status = "okay"; | 80 | status = "okay"; |
| 65 | 81 | ||
| 66 | sgtl5000: codec@0a { | 82 | sgtl5000: codec@0a { |
| @@ -72,6 +88,8 @@ | |||
| 72 | }; | 88 | }; |
| 73 | 89 | ||
| 74 | i2c@63fc8000 { /* I2C1 */ | 90 | i2c@63fc8000 { /* I2C1 */ |
| 91 | pinctrl-names = "default"; | ||
| 92 | pinctrl-0 = <&pinctrl_i2c1_1>; | ||
| 75 | status = "okay"; | 93 | status = "okay"; |
| 76 | 94 | ||
| 77 | accelerometer: mma8450@1c { | 95 | accelerometer: mma8450@1c { |
| @@ -158,10 +176,14 @@ | |||
| 158 | }; | 176 | }; |
| 159 | 177 | ||
| 160 | audmux@63fd0000 { | 178 | audmux@63fd0000 { |
| 179 | pinctrl-names = "default"; | ||
| 180 | pinctrl-0 = <&pinctrl_audmux_1>; | ||
| 161 | status = "okay"; | 181 | status = "okay"; |
| 162 | }; | 182 | }; |
| 163 | 183 | ||
| 164 | ethernet@63fec000 { | 184 | ethernet@63fec000 { |
| 185 | pinctrl-names = "default"; | ||
| 186 | pinctrl-0 = <&pinctrl_fec_1>; | ||
| 165 | phy-mode = "rmii"; | 187 | phy-mode = "rmii"; |
| 166 | phy-reset-gpios = <&gpio7 6 0>; | 188 | phy-reset-gpios = <&gpio7 6 0>; |
| 167 | status = "okay"; | 189 | status = "okay"; |
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts index 08091029168e..06c68580c842 100644 --- a/arch/arm/boot/dts/imx53-smd.dts +++ b/arch/arm/boot/dts/imx53-smd.dts | |||
| @@ -25,22 +25,30 @@ | |||
| 25 | aips@50000000 { /* AIPS1 */ | 25 | aips@50000000 { /* AIPS1 */ |
| 26 | spba@50000000 { | 26 | spba@50000000 { |
| 27 | esdhc@50004000 { /* ESDHC1 */ | 27 | esdhc@50004000 { /* ESDHC1 */ |
| 28 | pinctrl-names = "default"; | ||
| 29 | pinctrl-0 = <&pinctrl_esdhc1_1>; | ||
| 28 | cd-gpios = <&gpio3 13 0>; | 30 | cd-gpios = <&gpio3 13 0>; |
| 29 | wp-gpios = <&gpio4 11 0>; | 31 | wp-gpios = <&gpio4 11 0>; |
| 30 | status = "okay"; | 32 | status = "okay"; |
| 31 | }; | 33 | }; |
| 32 | 34 | ||
| 33 | esdhc@50008000 { /* ESDHC2 */ | 35 | esdhc@50008000 { /* ESDHC2 */ |
| 36 | pinctrl-names = "default"; | ||
| 37 | pinctrl-0 = <&pinctrl_esdhc2_1>; | ||
| 34 | non-removable; | 38 | non-removable; |
| 35 | status = "okay"; | 39 | status = "okay"; |
| 36 | }; | 40 | }; |
| 37 | 41 | ||
| 38 | uart3: serial@5000c000 { | 42 | uart3: serial@5000c000 { |
| 43 | pinctrl-names = "default"; | ||
| 44 | pinctrl-0 = <&pinctrl_uart3_1>; | ||
| 39 | fsl,uart-has-rtscts; | 45 | fsl,uart-has-rtscts; |
| 40 | status = "okay"; | 46 | status = "okay"; |
| 41 | }; | 47 | }; |
| 42 | 48 | ||
| 43 | ecspi@50010000 { /* ECSPI1 */ | 49 | ecspi@50010000 { /* ECSPI1 */ |
| 50 | pinctrl-names = "default"; | ||
| 51 | pinctrl-0 = <&pinctrl_ecspi1_1>; | ||
| 44 | fsl,spi-num-chipselects = <2>; | 52 | fsl,spi-num-chipselects = <2>; |
| 45 | cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; | 53 | cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; |
| 46 | status = "okay"; | 54 | status = "okay"; |
| @@ -72,35 +80,49 @@ | |||
| 72 | }; | 80 | }; |
| 73 | 81 | ||
| 74 | esdhc@50020000 { /* ESDHC3 */ | 82 | esdhc@50020000 { /* ESDHC3 */ |
| 83 | pinctrl-names = "default"; | ||
| 84 | pinctrl-0 = <&pinctrl_esdhc3_1>; | ||
| 75 | non-removable; | 85 | non-removable; |
| 76 | status = "okay"; | 86 | status = "okay"; |
| 77 | }; | 87 | }; |
| 78 | }; | 88 | }; |
| 79 | 89 | ||
| 80 | wdog@53f98000 { /* WDOG1 */ | ||
| 81 | status = "okay"; | ||
| 82 | }; | ||
| 83 | |||
| 84 | iomuxc@53fa8000 { | 90 | iomuxc@53fa8000 { |
| 85 | compatible = "fsl,imx53-iomuxc-smd"; | 91 | pinctrl-names = "default"; |
| 86 | reg = <0x53fa8000 0x4000>; | 92 | pinctrl-0 = <&pinctrl_hog>; |
| 93 | |||
| 94 | hog { | ||
| 95 | pinctrl_hog: hoggrp { | ||
| 96 | fsl,pins = < | ||
| 97 | 982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */ | ||
| 98 | 989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */ | ||
| 99 | 424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */ | ||
| 100 | 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */ | ||
| 101 | 449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */ | ||
| 102 | 43 0x80000000 /* MX53_PAD_KEY_ROW2__GPIO4_11 */ | ||
| 103 | 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */ | ||
| 104 | >; | ||
| 105 | }; | ||
| 106 | }; | ||
| 87 | }; | 107 | }; |
| 88 | 108 | ||
| 89 | uart1: serial@53fbc000 { | 109 | uart1: serial@53fbc000 { |
| 110 | pinctrl-names = "default"; | ||
| 111 | pinctrl-0 = <&pinctrl_uart1_1>; | ||
| 90 | status = "okay"; | 112 | status = "okay"; |
| 91 | }; | 113 | }; |
| 92 | 114 | ||
| 93 | uart2: serial@53fc0000 { | 115 | uart2: serial@53fc0000 { |
| 116 | pinctrl-names = "default"; | ||
| 117 | pinctrl-0 = <&pinctrl_uart2_1>; | ||
| 94 | status = "okay"; | 118 | status = "okay"; |
| 95 | }; | 119 | }; |
| 96 | }; | 120 | }; |
| 97 | 121 | ||
| 98 | aips@60000000 { /* AIPS2 */ | 122 | aips@60000000 { /* AIPS2 */ |
| 99 | sdma@63fb0000 { | ||
| 100 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; | ||
| 101 | }; | ||
| 102 | |||
| 103 | i2c@63fc4000 { /* I2C2 */ | 123 | i2c@63fc4000 { /* I2C2 */ |
| 124 | pinctrl-names = "default"; | ||
| 125 | pinctrl-0 = <&pinctrl_i2c2_1>; | ||
| 104 | status = "okay"; | 126 | status = "okay"; |
| 105 | 127 | ||
| 106 | codec: sgtl5000@0a { | 128 | codec: sgtl5000@0a { |
| @@ -120,6 +142,8 @@ | |||
| 120 | }; | 142 | }; |
| 121 | 143 | ||
| 122 | i2c@63fc8000 { /* I2C1 */ | 144 | i2c@63fc8000 { /* I2C1 */ |
| 145 | pinctrl-names = "default"; | ||
| 146 | pinctrl-0 = <&pinctrl_i2c1_1>; | ||
| 123 | status = "okay"; | 147 | status = "okay"; |
| 124 | 148 | ||
| 125 | accelerometer: mma8450@1c { | 149 | accelerometer: mma8450@1c { |
| @@ -139,6 +163,8 @@ | |||
| 139 | }; | 163 | }; |
| 140 | 164 | ||
| 141 | ethernet@63fec000 { | 165 | ethernet@63fec000 { |
| 166 | pinctrl-names = "default"; | ||
| 167 | pinctrl-0 = <&pinctrl_fec_1>; | ||
| 142 | phy-mode = "rmii"; | 168 | phy-mode = "rmii"; |
| 143 | phy-reset-gpios = <&gpio7 6 0>; | 169 | phy-reset-gpios = <&gpio7 6 0>; |
| 144 | status = "okay"; | 170 | status = "okay"; |
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index cd37165edce5..221cf3321b0a 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi | |||
| @@ -135,6 +135,34 @@ | |||
| 135 | }; | 135 | }; |
| 136 | }; | 136 | }; |
| 137 | 137 | ||
| 138 | usb@53f80000 { | ||
| 139 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; | ||
| 140 | reg = <0x53f80000 0x0200>; | ||
| 141 | interrupts = <18>; | ||
| 142 | status = "disabled"; | ||
| 143 | }; | ||
| 144 | |||
| 145 | usb@53f80200 { | ||
| 146 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; | ||
| 147 | reg = <0x53f80200 0x0200>; | ||
| 148 | interrupts = <14>; | ||
| 149 | status = "disabled"; | ||
| 150 | }; | ||
| 151 | |||
| 152 | usb@53f80400 { | ||
| 153 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; | ||
| 154 | reg = <0x53f80400 0x0200>; | ||
| 155 | interrupts = <16>; | ||
| 156 | status = "disabled"; | ||
| 157 | }; | ||
| 158 | |||
| 159 | usb@53f80600 { | ||
| 160 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; | ||
| 161 | reg = <0x53f80600 0x0200>; | ||
| 162 | interrupts = <17>; | ||
| 163 | status = "disabled"; | ||
| 164 | }; | ||
| 165 | |||
| 138 | gpio1: gpio@53f84000 { | 166 | gpio1: gpio@53f84000 { |
| 139 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; | 167 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 140 | reg = <0x53f84000 0x4000>; | 168 | reg = <0x53f84000 0x4000>; |
| @@ -179,7 +207,6 @@ | |||
| 179 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; | 207 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; |
| 180 | reg = <0x53f98000 0x4000>; | 208 | reg = <0x53f98000 0x4000>; |
| 181 | interrupts = <58>; | 209 | interrupts = <58>; |
| 182 | status = "disabled"; | ||
| 183 | }; | 210 | }; |
| 184 | 211 | ||
| 185 | wdog@53f9c000 { /* WDOG2 */ | 212 | wdog@53f9c000 { /* WDOG2 */ |
| @@ -189,6 +216,161 @@ | |||
| 189 | status = "disabled"; | 216 | status = "disabled"; |
| 190 | }; | 217 | }; |
| 191 | 218 | ||
| 219 | iomuxc@53fa8000 { | ||
| 220 | compatible = "fsl,imx53-iomuxc"; | ||
| 221 | reg = <0x53fa8000 0x4000>; | ||
| 222 | |||
| 223 | audmux { | ||
| 224 | pinctrl_audmux_1: audmuxgrp-1 { | ||
| 225 | fsl,pins = < | ||
| 226 | 10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */ | ||
| 227 | 17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */ | ||
| 228 | 23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */ | ||
| 229 | 30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */ | ||
| 230 | >; | ||
| 231 | }; | ||
| 232 | }; | ||
| 233 | |||
| 234 | fec { | ||
| 235 | pinctrl_fec_1: fecgrp-1 { | ||
| 236 | fsl,pins = < | ||
| 237 | 820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */ | ||
| 238 | 779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */ | ||
| 239 | 786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */ | ||
| 240 | 791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */ | ||
| 241 | 796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */ | ||
| 242 | 799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */ | ||
| 243 | 804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */ | ||
| 244 | 808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */ | ||
| 245 | 811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */ | ||
| 246 | 816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */ | ||
| 247 | >; | ||
| 248 | }; | ||
| 249 | }; | ||
| 250 | |||
| 251 | ecspi1 { | ||
| 252 | pinctrl_ecspi1_1: ecspi1grp-1 { | ||
| 253 | fsl,pins = < | ||
| 254 | 433 0x80000000 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */ | ||
| 255 | 439 0x80000000 /* MX53_PAD_EIM_D17__ECSPI1_MISO */ | ||
| 256 | 445 0x80000000 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */ | ||
| 257 | >; | ||
| 258 | }; | ||
| 259 | }; | ||
| 260 | |||
| 261 | esdhc1 { | ||
| 262 | pinctrl_esdhc1_1: esdhc1grp-1 { | ||
| 263 | fsl,pins = < | ||
| 264 | 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */ | ||
| 265 | 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */ | ||
| 266 | 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */ | ||
| 267 | 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */ | ||
| 268 | 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */ | ||
| 269 | 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */ | ||
| 270 | >; | ||
| 271 | }; | ||
| 272 | |||
| 273 | pinctrl_esdhc1_2: esdhc1grp-2 { | ||
| 274 | fsl,pins = < | ||
| 275 | 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */ | ||
| 276 | 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */ | ||
| 277 | 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */ | ||
| 278 | 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */ | ||
| 279 | 941 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */ | ||
| 280 | 948 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */ | ||
| 281 | 955 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */ | ||
| 282 | 962 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */ | ||
| 283 | 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */ | ||
| 284 | 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */ | ||
| 285 | >; | ||
| 286 | }; | ||
| 287 | }; | ||
| 288 | |||
| 289 | esdhc2 { | ||
| 290 | pinctrl_esdhc2_1: esdhc2grp-1 { | ||
| 291 | fsl,pins = < | ||
| 292 | 1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */ | ||
| 293 | 1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */ | ||
| 294 | 1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */ | ||
| 295 | 1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */ | ||
| 296 | 1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */ | ||
| 297 | 1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */ | ||
| 298 | >; | ||
| 299 | }; | ||
| 300 | }; | ||
| 301 | |||
| 302 | esdhc3 { | ||
| 303 | pinctrl_esdhc3_1: esdhc3grp-1 { | ||
| 304 | fsl,pins = < | ||
| 305 | 943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */ | ||
| 306 | 950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */ | ||
| 307 | 957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */ | ||
| 308 | 964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */ | ||
| 309 | 893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */ | ||
| 310 | 900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */ | ||
| 311 | 906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */ | ||
| 312 | 912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */ | ||
| 313 | 857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */ | ||
| 314 | 863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */ | ||
| 315 | >; | ||
| 316 | }; | ||
| 317 | }; | ||
| 318 | |||
| 319 | i2c1 { | ||
| 320 | pinctrl_i2c1_1: i2c1grp-1 { | ||
| 321 | fsl,pins = < | ||
| 322 | 333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */ | ||
| 323 | 341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */ | ||
| 324 | >; | ||
| 325 | }; | ||
| 326 | }; | ||
| 327 | |||
| 328 | i2c2 { | ||
| 329 | pinctrl_i2c2_1: i2c2grp-1 { | ||
| 330 | fsl,pins = < | ||
| 331 | 61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */ | ||
| 332 | 53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */ | ||
| 333 | >; | ||
| 334 | }; | ||
| 335 | }; | ||
| 336 | |||
| 337 | uart1 { | ||
| 338 | pinctrl_uart1_1: uart1grp-1 { | ||
| 339 | fsl,pins = < | ||
| 340 | 346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */ | ||
| 341 | 354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */ | ||
| 342 | >; | ||
| 343 | }; | ||
| 344 | |||
| 345 | pinctrl_uart1_2: uart1grp-2 { | ||
| 346 | fsl,pins = < | ||
| 347 | 828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */ | ||
| 348 | 832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */ | ||
| 349 | >; | ||
| 350 | }; | ||
| 351 | }; | ||
| 352 | |||
| 353 | uart2 { | ||
| 354 | pinctrl_uart2_1: uart2grp-1 { | ||
| 355 | fsl,pins = < | ||
| 356 | 841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */ | ||
| 357 | 836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */ | ||
| 358 | >; | ||
| 359 | }; | ||
| 360 | }; | ||
| 361 | |||
| 362 | uart3 { | ||
| 363 | pinctrl_uart3_1: uart3grp-1 { | ||
| 364 | fsl,pins = < | ||
| 365 | 884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */ | ||
| 366 | 888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */ | ||
| 367 | 875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */ | ||
| 368 | 880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */ | ||
| 369 | >; | ||
| 370 | }; | ||
| 371 | }; | ||
| 372 | }; | ||
| 373 | |||
| 192 | uart1: serial@53fbc000 { | 374 | uart1: serial@53fbc000 { |
| 193 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; | 375 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 194 | reg = <0x53fbc000 0x4000>; | 376 | reg = <0x53fbc000 0x4000>; |
| @@ -203,6 +385,20 @@ | |||
| 203 | status = "disabled"; | 385 | status = "disabled"; |
| 204 | }; | 386 | }; |
| 205 | 387 | ||
| 388 | can1: can@53fc8000 { | ||
| 389 | compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; | ||
| 390 | reg = <0x53fc8000 0x4000>; | ||
| 391 | interrupts = <82>; | ||
| 392 | status = "disabled"; | ||
| 393 | }; | ||
| 394 | |||
| 395 | can2: can@53fcc000 { | ||
| 396 | compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; | ||
| 397 | reg = <0x53fcc000 0x4000>; | ||
| 398 | interrupts = <83>; | ||
| 399 | status = "disabled"; | ||
| 400 | }; | ||
| 401 | |||
| 206 | gpio5: gpio@53fdc000 { | 402 | gpio5: gpio@53fdc000 { |
| 207 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; | 403 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 208 | reg = <0x53fdc000 0x4000>; | 404 | reg = <0x53fdc000 0x4000>; |
| @@ -277,6 +473,7 @@ | |||
| 277 | compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; | 473 | compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; |
| 278 | reg = <0x63fb0000 0x4000>; | 474 | reg = <0x63fb0000 0x4000>; |
| 279 | interrupts = <6>; | 475 | interrupts = <6>; |
| 476 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; | ||
| 280 | }; | 477 | }; |
| 281 | 478 | ||
| 282 | cspi@63fc0000 { | 479 | cspi@63fc0000 { |
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts index d792581672cc..15df4c105e89 100644 --- a/arch/arm/boot/dts/imx6q-arm2.dts +++ b/arch/arm/boot/dts/imx6q-arm2.dts | |||
| @@ -28,8 +28,27 @@ | |||
| 28 | status = "disabled"; /* gpmi nand conflicts with SD */ | 28 | status = "disabled"; /* gpmi nand conflicts with SD */ |
| 29 | }; | 29 | }; |
| 30 | 30 | ||
| 31 | aips-bus@02000000 { /* AIPS1 */ | ||
| 32 | iomuxc@020e0000 { | ||
| 33 | pinctrl-names = "default"; | ||
| 34 | pinctrl-0 = <&pinctrl_hog>; | ||
| 35 | |||
| 36 | hog { | ||
| 37 | pinctrl_hog: hoggrp { | ||
| 38 | fsl,pins = < | ||
| 39 | 176 0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */ | ||
| 40 | 1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */ | ||
| 41 | 1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */ | ||
| 42 | >; | ||
| 43 | }; | ||
| 44 | }; | ||
| 45 | }; | ||
| 46 | }; | ||
| 47 | |||
| 31 | aips-bus@02100000 { /* AIPS2 */ | 48 | aips-bus@02100000 { /* AIPS2 */ |
| 32 | ethernet@02188000 { | 49 | ethernet@02188000 { |
| 50 | pinctrl-names = "default"; | ||
| 51 | pinctrl-0 = <&pinctrl_enet_2>; | ||
| 33 | phy-mode = "rgmii"; | 52 | phy-mode = "rgmii"; |
| 34 | status = "okay"; | 53 | status = "okay"; |
| 35 | }; | 54 | }; |
| @@ -52,6 +71,8 @@ | |||
| 52 | }; | 71 | }; |
| 53 | 72 | ||
| 54 | uart4: serial@021f0000 { | 73 | uart4: serial@021f0000 { |
| 74 | pinctrl-names = "default"; | ||
| 75 | pinctrl-0 = <&pinctrl_uart4_1>; | ||
| 55 | status = "okay"; | 76 | status = "okay"; |
| 56 | }; | 77 | }; |
| 57 | }; | 78 | }; |
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts index cfdbe539c43e..0fb29ca7a9e1 100644 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts | |||
| @@ -46,15 +46,20 @@ | |||
| 46 | 46 | ||
| 47 | iomuxc@020e0000 { | 47 | iomuxc@020e0000 { |
| 48 | pinctrl-names = "default"; | 48 | pinctrl-names = "default"; |
| 49 | pinctrl-0 = <&pinctrl_gpio_hog>; | 49 | pinctrl-0 = <&pinctrl_hog>; |
| 50 | 50 | ||
| 51 | gpios { | 51 | hog { |
| 52 | pinctrl_gpio_hog: gpiohog { | 52 | pinctrl_hog: hoggrp { |
| 53 | fsl,pins = < | 53 | fsl,pins = < |
| 54 | 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */ | 54 | 1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */ |
| 55 | 121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */ | 55 | 1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */ |
| 56 | 953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */ | 56 | 121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */ |
| 57 | >; | 57 | 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */ |
| 58 | 152 0x80000000 /* MX6Q_PAD_EIM_D23__GPIO_3_23 */ | ||
| 59 | 1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */ | ||
| 60 | 1270 0x1f0b0 /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */ | ||
| 61 | 953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */ | ||
| 62 | >; | ||
| 58 | }; | 63 | }; |
| 59 | }; | 64 | }; |
| 60 | }; | 65 | }; |
| @@ -71,12 +76,16 @@ | |||
| 71 | }; | 76 | }; |
| 72 | 77 | ||
| 73 | ethernet@02188000 { | 78 | ethernet@02188000 { |
| 79 | pinctrl-names = "default"; | ||
| 80 | pinctrl-0 = <&pinctrl_enet_1>; | ||
| 74 | phy-mode = "rgmii"; | 81 | phy-mode = "rgmii"; |
| 75 | phy-reset-gpios = <&gpio3 23 0>; | 82 | phy-reset-gpios = <&gpio3 23 0>; |
| 76 | status = "okay"; | 83 | status = "okay"; |
| 77 | }; | 84 | }; |
| 78 | 85 | ||
| 79 | usdhc@02198000 { /* uSDHC3 */ | 86 | usdhc@02198000 { /* uSDHC3 */ |
| 87 | pinctrl-names = "default"; | ||
| 88 | pinctrl-0 = <&pinctrl_usdhc3_2>; | ||
| 80 | cd-gpios = <&gpio7 0 0>; | 89 | cd-gpios = <&gpio7 0 0>; |
| 81 | wp-gpios = <&gpio7 1 0>; | 90 | wp-gpios = <&gpio7 1 0>; |
| 82 | vmmc-supply = <®_3p3v>; | 91 | vmmc-supply = <®_3p3v>; |
| @@ -84,6 +93,8 @@ | |||
| 84 | }; | 93 | }; |
| 85 | 94 | ||
| 86 | usdhc@0219c000 { /* uSDHC4 */ | 95 | usdhc@0219c000 { /* uSDHC4 */ |
| 96 | pinctrl-names = "default"; | ||
| 97 | pinctrl-0 = <&pinctrl_usdhc4_2>; | ||
| 87 | cd-gpios = <&gpio2 6 0>; | 98 | cd-gpios = <&gpio2 6 0>; |
| 88 | wp-gpios = <&gpio2 7 0>; | 99 | wp-gpios = <&gpio2 7 0>; |
| 89 | vmmc-supply = <®_3p3v>; | 100 | vmmc-supply = <®_3p3v>; |
| @@ -99,7 +110,7 @@ | |||
| 99 | uart2: serial@021e8000 { | 110 | uart2: serial@021e8000 { |
| 100 | status = "okay"; | 111 | status = "okay"; |
| 101 | pinctrl-names = "default"; | 112 | pinctrl-names = "default"; |
| 102 | pinctrl-0 = <&pinctrl_serial2_1>; | 113 | pinctrl-0 = <&pinctrl_uart2_1>; |
| 103 | }; | 114 | }; |
| 104 | 115 | ||
| 105 | i2c@021a0000 { /* I2C1 */ | 116 | i2c@021a0000 { /* I2C1 */ |
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts index 07509a181178..e596c28c214d 100644 --- a/arch/arm/boot/dts/imx6q-sabresd.dts +++ b/arch/arm/boot/dts/imx6q-sabresd.dts | |||
| @@ -22,28 +22,51 @@ | |||
| 22 | }; | 22 | }; |
| 23 | 23 | ||
| 24 | soc { | 24 | soc { |
| 25 | |||
| 26 | aips-bus@02000000 { /* AIPS1 */ | 25 | aips-bus@02000000 { /* AIPS1 */ |
| 27 | spba-bus@02000000 { | 26 | spba-bus@02000000 { |
| 28 | uart1: serial@02020000 { | 27 | uart1: serial@02020000 { |
| 28 | pinctrl-names = "default"; | ||
| 29 | pinctrl-0 = <&pinctrl_uart1_1>; | ||
| 29 | status = "okay"; | 30 | status = "okay"; |
| 30 | }; | 31 | }; |
| 31 | }; | 32 | }; |
| 33 | |||
| 34 | iomuxc@020e0000 { | ||
| 35 | pinctrl-names = "default"; | ||
| 36 | pinctrl-0 = <&pinctrl_hog>; | ||
| 37 | |||
| 38 | hog { | ||
| 39 | pinctrl_hog: hoggrp { | ||
| 40 | fsl,pins = < | ||
| 41 | 1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */ | ||
| 42 | 1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */ | ||
| 43 | 1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */ | ||
| 44 | 1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */ | ||
| 45 | >; | ||
| 46 | }; | ||
| 47 | }; | ||
| 48 | }; | ||
| 32 | }; | 49 | }; |
| 33 | 50 | ||
| 34 | aips-bus@02100000 { /* AIPS2 */ | 51 | aips-bus@02100000 { /* AIPS2 */ |
| 35 | ethernet@02188000 { | 52 | ethernet@02188000 { |
| 53 | pinctrl-names = "default"; | ||
| 54 | pinctrl-0 = <&pinctrl_enet_1>; | ||
| 36 | phy-mode = "rgmii"; | 55 | phy-mode = "rgmii"; |
| 37 | status = "okay"; | 56 | status = "okay"; |
| 38 | }; | 57 | }; |
| 39 | 58 | ||
| 40 | usdhc@02194000 { /* uSDHC2 */ | 59 | usdhc@02194000 { /* uSDHC2 */ |
| 60 | pinctrl-names = "default"; | ||
| 61 | pinctrl-0 = <&pinctrl_usdhc2_1>; | ||
| 41 | cd-gpios = <&gpio2 2 0>; | 62 | cd-gpios = <&gpio2 2 0>; |
| 42 | wp-gpios = <&gpio2 3 0>; | 63 | wp-gpios = <&gpio2 3 0>; |
| 43 | status = "okay"; | 64 | status = "okay"; |
| 44 | }; | 65 | }; |
| 45 | 66 | ||
| 46 | usdhc@02198000 { /* uSDHC3 */ | 67 | usdhc@02198000 { /* uSDHC3 */ |
| 68 | pinctrl-names = "default"; | ||
| 69 | pinctrl-0 = <&pinctrl_usdhc3_1>; | ||
| 47 | cd-gpios = <&gpio2 0 0>; | 70 | cd-gpios = <&gpio2 0 0>; |
| 48 | wp-gpios = <&gpio2 1 0>; | 71 | wp-gpios = <&gpio2 1 0>; |
| 49 | status = "okay"; | 72 | status = "okay"; |
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 925da33420e2..e45476dc6d32 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi | |||
| @@ -383,7 +383,6 @@ | |||
| 383 | reg = <0x020bc000 0x4000>; | 383 | reg = <0x020bc000 0x4000>; |
| 384 | interrupts = <0 80 0x04>; | 384 | interrupts = <0 80 0x04>; |
| 385 | clocks = <&clks 0>; | 385 | clocks = <&clks 0>; |
| 386 | status = "disabled"; | ||
| 387 | }; | 386 | }; |
| 388 | 387 | ||
| 389 | wdog@020c0000 { /* WDOG2 */ | 388 | wdog@020c0000 { /* WDOG2 */ |
| @@ -539,86 +538,199 @@ | |||
| 539 | /* shared pinctrl settings */ | 538 | /* shared pinctrl settings */ |
| 540 | audmux { | 539 | audmux { |
| 541 | pinctrl_audmux_1: audmux-1 { | 540 | pinctrl_audmux_1: audmux-1 { |
| 542 | fsl,pins = <18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */ | 541 | fsl,pins = < |
| 543 | 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */ | 542 | 18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */ |
| 544 | 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */ | 543 | 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */ |
| 545 | 3 0x80000000>; /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */ | 544 | 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */ |
| 545 | 3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */ | ||
| 546 | >; | ||
| 547 | }; | ||
| 548 | }; | ||
| 549 | |||
| 550 | ecspi1 { | ||
| 551 | pinctrl_ecspi1_1: ecspi1grp-1 { | ||
| 552 | fsl,pins = < | ||
| 553 | 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */ | ||
| 554 | 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */ | ||
| 555 | 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */ | ||
| 556 | >; | ||
| 557 | }; | ||
| 558 | }; | ||
| 559 | |||
| 560 | enet { | ||
| 561 | pinctrl_enet_1: enetgrp-1 { | ||
| 562 | fsl,pins = < | ||
| 563 | 695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */ | ||
| 564 | 756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */ | ||
| 565 | 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */ | ||
| 566 | 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */ | ||
| 567 | 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */ | ||
| 568 | 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */ | ||
| 569 | 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */ | ||
| 570 | 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */ | ||
| 571 | 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */ | ||
| 572 | 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */ | ||
| 573 | 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */ | ||
| 574 | 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */ | ||
| 575 | 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */ | ||
| 576 | 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */ | ||
| 577 | 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ | ||
| 578 | >; | ||
| 579 | }; | ||
| 580 | |||
| 581 | pinctrl_enet_2: enetgrp-2 { | ||
| 582 | fsl,pins = < | ||
| 583 | 890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */ | ||
| 584 | 909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */ | ||
| 585 | 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */ | ||
| 586 | 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */ | ||
| 587 | 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */ | ||
| 588 | 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */ | ||
| 589 | 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */ | ||
| 590 | 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */ | ||
| 591 | 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */ | ||
| 592 | 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */ | ||
| 593 | 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */ | ||
| 594 | 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */ | ||
| 595 | 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */ | ||
| 596 | 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */ | ||
| 597 | 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ | ||
| 598 | >; | ||
| 546 | }; | 599 | }; |
| 547 | }; | 600 | }; |
| 548 | 601 | ||
| 549 | gpmi-nand { | 602 | gpmi-nand { |
| 550 | pinctrl_gpmi_nand_1: gpmi-nand-1 { | 603 | pinctrl_gpmi_nand_1: gpmi-nand-1 { |
| 551 | fsl,pins = <1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */ | 604 | fsl,pins = < |
| 552 | 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */ | 605 | 1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */ |
| 553 | 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */ | 606 | 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */ |
| 554 | 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */ | 607 | 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */ |
| 555 | 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */ | 608 | 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */ |
| 556 | 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */ | 609 | 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */ |
| 557 | 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */ | 610 | 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */ |
| 558 | 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */ | 611 | 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */ |
| 559 | 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */ | 612 | 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */ |
| 560 | 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */ | 613 | 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */ |
| 561 | 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */ | 614 | 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */ |
| 562 | 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */ | 615 | 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */ |
| 563 | 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */ | 616 | 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */ |
| 564 | 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */ | 617 | 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */ |
| 565 | 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */ | 618 | 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */ |
| 566 | 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */ | 619 | 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */ |
| 567 | 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */ | 620 | 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */ |
| 568 | 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */ | 621 | 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */ |
| 569 | 1463 0x00b1>; /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */ | 622 | 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */ |
| 623 | 1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */ | ||
| 624 | >; | ||
| 570 | }; | 625 | }; |
| 571 | }; | 626 | }; |
| 572 | 627 | ||
| 573 | i2c1 { | 628 | i2c1 { |
| 574 | pinctrl_i2c1_1: i2c1grp-1 { | 629 | pinctrl_i2c1_1: i2c1grp-1 { |
| 575 | fsl,pins = <137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */ | 630 | fsl,pins = < |
| 576 | 196 0x4001b8b1>; /* MX6Q_PAD_EIM_D28__I2C1_SDA */ | 631 | 137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */ |
| 632 | 196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */ | ||
| 633 | >; | ||
| 577 | }; | 634 | }; |
| 578 | }; | 635 | }; |
| 579 | 636 | ||
| 580 | serial2 { | 637 | uart1 { |
| 581 | pinctrl_serial2_1: serial2grp-1 { | 638 | pinctrl_uart1_1: uart1grp-1 { |
| 582 | fsl,pins = <183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */ | 639 | fsl,pins = < |
| 583 | 191 0x1b0b1>; /* MX6Q_PAD_EIM_D27__UART2_RXD */ | 640 | 1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */ |
| 641 | 1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */ | ||
| 642 | >; | ||
| 643 | }; | ||
| 644 | }; | ||
| 645 | |||
| 646 | uart2 { | ||
| 647 | pinctrl_uart2_1: uart2grp-1 { | ||
| 648 | fsl,pins = < | ||
| 649 | 183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */ | ||
| 650 | 191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */ | ||
| 651 | >; | ||
| 652 | }; | ||
| 653 | }; | ||
| 654 | |||
| 655 | uart4 { | ||
| 656 | pinctrl_uart4_1: uart4grp-1 { | ||
| 657 | fsl,pins = < | ||
| 658 | 877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */ | ||
| 659 | 885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */ | ||
| 660 | >; | ||
| 661 | }; | ||
| 662 | }; | ||
| 663 | |||
| 664 | usdhc2 { | ||
| 665 | pinctrl_usdhc2_1: usdhc2grp-1 { | ||
| 666 | fsl,pins = < | ||
| 667 | 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */ | ||
| 668 | 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */ | ||
| 669 | 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */ | ||
| 670 | 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */ | ||
| 671 | 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */ | ||
| 672 | 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */ | ||
| 673 | 1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */ | ||
| 674 | 1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */ | ||
| 675 | 1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */ | ||
| 676 | 1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */ | ||
| 677 | >; | ||
| 584 | }; | 678 | }; |
| 585 | }; | 679 | }; |
| 586 | 680 | ||
| 587 | usdhc3 { | 681 | usdhc3 { |
| 588 | pinctrl_usdhc3_1: usdhc3grp-1 { | 682 | pinctrl_usdhc3_1: usdhc3grp-1 { |
| 589 | fsl,pins = <1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ | 683 | fsl,pins = < |
| 590 | 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ | 684 | 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ |
| 591 | 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ | 685 | 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ |
| 592 | 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ | 686 | 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ |
| 593 | 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ | 687 | 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ |
| 594 | 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ | 688 | 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ |
| 595 | 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */ | 689 | 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ |
| 596 | 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */ | 690 | 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */ |
| 597 | 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */ | 691 | 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */ |
| 598 | 1241 0x17059>; /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */ | 692 | 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */ |
| 693 | 1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */ | ||
| 694 | >; | ||
| 695 | }; | ||
| 696 | |||
| 697 | pinctrl_usdhc3_2: usdhc3grp-2 { | ||
| 698 | fsl,pins = < | ||
| 699 | 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ | ||
| 700 | 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ | ||
| 701 | 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ | ||
| 702 | 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ | ||
| 703 | 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ | ||
| 704 | 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ | ||
| 705 | >; | ||
| 599 | }; | 706 | }; |
| 600 | }; | 707 | }; |
| 601 | 708 | ||
| 602 | usdhc4 { | 709 | usdhc4 { |
| 603 | pinctrl_usdhc4_1: usdhc4grp-1 { | 710 | pinctrl_usdhc4_1: usdhc4grp-1 { |
| 604 | fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ | 711 | fsl,pins = < |
| 605 | 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ | 712 | 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ |
| 606 | 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ | 713 | 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ |
| 607 | 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ | 714 | 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ |
| 608 | 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ | 715 | 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ |
| 609 | 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ | 716 | 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ |
| 610 | 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */ | 717 | 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ |
| 611 | 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */ | 718 | 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */ |
| 612 | 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */ | 719 | 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */ |
| 613 | 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ | 720 | 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */ |
| 721 | 1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ | ||
| 722 | >; | ||
| 614 | }; | 723 | }; |
| 615 | }; | ||
| 616 | 724 | ||
| 617 | ecspi1 { | 725 | pinctrl_usdhc4_2: usdhc4grp-2 { |
| 618 | pinctrl_ecspi1_1: ecspi1grp-1 { | 726 | fsl,pins = < |
| 619 | fsl,pins = <101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */ | 727 | 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ |
| 620 | 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */ | 728 | 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ |
| 621 | 94 0x100b1>; /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */ | 729 | 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ |
| 730 | 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ | ||
| 731 | 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ | ||
| 732 | 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ | ||
| 733 | >; | ||
| 622 | }; | 734 | }; |
| 623 | }; | 735 | }; |
| 624 | }; | 736 | }; |
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts index 52d947045106..f8ca6fa88192 100644 --- a/arch/arm/boot/dts/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/kirkwood-iconnect.dts | |||
| @@ -41,9 +41,13 @@ | |||
| 41 | }; | 41 | }; |
| 42 | power-blue { | 42 | power-blue { |
| 43 | label = "power:blue"; | 43 | label = "power:blue"; |
| 44 | gpios = <&gpio1 11 0>; | 44 | gpios = <&gpio1 10 0>; |
| 45 | linux,default-trigger = "timer"; | 45 | linux,default-trigger = "timer"; |
| 46 | }; | 46 | }; |
| 47 | power-red { | ||
| 48 | label = "power:red"; | ||
| 49 | gpios = <&gpio1 11 0>; | ||
| 50 | }; | ||
| 47 | usb1 { | 51 | usb1 { |
| 48 | label = "usb1:blue"; | 52 | label = "usb1:blue"; |
| 49 | gpios = <&gpio1 12 0>; | 53 | gpios = <&gpio1 12 0>; |
diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi index 80f74e256408..0514fb41627e 100644 --- a/arch/arm/boot/dts/mmp2.dtsi +++ b/arch/arm/boot/dts/mmp2.dtsi | |||
| @@ -26,6 +26,11 @@ | |||
| 26 | interrupt-parent = <&intc>; | 26 | interrupt-parent = <&intc>; |
| 27 | ranges; | 27 | ranges; |
| 28 | 28 | ||
| 29 | L2: l2-cache { | ||
| 30 | compatible = "marvell,tauros2-cache"; | ||
| 31 | marvell,tauros2-cache-features = <0x3>; | ||
| 32 | }; | ||
| 33 | |||
| 29 | axi@d4200000 { /* AXI */ | 34 | axi@d4200000 { /* AXI */ |
| 30 | compatible = "mrvl,axi-bus", "simple-bus"; | 35 | compatible = "mrvl,axi-bus", "simple-bus"; |
| 31 | #address-cells = <1>; | 36 | #address-cells = <1>; |
diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts index 802ec5b2fd00..a7ad85e4b8f9 100644 --- a/arch/arm/boot/dts/phy3250.dts +++ b/arch/arm/boot/dts/phy3250.dts | |||
| @@ -135,13 +135,11 @@ | |||
| 135 | ssp0: ssp@20084000 { | 135 | ssp0: ssp@20084000 { |
| 136 | #address-cells = <1>; | 136 | #address-cells = <1>; |
| 137 | #size-cells = <0>; | 137 | #size-cells = <0>; |
| 138 | pl022,num-chipselects = <1>; | 138 | num-cs = <1>; |
| 139 | cs-gpios = <&gpio 3 5 0>; | 139 | cs-gpios = <&gpio 3 5 0>; |
| 140 | 140 | ||
| 141 | eeprom: at25@0 { | 141 | eeprom: at25@0 { |
| 142 | pl022,hierarchy = <0>; | ||
| 143 | pl022,interface = <0>; | 142 | pl022,interface = <0>; |
| 144 | pl022,slave-tx-disable = <0>; | ||
| 145 | pl022,com-mode = <0>; | 143 | pl022,com-mode = <0>; |
| 146 | pl022,rx-level-trig = <1>; | 144 | pl022,rx-level-trig = <1>; |
| 147 | pl022,tx-level-trig = <1>; | 145 | pl022,tx-level-trig = <1>; |
diff --git a/arch/arm/boot/dts/prima2-cb.dts b/arch/arm/boot/dts/prima2-cb.dts deleted file mode 100644 index 34ae3a64ba25..000000000000 --- a/arch/arm/boot/dts/prima2-cb.dts +++ /dev/null | |||
| @@ -1,424 +0,0 @@ | |||
| 1 | /dts-v1/; | ||
| 2 | / { | ||
| 3 | model = "SiRF Prima2 eVB"; | ||
| 4 | compatible = "sirf,prima2-cb", "sirf,prima2"; | ||
| 5 | #address-cells = <1>; | ||
| 6 | #size-cells = <1>; | ||
| 7 | interrupt-parent = <&intc>; | ||
| 8 | |||
| 9 | memory { | ||
| 10 | reg = <0x00000000 0x20000000>; | ||
| 11 | }; | ||
| 12 | |||
| 13 | chosen { | ||
| 14 | bootargs = "mem=512M real_root=/dev/mmcblk0p2 console=ttyS0 panel=1 bootsplash=true bpp=16 androidboot.console=ttyS1"; | ||
| 15 | linux,stdout-path = &uart1; | ||
| 16 | }; | ||
| 17 | |||
| 18 | cpus { | ||
| 19 | #address-cells = <1>; | ||
| 20 | #size-cells = <0>; | ||
| 21 | |||
| 22 | cpu@0 { | ||
| 23 | reg = <0x0>; | ||
| 24 | d-cache-line-size = <32>; | ||
| 25 | i-cache-line-size = <32>; | ||
| 26 | d-cache-size = <32768>; | ||
| 27 | i-cache-size = <32768>; | ||
| 28 | /* from bootloader */ | ||
| 29 | timebase-frequency = <0>; | ||
| 30 | bus-frequency = <0>; | ||
| 31 | clock-frequency = <0>; | ||
| 32 | }; | ||
| 33 | }; | ||
| 34 | |||
| 35 | axi { | ||
| 36 | compatible = "simple-bus"; | ||
| 37 | #address-cells = <1>; | ||
| 38 | #size-cells = <1>; | ||
| 39 | ranges = <0x40000000 0x40000000 0x80000000>; | ||
| 40 | |||
| 41 | l2-cache-controller@80040000 { | ||
| 42 | compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache"; | ||
| 43 | reg = <0x80040000 0x1000>; | ||
| 44 | interrupts = <59>; | ||
| 45 | arm,tag-latency = <1 1 1>; | ||
| 46 | arm,data-latency = <1 1 1>; | ||
| 47 | arm,filter-ranges = <0 0x40000000>; | ||
| 48 | }; | ||
| 49 | |||
| 50 | intc: interrupt-controller@80020000 { | ||
| 51 | #interrupt-cells = <1>; | ||
| 52 | interrupt-controller; | ||
| 53 | compatible = "sirf,prima2-intc"; | ||
| 54 | reg = <0x80020000 0x1000>; | ||
| 55 | }; | ||
| 56 | |||
| 57 | sys-iobg { | ||
| 58 | compatible = "simple-bus"; | ||
| 59 | #address-cells = <1>; | ||
| 60 | #size-cells = <1>; | ||
| 61 | ranges = <0x88000000 0x88000000 0x40000>; | ||
| 62 | |||
| 63 | clock-controller@88000000 { | ||
| 64 | compatible = "sirf,prima2-clkc"; | ||
| 65 | reg = <0x88000000 0x1000>; | ||
| 66 | interrupts = <3>; | ||
| 67 | }; | ||
| 68 | |||
| 69 | reset-controller@88010000 { | ||
| 70 | compatible = "sirf,prima2-rstc"; | ||
| 71 | reg = <0x88010000 0x1000>; | ||
| 72 | }; | ||
| 73 | |||
| 74 | rsc-controller@88020000 { | ||
| 75 | compatible = "sirf,prima2-rsc"; | ||
| 76 | reg = <0x88020000 0x1000>; | ||
| 77 | }; | ||
| 78 | }; | ||
| 79 | |||
| 80 | mem-iobg { | ||
| 81 | compatible = "simple-bus"; | ||
| 82 | #address-cells = <1>; | ||
| 83 | #size-cells = <1>; | ||
| 84 | ranges = <0x90000000 0x90000000 0x10000>; | ||
| 85 | |||
| 86 | memory-controller@90000000 { | ||
| 87 | compatible = "sirf,prima2-memc"; | ||
| 88 | reg = <0x90000000 0x10000>; | ||
| 89 | interrupts = <27>; | ||
| 90 | }; | ||
| 91 | }; | ||
| 92 | |||
| 93 | disp-iobg { | ||
| 94 | compatible = "simple-bus"; | ||
| 95 | #address-cells = <1>; | ||
| 96 | #size-cells = <1>; | ||
| 97 | ranges = <0x90010000 0x90010000 0x30000>; | ||
| 98 | |||
| 99 | display@90010000 { | ||
| 100 | compatible = "sirf,prima2-lcd"; | ||
| 101 | reg = <0x90010000 0x20000>; | ||
| 102 | interrupts = <30>; | ||
| 103 | }; | ||
| 104 | |||
| 105 | vpp@90020000 { | ||
| 106 | compatible = "sirf,prima2-vpp"; | ||
| 107 | reg = <0x90020000 0x10000>; | ||
| 108 | interrupts = <31>; | ||
| 109 | }; | ||
| 110 | }; | ||
| 111 | |||
| 112 | graphics-iobg { | ||
| 113 | compatible = "simple-bus"; | ||
| 114 | #address-cells = <1>; | ||
| 115 | #size-cells = <1>; | ||
| 116 | ranges = <0x98000000 0x98000000 0x8000000>; | ||
| 117 | |||
| 118 | graphics@98000000 { | ||
| 119 | compatible = "powervr,sgx531"; | ||
| 120 | reg = <0x98000000 0x8000000>; | ||
| 121 | interrupts = <6>; | ||
| 122 | }; | ||
| 123 | }; | ||
| 124 | |||
| 125 | multimedia-iobg { | ||
| 126 | compatible = "simple-bus"; | ||
| 127 | #address-cells = <1>; | ||
| 128 | #size-cells = <1>; | ||
| 129 | ranges = <0xa0000000 0xa0000000 0x8000000>; | ||
| 130 | |||
| 131 | multimedia@a0000000 { | ||
| 132 | compatible = "sirf,prima2-video-codec"; | ||
| 133 | reg = <0xa0000000 0x8000000>; | ||
| 134 | interrupts = <5>; | ||
| 135 | }; | ||
| 136 | }; | ||
| 137 | |||
| 138 | dsp-iobg { | ||
| 139 | compatible = "simple-bus"; | ||
| 140 | #address-cells = <1>; | ||
| 141 | #size-cells = <1>; | ||
| 142 | ranges = <0xa8000000 0xa8000000 0x2000000>; | ||
| 143 | |||
| 144 | dspif@a8000000 { | ||
| 145 | compatible = "sirf,prima2-dspif"; | ||
| 146 | reg = <0xa8000000 0x10000>; | ||
| 147 | interrupts = <9>; | ||
| 148 | }; | ||
| 149 | |||
| 150 | gps@a8010000 { | ||
| 151 | compatible = "sirf,prima2-gps"; | ||
| 152 | reg = <0xa8010000 0x10000>; | ||
| 153 | interrupts = <7>; | ||
| 154 | }; | ||
| 155 | |||
| 156 | dsp@a9000000 { | ||
| 157 | compatible = "sirf,prima2-dsp"; | ||
| 158 | reg = <0xa9000000 0x1000000>; | ||
| 159 | interrupts = <8>; | ||
| 160 | }; | ||
| 161 | }; | ||
| 162 | |||
| 163 | peri-iobg { | ||
| 164 | compatible = "simple-bus"; | ||
| 165 | #address-cells = <1>; | ||
| 166 | #size-cells = <1>; | ||
| 167 | ranges = <0xb0000000 0xb0000000 0x180000>; | ||
| 168 | |||
| 169 | timer@b0020000 { | ||
| 170 | compatible = "sirf,prima2-tick"; | ||
| 171 | reg = <0xb0020000 0x1000>; | ||
| 172 | interrupts = <0>; | ||
| 173 | }; | ||
| 174 | |||
| 175 | nand@b0030000 { | ||
| 176 | compatible = "sirf,prima2-nand"; | ||
| 177 | reg = <0xb0030000 0x10000>; | ||
| 178 | interrupts = <41>; | ||
| 179 | }; | ||
| 180 | |||
| 181 | audio@b0040000 { | ||
| 182 | compatible = "sirf,prima2-audio"; | ||
| 183 | reg = <0xb0040000 0x10000>; | ||
| 184 | interrupts = <35>; | ||
| 185 | }; | ||
| 186 | |||
| 187 | uart0: uart@b0050000 { | ||
| 188 | cell-index = <0>; | ||
| 189 | compatible = "sirf,prima2-uart"; | ||
| 190 | reg = <0xb0050000 0x10000>; | ||
| 191 | interrupts = <17>; | ||
| 192 | }; | ||
| 193 | |||
| 194 | uart1: uart@b0060000 { | ||
| 195 | cell-index = <1>; | ||
| 196 | compatible = "sirf,prima2-uart"; | ||
| 197 | reg = <0xb0060000 0x10000>; | ||
| 198 | interrupts = <18>; | ||
| 199 | }; | ||
| 200 | |||
| 201 | uart2: uart@b0070000 { | ||
| 202 | cell-index = <2>; | ||
| 203 | compatible = "sirf,prima2-uart"; | ||
| 204 | reg = <0xb0070000 0x10000>; | ||
| 205 | interrupts = <19>; | ||
| 206 | }; | ||
| 207 | |||
| 208 | usp0: usp@b0080000 { | ||
| 209 | cell-index = <0>; | ||
| 210 | compatible = "sirf,prima2-usp"; | ||
| 211 | reg = <0xb0080000 0x10000>; | ||
| 212 | interrupts = <20>; | ||
| 213 | }; | ||
| 214 | |||
| 215 | usp1: usp@b0090000 { | ||
| 216 | cell-index = <1>; | ||
| 217 | compatible = "sirf,prima2-usp"; | ||
| 218 | reg = <0xb0090000 0x10000>; | ||
| 219 | interrupts = <21>; | ||
| 220 | }; | ||
| 221 | |||
| 222 | usp2: usp@b00a0000 { | ||
| 223 | cell-index = <2>; | ||
| 224 | compatible = "sirf,prima2-usp"; | ||
| 225 | reg = <0xb00a0000 0x10000>; | ||
| 226 | interrupts = <22>; | ||
| 227 | }; | ||
| 228 | |||
| 229 | dmac0: dma-controller@b00b0000 { | ||
| 230 | cell-index = <0>; | ||
| 231 | compatible = "sirf,prima2-dmac"; | ||
| 232 | reg = <0xb00b0000 0x10000>; | ||
| 233 | interrupts = <12>; | ||
| 234 | }; | ||
| 235 | |||
| 236 | dmac1: dma-controller@b0160000 { | ||
| 237 | cell-index = <1>; | ||
| 238 | compatible = "sirf,prima2-dmac"; | ||
| 239 | reg = <0xb0160000 0x10000>; | ||
| 240 | interrupts = <13>; | ||
| 241 | }; | ||
| 242 | |||
| 243 | vip@b00C0000 { | ||
| 244 | compatible = "sirf,prima2-vip"; | ||
| 245 | reg = <0xb00C0000 0x10000>; | ||
| 246 | }; | ||
| 247 | |||
| 248 | spi0: spi@b00d0000 { | ||
| 249 | cell-index = <0>; | ||
| 250 | compatible = "sirf,prima2-spi"; | ||
| 251 | reg = <0xb00d0000 0x10000>; | ||
| 252 | interrupts = <15>; | ||
| 253 | }; | ||
| 254 | |||
| 255 | spi1: spi@b0170000 { | ||
| 256 | cell-index = <1>; | ||
| 257 | compatible = "sirf,prima2-spi"; | ||
| 258 | reg = <0xb0170000 0x10000>; | ||
| 259 | interrupts = <16>; | ||
| 260 | }; | ||
| 261 | |||
| 262 | i2c0: i2c@b00e0000 { | ||
| 263 | cell-index = <0>; | ||
| 264 | compatible = "sirf,prima2-i2c"; | ||
| 265 | reg = <0xb00e0000 0x10000>; | ||
| 266 | interrupts = <24>; | ||
| 267 | }; | ||
| 268 | |||
| 269 | i2c1: i2c@b00f0000 { | ||
| 270 | cell-index = <1>; | ||
| 271 | compatible = "sirf,prima2-i2c"; | ||
| 272 | reg = <0xb00f0000 0x10000>; | ||
| 273 | interrupts = <25>; | ||
| 274 | }; | ||
| 275 | |||
| 276 | tsc@b0110000 { | ||
| 277 | compatible = "sirf,prima2-tsc"; | ||
| 278 | reg = <0xb0110000 0x10000>; | ||
| 279 | interrupts = <33>; | ||
| 280 | }; | ||
| 281 | |||
| 282 | gpio: gpio-controller@b0120000 { | ||
| 283 | #gpio-cells = <2>; | ||
| 284 | #interrupt-cells = <2>; | ||
| 285 | compatible = "sirf,prima2-gpio-pinmux"; | ||
| 286 | reg = <0xb0120000 0x10000>; | ||
| 287 | gpio-controller; | ||
| 288 | interrupt-controller; | ||
| 289 | }; | ||
| 290 | |||
| 291 | pwm@b0130000 { | ||
| 292 | compatible = "sirf,prima2-pwm"; | ||
| 293 | reg = <0xb0130000 0x10000>; | ||
| 294 | }; | ||
| 295 | |||
| 296 | efusesys@b0140000 { | ||
| 297 | compatible = "sirf,prima2-efuse"; | ||
| 298 | reg = <0xb0140000 0x10000>; | ||
| 299 | }; | ||
| 300 | |||
| 301 | pulsec@b0150000 { | ||
| 302 | compatible = "sirf,prima2-pulsec"; | ||
| 303 | reg = <0xb0150000 0x10000>; | ||
| 304 | interrupts = <48>; | ||
| 305 | }; | ||
| 306 | |||
| 307 | pci-iobg { | ||
| 308 | compatible = "sirf,prima2-pciiobg", "simple-bus"; | ||
| 309 | #address-cells = <1>; | ||
| 310 | #size-cells = <1>; | ||
| 311 | ranges = <0x56000000 0x56000000 0x1b00000>; | ||
| 312 | |||
| 313 | sd0: sdhci@56000000 { | ||
| 314 | cell-index = <0>; | ||
| 315 | compatible = "sirf,prima2-sdhc"; | ||
| 316 | reg = <0x56000000 0x100000>; | ||
| 317 | interrupts = <38>; | ||
| 318 | }; | ||
| 319 | |||
| 320 | sd1: sdhci@56100000 { | ||
| 321 | cell-index = <1>; | ||
| 322 | compatible = "sirf,prima2-sdhc"; | ||
| 323 | reg = <0x56100000 0x100000>; | ||
| 324 | interrupts = <38>; | ||
| 325 | }; | ||
| 326 | |||
| 327 | sd2: sdhci@56200000 { | ||
| 328 | cell-index = <2>; | ||
| 329 | compatible = "sirf,prima2-sdhc"; | ||
| 330 | reg = <0x56200000 0x100000>; | ||
| 331 | interrupts = <23>; | ||
| 332 | }; | ||
| 333 | |||
| 334 | sd3: sdhci@56300000 { | ||
| 335 | cell-index = <3>; | ||
| 336 | compatible = "sirf,prima2-sdhc"; | ||
| 337 | reg = <0x56300000 0x100000>; | ||
| 338 | interrupts = <23>; | ||
| 339 | }; | ||
| 340 | |||
| 341 | sd4: sdhci@56400000 { | ||
| 342 | cell-index = <4>; | ||
| 343 | compatible = "sirf,prima2-sdhc"; | ||
| 344 | reg = <0x56400000 0x100000>; | ||
| 345 | interrupts = <39>; | ||
| 346 | }; | ||
| 347 | |||
| 348 | sd5: sdhci@56500000 { | ||
| 349 | cell-index = <5>; | ||
| 350 | compatible = "sirf,prima2-sdhc"; | ||
| 351 | reg = <0x56500000 0x100000>; | ||
| 352 | interrupts = <39>; | ||
| 353 | }; | ||
| 354 | |||
| 355 | pci-copy@57900000 { | ||
| 356 | compatible = "sirf,prima2-pcicp"; | ||
| 357 | reg = <0x57900000 0x100000>; | ||
| 358 | interrupts = <40>; | ||
| 359 | }; | ||
| 360 | |||
| 361 | rom-interface@57a00000 { | ||
| 362 | compatible = "sirf,prima2-romif"; | ||
| 363 | reg = <0x57a00000 0x100000>; | ||
| 364 | }; | ||
| 365 | }; | ||
| 366 | }; | ||
| 367 | |||
| 368 | rtc-iobg { | ||
| 369 | compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus"; | ||
| 370 | #address-cells = <1>; | ||
| 371 | #size-cells = <1>; | ||
| 372 | reg = <0x80030000 0x10000>; | ||
| 373 | |||
| 374 | gpsrtc@1000 { | ||
| 375 | compatible = "sirf,prima2-gpsrtc"; | ||
| 376 | reg = <0x1000 0x1000>; | ||
| 377 | interrupts = <55 56 57>; | ||
| 378 | }; | ||
| 379 | |||
| 380 | sysrtc@2000 { | ||
| 381 | compatible = "sirf,prima2-sysrtc"; | ||
| 382 | reg = <0x2000 0x1000>; | ||
| 383 | interrupts = <52 53 54>; | ||
| 384 | }; | ||
| 385 | |||
| 386 | pwrc@3000 { | ||
| 387 | compatible = "sirf,prima2-pwrc"; | ||
| 388 | reg = <0x3000 0x1000>; | ||
| 389 | interrupts = <32>; | ||
| 390 | }; | ||
| 391 | }; | ||
| 392 | |||
| 393 | uus-iobg { | ||
| 394 | compatible = "simple-bus"; | ||
| 395 | #address-cells = <1>; | ||
| 396 | #size-cells = <1>; | ||
| 397 | ranges = <0xb8000000 0xb8000000 0x40000>; | ||
| 398 | |||
| 399 | usb0: usb@b00e0000 { | ||
| 400 | compatible = "chipidea,ci13611a-prima2"; | ||
| 401 | reg = <0xb8000000 0x10000>; | ||
| 402 | interrupts = <10>; | ||
| 403 | }; | ||
| 404 | |||
| 405 | usb1: usb@b00f0000 { | ||
| 406 | compatible = "chipidea,ci13611a-prima2"; | ||
| 407 | reg = <0xb8010000 0x10000>; | ||
| 408 | interrupts = <11>; | ||
| 409 | }; | ||
| 410 | |||
| 411 | sata@b00f0000 { | ||
| 412 | compatible = "synopsys,dwc-ahsata"; | ||
| 413 | reg = <0xb8020000 0x10000>; | ||
| 414 | interrupts = <37>; | ||
| 415 | }; | ||
| 416 | |||
| 417 | security@b00f0000 { | ||
| 418 | compatible = "sirf,prima2-security"; | ||
| 419 | reg = <0xb8030000 0x10000>; | ||
| 420 | interrupts = <42>; | ||
| 421 | }; | ||
| 422 | }; | ||
| 423 | }; | ||
| 424 | }; | ||
diff --git a/arch/arm/boot/dts/prima2-evb.dts b/arch/arm/boot/dts/prima2-evb.dts new file mode 100644 index 000000000000..57286b4e7b87 --- /dev/null +++ b/arch/arm/boot/dts/prima2-evb.dts | |||
| @@ -0,0 +1,37 @@ | |||
| 1 | /* | ||
| 2 | * DTS file for CSR SiRFprimaII Evaluation Board | ||
| 3 | * | ||
| 4 | * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. | ||
| 5 | * | ||
| 6 | * Licensed under GPLv2 or later. | ||
| 7 | */ | ||
| 8 | |||
| 9 | /dts-v1/; | ||
| 10 | |||
| 11 | /include/ "prima2.dtsi" | ||
| 12 | |||
| 13 | / { | ||
| 14 | model = "CSR SiRFprimaII Evaluation Board"; | ||
| 15 | compatible = "sirf,prima2", "sirf,prima2-cb"; | ||
| 16 | |||
| 17 | memory { | ||
| 18 | reg = <0x00000000 0x20000000>; | ||
| 19 | }; | ||
| 20 | |||
| 21 | axi { | ||
| 22 | peri-iobg { | ||
| 23 | uart@b0060000 { | ||
| 24 | pinctrl-names = "default"; | ||
| 25 | pinctrl-0 = <&uart1_pins_a>; | ||
| 26 | }; | ||
| 27 | spi@b00d0000 { | ||
| 28 | pinctrl-names = "default"; | ||
| 29 | pinctrl-0 = <&spi0_pins_a>; | ||
| 30 | }; | ||
| 31 | spi@b0170000 { | ||
| 32 | pinctrl-names = "default"; | ||
| 33 | pinctrl-0 = <&spi1_pins_a>; | ||
| 34 | }; | ||
| 35 | }; | ||
| 36 | }; | ||
| 37 | }; | ||
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi new file mode 100644 index 000000000000..055fca542120 --- /dev/null +++ b/arch/arm/boot/dts/prima2.dtsi | |||
| @@ -0,0 +1,640 @@ | |||
| 1 | /* | ||
| 2 | * DTS file for CSR SiRFprimaII SoC | ||
| 3 | * | ||
| 4 | * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. | ||
| 5 | * | ||
| 6 | * Licensed under GPLv2 or later. | ||
| 7 | */ | ||
| 8 | |||
| 9 | /include/ "skeleton.dtsi" | ||
| 10 | / { | ||
| 11 | compatible = "sirf,prima2"; | ||
| 12 | #address-cells = <1>; | ||
| 13 | #size-cells = <1>; | ||
| 14 | interrupt-parent = <&intc>; | ||
| 15 | |||
| 16 | cpus { | ||
| 17 | #address-cells = <1>; | ||
| 18 | #size-cells = <0>; | ||
| 19 | |||
| 20 | cpu@0 { | ||
| 21 | reg = <0x0>; | ||
| 22 | d-cache-line-size = <32>; | ||
| 23 | i-cache-line-size = <32>; | ||
| 24 | d-cache-size = <32768>; | ||
| 25 | i-cache-size = <32768>; | ||
| 26 | /* from bootloader */ | ||
| 27 | timebase-frequency = <0>; | ||
| 28 | bus-frequency = <0>; | ||
| 29 | clock-frequency = <0>; | ||
| 30 | }; | ||
| 31 | }; | ||
| 32 | |||
| 33 | axi { | ||
| 34 | compatible = "simple-bus"; | ||
| 35 | #address-cells = <1>; | ||
| 36 | #size-cells = <1>; | ||
| 37 | ranges = <0x40000000 0x40000000 0x80000000>; | ||
| 38 | |||
| 39 | l2-cache-controller@80040000 { | ||
| 40 | compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache"; | ||
| 41 | reg = <0x80040000 0x1000>; | ||
| 42 | interrupts = <59>; | ||
| 43 | arm,tag-latency = <1 1 1>; | ||
| 44 | arm,data-latency = <1 1 1>; | ||
| 45 | arm,filter-ranges = <0 0x40000000>; | ||
| 46 | }; | ||
| 47 | |||
| 48 | intc: interrupt-controller@80020000 { | ||
| 49 | #interrupt-cells = <1>; | ||
| 50 | interrupt-controller; | ||
| 51 | compatible = "sirf,prima2-intc"; | ||
| 52 | reg = <0x80020000 0x1000>; | ||
| 53 | }; | ||
| 54 | |||
| 55 | sys-iobg { | ||
| 56 | compatible = "simple-bus"; | ||
| 57 | #address-cells = <1>; | ||
| 58 | #size-cells = <1>; | ||
| 59 | ranges = <0x88000000 0x88000000 0x40000>; | ||
| 60 | |||
| 61 | clock-controller@88000000 { | ||
| 62 | compatible = "sirf,prima2-clkc"; | ||
| 63 | reg = <0x88000000 0x1000>; | ||
| 64 | interrupts = <3>; | ||
| 65 | }; | ||
| 66 | |||
| 67 | reset-controller@88010000 { | ||
| 68 | compatible = "sirf,prima2-rstc"; | ||
| 69 | reg = <0x88010000 0x1000>; | ||
| 70 | }; | ||
| 71 | |||
| 72 | rsc-controller@88020000 { | ||
| 73 | compatible = "sirf,prima2-rsc"; | ||
| 74 | reg = <0x88020000 0x1000>; | ||
| 75 | }; | ||
| 76 | }; | ||
| 77 | |||
| 78 | mem-iobg { | ||
| 79 | compatible = "simple-bus"; | ||
| 80 | #address-cells = <1>; | ||
| 81 | #size-cells = <1>; | ||
| 82 | ranges = <0x90000000 0x90000000 0x10000>; | ||
| 83 | |||
| 84 | memory-controller@90000000 { | ||
| 85 | compatible = "sirf,prima2-memc"; | ||
| 86 | reg = <0x90000000 0x10000>; | ||
| 87 | interrupts = <27>; | ||
| 88 | }; | ||
| 89 | }; | ||
| 90 | |||
| 91 | disp-iobg { | ||
| 92 | compatible = "simple-bus"; | ||
| 93 | #address-cells = <1>; | ||
| 94 | #size-cells = <1>; | ||
| 95 | ranges = <0x90010000 0x90010000 0x30000>; | ||
| 96 | |||
| 97 | display@90010000 { | ||
| 98 | compatible = "sirf,prima2-lcd"; | ||
| 99 | reg = <0x90010000 0x20000>; | ||
| 100 | interrupts = <30>; | ||
| 101 | }; | ||
| 102 | |||
| 103 | vpp@90020000 { | ||
| 104 | compatible = "sirf,prima2-vpp"; | ||
| 105 | reg = <0x90020000 0x10000>; | ||
| 106 | interrupts = <31>; | ||
| 107 | }; | ||
| 108 | }; | ||
| 109 | |||
| 110 | graphics-iobg { | ||
| 111 | compatible = "simple-bus"; | ||
| 112 | #address-cells = <1>; | ||
| 113 | #size-cells = <1>; | ||
| 114 | ranges = <0x98000000 0x98000000 0x8000000>; | ||
| 115 | |||
| 116 | graphics@98000000 { | ||
| 117 | compatible = "powervr,sgx531"; | ||
| 118 | reg = <0x98000000 0x8000000>; | ||
| 119 | interrupts = <6>; | ||
| 120 | }; | ||
| 121 | }; | ||
| 122 | |||
| 123 | multimedia-iobg { | ||
| 124 | compatible = "simple-bus"; | ||
| 125 | #address-cells = <1>; | ||
| 126 | #size-cells = <1>; | ||
| 127 | ranges = <0xa0000000 0xa0000000 0x8000000>; | ||
| 128 | |||
| 129 | multimedia@a0000000 { | ||
| 130 | compatible = "sirf,prima2-video-codec"; | ||
| 131 | reg = <0xa0000000 0x8000000>; | ||
| 132 | interrupts = <5>; | ||
| 133 | }; | ||
| 134 | }; | ||
| 135 | |||
| 136 | dsp-iobg { | ||
| 137 | compatible = "simple-bus"; | ||
| 138 | #address-cells = <1>; | ||
| 139 | #size-cells = <1>; | ||
| 140 | ranges = <0xa8000000 0xa8000000 0x2000000>; | ||
| 141 | |||
| 142 | dspif@a8000000 { | ||
| 143 | compatible = "sirf,prima2-dspif"; | ||
| 144 | reg = <0xa8000000 0x10000>; | ||
| 145 | interrupts = <9>; | ||
| 146 | }; | ||
| 147 | |||
| 148 | gps@a8010000 { | ||
| 149 | compatible = "sirf,prima2-gps"; | ||
| 150 | reg = <0xa8010000 0x10000>; | ||
| 151 | interrupts = <7>; | ||
| 152 | }; | ||
| 153 | |||
| 154 | dsp@a9000000 { | ||
| 155 | compatible = "sirf,prima2-dsp"; | ||
| 156 | reg = <0xa9000000 0x1000000>; | ||
| 157 | interrupts = <8>; | ||
| 158 | }; | ||
| 159 | }; | ||
| 160 | |||
| 161 | peri-iobg { | ||
| 162 | compatible = "simple-bus"; | ||
| 163 | #address-cells = <1>; | ||
| 164 | #size-cells = <1>; | ||
| 165 | ranges = <0xb0000000 0xb0000000 0x180000>; | ||
| 166 | |||
| 167 | timer@b0020000 { | ||
| 168 | compatible = "sirf,prima2-tick"; | ||
| 169 | reg = <0xb0020000 0x1000>; | ||
| 170 | interrupts = <0>; | ||
| 171 | }; | ||
| 172 | |||
| 173 | nand@b0030000 { | ||
| 174 | compatible = "sirf,prima2-nand"; | ||
| 175 | reg = <0xb0030000 0x10000>; | ||
| 176 | interrupts = <41>; | ||
| 177 | }; | ||
| 178 | |||
| 179 | audio@b0040000 { | ||
| 180 | compatible = "sirf,prima2-audio"; | ||
| 181 | reg = <0xb0040000 0x10000>; | ||
| 182 | interrupts = <35>; | ||
| 183 | }; | ||
| 184 | |||
| 185 | uart0: uart@b0050000 { | ||
| 186 | cell-index = <0>; | ||
| 187 | compatible = "sirf,prima2-uart"; | ||
| 188 | reg = <0xb0050000 0x10000>; | ||
| 189 | interrupts = <17>; | ||
| 190 | }; | ||
| 191 | |||
| 192 | uart1: uart@b0060000 { | ||
| 193 | cell-index = <1>; | ||
| 194 | compatible = "sirf,prima2-uart"; | ||
| 195 | reg = <0xb0060000 0x10000>; | ||
| 196 | interrupts = <18>; | ||
| 197 | }; | ||
| 198 | |||
| 199 | uart2: uart@b0070000 { | ||
| 200 | cell-index = <2>; | ||
| 201 | compatible = "sirf,prima2-uart"; | ||
| 202 | reg = <0xb0070000 0x10000>; | ||
| 203 | interrupts = <19>; | ||
| 204 | }; | ||
| 205 | |||
| 206 | usp0: usp@b0080000 { | ||
| 207 | cell-index = <0>; | ||
| 208 | compatible = "sirf,prima2-usp"; | ||
| 209 | reg = <0xb0080000 0x10000>; | ||
| 210 | interrupts = <20>; | ||
| 211 | }; | ||
| 212 | |||
| 213 | usp1: usp@b0090000 { | ||
| 214 | cell-index = <1>; | ||
| 215 | compatible = "sirf,prima2-usp"; | ||
| 216 | reg = <0xb0090000 0x10000>; | ||
| 217 | interrupts = <21>; | ||
| 218 | }; | ||
| 219 | |||
| 220 | usp2: usp@b00a0000 { | ||
| 221 | cell-index = <2>; | ||
| 222 | compatible = "sirf,prima2-usp"; | ||
| 223 | reg = <0xb00a0000 0x10000>; | ||
| 224 | interrupts = <22>; | ||
| 225 | }; | ||
| 226 | |||
| 227 | dmac0: dma-controller@b00b0000 { | ||
| 228 | cell-index = <0>; | ||
| 229 | compatible = "sirf,prima2-dmac"; | ||
| 230 | reg = <0xb00b0000 0x10000>; | ||
| 231 | interrupts = <12>; | ||
| 232 | }; | ||
| 233 | |||
| 234 | dmac1: dma-controller@b0160000 { | ||
| 235 | cell-index = <1>; | ||
| 236 | compatible = "sirf,prima2-dmac"; | ||
| 237 | reg = <0xb0160000 0x10000>; | ||
| 238 | interrupts = <13>; | ||
| 239 | }; | ||
| 240 | |||
| 241 | vip@b00C0000 { | ||
| 242 | compatible = "sirf,prima2-vip"; | ||
| 243 | reg = <0xb00C0000 0x10000>; | ||
| 244 | }; | ||
| 245 | |||
| 246 | spi0: spi@b00d0000 { | ||
| 247 | cell-index = <0>; | ||
| 248 | compatible = "sirf,prima2-spi"; | ||
| 249 | reg = <0xb00d0000 0x10000>; | ||
| 250 | interrupts = <15>; | ||
| 251 | }; | ||
| 252 | |||
| 253 | spi1: spi@b0170000 { | ||
| 254 | cell-index = <1>; | ||
| 255 | compatible = "sirf,prima2-spi"; | ||
| 256 | reg = <0xb0170000 0x10000>; | ||
| 257 | interrupts = <16>; | ||
| 258 | }; | ||
| 259 | |||
| 260 | i2c0: i2c@b00e0000 { | ||
| 261 | cell-index = <0>; | ||
| 262 | compatible = "sirf,prima2-i2c"; | ||
| 263 | reg = <0xb00e0000 0x10000>; | ||
| 264 | interrupts = <24>; | ||
| 265 | }; | ||
| 266 | |||
| 267 | i2c1: i2c@b00f0000 { | ||
| 268 | cell-index = <1>; | ||
| 269 | compatible = "sirf,prima2-i2c"; | ||
| 270 | reg = <0xb00f0000 0x10000>; | ||
| 271 | interrupts = <25>; | ||
| 272 | }; | ||
| 273 | |||
| 274 | tsc@b0110000 { | ||
| 275 | compatible = "sirf,prima2-tsc"; | ||
| 276 | reg = <0xb0110000 0x10000>; | ||
| 277 | interrupts = <33>; | ||
| 278 | }; | ||
| 279 | |||
| 280 | gpio: pinctrl@b0120000 { | ||
| 281 | #gpio-cells = <2>; | ||
| 282 | #interrupt-cells = <2>; | ||
| 283 | compatible = "sirf,prima2-pinctrl"; | ||
| 284 | reg = <0xb0120000 0x10000>; | ||
| 285 | interrupts = <43 44 45 46 47>; | ||
| 286 | gpio-controller; | ||
| 287 | interrupt-controller; | ||
| 288 | |||
| 289 | lcd_16pins_a: lcd0@0 { | ||
| 290 | lcd { | ||
| 291 | sirf,pins = "lcd_16bitsgrp"; | ||
| 292 | sirf,function = "lcd_16bits"; | ||
| 293 | }; | ||
| 294 | }; | ||
| 295 | lcd_18pins_a: lcd0@1 { | ||
| 296 | lcd { | ||
| 297 | sirf,pins = "lcd_18bitsgrp"; | ||
| 298 | sirf,function = "lcd_18bits"; | ||
| 299 | }; | ||
| 300 | }; | ||
| 301 | lcd_24pins_a: lcd0@2 { | ||
| 302 | lcd { | ||
| 303 | sirf,pins = "lcd_24bitsgrp"; | ||
| 304 | sirf,function = "lcd_24bits"; | ||
| 305 | }; | ||
| 306 | }; | ||
| 307 | lcdrom_pins_a: lcdrom0@0 { | ||
| 308 | lcd { | ||
| 309 | sirf,pins = "lcdromgrp"; | ||
| 310 | sirf,function = "lcdrom"; | ||
| 311 | }; | ||
| 312 | }; | ||
| 313 | uart0_pins_a: uart0@0 { | ||
| 314 | uart { | ||
| 315 | sirf,pins = "uart0grp"; | ||
| 316 | sirf,function = "uart0"; | ||
| 317 | }; | ||
| 318 | }; | ||
| 319 | uart1_pins_a: uart1@0 { | ||
| 320 | uart { | ||
| 321 | sirf,pins = "uart1grp"; | ||
| 322 | sirf,function = "uart1"; | ||
| 323 | }; | ||
| 324 | }; | ||
| 325 | uart2_pins_a: uart2@0 { | ||
| 326 | uart { | ||
| 327 | sirf,pins = "uart2grp"; | ||
| 328 | sirf,function = "uart2"; | ||
| 329 | }; | ||
| 330 | }; | ||
| 331 | uart2_noflow_pins_a: uart2@1 { | ||
| 332 | uart { | ||
| 333 | sirf,pins = "uart2_nostreamctrlgrp"; | ||
| 334 | sirf,function = "uart2_nostreamctrl"; | ||
| 335 | }; | ||
| 336 | }; | ||
| 337 | spi0_pins_a: spi0@0 { | ||
| 338 | spi { | ||
| 339 | sirf,pins = "spi0grp"; | ||
| 340 | sirf,function = "spi0"; | ||
| 341 | }; | ||
| 342 | }; | ||
| 343 | spi1_pins_a: spi1@0 { | ||
| 344 | spi { | ||
| 345 | sirf,pins = "spi1grp"; | ||
| 346 | sirf,function = "spi1"; | ||
| 347 | }; | ||
| 348 | }; | ||
| 349 | i2c0_pins_a: i2c0@0 { | ||
| 350 | i2c { | ||
| 351 | sirf,pins = "i2c0grp"; | ||
| 352 | sirf,function = "i2c0"; | ||
| 353 | }; | ||
| 354 | }; | ||
| 355 | i2c1_pins_a: i2c1@0 { | ||
| 356 | i2c { | ||
| 357 | sirf,pins = "i2c1grp"; | ||
| 358 | sirf,function = "i2c1"; | ||
| 359 | }; | ||
| 360 | }; | ||
| 361 | pwm0_pins_a: pwm0@0 { | ||
| 362 | pwm { | ||
| 363 | sirf,pins = "pwm0grp"; | ||
| 364 | sirf,function = "pwm0"; | ||
| 365 | }; | ||
| 366 | }; | ||
| 367 | pwm1_pins_a: pwm1@0 { | ||
| 368 | pwm { | ||
| 369 | sirf,pins = "pwm1grp"; | ||
| 370 | sirf,function = "pwm1"; | ||
| 371 | }; | ||
| 372 | }; | ||
| 373 | pwm2_pins_a: pwm2@0 { | ||
| 374 | pwm { | ||
| 375 | sirf,pins = "pwm2grp"; | ||
| 376 | sirf,function = "pwm2"; | ||
| 377 | }; | ||
| 378 | }; | ||
| 379 | pwm3_pins_a: pwm3@0 { | ||
| 380 | pwm { | ||
| 381 | sirf,pins = "pwm3grp"; | ||
| 382 | sirf,function = "pwm3"; | ||
| 383 | }; | ||
| 384 | }; | ||
| 385 | gps_pins_a: gps@0 { | ||
| 386 | gps { | ||
| 387 | sirf,pins = "gpsgrp"; | ||
| 388 | sirf,function = "gps"; | ||
| 389 | }; | ||
| 390 | }; | ||
| 391 | vip_pins_a: vip@0 { | ||
| 392 | vip { | ||
| 393 | sirf,pins = "vipgrp"; | ||
| 394 | sirf,function = "vip"; | ||
| 395 | }; | ||
| 396 | }; | ||
| 397 | sdmmc0_pins_a: sdmmc0@0 { | ||
| 398 | sdmmc0 { | ||
| 399 | sirf,pins = "sdmmc0grp"; | ||
| 400 | sirf,function = "sdmmc0"; | ||
| 401 | }; | ||
| 402 | }; | ||
| 403 | sdmmc1_pins_a: sdmmc1@0 { | ||
| 404 | sdmmc1 { | ||
| 405 | sirf,pins = "sdmmc1grp"; | ||
| 406 | sirf,function = "sdmmc1"; | ||
| 407 | }; | ||
| 408 | }; | ||
| 409 | sdmmc2_pins_a: sdmmc2@0 { | ||
| 410 | sdmmc2 { | ||
| 411 | sirf,pins = "sdmmc2grp"; | ||
| 412 | sirf,function = "sdmmc2"; | ||
| 413 | }; | ||
| 414 | }; | ||
| 415 | sdmmc3_pins_a: sdmmc3@0 { | ||
| 416 | sdmmc3 { | ||
| 417 | sirf,pins = "sdmmc3grp"; | ||
| 418 | sirf,function = "sdmmc3"; | ||
| 419 | }; | ||
| 420 | }; | ||
| 421 | sdmmc4_pins_a: sdmmc4@0 { | ||
| 422 | sdmmc4 { | ||
| 423 | sirf,pins = "sdmmc4grp"; | ||
| 424 | sirf,function = "sdmmc4"; | ||
| 425 | }; | ||
| 426 | }; | ||
| 427 | sdmmc5_pins_a: sdmmc5@0 { | ||
| 428 | sdmmc5 { | ||
| 429 | sirf,pins = "sdmmc5grp"; | ||
| 430 | sirf,function = "sdmmc5"; | ||
| 431 | }; | ||
| 432 | }; | ||
| 433 | i2s_pins_a: i2s@0 { | ||
| 434 | i2s { | ||
| 435 | sirf,pins = "i2sgrp"; | ||
| 436 | sirf,function = "i2s"; | ||
| 437 | }; | ||
| 438 | }; | ||
| 439 | ac97_pins_a: ac97@0 { | ||
| 440 | ac97 { | ||
| 441 | sirf,pins = "ac97grp"; | ||
| 442 | sirf,function = "ac97"; | ||
| 443 | }; | ||
| 444 | }; | ||
| 445 | nand_pins_a: nand@0 { | ||
| 446 | nand { | ||
| 447 | sirf,pins = "nandgrp"; | ||
| 448 | sirf,function = "nand"; | ||
| 449 | }; | ||
| 450 | }; | ||
| 451 | usp0_pins_a: usp0@0 { | ||
| 452 | usp0 { | ||
| 453 | sirf,pins = "usp0grp"; | ||
| 454 | sirf,function = "usp0"; | ||
| 455 | }; | ||
| 456 | }; | ||
| 457 | usp1_pins_a: usp1@0 { | ||
| 458 | usp1 { | ||
| 459 | sirf,pins = "usp1grp"; | ||
| 460 | sirf,function = "usp1"; | ||
| 461 | }; | ||
| 462 | }; | ||
| 463 | usp2_pins_a: usp2@0 { | ||
| 464 | usp2 { | ||
| 465 | sirf,pins = "usp2grp"; | ||
| 466 | sirf,function = "usp2"; | ||
| 467 | }; | ||
| 468 | }; | ||
| 469 | usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 { | ||
| 470 | usb0_utmi_drvbus { | ||
| 471 | sirf,pins = "usb0_utmi_drvbusgrp"; | ||
| 472 | sirf,function = "usb0_utmi_drvbus"; | ||
| 473 | }; | ||
| 474 | }; | ||
| 475 | usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 { | ||
| 476 | usb1_utmi_drvbus { | ||
| 477 | sirf,pins = "usb1_utmi_drvbusgrp"; | ||
| 478 | sirf,function = "usb1_utmi_drvbus"; | ||
| 479 | }; | ||
| 480 | }; | ||
| 481 | warm_rst_pins_a: warm_rst@0 { | ||
| 482 | warm_rst { | ||
| 483 | sirf,pins = "warm_rstgrp"; | ||
| 484 | sirf,function = "warm_rst"; | ||
| 485 | }; | ||
| 486 | }; | ||
| 487 | pulse_count_pins_a: pulse_count@0 { | ||
| 488 | pulse_count { | ||
| 489 | sirf,pins = "pulse_countgrp"; | ||
| 490 | sirf,function = "pulse_count"; | ||
| 491 | }; | ||
| 492 | }; | ||
| 493 | cko0_rst_pins_a: cko0_rst@0 { | ||
| 494 | cko0_rst { | ||
| 495 | sirf,pins = "cko0_rstgrp"; | ||
| 496 | sirf,function = "cko0_rst"; | ||
| 497 | }; | ||
| 498 | }; | ||
| 499 | cko1_rst_pins_a: cko1_rst@0 { | ||
| 500 | cko1_rst { | ||
| 501 | sirf,pins = "cko1_rstgrp"; | ||
| 502 | sirf,function = "cko1_rst"; | ||
| 503 | }; | ||
| 504 | }; | ||
| 505 | }; | ||
| 506 | |||
| 507 | pwm@b0130000 { | ||
| 508 | compatible = "sirf,prima2-pwm"; | ||
| 509 | reg = <0xb0130000 0x10000>; | ||
| 510 | }; | ||
| 511 | |||
| 512 | efusesys@b0140000 { | ||
| 513 | compatible = "sirf,prima2-efuse"; | ||
| 514 | reg = <0xb0140000 0x10000>; | ||
| 515 | }; | ||
| 516 | |||
| 517 | pulsec@b0150000 { | ||
| 518 | compatible = "sirf,prima2-pulsec"; | ||
| 519 | reg = <0xb0150000 0x10000>; | ||
| 520 | interrupts = <48>; | ||
| 521 | }; | ||
| 522 | |||
| 523 | pci-iobg { | ||
| 524 | compatible = "sirf,prima2-pciiobg", "simple-bus"; | ||
| 525 | #address-cells = <1>; | ||
| 526 | #size-cells = <1>; | ||
| 527 | ranges = <0x56000000 0x56000000 0x1b00000>; | ||
| 528 | |||
| 529 | sd0: sdhci@56000000 { | ||
| 530 | cell-index = <0>; | ||
| 531 | compatible = "sirf,prima2-sdhc"; | ||
| 532 | reg = <0x56000000 0x100000>; | ||
| 533 | interrupts = <38>; | ||
| 534 | }; | ||
| 535 | |||
| 536 | sd1: sdhci@56100000 { | ||
| 537 | cell-index = <1>; | ||
| 538 | compatible = "sirf,prima2-sdhc"; | ||
| 539 | reg = <0x56100000 0x100000>; | ||
| 540 | interrupts = <38>; | ||
| 541 | }; | ||
| 542 | |||
| 543 | sd2: sdhci@56200000 { | ||
| 544 | cell-index = <2>; | ||
| 545 | compatible = "sirf,prima2-sdhc"; | ||
| 546 | reg = <0x56200000 0x100000>; | ||
| 547 | interrupts = <23>; | ||
| 548 | }; | ||
| 549 | |||
| 550 | sd3: sdhci@56300000 { | ||
| 551 | cell-index = <3>; | ||
| 552 | compatible = "sirf,prima2-sdhc"; | ||
| 553 | reg = <0x56300000 0x100000>; | ||
| 554 | interrupts = <23>; | ||
| 555 | }; | ||
| 556 | |||
| 557 | sd4: sdhci@56400000 { | ||
| 558 | cell-index = <4>; | ||
| 559 | compatible = "sirf,prima2-sdhc"; | ||
| 560 | reg = <0x56400000 0x100000>; | ||
| 561 | interrupts = <39>; | ||
| 562 | }; | ||
| 563 | |||
| 564 | sd5: sdhci@56500000 { | ||
| 565 | cell-index = <5>; | ||
| 566 | compatible = "sirf,prima2-sdhc"; | ||
| 567 | reg = <0x56500000 0x100000>; | ||
| 568 | interrupts = <39>; | ||
| 569 | }; | ||
| 570 | |||
| 571 | pci-copy@57900000 { | ||
| 572 | compatible = "sirf,prima2-pcicp"; | ||
| 573 | reg = <0x57900000 0x100000>; | ||
| 574 | interrupts = <40>; | ||
| 575 | }; | ||
| 576 | |||
| 577 | rom-interface@57a00000 { | ||
| 578 | compatible = "sirf,prima2-romif"; | ||
| 579 | reg = <0x57a00000 0x100000>; | ||
| 580 | }; | ||
| 581 | }; | ||
| 582 | }; | ||
| 583 | |||
| 584 | rtc-iobg { | ||
| 585 | compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus"; | ||
| 586 | #address-cells = <1>; | ||
| 587 | #size-cells = <1>; | ||
| 588 | reg = <0x80030000 0x10000>; | ||
| 589 | |||
| 590 | gpsrtc@1000 { | ||
| 591 | compatible = "sirf,prima2-gpsrtc"; | ||
| 592 | reg = <0x1000 0x1000>; | ||
| 593 | interrupts = <55 56 57>; | ||
| 594 | }; | ||
| 595 | |||
| 596 | sysrtc@2000 { | ||
| 597 | compatible = "sirf,prima2-sysrtc"; | ||
| 598 | reg = <0x2000 0x1000>; | ||
| 599 | interrupts = <52 53 54>; | ||
| 600 | }; | ||
| 601 | |||
| 602 | pwrc@3000 { | ||
| 603 | compatible = "sirf,prima2-pwrc"; | ||
| 604 | reg = <0x3000 0x1000>; | ||
| 605 | interrupts = <32>; | ||
| 606 | }; | ||
| 607 | }; | ||
| 608 | |||
| 609 | uus-iobg { | ||
| 610 | compatible = "simple-bus"; | ||
| 611 | #address-cells = <1>; | ||
| 612 | #size-cells = <1>; | ||
| 613 | ranges = <0xb8000000 0xb8000000 0x40000>; | ||
| 614 | |||
| 615 | usb0: usb@b00e0000 { | ||
| 616 | compatible = "chipidea,ci13611a-prima2"; | ||
| 617 | reg = <0xb8000000 0x10000>; | ||
| 618 | interrupts = <10>; | ||
| 619 | }; | ||
| 620 | |||
| 621 | usb1: usb@b00f0000 { | ||
| 622 | compatible = "chipidea,ci13611a-prima2"; | ||
| 623 | reg = <0xb8010000 0x10000>; | ||
| 624 | interrupts = <11>; | ||
| 625 | }; | ||
| 626 | |||
| 627 | sata@b00f0000 { | ||
| 628 | compatible = "synopsys,dwc-ahsata"; | ||
| 629 | reg = <0xb8020000 0x10000>; | ||
| 630 | interrupts = <37>; | ||
| 631 | }; | ||
| 632 | |||
| 633 | security@b00f0000 { | ||
| 634 | compatible = "sirf,prima2-security"; | ||
| 635 | reg = <0xb8030000 0x10000>; | ||
| 636 | interrupts = <42>; | ||
| 637 | }; | ||
| 638 | }; | ||
| 639 | }; | ||
| 640 | }; | ||
diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi new file mode 100644 index 000000000000..d7c5d721a5c7 --- /dev/null +++ b/arch/arm/boot/dts/pxa27x.dtsi | |||
| @@ -0,0 +1,14 @@ | |||
| 1 | /* The pxa3xx skeleton simply augments the 2xx version */ | ||
| 2 | /include/ "pxa2xx.dtsi" | ||
| 3 | |||
| 4 | / { | ||
| 5 | model = "Marvell PXA27x familiy SoC"; | ||
| 6 | compatible = "marvell,pxa27x"; | ||
| 7 | |||
| 8 | pxabus { | ||
| 9 | pxairq: interrupt-controller@40d00000 { | ||
| 10 | marvell,intc-priority; | ||
| 11 | marvell,intc-nr-irqs = <34>; | ||
| 12 | }; | ||
| 13 | }; | ||
| 14 | }; | ||
diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi new file mode 100644 index 000000000000..f18aad35e8b3 --- /dev/null +++ b/arch/arm/boot/dts/pxa2xx.dtsi | |||
| @@ -0,0 +1,132 @@ | |||
| 1 | /* | ||
| 2 | * pxa2xx.dtsi - Device Tree Include file for Marvell PXA2xx family SoC | ||
| 3 | * | ||
| 4 | * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> | ||
| 5 | * | ||
| 6 | * Licensed under GPLv2 or later. | ||
| 7 | */ | ||
| 8 | |||
| 9 | /include/ "skeleton.dtsi" | ||
| 10 | |||
| 11 | / { | ||
| 12 | model = "Marvell PXA2xx family SoC"; | ||
| 13 | compatible = "marvell,pxa2xx"; | ||
| 14 | interrupt-parent = <&pxairq>; | ||
| 15 | |||
| 16 | aliases { | ||
| 17 | serial0 = &ffuart; | ||
| 18 | serial1 = &btuart; | ||
| 19 | serial2 = &stuart; | ||
| 20 | serial3 = &hwuart; | ||
| 21 | i2c0 = &pwri2c; | ||
| 22 | i2c1 = &pxai2c1; | ||
| 23 | }; | ||
| 24 | |||
| 25 | cpus { | ||
| 26 | cpu@0 { | ||
| 27 | compatible = "arm,xscale"; | ||
| 28 | }; | ||
| 29 | }; | ||
| 30 | |||
| 31 | pxabus { | ||
| 32 | compatible = "simple-bus"; | ||
| 33 | #address-cells = <1>; | ||
| 34 | #size-cells = <1>; | ||
| 35 | ranges; | ||
| 36 | |||
| 37 | pxairq: interrupt-controller@40d00000 { | ||
| 38 | #interrupt-cells = <1>; | ||
| 39 | compatible = "marvell,pxa-intc"; | ||
| 40 | interrupt-controller; | ||
| 41 | interrupt-parent; | ||
| 42 | marvell,intc-nr-irqs = <32>; | ||
| 43 | reg = <0x40d00000 0xd0>; | ||
| 44 | }; | ||
| 45 | |||
| 46 | gpio: gpio@40e00000 { | ||
| 47 | compatible = "mrvl,pxa-gpio"; | ||
| 48 | #address-cells = <0x1>; | ||
| 49 | #size-cells = <0x1>; | ||
| 50 | reg = <0x40e00000 0x10000>; | ||
| 51 | gpio-controller; | ||
| 52 | #gpio-cells = <0x2>; | ||
| 53 | interrupts = <10>; | ||
| 54 | interrupt-names = "gpio_mux"; | ||
| 55 | interrupt-controller; | ||
| 56 | #interrupt-cells = <0x2>; | ||
| 57 | ranges; | ||
| 58 | |||
| 59 | gcb0: gpio@40e00000 { | ||
| 60 | reg = <0x40e00000 0x4>; | ||
| 61 | }; | ||
| 62 | |||
| 63 | gcb1: gpio@40e00004 { | ||
| 64 | reg = <0x40e00004 0x4>; | ||
| 65 | }; | ||
| 66 | |||
| 67 | gcb2: gpio@40e00008 { | ||
| 68 | reg = <0x40e00008 0x4>; | ||
| 69 | }; | ||
| 70 | gcb3: gpio@40e0000c { | ||
| 71 | reg = <0x40e0000c 0x4>; | ||
| 72 | }; | ||
| 73 | }; | ||
| 74 | |||
| 75 | ffuart: uart@40100000 { | ||
| 76 | compatible = "mrvl,pxa-uart"; | ||
| 77 | reg = <0x40100000 0x30>; | ||
| 78 | interrupts = <22>; | ||
| 79 | status = "disabled"; | ||
| 80 | }; | ||
| 81 | |||
| 82 | btuart: uart@40200000 { | ||
| 83 | compatible = "mrvl,pxa-uart"; | ||
| 84 | reg = <0x40200000 0x30>; | ||
| 85 | interrupts = <21>; | ||
| 86 | status = "disabled"; | ||
| 87 | }; | ||
| 88 | |||
| 89 | stuart: uart@40700000 { | ||
| 90 | compatible = "mrvl,pxa-uart"; | ||
| 91 | reg = <0x40700000 0x30>; | ||
| 92 | interrupts = <20>; | ||
| 93 | status = "disabled"; | ||
| 94 | }; | ||
| 95 | |||
| 96 | hwuart: uart@41100000 { | ||
| 97 | compatible = "mrvl,pxa-uart"; | ||
| 98 | reg = <0x41100000 0x30>; | ||
| 99 | interrupts = <7>; | ||
| 100 | status = "disabled"; | ||
| 101 | }; | ||
| 102 | |||
| 103 | pxai2c1: i2c@40301680 { | ||
| 104 | compatible = "mrvl,pxa-i2c"; | ||
| 105 | reg = <0x40301680 0x30>; | ||
| 106 | interrupts = <18>; | ||
| 107 | #address-cells = <0x1>; | ||
| 108 | #size-cells = <0>; | ||
| 109 | status = "disabled"; | ||
| 110 | }; | ||
| 111 | |||
| 112 | usb0: ohci@4c000000 { | ||
| 113 | compatible = "mrvl,pxa-ohci"; | ||
| 114 | reg = <0x4c000000 0x10000>; | ||
| 115 | interrupts = <3>; | ||
| 116 | status = "disabled"; | ||
| 117 | }; | ||
| 118 | |||
| 119 | mmc0: mmc@41100000 { | ||
| 120 | compatible = "mrvl,pxa-mmc"; | ||
| 121 | reg = <0x41100000 0x1000>; | ||
| 122 | interrupts = <23>; | ||
| 123 | status = "disabled"; | ||
| 124 | }; | ||
| 125 | |||
| 126 | rtc@40900000 { | ||
| 127 | compatible = "marvell,pxa-rtc"; | ||
| 128 | reg = <0x40900000 0x3c>; | ||
| 129 | interrupts = <30 31>; | ||
| 130 | }; | ||
| 131 | }; | ||
| 132 | }; | ||
diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi new file mode 100644 index 000000000000..f9d92da86783 --- /dev/null +++ b/arch/arm/boot/dts/pxa3xx.dtsi | |||
| @@ -0,0 +1,32 @@ | |||
| 1 | /* The pxa3xx skeleton simply augments the 2xx version */ | ||
| 2 | /include/ "pxa2xx.dtsi" | ||
| 3 | |||
| 4 | / { | ||
| 5 | model = "Marvell PXA3xx familiy SoC"; | ||
| 6 | compatible = "marvell,pxa3xx"; | ||
| 7 | |||
| 8 | pxabus { | ||
| 9 | pwri2c: i2c@40f500c0 { | ||
| 10 | compatible = "mrvl,pwri2c"; | ||
| 11 | reg = <0x40f500c0 0x30>; | ||
| 12 | interrupts = <6>; | ||
| 13 | #address-cells = <0x1>; | ||
| 14 | #size-cells = <0>; | ||
| 15 | status = "disabled"; | ||
| 16 | }; | ||
| 17 | |||
| 18 | nand0: nand@43100000 { | ||
| 19 | compatible = "marvell,pxa3xx-nand"; | ||
| 20 | reg = <0x43100000 90>; | ||
| 21 | interrupts = <45>; | ||
| 22 | #address-cells = <1>; | ||
| 23 | #size-cells = <1>; | ||
| 24 | status = "disabled"; | ||
| 25 | }; | ||
| 26 | |||
| 27 | pxairq: interrupt-controller@40d00000 { | ||
| 28 | marvell,intc-priority; | ||
| 29 | marvell,intc-nr-irqs = <56>; | ||
| 30 | }; | ||
| 31 | }; | ||
| 32 | }; | ||
diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi index aebf32de73b4..a3be44d86bcd 100644 --- a/arch/arm/boot/dts/pxa910.dtsi +++ b/arch/arm/boot/dts/pxa910.dtsi | |||
| @@ -25,6 +25,11 @@ | |||
| 25 | interrupt-parent = <&intc>; | 25 | interrupt-parent = <&intc>; |
| 26 | ranges; | 26 | ranges; |
| 27 | 27 | ||
| 28 | L2: l2-cache { | ||
| 29 | compatible = "marvell,tauros2-cache"; | ||
| 30 | marvell,tauros2-cache-features = <0x3>; | ||
| 31 | }; | ||
| 32 | |||
| 28 | axi@d4200000 { /* AXI */ | 33 | axi@d4200000 { /* AXI */ |
| 29 | compatible = "mrvl,axi-bus", "simple-bus"; | 34 | compatible = "mrvl,axi-bus", "simple-bus"; |
| 30 | #address-cells = <1>; | 35 | #address-cells = <1>; |
diff --git a/arch/arm/boot/dts/twl6030.dtsi b/arch/arm/boot/dts/twl6030.dtsi index 3b2f3510d7eb..d351b27d7213 100644 --- a/arch/arm/boot/dts/twl6030.dtsi +++ b/arch/arm/boot/dts/twl6030.dtsi | |||
| @@ -66,6 +66,7 @@ | |||
| 66 | 66 | ||
| 67 | vcxio: regulator@8 { | 67 | vcxio: regulator@8 { |
| 68 | compatible = "ti,twl6030-vcxio"; | 68 | compatible = "ti,twl6030-vcxio"; |
| 69 | regulator-always-on; | ||
| 69 | }; | 70 | }; |
| 70 | 71 | ||
| 71 | vusb: regulator@9 { | 72 | vusb: regulator@9 { |
| @@ -74,10 +75,12 @@ | |||
| 74 | 75 | ||
| 75 | v1v8: regulator@10 { | 76 | v1v8: regulator@10 { |
| 76 | compatible = "ti,twl6030-v1v8"; | 77 | compatible = "ti,twl6030-v1v8"; |
| 78 | regulator-always-on; | ||
| 77 | }; | 79 | }; |
| 78 | 80 | ||
| 79 | v2v1: regulator@11 { | 81 | v2v1: regulator@11 { |
| 80 | compatible = "ti,twl6030-v2v1"; | 82 | compatible = "ti,twl6030-v2v1"; |
| 83 | regulator-always-on; | ||
| 81 | }; | 84 | }; |
| 82 | 85 | ||
| 83 | clk32kg: regulator@12 { | 86 | clk32kg: regulator@12 { |
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 3c9f32f9b6b4..565132d02105 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig | |||
| @@ -32,9 +32,7 @@ CONFIG_MACH_VPR200=y | |||
| 32 | CONFIG_MACH_IMX51_DT=y | 32 | CONFIG_MACH_IMX51_DT=y |
| 33 | CONFIG_MACH_MX51_3DS=y | 33 | CONFIG_MACH_MX51_3DS=y |
| 34 | CONFIG_MACH_EUKREA_CPUIMX51SD=y | 34 | CONFIG_MACH_EUKREA_CPUIMX51SD=y |
| 35 | CONFIG_MACH_MX51_EFIKAMX=y | 35 | CONFIG_SOC_IMX53=y |
| 36 | CONFIG_MACH_MX51_EFIKASB=y | ||
| 37 | CONFIG_MACH_IMX53_DT=y | ||
| 38 | CONFIG_SOC_IMX6Q=y | 36 | CONFIG_SOC_IMX6Q=y |
| 39 | CONFIG_MXC_PWM=y | 37 | CONFIG_MXC_PWM=y |
| 40 | CONFIG_SMP=y | 38 | CONFIG_SMP=y |
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig index 4edcfb4e4dee..36d60dda310c 100644 --- a/arch/arm/configs/mxs_defconfig +++ b/arch/arm/configs/mxs_defconfig | |||
| @@ -23,12 +23,6 @@ CONFIG_BLK_DEV_INTEGRITY=y | |||
| 23 | # CONFIG_IOSCHED_CFQ is not set | 23 | # CONFIG_IOSCHED_CFQ is not set |
| 24 | CONFIG_ARCH_MXS=y | 24 | CONFIG_ARCH_MXS=y |
| 25 | CONFIG_MACH_MXS_DT=y | 25 | CONFIG_MACH_MXS_DT=y |
| 26 | CONFIG_MACH_MX23EVK=y | ||
| 27 | CONFIG_MACH_MX28EVK=y | ||
| 28 | CONFIG_MACH_STMP378X_DEVB=y | ||
| 29 | CONFIG_MACH_TX28=y | ||
| 30 | CONFIG_MACH_M28EVK=y | ||
| 31 | CONFIG_MACH_APX4DEVKIT=y | ||
| 32 | # CONFIG_ARM_THUMB is not set | 26 | # CONFIG_ARM_THUMB is not set |
| 33 | CONFIG_NO_HZ=y | 27 | CONFIG_NO_HZ=y |
| 34 | CONFIG_HIGH_RES_TIMERS=y | 28 | CONFIG_HIGH_RES_TIMERS=y |
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig index 2d4f661d1cf6..da6845493caa 100644 --- a/arch/arm/configs/u8500_defconfig +++ b/arch/arm/configs/u8500_defconfig | |||
| @@ -86,6 +86,7 @@ CONFIG_NEW_LEDS=y | |||
| 86 | CONFIG_LEDS_CLASS=y | 86 | CONFIG_LEDS_CLASS=y |
| 87 | CONFIG_LEDS_LM3530=y | 87 | CONFIG_LEDS_LM3530=y |
| 88 | CONFIG_LEDS_LP5521=y | 88 | CONFIG_LEDS_LP5521=y |
| 89 | CONFIG_LEDS_GPIO=y | ||
| 89 | CONFIG_RTC_CLASS=y | 90 | CONFIG_RTC_CLASS=y |
| 90 | CONFIG_RTC_DRV_AB8500=y | 91 | CONFIG_RTC_DRV_AB8500=y |
| 91 | CONFIG_RTC_DRV_PL031=y | 92 | CONFIG_RTC_DRV_PL031=y |
diff --git a/arch/arm/include/asm/hardware/cache-tauros2.h b/arch/arm/include/asm/hardware/cache-tauros2.h index 538f17ca905b..295e2e40151b 100644 --- a/arch/arm/include/asm/hardware/cache-tauros2.h +++ b/arch/arm/include/asm/hardware/cache-tauros2.h | |||
| @@ -8,4 +8,7 @@ | |||
| 8 | * warranty of any kind, whether express or implied. | 8 | * warranty of any kind, whether express or implied. |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | extern void __init tauros2_init(void); | 11 | #define CACHE_TAUROS2_PREFETCH_ON (1 << 0) |
| 12 | #define CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1) | ||
| 13 | |||
| 14 | extern void __init tauros2_init(unsigned int features); | ||
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 4db5de54b6a7..e5a97d97e38d 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c | |||
| @@ -102,7 +102,8 @@ void __init dove_ehci1_init(void) | |||
| 102 | void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) | 102 | void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) |
| 103 | { | 103 | { |
| 104 | orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE, | 104 | orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE, |
| 105 | IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR); | 105 | IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR, |
| 106 | 1600); | ||
| 106 | } | 107 | } |
| 107 | 108 | ||
| 108 | /***************************************************************************** | 109 | /***************************************************************************** |
| @@ -288,7 +289,7 @@ void __init dove_init(void) | |||
| 288 | printk(KERN_INFO "TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000); | 289 | printk(KERN_INFO "TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000); |
| 289 | 290 | ||
| 290 | #ifdef CONFIG_CACHE_TAUROS2 | 291 | #ifdef CONFIG_CACHE_TAUROS2 |
| 291 | tauros2_init(); | 292 | tauros2_init(0); |
| 292 | #endif | 293 | #endif |
| 293 | dove_setup_cpu_mbus(); | 294 | dove_setup_cpu_mbus(); |
| 294 | 295 | ||
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c index 5ca80307d6d7..4e574c24581c 100644 --- a/arch/arm/mach-exynos/mach-origen.c +++ b/arch/arm/mach-exynos/mach-origen.c | |||
| @@ -42,6 +42,7 @@ | |||
| 42 | #include <plat/backlight.h> | 42 | #include <plat/backlight.h> |
| 43 | #include <plat/fb.h> | 43 | #include <plat/fb.h> |
| 44 | #include <plat/mfc.h> | 44 | #include <plat/mfc.h> |
| 45 | #include <plat/hdmi.h> | ||
| 45 | 46 | ||
| 46 | #include <mach/ohci.h> | 47 | #include <mach/ohci.h> |
| 47 | #include <mach/map.h> | 48 | #include <mach/map.h> |
| @@ -734,6 +735,11 @@ static void __init origen_bt_setup(void) | |||
| 734 | s3c_gpio_setpull(EXYNOS4_GPX2(2), S3C_GPIO_PULL_NONE); | 735 | s3c_gpio_setpull(EXYNOS4_GPX2(2), S3C_GPIO_PULL_NONE); |
| 735 | } | 736 | } |
| 736 | 737 | ||
| 738 | /* I2C module and id for HDMIPHY */ | ||
| 739 | static struct i2c_board_info hdmiphy_info = { | ||
| 740 | I2C_BOARD_INFO("hdmiphy-exynos4210", 0x38), | ||
| 741 | }; | ||
| 742 | |||
| 737 | static void s5p_tv_setup(void) | 743 | static void s5p_tv_setup(void) |
| 738 | { | 744 | { |
| 739 | /* Direct HPD to HDMI chip */ | 745 | /* Direct HPD to HDMI chip */ |
| @@ -781,6 +787,7 @@ static void __init origen_machine_init(void) | |||
| 781 | 787 | ||
| 782 | s5p_tv_setup(); | 788 | s5p_tv_setup(); |
| 783 | s5p_i2c_hdmiphy_set_platdata(NULL); | 789 | s5p_i2c_hdmiphy_set_platdata(NULL); |
| 790 | s5p_hdmi_set_platdata(&hdmiphy_info, NULL, 0); | ||
| 784 | 791 | ||
| 785 | #ifdef CONFIG_DRM_EXYNOS | 792 | #ifdef CONFIG_DRM_EXYNOS |
| 786 | s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata; | 793 | s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata; |
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c index 3cfa688d274a..73f2bce097e1 100644 --- a/arch/arm/mach-exynos/mach-smdkv310.c +++ b/arch/arm/mach-exynos/mach-smdkv310.c | |||
| @@ -40,6 +40,7 @@ | |||
| 40 | #include <plat/mfc.h> | 40 | #include <plat/mfc.h> |
| 41 | #include <plat/ehci.h> | 41 | #include <plat/ehci.h> |
| 42 | #include <plat/clock.h> | 42 | #include <plat/clock.h> |
| 43 | #include <plat/hdmi.h> | ||
| 43 | 44 | ||
| 44 | #include <mach/map.h> | 45 | #include <mach/map.h> |
| 45 | #include <mach/ohci.h> | 46 | #include <mach/ohci.h> |
| @@ -354,6 +355,11 @@ static struct platform_pwm_backlight_data smdkv310_bl_data = { | |||
| 354 | .pwm_period_ns = 1000, | 355 | .pwm_period_ns = 1000, |
| 355 | }; | 356 | }; |
| 356 | 357 | ||
| 358 | /* I2C module and id for HDMIPHY */ | ||
| 359 | static struct i2c_board_info hdmiphy_info = { | ||
| 360 | I2C_BOARD_INFO("hdmiphy-exynos4210", 0x38), | ||
| 361 | }; | ||
| 362 | |||
| 357 | static void s5p_tv_setup(void) | 363 | static void s5p_tv_setup(void) |
| 358 | { | 364 | { |
| 359 | /* direct HPD to HDMI chip */ | 365 | /* direct HPD to HDMI chip */ |
| @@ -388,6 +394,7 @@ static void __init smdkv310_machine_init(void) | |||
| 388 | 394 | ||
| 389 | s5p_tv_setup(); | 395 | s5p_tv_setup(); |
| 390 | s5p_i2c_hdmiphy_set_platdata(NULL); | 396 | s5p_i2c_hdmiphy_set_platdata(NULL); |
| 397 | s5p_hdmi_set_platdata(&hdmiphy_info, NULL, 0); | ||
| 391 | 398 | ||
| 392 | samsung_keypad_set_platdata(&smdkv310_keypad_data); | 399 | samsung_keypad_set_platdata(&smdkv310_keypad_data); |
| 393 | 400 | ||
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index afd542ad6f97..7ca5fe45945f 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig | |||
| @@ -101,13 +101,8 @@ config SOC_IMX51 | |||
| 101 | select SOC_IMX5 | 101 | select SOC_IMX5 |
| 102 | select ARCH_MX5 | 102 | select ARCH_MX5 |
| 103 | select ARCH_MX51 | 103 | select ARCH_MX51 |
| 104 | 104 | select PINCTRL | |
| 105 | config SOC_IMX53 | 105 | select PINCTRL_IMX51 |
| 106 | bool | ||
| 107 | select SOC_IMX5 | ||
| 108 | select ARCH_MX5 | ||
| 109 | select ARCH_MX53 | ||
| 110 | select HAVE_CAN_FLEXCAN if CAN | ||
| 111 | 106 | ||
| 112 | if ARCH_IMX_V4_V5 | 107 | if ARCH_IMX_V4_V5 |
| 113 | 108 | ||
| @@ -561,7 +556,6 @@ config MACH_BUG | |||
| 561 | config MACH_IMX31_DT | 556 | config MACH_IMX31_DT |
| 562 | bool "Support i.MX31 platforms from device tree" | 557 | bool "Support i.MX31 platforms from device tree" |
| 563 | select SOC_IMX31 | 558 | select SOC_IMX31 |
| 564 | select USE_OF | ||
| 565 | help | 559 | help |
| 566 | Include support for Freescale i.MX31 based platforms | 560 | Include support for Freescale i.MX31 based platforms |
| 567 | using the device tree for discovery. | 561 | using the device tree for discovery. |
| @@ -737,95 +731,19 @@ config MACH_EUKREA_MBIMXSD51_BASEBOARD | |||
| 737 | 731 | ||
| 738 | endchoice | 732 | endchoice |
| 739 | 733 | ||
| 740 | config MX51_EFIKA_COMMON | 734 | comment "Device tree only" |
| 741 | bool | ||
| 742 | select SOC_IMX51 | ||
| 743 | select IMX_HAVE_PLATFORM_IMX_UART | ||
| 744 | select IMX_HAVE_PLATFORM_MXC_EHCI | ||
| 745 | select IMX_HAVE_PLATFORM_PATA_IMX | ||
| 746 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
| 747 | select IMX_HAVE_PLATFORM_SPI_IMX | ||
| 748 | select MXC_ULPI if USB_ULPI | ||
| 749 | |||
| 750 | config MACH_MX51_EFIKAMX | ||
| 751 | bool "Support MX51 Genesi Efika MX nettop" | ||
| 752 | select LEDS_GPIO_REGISTER | ||
| 753 | select MX51_EFIKA_COMMON | ||
| 754 | help | ||
| 755 | Include support for Genesi Efika MX nettop. This includes specific | ||
| 756 | configurations for the board and its peripherals. | ||
| 757 | |||
| 758 | config MACH_MX51_EFIKASB | ||
| 759 | bool "Support MX51 Genesi Efika Smartbook" | ||
| 760 | select LEDS_GPIO_REGISTER | ||
| 761 | select MX51_EFIKA_COMMON | ||
| 762 | help | ||
| 763 | Include support for Genesi Efika Smartbook. This includes specific | ||
| 764 | configurations for the board and its peripherals. | ||
| 765 | |||
| 766 | comment "i.MX53 machines:" | ||
| 767 | |||
| 768 | config MACH_IMX53_DT | ||
| 769 | bool "Support i.MX53 platforms from device tree" | ||
| 770 | select SOC_IMX53 | ||
| 771 | select MACH_MX53_ARD | ||
| 772 | select MACH_MX53_EVK | ||
| 773 | select MACH_MX53_LOCO | ||
| 774 | select MACH_MX53_SMD | ||
| 775 | help | ||
| 776 | Include support for Freescale i.MX53 based platforms | ||
| 777 | using the device tree for discovery | ||
| 778 | |||
| 779 | config MACH_MX53_EVK | ||
| 780 | bool "Support MX53 EVK platforms" | ||
| 781 | select SOC_IMX53 | ||
| 782 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
| 783 | select IMX_HAVE_PLATFORM_IMX_UART | ||
| 784 | select IMX_HAVE_PLATFORM_IMX_I2C | ||
| 785 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
| 786 | select IMX_HAVE_PLATFORM_SPI_IMX | ||
| 787 | select LEDS_GPIO_REGISTER | ||
| 788 | help | ||
| 789 | Include support for MX53 EVK platform. This includes specific | ||
| 790 | configurations for the board and its peripherals. | ||
| 791 | |||
| 792 | config MACH_MX53_SMD | ||
| 793 | bool "Support MX53 SMD platforms" | ||
| 794 | select SOC_IMX53 | ||
| 795 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
| 796 | select IMX_HAVE_PLATFORM_IMX_I2C | ||
| 797 | select IMX_HAVE_PLATFORM_IMX_UART | ||
| 798 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
| 799 | help | ||
| 800 | Include support for MX53 SMD platform. This includes specific | ||
| 801 | configurations for the board and its peripherals. | ||
| 802 | 735 | ||
| 803 | config MACH_MX53_LOCO | 736 | config SOC_IMX53 |
| 804 | bool "Support MX53 LOCO platforms" | 737 | bool "i.MX53 support" |
| 805 | select SOC_IMX53 | 738 | select SOC_IMX5 |
| 806 | select IMX_HAVE_PLATFORM_IMX2_WDT | 739 | select ARCH_MX5 |
| 807 | select IMX_HAVE_PLATFORM_IMX_I2C | 740 | select ARCH_MX53 |
| 808 | select IMX_HAVE_PLATFORM_IMX_UART | 741 | select HAVE_CAN_FLEXCAN if CAN |
| 809 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | 742 | select PINCTRL |
| 810 | select IMX_HAVE_PLATFORM_GPIO_KEYS | 743 | select PINCTRL_IMX53 |
| 811 | select LEDS_GPIO_REGISTER | ||
| 812 | help | ||
| 813 | Include support for MX53 LOCO platform. This includes specific | ||
| 814 | configurations for the board and its peripherals. | ||
| 815 | 744 | ||
| 816 | config MACH_MX53_ARD | ||
| 817 | bool "Support MX53 ARD platforms" | ||
| 818 | select SOC_IMX53 | ||
| 819 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
| 820 | select IMX_HAVE_PLATFORM_IMX_I2C | ||
| 821 | select IMX_HAVE_PLATFORM_IMX_UART | ||
| 822 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
| 823 | select IMX_HAVE_PLATFORM_GPIO_KEYS | ||
| 824 | help | 745 | help |
| 825 | Include support for MX53 ARD platform. This includes specific | 746 | This enables support for Freescale i.MX53 processor. |
| 826 | configurations for the board and its peripherals. | ||
| 827 | |||
| 828 | comment "i.MX6 family:" | ||
| 829 | 747 | ||
| 830 | config SOC_IMX6Q | 748 | config SOC_IMX6Q |
| 831 | bool "i.MX6 Quad support" | 749 | bool "i.MX6 Quad support" |
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 07f7c226e4cf..f4c0e757d805 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile | |||
| @@ -9,7 +9,8 @@ obj-$(CONFIG_SOC_IMX27) += clk-imx27.o mm-imx27.o ehci-imx27.o | |||
| 9 | obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-imx31.o pm-imx3.o | 9 | obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-imx31.o pm-imx3.o |
| 10 | obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o | 10 | obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o |
| 11 | 11 | ||
| 12 | obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o pm-imx5.o cpu_op-mx51.o | 12 | imx5-pm-$(CONFIG_PM) += pm-imx5.o |
| 13 | obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) cpu_op-mx51.o | ||
| 13 | 14 | ||
| 14 | obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \ | 15 | obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \ |
| 15 | clk-pfd.o clk-busy.o | 16 | clk-pfd.o clk-busy.o |
| @@ -70,29 +71,21 @@ obj-$(CONFIG_DEBUG_LL) += lluart.o | |||
| 70 | obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o | 71 | obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o |
| 71 | obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o | 72 | obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o |
| 72 | obj-$(CONFIG_HAVE_IMX_SRC) += src.o | 73 | obj-$(CONFIG_HAVE_IMX_SRC) += src.o |
| 73 | obj-$(CONFIG_CPU_V7) += head-v7.o | 74 | AFLAGS_headsmp.o :=-Wa,-march=armv7-a |
| 74 | AFLAGS_head-v7.o :=-Wa,-march=armv7-a | 75 | obj-$(CONFIG_SMP) += headsmp.o platsmp.o |
| 75 | obj-$(CONFIG_SMP) += platsmp.o | ||
| 76 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o | 76 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o |
| 77 | obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o | 77 | obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o |
| 78 | 78 | ||
| 79 | ifeq ($(CONFIG_PM),y) | 79 | ifeq ($(CONFIG_PM),y) |
| 80 | obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o | 80 | obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o |
| 81 | endif | 81 | endif |
| 82 | 82 | ||
| 83 | # i.MX5 based machines | 83 | # i.MX5 based machines |
| 84 | obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o | 84 | obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o |
| 85 | obj-$(CONFIG_MACH_MX51_3DS) += mach-mx51_3ds.o | 85 | obj-$(CONFIG_MACH_MX51_3DS) += mach-mx51_3ds.o |
| 86 | obj-$(CONFIG_MACH_MX53_EVK) += mach-mx53_evk.o | ||
| 87 | obj-$(CONFIG_MACH_MX53_SMD) += mach-mx53_smd.o | ||
| 88 | obj-$(CONFIG_MACH_MX53_LOCO) += mach-mx53_loco.o | ||
| 89 | obj-$(CONFIG_MACH_MX53_ARD) += mach-mx53_ard.o | ||
| 90 | obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o | 86 | obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o |
| 91 | obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o | 87 | obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o |
| 92 | obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o | ||
| 93 | obj-$(CONFIG_MACH_MX51_EFIKAMX) += mach-mx51_efikamx.o | ||
| 94 | obj-$(CONFIG_MACH_MX51_EFIKASB) += mach-mx51_efikasb.o | ||
| 95 | obj-$(CONFIG_MACH_MX50_RDP) += mach-mx50_rdp.o | 88 | obj-$(CONFIG_MACH_MX50_RDP) += mach-mx50_rdp.o |
| 96 | 89 | ||
| 97 | obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o | 90 | obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o |
| 98 | obj-$(CONFIG_MACH_IMX53_DT) += imx53-dt.o | 91 | obj-$(CONFIG_SOC_IMX53) += mach-imx53.o |
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot index 05541cf4a878..c60967629e27 100644 --- a/arch/arm/mach-imx/Makefile.boot +++ b/arch/arm/mach-imx/Makefile.boot | |||
| @@ -39,8 +39,12 @@ params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100 | |||
| 39 | initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000 | 39 | initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000 |
| 40 | 40 | ||
| 41 | dtb-$(CONFIG_MACH_IMX51_DT) += imx51-babbage.dtb | 41 | dtb-$(CONFIG_MACH_IMX51_DT) += imx51-babbage.dtb |
| 42 | dtb-$(CONFIG_MACH_IMX53_DT) += imx53-ard.dtb imx53-evk.dtb \ | 42 | |
| 43 | imx53-qsb.dtb imx53-smd.dtb | 43 | dtb-$(CONFIG_SOC_IMX53) += imx53-ard.dtb \ |
| 44 | imx53-evk.dtb \ | ||
| 45 | imx53-qsb.dtb \ | ||
| 46 | imx53-smd.dtb \ | ||
| 47 | |||
| 44 | dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \ | 48 | dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \ |
| 45 | imx6q-sabrelite.dtb \ | 49 | imx6q-sabrelite.dtb \ |
| 46 | imx6q-sabresd.dtb \ | 50 | imx6q-sabresd.dtb \ |
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index bbc71f57b92b..32fdf73b8e5b 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c | |||
| @@ -152,7 +152,7 @@ enum mx6q_clks { | |||
| 152 | ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3, | 152 | ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3, |
| 153 | usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg, | 153 | usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg, |
| 154 | pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg, | 154 | pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg, |
| 155 | ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, | 155 | ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, |
| 156 | clk_max | 156 | clk_max |
| 157 | }; | 157 | }; |
| 158 | 158 | ||
| @@ -289,8 +289,10 @@ int __init mx6q_clocks_init(void) | |||
| 289 | clk[gpu3d_shader] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3); | 289 | clk[gpu3d_shader] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3); |
| 290 | clk[ipu1_podf] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3); | 290 | clk[ipu1_podf] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3); |
| 291 | clk[ipu2_podf] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3); | 291 | clk[ipu2_podf] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3); |
| 292 | clk[ldb_di0_podf] = imx_clk_divider("ldb_di0_podf", "ldb_di0_sel", base + 0x20, 10, 1); | 292 | clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); |
| 293 | clk[ldb_di1_podf] = imx_clk_divider("ldb_di1_podf", "ldb_di1_sel", base + 0x20, 11, 1); | 293 | clk[ldb_di0_podf] = imx_clk_divider("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1); |
| 294 | clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); | ||
| 295 | clk[ldb_di1_podf] = imx_clk_divider("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1); | ||
| 294 | clk[ipu1_di0_pre] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3); | 296 | clk[ipu1_di0_pre] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3); |
| 295 | clk[ipu1_di1_pre] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3); | 297 | clk[ipu1_di1_pre] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3); |
| 296 | clk[ipu2_di0_pre] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3); | 298 | clk[ipu2_di0_pre] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3); |
diff --git a/arch/arm/mach-imx/devices-imx53.h b/arch/arm/mach-imx/devices-imx53.h deleted file mode 100644 index 77e0db96c448..000000000000 --- a/arch/arm/mach-imx/devices-imx53.h +++ /dev/null | |||
| @@ -1,48 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it under | ||
| 5 | * the terms of the GNU General Public License version 2 as published by the | ||
| 6 | * Free Software Foundation. | ||
| 7 | */ | ||
| 8 | #include <mach/mx53.h> | ||
| 9 | #include <mach/devices-common.h> | ||
| 10 | |||
| 11 | extern const struct imx_fec_data imx53_fec_data; | ||
| 12 | #define imx53_add_fec(pdata) \ | ||
| 13 | imx_add_fec(&imx53_fec_data, pdata) | ||
| 14 | |||
| 15 | extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[]; | ||
| 16 | #define imx53_add_imx_uart(id, pdata) \ | ||
| 17 | imx_add_imx_uart_1irq(&imx53_imx_uart_data[id], pdata) | ||
| 18 | |||
| 19 | |||
| 20 | extern const struct imx_imx_i2c_data imx53_imx_i2c_data[]; | ||
| 21 | #define imx53_add_imx_i2c(id, pdata) \ | ||
| 22 | imx_add_imx_i2c(&imx53_imx_i2c_data[id], pdata) | ||
| 23 | |||
| 24 | extern const struct imx_sdhci_esdhc_imx_data imx53_sdhci_esdhc_imx_data[]; | ||
| 25 | #define imx53_add_sdhci_esdhc_imx(id, pdata) \ | ||
| 26 | imx_add_sdhci_esdhc_imx(&imx53_sdhci_esdhc_imx_data[id], pdata) | ||
| 27 | |||
| 28 | extern const struct imx_spi_imx_data imx53_ecspi_data[]; | ||
| 29 | #define imx53_add_ecspi(id, pdata) \ | ||
| 30 | imx_add_spi_imx(&imx53_ecspi_data[id], pdata) | ||
| 31 | |||
| 32 | extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[]; | ||
| 33 | #define imx53_add_imx2_wdt(id) \ | ||
| 34 | imx_add_imx2_wdt(&imx53_imx2_wdt_data[id]) | ||
| 35 | |||
| 36 | extern const struct imx_imx_ssi_data imx53_imx_ssi_data[]; | ||
| 37 | #define imx53_add_imx_ssi(id, pdata) \ | ||
| 38 | imx_add_imx_ssi(&imx53_imx_ssi_data[id], pdata) | ||
| 39 | |||
| 40 | extern const struct imx_imx_keypad_data imx53_imx_keypad_data; | ||
| 41 | #define imx53_add_imx_keypad(pdata) \ | ||
| 42 | imx_add_imx_keypad(&imx53_imx_keypad_data, pdata) | ||
| 43 | |||
| 44 | extern const struct imx_pata_imx_data imx53_pata_imx_data; | ||
| 45 | #define imx53_add_pata_imx() \ | ||
| 46 | imx_add_pata_imx(&imx53_pata_imx_data) | ||
| 47 | |||
| 48 | extern struct platform_device *__init imx53_add_ahci_imx(void); | ||
diff --git a/arch/arm/mach-imx/efika.h b/arch/arm/mach-imx/efika.h deleted file mode 100644 index 014aa985faae..000000000000 --- a/arch/arm/mach-imx/efika.h +++ /dev/null | |||
| @@ -1,10 +0,0 @@ | |||
| 1 | #ifndef _EFIKA_H | ||
| 2 | #define _EFIKA_H | ||
| 3 | |||
| 4 | #define EFIKA_WLAN_EN IMX_GPIO_NR(2, 16) | ||
| 5 | #define EFIKA_WLAN_RESET IMX_GPIO_NR(2, 10) | ||
| 6 | #define EFIKA_USB_PHY_RESET IMX_GPIO_NR(2, 9) | ||
| 7 | |||
| 8 | void __init efika_board_common_init(void); | ||
| 9 | |||
| 10 | #endif | ||
diff --git a/arch/arm/mach-imx/head-v7.S b/arch/arm/mach-imx/headsmp.S index 7e49deb128a4..7e49deb128a4 100644 --- a/arch/arm/mach-imx/head-v7.S +++ b/arch/arm/mach-imx/headsmp.S | |||
diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c index 20ed2d56c1af..f8f7437c83b8 100644 --- a/arch/arm/mach-imx/hotplug.c +++ b/arch/arm/mach-imx/hotplug.c | |||
| @@ -42,22 +42,6 @@ static inline void cpu_enter_lowpower(void) | |||
| 42 | : "cc"); | 42 | : "cc"); |
| 43 | } | 43 | } |
| 44 | 44 | ||
| 45 | static inline void cpu_leave_lowpower(void) | ||
| 46 | { | ||
| 47 | unsigned int v; | ||
| 48 | |||
| 49 | asm volatile( | ||
| 50 | "mrc p15, 0, %0, c1, c0, 0\n" | ||
| 51 | " orr %0, %0, %1\n" | ||
| 52 | " mcr p15, 0, %0, c1, c0, 0\n" | ||
| 53 | " mrc p15, 0, %0, c1, c0, 1\n" | ||
| 54 | " orr %0, %0, %2\n" | ||
| 55 | " mcr p15, 0, %0, c1, c0, 1\n" | ||
| 56 | : "=&r" (v) | ||
| 57 | : "Ir" (CR_C), "Ir" (0x40) | ||
| 58 | : "cc"); | ||
| 59 | } | ||
| 60 | |||
| 61 | /* | 45 | /* |
| 62 | * platform-specific code to shutdown a CPU | 46 | * platform-specific code to shutdown a CPU |
| 63 | * | 47 | * |
| @@ -67,11 +51,10 @@ void platform_cpu_die(unsigned int cpu) | |||
| 67 | { | 51 | { |
| 68 | cpu_enter_lowpower(); | 52 | cpu_enter_lowpower(); |
| 69 | imx_enable_cpu(cpu, false); | 53 | imx_enable_cpu(cpu, false); |
| 70 | cpu_do_idle(); | ||
| 71 | cpu_leave_lowpower(); | ||
| 72 | 54 | ||
| 73 | /* We should never return from idle */ | 55 | /* spin here until hardware takes it down */ |
| 74 | panic("cpu %d unexpectedly exit from shutdown\n", cpu); | 56 | while (1) |
| 57 | ; | ||
| 75 | } | 58 | } |
| 76 | 59 | ||
| 77 | int platform_cpu_disable(unsigned int cpu) | 60 | int platform_cpu_disable(unsigned int cpu) |
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c index d4067fe36357..f233b4bb2342 100644 --- a/arch/arm/mach-imx/imx51-dt.c +++ b/arch/arm/mach-imx/imx51-dt.c | |||
| @@ -13,7 +13,6 @@ | |||
| 13 | #include <linux/irq.h> | 13 | #include <linux/irq.h> |
| 14 | #include <linux/of_irq.h> | 14 | #include <linux/of_irq.h> |
| 15 | #include <linux/of_platform.h> | 15 | #include <linux/of_platform.h> |
| 16 | #include <linux/pinctrl/machine.h> | ||
| 17 | #include <asm/mach/arch.h> | 16 | #include <asm/mach/arch.h> |
| 18 | #include <asm/mach/time.h> | 17 | #include <asm/mach/time.h> |
| 19 | #include <mach/common.h> | 18 | #include <mach/common.h> |
| @@ -44,27 +43,8 @@ static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = { | |||
| 44 | { /* sentinel */ } | 43 | { /* sentinel */ } |
| 45 | }; | 44 | }; |
| 46 | 45 | ||
| 47 | static const struct of_device_id imx51_iomuxc_of_match[] __initconst = { | ||
| 48 | { .compatible = "fsl,imx51-iomuxc-babbage", .data = imx51_babbage_common_init, }, | ||
| 49 | { /* sentinel */ } | ||
| 50 | }; | ||
| 51 | |||
| 52 | static void __init imx51_dt_init(void) | 46 | static void __init imx51_dt_init(void) |
| 53 | { | 47 | { |
| 54 | struct device_node *node; | ||
| 55 | const struct of_device_id *of_id; | ||
| 56 | void (*func)(void); | ||
| 57 | |||
| 58 | pinctrl_provide_dummies(); | ||
| 59 | |||
| 60 | node = of_find_matching_node(NULL, imx51_iomuxc_of_match); | ||
| 61 | if (node) { | ||
| 62 | of_id = of_match_node(imx51_iomuxc_of_match, node); | ||
| 63 | func = of_id->data; | ||
| 64 | func(); | ||
| 65 | of_node_put(node); | ||
| 66 | } | ||
| 67 | |||
| 68 | of_platform_populate(NULL, of_default_bus_match_table, | 48 | of_platform_populate(NULL, of_default_bus_match_table, |
| 69 | imx51_auxdata_lookup, NULL); | 49 | imx51_auxdata_lookup, NULL); |
| 70 | } | 50 | } |
| @@ -79,7 +59,6 @@ static struct sys_timer imx51_timer = { | |||
| 79 | }; | 59 | }; |
| 80 | 60 | ||
| 81 | static const char *imx51_dt_board_compat[] __initdata = { | 61 | static const char *imx51_dt_board_compat[] __initdata = { |
| 82 | "fsl,imx51-babbage", | ||
| 83 | "fsl,imx51", | 62 | "fsl,imx51", |
| 84 | NULL | 63 | NULL |
| 85 | }; | 64 | }; |
diff --git a/arch/arm/mach-imx/imx53-dt.c b/arch/arm/mach-imx/mach-imx53.c index 1b7a2fc36591..29711e95579f 100644 --- a/arch/arm/mach-imx/imx53-dt.c +++ b/arch/arm/mach-imx/mach-imx53.c | |||
| @@ -17,7 +17,6 @@ | |||
| 17 | #include <linux/irq.h> | 17 | #include <linux/irq.h> |
| 18 | #include <linux/of_irq.h> | 18 | #include <linux/of_irq.h> |
| 19 | #include <linux/of_platform.h> | 19 | #include <linux/of_platform.h> |
| 20 | #include <linux/pinctrl/machine.h> | ||
| 21 | #include <asm/mach/arch.h> | 20 | #include <asm/mach/arch.h> |
| 22 | #include <asm/mach/time.h> | 21 | #include <asm/mach/time.h> |
| 23 | #include <mach/common.h> | 22 | #include <mach/common.h> |
| @@ -51,14 +50,6 @@ static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = { | |||
| 51 | { /* sentinel */ } | 50 | { /* sentinel */ } |
| 52 | }; | 51 | }; |
| 53 | 52 | ||
| 54 | static const struct of_device_id imx53_iomuxc_of_match[] __initconst = { | ||
| 55 | { .compatible = "fsl,imx53-iomuxc-ard", .data = imx53_ard_common_init, }, | ||
| 56 | { .compatible = "fsl,imx53-iomuxc-evk", .data = imx53_evk_common_init, }, | ||
| 57 | { .compatible = "fsl,imx53-iomuxc-qsb", .data = imx53_qsb_common_init, }, | ||
| 58 | { .compatible = "fsl,imx53-iomuxc-smd", .data = imx53_smd_common_init, }, | ||
| 59 | { /* sentinel */ } | ||
| 60 | }; | ||
| 61 | |||
| 62 | static void __init imx53_qsb_init(void) | 53 | static void __init imx53_qsb_init(void) |
| 63 | { | 54 | { |
| 64 | struct clk *clk; | 55 | struct clk *clk; |
| @@ -74,20 +65,6 @@ static void __init imx53_qsb_init(void) | |||
| 74 | 65 | ||
| 75 | static void __init imx53_dt_init(void) | 66 | static void __init imx53_dt_init(void) |
| 76 | { | 67 | { |
| 77 | struct device_node *node; | ||
| 78 | const struct of_device_id *of_id; | ||
| 79 | void (*func)(void); | ||
| 80 | |||
| 81 | pinctrl_provide_dummies(); | ||
| 82 | |||
| 83 | node = of_find_matching_node(NULL, imx53_iomuxc_of_match); | ||
| 84 | if (node) { | ||
| 85 | of_id = of_match_node(imx53_iomuxc_of_match, node); | ||
| 86 | func = of_id->data; | ||
| 87 | func(); | ||
| 88 | of_node_put(node); | ||
| 89 | } | ||
| 90 | |||
| 91 | if (of_machine_is_compatible("fsl,imx53-qsb")) | 68 | if (of_machine_is_compatible("fsl,imx53-qsb")) |
| 92 | imx53_qsb_init(); | 69 | imx53_qsb_init(); |
| 93 | 70 | ||
| @@ -105,10 +82,6 @@ static struct sys_timer imx53_timer = { | |||
| 105 | }; | 82 | }; |
| 106 | 83 | ||
| 107 | static const char *imx53_dt_board_compat[] __initdata = { | 84 | static const char *imx53_dt_board_compat[] __initdata = { |
| 108 | "fsl,imx53-ard", | ||
| 109 | "fsl,imx53-evk", | ||
| 110 | "fsl,imx53-qsb", | ||
| 111 | "fsl,imx53-smd", | ||
| 112 | "fsl,imx53", | 85 | "fsl,imx53", |
| 113 | NULL | 86 | NULL |
| 114 | }; | 87 | }; |
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 0b30aa8799d2..692b4b143bb1 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c | |||
| @@ -22,7 +22,6 @@ | |||
| 22 | #include <linux/of_address.h> | 22 | #include <linux/of_address.h> |
| 23 | #include <linux/of_irq.h> | 23 | #include <linux/of_irq.h> |
| 24 | #include <linux/of_platform.h> | 24 | #include <linux/of_platform.h> |
| 25 | #include <linux/pinctrl/machine.h> | ||
| 26 | #include <linux/phy.h> | 25 | #include <linux/phy.h> |
| 27 | #include <linux/micrel_phy.h> | 26 | #include <linux/micrel_phy.h> |
| 28 | #include <linux/mfd/anatop.h> | 27 | #include <linux/mfd/anatop.h> |
| @@ -71,7 +70,7 @@ soft: | |||
| 71 | /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */ | 70 | /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */ |
| 72 | static int ksz9021rn_phy_fixup(struct phy_device *phydev) | 71 | static int ksz9021rn_phy_fixup(struct phy_device *phydev) |
| 73 | { | 72 | { |
| 74 | if (IS_ENABLED(CONFIG_PHYLIB)) { | 73 | if (IS_BUILTIN(CONFIG_PHYLIB)) { |
| 75 | /* min rx data delay */ | 74 | /* min rx data delay */ |
| 76 | phy_write(phydev, 0x0b, 0x8105); | 75 | phy_write(phydev, 0x0b, 0x8105); |
| 77 | phy_write(phydev, 0x0c, 0x0000); | 76 | phy_write(phydev, 0x0c, 0x0000); |
| @@ -111,7 +110,7 @@ put_clk: | |||
| 111 | 110 | ||
| 112 | static void __init imx6q_sabrelite_init(void) | 111 | static void __init imx6q_sabrelite_init(void) |
| 113 | { | 112 | { |
| 114 | if (IS_ENABLED(CONFIG_PHYLIB)) | 113 | if (IS_BUILTIN(CONFIG_PHYLIB)) |
| 115 | phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, | 114 | phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, |
| 116 | ksz9021rn_phy_fixup); | 115 | ksz9021rn_phy_fixup); |
| 117 | imx6q_sabrelite_cko1_setup(); | 116 | imx6q_sabrelite_cko1_setup(); |
| @@ -158,12 +157,6 @@ static void __init imx6q_usb_init(void) | |||
| 158 | 157 | ||
| 159 | static void __init imx6q_init_machine(void) | 158 | static void __init imx6q_init_machine(void) |
| 160 | { | 159 | { |
| 161 | /* | ||
| 162 | * This should be removed when all imx6q boards have pinctrl | ||
| 163 | * states for devices defined in device tree. | ||
| 164 | */ | ||
| 165 | pinctrl_provide_dummies(); | ||
| 166 | |||
| 167 | if (of_machine_is_compatible("fsl,imx6q-sabrelite")) | 160 | if (of_machine_is_compatible("fsl,imx6q-sabrelite")) |
| 168 | imx6q_sabrelite_init(); | 161 | imx6q_sabrelite_init(); |
| 169 | 162 | ||
| @@ -217,9 +210,6 @@ static struct sys_timer imx6q_timer = { | |||
| 217 | }; | 210 | }; |
| 218 | 211 | ||
| 219 | static const char *imx6q_dt_compat[] __initdata = { | 212 | static const char *imx6q_dt_compat[] __initdata = { |
| 220 | "fsl,imx6q-arm2", | ||
| 221 | "fsl,imx6q-sabrelite", | ||
| 222 | "fsl,imx6q-sabresd", | ||
| 223 | "fsl,imx6q", | 213 | "fsl,imx6q", |
| 224 | NULL, | 214 | NULL, |
| 225 | }; | 215 | }; |
diff --git a/arch/arm/mach-imx/mach-mx51_efikamx.c b/arch/arm/mach-imx/mach-mx51_efikamx.c deleted file mode 100644 index 8d09c0126cab..000000000000 --- a/arch/arm/mach-imx/mach-mx51_efikamx.c +++ /dev/null | |||
| @@ -1,300 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Linaro Limited | ||
| 3 | * | ||
| 4 | * based on code from the following | ||
| 5 | * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 6 | * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved. | ||
| 7 | * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved. | ||
| 8 | * | ||
| 9 | * The code contained herein is licensed under the GNU General Public | ||
| 10 | * License. You may obtain a copy of the GNU General Public License | ||
| 11 | * Version 2 or later at the following locations: | ||
| 12 | * | ||
| 13 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 14 | * http://www.gnu.org/copyleft/gpl.html | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include <linux/init.h> | ||
| 18 | #include <linux/platform_device.h> | ||
| 19 | #include <linux/i2c.h> | ||
| 20 | #include <linux/gpio.h> | ||
| 21 | #include <linux/leds.h> | ||
| 22 | #include <linux/input.h> | ||
| 23 | #include <linux/delay.h> | ||
| 24 | #include <linux/io.h> | ||
| 25 | #include <linux/spi/flash.h> | ||
| 26 | #include <linux/spi/spi.h> | ||
| 27 | #include <linux/mfd/mc13892.h> | ||
| 28 | #include <linux/regulator/machine.h> | ||
| 29 | #include <linux/regulator/consumer.h> | ||
| 30 | |||
| 31 | #include <mach/common.h> | ||
| 32 | #include <mach/hardware.h> | ||
| 33 | #include <mach/iomux-mx51.h> | ||
| 34 | |||
| 35 | #include <asm/setup.h> | ||
| 36 | #include <asm/system_info.h> | ||
| 37 | #include <asm/mach-types.h> | ||
| 38 | #include <asm/mach/arch.h> | ||
| 39 | #include <asm/mach/time.h> | ||
| 40 | |||
| 41 | #include "devices-imx51.h" | ||
| 42 | #include "efika.h" | ||
| 43 | |||
| 44 | #define EFIKAMX_PCBID0 IMX_GPIO_NR(3, 16) | ||
| 45 | #define EFIKAMX_PCBID1 IMX_GPIO_NR(3, 17) | ||
| 46 | #define EFIKAMX_PCBID2 IMX_GPIO_NR(3, 11) | ||
| 47 | |||
| 48 | #define EFIKAMX_BLUE_LED IMX_GPIO_NR(3, 13) | ||
| 49 | #define EFIKAMX_GREEN_LED IMX_GPIO_NR(3, 14) | ||
| 50 | #define EFIKAMX_RED_LED IMX_GPIO_NR(3, 15) | ||
| 51 | |||
| 52 | #define EFIKAMX_POWER_KEY IMX_GPIO_NR(2, 31) | ||
| 53 | |||
| 54 | /* board 1.1 doesn't have same reset gpio */ | ||
| 55 | #define EFIKAMX_RESET1_1 IMX_GPIO_NR(3, 2) | ||
| 56 | #define EFIKAMX_RESET IMX_GPIO_NR(1, 4) | ||
| 57 | |||
| 58 | #define EFIKAMX_POWEROFF IMX_GPIO_NR(4, 13) | ||
| 59 | |||
| 60 | #define EFIKAMX_PMIC IMX_GPIO_NR(1, 6) | ||
| 61 | |||
| 62 | /* the pci ids pin have pull up. they're driven low according to board id */ | ||
| 63 | #define MX51_PAD_PCBID0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) | ||
| 64 | #define MX51_PAD_PCBID1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) | ||
| 65 | #define MX51_PAD_PCBID2 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) | ||
| 66 | #define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE) | ||
| 67 | |||
| 68 | static iomux_v3_cfg_t mx51efikamx_pads[] = { | ||
| 69 | /* board id */ | ||
| 70 | MX51_PAD_PCBID0, | ||
| 71 | MX51_PAD_PCBID1, | ||
| 72 | MX51_PAD_PCBID2, | ||
| 73 | |||
| 74 | /* leds */ | ||
| 75 | MX51_PAD_CSI1_D9__GPIO3_13, | ||
| 76 | MX51_PAD_CSI1_VSYNC__GPIO3_14, | ||
| 77 | MX51_PAD_CSI1_HSYNC__GPIO3_15, | ||
| 78 | |||
| 79 | /* power key */ | ||
| 80 | MX51_PAD_PWRKEY, | ||
| 81 | |||
| 82 | /* reset */ | ||
| 83 | MX51_PAD_DI1_PIN13__GPIO3_2, | ||
| 84 | MX51_PAD_GPIO1_4__GPIO1_4, | ||
| 85 | |||
| 86 | /* power off */ | ||
| 87 | MX51_PAD_CSI2_VSYNC__GPIO4_13, | ||
| 88 | }; | ||
| 89 | |||
| 90 | /* PCBID2 PCBID1 PCBID0 STATE | ||
| 91 | 1 1 1 ER1:rev1.1 | ||
| 92 | 1 1 0 ER2:rev1.2 | ||
| 93 | 1 0 1 ER3:rev1.3 | ||
| 94 | 1 0 0 ER4:rev1.4 | ||
| 95 | */ | ||
| 96 | static void __init mx51_efikamx_board_id(void) | ||
| 97 | { | ||
| 98 | int id; | ||
| 99 | |||
| 100 | /* things are taking time to settle */ | ||
| 101 | msleep(150); | ||
| 102 | |||
| 103 | gpio_request(EFIKAMX_PCBID0, "pcbid0"); | ||
| 104 | gpio_direction_input(EFIKAMX_PCBID0); | ||
| 105 | gpio_request(EFIKAMX_PCBID1, "pcbid1"); | ||
| 106 | gpio_direction_input(EFIKAMX_PCBID1); | ||
| 107 | gpio_request(EFIKAMX_PCBID2, "pcbid2"); | ||
| 108 | gpio_direction_input(EFIKAMX_PCBID2); | ||
| 109 | |||
| 110 | id = gpio_get_value(EFIKAMX_PCBID0) ? 1 : 0; | ||
| 111 | id |= (gpio_get_value(EFIKAMX_PCBID1) ? 1 : 0) << 1; | ||
| 112 | id |= (gpio_get_value(EFIKAMX_PCBID2) ? 1 : 0) << 2; | ||
| 113 | |||
| 114 | switch (id) { | ||
| 115 | case 7: | ||
| 116 | system_rev = 0x11; | ||
| 117 | break; | ||
| 118 | case 6: | ||
| 119 | system_rev = 0x12; | ||
| 120 | break; | ||
| 121 | case 5: | ||
| 122 | system_rev = 0x13; | ||
| 123 | break; | ||
| 124 | case 4: | ||
| 125 | system_rev = 0x14; | ||
| 126 | break; | ||
| 127 | default: | ||
| 128 | system_rev = 0x10; | ||
| 129 | break; | ||
| 130 | } | ||
| 131 | |||
| 132 | if ((system_rev == 0x10) | ||
| 133 | || (system_rev == 0x12) | ||
| 134 | || (system_rev == 0x14)) { | ||
| 135 | printk(KERN_WARNING | ||
| 136 | "EfikaMX: Unsupported board revision 1.%u!\n", | ||
| 137 | system_rev & 0xf); | ||
| 138 | } | ||
| 139 | } | ||
| 140 | |||
| 141 | static struct gpio_led mx51_efikamx_leds[] __initdata = { | ||
| 142 | { | ||
| 143 | .name = "efikamx:green", | ||
| 144 | .default_trigger = "default-on", | ||
| 145 | .gpio = EFIKAMX_GREEN_LED, | ||
| 146 | }, | ||
| 147 | { | ||
| 148 | .name = "efikamx:red", | ||
| 149 | .default_trigger = "ide-disk", | ||
| 150 | .gpio = EFIKAMX_RED_LED, | ||
| 151 | }, | ||
| 152 | { | ||
| 153 | .name = "efikamx:blue", | ||
| 154 | .default_trigger = "mmc0", | ||
| 155 | .gpio = EFIKAMX_BLUE_LED, | ||
| 156 | }, | ||
| 157 | }; | ||
| 158 | |||
| 159 | static const struct gpio_led_platform_data | ||
| 160 | mx51_efikamx_leds_data __initconst = { | ||
| 161 | .leds = mx51_efikamx_leds, | ||
| 162 | .num_leds = ARRAY_SIZE(mx51_efikamx_leds), | ||
| 163 | }; | ||
| 164 | |||
| 165 | static struct esdhc_platform_data sd_pdata = { | ||
| 166 | .cd_type = ESDHC_CD_CONTROLLER, | ||
| 167 | .wp_type = ESDHC_WP_CONTROLLER, | ||
| 168 | }; | ||
| 169 | |||
| 170 | static struct gpio_keys_button mx51_efikamx_powerkey[] = { | ||
| 171 | { | ||
| 172 | .code = KEY_POWER, | ||
| 173 | .gpio = EFIKAMX_POWER_KEY, | ||
| 174 | .type = EV_PWR, | ||
| 175 | .desc = "Power Button (CM)", | ||
| 176 | .wakeup = 1, | ||
| 177 | .debounce_interval = 10, /* ms */ | ||
| 178 | }, | ||
| 179 | }; | ||
| 180 | |||
| 181 | static const struct gpio_keys_platform_data mx51_efikamx_powerkey_data __initconst = { | ||
| 182 | .buttons = mx51_efikamx_powerkey, | ||
| 183 | .nbuttons = ARRAY_SIZE(mx51_efikamx_powerkey), | ||
| 184 | }; | ||
| 185 | |||
| 186 | static void mx51_efikamx_restart(char mode, const char *cmd) | ||
| 187 | { | ||
| 188 | if (system_rev == 0x11) | ||
| 189 | gpio_direction_output(EFIKAMX_RESET1_1, 0); | ||
| 190 | else | ||
| 191 | gpio_direction_output(EFIKAMX_RESET, 0); | ||
| 192 | } | ||
| 193 | |||
| 194 | static struct regulator *pwgt1, *pwgt2, *coincell; | ||
| 195 | |||
| 196 | static void mx51_efikamx_power_off(void) | ||
| 197 | { | ||
| 198 | if (!IS_ERR(coincell)) | ||
| 199 | regulator_disable(coincell); | ||
| 200 | |||
| 201 | if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) { | ||
| 202 | regulator_disable(pwgt2); | ||
| 203 | regulator_disable(pwgt1); | ||
| 204 | } | ||
| 205 | gpio_direction_output(EFIKAMX_POWEROFF, 1); | ||
| 206 | } | ||
| 207 | |||
| 208 | static int __init mx51_efikamx_power_init(void) | ||
| 209 | { | ||
| 210 | pwgt1 = regulator_get(NULL, "pwgt1"); | ||
| 211 | pwgt2 = regulator_get(NULL, "pwgt2"); | ||
| 212 | if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) { | ||
| 213 | regulator_enable(pwgt1); | ||
| 214 | regulator_enable(pwgt2); | ||
| 215 | } | ||
| 216 | gpio_request(EFIKAMX_POWEROFF, "poweroff"); | ||
| 217 | pm_power_off = mx51_efikamx_power_off; | ||
| 218 | |||
| 219 | /* enable coincell charger. maybe need a small power driver ? */ | ||
| 220 | coincell = regulator_get(NULL, "coincell"); | ||
| 221 | if (!IS_ERR(coincell)) { | ||
| 222 | regulator_set_voltage(coincell, 3000000, 3000000); | ||
| 223 | regulator_enable(coincell); | ||
| 224 | } | ||
| 225 | |||
| 226 | regulator_has_full_constraints(); | ||
| 227 | |||
| 228 | return 0; | ||
| 229 | } | ||
| 230 | |||
| 231 | static void __init mx51_efikamx_init_late(void) | ||
| 232 | { | ||
| 233 | imx51_init_late(); | ||
| 234 | mx51_efikamx_power_init(); | ||
| 235 | } | ||
| 236 | |||
| 237 | static void __init mx51_efikamx_init(void) | ||
| 238 | { | ||
| 239 | imx51_soc_init(); | ||
| 240 | |||
| 241 | mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads, | ||
| 242 | ARRAY_SIZE(mx51efikamx_pads)); | ||
| 243 | efika_board_common_init(); | ||
| 244 | |||
| 245 | mx51_efikamx_board_id(); | ||
| 246 | |||
| 247 | /* on < 1.2 boards both SD controllers are used */ | ||
| 248 | if (system_rev < 0x12) { | ||
| 249 | imx51_add_sdhci_esdhc_imx(0, NULL); | ||
| 250 | imx51_add_sdhci_esdhc_imx(1, &sd_pdata); | ||
| 251 | mx51_efikamx_leds[2].default_trigger = "mmc1"; | ||
| 252 | } else | ||
| 253 | imx51_add_sdhci_esdhc_imx(0, &sd_pdata); | ||
| 254 | |||
| 255 | gpio_led_register_device(-1, &mx51_efikamx_leds_data); | ||
| 256 | imx_add_gpio_keys(&mx51_efikamx_powerkey_data); | ||
| 257 | |||
| 258 | if (system_rev == 0x11) { | ||
| 259 | gpio_request(EFIKAMX_RESET1_1, "reset"); | ||
| 260 | gpio_direction_output(EFIKAMX_RESET1_1, 1); | ||
| 261 | } else { | ||
| 262 | gpio_request(EFIKAMX_RESET, "reset"); | ||
| 263 | gpio_direction_output(EFIKAMX_RESET, 1); | ||
| 264 | } | ||
| 265 | |||
| 266 | /* | ||
| 267 | * enable wifi by default only on mx | ||
| 268 | * sb and mx have same wlan pin but the value to enable it are | ||
| 269 | * different :/ | ||
| 270 | */ | ||
| 271 | gpio_request(EFIKA_WLAN_EN, "wlan_en"); | ||
| 272 | gpio_direction_output(EFIKA_WLAN_EN, 0); | ||
| 273 | msleep(10); | ||
| 274 | |||
| 275 | gpio_request(EFIKA_WLAN_RESET, "wlan_rst"); | ||
| 276 | gpio_direction_output(EFIKA_WLAN_RESET, 0); | ||
| 277 | msleep(10); | ||
| 278 | gpio_set_value(EFIKA_WLAN_RESET, 1); | ||
| 279 | } | ||
| 280 | |||
| 281 | static void __init mx51_efikamx_timer_init(void) | ||
| 282 | { | ||
| 283 | mx51_clocks_init(32768, 24000000, 22579200, 24576000); | ||
| 284 | } | ||
| 285 | |||
| 286 | static struct sys_timer mx51_efikamx_timer = { | ||
| 287 | .init = mx51_efikamx_timer_init, | ||
| 288 | }; | ||
| 289 | |||
| 290 | MACHINE_START(MX51_EFIKAMX, "Genesi Efika MX (Smarttop)") | ||
| 291 | .atag_offset = 0x100, | ||
| 292 | .map_io = mx51_map_io, | ||
| 293 | .init_early = imx51_init_early, | ||
| 294 | .init_irq = mx51_init_irq, | ||
| 295 | .handle_irq = imx51_handle_irq, | ||
| 296 | .timer = &mx51_efikamx_timer, | ||
| 297 | .init_machine = mx51_efikamx_init, | ||
| 298 | .init_late = mx51_efikamx_init_late, | ||
| 299 | .restart = mx51_efikamx_restart, | ||
| 300 | MACHINE_END | ||
diff --git a/arch/arm/mach-imx/mach-mx51_efikasb.c b/arch/arm/mach-imx/mach-mx51_efikasb.c deleted file mode 100644 index fdbd181b97ef..000000000000 --- a/arch/arm/mach-imx/mach-mx51_efikasb.c +++ /dev/null | |||
| @@ -1,296 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) Arnaud Patard <arnaud.patard@rtp-net.org> | ||
| 3 | * | ||
| 4 | * based on code from the following | ||
| 5 | * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 6 | * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved. | ||
| 7 | * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved. | ||
| 8 | * | ||
| 9 | * The code contained herein is licensed under the GNU General Public | ||
| 10 | * License. You may obtain a copy of the GNU General Public License | ||
| 11 | * Version 2 or later at the following locations: | ||
| 12 | * | ||
| 13 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 14 | * http://www.gnu.org/copyleft/gpl.html | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include <linux/init.h> | ||
| 18 | #include <linux/platform_device.h> | ||
| 19 | #include <linux/i2c.h> | ||
| 20 | #include <linux/gpio.h> | ||
| 21 | #include <linux/leds.h> | ||
| 22 | #include <linux/input.h> | ||
| 23 | #include <linux/delay.h> | ||
| 24 | #include <linux/io.h> | ||
| 25 | #include <linux/spi/flash.h> | ||
| 26 | #include <linux/spi/spi.h> | ||
| 27 | #include <linux/mfd/mc13892.h> | ||
| 28 | #include <linux/regulator/machine.h> | ||
| 29 | #include <linux/regulator/consumer.h> | ||
| 30 | #include <linux/usb/otg.h> | ||
| 31 | #include <linux/usb/ulpi.h> | ||
| 32 | #include <mach/ulpi.h> | ||
| 33 | |||
| 34 | #include <mach/common.h> | ||
| 35 | #include <mach/hardware.h> | ||
| 36 | #include <mach/iomux-mx51.h> | ||
| 37 | |||
| 38 | #include <asm/setup.h> | ||
| 39 | #include <asm/system_info.h> | ||
| 40 | #include <asm/mach-types.h> | ||
| 41 | #include <asm/mach/arch.h> | ||
| 42 | #include <asm/mach/time.h> | ||
| 43 | |||
| 44 | #include "devices-imx51.h" | ||
| 45 | #include "efika.h" | ||
| 46 | |||
| 47 | #define EFIKASB_USBH2_STP IMX_GPIO_NR(2, 20) | ||
| 48 | #define EFIKASB_GREEN_LED IMX_GPIO_NR(1, 3) | ||
| 49 | #define EFIKASB_WHITE_LED IMX_GPIO_NR(2, 25) | ||
| 50 | #define EFIKASB_PCBID0 IMX_GPIO_NR(2, 28) | ||
| 51 | #define EFIKASB_PCBID1 IMX_GPIO_NR(2, 29) | ||
| 52 | #define EFIKASB_PWRKEY IMX_GPIO_NR(2, 31) | ||
| 53 | #define EFIKASB_LID IMX_GPIO_NR(3, 14) | ||
| 54 | #define EFIKASB_POWEROFF IMX_GPIO_NR(4, 13) | ||
| 55 | #define EFIKASB_RFKILL IMX_GPIO_NR(3, 1) | ||
| 56 | |||
| 57 | #define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE) | ||
| 58 | #define MX51_PAD_SD1_CD IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_ESDHC_PAD_CTRL) | ||
| 59 | |||
| 60 | static iomux_v3_cfg_t mx51efikasb_pads[] = { | ||
| 61 | /* USB HOST2 */ | ||
| 62 | MX51_PAD_EIM_D16__USBH2_DATA0, | ||
| 63 | MX51_PAD_EIM_D17__USBH2_DATA1, | ||
| 64 | MX51_PAD_EIM_D18__USBH2_DATA2, | ||
| 65 | MX51_PAD_EIM_D19__USBH2_DATA3, | ||
| 66 | MX51_PAD_EIM_D20__USBH2_DATA4, | ||
| 67 | MX51_PAD_EIM_D21__USBH2_DATA5, | ||
| 68 | MX51_PAD_EIM_D22__USBH2_DATA6, | ||
| 69 | MX51_PAD_EIM_D23__USBH2_DATA7, | ||
| 70 | MX51_PAD_EIM_A24__USBH2_CLK, | ||
| 71 | MX51_PAD_EIM_A25__USBH2_DIR, | ||
| 72 | MX51_PAD_EIM_A26__USBH2_STP, | ||
| 73 | MX51_PAD_EIM_A27__USBH2_NXT, | ||
| 74 | |||
| 75 | /* leds */ | ||
| 76 | MX51_PAD_EIM_CS0__GPIO2_25, | ||
| 77 | MX51_PAD_GPIO1_3__GPIO1_3, | ||
| 78 | |||
| 79 | /* pcb id */ | ||
| 80 | MX51_PAD_EIM_CS3__GPIO2_28, | ||
| 81 | MX51_PAD_EIM_CS4__GPIO2_29, | ||
| 82 | |||
| 83 | /* lid */ | ||
| 84 | MX51_PAD_CSI1_VSYNC__GPIO3_14, | ||
| 85 | |||
| 86 | /* power key*/ | ||
| 87 | MX51_PAD_PWRKEY, | ||
| 88 | |||
| 89 | /* wifi/bt button */ | ||
| 90 | MX51_PAD_DI1_PIN12__GPIO3_1, | ||
| 91 | |||
| 92 | /* power off */ | ||
| 93 | MX51_PAD_CSI2_VSYNC__GPIO4_13, | ||
| 94 | |||
| 95 | /* wdog reset */ | ||
| 96 | MX51_PAD_GPIO1_4__WDOG1_WDOG_B, | ||
| 97 | |||
| 98 | /* BT */ | ||
| 99 | MX51_PAD_EIM_A17__GPIO2_11, | ||
| 100 | |||
| 101 | MX51_PAD_SD1_CD, | ||
| 102 | }; | ||
| 103 | |||
| 104 | static int initialize_usbh2_port(struct platform_device *pdev) | ||
| 105 | { | ||
| 106 | iomux_v3_cfg_t usbh2stp = MX51_PAD_EIM_A26__USBH2_STP; | ||
| 107 | iomux_v3_cfg_t usbh2gpio = MX51_PAD_EIM_A26__GPIO2_20; | ||
| 108 | |||
| 109 | mxc_iomux_v3_setup_pad(usbh2gpio); | ||
| 110 | gpio_request(EFIKASB_USBH2_STP, "usbh2_stp"); | ||
| 111 | gpio_direction_output(EFIKASB_USBH2_STP, 0); | ||
| 112 | msleep(1); | ||
| 113 | gpio_set_value(EFIKASB_USBH2_STP, 1); | ||
| 114 | msleep(1); | ||
| 115 | |||
| 116 | gpio_free(EFIKASB_USBH2_STP); | ||
| 117 | mxc_iomux_v3_setup_pad(usbh2stp); | ||
| 118 | |||
| 119 | mdelay(10); | ||
| 120 | |||
| 121 | return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD); | ||
| 122 | } | ||
| 123 | |||
| 124 | static struct mxc_usbh_platform_data usbh2_config __initdata = { | ||
| 125 | .init = initialize_usbh2_port, | ||
| 126 | .portsc = MXC_EHCI_MODE_ULPI, | ||
| 127 | }; | ||
| 128 | |||
| 129 | static void __init mx51_efikasb_usb(void) | ||
| 130 | { | ||
| 131 | usbh2_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | | ||
| 132 | ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND); | ||
| 133 | if (usbh2_config.otg) | ||
| 134 | imx51_add_mxc_ehci_hs(2, &usbh2_config); | ||
| 135 | } | ||
| 136 | |||
| 137 | static const struct gpio_led mx51_efikasb_leds[] __initconst = { | ||
| 138 | { | ||
| 139 | .name = "efikasb:green", | ||
| 140 | .default_trigger = "default-on", | ||
| 141 | .gpio = EFIKASB_GREEN_LED, | ||
| 142 | .active_low = 1, | ||
| 143 | }, | ||
| 144 | { | ||
| 145 | .name = "efikasb:white", | ||
| 146 | .default_trigger = "caps", | ||
| 147 | .gpio = EFIKASB_WHITE_LED, | ||
| 148 | }, | ||
| 149 | }; | ||
| 150 | |||
| 151 | static const struct gpio_led_platform_data | ||
| 152 | mx51_efikasb_leds_data __initconst = { | ||
| 153 | .leds = mx51_efikasb_leds, | ||
| 154 | .num_leds = ARRAY_SIZE(mx51_efikasb_leds), | ||
| 155 | }; | ||
| 156 | |||
| 157 | static struct gpio_keys_button mx51_efikasb_keys[] = { | ||
| 158 | { | ||
| 159 | .code = KEY_POWER, | ||
| 160 | .gpio = EFIKASB_PWRKEY, | ||
| 161 | .type = EV_KEY, | ||
| 162 | .desc = "Power Button", | ||
| 163 | .wakeup = 1, | ||
| 164 | .active_low = 1, | ||
| 165 | }, | ||
| 166 | { | ||
| 167 | .code = SW_LID, | ||
| 168 | .gpio = EFIKASB_LID, | ||
| 169 | .type = EV_SW, | ||
| 170 | .desc = "Lid Switch", | ||
| 171 | .active_low = 1, | ||
| 172 | }, | ||
| 173 | { | ||
| 174 | .code = KEY_RFKILL, | ||
| 175 | .gpio = EFIKASB_RFKILL, | ||
| 176 | .type = EV_KEY, | ||
| 177 | .desc = "rfkill", | ||
| 178 | .active_low = 1, | ||
| 179 | }, | ||
| 180 | }; | ||
| 181 | |||
| 182 | static const struct gpio_keys_platform_data mx51_efikasb_keys_data __initconst = { | ||
| 183 | .buttons = mx51_efikasb_keys, | ||
| 184 | .nbuttons = ARRAY_SIZE(mx51_efikasb_keys), | ||
| 185 | }; | ||
| 186 | |||
| 187 | static struct esdhc_platform_data sd0_pdata = { | ||
| 188 | #define EFIKASB_SD1_CD IMX_GPIO_NR(2, 27) | ||
| 189 | .cd_gpio = EFIKASB_SD1_CD, | ||
| 190 | .cd_type = ESDHC_CD_GPIO, | ||
| 191 | .wp_type = ESDHC_WP_CONTROLLER, | ||
| 192 | }; | ||
| 193 | |||
| 194 | static struct esdhc_platform_data sd1_pdata = { | ||
| 195 | .cd_type = ESDHC_CD_CONTROLLER, | ||
| 196 | .wp_type = ESDHC_WP_CONTROLLER, | ||
| 197 | }; | ||
| 198 | |||
| 199 | static struct regulator *pwgt1, *pwgt2; | ||
| 200 | |||
| 201 | static void mx51_efikasb_power_off(void) | ||
| 202 | { | ||
| 203 | gpio_set_value(EFIKA_USB_PHY_RESET, 0); | ||
| 204 | |||
| 205 | if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) { | ||
| 206 | regulator_disable(pwgt2); | ||
| 207 | regulator_disable(pwgt1); | ||
| 208 | } | ||
| 209 | gpio_direction_output(EFIKASB_POWEROFF, 1); | ||
| 210 | } | ||
| 211 | |||
| 212 | static int __init mx51_efikasb_power_init(void) | ||
| 213 | { | ||
| 214 | pwgt1 = regulator_get(NULL, "pwgt1"); | ||
| 215 | pwgt2 = regulator_get(NULL, "pwgt2"); | ||
| 216 | if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) { | ||
| 217 | regulator_enable(pwgt1); | ||
| 218 | regulator_enable(pwgt2); | ||
| 219 | } | ||
| 220 | gpio_request(EFIKASB_POWEROFF, "poweroff"); | ||
| 221 | pm_power_off = mx51_efikasb_power_off; | ||
| 222 | |||
| 223 | regulator_has_full_constraints(); | ||
| 224 | |||
| 225 | return 0; | ||
| 226 | } | ||
| 227 | |||
| 228 | static void __init mx51_efikasb_init_late(void) | ||
| 229 | { | ||
| 230 | imx51_init_late(); | ||
| 231 | mx51_efikasb_power_init(); | ||
| 232 | } | ||
| 233 | |||
| 234 | /* 01 R1.3 board | ||
| 235 | 10 R2.0 board */ | ||
| 236 | static void __init mx51_efikasb_board_id(void) | ||
| 237 | { | ||
| 238 | int id; | ||
| 239 | |||
| 240 | gpio_request(EFIKASB_PCBID0, "pcb id0"); | ||
| 241 | gpio_direction_input(EFIKASB_PCBID0); | ||
| 242 | gpio_request(EFIKASB_PCBID1, "pcb id1"); | ||
| 243 | gpio_direction_input(EFIKASB_PCBID1); | ||
| 244 | |||
| 245 | id = gpio_get_value(EFIKASB_PCBID0) ? 1 : 0; | ||
| 246 | id |= (gpio_get_value(EFIKASB_PCBID1) ? 1 : 0) << 1; | ||
| 247 | |||
| 248 | switch (id) { | ||
| 249 | default: | ||
| 250 | break; | ||
| 251 | case 1: | ||
| 252 | system_rev = 0x13; | ||
| 253 | break; | ||
| 254 | case 2: | ||
| 255 | system_rev = 0x20; | ||
| 256 | break; | ||
| 257 | } | ||
| 258 | } | ||
| 259 | |||
| 260 | static void __init efikasb_board_init(void) | ||
| 261 | { | ||
| 262 | imx51_soc_init(); | ||
| 263 | |||
| 264 | mxc_iomux_v3_setup_multiple_pads(mx51efikasb_pads, | ||
| 265 | ARRAY_SIZE(mx51efikasb_pads)); | ||
| 266 | efika_board_common_init(); | ||
| 267 | |||
| 268 | mx51_efikasb_board_id(); | ||
| 269 | mx51_efikasb_usb(); | ||
| 270 | imx51_add_sdhci_esdhc_imx(0, &sd0_pdata); | ||
| 271 | imx51_add_sdhci_esdhc_imx(1, &sd1_pdata); | ||
| 272 | |||
| 273 | gpio_led_register_device(-1, &mx51_efikasb_leds_data); | ||
| 274 | imx_add_gpio_keys(&mx51_efikasb_keys_data); | ||
| 275 | } | ||
| 276 | |||
| 277 | static void __init mx51_efikasb_timer_init(void) | ||
| 278 | { | ||
| 279 | mx51_clocks_init(32768, 24000000, 22579200, 24576000); | ||
| 280 | } | ||
| 281 | |||
| 282 | static struct sys_timer mx51_efikasb_timer = { | ||
| 283 | .init = mx51_efikasb_timer_init, | ||
| 284 | }; | ||
| 285 | |||
| 286 | MACHINE_START(MX51_EFIKASB, "Genesi Efika MX (Smartbook)") | ||
| 287 | .atag_offset = 0x100, | ||
| 288 | .map_io = mx51_map_io, | ||
| 289 | .init_early = imx51_init_early, | ||
| 290 | .init_irq = mx51_init_irq, | ||
| 291 | .handle_irq = imx51_handle_irq, | ||
| 292 | .init_machine = efikasb_board_init, | ||
| 293 | .init_late = mx51_efikasb_init_late, | ||
| 294 | .timer = &mx51_efikasb_timer, | ||
| 295 | .restart = mxc_restart, | ||
| 296 | MACHINE_END | ||
diff --git a/arch/arm/mach-imx/mach-mx53_ard.c b/arch/arm/mach-imx/mach-mx53_ard.c deleted file mode 100644 index 6c28e65f424d..000000000000 --- a/arch/arm/mach-imx/mach-mx53_ard.c +++ /dev/null | |||
| @@ -1,272 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | */ | ||
| 4 | |||
| 5 | /* | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | |||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | |||
| 16 | * You should have received a copy of the GNU General Public License along | ||
| 17 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #include <linux/init.h> | ||
| 22 | #include <linux/clk.h> | ||
| 23 | #include <linux/delay.h> | ||
| 24 | #include <linux/gpio.h> | ||
| 25 | #include <linux/smsc911x.h> | ||
| 26 | #include <linux/regulator/machine.h> | ||
| 27 | #include <linux/regulator/fixed.h> | ||
| 28 | |||
| 29 | #include <mach/common.h> | ||
| 30 | #include <mach/hardware.h> | ||
| 31 | #include <mach/iomux-mx53.h> | ||
| 32 | |||
| 33 | #include <asm/mach-types.h> | ||
| 34 | #include <asm/mach/arch.h> | ||
| 35 | #include <asm/mach/time.h> | ||
| 36 | |||
| 37 | #include "devices-imx53.h" | ||
| 38 | |||
| 39 | #define ARD_ETHERNET_INT_B IMX_GPIO_NR(2, 31) | ||
| 40 | #define ARD_SD1_CD IMX_GPIO_NR(1, 1) | ||
| 41 | #define ARD_SD1_WP IMX_GPIO_NR(1, 9) | ||
| 42 | #define ARD_I2CPORTEXP_B IMX_GPIO_NR(2, 3) | ||
| 43 | #define ARD_VOLUMEDOWN IMX_GPIO_NR(4, 0) | ||
| 44 | #define ARD_HOME IMX_GPIO_NR(5, 10) | ||
| 45 | #define ARD_BACK IMX_GPIO_NR(5, 11) | ||
| 46 | #define ARD_PROG IMX_GPIO_NR(5, 12) | ||
| 47 | #define ARD_VOLUMEUP IMX_GPIO_NR(5, 13) | ||
| 48 | |||
| 49 | static iomux_v3_cfg_t mx53_ard_pads[] = { | ||
| 50 | /* UART1 */ | ||
| 51 | MX53_PAD_PATA_DIOW__UART1_TXD_MUX, | ||
| 52 | MX53_PAD_PATA_DMACK__UART1_RXD_MUX, | ||
| 53 | /* WEIM for CS1 */ | ||
| 54 | MX53_PAD_EIM_EB3__GPIO2_31, /* ETHERNET_INT_B */ | ||
| 55 | MX53_PAD_EIM_D16__EMI_WEIM_D_16, | ||
| 56 | MX53_PAD_EIM_D17__EMI_WEIM_D_17, | ||
| 57 | MX53_PAD_EIM_D18__EMI_WEIM_D_18, | ||
| 58 | MX53_PAD_EIM_D19__EMI_WEIM_D_19, | ||
| 59 | MX53_PAD_EIM_D20__EMI_WEIM_D_20, | ||
| 60 | MX53_PAD_EIM_D21__EMI_WEIM_D_21, | ||
| 61 | MX53_PAD_EIM_D22__EMI_WEIM_D_22, | ||
| 62 | MX53_PAD_EIM_D23__EMI_WEIM_D_23, | ||
| 63 | MX53_PAD_EIM_D24__EMI_WEIM_D_24, | ||
| 64 | MX53_PAD_EIM_D25__EMI_WEIM_D_25, | ||
| 65 | MX53_PAD_EIM_D26__EMI_WEIM_D_26, | ||
| 66 | MX53_PAD_EIM_D27__EMI_WEIM_D_27, | ||
| 67 | MX53_PAD_EIM_D28__EMI_WEIM_D_28, | ||
| 68 | MX53_PAD_EIM_D29__EMI_WEIM_D_29, | ||
| 69 | MX53_PAD_EIM_D30__EMI_WEIM_D_30, | ||
| 70 | MX53_PAD_EIM_D31__EMI_WEIM_D_31, | ||
| 71 | MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0, | ||
| 72 | MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1, | ||
| 73 | MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2, | ||
| 74 | MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3, | ||
| 75 | MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4, | ||
| 76 | MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5, | ||
| 77 | MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6, | ||
| 78 | MX53_PAD_EIM_OE__EMI_WEIM_OE, | ||
| 79 | MX53_PAD_EIM_RW__EMI_WEIM_RW, | ||
| 80 | MX53_PAD_EIM_CS1__EMI_WEIM_CS_1, | ||
| 81 | /* SDHC1 */ | ||
| 82 | MX53_PAD_SD1_CMD__ESDHC1_CMD, | ||
| 83 | MX53_PAD_SD1_CLK__ESDHC1_CLK, | ||
| 84 | MX53_PAD_SD1_DATA0__ESDHC1_DAT0, | ||
| 85 | MX53_PAD_SD1_DATA1__ESDHC1_DAT1, | ||
| 86 | MX53_PAD_SD1_DATA2__ESDHC1_DAT2, | ||
| 87 | MX53_PAD_SD1_DATA3__ESDHC1_DAT3, | ||
| 88 | MX53_PAD_PATA_DATA8__ESDHC1_DAT4, | ||
| 89 | MX53_PAD_PATA_DATA9__ESDHC1_DAT5, | ||
| 90 | MX53_PAD_PATA_DATA10__ESDHC1_DAT6, | ||
| 91 | MX53_PAD_PATA_DATA11__ESDHC1_DAT7, | ||
| 92 | MX53_PAD_GPIO_1__GPIO1_1, | ||
| 93 | MX53_PAD_GPIO_9__GPIO1_9, | ||
| 94 | /* I2C2 */ | ||
| 95 | MX53_PAD_EIM_EB2__I2C2_SCL, | ||
| 96 | MX53_PAD_KEY_ROW3__I2C2_SDA, | ||
| 97 | /* I2C3 */ | ||
| 98 | MX53_PAD_GPIO_3__I2C3_SCL, | ||
| 99 | MX53_PAD_GPIO_16__I2C3_SDA, | ||
| 100 | /* GPIO */ | ||
| 101 | MX53_PAD_DISP0_DAT16__GPIO5_10, /* home */ | ||
| 102 | MX53_PAD_DISP0_DAT17__GPIO5_11, /* back */ | ||
| 103 | MX53_PAD_DISP0_DAT18__GPIO5_12, /* prog */ | ||
| 104 | MX53_PAD_DISP0_DAT19__GPIO5_13, /* vol up */ | ||
| 105 | MX53_PAD_GPIO_10__GPIO4_0, /* vol down */ | ||
| 106 | }; | ||
| 107 | |||
| 108 | #define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \ | ||
| 109 | { \ | ||
| 110 | .gpio = gpio_num, \ | ||
| 111 | .type = EV_KEY, \ | ||
| 112 | .code = ev_code, \ | ||
| 113 | .active_low = act_low, \ | ||
| 114 | .desc = "btn " descr, \ | ||
| 115 | .wakeup = wake, \ | ||
| 116 | } | ||
| 117 | |||
| 118 | static struct gpio_keys_button ard_buttons[] = { | ||
| 119 | GPIO_BUTTON(ARD_HOME, KEY_HOME, 1, "home", 0), | ||
| 120 | GPIO_BUTTON(ARD_BACK, KEY_BACK, 1, "back", 0), | ||
| 121 | GPIO_BUTTON(ARD_PROG, KEY_PROGRAM, 1, "program", 0), | ||
| 122 | GPIO_BUTTON(ARD_VOLUMEUP, KEY_VOLUMEUP, 1, "volume-up", 0), | ||
| 123 | GPIO_BUTTON(ARD_VOLUMEDOWN, KEY_VOLUMEDOWN, 1, "volume-down", 0), | ||
| 124 | }; | ||
| 125 | |||
| 126 | static const struct gpio_keys_platform_data ard_button_data __initconst = { | ||
| 127 | .buttons = ard_buttons, | ||
| 128 | .nbuttons = ARRAY_SIZE(ard_buttons), | ||
| 129 | }; | ||
| 130 | |||
| 131 | static struct resource ard_smsc911x_resources[] = { | ||
| 132 | { | ||
| 133 | .start = MX53_CS1_64MB_BASE_ADDR, | ||
| 134 | .end = MX53_CS1_64MB_BASE_ADDR + SZ_32M - 1, | ||
| 135 | .flags = IORESOURCE_MEM, | ||
| 136 | }, | ||
| 137 | { | ||
| 138 | /* irq number is run-time assigned */ | ||
| 139 | .flags = IORESOURCE_IRQ, | ||
| 140 | }, | ||
| 141 | }; | ||
| 142 | |||
| 143 | struct smsc911x_platform_config ard_smsc911x_config = { | ||
| 144 | .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, | ||
| 145 | .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, | ||
| 146 | .flags = SMSC911X_USE_32BIT, | ||
| 147 | }; | ||
| 148 | |||
| 149 | static struct platform_device ard_smsc_lan9220_device = { | ||
| 150 | .name = "smsc911x", | ||
| 151 | .id = -1, | ||
| 152 | .num_resources = ARRAY_SIZE(ard_smsc911x_resources), | ||
| 153 | .resource = ard_smsc911x_resources, | ||
| 154 | .dev = { | ||
| 155 | .platform_data = &ard_smsc911x_config, | ||
| 156 | }, | ||
| 157 | }; | ||
| 158 | |||
| 159 | static const struct esdhc_platform_data mx53_ard_sd1_data __initconst = { | ||
| 160 | .cd_gpio = ARD_SD1_CD, | ||
| 161 | .wp_gpio = ARD_SD1_WP, | ||
| 162 | }; | ||
| 163 | |||
| 164 | static struct imxi2c_platform_data mx53_ard_i2c2_data = { | ||
| 165 | .bitrate = 50000, | ||
| 166 | }; | ||
| 167 | |||
| 168 | static struct imxi2c_platform_data mx53_ard_i2c3_data = { | ||
| 169 | .bitrate = 400000, | ||
| 170 | }; | ||
| 171 | |||
| 172 | static void __init mx53_ard_io_init(void) | ||
| 173 | { | ||
| 174 | gpio_request(ARD_ETHERNET_INT_B, "eth-int-b"); | ||
| 175 | gpio_direction_input(ARD_ETHERNET_INT_B); | ||
| 176 | |||
| 177 | gpio_request(ARD_I2CPORTEXP_B, "i2cptexp-rst"); | ||
| 178 | gpio_direction_output(ARD_I2CPORTEXP_B, 1); | ||
| 179 | } | ||
| 180 | |||
| 181 | /* Config CS1 settings for ethernet controller */ | ||
| 182 | static int weim_cs_config(void) | ||
| 183 | { | ||
| 184 | u32 reg; | ||
| 185 | void __iomem *weim_base, *iomuxc_base; | ||
| 186 | |||
| 187 | weim_base = ioremap(MX53_WEIM_BASE_ADDR, SZ_4K); | ||
| 188 | if (!weim_base) | ||
| 189 | return -ENOMEM; | ||
| 190 | |||
| 191 | iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K); | ||
| 192 | if (!iomuxc_base) { | ||
| 193 | iounmap(weim_base); | ||
| 194 | return -ENOMEM; | ||
| 195 | } | ||
| 196 | |||
| 197 | /* CS1 timings for LAN9220 */ | ||
| 198 | writel(0x20001, (weim_base + 0x18)); | ||
| 199 | writel(0x0, (weim_base + 0x1C)); | ||
| 200 | writel(0x16000202, (weim_base + 0x20)); | ||
| 201 | writel(0x00000002, (weim_base + 0x24)); | ||
| 202 | writel(0x16002082, (weim_base + 0x28)); | ||
| 203 | writel(0x00000000, (weim_base + 0x2C)); | ||
| 204 | writel(0x00000000, (weim_base + 0x90)); | ||
| 205 | |||
| 206 | /* specify 64 MB on CS1 and CS0 on GPR1 */ | ||
| 207 | reg = readl(iomuxc_base + 0x4); | ||
| 208 | reg &= ~0x3F; | ||
| 209 | reg |= 0x1B; | ||
| 210 | writel(reg, (iomuxc_base + 0x4)); | ||
| 211 | |||
| 212 | iounmap(iomuxc_base); | ||
| 213 | iounmap(weim_base); | ||
| 214 | |||
| 215 | return 0; | ||
| 216 | } | ||
| 217 | |||
| 218 | static struct regulator_consumer_supply dummy_supplies[] = { | ||
| 219 | REGULATOR_SUPPLY("vdd33a", "smsc911x"), | ||
| 220 | REGULATOR_SUPPLY("vddvario", "smsc911x"), | ||
| 221 | }; | ||
| 222 | |||
| 223 | void __init imx53_ard_common_init(void) | ||
| 224 | { | ||
| 225 | mxc_iomux_v3_setup_multiple_pads(mx53_ard_pads, | ||
| 226 | ARRAY_SIZE(mx53_ard_pads)); | ||
| 227 | weim_cs_config(); | ||
| 228 | } | ||
| 229 | |||
| 230 | static struct platform_device *devices[] __initdata = { | ||
| 231 | &ard_smsc_lan9220_device, | ||
| 232 | }; | ||
| 233 | |||
| 234 | static void __init mx53_ard_board_init(void) | ||
| 235 | { | ||
| 236 | imx53_soc_init(); | ||
| 237 | imx53_add_imx_uart(0, NULL); | ||
| 238 | |||
| 239 | imx53_ard_common_init(); | ||
| 240 | mx53_ard_io_init(); | ||
| 241 | regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); | ||
| 242 | ard_smsc911x_resources[1].start = gpio_to_irq(ARD_ETHERNET_INT_B); | ||
| 243 | ard_smsc911x_resources[1].end = gpio_to_irq(ARD_ETHERNET_INT_B); | ||
| 244 | platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
| 245 | |||
| 246 | imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data); | ||
| 247 | imx53_add_imx2_wdt(0); | ||
| 248 | imx53_add_imx_i2c(1, &mx53_ard_i2c2_data); | ||
| 249 | imx53_add_imx_i2c(2, &mx53_ard_i2c3_data); | ||
| 250 | imx_add_gpio_keys(&ard_button_data); | ||
| 251 | imx53_add_ahci_imx(); | ||
| 252 | } | ||
| 253 | |||
| 254 | static void __init mx53_ard_timer_init(void) | ||
| 255 | { | ||
| 256 | mx53_clocks_init(32768, 24000000, 22579200, 0); | ||
| 257 | } | ||
| 258 | |||
| 259 | static struct sys_timer mx53_ard_timer = { | ||
| 260 | .init = mx53_ard_timer_init, | ||
| 261 | }; | ||
| 262 | |||
| 263 | MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board") | ||
| 264 | .map_io = mx53_map_io, | ||
| 265 | .init_early = imx53_init_early, | ||
| 266 | .init_irq = mx53_init_irq, | ||
| 267 | .handle_irq = imx53_handle_irq, | ||
| 268 | .timer = &mx53_ard_timer, | ||
| 269 | .init_machine = mx53_ard_board_init, | ||
| 270 | .init_late = imx53_init_late, | ||
| 271 | .restart = mxc_restart, | ||
| 272 | MACHINE_END | ||
diff --git a/arch/arm/mach-imx/mach-mx53_evk.c b/arch/arm/mach-imx/mach-mx53_evk.c deleted file mode 100644 index 09fe2197b491..000000000000 --- a/arch/arm/mach-imx/mach-mx53_evk.c +++ /dev/null | |||
| @@ -1,179 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org> | ||
| 4 | */ | ||
| 5 | |||
| 6 | /* | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | |||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | |||
| 17 | * You should have received a copy of the GNU General Public License along | ||
| 18 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
| 20 | */ | ||
| 21 | |||
| 22 | #include <linux/init.h> | ||
| 23 | #include <linux/clk.h> | ||
| 24 | #include <linux/delay.h> | ||
| 25 | #include <linux/gpio.h> | ||
| 26 | #include <linux/spi/flash.h> | ||
| 27 | #include <linux/spi/spi.h> | ||
| 28 | #include <mach/common.h> | ||
| 29 | #include <mach/hardware.h> | ||
| 30 | #include <asm/mach-types.h> | ||
| 31 | #include <asm/mach/arch.h> | ||
| 32 | #include <asm/mach/time.h> | ||
| 33 | #include <mach/iomux-mx53.h> | ||
| 34 | |||
| 35 | #define MX53_EVK_FEC_PHY_RST IMX_GPIO_NR(7, 6) | ||
| 36 | #define EVK_ECSPI1_CS0 IMX_GPIO_NR(2, 30) | ||
| 37 | #define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19) | ||
| 38 | #define MX53EVK_LED IMX_GPIO_NR(7, 7) | ||
| 39 | |||
| 40 | #include "devices-imx53.h" | ||
| 41 | |||
| 42 | static iomux_v3_cfg_t mx53_evk_pads[] = { | ||
| 43 | MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, | ||
| 44 | MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, | ||
| 45 | |||
| 46 | MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, | ||
| 47 | MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, | ||
| 48 | MX53_PAD_PATA_DIOR__UART2_RTS, | ||
| 49 | MX53_PAD_PATA_INTRQ__UART2_CTS, | ||
| 50 | |||
| 51 | MX53_PAD_PATA_CS_0__UART3_TXD_MUX, | ||
| 52 | MX53_PAD_PATA_CS_1__UART3_RXD_MUX, | ||
| 53 | |||
| 54 | MX53_PAD_EIM_D16__ECSPI1_SCLK, | ||
| 55 | MX53_PAD_EIM_D17__ECSPI1_MISO, | ||
| 56 | MX53_PAD_EIM_D18__ECSPI1_MOSI, | ||
| 57 | |||
| 58 | /* ecspi chip select lines */ | ||
| 59 | MX53_PAD_EIM_EB2__GPIO2_30, | ||
| 60 | MX53_PAD_EIM_D19__GPIO3_19, | ||
| 61 | /* LED */ | ||
| 62 | MX53_PAD_PATA_DA_1__GPIO7_7, | ||
| 63 | }; | ||
| 64 | |||
| 65 | static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = { | ||
| 66 | .flags = IMXUART_HAVE_RTSCTS, | ||
| 67 | }; | ||
| 68 | |||
| 69 | static const struct gpio_led mx53evk_leds[] __initconst = { | ||
| 70 | { | ||
| 71 | .name = "green", | ||
| 72 | .default_trigger = "heartbeat", | ||
| 73 | .gpio = MX53EVK_LED, | ||
| 74 | }, | ||
| 75 | }; | ||
| 76 | |||
| 77 | static const struct gpio_led_platform_data mx53evk_leds_data __initconst = { | ||
| 78 | .leds = mx53evk_leds, | ||
| 79 | .num_leds = ARRAY_SIZE(mx53evk_leds), | ||
| 80 | }; | ||
| 81 | |||
| 82 | static inline void mx53_evk_init_uart(void) | ||
| 83 | { | ||
| 84 | imx53_add_imx_uart(0, NULL); | ||
| 85 | imx53_add_imx_uart(1, &mx53_evk_uart_pdata); | ||
| 86 | imx53_add_imx_uart(2, NULL); | ||
| 87 | } | ||
| 88 | |||
| 89 | static const struct imxi2c_platform_data mx53_evk_i2c_data __initconst = { | ||
| 90 | .bitrate = 100000, | ||
| 91 | }; | ||
| 92 | |||
| 93 | static inline void mx53_evk_fec_reset(void) | ||
| 94 | { | ||
| 95 | int ret; | ||
| 96 | |||
| 97 | /* reset FEC PHY */ | ||
| 98 | ret = gpio_request_one(MX53_EVK_FEC_PHY_RST, GPIOF_OUT_INIT_LOW, | ||
| 99 | "fec-phy-reset"); | ||
| 100 | if (ret) { | ||
| 101 | printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); | ||
| 102 | return; | ||
| 103 | } | ||
| 104 | msleep(1); | ||
| 105 | gpio_set_value(MX53_EVK_FEC_PHY_RST, 1); | ||
| 106 | } | ||
| 107 | |||
| 108 | static const struct fec_platform_data mx53_evk_fec_pdata __initconst = { | ||
| 109 | .phy = PHY_INTERFACE_MODE_RMII, | ||
| 110 | }; | ||
| 111 | |||
| 112 | static struct spi_board_info mx53_evk_spi_board_info[] __initdata = { | ||
| 113 | { | ||
| 114 | .modalias = "mtd_dataflash", | ||
| 115 | .max_speed_hz = 25000000, | ||
| 116 | .bus_num = 0, | ||
| 117 | .chip_select = 1, | ||
| 118 | .mode = SPI_MODE_0, | ||
| 119 | .platform_data = NULL, | ||
| 120 | }, | ||
| 121 | }; | ||
| 122 | |||
| 123 | static int mx53_evk_spi_cs[] = { | ||
| 124 | EVK_ECSPI1_CS0, | ||
| 125 | EVK_ECSPI1_CS1, | ||
| 126 | }; | ||
| 127 | |||
| 128 | static const struct spi_imx_master mx53_evk_spi_data __initconst = { | ||
| 129 | .chipselect = mx53_evk_spi_cs, | ||
| 130 | .num_chipselect = ARRAY_SIZE(mx53_evk_spi_cs), | ||
| 131 | }; | ||
| 132 | |||
| 133 | void __init imx53_evk_common_init(void) | ||
| 134 | { | ||
| 135 | mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads, | ||
| 136 | ARRAY_SIZE(mx53_evk_pads)); | ||
| 137 | } | ||
| 138 | |||
| 139 | static void __init mx53_evk_board_init(void) | ||
| 140 | { | ||
| 141 | imx53_soc_init(); | ||
| 142 | imx53_evk_common_init(); | ||
| 143 | |||
| 144 | mx53_evk_init_uart(); | ||
| 145 | mx53_evk_fec_reset(); | ||
| 146 | imx53_add_fec(&mx53_evk_fec_pdata); | ||
| 147 | |||
| 148 | imx53_add_imx_i2c(0, &mx53_evk_i2c_data); | ||
| 149 | imx53_add_imx_i2c(1, &mx53_evk_i2c_data); | ||
| 150 | |||
| 151 | imx53_add_sdhci_esdhc_imx(0, NULL); | ||
| 152 | imx53_add_sdhci_esdhc_imx(1, NULL); | ||
| 153 | |||
| 154 | spi_register_board_info(mx53_evk_spi_board_info, | ||
| 155 | ARRAY_SIZE(mx53_evk_spi_board_info)); | ||
| 156 | imx53_add_ecspi(0, &mx53_evk_spi_data); | ||
| 157 | imx53_add_imx2_wdt(0); | ||
| 158 | gpio_led_register_device(-1, &mx53evk_leds_data); | ||
| 159 | } | ||
| 160 | |||
| 161 | static void __init mx53_evk_timer_init(void) | ||
| 162 | { | ||
| 163 | mx53_clocks_init(32768, 24000000, 22579200, 0); | ||
| 164 | } | ||
| 165 | |||
| 166 | static struct sys_timer mx53_evk_timer = { | ||
| 167 | .init = mx53_evk_timer_init, | ||
| 168 | }; | ||
| 169 | |||
| 170 | MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board") | ||
| 171 | .map_io = mx53_map_io, | ||
| 172 | .init_early = imx53_init_early, | ||
| 173 | .init_irq = mx53_init_irq, | ||
| 174 | .handle_irq = imx53_handle_irq, | ||
| 175 | .timer = &mx53_evk_timer, | ||
| 176 | .init_machine = mx53_evk_board_init, | ||
| 177 | .init_late = imx53_init_late, | ||
| 178 | .restart = mxc_restart, | ||
| 179 | MACHINE_END | ||
diff --git a/arch/arm/mach-imx/mach-mx53_loco.c b/arch/arm/mach-imx/mach-mx53_loco.c deleted file mode 100644 index 8abe23c1d3c8..000000000000 --- a/arch/arm/mach-imx/mach-mx53_loco.c +++ /dev/null | |||
| @@ -1,321 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | */ | ||
| 4 | |||
| 5 | /* | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | |||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | |||
| 16 | * You should have received a copy of the GNU General Public License along | ||
| 17 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #include <linux/init.h> | ||
| 22 | #include <linux/clk.h> | ||
| 23 | #include <linux/delay.h> | ||
| 24 | #include <linux/gpio.h> | ||
| 25 | #include <linux/i2c.h> | ||
| 26 | |||
| 27 | #include <mach/common.h> | ||
| 28 | #include <mach/hardware.h> | ||
| 29 | #include <mach/iomux-mx53.h> | ||
| 30 | |||
| 31 | #include <asm/mach-types.h> | ||
| 32 | #include <asm/mach/arch.h> | ||
| 33 | #include <asm/mach/time.h> | ||
| 34 | |||
| 35 | #include "devices-imx53.h" | ||
| 36 | |||
| 37 | #define MX53_LOCO_POWER IMX_GPIO_NR(1, 8) | ||
| 38 | #define MX53_LOCO_UI1 IMX_GPIO_NR(2, 14) | ||
| 39 | #define MX53_LOCO_UI2 IMX_GPIO_NR(2, 15) | ||
| 40 | #define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6) | ||
| 41 | #define LOCO_LED IMX_GPIO_NR(7, 7) | ||
| 42 | #define LOCO_SD3_CD IMX_GPIO_NR(3, 11) | ||
| 43 | #define LOCO_SD3_WP IMX_GPIO_NR(3, 12) | ||
| 44 | #define LOCO_SD1_CD IMX_GPIO_NR(3, 13) | ||
| 45 | #define LOCO_ACCEL_EN IMX_GPIO_NR(6, 14) | ||
| 46 | |||
| 47 | static iomux_v3_cfg_t mx53_loco_pads[] = { | ||
| 48 | /* FEC */ | ||
| 49 | MX53_PAD_FEC_MDC__FEC_MDC, | ||
| 50 | MX53_PAD_FEC_MDIO__FEC_MDIO, | ||
| 51 | MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, | ||
| 52 | MX53_PAD_FEC_RX_ER__FEC_RX_ER, | ||
| 53 | MX53_PAD_FEC_CRS_DV__FEC_RX_DV, | ||
| 54 | MX53_PAD_FEC_RXD1__FEC_RDATA_1, | ||
| 55 | MX53_PAD_FEC_RXD0__FEC_RDATA_0, | ||
| 56 | MX53_PAD_FEC_TX_EN__FEC_TX_EN, | ||
| 57 | MX53_PAD_FEC_TXD1__FEC_TDATA_1, | ||
| 58 | MX53_PAD_FEC_TXD0__FEC_TDATA_0, | ||
| 59 | /* FEC_nRST */ | ||
| 60 | MX53_PAD_PATA_DA_0__GPIO7_6, | ||
| 61 | /* FEC_nINT */ | ||
| 62 | MX53_PAD_PATA_DATA4__GPIO2_4, | ||
| 63 | /* AUDMUX5 */ | ||
| 64 | MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC, | ||
| 65 | MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD, | ||
| 66 | MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS, | ||
| 67 | MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD, | ||
| 68 | /* I2C1 */ | ||
| 69 | MX53_PAD_CSI0_DAT8__I2C1_SDA, | ||
| 70 | MX53_PAD_CSI0_DAT9__I2C1_SCL, | ||
| 71 | MX53_PAD_NANDF_CS1__GPIO6_14, /* Accelerometer Enable */ | ||
| 72 | /* I2C2 */ | ||
| 73 | MX53_PAD_KEY_COL3__I2C2_SCL, | ||
| 74 | MX53_PAD_KEY_ROW3__I2C2_SDA, | ||
| 75 | /* SD1 */ | ||
| 76 | MX53_PAD_SD1_CMD__ESDHC1_CMD, | ||
| 77 | MX53_PAD_SD1_CLK__ESDHC1_CLK, | ||
| 78 | MX53_PAD_SD1_DATA0__ESDHC1_DAT0, | ||
| 79 | MX53_PAD_SD1_DATA1__ESDHC1_DAT1, | ||
| 80 | MX53_PAD_SD1_DATA2__ESDHC1_DAT2, | ||
| 81 | MX53_PAD_SD1_DATA3__ESDHC1_DAT3, | ||
| 82 | /* SD1_CD */ | ||
| 83 | MX53_PAD_EIM_DA13__GPIO3_13, | ||
| 84 | /* SD3 */ | ||
| 85 | MX53_PAD_PATA_DATA8__ESDHC3_DAT0, | ||
| 86 | MX53_PAD_PATA_DATA9__ESDHC3_DAT1, | ||
| 87 | MX53_PAD_PATA_DATA10__ESDHC3_DAT2, | ||
| 88 | MX53_PAD_PATA_DATA11__ESDHC3_DAT3, | ||
| 89 | MX53_PAD_PATA_DATA0__ESDHC3_DAT4, | ||
| 90 | MX53_PAD_PATA_DATA1__ESDHC3_DAT5, | ||
| 91 | MX53_PAD_PATA_DATA2__ESDHC3_DAT6, | ||
| 92 | MX53_PAD_PATA_DATA3__ESDHC3_DAT7, | ||
| 93 | MX53_PAD_PATA_IORDY__ESDHC3_CLK, | ||
| 94 | MX53_PAD_PATA_RESET_B__ESDHC3_CMD, | ||
| 95 | /* SD3_CD */ | ||
| 96 | MX53_PAD_EIM_DA11__GPIO3_11, | ||
| 97 | /* SD3_WP */ | ||
| 98 | MX53_PAD_EIM_DA12__GPIO3_12, | ||
| 99 | /* VGA */ | ||
| 100 | MX53_PAD_EIM_OE__IPU_DI1_PIN7, | ||
| 101 | MX53_PAD_EIM_RW__IPU_DI1_PIN8, | ||
| 102 | /* DISPLB */ | ||
| 103 | MX53_PAD_EIM_D20__IPU_SER_DISP0_CS, | ||
| 104 | MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK, | ||
| 105 | MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN, | ||
| 106 | MX53_PAD_EIM_D23__IPU_DI0_D0_CS, | ||
| 107 | /* DISP0_POWER_EN */ | ||
| 108 | MX53_PAD_EIM_D24__GPIO3_24, | ||
| 109 | /* DISP0 DET INT */ | ||
| 110 | MX53_PAD_EIM_D31__GPIO3_31, | ||
| 111 | /* LVDS */ | ||
| 112 | MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3, | ||
| 113 | MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK, | ||
| 114 | MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2, | ||
| 115 | MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1, | ||
| 116 | MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0, | ||
| 117 | MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3, | ||
| 118 | MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2, | ||
| 119 | MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK, | ||
| 120 | MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1, | ||
| 121 | MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0, | ||
| 122 | /* I2C1 */ | ||
| 123 | MX53_PAD_CSI0_DAT8__I2C1_SDA, | ||
| 124 | MX53_PAD_CSI0_DAT9__I2C1_SCL, | ||
| 125 | /* UART1 */ | ||
| 126 | MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, | ||
| 127 | MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, | ||
| 128 | /* CSI0 */ | ||
| 129 | MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12, | ||
| 130 | MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13, | ||
| 131 | MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14, | ||
| 132 | MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15, | ||
| 133 | MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16, | ||
| 134 | MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17, | ||
| 135 | MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18, | ||
| 136 | MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19, | ||
| 137 | MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC, | ||
| 138 | MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC, | ||
| 139 | MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK, | ||
| 140 | /* DISPLAY */ | ||
| 141 | MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK, | ||
| 142 | MX53_PAD_DI0_PIN15__IPU_DI0_PIN15, | ||
| 143 | MX53_PAD_DI0_PIN2__IPU_DI0_PIN2, | ||
| 144 | MX53_PAD_DI0_PIN3__IPU_DI0_PIN3, | ||
| 145 | MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0, | ||
| 146 | MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1, | ||
| 147 | MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2, | ||
| 148 | MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3, | ||
| 149 | MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4, | ||
| 150 | MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5, | ||
| 151 | MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6, | ||
| 152 | MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7, | ||
| 153 | MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8, | ||
| 154 | MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9, | ||
| 155 | MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10, | ||
| 156 | MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11, | ||
| 157 | MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12, | ||
| 158 | MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13, | ||
| 159 | MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14, | ||
| 160 | MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15, | ||
| 161 | MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16, | ||
| 162 | MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17, | ||
| 163 | MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18, | ||
| 164 | MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19, | ||
| 165 | MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20, | ||
| 166 | MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21, | ||
| 167 | MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22, | ||
| 168 | MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23, | ||
| 169 | /* Audio CLK*/ | ||
| 170 | MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK, | ||
| 171 | /* PWM */ | ||
| 172 | MX53_PAD_GPIO_1__PWM2_PWMO, | ||
| 173 | /* SPDIF */ | ||
| 174 | MX53_PAD_GPIO_7__SPDIF_PLOCK, | ||
| 175 | MX53_PAD_GPIO_17__SPDIF_OUT1, | ||
| 176 | /* GPIO */ | ||
| 177 | MX53_PAD_PATA_DA_1__GPIO7_7, /* LED */ | ||
| 178 | MX53_PAD_PATA_DA_2__GPIO7_8, | ||
| 179 | MX53_PAD_PATA_DATA5__GPIO2_5, | ||
| 180 | MX53_PAD_PATA_DATA6__GPIO2_6, | ||
| 181 | MX53_PAD_PATA_DATA14__GPIO2_14, | ||
| 182 | MX53_PAD_PATA_DATA15__GPIO2_15, | ||
| 183 | MX53_PAD_PATA_INTRQ__GPIO7_2, | ||
| 184 | MX53_PAD_EIM_WAIT__GPIO5_0, | ||
| 185 | MX53_PAD_NANDF_WP_B__GPIO6_9, | ||
| 186 | MX53_PAD_NANDF_RB0__GPIO6_10, | ||
| 187 | MX53_PAD_NANDF_CS1__GPIO6_14, | ||
| 188 | MX53_PAD_NANDF_CS2__GPIO6_15, | ||
| 189 | MX53_PAD_NANDF_CS3__GPIO6_16, | ||
| 190 | MX53_PAD_GPIO_5__GPIO1_5, | ||
| 191 | MX53_PAD_GPIO_16__GPIO7_11, | ||
| 192 | MX53_PAD_GPIO_8__GPIO1_8, | ||
| 193 | }; | ||
| 194 | |||
| 195 | #define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \ | ||
| 196 | { \ | ||
| 197 | .gpio = gpio_num, \ | ||
| 198 | .type = EV_KEY, \ | ||
| 199 | .code = ev_code, \ | ||
| 200 | .active_low = act_low, \ | ||
| 201 | .desc = "btn " descr, \ | ||
| 202 | .wakeup = wake, \ | ||
| 203 | } | ||
| 204 | |||
| 205 | static struct gpio_keys_button loco_buttons[] = { | ||
| 206 | GPIO_BUTTON(MX53_LOCO_POWER, KEY_POWER, 1, "power", 0), | ||
| 207 | GPIO_BUTTON(MX53_LOCO_UI1, KEY_VOLUMEUP, 1, "volume-up", 0), | ||
| 208 | GPIO_BUTTON(MX53_LOCO_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0), | ||
| 209 | }; | ||
| 210 | |||
| 211 | static const struct gpio_keys_platform_data loco_button_data __initconst = { | ||
| 212 | .buttons = loco_buttons, | ||
| 213 | .nbuttons = ARRAY_SIZE(loco_buttons), | ||
| 214 | }; | ||
| 215 | |||
| 216 | static const struct esdhc_platform_data mx53_loco_sd1_data __initconst = { | ||
| 217 | .cd_gpio = LOCO_SD1_CD, | ||
| 218 | .cd_type = ESDHC_CD_GPIO, | ||
| 219 | .wp_type = ESDHC_WP_NONE, | ||
| 220 | }; | ||
| 221 | |||
| 222 | static const struct esdhc_platform_data mx53_loco_sd3_data __initconst = { | ||
| 223 | .cd_gpio = LOCO_SD3_CD, | ||
| 224 | .wp_gpio = LOCO_SD3_WP, | ||
| 225 | .cd_type = ESDHC_CD_GPIO, | ||
| 226 | .wp_type = ESDHC_WP_GPIO, | ||
| 227 | }; | ||
| 228 | |||
| 229 | static inline void mx53_loco_fec_reset(void) | ||
| 230 | { | ||
| 231 | int ret; | ||
| 232 | |||
| 233 | /* reset FEC PHY */ | ||
| 234 | ret = gpio_request(LOCO_FEC_PHY_RST, "fec-phy-reset"); | ||
| 235 | if (ret) { | ||
| 236 | printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); | ||
| 237 | return; | ||
| 238 | } | ||
| 239 | gpio_direction_output(LOCO_FEC_PHY_RST, 0); | ||
| 240 | msleep(1); | ||
| 241 | gpio_set_value(LOCO_FEC_PHY_RST, 1); | ||
| 242 | } | ||
| 243 | |||
| 244 | static const struct fec_platform_data mx53_loco_fec_data __initconst = { | ||
| 245 | .phy = PHY_INTERFACE_MODE_RMII, | ||
| 246 | }; | ||
| 247 | |||
| 248 | static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = { | ||
| 249 | .bitrate = 100000, | ||
| 250 | }; | ||
| 251 | |||
| 252 | static const struct gpio_led mx53loco_leds[] __initconst = { | ||
| 253 | { | ||
| 254 | .name = "green", | ||
| 255 | .default_trigger = "heartbeat", | ||
| 256 | .gpio = LOCO_LED, | ||
| 257 | }, | ||
| 258 | }; | ||
| 259 | |||
| 260 | static const struct gpio_led_platform_data mx53loco_leds_data __initconst = { | ||
| 261 | .leds = mx53loco_leds, | ||
| 262 | .num_leds = ARRAY_SIZE(mx53loco_leds), | ||
| 263 | }; | ||
| 264 | |||
| 265 | void __init imx53_qsb_common_init(void) | ||
| 266 | { | ||
| 267 | mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads, | ||
| 268 | ARRAY_SIZE(mx53_loco_pads)); | ||
| 269 | } | ||
| 270 | |||
| 271 | static struct i2c_board_info mx53loco_i2c_devices[] = { | ||
| 272 | { | ||
| 273 | I2C_BOARD_INFO("mma8450", 0x1C), | ||
| 274 | }, | ||
| 275 | }; | ||
| 276 | |||
| 277 | static void __init mx53_loco_board_init(void) | ||
| 278 | { | ||
| 279 | int ret; | ||
| 280 | imx53_soc_init(); | ||
| 281 | imx53_qsb_common_init(); | ||
| 282 | |||
| 283 | imx53_add_imx_uart(0, NULL); | ||
| 284 | mx53_loco_fec_reset(); | ||
| 285 | imx53_add_fec(&mx53_loco_fec_data); | ||
| 286 | imx53_add_imx2_wdt(0); | ||
| 287 | |||
| 288 | ret = gpio_request_one(LOCO_ACCEL_EN, GPIOF_OUT_INIT_HIGH, "accel_en"); | ||
| 289 | if (ret) | ||
| 290 | pr_err("Cannot request ACCEL_EN pin: %d\n", ret); | ||
| 291 | |||
| 292 | i2c_register_board_info(0, mx53loco_i2c_devices, | ||
| 293 | ARRAY_SIZE(mx53loco_i2c_devices)); | ||
| 294 | imx53_add_imx_i2c(0, &mx53_loco_i2c_data); | ||
| 295 | imx53_add_imx_i2c(1, &mx53_loco_i2c_data); | ||
| 296 | imx53_add_sdhci_esdhc_imx(0, &mx53_loco_sd1_data); | ||
| 297 | imx53_add_sdhci_esdhc_imx(2, &mx53_loco_sd3_data); | ||
| 298 | imx_add_gpio_keys(&loco_button_data); | ||
| 299 | gpio_led_register_device(-1, &mx53loco_leds_data); | ||
| 300 | imx53_add_ahci_imx(); | ||
| 301 | } | ||
| 302 | |||
| 303 | static void __init mx53_loco_timer_init(void) | ||
| 304 | { | ||
| 305 | mx53_clocks_init(32768, 24000000, 0, 0); | ||
| 306 | } | ||
| 307 | |||
| 308 | static struct sys_timer mx53_loco_timer = { | ||
| 309 | .init = mx53_loco_timer_init, | ||
| 310 | }; | ||
| 311 | |||
| 312 | MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board") | ||
| 313 | .map_io = mx53_map_io, | ||
| 314 | .init_early = imx53_init_early, | ||
| 315 | .init_irq = mx53_init_irq, | ||
| 316 | .handle_irq = imx53_handle_irq, | ||
| 317 | .timer = &mx53_loco_timer, | ||
| 318 | .init_machine = mx53_loco_board_init, | ||
| 319 | .init_late = imx53_init_late, | ||
| 320 | .restart = mxc_restart, | ||
| 321 | MACHINE_END | ||
diff --git a/arch/arm/mach-imx/mach-mx53_smd.c b/arch/arm/mach-imx/mach-mx53_smd.c deleted file mode 100644 index b15d6a6d3b68..000000000000 --- a/arch/arm/mach-imx/mach-mx53_smd.c +++ /dev/null | |||
| @@ -1,168 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | */ | ||
| 4 | |||
| 5 | /* | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | |||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | |||
| 16 | * You should have received a copy of the GNU General Public License along | ||
| 17 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #include <linux/init.h> | ||
| 22 | #include <linux/clk.h> | ||
| 23 | #include <linux/delay.h> | ||
| 24 | #include <linux/gpio.h> | ||
| 25 | |||
| 26 | #include <mach/common.h> | ||
| 27 | #include <mach/hardware.h> | ||
| 28 | #include <mach/iomux-mx53.h> | ||
| 29 | |||
| 30 | #include <asm/mach-types.h> | ||
| 31 | #include <asm/mach/arch.h> | ||
| 32 | #include <asm/mach/time.h> | ||
| 33 | |||
| 34 | #include "devices-imx53.h" | ||
| 35 | |||
| 36 | #define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6) | ||
| 37 | #define MX53_SMD_SATA_PWR_EN IMX_GPIO_NR(3, 3) | ||
| 38 | |||
| 39 | static iomux_v3_cfg_t mx53_smd_pads[] = { | ||
| 40 | MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, | ||
| 41 | MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, | ||
| 42 | |||
| 43 | MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, | ||
| 44 | MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, | ||
| 45 | |||
| 46 | MX53_PAD_PATA_CS_0__UART3_TXD_MUX, | ||
| 47 | MX53_PAD_PATA_CS_1__UART3_RXD_MUX, | ||
| 48 | MX53_PAD_PATA_DA_1__UART3_CTS, | ||
| 49 | MX53_PAD_PATA_DA_2__UART3_RTS, | ||
| 50 | /* I2C1 */ | ||
| 51 | MX53_PAD_CSI0_DAT8__I2C1_SDA, | ||
| 52 | MX53_PAD_CSI0_DAT9__I2C1_SCL, | ||
| 53 | /* SD1 */ | ||
| 54 | MX53_PAD_SD1_CMD__ESDHC1_CMD, | ||
| 55 | MX53_PAD_SD1_CLK__ESDHC1_CLK, | ||
| 56 | MX53_PAD_SD1_DATA0__ESDHC1_DAT0, | ||
| 57 | MX53_PAD_SD1_DATA1__ESDHC1_DAT1, | ||
| 58 | MX53_PAD_SD1_DATA2__ESDHC1_DAT2, | ||
| 59 | MX53_PAD_SD1_DATA3__ESDHC1_DAT3, | ||
| 60 | /* SD2 */ | ||
| 61 | MX53_PAD_SD2_CMD__ESDHC2_CMD, | ||
| 62 | MX53_PAD_SD2_CLK__ESDHC2_CLK, | ||
| 63 | MX53_PAD_SD2_DATA0__ESDHC2_DAT0, | ||
| 64 | MX53_PAD_SD2_DATA1__ESDHC2_DAT1, | ||
| 65 | MX53_PAD_SD2_DATA2__ESDHC2_DAT2, | ||
| 66 | MX53_PAD_SD2_DATA3__ESDHC2_DAT3, | ||
| 67 | /* SD3 */ | ||
| 68 | MX53_PAD_PATA_DATA8__ESDHC3_DAT0, | ||
| 69 | MX53_PAD_PATA_DATA9__ESDHC3_DAT1, | ||
| 70 | MX53_PAD_PATA_DATA10__ESDHC3_DAT2, | ||
| 71 | MX53_PAD_PATA_DATA11__ESDHC3_DAT3, | ||
| 72 | MX53_PAD_PATA_DATA0__ESDHC3_DAT4, | ||
| 73 | MX53_PAD_PATA_DATA1__ESDHC3_DAT5, | ||
| 74 | MX53_PAD_PATA_DATA2__ESDHC3_DAT6, | ||
| 75 | MX53_PAD_PATA_DATA3__ESDHC3_DAT7, | ||
| 76 | MX53_PAD_PATA_IORDY__ESDHC3_CLK, | ||
| 77 | MX53_PAD_PATA_RESET_B__ESDHC3_CMD, | ||
| 78 | }; | ||
| 79 | |||
| 80 | static const struct imxuart_platform_data mx53_smd_uart_data __initconst = { | ||
| 81 | .flags = IMXUART_HAVE_RTSCTS, | ||
| 82 | }; | ||
| 83 | |||
| 84 | static inline void mx53_smd_init_uart(void) | ||
| 85 | { | ||
| 86 | imx53_add_imx_uart(0, NULL); | ||
| 87 | imx53_add_imx_uart(1, NULL); | ||
| 88 | imx53_add_imx_uart(2, &mx53_smd_uart_data); | ||
| 89 | } | ||
| 90 | |||
| 91 | static inline void mx53_smd_fec_reset(void) | ||
| 92 | { | ||
| 93 | int ret; | ||
| 94 | |||
| 95 | /* reset FEC PHY */ | ||
| 96 | ret = gpio_request(SMD_FEC_PHY_RST, "fec-phy-reset"); | ||
| 97 | if (ret) { | ||
| 98 | printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); | ||
| 99 | return; | ||
| 100 | } | ||
| 101 | gpio_direction_output(SMD_FEC_PHY_RST, 0); | ||
| 102 | msleep(1); | ||
| 103 | gpio_set_value(SMD_FEC_PHY_RST, 1); | ||
| 104 | } | ||
| 105 | |||
| 106 | static const struct fec_platform_data mx53_smd_fec_data __initconst = { | ||
| 107 | .phy = PHY_INTERFACE_MODE_RMII, | ||
| 108 | }; | ||
| 109 | |||
| 110 | static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = { | ||
| 111 | .bitrate = 100000, | ||
| 112 | }; | ||
| 113 | |||
| 114 | static inline void mx53_smd_ahci_pwr_on(void) | ||
| 115 | { | ||
| 116 | int ret; | ||
| 117 | |||
| 118 | /* Enable SATA PWR */ | ||
| 119 | ret = gpio_request_one(MX53_SMD_SATA_PWR_EN, | ||
| 120 | GPIOF_DIR_OUT | GPIOF_INIT_HIGH, "ahci-sata-pwr"); | ||
| 121 | if (ret) { | ||
| 122 | pr_err("failed to enable SATA_PWR_EN: %d\n", ret); | ||
| 123 | return; | ||
| 124 | } | ||
| 125 | } | ||
| 126 | |||
| 127 | void __init imx53_smd_common_init(void) | ||
| 128 | { | ||
| 129 | mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads, | ||
| 130 | ARRAY_SIZE(mx53_smd_pads)); | ||
| 131 | } | ||
| 132 | |||
| 133 | static void __init mx53_smd_board_init(void) | ||
| 134 | { | ||
| 135 | imx53_soc_init(); | ||
| 136 | imx53_smd_common_init(); | ||
| 137 | |||
| 138 | mx53_smd_init_uart(); | ||
| 139 | mx53_smd_fec_reset(); | ||
| 140 | imx53_add_fec(&mx53_smd_fec_data); | ||
| 141 | imx53_add_imx2_wdt(0); | ||
| 142 | imx53_add_imx_i2c(0, &mx53_smd_i2c_data); | ||
| 143 | imx53_add_sdhci_esdhc_imx(0, NULL); | ||
| 144 | imx53_add_sdhci_esdhc_imx(1, NULL); | ||
| 145 | imx53_add_sdhci_esdhc_imx(2, NULL); | ||
| 146 | mx53_smd_ahci_pwr_on(); | ||
| 147 | imx53_add_ahci_imx(); | ||
| 148 | } | ||
| 149 | |||
| 150 | static void __init mx53_smd_timer_init(void) | ||
| 151 | { | ||
| 152 | mx53_clocks_init(32768, 24000000, 22579200, 0); | ||
| 153 | } | ||
| 154 | |||
| 155 | static struct sys_timer mx53_smd_timer = { | ||
| 156 | .init = mx53_smd_timer_init, | ||
| 157 | }; | ||
| 158 | |||
| 159 | MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board") | ||
| 160 | .map_io = mx53_map_io, | ||
| 161 | .init_early = imx53_init_early, | ||
| 162 | .init_irq = mx53_init_irq, | ||
| 163 | .handle_irq = imx53_handle_irq, | ||
| 164 | .timer = &mx53_smd_timer, | ||
| 165 | .init_machine = mx53_smd_board_init, | ||
| 166 | .init_late = imx53_init_late, | ||
| 167 | .restart = mxc_restart, | ||
| 168 | MACHINE_END | ||
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c index 52d8f534be10..acb0aadb4255 100644 --- a/arch/arm/mach-imx/mm-imx5.c +++ b/arch/arm/mach-imx/mm-imx5.c | |||
| @@ -128,25 +128,6 @@ static struct sdma_platform_data imx51_sdma_pdata __initdata = { | |||
| 128 | .script_addrs = &imx51_sdma_script, | 128 | .script_addrs = &imx51_sdma_script, |
| 129 | }; | 129 | }; |
| 130 | 130 | ||
| 131 | static struct sdma_script_start_addrs imx53_sdma_script __initdata = { | ||
| 132 | .ap_2_ap_addr = 642, | ||
| 133 | .app_2_mcu_addr = 683, | ||
| 134 | .mcu_2_app_addr = 747, | ||
| 135 | .uart_2_mcu_addr = 817, | ||
| 136 | .shp_2_mcu_addr = 891, | ||
| 137 | .mcu_2_shp_addr = 960, | ||
| 138 | .uartsh_2_mcu_addr = 1032, | ||
| 139 | .spdif_2_mcu_addr = 1100, | ||
| 140 | .mcu_2_spdif_addr = 1134, | ||
| 141 | .firi_2_mcu_addr = 1193, | ||
| 142 | .mcu_2_firi_addr = 1290, | ||
| 143 | }; | ||
| 144 | |||
| 145 | static struct sdma_platform_data imx53_sdma_pdata __initdata = { | ||
| 146 | .fw_name = "sdma-imx53.bin", | ||
| 147 | .script_addrs = &imx53_sdma_script, | ||
| 148 | }; | ||
| 149 | |||
| 150 | static const struct resource imx50_audmux_res[] __initconst = { | 131 | static const struct resource imx50_audmux_res[] __initconst = { |
| 151 | DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K), | 132 | DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K), |
| 152 | }; | 133 | }; |
| @@ -155,10 +136,6 @@ static const struct resource imx51_audmux_res[] __initconst = { | |||
| 155 | DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K), | 136 | DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K), |
| 156 | }; | 137 | }; |
| 157 | 138 | ||
| 158 | static const struct resource imx53_audmux_res[] __initconst = { | ||
| 159 | DEFINE_RES_MEM(MX53_AUDMUX_BASE_ADDR, SZ_16K), | ||
| 160 | }; | ||
| 161 | |||
| 162 | void __init imx50_soc_init(void) | 139 | void __init imx50_soc_init(void) |
| 163 | { | 140 | { |
| 164 | /* i.mx50 has the i.mx35 type gpio */ | 141 | /* i.mx50 has the i.mx35 type gpio */ |
| @@ -196,30 +173,6 @@ void __init imx51_soc_init(void) | |||
| 196 | ARRAY_SIZE(imx51_audmux_res)); | 173 | ARRAY_SIZE(imx51_audmux_res)); |
| 197 | } | 174 | } |
| 198 | 175 | ||
| 199 | void __init imx53_soc_init(void) | ||
| 200 | { | ||
| 201 | /* i.mx53 has the i.mx35 type gpio */ | ||
| 202 | mxc_register_gpio("imx35-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH); | ||
| 203 | mxc_register_gpio("imx35-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH); | ||
| 204 | mxc_register_gpio("imx35-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH); | ||
| 205 | mxc_register_gpio("imx35-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH); | ||
| 206 | mxc_register_gpio("imx35-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH); | ||
| 207 | mxc_register_gpio("imx35-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH); | ||
| 208 | mxc_register_gpio("imx35-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH); | ||
| 209 | |||
| 210 | pinctrl_provide_dummies(); | ||
| 211 | /* i.mx53 has the i.mx35 type sdma */ | ||
| 212 | imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata); | ||
| 213 | |||
| 214 | /* Setup AIPS registers */ | ||
| 215 | imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR)); | ||
| 216 | imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR)); | ||
| 217 | |||
| 218 | /* i.mx53 has the i.mx31 type audmux */ | ||
| 219 | platform_device_register_simple("imx31-audmux", 0, imx53_audmux_res, | ||
| 220 | ARRAY_SIZE(imx53_audmux_res)); | ||
| 221 | } | ||
| 222 | |||
| 223 | void __init imx51_init_late(void) | 176 | void __init imx51_init_late(void) |
| 224 | { | 177 | { |
| 225 | mx51_neon_fixup(); | 178 | mx51_neon_fixup(); |
diff --git a/arch/arm/mach-imx/mx51_efika.c b/arch/arm/mach-imx/mx51_efika.c deleted file mode 100644 index ee870c49bc63..000000000000 --- a/arch/arm/mach-imx/mx51_efika.c +++ /dev/null | |||
| @@ -1,633 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * based on code from the following | ||
| 3 | * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 4 | * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved. | ||
| 5 | * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved. | ||
| 6 | * | ||
| 7 | * The code contained herein is licensed under the GNU General Public | ||
| 8 | * License. You may obtain a copy of the GNU General Public License | ||
| 9 | * Version 2 or later at the following locations: | ||
| 10 | * | ||
| 11 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 12 | * http://www.gnu.org/copyleft/gpl.html | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/init.h> | ||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <linux/i2c.h> | ||
| 18 | #include <linux/gpio.h> | ||
| 19 | #include <linux/leds.h> | ||
| 20 | #include <linux/input.h> | ||
| 21 | #include <linux/delay.h> | ||
| 22 | #include <linux/io.h> | ||
| 23 | #include <linux/spi/flash.h> | ||
| 24 | #include <linux/spi/spi.h> | ||
| 25 | #include <linux/mfd/mc13892.h> | ||
| 26 | #include <linux/regulator/machine.h> | ||
| 27 | #include <linux/regulator/consumer.h> | ||
| 28 | |||
| 29 | #include <mach/common.h> | ||
| 30 | #include <mach/hardware.h> | ||
| 31 | #include <mach/iomux-mx51.h> | ||
| 32 | |||
| 33 | #include <linux/usb/otg.h> | ||
| 34 | #include <linux/usb/ulpi.h> | ||
| 35 | #include <mach/ulpi.h> | ||
| 36 | |||
| 37 | #include <asm/setup.h> | ||
| 38 | #include <asm/mach-types.h> | ||
| 39 | #include <asm/mach/arch.h> | ||
| 40 | #include <asm/mach/time.h> | ||
| 41 | |||
| 42 | #include "devices-imx51.h" | ||
| 43 | #include "efika.h" | ||
| 44 | #include "cpu_op-mx51.h" | ||
| 45 | |||
| 46 | #define MX51_USB_CTRL_1_OFFSET 0x10 | ||
| 47 | #define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) | ||
| 48 | #define MX51_USB_PLL_DIV_19_2_MHZ 0x01 | ||
| 49 | |||
| 50 | #define EFIKAMX_USB_HUB_RESET IMX_GPIO_NR(1, 5) | ||
| 51 | #define EFIKAMX_USBH1_STP IMX_GPIO_NR(1, 27) | ||
| 52 | |||
| 53 | #define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24) | ||
| 54 | #define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25) | ||
| 55 | |||
| 56 | #define EFIKAMX_PMIC IMX_GPIO_NR(1, 6) | ||
| 57 | |||
| 58 | static iomux_v3_cfg_t mx51efika_pads[] = { | ||
| 59 | /* UART1 */ | ||
| 60 | MX51_PAD_UART1_RXD__UART1_RXD, | ||
| 61 | MX51_PAD_UART1_TXD__UART1_TXD, | ||
| 62 | MX51_PAD_UART1_RTS__UART1_RTS, | ||
| 63 | MX51_PAD_UART1_CTS__UART1_CTS, | ||
| 64 | |||
| 65 | /* SD 1 */ | ||
| 66 | MX51_PAD_SD1_CMD__SD1_CMD, | ||
| 67 | MX51_PAD_SD1_CLK__SD1_CLK, | ||
| 68 | MX51_PAD_SD1_DATA0__SD1_DATA0, | ||
| 69 | MX51_PAD_SD1_DATA1__SD1_DATA1, | ||
| 70 | MX51_PAD_SD1_DATA2__SD1_DATA2, | ||
| 71 | MX51_PAD_SD1_DATA3__SD1_DATA3, | ||
| 72 | |||
| 73 | /* SD 2 */ | ||
| 74 | MX51_PAD_SD2_CMD__SD2_CMD, | ||
| 75 | MX51_PAD_SD2_CLK__SD2_CLK, | ||
| 76 | MX51_PAD_SD2_DATA0__SD2_DATA0, | ||
| 77 | MX51_PAD_SD2_DATA1__SD2_DATA1, | ||
| 78 | MX51_PAD_SD2_DATA2__SD2_DATA2, | ||
| 79 | MX51_PAD_SD2_DATA3__SD2_DATA3, | ||
| 80 | |||
| 81 | /* SD/MMC WP/CD */ | ||
| 82 | MX51_PAD_GPIO1_0__SD1_CD, | ||
| 83 | MX51_PAD_GPIO1_1__SD1_WP, | ||
| 84 | MX51_PAD_GPIO1_7__SD2_WP, | ||
| 85 | MX51_PAD_GPIO1_8__SD2_CD, | ||
| 86 | |||
| 87 | /* spi */ | ||
| 88 | MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, | ||
| 89 | MX51_PAD_CSPI1_MISO__ECSPI1_MISO, | ||
| 90 | MX51_PAD_CSPI1_SS0__GPIO4_24, | ||
| 91 | MX51_PAD_CSPI1_SS1__GPIO4_25, | ||
| 92 | MX51_PAD_CSPI1_RDY__ECSPI1_RDY, | ||
| 93 | MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, | ||
| 94 | MX51_PAD_GPIO1_6__GPIO1_6, | ||
| 95 | |||
| 96 | /* USB HOST1 */ | ||
| 97 | MX51_PAD_USBH1_CLK__USBH1_CLK, | ||
| 98 | MX51_PAD_USBH1_DIR__USBH1_DIR, | ||
| 99 | MX51_PAD_USBH1_NXT__USBH1_NXT, | ||
| 100 | MX51_PAD_USBH1_DATA0__USBH1_DATA0, | ||
| 101 | MX51_PAD_USBH1_DATA1__USBH1_DATA1, | ||
| 102 | MX51_PAD_USBH1_DATA2__USBH1_DATA2, | ||
| 103 | MX51_PAD_USBH1_DATA3__USBH1_DATA3, | ||
| 104 | MX51_PAD_USBH1_DATA4__USBH1_DATA4, | ||
| 105 | MX51_PAD_USBH1_DATA5__USBH1_DATA5, | ||
| 106 | MX51_PAD_USBH1_DATA6__USBH1_DATA6, | ||
| 107 | MX51_PAD_USBH1_DATA7__USBH1_DATA7, | ||
| 108 | |||
| 109 | /* USB HUB RESET */ | ||
| 110 | MX51_PAD_GPIO1_5__GPIO1_5, | ||
| 111 | |||
| 112 | /* WLAN */ | ||
| 113 | MX51_PAD_EIM_A22__GPIO2_16, | ||
| 114 | MX51_PAD_EIM_A16__GPIO2_10, | ||
| 115 | |||
| 116 | /* USB PHY RESET */ | ||
| 117 | MX51_PAD_EIM_D27__GPIO2_9, | ||
| 118 | }; | ||
| 119 | |||
| 120 | /* Serial ports */ | ||
| 121 | static const struct imxuart_platform_data uart_pdata = { | ||
| 122 | .flags = IMXUART_HAVE_RTSCTS, | ||
| 123 | }; | ||
| 124 | |||
| 125 | /* This function is board specific as the bit mask for the plldiv will also | ||
| 126 | * be different for other Freescale SoCs, thus a common bitmask is not | ||
| 127 | * possible and cannot get place in /plat-mxc/ehci.c. | ||
| 128 | */ | ||
| 129 | static int initialize_otg_port(struct platform_device *pdev) | ||
| 130 | { | ||
| 131 | u32 v; | ||
| 132 | void __iomem *usb_base; | ||
| 133 | void __iomem *usbother_base; | ||
| 134 | usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); | ||
| 135 | if (!usb_base) | ||
| 136 | return -ENOMEM; | ||
| 137 | usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET); | ||
| 138 | |||
| 139 | /* Set the PHY clock to 19.2MHz */ | ||
| 140 | v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); | ||
| 141 | v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK; | ||
| 142 | v |= MX51_USB_PLL_DIV_19_2_MHZ; | ||
| 143 | __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); | ||
| 144 | iounmap(usb_base); | ||
| 145 | |||
| 146 | mdelay(10); | ||
| 147 | |||
| 148 | return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY); | ||
| 149 | } | ||
| 150 | |||
| 151 | static const struct mxc_usbh_platform_data dr_utmi_config __initconst = { | ||
| 152 | .init = initialize_otg_port, | ||
| 153 | .portsc = MXC_EHCI_UTMI_16BIT, | ||
| 154 | }; | ||
| 155 | |||
| 156 | static int initialize_usbh1_port(struct platform_device *pdev) | ||
| 157 | { | ||
| 158 | iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP; | ||
| 159 | iomux_v3_cfg_t usbh1gpio = MX51_PAD_USBH1_STP__GPIO1_27; | ||
| 160 | u32 v; | ||
| 161 | void __iomem *usb_base; | ||
| 162 | void __iomem *socregs_base; | ||
| 163 | |||
| 164 | mxc_iomux_v3_setup_pad(usbh1gpio); | ||
| 165 | gpio_request(EFIKAMX_USBH1_STP, "usbh1_stp"); | ||
| 166 | gpio_direction_output(EFIKAMX_USBH1_STP, 0); | ||
| 167 | msleep(1); | ||
| 168 | gpio_set_value(EFIKAMX_USBH1_STP, 1); | ||
| 169 | msleep(1); | ||
| 170 | |||
| 171 | usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); | ||
| 172 | socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET); | ||
| 173 | |||
| 174 | /* The clock for the USBH1 ULPI port will come externally */ | ||
| 175 | /* from the PHY. */ | ||
| 176 | v = __raw_readl(socregs_base + MX51_USB_CTRL_1_OFFSET); | ||
| 177 | __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, | ||
| 178 | socregs_base + MX51_USB_CTRL_1_OFFSET); | ||
| 179 | |||
| 180 | iounmap(usb_base); | ||
| 181 | |||
| 182 | gpio_free(EFIKAMX_USBH1_STP); | ||
| 183 | mxc_iomux_v3_setup_pad(usbh1stp); | ||
| 184 | |||
| 185 | mdelay(10); | ||
| 186 | |||
| 187 | return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD); | ||
| 188 | } | ||
| 189 | |||
| 190 | static struct mxc_usbh_platform_data usbh1_config __initdata = { | ||
| 191 | .init = initialize_usbh1_port, | ||
| 192 | .portsc = MXC_EHCI_MODE_ULPI, | ||
| 193 | }; | ||
| 194 | |||
| 195 | static void mx51_efika_hubreset(void) | ||
| 196 | { | ||
| 197 | gpio_request(EFIKAMX_USB_HUB_RESET, "usb_hub_rst"); | ||
| 198 | gpio_direction_output(EFIKAMX_USB_HUB_RESET, 1); | ||
| 199 | msleep(1); | ||
| 200 | gpio_set_value(EFIKAMX_USB_HUB_RESET, 0); | ||
| 201 | msleep(1); | ||
| 202 | gpio_set_value(EFIKAMX_USB_HUB_RESET, 1); | ||
| 203 | } | ||
| 204 | |||
| 205 | static void __init mx51_efika_usb(void) | ||
| 206 | { | ||
| 207 | mx51_efika_hubreset(); | ||
| 208 | |||
| 209 | /* pulling it low, means no USB at all... */ | ||
| 210 | gpio_request(EFIKA_USB_PHY_RESET, "usb_phy_reset"); | ||
| 211 | gpio_direction_output(EFIKA_USB_PHY_RESET, 0); | ||
| 212 | msleep(1); | ||
| 213 | gpio_set_value(EFIKA_USB_PHY_RESET, 1); | ||
| 214 | |||
| 215 | usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | | ||
| 216 | ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND); | ||
| 217 | |||
| 218 | imx51_add_mxc_ehci_otg(&dr_utmi_config); | ||
| 219 | if (usbh1_config.otg) | ||
| 220 | imx51_add_mxc_ehci_hs(1, &usbh1_config); | ||
| 221 | } | ||
| 222 | |||
| 223 | static struct mtd_partition mx51_efika_spi_nor_partitions[] = { | ||
| 224 | { | ||
| 225 | .name = "u-boot", | ||
| 226 | .offset = 0, | ||
| 227 | .size = SZ_256K, | ||
| 228 | }, | ||
| 229 | { | ||
| 230 | .name = "config", | ||
| 231 | .offset = MTDPART_OFS_APPEND, | ||
| 232 | .size = SZ_64K, | ||
| 233 | }, | ||
| 234 | }; | ||
| 235 | |||
| 236 | static struct flash_platform_data mx51_efika_spi_flash_data = { | ||
| 237 | .name = "spi_flash", | ||
| 238 | .parts = mx51_efika_spi_nor_partitions, | ||
| 239 | .nr_parts = ARRAY_SIZE(mx51_efika_spi_nor_partitions), | ||
| 240 | .type = "sst25vf032b", | ||
| 241 | }; | ||
| 242 | |||
| 243 | static struct regulator_consumer_supply sw1_consumers[] = { | ||
| 244 | { | ||
| 245 | .supply = "cpu_vcc", | ||
| 246 | } | ||
| 247 | }; | ||
| 248 | |||
| 249 | static struct regulator_consumer_supply vdig_consumers[] = { | ||
| 250 | /* sgtl5000 */ | ||
| 251 | REGULATOR_SUPPLY("VDDA", "1-000a"), | ||
| 252 | REGULATOR_SUPPLY("VDDD", "1-000a"), | ||
| 253 | }; | ||
| 254 | |||
| 255 | static struct regulator_consumer_supply vvideo_consumers[] = { | ||
| 256 | /* sgtl5000 */ | ||
| 257 | REGULATOR_SUPPLY("VDDIO", "1-000a"), | ||
| 258 | }; | ||
| 259 | |||
| 260 | static struct regulator_consumer_supply vsd_consumers[] = { | ||
| 261 | REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.0"), | ||
| 262 | REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.1"), | ||
| 263 | }; | ||
| 264 | |||
| 265 | static struct regulator_consumer_supply pwgt1_consumer[] = { | ||
| 266 | { | ||
| 267 | .supply = "pwgt1", | ||
| 268 | } | ||
| 269 | }; | ||
| 270 | |||
| 271 | static struct regulator_consumer_supply pwgt2_consumer[] = { | ||
| 272 | { | ||
| 273 | .supply = "pwgt2", | ||
| 274 | } | ||
| 275 | }; | ||
| 276 | |||
| 277 | static struct regulator_consumer_supply coincell_consumer[] = { | ||
| 278 | { | ||
| 279 | .supply = "coincell", | ||
| 280 | } | ||
| 281 | }; | ||
| 282 | |||
| 283 | static struct regulator_init_data sw1_init = { | ||
| 284 | .constraints = { | ||
| 285 | .name = "SW1", | ||
| 286 | .min_uV = 600000, | ||
| 287 | .max_uV = 1375000, | ||
| 288 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, | ||
| 289 | .valid_modes_mask = 0, | ||
| 290 | .always_on = 1, | ||
| 291 | .boot_on = 1, | ||
| 292 | .state_mem = { | ||
| 293 | .uV = 850000, | ||
| 294 | .mode = REGULATOR_MODE_NORMAL, | ||
| 295 | .enabled = 1, | ||
| 296 | }, | ||
| 297 | }, | ||
| 298 | .num_consumer_supplies = ARRAY_SIZE(sw1_consumers), | ||
| 299 | .consumer_supplies = sw1_consumers, | ||
| 300 | }; | ||
| 301 | |||
| 302 | static struct regulator_init_data sw2_init = { | ||
| 303 | .constraints = { | ||
| 304 | .name = "SW2", | ||
| 305 | .min_uV = 900000, | ||
| 306 | .max_uV = 1850000, | ||
| 307 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, | ||
| 308 | .always_on = 1, | ||
| 309 | .boot_on = 1, | ||
| 310 | .state_mem = { | ||
| 311 | .uV = 950000, | ||
| 312 | .mode = REGULATOR_MODE_NORMAL, | ||
| 313 | .enabled = 1, | ||
| 314 | }, | ||
| 315 | } | ||
| 316 | }; | ||
| 317 | |||
| 318 | static struct regulator_init_data sw3_init = { | ||
| 319 | .constraints = { | ||
| 320 | .name = "SW3", | ||
| 321 | .min_uV = 1100000, | ||
| 322 | .max_uV = 1850000, | ||
| 323 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, | ||
| 324 | .always_on = 1, | ||
| 325 | .boot_on = 1, | ||
| 326 | } | ||
| 327 | }; | ||
| 328 | |||
| 329 | static struct regulator_init_data sw4_init = { | ||
| 330 | .constraints = { | ||
| 331 | .name = "SW4", | ||
| 332 | .min_uV = 1100000, | ||
| 333 | .max_uV = 1850000, | ||
| 334 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, | ||
| 335 | .always_on = 1, | ||
| 336 | .boot_on = 1, | ||
| 337 | } | ||
| 338 | }; | ||
| 339 | |||
| 340 | static struct regulator_init_data viohi_init = { | ||
| 341 | .constraints = { | ||
| 342 | .name = "VIOHI", | ||
| 343 | .boot_on = 1, | ||
| 344 | .always_on = 1, | ||
| 345 | } | ||
| 346 | }; | ||
| 347 | |||
| 348 | static struct regulator_init_data vusb_init = { | ||
| 349 | .constraints = { | ||
| 350 | .name = "VUSB", | ||
| 351 | .boot_on = 1, | ||
| 352 | .always_on = 1, | ||
| 353 | } | ||
| 354 | }; | ||
| 355 | |||
| 356 | static struct regulator_init_data swbst_init = { | ||
| 357 | .constraints = { | ||
| 358 | .name = "SWBST", | ||
| 359 | } | ||
| 360 | }; | ||
| 361 | |||
| 362 | static struct regulator_init_data vdig_init = { | ||
| 363 | .constraints = { | ||
| 364 | .name = "VDIG", | ||
| 365 | .min_uV = 1050000, | ||
| 366 | .max_uV = 1800000, | ||
| 367 | .valid_ops_mask = | ||
| 368 | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, | ||
| 369 | .boot_on = 1, | ||
| 370 | .always_on = 1, | ||
| 371 | }, | ||
| 372 | .num_consumer_supplies = ARRAY_SIZE(vdig_consumers), | ||
| 373 | .consumer_supplies = vdig_consumers, | ||
| 374 | }; | ||
| 375 | |||
| 376 | static struct regulator_init_data vpll_init = { | ||
| 377 | .constraints = { | ||
| 378 | .name = "VPLL", | ||
| 379 | .min_uV = 1050000, | ||
| 380 | .max_uV = 1800000, | ||
| 381 | .valid_ops_mask = | ||
| 382 | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, | ||
| 383 | .boot_on = 1, | ||
| 384 | .always_on = 1, | ||
| 385 | } | ||
| 386 | }; | ||
| 387 | |||
| 388 | static struct regulator_init_data vusb2_init = { | ||
| 389 | .constraints = { | ||
| 390 | .name = "VUSB2", | ||
| 391 | .min_uV = 2400000, | ||
| 392 | .max_uV = 2775000, | ||
| 393 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, | ||
| 394 | .boot_on = 1, | ||
| 395 | .always_on = 1, | ||
| 396 | } | ||
| 397 | }; | ||
| 398 | |||
| 399 | static struct regulator_init_data vvideo_init = { | ||
| 400 | .constraints = { | ||
| 401 | .name = "VVIDEO", | ||
| 402 | .min_uV = 2775000, | ||
| 403 | .max_uV = 2775000, | ||
| 404 | .valid_ops_mask = | ||
| 405 | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, | ||
| 406 | .boot_on = 1, | ||
| 407 | .apply_uV = 1, | ||
| 408 | }, | ||
| 409 | .num_consumer_supplies = ARRAY_SIZE(vvideo_consumers), | ||
| 410 | .consumer_supplies = vvideo_consumers, | ||
| 411 | }; | ||
| 412 | |||
| 413 | static struct regulator_init_data vaudio_init = { | ||
| 414 | .constraints = { | ||
| 415 | .name = "VAUDIO", | ||
| 416 | .min_uV = 2300000, | ||
| 417 | .max_uV = 3000000, | ||
| 418 | .valid_ops_mask = | ||
| 419 | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, | ||
| 420 | .boot_on = 1, | ||
| 421 | } | ||
| 422 | }; | ||
| 423 | |||
| 424 | static struct regulator_init_data vsd_init = { | ||
| 425 | .constraints = { | ||
| 426 | .name = "VSD", | ||
| 427 | .min_uV = 1800000, | ||
| 428 | .max_uV = 3150000, | ||
| 429 | .valid_ops_mask = | ||
| 430 | REGULATOR_CHANGE_VOLTAGE, | ||
| 431 | .boot_on = 1, | ||
| 432 | }, | ||
| 433 | .num_consumer_supplies = ARRAY_SIZE(vsd_consumers), | ||
| 434 | .consumer_supplies = vsd_consumers, | ||
| 435 | }; | ||
| 436 | |||
| 437 | static struct regulator_init_data vcam_init = { | ||
| 438 | .constraints = { | ||
| 439 | .name = "VCAM", | ||
| 440 | .min_uV = 2500000, | ||
| 441 | .max_uV = 3000000, | ||
| 442 | .valid_ops_mask = | ||
| 443 | REGULATOR_CHANGE_VOLTAGE | | ||
| 444 | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, | ||
| 445 | .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL, | ||
| 446 | .boot_on = 1, | ||
| 447 | } | ||
| 448 | }; | ||
| 449 | |||
| 450 | static struct regulator_init_data vgen1_init = { | ||
| 451 | .constraints = { | ||
| 452 | .name = "VGEN1", | ||
| 453 | .min_uV = 1200000, | ||
| 454 | .max_uV = 3150000, | ||
| 455 | .valid_ops_mask = | ||
| 456 | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, | ||
| 457 | .boot_on = 1, | ||
| 458 | .always_on = 1, | ||
| 459 | } | ||
| 460 | }; | ||
| 461 | |||
| 462 | static struct regulator_init_data vgen2_init = { | ||
| 463 | .constraints = { | ||
| 464 | .name = "VGEN2", | ||
| 465 | .min_uV = 1200000, | ||
| 466 | .max_uV = 3150000, | ||
| 467 | .valid_ops_mask = | ||
| 468 | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, | ||
| 469 | .boot_on = 1, | ||
| 470 | .always_on = 1, | ||
| 471 | } | ||
| 472 | }; | ||
| 473 | |||
| 474 | static struct regulator_init_data vgen3_init = { | ||
| 475 | .constraints = { | ||
| 476 | .name = "VGEN3", | ||
| 477 | .min_uV = 1800000, | ||
| 478 | .max_uV = 2900000, | ||
| 479 | .valid_ops_mask = | ||
| 480 | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, | ||
| 481 | .boot_on = 1, | ||
| 482 | .always_on = 1, | ||
| 483 | } | ||
| 484 | }; | ||
| 485 | |||
| 486 | static struct regulator_init_data gpo1_init = { | ||
| 487 | .constraints = { | ||
| 488 | .name = "GPO1", | ||
| 489 | } | ||
| 490 | }; | ||
| 491 | |||
| 492 | static struct regulator_init_data gpo2_init = { | ||
| 493 | .constraints = { | ||
| 494 | .name = "GPO2", | ||
| 495 | } | ||
| 496 | }; | ||
| 497 | |||
| 498 | static struct regulator_init_data gpo3_init = { | ||
| 499 | .constraints = { | ||
| 500 | .name = "GPO3", | ||
| 501 | } | ||
| 502 | }; | ||
| 503 | |||
| 504 | static struct regulator_init_data gpo4_init = { | ||
| 505 | .constraints = { | ||
| 506 | .name = "GPO4", | ||
| 507 | } | ||
| 508 | }; | ||
| 509 | |||
| 510 | static struct regulator_init_data pwgt1_init = { | ||
| 511 | .constraints = { | ||
| 512 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | ||
| 513 | .boot_on = 1, | ||
| 514 | }, | ||
| 515 | .num_consumer_supplies = ARRAY_SIZE(pwgt1_consumer), | ||
| 516 | .consumer_supplies = pwgt1_consumer, | ||
| 517 | }; | ||
| 518 | |||
| 519 | static struct regulator_init_data pwgt2_init = { | ||
| 520 | .constraints = { | ||
| 521 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | ||
| 522 | .boot_on = 1, | ||
| 523 | }, | ||
| 524 | .num_consumer_supplies = ARRAY_SIZE(pwgt2_consumer), | ||
| 525 | .consumer_supplies = pwgt2_consumer, | ||
| 526 | }; | ||
| 527 | |||
| 528 | static struct regulator_init_data vcoincell_init = { | ||
| 529 | .constraints = { | ||
| 530 | .name = "COINCELL", | ||
| 531 | .min_uV = 3000000, | ||
| 532 | .max_uV = 3000000, | ||
| 533 | .valid_ops_mask = | ||
| 534 | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, | ||
| 535 | }, | ||
| 536 | .num_consumer_supplies = ARRAY_SIZE(coincell_consumer), | ||
| 537 | .consumer_supplies = coincell_consumer, | ||
| 538 | }; | ||
| 539 | |||
| 540 | static struct mc13xxx_regulator_init_data mx51_efika_regulators[] = { | ||
| 541 | { .id = MC13892_SW1, .init_data = &sw1_init }, | ||
| 542 | { .id = MC13892_SW2, .init_data = &sw2_init }, | ||
| 543 | { .id = MC13892_SW3, .init_data = &sw3_init }, | ||
| 544 | { .id = MC13892_SW4, .init_data = &sw4_init }, | ||
| 545 | { .id = MC13892_SWBST, .init_data = &swbst_init }, | ||
| 546 | { .id = MC13892_VIOHI, .init_data = &viohi_init }, | ||
| 547 | { .id = MC13892_VPLL, .init_data = &vpll_init }, | ||
| 548 | { .id = MC13892_VDIG, .init_data = &vdig_init }, | ||
| 549 | { .id = MC13892_VSD, .init_data = &vsd_init }, | ||
| 550 | { .id = MC13892_VUSB2, .init_data = &vusb2_init }, | ||
| 551 | { .id = MC13892_VVIDEO, .init_data = &vvideo_init }, | ||
| 552 | { .id = MC13892_VAUDIO, .init_data = &vaudio_init }, | ||
| 553 | { .id = MC13892_VCAM, .init_data = &vcam_init }, | ||
| 554 | { .id = MC13892_VGEN1, .init_data = &vgen1_init }, | ||
| 555 | { .id = MC13892_VGEN2, .init_data = &vgen2_init }, | ||
| 556 | { .id = MC13892_VGEN3, .init_data = &vgen3_init }, | ||
| 557 | { .id = MC13892_VUSB, .init_data = &vusb_init }, | ||
| 558 | { .id = MC13892_GPO1, .init_data = &gpo1_init }, | ||
| 559 | { .id = MC13892_GPO2, .init_data = &gpo2_init }, | ||
| 560 | { .id = MC13892_GPO3, .init_data = &gpo3_init }, | ||
| 561 | { .id = MC13892_GPO4, .init_data = &gpo4_init }, | ||
| 562 | { .id = MC13892_PWGT1SPI, .init_data = &pwgt1_init }, | ||
| 563 | { .id = MC13892_PWGT2SPI, .init_data = &pwgt2_init }, | ||
| 564 | { .id = MC13892_VCOINCELL, .init_data = &vcoincell_init }, | ||
| 565 | }; | ||
| 566 | |||
| 567 | static struct mc13xxx_platform_data mx51_efika_mc13892_data = { | ||
| 568 | .flags = MC13XXX_USE_RTC, | ||
| 569 | .regulators = { | ||
| 570 | .num_regulators = ARRAY_SIZE(mx51_efika_regulators), | ||
| 571 | .regulators = mx51_efika_regulators, | ||
| 572 | }, | ||
| 573 | }; | ||
| 574 | |||
| 575 | static struct spi_board_info mx51_efika_spi_board_info[] __initdata = { | ||
| 576 | { | ||
| 577 | .modalias = "m25p80", | ||
| 578 | .max_speed_hz = 25000000, | ||
| 579 | .bus_num = 0, | ||
| 580 | .chip_select = 1, | ||
| 581 | .platform_data = &mx51_efika_spi_flash_data, | ||
| 582 | .irq = -1, | ||
| 583 | }, | ||
| 584 | { | ||
| 585 | .modalias = "mc13892", | ||
| 586 | .max_speed_hz = 1000000, | ||
| 587 | .bus_num = 0, | ||
| 588 | .chip_select = 0, | ||
| 589 | .platform_data = &mx51_efika_mc13892_data, | ||
| 590 | /* irq number is run-time assigned */ | ||
| 591 | }, | ||
| 592 | }; | ||
| 593 | |||
| 594 | static int mx51_efika_spi_cs[] = { | ||
| 595 | EFIKAMX_SPI_CS0, | ||
| 596 | EFIKAMX_SPI_CS1, | ||
| 597 | }; | ||
| 598 | |||
| 599 | static const struct spi_imx_master mx51_efika_spi_pdata __initconst = { | ||
| 600 | .chipselect = mx51_efika_spi_cs, | ||
| 601 | .num_chipselect = ARRAY_SIZE(mx51_efika_spi_cs), | ||
| 602 | }; | ||
| 603 | |||
| 604 | void __init efika_board_common_init(void) | ||
| 605 | { | ||
| 606 | mxc_iomux_v3_setup_multiple_pads(mx51efika_pads, | ||
| 607 | ARRAY_SIZE(mx51efika_pads)); | ||
| 608 | imx51_add_imx_uart(0, &uart_pdata); | ||
| 609 | mx51_efika_usb(); | ||
| 610 | |||
| 611 | /* FIXME: comes from original code. check this. */ | ||
| 612 | if (mx51_revision() < IMX_CHIP_REVISION_2_0) | ||
| 613 | sw2_init.constraints.state_mem.uV = 1100000; | ||
| 614 | else if (mx51_revision() == IMX_CHIP_REVISION_2_0) { | ||
| 615 | sw2_init.constraints.state_mem.uV = 1250000; | ||
| 616 | sw1_init.constraints.state_mem.uV = 1000000; | ||
| 617 | } | ||
| 618 | if (machine_is_mx51_efikasb()) | ||
| 619 | vgen1_init.constraints.max_uV = 1200000; | ||
| 620 | |||
| 621 | gpio_request(EFIKAMX_PMIC, "pmic irq"); | ||
| 622 | gpio_direction_input(EFIKAMX_PMIC); | ||
| 623 | mx51_efika_spi_board_info[1].irq = gpio_to_irq(EFIKAMX_PMIC); | ||
| 624 | spi_register_board_info(mx51_efika_spi_board_info, | ||
| 625 | ARRAY_SIZE(mx51_efika_spi_board_info)); | ||
| 626 | imx51_add_ecspi(0, &mx51_efika_spi_pdata); | ||
| 627 | |||
| 628 | imx51_add_pata_imx(); | ||
| 629 | |||
| 630 | #if defined(CONFIG_CPU_FREQ_IMX) | ||
| 631 | get_cpu_op = mx51_get_cpu_op; | ||
| 632 | #endif | ||
| 633 | } | ||
diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot index a5717558ee89..a13299d758e1 100644 --- a/arch/arm/mach-kirkwood/Makefile.boot +++ b/arch/arm/mach-kirkwood/Makefile.boot | |||
| @@ -7,7 +7,8 @@ dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns320.dtb | |||
| 7 | dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns325.dtb | 7 | dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns325.dtb |
| 8 | dtb-$(CONFIG_MACH_ICONNECT_DT) += kirkwood-iconnect.dtb | 8 | dtb-$(CONFIG_MACH_ICONNECT_DT) += kirkwood-iconnect.dtb |
| 9 | dtb-$(CONFIG_MACH_IB62X0_DT) += kirkwood-ib62x0.dtb | 9 | dtb-$(CONFIG_MACH_IB62X0_DT) += kirkwood-ib62x0.dtb |
| 10 | dtb-$(CONFIG_MACH_TS219_DT) += kirkwood-qnap-ts219.dtb | 10 | dtb-$(CONFIG_MACH_TS219_DT) += kirkwood-ts219-6281.dtb |
| 11 | dtb-$(CONFIG_MACH_TS219_DT) += kirkwood-ts219-6282.dtb | ||
| 11 | dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb | 12 | dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb |
| 12 | dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb | 13 | dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb |
| 13 | dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb | 14 | dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb |
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index c4b64adcbfce..3226077735b1 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c | |||
| @@ -301,7 +301,7 @@ void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data) | |||
| 301 | { | 301 | { |
| 302 | orion_ge00_init(eth_data, | 302 | orion_ge00_init(eth_data, |
| 303 | GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM, | 303 | GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM, |
| 304 | IRQ_KIRKWOOD_GE00_ERR); | 304 | IRQ_KIRKWOOD_GE00_ERR, 1600); |
| 305 | /* The interface forgets the MAC address assigned by u-boot if | 305 | /* The interface forgets the MAC address assigned by u-boot if |
| 306 | the clock is turned off, so claim the clk now. */ | 306 | the clock is turned off, so claim the clk now. */ |
| 307 | clk_prepare_enable(ge0); | 307 | clk_prepare_enable(ge0); |
| @@ -315,7 +315,7 @@ void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data) | |||
| 315 | { | 315 | { |
| 316 | orion_ge01_init(eth_data, | 316 | orion_ge01_init(eth_data, |
| 317 | GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM, | 317 | GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM, |
| 318 | IRQ_KIRKWOOD_GE01_ERR); | 318 | IRQ_KIRKWOOD_GE01_ERR, 1600); |
| 319 | clk_prepare_enable(ge1); | 319 | clk_prepare_enable(ge1); |
| 320 | } | 320 | } |
| 321 | 321 | ||
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig index 7fddd01b85b9..d697d07a1bf0 100644 --- a/arch/arm/mach-mmp/Kconfig +++ b/arch/arm/mach-mmp/Kconfig | |||
| @@ -108,18 +108,21 @@ endmenu | |||
| 108 | config CPU_PXA168 | 108 | config CPU_PXA168 |
| 109 | bool | 109 | bool |
| 110 | select CPU_MOHAWK | 110 | select CPU_MOHAWK |
| 111 | select COMMON_CLK | ||
| 111 | help | 112 | help |
| 112 | Select code specific to PXA168 | 113 | Select code specific to PXA168 |
| 113 | 114 | ||
| 114 | config CPU_PXA910 | 115 | config CPU_PXA910 |
| 115 | bool | 116 | bool |
| 116 | select CPU_MOHAWK | 117 | select CPU_MOHAWK |
| 118 | select COMMON_CLK | ||
| 117 | help | 119 | help |
| 118 | Select code specific to PXA910 | 120 | Select code specific to PXA910 |
| 119 | 121 | ||
| 120 | config CPU_MMP2 | 122 | config CPU_MMP2 |
| 121 | bool | 123 | bool |
| 122 | select CPU_PJ4 | 124 | select CPU_PJ4 |
| 125 | select COMMON_CLK | ||
| 123 | help | 126 | help |
| 124 | Select code specific to MMP2. MMP2 is ARMv7 compatible. | 127 | Select code specific to MMP2. MMP2 is ARMv7 compatible. |
| 125 | 128 | ||
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c index c709a24a9d25..c2bb95cf1a82 100644 --- a/arch/arm/mach-mmp/mmp2.c +++ b/arch/arm/mach-mmp/mmp2.c | |||
| @@ -163,7 +163,7 @@ static int __init mmp2_init(void) | |||
| 163 | { | 163 | { |
| 164 | if (cpu_is_mmp2()) { | 164 | if (cpu_is_mmp2()) { |
| 165 | #ifdef CONFIG_CACHE_TAUROS2 | 165 | #ifdef CONFIG_CACHE_TAUROS2 |
| 166 | tauros2_init(); | 166 | tauros2_init(0); |
| 167 | #endif | 167 | #endif |
| 168 | mfp_init_base(MFPR_VIRT_BASE); | 168 | mfp_init_base(MFPR_VIRT_BASE); |
| 169 | mfp_init_addr(mmp2_addr_map); | 169 | mfp_init_addr(mmp2_addr_map); |
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c index 6da52e9f2bdc..51ac8d1898c1 100644 --- a/arch/arm/mach-mmp/pxa910.c +++ b/arch/arm/mach-mmp/pxa910.c | |||
| @@ -14,6 +14,7 @@ | |||
| 14 | #include <linux/io.h> | 14 | #include <linux/io.h> |
| 15 | #include <linux/platform_device.h> | 15 | #include <linux/platform_device.h> |
| 16 | 16 | ||
| 17 | #include <asm/hardware/cache-tauros2.h> | ||
| 17 | #include <asm/mach/time.h> | 18 | #include <asm/mach/time.h> |
| 18 | #include <mach/addr-map.h> | 19 | #include <mach/addr-map.h> |
| 19 | #include <mach/regs-apbc.h> | 20 | #include <mach/regs-apbc.h> |
| @@ -116,6 +117,9 @@ static struct clk_lookup pxa910_clkregs[] = { | |||
| 116 | static int __init pxa910_init(void) | 117 | static int __init pxa910_init(void) |
| 117 | { | 118 | { |
| 118 | if (cpu_is_pxa910()) { | 119 | if (cpu_is_pxa910()) { |
| 120 | #ifdef CONFIG_CACHE_TAUROS2 | ||
| 121 | tauros2_init(0); | ||
| 122 | #endif | ||
| 119 | mfp_init_base(MFPR_VIRT_BASE); | 123 | mfp_init_base(MFPR_VIRT_BASE); |
| 120 | mfp_init_addr(pxa910_mfp_addr_map); | 124 | mfp_init_addr(pxa910_mfp_addr_map); |
| 121 | pxa_init_dma(IRQ_PXA910_DMA_INT0, 32); | 125 | pxa_init_dma(IRQ_PXA910_DMA_INT0, 32); |
diff --git a/arch/arm/mach-mmp/sram.c b/arch/arm/mach-mmp/sram.c index 4304f9519372..7e8a5a2e1ec7 100644 --- a/arch/arm/mach-mmp/sram.c +++ b/arch/arm/mach-mmp/sram.c | |||
| @@ -68,7 +68,7 @@ static int __devinit sram_probe(struct platform_device *pdev) | |||
| 68 | struct resource *res; | 68 | struct resource *res; |
| 69 | int ret = 0; | 69 | int ret = 0; |
| 70 | 70 | ||
| 71 | if (!pdata && !pdata->pool_name) | 71 | if (!pdata || !pdata->pool_name) |
| 72 | return -ENODEV; | 72 | return -ENODEV; |
| 73 | 73 | ||
| 74 | info = kzalloc(sizeof(*info), GFP_KERNEL); | 74 | info = kzalloc(sizeof(*info), GFP_KERNEL); |
diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c index 62b53d710efd..a9bc84180d21 100644 --- a/arch/arm/mach-mv78xx0/addr-map.c +++ b/arch/arm/mach-mv78xx0/addr-map.c | |||
| @@ -37,7 +37,7 @@ | |||
| 37 | #define WIN0_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4)) | 37 | #define WIN0_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4)) |
| 38 | #define WIN8_OFF(n) (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4)) | 38 | #define WIN8_OFF(n) (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4)) |
| 39 | 39 | ||
| 40 | static void __init __iomem *win_cfg_base(int win) | 40 | static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, int win) |
| 41 | { | 41 | { |
| 42 | /* | 42 | /* |
| 43 | * Find the control register base address for this window. | 43 | * Find the control register base address for this window. |
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index b4c53b846c9c..3057f7d4329a 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c | |||
| @@ -213,7 +213,8 @@ void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data) | |||
| 213 | { | 213 | { |
| 214 | orion_ge00_init(eth_data, | 214 | orion_ge00_init(eth_data, |
| 215 | GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM, | 215 | GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM, |
| 216 | IRQ_MV78XX0_GE_ERR); | 216 | IRQ_MV78XX0_GE_ERR, |
| 217 | MV643XX_TX_CSUM_DEFAULT_LIMIT); | ||
| 217 | } | 218 | } |
| 218 | 219 | ||
| 219 | 220 | ||
| @@ -224,7 +225,8 @@ void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data) | |||
| 224 | { | 225 | { |
| 225 | orion_ge01_init(eth_data, | 226 | orion_ge01_init(eth_data, |
| 226 | GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM, | 227 | GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM, |
| 227 | NO_IRQ); | 228 | NO_IRQ, |
| 229 | MV643XX_TX_CSUM_DEFAULT_LIMIT); | ||
| 228 | } | 230 | } |
| 229 | 231 | ||
| 230 | 232 | ||
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index 9a8bbda195b2..ecc431909d6f 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig | |||
| @@ -1,7 +1,5 @@ | |||
| 1 | if ARCH_MXS | 1 | if ARCH_MXS |
| 2 | 2 | ||
| 3 | source "arch/arm/mach-mxs/devices/Kconfig" | ||
| 4 | |||
| 5 | config SOC_IMX23 | 3 | config SOC_IMX23 |
| 6 | bool | 4 | bool |
| 7 | select ARM_AMBA | 5 | select ARM_AMBA |
| @@ -27,91 +25,4 @@ config MACH_MXS_DT | |||
| 27 | Include support for Freescale MXS platforms(i.MX23 and i.MX28) | 25 | Include support for Freescale MXS platforms(i.MX23 and i.MX28) |
| 28 | using the device tree for discovery | 26 | using the device tree for discovery |
| 29 | 27 | ||
| 30 | config MACH_STMP378X_DEVB | ||
| 31 | bool "Support STMP378x_devb Platform" | ||
| 32 | select SOC_IMX23 | ||
| 33 | select MXS_HAVE_AMBA_DUART | ||
| 34 | select MXS_HAVE_PLATFORM_AUART | ||
| 35 | select MXS_HAVE_PLATFORM_MXS_MMC | ||
| 36 | select MXS_HAVE_PLATFORM_RTC_STMP3XXX | ||
| 37 | help | ||
| 38 | Include support for STMP378x-devb platform. This includes specific | ||
| 39 | configurations for the board and its peripherals. | ||
| 40 | |||
| 41 | config MACH_MX23EVK | ||
| 42 | bool "Support MX23EVK Platform" | ||
| 43 | select SOC_IMX23 | ||
| 44 | select MXS_HAVE_AMBA_DUART | ||
| 45 | select MXS_HAVE_PLATFORM_AUART | ||
| 46 | select MXS_HAVE_PLATFORM_MXS_MMC | ||
| 47 | select MXS_HAVE_PLATFORM_MXSFB | ||
| 48 | select MXS_HAVE_PLATFORM_RTC_STMP3XXX | ||
| 49 | help | ||
| 50 | Include support for MX23EVK platform. This includes specific | ||
| 51 | configurations for the board and its peripherals. | ||
| 52 | |||
| 53 | config MACH_MX28EVK | ||
| 54 | bool "Support MX28EVK Platform" | ||
| 55 | select SOC_IMX28 | ||
| 56 | select LEDS_GPIO_REGISTER | ||
| 57 | select MXS_HAVE_AMBA_DUART | ||
| 58 | select MXS_HAVE_PLATFORM_AUART | ||
| 59 | select MXS_HAVE_PLATFORM_FEC | ||
| 60 | select MXS_HAVE_PLATFORM_FLEXCAN | ||
| 61 | select MXS_HAVE_PLATFORM_MXS_MMC | ||
| 62 | select MXS_HAVE_PLATFORM_MXSFB | ||
| 63 | select MXS_HAVE_PLATFORM_MXS_SAIF | ||
| 64 | select MXS_HAVE_PLATFORM_MXS_I2C | ||
| 65 | select MXS_HAVE_PLATFORM_RTC_STMP3XXX | ||
| 66 | help | ||
| 67 | Include support for MX28EVK platform. This includes specific | ||
| 68 | configurations for the board and its peripherals. | ||
| 69 | |||
| 70 | config MODULE_TX28 | ||
| 71 | bool | ||
| 72 | select SOC_IMX28 | ||
| 73 | select LEDS_GPIO_REGISTER | ||
| 74 | select MXS_HAVE_AMBA_DUART | ||
| 75 | select MXS_HAVE_PLATFORM_AUART | ||
| 76 | select MXS_HAVE_PLATFORM_FEC | ||
| 77 | select MXS_HAVE_PLATFORM_MXS_I2C | ||
| 78 | select MXS_HAVE_PLATFORM_MXS_MMC | ||
| 79 | select MXS_HAVE_PLATFORM_MXS_PWM | ||
| 80 | select MXS_HAVE_PLATFORM_RTC_STMP3XXX | ||
| 81 | |||
| 82 | config MODULE_M28 | ||
| 83 | bool | ||
| 84 | select SOC_IMX28 | ||
| 85 | select LEDS_GPIO_REGISTER | ||
| 86 | select MXS_HAVE_AMBA_DUART | ||
| 87 | select MXS_HAVE_PLATFORM_AUART | ||
| 88 | select MXS_HAVE_PLATFORM_FEC | ||
| 89 | select MXS_HAVE_PLATFORM_FLEXCAN | ||
| 90 | select MXS_HAVE_PLATFORM_MXS_I2C | ||
| 91 | select MXS_HAVE_PLATFORM_MXS_MMC | ||
| 92 | select MXS_HAVE_PLATFORM_MXSFB | ||
| 93 | |||
| 94 | config MODULE_APX4 | ||
| 95 | bool | ||
| 96 | select SOC_IMX28 | ||
| 97 | select LEDS_GPIO_REGISTER | ||
| 98 | select MXS_HAVE_AMBA_DUART | ||
| 99 | select MXS_HAVE_PLATFORM_AUART | ||
| 100 | select MXS_HAVE_PLATFORM_FEC | ||
| 101 | select MXS_HAVE_PLATFORM_MXS_I2C | ||
| 102 | select MXS_HAVE_PLATFORM_MXS_MMC | ||
| 103 | select MXS_HAVE_PLATFORM_MXS_SAIF | ||
| 104 | |||
| 105 | config MACH_TX28 | ||
| 106 | bool "Ka-Ro TX28 module" | ||
| 107 | select MODULE_TX28 | ||
| 108 | |||
| 109 | config MACH_M28EVK | ||
| 110 | bool "Support DENX M28EVK Platform" | ||
| 111 | select MODULE_M28 | ||
| 112 | |||
| 113 | config MACH_APX4DEVKIT | ||
| 114 | bool "Support Bluegiga APX4 Development Kit" | ||
| 115 | select MODULE_APX4 | ||
| 116 | |||
| 117 | endif | 28 | endif |
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile index fed3695a1339..3d3c8a973062 100644 --- a/arch/arm/mach-mxs/Makefile +++ b/arch/arm/mach-mxs/Makefile | |||
| @@ -1,15 +1,6 @@ | |||
| 1 | # Common support | 1 | # Common support |
| 2 | obj-y := devices.o icoll.o iomux.o ocotp.o system.o timer.o mm.o | 2 | obj-y := icoll.o ocotp.o system.o timer.o mm.o |
| 3 | 3 | ||
| 4 | obj-$(CONFIG_PM) += pm.o | 4 | obj-$(CONFIG_PM) += pm.o |
| 5 | 5 | ||
| 6 | obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o | 6 | obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o |
| 7 | obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o | ||
| 8 | obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o | ||
| 9 | obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o | ||
| 10 | obj-$(CONFIG_MACH_M28EVK) += mach-m28evk.o | ||
| 11 | obj-$(CONFIG_MACH_APX4DEVKIT) += mach-apx4devkit.o | ||
| 12 | obj-$(CONFIG_MODULE_TX28) += module-tx28.o | ||
| 13 | obj-$(CONFIG_MACH_TX28) += mach-tx28.o | ||
| 14 | |||
| 15 | obj-y += devices/ | ||
diff --git a/arch/arm/mach-mxs/Makefile.boot b/arch/arm/mach-mxs/Makefile.boot index 4582999cf080..8bd23a8558db 100644 --- a/arch/arm/mach-mxs/Makefile.boot +++ b/arch/arm/mach-mxs/Makefile.boot | |||
| @@ -5,6 +5,7 @@ dtb-y += imx23-evk.dtb \ | |||
| 5 | imx23-stmp378x_devb.dtb \ | 5 | imx23-stmp378x_devb.dtb \ |
| 6 | imx28-apx4devkit.dtb \ | 6 | imx28-apx4devkit.dtb \ |
| 7 | imx28-cfa10036.dtb \ | 7 | imx28-cfa10036.dtb \ |
| 8 | imx28-cfa10049.dtb \ | ||
| 8 | imx28-evk.dtb \ | 9 | imx28-evk.dtb \ |
| 9 | imx28-m28evk.dtb \ | 10 | imx28-m28evk.dtb \ |
| 10 | imx28-tx28.dtb \ | 11 | imx28-tx28.dtb \ |
diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h deleted file mode 100644 index 9ee5cede3d42..000000000000 --- a/arch/arm/mach-mxs/devices-mx23.h +++ /dev/null | |||
| @@ -1,43 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it under | ||
| 8 | * the terms of the GNU General Public License version 2 as published by the | ||
| 9 | * Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #include <mach/mx23.h> | ||
| 12 | #include <mach/devices-common.h> | ||
| 13 | #include <linux/mxsfb.h> | ||
| 14 | #include <linux/amba/bus.h> | ||
| 15 | |||
| 16 | static inline int mx23_add_duart(void) | ||
| 17 | { | ||
| 18 | struct amba_device *d; | ||
| 19 | |||
| 20 | d = amba_ahb_device_add(NULL, "duart", MX23_DUART_BASE_ADDR, SZ_8K, | ||
| 21 | MX23_INT_DUART, 0, 0, 0); | ||
| 22 | return IS_ERR(d) ? PTR_ERR(d) : 0; | ||
| 23 | } | ||
| 24 | |||
| 25 | extern const struct mxs_auart_data mx23_auart_data[] __initconst; | ||
| 26 | #define mx23_add_auart(id) mxs_add_auart(&mx23_auart_data[id]) | ||
| 27 | #define mx23_add_auart0() mx23_add_auart(0) | ||
| 28 | #define mx23_add_auart1() mx23_add_auart(1) | ||
| 29 | |||
| 30 | extern const struct mxs_gpmi_nand_data mx23_gpmi_nand_data __initconst; | ||
| 31 | #define mx23_add_gpmi_nand(pdata) \ | ||
| 32 | mxs_add_gpmi_nand(pdata, &mx23_gpmi_nand_data) | ||
| 33 | |||
| 34 | extern const struct mxs_mxs_mmc_data mx23_mxs_mmc_data[] __initconst; | ||
| 35 | #define mx23_add_mxs_mmc(id, pdata) \ | ||
| 36 | mxs_add_mxs_mmc(&mx23_mxs_mmc_data[id], pdata) | ||
| 37 | |||
| 38 | #define mx23_add_mxs_pwm(id) mxs_add_mxs_pwm(MX23_PWM_BASE_ADDR, id) | ||
| 39 | |||
| 40 | struct platform_device *__init mx23_add_mxsfb( | ||
| 41 | const struct mxsfb_platform_data *pdata); | ||
| 42 | |||
| 43 | struct platform_device *__init mx23_add_rtc_stmp3xxx(void); | ||
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h deleted file mode 100644 index fcab431060f4..000000000000 --- a/arch/arm/mach-mxs/devices-mx28.h +++ /dev/null | |||
| @@ -1,63 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it under | ||
| 8 | * the terms of the GNU General Public License version 2 as published by the | ||
| 9 | * Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #include <mach/mx28.h> | ||
| 12 | #include <mach/devices-common.h> | ||
| 13 | #include <linux/mxsfb.h> | ||
| 14 | #include <linux/amba/bus.h> | ||
| 15 | |||
| 16 | static inline int mx28_add_duart(void) | ||
| 17 | { | ||
| 18 | struct amba_device *d; | ||
| 19 | |||
| 20 | d = amba_ahb_device_add(NULL, "duart", MX28_DUART_BASE_ADDR, SZ_8K, | ||
| 21 | MX28_INT_DUART, 0, 0, 0); | ||
| 22 | return IS_ERR(d) ? PTR_ERR(d) : 0; | ||
| 23 | } | ||
| 24 | |||
| 25 | extern const struct mxs_auart_data mx28_auart_data[] __initconst; | ||
| 26 | #define mx28_add_auart(id) mxs_add_auart(&mx28_auart_data[id]) | ||
| 27 | #define mx28_add_auart0() mx28_add_auart(0) | ||
| 28 | #define mx28_add_auart1() mx28_add_auart(1) | ||
| 29 | #define mx28_add_auart2() mx28_add_auart(2) | ||
| 30 | #define mx28_add_auart3() mx28_add_auart(3) | ||
| 31 | #define mx28_add_auart4() mx28_add_auart(4) | ||
| 32 | |||
| 33 | extern const struct mxs_fec_data mx28_fec_data[] __initconst; | ||
| 34 | #define mx28_add_fec(id, pdata) \ | ||
| 35 | mxs_add_fec(&mx28_fec_data[id], pdata) | ||
| 36 | |||
| 37 | extern const struct mxs_flexcan_data mx28_flexcan_data[] __initconst; | ||
| 38 | #define mx28_add_flexcan(id, pdata) \ | ||
| 39 | mxs_add_flexcan(&mx28_flexcan_data[id], pdata) | ||
| 40 | #define mx28_add_flexcan0(pdata) mx28_add_flexcan(0, pdata) | ||
| 41 | #define mx28_add_flexcan1(pdata) mx28_add_flexcan(1, pdata) | ||
| 42 | |||
| 43 | extern const struct mxs_gpmi_nand_data mx28_gpmi_nand_data __initconst; | ||
| 44 | #define mx28_add_gpmi_nand(pdata) \ | ||
| 45 | mxs_add_gpmi_nand(pdata, &mx28_gpmi_nand_data) | ||
| 46 | |||
| 47 | extern const struct mxs_mxs_i2c_data mx28_mxs_i2c_data[] __initconst; | ||
| 48 | #define mx28_add_mxs_i2c(id) mxs_add_mxs_i2c(&mx28_mxs_i2c_data[id]) | ||
| 49 | |||
| 50 | extern const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst; | ||
| 51 | #define mx28_add_mxs_mmc(id, pdata) \ | ||
| 52 | mxs_add_mxs_mmc(&mx28_mxs_mmc_data[id], pdata) | ||
| 53 | |||
| 54 | #define mx28_add_mxs_pwm(id) mxs_add_mxs_pwm(MX28_PWM_BASE_ADDR, id) | ||
| 55 | |||
| 56 | struct platform_device *__init mx28_add_mxsfb( | ||
| 57 | const struct mxsfb_platform_data *pdata); | ||
| 58 | |||
| 59 | extern const struct mxs_saif_data mx28_saif_data[] __initconst; | ||
| 60 | #define mx28_add_saif(id, pdata) \ | ||
| 61 | mxs_add_saif(&mx28_saif_data[id], pdata) | ||
| 62 | |||
| 63 | struct platform_device *__init mx28_add_rtc_stmp3xxx(void); | ||
diff --git a/arch/arm/mach-mxs/devices.c b/arch/arm/mach-mxs/devices.c deleted file mode 100644 index cf50b5a66dda..000000000000 --- a/arch/arm/mach-mxs/devices.c +++ /dev/null | |||
| @@ -1,87 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2008 Sascha Hauer, kernel@pengutronix.de | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation; either version 2 | ||
| 7 | * of the License, or (at your option) any later version. | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | * | ||
| 13 | * You should have received a copy of the GNU General Public License | ||
| 14 | * along with this program; if not, write to the Free Software | ||
| 15 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, | ||
| 16 | * Boston, MA 02110-1301, USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/kernel.h> | ||
| 20 | #include <linux/slab.h> | ||
| 21 | #include <linux/init.h> | ||
| 22 | #include <linux/platform_device.h> | ||
| 23 | #include <linux/amba/bus.h> | ||
| 24 | |||
| 25 | struct platform_device *__init mxs_add_platform_device_dmamask( | ||
| 26 | const char *name, int id, | ||
| 27 | const struct resource *res, unsigned int num_resources, | ||
| 28 | const void *data, size_t size_data, u64 dmamask) | ||
| 29 | { | ||
| 30 | int ret = -ENOMEM; | ||
| 31 | struct platform_device *pdev; | ||
| 32 | |||
| 33 | pdev = platform_device_alloc(name, id); | ||
| 34 | if (!pdev) | ||
| 35 | goto err; | ||
| 36 | |||
| 37 | if (dmamask) { | ||
| 38 | /* | ||
| 39 | * This memory isn't freed when the device is put, | ||
| 40 | * I don't have a nice idea for that though. Conceptually | ||
| 41 | * dma_mask in struct device should not be a pointer. | ||
| 42 | * See http://thread.gmane.org/gmane.linux.kernel.pci/9081 | ||
| 43 | */ | ||
| 44 | pdev->dev.dma_mask = | ||
| 45 | kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL); | ||
| 46 | if (!pdev->dev.dma_mask) | ||
| 47 | /* ret is still -ENOMEM; */ | ||
| 48 | goto err; | ||
| 49 | |||
| 50 | *pdev->dev.dma_mask = dmamask; | ||
| 51 | pdev->dev.coherent_dma_mask = dmamask; | ||
| 52 | } | ||
| 53 | |||
| 54 | if (res) { | ||
| 55 | ret = platform_device_add_resources(pdev, res, num_resources); | ||
| 56 | if (ret) | ||
| 57 | goto err; | ||
| 58 | } | ||
| 59 | |||
| 60 | if (data) { | ||
| 61 | ret = platform_device_add_data(pdev, data, size_data); | ||
| 62 | if (ret) | ||
| 63 | goto err; | ||
| 64 | } | ||
| 65 | |||
| 66 | ret = platform_device_add(pdev); | ||
| 67 | if (ret) { | ||
| 68 | err: | ||
| 69 | if (dmamask) | ||
| 70 | kfree(pdev->dev.dma_mask); | ||
| 71 | platform_device_put(pdev); | ||
| 72 | return ERR_PTR(ret); | ||
| 73 | } | ||
| 74 | |||
| 75 | return pdev; | ||
| 76 | } | ||
| 77 | |||
| 78 | struct device mxs_apbh_bus = { | ||
| 79 | .init_name = "mxs_apbh", | ||
| 80 | .parent = &platform_bus, | ||
| 81 | }; | ||
| 82 | |||
| 83 | static int __init mxs_device_init(void) | ||
| 84 | { | ||
| 85 | return device_register(&mxs_apbh_bus); | ||
| 86 | } | ||
| 87 | core_initcall(mxs_device_init); | ||
diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig deleted file mode 100644 index 19659de1c4e8..000000000000 --- a/arch/arm/mach-mxs/devices/Kconfig +++ /dev/null | |||
| @@ -1,33 +0,0 @@ | |||
| 1 | config MXS_HAVE_AMBA_DUART | ||
| 2 | bool | ||
| 3 | |||
| 4 | config MXS_HAVE_PLATFORM_AUART | ||
| 5 | bool | ||
| 6 | |||
| 7 | config MXS_HAVE_PLATFORM_FEC | ||
| 8 | bool | ||
| 9 | |||
| 10 | config MXS_HAVE_PLATFORM_FLEXCAN | ||
| 11 | select HAVE_CAN_FLEXCAN if CAN | ||
| 12 | bool | ||
| 13 | |||
| 14 | config MXS_HAVE_PLATFORM_GPMI_NAND | ||
| 15 | bool | ||
| 16 | |||
| 17 | config MXS_HAVE_PLATFORM_MXS_I2C | ||
| 18 | bool | ||
| 19 | |||
| 20 | config MXS_HAVE_PLATFORM_MXS_MMC | ||
| 21 | bool | ||
| 22 | |||
| 23 | config MXS_HAVE_PLATFORM_MXS_PWM | ||
| 24 | bool | ||
| 25 | |||
| 26 | config MXS_HAVE_PLATFORM_MXSFB | ||
| 27 | bool | ||
| 28 | |||
| 29 | config MXS_HAVE_PLATFORM_MXS_SAIF | ||
| 30 | bool | ||
| 31 | |||
| 32 | config MXS_HAVE_PLATFORM_RTC_STMP3XXX | ||
| 33 | bool | ||
diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile deleted file mode 100644 index 5f72d9787444..000000000000 --- a/arch/arm/mach-mxs/devices/Makefile +++ /dev/null | |||
| @@ -1,12 +0,0 @@ | |||
| 1 | obj-$(CONFIG_MXS_HAVE_PLATFORM_AUART) += platform-auart.o | ||
| 2 | obj-y += platform-dma.o | ||
| 3 | obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o | ||
| 4 | obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o | ||
| 5 | obj-$(CONFIG_MXS_HAVE_PLATFORM_GPMI_NAND) += platform-gpmi-nand.o | ||
| 6 | obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_I2C) += platform-mxs-i2c.o | ||
| 7 | obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_MMC) += platform-mxs-mmc.o | ||
| 8 | obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o | ||
| 9 | obj-y += platform-gpio-mxs.o | ||
| 10 | obj-$(CONFIG_MXS_HAVE_PLATFORM_MXSFB) += platform-mxsfb.o | ||
| 11 | obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_SAIF) += platform-mxs-saif.o | ||
| 12 | obj-$(CONFIG_MXS_HAVE_PLATFORM_RTC_STMP3XXX) += platform-rtc-stmp3xxx.o | ||
diff --git a/arch/arm/mach-mxs/devices/platform-auart.c b/arch/arm/mach-mxs/devices/platform-auart.c deleted file mode 100644 index 27608f5d2ac8..000000000000 --- a/arch/arm/mach-mxs/devices/platform-auart.c +++ /dev/null | |||
| @@ -1,65 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Sascha Hauer <s.hauer@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include <linux/dma-mapping.h> | ||
| 10 | #include <asm/sizes.h> | ||
| 11 | #include <mach/mx23.h> | ||
| 12 | #include <mach/mx28.h> | ||
| 13 | #include <mach/devices-common.h> | ||
| 14 | |||
| 15 | #define mxs_auart_data_entry_single(soc, _id, hwid) \ | ||
| 16 | { \ | ||
| 17 | .id = _id, \ | ||
| 18 | .iobase = soc ## _AUART ## hwid ## _BASE_ADDR, \ | ||
| 19 | .irq = soc ## _INT_AUART ## hwid, \ | ||
| 20 | } | ||
| 21 | |||
| 22 | #define mxs_auart_data_entry(soc, _id, hwid) \ | ||
| 23 | [_id] = mxs_auart_data_entry_single(soc, _id, hwid) | ||
| 24 | |||
| 25 | #ifdef CONFIG_SOC_IMX23 | ||
| 26 | const struct mxs_auart_data mx23_auart_data[] __initconst = { | ||
| 27 | #define mx23_auart_data_entry(_id, hwid) \ | ||
| 28 | mxs_auart_data_entry(MX23, _id, hwid) | ||
| 29 | mx23_auart_data_entry(0, 1), | ||
| 30 | mx23_auart_data_entry(1, 2), | ||
| 31 | }; | ||
| 32 | #endif | ||
| 33 | |||
| 34 | #ifdef CONFIG_SOC_IMX28 | ||
| 35 | const struct mxs_auart_data mx28_auart_data[] __initconst = { | ||
| 36 | #define mx28_auart_data_entry(_id) \ | ||
| 37 | mxs_auart_data_entry(MX28, _id, _id) | ||
| 38 | mx28_auart_data_entry(0), | ||
| 39 | mx28_auart_data_entry(1), | ||
| 40 | mx28_auart_data_entry(2), | ||
| 41 | mx28_auart_data_entry(3), | ||
| 42 | mx28_auart_data_entry(4), | ||
| 43 | }; | ||
| 44 | #endif | ||
| 45 | |||
| 46 | struct platform_device *__init mxs_add_auart( | ||
| 47 | const struct mxs_auart_data *data) | ||
| 48 | { | ||
| 49 | struct resource res[] = { | ||
| 50 | { | ||
| 51 | .start = data->iobase, | ||
| 52 | .end = data->iobase + SZ_8K - 1, | ||
| 53 | .flags = IORESOURCE_MEM, | ||
| 54 | }, { | ||
| 55 | .start = data->irq, | ||
| 56 | .end = data->irq, | ||
| 57 | .flags = IORESOURCE_IRQ, | ||
| 58 | }, | ||
| 59 | }; | ||
| 60 | |||
| 61 | return mxs_add_platform_device_dmamask("mxs-auart", data->id, | ||
| 62 | res, ARRAY_SIZE(res), NULL, 0, | ||
| 63 | DMA_BIT_MASK(32)); | ||
| 64 | } | ||
| 65 | |||
diff --git a/arch/arm/mach-mxs/devices/platform-dma.c b/arch/arm/mach-mxs/devices/platform-dma.c deleted file mode 100644 index 46824501de00..000000000000 --- a/arch/arm/mach-mxs/devices/platform-dma.c +++ /dev/null | |||
| @@ -1,31 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it under | ||
| 5 | * the terms of the GNU General Public License version 2 as published by the | ||
| 6 | * Free Software Foundation. | ||
| 7 | */ | ||
| 8 | #include <linux/compiler.h> | ||
| 9 | #include <linux/dma-mapping.h> | ||
| 10 | #include <linux/err.h> | ||
| 11 | #include <linux/init.h> | ||
| 12 | |||
| 13 | #include <mach/mx23.h> | ||
| 14 | #include <mach/mx28.h> | ||
| 15 | #include <mach/devices-common.h> | ||
| 16 | |||
| 17 | struct platform_device *__init mxs_add_dma(const char *devid, | ||
| 18 | resource_size_t base) | ||
| 19 | { | ||
| 20 | struct resource res[] = { | ||
| 21 | { | ||
| 22 | .start = base, | ||
| 23 | .end = base + SZ_8K - 1, | ||
| 24 | .flags = IORESOURCE_MEM, | ||
| 25 | } | ||
| 26 | }; | ||
| 27 | |||
| 28 | return mxs_add_platform_device_dmamask(devid, -1, | ||
| 29 | res, ARRAY_SIZE(res), NULL, 0, | ||
| 30 | DMA_BIT_MASK(32)); | ||
| 31 | } | ||
diff --git a/arch/arm/mach-mxs/devices/platform-fec.c b/arch/arm/mach-mxs/devices/platform-fec.c deleted file mode 100644 index ae96a4fd8f14..000000000000 --- a/arch/arm/mach-mxs/devices/platform-fec.c +++ /dev/null | |||
| @@ -1,52 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include <linux/dma-mapping.h> | ||
| 10 | #include <asm/sizes.h> | ||
| 11 | #include <mach/mx28.h> | ||
| 12 | #include <mach/devices-common.h> | ||
| 13 | |||
| 14 | #define mxs_fec_data_entry_single(soc, _id) \ | ||
| 15 | { \ | ||
| 16 | .id = _id, \ | ||
| 17 | .iobase = soc ## _ENET_MAC ## _id ## _BASE_ADDR, \ | ||
| 18 | .irq = soc ## _INT_ENET_MAC ## _id, \ | ||
| 19 | } | ||
| 20 | |||
| 21 | #define mxs_fec_data_entry(soc, _id) \ | ||
| 22 | [_id] = mxs_fec_data_entry_single(soc, _id) | ||
| 23 | |||
| 24 | #ifdef CONFIG_SOC_IMX28 | ||
| 25 | const struct mxs_fec_data mx28_fec_data[] __initconst = { | ||
| 26 | #define mx28_fec_data_entry(_id) \ | ||
| 27 | mxs_fec_data_entry(MX28, _id) | ||
| 28 | mx28_fec_data_entry(0), | ||
| 29 | mx28_fec_data_entry(1), | ||
| 30 | }; | ||
| 31 | #endif | ||
| 32 | |||
| 33 | struct platform_device *__init mxs_add_fec( | ||
| 34 | const struct mxs_fec_data *data, | ||
| 35 | const struct fec_platform_data *pdata) | ||
| 36 | { | ||
| 37 | struct resource res[] = { | ||
| 38 | { | ||
| 39 | .start = data->iobase, | ||
| 40 | .end = data->iobase + SZ_16K - 1, | ||
| 41 | .flags = IORESOURCE_MEM, | ||
| 42 | }, { | ||
| 43 | .start = data->irq, | ||
| 44 | .end = data->irq, | ||
| 45 | .flags = IORESOURCE_IRQ, | ||
| 46 | }, | ||
| 47 | }; | ||
| 48 | |||
| 49 | return mxs_add_platform_device_dmamask("imx28-fec", data->id, | ||
| 50 | res, ARRAY_SIZE(res), pdata, sizeof(*pdata), | ||
| 51 | DMA_BIT_MASK(32)); | ||
| 52 | } | ||
diff --git a/arch/arm/mach-mxs/devices/platform-flexcan.c b/arch/arm/mach-mxs/devices/platform-flexcan.c deleted file mode 100644 index 43a6b4bae6fe..000000000000 --- a/arch/arm/mach-mxs/devices/platform-flexcan.c +++ /dev/null | |||
| @@ -1,51 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010, 2011 Pengutronix, | ||
| 3 | * Marc Kleine-Budde <kernel@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include <asm/sizes.h> | ||
| 10 | #include <mach/mx28.h> | ||
| 11 | #include <mach/devices-common.h> | ||
| 12 | |||
| 13 | #define mxs_flexcan_data_entry_single(soc, _id, _hwid, _size) \ | ||
| 14 | { \ | ||
| 15 | .id = _id, \ | ||
| 16 | .iobase = soc ## _CAN ## _hwid ## _BASE_ADDR, \ | ||
| 17 | .iosize = _size, \ | ||
| 18 | .irq = soc ## _INT_CAN ## _hwid, \ | ||
| 19 | } | ||
| 20 | |||
| 21 | #define mxs_flexcan_data_entry(soc, _id, _hwid, _size) \ | ||
| 22 | [_id] = mxs_flexcan_data_entry_single(soc, _id, _hwid, _size) | ||
| 23 | |||
| 24 | #ifdef CONFIG_SOC_IMX28 | ||
| 25 | const struct mxs_flexcan_data mx28_flexcan_data[] __initconst = { | ||
| 26 | #define mx28_flexcan_data_entry(_id, _hwid) \ | ||
| 27 | mxs_flexcan_data_entry_single(MX28, _id, _hwid, SZ_8K) | ||
| 28 | mx28_flexcan_data_entry(0, 0), | ||
| 29 | mx28_flexcan_data_entry(1, 1), | ||
| 30 | }; | ||
| 31 | #endif /* ifdef CONFIG_SOC_IMX28 */ | ||
| 32 | |||
| 33 | struct platform_device *__init mxs_add_flexcan( | ||
| 34 | const struct mxs_flexcan_data *data, | ||
| 35 | const struct flexcan_platform_data *pdata) | ||
| 36 | { | ||
| 37 | struct resource res[] = { | ||
| 38 | { | ||
| 39 | .start = data->iobase, | ||
| 40 | .end = data->iobase + data->iosize - 1, | ||
| 41 | .flags = IORESOURCE_MEM, | ||
| 42 | }, { | ||
| 43 | .start = data->irq, | ||
| 44 | .end = data->irq, | ||
| 45 | .flags = IORESOURCE_IRQ, | ||
| 46 | }, | ||
| 47 | }; | ||
| 48 | |||
| 49 | return mxs_add_platform_device("flexcan", data->id, | ||
| 50 | res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); | ||
| 51 | } | ||
diff --git a/arch/arm/mach-mxs/devices/platform-gpio-mxs.c b/arch/arm/mach-mxs/devices/platform-gpio-mxs.c deleted file mode 100644 index cd99f19ec637..000000000000 --- a/arch/arm/mach-mxs/devices/platform-gpio-mxs.c +++ /dev/null | |||
| @@ -1,33 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it under | ||
| 5 | * the terms of the GNU General Public License version 2 as published by the | ||
| 6 | * Free Software Foundation. | ||
| 7 | */ | ||
| 8 | #include <linux/compiler.h> | ||
| 9 | #include <linux/err.h> | ||
| 10 | #include <linux/init.h> | ||
| 11 | |||
| 12 | #include <mach/mx23.h> | ||
| 13 | #include <mach/mx28.h> | ||
| 14 | #include <mach/devices-common.h> | ||
| 15 | |||
| 16 | struct platform_device *__init mxs_add_gpio( | ||
| 17 | char *name, int id, resource_size_t iobase, int irq) | ||
| 18 | { | ||
| 19 | struct resource res[] = { | ||
| 20 | { | ||
| 21 | .start = iobase, | ||
| 22 | .end = iobase + SZ_8K - 1, | ||
| 23 | .flags = IORESOURCE_MEM, | ||
| 24 | }, { | ||
| 25 | .start = irq, | ||
| 26 | .end = irq, | ||
| 27 | .flags = IORESOURCE_IRQ, | ||
| 28 | }, | ||
| 29 | }; | ||
| 30 | |||
| 31 | return platform_device_register_resndata(&mxs_apbh_bus, | ||
| 32 | name, id, res, ARRAY_SIZE(res), NULL, 0); | ||
| 33 | } | ||
diff --git a/arch/arm/mach-mxs/devices/platform-gpmi-nand.c b/arch/arm/mach-mxs/devices/platform-gpmi-nand.c deleted file mode 100644 index 3e22df5944a8..000000000000 --- a/arch/arm/mach-mxs/devices/platform-gpmi-nand.c +++ /dev/null | |||
| @@ -1,81 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License along | ||
| 15 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
| 17 | */ | ||
| 18 | #include <asm/sizes.h> | ||
| 19 | #include <mach/mx23.h> | ||
| 20 | #include <mach/mx28.h> | ||
| 21 | #include <mach/devices-common.h> | ||
| 22 | #include <linux/dma-mapping.h> | ||
| 23 | |||
| 24 | #ifdef CONFIG_SOC_IMX23 | ||
| 25 | const struct mxs_gpmi_nand_data mx23_gpmi_nand_data __initconst = { | ||
| 26 | .devid = "imx23-gpmi-nand", | ||
| 27 | .res = { | ||
| 28 | /* GPMI */ | ||
| 29 | DEFINE_RES_MEM_NAMED(MX23_GPMI_BASE_ADDR, SZ_8K, | ||
| 30 | GPMI_NAND_GPMI_REGS_ADDR_RES_NAME), | ||
| 31 | DEFINE_RES_IRQ_NAMED(MX23_INT_GPMI_ATTENTION, | ||
| 32 | GPMI_NAND_GPMI_INTERRUPT_RES_NAME), | ||
| 33 | /* BCH */ | ||
| 34 | DEFINE_RES_MEM_NAMED(MX23_BCH_BASE_ADDR, SZ_8K, | ||
| 35 | GPMI_NAND_BCH_REGS_ADDR_RES_NAME), | ||
| 36 | DEFINE_RES_IRQ_NAMED(MX23_INT_BCH, | ||
| 37 | GPMI_NAND_BCH_INTERRUPT_RES_NAME), | ||
| 38 | /* DMA */ | ||
| 39 | DEFINE_RES_NAMED(MX23_DMA_GPMI0, | ||
| 40 | MX23_DMA_GPMI3 - MX23_DMA_GPMI0 + 1, | ||
| 41 | GPMI_NAND_DMA_CHANNELS_RES_NAME, | ||
| 42 | IORESOURCE_DMA), | ||
| 43 | DEFINE_RES_IRQ_NAMED(MX23_INT_GPMI_DMA, | ||
| 44 | GPMI_NAND_DMA_INTERRUPT_RES_NAME), | ||
| 45 | }, | ||
| 46 | }; | ||
| 47 | #endif | ||
| 48 | |||
| 49 | #ifdef CONFIG_SOC_IMX28 | ||
| 50 | const struct mxs_gpmi_nand_data mx28_gpmi_nand_data __initconst = { | ||
| 51 | .devid = "imx28-gpmi-nand", | ||
| 52 | .res = { | ||
| 53 | /* GPMI */ | ||
| 54 | DEFINE_RES_MEM_NAMED(MX28_GPMI_BASE_ADDR, SZ_8K, | ||
| 55 | GPMI_NAND_GPMI_REGS_ADDR_RES_NAME), | ||
| 56 | DEFINE_RES_IRQ_NAMED(MX28_INT_GPMI, | ||
| 57 | GPMI_NAND_GPMI_INTERRUPT_RES_NAME), | ||
| 58 | /* BCH */ | ||
| 59 | DEFINE_RES_MEM_NAMED(MX28_BCH_BASE_ADDR, SZ_8K, | ||
| 60 | GPMI_NAND_BCH_REGS_ADDR_RES_NAME), | ||
| 61 | DEFINE_RES_IRQ_NAMED(MX28_INT_BCH, | ||
| 62 | GPMI_NAND_BCH_INTERRUPT_RES_NAME), | ||
| 63 | /* DMA */ | ||
| 64 | DEFINE_RES_NAMED(MX28_DMA_GPMI0, | ||
| 65 | MX28_DMA_GPMI7 - MX28_DMA_GPMI0 + 1, | ||
| 66 | GPMI_NAND_DMA_CHANNELS_RES_NAME, | ||
| 67 | IORESOURCE_DMA), | ||
| 68 | DEFINE_RES_IRQ_NAMED(MX28_INT_GPMI_DMA, | ||
| 69 | GPMI_NAND_DMA_INTERRUPT_RES_NAME), | ||
| 70 | }, | ||
| 71 | }; | ||
| 72 | #endif | ||
| 73 | |||
| 74 | struct platform_device *__init | ||
| 75 | mxs_add_gpmi_nand(const struct gpmi_nand_platform_data *pdata, | ||
| 76 | const struct mxs_gpmi_nand_data *data) | ||
| 77 | { | ||
| 78 | return mxs_add_platform_device_dmamask(data->devid, -1, | ||
| 79 | data->res, GPMI_NAND_RES_SIZE, | ||
| 80 | pdata, sizeof(*pdata), DMA_BIT_MASK(32)); | ||
| 81 | } | ||
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-i2c.c b/arch/arm/mach-mxs/devices/platform-mxs-i2c.c deleted file mode 100644 index 79222ec8ede1..000000000000 --- a/arch/arm/mach-mxs/devices/platform-mxs-i2c.c +++ /dev/null | |||
| @@ -1,52 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2011 Pengutronix | ||
| 3 | * Wolfram Sang <w.sang@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include <asm/sizes.h> | ||
| 10 | #include <mach/mx28.h> | ||
| 11 | #include <mach/devices-common.h> | ||
| 12 | |||
| 13 | #define mxs_i2c_data_entry_single(soc, _id) \ | ||
| 14 | { \ | ||
| 15 | .id = _id, \ | ||
| 16 | .iobase = soc ## _I2C ## _id ## _BASE_ADDR, \ | ||
| 17 | .errirq = soc ## _INT_I2C ## _id ## _ERROR, \ | ||
| 18 | .dmairq = soc ## _INT_I2C ## _id ## _DMA, \ | ||
| 19 | } | ||
| 20 | |||
| 21 | #define mxs_i2c_data_entry(soc, _id) \ | ||
| 22 | [_id] = mxs_i2c_data_entry_single(soc, _id) | ||
| 23 | |||
| 24 | #ifdef CONFIG_SOC_IMX28 | ||
| 25 | const struct mxs_mxs_i2c_data mx28_mxs_i2c_data[] __initconst = { | ||
| 26 | mxs_i2c_data_entry(MX28, 0), | ||
| 27 | mxs_i2c_data_entry(MX28, 1), | ||
| 28 | }; | ||
| 29 | #endif | ||
| 30 | |||
| 31 | struct platform_device *__init mxs_add_mxs_i2c( | ||
| 32 | const struct mxs_mxs_i2c_data *data) | ||
| 33 | { | ||
| 34 | struct resource res[] = { | ||
| 35 | { | ||
| 36 | .start = data->iobase, | ||
| 37 | .end = data->iobase + SZ_8K - 1, | ||
| 38 | .flags = IORESOURCE_MEM, | ||
| 39 | }, { | ||
| 40 | .start = data->errirq, | ||
| 41 | .end = data->errirq, | ||
| 42 | .flags = IORESOURCE_IRQ, | ||
| 43 | }, { | ||
| 44 | .start = data->dmairq, | ||
| 45 | .end = data->dmairq, | ||
| 46 | .flags = IORESOURCE_IRQ, | ||
| 47 | }, | ||
| 48 | }; | ||
| 49 | |||
| 50 | return mxs_add_platform_device("mxs-i2c", data->id, res, | ||
| 51 | ARRAY_SIZE(res), NULL, 0); | ||
| 52 | } | ||
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-mmc.c b/arch/arm/mach-mxs/devices/platform-mxs-mmc.c deleted file mode 100644 index b33c9d05c552..000000000000 --- a/arch/arm/mach-mxs/devices/platform-mxs-mmc.c +++ /dev/null | |||
| @@ -1,76 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it under | ||
| 8 | * the terms of the GNU General Public License version 2 as published by the | ||
| 9 | * Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/compiler.h> | ||
| 13 | #include <linux/err.h> | ||
| 14 | #include <linux/init.h> | ||
| 15 | |||
| 16 | #include <mach/mx23.h> | ||
| 17 | #include <mach/mx28.h> | ||
| 18 | #include <mach/devices-common.h> | ||
| 19 | |||
| 20 | #define mxs_mxs_mmc_data_entry_single(soc, _devid, _id, hwid) \ | ||
| 21 | { \ | ||
| 22 | .devid = _devid, \ | ||
| 23 | .id = _id, \ | ||
| 24 | .iobase = soc ## _SSP ## hwid ## _BASE_ADDR, \ | ||
| 25 | .dma = soc ## _DMA_SSP ## hwid, \ | ||
| 26 | .irq_err = soc ## _INT_SSP ## hwid ## _ERROR, \ | ||
| 27 | .irq_dma = soc ## _INT_SSP ## hwid ## _DMA, \ | ||
| 28 | } | ||
| 29 | |||
| 30 | #define mxs_mxs_mmc_data_entry(soc, _devid, _id, hwid) \ | ||
| 31 | [_id] = mxs_mxs_mmc_data_entry_single(soc, _devid, _id, hwid) | ||
| 32 | |||
| 33 | |||
| 34 | #ifdef CONFIG_SOC_IMX23 | ||
| 35 | const struct mxs_mxs_mmc_data mx23_mxs_mmc_data[] __initconst = { | ||
| 36 | mxs_mxs_mmc_data_entry(MX23, "imx23-mmc", 0, 1), | ||
| 37 | mxs_mxs_mmc_data_entry(MX23, "imx23-mmc", 1, 2), | ||
| 38 | }; | ||
| 39 | #endif | ||
| 40 | |||
| 41 | #ifdef CONFIG_SOC_IMX28 | ||
| 42 | const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst = { | ||
| 43 | mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 0, 0), | ||
| 44 | mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 1, 1), | ||
| 45 | mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 2, 2), | ||
| 46 | mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 3, 3), | ||
| 47 | }; | ||
| 48 | #endif | ||
| 49 | |||
| 50 | struct platform_device *__init mxs_add_mxs_mmc( | ||
| 51 | const struct mxs_mxs_mmc_data *data, | ||
| 52 | const struct mxs_mmc_platform_data *pdata) | ||
| 53 | { | ||
| 54 | struct resource res[] = { | ||
| 55 | { | ||
| 56 | .start = data->iobase, | ||
| 57 | .end = data->iobase + SZ_8K - 1, | ||
| 58 | .flags = IORESOURCE_MEM, | ||
| 59 | }, { | ||
| 60 | .start = data->dma, | ||
| 61 | .end = data->dma, | ||
| 62 | .flags = IORESOURCE_DMA, | ||
| 63 | }, { | ||
| 64 | .start = data->irq_err, | ||
| 65 | .end = data->irq_err, | ||
| 66 | .flags = IORESOURCE_IRQ, | ||
| 67 | }, { | ||
| 68 | .start = data->irq_dma, | ||
| 69 | .end = data->irq_dma, | ||
| 70 | .flags = IORESOURCE_IRQ, | ||
| 71 | }, | ||
| 72 | }; | ||
| 73 | |||
| 74 | return mxs_add_platform_device(data->devid, data->id, | ||
| 75 | res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); | ||
| 76 | } | ||
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-pwm.c b/arch/arm/mach-mxs/devices/platform-mxs-pwm.c deleted file mode 100644 index 680f5a902936..000000000000 --- a/arch/arm/mach-mxs/devices/platform-mxs-pwm.c +++ /dev/null | |||
| @@ -1,22 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Sascha Hauer <s.hauer@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include <asm/sizes.h> | ||
| 10 | #include <mach/devices-common.h> | ||
| 11 | |||
| 12 | struct platform_device *__init mxs_add_mxs_pwm(resource_size_t iobase, int id) | ||
| 13 | { | ||
| 14 | struct resource res = { | ||
| 15 | .flags = IORESOURCE_MEM, | ||
| 16 | }; | ||
| 17 | |||
| 18 | res.start = iobase + 0x10 + 0x20 * id; | ||
| 19 | res.end = res.start + 0x1f; | ||
| 20 | |||
| 21 | return mxs_add_platform_device("mxs-pwm", id, &res, 1, NULL, 0); | ||
| 22 | } | ||
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-saif.c b/arch/arm/mach-mxs/devices/platform-mxs-saif.c deleted file mode 100644 index f6e3a60b4201..000000000000 --- a/arch/arm/mach-mxs/devices/platform-mxs-saif.c +++ /dev/null | |||
| @@ -1,61 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it under | ||
| 5 | * the terms of the GNU General Public License version 2 as published by the | ||
| 6 | * Free Software Foundation. | ||
| 7 | */ | ||
| 8 | #include <linux/compiler.h> | ||
| 9 | #include <linux/err.h> | ||
| 10 | #include <linux/init.h> | ||
| 11 | |||
| 12 | #include <mach/mx23.h> | ||
| 13 | #include <mach/mx28.h> | ||
| 14 | #include <mach/devices-common.h> | ||
| 15 | |||
| 16 | #define mxs_saif_data_entry_single(soc, _id) \ | ||
| 17 | { \ | ||
| 18 | .id = _id, \ | ||
| 19 | .iobase = soc ## _SAIF ## _id ## _BASE_ADDR, \ | ||
| 20 | .irq = soc ## _INT_SAIF ## _id, \ | ||
| 21 | .dma = soc ## _DMA_SAIF ## _id, \ | ||
| 22 | .dmairq = soc ## _INT_SAIF ## _id ##_DMA, \ | ||
| 23 | } | ||
| 24 | |||
| 25 | #define mxs_saif_data_entry(soc, _id) \ | ||
| 26 | [_id] = mxs_saif_data_entry_single(soc, _id) | ||
| 27 | |||
| 28 | #ifdef CONFIG_SOC_IMX28 | ||
| 29 | const struct mxs_saif_data mx28_saif_data[] __initconst = { | ||
| 30 | mxs_saif_data_entry(MX28, 0), | ||
| 31 | mxs_saif_data_entry(MX28, 1), | ||
| 32 | }; | ||
| 33 | #endif | ||
| 34 | |||
| 35 | struct platform_device *__init mxs_add_saif(const struct mxs_saif_data *data, | ||
| 36 | const struct mxs_saif_platform_data *pdata) | ||
| 37 | { | ||
| 38 | struct resource res[] = { | ||
| 39 | { | ||
| 40 | .start = data->iobase, | ||
| 41 | .end = data->iobase + SZ_4K - 1, | ||
| 42 | .flags = IORESOURCE_MEM, | ||
| 43 | }, { | ||
| 44 | .start = data->irq, | ||
| 45 | .end = data->irq, | ||
| 46 | .flags = IORESOURCE_IRQ, | ||
| 47 | }, { | ||
| 48 | .start = data->dma, | ||
| 49 | .end = data->dma, | ||
| 50 | .flags = IORESOURCE_DMA, | ||
| 51 | }, { | ||
| 52 | .start = data->dmairq, | ||
| 53 | .end = data->dmairq, | ||
| 54 | .flags = IORESOURCE_IRQ, | ||
| 55 | }, | ||
| 56 | |||
| 57 | }; | ||
| 58 | |||
| 59 | return mxs_add_platform_device("mxs-saif", data->id, res, | ||
| 60 | ARRAY_SIZE(res), pdata, sizeof(*pdata)); | ||
| 61 | } | ||
diff --git a/arch/arm/mach-mxs/devices/platform-mxsfb.c b/arch/arm/mach-mxs/devices/platform-mxsfb.c deleted file mode 100644 index 76b53f73418e..000000000000 --- a/arch/arm/mach-mxs/devices/platform-mxsfb.c +++ /dev/null | |||
| @@ -1,47 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2011 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it under | ||
| 5 | * the terms of the GNU General Public License version 2 as published by the | ||
| 6 | * Free Software Foundation. | ||
| 7 | */ | ||
| 8 | #include <linux/dma-mapping.h> | ||
| 9 | #include <asm/sizes.h> | ||
| 10 | #include <mach/mx23.h> | ||
| 11 | #include <mach/mx28.h> | ||
| 12 | #include <mach/devices-common.h> | ||
| 13 | #include <linux/mxsfb.h> | ||
| 14 | |||
| 15 | #ifdef CONFIG_SOC_IMX23 | ||
| 16 | struct platform_device *__init mx23_add_mxsfb( | ||
| 17 | const struct mxsfb_platform_data *pdata) | ||
| 18 | { | ||
| 19 | struct resource res[] = { | ||
| 20 | { | ||
| 21 | .start = MX23_LCDIF_BASE_ADDR, | ||
| 22 | .end = MX23_LCDIF_BASE_ADDR + SZ_8K - 1, | ||
| 23 | .flags = IORESOURCE_MEM, | ||
| 24 | }, | ||
| 25 | }; | ||
| 26 | |||
| 27 | return mxs_add_platform_device_dmamask("imx23-fb", -1, | ||
| 28 | res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32)); | ||
| 29 | } | ||
| 30 | #endif /* ifdef CONFIG_SOC_IMX23 */ | ||
| 31 | |||
| 32 | #ifdef CONFIG_SOC_IMX28 | ||
| 33 | struct platform_device *__init mx28_add_mxsfb( | ||
| 34 | const struct mxsfb_platform_data *pdata) | ||
| 35 | { | ||
| 36 | struct resource res[] = { | ||
| 37 | { | ||
| 38 | .start = MX28_LCDIF_BASE_ADDR, | ||
| 39 | .end = MX28_LCDIF_BASE_ADDR + SZ_8K - 1, | ||
| 40 | .flags = IORESOURCE_MEM, | ||
| 41 | }, | ||
| 42 | }; | ||
| 43 | |||
| 44 | return mxs_add_platform_device_dmamask("imx28-fb", -1, | ||
| 45 | res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32)); | ||
| 46 | } | ||
| 47 | #endif /* ifdef CONFIG_SOC_IMX28 */ | ||
diff --git a/arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c b/arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c deleted file mode 100644 index 639eaee15553..000000000000 --- a/arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c +++ /dev/null | |||
| @@ -1,51 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2011 Pengutronix, Wolfram Sang <w.sang@pengutronix.de> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it under | ||
| 5 | * the terms of the GNU General Public License version 2 as published by the | ||
| 6 | * Free Software Foundation. | ||
| 7 | */ | ||
| 8 | #include <asm/sizes.h> | ||
| 9 | #include <mach/mx23.h> | ||
| 10 | #include <mach/mx28.h> | ||
| 11 | #include <mach/devices-common.h> | ||
| 12 | |||
| 13 | #ifdef CONFIG_SOC_IMX23 | ||
| 14 | struct platform_device *__init mx23_add_rtc_stmp3xxx(void) | ||
| 15 | { | ||
| 16 | struct resource res[] = { | ||
| 17 | { | ||
| 18 | .start = MX23_RTC_BASE_ADDR, | ||
| 19 | .end = MX23_RTC_BASE_ADDR + SZ_8K - 1, | ||
| 20 | .flags = IORESOURCE_MEM, | ||
| 21 | }, { | ||
| 22 | .start = MX23_INT_RTC_ALARM, | ||
| 23 | .end = MX23_INT_RTC_ALARM, | ||
| 24 | .flags = IORESOURCE_IRQ, | ||
| 25 | }, | ||
| 26 | }; | ||
| 27 | |||
| 28 | return mxs_add_platform_device("stmp3xxx-rtc", 0, res, ARRAY_SIZE(res), | ||
| 29 | NULL, 0); | ||
| 30 | } | ||
| 31 | #endif /* CONFIG_SOC_IMX23 */ | ||
| 32 | |||
| 33 | #ifdef CONFIG_SOC_IMX28 | ||
| 34 | struct platform_device *__init mx28_add_rtc_stmp3xxx(void) | ||
| 35 | { | ||
| 36 | struct resource res[] = { | ||
| 37 | { | ||
| 38 | .start = MX28_RTC_BASE_ADDR, | ||
| 39 | .end = MX28_RTC_BASE_ADDR + SZ_8K - 1, | ||
| 40 | .flags = IORESOURCE_MEM, | ||
| 41 | }, { | ||
| 42 | .start = MX28_INT_RTC_ALARM, | ||
| 43 | .end = MX28_INT_RTC_ALARM, | ||
| 44 | .flags = IORESOURCE_IRQ, | ||
| 45 | }, | ||
| 46 | }; | ||
| 47 | |||
| 48 | return mxs_add_platform_device("stmp3xxx-rtc", 0, res, ARRAY_SIZE(res), | ||
| 49 | NULL, 0); | ||
| 50 | } | ||
| 51 | #endif /* CONFIG_SOC_IMX28 */ | ||
diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h index de6c7ba42544..4dec79563f19 100644 --- a/arch/arm/mach-mxs/include/mach/common.h +++ b/arch/arm/mach-mxs/include/mach/common.h | |||
| @@ -17,21 +17,12 @@ extern void mxs_timer_init(int); | |||
| 17 | extern void mxs_restart(char, const char *); | 17 | extern void mxs_restart(char, const char *); |
| 18 | extern int mxs_saif_clkmux_select(unsigned int clkmux); | 18 | extern int mxs_saif_clkmux_select(unsigned int clkmux); |
| 19 | 19 | ||
| 20 | extern void mx23_soc_init(void); | ||
| 21 | extern int mx23_clocks_init(void); | 20 | extern int mx23_clocks_init(void); |
| 22 | extern void mx23_map_io(void); | 21 | extern void mx23_map_io(void); |
| 23 | extern void mx23_init_irq(void); | ||
| 24 | 22 | ||
| 25 | extern void mx28_soc_init(void); | ||
| 26 | extern int mx28_clocks_init(void); | 23 | extern int mx28_clocks_init(void); |
| 27 | extern void mx28_map_io(void); | 24 | extern void mx28_map_io(void); |
| 28 | extern void mx28_init_irq(void); | ||
| 29 | 25 | ||
| 30 | extern void icoll_init_irq(void); | 26 | extern void icoll_init_irq(void); |
| 31 | 27 | ||
| 32 | extern struct platform_device *mxs_add_dma(const char *devid, | ||
| 33 | resource_size_t base); | ||
| 34 | extern struct platform_device *mxs_add_gpio(char *name, int id, | ||
| 35 | resource_size_t iobase, int irq); | ||
| 36 | |||
| 37 | #endif /* __MACH_MXS_COMMON_H__ */ | 28 | #endif /* __MACH_MXS_COMMON_H__ */ |
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h deleted file mode 100644 index e8b1d958240b..000000000000 --- a/arch/arm/mach-mxs/include/mach/devices-common.h +++ /dev/null | |||
| @@ -1,114 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009-2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include <linux/kernel.h> | ||
| 10 | #include <linux/platform_device.h> | ||
| 11 | #include <linux/init.h> | ||
| 12 | #include <linux/amba/bus.h> | ||
| 13 | |||
| 14 | extern struct device mxs_apbh_bus; | ||
| 15 | |||
| 16 | struct platform_device *mxs_add_platform_device_dmamask( | ||
| 17 | const char *name, int id, | ||
| 18 | const struct resource *res, unsigned int num_resources, | ||
| 19 | const void *data, size_t size_data, u64 dmamask); | ||
| 20 | |||
| 21 | static inline struct platform_device *mxs_add_platform_device( | ||
| 22 | const char *name, int id, | ||
| 23 | const struct resource *res, unsigned int num_resources, | ||
| 24 | const void *data, size_t size_data) | ||
| 25 | { | ||
| 26 | return mxs_add_platform_device_dmamask( | ||
| 27 | name, id, res, num_resources, data, size_data, 0); | ||
| 28 | } | ||
| 29 | |||
| 30 | /* auart */ | ||
| 31 | struct mxs_auart_data { | ||
| 32 | int id; | ||
| 33 | resource_size_t iobase; | ||
| 34 | resource_size_t iosize; | ||
| 35 | resource_size_t irq; | ||
| 36 | }; | ||
| 37 | struct platform_device *__init mxs_add_auart( | ||
| 38 | const struct mxs_auart_data *data); | ||
| 39 | |||
| 40 | /* fec */ | ||
| 41 | #include <linux/fec.h> | ||
| 42 | struct mxs_fec_data { | ||
| 43 | int id; | ||
| 44 | resource_size_t iobase; | ||
| 45 | resource_size_t iosize; | ||
| 46 | resource_size_t irq; | ||
| 47 | }; | ||
| 48 | struct platform_device *__init mxs_add_fec( | ||
| 49 | const struct mxs_fec_data *data, | ||
| 50 | const struct fec_platform_data *pdata); | ||
| 51 | |||
| 52 | /* flexcan */ | ||
| 53 | #include <linux/can/platform/flexcan.h> | ||
| 54 | struct mxs_flexcan_data { | ||
| 55 | int id; | ||
| 56 | resource_size_t iobase; | ||
| 57 | resource_size_t iosize; | ||
| 58 | resource_size_t irq; | ||
| 59 | }; | ||
| 60 | struct platform_device *__init mxs_add_flexcan( | ||
| 61 | const struct mxs_flexcan_data *data, | ||
| 62 | const struct flexcan_platform_data *pdata); | ||
| 63 | |||
| 64 | /* gpmi-nand */ | ||
| 65 | #include <linux/mtd/gpmi-nand.h> | ||
| 66 | struct mxs_gpmi_nand_data { | ||
| 67 | const char *devid; | ||
| 68 | const struct resource res[GPMI_NAND_RES_SIZE]; | ||
| 69 | }; | ||
| 70 | struct platform_device *__init | ||
| 71 | mxs_add_gpmi_nand(const struct gpmi_nand_platform_data *pdata, | ||
| 72 | const struct mxs_gpmi_nand_data *data); | ||
| 73 | |||
| 74 | /* i2c */ | ||
| 75 | struct mxs_mxs_i2c_data { | ||
| 76 | int id; | ||
| 77 | resource_size_t iobase; | ||
| 78 | resource_size_t errirq; | ||
| 79 | resource_size_t dmairq; | ||
| 80 | }; | ||
| 81 | struct platform_device * __init mxs_add_mxs_i2c( | ||
| 82 | const struct mxs_mxs_i2c_data *data); | ||
| 83 | |||
| 84 | /* mmc */ | ||
| 85 | #include <linux/mmc/mxs-mmc.h> | ||
| 86 | struct mxs_mxs_mmc_data { | ||
| 87 | const char *devid; | ||
| 88 | int id; | ||
| 89 | resource_size_t iobase; | ||
| 90 | resource_size_t dma; | ||
| 91 | resource_size_t irq_err; | ||
| 92 | resource_size_t irq_dma; | ||
| 93 | }; | ||
| 94 | struct platform_device *__init mxs_add_mxs_mmc( | ||
| 95 | const struct mxs_mxs_mmc_data *data, | ||
| 96 | const struct mxs_mmc_platform_data *pdata); | ||
| 97 | |||
| 98 | /* pwm */ | ||
| 99 | struct platform_device *__init mxs_add_mxs_pwm( | ||
| 100 | resource_size_t iobase, int id); | ||
| 101 | |||
| 102 | /* saif */ | ||
| 103 | #include <sound/saif.h> | ||
| 104 | struct mxs_saif_data { | ||
| 105 | int id; | ||
| 106 | resource_size_t iobase; | ||
| 107 | resource_size_t irq; | ||
| 108 | resource_size_t dma; | ||
| 109 | resource_size_t dmairq; | ||
| 110 | }; | ||
| 111 | |||
| 112 | struct platform_device *__init mxs_add_saif( | ||
| 113 | const struct mxs_saif_data *data, | ||
| 114 | const struct mxs_saif_platform_data *pdata); | ||
diff --git a/arch/arm/mach-mxs/include/mach/iomux-mx23.h b/arch/arm/mach-mxs/include/mach/iomux-mx23.h deleted file mode 100644 index b0190a4822f2..000000000000 --- a/arch/arm/mach-mxs/include/mach/iomux-mx23.h +++ /dev/null | |||
| @@ -1,355 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> | ||
| 3 | * Copyright (C) 2010 Freescale Semiconductor, Inc. | ||
| 4 | * | ||
| 5 | * The code contained herein is licensed under the GNU General Public | ||
| 6 | * License. You may obtain a copy of the GNU General Public License | ||
| 7 | * Version 2 or later at the following locations: | ||
| 8 | * | ||
| 9 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 10 | * http://www.gnu.org/copyleft/gpl.html | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __MACH_IOMUX_MX23_H__ | ||
| 14 | #define __MACH_IOMUX_MX23_H__ | ||
| 15 | |||
| 16 | #include <mach/iomux.h> | ||
| 17 | |||
| 18 | /* | ||
| 19 | * The naming convention for the pad modes is MX23_PAD_<padname>__<padmode> | ||
| 20 | * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> | ||
| 21 | * See also iomux.h | ||
| 22 | * | ||
| 23 | * BANK PIN MUX | ||
| 24 | */ | ||
| 25 | /* MUXSEL_0 */ | ||
| 26 | #define MX23_PAD_GPMI_D00__GPMI_D00 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_0) | ||
| 27 | #define MX23_PAD_GPMI_D01__GPMI_D01 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_0) | ||
| 28 | #define MX23_PAD_GPMI_D02__GPMI_D02 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_0) | ||
| 29 | #define MX23_PAD_GPMI_D03__GPMI_D03 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0) | ||
| 30 | #define MX23_PAD_GPMI_D04__GPMI_D04 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_0) | ||
| 31 | #define MX23_PAD_GPMI_D05__GPMI_D05 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_0) | ||
| 32 | #define MX23_PAD_GPMI_D06__GPMI_D06 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_0) | ||
| 33 | #define MX23_PAD_GPMI_D07__GPMI_D07 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_0) | ||
| 34 | #define MX23_PAD_GPMI_D08__GPMI_D08 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_0) | ||
| 35 | #define MX23_PAD_GPMI_D09__GPMI_D09 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_0) | ||
| 36 | #define MX23_PAD_GPMI_D10__GPMI_D10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_0) | ||
| 37 | #define MX23_PAD_GPMI_D11__GPMI_D11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_0) | ||
| 38 | #define MX23_PAD_GPMI_D12__GPMI_D12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_0) | ||
| 39 | #define MX23_PAD_GPMI_D13__GPMI_D13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_0) | ||
| 40 | #define MX23_PAD_GPMI_D14__GPMI_D14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_0) | ||
| 41 | #define MX23_PAD_GPMI_D15__GPMI_D15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_0) | ||
| 42 | #define MX23_PAD_GPMI_CLE__GPMI_CLE MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0) | ||
| 43 | #define MX23_PAD_GPMI_ALE__GPMI_ALE MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0) | ||
| 44 | #define MX23_PAD_GPMI_CE2N__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0) | ||
| 45 | #define MX23_PAD_GPMI_RDY0__GPMI_RDY0 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0) | ||
| 46 | #define MX23_PAD_GPMI_RDY1__GPMI_RDY1 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0) | ||
| 47 | #define MX23_PAD_GPMI_RDY2__GPMI_RDY2 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0) | ||
| 48 | #define MX23_PAD_GPMI_RDY3__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0) | ||
| 49 | #define MX23_PAD_GPMI_WPN__GPMI_WPN MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0) | ||
| 50 | #define MX23_PAD_GPMI_WRN__GPMI_WRN MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0) | ||
| 51 | #define MX23_PAD_GPMI_RDN__GPMI_RDN MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0) | ||
| 52 | #define MX23_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0) | ||
| 53 | #define MX23_PAD_AUART1_RTS__AUART1_RTS MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0) | ||
| 54 | #define MX23_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0) | ||
| 55 | #define MX23_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_0) | ||
| 56 | #define MX23_PAD_I2C_SCL__I2C_SCL MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_0) | ||
| 57 | #define MX23_PAD_I2C_SDA__I2C_SDA MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_0) | ||
| 58 | |||
| 59 | #define MX23_PAD_LCD_D00__LCD_D00 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_0) | ||
| 60 | #define MX23_PAD_LCD_D01__LCD_D01 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_0) | ||
| 61 | #define MX23_PAD_LCD_D02__LCD_D02 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_0) | ||
| 62 | #define MX23_PAD_LCD_D03__LCD_D03 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0) | ||
| 63 | #define MX23_PAD_LCD_D04__LCD_D04 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_0) | ||
| 64 | #define MX23_PAD_LCD_D05__LCD_D05 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_0) | ||
| 65 | #define MX23_PAD_LCD_D06__LCD_D06 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_0) | ||
| 66 | #define MX23_PAD_LCD_D07__LCD_D07 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_0) | ||
| 67 | #define MX23_PAD_LCD_D08__LCD_D08 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_0) | ||
| 68 | #define MX23_PAD_LCD_D09__LCD_D09 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_0) | ||
| 69 | #define MX23_PAD_LCD_D10__LCD_D10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0) | ||
| 70 | #define MX23_PAD_LCD_D11__LCD_D11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0) | ||
| 71 | #define MX23_PAD_LCD_D12__LCD_D12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0) | ||
| 72 | #define MX23_PAD_LCD_D13__LCD_D13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0) | ||
| 73 | #define MX23_PAD_LCD_D14__LCD_D14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0) | ||
| 74 | #define MX23_PAD_LCD_D15__LCD_D15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0) | ||
| 75 | #define MX23_PAD_LCD_D16__LCD_D16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0) | ||
| 76 | #define MX23_PAD_LCD_D17__LCD_D17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0) | ||
| 77 | #define MX23_PAD_LCD_RESET__LCD_RESET MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0) | ||
| 78 | #define MX23_PAD_LCD_RS__LCD_RS MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0) | ||
| 79 | #define MX23_PAD_LCD_WR__LCD_WR MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0) | ||
| 80 | #define MX23_PAD_LCD_CS__LCD_CS MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0) | ||
| 81 | #define MX23_PAD_LCD_DOTCK__LCD_DOTCK MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0) | ||
| 82 | #define MX23_PAD_LCD_ENABLE__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0) | ||
| 83 | #define MX23_PAD_LCD_HSYNC__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0) | ||
| 84 | #define MX23_PAD_LCD_VSYNC__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0) | ||
| 85 | #define MX23_PAD_PWM0__PWM0 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0) | ||
| 86 | #define MX23_PAD_PWM1__PWM1 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0) | ||
| 87 | #define MX23_PAD_PWM2__PWM2 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0) | ||
| 88 | #define MX23_PAD_PWM3__PWM3 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0) | ||
| 89 | #define MX23_PAD_PWM4__PWM4 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0) | ||
| 90 | |||
| 91 | #define MX23_PAD_SSP1_CMD__SSP1_CMD MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_0) | ||
| 92 | #define MX23_PAD_SSP1_DETECT__SSP1_DETECT MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_0) | ||
| 93 | #define MX23_PAD_SSP1_DATA0__SSP1_DATA0 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_0) | ||
| 94 | #define MX23_PAD_SSP1_DATA1__SSP1_DATA1 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0) | ||
| 95 | #define MX23_PAD_SSP1_DATA2__SSP1_DATA2 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_0) | ||
| 96 | #define MX23_PAD_SSP1_DATA3__SSP1_DATA3 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_0) | ||
| 97 | #define MX23_PAD_SSP1_SCK__SSP1_SCK MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_0) | ||
| 98 | #define MX23_PAD_ROTARYA__ROTARYA MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_0) | ||
| 99 | #define MX23_PAD_ROTARYB__ROTARYB MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_0) | ||
| 100 | #define MX23_PAD_EMI_A00__EMI_A00 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_0) | ||
| 101 | #define MX23_PAD_EMI_A01__EMI_A01 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0) | ||
| 102 | #define MX23_PAD_EMI_A02__EMI_A02 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_0) | ||
| 103 | #define MX23_PAD_EMI_A03__EMI_A03 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0) | ||
| 104 | #define MX23_PAD_EMI_A04__EMI_A04 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0) | ||
| 105 | #define MX23_PAD_EMI_A05__EMI_A05 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0) | ||
| 106 | #define MX23_PAD_EMI_A06__EMI_A06 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0) | ||
| 107 | #define MX23_PAD_EMI_A07__EMI_A07 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0) | ||
| 108 | #define MX23_PAD_EMI_A08__EMI_A08 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0) | ||
| 109 | #define MX23_PAD_EMI_A09__EMI_A09 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0) | ||
| 110 | #define MX23_PAD_EMI_A10__EMI_A10 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0) | ||
| 111 | #define MX23_PAD_EMI_A11__EMI_A11 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0) | ||
| 112 | #define MX23_PAD_EMI_A12__EMI_A12 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0) | ||
| 113 | #define MX23_PAD_EMI_BA0__EMI_BA0 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_0) | ||
| 114 | #define MX23_PAD_EMI_BA1__EMI_BA1 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_0) | ||
| 115 | #define MX23_PAD_EMI_CASN__EMI_CASN MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0) | ||
| 116 | #define MX23_PAD_EMI_CE0N__EMI_CE0N MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0) | ||
| 117 | #define MX23_PAD_EMI_CE1N__EMI_CE1N MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0) | ||
| 118 | #define MX23_PAD_GPMI_CE1N__GPMI_CE1N MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0) | ||
| 119 | #define MX23_PAD_GPMI_CE0N__GPMI_CE0N MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_0) | ||
| 120 | #define MX23_PAD_EMI_CKE__EMI_CKE MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_0) | ||
| 121 | #define MX23_PAD_EMI_RASN__EMI_RASN MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_0) | ||
| 122 | #define MX23_PAD_EMI_WEN__EMI_WEN MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_0) | ||
| 123 | |||
| 124 | #define MX23_PAD_EMI_D00__EMI_D00 MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0) | ||
| 125 | #define MX23_PAD_EMI_D01__EMI_D01 MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0) | ||
| 126 | #define MX23_PAD_EMI_D02__EMI_D02 MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0) | ||
| 127 | #define MX23_PAD_EMI_D03__EMI_D03 MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0) | ||
| 128 | #define MX23_PAD_EMI_D04__EMI_D04 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0) | ||
| 129 | #define MX23_PAD_EMI_D05__EMI_D05 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0) | ||
| 130 | #define MX23_PAD_EMI_D06__EMI_D06 MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0) | ||
| 131 | #define MX23_PAD_EMI_D07__EMI_D07 MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_0) | ||
| 132 | #define MX23_PAD_EMI_D08__EMI_D08 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_0) | ||
| 133 | #define MX23_PAD_EMI_D09__EMI_D09 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_0) | ||
| 134 | #define MX23_PAD_EMI_D10__EMI_D10 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0) | ||
| 135 | #define MX23_PAD_EMI_D11__EMI_D11 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0) | ||
| 136 | #define MX23_PAD_EMI_D12__EMI_D12 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0) | ||
| 137 | #define MX23_PAD_EMI_D13__EMI_D13 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0) | ||
| 138 | #define MX23_PAD_EMI_D14__EMI_D14 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0) | ||
| 139 | #define MX23_PAD_EMI_D15__EMI_D15 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0) | ||
| 140 | #define MX23_PAD_EMI_DQM0__EMI_DQM0 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0) | ||
| 141 | #define MX23_PAD_EMI_DQM1__EMI_DQM1 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0) | ||
| 142 | #define MX23_PAD_EMI_DQS0__EMI_DQS0 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0) | ||
| 143 | #define MX23_PAD_EMI_DQS1__EMI_DQS1 MXS_IOMUX_PAD_NAKED(3, 19, PAD_MUXSEL_0) | ||
| 144 | #define MX23_PAD_EMI_CLK__EMI_CLK MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0) | ||
| 145 | #define MX23_PAD_EMI_CLKN__EMI_CLKN MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0) | ||
| 146 | |||
| 147 | /* MUXSEL_1 */ | ||
| 148 | #define MX23_PAD_GPMI_D00__LCD_D8 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_1) | ||
| 149 | #define MX23_PAD_GPMI_D01__LCD_D9 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_1) | ||
| 150 | #define MX23_PAD_GPMI_D02__LCD_D10 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_1) | ||
| 151 | #define MX23_PAD_GPMI_D03__LCD_D11 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_1) | ||
| 152 | #define MX23_PAD_GPMI_D04__LCD_D12 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_1) | ||
| 153 | #define MX23_PAD_GPMI_D05__LCD_D13 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_1) | ||
| 154 | #define MX23_PAD_GPMI_D06__LCD_D14 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_1) | ||
| 155 | #define MX23_PAD_GPMI_D07__LCD_D15 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_1) | ||
| 156 | #define MX23_PAD_GPMI_D08__LCD_D18 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_1) | ||
| 157 | #define MX23_PAD_GPMI_D09__LCD_D19 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_1) | ||
| 158 | #define MX23_PAD_GPMI_D10__LCD_D20 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_1) | ||
| 159 | #define MX23_PAD_GPMI_D11__LCD_D21 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_1) | ||
| 160 | #define MX23_PAD_GPMI_D12__LCD_D22 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_1) | ||
| 161 | #define MX23_PAD_GPMI_D13__LCD_D23 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_1) | ||
| 162 | #define MX23_PAD_GPMI_D14__AUART2_RX MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_1) | ||
| 163 | #define MX23_PAD_GPMI_D15__AUART2_TX MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_1) | ||
| 164 | #define MX23_PAD_GPMI_CLE__LCD_D16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1) | ||
| 165 | #define MX23_PAD_GPMI_ALE__LCD_D17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1) | ||
| 166 | #define MX23_PAD_GPMI_CE2N__ATA_A2 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1) | ||
| 167 | #define MX23_PAD_AUART1_RTS__IR_CLK MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1) | ||
| 168 | #define MX23_PAD_AUART1_RX__IR_RX MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1) | ||
| 169 | #define MX23_PAD_AUART1_TX__IR_TX MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_1) | ||
| 170 | #define MX23_PAD_I2C_SCL__GPMI_RDY2 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_1) | ||
| 171 | #define MX23_PAD_I2C_SDA__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_1) | ||
| 172 | |||
| 173 | #define MX23_PAD_LCD_D00__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_1) | ||
| 174 | #define MX23_PAD_LCD_D01__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_1) | ||
| 175 | #define MX23_PAD_LCD_D02__ETM_DA10 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_1) | ||
| 176 | #define MX23_PAD_LCD_D03__ETM_DA11 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_1) | ||
| 177 | #define MX23_PAD_LCD_D04__ETM_DA12 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_1) | ||
| 178 | #define MX23_PAD_LCD_D05__ETM_DA13 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_1) | ||
| 179 | #define MX23_PAD_LCD_D06__ETM_DA14 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_1) | ||
| 180 | #define MX23_PAD_LCD_D07__ETM_DA15 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_1) | ||
| 181 | #define MX23_PAD_LCD_D08__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_1) | ||
| 182 | #define MX23_PAD_LCD_D09__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_1) | ||
| 183 | #define MX23_PAD_LCD_D10__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_1) | ||
| 184 | #define MX23_PAD_LCD_D11__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_1) | ||
| 185 | #define MX23_PAD_LCD_D12__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_1) | ||
| 186 | #define MX23_PAD_LCD_D13__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_1) | ||
| 187 | #define MX23_PAD_LCD_D14__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_1) | ||
| 188 | #define MX23_PAD_LCD_D15__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_1) | ||
| 189 | #define MX23_PAD_LCD_RESET__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_1) | ||
| 190 | #define MX23_PAD_LCD_RS__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_1) | ||
| 191 | #define MX23_PAD_LCD_DOTCK__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1) | ||
| 192 | #define MX23_PAD_LCD_ENABLE__I2C_SCL MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1) | ||
| 193 | #define MX23_PAD_LCD_HSYNC__I2C_SDA MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1) | ||
| 194 | #define MX23_PAD_LCD_VSYNC__LCD_BUSY MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1) | ||
| 195 | #define MX23_PAD_PWM0__ROTARYA MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1) | ||
| 196 | #define MX23_PAD_PWM1__ROTARYB MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1) | ||
| 197 | #define MX23_PAD_PWM2__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1) | ||
| 198 | #define MX23_PAD_PWM3__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1) | ||
| 199 | #define MX23_PAD_PWM4__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1) | ||
| 200 | |||
| 201 | #define MX23_PAD_SSP1_DETECT__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_1) | ||
| 202 | #define MX23_PAD_SSP1_DATA1__I2C_SCL MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_1) | ||
| 203 | #define MX23_PAD_SSP1_DATA2__I2C_SDA MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_1) | ||
| 204 | #define MX23_PAD_ROTARYA__AUART2_RTS MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_1) | ||
| 205 | #define MX23_PAD_ROTARYB__AUART2_CTS MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_1) | ||
| 206 | |||
| 207 | /* MUXSEL_2 */ | ||
| 208 | #define MX23_PAD_GPMI_D00__SSP2_DATA0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_2) | ||
| 209 | #define MX23_PAD_GPMI_D01__SSP2_DATA1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_2) | ||
| 210 | #define MX23_PAD_GPMI_D02__SSP2_DATA2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_2) | ||
| 211 | #define MX23_PAD_GPMI_D03__SSP2_DATA3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_2) | ||
| 212 | #define MX23_PAD_GPMI_D04__SSP2_DATA4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_2) | ||
| 213 | #define MX23_PAD_GPMI_D05__SSP2_DATA5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_2) | ||
| 214 | #define MX23_PAD_GPMI_D06__SSP2_DATA6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_2) | ||
| 215 | #define MX23_PAD_GPMI_D07__SSP2_DATA7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_2) | ||
| 216 | #define MX23_PAD_GPMI_D08__SSP1_DATA4 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_2) | ||
| 217 | #define MX23_PAD_GPMI_D09__SSP1_DATA5 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_2) | ||
| 218 | #define MX23_PAD_GPMI_D10__SSP1_DATA6 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_2) | ||
| 219 | #define MX23_PAD_GPMI_D11__SSP1_DATA7 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_2) | ||
| 220 | #define MX23_PAD_GPMI_D15__GPMI_CE3N MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_2) | ||
| 221 | #define MX23_PAD_GPMI_RDY0__SSP2_DETECT MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2) | ||
| 222 | #define MX23_PAD_GPMI_RDY1__SSP2_CMD MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2) | ||
| 223 | #define MX23_PAD_GPMI_WRN__SSP2_SCK MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_2) | ||
| 224 | #define MX23_PAD_AUART1_CTS__SSP1_DATA4 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2) | ||
| 225 | #define MX23_PAD_AUART1_RTS__SSP1_DATA5 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2) | ||
| 226 | #define MX23_PAD_AUART1_RX__SSP1_DATA6 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_2) | ||
| 227 | #define MX23_PAD_AUART1_TX__SSP1_DATA7 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_2) | ||
| 228 | #define MX23_PAD_I2C_SCL__AUART1_TX MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_2) | ||
| 229 | #define MX23_PAD_I2C_SDA__AUART1_RX MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_2) | ||
| 230 | |||
| 231 | #define MX23_PAD_LCD_D08__SAIF2_SDATA0 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_2) | ||
| 232 | #define MX23_PAD_LCD_D09__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_2) | ||
| 233 | #define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2) | ||
| 234 | #define MX23_PAD_LCD_D11__SAIF_LRCLK MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2) | ||
| 235 | #define MX23_PAD_LCD_D12__SAIF2_SDATA1 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2) | ||
| 236 | #define MX23_PAD_LCD_D13__SAIF2_SDATA2 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2) | ||
| 237 | #define MX23_PAD_LCD_D14__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2) | ||
| 238 | #define MX23_PAD_LCD_D15__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2) | ||
| 239 | #define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2) | ||
| 240 | #define MX23_PAD_LCD_RESET__GPMI_CE3N MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2) | ||
| 241 | #define MX23_PAD_PWM0__DUART_RX MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_2) | ||
| 242 | #define MX23_PAD_PWM1__DUART_TX MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_2) | ||
| 243 | #define MX23_PAD_PWM3__AUART1_CTS MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2) | ||
| 244 | #define MX23_PAD_PWM4__AUART1_RTS MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2) | ||
| 245 | |||
| 246 | #define MX23_PAD_SSP1_CMD__JTAG_TDO MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_2) | ||
| 247 | #define MX23_PAD_SSP1_DETECT__USB_OTG_ID MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_2) | ||
| 248 | #define MX23_PAD_SSP1_DATA0__JTAG_TDI MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_2) | ||
| 249 | #define MX23_PAD_SSP1_DATA1__JTAG_TCLK MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_2) | ||
| 250 | #define MX23_PAD_SSP1_DATA2__JTAG_RTCK MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_2) | ||
| 251 | #define MX23_PAD_SSP1_DATA3__JTAG_TMS MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_2) | ||
| 252 | #define MX23_PAD_SSP1_SCK__JTAG_TRST MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_2) | ||
| 253 | #define MX23_PAD_ROTARYA__SPDIF MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_2) | ||
| 254 | #define MX23_PAD_ROTARYB__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_2) | ||
| 255 | |||
| 256 | /* MUXSEL_GPIO */ | ||
| 257 | #define MX23_PAD_GPMI_D00__GPIO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO) | ||
| 258 | #define MX23_PAD_GPMI_D01__GPIO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO) | ||
| 259 | #define MX23_PAD_GPMI_D02__GPIO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO) | ||
| 260 | #define MX23_PAD_GPMI_D03__GPIO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO) | ||
| 261 | #define MX23_PAD_GPMI_D04__GPIO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO) | ||
| 262 | #define MX23_PAD_GPMI_D05__GPIO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO) | ||
| 263 | #define MX23_PAD_GPMI_D06__GPIO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO) | ||
| 264 | #define MX23_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO) | ||
| 265 | #define MX23_PAD_GPMI_D08__GPIO_0_8 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_GPIO) | ||
| 266 | #define MX23_PAD_GPMI_D09__GPIO_0_9 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_GPIO) | ||
| 267 | #define MX23_PAD_GPMI_D10__GPIO_0_10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO) | ||
| 268 | #define MX23_PAD_GPMI_D11__GPIO_0_11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO) | ||
| 269 | #define MX23_PAD_GPMI_D12__GPIO_0_12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO) | ||
| 270 | #define MX23_PAD_GPMI_D13__GPIO_0_13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO) | ||
| 271 | #define MX23_PAD_GPMI_D14__GPIO_0_14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO) | ||
| 272 | #define MX23_PAD_GPMI_D15__GPIO_0_15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO) | ||
| 273 | #define MX23_PAD_GPMI_CLE__GPIO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO) | ||
| 274 | #define MX23_PAD_GPMI_ALE__GPIO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO) | ||
| 275 | #define MX23_PAD_GPMI_CE2N__GPIO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO) | ||
| 276 | #define MX23_PAD_GPMI_RDY0__GPIO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO) | ||
| 277 | #define MX23_PAD_GPMI_RDY1__GPIO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO) | ||
| 278 | #define MX23_PAD_GPMI_RDY2__GPIO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO) | ||
| 279 | #define MX23_PAD_GPMI_RDY3__GPIO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO) | ||
| 280 | #define MX23_PAD_GPMI_WPN__GPIO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO) | ||
| 281 | #define MX23_PAD_GPMI_WRN__GPIO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO) | ||
| 282 | #define MX23_PAD_GPMI_RDN__GPIO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO) | ||
| 283 | #define MX23_PAD_AUART1_CTS__GPIO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO) | ||
| 284 | #define MX23_PAD_AUART1_RTS__GPIO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO) | ||
| 285 | #define MX23_PAD_AUART1_RX__GPIO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO) | ||
| 286 | #define MX23_PAD_AUART1_TX__GPIO_0_29 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO) | ||
| 287 | #define MX23_PAD_I2C_SCL__GPIO_0_30 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO) | ||
| 288 | #define MX23_PAD_I2C_SDA__GPIO_0_31 MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO) | ||
| 289 | |||
| 290 | #define MX23_PAD_LCD_D00__GPIO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO) | ||
| 291 | #define MX23_PAD_LCD_D01__GPIO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO) | ||
| 292 | #define MX23_PAD_LCD_D02__GPIO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO) | ||
| 293 | #define MX23_PAD_LCD_D03__GPIO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO) | ||
| 294 | #define MX23_PAD_LCD_D04__GPIO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO) | ||
| 295 | #define MX23_PAD_LCD_D05__GPIO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO) | ||
| 296 | #define MX23_PAD_LCD_D06__GPIO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO) | ||
| 297 | #define MX23_PAD_LCD_D07__GPIO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO) | ||
| 298 | #define MX23_PAD_LCD_D08__GPIO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO) | ||
| 299 | #define MX23_PAD_LCD_D09__GPIO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO) | ||
| 300 | #define MX23_PAD_LCD_D10__GPIO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO) | ||
| 301 | #define MX23_PAD_LCD_D11__GPIO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO) | ||
| 302 | #define MX23_PAD_LCD_D12__GPIO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO) | ||
| 303 | #define MX23_PAD_LCD_D13__GPIO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO) | ||
| 304 | #define MX23_PAD_LCD_D14__GPIO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO) | ||
| 305 | #define MX23_PAD_LCD_D15__GPIO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO) | ||
| 306 | #define MX23_PAD_LCD_D16__GPIO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO) | ||
| 307 | #define MX23_PAD_LCD_D17__GPIO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO) | ||
| 308 | #define MX23_PAD_LCD_RESET__GPIO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO) | ||
| 309 | #define MX23_PAD_LCD_RS__GPIO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO) | ||
| 310 | #define MX23_PAD_LCD_WR__GPIO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO) | ||
| 311 | #define MX23_PAD_LCD_CS__GPIO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO) | ||
| 312 | #define MX23_PAD_LCD_DOTCK__GPIO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO) | ||
| 313 | #define MX23_PAD_LCD_ENABLE__GPIO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO) | ||
| 314 | #define MX23_PAD_LCD_HSYNC__GPIO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO) | ||
| 315 | #define MX23_PAD_LCD_VSYNC__GPIO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO) | ||
| 316 | #define MX23_PAD_PWM0__GPIO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO) | ||
| 317 | #define MX23_PAD_PWM1__GPIO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO) | ||
| 318 | #define MX23_PAD_PWM2__GPIO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO) | ||
| 319 | #define MX23_PAD_PWM3__GPIO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO) | ||
| 320 | #define MX23_PAD_PWM4__GPIO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO) | ||
| 321 | |||
| 322 | #define MX23_PAD_SSP1_CMD__GPIO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO) | ||
| 323 | #define MX23_PAD_SSP1_DETECT__GPIO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO) | ||
| 324 | #define MX23_PAD_SSP1_DATA0__GPIO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO) | ||
| 325 | #define MX23_PAD_SSP1_DATA1__GPIO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO) | ||
| 326 | #define MX23_PAD_SSP1_DATA2__GPIO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO) | ||
| 327 | #define MX23_PAD_SSP1_DATA3__GPIO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO) | ||
| 328 | #define MX23_PAD_SSP1_SCK__GPIO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO) | ||
| 329 | #define MX23_PAD_ROTARYA__GPIO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO) | ||
| 330 | #define MX23_PAD_ROTARYB__GPIO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO) | ||
| 331 | #define MX23_PAD_EMI_A00__GPIO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO) | ||
| 332 | #define MX23_PAD_EMI_A01__GPIO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO) | ||
| 333 | #define MX23_PAD_EMI_A02__GPIO_2_11 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO) | ||
| 334 | #define MX23_PAD_EMI_A03__GPIO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO) | ||
| 335 | #define MX23_PAD_EMI_A04__GPIO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO) | ||
| 336 | #define MX23_PAD_EMI_A05__GPIO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO) | ||
| 337 | #define MX23_PAD_EMI_A06__GPIO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO) | ||
| 338 | #define MX23_PAD_EMI_A07__GPIO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO) | ||
| 339 | #define MX23_PAD_EMI_A08__GPIO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO) | ||
| 340 | #define MX23_PAD_EMI_A09__GPIO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO) | ||
| 341 | #define MX23_PAD_EMI_A10__GPIO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO) | ||
| 342 | #define MX23_PAD_EMI_A11__GPIO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO) | ||
| 343 | #define MX23_PAD_EMI_A12__GPIO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO) | ||
| 344 | #define MX23_PAD_EMI_BA0__GPIO_2_22 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO) | ||
| 345 | #define MX23_PAD_EMI_BA1__GPIO_2_23 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO) | ||
| 346 | #define MX23_PAD_EMI_CASN__GPIO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO) | ||
| 347 | #define MX23_PAD_EMI_CE0N__GPIO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO) | ||
| 348 | #define MX23_PAD_EMI_CE1N__GPIO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO) | ||
| 349 | #define MX23_PAD_GPMI_CE1N__GPIO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO) | ||
| 350 | #define MX23_PAD_GPMI_CE0N__GPIO_2_28 MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO) | ||
| 351 | #define MX23_PAD_EMI_CKE__GPIO_2_29 MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO) | ||
| 352 | #define MX23_PAD_EMI_RASN__GPIO_2_30 MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO) | ||
| 353 | #define MX23_PAD_EMI_WEN__GPIO_2_31 MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO) | ||
| 354 | |||
| 355 | #endif /* __MACH_IOMUX_MX23_H__ */ | ||
diff --git a/arch/arm/mach-mxs/include/mach/iomux-mx28.h b/arch/arm/mach-mxs/include/mach/iomux-mx28.h deleted file mode 100644 index f50fefd10520..000000000000 --- a/arch/arm/mach-mxs/include/mach/iomux-mx28.h +++ /dev/null | |||
| @@ -1,537 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> | ||
| 3 | * Copyright (C) 2010 Freescale Semiconductor, Inc. | ||
| 4 | * | ||
| 5 | * The code contained herein is licensed under the GNU General Public | ||
| 6 | * License. You may obtain a copy of the GNU General Public License | ||
| 7 | * Version 2 or later at the following locations: | ||
| 8 | * | ||
| 9 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 10 | * http://www.gnu.org/copyleft/gpl.html | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __MACH_IOMUX_MX28_H__ | ||
| 14 | #define __MACH_IOMUX_MX28_H__ | ||
| 15 | |||
| 16 | #include <mach/iomux.h> | ||
| 17 | |||
| 18 | /* | ||
| 19 | * The naming convention for the pad modes is MX28_PAD_<padname>__<padmode> | ||
| 20 | * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> | ||
| 21 | * See also iomux.h | ||
| 22 | * | ||
| 23 | * BANK PIN MUX | ||
| 24 | */ | ||
| 25 | /* MUXSEL_0 */ | ||
| 26 | #define MX28_PAD_GPMI_D00__GPMI_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_0) | ||
| 27 | #define MX28_PAD_GPMI_D01__GPMI_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_0) | ||
| 28 | #define MX28_PAD_GPMI_D02__GPMI_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_0) | ||
| 29 | #define MX28_PAD_GPMI_D03__GPMI_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0) | ||
| 30 | #define MX28_PAD_GPMI_D04__GPMI_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_0) | ||
| 31 | #define MX28_PAD_GPMI_D05__GPMI_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_0) | ||
| 32 | #define MX28_PAD_GPMI_D06__GPMI_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_0) | ||
| 33 | #define MX28_PAD_GPMI_D07__GPMI_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_0) | ||
| 34 | #define MX28_PAD_GPMI_CE0N__GPMI_CE0N MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0) | ||
| 35 | #define MX28_PAD_GPMI_CE1N__GPMI_CE1N MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0) | ||
| 36 | #define MX28_PAD_GPMI_CE2N__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0) | ||
| 37 | #define MX28_PAD_GPMI_CE3N__GPMI_CE3N MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0) | ||
| 38 | #define MX28_PAD_GPMI_RDY0__GPMI_READY0 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0) | ||
| 39 | #define MX28_PAD_GPMI_RDY1__GPMI_READY1 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0) | ||
| 40 | #define MX28_PAD_GPMI_RDY2__GPMI_READY2 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0) | ||
| 41 | #define MX28_PAD_GPMI_RDY3__GPMI_READY3 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0) | ||
| 42 | #define MX28_PAD_GPMI_RDN__GPMI_RDN MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0) | ||
| 43 | #define MX28_PAD_GPMI_WRN__GPMI_WRN MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0) | ||
| 44 | #define MX28_PAD_GPMI_ALE__GPMI_ALE MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0) | ||
| 45 | #define MX28_PAD_GPMI_CLE__GPMI_CLE MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0) | ||
| 46 | #define MX28_PAD_GPMI_RESETN__GPMI_RESETN MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0) | ||
| 47 | |||
| 48 | #define MX28_PAD_LCD_D00__LCD_D0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_0) | ||
| 49 | #define MX28_PAD_LCD_D01__LCD_D1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_0) | ||
| 50 | #define MX28_PAD_LCD_D02__LCD_D2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_0) | ||
| 51 | #define MX28_PAD_LCD_D03__LCD_D3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0) | ||
| 52 | #define MX28_PAD_LCD_D04__LCD_D4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_0) | ||
| 53 | #define MX28_PAD_LCD_D05__LCD_D5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_0) | ||
| 54 | #define MX28_PAD_LCD_D06__LCD_D6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_0) | ||
| 55 | #define MX28_PAD_LCD_D07__LCD_D7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_0) | ||
| 56 | #define MX28_PAD_LCD_D08__LCD_D8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_0) | ||
| 57 | #define MX28_PAD_LCD_D09__LCD_D9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_0) | ||
| 58 | #define MX28_PAD_LCD_D10__LCD_D10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0) | ||
| 59 | #define MX28_PAD_LCD_D11__LCD_D11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0) | ||
| 60 | #define MX28_PAD_LCD_D12__LCD_D12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0) | ||
| 61 | #define MX28_PAD_LCD_D13__LCD_D13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0) | ||
| 62 | #define MX28_PAD_LCD_D14__LCD_D14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0) | ||
| 63 | #define MX28_PAD_LCD_D15__LCD_D15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0) | ||
| 64 | #define MX28_PAD_LCD_D16__LCD_D16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0) | ||
| 65 | #define MX28_PAD_LCD_D17__LCD_D17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0) | ||
| 66 | #define MX28_PAD_LCD_D18__LCD_D18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0) | ||
| 67 | #define MX28_PAD_LCD_D19__LCD_D19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0) | ||
| 68 | #define MX28_PAD_LCD_D20__LCD_D20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0) | ||
| 69 | #define MX28_PAD_LCD_D21__LCD_D21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0) | ||
| 70 | #define MX28_PAD_LCD_D22__LCD_D22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0) | ||
| 71 | #define MX28_PAD_LCD_D23__LCD_D23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0) | ||
| 72 | #define MX28_PAD_LCD_RD_E__LCD_RD_E MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0) | ||
| 73 | #define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0) | ||
| 74 | #define MX28_PAD_LCD_RS__LCD_RS MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0) | ||
| 75 | #define MX28_PAD_LCD_CS__LCD_CS MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0) | ||
| 76 | #define MX28_PAD_LCD_VSYNC__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0) | ||
| 77 | #define MX28_PAD_LCD_HSYNC__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0) | ||
| 78 | #define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0) | ||
| 79 | #define MX28_PAD_LCD_ENABLE__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_0) | ||
| 80 | |||
| 81 | #define MX28_PAD_SSP0_DATA0__SSP0_D0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_0) | ||
| 82 | #define MX28_PAD_SSP0_DATA1__SSP0_D1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_0) | ||
| 83 | #define MX28_PAD_SSP0_DATA2__SSP0_D2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_0) | ||
| 84 | #define MX28_PAD_SSP0_DATA3__SSP0_D3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0) | ||
| 85 | #define MX28_PAD_SSP0_DATA4__SSP0_D4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_0) | ||
| 86 | #define MX28_PAD_SSP0_DATA5__SSP0_D5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_0) | ||
| 87 | #define MX28_PAD_SSP0_DATA6__SSP0_D6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_0) | ||
| 88 | #define MX28_PAD_SSP0_DATA7__SSP0_D7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_0) | ||
| 89 | #define MX28_PAD_SSP0_CMD__SSP0_CMD MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_0) | ||
| 90 | #define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_0) | ||
| 91 | #define MX28_PAD_SSP0_SCK__SSP0_SCK MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0) | ||
| 92 | #define MX28_PAD_SSP1_SCK__SSP1_SCK MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0) | ||
| 93 | #define MX28_PAD_SSP1_CMD__SSP1_CMD MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0) | ||
| 94 | #define MX28_PAD_SSP1_DATA0__SSP1_D0 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0) | ||
| 95 | #define MX28_PAD_SSP1_DATA3__SSP1_D3 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0) | ||
| 96 | #define MX28_PAD_SSP2_SCK__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0) | ||
| 97 | #define MX28_PAD_SSP2_MOSI__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0) | ||
| 98 | #define MX28_PAD_SSP2_MISO__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0) | ||
| 99 | #define MX28_PAD_SSP2_SS0__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0) | ||
| 100 | #define MX28_PAD_SSP2_SS1__SSP2_D4 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0) | ||
| 101 | #define MX28_PAD_SSP2_SS2__SSP2_D5 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0) | ||
| 102 | #define MX28_PAD_SSP3_SCK__SSP3_SCK MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0) | ||
| 103 | #define MX28_PAD_SSP3_MOSI__SSP3_CMD MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0) | ||
| 104 | #define MX28_PAD_SSP3_MISO__SSP3_D0 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0) | ||
| 105 | #define MX28_PAD_SSP3_SS0__SSP3_D3 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0) | ||
| 106 | |||
| 107 | #define MX28_PAD_AUART0_RX__AUART0_RX MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0) | ||
| 108 | #define MX28_PAD_AUART0_TX__AUART0_TX MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0) | ||
| 109 | #define MX28_PAD_AUART0_CTS__AUART0_CTS MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0) | ||
| 110 | #define MX28_PAD_AUART0_RTS__AUART0_RTS MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0) | ||
| 111 | #define MX28_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0) | ||
| 112 | #define MX28_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0) | ||
| 113 | #define MX28_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0) | ||
| 114 | #define MX28_PAD_AUART1_RTS__AUART1_RTS MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_0) | ||
| 115 | #define MX28_PAD_AUART2_RX__AUART2_RX MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_0) | ||
| 116 | #define MX28_PAD_AUART2_TX__AUART2_TX MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_0) | ||
| 117 | #define MX28_PAD_AUART2_CTS__AUART2_CTS MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0) | ||
| 118 | #define MX28_PAD_AUART2_RTS__AUART2_RTS MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0) | ||
| 119 | #define MX28_PAD_AUART3_RX__AUART3_RX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0) | ||
| 120 | #define MX28_PAD_AUART3_TX__AUART3_TX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0) | ||
| 121 | #define MX28_PAD_AUART3_CTS__AUART3_CTS MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0) | ||
| 122 | #define MX28_PAD_AUART3_RTS__AUART3_RTS MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0) | ||
| 123 | #define MX28_PAD_PWM0__PWM_0 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0) | ||
| 124 | #define MX28_PAD_PWM1__PWM_1 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0) | ||
| 125 | #define MX28_PAD_PWM2__PWM_2 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0) | ||
| 126 | #define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0) | ||
| 127 | #define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0) | ||
| 128 | #define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_0) | ||
| 129 | #define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_0) | ||
| 130 | #define MX28_PAD_I2C0_SCL__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_0) | ||
| 131 | #define MX28_PAD_I2C0_SDA__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_0) | ||
| 132 | #define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_0) | ||
| 133 | #define MX28_PAD_SPDIF__SPDIF_TX MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_0) | ||
| 134 | #define MX28_PAD_PWM3__PWM_3 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_0) | ||
| 135 | #define MX28_PAD_PWM4__PWM_4 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_0) | ||
| 136 | #define MX28_PAD_LCD_RESET__LCD_RESET MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_0) | ||
| 137 | |||
| 138 | #define MX28_PAD_ENET0_MDC__ENET0_MDC MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_0) | ||
| 139 | #define MX28_PAD_ENET0_MDIO__ENET0_MDIO MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_0) | ||
| 140 | #define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_0) | ||
| 141 | #define MX28_PAD_ENET0_RXD0__ENET0_RXD0 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_0) | ||
| 142 | #define MX28_PAD_ENET0_RXD1__ENET0_RXD1 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_0) | ||
| 143 | #define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_0) | ||
| 144 | #define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_0) | ||
| 145 | #define MX28_PAD_ENET0_TXD0__ENET0_TXD0 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_0) | ||
| 146 | #define MX28_PAD_ENET0_TXD1__ENET0_TXD1 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_0) | ||
| 147 | #define MX28_PAD_ENET0_RXD2__ENET0_RXD2 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_0) | ||
| 148 | #define MX28_PAD_ENET0_RXD3__ENET0_RXD3 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_0) | ||
| 149 | #define MX28_PAD_ENET0_TXD2__ENET0_TXD2 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_0) | ||
| 150 | #define MX28_PAD_ENET0_TXD3__ENET0_TXD3 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_0) | ||
| 151 | #define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_0) | ||
| 152 | #define MX28_PAD_ENET0_COL__ENET0_COL MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_0) | ||
| 153 | #define MX28_PAD_ENET0_CRS__ENET0_CRS MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_0) | ||
| 154 | #define MX28_PAD_ENET_CLK__CLKCTRL_ENET MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_0) | ||
| 155 | #define MX28_PAD_JTAG_RTCK__JTAG_RTCK MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_0) | ||
| 156 | |||
| 157 | #define MX28_PAD_EMI_D00__EMI_DATA0 MXS_IOMUX_PAD_NAKED(5, 0, PAD_MUXSEL_0) | ||
| 158 | #define MX28_PAD_EMI_D01__EMI_DATA1 MXS_IOMUX_PAD_NAKED(5, 1, PAD_MUXSEL_0) | ||
| 159 | #define MX28_PAD_EMI_D02__EMI_DATA2 MXS_IOMUX_PAD_NAKED(5, 2, PAD_MUXSEL_0) | ||
| 160 | #define MX28_PAD_EMI_D03__EMI_DATA3 MXS_IOMUX_PAD_NAKED(5, 3, PAD_MUXSEL_0) | ||
| 161 | #define MX28_PAD_EMI_D04__EMI_DATA4 MXS_IOMUX_PAD_NAKED(5, 4, PAD_MUXSEL_0) | ||
| 162 | #define MX28_PAD_EMI_D05__EMI_DATA5 MXS_IOMUX_PAD_NAKED(5, 5, PAD_MUXSEL_0) | ||
| 163 | #define MX28_PAD_EMI_D06__EMI_DATA6 MXS_IOMUX_PAD_NAKED(5, 6, PAD_MUXSEL_0) | ||
| 164 | #define MX28_PAD_EMI_D07__EMI_DATA7 MXS_IOMUX_PAD_NAKED(5, 7, PAD_MUXSEL_0) | ||
| 165 | #define MX28_PAD_EMI_D08__EMI_DATA8 MXS_IOMUX_PAD_NAKED(5, 8, PAD_MUXSEL_0) | ||
| 166 | #define MX28_PAD_EMI_D09__EMI_DATA9 MXS_IOMUX_PAD_NAKED(5, 9, PAD_MUXSEL_0) | ||
| 167 | #define MX28_PAD_EMI_D10__EMI_DATA10 MXS_IOMUX_PAD_NAKED(5, 10, PAD_MUXSEL_0) | ||
| 168 | #define MX28_PAD_EMI_D11__EMI_DATA11 MXS_IOMUX_PAD_NAKED(5, 11, PAD_MUXSEL_0) | ||
| 169 | #define MX28_PAD_EMI_D12__EMI_DATA12 MXS_IOMUX_PAD_NAKED(5, 12, PAD_MUXSEL_0) | ||
| 170 | #define MX28_PAD_EMI_D13__EMI_DATA13 MXS_IOMUX_PAD_NAKED(5, 13, PAD_MUXSEL_0) | ||
| 171 | #define MX28_PAD_EMI_D14__EMI_DATA14 MXS_IOMUX_PAD_NAKED(5, 14, PAD_MUXSEL_0) | ||
| 172 | #define MX28_PAD_EMI_D15__EMI_DATA15 MXS_IOMUX_PAD_NAKED(5, 15, PAD_MUXSEL_0) | ||
| 173 | #define MX28_PAD_EMI_ODT0__EMI_ODT0 MXS_IOMUX_PAD_NAKED(5, 16, PAD_MUXSEL_0) | ||
| 174 | #define MX28_PAD_EMI_DQM0__EMI_DQM0 MXS_IOMUX_PAD_NAKED(5, 17, PAD_MUXSEL_0) | ||
| 175 | #define MX28_PAD_EMI_ODT1__EMI_ODT1 MXS_IOMUX_PAD_NAKED(5, 18, PAD_MUXSEL_0) | ||
| 176 | #define MX28_PAD_EMI_DQM1__EMI_DQM1 MXS_IOMUX_PAD_NAKED(5, 19, PAD_MUXSEL_0) | ||
| 177 | #define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK MXS_IOMUX_PAD_NAKED(5, 20, PAD_MUXSEL_0) | ||
| 178 | #define MX28_PAD_EMI_CLK__EMI_CLK MXS_IOMUX_PAD_NAKED(5, 21, PAD_MUXSEL_0) | ||
| 179 | #define MX28_PAD_EMI_DQS0__EMI_DQS0 MXS_IOMUX_PAD_NAKED(5, 22, PAD_MUXSEL_0) | ||
| 180 | #define MX28_PAD_EMI_DQS1__EMI_DQS1 MXS_IOMUX_PAD_NAKED(5, 23, PAD_MUXSEL_0) | ||
| 181 | #define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN MXS_IOMUX_PAD_NAKED(5, 26, PAD_MUXSEL_0) | ||
| 182 | |||
| 183 | #define MX28_PAD_EMI_A00__EMI_ADDR0 MXS_IOMUX_PAD_NAKED(6, 0, PAD_MUXSEL_0) | ||
| 184 | #define MX28_PAD_EMI_A01__EMI_ADDR1 MXS_IOMUX_PAD_NAKED(6, 1, PAD_MUXSEL_0) | ||
| 185 | #define MX28_PAD_EMI_A02__EMI_ADDR2 MXS_IOMUX_PAD_NAKED(6, 2, PAD_MUXSEL_0) | ||
| 186 | #define MX28_PAD_EMI_A03__EMI_ADDR3 MXS_IOMUX_PAD_NAKED(6, 3, PAD_MUXSEL_0) | ||
| 187 | #define MX28_PAD_EMI_A04__EMI_ADDR4 MXS_IOMUX_PAD_NAKED(6, 4, PAD_MUXSEL_0) | ||
| 188 | #define MX28_PAD_EMI_A05__EMI_ADDR5 MXS_IOMUX_PAD_NAKED(6, 5, PAD_MUXSEL_0) | ||
| 189 | #define MX28_PAD_EMI_A06__EMI_ADDR6 MXS_IOMUX_PAD_NAKED(6, 6, PAD_MUXSEL_0) | ||
| 190 | #define MX28_PAD_EMI_A07__EMI_ADDR7 MXS_IOMUX_PAD_NAKED(6, 7, PAD_MUXSEL_0) | ||
| 191 | #define MX28_PAD_EMI_A08__EMI_ADDR8 MXS_IOMUX_PAD_NAKED(6, 8, PAD_MUXSEL_0) | ||
| 192 | #define MX28_PAD_EMI_A09__EMI_ADDR9 MXS_IOMUX_PAD_NAKED(6, 9, PAD_MUXSEL_0) | ||
| 193 | #define MX28_PAD_EMI_A10__EMI_ADDR10 MXS_IOMUX_PAD_NAKED(6, 10, PAD_MUXSEL_0) | ||
| 194 | #define MX28_PAD_EMI_A11__EMI_ADDR11 MXS_IOMUX_PAD_NAKED(6, 11, PAD_MUXSEL_0) | ||
| 195 | #define MX28_PAD_EMI_A12__EMI_ADDR12 MXS_IOMUX_PAD_NAKED(6, 12, PAD_MUXSEL_0) | ||
| 196 | #define MX28_PAD_EMI_A13__EMI_ADDR13 MXS_IOMUX_PAD_NAKED(6, 13, PAD_MUXSEL_0) | ||
| 197 | #define MX28_PAD_EMI_A14__EMI_ADDR14 MXS_IOMUX_PAD_NAKED(6, 14, PAD_MUXSEL_0) | ||
| 198 | #define MX28_PAD_EMI_BA0__EMI_BA0 MXS_IOMUX_PAD_NAKED(6, 16, PAD_MUXSEL_0) | ||
| 199 | #define MX28_PAD_EMI_BA1__EMI_BA1 MXS_IOMUX_PAD_NAKED(6, 17, PAD_MUXSEL_0) | ||
| 200 | #define MX28_PAD_EMI_BA2__EMI_BA2 MXS_IOMUX_PAD_NAKED(6, 18, PAD_MUXSEL_0) | ||
| 201 | #define MX28_PAD_EMI_CASN__EMI_CASN MXS_IOMUX_PAD_NAKED(6, 19, PAD_MUXSEL_0) | ||
| 202 | #define MX28_PAD_EMI_RASN__EMI_RASN MXS_IOMUX_PAD_NAKED(6, 20, PAD_MUXSEL_0) | ||
| 203 | #define MX28_PAD_EMI_WEN__EMI_WEN MXS_IOMUX_PAD_NAKED(6, 21, PAD_MUXSEL_0) | ||
| 204 | #define MX28_PAD_EMI_CE0N__EMI_CE0N MXS_IOMUX_PAD_NAKED(6, 22, PAD_MUXSEL_0) | ||
| 205 | #define MX28_PAD_EMI_CE1N__EMI_CE1N MXS_IOMUX_PAD_NAKED(6, 23, PAD_MUXSEL_0) | ||
| 206 | #define MX28_PAD_EMI_CKE__EMI_CKE MXS_IOMUX_PAD_NAKED(6, 24, PAD_MUXSEL_0) | ||
| 207 | |||
| 208 | /* MUXSEL_1 */ | ||
| 209 | #define MX28_PAD_GPMI_D00__SSP1_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_1) | ||
| 210 | #define MX28_PAD_GPMI_D01__SSP1_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_1) | ||
| 211 | #define MX28_PAD_GPMI_D02__SSP1_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_1) | ||
| 212 | #define MX28_PAD_GPMI_D03__SSP1_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_1) | ||
| 213 | #define MX28_PAD_GPMI_D04__SSP1_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_1) | ||
| 214 | #define MX28_PAD_GPMI_D05__SSP1_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_1) | ||
| 215 | #define MX28_PAD_GPMI_D06__SSP1_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_1) | ||
| 216 | #define MX28_PAD_GPMI_D07__SSP1_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_1) | ||
| 217 | #define MX28_PAD_GPMI_CE0N__SSP3_D0 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1) | ||
| 218 | #define MX28_PAD_GPMI_CE1N__SSP3_D3 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1) | ||
| 219 | #define MX28_PAD_GPMI_CE2N__CAN1_TX MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1) | ||
| 220 | #define MX28_PAD_GPMI_CE3N__CAN1_RX MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_1) | ||
| 221 | #define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_1) | ||
| 222 | #define MX28_PAD_GPMI_RDY1__SSP1_CMD MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_1) | ||
| 223 | #define MX28_PAD_GPMI_RDY2__CAN0_TX MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_1) | ||
| 224 | #define MX28_PAD_GPMI_RDY3__CAN0_RX MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_1) | ||
| 225 | #define MX28_PAD_GPMI_RDN__SSP3_SCK MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_1) | ||
| 226 | #define MX28_PAD_GPMI_WRN__SSP1_SCK MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_1) | ||
| 227 | #define MX28_PAD_GPMI_ALE__SSP3_D1 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_1) | ||
| 228 | #define MX28_PAD_GPMI_CLE__SSP3_D2 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1) | ||
| 229 | #define MX28_PAD_GPMI_RESETN__SSP3_CMD MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1) | ||
| 230 | |||
| 231 | #define MX28_PAD_LCD_D03__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_1) | ||
| 232 | #define MX28_PAD_LCD_D04__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_1) | ||
| 233 | #define MX28_PAD_LCD_D08__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_1) | ||
| 234 | #define MX28_PAD_LCD_D09__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_1) | ||
| 235 | #define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_1) | ||
| 236 | #define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_1) | ||
| 237 | #define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1) | ||
| 238 | #define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1) | ||
| 239 | #define MX28_PAD_LCD_RD_E__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1) | ||
| 240 | #define MX28_PAD_LCD_WR_RWN__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1) | ||
| 241 | #define MX28_PAD_LCD_RS__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1) | ||
| 242 | #define MX28_PAD_LCD_CS__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1) | ||
| 243 | #define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1) | ||
| 244 | #define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1) | ||
| 245 | #define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1) | ||
| 246 | |||
| 247 | #define MX28_PAD_SSP0_DATA4__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_1) | ||
| 248 | #define MX28_PAD_SSP0_DATA5__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_1) | ||
| 249 | #define MX28_PAD_SSP0_DATA6__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_1) | ||
| 250 | #define MX28_PAD_SSP0_DATA7__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_1) | ||
| 251 | #define MX28_PAD_SSP1_SCK__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_1) | ||
| 252 | #define MX28_PAD_SSP1_CMD__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_1) | ||
| 253 | #define MX28_PAD_SSP1_DATA0__SSP2_D6 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_1) | ||
| 254 | #define MX28_PAD_SSP1_DATA3__SSP2_D7 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_1) | ||
| 255 | #define MX28_PAD_SSP2_SCK__AUART2_RX MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_1) | ||
| 256 | #define MX28_PAD_SSP2_MOSI__AUART2_TX MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_1) | ||
| 257 | #define MX28_PAD_SSP2_MISO__AUART3_RX MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_1) | ||
| 258 | #define MX28_PAD_SSP2_SS0__AUART3_TX MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_1) | ||
| 259 | #define MX28_PAD_SSP2_SS1__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_1) | ||
| 260 | #define MX28_PAD_SSP2_SS2__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_1) | ||
| 261 | #define MX28_PAD_SSP3_SCK__AUART4_TX MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_1) | ||
| 262 | #define MX28_PAD_SSP3_MOSI__AUART4_RX MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_1) | ||
| 263 | #define MX28_PAD_SSP3_MISO__AUART4_RTS MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_1) | ||
| 264 | #define MX28_PAD_SSP3_SS0__AUART4_CTS MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_1) | ||
| 265 | |||
| 266 | #define MX28_PAD_AUART0_RX__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_1) | ||
| 267 | #define MX28_PAD_AUART0_TX__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_1) | ||
| 268 | #define MX28_PAD_AUART0_CTS__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_1) | ||
| 269 | #define MX28_PAD_AUART0_RTS__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_1) | ||
| 270 | #define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_1) | ||
| 271 | #define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_1) | ||
| 272 | #define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_1) | ||
| 273 | #define MX28_PAD_AUART1_RTS__USB0_ID MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_1) | ||
| 274 | #define MX28_PAD_AUART2_RX__SSP3_D1 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_1) | ||
| 275 | #define MX28_PAD_AUART2_TX__SSP3_D2 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_1) | ||
| 276 | #define MX28_PAD_AUART2_CTS__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_1) | ||
| 277 | #define MX28_PAD_AUART2_RTS__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_1) | ||
| 278 | #define MX28_PAD_AUART3_RX__CAN0_TX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_1) | ||
| 279 | #define MX28_PAD_AUART3_TX__CAN0_RX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_1) | ||
| 280 | #define MX28_PAD_AUART3_CTS__CAN1_TX MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_1) | ||
| 281 | #define MX28_PAD_AUART3_RTS__CAN1_RX MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_1) | ||
| 282 | #define MX28_PAD_PWM0__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_1) | ||
| 283 | #define MX28_PAD_PWM1__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_1) | ||
| 284 | #define MX28_PAD_PWM2__USB0_ID MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_1) | ||
| 285 | #define MX28_PAD_SAIF0_MCLK__PWM_3 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_1) | ||
| 286 | #define MX28_PAD_SAIF0_LRCLK__PWM_4 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_1) | ||
| 287 | #define MX28_PAD_SAIF0_BITCLK__PWM_5 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_1) | ||
| 288 | #define MX28_PAD_SAIF0_SDATA0__PWM_6 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_1) | ||
| 289 | #define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_1) | ||
| 290 | #define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_1) | ||
| 291 | #define MX28_PAD_SAIF1_SDATA0__PWM_7 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_1) | ||
| 292 | #define MX28_PAD_LCD_RESET__LCD_VSYNC MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_1) | ||
| 293 | |||
| 294 | #define MX28_PAD_ENET0_MDC__GPMI_CE4N MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_1) | ||
| 295 | #define MX28_PAD_ENET0_MDIO__GPMI_CE5N MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_1) | ||
| 296 | #define MX28_PAD_ENET0_RX_EN__GPMI_CE6N MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_1) | ||
| 297 | #define MX28_PAD_ENET0_RXD0__GPMI_CE7N MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_1) | ||
| 298 | #define MX28_PAD_ENET0_RXD1__GPMI_READY4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_1) | ||
| 299 | #define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_1) | ||
| 300 | #define MX28_PAD_ENET0_TX_EN__GPMI_READY5 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_1) | ||
| 301 | #define MX28_PAD_ENET0_TXD0__GPMI_READY6 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_1) | ||
| 302 | #define MX28_PAD_ENET0_TXD1__GPMI_READY7 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_1) | ||
| 303 | #define MX28_PAD_ENET0_RXD2__ENET1_RXD0 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_1) | ||
| 304 | #define MX28_PAD_ENET0_RXD3__ENET1_RXD1 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_1) | ||
| 305 | #define MX28_PAD_ENET0_TXD2__ENET1_TXD0 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_1) | ||
| 306 | #define MX28_PAD_ENET0_TXD3__ENET1_TXD1 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_1) | ||
| 307 | #define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_1) | ||
| 308 | #define MX28_PAD_ENET0_COL__ENET1_TX_EN MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_1) | ||
| 309 | #define MX28_PAD_ENET0_CRS__ENET1_RX_EN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_1) | ||
| 310 | |||
| 311 | /* MUXSEL_2 */ | ||
| 312 | #define MX28_PAD_GPMI_CE2N__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_2) | ||
| 313 | #define MX28_PAD_GPMI_CE3N__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2) | ||
| 314 | #define MX28_PAD_GPMI_RDY0__USB0_ID MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2) | ||
| 315 | #define MX28_PAD_GPMI_RDY2__ENET0_TX_ER MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_2) | ||
| 316 | #define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_2) | ||
| 317 | #define MX28_PAD_GPMI_ALE__SSP3_D4 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2) | ||
| 318 | #define MX28_PAD_GPMI_CLE__SSP3_D5 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2) | ||
| 319 | |||
| 320 | #define MX28_PAD_LCD_D00__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_2) | ||
| 321 | #define MX28_PAD_LCD_D01__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_2) | ||
| 322 | #define MX28_PAD_LCD_D02__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_2) | ||
| 323 | #define MX28_PAD_LCD_D03__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_2) | ||
| 324 | #define MX28_PAD_LCD_D04__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_2) | ||
| 325 | #define MX28_PAD_LCD_D05__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_2) | ||
| 326 | #define MX28_PAD_LCD_D06__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_2) | ||
| 327 | #define MX28_PAD_LCD_D07__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_2) | ||
| 328 | #define MX28_PAD_LCD_D08__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_2) | ||
| 329 | #define MX28_PAD_LCD_D09__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_2) | ||
| 330 | #define MX28_PAD_LCD_D10__ETM_DA10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2) | ||
| 331 | #define MX28_PAD_LCD_D11__ETM_DA11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2) | ||
| 332 | #define MX28_PAD_LCD_D12__ETM_DA12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2) | ||
| 333 | #define MX28_PAD_LCD_D13__ETM_DA13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2) | ||
| 334 | #define MX28_PAD_LCD_D14__ETM_DA14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2) | ||
| 335 | #define MX28_PAD_LCD_D15__ETM_DA15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2) | ||
| 336 | #define MX28_PAD_LCD_D16__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2) | ||
| 337 | #define MX28_PAD_LCD_D17__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_2) | ||
| 338 | #define MX28_PAD_LCD_D18__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2) | ||
| 339 | #define MX28_PAD_LCD_D19__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_2) | ||
| 340 | #define MX28_PAD_LCD_D20__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_2) | ||
| 341 | #define MX28_PAD_LCD_D21__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_2) | ||
| 342 | #define MX28_PAD_LCD_D22__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_2) | ||
| 343 | #define MX28_PAD_LCD_D23__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_2) | ||
| 344 | #define MX28_PAD_LCD_RD_E__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_2) | ||
| 345 | #define MX28_PAD_LCD_WR_RWN__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_2) | ||
| 346 | #define MX28_PAD_LCD_HSYNC__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2) | ||
| 347 | #define MX28_PAD_LCD_DOTCLK__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2) | ||
| 348 | |||
| 349 | #define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_2) | ||
| 350 | #define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_2) | ||
| 351 | #define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_2) | ||
| 352 | #define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_2) | ||
| 353 | #define MX28_PAD_SSP2_SCK__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_2) | ||
| 354 | #define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_2) | ||
| 355 | #define MX28_PAD_SSP2_MISO__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_2) | ||
| 356 | #define MX28_PAD_SSP2_SS0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_2) | ||
| 357 | #define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_2) | ||
| 358 | #define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_2) | ||
| 359 | #define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_2) | ||
| 360 | #define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_2) | ||
| 361 | #define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_2) | ||
| 362 | #define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_2) | ||
| 363 | |||
| 364 | #define MX28_PAD_AUART0_RX__DUART_CTS MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_2) | ||
| 365 | #define MX28_PAD_AUART0_TX__DUART_RTS MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_2) | ||
| 366 | #define MX28_PAD_AUART0_CTS__DUART_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_2) | ||
| 367 | #define MX28_PAD_AUART0_RTS__DUART_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_2) | ||
| 368 | #define MX28_PAD_AUART1_RX__PWM_0 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_2) | ||
| 369 | #define MX28_PAD_AUART1_TX__PWM_1 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_2) | ||
| 370 | #define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_2) | ||
| 371 | #define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_2) | ||
| 372 | #define MX28_PAD_AUART2_RX__SSP3_D4 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_2) | ||
| 373 | #define MX28_PAD_AUART2_TX__SSP3_D5 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_2) | ||
| 374 | #define MX28_PAD_AUART2_CTS__SAIF1_BITCLK MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_2) | ||
| 375 | #define MX28_PAD_AUART2_RTS__SAIF1_LRCLK MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_2) | ||
| 376 | #define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_2) | ||
| 377 | #define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_2) | ||
| 378 | #define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_2) | ||
| 379 | #define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_2) | ||
| 380 | #define MX28_PAD_PWM0__DUART_RX MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_2) | ||
| 381 | #define MX28_PAD_PWM1__DUART_TX MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_2) | ||
| 382 | #define MX28_PAD_PWM2__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_2) | ||
| 383 | #define MX28_PAD_SAIF0_MCLK__AUART4_CTS MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_2) | ||
| 384 | #define MX28_PAD_SAIF0_LRCLK__AUART4_RTS MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_2) | ||
| 385 | #define MX28_PAD_SAIF0_BITCLK__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_2) | ||
| 386 | #define MX28_PAD_SAIF0_SDATA0__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_2) | ||
| 387 | #define MX28_PAD_I2C0_SCL__DUART_RX MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_2) | ||
| 388 | #define MX28_PAD_I2C0_SDA__DUART_TX MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_2) | ||
| 389 | #define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_2) | ||
| 390 | #define MX28_PAD_SPDIF__ENET1_RX_ER MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_2) | ||
| 391 | |||
| 392 | #define MX28_PAD_ENET0_MDC__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_2) | ||
| 393 | #define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_2) | ||
| 394 | #define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_2) | ||
| 395 | #define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_2) | ||
| 396 | #define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_2) | ||
| 397 | #define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_2) | ||
| 398 | #define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_2) | ||
| 399 | #define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_2) | ||
| 400 | #define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_2) | ||
| 401 | #define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_2) | ||
| 402 | #define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_2) | ||
| 403 | #define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_2) | ||
| 404 | |||
| 405 | /* MUXSEL_GPIO */ | ||
| 406 | #define MX28_PAD_GPMI_D00__GPIO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO) | ||
| 407 | #define MX28_PAD_GPMI_D01__GPIO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO) | ||
| 408 | #define MX28_PAD_GPMI_D02__GPIO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO) | ||
| 409 | #define MX28_PAD_GPMI_D03__GPIO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO) | ||
| 410 | #define MX28_PAD_GPMI_D04__GPIO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO) | ||
| 411 | #define MX28_PAD_GPMI_D05__GPIO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO) | ||
| 412 | #define MX28_PAD_GPMI_D06__GPIO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO) | ||
| 413 | #define MX28_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO) | ||
| 414 | #define MX28_PAD_GPMI_CE0N__GPIO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO) | ||
| 415 | #define MX28_PAD_GPMI_CE1N__GPIO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO) | ||
| 416 | #define MX28_PAD_GPMI_CE2N__GPIO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO) | ||
| 417 | #define MX28_PAD_GPMI_CE3N__GPIO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO) | ||
| 418 | #define MX28_PAD_GPMI_RDY0__GPIO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO) | ||
| 419 | #define MX28_PAD_GPMI_RDY1__GPIO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO) | ||
| 420 | #define MX28_PAD_GPMI_RDY2__GPIO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO) | ||
| 421 | #define MX28_PAD_GPMI_RDY3__GPIO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO) | ||
| 422 | #define MX28_PAD_GPMI_RDN__GPIO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO) | ||
| 423 | #define MX28_PAD_GPMI_WRN__GPIO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO) | ||
| 424 | #define MX28_PAD_GPMI_ALE__GPIO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO) | ||
| 425 | #define MX28_PAD_GPMI_CLE__GPIO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO) | ||
| 426 | #define MX28_PAD_GPMI_RESETN__GPIO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO) | ||
| 427 | |||
| 428 | #define MX28_PAD_LCD_D00__GPIO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO) | ||
| 429 | #define MX28_PAD_LCD_D01__GPIO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO) | ||
| 430 | #define MX28_PAD_LCD_D02__GPIO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO) | ||
| 431 | #define MX28_PAD_LCD_D03__GPIO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO) | ||
| 432 | #define MX28_PAD_LCD_D04__GPIO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO) | ||
| 433 | #define MX28_PAD_LCD_D05__GPIO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO) | ||
| 434 | #define MX28_PAD_LCD_D06__GPIO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO) | ||
| 435 | #define MX28_PAD_LCD_D07__GPIO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO) | ||
| 436 | #define MX28_PAD_LCD_D08__GPIO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO) | ||
| 437 | #define MX28_PAD_LCD_D09__GPIO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO) | ||
| 438 | #define MX28_PAD_LCD_D10__GPIO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO) | ||
| 439 | #define MX28_PAD_LCD_D11__GPIO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO) | ||
| 440 | #define MX28_PAD_LCD_D12__GPIO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO) | ||
| 441 | #define MX28_PAD_LCD_D13__GPIO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO) | ||
| 442 | #define MX28_PAD_LCD_D14__GPIO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO) | ||
| 443 | #define MX28_PAD_LCD_D15__GPIO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO) | ||
| 444 | #define MX28_PAD_LCD_D16__GPIO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO) | ||
| 445 | #define MX28_PAD_LCD_D17__GPIO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO) | ||
| 446 | #define MX28_PAD_LCD_D18__GPIO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO) | ||
| 447 | #define MX28_PAD_LCD_D19__GPIO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO) | ||
| 448 | #define MX28_PAD_LCD_D20__GPIO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO) | ||
| 449 | #define MX28_PAD_LCD_D21__GPIO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO) | ||
| 450 | #define MX28_PAD_LCD_D22__GPIO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO) | ||
| 451 | #define MX28_PAD_LCD_D23__GPIO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO) | ||
| 452 | #define MX28_PAD_LCD_RD_E__GPIO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO) | ||
| 453 | #define MX28_PAD_LCD_WR_RWN__GPIO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO) | ||
| 454 | #define MX28_PAD_LCD_RS__GPIO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO) | ||
| 455 | #define MX28_PAD_LCD_CS__GPIO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO) | ||
| 456 | #define MX28_PAD_LCD_VSYNC__GPIO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO) | ||
| 457 | #define MX28_PAD_LCD_HSYNC__GPIO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO) | ||
| 458 | #define MX28_PAD_LCD_DOTCLK__GPIO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO) | ||
| 459 | #define MX28_PAD_LCD_ENABLE__GPIO_1_31 MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_GPIO) | ||
| 460 | |||
| 461 | #define MX28_PAD_SSP0_DATA0__GPIO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO) | ||
| 462 | #define MX28_PAD_SSP0_DATA1__GPIO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO) | ||
| 463 | #define MX28_PAD_SSP0_DATA2__GPIO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO) | ||
| 464 | #define MX28_PAD_SSP0_DATA3__GPIO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO) | ||
| 465 | #define MX28_PAD_SSP0_DATA4__GPIO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO) | ||
| 466 | #define MX28_PAD_SSP0_DATA5__GPIO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO) | ||
| 467 | #define MX28_PAD_SSP0_DATA6__GPIO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO) | ||
| 468 | #define MX28_PAD_SSP0_DATA7__GPIO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO) | ||
| 469 | #define MX28_PAD_SSP0_CMD__GPIO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO) | ||
| 470 | #define MX28_PAD_SSP0_DETECT__GPIO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO) | ||
| 471 | #define MX28_PAD_SSP0_SCK__GPIO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO) | ||
| 472 | #define MX28_PAD_SSP1_SCK__GPIO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO) | ||
| 473 | #define MX28_PAD_SSP1_CMD__GPIO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO) | ||
| 474 | #define MX28_PAD_SSP1_DATA0__GPIO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO) | ||
| 475 | #define MX28_PAD_SSP1_DATA3__GPIO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO) | ||
| 476 | #define MX28_PAD_SSP2_SCK__GPIO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO) | ||
| 477 | #define MX28_PAD_SSP2_MOSI__GPIO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO) | ||
| 478 | #define MX28_PAD_SSP2_MISO__GPIO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO) | ||
| 479 | #define MX28_PAD_SSP2_SS0__GPIO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO) | ||
| 480 | #define MX28_PAD_SSP2_SS1__GPIO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO) | ||
| 481 | #define MX28_PAD_SSP2_SS2__GPIO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO) | ||
| 482 | #define MX28_PAD_SSP3_SCK__GPIO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO) | ||
| 483 | #define MX28_PAD_SSP3_MOSI__GPIO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO) | ||
| 484 | #define MX28_PAD_SSP3_MISO__GPIO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO) | ||
| 485 | #define MX28_PAD_SSP3_SS0__GPIO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO) | ||
| 486 | |||
| 487 | #define MX28_PAD_AUART0_RX__GPIO_3_0 MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_GPIO) | ||
| 488 | #define MX28_PAD_AUART0_TX__GPIO_3_1 MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_GPIO) | ||
| 489 | #define MX28_PAD_AUART0_CTS__GPIO_3_2 MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_GPIO) | ||
| 490 | #define MX28_PAD_AUART0_RTS__GPIO_3_3 MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_GPIO) | ||
| 491 | #define MX28_PAD_AUART1_RX__GPIO_3_4 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_GPIO) | ||
| 492 | #define MX28_PAD_AUART1_TX__GPIO_3_5 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_GPIO) | ||
| 493 | #define MX28_PAD_AUART1_CTS__GPIO_3_6 MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_GPIO) | ||
| 494 | #define MX28_PAD_AUART1_RTS__GPIO_3_7 MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_GPIO) | ||
| 495 | #define MX28_PAD_AUART2_RX__GPIO_3_8 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_GPIO) | ||
| 496 | #define MX28_PAD_AUART2_TX__GPIO_3_9 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_GPIO) | ||
| 497 | #define MX28_PAD_AUART2_CTS__GPIO_3_10 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_GPIO) | ||
| 498 | #define MX28_PAD_AUART2_RTS__GPIO_3_11 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_GPIO) | ||
| 499 | #define MX28_PAD_AUART3_RX__GPIO_3_12 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_GPIO) | ||
| 500 | #define MX28_PAD_AUART3_TX__GPIO_3_13 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_GPIO) | ||
| 501 | #define MX28_PAD_AUART3_CTS__GPIO_3_14 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_GPIO) | ||
| 502 | #define MX28_PAD_AUART3_RTS__GPIO_3_15 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_GPIO) | ||
| 503 | #define MX28_PAD_PWM0__GPIO_3_16 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_GPIO) | ||
| 504 | #define MX28_PAD_PWM1__GPIO_3_17 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_GPIO) | ||
| 505 | #define MX28_PAD_PWM2__GPIO_3_18 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_GPIO) | ||
| 506 | #define MX28_PAD_SAIF0_MCLK__GPIO_3_20 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_GPIO) | ||
| 507 | #define MX28_PAD_SAIF0_LRCLK__GPIO_3_21 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_GPIO) | ||
| 508 | #define MX28_PAD_SAIF0_BITCLK__GPIO_3_22 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_GPIO) | ||
| 509 | #define MX28_PAD_SAIF0_SDATA0__GPIO_3_23 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_GPIO) | ||
| 510 | #define MX28_PAD_I2C0_SCL__GPIO_3_24 MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_GPIO) | ||
| 511 | #define MX28_PAD_I2C0_SDA__GPIO_3_25 MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_GPIO) | ||
| 512 | #define MX28_PAD_SAIF1_SDATA0__GPIO_3_26 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_GPIO) | ||
| 513 | #define MX28_PAD_SPDIF__GPIO_3_27 MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_GPIO) | ||
| 514 | #define MX28_PAD_PWM3__GPIO_3_28 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_GPIO) | ||
| 515 | #define MX28_PAD_PWM4__GPIO_3_29 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_GPIO) | ||
| 516 | #define MX28_PAD_LCD_RESET__GPIO_3_30 MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_GPIO) | ||
| 517 | |||
| 518 | #define MX28_PAD_ENET0_MDC__GPIO_4_0 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_GPIO) | ||
| 519 | #define MX28_PAD_ENET0_MDIO__GPIO_4_1 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_GPIO) | ||
| 520 | #define MX28_PAD_ENET0_RX_EN__GPIO_4_2 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_GPIO) | ||
| 521 | #define MX28_PAD_ENET0_RXD0__GPIO_4_3 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_GPIO) | ||
| 522 | #define MX28_PAD_ENET0_RXD1__GPIO_4_4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_GPIO) | ||
| 523 | #define MX28_PAD_ENET0_TX_CLK__GPIO_4_5 MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_GPIO) | ||
| 524 | #define MX28_PAD_ENET0_TX_EN__GPIO_4_6 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_GPIO) | ||
| 525 | #define MX28_PAD_ENET0_TXD0__GPIO_4_7 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_GPIO) | ||
| 526 | #define MX28_PAD_ENET0_TXD1__GPIO_4_8 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_GPIO) | ||
| 527 | #define MX28_PAD_ENET0_RXD2__GPIO_4_9 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_GPIO) | ||
| 528 | #define MX28_PAD_ENET0_RXD3__GPIO_4_10 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_GPIO) | ||
| 529 | #define MX28_PAD_ENET0_TXD2__GPIO_4_11 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_GPIO) | ||
| 530 | #define MX28_PAD_ENET0_TXD3__GPIO_4_12 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_GPIO) | ||
| 531 | #define MX28_PAD_ENET0_RX_CLK__GPIO_4_13 MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_GPIO) | ||
| 532 | #define MX28_PAD_ENET0_COL__GPIO_4_14 MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_GPIO) | ||
| 533 | #define MX28_PAD_ENET0_CRS__GPIO_4_15 MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_GPIO) | ||
| 534 | #define MX28_PAD_ENET_CLK__GPIO_4_16 MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_GPIO) | ||
| 535 | #define MX28_PAD_JTAG_RTCK__GPIO_4_20 MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_GPIO) | ||
| 536 | |||
| 537 | #endif /* __MACH_IOMUX_MX28_H__ */ | ||
diff --git a/arch/arm/mach-mxs/include/mach/iomux.h b/arch/arm/mach-mxs/include/mach/iomux.h deleted file mode 100644 index 7abdf58b8bb7..000000000000 --- a/arch/arm/mach-mxs/include/mach/iomux.h +++ /dev/null | |||
| @@ -1,168 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, | ||
| 3 | * <armlinux@phytec.de> | ||
| 4 | * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public License | ||
| 8 | * as published by the Free Software Foundation; either version 2 | ||
| 9 | * of the License, or (at your option) any later version. | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 18 | * MA 02110-1301, USA. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __MACH_MXS_IOMUX_H__ | ||
| 22 | #define __MACH_MXS_IOMUX_H__ | ||
| 23 | |||
| 24 | /* | ||
| 25 | * IOMUX/PAD Bit field definitions | ||
| 26 | * | ||
| 27 | * PAD_BANK: 0..2 (3) | ||
| 28 | * PAD_PIN: 3..7 (5) | ||
| 29 | * PAD_MUXSEL: 8..9 (2) | ||
| 30 | * PAD_MA: 10..11 (2) | ||
| 31 | * PAD_MA_VALID: 12 (1) | ||
| 32 | * PAD_VOL: 13 (1) | ||
| 33 | * PAD_VOL_VALID: 14 (1) | ||
| 34 | * PAD_PULL: 15 (1) | ||
| 35 | * PAD_PULL_VALID: 16 (1) | ||
| 36 | * RESERVED: 17..31 (15) | ||
| 37 | */ | ||
| 38 | typedef u32 iomux_cfg_t; | ||
| 39 | |||
| 40 | #define MXS_PAD_BANK_SHIFT 0 | ||
| 41 | #define MXS_PAD_BANK_MASK ((iomux_cfg_t)0x7 << MXS_PAD_BANK_SHIFT) | ||
| 42 | #define MXS_PAD_PIN_SHIFT 3 | ||
| 43 | #define MXS_PAD_PIN_MASK ((iomux_cfg_t)0x1f << MXS_PAD_PIN_SHIFT) | ||
| 44 | #define MXS_PAD_MUXSEL_SHIFT 8 | ||
| 45 | #define MXS_PAD_MUXSEL_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MUXSEL_SHIFT) | ||
| 46 | #define MXS_PAD_MA_SHIFT 10 | ||
| 47 | #define MXS_PAD_MA_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MA_SHIFT) | ||
| 48 | #define MXS_PAD_MA_VALID_SHIFT 12 | ||
| 49 | #define MXS_PAD_MA_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_MA_VALID_SHIFT) | ||
| 50 | #define MXS_PAD_VOL_SHIFT 13 | ||
| 51 | #define MXS_PAD_VOL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_SHIFT) | ||
| 52 | #define MXS_PAD_VOL_VALID_SHIFT 14 | ||
| 53 | #define MXS_PAD_VOL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_VALID_SHIFT) | ||
| 54 | #define MXS_PAD_PULL_SHIFT 15 | ||
| 55 | #define MXS_PAD_PULL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_SHIFT) | ||
| 56 | #define MXS_PAD_PULL_VALID_SHIFT 16 | ||
| 57 | #define MXS_PAD_PULL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_VALID_SHIFT) | ||
| 58 | |||
| 59 | #define PAD_MUXSEL_0 0 | ||
| 60 | #define PAD_MUXSEL_1 1 | ||
| 61 | #define PAD_MUXSEL_2 2 | ||
| 62 | #define PAD_MUXSEL_GPIO 3 | ||
| 63 | |||
| 64 | #define PAD_4MA 0 | ||
| 65 | #define PAD_8MA 1 | ||
| 66 | #define PAD_12MA 2 | ||
| 67 | #define PAD_16MA 3 | ||
| 68 | |||
| 69 | #define PAD_1V8 0 | ||
| 70 | #define PAD_3V3 1 | ||
| 71 | |||
| 72 | #define PAD_NOPULL 0 | ||
| 73 | #define PAD_PULLUP 1 | ||
| 74 | |||
| 75 | #define MXS_PAD_4MA ((PAD_4MA << MXS_PAD_MA_SHIFT) | \ | ||
| 76 | MXS_PAD_MA_VALID_MASK) | ||
| 77 | #define MXS_PAD_8MA ((PAD_8MA << MXS_PAD_MA_SHIFT) | \ | ||
| 78 | MXS_PAD_MA_VALID_MASK) | ||
| 79 | #define MXS_PAD_12MA ((PAD_12MA << MXS_PAD_MA_SHIFT) | \ | ||
| 80 | MXS_PAD_MA_VALID_MASK) | ||
| 81 | #define MXS_PAD_16MA ((PAD_16MA << MXS_PAD_MA_SHIFT) | \ | ||
| 82 | MXS_PAD_MA_VALID_MASK) | ||
| 83 | |||
| 84 | #define MXS_PAD_1V8 ((PAD_1V8 << MXS_PAD_VOL_SHIFT) | \ | ||
| 85 | MXS_PAD_VOL_VALID_MASK) | ||
| 86 | #define MXS_PAD_3V3 ((PAD_3V3 << MXS_PAD_VOL_SHIFT) | \ | ||
| 87 | MXS_PAD_VOL_VALID_MASK) | ||
| 88 | |||
| 89 | #define MXS_PAD_NOPULL ((PAD_NOPULL << MXS_PAD_PULL_SHIFT) | \ | ||
| 90 | MXS_PAD_PULL_VALID_MASK) | ||
| 91 | #define MXS_PAD_PULLUP ((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \ | ||
| 92 | MXS_PAD_PULL_VALID_MASK) | ||
| 93 | |||
| 94 | /* generic pad control used in most cases */ | ||
| 95 | #define MXS_PAD_CTRL (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL) | ||
| 96 | |||
| 97 | #define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull) \ | ||
| 98 | (((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) | \ | ||
| 99 | ((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) | \ | ||
| 100 | ((iomux_cfg_t)(_muxsel) << MXS_PAD_MUXSEL_SHIFT) | \ | ||
| 101 | ((iomux_cfg_t)(_ma) << MXS_PAD_MA_SHIFT) | \ | ||
| 102 | ((iomux_cfg_t)(_vol) << MXS_PAD_VOL_SHIFT) | \ | ||
| 103 | ((iomux_cfg_t)(_pull) << MXS_PAD_PULL_SHIFT)) | ||
| 104 | |||
| 105 | /* | ||
| 106 | * A pad becomes naked, when none of mA, vol or pull | ||
| 107 | * validity bits is set. | ||
| 108 | */ | ||
| 109 | #define MXS_IOMUX_PAD_NAKED(_bank, _pin, _muxsel) \ | ||
| 110 | MXS_IOMUX_PAD(_bank, _pin, _muxsel, 0, 0, 0) | ||
| 111 | |||
| 112 | static inline unsigned int PAD_BANK(iomux_cfg_t pad) | ||
| 113 | { | ||
| 114 | return (pad & MXS_PAD_BANK_MASK) >> MXS_PAD_BANK_SHIFT; | ||
| 115 | } | ||
| 116 | |||
| 117 | static inline unsigned int PAD_PIN(iomux_cfg_t pad) | ||
| 118 | { | ||
| 119 | return (pad & MXS_PAD_PIN_MASK) >> MXS_PAD_PIN_SHIFT; | ||
| 120 | } | ||
| 121 | |||
| 122 | static inline unsigned int PAD_MUXSEL(iomux_cfg_t pad) | ||
| 123 | { | ||
| 124 | return (pad & MXS_PAD_MUXSEL_MASK) >> MXS_PAD_MUXSEL_SHIFT; | ||
| 125 | } | ||
| 126 | |||
| 127 | static inline unsigned int PAD_MA(iomux_cfg_t pad) | ||
| 128 | { | ||
| 129 | return (pad & MXS_PAD_MA_MASK) >> MXS_PAD_MA_SHIFT; | ||
| 130 | } | ||
| 131 | |||
| 132 | static inline unsigned int PAD_MA_VALID(iomux_cfg_t pad) | ||
| 133 | { | ||
| 134 | return (pad & MXS_PAD_MA_VALID_MASK) >> MXS_PAD_MA_VALID_SHIFT; | ||
| 135 | } | ||
| 136 | |||
| 137 | static inline unsigned int PAD_VOL(iomux_cfg_t pad) | ||
| 138 | { | ||
| 139 | return (pad & MXS_PAD_VOL_MASK) >> MXS_PAD_VOL_SHIFT; | ||
| 140 | } | ||
| 141 | |||
| 142 | static inline unsigned int PAD_VOL_VALID(iomux_cfg_t pad) | ||
| 143 | { | ||
| 144 | return (pad & MXS_PAD_VOL_VALID_MASK) >> MXS_PAD_VOL_VALID_SHIFT; | ||
| 145 | } | ||
| 146 | |||
| 147 | static inline unsigned int PAD_PULL(iomux_cfg_t pad) | ||
| 148 | { | ||
| 149 | return (pad & MXS_PAD_PULL_MASK) >> MXS_PAD_PULL_SHIFT; | ||
| 150 | } | ||
| 151 | |||
| 152 | static inline unsigned int PAD_PULL_VALID(iomux_cfg_t pad) | ||
| 153 | { | ||
| 154 | return (pad & MXS_PAD_PULL_VALID_MASK) >> MXS_PAD_PULL_VALID_SHIFT; | ||
| 155 | } | ||
| 156 | |||
| 157 | /* | ||
| 158 | * configures a single pad in the iomuxer | ||
| 159 | */ | ||
| 160 | int mxs_iomux_setup_pad(iomux_cfg_t pad); | ||
| 161 | |||
| 162 | /* | ||
| 163 | * configures multiple pads | ||
| 164 | * convenient way to call the above function with tables | ||
| 165 | */ | ||
| 166 | int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count); | ||
| 167 | |||
| 168 | #endif /* __MACH_MXS_IOMUX_H__*/ | ||
diff --git a/arch/arm/mach-mxs/iomux.c b/arch/arm/mach-mxs/iomux.c deleted file mode 100644 index 0e804e2f11f4..000000000000 --- a/arch/arm/mach-mxs/iomux.c +++ /dev/null | |||
| @@ -1,101 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2004-2006,2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> | ||
| 4 | * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, | ||
| 5 | * <armlinux@phytec.de> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or | ||
| 8 | * modify it under the terms of the GNU General Public License | ||
| 9 | * as published by the Free Software Foundation; either version 2 | ||
| 10 | * of the License, or (at your option) any later version. | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 19 | * MA 02110-1301, USA. | ||
| 20 | */ | ||
| 21 | |||
| 22 | #include <linux/errno.h> | ||
| 23 | #include <linux/init.h> | ||
| 24 | #include <linux/kernel.h> | ||
| 25 | #include <linux/module.h> | ||
| 26 | #include <linux/string.h> | ||
| 27 | #include <linux/gpio.h> | ||
| 28 | |||
| 29 | #include <asm/mach/map.h> | ||
| 30 | |||
| 31 | #include <mach/mxs.h> | ||
| 32 | #include <mach/iomux.h> | ||
| 33 | |||
| 34 | /* | ||
| 35 | * configures a single pad in the iomuxer | ||
| 36 | */ | ||
| 37 | int mxs_iomux_setup_pad(iomux_cfg_t pad) | ||
| 38 | { | ||
| 39 | u32 reg, ofs, bp, bm; | ||
| 40 | void __iomem *iomux_base = MXS_IO_ADDRESS(MXS_PINCTRL_BASE_ADDR); | ||
| 41 | |||
| 42 | /* muxsel */ | ||
| 43 | ofs = 0x100; | ||
| 44 | ofs += PAD_BANK(pad) * 0x20 + PAD_PIN(pad) / 16 * 0x10; | ||
| 45 | bp = PAD_PIN(pad) % 16 * 2; | ||
| 46 | bm = 0x3 << bp; | ||
| 47 | reg = __raw_readl(iomux_base + ofs); | ||
| 48 | reg &= ~bm; | ||
| 49 | reg |= PAD_MUXSEL(pad) << bp; | ||
| 50 | __raw_writel(reg, iomux_base + ofs); | ||
| 51 | |||
| 52 | /* drive */ | ||
| 53 | ofs = cpu_is_mx23() ? 0x200 : 0x300; | ||
| 54 | ofs += PAD_BANK(pad) * 0x40 + PAD_PIN(pad) / 8 * 0x10; | ||
| 55 | /* mA */ | ||
| 56 | if (PAD_MA_VALID(pad)) { | ||
| 57 | bp = PAD_PIN(pad) % 8 * 4; | ||
| 58 | bm = 0x3 << bp; | ||
| 59 | reg = __raw_readl(iomux_base + ofs); | ||
| 60 | reg &= ~bm; | ||
| 61 | reg |= PAD_MA(pad) << bp; | ||
| 62 | __raw_writel(reg, iomux_base + ofs); | ||
| 63 | } | ||
| 64 | /* vol */ | ||
| 65 | if (PAD_VOL_VALID(pad)) { | ||
| 66 | bp = PAD_PIN(pad) % 8 * 4 + 2; | ||
| 67 | if (PAD_VOL(pad)) | ||
| 68 | __mxs_setl(1 << bp, iomux_base + ofs); | ||
| 69 | else | ||
| 70 | __mxs_clrl(1 << bp, iomux_base + ofs); | ||
| 71 | } | ||
| 72 | |||
| 73 | /* pull */ | ||
| 74 | if (PAD_PULL_VALID(pad)) { | ||
| 75 | ofs = cpu_is_mx23() ? 0x400 : 0x600; | ||
| 76 | ofs += PAD_BANK(pad) * 0x10; | ||
| 77 | bp = PAD_PIN(pad); | ||
| 78 | if (PAD_PULL(pad)) | ||
| 79 | __mxs_setl(1 << bp, iomux_base + ofs); | ||
| 80 | else | ||
| 81 | __mxs_clrl(1 << bp, iomux_base + ofs); | ||
| 82 | } | ||
| 83 | |||
| 84 | return 0; | ||
| 85 | } | ||
| 86 | |||
| 87 | int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count) | ||
| 88 | { | ||
| 89 | const iomux_cfg_t *p = pad_list; | ||
| 90 | int i; | ||
| 91 | int ret; | ||
| 92 | |||
| 93 | for (i = 0; i < count; i++) { | ||
| 94 | ret = mxs_iomux_setup_pad(*p); | ||
| 95 | if (ret) | ||
| 96 | return ret; | ||
| 97 | p++; | ||
| 98 | } | ||
| 99 | |||
| 100 | return 0; | ||
| 101 | } | ||
diff --git a/arch/arm/mach-mxs/mach-apx4devkit.c b/arch/arm/mach-mxs/mach-apx4devkit.c deleted file mode 100644 index f5f061757deb..000000000000 --- a/arch/arm/mach-mxs/mach-apx4devkit.c +++ /dev/null | |||
| @@ -1,273 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2011-2012 | ||
| 3 | * Lauri Hintsala, Bluegiga, <lauri.hintsala@bluegiga.com> | ||
| 4 | * Veli-Pekka Peltola, Bluegiga, <veli-pekka.peltola@bluegiga.com> | ||
| 5 | * | ||
| 6 | * based on: mach-mx28evk.c | ||
| 7 | * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | * | ||
| 14 | * This program is distributed in the hope that it will be useful, | ||
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 17 | * GNU General Public License for more details. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #include <linux/delay.h> | ||
| 21 | #include <linux/platform_device.h> | ||
| 22 | #include <linux/gpio.h> | ||
| 23 | #include <linux/leds.h> | ||
| 24 | #include <linux/clk.h> | ||
| 25 | #include <linux/i2c.h> | ||
| 26 | #include <linux/regulator/machine.h> | ||
| 27 | #include <linux/regulator/fixed.h> | ||
| 28 | #include <linux/micrel_phy.h> | ||
| 29 | |||
| 30 | #include <asm/mach-types.h> | ||
| 31 | #include <asm/mach/arch.h> | ||
| 32 | #include <asm/mach/time.h> | ||
| 33 | |||
| 34 | #include <mach/common.h> | ||
| 35 | #include <mach/digctl.h> | ||
| 36 | #include <mach/iomux-mx28.h> | ||
| 37 | |||
| 38 | #include "devices-mx28.h" | ||
| 39 | |||
| 40 | #define APX4DEVKIT_GPIO_USERLED MXS_GPIO_NR(3, 28) | ||
| 41 | |||
| 42 | static const iomux_cfg_t apx4devkit_pads[] __initconst = { | ||
| 43 | /* duart */ | ||
| 44 | MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL, | ||
| 45 | MX28_PAD_PWM1__DUART_TX | MXS_PAD_CTRL, | ||
| 46 | |||
| 47 | /* auart0 */ | ||
| 48 | MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL, | ||
| 49 | MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL, | ||
| 50 | MX28_PAD_AUART0_CTS__AUART0_CTS | MXS_PAD_CTRL, | ||
| 51 | MX28_PAD_AUART0_RTS__AUART0_RTS | MXS_PAD_CTRL, | ||
| 52 | |||
| 53 | /* auart1 */ | ||
| 54 | MX28_PAD_AUART1_RX__AUART1_RX | MXS_PAD_CTRL, | ||
| 55 | MX28_PAD_AUART1_TX__AUART1_TX | MXS_PAD_CTRL, | ||
| 56 | |||
| 57 | /* auart2 */ | ||
| 58 | MX28_PAD_SSP2_SCK__AUART2_RX | MXS_PAD_CTRL, | ||
| 59 | MX28_PAD_SSP2_MOSI__AUART2_TX | MXS_PAD_CTRL, | ||
| 60 | |||
| 61 | /* auart3 */ | ||
| 62 | MX28_PAD_SSP2_MISO__AUART3_RX | MXS_PAD_CTRL, | ||
| 63 | MX28_PAD_SSP2_SS0__AUART3_TX | MXS_PAD_CTRL, | ||
| 64 | |||
| 65 | #define MXS_PAD_FEC (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP) | ||
| 66 | /* fec0 */ | ||
| 67 | MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC, | ||
| 68 | MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC, | ||
| 69 | MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC, | ||
| 70 | MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC, | ||
| 71 | MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC, | ||
| 72 | MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC, | ||
| 73 | MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC, | ||
| 74 | MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC, | ||
| 75 | MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC, | ||
| 76 | |||
| 77 | /* i2c */ | ||
| 78 | MX28_PAD_I2C0_SCL__I2C0_SCL, | ||
| 79 | MX28_PAD_I2C0_SDA__I2C0_SDA, | ||
| 80 | |||
| 81 | /* mmc0 */ | ||
| 82 | MX28_PAD_SSP0_DATA0__SSP0_D0 | | ||
| 83 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 84 | MX28_PAD_SSP0_DATA1__SSP0_D1 | | ||
| 85 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 86 | MX28_PAD_SSP0_DATA2__SSP0_D2 | | ||
| 87 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 88 | MX28_PAD_SSP0_DATA3__SSP0_D3 | | ||
| 89 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 90 | MX28_PAD_SSP0_DATA4__SSP0_D4 | | ||
| 91 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 92 | MX28_PAD_SSP0_DATA5__SSP0_D5 | | ||
| 93 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 94 | MX28_PAD_SSP0_DATA6__SSP0_D6 | | ||
| 95 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 96 | MX28_PAD_SSP0_DATA7__SSP0_D7 | | ||
| 97 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 98 | MX28_PAD_SSP0_CMD__SSP0_CMD | | ||
| 99 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 100 | MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | | ||
| 101 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 102 | MX28_PAD_SSP0_SCK__SSP0_SCK | | ||
| 103 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 104 | |||
| 105 | /* led */ | ||
| 106 | MX28_PAD_PWM3__GPIO_3_28 | MXS_PAD_CTRL, | ||
| 107 | |||
| 108 | /* saif0 & saif1 */ | ||
| 109 | MX28_PAD_SAIF0_MCLK__SAIF0_MCLK | | ||
| 110 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 111 | MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK | | ||
| 112 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 113 | MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK | | ||
| 114 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 115 | MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 | | ||
| 116 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 117 | MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 | | ||
| 118 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 119 | }; | ||
| 120 | |||
| 121 | /* led */ | ||
| 122 | static const struct gpio_led apx4devkit_leds[] __initconst = { | ||
| 123 | { | ||
| 124 | .name = "user-led", | ||
| 125 | .default_trigger = "heartbeat", | ||
| 126 | .gpio = APX4DEVKIT_GPIO_USERLED, | ||
| 127 | }, | ||
| 128 | }; | ||
| 129 | |||
| 130 | static const struct gpio_led_platform_data apx4devkit_led_data __initconst = { | ||
| 131 | .leds = apx4devkit_leds, | ||
| 132 | .num_leds = ARRAY_SIZE(apx4devkit_leds), | ||
| 133 | }; | ||
| 134 | |||
| 135 | static const struct fec_platform_data mx28_fec_pdata __initconst = { | ||
| 136 | .phy = PHY_INTERFACE_MODE_RMII, | ||
| 137 | }; | ||
| 138 | |||
| 139 | static const struct mxs_mmc_platform_data apx4devkit_mmc_pdata __initconst = { | ||
| 140 | .wp_gpio = -EINVAL, | ||
| 141 | .flags = SLOTF_4_BIT_CAPABLE, | ||
| 142 | }; | ||
| 143 | |||
| 144 | static const struct i2c_board_info apx4devkit_i2c_boardinfo[] __initconst = { | ||
| 145 | { I2C_BOARD_INFO("sgtl5000", 0x0a) }, /* ASoC */ | ||
| 146 | { I2C_BOARD_INFO("pcf8563", 0x51) }, /* RTC */ | ||
| 147 | }; | ||
| 148 | |||
| 149 | #if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || \ | ||
| 150 | defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE) | ||
| 151 | static struct regulator_consumer_supply apx4devkit_audio_consumer_supplies[] = { | ||
| 152 | REGULATOR_SUPPLY("VDDA", "0-000a"), | ||
| 153 | REGULATOR_SUPPLY("VDDIO", "0-000a"), | ||
| 154 | }; | ||
| 155 | |||
| 156 | static struct regulator_init_data apx4devkit_vdd_reg_init_data = { | ||
| 157 | .constraints = { | ||
| 158 | .name = "3V3", | ||
| 159 | .always_on = 1, | ||
| 160 | }, | ||
| 161 | .consumer_supplies = apx4devkit_audio_consumer_supplies, | ||
| 162 | .num_consumer_supplies = ARRAY_SIZE(apx4devkit_audio_consumer_supplies), | ||
| 163 | }; | ||
| 164 | |||
| 165 | static struct fixed_voltage_config apx4devkit_vdd_pdata = { | ||
| 166 | .supply_name = "board-3V3", | ||
| 167 | .microvolts = 3300000, | ||
| 168 | .gpio = -EINVAL, | ||
| 169 | .enabled_at_boot = 1, | ||
| 170 | .init_data = &apx4devkit_vdd_reg_init_data, | ||
| 171 | }; | ||
| 172 | |||
| 173 | static struct platform_device apx4devkit_voltage_regulator = { | ||
| 174 | .name = "reg-fixed-voltage", | ||
| 175 | .id = -1, | ||
| 176 | .num_resources = 0, | ||
| 177 | .dev = { | ||
| 178 | .platform_data = &apx4devkit_vdd_pdata, | ||
| 179 | }, | ||
| 180 | }; | ||
| 181 | |||
| 182 | static void __init apx4devkit_add_regulators(void) | ||
| 183 | { | ||
| 184 | platform_device_register(&apx4devkit_voltage_regulator); | ||
| 185 | } | ||
| 186 | #else | ||
| 187 | static void __init apx4devkit_add_regulators(void) {} | ||
| 188 | #endif | ||
| 189 | |||
| 190 | static const struct mxs_saif_platform_data | ||
| 191 | apx4devkit_mxs_saif_pdata[] __initconst = { | ||
| 192 | /* working on EXTMSTR0 mode (saif0 master, saif1 slave) */ | ||
| 193 | { | ||
| 194 | .master_mode = 1, | ||
| 195 | .master_id = 0, | ||
| 196 | }, { | ||
| 197 | .master_mode = 0, | ||
| 198 | .master_id = 0, | ||
| 199 | }, | ||
| 200 | }; | ||
| 201 | |||
| 202 | static int apx4devkit_phy_fixup(struct phy_device *phy) | ||
| 203 | { | ||
| 204 | phy->dev_flags |= MICREL_PHY_50MHZ_CLK; | ||
| 205 | return 0; | ||
| 206 | } | ||
| 207 | |||
| 208 | static void __init apx4devkit_fec_phy_clk_enable(void) | ||
| 209 | { | ||
| 210 | struct clk *clk; | ||
| 211 | |||
| 212 | /* Enable fec phy clock */ | ||
| 213 | clk = clk_get_sys("enet_out", NULL); | ||
| 214 | if (!IS_ERR(clk)) | ||
| 215 | clk_prepare_enable(clk); | ||
| 216 | } | ||
| 217 | |||
| 218 | static void __init apx4devkit_init(void) | ||
| 219 | { | ||
| 220 | mx28_soc_init(); | ||
| 221 | |||
| 222 | mxs_iomux_setup_multiple_pads(apx4devkit_pads, | ||
| 223 | ARRAY_SIZE(apx4devkit_pads)); | ||
| 224 | |||
| 225 | mx28_add_duart(); | ||
| 226 | mx28_add_auart0(); | ||
| 227 | mx28_add_auart1(); | ||
| 228 | mx28_add_auart2(); | ||
| 229 | mx28_add_auart3(); | ||
| 230 | |||
| 231 | /* | ||
| 232 | * Register fixup for the Micrel KS8031 PHY clock | ||
| 233 | * (shares same ID with KS8051) | ||
| 234 | */ | ||
| 235 | phy_register_fixup_for_uid(PHY_ID_KS8051, MICREL_PHY_ID_MASK, | ||
| 236 | apx4devkit_phy_fixup); | ||
| 237 | |||
| 238 | apx4devkit_fec_phy_clk_enable(); | ||
| 239 | mx28_add_fec(0, &mx28_fec_pdata); | ||
| 240 | |||
| 241 | mx28_add_mxs_mmc(0, &apx4devkit_mmc_pdata); | ||
| 242 | |||
| 243 | gpio_led_register_device(0, &apx4devkit_led_data); | ||
| 244 | |||
| 245 | mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0); | ||
| 246 | mx28_add_saif(0, &apx4devkit_mxs_saif_pdata[0]); | ||
| 247 | mx28_add_saif(1, &apx4devkit_mxs_saif_pdata[1]); | ||
| 248 | |||
| 249 | apx4devkit_add_regulators(); | ||
| 250 | |||
| 251 | mx28_add_mxs_i2c(0); | ||
| 252 | i2c_register_board_info(0, apx4devkit_i2c_boardinfo, | ||
| 253 | ARRAY_SIZE(apx4devkit_i2c_boardinfo)); | ||
| 254 | |||
| 255 | mxs_add_platform_device("mxs-sgtl5000", 0, NULL, 0, NULL, 0); | ||
| 256 | } | ||
| 257 | |||
| 258 | static void __init apx4devkit_timer_init(void) | ||
| 259 | { | ||
| 260 | mx28_clocks_init(); | ||
| 261 | } | ||
| 262 | |||
| 263 | static struct sys_timer apx4devkit_timer = { | ||
| 264 | .init = apx4devkit_timer_init, | ||
| 265 | }; | ||
| 266 | |||
| 267 | MACHINE_START(APX4DEVKIT, "Bluegiga APX4 Development Kit") | ||
| 268 | .map_io = mx28_map_io, | ||
| 269 | .init_irq = mx28_init_irq, | ||
| 270 | .timer = &apx4devkit_timer, | ||
| 271 | .init_machine = apx4devkit_init, | ||
| 272 | .restart = mxs_restart, | ||
| 273 | MACHINE_END | ||
diff --git a/arch/arm/mach-mxs/mach-m28evk.c b/arch/arm/mach-mxs/mach-m28evk.c deleted file mode 100644 index 4c00c879b893..000000000000 --- a/arch/arm/mach-mxs/mach-m28evk.c +++ /dev/null | |||
| @@ -1,366 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2011 | ||
| 3 | * Stefano Babic, DENX Software Engineering, <sbabic@denx.de> | ||
| 4 | * | ||
| 5 | * based on: mach-mx28_evk.c | ||
| 6 | * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/delay.h> | ||
| 20 | #include <linux/platform_device.h> | ||
| 21 | #include <linux/gpio.h> | ||
| 22 | #include <linux/leds.h> | ||
| 23 | #include <linux/irq.h> | ||
| 24 | #include <linux/clk.h> | ||
| 25 | #include <linux/i2c.h> | ||
| 26 | #include <linux/i2c/at24.h> | ||
| 27 | |||
| 28 | #include <asm/mach-types.h> | ||
| 29 | #include <asm/mach/arch.h> | ||
| 30 | #include <asm/mach/time.h> | ||
| 31 | |||
| 32 | #include <mach/common.h> | ||
| 33 | #include <mach/iomux-mx28.h> | ||
| 34 | |||
| 35 | #include "devices-mx28.h" | ||
| 36 | |||
| 37 | #define M28EVK_GPIO_USERLED1 MXS_GPIO_NR(3, 16) | ||
| 38 | #define M28EVK_GPIO_USERLED2 MXS_GPIO_NR(3, 17) | ||
| 39 | |||
| 40 | #define MX28EVK_BL_ENABLE MXS_GPIO_NR(3, 18) | ||
| 41 | #define M28EVK_LCD_ENABLE MXS_GPIO_NR(3, 28) | ||
| 42 | |||
| 43 | #define MX28EVK_MMC0_WRITE_PROTECT MXS_GPIO_NR(2, 12) | ||
| 44 | #define MX28EVK_MMC1_WRITE_PROTECT MXS_GPIO_NR(0, 28) | ||
| 45 | |||
| 46 | static const iomux_cfg_t m28evk_pads[] __initconst = { | ||
| 47 | /* duart */ | ||
| 48 | MX28_PAD_AUART0_CTS__DUART_RX | MXS_PAD_CTRL, | ||
| 49 | MX28_PAD_AUART0_RTS__DUART_TX | MXS_PAD_CTRL, | ||
| 50 | |||
| 51 | /* auart0 */ | ||
| 52 | MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL, | ||
| 53 | MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL, | ||
| 54 | |||
| 55 | /* auart3 */ | ||
| 56 | MX28_PAD_AUART3_RX__AUART3_RX | MXS_PAD_CTRL, | ||
| 57 | MX28_PAD_AUART3_TX__AUART3_TX | MXS_PAD_CTRL, | ||
| 58 | MX28_PAD_AUART3_CTS__AUART3_CTS | MXS_PAD_CTRL, | ||
| 59 | MX28_PAD_AUART3_RTS__AUART3_RTS | MXS_PAD_CTRL, | ||
| 60 | |||
| 61 | #define MXS_PAD_FEC (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP) | ||
| 62 | /* fec0 */ | ||
| 63 | MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC, | ||
| 64 | MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC, | ||
| 65 | MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC, | ||
| 66 | MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC, | ||
| 67 | MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC, | ||
| 68 | MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC, | ||
| 69 | MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC, | ||
| 70 | MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC, | ||
| 71 | MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC, | ||
| 72 | /* fec1 */ | ||
| 73 | MX28_PAD_ENET0_CRS__ENET1_RX_EN | MXS_PAD_FEC, | ||
| 74 | MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MXS_PAD_FEC, | ||
| 75 | MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MXS_PAD_FEC, | ||
| 76 | MX28_PAD_ENET0_COL__ENET1_TX_EN | MXS_PAD_FEC, | ||
| 77 | MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MXS_PAD_FEC, | ||
| 78 | MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MXS_PAD_FEC, | ||
| 79 | |||
| 80 | /* flexcan0 */ | ||
| 81 | MX28_PAD_GPMI_RDY2__CAN0_TX, | ||
| 82 | MX28_PAD_GPMI_RDY3__CAN0_RX, | ||
| 83 | |||
| 84 | /* flexcan1 */ | ||
| 85 | MX28_PAD_GPMI_CE2N__CAN1_TX, | ||
| 86 | MX28_PAD_GPMI_CE3N__CAN1_RX, | ||
| 87 | |||
| 88 | /* I2C */ | ||
| 89 | MX28_PAD_I2C0_SCL__I2C0_SCL, | ||
| 90 | MX28_PAD_I2C0_SDA__I2C0_SDA, | ||
| 91 | |||
| 92 | /* mxsfb (lcdif) */ | ||
| 93 | MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL, | ||
| 94 | MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL, | ||
| 95 | MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL, | ||
| 96 | MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL, | ||
| 97 | MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL, | ||
| 98 | MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL, | ||
| 99 | MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL, | ||
| 100 | MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL, | ||
| 101 | MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL, | ||
| 102 | MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL, | ||
| 103 | MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL, | ||
| 104 | MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL, | ||
| 105 | MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL, | ||
| 106 | MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL, | ||
| 107 | MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL, | ||
| 108 | MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL, | ||
| 109 | MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL, | ||
| 110 | MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL, | ||
| 111 | MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL, | ||
| 112 | MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL, | ||
| 113 | MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL, | ||
| 114 | MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL, | ||
| 115 | MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL, | ||
| 116 | MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL, | ||
| 117 | |||
| 118 | MX28_PAD_LCD_ENABLE__LCD_ENABLE | MXS_PAD_CTRL, | ||
| 119 | MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MXS_PAD_CTRL, | ||
| 120 | |||
| 121 | /* mmc0 */ | ||
| 122 | MX28_PAD_SSP0_DATA0__SSP0_D0 | | ||
| 123 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 124 | MX28_PAD_SSP0_DATA1__SSP0_D1 | | ||
| 125 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 126 | MX28_PAD_SSP0_DATA2__SSP0_D2 | | ||
| 127 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 128 | MX28_PAD_SSP0_DATA3__SSP0_D3 | | ||
| 129 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 130 | MX28_PAD_SSP0_DATA4__SSP0_D4 | | ||
| 131 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 132 | MX28_PAD_SSP0_DATA5__SSP0_D5 | | ||
| 133 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 134 | MX28_PAD_SSP0_DATA6__SSP0_D6 | | ||
| 135 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 136 | MX28_PAD_SSP0_DATA7__SSP0_D7 | | ||
| 137 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 138 | MX28_PAD_SSP0_CMD__SSP0_CMD | | ||
| 139 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 140 | MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | | ||
| 141 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 142 | MX28_PAD_SSP0_SCK__SSP0_SCK | | ||
| 143 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 144 | |||
| 145 | /* mmc1 */ | ||
| 146 | MX28_PAD_GPMI_D00__SSP1_D0 | | ||
| 147 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 148 | MX28_PAD_GPMI_D01__SSP1_D1 | | ||
| 149 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 150 | MX28_PAD_GPMI_D02__SSP1_D2 | | ||
| 151 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 152 | MX28_PAD_GPMI_D03__SSP1_D3 | | ||
| 153 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 154 | MX28_PAD_GPMI_D04__SSP1_D4 | | ||
| 155 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 156 | MX28_PAD_GPMI_D05__SSP1_D5 | | ||
| 157 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 158 | MX28_PAD_GPMI_D06__SSP1_D6 | | ||
| 159 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 160 | MX28_PAD_GPMI_D07__SSP1_D7 | | ||
| 161 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 162 | MX28_PAD_GPMI_RDY1__SSP1_CMD | | ||
| 163 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 164 | MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT | | ||
| 165 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 166 | MX28_PAD_GPMI_WRN__SSP1_SCK | | ||
| 167 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 168 | /* write protect */ | ||
| 169 | MX28_PAD_GPMI_RESETN__GPIO_0_28 | | ||
| 170 | (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 171 | /* slot power enable */ | ||
| 172 | MX28_PAD_PWM4__GPIO_3_29 | | ||
| 173 | (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 174 | |||
| 175 | /* led */ | ||
| 176 | MX28_PAD_PWM0__GPIO_3_16 | MXS_PAD_CTRL, | ||
| 177 | MX28_PAD_PWM1__GPIO_3_17 | MXS_PAD_CTRL, | ||
| 178 | |||
| 179 | /* nand */ | ||
| 180 | MX28_PAD_GPMI_D00__GPMI_D0 | | ||
| 181 | (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), | ||
| 182 | MX28_PAD_GPMI_D01__GPMI_D1 | | ||
| 183 | (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), | ||
| 184 | MX28_PAD_GPMI_D02__GPMI_D2 | | ||
| 185 | (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), | ||
| 186 | MX28_PAD_GPMI_D03__GPMI_D3 | | ||
| 187 | (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), | ||
| 188 | MX28_PAD_GPMI_D04__GPMI_D4 | | ||
| 189 | (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), | ||
| 190 | MX28_PAD_GPMI_D05__GPMI_D5 | | ||
| 191 | (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), | ||
| 192 | MX28_PAD_GPMI_D06__GPMI_D6 | | ||
| 193 | (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), | ||
| 194 | MX28_PAD_GPMI_D07__GPMI_D7 | | ||
| 195 | (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), | ||
| 196 | MX28_PAD_GPMI_CE0N__GPMI_CE0N | | ||
| 197 | (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), | ||
| 198 | MX28_PAD_GPMI_RDY0__GPMI_READY0 | | ||
| 199 | (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), | ||
| 200 | MX28_PAD_GPMI_RDN__GPMI_RDN | | ||
| 201 | (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP), | ||
| 202 | MX28_PAD_GPMI_WRN__GPMI_WRN | | ||
| 203 | (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP), | ||
| 204 | MX28_PAD_GPMI_ALE__GPMI_ALE | | ||
| 205 | (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_PULLUP), | ||
| 206 | MX28_PAD_GPMI_CLE__GPMI_CLE | | ||
| 207 | (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_PULLUP), | ||
| 208 | MX28_PAD_GPMI_RESETN__GPMI_RESETN | | ||
| 209 | (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP), | ||
| 210 | |||
| 211 | /* Backlight */ | ||
| 212 | MX28_PAD_PWM3__GPIO_3_28 | MXS_PAD_CTRL, | ||
| 213 | }; | ||
| 214 | |||
| 215 | /* led */ | ||
| 216 | static const struct gpio_led m28evk_leds[] __initconst = { | ||
| 217 | { | ||
| 218 | .name = "user-led1", | ||
| 219 | .default_trigger = "heartbeat", | ||
| 220 | .gpio = M28EVK_GPIO_USERLED1, | ||
| 221 | }, | ||
| 222 | { | ||
| 223 | .name = "user-led2", | ||
| 224 | .default_trigger = "heartbeat", | ||
| 225 | .gpio = M28EVK_GPIO_USERLED2, | ||
| 226 | }, | ||
| 227 | }; | ||
| 228 | |||
| 229 | static const struct gpio_led_platform_data m28evk_led_data __initconst = { | ||
| 230 | .leds = m28evk_leds, | ||
| 231 | .num_leds = ARRAY_SIZE(m28evk_leds), | ||
| 232 | }; | ||
| 233 | |||
| 234 | static struct fec_platform_data mx28_fec_pdata[] __initdata = { | ||
| 235 | { | ||
| 236 | /* fec0 */ | ||
| 237 | .phy = PHY_INTERFACE_MODE_RMII, | ||
| 238 | }, { | ||
| 239 | /* fec1 */ | ||
| 240 | .phy = PHY_INTERFACE_MODE_RMII, | ||
| 241 | }, | ||
| 242 | }; | ||
| 243 | |||
| 244 | static int __init m28evk_fec_get_mac(void) | ||
| 245 | { | ||
| 246 | int i; | ||
| 247 | u32 val; | ||
| 248 | const u32 *ocotp = mxs_get_ocotp(); | ||
| 249 | |||
| 250 | if (!ocotp) | ||
| 251 | return -ETIMEDOUT; | ||
| 252 | |||
| 253 | /* | ||
| 254 | * OCOTP only stores the last 4 octets for each mac address, | ||
| 255 | * so hard-code DENX OUI (C0:E5:4E) here. | ||
| 256 | */ | ||
| 257 | for (i = 0; i < 2; i++) { | ||
| 258 | val = ocotp[i]; | ||
| 259 | mx28_fec_pdata[i].mac[0] = 0xC0; | ||
| 260 | mx28_fec_pdata[i].mac[1] = 0xE5; | ||
| 261 | mx28_fec_pdata[i].mac[2] = 0x4E; | ||
| 262 | mx28_fec_pdata[i].mac[3] = (val >> 16) & 0xff; | ||
| 263 | mx28_fec_pdata[i].mac[4] = (val >> 8) & 0xff; | ||
| 264 | mx28_fec_pdata[i].mac[5] = (val >> 0) & 0xff; | ||
| 265 | } | ||
| 266 | |||
| 267 | return 0; | ||
| 268 | } | ||
| 269 | |||
| 270 | /* mxsfb (lcdif) */ | ||
| 271 | static struct fb_videomode m28evk_video_modes[] = { | ||
| 272 | { | ||
| 273 | .name = "Ampire AM-800480R2TMQW-T01H", | ||
| 274 | .refresh = 60, | ||
| 275 | .xres = 800, | ||
| 276 | .yres = 480, | ||
| 277 | .pixclock = 30066, /* picosecond (33.26 MHz) */ | ||
| 278 | .left_margin = 0, | ||
| 279 | .right_margin = 256, | ||
| 280 | .upper_margin = 0, | ||
| 281 | .lower_margin = 45, | ||
| 282 | .hsync_len = 1, | ||
| 283 | .vsync_len = 1, | ||
| 284 | .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT, | ||
| 285 | }, | ||
| 286 | }; | ||
| 287 | |||
| 288 | static const struct mxsfb_platform_data m28evk_mxsfb_pdata __initconst = { | ||
| 289 | .mode_list = m28evk_video_modes, | ||
| 290 | .mode_count = ARRAY_SIZE(m28evk_video_modes), | ||
| 291 | .default_bpp = 16, | ||
| 292 | .ld_intf_width = STMLCDIF_18BIT, | ||
| 293 | }; | ||
| 294 | |||
| 295 | static struct at24_platform_data m28evk_eeprom = { | ||
| 296 | .byte_len = 16384, | ||
| 297 | .page_size = 32, | ||
| 298 | .flags = AT24_FLAG_ADDR16, | ||
| 299 | }; | ||
| 300 | |||
| 301 | static struct i2c_board_info m28_stk5v3_i2c_boardinfo[] __initdata = { | ||
| 302 | { | ||
| 303 | I2C_BOARD_INFO("at24", 0x51), /* E0=1, E1=0, E2=0 */ | ||
| 304 | .platform_data = &m28evk_eeprom, | ||
| 305 | }, | ||
| 306 | }; | ||
| 307 | |||
| 308 | static struct mxs_mmc_platform_data m28evk_mmc_pdata[] __initdata = { | ||
| 309 | { | ||
| 310 | /* mmc0 */ | ||
| 311 | .wp_gpio = MX28EVK_MMC0_WRITE_PROTECT, | ||
| 312 | .flags = SLOTF_8_BIT_CAPABLE, | ||
| 313 | }, { | ||
| 314 | /* mmc1 */ | ||
| 315 | .wp_gpio = MX28EVK_MMC1_WRITE_PROTECT, | ||
| 316 | .flags = SLOTF_8_BIT_CAPABLE, | ||
| 317 | }, | ||
| 318 | }; | ||
| 319 | |||
| 320 | static void __init m28evk_init(void) | ||
| 321 | { | ||
| 322 | mx28_soc_init(); | ||
| 323 | |||
| 324 | mxs_iomux_setup_multiple_pads(m28evk_pads, ARRAY_SIZE(m28evk_pads)); | ||
| 325 | |||
| 326 | mx28_add_duart(); | ||
| 327 | mx28_add_auart0(); | ||
| 328 | mx28_add_auart3(); | ||
| 329 | |||
| 330 | if (!m28evk_fec_get_mac()) { | ||
| 331 | mx28_add_fec(0, &mx28_fec_pdata[0]); | ||
| 332 | mx28_add_fec(1, &mx28_fec_pdata[1]); | ||
| 333 | } | ||
| 334 | |||
| 335 | mx28_add_flexcan(0, NULL); | ||
| 336 | mx28_add_flexcan(1, NULL); | ||
| 337 | |||
| 338 | mx28_add_mxsfb(&m28evk_mxsfb_pdata); | ||
| 339 | |||
| 340 | mx28_add_mxs_mmc(0, &m28evk_mmc_pdata[0]); | ||
| 341 | mx28_add_mxs_mmc(1, &m28evk_mmc_pdata[1]); | ||
| 342 | |||
| 343 | gpio_led_register_device(0, &m28evk_led_data); | ||
| 344 | |||
| 345 | /* I2C */ | ||
| 346 | mx28_add_mxs_i2c(0); | ||
| 347 | i2c_register_board_info(0, m28_stk5v3_i2c_boardinfo, | ||
| 348 | ARRAY_SIZE(m28_stk5v3_i2c_boardinfo)); | ||
| 349 | } | ||
| 350 | |||
| 351 | static void __init m28evk_timer_init(void) | ||
| 352 | { | ||
| 353 | mx28_clocks_init(); | ||
| 354 | } | ||
| 355 | |||
| 356 | static struct sys_timer m28evk_timer = { | ||
| 357 | .init = m28evk_timer_init, | ||
| 358 | }; | ||
| 359 | |||
| 360 | MACHINE_START(M28EVK, "DENX M28 EVK") | ||
| 361 | .map_io = mx28_map_io, | ||
| 362 | .init_irq = mx28_init_irq, | ||
| 363 | .timer = &m28evk_timer, | ||
| 364 | .init_machine = m28evk_init, | ||
| 365 | .restart = mxs_restart, | ||
| 366 | MACHINE_END | ||
diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c deleted file mode 100644 index e7272a41939d..000000000000 --- a/arch/arm/mach-mxs/mach-mx23evk.c +++ /dev/null | |||
| @@ -1,190 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/delay.h> | ||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <linux/gpio.h> | ||
| 18 | |||
| 19 | #include <asm/mach-types.h> | ||
| 20 | #include <asm/mach/arch.h> | ||
| 21 | #include <asm/mach/time.h> | ||
| 22 | |||
| 23 | #include <mach/common.h> | ||
| 24 | #include <mach/iomux-mx23.h> | ||
| 25 | |||
| 26 | #include "devices-mx23.h" | ||
| 27 | |||
| 28 | #define MX23EVK_LCD_ENABLE MXS_GPIO_NR(1, 18) | ||
| 29 | #define MX23EVK_BL_ENABLE MXS_GPIO_NR(1, 28) | ||
| 30 | #define MX23EVK_MMC0_WRITE_PROTECT MXS_GPIO_NR(1, 30) | ||
| 31 | #define MX23EVK_MMC0_SLOT_POWER MXS_GPIO_NR(1, 29) | ||
| 32 | |||
| 33 | static const iomux_cfg_t mx23evk_pads[] __initconst = { | ||
| 34 | /* duart */ | ||
| 35 | MX23_PAD_PWM0__DUART_RX | MXS_PAD_CTRL, | ||
| 36 | MX23_PAD_PWM1__DUART_TX | MXS_PAD_CTRL, | ||
| 37 | |||
| 38 | /* auart */ | ||
| 39 | MX23_PAD_AUART1_RX__AUART1_RX | MXS_PAD_CTRL, | ||
| 40 | MX23_PAD_AUART1_TX__AUART1_TX | MXS_PAD_CTRL, | ||
| 41 | MX23_PAD_AUART1_CTS__AUART1_CTS | MXS_PAD_CTRL, | ||
| 42 | MX23_PAD_AUART1_RTS__AUART1_RTS | MXS_PAD_CTRL, | ||
| 43 | |||
| 44 | /* mxsfb (lcdif) */ | ||
| 45 | MX23_PAD_LCD_D00__LCD_D00 | MXS_PAD_CTRL, | ||
| 46 | MX23_PAD_LCD_D01__LCD_D01 | MXS_PAD_CTRL, | ||
| 47 | MX23_PAD_LCD_D02__LCD_D02 | MXS_PAD_CTRL, | ||
| 48 | MX23_PAD_LCD_D03__LCD_D03 | MXS_PAD_CTRL, | ||
| 49 | MX23_PAD_LCD_D04__LCD_D04 | MXS_PAD_CTRL, | ||
| 50 | MX23_PAD_LCD_D05__LCD_D05 | MXS_PAD_CTRL, | ||
| 51 | MX23_PAD_LCD_D06__LCD_D06 | MXS_PAD_CTRL, | ||
| 52 | MX23_PAD_LCD_D07__LCD_D07 | MXS_PAD_CTRL, | ||
| 53 | MX23_PAD_LCD_D08__LCD_D08 | MXS_PAD_CTRL, | ||
| 54 | MX23_PAD_LCD_D09__LCD_D09 | MXS_PAD_CTRL, | ||
| 55 | MX23_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL, | ||
| 56 | MX23_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL, | ||
| 57 | MX23_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL, | ||
| 58 | MX23_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL, | ||
| 59 | MX23_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL, | ||
| 60 | MX23_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL, | ||
| 61 | MX23_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL, | ||
| 62 | MX23_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL, | ||
| 63 | MX23_PAD_GPMI_D08__LCD_D18 | MXS_PAD_CTRL, | ||
| 64 | MX23_PAD_GPMI_D09__LCD_D19 | MXS_PAD_CTRL, | ||
| 65 | MX23_PAD_GPMI_D10__LCD_D20 | MXS_PAD_CTRL, | ||
| 66 | MX23_PAD_GPMI_D11__LCD_D21 | MXS_PAD_CTRL, | ||
| 67 | MX23_PAD_GPMI_D12__LCD_D22 | MXS_PAD_CTRL, | ||
| 68 | MX23_PAD_GPMI_D13__LCD_D23 | MXS_PAD_CTRL, | ||
| 69 | MX23_PAD_LCD_VSYNC__LCD_VSYNC | MXS_PAD_CTRL, | ||
| 70 | MX23_PAD_LCD_HSYNC__LCD_HSYNC | MXS_PAD_CTRL, | ||
| 71 | MX23_PAD_LCD_DOTCK__LCD_DOTCK | MXS_PAD_CTRL, | ||
| 72 | MX23_PAD_LCD_ENABLE__LCD_ENABLE | MXS_PAD_CTRL, | ||
| 73 | /* LCD panel enable */ | ||
| 74 | MX23_PAD_LCD_RESET__GPIO_1_18 | MXS_PAD_CTRL, | ||
| 75 | /* backlight control */ | ||
| 76 | MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_CTRL, | ||
| 77 | |||
| 78 | /* mmc */ | ||
| 79 | MX23_PAD_SSP1_DATA0__SSP1_DATA0 | | ||
| 80 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 81 | MX23_PAD_SSP1_DATA1__SSP1_DATA1 | | ||
| 82 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 83 | MX23_PAD_SSP1_DATA2__SSP1_DATA2 | | ||
| 84 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 85 | MX23_PAD_SSP1_DATA3__SSP1_DATA3 | | ||
| 86 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 87 | MX23_PAD_GPMI_D08__SSP1_DATA4 | | ||
| 88 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 89 | MX23_PAD_GPMI_D09__SSP1_DATA5 | | ||
| 90 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 91 | MX23_PAD_GPMI_D10__SSP1_DATA6 | | ||
| 92 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 93 | MX23_PAD_GPMI_D11__SSP1_DATA7 | | ||
| 94 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 95 | MX23_PAD_SSP1_CMD__SSP1_CMD | | ||
| 96 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 97 | MX23_PAD_SSP1_DETECT__SSP1_DETECT | | ||
| 98 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 99 | MX23_PAD_SSP1_SCK__SSP1_SCK | | ||
| 100 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 101 | /* write protect */ | ||
| 102 | MX23_PAD_PWM4__GPIO_1_30 | | ||
| 103 | (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 104 | /* slot power enable */ | ||
| 105 | MX23_PAD_PWM3__GPIO_1_29 | | ||
| 106 | (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 107 | }; | ||
| 108 | |||
| 109 | /* mxsfb (lcdif) */ | ||
| 110 | static struct fb_videomode mx23evk_video_modes[] = { | ||
| 111 | { | ||
| 112 | .name = "Samsung-LMS430HF02", | ||
| 113 | .refresh = 60, | ||
| 114 | .xres = 480, | ||
| 115 | .yres = 272, | ||
| 116 | .pixclock = 108096, /* picosecond (9.2 MHz) */ | ||
| 117 | .left_margin = 15, | ||
| 118 | .right_margin = 8, | ||
| 119 | .upper_margin = 12, | ||
| 120 | .lower_margin = 4, | ||
| 121 | .hsync_len = 1, | ||
| 122 | .vsync_len = 1, | ||
| 123 | .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT | | ||
| 124 | FB_SYNC_DOTCLK_FAILING_ACT, | ||
| 125 | }, | ||
| 126 | }; | ||
| 127 | |||
| 128 | static const struct mxsfb_platform_data mx23evk_mxsfb_pdata __initconst = { | ||
| 129 | .mode_list = mx23evk_video_modes, | ||
| 130 | .mode_count = ARRAY_SIZE(mx23evk_video_modes), | ||
| 131 | .default_bpp = 32, | ||
| 132 | .ld_intf_width = STMLCDIF_24BIT, | ||
| 133 | }; | ||
| 134 | |||
| 135 | static struct mxs_mmc_platform_data mx23evk_mmc_pdata __initdata = { | ||
| 136 | .wp_gpio = MX23EVK_MMC0_WRITE_PROTECT, | ||
| 137 | .flags = SLOTF_8_BIT_CAPABLE, | ||
| 138 | }; | ||
| 139 | |||
| 140 | static void __init mx23evk_init(void) | ||
| 141 | { | ||
| 142 | int ret; | ||
| 143 | |||
| 144 | mx23_soc_init(); | ||
| 145 | |||
| 146 | mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads)); | ||
| 147 | |||
| 148 | mx23_add_duart(); | ||
| 149 | mx23_add_auart0(); | ||
| 150 | |||
| 151 | /* power on mmc slot by writing 0 to the gpio */ | ||
| 152 | ret = gpio_request_one(MX23EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW, | ||
| 153 | "mmc0-slot-power"); | ||
| 154 | if (ret) | ||
| 155 | pr_warn("failed to request gpio mmc0-slot-power: %d\n", ret); | ||
| 156 | mx23_add_mxs_mmc(0, &mx23evk_mmc_pdata); | ||
| 157 | |||
| 158 | ret = gpio_request_one(MX23EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable"); | ||
| 159 | if (ret) | ||
| 160 | pr_warn("failed to request gpio lcd-enable: %d\n", ret); | ||
| 161 | else | ||
| 162 | gpio_set_value(MX23EVK_LCD_ENABLE, 1); | ||
| 163 | |||
| 164 | ret = gpio_request_one(MX23EVK_BL_ENABLE, GPIOF_DIR_OUT, "bl-enable"); | ||
| 165 | if (ret) | ||
| 166 | pr_warn("failed to request gpio bl-enable: %d\n", ret); | ||
| 167 | else | ||
| 168 | gpio_set_value(MX23EVK_BL_ENABLE, 1); | ||
| 169 | |||
| 170 | mx23_add_mxsfb(&mx23evk_mxsfb_pdata); | ||
| 171 | mx23_add_rtc_stmp3xxx(); | ||
| 172 | } | ||
| 173 | |||
| 174 | static void __init mx23evk_timer_init(void) | ||
| 175 | { | ||
| 176 | mx23_clocks_init(); | ||
| 177 | } | ||
| 178 | |||
| 179 | static struct sys_timer mx23evk_timer = { | ||
| 180 | .init = mx23evk_timer_init, | ||
| 181 | }; | ||
| 182 | |||
| 183 | MACHINE_START(MX23EVK, "Freescale MX23 EVK") | ||
| 184 | /* Maintainer: Freescale Semiconductor, Inc. */ | ||
| 185 | .map_io = mx23_map_io, | ||
| 186 | .init_irq = mx23_init_irq, | ||
| 187 | .timer = &mx23evk_timer, | ||
| 188 | .init_machine = mx23evk_init, | ||
| 189 | .restart = mxs_restart, | ||
| 190 | MACHINE_END | ||
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c deleted file mode 100644 index dafd48e86c8c..000000000000 --- a/arch/arm/mach-mxs/mach-mx28evk.c +++ /dev/null | |||
| @@ -1,477 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/delay.h> | ||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <linux/gpio.h> | ||
| 18 | #include <linux/leds.h> | ||
| 19 | #include <linux/clk.h> | ||
| 20 | #include <linux/i2c.h> | ||
| 21 | #include <linux/regulator/machine.h> | ||
| 22 | #include <linux/regulator/fixed.h> | ||
| 23 | |||
| 24 | #include <asm/mach-types.h> | ||
| 25 | #include <asm/mach/arch.h> | ||
| 26 | #include <asm/mach/time.h> | ||
| 27 | |||
| 28 | #include <mach/common.h> | ||
| 29 | #include <mach/iomux-mx28.h> | ||
| 30 | #include <mach/digctl.h> | ||
| 31 | |||
| 32 | #include "devices-mx28.h" | ||
| 33 | |||
| 34 | #define MX28EVK_FLEXCAN_SWITCH MXS_GPIO_NR(2, 13) | ||
| 35 | #define MX28EVK_FEC_PHY_POWER MXS_GPIO_NR(2, 15) | ||
| 36 | #define MX28EVK_GPIO_LED MXS_GPIO_NR(3, 5) | ||
| 37 | #define MX28EVK_BL_ENABLE MXS_GPIO_NR(3, 18) | ||
| 38 | #define MX28EVK_LCD_ENABLE MXS_GPIO_NR(3, 30) | ||
| 39 | #define MX28EVK_FEC_PHY_RESET MXS_GPIO_NR(4, 13) | ||
| 40 | |||
| 41 | #define MX28EVK_MMC0_WRITE_PROTECT MXS_GPIO_NR(2, 12) | ||
| 42 | #define MX28EVK_MMC1_WRITE_PROTECT MXS_GPIO_NR(0, 28) | ||
| 43 | #define MX28EVK_MMC0_SLOT_POWER MXS_GPIO_NR(3, 28) | ||
| 44 | #define MX28EVK_MMC1_SLOT_POWER MXS_GPIO_NR(3, 29) | ||
| 45 | |||
| 46 | static const iomux_cfg_t mx28evk_pads[] __initconst = { | ||
| 47 | /* duart */ | ||
| 48 | MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL, | ||
| 49 | MX28_PAD_PWM1__DUART_TX | MXS_PAD_CTRL, | ||
| 50 | |||
| 51 | /* auart0 */ | ||
| 52 | MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL, | ||
| 53 | MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL, | ||
| 54 | MX28_PAD_AUART0_CTS__AUART0_CTS | MXS_PAD_CTRL, | ||
| 55 | MX28_PAD_AUART0_RTS__AUART0_RTS | MXS_PAD_CTRL, | ||
| 56 | /* auart3 */ | ||
| 57 | MX28_PAD_AUART3_RX__AUART3_RX | MXS_PAD_CTRL, | ||
| 58 | MX28_PAD_AUART3_TX__AUART3_TX | MXS_PAD_CTRL, | ||
| 59 | MX28_PAD_AUART3_CTS__AUART3_CTS | MXS_PAD_CTRL, | ||
| 60 | MX28_PAD_AUART3_RTS__AUART3_RTS | MXS_PAD_CTRL, | ||
| 61 | |||
| 62 | #define MXS_PAD_FEC (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP) | ||
| 63 | /* fec0 */ | ||
| 64 | MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC, | ||
| 65 | MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC, | ||
| 66 | MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC, | ||
| 67 | MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC, | ||
| 68 | MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC, | ||
| 69 | MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC, | ||
| 70 | MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC, | ||
| 71 | MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC, | ||
| 72 | MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC, | ||
| 73 | /* fec1 */ | ||
| 74 | MX28_PAD_ENET0_CRS__ENET1_RX_EN | MXS_PAD_FEC, | ||
| 75 | MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MXS_PAD_FEC, | ||
| 76 | MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MXS_PAD_FEC, | ||
| 77 | MX28_PAD_ENET0_COL__ENET1_TX_EN | MXS_PAD_FEC, | ||
| 78 | MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MXS_PAD_FEC, | ||
| 79 | MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MXS_PAD_FEC, | ||
| 80 | /* phy power line */ | ||
| 81 | MX28_PAD_SSP1_DATA3__GPIO_2_15 | MXS_PAD_CTRL, | ||
| 82 | /* phy reset line */ | ||
| 83 | MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | MXS_PAD_CTRL, | ||
| 84 | |||
| 85 | /* flexcan0 */ | ||
| 86 | MX28_PAD_GPMI_RDY2__CAN0_TX, | ||
| 87 | MX28_PAD_GPMI_RDY3__CAN0_RX, | ||
| 88 | /* flexcan1 */ | ||
| 89 | MX28_PAD_GPMI_CE2N__CAN1_TX, | ||
| 90 | MX28_PAD_GPMI_CE3N__CAN1_RX, | ||
| 91 | /* transceiver power control */ | ||
| 92 | MX28_PAD_SSP1_CMD__GPIO_2_13, | ||
| 93 | |||
| 94 | /* mxsfb (lcdif) */ | ||
| 95 | MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL, | ||
| 96 | MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL, | ||
| 97 | MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL, | ||
| 98 | MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL, | ||
| 99 | MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL, | ||
| 100 | MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL, | ||
| 101 | MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL, | ||
| 102 | MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL, | ||
| 103 | MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL, | ||
| 104 | MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL, | ||
| 105 | MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL, | ||
| 106 | MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL, | ||
| 107 | MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL, | ||
| 108 | MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL, | ||
| 109 | MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL, | ||
| 110 | MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL, | ||
| 111 | MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL, | ||
| 112 | MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL, | ||
| 113 | MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL, | ||
| 114 | MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL, | ||
| 115 | MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL, | ||
| 116 | MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL, | ||
| 117 | MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL, | ||
| 118 | MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL, | ||
| 119 | MX28_PAD_LCD_RD_E__LCD_VSYNC | MXS_PAD_CTRL, | ||
| 120 | MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MXS_PAD_CTRL, | ||
| 121 | MX28_PAD_LCD_RS__LCD_DOTCLK | MXS_PAD_CTRL, | ||
| 122 | MX28_PAD_LCD_CS__LCD_ENABLE | MXS_PAD_CTRL, | ||
| 123 | /* LCD panel enable */ | ||
| 124 | MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL, | ||
| 125 | /* backlight control */ | ||
| 126 | MX28_PAD_PWM2__GPIO_3_18 | MXS_PAD_CTRL, | ||
| 127 | /* mmc0 */ | ||
| 128 | MX28_PAD_SSP0_DATA0__SSP0_D0 | | ||
| 129 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 130 | MX28_PAD_SSP0_DATA1__SSP0_D1 | | ||
| 131 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 132 | MX28_PAD_SSP0_DATA2__SSP0_D2 | | ||
| 133 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 134 | MX28_PAD_SSP0_DATA3__SSP0_D3 | | ||
| 135 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 136 | MX28_PAD_SSP0_DATA4__SSP0_D4 | | ||
| 137 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 138 | MX28_PAD_SSP0_DATA5__SSP0_D5 | | ||
| 139 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 140 | MX28_PAD_SSP0_DATA6__SSP0_D6 | | ||
| 141 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 142 | MX28_PAD_SSP0_DATA7__SSP0_D7 | | ||
| 143 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 144 | MX28_PAD_SSP0_CMD__SSP0_CMD | | ||
| 145 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 146 | MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | | ||
| 147 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 148 | MX28_PAD_SSP0_SCK__SSP0_SCK | | ||
| 149 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 150 | /* write protect */ | ||
| 151 | MX28_PAD_SSP1_SCK__GPIO_2_12 | | ||
| 152 | (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 153 | /* slot power enable */ | ||
| 154 | MX28_PAD_PWM3__GPIO_3_28 | | ||
| 155 | (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 156 | |||
| 157 | /* mmc1 */ | ||
| 158 | MX28_PAD_GPMI_D00__SSP1_D0 | | ||
| 159 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 160 | MX28_PAD_GPMI_D01__SSP1_D1 | | ||
| 161 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 162 | MX28_PAD_GPMI_D02__SSP1_D2 | | ||
| 163 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 164 | MX28_PAD_GPMI_D03__SSP1_D3 | | ||
| 165 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 166 | MX28_PAD_GPMI_D04__SSP1_D4 | | ||
| 167 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 168 | MX28_PAD_GPMI_D05__SSP1_D5 | | ||
| 169 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 170 | MX28_PAD_GPMI_D06__SSP1_D6 | | ||
| 171 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 172 | MX28_PAD_GPMI_D07__SSP1_D7 | | ||
| 173 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 174 | MX28_PAD_GPMI_RDY1__SSP1_CMD | | ||
| 175 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 176 | MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT | | ||
| 177 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 178 | MX28_PAD_GPMI_WRN__SSP1_SCK | | ||
| 179 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 180 | /* write protect */ | ||
| 181 | MX28_PAD_GPMI_RESETN__GPIO_0_28 | | ||
| 182 | (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 183 | /* slot power enable */ | ||
| 184 | MX28_PAD_PWM4__GPIO_3_29 | | ||
| 185 | (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 186 | |||
| 187 | /* led */ | ||
| 188 | MX28_PAD_AUART1_TX__GPIO_3_5 | MXS_PAD_CTRL, | ||
| 189 | |||
| 190 | /* I2C */ | ||
| 191 | MX28_PAD_I2C0_SCL__I2C0_SCL | | ||
| 192 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 193 | MX28_PAD_I2C0_SDA__I2C0_SDA | | ||
| 194 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 195 | |||
| 196 | /* saif0 & saif1 */ | ||
| 197 | MX28_PAD_SAIF0_MCLK__SAIF0_MCLK | | ||
| 198 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 199 | MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK | | ||
| 200 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 201 | MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK | | ||
| 202 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 203 | MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 | | ||
| 204 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 205 | MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 | | ||
| 206 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 207 | }; | ||
| 208 | |||
| 209 | /* led */ | ||
| 210 | static const struct gpio_led mx28evk_leds[] __initconst = { | ||
| 211 | { | ||
| 212 | .name = "GPIO-LED", | ||
| 213 | .default_trigger = "heartbeat", | ||
| 214 | .gpio = MX28EVK_GPIO_LED, | ||
| 215 | }, | ||
| 216 | }; | ||
| 217 | |||
| 218 | static const struct gpio_led_platform_data mx28evk_led_data __initconst = { | ||
| 219 | .leds = mx28evk_leds, | ||
| 220 | .num_leds = ARRAY_SIZE(mx28evk_leds), | ||
| 221 | }; | ||
| 222 | |||
| 223 | /* fec */ | ||
| 224 | static void __init mx28evk_fec_reset(void) | ||
| 225 | { | ||
| 226 | struct clk *clk; | ||
| 227 | |||
| 228 | /* Enable fec phy clock */ | ||
| 229 | clk = clk_get_sys("enet_out", NULL); | ||
| 230 | if (!IS_ERR(clk)) | ||
| 231 | clk_prepare_enable(clk); | ||
| 232 | |||
| 233 | gpio_set_value(MX28EVK_FEC_PHY_RESET, 0); | ||
| 234 | mdelay(1); | ||
| 235 | gpio_set_value(MX28EVK_FEC_PHY_RESET, 1); | ||
| 236 | } | ||
| 237 | |||
| 238 | static struct fec_platform_data mx28_fec_pdata[] __initdata = { | ||
| 239 | { | ||
| 240 | /* fec0 */ | ||
| 241 | .phy = PHY_INTERFACE_MODE_RMII, | ||
| 242 | }, { | ||
| 243 | /* fec1 */ | ||
| 244 | .phy = PHY_INTERFACE_MODE_RMII, | ||
| 245 | }, | ||
| 246 | }; | ||
| 247 | |||
| 248 | static int __init mx28evk_fec_get_mac(void) | ||
| 249 | { | ||
| 250 | int i; | ||
| 251 | u32 val; | ||
| 252 | const u32 *ocotp = mxs_get_ocotp(); | ||
| 253 | |||
| 254 | if (!ocotp) | ||
| 255 | return -ETIMEDOUT; | ||
| 256 | |||
| 257 | /* | ||
| 258 | * OCOTP only stores the last 4 octets for each mac address, | ||
| 259 | * so hard-code Freescale OUI (00:04:9f) here. | ||
| 260 | */ | ||
| 261 | for (i = 0; i < 2; i++) { | ||
| 262 | val = ocotp[i]; | ||
| 263 | mx28_fec_pdata[i].mac[0] = 0x00; | ||
| 264 | mx28_fec_pdata[i].mac[1] = 0x04; | ||
| 265 | mx28_fec_pdata[i].mac[2] = 0x9f; | ||
| 266 | mx28_fec_pdata[i].mac[3] = (val >> 16) & 0xff; | ||
| 267 | mx28_fec_pdata[i].mac[4] = (val >> 8) & 0xff; | ||
| 268 | mx28_fec_pdata[i].mac[5] = (val >> 0) & 0xff; | ||
| 269 | } | ||
| 270 | |||
| 271 | return 0; | ||
| 272 | } | ||
| 273 | |||
| 274 | /* | ||
| 275 | * MX28EVK_FLEXCAN_SWITCH is shared between both flexcan controllers | ||
| 276 | */ | ||
| 277 | static int flexcan0_en, flexcan1_en; | ||
| 278 | |||
| 279 | static void mx28evk_flexcan_switch(void) | ||
| 280 | { | ||
| 281 | if (flexcan0_en || flexcan1_en) | ||
| 282 | gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 1); | ||
| 283 | else | ||
| 284 | gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 0); | ||
| 285 | } | ||
| 286 | |||
| 287 | static void mx28evk_flexcan0_switch(int enable) | ||
| 288 | { | ||
| 289 | flexcan0_en = enable; | ||
| 290 | mx28evk_flexcan_switch(); | ||
| 291 | } | ||
| 292 | |||
| 293 | static void mx28evk_flexcan1_switch(int enable) | ||
| 294 | { | ||
| 295 | flexcan1_en = enable; | ||
| 296 | mx28evk_flexcan_switch(); | ||
| 297 | } | ||
| 298 | |||
| 299 | static const struct flexcan_platform_data | ||
| 300 | mx28evk_flexcan_pdata[] __initconst = { | ||
| 301 | { | ||
| 302 | .transceiver_switch = mx28evk_flexcan0_switch, | ||
| 303 | }, { | ||
| 304 | .transceiver_switch = mx28evk_flexcan1_switch, | ||
| 305 | } | ||
| 306 | }; | ||
| 307 | |||
| 308 | /* mxsfb (lcdif) */ | ||
| 309 | static struct fb_videomode mx28evk_video_modes[] = { | ||
| 310 | { | ||
| 311 | .name = "Seiko-43WVF1G", | ||
| 312 | .refresh = 60, | ||
| 313 | .xres = 800, | ||
| 314 | .yres = 480, | ||
| 315 | .pixclock = 29851, /* picosecond (33.5 MHz) */ | ||
| 316 | .left_margin = 89, | ||
| 317 | .right_margin = 164, | ||
| 318 | .upper_margin = 23, | ||
| 319 | .lower_margin = 10, | ||
| 320 | .hsync_len = 10, | ||
| 321 | .vsync_len = 10, | ||
| 322 | .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT | | ||
| 323 | FB_SYNC_DOTCLK_FAILING_ACT, | ||
| 324 | }, | ||
| 325 | }; | ||
| 326 | |||
| 327 | static const struct mxsfb_platform_data mx28evk_mxsfb_pdata __initconst = { | ||
| 328 | .mode_list = mx28evk_video_modes, | ||
| 329 | .mode_count = ARRAY_SIZE(mx28evk_video_modes), | ||
| 330 | .default_bpp = 32, | ||
| 331 | .ld_intf_width = STMLCDIF_24BIT, | ||
| 332 | }; | ||
| 333 | |||
| 334 | static struct mxs_mmc_platform_data mx28evk_mmc_pdata[] __initdata = { | ||
| 335 | { | ||
| 336 | /* mmc0 */ | ||
| 337 | .wp_gpio = MX28EVK_MMC0_WRITE_PROTECT, | ||
| 338 | .flags = SLOTF_8_BIT_CAPABLE, | ||
| 339 | }, { | ||
| 340 | /* mmc1 */ | ||
| 341 | .wp_gpio = MX28EVK_MMC1_WRITE_PROTECT, | ||
| 342 | .flags = SLOTF_8_BIT_CAPABLE, | ||
| 343 | }, | ||
| 344 | }; | ||
| 345 | |||
| 346 | static struct i2c_board_info mxs_i2c0_board_info[] __initdata = { | ||
| 347 | { | ||
| 348 | I2C_BOARD_INFO("sgtl5000", 0x0a), | ||
| 349 | }, | ||
| 350 | }; | ||
| 351 | |||
| 352 | #if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE) | ||
| 353 | static struct regulator_consumer_supply mx28evk_audio_consumer_supplies[] = { | ||
| 354 | REGULATOR_SUPPLY("VDDA", "0-000a"), | ||
| 355 | REGULATOR_SUPPLY("VDDIO", "0-000a"), | ||
| 356 | }; | ||
| 357 | |||
| 358 | static struct regulator_init_data mx28evk_vdd_reg_init_data = { | ||
| 359 | .constraints = { | ||
| 360 | .name = "3V3", | ||
| 361 | .always_on = 1, | ||
| 362 | }, | ||
| 363 | .consumer_supplies = mx28evk_audio_consumer_supplies, | ||
| 364 | .num_consumer_supplies = ARRAY_SIZE(mx28evk_audio_consumer_supplies), | ||
| 365 | }; | ||
| 366 | |||
| 367 | static struct fixed_voltage_config mx28evk_vdd_pdata = { | ||
| 368 | .supply_name = "board-3V3", | ||
| 369 | .microvolts = 3300000, | ||
| 370 | .gpio = -EINVAL, | ||
| 371 | .enabled_at_boot = 1, | ||
| 372 | .init_data = &mx28evk_vdd_reg_init_data, | ||
| 373 | }; | ||
| 374 | static struct platform_device mx28evk_voltage_regulator = { | ||
| 375 | .name = "reg-fixed-voltage", | ||
| 376 | .id = -1, | ||
| 377 | .num_resources = 0, | ||
| 378 | .dev = { | ||
| 379 | .platform_data = &mx28evk_vdd_pdata, | ||
| 380 | }, | ||
| 381 | }; | ||
| 382 | static void __init mx28evk_add_regulators(void) | ||
| 383 | { | ||
| 384 | platform_device_register(&mx28evk_voltage_regulator); | ||
| 385 | } | ||
| 386 | #else | ||
| 387 | static void __init mx28evk_add_regulators(void) {} | ||
| 388 | #endif | ||
| 389 | |||
| 390 | static const struct gpio mx28evk_gpios[] __initconst = { | ||
| 391 | { MX28EVK_LCD_ENABLE, GPIOF_OUT_INIT_HIGH, "lcd-enable" }, | ||
| 392 | { MX28EVK_BL_ENABLE, GPIOF_OUT_INIT_HIGH, "bl-enable" }, | ||
| 393 | { MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT, "flexcan-switch" }, | ||
| 394 | { MX28EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW, "mmc0-slot-power" }, | ||
| 395 | { MX28EVK_MMC1_SLOT_POWER, GPIOF_OUT_INIT_LOW, "mmc1-slot-power" }, | ||
| 396 | { MX28EVK_FEC_PHY_POWER, GPIOF_OUT_INIT_LOW, "fec-phy-power" }, | ||
| 397 | { MX28EVK_FEC_PHY_RESET, GPIOF_DIR_OUT, "fec-phy-reset" }, | ||
| 398 | }; | ||
| 399 | |||
| 400 | static const struct mxs_saif_platform_data | ||
| 401 | mx28evk_mxs_saif_pdata[] __initconst = { | ||
| 402 | /* working on EXTMSTR0 mode (saif0 master, saif1 slave) */ | ||
| 403 | { | ||
| 404 | .master_mode = 1, | ||
| 405 | .master_id = 0, | ||
| 406 | }, { | ||
| 407 | .master_mode = 0, | ||
| 408 | .master_id = 0, | ||
| 409 | }, | ||
| 410 | }; | ||
| 411 | |||
| 412 | static void __init mx28evk_init(void) | ||
| 413 | { | ||
| 414 | int ret; | ||
| 415 | |||
| 416 | mx28_soc_init(); | ||
| 417 | |||
| 418 | mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads)); | ||
| 419 | |||
| 420 | mx28_add_duart(); | ||
| 421 | mx28_add_auart0(); | ||
| 422 | mx28_add_auart3(); | ||
| 423 | |||
| 424 | if (mx28evk_fec_get_mac()) | ||
| 425 | pr_warn("%s: failed on fec mac setup\n", __func__); | ||
| 426 | |||
| 427 | ret = gpio_request_array(mx28evk_gpios, ARRAY_SIZE(mx28evk_gpios)); | ||
| 428 | if (ret) | ||
| 429 | pr_err("One or more GPIOs failed to be requested: %d\n", ret); | ||
| 430 | |||
| 431 | mx28evk_fec_reset(); | ||
| 432 | mx28_add_fec(0, &mx28_fec_pdata[0]); | ||
| 433 | mx28_add_fec(1, &mx28_fec_pdata[1]); | ||
| 434 | |||
| 435 | mx28_add_flexcan(0, &mx28evk_flexcan_pdata[0]); | ||
| 436 | mx28_add_flexcan(1, &mx28evk_flexcan_pdata[1]); | ||
| 437 | |||
| 438 | mx28_add_mxsfb(&mx28evk_mxsfb_pdata); | ||
| 439 | |||
| 440 | mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0); | ||
| 441 | mx28_add_saif(0, &mx28evk_mxs_saif_pdata[0]); | ||
| 442 | mx28_add_saif(1, &mx28evk_mxs_saif_pdata[1]); | ||
| 443 | |||
| 444 | mx28_add_mxs_i2c(0); | ||
| 445 | i2c_register_board_info(0, mxs_i2c0_board_info, | ||
| 446 | ARRAY_SIZE(mxs_i2c0_board_info)); | ||
| 447 | |||
| 448 | mx28evk_add_regulators(); | ||
| 449 | |||
| 450 | mxs_add_platform_device("mxs-sgtl5000", 0, NULL, 0, | ||
| 451 | NULL, 0); | ||
| 452 | |||
| 453 | mx28_add_mxs_mmc(0, &mx28evk_mmc_pdata[0]); | ||
| 454 | mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]); | ||
| 455 | |||
| 456 | mx28_add_rtc_stmp3xxx(); | ||
| 457 | |||
| 458 | gpio_led_register_device(0, &mx28evk_led_data); | ||
| 459 | } | ||
| 460 | |||
| 461 | static void __init mx28evk_timer_init(void) | ||
| 462 | { | ||
| 463 | mx28_clocks_init(); | ||
| 464 | } | ||
| 465 | |||
| 466 | static struct sys_timer mx28evk_timer = { | ||
| 467 | .init = mx28evk_timer_init, | ||
| 468 | }; | ||
| 469 | |||
| 470 | MACHINE_START(MX28EVK, "Freescale MX28 EVK") | ||
| 471 | /* Maintainer: Freescale Semiconductor, Inc. */ | ||
| 472 | .map_io = mx28_map_io, | ||
| 473 | .init_irq = mx28_init_irq, | ||
| 474 | .timer = &mx28evk_timer, | ||
| 475 | .init_machine = mx28evk_init, | ||
| 476 | .restart = mxs_restart, | ||
| 477 | MACHINE_END | ||
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index 8dabfe81d07c..5cbb6376c685 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c | |||
| @@ -12,8 +12,10 @@ | |||
| 12 | 12 | ||
| 13 | #include <linux/clk.h> | 13 | #include <linux/clk.h> |
| 14 | #include <linux/clkdev.h> | 14 | #include <linux/clkdev.h> |
| 15 | #include <linux/can/platform/flexcan.h> | ||
| 16 | #include <linux/delay.h> | ||
| 15 | #include <linux/err.h> | 17 | #include <linux/err.h> |
| 16 | #include <linux/init.h> | 18 | #include <linux/gpio.h> |
| 17 | #include <linux/init.h> | 19 | #include <linux/init.h> |
| 18 | #include <linux/irqdomain.h> | 20 | #include <linux/irqdomain.h> |
| 19 | #include <linux/micrel_phy.h> | 21 | #include <linux/micrel_phy.h> |
| @@ -21,9 +23,12 @@ | |||
| 21 | #include <linux/of_irq.h> | 23 | #include <linux/of_irq.h> |
| 22 | #include <linux/of_platform.h> | 24 | #include <linux/of_platform.h> |
| 23 | #include <linux/phy.h> | 25 | #include <linux/phy.h> |
| 26 | #include <linux/pinctrl/consumer.h> | ||
| 24 | #include <asm/mach/arch.h> | 27 | #include <asm/mach/arch.h> |
| 25 | #include <asm/mach/time.h> | 28 | #include <asm/mach/time.h> |
| 26 | #include <mach/common.h> | 29 | #include <mach/common.h> |
| 30 | #include <mach/digctl.h> | ||
| 31 | #include <mach/mxs.h> | ||
| 27 | 32 | ||
| 28 | static struct fb_videomode mx23evk_video_modes[] = { | 33 | static struct fb_videomode mx23evk_video_modes[] = { |
| 29 | { | 34 | { |
| @@ -99,9 +104,40 @@ static struct fb_videomode apx4devkit_video_modes[] = { | |||
| 99 | 104 | ||
| 100 | static struct mxsfb_platform_data mxsfb_pdata __initdata; | 105 | static struct mxsfb_platform_data mxsfb_pdata __initdata; |
| 101 | 106 | ||
| 107 | /* | ||
| 108 | * MX28EVK_FLEXCAN_SWITCH is shared between both flexcan controllers | ||
| 109 | */ | ||
| 110 | #define MX28EVK_FLEXCAN_SWITCH MXS_GPIO_NR(2, 13) | ||
| 111 | |||
| 112 | static int flexcan0_en, flexcan1_en; | ||
| 113 | |||
| 114 | static void mx28evk_flexcan_switch(void) | ||
| 115 | { | ||
| 116 | if (flexcan0_en || flexcan1_en) | ||
| 117 | gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 1); | ||
| 118 | else | ||
| 119 | gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 0); | ||
| 120 | } | ||
| 121 | |||
| 122 | static void mx28evk_flexcan0_switch(int enable) | ||
| 123 | { | ||
| 124 | flexcan0_en = enable; | ||
| 125 | mx28evk_flexcan_switch(); | ||
| 126 | } | ||
| 127 | |||
| 128 | static void mx28evk_flexcan1_switch(int enable) | ||
| 129 | { | ||
| 130 | flexcan1_en = enable; | ||
| 131 | mx28evk_flexcan_switch(); | ||
| 132 | } | ||
| 133 | |||
| 134 | static struct flexcan_platform_data flexcan_pdata[2]; | ||
| 135 | |||
| 102 | static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = { | 136 | static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = { |
| 103 | OF_DEV_AUXDATA("fsl,imx23-lcdif", 0x80030000, NULL, &mxsfb_pdata), | 137 | OF_DEV_AUXDATA("fsl,imx23-lcdif", 0x80030000, NULL, &mxsfb_pdata), |
| 104 | OF_DEV_AUXDATA("fsl,imx28-lcdif", 0x80030000, NULL, &mxsfb_pdata), | 138 | OF_DEV_AUXDATA("fsl,imx28-lcdif", 0x80030000, NULL, &mxsfb_pdata), |
| 139 | OF_DEV_AUXDATA("fsl,imx28-flexcan", 0x80032000, NULL, &flexcan_pdata[0]), | ||
| 140 | OF_DEV_AUXDATA("fsl,imx28-flexcan", 0x80034000, NULL, &flexcan_pdata[1]), | ||
| 105 | { /* sentinel */ } | 141 | { /* sentinel */ } |
| 106 | }; | 142 | }; |
| 107 | 143 | ||
| @@ -237,11 +273,21 @@ static void __init imx28_evk_init(void) | |||
| 237 | mxsfb_pdata.mode_count = ARRAY_SIZE(mx28evk_video_modes); | 273 | mxsfb_pdata.mode_count = ARRAY_SIZE(mx28evk_video_modes); |
| 238 | mxsfb_pdata.default_bpp = 32; | 274 | mxsfb_pdata.default_bpp = 32; |
| 239 | mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; | 275 | mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; |
| 276 | |||
| 277 | mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0); | ||
| 278 | } | ||
| 279 | |||
| 280 | static void __init imx28_evk_post_init(void) | ||
| 281 | { | ||
| 282 | if (!gpio_request_one(MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT, | ||
| 283 | "flexcan-switch")) { | ||
| 284 | flexcan_pdata[0].transceiver_switch = mx28evk_flexcan0_switch; | ||
| 285 | flexcan_pdata[1].transceiver_switch = mx28evk_flexcan1_switch; | ||
| 286 | } | ||
| 240 | } | 287 | } |
| 241 | 288 | ||
| 242 | static void __init m28evk_init(void) | 289 | static void __init m28evk_init(void) |
| 243 | { | 290 | { |
| 244 | enable_clk_enet_out(); | ||
| 245 | update_fec_mac_prop(OUI_DENX); | 291 | update_fec_mac_prop(OUI_DENX); |
| 246 | 292 | ||
| 247 | mxsfb_pdata.mode_list = m28evk_video_modes; | 293 | mxsfb_pdata.mode_list = m28evk_video_modes; |
| @@ -270,6 +316,80 @@ static void __init apx4devkit_init(void) | |||
| 270 | mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; | 316 | mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; |
| 271 | } | 317 | } |
| 272 | 318 | ||
| 319 | #define ENET0_MDC__GPIO_4_0 MXS_GPIO_NR(4, 0) | ||
| 320 | #define ENET0_MDIO__GPIO_4_1 MXS_GPIO_NR(4, 1) | ||
| 321 | #define ENET0_RX_EN__GPIO_4_2 MXS_GPIO_NR(4, 2) | ||
| 322 | #define ENET0_RXD0__GPIO_4_3 MXS_GPIO_NR(4, 3) | ||
| 323 | #define ENET0_RXD1__GPIO_4_4 MXS_GPIO_NR(4, 4) | ||
| 324 | #define ENET0_TX_EN__GPIO_4_6 MXS_GPIO_NR(4, 6) | ||
| 325 | #define ENET0_TXD0__GPIO_4_7 MXS_GPIO_NR(4, 7) | ||
| 326 | #define ENET0_TXD1__GPIO_4_8 MXS_GPIO_NR(4, 8) | ||
| 327 | #define ENET_CLK__GPIO_4_16 MXS_GPIO_NR(4, 16) | ||
| 328 | |||
| 329 | #define TX28_FEC_PHY_POWER MXS_GPIO_NR(3, 29) | ||
| 330 | #define TX28_FEC_PHY_RESET MXS_GPIO_NR(4, 13) | ||
| 331 | #define TX28_FEC_nINT MXS_GPIO_NR(4, 5) | ||
| 332 | |||
| 333 | static const struct gpio tx28_gpios[] __initconst = { | ||
| 334 | { ENET0_MDC__GPIO_4_0, GPIOF_OUT_INIT_LOW, "GPIO_4_0" }, | ||
| 335 | { ENET0_MDIO__GPIO_4_1, GPIOF_OUT_INIT_LOW, "GPIO_4_1" }, | ||
| 336 | { ENET0_RX_EN__GPIO_4_2, GPIOF_OUT_INIT_LOW, "GPIO_4_2" }, | ||
| 337 | { ENET0_RXD0__GPIO_4_3, GPIOF_OUT_INIT_LOW, "GPIO_4_3" }, | ||
| 338 | { ENET0_RXD1__GPIO_4_4, GPIOF_OUT_INIT_LOW, "GPIO_4_4" }, | ||
| 339 | { ENET0_TX_EN__GPIO_4_6, GPIOF_OUT_INIT_LOW, "GPIO_4_6" }, | ||
| 340 | { ENET0_TXD0__GPIO_4_7, GPIOF_OUT_INIT_LOW, "GPIO_4_7" }, | ||
| 341 | { ENET0_TXD1__GPIO_4_8, GPIOF_OUT_INIT_LOW, "GPIO_4_8" }, | ||
| 342 | { ENET_CLK__GPIO_4_16, GPIOF_OUT_INIT_LOW, "GPIO_4_16" }, | ||
| 343 | { TX28_FEC_PHY_POWER, GPIOF_OUT_INIT_LOW, "fec-phy-power" }, | ||
| 344 | { TX28_FEC_PHY_RESET, GPIOF_OUT_INIT_LOW, "fec-phy-reset" }, | ||
| 345 | { TX28_FEC_nINT, GPIOF_DIR_IN, "fec-int" }, | ||
| 346 | }; | ||
| 347 | |||
| 348 | static void __init tx28_post_init(void) | ||
| 349 | { | ||
| 350 | struct device_node *np; | ||
| 351 | struct platform_device *pdev; | ||
| 352 | struct pinctrl *pctl; | ||
| 353 | int ret; | ||
| 354 | |||
| 355 | enable_clk_enet_out(); | ||
| 356 | |||
| 357 | np = of_find_compatible_node(NULL, NULL, "fsl,imx28-fec"); | ||
| 358 | pdev = of_find_device_by_node(np); | ||
| 359 | if (!pdev) { | ||
| 360 | pr_err("%s: failed to find fec device\n", __func__); | ||
| 361 | return; | ||
| 362 | } | ||
| 363 | |||
| 364 | pctl = pinctrl_get_select(&pdev->dev, "gpio_mode"); | ||
| 365 | if (IS_ERR(pctl)) { | ||
| 366 | pr_err("%s: failed to get pinctrl state\n", __func__); | ||
| 367 | return; | ||
| 368 | } | ||
| 369 | |||
| 370 | ret = gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios)); | ||
| 371 | if (ret) { | ||
| 372 | pr_err("%s: failed to request gpios: %d\n", __func__, ret); | ||
| 373 | return; | ||
| 374 | } | ||
| 375 | |||
| 376 | /* Power up fec phy */ | ||
| 377 | gpio_set_value(TX28_FEC_PHY_POWER, 1); | ||
| 378 | msleep(26); /* 25ms according to data sheet */ | ||
| 379 | |||
| 380 | /* Mode strap pins */ | ||
| 381 | gpio_set_value(ENET0_RX_EN__GPIO_4_2, 1); | ||
| 382 | gpio_set_value(ENET0_RXD0__GPIO_4_3, 1); | ||
| 383 | gpio_set_value(ENET0_RXD1__GPIO_4_4, 1); | ||
| 384 | |||
| 385 | udelay(100); /* minimum assertion time for nRST */ | ||
| 386 | |||
| 387 | /* Deasserting FEC PHY RESET */ | ||
| 388 | gpio_set_value(TX28_FEC_PHY_RESET, 1); | ||
| 389 | |||
| 390 | pinctrl_put(pctl); | ||
| 391 | } | ||
| 392 | |||
| 273 | static void __init mxs_machine_init(void) | 393 | static void __init mxs_machine_init(void) |
| 274 | { | 394 | { |
| 275 | if (of_machine_is_compatible("fsl,imx28-evk")) | 395 | if (of_machine_is_compatible("fsl,imx28-evk")) |
| @@ -283,22 +403,20 @@ static void __init mxs_machine_init(void) | |||
| 283 | 403 | ||
| 284 | of_platform_populate(NULL, of_default_bus_match_table, | 404 | of_platform_populate(NULL, of_default_bus_match_table, |
| 285 | mxs_auxdata_lookup, NULL); | 405 | mxs_auxdata_lookup, NULL); |
| 406 | |||
| 407 | if (of_machine_is_compatible("karo,tx28")) | ||
| 408 | tx28_post_init(); | ||
| 409 | |||
| 410 | if (of_machine_is_compatible("fsl,imx28-evk")) | ||
| 411 | imx28_evk_post_init(); | ||
| 286 | } | 412 | } |
| 287 | 413 | ||
| 288 | static const char *imx23_dt_compat[] __initdata = { | 414 | static const char *imx23_dt_compat[] __initdata = { |
| 289 | "fsl,imx23-evk", | ||
| 290 | "fsl,stmp378x_devb" | ||
| 291 | "olimex,imx23-olinuxino", | ||
| 292 | "fsl,imx23", | 415 | "fsl,imx23", |
| 293 | NULL, | 416 | NULL, |
| 294 | }; | 417 | }; |
| 295 | 418 | ||
| 296 | static const char *imx28_dt_compat[] __initdata = { | 419 | static const char *imx28_dt_compat[] __initdata = { |
| 297 | "bluegiga,apx4devkit", | ||
| 298 | "crystalfontz,cfa10036", | ||
| 299 | "denx,m28evk", | ||
| 300 | "fsl,imx28-evk", | ||
| 301 | "karo,tx28", | ||
| 302 | "fsl,imx28", | 420 | "fsl,imx28", |
| 303 | NULL, | 421 | NULL, |
| 304 | }; | 422 | }; |
diff --git a/arch/arm/mach-mxs/mach-stmp378x_devb.c b/arch/arm/mach-mxs/mach-stmp378x_devb.c deleted file mode 100644 index 6548965e4a76..000000000000 --- a/arch/arm/mach-mxs/mach-stmp378x_devb.c +++ /dev/null | |||
| @@ -1,123 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * board setup for STMP378x-Development-Board | ||
| 3 | * | ||
| 4 | * based on mx23evk board setup and information gained form the original | ||
| 5 | * plat-stmp based board setup, now converted to mach-mxs. | ||
| 6 | * | ||
| 7 | * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 8 | * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; version 2 of the License. | ||
| 13 | * | ||
| 14 | * This program is distributed in the hope that it will be useful, | ||
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 17 | * GNU General Public License for more details. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #include <linux/platform_device.h> | ||
| 21 | #include <linux/gpio.h> | ||
| 22 | #include <linux/spi/spi.h> | ||
| 23 | |||
| 24 | #include <asm/mach-types.h> | ||
| 25 | #include <asm/mach/arch.h> | ||
| 26 | #include <asm/mach/time.h> | ||
| 27 | |||
| 28 | #include <mach/common.h> | ||
| 29 | #include <mach/iomux-mx23.h> | ||
| 30 | |||
| 31 | #include "devices-mx23.h" | ||
| 32 | |||
| 33 | #define STMP378X_DEVB_MMC0_WRITE_PROTECT MXS_GPIO_NR(1, 30) | ||
| 34 | #define STMP378X_DEVB_MMC0_SLOT_POWER MXS_GPIO_NR(1, 29) | ||
| 35 | |||
| 36 | #define STMP378X_DEVB_PAD_AUART (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL) | ||
| 37 | |||
| 38 | static const iomux_cfg_t stmp378x_dvb_pads[] __initconst = { | ||
| 39 | /* duart (extended setup missing in old boardcode, too */ | ||
| 40 | MX23_PAD_PWM0__DUART_RX, | ||
| 41 | MX23_PAD_PWM1__DUART_TX, | ||
| 42 | |||
| 43 | /* auart */ | ||
| 44 | MX23_PAD_AUART1_RX__AUART1_RX | STMP378X_DEVB_PAD_AUART, | ||
| 45 | MX23_PAD_AUART1_TX__AUART1_TX | STMP378X_DEVB_PAD_AUART, | ||
| 46 | MX23_PAD_AUART1_CTS__AUART1_CTS | STMP378X_DEVB_PAD_AUART, | ||
| 47 | MX23_PAD_AUART1_RTS__AUART1_RTS | STMP378X_DEVB_PAD_AUART, | ||
| 48 | |||
| 49 | /* mmc */ | ||
| 50 | MX23_PAD_SSP1_DATA0__SSP1_DATA0 | | ||
| 51 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 52 | MX23_PAD_SSP1_DATA1__SSP1_DATA1 | | ||
| 53 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 54 | MX23_PAD_SSP1_DATA2__SSP1_DATA2 | | ||
| 55 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 56 | MX23_PAD_SSP1_DATA3__SSP1_DATA3 | | ||
| 57 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 58 | MX23_PAD_SSP1_CMD__SSP1_CMD | | ||
| 59 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 60 | MX23_PAD_SSP1_DETECT__SSP1_DETECT | | ||
| 61 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 62 | MX23_PAD_SSP1_SCK__SSP1_SCK | | ||
| 63 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 64 | MX23_PAD_PWM4__GPIO_1_30 | MXS_PAD_CTRL, /* write protect */ | ||
| 65 | MX23_PAD_PWM3__GPIO_1_29 | MXS_PAD_CTRL, /* power enable */ | ||
| 66 | }; | ||
| 67 | |||
| 68 | static struct mxs_mmc_platform_data stmp378x_dvb_mmc_pdata __initdata = { | ||
| 69 | .wp_gpio = STMP378X_DEVB_MMC0_WRITE_PROTECT, | ||
| 70 | }; | ||
| 71 | |||
| 72 | static struct spi_board_info spi_board_info[] __initdata = { | ||
| 73 | #if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE) | ||
| 74 | { | ||
| 75 | .modalias = "enc28j60", | ||
| 76 | .max_speed_hz = 6 * 1000 * 1000, | ||
| 77 | .bus_num = 1, | ||
| 78 | .chip_select = 0, | ||
| 79 | .platform_data = NULL, | ||
| 80 | }, | ||
| 81 | #endif | ||
| 82 | }; | ||
| 83 | |||
| 84 | static void __init stmp378x_dvb_init(void) | ||
| 85 | { | ||
| 86 | int ret; | ||
| 87 | |||
| 88 | mx23_soc_init(); | ||
| 89 | |||
| 90 | mxs_iomux_setup_multiple_pads(stmp378x_dvb_pads, | ||
| 91 | ARRAY_SIZE(stmp378x_dvb_pads)); | ||
| 92 | |||
| 93 | mx23_add_duart(); | ||
| 94 | mx23_add_auart0(); | ||
| 95 | mx23_add_rtc_stmp3xxx(); | ||
| 96 | |||
| 97 | /* power on mmc slot */ | ||
| 98 | ret = gpio_request_one(STMP378X_DEVB_MMC0_SLOT_POWER, | ||
| 99 | GPIOF_OUT_INIT_LOW, "mmc0-slot-power"); | ||
| 100 | if (ret) | ||
| 101 | pr_warn("could not power mmc (%d)\n", ret); | ||
| 102 | |||
| 103 | mx23_add_mxs_mmc(0, &stmp378x_dvb_mmc_pdata); | ||
| 104 | |||
| 105 | spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); | ||
| 106 | } | ||
| 107 | |||
| 108 | static void __init stmp378x_dvb_timer_init(void) | ||
| 109 | { | ||
| 110 | mx23_clocks_init(); | ||
| 111 | } | ||
| 112 | |||
| 113 | static struct sys_timer stmp378x_dvb_timer = { | ||
| 114 | .init = stmp378x_dvb_timer_init, | ||
| 115 | }; | ||
| 116 | |||
| 117 | MACHINE_START(STMP378X, "STMP378X") | ||
| 118 | .map_io = mx23_map_io, | ||
| 119 | .init_irq = mx23_init_irq, | ||
| 120 | .timer = &stmp378x_dvb_timer, | ||
| 121 | .init_machine = stmp378x_dvb_init, | ||
| 122 | .restart = mxs_restart, | ||
| 123 | MACHINE_END | ||
diff --git a/arch/arm/mach-mxs/mach-tx28.c b/arch/arm/mach-mxs/mach-tx28.c deleted file mode 100644 index 8837029de1a4..000000000000 --- a/arch/arm/mach-mxs/mach-tx28.c +++ /dev/null | |||
| @@ -1,184 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 <LW@KARO-electronics.de> | ||
| 3 | * | ||
| 4 | * based on: mach-mx28_evk.c | ||
| 5 | * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or | ||
| 8 | * modify it under the terms of the GNU General Public License | ||
| 9 | * version 2 as published by the Free Software Foundation | ||
| 10 | */ | ||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/gpio.h> | ||
| 13 | #include <linux/leds.h> | ||
| 14 | #include <linux/platform_device.h> | ||
| 15 | #include <linux/spi/spi.h> | ||
| 16 | #include <linux/spi/spi_gpio.h> | ||
| 17 | #include <linux/i2c.h> | ||
| 18 | |||
| 19 | #include <asm/mach/arch.h> | ||
| 20 | #include <asm/mach/time.h> | ||
| 21 | |||
| 22 | #include <mach/common.h> | ||
| 23 | #include <mach/iomux-mx28.h> | ||
| 24 | |||
| 25 | #include "devices-mx28.h" | ||
| 26 | #include "module-tx28.h" | ||
| 27 | |||
| 28 | #define TX28_STK5_GPIO_LED MXS_GPIO_NR(4, 10) | ||
| 29 | |||
| 30 | static const iomux_cfg_t tx28_stk5v3_pads[] __initconst = { | ||
| 31 | /* LED */ | ||
| 32 | MX28_PAD_ENET0_RXD3__GPIO_4_10 | | ||
| 33 | MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL, | ||
| 34 | |||
| 35 | /* framebuffer */ | ||
| 36 | #define LCD_MODE (MXS_PAD_3V3 | MXS_PAD_4MA) | ||
| 37 | MX28_PAD_LCD_D00__LCD_D0 | LCD_MODE, | ||
| 38 | MX28_PAD_LCD_D01__LCD_D1 | LCD_MODE, | ||
| 39 | MX28_PAD_LCD_D02__LCD_D2 | LCD_MODE, | ||
| 40 | MX28_PAD_LCD_D03__LCD_D3 | LCD_MODE, | ||
| 41 | MX28_PAD_LCD_D04__LCD_D4 | LCD_MODE, | ||
| 42 | MX28_PAD_LCD_D05__LCD_D5 | LCD_MODE, | ||
| 43 | MX28_PAD_LCD_D06__LCD_D6 | LCD_MODE, | ||
| 44 | MX28_PAD_LCD_D07__LCD_D7 | LCD_MODE, | ||
| 45 | MX28_PAD_LCD_D08__LCD_D8 | LCD_MODE, | ||
| 46 | MX28_PAD_LCD_D09__LCD_D9 | LCD_MODE, | ||
| 47 | MX28_PAD_LCD_D10__LCD_D10 | LCD_MODE, | ||
| 48 | MX28_PAD_LCD_D11__LCD_D11 | LCD_MODE, | ||
| 49 | MX28_PAD_LCD_D12__LCD_D12 | LCD_MODE, | ||
| 50 | MX28_PAD_LCD_D13__LCD_D13 | LCD_MODE, | ||
| 51 | MX28_PAD_LCD_D14__LCD_D14 | LCD_MODE, | ||
| 52 | MX28_PAD_LCD_D15__LCD_D15 | LCD_MODE, | ||
| 53 | MX28_PAD_LCD_D16__LCD_D16 | LCD_MODE, | ||
| 54 | MX28_PAD_LCD_D17__LCD_D17 | LCD_MODE, | ||
| 55 | MX28_PAD_LCD_D18__LCD_D18 | LCD_MODE, | ||
| 56 | MX28_PAD_LCD_D19__LCD_D19 | LCD_MODE, | ||
| 57 | MX28_PAD_LCD_D20__LCD_D20 | LCD_MODE, | ||
| 58 | MX28_PAD_LCD_D21__LCD_D21 | LCD_MODE, | ||
| 59 | MX28_PAD_LCD_D22__LCD_D22 | LCD_MODE, | ||
| 60 | MX28_PAD_LCD_D23__LCD_D23 | LCD_MODE, | ||
| 61 | MX28_PAD_LCD_RD_E__LCD_VSYNC | LCD_MODE, | ||
| 62 | MX28_PAD_LCD_WR_RWN__LCD_HSYNC | LCD_MODE, | ||
| 63 | MX28_PAD_LCD_RS__LCD_DOTCLK | LCD_MODE, | ||
| 64 | MX28_PAD_LCD_CS__LCD_CS | LCD_MODE, | ||
| 65 | MX28_PAD_LCD_VSYNC__LCD_VSYNC | LCD_MODE, | ||
| 66 | MX28_PAD_LCD_HSYNC__LCD_HSYNC | LCD_MODE, | ||
| 67 | MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | LCD_MODE, | ||
| 68 | MX28_PAD_LCD_ENABLE__GPIO_1_31 | LCD_MODE, | ||
| 69 | MX28_PAD_LCD_RESET__GPIO_3_30 | LCD_MODE, | ||
| 70 | MX28_PAD_PWM0__PWM_0 | LCD_MODE, | ||
| 71 | |||
| 72 | /* UART1 */ | ||
| 73 | MX28_PAD_AUART0_CTS__DUART_RX, | ||
| 74 | MX28_PAD_AUART0_RTS__DUART_TX, | ||
| 75 | MX28_PAD_AUART0_TX__DUART_RTS, | ||
| 76 | MX28_PAD_AUART0_RX__DUART_CTS, | ||
| 77 | |||
| 78 | /* UART2 */ | ||
| 79 | MX28_PAD_AUART1_RX__AUART1_RX, | ||
| 80 | MX28_PAD_AUART1_TX__AUART1_TX, | ||
| 81 | MX28_PAD_AUART1_RTS__AUART1_RTS, | ||
| 82 | MX28_PAD_AUART1_CTS__AUART1_CTS, | ||
| 83 | |||
| 84 | /* CAN */ | ||
| 85 | MX28_PAD_GPMI_RDY2__CAN0_TX, | ||
| 86 | MX28_PAD_GPMI_RDY3__CAN0_RX, | ||
| 87 | |||
| 88 | /* I2C */ | ||
| 89 | MX28_PAD_I2C0_SCL__I2C0_SCL, | ||
| 90 | MX28_PAD_I2C0_SDA__I2C0_SDA, | ||
| 91 | |||
| 92 | /* TSC2007 */ | ||
| 93 | MX28_PAD_SAIF0_MCLK__GPIO_3_20 | MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP, | ||
| 94 | |||
| 95 | /* MMC0 */ | ||
| 96 | MX28_PAD_SSP0_DATA0__SSP0_D0 | | ||
| 97 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 98 | MX28_PAD_SSP0_DATA1__SSP0_D1 | | ||
| 99 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 100 | MX28_PAD_SSP0_DATA2__SSP0_D2 | | ||
| 101 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 102 | MX28_PAD_SSP0_DATA3__SSP0_D3 | | ||
| 103 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 104 | MX28_PAD_SSP0_CMD__SSP0_CMD | | ||
| 105 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 106 | MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | | ||
| 107 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 108 | MX28_PAD_SSP0_SCK__SSP0_SCK | | ||
| 109 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 110 | }; | ||
| 111 | |||
| 112 | static const struct gpio_led tx28_stk5v3_leds[] __initconst = { | ||
| 113 | { | ||
| 114 | .name = "GPIO-LED", | ||
| 115 | .default_trigger = "heartbeat", | ||
| 116 | .gpio = TX28_STK5_GPIO_LED, | ||
| 117 | }, | ||
| 118 | }; | ||
| 119 | |||
| 120 | static const struct gpio_led_platform_data tx28_stk5v3_led_data __initconst = { | ||
| 121 | .leds = tx28_stk5v3_leds, | ||
| 122 | .num_leds = ARRAY_SIZE(tx28_stk5v3_leds), | ||
| 123 | }; | ||
| 124 | |||
| 125 | static struct spi_board_info tx28_spi_board_info[] = { | ||
| 126 | { | ||
| 127 | .modalias = "spidev", | ||
| 128 | .max_speed_hz = 20000000, | ||
| 129 | .bus_num = 0, | ||
| 130 | .chip_select = 1, | ||
| 131 | .controller_data = (void *)SPI_GPIO_NO_CHIPSELECT, | ||
| 132 | .mode = SPI_MODE_0, | ||
| 133 | }, | ||
| 134 | }; | ||
| 135 | |||
| 136 | static struct i2c_board_info tx28_stk5v3_i2c_boardinfo[] __initdata = { | ||
| 137 | { | ||
| 138 | I2C_BOARD_INFO("ds1339", 0x68), | ||
| 139 | }, | ||
| 140 | }; | ||
| 141 | |||
| 142 | static struct mxs_mmc_platform_data tx28_mmc0_pdata __initdata = { | ||
| 143 | .wp_gpio = -EINVAL, | ||
| 144 | .flags = SLOTF_4_BIT_CAPABLE, | ||
| 145 | }; | ||
| 146 | |||
| 147 | static void __init tx28_stk5v3_init(void) | ||
| 148 | { | ||
| 149 | mx28_soc_init(); | ||
| 150 | |||
| 151 | mxs_iomux_setup_multiple_pads(tx28_stk5v3_pads, | ||
| 152 | ARRAY_SIZE(tx28_stk5v3_pads)); | ||
| 153 | |||
| 154 | mx28_add_duart(); /* UART1 */ | ||
| 155 | mx28_add_auart(1); /* UART2 */ | ||
| 156 | |||
| 157 | tx28_add_fec0(); | ||
| 158 | /* spi via ssp will be added when available */ | ||
| 159 | spi_register_board_info(tx28_spi_board_info, | ||
| 160 | ARRAY_SIZE(tx28_spi_board_info)); | ||
| 161 | gpio_led_register_device(0, &tx28_stk5v3_led_data); | ||
| 162 | mx28_add_mxs_i2c(0); | ||
| 163 | i2c_register_board_info(0, tx28_stk5v3_i2c_boardinfo, | ||
| 164 | ARRAY_SIZE(tx28_stk5v3_i2c_boardinfo)); | ||
| 165 | mx28_add_mxs_mmc(0, &tx28_mmc0_pdata); | ||
| 166 | mx28_add_rtc_stmp3xxx(); | ||
| 167 | } | ||
| 168 | |||
| 169 | static void __init tx28_timer_init(void) | ||
| 170 | { | ||
| 171 | mx28_clocks_init(); | ||
| 172 | } | ||
| 173 | |||
| 174 | static struct sys_timer tx28_timer = { | ||
| 175 | .init = tx28_timer_init, | ||
| 176 | }; | ||
| 177 | |||
| 178 | MACHINE_START(TX28, "Ka-Ro electronics TX28 module") | ||
| 179 | .map_io = mx28_map_io, | ||
| 180 | .init_irq = mx28_init_irq, | ||
| 181 | .timer = &tx28_timer, | ||
| 182 | .init_machine = tx28_stk5v3_init, | ||
| 183 | .restart = mxs_restart, | ||
| 184 | MACHINE_END | ||
diff --git a/arch/arm/mach-mxs/mm.c b/arch/arm/mach-mxs/mm.c index dccb67a9e7c4..a4294aa9f301 100644 --- a/arch/arm/mach-mxs/mm.c +++ b/arch/arm/mach-mxs/mm.c | |||
| @@ -13,14 +13,11 @@ | |||
| 13 | 13 | ||
| 14 | #include <linux/mm.h> | 14 | #include <linux/mm.h> |
| 15 | #include <linux/init.h> | 15 | #include <linux/init.h> |
| 16 | #include <linux/pinctrl/machine.h> | ||
| 17 | 16 | ||
| 18 | #include <asm/mach/map.h> | 17 | #include <asm/mach/map.h> |
| 19 | 18 | ||
| 20 | #include <mach/mx23.h> | 19 | #include <mach/mx23.h> |
| 21 | #include <mach/mx28.h> | 20 | #include <mach/mx28.h> |
| 22 | #include <mach/common.h> | ||
| 23 | #include <mach/iomux.h> | ||
| 24 | 21 | ||
| 25 | /* | 22 | /* |
| 26 | * Define the MX23 memory map. | 23 | * Define the MX23 memory map. |
| @@ -48,43 +45,7 @@ void __init mx23_map_io(void) | |||
| 48 | iotable_init(mx23_io_desc, ARRAY_SIZE(mx23_io_desc)); | 45 | iotable_init(mx23_io_desc, ARRAY_SIZE(mx23_io_desc)); |
| 49 | } | 46 | } |
| 50 | 47 | ||
| 51 | void __init mx23_init_irq(void) | ||
| 52 | { | ||
| 53 | icoll_init_irq(); | ||
| 54 | } | ||
| 55 | |||
| 56 | void __init mx28_map_io(void) | 48 | void __init mx28_map_io(void) |
| 57 | { | 49 | { |
| 58 | iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc)); | 50 | iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc)); |
| 59 | } | 51 | } |
| 60 | |||
| 61 | void __init mx28_init_irq(void) | ||
| 62 | { | ||
| 63 | icoll_init_irq(); | ||
| 64 | } | ||
| 65 | |||
| 66 | void __init mx23_soc_init(void) | ||
| 67 | { | ||
| 68 | pinctrl_provide_dummies(); | ||
| 69 | |||
| 70 | mxs_add_dma("imx23-dma-apbh", MX23_APBH_DMA_BASE_ADDR); | ||
| 71 | mxs_add_dma("imx23-dma-apbx", MX23_APBX_DMA_BASE_ADDR); | ||
| 72 | |||
| 73 | mxs_add_gpio("imx23-gpio", 0, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO0); | ||
| 74 | mxs_add_gpio("imx23-gpio", 1, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO1); | ||
| 75 | mxs_add_gpio("imx23-gpio", 2, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO2); | ||
| 76 | } | ||
| 77 | |||
| 78 | void __init mx28_soc_init(void) | ||
| 79 | { | ||
| 80 | pinctrl_provide_dummies(); | ||
| 81 | |||
| 82 | mxs_add_dma("imx28-dma-apbh", MX23_APBH_DMA_BASE_ADDR); | ||
| 83 | mxs_add_dma("imx28-dma-apbx", MX23_APBX_DMA_BASE_ADDR); | ||
| 84 | |||
| 85 | mxs_add_gpio("imx28-gpio", 0, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO0); | ||
| 86 | mxs_add_gpio("imx28-gpio", 1, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO1); | ||
| 87 | mxs_add_gpio("imx28-gpio", 2, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO2); | ||
| 88 | mxs_add_gpio("imx28-gpio", 3, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO3); | ||
| 89 | mxs_add_gpio("imx28-gpio", 4, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO4); | ||
| 90 | } | ||
diff --git a/arch/arm/mach-mxs/module-tx28.c b/arch/arm/mach-mxs/module-tx28.c deleted file mode 100644 index 0f71f82101cc..000000000000 --- a/arch/arm/mach-mxs/module-tx28.c +++ /dev/null | |||
| @@ -1,160 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 <LW@KARO-electronics.de> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it under | ||
| 5 | * the terms of the GNU General Public License version 2 as published by the | ||
| 6 | * Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <linux/delay.h> | ||
| 10 | #include <linux/fec.h> | ||
| 11 | #include <linux/gpio.h> | ||
| 12 | |||
| 13 | #include <mach/iomux-mx28.h> | ||
| 14 | #include "devices-mx28.h" | ||
| 15 | |||
| 16 | #include "module-tx28.h" | ||
| 17 | |||
| 18 | #define TX28_FEC_PHY_POWER MXS_GPIO_NR(3, 29) | ||
| 19 | #define TX28_FEC_PHY_RESET MXS_GPIO_NR(4, 13) | ||
| 20 | |||
| 21 | static const iomux_cfg_t tx28_fec_gpio_pads[] __initconst = { | ||
| 22 | /* PHY POWER */ | ||
| 23 | MX28_PAD_PWM4__GPIO_3_29 | | ||
| 24 | MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3, | ||
| 25 | /* PHY RESET */ | ||
| 26 | MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | | ||
| 27 | MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3, | ||
| 28 | /* Mode strap pins 0-2 */ | ||
| 29 | MX28_PAD_ENET0_RXD0__GPIO_4_3 | | ||
| 30 | MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3, | ||
| 31 | MX28_PAD_ENET0_RXD1__GPIO_4_4 | | ||
| 32 | MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3, | ||
| 33 | MX28_PAD_ENET0_RX_EN__GPIO_4_2 | | ||
| 34 | MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3, | ||
| 35 | /* nINT */ | ||
| 36 | MX28_PAD_ENET0_TX_CLK__GPIO_4_5 | | ||
| 37 | MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3, | ||
| 38 | |||
| 39 | MX28_PAD_ENET0_MDC__GPIO_4_0, | ||
| 40 | MX28_PAD_ENET0_MDIO__GPIO_4_1, | ||
| 41 | MX28_PAD_ENET0_TX_EN__GPIO_4_6, | ||
| 42 | MX28_PAD_ENET0_TXD0__GPIO_4_7, | ||
| 43 | MX28_PAD_ENET0_TXD1__GPIO_4_8, | ||
| 44 | MX28_PAD_ENET_CLK__GPIO_4_16, | ||
| 45 | }; | ||
| 46 | |||
| 47 | #define FEC_MODE (MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3) | ||
| 48 | static const iomux_cfg_t tx28_fec0_pads[] __initconst = { | ||
| 49 | MX28_PAD_ENET0_MDC__ENET0_MDC | FEC_MODE, | ||
| 50 | MX28_PAD_ENET0_MDIO__ENET0_MDIO | FEC_MODE, | ||
| 51 | MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | FEC_MODE, | ||
| 52 | MX28_PAD_ENET0_RXD0__ENET0_RXD0 | FEC_MODE, | ||
| 53 | MX28_PAD_ENET0_RXD1__ENET0_RXD1 | FEC_MODE, | ||
| 54 | MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | FEC_MODE, | ||
| 55 | MX28_PAD_ENET0_TXD0__ENET0_TXD0 | FEC_MODE, | ||
| 56 | MX28_PAD_ENET0_TXD1__ENET0_TXD1 | FEC_MODE, | ||
| 57 | MX28_PAD_ENET_CLK__CLKCTRL_ENET | FEC_MODE, | ||
| 58 | }; | ||
| 59 | |||
| 60 | static const iomux_cfg_t tx28_fec1_pads[] __initconst = { | ||
| 61 | MX28_PAD_ENET0_RXD2__ENET1_RXD0, | ||
| 62 | MX28_PAD_ENET0_RXD3__ENET1_RXD1, | ||
| 63 | MX28_PAD_ENET0_TXD2__ENET1_TXD0, | ||
| 64 | MX28_PAD_ENET0_TXD3__ENET1_TXD1, | ||
| 65 | MX28_PAD_ENET0_COL__ENET1_TX_EN, | ||
| 66 | MX28_PAD_ENET0_CRS__ENET1_RX_EN, | ||
| 67 | }; | ||
| 68 | |||
| 69 | static const struct fec_platform_data tx28_fec0_data __initconst = { | ||
| 70 | .phy = PHY_INTERFACE_MODE_RMII, | ||
| 71 | }; | ||
| 72 | |||
| 73 | static const struct fec_platform_data tx28_fec1_data __initconst = { | ||
| 74 | .phy = PHY_INTERFACE_MODE_RMII, | ||
| 75 | }; | ||
| 76 | |||
| 77 | int __init tx28_add_fec0(void) | ||
| 78 | { | ||
| 79 | int i, ret; | ||
| 80 | |||
| 81 | pr_debug("%s: Switching FEC PHY power off\n", __func__); | ||
| 82 | ret = mxs_iomux_setup_multiple_pads(tx28_fec_gpio_pads, | ||
| 83 | ARRAY_SIZE(tx28_fec_gpio_pads)); | ||
| 84 | for (i = 0; i < ARRAY_SIZE(tx28_fec_gpio_pads); i++) { | ||
| 85 | unsigned int gpio = MXS_GPIO_NR(PAD_BANK(tx28_fec_gpio_pads[i]), | ||
| 86 | PAD_PIN(tx28_fec_gpio_pads[i])); | ||
| 87 | |||
| 88 | ret = gpio_request(gpio, "FEC"); | ||
| 89 | if (ret) { | ||
| 90 | pr_err("Failed to request GPIO_%d_%d: %d\n", | ||
| 91 | PAD_BANK(tx28_fec_gpio_pads[i]), | ||
| 92 | PAD_PIN(tx28_fec_gpio_pads[i]), ret); | ||
| 93 | goto free_gpios; | ||
| 94 | } | ||
| 95 | ret = gpio_direction_output(gpio, 0); | ||
| 96 | if (ret) { | ||
| 97 | pr_err("Failed to set direction of GPIO_%d_%d to output: %d\n", | ||
| 98 | gpio / 32 + 1, gpio % 32, ret); | ||
| 99 | goto free_gpios; | ||
| 100 | } | ||
| 101 | } | ||
| 102 | |||
| 103 | /* Power up fec phy */ | ||
| 104 | pr_debug("%s: Switching FEC PHY power on\n", __func__); | ||
| 105 | ret = gpio_direction_output(TX28_FEC_PHY_POWER, 1); | ||
| 106 | if (ret) { | ||
| 107 | pr_err("Failed to power on PHY: %d\n", ret); | ||
| 108 | goto free_gpios; | ||
| 109 | } | ||
| 110 | mdelay(26); /* 25ms according to data sheet */ | ||
| 111 | |||
| 112 | /* nINT */ | ||
| 113 | gpio_direction_input(MXS_GPIO_NR(4, 5)); | ||
| 114 | /* Mode strap pins */ | ||
| 115 | gpio_direction_output(MXS_GPIO_NR(4, 2), 1); | ||
| 116 | gpio_direction_output(MXS_GPIO_NR(4, 3), 1); | ||
| 117 | gpio_direction_output(MXS_GPIO_NR(4, 4), 1); | ||
| 118 | |||
| 119 | udelay(100); /* minimum assertion time for nRST */ | ||
| 120 | |||
| 121 | pr_debug("%s: Deasserting FEC PHY RESET\n", __func__); | ||
| 122 | gpio_set_value(TX28_FEC_PHY_RESET, 1); | ||
| 123 | |||
| 124 | ret = mxs_iomux_setup_multiple_pads(tx28_fec0_pads, | ||
| 125 | ARRAY_SIZE(tx28_fec0_pads)); | ||
| 126 | if (ret) { | ||
| 127 | pr_debug("%s: mxs_iomux_setup_multiple_pads() failed with rc: %d\n", | ||
| 128 | __func__, ret); | ||
| 129 | goto free_gpios; | ||
| 130 | } | ||
| 131 | pr_debug("%s: Registering FEC0 device\n", __func__); | ||
| 132 | mx28_add_fec(0, &tx28_fec0_data); | ||
| 133 | return 0; | ||
| 134 | |||
| 135 | free_gpios: | ||
| 136 | while (--i >= 0) { | ||
| 137 | unsigned int gpio = MXS_GPIO_NR(PAD_BANK(tx28_fec_gpio_pads[i]), | ||
| 138 | PAD_PIN(tx28_fec_gpio_pads[i])); | ||
| 139 | |||
| 140 | gpio_free(gpio); | ||
| 141 | } | ||
| 142 | |||
| 143 | return ret; | ||
| 144 | } | ||
| 145 | |||
| 146 | int __init tx28_add_fec1(void) | ||
| 147 | { | ||
| 148 | int ret; | ||
| 149 | |||
| 150 | ret = mxs_iomux_setup_multiple_pads(tx28_fec1_pads, | ||
| 151 | ARRAY_SIZE(tx28_fec1_pads)); | ||
| 152 | if (ret) { | ||
| 153 | pr_debug("%s: mxs_iomux_setup_multiple_pads() failed with rc: %d\n", | ||
| 154 | __func__, ret); | ||
| 155 | return ret; | ||
| 156 | } | ||
| 157 | pr_debug("%s: Registering FEC1 device\n", __func__); | ||
| 158 | mx28_add_fec(1, &tx28_fec1_data); | ||
| 159 | return 0; | ||
| 160 | } | ||
diff --git a/arch/arm/mach-mxs/module-tx28.h b/arch/arm/mach-mxs/module-tx28.h deleted file mode 100644 index 8ed425457d30..000000000000 --- a/arch/arm/mach-mxs/module-tx28.h +++ /dev/null | |||
| @@ -1,10 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | int __init tx28_add_fec0(void); | ||
| 10 | int __init tx28_add_fec1(void); | ||
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index dd2db025f778..fcd4e85c4ddc 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig | |||
| @@ -62,13 +62,14 @@ config ARCH_OMAP4 | |||
| 62 | select PM_OPP if PM | 62 | select PM_OPP if PM |
| 63 | select USB_ARCH_HAS_EHCI if USB_SUPPORT | 63 | select USB_ARCH_HAS_EHCI if USB_SUPPORT |
| 64 | select ARM_CPU_SUSPEND if PM | 64 | select ARM_CPU_SUSPEND if PM |
| 65 | select ARCH_NEEDS_CPU_IDLE_COUPLED | 65 | select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP |
| 66 | 66 | ||
| 67 | config SOC_OMAP5 | 67 | config SOC_OMAP5 |
| 68 | bool "TI OMAP5" | 68 | bool "TI OMAP5" |
| 69 | select CPU_V7 | 69 | select CPU_V7 |
| 70 | select ARM_GIC | 70 | select ARM_GIC |
| 71 | select HAVE_SMP | 71 | select HAVE_SMP |
| 72 | select ARM_CPU_SUSPEND if PM | ||
| 72 | 73 | ||
| 73 | comment "OMAP Core Type" | 74 | comment "OMAP Core Type" |
| 74 | depends on ARCH_OMAP2 | 75 | depends on ARCH_OMAP2 |
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 74915295482e..28214483aaba 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c | |||
| @@ -554,6 +554,8 @@ static const struct usbhs_omap_board_data igep3_usbhs_bdata __initconst = { | |||
| 554 | 554 | ||
| 555 | #ifdef CONFIG_OMAP_MUX | 555 | #ifdef CONFIG_OMAP_MUX |
| 556 | static struct omap_board_mux board_mux[] __initdata = { | 556 | static struct omap_board_mux board_mux[] __initdata = { |
| 557 | /* SMSC9221 LAN Controller ETH IRQ (GPIO_176) */ | ||
| 558 | OMAP3_MUX(MCSPI1_CS2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), | ||
| 557 | { .reg_offset = OMAP_MUX_TERMINATOR }, | 559 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
| 558 | }; | 560 | }; |
| 559 | #endif | 561 | #endif |
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index ef230a0eb5eb..0d362e9f9cb9 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c | |||
| @@ -58,6 +58,7 @@ | |||
| 58 | #include "hsmmc.h" | 58 | #include "hsmmc.h" |
| 59 | #include "common-board-devices.h" | 59 | #include "common-board-devices.h" |
| 60 | 60 | ||
| 61 | #define OMAP3_EVM_TS_GPIO 175 | ||
| 61 | #define OMAP3_EVM_EHCI_VBUS 22 | 62 | #define OMAP3_EVM_EHCI_VBUS 22 |
| 62 | #define OMAP3_EVM_EHCI_SELECT 61 | 63 | #define OMAP3_EVM_EHCI_SELECT 61 |
| 63 | 64 | ||
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c index 14734746457c..c1875862679f 100644 --- a/arch/arm/mach-omap2/common-board-devices.c +++ b/arch/arm/mach-omap2/common-board-devices.c | |||
| @@ -35,16 +35,6 @@ static struct omap2_mcspi_device_config ads7846_mcspi_config = { | |||
| 35 | .turbo_mode = 0, | 35 | .turbo_mode = 0, |
| 36 | }; | 36 | }; |
| 37 | 37 | ||
| 38 | /* | ||
| 39 | * ADS7846 driver maybe request a gpio according to the value | ||
| 40 | * of pdata->get_pendown_state, but we have done this. So set | ||
| 41 | * get_pendown_state to avoid twice gpio requesting. | ||
| 42 | */ | ||
| 43 | static int omap3_get_pendown_state(void) | ||
| 44 | { | ||
| 45 | return !gpio_get_value(OMAP3_EVM_TS_GPIO); | ||
| 46 | } | ||
| 47 | |||
| 48 | static struct ads7846_platform_data ads7846_config = { | 38 | static struct ads7846_platform_data ads7846_config = { |
| 49 | .x_max = 0x0fff, | 39 | .x_max = 0x0fff, |
| 50 | .y_max = 0x0fff, | 40 | .y_max = 0x0fff, |
| @@ -55,7 +45,6 @@ static struct ads7846_platform_data ads7846_config = { | |||
| 55 | .debounce_rep = 1, | 45 | .debounce_rep = 1, |
| 56 | .gpio_pendown = -EINVAL, | 46 | .gpio_pendown = -EINVAL, |
| 57 | .keep_vref_on = 1, | 47 | .keep_vref_on = 1, |
| 58 | .get_pendown_state = &omap3_get_pendown_state, | ||
| 59 | }; | 48 | }; |
| 60 | 49 | ||
| 61 | static struct spi_board_info ads7846_spi_board_info __initdata = { | 50 | static struct spi_board_info ads7846_spi_board_info __initdata = { |
diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h index 4c4ef6a6166b..a0b4a42836ab 100644 --- a/arch/arm/mach-omap2/common-board-devices.h +++ b/arch/arm/mach-omap2/common-board-devices.h | |||
| @@ -4,7 +4,6 @@ | |||
| 4 | #include "twl-common.h" | 4 | #include "twl-common.h" |
| 5 | 5 | ||
| 6 | #define NAND_BLOCK_SIZE SZ_128K | 6 | #define NAND_BLOCK_SIZE SZ_128K |
| 7 | #define OMAP3_EVM_TS_GPIO 175 | ||
| 8 | 7 | ||
| 9 | struct mtd_partition; | 8 | struct mtd_partition; |
| 10 | struct ads7846_platform_data; | 9 | struct ads7846_platform_data; |
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c index ee05e193fc61..288bee6cbb76 100644 --- a/arch/arm/mach-omap2/cpuidle44xx.c +++ b/arch/arm/mach-omap2/cpuidle44xx.c | |||
| @@ -238,8 +238,9 @@ int __init omap4_idle_init(void) | |||
| 238 | for_each_cpu(cpu_id, cpu_online_mask) { | 238 | for_each_cpu(cpu_id, cpu_online_mask) { |
| 239 | dev = &per_cpu(omap4_idle_dev, cpu_id); | 239 | dev = &per_cpu(omap4_idle_dev, cpu_id); |
| 240 | dev->cpu = cpu_id; | 240 | dev->cpu = cpu_id; |
| 241 | #ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED | ||
| 241 | dev->coupled_cpus = *cpu_online_mask; | 242 | dev->coupled_cpus = *cpu_online_mask; |
| 242 | 243 | #endif | |
| 243 | cpuidle_register_driver(&omap4_idle_driver); | 244 | cpuidle_register_driver(&omap4_idle_driver); |
| 244 | 245 | ||
| 245 | if (cpuidle_register_device(dev)) { | 246 | if (cpuidle_register_device(dev)) { |
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h index 471e62a74a16..76f9b3c2f586 100644 --- a/arch/arm/mach-omap2/mux.h +++ b/arch/arm/mach-omap2/mux.h | |||
| @@ -127,7 +127,6 @@ struct omap_mux_partition { | |||
| 127 | * @gpio: GPIO number | 127 | * @gpio: GPIO number |
| 128 | * @muxnames: available signal modes for a ball | 128 | * @muxnames: available signal modes for a ball |
| 129 | * @balls: available balls on the package | 129 | * @balls: available balls on the package |
| 130 | * @partition: mux partition | ||
| 131 | */ | 130 | */ |
| 132 | struct omap_mux { | 131 | struct omap_mux { |
| 133 | u16 reg_offset; | 132 | u16 reg_offset; |
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c index 2293ba27101b..c95415da23c2 100644 --- a/arch/arm/mach-omap2/opp4xxx_data.c +++ b/arch/arm/mach-omap2/opp4xxx_data.c | |||
| @@ -94,7 +94,7 @@ int __init omap4_opp_init(void) | |||
| 94 | { | 94 | { |
| 95 | int r = -ENODEV; | 95 | int r = -ENODEV; |
| 96 | 96 | ||
| 97 | if (!cpu_is_omap44xx()) | 97 | if (!cpu_is_omap443x()) |
| 98 | return r; | 98 | return r; |
| 99 | 99 | ||
| 100 | r = omap_init_opp_table(omap44xx_opp_def_list, | 100 | r = omap_init_opp_table(omap44xx_opp_def_list, |
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index e4fc88c65dbd..05bd8f02723f 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c | |||
| @@ -272,21 +272,16 @@ void omap_sram_idle(void) | |||
| 272 | per_next_state = pwrdm_read_next_pwrst(per_pwrdm); | 272 | per_next_state = pwrdm_read_next_pwrst(per_pwrdm); |
| 273 | core_next_state = pwrdm_read_next_pwrst(core_pwrdm); | 273 | core_next_state = pwrdm_read_next_pwrst(core_pwrdm); |
| 274 | 274 | ||
| 275 | if (mpu_next_state < PWRDM_POWER_ON) { | 275 | pwrdm_pre_transition(NULL); |
| 276 | pwrdm_pre_transition(mpu_pwrdm); | ||
| 277 | pwrdm_pre_transition(neon_pwrdm); | ||
| 278 | } | ||
| 279 | 276 | ||
| 280 | /* PER */ | 277 | /* PER */ |
| 281 | if (per_next_state < PWRDM_POWER_ON) { | 278 | if (per_next_state < PWRDM_POWER_ON) { |
| 282 | pwrdm_pre_transition(per_pwrdm); | ||
| 283 | per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0; | 279 | per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0; |
| 284 | omap2_gpio_prepare_for_idle(per_going_off); | 280 | omap2_gpio_prepare_for_idle(per_going_off); |
| 285 | } | 281 | } |
| 286 | 282 | ||
| 287 | /* CORE */ | 283 | /* CORE */ |
| 288 | if (core_next_state < PWRDM_POWER_ON) { | 284 | if (core_next_state < PWRDM_POWER_ON) { |
| 289 | pwrdm_pre_transition(core_pwrdm); | ||
| 290 | if (core_next_state == PWRDM_POWER_OFF) { | 285 | if (core_next_state == PWRDM_POWER_OFF) { |
| 291 | omap3_core_save_context(); | 286 | omap3_core_save_context(); |
| 292 | omap3_cm_save_context(); | 287 | omap3_cm_save_context(); |
| @@ -339,20 +334,14 @@ void omap_sram_idle(void) | |||
| 339 | omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, | 334 | omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, |
| 340 | OMAP3430_GR_MOD, | 335 | OMAP3430_GR_MOD, |
| 341 | OMAP3_PRM_VOLTCTRL_OFFSET); | 336 | OMAP3_PRM_VOLTCTRL_OFFSET); |
| 342 | pwrdm_post_transition(core_pwrdm); | ||
| 343 | } | 337 | } |
| 344 | omap3_intc_resume_idle(); | 338 | omap3_intc_resume_idle(); |
| 345 | 339 | ||
| 340 | pwrdm_post_transition(NULL); | ||
| 341 | |||
| 346 | /* PER */ | 342 | /* PER */ |
| 347 | if (per_next_state < PWRDM_POWER_ON) { | 343 | if (per_next_state < PWRDM_POWER_ON) |
| 348 | omap2_gpio_resume_after_idle(); | 344 | omap2_gpio_resume_after_idle(); |
| 349 | pwrdm_post_transition(per_pwrdm); | ||
| 350 | } | ||
| 351 | |||
| 352 | if (mpu_next_state < PWRDM_POWER_ON) { | ||
| 353 | pwrdm_post_transition(mpu_pwrdm); | ||
| 354 | pwrdm_post_transition(neon_pwrdm); | ||
| 355 | } | ||
| 356 | } | 345 | } |
| 357 | 346 | ||
| 358 | static void omap3_pm_idle(void) | 347 | static void omap3_pm_idle(void) |
diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S index 9f6b83d1b193..91e71d8f46f0 100644 --- a/arch/arm/mach-omap2/sleep44xx.S +++ b/arch/arm/mach-omap2/sleep44xx.S | |||
| @@ -56,9 +56,13 @@ ppa_por_params: | |||
| 56 | * The restore function pointer is stored at CPUx_WAKEUP_NS_PA_ADDR_OFFSET. | 56 | * The restore function pointer is stored at CPUx_WAKEUP_NS_PA_ADDR_OFFSET. |
| 57 | * It returns to the caller for CPU INACTIVE and ON power states or in case | 57 | * It returns to the caller for CPU INACTIVE and ON power states or in case |
| 58 | * CPU failed to transition to targeted OFF/DORMANT state. | 58 | * CPU failed to transition to targeted OFF/DORMANT state. |
| 59 | * | ||
| 60 | * omap4_finish_suspend() calls v7_flush_dcache_all() which doesn't save | ||
| 61 | * stack frame and it expects the caller to take care of it. Hence the entire | ||
| 62 | * stack frame is saved to avoid possible stack corruption. | ||
| 59 | */ | 63 | */ |
| 60 | ENTRY(omap4_finish_suspend) | 64 | ENTRY(omap4_finish_suspend) |
| 61 | stmfd sp!, {lr} | 65 | stmfd sp!, {r4-r12, lr} |
| 62 | cmp r0, #0x0 | 66 | cmp r0, #0x0 |
| 63 | beq do_WFI @ No lowpower state, jump to WFI | 67 | beq do_WFI @ No lowpower state, jump to WFI |
| 64 | 68 | ||
| @@ -226,7 +230,7 @@ scu_gp_clear: | |||
| 226 | skip_scu_gp_clear: | 230 | skip_scu_gp_clear: |
| 227 | isb | 231 | isb |
| 228 | dsb | 232 | dsb |
| 229 | ldmfd sp!, {pc} | 233 | ldmfd sp!, {r4-r12, pc} |
| 230 | ENDPROC(omap4_finish_suspend) | 234 | ENDPROC(omap4_finish_suspend) |
| 231 | 235 | ||
| 232 | /* | 236 | /* |
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c index de47f170ba50..db5ff6642375 100644 --- a/arch/arm/mach-omap2/twl-common.c +++ b/arch/arm/mach-omap2/twl-common.c | |||
| @@ -67,6 +67,7 @@ void __init omap_pmic_init(int bus, u32 clkrate, | |||
| 67 | const char *pmic_type, int pmic_irq, | 67 | const char *pmic_type, int pmic_irq, |
| 68 | struct twl4030_platform_data *pmic_data) | 68 | struct twl4030_platform_data *pmic_data) |
| 69 | { | 69 | { |
| 70 | omap_mux_init_signal("sys_nirq", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE); | ||
| 70 | strncpy(pmic_i2c_board_info.type, pmic_type, | 71 | strncpy(pmic_i2c_board_info.type, pmic_type, |
| 71 | sizeof(pmic_i2c_board_info.type)); | 72 | sizeof(pmic_i2c_board_info.type)); |
| 72 | pmic_i2c_board_info.irq = pmic_irq; | 73 | pmic_i2c_board_info.irq = pmic_irq; |
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 9148b229d0de..410291c67666 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c | |||
| @@ -109,7 +109,8 @@ void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) | |||
| 109 | { | 109 | { |
| 110 | orion_ge00_init(eth_data, | 110 | orion_ge00_init(eth_data, |
| 111 | ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM, | 111 | ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM, |
| 112 | IRQ_ORION5X_ETH_ERR); | 112 | IRQ_ORION5X_ETH_ERR, |
| 113 | MV643XX_TX_CSUM_DEFAULT_LIMIT); | ||
| 113 | } | 114 | } |
| 114 | 115 | ||
| 115 | 116 | ||
diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile index 13dd1604d951..841847d56032 100644 --- a/arch/arm/mach-prima2/Makefile +++ b/arch/arm/mach-prima2/Makefile | |||
| @@ -1,6 +1,5 @@ | |||
| 1 | obj-y := timer.o | 1 | obj-y := timer.o |
| 2 | obj-y += irq.o | 2 | obj-y += irq.o |
| 3 | obj-y += clock.o | ||
| 4 | obj-y += rstc.o | 3 | obj-y += rstc.o |
| 5 | obj-y += prima2.o | 4 | obj-y += prima2.o |
| 6 | obj-y += rtciobrg.o | 5 | obj-y += rtciobrg.o |
diff --git a/arch/arm/mach-prima2/Makefile.boot b/arch/arm/mach-prima2/Makefile.boot index c77a4883a4ee..98167da874c9 100644 --- a/arch/arm/mach-prima2/Makefile.boot +++ b/arch/arm/mach-prima2/Makefile.boot | |||
| @@ -1,3 +1,5 @@ | |||
| 1 | zreladdr-y += 0x00008000 | 1 | zreladdr-y += 0x00008000 |
| 2 | params_phys-y := 0x00000100 | 2 | params_phys-y := 0x00000100 |
| 3 | initrd_phys-y := 0x00800000 | 3 | initrd_phys-y := 0x00800000 |
| 4 | |||
| 5 | dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb | ||
diff --git a/arch/arm/mach-prima2/clock.c b/arch/arm/mach-prima2/clock.c deleted file mode 100644 index aebad7e565cf..000000000000 --- a/arch/arm/mach-prima2/clock.c +++ /dev/null | |||
| @@ -1,510 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Clock tree for CSR SiRFprimaII | ||
| 3 | * | ||
| 4 | * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. | ||
| 5 | * | ||
| 6 | * Licensed under GPLv2 or later. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <linux/module.h> | ||
| 10 | #include <linux/bitops.h> | ||
| 11 | #include <linux/err.h> | ||
| 12 | #include <linux/errno.h> | ||
| 13 | #include <linux/io.h> | ||
| 14 | #include <linux/clkdev.h> | ||
| 15 | #include <linux/clk.h> | ||
| 16 | #include <linux/spinlock.h> | ||
| 17 | #include <linux/of.h> | ||
| 18 | #include <linux/of_address.h> | ||
| 19 | #include <asm/mach/map.h> | ||
| 20 | #include <mach/map.h> | ||
| 21 | |||
| 22 | #define SIRFSOC_CLKC_CLK_EN0 0x0000 | ||
| 23 | #define SIRFSOC_CLKC_CLK_EN1 0x0004 | ||
| 24 | #define SIRFSOC_CLKC_REF_CFG 0x0014 | ||
| 25 | #define SIRFSOC_CLKC_CPU_CFG 0x0018 | ||
| 26 | #define SIRFSOC_CLKC_MEM_CFG 0x001c | ||
| 27 | #define SIRFSOC_CLKC_SYS_CFG 0x0020 | ||
| 28 | #define SIRFSOC_CLKC_IO_CFG 0x0024 | ||
| 29 | #define SIRFSOC_CLKC_DSP_CFG 0x0028 | ||
| 30 | #define SIRFSOC_CLKC_GFX_CFG 0x002c | ||
| 31 | #define SIRFSOC_CLKC_MM_CFG 0x0030 | ||
| 32 | #define SIRFSOC_LKC_LCD_CFG 0x0034 | ||
| 33 | #define SIRFSOC_CLKC_MMC_CFG 0x0038 | ||
| 34 | #define SIRFSOC_CLKC_PLL1_CFG0 0x0040 | ||
| 35 | #define SIRFSOC_CLKC_PLL2_CFG0 0x0044 | ||
| 36 | #define SIRFSOC_CLKC_PLL3_CFG0 0x0048 | ||
| 37 | #define SIRFSOC_CLKC_PLL1_CFG1 0x004c | ||
| 38 | #define SIRFSOC_CLKC_PLL2_CFG1 0x0050 | ||
| 39 | #define SIRFSOC_CLKC_PLL3_CFG1 0x0054 | ||
| 40 | #define SIRFSOC_CLKC_PLL1_CFG2 0x0058 | ||
| 41 | #define SIRFSOC_CLKC_PLL2_CFG2 0x005c | ||
| 42 | #define SIRFSOC_CLKC_PLL3_CFG2 0x0060 | ||
| 43 | |||
| 44 | #define SIRFSOC_CLOCK_VA_BASE SIRFSOC_VA(0x005000) | ||
| 45 | |||
| 46 | #define KHZ 1000 | ||
| 47 | #define MHZ (KHZ * KHZ) | ||
| 48 | |||
| 49 | struct clk_ops { | ||
| 50 | unsigned long (*get_rate)(struct clk *clk); | ||
| 51 | long (*round_rate)(struct clk *clk, unsigned long rate); | ||
| 52 | int (*set_rate)(struct clk *clk, unsigned long rate); | ||
| 53 | int (*enable)(struct clk *clk); | ||
| 54 | int (*disable)(struct clk *clk); | ||
| 55 | struct clk *(*get_parent)(struct clk *clk); | ||
| 56 | int (*set_parent)(struct clk *clk, struct clk *parent); | ||
| 57 | }; | ||
| 58 | |||
| 59 | struct clk { | ||
| 60 | struct clk *parent; /* parent clk */ | ||
| 61 | unsigned long rate; /* clock rate in Hz */ | ||
| 62 | signed char usage; /* clock enable count */ | ||
| 63 | signed char enable_bit; /* enable bit: 0 ~ 63 */ | ||
| 64 | unsigned short regofs; /* register offset */ | ||
| 65 | struct clk_ops *ops; /* clock operation */ | ||
| 66 | }; | ||
| 67 | |||
| 68 | static DEFINE_SPINLOCK(clocks_lock); | ||
| 69 | |||
| 70 | static inline unsigned long clkc_readl(unsigned reg) | ||
| 71 | { | ||
| 72 | return readl(SIRFSOC_CLOCK_VA_BASE + reg); | ||
| 73 | } | ||
| 74 | |||
| 75 | static inline void clkc_writel(u32 val, unsigned reg) | ||
| 76 | { | ||
| 77 | writel(val, SIRFSOC_CLOCK_VA_BASE + reg); | ||
| 78 | } | ||
| 79 | |||
| 80 | /* | ||
| 81 | * osc_rtc - real time oscillator - 32.768KHz | ||
| 82 | * osc_sys - high speed oscillator - 26MHz | ||
| 83 | */ | ||
| 84 | |||
| 85 | static struct clk clk_rtc = { | ||
| 86 | .rate = 32768, | ||
| 87 | }; | ||
| 88 | |||
| 89 | static struct clk clk_osc = { | ||
| 90 | .rate = 26 * MHZ, | ||
| 91 | }; | ||
| 92 | |||
| 93 | /* | ||
| 94 | * std pll | ||
| 95 | */ | ||
| 96 | static unsigned long std_pll_get_rate(struct clk *clk) | ||
| 97 | { | ||
| 98 | unsigned long fin = clk_get_rate(clk->parent); | ||
| 99 | u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - | ||
| 100 | SIRFSOC_CLKC_PLL1_CFG0; | ||
| 101 | |||
| 102 | if (clkc_readl(regcfg2) & BIT(2)) { | ||
| 103 | /* pll bypass mode */ | ||
| 104 | clk->rate = fin; | ||
| 105 | } else { | ||
| 106 | /* fout = fin * nf / nr / od */ | ||
| 107 | u32 cfg0 = clkc_readl(clk->regofs); | ||
| 108 | u32 nf = (cfg0 & (BIT(13) - 1)) + 1; | ||
| 109 | u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1; | ||
| 110 | u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1; | ||
| 111 | WARN_ON(fin % MHZ); | ||
| 112 | clk->rate = fin / MHZ * nf / nr / od * MHZ; | ||
| 113 | } | ||
| 114 | |||
| 115 | return clk->rate; | ||
| 116 | } | ||
| 117 | |||
| 118 | static int std_pll_set_rate(struct clk *clk, unsigned long rate) | ||
| 119 | { | ||
| 120 | unsigned long fin, nf, nr, od, reg; | ||
| 121 | |||
| 122 | /* | ||
| 123 | * fout = fin * nf / (nr * od); | ||
| 124 | * set od = 1, nr = fin/MHz, so fout = nf * MHz | ||
| 125 | */ | ||
| 126 | |||
| 127 | nf = rate / MHZ; | ||
| 128 | if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1)) | ||
| 129 | return -EINVAL; | ||
| 130 | |||
| 131 | fin = clk_get_rate(clk->parent); | ||
| 132 | BUG_ON(fin < MHZ); | ||
| 133 | |||
| 134 | nr = fin / MHZ; | ||
| 135 | BUG_ON((fin % MHZ) || nr > BIT(6)); | ||
| 136 | |||
| 137 | od = 1; | ||
| 138 | |||
| 139 | reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19); | ||
| 140 | clkc_writel(reg, clk->regofs); | ||
| 141 | |||
| 142 | reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0; | ||
| 143 | clkc_writel((nf >> 1) - 1, reg); | ||
| 144 | |||
| 145 | reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0; | ||
| 146 | while (!(clkc_readl(reg) & BIT(6))) | ||
| 147 | cpu_relax(); | ||
| 148 | |||
| 149 | clk->rate = 0; /* set to zero will force recalculation */ | ||
| 150 | return 0; | ||
| 151 | } | ||
| 152 | |||
| 153 | static struct clk_ops std_pll_ops = { | ||
| 154 | .get_rate = std_pll_get_rate, | ||
| 155 | .set_rate = std_pll_set_rate, | ||
| 156 | }; | ||
| 157 | |||
| 158 | static struct clk clk_pll1 = { | ||
| 159 | .parent = &clk_osc, | ||
| 160 | .regofs = SIRFSOC_CLKC_PLL1_CFG0, | ||
| 161 | .ops = &std_pll_ops, | ||
| 162 | }; | ||
| 163 | |||
| 164 | static struct clk clk_pll2 = { | ||
| 165 | .parent = &clk_osc, | ||
| 166 | .regofs = SIRFSOC_CLKC_PLL2_CFG0, | ||
| 167 | .ops = &std_pll_ops, | ||
| 168 | }; | ||
| 169 | |||
| 170 | static struct clk clk_pll3 = { | ||
| 171 | .parent = &clk_osc, | ||
| 172 | .regofs = SIRFSOC_CLKC_PLL3_CFG0, | ||
| 173 | .ops = &std_pll_ops, | ||
| 174 | }; | ||
| 175 | |||
| 176 | /* | ||
| 177 | * clock domains - cpu, mem, sys/io | ||
| 178 | */ | ||
| 179 | |||
| 180 | static struct clk clk_mem; | ||
| 181 | |||
| 182 | static struct clk *dmn_get_parent(struct clk *clk) | ||
| 183 | { | ||
| 184 | struct clk *clks[] = { | ||
| 185 | &clk_osc, &clk_rtc, &clk_pll1, &clk_pll2, &clk_pll3 | ||
| 186 | }; | ||
| 187 | u32 cfg = clkc_readl(clk->regofs); | ||
| 188 | WARN_ON((cfg & (BIT(3) - 1)) > 4); | ||
| 189 | return clks[cfg & (BIT(3) - 1)]; | ||
| 190 | } | ||
| 191 | |||
| 192 | static int dmn_set_parent(struct clk *clk, struct clk *parent) | ||
| 193 | { | ||
| 194 | const struct clk *clks[] = { | ||
| 195 | &clk_osc, &clk_rtc, &clk_pll1, &clk_pll2, &clk_pll3 | ||
| 196 | }; | ||
| 197 | u32 cfg = clkc_readl(clk->regofs); | ||
| 198 | int i; | ||
| 199 | for (i = 0; i < ARRAY_SIZE(clks); i++) { | ||
| 200 | if (clks[i] == parent) { | ||
| 201 | cfg &= ~(BIT(3) - 1); | ||
| 202 | clkc_writel(cfg | i, clk->regofs); | ||
| 203 | /* BIT(3) - switching status: 1 - busy, 0 - done */ | ||
| 204 | while (clkc_readl(clk->regofs) & BIT(3)) | ||
| 205 | cpu_relax(); | ||
| 206 | return 0; | ||
| 207 | } | ||
| 208 | } | ||
| 209 | return -EINVAL; | ||
| 210 | } | ||
| 211 | |||
| 212 | static unsigned long dmn_get_rate(struct clk *clk) | ||
| 213 | { | ||
| 214 | unsigned long fin = clk_get_rate(clk->parent); | ||
| 215 | u32 cfg = clkc_readl(clk->regofs); | ||
| 216 | if (cfg & BIT(24)) { | ||
| 217 | /* fcd bypass mode */ | ||
| 218 | clk->rate = fin; | ||
| 219 | } else { | ||
| 220 | /* | ||
| 221 | * wait count: bit[19:16], hold count: bit[23:20] | ||
| 222 | */ | ||
| 223 | u32 wait = (cfg >> 16) & (BIT(4) - 1); | ||
| 224 | u32 hold = (cfg >> 20) & (BIT(4) - 1); | ||
| 225 | |||
| 226 | clk->rate = fin / (wait + hold + 2); | ||
| 227 | } | ||
| 228 | |||
| 229 | return clk->rate; | ||
| 230 | } | ||
| 231 | |||
| 232 | static int dmn_set_rate(struct clk *clk, unsigned long rate) | ||
| 233 | { | ||
| 234 | unsigned long fin; | ||
| 235 | unsigned ratio, wait, hold, reg; | ||
| 236 | unsigned bits = (clk == &clk_mem) ? 3 : 4; | ||
| 237 | |||
| 238 | fin = clk_get_rate(clk->parent); | ||
| 239 | ratio = fin / rate; | ||
| 240 | |||
| 241 | if (unlikely(ratio < 2 || ratio > BIT(bits + 1))) | ||
| 242 | return -EINVAL; | ||
| 243 | |||
| 244 | WARN_ON(fin % rate); | ||
| 245 | |||
| 246 | wait = (ratio >> 1) - 1; | ||
| 247 | hold = ratio - wait - 2; | ||
| 248 | |||
| 249 | reg = clkc_readl(clk->regofs); | ||
| 250 | reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20)); | ||
| 251 | reg |= (wait << 16) | (hold << 20) | BIT(25); | ||
| 252 | clkc_writel(reg, clk->regofs); | ||
| 253 | |||
| 254 | /* waiting FCD been effective */ | ||
| 255 | while (clkc_readl(clk->regofs) & BIT(25)) | ||
| 256 | cpu_relax(); | ||
| 257 | |||
| 258 | clk->rate = 0; /* set to zero will force recalculation */ | ||
| 259 | |||
| 260 | return 0; | ||
| 261 | } | ||
| 262 | |||
| 263 | /* | ||
| 264 | * cpu clock has no FCD register in Prima2, can only change pll | ||
| 265 | */ | ||
| 266 | static int cpu_set_rate(struct clk *clk, unsigned long rate) | ||
| 267 | { | ||
| 268 | int ret1, ret2; | ||
| 269 | struct clk *cur_parent, *tmp_parent; | ||
| 270 | |||
| 271 | cur_parent = dmn_get_parent(clk); | ||
| 272 | BUG_ON(cur_parent == NULL || cur_parent->usage > 1); | ||
| 273 | |||
| 274 | /* switch to tmp pll before setting parent clock's rate */ | ||
| 275 | tmp_parent = cur_parent == &clk_pll1 ? &clk_pll2 : &clk_pll1; | ||
| 276 | ret1 = dmn_set_parent(clk, tmp_parent); | ||
| 277 | BUG_ON(ret1); | ||
| 278 | |||
| 279 | ret2 = clk_set_rate(cur_parent, rate); | ||
| 280 | |||
| 281 | ret1 = dmn_set_parent(clk, cur_parent); | ||
| 282 | |||
| 283 | clk->rate = 0; /* set to zero will force recalculation */ | ||
| 284 | |||
| 285 | return ret2 ? ret2 : ret1; | ||
| 286 | } | ||
| 287 | |||
| 288 | static struct clk_ops cpu_ops = { | ||
| 289 | .get_parent = dmn_get_parent, | ||
| 290 | .set_parent = dmn_set_parent, | ||
| 291 | .set_rate = cpu_set_rate, | ||
| 292 | }; | ||
| 293 | |||
| 294 | static struct clk clk_cpu = { | ||
| 295 | .parent = &clk_pll1, | ||
| 296 | .regofs = SIRFSOC_CLKC_CPU_CFG, | ||
| 297 | .ops = &cpu_ops, | ||
| 298 | }; | ||
| 299 | |||
| 300 | |||
| 301 | static struct clk_ops msi_ops = { | ||
| 302 | .set_rate = dmn_set_rate, | ||
| 303 | .get_rate = dmn_get_rate, | ||
| 304 | .set_parent = dmn_set_parent, | ||
| 305 | .get_parent = dmn_get_parent, | ||
| 306 | }; | ||
| 307 | |||
| 308 | static struct clk clk_mem = { | ||
| 309 | .parent = &clk_pll2, | ||
| 310 | .regofs = SIRFSOC_CLKC_MEM_CFG, | ||
| 311 | .ops = &msi_ops, | ||
| 312 | }; | ||
| 313 | |||
| 314 | static struct clk clk_sys = { | ||
| 315 | .parent = &clk_pll3, | ||
| 316 | .regofs = SIRFSOC_CLKC_SYS_CFG, | ||
| 317 | .ops = &msi_ops, | ||
| 318 | }; | ||
| 319 | |||
| 320 | static struct clk clk_io = { | ||
| 321 | .parent = &clk_pll3, | ||
| 322 | .regofs = SIRFSOC_CLKC_IO_CFG, | ||
| 323 | .ops = &msi_ops, | ||
| 324 | }; | ||
| 325 | |||
| 326 | /* | ||
| 327 | * on-chip clock sets | ||
| 328 | */ | ||
| 329 | static struct clk_lookup onchip_clks[] = { | ||
| 330 | { | ||
| 331 | .dev_id = "rtc", | ||
| 332 | .clk = &clk_rtc, | ||
| 333 | }, { | ||
| 334 | .dev_id = "osc", | ||
| 335 | .clk = &clk_osc, | ||
| 336 | }, { | ||
| 337 | .dev_id = "pll1", | ||
| 338 | .clk = &clk_pll1, | ||
| 339 | }, { | ||
| 340 | .dev_id = "pll2", | ||
| 341 | .clk = &clk_pll2, | ||
| 342 | }, { | ||
| 343 | .dev_id = "pll3", | ||
| 344 | .clk = &clk_pll3, | ||
| 345 | }, { | ||
| 346 | .dev_id = "cpu", | ||
| 347 | .clk = &clk_cpu, | ||
| 348 | }, { | ||
| 349 | .dev_id = "mem", | ||
| 350 | .clk = &clk_mem, | ||
| 351 | }, { | ||
| 352 | .dev_id = "sys", | ||
| 353 | .clk = &clk_sys, | ||
| 354 | }, { | ||
| 355 | .dev_id = "io", | ||
| 356 | .clk = &clk_io, | ||
| 357 | }, | ||
| 358 | }; | ||
| 359 | |||
| 360 | int clk_enable(struct clk *clk) | ||
| 361 | { | ||
| 362 | unsigned long flags; | ||
| 363 | |||
| 364 | if (unlikely(IS_ERR_OR_NULL(clk))) | ||
| 365 | return -EINVAL; | ||
| 366 | |||
| 367 | if (clk->parent) | ||
| 368 | clk_enable(clk->parent); | ||
| 369 | |||
| 370 | spin_lock_irqsave(&clocks_lock, flags); | ||
| 371 | if (!clk->usage++ && clk->ops && clk->ops->enable) | ||
| 372 | clk->ops->enable(clk); | ||
| 373 | spin_unlock_irqrestore(&clocks_lock, flags); | ||
| 374 | return 0; | ||
| 375 | } | ||
| 376 | EXPORT_SYMBOL(clk_enable); | ||
| 377 | |||
| 378 | void clk_disable(struct clk *clk) | ||
| 379 | { | ||
| 380 | unsigned long flags; | ||
| 381 | |||
| 382 | if (unlikely(IS_ERR_OR_NULL(clk))) | ||
| 383 | return; | ||
| 384 | |||
| 385 | WARN_ON(!clk->usage); | ||
| 386 | |||
| 387 | spin_lock_irqsave(&clocks_lock, flags); | ||
| 388 | if (--clk->usage == 0 && clk->ops && clk->ops->disable) | ||
| 389 | clk->ops->disable(clk); | ||
| 390 | spin_unlock_irqrestore(&clocks_lock, flags); | ||
| 391 | |||
| 392 | if (clk->parent) | ||
| 393 | clk_disable(clk->parent); | ||
| 394 | } | ||
| 395 | EXPORT_SYMBOL(clk_disable); | ||
| 396 | |||
| 397 | unsigned long clk_get_rate(struct clk *clk) | ||
| 398 | { | ||
| 399 | if (unlikely(IS_ERR_OR_NULL(clk))) | ||
| 400 | return 0; | ||
| 401 | |||
| 402 | if (clk->rate) | ||
| 403 | return clk->rate; | ||
| 404 | |||
| 405 | if (clk->ops && clk->ops->get_rate) | ||
| 406 | return clk->ops->get_rate(clk); | ||
| 407 | |||
| 408 | return clk_get_rate(clk->parent); | ||
| 409 | } | ||
| 410 | EXPORT_SYMBOL(clk_get_rate); | ||
| 411 | |||
| 412 | long clk_round_rate(struct clk *clk, unsigned long rate) | ||
| 413 | { | ||
| 414 | if (unlikely(IS_ERR_OR_NULL(clk))) | ||
| 415 | return 0; | ||
| 416 | |||
| 417 | if (clk->ops && clk->ops->round_rate) | ||
| 418 | return clk->ops->round_rate(clk, rate); | ||
| 419 | |||
| 420 | return 0; | ||
| 421 | } | ||
| 422 | EXPORT_SYMBOL(clk_round_rate); | ||
| 423 | |||
| 424 | int clk_set_rate(struct clk *clk, unsigned long rate) | ||
| 425 | { | ||
| 426 | if (unlikely(IS_ERR_OR_NULL(clk))) | ||
| 427 | return -EINVAL; | ||
| 428 | |||
| 429 | if (!clk->ops || !clk->ops->set_rate) | ||
| 430 | return -EINVAL; | ||
| 431 | |||
| 432 | return clk->ops->set_rate(clk, rate); | ||
| 433 | } | ||
| 434 | EXPORT_SYMBOL(clk_set_rate); | ||
| 435 | |||
| 436 | int clk_set_parent(struct clk *clk, struct clk *parent) | ||
| 437 | { | ||
| 438 | int ret; | ||
| 439 | unsigned long flags; | ||
| 440 | |||
| 441 | if (unlikely(IS_ERR_OR_NULL(clk))) | ||
| 442 | return -EINVAL; | ||
| 443 | |||
| 444 | if (!clk->ops || !clk->ops->set_parent) | ||
| 445 | return -EINVAL; | ||
| 446 | |||
| 447 | spin_lock_irqsave(&clocks_lock, flags); | ||
| 448 | ret = clk->ops->set_parent(clk, parent); | ||
| 449 | if (!ret) { | ||
| 450 | parent->usage += clk->usage; | ||
| 451 | clk->parent->usage -= clk->usage; | ||
| 452 | BUG_ON(clk->parent->usage < 0); | ||
| 453 | clk->parent = parent; | ||
| 454 | } | ||
| 455 | spin_unlock_irqrestore(&clocks_lock, flags); | ||
| 456 | return ret; | ||
| 457 | } | ||
| 458 | EXPORT_SYMBOL(clk_set_parent); | ||
| 459 | |||
| 460 | struct clk *clk_get_parent(struct clk *clk) | ||
| 461 | { | ||
| 462 | unsigned long flags; | ||
| 463 | |||
| 464 | if (unlikely(IS_ERR_OR_NULL(clk))) | ||
| 465 | return NULL; | ||
| 466 | |||
| 467 | if (!clk->ops || !clk->ops->get_parent) | ||
| 468 | return clk->parent; | ||
| 469 | |||
| 470 | spin_lock_irqsave(&clocks_lock, flags); | ||
| 471 | clk->parent = clk->ops->get_parent(clk); | ||
| 472 | spin_unlock_irqrestore(&clocks_lock, flags); | ||
| 473 | return clk->parent; | ||
| 474 | } | ||
| 475 | EXPORT_SYMBOL(clk_get_parent); | ||
| 476 | |||
| 477 | static void __init sirfsoc_clk_init(void) | ||
| 478 | { | ||
| 479 | clkdev_add_table(onchip_clks, ARRAY_SIZE(onchip_clks)); | ||
| 480 | } | ||
| 481 | |||
| 482 | static struct of_device_id clkc_ids[] = { | ||
| 483 | { .compatible = "sirf,prima2-clkc" }, | ||
| 484 | {}, | ||
| 485 | }; | ||
| 486 | |||
| 487 | void __init sirfsoc_of_clk_init(void) | ||
| 488 | { | ||
| 489 | struct device_node *np; | ||
| 490 | struct resource res; | ||
| 491 | struct map_desc sirfsoc_clkc_iodesc = { | ||
| 492 | .virtual = SIRFSOC_CLOCK_VA_BASE, | ||
| 493 | .type = MT_DEVICE, | ||
| 494 | }; | ||
| 495 | |||
| 496 | np = of_find_matching_node(NULL, clkc_ids); | ||
| 497 | if (!np) | ||
| 498 | panic("unable to find compatible clkc node in dtb\n"); | ||
| 499 | |||
| 500 | if (of_address_to_resource(np, 0, &res)) | ||
| 501 | panic("unable to find clkc range in dtb"); | ||
| 502 | of_node_put(np); | ||
| 503 | |||
| 504 | sirfsoc_clkc_iodesc.pfn = __phys_to_pfn(res.start); | ||
| 505 | sirfsoc_clkc_iodesc.length = 1 + res.end - res.start; | ||
| 506 | |||
| 507 | iotable_init(&sirfsoc_clkc_iodesc, 1); | ||
| 508 | |||
| 509 | sirfsoc_clk_init(); | ||
| 510 | } | ||
diff --git a/arch/arm/mach-prima2/prima2.c b/arch/arm/mach-prima2/prima2.c index 8f0429d4b79f..e9a17aebe0d6 100644 --- a/arch/arm/mach-prima2/prima2.c +++ b/arch/arm/mach-prima2/prima2.c | |||
| @@ -38,7 +38,6 @@ static const char *prima2cb_dt_match[] __initdata = { | |||
| 38 | MACHINE_START(PRIMA2_EVB, "prima2cb") | 38 | MACHINE_START(PRIMA2_EVB, "prima2cb") |
| 39 | /* Maintainer: Barry Song <baohua.song@csr.com> */ | 39 | /* Maintainer: Barry Song <baohua.song@csr.com> */ |
| 40 | .atag_offset = 0x100, | 40 | .atag_offset = 0x100, |
| 41 | .init_early = sirfsoc_of_clk_init, | ||
| 42 | .map_io = sirfsoc_map_lluart, | 41 | .map_io = sirfsoc_map_lluart, |
| 43 | .init_irq = sirfsoc_of_irq_init, | 42 | .init_irq = sirfsoc_of_irq_init, |
| 44 | .timer = &sirfsoc_timer, | 43 | .timer = &sirfsoc_timer, |
diff --git a/arch/arm/mach-prima2/timer.c b/arch/arm/mach-prima2/timer.c index f224107de7bc..d95bf252f694 100644 --- a/arch/arm/mach-prima2/timer.c +++ b/arch/arm/mach-prima2/timer.c | |||
| @@ -21,6 +21,8 @@ | |||
| 21 | #include <asm/sched_clock.h> | 21 | #include <asm/sched_clock.h> |
| 22 | #include <asm/mach/time.h> | 22 | #include <asm/mach/time.h> |
| 23 | 23 | ||
| 24 | #include "common.h" | ||
| 25 | |||
| 24 | #define SIRFSOC_TIMER_COUNTER_LO 0x0000 | 26 | #define SIRFSOC_TIMER_COUNTER_LO 0x0000 |
| 25 | #define SIRFSOC_TIMER_COUNTER_HI 0x0004 | 27 | #define SIRFSOC_TIMER_COUNTER_HI 0x0004 |
| 26 | #define SIRFSOC_TIMER_MATCH_0 0x0008 | 28 | #define SIRFSOC_TIMER_MATCH_0 0x0008 |
| @@ -188,9 +190,13 @@ static void __init sirfsoc_clockevent_init(void) | |||
| 188 | static void __init sirfsoc_timer_init(void) | 190 | static void __init sirfsoc_timer_init(void) |
| 189 | { | 191 | { |
| 190 | unsigned long rate; | 192 | unsigned long rate; |
| 193 | struct clk *clk; | ||
| 194 | |||
| 195 | /* initialize clocking early, we want to set the OS timer */ | ||
| 196 | sirfsoc_of_clk_init(); | ||
| 191 | 197 | ||
| 192 | /* timer's input clock is io clock */ | 198 | /* timer's input clock is io clock */ |
| 193 | struct clk *clk = clk_get_sys("io", NULL); | 199 | clk = clk_get_sys("io", NULL); |
| 194 | 200 | ||
| 195 | BUG_ON(IS_ERR(clk)); | 201 | BUG_ON(IS_ERR(clk)); |
| 196 | 202 | ||
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index fe2d1f80ef50..8e6288de69b9 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig | |||
| @@ -25,6 +25,18 @@ config PXA_V7_MACH_AUTO | |||
| 25 | if !ARCH_PXA_V7 | 25 | if !ARCH_PXA_V7 |
| 26 | comment "Intel/Marvell Dev Platforms (sorted by hardware release time)" | 26 | comment "Intel/Marvell Dev Platforms (sorted by hardware release time)" |
| 27 | 27 | ||
| 28 | config MACH_PXA3XX_DT | ||
| 29 | bool "Support PXA3xx platforms from device tree" | ||
| 30 | select PXA3xx | ||
| 31 | select CPU_PXA300 | ||
| 32 | select POWER_SUPPLY | ||
| 33 | select HAVE_PWM | ||
| 34 | select USE_OF | ||
| 35 | help | ||
| 36 | Include support for Marvell PXA3xx based platforms using | ||
| 37 | the device tree. Needn't select any other machine while | ||
| 38 | MACH_PXA3XX_DT is enabled. | ||
| 39 | |||
| 28 | config ARCH_LUBBOCK | 40 | config ARCH_LUBBOCK |
| 29 | bool "Intel DBPXA250 Development Platform (aka Lubbock)" | 41 | bool "Intel DBPXA250 Development Platform (aka Lubbock)" |
| 30 | select PXA25x | 42 | select PXA25x |
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index be0f7df8685c..2bedc9ed076c 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile | |||
| @@ -26,6 +26,9 @@ obj-$(CONFIG_CPU_PXA930) += pxa930.o | |||
| 26 | 26 | ||
| 27 | # NOTE: keep the order of boards in accordance to their order in Kconfig | 27 | # NOTE: keep the order of boards in accordance to their order in Kconfig |
| 28 | 28 | ||
| 29 | # Device Tree support | ||
| 30 | obj-$(CONFIG_MACH_PXA3XX_DT) += pxa-dt.o | ||
| 31 | |||
| 29 | # Intel/Marvell Dev Platforms | 32 | # Intel/Marvell Dev Platforms |
| 30 | obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o | 33 | obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o |
| 31 | obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o | 34 | obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o |
diff --git a/arch/arm/mach-pxa/clock-pxa3xx.c b/arch/arm/mach-pxa/clock-pxa3xx.c index 2a37a9a8f621..d4e9499832dc 100644 --- a/arch/arm/mach-pxa/clock-pxa3xx.c +++ b/arch/arm/mach-pxa/clock-pxa3xx.c | |||
| @@ -127,8 +127,10 @@ void clk_pxa3xx_cken_enable(struct clk *clk) | |||
| 127 | 127 | ||
| 128 | if (clk->cken < 32) | 128 | if (clk->cken < 32) |
| 129 | CKENA |= mask; | 129 | CKENA |= mask; |
| 130 | else | 130 | else if (clk->cken < 64) |
| 131 | CKENB |= mask; | 131 | CKENB |= mask; |
| 132 | else | ||
| 133 | CKENC |= mask; | ||
| 132 | } | 134 | } |
| 133 | 135 | ||
| 134 | void clk_pxa3xx_cken_disable(struct clk *clk) | 136 | void clk_pxa3xx_cken_disable(struct clk *clk) |
| @@ -137,8 +139,10 @@ void clk_pxa3xx_cken_disable(struct clk *clk) | |||
| 137 | 139 | ||
| 138 | if (clk->cken < 32) | 140 | if (clk->cken < 32) |
| 139 | CKENA &= ~mask; | 141 | CKENA &= ~mask; |
| 140 | else | 142 | else if (clk->cken < 64) |
| 141 | CKENB &= ~mask; | 143 | CKENB &= ~mask; |
| 144 | else | ||
| 145 | CKENC &= ~mask; | ||
| 142 | } | 146 | } |
| 143 | 147 | ||
| 144 | const struct clkops clk_pxa3xx_cken_ops = { | 148 | const struct clkops clk_pxa3xx_cken_ops = { |
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h index 207ecb49a61b..f4d48d20754e 100644 --- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h | |||
| @@ -131,6 +131,7 @@ | |||
| 131 | #define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */ | 131 | #define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */ |
| 132 | #define CKENA __REG(0x4134000C) /* A Clock Enable Register */ | 132 | #define CKENA __REG(0x4134000C) /* A Clock Enable Register */ |
| 133 | #define CKENB __REG(0x41340010) /* B Clock Enable Register */ | 133 | #define CKENB __REG(0x41340010) /* B Clock Enable Register */ |
| 134 | #define CKENC __REG(0x41340024) /* C Clock Enable Register */ | ||
| 134 | #define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */ | 135 | #define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */ |
| 135 | 136 | ||
| 136 | #define ACCR_XPDIS (1 << 31) /* Core PLL Output Disable */ | 137 | #define ACCR_XPDIS (1 << 31) /* Core PLL Output Disable */ |
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index 5dae15ea6718..b6cc1816463e 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c | |||
| @@ -17,6 +17,8 @@ | |||
| 17 | #include <linux/syscore_ops.h> | 17 | #include <linux/syscore_ops.h> |
| 18 | #include <linux/io.h> | 18 | #include <linux/io.h> |
| 19 | #include <linux/irq.h> | 19 | #include <linux/irq.h> |
| 20 | #include <linux/of_address.h> | ||
| 21 | #include <linux/of_irq.h> | ||
| 20 | 22 | ||
| 21 | #include <asm/exception.h> | 23 | #include <asm/exception.h> |
| 22 | 24 | ||
| @@ -25,8 +27,6 @@ | |||
| 25 | 27 | ||
| 26 | #include "generic.h" | 28 | #include "generic.h" |
| 27 | 29 | ||
| 28 | #define IRQ_BASE io_p2v(0x40d00000) | ||
| 29 | |||
| 30 | #define ICIP (0x000) | 30 | #define ICIP (0x000) |
| 31 | #define ICMR (0x004) | 31 | #define ICMR (0x004) |
| 32 | #define ICLR (0x008) | 32 | #define ICLR (0x008) |
| @@ -48,22 +48,19 @@ | |||
| 48 | * This is for peripheral IRQs internal to the PXA chip. | 48 | * This is for peripheral IRQs internal to the PXA chip. |
| 49 | */ | 49 | */ |
| 50 | 50 | ||
| 51 | static void __iomem *pxa_irq_base; | ||
| 51 | static int pxa_internal_irq_nr; | 52 | static int pxa_internal_irq_nr; |
| 52 | 53 | static bool cpu_has_ipr; | |
| 53 | static inline int cpu_has_ipr(void) | ||
| 54 | { | ||
| 55 | return !cpu_is_pxa25x(); | ||
| 56 | } | ||
| 57 | 54 | ||
| 58 | static inline void __iomem *irq_base(int i) | 55 | static inline void __iomem *irq_base(int i) |
| 59 | { | 56 | { |
| 60 | static unsigned long phys_base[] = { | 57 | static unsigned long phys_base_offset[] = { |
| 61 | 0x40d00000, | 58 | 0x0, |
| 62 | 0x40d0009c, | 59 | 0x9c, |
| 63 | 0x40d00130, | 60 | 0x130, |
| 64 | }; | 61 | }; |
| 65 | 62 | ||
| 66 | return io_p2v(phys_base[i]); | 63 | return pxa_irq_base + phys_base_offset[i]; |
| 67 | } | 64 | } |
| 68 | 65 | ||
| 69 | void pxa_mask_irq(struct irq_data *d) | 66 | void pxa_mask_irq(struct irq_data *d) |
| @@ -96,8 +93,8 @@ asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs) | |||
| 96 | uint32_t icip, icmr, mask; | 93 | uint32_t icip, icmr, mask; |
| 97 | 94 | ||
| 98 | do { | 95 | do { |
| 99 | icip = __raw_readl(IRQ_BASE + ICIP); | 96 | icip = __raw_readl(pxa_irq_base + ICIP); |
| 100 | icmr = __raw_readl(IRQ_BASE + ICMR); | 97 | icmr = __raw_readl(pxa_irq_base + ICMR); |
| 101 | mask = icip & icmr; | 98 | mask = icip & icmr; |
| 102 | 99 | ||
| 103 | if (mask == 0) | 100 | if (mask == 0) |
| @@ -128,6 +125,8 @@ void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int)) | |||
| 128 | BUG_ON(irq_nr > MAX_INTERNAL_IRQS); | 125 | BUG_ON(irq_nr > MAX_INTERNAL_IRQS); |
| 129 | 126 | ||
| 130 | pxa_internal_irq_nr = irq_nr; | 127 | pxa_internal_irq_nr = irq_nr; |
| 128 | cpu_has_ipr = !cpu_is_pxa25x(); | ||
| 129 | pxa_irq_base = io_p2v(0x40d00000); | ||
| 131 | 130 | ||
| 132 | for (n = 0; n < irq_nr; n += 32) { | 131 | for (n = 0; n < irq_nr; n += 32) { |
| 133 | void __iomem *base = irq_base(n >> 5); | 132 | void __iomem *base = irq_base(n >> 5); |
| @@ -136,8 +135,8 @@ void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int)) | |||
| 136 | __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ | 135 | __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ |
| 137 | for (i = n; (i < (n + 32)) && (i < irq_nr); i++) { | 136 | for (i = n; (i < (n + 32)) && (i < irq_nr); i++) { |
| 138 | /* initialize interrupt priority */ | 137 | /* initialize interrupt priority */ |
| 139 | if (cpu_has_ipr()) | 138 | if (cpu_has_ipr) |
| 140 | __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i)); | 139 | __raw_writel(i | IPR_VALID, pxa_irq_base + IPR(i)); |
| 141 | 140 | ||
| 142 | irq = PXA_IRQ(i); | 141 | irq = PXA_IRQ(i); |
| 143 | irq_set_chip_and_handler(irq, &pxa_internal_irq_chip, | 142 | irq_set_chip_and_handler(irq, &pxa_internal_irq_chip, |
| @@ -168,9 +167,9 @@ static int pxa_irq_suspend(void) | |||
| 168 | __raw_writel(0, base + ICMR); | 167 | __raw_writel(0, base + ICMR); |
| 169 | } | 168 | } |
| 170 | 169 | ||
| 171 | if (cpu_has_ipr()) { | 170 | if (cpu_has_ipr) { |
| 172 | for (i = 0; i < pxa_internal_irq_nr; i++) | 171 | for (i = 0; i < pxa_internal_irq_nr; i++) |
| 173 | saved_ipr[i] = __raw_readl(IRQ_BASE + IPR(i)); | 172 | saved_ipr[i] = __raw_readl(pxa_irq_base + IPR(i)); |
| 174 | } | 173 | } |
| 175 | 174 | ||
| 176 | return 0; | 175 | return 0; |
| @@ -187,11 +186,11 @@ static void pxa_irq_resume(void) | |||
| 187 | __raw_writel(0, base + ICLR); | 186 | __raw_writel(0, base + ICLR); |
| 188 | } | 187 | } |
| 189 | 188 | ||
| 190 | if (cpu_has_ipr()) | 189 | if (cpu_has_ipr) |
| 191 | for (i = 0; i < pxa_internal_irq_nr; i++) | 190 | for (i = 0; i < pxa_internal_irq_nr; i++) |
| 192 | __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i)); | 191 | __raw_writel(saved_ipr[i], pxa_irq_base + IPR(i)); |
| 193 | 192 | ||
| 194 | __raw_writel(1, IRQ_BASE + ICCR); | 193 | __raw_writel(1, pxa_irq_base + ICCR); |
| 195 | } | 194 | } |
| 196 | #else | 195 | #else |
| 197 | #define pxa_irq_suspend NULL | 196 | #define pxa_irq_suspend NULL |
| @@ -202,3 +201,93 @@ struct syscore_ops pxa_irq_syscore_ops = { | |||
| 202 | .suspend = pxa_irq_suspend, | 201 | .suspend = pxa_irq_suspend, |
| 203 | .resume = pxa_irq_resume, | 202 | .resume = pxa_irq_resume, |
| 204 | }; | 203 | }; |
| 204 | |||
| 205 | #ifdef CONFIG_OF | ||
| 206 | static struct irq_domain *pxa_irq_domain; | ||
| 207 | |||
| 208 | static int pxa_irq_map(struct irq_domain *h, unsigned int virq, | ||
| 209 | irq_hw_number_t hw) | ||
| 210 | { | ||
| 211 | void __iomem *base = irq_base(hw / 32); | ||
| 212 | |||
| 213 | /* initialize interrupt priority */ | ||
| 214 | if (cpu_has_ipr) | ||
| 215 | __raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw)); | ||
| 216 | |||
| 217 | irq_set_chip_and_handler(hw, &pxa_internal_irq_chip, | ||
| 218 | handle_level_irq); | ||
| 219 | irq_set_chip_data(hw, base); | ||
| 220 | set_irq_flags(hw, IRQF_VALID); | ||
| 221 | |||
| 222 | return 0; | ||
| 223 | } | ||
| 224 | |||
| 225 | static struct irq_domain_ops pxa_irq_ops = { | ||
| 226 | .map = pxa_irq_map, | ||
| 227 | .xlate = irq_domain_xlate_onecell, | ||
| 228 | }; | ||
| 229 | |||
| 230 | static const struct of_device_id intc_ids[] __initconst = { | ||
| 231 | { .compatible = "marvell,pxa-intc", }, | ||
| 232 | {} | ||
| 233 | }; | ||
| 234 | |||
| 235 | void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int)) | ||
| 236 | { | ||
| 237 | struct device_node *node; | ||
| 238 | const struct of_device_id *of_id; | ||
| 239 | struct pxa_intc_conf *conf; | ||
| 240 | struct resource res; | ||
| 241 | int n, ret; | ||
| 242 | |||
| 243 | node = of_find_matching_node(NULL, intc_ids); | ||
| 244 | if (!node) { | ||
| 245 | pr_err("Failed to find interrupt controller in arch-pxa\n"); | ||
| 246 | return; | ||
| 247 | } | ||
| 248 | of_id = of_match_node(intc_ids, node); | ||
| 249 | conf = of_id->data; | ||
| 250 | |||
| 251 | ret = of_property_read_u32(node, "marvell,intc-nr-irqs", | ||
| 252 | &pxa_internal_irq_nr); | ||
| 253 | if (ret) { | ||
| 254 | pr_err("Not found marvell,intc-nr-irqs property\n"); | ||
| 255 | return; | ||
| 256 | } | ||
| 257 | |||
| 258 | ret = of_address_to_resource(node, 0, &res); | ||
| 259 | if (ret < 0) { | ||
| 260 | pr_err("No registers defined for node\n"); | ||
| 261 | return; | ||
| 262 | } | ||
| 263 | pxa_irq_base = io_p2v(res.start); | ||
| 264 | |||
| 265 | if (of_find_property(node, "marvell,intc-priority", NULL)) | ||
| 266 | cpu_has_ipr = 1; | ||
| 267 | |||
| 268 | ret = irq_alloc_descs(-1, 0, pxa_internal_irq_nr, 0); | ||
| 269 | if (ret < 0) { | ||
| 270 | pr_err("Failed to allocate IRQ numbers\n"); | ||
| 271 | return; | ||
| 272 | } | ||
| 273 | |||
| 274 | pxa_irq_domain = irq_domain_add_legacy(node, pxa_internal_irq_nr, 0, 0, | ||
| 275 | &pxa_irq_ops, NULL); | ||
| 276 | if (!pxa_irq_domain) | ||
| 277 | panic("Unable to add PXA IRQ domain\n"); | ||
| 278 | |||
| 279 | irq_set_default_host(pxa_irq_domain); | ||
| 280 | |||
| 281 | for (n = 0; n < pxa_internal_irq_nr; n += 32) { | ||
| 282 | void __iomem *base = irq_base(n >> 5); | ||
| 283 | |||
| 284 | __raw_writel(0, base + ICMR); /* disable all IRQs */ | ||
| 285 | __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ | ||
| 286 | } | ||
| 287 | |||
| 288 | /* only unmasked interrupts kick us out of idle */ | ||
| 289 | __raw_writel(1, irq_base(0) + ICCR); | ||
| 290 | |||
| 291 | pxa_internal_irq_chip.irq_set_wake = fn; | ||
| 292 | } | ||
| 293 | #endif /* CONFIG_OF */ | ||
diff --git a/arch/arm/mach-pxa/pxa-dt.c b/arch/arm/mach-pxa/pxa-dt.c new file mode 100644 index 000000000000..c9192cea0033 --- /dev/null +++ b/arch/arm/mach-pxa/pxa-dt.c | |||
| @@ -0,0 +1,63 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-pxa/pxa-dt.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2012 Daniel Mack | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * publishhed by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/irq.h> | ||
| 12 | #include <linux/irqdomain.h> | ||
| 13 | #include <linux/of_irq.h> | ||
| 14 | #include <linux/of_platform.h> | ||
| 15 | #include <asm/mach/arch.h> | ||
| 16 | #include <asm/mach/time.h> | ||
| 17 | #include <mach/irqs.h> | ||
| 18 | #include <mach/pxa3xx.h> | ||
| 19 | |||
| 20 | #include "generic.h" | ||
| 21 | |||
| 22 | #ifdef CONFIG_PXA3xx | ||
| 23 | extern void __init pxa3xx_dt_init_irq(void); | ||
| 24 | |||
| 25 | static const struct of_dev_auxdata pxa3xx_auxdata_lookup[] __initconst = { | ||
| 26 | OF_DEV_AUXDATA("mrvl,pxa-uart", 0x40100000, "pxa2xx-uart.0", NULL), | ||
| 27 | OF_DEV_AUXDATA("mrvl,pxa-uart", 0x40200000, "pxa2xx-uart.1", NULL), | ||
| 28 | OF_DEV_AUXDATA("mrvl,pxa-uart", 0x40700000, "pxa2xx-uart.2", NULL), | ||
| 29 | OF_DEV_AUXDATA("mrvl,pxa-uart", 0x41600000, "pxa2xx-uart.3", NULL), | ||
| 30 | OF_DEV_AUXDATA("marvell,pxa-mmc", 0x41100000, "pxa2xx-mci.0", NULL), | ||
| 31 | OF_DEV_AUXDATA("mrvl,pxa-gpio", 0x40e00000, "pxa-gpio", NULL), | ||
| 32 | OF_DEV_AUXDATA("marvell,pxa-ohci", 0x4c000000, "pxa27x-ohci", NULL), | ||
| 33 | OF_DEV_AUXDATA("mrvl,pxa-i2c", 0x40301680, "pxa2xx-i2c.0", NULL), | ||
| 34 | OF_DEV_AUXDATA("mrvl,pwri2c", 0x40f500c0, "pxa3xx-i2c.1", NULL), | ||
| 35 | OF_DEV_AUXDATA("marvell,pxa3xx-nand", 0x43100000, "pxa3xx-nand", NULL), | ||
| 36 | {} | ||
| 37 | }; | ||
| 38 | |||
| 39 | static void __init pxa3xx_dt_init(void) | ||
| 40 | { | ||
| 41 | of_platform_populate(NULL, of_default_bus_match_table, | ||
| 42 | pxa3xx_auxdata_lookup, NULL); | ||
| 43 | } | ||
| 44 | |||
| 45 | static const char *pxa3xx_dt_board_compat[] __initdata = { | ||
| 46 | "marvell,pxa300", | ||
| 47 | "marvell,pxa310", | ||
| 48 | "marvell,pxa320", | ||
| 49 | NULL, | ||
| 50 | }; | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifdef CONFIG_PXA3xx | ||
| 54 | DT_MACHINE_START(PXA_DT, "Marvell PXA3xx (Device Tree Support)") | ||
| 55 | .map_io = pxa3xx_map_io, | ||
| 56 | .init_irq = pxa3xx_dt_init_irq, | ||
| 57 | .handle_irq = pxa3xx_handle_irq, | ||
| 58 | .timer = &pxa_timer, | ||
| 59 | .restart = pxa_restart, | ||
| 60 | .init_machine = pxa3xx_dt_init, | ||
| 61 | .dt_compat = pxa3xx_dt_board_compat, | ||
| 62 | MACHINE_END | ||
| 63 | #endif | ||
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index dffb7e813d98..ff9c9574ec3e 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c | |||
| @@ -19,6 +19,7 @@ | |||
| 19 | #include <linux/platform_device.h> | 19 | #include <linux/platform_device.h> |
| 20 | #include <linux/irq.h> | 20 | #include <linux/irq.h> |
| 21 | #include <linux/io.h> | 21 | #include <linux/io.h> |
| 22 | #include <linux/of.h> | ||
| 22 | #include <linux/syscore_ops.h> | 23 | #include <linux/syscore_ops.h> |
| 23 | #include <linux/i2c/pxa-i2c.h> | 24 | #include <linux/i2c/pxa-i2c.h> |
| 24 | 25 | ||
| @@ -40,6 +41,8 @@ | |||
| 40 | #define PECR_IE(n) ((1 << ((n) * 2)) << 28) | 41 | #define PECR_IE(n) ((1 << ((n) * 2)) << 28) |
| 41 | #define PECR_IS(n) ((1 << ((n) * 2)) << 29) | 42 | #define PECR_IS(n) ((1 << ((n) * 2)) << 29) |
| 42 | 43 | ||
| 44 | extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int)); | ||
| 45 | |||
| 43 | static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1); | 46 | static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1); |
| 44 | static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1); | 47 | static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1); |
| 45 | static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1); | 48 | static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1); |
| @@ -382,7 +385,7 @@ static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *, | |||
| 382 | pxa_ext_wakeup_chip.irq_set_wake = fn; | 385 | pxa_ext_wakeup_chip.irq_set_wake = fn; |
| 383 | } | 386 | } |
| 384 | 387 | ||
| 385 | void __init pxa3xx_init_irq(void) | 388 | static void __init __pxa3xx_init_irq(void) |
| 386 | { | 389 | { |
| 387 | /* enable CP6 access */ | 390 | /* enable CP6 access */ |
| 388 | u32 value; | 391 | u32 value; |
| @@ -390,10 +393,23 @@ void __init pxa3xx_init_irq(void) | |||
| 390 | value |= (1 << 6); | 393 | value |= (1 << 6); |
| 391 | __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); | 394 | __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); |
| 392 | 395 | ||
| 393 | pxa_init_irq(56, pxa3xx_set_wake); | ||
| 394 | pxa_init_ext_wakeup_irq(pxa3xx_set_wake); | 396 | pxa_init_ext_wakeup_irq(pxa3xx_set_wake); |
| 395 | } | 397 | } |
| 396 | 398 | ||
| 399 | void __init pxa3xx_init_irq(void) | ||
| 400 | { | ||
| 401 | __pxa3xx_init_irq(); | ||
| 402 | pxa_init_irq(56, pxa3xx_set_wake); | ||
| 403 | } | ||
| 404 | |||
| 405 | #ifdef CONFIG_OF | ||
| 406 | void __init pxa3xx_dt_init_irq(void) | ||
| 407 | { | ||
| 408 | __pxa3xx_init_irq(); | ||
| 409 | pxa_dt_irq_init(pxa3xx_set_wake); | ||
| 410 | } | ||
| 411 | #endif /* CONFIG_OF */ | ||
| 412 | |||
| 397 | static struct map_desc pxa3xx_io_desc[] __initdata = { | 413 | static struct map_desc pxa3xx_io_desc[] __initdata = { |
| 398 | { /* Mem Ctl */ | 414 | { /* Mem Ctl */ |
| 399 | .virtual = (unsigned long)SMEMC_VIRT, | 415 | .virtual = (unsigned long)SMEMC_VIRT, |
| @@ -466,7 +482,8 @@ static int __init pxa3xx_init(void) | |||
| 466 | register_syscore_ops(&pxa3xx_mfp_syscore_ops); | 482 | register_syscore_ops(&pxa3xx_mfp_syscore_ops); |
| 467 | register_syscore_ops(&pxa3xx_clock_syscore_ops); | 483 | register_syscore_ops(&pxa3xx_clock_syscore_ops); |
| 468 | 484 | ||
| 469 | ret = platform_add_devices(devices, ARRAY_SIZE(devices)); | 485 | if (!of_have_populated_dt()) |
| 486 | ret = platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
| 470 | } | 487 | } |
| 471 | 488 | ||
| 472 | return ret; | 489 | return ret; |
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index 45868bb43cbd..ff007d15e0ec 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c | |||
| @@ -30,7 +30,6 @@ | |||
| 30 | #include <linux/ata_platform.h> | 30 | #include <linux/ata_platform.h> |
| 31 | #include <linux/amba/mmci.h> | 31 | #include <linux/amba/mmci.h> |
| 32 | #include <linux/gfp.h> | 32 | #include <linux/gfp.h> |
| 33 | #include <linux/clkdev.h> | ||
| 34 | #include <linux/mtd/physmap.h> | 33 | #include <linux/mtd/physmap.h> |
| 35 | 34 | ||
| 36 | #include <mach/hardware.h> | 35 | #include <mach/hardware.h> |
| @@ -226,115 +225,10 @@ struct mmci_platform_data realview_mmc1_plat_data = { | |||
| 226 | .cd_invert = true, | 225 | .cd_invert = true, |
| 227 | }; | 226 | }; |
| 228 | 227 | ||
| 229 | /* | ||
| 230 | * Clock handling | ||
| 231 | */ | ||
| 232 | static const struct icst_params realview_oscvco_params = { | ||
| 233 | .ref = 24000000, | ||
| 234 | .vco_max = ICST307_VCO_MAX, | ||
| 235 | .vco_min = ICST307_VCO_MIN, | ||
| 236 | .vd_min = 4 + 8, | ||
| 237 | .vd_max = 511 + 8, | ||
| 238 | .rd_min = 1 + 2, | ||
| 239 | .rd_max = 127 + 2, | ||
| 240 | .s2div = icst307_s2div, | ||
| 241 | .idx2s = icst307_idx2s, | ||
| 242 | }; | ||
| 243 | |||
| 244 | static void realview_oscvco_set(struct clk *clk, struct icst_vco vco) | ||
| 245 | { | ||
| 246 | void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET; | ||
| 247 | u32 val; | ||
| 248 | |||
| 249 | val = readl(clk->vcoreg) & ~0x7ffff; | ||
| 250 | val |= vco.v | (vco.r << 9) | (vco.s << 16); | ||
| 251 | |||
| 252 | writel(0xa05f, sys_lock); | ||
| 253 | writel(val, clk->vcoreg); | ||
| 254 | writel(0, sys_lock); | ||
| 255 | } | ||
| 256 | |||
| 257 | static const struct clk_ops oscvco_clk_ops = { | ||
| 258 | .round = icst_clk_round, | ||
| 259 | .set = icst_clk_set, | ||
| 260 | .setvco = realview_oscvco_set, | ||
| 261 | }; | ||
| 262 | |||
| 263 | static struct clk oscvco_clk = { | ||
| 264 | .ops = &oscvco_clk_ops, | ||
| 265 | .params = &realview_oscvco_params, | ||
| 266 | }; | ||
| 267 | |||
| 268 | /* | ||
| 269 | * These are fixed clocks. | ||
| 270 | */ | ||
| 271 | static struct clk ref24_clk = { | ||
| 272 | .rate = 24000000, | ||
| 273 | }; | ||
| 274 | |||
| 275 | static struct clk sp804_clk = { | ||
| 276 | .rate = 1000000, | ||
| 277 | }; | ||
| 278 | |||
| 279 | static struct clk dummy_apb_pclk; | ||
| 280 | |||
| 281 | static struct clk_lookup lookups[] = { | ||
| 282 | { /* Bus clock */ | ||
| 283 | .con_id = "apb_pclk", | ||
| 284 | .clk = &dummy_apb_pclk, | ||
| 285 | }, { /* UART0 */ | ||
| 286 | .dev_id = "dev:uart0", | ||
| 287 | .clk = &ref24_clk, | ||
| 288 | }, { /* UART1 */ | ||
| 289 | .dev_id = "dev:uart1", | ||
| 290 | .clk = &ref24_clk, | ||
| 291 | }, { /* UART2 */ | ||
| 292 | .dev_id = "dev:uart2", | ||
| 293 | .clk = &ref24_clk, | ||
| 294 | }, { /* UART3 */ | ||
| 295 | .dev_id = "fpga:uart3", | ||
| 296 | .clk = &ref24_clk, | ||
| 297 | }, { /* UART3 is on the dev chip in PB1176 */ | ||
| 298 | .dev_id = "dev:uart3", | ||
| 299 | .clk = &ref24_clk, | ||
| 300 | }, { /* UART4 only exists in PB1176 */ | ||
| 301 | .dev_id = "fpga:uart4", | ||
| 302 | .clk = &ref24_clk, | ||
| 303 | }, { /* KMI0 */ | ||
| 304 | .dev_id = "fpga:kmi0", | ||
| 305 | .clk = &ref24_clk, | ||
| 306 | }, { /* KMI1 */ | ||
| 307 | .dev_id = "fpga:kmi1", | ||
| 308 | .clk = &ref24_clk, | ||
| 309 | }, { /* MMC0 */ | ||
| 310 | .dev_id = "fpga:mmc0", | ||
| 311 | .clk = &ref24_clk, | ||
| 312 | }, { /* CLCD is in the PB1176 and EB DevChip */ | ||
| 313 | .dev_id = "dev:clcd", | ||
| 314 | .clk = &oscvco_clk, | ||
| 315 | }, { /* PB:CLCD */ | ||
| 316 | .dev_id = "issp:clcd", | ||
| 317 | .clk = &oscvco_clk, | ||
| 318 | }, { /* SSP */ | ||
| 319 | .dev_id = "dev:ssp0", | ||
| 320 | .clk = &ref24_clk, | ||
| 321 | }, { /* SP804 timers */ | ||
| 322 | .dev_id = "sp804", | ||
| 323 | .clk = &sp804_clk, | ||
| 324 | }, | ||
| 325 | }; | ||
| 326 | |||
| 327 | void __init realview_init_early(void) | 228 | void __init realview_init_early(void) |
| 328 | { | 229 | { |
| 329 | void __iomem *sys = __io_address(REALVIEW_SYS_BASE); | 230 | void __iomem *sys = __io_address(REALVIEW_SYS_BASE); |
| 330 | 231 | ||
| 331 | if (machine_is_realview_pb1176()) | ||
| 332 | oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC0_OFFSET; | ||
| 333 | else | ||
| 334 | oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC4_OFFSET; | ||
| 335 | |||
| 336 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); | ||
| 337 | |||
| 338 | versatile_sched_clock_init(sys + REALVIEW_SYS_24MHz_OFFSET, 24000000); | 232 | versatile_sched_clock_init(sys + REALVIEW_SYS_24MHz_OFFSET, 24000000); |
| 339 | } | 233 | } |
| 340 | 234 | ||
diff --git a/arch/arm/mach-realview/include/mach/clkdev.h b/arch/arm/mach-realview/include/mach/clkdev.h deleted file mode 100644 index e58d0771b64e..000000000000 --- a/arch/arm/mach-realview/include/mach/clkdev.h +++ /dev/null | |||
| @@ -1,16 +0,0 @@ | |||
| 1 | #ifndef __ASM_MACH_CLKDEV_H | ||
| 2 | #define __ASM_MACH_CLKDEV_H | ||
| 3 | |||
| 4 | #include <plat/clock.h> | ||
| 5 | |||
| 6 | struct clk { | ||
| 7 | unsigned long rate; | ||
| 8 | const struct clk_ops *ops; | ||
| 9 | const struct icst_params *params; | ||
| 10 | void __iomem *vcoreg; | ||
| 11 | }; | ||
| 12 | |||
| 13 | #define __clk_get(clk) ({ 1; }) | ||
| 14 | #define __clk_put(clk) do { } while (0) | ||
| 15 | |||
| 16 | #endif | ||
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index baf382c5e776..a33e33b76733 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c | |||
| @@ -27,6 +27,7 @@ | |||
| 27 | #include <linux/amba/mmci.h> | 27 | #include <linux/amba/mmci.h> |
| 28 | #include <linux/amba/pl022.h> | 28 | #include <linux/amba/pl022.h> |
| 29 | #include <linux/io.h> | 29 | #include <linux/io.h> |
| 30 | #include <linux/platform_data/clk-realview.h> | ||
| 30 | 31 | ||
| 31 | #include <mach/hardware.h> | 32 | #include <mach/hardware.h> |
| 32 | #include <asm/irq.h> | 33 | #include <asm/irq.h> |
| @@ -414,6 +415,7 @@ static void __init realview_eb_timer_init(void) | |||
| 414 | else | 415 | else |
| 415 | timer_irq = IRQ_EB_TIMER0_1; | 416 | timer_irq = IRQ_EB_TIMER0_1; |
| 416 | 417 | ||
| 418 | realview_clk_init(__io_address(REALVIEW_SYS_BASE), false); | ||
| 417 | realview_timer_init(timer_irq); | 419 | realview_timer_init(timer_irq); |
| 418 | realview_eb_twd_init(); | 420 | realview_eb_twd_init(); |
| 419 | } | 421 | } |
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c index b1d7cafa1a6d..f0298cbc203e 100644 --- a/arch/arm/mach-realview/realview_pb1176.c +++ b/arch/arm/mach-realview/realview_pb1176.c | |||
| @@ -29,6 +29,7 @@ | |||
| 29 | #include <linux/mtd/physmap.h> | 29 | #include <linux/mtd/physmap.h> |
| 30 | #include <linux/mtd/partitions.h> | 30 | #include <linux/mtd/partitions.h> |
| 31 | #include <linux/io.h> | 31 | #include <linux/io.h> |
| 32 | #include <linux/platform_data/clk-realview.h> | ||
| 32 | 33 | ||
| 33 | #include <mach/hardware.h> | 34 | #include <mach/hardware.h> |
| 34 | #include <asm/irq.h> | 35 | #include <asm/irq.h> |
| @@ -326,6 +327,7 @@ static void __init realview_pb1176_timer_init(void) | |||
| 326 | timer2_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE); | 327 | timer2_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE); |
| 327 | timer3_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE) + 0x20; | 328 | timer3_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE) + 0x20; |
| 328 | 329 | ||
| 330 | realview_clk_init(__io_address(REALVIEW_SYS_BASE), true); | ||
| 329 | realview_timer_init(IRQ_DC1176_TIMER0); | 331 | realview_timer_init(IRQ_DC1176_TIMER0); |
| 330 | } | 332 | } |
| 331 | 333 | ||
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c index a98c536e3327..1f019f76f7b5 100644 --- a/arch/arm/mach-realview/realview_pb11mp.c +++ b/arch/arm/mach-realview/realview_pb11mp.c | |||
| @@ -27,6 +27,7 @@ | |||
| 27 | #include <linux/amba/mmci.h> | 27 | #include <linux/amba/mmci.h> |
| 28 | #include <linux/amba/pl022.h> | 28 | #include <linux/amba/pl022.h> |
| 29 | #include <linux/io.h> | 29 | #include <linux/io.h> |
| 30 | #include <linux/platform_data/clk-realview.h> | ||
| 30 | 31 | ||
| 31 | #include <mach/hardware.h> | 32 | #include <mach/hardware.h> |
| 32 | #include <asm/irq.h> | 33 | #include <asm/irq.h> |
| @@ -312,6 +313,7 @@ static void __init realview_pb11mp_timer_init(void) | |||
| 312 | timer2_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE); | 313 | timer2_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE); |
| 313 | timer3_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE) + 0x20; | 314 | timer3_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE) + 0x20; |
| 314 | 315 | ||
| 316 | realview_clk_init(__io_address(REALVIEW_SYS_BASE), false); | ||
| 315 | realview_timer_init(IRQ_TC11MP_TIMER0_1); | 317 | realview_timer_init(IRQ_TC11MP_TIMER0_1); |
| 316 | realview_pb11mp_twd_init(); | 318 | realview_pb11mp_twd_init(); |
| 317 | } | 319 | } |
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c index 59650174e6ed..5032775dbfee 100644 --- a/arch/arm/mach-realview/realview_pba8.c +++ b/arch/arm/mach-realview/realview_pba8.c | |||
| @@ -27,6 +27,7 @@ | |||
| 27 | #include <linux/amba/mmci.h> | 27 | #include <linux/amba/mmci.h> |
| 28 | #include <linux/amba/pl022.h> | 28 | #include <linux/amba/pl022.h> |
| 29 | #include <linux/io.h> | 29 | #include <linux/io.h> |
| 30 | #include <linux/platform_data/clk-realview.h> | ||
| 30 | 31 | ||
| 31 | #include <asm/irq.h> | 32 | #include <asm/irq.h> |
| 32 | #include <asm/leds.h> | 33 | #include <asm/leds.h> |
| @@ -261,6 +262,7 @@ static void __init realview_pba8_timer_init(void) | |||
| 261 | timer2_va_base = __io_address(REALVIEW_PBA8_TIMER2_3_BASE); | 262 | timer2_va_base = __io_address(REALVIEW_PBA8_TIMER2_3_BASE); |
| 262 | timer3_va_base = __io_address(REALVIEW_PBA8_TIMER2_3_BASE) + 0x20; | 263 | timer3_va_base = __io_address(REALVIEW_PBA8_TIMER2_3_BASE) + 0x20; |
| 263 | 264 | ||
| 265 | realview_clk_init(__io_address(REALVIEW_SYS_BASE), false); | ||
| 264 | realview_timer_init(IRQ_PBA8_TIMER0_1); | 266 | realview_timer_init(IRQ_PBA8_TIMER0_1); |
| 265 | } | 267 | } |
| 266 | 268 | ||
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c index 3f2f605624e9..de64ba0ddb95 100644 --- a/arch/arm/mach-realview/realview_pbx.c +++ b/arch/arm/mach-realview/realview_pbx.c | |||
| @@ -26,6 +26,7 @@ | |||
| 26 | #include <linux/amba/mmci.h> | 26 | #include <linux/amba/mmci.h> |
| 27 | #include <linux/amba/pl022.h> | 27 | #include <linux/amba/pl022.h> |
| 28 | #include <linux/io.h> | 28 | #include <linux/io.h> |
| 29 | #include <linux/platform_data/clk-realview.h> | ||
| 29 | 30 | ||
| 30 | #include <asm/irq.h> | 31 | #include <asm/irq.h> |
| 31 | #include <asm/leds.h> | 32 | #include <asm/leds.h> |
| @@ -320,6 +321,7 @@ static void __init realview_pbx_timer_init(void) | |||
| 320 | timer2_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE); | 321 | timer2_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE); |
| 321 | timer3_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE) + 0x20; | 322 | timer3_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE) + 0x20; |
| 322 | 323 | ||
| 324 | realview_clk_init(__io_address(REALVIEW_SYS_BASE), false); | ||
| 323 | realview_timer_init(IRQ_PBX_TIMER0_1); | 325 | realview_timer_init(IRQ_PBX_TIMER0_1); |
| 324 | realview_pbx_twd_init(); | 326 | realview_pbx_twd_init(); |
| 325 | } | 327 | } |
diff --git a/arch/arm/mach-s3c24xx/include/mach/dma.h b/arch/arm/mach-s3c24xx/include/mach/dma.h index 454831b66037..ee99fd56c043 100644 --- a/arch/arm/mach-s3c24xx/include/mach/dma.h +++ b/arch/arm/mach-s3c24xx/include/mach/dma.h | |||
| @@ -24,7 +24,8 @@ | |||
| 24 | */ | 24 | */ |
| 25 | 25 | ||
| 26 | enum dma_ch { | 26 | enum dma_ch { |
| 27 | DMACH_XD0, | 27 | DMACH_DT_PROP = -1, /* not yet supported, do not use */ |
| 28 | DMACH_XD0 = 0, | ||
| 28 | DMACH_XD1, | 29 | DMACH_XD1, |
| 29 | DMACH_SDI, | 30 | DMACH_SDI, |
| 30 | DMACH_SPI0, | 31 | DMACH_SPI0, |
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot index 498efd99338d..5e410192ffb8 100644 --- a/arch/arm/mach-shmobile/Makefile.boot +++ b/arch/arm/mach-shmobile/Makefile.boot | |||
| @@ -7,3 +7,7 @@ __ZRELADDR := $(shell /bin/bash -c 'printf "0x%08x" \ | |||
| 7 | # | 7 | # |
| 8 | #params_phys-y (Instead: Pass atags pointer in r2) | 8 | #params_phys-y (Instead: Pass atags pointer in r2) |
| 9 | #initrd_phys-y (Instead: Use compiled-in initramfs) | 9 | #initrd_phys-y (Instead: Use compiled-in initramfs) |
| 10 | |||
| 11 | dtb-$(CONFIG_MACH_KZM9G) += sh73a0-kzm9g.dtb | ||
| 12 | dtb-$(CONFIG_MACH_KZM9D) += emev2-kzm9d.dtb | ||
| 13 | dtb-$(CONFIG_MACH_ARMADILLO800EVA) += r8a7740-armadillo800eva.dtb | ||
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index c013bbf79cac..a258996d954b 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig | |||
| @@ -11,6 +11,7 @@ config UX500_SOC_COMMON | |||
| 11 | select CACHE_L2X0 | 11 | select CACHE_L2X0 |
| 12 | select PINCTRL | 12 | select PINCTRL |
| 13 | select PINCTRL_NOMADIK | 13 | select PINCTRL_NOMADIK |
| 14 | select COMMON_CLK | ||
| 14 | 15 | ||
| 15 | config UX500_SOC_DB8500 | 16 | config UX500_SOC_DB8500 |
| 16 | bool | 17 | bool |
| @@ -41,7 +42,6 @@ config MACH_HREFV60 | |||
| 41 | config MACH_SNOWBALL | 42 | config MACH_SNOWBALL |
| 42 | bool "U8500 Snowball platform" | 43 | bool "U8500 Snowball platform" |
| 43 | select MACH_MOP500 | 44 | select MACH_MOP500 |
| 44 | select LEDS_GPIO | ||
| 45 | help | 45 | help |
| 46 | Include support for the snowball development platform. | 46 | Include support for the snowball development platform. |
| 47 | 47 | ||
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile index 026086ff9e6c..5691ef679d01 100644 --- a/arch/arm/mach-ux500/Makefile +++ b/arch/arm/mach-ux500/Makefile | |||
| @@ -2,7 +2,7 @@ | |||
| 2 | # Makefile for the linux kernel, U8500 machine. | 2 | # Makefile for the linux kernel, U8500 machine. |
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | obj-y := clock.o cpu.o devices.o devices-common.o \ | 5 | obj-y := cpu.o devices.o devices-common.o \ |
| 6 | id.o usb.o timer.o | 6 | id.o usb.o timer.o |
| 7 | obj-$(CONFIG_CPU_IDLE) += cpuidle.o | 7 | obj-$(CONFIG_CPU_IDLE) += cpuidle.o |
| 8 | obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o | 8 | obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o |
diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-msp.c index 996048038743..df15646036aa 100644 --- a/arch/arm/mach-ux500/board-mop500-msp.c +++ b/arch/arm/mach-ux500/board-mop500-msp.c | |||
| @@ -191,9 +191,9 @@ static struct platform_device *db8500_add_msp_i2s(struct device *parent, | |||
| 191 | return pdev; | 191 | return pdev; |
| 192 | } | 192 | } |
| 193 | 193 | ||
| 194 | /* Platform device for ASoC U8500 machine */ | 194 | /* Platform device for ASoC MOP500 machine */ |
| 195 | static struct platform_device snd_soc_u8500 = { | 195 | static struct platform_device snd_soc_mop500 = { |
| 196 | .name = "snd-soc-u8500", | 196 | .name = "snd-soc-mop500", |
| 197 | .id = 0, | 197 | .id = 0, |
| 198 | .dev = { | 198 | .dev = { |
| 199 | .platform_data = NULL, | 199 | .platform_data = NULL, |
| @@ -227,8 +227,8 @@ int mop500_msp_init(struct device *parent) | |||
| 227 | { | 227 | { |
| 228 | struct platform_device *msp1; | 228 | struct platform_device *msp1; |
| 229 | 229 | ||
| 230 | pr_info("%s: Register platform-device 'snd-soc-u8500'.\n", __func__); | 230 | pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__); |
| 231 | platform_device_register(&snd_soc_u8500); | 231 | platform_device_register(&snd_soc_mop500); |
| 232 | 232 | ||
| 233 | pr_info("Initialize MSP I2S-devices.\n"); | 233 | pr_info("Initialize MSP I2S-devices.\n"); |
| 234 | db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0, | 234 | db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0, |
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index 8674a890fd1c..a534d8880de1 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c | |||
| @@ -797,6 +797,7 @@ static void __init u8500_init_machine(void) | |||
| 797 | ARRAY_SIZE(mop500_platform_devs)); | 797 | ARRAY_SIZE(mop500_platform_devs)); |
| 798 | 798 | ||
| 799 | mop500_sdi_init(parent); | 799 | mop500_sdi_init(parent); |
| 800 | mop500_msp_init(parent); | ||
| 800 | i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); | 801 | i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); |
| 801 | i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs); | 802 | i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs); |
| 802 | i2c_register_board_info(2, mop500_i2c2_devices, | 803 | i2c_register_board_info(2, mop500_i2c2_devices, |
| @@ -804,6 +805,8 @@ static void __init u8500_init_machine(void) | |||
| 804 | 805 | ||
| 805 | mop500_uib_init(); | 806 | mop500_uib_init(); |
| 806 | 807 | ||
| 808 | } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) { | ||
| 809 | mop500_msp_init(parent); | ||
| 807 | } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) { | 810 | } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) { |
| 808 | /* | 811 | /* |
| 809 | * The HREFv60 board removed a GPIO expander and routed | 812 | * The HREFv60 board removed a GPIO expander and routed |
| @@ -815,6 +818,7 @@ static void __init u8500_init_machine(void) | |||
| 815 | ARRAY_SIZE(mop500_platform_devs)); | 818 | ARRAY_SIZE(mop500_platform_devs)); |
| 816 | 819 | ||
| 817 | hrefv60_sdi_init(parent); | 820 | hrefv60_sdi_init(parent); |
| 821 | mop500_msp_init(parent); | ||
| 818 | 822 | ||
| 819 | i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); | 823 | i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); |
| 820 | i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES; | 824 | i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES; |
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c deleted file mode 100644 index 8d73b066a18d..000000000000 --- a/arch/arm/mach-ux500/clock.c +++ /dev/null | |||
| @@ -1,715 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009 ST-Ericsson | ||
| 3 | * Copyright (C) 2009 STMicroelectronics | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License version 2 as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include <linux/module.h> | ||
| 10 | #include <linux/kernel.h> | ||
| 11 | #include <linux/list.h> | ||
| 12 | #include <linux/errno.h> | ||
| 13 | #include <linux/err.h> | ||
| 14 | #include <linux/clk.h> | ||
| 15 | #include <linux/io.h> | ||
| 16 | #include <linux/clkdev.h> | ||
| 17 | #include <linux/cpufreq.h> | ||
| 18 | |||
| 19 | #include <plat/mtu.h> | ||
| 20 | #include <mach/hardware.h> | ||
| 21 | #include "clock.h" | ||
| 22 | |||
| 23 | #ifdef CONFIG_DEBUG_FS | ||
| 24 | #include <linux/debugfs.h> | ||
| 25 | #include <linux/uaccess.h> /* for copy_from_user */ | ||
| 26 | static LIST_HEAD(clk_list); | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #define PRCC_PCKEN 0x00 | ||
| 30 | #define PRCC_PCKDIS 0x04 | ||
| 31 | #define PRCC_KCKEN 0x08 | ||
| 32 | #define PRCC_KCKDIS 0x0C | ||
| 33 | |||
| 34 | #define PRCM_YYCLKEN0_MGT_SET 0x510 | ||
| 35 | #define PRCM_YYCLKEN1_MGT_SET 0x514 | ||
| 36 | #define PRCM_YYCLKEN0_MGT_CLR 0x518 | ||
| 37 | #define PRCM_YYCLKEN1_MGT_CLR 0x51C | ||
| 38 | #define PRCM_YYCLKEN0_MGT_VAL 0x520 | ||
| 39 | #define PRCM_YYCLKEN1_MGT_VAL 0x524 | ||
| 40 | |||
| 41 | #define PRCM_SVAMMDSPCLK_MGT 0x008 | ||
| 42 | #define PRCM_SIAMMDSPCLK_MGT 0x00C | ||
| 43 | #define PRCM_SGACLK_MGT 0x014 | ||
| 44 | #define PRCM_UARTCLK_MGT 0x018 | ||
| 45 | #define PRCM_MSP02CLK_MGT 0x01C | ||
| 46 | #define PRCM_MSP1CLK_MGT 0x288 | ||
| 47 | #define PRCM_I2CCLK_MGT 0x020 | ||
| 48 | #define PRCM_SDMMCCLK_MGT 0x024 | ||
| 49 | #define PRCM_SLIMCLK_MGT 0x028 | ||
| 50 | #define PRCM_PER1CLK_MGT 0x02C | ||
| 51 | #define PRCM_PER2CLK_MGT 0x030 | ||
| 52 | #define PRCM_PER3CLK_MGT 0x034 | ||
| 53 | #define PRCM_PER5CLK_MGT 0x038 | ||
| 54 | #define PRCM_PER6CLK_MGT 0x03C | ||
| 55 | #define PRCM_PER7CLK_MGT 0x040 | ||
| 56 | #define PRCM_LCDCLK_MGT 0x044 | ||
| 57 | #define PRCM_BMLCLK_MGT 0x04C | ||
| 58 | #define PRCM_HSITXCLK_MGT 0x050 | ||
| 59 | #define PRCM_HSIRXCLK_MGT 0x054 | ||
| 60 | #define PRCM_HDMICLK_MGT 0x058 | ||
| 61 | #define PRCM_APEATCLK_MGT 0x05C | ||
| 62 | #define PRCM_APETRACECLK_MGT 0x060 | ||
| 63 | #define PRCM_MCDECLK_MGT 0x064 | ||
| 64 | #define PRCM_IPI2CCLK_MGT 0x068 | ||
| 65 | #define PRCM_DSIALTCLK_MGT 0x06C | ||
| 66 | #define PRCM_DMACLK_MGT 0x074 | ||
| 67 | #define PRCM_B2R2CLK_MGT 0x078 | ||
| 68 | #define PRCM_TVCLK_MGT 0x07C | ||
| 69 | #define PRCM_TCR 0x1C8 | ||
| 70 | #define PRCM_TCR_STOPPED (1 << 16) | ||
| 71 | #define PRCM_TCR_DOZE_MODE (1 << 17) | ||
| 72 | #define PRCM_UNIPROCLK_MGT 0x278 | ||
| 73 | #define PRCM_SSPCLK_MGT 0x280 | ||
| 74 | #define PRCM_RNGCLK_MGT 0x284 | ||
| 75 | #define PRCM_UICCCLK_MGT 0x27C | ||
| 76 | |||
| 77 | #define PRCM_MGT_ENABLE (1 << 8) | ||
| 78 | |||
| 79 | static DEFINE_SPINLOCK(clocks_lock); | ||
| 80 | |||
| 81 | static void __clk_enable(struct clk *clk) | ||
| 82 | { | ||
| 83 | if (clk->enabled++ == 0) { | ||
| 84 | if (clk->parent_cluster) | ||
| 85 | __clk_enable(clk->parent_cluster); | ||
| 86 | |||
| 87 | if (clk->parent_periph) | ||
| 88 | __clk_enable(clk->parent_periph); | ||
| 89 | |||
| 90 | if (clk->ops && clk->ops->enable) | ||
| 91 | clk->ops->enable(clk); | ||
| 92 | } | ||
| 93 | } | ||
| 94 | |||
| 95 | int clk_enable(struct clk *clk) | ||
| 96 | { | ||
| 97 | unsigned long flags; | ||
| 98 | |||
| 99 | spin_lock_irqsave(&clocks_lock, flags); | ||
| 100 | __clk_enable(clk); | ||
| 101 | spin_unlock_irqrestore(&clocks_lock, flags); | ||
| 102 | |||
| 103 | return 0; | ||
| 104 | } | ||
| 105 | EXPORT_SYMBOL(clk_enable); | ||
| 106 | |||
| 107 | static void __clk_disable(struct clk *clk) | ||
| 108 | { | ||
| 109 | if (--clk->enabled == 0) { | ||
| 110 | if (clk->ops && clk->ops->disable) | ||
| 111 | clk->ops->disable(clk); | ||
| 112 | |||
| 113 | if (clk->parent_periph) | ||
| 114 | __clk_disable(clk->parent_periph); | ||
| 115 | |||
| 116 | if (clk->parent_cluster) | ||
| 117 | __clk_disable(clk->parent_cluster); | ||
| 118 | } | ||
| 119 | } | ||
| 120 | |||
| 121 | void clk_disable(struct clk *clk) | ||
| 122 | { | ||
| 123 | unsigned long flags; | ||
| 124 | |||
| 125 | WARN_ON(!clk->enabled); | ||
| 126 | |||
| 127 | spin_lock_irqsave(&clocks_lock, flags); | ||
| 128 | __clk_disable(clk); | ||
| 129 | spin_unlock_irqrestore(&clocks_lock, flags); | ||
| 130 | } | ||
| 131 | EXPORT_SYMBOL(clk_disable); | ||
| 132 | |||
| 133 | /* | ||
| 134 | * The MTU has a separate, rather complex muxing setup | ||
| 135 | * with alternative parents (peripheral cluster or | ||
| 136 | * ULP or fixed 32768 Hz) depending on settings | ||
| 137 | */ | ||
| 138 | static unsigned long clk_mtu_get_rate(struct clk *clk) | ||
| 139 | { | ||
| 140 | void __iomem *addr; | ||
| 141 | u32 tcr; | ||
| 142 | int mtu = (int) clk->data; | ||
| 143 | /* | ||
| 144 | * One of these is selected eventually | ||
| 145 | * TODO: Replace the constant with a reference | ||
| 146 | * to the ULP source once this is modeled. | ||
| 147 | */ | ||
| 148 | unsigned long clk32k = 32768; | ||
| 149 | unsigned long mturate; | ||
| 150 | unsigned long retclk; | ||
| 151 | |||
| 152 | if (cpu_is_u8500_family()) | ||
| 153 | addr = __io_address(U8500_PRCMU_BASE); | ||
| 154 | else | ||
| 155 | ux500_unknown_soc(); | ||
| 156 | |||
| 157 | /* | ||
| 158 | * On a startup, always conifgure the TCR to the doze mode; | ||
| 159 | * bootloaders do it for us. Do this in the kernel too. | ||
| 160 | */ | ||
| 161 | writel(PRCM_TCR_DOZE_MODE, addr + PRCM_TCR); | ||
| 162 | |||
| 163 | tcr = readl(addr + PRCM_TCR); | ||
| 164 | |||
| 165 | /* Get the rate from the parent as a default */ | ||
| 166 | if (clk->parent_periph) | ||
| 167 | mturate = clk_get_rate(clk->parent_periph); | ||
| 168 | else if (clk->parent_cluster) | ||
| 169 | mturate = clk_get_rate(clk->parent_cluster); | ||
| 170 | else | ||
| 171 | /* We need to be connected SOMEWHERE */ | ||
| 172 | BUG(); | ||
| 173 | |||
| 174 | /* Return the clock selected for this MTU */ | ||
| 175 | if (tcr & (1 << mtu)) | ||
| 176 | retclk = clk32k; | ||
| 177 | else | ||
| 178 | retclk = mturate; | ||
| 179 | |||
| 180 | pr_info("MTU%d clock rate: %lu Hz\n", mtu, retclk); | ||
| 181 | return retclk; | ||
| 182 | } | ||
| 183 | |||
| 184 | unsigned long clk_get_rate(struct clk *clk) | ||
| 185 | { | ||
| 186 | unsigned long rate; | ||
| 187 | |||
| 188 | /* | ||
| 189 | * If there is a custom getrate callback for this clock, | ||
| 190 | * it will take precedence. | ||
| 191 | */ | ||
| 192 | if (clk->get_rate) | ||
| 193 | return clk->get_rate(clk); | ||
| 194 | |||
| 195 | if (clk->ops && clk->ops->get_rate) | ||
| 196 | return clk->ops->get_rate(clk); | ||
| 197 | |||
| 198 | rate = clk->rate; | ||
| 199 | if (!rate) { | ||
| 200 | if (clk->parent_periph) | ||
| 201 | rate = clk_get_rate(clk->parent_periph); | ||
| 202 | else if (clk->parent_cluster) | ||
| 203 | rate = clk_get_rate(clk->parent_cluster); | ||
| 204 | } | ||
| 205 | |||
| 206 | return rate; | ||
| 207 | } | ||
| 208 | EXPORT_SYMBOL(clk_get_rate); | ||
| 209 | |||
| 210 | long clk_round_rate(struct clk *clk, unsigned long rate) | ||
| 211 | { | ||
| 212 | /*TODO*/ | ||
| 213 | return rate; | ||
| 214 | } | ||
| 215 | EXPORT_SYMBOL(clk_round_rate); | ||
| 216 | |||
| 217 | int clk_set_rate(struct clk *clk, unsigned long rate) | ||
| 218 | { | ||
| 219 | clk->rate = rate; | ||
| 220 | return 0; | ||
| 221 | } | ||
| 222 | EXPORT_SYMBOL(clk_set_rate); | ||
| 223 | |||
| 224 | int clk_set_parent(struct clk *clk, struct clk *parent) | ||
| 225 | { | ||
| 226 | /*TODO*/ | ||
| 227 | return -ENOSYS; | ||
| 228 | } | ||
| 229 | EXPORT_SYMBOL(clk_set_parent); | ||
| 230 | |||
| 231 | static void clk_prcmu_enable(struct clk *clk) | ||
| 232 | { | ||
| 233 | void __iomem *cg_set_reg = __io_address(U8500_PRCMU_BASE) | ||
| 234 | + PRCM_YYCLKEN0_MGT_SET + clk->prcmu_cg_off; | ||
| 235 | |||
| 236 | writel(1 << clk->prcmu_cg_bit, cg_set_reg); | ||
| 237 | } | ||
| 238 | |||
| 239 | static void clk_prcmu_disable(struct clk *clk) | ||
| 240 | { | ||
| 241 | void __iomem *cg_clr_reg = __io_address(U8500_PRCMU_BASE) | ||
| 242 | + PRCM_YYCLKEN0_MGT_CLR + clk->prcmu_cg_off; | ||
| 243 | |||
| 244 | writel(1 << clk->prcmu_cg_bit, cg_clr_reg); | ||
| 245 | } | ||
| 246 | |||
| 247 | static struct clkops clk_prcmu_ops = { | ||
| 248 | .enable = clk_prcmu_enable, | ||
| 249 | .disable = clk_prcmu_disable, | ||
| 250 | }; | ||
| 251 | |||
| 252 | static unsigned int clkrst_base[] = { | ||
| 253 | [1] = U8500_CLKRST1_BASE, | ||
| 254 | [2] = U8500_CLKRST2_BASE, | ||
| 255 | [3] = U8500_CLKRST3_BASE, | ||
| 256 | [5] = U8500_CLKRST5_BASE, | ||
| 257 | [6] = U8500_CLKRST6_BASE, | ||
| 258 | }; | ||
| 259 | |||
| 260 | static void clk_prcc_enable(struct clk *clk) | ||
| 261 | { | ||
| 262 | void __iomem *addr = __io_address(clkrst_base[clk->cluster]); | ||
| 263 | |||
| 264 | if (clk->prcc_kernel != -1) | ||
| 265 | writel(1 << clk->prcc_kernel, addr + PRCC_KCKEN); | ||
| 266 | |||
| 267 | if (clk->prcc_bus != -1) | ||
| 268 | writel(1 << clk->prcc_bus, addr + PRCC_PCKEN); | ||
| 269 | } | ||
| 270 | |||
| 271 | static void clk_prcc_disable(struct clk *clk) | ||
| 272 | { | ||
| 273 | void __iomem *addr = __io_address(clkrst_base[clk->cluster]); | ||
| 274 | |||
| 275 | if (clk->prcc_bus != -1) | ||
| 276 | writel(1 << clk->prcc_bus, addr + PRCC_PCKDIS); | ||
| 277 | |||
| 278 | if (clk->prcc_kernel != -1) | ||
| 279 | writel(1 << clk->prcc_kernel, addr + PRCC_KCKDIS); | ||
| 280 | } | ||
| 281 | |||
| 282 | static struct clkops clk_prcc_ops = { | ||
| 283 | .enable = clk_prcc_enable, | ||
| 284 | .disable = clk_prcc_disable, | ||
| 285 | }; | ||
| 286 | |||
| 287 | static struct clk clk_32khz = { | ||
| 288 | .name = "clk_32khz", | ||
| 289 | .rate = 32000, | ||
| 290 | }; | ||
| 291 | |||
| 292 | /* | ||
| 293 | * PRCMU level clock gating | ||
| 294 | */ | ||
| 295 | |||
| 296 | /* Bank 0 */ | ||
| 297 | static DEFINE_PRCMU_CLK(svaclk, 0x0, 2, SVAMMDSPCLK); | ||
| 298 | static DEFINE_PRCMU_CLK(siaclk, 0x0, 3, SIAMMDSPCLK); | ||
| 299 | static DEFINE_PRCMU_CLK(sgaclk, 0x0, 4, SGACLK); | ||
| 300 | static DEFINE_PRCMU_CLK_RATE(uartclk, 0x0, 5, UARTCLK, 38400000); | ||
| 301 | static DEFINE_PRCMU_CLK(msp02clk, 0x0, 6, MSP02CLK); | ||
| 302 | static DEFINE_PRCMU_CLK(msp1clk, 0x0, 7, MSP1CLK); /* v1 */ | ||
| 303 | static DEFINE_PRCMU_CLK_RATE(i2cclk, 0x0, 8, I2CCLK, 48000000); | ||
| 304 | static DEFINE_PRCMU_CLK_RATE(sdmmcclk, 0x0, 9, SDMMCCLK, 100000000); | ||
| 305 | static DEFINE_PRCMU_CLK(slimclk, 0x0, 10, SLIMCLK); | ||
| 306 | static DEFINE_PRCMU_CLK(per1clk, 0x0, 11, PER1CLK); | ||
| 307 | static DEFINE_PRCMU_CLK(per2clk, 0x0, 12, PER2CLK); | ||
| 308 | static DEFINE_PRCMU_CLK(per3clk, 0x0, 13, PER3CLK); | ||
| 309 | static DEFINE_PRCMU_CLK(per5clk, 0x0, 14, PER5CLK); | ||
| 310 | static DEFINE_PRCMU_CLK_RATE(per6clk, 0x0, 15, PER6CLK, 133330000); | ||
| 311 | static DEFINE_PRCMU_CLK(lcdclk, 0x0, 17, LCDCLK); | ||
| 312 | static DEFINE_PRCMU_CLK(bmlclk, 0x0, 18, BMLCLK); | ||
| 313 | static DEFINE_PRCMU_CLK(hsitxclk, 0x0, 19, HSITXCLK); | ||
| 314 | static DEFINE_PRCMU_CLK(hsirxclk, 0x0, 20, HSIRXCLK); | ||
| 315 | static DEFINE_PRCMU_CLK(hdmiclk, 0x0, 21, HDMICLK); | ||
| 316 | static DEFINE_PRCMU_CLK(apeatclk, 0x0, 22, APEATCLK); | ||
| 317 | static DEFINE_PRCMU_CLK(apetraceclk, 0x0, 23, APETRACECLK); | ||
| 318 | static DEFINE_PRCMU_CLK(mcdeclk, 0x0, 24, MCDECLK); | ||
| 319 | static DEFINE_PRCMU_CLK(ipi2clk, 0x0, 25, IPI2CCLK); | ||
| 320 | static DEFINE_PRCMU_CLK(dsialtclk, 0x0, 26, DSIALTCLK); /* v1 */ | ||
| 321 | static DEFINE_PRCMU_CLK(dmaclk, 0x0, 27, DMACLK); | ||
| 322 | static DEFINE_PRCMU_CLK(b2r2clk, 0x0, 28, B2R2CLK); | ||
| 323 | static DEFINE_PRCMU_CLK(tvclk, 0x0, 29, TVCLK); | ||
| 324 | static DEFINE_PRCMU_CLK(uniproclk, 0x0, 30, UNIPROCLK); /* v1 */ | ||
| 325 | static DEFINE_PRCMU_CLK_RATE(sspclk, 0x0, 31, SSPCLK, 48000000); /* v1 */ | ||
| 326 | |||
| 327 | /* Bank 1 */ | ||
| 328 | static DEFINE_PRCMU_CLK(rngclk, 0x4, 0, RNGCLK); /* v1 */ | ||
| 329 | static DEFINE_PRCMU_CLK(uiccclk, 0x4, 1, UICCCLK); /* v1 */ | ||
| 330 | |||
| 331 | /* | ||
| 332 | * PRCC level clock gating | ||
| 333 | * Format: per#, clk, PCKEN bit, KCKEN bit, parent | ||
| 334 | */ | ||
| 335 | |||
| 336 | /* Peripheral Cluster #1 */ | ||
| 337 | static DEFINE_PRCC_CLK(1, msp3, 11, 10, &clk_msp1clk); | ||
| 338 | static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk); | ||
| 339 | static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL); | ||
| 340 | static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk); | ||
| 341 | static DEFINE_PRCC_CLK(1, spi3, 7, -1, NULL); | ||
| 342 | static DEFINE_PRCC_CLK(1, i2c2, 6, 6, &clk_i2cclk); | ||
| 343 | static DEFINE_PRCC_CLK(1, sdi0, 5, 5, &clk_sdmmcclk); | ||
| 344 | static DEFINE_PRCC_CLK(1, msp1, 4, 4, &clk_msp1clk); | ||
| 345 | static DEFINE_PRCC_CLK(1, msp0, 3, 3, &clk_msp02clk); | ||
| 346 | static DEFINE_PRCC_CLK(1, i2c1, 2, 2, &clk_i2cclk); | ||
| 347 | static DEFINE_PRCC_CLK(1, uart1, 1, 1, &clk_uartclk); | ||
| 348 | static DEFINE_PRCC_CLK(1, uart0, 0, 0, &clk_uartclk); | ||
| 349 | |||
| 350 | /* Peripheral Cluster #2 */ | ||
| 351 | static DEFINE_PRCC_CLK(2, gpio1, 11, -1, NULL); | ||
| 352 | static DEFINE_PRCC_CLK(2, ssitx, 10, 7, NULL); | ||
| 353 | static DEFINE_PRCC_CLK(2, ssirx, 9, 6, NULL); | ||
| 354 | static DEFINE_PRCC_CLK(2, spi0, 8, -1, NULL); | ||
| 355 | static DEFINE_PRCC_CLK(2, sdi3, 7, 5, &clk_sdmmcclk); | ||
| 356 | static DEFINE_PRCC_CLK(2, sdi1, 6, 4, &clk_sdmmcclk); | ||
| 357 | static DEFINE_PRCC_CLK(2, msp2, 5, 3, &clk_msp02clk); | ||
| 358 | static DEFINE_PRCC_CLK(2, sdi4, 4, 2, &clk_sdmmcclk); | ||
| 359 | static DEFINE_PRCC_CLK(2, pwl, 3, 1, NULL); | ||
| 360 | static DEFINE_PRCC_CLK(2, spi1, 2, -1, NULL); | ||
| 361 | static DEFINE_PRCC_CLK(2, spi2, 1, -1, NULL); | ||
| 362 | static DEFINE_PRCC_CLK(2, i2c3, 0, 0, &clk_i2cclk); | ||
| 363 | |||
| 364 | /* Peripheral Cluster #3 */ | ||
| 365 | static DEFINE_PRCC_CLK(3, gpio2, 8, -1, NULL); | ||
| 366 | static DEFINE_PRCC_CLK(3, sdi5, 7, 7, &clk_sdmmcclk); | ||
| 367 | static DEFINE_PRCC_CLK(3, uart2, 6, 6, &clk_uartclk); | ||
| 368 | static DEFINE_PRCC_CLK(3, ske, 5, 5, &clk_32khz); | ||
| 369 | static DEFINE_PRCC_CLK(3, sdi2, 4, 4, &clk_sdmmcclk); | ||
| 370 | static DEFINE_PRCC_CLK(3, i2c0, 3, 3, &clk_i2cclk); | ||
| 371 | static DEFINE_PRCC_CLK(3, ssp1, 2, 2, &clk_sspclk); | ||
| 372 | static DEFINE_PRCC_CLK(3, ssp0, 1, 1, &clk_sspclk); | ||
| 373 | static DEFINE_PRCC_CLK(3, fsmc, 0, -1, NULL); | ||
| 374 | |||
| 375 | /* Peripheral Cluster #4 is in the always on domain */ | ||
| 376 | |||
| 377 | /* Peripheral Cluster #5 */ | ||
| 378 | static DEFINE_PRCC_CLK(5, gpio3, 1, -1, NULL); | ||
| 379 | static DEFINE_PRCC_CLK(5, usb, 0, 0, NULL); | ||
| 380 | |||
| 381 | /* Peripheral Cluster #6 */ | ||
| 382 | |||
| 383 | /* MTU ID in data */ | ||
| 384 | static DEFINE_PRCC_CLK_CUSTOM(6, mtu1, 9, -1, NULL, clk_mtu_get_rate, 1); | ||
| 385 | static DEFINE_PRCC_CLK_CUSTOM(6, mtu0, 8, -1, NULL, clk_mtu_get_rate, 0); | ||
| 386 | static DEFINE_PRCC_CLK(6, cfgreg, 7, 7, NULL); | ||
| 387 | static DEFINE_PRCC_CLK(6, hash1, 6, -1, NULL); | ||
| 388 | static DEFINE_PRCC_CLK(6, unipro, 5, 1, &clk_uniproclk); | ||
| 389 | static DEFINE_PRCC_CLK(6, pka, 4, -1, NULL); | ||
| 390 | static DEFINE_PRCC_CLK(6, hash0, 3, -1, NULL); | ||
| 391 | static DEFINE_PRCC_CLK(6, cryp0, 2, -1, NULL); | ||
| 392 | static DEFINE_PRCC_CLK(6, cryp1, 1, -1, NULL); | ||
| 393 | static DEFINE_PRCC_CLK(6, rng, 0, 0, &clk_rngclk); | ||
| 394 | |||
| 395 | static struct clk clk_dummy_apb_pclk = { | ||
| 396 | .name = "apb_pclk", | ||
| 397 | }; | ||
| 398 | |||
| 399 | static struct clk_lookup u8500_clks[] = { | ||
| 400 | CLK(dummy_apb_pclk, NULL, "apb_pclk"), | ||
| 401 | |||
| 402 | /* Peripheral Cluster #1 */ | ||
| 403 | CLK(gpio0, "gpio.0", NULL), | ||
| 404 | CLK(gpio0, "gpio.1", NULL), | ||
| 405 | CLK(slimbus0, "slimbus0", NULL), | ||
| 406 | CLK(i2c2, "nmk-i2c.2", NULL), | ||
| 407 | CLK(sdi0, "sdi0", NULL), | ||
| 408 | CLK(msp0, "ux500-msp-i2s.0", NULL), | ||
| 409 | CLK(i2c1, "nmk-i2c.1", NULL), | ||
| 410 | CLK(uart1, "uart1", NULL), | ||
| 411 | CLK(uart0, "uart0", NULL), | ||
| 412 | |||
| 413 | /* Peripheral Cluster #3 */ | ||
| 414 | CLK(gpio2, "gpio.2", NULL), | ||
| 415 | CLK(gpio2, "gpio.3", NULL), | ||
| 416 | CLK(gpio2, "gpio.4", NULL), | ||
| 417 | CLK(gpio2, "gpio.5", NULL), | ||
| 418 | CLK(sdi5, "sdi5", NULL), | ||
| 419 | CLK(uart2, "uart2", NULL), | ||
| 420 | CLK(ske, "ske", NULL), | ||
| 421 | CLK(ske, "nmk-ske-keypad", NULL), | ||
| 422 | CLK(sdi2, "sdi2", NULL), | ||
| 423 | CLK(i2c0, "nmk-i2c.0", NULL), | ||
| 424 | CLK(fsmc, "fsmc", NULL), | ||
| 425 | |||
| 426 | /* Peripheral Cluster #5 */ | ||
| 427 | CLK(gpio3, "gpio.8", NULL), | ||
| 428 | |||
| 429 | /* Peripheral Cluster #6 */ | ||
| 430 | CLK(hash1, "hash1", NULL), | ||
| 431 | CLK(pka, "pka", NULL), | ||
| 432 | CLK(hash0, "hash0", NULL), | ||
| 433 | CLK(cryp0, "cryp0", NULL), | ||
| 434 | CLK(cryp1, "cryp1", NULL), | ||
| 435 | |||
| 436 | /* PRCMU level clock gating */ | ||
| 437 | |||
| 438 | /* Bank 0 */ | ||
| 439 | CLK(svaclk, "sva", NULL), | ||
| 440 | CLK(siaclk, "sia", NULL), | ||
| 441 | CLK(sgaclk, "sga", NULL), | ||
| 442 | CLK(slimclk, "slim", NULL), | ||
| 443 | CLK(lcdclk, "lcd", NULL), | ||
| 444 | CLK(bmlclk, "bml", NULL), | ||
| 445 | CLK(hsitxclk, "stm-hsi.0", NULL), | ||
| 446 | CLK(hsirxclk, "stm-hsi.1", NULL), | ||
| 447 | CLK(hdmiclk, "hdmi", NULL), | ||
| 448 | CLK(apeatclk, "apeat", NULL), | ||
| 449 | CLK(apetraceclk, "apetrace", NULL), | ||
| 450 | CLK(mcdeclk, "mcde", NULL), | ||
| 451 | CLK(ipi2clk, "ipi2", NULL), | ||
| 452 | CLK(dmaclk, "dma40.0", NULL), | ||
| 453 | CLK(b2r2clk, "b2r2", NULL), | ||
| 454 | CLK(tvclk, "tv", NULL), | ||
| 455 | |||
| 456 | /* Peripheral Cluster #1 */ | ||
| 457 | CLK(i2c4, "nmk-i2c.4", NULL), | ||
| 458 | CLK(spi3, "spi3", NULL), | ||
| 459 | CLK(msp1, "ux500-msp-i2s.1", NULL), | ||
| 460 | CLK(msp3, "ux500-msp-i2s.3", NULL), | ||
| 461 | |||
| 462 | /* Peripheral Cluster #2 */ | ||
| 463 | CLK(gpio1, "gpio.6", NULL), | ||
| 464 | CLK(gpio1, "gpio.7", NULL), | ||
| 465 | CLK(ssitx, "ssitx", NULL), | ||
| 466 | CLK(ssirx, "ssirx", NULL), | ||
| 467 | CLK(spi0, "spi0", NULL), | ||
| 468 | CLK(sdi3, "sdi3", NULL), | ||
| 469 | CLK(sdi1, "sdi1", NULL), | ||
| 470 | CLK(msp2, "ux500-msp-i2s.2", NULL), | ||
| 471 | CLK(sdi4, "sdi4", NULL), | ||
| 472 | CLK(pwl, "pwl", NULL), | ||
| 473 | CLK(spi1, "spi1", NULL), | ||
| 474 | CLK(spi2, "spi2", NULL), | ||
| 475 | CLK(i2c3, "nmk-i2c.3", NULL), | ||
| 476 | |||
| 477 | /* Peripheral Cluster #3 */ | ||
| 478 | CLK(ssp1, "ssp1", NULL), | ||
| 479 | CLK(ssp0, "ssp0", NULL), | ||
| 480 | |||
| 481 | /* Peripheral Cluster #5 */ | ||
| 482 | CLK(usb, "musb-ux500.0", "usb"), | ||
| 483 | |||
| 484 | /* Peripheral Cluster #6 */ | ||
| 485 | CLK(mtu1, "mtu1", NULL), | ||
| 486 | CLK(mtu0, "mtu0", NULL), | ||
| 487 | CLK(cfgreg, "cfgreg", NULL), | ||
| 488 | CLK(hash1, "hash1", NULL), | ||
| 489 | CLK(unipro, "unipro", NULL), | ||
| 490 | CLK(rng, "rng", NULL), | ||
| 491 | |||
| 492 | /* PRCMU level clock gating */ | ||
| 493 | |||
| 494 | /* Bank 0 */ | ||
| 495 | CLK(uniproclk, "uniproclk", NULL), | ||
| 496 | CLK(dsialtclk, "dsialt", NULL), | ||
| 497 | |||
| 498 | /* Bank 1 */ | ||
| 499 | CLK(rngclk, "rng", NULL), | ||
| 500 | CLK(uiccclk, "uicc", NULL), | ||
| 501 | }; | ||
| 502 | |||
| 503 | #ifdef CONFIG_DEBUG_FS | ||
| 504 | /* | ||
| 505 | * debugfs support to trace clock tree hierarchy and attributes with | ||
| 506 | * powerdebug | ||
| 507 | */ | ||
| 508 | static struct dentry *clk_debugfs_root; | ||
| 509 | |||
| 510 | void __init clk_debugfs_add_table(struct clk_lookup *cl, size_t num) | ||
| 511 | { | ||
| 512 | while (num--) { | ||
| 513 | /* Check that the clock has not been already registered */ | ||
| 514 | if (!(cl->clk->list.prev != cl->clk->list.next)) | ||
| 515 | list_add_tail(&cl->clk->list, &clk_list); | ||
| 516 | |||
| 517 | cl++; | ||
| 518 | } | ||
| 519 | } | ||
| 520 | |||
| 521 | static ssize_t usecount_dbg_read(struct file *file, char __user *buf, | ||
| 522 | size_t size, loff_t *off) | ||
| 523 | { | ||
| 524 | struct clk *clk = file->f_dentry->d_inode->i_private; | ||
| 525 | char cusecount[128]; | ||
| 526 | unsigned int len; | ||
| 527 | |||
| 528 | len = sprintf(cusecount, "%u\n", clk->enabled); | ||
| 529 | return simple_read_from_buffer(buf, size, off, cusecount, len); | ||
| 530 | } | ||
| 531 | |||
| 532 | static ssize_t rate_dbg_read(struct file *file, char __user *buf, | ||
| 533 | size_t size, loff_t *off) | ||
| 534 | { | ||
| 535 | struct clk *clk = file->f_dentry->d_inode->i_private; | ||
| 536 | char crate[128]; | ||
| 537 | unsigned int rate; | ||
| 538 | unsigned int len; | ||
| 539 | |||
| 540 | rate = clk_get_rate(clk); | ||
| 541 | len = sprintf(crate, "%u\n", rate); | ||
| 542 | return simple_read_from_buffer(buf, size, off, crate, len); | ||
| 543 | } | ||
| 544 | |||
| 545 | static const struct file_operations usecount_fops = { | ||
| 546 | .read = usecount_dbg_read, | ||
| 547 | }; | ||
| 548 | |||
| 549 | static const struct file_operations set_rate_fops = { | ||
| 550 | .read = rate_dbg_read, | ||
| 551 | }; | ||
| 552 | |||
| 553 | static struct dentry *clk_debugfs_register_dir(struct clk *c, | ||
| 554 | struct dentry *p_dentry) | ||
| 555 | { | ||
| 556 | struct dentry *d, *clk_d; | ||
| 557 | const char *p = c->name; | ||
| 558 | |||
| 559 | if (!p) | ||
| 560 | p = "BUG"; | ||
| 561 | |||
| 562 | clk_d = debugfs_create_dir(p, p_dentry); | ||
| 563 | if (!clk_d) | ||
| 564 | return NULL; | ||
| 565 | |||
| 566 | d = debugfs_create_file("usecount", S_IRUGO, | ||
| 567 | clk_d, c, &usecount_fops); | ||
| 568 | if (!d) | ||
| 569 | goto err_out; | ||
| 570 | d = debugfs_create_file("rate", S_IRUGO, | ||
| 571 | clk_d, c, &set_rate_fops); | ||
| 572 | if (!d) | ||
| 573 | goto err_out; | ||
| 574 | /* | ||
| 575 | * TODO : not currently available in ux500 | ||
| 576 | * d = debugfs_create_x32("flags", S_IRUGO, clk_d, (u32 *)&c->flags); | ||
| 577 | * if (!d) | ||
| 578 | * goto err_out; | ||
| 579 | */ | ||
| 580 | |||
| 581 | return clk_d; | ||
| 582 | |||
| 583 | err_out: | ||
| 584 | debugfs_remove_recursive(clk_d); | ||
| 585 | return NULL; | ||
| 586 | } | ||
| 587 | |||
| 588 | static int clk_debugfs_register_one(struct clk *c) | ||
| 589 | { | ||
| 590 | struct clk *pa = c->parent_periph; | ||
| 591 | struct clk *bpa = c->parent_cluster; | ||
| 592 | |||
| 593 | if (!(bpa && !pa)) { | ||
| 594 | c->dent = clk_debugfs_register_dir(c, | ||
| 595 | pa ? pa->dent : clk_debugfs_root); | ||
| 596 | if (!c->dent) | ||
| 597 | return -ENOMEM; | ||
| 598 | } | ||
| 599 | |||
| 600 | if (bpa) { | ||
| 601 | c->dent_bus = clk_debugfs_register_dir(c, | ||
| 602 | bpa->dent_bus ? bpa->dent_bus : bpa->dent); | ||
| 603 | if ((!c->dent_bus) && (c->dent)) { | ||
| 604 | debugfs_remove_recursive(c->dent); | ||
| 605 | c->dent = NULL; | ||
| 606 | return -ENOMEM; | ||
| 607 | } | ||
| 608 | } | ||
| 609 | return 0; | ||
| 610 | } | ||
| 611 | |||
| 612 | static int clk_debugfs_register(struct clk *c) | ||
| 613 | { | ||
| 614 | int err; | ||
| 615 | struct clk *pa = c->parent_periph; | ||
| 616 | struct clk *bpa = c->parent_cluster; | ||
| 617 | |||
| 618 | if (pa && (!pa->dent && !pa->dent_bus)) { | ||
| 619 | err = clk_debugfs_register(pa); | ||
| 620 | if (err) | ||
| 621 | return err; | ||
| 622 | } | ||
| 623 | |||
| 624 | if (bpa && (!bpa->dent && !bpa->dent_bus)) { | ||
| 625 | err = clk_debugfs_register(bpa); | ||
| 626 | if (err) | ||
| 627 | return err; | ||
| 628 | } | ||
| 629 | |||
| 630 | if ((!c->dent) && (!c->dent_bus)) { | ||
| 631 | err = clk_debugfs_register_one(c); | ||
| 632 | if (err) | ||
| 633 | return err; | ||
| 634 | } | ||
| 635 | return 0; | ||
| 636 | } | ||
| 637 | |||
| 638 | int __init clk_debugfs_init(void) | ||
| 639 | { | ||
| 640 | struct clk *c; | ||
| 641 | struct dentry *d; | ||
| 642 | int err; | ||
| 643 | |||
| 644 | d = debugfs_create_dir("clock", NULL); | ||
| 645 | if (!d) | ||
| 646 | return -ENOMEM; | ||
| 647 | clk_debugfs_root = d; | ||
| 648 | |||
| 649 | list_for_each_entry(c, &clk_list, list) { | ||
| 650 | err = clk_debugfs_register(c); | ||
| 651 | if (err) | ||
| 652 | goto err_out; | ||
| 653 | } | ||
| 654 | return 0; | ||
| 655 | err_out: | ||
| 656 | debugfs_remove_recursive(clk_debugfs_root); | ||
| 657 | return err; | ||
| 658 | } | ||
| 659 | |||
| 660 | #endif /* defined(CONFIG_DEBUG_FS) */ | ||
| 661 | |||
| 662 | unsigned long clk_smp_twd_rate = 500000000; | ||
| 663 | |||
| 664 | unsigned long clk_smp_twd_get_rate(struct clk *clk) | ||
| 665 | { | ||
| 666 | return clk_smp_twd_rate; | ||
| 667 | } | ||
| 668 | |||
| 669 | static struct clk clk_smp_twd = { | ||
| 670 | .get_rate = clk_smp_twd_get_rate, | ||
| 671 | .name = "smp_twd", | ||
| 672 | }; | ||
| 673 | |||
| 674 | static struct clk_lookup clk_smp_twd_lookup = { | ||
| 675 | .dev_id = "smp_twd", | ||
| 676 | .clk = &clk_smp_twd, | ||
| 677 | }; | ||
| 678 | |||
| 679 | #ifdef CONFIG_CPU_FREQ | ||
| 680 | |||
| 681 | static int clk_twd_cpufreq_transition(struct notifier_block *nb, | ||
| 682 | unsigned long state, void *data) | ||
| 683 | { | ||
| 684 | struct cpufreq_freqs *f = data; | ||
| 685 | |||
| 686 | if (state == CPUFREQ_PRECHANGE) { | ||
| 687 | /* Save frequency in simple Hz */ | ||
| 688 | clk_smp_twd_rate = (f->new * 1000) / 2; | ||
| 689 | } | ||
| 690 | |||
| 691 | return NOTIFY_OK; | ||
| 692 | } | ||
| 693 | |||
| 694 | static struct notifier_block clk_twd_cpufreq_nb = { | ||
| 695 | .notifier_call = clk_twd_cpufreq_transition, | ||
| 696 | }; | ||
| 697 | |||
| 698 | int clk_init_smp_twd_cpufreq(void) | ||
| 699 | { | ||
| 700 | return cpufreq_register_notifier(&clk_twd_cpufreq_nb, | ||
| 701 | CPUFREQ_TRANSITION_NOTIFIER); | ||
| 702 | } | ||
| 703 | |||
| 704 | #endif | ||
| 705 | |||
| 706 | int __init clk_init(void) | ||
| 707 | { | ||
| 708 | clkdev_add_table(u8500_clks, ARRAY_SIZE(u8500_clks)); | ||
| 709 | clkdev_add(&clk_smp_twd_lookup); | ||
| 710 | |||
| 711 | #ifdef CONFIG_DEBUG_FS | ||
| 712 | clk_debugfs_add_table(u8500_clks, ARRAY_SIZE(u8500_clks)); | ||
| 713 | #endif | ||
| 714 | return 0; | ||
| 715 | } | ||
diff --git a/arch/arm/mach-ux500/clock.h b/arch/arm/mach-ux500/clock.h deleted file mode 100644 index 65d27a13f46d..000000000000 --- a/arch/arm/mach-ux500/clock.h +++ /dev/null | |||
| @@ -1,164 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 ST-Ericsson | ||
| 3 | * Copyright (C) 2009 STMicroelectronics | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License version 2 as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | */ | ||
| 9 | |||
| 10 | /** | ||
| 11 | * struct clkops - ux500 clock operations | ||
| 12 | * @enable: function to enable the clock | ||
| 13 | * @disable: function to disable the clock | ||
| 14 | * @get_rate: function to get the current clock rate | ||
| 15 | * | ||
| 16 | * This structure contains function pointers to functions that will be used to | ||
| 17 | * control the clock. All of these functions are optional. If get_rate is | ||
| 18 | * NULL, the rate in the struct clk will be used. | ||
| 19 | */ | ||
| 20 | struct clkops { | ||
| 21 | void (*enable) (struct clk *); | ||
| 22 | void (*disable) (struct clk *); | ||
| 23 | unsigned long (*get_rate) (struct clk *); | ||
| 24 | int (*set_parent)(struct clk *, struct clk *); | ||
| 25 | }; | ||
| 26 | |||
| 27 | /** | ||
| 28 | * struct clk - ux500 clock structure | ||
| 29 | * @ops: pointer to clkops struct used to control this clock | ||
| 30 | * @name: name, for debugging | ||
| 31 | * @enabled: refcount. positive if enabled, zero if disabled | ||
| 32 | * @get_rate: custom callback for getting the clock rate | ||
| 33 | * @data: custom per-clock data for example for the get_rate | ||
| 34 | * callback | ||
| 35 | * @rate: fixed rate for clocks which don't implement | ||
| 36 | * ops->getrate | ||
| 37 | * @prcmu_cg_off: address offset of the combined enable/disable register | ||
| 38 | * (used on u8500v1) | ||
| 39 | * @prcmu_cg_bit: bit in the combined enable/disable register (used on | ||
| 40 | * u8500v1) | ||
| 41 | * @prcmu_cg_mgt: address of the enable/disable register (used on | ||
| 42 | * u8500ed) | ||
| 43 | * @cluster: peripheral cluster number | ||
| 44 | * @prcc_bus: bit for the bus clock in the peripheral's CLKRST | ||
| 45 | * @prcc_kernel: bit for the kernel clock in the peripheral's CLKRST. | ||
| 46 | * -1 if no kernel clock exists. | ||
| 47 | * @parent_cluster: pointer to parent's cluster clk struct | ||
| 48 | * @parent_periph: pointer to parent's peripheral clk struct | ||
| 49 | * | ||
| 50 | * Peripherals are organised into clusters, and each cluster has an associated | ||
| 51 | * bus clock. Some peripherals also have a parent peripheral clock. | ||
| 52 | * | ||
| 53 | * In order to enable a clock for a peripheral, we need to enable: | ||
| 54 | * (1) the parent cluster (bus) clock at the PRCMU level | ||
| 55 | * (2) the parent peripheral clock (if any) at the PRCMU level | ||
| 56 | * (3) the peripheral's bus & kernel clock at the PRCC level | ||
| 57 | * | ||
| 58 | * (1) and (2) are handled by defining clk structs (DEFINE_PRCMU_CLK) for each | ||
| 59 | * of the cluster and peripheral clocks, and hooking these as the parents of | ||
| 60 | * the individual peripheral clocks. | ||
| 61 | * | ||
| 62 | * (3) is handled by specifying the bits in the PRCC control registers required | ||
| 63 | * to enable these clocks and modifying them in the ->enable and | ||
| 64 | * ->disable callbacks of the peripheral clocks (DEFINE_PRCC_CLK). | ||
| 65 | * | ||
| 66 | * This structure describes both the PRCMU-level clocks and PRCC-level clocks. | ||
| 67 | * The prcmu_* fields are only used for the PRCMU clocks, and the cluster, | ||
| 68 | * prcc, and parent pointers are only used for the PRCC-level clocks. | ||
| 69 | */ | ||
| 70 | struct clk { | ||
| 71 | const struct clkops *ops; | ||
| 72 | const char *name; | ||
| 73 | unsigned int enabled; | ||
| 74 | unsigned long (*get_rate)(struct clk *); | ||
| 75 | void *data; | ||
| 76 | |||
| 77 | unsigned long rate; | ||
| 78 | struct list_head list; | ||
| 79 | |||
| 80 | /* These three are only for PRCMU clks */ | ||
| 81 | |||
| 82 | unsigned int prcmu_cg_off; | ||
| 83 | unsigned int prcmu_cg_bit; | ||
| 84 | unsigned int prcmu_cg_mgt; | ||
| 85 | |||
| 86 | /* The rest are only for PRCC clks */ | ||
| 87 | |||
| 88 | int cluster; | ||
| 89 | unsigned int prcc_bus; | ||
| 90 | unsigned int prcc_kernel; | ||
| 91 | |||
| 92 | struct clk *parent_cluster; | ||
| 93 | struct clk *parent_periph; | ||
| 94 | #if defined(CONFIG_DEBUG_FS) | ||
| 95 | struct dentry *dent; /* For visible tree hierarchy */ | ||
| 96 | struct dentry *dent_bus; /* For visible tree hierarchy */ | ||
| 97 | #endif | ||
| 98 | }; | ||
| 99 | |||
| 100 | #define DEFINE_PRCMU_CLK(_name, _cg_off, _cg_bit, _reg) \ | ||
| 101 | struct clk clk_##_name = { \ | ||
| 102 | .name = #_name, \ | ||
| 103 | .ops = &clk_prcmu_ops, \ | ||
| 104 | .prcmu_cg_off = _cg_off, \ | ||
| 105 | .prcmu_cg_bit = _cg_bit, \ | ||
| 106 | .prcmu_cg_mgt = PRCM_##_reg##_MGT \ | ||
| 107 | } | ||
| 108 | |||
| 109 | #define DEFINE_PRCMU_CLK_RATE(_name, _cg_off, _cg_bit, _reg, _rate) \ | ||
| 110 | struct clk clk_##_name = { \ | ||
| 111 | .name = #_name, \ | ||
| 112 | .ops = &clk_prcmu_ops, \ | ||
| 113 | .prcmu_cg_off = _cg_off, \ | ||
| 114 | .prcmu_cg_bit = _cg_bit, \ | ||
| 115 | .rate = _rate, \ | ||
| 116 | .prcmu_cg_mgt = PRCM_##_reg##_MGT \ | ||
| 117 | } | ||
| 118 | |||
| 119 | #define DEFINE_PRCC_CLK(_pclust, _name, _bus_en, _kernel_en, _kernclk) \ | ||
| 120 | struct clk clk_##_name = { \ | ||
| 121 | .name = #_name, \ | ||
| 122 | .ops = &clk_prcc_ops, \ | ||
| 123 | .cluster = _pclust, \ | ||
| 124 | .prcc_bus = _bus_en, \ | ||
| 125 | .prcc_kernel = _kernel_en, \ | ||
| 126 | .parent_cluster = &clk_per##_pclust##clk, \ | ||
| 127 | .parent_periph = _kernclk \ | ||
| 128 | } | ||
| 129 | |||
| 130 | #define DEFINE_PRCC_CLK_CUSTOM(_pclust, _name, _bus_en, _kernel_en, _kernclk, _callback, _data) \ | ||
| 131 | struct clk clk_##_name = { \ | ||
| 132 | .name = #_name, \ | ||
| 133 | .ops = &clk_prcc_ops, \ | ||
| 134 | .cluster = _pclust, \ | ||
| 135 | .prcc_bus = _bus_en, \ | ||
| 136 | .prcc_kernel = _kernel_en, \ | ||
| 137 | .parent_cluster = &clk_per##_pclust##clk, \ | ||
| 138 | .parent_periph = _kernclk, \ | ||
| 139 | .get_rate = _callback, \ | ||
| 140 | .data = (void *) _data \ | ||
| 141 | } | ||
| 142 | |||
| 143 | |||
| 144 | #define CLK(_clk, _devname, _conname) \ | ||
| 145 | { \ | ||
| 146 | .clk = &clk_##_clk, \ | ||
| 147 | .dev_id = _devname, \ | ||
| 148 | .con_id = _conname, \ | ||
| 149 | } | ||
| 150 | |||
| 151 | int __init clk_db8500_ed_fixup(void); | ||
| 152 | int __init clk_init(void); | ||
| 153 | |||
| 154 | #ifdef CONFIG_DEBUG_FS | ||
| 155 | int clk_debugfs_init(void); | ||
| 156 | #else | ||
| 157 | static inline int clk_debugfs_init(void) { return 0; } | ||
| 158 | #endif | ||
| 159 | |||
| 160 | #ifdef CONFIG_CPU_FREQ | ||
| 161 | int clk_init_smp_twd_cpufreq(void); | ||
| 162 | #else | ||
| 163 | static inline int clk_init_smp_twd_cpufreq(void) { return 0; } | ||
| 164 | #endif | ||
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index e2360e7c770d..17a78ec516ff 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c | |||
| @@ -8,7 +8,6 @@ | |||
| 8 | 8 | ||
| 9 | #include <linux/platform_device.h> | 9 | #include <linux/platform_device.h> |
| 10 | #include <linux/io.h> | 10 | #include <linux/io.h> |
| 11 | #include <linux/clk.h> | ||
| 12 | #include <linux/mfd/db8500-prcmu.h> | 11 | #include <linux/mfd/db8500-prcmu.h> |
| 13 | #include <linux/clksrc-dbx500-prcmu.h> | 12 | #include <linux/clksrc-dbx500-prcmu.h> |
| 14 | #include <linux/sys_soc.h> | 13 | #include <linux/sys_soc.h> |
| @@ -17,6 +16,7 @@ | |||
| 17 | #include <linux/stat.h> | 16 | #include <linux/stat.h> |
| 18 | #include <linux/of.h> | 17 | #include <linux/of.h> |
| 19 | #include <linux/of_irq.h> | 18 | #include <linux/of_irq.h> |
| 19 | #include <linux/platform_data/clk-ux500.h> | ||
| 20 | 20 | ||
| 21 | #include <asm/hardware/gic.h> | 21 | #include <asm/hardware/gic.h> |
| 22 | #include <asm/mach/map.h> | 22 | #include <asm/mach/map.h> |
| @@ -25,8 +25,6 @@ | |||
| 25 | #include <mach/setup.h> | 25 | #include <mach/setup.h> |
| 26 | #include <mach/devices.h> | 26 | #include <mach/devices.h> |
| 27 | 27 | ||
| 28 | #include "clock.h" | ||
| 29 | |||
| 30 | void __iomem *_PRCMU_BASE; | 28 | void __iomem *_PRCMU_BASE; |
| 31 | 29 | ||
| 32 | /* | 30 | /* |
| @@ -70,13 +68,17 @@ void __init ux500_init_irq(void) | |||
| 70 | */ | 68 | */ |
| 71 | if (cpu_is_u8500_family()) | 69 | if (cpu_is_u8500_family()) |
| 72 | db8500_prcmu_early_init(); | 70 | db8500_prcmu_early_init(); |
| 73 | clk_init(); | 71 | |
| 72 | if (cpu_is_u8500_family()) | ||
| 73 | u8500_clk_init(); | ||
| 74 | else if (cpu_is_u9540()) | ||
| 75 | u9540_clk_init(); | ||
| 76 | else if (cpu_is_u8540()) | ||
| 77 | u8540_clk_init(); | ||
| 74 | } | 78 | } |
| 75 | 79 | ||
| 76 | void __init ux500_init_late(void) | 80 | void __init ux500_init_late(void) |
| 77 | { | 81 | { |
| 78 | clk_debugfs_init(); | ||
| 79 | clk_init_smp_twd_cpufreq(); | ||
| 80 | } | 82 | } |
| 81 | 83 | ||
| 82 | static const char * __init ux500_get_machine(void) | 84 | static const char * __init ux500_get_machine(void) |
diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c index 23a7643e9a87..1be0f4e5e6eb 100644 --- a/arch/arm/mm/cache-tauros2.c +++ b/arch/arm/mm/cache-tauros2.c | |||
| @@ -15,8 +15,11 @@ | |||
| 15 | */ | 15 | */ |
| 16 | 16 | ||
| 17 | #include <linux/init.h> | 17 | #include <linux/init.h> |
| 18 | #include <linux/of.h> | ||
| 19 | #include <linux/of_address.h> | ||
| 18 | #include <asm/cacheflush.h> | 20 | #include <asm/cacheflush.h> |
| 19 | #include <asm/cp15.h> | 21 | #include <asm/cp15.h> |
| 22 | #include <asm/cputype.h> | ||
| 20 | #include <asm/hardware/cache-tauros2.h> | 23 | #include <asm/hardware/cache-tauros2.h> |
| 21 | 24 | ||
| 22 | 25 | ||
| @@ -144,25 +147,8 @@ static inline void __init write_extra_features(u32 u) | |||
| 144 | __asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u)); | 147 | __asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u)); |
| 145 | } | 148 | } |
| 146 | 149 | ||
| 147 | static void __init disable_l2_prefetch(void) | ||
| 148 | { | ||
| 149 | u32 u; | ||
| 150 | |||
| 151 | /* | ||
| 152 | * Read the CPU Extra Features register and verify that the | ||
| 153 | * Disable L2 Prefetch bit is set. | ||
| 154 | */ | ||
| 155 | u = read_extra_features(); | ||
| 156 | if (!(u & 0x01000000)) { | ||
| 157 | printk(KERN_INFO "Tauros2: Disabling L2 prefetch.\n"); | ||
| 158 | write_extra_features(u | 0x01000000); | ||
| 159 | } | ||
| 160 | } | ||
| 161 | |||
| 162 | static inline int __init cpuid_scheme(void) | 150 | static inline int __init cpuid_scheme(void) |
| 163 | { | 151 | { |
| 164 | extern int processor_id; | ||
| 165 | |||
| 166 | return !!((processor_id & 0x000f0000) == 0x000f0000); | 152 | return !!((processor_id & 0x000f0000) == 0x000f0000); |
| 167 | } | 153 | } |
| 168 | 154 | ||
| @@ -189,12 +175,36 @@ static inline void __init write_actlr(u32 actlr) | |||
| 189 | __asm__("mcr p15, 0, %0, c1, c0, 1\n" : : "r" (actlr)); | 175 | __asm__("mcr p15, 0, %0, c1, c0, 1\n" : : "r" (actlr)); |
| 190 | } | 176 | } |
| 191 | 177 | ||
| 192 | void __init tauros2_init(void) | 178 | static void enable_extra_feature(unsigned int features) |
| 179 | { | ||
| 180 | u32 u; | ||
| 181 | |||
| 182 | u = read_extra_features(); | ||
| 183 | |||
| 184 | if (features & CACHE_TAUROS2_PREFETCH_ON) | ||
| 185 | u &= ~0x01000000; | ||
| 186 | else | ||
| 187 | u |= 0x01000000; | ||
| 188 | printk(KERN_INFO "Tauros2: %s L2 prefetch.\n", | ||
| 189 | (features & CACHE_TAUROS2_PREFETCH_ON) | ||
| 190 | ? "Enabling" : "Disabling"); | ||
| 191 | |||
| 192 | if (features & CACHE_TAUROS2_LINEFILL_BURST8) | ||
| 193 | u |= 0x00100000; | ||
| 194 | else | ||
| 195 | u &= ~0x00100000; | ||
| 196 | printk(KERN_INFO "Tauros2: %s line fill burt8.\n", | ||
| 197 | (features & CACHE_TAUROS2_LINEFILL_BURST8) | ||
| 198 | ? "Enabling" : "Disabling"); | ||
| 199 | |||
| 200 | write_extra_features(u); | ||
| 201 | } | ||
| 202 | |||
| 203 | static void __init tauros2_internal_init(unsigned int features) | ||
| 193 | { | 204 | { |
| 194 | extern int processor_id; | 205 | char *mode = NULL; |
| 195 | char *mode; | ||
| 196 | 206 | ||
| 197 | disable_l2_prefetch(); | 207 | enable_extra_feature(features); |
| 198 | 208 | ||
| 199 | #ifdef CONFIG_CPU_32v5 | 209 | #ifdef CONFIG_CPU_32v5 |
| 200 | if ((processor_id & 0xff0f0000) == 0x56050000) { | 210 | if ((processor_id & 0xff0f0000) == 0x56050000) { |
| @@ -286,3 +296,34 @@ void __init tauros2_init(void) | |||
| 286 | printk(KERN_INFO "Tauros2: L2 cache support initialised " | 296 | printk(KERN_INFO "Tauros2: L2 cache support initialised " |
| 287 | "in %s mode.\n", mode); | 297 | "in %s mode.\n", mode); |
| 288 | } | 298 | } |
| 299 | |||
| 300 | #ifdef CONFIG_OF | ||
| 301 | static const struct of_device_id tauros2_ids[] __initconst = { | ||
| 302 | { .compatible = "marvell,tauros2-cache"}, | ||
| 303 | {} | ||
| 304 | }; | ||
| 305 | #endif | ||
| 306 | |||
| 307 | void __init tauros2_init(unsigned int features) | ||
| 308 | { | ||
| 309 | #ifdef CONFIG_OF | ||
| 310 | struct device_node *node; | ||
| 311 | int ret; | ||
| 312 | unsigned int f; | ||
| 313 | |||
| 314 | node = of_find_matching_node(NULL, tauros2_ids); | ||
| 315 | if (!node) { | ||
| 316 | pr_info("Not found marvell,tauros2-cache, disable it\n"); | ||
| 317 | return; | ||
| 318 | } | ||
| 319 | |||
| 320 | ret = of_property_read_u32(node, "marvell,tauros2-cache-features", &f); | ||
| 321 | if (ret) { | ||
| 322 | pr_info("Not found marvell,tauros-cache-features property, " | ||
| 323 | "disable extra features\n"); | ||
| 324 | features = 0; | ||
| 325 | } else | ||
| 326 | features = f; | ||
| 327 | #endif | ||
| 328 | tauros2_internal_init(features); | ||
| 329 | } | ||
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 7128e9710417..28ba09f4ebb9 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h | |||
| @@ -52,7 +52,6 @@ extern void imx31_soc_init(void); | |||
| 52 | extern void imx35_soc_init(void); | 52 | extern void imx35_soc_init(void); |
| 53 | extern void imx50_soc_init(void); | 53 | extern void imx50_soc_init(void); |
| 54 | extern void imx51_soc_init(void); | 54 | extern void imx51_soc_init(void); |
| 55 | extern void imx53_soc_init(void); | ||
| 56 | extern void imx51_init_late(void); | 55 | extern void imx51_init_late(void); |
| 57 | extern void imx53_init_late(void); | 56 | extern void imx53_init_late(void); |
| 58 | extern void epit_timer_init(void __iomem *base, int irq); | 57 | extern void epit_timer_init(void __iomem *base, int irq); |
| @@ -137,11 +136,6 @@ extern void imx_src_prepare_restart(void); | |||
| 137 | extern void imx_gpc_init(void); | 136 | extern void imx_gpc_init(void); |
| 138 | extern void imx_gpc_pre_suspend(void); | 137 | extern void imx_gpc_pre_suspend(void); |
| 139 | extern void imx_gpc_post_resume(void); | 138 | extern void imx_gpc_post_resume(void); |
| 140 | extern void imx51_babbage_common_init(void); | ||
| 141 | extern void imx53_ard_common_init(void); | ||
| 142 | extern void imx53_evk_common_init(void); | ||
| 143 | extern void imx53_qsb_common_init(void); | ||
| 144 | extern void imx53_smd_common_init(void); | ||
| 145 | extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); | 139 | extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); |
| 146 | extern void imx6q_clock_map_io(void); | 140 | extern void imx6q_clock_map_io(void); |
| 147 | 141 | ||
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h deleted file mode 100644 index 9761e003bde2..000000000000 --- a/arch/arm/plat-mxc/include/mach/iomux-mx53.h +++ /dev/null | |||
| @@ -1,1219 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License along | ||
| 15 | * with this program; if not, write to the Free Software Foundation, Inc.. | ||
| 16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef __MACH_IOMUX_MX53_H__ | ||
| 20 | #define __MACH_IOMUX_MX53_H__ | ||
| 21 | |||
| 22 | #include <mach/iomux-v3.h> | ||
| 23 | |||
| 24 | /* These 2 defines are for pins that may not have a mux register, but could | ||
| 25 | * have a pad setting register, and vice-versa. */ | ||
| 26 | #define __NA_ 0x00 | ||
| 27 | |||
| 28 | #define MX53_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ | ||
| 29 | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS) | ||
| 30 | #define MX53_SDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ | ||
| 31 | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \ | ||
| 32 | PAD_CTL_SRE_FAST) | ||
| 33 | |||
| 34 | |||
| 35 | #define MX53_PAD_GPIO_19__KPP_COL_5 IOMUX_PAD(0x348, 0x020, 0, 0x840, 0, NO_PAD_CTRL) | ||
| 36 | #define MX53_PAD_GPIO_19__GPIO4_5 IOMUX_PAD(0x348, 0x020, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 37 | #define MX53_PAD_GPIO_19__CCM_CLKO IOMUX_PAD(0x348, 0x020, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 38 | #define MX53_PAD_GPIO_19__SPDIF_OUT1 IOMUX_PAD(0x348, 0x020, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 39 | #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 IOMUX_PAD(0x348, 0x020, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 40 | #define MX53_PAD_GPIO_19__ECSPI1_RDY IOMUX_PAD(0x348, 0x020, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 41 | #define MX53_PAD_GPIO_19__FEC_TDATA_3 IOMUX_PAD(0x348, 0x020, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 42 | #define MX53_PAD_GPIO_19__SRC_INT_BOOT IOMUX_PAD(0x348, 0x020, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 43 | #define MX53_PAD_KEY_COL0__KPP_COL_0 IOMUX_PAD(0x34C, 0x024, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 44 | #define MX53_PAD_KEY_COL0__GPIO4_6 IOMUX_PAD(0x34C, 0x024, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 45 | #define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC IOMUX_PAD(0x34C, 0x024, 2, 0x758, 0, NO_PAD_CTRL) | ||
| 46 | #define MX53_PAD_KEY_COL0__UART4_TXD_MUX IOMUX_PAD(0x34C, 0x024, 4, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 47 | #define MX53_PAD_KEY_COL0__ECSPI1_SCLK IOMUX_PAD(0x34C, 0x024, 5, 0x79C, 0, NO_PAD_CTRL) | ||
| 48 | #define MX53_PAD_KEY_COL0__FEC_RDATA_3 IOMUX_PAD(0x34C, 0x024, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 49 | #define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST IOMUX_PAD(0x34C, 0x024, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 50 | #define MX53_PAD_KEY_ROW0__KPP_ROW_0 IOMUX_PAD(0x350, 0x028, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 51 | #define MX53_PAD_KEY_ROW0__GPIO4_7 IOMUX_PAD(0x350, 0x028, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 52 | #define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD IOMUX_PAD(0x350, 0x028, 2, 0x74C, 0, NO_PAD_CTRL) | ||
| 53 | #define MX53_PAD_KEY_ROW0__UART4_RXD_MUX IOMUX_PAD(0x350, 0x028, 4, 0x890, 1, MX53_UART_PAD_CTRL) | ||
| 54 | #define MX53_PAD_KEY_ROW0__ECSPI1_MOSI IOMUX_PAD(0x350, 0x028, 5, 0x7A4, 0, NO_PAD_CTRL) | ||
| 55 | #define MX53_PAD_KEY_ROW0__FEC_TX_ER IOMUX_PAD(0x350, 0x028, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 56 | #define MX53_PAD_KEY_COL1__KPP_COL_1 IOMUX_PAD(0x354, 0x02C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 57 | #define MX53_PAD_KEY_COL1__GPIO4_8 IOMUX_PAD(0x354, 0x02C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 58 | #define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS IOMUX_PAD(0x354, 0x02C, 2, 0x75C, 0, NO_PAD_CTRL) | ||
| 59 | #define MX53_PAD_KEY_COL1__UART5_TXD_MUX IOMUX_PAD(0x354, 0x02C, 4, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 60 | #define MX53_PAD_KEY_COL1__ECSPI1_MISO IOMUX_PAD(0x354, 0x02C, 5, 0x7A0, 0, NO_PAD_CTRL) | ||
| 61 | #define MX53_PAD_KEY_COL1__FEC_RX_CLK IOMUX_PAD(0x354, 0x02C, 6, 0x808, 0, NO_PAD_CTRL) | ||
| 62 | #define MX53_PAD_KEY_COL1__USBPHY1_TXREADY IOMUX_PAD(0x354, 0x02C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 63 | #define MX53_PAD_KEY_ROW1__KPP_ROW_1 IOMUX_PAD(0x358, 0x030, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 64 | #define MX53_PAD_KEY_ROW1__GPIO4_9 IOMUX_PAD(0x358, 0x030, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 65 | #define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD IOMUX_PAD(0x358, 0x030, 2, 0x748, 0, NO_PAD_CTRL) | ||
| 66 | #define MX53_PAD_KEY_ROW1__UART5_RXD_MUX IOMUX_PAD(0x358, 0x030, 4, 0x898, 1, MX53_UART_PAD_CTRL) | ||
| 67 | #define MX53_PAD_KEY_ROW1__ECSPI1_SS0 IOMUX_PAD(0x358, 0x030, 5, 0x7A8, 0, NO_PAD_CTRL) | ||
| 68 | #define MX53_PAD_KEY_ROW1__FEC_COL IOMUX_PAD(0x358, 0x030, 6, 0x800, 0, NO_PAD_CTRL) | ||
| 69 | #define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID IOMUX_PAD(0x358, 0x030, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 70 | #define MX53_PAD_KEY_COL2__KPP_COL_2 IOMUX_PAD(0x35C, 0x034, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 71 | #define MX53_PAD_KEY_COL2__GPIO4_10 IOMUX_PAD(0x35C, 0x034, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 72 | #define MX53_PAD_KEY_COL2__CAN1_TXCAN IOMUX_PAD(0x35C, 0x034, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 73 | #define MX53_PAD_KEY_COL2__FEC_MDIO IOMUX_PAD(0x35C, 0x034, 4, 0x804, 0, NO_PAD_CTRL) | ||
| 74 | #define MX53_PAD_KEY_COL2__ECSPI1_SS1 IOMUX_PAD(0x35C, 0x034, 5, 0x7AC, 0, NO_PAD_CTRL) | ||
| 75 | #define MX53_PAD_KEY_COL2__FEC_RDATA_2 IOMUX_PAD(0x35C, 0x034, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 76 | #define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE IOMUX_PAD(0x35C, 0x034, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 77 | #define MX53_PAD_KEY_ROW2__KPP_ROW_2 IOMUX_PAD(0x360, 0x038, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 78 | #define MX53_PAD_KEY_ROW2__GPIO4_11 IOMUX_PAD(0x360, 0x038, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 79 | #define MX53_PAD_KEY_ROW2__CAN1_RXCAN IOMUX_PAD(0x360, 0x038, 2, 0x760, 0, NO_PAD_CTRL) | ||
| 80 | #define MX53_PAD_KEY_ROW2__FEC_MDC IOMUX_PAD(0x360, 0x038, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 81 | #define MX53_PAD_KEY_ROW2__ECSPI1_SS2 IOMUX_PAD(0x360, 0x038, 5, 0x7B0, 0, NO_PAD_CTRL) | ||
| 82 | #define MX53_PAD_KEY_ROW2__FEC_TDATA_2 IOMUX_PAD(0x360, 0x038, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 83 | #define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR IOMUX_PAD(0x360, 0x038, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 84 | #define MX53_PAD_KEY_COL3__KPP_COL_3 IOMUX_PAD(0x364, 0x03C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 85 | #define MX53_PAD_KEY_COL3__GPIO4_12 IOMUX_PAD(0x364, 0x03C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 86 | #define MX53_PAD_KEY_COL3__USBOH3_H2_DP IOMUX_PAD(0x364, 0x03C, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 87 | #define MX53_PAD_KEY_COL3__SPDIF_IN1 IOMUX_PAD(0x364, 0x03C, 3, 0x870, 0, NO_PAD_CTRL) | ||
| 88 | #define MX53_PAD_KEY_COL3__I2C2_SCL IOMUX_PAD(0x364, 0x03C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, NO_PAD_CTRL) | ||
| 89 | #define MX53_PAD_KEY_COL3__ECSPI1_SS3 IOMUX_PAD(0x364, 0x03C, 5, 0x7B4, 0, NO_PAD_CTRL) | ||
| 90 | #define MX53_PAD_KEY_COL3__FEC_CRS IOMUX_PAD(0x364, 0x03C, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 91 | #define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK IOMUX_PAD(0x364, 0x03C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 92 | #define MX53_PAD_KEY_ROW3__KPP_ROW_3 IOMUX_PAD(0x368, 0x040, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 93 | #define MX53_PAD_KEY_ROW3__GPIO4_13 IOMUX_PAD(0x368, 0x040, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 94 | #define MX53_PAD_KEY_ROW3__USBOH3_H2_DM IOMUX_PAD(0x368, 0x040, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 95 | #define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK IOMUX_PAD(0x368, 0x040, 3, 0x768, 0, NO_PAD_CTRL) | ||
| 96 | #define MX53_PAD_KEY_ROW3__I2C2_SDA IOMUX_PAD(0x368, 0x040, 4 | IOMUX_CONFIG_SION, 0x820, 0, NO_PAD_CTRL) | ||
| 97 | #define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT IOMUX_PAD(0x368, 0x040, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 98 | #define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP IOMUX_PAD(0x368, 0x040, 6, 0x77C, 0, NO_PAD_CTRL) | ||
| 99 | #define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 IOMUX_PAD(0x368, 0x040, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 100 | #define MX53_PAD_KEY_COL4__KPP_COL_4 IOMUX_PAD(0x36C, 0x044, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 101 | #define MX53_PAD_KEY_COL4__GPIO4_14 IOMUX_PAD(0x36C, 0x044, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 102 | #define MX53_PAD_KEY_COL4__CAN2_TXCAN IOMUX_PAD(0x36C, 0x044, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 103 | #define MX53_PAD_KEY_COL4__IPU_SISG_4 IOMUX_PAD(0x36C, 0x044, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 104 | #define MX53_PAD_KEY_COL4__UART5_RTS IOMUX_PAD(0x36C, 0x044, 4, 0x894, 0, MX53_UART_PAD_CTRL) | ||
| 105 | #define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC IOMUX_PAD(0x36C, 0x044, 5, 0x89C, 0, NO_PAD_CTRL) | ||
| 106 | #define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 IOMUX_PAD(0x36C, 0x044, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 107 | #define MX53_PAD_KEY_ROW4__KPP_ROW_4 IOMUX_PAD(0x370, 0x048, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 108 | #define MX53_PAD_KEY_ROW4__GPIO4_15 IOMUX_PAD(0x370, 0x048, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 109 | #define MX53_PAD_KEY_ROW4__CAN2_RXCAN IOMUX_PAD(0x370, 0x048, 2, 0x764, 0, NO_PAD_CTRL) | ||
| 110 | #define MX53_PAD_KEY_ROW4__IPU_SISG_5 IOMUX_PAD(0x370, 0x048, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 111 | #define MX53_PAD_KEY_ROW4__UART5_CTS IOMUX_PAD(0x370, 0x048, 4, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 112 | #define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR IOMUX_PAD(0x370, 0x048, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 113 | #define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID IOMUX_PAD(0x370, 0x048, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 114 | #define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK IOMUX_PAD(0x378, 0x04C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 115 | #define MX53_PAD_DI0_DISP_CLK__GPIO4_16 IOMUX_PAD(0x378, 0x04C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 116 | #define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR IOMUX_PAD(0x378, 0x04C, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 117 | #define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 IOMUX_PAD(0x378, 0x04C, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 118 | #define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 IOMUX_PAD(0x378, 0x04C, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 119 | #define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID IOMUX_PAD(0x378, 0x04C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 120 | #define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 IOMUX_PAD(0x37C, 0x050, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 121 | #define MX53_PAD_DI0_PIN15__GPIO4_17 IOMUX_PAD(0x37C, 0x050, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 122 | #define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC IOMUX_PAD(0x37C, 0x050, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 123 | #define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 IOMUX_PAD(0x37C, 0x050, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 124 | #define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 IOMUX_PAD(0x37C, 0x050, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 125 | #define MX53_PAD_DI0_PIN15__USBPHY1_BVALID IOMUX_PAD(0x37C, 0x050, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 126 | #define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 IOMUX_PAD(0x380, 0x054, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 127 | #define MX53_PAD_DI0_PIN2__GPIO4_18 IOMUX_PAD(0x380, 0x054, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 128 | #define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD IOMUX_PAD(0x380, 0x054, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 129 | #define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 IOMUX_PAD(0x380, 0x054, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 130 | #define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 IOMUX_PAD(0x380, 0x054, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 131 | #define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION IOMUX_PAD(0x380, 0x054, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 132 | #define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 IOMUX_PAD(0x384, 0x058, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 133 | #define MX53_PAD_DI0_PIN3__GPIO4_19 IOMUX_PAD(0x384, 0x058, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 134 | #define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS IOMUX_PAD(0x384, 0x058, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 135 | #define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 IOMUX_PAD(0x384, 0x058, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 136 | #define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 IOMUX_PAD(0x384, 0x058, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 137 | #define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG IOMUX_PAD(0x384, 0x058, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 138 | #define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 IOMUX_PAD(0x388, 0x05C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 139 | #define MX53_PAD_DI0_PIN4__GPIO4_20 IOMUX_PAD(0x388, 0x05C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 140 | #define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD IOMUX_PAD(0x388, 0x05C, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 141 | #define MX53_PAD_DI0_PIN4__ESDHC1_WP IOMUX_PAD(0x388, 0x05C, 3, 0x7FC, 0, NO_PAD_CTRL) | ||
| 142 | #define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD IOMUX_PAD(0x388, 0x05C, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 143 | #define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 IOMUX_PAD(0x388, 0x05C, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 144 | #define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT IOMUX_PAD(0x388, 0x05C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 145 | #define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 IOMUX_PAD(0x38C, 0x060, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 146 | #define MX53_PAD_DISP0_DAT0__GPIO4_21 IOMUX_PAD(0x38C, 0x060, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 147 | #define MX53_PAD_DISP0_DAT0__CSPI_SCLK IOMUX_PAD(0x38C, 0x060, 2, 0x780, 0, NO_PAD_CTRL) | ||
| 148 | #define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 IOMUX_PAD(0x38C, 0x060, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 149 | #define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN IOMUX_PAD(0x38C, 0x060, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 150 | #define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 IOMUX_PAD(0x38C, 0x060, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 151 | #define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY IOMUX_PAD(0x38C, 0x060, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 152 | #define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 IOMUX_PAD(0x390, 0x064, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 153 | #define MX53_PAD_DISP0_DAT1__GPIO4_22 IOMUX_PAD(0x390, 0x064, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 154 | #define MX53_PAD_DISP0_DAT1__CSPI_MOSI IOMUX_PAD(0x390, 0x064, 2, 0x788, 0, NO_PAD_CTRL) | ||
| 155 | #define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 IOMUX_PAD(0x390, 0x064, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 156 | #define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL \ | ||
| 157 | IOMUX_PAD(0x390, 0x064, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 158 | #define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 IOMUX_PAD(0x390, 0x064, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 159 | #define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID IOMUX_PAD(0x390, 0x064, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 160 | #define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 IOMUX_PAD(0x394, 0x068, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 161 | #define MX53_PAD_DISP0_DAT2__GPIO4_23 IOMUX_PAD(0x394, 0x068, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 162 | #define MX53_PAD_DISP0_DAT2__CSPI_MISO IOMUX_PAD(0x394, 0x068, 2, 0x784, 0, NO_PAD_CTRL) | ||
| 163 | #define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 IOMUX_PAD(0x394, 0x068, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 164 | #define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE IOMUX_PAD(0x394, 0x068, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 165 | #define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 IOMUX_PAD(0x394, 0x068, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 166 | #define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE IOMUX_PAD(0x394, 0x068, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 167 | #define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 IOMUX_PAD(0x398, 0x06C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 168 | #define MX53_PAD_DISP0_DAT3__GPIO4_24 IOMUX_PAD(0x398, 0x06C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 169 | #define MX53_PAD_DISP0_DAT3__CSPI_SS0 IOMUX_PAD(0x398, 0x06C, 2, 0x78C, 0, NO_PAD_CTRL) | ||
| 170 | #define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 IOMUX_PAD(0x398, 0x06C, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 171 | #define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR IOMUX_PAD(0x398, 0x06C, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 172 | #define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 IOMUX_PAD(0x398, 0x06C, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 173 | #define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR IOMUX_PAD(0x398, 0x06C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 174 | #define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 IOMUX_PAD(0x39C, 0x070, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 175 | #define MX53_PAD_DISP0_DAT4__GPIO4_25 IOMUX_PAD(0x39C, 0x070, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 176 | #define MX53_PAD_DISP0_DAT4__CSPI_SS1 IOMUX_PAD(0x39C, 0x070, 2, 0x790, 0, NO_PAD_CTRL) | ||
| 177 | #define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 IOMUX_PAD(0x39C, 0x070, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 178 | #define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB IOMUX_PAD(0x39C, 0x070, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 179 | #define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 IOMUX_PAD(0x39C, 0x070, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 180 | #define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK IOMUX_PAD(0x39C, 0x070, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 181 | #define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 IOMUX_PAD(0x3A0, 0x074, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 182 | #define MX53_PAD_DISP0_DAT5__GPIO4_26 IOMUX_PAD(0x3A0, 0x074, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 183 | #define MX53_PAD_DISP0_DAT5__CSPI_SS2 IOMUX_PAD(0x3A0, 0x074, 2, 0x794, 0, NO_PAD_CTRL) | ||
| 184 | #define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 IOMUX_PAD(0x3A0, 0x074, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 185 | #define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS IOMUX_PAD(0x3A0, 0x074, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 186 | #define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 IOMUX_PAD(0x3A0, 0x074, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 187 | #define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 IOMUX_PAD(0x3A0, 0x074, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 188 | #define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 IOMUX_PAD(0x3A4, 0x078, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 189 | #define MX53_PAD_DISP0_DAT6__GPIO4_27 IOMUX_PAD(0x3A4, 0x078, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 190 | #define MX53_PAD_DISP0_DAT6__CSPI_SS3 IOMUX_PAD(0x3A4, 0x078, 2, 0x798, 0, NO_PAD_CTRL) | ||
| 191 | #define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 IOMUX_PAD(0x3A4, 0x078, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 192 | #define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE IOMUX_PAD(0x3A4, 0x078, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 193 | #define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 IOMUX_PAD(0x3A4, 0x078, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 194 | #define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 IOMUX_PAD(0x3A4, 0x078, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 195 | #define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 IOMUX_PAD(0x3A8, 0x07C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 196 | #define MX53_PAD_DISP0_DAT7__GPIO4_28 IOMUX_PAD(0x3A8, 0x07C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 197 | #define MX53_PAD_DISP0_DAT7__CSPI_RDY IOMUX_PAD(0x3A8, 0x07C, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 198 | #define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 IOMUX_PAD(0x3A8, 0x07C, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 199 | #define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 IOMUX_PAD(0x3A8, 0x07C, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 200 | #define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 IOMUX_PAD(0x3A8, 0x07C, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 201 | #define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID IOMUX_PAD(0x3A8, 0x07C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 202 | #define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 IOMUX_PAD(0x3AC, 0x080, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 203 | #define MX53_PAD_DISP0_DAT8__GPIO4_29 IOMUX_PAD(0x3AC, 0x080, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 204 | #define MX53_PAD_DISP0_DAT8__PWM1_PWMO IOMUX_PAD(0x3AC, 0x080, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 205 | #define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B IOMUX_PAD(0x3AC, 0x080, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 206 | #define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 IOMUX_PAD(0x3AC, 0x080, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 207 | #define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 IOMUX_PAD(0x3AC, 0x080, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 208 | #define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID IOMUX_PAD(0x3AC, 0x080, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 209 | #define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 IOMUX_PAD(0x3B0, 0x084, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 210 | #define MX53_PAD_DISP0_DAT9__GPIO4_30 IOMUX_PAD(0x3B0, 0x084, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 211 | #define MX53_PAD_DISP0_DAT9__PWM2_PWMO IOMUX_PAD(0x3B0, 0x084, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 212 | #define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B IOMUX_PAD(0x3B0, 0x084, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 213 | #define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 IOMUX_PAD(0x3B0, 0x084, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 214 | #define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 IOMUX_PAD(0x3B0, 0x084, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 215 | #define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 IOMUX_PAD(0x3B0, 0x084, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 216 | #define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 IOMUX_PAD(0x3B4, 0x088, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 217 | #define MX53_PAD_DISP0_DAT10__GPIO4_31 IOMUX_PAD(0x3B4, 0x088, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 218 | #define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP IOMUX_PAD(0x3B4, 0x088, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 219 | #define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 \ | ||
| 220 | IOMUX_PAD(0x3B4, 0x088, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 221 | #define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 IOMUX_PAD(0x3B4, 0x088, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 222 | #define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 IOMUX_PAD(0x3B4, 0x088, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 223 | #define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 IOMUX_PAD(0x3B8, 0x08C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 224 | #define MX53_PAD_DISP0_DAT11__GPIO5_5 IOMUX_PAD(0x3B8, 0x08C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 225 | #define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT IOMUX_PAD(0x3B8, 0x08C, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 226 | #define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 \ | ||
| 227 | IOMUX_PAD(0x3B8, 0x08C, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 228 | #define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 IOMUX_PAD(0x3B8, 0x08C, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 229 | #define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 IOMUX_PAD(0x3B8, 0x08C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 230 | #define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 IOMUX_PAD(0x3BC, 0x090, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 231 | #define MX53_PAD_DISP0_DAT12__GPIO5_6 IOMUX_PAD(0x3BC, 0x090, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 232 | #define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK IOMUX_PAD(0x3BC, 0x090, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 233 | #define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 \ | ||
| 234 | IOMUX_PAD(0x3BC, 0x090, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 235 | #define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 IOMUX_PAD(0x3BC, 0x090, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 236 | #define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 IOMUX_PAD(0x3BC, 0x090, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 237 | #define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 IOMUX_PAD(0x3C0, 0x094, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 238 | #define MX53_PAD_DISP0_DAT13__GPIO5_7 IOMUX_PAD(0x3C0, 0x094, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 239 | #define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS IOMUX_PAD(0x3C0, 0x094, 3, 0x754, 0, NO_PAD_CTRL) | ||
| 240 | #define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 \ | ||
| 241 | IOMUX_PAD(0x3C0, 0x094, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 242 | #define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 IOMUX_PAD(0x3C0, 0x094, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 243 | #define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 IOMUX_PAD(0x3C0, 0x094, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 244 | #define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 IOMUX_PAD(0x3C4, 0x098, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 245 | #define MX53_PAD_DISP0_DAT14__GPIO5_8 IOMUX_PAD(0x3C4, 0x098, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 246 | #define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC IOMUX_PAD(0x3C4, 0x098, 3, 0x750, 0, NO_PAD_CTRL) | ||
| 247 | #define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 \ | ||
| 248 | IOMUX_PAD(0x3C4, 0x098, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 249 | #define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 IOMUX_PAD(0x3C4, 0x098, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 250 | #define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 IOMUX_PAD(0x3C4, 0x098, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 251 | #define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 IOMUX_PAD(0x3C8, 0x09C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 252 | #define MX53_PAD_DISP0_DAT15__GPIO5_9 IOMUX_PAD(0x3C8, 0x09C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 253 | #define MX53_PAD_DISP0_DAT15__ECSPI1_SS1 IOMUX_PAD(0x3C8, 0x09C, 2, 0x7AC, 1, NO_PAD_CTRL) | ||
| 254 | #define MX53_PAD_DISP0_DAT15__ECSPI2_SS1 IOMUX_PAD(0x3C8, 0x09C, 3, 0x7C8, 0, NO_PAD_CTRL) | ||
| 255 | #define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 \ | ||
| 256 | IOMUX_PAD(0x3C8, 0x09C, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 257 | #define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 IOMUX_PAD(0x3C8, 0x09C, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 258 | #define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 IOMUX_PAD(0x3C8, 0x09C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 259 | #define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 IOMUX_PAD(0x3CC, 0x0A0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 260 | #define MX53_PAD_DISP0_DAT16__GPIO5_10 IOMUX_PAD(0x3CC, 0x0A0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 261 | #define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI IOMUX_PAD(0x3CC, 0x0A0, 2, 0x7C0, 0, NO_PAD_CTRL) | ||
| 262 | #define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC IOMUX_PAD(0x3CC, 0x0A0, 3, 0x758, 1, NO_PAD_CTRL) | ||
| 263 | #define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 IOMUX_PAD(0x3CC, 0x0A0, 4, 0x868, 0, NO_PAD_CTRL) | ||
| 264 | #define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 \ | ||
| 265 | IOMUX_PAD(0x3CC, 0x0A0, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 266 | #define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 IOMUX_PAD(0x3CC, 0x0A0, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 267 | #define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 IOMUX_PAD(0x3CC, 0x0A0, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 268 | #define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 IOMUX_PAD(0x3D0, 0x0A4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 269 | #define MX53_PAD_DISP0_DAT17__GPIO5_11 IOMUX_PAD(0x3D0, 0x0A4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 270 | #define MX53_PAD_DISP0_DAT17__ECSPI2_MISO IOMUX_PAD(0x3D0, 0x0A4, 2, 0x7BC, 0, NO_PAD_CTRL) | ||
| 271 | #define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD IOMUX_PAD(0x3D0, 0x0A4, 3, 0x74C, 1, NO_PAD_CTRL) | ||
| 272 | #define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 IOMUX_PAD(0x3D0, 0x0A4, 4, 0x86C, 0, NO_PAD_CTRL) | ||
| 273 | #define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 \ | ||
| 274 | IOMUX_PAD(0x3D0, 0x0A4, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 275 | #define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 IOMUX_PAD(0x3D0, 0x0A4, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 276 | #define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 IOMUX_PAD(0x3D4, 0x0A8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 277 | #define MX53_PAD_DISP0_DAT18__GPIO5_12 IOMUX_PAD(0x3D4, 0x0A8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 278 | #define MX53_PAD_DISP0_DAT18__ECSPI2_SS0 IOMUX_PAD(0x3D4, 0x0A8, 2, 0x7C4, 0, NO_PAD_CTRL) | ||
| 279 | #define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS IOMUX_PAD(0x3D4, 0x0A8, 3, 0x75C, 1, NO_PAD_CTRL) | ||
| 280 | #define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS IOMUX_PAD(0x3D4, 0x0A8, 4, 0x73C, 0, NO_PAD_CTRL) | ||
| 281 | #define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 \ | ||
| 282 | IOMUX_PAD(0x3D4, 0x0A8, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 283 | #define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 IOMUX_PAD(0x3D4, 0x0A8, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 284 | #define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 IOMUX_PAD(0x3D4, 0x0A8, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 285 | #define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 IOMUX_PAD(0x3D8, 0x0AC, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 286 | #define MX53_PAD_DISP0_DAT19__GPIO5_13 IOMUX_PAD(0x3D8, 0x0AC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 287 | #define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK IOMUX_PAD(0x3D8, 0x0AC, 2, 0x7B8, 0, NO_PAD_CTRL) | ||
| 288 | #define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD IOMUX_PAD(0x3D8, 0x0AC, 3, 0x748, 1, NO_PAD_CTRL) | ||
| 289 | #define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC IOMUX_PAD(0x3D8, 0x0AC, 4, 0x738, 0, NO_PAD_CTRL) | ||
| 290 | #define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 \ | ||
| 291 | IOMUX_PAD(0x3D8, 0x0AC, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 292 | #define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 IOMUX_PAD(0x3D8, 0x0AC, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 293 | #define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 IOMUX_PAD(0x3D8, 0x0AC, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 294 | #define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 IOMUX_PAD(0x3DC, 0x0B0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 295 | #define MX53_PAD_DISP0_DAT20__GPIO5_14 IOMUX_PAD(0x3DC, 0x0B0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 296 | #define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK IOMUX_PAD(0x3DC, 0x0B0, 2, 0x79C, 1, NO_PAD_CTRL) | ||
| 297 | #define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC IOMUX_PAD(0x3DC, 0x0B0, 3, 0x740, 0, NO_PAD_CTRL) | ||
| 298 | #define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 \ | ||
| 299 | IOMUX_PAD(0x3DC, 0x0B0, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 300 | #define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 IOMUX_PAD(0x3DC, 0x0B0, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 301 | #define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI IOMUX_PAD(0x3DC, 0x0B0, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 302 | #define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 IOMUX_PAD(0x3E0, 0x0B4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 303 | #define MX53_PAD_DISP0_DAT21__GPIO5_15 IOMUX_PAD(0x3E0, 0x0B4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 304 | #define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI IOMUX_PAD(0x3E0, 0x0B4, 2, 0x7A4, 1, NO_PAD_CTRL) | ||
| 305 | #define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD IOMUX_PAD(0x3E0, 0x0B4, 3, 0x734, 0, NO_PAD_CTRL) | ||
| 306 | #define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 IOMUX_PAD(0x3E0, 0x0B4, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 307 | #define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 IOMUX_PAD(0x3E0, 0x0B4, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 308 | #define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO IOMUX_PAD(0x3E0, 0x0B4, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 309 | #define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 IOMUX_PAD(0x3E4, 0x0B8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 310 | #define MX53_PAD_DISP0_DAT22__GPIO5_16 IOMUX_PAD(0x3E4, 0x0B8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 311 | #define MX53_PAD_DISP0_DAT22__ECSPI1_MISO IOMUX_PAD(0x3E4, 0x0B8, 2, 0x7A0, 1, NO_PAD_CTRL) | ||
| 312 | #define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS IOMUX_PAD(0x3E4, 0x0B8, 3, 0x744, 0, NO_PAD_CTRL) | ||
| 313 | #define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 IOMUX_PAD(0x3E4, 0x0B8, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 314 | #define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 IOMUX_PAD(0x3E4, 0x0B8, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 315 | #define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK IOMUX_PAD(0x3E4, 0x0B8, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 316 | #define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 IOMUX_PAD(0x3E8, 0x0BC, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 317 | #define MX53_PAD_DISP0_DAT23__GPIO5_17 IOMUX_PAD(0x3E8, 0x0BC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 318 | #define MX53_PAD_DISP0_DAT23__ECSPI1_SS0 IOMUX_PAD(0x3E8, 0x0BC, 2, 0x7A8, 1, NO_PAD_CTRL) | ||
| 319 | #define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD IOMUX_PAD(0x3E8, 0x0BC, 3, 0x730, 0, NO_PAD_CTRL) | ||
| 320 | #define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 IOMUX_PAD(0x3E8, 0x0BC, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 321 | #define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 IOMUX_PAD(0x3E8, 0x0BC, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 322 | #define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS IOMUX_PAD(0x3E8, 0x0BC, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 323 | #define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK IOMUX_PAD(0x3EC, 0x0C0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 324 | #define MX53_PAD_CSI0_PIXCLK__GPIO5_18 IOMUX_PAD(0x3EC, 0x0C0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 325 | #define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 IOMUX_PAD(0x3EC, 0x0C0, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 326 | #define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 IOMUX_PAD(0x3EC, 0x0C0, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 327 | #define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC IOMUX_PAD(0x3F0, 0x0C4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 328 | #define MX53_PAD_CSI0_MCLK__GPIO5_19 IOMUX_PAD(0x3F0, 0x0C4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 329 | #define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK IOMUX_PAD(0x3F0, 0x0C4, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 330 | #define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 IOMUX_PAD(0x3F0, 0x0C4, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 331 | #define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 IOMUX_PAD(0x3F0, 0x0C4, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 332 | #define MX53_PAD_CSI0_MCLK__TPIU_TRCTL IOMUX_PAD(0x3F0, 0x0C4, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 333 | #define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN IOMUX_PAD(0x3F4, 0x0C8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 334 | #define MX53_PAD_CSI0_DATA_EN__GPIO5_20 IOMUX_PAD(0x3F4, 0x0C8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 335 | #define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 IOMUX_PAD(0x3F4, 0x0C8, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 336 | #define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 IOMUX_PAD(0x3F4, 0x0C8, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 337 | #define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK IOMUX_PAD(0x3F4, 0x0C8, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 338 | #define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC IOMUX_PAD(0x3F8, 0x0CC, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 339 | #define MX53_PAD_CSI0_VSYNC__GPIO5_21 IOMUX_PAD(0x3F8, 0x0CC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 340 | #define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 IOMUX_PAD(0x3F8, 0x0CC, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 341 | #define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 IOMUX_PAD(0x3F8, 0x0CC, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 342 | #define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 IOMUX_PAD(0x3F8, 0x0CC, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 343 | #define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 IOMUX_PAD(0x3FC, 0x0D0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 344 | #define MX53_PAD_CSI0_DAT4__GPIO5_22 IOMUX_PAD(0x3FC, 0x0D0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 345 | #define MX53_PAD_CSI0_DAT4__KPP_COL_5 IOMUX_PAD(0x3FC, 0x0D0, 2, 0x840, 1, NO_PAD_CTRL) | ||
| 346 | #define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK IOMUX_PAD(0x3FC, 0x0D0, 3, 0x79C, 2, NO_PAD_CTRL) | ||
| 347 | #define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP IOMUX_PAD(0x3FC, 0x0D0, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 348 | #define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC IOMUX_PAD(0x3FC, 0x0D0, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 349 | #define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 IOMUX_PAD(0x3FC, 0x0D0, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 350 | #define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 IOMUX_PAD(0x3FC, 0x0D0, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 351 | #define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 IOMUX_PAD(0x400, 0x0D4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 352 | #define MX53_PAD_CSI0_DAT5__GPIO5_23 IOMUX_PAD(0x400, 0x0D4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 353 | #define MX53_PAD_CSI0_DAT5__KPP_ROW_5 IOMUX_PAD(0x400, 0x0D4, 2, 0x84C, 0, NO_PAD_CTRL) | ||
| 354 | #define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI IOMUX_PAD(0x400, 0x0D4, 3, 0x7A4, 2, NO_PAD_CTRL) | ||
| 355 | #define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT IOMUX_PAD(0x400, 0x0D4, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 356 | #define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD IOMUX_PAD(0x400, 0x0D4, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 357 | #define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 IOMUX_PAD(0x400, 0x0D4, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 358 | #define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 IOMUX_PAD(0x400, 0x0D4, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 359 | #define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 IOMUX_PAD(0x404, 0x0D8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 360 | #define MX53_PAD_CSI0_DAT6__GPIO5_24 IOMUX_PAD(0x404, 0x0D8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 361 | #define MX53_PAD_CSI0_DAT6__KPP_COL_6 IOMUX_PAD(0x404, 0x0D8, 2, 0x844, 0, NO_PAD_CTRL) | ||
| 362 | #define MX53_PAD_CSI0_DAT6__ECSPI1_MISO IOMUX_PAD(0x404, 0x0D8, 3, 0x7A0, 2, NO_PAD_CTRL) | ||
| 363 | #define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK IOMUX_PAD(0x404, 0x0D8, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 364 | #define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS IOMUX_PAD(0x404, 0x0D8, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 365 | #define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 IOMUX_PAD(0x404, 0x0D8, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 366 | #define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 IOMUX_PAD(0x404, 0x0D8, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 367 | #define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 IOMUX_PAD(0x408, 0x0DC, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 368 | #define MX53_PAD_CSI0_DAT7__GPIO5_25 IOMUX_PAD(0x408, 0x0DC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 369 | #define MX53_PAD_CSI0_DAT7__KPP_ROW_6 IOMUX_PAD(0x408, 0x0DC, 2, 0x850, 0, NO_PAD_CTRL) | ||
| 370 | #define MX53_PAD_CSI0_DAT7__ECSPI1_SS0 IOMUX_PAD(0x408, 0x0DC, 3, 0x7A8, 2, NO_PAD_CTRL) | ||
| 371 | #define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR IOMUX_PAD(0x408, 0x0DC, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 372 | #define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD IOMUX_PAD(0x408, 0x0DC, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 373 | #define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 IOMUX_PAD(0x408, 0x0DC, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 374 | #define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 IOMUX_PAD(0x408, 0x0DC, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 375 | #define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 IOMUX_PAD(0x40C, 0x0E0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 376 | #define MX53_PAD_CSI0_DAT8__GPIO5_26 IOMUX_PAD(0x40C, 0x0E0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 377 | #define MX53_PAD_CSI0_DAT8__KPP_COL_7 IOMUX_PAD(0x40C, 0x0E0, 2, 0x848, 0, NO_PAD_CTRL) | ||
| 378 | #define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK IOMUX_PAD(0x40C, 0x0E0, 3, 0x7B8, 1, NO_PAD_CTRL) | ||
| 379 | #define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC IOMUX_PAD(0x40C, 0x0E0, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 380 | #define MX53_PAD_CSI0_DAT8__I2C1_SDA IOMUX_PAD(0x40C, 0x0E0, 5 | IOMUX_CONFIG_SION, 0x818, 0, NO_PAD_CTRL) | ||
| 381 | #define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 IOMUX_PAD(0x40C, 0x0E0, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 382 | #define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 IOMUX_PAD(0x40C, 0x0E0, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 383 | #define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 IOMUX_PAD(0x410, 0x0E4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 384 | #define MX53_PAD_CSI0_DAT9__GPIO5_27 IOMUX_PAD(0x410, 0x0E4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 385 | #define MX53_PAD_CSI0_DAT9__KPP_ROW_7 IOMUX_PAD(0x410, 0x0E4, 2, 0x854, 0, NO_PAD_CTRL) | ||
| 386 | #define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI IOMUX_PAD(0x410, 0x0E4, 3, 0x7C0, 1, NO_PAD_CTRL) | ||
| 387 | #define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR IOMUX_PAD(0x410, 0x0E4, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 388 | #define MX53_PAD_CSI0_DAT9__I2C1_SCL IOMUX_PAD(0x410, 0x0E4, 5 | IOMUX_CONFIG_SION, 0x814, 0, NO_PAD_CTRL) | ||
| 389 | #define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 IOMUX_PAD(0x410, 0x0E4, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 390 | #define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 IOMUX_PAD(0x410, 0x0E4, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 391 | #define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 IOMUX_PAD(0x414, 0x0E8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 392 | #define MX53_PAD_CSI0_DAT10__GPIO5_28 IOMUX_PAD(0x414, 0x0E8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 393 | #define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX IOMUX_PAD(0x414, 0x0E8, 2, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 394 | #define MX53_PAD_CSI0_DAT10__ECSPI2_MISO IOMUX_PAD(0x414, 0x0E8, 3, 0x7BC, 1, NO_PAD_CTRL) | ||
| 395 | #define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC IOMUX_PAD(0x414, 0x0E8, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 396 | #define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 IOMUX_PAD(0x414, 0x0E8, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 397 | #define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 IOMUX_PAD(0x414, 0x0E8, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 398 | #define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 IOMUX_PAD(0x414, 0x0E8, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 399 | #define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 IOMUX_PAD(0x418, 0x0EC, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 400 | #define MX53_PAD_CSI0_DAT11__GPIO5_29 IOMUX_PAD(0x418, 0x0EC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 401 | #define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX IOMUX_PAD(0x418, 0x0EC, 2, 0x878, 1, MX53_UART_PAD_CTRL) | ||
| 402 | #define MX53_PAD_CSI0_DAT11__ECSPI2_SS0 IOMUX_PAD(0x418, 0x0EC, 3, 0x7C4, 1, NO_PAD_CTRL) | ||
| 403 | #define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS IOMUX_PAD(0x418, 0x0EC, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 404 | #define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 IOMUX_PAD(0x418, 0x0EC, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 405 | #define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 IOMUX_PAD(0x418, 0x0EC, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 406 | #define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 IOMUX_PAD(0x418, 0x0EC, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 407 | #define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 IOMUX_PAD(0x41C, 0x0F0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 408 | #define MX53_PAD_CSI0_DAT12__GPIO5_30 IOMUX_PAD(0x41C, 0x0F0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 409 | #define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX IOMUX_PAD(0x41C, 0x0F0, 2, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 410 | #define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 IOMUX_PAD(0x41C, 0x0F0, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 411 | #define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 IOMUX_PAD(0x41C, 0x0F0, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 412 | #define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 IOMUX_PAD(0x41C, 0x0F0, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 413 | #define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 IOMUX_PAD(0x41C, 0x0F0, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 414 | #define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 IOMUX_PAD(0x420, 0x0F4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 415 | #define MX53_PAD_CSI0_DAT13__GPIO5_31 IOMUX_PAD(0x420, 0x0F4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 416 | #define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX IOMUX_PAD(0x420, 0x0F4, 2, 0x890, 3, MX53_UART_PAD_CTRL) | ||
| 417 | #define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 IOMUX_PAD(0x420, 0x0F4, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 418 | #define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 IOMUX_PAD(0x420, 0x0F4, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 419 | #define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 IOMUX_PAD(0x420, 0x0F4, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 420 | #define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 IOMUX_PAD(0x420, 0x0F4, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 421 | #define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 IOMUX_PAD(0x424, 0x0F8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 422 | #define MX53_PAD_CSI0_DAT14__GPIO6_0 IOMUX_PAD(0x424, 0x0F8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 423 | #define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX IOMUX_PAD(0x424, 0x0F8, 2, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 424 | #define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 IOMUX_PAD(0x424, 0x0F8, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 425 | #define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 IOMUX_PAD(0x424, 0x0F8, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 426 | #define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 IOMUX_PAD(0x424, 0x0F8, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 427 | #define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 IOMUX_PAD(0x424, 0x0F8, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 428 | #define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 IOMUX_PAD(0x428, 0x0FC, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 429 | #define MX53_PAD_CSI0_DAT15__GPIO6_1 IOMUX_PAD(0x428, 0x0FC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 430 | #define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX IOMUX_PAD(0x428, 0x0FC, 2, 0x898, 3, MX53_UART_PAD_CTRL) | ||
| 431 | #define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 IOMUX_PAD(0x428, 0x0FC, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 432 | #define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 IOMUX_PAD(0x428, 0x0FC, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 433 | #define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 IOMUX_PAD(0x428, 0x0FC, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 434 | #define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 IOMUX_PAD(0x428, 0x0FC, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 435 | #define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 IOMUX_PAD(0x42C, 0x100, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 436 | #define MX53_PAD_CSI0_DAT16__GPIO6_2 IOMUX_PAD(0x42C, 0x100, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 437 | #define MX53_PAD_CSI0_DAT16__UART4_RTS IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, MX53_UART_PAD_CTRL) | ||
| 438 | #define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 IOMUX_PAD(0x42C, 0x100, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 439 | #define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 IOMUX_PAD(0x42C, 0x100, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 440 | #define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 IOMUX_PAD(0x42C, 0x100, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 441 | #define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 IOMUX_PAD(0x42C, 0x100, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 442 | #define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 IOMUX_PAD(0x430, 0x104, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 443 | #define MX53_PAD_CSI0_DAT17__GPIO6_3 IOMUX_PAD(0x430, 0x104, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 444 | #define MX53_PAD_CSI0_DAT17__UART4_CTS IOMUX_PAD(0x430, 0x104, 2, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 445 | #define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 IOMUX_PAD(0x430, 0x104, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 446 | #define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 IOMUX_PAD(0x430, 0x104, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 447 | #define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 IOMUX_PAD(0x430, 0x104, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 448 | #define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 IOMUX_PAD(0x430, 0x104, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 449 | #define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 IOMUX_PAD(0x434, 0x108, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 450 | #define MX53_PAD_CSI0_DAT18__GPIO6_4 IOMUX_PAD(0x434, 0x108, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 451 | #define MX53_PAD_CSI0_DAT18__UART5_RTS IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, MX53_UART_PAD_CTRL) | ||
| 452 | #define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 IOMUX_PAD(0x434, 0x108, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 453 | #define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 IOMUX_PAD(0x434, 0x108, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 454 | #define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 IOMUX_PAD(0x434, 0x108, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 455 | #define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 IOMUX_PAD(0x434, 0x108, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 456 | #define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 IOMUX_PAD(0x438, 0x10C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 457 | #define MX53_PAD_CSI0_DAT19__GPIO6_5 IOMUX_PAD(0x438, 0x10C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 458 | #define MX53_PAD_CSI0_DAT19__UART5_CTS IOMUX_PAD(0x438, 0x10C, 2, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 459 | #define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 IOMUX_PAD(0x438, 0x10C, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 460 | #define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 IOMUX_PAD(0x438, 0x10C, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 461 | #define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 IOMUX_PAD(0x438, 0x10C, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 462 | #define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK IOMUX_PAD(0x438, 0x10C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 463 | #define MX53_PAD_EIM_A25__EMI_WEIM_A_25 IOMUX_PAD(0x458, 0x110, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 464 | #define MX53_PAD_EIM_A25__GPIO5_2 IOMUX_PAD(0x458, 0x110, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 465 | #define MX53_PAD_EIM_A25__ECSPI2_RDY IOMUX_PAD(0x458, 0x110, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 466 | #define MX53_PAD_EIM_A25__IPU_DI1_PIN12 IOMUX_PAD(0x458, 0x110, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 467 | #define MX53_PAD_EIM_A25__CSPI_SS1 IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, NO_PAD_CTRL) | ||
| 468 | #define MX53_PAD_EIM_A25__IPU_DI0_D1_CS IOMUX_PAD(0x458, 0x110, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 469 | #define MX53_PAD_EIM_A25__USBPHY1_BISTOK IOMUX_PAD(0x458, 0x110, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 470 | #define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 IOMUX_PAD(0x45C, 0x114, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 471 | #define MX53_PAD_EIM_EB2__GPIO2_30 IOMUX_PAD(0x45C, 0x114, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 472 | #define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, NO_PAD_CTRL) | ||
| 473 | #define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS IOMUX_PAD(0x45C, 0x114, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 474 | #define MX53_PAD_EIM_EB2__ECSPI1_SS0 IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, NO_PAD_CTRL) | ||
| 475 | #define MX53_PAD_EIM_EB2__I2C2_SCL IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, NO_PAD_CTRL) | ||
| 476 | #define MX53_PAD_EIM_D16__EMI_WEIM_D_16 IOMUX_PAD(0x460, 0x118, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 477 | #define MX53_PAD_EIM_D16__GPIO3_16 IOMUX_PAD(0x460, 0x118, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 478 | #define MX53_PAD_EIM_D16__IPU_DI0_PIN5 IOMUX_PAD(0x460, 0x118, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 479 | #define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK IOMUX_PAD(0x460, 0x118, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 480 | #define MX53_PAD_EIM_D16__ECSPI1_SCLK IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, NO_PAD_CTRL) | ||
| 481 | #define MX53_PAD_EIM_D16__I2C2_SDA IOMUX_PAD(0x460, 0x118, 5 | IOMUX_CONFIG_SION, 0x820, 1, NO_PAD_CTRL) | ||
| 482 | #define MX53_PAD_EIM_D17__EMI_WEIM_D_17 IOMUX_PAD(0x464, 0x11C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 483 | #define MX53_PAD_EIM_D17__GPIO3_17 IOMUX_PAD(0x464, 0x11C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 484 | #define MX53_PAD_EIM_D17__IPU_DI0_PIN6 IOMUX_PAD(0x464, 0x11C, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 485 | #define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, NO_PAD_CTRL) | ||
| 486 | #define MX53_PAD_EIM_D17__ECSPI1_MISO IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, NO_PAD_CTRL) | ||
| 487 | #define MX53_PAD_EIM_D17__I2C3_SCL IOMUX_PAD(0x464, 0x11C, 5 | IOMUX_CONFIG_SION, 0x824, 0, NO_PAD_CTRL) | ||
| 488 | #define MX53_PAD_EIM_D18__EMI_WEIM_D_18 IOMUX_PAD(0x468, 0x120, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 489 | #define MX53_PAD_EIM_D18__GPIO3_18 IOMUX_PAD(0x468, 0x120, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 490 | #define MX53_PAD_EIM_D18__IPU_DI0_PIN7 IOMUX_PAD(0x468, 0x120, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 491 | #define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, NO_PAD_CTRL) | ||
| 492 | #define MX53_PAD_EIM_D18__ECSPI1_MOSI IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, NO_PAD_CTRL) | ||
| 493 | #define MX53_PAD_EIM_D18__I2C3_SDA IOMUX_PAD(0x468, 0x120, 5 | IOMUX_CONFIG_SION, 0x828, 0, NO_PAD_CTRL) | ||
| 494 | #define MX53_PAD_EIM_D18__IPU_DI1_D0_CS IOMUX_PAD(0x468, 0x120, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 495 | #define MX53_PAD_EIM_D19__EMI_WEIM_D_19 IOMUX_PAD(0x46C, 0x124, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 496 | #define MX53_PAD_EIM_D19__GPIO3_19 IOMUX_PAD(0x46C, 0x124, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 497 | #define MX53_PAD_EIM_D19__IPU_DI0_PIN8 IOMUX_PAD(0x46C, 0x124, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 498 | #define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS IOMUX_PAD(0x46C, 0x124, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 499 | #define MX53_PAD_EIM_D19__ECSPI1_SS1 IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, NO_PAD_CTRL) | ||
| 500 | #define MX53_PAD_EIM_D19__EPIT1_EPITO IOMUX_PAD(0x46C, 0x124, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 501 | #define MX53_PAD_EIM_D19__UART1_CTS IOMUX_PAD(0x46C, 0x124, 6, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 502 | #define MX53_PAD_EIM_D19__USBOH3_USBH2_OC IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, NO_PAD_CTRL) | ||
| 503 | #define MX53_PAD_EIM_D20__EMI_WEIM_D_20 IOMUX_PAD(0x470, 0x128, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 504 | #define MX53_PAD_EIM_D20__GPIO3_20 IOMUX_PAD(0x470, 0x128, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 505 | #define MX53_PAD_EIM_D20__IPU_DI0_PIN16 IOMUX_PAD(0x470, 0x128, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 506 | #define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS IOMUX_PAD(0x470, 0x128, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 507 | #define MX53_PAD_EIM_D20__CSPI_SS0 IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, NO_PAD_CTRL) | ||
| 508 | #define MX53_PAD_EIM_D20__EPIT2_EPITO IOMUX_PAD(0x470, 0x128, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 509 | #define MX53_PAD_EIM_D20__UART1_RTS IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, MX53_UART_PAD_CTRL) | ||
| 510 | #define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR IOMUX_PAD(0x470, 0x128, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 511 | #define MX53_PAD_EIM_D21__EMI_WEIM_D_21 IOMUX_PAD(0x474, 0x12C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 512 | #define MX53_PAD_EIM_D21__GPIO3_21 IOMUX_PAD(0x474, 0x12C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 513 | #define MX53_PAD_EIM_D21__IPU_DI0_PIN17 IOMUX_PAD(0x474, 0x12C, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 514 | #define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK IOMUX_PAD(0x474, 0x12C, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 515 | #define MX53_PAD_EIM_D21__CSPI_SCLK IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, NO_PAD_CTRL) | ||
| 516 | #define MX53_PAD_EIM_D21__I2C1_SCL IOMUX_PAD(0x474, 0x12C, 5 | IOMUX_CONFIG_SION, 0x814, 1, NO_PAD_CTRL) | ||
| 517 | #define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, NO_PAD_CTRL) | ||
| 518 | #define MX53_PAD_EIM_D22__EMI_WEIM_D_22 IOMUX_PAD(0x478, 0x130, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 519 | #define MX53_PAD_EIM_D22__GPIO3_22 IOMUX_PAD(0x478, 0x130, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 520 | #define MX53_PAD_EIM_D22__IPU_DI0_PIN1 IOMUX_PAD(0x478, 0x130, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 521 | #define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, NO_PAD_CTRL) | ||
| 522 | #define MX53_PAD_EIM_D22__CSPI_MISO IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, NO_PAD_CTRL) | ||
| 523 | #define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR IOMUX_PAD(0x478, 0x130, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 524 | #define MX53_PAD_EIM_D23__EMI_WEIM_D_23 IOMUX_PAD(0x47C, 0x134, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 525 | #define MX53_PAD_EIM_D23__GPIO3_23 IOMUX_PAD(0x47C, 0x134, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 526 | #define MX53_PAD_EIM_D23__UART3_CTS IOMUX_PAD(0x47C, 0x134, 2, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 527 | #define MX53_PAD_EIM_D23__UART1_DCD IOMUX_PAD(0x47C, 0x134, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 528 | #define MX53_PAD_EIM_D23__IPU_DI0_D0_CS IOMUX_PAD(0x47C, 0x134, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 529 | #define MX53_PAD_EIM_D23__IPU_DI1_PIN2 IOMUX_PAD(0x47C, 0x134, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 530 | #define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, NO_PAD_CTRL) | ||
| 531 | #define MX53_PAD_EIM_D23__IPU_DI1_PIN14 IOMUX_PAD(0x47C, 0x134, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 532 | #define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 IOMUX_PAD(0x480, 0x138, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 533 | #define MX53_PAD_EIM_EB3__GPIO2_31 IOMUX_PAD(0x480, 0x138, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 534 | #define MX53_PAD_EIM_EB3__UART3_RTS IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, MX53_UART_PAD_CTRL) | ||
| 535 | #define MX53_PAD_EIM_EB3__UART1_RI IOMUX_PAD(0x480, 0x138, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 536 | #define MX53_PAD_EIM_EB3__IPU_DI1_PIN3 IOMUX_PAD(0x480, 0x138, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 537 | #define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, NO_PAD_CTRL) | ||
| 538 | #define MX53_PAD_EIM_EB3__IPU_DI1_PIN16 IOMUX_PAD(0x480, 0x138, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 539 | #define MX53_PAD_EIM_D24__EMI_WEIM_D_24 IOMUX_PAD(0x484, 0x13C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 540 | #define MX53_PAD_EIM_D24__GPIO3_24 IOMUX_PAD(0x484, 0x13C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 541 | #define MX53_PAD_EIM_D24__UART3_TXD_MUX IOMUX_PAD(0x484, 0x13C, 2, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 542 | #define MX53_PAD_EIM_D24__ECSPI1_SS2 IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, NO_PAD_CTRL) | ||
| 543 | #define MX53_PAD_EIM_D24__CSPI_SS2 IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, NO_PAD_CTRL) | ||
| 544 | #define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, NO_PAD_CTRL) | ||
| 545 | #define MX53_PAD_EIM_D24__ECSPI2_SS2 IOMUX_PAD(0x484, 0x13C, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 546 | #define MX53_PAD_EIM_D24__UART1_DTR IOMUX_PAD(0x484, 0x13C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 547 | #define MX53_PAD_EIM_D25__EMI_WEIM_D_25 IOMUX_PAD(0x488, 0x140, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 548 | #define MX53_PAD_EIM_D25__GPIO3_25 IOMUX_PAD(0x488, 0x140, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 549 | #define MX53_PAD_EIM_D25__UART3_RXD_MUX IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, MX53_UART_PAD_CTRL) | ||
| 550 | #define MX53_PAD_EIM_D25__ECSPI1_SS3 IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, NO_PAD_CTRL) | ||
| 551 | #define MX53_PAD_EIM_D25__CSPI_SS3 IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, NO_PAD_CTRL) | ||
| 552 | #define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, NO_PAD_CTRL) | ||
| 553 | #define MX53_PAD_EIM_D25__ECSPI2_SS3 IOMUX_PAD(0x488, 0x140, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 554 | #define MX53_PAD_EIM_D25__UART1_DSR IOMUX_PAD(0x488, 0x140, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 555 | #define MX53_PAD_EIM_D26__EMI_WEIM_D_26 IOMUX_PAD(0x48C, 0x144, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 556 | #define MX53_PAD_EIM_D26__GPIO3_26 IOMUX_PAD(0x48C, 0x144, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 557 | #define MX53_PAD_EIM_D26__UART2_TXD_MUX IOMUX_PAD(0x48C, 0x144, 2, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 558 | #define MX53_PAD_EIM_D26__FIRI_RXD IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, NO_PAD_CTRL) | ||
| 559 | #define MX53_PAD_EIM_D26__IPU_CSI0_D_1 IOMUX_PAD(0x48C, 0x144, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 560 | #define MX53_PAD_EIM_D26__IPU_DI1_PIN11 IOMUX_PAD(0x48C, 0x144, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 561 | #define MX53_PAD_EIM_D26__IPU_SISG_2 IOMUX_PAD(0x48C, 0x144, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 562 | #define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 IOMUX_PAD(0x48C, 0x144, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 563 | #define MX53_PAD_EIM_D27__EMI_WEIM_D_27 IOMUX_PAD(0x490, 0x148, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 564 | #define MX53_PAD_EIM_D27__GPIO3_27 IOMUX_PAD(0x490, 0x148, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 565 | #define MX53_PAD_EIM_D27__UART2_RXD_MUX IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, MX53_UART_PAD_CTRL) | ||
| 566 | #define MX53_PAD_EIM_D27__FIRI_TXD IOMUX_PAD(0x490, 0x148, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 567 | #define MX53_PAD_EIM_D27__IPU_CSI0_D_0 IOMUX_PAD(0x490, 0x148, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 568 | #define MX53_PAD_EIM_D27__IPU_DI1_PIN13 IOMUX_PAD(0x490, 0x148, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 569 | #define MX53_PAD_EIM_D27__IPU_SISG_3 IOMUX_PAD(0x490, 0x148, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 570 | #define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 IOMUX_PAD(0x490, 0x148, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 571 | #define MX53_PAD_EIM_D28__EMI_WEIM_D_28 IOMUX_PAD(0x494, 0x14C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 572 | #define MX53_PAD_EIM_D28__GPIO3_28 IOMUX_PAD(0x494, 0x14C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 573 | #define MX53_PAD_EIM_D28__UART2_CTS IOMUX_PAD(0x494, 0x14C, 2, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 574 | #define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, NO_PAD_CTRL) | ||
| 575 | #define MX53_PAD_EIM_D28__CSPI_MOSI IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, NO_PAD_CTRL) | ||
| 576 | #define MX53_PAD_EIM_D28__I2C1_SDA IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, NO_PAD_CTRL) | ||
| 577 | #define MX53_PAD_EIM_D28__IPU_EXT_TRIG IOMUX_PAD(0x494, 0x14C, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 578 | #define MX53_PAD_EIM_D28__IPU_DI0_PIN13 IOMUX_PAD(0x494, 0x14C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 579 | #define MX53_PAD_EIM_D29__EMI_WEIM_D_29 IOMUX_PAD(0x498, 0x150, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 580 | #define MX53_PAD_EIM_D29__GPIO3_29 IOMUX_PAD(0x498, 0x150, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 581 | #define MX53_PAD_EIM_D29__UART2_RTS IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, MX53_UART_PAD_CTRL) | ||
| 582 | #define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS IOMUX_PAD(0x498, 0x150, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 583 | #define MX53_PAD_EIM_D29__CSPI_SS0 IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, NO_PAD_CTRL) | ||
| 584 | #define MX53_PAD_EIM_D29__IPU_DI1_PIN15 IOMUX_PAD(0x498, 0x150, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 585 | #define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, NO_PAD_CTRL) | ||
| 586 | #define MX53_PAD_EIM_D29__IPU_DI0_PIN14 IOMUX_PAD(0x498, 0x150, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 587 | #define MX53_PAD_EIM_D30__EMI_WEIM_D_30 IOMUX_PAD(0x49C, 0x154, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 588 | #define MX53_PAD_EIM_D30__GPIO3_30 IOMUX_PAD(0x49C, 0x154, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 589 | #define MX53_PAD_EIM_D30__UART3_CTS IOMUX_PAD(0x49C, 0x154, 2, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 590 | #define MX53_PAD_EIM_D30__IPU_CSI0_D_3 IOMUX_PAD(0x49C, 0x154, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 591 | #define MX53_PAD_EIM_D30__IPU_DI0_PIN11 IOMUX_PAD(0x49C, 0x154, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 592 | #define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 IOMUX_PAD(0x49C, 0x154, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 593 | #define MX53_PAD_EIM_D30__USBOH3_USBH1_OC IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, NO_PAD_CTRL) | ||
| 594 | #define MX53_PAD_EIM_D30__USBOH3_USBH2_OC IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, NO_PAD_CTRL) | ||
| 595 | #define MX53_PAD_EIM_D31__EMI_WEIM_D_31 IOMUX_PAD(0x4A0, 0x158, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 596 | #define MX53_PAD_EIM_D31__GPIO3_31 IOMUX_PAD(0x4A0, 0x158, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 597 | #define MX53_PAD_EIM_D31__UART3_RTS IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, MX53_UART_PAD_CTRL) | ||
| 598 | #define MX53_PAD_EIM_D31__IPU_CSI0_D_2 IOMUX_PAD(0x4A0, 0x158, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 599 | #define MX53_PAD_EIM_D31__IPU_DI0_PIN12 IOMUX_PAD(0x4A0, 0x158, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 600 | #define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 IOMUX_PAD(0x4A0, 0x158, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 601 | #define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR IOMUX_PAD(0x4A0, 0x158, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 602 | #define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR IOMUX_PAD(0x4A0, 0x158, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 603 | #define MX53_PAD_EIM_A24__EMI_WEIM_A_24 IOMUX_PAD(0x4A8, 0x15C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 604 | #define MX53_PAD_EIM_A24__GPIO5_4 IOMUX_PAD(0x4A8, 0x15C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 605 | #define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 IOMUX_PAD(0x4A8, 0x15C, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 606 | #define MX53_PAD_EIM_A24__IPU_CSI1_D_19 IOMUX_PAD(0x4A8, 0x15C, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 607 | #define MX53_PAD_EIM_A24__IPU_SISG_2 IOMUX_PAD(0x4A8, 0x15C, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 608 | #define MX53_PAD_EIM_A24__USBPHY2_BVALID IOMUX_PAD(0x4A8, 0x15C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 609 | #define MX53_PAD_EIM_A23__EMI_WEIM_A_23 IOMUX_PAD(0x4AC, 0x160, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 610 | #define MX53_PAD_EIM_A23__GPIO6_6 IOMUX_PAD(0x4AC, 0x160, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 611 | #define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 IOMUX_PAD(0x4AC, 0x160, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 612 | #define MX53_PAD_EIM_A23__IPU_CSI1_D_18 IOMUX_PAD(0x4AC, 0x160, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 613 | #define MX53_PAD_EIM_A23__IPU_SISG_3 IOMUX_PAD(0x4AC, 0x160, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 614 | #define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION IOMUX_PAD(0x4AC, 0x160, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 615 | #define MX53_PAD_EIM_A22__EMI_WEIM_A_22 IOMUX_PAD(0x4B0, 0x164, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 616 | #define MX53_PAD_EIM_A22__GPIO2_16 IOMUX_PAD(0x4B0, 0x164, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 617 | #define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 IOMUX_PAD(0x4B0, 0x164, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 618 | #define MX53_PAD_EIM_A22__IPU_CSI1_D_17 IOMUX_PAD(0x4B0, 0x164, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 619 | #define MX53_PAD_EIM_A22__SRC_BT_CFG1_7 IOMUX_PAD(0x4B0, 0x164, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 620 | #define MX53_PAD_EIM_A21__EMI_WEIM_A_21 IOMUX_PAD(0x4B4, 0x168, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 621 | #define MX53_PAD_EIM_A21__GPIO2_17 IOMUX_PAD(0x4B4, 0x168, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 622 | #define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 IOMUX_PAD(0x4B4, 0x168, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 623 | #define MX53_PAD_EIM_A21__IPU_CSI1_D_16 IOMUX_PAD(0x4B4, 0x168, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 624 | #define MX53_PAD_EIM_A21__SRC_BT_CFG1_6 IOMUX_PAD(0x4B4, 0x168, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 625 | #define MX53_PAD_EIM_A20__EMI_WEIM_A_20 IOMUX_PAD(0x4B8, 0x16C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 626 | #define MX53_PAD_EIM_A20__GPIO2_18 IOMUX_PAD(0x4B8, 0x16C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 627 | #define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 IOMUX_PAD(0x4B8, 0x16C, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 628 | #define MX53_PAD_EIM_A20__IPU_CSI1_D_15 IOMUX_PAD(0x4B8, 0x16C, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 629 | #define MX53_PAD_EIM_A20__SRC_BT_CFG1_5 IOMUX_PAD(0x4B8, 0x16C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 630 | #define MX53_PAD_EIM_A19__EMI_WEIM_A_19 IOMUX_PAD(0x4BC, 0x170, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 631 | #define MX53_PAD_EIM_A19__GPIO2_19 IOMUX_PAD(0x4BC, 0x170, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 632 | #define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 IOMUX_PAD(0x4BC, 0x170, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 633 | #define MX53_PAD_EIM_A19__IPU_CSI1_D_14 IOMUX_PAD(0x4BC, 0x170, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 634 | #define MX53_PAD_EIM_A19__SRC_BT_CFG1_4 IOMUX_PAD(0x4BC, 0x170, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 635 | #define MX53_PAD_EIM_A18__EMI_WEIM_A_18 IOMUX_PAD(0x4C0, 0x174, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 636 | #define MX53_PAD_EIM_A18__GPIO2_20 IOMUX_PAD(0x4C0, 0x174, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 637 | #define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 IOMUX_PAD(0x4C0, 0x174, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 638 | #define MX53_PAD_EIM_A18__IPU_CSI1_D_13 IOMUX_PAD(0x4C0, 0x174, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 639 | #define MX53_PAD_EIM_A18__SRC_BT_CFG1_3 IOMUX_PAD(0x4C0, 0x174, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 640 | #define MX53_PAD_EIM_A17__EMI_WEIM_A_17 IOMUX_PAD(0x4C4, 0x178, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 641 | #define MX53_PAD_EIM_A17__GPIO2_21 IOMUX_PAD(0x4C4, 0x178, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 642 | #define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 IOMUX_PAD(0x4C4, 0x178, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 643 | #define MX53_PAD_EIM_A17__IPU_CSI1_D_12 IOMUX_PAD(0x4C4, 0x178, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 644 | #define MX53_PAD_EIM_A17__SRC_BT_CFG1_2 IOMUX_PAD(0x4C4, 0x178, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 645 | #define MX53_PAD_EIM_A16__EMI_WEIM_A_16 IOMUX_PAD(0x4C8, 0x17C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 646 | #define MX53_PAD_EIM_A16__GPIO2_22 IOMUX_PAD(0x4C8, 0x17C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 647 | #define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK IOMUX_PAD(0x4C8, 0x17C, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 648 | #define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK IOMUX_PAD(0x4C8, 0x17C, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 649 | #define MX53_PAD_EIM_A16__SRC_BT_CFG1_1 IOMUX_PAD(0x4C8, 0x17C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 650 | #define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 IOMUX_PAD(0x4CC, 0x180, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 651 | #define MX53_PAD_EIM_CS0__GPIO2_23 IOMUX_PAD(0x4CC, 0x180, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 652 | #define MX53_PAD_EIM_CS0__ECSPI2_SCLK IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, NO_PAD_CTRL) | ||
| 653 | #define MX53_PAD_EIM_CS0__IPU_DI1_PIN5 IOMUX_PAD(0x4CC, 0x180, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 654 | #define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 IOMUX_PAD(0x4D0, 0x184, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 655 | #define MX53_PAD_EIM_CS1__GPIO2_24 IOMUX_PAD(0x4D0, 0x184, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 656 | #define MX53_PAD_EIM_CS1__ECSPI2_MOSI IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, NO_PAD_CTRL) | ||
| 657 | #define MX53_PAD_EIM_CS1__IPU_DI1_PIN6 IOMUX_PAD(0x4D0, 0x184, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 658 | #define MX53_PAD_EIM_OE__EMI_WEIM_OE IOMUX_PAD(0x4D4, 0x188, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 659 | #define MX53_PAD_EIM_OE__GPIO2_25 IOMUX_PAD(0x4D4, 0x188, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 660 | #define MX53_PAD_EIM_OE__ECSPI2_MISO IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, NO_PAD_CTRL) | ||
| 661 | #define MX53_PAD_EIM_OE__IPU_DI1_PIN7 IOMUX_PAD(0x4D4, 0x188, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 662 | #define MX53_PAD_EIM_OE__USBPHY2_IDDIG IOMUX_PAD(0x4D4, 0x188, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 663 | #define MX53_PAD_EIM_RW__EMI_WEIM_RW IOMUX_PAD(0x4D8, 0x18C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 664 | #define MX53_PAD_EIM_RW__GPIO2_26 IOMUX_PAD(0x4D8, 0x18C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 665 | #define MX53_PAD_EIM_RW__ECSPI2_SS0 IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, NO_PAD_CTRL) | ||
| 666 | #define MX53_PAD_EIM_RW__IPU_DI1_PIN8 IOMUX_PAD(0x4D8, 0x18C, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 667 | #define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT IOMUX_PAD(0x4D8, 0x18C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 668 | #define MX53_PAD_EIM_LBA__EMI_WEIM_LBA IOMUX_PAD(0x4DC, 0x190, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 669 | #define MX53_PAD_EIM_LBA__GPIO2_27 IOMUX_PAD(0x4DC, 0x190, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 670 | #define MX53_PAD_EIM_LBA__ECSPI2_SS1 IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, NO_PAD_CTRL) | ||
| 671 | #define MX53_PAD_EIM_LBA__IPU_DI1_PIN17 IOMUX_PAD(0x4DC, 0x190, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 672 | #define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 IOMUX_PAD(0x4DC, 0x190, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 673 | #define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 IOMUX_PAD(0x4E4, 0x194, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 674 | #define MX53_PAD_EIM_EB0__GPIO2_28 IOMUX_PAD(0x4E4, 0x194, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 675 | #define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 IOMUX_PAD(0x4E4, 0x194, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 676 | #define MX53_PAD_EIM_EB0__IPU_CSI1_D_11 IOMUX_PAD(0x4E4, 0x194, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 677 | #define MX53_PAD_EIM_EB0__GPC_PMIC_RDY IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, NO_PAD_CTRL) | ||
| 678 | #define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 IOMUX_PAD(0x4E4, 0x194, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 679 | #define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 IOMUX_PAD(0x4E8, 0x198, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 680 | #define MX53_PAD_EIM_EB1__GPIO2_29 IOMUX_PAD(0x4E8, 0x198, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 681 | #define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 IOMUX_PAD(0x4E8, 0x198, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 682 | #define MX53_PAD_EIM_EB1__IPU_CSI1_D_10 IOMUX_PAD(0x4E8, 0x198, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 683 | #define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 IOMUX_PAD(0x4E8, 0x198, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 684 | #define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 IOMUX_PAD(0x4EC, 0x19C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 685 | #define MX53_PAD_EIM_DA0__GPIO3_0 IOMUX_PAD(0x4EC, 0x19C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 686 | #define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 IOMUX_PAD(0x4EC, 0x19C, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 687 | #define MX53_PAD_EIM_DA0__IPU_CSI1_D_9 IOMUX_PAD(0x4EC, 0x19C, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 688 | #define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 IOMUX_PAD(0x4EC, 0x19C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 689 | #define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 IOMUX_PAD(0x4F0, 0x1A0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 690 | #define MX53_PAD_EIM_DA1__GPIO3_1 IOMUX_PAD(0x4F0, 0x1A0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 691 | #define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 IOMUX_PAD(0x4F0, 0x1A0, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 692 | #define MX53_PAD_EIM_DA1__IPU_CSI1_D_8 IOMUX_PAD(0x4F0, 0x1A0, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 693 | #define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 IOMUX_PAD(0x4F0, 0x1A0, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 694 | #define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 IOMUX_PAD(0x4F4, 0x1A4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 695 | #define MX53_PAD_EIM_DA2__GPIO3_2 IOMUX_PAD(0x4F4, 0x1A4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 696 | #define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 IOMUX_PAD(0x4F4, 0x1A4, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 697 | #define MX53_PAD_EIM_DA2__IPU_CSI1_D_7 IOMUX_PAD(0x4F4, 0x1A4, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 698 | #define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 IOMUX_PAD(0x4F4, 0x1A4, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 699 | #define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 IOMUX_PAD(0x4F8, 0x1A8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 700 | #define MX53_PAD_EIM_DA3__GPIO3_3 IOMUX_PAD(0x4F8, 0x1A8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 701 | #define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 IOMUX_PAD(0x4F8, 0x1A8, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 702 | #define MX53_PAD_EIM_DA3__IPU_CSI1_D_6 IOMUX_PAD(0x4F8, 0x1A8, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 703 | #define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 IOMUX_PAD(0x4F8, 0x1A8, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 704 | #define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 IOMUX_PAD(0x4FC, 0x1AC, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 705 | #define MX53_PAD_EIM_DA4__GPIO3_4 IOMUX_PAD(0x4FC, 0x1AC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 706 | #define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 IOMUX_PAD(0x4FC, 0x1AC, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 707 | #define MX53_PAD_EIM_DA4__IPU_CSI1_D_5 IOMUX_PAD(0x4FC, 0x1AC, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 708 | #define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 IOMUX_PAD(0x4FC, 0x1AC, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 709 | #define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 IOMUX_PAD(0x500, 0x1B0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 710 | #define MX53_PAD_EIM_DA5__GPIO3_5 IOMUX_PAD(0x500, 0x1B0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 711 | #define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 IOMUX_PAD(0x500, 0x1B0, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 712 | #define MX53_PAD_EIM_DA5__IPU_CSI1_D_4 IOMUX_PAD(0x500, 0x1B0, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 713 | #define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 IOMUX_PAD(0x500, 0x1B0, 7 | IOMUX_CONFIG_SION, __NA_, 0, NO_PAD_CTRL) | ||
| 714 | #define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 IOMUX_PAD(0x504, 0x1B4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 715 | #define MX53_PAD_EIM_DA6__GPIO3_6 IOMUX_PAD(0x504, 0x1B4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 716 | #define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 IOMUX_PAD(0x504, 0x1B4, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 717 | #define MX53_PAD_EIM_DA6__IPU_CSI1_D_3 IOMUX_PAD(0x504, 0x1B4, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 718 | #define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 IOMUX_PAD(0x504, 0x1B4, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 719 | #define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 IOMUX_PAD(0x508, 0x1B8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 720 | #define MX53_PAD_EIM_DA7__GPIO3_7 IOMUX_PAD(0x508, 0x1B8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 721 | #define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 IOMUX_PAD(0x508, 0x1B8, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 722 | #define MX53_PAD_EIM_DA7__IPU_CSI1_D_2 IOMUX_PAD(0x508, 0x1B8, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 723 | #define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 IOMUX_PAD(0x508, 0x1B8, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 724 | #define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 IOMUX_PAD(0x50C, 0x1BC, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 725 | #define MX53_PAD_EIM_DA8__GPIO3_8 IOMUX_PAD(0x50C, 0x1BC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 726 | #define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 IOMUX_PAD(0x50C, 0x1BC, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 727 | #define MX53_PAD_EIM_DA8__IPU_CSI1_D_1 IOMUX_PAD(0x50C, 0x1BC, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 728 | #define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 IOMUX_PAD(0x50C, 0x1BC, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 729 | #define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 IOMUX_PAD(0x510, 0x1C0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 730 | #define MX53_PAD_EIM_DA9__GPIO3_9 IOMUX_PAD(0x510, 0x1C0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 731 | #define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 IOMUX_PAD(0x510, 0x1C0, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 732 | #define MX53_PAD_EIM_DA9__IPU_CSI1_D_0 IOMUX_PAD(0x510, 0x1C0, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 733 | #define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 IOMUX_PAD(0x510, 0x1C0, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 734 | #define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 IOMUX_PAD(0x514, 0x1C4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 735 | #define MX53_PAD_EIM_DA10__GPIO3_10 IOMUX_PAD(0x514, 0x1C4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 736 | #define MX53_PAD_EIM_DA10__IPU_DI1_PIN15 IOMUX_PAD(0x514, 0x1C4, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 737 | #define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, NO_PAD_CTRL) | ||
| 738 | #define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 IOMUX_PAD(0x514, 0x1C4, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 739 | #define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 IOMUX_PAD(0x518, 0x1C8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 740 | #define MX53_PAD_EIM_DA11__GPIO3_11 IOMUX_PAD(0x518, 0x1C8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 741 | #define MX53_PAD_EIM_DA11__IPU_DI1_PIN2 IOMUX_PAD(0x518, 0x1C8, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 742 | #define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, NO_PAD_CTRL) | ||
| 743 | #define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 IOMUX_PAD(0x51C, 0x1CC, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 744 | #define MX53_PAD_EIM_DA12__GPIO3_12 IOMUX_PAD(0x51C, 0x1CC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 745 | #define MX53_PAD_EIM_DA12__IPU_DI1_PIN3 IOMUX_PAD(0x51C, 0x1CC, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 746 | #define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, NO_PAD_CTRL) | ||
| 747 | #define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 IOMUX_PAD(0x520, 0x1D0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 748 | #define MX53_PAD_EIM_DA13__GPIO3_13 IOMUX_PAD(0x520, 0x1D0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 749 | #define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS IOMUX_PAD(0x520, 0x1D0, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 750 | #define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, NO_PAD_CTRL) | ||
| 751 | #define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 IOMUX_PAD(0x524, 0x1D4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 752 | #define MX53_PAD_EIM_DA14__GPIO3_14 IOMUX_PAD(0x524, 0x1D4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 753 | #define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS IOMUX_PAD(0x524, 0x1D4, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 754 | #define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK IOMUX_PAD(0x524, 0x1D4, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 755 | #define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 IOMUX_PAD(0x528, 0x1D8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 756 | #define MX53_PAD_EIM_DA15__GPIO3_15 IOMUX_PAD(0x528, 0x1D8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 757 | #define MX53_PAD_EIM_DA15__IPU_DI1_PIN1 IOMUX_PAD(0x528, 0x1D8, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 758 | #define MX53_PAD_EIM_DA15__IPU_DI1_PIN4 IOMUX_PAD(0x528, 0x1D8, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 759 | #define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B IOMUX_PAD(0x52C, 0x1DC, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 760 | #define MX53_PAD_NANDF_WE_B__GPIO6_12 IOMUX_PAD(0x52C, 0x1DC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 761 | #define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B IOMUX_PAD(0x530, 0x1E0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 762 | #define MX53_PAD_NANDF_RE_B__GPIO6_13 IOMUX_PAD(0x530, 0x1E0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 763 | #define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT IOMUX_PAD(0x534, 0x1E4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 764 | #define MX53_PAD_EIM_WAIT__GPIO5_0 IOMUX_PAD(0x534, 0x1E4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 765 | #define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B IOMUX_PAD(0x534, 0x1E4, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 766 | #define MX53_PAD_LVDS1_TX3_P__GPIO6_22 IOMUX_PAD(__NA_, 0x1EC, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 767 | #define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 IOMUX_PAD(__NA_, 0x1EC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 768 | #define MX53_PAD_LVDS1_TX2_P__GPIO6_24 IOMUX_PAD(__NA_, 0x1F0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 769 | #define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 IOMUX_PAD(__NA_, 0x1F0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 770 | #define MX53_PAD_LVDS1_CLK_P__GPIO6_26 IOMUX_PAD(__NA_, 0x1F4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 771 | #define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK IOMUX_PAD(__NA_, 0x1F4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 772 | #define MX53_PAD_LVDS1_TX1_P__GPIO6_28 IOMUX_PAD(__NA_, 0x1F8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 773 | #define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 IOMUX_PAD(__NA_, 0x1F8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 774 | #define MX53_PAD_LVDS1_TX0_P__GPIO6_30 IOMUX_PAD(__NA_, 0x1FC, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 775 | #define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 IOMUX_PAD(__NA_, 0x1FC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 776 | #define MX53_PAD_LVDS0_TX3_P__GPIO7_22 IOMUX_PAD(__NA_, 0x200, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 777 | #define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 IOMUX_PAD(__NA_, 0x200, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 778 | #define MX53_PAD_LVDS0_CLK_P__GPIO7_24 IOMUX_PAD(__NA_, 0x204, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 779 | #define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK IOMUX_PAD(__NA_, 0x204, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 780 | #define MX53_PAD_LVDS0_TX2_P__GPIO7_26 IOMUX_PAD(__NA_, 0x208, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 781 | #define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 IOMUX_PAD(__NA_, 0x208, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 782 | #define MX53_PAD_LVDS0_TX1_P__GPIO7_28 IOMUX_PAD(__NA_, 0x20C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 783 | #define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 IOMUX_PAD(__NA_, 0x20C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 784 | #define MX53_PAD_LVDS0_TX0_P__GPIO7_30 IOMUX_PAD(__NA_, 0x210, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 785 | #define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 IOMUX_PAD(__NA_, 0x210, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 786 | #define MX53_PAD_GPIO_10__GPIO4_0 IOMUX_PAD(0x540, 0x214, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 787 | #define MX53_PAD_GPIO_10__OSC32k_32K_OUT IOMUX_PAD(0x540, 0x214, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 788 | #define MX53_PAD_GPIO_11__GPIO4_1 IOMUX_PAD(0x544, 0x218, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 789 | #define MX53_PAD_GPIO_12__GPIO4_2 IOMUX_PAD(0x548, 0x21C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 790 | #define MX53_PAD_GPIO_13__GPIO4_3 IOMUX_PAD(0x54C, 0x220, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 791 | #define MX53_PAD_GPIO_14__GPIO4_4 IOMUX_PAD(0x550, 0x224, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 792 | #define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE IOMUX_PAD(0x5A0, 0x228, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 793 | #define MX53_PAD_NANDF_CLE__GPIO6_7 IOMUX_PAD(0x5A0, 0x228, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 794 | #define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 IOMUX_PAD(0x5A0, 0x228, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 795 | #define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE IOMUX_PAD(0x5A4, 0x22C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 796 | #define MX53_PAD_NANDF_ALE__GPIO6_8 IOMUX_PAD(0x5A4, 0x22C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 797 | #define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 IOMUX_PAD(0x5A4, 0x22C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 798 | #define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B IOMUX_PAD(0x5A8, 0x230, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 799 | #define MX53_PAD_NANDF_WP_B__GPIO6_9 IOMUX_PAD(0x5A8, 0x230, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 800 | #define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 IOMUX_PAD(0x5A8, 0x230, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 801 | #define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 IOMUX_PAD(0x5AC, 0x234, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 802 | #define MX53_PAD_NANDF_RB0__GPIO6_10 IOMUX_PAD(0x5AC, 0x234, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 803 | #define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 IOMUX_PAD(0x5AC, 0x234, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 804 | #define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 IOMUX_PAD(0x5B0, 0x238, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 805 | #define MX53_PAD_NANDF_CS0__GPIO6_11 IOMUX_PAD(0x5B0, 0x238, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 806 | #define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 IOMUX_PAD(0x5B0, 0x238, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 807 | #define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 IOMUX_PAD(0x5B4, 0x23C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 808 | #define MX53_PAD_NANDF_CS1__GPIO6_14 IOMUX_PAD(0x5B4, 0x23C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 809 | #define MX53_PAD_NANDF_CS1__MLB_MLBCLK IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, NO_PAD_CTRL) | ||
| 810 | #define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 IOMUX_PAD(0x5B4, 0x23C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 811 | #define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 IOMUX_PAD(0x5B8, 0x240, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 812 | #define MX53_PAD_NANDF_CS2__GPIO6_15 IOMUX_PAD(0x5B8, 0x240, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 813 | #define MX53_PAD_NANDF_CS2__IPU_SISG_0 IOMUX_PAD(0x5B8, 0x240, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 814 | #define MX53_PAD_NANDF_CS2__ESAI1_TX0 IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, NO_PAD_CTRL) | ||
| 815 | #define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE IOMUX_PAD(0x5B8, 0x240, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 816 | #define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK IOMUX_PAD(0x5B8, 0x240, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 817 | #define MX53_PAD_NANDF_CS2__MLB_MLBSIG IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, NO_PAD_CTRL) | ||
| 818 | #define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 IOMUX_PAD(0x5B8, 0x240, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 819 | #define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 IOMUX_PAD(0x5BC, 0x244, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 820 | #define MX53_PAD_NANDF_CS3__GPIO6_16 IOMUX_PAD(0x5BC, 0x244, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 821 | #define MX53_PAD_NANDF_CS3__IPU_SISG_1 IOMUX_PAD(0x5BC, 0x244, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 822 | #define MX53_PAD_NANDF_CS3__ESAI1_TX1 IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, NO_PAD_CTRL) | ||
| 823 | #define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 IOMUX_PAD(0x5BC, 0x244, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 824 | #define MX53_PAD_NANDF_CS3__MLB_MLBDAT IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, NO_PAD_CTRL) | ||
| 825 | #define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 IOMUX_PAD(0x5BC, 0x244, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 826 | #define MX53_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, NO_PAD_CTRL) | ||
| 827 | #define MX53_PAD_FEC_MDIO__GPIO1_22 IOMUX_PAD(0x5C4, 0x248, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 828 | #define MX53_PAD_FEC_MDIO__ESAI1_SCKR IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, NO_PAD_CTRL) | ||
| 829 | #define MX53_PAD_FEC_MDIO__FEC_COL IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, NO_PAD_CTRL) | ||
| 830 | #define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 IOMUX_PAD(0x5C4, 0x248, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 831 | #define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 IOMUX_PAD(0x5C4, 0x248, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 832 | #define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 IOMUX_PAD(0x5C4, 0x248, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 833 | #define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK IOMUX_PAD(0x5C8, 0x24C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 834 | #define MX53_PAD_FEC_REF_CLK__GPIO1_23 IOMUX_PAD(0x5C8, 0x24C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 835 | #define MX53_PAD_FEC_REF_CLK__ESAI1_FSR IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, NO_PAD_CTRL) | ||
| 836 | #define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 IOMUX_PAD(0x5C8, 0x24C, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 837 | #define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 IOMUX_PAD(0x5C8, 0x24C, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 838 | #define MX53_PAD_FEC_RX_ER__FEC_RX_ER IOMUX_PAD(0x5CC, 0x250, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 839 | #define MX53_PAD_FEC_RX_ER__GPIO1_24 IOMUX_PAD(0x5CC, 0x250, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 840 | #define MX53_PAD_FEC_RX_ER__ESAI1_HCKR IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, NO_PAD_CTRL) | ||
| 841 | #define MX53_PAD_FEC_RX_ER__FEC_RX_CLK IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, NO_PAD_CTRL) | ||
| 842 | #define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 IOMUX_PAD(0x5CC, 0x250, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 843 | #define MX53_PAD_FEC_CRS_DV__FEC_RX_DV IOMUX_PAD(0x5D0, 0x254, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 844 | #define MX53_PAD_FEC_CRS_DV__GPIO1_25 IOMUX_PAD(0x5D0, 0x254, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 845 | #define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, NO_PAD_CTRL) | ||
| 846 | #define MX53_PAD_FEC_RXD1__FEC_RDATA_1 IOMUX_PAD(0x5D4, 0x258, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 847 | #define MX53_PAD_FEC_RXD1__GPIO1_26 IOMUX_PAD(0x5D4, 0x258, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 848 | #define MX53_PAD_FEC_RXD1__ESAI1_FST IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, NO_PAD_CTRL) | ||
| 849 | #define MX53_PAD_FEC_RXD1__MLB_MLBSIG IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, NO_PAD_CTRL) | ||
| 850 | #define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 IOMUX_PAD(0x5D4, 0x258, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 851 | #define MX53_PAD_FEC_RXD0__FEC_RDATA_0 IOMUX_PAD(0x5D8, 0x25C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 852 | #define MX53_PAD_FEC_RXD0__GPIO1_27 IOMUX_PAD(0x5D8, 0x25C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 853 | #define MX53_PAD_FEC_RXD0__ESAI1_HCKT IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, NO_PAD_CTRL) | ||
| 854 | #define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT IOMUX_PAD(0x5D8, 0x25C, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 855 | #define MX53_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x5DC, 0x260, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 856 | #define MX53_PAD_FEC_TX_EN__GPIO1_28 IOMUX_PAD(0x5DC, 0x260, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 857 | #define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, NO_PAD_CTRL) | ||
| 858 | #define MX53_PAD_FEC_TXD1__FEC_TDATA_1 IOMUX_PAD(0x5E0, 0x264, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 859 | #define MX53_PAD_FEC_TXD1__GPIO1_29 IOMUX_PAD(0x5E0, 0x264, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 860 | #define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, NO_PAD_CTRL) | ||
| 861 | #define MX53_PAD_FEC_TXD1__MLB_MLBCLK IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, NO_PAD_CTRL) | ||
| 862 | #define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK IOMUX_PAD(0x5E0, 0x264, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 863 | #define MX53_PAD_FEC_TXD0__FEC_TDATA_0 IOMUX_PAD(0x5E4, 0x268, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 864 | #define MX53_PAD_FEC_TXD0__GPIO1_30 IOMUX_PAD(0x5E4, 0x268, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 865 | #define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, NO_PAD_CTRL) | ||
| 866 | #define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 IOMUX_PAD(0x5E4, 0x268, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 867 | #define MX53_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x5E8, 0x26C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 868 | #define MX53_PAD_FEC_MDC__GPIO1_31 IOMUX_PAD(0x5E8, 0x26C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 869 | #define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, NO_PAD_CTRL) | ||
| 870 | #define MX53_PAD_FEC_MDC__MLB_MLBDAT IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, NO_PAD_CTRL) | ||
| 871 | #define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG IOMUX_PAD(0x5E8, 0x26C, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 872 | #define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 IOMUX_PAD(0x5E8, 0x26C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 873 | #define MX53_PAD_PATA_DIOW__PATA_DIOW IOMUX_PAD(0x5F0, 0x270, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 874 | #define MX53_PAD_PATA_DIOW__GPIO6_17 IOMUX_PAD(0x5F0, 0x270, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 875 | #define MX53_PAD_PATA_DIOW__UART1_TXD_MUX IOMUX_PAD(0x5F0, 0x270, 3, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 876 | #define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 IOMUX_PAD(0x5F0, 0x270, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 877 | #define MX53_PAD_PATA_DMACK__PATA_DMACK IOMUX_PAD(0x5F4, 0x274, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 878 | #define MX53_PAD_PATA_DMACK__GPIO6_18 IOMUX_PAD(0x5F4, 0x274, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 879 | #define MX53_PAD_PATA_DMACK__UART1_RXD_MUX IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, MX53_UART_PAD_CTRL) | ||
| 880 | #define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 IOMUX_PAD(0x5F4, 0x274, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 881 | #define MX53_PAD_PATA_DMARQ__PATA_DMARQ IOMUX_PAD(0x5F8, 0x278, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 882 | #define MX53_PAD_PATA_DMARQ__GPIO7_0 IOMUX_PAD(0x5F8, 0x278, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 883 | #define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX IOMUX_PAD(0x5F8, 0x278, 3, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 884 | #define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 IOMUX_PAD(0x5F8, 0x278, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 885 | #define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 IOMUX_PAD(0x5F8, 0x278, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 886 | #define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN IOMUX_PAD(0x5FC, 0x27C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 887 | #define MX53_PAD_PATA_BUFFER_EN__GPIO7_1 IOMUX_PAD(0x5FC, 0x27C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 888 | #define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL) | ||
| 889 | #define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 IOMUX_PAD(0x5FC, 0x27C, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 890 | #define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 IOMUX_PAD(0x5FC, 0x27C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 891 | #define MX53_PAD_PATA_INTRQ__PATA_INTRQ IOMUX_PAD(0x600, 0x280, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 892 | #define MX53_PAD_PATA_INTRQ__GPIO7_2 IOMUX_PAD(0x600, 0x280, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 893 | #define MX53_PAD_PATA_INTRQ__UART2_CTS IOMUX_PAD(0x600, 0x280, 3, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 894 | #define MX53_PAD_PATA_INTRQ__CAN1_TXCAN IOMUX_PAD(0x600, 0x280, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 895 | #define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 IOMUX_PAD(0x600, 0x280, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 896 | #define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 IOMUX_PAD(0x600, 0x280, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 897 | #define MX53_PAD_PATA_DIOR__PATA_DIOR IOMUX_PAD(0x604, 0x284, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 898 | #define MX53_PAD_PATA_DIOR__GPIO7_3 IOMUX_PAD(0x604, 0x284, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 899 | #define MX53_PAD_PATA_DIOR__UART2_RTS IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL) | ||
| 900 | #define MX53_PAD_PATA_DIOR__CAN1_RXCAN IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, NO_PAD_CTRL) | ||
| 901 | #define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 IOMUX_PAD(0x604, 0x284, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 902 | #define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B IOMUX_PAD(0x608, 0x288, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 903 | #define MX53_PAD_PATA_RESET_B__GPIO7_4 IOMUX_PAD(0x608, 0x288, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 904 | #define MX53_PAD_PATA_RESET_B__ESDHC3_CMD IOMUX_PAD(0x608, 0x288, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 905 | #define MX53_PAD_PATA_RESET_B__UART1_CTS IOMUX_PAD(0x608, 0x288, 3, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 906 | #define MX53_PAD_PATA_RESET_B__CAN2_TXCAN IOMUX_PAD(0x608, 0x288, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 907 | #define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 IOMUX_PAD(0x608, 0x288, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 908 | #define MX53_PAD_PATA_IORDY__PATA_IORDY IOMUX_PAD(0x60C, 0x28C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 909 | #define MX53_PAD_PATA_IORDY__GPIO7_5 IOMUX_PAD(0x60C, 0x28C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 910 | #define MX53_PAD_PATA_IORDY__ESDHC3_CLK IOMUX_PAD(0x60C, 0x28C, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 911 | #define MX53_PAD_PATA_IORDY__UART1_RTS IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, MX53_UART_PAD_CTRL) | ||
| 912 | #define MX53_PAD_PATA_IORDY__CAN2_RXCAN IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, NO_PAD_CTRL) | ||
| 913 | #define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 IOMUX_PAD(0x60C, 0x28C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 914 | #define MX53_PAD_PATA_DA_0__PATA_DA_0 IOMUX_PAD(0x610, 0x290, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 915 | #define MX53_PAD_PATA_DA_0__GPIO7_6 IOMUX_PAD(0x610, 0x290, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 916 | #define MX53_PAD_PATA_DA_0__ESDHC3_RST IOMUX_PAD(0x610, 0x290, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 917 | #define MX53_PAD_PATA_DA_0__OWIRE_LINE IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, NO_PAD_CTRL) | ||
| 918 | #define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 IOMUX_PAD(0x610, 0x290, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 919 | #define MX53_PAD_PATA_DA_1__PATA_DA_1 IOMUX_PAD(0x614, 0x294, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 920 | #define MX53_PAD_PATA_DA_1__GPIO7_7 IOMUX_PAD(0x614, 0x294, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 921 | #define MX53_PAD_PATA_DA_1__ESDHC4_CMD IOMUX_PAD(0x614, 0x294, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 922 | #define MX53_PAD_PATA_DA_1__UART3_CTS IOMUX_PAD(0x614, 0x294, 4, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 923 | #define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 IOMUX_PAD(0x614, 0x294, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 924 | #define MX53_PAD_PATA_DA_2__PATA_DA_2 IOMUX_PAD(0x618, 0x298, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 925 | #define MX53_PAD_PATA_DA_2__GPIO7_8 IOMUX_PAD(0x618, 0x298, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 926 | #define MX53_PAD_PATA_DA_2__ESDHC4_CLK IOMUX_PAD(0x618, 0x298, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 927 | #define MX53_PAD_PATA_DA_2__UART3_RTS IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL) | ||
| 928 | #define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 IOMUX_PAD(0x618, 0x298, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 929 | #define MX53_PAD_PATA_CS_0__PATA_CS_0 IOMUX_PAD(0x61C, 0x29C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 930 | #define MX53_PAD_PATA_CS_0__GPIO7_9 IOMUX_PAD(0x61C, 0x29C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 931 | #define MX53_PAD_PATA_CS_0__UART3_TXD_MUX IOMUX_PAD(0x61C, 0x29C, 4, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 932 | #define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 IOMUX_PAD(0x61C, 0x29C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 933 | #define MX53_PAD_PATA_CS_1__PATA_CS_1 IOMUX_PAD(0x620, 0x2A0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 934 | #define MX53_PAD_PATA_CS_1__GPIO7_10 IOMUX_PAD(0x620, 0x2A0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 935 | #define MX53_PAD_PATA_CS_1__UART3_RXD_MUX IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL) | ||
| 936 | #define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 IOMUX_PAD(0x620, 0x2A0, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 937 | #define MX53_PAD_PATA_DATA0__PATA_DATA_0 IOMUX_PAD(0x628, 0x2A4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 938 | #define MX53_PAD_PATA_DATA0__GPIO2_0 IOMUX_PAD(0x628, 0x2A4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 939 | #define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 IOMUX_PAD(0x628, 0x2A4, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 940 | #define MX53_PAD_PATA_DATA0__ESDHC3_DAT4 IOMUX_PAD(0x628, 0x2A4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 941 | #define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 IOMUX_PAD(0x628, 0x2A4, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 942 | #define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 IOMUX_PAD(0x628, 0x2A4, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 943 | #define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 IOMUX_PAD(0x628, 0x2A4, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 944 | #define MX53_PAD_PATA_DATA1__PATA_DATA_1 IOMUX_PAD(0x62C, 0x2A8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 945 | #define MX53_PAD_PATA_DATA1__GPIO2_1 IOMUX_PAD(0x62C, 0x2A8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 946 | #define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 IOMUX_PAD(0x62C, 0x2A8, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 947 | #define MX53_PAD_PATA_DATA1__ESDHC3_DAT5 IOMUX_PAD(0x62C, 0x2A8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 948 | #define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 IOMUX_PAD(0x62C, 0x2A8, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 949 | #define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 IOMUX_PAD(0x62C, 0x2A8, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 950 | #define MX53_PAD_PATA_DATA2__PATA_DATA_2 IOMUX_PAD(0x630, 0x2AC, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 951 | #define MX53_PAD_PATA_DATA2__GPIO2_2 IOMUX_PAD(0x630, 0x2AC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 952 | #define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 IOMUX_PAD(0x630, 0x2AC, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 953 | #define MX53_PAD_PATA_DATA2__ESDHC3_DAT6 IOMUX_PAD(0x630, 0x2AC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 954 | #define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 IOMUX_PAD(0x630, 0x2AC, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 955 | #define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 IOMUX_PAD(0x630, 0x2AC, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 956 | #define MX53_PAD_PATA_DATA3__PATA_DATA_3 IOMUX_PAD(0x634, 0x2B0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 957 | #define MX53_PAD_PATA_DATA3__GPIO2_3 IOMUX_PAD(0x634, 0x2B0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 958 | #define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 IOMUX_PAD(0x634, 0x2B0, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 959 | #define MX53_PAD_PATA_DATA3__ESDHC3_DAT7 IOMUX_PAD(0x634, 0x2B0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 960 | #define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 IOMUX_PAD(0x634, 0x2B0, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 961 | #define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 IOMUX_PAD(0x634, 0x2B0, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 962 | #define MX53_PAD_PATA_DATA4__PATA_DATA_4 IOMUX_PAD(0x638, 0x2B4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 963 | #define MX53_PAD_PATA_DATA4__GPIO2_4 IOMUX_PAD(0x638, 0x2B4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 964 | #define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 IOMUX_PAD(0x638, 0x2B4, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 965 | #define MX53_PAD_PATA_DATA4__ESDHC4_DAT4 IOMUX_PAD(0x638, 0x2B4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 966 | #define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 IOMUX_PAD(0x638, 0x2B4, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 967 | #define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 IOMUX_PAD(0x638, 0x2B4, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 968 | #define MX53_PAD_PATA_DATA5__PATA_DATA_5 IOMUX_PAD(0x63C, 0x2B8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 969 | #define MX53_PAD_PATA_DATA5__GPIO2_5 IOMUX_PAD(0x63C, 0x2B8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 970 | #define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 IOMUX_PAD(0x63C, 0x2B8, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 971 | #define MX53_PAD_PATA_DATA5__ESDHC4_DAT5 IOMUX_PAD(0x63C, 0x2B8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 972 | #define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 IOMUX_PAD(0x63C, 0x2B8, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 973 | #define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 IOMUX_PAD(0x63C, 0x2B8, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 974 | #define MX53_PAD_PATA_DATA6__PATA_DATA_6 IOMUX_PAD(0x640, 0x2BC, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 975 | #define MX53_PAD_PATA_DATA6__GPIO2_6 IOMUX_PAD(0x640, 0x2BC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 976 | #define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 IOMUX_PAD(0x640, 0x2BC, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 977 | #define MX53_PAD_PATA_DATA6__ESDHC4_DAT6 IOMUX_PAD(0x640, 0x2BC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 978 | #define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 IOMUX_PAD(0x640, 0x2BC, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 979 | #define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 IOMUX_PAD(0x640, 0x2BC, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 980 | #define MX53_PAD_PATA_DATA7__PATA_DATA_7 IOMUX_PAD(0x644, 0x2C0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 981 | #define MX53_PAD_PATA_DATA7__GPIO2_7 IOMUX_PAD(0x644, 0x2C0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 982 | #define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 IOMUX_PAD(0x644, 0x2C0, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 983 | #define MX53_PAD_PATA_DATA7__ESDHC4_DAT7 IOMUX_PAD(0x644, 0x2C0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 984 | #define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 IOMUX_PAD(0x644, 0x2C0, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 985 | #define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 IOMUX_PAD(0x644, 0x2C0, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 986 | #define MX53_PAD_PATA_DATA8__PATA_DATA_8 IOMUX_PAD(0x648, 0x2C4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 987 | #define MX53_PAD_PATA_DATA8__GPIO2_8 IOMUX_PAD(0x648, 0x2C4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 988 | #define MX53_PAD_PATA_DATA8__ESDHC1_DAT4 IOMUX_PAD(0x648, 0x2C4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 989 | #define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 IOMUX_PAD(0x648, 0x2C4, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 990 | #define MX53_PAD_PATA_DATA8__ESDHC3_DAT0 IOMUX_PAD(0x648, 0x2C4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 991 | #define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 IOMUX_PAD(0x648, 0x2C4, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 992 | #define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 IOMUX_PAD(0x648, 0x2C4, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 993 | #define MX53_PAD_PATA_DATA9__PATA_DATA_9 IOMUX_PAD(0x64C, 0x2C8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 994 | #define MX53_PAD_PATA_DATA9__GPIO2_9 IOMUX_PAD(0x64C, 0x2C8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 995 | #define MX53_PAD_PATA_DATA9__ESDHC1_DAT5 IOMUX_PAD(0x64C, 0x2C8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 996 | #define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 IOMUX_PAD(0x64C, 0x2C8, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 997 | #define MX53_PAD_PATA_DATA9__ESDHC3_DAT1 IOMUX_PAD(0x64C, 0x2C8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 998 | #define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 IOMUX_PAD(0x64C, 0x2C8, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 999 | #define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 IOMUX_PAD(0x64C, 0x2C8, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1000 | #define MX53_PAD_PATA_DATA10__PATA_DATA_10 IOMUX_PAD(0x650, 0x2CC, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 1001 | #define MX53_PAD_PATA_DATA10__GPIO2_10 IOMUX_PAD(0x650, 0x2CC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1002 | #define MX53_PAD_PATA_DATA10__ESDHC1_DAT6 IOMUX_PAD(0x650, 0x2CC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1003 | #define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 IOMUX_PAD(0x650, 0x2CC, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1004 | #define MX53_PAD_PATA_DATA10__ESDHC3_DAT2 IOMUX_PAD(0x650, 0x2CC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1005 | #define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 IOMUX_PAD(0x650, 0x2CC, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1006 | #define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 IOMUX_PAD(0x650, 0x2CC, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1007 | #define MX53_PAD_PATA_DATA11__PATA_DATA_11 IOMUX_PAD(0x654, 0x2D0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 1008 | #define MX53_PAD_PATA_DATA11__GPIO2_11 IOMUX_PAD(0x654, 0x2D0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1009 | #define MX53_PAD_PATA_DATA11__ESDHC1_DAT7 IOMUX_PAD(0x654, 0x2D0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1010 | #define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 IOMUX_PAD(0x654, 0x2D0, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1011 | #define MX53_PAD_PATA_DATA11__ESDHC3_DAT3 IOMUX_PAD(0x654, 0x2D0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1012 | #define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 IOMUX_PAD(0x654, 0x2D0, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1013 | #define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 IOMUX_PAD(0x654, 0x2D0, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1014 | #define MX53_PAD_PATA_DATA12__PATA_DATA_12 IOMUX_PAD(0x658, 0x2D4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 1015 | #define MX53_PAD_PATA_DATA12__GPIO2_12 IOMUX_PAD(0x658, 0x2D4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1016 | #define MX53_PAD_PATA_DATA12__ESDHC2_DAT4 IOMUX_PAD(0x658, 0x2D4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1017 | #define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 IOMUX_PAD(0x658, 0x2D4, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1018 | #define MX53_PAD_PATA_DATA12__ESDHC4_DAT0 IOMUX_PAD(0x658, 0x2D4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1019 | #define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 IOMUX_PAD(0x658, 0x2D4, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1020 | #define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 IOMUX_PAD(0x658, 0x2D4, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1021 | #define MX53_PAD_PATA_DATA13__PATA_DATA_13 IOMUX_PAD(0x65C, 0x2D8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 1022 | #define MX53_PAD_PATA_DATA13__GPIO2_13 IOMUX_PAD(0x65C, 0x2D8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1023 | #define MX53_PAD_PATA_DATA13__ESDHC2_DAT5 IOMUX_PAD(0x65C, 0x2D8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1024 | #define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 IOMUX_PAD(0x65C, 0x2D8, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1025 | #define MX53_PAD_PATA_DATA13__ESDHC4_DAT1 IOMUX_PAD(0x65C, 0x2D8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1026 | #define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 IOMUX_PAD(0x65C, 0x2D8, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1027 | #define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 IOMUX_PAD(0x65C, 0x2D8, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1028 | #define MX53_PAD_PATA_DATA14__PATA_DATA_14 IOMUX_PAD(0x660, 0x2DC, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 1029 | #define MX53_PAD_PATA_DATA14__GPIO2_14 IOMUX_PAD(0x660, 0x2DC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1030 | #define MX53_PAD_PATA_DATA14__ESDHC2_DAT6 IOMUX_PAD(0x660, 0x2DC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1031 | #define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 IOMUX_PAD(0x660, 0x2DC, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1032 | #define MX53_PAD_PATA_DATA14__ESDHC4_DAT2 IOMUX_PAD(0x660, 0x2DC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1033 | #define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 IOMUX_PAD(0x660, 0x2DC, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1034 | #define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 IOMUX_PAD(0x660, 0x2DC, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1035 | #define MX53_PAD_PATA_DATA15__PATA_DATA_15 IOMUX_PAD(0x664, 0x2E0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 1036 | #define MX53_PAD_PATA_DATA15__GPIO2_15 IOMUX_PAD(0x664, 0x2E0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1037 | #define MX53_PAD_PATA_DATA15__ESDHC2_DAT7 IOMUX_PAD(0x664, 0x2E0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1038 | #define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 IOMUX_PAD(0x664, 0x2E0, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1039 | #define MX53_PAD_PATA_DATA15__ESDHC4_DAT3 IOMUX_PAD(0x664, 0x2E0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1040 | #define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 IOMUX_PAD(0x664, 0x2E0, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1041 | #define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 IOMUX_PAD(0x664, 0x2E0, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1042 | #define MX53_PAD_SD1_DATA0__ESDHC1_DAT0 IOMUX_PAD(0x66C, 0x2E4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1043 | #define MX53_PAD_SD1_DATA0__GPIO1_16 IOMUX_PAD(0x66C, 0x2E4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1044 | #define MX53_PAD_SD1_DATA0__GPT_CAPIN1 IOMUX_PAD(0x66C, 0x2E4, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1045 | #define MX53_PAD_SD1_DATA0__CSPI_MISO IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, NO_PAD_CTRL) | ||
| 1046 | #define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, NO_PAD_CTRL) | ||
| 1047 | #define MX53_PAD_SD1_DATA1__ESDHC1_DAT1 IOMUX_PAD(0x670, 0x2E8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1048 | #define MX53_PAD_SD1_DATA1__GPIO1_17 IOMUX_PAD(0x670, 0x2E8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1049 | #define MX53_PAD_SD1_DATA1__GPT_CAPIN2 IOMUX_PAD(0x670, 0x2E8, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1050 | #define MX53_PAD_SD1_DATA1__CSPI_SS0 IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, NO_PAD_CTRL) | ||
| 1051 | #define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, NO_PAD_CTRL) | ||
| 1052 | #define MX53_PAD_SD1_CMD__ESDHC1_CMD IOMUX_PAD(0x674, 0x2EC, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1053 | #define MX53_PAD_SD1_CMD__GPIO1_18 IOMUX_PAD(0x674, 0x2EC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1054 | #define MX53_PAD_SD1_CMD__GPT_CMPOUT1 IOMUX_PAD(0x674, 0x2EC, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1055 | #define MX53_PAD_SD1_CMD__CSPI_MOSI IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, NO_PAD_CTRL) | ||
| 1056 | #define MX53_PAD_SD1_CMD__CCM_PLL1_BYP IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, NO_PAD_CTRL) | ||
| 1057 | #define MX53_PAD_SD1_DATA2__ESDHC1_DAT2 IOMUX_PAD(0x678, 0x2F0, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1058 | #define MX53_PAD_SD1_DATA2__GPIO1_19 IOMUX_PAD(0x678, 0x2F0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1059 | #define MX53_PAD_SD1_DATA2__GPT_CMPOUT2 IOMUX_PAD(0x678, 0x2F0, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 1060 | #define MX53_PAD_SD1_DATA2__PWM2_PWMO IOMUX_PAD(0x678, 0x2F0, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1061 | #define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B IOMUX_PAD(0x678, 0x2F0, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 1062 | #define MX53_PAD_SD1_DATA2__CSPI_SS1 IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, NO_PAD_CTRL) | ||
| 1063 | #define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB IOMUX_PAD(0x678, 0x2F0, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1064 | #define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, NO_PAD_CTRL) | ||
| 1065 | #define MX53_PAD_SD1_CLK__ESDHC1_CLK IOMUX_PAD(0x67C, 0x2F4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1066 | #define MX53_PAD_SD1_CLK__GPIO1_20 IOMUX_PAD(0x67C, 0x2F4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1067 | #define MX53_PAD_SD1_CLK__OSC32k_32K_OUT IOMUX_PAD(0x67C, 0x2F4, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 1068 | #define MX53_PAD_SD1_CLK__GPT_CLKIN IOMUX_PAD(0x67C, 0x2F4, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1069 | #define MX53_PAD_SD1_CLK__CSPI_SCLK IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, NO_PAD_CTRL) | ||
| 1070 | #define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 IOMUX_PAD(0x67C, 0x2F4, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 1071 | #define MX53_PAD_SD1_DATA3__ESDHC1_DAT3 IOMUX_PAD(0x680, 0x2F8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1072 | #define MX53_PAD_SD1_DATA3__GPIO1_21 IOMUX_PAD(0x680, 0x2F8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1073 | #define MX53_PAD_SD1_DATA3__GPT_CMPOUT3 IOMUX_PAD(0x680, 0x2F8, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 1074 | #define MX53_PAD_SD1_DATA3__PWM1_PWMO IOMUX_PAD(0x680, 0x2F8, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1075 | #define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B IOMUX_PAD(0x680, 0x2F8, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 1076 | #define MX53_PAD_SD1_DATA3__CSPI_SS2 IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, NO_PAD_CTRL) | ||
| 1077 | #define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB IOMUX_PAD(0x680, 0x2F8, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1078 | #define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 IOMUX_PAD(0x680, 0x2F8, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 1079 | #define MX53_PAD_SD2_CLK__ESDHC2_CLK IOMUX_PAD(0x688, 0x2FC, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1080 | #define MX53_PAD_SD2_CLK__GPIO1_10 IOMUX_PAD(0x688, 0x2FC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1081 | #define MX53_PAD_SD2_CLK__KPP_COL_5 IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, NO_PAD_CTRL) | ||
| 1082 | #define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, NO_PAD_CTRL) | ||
| 1083 | #define MX53_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, NO_PAD_CTRL) | ||
| 1084 | #define MX53_PAD_SD2_CLK__SCC_RANDOM_V IOMUX_PAD(0x688, 0x2FC, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 1085 | #define MX53_PAD_SD2_CMD__ESDHC2_CMD IOMUX_PAD(0x68C, 0x300, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1086 | #define MX53_PAD_SD2_CMD__GPIO1_11 IOMUX_PAD(0x68C, 0x300, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1087 | #define MX53_PAD_SD2_CMD__KPP_ROW_5 IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, NO_PAD_CTRL) | ||
| 1088 | #define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, NO_PAD_CTRL) | ||
| 1089 | #define MX53_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, NO_PAD_CTRL) | ||
| 1090 | #define MX53_PAD_SD2_CMD__SCC_RANDOM IOMUX_PAD(0x68C, 0x300, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 1091 | #define MX53_PAD_SD2_DATA3__ESDHC2_DAT3 IOMUX_PAD(0x690, 0x304, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1092 | #define MX53_PAD_SD2_DATA3__GPIO1_12 IOMUX_PAD(0x690, 0x304, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1093 | #define MX53_PAD_SD2_DATA3__KPP_COL_6 IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, NO_PAD_CTRL) | ||
| 1094 | #define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, NO_PAD_CTRL) | ||
| 1095 | #define MX53_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, NO_PAD_CTRL) | ||
| 1096 | #define MX53_PAD_SD2_DATA3__SJC_DONE IOMUX_PAD(0x690, 0x304, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 1097 | #define MX53_PAD_SD2_DATA2__ESDHC2_DAT2 IOMUX_PAD(0x694, 0x308, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1098 | #define MX53_PAD_SD2_DATA2__GPIO1_13 IOMUX_PAD(0x694, 0x308, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1099 | #define MX53_PAD_SD2_DATA2__KPP_ROW_6 IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, NO_PAD_CTRL) | ||
| 1100 | #define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, NO_PAD_CTRL) | ||
| 1101 | #define MX53_PAD_SD2_DATA2__CSPI_SS1 IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, NO_PAD_CTRL) | ||
| 1102 | #define MX53_PAD_SD2_DATA2__SJC_FAIL IOMUX_PAD(0x694, 0x308, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 1103 | #define MX53_PAD_SD2_DATA1__ESDHC2_DAT1 IOMUX_PAD(0x698, 0x30C, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1104 | #define MX53_PAD_SD2_DATA1__GPIO1_14 IOMUX_PAD(0x698, 0x30C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1105 | #define MX53_PAD_SD2_DATA1__KPP_COL_7 IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, NO_PAD_CTRL) | ||
| 1106 | #define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, NO_PAD_CTRL) | ||
| 1107 | #define MX53_PAD_SD2_DATA1__CSPI_SS0 IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, NO_PAD_CTRL) | ||
| 1108 | #define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO IOMUX_PAD(0x698, 0x30C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 1109 | #define MX53_PAD_SD2_DATA0__ESDHC2_DAT0 IOMUX_PAD(0x69C, 0x310, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1110 | #define MX53_PAD_SD2_DATA0__GPIO1_15 IOMUX_PAD(0x69C, 0x310, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1111 | #define MX53_PAD_SD2_DATA0__KPP_ROW_7 IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, NO_PAD_CTRL) | ||
| 1112 | #define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, NO_PAD_CTRL) | ||
| 1113 | #define MX53_PAD_SD2_DATA0__CSPI_MISO IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, NO_PAD_CTRL) | ||
| 1114 | #define MX53_PAD_SD2_DATA0__RTIC_DONE_INT IOMUX_PAD(0x69C, 0x310, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 1115 | #define MX53_PAD_GPIO_0__CCM_CLKO IOMUX_PAD(0x6A4, 0x314, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 1116 | #define MX53_PAD_GPIO_0__GPIO1_0 IOMUX_PAD(0x6A4, 0x314, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1117 | #define MX53_PAD_GPIO_0__KPP_COL_5 IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, NO_PAD_CTRL) | ||
| 1118 | #define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK IOMUX_PAD(0x6A4, 0x314, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1119 | #define MX53_PAD_GPIO_0__EPIT1_EPITO IOMUX_PAD(0x6A4, 0x314, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 1120 | #define MX53_PAD_GPIO_0__SRTC_ALARM_DEB IOMUX_PAD(0x6A4, 0x314, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1121 | #define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR IOMUX_PAD(0x6A4, 0x314, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1122 | #define MX53_PAD_GPIO_0__CSU_TD IOMUX_PAD(0x6A4, 0x314, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 1123 | #define MX53_PAD_GPIO_1__ESAI1_SCKR IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, NO_PAD_CTRL) | ||
| 1124 | #define MX53_PAD_GPIO_1__GPIO1_1 IOMUX_PAD(0x6A8, 0x318, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1125 | #define MX53_PAD_GPIO_1__KPP_ROW_5 IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, NO_PAD_CTRL) | ||
| 1126 | #define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK IOMUX_PAD(0x6A8, 0x318, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1127 | #define MX53_PAD_GPIO_1__PWM2_PWMO IOMUX_PAD(0x6A8, 0x318, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 1128 | #define MX53_PAD_GPIO_1__WDOG2_WDOG_B IOMUX_PAD(0x6A8, 0x318, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1129 | #define MX53_PAD_GPIO_1__ESDHC1_CD IOMUX_PAD(0x6A8, 0x318, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1130 | #define MX53_PAD_GPIO_1__SRC_TESTER_ACK IOMUX_PAD(0x6A8, 0x318, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 1131 | #define MX53_PAD_GPIO_9__ESAI1_FSR IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, NO_PAD_CTRL) | ||
| 1132 | #define MX53_PAD_GPIO_9__GPIO1_9 IOMUX_PAD(0x6AC, 0x31C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1133 | #define MX53_PAD_GPIO_9__KPP_COL_6 IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, NO_PAD_CTRL) | ||
| 1134 | #define MX53_PAD_GPIO_9__CCM_REF_EN_B IOMUX_PAD(0x6AC, 0x31C, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1135 | #define MX53_PAD_GPIO_9__PWM1_PWMO IOMUX_PAD(0x6AC, 0x31C, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 1136 | #define MX53_PAD_GPIO_9__WDOG1_WDOG_B IOMUX_PAD(0x6AC, 0x31C, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1137 | #define MX53_PAD_GPIO_9__ESDHC1_WP IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, NO_PAD_CTRL) | ||
| 1138 | #define MX53_PAD_GPIO_9__SCC_FAIL_STATE IOMUX_PAD(0x6AC, 0x31C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 1139 | #define MX53_PAD_GPIO_3__ESAI1_HCKR IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, NO_PAD_CTRL) | ||
| 1140 | #define MX53_PAD_GPIO_3__GPIO1_3 IOMUX_PAD(0x6B0, 0x320, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1141 | #define MX53_PAD_GPIO_3__I2C3_SCL IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, NO_PAD_CTRL) | ||
| 1142 | #define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN IOMUX_PAD(0x6B0, 0x320, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1143 | #define MX53_PAD_GPIO_3__CCM_CLKO2 IOMUX_PAD(0x6B0, 0x320, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 1144 | #define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 IOMUX_PAD(0x6B0, 0x320, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1145 | #define MX53_PAD_GPIO_3__USBOH3_USBH1_OC IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, NO_PAD_CTRL) | ||
| 1146 | #define MX53_PAD_GPIO_3__MLB_MLBCLK IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, NO_PAD_CTRL) | ||
| 1147 | #define MX53_PAD_GPIO_6__ESAI1_SCKT IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, NO_PAD_CTRL) | ||
| 1148 | #define MX53_PAD_GPIO_6__GPIO1_6 IOMUX_PAD(0x6B4, 0x324, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1149 | #define MX53_PAD_GPIO_6__I2C3_SDA IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, NO_PAD_CTRL) | ||
| 1150 | #define MX53_PAD_GPIO_6__CCM_CCM_OUT_0 IOMUX_PAD(0x6B4, 0x324, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1151 | #define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB IOMUX_PAD(0x6B4, 0x324, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 1152 | #define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 IOMUX_PAD(0x6B4, 0x324, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1153 | #define MX53_PAD_GPIO_6__ESDHC2_LCTL IOMUX_PAD(0x6B4, 0x324, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1154 | #define MX53_PAD_GPIO_6__MLB_MLBSIG IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, NO_PAD_CTRL) | ||
| 1155 | #define MX53_PAD_GPIO_2__ESAI1_FST IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, NO_PAD_CTRL) | ||
| 1156 | #define MX53_PAD_GPIO_2__GPIO1_2 IOMUX_PAD(0x6B8, 0x328, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1157 | #define MX53_PAD_GPIO_2__KPP_ROW_6 IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, NO_PAD_CTRL) | ||
| 1158 | #define MX53_PAD_GPIO_2__CCM_CCM_OUT_1 IOMUX_PAD(0x6B8, 0x328, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1159 | #define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 IOMUX_PAD(0x6B8, 0x328, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 1160 | #define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 IOMUX_PAD(0x6B8, 0x328, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1161 | #define MX53_PAD_GPIO_2__ESDHC2_WP IOMUX_PAD(0x6B8, 0x328, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1162 | #define MX53_PAD_GPIO_2__MLB_MLBDAT IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, NO_PAD_CTRL) | ||
| 1163 | #define MX53_PAD_GPIO_4__ESAI1_HCKT IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, NO_PAD_CTRL) | ||
| 1164 | #define MX53_PAD_GPIO_4__GPIO1_4 IOMUX_PAD(0x6BC, 0x32C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1165 | #define MX53_PAD_GPIO_4__KPP_COL_7 IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, NO_PAD_CTRL) | ||
| 1166 | #define MX53_PAD_GPIO_4__CCM_CCM_OUT_2 IOMUX_PAD(0x6BC, 0x32C, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1167 | #define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 IOMUX_PAD(0x6BC, 0x32C, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 1168 | #define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 IOMUX_PAD(0x6BC, 0x32C, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1169 | #define MX53_PAD_GPIO_4__ESDHC2_CD IOMUX_PAD(0x6BC, 0x32C, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1170 | #define MX53_PAD_GPIO_4__SCC_SEC_STATE IOMUX_PAD(0x6BC, 0x32C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 1171 | #define MX53_PAD_GPIO_5__ESAI1_TX2_RX3 IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, NO_PAD_CTRL) | ||
| 1172 | #define MX53_PAD_GPIO_5__GPIO1_5 IOMUX_PAD(0x6C0, 0x330, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1173 | #define MX53_PAD_GPIO_5__KPP_ROW_7 IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, NO_PAD_CTRL) | ||
| 1174 | #define MX53_PAD_GPIO_5__CCM_CLKO IOMUX_PAD(0x6C0, 0x330, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1175 | #define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 IOMUX_PAD(0x6C0, 0x330, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 1176 | #define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 IOMUX_PAD(0x6C0, 0x330, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1177 | #define MX53_PAD_GPIO_5__I2C3_SCL IOMUX_PAD(0x6C0, 0x330, 6 | IOMUX_CONFIG_SION, 0x824, 2, NO_PAD_CTRL) | ||
| 1178 | #define MX53_PAD_GPIO_5__CCM_PLL1_BYP IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, NO_PAD_CTRL) | ||
| 1179 | #define MX53_PAD_GPIO_7__ESAI1_TX4_RX1 IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, NO_PAD_CTRL) | ||
| 1180 | #define MX53_PAD_GPIO_7__GPIO1_7 IOMUX_PAD(0x6C4, 0x334, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1181 | #define MX53_PAD_GPIO_7__EPIT1_EPITO IOMUX_PAD(0x6C4, 0x334, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 1182 | #define MX53_PAD_GPIO_7__CAN1_TXCAN IOMUX_PAD(0x6C4, 0x334, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1183 | #define MX53_PAD_GPIO_7__UART2_TXD_MUX IOMUX_PAD(0x6C4, 0x334, 4, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 1184 | #define MX53_PAD_GPIO_7__FIRI_RXD IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, NO_PAD_CTRL) | ||
| 1185 | #define MX53_PAD_GPIO_7__SPDIF_PLOCK IOMUX_PAD(0x6C4, 0x334, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1186 | #define MX53_PAD_GPIO_7__CCM_PLL2_BYP IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, NO_PAD_CTRL) | ||
| 1187 | #define MX53_PAD_GPIO_8__ESAI1_TX5_RX0 IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, NO_PAD_CTRL) | ||
| 1188 | #define MX53_PAD_GPIO_8__GPIO1_8 IOMUX_PAD(0x6C8, 0x338, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1189 | #define MX53_PAD_GPIO_8__EPIT2_EPITO IOMUX_PAD(0x6C8, 0x338, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 1190 | #define MX53_PAD_GPIO_8__CAN1_RXCAN IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 2, NO_PAD_CTRL) | ||
| 1191 | #define MX53_PAD_GPIO_8__UART2_RXD_MUX IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, MX53_UART_PAD_CTRL) | ||
| 1192 | #define MX53_PAD_GPIO_8__FIRI_TXD IOMUX_PAD(0x6C8, 0x338, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1193 | #define MX53_PAD_GPIO_8__SPDIF_SRCLK IOMUX_PAD(0x6C8, 0x338, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1194 | #define MX53_PAD_GPIO_8__CCM_PLL3_BYP IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, NO_PAD_CTRL) | ||
| 1195 | #define MX53_PAD_GPIO_16__ESAI1_TX3_RX2 IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, NO_PAD_CTRL) | ||
| 1196 | #define MX53_PAD_GPIO_16__GPIO7_11 IOMUX_PAD(0x6CC, 0x33C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1197 | #define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT IOMUX_PAD(0x6CC, 0x33C, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 1198 | #define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 IOMUX_PAD(0x6CC, 0x33C, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 1199 | #define MX53_PAD_GPIO_16__SPDIF_IN1 IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, NO_PAD_CTRL) | ||
| 1200 | #define MX53_PAD_GPIO_16__I2C3_SDA IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, NO_PAD_CTRL) | ||
| 1201 | #define MX53_PAD_GPIO_16__SJC_DE_B IOMUX_PAD(0x6CC, 0x33C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 1202 | #define MX53_PAD_GPIO_17__ESAI1_TX0 IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, NO_PAD_CTRL) | ||
| 1203 | #define MX53_PAD_GPIO_17__GPIO7_12 IOMUX_PAD(0x6D0, 0x340, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1204 | #define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, NO_PAD_CTRL) | ||
| 1205 | #define MX53_PAD_GPIO_17__GPC_PMIC_RDY IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, NO_PAD_CTRL) | ||
| 1206 | #define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG IOMUX_PAD(0x6D0, 0x340, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 1207 | #define MX53_PAD_GPIO_17__SPDIF_OUT1 IOMUX_PAD(0x6D0, 0x340, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1208 | #define MX53_PAD_GPIO_17__IPU_SNOOP2 IOMUX_PAD(0x6D0, 0x340, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1209 | #define MX53_PAD_GPIO_17__SJC_JTAG_ACT IOMUX_PAD(0x6D0, 0x340, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 1210 | #define MX53_PAD_GPIO_18__ESAI1_TX1 IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, NO_PAD_CTRL) | ||
| 1211 | #define MX53_PAD_GPIO_18__GPIO7_13 IOMUX_PAD(0x6D4, 0x344, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1212 | #define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, NO_PAD_CTRL) | ||
| 1213 | #define MX53_PAD_GPIO_18__OWIRE_LINE IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, NO_PAD_CTRL) | ||
| 1214 | #define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG IOMUX_PAD(0x6D4, 0x344, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 1215 | #define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, NO_PAD_CTRL) | ||
| 1216 | #define MX53_PAD_GPIO_18__ESDHC1_LCTL IOMUX_PAD(0x6D4, 0x344, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1217 | #define MX53_PAD_GPIO_18__SRC_SYSTEM_RST IOMUX_PAD(0x6D4, 0x344, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 1218 | |||
| 1219 | #endif /* __MACH_IOMUX_MX53_H__ */ | ||
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 626ad8cad7a9..938b50a33439 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c | |||
| @@ -189,6 +189,7 @@ struct omap_dm_timer *omap_dm_timer_request(void) | |||
| 189 | timer->reserved = 1; | 189 | timer->reserved = 1; |
| 190 | break; | 190 | break; |
| 191 | } | 191 | } |
| 192 | spin_unlock_irqrestore(&dm_timer_lock, flags); | ||
| 192 | 193 | ||
| 193 | if (timer) { | 194 | if (timer) { |
| 194 | ret = omap_dm_timer_prepare(timer); | 195 | ret = omap_dm_timer_prepare(timer); |
| @@ -197,7 +198,6 @@ struct omap_dm_timer *omap_dm_timer_request(void) | |||
| 197 | timer = NULL; | 198 | timer = NULL; |
| 198 | } | 199 | } |
| 199 | } | 200 | } |
| 200 | spin_unlock_irqrestore(&dm_timer_lock, flags); | ||
| 201 | 201 | ||
| 202 | if (!timer) | 202 | if (!timer) |
| 203 | pr_debug("%s: timer request failed!\n", __func__); | 203 | pr_debug("%s: timer request failed!\n", __func__); |
| @@ -220,6 +220,7 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id) | |||
| 220 | break; | 220 | break; |
| 221 | } | 221 | } |
| 222 | } | 222 | } |
| 223 | spin_unlock_irqrestore(&dm_timer_lock, flags); | ||
| 223 | 224 | ||
| 224 | if (timer) { | 225 | if (timer) { |
| 225 | ret = omap_dm_timer_prepare(timer); | 226 | ret = omap_dm_timer_prepare(timer); |
| @@ -228,7 +229,6 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id) | |||
| 228 | timer = NULL; | 229 | timer = NULL; |
| 229 | } | 230 | } |
| 230 | } | 231 | } |
| 231 | spin_unlock_irqrestore(&dm_timer_lock, flags); | ||
| 232 | 232 | ||
| 233 | if (!timer) | 233 | if (!timer) |
| 234 | pr_debug("%s: timer%d request failed!\n", __func__, id); | 234 | pr_debug("%s: timer%d request failed!\n", __func__, id); |
| @@ -258,7 +258,7 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_enable); | |||
| 258 | 258 | ||
| 259 | void omap_dm_timer_disable(struct omap_dm_timer *timer) | 259 | void omap_dm_timer_disable(struct omap_dm_timer *timer) |
| 260 | { | 260 | { |
| 261 | pm_runtime_put(&timer->pdev->dev); | 261 | pm_runtime_put_sync(&timer->pdev->dev); |
| 262 | } | 262 | } |
| 263 | EXPORT_SYMBOL_GPL(omap_dm_timer_disable); | 263 | EXPORT_SYMBOL_GPL(omap_dm_timer_disable); |
| 264 | 264 | ||
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index 68b180edcfff..bb5d08a70dbc 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h | |||
| @@ -372,7 +372,8 @@ IS_OMAP_TYPE(3430, 0x3430) | |||
| 372 | #define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \ | 372 | #define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \ |
| 373 | cpu_is_omap16xx()) | 373 | cpu_is_omap16xx()) |
| 374 | #define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \ | 374 | #define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \ |
| 375 | cpu_is_omap44xx() || soc_is_omap54xx()) | 375 | cpu_is_omap44xx() || soc_is_omap54xx() || \ |
| 376 | soc_is_am33xx()) | ||
| 376 | 377 | ||
| 377 | /* Various silicon revisions for omap2 */ | 378 | /* Various silicon revisions for omap2 */ |
| 378 | #define OMAP242X_CLASS 0x24200024 | 379 | #define OMAP242X_CLASS 0x24200024 |
diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h index 045e320f1067..324d31b14852 100644 --- a/arch/arm/plat-omap/include/plat/multi.h +++ b/arch/arm/plat-omap/include/plat/multi.h | |||
| @@ -108,4 +108,13 @@ | |||
| 108 | # endif | 108 | # endif |
| 109 | #endif | 109 | #endif |
| 110 | 110 | ||
| 111 | #ifdef CONFIG_SOC_AM33XX | ||
| 112 | # ifdef OMAP_NAME | ||
| 113 | # undef MULTI_OMAP2 | ||
| 114 | # define MULTI_OMAP2 | ||
| 115 | # else | ||
| 116 | # define OMAP_NAME am33xx | ||
| 117 | # endif | ||
| 118 | #endif | ||
| 119 | |||
| 111 | #endif /* __PLAT_OMAP_MULTI_H */ | 120 | #endif /* __PLAT_OMAP_MULTI_H */ |
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h index b8d19a136781..7f7b112acccb 100644 --- a/arch/arm/plat-omap/include/plat/uncompress.h +++ b/arch/arm/plat-omap/include/plat/uncompress.h | |||
| @@ -110,7 +110,7 @@ static inline void flush(void) | |||
| 110 | _DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT, \ | 110 | _DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT, \ |
| 111 | AM33XXUART##p) | 111 | AM33XXUART##p) |
| 112 | 112 | ||
| 113 | static inline void __arch_decomp_setup(unsigned long arch_id) | 113 | static inline void arch_decomp_setup(void) |
| 114 | { | 114 | { |
| 115 | int port = 0; | 115 | int port = 0; |
| 116 | 116 | ||
| @@ -198,8 +198,6 @@ static inline void __arch_decomp_setup(unsigned long arch_id) | |||
| 198 | } while (0); | 198 | } while (0); |
| 199 | } | 199 | } |
| 200 | 200 | ||
| 201 | #define arch_decomp_setup() __arch_decomp_setup(arch_id) | ||
| 202 | |||
| 203 | /* | 201 | /* |
| 204 | * nothing to do | 202 | * nothing to do |
| 205 | */ | 203 | */ |
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index d245a87dc014..b8b747a9d360 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c | |||
| @@ -291,10 +291,12 @@ static struct platform_device orion_ge00 = { | |||
| 291 | void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data, | 291 | void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data, |
| 292 | unsigned long mapbase, | 292 | unsigned long mapbase, |
| 293 | unsigned long irq, | 293 | unsigned long irq, |
| 294 | unsigned long irq_err) | 294 | unsigned long irq_err, |
| 295 | unsigned int tx_csum_limit) | ||
| 295 | { | 296 | { |
| 296 | fill_resources(&orion_ge00_shared, orion_ge00_shared_resources, | 297 | fill_resources(&orion_ge00_shared, orion_ge00_shared_resources, |
| 297 | mapbase + 0x2000, SZ_16K - 1, irq_err); | 298 | mapbase + 0x2000, SZ_16K - 1, irq_err); |
| 299 | orion_ge00_shared_data.tx_csum_limit = tx_csum_limit; | ||
| 298 | ge_complete(&orion_ge00_shared_data, | 300 | ge_complete(&orion_ge00_shared_data, |
| 299 | orion_ge00_resources, irq, &orion_ge00_shared, | 301 | orion_ge00_resources, irq, &orion_ge00_shared, |
| 300 | eth_data, &orion_ge00); | 302 | eth_data, &orion_ge00); |
| @@ -343,10 +345,12 @@ static struct platform_device orion_ge01 = { | |||
| 343 | void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data, | 345 | void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data, |
| 344 | unsigned long mapbase, | 346 | unsigned long mapbase, |
| 345 | unsigned long irq, | 347 | unsigned long irq, |
| 346 | unsigned long irq_err) | 348 | unsigned long irq_err, |
| 349 | unsigned int tx_csum_limit) | ||
| 347 | { | 350 | { |
| 348 | fill_resources(&orion_ge01_shared, orion_ge01_shared_resources, | 351 | fill_resources(&orion_ge01_shared, orion_ge01_shared_resources, |
| 349 | mapbase + 0x2000, SZ_16K - 1, irq_err); | 352 | mapbase + 0x2000, SZ_16K - 1, irq_err); |
| 353 | orion_ge01_shared_data.tx_csum_limit = tx_csum_limit; | ||
| 350 | ge_complete(&orion_ge01_shared_data, | 354 | ge_complete(&orion_ge01_shared_data, |
| 351 | orion_ge01_resources, irq, &orion_ge01_shared, | 355 | orion_ge01_resources, irq, &orion_ge01_shared, |
| 352 | eth_data, &orion_ge01); | 356 | eth_data, &orion_ge01); |
diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h index e00fdb213609..ae2377ef63e5 100644 --- a/arch/arm/plat-orion/include/plat/common.h +++ b/arch/arm/plat-orion/include/plat/common.h | |||
| @@ -39,12 +39,14 @@ void __init orion_rtc_init(unsigned long mapbase, | |||
| 39 | void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data, | 39 | void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data, |
| 40 | unsigned long mapbase, | 40 | unsigned long mapbase, |
| 41 | unsigned long irq, | 41 | unsigned long irq, |
| 42 | unsigned long irq_err); | 42 | unsigned long irq_err, |
| 43 | unsigned int tx_csum_limit); | ||
| 43 | 44 | ||
| 44 | void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data, | 45 | void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data, |
| 45 | unsigned long mapbase, | 46 | unsigned long mapbase, |
| 46 | unsigned long irq, | 47 | unsigned long irq, |
| 47 | unsigned long irq_err); | 48 | unsigned long irq_err, |
| 49 | unsigned int tx_csum_limit); | ||
| 48 | 50 | ||
| 49 | void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data, | 51 | void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data, |
| 50 | unsigned long mapbase, | 52 | unsigned long mapbase, |
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c index 28f898f75380..db98e7021f0d 100644 --- a/arch/arm/plat-s3c24xx/dma.c +++ b/arch/arm/plat-s3c24xx/dma.c | |||
| @@ -430,7 +430,7 @@ s3c2410_dma_canload(struct s3c2410_dma_chan *chan) | |||
| 430 | * when necessary. | 430 | * when necessary. |
| 431 | */ | 431 | */ |
| 432 | 432 | ||
| 433 | int s3c2410_dma_enqueue(unsigned int channel, void *id, | 433 | int s3c2410_dma_enqueue(enum dma_ch channel, void *id, |
| 434 | dma_addr_t data, int size) | 434 | dma_addr_t data, int size) |
| 435 | { | 435 | { |
| 436 | struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); | 436 | struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); |
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c index 74e31ce35538..fc49f3dabd76 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/plat-samsung/devs.c | |||
| @@ -32,6 +32,8 @@ | |||
| 32 | #include <linux/platform_data/s3c-hsudc.h> | 32 | #include <linux/platform_data/s3c-hsudc.h> |
| 33 | #include <linux/platform_data/s3c-hsotg.h> | 33 | #include <linux/platform_data/s3c-hsotg.h> |
| 34 | 34 | ||
| 35 | #include <media/s5p_hdmi.h> | ||
| 36 | |||
| 35 | #include <asm/irq.h> | 37 | #include <asm/irq.h> |
| 36 | #include <asm/pmu.h> | 38 | #include <asm/pmu.h> |
| 37 | #include <asm/mach/arch.h> | 39 | #include <asm/mach/arch.h> |
| @@ -748,7 +750,8 @@ void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd) | |||
| 748 | if (!pd) { | 750 | if (!pd) { |
| 749 | pd = &default_i2c_data; | 751 | pd = &default_i2c_data; |
| 750 | 752 | ||
| 751 | if (soc_is_exynos4210()) | 753 | if (soc_is_exynos4210() || |
| 754 | soc_is_exynos4212() || soc_is_exynos4412()) | ||
| 752 | pd->bus_num = 8; | 755 | pd->bus_num = 8; |
| 753 | else if (soc_is_s5pv210()) | 756 | else if (soc_is_s5pv210()) |
| 754 | pd->bus_num = 3; | 757 | pd->bus_num = 3; |
| @@ -759,6 +762,30 @@ void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd) | |||
| 759 | npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), | 762 | npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), |
| 760 | &s5p_device_i2c_hdmiphy); | 763 | &s5p_device_i2c_hdmiphy); |
| 761 | } | 764 | } |
| 765 | |||
| 766 | struct s5p_hdmi_platform_data s5p_hdmi_def_platdata; | ||
| 767 | |||
| 768 | void __init s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info, | ||
| 769 | struct i2c_board_info *mhl_info, int mhl_bus) | ||
| 770 | { | ||
| 771 | struct s5p_hdmi_platform_data *pd = &s5p_hdmi_def_platdata; | ||
| 772 | |||
| 773 | if (soc_is_exynos4210() || | ||
| 774 | soc_is_exynos4212() || soc_is_exynos4412()) | ||
| 775 | pd->hdmiphy_bus = 8; | ||
| 776 | else if (soc_is_s5pv210()) | ||
| 777 | pd->hdmiphy_bus = 3; | ||
| 778 | else | ||
| 779 | pd->hdmiphy_bus = 0; | ||
| 780 | |||
| 781 | pd->hdmiphy_info = hdmiphy_info; | ||
| 782 | pd->mhl_info = mhl_info; | ||
| 783 | pd->mhl_bus = mhl_bus; | ||
| 784 | |||
| 785 | s3c_set_platdata(pd, sizeof(struct s5p_hdmi_platform_data), | ||
| 786 | &s5p_device_hdmi); | ||
| 787 | } | ||
| 788 | |||
| 762 | #endif /* CONFIG_S5P_DEV_I2C_HDMIPHY */ | 789 | #endif /* CONFIG_S5P_DEV_I2C_HDMIPHY */ |
| 763 | 790 | ||
| 764 | /* I2S */ | 791 | /* I2S */ |
diff --git a/arch/arm/plat-samsung/include/plat/hdmi.h b/arch/arm/plat-samsung/include/plat/hdmi.h new file mode 100644 index 000000000000..331d046ac2c5 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/hdmi.h | |||
| @@ -0,0 +1,16 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2012 Samsung Electronics Co.Ltd | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it | ||
| 5 | * under the terms of the GNU General Public License as published by the | ||
| 6 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 7 | * option) any later version. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __PLAT_SAMSUNG_HDMI_H | ||
| 11 | #define __PLAT_SAMSUNG_HDMI_H __FILE__ | ||
| 12 | |||
| 13 | extern void s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info, | ||
| 14 | struct i2c_board_info *mhl_info, int mhl_bus); | ||
| 15 | |||
| 16 | #endif /* __PLAT_SAMSUNG_HDMI_H */ | ||
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c index 64ab65f0fdbc..15070284343e 100644 --- a/arch/arm/plat-samsung/pm.c +++ b/arch/arm/plat-samsung/pm.c | |||
| @@ -74,7 +74,7 @@ unsigned char pm_uart_udivslot; | |||
| 74 | 74 | ||
| 75 | #ifdef CONFIG_SAMSUNG_PM_DEBUG | 75 | #ifdef CONFIG_SAMSUNG_PM_DEBUG |
| 76 | 76 | ||
| 77 | struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS]; | 77 | static struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS]; |
| 78 | 78 | ||
| 79 | static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save) | 79 | static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save) |
| 80 | { | 80 | { |
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 331d574df99c..faf65286574e 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig | |||
| @@ -89,6 +89,7 @@ config ATH79 | |||
| 89 | select CEVT_R4K | 89 | select CEVT_R4K |
| 90 | select CSRC_R4K | 90 | select CSRC_R4K |
| 91 | select DMA_NONCOHERENT | 91 | select DMA_NONCOHERENT |
| 92 | select HAVE_CLK | ||
| 92 | select IRQ_CPU | 93 | select IRQ_CPU |
| 93 | select MIPS_MACHINE | 94 | select MIPS_MACHINE |
| 94 | select SYS_HAS_CPU_MIPS32_R2 | 95 | select SYS_HAS_CPU_MIPS32_R2 |
diff --git a/arch/mips/alchemy/board-mtx1.c b/arch/mips/alchemy/board-mtx1.c index 99969484c475..a124c251c0c9 100644 --- a/arch/mips/alchemy/board-mtx1.c +++ b/arch/mips/alchemy/board-mtx1.c | |||
| @@ -228,6 +228,8 @@ static int mtx1_pci_idsel(unsigned int devsel, int assert) | |||
| 228 | * adapter on the mtx-1 "singleboard" variant. It triggers a custom | 228 | * adapter on the mtx-1 "singleboard" variant. It triggers a custom |
| 229 | * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals. | 229 | * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals. |
| 230 | */ | 230 | */ |
| 231 | udelay(1); | ||
| 232 | |||
| 231 | if (assert && devsel != 0) | 233 | if (assert && devsel != 0) |
| 232 | /* Suppress signal to Cardbus */ | 234 | /* Suppress signal to Cardbus */ |
| 233 | alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */ | 235 | alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */ |
diff --git a/arch/mips/ath79/dev-usb.c b/arch/mips/ath79/dev-usb.c index 36e9570e7bc4..b2a2311ec85b 100644 --- a/arch/mips/ath79/dev-usb.c +++ b/arch/mips/ath79/dev-usb.c | |||
| @@ -145,6 +145,8 @@ static void __init ar7240_usb_setup(void) | |||
| 145 | 145 | ||
| 146 | ath79_ohci_resources[0].start = AR7240_OHCI_BASE; | 146 | ath79_ohci_resources[0].start = AR7240_OHCI_BASE; |
| 147 | ath79_ohci_resources[0].end = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1; | 147 | ath79_ohci_resources[0].end = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1; |
| 148 | ath79_ohci_resources[1].start = ATH79_CPU_IRQ_USB; | ||
| 149 | ath79_ohci_resources[1].end = ATH79_CPU_IRQ_USB; | ||
| 148 | platform_device_register(&ath79_ohci_device); | 150 | platform_device_register(&ath79_ohci_device); |
| 149 | } | 151 | } |
| 150 | 152 | ||
diff --git a/arch/mips/ath79/gpio.c b/arch/mips/ath79/gpio.c index 29054f211832..48fe762d2526 100644 --- a/arch/mips/ath79/gpio.c +++ b/arch/mips/ath79/gpio.c | |||
| @@ -188,8 +188,10 @@ void __init ath79_gpio_init(void) | |||
| 188 | 188 | ||
| 189 | if (soc_is_ar71xx()) | 189 | if (soc_is_ar71xx()) |
| 190 | ath79_gpio_count = AR71XX_GPIO_COUNT; | 190 | ath79_gpio_count = AR71XX_GPIO_COUNT; |
| 191 | else if (soc_is_ar724x()) | 191 | else if (soc_is_ar7240()) |
| 192 | ath79_gpio_count = AR724X_GPIO_COUNT; | 192 | ath79_gpio_count = AR7240_GPIO_COUNT; |
| 193 | else if (soc_is_ar7241() || soc_is_ar7242()) | ||
| 194 | ath79_gpio_count = AR7241_GPIO_COUNT; | ||
| 193 | else if (soc_is_ar913x()) | 195 | else if (soc_is_ar913x()) |
| 194 | ath79_gpio_count = AR913X_GPIO_COUNT; | 196 | ath79_gpio_count = AR913X_GPIO_COUNT; |
| 195 | else if (soc_is_ar933x()) | 197 | else if (soc_is_ar933x()) |
diff --git a/arch/mips/bcm63xx/dev-spi.c b/arch/mips/bcm63xx/dev-spi.c index e39f73048d4f..f1c9c3e2f678 100644 --- a/arch/mips/bcm63xx/dev-spi.c +++ b/arch/mips/bcm63xx/dev-spi.c | |||
| @@ -106,11 +106,15 @@ int __init bcm63xx_spi_register(void) | |||
| 106 | if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) { | 106 | if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) { |
| 107 | spi_resources[0].end += BCM_6338_RSET_SPI_SIZE - 1; | 107 | spi_resources[0].end += BCM_6338_RSET_SPI_SIZE - 1; |
| 108 | spi_pdata.fifo_size = SPI_6338_MSG_DATA_SIZE; | 108 | spi_pdata.fifo_size = SPI_6338_MSG_DATA_SIZE; |
| 109 | spi_pdata.msg_type_shift = SPI_6338_MSG_TYPE_SHIFT; | ||
| 110 | spi_pdata.msg_ctl_width = SPI_6338_MSG_CTL_WIDTH; | ||
| 109 | } | 111 | } |
| 110 | 112 | ||
| 111 | if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) { | 113 | if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) { |
| 112 | spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1; | 114 | spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1; |
| 113 | spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE; | 115 | spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE; |
| 116 | spi_pdata.msg_type_shift = SPI_6358_MSG_TYPE_SHIFT; | ||
| 117 | spi_pdata.msg_ctl_width = SPI_6358_MSG_CTL_WIDTH; | ||
| 114 | } | 118 | } |
| 115 | 119 | ||
| 116 | bcm63xx_spi_regs_init(); | 120 | bcm63xx_spi_regs_init(); |
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index 7fb1f222b8a5..274cd4fad30c 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c | |||
| @@ -61,6 +61,12 @@ static void octeon_irq_set_ciu_mapping(int irq, int line, int bit, | |||
| 61 | octeon_irq_ciu_to_irq[line][bit] = irq; | 61 | octeon_irq_ciu_to_irq[line][bit] = irq; |
| 62 | } | 62 | } |
| 63 | 63 | ||
| 64 | static void octeon_irq_force_ciu_mapping(struct irq_domain *domain, | ||
| 65 | int irq, int line, int bit) | ||
| 66 | { | ||
| 67 | irq_domain_associate(domain, irq, line << 6 | bit); | ||
| 68 | } | ||
| 69 | |||
| 64 | static int octeon_coreid_for_cpu(int cpu) | 70 | static int octeon_coreid_for_cpu(int cpu) |
| 65 | { | 71 | { |
| 66 | #ifdef CONFIG_SMP | 72 | #ifdef CONFIG_SMP |
| @@ -183,19 +189,9 @@ static void __init octeon_irq_init_core(void) | |||
| 183 | mutex_init(&cd->core_irq_mutex); | 189 | mutex_init(&cd->core_irq_mutex); |
| 184 | 190 | ||
| 185 | irq = OCTEON_IRQ_SW0 + i; | 191 | irq = OCTEON_IRQ_SW0 + i; |
| 186 | switch (irq) { | 192 | irq_set_chip_data(irq, cd); |
| 187 | case OCTEON_IRQ_TIMER: | 193 | irq_set_chip_and_handler(irq, &octeon_irq_chip_core, |
| 188 | case OCTEON_IRQ_SW0: | 194 | handle_percpu_irq); |
| 189 | case OCTEON_IRQ_SW1: | ||
| 190 | case OCTEON_IRQ_5: | ||
| 191 | case OCTEON_IRQ_PERF: | ||
| 192 | irq_set_chip_data(irq, cd); | ||
| 193 | irq_set_chip_and_handler(irq, &octeon_irq_chip_core, | ||
| 194 | handle_percpu_irq); | ||
| 195 | break; | ||
| 196 | default: | ||
| 197 | break; | ||
| 198 | } | ||
| 199 | } | 195 | } |
| 200 | } | 196 | } |
| 201 | 197 | ||
| @@ -890,7 +886,6 @@ static int octeon_irq_gpio_xlat(struct irq_domain *d, | |||
| 890 | unsigned int type; | 886 | unsigned int type; |
| 891 | unsigned int pin; | 887 | unsigned int pin; |
| 892 | unsigned int trigger; | 888 | unsigned int trigger; |
| 893 | struct octeon_irq_gpio_domain_data *gpiod; | ||
| 894 | 889 | ||
| 895 | if (d->of_node != node) | 890 | if (d->of_node != node) |
| 896 | return -EINVAL; | 891 | return -EINVAL; |
| @@ -925,8 +920,7 @@ static int octeon_irq_gpio_xlat(struct irq_domain *d, | |||
| 925 | break; | 920 | break; |
| 926 | } | 921 | } |
| 927 | *out_type = type; | 922 | *out_type = type; |
| 928 | gpiod = d->host_data; | 923 | *out_hwirq = pin; |
| 929 | *out_hwirq = gpiod->base_hwirq + pin; | ||
| 930 | 924 | ||
| 931 | return 0; | 925 | return 0; |
| 932 | } | 926 | } |
| @@ -996,19 +990,21 @@ static int octeon_irq_ciu_map(struct irq_domain *d, | |||
| 996 | static int octeon_irq_gpio_map(struct irq_domain *d, | 990 | static int octeon_irq_gpio_map(struct irq_domain *d, |
| 997 | unsigned int virq, irq_hw_number_t hw) | 991 | unsigned int virq, irq_hw_number_t hw) |
| 998 | { | 992 | { |
| 999 | unsigned int line = hw >> 6; | 993 | struct octeon_irq_gpio_domain_data *gpiod = d->host_data; |
| 1000 | unsigned int bit = hw & 63; | 994 | unsigned int line, bit; |
| 1001 | 995 | ||
| 1002 | if (!octeon_irq_virq_in_range(virq)) | 996 | if (!octeon_irq_virq_in_range(virq)) |
| 1003 | return -EINVAL; | 997 | return -EINVAL; |
| 1004 | 998 | ||
| 999 | hw += gpiod->base_hwirq; | ||
| 1000 | line = hw >> 6; | ||
| 1001 | bit = hw & 63; | ||
| 1005 | if (line > 1 || octeon_irq_ciu_to_irq[line][bit] != 0) | 1002 | if (line > 1 || octeon_irq_ciu_to_irq[line][bit] != 0) |
| 1006 | return -EINVAL; | 1003 | return -EINVAL; |
| 1007 | 1004 | ||
| 1008 | octeon_irq_set_ciu_mapping(virq, line, bit, | 1005 | octeon_irq_set_ciu_mapping(virq, line, bit, |
| 1009 | octeon_irq_gpio_chip, | 1006 | octeon_irq_gpio_chip, |
| 1010 | octeon_irq_handle_gpio); | 1007 | octeon_irq_handle_gpio); |
| 1011 | |||
| 1012 | return 0; | 1008 | return 0; |
| 1013 | } | 1009 | } |
| 1014 | 1010 | ||
| @@ -1149,6 +1145,7 @@ static void __init octeon_irq_init_ciu(void) | |||
| 1149 | struct irq_chip *chip_wd; | 1145 | struct irq_chip *chip_wd; |
| 1150 | struct device_node *gpio_node; | 1146 | struct device_node *gpio_node; |
| 1151 | struct device_node *ciu_node; | 1147 | struct device_node *ciu_node; |
| 1148 | struct irq_domain *ciu_domain = NULL; | ||
| 1152 | 1149 | ||
| 1153 | octeon_irq_init_ciu_percpu(); | 1150 | octeon_irq_init_ciu_percpu(); |
| 1154 | octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu; | 1151 | octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu; |
| @@ -1177,31 +1174,6 @@ static void __init octeon_irq_init_ciu(void) | |||
| 1177 | /* Mips internal */ | 1174 | /* Mips internal */ |
| 1178 | octeon_irq_init_core(); | 1175 | octeon_irq_init_core(); |
| 1179 | 1176 | ||
| 1180 | /* CIU_0 */ | ||
| 1181 | for (i = 0; i < 16; i++) | ||
| 1182 | octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WORKQ0, 0, i + 0, chip, handle_level_irq); | ||
| 1183 | |||
| 1184 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, chip_mbox, handle_percpu_irq); | ||
| 1185 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, chip_mbox, handle_percpu_irq); | ||
| 1186 | |||
| 1187 | for (i = 0; i < 4; i++) | ||
| 1188 | octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_INT0, 0, i + 36, chip, handle_level_irq); | ||
| 1189 | for (i = 0; i < 4; i++) | ||
| 1190 | octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_MSI0, 0, i + 40, chip, handle_level_irq); | ||
| 1191 | |||
| 1192 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_RML, 0, 46, chip, handle_level_irq); | ||
| 1193 | for (i = 0; i < 4; i++) | ||
| 1194 | octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_TIMER0, 0, i + 52, chip, handle_edge_irq); | ||
| 1195 | |||
| 1196 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB0, 0, 56, chip, handle_level_irq); | ||
| 1197 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_BOOTDMA, 0, 63, chip, handle_level_irq); | ||
| 1198 | |||
| 1199 | /* CIU_1 */ | ||
| 1200 | for (i = 0; i < 16; i++) | ||
| 1201 | octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i + 0, chip_wd, handle_level_irq); | ||
| 1202 | |||
| 1203 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB1, 1, 17, chip, handle_level_irq); | ||
| 1204 | |||
| 1205 | gpio_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-gpio"); | 1177 | gpio_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-gpio"); |
| 1206 | if (gpio_node) { | 1178 | if (gpio_node) { |
| 1207 | struct octeon_irq_gpio_domain_data *gpiod; | 1179 | struct octeon_irq_gpio_domain_data *gpiod; |
| @@ -1219,10 +1191,35 @@ static void __init octeon_irq_init_ciu(void) | |||
| 1219 | 1191 | ||
| 1220 | ciu_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-ciu"); | 1192 | ciu_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-ciu"); |
| 1221 | if (ciu_node) { | 1193 | if (ciu_node) { |
| 1222 | irq_domain_add_tree(ciu_node, &octeon_irq_domain_ciu_ops, NULL); | 1194 | ciu_domain = irq_domain_add_tree(ciu_node, &octeon_irq_domain_ciu_ops, NULL); |
| 1223 | of_node_put(ciu_node); | 1195 | of_node_put(ciu_node); |
| 1224 | } else | 1196 | } else |
| 1225 | pr_warn("Cannot find device node for cavium,octeon-3860-ciu.\n"); | 1197 | panic("Cannot find device node for cavium,octeon-3860-ciu."); |
| 1198 | |||
| 1199 | /* CIU_0 */ | ||
| 1200 | for (i = 0; i < 16; i++) | ||
| 1201 | octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_WORKQ0, 0, i + 0); | ||
| 1202 | |||
| 1203 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, chip_mbox, handle_percpu_irq); | ||
| 1204 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, chip_mbox, handle_percpu_irq); | ||
| 1205 | |||
| 1206 | for (i = 0; i < 4; i++) | ||
| 1207 | octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_PCI_INT0, 0, i + 36); | ||
| 1208 | for (i = 0; i < 4; i++) | ||
| 1209 | octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_PCI_MSI0, 0, i + 40); | ||
| 1210 | |||
| 1211 | octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_RML, 0, 46); | ||
| 1212 | for (i = 0; i < 4; i++) | ||
| 1213 | octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_TIMER0, 0, i + 52); | ||
| 1214 | |||
| 1215 | octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_USB0, 0, 56); | ||
| 1216 | octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_BOOTDMA, 0, 63); | ||
| 1217 | |||
| 1218 | /* CIU_1 */ | ||
| 1219 | for (i = 0; i < 16; i++) | ||
| 1220 | octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i + 0, chip_wd, handle_level_irq); | ||
| 1221 | |||
| 1222 | octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_USB1, 1, 17); | ||
| 1226 | 1223 | ||
| 1227 | /* Enable the CIU lines */ | 1224 | /* Enable the CIU lines */ |
| 1228 | set_c0_status(STATUSF_IP3 | STATUSF_IP2); | 1225 | set_c0_status(STATUSF_IP3 | STATUSF_IP2); |
diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 1caa78ad06d5..dde504477fac 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h | |||
| @@ -393,7 +393,8 @@ | |||
| 393 | #define AR71XX_GPIO_REG_FUNC 0x28 | 393 | #define AR71XX_GPIO_REG_FUNC 0x28 |
| 394 | 394 | ||
| 395 | #define AR71XX_GPIO_COUNT 16 | 395 | #define AR71XX_GPIO_COUNT 16 |
| 396 | #define AR724X_GPIO_COUNT 18 | 396 | #define AR7240_GPIO_COUNT 18 |
| 397 | #define AR7241_GPIO_COUNT 20 | ||
| 397 | #define AR913X_GPIO_COUNT 22 | 398 | #define AR913X_GPIO_COUNT 22 |
| 398 | #define AR933X_GPIO_COUNT 30 | 399 | #define AR933X_GPIO_COUNT 30 |
| 399 | #define AR934X_GPIO_COUNT 23 | 400 | #define AR934X_GPIO_COUNT 23 |
diff --git a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h index 4476fa03bf36..6ddae926bf79 100644 --- a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h | |||
| @@ -42,7 +42,6 @@ | |||
| 42 | #define cpu_has_mips64r1 0 | 42 | #define cpu_has_mips64r1 0 |
| 43 | #define cpu_has_mips64r2 0 | 43 | #define cpu_has_mips64r2 0 |
| 44 | 44 | ||
| 45 | #define cpu_has_dsp 0 | ||
| 46 | #define cpu_has_mipsmt 0 | 45 | #define cpu_has_mipsmt 0 |
| 47 | 46 | ||
| 48 | #define cpu_has_64bits 0 | 47 | #define cpu_has_64bits 0 |
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h index 7d98dbe5d4b5..c9bae1362606 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h | |||
| @@ -9,6 +9,8 @@ int __init bcm63xx_spi_register(void); | |||
| 9 | 9 | ||
| 10 | struct bcm63xx_spi_pdata { | 10 | struct bcm63xx_spi_pdata { |
| 11 | unsigned int fifo_size; | 11 | unsigned int fifo_size; |
| 12 | unsigned int msg_type_shift; | ||
| 13 | unsigned int msg_ctl_width; | ||
| 12 | int bus_num; | 14 | int bus_num; |
| 13 | int num_chipselect; | 15 | int num_chipselect; |
| 14 | u32 speed_hz; | 16 | u32 speed_hz; |
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index 4ccc2a748aff..61f2a2a5099d 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | |||
| @@ -1054,7 +1054,8 @@ | |||
| 1054 | #define SPI_6338_FILL_BYTE 0x07 | 1054 | #define SPI_6338_FILL_BYTE 0x07 |
| 1055 | #define SPI_6338_MSG_TAIL 0x09 | 1055 | #define SPI_6338_MSG_TAIL 0x09 |
| 1056 | #define SPI_6338_RX_TAIL 0x0b | 1056 | #define SPI_6338_RX_TAIL 0x0b |
| 1057 | #define SPI_6338_MSG_CTL 0x40 | 1057 | #define SPI_6338_MSG_CTL 0x40 /* 8-bits register */ |
| 1058 | #define SPI_6338_MSG_CTL_WIDTH 8 | ||
| 1058 | #define SPI_6338_MSG_DATA 0x41 | 1059 | #define SPI_6338_MSG_DATA 0x41 |
| 1059 | #define SPI_6338_MSG_DATA_SIZE 0x3f | 1060 | #define SPI_6338_MSG_DATA_SIZE 0x3f |
| 1060 | #define SPI_6338_RX_DATA 0x80 | 1061 | #define SPI_6338_RX_DATA 0x80 |
| @@ -1070,7 +1071,8 @@ | |||
| 1070 | #define SPI_6348_FILL_BYTE 0x07 | 1071 | #define SPI_6348_FILL_BYTE 0x07 |
| 1071 | #define SPI_6348_MSG_TAIL 0x09 | 1072 | #define SPI_6348_MSG_TAIL 0x09 |
| 1072 | #define SPI_6348_RX_TAIL 0x0b | 1073 | #define SPI_6348_RX_TAIL 0x0b |
| 1073 | #define SPI_6348_MSG_CTL 0x40 | 1074 | #define SPI_6348_MSG_CTL 0x40 /* 8-bits register */ |
| 1075 | #define SPI_6348_MSG_CTL_WIDTH 8 | ||
| 1074 | #define SPI_6348_MSG_DATA 0x41 | 1076 | #define SPI_6348_MSG_DATA 0x41 |
| 1075 | #define SPI_6348_MSG_DATA_SIZE 0x3f | 1077 | #define SPI_6348_MSG_DATA_SIZE 0x3f |
| 1076 | #define SPI_6348_RX_DATA 0x80 | 1078 | #define SPI_6348_RX_DATA 0x80 |
| @@ -1078,6 +1080,7 @@ | |||
| 1078 | 1080 | ||
| 1079 | /* BCM 6358 SPI core */ | 1081 | /* BCM 6358 SPI core */ |
| 1080 | #define SPI_6358_MSG_CTL 0x00 /* 16-bits register */ | 1082 | #define SPI_6358_MSG_CTL 0x00 /* 16-bits register */ |
| 1083 | #define SPI_6358_MSG_CTL_WIDTH 16 | ||
| 1081 | #define SPI_6358_MSG_DATA 0x02 | 1084 | #define SPI_6358_MSG_DATA 0x02 |
| 1082 | #define SPI_6358_MSG_DATA_SIZE 0x21e | 1085 | #define SPI_6358_MSG_DATA_SIZE 0x21e |
| 1083 | #define SPI_6358_RX_DATA 0x400 | 1086 | #define SPI_6358_RX_DATA 0x400 |
| @@ -1094,6 +1097,7 @@ | |||
| 1094 | 1097 | ||
| 1095 | /* BCM 6358 SPI core */ | 1098 | /* BCM 6358 SPI core */ |
| 1096 | #define SPI_6368_MSG_CTL 0x00 /* 16-bits register */ | 1099 | #define SPI_6368_MSG_CTL 0x00 /* 16-bits register */ |
| 1100 | #define SPI_6368_MSG_CTL_WIDTH 16 | ||
| 1097 | #define SPI_6368_MSG_DATA 0x02 | 1101 | #define SPI_6368_MSG_DATA 0x02 |
| 1098 | #define SPI_6368_MSG_DATA_SIZE 0x21e | 1102 | #define SPI_6368_MSG_DATA_SIZE 0x21e |
| 1099 | #define SPI_6368_RX_DATA 0x400 | 1103 | #define SPI_6368_RX_DATA 0x400 |
| @@ -1115,7 +1119,10 @@ | |||
| 1115 | #define SPI_HD_W 0x01 | 1119 | #define SPI_HD_W 0x01 |
| 1116 | #define SPI_HD_R 0x02 | 1120 | #define SPI_HD_R 0x02 |
| 1117 | #define SPI_BYTE_CNT_SHIFT 0 | 1121 | #define SPI_BYTE_CNT_SHIFT 0 |
| 1118 | #define SPI_MSG_TYPE_SHIFT 14 | 1122 | #define SPI_6338_MSG_TYPE_SHIFT 6 |
| 1123 | #define SPI_6348_MSG_TYPE_SHIFT 6 | ||
| 1124 | #define SPI_6358_MSG_TYPE_SHIFT 14 | ||
| 1125 | #define SPI_6368_MSG_TYPE_SHIFT 14 | ||
| 1119 | 1126 | ||
| 1120 | /* Command */ | 1127 | /* Command */ |
| 1121 | #define SPI_CMD_NOOP 0x00 | 1128 | #define SPI_CMD_NOOP 0x00 |
diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h index 418992042f6f..c22a3078bf11 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/irq.h +++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h | |||
| @@ -21,14 +21,10 @@ enum octeon_irq { | |||
| 21 | OCTEON_IRQ_TIMER, | 21 | OCTEON_IRQ_TIMER, |
| 22 | /* sources in CIU_INTX_EN0 */ | 22 | /* sources in CIU_INTX_EN0 */ |
| 23 | OCTEON_IRQ_WORKQ0, | 23 | OCTEON_IRQ_WORKQ0, |
| 24 | OCTEON_IRQ_GPIO0 = OCTEON_IRQ_WORKQ0 + 16, | 24 | OCTEON_IRQ_WDOG0 = OCTEON_IRQ_WORKQ0 + 16, |
| 25 | OCTEON_IRQ_WDOG0 = OCTEON_IRQ_GPIO0 + 16, | ||
| 26 | OCTEON_IRQ_WDOG15 = OCTEON_IRQ_WDOG0 + 15, | 25 | OCTEON_IRQ_WDOG15 = OCTEON_IRQ_WDOG0 + 15, |
| 27 | OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 16, | 26 | OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 16, |
| 28 | OCTEON_IRQ_MBOX1, | 27 | OCTEON_IRQ_MBOX1, |
| 29 | OCTEON_IRQ_UART0, | ||
| 30 | OCTEON_IRQ_UART1, | ||
| 31 | OCTEON_IRQ_UART2, | ||
| 32 | OCTEON_IRQ_PCI_INT0, | 28 | OCTEON_IRQ_PCI_INT0, |
| 33 | OCTEON_IRQ_PCI_INT1, | 29 | OCTEON_IRQ_PCI_INT1, |
| 34 | OCTEON_IRQ_PCI_INT2, | 30 | OCTEON_IRQ_PCI_INT2, |
| @@ -38,8 +34,6 @@ enum octeon_irq { | |||
| 38 | OCTEON_IRQ_PCI_MSI2, | 34 | OCTEON_IRQ_PCI_MSI2, |
| 39 | OCTEON_IRQ_PCI_MSI3, | 35 | OCTEON_IRQ_PCI_MSI3, |
| 40 | 36 | ||
| 41 | OCTEON_IRQ_TWSI, | ||
| 42 | OCTEON_IRQ_TWSI2, | ||
| 43 | OCTEON_IRQ_RML, | 37 | OCTEON_IRQ_RML, |
| 44 | OCTEON_IRQ_TIMER0, | 38 | OCTEON_IRQ_TIMER0, |
| 45 | OCTEON_IRQ_TIMER1, | 39 | OCTEON_IRQ_TIMER1, |
| @@ -47,8 +41,6 @@ enum octeon_irq { | |||
| 47 | OCTEON_IRQ_TIMER3, | 41 | OCTEON_IRQ_TIMER3, |
| 48 | OCTEON_IRQ_USB0, | 42 | OCTEON_IRQ_USB0, |
| 49 | OCTEON_IRQ_USB1, | 43 | OCTEON_IRQ_USB1, |
| 50 | OCTEON_IRQ_MII0, | ||
| 51 | OCTEON_IRQ_MII1, | ||
| 52 | OCTEON_IRQ_BOOTDMA, | 44 | OCTEON_IRQ_BOOTDMA, |
| 53 | #ifndef CONFIG_PCI_MSI | 45 | #ifndef CONFIG_PCI_MSI |
| 54 | OCTEON_IRQ_LAST = 127 | 46 | OCTEON_IRQ_LAST = 127 |
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h index 7531ecd654d6..dca8bce8c7ab 100644 --- a/arch/mips/include/asm/module.h +++ b/arch/mips/include/asm/module.h | |||
| @@ -10,6 +10,7 @@ struct mod_arch_specific { | |||
| 10 | struct list_head dbe_list; | 10 | struct list_head dbe_list; |
| 11 | const struct exception_table_entry *dbe_start; | 11 | const struct exception_table_entry *dbe_start; |
| 12 | const struct exception_table_entry *dbe_end; | 12 | const struct exception_table_entry *dbe_end; |
| 13 | struct mips_hi16 *r_mips_hi16_list; | ||
| 13 | }; | 14 | }; |
| 14 | 15 | ||
| 15 | typedef uint8_t Elf64_Byte; /* Type for a 8-bit quantity. */ | 16 | typedef uint8_t Elf64_Byte; /* Type for a 8-bit quantity. */ |
diff --git a/arch/mips/include/asm/r4k-timer.h b/arch/mips/include/asm/r4k-timer.h index a37d12b3b61c..afe9e0e03fe9 100644 --- a/arch/mips/include/asm/r4k-timer.h +++ b/arch/mips/include/asm/r4k-timer.h | |||
| @@ -12,16 +12,16 @@ | |||
| 12 | 12 | ||
| 13 | #ifdef CONFIG_SYNC_R4K | 13 | #ifdef CONFIG_SYNC_R4K |
| 14 | 14 | ||
| 15 | extern void synchronise_count_master(void); | 15 | extern void synchronise_count_master(int cpu); |
| 16 | extern void synchronise_count_slave(void); | 16 | extern void synchronise_count_slave(int cpu); |
| 17 | 17 | ||
| 18 | #else | 18 | #else |
| 19 | 19 | ||
| 20 | static inline void synchronise_count_master(void) | 20 | static inline void synchronise_count_master(int cpu) |
| 21 | { | 21 | { |
| 22 | } | 22 | } |
| 23 | 23 | ||
| 24 | static inline void synchronise_count_slave(void) | 24 | static inline void synchronise_count_slave(int cpu) |
| 25 | { | 25 | { |
| 26 | } | 26 | } |
| 27 | 27 | ||
diff --git a/arch/mips/kernel/module.c b/arch/mips/kernel/module.c index a5066b1c3de3..4f8c3cba8c0c 100644 --- a/arch/mips/kernel/module.c +++ b/arch/mips/kernel/module.c | |||
| @@ -39,8 +39,6 @@ struct mips_hi16 { | |||
| 39 | Elf_Addr value; | 39 | Elf_Addr value; |
| 40 | }; | 40 | }; |
| 41 | 41 | ||
| 42 | static struct mips_hi16 *mips_hi16_list; | ||
| 43 | |||
| 44 | static LIST_HEAD(dbe_list); | 42 | static LIST_HEAD(dbe_list); |
| 45 | static DEFINE_SPINLOCK(dbe_lock); | 43 | static DEFINE_SPINLOCK(dbe_lock); |
| 46 | 44 | ||
| @@ -128,8 +126,8 @@ static int apply_r_mips_hi16_rel(struct module *me, u32 *location, Elf_Addr v) | |||
| 128 | 126 | ||
| 129 | n->addr = (Elf_Addr *)location; | 127 | n->addr = (Elf_Addr *)location; |
| 130 | n->value = v; | 128 | n->value = v; |
| 131 | n->next = mips_hi16_list; | 129 | n->next = me->arch.r_mips_hi16_list; |
| 132 | mips_hi16_list = n; | 130 | me->arch.r_mips_hi16_list = n; |
| 133 | 131 | ||
| 134 | return 0; | 132 | return 0; |
| 135 | } | 133 | } |
| @@ -142,18 +140,28 @@ static int apply_r_mips_hi16_rela(struct module *me, u32 *location, Elf_Addr v) | |||
| 142 | return 0; | 140 | return 0; |
| 143 | } | 141 | } |
| 144 | 142 | ||
| 143 | static void free_relocation_chain(struct mips_hi16 *l) | ||
| 144 | { | ||
| 145 | struct mips_hi16 *next; | ||
| 146 | |||
| 147 | while (l) { | ||
| 148 | next = l->next; | ||
| 149 | kfree(l); | ||
| 150 | l = next; | ||
| 151 | } | ||
| 152 | } | ||
| 153 | |||
| 145 | static int apply_r_mips_lo16_rel(struct module *me, u32 *location, Elf_Addr v) | 154 | static int apply_r_mips_lo16_rel(struct module *me, u32 *location, Elf_Addr v) |
| 146 | { | 155 | { |
| 147 | unsigned long insnlo = *location; | 156 | unsigned long insnlo = *location; |
| 157 | struct mips_hi16 *l; | ||
| 148 | Elf_Addr val, vallo; | 158 | Elf_Addr val, vallo; |
| 149 | 159 | ||
| 150 | /* Sign extend the addend we extract from the lo insn. */ | 160 | /* Sign extend the addend we extract from the lo insn. */ |
| 151 | vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000; | 161 | vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000; |
| 152 | 162 | ||
| 153 | if (mips_hi16_list != NULL) { | 163 | if (me->arch.r_mips_hi16_list != NULL) { |
| 154 | struct mips_hi16 *l; | 164 | l = me->arch.r_mips_hi16_list; |
| 155 | |||
| 156 | l = mips_hi16_list; | ||
| 157 | while (l != NULL) { | 165 | while (l != NULL) { |
| 158 | struct mips_hi16 *next; | 166 | struct mips_hi16 *next; |
| 159 | unsigned long insn; | 167 | unsigned long insn; |
| @@ -188,7 +196,7 @@ static int apply_r_mips_lo16_rel(struct module *me, u32 *location, Elf_Addr v) | |||
| 188 | l = next; | 196 | l = next; |
| 189 | } | 197 | } |
| 190 | 198 | ||
| 191 | mips_hi16_list = NULL; | 199 | me->arch.r_mips_hi16_list = NULL; |
| 192 | } | 200 | } |
| 193 | 201 | ||
| 194 | /* | 202 | /* |
| @@ -201,6 +209,9 @@ static int apply_r_mips_lo16_rel(struct module *me, u32 *location, Elf_Addr v) | |||
| 201 | return 0; | 209 | return 0; |
| 202 | 210 | ||
| 203 | out_danger: | 211 | out_danger: |
| 212 | free_relocation_chain(l); | ||
| 213 | me->arch.r_mips_hi16_list = NULL; | ||
| 214 | |||
| 204 | pr_err("module %s: dangerous R_MIPS_LO16 REL relocation\n", me->name); | 215 | pr_err("module %s: dangerous R_MIPS_LO16 REL relocation\n", me->name); |
| 205 | 216 | ||
| 206 | return -ENOEXEC; | 217 | return -ENOEXEC; |
| @@ -273,6 +284,7 @@ int apply_relocate(Elf_Shdr *sechdrs, const char *strtab, | |||
| 273 | pr_debug("Applying relocate section %u to %u\n", relsec, | 284 | pr_debug("Applying relocate section %u to %u\n", relsec, |
| 274 | sechdrs[relsec].sh_info); | 285 | sechdrs[relsec].sh_info); |
| 275 | 286 | ||
| 287 | me->arch.r_mips_hi16_list = NULL; | ||
| 276 | for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { | 288 | for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { |
| 277 | /* This is where to make the change */ | 289 | /* This is where to make the change */ |
| 278 | location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr | 290 | location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr |
| @@ -296,6 +308,19 @@ int apply_relocate(Elf_Shdr *sechdrs, const char *strtab, | |||
| 296 | return res; | 308 | return res; |
| 297 | } | 309 | } |
| 298 | 310 | ||
| 311 | /* | ||
| 312 | * Normally the hi16 list should be deallocated at this point. A | ||
| 313 | * malformed binary however could contain a series of R_MIPS_HI16 | ||
| 314 | * relocations not followed by a R_MIPS_LO16 relocation. In that | ||
| 315 | * case, free up the list and return an error. | ||
| 316 | */ | ||
| 317 | if (me->arch.r_mips_hi16_list) { | ||
| 318 | free_relocation_chain(me->arch.r_mips_hi16_list); | ||
| 319 | me->arch.r_mips_hi16_list = NULL; | ||
| 320 | |||
| 321 | return -ENOEXEC; | ||
| 322 | } | ||
| 323 | |||
| 299 | return 0; | 324 | return 0; |
| 300 | } | 325 | } |
| 301 | 326 | ||
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 31637d8c8738..9005bf9fb859 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c | |||
| @@ -130,7 +130,7 @@ asmlinkage __cpuinit void start_secondary(void) | |||
| 130 | 130 | ||
| 131 | cpu_set(cpu, cpu_callin_map); | 131 | cpu_set(cpu, cpu_callin_map); |
| 132 | 132 | ||
| 133 | synchronise_count_slave(); | 133 | synchronise_count_slave(cpu); |
| 134 | 134 | ||
| 135 | /* | 135 | /* |
| 136 | * irq will be enabled in ->smp_finish(), enabling it too early | 136 | * irq will be enabled in ->smp_finish(), enabling it too early |
| @@ -173,7 +173,6 @@ void smp_send_stop(void) | |||
| 173 | void __init smp_cpus_done(unsigned int max_cpus) | 173 | void __init smp_cpus_done(unsigned int max_cpus) |
| 174 | { | 174 | { |
| 175 | mp_ops->cpus_done(); | 175 | mp_ops->cpus_done(); |
| 176 | synchronise_count_master(); | ||
| 177 | } | 176 | } |
| 178 | 177 | ||
| 179 | /* called from main before smp_init() */ | 178 | /* called from main before smp_init() */ |
| @@ -206,6 +205,7 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle) | |||
| 206 | while (!cpu_isset(cpu, cpu_callin_map)) | 205 | while (!cpu_isset(cpu, cpu_callin_map)) |
| 207 | udelay(100); | 206 | udelay(100); |
| 208 | 207 | ||
| 208 | synchronise_count_master(cpu); | ||
| 209 | return 0; | 209 | return 0; |
| 210 | } | 210 | } |
| 211 | 211 | ||
diff --git a/arch/mips/kernel/sync-r4k.c b/arch/mips/kernel/sync-r4k.c index 842d55e411fd..7f1eca3858de 100644 --- a/arch/mips/kernel/sync-r4k.c +++ b/arch/mips/kernel/sync-r4k.c | |||
| @@ -28,12 +28,11 @@ static atomic_t __cpuinitdata count_reference = ATOMIC_INIT(0); | |||
| 28 | #define COUNTON 100 | 28 | #define COUNTON 100 |
| 29 | #define NR_LOOPS 5 | 29 | #define NR_LOOPS 5 |
| 30 | 30 | ||
| 31 | void __cpuinit synchronise_count_master(void) | 31 | void __cpuinit synchronise_count_master(int cpu) |
| 32 | { | 32 | { |
| 33 | int i; | 33 | int i; |
| 34 | unsigned long flags; | 34 | unsigned long flags; |
| 35 | unsigned int initcount; | 35 | unsigned int initcount; |
| 36 | int nslaves; | ||
| 37 | 36 | ||
| 38 | #ifdef CONFIG_MIPS_MT_SMTC | 37 | #ifdef CONFIG_MIPS_MT_SMTC |
| 39 | /* | 38 | /* |
| @@ -43,8 +42,7 @@ void __cpuinit synchronise_count_master(void) | |||
| 43 | return; | 42 | return; |
| 44 | #endif | 43 | #endif |
| 45 | 44 | ||
| 46 | printk(KERN_INFO "Synchronize counters across %u CPUs: ", | 45 | printk(KERN_INFO "Synchronize counters for CPU %u: ", cpu); |
| 47 | num_online_cpus()); | ||
| 48 | 46 | ||
| 49 | local_irq_save(flags); | 47 | local_irq_save(flags); |
| 50 | 48 | ||
| @@ -52,7 +50,7 @@ void __cpuinit synchronise_count_master(void) | |||
| 52 | * Notify the slaves that it's time to start | 50 | * Notify the slaves that it's time to start |
| 53 | */ | 51 | */ |
| 54 | atomic_set(&count_reference, read_c0_count()); | 52 | atomic_set(&count_reference, read_c0_count()); |
| 55 | atomic_set(&count_start_flag, 1); | 53 | atomic_set(&count_start_flag, cpu); |
| 56 | smp_wmb(); | 54 | smp_wmb(); |
| 57 | 55 | ||
| 58 | /* Count will be initialised to current timer for all CPU's */ | 56 | /* Count will be initialised to current timer for all CPU's */ |
| @@ -69,10 +67,9 @@ void __cpuinit synchronise_count_master(void) | |||
| 69 | * two CPUs. | 67 | * two CPUs. |
| 70 | */ | 68 | */ |
| 71 | 69 | ||
| 72 | nslaves = num_online_cpus()-1; | ||
| 73 | for (i = 0; i < NR_LOOPS; i++) { | 70 | for (i = 0; i < NR_LOOPS; i++) { |
| 74 | /* slaves loop on '!= ncpus' */ | 71 | /* slaves loop on '!= 2' */ |
| 75 | while (atomic_read(&count_count_start) != nslaves) | 72 | while (atomic_read(&count_count_start) != 1) |
| 76 | mb(); | 73 | mb(); |
| 77 | atomic_set(&count_count_stop, 0); | 74 | atomic_set(&count_count_stop, 0); |
| 78 | smp_wmb(); | 75 | smp_wmb(); |
| @@ -89,7 +86,7 @@ void __cpuinit synchronise_count_master(void) | |||
| 89 | /* | 86 | /* |
| 90 | * Wait for all slaves to leave the synchronization point: | 87 | * Wait for all slaves to leave the synchronization point: |
| 91 | */ | 88 | */ |
| 92 | while (atomic_read(&count_count_stop) != nslaves) | 89 | while (atomic_read(&count_count_stop) != 1) |
| 93 | mb(); | 90 | mb(); |
| 94 | atomic_set(&count_count_start, 0); | 91 | atomic_set(&count_count_start, 0); |
| 95 | smp_wmb(); | 92 | smp_wmb(); |
| @@ -97,6 +94,7 @@ void __cpuinit synchronise_count_master(void) | |||
| 97 | } | 94 | } |
| 98 | /* Arrange for an interrupt in a short while */ | 95 | /* Arrange for an interrupt in a short while */ |
| 99 | write_c0_compare(read_c0_count() + COUNTON); | 96 | write_c0_compare(read_c0_count() + COUNTON); |
| 97 | atomic_set(&count_start_flag, 0); | ||
| 100 | 98 | ||
| 101 | local_irq_restore(flags); | 99 | local_irq_restore(flags); |
| 102 | 100 | ||
| @@ -108,11 +106,10 @@ void __cpuinit synchronise_count_master(void) | |||
| 108 | printk("done.\n"); | 106 | printk("done.\n"); |
| 109 | } | 107 | } |
| 110 | 108 | ||
| 111 | void __cpuinit synchronise_count_slave(void) | 109 | void __cpuinit synchronise_count_slave(int cpu) |
| 112 | { | 110 | { |
| 113 | int i; | 111 | int i; |
| 114 | unsigned int initcount; | 112 | unsigned int initcount; |
| 115 | int ncpus; | ||
| 116 | 113 | ||
| 117 | #ifdef CONFIG_MIPS_MT_SMTC | 114 | #ifdef CONFIG_MIPS_MT_SMTC |
| 118 | /* | 115 | /* |
| @@ -127,16 +124,15 @@ void __cpuinit synchronise_count_slave(void) | |||
| 127 | * so we first wait for the master to say everyone is ready | 124 | * so we first wait for the master to say everyone is ready |
| 128 | */ | 125 | */ |
| 129 | 126 | ||
| 130 | while (!atomic_read(&count_start_flag)) | 127 | while (atomic_read(&count_start_flag) != cpu) |
| 131 | mb(); | 128 | mb(); |
| 132 | 129 | ||
| 133 | /* Count will be initialised to next expire for all CPU's */ | 130 | /* Count will be initialised to next expire for all CPU's */ |
| 134 | initcount = atomic_read(&count_reference); | 131 | initcount = atomic_read(&count_reference); |
| 135 | 132 | ||
| 136 | ncpus = num_online_cpus(); | ||
| 137 | for (i = 0; i < NR_LOOPS; i++) { | 133 | for (i = 0; i < NR_LOOPS; i++) { |
| 138 | atomic_inc(&count_count_start); | 134 | atomic_inc(&count_count_start); |
| 139 | while (atomic_read(&count_count_start) != ncpus) | 135 | while (atomic_read(&count_count_start) != 2) |
| 140 | mb(); | 136 | mb(); |
| 141 | 137 | ||
| 142 | /* | 138 | /* |
| @@ -146,7 +142,7 @@ void __cpuinit synchronise_count_slave(void) | |||
| 146 | write_c0_count(initcount); | 142 | write_c0_count(initcount); |
| 147 | 143 | ||
| 148 | atomic_inc(&count_count_stop); | 144 | atomic_inc(&count_count_stop); |
| 149 | while (atomic_read(&count_count_stop) != ncpus) | 145 | while (atomic_read(&count_count_stop) != 2) |
| 150 | mb(); | 146 | mb(); |
| 151 | } | 147 | } |
| 152 | /* Arrange for an interrupt in a short while */ | 148 | /* Arrange for an interrupt in a short while */ |
diff --git a/arch/mips/mti-malta/malta-pci.c b/arch/mips/mti-malta/malta-pci.c index 284dea54faf5..2147cb34e705 100644 --- a/arch/mips/mti-malta/malta-pci.c +++ b/arch/mips/mti-malta/malta-pci.c | |||
| @@ -252,16 +252,3 @@ void __init mips_pcibios_init(void) | |||
| 252 | 252 | ||
| 253 | register_pci_controller(controller); | 253 | register_pci_controller(controller); |
| 254 | } | 254 | } |
| 255 | |||
| 256 | /* Enable PCI 2.1 compatibility in PIIX4 */ | ||
| 257 | static void __devinit quirk_dlcsetup(struct pci_dev *dev) | ||
| 258 | { | ||
| 259 | u8 odlc, ndlc; | ||
| 260 | (void) pci_read_config_byte(dev, 0x82, &odlc); | ||
| 261 | /* Enable passive releases and delayed transaction */ | ||
| 262 | ndlc = odlc | 7; | ||
| 263 | (void) pci_write_config_byte(dev, 0x82, ndlc); | ||
| 264 | } | ||
| 265 | |||
| 266 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, | ||
| 267 | quirk_dlcsetup); | ||
diff --git a/arch/mips/pci/pci-ar724x.c b/arch/mips/pci/pci-ar724x.c index 414a7459858d..86d77a666458 100644 --- a/arch/mips/pci/pci-ar724x.c +++ b/arch/mips/pci/pci-ar724x.c | |||
| @@ -23,9 +23,12 @@ | |||
| 23 | #define AR724X_PCI_MEM_BASE 0x10000000 | 23 | #define AR724X_PCI_MEM_BASE 0x10000000 |
| 24 | #define AR724X_PCI_MEM_SIZE 0x08000000 | 24 | #define AR724X_PCI_MEM_SIZE 0x08000000 |
| 25 | 25 | ||
| 26 | #define AR724X_PCI_REG_RESET 0x18 | ||
| 26 | #define AR724X_PCI_REG_INT_STATUS 0x4c | 27 | #define AR724X_PCI_REG_INT_STATUS 0x4c |
| 27 | #define AR724X_PCI_REG_INT_MASK 0x50 | 28 | #define AR724X_PCI_REG_INT_MASK 0x50 |
| 28 | 29 | ||
| 30 | #define AR724X_PCI_RESET_LINK_UP BIT(0) | ||
| 31 | |||
| 29 | #define AR724X_PCI_INT_DEV0 BIT(14) | 32 | #define AR724X_PCI_INT_DEV0 BIT(14) |
| 30 | 33 | ||
| 31 | #define AR724X_PCI_IRQ_COUNT 1 | 34 | #define AR724X_PCI_IRQ_COUNT 1 |
| @@ -38,6 +41,15 @@ static void __iomem *ar724x_pci_ctrl_base; | |||
| 38 | 41 | ||
| 39 | static u32 ar724x_pci_bar0_value; | 42 | static u32 ar724x_pci_bar0_value; |
| 40 | static bool ar724x_pci_bar0_is_cached; | 43 | static bool ar724x_pci_bar0_is_cached; |
| 44 | static bool ar724x_pci_link_up; | ||
| 45 | |||
| 46 | static inline bool ar724x_pci_check_link(void) | ||
| 47 | { | ||
| 48 | u32 reset; | ||
| 49 | |||
| 50 | reset = __raw_readl(ar724x_pci_ctrl_base + AR724X_PCI_REG_RESET); | ||
| 51 | return reset & AR724X_PCI_RESET_LINK_UP; | ||
| 52 | } | ||
| 41 | 53 | ||
| 42 | static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, | 54 | static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, |
| 43 | int size, uint32_t *value) | 55 | int size, uint32_t *value) |
| @@ -46,6 +58,9 @@ static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, | |||
| 46 | void __iomem *base; | 58 | void __iomem *base; |
| 47 | u32 data; | 59 | u32 data; |
| 48 | 60 | ||
| 61 | if (!ar724x_pci_link_up) | ||
| 62 | return PCIBIOS_DEVICE_NOT_FOUND; | ||
| 63 | |||
| 49 | if (devfn) | 64 | if (devfn) |
| 50 | return PCIBIOS_DEVICE_NOT_FOUND; | 65 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 51 | 66 | ||
| @@ -96,6 +111,9 @@ static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, | |||
| 96 | u32 data; | 111 | u32 data; |
| 97 | int s; | 112 | int s; |
| 98 | 113 | ||
| 114 | if (!ar724x_pci_link_up) | ||
| 115 | return PCIBIOS_DEVICE_NOT_FOUND; | ||
| 116 | |||
| 99 | if (devfn) | 117 | if (devfn) |
| 100 | return PCIBIOS_DEVICE_NOT_FOUND; | 118 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 101 | 119 | ||
| @@ -280,6 +298,10 @@ int __init ar724x_pcibios_init(int irq) | |||
| 280 | if (ar724x_pci_ctrl_base == NULL) | 298 | if (ar724x_pci_ctrl_base == NULL) |
| 281 | goto err_unmap_devcfg; | 299 | goto err_unmap_devcfg; |
| 282 | 300 | ||
| 301 | ar724x_pci_link_up = ar724x_pci_check_link(); | ||
| 302 | if (!ar724x_pci_link_up) | ||
| 303 | pr_warn("ar724x: PCIe link is down\n"); | ||
| 304 | |||
| 283 | ar724x_pci_irq_init(irq); | 305 | ar724x_pci_irq_init(irq); |
| 284 | register_pci_controller(&ar724x_pci_controller); | 306 | register_pci_controller(&ar724x_pci_controller); |
| 285 | 307 | ||
diff --git a/arch/parisc/include/asm/atomic.h b/arch/parisc/include/asm/atomic.h index 6c6defc24619..af9cf30ed474 100644 --- a/arch/parisc/include/asm/atomic.h +++ b/arch/parisc/include/asm/atomic.h | |||
| @@ -141,7 +141,7 @@ static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u) | |||
| 141 | 141 | ||
| 142 | #define atomic_sub_and_test(i,v) (atomic_sub_return((i),(v)) == 0) | 142 | #define atomic_sub_and_test(i,v) (atomic_sub_return((i),(v)) == 0) |
| 143 | 143 | ||
| 144 | #define ATOMIC_INIT(i) ((atomic_t) { (i) }) | 144 | #define ATOMIC_INIT(i) { (i) } |
| 145 | 145 | ||
| 146 | #define smp_mb__before_atomic_dec() smp_mb() | 146 | #define smp_mb__before_atomic_dec() smp_mb() |
| 147 | #define smp_mb__after_atomic_dec() smp_mb() | 147 | #define smp_mb__after_atomic_dec() smp_mb() |
| @@ -150,7 +150,7 @@ static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u) | |||
| 150 | 150 | ||
| 151 | #ifdef CONFIG_64BIT | 151 | #ifdef CONFIG_64BIT |
| 152 | 152 | ||
| 153 | #define ATOMIC64_INIT(i) ((atomic64_t) { (i) }) | 153 | #define ATOMIC64_INIT(i) { (i) } |
| 154 | 154 | ||
| 155 | static __inline__ s64 | 155 | static __inline__ s64 |
| 156 | __atomic64_add_return(s64 i, atomic64_t *v) | 156 | __atomic64_add_return(s64 i, atomic64_t *v) |
diff --git a/arch/parisc/kernel/process.c b/arch/parisc/kernel/process.c index d4b94b395c16..2c05a9292a81 100644 --- a/arch/parisc/kernel/process.c +++ b/arch/parisc/kernel/process.c | |||
| @@ -309,7 +309,7 @@ copy_thread(unsigned long clone_flags, unsigned long usp, | |||
| 309 | cregs->ksp = (unsigned long)stack | 309 | cregs->ksp = (unsigned long)stack |
| 310 | + (pregs->gr[21] & (THREAD_SIZE - 1)); | 310 | + (pregs->gr[21] & (THREAD_SIZE - 1)); |
| 311 | cregs->gr[30] = usp; | 311 | cregs->gr[30] = usp; |
| 312 | if (p->personality == PER_HPUX) { | 312 | if (personality(p->personality) == PER_HPUX) { |
| 313 | #ifdef CONFIG_HPUX | 313 | #ifdef CONFIG_HPUX |
| 314 | cregs->kpc = (unsigned long) &hpux_child_return; | 314 | cregs->kpc = (unsigned long) &hpux_child_return; |
| 315 | #else | 315 | #else |
diff --git a/arch/parisc/kernel/sys_parisc.c b/arch/parisc/kernel/sys_parisc.c index c9b932260f47..7426e40699bd 100644 --- a/arch/parisc/kernel/sys_parisc.c +++ b/arch/parisc/kernel/sys_parisc.c | |||
| @@ -225,12 +225,12 @@ long parisc_personality(unsigned long personality) | |||
| 225 | long err; | 225 | long err; |
| 226 | 226 | ||
| 227 | if (personality(current->personality) == PER_LINUX32 | 227 | if (personality(current->personality) == PER_LINUX32 |
| 228 | && personality == PER_LINUX) | 228 | && personality(personality) == PER_LINUX) |
| 229 | personality = PER_LINUX32; | 229 | personality = (personality & ~PER_MASK) | PER_LINUX32; |
| 230 | 230 | ||
| 231 | err = sys_personality(personality); | 231 | err = sys_personality(personality); |
| 232 | if (err == PER_LINUX32) | 232 | if (personality(err) == PER_LINUX32) |
| 233 | err = PER_LINUX; | 233 | err = (err & ~PER_MASK) | PER_LINUX; |
| 234 | 234 | ||
| 235 | return err; | 235 | return err; |
| 236 | } | 236 | } |
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi index 8d35d2c1f694..4f9c9f682ecf 100644 --- a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi | |||
| @@ -345,6 +345,13 @@ | |||
| 345 | /include/ "qoriq-duart-1.dtsi" | 345 | /include/ "qoriq-duart-1.dtsi" |
| 346 | /include/ "qoriq-gpio-0.dtsi" | 346 | /include/ "qoriq-gpio-0.dtsi" |
| 347 | /include/ "qoriq-usb2-mph-0.dtsi" | 347 | /include/ "qoriq-usb2-mph-0.dtsi" |
| 348 | usb@210000 { | ||
| 349 | compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph"; | ||
| 350 | port0; | ||
| 351 | }; | ||
| 348 | /include/ "qoriq-usb2-dr-0.dtsi" | 352 | /include/ "qoriq-usb2-dr-0.dtsi" |
| 353 | usb@211000 { | ||
| 354 | compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; | ||
| 355 | }; | ||
| 349 | /include/ "qoriq-sec4.0-0.dtsi" | 356 | /include/ "qoriq-sec4.0-0.dtsi" |
| 350 | }; | 357 | }; |
diff --git a/arch/powerpc/configs/85xx/p1023rds_defconfig b/arch/powerpc/configs/85xx/p1023rds_defconfig index f4337bacd0e7..26e541c4662b 100644 --- a/arch/powerpc/configs/85xx/p1023rds_defconfig +++ b/arch/powerpc/configs/85xx/p1023rds_defconfig | |||
| @@ -6,28 +6,27 @@ CONFIG_SYSVIPC=y | |||
| 6 | CONFIG_POSIX_MQUEUE=y | 6 | CONFIG_POSIX_MQUEUE=y |
| 7 | CONFIG_BSD_PROCESS_ACCT=y | 7 | CONFIG_BSD_PROCESS_ACCT=y |
| 8 | CONFIG_AUDIT=y | 8 | CONFIG_AUDIT=y |
| 9 | CONFIG_SPARSE_IRQ=y | 9 | CONFIG_IRQ_DOMAIN_DEBUG=y |
| 10 | CONFIG_NO_HZ=y | ||
| 11 | CONFIG_HIGH_RES_TIMERS=y | ||
| 10 | CONFIG_IKCONFIG=y | 12 | CONFIG_IKCONFIG=y |
| 11 | CONFIG_IKCONFIG_PROC=y | 13 | CONFIG_IKCONFIG_PROC=y |
| 12 | CONFIG_LOG_BUF_SHIFT=14 | 14 | CONFIG_LOG_BUF_SHIFT=14 |
| 13 | CONFIG_BLK_DEV_INITRD=y | 15 | CONFIG_BLK_DEV_INITRD=y |
| 14 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | ||
| 15 | CONFIG_KALLSYMS_ALL=y | 16 | CONFIG_KALLSYMS_ALL=y |
| 16 | CONFIG_KALLSYMS_EXTRA_PASS=y | ||
| 17 | CONFIG_EMBEDDED=y | 17 | CONFIG_EMBEDDED=y |
| 18 | CONFIG_MODULES=y | 18 | CONFIG_MODULES=y |
| 19 | CONFIG_MODULE_UNLOAD=y | 19 | CONFIG_MODULE_UNLOAD=y |
| 20 | CONFIG_MODULE_FORCE_UNLOAD=y | 20 | CONFIG_MODULE_FORCE_UNLOAD=y |
| 21 | CONFIG_MODVERSIONS=y | 21 | CONFIG_MODVERSIONS=y |
| 22 | # CONFIG_BLK_DEV_BSG is not set | 22 | # CONFIG_BLK_DEV_BSG is not set |
| 23 | CONFIG_PARTITION_ADVANCED=y | ||
| 24 | CONFIG_MAC_PARTITION=y | ||
| 23 | CONFIG_P1023_RDS=y | 25 | CONFIG_P1023_RDS=y |
| 24 | CONFIG_QUICC_ENGINE=y | 26 | CONFIG_QUICC_ENGINE=y |
| 25 | CONFIG_QE_GPIO=y | 27 | CONFIG_QE_GPIO=y |
| 26 | CONFIG_CPM2=y | 28 | CONFIG_CPM2=y |
| 27 | CONFIG_GPIO_MPC8XXX=y | ||
| 28 | CONFIG_HIGHMEM=y | 29 | CONFIG_HIGHMEM=y |
| 29 | CONFIG_NO_HZ=y | ||
| 30 | CONFIG_HIGH_RES_TIMERS=y | ||
| 31 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | 30 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set |
| 32 | CONFIG_BINFMT_MISC=m | 31 | CONFIG_BINFMT_MISC=m |
| 33 | CONFIG_MATH_EMULATION=y | 32 | CONFIG_MATH_EMULATION=y |
| @@ -63,11 +62,11 @@ CONFIG_INET_ESP=y | |||
| 63 | CONFIG_IPV6=y | 62 | CONFIG_IPV6=y |
| 64 | CONFIG_IP_SCTP=m | 63 | CONFIG_IP_SCTP=m |
| 65 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 64 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 65 | CONFIG_DEVTMPFS=y | ||
| 66 | CONFIG_PROC_DEVICETREE=y | 66 | CONFIG_PROC_DEVICETREE=y |
| 67 | CONFIG_BLK_DEV_LOOP=y | 67 | CONFIG_BLK_DEV_LOOP=y |
| 68 | CONFIG_BLK_DEV_RAM=y | 68 | CONFIG_BLK_DEV_RAM=y |
| 69 | CONFIG_BLK_DEV_RAM_SIZE=131072 | 69 | CONFIG_BLK_DEV_RAM_SIZE=131072 |
| 70 | CONFIG_MISC_DEVICES=y | ||
| 71 | CONFIG_EEPROM_LEGACY=y | 70 | CONFIG_EEPROM_LEGACY=y |
| 72 | CONFIG_BLK_DEV_SD=y | 71 | CONFIG_BLK_DEV_SD=y |
| 73 | CONFIG_CHR_DEV_ST=y | 72 | CONFIG_CHR_DEV_ST=y |
| @@ -80,15 +79,14 @@ CONFIG_SATA_FSL=y | |||
| 80 | CONFIG_SATA_SIL24=y | 79 | CONFIG_SATA_SIL24=y |
| 81 | CONFIG_NETDEVICES=y | 80 | CONFIG_NETDEVICES=y |
| 82 | CONFIG_DUMMY=y | 81 | CONFIG_DUMMY=y |
| 82 | CONFIG_FS_ENET=y | ||
| 83 | CONFIG_FSL_PQ_MDIO=y | ||
| 84 | CONFIG_E1000E=y | ||
| 83 | CONFIG_MARVELL_PHY=y | 85 | CONFIG_MARVELL_PHY=y |
| 84 | CONFIG_DAVICOM_PHY=y | 86 | CONFIG_DAVICOM_PHY=y |
| 85 | CONFIG_CICADA_PHY=y | 87 | CONFIG_CICADA_PHY=y |
| 86 | CONFIG_VITESSE_PHY=y | 88 | CONFIG_VITESSE_PHY=y |
| 87 | CONFIG_FIXED_PHY=y | 89 | CONFIG_FIXED_PHY=y |
| 88 | CONFIG_NET_ETHERNET=y | ||
| 89 | CONFIG_FS_ENET=y | ||
| 90 | CONFIG_E1000E=y | ||
| 91 | CONFIG_FSL_PQ_MDIO=y | ||
| 92 | CONFIG_INPUT_FF_MEMLESS=m | 90 | CONFIG_INPUT_FF_MEMLESS=m |
| 93 | # CONFIG_INPUT_MOUSEDEV is not set | 91 | # CONFIG_INPUT_MOUSEDEV is not set |
| 94 | # CONFIG_INPUT_KEYBOARD is not set | 92 | # CONFIG_INPUT_KEYBOARD is not set |
| @@ -98,16 +96,15 @@ CONFIG_SERIAL_8250=y | |||
| 98 | CONFIG_SERIAL_8250_CONSOLE=y | 96 | CONFIG_SERIAL_8250_CONSOLE=y |
| 99 | CONFIG_SERIAL_8250_NR_UARTS=2 | 97 | CONFIG_SERIAL_8250_NR_UARTS=2 |
| 100 | CONFIG_SERIAL_8250_RUNTIME_UARTS=2 | 98 | CONFIG_SERIAL_8250_RUNTIME_UARTS=2 |
| 101 | CONFIG_SERIAL_8250_EXTENDED=y | ||
| 102 | CONFIG_SERIAL_8250_MANY_PORTS=y | 99 | CONFIG_SERIAL_8250_MANY_PORTS=y |
| 103 | CONFIG_SERIAL_8250_DETECT_IRQ=y | 100 | CONFIG_SERIAL_8250_DETECT_IRQ=y |
| 104 | CONFIG_SERIAL_8250_RSA=y | 101 | CONFIG_SERIAL_8250_RSA=y |
| 105 | CONFIG_SERIAL_QE=m | 102 | CONFIG_SERIAL_QE=m |
| 106 | CONFIG_HW_RANDOM=y | ||
| 107 | CONFIG_NVRAM=y | 103 | CONFIG_NVRAM=y |
| 108 | CONFIG_I2C=y | 104 | CONFIG_I2C=y |
| 109 | CONFIG_I2C_CPM=m | 105 | CONFIG_I2C_CPM=m |
| 110 | CONFIG_I2C_MPC=y | 106 | CONFIG_I2C_MPC=y |
| 107 | CONFIG_GPIO_MPC8XXX=y | ||
| 111 | # CONFIG_HWMON is not set | 108 | # CONFIG_HWMON is not set |
| 112 | CONFIG_VIDEO_OUTPUT_CONTROL=y | 109 | CONFIG_VIDEO_OUTPUT_CONTROL=y |
| 113 | CONFIG_SOUND=y | 110 | CONFIG_SOUND=y |
| @@ -123,7 +120,6 @@ CONFIG_DMADEVICES=y | |||
| 123 | CONFIG_FSL_DMA=y | 120 | CONFIG_FSL_DMA=y |
| 124 | # CONFIG_NET_DMA is not set | 121 | # CONFIG_NET_DMA is not set |
| 125 | CONFIG_STAGING=y | 122 | CONFIG_STAGING=y |
| 126 | # CONFIG_STAGING_EXCLUDE_BUILD is not set | ||
| 127 | CONFIG_EXT2_FS=y | 123 | CONFIG_EXT2_FS=y |
| 128 | CONFIG_EXT3_FS=y | 124 | CONFIG_EXT3_FS=y |
| 129 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set | 125 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set |
| @@ -150,22 +146,15 @@ CONFIG_QNX4FS_FS=m | |||
| 150 | CONFIG_SYSV_FS=m | 146 | CONFIG_SYSV_FS=m |
| 151 | CONFIG_UFS_FS=m | 147 | CONFIG_UFS_FS=m |
| 152 | CONFIG_NFS_FS=y | 148 | CONFIG_NFS_FS=y |
| 153 | CONFIG_NFS_V3=y | ||
| 154 | CONFIG_NFS_V4=y | 149 | CONFIG_NFS_V4=y |
| 155 | CONFIG_ROOT_NFS=y | 150 | CONFIG_ROOT_NFS=y |
| 156 | CONFIG_NFSD=y | 151 | CONFIG_NFSD=y |
| 157 | CONFIG_PARTITION_ADVANCED=y | ||
| 158 | CONFIG_MAC_PARTITION=y | ||
| 159 | CONFIG_CRC_T10DIF=y | 152 | CONFIG_CRC_T10DIF=y |
| 160 | CONFIG_FRAME_WARN=8092 | 153 | CONFIG_FRAME_WARN=8092 |
| 161 | CONFIG_DEBUG_FS=y | 154 | CONFIG_DEBUG_FS=y |
| 162 | CONFIG_DEBUG_KERNEL=y | ||
| 163 | CONFIG_DETECT_HUNG_TASK=y | 155 | CONFIG_DETECT_HUNG_TASK=y |
| 164 | # CONFIG_DEBUG_BUGVERBOSE is not set | 156 | # CONFIG_DEBUG_BUGVERBOSE is not set |
| 165 | CONFIG_DEBUG_INFO=y | 157 | CONFIG_DEBUG_INFO=y |
| 166 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 167 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
| 168 | CONFIG_IRQ_DOMAIN_DEBUG=y | ||
| 169 | CONFIG_CRYPTO_PCBC=m | 158 | CONFIG_CRYPTO_PCBC=m |
| 170 | CONFIG_CRYPTO_SHA256=y | 159 | CONFIG_CRYPTO_SHA256=y |
| 171 | CONFIG_CRYPTO_SHA512=y | 160 | CONFIG_CRYPTO_SHA512=y |
diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig index cbb98c1234fd..8b3d57c1ebe8 100644 --- a/arch/powerpc/configs/corenet32_smp_defconfig +++ b/arch/powerpc/configs/corenet32_smp_defconfig | |||
| @@ -6,8 +6,8 @@ CONFIG_SYSVIPC=y | |||
| 6 | CONFIG_POSIX_MQUEUE=y | 6 | CONFIG_POSIX_MQUEUE=y |
| 7 | CONFIG_BSD_PROCESS_ACCT=y | 7 | CONFIG_BSD_PROCESS_ACCT=y |
| 8 | CONFIG_AUDIT=y | 8 | CONFIG_AUDIT=y |
| 9 | CONFIG_SPARSE_IRQ=y | 9 | CONFIG_NO_HZ=y |
| 10 | CONFIG_RCU_TRACE=y | 10 | CONFIG_HIGH_RES_TIMERS=y |
| 11 | CONFIG_IKCONFIG=y | 11 | CONFIG_IKCONFIG=y |
| 12 | CONFIG_IKCONFIG_PROC=y | 12 | CONFIG_IKCONFIG_PROC=y |
| 13 | CONFIG_LOG_BUF_SHIFT=14 | 13 | CONFIG_LOG_BUF_SHIFT=14 |
| @@ -21,23 +21,22 @@ CONFIG_MODULE_UNLOAD=y | |||
| 21 | CONFIG_MODULE_FORCE_UNLOAD=y | 21 | CONFIG_MODULE_FORCE_UNLOAD=y |
| 22 | CONFIG_MODVERSIONS=y | 22 | CONFIG_MODVERSIONS=y |
| 23 | # CONFIG_BLK_DEV_BSG is not set | 23 | # CONFIG_BLK_DEV_BSG is not set |
| 24 | CONFIG_PARTITION_ADVANCED=y | ||
| 25 | CONFIG_MAC_PARTITION=y | ||
| 24 | CONFIG_P2041_RDB=y | 26 | CONFIG_P2041_RDB=y |
| 25 | CONFIG_P3041_DS=y | 27 | CONFIG_P3041_DS=y |
| 26 | CONFIG_P4080_DS=y | 28 | CONFIG_P4080_DS=y |
| 27 | CONFIG_P5020_DS=y | 29 | CONFIG_P5020_DS=y |
| 28 | CONFIG_HIGHMEM=y | 30 | CONFIG_HIGHMEM=y |
| 29 | CONFIG_NO_HZ=y | ||
| 30 | CONFIG_HIGH_RES_TIMERS=y | ||
| 31 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | 31 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set |
| 32 | CONFIG_BINFMT_MISC=m | 32 | CONFIG_BINFMT_MISC=m |
| 33 | CONFIG_KEXEC=y | 33 | CONFIG_KEXEC=y |
| 34 | CONFIG_IRQ_ALL_CPUS=y | 34 | CONFIG_IRQ_ALL_CPUS=y |
| 35 | CONFIG_FORCE_MAX_ZONEORDER=13 | 35 | CONFIG_FORCE_MAX_ZONEORDER=13 |
| 36 | CONFIG_FSL_LBC=y | ||
| 37 | CONFIG_PCI=y | 36 | CONFIG_PCI=y |
| 38 | CONFIG_PCIEPORTBUS=y | 37 | CONFIG_PCIEPORTBUS=y |
| 39 | CONFIG_PCI_MSI=y | ||
| 40 | # CONFIG_PCIEASPM is not set | 38 | # CONFIG_PCIEASPM is not set |
| 39 | CONFIG_PCI_MSI=y | ||
| 41 | CONFIG_RAPIDIO=y | 40 | CONFIG_RAPIDIO=y |
| 42 | CONFIG_FSL_RIO=y | 41 | CONFIG_FSL_RIO=y |
| 43 | CONFIG_NET=y | 42 | CONFIG_NET=y |
| @@ -70,6 +69,7 @@ CONFIG_INET_IPCOMP=y | |||
| 70 | CONFIG_IPV6=y | 69 | CONFIG_IPV6=y |
| 71 | CONFIG_IP_SCTP=m | 70 | CONFIG_IP_SCTP=m |
| 72 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 71 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 72 | CONFIG_DEVTMPFS=y | ||
| 73 | CONFIG_MTD=y | 73 | CONFIG_MTD=y |
| 74 | CONFIG_MTD_CMDLINE_PARTS=y | 74 | CONFIG_MTD_CMDLINE_PARTS=y |
| 75 | CONFIG_MTD_CHAR=y | 75 | CONFIG_MTD_CHAR=y |
| @@ -77,17 +77,14 @@ CONFIG_MTD_BLOCK=y | |||
| 77 | CONFIG_MTD_CFI=y | 77 | CONFIG_MTD_CFI=y |
| 78 | CONFIG_MTD_CFI_AMDSTD=y | 78 | CONFIG_MTD_CFI_AMDSTD=y |
| 79 | CONFIG_MTD_PHYSMAP_OF=y | 79 | CONFIG_MTD_PHYSMAP_OF=y |
| 80 | CONFIG_MTD_M25P80=y | ||
| 80 | CONFIG_MTD_NAND=y | 81 | CONFIG_MTD_NAND=y |
| 81 | CONFIG_MTD_NAND_ECC=y | ||
| 82 | CONFIG_MTD_NAND_IDS=y | ||
| 83 | CONFIG_MTD_NAND_FSL_IFC=y | ||
| 84 | CONFIG_MTD_NAND_FSL_ELBC=y | 82 | CONFIG_MTD_NAND_FSL_ELBC=y |
| 85 | CONFIG_MTD_M25P80=y | 83 | CONFIG_MTD_NAND_FSL_IFC=y |
| 86 | CONFIG_PROC_DEVICETREE=y | 84 | CONFIG_PROC_DEVICETREE=y |
| 87 | CONFIG_BLK_DEV_LOOP=y | 85 | CONFIG_BLK_DEV_LOOP=y |
| 88 | CONFIG_BLK_DEV_RAM=y | 86 | CONFIG_BLK_DEV_RAM=y |
| 89 | CONFIG_BLK_DEV_RAM_SIZE=131072 | 87 | CONFIG_BLK_DEV_RAM_SIZE=131072 |
| 90 | CONFIG_MISC_DEVICES=y | ||
| 91 | CONFIG_BLK_DEV_SD=y | 88 | CONFIG_BLK_DEV_SD=y |
| 92 | CONFIG_CHR_DEV_ST=y | 89 | CONFIG_CHR_DEV_ST=y |
| 93 | CONFIG_BLK_DEV_SR=y | 90 | CONFIG_BLK_DEV_SR=y |
| @@ -115,11 +112,9 @@ CONFIG_SERIO_LIBPS2=y | |||
| 115 | CONFIG_PPC_EPAPR_HV_BYTECHAN=y | 112 | CONFIG_PPC_EPAPR_HV_BYTECHAN=y |
| 116 | CONFIG_SERIAL_8250=y | 113 | CONFIG_SERIAL_8250=y |
| 117 | CONFIG_SERIAL_8250_CONSOLE=y | 114 | CONFIG_SERIAL_8250_CONSOLE=y |
| 118 | CONFIG_SERIAL_8250_EXTENDED=y | ||
| 119 | CONFIG_SERIAL_8250_MANY_PORTS=y | 115 | CONFIG_SERIAL_8250_MANY_PORTS=y |
| 120 | CONFIG_SERIAL_8250_DETECT_IRQ=y | 116 | CONFIG_SERIAL_8250_DETECT_IRQ=y |
| 121 | CONFIG_SERIAL_8250_RSA=y | 117 | CONFIG_SERIAL_8250_RSA=y |
| 122 | CONFIG_HW_RANDOM=y | ||
| 123 | CONFIG_NVRAM=y | 118 | CONFIG_NVRAM=y |
| 124 | CONFIG_I2C=y | 119 | CONFIG_I2C=y |
| 125 | CONFIG_I2C_CHARDEV=y | 120 | CONFIG_I2C_CHARDEV=y |
| @@ -132,7 +127,6 @@ CONFIG_SPI_FSL_ESPI=y | |||
| 132 | CONFIG_VIDEO_OUTPUT_CONTROL=y | 127 | CONFIG_VIDEO_OUTPUT_CONTROL=y |
| 133 | CONFIG_USB_HID=m | 128 | CONFIG_USB_HID=m |
| 134 | CONFIG_USB=y | 129 | CONFIG_USB=y |
| 135 | CONFIG_USB_DEVICEFS=y | ||
| 136 | CONFIG_USB_MON=y | 130 | CONFIG_USB_MON=y |
| 137 | CONFIG_USB_EHCI_HCD=y | 131 | CONFIG_USB_EHCI_HCD=y |
| 138 | CONFIG_USB_EHCI_FSL=y | 132 | CONFIG_USB_EHCI_FSL=y |
| @@ -142,8 +136,6 @@ CONFIG_USB_OHCI_HCD_PPC_OF_LE=y | |||
| 142 | CONFIG_USB_STORAGE=y | 136 | CONFIG_USB_STORAGE=y |
| 143 | CONFIG_MMC=y | 137 | CONFIG_MMC=y |
| 144 | CONFIG_MMC_SDHCI=y | 138 | CONFIG_MMC_SDHCI=y |
| 145 | CONFIG_MMC_SDHCI_OF=y | ||
| 146 | CONFIG_MMC_SDHCI_OF_ESDHC=y | ||
| 147 | CONFIG_EDAC=y | 139 | CONFIG_EDAC=y |
| 148 | CONFIG_EDAC_MM_EDAC=y | 140 | CONFIG_EDAC_MM_EDAC=y |
| 149 | CONFIG_EDAC_MPC85XX=y | 141 | CONFIG_EDAC_MPC85XX=y |
| @@ -170,19 +162,16 @@ CONFIG_HUGETLBFS=y | |||
| 170 | CONFIG_JFFS2_FS=y | 162 | CONFIG_JFFS2_FS=y |
| 171 | CONFIG_CRAMFS=y | 163 | CONFIG_CRAMFS=y |
| 172 | CONFIG_NFS_FS=y | 164 | CONFIG_NFS_FS=y |
| 173 | CONFIG_NFS_V3=y | ||
| 174 | CONFIG_NFS_V4=y | 165 | CONFIG_NFS_V4=y |
| 175 | CONFIG_ROOT_NFS=y | 166 | CONFIG_ROOT_NFS=y |
| 176 | CONFIG_NFSD=m | 167 | CONFIG_NFSD=m |
| 177 | CONFIG_PARTITION_ADVANCED=y | ||
| 178 | CONFIG_MAC_PARTITION=y | ||
| 179 | CONFIG_NLS_ISO8859_1=y | 168 | CONFIG_NLS_ISO8859_1=y |
| 180 | CONFIG_NLS_UTF8=m | 169 | CONFIG_NLS_UTF8=m |
| 181 | CONFIG_MAGIC_SYSRQ=y | 170 | CONFIG_MAGIC_SYSRQ=y |
| 182 | CONFIG_DEBUG_SHIRQ=y | 171 | CONFIG_DEBUG_SHIRQ=y |
| 183 | CONFIG_DETECT_HUNG_TASK=y | 172 | CONFIG_DETECT_HUNG_TASK=y |
| 184 | CONFIG_DEBUG_INFO=y | 173 | CONFIG_DEBUG_INFO=y |
| 185 | CONFIG_SYSCTL_SYSCALL_CHECK=y | 174 | CONFIG_RCU_TRACE=y |
| 186 | CONFIG_CRYPTO_NULL=y | 175 | CONFIG_CRYPTO_NULL=y |
| 187 | CONFIG_CRYPTO_PCBC=m | 176 | CONFIG_CRYPTO_PCBC=m |
| 188 | CONFIG_CRYPTO_MD4=y | 177 | CONFIG_CRYPTO_MD4=y |
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig index dd89de8b0b7f..0516e22ca3de 100644 --- a/arch/powerpc/configs/corenet64_smp_defconfig +++ b/arch/powerpc/configs/corenet64_smp_defconfig | |||
| @@ -56,6 +56,7 @@ CONFIG_INET_ESP=y | |||
| 56 | CONFIG_IPV6=y | 56 | CONFIG_IPV6=y |
| 57 | CONFIG_IP_SCTP=m | 57 | CONFIG_IP_SCTP=m |
| 58 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 58 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 59 | CONFIG_DEVTMPFS=y | ||
| 59 | CONFIG_MTD=y | 60 | CONFIG_MTD=y |
| 60 | CONFIG_MTD_CMDLINE_PARTS=y | 61 | CONFIG_MTD_CMDLINE_PARTS=y |
| 61 | CONFIG_MTD_CHAR=y | 62 | CONFIG_MTD_CHAR=y |
diff --git a/arch/powerpc/configs/g5_defconfig b/arch/powerpc/configs/g5_defconfig index 15130066e5e2..07b7f2af2dca 100644 --- a/arch/powerpc/configs/g5_defconfig +++ b/arch/powerpc/configs/g5_defconfig | |||
| @@ -1,8 +1,10 @@ | |||
| 1 | CONFIG_PPC64=y | ||
| 2 | CONFIG_ALTIVEC=y | ||
| 3 | CONFIG_SMP=y | ||
| 4 | CONFIG_NR_CPUS=4 | ||
| 1 | CONFIG_EXPERIMENTAL=y | 5 | CONFIG_EXPERIMENTAL=y |
| 2 | CONFIG_SYSVIPC=y | 6 | CONFIG_SYSVIPC=y |
| 3 | CONFIG_POSIX_MQUEUE=y | 7 | CONFIG_POSIX_MQUEUE=y |
| 4 | CONFIG_NO_HZ=y | ||
| 5 | CONFIG_HIGH_RES_TIMERS=y | ||
| 6 | CONFIG_IKCONFIG=y | 8 | CONFIG_IKCONFIG=y |
| 7 | CONFIG_IKCONFIG_PROC=y | 9 | CONFIG_IKCONFIG_PROC=y |
| 8 | CONFIG_BLK_DEV_INITRD=y | 10 | CONFIG_BLK_DEV_INITRD=y |
| @@ -13,15 +15,16 @@ CONFIG_MODULES=y | |||
| 13 | CONFIG_MODULE_UNLOAD=y | 15 | CONFIG_MODULE_UNLOAD=y |
| 14 | CONFIG_MODVERSIONS=y | 16 | CONFIG_MODVERSIONS=y |
| 15 | CONFIG_MODULE_SRCVERSION_ALL=y | 17 | CONFIG_MODULE_SRCVERSION_ALL=y |
| 16 | CONFIG_PARTITION_ADVANCED=y | 18 | # CONFIG_PPC_PSERIES is not set |
| 17 | CONFIG_MAC_PARTITION=y | ||
| 18 | CONFIG_SMP=y | ||
| 19 | CONFIG_NR_CPUS=4 | ||
| 20 | CONFIG_KEXEC=y | ||
| 21 | # CONFIG_RELOCATABLE is not set | ||
| 22 | CONFIG_CPU_FREQ=y | 19 | CONFIG_CPU_FREQ=y |
| 23 | CONFIG_CPU_FREQ_GOV_POWERSAVE=y | 20 | CONFIG_CPU_FREQ_GOV_POWERSAVE=y |
| 24 | CONFIG_CPU_FREQ_GOV_USERSPACE=y | 21 | CONFIG_CPU_FREQ_GOV_USERSPACE=y |
| 22 | CONFIG_CPU_FREQ_PMAC64=y | ||
| 23 | CONFIG_NO_HZ=y | ||
| 24 | CONFIG_HIGH_RES_TIMERS=y | ||
| 25 | CONFIG_KEXEC=y | ||
| 26 | CONFIG_IRQ_ALL_CPUS=y | ||
| 27 | # CONFIG_MIGRATION is not set | ||
| 25 | CONFIG_PCI_MSI=y | 28 | CONFIG_PCI_MSI=y |
| 26 | CONFIG_NET=y | 29 | CONFIG_NET=y |
| 27 | CONFIG_PACKET=y | 30 | CONFIG_PACKET=y |
| @@ -49,6 +52,7 @@ CONFIG_NF_CT_NETLINK=m | |||
| 49 | CONFIG_NF_CONNTRACK_IPV4=m | 52 | CONFIG_NF_CONNTRACK_IPV4=m |
| 50 | CONFIG_IP_NF_QUEUE=m | 53 | CONFIG_IP_NF_QUEUE=m |
| 51 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 54 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 55 | CONFIG_PROC_DEVICETREE=y | ||
| 52 | CONFIG_BLK_DEV_LOOP=y | 56 | CONFIG_BLK_DEV_LOOP=y |
| 53 | CONFIG_BLK_DEV_NBD=m | 57 | CONFIG_BLK_DEV_NBD=m |
| 54 | CONFIG_BLK_DEV_RAM=y | 58 | CONFIG_BLK_DEV_RAM=y |
| @@ -56,6 +60,8 @@ CONFIG_BLK_DEV_RAM_SIZE=65536 | |||
| 56 | CONFIG_CDROM_PKTCDVD=m | 60 | CONFIG_CDROM_PKTCDVD=m |
| 57 | CONFIG_IDE=y | 61 | CONFIG_IDE=y |
| 58 | CONFIG_BLK_DEV_IDECD=y | 62 | CONFIG_BLK_DEV_IDECD=y |
| 63 | CONFIG_BLK_DEV_IDE_PMAC=y | ||
| 64 | CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST=y | ||
| 59 | CONFIG_BLK_DEV_SD=y | 65 | CONFIG_BLK_DEV_SD=y |
| 60 | CONFIG_CHR_DEV_ST=y | 66 | CONFIG_CHR_DEV_ST=y |
| 61 | CONFIG_BLK_DEV_SR=y | 67 | CONFIG_BLK_DEV_SR=y |
| @@ -79,24 +85,33 @@ CONFIG_DM_CRYPT=m | |||
| 79 | CONFIG_DM_SNAPSHOT=m | 85 | CONFIG_DM_SNAPSHOT=m |
| 80 | CONFIG_DM_MIRROR=m | 86 | CONFIG_DM_MIRROR=m |
| 81 | CONFIG_DM_ZERO=m | 87 | CONFIG_DM_ZERO=m |
| 82 | CONFIG_MACINTOSH_DRIVERS=y | 88 | CONFIG_IEEE1394=y |
| 89 | CONFIG_IEEE1394_OHCI1394=y | ||
| 90 | CONFIG_IEEE1394_SBP2=m | ||
| 91 | CONFIG_IEEE1394_ETH1394=m | ||
| 92 | CONFIG_IEEE1394_RAWIO=y | ||
| 93 | CONFIG_IEEE1394_VIDEO1394=m | ||
| 94 | CONFIG_IEEE1394_DV1394=m | ||
| 95 | CONFIG_ADB_PMU=y | ||
| 96 | CONFIG_PMAC_SMU=y | ||
| 83 | CONFIG_MAC_EMUMOUSEBTN=y | 97 | CONFIG_MAC_EMUMOUSEBTN=y |
| 98 | CONFIG_THERM_PM72=y | ||
| 99 | CONFIG_WINDFARM=y | ||
| 100 | CONFIG_WINDFARM_PM81=y | ||
| 101 | CONFIG_WINDFARM_PM91=y | ||
| 102 | CONFIG_WINDFARM_PM112=y | ||
| 103 | CONFIG_WINDFARM_PM121=y | ||
| 84 | CONFIG_NETDEVICES=y | 104 | CONFIG_NETDEVICES=y |
| 85 | CONFIG_BONDING=m | ||
| 86 | CONFIG_DUMMY=m | 105 | CONFIG_DUMMY=m |
| 87 | CONFIG_MII=y | 106 | CONFIG_BONDING=m |
| 88 | CONFIG_TUN=m | 107 | CONFIG_TUN=m |
| 108 | CONFIG_NET_ETHERNET=y | ||
| 109 | CONFIG_MII=y | ||
| 110 | CONFIG_SUNGEM=y | ||
| 89 | CONFIG_ACENIC=m | 111 | CONFIG_ACENIC=m |
| 90 | CONFIG_ACENIC_OMIT_TIGON_I=y | 112 | CONFIG_ACENIC_OMIT_TIGON_I=y |
| 91 | CONFIG_TIGON3=y | ||
| 92 | CONFIG_E1000=y | 113 | CONFIG_E1000=y |
| 93 | CONFIG_SUNGEM=y | 114 | CONFIG_TIGON3=y |
| 94 | CONFIG_PPP=m | ||
| 95 | CONFIG_PPP_BSDCOMP=m | ||
| 96 | CONFIG_PPP_DEFLATE=m | ||
| 97 | CONFIG_PPPOE=m | ||
| 98 | CONFIG_PPP_ASYNC=m | ||
| 99 | CONFIG_PPP_SYNC_TTY=m | ||
| 100 | CONFIG_USB_CATC=m | 115 | CONFIG_USB_CATC=m |
| 101 | CONFIG_USB_KAWETH=m | 116 | CONFIG_USB_KAWETH=m |
| 102 | CONFIG_USB_PEGASUS=m | 117 | CONFIG_USB_PEGASUS=m |
| @@ -106,24 +121,36 @@ CONFIG_USB_USBNET=m | |||
| 106 | # CONFIG_USB_NET_NET1080 is not set | 121 | # CONFIG_USB_NET_NET1080 is not set |
| 107 | # CONFIG_USB_NET_CDC_SUBSET is not set | 122 | # CONFIG_USB_NET_CDC_SUBSET is not set |
| 108 | # CONFIG_USB_NET_ZAURUS is not set | 123 | # CONFIG_USB_NET_ZAURUS is not set |
| 124 | CONFIG_PPP=m | ||
| 125 | CONFIG_PPP_ASYNC=m | ||
| 126 | CONFIG_PPP_SYNC_TTY=m | ||
| 127 | CONFIG_PPP_DEFLATE=m | ||
| 128 | CONFIG_PPP_BSDCOMP=m | ||
| 129 | CONFIG_PPPOE=m | ||
| 109 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | 130 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set |
| 110 | CONFIG_INPUT_JOYDEV=m | 131 | CONFIG_INPUT_JOYDEV=m |
| 111 | CONFIG_INPUT_EVDEV=y | 132 | CONFIG_INPUT_EVDEV=y |
| 133 | # CONFIG_KEYBOARD_ATKBD is not set | ||
| 112 | # CONFIG_MOUSE_PS2 is not set | 134 | # CONFIG_MOUSE_PS2 is not set |
| 135 | # CONFIG_SERIO_I8042 is not set | ||
| 113 | # CONFIG_SERIO_SERPORT is not set | 136 | # CONFIG_SERIO_SERPORT is not set |
| 114 | CONFIG_VT_HW_CONSOLE_BINDING=y | ||
| 115 | # CONFIG_HW_RANDOM is not set | 137 | # CONFIG_HW_RANDOM is not set |
| 116 | CONFIG_GEN_RTC=y | 138 | CONFIG_GEN_RTC=y |
| 117 | CONFIG_RAW_DRIVER=y | 139 | CONFIG_RAW_DRIVER=y |
| 118 | CONFIG_I2C_CHARDEV=y | 140 | CONFIG_I2C_CHARDEV=y |
| 119 | # CONFIG_HWMON is not set | 141 | # CONFIG_HWMON is not set |
| 120 | CONFIG_AGP=y | 142 | CONFIG_AGP=m |
| 121 | CONFIG_DRM=y | 143 | CONFIG_AGP_UNINORTH=m |
| 122 | CONFIG_DRM_NOUVEAU=y | ||
| 123 | CONFIG_VIDEO_OUTPUT_CONTROL=m | 144 | CONFIG_VIDEO_OUTPUT_CONTROL=m |
| 145 | CONFIG_FB=y | ||
| 124 | CONFIG_FIRMWARE_EDID=y | 146 | CONFIG_FIRMWARE_EDID=y |
| 125 | CONFIG_FB_TILEBLITTING=y | 147 | CONFIG_FB_TILEBLITTING=y |
| 148 | CONFIG_FB_OF=y | ||
| 149 | CONFIG_FB_NVIDIA=y | ||
| 150 | CONFIG_FB_NVIDIA_I2C=y | ||
| 126 | CONFIG_FB_RADEON=y | 151 | CONFIG_FB_RADEON=y |
| 152 | # CONFIG_VGA_CONSOLE is not set | ||
| 153 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 127 | CONFIG_LOGO=y | 154 | CONFIG_LOGO=y |
| 128 | CONFIG_SOUND=m | 155 | CONFIG_SOUND=m |
| 129 | CONFIG_SND=m | 156 | CONFIG_SND=m |
| @@ -131,7 +158,15 @@ CONFIG_SND_SEQUENCER=m | |||
| 131 | CONFIG_SND_MIXER_OSS=m | 158 | CONFIG_SND_MIXER_OSS=m |
| 132 | CONFIG_SND_PCM_OSS=m | 159 | CONFIG_SND_PCM_OSS=m |
| 133 | CONFIG_SND_SEQUENCER_OSS=y | 160 | CONFIG_SND_SEQUENCER_OSS=y |
| 161 | CONFIG_SND_POWERMAC=m | ||
| 162 | CONFIG_SND_AOA=m | ||
| 163 | CONFIG_SND_AOA_FABRIC_LAYOUT=m | ||
| 164 | CONFIG_SND_AOA_ONYX=m | ||
| 165 | CONFIG_SND_AOA_TAS=m | ||
| 166 | CONFIG_SND_AOA_TOONIE=m | ||
| 134 | CONFIG_SND_USB_AUDIO=m | 167 | CONFIG_SND_USB_AUDIO=m |
| 168 | CONFIG_HID_PID=y | ||
| 169 | CONFIG_USB_HIDDEV=y | ||
| 135 | CONFIG_HID_GYRATION=y | 170 | CONFIG_HID_GYRATION=y |
| 136 | CONFIG_LOGITECH_FF=y | 171 | CONFIG_LOGITECH_FF=y |
| 137 | CONFIG_HID_PANTHERLORD=y | 172 | CONFIG_HID_PANTHERLORD=y |
| @@ -139,12 +174,13 @@ CONFIG_HID_PETALYNX=y | |||
| 139 | CONFIG_HID_SAMSUNG=y | 174 | CONFIG_HID_SAMSUNG=y |
| 140 | CONFIG_HID_SONY=y | 175 | CONFIG_HID_SONY=y |
| 141 | CONFIG_HID_SUNPLUS=y | 176 | CONFIG_HID_SUNPLUS=y |
| 142 | CONFIG_HID_PID=y | ||
| 143 | CONFIG_USB_HIDDEV=y | ||
| 144 | CONFIG_USB=y | 177 | CONFIG_USB=y |
| 178 | CONFIG_USB_DEVICEFS=y | ||
| 145 | CONFIG_USB_MON=y | 179 | CONFIG_USB_MON=y |
| 146 | CONFIG_USB_EHCI_HCD=y | 180 | CONFIG_USB_EHCI_HCD=y |
| 181 | # CONFIG_USB_EHCI_HCD_PPC_OF is not set | ||
| 147 | CONFIG_USB_OHCI_HCD=y | 182 | CONFIG_USB_OHCI_HCD=y |
| 183 | CONFIG_USB_OHCI_HCD_PPC_OF_BE=y | ||
| 148 | CONFIG_USB_ACM=m | 184 | CONFIG_USB_ACM=m |
| 149 | CONFIG_USB_PRINTER=y | 185 | CONFIG_USB_PRINTER=y |
| 150 | CONFIG_USB_STORAGE=y | 186 | CONFIG_USB_STORAGE=y |
| @@ -208,6 +244,8 @@ CONFIG_REISERFS_FS_POSIX_ACL=y | |||
| 208 | CONFIG_REISERFS_FS_SECURITY=y | 244 | CONFIG_REISERFS_FS_SECURITY=y |
| 209 | CONFIG_XFS_FS=m | 245 | CONFIG_XFS_FS=m |
| 210 | CONFIG_XFS_POSIX_ACL=y | 246 | CONFIG_XFS_POSIX_ACL=y |
| 247 | CONFIG_INOTIFY=y | ||
| 248 | CONFIG_AUTOFS_FS=m | ||
| 211 | CONFIG_ISO9660_FS=y | 249 | CONFIG_ISO9660_FS=y |
| 212 | CONFIG_JOLIET=y | 250 | CONFIG_JOLIET=y |
| 213 | CONFIG_ZISOFS=y | 251 | CONFIG_ZISOFS=y |
| @@ -221,12 +259,14 @@ CONFIG_HFS_FS=m | |||
| 221 | CONFIG_HFSPLUS_FS=m | 259 | CONFIG_HFSPLUS_FS=m |
| 222 | CONFIG_CRAMFS=y | 260 | CONFIG_CRAMFS=y |
| 223 | CONFIG_NFS_FS=y | 261 | CONFIG_NFS_FS=y |
| 262 | CONFIG_NFS_V3=y | ||
| 224 | CONFIG_NFS_V3_ACL=y | 263 | CONFIG_NFS_V3_ACL=y |
| 225 | CONFIG_NFS_V4=y | 264 | CONFIG_NFS_V4=y |
| 226 | CONFIG_NFSD=y | 265 | CONFIG_NFSD=y |
| 227 | CONFIG_NFSD_V3_ACL=y | 266 | CONFIG_NFSD_V3_ACL=y |
| 228 | CONFIG_NFSD_V4=y | 267 | CONFIG_NFSD_V4=y |
| 229 | CONFIG_CIFS=m | 268 | CONFIG_CIFS=m |
| 269 | CONFIG_PARTITION_ADVANCED=y | ||
| 230 | CONFIG_NLS_CODEPAGE_437=y | 270 | CONFIG_NLS_CODEPAGE_437=y |
| 231 | CONFIG_NLS_CODEPAGE_1250=y | 271 | CONFIG_NLS_CODEPAGE_1250=y |
| 232 | CONFIG_NLS_CODEPAGE_1251=y | 272 | CONFIG_NLS_CODEPAGE_1251=y |
| @@ -234,23 +274,29 @@ CONFIG_NLS_ASCII=y | |||
| 234 | CONFIG_NLS_ISO8859_1=y | 274 | CONFIG_NLS_ISO8859_1=y |
| 235 | CONFIG_NLS_ISO8859_15=y | 275 | CONFIG_NLS_ISO8859_15=y |
| 236 | CONFIG_NLS_UTF8=y | 276 | CONFIG_NLS_UTF8=y |
| 277 | CONFIG_CRC_T10DIF=y | ||
| 278 | CONFIG_LIBCRC32C=m | ||
| 237 | CONFIG_MAGIC_SYSRQ=y | 279 | CONFIG_MAGIC_SYSRQ=y |
| 238 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 239 | CONFIG_DEBUG_FS=y | 280 | CONFIG_DEBUG_FS=y |
| 240 | CONFIG_DEBUG_KERNEL=y | 281 | CONFIG_DEBUG_KERNEL=y |
| 241 | CONFIG_DEBUG_MUTEXES=y | 282 | CONFIG_DEBUG_MUTEXES=y |
| 283 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 242 | CONFIG_LATENCYTOP=y | 284 | CONFIG_LATENCYTOP=y |
| 243 | CONFIG_STRICT_DEVMEM=y | 285 | CONFIG_SYSCTL_SYSCALL_CHECK=y |
| 286 | CONFIG_BOOTX_TEXT=y | ||
| 244 | CONFIG_CRYPTO_NULL=m | 287 | CONFIG_CRYPTO_NULL=m |
| 245 | CONFIG_CRYPTO_TEST=m | 288 | CONFIG_CRYPTO_TEST=m |
| 289 | CONFIG_CRYPTO_ECB=m | ||
| 246 | CONFIG_CRYPTO_PCBC=m | 290 | CONFIG_CRYPTO_PCBC=m |
| 247 | CONFIG_CRYPTO_HMAC=y | 291 | CONFIG_CRYPTO_HMAC=y |
| 292 | CONFIG_CRYPTO_MD4=m | ||
| 248 | CONFIG_CRYPTO_MICHAEL_MIC=m | 293 | CONFIG_CRYPTO_MICHAEL_MIC=m |
| 249 | CONFIG_CRYPTO_SHA256=m | 294 | CONFIG_CRYPTO_SHA256=m |
| 250 | CONFIG_CRYPTO_SHA512=m | 295 | CONFIG_CRYPTO_SHA512=m |
| 251 | CONFIG_CRYPTO_WP512=m | 296 | CONFIG_CRYPTO_WP512=m |
| 252 | CONFIG_CRYPTO_AES=m | 297 | CONFIG_CRYPTO_AES=m |
| 253 | CONFIG_CRYPTO_ANUBIS=m | 298 | CONFIG_CRYPTO_ANUBIS=m |
| 299 | CONFIG_CRYPTO_ARC4=m | ||
| 254 | CONFIG_CRYPTO_BLOWFISH=m | 300 | CONFIG_CRYPTO_BLOWFISH=m |
| 255 | CONFIG_CRYPTO_CAST5=m | 301 | CONFIG_CRYPTO_CAST5=m |
| 256 | CONFIG_CRYPTO_CAST6=m | 302 | CONFIG_CRYPTO_CAST6=m |
| @@ -260,6 +306,3 @@ CONFIG_CRYPTO_TEA=m | |||
| 260 | CONFIG_CRYPTO_TWOFISH=m | 306 | CONFIG_CRYPTO_TWOFISH=m |
| 261 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | 307 | # CONFIG_CRYPTO_ANSI_CPRNG is not set |
| 262 | # CONFIG_CRYPTO_HW is not set | 308 | # CONFIG_CRYPTO_HW is not set |
| 263 | # CONFIG_VIRTUALIZATION is not set | ||
| 264 | CONFIG_CRC_T10DIF=y | ||
| 265 | CONFIG_LIBCRC32C=m | ||
diff --git a/arch/powerpc/configs/mpc83xx_defconfig b/arch/powerpc/configs/mpc83xx_defconfig index 5aac9a8bc53b..9352e4430c3b 100644 --- a/arch/powerpc/configs/mpc83xx_defconfig +++ b/arch/powerpc/configs/mpc83xx_defconfig | |||
| @@ -2,12 +2,12 @@ CONFIG_EXPERIMENTAL=y | |||
| 2 | CONFIG_SYSVIPC=y | 2 | CONFIG_SYSVIPC=y |
| 3 | CONFIG_LOG_BUF_SHIFT=14 | 3 | CONFIG_LOG_BUF_SHIFT=14 |
| 4 | CONFIG_BLK_DEV_INITRD=y | 4 | CONFIG_BLK_DEV_INITRD=y |
| 5 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | ||
| 6 | CONFIG_EXPERT=y | 5 | CONFIG_EXPERT=y |
| 7 | CONFIG_SLAB=y | 6 | CONFIG_SLAB=y |
| 8 | CONFIG_MODULES=y | 7 | CONFIG_MODULES=y |
| 9 | CONFIG_MODULE_UNLOAD=y | 8 | CONFIG_MODULE_UNLOAD=y |
| 10 | # CONFIG_BLK_DEV_BSG is not set | 9 | # CONFIG_BLK_DEV_BSG is not set |
| 10 | CONFIG_PARTITION_ADVANCED=y | ||
| 11 | # CONFIG_PPC_CHRP is not set | 11 | # CONFIG_PPC_CHRP is not set |
| 12 | # CONFIG_PPC_PMAC is not set | 12 | # CONFIG_PPC_PMAC is not set |
| 13 | CONFIG_PPC_83xx=y | 13 | CONFIG_PPC_83xx=y |
| @@ -25,7 +25,6 @@ CONFIG_ASP834x=y | |||
| 25 | CONFIG_QUICC_ENGINE=y | 25 | CONFIG_QUICC_ENGINE=y |
| 26 | CONFIG_QE_GPIO=y | 26 | CONFIG_QE_GPIO=y |
| 27 | CONFIG_MATH_EMULATION=y | 27 | CONFIG_MATH_EMULATION=y |
| 28 | CONFIG_SPARSE_IRQ=y | ||
| 29 | CONFIG_PCI=y | 28 | CONFIG_PCI=y |
| 30 | CONFIG_NET=y | 29 | CONFIG_NET=y |
| 31 | CONFIG_PACKET=y | 30 | CONFIG_PACKET=y |
| @@ -42,10 +41,9 @@ CONFIG_INET_ESP=y | |||
| 42 | # CONFIG_INET_LRO is not set | 41 | # CONFIG_INET_LRO is not set |
| 43 | # CONFIG_IPV6 is not set | 42 | # CONFIG_IPV6 is not set |
| 44 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 43 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 44 | CONFIG_DEVTMPFS=y | ||
| 45 | # CONFIG_FW_LOADER is not set | 45 | # CONFIG_FW_LOADER is not set |
| 46 | CONFIG_MTD=y | 46 | CONFIG_MTD=y |
| 47 | CONFIG_MTD_PARTITIONS=y | ||
| 48 | CONFIG_MTD_OF_PARTS=y | ||
| 49 | CONFIG_MTD_CHAR=y | 47 | CONFIG_MTD_CHAR=y |
| 50 | CONFIG_MTD_BLOCK=y | 48 | CONFIG_MTD_BLOCK=y |
| 51 | CONFIG_MTD_CFI=y | 49 | CONFIG_MTD_CFI=y |
| @@ -64,15 +62,14 @@ CONFIG_ATA=y | |||
| 64 | CONFIG_SATA_FSL=y | 62 | CONFIG_SATA_FSL=y |
| 65 | CONFIG_SATA_SIL=y | 63 | CONFIG_SATA_SIL=y |
| 66 | CONFIG_NETDEVICES=y | 64 | CONFIG_NETDEVICES=y |
| 65 | CONFIG_MII=y | ||
| 66 | CONFIG_UCC_GETH=y | ||
| 67 | CONFIG_GIANFAR=y | ||
| 67 | CONFIG_MARVELL_PHY=y | 68 | CONFIG_MARVELL_PHY=y |
| 68 | CONFIG_DAVICOM_PHY=y | 69 | CONFIG_DAVICOM_PHY=y |
| 69 | CONFIG_VITESSE_PHY=y | 70 | CONFIG_VITESSE_PHY=y |
| 70 | CONFIG_ICPLUS_PHY=y | 71 | CONFIG_ICPLUS_PHY=y |
| 71 | CONFIG_FIXED_PHY=y | 72 | CONFIG_FIXED_PHY=y |
| 72 | CONFIG_NET_ETHERNET=y | ||
| 73 | CONFIG_MII=y | ||
| 74 | CONFIG_GIANFAR=y | ||
| 75 | CONFIG_UCC_GETH=y | ||
| 76 | CONFIG_INPUT_FF_MEMLESS=m | 73 | CONFIG_INPUT_FF_MEMLESS=m |
| 77 | # CONFIG_INPUT_MOUSEDEV is not set | 74 | # CONFIG_INPUT_MOUSEDEV is not set |
| 78 | # CONFIG_INPUT_KEYBOARD is not set | 75 | # CONFIG_INPUT_KEYBOARD is not set |
| @@ -112,17 +109,12 @@ CONFIG_RTC_DRV_DS1374=y | |||
| 112 | CONFIG_EXT2_FS=y | 109 | CONFIG_EXT2_FS=y |
| 113 | CONFIG_EXT3_FS=y | 110 | CONFIG_EXT3_FS=y |
| 114 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set | 111 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set |
| 115 | CONFIG_INOTIFY=y | ||
| 116 | CONFIG_PROC_KCORE=y | 112 | CONFIG_PROC_KCORE=y |
| 117 | CONFIG_TMPFS=y | 113 | CONFIG_TMPFS=y |
| 118 | CONFIG_NFS_FS=y | 114 | CONFIG_NFS_FS=y |
| 119 | CONFIG_NFS_V3=y | ||
| 120 | CONFIG_NFS_V4=y | 115 | CONFIG_NFS_V4=y |
| 121 | CONFIG_ROOT_NFS=y | 116 | CONFIG_ROOT_NFS=y |
| 122 | CONFIG_PARTITION_ADVANCED=y | ||
| 123 | CONFIG_CRC_T10DIF=y | 117 | CONFIG_CRC_T10DIF=y |
| 124 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 125 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
| 126 | CONFIG_CRYPTO_ECB=m | 118 | CONFIG_CRYPTO_ECB=m |
| 127 | CONFIG_CRYPTO_PCBC=m | 119 | CONFIG_CRYPTO_PCBC=m |
| 128 | CONFIG_CRYPTO_SHA256=y | 120 | CONFIG_CRYPTO_SHA256=y |
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig index 03ee911c4577..8b5bda27d248 100644 --- a/arch/powerpc/configs/mpc85xx_defconfig +++ b/arch/powerpc/configs/mpc85xx_defconfig | |||
| @@ -5,7 +5,9 @@ CONFIG_SYSVIPC=y | |||
| 5 | CONFIG_POSIX_MQUEUE=y | 5 | CONFIG_POSIX_MQUEUE=y |
| 6 | CONFIG_BSD_PROCESS_ACCT=y | 6 | CONFIG_BSD_PROCESS_ACCT=y |
| 7 | CONFIG_AUDIT=y | 7 | CONFIG_AUDIT=y |
| 8 | CONFIG_SPARSE_IRQ=y | 8 | CONFIG_IRQ_DOMAIN_DEBUG=y |
| 9 | CONFIG_NO_HZ=y | ||
| 10 | CONFIG_HIGH_RES_TIMERS=y | ||
| 9 | CONFIG_IKCONFIG=y | 11 | CONFIG_IKCONFIG=y |
| 10 | CONFIG_IKCONFIG_PROC=y | 12 | CONFIG_IKCONFIG_PROC=y |
| 11 | CONFIG_LOG_BUF_SHIFT=14 | 13 | CONFIG_LOG_BUF_SHIFT=14 |
| @@ -17,6 +19,8 @@ CONFIG_MODULE_UNLOAD=y | |||
| 17 | CONFIG_MODULE_FORCE_UNLOAD=y | 19 | CONFIG_MODULE_FORCE_UNLOAD=y |
| 18 | CONFIG_MODVERSIONS=y | 20 | CONFIG_MODVERSIONS=y |
| 19 | # CONFIG_BLK_DEV_BSG is not set | 21 | # CONFIG_BLK_DEV_BSG is not set |
| 22 | CONFIG_PARTITION_ADVANCED=y | ||
| 23 | CONFIG_MAC_PARTITION=y | ||
| 20 | CONFIG_MPC8540_ADS=y | 24 | CONFIG_MPC8540_ADS=y |
| 21 | CONFIG_MPC8560_ADS=y | 25 | CONFIG_MPC8560_ADS=y |
| 22 | CONFIG_MPC85xx_CDS=y | 26 | CONFIG_MPC85xx_CDS=y |
| @@ -40,8 +44,6 @@ CONFIG_SBC8548=y | |||
| 40 | CONFIG_QUICC_ENGINE=y | 44 | CONFIG_QUICC_ENGINE=y |
| 41 | CONFIG_QE_GPIO=y | 45 | CONFIG_QE_GPIO=y |
| 42 | CONFIG_HIGHMEM=y | 46 | CONFIG_HIGHMEM=y |
| 43 | CONFIG_NO_HZ=y | ||
| 44 | CONFIG_HIGH_RES_TIMERS=y | ||
| 45 | CONFIG_BINFMT_MISC=m | 47 | CONFIG_BINFMT_MISC=m |
| 46 | CONFIG_MATH_EMULATION=y | 48 | CONFIG_MATH_EMULATION=y |
| 47 | CONFIG_FORCE_MAX_ZONEORDER=12 | 49 | CONFIG_FORCE_MAX_ZONEORDER=12 |
| @@ -74,36 +76,25 @@ CONFIG_INET_ESP=y | |||
| 74 | CONFIG_IPV6=y | 76 | CONFIG_IPV6=y |
| 75 | CONFIG_IP_SCTP=m | 77 | CONFIG_IP_SCTP=m |
| 76 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 78 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 79 | CONFIG_DEVTMPFS=y | ||
| 77 | CONFIG_MTD=y | 80 | CONFIG_MTD=y |
| 78 | CONFIG_MTD_CMDLINE_PARTS=y | 81 | CONFIG_MTD_CMDLINE_PARTS=y |
| 79 | CONFIG_MTD_CHAR=y | 82 | CONFIG_MTD_CHAR=y |
| 80 | CONFIG_MTD_BLOCK=y | 83 | CONFIG_MTD_BLOCK=y |
| 81 | CONFIG_MTD_CFI=y | ||
| 82 | CONFIG_FTL=y | 84 | CONFIG_FTL=y |
| 83 | CONFIG_MTD_GEN_PROBE=y | 85 | CONFIG_MTD_CFI=y |
| 84 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 85 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 86 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 87 | CONFIG_MTD_CFI_I1=y | ||
| 88 | CONFIG_MTD_CFI_I2=y | ||
| 89 | CONFIG_MTD_CFI_INTELEXT=y | 86 | CONFIG_MTD_CFI_INTELEXT=y |
| 90 | CONFIG_MTD_CFI_AMDSTD=y | 87 | CONFIG_MTD_CFI_AMDSTD=y |
| 91 | CONFIG_MTD_CFI_UTIL=y | ||
| 92 | CONFIG_MTD_PHYSMAP_OF=y | 88 | CONFIG_MTD_PHYSMAP_OF=y |
| 93 | CONFIG_MTD_PARTITIONS=y | 89 | CONFIG_MTD_M25P80=y |
| 94 | CONFIG_MTD_OF_PARTS=y | ||
| 95 | CONFIG_MTD_NAND=y | 90 | CONFIG_MTD_NAND=y |
| 96 | CONFIG_MTD_NAND_FSL_ELBC=y | 91 | CONFIG_MTD_NAND_FSL_ELBC=y |
| 97 | CONFIG_MTD_NAND_FSL_IFC=y | 92 | CONFIG_MTD_NAND_FSL_IFC=y |
| 98 | CONFIG_MTD_NAND_IDS=y | ||
| 99 | CONFIG_MTD_NAND_ECC=y | ||
| 100 | CONFIG_MTD_M25P80=y | ||
| 101 | CONFIG_PROC_DEVICETREE=y | 93 | CONFIG_PROC_DEVICETREE=y |
| 102 | CONFIG_BLK_DEV_LOOP=y | 94 | CONFIG_BLK_DEV_LOOP=y |
| 103 | CONFIG_BLK_DEV_NBD=y | 95 | CONFIG_BLK_DEV_NBD=y |
| 104 | CONFIG_BLK_DEV_RAM=y | 96 | CONFIG_BLK_DEV_RAM=y |
| 105 | CONFIG_BLK_DEV_RAM_SIZE=131072 | 97 | CONFIG_BLK_DEV_RAM_SIZE=131072 |
| 106 | CONFIG_MISC_DEVICES=y | ||
| 107 | CONFIG_EEPROM_LEGACY=y | 98 | CONFIG_EEPROM_LEGACY=y |
| 108 | CONFIG_BLK_DEV_SD=y | 99 | CONFIG_BLK_DEV_SD=y |
| 109 | CONFIG_CHR_DEV_ST=y | 100 | CONFIG_CHR_DEV_ST=y |
| @@ -115,6 +106,7 @@ CONFIG_ATA=y | |||
| 115 | CONFIG_SATA_AHCI=y | 106 | CONFIG_SATA_AHCI=y |
| 116 | CONFIG_SATA_FSL=y | 107 | CONFIG_SATA_FSL=y |
| 117 | CONFIG_PATA_ALI=y | 108 | CONFIG_PATA_ALI=y |
| 109 | CONFIG_PATA_VIA=y | ||
| 118 | CONFIG_NETDEVICES=y | 110 | CONFIG_NETDEVICES=y |
| 119 | CONFIG_DUMMY=y | 111 | CONFIG_DUMMY=y |
| 120 | CONFIG_FS_ENET=y | 112 | CONFIG_FS_ENET=y |
| @@ -134,7 +126,6 @@ CONFIG_SERIAL_8250=y | |||
| 134 | CONFIG_SERIAL_8250_CONSOLE=y | 126 | CONFIG_SERIAL_8250_CONSOLE=y |
| 135 | CONFIG_SERIAL_8250_NR_UARTS=2 | 127 | CONFIG_SERIAL_8250_NR_UARTS=2 |
| 136 | CONFIG_SERIAL_8250_RUNTIME_UARTS=2 | 128 | CONFIG_SERIAL_8250_RUNTIME_UARTS=2 |
| 137 | CONFIG_SERIAL_8250_EXTENDED=y | ||
| 138 | CONFIG_SERIAL_8250_MANY_PORTS=y | 129 | CONFIG_SERIAL_8250_MANY_PORTS=y |
| 139 | CONFIG_SERIAL_8250_DETECT_IRQ=y | 130 | CONFIG_SERIAL_8250_DETECT_IRQ=y |
| 140 | CONFIG_SERIAL_8250_RSA=y | 131 | CONFIG_SERIAL_8250_RSA=y |
| @@ -183,7 +174,6 @@ CONFIG_HID_SAMSUNG=y | |||
| 183 | CONFIG_HID_SONY=y | 174 | CONFIG_HID_SONY=y |
| 184 | CONFIG_HID_SUNPLUS=y | 175 | CONFIG_HID_SUNPLUS=y |
| 185 | CONFIG_USB=y | 176 | CONFIG_USB=y |
| 186 | CONFIG_USB_DEVICEFS=y | ||
| 187 | CONFIG_USB_MON=y | 177 | CONFIG_USB_MON=y |
| 188 | CONFIG_USB_EHCI_HCD=y | 178 | CONFIG_USB_EHCI_HCD=y |
| 189 | CONFIG_USB_EHCI_FSL=y | 179 | CONFIG_USB_EHCI_FSL=y |
| @@ -229,18 +219,13 @@ CONFIG_QNX4FS_FS=m | |||
| 229 | CONFIG_SYSV_FS=m | 219 | CONFIG_SYSV_FS=m |
| 230 | CONFIG_UFS_FS=m | 220 | CONFIG_UFS_FS=m |
| 231 | CONFIG_NFS_FS=y | 221 | CONFIG_NFS_FS=y |
| 232 | CONFIG_NFS_V3=y | ||
| 233 | CONFIG_NFS_V4=y | 222 | CONFIG_NFS_V4=y |
| 234 | CONFIG_ROOT_NFS=y | 223 | CONFIG_ROOT_NFS=y |
| 235 | CONFIG_NFSD=y | 224 | CONFIG_NFSD=y |
| 236 | CONFIG_PARTITION_ADVANCED=y | ||
| 237 | CONFIG_MAC_PARTITION=y | ||
| 238 | CONFIG_CRC_T10DIF=y | 225 | CONFIG_CRC_T10DIF=y |
| 239 | CONFIG_DEBUG_FS=y | 226 | CONFIG_DEBUG_FS=y |
| 240 | CONFIG_DETECT_HUNG_TASK=y | 227 | CONFIG_DETECT_HUNG_TASK=y |
| 241 | CONFIG_DEBUG_INFO=y | 228 | CONFIG_DEBUG_INFO=y |
| 242 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
| 243 | CONFIG_IRQ_DOMAIN_DEBUG=y | ||
| 244 | CONFIG_CRYPTO_PCBC=m | 229 | CONFIG_CRYPTO_PCBC=m |
| 245 | CONFIG_CRYPTO_SHA256=y | 230 | CONFIG_CRYPTO_SHA256=y |
| 246 | CONFIG_CRYPTO_SHA512=y | 231 | CONFIG_CRYPTO_SHA512=y |
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig index fdfa84dc908f..b0974e7e98ae 100644 --- a/arch/powerpc/configs/mpc85xx_smp_defconfig +++ b/arch/powerpc/configs/mpc85xx_smp_defconfig | |||
| @@ -7,7 +7,9 @@ CONFIG_SYSVIPC=y | |||
| 7 | CONFIG_POSIX_MQUEUE=y | 7 | CONFIG_POSIX_MQUEUE=y |
| 8 | CONFIG_BSD_PROCESS_ACCT=y | 8 | CONFIG_BSD_PROCESS_ACCT=y |
| 9 | CONFIG_AUDIT=y | 9 | CONFIG_AUDIT=y |
| 10 | CONFIG_SPARSE_IRQ=y | 10 | CONFIG_IRQ_DOMAIN_DEBUG=y |
| 11 | CONFIG_NO_HZ=y | ||
| 12 | CONFIG_HIGH_RES_TIMERS=y | ||
| 11 | CONFIG_IKCONFIG=y | 13 | CONFIG_IKCONFIG=y |
| 12 | CONFIG_IKCONFIG_PROC=y | 14 | CONFIG_IKCONFIG_PROC=y |
| 13 | CONFIG_LOG_BUF_SHIFT=14 | 15 | CONFIG_LOG_BUF_SHIFT=14 |
| @@ -19,6 +21,8 @@ CONFIG_MODULE_UNLOAD=y | |||
| 19 | CONFIG_MODULE_FORCE_UNLOAD=y | 21 | CONFIG_MODULE_FORCE_UNLOAD=y |
| 20 | CONFIG_MODVERSIONS=y | 22 | CONFIG_MODVERSIONS=y |
| 21 | # CONFIG_BLK_DEV_BSG is not set | 23 | # CONFIG_BLK_DEV_BSG is not set |
| 24 | CONFIG_PARTITION_ADVANCED=y | ||
| 25 | CONFIG_MAC_PARTITION=y | ||
| 22 | CONFIG_MPC8540_ADS=y | 26 | CONFIG_MPC8540_ADS=y |
| 23 | CONFIG_MPC8560_ADS=y | 27 | CONFIG_MPC8560_ADS=y |
| 24 | CONFIG_MPC85xx_CDS=y | 28 | CONFIG_MPC85xx_CDS=y |
| @@ -42,8 +46,6 @@ CONFIG_SBC8548=y | |||
| 42 | CONFIG_QUICC_ENGINE=y | 46 | CONFIG_QUICC_ENGINE=y |
| 43 | CONFIG_QE_GPIO=y | 47 | CONFIG_QE_GPIO=y |
| 44 | CONFIG_HIGHMEM=y | 48 | CONFIG_HIGHMEM=y |
| 45 | CONFIG_NO_HZ=y | ||
| 46 | CONFIG_HIGH_RES_TIMERS=y | ||
| 47 | CONFIG_BINFMT_MISC=m | 49 | CONFIG_BINFMT_MISC=m |
| 48 | CONFIG_MATH_EMULATION=y | 50 | CONFIG_MATH_EMULATION=y |
| 49 | CONFIG_IRQ_ALL_CPUS=y | 51 | CONFIG_IRQ_ALL_CPUS=y |
| @@ -77,36 +79,25 @@ CONFIG_INET_ESP=y | |||
| 77 | CONFIG_IPV6=y | 79 | CONFIG_IPV6=y |
| 78 | CONFIG_IP_SCTP=m | 80 | CONFIG_IP_SCTP=m |
| 79 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 81 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 82 | CONFIG_DEVTMPFS=y | ||
| 80 | CONFIG_MTD=y | 83 | CONFIG_MTD=y |
| 81 | CONFIG_MTD_CMDLINE_PARTS=y | 84 | CONFIG_MTD_CMDLINE_PARTS=y |
| 82 | CONFIG_MTD_CHAR=y | 85 | CONFIG_MTD_CHAR=y |
| 83 | CONFIG_MTD_BLOCK=y | 86 | CONFIG_MTD_BLOCK=y |
| 84 | CONFIG_MTD_CFI=y | ||
| 85 | CONFIG_FTL=y | 87 | CONFIG_FTL=y |
| 86 | CONFIG_MTD_GEN_PROBE=y | 88 | CONFIG_MTD_CFI=y |
| 87 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 88 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 89 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 90 | CONFIG_MTD_CFI_I1=y | ||
| 91 | CONFIG_MTD_CFI_I2=y | ||
| 92 | CONFIG_MTD_CFI_INTELEXT=y | 89 | CONFIG_MTD_CFI_INTELEXT=y |
| 93 | CONFIG_MTD_CFI_AMDSTD=y | 90 | CONFIG_MTD_CFI_AMDSTD=y |
| 94 | CONFIG_MTD_CFI_UTIL=y | ||
| 95 | CONFIG_MTD_PHYSMAP_OF=y | 91 | CONFIG_MTD_PHYSMAP_OF=y |
| 96 | CONFIG_MTD_PARTITIONS=y | 92 | CONFIG_MTD_M25P80=y |
| 97 | CONFIG_MTD_OF_PARTS=y | ||
| 98 | CONFIG_MTD_NAND=y | 93 | CONFIG_MTD_NAND=y |
| 99 | CONFIG_MTD_NAND_FSL_ELBC=y | 94 | CONFIG_MTD_NAND_FSL_ELBC=y |
| 100 | CONFIG_MTD_NAND_FSL_IFC=y | 95 | CONFIG_MTD_NAND_FSL_IFC=y |
| 101 | CONFIG_MTD_NAND_IDS=y | ||
| 102 | CONFIG_MTD_NAND_ECC=y | ||
| 103 | CONFIG_MTD_M25P80=y | ||
| 104 | CONFIG_PROC_DEVICETREE=y | 96 | CONFIG_PROC_DEVICETREE=y |
| 105 | CONFIG_BLK_DEV_LOOP=y | 97 | CONFIG_BLK_DEV_LOOP=y |
| 106 | CONFIG_BLK_DEV_NBD=y | 98 | CONFIG_BLK_DEV_NBD=y |
| 107 | CONFIG_BLK_DEV_RAM=y | 99 | CONFIG_BLK_DEV_RAM=y |
| 108 | CONFIG_BLK_DEV_RAM_SIZE=131072 | 100 | CONFIG_BLK_DEV_RAM_SIZE=131072 |
| 109 | CONFIG_MISC_DEVICES=y | ||
| 110 | CONFIG_EEPROM_LEGACY=y | 101 | CONFIG_EEPROM_LEGACY=y |
| 111 | CONFIG_BLK_DEV_SD=y | 102 | CONFIG_BLK_DEV_SD=y |
| 112 | CONFIG_CHR_DEV_ST=y | 103 | CONFIG_CHR_DEV_ST=y |
| @@ -137,7 +128,6 @@ CONFIG_SERIAL_8250=y | |||
| 137 | CONFIG_SERIAL_8250_CONSOLE=y | 128 | CONFIG_SERIAL_8250_CONSOLE=y |
| 138 | CONFIG_SERIAL_8250_NR_UARTS=2 | 129 | CONFIG_SERIAL_8250_NR_UARTS=2 |
| 139 | CONFIG_SERIAL_8250_RUNTIME_UARTS=2 | 130 | CONFIG_SERIAL_8250_RUNTIME_UARTS=2 |
| 140 | CONFIG_SERIAL_8250_EXTENDED=y | ||
| 141 | CONFIG_SERIAL_8250_MANY_PORTS=y | 131 | CONFIG_SERIAL_8250_MANY_PORTS=y |
| 142 | CONFIG_SERIAL_8250_DETECT_IRQ=y | 132 | CONFIG_SERIAL_8250_DETECT_IRQ=y |
| 143 | CONFIG_SERIAL_8250_RSA=y | 133 | CONFIG_SERIAL_8250_RSA=y |
| @@ -186,7 +176,6 @@ CONFIG_HID_SAMSUNG=y | |||
| 186 | CONFIG_HID_SONY=y | 176 | CONFIG_HID_SONY=y |
| 187 | CONFIG_HID_SUNPLUS=y | 177 | CONFIG_HID_SUNPLUS=y |
| 188 | CONFIG_USB=y | 178 | CONFIG_USB=y |
| 189 | CONFIG_USB_DEVICEFS=y | ||
| 190 | CONFIG_USB_MON=y | 179 | CONFIG_USB_MON=y |
| 191 | CONFIG_USB_EHCI_HCD=y | 180 | CONFIG_USB_EHCI_HCD=y |
| 192 | CONFIG_USB_EHCI_FSL=y | 181 | CONFIG_USB_EHCI_FSL=y |
| @@ -232,18 +221,13 @@ CONFIG_QNX4FS_FS=m | |||
| 232 | CONFIG_SYSV_FS=m | 221 | CONFIG_SYSV_FS=m |
| 233 | CONFIG_UFS_FS=m | 222 | CONFIG_UFS_FS=m |
| 234 | CONFIG_NFS_FS=y | 223 | CONFIG_NFS_FS=y |
| 235 | CONFIG_NFS_V3=y | ||
| 236 | CONFIG_NFS_V4=y | 224 | CONFIG_NFS_V4=y |
| 237 | CONFIG_ROOT_NFS=y | 225 | CONFIG_ROOT_NFS=y |
| 238 | CONFIG_NFSD=y | 226 | CONFIG_NFSD=y |
| 239 | CONFIG_PARTITION_ADVANCED=y | ||
| 240 | CONFIG_MAC_PARTITION=y | ||
| 241 | CONFIG_CRC_T10DIF=y | 227 | CONFIG_CRC_T10DIF=y |
| 242 | CONFIG_DEBUG_FS=y | 228 | CONFIG_DEBUG_FS=y |
| 243 | CONFIG_DETECT_HUNG_TASK=y | 229 | CONFIG_DETECT_HUNG_TASK=y |
| 244 | CONFIG_DEBUG_INFO=y | 230 | CONFIG_DEBUG_INFO=y |
| 245 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
| 246 | CONFIG_IRQ_DOMAIN_DEBUG=y | ||
| 247 | CONFIG_CRYPTO_PCBC=m | 231 | CONFIG_CRYPTO_PCBC=m |
| 248 | CONFIG_CRYPTO_SHA256=y | 232 | CONFIG_CRYPTO_SHA256=y |
| 249 | CONFIG_CRYPTO_SHA512=y | 233 | CONFIG_CRYPTO_SHA512=y |
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h index 50d82c8a037f..b3c083de17ad 100644 --- a/arch/powerpc/include/asm/cputable.h +++ b/arch/powerpc/include/asm/cputable.h | |||
| @@ -553,9 +553,7 @@ static inline int cpu_has_feature(unsigned long feature) | |||
| 553 | & feature); | 553 | & feature); |
| 554 | } | 554 | } |
| 555 | 555 | ||
| 556 | #ifdef CONFIG_HAVE_HW_BREAKPOINT | ||
| 557 | #define HBP_NUM 1 | 556 | #define HBP_NUM 1 |
| 558 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | ||
| 559 | 557 | ||
| 560 | #endif /* !__ASSEMBLY__ */ | 558 | #endif /* !__ASSEMBLY__ */ |
| 561 | 559 | ||
diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h index 50ea12fd7bf5..a8bf5c673a3c 100644 --- a/arch/powerpc/include/asm/kvm_host.h +++ b/arch/powerpc/include/asm/kvm_host.h | |||
| @@ -33,6 +33,7 @@ | |||
| 33 | #include <asm/kvm_asm.h> | 33 | #include <asm/kvm_asm.h> |
| 34 | #include <asm/processor.h> | 34 | #include <asm/processor.h> |
| 35 | #include <asm/page.h> | 35 | #include <asm/page.h> |
| 36 | #include <asm/cacheflush.h> | ||
| 36 | 37 | ||
| 37 | #define KVM_MAX_VCPUS NR_CPUS | 38 | #define KVM_MAX_VCPUS NR_CPUS |
| 38 | #define KVM_MAX_VCORES NR_CPUS | 39 | #define KVM_MAX_VCORES NR_CPUS |
diff --git a/arch/powerpc/include/asm/kvm_ppc.h b/arch/powerpc/include/asm/kvm_ppc.h index 0124937a23b9..e006f0bdea95 100644 --- a/arch/powerpc/include/asm/kvm_ppc.h +++ b/arch/powerpc/include/asm/kvm_ppc.h | |||
| @@ -219,4 +219,16 @@ void kvmppc_claim_lpid(long lpid); | |||
| 219 | void kvmppc_free_lpid(long lpid); | 219 | void kvmppc_free_lpid(long lpid); |
| 220 | void kvmppc_init_lpid(unsigned long nr_lpids); | 220 | void kvmppc_init_lpid(unsigned long nr_lpids); |
| 221 | 221 | ||
| 222 | static inline void kvmppc_mmu_flush_icache(pfn_t pfn) | ||
| 223 | { | ||
| 224 | /* Clear i-cache for new pages */ | ||
| 225 | struct page *page; | ||
| 226 | page = pfn_to_page(pfn); | ||
| 227 | if (!test_bit(PG_arch_1, &page->flags)) { | ||
| 228 | flush_dcache_icache_page(page); | ||
| 229 | set_bit(PG_arch_1, &page->flags); | ||
| 230 | } | ||
| 231 | } | ||
| 232 | |||
| 233 | |||
| 222 | #endif /* __POWERPC_KVM_PPC_H__ */ | 234 | #endif /* __POWERPC_KVM_PPC_H__ */ |
diff --git a/arch/powerpc/include/asm/mpic_msgr.h b/arch/powerpc/include/asm/mpic_msgr.h index 326d33ca55cd..d4f471fb1031 100644 --- a/arch/powerpc/include/asm/mpic_msgr.h +++ b/arch/powerpc/include/asm/mpic_msgr.h | |||
| @@ -14,6 +14,7 @@ | |||
| 14 | #include <linux/types.h> | 14 | #include <linux/types.h> |
| 15 | #include <linux/spinlock.h> | 15 | #include <linux/spinlock.h> |
| 16 | #include <asm/smp.h> | 16 | #include <asm/smp.h> |
| 17 | #include <asm/io.h> | ||
| 17 | 18 | ||
| 18 | struct mpic_msgr { | 19 | struct mpic_msgr { |
| 19 | u32 __iomem *base; | 20 | u32 __iomem *base; |
diff --git a/arch/powerpc/kernel/dma-iommu.c b/arch/powerpc/kernel/dma-iommu.c index 2d7bb8ced136..e4897523de41 100644 --- a/arch/powerpc/kernel/dma-iommu.c +++ b/arch/powerpc/kernel/dma-iommu.c | |||
| @@ -83,11 +83,10 @@ static int dma_iommu_dma_supported(struct device *dev, u64 mask) | |||
| 83 | return 0; | 83 | return 0; |
| 84 | } | 84 | } |
| 85 | 85 | ||
| 86 | if ((tbl->it_offset + tbl->it_size) > (mask >> IOMMU_PAGE_SHIFT)) { | 86 | if (tbl->it_offset > (mask >> IOMMU_PAGE_SHIFT)) { |
| 87 | dev_info(dev, "Warning: IOMMU window too big for device mask\n"); | 87 | dev_info(dev, "Warning: IOMMU offset too big for device mask\n"); |
| 88 | dev_info(dev, "mask: 0x%08llx, table end: 0x%08lx\n", | 88 | dev_info(dev, "mask: 0x%08llx, table offset: 0x%08lx\n", |
| 89 | mask, (tbl->it_offset + tbl->it_size) << | 89 | mask, tbl->it_offset << IOMMU_PAGE_SHIFT); |
| 90 | IOMMU_PAGE_SHIFT); | ||
| 91 | return 0; | 90 | return 0; |
| 92 | } else | 91 | } else |
| 93 | return 1; | 92 | return 1; |
diff --git a/arch/powerpc/kernel/hw_breakpoint.c b/arch/powerpc/kernel/hw_breakpoint.c index f3a82dde61db..956a4c496de9 100644 --- a/arch/powerpc/kernel/hw_breakpoint.c +++ b/arch/powerpc/kernel/hw_breakpoint.c | |||
| @@ -253,7 +253,7 @@ int __kprobes hw_breakpoint_handler(struct die_args *args) | |||
| 253 | 253 | ||
| 254 | /* Do not emulate user-space instructions, instead single-step them */ | 254 | /* Do not emulate user-space instructions, instead single-step them */ |
| 255 | if (user_mode(regs)) { | 255 | if (user_mode(regs)) { |
| 256 | bp->ctx->task->thread.last_hit_ubp = bp; | 256 | current->thread.last_hit_ubp = bp; |
| 257 | regs->msr |= MSR_SE; | 257 | regs->msr |= MSR_SE; |
| 258 | goto out; | 258 | goto out; |
| 259 | } | 259 | } |
diff --git a/arch/powerpc/kernel/kgdb.c b/arch/powerpc/kernel/kgdb.c index 782bd0a3c2f0..c470a40b29f5 100644 --- a/arch/powerpc/kernel/kgdb.c +++ b/arch/powerpc/kernel/kgdb.c | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | #include <asm/processor.h> | 25 | #include <asm/processor.h> |
| 26 | #include <asm/machdep.h> | 26 | #include <asm/machdep.h> |
| 27 | #include <asm/debug.h> | 27 | #include <asm/debug.h> |
| 28 | #include <linux/slab.h> | ||
| 28 | 29 | ||
| 29 | /* | 30 | /* |
| 30 | * This table contains the mapping between PowerPC hardware trap types, and | 31 | * This table contains the mapping between PowerPC hardware trap types, and |
| @@ -101,6 +102,21 @@ static int computeSignal(unsigned int tt) | |||
| 101 | return SIGHUP; /* default for things we don't know about */ | 102 | return SIGHUP; /* default for things we don't know about */ |
| 102 | } | 103 | } |
| 103 | 104 | ||
| 105 | /** | ||
| 106 | * | ||
| 107 | * kgdb_skipexception - Bail out of KGDB when we've been triggered. | ||
| 108 | * @exception: Exception vector number | ||
| 109 | * @regs: Current &struct pt_regs. | ||
| 110 | * | ||
| 111 | * On some architectures we need to skip a breakpoint exception when | ||
| 112 | * it occurs after a breakpoint has been removed. | ||
| 113 | * | ||
| 114 | */ | ||
| 115 | int kgdb_skipexception(int exception, struct pt_regs *regs) | ||
| 116 | { | ||
| 117 | return kgdb_isremovedbreak(regs->nip); | ||
| 118 | } | ||
| 119 | |||
| 104 | static int kgdb_call_nmi_hook(struct pt_regs *regs) | 120 | static int kgdb_call_nmi_hook(struct pt_regs *regs) |
| 105 | { | 121 | { |
| 106 | kgdb_nmicallback(raw_smp_processor_id(), regs); | 122 | kgdb_nmicallback(raw_smp_processor_id(), regs); |
| @@ -138,6 +154,8 @@ static int kgdb_handle_breakpoint(struct pt_regs *regs) | |||
| 138 | static int kgdb_singlestep(struct pt_regs *regs) | 154 | static int kgdb_singlestep(struct pt_regs *regs) |
| 139 | { | 155 | { |
| 140 | struct thread_info *thread_info, *exception_thread_info; | 156 | struct thread_info *thread_info, *exception_thread_info; |
| 157 | struct thread_info *backup_current_thread_info = \ | ||
| 158 | (struct thread_info *)kmalloc(sizeof(struct thread_info), GFP_KERNEL); | ||
| 141 | 159 | ||
| 142 | if (user_mode(regs)) | 160 | if (user_mode(regs)) |
| 143 | return 0; | 161 | return 0; |
| @@ -155,13 +173,17 @@ static int kgdb_singlestep(struct pt_regs *regs) | |||
| 155 | thread_info = (struct thread_info *)(regs->gpr[1] & ~(THREAD_SIZE-1)); | 173 | thread_info = (struct thread_info *)(regs->gpr[1] & ~(THREAD_SIZE-1)); |
| 156 | exception_thread_info = current_thread_info(); | 174 | exception_thread_info = current_thread_info(); |
| 157 | 175 | ||
| 158 | if (thread_info != exception_thread_info) | 176 | if (thread_info != exception_thread_info) { |
| 177 | /* Save the original current_thread_info. */ | ||
| 178 | memcpy(backup_current_thread_info, exception_thread_info, sizeof *thread_info); | ||
| 159 | memcpy(exception_thread_info, thread_info, sizeof *thread_info); | 179 | memcpy(exception_thread_info, thread_info, sizeof *thread_info); |
| 180 | } | ||
| 160 | 181 | ||
| 161 | kgdb_handle_exception(0, SIGTRAP, 0, regs); | 182 | kgdb_handle_exception(0, SIGTRAP, 0, regs); |
| 162 | 183 | ||
| 163 | if (thread_info != exception_thread_info) | 184 | if (thread_info != exception_thread_info) |
| 164 | memcpy(thread_info, exception_thread_info, sizeof *thread_info); | 185 | /* Restore current_thread_info lastly. */ |
| 186 | memcpy(exception_thread_info, backup_current_thread_info, sizeof *thread_info); | ||
| 165 | 187 | ||
| 166 | return 1; | 188 | return 1; |
| 167 | } | 189 | } |
| @@ -410,7 +432,6 @@ int kgdb_arch_handle_exception(int vector, int signo, int err_code, | |||
| 410 | #else | 432 | #else |
| 411 | linux_regs->msr |= MSR_SE; | 433 | linux_regs->msr |= MSR_SE; |
| 412 | #endif | 434 | #endif |
| 413 | kgdb_single_step = 1; | ||
| 414 | atomic_set(&kgdb_cpu_doing_single_step, | 435 | atomic_set(&kgdb_cpu_doing_single_step, |
| 415 | raw_smp_processor_id()); | 436 | raw_smp_processor_id()); |
| 416 | } | 437 | } |
diff --git a/arch/powerpc/kernel/syscalls.c b/arch/powerpc/kernel/syscalls.c index f2496f2faecc..4e3cc47f26b9 100644 --- a/arch/powerpc/kernel/syscalls.c +++ b/arch/powerpc/kernel/syscalls.c | |||
| @@ -107,11 +107,11 @@ long ppc64_personality(unsigned long personality) | |||
| 107 | long ret; | 107 | long ret; |
| 108 | 108 | ||
| 109 | if (personality(current->personality) == PER_LINUX32 | 109 | if (personality(current->personality) == PER_LINUX32 |
| 110 | && personality == PER_LINUX) | 110 | && personality(personality) == PER_LINUX) |
| 111 | personality = PER_LINUX32; | 111 | personality = (personality & ~PER_MASK) | PER_LINUX32; |
| 112 | ret = sys_personality(personality); | 112 | ret = sys_personality(personality); |
| 113 | if (ret == PER_LINUX32) | 113 | if (personality(ret) == PER_LINUX32) |
| 114 | ret = PER_LINUX; | 114 | ret = (ret & ~PER_MASK) | PER_LINUX; |
| 115 | return ret; | 115 | return ret; |
| 116 | } | 116 | } |
| 117 | #endif | 117 | #endif |
diff --git a/arch/powerpc/kvm/book3s_32_mmu_host.c b/arch/powerpc/kvm/book3s_32_mmu_host.c index f922c29bb234..837f13e7b6bf 100644 --- a/arch/powerpc/kvm/book3s_32_mmu_host.c +++ b/arch/powerpc/kvm/book3s_32_mmu_host.c | |||
| @@ -211,6 +211,9 @@ next_pteg: | |||
| 211 | pteg1 |= PP_RWRX; | 211 | pteg1 |= PP_RWRX; |
| 212 | } | 212 | } |
| 213 | 213 | ||
| 214 | if (orig_pte->may_execute) | ||
| 215 | kvmppc_mmu_flush_icache(hpaddr >> PAGE_SHIFT); | ||
| 216 | |||
| 214 | local_irq_disable(); | 217 | local_irq_disable(); |
| 215 | 218 | ||
| 216 | if (pteg[rr]) { | 219 | if (pteg[rr]) { |
diff --git a/arch/powerpc/kvm/book3s_64_mmu_host.c b/arch/powerpc/kvm/book3s_64_mmu_host.c index 10fc8ec9d2a8..0688b6b39585 100644 --- a/arch/powerpc/kvm/book3s_64_mmu_host.c +++ b/arch/powerpc/kvm/book3s_64_mmu_host.c | |||
| @@ -126,6 +126,8 @@ int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *orig_pte) | |||
| 126 | 126 | ||
| 127 | if (!orig_pte->may_execute) | 127 | if (!orig_pte->may_execute) |
| 128 | rflags |= HPTE_R_N; | 128 | rflags |= HPTE_R_N; |
| 129 | else | ||
| 130 | kvmppc_mmu_flush_icache(hpaddr >> PAGE_SHIFT); | ||
| 129 | 131 | ||
| 130 | hash = hpt_hash(va, PTE_SIZE, MMU_SEGSIZE_256M); | 132 | hash = hpt_hash(va, PTE_SIZE, MMU_SEGSIZE_256M); |
| 131 | 133 | ||
diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S index 5a84c8d3d040..44b72feaff7d 100644 --- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S +++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S | |||
| @@ -1421,13 +1421,13 @@ _GLOBAL(kvmppc_h_cede) | |||
| 1421 | sync /* order setting ceded vs. testing prodded */ | 1421 | sync /* order setting ceded vs. testing prodded */ |
| 1422 | lbz r5,VCPU_PRODDED(r3) | 1422 | lbz r5,VCPU_PRODDED(r3) |
| 1423 | cmpwi r5,0 | 1423 | cmpwi r5,0 |
| 1424 | bne 1f | 1424 | bne kvm_cede_prodded |
| 1425 | li r0,0 /* set trap to 0 to say hcall is handled */ | 1425 | li r0,0 /* set trap to 0 to say hcall is handled */ |
| 1426 | stw r0,VCPU_TRAP(r3) | 1426 | stw r0,VCPU_TRAP(r3) |
| 1427 | li r0,H_SUCCESS | 1427 | li r0,H_SUCCESS |
| 1428 | std r0,VCPU_GPR(R3)(r3) | 1428 | std r0,VCPU_GPR(R3)(r3) |
| 1429 | BEGIN_FTR_SECTION | 1429 | BEGIN_FTR_SECTION |
| 1430 | b 2f /* just send it up to host on 970 */ | 1430 | b kvm_cede_exit /* just send it up to host on 970 */ |
| 1431 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206) | 1431 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206) |
| 1432 | 1432 | ||
| 1433 | /* | 1433 | /* |
| @@ -1446,7 +1446,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206) | |||
| 1446 | or r4,r4,r0 | 1446 | or r4,r4,r0 |
| 1447 | PPC_POPCNTW(R7,R4) | 1447 | PPC_POPCNTW(R7,R4) |
| 1448 | cmpw r7,r8 | 1448 | cmpw r7,r8 |
| 1449 | bge 2f | 1449 | bge kvm_cede_exit |
| 1450 | stwcx. r4,0,r6 | 1450 | stwcx. r4,0,r6 |
| 1451 | bne 31b | 1451 | bne 31b |
| 1452 | li r0,1 | 1452 | li r0,1 |
| @@ -1555,7 +1555,8 @@ kvm_end_cede: | |||
| 1555 | b hcall_real_fallback | 1555 | b hcall_real_fallback |
| 1556 | 1556 | ||
| 1557 | /* cede when already previously prodded case */ | 1557 | /* cede when already previously prodded case */ |
| 1558 | 1: li r0,0 | 1558 | kvm_cede_prodded: |
| 1559 | li r0,0 | ||
| 1559 | stb r0,VCPU_PRODDED(r3) | 1560 | stb r0,VCPU_PRODDED(r3) |
| 1560 | sync /* order testing prodded vs. clearing ceded */ | 1561 | sync /* order testing prodded vs. clearing ceded */ |
| 1561 | stb r0,VCPU_CEDED(r3) | 1562 | stb r0,VCPU_CEDED(r3) |
| @@ -1563,7 +1564,8 @@ kvm_end_cede: | |||
| 1563 | blr | 1564 | blr |
| 1564 | 1565 | ||
| 1565 | /* we've ceded but we want to give control to the host */ | 1566 | /* we've ceded but we want to give control to the host */ |
| 1566 | 2: li r3,H_TOO_HARD | 1567 | kvm_cede_exit: |
| 1568 | li r3,H_TOO_HARD | ||
| 1567 | blr | 1569 | blr |
| 1568 | 1570 | ||
| 1569 | secondary_too_late: | 1571 | secondary_too_late: |
diff --git a/arch/powerpc/kvm/e500_tlb.c b/arch/powerpc/kvm/e500_tlb.c index c510fc961302..a2b66717813d 100644 --- a/arch/powerpc/kvm/e500_tlb.c +++ b/arch/powerpc/kvm/e500_tlb.c | |||
| @@ -322,11 +322,11 @@ static inline void kvmppc_e500_ref_release(struct tlbe_ref *ref) | |||
| 322 | static void clear_tlb1_bitmap(struct kvmppc_vcpu_e500 *vcpu_e500) | 322 | static void clear_tlb1_bitmap(struct kvmppc_vcpu_e500 *vcpu_e500) |
| 323 | { | 323 | { |
| 324 | if (vcpu_e500->g2h_tlb1_map) | 324 | if (vcpu_e500->g2h_tlb1_map) |
| 325 | memset(vcpu_e500->g2h_tlb1_map, | 325 | memset(vcpu_e500->g2h_tlb1_map, 0, |
| 326 | sizeof(u64) * vcpu_e500->gtlb_params[1].entries, 0); | 326 | sizeof(u64) * vcpu_e500->gtlb_params[1].entries); |
| 327 | if (vcpu_e500->h2g_tlb1_rmap) | 327 | if (vcpu_e500->h2g_tlb1_rmap) |
| 328 | memset(vcpu_e500->h2g_tlb1_rmap, | 328 | memset(vcpu_e500->h2g_tlb1_rmap, 0, |
| 329 | sizeof(unsigned int) * host_tlb_params[1].entries, 0); | 329 | sizeof(unsigned int) * host_tlb_params[1].entries); |
| 330 | } | 330 | } |
| 331 | 331 | ||
| 332 | static void clear_tlb_privs(struct kvmppc_vcpu_e500 *vcpu_e500) | 332 | static void clear_tlb_privs(struct kvmppc_vcpu_e500 *vcpu_e500) |
| @@ -539,6 +539,9 @@ static inline void kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500, | |||
| 539 | 539 | ||
| 540 | kvmppc_e500_setup_stlbe(&vcpu_e500->vcpu, gtlbe, tsize, | 540 | kvmppc_e500_setup_stlbe(&vcpu_e500->vcpu, gtlbe, tsize, |
| 541 | ref, gvaddr, stlbe); | 541 | ref, gvaddr, stlbe); |
| 542 | |||
| 543 | /* Clear i-cache for new pages */ | ||
| 544 | kvmppc_mmu_flush_icache(pfn); | ||
| 542 | } | 545 | } |
| 543 | 546 | ||
| 544 | /* XXX only map the one-one case, for now use TLB0 */ | 547 | /* XXX only map the one-one case, for now use TLB0 */ |
diff --git a/arch/powerpc/lib/copyuser_power7.S b/arch/powerpc/lib/copyuser_power7.S index f9ede7c6606e..0d24ff15f5f6 100644 --- a/arch/powerpc/lib/copyuser_power7.S +++ b/arch/powerpc/lib/copyuser_power7.S | |||
| @@ -288,7 +288,7 @@ err1; stb r0,0(r3) | |||
| 288 | std r0,16(r1) | 288 | std r0,16(r1) |
| 289 | stdu r1,-STACKFRAMESIZE(r1) | 289 | stdu r1,-STACKFRAMESIZE(r1) |
| 290 | bl .enter_vmx_usercopy | 290 | bl .enter_vmx_usercopy |
| 291 | cmpwi r3,0 | 291 | cmpwi cr1,r3,0 |
| 292 | ld r0,STACKFRAMESIZE+16(r1) | 292 | ld r0,STACKFRAMESIZE+16(r1) |
| 293 | ld r3,STACKFRAMESIZE+48(r1) | 293 | ld r3,STACKFRAMESIZE+48(r1) |
| 294 | ld r4,STACKFRAMESIZE+56(r1) | 294 | ld r4,STACKFRAMESIZE+56(r1) |
| @@ -326,38 +326,7 @@ err1; stb r0,0(r3) | |||
| 326 | dcbt r0,r8,0b01010 /* GO */ | 326 | dcbt r0,r8,0b01010 /* GO */ |
| 327 | .machine pop | 327 | .machine pop |
| 328 | 328 | ||
| 329 | /* | 329 | beq cr1,.Lunwind_stack_nonvmx_copy |
| 330 | * We prefetch both the source and destination using enhanced touch | ||
| 331 | * instructions. We use a stream ID of 0 for the load side and | ||
| 332 | * 1 for the store side. | ||
| 333 | */ | ||
| 334 | clrrdi r6,r4,7 | ||
| 335 | clrrdi r9,r3,7 | ||
| 336 | ori r9,r9,1 /* stream=1 */ | ||
| 337 | |||
| 338 | srdi r7,r5,7 /* length in cachelines, capped at 0x3FF */ | ||
| 339 | cmpldi cr1,r7,0x3FF | ||
| 340 | ble cr1,1f | ||
| 341 | li r7,0x3FF | ||
| 342 | 1: lis r0,0x0E00 /* depth=7 */ | ||
| 343 | sldi r7,r7,7 | ||
| 344 | or r7,r7,r0 | ||
| 345 | ori r10,r7,1 /* stream=1 */ | ||
| 346 | |||
| 347 | lis r8,0x8000 /* GO=1 */ | ||
| 348 | clrldi r8,r8,32 | ||
| 349 | |||
| 350 | .machine push | ||
| 351 | .machine "power4" | ||
| 352 | dcbt r0,r6,0b01000 | ||
| 353 | dcbt r0,r7,0b01010 | ||
| 354 | dcbtst r0,r9,0b01000 | ||
| 355 | dcbtst r0,r10,0b01010 | ||
| 356 | eieio | ||
| 357 | dcbt r0,r8,0b01010 /* GO */ | ||
| 358 | .machine pop | ||
| 359 | |||
| 360 | beq .Lunwind_stack_nonvmx_copy | ||
| 361 | 330 | ||
| 362 | /* | 331 | /* |
| 363 | * If source and destination are not relatively aligned we use a | 332 | * If source and destination are not relatively aligned we use a |
diff --git a/arch/powerpc/lib/memcpy_power7.S b/arch/powerpc/lib/memcpy_power7.S index 0efdc51bc716..7ba6c96de778 100644 --- a/arch/powerpc/lib/memcpy_power7.S +++ b/arch/powerpc/lib/memcpy_power7.S | |||
| @@ -222,7 +222,7 @@ _GLOBAL(memcpy_power7) | |||
| 222 | std r0,16(r1) | 222 | std r0,16(r1) |
| 223 | stdu r1,-STACKFRAMESIZE(r1) | 223 | stdu r1,-STACKFRAMESIZE(r1) |
| 224 | bl .enter_vmx_copy | 224 | bl .enter_vmx_copy |
| 225 | cmpwi r3,0 | 225 | cmpwi cr1,r3,0 |
| 226 | ld r0,STACKFRAMESIZE+16(r1) | 226 | ld r0,STACKFRAMESIZE+16(r1) |
| 227 | ld r3,STACKFRAMESIZE+48(r1) | 227 | ld r3,STACKFRAMESIZE+48(r1) |
| 228 | ld r4,STACKFRAMESIZE+56(r1) | 228 | ld r4,STACKFRAMESIZE+56(r1) |
| @@ -260,7 +260,7 @@ _GLOBAL(memcpy_power7) | |||
| 260 | dcbt r0,r8,0b01010 /* GO */ | 260 | dcbt r0,r8,0b01010 /* GO */ |
| 261 | .machine pop | 261 | .machine pop |
| 262 | 262 | ||
| 263 | beq .Lunwind_stack_nonvmx_copy | 263 | beq cr1,.Lunwind_stack_nonvmx_copy |
| 264 | 264 | ||
| 265 | /* | 265 | /* |
| 266 | * If source and destination are not relatively aligned we use a | 266 | * If source and destination are not relatively aligned we use a |
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c index baaafde7d135..fbdad0e3929a 100644 --- a/arch/powerpc/mm/mem.c +++ b/arch/powerpc/mm/mem.c | |||
| @@ -469,6 +469,7 @@ void flush_dcache_icache_page(struct page *page) | |||
| 469 | __flush_dcache_icache_phys(page_to_pfn(page) << PAGE_SHIFT); | 469 | __flush_dcache_icache_phys(page_to_pfn(page) << PAGE_SHIFT); |
| 470 | #endif | 470 | #endif |
| 471 | } | 471 | } |
| 472 | EXPORT_SYMBOL(flush_dcache_icache_page); | ||
| 472 | 473 | ||
| 473 | void clear_user_page(void *page, unsigned long vaddr, struct page *pg) | 474 | void clear_user_page(void *page, unsigned long vaddr, struct page *pg) |
| 474 | { | 475 | { |
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c index 77b49ddda9d3..7cd2dbd6e4c4 100644 --- a/arch/powerpc/perf/core-book3s.c +++ b/arch/powerpc/perf/core-book3s.c | |||
| @@ -1431,7 +1431,7 @@ static void perf_event_interrupt(struct pt_regs *regs) | |||
| 1431 | if (!event->hw.idx || is_limited_pmc(event->hw.idx)) | 1431 | if (!event->hw.idx || is_limited_pmc(event->hw.idx)) |
| 1432 | continue; | 1432 | continue; |
| 1433 | val = read_pmc(event->hw.idx); | 1433 | val = read_pmc(event->hw.idx); |
| 1434 | if ((int)val < 0) { | 1434 | if (pmc_overflow(val)) { |
| 1435 | /* event has overflowed */ | 1435 | /* event has overflowed */ |
| 1436 | found = 1; | 1436 | found = 1; |
| 1437 | record_and_restart(event, val, regs); | 1437 | record_and_restart(event, val, regs); |
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index a7b2a600d0a4..c37f46136321 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c | |||
| @@ -465,7 +465,7 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary) | |||
| 465 | iounmap(hose->cfg_data); | 465 | iounmap(hose->cfg_data); |
| 466 | iounmap(hose->cfg_addr); | 466 | iounmap(hose->cfg_addr); |
| 467 | pcibios_free_controller(hose); | 467 | pcibios_free_controller(hose); |
| 468 | return 0; | 468 | return -ENODEV; |
| 469 | } | 469 | } |
| 470 | 470 | ||
| 471 | setup_pci_cmd(hose); | 471 | setup_pci_cmd(hose); |
| @@ -827,6 +827,7 @@ struct device_node *fsl_pci_primary; | |||
| 827 | 827 | ||
| 828 | void __devinit fsl_pci_init(void) | 828 | void __devinit fsl_pci_init(void) |
| 829 | { | 829 | { |
| 830 | int ret; | ||
| 830 | struct device_node *node; | 831 | struct device_node *node; |
| 831 | struct pci_controller *hose; | 832 | struct pci_controller *hose; |
| 832 | dma_addr_t max = 0xffffffff; | 833 | dma_addr_t max = 0xffffffff; |
| @@ -855,10 +856,12 @@ void __devinit fsl_pci_init(void) | |||
| 855 | if (!fsl_pci_primary) | 856 | if (!fsl_pci_primary) |
| 856 | fsl_pci_primary = node; | 857 | fsl_pci_primary = node; |
| 857 | 858 | ||
| 858 | fsl_add_bridge(node, fsl_pci_primary == node); | 859 | ret = fsl_add_bridge(node, fsl_pci_primary == node); |
| 859 | hose = pci_find_hose_for_OF_device(node); | 860 | if (ret == 0) { |
| 860 | max = min(max, hose->dma_window_base_cur + | 861 | hose = pci_find_hose_for_OF_device(node); |
| 861 | hose->dma_window_size); | 862 | max = min(max, hose->dma_window_base_cur + |
| 863 | hose->dma_window_size); | ||
| 864 | } | ||
| 862 | } | 865 | } |
| 863 | } | 866 | } |
| 864 | 867 | ||
diff --git a/arch/powerpc/sysdev/mpic_msgr.c b/arch/powerpc/sysdev/mpic_msgr.c index 483d8fa72e8b..e961f8c4a8f0 100644 --- a/arch/powerpc/sysdev/mpic_msgr.c +++ b/arch/powerpc/sysdev/mpic_msgr.c | |||
| @@ -14,6 +14,9 @@ | |||
| 14 | #include <linux/list.h> | 14 | #include <linux/list.h> |
| 15 | #include <linux/of_platform.h> | 15 | #include <linux/of_platform.h> |
| 16 | #include <linux/errno.h> | 16 | #include <linux/errno.h> |
| 17 | #include <linux/err.h> | ||
| 18 | #include <linux/export.h> | ||
| 19 | #include <linux/slab.h> | ||
| 17 | #include <asm/prom.h> | 20 | #include <asm/prom.h> |
| 18 | #include <asm/hw_irq.h> | 21 | #include <asm/hw_irq.h> |
| 19 | #include <asm/ppc-pci.h> | 22 | #include <asm/ppc-pci.h> |
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c index eab3492a45c5..9b49c65ee7a4 100644 --- a/arch/powerpc/xmon/xmon.c +++ b/arch/powerpc/xmon/xmon.c | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | #include <linux/reboot.h> | 17 | #include <linux/reboot.h> |
| 18 | #include <linux/delay.h> | 18 | #include <linux/delay.h> |
| 19 | #include <linux/kallsyms.h> | 19 | #include <linux/kallsyms.h> |
| 20 | #include <linux/kmsg_dump.h> | ||
| 20 | #include <linux/cpumask.h> | 21 | #include <linux/cpumask.h> |
| 21 | #include <linux/export.h> | 22 | #include <linux/export.h> |
| 22 | #include <linux/sysrq.h> | 23 | #include <linux/sysrq.h> |
| @@ -894,13 +895,13 @@ cmds(struct pt_regs *excp) | |||
| 894 | #endif | 895 | #endif |
| 895 | default: | 896 | default: |
| 896 | printf("Unrecognized command: "); | 897 | printf("Unrecognized command: "); |
| 897 | do { | 898 | do { |
| 898 | if (' ' < cmd && cmd <= '~') | 899 | if (' ' < cmd && cmd <= '~') |
| 899 | putchar(cmd); | 900 | putchar(cmd); |
| 900 | else | 901 | else |
| 901 | printf("\\x%x", cmd); | 902 | printf("\\x%x", cmd); |
| 902 | cmd = inchar(); | 903 | cmd = inchar(); |
| 903 | } while (cmd != '\n'); | 904 | } while (cmd != '\n'); |
| 904 | printf(" (type ? for help)\n"); | 905 | printf(" (type ? for help)\n"); |
| 905 | break; | 906 | break; |
| 906 | } | 907 | } |
| @@ -1097,7 +1098,7 @@ static long check_bp_loc(unsigned long addr) | |||
| 1097 | return 1; | 1098 | return 1; |
| 1098 | } | 1099 | } |
| 1099 | 1100 | ||
| 1100 | static char *breakpoint_help_string = | 1101 | static char *breakpoint_help_string = |
| 1101 | "Breakpoint command usage:\n" | 1102 | "Breakpoint command usage:\n" |
| 1102 | "b show breakpoints\n" | 1103 | "b show breakpoints\n" |
| 1103 | "b <addr> [cnt] set breakpoint at given instr addr\n" | 1104 | "b <addr> [cnt] set breakpoint at given instr addr\n" |
| @@ -1193,7 +1194,7 @@ bpt_cmds(void) | |||
| 1193 | 1194 | ||
| 1194 | default: | 1195 | default: |
| 1195 | termch = cmd; | 1196 | termch = cmd; |
| 1196 | cmd = skipbl(); | 1197 | cmd = skipbl(); |
| 1197 | if (cmd == '?') { | 1198 | if (cmd == '?') { |
| 1198 | printf(breakpoint_help_string); | 1199 | printf(breakpoint_help_string); |
| 1199 | break; | 1200 | break; |
| @@ -1359,7 +1360,7 @@ static void xmon_show_stack(unsigned long sp, unsigned long lr, | |||
| 1359 | sp + REGS_OFFSET); | 1360 | sp + REGS_OFFSET); |
| 1360 | break; | 1361 | break; |
| 1361 | } | 1362 | } |
| 1362 | printf("--- Exception: %lx %s at ", regs.trap, | 1363 | printf("--- Exception: %lx %s at ", regs.trap, |
| 1363 | getvecname(TRAP(®s))); | 1364 | getvecname(TRAP(®s))); |
| 1364 | pc = regs.nip; | 1365 | pc = regs.nip; |
| 1365 | lr = regs.link; | 1366 | lr = regs.link; |
| @@ -1623,14 +1624,14 @@ static void super_regs(void) | |||
| 1623 | 1624 | ||
| 1624 | cmd = skipbl(); | 1625 | cmd = skipbl(); |
| 1625 | if (cmd == '\n') { | 1626 | if (cmd == '\n') { |
| 1626 | unsigned long sp, toc; | 1627 | unsigned long sp, toc; |
| 1627 | asm("mr %0,1" : "=r" (sp) :); | 1628 | asm("mr %0,1" : "=r" (sp) :); |
| 1628 | asm("mr %0,2" : "=r" (toc) :); | 1629 | asm("mr %0,2" : "=r" (toc) :); |
| 1629 | 1630 | ||
| 1630 | printf("msr = "REG" sprg0= "REG"\n", | 1631 | printf("msr = "REG" sprg0= "REG"\n", |
| 1631 | mfmsr(), mfspr(SPRN_SPRG0)); | 1632 | mfmsr(), mfspr(SPRN_SPRG0)); |
| 1632 | printf("pvr = "REG" sprg1= "REG"\n", | 1633 | printf("pvr = "REG" sprg1= "REG"\n", |
| 1633 | mfspr(SPRN_PVR), mfspr(SPRN_SPRG1)); | 1634 | mfspr(SPRN_PVR), mfspr(SPRN_SPRG1)); |
| 1634 | printf("dec = "REG" sprg2= "REG"\n", | 1635 | printf("dec = "REG" sprg2= "REG"\n", |
| 1635 | mfspr(SPRN_DEC), mfspr(SPRN_SPRG2)); | 1636 | mfspr(SPRN_DEC), mfspr(SPRN_SPRG2)); |
| 1636 | printf("sp = "REG" sprg3= "REG"\n", sp, mfspr(SPRN_SPRG3)); | 1637 | printf("sp = "REG" sprg3= "REG"\n", sp, mfspr(SPRN_SPRG3)); |
| @@ -1783,7 +1784,7 @@ byterev(unsigned char *val, int size) | |||
| 1783 | static int brev; | 1784 | static int brev; |
| 1784 | static int mnoread; | 1785 | static int mnoread; |
| 1785 | 1786 | ||
| 1786 | static char *memex_help_string = | 1787 | static char *memex_help_string = |
| 1787 | "Memory examine command usage:\n" | 1788 | "Memory examine command usage:\n" |
| 1788 | "m [addr] [flags] examine/change memory\n" | 1789 | "m [addr] [flags] examine/change memory\n" |
| 1789 | " addr is optional. will start where left off.\n" | 1790 | " addr is optional. will start where left off.\n" |
| @@ -1798,7 +1799,7 @@ static char *memex_help_string = | |||
| 1798 | "NOTE: flags are saved as defaults\n" | 1799 | "NOTE: flags are saved as defaults\n" |
| 1799 | ""; | 1800 | ""; |
| 1800 | 1801 | ||
| 1801 | static char *memex_subcmd_help_string = | 1802 | static char *memex_subcmd_help_string = |
| 1802 | "Memory examine subcommands:\n" | 1803 | "Memory examine subcommands:\n" |
| 1803 | " hexval write this val to current location\n" | 1804 | " hexval write this val to current location\n" |
| 1804 | " 'string' write chars from string to this location\n" | 1805 | " 'string' write chars from string to this location\n" |
| @@ -2064,7 +2065,7 @@ prdump(unsigned long adrs, long ndump) | |||
| 2064 | nr = mread(adrs, temp, r); | 2065 | nr = mread(adrs, temp, r); |
| 2065 | adrs += nr; | 2066 | adrs += nr; |
| 2066 | for (m = 0; m < r; ++m) { | 2067 | for (m = 0; m < r; ++m) { |
| 2067 | if ((m & (sizeof(long) - 1)) == 0 && m > 0) | 2068 | if ((m & (sizeof(long) - 1)) == 0 && m > 0) |
| 2068 | putchar(' '); | 2069 | putchar(' '); |
| 2069 | if (m < nr) | 2070 | if (m < nr) |
| 2070 | printf("%.2x", temp[m]); | 2071 | printf("%.2x", temp[m]); |
| @@ -2072,7 +2073,7 @@ prdump(unsigned long adrs, long ndump) | |||
| 2072 | printf("%s", fault_chars[fault_type]); | 2073 | printf("%s", fault_chars[fault_type]); |
| 2073 | } | 2074 | } |
| 2074 | for (; m < 16; ++m) { | 2075 | for (; m < 16; ++m) { |
| 2075 | if ((m & (sizeof(long) - 1)) == 0) | 2076 | if ((m & (sizeof(long) - 1)) == 0) |
| 2076 | putchar(' '); | 2077 | putchar(' '); |
| 2077 | printf(" "); | 2078 | printf(" "); |
| 2078 | } | 2079 | } |
| @@ -2148,45 +2149,28 @@ print_address(unsigned long addr) | |||
| 2148 | void | 2149 | void |
| 2149 | dump_log_buf(void) | 2150 | dump_log_buf(void) |
| 2150 | { | 2151 | { |
| 2151 | const unsigned long size = 128; | 2152 | struct kmsg_dumper dumper = { .active = 1 }; |
| 2152 | unsigned long end, addr; | 2153 | unsigned char buf[128]; |
| 2153 | unsigned char buf[size + 1]; | 2154 | size_t len; |
| 2154 | 2155 | ||
| 2155 | addr = 0; | 2156 | if (setjmp(bus_error_jmp) != 0) { |
| 2156 | buf[size] = '\0'; | 2157 | printf("Error dumping printk buffer!\n"); |
| 2157 | 2158 | return; | |
| 2158 | if (setjmp(bus_error_jmp) != 0) { | 2159 | } |
| 2159 | printf("Unable to lookup symbol __log_buf!\n"); | 2160 | |
| 2160 | return; | 2161 | catch_memory_errors = 1; |
| 2161 | } | 2162 | sync(); |
| 2162 | 2163 | ||
| 2163 | catch_memory_errors = 1; | 2164 | kmsg_dump_rewind_nolock(&dumper); |
| 2164 | sync(); | 2165 | while (kmsg_dump_get_line_nolock(&dumper, false, buf, sizeof(buf), &len)) { |
| 2165 | addr = kallsyms_lookup_name("__log_buf"); | 2166 | buf[len] = '\0'; |
| 2166 | 2167 | printf("%s", buf); | |
| 2167 | if (! addr) | 2168 | } |
| 2168 | printf("Symbol __log_buf not found!\n"); | 2169 | |
| 2169 | else { | 2170 | sync(); |
| 2170 | end = addr + (1 << CONFIG_LOG_BUF_SHIFT); | 2171 | /* wait a little while to see if we get a machine check */ |
| 2171 | while (addr < end) { | 2172 | __delay(200); |
| 2172 | if (! mread(addr, buf, size)) { | 2173 | catch_memory_errors = 0; |
| 2173 | printf("Can't read memory at address 0x%lx\n", addr); | ||
| 2174 | break; | ||
| 2175 | } | ||
| 2176 | |||
| 2177 | printf("%s", buf); | ||
| 2178 | |||
| 2179 | if (strlen(buf) < size) | ||
| 2180 | break; | ||
| 2181 | |||
| 2182 | addr += size; | ||
| 2183 | } | ||
| 2184 | } | ||
| 2185 | |||
| 2186 | sync(); | ||
| 2187 | /* wait a little while to see if we get a machine check */ | ||
| 2188 | __delay(200); | ||
| 2189 | catch_memory_errors = 0; | ||
| 2190 | } | 2174 | } |
| 2191 | 2175 | ||
| 2192 | /* | 2176 | /* |
diff --git a/arch/s390/include/asm/elf.h b/arch/s390/include/asm/elf.h index 32e8449640fa..9b94a160fe7f 100644 --- a/arch/s390/include/asm/elf.h +++ b/arch/s390/include/asm/elf.h | |||
| @@ -180,7 +180,8 @@ extern char elf_platform[]; | |||
| 180 | #define ELF_PLATFORM (elf_platform) | 180 | #define ELF_PLATFORM (elf_platform) |
| 181 | 181 | ||
| 182 | #ifndef CONFIG_64BIT | 182 | #ifndef CONFIG_64BIT |
| 183 | #define SET_PERSONALITY(ex) set_personality(PER_LINUX) | 183 | #define SET_PERSONALITY(ex) \ |
| 184 | set_personality(PER_LINUX | (current->personality & (~PER_MASK))) | ||
| 184 | #else /* CONFIG_64BIT */ | 185 | #else /* CONFIG_64BIT */ |
| 185 | #define SET_PERSONALITY(ex) \ | 186 | #define SET_PERSONALITY(ex) \ |
| 186 | do { \ | 187 | do { \ |
diff --git a/arch/s390/include/asm/posix_types.h b/arch/s390/include/asm/posix_types.h index 7bcc14e395f0..bf2a2ad2f800 100644 --- a/arch/s390/include/asm/posix_types.h +++ b/arch/s390/include/asm/posix_types.h | |||
| @@ -13,6 +13,7 @@ | |||
| 13 | */ | 13 | */ |
| 14 | 14 | ||
| 15 | typedef unsigned long __kernel_size_t; | 15 | typedef unsigned long __kernel_size_t; |
| 16 | typedef long __kernel_ssize_t; | ||
| 16 | #define __kernel_size_t __kernel_size_t | 17 | #define __kernel_size_t __kernel_size_t |
| 17 | 18 | ||
| 18 | typedef unsigned short __kernel_old_dev_t; | 19 | typedef unsigned short __kernel_old_dev_t; |
| @@ -25,7 +26,6 @@ typedef unsigned short __kernel_mode_t; | |||
| 25 | typedef unsigned short __kernel_ipc_pid_t; | 26 | typedef unsigned short __kernel_ipc_pid_t; |
| 26 | typedef unsigned short __kernel_uid_t; | 27 | typedef unsigned short __kernel_uid_t; |
| 27 | typedef unsigned short __kernel_gid_t; | 28 | typedef unsigned short __kernel_gid_t; |
| 28 | typedef int __kernel_ssize_t; | ||
| 29 | typedef int __kernel_ptrdiff_t; | 29 | typedef int __kernel_ptrdiff_t; |
| 30 | 30 | ||
| 31 | #else /* __s390x__ */ | 31 | #else /* __s390x__ */ |
| @@ -35,7 +35,6 @@ typedef unsigned int __kernel_mode_t; | |||
| 35 | typedef int __kernel_ipc_pid_t; | 35 | typedef int __kernel_ipc_pid_t; |
| 36 | typedef unsigned int __kernel_uid_t; | 36 | typedef unsigned int __kernel_uid_t; |
| 37 | typedef unsigned int __kernel_gid_t; | 37 | typedef unsigned int __kernel_gid_t; |
| 38 | typedef long __kernel_ssize_t; | ||
| 39 | typedef long __kernel_ptrdiff_t; | 38 | typedef long __kernel_ptrdiff_t; |
| 40 | typedef unsigned long __kernel_sigset_t; /* at least 32 bits */ | 39 | typedef unsigned long __kernel_sigset_t; /* at least 32 bits */ |
| 41 | 40 | ||
diff --git a/arch/s390/include/asm/smp.h b/arch/s390/include/asm/smp.h index a0a8340daafa..ce26ac3cb162 100644 --- a/arch/s390/include/asm/smp.h +++ b/arch/s390/include/asm/smp.h | |||
| @@ -44,6 +44,7 @@ static inline void smp_call_online_cpu(void (*func)(void *), void *data) | |||
| 44 | } | 44 | } |
| 45 | 45 | ||
| 46 | static inline int smp_find_processor_id(int address) { return 0; } | 46 | static inline int smp_find_processor_id(int address) { return 0; } |
| 47 | static inline int smp_store_status(int cpu) { return 0; } | ||
| 47 | static inline int smp_vcpu_scheduled(int cpu) { return 1; } | 48 | static inline int smp_vcpu_scheduled(int cpu) { return 1; } |
| 48 | static inline void smp_yield_cpu(int cpu) { } | 49 | static inline void smp_yield_cpu(int cpu) { } |
| 49 | static inline void smp_yield(void) { } | 50 | static inline void smp_yield(void) { } |
diff --git a/arch/x86/include/asm/spinlock.h b/arch/x86/include/asm/spinlock.h index b315a33867f2..33692eaabab5 100644 --- a/arch/x86/include/asm/spinlock.h +++ b/arch/x86/include/asm/spinlock.h | |||
| @@ -12,8 +12,7 @@ | |||
| 12 | * Simple spin lock operations. There are two variants, one clears IRQ's | 12 | * Simple spin lock operations. There are two variants, one clears IRQ's |
| 13 | * on the local processor, one does not. | 13 | * on the local processor, one does not. |
| 14 | * | 14 | * |
| 15 | * These are fair FIFO ticket locks, which are currently limited to 256 | 15 | * These are fair FIFO ticket locks, which support up to 2^16 CPUs. |
| 16 | * CPUs. | ||
| 17 | * | 16 | * |
| 18 | * (the type definitions are in asm/spinlock_types.h) | 17 | * (the type definitions are in asm/spinlock_types.h) |
| 19 | */ | 18 | */ |
diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c index afb7ff79a29f..ced4534baed5 100644 --- a/arch/x86/kernel/alternative.c +++ b/arch/x86/kernel/alternative.c | |||
| @@ -165,7 +165,7 @@ static const unsigned char * const k7_nops[ASM_NOP_MAX+2] = | |||
| 165 | #endif | 165 | #endif |
| 166 | 166 | ||
| 167 | #ifdef P6_NOP1 | 167 | #ifdef P6_NOP1 |
| 168 | static const unsigned char __initconst_or_module p6nops[] = | 168 | static const unsigned char p6nops[] = |
| 169 | { | 169 | { |
| 170 | P6_NOP1, | 170 | P6_NOP1, |
| 171 | P6_NOP2, | 171 | P6_NOP2, |
diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c index 7ad683d78645..d44f7829968e 100644 --- a/arch/x86/kernel/irq.c +++ b/arch/x86/kernel/irq.c | |||
| @@ -270,7 +270,7 @@ void fixup_irqs(void) | |||
| 270 | 270 | ||
| 271 | if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) { | 271 | if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) { |
| 272 | break_affinity = 1; | 272 | break_affinity = 1; |
| 273 | affinity = cpu_all_mask; | 273 | affinity = cpu_online_mask; |
| 274 | } | 274 | } |
| 275 | 275 | ||
| 276 | chip = irq_data_get_irq_chip(data); | 276 | chip = irq_data_get_irq_chip(data); |
diff --git a/arch/x86/kernel/microcode_amd.c b/arch/x86/kernel/microcode_amd.c index 8a2ce8fd41c0..82746f942cd8 100644 --- a/arch/x86/kernel/microcode_amd.c +++ b/arch/x86/kernel/microcode_amd.c | |||
| @@ -143,11 +143,12 @@ static int get_matching_microcode(int cpu, const u8 *ucode_ptr, | |||
| 143 | unsigned int *current_size) | 143 | unsigned int *current_size) |
| 144 | { | 144 | { |
| 145 | struct microcode_header_amd *mc_hdr; | 145 | struct microcode_header_amd *mc_hdr; |
| 146 | unsigned int actual_size; | 146 | unsigned int actual_size, patch_size; |
| 147 | u16 equiv_cpu_id; | 147 | u16 equiv_cpu_id; |
| 148 | 148 | ||
| 149 | /* size of the current patch we're staring at */ | 149 | /* size of the current patch we're staring at */ |
| 150 | *current_size = *(u32 *)(ucode_ptr + 4) + SECTION_HDR_SIZE; | 150 | patch_size = *(u32 *)(ucode_ptr + 4); |
| 151 | *current_size = patch_size + SECTION_HDR_SIZE; | ||
| 151 | 152 | ||
| 152 | equiv_cpu_id = find_equiv_id(); | 153 | equiv_cpu_id = find_equiv_id(); |
| 153 | if (!equiv_cpu_id) | 154 | if (!equiv_cpu_id) |
| @@ -174,7 +175,7 @@ static int get_matching_microcode(int cpu, const u8 *ucode_ptr, | |||
| 174 | /* | 175 | /* |
| 175 | * now that the header looks sane, verify its size | 176 | * now that the header looks sane, verify its size |
| 176 | */ | 177 | */ |
| 177 | actual_size = verify_ucode_size(cpu, *current_size, leftover_size); | 178 | actual_size = verify_ucode_size(cpu, patch_size, leftover_size); |
| 178 | if (!actual_size) | 179 | if (!actual_size) |
| 179 | return 0; | 180 | return 0; |
| 180 | 181 | ||
diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c index 97d9a9914ba8..a3b57a27be88 100644 --- a/arch/x86/kvm/emulate.c +++ b/arch/x86/kvm/emulate.c | |||
| @@ -475,13 +475,26 @@ register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg) | |||
| 475 | return address_mask(ctxt, reg); | 475 | return address_mask(ctxt, reg); |
| 476 | } | 476 | } |
| 477 | 477 | ||
| 478 | static void masked_increment(ulong *reg, ulong mask, int inc) | ||
| 479 | { | ||
| 480 | assign_masked(reg, *reg + inc, mask); | ||
| 481 | } | ||
| 482 | |||
| 478 | static inline void | 483 | static inline void |
| 479 | register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc) | 484 | register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc) |
| 480 | { | 485 | { |
| 486 | ulong mask; | ||
| 487 | |||
| 481 | if (ctxt->ad_bytes == sizeof(unsigned long)) | 488 | if (ctxt->ad_bytes == sizeof(unsigned long)) |
| 482 | *reg += inc; | 489 | mask = ~0UL; |
| 483 | else | 490 | else |
| 484 | *reg = (*reg & ~ad_mask(ctxt)) | ((*reg + inc) & ad_mask(ctxt)); | 491 | mask = ad_mask(ctxt); |
| 492 | masked_increment(reg, mask, inc); | ||
| 493 | } | ||
| 494 | |||
| 495 | static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc) | ||
| 496 | { | ||
| 497 | masked_increment(&ctxt->regs[VCPU_REGS_RSP], stack_mask(ctxt), inc); | ||
| 485 | } | 498 | } |
| 486 | 499 | ||
| 487 | static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel) | 500 | static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel) |
| @@ -1522,8 +1535,8 @@ static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes) | |||
| 1522 | { | 1535 | { |
| 1523 | struct segmented_address addr; | 1536 | struct segmented_address addr; |
| 1524 | 1537 | ||
| 1525 | register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], -bytes); | 1538 | rsp_increment(ctxt, -bytes); |
| 1526 | addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]); | 1539 | addr.ea = ctxt->regs[VCPU_REGS_RSP] & stack_mask(ctxt); |
| 1527 | addr.seg = VCPU_SREG_SS; | 1540 | addr.seg = VCPU_SREG_SS; |
| 1528 | 1541 | ||
| 1529 | return segmented_write(ctxt, addr, data, bytes); | 1542 | return segmented_write(ctxt, addr, data, bytes); |
| @@ -1542,13 +1555,13 @@ static int emulate_pop(struct x86_emulate_ctxt *ctxt, | |||
| 1542 | int rc; | 1555 | int rc; |
| 1543 | struct segmented_address addr; | 1556 | struct segmented_address addr; |
| 1544 | 1557 | ||
| 1545 | addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]); | 1558 | addr.ea = ctxt->regs[VCPU_REGS_RSP] & stack_mask(ctxt); |
| 1546 | addr.seg = VCPU_SREG_SS; | 1559 | addr.seg = VCPU_SREG_SS; |
| 1547 | rc = segmented_read(ctxt, addr, dest, len); | 1560 | rc = segmented_read(ctxt, addr, dest, len); |
| 1548 | if (rc != X86EMUL_CONTINUE) | 1561 | if (rc != X86EMUL_CONTINUE) |
| 1549 | return rc; | 1562 | return rc; |
| 1550 | 1563 | ||
| 1551 | register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], len); | 1564 | rsp_increment(ctxt, len); |
| 1552 | return rc; | 1565 | return rc; |
| 1553 | } | 1566 | } |
| 1554 | 1567 | ||
| @@ -1688,8 +1701,7 @@ static int em_popa(struct x86_emulate_ctxt *ctxt) | |||
| 1688 | 1701 | ||
| 1689 | while (reg >= VCPU_REGS_RAX) { | 1702 | while (reg >= VCPU_REGS_RAX) { |
| 1690 | if (reg == VCPU_REGS_RSP) { | 1703 | if (reg == VCPU_REGS_RSP) { |
| 1691 | register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], | 1704 | rsp_increment(ctxt, ctxt->op_bytes); |
| 1692 | ctxt->op_bytes); | ||
| 1693 | --reg; | 1705 | --reg; |
| 1694 | } | 1706 | } |
| 1695 | 1707 | ||
| @@ -2825,7 +2837,7 @@ static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt) | |||
| 2825 | rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); | 2837 | rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); |
| 2826 | if (rc != X86EMUL_CONTINUE) | 2838 | if (rc != X86EMUL_CONTINUE) |
| 2827 | return rc; | 2839 | return rc; |
| 2828 | register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], ctxt->src.val); | 2840 | rsp_increment(ctxt, ctxt->src.val); |
| 2829 | return X86EMUL_CONTINUE; | 2841 | return X86EMUL_CONTINUE; |
| 2830 | } | 2842 | } |
| 2831 | 2843 | ||
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index 01ca00423938..7fbd0d273ea8 100644 --- a/arch/x86/kvm/mmu.c +++ b/arch/x86/kvm/mmu.c | |||
| @@ -4113,16 +4113,21 @@ static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc) | |||
| 4113 | LIST_HEAD(invalid_list); | 4113 | LIST_HEAD(invalid_list); |
| 4114 | 4114 | ||
| 4115 | /* | 4115 | /* |
| 4116 | * Never scan more than sc->nr_to_scan VM instances. | ||
| 4117 | * Will not hit this condition practically since we do not try | ||
| 4118 | * to shrink more than one VM and it is very unlikely to see | ||
| 4119 | * !n_used_mmu_pages so many times. | ||
| 4120 | */ | ||
| 4121 | if (!nr_to_scan--) | ||
| 4122 | break; | ||
| 4123 | /* | ||
| 4116 | * n_used_mmu_pages is accessed without holding kvm->mmu_lock | 4124 | * n_used_mmu_pages is accessed without holding kvm->mmu_lock |
| 4117 | * here. We may skip a VM instance errorneosly, but we do not | 4125 | * here. We may skip a VM instance errorneosly, but we do not |
| 4118 | * want to shrink a VM that only started to populate its MMU | 4126 | * want to shrink a VM that only started to populate its MMU |
| 4119 | * anyway. | 4127 | * anyway. |
| 4120 | */ | 4128 | */ |
| 4121 | if (kvm->arch.n_used_mmu_pages > 0) { | 4129 | if (!kvm->arch.n_used_mmu_pages) |
| 4122 | if (!nr_to_scan--) | ||
| 4123 | break; | ||
| 4124 | continue; | 4130 | continue; |
| 4125 | } | ||
| 4126 | 4131 | ||
| 4127 | idx = srcu_read_lock(&kvm->srcu); | 4132 | idx = srcu_read_lock(&kvm->srcu); |
| 4128 | spin_lock(&kvm->mmu_lock); | 4133 | spin_lock(&kvm->mmu_lock); |
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 42bce48f6928..148ed666e311 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c | |||
| @@ -806,7 +806,7 @@ EXPORT_SYMBOL_GPL(kvm_rdpmc); | |||
| 806 | * kvm-specific. Those are put in the beginning of the list. | 806 | * kvm-specific. Those are put in the beginning of the list. |
| 807 | */ | 807 | */ |
| 808 | 808 | ||
| 809 | #define KVM_SAVE_MSRS_BEGIN 9 | 809 | #define KVM_SAVE_MSRS_BEGIN 10 |
| 810 | static u32 msrs_to_save[] = { | 810 | static u32 msrs_to_save[] = { |
| 811 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, | 811 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
| 812 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, | 812 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, |
| @@ -2000,6 +2000,9 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) | |||
| 2000 | case MSR_KVM_STEAL_TIME: | 2000 | case MSR_KVM_STEAL_TIME: |
| 2001 | data = vcpu->arch.st.msr_val; | 2001 | data = vcpu->arch.st.msr_val; |
| 2002 | break; | 2002 | break; |
| 2003 | case MSR_KVM_PV_EOI_EN: | ||
| 2004 | data = vcpu->arch.pv_eoi.msr_val; | ||
| 2005 | break; | ||
| 2003 | case MSR_IA32_P5_MC_ADDR: | 2006 | case MSR_IA32_P5_MC_ADDR: |
| 2004 | case MSR_IA32_P5_MC_TYPE: | 2007 | case MSR_IA32_P5_MC_TYPE: |
| 2005 | case MSR_IA32_MCG_CAP: | 2008 | case MSR_IA32_MCG_CAP: |
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c index bf4bda6d3e9a..9642d4a38602 100644 --- a/arch/x86/xen/enlighten.c +++ b/arch/x86/xen/enlighten.c | |||
| @@ -31,7 +31,6 @@ | |||
| 31 | #include <linux/pci.h> | 31 | #include <linux/pci.h> |
| 32 | #include <linux/gfp.h> | 32 | #include <linux/gfp.h> |
| 33 | #include <linux/memblock.h> | 33 | #include <linux/memblock.h> |
| 34 | #include <linux/syscore_ops.h> | ||
| 35 | 34 | ||
| 36 | #include <xen/xen.h> | 35 | #include <xen/xen.h> |
| 37 | #include <xen/interface/xen.h> | 36 | #include <xen/interface/xen.h> |
| @@ -1470,130 +1469,38 @@ asmlinkage void __init xen_start_kernel(void) | |||
| 1470 | #endif | 1469 | #endif |
| 1471 | } | 1470 | } |
| 1472 | 1471 | ||
| 1473 | #ifdef CONFIG_XEN_PVHVM | 1472 | void __ref xen_hvm_init_shared_info(void) |
| 1474 | /* | ||
| 1475 | * The pfn containing the shared_info is located somewhere in RAM. This | ||
| 1476 | * will cause trouble if the current kernel is doing a kexec boot into a | ||
| 1477 | * new kernel. The new kernel (and its startup code) can not know where | ||
| 1478 | * the pfn is, so it can not reserve the page. The hypervisor will | ||
| 1479 | * continue to update the pfn, and as a result memory corruption occours | ||
| 1480 | * in the new kernel. | ||
| 1481 | * | ||
| 1482 | * One way to work around this issue is to allocate a page in the | ||
| 1483 | * xen-platform pci device's BAR memory range. But pci init is done very | ||
| 1484 | * late and the shared_info page is already in use very early to read | ||
| 1485 | * the pvclock. So moving the pfn from RAM to MMIO is racy because some | ||
| 1486 | * code paths on other vcpus could access the pfn during the small | ||
| 1487 | * window when the old pfn is moved to the new pfn. There is even a | ||
| 1488 | * small window were the old pfn is not backed by a mfn, and during that | ||
| 1489 | * time all reads return -1. | ||
| 1490 | * | ||
| 1491 | * Because it is not known upfront where the MMIO region is located it | ||
| 1492 | * can not be used right from the start in xen_hvm_init_shared_info. | ||
| 1493 | * | ||
| 1494 | * To minimise trouble the move of the pfn is done shortly before kexec. | ||
| 1495 | * This does not eliminate the race because all vcpus are still online | ||
| 1496 | * when the syscore_ops will be called. But hopefully there is no work | ||
| 1497 | * pending at this point in time. Also the syscore_op is run last which | ||
| 1498 | * reduces the risk further. | ||
| 1499 | */ | ||
| 1500 | |||
| 1501 | static struct shared_info *xen_hvm_shared_info; | ||
| 1502 | |||
| 1503 | static void xen_hvm_connect_shared_info(unsigned long pfn) | ||
| 1504 | { | 1473 | { |
| 1474 | int cpu; | ||
| 1505 | struct xen_add_to_physmap xatp; | 1475 | struct xen_add_to_physmap xatp; |
| 1476 | static struct shared_info *shared_info_page = 0; | ||
| 1506 | 1477 | ||
| 1478 | if (!shared_info_page) | ||
| 1479 | shared_info_page = (struct shared_info *) | ||
| 1480 | extend_brk(PAGE_SIZE, PAGE_SIZE); | ||
| 1507 | xatp.domid = DOMID_SELF; | 1481 | xatp.domid = DOMID_SELF; |
| 1508 | xatp.idx = 0; | 1482 | xatp.idx = 0; |
| 1509 | xatp.space = XENMAPSPACE_shared_info; | 1483 | xatp.space = XENMAPSPACE_shared_info; |
| 1510 | xatp.gpfn = pfn; | 1484 | xatp.gpfn = __pa(shared_info_page) >> PAGE_SHIFT; |
| 1511 | if (HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp)) | 1485 | if (HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp)) |
| 1512 | BUG(); | 1486 | BUG(); |
| 1513 | 1487 | ||
| 1514 | } | 1488 | HYPERVISOR_shared_info = (struct shared_info *)shared_info_page; |
| 1515 | static void xen_hvm_set_shared_info(struct shared_info *sip) | ||
| 1516 | { | ||
| 1517 | int cpu; | ||
| 1518 | |||
| 1519 | HYPERVISOR_shared_info = sip; | ||
| 1520 | 1489 | ||
| 1521 | /* xen_vcpu is a pointer to the vcpu_info struct in the shared_info | 1490 | /* xen_vcpu is a pointer to the vcpu_info struct in the shared_info |
| 1522 | * page, we use it in the event channel upcall and in some pvclock | 1491 | * page, we use it in the event channel upcall and in some pvclock |
| 1523 | * related functions. We don't need the vcpu_info placement | 1492 | * related functions. We don't need the vcpu_info placement |
| 1524 | * optimizations because we don't use any pv_mmu or pv_irq op on | 1493 | * optimizations because we don't use any pv_mmu or pv_irq op on |
| 1525 | * HVM. | 1494 | * HVM. |
| 1526 | * When xen_hvm_set_shared_info is run at boot time only vcpu 0 is | 1495 | * When xen_hvm_init_shared_info is run at boot time only vcpu 0 is |
| 1527 | * online but xen_hvm_set_shared_info is run at resume time too and | 1496 | * online but xen_hvm_init_shared_info is run at resume time too and |
| 1528 | * in that case multiple vcpus might be online. */ | 1497 | * in that case multiple vcpus might be online. */ |
| 1529 | for_each_online_cpu(cpu) { | 1498 | for_each_online_cpu(cpu) { |
| 1530 | per_cpu(xen_vcpu, cpu) = &HYPERVISOR_shared_info->vcpu_info[cpu]; | 1499 | per_cpu(xen_vcpu, cpu) = &HYPERVISOR_shared_info->vcpu_info[cpu]; |
| 1531 | } | 1500 | } |
| 1532 | } | 1501 | } |
| 1533 | 1502 | ||
| 1534 | /* Reconnect the shared_info pfn to a mfn */ | 1503 | #ifdef CONFIG_XEN_PVHVM |
| 1535 | void xen_hvm_resume_shared_info(void) | ||
| 1536 | { | ||
| 1537 | xen_hvm_connect_shared_info(__pa(xen_hvm_shared_info) >> PAGE_SHIFT); | ||
| 1538 | } | ||
| 1539 | |||
| 1540 | #ifdef CONFIG_KEXEC | ||
| 1541 | static struct shared_info *xen_hvm_shared_info_kexec; | ||
| 1542 | static unsigned long xen_hvm_shared_info_pfn_kexec; | ||
| 1543 | |||
| 1544 | /* Remember a pfn in MMIO space for kexec reboot */ | ||
| 1545 | void __devinit xen_hvm_prepare_kexec(struct shared_info *sip, unsigned long pfn) | ||
| 1546 | { | ||
| 1547 | xen_hvm_shared_info_kexec = sip; | ||
| 1548 | xen_hvm_shared_info_pfn_kexec = pfn; | ||
| 1549 | } | ||
| 1550 | |||
| 1551 | static void xen_hvm_syscore_shutdown(void) | ||
| 1552 | { | ||
| 1553 | struct xen_memory_reservation reservation = { | ||
| 1554 | .domid = DOMID_SELF, | ||
| 1555 | .nr_extents = 1, | ||
| 1556 | }; | ||
| 1557 | unsigned long prev_pfn; | ||
| 1558 | int rc; | ||
| 1559 | |||
| 1560 | if (!xen_hvm_shared_info_kexec) | ||
| 1561 | return; | ||
| 1562 | |||
| 1563 | prev_pfn = __pa(xen_hvm_shared_info) >> PAGE_SHIFT; | ||
| 1564 | set_xen_guest_handle(reservation.extent_start, &prev_pfn); | ||
| 1565 | |||
| 1566 | /* Move pfn to MMIO, disconnects previous pfn from mfn */ | ||
| 1567 | xen_hvm_connect_shared_info(xen_hvm_shared_info_pfn_kexec); | ||
| 1568 | |||
| 1569 | /* Update pointers, following hypercall is also a memory barrier */ | ||
| 1570 | xen_hvm_set_shared_info(xen_hvm_shared_info_kexec); | ||
| 1571 | |||
| 1572 | /* Allocate new mfn for previous pfn */ | ||
| 1573 | do { | ||
| 1574 | rc = HYPERVISOR_memory_op(XENMEM_populate_physmap, &reservation); | ||
| 1575 | if (rc == 0) | ||
| 1576 | msleep(123); | ||
| 1577 | } while (rc == 0); | ||
| 1578 | |||
| 1579 | /* Make sure the previous pfn is really connected to a (new) mfn */ | ||
| 1580 | BUG_ON(rc != 1); | ||
| 1581 | } | ||
| 1582 | |||
| 1583 | static struct syscore_ops xen_hvm_syscore_ops = { | ||
| 1584 | .shutdown = xen_hvm_syscore_shutdown, | ||
| 1585 | }; | ||
| 1586 | #endif | ||
| 1587 | |||
| 1588 | /* Use a pfn in RAM, may move to MMIO before kexec. */ | ||
| 1589 | static void __init xen_hvm_init_shared_info(void) | ||
| 1590 | { | ||
| 1591 | /* Remember pointer for resume */ | ||
| 1592 | xen_hvm_shared_info = extend_brk(PAGE_SIZE, PAGE_SIZE); | ||
| 1593 | xen_hvm_connect_shared_info(__pa(xen_hvm_shared_info) >> PAGE_SHIFT); | ||
| 1594 | xen_hvm_set_shared_info(xen_hvm_shared_info); | ||
| 1595 | } | ||
| 1596 | |||
| 1597 | static void __init init_hvm_pv_info(void) | 1504 | static void __init init_hvm_pv_info(void) |
| 1598 | { | 1505 | { |
| 1599 | int major, minor; | 1506 | int major, minor; |
| @@ -1644,9 +1551,6 @@ static void __init xen_hvm_guest_init(void) | |||
| 1644 | init_hvm_pv_info(); | 1551 | init_hvm_pv_info(); |
| 1645 | 1552 | ||
| 1646 | xen_hvm_init_shared_info(); | 1553 | xen_hvm_init_shared_info(); |
| 1647 | #ifdef CONFIG_KEXEC | ||
| 1648 | register_syscore_ops(&xen_hvm_syscore_ops); | ||
| 1649 | #endif | ||
| 1650 | 1554 | ||
| 1651 | if (xen_feature(XENFEAT_hvm_callback_vector)) | 1555 | if (xen_feature(XENFEAT_hvm_callback_vector)) |
| 1652 | xen_have_vector_callback = 1; | 1556 | xen_have_vector_callback = 1; |
diff --git a/arch/x86/xen/p2m.c b/arch/x86/xen/p2m.c index b2e91d40a4cb..d4b255463253 100644 --- a/arch/x86/xen/p2m.c +++ b/arch/x86/xen/p2m.c | |||
| @@ -196,9 +196,11 @@ RESERVE_BRK(p2m_mid_identity, PAGE_SIZE * 2 * 3); | |||
| 196 | 196 | ||
| 197 | /* When we populate back during bootup, the amount of pages can vary. The | 197 | /* When we populate back during bootup, the amount of pages can vary. The |
| 198 | * max we have is seen is 395979, but that does not mean it can't be more. | 198 | * max we have is seen is 395979, but that does not mean it can't be more. |
| 199 | * But some machines can have 3GB I/O holes even. So lets reserve enough | 199 | * Some machines can have 3GB I/O holes even. With early_can_reuse_p2m_middle |
| 200 | * for 4GB of I/O and E820 holes. */ | 200 | * it can re-use Xen provided mfn_list array, so we only need to allocate at |
| 201 | RESERVE_BRK(p2m_populated, PMD_SIZE * 4); | 201 | * most three P2M top nodes. */ |
| 202 | RESERVE_BRK(p2m_populated, PAGE_SIZE * 3); | ||
| 203 | |||
| 202 | static inline unsigned p2m_top_index(unsigned long pfn) | 204 | static inline unsigned p2m_top_index(unsigned long pfn) |
| 203 | { | 205 | { |
| 204 | BUG_ON(pfn >= MAX_P2M_PFN); | 206 | BUG_ON(pfn >= MAX_P2M_PFN); |
| @@ -575,12 +577,99 @@ static bool __init early_alloc_p2m(unsigned long pfn) | |||
| 575 | } | 577 | } |
| 576 | return true; | 578 | return true; |
| 577 | } | 579 | } |
| 580 | |||
| 581 | /* | ||
| 582 | * Skim over the P2M tree looking at pages that are either filled with | ||
| 583 | * INVALID_P2M_ENTRY or with 1:1 PFNs. If found, re-use that page and | ||
| 584 | * replace the P2M leaf with a p2m_missing or p2m_identity. | ||
| 585 | * Stick the old page in the new P2M tree location. | ||
| 586 | */ | ||
| 587 | bool __init early_can_reuse_p2m_middle(unsigned long set_pfn, unsigned long set_mfn) | ||
| 588 | { | ||
| 589 | unsigned topidx; | ||
| 590 | unsigned mididx; | ||
| 591 | unsigned ident_pfns; | ||
| 592 | unsigned inv_pfns; | ||
| 593 | unsigned long *p2m; | ||
| 594 | unsigned long *mid_mfn_p; | ||
| 595 | unsigned idx; | ||
| 596 | unsigned long pfn; | ||
| 597 | |||
| 598 | /* We only look when this entails a P2M middle layer */ | ||
| 599 | if (p2m_index(set_pfn)) | ||
| 600 | return false; | ||
| 601 | |||
| 602 | for (pfn = 0; pfn <= MAX_DOMAIN_PAGES; pfn += P2M_PER_PAGE) { | ||
| 603 | topidx = p2m_top_index(pfn); | ||
| 604 | |||
| 605 | if (!p2m_top[topidx]) | ||
| 606 | continue; | ||
| 607 | |||
| 608 | if (p2m_top[topidx] == p2m_mid_missing) | ||
| 609 | continue; | ||
| 610 | |||
| 611 | mididx = p2m_mid_index(pfn); | ||
| 612 | p2m = p2m_top[topidx][mididx]; | ||
| 613 | if (!p2m) | ||
| 614 | continue; | ||
| 615 | |||
| 616 | if ((p2m == p2m_missing) || (p2m == p2m_identity)) | ||
| 617 | continue; | ||
| 618 | |||
| 619 | if ((unsigned long)p2m == INVALID_P2M_ENTRY) | ||
| 620 | continue; | ||
| 621 | |||
| 622 | ident_pfns = 0; | ||
| 623 | inv_pfns = 0; | ||
| 624 | for (idx = 0; idx < P2M_PER_PAGE; idx++) { | ||
| 625 | /* IDENTITY_PFNs are 1:1 */ | ||
| 626 | if (p2m[idx] == IDENTITY_FRAME(pfn + idx)) | ||
| 627 | ident_pfns++; | ||
| 628 | else if (p2m[idx] == INVALID_P2M_ENTRY) | ||
| 629 | inv_pfns++; | ||
| 630 | else | ||
| 631 | break; | ||
| 632 | } | ||
| 633 | if ((ident_pfns == P2M_PER_PAGE) || (inv_pfns == P2M_PER_PAGE)) | ||
| 634 | goto found; | ||
| 635 | } | ||
| 636 | return false; | ||
| 637 | found: | ||
| 638 | /* Found one, replace old with p2m_identity or p2m_missing */ | ||
| 639 | p2m_top[topidx][mididx] = (ident_pfns ? p2m_identity : p2m_missing); | ||
| 640 | /* And the other for save/restore.. */ | ||
| 641 | mid_mfn_p = p2m_top_mfn_p[topidx]; | ||
| 642 | /* NOTE: Even if it is a p2m_identity it should still be point to | ||
| 643 | * a page filled with INVALID_P2M_ENTRY entries. */ | ||
| 644 | mid_mfn_p[mididx] = virt_to_mfn(p2m_missing); | ||
| 645 | |||
| 646 | /* Reset where we want to stick the old page in. */ | ||
| 647 | topidx = p2m_top_index(set_pfn); | ||
| 648 | mididx = p2m_mid_index(set_pfn); | ||
| 649 | |||
| 650 | /* This shouldn't happen */ | ||
| 651 | if (WARN_ON(p2m_top[topidx] == p2m_mid_missing)) | ||
| 652 | early_alloc_p2m(set_pfn); | ||
| 653 | |||
| 654 | if (WARN_ON(p2m_top[topidx][mididx] != p2m_missing)) | ||
| 655 | return false; | ||
| 656 | |||
| 657 | p2m_init(p2m); | ||
| 658 | p2m_top[topidx][mididx] = p2m; | ||
| 659 | mid_mfn_p = p2m_top_mfn_p[topidx]; | ||
| 660 | mid_mfn_p[mididx] = virt_to_mfn(p2m); | ||
| 661 | |||
| 662 | return true; | ||
| 663 | } | ||
| 578 | bool __init early_set_phys_to_machine(unsigned long pfn, unsigned long mfn) | 664 | bool __init early_set_phys_to_machine(unsigned long pfn, unsigned long mfn) |
| 579 | { | 665 | { |
| 580 | if (unlikely(!__set_phys_to_machine(pfn, mfn))) { | 666 | if (unlikely(!__set_phys_to_machine(pfn, mfn))) { |
| 581 | if (!early_alloc_p2m(pfn)) | 667 | if (!early_alloc_p2m(pfn)) |
| 582 | return false; | 668 | return false; |
| 583 | 669 | ||
| 670 | if (early_can_reuse_p2m_middle(pfn, mfn)) | ||
| 671 | return __set_phys_to_machine(pfn, mfn); | ||
| 672 | |||
| 584 | if (!early_alloc_p2m_middle(pfn, false /* boundary crossover OK!*/)) | 673 | if (!early_alloc_p2m_middle(pfn, false /* boundary crossover OK!*/)) |
| 585 | return false; | 674 | return false; |
| 586 | 675 | ||
diff --git a/arch/x86/xen/setup.c b/arch/x86/xen/setup.c index ead85576d54a..d11ca11d14fc 100644 --- a/arch/x86/xen/setup.c +++ b/arch/x86/xen/setup.c | |||
| @@ -78,9 +78,16 @@ static void __init xen_add_extra_mem(u64 start, u64 size) | |||
| 78 | memblock_reserve(start, size); | 78 | memblock_reserve(start, size); |
| 79 | 79 | ||
| 80 | xen_max_p2m_pfn = PFN_DOWN(start + size); | 80 | xen_max_p2m_pfn = PFN_DOWN(start + size); |
| 81 | for (pfn = PFN_DOWN(start); pfn < xen_max_p2m_pfn; pfn++) { | ||
| 82 | unsigned long mfn = pfn_to_mfn(pfn); | ||
| 83 | |||
| 84 | if (WARN(mfn == pfn, "Trying to over-write 1-1 mapping (pfn: %lx)\n", pfn)) | ||
| 85 | continue; | ||
| 86 | WARN(mfn != INVALID_P2M_ENTRY, "Trying to remove %lx which has %lx mfn!\n", | ||
| 87 | pfn, mfn); | ||
| 81 | 88 | ||
| 82 | for (pfn = PFN_DOWN(start); pfn <= xen_max_p2m_pfn; pfn++) | ||
| 83 | __set_phys_to_machine(pfn, INVALID_P2M_ENTRY); | 89 | __set_phys_to_machine(pfn, INVALID_P2M_ENTRY); |
| 90 | } | ||
| 84 | } | 91 | } |
| 85 | 92 | ||
| 86 | static unsigned long __init xen_do_chunk(unsigned long start, | 93 | static unsigned long __init xen_do_chunk(unsigned long start, |
diff --git a/arch/x86/xen/suspend.c b/arch/x86/xen/suspend.c index ae8a00c39de4..45329c8c226e 100644 --- a/arch/x86/xen/suspend.c +++ b/arch/x86/xen/suspend.c | |||
| @@ -30,7 +30,7 @@ void xen_arch_hvm_post_suspend(int suspend_cancelled) | |||
| 30 | { | 30 | { |
| 31 | #ifdef CONFIG_XEN_PVHVM | 31 | #ifdef CONFIG_XEN_PVHVM |
| 32 | int cpu; | 32 | int cpu; |
| 33 | xen_hvm_resume_shared_info(); | 33 | xen_hvm_init_shared_info(); |
| 34 | xen_callback_vector(); | 34 | xen_callback_vector(); |
| 35 | xen_unplug_emulated_devices(); | 35 | xen_unplug_emulated_devices(); |
| 36 | if (xen_feature(XENFEAT_hvm_safe_pvclock)) { | 36 | if (xen_feature(XENFEAT_hvm_safe_pvclock)) { |
diff --git a/arch/x86/xen/xen-ops.h b/arch/x86/xen/xen-ops.h index 1e4329e04e0f..202d4c150154 100644 --- a/arch/x86/xen/xen-ops.h +++ b/arch/x86/xen/xen-ops.h | |||
| @@ -41,7 +41,7 @@ void xen_enable_syscall(void); | |||
| 41 | void xen_vcpu_restore(void); | 41 | void xen_vcpu_restore(void); |
| 42 | 42 | ||
| 43 | void xen_callback_vector(void); | 43 | void xen_callback_vector(void); |
| 44 | void xen_hvm_resume_shared_info(void); | 44 | void xen_hvm_init_shared_info(void); |
| 45 | void xen_unplug_emulated_devices(void); | 45 | void xen_unplug_emulated_devices(void); |
| 46 | 46 | ||
| 47 | void __init xen_build_dynamic_phys_to_machine(void); | 47 | void __init xen_build_dynamic_phys_to_machine(void); |
diff --git a/block/blk-lib.c b/block/blk-lib.c index 2b461b496a78..19cc761cacb2 100644 --- a/block/blk-lib.c +++ b/block/blk-lib.c | |||
| @@ -44,6 +44,7 @@ int blkdev_issue_discard(struct block_device *bdev, sector_t sector, | |||
| 44 | struct request_queue *q = bdev_get_queue(bdev); | 44 | struct request_queue *q = bdev_get_queue(bdev); |
| 45 | int type = REQ_WRITE | REQ_DISCARD; | 45 | int type = REQ_WRITE | REQ_DISCARD; |
| 46 | unsigned int max_discard_sectors; | 46 | unsigned int max_discard_sectors; |
| 47 | unsigned int granularity, alignment, mask; | ||
| 47 | struct bio_batch bb; | 48 | struct bio_batch bb; |
| 48 | struct bio *bio; | 49 | struct bio *bio; |
| 49 | int ret = 0; | 50 | int ret = 0; |
| @@ -54,18 +55,20 @@ int blkdev_issue_discard(struct block_device *bdev, sector_t sector, | |||
| 54 | if (!blk_queue_discard(q)) | 55 | if (!blk_queue_discard(q)) |
| 55 | return -EOPNOTSUPP; | 56 | return -EOPNOTSUPP; |
| 56 | 57 | ||
| 58 | /* Zero-sector (unknown) and one-sector granularities are the same. */ | ||
| 59 | granularity = max(q->limits.discard_granularity >> 9, 1U); | ||
| 60 | mask = granularity - 1; | ||
| 61 | alignment = (bdev_discard_alignment(bdev) >> 9) & mask; | ||
| 62 | |||
| 57 | /* | 63 | /* |
| 58 | * Ensure that max_discard_sectors is of the proper | 64 | * Ensure that max_discard_sectors is of the proper |
| 59 | * granularity | 65 | * granularity, so that requests stay aligned after a split. |
| 60 | */ | 66 | */ |
| 61 | max_discard_sectors = min(q->limits.max_discard_sectors, UINT_MAX >> 9); | 67 | max_discard_sectors = min(q->limits.max_discard_sectors, UINT_MAX >> 9); |
| 68 | max_discard_sectors = round_down(max_discard_sectors, granularity); | ||
| 62 | if (unlikely(!max_discard_sectors)) { | 69 | if (unlikely(!max_discard_sectors)) { |
| 63 | /* Avoid infinite loop below. Being cautious never hurts. */ | 70 | /* Avoid infinite loop below. Being cautious never hurts. */ |
| 64 | return -EOPNOTSUPP; | 71 | return -EOPNOTSUPP; |
| 65 | } else if (q->limits.discard_granularity) { | ||
| 66 | unsigned int disc_sects = q->limits.discard_granularity >> 9; | ||
| 67 | |||
| 68 | max_discard_sectors &= ~(disc_sects - 1); | ||
| 69 | } | 72 | } |
| 70 | 73 | ||
| 71 | if (flags & BLKDEV_DISCARD_SECURE) { | 74 | if (flags & BLKDEV_DISCARD_SECURE) { |
| @@ -79,25 +82,37 @@ int blkdev_issue_discard(struct block_device *bdev, sector_t sector, | |||
| 79 | bb.wait = &wait; | 82 | bb.wait = &wait; |
| 80 | 83 | ||
| 81 | while (nr_sects) { | 84 | while (nr_sects) { |
| 85 | unsigned int req_sects; | ||
| 86 | sector_t end_sect; | ||
| 87 | |||
| 82 | bio = bio_alloc(gfp_mask, 1); | 88 | bio = bio_alloc(gfp_mask, 1); |
| 83 | if (!bio) { | 89 | if (!bio) { |
| 84 | ret = -ENOMEM; | 90 | ret = -ENOMEM; |
| 85 | break; | 91 | break; |
| 86 | } | 92 | } |
| 87 | 93 | ||
| 94 | req_sects = min_t(sector_t, nr_sects, max_discard_sectors); | ||
| 95 | |||
| 96 | /* | ||
| 97 | * If splitting a request, and the next starting sector would be | ||
| 98 | * misaligned, stop the discard at the previous aligned sector. | ||
| 99 | */ | ||
| 100 | end_sect = sector + req_sects; | ||
| 101 | if (req_sects < nr_sects && (end_sect & mask) != alignment) { | ||
| 102 | end_sect = | ||
| 103 | round_down(end_sect - alignment, granularity) | ||
| 104 | + alignment; | ||
| 105 | req_sects = end_sect - sector; | ||
| 106 | } | ||
| 107 | |||
| 88 | bio->bi_sector = sector; | 108 | bio->bi_sector = sector; |
| 89 | bio->bi_end_io = bio_batch_end_io; | 109 | bio->bi_end_io = bio_batch_end_io; |
| 90 | bio->bi_bdev = bdev; | 110 | bio->bi_bdev = bdev; |
| 91 | bio->bi_private = &bb; | 111 | bio->bi_private = &bb; |
| 92 | 112 | ||
| 93 | if (nr_sects > max_discard_sectors) { | 113 | bio->bi_size = req_sects << 9; |
| 94 | bio->bi_size = max_discard_sectors << 9; | 114 | nr_sects -= req_sects; |
| 95 | nr_sects -= max_discard_sectors; | 115 | sector = end_sect; |
| 96 | sector += max_discard_sectors; | ||
| 97 | } else { | ||
| 98 | bio->bi_size = nr_sects << 9; | ||
| 99 | nr_sects = 0; | ||
| 100 | } | ||
| 101 | 116 | ||
| 102 | atomic_inc(&bb.done); | 117 | atomic_inc(&bb.done); |
| 103 | submit_bio(type, bio); | 118 | submit_bio(type, bio); |
diff --git a/block/blk-merge.c b/block/blk-merge.c index 160035f54882..e76279e41162 100644 --- a/block/blk-merge.c +++ b/block/blk-merge.c | |||
| @@ -110,6 +110,49 @@ static int blk_phys_contig_segment(struct request_queue *q, struct bio *bio, | |||
| 110 | return 0; | 110 | return 0; |
| 111 | } | 111 | } |
| 112 | 112 | ||
| 113 | static void | ||
| 114 | __blk_segment_map_sg(struct request_queue *q, struct bio_vec *bvec, | ||
| 115 | struct scatterlist *sglist, struct bio_vec **bvprv, | ||
| 116 | struct scatterlist **sg, int *nsegs, int *cluster) | ||
| 117 | { | ||
| 118 | |||
| 119 | int nbytes = bvec->bv_len; | ||
| 120 | |||
| 121 | if (*bvprv && *cluster) { | ||
| 122 | if ((*sg)->length + nbytes > queue_max_segment_size(q)) | ||
| 123 | goto new_segment; | ||
| 124 | |||
| 125 | if (!BIOVEC_PHYS_MERGEABLE(*bvprv, bvec)) | ||
| 126 | goto new_segment; | ||
| 127 | if (!BIOVEC_SEG_BOUNDARY(q, *bvprv, bvec)) | ||
| 128 | goto new_segment; | ||
| 129 | |||
| 130 | (*sg)->length += nbytes; | ||
| 131 | } else { | ||
| 132 | new_segment: | ||
| 133 | if (!*sg) | ||
| 134 | *sg = sglist; | ||
| 135 | else { | ||
| 136 | /* | ||
| 137 | * If the driver previously mapped a shorter | ||
| 138 | * list, we could see a termination bit | ||
| 139 | * prematurely unless it fully inits the sg | ||
| 140 | * table on each mapping. We KNOW that there | ||
| 141 | * must be more entries here or the driver | ||
| 142 | * would be buggy, so force clear the | ||
| 143 | * termination bit to avoid doing a full | ||
| 144 | * sg_init_table() in drivers for each command. | ||
| 145 | */ | ||
| 146 | (*sg)->page_link &= ~0x02; | ||
| 147 | *sg = sg_next(*sg); | ||
| 148 | } | ||
| 149 | |||
| 150 | sg_set_page(*sg, bvec->bv_page, nbytes, bvec->bv_offset); | ||
| 151 | (*nsegs)++; | ||
| 152 | } | ||
| 153 | *bvprv = bvec; | ||
| 154 | } | ||
| 155 | |||
| 113 | /* | 156 | /* |
| 114 | * map a request to scatterlist, return number of sg entries setup. Caller | 157 | * map a request to scatterlist, return number of sg entries setup. Caller |
| 115 | * must make sure sg can hold rq->nr_phys_segments entries | 158 | * must make sure sg can hold rq->nr_phys_segments entries |
| @@ -131,41 +174,8 @@ int blk_rq_map_sg(struct request_queue *q, struct request *rq, | |||
| 131 | bvprv = NULL; | 174 | bvprv = NULL; |
| 132 | sg = NULL; | 175 | sg = NULL; |
| 133 | rq_for_each_segment(bvec, rq, iter) { | 176 | rq_for_each_segment(bvec, rq, iter) { |
| 134 | int nbytes = bvec->bv_len; | 177 | __blk_segment_map_sg(q, bvec, sglist, &bvprv, &sg, |
| 135 | 178 | &nsegs, &cluster); | |
| 136 | if (bvprv && cluster) { | ||
| 137 | if (sg->length + nbytes > queue_max_segment_size(q)) | ||
| 138 | goto new_segment; | ||
| 139 | |||
| 140 | if (!BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) | ||
| 141 | goto new_segment; | ||
| 142 | if (!BIOVEC_SEG_BOUNDARY(q, bvprv, bvec)) | ||
| 143 | goto new_segment; | ||
| 144 | |||
| 145 | sg->length += nbytes; | ||
| 146 | } else { | ||
| 147 | new_segment: | ||
| 148 | if (!sg) | ||
| 149 | sg = sglist; | ||
| 150 | else { | ||
| 151 | /* | ||
| 152 | * If the driver previously mapped a shorter | ||
| 153 | * list, we could see a termination bit | ||
| 154 | * prematurely unless it fully inits the sg | ||
| 155 | * table on each mapping. We KNOW that there | ||
| 156 | * must be more entries here or the driver | ||
| 157 | * would be buggy, so force clear the | ||
| 158 | * termination bit to avoid doing a full | ||
| 159 | * sg_init_table() in drivers for each command. | ||
| 160 | */ | ||
| 161 | sg->page_link &= ~0x02; | ||
| 162 | sg = sg_next(sg); | ||
| 163 | } | ||
| 164 | |||
| 165 | sg_set_page(sg, bvec->bv_page, nbytes, bvec->bv_offset); | ||
| 166 | nsegs++; | ||
| 167 | } | ||
| 168 | bvprv = bvec; | ||
| 169 | } /* segments in rq */ | 179 | } /* segments in rq */ |
| 170 | 180 | ||
| 171 | 181 | ||
| @@ -199,6 +209,43 @@ new_segment: | |||
| 199 | } | 209 | } |
| 200 | EXPORT_SYMBOL(blk_rq_map_sg); | 210 | EXPORT_SYMBOL(blk_rq_map_sg); |
| 201 | 211 | ||
| 212 | /** | ||
| 213 | * blk_bio_map_sg - map a bio to a scatterlist | ||
| 214 | * @q: request_queue in question | ||
| 215 | * @bio: bio being mapped | ||
| 216 | * @sglist: scatterlist being mapped | ||
| 217 | * | ||
| 218 | * Note: | ||
| 219 | * Caller must make sure sg can hold bio->bi_phys_segments entries | ||
| 220 | * | ||
| 221 | * Will return the number of sg entries setup | ||
| 222 | */ | ||
| 223 | int blk_bio_map_sg(struct request_queue *q, struct bio *bio, | ||
| 224 | struct scatterlist *sglist) | ||
| 225 | { | ||
| 226 | struct bio_vec *bvec, *bvprv; | ||
| 227 | struct scatterlist *sg; | ||
| 228 | int nsegs, cluster; | ||
| 229 | unsigned long i; | ||
| 230 | |||
| 231 | nsegs = 0; | ||
| 232 | cluster = blk_queue_cluster(q); | ||
| 233 | |||
| 234 | bvprv = NULL; | ||
| 235 | sg = NULL; | ||
| 236 | bio_for_each_segment(bvec, bio, i) { | ||
| 237 | __blk_segment_map_sg(q, bvec, sglist, &bvprv, &sg, | ||
| 238 | &nsegs, &cluster); | ||
| 239 | } /* segments in bio */ | ||
| 240 | |||
| 241 | if (sg) | ||
| 242 | sg_mark_end(sg); | ||
| 243 | |||
| 244 | BUG_ON(bio->bi_phys_segments && nsegs > bio->bi_phys_segments); | ||
| 245 | return nsegs; | ||
| 246 | } | ||
| 247 | EXPORT_SYMBOL(blk_bio_map_sg); | ||
| 248 | |||
| 202 | static inline int ll_new_hw_segment(struct request_queue *q, | 249 | static inline int ll_new_hw_segment(struct request_queue *q, |
| 203 | struct request *req, | 250 | struct request *req, |
| 204 | struct bio *bio) | 251 | struct bio *bio) |
diff --git a/block/genhd.c b/block/genhd.c index cac7366957c3..d839723303c8 100644 --- a/block/genhd.c +++ b/block/genhd.c | |||
| @@ -835,7 +835,7 @@ static void disk_seqf_stop(struct seq_file *seqf, void *v) | |||
| 835 | 835 | ||
| 836 | static void *show_partition_start(struct seq_file *seqf, loff_t *pos) | 836 | static void *show_partition_start(struct seq_file *seqf, loff_t *pos) |
| 837 | { | 837 | { |
| 838 | static void *p; | 838 | void *p; |
| 839 | 839 | ||
| 840 | p = disk_seqf_start(seqf, pos); | 840 | p = disk_seqf_start(seqf, pos); |
| 841 | if (!IS_ERR_OR_NULL(p) && !*pos) | 841 | if (!IS_ERR_OR_NULL(p) && !*pos) |
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 2be8ef1d3093..27cecd313e75 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig | |||
| @@ -115,7 +115,7 @@ config SATA_SIL24 | |||
| 115 | If unsure, say N. | 115 | If unsure, say N. |
| 116 | 116 | ||
| 117 | config ATA_SFF | 117 | config ATA_SFF |
| 118 | bool "ATA SFF support" | 118 | bool "ATA SFF support (for legacy IDE and PATA)" |
| 119 | default y | 119 | default y |
| 120 | help | 120 | help |
| 121 | This option adds support for ATA controllers with SFF | 121 | This option adds support for ATA controllers with SFF |
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index 062e6a1a248f..50d5dea0ff59 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c | |||
| @@ -256,6 +256,14 @@ static const struct pci_device_id ahci_pci_tbl[] = { | |||
| 256 | { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */ | 256 | { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */ |
| 257 | { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */ | 257 | { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */ |
| 258 | { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */ | 258 | { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */ |
| 259 | { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */ | ||
| 260 | { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */ | ||
| 261 | { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */ | ||
| 262 | { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */ | ||
| 263 | { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */ | ||
| 264 | { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */ | ||
| 265 | { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */ | ||
| 266 | { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */ | ||
| 259 | 267 | ||
| 260 | /* JMicron 360/1/3/5/6, match class to avoid IDE function */ | 268 | /* JMicron 360/1/3/5/6, match class to avoid IDE function */ |
| 261 | { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | 269 | { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h index c2594ddf25b0..57eb1c212a4c 100644 --- a/drivers/ata/ahci.h +++ b/drivers/ata/ahci.h | |||
| @@ -320,6 +320,7 @@ extern struct device_attribute *ahci_sdev_attrs[]; | |||
| 320 | extern struct ata_port_operations ahci_ops; | 320 | extern struct ata_port_operations ahci_ops; |
| 321 | extern struct ata_port_operations ahci_pmp_retry_srst_ops; | 321 | extern struct ata_port_operations ahci_pmp_retry_srst_ops; |
| 322 | 322 | ||
| 323 | unsigned int ahci_dev_classify(struct ata_port *ap); | ||
| 323 | void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, | 324 | void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
| 324 | u32 opts); | 325 | u32 opts); |
| 325 | void ahci_save_initial_config(struct device *dev, | 326 | void ahci_save_initial_config(struct device *dev, |
diff --git a/drivers/ata/ata_piix.c b/drivers/ata/ata_piix.c index 3c809bfbccf5..ef773e12af79 100644 --- a/drivers/ata/ata_piix.c +++ b/drivers/ata/ata_piix.c | |||
| @@ -329,6 +329,14 @@ static const struct pci_device_id piix_pci_tbl[] = { | |||
| 329 | { 0x8086, 0x8c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, | 329 | { 0x8086, 0x8c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
| 330 | /* SATA Controller IDE (Lynx Point) */ | 330 | /* SATA Controller IDE (Lynx Point) */ |
| 331 | { 0x8086, 0x8c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, | 331 | { 0x8086, 0x8c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
| 332 | /* SATA Controller IDE (Lynx Point-LP) */ | ||
| 333 | { 0x8086, 0x9c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, | ||
| 334 | /* SATA Controller IDE (Lynx Point-LP) */ | ||
| 335 | { 0x8086, 0x9c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, | ||
| 336 | /* SATA Controller IDE (Lynx Point-LP) */ | ||
| 337 | { 0x8086, 0x9c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, | ||
| 338 | /* SATA Controller IDE (Lynx Point-LP) */ | ||
| 339 | { 0x8086, 0x9c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, | ||
| 332 | /* SATA Controller IDE (DH89xxCC) */ | 340 | /* SATA Controller IDE (DH89xxCC) */ |
| 333 | { 0x8086, 0x2326, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, | 341 | { 0x8086, 0x2326, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
| 334 | { } /* terminate list */ | 342 | { } /* terminate list */ |
diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c index f9eaa82311a9..555c07afa05b 100644 --- a/drivers/ata/libahci.c +++ b/drivers/ata/libahci.c | |||
| @@ -1139,7 +1139,7 @@ static void ahci_dev_config(struct ata_device *dev) | |||
| 1139 | } | 1139 | } |
| 1140 | } | 1140 | } |
| 1141 | 1141 | ||
| 1142 | static unsigned int ahci_dev_classify(struct ata_port *ap) | 1142 | unsigned int ahci_dev_classify(struct ata_port *ap) |
| 1143 | { | 1143 | { |
| 1144 | void __iomem *port_mmio = ahci_port_base(ap); | 1144 | void __iomem *port_mmio = ahci_port_base(ap); |
| 1145 | struct ata_taskfile tf; | 1145 | struct ata_taskfile tf; |
| @@ -1153,6 +1153,7 @@ static unsigned int ahci_dev_classify(struct ata_port *ap) | |||
| 1153 | 1153 | ||
| 1154 | return ata_dev_classify(&tf); | 1154 | return ata_dev_classify(&tf); |
| 1155 | } | 1155 | } |
| 1156 | EXPORT_SYMBOL_GPL(ahci_dev_classify); | ||
| 1156 | 1157 | ||
| 1157 | void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, | 1158 | void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
| 1158 | u32 opts) | 1159 | u32 opts) |
diff --git a/drivers/ata/libata-acpi.c b/drivers/ata/libata-acpi.c index 902b5a457170..fd9ecf74e631 100644 --- a/drivers/ata/libata-acpi.c +++ b/drivers/ata/libata-acpi.c | |||
| @@ -60,17 +60,7 @@ acpi_handle ata_ap_acpi_handle(struct ata_port *ap) | |||
| 60 | if (ap->flags & ATA_FLAG_ACPI_SATA) | 60 | if (ap->flags & ATA_FLAG_ACPI_SATA) |
| 61 | return NULL; | 61 | return NULL; |
| 62 | 62 | ||
| 63 | /* | 63 | return acpi_get_child(DEVICE_ACPI_HANDLE(ap->host->dev), ap->port_no); |
| 64 | * If acpi bind operation has already happened, we can get the handle | ||
| 65 | * for the port by checking the corresponding scsi_host device's | ||
| 66 | * firmware node, otherwise we will need to find out the handle from | ||
| 67 | * its parent's acpi node. | ||
| 68 | */ | ||
| 69 | if (ap->scsi_host) | ||
| 70 | return DEVICE_ACPI_HANDLE(&ap->scsi_host->shost_gendev); | ||
| 71 | else | ||
| 72 | return acpi_get_child(DEVICE_ACPI_HANDLE(ap->host->dev), | ||
| 73 | ap->port_no); | ||
| 74 | } | 64 | } |
| 75 | EXPORT_SYMBOL(ata_ap_acpi_handle); | 65 | EXPORT_SYMBOL(ata_ap_acpi_handle); |
| 76 | 66 | ||
| @@ -1101,6 +1091,9 @@ static int ata_acpi_bind_host(struct ata_port *ap, acpi_handle *handle) | |||
| 1101 | if (!*handle) | 1091 | if (!*handle) |
| 1102 | return -ENODEV; | 1092 | return -ENODEV; |
| 1103 | 1093 | ||
| 1094 | if (ata_acpi_gtm(ap, &ap->__acpi_init_gtm) == 0) | ||
| 1095 | ap->pflags |= ATA_PFLAG_INIT_GTM_VALID; | ||
| 1096 | |||
| 1104 | return 0; | 1097 | return 0; |
| 1105 | } | 1098 | } |
| 1106 | 1099 | ||
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c index fadd5866d40f..8e1039c8e159 100644 --- a/drivers/ata/libata-core.c +++ b/drivers/ata/libata-core.c | |||
| @@ -4062,7 +4062,7 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = { | |||
| 4062 | { "_NEC DV5800A", NULL, ATA_HORKAGE_NODMA }, | 4062 | { "_NEC DV5800A", NULL, ATA_HORKAGE_NODMA }, |
| 4063 | { "SAMSUNG CD-ROM SN-124", "N001", ATA_HORKAGE_NODMA }, | 4063 | { "SAMSUNG CD-ROM SN-124", "N001", ATA_HORKAGE_NODMA }, |
| 4064 | { "Seagate STT20000A", NULL, ATA_HORKAGE_NODMA }, | 4064 | { "Seagate STT20000A", NULL, ATA_HORKAGE_NODMA }, |
| 4065 | { "2GB ATA Flash Disk", "ADMA428M", ATA_HORKAGE_NODMA }, | 4065 | { " 2GB ATA Flash Disk", "ADMA428M", ATA_HORKAGE_NODMA }, |
| 4066 | /* Odd clown on sil3726/4726 PMPs */ | 4066 | /* Odd clown on sil3726/4726 PMPs */ |
| 4067 | { "Config Disk", NULL, ATA_HORKAGE_DISABLE }, | 4067 | { "Config Disk", NULL, ATA_HORKAGE_DISABLE }, |
| 4068 | 4068 | ||
| @@ -4128,6 +4128,7 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = { | |||
| 4128 | 4128 | ||
| 4129 | /* Devices that do not need bridging limits applied */ | 4129 | /* Devices that do not need bridging limits applied */ |
| 4130 | { "MTRON MSP-SATA*", NULL, ATA_HORKAGE_BRIDGE_OK, }, | 4130 | { "MTRON MSP-SATA*", NULL, ATA_HORKAGE_BRIDGE_OK, }, |
| 4131 | { "BUFFALO HD-QSU2/R5", NULL, ATA_HORKAGE_BRIDGE_OK, }, | ||
| 4131 | 4132 | ||
| 4132 | /* Devices which aren't very happy with higher link speeds */ | 4133 | /* Devices which aren't very happy with higher link speeds */ |
| 4133 | { "WD My Book", NULL, ATA_HORKAGE_1_5_GBPS, }, | 4134 | { "WD My Book", NULL, ATA_HORKAGE_1_5_GBPS, }, |
diff --git a/drivers/ata/pata_atiixp.c b/drivers/ata/pata_atiixp.c index 361c75cea57b..24e51056ac26 100644 --- a/drivers/ata/pata_atiixp.c +++ b/drivers/ata/pata_atiixp.c | |||
| @@ -20,6 +20,7 @@ | |||
| 20 | #include <linux/delay.h> | 20 | #include <linux/delay.h> |
| 21 | #include <scsi/scsi_host.h> | 21 | #include <scsi/scsi_host.h> |
| 22 | #include <linux/libata.h> | 22 | #include <linux/libata.h> |
| 23 | #include <linux/dmi.h> | ||
| 23 | 24 | ||
| 24 | #define DRV_NAME "pata_atiixp" | 25 | #define DRV_NAME "pata_atiixp" |
| 25 | #define DRV_VERSION "0.4.6" | 26 | #define DRV_VERSION "0.4.6" |
| @@ -33,11 +34,26 @@ enum { | |||
| 33 | ATIIXP_IDE_UDMA_MODE = 0x56 | 34 | ATIIXP_IDE_UDMA_MODE = 0x56 |
| 34 | }; | 35 | }; |
| 35 | 36 | ||
| 37 | static const struct dmi_system_id attixp_cable_override_dmi_table[] = { | ||
| 38 | { | ||
| 39 | /* Board has onboard PATA<->SATA converters */ | ||
| 40 | .ident = "MSI E350DM-E33", | ||
| 41 | .matches = { | ||
| 42 | DMI_MATCH(DMI_BOARD_VENDOR, "MSI"), | ||
| 43 | DMI_MATCH(DMI_BOARD_NAME, "E350DM-E33(MS-7720)"), | ||
| 44 | }, | ||
| 45 | }, | ||
| 46 | { } | ||
| 47 | }; | ||
| 48 | |||
| 36 | static int atiixp_cable_detect(struct ata_port *ap) | 49 | static int atiixp_cable_detect(struct ata_port *ap) |
| 37 | { | 50 | { |
| 38 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | 51 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
| 39 | u8 udma; | 52 | u8 udma; |
| 40 | 53 | ||
| 54 | if (dmi_check_system(attixp_cable_override_dmi_table)) | ||
| 55 | return ATA_CBL_PATA40_SHORT; | ||
| 56 | |||
| 41 | /* Hack from drivers/ide/pci. Really we want to know how to do the | 57 | /* Hack from drivers/ide/pci. Really we want to know how to do the |
| 42 | raw detection not play follow the bios mode guess */ | 58 | raw detection not play follow the bios mode guess */ |
| 43 | pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ap->port_no, &udma); | 59 | pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ap->port_no, &udma); |
diff --git a/drivers/block/drbd/drbd_bitmap.c b/drivers/block/drbd/drbd_bitmap.c index ba91b408abad..d84566496746 100644 --- a/drivers/block/drbd/drbd_bitmap.c +++ b/drivers/block/drbd/drbd_bitmap.c | |||
| @@ -889,6 +889,7 @@ struct bm_aio_ctx { | |||
| 889 | unsigned int done; | 889 | unsigned int done; |
| 890 | unsigned flags; | 890 | unsigned flags; |
| 891 | #define BM_AIO_COPY_PAGES 1 | 891 | #define BM_AIO_COPY_PAGES 1 |
| 892 | #define BM_WRITE_ALL_PAGES 2 | ||
| 892 | int error; | 893 | int error; |
| 893 | struct kref kref; | 894 | struct kref kref; |
| 894 | }; | 895 | }; |
| @@ -1059,7 +1060,8 @@ static int bm_rw(struct drbd_conf *mdev, int rw, unsigned flags, unsigned lazy_w | |||
| 1059 | if (lazy_writeout_upper_idx && i == lazy_writeout_upper_idx) | 1060 | if (lazy_writeout_upper_idx && i == lazy_writeout_upper_idx) |
| 1060 | break; | 1061 | break; |
| 1061 | if (rw & WRITE) { | 1062 | if (rw & WRITE) { |
| 1062 | if (bm_test_page_unchanged(b->bm_pages[i])) { | 1063 | if (!(flags & BM_WRITE_ALL_PAGES) && |
| 1064 | bm_test_page_unchanged(b->bm_pages[i])) { | ||
| 1063 | dynamic_dev_dbg(DEV, "skipped bm write for idx %u\n", i); | 1065 | dynamic_dev_dbg(DEV, "skipped bm write for idx %u\n", i); |
| 1064 | continue; | 1066 | continue; |
| 1065 | } | 1067 | } |
| @@ -1141,6 +1143,17 @@ int drbd_bm_write(struct drbd_conf *mdev) __must_hold(local) | |||
| 1141 | } | 1143 | } |
| 1142 | 1144 | ||
| 1143 | /** | 1145 | /** |
| 1146 | * drbd_bm_write_all() - Write the whole bitmap to its on disk location. | ||
| 1147 | * @mdev: DRBD device. | ||
| 1148 | * | ||
| 1149 | * Will write all pages. | ||
| 1150 | */ | ||
| 1151 | int drbd_bm_write_all(struct drbd_conf *mdev) __must_hold(local) | ||
| 1152 | { | ||
| 1153 | return bm_rw(mdev, WRITE, BM_WRITE_ALL_PAGES, 0); | ||
| 1154 | } | ||
| 1155 | |||
| 1156 | /** | ||
| 1144 | * drbd_bm_lazy_write_out() - Write bitmap pages 0 to @upper_idx-1, if they have changed. | 1157 | * drbd_bm_lazy_write_out() - Write bitmap pages 0 to @upper_idx-1, if they have changed. |
| 1145 | * @mdev: DRBD device. | 1158 | * @mdev: DRBD device. |
| 1146 | * @upper_idx: 0: write all changed pages; +ve: page index to stop scanning for changed pages | 1159 | * @upper_idx: 0: write all changed pages; +ve: page index to stop scanning for changed pages |
diff --git a/drivers/block/drbd/drbd_int.h b/drivers/block/drbd/drbd_int.h index b2ca143d0053..b953cc7c9c00 100644 --- a/drivers/block/drbd/drbd_int.h +++ b/drivers/block/drbd/drbd_int.h | |||
| @@ -1469,6 +1469,7 @@ extern int drbd_bm_e_weight(struct drbd_conf *mdev, unsigned long enr); | |||
| 1469 | extern int drbd_bm_write_page(struct drbd_conf *mdev, unsigned int idx) __must_hold(local); | 1469 | extern int drbd_bm_write_page(struct drbd_conf *mdev, unsigned int idx) __must_hold(local); |
| 1470 | extern int drbd_bm_read(struct drbd_conf *mdev) __must_hold(local); | 1470 | extern int drbd_bm_read(struct drbd_conf *mdev) __must_hold(local); |
| 1471 | extern int drbd_bm_write(struct drbd_conf *mdev) __must_hold(local); | 1471 | extern int drbd_bm_write(struct drbd_conf *mdev) __must_hold(local); |
| 1472 | extern int drbd_bm_write_all(struct drbd_conf *mdev) __must_hold(local); | ||
| 1472 | extern int drbd_bm_write_copy_pages(struct drbd_conf *mdev) __must_hold(local); | 1473 | extern int drbd_bm_write_copy_pages(struct drbd_conf *mdev) __must_hold(local); |
| 1473 | extern unsigned long drbd_bm_ALe_set_all(struct drbd_conf *mdev, | 1474 | extern unsigned long drbd_bm_ALe_set_all(struct drbd_conf *mdev, |
| 1474 | unsigned long al_enr); | 1475 | unsigned long al_enr); |
diff --git a/drivers/block/drbd/drbd_main.c b/drivers/block/drbd/drbd_main.c index dbe6135a2abe..f93a0320e952 100644 --- a/drivers/block/drbd/drbd_main.c +++ b/drivers/block/drbd/drbd_main.c | |||
| @@ -79,6 +79,7 @@ static int w_md_sync(struct drbd_conf *mdev, struct drbd_work *w, int unused); | |||
| 79 | static void md_sync_timer_fn(unsigned long data); | 79 | static void md_sync_timer_fn(unsigned long data); |
| 80 | static int w_bitmap_io(struct drbd_conf *mdev, struct drbd_work *w, int unused); | 80 | static int w_bitmap_io(struct drbd_conf *mdev, struct drbd_work *w, int unused); |
| 81 | static int w_go_diskless(struct drbd_conf *mdev, struct drbd_work *w, int unused); | 81 | static int w_go_diskless(struct drbd_conf *mdev, struct drbd_work *w, int unused); |
| 82 | static void _tl_clear(struct drbd_conf *mdev); | ||
| 82 | 83 | ||
| 83 | MODULE_AUTHOR("Philipp Reisner <phil@linbit.com>, " | 84 | MODULE_AUTHOR("Philipp Reisner <phil@linbit.com>, " |
| 84 | "Lars Ellenberg <lars@linbit.com>"); | 85 | "Lars Ellenberg <lars@linbit.com>"); |
| @@ -432,19 +433,10 @@ static void _tl_restart(struct drbd_conf *mdev, enum drbd_req_event what) | |||
| 432 | 433 | ||
| 433 | /* Actions operating on the disk state, also want to work on | 434 | /* Actions operating on the disk state, also want to work on |
| 434 | requests that got barrier acked. */ | 435 | requests that got barrier acked. */ |
| 435 | switch (what) { | ||
| 436 | case fail_frozen_disk_io: | ||
| 437 | case restart_frozen_disk_io: | ||
| 438 | list_for_each_safe(le, tle, &mdev->barrier_acked_requests) { | ||
| 439 | req = list_entry(le, struct drbd_request, tl_requests); | ||
| 440 | _req_mod(req, what); | ||
| 441 | } | ||
| 442 | 436 | ||
| 443 | case connection_lost_while_pending: | 437 | list_for_each_safe(le, tle, &mdev->barrier_acked_requests) { |
| 444 | case resend: | 438 | req = list_entry(le, struct drbd_request, tl_requests); |
| 445 | break; | 439 | _req_mod(req, what); |
| 446 | default: | ||
| 447 | dev_err(DEV, "what = %d in _tl_restart()\n", what); | ||
| 448 | } | 440 | } |
| 449 | } | 441 | } |
| 450 | 442 | ||
| @@ -459,11 +451,16 @@ static void _tl_restart(struct drbd_conf *mdev, enum drbd_req_event what) | |||
| 459 | */ | 451 | */ |
| 460 | void tl_clear(struct drbd_conf *mdev) | 452 | void tl_clear(struct drbd_conf *mdev) |
| 461 | { | 453 | { |
| 454 | spin_lock_irq(&mdev->req_lock); | ||
| 455 | _tl_clear(mdev); | ||
| 456 | spin_unlock_irq(&mdev->req_lock); | ||
| 457 | } | ||
| 458 | |||
| 459 | static void _tl_clear(struct drbd_conf *mdev) | ||
| 460 | { | ||
| 462 | struct list_head *le, *tle; | 461 | struct list_head *le, *tle; |
| 463 | struct drbd_request *r; | 462 | struct drbd_request *r; |
| 464 | 463 | ||
| 465 | spin_lock_irq(&mdev->req_lock); | ||
| 466 | |||
| 467 | _tl_restart(mdev, connection_lost_while_pending); | 464 | _tl_restart(mdev, connection_lost_while_pending); |
| 468 | 465 | ||
| 469 | /* we expect this list to be empty. */ | 466 | /* we expect this list to be empty. */ |
| @@ -482,7 +479,6 @@ void tl_clear(struct drbd_conf *mdev) | |||
| 482 | 479 | ||
| 483 | memset(mdev->app_reads_hash, 0, APP_R_HSIZE*sizeof(void *)); | 480 | memset(mdev->app_reads_hash, 0, APP_R_HSIZE*sizeof(void *)); |
| 484 | 481 | ||
| 485 | spin_unlock_irq(&mdev->req_lock); | ||
| 486 | } | 482 | } |
| 487 | 483 | ||
| 488 | void tl_restart(struct drbd_conf *mdev, enum drbd_req_event what) | 484 | void tl_restart(struct drbd_conf *mdev, enum drbd_req_event what) |
| @@ -1476,12 +1472,12 @@ static void after_state_ch(struct drbd_conf *mdev, union drbd_state os, | |||
| 1476 | if (ns.susp_fen) { | 1472 | if (ns.susp_fen) { |
| 1477 | /* case1: The outdate peer handler is successful: */ | 1473 | /* case1: The outdate peer handler is successful: */ |
| 1478 | if (os.pdsk > D_OUTDATED && ns.pdsk <= D_OUTDATED) { | 1474 | if (os.pdsk > D_OUTDATED && ns.pdsk <= D_OUTDATED) { |
| 1479 | tl_clear(mdev); | ||
| 1480 | if (test_bit(NEW_CUR_UUID, &mdev->flags)) { | 1475 | if (test_bit(NEW_CUR_UUID, &mdev->flags)) { |
| 1481 | drbd_uuid_new_current(mdev); | 1476 | drbd_uuid_new_current(mdev); |
| 1482 | clear_bit(NEW_CUR_UUID, &mdev->flags); | 1477 | clear_bit(NEW_CUR_UUID, &mdev->flags); |
| 1483 | } | 1478 | } |
| 1484 | spin_lock_irq(&mdev->req_lock); | 1479 | spin_lock_irq(&mdev->req_lock); |
| 1480 | _tl_clear(mdev); | ||
| 1485 | _drbd_set_state(_NS(mdev, susp_fen, 0), CS_VERBOSE, NULL); | 1481 | _drbd_set_state(_NS(mdev, susp_fen, 0), CS_VERBOSE, NULL); |
| 1486 | spin_unlock_irq(&mdev->req_lock); | 1482 | spin_unlock_irq(&mdev->req_lock); |
| 1487 | } | 1483 | } |
diff --git a/drivers/block/drbd/drbd_nl.c b/drivers/block/drbd/drbd_nl.c index fb9dce8daa24..edb490aad8b4 100644 --- a/drivers/block/drbd/drbd_nl.c +++ b/drivers/block/drbd/drbd_nl.c | |||
| @@ -674,8 +674,8 @@ enum determine_dev_size drbd_determine_dev_size(struct drbd_conf *mdev, enum dds | |||
| 674 | la_size_changed && md_moved ? "size changed and md moved" : | 674 | la_size_changed && md_moved ? "size changed and md moved" : |
| 675 | la_size_changed ? "size changed" : "md moved"); | 675 | la_size_changed ? "size changed" : "md moved"); |
| 676 | /* next line implicitly does drbd_suspend_io()+drbd_resume_io() */ | 676 | /* next line implicitly does drbd_suspend_io()+drbd_resume_io() */ |
| 677 | err = drbd_bitmap_io(mdev, &drbd_bm_write, | 677 | err = drbd_bitmap_io(mdev, md_moved ? &drbd_bm_write_all : &drbd_bm_write, |
| 678 | "size changed", BM_LOCKED_MASK); | 678 | "size changed", BM_LOCKED_MASK); |
| 679 | if (err) { | 679 | if (err) { |
| 680 | rv = dev_size_error; | 680 | rv = dev_size_error; |
| 681 | goto out; | 681 | goto out; |
diff --git a/drivers/block/drbd/drbd_req.c b/drivers/block/drbd/drbd_req.c index 910335c30927..01b2ac641c7b 100644 --- a/drivers/block/drbd/drbd_req.c +++ b/drivers/block/drbd/drbd_req.c | |||
| @@ -695,6 +695,12 @@ int __req_mod(struct drbd_request *req, enum drbd_req_event what, | |||
| 695 | break; | 695 | break; |
| 696 | 696 | ||
| 697 | case resend: | 697 | case resend: |
| 698 | /* Simply complete (local only) READs. */ | ||
| 699 | if (!(req->rq_state & RQ_WRITE) && !req->w.cb) { | ||
| 700 | _req_may_be_done(req, m); | ||
| 701 | break; | ||
| 702 | } | ||
| 703 | |||
| 698 | /* If RQ_NET_OK is already set, we got a P_WRITE_ACK or P_RECV_ACK | 704 | /* If RQ_NET_OK is already set, we got a P_WRITE_ACK or P_RECV_ACK |
| 699 | before the connection loss (B&C only); only P_BARRIER_ACK was missing. | 705 | before the connection loss (B&C only); only P_BARRIER_ACK was missing. |
| 700 | Trowing them out of the TL here by pretending we got a BARRIER_ACK | 706 | Trowing them out of the TL here by pretending we got a BARRIER_ACK |
| @@ -834,7 +840,15 @@ static int drbd_make_request_common(struct drbd_conf *mdev, struct bio *bio, uns | |||
| 834 | req->private_bio = NULL; | 840 | req->private_bio = NULL; |
| 835 | } | 841 | } |
| 836 | if (rw == WRITE) { | 842 | if (rw == WRITE) { |
| 837 | remote = 1; | 843 | /* Need to replicate writes. Unless it is an empty flush, |
| 844 | * which is better mapped to a DRBD P_BARRIER packet, | ||
| 845 | * also for drbd wire protocol compatibility reasons. */ | ||
| 846 | if (unlikely(size == 0)) { | ||
| 847 | /* The only size==0 bios we expect are empty flushes. */ | ||
| 848 | D_ASSERT(bio->bi_rw & REQ_FLUSH); | ||
| 849 | remote = 0; | ||
| 850 | } else | ||
| 851 | remote = 1; | ||
| 838 | } else { | 852 | } else { |
| 839 | /* READ || READA */ | 853 | /* READ || READA */ |
| 840 | if (local) { | 854 | if (local) { |
| @@ -870,8 +884,11 @@ static int drbd_make_request_common(struct drbd_conf *mdev, struct bio *bio, uns | |||
| 870 | * extent. This waits for any resync activity in the corresponding | 884 | * extent. This waits for any resync activity in the corresponding |
| 871 | * resync extent to finish, and, if necessary, pulls in the target | 885 | * resync extent to finish, and, if necessary, pulls in the target |
| 872 | * extent into the activity log, which involves further disk io because | 886 | * extent into the activity log, which involves further disk io because |
| 873 | * of transactional on-disk meta data updates. */ | 887 | * of transactional on-disk meta data updates. |
| 874 | if (rw == WRITE && local && !test_bit(AL_SUSPENDED, &mdev->flags)) { | 888 | * Empty flushes don't need to go into the activity log, they can only |
| 889 | * flush data for pending writes which are already in there. */ | ||
| 890 | if (rw == WRITE && local && size | ||
| 891 | && !test_bit(AL_SUSPENDED, &mdev->flags)) { | ||
| 875 | req->rq_state |= RQ_IN_ACT_LOG; | 892 | req->rq_state |= RQ_IN_ACT_LOG; |
| 876 | drbd_al_begin_io(mdev, sector); | 893 | drbd_al_begin_io(mdev, sector); |
| 877 | } | 894 | } |
| @@ -994,7 +1011,10 @@ allocate_barrier: | |||
| 994 | if (rw == WRITE && _req_conflicts(req)) | 1011 | if (rw == WRITE && _req_conflicts(req)) |
| 995 | goto fail_conflicting; | 1012 | goto fail_conflicting; |
| 996 | 1013 | ||
| 997 | list_add_tail(&req->tl_requests, &mdev->newest_tle->requests); | 1014 | /* no point in adding empty flushes to the transfer log, |
| 1015 | * they are mapped to drbd barriers already. */ | ||
| 1016 | if (likely(size!=0)) | ||
| 1017 | list_add_tail(&req->tl_requests, &mdev->newest_tle->requests); | ||
| 998 | 1018 | ||
| 999 | /* NOTE remote first: to get the concurrent write detection right, | 1019 | /* NOTE remote first: to get the concurrent write detection right, |
| 1000 | * we must register the request before start of local IO. */ | 1020 | * we must register the request before start of local IO. */ |
| @@ -1014,6 +1034,14 @@ allocate_barrier: | |||
| 1014 | mdev->net_conf->on_congestion != OC_BLOCK && mdev->agreed_pro_version >= 96) | 1034 | mdev->net_conf->on_congestion != OC_BLOCK && mdev->agreed_pro_version >= 96) |
| 1015 | maybe_pull_ahead(mdev); | 1035 | maybe_pull_ahead(mdev); |
| 1016 | 1036 | ||
| 1037 | /* If this was a flush, queue a drbd barrier/start a new epoch. | ||
| 1038 | * Unless the current epoch was empty anyways, or we are not currently | ||
| 1039 | * replicating, in which case there is no point. */ | ||
| 1040 | if (unlikely(bio->bi_rw & REQ_FLUSH) | ||
| 1041 | && mdev->newest_tle->n_writes | ||
| 1042 | && drbd_should_do_remote(mdev->state)) | ||
| 1043 | queue_barrier(mdev); | ||
| 1044 | |||
| 1017 | spin_unlock_irq(&mdev->req_lock); | 1045 | spin_unlock_irq(&mdev->req_lock); |
| 1018 | kfree(b); /* if someone else has beaten us to it... */ | 1046 | kfree(b); /* if someone else has beaten us to it... */ |
| 1019 | 1047 | ||
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 7f0b5ca78516..bace9e98f75d 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig | |||
| @@ -40,4 +40,17 @@ config COMMON_CLK_WM831X | |||
| 40 | Supports the clocking subsystem of the WM831x/2x series of | 40 | Supports the clocking subsystem of the WM831x/2x series of |
| 41 | PMICs from Wolfson Microlectronics. | 41 | PMICs from Wolfson Microlectronics. |
| 42 | 42 | ||
| 43 | config COMMON_CLK_VERSATILE | ||
| 44 | bool "Clock driver for ARM Reference designs" | ||
| 45 | depends on ARCH_INTEGRATOR || ARCH_REALVIEW | ||
| 46 | ---help--- | ||
| 47 | Supports clocking on ARM Reference designs Integrator/AP, | ||
| 48 | Integrator/CP, RealView PB1176, EB, PB11MP and PBX. | ||
| 49 | |||
| 50 | config COMMON_CLK_MAX77686 | ||
| 51 | tristate "Clock driver for Maxim 77686 MFD" | ||
| 52 | depends on MFD_MAX77686 | ||
| 53 | ---help--- | ||
| 54 | This driver supports Maxim 77686 crystal oscillator clock. | ||
| 55 | |||
| 43 | endmenu | 56 | endmenu |
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 5869ea387054..6327536b4900 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile | |||
| @@ -9,7 +9,14 @@ obj-$(CONFIG_ARCH_MXS) += mxs/ | |||
| 9 | obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/ | 9 | obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/ |
| 10 | obj-$(CONFIG_PLAT_SPEAR) += spear/ | 10 | obj-$(CONFIG_PLAT_SPEAR) += spear/ |
| 11 | obj-$(CONFIG_ARCH_U300) += clk-u300.o | 11 | obj-$(CONFIG_ARCH_U300) += clk-u300.o |
| 12 | obj-$(CONFIG_ARCH_INTEGRATOR) += versatile/ | 12 | obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/ |
| 13 | obj-$(CONFIG_ARCH_PRIMA2) += clk-prima2.o | ||
| 14 | ifeq ($(CONFIG_COMMON_CLK), y) | ||
| 15 | obj-$(CONFIG_ARCH_MMP) += mmp/ | ||
| 16 | endif | ||
| 17 | obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o | ||
| 18 | obj-$(CONFIG_ARCH_U8500) += ux500/ | ||
| 13 | 19 | ||
| 14 | # Chip specific | 20 | # Chip specific |
| 15 | obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o | 21 | obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o |
| 22 | obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o | ||
diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/clk-ls1x.c new file mode 100644 index 000000000000..f20b750235f6 --- /dev/null +++ b/drivers/clk/clk-ls1x.c | |||
| @@ -0,0 +1,111 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2012 Zhang, Keguang <keguang.zhang@gmail.com> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it | ||
| 5 | * under the terms of the GNU General Public License as published by the | ||
| 6 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 7 | * option) any later version. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #include <linux/clkdev.h> | ||
| 11 | #include <linux/clk-provider.h> | ||
| 12 | #include <linux/io.h> | ||
| 13 | #include <linux/slab.h> | ||
| 14 | #include <linux/err.h> | ||
| 15 | |||
| 16 | #include <loongson1.h> | ||
| 17 | |||
| 18 | #define OSC 33 | ||
| 19 | |||
| 20 | static DEFINE_SPINLOCK(_lock); | ||
| 21 | |||
| 22 | static int ls1x_pll_clk_enable(struct clk_hw *hw) | ||
| 23 | { | ||
| 24 | return 0; | ||
| 25 | } | ||
| 26 | |||
| 27 | static void ls1x_pll_clk_disable(struct clk_hw *hw) | ||
| 28 | { | ||
| 29 | } | ||
| 30 | |||
| 31 | static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw, | ||
| 32 | unsigned long parent_rate) | ||
| 33 | { | ||
| 34 | u32 pll, rate; | ||
| 35 | |||
| 36 | pll = __raw_readl(LS1X_CLK_PLL_FREQ); | ||
| 37 | rate = ((12 + (pll & 0x3f)) * 1000000) + | ||
| 38 | ((((pll >> 8) & 0x3ff) * 1000000) >> 10); | ||
| 39 | rate *= OSC; | ||
| 40 | rate >>= 1; | ||
| 41 | |||
| 42 | return rate; | ||
| 43 | } | ||
| 44 | |||
| 45 | static const struct clk_ops ls1x_pll_clk_ops = { | ||
| 46 | .enable = ls1x_pll_clk_enable, | ||
| 47 | .disable = ls1x_pll_clk_disable, | ||
| 48 | .recalc_rate = ls1x_pll_recalc_rate, | ||
| 49 | }; | ||
| 50 | |||
| 51 | static struct clk * __init clk_register_pll(struct device *dev, | ||
| 52 | const char *name, const char *parent_name, unsigned long flags) | ||
| 53 | { | ||
| 54 | struct clk_hw *hw; | ||
| 55 | struct clk *clk; | ||
| 56 | struct clk_init_data init; | ||
| 57 | |||
| 58 | /* allocate the divider */ | ||
| 59 | hw = kzalloc(sizeof(struct clk_hw), GFP_KERNEL); | ||
| 60 | if (!hw) { | ||
| 61 | pr_err("%s: could not allocate clk_hw\n", __func__); | ||
| 62 | return ERR_PTR(-ENOMEM); | ||
| 63 | } | ||
| 64 | |||
| 65 | init.name = name; | ||
| 66 | init.ops = &ls1x_pll_clk_ops; | ||
| 67 | init.flags = flags | CLK_IS_BASIC; | ||
| 68 | init.parent_names = (parent_name ? &parent_name : NULL); | ||
| 69 | init.num_parents = (parent_name ? 1 : 0); | ||
| 70 | hw->init = &init; | ||
| 71 | |||
| 72 | /* register the clock */ | ||
| 73 | clk = clk_register(dev, hw); | ||
| 74 | |||
| 75 | if (IS_ERR(clk)) | ||
| 76 | kfree(hw); | ||
| 77 | |||
| 78 | return clk; | ||
| 79 | } | ||
| 80 | |||
| 81 | void __init ls1x_clk_init(void) | ||
| 82 | { | ||
| 83 | struct clk *clk; | ||
| 84 | |||
| 85 | clk = clk_register_pll(NULL, "pll_clk", NULL, CLK_IS_ROOT); | ||
| 86 | clk_prepare_enable(clk); | ||
| 87 | |||
| 88 | clk = clk_register_divider(NULL, "cpu_clk", "pll_clk", | ||
| 89 | CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_CPU_SHIFT, | ||
| 90 | DIV_CPU_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock); | ||
| 91 | clk_prepare_enable(clk); | ||
| 92 | clk_register_clkdev(clk, "cpu", NULL); | ||
| 93 | |||
| 94 | clk = clk_register_divider(NULL, "dc_clk", "pll_clk", | ||
| 95 | CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT, | ||
| 96 | DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock); | ||
| 97 | clk_prepare_enable(clk); | ||
| 98 | clk_register_clkdev(clk, "dc", NULL); | ||
| 99 | |||
| 100 | clk = clk_register_divider(NULL, "ahb_clk", "pll_clk", | ||
| 101 | CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT, | ||
| 102 | DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock); | ||
| 103 | clk_prepare_enable(clk); | ||
| 104 | clk_register_clkdev(clk, "ahb", NULL); | ||
| 105 | clk_register_clkdev(clk, "stmmaceth", NULL); | ||
| 106 | |||
| 107 | clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1, 2); | ||
| 108 | clk_prepare_enable(clk); | ||
| 109 | clk_register_clkdev(clk, "apb", NULL); | ||
| 110 | clk_register_clkdev(clk, "serial8250", NULL); | ||
| 111 | } | ||
diff --git a/drivers/clk/clk-max77686.c b/drivers/clk/clk-max77686.c new file mode 100644 index 000000000000..ac5f5434cb9a --- /dev/null +++ b/drivers/clk/clk-max77686.c | |||
| @@ -0,0 +1,244 @@ | |||
| 1 | /* | ||
| 2 | * clk-max77686.c - Clock driver for Maxim 77686 | ||
| 3 | * | ||
| 4 | * Copyright (C) 2012 Samsung Electornics | ||
| 5 | * Jonghwa Lee <jonghwa3.lee@samsung.com> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License as published by the | ||
| 9 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 10 | * option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 20 | * | ||
| 21 | */ | ||
| 22 | |||
| 23 | #include <linux/kernel.h> | ||
| 24 | #include <linux/slab.h> | ||
| 25 | #include <linux/err.h> | ||
| 26 | #include <linux/platform_device.h> | ||
| 27 | #include <linux/mfd/max77686.h> | ||
| 28 | #include <linux/mfd/max77686-private.h> | ||
| 29 | #include <linux/clk-provider.h> | ||
| 30 | #include <linux/mutex.h> | ||
| 31 | #include <linux/clkdev.h> | ||
| 32 | |||
| 33 | enum { | ||
| 34 | MAX77686_CLK_AP = 0, | ||
| 35 | MAX77686_CLK_CP, | ||
| 36 | MAX77686_CLK_PMIC, | ||
| 37 | MAX77686_CLKS_NUM, | ||
| 38 | }; | ||
| 39 | |||
| 40 | struct max77686_clk { | ||
| 41 | struct max77686_dev *iodev; | ||
| 42 | u32 mask; | ||
| 43 | struct clk_hw hw; | ||
| 44 | struct clk_lookup *lookup; | ||
| 45 | }; | ||
| 46 | |||
| 47 | static struct max77686_clk *get_max77686_clk(struct clk_hw *hw) | ||
| 48 | { | ||
| 49 | return container_of(hw, struct max77686_clk, hw); | ||
| 50 | } | ||
| 51 | |||
| 52 | static int max77686_clk_prepare(struct clk_hw *hw) | ||
| 53 | { | ||
| 54 | struct max77686_clk *max77686; | ||
| 55 | int ret; | ||
| 56 | |||
| 57 | max77686 = get_max77686_clk(hw); | ||
| 58 | if (!max77686) | ||
| 59 | return -ENOMEM; | ||
| 60 | |||
| 61 | ret = regmap_update_bits(max77686->iodev->regmap, | ||
| 62 | MAX77686_REG_32KHZ, max77686->mask, max77686->mask); | ||
| 63 | |||
| 64 | return ret; | ||
| 65 | } | ||
| 66 | |||
| 67 | static void max77686_clk_unprepare(struct clk_hw *hw) | ||
| 68 | { | ||
| 69 | struct max77686_clk *max77686; | ||
| 70 | |||
| 71 | max77686 = get_max77686_clk(hw); | ||
| 72 | if (!max77686) | ||
| 73 | return; | ||
| 74 | |||
| 75 | regmap_update_bits(max77686->iodev->regmap, | ||
| 76 | MAX77686_REG_32KHZ, max77686->mask, ~max77686->mask); | ||
| 77 | } | ||
| 78 | |||
| 79 | static int max77686_clk_is_enabled(struct clk_hw *hw) | ||
| 80 | { | ||
| 81 | struct max77686_clk *max77686; | ||
| 82 | int ret; | ||
| 83 | u32 val; | ||
| 84 | |||
| 85 | max77686 = get_max77686_clk(hw); | ||
| 86 | if (!max77686) | ||
| 87 | return -ENOMEM; | ||
| 88 | |||
| 89 | ret = regmap_read(max77686->iodev->regmap, | ||
| 90 | MAX77686_REG_32KHZ, &val); | ||
| 91 | |||
| 92 | if (ret < 0) | ||
| 93 | return -EINVAL; | ||
| 94 | |||
| 95 | return val & max77686->mask; | ||
| 96 | } | ||
| 97 | |||
| 98 | static struct clk_ops max77686_clk_ops = { | ||
| 99 | .prepare = max77686_clk_prepare, | ||
| 100 | .unprepare = max77686_clk_unprepare, | ||
| 101 | .is_enabled = max77686_clk_is_enabled, | ||
| 102 | }; | ||
| 103 | |||
| 104 | static struct clk_init_data max77686_clks_init[MAX77686_CLKS_NUM] = { | ||
| 105 | [MAX77686_CLK_AP] = { | ||
| 106 | .name = "32khz_ap", | ||
| 107 | .ops = &max77686_clk_ops, | ||
| 108 | .flags = CLK_IS_ROOT, | ||
| 109 | }, | ||
| 110 | [MAX77686_CLK_CP] = { | ||
| 111 | .name = "32khz_cp", | ||
| 112 | .ops = &max77686_clk_ops, | ||
| 113 | .flags = CLK_IS_ROOT, | ||
| 114 | }, | ||
| 115 | [MAX77686_CLK_PMIC] = { | ||
| 116 | .name = "32khz_pmic", | ||
| 117 | .ops = &max77686_clk_ops, | ||
| 118 | .flags = CLK_IS_ROOT, | ||
| 119 | }, | ||
| 120 | }; | ||
| 121 | |||
| 122 | static int max77686_clk_register(struct device *dev, | ||
| 123 | struct max77686_clk *max77686) | ||
| 124 | { | ||
| 125 | struct clk *clk; | ||
| 126 | struct clk_hw *hw = &max77686->hw; | ||
| 127 | |||
| 128 | clk = clk_register(dev, hw); | ||
| 129 | |||
| 130 | if (IS_ERR(clk)) | ||
| 131 | return -ENOMEM; | ||
| 132 | |||
| 133 | max77686->lookup = devm_kzalloc(dev, sizeof(struct clk_lookup), | ||
| 134 | GFP_KERNEL); | ||
| 135 | if (IS_ERR(max77686->lookup)) | ||
| 136 | return -ENOMEM; | ||
| 137 | |||
| 138 | max77686->lookup->con_id = hw->init->name; | ||
| 139 | max77686->lookup->clk = clk; | ||
| 140 | |||
| 141 | clkdev_add(max77686->lookup); | ||
| 142 | |||
| 143 | return 0; | ||
| 144 | } | ||
| 145 | |||
| 146 | static __devinit int max77686_clk_probe(struct platform_device *pdev) | ||
| 147 | { | ||
| 148 | struct max77686_dev *iodev = dev_get_drvdata(pdev->dev.parent); | ||
| 149 | struct max77686_clk **max77686_clks; | ||
| 150 | int i, ret; | ||
| 151 | |||
| 152 | max77686_clks = devm_kzalloc(&pdev->dev, sizeof(struct max77686_clk *) | ||
| 153 | * MAX77686_CLKS_NUM, GFP_KERNEL); | ||
| 154 | if (IS_ERR(max77686_clks)) | ||
| 155 | return -ENOMEM; | ||
| 156 | |||
| 157 | for (i = 0; i < MAX77686_CLKS_NUM; i++) { | ||
| 158 | max77686_clks[i] = devm_kzalloc(&pdev->dev, | ||
| 159 | sizeof(struct max77686_clk), GFP_KERNEL); | ||
| 160 | if (IS_ERR(max77686_clks[i])) | ||
| 161 | return -ENOMEM; | ||
| 162 | } | ||
| 163 | |||
| 164 | for (i = 0; i < MAX77686_CLKS_NUM; i++) { | ||
| 165 | max77686_clks[i]->iodev = iodev; | ||
| 166 | max77686_clks[i]->mask = 1 << i; | ||
| 167 | max77686_clks[i]->hw.init = &max77686_clks_init[i]; | ||
| 168 | |||
| 169 | ret = max77686_clk_register(&pdev->dev, max77686_clks[i]); | ||
| 170 | if (ret) { | ||
| 171 | switch (i) { | ||
| 172 | case MAX77686_CLK_AP: | ||
| 173 | dev_err(&pdev->dev, "Fail to register CLK_AP\n"); | ||
| 174 | goto err_clk_ap; | ||
| 175 | break; | ||
| 176 | case MAX77686_CLK_CP: | ||
| 177 | dev_err(&pdev->dev, "Fail to register CLK_CP\n"); | ||
| 178 | goto err_clk_cp; | ||
| 179 | break; | ||
| 180 | case MAX77686_CLK_PMIC: | ||
| 181 | dev_err(&pdev->dev, "Fail to register CLK_PMIC\n"); | ||
| 182 | goto err_clk_pmic; | ||
| 183 | } | ||
| 184 | } | ||
| 185 | } | ||
| 186 | |||
| 187 | platform_set_drvdata(pdev, max77686_clks); | ||
| 188 | |||
| 189 | goto out; | ||
| 190 | |||
| 191 | err_clk_pmic: | ||
| 192 | clkdev_drop(max77686_clks[MAX77686_CLK_CP]->lookup); | ||
| 193 | kfree(max77686_clks[MAX77686_CLK_CP]->hw.clk); | ||
| 194 | err_clk_cp: | ||
| 195 | clkdev_drop(max77686_clks[MAX77686_CLK_AP]->lookup); | ||
| 196 | kfree(max77686_clks[MAX77686_CLK_AP]->hw.clk); | ||
| 197 | err_clk_ap: | ||
| 198 | out: | ||
| 199 | return ret; | ||
| 200 | } | ||
| 201 | |||
| 202 | static int __devexit max77686_clk_remove(struct platform_device *pdev) | ||
| 203 | { | ||
| 204 | struct max77686_clk **max77686_clks = platform_get_drvdata(pdev); | ||
| 205 | int i; | ||
| 206 | |||
| 207 | for (i = 0; i < MAX77686_CLKS_NUM; i++) { | ||
| 208 | clkdev_drop(max77686_clks[i]->lookup); | ||
| 209 | kfree(max77686_clks[i]->hw.clk); | ||
| 210 | } | ||
| 211 | return 0; | ||
| 212 | } | ||
| 213 | |||
| 214 | static const struct platform_device_id max77686_clk_id[] = { | ||
| 215 | { "max77686-clk", 0}, | ||
| 216 | { }, | ||
| 217 | }; | ||
| 218 | MODULE_DEVICE_TABLE(platform, max77686_clk_id); | ||
| 219 | |||
| 220 | static struct platform_driver max77686_clk_driver = { | ||
| 221 | .driver = { | ||
| 222 | .name = "max77686-clk", | ||
| 223 | .owner = THIS_MODULE, | ||
| 224 | }, | ||
| 225 | .probe = max77686_clk_probe, | ||
| 226 | .remove = __devexit_p(max77686_clk_remove), | ||
| 227 | .id_table = max77686_clk_id, | ||
| 228 | }; | ||
| 229 | |||
| 230 | static int __init max77686_clk_init(void) | ||
| 231 | { | ||
| 232 | return platform_driver_register(&max77686_clk_driver); | ||
| 233 | } | ||
| 234 | subsys_initcall(max77686_clk_init); | ||
| 235 | |||
| 236 | static void __init max77686_clk_cleanup(void) | ||
| 237 | { | ||
| 238 | platform_driver_unregister(&max77686_clk_driver); | ||
| 239 | } | ||
| 240 | module_exit(max77686_clk_cleanup); | ||
| 241 | |||
| 242 | MODULE_DESCRIPTION("MAXIM 77686 Clock Driver"); | ||
| 243 | MODULE_AUTHOR("Jonghwa Lee <jonghwa3.lee@samsung.com>"); | ||
| 244 | MODULE_LICENSE("GPL"); | ||
diff --git a/drivers/clk/clk-prima2.c b/drivers/clk/clk-prima2.c new file mode 100644 index 000000000000..517874fa6858 --- /dev/null +++ b/drivers/clk/clk-prima2.c | |||
| @@ -0,0 +1,1171 @@ | |||
| 1 | /* | ||
| 2 | * Clock tree for CSR SiRFprimaII | ||
| 3 | * | ||
| 4 | * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. | ||
| 5 | * | ||
| 6 | * Licensed under GPLv2 or later. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <linux/module.h> | ||
| 10 | #include <linux/bitops.h> | ||
| 11 | #include <linux/io.h> | ||
| 12 | #include <linux/clk.h> | ||
| 13 | #include <linux/clkdev.h> | ||
| 14 | #include <linux/clk-provider.h> | ||
| 15 | #include <linux/of_address.h> | ||
| 16 | #include <linux/syscore_ops.h> | ||
| 17 | |||
| 18 | #define SIRFSOC_CLKC_CLK_EN0 0x0000 | ||
| 19 | #define SIRFSOC_CLKC_CLK_EN1 0x0004 | ||
| 20 | #define SIRFSOC_CLKC_REF_CFG 0x0014 | ||
| 21 | #define SIRFSOC_CLKC_CPU_CFG 0x0018 | ||
| 22 | #define SIRFSOC_CLKC_MEM_CFG 0x001c | ||
| 23 | #define SIRFSOC_CLKC_SYS_CFG 0x0020 | ||
| 24 | #define SIRFSOC_CLKC_IO_CFG 0x0024 | ||
| 25 | #define SIRFSOC_CLKC_DSP_CFG 0x0028 | ||
| 26 | #define SIRFSOC_CLKC_GFX_CFG 0x002c | ||
| 27 | #define SIRFSOC_CLKC_MM_CFG 0x0030 | ||
| 28 | #define SIRFSOC_CLKC_LCD_CFG 0x0034 | ||
| 29 | #define SIRFSOC_CLKC_MMC_CFG 0x0038 | ||
| 30 | #define SIRFSOC_CLKC_PLL1_CFG0 0x0040 | ||
| 31 | #define SIRFSOC_CLKC_PLL2_CFG0 0x0044 | ||
| 32 | #define SIRFSOC_CLKC_PLL3_CFG0 0x0048 | ||
| 33 | #define SIRFSOC_CLKC_PLL1_CFG1 0x004c | ||
| 34 | #define SIRFSOC_CLKC_PLL2_CFG1 0x0050 | ||
| 35 | #define SIRFSOC_CLKC_PLL3_CFG1 0x0054 | ||
| 36 | #define SIRFSOC_CLKC_PLL1_CFG2 0x0058 | ||
| 37 | #define SIRFSOC_CLKC_PLL2_CFG2 0x005c | ||
| 38 | #define SIRFSOC_CLKC_PLL3_CFG2 0x0060 | ||
| 39 | #define SIRFSOC_USBPHY_PLL_CTRL 0x0008 | ||
| 40 | #define SIRFSOC_USBPHY_PLL_POWERDOWN BIT(1) | ||
| 41 | #define SIRFSOC_USBPHY_PLL_BYPASS BIT(2) | ||
| 42 | #define SIRFSOC_USBPHY_PLL_LOCK BIT(3) | ||
| 43 | |||
| 44 | static void *sirfsoc_clk_vbase, *sirfsoc_rsc_vbase; | ||
| 45 | |||
| 46 | #define KHZ 1000 | ||
| 47 | #define MHZ (KHZ * KHZ) | ||
| 48 | |||
| 49 | /* | ||
| 50 | * SiRFprimaII clock controller | ||
| 51 | * - 2 oscillators: osc-26MHz, rtc-32.768KHz | ||
| 52 | * - 3 standard configurable plls: pll1, pll2 & pll3 | ||
| 53 | * - 2 exclusive plls: usb phy pll and sata phy pll | ||
| 54 | * - 8 clock domains: cpu/cpudiv, mem/memdiv, sys/io, dsp, graphic, multimedia, | ||
| 55 | * display and sdphy. | ||
| 56 | * Each clock domain can select its own clock source from five clock sources, | ||
| 57 | * X_XIN, X_XINW, PLL1, PLL2 and PLL3. The domain clock is used as the source | ||
| 58 | * clock of the group clock. | ||
| 59 | * - dsp domain: gps, mf | ||
| 60 | * - io domain: dmac, nand, audio, uart, i2c, spi, usp, pwm, pulse | ||
| 61 | * - sys domain: security | ||
| 62 | */ | ||
| 63 | |||
| 64 | struct clk_pll { | ||
| 65 | struct clk_hw hw; | ||
| 66 | unsigned short regofs; /* register offset */ | ||
| 67 | }; | ||
| 68 | |||
| 69 | #define to_pllclk(_hw) container_of(_hw, struct clk_pll, hw) | ||
| 70 | |||
| 71 | struct clk_dmn { | ||
| 72 | struct clk_hw hw; | ||
| 73 | signed char enable_bit; /* enable bit: 0 ~ 63 */ | ||
| 74 | unsigned short regofs; /* register offset */ | ||
| 75 | }; | ||
| 76 | |||
| 77 | #define to_dmnclk(_hw) container_of(_hw, struct clk_dmn, hw) | ||
| 78 | |||
| 79 | struct clk_std { | ||
| 80 | struct clk_hw hw; | ||
| 81 | signed char enable_bit; /* enable bit: 0 ~ 63 */ | ||
| 82 | }; | ||
| 83 | |||
| 84 | #define to_stdclk(_hw) container_of(_hw, struct clk_std, hw) | ||
| 85 | |||
| 86 | static int std_clk_is_enabled(struct clk_hw *hw); | ||
| 87 | static int std_clk_enable(struct clk_hw *hw); | ||
| 88 | static void std_clk_disable(struct clk_hw *hw); | ||
| 89 | |||
| 90 | static inline unsigned long clkc_readl(unsigned reg) | ||
| 91 | { | ||
| 92 | return readl(sirfsoc_clk_vbase + reg); | ||
| 93 | } | ||
| 94 | |||
| 95 | static inline void clkc_writel(u32 val, unsigned reg) | ||
| 96 | { | ||
| 97 | writel(val, sirfsoc_clk_vbase + reg); | ||
| 98 | } | ||
| 99 | |||
| 100 | /* | ||
| 101 | * std pll | ||
| 102 | */ | ||
| 103 | |||
| 104 | static unsigned long pll_clk_recalc_rate(struct clk_hw *hw, | ||
| 105 | unsigned long parent_rate) | ||
| 106 | { | ||
| 107 | unsigned long fin = parent_rate; | ||
| 108 | struct clk_pll *clk = to_pllclk(hw); | ||
| 109 | u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - | ||
| 110 | SIRFSOC_CLKC_PLL1_CFG0; | ||
| 111 | |||
| 112 | if (clkc_readl(regcfg2) & BIT(2)) { | ||
| 113 | /* pll bypass mode */ | ||
| 114 | return fin; | ||
| 115 | } else { | ||
| 116 | /* fout = fin * nf / nr / od */ | ||
| 117 | u32 cfg0 = clkc_readl(clk->regofs); | ||
| 118 | u32 nf = (cfg0 & (BIT(13) - 1)) + 1; | ||
| 119 | u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1; | ||
| 120 | u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1; | ||
| 121 | WARN_ON(fin % MHZ); | ||
| 122 | return fin / MHZ * nf / nr / od * MHZ; | ||
| 123 | } | ||
| 124 | } | ||
| 125 | |||
| 126 | static long pll_clk_round_rate(struct clk_hw *hw, unsigned long rate, | ||
| 127 | unsigned long *parent_rate) | ||
| 128 | { | ||
| 129 | unsigned long fin, nf, nr, od; | ||
| 130 | |||
| 131 | /* | ||
| 132 | * fout = fin * nf / (nr * od); | ||
| 133 | * set od = 1, nr = fin/MHz, so fout = nf * MHz | ||
| 134 | */ | ||
| 135 | rate = rate - rate % MHZ; | ||
| 136 | |||
| 137 | nf = rate / MHZ; | ||
| 138 | if (nf > BIT(13)) | ||
| 139 | nf = BIT(13); | ||
| 140 | if (nf < 1) | ||
| 141 | nf = 1; | ||
| 142 | |||
| 143 | fin = *parent_rate; | ||
| 144 | |||
| 145 | nr = fin / MHZ; | ||
| 146 | if (nr > BIT(6)) | ||
| 147 | nr = BIT(6); | ||
| 148 | od = 1; | ||
| 149 | |||
| 150 | return fin * nf / (nr * od); | ||
| 151 | } | ||
| 152 | |||
| 153 | static int pll_clk_set_rate(struct clk_hw *hw, unsigned long rate, | ||
| 154 | unsigned long parent_rate) | ||
| 155 | { | ||
| 156 | struct clk_pll *clk = to_pllclk(hw); | ||
| 157 | unsigned long fin, nf, nr, od, reg; | ||
| 158 | |||
| 159 | /* | ||
| 160 | * fout = fin * nf / (nr * od); | ||
| 161 | * set od = 1, nr = fin/MHz, so fout = nf * MHz | ||
| 162 | */ | ||
| 163 | |||
| 164 | nf = rate / MHZ; | ||
| 165 | if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1)) | ||
| 166 | return -EINVAL; | ||
| 167 | |||
| 168 | fin = parent_rate; | ||
| 169 | BUG_ON(fin < MHZ); | ||
| 170 | |||
| 171 | nr = fin / MHZ; | ||
| 172 | BUG_ON((fin % MHZ) || nr > BIT(6)); | ||
| 173 | |||
| 174 | od = 1; | ||
| 175 | |||
| 176 | reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19); | ||
| 177 | clkc_writel(reg, clk->regofs); | ||
| 178 | |||
| 179 | reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0; | ||
| 180 | clkc_writel((nf >> 1) - 1, reg); | ||
| 181 | |||
| 182 | reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0; | ||
| 183 | while (!(clkc_readl(reg) & BIT(6))) | ||
| 184 | cpu_relax(); | ||
| 185 | |||
| 186 | return 0; | ||
| 187 | } | ||
| 188 | |||
| 189 | static struct clk_ops std_pll_ops = { | ||
| 190 | .recalc_rate = pll_clk_recalc_rate, | ||
| 191 | .round_rate = pll_clk_round_rate, | ||
| 192 | .set_rate = pll_clk_set_rate, | ||
| 193 | }; | ||
| 194 | |||
| 195 | static const char *pll_clk_parents[] = { | ||
| 196 | "osc", | ||
| 197 | }; | ||
| 198 | |||
| 199 | static struct clk_init_data clk_pll1_init = { | ||
| 200 | .name = "pll1", | ||
| 201 | .ops = &std_pll_ops, | ||
| 202 | .parent_names = pll_clk_parents, | ||
| 203 | .num_parents = ARRAY_SIZE(pll_clk_parents), | ||
| 204 | }; | ||
| 205 | |||
| 206 | static struct clk_init_data clk_pll2_init = { | ||
| 207 | .name = "pll2", | ||
| 208 | .ops = &std_pll_ops, | ||
| 209 | .parent_names = pll_clk_parents, | ||
| 210 | .num_parents = ARRAY_SIZE(pll_clk_parents), | ||
| 211 | }; | ||
| 212 | |||
| 213 | static struct clk_init_data clk_pll3_init = { | ||
| 214 | .name = "pll3", | ||
| 215 | .ops = &std_pll_ops, | ||
| 216 | .parent_names = pll_clk_parents, | ||
| 217 | .num_parents = ARRAY_SIZE(pll_clk_parents), | ||
| 218 | }; | ||
| 219 | |||
| 220 | static struct clk_pll clk_pll1 = { | ||
| 221 | .regofs = SIRFSOC_CLKC_PLL1_CFG0, | ||
| 222 | .hw = { | ||
| 223 | .init = &clk_pll1_init, | ||
| 224 | }, | ||
| 225 | }; | ||
| 226 | |||
| 227 | static struct clk_pll clk_pll2 = { | ||
| 228 | .regofs = SIRFSOC_CLKC_PLL2_CFG0, | ||
| 229 | .hw = { | ||
| 230 | .init = &clk_pll2_init, | ||
| 231 | }, | ||
| 232 | }; | ||
| 233 | |||
| 234 | static struct clk_pll clk_pll3 = { | ||
| 235 | .regofs = SIRFSOC_CLKC_PLL3_CFG0, | ||
| 236 | .hw = { | ||
| 237 | .init = &clk_pll3_init, | ||
| 238 | }, | ||
| 239 | }; | ||
| 240 | |||
| 241 | /* | ||
| 242 | * usb uses specified pll | ||
| 243 | */ | ||
| 244 | |||
| 245 | static int usb_pll_clk_enable(struct clk_hw *hw) | ||
| 246 | { | ||
| 247 | u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); | ||
| 248 | reg &= ~(SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS); | ||
| 249 | writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); | ||
| 250 | while (!(readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL) & | ||
| 251 | SIRFSOC_USBPHY_PLL_LOCK)) | ||
| 252 | cpu_relax(); | ||
| 253 | |||
| 254 | return 0; | ||
| 255 | } | ||
| 256 | |||
| 257 | static void usb_pll_clk_disable(struct clk_hw *clk) | ||
| 258 | { | ||
| 259 | u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); | ||
| 260 | reg |= (SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS); | ||
| 261 | writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); | ||
| 262 | } | ||
| 263 | |||
| 264 | static unsigned long usb_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) | ||
| 265 | { | ||
| 266 | u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); | ||
| 267 | return (reg & SIRFSOC_USBPHY_PLL_BYPASS) ? parent_rate : 48*MHZ; | ||
| 268 | } | ||
| 269 | |||
| 270 | static struct clk_ops usb_pll_ops = { | ||
| 271 | .enable = usb_pll_clk_enable, | ||
| 272 | .disable = usb_pll_clk_disable, | ||
| 273 | .recalc_rate = usb_pll_clk_recalc_rate, | ||
| 274 | }; | ||
| 275 | |||
| 276 | static struct clk_init_data clk_usb_pll_init = { | ||
| 277 | .name = "usb_pll", | ||
| 278 | .ops = &usb_pll_ops, | ||
| 279 | .parent_names = pll_clk_parents, | ||
| 280 | .num_parents = ARRAY_SIZE(pll_clk_parents), | ||
| 281 | }; | ||
| 282 | |||
| 283 | static struct clk_hw usb_pll_clk_hw = { | ||
| 284 | .init = &clk_usb_pll_init, | ||
| 285 | }; | ||
| 286 | |||
| 287 | /* | ||
| 288 | * clock domains - cpu, mem, sys/io, dsp, gfx | ||
| 289 | */ | ||
| 290 | |||
| 291 | static const char *dmn_clk_parents[] = { | ||
| 292 | "rtc", | ||
| 293 | "osc", | ||
| 294 | "pll1", | ||
| 295 | "pll2", | ||
| 296 | "pll3", | ||
| 297 | }; | ||
| 298 | |||
| 299 | static u8 dmn_clk_get_parent(struct clk_hw *hw) | ||
| 300 | { | ||
| 301 | struct clk_dmn *clk = to_dmnclk(hw); | ||
| 302 | u32 cfg = clkc_readl(clk->regofs); | ||
| 303 | |||
| 304 | /* parent of io domain can only be pll3 */ | ||
| 305 | if (strcmp(hw->init->name, "io") == 0) | ||
| 306 | return 4; | ||
| 307 | |||
| 308 | WARN_ON((cfg & (BIT(3) - 1)) > 4); | ||
| 309 | |||
| 310 | return cfg & (BIT(3) - 1); | ||
| 311 | } | ||
| 312 | |||
| 313 | static int dmn_clk_set_parent(struct clk_hw *hw, u8 parent) | ||
| 314 | { | ||
| 315 | struct clk_dmn *clk = to_dmnclk(hw); | ||
| 316 | u32 cfg = clkc_readl(clk->regofs); | ||
| 317 | |||
| 318 | /* parent of io domain can only be pll3 */ | ||
| 319 | if (strcmp(hw->init->name, "io") == 0) | ||
| 320 | return -EINVAL; | ||
| 321 | |||
| 322 | cfg &= ~(BIT(3) - 1); | ||
| 323 | clkc_writel(cfg | parent, clk->regofs); | ||
| 324 | /* BIT(3) - switching status: 1 - busy, 0 - done */ | ||
| 325 | while (clkc_readl(clk->regofs) & BIT(3)) | ||
| 326 | cpu_relax(); | ||
| 327 | |||
| 328 | return 0; | ||
| 329 | } | ||
| 330 | |||
| 331 | static unsigned long dmn_clk_recalc_rate(struct clk_hw *hw, | ||
| 332 | unsigned long parent_rate) | ||
| 333 | |||
| 334 | { | ||
| 335 | unsigned long fin = parent_rate; | ||
| 336 | struct clk_dmn *clk = to_dmnclk(hw); | ||
| 337 | |||
| 338 | u32 cfg = clkc_readl(clk->regofs); | ||
| 339 | |||
| 340 | if (cfg & BIT(24)) { | ||
| 341 | /* fcd bypass mode */ | ||
| 342 | return fin; | ||
| 343 | } else { | ||
| 344 | /* | ||
| 345 | * wait count: bit[19:16], hold count: bit[23:20] | ||
| 346 | */ | ||
| 347 | u32 wait = (cfg >> 16) & (BIT(4) - 1); | ||
| 348 | u32 hold = (cfg >> 20) & (BIT(4) - 1); | ||
| 349 | |||
| 350 | return fin / (wait + hold + 2); | ||
| 351 | } | ||
| 352 | } | ||
| 353 | |||
| 354 | static long dmn_clk_round_rate(struct clk_hw *hw, unsigned long rate, | ||
| 355 | unsigned long *parent_rate) | ||
| 356 | { | ||
| 357 | unsigned long fin; | ||
| 358 | unsigned ratio, wait, hold; | ||
| 359 | unsigned bits = (strcmp(hw->init->name, "mem") == 0) ? 3 : 4; | ||
| 360 | |||
| 361 | fin = *parent_rate; | ||
| 362 | ratio = fin / rate; | ||
| 363 | |||
| 364 | if (ratio < 2) | ||
| 365 | ratio = 2; | ||
| 366 | if (ratio > BIT(bits + 1)) | ||
| 367 | ratio = BIT(bits + 1); | ||
| 368 | |||
| 369 | wait = (ratio >> 1) - 1; | ||
| 370 | hold = ratio - wait - 2; | ||
| 371 | |||
| 372 | return fin / (wait + hold + 2); | ||
| 373 | } | ||
| 374 | |||
| 375 | static int dmn_clk_set_rate(struct clk_hw *hw, unsigned long rate, | ||
| 376 | unsigned long parent_rate) | ||
| 377 | { | ||
| 378 | struct clk_dmn *clk = to_dmnclk(hw); | ||
| 379 | unsigned long fin; | ||
| 380 | unsigned ratio, wait, hold, reg; | ||
| 381 | unsigned bits = (strcmp(hw->init->name, "mem") == 0) ? 3 : 4; | ||
| 382 | |||
| 383 | fin = parent_rate; | ||
| 384 | ratio = fin / rate; | ||
| 385 | |||
| 386 | if (unlikely(ratio < 2 || ratio > BIT(bits + 1))) | ||
| 387 | return -EINVAL; | ||
| 388 | |||
| 389 | WARN_ON(fin % rate); | ||
| 390 | |||
| 391 | wait = (ratio >> 1) - 1; | ||
| 392 | hold = ratio - wait - 2; | ||
| 393 | |||
| 394 | reg = clkc_readl(clk->regofs); | ||
| 395 | reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20)); | ||
| 396 | reg |= (wait << 16) | (hold << 20) | BIT(25); | ||
| 397 | clkc_writel(reg, clk->regofs); | ||
| 398 | |||
| 399 | /* waiting FCD been effective */ | ||
| 400 | while (clkc_readl(clk->regofs) & BIT(25)) | ||
| 401 | cpu_relax(); | ||
| 402 | |||
| 403 | return 0; | ||
| 404 | } | ||
| 405 | |||
| 406 | static struct clk_ops msi_ops = { | ||
| 407 | .set_rate = dmn_clk_set_rate, | ||
| 408 | .round_rate = dmn_clk_round_rate, | ||
| 409 | .recalc_rate = dmn_clk_recalc_rate, | ||
| 410 | .set_parent = dmn_clk_set_parent, | ||
| 411 | .get_parent = dmn_clk_get_parent, | ||
| 412 | }; | ||
| 413 | |||
| 414 | static struct clk_init_data clk_mem_init = { | ||
| 415 | .name = "mem", | ||
| 416 | .ops = &msi_ops, | ||
| 417 | .parent_names = dmn_clk_parents, | ||
| 418 | .num_parents = ARRAY_SIZE(dmn_clk_parents), | ||
| 419 | }; | ||
| 420 | |||
| 421 | static struct clk_dmn clk_mem = { | ||
| 422 | .regofs = SIRFSOC_CLKC_MEM_CFG, | ||
| 423 | .hw = { | ||
| 424 | .init = &clk_mem_init, | ||
| 425 | }, | ||
| 426 | }; | ||
| 427 | |||
| 428 | static struct clk_init_data clk_sys_init = { | ||
| 429 | .name = "sys", | ||
| 430 | .ops = &msi_ops, | ||
| 431 | .parent_names = dmn_clk_parents, | ||
| 432 | .num_parents = ARRAY_SIZE(dmn_clk_parents), | ||
| 433 | .flags = CLK_SET_RATE_GATE, | ||
| 434 | }; | ||
| 435 | |||
| 436 | static struct clk_dmn clk_sys = { | ||
| 437 | .regofs = SIRFSOC_CLKC_SYS_CFG, | ||
| 438 | .hw = { | ||
| 439 | .init = &clk_sys_init, | ||
| 440 | }, | ||
| 441 | }; | ||
| 442 | |||
| 443 | static struct clk_init_data clk_io_init = { | ||
| 444 | .name = "io", | ||
| 445 | .ops = &msi_ops, | ||
| 446 | .parent_names = dmn_clk_parents, | ||
| 447 | .num_parents = ARRAY_SIZE(dmn_clk_parents), | ||
| 448 | }; | ||
| 449 | |||
| 450 | static struct clk_dmn clk_io = { | ||
| 451 | .regofs = SIRFSOC_CLKC_IO_CFG, | ||
| 452 | .hw = { | ||
| 453 | .init = &clk_io_init, | ||
| 454 | }, | ||
| 455 | }; | ||
| 456 | |||
| 457 | static struct clk_ops cpu_ops = { | ||
| 458 | .set_parent = dmn_clk_set_parent, | ||
| 459 | .get_parent = dmn_clk_get_parent, | ||
| 460 | }; | ||
| 461 | |||
| 462 | static struct clk_init_data clk_cpu_init = { | ||
| 463 | .name = "cpu", | ||
| 464 | .ops = &cpu_ops, | ||
| 465 | .parent_names = dmn_clk_parents, | ||
| 466 | .num_parents = ARRAY_SIZE(dmn_clk_parents), | ||
| 467 | .flags = CLK_SET_RATE_PARENT, | ||
| 468 | }; | ||
| 469 | |||
| 470 | static struct clk_dmn clk_cpu = { | ||
| 471 | .regofs = SIRFSOC_CLKC_CPU_CFG, | ||
| 472 | .hw = { | ||
| 473 | .init = &clk_cpu_init, | ||
| 474 | }, | ||
| 475 | }; | ||
| 476 | |||
| 477 | static struct clk_ops dmn_ops = { | ||
| 478 | .is_enabled = std_clk_is_enabled, | ||
| 479 | .enable = std_clk_enable, | ||
| 480 | .disable = std_clk_disable, | ||
| 481 | .set_rate = dmn_clk_set_rate, | ||
| 482 | .round_rate = dmn_clk_round_rate, | ||
| 483 | .recalc_rate = dmn_clk_recalc_rate, | ||
| 484 | .set_parent = dmn_clk_set_parent, | ||
| 485 | .get_parent = dmn_clk_get_parent, | ||
| 486 | }; | ||
| 487 | |||
| 488 | /* dsp, gfx, mm, lcd and vpp domain */ | ||
| 489 | |||
| 490 | static struct clk_init_data clk_dsp_init = { | ||
| 491 | .name = "dsp", | ||
| 492 | .ops = &dmn_ops, | ||
| 493 | .parent_names = dmn_clk_parents, | ||
| 494 | .num_parents = ARRAY_SIZE(dmn_clk_parents), | ||
| 495 | }; | ||
| 496 | |||
| 497 | static struct clk_dmn clk_dsp = { | ||
| 498 | .regofs = SIRFSOC_CLKC_DSP_CFG, | ||
| 499 | .enable_bit = 0, | ||
| 500 | .hw = { | ||
| 501 | .init = &clk_dsp_init, | ||
| 502 | }, | ||
| 503 | }; | ||
| 504 | |||
| 505 | static struct clk_init_data clk_gfx_init = { | ||
| 506 | .name = "gfx", | ||
| 507 | .ops = &dmn_ops, | ||
| 508 | .parent_names = dmn_clk_parents, | ||
| 509 | .num_parents = ARRAY_SIZE(dmn_clk_parents), | ||
| 510 | }; | ||
| 511 | |||
| 512 | static struct clk_dmn clk_gfx = { | ||
| 513 | .regofs = SIRFSOC_CLKC_GFX_CFG, | ||
| 514 | .enable_bit = 8, | ||
| 515 | .hw = { | ||
| 516 | .init = &clk_gfx_init, | ||
| 517 | }, | ||
| 518 | }; | ||
| 519 | |||
| 520 | static struct clk_init_data clk_mm_init = { | ||
| 521 | .name = "mm", | ||
| 522 | .ops = &dmn_ops, | ||
| 523 | .parent_names = dmn_clk_parents, | ||
| 524 | .num_parents = ARRAY_SIZE(dmn_clk_parents), | ||
| 525 | }; | ||
| 526 | |||
| 527 | static struct clk_dmn clk_mm = { | ||
| 528 | .regofs = SIRFSOC_CLKC_MM_CFG, | ||
| 529 | .enable_bit = 9, | ||
| 530 | .hw = { | ||
| 531 | .init = &clk_mm_init, | ||
| 532 | }, | ||
| 533 | }; | ||
| 534 | |||
| 535 | static struct clk_init_data clk_lcd_init = { | ||
| 536 | .name = "lcd", | ||
| 537 | .ops = &dmn_ops, | ||
| 538 | .parent_names = dmn_clk_parents, | ||
| 539 | .num_parents = ARRAY_SIZE(dmn_clk_parents), | ||
| 540 | }; | ||
| 541 | |||
| 542 | static struct clk_dmn clk_lcd = { | ||
| 543 | .regofs = SIRFSOC_CLKC_LCD_CFG, | ||
| 544 | .enable_bit = 10, | ||
| 545 | .hw = { | ||
| 546 | .init = &clk_lcd_init, | ||
| 547 | }, | ||
| 548 | }; | ||
| 549 | |||
| 550 | static struct clk_init_data clk_vpp_init = { | ||
| 551 | .name = "vpp", | ||
| 552 | .ops = &dmn_ops, | ||
| 553 | .parent_names = dmn_clk_parents, | ||
| 554 | .num_parents = ARRAY_SIZE(dmn_clk_parents), | ||
| 555 | }; | ||
| 556 | |||
| 557 | static struct clk_dmn clk_vpp = { | ||
| 558 | .regofs = SIRFSOC_CLKC_LCD_CFG, | ||
| 559 | .enable_bit = 11, | ||
| 560 | .hw = { | ||
| 561 | .init = &clk_vpp_init, | ||
| 562 | }, | ||
| 563 | }; | ||
| 564 | |||
| 565 | static struct clk_init_data clk_mmc01_init = { | ||
| 566 | .name = "mmc01", | ||
| 567 | .ops = &dmn_ops, | ||
| 568 | .parent_names = dmn_clk_parents, | ||
| 569 | .num_parents = ARRAY_SIZE(dmn_clk_parents), | ||
| 570 | }; | ||
| 571 | |||
| 572 | static struct clk_dmn clk_mmc01 = { | ||
| 573 | .regofs = SIRFSOC_CLKC_MMC_CFG, | ||
| 574 | .enable_bit = 59, | ||
| 575 | .hw = { | ||
| 576 | .init = &clk_mmc01_init, | ||
| 577 | }, | ||
| 578 | }; | ||
| 579 | |||
| 580 | static struct clk_init_data clk_mmc23_init = { | ||
| 581 | .name = "mmc23", | ||
| 582 | .ops = &dmn_ops, | ||
| 583 | .parent_names = dmn_clk_parents, | ||
| 584 | .num_parents = ARRAY_SIZE(dmn_clk_parents), | ||
| 585 | }; | ||
| 586 | |||
| 587 | static struct clk_dmn clk_mmc23 = { | ||
| 588 | .regofs = SIRFSOC_CLKC_MMC_CFG, | ||
| 589 | .enable_bit = 60, | ||
| 590 | .hw = { | ||
| 591 | .init = &clk_mmc23_init, | ||
| 592 | }, | ||
| 593 | }; | ||
| 594 | |||
| 595 | static struct clk_init_data clk_mmc45_init = { | ||
| 596 | .name = "mmc45", | ||
| 597 | .ops = &dmn_ops, | ||
| 598 | .parent_names = dmn_clk_parents, | ||
| 599 | .num_parents = ARRAY_SIZE(dmn_clk_parents), | ||
| 600 | }; | ||
| 601 | |||
| 602 | static struct clk_dmn clk_mmc45 = { | ||
| 603 | .regofs = SIRFSOC_CLKC_MMC_CFG, | ||
| 604 | .enable_bit = 61, | ||
| 605 | .hw = { | ||
| 606 | .init = &clk_mmc45_init, | ||
| 607 | }, | ||
| 608 | }; | ||
| 609 | |||
| 610 | /* | ||
| 611 | * peripheral controllers in io domain | ||
| 612 | */ | ||
| 613 | |||
| 614 | static int std_clk_is_enabled(struct clk_hw *hw) | ||
| 615 | { | ||
| 616 | u32 reg; | ||
| 617 | int bit; | ||
| 618 | struct clk_std *clk = to_stdclk(hw); | ||
| 619 | |||
| 620 | bit = clk->enable_bit % 32; | ||
| 621 | reg = clk->enable_bit / 32; | ||
| 622 | reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg); | ||
| 623 | |||
| 624 | return !!(clkc_readl(reg) & BIT(bit)); | ||
| 625 | } | ||
| 626 | |||
| 627 | static int std_clk_enable(struct clk_hw *hw) | ||
| 628 | { | ||
| 629 | u32 val, reg; | ||
| 630 | int bit; | ||
| 631 | struct clk_std *clk = to_stdclk(hw); | ||
| 632 | |||
| 633 | BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63); | ||
| 634 | |||
| 635 | bit = clk->enable_bit % 32; | ||
| 636 | reg = clk->enable_bit / 32; | ||
| 637 | reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg); | ||
| 638 | |||
| 639 | val = clkc_readl(reg) | BIT(bit); | ||
| 640 | clkc_writel(val, reg); | ||
| 641 | return 0; | ||
| 642 | } | ||
| 643 | |||
| 644 | static void std_clk_disable(struct clk_hw *hw) | ||
| 645 | { | ||
| 646 | u32 val, reg; | ||
| 647 | int bit; | ||
| 648 | struct clk_std *clk = to_stdclk(hw); | ||
| 649 | |||
| 650 | BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63); | ||
| 651 | |||
| 652 | bit = clk->enable_bit % 32; | ||
| 653 | reg = clk->enable_bit / 32; | ||
| 654 | reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg); | ||
| 655 | |||
| 656 | val = clkc_readl(reg) & ~BIT(bit); | ||
| 657 | clkc_writel(val, reg); | ||
| 658 | } | ||
| 659 | |||
| 660 | static const char *std_clk_io_parents[] = { | ||
| 661 | "io", | ||
| 662 | }; | ||
| 663 | |||
| 664 | static struct clk_ops ios_ops = { | ||
| 665 | .is_enabled = std_clk_is_enabled, | ||
| 666 | .enable = std_clk_enable, | ||
| 667 | .disable = std_clk_disable, | ||
| 668 | }; | ||
| 669 | |||
| 670 | static struct clk_init_data clk_dmac0_init = { | ||
| 671 | .name = "dmac0", | ||
| 672 | .ops = &ios_ops, | ||
| 673 | .parent_names = std_clk_io_parents, | ||
| 674 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | ||
| 675 | }; | ||
| 676 | |||
| 677 | static struct clk_std clk_dmac0 = { | ||
| 678 | .enable_bit = 32, | ||
| 679 | .hw = { | ||
| 680 | .init = &clk_dmac0_init, | ||
| 681 | }, | ||
| 682 | }; | ||
| 683 | |||
| 684 | static struct clk_init_data clk_dmac1_init = { | ||
| 685 | .name = "dmac1", | ||
| 686 | .ops = &ios_ops, | ||
| 687 | .parent_names = std_clk_io_parents, | ||
| 688 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | ||
| 689 | }; | ||
| 690 | |||
| 691 | static struct clk_std clk_dmac1 = { | ||
| 692 | .enable_bit = 33, | ||
| 693 | .hw = { | ||
| 694 | .init = &clk_dmac1_init, | ||
| 695 | }, | ||
| 696 | }; | ||
| 697 | |||
| 698 | static struct clk_init_data clk_nand_init = { | ||
| 699 | .name = "nand", | ||
| 700 | .ops = &ios_ops, | ||
| 701 | .parent_names = std_clk_io_parents, | ||
| 702 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | ||
| 703 | }; | ||
| 704 | |||
| 705 | static struct clk_std clk_nand = { | ||
| 706 | .enable_bit = 34, | ||
| 707 | .hw = { | ||
| 708 | .init = &clk_nand_init, | ||
| 709 | }, | ||
| 710 | }; | ||
| 711 | |||
| 712 | static struct clk_init_data clk_audio_init = { | ||
| 713 | .name = "audio", | ||
| 714 | .ops = &ios_ops, | ||
| 715 | .parent_names = std_clk_io_parents, | ||
| 716 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | ||
| 717 | }; | ||
| 718 | |||
| 719 | static struct clk_std clk_audio = { | ||
| 720 | .enable_bit = 35, | ||
| 721 | .hw = { | ||
| 722 | .init = &clk_audio_init, | ||
| 723 | }, | ||
| 724 | }; | ||
| 725 | |||
| 726 | static struct clk_init_data clk_uart0_init = { | ||
| 727 | .name = "uart0", | ||
| 728 | .ops = &ios_ops, | ||
| 729 | .parent_names = std_clk_io_parents, | ||
| 730 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | ||
| 731 | }; | ||
| 732 | |||
| 733 | static struct clk_std clk_uart0 = { | ||
| 734 | .enable_bit = 36, | ||
| 735 | .hw = { | ||
| 736 | .init = &clk_uart0_init, | ||
| 737 | }, | ||
| 738 | }; | ||
| 739 | |||
| 740 | static struct clk_init_data clk_uart1_init = { | ||
| 741 | .name = "uart1", | ||
| 742 | .ops = &ios_ops, | ||
| 743 | .parent_names = std_clk_io_parents, | ||
| 744 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | ||
| 745 | }; | ||
| 746 | |||
| 747 | static struct clk_std clk_uart1 = { | ||
| 748 | .enable_bit = 37, | ||
| 749 | .hw = { | ||
| 750 | .init = &clk_uart1_init, | ||
| 751 | }, | ||
| 752 | }; | ||
| 753 | |||
| 754 | static struct clk_init_data clk_uart2_init = { | ||
| 755 | .name = "uart2", | ||
| 756 | .ops = &ios_ops, | ||
| 757 | .parent_names = std_clk_io_parents, | ||
| 758 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | ||
| 759 | }; | ||
| 760 | |||
| 761 | static struct clk_std clk_uart2 = { | ||
| 762 | .enable_bit = 38, | ||
| 763 | .hw = { | ||
| 764 | .init = &clk_uart2_init, | ||
| 765 | }, | ||
| 766 | }; | ||
| 767 | |||
| 768 | static struct clk_init_data clk_usp0_init = { | ||
| 769 | .name = "usp0", | ||
| 770 | .ops = &ios_ops, | ||
| 771 | .parent_names = std_clk_io_parents, | ||
| 772 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | ||
| 773 | }; | ||
| 774 | |||
| 775 | static struct clk_std clk_usp0 = { | ||
| 776 | .enable_bit = 39, | ||
| 777 | .hw = { | ||
| 778 | .init = &clk_usp0_init, | ||
| 779 | }, | ||
| 780 | }; | ||
| 781 | |||
| 782 | static struct clk_init_data clk_usp1_init = { | ||
| 783 | .name = "usp1", | ||
| 784 | .ops = &ios_ops, | ||
| 785 | .parent_names = std_clk_io_parents, | ||
| 786 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | ||
| 787 | }; | ||
| 788 | |||
| 789 | static struct clk_std clk_usp1 = { | ||
| 790 | .enable_bit = 40, | ||
| 791 | .hw = { | ||
| 792 | .init = &clk_usp1_init, | ||
| 793 | }, | ||
| 794 | }; | ||
| 795 | |||
| 796 | static struct clk_init_data clk_usp2_init = { | ||
| 797 | .name = "usp2", | ||
| 798 | .ops = &ios_ops, | ||
| 799 | .parent_names = std_clk_io_parents, | ||
| 800 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | ||
| 801 | }; | ||
| 802 | |||
| 803 | static struct clk_std clk_usp2 = { | ||
| 804 | .enable_bit = 41, | ||
| 805 | .hw = { | ||
| 806 | .init = &clk_usp2_init, | ||
| 807 | }, | ||
| 808 | }; | ||
| 809 | |||
| 810 | static struct clk_init_data clk_vip_init = { | ||
| 811 | .name = "vip", | ||
| 812 | .ops = &ios_ops, | ||
| 813 | .parent_names = std_clk_io_parents, | ||
| 814 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | ||
| 815 | }; | ||
| 816 | |||
| 817 | static struct clk_std clk_vip = { | ||
| 818 | .enable_bit = 42, | ||
| 819 | .hw = { | ||
| 820 | .init = &clk_vip_init, | ||
| 821 | }, | ||
| 822 | }; | ||
| 823 | |||
| 824 | static struct clk_init_data clk_spi0_init = { | ||
| 825 | .name = "spi0", | ||
| 826 | .ops = &ios_ops, | ||
| 827 | .parent_names = std_clk_io_parents, | ||
| 828 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | ||
| 829 | }; | ||
| 830 | |||
| 831 | static struct clk_std clk_spi0 = { | ||
| 832 | .enable_bit = 43, | ||
| 833 | .hw = { | ||
| 834 | .init = &clk_spi0_init, | ||
| 835 | }, | ||
| 836 | }; | ||
| 837 | |||
| 838 | static struct clk_init_data clk_spi1_init = { | ||
| 839 | .name = "spi1", | ||
| 840 | .ops = &ios_ops, | ||
| 841 | .parent_names = std_clk_io_parents, | ||
| 842 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | ||
| 843 | }; | ||
| 844 | |||
| 845 | static struct clk_std clk_spi1 = { | ||
| 846 | .enable_bit = 44, | ||
| 847 | .hw = { | ||
| 848 | .init = &clk_spi1_init, | ||
| 849 | }, | ||
| 850 | }; | ||
| 851 | |||
| 852 | static struct clk_init_data clk_tsc_init = { | ||
| 853 | .name = "tsc", | ||
| 854 | .ops = &ios_ops, | ||
| 855 | .parent_names = std_clk_io_parents, | ||
| 856 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | ||
| 857 | }; | ||
| 858 | |||
| 859 | static struct clk_std clk_tsc = { | ||
| 860 | .enable_bit = 45, | ||
| 861 | .hw = { | ||
| 862 | .init = &clk_tsc_init, | ||
| 863 | }, | ||
| 864 | }; | ||
| 865 | |||
| 866 | static struct clk_init_data clk_i2c0_init = { | ||
| 867 | .name = "i2c0", | ||
| 868 | .ops = &ios_ops, | ||
| 869 | .parent_names = std_clk_io_parents, | ||
| 870 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | ||
| 871 | }; | ||
| 872 | |||
| 873 | static struct clk_std clk_i2c0 = { | ||
| 874 | .enable_bit = 46, | ||
| 875 | .hw = { | ||
| 876 | .init = &clk_i2c0_init, | ||
| 877 | }, | ||
| 878 | }; | ||
| 879 | |||
| 880 | static struct clk_init_data clk_i2c1_init = { | ||
| 881 | .name = "i2c1", | ||
| 882 | .ops = &ios_ops, | ||
| 883 | .parent_names = std_clk_io_parents, | ||
| 884 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | ||
| 885 | }; | ||
| 886 | |||
| 887 | static struct clk_std clk_i2c1 = { | ||
| 888 | .enable_bit = 47, | ||
| 889 | .hw = { | ||
| 890 | .init = &clk_i2c1_init, | ||
| 891 | }, | ||
| 892 | }; | ||
| 893 | |||
| 894 | static struct clk_init_data clk_pwmc_init = { | ||
| 895 | .name = "pwmc", | ||
| 896 | .ops = &ios_ops, | ||
| 897 | .parent_names = std_clk_io_parents, | ||
| 898 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | ||
| 899 | }; | ||
| 900 | |||
| 901 | static struct clk_std clk_pwmc = { | ||
| 902 | .enable_bit = 48, | ||
| 903 | .hw = { | ||
| 904 | .init = &clk_pwmc_init, | ||
| 905 | }, | ||
| 906 | }; | ||
| 907 | |||
| 908 | static struct clk_init_data clk_efuse_init = { | ||
| 909 | .name = "efuse", | ||
| 910 | .ops = &ios_ops, | ||
| 911 | .parent_names = std_clk_io_parents, | ||
| 912 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | ||
| 913 | }; | ||
| 914 | |||
| 915 | static struct clk_std clk_efuse = { | ||
| 916 | .enable_bit = 49, | ||
| 917 | .hw = { | ||
| 918 | .init = &clk_efuse_init, | ||
| 919 | }, | ||
| 920 | }; | ||
| 921 | |||
| 922 | static struct clk_init_data clk_pulse_init = { | ||
| 923 | .name = "pulse", | ||
| 924 | .ops = &ios_ops, | ||
| 925 | .parent_names = std_clk_io_parents, | ||
| 926 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | ||
| 927 | }; | ||
| 928 | |||
| 929 | static struct clk_std clk_pulse = { | ||
| 930 | .enable_bit = 50, | ||
| 931 | .hw = { | ||
| 932 | .init = &clk_pulse_init, | ||
| 933 | }, | ||
| 934 | }; | ||
| 935 | |||
| 936 | static const char *std_clk_dsp_parents[] = { | ||
| 937 | "dsp", | ||
| 938 | }; | ||
| 939 | |||
| 940 | static struct clk_init_data clk_gps_init = { | ||
| 941 | .name = "gps", | ||
| 942 | .ops = &ios_ops, | ||
| 943 | .parent_names = std_clk_dsp_parents, | ||
| 944 | .num_parents = ARRAY_SIZE(std_clk_dsp_parents), | ||
| 945 | }; | ||
| 946 | |||
| 947 | static struct clk_std clk_gps = { | ||
| 948 | .enable_bit = 1, | ||
| 949 | .hw = { | ||
| 950 | .init = &clk_gps_init, | ||
| 951 | }, | ||
| 952 | }; | ||
| 953 | |||
| 954 | static struct clk_init_data clk_mf_init = { | ||
| 955 | .name = "mf", | ||
| 956 | .ops = &ios_ops, | ||
| 957 | .parent_names = std_clk_io_parents, | ||
| 958 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | ||
| 959 | }; | ||
| 960 | |||
| 961 | static struct clk_std clk_mf = { | ||
| 962 | .enable_bit = 2, | ||
| 963 | .hw = { | ||
| 964 | .init = &clk_mf_init, | ||
| 965 | }, | ||
| 966 | }; | ||
| 967 | |||
| 968 | static const char *std_clk_sys_parents[] = { | ||
| 969 | "sys", | ||
| 970 | }; | ||
| 971 | |||
| 972 | static struct clk_init_data clk_security_init = { | ||
| 973 | .name = "mf", | ||
| 974 | .ops = &ios_ops, | ||
| 975 | .parent_names = std_clk_sys_parents, | ||
| 976 | .num_parents = ARRAY_SIZE(std_clk_sys_parents), | ||
| 977 | }; | ||
| 978 | |||
| 979 | static struct clk_std clk_security = { | ||
| 980 | .enable_bit = 19, | ||
| 981 | .hw = { | ||
| 982 | .init = &clk_security_init, | ||
| 983 | }, | ||
| 984 | }; | ||
| 985 | |||
| 986 | static const char *std_clk_usb_parents[] = { | ||
| 987 | "usb_pll", | ||
| 988 | }; | ||
| 989 | |||
| 990 | static struct clk_init_data clk_usb0_init = { | ||
| 991 | .name = "usb0", | ||
| 992 | .ops = &ios_ops, | ||
| 993 | .parent_names = std_clk_usb_parents, | ||
| 994 | .num_parents = ARRAY_SIZE(std_clk_usb_parents), | ||
| 995 | }; | ||
| 996 | |||
| 997 | static struct clk_std clk_usb0 = { | ||
| 998 | .enable_bit = 16, | ||
| 999 | .hw = { | ||
| 1000 | .init = &clk_usb0_init, | ||
| 1001 | }, | ||
| 1002 | }; | ||
| 1003 | |||
| 1004 | static struct clk_init_data clk_usb1_init = { | ||
| 1005 | .name = "usb1", | ||
| 1006 | .ops = &ios_ops, | ||
| 1007 | .parent_names = std_clk_usb_parents, | ||
| 1008 | .num_parents = ARRAY_SIZE(std_clk_usb_parents), | ||
| 1009 | }; | ||
| 1010 | |||
| 1011 | static struct clk_std clk_usb1 = { | ||
| 1012 | .enable_bit = 17, | ||
| 1013 | .hw = { | ||
| 1014 | .init = &clk_usb1_init, | ||
| 1015 | }, | ||
| 1016 | }; | ||
| 1017 | |||
| 1018 | static struct of_device_id clkc_ids[] = { | ||
| 1019 | { .compatible = "sirf,prima2-clkc" }, | ||
| 1020 | {}, | ||
| 1021 | }; | ||
| 1022 | |||
| 1023 | static struct of_device_id rsc_ids[] = { | ||
| 1024 | { .compatible = "sirf,prima2-rsc" }, | ||
| 1025 | {}, | ||
| 1026 | }; | ||
| 1027 | |||
| 1028 | void __init sirfsoc_of_clk_init(void) | ||
| 1029 | { | ||
| 1030 | struct clk *clk; | ||
| 1031 | struct device_node *np; | ||
| 1032 | |||
| 1033 | np = of_find_matching_node(NULL, clkc_ids); | ||
| 1034 | if (!np) | ||
| 1035 | panic("unable to find compatible clkc node in dtb\n"); | ||
| 1036 | |||
| 1037 | sirfsoc_clk_vbase = of_iomap(np, 0); | ||
| 1038 | if (!sirfsoc_clk_vbase) | ||
| 1039 | panic("unable to map clkc registers\n"); | ||
| 1040 | |||
| 1041 | of_node_put(np); | ||
| 1042 | |||
| 1043 | np = of_find_matching_node(NULL, rsc_ids); | ||
| 1044 | if (!np) | ||
| 1045 | panic("unable to find compatible rsc node in dtb\n"); | ||
| 1046 | |||
| 1047 | sirfsoc_rsc_vbase = of_iomap(np, 0); | ||
| 1048 | if (!sirfsoc_rsc_vbase) | ||
| 1049 | panic("unable to map rsc registers\n"); | ||
| 1050 | |||
| 1051 | of_node_put(np); | ||
| 1052 | |||
| 1053 | |||
| 1054 | /* These are always available (RTC and 26MHz OSC)*/ | ||
| 1055 | clk = clk_register_fixed_rate(NULL, "rtc", NULL, | ||
| 1056 | CLK_IS_ROOT, 32768); | ||
| 1057 | BUG_ON(!clk); | ||
| 1058 | clk = clk_register_fixed_rate(NULL, "osc", NULL, | ||
| 1059 | CLK_IS_ROOT, 26000000); | ||
| 1060 | BUG_ON(!clk); | ||
| 1061 | |||
| 1062 | clk = clk_register(NULL, &clk_pll1.hw); | ||
| 1063 | BUG_ON(!clk); | ||
| 1064 | clk = clk_register(NULL, &clk_pll2.hw); | ||
| 1065 | BUG_ON(!clk); | ||
| 1066 | clk = clk_register(NULL, &clk_pll3.hw); | ||
| 1067 | BUG_ON(!clk); | ||
| 1068 | clk = clk_register(NULL, &clk_mem.hw); | ||
| 1069 | BUG_ON(!clk); | ||
| 1070 | clk = clk_register(NULL, &clk_sys.hw); | ||
| 1071 | BUG_ON(!clk); | ||
| 1072 | clk = clk_register(NULL, &clk_security.hw); | ||
| 1073 | BUG_ON(!clk); | ||
| 1074 | clk_register_clkdev(clk, NULL, "b8030000.security"); | ||
| 1075 | clk = clk_register(NULL, &clk_dsp.hw); | ||
| 1076 | BUG_ON(!clk); | ||
| 1077 | clk = clk_register(NULL, &clk_gps.hw); | ||
| 1078 | BUG_ON(!clk); | ||
| 1079 | clk_register_clkdev(clk, NULL, "a8010000.gps"); | ||
| 1080 | clk = clk_register(NULL, &clk_mf.hw); | ||
| 1081 | BUG_ON(!clk); | ||
| 1082 | clk = clk_register(NULL, &clk_io.hw); | ||
| 1083 | BUG_ON(!clk); | ||
| 1084 | clk_register_clkdev(clk, NULL, "io"); | ||
| 1085 | clk = clk_register(NULL, &clk_cpu.hw); | ||
| 1086 | BUG_ON(!clk); | ||
| 1087 | clk_register_clkdev(clk, NULL, "cpu"); | ||
| 1088 | clk = clk_register(NULL, &clk_uart0.hw); | ||
| 1089 | BUG_ON(!clk); | ||
| 1090 | clk_register_clkdev(clk, NULL, "b0050000.uart"); | ||
| 1091 | clk = clk_register(NULL, &clk_uart1.hw); | ||
| 1092 | BUG_ON(!clk); | ||
| 1093 | clk_register_clkdev(clk, NULL, "b0060000.uart"); | ||
| 1094 | clk = clk_register(NULL, &clk_uart2.hw); | ||
| 1095 | BUG_ON(!clk); | ||
| 1096 | clk_register_clkdev(clk, NULL, "b0070000.uart"); | ||
| 1097 | clk = clk_register(NULL, &clk_tsc.hw); | ||
| 1098 | BUG_ON(!clk); | ||
| 1099 | clk_register_clkdev(clk, NULL, "b0110000.tsc"); | ||
| 1100 | clk = clk_register(NULL, &clk_i2c0.hw); | ||
| 1101 | BUG_ON(!clk); | ||
| 1102 | clk_register_clkdev(clk, NULL, "b00e0000.i2c"); | ||
| 1103 | clk = clk_register(NULL, &clk_i2c1.hw); | ||
| 1104 | BUG_ON(!clk); | ||
| 1105 | clk_register_clkdev(clk, NULL, "b00f0000.i2c"); | ||
| 1106 | clk = clk_register(NULL, &clk_spi0.hw); | ||
| 1107 | BUG_ON(!clk); | ||
| 1108 | clk_register_clkdev(clk, NULL, "b00d0000.spi"); | ||
| 1109 | clk = clk_register(NULL, &clk_spi1.hw); | ||
| 1110 | BUG_ON(!clk); | ||
| 1111 | clk_register_clkdev(clk, NULL, "b0170000.spi"); | ||
| 1112 | clk = clk_register(NULL, &clk_pwmc.hw); | ||
| 1113 | BUG_ON(!clk); | ||
| 1114 | clk_register_clkdev(clk, NULL, "b0130000.pwm"); | ||
| 1115 | clk = clk_register(NULL, &clk_efuse.hw); | ||
| 1116 | BUG_ON(!clk); | ||
| 1117 | clk_register_clkdev(clk, NULL, "b0140000.efusesys"); | ||
| 1118 | clk = clk_register(NULL, &clk_pulse.hw); | ||
| 1119 | BUG_ON(!clk); | ||
| 1120 | clk_register_clkdev(clk, NULL, "b0150000.pulsec"); | ||
| 1121 | clk = clk_register(NULL, &clk_dmac0.hw); | ||
| 1122 | BUG_ON(!clk); | ||
| 1123 | clk_register_clkdev(clk, NULL, "b00b0000.dma-controller"); | ||
| 1124 | clk = clk_register(NULL, &clk_dmac1.hw); | ||
| 1125 | BUG_ON(!clk); | ||
| 1126 | clk_register_clkdev(clk, NULL, "b0160000.dma-controller"); | ||
| 1127 | clk = clk_register(NULL, &clk_nand.hw); | ||
| 1128 | BUG_ON(!clk); | ||
| 1129 | clk_register_clkdev(clk, NULL, "b0030000.nand"); | ||
| 1130 | clk = clk_register(NULL, &clk_audio.hw); | ||
| 1131 | BUG_ON(!clk); | ||
| 1132 | clk_register_clkdev(clk, NULL, "b0040000.audio"); | ||
| 1133 | clk = clk_register(NULL, &clk_usp0.hw); | ||
| 1134 | BUG_ON(!clk); | ||
| 1135 | clk_register_clkdev(clk, NULL, "b0080000.usp"); | ||
| 1136 | clk = clk_register(NULL, &clk_usp1.hw); | ||
| 1137 | BUG_ON(!clk); | ||
| 1138 | clk_register_clkdev(clk, NULL, "b0090000.usp"); | ||
| 1139 | clk = clk_register(NULL, &clk_usp2.hw); | ||
| 1140 | BUG_ON(!clk); | ||
| 1141 | clk_register_clkdev(clk, NULL, "b00a0000.usp"); | ||
| 1142 | clk = clk_register(NULL, &clk_vip.hw); | ||
| 1143 | BUG_ON(!clk); | ||
| 1144 | clk_register_clkdev(clk, NULL, "b00c0000.vip"); | ||
| 1145 | clk = clk_register(NULL, &clk_gfx.hw); | ||
| 1146 | BUG_ON(!clk); | ||
| 1147 | clk_register_clkdev(clk, NULL, "98000000.graphics"); | ||
| 1148 | clk = clk_register(NULL, &clk_mm.hw); | ||
| 1149 | BUG_ON(!clk); | ||
| 1150 | clk_register_clkdev(clk, NULL, "a0000000.multimedia"); | ||
| 1151 | clk = clk_register(NULL, &clk_lcd.hw); | ||
| 1152 | BUG_ON(!clk); | ||
| 1153 | clk_register_clkdev(clk, NULL, "90010000.display"); | ||
| 1154 | clk = clk_register(NULL, &clk_vpp.hw); | ||
| 1155 | BUG_ON(!clk); | ||
| 1156 | clk_register_clkdev(clk, NULL, "90020000.vpp"); | ||
| 1157 | clk = clk_register(NULL, &clk_mmc01.hw); | ||
| 1158 | BUG_ON(!clk); | ||
| 1159 | clk = clk_register(NULL, &clk_mmc23.hw); | ||
| 1160 | BUG_ON(!clk); | ||
| 1161 | clk = clk_register(NULL, &clk_mmc45.hw); | ||
| 1162 | BUG_ON(!clk); | ||
| 1163 | clk = clk_register(NULL, &usb_pll_clk_hw); | ||
| 1164 | BUG_ON(!clk); | ||
| 1165 | clk = clk_register(NULL, &clk_usb0.hw); | ||
| 1166 | BUG_ON(!clk); | ||
| 1167 | clk_register_clkdev(clk, NULL, "b00e0000.usb"); | ||
| 1168 | clk = clk_register(NULL, &clk_usb1.hw); | ||
| 1169 | BUG_ON(!clk); | ||
| 1170 | clk_register_clkdev(clk, NULL, "b00f0000.usb"); | ||
| 1171 | } | ||
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index efdfd009c270..56e4495ebeb1 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c | |||
| @@ -558,25 +558,6 @@ int clk_enable(struct clk *clk) | |||
| 558 | EXPORT_SYMBOL_GPL(clk_enable); | 558 | EXPORT_SYMBOL_GPL(clk_enable); |
| 559 | 559 | ||
| 560 | /** | 560 | /** |
| 561 | * clk_get_rate - return the rate of clk | ||
| 562 | * @clk: the clk whose rate is being returned | ||
| 563 | * | ||
| 564 | * Simply returns the cached rate of the clk. Does not query the hardware. If | ||
| 565 | * clk is NULL then returns 0. | ||
| 566 | */ | ||
| 567 | unsigned long clk_get_rate(struct clk *clk) | ||
| 568 | { | ||
| 569 | unsigned long rate; | ||
| 570 | |||
| 571 | mutex_lock(&prepare_lock); | ||
| 572 | rate = __clk_get_rate(clk); | ||
| 573 | mutex_unlock(&prepare_lock); | ||
| 574 | |||
| 575 | return rate; | ||
| 576 | } | ||
| 577 | EXPORT_SYMBOL_GPL(clk_get_rate); | ||
| 578 | |||
| 579 | /** | ||
| 580 | * __clk_round_rate - round the given rate for a clk | 561 | * __clk_round_rate - round the given rate for a clk |
| 581 | * @clk: round the rate of this clock | 562 | * @clk: round the rate of this clock |
| 582 | * | 563 | * |
| @@ -702,6 +683,30 @@ static void __clk_recalc_rates(struct clk *clk, unsigned long msg) | |||
| 702 | } | 683 | } |
| 703 | 684 | ||
| 704 | /** | 685 | /** |
| 686 | * clk_get_rate - return the rate of clk | ||
| 687 | * @clk: the clk whose rate is being returned | ||
| 688 | * | ||
| 689 | * Simply returns the cached rate of the clk, unless CLK_GET_RATE_NOCACHE flag | ||
| 690 | * is set, which means a recalc_rate will be issued. | ||
| 691 | * If clk is NULL then returns 0. | ||
| 692 | */ | ||
| 693 | unsigned long clk_get_rate(struct clk *clk) | ||
| 694 | { | ||
| 695 | unsigned long rate; | ||
| 696 | |||
| 697 | mutex_lock(&prepare_lock); | ||
| 698 | |||
| 699 | if (clk && (clk->flags & CLK_GET_RATE_NOCACHE)) | ||
| 700 | __clk_recalc_rates(clk, 0); | ||
| 701 | |||
| 702 | rate = __clk_get_rate(clk); | ||
| 703 | mutex_unlock(&prepare_lock); | ||
| 704 | |||
| 705 | return rate; | ||
| 706 | } | ||
| 707 | EXPORT_SYMBOL_GPL(clk_get_rate); | ||
| 708 | |||
| 709 | /** | ||
| 705 | * __clk_speculate_rates | 710 | * __clk_speculate_rates |
| 706 | * @clk: first clk in the subtree | 711 | * @clk: first clk in the subtree |
| 707 | * @parent_rate: the "future" rate of clk's parent | 712 | * @parent_rate: the "future" rate of clk's parent |
| @@ -1582,6 +1587,20 @@ struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, | |||
| 1582 | } | 1587 | } |
| 1583 | EXPORT_SYMBOL_GPL(of_clk_src_simple_get); | 1588 | EXPORT_SYMBOL_GPL(of_clk_src_simple_get); |
| 1584 | 1589 | ||
| 1590 | struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data) | ||
| 1591 | { | ||
| 1592 | struct clk_onecell_data *clk_data = data; | ||
| 1593 | unsigned int idx = clkspec->args[0]; | ||
| 1594 | |||
| 1595 | if (idx >= clk_data->clk_num) { | ||
| 1596 | pr_err("%s: invalid clock index %d\n", __func__, idx); | ||
| 1597 | return ERR_PTR(-EINVAL); | ||
| 1598 | } | ||
| 1599 | |||
| 1600 | return clk_data->clks[idx]; | ||
| 1601 | } | ||
| 1602 | EXPORT_SYMBOL_GPL(of_clk_src_onecell_get); | ||
| 1603 | |||
| 1585 | /** | 1604 | /** |
| 1586 | * of_clk_add_provider() - Register a clock provider for a node | 1605 | * of_clk_add_provider() - Register a clock provider for a node |
| 1587 | * @np: Device node pointer associated with clock provider | 1606 | * @np: Device node pointer associated with clock provider |
diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile new file mode 100644 index 000000000000..392d78044ce3 --- /dev/null +++ b/drivers/clk/mmp/Makefile | |||
| @@ -0,0 +1,9 @@ | |||
| 1 | # | ||
| 2 | # Makefile for mmp specific clk | ||
| 3 | # | ||
| 4 | |||
| 5 | obj-y += clk-apbc.o clk-apmu.o clk-frac.o | ||
| 6 | |||
| 7 | obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o | ||
| 8 | obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o | ||
| 9 | obj-$(CONFIG_CPU_MMP2) += clk-mmp2.o | ||
diff --git a/drivers/clk/mmp/clk-apbc.c b/drivers/clk/mmp/clk-apbc.c new file mode 100644 index 000000000000..d14120eaa71f --- /dev/null +++ b/drivers/clk/mmp/clk-apbc.c | |||
| @@ -0,0 +1,152 @@ | |||
| 1 | /* | ||
| 2 | * mmp APB clock operation source file | ||
| 3 | * | ||
| 4 | * Copyright (C) 2012 Marvell | ||
| 5 | * Chao Xie <xiechao.mail@gmail.com> | ||
| 6 | * | ||
| 7 | * This file is licensed under the terms of the GNU General Public | ||
| 8 | * License version 2. This program is licensed "as is" without any | ||
| 9 | * warranty of any kind, whether express or implied. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/kernel.h> | ||
| 13 | #include <linux/clk.h> | ||
| 14 | #include <linux/io.h> | ||
| 15 | #include <linux/err.h> | ||
| 16 | #include <linux/delay.h> | ||
| 17 | #include <linux/slab.h> | ||
| 18 | |||
| 19 | #include "clk.h" | ||
| 20 | |||
| 21 | /* Common APB clock register bit definitions */ | ||
| 22 | #define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */ | ||
| 23 | #define APBC_FNCLK (1 << 1) /* Functional Clock Enable */ | ||
| 24 | #define APBC_RST (1 << 2) /* Reset Generation */ | ||
| 25 | #define APBC_POWER (1 << 7) /* Reset Generation */ | ||
| 26 | |||
| 27 | #define to_clk_apbc(hw) container_of(hw, struct clk_apbc, hw) | ||
| 28 | struct clk_apbc { | ||
| 29 | struct clk_hw hw; | ||
| 30 | void __iomem *base; | ||
| 31 | unsigned int delay; | ||
| 32 | unsigned int flags; | ||
| 33 | spinlock_t *lock; | ||
| 34 | }; | ||
| 35 | |||
| 36 | static int clk_apbc_prepare(struct clk_hw *hw) | ||
| 37 | { | ||
| 38 | struct clk_apbc *apbc = to_clk_apbc(hw); | ||
| 39 | unsigned int data; | ||
| 40 | unsigned long flags = 0; | ||
| 41 | |||
| 42 | /* | ||
| 43 | * It may share same register as MUX clock, | ||
| 44 | * and it will impact FNCLK enable. Spinlock is needed | ||
| 45 | */ | ||
| 46 | if (apbc->lock) | ||
| 47 | spin_lock_irqsave(apbc->lock, flags); | ||
| 48 | |||
| 49 | data = readl_relaxed(apbc->base); | ||
| 50 | if (apbc->flags & APBC_POWER_CTRL) | ||
| 51 | data |= APBC_POWER; | ||
| 52 | data |= APBC_FNCLK; | ||
| 53 | writel_relaxed(data, apbc->base); | ||
| 54 | |||
| 55 | if (apbc->lock) | ||
| 56 | spin_unlock_irqrestore(apbc->lock, flags); | ||
| 57 | |||
| 58 | udelay(apbc->delay); | ||
| 59 | |||
| 60 | if (apbc->lock) | ||
| 61 | spin_lock_irqsave(apbc->lock, flags); | ||
| 62 | |||
| 63 | data = readl_relaxed(apbc->base); | ||
| 64 | data |= APBC_APBCLK; | ||
| 65 | writel_relaxed(data, apbc->base); | ||
| 66 | |||
| 67 | if (apbc->lock) | ||
| 68 | spin_unlock_irqrestore(apbc->lock, flags); | ||
| 69 | |||
| 70 | udelay(apbc->delay); | ||
| 71 | |||
| 72 | if (!(apbc->flags & APBC_NO_BUS_CTRL)) { | ||
| 73 | if (apbc->lock) | ||
| 74 | spin_lock_irqsave(apbc->lock, flags); | ||
| 75 | |||
| 76 | data = readl_relaxed(apbc->base); | ||
| 77 | data &= ~APBC_RST; | ||
| 78 | writel_relaxed(data, apbc->base); | ||
| 79 | |||
| 80 | if (apbc->lock) | ||
| 81 | spin_unlock_irqrestore(apbc->lock, flags); | ||
| 82 | } | ||
| 83 | |||
| 84 | return 0; | ||
| 85 | } | ||
| 86 | |||
| 87 | static void clk_apbc_unprepare(struct clk_hw *hw) | ||
| 88 | { | ||
| 89 | struct clk_apbc *apbc = to_clk_apbc(hw); | ||
| 90 | unsigned long data; | ||
| 91 | unsigned long flags = 0; | ||
| 92 | |||
| 93 | if (apbc->lock) | ||
| 94 | spin_lock_irqsave(apbc->lock, flags); | ||
| 95 | |||
| 96 | data = readl_relaxed(apbc->base); | ||
| 97 | if (apbc->flags & APBC_POWER_CTRL) | ||
| 98 | data &= ~APBC_POWER; | ||
| 99 | data &= ~APBC_FNCLK; | ||
| 100 | writel_relaxed(data, apbc->base); | ||
| 101 | |||
| 102 | if (apbc->lock) | ||
| 103 | spin_unlock_irqrestore(apbc->lock, flags); | ||
| 104 | |||
| 105 | udelay(10); | ||
| 106 | |||
| 107 | if (apbc->lock) | ||
| 108 | spin_lock_irqsave(apbc->lock, flags); | ||
| 109 | |||
| 110 | data = readl_relaxed(apbc->base); | ||
| 111 | data &= ~APBC_APBCLK; | ||
| 112 | writel_relaxed(data, apbc->base); | ||
| 113 | |||
| 114 | if (apbc->lock) | ||
| 115 | spin_unlock_irqrestore(apbc->lock, flags); | ||
| 116 | } | ||
| 117 | |||
| 118 | struct clk_ops clk_apbc_ops = { | ||
| 119 | .prepare = clk_apbc_prepare, | ||
| 120 | .unprepare = clk_apbc_unprepare, | ||
| 121 | }; | ||
| 122 | |||
| 123 | struct clk *mmp_clk_register_apbc(const char *name, const char *parent_name, | ||
| 124 | void __iomem *base, unsigned int delay, | ||
| 125 | unsigned int apbc_flags, spinlock_t *lock) | ||
| 126 | { | ||
| 127 | struct clk_apbc *apbc; | ||
| 128 | struct clk *clk; | ||
| 129 | struct clk_init_data init; | ||
| 130 | |||
| 131 | apbc = kzalloc(sizeof(*apbc), GFP_KERNEL); | ||
| 132 | if (!apbc) | ||
| 133 | return NULL; | ||
| 134 | |||
| 135 | init.name = name; | ||
| 136 | init.ops = &clk_apbc_ops; | ||
| 137 | init.flags = CLK_SET_RATE_PARENT; | ||
| 138 | init.parent_names = (parent_name ? &parent_name : NULL); | ||
| 139 | init.num_parents = (parent_name ? 1 : 0); | ||
| 140 | |||
| 141 | apbc->base = base; | ||
| 142 | apbc->delay = delay; | ||
| 143 | apbc->flags = apbc_flags; | ||
| 144 | apbc->lock = lock; | ||
| 145 | apbc->hw.init = &init; | ||
| 146 | |||
| 147 | clk = clk_register(NULL, &apbc->hw); | ||
| 148 | if (IS_ERR(clk)) | ||
| 149 | kfree(apbc); | ||
| 150 | |||
| 151 | return clk; | ||
| 152 | } | ||
diff --git a/drivers/clk/mmp/clk-apmu.c b/drivers/clk/mmp/clk-apmu.c new file mode 100644 index 000000000000..abe182b2377f --- /dev/null +++ b/drivers/clk/mmp/clk-apmu.c | |||
| @@ -0,0 +1,97 @@ | |||
| 1 | /* | ||
| 2 | * mmp AXI peripharal clock operation source file | ||
| 3 | * | ||
| 4 | * Copyright (C) 2012 Marvell | ||
| 5 | * Chao Xie <xiechao.mail@gmail.com> | ||
| 6 | * | ||
| 7 | * This file is licensed under the terms of the GNU General Public | ||
| 8 | * License version 2. This program is licensed "as is" without any | ||
| 9 | * warranty of any kind, whether express or implied. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/kernel.h> | ||
| 13 | #include <linux/clk.h> | ||
| 14 | #include <linux/io.h> | ||
| 15 | #include <linux/err.h> | ||
| 16 | #include <linux/delay.h> | ||
| 17 | #include <linux/slab.h> | ||
| 18 | |||
| 19 | #include "clk.h" | ||
| 20 | |||
| 21 | #define to_clk_apmu(clk) (container_of(clk, struct clk_apmu, clk)) | ||
| 22 | struct clk_apmu { | ||
| 23 | struct clk_hw hw; | ||
| 24 | void __iomem *base; | ||
| 25 | u32 rst_mask; | ||
| 26 | u32 enable_mask; | ||
| 27 | spinlock_t *lock; | ||
| 28 | }; | ||
| 29 | |||
| 30 | static int clk_apmu_enable(struct clk_hw *hw) | ||
| 31 | { | ||
| 32 | struct clk_apmu *apmu = to_clk_apmu(hw); | ||
| 33 | unsigned long data; | ||
| 34 | unsigned long flags = 0; | ||
| 35 | |||
| 36 | if (apmu->lock) | ||
| 37 | spin_lock_irqsave(apmu->lock, flags); | ||
| 38 | |||
| 39 | data = readl_relaxed(apmu->base) | apmu->enable_mask; | ||
| 40 | writel_relaxed(data, apmu->base); | ||
| 41 | |||
| 42 | if (apmu->lock) | ||
| 43 | spin_unlock_irqrestore(apmu->lock, flags); | ||
| 44 | |||
| 45 | return 0; | ||
| 46 | } | ||
| 47 | |||
| 48 | static void clk_apmu_disable(struct clk_hw *hw) | ||
| 49 | { | ||
| 50 | struct clk_apmu *apmu = to_clk_apmu(hw); | ||
| 51 | unsigned long data; | ||
| 52 | unsigned long flags = 0; | ||
| 53 | |||
| 54 | if (apmu->lock) | ||
| 55 | spin_lock_irqsave(apmu->lock, flags); | ||
| 56 | |||
| 57 | data = readl_relaxed(apmu->base) & ~apmu->enable_mask; | ||
| 58 | writel_relaxed(data, apmu->base); | ||
| 59 | |||
| 60 | if (apmu->lock) | ||
| 61 | spin_unlock_irqrestore(apmu->lock, flags); | ||
| 62 | } | ||
| 63 | |||
| 64 | struct clk_ops clk_apmu_ops = { | ||
| 65 | .enable = clk_apmu_enable, | ||
| 66 | .disable = clk_apmu_disable, | ||
| 67 | }; | ||
| 68 | |||
| 69 | struct clk *mmp_clk_register_apmu(const char *name, const char *parent_name, | ||
| 70 | void __iomem *base, u32 enable_mask, spinlock_t *lock) | ||
| 71 | { | ||
| 72 | struct clk_apmu *apmu; | ||
| 73 | struct clk *clk; | ||
| 74 | struct clk_init_data init; | ||
| 75 | |||
| 76 | apmu = kzalloc(sizeof(*apmu), GFP_KERNEL); | ||
| 77 | if (!apmu) | ||
| 78 | return NULL; | ||
| 79 | |||
| 80 | init.name = name; | ||
| 81 | init.ops = &clk_apmu_ops; | ||
| 82 | init.flags = CLK_SET_RATE_PARENT; | ||
| 83 | init.parent_names = (parent_name ? &parent_name : NULL); | ||
| 84 | init.num_parents = (parent_name ? 1 : 0); | ||
| 85 | |||
| 86 | apmu->base = base; | ||
| 87 | apmu->enable_mask = enable_mask; | ||
| 88 | apmu->lock = lock; | ||
| 89 | apmu->hw.init = &init; | ||
| 90 | |||
| 91 | clk = clk_register(NULL, &apmu->hw); | ||
| 92 | |||
| 93 | if (IS_ERR(clk)) | ||
| 94 | kfree(apmu); | ||
| 95 | |||
| 96 | return clk; | ||
| 97 | } | ||
diff --git a/drivers/clk/mmp/clk-frac.c b/drivers/clk/mmp/clk-frac.c new file mode 100644 index 000000000000..80c1dd15d15c --- /dev/null +++ b/drivers/clk/mmp/clk-frac.c | |||
| @@ -0,0 +1,153 @@ | |||
| 1 | /* | ||
| 2 | * mmp factor clock operation source file | ||
| 3 | * | ||
| 4 | * Copyright (C) 2012 Marvell | ||
| 5 | * Chao Xie <xiechao.mail@gmail.com> | ||
| 6 | * | ||
| 7 | * This file is licensed under the terms of the GNU General Public | ||
| 8 | * License version 2. This program is licensed "as is" without any | ||
| 9 | * warranty of any kind, whether express or implied. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/clk-provider.h> | ||
| 13 | #include <linux/slab.h> | ||
| 14 | #include <linux/io.h> | ||
| 15 | #include <linux/err.h> | ||
| 16 | |||
| 17 | #include "clk.h" | ||
| 18 | /* | ||
| 19 | * It is M/N clock | ||
| 20 | * | ||
| 21 | * Fout from synthesizer can be given from two equations: | ||
| 22 | * numerator/denominator = Fin / (Fout * factor) | ||
| 23 | */ | ||
| 24 | |||
| 25 | #define to_clk_factor(hw) container_of(hw, struct clk_factor, hw) | ||
| 26 | struct clk_factor { | ||
| 27 | struct clk_hw hw; | ||
| 28 | void __iomem *base; | ||
| 29 | struct clk_factor_masks *masks; | ||
| 30 | struct clk_factor_tbl *ftbl; | ||
| 31 | unsigned int ftbl_cnt; | ||
| 32 | }; | ||
| 33 | |||
| 34 | static long clk_factor_round_rate(struct clk_hw *hw, unsigned long drate, | ||
| 35 | unsigned long *prate) | ||
| 36 | { | ||
| 37 | struct clk_factor *factor = to_clk_factor(hw); | ||
| 38 | unsigned long rate = 0, prev_rate; | ||
| 39 | int i; | ||
| 40 | |||
| 41 | for (i = 0; i < factor->ftbl_cnt; i++) { | ||
| 42 | prev_rate = rate; | ||
| 43 | rate = (((*prate / 10000) * factor->ftbl[i].num) / | ||
| 44 | (factor->ftbl[i].den * factor->masks->factor)) * 10000; | ||
| 45 | if (rate > drate) | ||
| 46 | break; | ||
| 47 | } | ||
| 48 | if (i == 0) | ||
| 49 | return rate; | ||
| 50 | else | ||
| 51 | return prev_rate; | ||
| 52 | } | ||
| 53 | |||
| 54 | static unsigned long clk_factor_recalc_rate(struct clk_hw *hw, | ||
| 55 | unsigned long parent_rate) | ||
| 56 | { | ||
| 57 | struct clk_factor *factor = to_clk_factor(hw); | ||
| 58 | struct clk_factor_masks *masks = factor->masks; | ||
| 59 | unsigned int val, num, den; | ||
| 60 | |||
| 61 | val = readl_relaxed(factor->base); | ||
| 62 | |||
| 63 | /* calculate numerator */ | ||
| 64 | num = (val >> masks->num_shift) & masks->num_mask; | ||
| 65 | |||
| 66 | /* calculate denominator */ | ||
| 67 | den = (val >> masks->den_shift) & masks->num_mask; | ||
| 68 | |||
| 69 | if (!den) | ||
| 70 | return 0; | ||
| 71 | |||
| 72 | return (((parent_rate / 10000) * den) / | ||
| 73 | (num * factor->masks->factor)) * 10000; | ||
| 74 | } | ||
| 75 | |||
| 76 | /* Configures new clock rate*/ | ||
| 77 | static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate, | ||
| 78 | unsigned long prate) | ||
| 79 | { | ||
| 80 | struct clk_factor *factor = to_clk_factor(hw); | ||
| 81 | struct clk_factor_masks *masks = factor->masks; | ||
| 82 | int i; | ||
| 83 | unsigned long val; | ||
| 84 | unsigned long prev_rate, rate = 0; | ||
| 85 | |||
| 86 | for (i = 0; i < factor->ftbl_cnt; i++) { | ||
| 87 | prev_rate = rate; | ||
| 88 | rate = (((prate / 10000) * factor->ftbl[i].num) / | ||
| 89 | (factor->ftbl[i].den * factor->masks->factor)) * 10000; | ||
| 90 | if (rate > drate) | ||
| 91 | break; | ||
| 92 | } | ||
| 93 | if (i > 0) | ||
| 94 | i--; | ||
| 95 | |||
| 96 | val = readl_relaxed(factor->base); | ||
| 97 | |||
| 98 | val &= ~(masks->num_mask << masks->num_shift); | ||
| 99 | val |= (factor->ftbl[i].num & masks->num_mask) << masks->num_shift; | ||
| 100 | |||
| 101 | val &= ~(masks->den_mask << masks->den_shift); | ||
| 102 | val |= (factor->ftbl[i].den & masks->den_mask) << masks->den_shift; | ||
| 103 | |||
| 104 | writel_relaxed(val, factor->base); | ||
| 105 | |||
| 106 | return 0; | ||
| 107 | } | ||
| 108 | |||
| 109 | static struct clk_ops clk_factor_ops = { | ||
| 110 | .recalc_rate = clk_factor_recalc_rate, | ||
| 111 | .round_rate = clk_factor_round_rate, | ||
| 112 | .set_rate = clk_factor_set_rate, | ||
| 113 | }; | ||
| 114 | |||
| 115 | struct clk *mmp_clk_register_factor(const char *name, const char *parent_name, | ||
| 116 | unsigned long flags, void __iomem *base, | ||
| 117 | struct clk_factor_masks *masks, struct clk_factor_tbl *ftbl, | ||
| 118 | unsigned int ftbl_cnt) | ||
| 119 | { | ||
| 120 | struct clk_factor *factor; | ||
| 121 | struct clk_init_data init; | ||
| 122 | struct clk *clk; | ||
| 123 | |||
| 124 | if (!masks) { | ||
| 125 | pr_err("%s: must pass a clk_factor_mask\n", __func__); | ||
| 126 | return ERR_PTR(-EINVAL); | ||
| 127 | } | ||
| 128 | |||
| 129 | factor = kzalloc(sizeof(*factor), GFP_KERNEL); | ||
| 130 | if (!factor) { | ||
| 131 | pr_err("%s: could not allocate factor clk\n", __func__); | ||
| 132 | return ERR_PTR(-ENOMEM); | ||
| 133 | } | ||
| 134 | |||
| 135 | /* struct clk_aux assignments */ | ||
| 136 | factor->base = base; | ||
| 137 | factor->masks = masks; | ||
| 138 | factor->ftbl = ftbl; | ||
| 139 | factor->ftbl_cnt = ftbl_cnt; | ||
| 140 | factor->hw.init = &init; | ||
| 141 | |||
| 142 | init.name = name; | ||
| 143 | init.ops = &clk_factor_ops; | ||
| 144 | init.flags = flags; | ||
| 145 | init.parent_names = &parent_name; | ||
| 146 | init.num_parents = 1; | ||
| 147 | |||
| 148 | clk = clk_register(NULL, &factor->hw); | ||
| 149 | if (IS_ERR_OR_NULL(clk)) | ||
| 150 | kfree(factor); | ||
| 151 | |||
| 152 | return clk; | ||
| 153 | } | ||
diff --git a/drivers/clk/mmp/clk-mmp2.c b/drivers/clk/mmp/clk-mmp2.c new file mode 100644 index 000000000000..ade435820c7e --- /dev/null +++ b/drivers/clk/mmp/clk-mmp2.c | |||
| @@ -0,0 +1,449 @@ | |||
| 1 | /* | ||
| 2 | * mmp2 clock framework source file | ||
| 3 | * | ||
| 4 | * Copyright (C) 2012 Marvell | ||
| 5 | * Chao Xie <xiechao.mail@gmail.com> | ||
| 6 | * | ||
| 7 | * This file is licensed under the terms of the GNU General Public | ||
| 8 | * License version 2. This program is licensed "as is" without any | ||
| 9 | * warranty of any kind, whether express or implied. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/module.h> | ||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/spinlock.h> | ||
| 15 | #include <linux/io.h> | ||
| 16 | #include <linux/delay.h> | ||
| 17 | #include <linux/err.h> | ||
| 18 | |||
| 19 | #include <mach/addr-map.h> | ||
| 20 | |||
| 21 | #include "clk.h" | ||
| 22 | |||
| 23 | #define APBC_RTC 0x0 | ||
| 24 | #define APBC_TWSI0 0x4 | ||
| 25 | #define APBC_TWSI1 0x8 | ||
| 26 | #define APBC_TWSI2 0xc | ||
| 27 | #define APBC_TWSI3 0x10 | ||
| 28 | #define APBC_TWSI4 0x7c | ||
| 29 | #define APBC_TWSI5 0x80 | ||
| 30 | #define APBC_KPC 0x18 | ||
| 31 | #define APBC_UART0 0x2c | ||
| 32 | #define APBC_UART1 0x30 | ||
| 33 | #define APBC_UART2 0x34 | ||
| 34 | #define APBC_UART3 0x88 | ||
| 35 | #define APBC_GPIO 0x38 | ||
| 36 | #define APBC_PWM0 0x3c | ||
| 37 | #define APBC_PWM1 0x40 | ||
| 38 | #define APBC_PWM2 0x44 | ||
| 39 | #define APBC_PWM3 0x48 | ||
| 40 | #define APBC_SSP0 0x50 | ||
| 41 | #define APBC_SSP1 0x54 | ||
| 42 | #define APBC_SSP2 0x58 | ||
| 43 | #define APBC_SSP3 0x5c | ||
| 44 | #define APMU_SDH0 0x54 | ||
| 45 | #define APMU_SDH1 0x58 | ||
| 46 | #define APMU_SDH2 0xe8 | ||
| 47 | #define APMU_SDH3 0xec | ||
| 48 | #define APMU_USB 0x5c | ||
| 49 | #define APMU_DISP0 0x4c | ||
| 50 | #define APMU_DISP1 0x110 | ||
| 51 | #define APMU_CCIC0 0x50 | ||
| 52 | #define APMU_CCIC1 0xf4 | ||
| 53 | #define MPMU_UART_PLL 0x14 | ||
| 54 | |||
| 55 | static DEFINE_SPINLOCK(clk_lock); | ||
| 56 | |||
| 57 | static struct clk_factor_masks uart_factor_masks = { | ||
| 58 | .factor = 2, | ||
| 59 | .num_mask = 0x1fff, | ||
| 60 | .den_mask = 0x1fff, | ||
| 61 | .num_shift = 16, | ||
| 62 | .den_shift = 0, | ||
| 63 | }; | ||
| 64 | |||
| 65 | static struct clk_factor_tbl uart_factor_tbl[] = { | ||
| 66 | {.num = 14634, .den = 2165}, /*14.745MHZ */ | ||
| 67 | {.num = 3521, .den = 689}, /*19.23MHZ */ | ||
| 68 | {.num = 9679, .den = 5728}, /*58.9824MHZ */ | ||
| 69 | {.num = 15850, .den = 9451}, /*59.429MHZ */ | ||
| 70 | }; | ||
| 71 | |||
| 72 | static const char *uart_parent[] = {"uart_pll", "vctcxo"}; | ||
| 73 | static const char *ssp_parent[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"}; | ||
| 74 | static const char *sdh_parent[] = {"pll1_4", "pll2", "usb_pll", "pll1"}; | ||
| 75 | static const char *disp_parent[] = {"pll1", "pll1_16", "pll2", "vctcxo"}; | ||
| 76 | static const char *ccic_parent[] = {"pll1_2", "pll1_16", "vctcxo"}; | ||
| 77 | |||
| 78 | void __init mmp2_clk_init(void) | ||
| 79 | { | ||
| 80 | struct clk *clk; | ||
| 81 | struct clk *vctcxo; | ||
| 82 | void __iomem *mpmu_base; | ||
| 83 | void __iomem *apmu_base; | ||
| 84 | void __iomem *apbc_base; | ||
| 85 | |||
| 86 | mpmu_base = ioremap(APB_PHYS_BASE + 0x50000, SZ_4K); | ||
| 87 | if (mpmu_base == NULL) { | ||
| 88 | pr_err("error to ioremap MPMU base\n"); | ||
| 89 | return; | ||
| 90 | } | ||
| 91 | |||
| 92 | apmu_base = ioremap(AXI_PHYS_BASE + 0x82800, SZ_4K); | ||
| 93 | if (apmu_base == NULL) { | ||
| 94 | pr_err("error to ioremap APMU base\n"); | ||
| 95 | return; | ||
| 96 | } | ||
| 97 | |||
| 98 | apbc_base = ioremap(APB_PHYS_BASE + 0x15000, SZ_4K); | ||
| 99 | if (apbc_base == NULL) { | ||
| 100 | pr_err("error to ioremap APBC base\n"); | ||
| 101 | return; | ||
| 102 | } | ||
| 103 | |||
| 104 | clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200); | ||
| 105 | clk_register_clkdev(clk, "clk32", NULL); | ||
| 106 | |||
| 107 | vctcxo = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT, | ||
| 108 | 26000000); | ||
| 109 | clk_register_clkdev(vctcxo, "vctcxo", NULL); | ||
| 110 | |||
| 111 | clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT, | ||
| 112 | 800000000); | ||
| 113 | clk_register_clkdev(clk, "pll1", NULL); | ||
| 114 | |||
| 115 | clk = clk_register_fixed_rate(NULL, "usb_pll", NULL, CLK_IS_ROOT, | ||
| 116 | 480000000); | ||
| 117 | clk_register_clkdev(clk, "usb_pll", NULL); | ||
| 118 | |||
| 119 | clk = clk_register_fixed_rate(NULL, "pll2", NULL, CLK_IS_ROOT, | ||
| 120 | 960000000); | ||
| 121 | clk_register_clkdev(clk, "pll2", NULL); | ||
| 122 | |||
| 123 | clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", | ||
| 124 | CLK_SET_RATE_PARENT, 1, 2); | ||
| 125 | clk_register_clkdev(clk, "pll1_2", NULL); | ||
| 126 | |||
| 127 | clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2", | ||
| 128 | CLK_SET_RATE_PARENT, 1, 2); | ||
| 129 | clk_register_clkdev(clk, "pll1_4", NULL); | ||
| 130 | |||
| 131 | clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4", | ||
| 132 | CLK_SET_RATE_PARENT, 1, 2); | ||
| 133 | clk_register_clkdev(clk, "pll1_8", NULL); | ||
| 134 | |||
| 135 | clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8", | ||
| 136 | CLK_SET_RATE_PARENT, 1, 2); | ||
| 137 | clk_register_clkdev(clk, "pll1_16", NULL); | ||
| 138 | |||
| 139 | clk = clk_register_fixed_factor(NULL, "pll1_20", "pll1_4", | ||
| 140 | CLK_SET_RATE_PARENT, 1, 5); | ||
| 141 | clk_register_clkdev(clk, "pll1_20", NULL); | ||
| 142 | |||
| 143 | clk = clk_register_fixed_factor(NULL, "pll1_3", "pll1", | ||
| 144 | CLK_SET_RATE_PARENT, 1, 3); | ||
| 145 | clk_register_clkdev(clk, "pll1_3", NULL); | ||
| 146 | |||
| 147 | clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_3", | ||
| 148 | CLK_SET_RATE_PARENT, 1, 2); | ||
| 149 | clk_register_clkdev(clk, "pll1_6", NULL); | ||
| 150 | |||
| 151 | clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6", | ||
| 152 | CLK_SET_RATE_PARENT, 1, 2); | ||
| 153 | clk_register_clkdev(clk, "pll1_12", NULL); | ||
| 154 | |||
| 155 | clk = clk_register_fixed_factor(NULL, "pll2_2", "pll2", | ||
| 156 | CLK_SET_RATE_PARENT, 1, 2); | ||
| 157 | clk_register_clkdev(clk, "pll2_2", NULL); | ||
| 158 | |||
| 159 | clk = clk_register_fixed_factor(NULL, "pll2_4", "pll2_2", | ||
| 160 | CLK_SET_RATE_PARENT, 1, 2); | ||
| 161 | clk_register_clkdev(clk, "pll2_4", NULL); | ||
| 162 | |||
| 163 | clk = clk_register_fixed_factor(NULL, "pll2_8", "pll2_4", | ||
| 164 | CLK_SET_RATE_PARENT, 1, 2); | ||
| 165 | clk_register_clkdev(clk, "pll2_8", NULL); | ||
| 166 | |||
| 167 | clk = clk_register_fixed_factor(NULL, "pll2_16", "pll2_8", | ||
| 168 | CLK_SET_RATE_PARENT, 1, 2); | ||
| 169 | clk_register_clkdev(clk, "pll2_16", NULL); | ||
| 170 | |||
| 171 | clk = clk_register_fixed_factor(NULL, "pll2_3", "pll2", | ||
| 172 | CLK_SET_RATE_PARENT, 1, 3); | ||
| 173 | clk_register_clkdev(clk, "pll2_3", NULL); | ||
| 174 | |||
| 175 | clk = clk_register_fixed_factor(NULL, "pll2_6", "pll2_3", | ||
| 176 | CLK_SET_RATE_PARENT, 1, 2); | ||
| 177 | clk_register_clkdev(clk, "pll2_6", NULL); | ||
| 178 | |||
| 179 | clk = clk_register_fixed_factor(NULL, "pll2_12", "pll2_6", | ||
| 180 | CLK_SET_RATE_PARENT, 1, 2); | ||
| 181 | clk_register_clkdev(clk, "pll2_12", NULL); | ||
| 182 | |||
| 183 | clk = clk_register_fixed_factor(NULL, "vctcxo_2", "vctcxo", | ||
| 184 | CLK_SET_RATE_PARENT, 1, 2); | ||
| 185 | clk_register_clkdev(clk, "vctcxo_2", NULL); | ||
| 186 | |||
| 187 | clk = clk_register_fixed_factor(NULL, "vctcxo_4", "vctcxo_2", | ||
| 188 | CLK_SET_RATE_PARENT, 1, 2); | ||
| 189 | clk_register_clkdev(clk, "vctcxo_4", NULL); | ||
| 190 | |||
| 191 | clk = mmp_clk_register_factor("uart_pll", "pll1_4", 0, | ||
| 192 | mpmu_base + MPMU_UART_PLL, | ||
| 193 | &uart_factor_masks, uart_factor_tbl, | ||
| 194 | ARRAY_SIZE(uart_factor_tbl)); | ||
| 195 | clk_set_rate(clk, 14745600); | ||
| 196 | clk_register_clkdev(clk, "uart_pll", NULL); | ||
| 197 | |||
| 198 | clk = mmp_clk_register_apbc("twsi0", "vctcxo", | ||
| 199 | apbc_base + APBC_TWSI0, 10, 0, &clk_lock); | ||
| 200 | clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0"); | ||
| 201 | |||
| 202 | clk = mmp_clk_register_apbc("twsi1", "vctcxo", | ||
| 203 | apbc_base + APBC_TWSI1, 10, 0, &clk_lock); | ||
| 204 | clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1"); | ||
| 205 | |||
| 206 | clk = mmp_clk_register_apbc("twsi2", "vctcxo", | ||
| 207 | apbc_base + APBC_TWSI2, 10, 0, &clk_lock); | ||
| 208 | clk_register_clkdev(clk, NULL, "pxa2xx-i2c.2"); | ||
| 209 | |||
| 210 | clk = mmp_clk_register_apbc("twsi3", "vctcxo", | ||
| 211 | apbc_base + APBC_TWSI3, 10, 0, &clk_lock); | ||
| 212 | clk_register_clkdev(clk, NULL, "pxa2xx-i2c.3"); | ||
| 213 | |||
| 214 | clk = mmp_clk_register_apbc("twsi4", "vctcxo", | ||
| 215 | apbc_base + APBC_TWSI4, 10, 0, &clk_lock); | ||
| 216 | clk_register_clkdev(clk, NULL, "pxa2xx-i2c.4"); | ||
| 217 | |||
| 218 | clk = mmp_clk_register_apbc("twsi5", "vctcxo", | ||
| 219 | apbc_base + APBC_TWSI5, 10, 0, &clk_lock); | ||
| 220 | clk_register_clkdev(clk, NULL, "pxa2xx-i2c.5"); | ||
| 221 | |||
| 222 | clk = mmp_clk_register_apbc("gpio", "vctcxo", | ||
| 223 | apbc_base + APBC_GPIO, 10, 0, &clk_lock); | ||
| 224 | clk_register_clkdev(clk, NULL, "pxa-gpio"); | ||
| 225 | |||
| 226 | clk = mmp_clk_register_apbc("kpc", "clk32", | ||
| 227 | apbc_base + APBC_KPC, 10, 0, &clk_lock); | ||
| 228 | clk_register_clkdev(clk, NULL, "pxa27x-keypad"); | ||
| 229 | |||
| 230 | clk = mmp_clk_register_apbc("rtc", "clk32", | ||
| 231 | apbc_base + APBC_RTC, 10, 0, &clk_lock); | ||
| 232 | clk_register_clkdev(clk, NULL, "mmp-rtc"); | ||
| 233 | |||
| 234 | clk = mmp_clk_register_apbc("pwm0", "vctcxo", | ||
| 235 | apbc_base + APBC_PWM0, 10, 0, &clk_lock); | ||
| 236 | clk_register_clkdev(clk, NULL, "mmp2-pwm.0"); | ||
| 237 | |||
| 238 | clk = mmp_clk_register_apbc("pwm1", "vctcxo", | ||
| 239 | apbc_base + APBC_PWM1, 10, 0, &clk_lock); | ||
| 240 | clk_register_clkdev(clk, NULL, "mmp2-pwm.1"); | ||
| 241 | |||
| 242 | clk = mmp_clk_register_apbc("pwm2", "vctcxo", | ||
| 243 | apbc_base + APBC_PWM2, 10, 0, &clk_lock); | ||
| 244 | clk_register_clkdev(clk, NULL, "mmp2-pwm.2"); | ||
| 245 | |||
| 246 | clk = mmp_clk_register_apbc("pwm3", "vctcxo", | ||
| 247 | apbc_base + APBC_PWM3, 10, 0, &clk_lock); | ||
| 248 | clk_register_clkdev(clk, NULL, "mmp2-pwm.3"); | ||
| 249 | |||
| 250 | clk = clk_register_mux(NULL, "uart0_mux", uart_parent, | ||
| 251 | ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, | ||
| 252 | apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); | ||
| 253 | clk_set_parent(clk, vctcxo); | ||
| 254 | clk_register_clkdev(clk, "uart_mux.0", NULL); | ||
| 255 | |||
| 256 | clk = mmp_clk_register_apbc("uart0", "uart0_mux", | ||
| 257 | apbc_base + APBC_UART0, 10, 0, &clk_lock); | ||
| 258 | clk_register_clkdev(clk, NULL, "pxa2xx-uart.0"); | ||
| 259 | |||
| 260 | clk = clk_register_mux(NULL, "uart1_mux", uart_parent, | ||
| 261 | ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, | ||
| 262 | apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); | ||
| 263 | clk_set_parent(clk, vctcxo); | ||
| 264 | clk_register_clkdev(clk, "uart_mux.1", NULL); | ||
| 265 | |||
| 266 | clk = mmp_clk_register_apbc("uart1", "uart1_mux", | ||
| 267 | apbc_base + APBC_UART1, 10, 0, &clk_lock); | ||
| 268 | clk_register_clkdev(clk, NULL, "pxa2xx-uart.1"); | ||
| 269 | |||
| 270 | clk = clk_register_mux(NULL, "uart2_mux", uart_parent, | ||
| 271 | ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, | ||
| 272 | apbc_base + APBC_UART2, 4, 3, 0, &clk_lock); | ||
| 273 | clk_set_parent(clk, vctcxo); | ||
| 274 | clk_register_clkdev(clk, "uart_mux.2", NULL); | ||
| 275 | |||
| 276 | clk = mmp_clk_register_apbc("uart2", "uart2_mux", | ||
| 277 | apbc_base + APBC_UART2, 10, 0, &clk_lock); | ||
| 278 | clk_register_clkdev(clk, NULL, "pxa2xx-uart.2"); | ||
| 279 | |||
| 280 | clk = clk_register_mux(NULL, "uart3_mux", uart_parent, | ||
| 281 | ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, | ||
| 282 | apbc_base + APBC_UART3, 4, 3, 0, &clk_lock); | ||
| 283 | clk_set_parent(clk, vctcxo); | ||
| 284 | clk_register_clkdev(clk, "uart_mux.3", NULL); | ||
| 285 | |||
| 286 | clk = mmp_clk_register_apbc("uart3", "uart3_mux", | ||
| 287 | apbc_base + APBC_UART3, 10, 0, &clk_lock); | ||
| 288 | clk_register_clkdev(clk, NULL, "pxa2xx-uart.3"); | ||
| 289 | |||
| 290 | clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent, | ||
| 291 | ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, | ||
| 292 | apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); | ||
| 293 | clk_register_clkdev(clk, "uart_mux.0", NULL); | ||
| 294 | |||
| 295 | clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", | ||
| 296 | apbc_base + APBC_SSP0, 10, 0, &clk_lock); | ||
| 297 | clk_register_clkdev(clk, NULL, "mmp-ssp.0"); | ||
| 298 | |||
| 299 | clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent, | ||
| 300 | ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, | ||
| 301 | apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock); | ||
| 302 | clk_register_clkdev(clk, "ssp_mux.1", NULL); | ||
| 303 | |||
| 304 | clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", | ||
| 305 | apbc_base + APBC_SSP1, 10, 0, &clk_lock); | ||
| 306 | clk_register_clkdev(clk, NULL, "mmp-ssp.1"); | ||
| 307 | |||
| 308 | clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent, | ||
| 309 | ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, | ||
| 310 | apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock); | ||
| 311 | clk_register_clkdev(clk, "ssp_mux.2", NULL); | ||
| 312 | |||
| 313 | clk = mmp_clk_register_apbc("ssp2", "ssp2_mux", | ||
| 314 | apbc_base + APBC_SSP2, 10, 0, &clk_lock); | ||
| 315 | clk_register_clkdev(clk, NULL, "mmp-ssp.2"); | ||
| 316 | |||
| 317 | clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent, | ||
| 318 | ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, | ||
| 319 | apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock); | ||
| 320 | clk_register_clkdev(clk, "ssp_mux.3", NULL); | ||
| 321 | |||
| 322 | clk = mmp_clk_register_apbc("ssp3", "ssp3_mux", | ||
| 323 | apbc_base + APBC_SSP3, 10, 0, &clk_lock); | ||
| 324 | clk_register_clkdev(clk, NULL, "mmp-ssp.3"); | ||
| 325 | |||
| 326 | clk = clk_register_mux(NULL, "sdh_mux", sdh_parent, | ||
| 327 | ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT, | ||
| 328 | apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock); | ||
| 329 | clk_register_clkdev(clk, "sdh_mux", NULL); | ||
| 330 | |||
| 331 | clk = clk_register_divider(NULL, "sdh_div", "sdh_mux", | ||
| 332 | CLK_SET_RATE_PARENT, apmu_base + APMU_SDH0, | ||
| 333 | 10, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); | ||
| 334 | clk_register_clkdev(clk, "sdh_div", NULL); | ||
| 335 | |||
| 336 | clk = mmp_clk_register_apmu("sdh0", "sdh_div", apmu_base + APMU_SDH0, | ||
| 337 | 0x1b, &clk_lock); | ||
| 338 | clk_register_clkdev(clk, NULL, "sdhci-pxav3.0"); | ||
| 339 | |||
| 340 | clk = mmp_clk_register_apmu("sdh1", "sdh_div", apmu_base + APMU_SDH1, | ||
| 341 | 0x1b, &clk_lock); | ||
| 342 | clk_register_clkdev(clk, NULL, "sdhci-pxav3.1"); | ||
| 343 | |||
| 344 | clk = mmp_clk_register_apmu("sdh2", "sdh_div", apmu_base + APMU_SDH2, | ||
| 345 | 0x1b, &clk_lock); | ||
| 346 | clk_register_clkdev(clk, NULL, "sdhci-pxav3.2"); | ||
| 347 | |||
| 348 | clk = mmp_clk_register_apmu("sdh3", "sdh_div", apmu_base + APMU_SDH3, | ||
| 349 | 0x1b, &clk_lock); | ||
| 350 | clk_register_clkdev(clk, NULL, "sdhci-pxav3.3"); | ||
| 351 | |||
| 352 | clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB, | ||
| 353 | 0x9, &clk_lock); | ||
| 354 | clk_register_clkdev(clk, "usb_clk", NULL); | ||
| 355 | |||
| 356 | clk = clk_register_mux(NULL, "disp0_mux", disp_parent, | ||
| 357 | ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT, | ||
| 358 | apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock); | ||
| 359 | clk_register_clkdev(clk, "disp_mux.0", NULL); | ||
| 360 | |||
| 361 | clk = clk_register_divider(NULL, "disp0_div", "disp0_mux", | ||
| 362 | CLK_SET_RATE_PARENT, apmu_base + APMU_DISP0, | ||
| 363 | 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); | ||
| 364 | clk_register_clkdev(clk, "disp_div.0", NULL); | ||
| 365 | |||
| 366 | clk = mmp_clk_register_apmu("disp0", "disp0_div", | ||
| 367 | apmu_base + APMU_DISP0, 0x1b, &clk_lock); | ||
| 368 | clk_register_clkdev(clk, NULL, "mmp-disp.0"); | ||
| 369 | |||
| 370 | clk = clk_register_divider(NULL, "disp0_sphy_div", "disp0_mux", 0, | ||
| 371 | apmu_base + APMU_DISP0, 15, 5, 0, &clk_lock); | ||
| 372 | clk_register_clkdev(clk, "disp_sphy_div.0", NULL); | ||
| 373 | |||
| 374 | clk = mmp_clk_register_apmu("disp0_sphy", "disp0_sphy_div", | ||
| 375 | apmu_base + APMU_DISP0, 0x1024, &clk_lock); | ||
| 376 | clk_register_clkdev(clk, "disp_sphy.0", NULL); | ||
| 377 | |||
| 378 | clk = clk_register_mux(NULL, "disp1_mux", disp_parent, | ||
| 379 | ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT, | ||
| 380 | apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock); | ||
| 381 | clk_register_clkdev(clk, "disp_mux.1", NULL); | ||
| 382 | |||
| 383 | clk = clk_register_divider(NULL, "disp1_div", "disp1_mux", | ||
| 384 | CLK_SET_RATE_PARENT, apmu_base + APMU_DISP1, | ||
| 385 | 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); | ||
| 386 | clk_register_clkdev(clk, "disp_div.1", NULL); | ||
| 387 | |||
| 388 | clk = mmp_clk_register_apmu("disp1", "disp1_div", | ||
| 389 | apmu_base + APMU_DISP1, 0x1b, &clk_lock); | ||
| 390 | clk_register_clkdev(clk, NULL, "mmp-disp.1"); | ||
| 391 | |||
| 392 | clk = mmp_clk_register_apmu("ccic_arbiter", "vctcxo", | ||
| 393 | apmu_base + APMU_CCIC0, 0x1800, &clk_lock); | ||
| 394 | clk_register_clkdev(clk, "ccic_arbiter", NULL); | ||
| 395 | |||
| 396 | clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent, | ||
| 397 | ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT, | ||
| 398 | apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock); | ||
| 399 | clk_register_clkdev(clk, "ccic_mux.0", NULL); | ||
| 400 | |||
| 401 | clk = clk_register_divider(NULL, "ccic0_div", "ccic0_mux", | ||
| 402 | CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, | ||
| 403 | 17, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); | ||
| 404 | clk_register_clkdev(clk, "ccic_div.0", NULL); | ||
| 405 | |||
| 406 | clk = mmp_clk_register_apmu("ccic0", "ccic0_div", | ||
| 407 | apmu_base + APMU_CCIC0, 0x1b, &clk_lock); | ||
| 408 | clk_register_clkdev(clk, "fnclk", "mmp-ccic.0"); | ||
| 409 | |||
| 410 | clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_div", | ||
| 411 | apmu_base + APMU_CCIC0, 0x24, &clk_lock); | ||
| 412 | clk_register_clkdev(clk, "phyclk", "mmp-ccic.0"); | ||
| 413 | |||
| 414 | clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_div", | ||
| 415 | CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, | ||
| 416 | 10, 5, 0, &clk_lock); | ||
| 417 | clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.0"); | ||
| 418 | |||
| 419 | clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div", | ||
| 420 | apmu_base + APMU_CCIC0, 0x300, &clk_lock); | ||
| 421 | clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0"); | ||
| 422 | |||
| 423 | clk = clk_register_mux(NULL, "ccic1_mux", ccic_parent, | ||
| 424 | ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT, | ||
| 425 | apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock); | ||
| 426 | clk_register_clkdev(clk, "ccic_mux.1", NULL); | ||
| 427 | |||
| 428 | clk = clk_register_divider(NULL, "ccic1_div", "ccic1_mux", | ||
| 429 | CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1, | ||
| 430 | 16, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); | ||
| 431 | clk_register_clkdev(clk, "ccic_div.1", NULL); | ||
| 432 | |||
| 433 | clk = mmp_clk_register_apmu("ccic1", "ccic1_div", | ||
| 434 | apmu_base + APMU_CCIC1, 0x1b, &clk_lock); | ||
| 435 | clk_register_clkdev(clk, "fnclk", "mmp-ccic.1"); | ||
| 436 | |||
| 437 | clk = mmp_clk_register_apmu("ccic1_phy", "ccic1_div", | ||
| 438 | apmu_base + APMU_CCIC1, 0x24, &clk_lock); | ||
| 439 | clk_register_clkdev(clk, "phyclk", "mmp-ccic.1"); | ||
| 440 | |||
| 441 | clk = clk_register_divider(NULL, "ccic1_sphy_div", "ccic1_div", | ||
| 442 | CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1, | ||
| 443 | 10, 5, 0, &clk_lock); | ||
| 444 | clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.1"); | ||
| 445 | |||
| 446 | clk = mmp_clk_register_apmu("ccic1_sphy", "ccic1_sphy_div", | ||
| 447 | apmu_base + APMU_CCIC1, 0x300, &clk_lock); | ||
| 448 | clk_register_clkdev(clk, "sphyclk", "mmp-ccic.1"); | ||
| 449 | } | ||
diff --git a/drivers/clk/mmp/clk-pxa168.c b/drivers/clk/mmp/clk-pxa168.c new file mode 100644 index 000000000000..e8d036c12cbf --- /dev/null +++ b/drivers/clk/mmp/clk-pxa168.c | |||
| @@ -0,0 +1,346 @@ | |||
| 1 | /* | ||
| 2 | * pxa168 clock framework source file | ||
| 3 | * | ||
| 4 | * Copyright (C) 2012 Marvell | ||
| 5 | * Chao Xie <xiechao.mail@gmail.com> | ||
| 6 | * | ||
| 7 | * This file is licensed under the terms of the GNU General Public | ||
| 8 | * License version 2. This program is licensed "as is" without any | ||
| 9 | * warranty of any kind, whether express or implied. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/module.h> | ||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/spinlock.h> | ||
| 15 | #include <linux/io.h> | ||
| 16 | #include <linux/delay.h> | ||
| 17 | #include <linux/err.h> | ||
| 18 | |||
| 19 | #include <mach/addr-map.h> | ||
| 20 | |||
| 21 | #include "clk.h" | ||
| 22 | |||
| 23 | #define APBC_RTC 0x28 | ||
| 24 | #define APBC_TWSI0 0x2c | ||
| 25 | #define APBC_KPC 0x30 | ||
| 26 | #define APBC_UART0 0x0 | ||
| 27 | #define APBC_UART1 0x4 | ||
| 28 | #define APBC_GPIO 0x8 | ||
| 29 | #define APBC_PWM0 0xc | ||
| 30 | #define APBC_PWM1 0x10 | ||
| 31 | #define APBC_PWM2 0x14 | ||
| 32 | #define APBC_PWM3 0x18 | ||
| 33 | #define APBC_SSP0 0x81c | ||
| 34 | #define APBC_SSP1 0x820 | ||
| 35 | #define APBC_SSP2 0x84c | ||
| 36 | #define APBC_SSP3 0x858 | ||
| 37 | #define APBC_SSP4 0x85c | ||
| 38 | #define APBC_TWSI1 0x6c | ||
| 39 | #define APBC_UART2 0x70 | ||
| 40 | #define APMU_SDH0 0x54 | ||
| 41 | #define APMU_SDH1 0x58 | ||
| 42 | #define APMU_USB 0x5c | ||
| 43 | #define APMU_DISP0 0x4c | ||
| 44 | #define APMU_CCIC0 0x50 | ||
| 45 | #define APMU_DFC 0x60 | ||
| 46 | #define MPMU_UART_PLL 0x14 | ||
| 47 | |||
| 48 | static DEFINE_SPINLOCK(clk_lock); | ||
| 49 | |||
| 50 | static struct clk_factor_masks uart_factor_masks = { | ||
| 51 | .factor = 2, | ||
| 52 | .num_mask = 0x1fff, | ||
| 53 | .den_mask = 0x1fff, | ||
| 54 | .num_shift = 16, | ||
| 55 | .den_shift = 0, | ||
| 56 | }; | ||
| 57 | |||
| 58 | static struct clk_factor_tbl uart_factor_tbl[] = { | ||
| 59 | {.num = 8125, .den = 1536}, /*14.745MHZ */ | ||
| 60 | }; | ||
| 61 | |||
| 62 | static const char *uart_parent[] = {"pll1_3_16", "uart_pll"}; | ||
| 63 | static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"}; | ||
| 64 | static const char *sdh_parent[] = {"pll1_12", "pll1_13"}; | ||
| 65 | static const char *disp_parent[] = {"pll1_2", "pll1_12"}; | ||
| 66 | static const char *ccic_parent[] = {"pll1_2", "pll1_12"}; | ||
| 67 | static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"}; | ||
| 68 | |||
| 69 | void __init pxa168_clk_init(void) | ||
| 70 | { | ||
| 71 | struct clk *clk; | ||
| 72 | struct clk *uart_pll; | ||
| 73 | void __iomem *mpmu_base; | ||
| 74 | void __iomem *apmu_base; | ||
| 75 | void __iomem *apbc_base; | ||
| 76 | |||
| 77 | mpmu_base = ioremap(APB_PHYS_BASE + 0x50000, SZ_4K); | ||
| 78 | if (mpmu_base == NULL) { | ||
| 79 | pr_err("error to ioremap MPMU base\n"); | ||
| 80 | return; | ||
| 81 | } | ||
| 82 | |||
| 83 | apmu_base = ioremap(AXI_PHYS_BASE + 0x82800, SZ_4K); | ||
| 84 | if (apmu_base == NULL) { | ||
| 85 | pr_err("error to ioremap APMU base\n"); | ||
| 86 | return; | ||
| 87 | } | ||
| 88 | |||
| 89 | apbc_base = ioremap(APB_PHYS_BASE + 0x15000, SZ_4K); | ||
| 90 | if (apbc_base == NULL) { | ||
| 91 | pr_err("error to ioremap APBC base\n"); | ||
| 92 | return; | ||
| 93 | } | ||
| 94 | |||
| 95 | clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200); | ||
| 96 | clk_register_clkdev(clk, "clk32", NULL); | ||
| 97 | |||
| 98 | clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT, | ||
| 99 | 26000000); | ||
| 100 | clk_register_clkdev(clk, "vctcxo", NULL); | ||
| 101 | |||
| 102 | clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT, | ||
| 103 | 624000000); | ||
| 104 | clk_register_clkdev(clk, "pll1", NULL); | ||
| 105 | |||
| 106 | clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", | ||
| 107 | CLK_SET_RATE_PARENT, 1, 2); | ||
| 108 | clk_register_clkdev(clk, "pll1_2", NULL); | ||
| 109 | |||
| 110 | clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2", | ||
| 111 | CLK_SET_RATE_PARENT, 1, 2); | ||
| 112 | clk_register_clkdev(clk, "pll1_4", NULL); | ||
| 113 | |||
| 114 | clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4", | ||
| 115 | CLK_SET_RATE_PARENT, 1, 2); | ||
| 116 | clk_register_clkdev(clk, "pll1_8", NULL); | ||
| 117 | |||
| 118 | clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8", | ||
| 119 | CLK_SET_RATE_PARENT, 1, 2); | ||
| 120 | clk_register_clkdev(clk, "pll1_16", NULL); | ||
| 121 | |||
| 122 | clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2", | ||
| 123 | CLK_SET_RATE_PARENT, 1, 3); | ||
| 124 | clk_register_clkdev(clk, "pll1_6", NULL); | ||
| 125 | |||
| 126 | clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6", | ||
| 127 | CLK_SET_RATE_PARENT, 1, 2); | ||
| 128 | clk_register_clkdev(clk, "pll1_12", NULL); | ||
| 129 | |||
| 130 | clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12", | ||
| 131 | CLK_SET_RATE_PARENT, 1, 2); | ||
| 132 | clk_register_clkdev(clk, "pll1_24", NULL); | ||
| 133 | |||
| 134 | clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24", | ||
| 135 | CLK_SET_RATE_PARENT, 1, 2); | ||
| 136 | clk_register_clkdev(clk, "pll1_48", NULL); | ||
| 137 | |||
| 138 | clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48", | ||
| 139 | CLK_SET_RATE_PARENT, 1, 2); | ||
| 140 | clk_register_clkdev(clk, "pll1_96", NULL); | ||
| 141 | |||
| 142 | clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1", | ||
| 143 | CLK_SET_RATE_PARENT, 1, 13); | ||
| 144 | clk_register_clkdev(clk, "pll1_13", NULL); | ||
| 145 | |||
| 146 | clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1", | ||
| 147 | CLK_SET_RATE_PARENT, 2, 3); | ||
| 148 | clk_register_clkdev(clk, "pll1_13_1_5", NULL); | ||
| 149 | |||
| 150 | clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1", | ||
| 151 | CLK_SET_RATE_PARENT, 2, 3); | ||
| 152 | clk_register_clkdev(clk, "pll1_2_1_5", NULL); | ||
| 153 | |||
| 154 | clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1", | ||
| 155 | CLK_SET_RATE_PARENT, 3, 16); | ||
| 156 | clk_register_clkdev(clk, "pll1_3_16", NULL); | ||
| 157 | |||
| 158 | uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0, | ||
| 159 | mpmu_base + MPMU_UART_PLL, | ||
| 160 | &uart_factor_masks, uart_factor_tbl, | ||
| 161 | ARRAY_SIZE(uart_factor_tbl)); | ||
| 162 | clk_set_rate(uart_pll, 14745600); | ||
| 163 | clk_register_clkdev(uart_pll, "uart_pll", NULL); | ||
| 164 | |||
| 165 | clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5", | ||
| 166 | apbc_base + APBC_TWSI0, 10, 0, &clk_lock); | ||
| 167 | clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0"); | ||
| 168 | |||
| 169 | clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5", | ||
| 170 | apbc_base + APBC_TWSI1, 10, 0, &clk_lock); | ||
| 171 | clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1"); | ||
| 172 | |||
| 173 | clk = mmp_clk_register_apbc("gpio", "vctcxo", | ||
| 174 | apbc_base + APBC_GPIO, 10, 0, &clk_lock); | ||
| 175 | clk_register_clkdev(clk, NULL, "pxa-gpio"); | ||
| 176 | |||
| 177 | clk = mmp_clk_register_apbc("kpc", "clk32", | ||
| 178 | apbc_base + APBC_KPC, 10, 0, &clk_lock); | ||
| 179 | clk_register_clkdev(clk, NULL, "pxa27x-keypad"); | ||
| 180 | |||
| 181 | clk = mmp_clk_register_apbc("rtc", "clk32", | ||
| 182 | apbc_base + APBC_RTC, 10, 0, &clk_lock); | ||
| 183 | clk_register_clkdev(clk, NULL, "sa1100-rtc"); | ||
| 184 | |||
| 185 | clk = mmp_clk_register_apbc("pwm0", "pll1_48", | ||
| 186 | apbc_base + APBC_PWM0, 10, 0, &clk_lock); | ||
| 187 | clk_register_clkdev(clk, NULL, "pxa168-pwm.0"); | ||
| 188 | |||
| 189 | clk = mmp_clk_register_apbc("pwm1", "pll1_48", | ||
| 190 | apbc_base + APBC_PWM1, 10, 0, &clk_lock); | ||
| 191 | clk_register_clkdev(clk, NULL, "pxa168-pwm.1"); | ||
| 192 | |||
| 193 | clk = mmp_clk_register_apbc("pwm2", "pll1_48", | ||
| 194 | apbc_base + APBC_PWM2, 10, 0, &clk_lock); | ||
| 195 | clk_register_clkdev(clk, NULL, "pxa168-pwm.2"); | ||
| 196 | |||
| 197 | clk = mmp_clk_register_apbc("pwm3", "pll1_48", | ||
| 198 | apbc_base + APBC_PWM3, 10, 0, &clk_lock); | ||
| 199 | clk_register_clkdev(clk, NULL, "pxa168-pwm.3"); | ||
| 200 | |||
| 201 | clk = clk_register_mux(NULL, "uart0_mux", uart_parent, | ||
| 202 | ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, | ||
| 203 | apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); | ||
| 204 | clk_set_parent(clk, uart_pll); | ||
| 205 | clk_register_clkdev(clk, "uart_mux.0", NULL); | ||
| 206 | |||
| 207 | clk = mmp_clk_register_apbc("uart0", "uart0_mux", | ||
| 208 | apbc_base + APBC_UART0, 10, 0, &clk_lock); | ||
| 209 | clk_register_clkdev(clk, NULL, "pxa2xx-uart.0"); | ||
| 210 | |||
| 211 | clk = clk_register_mux(NULL, "uart1_mux", uart_parent, | ||
| 212 | ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, | ||
| 213 | apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); | ||
| 214 | clk_set_parent(clk, uart_pll); | ||
| 215 | clk_register_clkdev(clk, "uart_mux.1", NULL); | ||
| 216 | |||
| 217 | clk = mmp_clk_register_apbc("uart1", "uart1_mux", | ||
| 218 | apbc_base + APBC_UART1, 10, 0, &clk_lock); | ||
| 219 | clk_register_clkdev(clk, NULL, "pxa2xx-uart.1"); | ||
| 220 | |||
| 221 | clk = clk_register_mux(NULL, "uart2_mux", uart_parent, | ||
| 222 | ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, | ||
| 223 | apbc_base + APBC_UART2, 4, 3, 0, &clk_lock); | ||
| 224 | clk_set_parent(clk, uart_pll); | ||
| 225 | clk_register_clkdev(clk, "uart_mux.2", NULL); | ||
| 226 | |||
| 227 | clk = mmp_clk_register_apbc("uart2", "uart2_mux", | ||
| 228 | apbc_base + APBC_UART2, 10, 0, &clk_lock); | ||
| 229 | clk_register_clkdev(clk, NULL, "pxa2xx-uart.2"); | ||
| 230 | |||
| 231 | clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent, | ||
| 232 | ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, | ||
| 233 | apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); | ||
| 234 | clk_register_clkdev(clk, "uart_mux.0", NULL); | ||
| 235 | |||
| 236 | clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", apbc_base + APBC_SSP0, | ||
| 237 | 10, 0, &clk_lock); | ||
| 238 | clk_register_clkdev(clk, NULL, "mmp-ssp.0"); | ||
| 239 | |||
| 240 | clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent, | ||
| 241 | ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, | ||
| 242 | apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock); | ||
| 243 | clk_register_clkdev(clk, "ssp_mux.1", NULL); | ||
| 244 | |||
| 245 | clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", apbc_base + APBC_SSP1, | ||
| 246 | 10, 0, &clk_lock); | ||
| 247 | clk_register_clkdev(clk, NULL, "mmp-ssp.1"); | ||
| 248 | |||
| 249 | clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent, | ||
| 250 | ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, | ||
| 251 | apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock); | ||
| 252 | clk_register_clkdev(clk, "ssp_mux.2", NULL); | ||
| 253 | |||
| 254 | clk = mmp_clk_register_apbc("ssp2", "ssp1_mux", apbc_base + APBC_SSP2, | ||
| 255 | 10, 0, &clk_lock); | ||
| 256 | clk_register_clkdev(clk, NULL, "mmp-ssp.2"); | ||
| 257 | |||
| 258 | clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent, | ||
| 259 | ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, | ||
| 260 | apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock); | ||
| 261 | clk_register_clkdev(clk, "ssp_mux.3", NULL); | ||
| 262 | |||
| 263 | clk = mmp_clk_register_apbc("ssp3", "ssp1_mux", apbc_base + APBC_SSP3, | ||
| 264 | 10, 0, &clk_lock); | ||
| 265 | clk_register_clkdev(clk, NULL, "mmp-ssp.3"); | ||
| 266 | |||
| 267 | clk = clk_register_mux(NULL, "ssp4_mux", ssp_parent, | ||
| 268 | ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, | ||
| 269 | apbc_base + APBC_SSP4, 4, 3, 0, &clk_lock); | ||
| 270 | clk_register_clkdev(clk, "ssp_mux.4", NULL); | ||
| 271 | |||
| 272 | clk = mmp_clk_register_apbc("ssp4", "ssp1_mux", apbc_base + APBC_SSP4, | ||
| 273 | 10, 0, &clk_lock); | ||
| 274 | clk_register_clkdev(clk, NULL, "mmp-ssp.4"); | ||
| 275 | |||
| 276 | clk = mmp_clk_register_apmu("dfc", "pll1_4", apmu_base + APMU_DFC, | ||
| 277 | 0x19b, &clk_lock); | ||
| 278 | clk_register_clkdev(clk, NULL, "pxa3xx-nand.0"); | ||
| 279 | |||
| 280 | clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent, | ||
| 281 | ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT, | ||
| 282 | apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock); | ||
| 283 | clk_register_clkdev(clk, "sdh0_mux", NULL); | ||
| 284 | |||
| 285 | clk = mmp_clk_register_apmu("sdh0", "sdh_mux", apmu_base + APMU_SDH0, | ||
| 286 | 0x1b, &clk_lock); | ||
| 287 | clk_register_clkdev(clk, NULL, "sdhci-pxa.0"); | ||
| 288 | |||
| 289 | clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent, | ||
| 290 | ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT, | ||
| 291 | apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock); | ||
| 292 | clk_register_clkdev(clk, "sdh1_mux", NULL); | ||
| 293 | |||
| 294 | clk = mmp_clk_register_apmu("sdh1", "sdh1_mux", apmu_base + APMU_SDH1, | ||
| 295 | 0x1b, &clk_lock); | ||
| 296 | clk_register_clkdev(clk, NULL, "sdhci-pxa.1"); | ||
| 297 | |||
| 298 | clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB, | ||
| 299 | 0x9, &clk_lock); | ||
| 300 | clk_register_clkdev(clk, "usb_clk", NULL); | ||
| 301 | |||
| 302 | clk = mmp_clk_register_apmu("sph", "usb_pll", apmu_base + APMU_USB, | ||
| 303 | 0x12, &clk_lock); | ||
| 304 | clk_register_clkdev(clk, "sph_clk", NULL); | ||
| 305 | |||
| 306 | clk = clk_register_mux(NULL, "disp0_mux", disp_parent, | ||
| 307 | ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT, | ||
| 308 | apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock); | ||
| 309 | clk_register_clkdev(clk, "disp_mux.0", NULL); | ||
| 310 | |||
| 311 | clk = mmp_clk_register_apmu("disp0", "disp0_mux", | ||
| 312 | apmu_base + APMU_DISP0, 0x1b, &clk_lock); | ||
| 313 | clk_register_clkdev(clk, "fnclk", "mmp-disp.0"); | ||
| 314 | |||
| 315 | clk = mmp_clk_register_apmu("disp0_hclk", "disp0_mux", | ||
| 316 | apmu_base + APMU_DISP0, 0x24, &clk_lock); | ||
| 317 | clk_register_clkdev(clk, "hclk", "mmp-disp.0"); | ||
| 318 | |||
| 319 | clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent, | ||
| 320 | ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT, | ||
| 321 | apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock); | ||
| 322 | clk_register_clkdev(clk, "ccic_mux.0", NULL); | ||
| 323 | |||
| 324 | clk = mmp_clk_register_apmu("ccic0", "ccic0_mux", | ||
| 325 | apmu_base + APMU_CCIC0, 0x1b, &clk_lock); | ||
| 326 | clk_register_clkdev(clk, "fnclk", "mmp-ccic.0"); | ||
| 327 | |||
| 328 | clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent, | ||
| 329 | ARRAY_SIZE(ccic_phy_parent), | ||
| 330 | CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, | ||
| 331 | 7, 1, 0, &clk_lock); | ||
| 332 | clk_register_clkdev(clk, "ccic_phy_mux.0", NULL); | ||
| 333 | |||
| 334 | clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux", | ||
| 335 | apmu_base + APMU_CCIC0, 0x24, &clk_lock); | ||
| 336 | clk_register_clkdev(clk, "phyclk", "mmp-ccic.0"); | ||
| 337 | |||
| 338 | clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux", | ||
| 339 | CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, | ||
| 340 | 10, 5, 0, &clk_lock); | ||
| 341 | clk_register_clkdev(clk, "sphyclk_div", NULL); | ||
| 342 | |||
| 343 | clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div", | ||
| 344 | apmu_base + APMU_CCIC0, 0x300, &clk_lock); | ||
| 345 | clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0"); | ||
| 346 | } | ||
diff --git a/drivers/clk/mmp/clk-pxa910.c b/drivers/clk/mmp/clk-pxa910.c new file mode 100644 index 000000000000..7048c31d6e7e --- /dev/null +++ b/drivers/clk/mmp/clk-pxa910.c | |||
| @@ -0,0 +1,320 @@ | |||
| 1 | /* | ||
| 2 | * pxa910 clock framework source file | ||
| 3 | * | ||
| 4 | * Copyright (C) 2012 Marvell | ||
| 5 | * Chao Xie <xiechao.mail@gmail.com> | ||
| 6 | * | ||
| 7 | * This file is licensed under the terms of the GNU General Public | ||
| 8 | * License version 2. This program is licensed "as is" without any | ||
| 9 | * warranty of any kind, whether express or implied. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/module.h> | ||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/spinlock.h> | ||
| 15 | #include <linux/io.h> | ||
| 16 | #include <linux/delay.h> | ||
| 17 | #include <linux/err.h> | ||
| 18 | |||
| 19 | #include <mach/addr-map.h> | ||
| 20 | |||
| 21 | #include "clk.h" | ||
| 22 | |||
| 23 | #define APBC_RTC 0x28 | ||
| 24 | #define APBC_TWSI0 0x2c | ||
| 25 | #define APBC_KPC 0x18 | ||
| 26 | #define APBC_UART0 0x0 | ||
| 27 | #define APBC_UART1 0x4 | ||
| 28 | #define APBC_GPIO 0x8 | ||
| 29 | #define APBC_PWM0 0xc | ||
| 30 | #define APBC_PWM1 0x10 | ||
| 31 | #define APBC_PWM2 0x14 | ||
| 32 | #define APBC_PWM3 0x18 | ||
| 33 | #define APBC_SSP0 0x1c | ||
| 34 | #define APBC_SSP1 0x20 | ||
| 35 | #define APBC_SSP2 0x4c | ||
| 36 | #define APBCP_TWSI1 0x28 | ||
| 37 | #define APBCP_UART2 0x1c | ||
| 38 | #define APMU_SDH0 0x54 | ||
| 39 | #define APMU_SDH1 0x58 | ||
| 40 | #define APMU_USB 0x5c | ||
| 41 | #define APMU_DISP0 0x4c | ||
| 42 | #define APMU_CCIC0 0x50 | ||
| 43 | #define APMU_DFC 0x60 | ||
| 44 | #define MPMU_UART_PLL 0x14 | ||
| 45 | |||
| 46 | static DEFINE_SPINLOCK(clk_lock); | ||
| 47 | |||
| 48 | static struct clk_factor_masks uart_factor_masks = { | ||
| 49 | .factor = 2, | ||
| 50 | .num_mask = 0x1fff, | ||
| 51 | .den_mask = 0x1fff, | ||
| 52 | .num_shift = 16, | ||
| 53 | .den_shift = 0, | ||
| 54 | }; | ||
| 55 | |||
| 56 | static struct clk_factor_tbl uart_factor_tbl[] = { | ||
| 57 | {.num = 8125, .den = 1536}, /*14.745MHZ */ | ||
| 58 | }; | ||
| 59 | |||
| 60 | static const char *uart_parent[] = {"pll1_3_16", "uart_pll"}; | ||
| 61 | static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"}; | ||
| 62 | static const char *sdh_parent[] = {"pll1_12", "pll1_13"}; | ||
| 63 | static const char *disp_parent[] = {"pll1_2", "pll1_12"}; | ||
| 64 | static const char *ccic_parent[] = {"pll1_2", "pll1_12"}; | ||
| 65 | static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"}; | ||
| 66 | |||
| 67 | void __init pxa910_clk_init(void) | ||
| 68 | { | ||
| 69 | struct clk *clk; | ||
| 70 | struct clk *uart_pll; | ||
| 71 | void __iomem *mpmu_base; | ||
| 72 | void __iomem *apmu_base; | ||
| 73 | void __iomem *apbcp_base; | ||
| 74 | void __iomem *apbc_base; | ||
| 75 | |||
| 76 | mpmu_base = ioremap(APB_PHYS_BASE + 0x50000, SZ_4K); | ||
| 77 | if (mpmu_base == NULL) { | ||
| 78 | pr_err("error to ioremap MPMU base\n"); | ||
| 79 | return; | ||
| 80 | } | ||
| 81 | |||
| 82 | apmu_base = ioremap(AXI_PHYS_BASE + 0x82800, SZ_4K); | ||
| 83 | if (apmu_base == NULL) { | ||
| 84 | pr_err("error to ioremap APMU base\n"); | ||
| 85 | return; | ||
| 86 | } | ||
| 87 | |||
| 88 | apbcp_base = ioremap(APB_PHYS_BASE + 0x3b000, SZ_4K); | ||
| 89 | if (apbcp_base == NULL) { | ||
| 90 | pr_err("error to ioremap APBC extension base\n"); | ||
| 91 | return; | ||
| 92 | } | ||
| 93 | |||
| 94 | apbc_base = ioremap(APB_PHYS_BASE + 0x15000, SZ_4K); | ||
| 95 | if (apbc_base == NULL) { | ||
| 96 | pr_err("error to ioremap APBC base\n"); | ||
| 97 | return; | ||
| 98 | } | ||
| 99 | |||
| 100 | clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200); | ||
| 101 | clk_register_clkdev(clk, "clk32", NULL); | ||
| 102 | |||
| 103 | clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT, | ||
| 104 | 26000000); | ||
| 105 | clk_register_clkdev(clk, "vctcxo", NULL); | ||
| 106 | |||
| 107 | clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT, | ||
| 108 | 624000000); | ||
| 109 | clk_register_clkdev(clk, "pll1", NULL); | ||
| 110 | |||
| 111 | clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", | ||
| 112 | CLK_SET_RATE_PARENT, 1, 2); | ||
| 113 | clk_register_clkdev(clk, "pll1_2", NULL); | ||
| 114 | |||
| 115 | clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2", | ||
| 116 | CLK_SET_RATE_PARENT, 1, 2); | ||
| 117 | clk_register_clkdev(clk, "pll1_4", NULL); | ||
| 118 | |||
| 119 | clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4", | ||
| 120 | CLK_SET_RATE_PARENT, 1, 2); | ||
| 121 | clk_register_clkdev(clk, "pll1_8", NULL); | ||
| 122 | |||
| 123 | clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8", | ||
| 124 | CLK_SET_RATE_PARENT, 1, 2); | ||
| 125 | clk_register_clkdev(clk, "pll1_16", NULL); | ||
| 126 | |||
| 127 | clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2", | ||
| 128 | CLK_SET_RATE_PARENT, 1, 3); | ||
| 129 | clk_register_clkdev(clk, "pll1_6", NULL); | ||
| 130 | |||
| 131 | clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6", | ||
| 132 | CLK_SET_RATE_PARENT, 1, 2); | ||
| 133 | clk_register_clkdev(clk, "pll1_12", NULL); | ||
| 134 | |||
| 135 | clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12", | ||
| 136 | CLK_SET_RATE_PARENT, 1, 2); | ||
| 137 | clk_register_clkdev(clk, "pll1_24", NULL); | ||
| 138 | |||
| 139 | clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24", | ||
| 140 | CLK_SET_RATE_PARENT, 1, 2); | ||
| 141 | clk_register_clkdev(clk, "pll1_48", NULL); | ||
| 142 | |||
| 143 | clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48", | ||
| 144 | CLK_SET_RATE_PARENT, 1, 2); | ||
| 145 | clk_register_clkdev(clk, "pll1_96", NULL); | ||
| 146 | |||
| 147 | clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1", | ||
| 148 | CLK_SET_RATE_PARENT, 1, 13); | ||
| 149 | clk_register_clkdev(clk, "pll1_13", NULL); | ||
| 150 | |||
| 151 | clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1", | ||
| 152 | CLK_SET_RATE_PARENT, 2, 3); | ||
| 153 | clk_register_clkdev(clk, "pll1_13_1_5", NULL); | ||
| 154 | |||
| 155 | clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1", | ||
| 156 | CLK_SET_RATE_PARENT, 2, 3); | ||
| 157 | clk_register_clkdev(clk, "pll1_2_1_5", NULL); | ||
| 158 | |||
| 159 | clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1", | ||
| 160 | CLK_SET_RATE_PARENT, 3, 16); | ||
| 161 | clk_register_clkdev(clk, "pll1_3_16", NULL); | ||
| 162 | |||
| 163 | uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0, | ||
| 164 | mpmu_base + MPMU_UART_PLL, | ||
| 165 | &uart_factor_masks, uart_factor_tbl, | ||
| 166 | ARRAY_SIZE(uart_factor_tbl)); | ||
| 167 | clk_set_rate(uart_pll, 14745600); | ||
| 168 | clk_register_clkdev(uart_pll, "uart_pll", NULL); | ||
| 169 | |||
| 170 | clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5", | ||
| 171 | apbc_base + APBC_TWSI0, 10, 0, &clk_lock); | ||
| 172 | clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0"); | ||
| 173 | |||
| 174 | clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5", | ||
| 175 | apbcp_base + APBCP_TWSI1, 10, 0, &clk_lock); | ||
| 176 | clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1"); | ||
| 177 | |||
| 178 | clk = mmp_clk_register_apbc("gpio", "vctcxo", | ||
| 179 | apbc_base + APBC_GPIO, 10, 0, &clk_lock); | ||
| 180 | clk_register_clkdev(clk, NULL, "pxa-gpio"); | ||
| 181 | |||
| 182 | clk = mmp_clk_register_apbc("kpc", "clk32", | ||
| 183 | apbc_base + APBC_KPC, 10, 0, &clk_lock); | ||
| 184 | clk_register_clkdev(clk, NULL, "pxa27x-keypad"); | ||
| 185 | |||
| 186 | clk = mmp_clk_register_apbc("rtc", "clk32", | ||
| 187 | apbc_base + APBC_RTC, 10, 0, &clk_lock); | ||
| 188 | clk_register_clkdev(clk, NULL, "sa1100-rtc"); | ||
| 189 | |||
| 190 | clk = mmp_clk_register_apbc("pwm0", "pll1_48", | ||
| 191 | apbc_base + APBC_PWM0, 10, 0, &clk_lock); | ||
| 192 | clk_register_clkdev(clk, NULL, "pxa910-pwm.0"); | ||
| 193 | |||
| 194 | clk = mmp_clk_register_apbc("pwm1", "pll1_48", | ||
| 195 | apbc_base + APBC_PWM1, 10, 0, &clk_lock); | ||
| 196 | clk_register_clkdev(clk, NULL, "pxa910-pwm.1"); | ||
| 197 | |||
| 198 | clk = mmp_clk_register_apbc("pwm2", "pll1_48", | ||
| 199 | apbc_base + APBC_PWM2, 10, 0, &clk_lock); | ||
| 200 | clk_register_clkdev(clk, NULL, "pxa910-pwm.2"); | ||
| 201 | |||
| 202 | clk = mmp_clk_register_apbc("pwm3", "pll1_48", | ||
| 203 | apbc_base + APBC_PWM3, 10, 0, &clk_lock); | ||
| 204 | clk_register_clkdev(clk, NULL, "pxa910-pwm.3"); | ||
| 205 | |||
| 206 | clk = clk_register_mux(NULL, "uart0_mux", uart_parent, | ||
| 207 | ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, | ||
| 208 | apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); | ||
| 209 | clk_set_parent(clk, uart_pll); | ||
| 210 | clk_register_clkdev(clk, "uart_mux.0", NULL); | ||
| 211 | |||
| 212 | clk = mmp_clk_register_apbc("uart0", "uart0_mux", | ||
| 213 | apbc_base + APBC_UART0, 10, 0, &clk_lock); | ||
| 214 | clk_register_clkdev(clk, NULL, "pxa2xx-uart.0"); | ||
| 215 | |||
| 216 | clk = clk_register_mux(NULL, "uart1_mux", uart_parent, | ||
| 217 | ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, | ||
| 218 | apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); | ||
| 219 | clk_set_parent(clk, uart_pll); | ||
| 220 | clk_register_clkdev(clk, "uart_mux.1", NULL); | ||
| 221 | |||
| 222 | clk = mmp_clk_register_apbc("uart1", "uart1_mux", | ||
| 223 | apbc_base + APBC_UART1, 10, 0, &clk_lock); | ||
| 224 | clk_register_clkdev(clk, NULL, "pxa2xx-uart.1"); | ||
| 225 | |||
| 226 | clk = clk_register_mux(NULL, "uart2_mux", uart_parent, | ||
| 227 | ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, | ||
| 228 | apbcp_base + APBCP_UART2, 4, 3, 0, &clk_lock); | ||
| 229 | clk_set_parent(clk, uart_pll); | ||
| 230 | clk_register_clkdev(clk, "uart_mux.2", NULL); | ||
| 231 | |||
| 232 | clk = mmp_clk_register_apbc("uart2", "uart2_mux", | ||
| 233 | apbcp_base + APBCP_UART2, 10, 0, &clk_lock); | ||
| 234 | clk_register_clkdev(clk, NULL, "pxa2xx-uart.2"); | ||
| 235 | |||
| 236 | clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent, | ||
| 237 | ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, | ||
| 238 | apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); | ||
| 239 | clk_register_clkdev(clk, "uart_mux.0", NULL); | ||
| 240 | |||
| 241 | clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", | ||
| 242 | apbc_base + APBC_SSP0, 10, 0, &clk_lock); | ||
| 243 | clk_register_clkdev(clk, NULL, "mmp-ssp.0"); | ||
| 244 | |||
| 245 | clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent, | ||
| 246 | ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, | ||
| 247 | apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock); | ||
| 248 | clk_register_clkdev(clk, "ssp_mux.1", NULL); | ||
| 249 | |||
| 250 | clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", | ||
| 251 | apbc_base + APBC_SSP1, 10, 0, &clk_lock); | ||
| 252 | clk_register_clkdev(clk, NULL, "mmp-ssp.1"); | ||
| 253 | |||
| 254 | clk = mmp_clk_register_apmu("dfc", "pll1_4", | ||
| 255 | apmu_base + APMU_DFC, 0x19b, &clk_lock); | ||
| 256 | clk_register_clkdev(clk, NULL, "pxa3xx-nand.0"); | ||
| 257 | |||
| 258 | clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent, | ||
| 259 | ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT, | ||
| 260 | apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock); | ||
| 261 | clk_register_clkdev(clk, "sdh0_mux", NULL); | ||
| 262 | |||
| 263 | clk = mmp_clk_register_apmu("sdh0", "sdh_mux", | ||
| 264 | apmu_base + APMU_SDH0, 0x1b, &clk_lock); | ||
| 265 | clk_register_clkdev(clk, NULL, "sdhci-pxa.0"); | ||
| 266 | |||
| 267 | clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent, | ||
| 268 | ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT, | ||
| 269 | apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock); | ||
| 270 | clk_register_clkdev(clk, "sdh1_mux", NULL); | ||
| 271 | |||
| 272 | clk = mmp_clk_register_apmu("sdh1", "sdh1_mux", | ||
| 273 | apmu_base + APMU_SDH1, 0x1b, &clk_lock); | ||
| 274 | clk_register_clkdev(clk, NULL, "sdhci-pxa.1"); | ||
| 275 | |||
| 276 | clk = mmp_clk_register_apmu("usb", "usb_pll", | ||
| 277 | apmu_base + APMU_USB, 0x9, &clk_lock); | ||
| 278 | clk_register_clkdev(clk, "usb_clk", NULL); | ||
| 279 | |||
| 280 | clk = mmp_clk_register_apmu("sph", "usb_pll", | ||
| 281 | apmu_base + APMU_USB, 0x12, &clk_lock); | ||
| 282 | clk_register_clkdev(clk, "sph_clk", NULL); | ||
| 283 | |||
| 284 | clk = clk_register_mux(NULL, "disp0_mux", disp_parent, | ||
| 285 | ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT, | ||
| 286 | apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock); | ||
| 287 | clk_register_clkdev(clk, "disp_mux.0", NULL); | ||
| 288 | |||
| 289 | clk = mmp_clk_register_apmu("disp0", "disp0_mux", | ||
| 290 | apmu_base + APMU_DISP0, 0x1b, &clk_lock); | ||
| 291 | clk_register_clkdev(clk, NULL, "mmp-disp.0"); | ||
| 292 | |||
| 293 | clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent, | ||
| 294 | ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT, | ||
| 295 | apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock); | ||
| 296 | clk_register_clkdev(clk, "ccic_mux.0", NULL); | ||
| 297 | |||
| 298 | clk = mmp_clk_register_apmu("ccic0", "ccic0_mux", | ||
| 299 | apmu_base + APMU_CCIC0, 0x1b, &clk_lock); | ||
| 300 | clk_register_clkdev(clk, "fnclk", "mmp-ccic.0"); | ||
| 301 | |||
| 302 | clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent, | ||
| 303 | ARRAY_SIZE(ccic_phy_parent), | ||
| 304 | CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, | ||
| 305 | 7, 1, 0, &clk_lock); | ||
| 306 | clk_register_clkdev(clk, "ccic_phy_mux.0", NULL); | ||
| 307 | |||
| 308 | clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux", | ||
| 309 | apmu_base + APMU_CCIC0, 0x24, &clk_lock); | ||
| 310 | clk_register_clkdev(clk, "phyclk", "mmp-ccic.0"); | ||
| 311 | |||
| 312 | clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux", | ||
| 313 | CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, | ||
| 314 | 10, 5, 0, &clk_lock); | ||
| 315 | clk_register_clkdev(clk, "sphyclk_div", NULL); | ||
| 316 | |||
| 317 | clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div", | ||
| 318 | apmu_base + APMU_CCIC0, 0x300, &clk_lock); | ||
| 319 | clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0"); | ||
| 320 | } | ||
diff --git a/drivers/clk/mmp/clk.h b/drivers/clk/mmp/clk.h new file mode 100644 index 000000000000..ab86dd4a416a --- /dev/null +++ b/drivers/clk/mmp/clk.h | |||
| @@ -0,0 +1,35 @@ | |||
| 1 | #ifndef __MACH_MMP_CLK_H | ||
| 2 | #define __MACH_MMP_CLK_H | ||
| 3 | |||
| 4 | #include <linux/clk-provider.h> | ||
| 5 | #include <linux/clkdev.h> | ||
| 6 | |||
| 7 | #define APBC_NO_BUS_CTRL BIT(0) | ||
| 8 | #define APBC_POWER_CTRL BIT(1) | ||
| 9 | |||
| 10 | struct clk_factor_masks { | ||
| 11 | unsigned int factor; | ||
| 12 | unsigned int num_mask; | ||
| 13 | unsigned int den_mask; | ||
| 14 | unsigned int num_shift; | ||
| 15 | unsigned int den_shift; | ||
| 16 | }; | ||
| 17 | |||
| 18 | struct clk_factor_tbl { | ||
| 19 | unsigned int num; | ||
| 20 | unsigned int den; | ||
| 21 | }; | ||
| 22 | |||
| 23 | extern struct clk *mmp_clk_register_pll2(const char *name, | ||
| 24 | const char *parent_name, unsigned long flags); | ||
| 25 | extern struct clk *mmp_clk_register_apbc(const char *name, | ||
| 26 | const char *parent_name, void __iomem *base, | ||
| 27 | unsigned int delay, unsigned int apbc_flags, spinlock_t *lock); | ||
| 28 | extern struct clk *mmp_clk_register_apmu(const char *name, | ||
| 29 | const char *parent_name, void __iomem *base, u32 enable_mask, | ||
| 30 | spinlock_t *lock); | ||
| 31 | extern struct clk *mmp_clk_register_factor(const char *name, | ||
| 32 | const char *parent_name, unsigned long flags, | ||
| 33 | void __iomem *base, struct clk_factor_masks *masks, | ||
| 34 | struct clk_factor_tbl *ftbl, unsigned int ftbl_cnt); | ||
| 35 | #endif | ||
diff --git a/drivers/clk/mxs/clk-imx23.c b/drivers/clk/mxs/clk-imx23.c index 844043ad0fe4..9f6d15546cbe 100644 --- a/drivers/clk/mxs/clk-imx23.c +++ b/drivers/clk/mxs/clk-imx23.c | |||
| @@ -14,6 +14,7 @@ | |||
| 14 | #include <linux/err.h> | 14 | #include <linux/err.h> |
| 15 | #include <linux/init.h> | 15 | #include <linux/init.h> |
| 16 | #include <linux/io.h> | 16 | #include <linux/io.h> |
| 17 | #include <linux/of.h> | ||
| 17 | #include <mach/common.h> | 18 | #include <mach/common.h> |
| 18 | #include <mach/mx23.h> | 19 | #include <mach/mx23.h> |
| 19 | #include "clk.h" | 20 | #include "clk.h" |
| @@ -71,44 +72,6 @@ static void __init clk_misc_init(void) | |||
| 71 | __mxs_setl(30 << BP_FRAC_IOFRAC, FRAC); | 72 | __mxs_setl(30 << BP_FRAC_IOFRAC, FRAC); |
| 72 | } | 73 | } |
| 73 | 74 | ||
| 74 | static struct clk_lookup uart_lookups[] = { | ||
| 75 | { .dev_id = "duart", }, | ||
| 76 | { .dev_id = "mxs-auart.0", }, | ||
| 77 | { .dev_id = "mxs-auart.1", }, | ||
| 78 | { .dev_id = "8006c000.serial", }, | ||
| 79 | { .dev_id = "8006e000.serial", }, | ||
| 80 | { .dev_id = "80070000.serial", }, | ||
| 81 | }; | ||
| 82 | |||
| 83 | static struct clk_lookup hbus_lookups[] = { | ||
| 84 | { .dev_id = "imx23-dma-apbh", }, | ||
| 85 | { .dev_id = "80004000.dma-apbh", }, | ||
| 86 | }; | ||
| 87 | |||
| 88 | static struct clk_lookup xbus_lookups[] = { | ||
| 89 | { .dev_id = "duart", .con_id = "apb_pclk"}, | ||
| 90 | { .dev_id = "80070000.serial", .con_id = "apb_pclk"}, | ||
| 91 | { .dev_id = "imx23-dma-apbx", }, | ||
| 92 | { .dev_id = "80024000.dma-apbx", }, | ||
| 93 | }; | ||
| 94 | |||
| 95 | static struct clk_lookup ssp_lookups[] = { | ||
| 96 | { .dev_id = "imx23-mmc.0", }, | ||
| 97 | { .dev_id = "imx23-mmc.1", }, | ||
| 98 | { .dev_id = "80010000.ssp", }, | ||
| 99 | { .dev_id = "80034000.ssp", }, | ||
| 100 | }; | ||
| 101 | |||
| 102 | static struct clk_lookup lcdif_lookups[] = { | ||
| 103 | { .dev_id = "imx23-fb", }, | ||
| 104 | { .dev_id = "80030000.lcdif", }, | ||
| 105 | }; | ||
| 106 | |||
| 107 | static struct clk_lookup gpmi_lookups[] = { | ||
| 108 | { .dev_id = "imx23-gpmi-nand", }, | ||
| 109 | { .dev_id = "8000c000.gpmi-nand", }, | ||
| 110 | }; | ||
| 111 | |||
| 112 | static const char *sel_pll[] __initconst = { "pll", "ref_xtal", }; | 75 | static const char *sel_pll[] __initconst = { "pll", "ref_xtal", }; |
| 113 | static const char *sel_cpu[] __initconst = { "ref_cpu", "ref_xtal", }; | 76 | static const char *sel_cpu[] __initconst = { "ref_cpu", "ref_xtal", }; |
| 114 | static const char *sel_pix[] __initconst = { "ref_pix", "ref_xtal", }; | 77 | static const char *sel_pix[] __initconst = { "ref_pix", "ref_xtal", }; |
| @@ -127,6 +90,7 @@ enum imx23_clk { | |||
| 127 | }; | 90 | }; |
| 128 | 91 | ||
| 129 | static struct clk *clks[clk_max]; | 92 | static struct clk *clks[clk_max]; |
| 93 | static struct clk_onecell_data clk_data; | ||
| 130 | 94 | ||
| 131 | static enum imx23_clk clks_init_on[] __initdata = { | 95 | static enum imx23_clk clks_init_on[] __initdata = { |
| 132 | cpu, hbus, xbus, emi, uart, | 96 | cpu, hbus, xbus, emi, uart, |
| @@ -134,6 +98,7 @@ static enum imx23_clk clks_init_on[] __initdata = { | |||
| 134 | 98 | ||
| 135 | int __init mx23_clocks_init(void) | 99 | int __init mx23_clocks_init(void) |
| 136 | { | 100 | { |
| 101 | struct device_node *np; | ||
| 137 | int i; | 102 | int i; |
| 138 | 103 | ||
| 139 | clk_misc_init(); | 104 | clk_misc_init(); |
| @@ -188,14 +153,14 @@ int __init mx23_clocks_init(void) | |||
| 188 | return PTR_ERR(clks[i]); | 153 | return PTR_ERR(clks[i]); |
| 189 | } | 154 | } |
| 190 | 155 | ||
| 156 | np = of_find_compatible_node(NULL, NULL, "fsl,imx23-clkctrl"); | ||
| 157 | if (np) { | ||
| 158 | clk_data.clks = clks; | ||
| 159 | clk_data.clk_num = ARRAY_SIZE(clks); | ||
| 160 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | ||
| 161 | } | ||
| 162 | |||
| 191 | clk_register_clkdev(clks[clk32k], NULL, "timrot"); | 163 | clk_register_clkdev(clks[clk32k], NULL, "timrot"); |
| 192 | clk_register_clkdev(clks[pwm], NULL, "80064000.pwm"); | ||
| 193 | clk_register_clkdevs(clks[hbus], hbus_lookups, ARRAY_SIZE(hbus_lookups)); | ||
| 194 | clk_register_clkdevs(clks[xbus], xbus_lookups, ARRAY_SIZE(xbus_lookups)); | ||
| 195 | clk_register_clkdevs(clks[uart], uart_lookups, ARRAY_SIZE(uart_lookups)); | ||
| 196 | clk_register_clkdevs(clks[ssp], ssp_lookups, ARRAY_SIZE(ssp_lookups)); | ||
| 197 | clk_register_clkdevs(clks[gpmi], gpmi_lookups, ARRAY_SIZE(gpmi_lookups)); | ||
| 198 | clk_register_clkdevs(clks[lcdif], lcdif_lookups, ARRAY_SIZE(lcdif_lookups)); | ||
| 199 | 164 | ||
| 200 | for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) | 165 | for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) |
| 201 | clk_prepare_enable(clks[clks_init_on[i]]); | 166 | clk_prepare_enable(clks[clks_init_on[i]]); |
diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c index e3aab67b3eb7..613e76f3758e 100644 --- a/drivers/clk/mxs/clk-imx28.c +++ b/drivers/clk/mxs/clk-imx28.c | |||
| @@ -14,6 +14,7 @@ | |||
| 14 | #include <linux/err.h> | 14 | #include <linux/err.h> |
| 15 | #include <linux/init.h> | 15 | #include <linux/init.h> |
| 16 | #include <linux/io.h> | 16 | #include <linux/io.h> |
| 17 | #include <linux/of.h> | ||
| 17 | #include <mach/common.h> | 18 | #include <mach/common.h> |
| 18 | #include <mach/mx28.h> | 19 | #include <mach/mx28.h> |
| 19 | #include "clk.h" | 20 | #include "clk.h" |
| @@ -120,90 +121,6 @@ static void __init clk_misc_init(void) | |||
| 120 | writel_relaxed(val, FRAC0); | 121 | writel_relaxed(val, FRAC0); |
| 121 | } | 122 | } |
| 122 | 123 | ||
| 123 | static struct clk_lookup uart_lookups[] = { | ||
| 124 | { .dev_id = "duart", }, | ||
| 125 | { .dev_id = "mxs-auart.0", }, | ||
| 126 | { .dev_id = "mxs-auart.1", }, | ||
| 127 | { .dev_id = "mxs-auart.2", }, | ||
| 128 | { .dev_id = "mxs-auart.3", }, | ||
| 129 | { .dev_id = "mxs-auart.4", }, | ||
| 130 | { .dev_id = "8006a000.serial", }, | ||
| 131 | { .dev_id = "8006c000.serial", }, | ||
| 132 | { .dev_id = "8006e000.serial", }, | ||
| 133 | { .dev_id = "80070000.serial", }, | ||
| 134 | { .dev_id = "80072000.serial", }, | ||
| 135 | { .dev_id = "80074000.serial", }, | ||
| 136 | }; | ||
| 137 | |||
| 138 | static struct clk_lookup hbus_lookups[] = { | ||
| 139 | { .dev_id = "imx28-dma-apbh", }, | ||
| 140 | { .dev_id = "80004000.dma-apbh", }, | ||
| 141 | }; | ||
| 142 | |||
| 143 | static struct clk_lookup xbus_lookups[] = { | ||
| 144 | { .dev_id = "duart", .con_id = "apb_pclk"}, | ||
| 145 | { .dev_id = "80074000.serial", .con_id = "apb_pclk"}, | ||
| 146 | { .dev_id = "imx28-dma-apbx", }, | ||
| 147 | { .dev_id = "80024000.dma-apbx", }, | ||
| 148 | }; | ||
| 149 | |||
| 150 | static struct clk_lookup ssp0_lookups[] = { | ||
| 151 | { .dev_id = "imx28-mmc.0", }, | ||
| 152 | { .dev_id = "80010000.ssp", }, | ||
| 153 | }; | ||
| 154 | |||
| 155 | static struct clk_lookup ssp1_lookups[] = { | ||
| 156 | { .dev_id = "imx28-mmc.1", }, | ||
| 157 | { .dev_id = "80012000.ssp", }, | ||
| 158 | }; | ||
| 159 | |||
| 160 | static struct clk_lookup ssp2_lookups[] = { | ||
| 161 | { .dev_id = "imx28-mmc.2", }, | ||
| 162 | { .dev_id = "80014000.ssp", }, | ||
| 163 | }; | ||
| 164 | |||
| 165 | static struct clk_lookup ssp3_lookups[] = { | ||
| 166 | { .dev_id = "imx28-mmc.3", }, | ||
| 167 | { .dev_id = "80016000.ssp", }, | ||
| 168 | }; | ||
| 169 | |||
| 170 | static struct clk_lookup lcdif_lookups[] = { | ||
| 171 | { .dev_id = "imx28-fb", }, | ||
| 172 | { .dev_id = "80030000.lcdif", }, | ||
| 173 | }; | ||
| 174 | |||
| 175 | static struct clk_lookup gpmi_lookups[] = { | ||
| 176 | { .dev_id = "imx28-gpmi-nand", }, | ||
| 177 | { .dev_id = "8000c000.gpmi-nand", }, | ||
| 178 | }; | ||
| 179 | |||
| 180 | static struct clk_lookup fec_lookups[] = { | ||
| 181 | { .dev_id = "imx28-fec.0", }, | ||
| 182 | { .dev_id = "imx28-fec.1", }, | ||
| 183 | { .dev_id = "800f0000.ethernet", }, | ||
| 184 | { .dev_id = "800f4000.ethernet", }, | ||
| 185 | }; | ||
| 186 | |||
| 187 | static struct clk_lookup can0_lookups[] = { | ||
| 188 | { .dev_id = "flexcan.0", }, | ||
| 189 | { .dev_id = "80032000.can", }, | ||
| 190 | }; | ||
| 191 | |||
| 192 | static struct clk_lookup can1_lookups[] = { | ||
| 193 | { .dev_id = "flexcan.1", }, | ||
| 194 | { .dev_id = "80034000.can", }, | ||
| 195 | }; | ||
| 196 | |||
| 197 | static struct clk_lookup saif0_lookups[] = { | ||
| 198 | { .dev_id = "mxs-saif.0", }, | ||
| 199 | { .dev_id = "80042000.saif", }, | ||
| 200 | }; | ||
| 201 | |||
| 202 | static struct clk_lookup saif1_lookups[] = { | ||
| 203 | { .dev_id = "mxs-saif.1", }, | ||
| 204 | { .dev_id = "80046000.saif", }, | ||
| 205 | }; | ||
| 206 | |||
| 207 | static const char *sel_cpu[] __initconst = { "ref_cpu", "ref_xtal", }; | 124 | static const char *sel_cpu[] __initconst = { "ref_cpu", "ref_xtal", }; |
| 208 | static const char *sel_io0[] __initconst = { "ref_io0", "ref_xtal", }; | 125 | static const char *sel_io0[] __initconst = { "ref_io0", "ref_xtal", }; |
| 209 | static const char *sel_io1[] __initconst = { "ref_io1", "ref_xtal", }; | 126 | static const char *sel_io1[] __initconst = { "ref_io1", "ref_xtal", }; |
| @@ -228,6 +145,7 @@ enum imx28_clk { | |||
| 228 | }; | 145 | }; |
| 229 | 146 | ||
| 230 | static struct clk *clks[clk_max]; | 147 | static struct clk *clks[clk_max]; |
| 148 | static struct clk_onecell_data clk_data; | ||
| 231 | 149 | ||
| 232 | static enum imx28_clk clks_init_on[] __initdata = { | 150 | static enum imx28_clk clks_init_on[] __initdata = { |
| 233 | cpu, hbus, xbus, emi, uart, | 151 | cpu, hbus, xbus, emi, uart, |
| @@ -235,6 +153,7 @@ static enum imx28_clk clks_init_on[] __initdata = { | |||
| 235 | 153 | ||
| 236 | int __init mx28_clocks_init(void) | 154 | int __init mx28_clocks_init(void) |
| 237 | { | 155 | { |
| 156 | struct device_node *np; | ||
| 238 | int i; | 157 | int i; |
| 239 | 158 | ||
| 240 | clk_misc_init(); | 159 | clk_misc_init(); |
| @@ -312,27 +231,15 @@ int __init mx28_clocks_init(void) | |||
| 312 | return PTR_ERR(clks[i]); | 231 | return PTR_ERR(clks[i]); |
| 313 | } | 232 | } |
| 314 | 233 | ||
| 234 | np = of_find_compatible_node(NULL, NULL, "fsl,imx28-clkctrl"); | ||
| 235 | if (np) { | ||
| 236 | clk_data.clks = clks; | ||
| 237 | clk_data.clk_num = ARRAY_SIZE(clks); | ||
| 238 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | ||
| 239 | } | ||
| 240 | |||
| 315 | clk_register_clkdev(clks[clk32k], NULL, "timrot"); | 241 | clk_register_clkdev(clks[clk32k], NULL, "timrot"); |
| 316 | clk_register_clkdev(clks[enet_out], NULL, "enet_out"); | 242 | clk_register_clkdev(clks[enet_out], NULL, "enet_out"); |
| 317 | clk_register_clkdev(clks[pwm], NULL, "80064000.pwm"); | ||
| 318 | clk_register_clkdevs(clks[hbus], hbus_lookups, ARRAY_SIZE(hbus_lookups)); | ||
| 319 | clk_register_clkdevs(clks[xbus], xbus_lookups, ARRAY_SIZE(xbus_lookups)); | ||
| 320 | clk_register_clkdevs(clks[uart], uart_lookups, ARRAY_SIZE(uart_lookups)); | ||
| 321 | clk_register_clkdevs(clks[ssp0], ssp0_lookups, ARRAY_SIZE(ssp0_lookups)); | ||
| 322 | clk_register_clkdevs(clks[ssp1], ssp1_lookups, ARRAY_SIZE(ssp1_lookups)); | ||
| 323 | clk_register_clkdevs(clks[ssp2], ssp2_lookups, ARRAY_SIZE(ssp2_lookups)); | ||
| 324 | clk_register_clkdevs(clks[ssp3], ssp3_lookups, ARRAY_SIZE(ssp3_lookups)); | ||
| 325 | clk_register_clkdevs(clks[gpmi], gpmi_lookups, ARRAY_SIZE(gpmi_lookups)); | ||
| 326 | clk_register_clkdevs(clks[saif0], saif0_lookups, ARRAY_SIZE(saif0_lookups)); | ||
| 327 | clk_register_clkdevs(clks[saif1], saif1_lookups, ARRAY_SIZE(saif1_lookups)); | ||
| 328 | clk_register_clkdevs(clks[lcdif], lcdif_lookups, ARRAY_SIZE(lcdif_lookups)); | ||
| 329 | clk_register_clkdevs(clks[fec], fec_lookups, ARRAY_SIZE(fec_lookups)); | ||
| 330 | clk_register_clkdevs(clks[can0], can0_lookups, ARRAY_SIZE(can0_lookups)); | ||
| 331 | clk_register_clkdevs(clks[can1], can1_lookups, ARRAY_SIZE(can1_lookups)); | ||
| 332 | clk_register_clkdev(clks[usb0_pwr], NULL, "8007c000.usbphy"); | ||
| 333 | clk_register_clkdev(clks[usb1_pwr], NULL, "8007e000.usbphy"); | ||
| 334 | clk_register_clkdev(clks[usb0], NULL, "80080000.usb"); | ||
| 335 | clk_register_clkdev(clks[usb1], NULL, "80090000.usb"); | ||
| 336 | 243 | ||
| 337 | for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) | 244 | for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) |
| 338 | clk_prepare_enable(clks[clks_init_on[i]]); | 245 | clk_prepare_enable(clks[clks_init_on[i]]); |
diff --git a/drivers/clk/ux500/Makefile b/drivers/clk/ux500/Makefile new file mode 100644 index 000000000000..858fbfe66281 --- /dev/null +++ b/drivers/clk/ux500/Makefile | |||
| @@ -0,0 +1,12 @@ | |||
| 1 | # | ||
| 2 | # Makefile for ux500 clocks | ||
| 3 | # | ||
| 4 | |||
| 5 | # Clock types | ||
| 6 | obj-y += clk-prcc.o | ||
| 7 | obj-y += clk-prcmu.o | ||
| 8 | |||
| 9 | # Clock definitions | ||
| 10 | obj-y += u8500_clk.o | ||
| 11 | obj-y += u9540_clk.o | ||
| 12 | obj-y += u8540_clk.o | ||
diff --git a/drivers/clk/ux500/clk-prcc.c b/drivers/clk/ux500/clk-prcc.c new file mode 100644 index 000000000000..7eee7f768355 --- /dev/null +++ b/drivers/clk/ux500/clk-prcc.c | |||
| @@ -0,0 +1,164 @@ | |||
| 1 | /* | ||
| 2 | * PRCC clock implementation for ux500 platform. | ||
| 3 | * | ||
| 4 | * Copyright (C) 2012 ST-Ericsson SA | ||
| 5 | * Author: Ulf Hansson <ulf.hansson@linaro.org> | ||
| 6 | * | ||
| 7 | * License terms: GNU General Public License (GPL) version 2 | ||
| 8 | */ | ||
| 9 | |||
| 10 | #include <linux/clk-provider.h> | ||
| 11 | #include <linux/clk-private.h> | ||
| 12 | #include <linux/slab.h> | ||
| 13 | #include <linux/io.h> | ||
| 14 | #include <linux/err.h> | ||
| 15 | #include <linux/types.h> | ||
| 16 | #include <mach/hardware.h> | ||
| 17 | |||
| 18 | #include "clk.h" | ||
| 19 | |||
| 20 | #define PRCC_PCKEN 0x000 | ||
| 21 | #define PRCC_PCKDIS 0x004 | ||
| 22 | #define PRCC_KCKEN 0x008 | ||
| 23 | #define PRCC_KCKDIS 0x00C | ||
| 24 | #define PRCC_PCKSR 0x010 | ||
| 25 | #define PRCC_KCKSR 0x014 | ||
| 26 | |||
| 27 | #define to_clk_prcc(_hw) container_of(_hw, struct clk_prcc, hw) | ||
| 28 | |||
| 29 | struct clk_prcc { | ||
| 30 | struct clk_hw hw; | ||
| 31 | void __iomem *base; | ||
| 32 | u32 cg_sel; | ||
| 33 | int is_enabled; | ||
| 34 | }; | ||
| 35 | |||
| 36 | /* PRCC clock operations. */ | ||
| 37 | |||
| 38 | static int clk_prcc_pclk_enable(struct clk_hw *hw) | ||
| 39 | { | ||
| 40 | struct clk_prcc *clk = to_clk_prcc(hw); | ||
| 41 | |||
| 42 | writel(clk->cg_sel, (clk->base + PRCC_PCKEN)); | ||
| 43 | while (!(readl(clk->base + PRCC_PCKSR) & clk->cg_sel)) | ||
| 44 | cpu_relax(); | ||
| 45 | |||
| 46 | clk->is_enabled = 1; | ||
| 47 | return 0; | ||
| 48 | } | ||
| 49 | |||
| 50 | static void clk_prcc_pclk_disable(struct clk_hw *hw) | ||
| 51 | { | ||
| 52 | struct clk_prcc *clk = to_clk_prcc(hw); | ||
| 53 | |||
| 54 | writel(clk->cg_sel, (clk->base + PRCC_PCKDIS)); | ||
| 55 | clk->is_enabled = 0; | ||
| 56 | } | ||
| 57 | |||
| 58 | static int clk_prcc_kclk_enable(struct clk_hw *hw) | ||
| 59 | { | ||
| 60 | struct clk_prcc *clk = to_clk_prcc(hw); | ||
| 61 | |||
| 62 | writel(clk->cg_sel, (clk->base + PRCC_KCKEN)); | ||
| 63 | while (!(readl(clk->base + PRCC_KCKSR) & clk->cg_sel)) | ||
| 64 | cpu_relax(); | ||
| 65 | |||
| 66 | clk->is_enabled = 1; | ||
| 67 | return 0; | ||
| 68 | } | ||
| 69 | |||
| 70 | static void clk_prcc_kclk_disable(struct clk_hw *hw) | ||
| 71 | { | ||
| 72 | struct clk_prcc *clk = to_clk_prcc(hw); | ||
| 73 | |||
| 74 | writel(clk->cg_sel, (clk->base + PRCC_KCKDIS)); | ||
| 75 | clk->is_enabled = 0; | ||
| 76 | } | ||
| 77 | |||
| 78 | static int clk_prcc_is_enabled(struct clk_hw *hw) | ||
| 79 | { | ||
| 80 | struct clk_prcc *clk = to_clk_prcc(hw); | ||
| 81 | return clk->is_enabled; | ||
| 82 | } | ||
| 83 | |||
| 84 | static struct clk_ops clk_prcc_pclk_ops = { | ||
| 85 | .enable = clk_prcc_pclk_enable, | ||
| 86 | .disable = clk_prcc_pclk_disable, | ||
| 87 | .is_enabled = clk_prcc_is_enabled, | ||
| 88 | }; | ||
| 89 | |||
| 90 | static struct clk_ops clk_prcc_kclk_ops = { | ||
| 91 | .enable = clk_prcc_kclk_enable, | ||
| 92 | .disable = clk_prcc_kclk_disable, | ||
| 93 | .is_enabled = clk_prcc_is_enabled, | ||
| 94 | }; | ||
| 95 | |||
| 96 | static struct clk *clk_reg_prcc(const char *name, | ||
| 97 | const char *parent_name, | ||
| 98 | resource_size_t phy_base, | ||
| 99 | u32 cg_sel, | ||
| 100 | unsigned long flags, | ||
| 101 | struct clk_ops *clk_prcc_ops) | ||
| 102 | { | ||
| 103 | struct clk_prcc *clk; | ||
| 104 | struct clk_init_data clk_prcc_init; | ||
| 105 | struct clk *clk_reg; | ||
| 106 | |||
| 107 | if (!name) { | ||
| 108 | pr_err("clk_prcc: %s invalid arguments passed\n", __func__); | ||
| 109 | return ERR_PTR(-EINVAL); | ||
| 110 | } | ||
| 111 | |||
| 112 | clk = kzalloc(sizeof(struct clk_prcc), GFP_KERNEL); | ||
| 113 | if (!clk) { | ||
| 114 | pr_err("clk_prcc: %s could not allocate clk\n", __func__); | ||
| 115 | return ERR_PTR(-ENOMEM); | ||
| 116 | } | ||
| 117 | |||
| 118 | clk->base = ioremap(phy_base, SZ_4K); | ||
| 119 | if (!clk->base) | ||
| 120 | goto free_clk; | ||
| 121 | |||
| 122 | clk->cg_sel = cg_sel; | ||
| 123 | clk->is_enabled = 1; | ||
| 124 | |||
| 125 | clk_prcc_init.name = name; | ||
| 126 | clk_prcc_init.ops = clk_prcc_ops; | ||
| 127 | clk_prcc_init.flags = flags; | ||
| 128 | clk_prcc_init.parent_names = (parent_name ? &parent_name : NULL); | ||
| 129 | clk_prcc_init.num_parents = (parent_name ? 1 : 0); | ||
| 130 | clk->hw.init = &clk_prcc_init; | ||
| 131 | |||
| 132 | clk_reg = clk_register(NULL, &clk->hw); | ||
| 133 | if (IS_ERR_OR_NULL(clk_reg)) | ||
| 134 | goto unmap_clk; | ||
| 135 | |||
| 136 | return clk_reg; | ||
| 137 | |||
| 138 | unmap_clk: | ||
| 139 | iounmap(clk->base); | ||
| 140 | free_clk: | ||
| 141 | kfree(clk); | ||
| 142 | pr_err("clk_prcc: %s failed to register clk\n", __func__); | ||
| 143 | return ERR_PTR(-ENOMEM); | ||
| 144 | } | ||
| 145 | |||
| 146 | struct clk *clk_reg_prcc_pclk(const char *name, | ||
| 147 | const char *parent_name, | ||
| 148 | resource_size_t phy_base, | ||
| 149 | u32 cg_sel, | ||
| 150 | unsigned long flags) | ||
| 151 | { | ||
| 152 | return clk_reg_prcc(name, parent_name, phy_base, cg_sel, flags, | ||
| 153 | &clk_prcc_pclk_ops); | ||
| 154 | } | ||
| 155 | |||
| 156 | struct clk *clk_reg_prcc_kclk(const char *name, | ||
| 157 | const char *parent_name, | ||
| 158 | resource_size_t phy_base, | ||
| 159 | u32 cg_sel, | ||
| 160 | unsigned long flags) | ||
| 161 | { | ||
| 162 | return clk_reg_prcc(name, parent_name, phy_base, cg_sel, flags, | ||
| 163 | &clk_prcc_kclk_ops); | ||
| 164 | } | ||
diff --git a/drivers/clk/ux500/clk-prcmu.c b/drivers/clk/ux500/clk-prcmu.c new file mode 100644 index 000000000000..930cdfeb47ab --- /dev/null +++ b/drivers/clk/ux500/clk-prcmu.c | |||
| @@ -0,0 +1,252 @@ | |||
| 1 | /* | ||
| 2 | * PRCMU clock implementation for ux500 platform. | ||
| 3 | * | ||
| 4 | * Copyright (C) 2012 ST-Ericsson SA | ||
| 5 | * Author: Ulf Hansson <ulf.hansson@linaro.org> | ||
| 6 | * | ||
| 7 | * License terms: GNU General Public License (GPL) version 2 | ||
| 8 | */ | ||
| 9 | |||
| 10 | #include <linux/clk-provider.h> | ||
| 11 | #include <linux/clk-private.h> | ||
| 12 | #include <linux/mfd/dbx500-prcmu.h> | ||
| 13 | #include <linux/slab.h> | ||
| 14 | #include <linux/io.h> | ||
| 15 | #include <linux/err.h> | ||
| 16 | #include "clk.h" | ||
| 17 | |||
| 18 | #define to_clk_prcmu(_hw) container_of(_hw, struct clk_prcmu, hw) | ||
| 19 | |||
| 20 | struct clk_prcmu { | ||
| 21 | struct clk_hw hw; | ||
| 22 | u8 cg_sel; | ||
| 23 | int is_enabled; | ||
| 24 | }; | ||
| 25 | |||
| 26 | /* PRCMU clock operations. */ | ||
| 27 | |||
| 28 | static int clk_prcmu_prepare(struct clk_hw *hw) | ||
| 29 | { | ||
| 30 | struct clk_prcmu *clk = to_clk_prcmu(hw); | ||
| 31 | return prcmu_request_clock(clk->cg_sel, true); | ||
| 32 | } | ||
| 33 | |||
| 34 | static void clk_prcmu_unprepare(struct clk_hw *hw) | ||
| 35 | { | ||
| 36 | struct clk_prcmu *clk = to_clk_prcmu(hw); | ||
| 37 | if (prcmu_request_clock(clk->cg_sel, false)) | ||
| 38 | pr_err("clk_prcmu: %s failed to disable %s.\n", __func__, | ||
| 39 | hw->init->name); | ||
| 40 | } | ||
| 41 | |||
| 42 | static int clk_prcmu_enable(struct clk_hw *hw) | ||
| 43 | { | ||
| 44 | struct clk_prcmu *clk = to_clk_prcmu(hw); | ||
| 45 | clk->is_enabled = 1; | ||
| 46 | return 0; | ||
| 47 | } | ||
| 48 | |||
| 49 | static void clk_prcmu_disable(struct clk_hw *hw) | ||
| 50 | { | ||
| 51 | struct clk_prcmu *clk = to_clk_prcmu(hw); | ||
| 52 | clk->is_enabled = 0; | ||
| 53 | } | ||
| 54 | |||
| 55 | static int clk_prcmu_is_enabled(struct clk_hw *hw) | ||
| 56 | { | ||
| 57 | struct clk_prcmu *clk = to_clk_prcmu(hw); | ||
| 58 | return clk->is_enabled; | ||
| 59 | } | ||
| 60 | |||
| 61 | static unsigned long clk_prcmu_recalc_rate(struct clk_hw *hw, | ||
| 62 | unsigned long parent_rate) | ||
| 63 | { | ||
| 64 | struct clk_prcmu *clk = to_clk_prcmu(hw); | ||
| 65 | return prcmu_clock_rate(clk->cg_sel); | ||
| 66 | } | ||
| 67 | |||
| 68 | static long clk_prcmu_round_rate(struct clk_hw *hw, unsigned long rate, | ||
| 69 | unsigned long *parent_rate) | ||
| 70 | { | ||
| 71 | struct clk_prcmu *clk = to_clk_prcmu(hw); | ||
| 72 | return prcmu_round_clock_rate(clk->cg_sel, rate); | ||
| 73 | } | ||
| 74 | |||
| 75 | static int clk_prcmu_set_rate(struct clk_hw *hw, unsigned long rate, | ||
| 76 | unsigned long parent_rate) | ||
| 77 | { | ||
| 78 | struct clk_prcmu *clk = to_clk_prcmu(hw); | ||
| 79 | return prcmu_set_clock_rate(clk->cg_sel, rate); | ||
| 80 | } | ||
| 81 | |||
| 82 | static int request_ape_opp100(bool enable) | ||
| 83 | { | ||
| 84 | static int reqs; | ||
| 85 | int err = 0; | ||
| 86 | |||
| 87 | if (enable) { | ||
| 88 | if (!reqs) | ||
| 89 | err = prcmu_qos_add_requirement(PRCMU_QOS_APE_OPP, | ||
| 90 | "clock", 100); | ||
| 91 | if (!err) | ||
| 92 | reqs++; | ||
| 93 | } else { | ||
| 94 | reqs--; | ||
| 95 | if (!reqs) | ||
| 96 | prcmu_qos_remove_requirement(PRCMU_QOS_APE_OPP, | ||
| 97 | "clock"); | ||
| 98 | } | ||
| 99 | return err; | ||
| 100 | } | ||
| 101 | |||
| 102 | static int clk_prcmu_opp_prepare(struct clk_hw *hw) | ||
| 103 | { | ||
| 104 | int err; | ||
| 105 | struct clk_prcmu *clk = to_clk_prcmu(hw); | ||
| 106 | |||
| 107 | err = request_ape_opp100(true); | ||
| 108 | if (err) { | ||
| 109 | pr_err("clk_prcmu: %s failed to request APE OPP100 for %s.\n", | ||
| 110 | __func__, hw->init->name); | ||
| 111 | return err; | ||
| 112 | } | ||
| 113 | |||
| 114 | err = prcmu_request_clock(clk->cg_sel, true); | ||
| 115 | if (err) | ||
| 116 | request_ape_opp100(false); | ||
| 117 | |||
| 118 | return err; | ||
| 119 | } | ||
| 120 | |||
| 121 | static void clk_prcmu_opp_unprepare(struct clk_hw *hw) | ||
| 122 | { | ||
| 123 | struct clk_prcmu *clk = to_clk_prcmu(hw); | ||
| 124 | |||
| 125 | if (prcmu_request_clock(clk->cg_sel, false)) | ||
| 126 | goto out_error; | ||
| 127 | if (request_ape_opp100(false)) | ||
| 128 | goto out_error; | ||
| 129 | return; | ||
| 130 | |||
| 131 | out_error: | ||
| 132 | pr_err("clk_prcmu: %s failed to disable %s.\n", __func__, | ||
| 133 | hw->init->name); | ||
| 134 | } | ||
| 135 | |||
| 136 | static struct clk_ops clk_prcmu_scalable_ops = { | ||
| 137 | .prepare = clk_prcmu_prepare, | ||
| 138 | .unprepare = clk_prcmu_unprepare, | ||
| 139 | .enable = clk_prcmu_enable, | ||
| 140 | .disable = clk_prcmu_disable, | ||
| 141 | .is_enabled = clk_prcmu_is_enabled, | ||
| 142 | .recalc_rate = clk_prcmu_recalc_rate, | ||
| 143 | .round_rate = clk_prcmu_round_rate, | ||
| 144 | .set_rate = clk_prcmu_set_rate, | ||
| 145 | }; | ||
| 146 | |||
| 147 | static struct clk_ops clk_prcmu_gate_ops = { | ||
| 148 | .prepare = clk_prcmu_prepare, | ||
| 149 | .unprepare = clk_prcmu_unprepare, | ||
| 150 | .enable = clk_prcmu_enable, | ||
| 151 | .disable = clk_prcmu_disable, | ||
| 152 | .is_enabled = clk_prcmu_is_enabled, | ||
| 153 | .recalc_rate = clk_prcmu_recalc_rate, | ||
| 154 | }; | ||
| 155 | |||
| 156 | static struct clk_ops clk_prcmu_rate_ops = { | ||
| 157 | .is_enabled = clk_prcmu_is_enabled, | ||
| 158 | .recalc_rate = clk_prcmu_recalc_rate, | ||
| 159 | }; | ||
| 160 | |||
| 161 | static struct clk_ops clk_prcmu_opp_gate_ops = { | ||
| 162 | .prepare = clk_prcmu_opp_prepare, | ||
| 163 | .unprepare = clk_prcmu_opp_unprepare, | ||
| 164 | .enable = clk_prcmu_enable, | ||
| 165 | .disable = clk_prcmu_disable, | ||
| 166 | .is_enabled = clk_prcmu_is_enabled, | ||
| 167 | .recalc_rate = clk_prcmu_recalc_rate, | ||
| 168 | }; | ||
| 169 | |||
| 170 | static struct clk *clk_reg_prcmu(const char *name, | ||
| 171 | const char *parent_name, | ||
| 172 | u8 cg_sel, | ||
| 173 | unsigned long rate, | ||
| 174 | unsigned long flags, | ||
| 175 | struct clk_ops *clk_prcmu_ops) | ||
| 176 | { | ||
| 177 | struct clk_prcmu *clk; | ||
| 178 | struct clk_init_data clk_prcmu_init; | ||
| 179 | struct clk *clk_reg; | ||
| 180 | |||
| 181 | if (!name) { | ||
| 182 | pr_err("clk_prcmu: %s invalid arguments passed\n", __func__); | ||
| 183 | return ERR_PTR(-EINVAL); | ||
| 184 | } | ||
| 185 | |||
| 186 | clk = kzalloc(sizeof(struct clk_prcmu), GFP_KERNEL); | ||
| 187 | if (!clk) { | ||
| 188 | pr_err("clk_prcmu: %s could not allocate clk\n", __func__); | ||
| 189 | return ERR_PTR(-ENOMEM); | ||
| 190 | } | ||
| 191 | |||
| 192 | clk->cg_sel = cg_sel; | ||
| 193 | clk->is_enabled = 1; | ||
| 194 | /* "rate" can be used for changing the initial frequency */ | ||
| 195 | if (rate) | ||
| 196 | prcmu_set_clock_rate(cg_sel, rate); | ||
| 197 | |||
| 198 | clk_prcmu_init.name = name; | ||
| 199 | clk_prcmu_init.ops = clk_prcmu_ops; | ||
| 200 | clk_prcmu_init.flags = flags; | ||
| 201 | clk_prcmu_init.parent_names = (parent_name ? &parent_name : NULL); | ||
| 202 | clk_prcmu_init.num_parents = (parent_name ? 1 : 0); | ||
| 203 | clk->hw.init = &clk_prcmu_init; | ||
| 204 | |||
| 205 | clk_reg = clk_register(NULL, &clk->hw); | ||
| 206 | if (IS_ERR_OR_NULL(clk_reg)) | ||
| 207 | goto free_clk; | ||
| 208 | |||
| 209 | return clk_reg; | ||
| 210 | |||
| 211 | free_clk: | ||
| 212 | kfree(clk); | ||
| 213 | pr_err("clk_prcmu: %s failed to register clk\n", __func__); | ||
| 214 | return ERR_PTR(-ENOMEM); | ||
| 215 | } | ||
| 216 | |||
| 217 | struct clk *clk_reg_prcmu_scalable(const char *name, | ||
| 218 | const char *parent_name, | ||
| 219 | u8 cg_sel, | ||
| 220 | unsigned long rate, | ||
| 221 | unsigned long flags) | ||
| 222 | { | ||
| 223 | return clk_reg_prcmu(name, parent_name, cg_sel, rate, flags, | ||
| 224 | &clk_prcmu_scalable_ops); | ||
| 225 | } | ||
| 226 | |||
| 227 | struct clk *clk_reg_prcmu_gate(const char *name, | ||
| 228 | const char *parent_name, | ||
| 229 | u8 cg_sel, | ||
| 230 | unsigned long flags) | ||
| 231 | { | ||
| 232 | return clk_reg_prcmu(name, parent_name, cg_sel, 0, flags, | ||
| 233 | &clk_prcmu_gate_ops); | ||
| 234 | } | ||
| 235 | |||
| 236 | struct clk *clk_reg_prcmu_rate(const char *name, | ||
| 237 | const char *parent_name, | ||
| 238 | u8 cg_sel, | ||
| 239 | unsigned long flags) | ||
| 240 | { | ||
| 241 | return clk_reg_prcmu(name, parent_name, cg_sel, 0, flags, | ||
| 242 | &clk_prcmu_rate_ops); | ||
| 243 | } | ||
| 244 | |||
| 245 | struct clk *clk_reg_prcmu_opp_gate(const char *name, | ||
| 246 | const char *parent_name, | ||
| 247 | u8 cg_sel, | ||
| 248 | unsigned long flags) | ||
| 249 | { | ||
| 250 | return clk_reg_prcmu(name, parent_name, cg_sel, 0, flags, | ||
| 251 | &clk_prcmu_opp_gate_ops); | ||
| 252 | } | ||
diff --git a/drivers/clk/ux500/clk.h b/drivers/clk/ux500/clk.h new file mode 100644 index 000000000000..836d7d16751e --- /dev/null +++ b/drivers/clk/ux500/clk.h | |||
| @@ -0,0 +1,48 @@ | |||
| 1 | /* | ||
| 2 | * Clocks for ux500 platforms | ||
| 3 | * | ||
| 4 | * Copyright (C) 2012 ST-Ericsson SA | ||
| 5 | * Author: Ulf Hansson <ulf.hansson@linaro.org> | ||
| 6 | * | ||
| 7 | * License terms: GNU General Public License (GPL) version 2 | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __UX500_CLK_H | ||
| 11 | #define __UX500_CLK_H | ||
| 12 | |||
| 13 | #include <linux/clk.h> | ||
| 14 | |||
| 15 | struct clk *clk_reg_prcc_pclk(const char *name, | ||
| 16 | const char *parent_name, | ||
| 17 | unsigned int phy_base, | ||
| 18 | u32 cg_sel, | ||
| 19 | unsigned long flags); | ||
| 20 | |||
| 21 | struct clk *clk_reg_prcc_kclk(const char *name, | ||
| 22 | const char *parent_name, | ||
| 23 | unsigned int phy_base, | ||
| 24 | u32 cg_sel, | ||
| 25 | unsigned long flags); | ||
| 26 | |||
| 27 | struct clk *clk_reg_prcmu_scalable(const char *name, | ||
| 28 | const char *parent_name, | ||
| 29 | u8 cg_sel, | ||
| 30 | unsigned long rate, | ||
| 31 | unsigned long flags); | ||
| 32 | |||
| 33 | struct clk *clk_reg_prcmu_gate(const char *name, | ||
| 34 | const char *parent_name, | ||
| 35 | u8 cg_sel, | ||
| 36 | unsigned long flags); | ||
| 37 | |||
| 38 | struct clk *clk_reg_prcmu_rate(const char *name, | ||
| 39 | const char *parent_name, | ||
| 40 | u8 cg_sel, | ||
| 41 | unsigned long flags); | ||
| 42 | |||
| 43 | struct clk *clk_reg_prcmu_opp_gate(const char *name, | ||
| 44 | const char *parent_name, | ||
| 45 | u8 cg_sel, | ||
| 46 | unsigned long flags); | ||
| 47 | |||
| 48 | #endif /* __UX500_CLK_H */ | ||
diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c new file mode 100644 index 000000000000..ca4a25ed844c --- /dev/null +++ b/drivers/clk/ux500/u8500_clk.c | |||
| @@ -0,0 +1,477 @@ | |||
| 1 | /* | ||
| 2 | * Clock definitions for u8500 platform. | ||
| 3 | * | ||
| 4 | * Copyright (C) 2012 ST-Ericsson SA | ||
| 5 | * Author: Ulf Hansson <ulf.hansson@linaro.org> | ||
| 6 | * | ||
| 7 | * License terms: GNU General Public License (GPL) version 2 | ||
| 8 | */ | ||
| 9 | |||
| 10 | #include <linux/clk.h> | ||
| 11 | #include <linux/clkdev.h> | ||
| 12 | #include <linux/clk-provider.h> | ||
| 13 | #include <linux/mfd/dbx500-prcmu.h> | ||
| 14 | #include <linux/platform_data/clk-ux500.h> | ||
| 15 | |||
| 16 | #include "clk.h" | ||
| 17 | |||
| 18 | void u8500_clk_init(void) | ||
| 19 | { | ||
| 20 | struct prcmu_fw_version *fw_version; | ||
| 21 | const char *sgaclk_parent = NULL; | ||
| 22 | struct clk *clk; | ||
| 23 | |||
| 24 | /* Clock sources */ | ||
| 25 | clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0, | ||
| 26 | CLK_IS_ROOT|CLK_IGNORE_UNUSED); | ||
| 27 | clk_register_clkdev(clk, "soc0_pll", NULL); | ||
| 28 | |||
| 29 | clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1, | ||
| 30 | CLK_IS_ROOT|CLK_IGNORE_UNUSED); | ||
| 31 | clk_register_clkdev(clk, "soc1_pll", NULL); | ||
| 32 | |||
| 33 | clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR, | ||
| 34 | CLK_IS_ROOT|CLK_IGNORE_UNUSED); | ||
| 35 | clk_register_clkdev(clk, "ddr_pll", NULL); | ||
| 36 | |||
| 37 | /* FIXME: Add sys, ulp and int clocks here. */ | ||
| 38 | |||
| 39 | clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL", | ||
| 40 | CLK_IS_ROOT|CLK_IGNORE_UNUSED, | ||
| 41 | 32768); | ||
| 42 | clk_register_clkdev(clk, "clk32k", NULL); | ||
| 43 | clk_register_clkdev(clk, NULL, "rtc-pl031"); | ||
| 44 | |||
| 45 | /* PRCMU clocks */ | ||
| 46 | fw_version = prcmu_get_fw_version(); | ||
| 47 | if (fw_version != NULL) { | ||
| 48 | switch (fw_version->project) { | ||
| 49 | case PRCMU_FW_PROJECT_U8500_C2: | ||
| 50 | case PRCMU_FW_PROJECT_U8520: | ||
| 51 | case PRCMU_FW_PROJECT_U8420: | ||
| 52 | sgaclk_parent = "soc0_pll"; | ||
| 53 | break; | ||
| 54 | default: | ||
| 55 | break; | ||
| 56 | } | ||
| 57 | } | ||
| 58 | |||
| 59 | if (sgaclk_parent) | ||
| 60 | clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent, | ||
| 61 | PRCMU_SGACLK, 0); | ||
| 62 | else | ||
| 63 | clk = clk_reg_prcmu_gate("sgclk", NULL, | ||
| 64 | PRCMU_SGACLK, CLK_IS_ROOT); | ||
| 65 | clk_register_clkdev(clk, NULL, "mali"); | ||
| 66 | |||
| 67 | clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT); | ||
| 68 | clk_register_clkdev(clk, NULL, "UART"); | ||
| 69 | |||
| 70 | clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, CLK_IS_ROOT); | ||
| 71 | clk_register_clkdev(clk, NULL, "MSP02"); | ||
| 72 | |||
| 73 | clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT); | ||
| 74 | clk_register_clkdev(clk, NULL, "MSP1"); | ||
| 75 | |||
| 76 | clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT); | ||
| 77 | clk_register_clkdev(clk, NULL, "I2C"); | ||
| 78 | |||
| 79 | clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT); | ||
| 80 | clk_register_clkdev(clk, NULL, "slim"); | ||
| 81 | |||
| 82 | clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT); | ||
| 83 | clk_register_clkdev(clk, NULL, "PERIPH1"); | ||
| 84 | |||
| 85 | clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT); | ||
| 86 | clk_register_clkdev(clk, NULL, "PERIPH2"); | ||
| 87 | |||
| 88 | clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT); | ||
| 89 | clk_register_clkdev(clk, NULL, "PERIPH3"); | ||
| 90 | |||
| 91 | clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT); | ||
| 92 | clk_register_clkdev(clk, NULL, "PERIPH5"); | ||
| 93 | |||
| 94 | clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT); | ||
| 95 | clk_register_clkdev(clk, NULL, "PERIPH6"); | ||
| 96 | |||
| 97 | clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT); | ||
| 98 | clk_register_clkdev(clk, NULL, "PERIPH7"); | ||
| 99 | |||
| 100 | clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0, | ||
| 101 | CLK_IS_ROOT|CLK_SET_RATE_GATE); | ||
| 102 | clk_register_clkdev(clk, NULL, "lcd"); | ||
| 103 | clk_register_clkdev(clk, "lcd", "mcde"); | ||
| 104 | |||
| 105 | clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, CLK_IS_ROOT); | ||
| 106 | clk_register_clkdev(clk, NULL, "bml"); | ||
| 107 | |||
| 108 | clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0, | ||
| 109 | CLK_IS_ROOT|CLK_SET_RATE_GATE); | ||
| 110 | |||
| 111 | clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0, | ||
| 112 | CLK_IS_ROOT|CLK_SET_RATE_GATE); | ||
| 113 | |||
| 114 | clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0, | ||
| 115 | CLK_IS_ROOT|CLK_SET_RATE_GATE); | ||
| 116 | clk_register_clkdev(clk, NULL, "hdmi"); | ||
| 117 | clk_register_clkdev(clk, "hdmi", "mcde"); | ||
| 118 | |||
| 119 | clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, CLK_IS_ROOT); | ||
| 120 | clk_register_clkdev(clk, NULL, "apeat"); | ||
| 121 | |||
| 122 | clk = clk_reg_prcmu_gate("apetraceclk", NULL, PRCMU_APETRACECLK, | ||
| 123 | CLK_IS_ROOT); | ||
| 124 | clk_register_clkdev(clk, NULL, "apetrace"); | ||
| 125 | |||
| 126 | clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT); | ||
| 127 | clk_register_clkdev(clk, NULL, "mcde"); | ||
| 128 | clk_register_clkdev(clk, "mcde", "mcde"); | ||
| 129 | clk_register_clkdev(clk, "dsisys", "dsilink.0"); | ||
| 130 | clk_register_clkdev(clk, "dsisys", "dsilink.1"); | ||
| 131 | clk_register_clkdev(clk, "dsisys", "dsilink.2"); | ||
| 132 | |||
| 133 | clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK, | ||
| 134 | CLK_IS_ROOT); | ||
| 135 | clk_register_clkdev(clk, NULL, "ipi2"); | ||
| 136 | |||
| 137 | clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK, | ||
| 138 | CLK_IS_ROOT); | ||
| 139 | clk_register_clkdev(clk, NULL, "dsialt"); | ||
| 140 | |||
| 141 | clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT); | ||
| 142 | clk_register_clkdev(clk, NULL, "dma40.0"); | ||
| 143 | |||
| 144 | clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT); | ||
| 145 | clk_register_clkdev(clk, NULL, "b2r2"); | ||
| 146 | clk_register_clkdev(clk, NULL, "b2r2_core"); | ||
| 147 | clk_register_clkdev(clk, NULL, "U8500-B2R2.0"); | ||
| 148 | |||
| 149 | clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0, | ||
| 150 | CLK_IS_ROOT|CLK_SET_RATE_GATE); | ||
| 151 | clk_register_clkdev(clk, NULL, "tv"); | ||
| 152 | clk_register_clkdev(clk, "tv", "mcde"); | ||
| 153 | |||
| 154 | clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT); | ||
| 155 | clk_register_clkdev(clk, NULL, "SSP"); | ||
| 156 | |||
| 157 | clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT); | ||
| 158 | clk_register_clkdev(clk, NULL, "rngclk"); | ||
| 159 | |||
| 160 | clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT); | ||
| 161 | clk_register_clkdev(clk, NULL, "uicc"); | ||
| 162 | |||
| 163 | /* | ||
| 164 | * FIXME: The MTU clocks might need some kind of "parent muxed join" | ||
| 165 | * and these have no K-clocks. For now, we ignore the missing | ||
| 166 | * connection to the corresponding P-clocks, p6_mtu0_clk and | ||
| 167 | * p6_mtu1_clk. Instead timclk is used which is the valid parent. | ||
| 168 | */ | ||
| 169 | clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT); | ||
| 170 | clk_register_clkdev(clk, NULL, "mtu0"); | ||
| 171 | clk_register_clkdev(clk, NULL, "mtu1"); | ||
| 172 | |||
| 173 | clk = clk_reg_prcmu_gate("sdmmcclk", NULL, PRCMU_SDMMCCLK, CLK_IS_ROOT); | ||
| 174 | clk_register_clkdev(clk, NULL, "sdmmc"); | ||
| 175 | |||
| 176 | |||
| 177 | clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk", | ||
| 178 | PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE); | ||
| 179 | clk_register_clkdev(clk, "dsihs2", "mcde"); | ||
| 180 | clk_register_clkdev(clk, "dsihs2", "dsilink.2"); | ||
| 181 | |||
| 182 | |||
| 183 | clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll", | ||
| 184 | PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE); | ||
| 185 | clk_register_clkdev(clk, "dsihs0", "mcde"); | ||
| 186 | clk_register_clkdev(clk, "dsihs0", "dsilink.0"); | ||
| 187 | |||
| 188 | clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll", | ||
| 189 | PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE); | ||
| 190 | clk_register_clkdev(clk, "dsihs1", "mcde"); | ||
| 191 | clk_register_clkdev(clk, "dsihs1", "dsilink.1"); | ||
| 192 | |||
| 193 | clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk", | ||
| 194 | PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE); | ||
| 195 | clk_register_clkdev(clk, "dsilp0", "dsilink.0"); | ||
| 196 | clk_register_clkdev(clk, "dsilp0", "mcde"); | ||
| 197 | |||
| 198 | clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk", | ||
| 199 | PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE); | ||
| 200 | clk_register_clkdev(clk, "dsilp1", "dsilink.1"); | ||
| 201 | clk_register_clkdev(clk, "dsilp1", "mcde"); | ||
| 202 | |||
| 203 | clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk", | ||
| 204 | PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE); | ||
| 205 | clk_register_clkdev(clk, "dsilp2", "dsilink.2"); | ||
| 206 | clk_register_clkdev(clk, "dsilp2", "mcde"); | ||
| 207 | |||
| 208 | clk = clk_reg_prcmu_rate("smp_twd", NULL, PRCMU_ARMSS, | ||
| 209 | CLK_IS_ROOT|CLK_GET_RATE_NOCACHE| | ||
| 210 | CLK_IGNORE_UNUSED); | ||
| 211 | clk_register_clkdev(clk, NULL, "smp_twd"); | ||
| 212 | |||
| 213 | /* | ||
| 214 | * FIXME: Add special handled PRCMU clocks here: | ||
| 215 | * 1. clk_arm, use PRCMU_ARMCLK. | ||
| 216 | * 2. clkout0yuv, use PRCMU as parent + need regulator + pinctrl. | ||
| 217 | * 3. ab9540_clkout1yuv, see clkout0yuv | ||
| 218 | */ | ||
| 219 | |||
| 220 | /* PRCC P-clocks */ | ||
| 221 | clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", U8500_CLKRST1_BASE, | ||
| 222 | BIT(0), 0); | ||
| 223 | clk_register_clkdev(clk, "apb_pclk", "uart0"); | ||
| 224 | |||
| 225 | clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", U8500_CLKRST1_BASE, | ||
| 226 | BIT(1), 0); | ||
| 227 | clk_register_clkdev(clk, "apb_pclk", "uart1"); | ||
| 228 | |||
| 229 | clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", U8500_CLKRST1_BASE, | ||
| 230 | BIT(2), 0); | ||
| 231 | clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", U8500_CLKRST1_BASE, | ||
| 232 | BIT(3), 0); | ||
| 233 | clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", U8500_CLKRST1_BASE, | ||
| 234 | BIT(4), 0); | ||
| 235 | |||
| 236 | clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", U8500_CLKRST1_BASE, | ||
| 237 | BIT(5), 0); | ||
| 238 | clk_register_clkdev(clk, "apb_pclk", "sdi0"); | ||
| 239 | |||
| 240 | clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", U8500_CLKRST1_BASE, | ||
| 241 | BIT(6), 0); | ||
| 242 | |||
| 243 | clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", U8500_CLKRST1_BASE, | ||
| 244 | BIT(7), 0); | ||
| 245 | clk_register_clkdev(clk, NULL, "spi3"); | ||
| 246 | |||
| 247 | clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", U8500_CLKRST1_BASE, | ||
| 248 | BIT(8), 0); | ||
| 249 | |||
| 250 | clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", U8500_CLKRST1_BASE, | ||
| 251 | BIT(9), 0); | ||
| 252 | clk_register_clkdev(clk, NULL, "gpio.0"); | ||
| 253 | clk_register_clkdev(clk, NULL, "gpio.1"); | ||
| 254 | clk_register_clkdev(clk, NULL, "gpioblock0"); | ||
| 255 | |||
| 256 | clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", U8500_CLKRST1_BASE, | ||
| 257 | BIT(10), 0); | ||
| 258 | clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", U8500_CLKRST1_BASE, | ||
| 259 | BIT(11), 0); | ||
| 260 | |||
| 261 | clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", U8500_CLKRST2_BASE, | ||
| 262 | BIT(0), 0); | ||
| 263 | |||
| 264 | clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", U8500_CLKRST2_BASE, | ||
| 265 | BIT(1), 0); | ||
| 266 | clk_register_clkdev(clk, NULL, "spi2"); | ||
| 267 | |||
| 268 | clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", U8500_CLKRST2_BASE, | ||
| 269 | BIT(2), 0); | ||
| 270 | clk_register_clkdev(clk, NULL, "spi1"); | ||
| 271 | |||
| 272 | clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", U8500_CLKRST2_BASE, | ||
| 273 | BIT(3), 0); | ||
| 274 | clk_register_clkdev(clk, NULL, "pwl"); | ||
| 275 | |||
| 276 | clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", U8500_CLKRST2_BASE, | ||
| 277 | BIT(4), 0); | ||
| 278 | clk_register_clkdev(clk, "apb_pclk", "sdi4"); | ||
| 279 | |||
| 280 | clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", U8500_CLKRST2_BASE, | ||
| 281 | BIT(5), 0); | ||
| 282 | |||
| 283 | clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", U8500_CLKRST2_BASE, | ||
| 284 | BIT(6), 0); | ||
| 285 | clk_register_clkdev(clk, "apb_pclk", "sdi1"); | ||
| 286 | |||
| 287 | |||
| 288 | clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", U8500_CLKRST2_BASE, | ||
| 289 | BIT(7), 0); | ||
| 290 | clk_register_clkdev(clk, "apb_pclk", "sdi3"); | ||
| 291 | |||
| 292 | clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", U8500_CLKRST2_BASE, | ||
| 293 | BIT(8), 0); | ||
| 294 | clk_register_clkdev(clk, NULL, "spi0"); | ||
| 295 | |||
| 296 | clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", U8500_CLKRST2_BASE, | ||
| 297 | BIT(9), 0); | ||
| 298 | clk_register_clkdev(clk, "hsir_hclk", "ste_hsi.0"); | ||
| 299 | |||
| 300 | clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", U8500_CLKRST2_BASE, | ||
| 301 | BIT(10), 0); | ||
| 302 | clk_register_clkdev(clk, "hsit_hclk", "ste_hsi.0"); | ||
| 303 | |||
| 304 | clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", U8500_CLKRST2_BASE, | ||
| 305 | BIT(11), 0); | ||
| 306 | clk_register_clkdev(clk, NULL, "gpio.6"); | ||
| 307 | clk_register_clkdev(clk, NULL, "gpio.7"); | ||
| 308 | clk_register_clkdev(clk, NULL, "gpioblock1"); | ||
| 309 | |||
| 310 | clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", U8500_CLKRST2_BASE, | ||
| 311 | BIT(11), 0); | ||
| 312 | |||
| 313 | clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", U8500_CLKRST3_BASE, | ||
| 314 | BIT(0), 0); | ||
| 315 | clk_register_clkdev(clk, NULL, "fsmc"); | ||
| 316 | |||
| 317 | clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", U8500_CLKRST3_BASE, | ||
| 318 | BIT(1), 0); | ||
| 319 | clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", U8500_CLKRST3_BASE, | ||
| 320 | BIT(2), 0); | ||
| 321 | clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", U8500_CLKRST3_BASE, | ||
| 322 | BIT(3), 0); | ||
| 323 | |||
| 324 | clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", U8500_CLKRST3_BASE, | ||
| 325 | BIT(4), 0); | ||
| 326 | clk_register_clkdev(clk, "apb_pclk", "sdi2"); | ||
| 327 | |||
| 328 | clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", U8500_CLKRST3_BASE, | ||
| 329 | BIT(5), 0); | ||
| 330 | |||
| 331 | clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", U8500_CLKRST3_BASE, | ||
| 332 | BIT(6), 0); | ||
| 333 | clk_register_clkdev(clk, "apb_pclk", "uart2"); | ||
| 334 | |||
| 335 | clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", U8500_CLKRST3_BASE, | ||
| 336 | BIT(7), 0); | ||
| 337 | clk_register_clkdev(clk, "apb_pclk", "sdi5"); | ||
| 338 | |||
| 339 | clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", U8500_CLKRST3_BASE, | ||
| 340 | BIT(8), 0); | ||
| 341 | clk_register_clkdev(clk, NULL, "gpio.2"); | ||
| 342 | clk_register_clkdev(clk, NULL, "gpio.3"); | ||
| 343 | clk_register_clkdev(clk, NULL, "gpio.4"); | ||
| 344 | clk_register_clkdev(clk, NULL, "gpio.5"); | ||
| 345 | clk_register_clkdev(clk, NULL, "gpioblock2"); | ||
| 346 | |||
| 347 | clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", U8500_CLKRST5_BASE, | ||
| 348 | BIT(0), 0); | ||
| 349 | clk_register_clkdev(clk, "usb", "musb-ux500.0"); | ||
| 350 | |||
| 351 | clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", U8500_CLKRST5_BASE, | ||
| 352 | BIT(1), 0); | ||
| 353 | clk_register_clkdev(clk, NULL, "gpio.8"); | ||
| 354 | clk_register_clkdev(clk, NULL, "gpioblock3"); | ||
| 355 | |||
| 356 | clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", U8500_CLKRST6_BASE, | ||
| 357 | BIT(0), 0); | ||
| 358 | |||
| 359 | clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", U8500_CLKRST6_BASE, | ||
| 360 | BIT(1), 0); | ||
| 361 | clk_register_clkdev(clk, NULL, "cryp0"); | ||
| 362 | clk_register_clkdev(clk, NULL, "cryp1"); | ||
| 363 | |||
| 364 | clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", U8500_CLKRST6_BASE, | ||
| 365 | BIT(2), 0); | ||
| 366 | clk_register_clkdev(clk, NULL, "hash0"); | ||
| 367 | |||
| 368 | clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", U8500_CLKRST6_BASE, | ||
| 369 | BIT(3), 0); | ||
| 370 | clk_register_clkdev(clk, NULL, "pka"); | ||
| 371 | |||
| 372 | clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", U8500_CLKRST6_BASE, | ||
| 373 | BIT(4), 0); | ||
| 374 | clk_register_clkdev(clk, NULL, "hash1"); | ||
| 375 | |||
| 376 | clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", U8500_CLKRST6_BASE, | ||
| 377 | BIT(5), 0); | ||
| 378 | clk_register_clkdev(clk, NULL, "cfgreg"); | ||
| 379 | |||
| 380 | clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", U8500_CLKRST6_BASE, | ||
| 381 | BIT(6), 0); | ||
| 382 | clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", U8500_CLKRST6_BASE, | ||
| 383 | BIT(7), 0); | ||
| 384 | |||
| 385 | /* PRCC K-clocks | ||
| 386 | * | ||
| 387 | * FIXME: Some drivers requires PERPIH[n| to be automatically enabled | ||
| 388 | * by enabling just the K-clock, even if it is not a valid parent to | ||
| 389 | * the K-clock. Until drivers get fixed we might need some kind of | ||
| 390 | * "parent muxed join". | ||
| 391 | */ | ||
| 392 | |||
| 393 | /* Periph1 */ | ||
| 394 | clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk", | ||
| 395 | U8500_CLKRST1_BASE, BIT(0), CLK_SET_RATE_GATE); | ||
| 396 | clk_register_clkdev(clk, NULL, "uart0"); | ||
| 397 | |||
| 398 | clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk", | ||
| 399 | U8500_CLKRST1_BASE, BIT(1), CLK_SET_RATE_GATE); | ||
| 400 | clk_register_clkdev(clk, NULL, "uart1"); | ||
| 401 | |||
| 402 | clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk", | ||
| 403 | U8500_CLKRST1_BASE, BIT(2), CLK_SET_RATE_GATE); | ||
| 404 | clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk", | ||
| 405 | U8500_CLKRST1_BASE, BIT(3), CLK_SET_RATE_GATE); | ||
| 406 | clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk", | ||
| 407 | U8500_CLKRST1_BASE, BIT(4), CLK_SET_RATE_GATE); | ||
| 408 | |||
| 409 | clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk", | ||
| 410 | U8500_CLKRST1_BASE, BIT(5), CLK_SET_RATE_GATE); | ||
| 411 | clk_register_clkdev(clk, NULL, "sdi0"); | ||
| 412 | |||
| 413 | clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk", | ||
| 414 | U8500_CLKRST1_BASE, BIT(6), CLK_SET_RATE_GATE); | ||
| 415 | clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk", | ||
| 416 | U8500_CLKRST1_BASE, BIT(3), CLK_SET_RATE_GATE); | ||
| 417 | /* FIXME: Redefinition of BIT(3). */ | ||
| 418 | clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk", | ||
| 419 | U8500_CLKRST1_BASE, BIT(9), CLK_SET_RATE_GATE); | ||
| 420 | clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk", | ||
| 421 | U8500_CLKRST1_BASE, BIT(10), CLK_SET_RATE_GATE); | ||
| 422 | |||
| 423 | /* Periph2 */ | ||
| 424 | clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk", | ||
| 425 | U8500_CLKRST2_BASE, BIT(0), CLK_SET_RATE_GATE); | ||
| 426 | |||
| 427 | clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk", | ||
| 428 | U8500_CLKRST2_BASE, BIT(2), CLK_SET_RATE_GATE); | ||
| 429 | clk_register_clkdev(clk, NULL, "sdi4"); | ||
| 430 | |||
| 431 | clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk", | ||
| 432 | U8500_CLKRST2_BASE, BIT(3), CLK_SET_RATE_GATE); | ||
| 433 | |||
| 434 | clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk", | ||
| 435 | U8500_CLKRST2_BASE, BIT(4), CLK_SET_RATE_GATE); | ||
| 436 | clk_register_clkdev(clk, NULL, "sdi1"); | ||
| 437 | |||
| 438 | clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk", | ||
| 439 | U8500_CLKRST2_BASE, BIT(5), CLK_SET_RATE_GATE); | ||
| 440 | clk_register_clkdev(clk, NULL, "sdi3"); | ||
| 441 | |||
| 442 | /* Note that rate is received from parent. */ | ||
| 443 | clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk", | ||
| 444 | U8500_CLKRST2_BASE, BIT(6), | ||
| 445 | CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); | ||
| 446 | clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk", | ||
| 447 | U8500_CLKRST2_BASE, BIT(7), | ||
| 448 | CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); | ||
| 449 | |||
| 450 | /* Periph3 */ | ||
| 451 | clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk", | ||
| 452 | U8500_CLKRST3_BASE, BIT(1), CLK_SET_RATE_GATE); | ||
| 453 | clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk", | ||
| 454 | U8500_CLKRST3_BASE, BIT(2), CLK_SET_RATE_GATE); | ||
| 455 | clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk", | ||
| 456 | U8500_CLKRST3_BASE, BIT(3), CLK_SET_RATE_GATE); | ||
| 457 | |||
| 458 | clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk", | ||
| 459 | U8500_CLKRST3_BASE, BIT(4), CLK_SET_RATE_GATE); | ||
| 460 | clk_register_clkdev(clk, NULL, "sdi2"); | ||
| 461 | |||
| 462 | clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k", | ||
| 463 | U8500_CLKRST3_BASE, BIT(5), CLK_SET_RATE_GATE); | ||
| 464 | |||
| 465 | clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk", | ||
| 466 | U8500_CLKRST3_BASE, BIT(6), CLK_SET_RATE_GATE); | ||
| 467 | clk_register_clkdev(clk, NULL, "uart2"); | ||
| 468 | |||
| 469 | clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk", | ||
| 470 | U8500_CLKRST3_BASE, BIT(7), CLK_SET_RATE_GATE); | ||
| 471 | clk_register_clkdev(clk, NULL, "sdi5"); | ||
| 472 | |||
| 473 | /* Periph6 */ | ||
| 474 | clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk", | ||
| 475 | U8500_CLKRST6_BASE, BIT(0), CLK_SET_RATE_GATE); | ||
| 476 | |||
| 477 | } | ||
diff --git a/drivers/clk/ux500/u8540_clk.c b/drivers/clk/ux500/u8540_clk.c new file mode 100644 index 000000000000..10adfd2ead21 --- /dev/null +++ b/drivers/clk/ux500/u8540_clk.c | |||
| @@ -0,0 +1,21 @@ | |||
| 1 | /* | ||
| 2 | * Clock definitions for u8540 platform. | ||
| 3 | * | ||
| 4 | * Copyright (C) 2012 ST-Ericsson SA | ||
| 5 | * Author: Ulf Hansson <ulf.hansson@linaro.org> | ||
| 6 | * | ||
| 7 | * License terms: GNU General Public License (GPL) version 2 | ||
| 8 | */ | ||
| 9 | |||
| 10 | #include <linux/clk.h> | ||
| 11 | #include <linux/clkdev.h> | ||
| 12 | #include <linux/clk-provider.h> | ||
| 13 | #include <linux/mfd/dbx500-prcmu.h> | ||
| 14 | #include <linux/platform_data/clk-ux500.h> | ||
| 15 | |||
| 16 | #include "clk.h" | ||
| 17 | |||
| 18 | void u8540_clk_init(void) | ||
| 19 | { | ||
| 20 | /* register clocks here */ | ||
| 21 | } | ||
diff --git a/drivers/clk/ux500/u9540_clk.c b/drivers/clk/ux500/u9540_clk.c new file mode 100644 index 000000000000..dbc0191e16c8 --- /dev/null +++ b/drivers/clk/ux500/u9540_clk.c | |||
| @@ -0,0 +1,21 @@ | |||
| 1 | /* | ||
| 2 | * Clock definitions for u9540 platform. | ||
| 3 | * | ||
| 4 | * Copyright (C) 2012 ST-Ericsson SA | ||
| 5 | * Author: Ulf Hansson <ulf.hansson@linaro.org> | ||
| 6 | * | ||
| 7 | * License terms: GNU General Public License (GPL) version 2 | ||
| 8 | */ | ||
| 9 | |||
| 10 | #include <linux/clk.h> | ||
| 11 | #include <linux/clkdev.h> | ||
| 12 | #include <linux/clk-provider.h> | ||
| 13 | #include <linux/mfd/dbx500-prcmu.h> | ||
| 14 | #include <linux/platform_data/clk-ux500.h> | ||
| 15 | |||
| 16 | #include "clk.h" | ||
| 17 | |||
| 18 | void u9540_clk_init(void) | ||
| 19 | { | ||
| 20 | /* register clocks here */ | ||
| 21 | } | ||
diff --git a/drivers/clk/versatile/Makefile b/drivers/clk/versatile/Makefile index 50cf6a2ee693..c0a0f6478798 100644 --- a/drivers/clk/versatile/Makefile +++ b/drivers/clk/versatile/Makefile | |||
| @@ -1,3 +1,4 @@ | |||
| 1 | # Makefile for Versatile-specific clocks | 1 | # Makefile for Versatile-specific clocks |
| 2 | obj-$(CONFIG_ICST) += clk-icst.o | 2 | obj-$(CONFIG_ICST) += clk-icst.o |
| 3 | obj-$(CONFIG_ARCH_INTEGRATOR) += clk-integrator.o | 3 | obj-$(CONFIG_ARCH_INTEGRATOR) += clk-integrator.o |
| 4 | obj-$(CONFIG_ARCH_REALVIEW) += clk-realview.o | ||
diff --git a/drivers/clk/versatile/clk-realview.c b/drivers/clk/versatile/clk-realview.c new file mode 100644 index 000000000000..e21a99cef378 --- /dev/null +++ b/drivers/clk/versatile/clk-realview.c | |||
| @@ -0,0 +1,114 @@ | |||
| 1 | #include <linux/clk.h> | ||
| 2 | #include <linux/clkdev.h> | ||
| 3 | #include <linux/err.h> | ||
| 4 | #include <linux/io.h> | ||
| 5 | #include <linux/clk-provider.h> | ||
| 6 | |||
| 7 | #include <mach/hardware.h> | ||
| 8 | #include <mach/platform.h> | ||
| 9 | |||
| 10 | #include "clk-icst.h" | ||
| 11 | |||
| 12 | /* | ||
| 13 | * Implementation of the ARM RealView clock trees. | ||
| 14 | */ | ||
| 15 | |||
| 16 | static void __iomem *sys_lock; | ||
| 17 | static void __iomem *sys_vcoreg; | ||
| 18 | |||
| 19 | /** | ||
| 20 | * realview_oscvco_get() - get ICST OSC settings for the RealView | ||
| 21 | */ | ||
| 22 | static struct icst_vco realview_oscvco_get(void) | ||
| 23 | { | ||
| 24 | u32 val; | ||
| 25 | struct icst_vco vco; | ||
| 26 | |||
| 27 | val = readl(sys_vcoreg); | ||
| 28 | vco.v = val & 0x1ff; | ||
| 29 | vco.r = (val >> 9) & 0x7f; | ||
| 30 | vco.s = (val >> 16) & 03; | ||
| 31 | return vco; | ||
| 32 | } | ||
| 33 | |||
| 34 | static void realview_oscvco_set(struct icst_vco vco) | ||
| 35 | { | ||
| 36 | u32 val; | ||
| 37 | |||
| 38 | val = readl(sys_vcoreg) & ~0x7ffff; | ||
| 39 | val |= vco.v | (vco.r << 9) | (vco.s << 16); | ||
| 40 | |||
| 41 | /* This magic unlocks the CM VCO so it can be controlled */ | ||
| 42 | writel(0xa05f, sys_lock); | ||
| 43 | writel(val, sys_vcoreg); | ||
| 44 | /* This locks the CM again */ | ||
| 45 | writel(0, sys_lock); | ||
| 46 | } | ||
| 47 | |||
| 48 | static const struct icst_params realview_oscvco_params = { | ||
| 49 | .ref = 24000000, | ||
| 50 | .vco_max = ICST307_VCO_MAX, | ||
| 51 | .vco_min = ICST307_VCO_MIN, | ||
| 52 | .vd_min = 4 + 8, | ||
| 53 | .vd_max = 511 + 8, | ||
| 54 | .rd_min = 1 + 2, | ||
| 55 | .rd_max = 127 + 2, | ||
| 56 | .s2div = icst307_s2div, | ||
| 57 | .idx2s = icst307_idx2s, | ||
| 58 | }; | ||
| 59 | |||
| 60 | static const struct clk_icst_desc __initdata realview_icst_desc = { | ||
| 61 | .params = &realview_oscvco_params, | ||
| 62 | .getvco = realview_oscvco_get, | ||
| 63 | .setvco = realview_oscvco_set, | ||
| 64 | }; | ||
| 65 | |||
| 66 | /* | ||
| 67 | * realview_clk_init() - set up the RealView clock tree | ||
| 68 | */ | ||
| 69 | void __init realview_clk_init(void __iomem *sysbase, bool is_pb1176) | ||
| 70 | { | ||
| 71 | struct clk *clk; | ||
| 72 | |||
| 73 | sys_lock = sysbase + REALVIEW_SYS_LOCK_OFFSET; | ||
| 74 | if (is_pb1176) | ||
| 75 | sys_vcoreg = sysbase + REALVIEW_SYS_OSC0_OFFSET; | ||
| 76 | else | ||
| 77 | sys_vcoreg = sysbase + REALVIEW_SYS_OSC4_OFFSET; | ||
| 78 | |||
| 79 | |||
| 80 | /* APB clock dummy */ | ||
| 81 | clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0); | ||
| 82 | clk_register_clkdev(clk, "apb_pclk", NULL); | ||
| 83 | |||
| 84 | /* 24 MHz clock */ | ||
| 85 | clk = clk_register_fixed_rate(NULL, "clk24mhz", NULL, CLK_IS_ROOT, | ||
| 86 | 24000000); | ||
| 87 | clk_register_clkdev(clk, NULL, "dev:uart0"); | ||
| 88 | clk_register_clkdev(clk, NULL, "dev:uart1"); | ||
| 89 | clk_register_clkdev(clk, NULL, "dev:uart2"); | ||
| 90 | clk_register_clkdev(clk, NULL, "fpga:kmi0"); | ||
| 91 | clk_register_clkdev(clk, NULL, "fpga:kmi1"); | ||
| 92 | clk_register_clkdev(clk, NULL, "fpga:mmc0"); | ||
| 93 | clk_register_clkdev(clk, NULL, "dev:ssp0"); | ||
| 94 | if (is_pb1176) { | ||
| 95 | /* | ||
| 96 | * UART3 is on the dev chip in PB1176 | ||
| 97 | * UART4 only exists in PB1176 | ||
| 98 | */ | ||
| 99 | clk_register_clkdev(clk, NULL, "dev:uart3"); | ||
| 100 | clk_register_clkdev(clk, NULL, "dev:uart4"); | ||
| 101 | } else | ||
| 102 | clk_register_clkdev(clk, NULL, "fpga:uart3"); | ||
| 103 | |||
| 104 | |||
| 105 | /* 1 MHz clock */ | ||
| 106 | clk = clk_register_fixed_rate(NULL, "clk1mhz", NULL, CLK_IS_ROOT, | ||
| 107 | 1000000); | ||
| 108 | clk_register_clkdev(clk, NULL, "sp804"); | ||
| 109 | |||
| 110 | /* ICST VCO clock */ | ||
| 111 | clk = icst_clk_register(NULL, &realview_icst_desc); | ||
| 112 | clk_register_clkdev(clk, NULL, "dev:clcd"); | ||
| 113 | clk_register_clkdev(clk, NULL, "issp:clcd"); | ||
| 114 | } | ||
diff --git a/drivers/cpufreq/omap-cpufreq.c b/drivers/cpufreq/omap-cpufreq.c index 17fa04d08be9..b47034e650a5 100644 --- a/drivers/cpufreq/omap-cpufreq.c +++ b/drivers/cpufreq/omap-cpufreq.c | |||
| @@ -218,7 +218,7 @@ static int __cpuinit omap_cpu_init(struct cpufreq_policy *policy) | |||
| 218 | 218 | ||
| 219 | policy->cur = policy->min = policy->max = omap_getspeed(policy->cpu); | 219 | policy->cur = policy->min = policy->max = omap_getspeed(policy->cpu); |
| 220 | 220 | ||
| 221 | if (atomic_inc_return(&freq_table_users) == 1) | 221 | if (!freq_table) |
| 222 | result = opp_init_cpufreq_table(mpu_dev, &freq_table); | 222 | result = opp_init_cpufreq_table(mpu_dev, &freq_table); |
| 223 | 223 | ||
| 224 | if (result) { | 224 | if (result) { |
| @@ -227,6 +227,8 @@ static int __cpuinit omap_cpu_init(struct cpufreq_policy *policy) | |||
| 227 | goto fail_ck; | 227 | goto fail_ck; |
| 228 | } | 228 | } |
| 229 | 229 | ||
| 230 | atomic_inc_return(&freq_table_users); | ||
| 231 | |||
| 230 | result = cpufreq_frequency_table_cpuinfo(policy, freq_table); | 232 | result = cpufreq_frequency_table_cpuinfo(policy, freq_table); |
| 231 | if (result) | 233 | if (result) |
| 232 | goto fail_table; | 234 | goto fail_table; |
diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c index 53c8c51d5881..93d14070141a 100644 --- a/drivers/crypto/caam/jr.c +++ b/drivers/crypto/caam/jr.c | |||
| @@ -63,7 +63,7 @@ static void caam_jr_dequeue(unsigned long devarg) | |||
| 63 | 63 | ||
| 64 | head = ACCESS_ONCE(jrp->head); | 64 | head = ACCESS_ONCE(jrp->head); |
| 65 | 65 | ||
| 66 | spin_lock_bh(&jrp->outlock); | 66 | spin_lock(&jrp->outlock); |
| 67 | 67 | ||
| 68 | sw_idx = tail = jrp->tail; | 68 | sw_idx = tail = jrp->tail; |
| 69 | hw_idx = jrp->out_ring_read_index; | 69 | hw_idx = jrp->out_ring_read_index; |
| @@ -115,7 +115,7 @@ static void caam_jr_dequeue(unsigned long devarg) | |||
| 115 | jrp->tail = tail; | 115 | jrp->tail = tail; |
| 116 | } | 116 | } |
| 117 | 117 | ||
| 118 | spin_unlock_bh(&jrp->outlock); | 118 | spin_unlock(&jrp->outlock); |
| 119 | 119 | ||
| 120 | /* Finally, execute user's callback */ | 120 | /* Finally, execute user's callback */ |
| 121 | usercall(dev, userdesc, userstatus, userarg); | 121 | usercall(dev, userdesc, userstatus, userarg); |
| @@ -236,14 +236,14 @@ int caam_jr_enqueue(struct device *dev, u32 *desc, | |||
| 236 | return -EIO; | 236 | return -EIO; |
| 237 | } | 237 | } |
| 238 | 238 | ||
| 239 | spin_lock(&jrp->inplock); | 239 | spin_lock_bh(&jrp->inplock); |
| 240 | 240 | ||
| 241 | head = jrp->head; | 241 | head = jrp->head; |
| 242 | tail = ACCESS_ONCE(jrp->tail); | 242 | tail = ACCESS_ONCE(jrp->tail); |
| 243 | 243 | ||
| 244 | if (!rd_reg32(&jrp->rregs->inpring_avail) || | 244 | if (!rd_reg32(&jrp->rregs->inpring_avail) || |
| 245 | CIRC_SPACE(head, tail, JOBR_DEPTH) <= 0) { | 245 | CIRC_SPACE(head, tail, JOBR_DEPTH) <= 0) { |
| 246 | spin_unlock(&jrp->inplock); | 246 | spin_unlock_bh(&jrp->inplock); |
| 247 | dma_unmap_single(dev, desc_dma, desc_size, DMA_TO_DEVICE); | 247 | dma_unmap_single(dev, desc_dma, desc_size, DMA_TO_DEVICE); |
| 248 | return -EBUSY; | 248 | return -EBUSY; |
| 249 | } | 249 | } |
| @@ -265,7 +265,7 @@ int caam_jr_enqueue(struct device *dev, u32 *desc, | |||
| 265 | 265 | ||
| 266 | wr_reg32(&jrp->rregs->inpring_jobadd, 1); | 266 | wr_reg32(&jrp->rregs->inpring_jobadd, 1); |
| 267 | 267 | ||
| 268 | spin_unlock(&jrp->inplock); | 268 | spin_unlock_bh(&jrp->inplock); |
| 269 | 269 | ||
| 270 | return 0; | 270 | return 0; |
| 271 | } | 271 | } |
diff --git a/drivers/crypto/hifn_795x.c b/drivers/crypto/hifn_795x.c index c9c4befb5a8d..df14358d7fa1 100644 --- a/drivers/crypto/hifn_795x.c +++ b/drivers/crypto/hifn_795x.c | |||
| @@ -821,8 +821,8 @@ static int hifn_register_rng(struct hifn_device *dev) | |||
| 821 | /* | 821 | /* |
| 822 | * We must wait at least 256 Pk_clk cycles between two reads of the rng. | 822 | * We must wait at least 256 Pk_clk cycles between two reads of the rng. |
| 823 | */ | 823 | */ |
| 824 | dev->rng_wait_time = DIV_ROUND_UP(NSEC_PER_SEC, dev->pk_clk_freq) * | 824 | dev->rng_wait_time = DIV_ROUND_UP_ULL(NSEC_PER_SEC, |
| 825 | 256; | 825 | dev->pk_clk_freq) * 256; |
| 826 | 826 | ||
| 827 | dev->rng.name = dev->name; | 827 | dev->rng.name = dev->name; |
| 828 | dev->rng.data_present = hifn_rng_data_present, | 828 | dev->rng.data_present = hifn_rng_data_present, |
diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c index 9cac88a65f78..9528779ca463 100644 --- a/drivers/gpio/gpio-pxa.c +++ b/drivers/gpio/gpio-pxa.c | |||
| @@ -26,6 +26,8 @@ | |||
| 26 | #include <linux/syscore_ops.h> | 26 | #include <linux/syscore_ops.h> |
| 27 | #include <linux/slab.h> | 27 | #include <linux/slab.h> |
| 28 | 28 | ||
| 29 | #include <asm/mach/irq.h> | ||
| 30 | |||
| 29 | #include <mach/irqs.h> | 31 | #include <mach/irqs.h> |
| 30 | 32 | ||
| 31 | /* | 33 | /* |
| @@ -59,6 +61,7 @@ | |||
| 59 | #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) | 61 | #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) |
| 60 | 62 | ||
| 61 | int pxa_last_gpio; | 63 | int pxa_last_gpio; |
| 64 | static int irq_base; | ||
| 62 | 65 | ||
| 63 | #ifdef CONFIG_OF | 66 | #ifdef CONFIG_OF |
| 64 | static struct irq_domain *domain; | 67 | static struct irq_domain *domain; |
| @@ -167,63 +170,14 @@ static inline int __gpio_is_occupied(unsigned gpio) | |||
| 167 | return ret; | 170 | return ret; |
| 168 | } | 171 | } |
| 169 | 172 | ||
| 170 | #ifdef CONFIG_ARCH_PXA | ||
| 171 | static inline int __pxa_gpio_to_irq(int gpio) | ||
| 172 | { | ||
| 173 | if (gpio_is_pxa_type(gpio_type)) | ||
| 174 | return PXA_GPIO_TO_IRQ(gpio); | ||
| 175 | return -1; | ||
| 176 | } | ||
| 177 | |||
| 178 | static inline int __pxa_irq_to_gpio(int irq) | ||
| 179 | { | ||
| 180 | if (gpio_is_pxa_type(gpio_type)) | ||
| 181 | return irq - PXA_GPIO_TO_IRQ(0); | ||
| 182 | return -1; | ||
| 183 | } | ||
| 184 | #else | ||
| 185 | static inline int __pxa_gpio_to_irq(int gpio) { return -1; } | ||
| 186 | static inline int __pxa_irq_to_gpio(int irq) { return -1; } | ||
| 187 | #endif | ||
| 188 | |||
| 189 | #ifdef CONFIG_ARCH_MMP | ||
| 190 | static inline int __mmp_gpio_to_irq(int gpio) | ||
| 191 | { | ||
| 192 | if (gpio_is_mmp_type(gpio_type)) | ||
| 193 | return MMP_GPIO_TO_IRQ(gpio); | ||
| 194 | return -1; | ||
| 195 | } | ||
| 196 | |||
| 197 | static inline int __mmp_irq_to_gpio(int irq) | ||
| 198 | { | ||
| 199 | if (gpio_is_mmp_type(gpio_type)) | ||
| 200 | return irq - MMP_GPIO_TO_IRQ(0); | ||
| 201 | return -1; | ||
| 202 | } | ||
| 203 | #else | ||
| 204 | static inline int __mmp_gpio_to_irq(int gpio) { return -1; } | ||
| 205 | static inline int __mmp_irq_to_gpio(int irq) { return -1; } | ||
| 206 | #endif | ||
| 207 | |||
| 208 | static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | 173 | static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
| 209 | { | 174 | { |
| 210 | int gpio, ret; | 175 | return chip->base + offset + irq_base; |
| 211 | |||
| 212 | gpio = chip->base + offset; | ||
| 213 | ret = __pxa_gpio_to_irq(gpio); | ||
| 214 | if (ret >= 0) | ||
| 215 | return ret; | ||
| 216 | return __mmp_gpio_to_irq(gpio); | ||
| 217 | } | 176 | } |
| 218 | 177 | ||
| 219 | int pxa_irq_to_gpio(int irq) | 178 | int pxa_irq_to_gpio(int irq) |
| 220 | { | 179 | { |
| 221 | int ret; | 180 | return irq - irq_base; |
| 222 | |||
| 223 | ret = __pxa_irq_to_gpio(irq); | ||
| 224 | if (ret >= 0) | ||
| 225 | return ret; | ||
| 226 | return __mmp_irq_to_gpio(irq); | ||
| 227 | } | 181 | } |
| 228 | 182 | ||
| 229 | static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | 183 | static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
| @@ -403,6 +357,9 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) | |||
| 403 | struct pxa_gpio_chip *c; | 357 | struct pxa_gpio_chip *c; |
| 404 | int loop, gpio, gpio_base, n; | 358 | int loop, gpio, gpio_base, n; |
| 405 | unsigned long gedr; | 359 | unsigned long gedr; |
| 360 | struct irq_chip *chip = irq_desc_get_chip(desc); | ||
| 361 | |||
| 362 | chained_irq_enter(chip, desc); | ||
| 406 | 363 | ||
| 407 | do { | 364 | do { |
| 408 | loop = 0; | 365 | loop = 0; |
| @@ -422,6 +379,8 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) | |||
| 422 | } | 379 | } |
| 423 | } | 380 | } |
| 424 | } while (loop); | 381 | } while (loop); |
| 382 | |||
| 383 | chained_irq_exit(chip, desc); | ||
| 425 | } | 384 | } |
| 426 | 385 | ||
| 427 | static void pxa_ack_muxed_gpio(struct irq_data *d) | 386 | static void pxa_ack_muxed_gpio(struct irq_data *d) |
| @@ -535,7 +494,7 @@ const struct irq_domain_ops pxa_irq_domain_ops = { | |||
| 535 | 494 | ||
| 536 | static int __devinit pxa_gpio_probe_dt(struct platform_device *pdev) | 495 | static int __devinit pxa_gpio_probe_dt(struct platform_device *pdev) |
| 537 | { | 496 | { |
| 538 | int ret, nr_banks, nr_gpios, irq_base; | 497 | int ret, nr_banks, nr_gpios; |
| 539 | struct device_node *prev, *next, *np = pdev->dev.of_node; | 498 | struct device_node *prev, *next, *np = pdev->dev.of_node; |
| 540 | const struct of_device_id *of_id = | 499 | const struct of_device_id *of_id = |
| 541 | of_match_device(pxa_gpio_dt_ids, &pdev->dev); | 500 | of_match_device(pxa_gpio_dt_ids, &pdev->dev); |
| @@ -590,10 +549,20 @@ static int __devinit pxa_gpio_probe(struct platform_device *pdev) | |||
| 590 | int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0; | 549 | int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0; |
| 591 | 550 | ||
| 592 | ret = pxa_gpio_probe_dt(pdev); | 551 | ret = pxa_gpio_probe_dt(pdev); |
| 593 | if (ret < 0) | 552 | if (ret < 0) { |
| 594 | pxa_last_gpio = pxa_gpio_nums(); | 553 | pxa_last_gpio = pxa_gpio_nums(); |
| 595 | else | 554 | #ifdef CONFIG_ARCH_PXA |
| 555 | if (gpio_is_pxa_type(gpio_type)) | ||
| 556 | irq_base = PXA_GPIO_TO_IRQ(0); | ||
| 557 | #endif | ||
| 558 | #ifdef CONFIG_ARCH_MMP | ||
| 559 | if (gpio_is_mmp_type(gpio_type)) | ||
| 560 | irq_base = MMP_GPIO_TO_IRQ(0); | ||
| 561 | #endif | ||
| 562 | } else { | ||
| 596 | use_of = 1; | 563 | use_of = 1; |
| 564 | } | ||
| 565 | |||
| 597 | if (!pxa_last_gpio) | 566 | if (!pxa_last_gpio) |
| 598 | return -EINVAL; | 567 | return -EINVAL; |
| 599 | 568 | ||
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index 08a7aa722d6b..6fbfc244748f 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c | |||
| @@ -1981,7 +1981,7 @@ int drm_mode_cursor_ioctl(struct drm_device *dev, | |||
| 1981 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | 1981 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 1982 | return -EINVAL; | 1982 | return -EINVAL; |
| 1983 | 1983 | ||
| 1984 | if (!req->flags) | 1984 | if (!req->flags || (~DRM_MODE_CURSOR_FLAGS & req->flags)) |
| 1985 | return -EINVAL; | 1985 | return -EINVAL; |
| 1986 | 1986 | ||
| 1987 | mutex_lock(&dev->mode_config.mutex); | 1987 | mutex_lock(&dev->mode_config.mutex); |
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index a8743c399e83..b7ee230572b7 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c | |||
| @@ -87,6 +87,9 @@ static struct edid_quirk { | |||
| 87 | int product_id; | 87 | int product_id; |
| 88 | u32 quirks; | 88 | u32 quirks; |
| 89 | } edid_quirk_list[] = { | 89 | } edid_quirk_list[] = { |
| 90 | /* ASUS VW222S */ | ||
| 91 | { "ACI", 0x22a2, EDID_QUIRK_FORCE_REDUCED_BLANKING }, | ||
| 92 | |||
| 90 | /* Acer AL1706 */ | 93 | /* Acer AL1706 */ |
| 91 | { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, | 94 | { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, |
| 92 | /* Acer F51 */ | 95 | /* Acer F51 */ |
diff --git a/drivers/gpu/drm/gma500/psb_intel_display.c b/drivers/gpu/drm/gma500/psb_intel_display.c index 30dc22a7156c..8033526bb53b 100644 --- a/drivers/gpu/drm/gma500/psb_intel_display.c +++ b/drivers/gpu/drm/gma500/psb_intel_display.c | |||
| @@ -1362,6 +1362,9 @@ void psb_intel_crtc_init(struct drm_device *dev, int pipe, | |||
| 1362 | (struct drm_connector **) (psb_intel_crtc + 1); | 1362 | (struct drm_connector **) (psb_intel_crtc + 1); |
| 1363 | psb_intel_crtc->mode_set.num_connectors = 0; | 1363 | psb_intel_crtc->mode_set.num_connectors = 0; |
| 1364 | psb_intel_cursor_init(dev, psb_intel_crtc); | 1364 | psb_intel_cursor_init(dev, psb_intel_crtc); |
| 1365 | |||
| 1366 | /* Set to true so that the pipe is forced off on initial config. */ | ||
| 1367 | psb_intel_crtc->active = true; | ||
| 1365 | } | 1368 | } |
| 1366 | 1369 | ||
| 1367 | int psb_intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, | 1370 | int psb_intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index d9a5372ec56f..60815b861ec2 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c | |||
| @@ -72,7 +72,7 @@ int i915_gem_init_aliasing_ppgtt(struct drm_device *dev) | |||
| 72 | /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024 | 72 | /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024 |
| 73 | * entries. For aliasing ppgtt support we just steal them at the end for | 73 | * entries. For aliasing ppgtt support we just steal them at the end for |
| 74 | * now. */ | 74 | * now. */ |
| 75 | first_pd_entry_in_global_pt = 512*1024 - I915_PPGTT_PD_ENTRIES; | 75 | first_pd_entry_in_global_pt = dev_priv->mm.gtt->gtt_total_entries - I915_PPGTT_PD_ENTRIES; |
| 76 | 76 | ||
| 77 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | 77 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); |
| 78 | if (!ppgtt) | 78 | if (!ppgtt) |
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a69a3d0d3acf..2dfa6cf4886b 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
| @@ -1384,7 +1384,7 @@ static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |||
| 1384 | enum pipe pipe, int reg) | 1384 | enum pipe pipe, int reg) |
| 1385 | { | 1385 | { |
| 1386 | u32 val = I915_READ(reg); | 1386 | u32 val = I915_READ(reg); |
| 1387 | WARN(hdmi_pipe_enabled(dev_priv, val, pipe), | 1387 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
| 1388 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", | 1388 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
| 1389 | reg, pipe_name(pipe)); | 1389 | reg, pipe_name(pipe)); |
| 1390 | 1390 | ||
| @@ -1404,13 +1404,13 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |||
| 1404 | 1404 | ||
| 1405 | reg = PCH_ADPA; | 1405 | reg = PCH_ADPA; |
| 1406 | val = I915_READ(reg); | 1406 | val = I915_READ(reg); |
| 1407 | WARN(adpa_pipe_enabled(dev_priv, val, pipe), | 1407 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
| 1408 | "PCH VGA enabled on transcoder %c, should be disabled\n", | 1408 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
| 1409 | pipe_name(pipe)); | 1409 | pipe_name(pipe)); |
| 1410 | 1410 | ||
| 1411 | reg = PCH_LVDS; | 1411 | reg = PCH_LVDS; |
| 1412 | val = I915_READ(reg); | 1412 | val = I915_READ(reg); |
| 1413 | WARN(lvds_pipe_enabled(dev_priv, val, pipe), | 1413 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
| 1414 | "PCH LVDS enabled on transcoder %c, should be disabled\n", | 1414 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
| 1415 | pipe_name(pipe)); | 1415 | pipe_name(pipe)); |
| 1416 | 1416 | ||
| @@ -1872,7 +1872,7 @@ static void disable_pch_hdmi(struct drm_i915_private *dev_priv, | |||
| 1872 | enum pipe pipe, int reg) | 1872 | enum pipe pipe, int reg) |
| 1873 | { | 1873 | { |
| 1874 | u32 val = I915_READ(reg); | 1874 | u32 val = I915_READ(reg); |
| 1875 | if (hdmi_pipe_enabled(dev_priv, val, pipe)) { | 1875 | if (hdmi_pipe_enabled(dev_priv, pipe, val)) { |
| 1876 | DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n", | 1876 | DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n", |
| 1877 | reg, pipe); | 1877 | reg, pipe); |
| 1878 | I915_WRITE(reg, val & ~PORT_ENABLE); | 1878 | I915_WRITE(reg, val & ~PORT_ENABLE); |
| @@ -1894,12 +1894,12 @@ static void intel_disable_pch_ports(struct drm_i915_private *dev_priv, | |||
| 1894 | 1894 | ||
| 1895 | reg = PCH_ADPA; | 1895 | reg = PCH_ADPA; |
| 1896 | val = I915_READ(reg); | 1896 | val = I915_READ(reg); |
| 1897 | if (adpa_pipe_enabled(dev_priv, val, pipe)) | 1897 | if (adpa_pipe_enabled(dev_priv, pipe, val)) |
| 1898 | I915_WRITE(reg, val & ~ADPA_DAC_ENABLE); | 1898 | I915_WRITE(reg, val & ~ADPA_DAC_ENABLE); |
| 1899 | 1899 | ||
| 1900 | reg = PCH_LVDS; | 1900 | reg = PCH_LVDS; |
| 1901 | val = I915_READ(reg); | 1901 | val = I915_READ(reg); |
| 1902 | if (lvds_pipe_enabled(dev_priv, val, pipe)) { | 1902 | if (lvds_pipe_enabled(dev_priv, pipe, val)) { |
| 1903 | DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val); | 1903 | DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val); |
| 1904 | I915_WRITE(reg, val & ~LVDS_PORT_EN); | 1904 | I915_WRITE(reg, val & ~LVDS_PORT_EN); |
| 1905 | POSTING_READ(reg); | 1905 | POSTING_READ(reg); |
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index e05c0d3e3440..e9a6f6aaed85 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c | |||
| @@ -780,6 +780,14 @@ static const struct dmi_system_id intel_no_lvds[] = { | |||
| 780 | DMI_MATCH(DMI_BOARD_NAME, "ZBOXSD-ID12/ID13"), | 780 | DMI_MATCH(DMI_BOARD_NAME, "ZBOXSD-ID12/ID13"), |
| 781 | }, | 781 | }, |
| 782 | }, | 782 | }, |
| 783 | { | ||
| 784 | .callback = intel_no_lvds_dmi_callback, | ||
| 785 | .ident = "Gigabyte GA-D525TUD", | ||
| 786 | .matches = { | ||
| 787 | DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), | ||
| 788 | DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), | ||
| 789 | }, | ||
| 790 | }, | ||
| 783 | 791 | ||
| 784 | { } /* terminating entry */ | 792 | { } /* terminating entry */ |
| 785 | }; | 793 | }; |
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index cc8df4de2d92..7644f31a3778 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c | |||
| @@ -60,11 +60,11 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, | |||
| 60 | 60 | ||
| 61 | switch (fb->pixel_format) { | 61 | switch (fb->pixel_format) { |
| 62 | case DRM_FORMAT_XBGR8888: | 62 | case DRM_FORMAT_XBGR8888: |
| 63 | sprctl |= SPRITE_FORMAT_RGBX888; | 63 | sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; |
| 64 | pixel_size = 4; | 64 | pixel_size = 4; |
| 65 | break; | 65 | break; |
| 66 | case DRM_FORMAT_XRGB8888: | 66 | case DRM_FORMAT_XRGB8888: |
| 67 | sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; | 67 | sprctl |= SPRITE_FORMAT_RGBX888; |
| 68 | pixel_size = 4; | 68 | pixel_size = 4; |
| 69 | break; | 69 | break; |
| 70 | case DRM_FORMAT_YUYV: | 70 | case DRM_FORMAT_YUYV: |
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c index 1866dbb49979..c61014442aa9 100644 --- a/drivers/gpu/drm/nouveau/nouveau_state.c +++ b/drivers/gpu/drm/nouveau/nouveau_state.c | |||
| @@ -736,9 +736,11 @@ nouveau_card_init(struct drm_device *dev) | |||
| 736 | } | 736 | } |
| 737 | break; | 737 | break; |
| 738 | case NV_C0: | 738 | case NV_C0: |
| 739 | nvc0_copy_create(dev, 1); | 739 | if (!(nv_rd32(dev, 0x022500) & 0x00000200)) |
| 740 | nvc0_copy_create(dev, 1); | ||
| 740 | case NV_D0: | 741 | case NV_D0: |
| 741 | nvc0_copy_create(dev, 0); | 742 | if (!(nv_rd32(dev, 0x022500) & 0x00000100)) |
| 743 | nvc0_copy_create(dev, 0); | ||
| 742 | break; | 744 | break; |
| 743 | default: | 745 | default: |
| 744 | break; | 746 | break; |
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index f4d4505fe831..2817101fb167 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c | |||
| @@ -258,7 +258,6 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) | |||
| 258 | radeon_crtc->enabled = true; | 258 | radeon_crtc->enabled = true; |
| 259 | /* adjust pm to dpms changes BEFORE enabling crtcs */ | 259 | /* adjust pm to dpms changes BEFORE enabling crtcs */ |
| 260 | radeon_pm_compute_clocks(rdev); | 260 | radeon_pm_compute_clocks(rdev); |
| 261 | /* disable crtc pair power gating before programming */ | ||
| 262 | if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set) | 261 | if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set) |
| 263 | atombios_powergate_crtc(crtc, ATOM_DISABLE); | 262 | atombios_powergate_crtc(crtc, ATOM_DISABLE); |
| 264 | atombios_enable_crtc(crtc, ATOM_ENABLE); | 263 | atombios_enable_crtc(crtc, ATOM_ENABLE); |
| @@ -278,25 +277,8 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) | |||
| 278 | atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); | 277 | atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); |
| 279 | atombios_enable_crtc(crtc, ATOM_DISABLE); | 278 | atombios_enable_crtc(crtc, ATOM_DISABLE); |
| 280 | radeon_crtc->enabled = false; | 279 | radeon_crtc->enabled = false; |
| 281 | /* power gating is per-pair */ | 280 | if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set) |
| 282 | if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set) { | 281 | atombios_powergate_crtc(crtc, ATOM_ENABLE); |
| 283 | struct drm_crtc *other_crtc; | ||
| 284 | struct radeon_crtc *other_radeon_crtc; | ||
| 285 | list_for_each_entry(other_crtc, &rdev->ddev->mode_config.crtc_list, head) { | ||
| 286 | other_radeon_crtc = to_radeon_crtc(other_crtc); | ||
| 287 | if (((radeon_crtc->crtc_id == 0) && (other_radeon_crtc->crtc_id == 1)) || | ||
| 288 | ((radeon_crtc->crtc_id == 1) && (other_radeon_crtc->crtc_id == 0)) || | ||
| 289 | ((radeon_crtc->crtc_id == 2) && (other_radeon_crtc->crtc_id == 3)) || | ||
| 290 | ((radeon_crtc->crtc_id == 3) && (other_radeon_crtc->crtc_id == 2)) || | ||
| 291 | ((radeon_crtc->crtc_id == 4) && (other_radeon_crtc->crtc_id == 5)) || | ||
| 292 | ((radeon_crtc->crtc_id == 5) && (other_radeon_crtc->crtc_id == 4))) { | ||
| 293 | /* if both crtcs in the pair are off, enable power gating */ | ||
| 294 | if (other_radeon_crtc->enabled == false) | ||
| 295 | atombios_powergate_crtc(crtc, ATOM_ENABLE); | ||
| 296 | break; | ||
| 297 | } | ||
| 298 | } | ||
| 299 | } | ||
| 300 | /* adjust pm to dpms changes AFTER disabling crtcs */ | 282 | /* adjust pm to dpms changes AFTER disabling crtcs */ |
| 301 | radeon_pm_compute_clocks(rdev); | 283 | radeon_pm_compute_clocks(rdev); |
| 302 | break; | 284 | break; |
| @@ -1682,9 +1664,22 @@ static void atombios_crtc_disable(struct drm_crtc *crtc) | |||
| 1682 | struct drm_device *dev = crtc->dev; | 1664 | struct drm_device *dev = crtc->dev; |
| 1683 | struct radeon_device *rdev = dev->dev_private; | 1665 | struct radeon_device *rdev = dev->dev_private; |
| 1684 | struct radeon_atom_ss ss; | 1666 | struct radeon_atom_ss ss; |
| 1667 | int i; | ||
| 1685 | 1668 | ||
| 1686 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); | 1669 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
| 1687 | 1670 | ||
| 1671 | for (i = 0; i < rdev->num_crtc; i++) { | ||
| 1672 | if (rdev->mode_info.crtcs[i] && | ||
| 1673 | rdev->mode_info.crtcs[i]->enabled && | ||
| 1674 | i != radeon_crtc->crtc_id && | ||
| 1675 | radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) { | ||
| 1676 | /* one other crtc is using this pll don't turn | ||
| 1677 | * off the pll | ||
| 1678 | */ | ||
| 1679 | goto done; | ||
| 1680 | } | ||
| 1681 | } | ||
| 1682 | |||
| 1688 | switch (radeon_crtc->pll_id) { | 1683 | switch (radeon_crtc->pll_id) { |
| 1689 | case ATOM_PPLL1: | 1684 | case ATOM_PPLL1: |
| 1690 | case ATOM_PPLL2: | 1685 | case ATOM_PPLL2: |
| @@ -1701,6 +1696,7 @@ static void atombios_crtc_disable(struct drm_crtc *crtc) | |||
| 1701 | default: | 1696 | default: |
| 1702 | break; | 1697 | break; |
| 1703 | } | 1698 | } |
| 1699 | done: | ||
| 1704 | radeon_crtc->pll_id = -1; | 1700 | radeon_crtc->pll_id = -1; |
| 1705 | } | 1701 | } |
| 1706 | 1702 | ||
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c index 7712cf5ab33b..3623b98ed3fe 100644 --- a/drivers/gpu/drm/radeon/atombios_dp.c +++ b/drivers/gpu/drm/radeon/atombios_dp.c | |||
| @@ -577,30 +577,25 @@ int radeon_dp_get_panel_mode(struct drm_encoder *encoder, | |||
| 577 | struct radeon_device *rdev = dev->dev_private; | 577 | struct radeon_device *rdev = dev->dev_private; |
| 578 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | 578 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| 579 | int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; | 579 | int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; |
| 580 | u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector); | ||
| 581 | u8 tmp; | ||
| 580 | 582 | ||
| 581 | if (!ASIC_IS_DCE4(rdev)) | 583 | if (!ASIC_IS_DCE4(rdev)) |
| 582 | return panel_mode; | 584 | return panel_mode; |
| 583 | 585 | ||
| 584 | if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == | 586 | if (dp_bridge != ENCODER_OBJECT_ID_NONE) { |
| 585 | ENCODER_OBJECT_ID_NUTMEG) | 587 | /* DP bridge chips */ |
| 586 | panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; | 588 | tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); |
| 587 | else if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == | 589 | if (tmp & 1) |
| 588 | ENCODER_OBJECT_ID_TRAVIS) { | 590 | panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; |
| 589 | u8 id[6]; | 591 | else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || |
| 590 | int i; | 592 | (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) |
| 591 | for (i = 0; i < 6; i++) | ||
| 592 | id[i] = radeon_read_dpcd_reg(radeon_connector, 0x503 + i); | ||
| 593 | if (id[0] == 0x73 && | ||
| 594 | id[1] == 0x69 && | ||
| 595 | id[2] == 0x76 && | ||
| 596 | id[3] == 0x61 && | ||
| 597 | id[4] == 0x72 && | ||
| 598 | id[5] == 0x54) | ||
| 599 | panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; | 593 | panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; |
| 600 | else | 594 | else |
| 601 | panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; | 595 | panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; |
| 602 | } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { | 596 | } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
| 603 | u8 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); | 597 | /* eDP */ |
| 598 | tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); | ||
| 604 | if (tmp & 1) | 599 | if (tmp & 1) |
| 605 | panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; | 600 | panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; |
| 606 | } | 601 | } |
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c index f9bc27fe269a..6e8803a1170c 100644 --- a/drivers/gpu/drm/radeon/atombios_encoders.c +++ b/drivers/gpu/drm/radeon/atombios_encoders.c | |||
| @@ -1379,6 +1379,8 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) | |||
| 1379 | struct drm_device *dev = encoder->dev; | 1379 | struct drm_device *dev = encoder->dev; |
| 1380 | struct radeon_device *rdev = dev->dev_private; | 1380 | struct radeon_device *rdev = dev->dev_private; |
| 1381 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | 1381 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 1382 | struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); | ||
| 1383 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | ||
| 1382 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); | 1384 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
| 1383 | struct radeon_connector *radeon_connector = NULL; | 1385 | struct radeon_connector *radeon_connector = NULL; |
| 1384 | struct radeon_connector_atom_dig *radeon_dig_connector = NULL; | 1386 | struct radeon_connector_atom_dig *radeon_dig_connector = NULL; |
| @@ -1390,19 +1392,37 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) | |||
| 1390 | 1392 | ||
| 1391 | switch (mode) { | 1393 | switch (mode) { |
| 1392 | case DRM_MODE_DPMS_ON: | 1394 | case DRM_MODE_DPMS_ON: |
| 1393 | /* some early dce3.2 boards have a bug in their transmitter control table */ | 1395 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { |
| 1394 | if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730) || | 1396 | if (!connector) |
| 1395 | ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { | 1397 | dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; |
| 1396 | if (ASIC_IS_DCE6(rdev)) { | 1398 | else |
| 1397 | /* It seems we need to call ATOM_ENCODER_CMD_SETUP again | 1399 | dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector); |
| 1398 | * before reenabling encoder on DPMS ON, otherwise we never | 1400 | |
| 1399 | * get picture | 1401 | /* setup and enable the encoder */ |
| 1400 | */ | 1402 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); |
| 1401 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); | 1403 | atombios_dig_encoder_setup(encoder, |
| 1404 | ATOM_ENCODER_CMD_SETUP_PANEL_MODE, | ||
| 1405 | dig->panel_mode); | ||
| 1406 | if (ext_encoder) { | ||
| 1407 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) | ||
| 1408 | atombios_external_encoder_setup(encoder, ext_encoder, | ||
| 1409 | EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); | ||
| 1402 | } | 1410 | } |
| 1403 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); | 1411 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); |
| 1404 | } else { | 1412 | } else if (ASIC_IS_DCE4(rdev)) { |
| 1413 | /* setup and enable the encoder */ | ||
| 1414 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); | ||
| 1415 | /* enable the transmitter */ | ||
| 1416 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); | ||
| 1405 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); | 1417 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); |
| 1418 | } else { | ||
| 1419 | /* setup and enable the encoder and transmitter */ | ||
| 1420 | atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); | ||
| 1421 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); | ||
| 1422 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); | ||
| 1423 | /* some early dce3.2 boards have a bug in their transmitter control table */ | ||
| 1424 | if ((rdev->family != CHIP_RV710) || (rdev->family != CHIP_RV730)) | ||
| 1425 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); | ||
| 1406 | } | 1426 | } |
| 1407 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { | 1427 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { |
| 1408 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { | 1428 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
| @@ -1420,10 +1440,19 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) | |||
| 1420 | case DRM_MODE_DPMS_STANDBY: | 1440 | case DRM_MODE_DPMS_STANDBY: |
| 1421 | case DRM_MODE_DPMS_SUSPEND: | 1441 | case DRM_MODE_DPMS_SUSPEND: |
| 1422 | case DRM_MODE_DPMS_OFF: | 1442 | case DRM_MODE_DPMS_OFF: |
| 1423 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) | 1443 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { |
| 1444 | /* disable the transmitter */ | ||
| 1424 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); | 1445 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
| 1425 | else | 1446 | } else if (ASIC_IS_DCE4(rdev)) { |
| 1447 | /* disable the transmitter */ | ||
| 1448 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); | ||
| 1449 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); | ||
| 1450 | } else { | ||
| 1451 | /* disable the encoder and transmitter */ | ||
| 1426 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); | 1452 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); |
| 1453 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); | ||
| 1454 | atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); | ||
| 1455 | } | ||
| 1427 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { | 1456 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { |
| 1428 | if (ASIC_IS_DCE4(rdev)) | 1457 | if (ASIC_IS_DCE4(rdev)) |
| 1429 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); | 1458 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); |
| @@ -1740,13 +1769,34 @@ static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) | |||
| 1740 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | 1769 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
| 1741 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | 1770 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 1742 | struct drm_encoder *test_encoder; | 1771 | struct drm_encoder *test_encoder; |
| 1743 | struct radeon_encoder_atom_dig *dig; | 1772 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 1744 | uint32_t dig_enc_in_use = 0; | 1773 | uint32_t dig_enc_in_use = 0; |
| 1745 | 1774 | ||
| 1746 | /* DCE4/5 */ | 1775 | if (ASIC_IS_DCE6(rdev)) { |
| 1747 | if (ASIC_IS_DCE4(rdev)) { | 1776 | /* DCE6 */ |
| 1748 | dig = radeon_encoder->enc_priv; | 1777 | switch (radeon_encoder->encoder_id) { |
| 1749 | if (ASIC_IS_DCE41(rdev)) { | 1778 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| 1779 | if (dig->linkb) | ||
| 1780 | return 1; | ||
| 1781 | else | ||
| 1782 | return 0; | ||
| 1783 | break; | ||
| 1784 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | ||
| 1785 | if (dig->linkb) | ||
| 1786 | return 3; | ||
| 1787 | else | ||
| 1788 | return 2; | ||
| 1789 | break; | ||
| 1790 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | ||
| 1791 | if (dig->linkb) | ||
| 1792 | return 5; | ||
| 1793 | else | ||
| 1794 | return 4; | ||
| 1795 | break; | ||
| 1796 | } | ||
| 1797 | } else if (ASIC_IS_DCE4(rdev)) { | ||
| 1798 | /* DCE4/5 */ | ||
| 1799 | if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) { | ||
| 1750 | /* ontario follows DCE4 */ | 1800 | /* ontario follows DCE4 */ |
| 1751 | if (rdev->family == CHIP_PALM) { | 1801 | if (rdev->family == CHIP_PALM) { |
| 1752 | if (dig->linkb) | 1802 | if (dig->linkb) |
| @@ -1848,10 +1898,12 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder, | |||
| 1848 | struct drm_device *dev = encoder->dev; | 1898 | struct drm_device *dev = encoder->dev; |
| 1849 | struct radeon_device *rdev = dev->dev_private; | 1899 | struct radeon_device *rdev = dev->dev_private; |
| 1850 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | 1900 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 1851 | struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); | ||
| 1852 | 1901 | ||
| 1853 | radeon_encoder->pixel_clock = adjusted_mode->clock; | 1902 | radeon_encoder->pixel_clock = adjusted_mode->clock; |
| 1854 | 1903 | ||
| 1904 | /* need to call this here rather than in prepare() since we need some crtc info */ | ||
| 1905 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); | ||
| 1906 | |||
| 1855 | if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { | 1907 | if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { |
| 1856 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) | 1908 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) |
| 1857 | atombios_yuv_setup(encoder, true); | 1909 | atombios_yuv_setup(encoder, true); |
| @@ -1870,38 +1922,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder, | |||
| 1870 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | 1922 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
| 1871 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | 1923 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
| 1872 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | 1924 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
| 1873 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { | 1925 | /* handled in dpms */ |
| 1874 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); | ||
| 1875 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | ||
| 1876 | |||
| 1877 | if (!connector) | ||
| 1878 | dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; | ||
| 1879 | else | ||
| 1880 | dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector); | ||
| 1881 | |||
| 1882 | /* setup and enable the encoder */ | ||
| 1883 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); | ||
| 1884 | atombios_dig_encoder_setup(encoder, | ||
| 1885 | ATOM_ENCODER_CMD_SETUP_PANEL_MODE, | ||
| 1886 | dig->panel_mode); | ||
| 1887 | } else if (ASIC_IS_DCE4(rdev)) { | ||
| 1888 | /* disable the transmitter */ | ||
| 1889 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); | ||
| 1890 | /* setup and enable the encoder */ | ||
| 1891 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); | ||
| 1892 | |||
| 1893 | /* enable the transmitter */ | ||
| 1894 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); | ||
| 1895 | } else { | ||
| 1896 | /* disable the encoder and transmitter */ | ||
| 1897 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); | ||
| 1898 | atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); | ||
| 1899 | |||
| 1900 | /* setup and enable the encoder and transmitter */ | ||
| 1901 | atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); | ||
| 1902 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); | ||
| 1903 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); | ||
| 1904 | } | ||
| 1905 | break; | 1926 | break; |
| 1906 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | 1927 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
| 1907 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | 1928 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
| @@ -1922,14 +1943,6 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder, | |||
| 1922 | break; | 1943 | break; |
| 1923 | } | 1944 | } |
| 1924 | 1945 | ||
| 1925 | if (ext_encoder) { | ||
| 1926 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) | ||
| 1927 | atombios_external_encoder_setup(encoder, ext_encoder, | ||
| 1928 | EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); | ||
| 1929 | else | ||
| 1930 | atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); | ||
| 1931 | } | ||
| 1932 | |||
| 1933 | atombios_apply_encoder_quirks(encoder, adjusted_mode); | 1946 | atombios_apply_encoder_quirks(encoder, adjusted_mode); |
| 1934 | 1947 | ||
| 1935 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { | 1948 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { |
| @@ -2116,7 +2129,6 @@ static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) | |||
| 2116 | } | 2129 | } |
| 2117 | 2130 | ||
| 2118 | radeon_atom_output_lock(encoder, true); | 2131 | radeon_atom_output_lock(encoder, true); |
| 2119 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); | ||
| 2120 | 2132 | ||
| 2121 | if (connector) { | 2133 | if (connector) { |
| 2122 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | 2134 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| @@ -2137,6 +2149,7 @@ static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) | |||
| 2137 | 2149 | ||
| 2138 | static void radeon_atom_encoder_commit(struct drm_encoder *encoder) | 2150 | static void radeon_atom_encoder_commit(struct drm_encoder *encoder) |
| 2139 | { | 2151 | { |
| 2152 | /* need to call this here as we need the crtc set up */ | ||
| 2140 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); | 2153 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); |
| 2141 | radeon_atom_output_lock(encoder, false); | 2154 | radeon_atom_output_lock(encoder, false); |
| 2142 | } | 2155 | } |
| @@ -2177,14 +2190,7 @@ static void radeon_atom_encoder_disable(struct drm_encoder *encoder) | |||
| 2177 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | 2190 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
| 2178 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | 2191 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
| 2179 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | 2192 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
| 2180 | if (ASIC_IS_DCE4(rdev)) | 2193 | /* handled in dpms */ |
| 2181 | /* disable the transmitter */ | ||
| 2182 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); | ||
| 2183 | else { | ||
| 2184 | /* disable the encoder and transmitter */ | ||
| 2185 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); | ||
| 2186 | atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); | ||
| 2187 | } | ||
| 2188 | break; | 2194 | break; |
| 2189 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | 2195 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
| 2190 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | 2196 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c index ab74e6b149e7..f37676d7f217 100644 --- a/drivers/gpu/drm/radeon/r600_cs.c +++ b/drivers/gpu/drm/radeon/r600_cs.c | |||
| @@ -63,6 +63,7 @@ struct r600_cs_track { | |||
| 63 | u32 cb_color_size_idx[8]; /* unused */ | 63 | u32 cb_color_size_idx[8]; /* unused */ |
| 64 | u32 cb_target_mask; | 64 | u32 cb_target_mask; |
| 65 | u32 cb_shader_mask; /* unused */ | 65 | u32 cb_shader_mask; /* unused */ |
| 66 | bool is_resolve; | ||
| 66 | u32 cb_color_size[8]; | 67 | u32 cb_color_size[8]; |
| 67 | u32 vgt_strmout_en; | 68 | u32 vgt_strmout_en; |
| 68 | u32 vgt_strmout_buffer_en; | 69 | u32 vgt_strmout_buffer_en; |
| @@ -315,7 +316,15 @@ static void r600_cs_track_init(struct r600_cs_track *track) | |||
| 315 | track->cb_color_bo[i] = NULL; | 316 | track->cb_color_bo[i] = NULL; |
| 316 | track->cb_color_bo_offset[i] = 0xFFFFFFFF; | 317 | track->cb_color_bo_offset[i] = 0xFFFFFFFF; |
| 317 | track->cb_color_bo_mc[i] = 0xFFFFFFFF; | 318 | track->cb_color_bo_mc[i] = 0xFFFFFFFF; |
| 318 | } | 319 | track->cb_color_frag_bo[i] = NULL; |
| 320 | track->cb_color_frag_offset[i] = 0xFFFFFFFF; | ||
| 321 | track->cb_color_tile_bo[i] = NULL; | ||
| 322 | track->cb_color_tile_offset[i] = 0xFFFFFFFF; | ||
| 323 | track->cb_color_mask[i] = 0xFFFFFFFF; | ||
| 324 | } | ||
| 325 | track->is_resolve = false; | ||
| 326 | track->nsamples = 16; | ||
| 327 | track->log_nsamples = 4; | ||
| 319 | track->cb_target_mask = 0xFFFFFFFF; | 328 | track->cb_target_mask = 0xFFFFFFFF; |
| 320 | track->cb_shader_mask = 0xFFFFFFFF; | 329 | track->cb_shader_mask = 0xFFFFFFFF; |
| 321 | track->cb_dirty = true; | 330 | track->cb_dirty = true; |
| @@ -352,6 +361,8 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) | |||
| 352 | volatile u32 *ib = p->ib.ptr; | 361 | volatile u32 *ib = p->ib.ptr; |
| 353 | unsigned array_mode; | 362 | unsigned array_mode; |
| 354 | u32 format; | 363 | u32 format; |
| 364 | /* When resolve is used, the second colorbuffer has always 1 sample. */ | ||
| 365 | unsigned nsamples = track->is_resolve && i == 1 ? 1 : track->nsamples; | ||
| 355 | 366 | ||
| 356 | size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i]; | 367 | size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i]; |
| 357 | format = G_0280A0_FORMAT(track->cb_color_info[i]); | 368 | format = G_0280A0_FORMAT(track->cb_color_info[i]); |
| @@ -375,7 +386,7 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) | |||
| 375 | array_check.group_size = track->group_size; | 386 | array_check.group_size = track->group_size; |
| 376 | array_check.nbanks = track->nbanks; | 387 | array_check.nbanks = track->nbanks; |
| 377 | array_check.npipes = track->npipes; | 388 | array_check.npipes = track->npipes; |
| 378 | array_check.nsamples = track->nsamples; | 389 | array_check.nsamples = nsamples; |
| 379 | array_check.blocksize = r600_fmt_get_blocksize(format); | 390 | array_check.blocksize = r600_fmt_get_blocksize(format); |
| 380 | if (r600_get_array_mode_alignment(&array_check, | 391 | if (r600_get_array_mode_alignment(&array_check, |
| 381 | &pitch_align, &height_align, &depth_align, &base_align)) { | 392 | &pitch_align, &height_align, &depth_align, &base_align)) { |
| @@ -421,7 +432,7 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) | |||
| 421 | 432 | ||
| 422 | /* check offset */ | 433 | /* check offset */ |
| 423 | tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) * | 434 | tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) * |
| 424 | r600_fmt_get_blocksize(format) * track->nsamples; | 435 | r600_fmt_get_blocksize(format) * nsamples; |
| 425 | switch (array_mode) { | 436 | switch (array_mode) { |
| 426 | default: | 437 | default: |
| 427 | case V_0280A0_ARRAY_LINEAR_GENERAL: | 438 | case V_0280A0_ARRAY_LINEAR_GENERAL: |
| @@ -792,6 +803,12 @@ static int r600_cs_track_check(struct radeon_cs_parser *p) | |||
| 792 | */ | 803 | */ |
| 793 | if (track->cb_dirty) { | 804 | if (track->cb_dirty) { |
| 794 | tmp = track->cb_target_mask; | 805 | tmp = track->cb_target_mask; |
| 806 | |||
| 807 | /* We must check both colorbuffers for RESOLVE. */ | ||
| 808 | if (track->is_resolve) { | ||
| 809 | tmp |= 0xff; | ||
| 810 | } | ||
| 811 | |||
| 795 | for (i = 0; i < 8; i++) { | 812 | for (i = 0; i < 8; i++) { |
| 796 | if ((tmp >> (i * 4)) & 0xF) { | 813 | if ((tmp >> (i * 4)) & 0xF) { |
| 797 | /* at least one component is enabled */ | 814 | /* at least one component is enabled */ |
| @@ -1281,6 +1298,11 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
| 1281 | track->nsamples = 1 << tmp; | 1298 | track->nsamples = 1 << tmp; |
| 1282 | track->cb_dirty = true; | 1299 | track->cb_dirty = true; |
| 1283 | break; | 1300 | break; |
| 1301 | case R_028808_CB_COLOR_CONTROL: | ||
| 1302 | tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx)); | ||
| 1303 | track->is_resolve = tmp == V_028808_SPECIAL_RESOLVE_BOX; | ||
| 1304 | track->cb_dirty = true; | ||
| 1305 | break; | ||
| 1284 | case R_0280A0_CB_COLOR0_INFO: | 1306 | case R_0280A0_CB_COLOR0_INFO: |
| 1285 | case R_0280A4_CB_COLOR1_INFO: | 1307 | case R_0280A4_CB_COLOR1_INFO: |
| 1286 | case R_0280A8_CB_COLOR2_INFO: | 1308 | case R_0280A8_CB_COLOR2_INFO: |
| @@ -1416,7 +1438,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
| 1416 | case R_028118_CB_COLOR6_MASK: | 1438 | case R_028118_CB_COLOR6_MASK: |
| 1417 | case R_02811C_CB_COLOR7_MASK: | 1439 | case R_02811C_CB_COLOR7_MASK: |
| 1418 | tmp = (reg - R_028100_CB_COLOR0_MASK) / 4; | 1440 | tmp = (reg - R_028100_CB_COLOR0_MASK) / 4; |
| 1419 | track->cb_color_mask[tmp] = ib[idx]; | 1441 | track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx); |
| 1420 | if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) { | 1442 | if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) { |
| 1421 | track->cb_dirty = true; | 1443 | track->cb_dirty = true; |
| 1422 | } | 1444 | } |
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h index bdb69a63062f..fa6f37099ba9 100644 --- a/drivers/gpu/drm/radeon/r600d.h +++ b/drivers/gpu/drm/radeon/r600d.h | |||
| @@ -66,6 +66,14 @@ | |||
| 66 | #define CC_RB_BACKEND_DISABLE 0x98F4 | 66 | #define CC_RB_BACKEND_DISABLE 0x98F4 |
| 67 | #define BACKEND_DISABLE(x) ((x) << 16) | 67 | #define BACKEND_DISABLE(x) ((x) << 16) |
| 68 | 68 | ||
| 69 | #define R_028808_CB_COLOR_CONTROL 0x28808 | ||
| 70 | #define S_028808_SPECIAL_OP(x) (((x) & 0x7) << 4) | ||
| 71 | #define G_028808_SPECIAL_OP(x) (((x) >> 4) & 0x7) | ||
| 72 | #define C_028808_SPECIAL_OP 0xFFFFFF8F | ||
| 73 | #define V_028808_SPECIAL_NORMAL 0x00 | ||
| 74 | #define V_028808_SPECIAL_DISABLE 0x01 | ||
| 75 | #define V_028808_SPECIAL_RESOLVE_BOX 0x07 | ||
| 76 | |||
| 69 | #define CB_COLOR0_BASE 0x28040 | 77 | #define CB_COLOR0_BASE 0x28040 |
| 70 | #define CB_COLOR1_BASE 0x28044 | 78 | #define CB_COLOR1_BASE 0x28044 |
| 71 | #define CB_COLOR2_BASE 0x28048 | 79 | #define CB_COLOR2_BASE 0x28048 |
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index d2e243867ac6..7a3daebd732d 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c | |||
| @@ -1051,7 +1051,7 @@ int radeon_device_init(struct radeon_device *rdev, | |||
| 1051 | if (rdev->flags & RADEON_IS_AGP) | 1051 | if (rdev->flags & RADEON_IS_AGP) |
| 1052 | rdev->need_dma32 = true; | 1052 | rdev->need_dma32 = true; |
| 1053 | if ((rdev->flags & RADEON_IS_PCI) && | 1053 | if ((rdev->flags & RADEON_IS_PCI) && |
| 1054 | (rdev->family < CHIP_RS400)) | 1054 | (rdev->family <= CHIP_RS740)) |
| 1055 | rdev->need_dma32 = true; | 1055 | rdev->need_dma32 = true; |
| 1056 | 1056 | ||
| 1057 | dma_bits = rdev->need_dma32 ? 32 : 40; | 1057 | dma_bits = rdev->need_dma32 ? 32 : 40; |
| @@ -1346,12 +1346,15 @@ retry: | |||
| 1346 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { | 1346 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
| 1347 | radeon_ring_restore(rdev, &rdev->ring[i], | 1347 | radeon_ring_restore(rdev, &rdev->ring[i], |
| 1348 | ring_sizes[i], ring_data[i]); | 1348 | ring_sizes[i], ring_data[i]); |
| 1349 | ring_sizes[i] = 0; | ||
| 1350 | ring_data[i] = NULL; | ||
| 1349 | } | 1351 | } |
| 1350 | 1352 | ||
| 1351 | r = radeon_ib_ring_tests(rdev); | 1353 | r = radeon_ib_ring_tests(rdev); |
| 1352 | if (r) { | 1354 | if (r) { |
| 1353 | dev_err(rdev->dev, "ib ring test failed (%d).\n", r); | 1355 | dev_err(rdev->dev, "ib ring test failed (%d).\n", r); |
| 1354 | if (saved) { | 1356 | if (saved) { |
| 1357 | saved = false; | ||
| 1355 | radeon_suspend(rdev); | 1358 | radeon_suspend(rdev); |
| 1356 | goto retry; | 1359 | goto retry; |
| 1357 | } | 1360 | } |
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c index 27d22d709c90..8c593ea82c41 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.c +++ b/drivers/gpu/drm/radeon/radeon_drv.c | |||
| @@ -63,9 +63,10 @@ | |||
| 63 | * 2.19.0 - r600-eg: MSAA textures | 63 | * 2.19.0 - r600-eg: MSAA textures |
| 64 | * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query | 64 | * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query |
| 65 | * 2.21.0 - r600-r700: FMASK and CMASK | 65 | * 2.21.0 - r600-r700: FMASK and CMASK |
| 66 | * 2.22.0 - r600 only: RESOLVE_BOX allowed | ||
| 66 | */ | 67 | */ |
| 67 | #define KMS_DRIVER_MAJOR 2 | 68 | #define KMS_DRIVER_MAJOR 2 |
| 68 | #define KMS_DRIVER_MINOR 21 | 69 | #define KMS_DRIVER_MINOR 22 |
| 69 | #define KMS_DRIVER_PATCHLEVEL 0 | 70 | #define KMS_DRIVER_PATCHLEVEL 0 |
| 70 | int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); | 71 | int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); |
| 71 | int radeon_driver_unload_kms(struct drm_device *dev); | 72 | int radeon_driver_unload_kms(struct drm_device *dev); |
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r600 b/drivers/gpu/drm/radeon/reg_srcs/r600 index f93e45d869f4..20bfbda7b3f1 100644 --- a/drivers/gpu/drm/radeon/reg_srcs/r600 +++ b/drivers/gpu/drm/radeon/reg_srcs/r600 | |||
| @@ -744,7 +744,6 @@ r600 0x9400 | |||
| 744 | 0x00028C38 CB_CLRCMP_DST | 744 | 0x00028C38 CB_CLRCMP_DST |
| 745 | 0x00028C3C CB_CLRCMP_MSK | 745 | 0x00028C3C CB_CLRCMP_MSK |
| 746 | 0x00028C34 CB_CLRCMP_SRC | 746 | 0x00028C34 CB_CLRCMP_SRC |
| 747 | 0x00028808 CB_COLOR_CONTROL | ||
| 748 | 0x0002842C CB_FOG_BLUE | 747 | 0x0002842C CB_FOG_BLUE |
| 749 | 0x00028428 CB_FOG_GREEN | 748 | 0x00028428 CB_FOG_GREEN |
| 750 | 0x00028424 CB_FOG_RED | 749 | 0x00028424 CB_FOG_RED |
diff --git a/drivers/hid/hid-core.c b/drivers/hid/hid-core.c index 60ea284407ce..8bf8a64e5115 100644 --- a/drivers/hid/hid-core.c +++ b/drivers/hid/hid-core.c | |||
| @@ -1624,7 +1624,6 @@ static const struct hid_device_id hid_have_special_driver[] = { | |||
| 1624 | { HID_USB_DEVICE(USB_VENDOR_ID_ORTEK, USB_DEVICE_ID_ORTEK_WKB2000) }, | 1624 | { HID_USB_DEVICE(USB_VENDOR_ID_ORTEK, USB_DEVICE_ID_ORTEK_WKB2000) }, |
| 1625 | { HID_USB_DEVICE(USB_VENDOR_ID_PETALYNX, USB_DEVICE_ID_PETALYNX_MAXTER_REMOTE) }, | 1625 | { HID_USB_DEVICE(USB_VENDOR_ID_PETALYNX, USB_DEVICE_ID_PETALYNX_MAXTER_REMOTE) }, |
| 1626 | { HID_USB_DEVICE(USB_VENDOR_ID_PRIMAX, USB_DEVICE_ID_PRIMAX_KEYBOARD) }, | 1626 | { HID_USB_DEVICE(USB_VENDOR_ID_PRIMAX, USB_DEVICE_ID_PRIMAX_KEYBOARD) }, |
| 1627 | { HID_USB_DEVICE(USB_VENDOR_ID_QUANTA, USB_DEVICE_ID_PIXART_IMAGING_INC_OPTICAL_TOUCH_SCREEN) }, | ||
| 1628 | { HID_USB_DEVICE(USB_VENDOR_ID_ROCCAT, USB_DEVICE_ID_ROCCAT_KONE) }, | 1627 | { HID_USB_DEVICE(USB_VENDOR_ID_ROCCAT, USB_DEVICE_ID_ROCCAT_KONE) }, |
| 1629 | { HID_USB_DEVICE(USB_VENDOR_ID_ROCCAT, USB_DEVICE_ID_ROCCAT_ARVO) }, | 1628 | { HID_USB_DEVICE(USB_VENDOR_ID_ROCCAT, USB_DEVICE_ID_ROCCAT_ARVO) }, |
| 1630 | { HID_USB_DEVICE(USB_VENDOR_ID_ROCCAT, USB_DEVICE_ID_ROCCAT_ISKU) }, | 1629 | { HID_USB_DEVICE(USB_VENDOR_ID_ROCCAT, USB_DEVICE_ID_ROCCAT_ISKU) }, |
diff --git a/drivers/hwmon/asus_atk0110.c b/drivers/hwmon/asus_atk0110.c index 351d1f4593e7..4ee578948723 100644 --- a/drivers/hwmon/asus_atk0110.c +++ b/drivers/hwmon/asus_atk0110.c | |||
| @@ -34,6 +34,12 @@ static const struct dmi_system_id __initconst atk_force_new_if[] = { | |||
| 34 | .matches = { | 34 | .matches = { |
| 35 | DMI_MATCH(DMI_BOARD_NAME, "SABERTOOTH X58") | 35 | DMI_MATCH(DMI_BOARD_NAME, "SABERTOOTH X58") |
| 36 | } | 36 | } |
| 37 | }, { | ||
| 38 | /* Old interface reads the same sensor for fan0 and fan1 */ | ||
| 39 | .ident = "Asus M5A78L", | ||
| 40 | .matches = { | ||
| 41 | DMI_MATCH(DMI_BOARD_NAME, "M5A78L") | ||
| 42 | } | ||
| 37 | }, | 43 | }, |
| 38 | { } | 44 | { } |
| 39 | }; | 45 | }; |
diff --git a/drivers/ide/ide-pm.c b/drivers/ide/ide-pm.c index 92406097efeb..8d1e32d7cd97 100644 --- a/drivers/ide/ide-pm.c +++ b/drivers/ide/ide-pm.c | |||
| @@ -4,7 +4,7 @@ | |||
| 4 | 4 | ||
| 5 | int generic_ide_suspend(struct device *dev, pm_message_t mesg) | 5 | int generic_ide_suspend(struct device *dev, pm_message_t mesg) |
| 6 | { | 6 | { |
| 7 | ide_drive_t *drive = dev_get_drvdata(dev); | 7 | ide_drive_t *drive = to_ide_device(dev); |
| 8 | ide_drive_t *pair = ide_get_pair_dev(drive); | 8 | ide_drive_t *pair = ide_get_pair_dev(drive); |
| 9 | ide_hwif_t *hwif = drive->hwif; | 9 | ide_hwif_t *hwif = drive->hwif; |
| 10 | struct request *rq; | 10 | struct request *rq; |
| @@ -40,7 +40,7 @@ int generic_ide_suspend(struct device *dev, pm_message_t mesg) | |||
| 40 | 40 | ||
| 41 | int generic_ide_resume(struct device *dev) | 41 | int generic_ide_resume(struct device *dev) |
| 42 | { | 42 | { |
| 43 | ide_drive_t *drive = dev_get_drvdata(dev); | 43 | ide_drive_t *drive = to_ide_device(dev); |
| 44 | ide_drive_t *pair = ide_get_pair_dev(drive); | 44 | ide_drive_t *pair = ide_get_pair_dev(drive); |
| 45 | ide_hwif_t *hwif = drive->hwif; | 45 | ide_hwif_t *hwif = drive->hwif; |
| 46 | struct request *rq; | 46 | struct request *rq; |
diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c index 7040a0081130..6b37e2d6ed8f 100644 --- a/drivers/mfd/db8500-prcmu.c +++ b/drivers/mfd/db8500-prcmu.c | |||
| @@ -418,6 +418,9 @@ static struct { | |||
| 418 | 418 | ||
| 419 | static atomic_t ac_wake_req_state = ATOMIC_INIT(0); | 419 | static atomic_t ac_wake_req_state = ATOMIC_INIT(0); |
| 420 | 420 | ||
| 421 | /* Functions definition */ | ||
| 422 | static void compute_armss_rate(void); | ||
| 423 | |||
| 421 | /* Spinlocks */ | 424 | /* Spinlocks */ |
| 422 | static DEFINE_SPINLOCK(prcmu_lock); | 425 | static DEFINE_SPINLOCK(prcmu_lock); |
| 423 | static DEFINE_SPINLOCK(clkout_lock); | 426 | static DEFINE_SPINLOCK(clkout_lock); |
| @@ -517,6 +520,7 @@ static struct dsiescclk dsiescclk[3] = { | |||
| 517 | } | 520 | } |
| 518 | }; | 521 | }; |
| 519 | 522 | ||
| 523 | |||
| 520 | /* | 524 | /* |
| 521 | * Used by MCDE to setup all necessary PRCMU registers | 525 | * Used by MCDE to setup all necessary PRCMU registers |
| 522 | */ | 526 | */ |
| @@ -1013,6 +1017,7 @@ int db8500_prcmu_set_arm_opp(u8 opp) | |||
| 1013 | (mb1_transfer.ack.arm_opp != opp)) | 1017 | (mb1_transfer.ack.arm_opp != opp)) |
| 1014 | r = -EIO; | 1018 | r = -EIO; |
| 1015 | 1019 | ||
| 1020 | compute_armss_rate(); | ||
| 1016 | mutex_unlock(&mb1_transfer.lock); | 1021 | mutex_unlock(&mb1_transfer.lock); |
| 1017 | 1022 | ||
| 1018 | return r; | 1023 | return r; |
| @@ -1612,6 +1617,7 @@ static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate, | |||
| 1612 | if ((branch == PLL_FIX) || ((branch == PLL_DIV) && | 1617 | if ((branch == PLL_FIX) || ((branch == PLL_DIV) && |
| 1613 | (val & PRCM_PLL_FREQ_DIV2EN) && | 1618 | (val & PRCM_PLL_FREQ_DIV2EN) && |
| 1614 | ((reg == PRCM_PLLSOC0_FREQ) || | 1619 | ((reg == PRCM_PLLSOC0_FREQ) || |
| 1620 | (reg == PRCM_PLLARM_FREQ) || | ||
| 1615 | (reg == PRCM_PLLDDR_FREQ)))) | 1621 | (reg == PRCM_PLLDDR_FREQ)))) |
| 1616 | div *= 2; | 1622 | div *= 2; |
| 1617 | 1623 | ||
| @@ -1661,6 +1667,39 @@ static unsigned long clock_rate(u8 clock) | |||
| 1661 | else | 1667 | else |
| 1662 | return 0; | 1668 | return 0; |
| 1663 | } | 1669 | } |
| 1670 | static unsigned long latest_armss_rate; | ||
| 1671 | static unsigned long armss_rate(void) | ||
| 1672 | { | ||
| 1673 | return latest_armss_rate; | ||
| 1674 | } | ||
| 1675 | |||
| 1676 | static void compute_armss_rate(void) | ||
| 1677 | { | ||
| 1678 | u32 r; | ||
| 1679 | unsigned long rate; | ||
| 1680 | |||
| 1681 | r = readl(PRCM_ARM_CHGCLKREQ); | ||
| 1682 | |||
| 1683 | if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) { | ||
| 1684 | /* External ARMCLKFIX clock */ | ||
| 1685 | |||
| 1686 | rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX); | ||
| 1687 | |||
| 1688 | /* Check PRCM_ARM_CHGCLKREQ divider */ | ||
| 1689 | if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL)) | ||
| 1690 | rate /= 2; | ||
| 1691 | |||
| 1692 | /* Check PRCM_ARMCLKFIX_MGT divider */ | ||
| 1693 | r = readl(PRCM_ARMCLKFIX_MGT); | ||
| 1694 | r &= PRCM_CLK_MGT_CLKPLLDIV_MASK; | ||
| 1695 | rate /= r; | ||
| 1696 | |||
| 1697 | } else {/* ARM PLL */ | ||
| 1698 | rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV); | ||
| 1699 | } | ||
| 1700 | |||
| 1701 | latest_armss_rate = rate; | ||
| 1702 | } | ||
| 1664 | 1703 | ||
| 1665 | static unsigned long dsiclk_rate(u8 n) | 1704 | static unsigned long dsiclk_rate(u8 n) |
| 1666 | { | 1705 | { |
| @@ -1707,6 +1746,8 @@ unsigned long prcmu_clock_rate(u8 clock) | |||
| 1707 | return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW); | 1746 | return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW); |
| 1708 | else if (clock == PRCMU_PLLSOC1) | 1747 | else if (clock == PRCMU_PLLSOC1) |
| 1709 | return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW); | 1748 | return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW); |
| 1749 | else if (clock == PRCMU_ARMSS) | ||
| 1750 | return armss_rate(); | ||
| 1710 | else if (clock == PRCMU_PLLDDR) | 1751 | else if (clock == PRCMU_PLLDDR) |
| 1711 | return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW); | 1752 | return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW); |
| 1712 | else if (clock == PRCMU_PLLDSI) | 1753 | else if (clock == PRCMU_PLLDSI) |
| @@ -2693,6 +2734,7 @@ void __init db8500_prcmu_early_init(void) | |||
| 2693 | handle_simple_irq); | 2734 | handle_simple_irq); |
| 2694 | set_irq_flags(irq, IRQF_VALID); | 2735 | set_irq_flags(irq, IRQF_VALID); |
| 2695 | } | 2736 | } |
| 2737 | compute_armss_rate(); | ||
| 2696 | } | 2738 | } |
| 2697 | 2739 | ||
| 2698 | static void __init init_prcm_registers(void) | 2740 | static void __init init_prcm_registers(void) |
diff --git a/drivers/mfd/dbx500-prcmu-regs.h b/drivers/mfd/dbx500-prcmu-regs.h index 23108a6e3167..79c76ebdba52 100644 --- a/drivers/mfd/dbx500-prcmu-regs.h +++ b/drivers/mfd/dbx500-prcmu-regs.h | |||
| @@ -61,7 +61,8 @@ | |||
| 61 | #define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3 0x2 | 61 | #define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3 0x2 |
| 62 | 62 | ||
| 63 | #define PRCM_ARM_CHGCLKREQ (_PRCMU_BASE + 0x114) | 63 | #define PRCM_ARM_CHGCLKREQ (_PRCMU_BASE + 0x114) |
| 64 | #define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ 0x1 | 64 | #define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ BIT(0) |
| 65 | #define PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL BIT(16) | ||
| 65 | 66 | ||
| 66 | #define PRCM_PLLARM_ENABLE (_PRCMU_BASE + 0x98) | 67 | #define PRCM_PLLARM_ENABLE (_PRCMU_BASE + 0x98) |
| 67 | #define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE 0x1 | 68 | #define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE 0x1 |
| @@ -140,6 +141,7 @@ | |||
| 140 | /* PRCMU clock/PLL/reset registers */ | 141 | /* PRCMU clock/PLL/reset registers */ |
| 141 | #define PRCM_PLLSOC0_FREQ (_PRCMU_BASE + 0x080) | 142 | #define PRCM_PLLSOC0_FREQ (_PRCMU_BASE + 0x080) |
| 142 | #define PRCM_PLLSOC1_FREQ (_PRCMU_BASE + 0x084) | 143 | #define PRCM_PLLSOC1_FREQ (_PRCMU_BASE + 0x084) |
| 144 | #define PRCM_PLLARM_FREQ (_PRCMU_BASE + 0x088) | ||
| 143 | #define PRCM_PLLDDR_FREQ (_PRCMU_BASE + 0x08C) | 145 | #define PRCM_PLLDDR_FREQ (_PRCMU_BASE + 0x08C) |
| 144 | #define PRCM_PLL_FREQ_D_SHIFT 0 | 146 | #define PRCM_PLL_FREQ_D_SHIFT 0 |
| 145 | #define PRCM_PLL_FREQ_D_MASK BITS(0, 7) | 147 | #define PRCM_PLL_FREQ_D_MASK BITS(0, 7) |
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index 252aaefcacfa..d944d6ef7da8 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c | |||
| @@ -22,6 +22,8 @@ | |||
| 22 | #include <linux/io.h> | 22 | #include <linux/io.h> |
| 23 | #include <linux/irq.h> | 23 | #include <linux/irq.h> |
| 24 | #include <linux/slab.h> | 24 | #include <linux/slab.h> |
| 25 | #include <linux/of.h> | ||
| 26 | #include <linux/of_device.h> | ||
| 25 | 27 | ||
| 26 | #include <mach/dma.h> | 28 | #include <mach/dma.h> |
| 27 | #include <plat/pxa3xx_nand.h> | 29 | #include <plat/pxa3xx_nand.h> |
| @@ -1032,7 +1034,7 @@ static int alloc_nand_resource(struct platform_device *pdev) | |||
| 1032 | struct pxa3xx_nand_platform_data *pdata; | 1034 | struct pxa3xx_nand_platform_data *pdata; |
| 1033 | struct pxa3xx_nand_info *info; | 1035 | struct pxa3xx_nand_info *info; |
| 1034 | struct pxa3xx_nand_host *host; | 1036 | struct pxa3xx_nand_host *host; |
| 1035 | struct nand_chip *chip; | 1037 | struct nand_chip *chip = NULL; |
| 1036 | struct mtd_info *mtd; | 1038 | struct mtd_info *mtd; |
| 1037 | struct resource *r; | 1039 | struct resource *r; |
| 1038 | int ret, irq, cs; | 1040 | int ret, irq, cs; |
| @@ -1081,21 +1083,31 @@ static int alloc_nand_resource(struct platform_device *pdev) | |||
| 1081 | } | 1083 | } |
| 1082 | clk_enable(info->clk); | 1084 | clk_enable(info->clk); |
| 1083 | 1085 | ||
| 1084 | r = platform_get_resource(pdev, IORESOURCE_DMA, 0); | 1086 | /* |
| 1085 | if (r == NULL) { | 1087 | * This is a dirty hack to make this driver work from devicetree |
| 1086 | dev_err(&pdev->dev, "no resource defined for data DMA\n"); | 1088 | * bindings. It can be removed once we have a prober DMA controller |
| 1087 | ret = -ENXIO; | 1089 | * framework for DT. |
| 1088 | goto fail_put_clk; | 1090 | */ |
| 1089 | } | 1091 | if (pdev->dev.of_node && cpu_is_pxa3xx()) { |
| 1090 | info->drcmr_dat = r->start; | 1092 | info->drcmr_dat = 97; |
| 1093 | info->drcmr_cmd = 99; | ||
| 1094 | } else { | ||
| 1095 | r = platform_get_resource(pdev, IORESOURCE_DMA, 0); | ||
| 1096 | if (r == NULL) { | ||
| 1097 | dev_err(&pdev->dev, "no resource defined for data DMA\n"); | ||
| 1098 | ret = -ENXIO; | ||
| 1099 | goto fail_put_clk; | ||
| 1100 | } | ||
| 1101 | info->drcmr_dat = r->start; | ||
| 1091 | 1102 | ||
| 1092 | r = platform_get_resource(pdev, IORESOURCE_DMA, 1); | 1103 | r = platform_get_resource(pdev, IORESOURCE_DMA, 1); |
| 1093 | if (r == NULL) { | 1104 | if (r == NULL) { |
| 1094 | dev_err(&pdev->dev, "no resource defined for command DMA\n"); | 1105 | dev_err(&pdev->dev, "no resource defined for command DMA\n"); |
| 1095 | ret = -ENXIO; | 1106 | ret = -ENXIO; |
| 1096 | goto fail_put_clk; | 1107 | goto fail_put_clk; |
| 1108 | } | ||
| 1109 | info->drcmr_cmd = r->start; | ||
| 1097 | } | 1110 | } |
| 1098 | info->drcmr_cmd = r->start; | ||
| 1099 | 1111 | ||
| 1100 | irq = platform_get_irq(pdev, 0); | 1112 | irq = platform_get_irq(pdev, 0); |
| 1101 | if (irq < 0) { | 1113 | if (irq < 0) { |
| @@ -1200,12 +1212,55 @@ static int pxa3xx_nand_remove(struct platform_device *pdev) | |||
| 1200 | return 0; | 1212 | return 0; |
| 1201 | } | 1213 | } |
| 1202 | 1214 | ||
| 1215 | #ifdef CONFIG_OF | ||
| 1216 | static struct of_device_id pxa3xx_nand_dt_ids[] = { | ||
| 1217 | { .compatible = "marvell,pxa3xx-nand" }, | ||
| 1218 | {} | ||
| 1219 | }; | ||
| 1220 | MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids); | ||
| 1221 | |||
| 1222 | static int pxa3xx_nand_probe_dt(struct platform_device *pdev) | ||
| 1223 | { | ||
| 1224 | struct pxa3xx_nand_platform_data *pdata; | ||
| 1225 | struct device_node *np = pdev->dev.of_node; | ||
| 1226 | const struct of_device_id *of_id = | ||
| 1227 | of_match_device(pxa3xx_nand_dt_ids, &pdev->dev); | ||
| 1228 | |||
| 1229 | if (!of_id) | ||
| 1230 | return 0; | ||
| 1231 | |||
| 1232 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | ||
| 1233 | if (!pdata) | ||
| 1234 | return -ENOMEM; | ||
| 1235 | |||
| 1236 | if (of_get_property(np, "marvell,nand-enable-arbiter", NULL)) | ||
| 1237 | pdata->enable_arbiter = 1; | ||
| 1238 | if (of_get_property(np, "marvell,nand-keep-config", NULL)) | ||
| 1239 | pdata->keep_config = 1; | ||
| 1240 | of_property_read_u32(np, "num-cs", &pdata->num_cs); | ||
| 1241 | |||
| 1242 | pdev->dev.platform_data = pdata; | ||
| 1243 | |||
| 1244 | return 0; | ||
| 1245 | } | ||
| 1246 | #else | ||
| 1247 | static inline int pxa3xx_nand_probe_dt(struct platform_device *pdev) | ||
| 1248 | { | ||
| 1249 | return 0; | ||
| 1250 | } | ||
| 1251 | #endif | ||
| 1252 | |||
| 1203 | static int pxa3xx_nand_probe(struct platform_device *pdev) | 1253 | static int pxa3xx_nand_probe(struct platform_device *pdev) |
| 1204 | { | 1254 | { |
| 1205 | struct pxa3xx_nand_platform_data *pdata; | 1255 | struct pxa3xx_nand_platform_data *pdata; |
| 1256 | struct mtd_part_parser_data ppdata = {}; | ||
| 1206 | struct pxa3xx_nand_info *info; | 1257 | struct pxa3xx_nand_info *info; |
| 1207 | int ret, cs, probe_success; | 1258 | int ret, cs, probe_success; |
| 1208 | 1259 | ||
| 1260 | ret = pxa3xx_nand_probe_dt(pdev); | ||
| 1261 | if (ret) | ||
| 1262 | return ret; | ||
| 1263 | |||
| 1209 | pdata = pdev->dev.platform_data; | 1264 | pdata = pdev->dev.platform_data; |
| 1210 | if (!pdata) { | 1265 | if (!pdata) { |
| 1211 | dev_err(&pdev->dev, "no platform data defined\n"); | 1266 | dev_err(&pdev->dev, "no platform data defined\n"); |
| @@ -1229,8 +1284,9 @@ static int pxa3xx_nand_probe(struct platform_device *pdev) | |||
| 1229 | continue; | 1284 | continue; |
| 1230 | } | 1285 | } |
| 1231 | 1286 | ||
| 1287 | ppdata.of_node = pdev->dev.of_node; | ||
| 1232 | ret = mtd_device_parse_register(info->host[cs]->mtd, NULL, | 1288 | ret = mtd_device_parse_register(info->host[cs]->mtd, NULL, |
| 1233 | NULL, pdata->parts[cs], | 1289 | &ppdata, pdata->parts[cs], |
| 1234 | pdata->nr_parts[cs]); | 1290 | pdata->nr_parts[cs]); |
| 1235 | if (!ret) | 1291 | if (!ret) |
| 1236 | probe_success = 1; | 1292 | probe_success = 1; |
| @@ -1306,6 +1362,7 @@ static int pxa3xx_nand_resume(struct platform_device *pdev) | |||
| 1306 | static struct platform_driver pxa3xx_nand_driver = { | 1362 | static struct platform_driver pxa3xx_nand_driver = { |
| 1307 | .driver = { | 1363 | .driver = { |
| 1308 | .name = "pxa3xx-nand", | 1364 | .name = "pxa3xx-nand", |
| 1365 | .of_match_table = of_match_ptr(pxa3xx_nand_dt_ids), | ||
| 1309 | }, | 1366 | }, |
| 1310 | .probe = pxa3xx_nand_probe, | 1367 | .probe = pxa3xx_nand_probe, |
| 1311 | .remove = pxa3xx_nand_remove, | 1368 | .remove = pxa3xx_nand_remove, |
diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/pinctrl-sirf.c index 7fca6ce5952b..304360cd213e 100644 --- a/drivers/pinctrl/pinctrl-sirf.c +++ b/drivers/pinctrl/pinctrl-sirf.c | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | #include <linux/pinctrl/pinctrl.h> | 17 | #include <linux/pinctrl/pinctrl.h> |
| 18 | #include <linux/pinctrl/pinmux.h> | 18 | #include <linux/pinctrl/pinmux.h> |
| 19 | #include <linux/pinctrl/consumer.h> | 19 | #include <linux/pinctrl/consumer.h> |
| 20 | #include <linux/pinctrl/machine.h> | ||
| 20 | #include <linux/of.h> | 21 | #include <linux/of.h> |
| 21 | #include <linux/of_address.h> | 22 | #include <linux/of_address.h> |
| 22 | #include <linux/of_device.h> | 23 | #include <linux/of_device.h> |
| @@ -916,11 +917,66 @@ static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s | |||
| 916 | seq_printf(s, " " DRIVER_NAME); | 917 | seq_printf(s, " " DRIVER_NAME); |
| 917 | } | 918 | } |
| 918 | 919 | ||
| 920 | static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev, | ||
| 921 | struct device_node *np_config, | ||
| 922 | struct pinctrl_map **map, unsigned *num_maps) | ||
| 923 | { | ||
| 924 | struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev); | ||
| 925 | struct device_node *np; | ||
| 926 | struct property *prop; | ||
| 927 | const char *function, *group; | ||
| 928 | int ret, index = 0, count = 0; | ||
| 929 | |||
| 930 | /* calculate number of maps required */ | ||
| 931 | for_each_child_of_node(np_config, np) { | ||
| 932 | ret = of_property_read_string(np, "sirf,function", &function); | ||
| 933 | if (ret < 0) | ||
| 934 | return ret; | ||
| 935 | |||
| 936 | ret = of_property_count_strings(np, "sirf,pins"); | ||
| 937 | if (ret < 0) | ||
| 938 | return ret; | ||
| 939 | |||
| 940 | count += ret; | ||
| 941 | } | ||
| 942 | |||
| 943 | if (!count) { | ||
| 944 | dev_err(spmx->dev, "No child nodes passed via DT\n"); | ||
| 945 | return -ENODEV; | ||
| 946 | } | ||
| 947 | |||
| 948 | *map = kzalloc(sizeof(**map) * count, GFP_KERNEL); | ||
| 949 | if (!*map) | ||
| 950 | return -ENOMEM; | ||
| 951 | |||
| 952 | for_each_child_of_node(np_config, np) { | ||
| 953 | of_property_read_string(np, "sirf,function", &function); | ||
| 954 | of_property_for_each_string(np, "sirf,pins", prop, group) { | ||
| 955 | (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP; | ||
| 956 | (*map)[index].data.mux.group = group; | ||
| 957 | (*map)[index].data.mux.function = function; | ||
| 958 | index++; | ||
| 959 | } | ||
| 960 | } | ||
| 961 | |||
| 962 | *num_maps = count; | ||
| 963 | |||
| 964 | return 0; | ||
| 965 | } | ||
| 966 | |||
| 967 | static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev, | ||
| 968 | struct pinctrl_map *map, unsigned num_maps) | ||
| 969 | { | ||
| 970 | kfree(map); | ||
| 971 | } | ||
| 972 | |||
| 919 | static struct pinctrl_ops sirfsoc_pctrl_ops = { | 973 | static struct pinctrl_ops sirfsoc_pctrl_ops = { |
| 920 | .get_groups_count = sirfsoc_get_groups_count, | 974 | .get_groups_count = sirfsoc_get_groups_count, |
| 921 | .get_group_name = sirfsoc_get_group_name, | 975 | .get_group_name = sirfsoc_get_group_name, |
| 922 | .get_group_pins = sirfsoc_get_group_pins, | 976 | .get_group_pins = sirfsoc_get_group_pins, |
| 923 | .pin_dbg_show = sirfsoc_pin_dbg_show, | 977 | .pin_dbg_show = sirfsoc_pin_dbg_show, |
| 978 | .dt_node_to_map = sirfsoc_dt_node_to_map, | ||
| 979 | .dt_free_map = sirfsoc_dt_free_map, | ||
| 924 | }; | 980 | }; |
| 925 | 981 | ||
| 926 | struct sirfsoc_pmx_func { | 982 | struct sirfsoc_pmx_func { |
| @@ -1221,7 +1277,7 @@ out_no_gpio_remap: | |||
| 1221 | } | 1277 | } |
| 1222 | 1278 | ||
| 1223 | static const struct of_device_id pinmux_ids[] __devinitconst = { | 1279 | static const struct of_device_id pinmux_ids[] __devinitconst = { |
| 1224 | { .compatible = "sirf,prima2-gpio-pinmux" }, | 1280 | { .compatible = "sirf,prima2-pinctrl" }, |
| 1225 | {} | 1281 | {} |
| 1226 | }; | 1282 | }; |
| 1227 | 1283 | ||
diff --git a/drivers/rtc/rtc-pxa.c b/drivers/rtc/rtc-pxa.c index 0075c8fd93d8..f771b2ee4b18 100644 --- a/drivers/rtc/rtc-pxa.c +++ b/drivers/rtc/rtc-pxa.c | |||
| @@ -27,6 +27,8 @@ | |||
| 27 | #include <linux/interrupt.h> | 27 | #include <linux/interrupt.h> |
| 28 | #include <linux/io.h> | 28 | #include <linux/io.h> |
| 29 | #include <linux/slab.h> | 29 | #include <linux/slab.h> |
| 30 | #include <linux/of.h> | ||
| 31 | #include <linux/of_device.h> | ||
| 30 | 32 | ||
| 31 | #include <mach/hardware.h> | 33 | #include <mach/hardware.h> |
| 32 | 34 | ||
| @@ -396,6 +398,14 @@ static int __exit pxa_rtc_remove(struct platform_device *pdev) | |||
| 396 | return 0; | 398 | return 0; |
| 397 | } | 399 | } |
| 398 | 400 | ||
| 401 | #ifdef CONFIG_OF | ||
| 402 | static struct of_device_id pxa_rtc_dt_ids[] = { | ||
| 403 | { .compatible = "marvell,pxa-rtc" }, | ||
| 404 | {} | ||
| 405 | }; | ||
| 406 | MODULE_DEVICE_TABLE(of, pxa_rtc_dt_ids); | ||
| 407 | #endif | ||
| 408 | |||
| 399 | #ifdef CONFIG_PM | 409 | #ifdef CONFIG_PM |
| 400 | static int pxa_rtc_suspend(struct device *dev) | 410 | static int pxa_rtc_suspend(struct device *dev) |
| 401 | { | 411 | { |
| @@ -425,6 +435,7 @@ static struct platform_driver pxa_rtc_driver = { | |||
| 425 | .remove = __exit_p(pxa_rtc_remove), | 435 | .remove = __exit_p(pxa_rtc_remove), |
| 426 | .driver = { | 436 | .driver = { |
| 427 | .name = "pxa-rtc", | 437 | .name = "pxa-rtc", |
| 438 | .of_match_table = of_match_ptr(pxa_rtc_dt_ids), | ||
| 428 | #ifdef CONFIG_PM | 439 | #ifdef CONFIG_PM |
| 429 | .pm = &pxa_rtc_pm_ops, | 440 | .pm = &pxa_rtc_pm_ops, |
| 430 | #endif | 441 | #endif |
diff --git a/drivers/s390/block/dasd_eckd.c b/drivers/s390/block/dasd_eckd.c index 40a826a7295f..2fb2b9ea97ec 100644 --- a/drivers/s390/block/dasd_eckd.c +++ b/drivers/s390/block/dasd_eckd.c | |||
| @@ -3804,7 +3804,7 @@ dasd_eckd_ioctl(struct dasd_block *block, unsigned int cmd, void __user *argp) | |||
| 3804 | case BIODASDSYMMIO: | 3804 | case BIODASDSYMMIO: |
| 3805 | return dasd_symm_io(device, argp); | 3805 | return dasd_symm_io(device, argp); |
| 3806 | default: | 3806 | default: |
| 3807 | return -ENOIOCTLCMD; | 3807 | return -ENOTTY; |
| 3808 | } | 3808 | } |
| 3809 | } | 3809 | } |
| 3810 | 3810 | ||
diff --git a/drivers/s390/block/dasd_ioctl.c b/drivers/s390/block/dasd_ioctl.c index cceae70279f6..654c6921a6d4 100644 --- a/drivers/s390/block/dasd_ioctl.c +++ b/drivers/s390/block/dasd_ioctl.c | |||
| @@ -498,12 +498,9 @@ int dasd_ioctl(struct block_device *bdev, fmode_t mode, | |||
| 498 | break; | 498 | break; |
| 499 | default: | 499 | default: |
| 500 | /* if the discipline has an ioctl method try it. */ | 500 | /* if the discipline has an ioctl method try it. */ |
| 501 | if (base->discipline->ioctl) { | 501 | rc = -ENOTTY; |
| 502 | if (base->discipline->ioctl) | ||
| 502 | rc = base->discipline->ioctl(block, cmd, argp); | 503 | rc = base->discipline->ioctl(block, cmd, argp); |
| 503 | if (rc == -ENOIOCTLCMD) | ||
| 504 | rc = -EINVAL; | ||
| 505 | } else | ||
| 506 | rc = -EINVAL; | ||
| 507 | } | 504 | } |
| 508 | dasd_put_device(base); | 505 | dasd_put_device(base); |
| 509 | return rc; | 506 | return rc; |
diff --git a/drivers/spi/spi-bcm63xx.c b/drivers/spi/spi-bcm63xx.c index ea0aaa3f13d0..a9f4049c6769 100644 --- a/drivers/spi/spi-bcm63xx.c +++ b/drivers/spi/spi-bcm63xx.c | |||
| @@ -47,6 +47,8 @@ struct bcm63xx_spi { | |||
| 47 | /* Platform data */ | 47 | /* Platform data */ |
| 48 | u32 speed_hz; | 48 | u32 speed_hz; |
| 49 | unsigned fifo_size; | 49 | unsigned fifo_size; |
| 50 | unsigned int msg_type_shift; | ||
| 51 | unsigned int msg_ctl_width; | ||
| 50 | 52 | ||
| 51 | /* Data buffers */ | 53 | /* Data buffers */ |
| 52 | const unsigned char *tx_ptr; | 54 | const unsigned char *tx_ptr; |
| @@ -221,13 +223,20 @@ static unsigned int bcm63xx_txrx_bufs(struct spi_device *spi, | |||
| 221 | msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT); | 223 | msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT); |
| 222 | 224 | ||
| 223 | if (t->rx_buf && t->tx_buf) | 225 | if (t->rx_buf && t->tx_buf) |
| 224 | msg_ctl |= (SPI_FD_RW << SPI_MSG_TYPE_SHIFT); | 226 | msg_ctl |= (SPI_FD_RW << bs->msg_type_shift); |
| 225 | else if (t->rx_buf) | 227 | else if (t->rx_buf) |
| 226 | msg_ctl |= (SPI_HD_R << SPI_MSG_TYPE_SHIFT); | 228 | msg_ctl |= (SPI_HD_R << bs->msg_type_shift); |
| 227 | else if (t->tx_buf) | 229 | else if (t->tx_buf) |
| 228 | msg_ctl |= (SPI_HD_W << SPI_MSG_TYPE_SHIFT); | 230 | msg_ctl |= (SPI_HD_W << bs->msg_type_shift); |
| 229 | 231 | ||
| 230 | bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL); | 232 | switch (bs->msg_ctl_width) { |
| 233 | case 8: | ||
| 234 | bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL); | ||
| 235 | break; | ||
| 236 | case 16: | ||
| 237 | bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL); | ||
| 238 | break; | ||
| 239 | } | ||
| 231 | 240 | ||
| 232 | /* Issue the transfer */ | 241 | /* Issue the transfer */ |
| 233 | cmd = SPI_CMD_START_IMMEDIATE; | 242 | cmd = SPI_CMD_START_IMMEDIATE; |
| @@ -406,9 +415,21 @@ static int __devinit bcm63xx_spi_probe(struct platform_device *pdev) | |||
| 406 | master->transfer_one_message = bcm63xx_spi_transfer_one; | 415 | master->transfer_one_message = bcm63xx_spi_transfer_one; |
| 407 | master->mode_bits = MODEBITS; | 416 | master->mode_bits = MODEBITS; |
| 408 | bs->speed_hz = pdata->speed_hz; | 417 | bs->speed_hz = pdata->speed_hz; |
| 418 | bs->msg_type_shift = pdata->msg_type_shift; | ||
| 419 | bs->msg_ctl_width = pdata->msg_ctl_width; | ||
| 409 | bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA)); | 420 | bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA)); |
| 410 | bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA)); | 421 | bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA)); |
| 411 | 422 | ||
| 423 | switch (bs->msg_ctl_width) { | ||
| 424 | case 8: | ||
| 425 | case 16: | ||
| 426 | break; | ||
| 427 | default: | ||
| 428 | dev_err(dev, "unsupported MSG_CTL width: %d\n", | ||
| 429 | bs->msg_ctl_width); | ||
| 430 | goto out_clk_disable; | ||
| 431 | } | ||
| 432 | |||
| 412 | /* Initialize hardware */ | 433 | /* Initialize hardware */ |
| 413 | clk_enable(bs->clk); | 434 | clk_enable(bs->clk); |
| 414 | bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); | 435 | bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); |
diff --git a/drivers/watchdog/booke_wdt.c b/drivers/watchdog/booke_wdt.c index 3fe82d0e8caa..5b06d31ab6a9 100644 --- a/drivers/watchdog/booke_wdt.c +++ b/drivers/watchdog/booke_wdt.c | |||
| @@ -166,18 +166,17 @@ static long booke_wdt_ioctl(struct file *file, | |||
| 166 | 166 | ||
| 167 | switch (cmd) { | 167 | switch (cmd) { |
| 168 | case WDIOC_GETSUPPORT: | 168 | case WDIOC_GETSUPPORT: |
| 169 | if (copy_to_user((void *)arg, &ident, sizeof(ident))) | 169 | return copy_to_user(p, &ident, sizeof(ident)) ? -EFAULT : 0; |
| 170 | return -EFAULT; | ||
| 171 | case WDIOC_GETSTATUS: | 170 | case WDIOC_GETSTATUS: |
| 172 | return put_user(0, p); | 171 | return put_user(0, p); |
| 173 | case WDIOC_GETBOOTSTATUS: | 172 | case WDIOC_GETBOOTSTATUS: |
| 174 | /* XXX: something is clearing TSR */ | 173 | /* XXX: something is clearing TSR */ |
| 175 | tmp = mfspr(SPRN_TSR) & TSR_WRS(3); | 174 | tmp = mfspr(SPRN_TSR) & TSR_WRS(3); |
| 176 | /* returns CARDRESET if last reset was caused by the WDT */ | 175 | /* returns CARDRESET if last reset was caused by the WDT */ |
| 177 | return (tmp ? WDIOF_CARDRESET : 0); | 176 | return put_user((tmp ? WDIOF_CARDRESET : 0), p); |
| 178 | case WDIOC_SETOPTIONS: | 177 | case WDIOC_SETOPTIONS: |
| 179 | if (get_user(tmp, p)) | 178 | if (get_user(tmp, p)) |
| 180 | return -EINVAL; | 179 | return -EFAULT; |
| 181 | if (tmp == WDIOS_ENABLECARD) { | 180 | if (tmp == WDIOS_ENABLECARD) { |
| 182 | booke_wdt_ping(); | 181 | booke_wdt_ping(); |
| 183 | break; | 182 | break; |
diff --git a/drivers/watchdog/da9052_wdt.c b/drivers/watchdog/da9052_wdt.c index 3f75129eb0a9..f7abbaeebcaf 100644 --- a/drivers/watchdog/da9052_wdt.c +++ b/drivers/watchdog/da9052_wdt.c | |||
| @@ -21,7 +21,6 @@ | |||
| 21 | #include <linux/types.h> | 21 | #include <linux/types.h> |
| 22 | #include <linux/kernel.h> | 22 | #include <linux/kernel.h> |
| 23 | #include <linux/jiffies.h> | 23 | #include <linux/jiffies.h> |
| 24 | #include <linux/delay.h> | ||
| 25 | 24 | ||
| 26 | #include <linux/mfd/da9052/reg.h> | 25 | #include <linux/mfd/da9052/reg.h> |
| 27 | #include <linux/mfd/da9052/da9052.h> | 26 | #include <linux/mfd/da9052/da9052.h> |
diff --git a/drivers/xen/platform-pci.c b/drivers/xen/platform-pci.c index d4c50d63acbc..97ca359ae2bd 100644 --- a/drivers/xen/platform-pci.c +++ b/drivers/xen/platform-pci.c | |||
| @@ -101,19 +101,6 @@ static int platform_pci_resume(struct pci_dev *pdev) | |||
| 101 | return 0; | 101 | return 0; |
| 102 | } | 102 | } |
| 103 | 103 | ||
| 104 | static void __devinit prepare_shared_info(void) | ||
| 105 | { | ||
| 106 | #ifdef CONFIG_KEXEC | ||
| 107 | unsigned long addr; | ||
| 108 | struct shared_info *hvm_shared_info; | ||
| 109 | |||
| 110 | addr = alloc_xen_mmio(PAGE_SIZE); | ||
| 111 | hvm_shared_info = ioremap(addr, PAGE_SIZE); | ||
| 112 | memset(hvm_shared_info, 0, PAGE_SIZE); | ||
| 113 | xen_hvm_prepare_kexec(hvm_shared_info, addr >> PAGE_SHIFT); | ||
| 114 | #endif | ||
| 115 | } | ||
| 116 | |||
| 117 | static int __devinit platform_pci_init(struct pci_dev *pdev, | 104 | static int __devinit platform_pci_init(struct pci_dev *pdev, |
| 118 | const struct pci_device_id *ent) | 105 | const struct pci_device_id *ent) |
| 119 | { | 106 | { |
| @@ -151,8 +138,6 @@ static int __devinit platform_pci_init(struct pci_dev *pdev, | |||
| 151 | platform_mmio = mmio_addr; | 138 | platform_mmio = mmio_addr; |
| 152 | platform_mmiolen = mmio_len; | 139 | platform_mmiolen = mmio_len; |
| 153 | 140 | ||
| 154 | prepare_shared_info(); | ||
| 155 | |||
| 156 | if (!xen_have_vector_callback) { | 141 | if (!xen_have_vector_callback) { |
| 157 | ret = xen_allocate_irq(pdev); | 142 | ret = xen_allocate_irq(pdev); |
| 158 | if (ret) { | 143 | if (ret) { |
| @@ -73,7 +73,7 @@ static struct kmem_cache *bio_find_or_create_slab(unsigned int extra_size) | |||
| 73 | { | 73 | { |
| 74 | unsigned int sz = sizeof(struct bio) + extra_size; | 74 | unsigned int sz = sizeof(struct bio) + extra_size; |
| 75 | struct kmem_cache *slab = NULL; | 75 | struct kmem_cache *slab = NULL; |
| 76 | struct bio_slab *bslab; | 76 | struct bio_slab *bslab, *new_bio_slabs; |
| 77 | unsigned int i, entry = -1; | 77 | unsigned int i, entry = -1; |
| 78 | 78 | ||
| 79 | mutex_lock(&bio_slab_lock); | 79 | mutex_lock(&bio_slab_lock); |
| @@ -97,11 +97,12 @@ static struct kmem_cache *bio_find_or_create_slab(unsigned int extra_size) | |||
| 97 | 97 | ||
| 98 | if (bio_slab_nr == bio_slab_max && entry == -1) { | 98 | if (bio_slab_nr == bio_slab_max && entry == -1) { |
| 99 | bio_slab_max <<= 1; | 99 | bio_slab_max <<= 1; |
| 100 | bio_slabs = krealloc(bio_slabs, | 100 | new_bio_slabs = krealloc(bio_slabs, |
| 101 | bio_slab_max * sizeof(struct bio_slab), | 101 | bio_slab_max * sizeof(struct bio_slab), |
| 102 | GFP_KERNEL); | 102 | GFP_KERNEL); |
| 103 | if (!bio_slabs) | 103 | if (!new_bio_slabs) |
| 104 | goto out_unlock; | 104 | goto out_unlock; |
| 105 | bio_slabs = new_bio_slabs; | ||
| 105 | } | 106 | } |
| 106 | if (entry == -1) | 107 | if (entry == -1) |
| 107 | entry = bio_slab_nr++; | 108 | entry = bio_slab_nr++; |
diff --git a/fs/block_dev.c b/fs/block_dev.c index 1e519195d45b..38e721b35d45 100644 --- a/fs/block_dev.c +++ b/fs/block_dev.c | |||
| @@ -1578,10 +1578,12 @@ ssize_t blkdev_aio_write(struct kiocb *iocb, const struct iovec *iov, | |||
| 1578 | unsigned long nr_segs, loff_t pos) | 1578 | unsigned long nr_segs, loff_t pos) |
| 1579 | { | 1579 | { |
| 1580 | struct file *file = iocb->ki_filp; | 1580 | struct file *file = iocb->ki_filp; |
| 1581 | struct blk_plug plug; | ||
| 1581 | ssize_t ret; | 1582 | ssize_t ret; |
| 1582 | 1583 | ||
| 1583 | BUG_ON(iocb->ki_pos != pos); | 1584 | BUG_ON(iocb->ki_pos != pos); |
| 1584 | 1585 | ||
| 1586 | blk_start_plug(&plug); | ||
| 1585 | ret = __generic_file_aio_write(iocb, iov, nr_segs, &iocb->ki_pos); | 1587 | ret = __generic_file_aio_write(iocb, iov, nr_segs, &iocb->ki_pos); |
| 1586 | if (ret > 0 || ret == -EIOCBQUEUED) { | 1588 | if (ret > 0 || ret == -EIOCBQUEUED) { |
| 1587 | ssize_t err; | 1589 | ssize_t err; |
| @@ -1590,6 +1592,7 @@ ssize_t blkdev_aio_write(struct kiocb *iocb, const struct iovec *iov, | |||
| 1590 | if (err < 0 && ret > 0) | 1592 | if (err < 0 && ret > 0) |
| 1591 | ret = err; | 1593 | ret = err; |
| 1592 | } | 1594 | } |
| 1595 | blk_finish_plug(&plug); | ||
| 1593 | return ret; | 1596 | return ret; |
| 1594 | } | 1597 | } |
| 1595 | EXPORT_SYMBOL_GPL(blkdev_aio_write); | 1598 | EXPORT_SYMBOL_GPL(blkdev_aio_write); |
diff --git a/fs/btrfs/backref.c b/fs/btrfs/backref.c index a256f3b2a845..ff6475f409d6 100644 --- a/fs/btrfs/backref.c +++ b/fs/btrfs/backref.c | |||
| @@ -1438,10 +1438,10 @@ int iterate_inodes_from_logical(u64 logical, struct btrfs_fs_info *fs_info, | |||
| 1438 | ret = extent_from_logical(fs_info, logical, path, | 1438 | ret = extent_from_logical(fs_info, logical, path, |
| 1439 | &found_key); | 1439 | &found_key); |
| 1440 | btrfs_release_path(path); | 1440 | btrfs_release_path(path); |
| 1441 | if (ret & BTRFS_EXTENT_FLAG_TREE_BLOCK) | ||
| 1442 | ret = -EINVAL; | ||
| 1443 | if (ret < 0) | 1441 | if (ret < 0) |
| 1444 | return ret; | 1442 | return ret; |
| 1443 | if (ret & BTRFS_EXTENT_FLAG_TREE_BLOCK) | ||
| 1444 | return -EINVAL; | ||
| 1445 | 1445 | ||
| 1446 | extent_item_pos = logical - found_key.objectid; | 1446 | extent_item_pos = logical - found_key.objectid; |
| 1447 | ret = iterate_extent_inodes(fs_info, found_key.objectid, | 1447 | ret = iterate_extent_inodes(fs_info, found_key.objectid, |
diff --git a/fs/btrfs/compression.c b/fs/btrfs/compression.c index 86eff48dab78..43d1c5a3a030 100644 --- a/fs/btrfs/compression.c +++ b/fs/btrfs/compression.c | |||
| @@ -818,6 +818,7 @@ static void free_workspace(int type, struct list_head *workspace) | |||
| 818 | btrfs_compress_op[idx]->free_workspace(workspace); | 818 | btrfs_compress_op[idx]->free_workspace(workspace); |
| 819 | atomic_dec(alloc_workspace); | 819 | atomic_dec(alloc_workspace); |
| 820 | wake: | 820 | wake: |
| 821 | smp_mb(); | ||
| 821 | if (waitqueue_active(workspace_wait)) | 822 | if (waitqueue_active(workspace_wait)) |
| 822 | wake_up(workspace_wait); | 823 | wake_up(workspace_wait); |
| 823 | } | 824 | } |
diff --git a/fs/btrfs/ctree.c b/fs/btrfs/ctree.c index 9d7621f271ff..6d183f60d63a 100644 --- a/fs/btrfs/ctree.c +++ b/fs/btrfs/ctree.c | |||
| @@ -421,12 +421,6 @@ void btrfs_put_tree_mod_seq(struct btrfs_fs_info *fs_info, | |||
| 421 | spin_unlock(&fs_info->tree_mod_seq_lock); | 421 | spin_unlock(&fs_info->tree_mod_seq_lock); |
| 422 | 422 | ||
| 423 | /* | 423 | /* |
| 424 | * we removed the lowest blocker from the blocker list, so there may be | ||
| 425 | * more processible delayed refs. | ||
| 426 | */ | ||
| 427 | wake_up(&fs_info->tree_mod_seq_wait); | ||
| 428 | |||
| 429 | /* | ||
| 430 | * anything that's lower than the lowest existing (read: blocked) | 424 | * anything that's lower than the lowest existing (read: blocked) |
| 431 | * sequence number can be removed from the tree. | 425 | * sequence number can be removed from the tree. |
| 432 | */ | 426 | */ |
| @@ -631,6 +625,9 @@ __tree_mod_log_free_eb(struct btrfs_fs_info *fs_info, struct extent_buffer *eb) | |||
| 631 | u32 nritems; | 625 | u32 nritems; |
| 632 | int ret; | 626 | int ret; |
| 633 | 627 | ||
| 628 | if (btrfs_header_level(eb) == 0) | ||
| 629 | return; | ||
| 630 | |||
| 634 | nritems = btrfs_header_nritems(eb); | 631 | nritems = btrfs_header_nritems(eb); |
| 635 | for (i = nritems - 1; i >= 0; i--) { | 632 | for (i = nritems - 1; i >= 0; i--) { |
| 636 | ret = tree_mod_log_insert_key_locked(fs_info, eb, i, | 633 | ret = tree_mod_log_insert_key_locked(fs_info, eb, i, |
diff --git a/fs/btrfs/ctree.h b/fs/btrfs/ctree.h index 4bab807227ad..0d195b507660 100644 --- a/fs/btrfs/ctree.h +++ b/fs/btrfs/ctree.h | |||
| @@ -1252,7 +1252,6 @@ struct btrfs_fs_info { | |||
| 1252 | atomic_t tree_mod_seq; | 1252 | atomic_t tree_mod_seq; |
| 1253 | struct list_head tree_mod_seq_list; | 1253 | struct list_head tree_mod_seq_list; |
| 1254 | struct seq_list tree_mod_seq_elem; | 1254 | struct seq_list tree_mod_seq_elem; |
| 1255 | wait_queue_head_t tree_mod_seq_wait; | ||
| 1256 | 1255 | ||
| 1257 | /* this protects tree_mod_log */ | 1256 | /* this protects tree_mod_log */ |
| 1258 | rwlock_t tree_mod_log_lock; | 1257 | rwlock_t tree_mod_log_lock; |
| @@ -3192,7 +3191,7 @@ int btrfs_del_csums(struct btrfs_trans_handle *trans, | |||
| 3192 | int btrfs_lookup_bio_sums(struct btrfs_root *root, struct inode *inode, | 3191 | int btrfs_lookup_bio_sums(struct btrfs_root *root, struct inode *inode, |
| 3193 | struct bio *bio, u32 *dst); | 3192 | struct bio *bio, u32 *dst); |
| 3194 | int btrfs_lookup_bio_sums_dio(struct btrfs_root *root, struct inode *inode, | 3193 | int btrfs_lookup_bio_sums_dio(struct btrfs_root *root, struct inode *inode, |
| 3195 | struct bio *bio, u64 logical_offset, u32 *dst); | 3194 | struct bio *bio, u64 logical_offset); |
| 3196 | int btrfs_insert_file_extent(struct btrfs_trans_handle *trans, | 3195 | int btrfs_insert_file_extent(struct btrfs_trans_handle *trans, |
| 3197 | struct btrfs_root *root, | 3196 | struct btrfs_root *root, |
| 3198 | u64 objectid, u64 pos, | 3197 | u64 objectid, u64 pos, |
diff --git a/fs/btrfs/delayed-inode.c b/fs/btrfs/delayed-inode.c index 335605c8ceab..07d5eeb1e6f1 100644 --- a/fs/btrfs/delayed-inode.c +++ b/fs/btrfs/delayed-inode.c | |||
| @@ -512,8 +512,8 @@ static void __btrfs_remove_delayed_item(struct btrfs_delayed_item *delayed_item) | |||
| 512 | 512 | ||
| 513 | rb_erase(&delayed_item->rb_node, root); | 513 | rb_erase(&delayed_item->rb_node, root); |
| 514 | delayed_item->delayed_node->count--; | 514 | delayed_item->delayed_node->count--; |
| 515 | atomic_dec(&delayed_root->items); | 515 | if (atomic_dec_return(&delayed_root->items) < |
| 516 | if (atomic_read(&delayed_root->items) < BTRFS_DELAYED_BACKGROUND && | 516 | BTRFS_DELAYED_BACKGROUND && |
| 517 | waitqueue_active(&delayed_root->wait)) | 517 | waitqueue_active(&delayed_root->wait)) |
| 518 | wake_up(&delayed_root->wait); | 518 | wake_up(&delayed_root->wait); |
| 519 | } | 519 | } |
| @@ -1028,9 +1028,10 @@ do_again: | |||
| 1028 | btrfs_release_delayed_item(prev); | 1028 | btrfs_release_delayed_item(prev); |
| 1029 | ret = 0; | 1029 | ret = 0; |
| 1030 | btrfs_release_path(path); | 1030 | btrfs_release_path(path); |
| 1031 | if (curr) | 1031 | if (curr) { |
| 1032 | mutex_unlock(&node->mutex); | ||
| 1032 | goto do_again; | 1033 | goto do_again; |
| 1033 | else | 1034 | } else |
| 1034 | goto delete_fail; | 1035 | goto delete_fail; |
| 1035 | } | 1036 | } |
| 1036 | 1037 | ||
| @@ -1055,8 +1056,7 @@ static void btrfs_release_delayed_inode(struct btrfs_delayed_node *delayed_node) | |||
| 1055 | delayed_node->count--; | 1056 | delayed_node->count--; |
| 1056 | 1057 | ||
| 1057 | delayed_root = delayed_node->root->fs_info->delayed_root; | 1058 | delayed_root = delayed_node->root->fs_info->delayed_root; |
| 1058 | atomic_dec(&delayed_root->items); | 1059 | if (atomic_dec_return(&delayed_root->items) < |
| 1059 | if (atomic_read(&delayed_root->items) < | ||
| 1060 | BTRFS_DELAYED_BACKGROUND && | 1060 | BTRFS_DELAYED_BACKGROUND && |
| 1061 | waitqueue_active(&delayed_root->wait)) | 1061 | waitqueue_active(&delayed_root->wait)) |
| 1062 | wake_up(&delayed_root->wait); | 1062 | wake_up(&delayed_root->wait); |
diff --git a/fs/btrfs/delayed-ref.c b/fs/btrfs/delayed-ref.c index da7419ed01bb..ae9411773397 100644 --- a/fs/btrfs/delayed-ref.c +++ b/fs/btrfs/delayed-ref.c | |||
| @@ -38,17 +38,14 @@ | |||
| 38 | static int comp_tree_refs(struct btrfs_delayed_tree_ref *ref2, | 38 | static int comp_tree_refs(struct btrfs_delayed_tree_ref *ref2, |
| 39 | struct btrfs_delayed_tree_ref *ref1) | 39 | struct btrfs_delayed_tree_ref *ref1) |
| 40 | { | 40 | { |
| 41 | if (ref1->node.type == BTRFS_TREE_BLOCK_REF_KEY) { | 41 | if (ref1->root < ref2->root) |
| 42 | if (ref1->root < ref2->root) | 42 | return -1; |
| 43 | return -1; | 43 | if (ref1->root > ref2->root) |
| 44 | if (ref1->root > ref2->root) | 44 | return 1; |
| 45 | return 1; | 45 | if (ref1->parent < ref2->parent) |
| 46 | } else { | 46 | return -1; |
| 47 | if (ref1->parent < ref2->parent) | 47 | if (ref1->parent > ref2->parent) |
| 48 | return -1; | 48 | return 1; |
| 49 | if (ref1->parent > ref2->parent) | ||
| 50 | return 1; | ||
| 51 | } | ||
| 52 | return 0; | 49 | return 0; |
| 53 | } | 50 | } |
| 54 | 51 | ||
| @@ -85,7 +82,8 @@ static int comp_data_refs(struct btrfs_delayed_data_ref *ref2, | |||
| 85 | * type of the delayed backrefs and content of delayed backrefs. | 82 | * type of the delayed backrefs and content of delayed backrefs. |
| 86 | */ | 83 | */ |
| 87 | static int comp_entry(struct btrfs_delayed_ref_node *ref2, | 84 | static int comp_entry(struct btrfs_delayed_ref_node *ref2, |
| 88 | struct btrfs_delayed_ref_node *ref1) | 85 | struct btrfs_delayed_ref_node *ref1, |
| 86 | bool compare_seq) | ||
| 89 | { | 87 | { |
| 90 | if (ref1->bytenr < ref2->bytenr) | 88 | if (ref1->bytenr < ref2->bytenr) |
| 91 | return -1; | 89 | return -1; |
| @@ -102,10 +100,12 @@ static int comp_entry(struct btrfs_delayed_ref_node *ref2, | |||
| 102 | if (ref1->type > ref2->type) | 100 | if (ref1->type > ref2->type) |
| 103 | return 1; | 101 | return 1; |
| 104 | /* merging of sequenced refs is not allowed */ | 102 | /* merging of sequenced refs is not allowed */ |
| 105 | if (ref1->seq < ref2->seq) | 103 | if (compare_seq) { |
| 106 | return -1; | 104 | if (ref1->seq < ref2->seq) |
| 107 | if (ref1->seq > ref2->seq) | 105 | return -1; |
| 108 | return 1; | 106 | if (ref1->seq > ref2->seq) |
| 107 | return 1; | ||
| 108 | } | ||
| 109 | if (ref1->type == BTRFS_TREE_BLOCK_REF_KEY || | 109 | if (ref1->type == BTRFS_TREE_BLOCK_REF_KEY || |
| 110 | ref1->type == BTRFS_SHARED_BLOCK_REF_KEY) { | 110 | ref1->type == BTRFS_SHARED_BLOCK_REF_KEY) { |
| 111 | return comp_tree_refs(btrfs_delayed_node_to_tree_ref(ref2), | 111 | return comp_tree_refs(btrfs_delayed_node_to_tree_ref(ref2), |
| @@ -139,7 +139,7 @@ static struct btrfs_delayed_ref_node *tree_insert(struct rb_root *root, | |||
| 139 | entry = rb_entry(parent_node, struct btrfs_delayed_ref_node, | 139 | entry = rb_entry(parent_node, struct btrfs_delayed_ref_node, |
| 140 | rb_node); | 140 | rb_node); |
| 141 | 141 | ||
| 142 | cmp = comp_entry(entry, ins); | 142 | cmp = comp_entry(entry, ins, 1); |
| 143 | if (cmp < 0) | 143 | if (cmp < 0) |
| 144 | p = &(*p)->rb_left; | 144 | p = &(*p)->rb_left; |
| 145 | else if (cmp > 0) | 145 | else if (cmp > 0) |
| @@ -233,6 +233,114 @@ int btrfs_delayed_ref_lock(struct btrfs_trans_handle *trans, | |||
| 233 | return 0; | 233 | return 0; |
| 234 | } | 234 | } |
| 235 | 235 | ||
| 236 | static void inline drop_delayed_ref(struct btrfs_trans_handle *trans, | ||
| 237 | struct btrfs_delayed_ref_root *delayed_refs, | ||
| 238 | struct btrfs_delayed_ref_node *ref) | ||
| 239 | { | ||
| 240 | rb_erase(&ref->rb_node, &delayed_refs->root); | ||
| 241 | ref->in_tree = 0; | ||
| 242 | btrfs_put_delayed_ref(ref); | ||
| 243 | delayed_refs->num_entries--; | ||
| 244 | if (trans->delayed_ref_updates) | ||
| 245 | trans->delayed_ref_updates--; | ||
| 246 | } | ||
| 247 | |||
| 248 | static int merge_ref(struct btrfs_trans_handle *trans, | ||
| 249 | struct btrfs_delayed_ref_root *delayed_refs, | ||
| 250 | struct btrfs_delayed_ref_node *ref, u64 seq) | ||
| 251 | { | ||
| 252 | struct rb_node *node; | ||
| 253 | int merged = 0; | ||
| 254 | int mod = 0; | ||
| 255 | int done = 0; | ||
| 256 | |||
| 257 | node = rb_prev(&ref->rb_node); | ||
| 258 | while (node) { | ||
| 259 | struct btrfs_delayed_ref_node *next; | ||
| 260 | |||
| 261 | next = rb_entry(node, struct btrfs_delayed_ref_node, rb_node); | ||
| 262 | node = rb_prev(node); | ||
| 263 | if (next->bytenr != ref->bytenr) | ||
| 264 | break; | ||
| 265 | if (seq && next->seq >= seq) | ||
| 266 | break; | ||
| 267 | if (comp_entry(ref, next, 0)) | ||
| 268 | continue; | ||
| 269 | |||
| 270 | if (ref->action == next->action) { | ||
| 271 | mod = next->ref_mod; | ||
| 272 | } else { | ||
| 273 | if (ref->ref_mod < next->ref_mod) { | ||
| 274 | struct btrfs_delayed_ref_node *tmp; | ||
| 275 | |||
| 276 | tmp = ref; | ||
| 277 | ref = next; | ||
| 278 | next = tmp; | ||
| 279 | done = 1; | ||
| 280 | } | ||
| 281 | mod = -next->ref_mod; | ||
| 282 | } | ||
| 283 | |||
| 284 | merged++; | ||
| 285 | drop_delayed_ref(trans, delayed_refs, next); | ||
| 286 | ref->ref_mod += mod; | ||
| 287 | if (ref->ref_mod == 0) { | ||
| 288 | drop_delayed_ref(trans, delayed_refs, ref); | ||
| 289 | break; | ||
| 290 | } else { | ||
| 291 | /* | ||
| 292 | * You can't have multiples of the same ref on a tree | ||
| 293 | * block. | ||
| 294 | */ | ||
| 295 | WARN_ON(ref->type == BTRFS_TREE_BLOCK_REF_KEY || | ||
| 296 | ref->type == BTRFS_SHARED_BLOCK_REF_KEY); | ||
| 297 | } | ||
| 298 | |||
| 299 | if (done) | ||
| 300 | break; | ||
| 301 | node = rb_prev(&ref->rb_node); | ||
| 302 | } | ||
| 303 | |||
| 304 | return merged; | ||
| 305 | } | ||
| 306 | |||
| 307 | void btrfs_merge_delayed_refs(struct btrfs_trans_handle *trans, | ||
| 308 | struct btrfs_fs_info *fs_info, | ||
| 309 | struct btrfs_delayed_ref_root *delayed_refs, | ||
| 310 | struct btrfs_delayed_ref_head *head) | ||
| 311 | { | ||
| 312 | struct rb_node *node; | ||
| 313 | u64 seq = 0; | ||
| 314 | |||
| 315 | spin_lock(&fs_info->tree_mod_seq_lock); | ||
| 316 | if (!list_empty(&fs_info->tree_mod_seq_list)) { | ||
| 317 | struct seq_list *elem; | ||
| 318 | |||
| 319 | elem = list_first_entry(&fs_info->tree_mod_seq_list, | ||
| 320 | struct seq_list, list); | ||
| 321 | seq = elem->seq; | ||
| 322 | } | ||
| 323 | spin_unlock(&fs_info->tree_mod_seq_lock); | ||
| 324 | |||
| 325 | node = rb_prev(&head->node.rb_node); | ||
| 326 | while (node) { | ||
| 327 | struct btrfs_delayed_ref_node *ref; | ||
| 328 | |||
| 329 | ref = rb_entry(node, struct btrfs_delayed_ref_node, | ||
| 330 | rb_node); | ||
| 331 | if (ref->bytenr != head->node.bytenr) | ||
| 332 | break; | ||
| 333 | |||
| 334 | /* We can't merge refs that are outside of our seq count */ | ||
| 335 | if (seq && ref->seq >= seq) | ||
| 336 | break; | ||
| 337 | if (merge_ref(trans, delayed_refs, ref, seq)) | ||
| 338 | node = rb_prev(&head->node.rb_node); | ||
| 339 | else | ||
| 340 | node = rb_prev(node); | ||
| 341 | } | ||
| 342 | } | ||
| 343 | |||
| 236 | int btrfs_check_delayed_seq(struct btrfs_fs_info *fs_info, | 344 | int btrfs_check_delayed_seq(struct btrfs_fs_info *fs_info, |
| 237 | struct btrfs_delayed_ref_root *delayed_refs, | 345 | struct btrfs_delayed_ref_root *delayed_refs, |
| 238 | u64 seq) | 346 | u64 seq) |
| @@ -336,18 +444,11 @@ update_existing_ref(struct btrfs_trans_handle *trans, | |||
| 336 | * every changing the extent allocation tree. | 444 | * every changing the extent allocation tree. |
| 337 | */ | 445 | */ |
| 338 | existing->ref_mod--; | 446 | existing->ref_mod--; |
| 339 | if (existing->ref_mod == 0) { | 447 | if (existing->ref_mod == 0) |
| 340 | rb_erase(&existing->rb_node, | 448 | drop_delayed_ref(trans, delayed_refs, existing); |
| 341 | &delayed_refs->root); | 449 | else |
| 342 | existing->in_tree = 0; | ||
| 343 | btrfs_put_delayed_ref(existing); | ||
| 344 | delayed_refs->num_entries--; | ||
| 345 | if (trans->delayed_ref_updates) | ||
| 346 | trans->delayed_ref_updates--; | ||
| 347 | } else { | ||
| 348 | WARN_ON(existing->type == BTRFS_TREE_BLOCK_REF_KEY || | 450 | WARN_ON(existing->type == BTRFS_TREE_BLOCK_REF_KEY || |
| 349 | existing->type == BTRFS_SHARED_BLOCK_REF_KEY); | 451 | existing->type == BTRFS_SHARED_BLOCK_REF_KEY); |
| 350 | } | ||
| 351 | } else { | 452 | } else { |
| 352 | WARN_ON(existing->type == BTRFS_TREE_BLOCK_REF_KEY || | 453 | WARN_ON(existing->type == BTRFS_TREE_BLOCK_REF_KEY || |
| 353 | existing->type == BTRFS_SHARED_BLOCK_REF_KEY); | 454 | existing->type == BTRFS_SHARED_BLOCK_REF_KEY); |
| @@ -662,9 +763,6 @@ int btrfs_add_delayed_tree_ref(struct btrfs_fs_info *fs_info, | |||
| 662 | add_delayed_tree_ref(fs_info, trans, &ref->node, bytenr, | 763 | add_delayed_tree_ref(fs_info, trans, &ref->node, bytenr, |
| 663 | num_bytes, parent, ref_root, level, action, | 764 | num_bytes, parent, ref_root, level, action, |
| 664 | for_cow); | 765 | for_cow); |
| 665 | if (!need_ref_seq(for_cow, ref_root) && | ||
| 666 | waitqueue_active(&fs_info->tree_mod_seq_wait)) | ||
| 667 | wake_up(&fs_info->tree_mod_seq_wait); | ||
| 668 | spin_unlock(&delayed_refs->lock); | 766 | spin_unlock(&delayed_refs->lock); |
| 669 | if (need_ref_seq(for_cow, ref_root)) | 767 | if (need_ref_seq(for_cow, ref_root)) |
| 670 | btrfs_qgroup_record_ref(trans, &ref->node, extent_op); | 768 | btrfs_qgroup_record_ref(trans, &ref->node, extent_op); |
| @@ -713,9 +811,6 @@ int btrfs_add_delayed_data_ref(struct btrfs_fs_info *fs_info, | |||
| 713 | add_delayed_data_ref(fs_info, trans, &ref->node, bytenr, | 811 | add_delayed_data_ref(fs_info, trans, &ref->node, bytenr, |
| 714 | num_bytes, parent, ref_root, owner, offset, | 812 | num_bytes, parent, ref_root, owner, offset, |
| 715 | action, for_cow); | 813 | action, for_cow); |
| 716 | if (!need_ref_seq(for_cow, ref_root) && | ||
| 717 | waitqueue_active(&fs_info->tree_mod_seq_wait)) | ||
| 718 | wake_up(&fs_info->tree_mod_seq_wait); | ||
| 719 | spin_unlock(&delayed_refs->lock); | 814 | spin_unlock(&delayed_refs->lock); |
| 720 | if (need_ref_seq(for_cow, ref_root)) | 815 | if (need_ref_seq(for_cow, ref_root)) |
| 721 | btrfs_qgroup_record_ref(trans, &ref->node, extent_op); | 816 | btrfs_qgroup_record_ref(trans, &ref->node, extent_op); |
| @@ -744,8 +839,6 @@ int btrfs_add_delayed_extent_op(struct btrfs_fs_info *fs_info, | |||
| 744 | num_bytes, BTRFS_UPDATE_DELAYED_HEAD, | 839 | num_bytes, BTRFS_UPDATE_DELAYED_HEAD, |
| 745 | extent_op->is_data); | 840 | extent_op->is_data); |
| 746 | 841 | ||
| 747 | if (waitqueue_active(&fs_info->tree_mod_seq_wait)) | ||
| 748 | wake_up(&fs_info->tree_mod_seq_wait); | ||
| 749 | spin_unlock(&delayed_refs->lock); | 842 | spin_unlock(&delayed_refs->lock); |
| 750 | return 0; | 843 | return 0; |
| 751 | } | 844 | } |
diff --git a/fs/btrfs/delayed-ref.h b/fs/btrfs/delayed-ref.h index 0d7c90c366b6..ab5300595847 100644 --- a/fs/btrfs/delayed-ref.h +++ b/fs/btrfs/delayed-ref.h | |||
| @@ -167,6 +167,10 @@ int btrfs_add_delayed_extent_op(struct btrfs_fs_info *fs_info, | |||
| 167 | struct btrfs_trans_handle *trans, | 167 | struct btrfs_trans_handle *trans, |
| 168 | u64 bytenr, u64 num_bytes, | 168 | u64 bytenr, u64 num_bytes, |
| 169 | struct btrfs_delayed_extent_op *extent_op); | 169 | struct btrfs_delayed_extent_op *extent_op); |
| 170 | void btrfs_merge_delayed_refs(struct btrfs_trans_handle *trans, | ||
| 171 | struct btrfs_fs_info *fs_info, | ||
| 172 | struct btrfs_delayed_ref_root *delayed_refs, | ||
| 173 | struct btrfs_delayed_ref_head *head); | ||
| 170 | 174 | ||
| 171 | struct btrfs_delayed_ref_head * | 175 | struct btrfs_delayed_ref_head * |
| 172 | btrfs_find_delayed_ref_head(struct btrfs_trans_handle *trans, u64 bytenr); | 176 | btrfs_find_delayed_ref_head(struct btrfs_trans_handle *trans, u64 bytenr); |
diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c index 62e0cafd6e25..22e98e04c2ea 100644 --- a/fs/btrfs/disk-io.c +++ b/fs/btrfs/disk-io.c | |||
| @@ -377,9 +377,13 @@ static int btree_read_extent_buffer_pages(struct btrfs_root *root, | |||
| 377 | ret = read_extent_buffer_pages(io_tree, eb, start, | 377 | ret = read_extent_buffer_pages(io_tree, eb, start, |
| 378 | WAIT_COMPLETE, | 378 | WAIT_COMPLETE, |
| 379 | btree_get_extent, mirror_num); | 379 | btree_get_extent, mirror_num); |
| 380 | if (!ret && !verify_parent_transid(io_tree, eb, | 380 | if (!ret) { |
| 381 | if (!verify_parent_transid(io_tree, eb, | ||
| 381 | parent_transid, 0)) | 382 | parent_transid, 0)) |
| 382 | break; | 383 | break; |
| 384 | else | ||
| 385 | ret = -EIO; | ||
| 386 | } | ||
| 383 | 387 | ||
| 384 | /* | 388 | /* |
| 385 | * This buffer's crc is fine, but its contents are corrupted, so | 389 | * This buffer's crc is fine, but its contents are corrupted, so |
| @@ -754,9 +758,7 @@ static void run_one_async_done(struct btrfs_work *work) | |||
| 754 | limit = btrfs_async_submit_limit(fs_info); | 758 | limit = btrfs_async_submit_limit(fs_info); |
| 755 | limit = limit * 2 / 3; | 759 | limit = limit * 2 / 3; |
| 756 | 760 | ||
| 757 | atomic_dec(&fs_info->nr_async_submits); | 761 | if (atomic_dec_return(&fs_info->nr_async_submits) < limit && |
| 758 | |||
| 759 | if (atomic_read(&fs_info->nr_async_submits) < limit && | ||
| 760 | waitqueue_active(&fs_info->async_submit_wait)) | 762 | waitqueue_active(&fs_info->async_submit_wait)) |
| 761 | wake_up(&fs_info->async_submit_wait); | 763 | wake_up(&fs_info->async_submit_wait); |
| 762 | 764 | ||
| @@ -2032,8 +2034,6 @@ int open_ctree(struct super_block *sb, | |||
| 2032 | fs_info->free_chunk_space = 0; | 2034 | fs_info->free_chunk_space = 0; |
| 2033 | fs_info->tree_mod_log = RB_ROOT; | 2035 | fs_info->tree_mod_log = RB_ROOT; |
| 2034 | 2036 | ||
| 2035 | init_waitqueue_head(&fs_info->tree_mod_seq_wait); | ||
| 2036 | |||
| 2037 | /* readahead state */ | 2037 | /* readahead state */ |
| 2038 | INIT_RADIX_TREE(&fs_info->reada_tree, GFP_NOFS & ~__GFP_WAIT); | 2038 | INIT_RADIX_TREE(&fs_info->reada_tree, GFP_NOFS & ~__GFP_WAIT); |
| 2039 | spin_lock_init(&fs_info->reada_lock); | 2039 | spin_lock_init(&fs_info->reada_lock); |
| @@ -2528,8 +2528,7 @@ retry_root_backup: | |||
| 2528 | goto fail_trans_kthread; | 2528 | goto fail_trans_kthread; |
| 2529 | 2529 | ||
| 2530 | /* do not make disk changes in broken FS */ | 2530 | /* do not make disk changes in broken FS */ |
| 2531 | if (btrfs_super_log_root(disk_super) != 0 && | 2531 | if (btrfs_super_log_root(disk_super) != 0) { |
| 2532 | !(fs_info->fs_state & BTRFS_SUPER_FLAG_ERROR)) { | ||
| 2533 | u64 bytenr = btrfs_super_log_root(disk_super); | 2532 | u64 bytenr = btrfs_super_log_root(disk_super); |
| 2534 | 2533 | ||
| 2535 | if (fs_devices->rw_devices == 0) { | 2534 | if (fs_devices->rw_devices == 0) { |
| @@ -3189,30 +3188,14 @@ int close_ctree(struct btrfs_root *root) | |||
| 3189 | /* clear out the rbtree of defraggable inodes */ | 3188 | /* clear out the rbtree of defraggable inodes */ |
| 3190 | btrfs_run_defrag_inodes(fs_info); | 3189 | btrfs_run_defrag_inodes(fs_info); |
| 3191 | 3190 | ||
| 3192 | /* | ||
| 3193 | * Here come 2 situations when btrfs is broken to flip readonly: | ||
| 3194 | * | ||
| 3195 | * 1. when btrfs flips readonly somewhere else before | ||
| 3196 | * btrfs_commit_super, sb->s_flags has MS_RDONLY flag, | ||
| 3197 | * and btrfs will skip to write sb directly to keep | ||
| 3198 | * ERROR state on disk. | ||
| 3199 | * | ||
| 3200 | * 2. when btrfs flips readonly just in btrfs_commit_super, | ||
| 3201 | * and in such case, btrfs cannot write sb via btrfs_commit_super, | ||
| 3202 | * and since fs_state has been set BTRFS_SUPER_FLAG_ERROR flag, | ||
| 3203 | * btrfs will cleanup all FS resources first and write sb then. | ||
| 3204 | */ | ||
| 3205 | if (!(fs_info->sb->s_flags & MS_RDONLY)) { | 3191 | if (!(fs_info->sb->s_flags & MS_RDONLY)) { |
| 3206 | ret = btrfs_commit_super(root); | 3192 | ret = btrfs_commit_super(root); |
| 3207 | if (ret) | 3193 | if (ret) |
| 3208 | printk(KERN_ERR "btrfs: commit super ret %d\n", ret); | 3194 | printk(KERN_ERR "btrfs: commit super ret %d\n", ret); |
| 3209 | } | 3195 | } |
| 3210 | 3196 | ||
| 3211 | if (fs_info->fs_state & BTRFS_SUPER_FLAG_ERROR) { | 3197 | if (fs_info->fs_state & BTRFS_SUPER_FLAG_ERROR) |
| 3212 | ret = btrfs_error_commit_super(root); | 3198 | btrfs_error_commit_super(root); |
| 3213 | if (ret) | ||
| 3214 | printk(KERN_ERR "btrfs: commit super ret %d\n", ret); | ||
| 3215 | } | ||
| 3216 | 3199 | ||
| 3217 | btrfs_put_block_group_cache(fs_info); | 3200 | btrfs_put_block_group_cache(fs_info); |
| 3218 | 3201 | ||
| @@ -3434,18 +3417,11 @@ static int btrfs_check_super_valid(struct btrfs_fs_info *fs_info, | |||
| 3434 | if (read_only) | 3417 | if (read_only) |
| 3435 | return 0; | 3418 | return 0; |
| 3436 | 3419 | ||
| 3437 | if (fs_info->fs_state & BTRFS_SUPER_FLAG_ERROR) { | ||
| 3438 | printk(KERN_WARNING "warning: mount fs with errors, " | ||
| 3439 | "running btrfsck is recommended\n"); | ||
| 3440 | } | ||
| 3441 | |||
| 3442 | return 0; | 3420 | return 0; |
| 3443 | } | 3421 | } |
| 3444 | 3422 | ||
| 3445 | int btrfs_error_commit_super(struct btrfs_root *root) | 3423 | void btrfs_error_commit_super(struct btrfs_root *root) |
| 3446 | { | 3424 | { |
| 3447 | int ret; | ||
| 3448 | |||
| 3449 | mutex_lock(&root->fs_info->cleaner_mutex); | 3425 | mutex_lock(&root->fs_info->cleaner_mutex); |
| 3450 | btrfs_run_delayed_iputs(root); | 3426 | btrfs_run_delayed_iputs(root); |
| 3451 | mutex_unlock(&root->fs_info->cleaner_mutex); | 3427 | mutex_unlock(&root->fs_info->cleaner_mutex); |
| @@ -3455,10 +3431,6 @@ int btrfs_error_commit_super(struct btrfs_root *root) | |||
| 3455 | 3431 | ||
| 3456 | /* cleanup FS via transaction */ | 3432 | /* cleanup FS via transaction */ |
| 3457 | btrfs_cleanup_transaction(root); | 3433 | btrfs_cleanup_transaction(root); |
| 3458 | |||
| 3459 | ret = write_ctree_super(NULL, root, 0); | ||
| 3460 | |||
| 3461 | return ret; | ||
| 3462 | } | 3434 | } |
| 3463 | 3435 | ||
| 3464 | static void btrfs_destroy_ordered_operations(struct btrfs_root *root) | 3436 | static void btrfs_destroy_ordered_operations(struct btrfs_root *root) |
| @@ -3782,14 +3754,17 @@ int btrfs_cleanup_transaction(struct btrfs_root *root) | |||
| 3782 | /* FIXME: cleanup wait for commit */ | 3754 | /* FIXME: cleanup wait for commit */ |
| 3783 | t->in_commit = 1; | 3755 | t->in_commit = 1; |
| 3784 | t->blocked = 1; | 3756 | t->blocked = 1; |
| 3757 | smp_mb(); | ||
| 3785 | if (waitqueue_active(&root->fs_info->transaction_blocked_wait)) | 3758 | if (waitqueue_active(&root->fs_info->transaction_blocked_wait)) |
| 3786 | wake_up(&root->fs_info->transaction_blocked_wait); | 3759 | wake_up(&root->fs_info->transaction_blocked_wait); |
| 3787 | 3760 | ||
| 3788 | t->blocked = 0; | 3761 | t->blocked = 0; |
| 3762 | smp_mb(); | ||
| 3789 | if (waitqueue_active(&root->fs_info->transaction_wait)) | 3763 | if (waitqueue_active(&root->fs_info->transaction_wait)) |
| 3790 | wake_up(&root->fs_info->transaction_wait); | 3764 | wake_up(&root->fs_info->transaction_wait); |
| 3791 | 3765 | ||
| 3792 | t->commit_done = 1; | 3766 | t->commit_done = 1; |
| 3767 | smp_mb(); | ||
| 3793 | if (waitqueue_active(&t->commit_wait)) | 3768 | if (waitqueue_active(&t->commit_wait)) |
| 3794 | wake_up(&t->commit_wait); | 3769 | wake_up(&t->commit_wait); |
| 3795 | 3770 | ||
diff --git a/fs/btrfs/disk-io.h b/fs/btrfs/disk-io.h index 95e147eea239..c5b00a735fef 100644 --- a/fs/btrfs/disk-io.h +++ b/fs/btrfs/disk-io.h | |||
| @@ -54,7 +54,7 @@ int write_ctree_super(struct btrfs_trans_handle *trans, | |||
| 54 | struct btrfs_root *root, int max_mirrors); | 54 | struct btrfs_root *root, int max_mirrors); |
| 55 | struct buffer_head *btrfs_read_dev_super(struct block_device *bdev); | 55 | struct buffer_head *btrfs_read_dev_super(struct block_device *bdev); |
| 56 | int btrfs_commit_super(struct btrfs_root *root); | 56 | int btrfs_commit_super(struct btrfs_root *root); |
| 57 | int btrfs_error_commit_super(struct btrfs_root *root); | 57 | void btrfs_error_commit_super(struct btrfs_root *root); |
| 58 | struct extent_buffer *btrfs_find_tree_block(struct btrfs_root *root, | 58 | struct extent_buffer *btrfs_find_tree_block(struct btrfs_root *root, |
| 59 | u64 bytenr, u32 blocksize); | 59 | u64 bytenr, u32 blocksize); |
| 60 | struct btrfs_root *btrfs_read_fs_root_no_radix(struct btrfs_root *tree_root, | 60 | struct btrfs_root *btrfs_read_fs_root_no_radix(struct btrfs_root *tree_root, |
diff --git a/fs/btrfs/extent-tree.c b/fs/btrfs/extent-tree.c index 4e1b153b7c47..ba58024d40d3 100644 --- a/fs/btrfs/extent-tree.c +++ b/fs/btrfs/extent-tree.c | |||
| @@ -2252,6 +2252,16 @@ static noinline int run_clustered_refs(struct btrfs_trans_handle *trans, | |||
| 2252 | } | 2252 | } |
| 2253 | 2253 | ||
| 2254 | /* | 2254 | /* |
| 2255 | * We need to try and merge add/drops of the same ref since we | ||
| 2256 | * can run into issues with relocate dropping the implicit ref | ||
| 2257 | * and then it being added back again before the drop can | ||
| 2258 | * finish. If we merged anything we need to re-loop so we can | ||
| 2259 | * get a good ref. | ||
| 2260 | */ | ||
| 2261 | btrfs_merge_delayed_refs(trans, fs_info, delayed_refs, | ||
| 2262 | locked_ref); | ||
| 2263 | |||
| 2264 | /* | ||
| 2255 | * locked_ref is the head node, so we have to go one | 2265 | * locked_ref is the head node, so we have to go one |
| 2256 | * node back for any delayed ref updates | 2266 | * node back for any delayed ref updates |
| 2257 | */ | 2267 | */ |
| @@ -2318,12 +2328,23 @@ static noinline int run_clustered_refs(struct btrfs_trans_handle *trans, | |||
| 2318 | ref->in_tree = 0; | 2328 | ref->in_tree = 0; |
| 2319 | rb_erase(&ref->rb_node, &delayed_refs->root); | 2329 | rb_erase(&ref->rb_node, &delayed_refs->root); |
| 2320 | delayed_refs->num_entries--; | 2330 | delayed_refs->num_entries--; |
| 2321 | /* | 2331 | if (locked_ref) { |
| 2322 | * we modified num_entries, but as we're currently running | 2332 | /* |
| 2323 | * delayed refs, skip | 2333 | * when we play the delayed ref, also correct the |
| 2324 | * wake_up(&delayed_refs->seq_wait); | 2334 | * ref_mod on head |
| 2325 | * here. | 2335 | */ |
| 2326 | */ | 2336 | switch (ref->action) { |
| 2337 | case BTRFS_ADD_DELAYED_REF: | ||
| 2338 | case BTRFS_ADD_DELAYED_EXTENT: | ||
| 2339 | locked_ref->node.ref_mod -= ref->ref_mod; | ||
| 2340 | break; | ||
| 2341 | case BTRFS_DROP_DELAYED_REF: | ||
| 2342 | locked_ref->node.ref_mod += ref->ref_mod; | ||
| 2343 | break; | ||
| 2344 | default: | ||
| 2345 | WARN_ON(1); | ||
| 2346 | } | ||
| 2347 | } | ||
| 2327 | spin_unlock(&delayed_refs->lock); | 2348 | spin_unlock(&delayed_refs->lock); |
| 2328 | 2349 | ||
| 2329 | ret = run_one_delayed_ref(trans, root, ref, extent_op, | 2350 | ret = run_one_delayed_ref(trans, root, ref, extent_op, |
| @@ -2350,22 +2371,6 @@ next: | |||
| 2350 | return count; | 2371 | return count; |
| 2351 | } | 2372 | } |
| 2352 | 2373 | ||
| 2353 | static void wait_for_more_refs(struct btrfs_fs_info *fs_info, | ||
| 2354 | struct btrfs_delayed_ref_root *delayed_refs, | ||
| 2355 | unsigned long num_refs, | ||
| 2356 | struct list_head *first_seq) | ||
| 2357 | { | ||
| 2358 | spin_unlock(&delayed_refs->lock); | ||
| 2359 | pr_debug("waiting for more refs (num %ld, first %p)\n", | ||
| 2360 | num_refs, first_seq); | ||
| 2361 | wait_event(fs_info->tree_mod_seq_wait, | ||
| 2362 | num_refs != delayed_refs->num_entries || | ||
| 2363 | fs_info->tree_mod_seq_list.next != first_seq); | ||
| 2364 | pr_debug("done waiting for more refs (num %ld, first %p)\n", | ||
| 2365 | delayed_refs->num_entries, fs_info->tree_mod_seq_list.next); | ||
| 2366 | spin_lock(&delayed_refs->lock); | ||
| 2367 | } | ||
| 2368 | |||
| 2369 | #ifdef SCRAMBLE_DELAYED_REFS | 2374 | #ifdef SCRAMBLE_DELAYED_REFS |
| 2370 | /* | 2375 | /* |
| 2371 | * Normally delayed refs get processed in ascending bytenr order. This | 2376 | * Normally delayed refs get processed in ascending bytenr order. This |
| @@ -2460,13 +2465,11 @@ int btrfs_run_delayed_refs(struct btrfs_trans_handle *trans, | |||
| 2460 | struct btrfs_delayed_ref_root *delayed_refs; | 2465 | struct btrfs_delayed_ref_root *delayed_refs; |
| 2461 | struct btrfs_delayed_ref_node *ref; | 2466 | struct btrfs_delayed_ref_node *ref; |
| 2462 | struct list_head cluster; | 2467 | struct list_head cluster; |
| 2463 | struct list_head *first_seq = NULL; | ||
| 2464 | int ret; | 2468 | int ret; |
| 2465 | u64 delayed_start; | 2469 | u64 delayed_start; |
| 2466 | int run_all = count == (unsigned long)-1; | 2470 | int run_all = count == (unsigned long)-1; |
| 2467 | int run_most = 0; | 2471 | int run_most = 0; |
| 2468 | unsigned long num_refs = 0; | 2472 | int loops; |
| 2469 | int consider_waiting; | ||
| 2470 | 2473 | ||
| 2471 | /* We'll clean this up in btrfs_cleanup_transaction */ | 2474 | /* We'll clean this up in btrfs_cleanup_transaction */ |
| 2472 | if (trans->aborted) | 2475 | if (trans->aborted) |
| @@ -2484,7 +2487,7 @@ int btrfs_run_delayed_refs(struct btrfs_trans_handle *trans, | |||
| 2484 | delayed_refs = &trans->transaction->delayed_refs; | 2487 | delayed_refs = &trans->transaction->delayed_refs; |
| 2485 | INIT_LIST_HEAD(&cluster); | 2488 | INIT_LIST_HEAD(&cluster); |
| 2486 | again: | 2489 | again: |
| 2487 | consider_waiting = 0; | 2490 | loops = 0; |
| 2488 | spin_lock(&delayed_refs->lock); | 2491 | spin_lock(&delayed_refs->lock); |
| 2489 | 2492 | ||
| 2490 | #ifdef SCRAMBLE_DELAYED_REFS | 2493 | #ifdef SCRAMBLE_DELAYED_REFS |
| @@ -2512,31 +2515,6 @@ again: | |||
| 2512 | if (ret) | 2515 | if (ret) |
| 2513 | break; | 2516 | break; |
| 2514 | 2517 | ||
| 2515 | if (delayed_start >= delayed_refs->run_delayed_start) { | ||
| 2516 | if (consider_waiting == 0) { | ||
| 2517 | /* | ||
| 2518 | * btrfs_find_ref_cluster looped. let's do one | ||
| 2519 | * more cycle. if we don't run any delayed ref | ||
| 2520 | * during that cycle (because we can't because | ||
| 2521 | * all of them are blocked) and if the number of | ||
| 2522 | * refs doesn't change, we avoid busy waiting. | ||
| 2523 | */ | ||
| 2524 | consider_waiting = 1; | ||
| 2525 | num_refs = delayed_refs->num_entries; | ||
| 2526 | first_seq = root->fs_info->tree_mod_seq_list.next; | ||
| 2527 | } else { | ||
| 2528 | wait_for_more_refs(root->fs_info, delayed_refs, | ||
| 2529 | num_refs, first_seq); | ||
| 2530 | /* | ||
| 2531 | * after waiting, things have changed. we | ||
| 2532 | * dropped the lock and someone else might have | ||
| 2533 | * run some refs, built new clusters and so on. | ||
| 2534 | * therefore, we restart staleness detection. | ||
| 2535 | */ | ||
| 2536 | consider_waiting = 0; | ||
| 2537 | } | ||
| 2538 | } | ||
| 2539 | |||
| 2540 | ret = run_clustered_refs(trans, root, &cluster); | 2518 | ret = run_clustered_refs(trans, root, &cluster); |
| 2541 | if (ret < 0) { | 2519 | if (ret < 0) { |
| 2542 | spin_unlock(&delayed_refs->lock); | 2520 | spin_unlock(&delayed_refs->lock); |
| @@ -2549,9 +2527,26 @@ again: | |||
| 2549 | if (count == 0) | 2527 | if (count == 0) |
| 2550 | break; | 2528 | break; |
| 2551 | 2529 | ||
| 2552 | if (ret || delayed_refs->run_delayed_start == 0) { | 2530 | if (delayed_start >= delayed_refs->run_delayed_start) { |
| 2531 | if (loops == 0) { | ||
| 2532 | /* | ||
| 2533 | * btrfs_find_ref_cluster looped. let's do one | ||
| 2534 | * more cycle. if we don't run any delayed ref | ||
| 2535 | * during that cycle (because we can't because | ||
| 2536 | * all of them are blocked), bail out. | ||
| 2537 | */ | ||
| 2538 | loops = 1; | ||
| 2539 | } else { | ||
| 2540 | /* | ||
| 2541 | * no runnable refs left, stop trying | ||
| 2542 | */ | ||
| 2543 | BUG_ON(run_all); | ||
| 2544 | break; | ||
| 2545 | } | ||
| 2546 | } | ||
| 2547 | if (ret) { | ||
| 2553 | /* refs were run, let's reset staleness detection */ | 2548 | /* refs were run, let's reset staleness detection */ |
| 2554 | consider_waiting = 0; | 2549 | loops = 0; |
| 2555 | } | 2550 | } |
| 2556 | } | 2551 | } |
| 2557 | 2552 | ||
| @@ -3007,17 +3002,16 @@ again: | |||
| 3007 | } | 3002 | } |
| 3008 | spin_unlock(&block_group->lock); | 3003 | spin_unlock(&block_group->lock); |
| 3009 | 3004 | ||
| 3010 | num_pages = (int)div64_u64(block_group->key.offset, 1024 * 1024 * 1024); | 3005 | /* |
| 3006 | * Try to preallocate enough space based on how big the block group is. | ||
| 3007 | * Keep in mind this has to include any pinned space which could end up | ||
| 3008 | * taking up quite a bit since it's not folded into the other space | ||
| 3009 | * cache. | ||
| 3010 | */ | ||
| 3011 | num_pages = (int)div64_u64(block_group->key.offset, 256 * 1024 * 1024); | ||
| 3011 | if (!num_pages) | 3012 | if (!num_pages) |
| 3012 | num_pages = 1; | 3013 | num_pages = 1; |
| 3013 | 3014 | ||
| 3014 | /* | ||
| 3015 | * Just to make absolutely sure we have enough space, we're going to | ||
| 3016 | * preallocate 12 pages worth of space for each block group. In | ||
| 3017 | * practice we ought to use at most 8, but we need extra space so we can | ||
| 3018 | * add our header and have a terminator between the extents and the | ||
| 3019 | * bitmaps. | ||
| 3020 | */ | ||
| 3021 | num_pages *= 16; | 3015 | num_pages *= 16; |
| 3022 | num_pages *= PAGE_CACHE_SIZE; | 3016 | num_pages *= PAGE_CACHE_SIZE; |
| 3023 | 3017 | ||
| @@ -4571,8 +4565,10 @@ int btrfs_delalloc_reserve_metadata(struct inode *inode, u64 num_bytes) | |||
| 4571 | if (root->fs_info->quota_enabled) { | 4565 | if (root->fs_info->quota_enabled) { |
| 4572 | ret = btrfs_qgroup_reserve(root, num_bytes + | 4566 | ret = btrfs_qgroup_reserve(root, num_bytes + |
| 4573 | nr_extents * root->leafsize); | 4567 | nr_extents * root->leafsize); |
| 4574 | if (ret) | 4568 | if (ret) { |
| 4569 | mutex_unlock(&BTRFS_I(inode)->delalloc_mutex); | ||
| 4575 | return ret; | 4570 | return ret; |
| 4571 | } | ||
| 4576 | } | 4572 | } |
| 4577 | 4573 | ||
| 4578 | ret = reserve_metadata_bytes(root, block_rsv, to_reserve, flush); | 4574 | ret = reserve_metadata_bytes(root, block_rsv, to_reserve, flush); |
| @@ -5294,9 +5290,6 @@ static noinline int check_ref_cleanup(struct btrfs_trans_handle *trans, | |||
| 5294 | rb_erase(&head->node.rb_node, &delayed_refs->root); | 5290 | rb_erase(&head->node.rb_node, &delayed_refs->root); |
| 5295 | 5291 | ||
| 5296 | delayed_refs->num_entries--; | 5292 | delayed_refs->num_entries--; |
| 5297 | smp_mb(); | ||
| 5298 | if (waitqueue_active(&root->fs_info->tree_mod_seq_wait)) | ||
| 5299 | wake_up(&root->fs_info->tree_mod_seq_wait); | ||
| 5300 | 5293 | ||
| 5301 | /* | 5294 | /* |
| 5302 | * we don't take a ref on the node because we're removing it from the | 5295 | * we don't take a ref on the node because we're removing it from the |
diff --git a/fs/btrfs/extent_io.c b/fs/btrfs/extent_io.c index 45c81bb4ac82..4c878476bb91 100644 --- a/fs/btrfs/extent_io.c +++ b/fs/btrfs/extent_io.c | |||
| @@ -2330,23 +2330,10 @@ static void end_bio_extent_readpage(struct bio *bio, int err) | |||
| 2330 | if (uptodate && tree->ops && tree->ops->readpage_end_io_hook) { | 2330 | if (uptodate && tree->ops && tree->ops->readpage_end_io_hook) { |
| 2331 | ret = tree->ops->readpage_end_io_hook(page, start, end, | 2331 | ret = tree->ops->readpage_end_io_hook(page, start, end, |
| 2332 | state, mirror); | 2332 | state, mirror); |
| 2333 | if (ret) { | 2333 | if (ret) |
| 2334 | /* no IO indicated but software detected errors | ||
| 2335 | * in the block, either checksum errors or | ||
| 2336 | * issues with the contents */ | ||
| 2337 | struct btrfs_root *root = | ||
| 2338 | BTRFS_I(page->mapping->host)->root; | ||
| 2339 | struct btrfs_device *device; | ||
| 2340 | |||
| 2341 | uptodate = 0; | 2334 | uptodate = 0; |
| 2342 | device = btrfs_find_device_for_logical( | 2335 | else |
| 2343 | root, start, mirror); | ||
| 2344 | if (device) | ||
| 2345 | btrfs_dev_stat_inc_and_print(device, | ||
| 2346 | BTRFS_DEV_STAT_CORRUPTION_ERRS); | ||
| 2347 | } else { | ||
| 2348 | clean_io_failure(start, page); | 2336 | clean_io_failure(start, page); |
| 2349 | } | ||
| 2350 | } | 2337 | } |
| 2351 | 2338 | ||
| 2352 | if (!uptodate && tree->ops && tree->ops->readpage_io_failed_hook) { | 2339 | if (!uptodate && tree->ops && tree->ops->readpage_io_failed_hook) { |
diff --git a/fs/btrfs/file-item.c b/fs/btrfs/file-item.c index b45b9de0c21d..857d93cd01dc 100644 --- a/fs/btrfs/file-item.c +++ b/fs/btrfs/file-item.c | |||
| @@ -272,9 +272,9 @@ int btrfs_lookup_bio_sums(struct btrfs_root *root, struct inode *inode, | |||
| 272 | } | 272 | } |
| 273 | 273 | ||
| 274 | int btrfs_lookup_bio_sums_dio(struct btrfs_root *root, struct inode *inode, | 274 | int btrfs_lookup_bio_sums_dio(struct btrfs_root *root, struct inode *inode, |
| 275 | struct bio *bio, u64 offset, u32 *dst) | 275 | struct bio *bio, u64 offset) |
| 276 | { | 276 | { |
| 277 | return __btrfs_lookup_bio_sums(root, inode, bio, offset, dst, 1); | 277 | return __btrfs_lookup_bio_sums(root, inode, bio, offset, NULL, 1); |
| 278 | } | 278 | } |
| 279 | 279 | ||
| 280 | int btrfs_lookup_csums_range(struct btrfs_root *root, u64 start, u64 end, | 280 | int btrfs_lookup_csums_range(struct btrfs_root *root, u64 start, u64 end, |
diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c index 6e8f416773d4..ec154f954646 100644 --- a/fs/btrfs/inode.c +++ b/fs/btrfs/inode.c | |||
| @@ -1008,9 +1008,7 @@ static noinline void async_cow_submit(struct btrfs_work *work) | |||
| 1008 | nr_pages = (async_cow->end - async_cow->start + PAGE_CACHE_SIZE) >> | 1008 | nr_pages = (async_cow->end - async_cow->start + PAGE_CACHE_SIZE) >> |
| 1009 | PAGE_CACHE_SHIFT; | 1009 | PAGE_CACHE_SHIFT; |
| 1010 | 1010 | ||
| 1011 | atomic_sub(nr_pages, &root->fs_info->async_delalloc_pages); | 1011 | if (atomic_sub_return(nr_pages, &root->fs_info->async_delalloc_pages) < |
| 1012 | |||
| 1013 | if (atomic_read(&root->fs_info->async_delalloc_pages) < | ||
| 1014 | 5 * 1024 * 1024 && | 1012 | 5 * 1024 * 1024 && |
| 1015 | waitqueue_active(&root->fs_info->async_submit_wait)) | 1013 | waitqueue_active(&root->fs_info->async_submit_wait)) |
| 1016 | wake_up(&root->fs_info->async_submit_wait); | 1014 | wake_up(&root->fs_info->async_submit_wait); |
| @@ -1885,8 +1883,11 @@ static int btrfs_finish_ordered_io(struct btrfs_ordered_extent *ordered_extent) | |||
| 1885 | trans = btrfs_join_transaction_nolock(root); | 1883 | trans = btrfs_join_transaction_nolock(root); |
| 1886 | else | 1884 | else |
| 1887 | trans = btrfs_join_transaction(root); | 1885 | trans = btrfs_join_transaction(root); |
| 1888 | if (IS_ERR(trans)) | 1886 | if (IS_ERR(trans)) { |
| 1889 | return PTR_ERR(trans); | 1887 | ret = PTR_ERR(trans); |
| 1888 | trans = NULL; | ||
| 1889 | goto out; | ||
| 1890 | } | ||
| 1890 | trans->block_rsv = &root->fs_info->delalloc_block_rsv; | 1891 | trans->block_rsv = &root->fs_info->delalloc_block_rsv; |
| 1891 | ret = btrfs_update_inode_fallback(trans, root, inode); | 1892 | ret = btrfs_update_inode_fallback(trans, root, inode); |
| 1892 | if (ret) /* -ENOMEM or corruption */ | 1893 | if (ret) /* -ENOMEM or corruption */ |
| @@ -3174,7 +3175,7 @@ int btrfs_unlink_subvol(struct btrfs_trans_handle *trans, | |||
| 3174 | btrfs_i_size_write(dir, dir->i_size - name_len * 2); | 3175 | btrfs_i_size_write(dir, dir->i_size - name_len * 2); |
| 3175 | inode_inc_iversion(dir); | 3176 | inode_inc_iversion(dir); |
| 3176 | dir->i_mtime = dir->i_ctime = CURRENT_TIME; | 3177 | dir->i_mtime = dir->i_ctime = CURRENT_TIME; |
| 3177 | ret = btrfs_update_inode(trans, root, dir); | 3178 | ret = btrfs_update_inode_fallback(trans, root, dir); |
| 3178 | if (ret) | 3179 | if (ret) |
| 3179 | btrfs_abort_transaction(trans, root, ret); | 3180 | btrfs_abort_transaction(trans, root, ret); |
| 3180 | out: | 3181 | out: |
| @@ -5774,18 +5775,112 @@ out: | |||
| 5774 | return ret; | 5775 | return ret; |
| 5775 | } | 5776 | } |
| 5776 | 5777 | ||
| 5778 | static int lock_extent_direct(struct inode *inode, u64 lockstart, u64 lockend, | ||
| 5779 | struct extent_state **cached_state, int writing) | ||
| 5780 | { | ||
| 5781 | struct btrfs_ordered_extent *ordered; | ||
| 5782 | int ret = 0; | ||
| 5783 | |||
| 5784 | while (1) { | ||
| 5785 | lock_extent_bits(&BTRFS_I(inode)->io_tree, lockstart, lockend, | ||
| 5786 | 0, cached_state); | ||
| 5787 | /* | ||
| 5788 | * We're concerned with the entire range that we're going to be | ||
| 5789 | * doing DIO to, so we need to make sure theres no ordered | ||
| 5790 | * extents in this range. | ||
| 5791 | */ | ||
| 5792 | ordered = btrfs_lookup_ordered_range(inode, lockstart, | ||
| 5793 | lockend - lockstart + 1); | ||
| 5794 | |||
| 5795 | /* | ||
| 5796 | * We need to make sure there are no buffered pages in this | ||
| 5797 | * range either, we could have raced between the invalidate in | ||
| 5798 | * generic_file_direct_write and locking the extent. The | ||
| 5799 | * invalidate needs to happen so that reads after a write do not | ||
| 5800 | * get stale data. | ||
| 5801 | */ | ||
| 5802 | if (!ordered && (!writing || | ||
| 5803 | !test_range_bit(&BTRFS_I(inode)->io_tree, | ||
| 5804 | lockstart, lockend, EXTENT_UPTODATE, 0, | ||
| 5805 | *cached_state))) | ||
| 5806 | break; | ||
| 5807 | |||
| 5808 | unlock_extent_cached(&BTRFS_I(inode)->io_tree, lockstart, lockend, | ||
| 5809 | cached_state, GFP_NOFS); | ||
| 5810 | |||
| 5811 | if (ordered) { | ||
| 5812 | btrfs_start_ordered_extent(inode, ordered, 1); | ||
| 5813 | btrfs_put_ordered_extent(ordered); | ||
| 5814 | } else { | ||
| 5815 | /* Screw you mmap */ | ||
| 5816 | ret = filemap_write_and_wait_range(inode->i_mapping, | ||
| 5817 | lockstart, | ||
| 5818 | lockend); | ||
| 5819 | if (ret) | ||
| 5820 | break; | ||
| 5821 | |||
| 5822 | /* | ||
| 5823 | * If we found a page that couldn't be invalidated just | ||
| 5824 | * fall back to buffered. | ||
| 5825 | */ | ||
| 5826 | ret = invalidate_inode_pages2_range(inode->i_mapping, | ||
| 5827 | lockstart >> PAGE_CACHE_SHIFT, | ||
| 5828 | lockend >> PAGE_CACHE_SHIFT); | ||
| 5829 | if (ret) | ||
| 5830 | break; | ||
| 5831 | } | ||
| 5832 | |||
| 5833 | cond_resched(); | ||
| 5834 | } | ||
| 5835 | |||
| 5836 | return ret; | ||
| 5837 | } | ||
| 5838 | |||
| 5777 | static int btrfs_get_blocks_direct(struct inode *inode, sector_t iblock, | 5839 | static int btrfs_get_blocks_direct(struct inode *inode, sector_t iblock, |
| 5778 | struct buffer_head *bh_result, int create) | 5840 | struct buffer_head *bh_result, int create) |
| 5779 | { | 5841 | { |
| 5780 | struct extent_map *em; | 5842 | struct extent_map *em; |
| 5781 | struct btrfs_root *root = BTRFS_I(inode)->root; | 5843 | struct btrfs_root *root = BTRFS_I(inode)->root; |
| 5844 | struct extent_state *cached_state = NULL; | ||
| 5782 | u64 start = iblock << inode->i_blkbits; | 5845 | u64 start = iblock << inode->i_blkbits; |
| 5846 | u64 lockstart, lockend; | ||
| 5783 | u64 len = bh_result->b_size; | 5847 | u64 len = bh_result->b_size; |
| 5784 | struct btrfs_trans_handle *trans; | 5848 | struct btrfs_trans_handle *trans; |
| 5849 | int unlock_bits = EXTENT_LOCKED; | ||
| 5850 | int ret; | ||
| 5851 | |||
| 5852 | if (create) { | ||
| 5853 | ret = btrfs_delalloc_reserve_space(inode, len); | ||
| 5854 | if (ret) | ||
| 5855 | return ret; | ||
| 5856 | unlock_bits |= EXTENT_DELALLOC | EXTENT_DIRTY; | ||
| 5857 | } else { | ||
| 5858 | len = min_t(u64, len, root->sectorsize); | ||
| 5859 | } | ||
| 5860 | |||
| 5861 | lockstart = start; | ||
| 5862 | lockend = start + len - 1; | ||
| 5863 | |||
| 5864 | /* | ||
| 5865 | * If this errors out it's because we couldn't invalidate pagecache for | ||
| 5866 | * this range and we need to fallback to buffered. | ||
| 5867 | */ | ||
| 5868 | if (lock_extent_direct(inode, lockstart, lockend, &cached_state, create)) | ||
| 5869 | return -ENOTBLK; | ||
| 5870 | |||
| 5871 | if (create) { | ||
| 5872 | ret = set_extent_bit(&BTRFS_I(inode)->io_tree, lockstart, | ||
| 5873 | lockend, EXTENT_DELALLOC, NULL, | ||
| 5874 | &cached_state, GFP_NOFS); | ||
| 5875 | if (ret) | ||
| 5876 | goto unlock_err; | ||
| 5877 | } | ||
| 5785 | 5878 | ||
| 5786 | em = btrfs_get_extent(inode, NULL, 0, start, len, 0); | 5879 | em = btrfs_get_extent(inode, NULL, 0, start, len, 0); |
| 5787 | if (IS_ERR(em)) | 5880 | if (IS_ERR(em)) { |
| 5788 | return PTR_ERR(em); | 5881 | ret = PTR_ERR(em); |
| 5882 | goto unlock_err; | ||
| 5883 | } | ||
| 5789 | 5884 | ||
| 5790 | /* | 5885 | /* |
| 5791 | * Ok for INLINE and COMPRESSED extents we need to fallback on buffered | 5886 | * Ok for INLINE and COMPRESSED extents we need to fallback on buffered |
| @@ -5804,17 +5899,16 @@ static int btrfs_get_blocks_direct(struct inode *inode, sector_t iblock, | |||
| 5804 | if (test_bit(EXTENT_FLAG_COMPRESSED, &em->flags) || | 5899 | if (test_bit(EXTENT_FLAG_COMPRESSED, &em->flags) || |
| 5805 | em->block_start == EXTENT_MAP_INLINE) { | 5900 | em->block_start == EXTENT_MAP_INLINE) { |
| 5806 | free_extent_map(em); | 5901 | free_extent_map(em); |
| 5807 | return -ENOTBLK; | 5902 | ret = -ENOTBLK; |
| 5903 | goto unlock_err; | ||
| 5808 | } | 5904 | } |
| 5809 | 5905 | ||
| 5810 | /* Just a good old fashioned hole, return */ | 5906 | /* Just a good old fashioned hole, return */ |
| 5811 | if (!create && (em->block_start == EXTENT_MAP_HOLE || | 5907 | if (!create && (em->block_start == EXTENT_MAP_HOLE || |
| 5812 | test_bit(EXTENT_FLAG_PREALLOC, &em->flags))) { | 5908 | test_bit(EXTENT_FLAG_PREALLOC, &em->flags))) { |
| 5813 | free_extent_map(em); | 5909 | free_extent_map(em); |
| 5814 | /* DIO will do one hole at a time, so just unlock a sector */ | 5910 | ret = 0; |
| 5815 | unlock_extent(&BTRFS_I(inode)->io_tree, start, | 5911 | goto unlock_err; |
| 5816 | start + root->sectorsize - 1); | ||
| 5817 | return 0; | ||
| 5818 | } | 5912 | } |
| 5819 | 5913 | ||
| 5820 | /* | 5914 | /* |
| @@ -5827,8 +5921,9 @@ static int btrfs_get_blocks_direct(struct inode *inode, sector_t iblock, | |||
| 5827 | * | 5921 | * |
| 5828 | */ | 5922 | */ |
| 5829 | if (!create) { | 5923 | if (!create) { |
| 5830 | len = em->len - (start - em->start); | 5924 | len = min(len, em->len - (start - em->start)); |
| 5831 | goto map; | 5925 | lockstart = start + len; |
| 5926 | goto unlock; | ||
| 5832 | } | 5927 | } |
| 5833 | 5928 | ||
| 5834 | if (test_bit(EXTENT_FLAG_PREALLOC, &em->flags) || | 5929 | if (test_bit(EXTENT_FLAG_PREALLOC, &em->flags) || |
| @@ -5860,7 +5955,7 @@ static int btrfs_get_blocks_direct(struct inode *inode, sector_t iblock, | |||
| 5860 | btrfs_end_transaction(trans, root); | 5955 | btrfs_end_transaction(trans, root); |
| 5861 | if (ret) { | 5956 | if (ret) { |
| 5862 | free_extent_map(em); | 5957 | free_extent_map(em); |
| 5863 | return ret; | 5958 | goto unlock_err; |
| 5864 | } | 5959 | } |
| 5865 | goto unlock; | 5960 | goto unlock; |
| 5866 | } | 5961 | } |
| @@ -5873,14 +5968,12 @@ must_cow: | |||
| 5873 | */ | 5968 | */ |
| 5874 | len = bh_result->b_size; | 5969 | len = bh_result->b_size; |
| 5875 | em = btrfs_new_extent_direct(inode, em, start, len); | 5970 | em = btrfs_new_extent_direct(inode, em, start, len); |
| 5876 | if (IS_ERR(em)) | 5971 | if (IS_ERR(em)) { |
| 5877 | return PTR_ERR(em); | 5972 | ret = PTR_ERR(em); |
| 5973 | goto unlock_err; | ||
| 5974 | } | ||
| 5878 | len = min(len, em->len - (start - em->start)); | 5975 | len = min(len, em->len - (start - em->start)); |
| 5879 | unlock: | 5976 | unlock: |
| 5880 | clear_extent_bit(&BTRFS_I(inode)->io_tree, start, start + len - 1, | ||
| 5881 | EXTENT_LOCKED | EXTENT_DELALLOC | EXTENT_DIRTY, 1, | ||
| 5882 | 0, NULL, GFP_NOFS); | ||
| 5883 | map: | ||
| 5884 | bh_result->b_blocknr = (em->block_start + (start - em->start)) >> | 5977 | bh_result->b_blocknr = (em->block_start + (start - em->start)) >> |
| 5885 | inode->i_blkbits; | 5978 | inode->i_blkbits; |
| 5886 | bh_result->b_size = len; | 5979 | bh_result->b_size = len; |
| @@ -5898,9 +5991,44 @@ map: | |||
| 5898 | i_size_write(inode, start + len); | 5991 | i_size_write(inode, start + len); |
| 5899 | } | 5992 | } |
| 5900 | 5993 | ||
| 5994 | /* | ||
| 5995 | * In the case of write we need to clear and unlock the entire range, | ||
| 5996 | * in the case of read we need to unlock only the end area that we | ||
| 5997 | * aren't using if there is any left over space. | ||
| 5998 | */ | ||
| 5999 | if (lockstart < lockend) { | ||
| 6000 | if (create && len < lockend - lockstart) { | ||
| 6001 | clear_extent_bit(&BTRFS_I(inode)->io_tree, lockstart, | ||
| 6002 | lockstart + len - 1, unlock_bits, 1, 0, | ||
| 6003 | &cached_state, GFP_NOFS); | ||
| 6004 | /* | ||
| 6005 | * Beside unlock, we also need to cleanup reserved space | ||
| 6006 | * for the left range by attaching EXTENT_DO_ACCOUNTING. | ||
| 6007 | */ | ||
| 6008 | clear_extent_bit(&BTRFS_I(inode)->io_tree, | ||
| 6009 | lockstart + len, lockend, | ||
| 6010 | unlock_bits | EXTENT_DO_ACCOUNTING, | ||
| 6011 | 1, 0, NULL, GFP_NOFS); | ||
| 6012 | } else { | ||
| 6013 | clear_extent_bit(&BTRFS_I(inode)->io_tree, lockstart, | ||
| 6014 | lockend, unlock_bits, 1, 0, | ||
| 6015 | &cached_state, GFP_NOFS); | ||
| 6016 | } | ||
| 6017 | } else { | ||
| 6018 | free_extent_state(cached_state); | ||
| 6019 | } | ||
| 6020 | |||
| 5901 | free_extent_map(em); | 6021 | free_extent_map(em); |
| 5902 | 6022 | ||
| 5903 | return 0; | 6023 | return 0; |
| 6024 | |||
| 6025 | unlock_err: | ||
| 6026 | if (create) | ||
| 6027 | unlock_bits |= EXTENT_DO_ACCOUNTING; | ||
| 6028 | |||
| 6029 | clear_extent_bit(&BTRFS_I(inode)->io_tree, lockstart, lockend, | ||
| 6030 | unlock_bits, 1, 0, &cached_state, GFP_NOFS); | ||
| 6031 | return ret; | ||
| 5904 | } | 6032 | } |
| 5905 | 6033 | ||
| 5906 | struct btrfs_dio_private { | 6034 | struct btrfs_dio_private { |
| @@ -5908,7 +6036,6 @@ struct btrfs_dio_private { | |||
| 5908 | u64 logical_offset; | 6036 | u64 logical_offset; |
| 5909 | u64 disk_bytenr; | 6037 | u64 disk_bytenr; |
| 5910 | u64 bytes; | 6038 | u64 bytes; |
| 5911 | u32 *csums; | ||
| 5912 | void *private; | 6039 | void *private; |
| 5913 | 6040 | ||
| 5914 | /* number of bios pending for this dio */ | 6041 | /* number of bios pending for this dio */ |
| @@ -5928,7 +6055,6 @@ static void btrfs_endio_direct_read(struct bio *bio, int err) | |||
| 5928 | struct inode *inode = dip->inode; | 6055 | struct inode *inode = dip->inode; |
| 5929 | struct btrfs_root *root = BTRFS_I(inode)->root; | 6056 | struct btrfs_root *root = BTRFS_I(inode)->root; |
| 5930 | u64 start; | 6057 | u64 start; |
| 5931 | u32 *private = dip->csums; | ||
| 5932 | 6058 | ||
| 5933 | start = dip->logical_offset; | 6059 | start = dip->logical_offset; |
| 5934 | do { | 6060 | do { |
| @@ -5936,8 +6062,12 @@ static void btrfs_endio_direct_read(struct bio *bio, int err) | |||
| 5936 | struct page *page = bvec->bv_page; | 6062 | struct page *page = bvec->bv_page; |
| 5937 | char *kaddr; | 6063 | char *kaddr; |
| 5938 | u32 csum = ~(u32)0; | 6064 | u32 csum = ~(u32)0; |
| 6065 | u64 private = ~(u32)0; | ||
| 5939 | unsigned long flags; | 6066 | unsigned long flags; |
| 5940 | 6067 | ||
| 6068 | if (get_state_private(&BTRFS_I(inode)->io_tree, | ||
| 6069 | start, &private)) | ||
| 6070 | goto failed; | ||
| 5941 | local_irq_save(flags); | 6071 | local_irq_save(flags); |
| 5942 | kaddr = kmap_atomic(page); | 6072 | kaddr = kmap_atomic(page); |
| 5943 | csum = btrfs_csum_data(root, kaddr + bvec->bv_offset, | 6073 | csum = btrfs_csum_data(root, kaddr + bvec->bv_offset, |
| @@ -5947,18 +6077,18 @@ static void btrfs_endio_direct_read(struct bio *bio, int err) | |||
| 5947 | local_irq_restore(flags); | 6077 | local_irq_restore(flags); |
| 5948 | 6078 | ||
| 5949 | flush_dcache_page(bvec->bv_page); | 6079 | flush_dcache_page(bvec->bv_page); |
| 5950 | if (csum != *private) { | 6080 | if (csum != private) { |
| 6081 | failed: | ||
| 5951 | printk(KERN_ERR "btrfs csum failed ino %llu off" | 6082 | printk(KERN_ERR "btrfs csum failed ino %llu off" |
| 5952 | " %llu csum %u private %u\n", | 6083 | " %llu csum %u private %u\n", |
| 5953 | (unsigned long long)btrfs_ino(inode), | 6084 | (unsigned long long)btrfs_ino(inode), |
| 5954 | (unsigned long long)start, | 6085 | (unsigned long long)start, |
| 5955 | csum, *private); | 6086 | csum, (unsigned)private); |
| 5956 | err = -EIO; | 6087 | err = -EIO; |
| 5957 | } | 6088 | } |
| 5958 | } | 6089 | } |
| 5959 | 6090 | ||
| 5960 | start += bvec->bv_len; | 6091 | start += bvec->bv_len; |
| 5961 | private++; | ||
| 5962 | bvec++; | 6092 | bvec++; |
| 5963 | } while (bvec <= bvec_end); | 6093 | } while (bvec <= bvec_end); |
| 5964 | 6094 | ||
| @@ -5966,7 +6096,6 @@ static void btrfs_endio_direct_read(struct bio *bio, int err) | |||
| 5966 | dip->logical_offset + dip->bytes - 1); | 6096 | dip->logical_offset + dip->bytes - 1); |
| 5967 | bio->bi_private = dip->private; | 6097 | bio->bi_private = dip->private; |
| 5968 | 6098 | ||
| 5969 | kfree(dip->csums); | ||
| 5970 | kfree(dip); | 6099 | kfree(dip); |
| 5971 | 6100 | ||
| 5972 | /* If we had a csum failure make sure to clear the uptodate flag */ | 6101 | /* If we had a csum failure make sure to clear the uptodate flag */ |
| @@ -6072,7 +6201,7 @@ static struct bio *btrfs_dio_bio_alloc(struct block_device *bdev, | |||
| 6072 | 6201 | ||
| 6073 | static inline int __btrfs_submit_dio_bio(struct bio *bio, struct inode *inode, | 6202 | static inline int __btrfs_submit_dio_bio(struct bio *bio, struct inode *inode, |
| 6074 | int rw, u64 file_offset, int skip_sum, | 6203 | int rw, u64 file_offset, int skip_sum, |
| 6075 | u32 *csums, int async_submit) | 6204 | int async_submit) |
| 6076 | { | 6205 | { |
| 6077 | int write = rw & REQ_WRITE; | 6206 | int write = rw & REQ_WRITE; |
| 6078 | struct btrfs_root *root = BTRFS_I(inode)->root; | 6207 | struct btrfs_root *root = BTRFS_I(inode)->root; |
| @@ -6105,8 +6234,7 @@ static inline int __btrfs_submit_dio_bio(struct bio *bio, struct inode *inode, | |||
| 6105 | if (ret) | 6234 | if (ret) |
| 6106 | goto err; | 6235 | goto err; |
| 6107 | } else if (!skip_sum) { | 6236 | } else if (!skip_sum) { |
| 6108 | ret = btrfs_lookup_bio_sums_dio(root, inode, bio, | 6237 | ret = btrfs_lookup_bio_sums_dio(root, inode, bio, file_offset); |
| 6109 | file_offset, csums); | ||
| 6110 | if (ret) | 6238 | if (ret) |
| 6111 | goto err; | 6239 | goto err; |
| 6112 | } | 6240 | } |
| @@ -6132,10 +6260,8 @@ static int btrfs_submit_direct_hook(int rw, struct btrfs_dio_private *dip, | |||
| 6132 | u64 submit_len = 0; | 6260 | u64 submit_len = 0; |
| 6133 | u64 map_length; | 6261 | u64 map_length; |
| 6134 | int nr_pages = 0; | 6262 | int nr_pages = 0; |
| 6135 | u32 *csums = dip->csums; | ||
| 6136 | int ret = 0; | 6263 | int ret = 0; |
| 6137 | int async_submit = 0; | 6264 | int async_submit = 0; |
| 6138 | int write = rw & REQ_WRITE; | ||
| 6139 | 6265 | ||
| 6140 | map_length = orig_bio->bi_size; | 6266 | map_length = orig_bio->bi_size; |
| 6141 | ret = btrfs_map_block(map_tree, READ, start_sector << 9, | 6267 | ret = btrfs_map_block(map_tree, READ, start_sector << 9, |
| @@ -6171,16 +6297,13 @@ static int btrfs_submit_direct_hook(int rw, struct btrfs_dio_private *dip, | |||
| 6171 | atomic_inc(&dip->pending_bios); | 6297 | atomic_inc(&dip->pending_bios); |
| 6172 | ret = __btrfs_submit_dio_bio(bio, inode, rw, | 6298 | ret = __btrfs_submit_dio_bio(bio, inode, rw, |
| 6173 | file_offset, skip_sum, | 6299 | file_offset, skip_sum, |
| 6174 | csums, async_submit); | 6300 | async_submit); |
| 6175 | if (ret) { | 6301 | if (ret) { |
| 6176 | bio_put(bio); | 6302 | bio_put(bio); |
| 6177 | atomic_dec(&dip->pending_bios); | 6303 | atomic_dec(&dip->pending_bios); |
| 6178 | goto out_err; | 6304 | goto out_err; |
| 6179 | } | 6305 | } |
| 6180 | 6306 | ||
| 6181 | /* Write's use the ordered csums */ | ||
| 6182 | if (!write && !skip_sum) | ||
| 6183 | csums = csums + nr_pages; | ||
| 6184 | start_sector += submit_len >> 9; | 6307 | start_sector += submit_len >> 9; |
| 6185 | file_offset += submit_len; | 6308 | file_offset += submit_len; |
| 6186 | 6309 | ||
| @@ -6210,7 +6333,7 @@ static int btrfs_submit_direct_hook(int rw, struct btrfs_dio_private *dip, | |||
| 6210 | 6333 | ||
| 6211 | submit: | 6334 | submit: |
| 6212 | ret = __btrfs_submit_dio_bio(bio, inode, rw, file_offset, skip_sum, | 6335 | ret = __btrfs_submit_dio_bio(bio, inode, rw, file_offset, skip_sum, |
| 6213 | csums, async_submit); | 6336 | async_submit); |
| 6214 | if (!ret) | 6337 | if (!ret) |
| 6215 | return 0; | 6338 | return 0; |
| 6216 | 6339 | ||
| @@ -6246,17 +6369,6 @@ static void btrfs_submit_direct(int rw, struct bio *bio, struct inode *inode, | |||
| 6246 | ret = -ENOMEM; | 6369 | ret = -ENOMEM; |
| 6247 | goto free_ordered; | 6370 | goto free_ordered; |
| 6248 | } | 6371 | } |
| 6249 | dip->csums = NULL; | ||
| 6250 | |||
| 6251 | /* Write's use the ordered csum stuff, so we don't need dip->csums */ | ||
| 6252 | if (!write && !skip_sum) { | ||
| 6253 | dip->csums = kmalloc(sizeof(u32) * bio->bi_vcnt, GFP_NOFS); | ||
| 6254 | if (!dip->csums) { | ||
| 6255 | kfree(dip); | ||
| 6256 | ret = -ENOMEM; | ||
| 6257 | goto free_ordered; | ||
| 6258 | } | ||
| 6259 | } | ||
| 6260 | 6372 | ||
| 6261 | dip->private = bio->bi_private; | 6373 | dip->private = bio->bi_private; |
| 6262 | dip->inode = inode; | 6374 | dip->inode = inode; |
| @@ -6341,132 +6453,22 @@ static ssize_t check_direct_IO(struct btrfs_root *root, int rw, struct kiocb *io | |||
| 6341 | out: | 6453 | out: |
| 6342 | return retval; | 6454 | return retval; |
| 6343 | } | 6455 | } |
| 6456 | |||
| 6344 | static ssize_t btrfs_direct_IO(int rw, struct kiocb *iocb, | 6457 | static ssize_t btrfs_direct_IO(int rw, struct kiocb *iocb, |
| 6345 | const struct iovec *iov, loff_t offset, | 6458 | const struct iovec *iov, loff_t offset, |
| 6346 | unsigned long nr_segs) | 6459 | unsigned long nr_segs) |
| 6347 | { | 6460 | { |
| 6348 | struct file *file = iocb->ki_filp; | 6461 | struct file *file = iocb->ki_filp; |
| 6349 | struct inode *inode = file->f_mapping->host; | 6462 | struct inode *inode = file->f_mapping->host; |
| 6350 | struct btrfs_ordered_extent *ordered; | ||
| 6351 | struct extent_state *cached_state = NULL; | ||
| 6352 | u64 lockstart, lockend; | ||
| 6353 | ssize_t ret; | ||
| 6354 | int writing = rw & WRITE; | ||
| 6355 | int write_bits = 0; | ||
| 6356 | size_t count = iov_length(iov, nr_segs); | ||
| 6357 | 6463 | ||
| 6358 | if (check_direct_IO(BTRFS_I(inode)->root, rw, iocb, iov, | 6464 | if (check_direct_IO(BTRFS_I(inode)->root, rw, iocb, iov, |
| 6359 | offset, nr_segs)) { | 6465 | offset, nr_segs)) |
| 6360 | return 0; | 6466 | return 0; |
| 6361 | } | ||
| 6362 | |||
| 6363 | lockstart = offset; | ||
| 6364 | lockend = offset + count - 1; | ||
| 6365 | |||
| 6366 | if (writing) { | ||
| 6367 | ret = btrfs_delalloc_reserve_space(inode, count); | ||
| 6368 | if (ret) | ||
| 6369 | goto out; | ||
| 6370 | } | ||
| 6371 | |||
| 6372 | while (1) { | ||
| 6373 | lock_extent_bits(&BTRFS_I(inode)->io_tree, lockstart, lockend, | ||
| 6374 | 0, &cached_state); | ||
| 6375 | /* | ||
| 6376 | * We're concerned with the entire range that we're going to be | ||
| 6377 | * doing DIO to, so we need to make sure theres no ordered | ||
| 6378 | * extents in this range. | ||
| 6379 | */ | ||
| 6380 | ordered = btrfs_lookup_ordered_range(inode, lockstart, | ||
| 6381 | lockend - lockstart + 1); | ||
| 6382 | |||
| 6383 | /* | ||
| 6384 | * We need to make sure there are no buffered pages in this | ||
| 6385 | * range either, we could have raced between the invalidate in | ||
| 6386 | * generic_file_direct_write and locking the extent. The | ||
| 6387 | * invalidate needs to happen so that reads after a write do not | ||
| 6388 | * get stale data. | ||
| 6389 | */ | ||
| 6390 | if (!ordered && (!writing || | ||
| 6391 | !test_range_bit(&BTRFS_I(inode)->io_tree, | ||
| 6392 | lockstart, lockend, EXTENT_UPTODATE, 0, | ||
| 6393 | cached_state))) | ||
| 6394 | break; | ||
| 6395 | |||
| 6396 | unlock_extent_cached(&BTRFS_I(inode)->io_tree, lockstart, lockend, | ||
| 6397 | &cached_state, GFP_NOFS); | ||
| 6398 | |||
| 6399 | if (ordered) { | ||
| 6400 | btrfs_start_ordered_extent(inode, ordered, 1); | ||
| 6401 | btrfs_put_ordered_extent(ordered); | ||
| 6402 | } else { | ||
| 6403 | /* Screw you mmap */ | ||
| 6404 | ret = filemap_write_and_wait_range(file->f_mapping, | ||
| 6405 | lockstart, | ||
| 6406 | lockend); | ||
| 6407 | if (ret) | ||
| 6408 | goto out; | ||
| 6409 | |||
| 6410 | /* | ||
| 6411 | * If we found a page that couldn't be invalidated just | ||
| 6412 | * fall back to buffered. | ||
| 6413 | */ | ||
| 6414 | ret = invalidate_inode_pages2_range(file->f_mapping, | ||
| 6415 | lockstart >> PAGE_CACHE_SHIFT, | ||
| 6416 | lockend >> PAGE_CACHE_SHIFT); | ||
| 6417 | if (ret) { | ||
| 6418 | if (ret == -EBUSY) | ||
| 6419 | ret = 0; | ||
| 6420 | goto out; | ||
| 6421 | } | ||
| 6422 | } | ||
| 6423 | |||
| 6424 | cond_resched(); | ||
| 6425 | } | ||
| 6426 | 6467 | ||
| 6427 | /* | 6468 | return __blockdev_direct_IO(rw, iocb, inode, |
| 6428 | * we don't use btrfs_set_extent_delalloc because we don't want | ||
| 6429 | * the dirty or uptodate bits | ||
| 6430 | */ | ||
| 6431 | if (writing) { | ||
| 6432 | write_bits = EXTENT_DELALLOC | EXTENT_DO_ACCOUNTING; | ||
| 6433 | ret = set_extent_bit(&BTRFS_I(inode)->io_tree, lockstart, lockend, | ||
| 6434 | EXTENT_DELALLOC, NULL, &cached_state, | ||
| 6435 | GFP_NOFS); | ||
| 6436 | if (ret) { | ||
| 6437 | clear_extent_bit(&BTRFS_I(inode)->io_tree, lockstart, | ||
| 6438 | lockend, EXTENT_LOCKED | write_bits, | ||
| 6439 | 1, 0, &cached_state, GFP_NOFS); | ||
| 6440 | goto out; | ||
| 6441 | } | ||
| 6442 | } | ||
| 6443 | |||
| 6444 | free_extent_state(cached_state); | ||
| 6445 | cached_state = NULL; | ||
| 6446 | |||
| 6447 | ret = __blockdev_direct_IO(rw, iocb, inode, | ||
| 6448 | BTRFS_I(inode)->root->fs_info->fs_devices->latest_bdev, | 6469 | BTRFS_I(inode)->root->fs_info->fs_devices->latest_bdev, |
| 6449 | iov, offset, nr_segs, btrfs_get_blocks_direct, NULL, | 6470 | iov, offset, nr_segs, btrfs_get_blocks_direct, NULL, |
| 6450 | btrfs_submit_direct, 0); | 6471 | btrfs_submit_direct, 0); |
| 6451 | |||
| 6452 | if (ret < 0 && ret != -EIOCBQUEUED) { | ||
| 6453 | clear_extent_bit(&BTRFS_I(inode)->io_tree, offset, | ||
| 6454 | offset + iov_length(iov, nr_segs) - 1, | ||
| 6455 | EXTENT_LOCKED | write_bits, 1, 0, | ||
| 6456 | &cached_state, GFP_NOFS); | ||
| 6457 | } else if (ret >= 0 && ret < iov_length(iov, nr_segs)) { | ||
| 6458 | /* | ||
| 6459 | * We're falling back to buffered, unlock the section we didn't | ||
| 6460 | * do IO on. | ||
| 6461 | */ | ||
| 6462 | clear_extent_bit(&BTRFS_I(inode)->io_tree, offset + ret, | ||
| 6463 | offset + iov_length(iov, nr_segs) - 1, | ||
| 6464 | EXTENT_LOCKED | write_bits, 1, 0, | ||
| 6465 | &cached_state, GFP_NOFS); | ||
| 6466 | } | ||
| 6467 | out: | ||
| 6468 | free_extent_state(cached_state); | ||
| 6469 | return ret; | ||
| 6470 | } | 6472 | } |
| 6471 | 6473 | ||
| 6472 | static int btrfs_fiemap(struct inode *inode, struct fiemap_extent_info *fieinfo, | 6474 | static int btrfs_fiemap(struct inode *inode, struct fiemap_extent_info *fieinfo, |
diff --git a/fs/btrfs/ioctl.c b/fs/btrfs/ioctl.c index 7bb755677a22..9df50fa8a078 100644 --- a/fs/btrfs/ioctl.c +++ b/fs/btrfs/ioctl.c | |||
| @@ -424,7 +424,7 @@ static noinline int create_subvol(struct btrfs_root *root, | |||
| 424 | uuid_le_gen(&new_uuid); | 424 | uuid_le_gen(&new_uuid); |
| 425 | memcpy(root_item.uuid, new_uuid.b, BTRFS_UUID_SIZE); | 425 | memcpy(root_item.uuid, new_uuid.b, BTRFS_UUID_SIZE); |
| 426 | root_item.otime.sec = cpu_to_le64(cur_time.tv_sec); | 426 | root_item.otime.sec = cpu_to_le64(cur_time.tv_sec); |
| 427 | root_item.otime.nsec = cpu_to_le64(cur_time.tv_nsec); | 427 | root_item.otime.nsec = cpu_to_le32(cur_time.tv_nsec); |
| 428 | root_item.ctime = root_item.otime; | 428 | root_item.ctime = root_item.otime; |
| 429 | btrfs_set_root_ctransid(&root_item, trans->transid); | 429 | btrfs_set_root_ctransid(&root_item, trans->transid); |
| 430 | btrfs_set_root_otransid(&root_item, trans->transid); | 430 | btrfs_set_root_otransid(&root_item, trans->transid); |
diff --git a/fs/btrfs/locking.c b/fs/btrfs/locking.c index a44eff074805..2a1762c66041 100644 --- a/fs/btrfs/locking.c +++ b/fs/btrfs/locking.c | |||
| @@ -67,7 +67,7 @@ void btrfs_clear_lock_blocking_rw(struct extent_buffer *eb, int rw) | |||
| 67 | { | 67 | { |
| 68 | if (eb->lock_nested) { | 68 | if (eb->lock_nested) { |
| 69 | read_lock(&eb->lock); | 69 | read_lock(&eb->lock); |
| 70 | if (&eb->lock_nested && current->pid == eb->lock_owner) { | 70 | if (eb->lock_nested && current->pid == eb->lock_owner) { |
| 71 | read_unlock(&eb->lock); | 71 | read_unlock(&eb->lock); |
| 72 | return; | 72 | return; |
| 73 | } | 73 | } |
diff --git a/fs/btrfs/qgroup.c b/fs/btrfs/qgroup.c index bc424ae5a81a..38b42e7bc91d 100644 --- a/fs/btrfs/qgroup.c +++ b/fs/btrfs/qgroup.c | |||
| @@ -1364,13 +1364,17 @@ int btrfs_qgroup_inherit(struct btrfs_trans_handle *trans, | |||
| 1364 | spin_lock(&fs_info->qgroup_lock); | 1364 | spin_lock(&fs_info->qgroup_lock); |
| 1365 | 1365 | ||
| 1366 | dstgroup = add_qgroup_rb(fs_info, objectid); | 1366 | dstgroup = add_qgroup_rb(fs_info, objectid); |
| 1367 | if (!dstgroup) | 1367 | if (IS_ERR(dstgroup)) { |
| 1368 | ret = PTR_ERR(dstgroup); | ||
| 1368 | goto unlock; | 1369 | goto unlock; |
| 1370 | } | ||
| 1369 | 1371 | ||
| 1370 | if (srcid) { | 1372 | if (srcid) { |
| 1371 | srcgroup = find_qgroup_rb(fs_info, srcid); | 1373 | srcgroup = find_qgroup_rb(fs_info, srcid); |
| 1372 | if (!srcgroup) | 1374 | if (!srcgroup) { |
| 1375 | ret = -EINVAL; | ||
| 1373 | goto unlock; | 1376 | goto unlock; |
| 1377 | } | ||
| 1374 | dstgroup->rfer = srcgroup->rfer - level_size; | 1378 | dstgroup->rfer = srcgroup->rfer - level_size; |
| 1375 | dstgroup->rfer_cmpr = srcgroup->rfer_cmpr - level_size; | 1379 | dstgroup->rfer_cmpr = srcgroup->rfer_cmpr - level_size; |
| 1376 | srcgroup->excl = level_size; | 1380 | srcgroup->excl = level_size; |
| @@ -1379,8 +1383,10 @@ int btrfs_qgroup_inherit(struct btrfs_trans_handle *trans, | |||
| 1379 | qgroup_dirty(fs_info, srcgroup); | 1383 | qgroup_dirty(fs_info, srcgroup); |
| 1380 | } | 1384 | } |
| 1381 | 1385 | ||
| 1382 | if (!inherit) | 1386 | if (!inherit) { |
| 1387 | ret = -EINVAL; | ||
| 1383 | goto unlock; | 1388 | goto unlock; |
| 1389 | } | ||
| 1384 | 1390 | ||
| 1385 | i_qgroups = (u64 *)(inherit + 1); | 1391 | i_qgroups = (u64 *)(inherit + 1); |
| 1386 | for (i = 0; i < inherit->num_qgroups; ++i) { | 1392 | for (i = 0; i < inherit->num_qgroups; ++i) { |
diff --git a/fs/btrfs/root-tree.c b/fs/btrfs/root-tree.c index 6bb465cca20f..10d8e4d88071 100644 --- a/fs/btrfs/root-tree.c +++ b/fs/btrfs/root-tree.c | |||
| @@ -544,8 +544,8 @@ void btrfs_update_root_times(struct btrfs_trans_handle *trans, | |||
| 544 | struct timespec ct = CURRENT_TIME; | 544 | struct timespec ct = CURRENT_TIME; |
| 545 | 545 | ||
| 546 | spin_lock(&root->root_times_lock); | 546 | spin_lock(&root->root_times_lock); |
| 547 | item->ctransid = trans->transid; | 547 | item->ctransid = cpu_to_le64(trans->transid); |
| 548 | item->ctime.sec = cpu_to_le64(ct.tv_sec); | 548 | item->ctime.sec = cpu_to_le64(ct.tv_sec); |
| 549 | item->ctime.nsec = cpu_to_le64(ct.tv_nsec); | 549 | item->ctime.nsec = cpu_to_le32(ct.tv_nsec); |
| 550 | spin_unlock(&root->root_times_lock); | 550 | spin_unlock(&root->root_times_lock); |
| 551 | } | 551 | } |
diff --git a/fs/btrfs/super.c b/fs/btrfs/super.c index f2eb24c477a3..83d6f9f9c220 100644 --- a/fs/btrfs/super.c +++ b/fs/btrfs/super.c | |||
| @@ -838,7 +838,6 @@ int btrfs_sync_fs(struct super_block *sb, int wait) | |||
| 838 | struct btrfs_trans_handle *trans; | 838 | struct btrfs_trans_handle *trans; |
| 839 | struct btrfs_fs_info *fs_info = btrfs_sb(sb); | 839 | struct btrfs_fs_info *fs_info = btrfs_sb(sb); |
| 840 | struct btrfs_root *root = fs_info->tree_root; | 840 | struct btrfs_root *root = fs_info->tree_root; |
| 841 | int ret; | ||
| 842 | 841 | ||
| 843 | trace_btrfs_sync_fs(wait); | 842 | trace_btrfs_sync_fs(wait); |
| 844 | 843 | ||
| @@ -849,11 +848,17 @@ int btrfs_sync_fs(struct super_block *sb, int wait) | |||
| 849 | 848 | ||
| 850 | btrfs_wait_ordered_extents(root, 0, 0); | 849 | btrfs_wait_ordered_extents(root, 0, 0); |
| 851 | 850 | ||
| 852 | trans = btrfs_start_transaction(root, 0); | 851 | spin_lock(&fs_info->trans_lock); |
| 852 | if (!fs_info->running_transaction) { | ||
| 853 | spin_unlock(&fs_info->trans_lock); | ||
| 854 | return 0; | ||
| 855 | } | ||
| 856 | spin_unlock(&fs_info->trans_lock); | ||
| 857 | |||
| 858 | trans = btrfs_join_transaction(root); | ||
| 853 | if (IS_ERR(trans)) | 859 | if (IS_ERR(trans)) |
| 854 | return PTR_ERR(trans); | 860 | return PTR_ERR(trans); |
| 855 | ret = btrfs_commit_transaction(trans, root); | 861 | return btrfs_commit_transaction(trans, root); |
| 856 | return ret; | ||
| 857 | } | 862 | } |
| 858 | 863 | ||
| 859 | static int btrfs_show_options(struct seq_file *seq, struct dentry *dentry) | 864 | static int btrfs_show_options(struct seq_file *seq, struct dentry *dentry) |
| @@ -1530,6 +1535,8 @@ static int btrfs_show_devname(struct seq_file *m, struct dentry *root) | |||
| 1530 | while (cur_devices) { | 1535 | while (cur_devices) { |
| 1531 | head = &cur_devices->devices; | 1536 | head = &cur_devices->devices; |
| 1532 | list_for_each_entry(dev, head, dev_list) { | 1537 | list_for_each_entry(dev, head, dev_list) { |
| 1538 | if (dev->missing) | ||
| 1539 | continue; | ||
| 1533 | if (!first_dev || dev->devid < first_dev->devid) | 1540 | if (!first_dev || dev->devid < first_dev->devid) |
| 1534 | first_dev = dev; | 1541 | first_dev = dev; |
| 1535 | } | 1542 | } |
diff --git a/fs/btrfs/transaction.c b/fs/btrfs/transaction.c index 17be3dedacba..27c26004e050 100644 --- a/fs/btrfs/transaction.c +++ b/fs/btrfs/transaction.c | |||
| @@ -1031,6 +1031,7 @@ static noinline int create_pending_snapshot(struct btrfs_trans_handle *trans, | |||
| 1031 | 1031 | ||
| 1032 | btrfs_i_size_write(parent_inode, parent_inode->i_size + | 1032 | btrfs_i_size_write(parent_inode, parent_inode->i_size + |
| 1033 | dentry->d_name.len * 2); | 1033 | dentry->d_name.len * 2); |
| 1034 | parent_inode->i_mtime = parent_inode->i_ctime = CURRENT_TIME; | ||
| 1034 | ret = btrfs_update_inode(trans, parent_root, parent_inode); | 1035 | ret = btrfs_update_inode(trans, parent_root, parent_inode); |
| 1035 | if (ret) | 1036 | if (ret) |
| 1036 | goto abort_trans_dput; | 1037 | goto abort_trans_dput; |
| @@ -1066,7 +1067,7 @@ static noinline int create_pending_snapshot(struct btrfs_trans_handle *trans, | |||
| 1066 | memcpy(new_root_item->parent_uuid, root->root_item.uuid, | 1067 | memcpy(new_root_item->parent_uuid, root->root_item.uuid, |
| 1067 | BTRFS_UUID_SIZE); | 1068 | BTRFS_UUID_SIZE); |
| 1068 | new_root_item->otime.sec = cpu_to_le64(cur_time.tv_sec); | 1069 | new_root_item->otime.sec = cpu_to_le64(cur_time.tv_sec); |
| 1069 | new_root_item->otime.nsec = cpu_to_le64(cur_time.tv_nsec); | 1070 | new_root_item->otime.nsec = cpu_to_le32(cur_time.tv_nsec); |
| 1070 | btrfs_set_root_otransid(new_root_item, trans->transid); | 1071 | btrfs_set_root_otransid(new_root_item, trans->transid); |
| 1071 | memset(&new_root_item->stime, 0, sizeof(new_root_item->stime)); | 1072 | memset(&new_root_item->stime, 0, sizeof(new_root_item->stime)); |
| 1072 | memset(&new_root_item->rtime, 0, sizeof(new_root_item->rtime)); | 1073 | memset(&new_root_item->rtime, 0, sizeof(new_root_item->rtime)); |
diff --git a/fs/btrfs/volumes.c b/fs/btrfs/volumes.c index e86ae04abe6a..88b969aeeb71 100644 --- a/fs/btrfs/volumes.c +++ b/fs/btrfs/volumes.c | |||
| @@ -227,9 +227,8 @@ loop_lock: | |||
| 227 | cur = pending; | 227 | cur = pending; |
| 228 | pending = pending->bi_next; | 228 | pending = pending->bi_next; |
| 229 | cur->bi_next = NULL; | 229 | cur->bi_next = NULL; |
| 230 | atomic_dec(&fs_info->nr_async_bios); | ||
| 231 | 230 | ||
| 232 | if (atomic_read(&fs_info->nr_async_bios) < limit && | 231 | if (atomic_dec_return(&fs_info->nr_async_bios) < limit && |
| 233 | waitqueue_active(&fs_info->async_submit_wait)) | 232 | waitqueue_active(&fs_info->async_submit_wait)) |
| 234 | wake_up(&fs_info->async_submit_wait); | 233 | wake_up(&fs_info->async_submit_wait); |
| 235 | 234 | ||
| @@ -569,9 +568,11 @@ static int __btrfs_close_devices(struct btrfs_fs_devices *fs_devices) | |||
| 569 | memcpy(new_device, device, sizeof(*new_device)); | 568 | memcpy(new_device, device, sizeof(*new_device)); |
| 570 | 569 | ||
| 571 | /* Safe because we are under uuid_mutex */ | 570 | /* Safe because we are under uuid_mutex */ |
| 572 | name = rcu_string_strdup(device->name->str, GFP_NOFS); | 571 | if (device->name) { |
| 573 | BUG_ON(device->name && !name); /* -ENOMEM */ | 572 | name = rcu_string_strdup(device->name->str, GFP_NOFS); |
| 574 | rcu_assign_pointer(new_device->name, name); | 573 | BUG_ON(device->name && !name); /* -ENOMEM */ |
| 574 | rcu_assign_pointer(new_device->name, name); | ||
| 575 | } | ||
| 575 | new_device->bdev = NULL; | 576 | new_device->bdev = NULL; |
| 576 | new_device->writeable = 0; | 577 | new_device->writeable = 0; |
| 577 | new_device->in_fs_metadata = 0; | 578 | new_device->in_fs_metadata = 0; |
| @@ -4605,28 +4606,6 @@ int btrfs_read_sys_array(struct btrfs_root *root) | |||
| 4605 | return ret; | 4606 | return ret; |
| 4606 | } | 4607 | } |
| 4607 | 4608 | ||
| 4608 | struct btrfs_device *btrfs_find_device_for_logical(struct btrfs_root *root, | ||
| 4609 | u64 logical, int mirror_num) | ||
| 4610 | { | ||
| 4611 | struct btrfs_mapping_tree *map_tree = &root->fs_info->mapping_tree; | ||
| 4612 | int ret; | ||
| 4613 | u64 map_length = 0; | ||
| 4614 | struct btrfs_bio *bbio = NULL; | ||
| 4615 | struct btrfs_device *device; | ||
| 4616 | |||
| 4617 | BUG_ON(mirror_num == 0); | ||
| 4618 | ret = btrfs_map_block(map_tree, WRITE, logical, &map_length, &bbio, | ||
| 4619 | mirror_num); | ||
| 4620 | if (ret) { | ||
| 4621 | BUG_ON(bbio != NULL); | ||
| 4622 | return NULL; | ||
| 4623 | } | ||
| 4624 | BUG_ON(mirror_num != bbio->mirror_num); | ||
| 4625 | device = bbio->stripes[mirror_num - 1].dev; | ||
| 4626 | kfree(bbio); | ||
| 4627 | return device; | ||
| 4628 | } | ||
| 4629 | |||
| 4630 | int btrfs_read_chunk_tree(struct btrfs_root *root) | 4609 | int btrfs_read_chunk_tree(struct btrfs_root *root) |
| 4631 | { | 4610 | { |
| 4632 | struct btrfs_path *path; | 4611 | struct btrfs_path *path; |
diff --git a/fs/btrfs/volumes.h b/fs/btrfs/volumes.h index 5479325987b3..53c06af92e8d 100644 --- a/fs/btrfs/volumes.h +++ b/fs/btrfs/volumes.h | |||
| @@ -289,8 +289,6 @@ int btrfs_cancel_balance(struct btrfs_fs_info *fs_info); | |||
| 289 | int btrfs_chunk_readonly(struct btrfs_root *root, u64 chunk_offset); | 289 | int btrfs_chunk_readonly(struct btrfs_root *root, u64 chunk_offset); |
| 290 | int find_free_dev_extent(struct btrfs_device *device, u64 num_bytes, | 290 | int find_free_dev_extent(struct btrfs_device *device, u64 num_bytes, |
| 291 | u64 *start, u64 *max_avail); | 291 | u64 *start, u64 *max_avail); |
| 292 | struct btrfs_device *btrfs_find_device_for_logical(struct btrfs_root *root, | ||
| 293 | u64 logical, int mirror_num); | ||
| 294 | void btrfs_dev_stat_print_on_error(struct btrfs_device *device); | 292 | void btrfs_dev_stat_print_on_error(struct btrfs_device *device); |
| 295 | void btrfs_dev_stat_inc_and_print(struct btrfs_device *dev, int index); | 293 | void btrfs_dev_stat_inc_and_print(struct btrfs_device *dev, int index); |
| 296 | int btrfs_get_dev_stats(struct btrfs_root *root, | 294 | int btrfs_get_dev_stats(struct btrfs_root *root, |
diff --git a/fs/buffer.c b/fs/buffer.c index 9f6d2e41281d..58e2e7b77372 100644 --- a/fs/buffer.c +++ b/fs/buffer.c | |||
| @@ -914,7 +914,7 @@ link_dev_buffers(struct page *page, struct buffer_head *head) | |||
| 914 | /* | 914 | /* |
| 915 | * Initialise the state of a blockdev page's buffers. | 915 | * Initialise the state of a blockdev page's buffers. |
| 916 | */ | 916 | */ |
| 917 | static void | 917 | static sector_t |
| 918 | init_page_buffers(struct page *page, struct block_device *bdev, | 918 | init_page_buffers(struct page *page, struct block_device *bdev, |
| 919 | sector_t block, int size) | 919 | sector_t block, int size) |
| 920 | { | 920 | { |
| @@ -936,33 +936,41 @@ init_page_buffers(struct page *page, struct block_device *bdev, | |||
| 936 | block++; | 936 | block++; |
| 937 | bh = bh->b_this_page; | 937 | bh = bh->b_this_page; |
| 938 | } while (bh != head); | 938 | } while (bh != head); |
| 939 | |||
| 940 | /* | ||
| 941 | * Caller needs to validate requested block against end of device. | ||
| 942 | */ | ||
| 943 | return end_block; | ||
| 939 | } | 944 | } |
| 940 | 945 | ||
| 941 | /* | 946 | /* |
| 942 | * Create the page-cache page that contains the requested block. | 947 | * Create the page-cache page that contains the requested block. |
| 943 | * | 948 | * |
| 944 | * This is user purely for blockdev mappings. | 949 | * This is used purely for blockdev mappings. |
| 945 | */ | 950 | */ |
| 946 | static struct page * | 951 | static int |
| 947 | grow_dev_page(struct block_device *bdev, sector_t block, | 952 | grow_dev_page(struct block_device *bdev, sector_t block, |
| 948 | pgoff_t index, int size) | 953 | pgoff_t index, int size, int sizebits) |
| 949 | { | 954 | { |
| 950 | struct inode *inode = bdev->bd_inode; | 955 | struct inode *inode = bdev->bd_inode; |
| 951 | struct page *page; | 956 | struct page *page; |
| 952 | struct buffer_head *bh; | 957 | struct buffer_head *bh; |
| 958 | sector_t end_block; | ||
| 959 | int ret = 0; /* Will call free_more_memory() */ | ||
| 953 | 960 | ||
| 954 | page = find_or_create_page(inode->i_mapping, index, | 961 | page = find_or_create_page(inode->i_mapping, index, |
| 955 | (mapping_gfp_mask(inode->i_mapping) & ~__GFP_FS)|__GFP_MOVABLE); | 962 | (mapping_gfp_mask(inode->i_mapping) & ~__GFP_FS)|__GFP_MOVABLE); |
| 956 | if (!page) | 963 | if (!page) |
| 957 | return NULL; | 964 | return ret; |
| 958 | 965 | ||
| 959 | BUG_ON(!PageLocked(page)); | 966 | BUG_ON(!PageLocked(page)); |
| 960 | 967 | ||
| 961 | if (page_has_buffers(page)) { | 968 | if (page_has_buffers(page)) { |
| 962 | bh = page_buffers(page); | 969 | bh = page_buffers(page); |
| 963 | if (bh->b_size == size) { | 970 | if (bh->b_size == size) { |
| 964 | init_page_buffers(page, bdev, block, size); | 971 | end_block = init_page_buffers(page, bdev, |
| 965 | return page; | 972 | index << sizebits, size); |
| 973 | goto done; | ||
| 966 | } | 974 | } |
| 967 | if (!try_to_free_buffers(page)) | 975 | if (!try_to_free_buffers(page)) |
| 968 | goto failed; | 976 | goto failed; |
| @@ -982,14 +990,14 @@ grow_dev_page(struct block_device *bdev, sector_t block, | |||
| 982 | */ | 990 | */ |
| 983 | spin_lock(&inode->i_mapping->private_lock); | 991 | spin_lock(&inode->i_mapping->private_lock); |
| 984 | link_dev_buffers(page, bh); | 992 | link_dev_buffers(page, bh); |
| 985 | init_page_buffers(page, bdev, block, size); | 993 | end_block = init_page_buffers(page, bdev, index << sizebits, size); |
| 986 | spin_unlock(&inode->i_mapping->private_lock); | 994 | spin_unlock(&inode->i_mapping->private_lock); |
| 987 | return page; | 995 | done: |
| 988 | 996 | ret = (block < end_block) ? 1 : -ENXIO; | |
| 989 | failed: | 997 | failed: |
| 990 | unlock_page(page); | 998 | unlock_page(page); |
| 991 | page_cache_release(page); | 999 | page_cache_release(page); |
| 992 | return NULL; | 1000 | return ret; |
| 993 | } | 1001 | } |
| 994 | 1002 | ||
| 995 | /* | 1003 | /* |
| @@ -999,7 +1007,6 @@ failed: | |||
| 999 | static int | 1007 | static int |
| 1000 | grow_buffers(struct block_device *bdev, sector_t block, int size) | 1008 | grow_buffers(struct block_device *bdev, sector_t block, int size) |
| 1001 | { | 1009 | { |
| 1002 | struct page *page; | ||
| 1003 | pgoff_t index; | 1010 | pgoff_t index; |
| 1004 | int sizebits; | 1011 | int sizebits; |
| 1005 | 1012 | ||
| @@ -1023,22 +1030,14 @@ grow_buffers(struct block_device *bdev, sector_t block, int size) | |||
| 1023 | bdevname(bdev, b)); | 1030 | bdevname(bdev, b)); |
| 1024 | return -EIO; | 1031 | return -EIO; |
| 1025 | } | 1032 | } |
| 1026 | block = index << sizebits; | 1033 | |
| 1027 | /* Create a page with the proper size buffers.. */ | 1034 | /* Create a page with the proper size buffers.. */ |
| 1028 | page = grow_dev_page(bdev, block, index, size); | 1035 | return grow_dev_page(bdev, block, index, size, sizebits); |
| 1029 | if (!page) | ||
| 1030 | return 0; | ||
| 1031 | unlock_page(page); | ||
| 1032 | page_cache_release(page); | ||
| 1033 | return 1; | ||
| 1034 | } | 1036 | } |
| 1035 | 1037 | ||
| 1036 | static struct buffer_head * | 1038 | static struct buffer_head * |
| 1037 | __getblk_slow(struct block_device *bdev, sector_t block, int size) | 1039 | __getblk_slow(struct block_device *bdev, sector_t block, int size) |
| 1038 | { | 1040 | { |
| 1039 | int ret; | ||
| 1040 | struct buffer_head *bh; | ||
| 1041 | |||
| 1042 | /* Size must be multiple of hard sectorsize */ | 1041 | /* Size must be multiple of hard sectorsize */ |
| 1043 | if (unlikely(size & (bdev_logical_block_size(bdev)-1) || | 1042 | if (unlikely(size & (bdev_logical_block_size(bdev)-1) || |
| 1044 | (size < 512 || size > PAGE_SIZE))) { | 1043 | (size < 512 || size > PAGE_SIZE))) { |
| @@ -1051,21 +1050,20 @@ __getblk_slow(struct block_device *bdev, sector_t block, int size) | |||
| 1051 | return NULL; | 1050 | return NULL; |
| 1052 | } | 1051 | } |
| 1053 | 1052 | ||
| 1054 | retry: | 1053 | for (;;) { |
| 1055 | bh = __find_get_block(bdev, block, size); | 1054 | struct buffer_head *bh; |
| 1056 | if (bh) | 1055 | int ret; |
| 1057 | return bh; | ||
| 1058 | 1056 | ||
| 1059 | ret = grow_buffers(bdev, block, size); | ||
| 1060 | if (ret == 0) { | ||
| 1061 | free_more_memory(); | ||
| 1062 | goto retry; | ||
| 1063 | } else if (ret > 0) { | ||
| 1064 | bh = __find_get_block(bdev, block, size); | 1057 | bh = __find_get_block(bdev, block, size); |
| 1065 | if (bh) | 1058 | if (bh) |
| 1066 | return bh; | 1059 | return bh; |
| 1060 | |||
| 1061 | ret = grow_buffers(bdev, block, size); | ||
| 1062 | if (ret < 0) | ||
| 1063 | return NULL; | ||
| 1064 | if (ret == 0) | ||
| 1065 | free_more_memory(); | ||
| 1067 | } | 1066 | } |
| 1068 | return NULL; | ||
| 1069 | } | 1067 | } |
| 1070 | 1068 | ||
| 1071 | /* | 1069 | /* |
| @@ -1321,10 +1319,6 @@ EXPORT_SYMBOL(__find_get_block); | |||
| 1321 | * which corresponds to the passed block_device, block and size. The | 1319 | * which corresponds to the passed block_device, block and size. The |
| 1322 | * returned buffer has its reference count incremented. | 1320 | * returned buffer has its reference count incremented. |
| 1323 | * | 1321 | * |
| 1324 | * __getblk() cannot fail - it just keeps trying. If you pass it an | ||
| 1325 | * illegal block number, __getblk() will happily return a buffer_head | ||
| 1326 | * which represents the non-existent block. Very weird. | ||
| 1327 | * | ||
| 1328 | * __getblk() will lock up the machine if grow_dev_page's try_to_free_buffers() | 1322 | * __getblk() will lock up the machine if grow_dev_page's try_to_free_buffers() |
| 1329 | * attempt is failing. FIXME, perhaps? | 1323 | * attempt is failing. FIXME, perhaps? |
| 1330 | */ | 1324 | */ |
diff --git a/fs/direct-io.c b/fs/direct-io.c index 1faf4cb56f39..f86c720dba0e 100644 --- a/fs/direct-io.c +++ b/fs/direct-io.c | |||
| @@ -1062,6 +1062,7 @@ do_blockdev_direct_IO(int rw, struct kiocb *iocb, struct inode *inode, | |||
| 1062 | unsigned long user_addr; | 1062 | unsigned long user_addr; |
| 1063 | size_t bytes; | 1063 | size_t bytes; |
| 1064 | struct buffer_head map_bh = { 0, }; | 1064 | struct buffer_head map_bh = { 0, }; |
| 1065 | struct blk_plug plug; | ||
| 1065 | 1066 | ||
| 1066 | if (rw & WRITE) | 1067 | if (rw & WRITE) |
| 1067 | rw = WRITE_ODIRECT; | 1068 | rw = WRITE_ODIRECT; |
| @@ -1177,6 +1178,8 @@ do_blockdev_direct_IO(int rw, struct kiocb *iocb, struct inode *inode, | |||
| 1177 | PAGE_SIZE - user_addr / PAGE_SIZE); | 1178 | PAGE_SIZE - user_addr / PAGE_SIZE); |
| 1178 | } | 1179 | } |
| 1179 | 1180 | ||
| 1181 | blk_start_plug(&plug); | ||
| 1182 | |||
| 1180 | for (seg = 0; seg < nr_segs; seg++) { | 1183 | for (seg = 0; seg < nr_segs; seg++) { |
| 1181 | user_addr = (unsigned long)iov[seg].iov_base; | 1184 | user_addr = (unsigned long)iov[seg].iov_base; |
| 1182 | sdio.size += bytes = iov[seg].iov_len; | 1185 | sdio.size += bytes = iov[seg].iov_len; |
| @@ -1235,6 +1238,8 @@ do_blockdev_direct_IO(int rw, struct kiocb *iocb, struct inode *inode, | |||
| 1235 | if (sdio.bio) | 1238 | if (sdio.bio) |
| 1236 | dio_bio_submit(dio, &sdio); | 1239 | dio_bio_submit(dio, &sdio); |
| 1237 | 1240 | ||
| 1241 | blk_finish_plug(&plug); | ||
| 1242 | |||
| 1238 | /* | 1243 | /* |
| 1239 | * It is possible that, we return short IO due to end of file. | 1244 | * It is possible that, we return short IO due to end of file. |
| 1240 | * In that case, we need to release all the pages we got hold on. | 1245 | * In that case, we need to release all the pages we got hold on. |
diff --git a/fs/jbd/journal.c b/fs/jbd/journal.c index 09357508ec9a..a2862339323b 100644 --- a/fs/jbd/journal.c +++ b/fs/jbd/journal.c | |||
| @@ -1113,6 +1113,11 @@ static void mark_journal_empty(journal_t *journal) | |||
| 1113 | 1113 | ||
| 1114 | BUG_ON(!mutex_is_locked(&journal->j_checkpoint_mutex)); | 1114 | BUG_ON(!mutex_is_locked(&journal->j_checkpoint_mutex)); |
| 1115 | spin_lock(&journal->j_state_lock); | 1115 | spin_lock(&journal->j_state_lock); |
| 1116 | /* Is it already empty? */ | ||
| 1117 | if (sb->s_start == 0) { | ||
| 1118 | spin_unlock(&journal->j_state_lock); | ||
| 1119 | return; | ||
| 1120 | } | ||
| 1116 | jbd_debug(1, "JBD: Marking journal as empty (seq %d)\n", | 1121 | jbd_debug(1, "JBD: Marking journal as empty (seq %d)\n", |
| 1117 | journal->j_tail_sequence); | 1122 | journal->j_tail_sequence); |
| 1118 | 1123 | ||
diff --git a/fs/logfs/dev_bdev.c b/fs/logfs/dev_bdev.c index df0de27c2733..e784a217b500 100644 --- a/fs/logfs/dev_bdev.c +++ b/fs/logfs/dev_bdev.c | |||
| @@ -26,6 +26,7 @@ static int sync_request(struct page *page, struct block_device *bdev, int rw) | |||
| 26 | struct completion complete; | 26 | struct completion complete; |
| 27 | 27 | ||
| 28 | bio_init(&bio); | 28 | bio_init(&bio); |
| 29 | bio.bi_max_vecs = 1; | ||
| 29 | bio.bi_io_vec = &bio_vec; | 30 | bio.bi_io_vec = &bio_vec; |
| 30 | bio_vec.bv_page = page; | 31 | bio_vec.bv_page = page; |
| 31 | bio_vec.bv_len = PAGE_SIZE; | 32 | bio_vec.bv_len = PAGE_SIZE; |
| @@ -95,12 +96,11 @@ static int __bdev_writeseg(struct super_block *sb, u64 ofs, pgoff_t index, | |||
| 95 | struct address_space *mapping = super->s_mapping_inode->i_mapping; | 96 | struct address_space *mapping = super->s_mapping_inode->i_mapping; |
| 96 | struct bio *bio; | 97 | struct bio *bio; |
| 97 | struct page *page; | 98 | struct page *page; |
| 98 | struct request_queue *q = bdev_get_queue(sb->s_bdev); | 99 | unsigned int max_pages; |
| 99 | unsigned int max_pages = queue_max_hw_sectors(q) >> (PAGE_SHIFT - 9); | ||
| 100 | int i; | 100 | int i; |
| 101 | 101 | ||
| 102 | if (max_pages > BIO_MAX_PAGES) | 102 | max_pages = min(nr_pages, (size_t) bio_get_nr_vecs(super->s_bdev)); |
| 103 | max_pages = BIO_MAX_PAGES; | 103 | |
| 104 | bio = bio_alloc(GFP_NOFS, max_pages); | 104 | bio = bio_alloc(GFP_NOFS, max_pages); |
| 105 | BUG_ON(!bio); | 105 | BUG_ON(!bio); |
| 106 | 106 | ||
| @@ -190,12 +190,11 @@ static int do_erase(struct super_block *sb, u64 ofs, pgoff_t index, | |||
| 190 | { | 190 | { |
| 191 | struct logfs_super *super = logfs_super(sb); | 191 | struct logfs_super *super = logfs_super(sb); |
| 192 | struct bio *bio; | 192 | struct bio *bio; |
| 193 | struct request_queue *q = bdev_get_queue(sb->s_bdev); | 193 | unsigned int max_pages; |
| 194 | unsigned int max_pages = queue_max_hw_sectors(q) >> (PAGE_SHIFT - 9); | ||
| 195 | int i; | 194 | int i; |
| 196 | 195 | ||
| 197 | if (max_pages > BIO_MAX_PAGES) | 196 | max_pages = min(nr_pages, (size_t) bio_get_nr_vecs(super->s_bdev)); |
| 198 | max_pages = BIO_MAX_PAGES; | 197 | |
| 199 | bio = bio_alloc(GFP_NOFS, max_pages); | 198 | bio = bio_alloc(GFP_NOFS, max_pages); |
| 200 | BUG_ON(!bio); | 199 | BUG_ON(!bio); |
| 201 | 200 | ||
diff --git a/fs/logfs/inode.c b/fs/logfs/inode.c index a422f42238b2..6984562738d3 100644 --- a/fs/logfs/inode.c +++ b/fs/logfs/inode.c | |||
| @@ -156,10 +156,26 @@ static void __logfs_destroy_inode(struct inode *inode) | |||
| 156 | call_rcu(&inode->i_rcu, logfs_i_callback); | 156 | call_rcu(&inode->i_rcu, logfs_i_callback); |
| 157 | } | 157 | } |
| 158 | 158 | ||
| 159 | static void __logfs_destroy_meta_inode(struct inode *inode) | ||
| 160 | { | ||
| 161 | struct logfs_inode *li = logfs_inode(inode); | ||
| 162 | BUG_ON(li->li_block); | ||
| 163 | call_rcu(&inode->i_rcu, logfs_i_callback); | ||
| 164 | } | ||
| 165 | |||
| 159 | static void logfs_destroy_inode(struct inode *inode) | 166 | static void logfs_destroy_inode(struct inode *inode) |
| 160 | { | 167 | { |
| 161 | struct logfs_inode *li = logfs_inode(inode); | 168 | struct logfs_inode *li = logfs_inode(inode); |
| 162 | 169 | ||
| 170 | if (inode->i_ino < LOGFS_RESERVED_INOS) { | ||
| 171 | /* | ||
| 172 | * The reserved inodes are never destroyed unless we are in | ||
| 173 | * unmont path. | ||
| 174 | */ | ||
| 175 | __logfs_destroy_meta_inode(inode); | ||
| 176 | return; | ||
| 177 | } | ||
| 178 | |||
| 163 | BUG_ON(list_empty(&li->li_freeing_list)); | 179 | BUG_ON(list_empty(&li->li_freeing_list)); |
| 164 | spin_lock(&logfs_inode_lock); | 180 | spin_lock(&logfs_inode_lock); |
| 165 | li->li_refcount--; | 181 | li->li_refcount--; |
| @@ -373,8 +389,8 @@ static void logfs_put_super(struct super_block *sb) | |||
| 373 | { | 389 | { |
| 374 | struct logfs_super *super = logfs_super(sb); | 390 | struct logfs_super *super = logfs_super(sb); |
| 375 | /* kill the meta-inodes */ | 391 | /* kill the meta-inodes */ |
| 376 | iput(super->s_master_inode); | ||
| 377 | iput(super->s_segfile_inode); | 392 | iput(super->s_segfile_inode); |
| 393 | iput(super->s_master_inode); | ||
| 378 | iput(super->s_mapping_inode); | 394 | iput(super->s_mapping_inode); |
| 379 | } | 395 | } |
| 380 | 396 | ||
diff --git a/fs/logfs/journal.c b/fs/logfs/journal.c index 1e1c369df22b..2a09b8d73989 100644 --- a/fs/logfs/journal.c +++ b/fs/logfs/journal.c | |||
| @@ -565,7 +565,7 @@ static void write_wbuf(struct super_block *sb, struct logfs_area *area, | |||
| 565 | index = ofs >> PAGE_SHIFT; | 565 | index = ofs >> PAGE_SHIFT; |
| 566 | page_ofs = ofs & (PAGE_SIZE - 1); | 566 | page_ofs = ofs & (PAGE_SIZE - 1); |
| 567 | 567 | ||
| 568 | page = find_lock_page(mapping, index); | 568 | page = find_or_create_page(mapping, index, GFP_NOFS); |
| 569 | BUG_ON(!page); | 569 | BUG_ON(!page); |
| 570 | memcpy(wbuf, page_address(page) + page_ofs, super->s_writesize); | 570 | memcpy(wbuf, page_address(page) + page_ofs, super->s_writesize); |
| 571 | unlock_page(page); | 571 | unlock_page(page); |
diff --git a/fs/logfs/readwrite.c b/fs/logfs/readwrite.c index f1cb512c5019..5be0abef603d 100644 --- a/fs/logfs/readwrite.c +++ b/fs/logfs/readwrite.c | |||
| @@ -2189,7 +2189,6 @@ void logfs_evict_inode(struct inode *inode) | |||
| 2189 | return; | 2189 | return; |
| 2190 | } | 2190 | } |
| 2191 | 2191 | ||
| 2192 | BUG_ON(inode->i_ino < LOGFS_RESERVED_INOS); | ||
| 2193 | page = inode_to_page(inode); | 2192 | page = inode_to_page(inode); |
| 2194 | BUG_ON(!page); /* FIXME: Use emergency page */ | 2193 | BUG_ON(!page); /* FIXME: Use emergency page */ |
| 2195 | logfs_put_write_page(page); | 2194 | logfs_put_write_page(page); |
diff --git a/fs/logfs/segment.c b/fs/logfs/segment.c index e28d090c98d6..038da0991794 100644 --- a/fs/logfs/segment.c +++ b/fs/logfs/segment.c | |||
| @@ -886,7 +886,7 @@ static struct logfs_area *alloc_area(struct super_block *sb) | |||
| 886 | 886 | ||
| 887 | static void map_invalidatepage(struct page *page, unsigned long l) | 887 | static void map_invalidatepage(struct page *page, unsigned long l) |
| 888 | { | 888 | { |
| 889 | BUG(); | 889 | return; |
| 890 | } | 890 | } |
| 891 | 891 | ||
| 892 | static int map_releasepage(struct page *page, gfp_t g) | 892 | static int map_releasepage(struct page *page, gfp_t g) |
diff --git a/fs/nfsd/nfs4callback.c b/fs/nfsd/nfs4callback.c index cbaf4f8bb7b7..4c7bd35b1876 100644 --- a/fs/nfsd/nfs4callback.c +++ b/fs/nfsd/nfs4callback.c | |||
| @@ -651,12 +651,12 @@ static int setup_callback_client(struct nfs4_client *clp, struct nfs4_cb_conn *c | |||
| 651 | 651 | ||
| 652 | if (clp->cl_minorversion == 0) { | 652 | if (clp->cl_minorversion == 0) { |
| 653 | if (!clp->cl_cred.cr_principal && | 653 | if (!clp->cl_cred.cr_principal && |
| 654 | (clp->cl_flavor >= RPC_AUTH_GSS_KRB5)) | 654 | (clp->cl_cred.cr_flavor >= RPC_AUTH_GSS_KRB5)) |
| 655 | return -EINVAL; | 655 | return -EINVAL; |
| 656 | args.client_name = clp->cl_cred.cr_principal; | 656 | args.client_name = clp->cl_cred.cr_principal; |
| 657 | args.prognumber = conn->cb_prog, | 657 | args.prognumber = conn->cb_prog, |
| 658 | args.protocol = XPRT_TRANSPORT_TCP; | 658 | args.protocol = XPRT_TRANSPORT_TCP; |
| 659 | args.authflavor = clp->cl_flavor; | 659 | args.authflavor = clp->cl_cred.cr_flavor; |
| 660 | clp->cl_cb_ident = conn->cb_ident; | 660 | clp->cl_cb_ident = conn->cb_ident; |
| 661 | } else { | 661 | } else { |
| 662 | if (!conn->cb_xprt) | 662 | if (!conn->cb_xprt) |
diff --git a/fs/nfsd/state.h b/fs/nfsd/state.h index e6173147f982..22bd0a66c356 100644 --- a/fs/nfsd/state.h +++ b/fs/nfsd/state.h | |||
| @@ -231,7 +231,6 @@ struct nfs4_client { | |||
| 231 | nfs4_verifier cl_verifier; /* generated by client */ | 231 | nfs4_verifier cl_verifier; /* generated by client */ |
| 232 | time_t cl_time; /* time of last lease renewal */ | 232 | time_t cl_time; /* time of last lease renewal */ |
| 233 | struct sockaddr_storage cl_addr; /* client ipaddress */ | 233 | struct sockaddr_storage cl_addr; /* client ipaddress */ |
| 234 | u32 cl_flavor; /* setclientid pseudoflavor */ | ||
| 235 | struct svc_cred cl_cred; /* setclientid principal */ | 234 | struct svc_cred cl_cred; /* setclientid principal */ |
| 236 | clientid_t cl_clientid; /* generated by server */ | 235 | clientid_t cl_clientid; /* generated by server */ |
| 237 | nfs4_verifier cl_confirm; /* generated by server */ | 236 | nfs4_verifier cl_confirm; /* generated by server */ |
diff --git a/fs/quota/dquot.c b/fs/quota/dquot.c index 36a29b753c79..c495a3055e2a 100644 --- a/fs/quota/dquot.c +++ b/fs/quota/dquot.c | |||
| @@ -1589,10 +1589,10 @@ int __dquot_alloc_space(struct inode *inode, qsize_t number, int flags) | |||
| 1589 | goto out; | 1589 | goto out; |
| 1590 | } | 1590 | } |
| 1591 | 1591 | ||
| 1592 | down_read(&sb_dqopt(inode->i_sb)->dqptr_sem); | ||
| 1593 | for (cnt = 0; cnt < MAXQUOTAS; cnt++) | 1592 | for (cnt = 0; cnt < MAXQUOTAS; cnt++) |
| 1594 | warn[cnt].w_type = QUOTA_NL_NOWARN; | 1593 | warn[cnt].w_type = QUOTA_NL_NOWARN; |
| 1595 | 1594 | ||
| 1595 | down_read(&sb_dqopt(inode->i_sb)->dqptr_sem); | ||
| 1596 | spin_lock(&dq_data_lock); | 1596 | spin_lock(&dq_data_lock); |
| 1597 | for (cnt = 0; cnt < MAXQUOTAS; cnt++) { | 1597 | for (cnt = 0; cnt < MAXQUOTAS; cnt++) { |
| 1598 | if (!dquots[cnt]) | 1598 | if (!dquots[cnt]) |
diff --git a/fs/reiserfs/bitmap.c b/fs/reiserfs/bitmap.c index 4c0c7d163d15..a98b7740a0fc 100644 --- a/fs/reiserfs/bitmap.c +++ b/fs/reiserfs/bitmap.c | |||
| @@ -1334,9 +1334,7 @@ struct buffer_head *reiserfs_read_bitmap_block(struct super_block *sb, | |||
| 1334 | else if (bitmap == 0) | 1334 | else if (bitmap == 0) |
| 1335 | block = (REISERFS_DISK_OFFSET_IN_BYTES >> sb->s_blocksize_bits) + 1; | 1335 | block = (REISERFS_DISK_OFFSET_IN_BYTES >> sb->s_blocksize_bits) + 1; |
| 1336 | 1336 | ||
| 1337 | reiserfs_write_unlock(sb); | ||
| 1338 | bh = sb_bread(sb, block); | 1337 | bh = sb_bread(sb, block); |
| 1339 | reiserfs_write_lock(sb); | ||
| 1340 | if (bh == NULL) | 1338 | if (bh == NULL) |
| 1341 | reiserfs_warning(sb, "sh-2029: %s: bitmap block (#%u) " | 1339 | reiserfs_warning(sb, "sh-2029: %s: bitmap block (#%u) " |
| 1342 | "reading failed", __func__, block); | 1340 | "reading failed", __func__, block); |
diff --git a/fs/reiserfs/inode.c b/fs/reiserfs/inode.c index a6d4268fb6c1..855da58db145 100644 --- a/fs/reiserfs/inode.c +++ b/fs/reiserfs/inode.c | |||
| @@ -76,10 +76,10 @@ void reiserfs_evict_inode(struct inode *inode) | |||
| 76 | ; | 76 | ; |
| 77 | } | 77 | } |
| 78 | out: | 78 | out: |
| 79 | reiserfs_write_unlock_once(inode->i_sb, depth); | ||
| 79 | clear_inode(inode); /* note this must go after the journal_end to prevent deadlock */ | 80 | clear_inode(inode); /* note this must go after the journal_end to prevent deadlock */ |
| 80 | dquot_drop(inode); | 81 | dquot_drop(inode); |
| 81 | inode->i_blocks = 0; | 82 | inode->i_blocks = 0; |
| 82 | reiserfs_write_unlock_once(inode->i_sb, depth); | ||
| 83 | return; | 83 | return; |
| 84 | 84 | ||
| 85 | no_delete: | 85 | no_delete: |
diff --git a/fs/ubifs/debug.h b/fs/ubifs/debug.h index 8b8cc4e945f4..760de723dadb 100644 --- a/fs/ubifs/debug.h +++ b/fs/ubifs/debug.h | |||
| @@ -167,7 +167,7 @@ struct ubifs_global_debug_info { | |||
| 167 | #define ubifs_dbg_msg(type, fmt, ...) \ | 167 | #define ubifs_dbg_msg(type, fmt, ...) \ |
| 168 | pr_debug("UBIFS DBG " type ": " fmt "\n", ##__VA_ARGS__) | 168 | pr_debug("UBIFS DBG " type ": " fmt "\n", ##__VA_ARGS__) |
| 169 | 169 | ||
| 170 | #define DBG_KEY_BUF_LEN 32 | 170 | #define DBG_KEY_BUF_LEN 48 |
| 171 | #define ubifs_dbg_msg_key(type, key, fmt, ...) do { \ | 171 | #define ubifs_dbg_msg_key(type, key, fmt, ...) do { \ |
| 172 | char __tmp_key_buf[DBG_KEY_BUF_LEN]; \ | 172 | char __tmp_key_buf[DBG_KEY_BUF_LEN]; \ |
| 173 | pr_debug("UBIFS DBG " type ": " fmt "%s\n", ##__VA_ARGS__, \ | 173 | pr_debug("UBIFS DBG " type ": " fmt "%s\n", ##__VA_ARGS__, \ |
diff --git a/fs/ubifs/lpt.c b/fs/ubifs/lpt.c index ce33b2beb151..8640920766ed 100644 --- a/fs/ubifs/lpt.c +++ b/fs/ubifs/lpt.c | |||
| @@ -1749,7 +1749,10 @@ int ubifs_lpt_init(struct ubifs_info *c, int rd, int wr) | |||
| 1749 | return 0; | 1749 | return 0; |
| 1750 | 1750 | ||
| 1751 | out_err: | 1751 | out_err: |
| 1752 | ubifs_lpt_free(c, 0); | 1752 | if (wr) |
| 1753 | ubifs_lpt_free(c, 1); | ||
| 1754 | if (rd) | ||
| 1755 | ubifs_lpt_free(c, 0); | ||
| 1753 | return err; | 1756 | return err; |
| 1754 | } | 1757 | } |
| 1755 | 1758 | ||
diff --git a/fs/ubifs/recovery.c b/fs/ubifs/recovery.c index c30d976b4be8..edeec499c048 100644 --- a/fs/ubifs/recovery.c +++ b/fs/ubifs/recovery.c | |||
| @@ -788,7 +788,7 @@ struct ubifs_scan_leb *ubifs_recover_leb(struct ubifs_info *c, int lnum, | |||
| 788 | 788 | ||
| 789 | corrupted_rescan: | 789 | corrupted_rescan: |
| 790 | /* Re-scan the corrupted data with verbose messages */ | 790 | /* Re-scan the corrupted data with verbose messages */ |
| 791 | ubifs_err("corruptio %d", ret); | 791 | ubifs_err("corruption %d", ret); |
| 792 | ubifs_scan_a_node(c, buf, len, lnum, offs, 1); | 792 | ubifs_scan_a_node(c, buf, len, lnum, offs, 1); |
| 793 | corrupted: | 793 | corrupted: |
| 794 | ubifs_scanned_corruption(c, lnum, offs, buf); | 794 | ubifs_scanned_corruption(c, lnum, offs, buf); |
diff --git a/fs/ubifs/replay.c b/fs/ubifs/replay.c index eba46d4a7619..94d78fc5d4e0 100644 --- a/fs/ubifs/replay.c +++ b/fs/ubifs/replay.c | |||
| @@ -1026,7 +1026,6 @@ int ubifs_replay_journal(struct ubifs_info *c) | |||
| 1026 | c->replaying = 1; | 1026 | c->replaying = 1; |
| 1027 | lnum = c->ltail_lnum = c->lhead_lnum; | 1027 | lnum = c->ltail_lnum = c->lhead_lnum; |
| 1028 | 1028 | ||
| 1029 | lnum = UBIFS_LOG_LNUM; | ||
| 1030 | do { | 1029 | do { |
| 1031 | err = replay_log_leb(c, lnum, 0, c->sbuf); | 1030 | err = replay_log_leb(c, lnum, 0, c->sbuf); |
| 1032 | if (err == 1) | 1031 | if (err == 1) |
| @@ -1035,7 +1034,7 @@ int ubifs_replay_journal(struct ubifs_info *c) | |||
| 1035 | if (err) | 1034 | if (err) |
| 1036 | goto out; | 1035 | goto out; |
| 1037 | lnum = ubifs_next_log_lnum(c, lnum); | 1036 | lnum = ubifs_next_log_lnum(c, lnum); |
| 1038 | } while (lnum != UBIFS_LOG_LNUM); | 1037 | } while (lnum != c->ltail_lnum); |
| 1039 | 1038 | ||
| 1040 | err = replay_buds(c); | 1039 | err = replay_buds(c); |
| 1041 | if (err) | 1040 | if (err) |
diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c index c3fa6c5327a3..71a197f0f93d 100644 --- a/fs/ubifs/super.c +++ b/fs/ubifs/super.c | |||
| @@ -1157,9 +1157,6 @@ static int check_free_space(struct ubifs_info *c) | |||
| 1157 | * | 1157 | * |
| 1158 | * This function mounts UBIFS file system. Returns zero in case of success and | 1158 | * This function mounts UBIFS file system. Returns zero in case of success and |
| 1159 | * a negative error code in case of failure. | 1159 | * a negative error code in case of failure. |
| 1160 | * | ||
| 1161 | * Note, the function does not de-allocate resources it it fails half way | ||
| 1162 | * through, and the caller has to do this instead. | ||
| 1163 | */ | 1160 | */ |
| 1164 | static int mount_ubifs(struct ubifs_info *c) | 1161 | static int mount_ubifs(struct ubifs_info *c) |
| 1165 | { | 1162 | { |
diff --git a/fs/udf/inode.c b/fs/udf/inode.c index fafaad795cd6..aa233469b3c1 100644 --- a/fs/udf/inode.c +++ b/fs/udf/inode.c | |||
| @@ -1124,14 +1124,17 @@ int udf_setsize(struct inode *inode, loff_t newsize) | |||
| 1124 | if (err) | 1124 | if (err) |
| 1125 | return err; | 1125 | return err; |
| 1126 | down_write(&iinfo->i_data_sem); | 1126 | down_write(&iinfo->i_data_sem); |
| 1127 | } else | 1127 | } else { |
| 1128 | iinfo->i_lenAlloc = newsize; | 1128 | iinfo->i_lenAlloc = newsize; |
| 1129 | goto set_size; | ||
| 1130 | } | ||
| 1129 | } | 1131 | } |
| 1130 | err = udf_extend_file(inode, newsize); | 1132 | err = udf_extend_file(inode, newsize); |
| 1131 | if (err) { | 1133 | if (err) { |
| 1132 | up_write(&iinfo->i_data_sem); | 1134 | up_write(&iinfo->i_data_sem); |
| 1133 | return err; | 1135 | return err; |
| 1134 | } | 1136 | } |
| 1137 | set_size: | ||
| 1135 | truncate_setsize(inode, newsize); | 1138 | truncate_setsize(inode, newsize); |
| 1136 | up_write(&iinfo->i_data_sem); | 1139 | up_write(&iinfo->i_data_sem); |
| 1137 | } else { | 1140 | } else { |
diff --git a/fs/udf/super.c b/fs/udf/super.c index dcbf98722afc..18fc038a438d 100644 --- a/fs/udf/super.c +++ b/fs/udf/super.c | |||
| @@ -1344,6 +1344,7 @@ static int udf_load_logicalvol(struct super_block *sb, sector_t block, | |||
| 1344 | udf_err(sb, "error loading logical volume descriptor: " | 1344 | udf_err(sb, "error loading logical volume descriptor: " |
| 1345 | "Partition table too long (%u > %lu)\n", table_len, | 1345 | "Partition table too long (%u > %lu)\n", table_len, |
| 1346 | sb->s_blocksize - sizeof(*lvd)); | 1346 | sb->s_blocksize - sizeof(*lvd)); |
| 1347 | ret = 1; | ||
| 1347 | goto out_bh; | 1348 | goto out_bh; |
| 1348 | } | 1349 | } |
| 1349 | 1350 | ||
| @@ -1388,8 +1389,10 @@ static int udf_load_logicalvol(struct super_block *sb, sector_t block, | |||
| 1388 | UDF_ID_SPARABLE, | 1389 | UDF_ID_SPARABLE, |
| 1389 | strlen(UDF_ID_SPARABLE))) { | 1390 | strlen(UDF_ID_SPARABLE))) { |
| 1390 | if (udf_load_sparable_map(sb, map, | 1391 | if (udf_load_sparable_map(sb, map, |
| 1391 | (struct sparablePartitionMap *)gpm) < 0) | 1392 | (struct sparablePartitionMap *)gpm) < 0) { |
| 1393 | ret = 1; | ||
| 1392 | goto out_bh; | 1394 | goto out_bh; |
| 1395 | } | ||
| 1393 | } else if (!strncmp(upm2->partIdent.ident, | 1396 | } else if (!strncmp(upm2->partIdent.ident, |
| 1394 | UDF_ID_METADATA, | 1397 | UDF_ID_METADATA, |
| 1395 | strlen(UDF_ID_METADATA))) { | 1398 | strlen(UDF_ID_METADATA))) { |
| @@ -2000,6 +2003,8 @@ static int udf_fill_super(struct super_block *sb, void *options, int silent) | |||
| 2000 | if (!silent) | 2003 | if (!silent) |
| 2001 | pr_notice("Rescanning with blocksize %d\n", | 2004 | pr_notice("Rescanning with blocksize %d\n", |
| 2002 | UDF_DEFAULT_BLOCKSIZE); | 2005 | UDF_DEFAULT_BLOCKSIZE); |
| 2006 | brelse(sbi->s_lvid_bh); | ||
| 2007 | sbi->s_lvid_bh = NULL; | ||
| 2003 | uopt.blocksize = UDF_DEFAULT_BLOCKSIZE; | 2008 | uopt.blocksize = UDF_DEFAULT_BLOCKSIZE; |
| 2004 | ret = udf_load_vrs(sb, &uopt, silent, &fileset); | 2009 | ret = udf_load_vrs(sb, &uopt, silent, &fileset); |
| 2005 | } | 2010 | } |
diff --git a/fs/xfs/xfs_discard.c b/fs/xfs/xfs_discard.c index f9c3fe304a17..69cf4fcde03e 100644 --- a/fs/xfs/xfs_discard.c +++ b/fs/xfs/xfs_discard.c | |||
| @@ -179,12 +179,14 @@ xfs_ioc_trim( | |||
| 179 | * used by the fstrim application. In the end it really doesn't | 179 | * used by the fstrim application. In the end it really doesn't |
| 180 | * matter as trimming blocks is an advisory interface. | 180 | * matter as trimming blocks is an advisory interface. |
| 181 | */ | 181 | */ |
| 182 | if (range.start >= XFS_FSB_TO_B(mp, mp->m_sb.sb_dblocks) || | ||
| 183 | range.minlen > XFS_FSB_TO_B(mp, XFS_ALLOC_AG_MAX_USABLE(mp))) | ||
| 184 | return -XFS_ERROR(EINVAL); | ||
| 185 | |||
| 182 | start = BTOBB(range.start); | 186 | start = BTOBB(range.start); |
| 183 | end = start + BTOBBT(range.len) - 1; | 187 | end = start + BTOBBT(range.len) - 1; |
| 184 | minlen = BTOBB(max_t(u64, granularity, range.minlen)); | 188 | minlen = BTOBB(max_t(u64, granularity, range.minlen)); |
| 185 | 189 | ||
| 186 | if (XFS_BB_TO_FSB(mp, start) >= mp->m_sb.sb_dblocks) | ||
| 187 | return -XFS_ERROR(EINVAL); | ||
| 188 | if (end > XFS_FSB_TO_BB(mp, mp->m_sb.sb_dblocks) - 1) | 190 | if (end > XFS_FSB_TO_BB(mp, mp->m_sb.sb_dblocks) - 1) |
| 189 | end = XFS_FSB_TO_BB(mp, mp->m_sb.sb_dblocks)- 1; | 191 | end = XFS_FSB_TO_BB(mp, mp->m_sb.sb_dblocks)- 1; |
| 190 | 192 | ||
diff --git a/fs/xfs/xfs_ialloc.c b/fs/xfs/xfs_ialloc.c index 21e37b55f7e5..5aceb3f8ecd6 100644 --- a/fs/xfs/xfs_ialloc.c +++ b/fs/xfs/xfs_ialloc.c | |||
| @@ -962,23 +962,22 @@ xfs_dialloc( | |||
| 962 | if (!pag->pagi_freecount && !okalloc) | 962 | if (!pag->pagi_freecount && !okalloc) |
| 963 | goto nextag; | 963 | goto nextag; |
| 964 | 964 | ||
| 965 | /* | ||
| 966 | * Then read in the AGI buffer and recheck with the AGI buffer | ||
| 967 | * lock held. | ||
| 968 | */ | ||
| 965 | error = xfs_ialloc_read_agi(mp, tp, agno, &agbp); | 969 | error = xfs_ialloc_read_agi(mp, tp, agno, &agbp); |
| 966 | if (error) | 970 | if (error) |
| 967 | goto out_error; | 971 | goto out_error; |
| 968 | 972 | ||
| 969 | /* | ||
| 970 | * Once the AGI has been read in we have to recheck | ||
| 971 | * pagi_freecount with the AGI buffer lock held. | ||
| 972 | */ | ||
| 973 | if (pag->pagi_freecount) { | 973 | if (pag->pagi_freecount) { |
| 974 | xfs_perag_put(pag); | 974 | xfs_perag_put(pag); |
| 975 | goto out_alloc; | 975 | goto out_alloc; |
| 976 | } | 976 | } |
| 977 | 977 | ||
| 978 | if (!okalloc) { | 978 | if (!okalloc) |
| 979 | xfs_trans_brelse(tp, agbp); | 979 | goto nextag_relse_buffer; |
| 980 | goto nextag; | 980 | |
| 981 | } | ||
| 982 | 981 | ||
| 983 | error = xfs_ialloc_ag_alloc(tp, agbp, &ialloced); | 982 | error = xfs_ialloc_ag_alloc(tp, agbp, &ialloced); |
| 984 | if (error) { | 983 | if (error) { |
| @@ -1007,6 +1006,8 @@ xfs_dialloc( | |||
| 1007 | return 0; | 1006 | return 0; |
| 1008 | } | 1007 | } |
| 1009 | 1008 | ||
| 1009 | nextag_relse_buffer: | ||
| 1010 | xfs_trans_brelse(tp, agbp); | ||
| 1010 | nextag: | 1011 | nextag: |
| 1011 | xfs_perag_put(pag); | 1012 | xfs_perag_put(pag); |
| 1012 | if (++agno == mp->m_sb.sb_agcount) | 1013 | if (++agno == mp->m_sb.sb_agcount) |
diff --git a/fs/xfs/xfs_rtalloc.c b/fs/xfs/xfs_rtalloc.c index 92d4331cd4f1..ca28a4ba4b54 100644 --- a/fs/xfs/xfs_rtalloc.c +++ b/fs/xfs/xfs_rtalloc.c | |||
| @@ -857,7 +857,7 @@ xfs_rtbuf_get( | |||
| 857 | xfs_buf_t *bp; /* block buffer, result */ | 857 | xfs_buf_t *bp; /* block buffer, result */ |
| 858 | xfs_inode_t *ip; /* bitmap or summary inode */ | 858 | xfs_inode_t *ip; /* bitmap or summary inode */ |
| 859 | xfs_bmbt_irec_t map; | 859 | xfs_bmbt_irec_t map; |
| 860 | int nmap; | 860 | int nmap = 1; |
| 861 | int error; /* error value */ | 861 | int error; /* error value */ |
| 862 | 862 | ||
| 863 | ip = issum ? mp->m_rsumip : mp->m_rbmip; | 863 | ip = issum ? mp->m_rsumip : mp->m_rbmip; |
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index ced362533e3c..bfacf0d5a225 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h | |||
| @@ -118,7 +118,8 @@ enum drm_mode_status { | |||
| 118 | .hdisplay = (hd), .hsync_start = (hss), .hsync_end = (hse), \ | 118 | .hdisplay = (hd), .hsync_start = (hss), .hsync_end = (hse), \ |
| 119 | .htotal = (ht), .hskew = (hsk), .vdisplay = (vd), \ | 119 | .htotal = (ht), .hskew = (hsk), .vdisplay = (vd), \ |
| 120 | .vsync_start = (vss), .vsync_end = (vse), .vtotal = (vt), \ | 120 | .vsync_start = (vss), .vsync_end = (vse), .vtotal = (vt), \ |
| 121 | .vscan = (vs), .flags = (f), .vrefresh = 0 | 121 | .vscan = (vs), .flags = (f), .vrefresh = 0, \ |
| 122 | .base.type = DRM_MODE_OBJECT_MODE | ||
| 122 | 123 | ||
| 123 | #define CRTC_INTERLACE_HALVE_V 0x1 /* halve V values for interlacing */ | 124 | #define CRTC_INTERLACE_HALVE_V 0x1 /* halve V values for interlacing */ |
| 124 | 125 | ||
diff --git a/include/drm/drm_mode.h b/include/drm/drm_mode.h index 5581980b14f6..3d6301b6ec16 100644 --- a/include/drm/drm_mode.h +++ b/include/drm/drm_mode.h | |||
| @@ -359,8 +359,9 @@ struct drm_mode_mode_cmd { | |||
| 359 | struct drm_mode_modeinfo mode; | 359 | struct drm_mode_modeinfo mode; |
| 360 | }; | 360 | }; |
| 361 | 361 | ||
| 362 | #define DRM_MODE_CURSOR_BO (1<<0) | 362 | #define DRM_MODE_CURSOR_BO 0x01 |
| 363 | #define DRM_MODE_CURSOR_MOVE (1<<1) | 363 | #define DRM_MODE_CURSOR_MOVE 0x02 |
| 364 | #define DRM_MODE_CURSOR_FLAGS 0x03 | ||
| 364 | 365 | ||
| 365 | /* | 366 | /* |
| 366 | * depending on the value in flags different members are used. | 367 | * depending on the value in flags different members are used. |
diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h index 4e72a9d48232..4a2ab7c85393 100644 --- a/include/linux/blkdev.h +++ b/include/linux/blkdev.h | |||
| @@ -601,7 +601,7 @@ static inline void blk_clear_rl_full(struct request_list *rl, bool sync) | |||
| 601 | * it already be started by driver. | 601 | * it already be started by driver. |
| 602 | */ | 602 | */ |
| 603 | #define RQ_NOMERGE_FLAGS \ | 603 | #define RQ_NOMERGE_FLAGS \ |
| 604 | (REQ_NOMERGE | REQ_STARTED | REQ_SOFTBARRIER | REQ_FLUSH | REQ_FUA) | 604 | (REQ_NOMERGE | REQ_STARTED | REQ_SOFTBARRIER | REQ_FLUSH | REQ_FUA | REQ_DISCARD) |
| 605 | #define rq_mergeable(rq) \ | 605 | #define rq_mergeable(rq) \ |
| 606 | (!((rq)->cmd_flags & RQ_NOMERGE_FLAGS) && \ | 606 | (!((rq)->cmd_flags & RQ_NOMERGE_FLAGS) && \ |
| 607 | (((rq)->cmd_flags & REQ_DISCARD) || \ | 607 | (((rq)->cmd_flags & REQ_DISCARD) || \ |
| @@ -894,6 +894,8 @@ extern void blk_queue_flush_queueable(struct request_queue *q, bool queueable); | |||
| 894 | extern struct backing_dev_info *blk_get_backing_dev_info(struct block_device *bdev); | 894 | extern struct backing_dev_info *blk_get_backing_dev_info(struct block_device *bdev); |
| 895 | 895 | ||
| 896 | extern int blk_rq_map_sg(struct request_queue *, struct request *, struct scatterlist *); | 896 | extern int blk_rq_map_sg(struct request_queue *, struct request *, struct scatterlist *); |
| 897 | extern int blk_bio_map_sg(struct request_queue *q, struct bio *bio, | ||
| 898 | struct scatterlist *sglist); | ||
| 897 | extern void blk_dump_rq_flags(struct request *, char *); | 899 | extern void blk_dump_rq_flags(struct request *, char *); |
| 898 | extern long nr_blockdev_pages(void); | 900 | extern long nr_blockdev_pages(void); |
| 899 | 901 | ||
| @@ -1139,6 +1141,16 @@ static inline int queue_limit_discard_alignment(struct queue_limits *lim, sector | |||
| 1139 | & (lim->discard_granularity - 1); | 1141 | & (lim->discard_granularity - 1); |
| 1140 | } | 1142 | } |
| 1141 | 1143 | ||
| 1144 | static inline int bdev_discard_alignment(struct block_device *bdev) | ||
| 1145 | { | ||
| 1146 | struct request_queue *q = bdev_get_queue(bdev); | ||
| 1147 | |||
| 1148 | if (bdev != bdev->bd_contains) | ||
| 1149 | return bdev->bd_part->discard_alignment; | ||
| 1150 | |||
| 1151 | return q->limits.discard_alignment; | ||
| 1152 | } | ||
| 1153 | |||
| 1142 | static inline unsigned int queue_discard_zeroes_data(struct request_queue *q) | 1154 | static inline unsigned int queue_discard_zeroes_data(struct request_queue *q) |
| 1143 | { | 1155 | { |
| 1144 | if (q->limits.max_discard_sectors && q->limits.discard_zeroes_data == 1) | 1156 | if (q->limits.max_discard_sectors && q->limits.discard_zeroes_data == 1) |
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 77335fac943e..c12731582920 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h | |||
| @@ -26,6 +26,7 @@ | |||
| 26 | #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ | 26 | #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ |
| 27 | #define CLK_IS_ROOT BIT(4) /* root clk, has no parent */ | 27 | #define CLK_IS_ROOT BIT(4) /* root clk, has no parent */ |
| 28 | #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ | 28 | #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ |
| 29 | #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ | ||
| 29 | 30 | ||
| 30 | struct clk_hw; | 31 | struct clk_hw; |
| 31 | 32 | ||
| @@ -360,6 +361,11 @@ int of_clk_add_provider(struct device_node *np, | |||
| 360 | void of_clk_del_provider(struct device_node *np); | 361 | void of_clk_del_provider(struct device_node *np); |
| 361 | struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, | 362 | struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, |
| 362 | void *data); | 363 | void *data); |
| 364 | struct clk_onecell_data { | ||
| 365 | struct clk **clks; | ||
| 366 | unsigned int clk_num; | ||
| 367 | }; | ||
| 368 | struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); | ||
| 363 | const char *of_clk_get_parent_name(struct device_node *np, int index); | 369 | const char *of_clk_get_parent_name(struct device_node *np, int index); |
| 364 | void of_clk_init(const struct of_device_id *matches); | 370 | void of_clk_init(const struct of_device_id *matches); |
| 365 | 371 | ||
diff --git a/include/linux/cpuidle.h b/include/linux/cpuidle.h index 040b13b5c14a..279b1eaa8b73 100644 --- a/include/linux/cpuidle.h +++ b/include/linux/cpuidle.h | |||
| @@ -194,6 +194,10 @@ static inline int cpuidle_play_dead(void) {return -ENODEV; } | |||
| 194 | 194 | ||
| 195 | #ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED | 195 | #ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED |
| 196 | void cpuidle_coupled_parallel_barrier(struct cpuidle_device *dev, atomic_t *a); | 196 | void cpuidle_coupled_parallel_barrier(struct cpuidle_device *dev, atomic_t *a); |
| 197 | #else | ||
| 198 | static inline void cpuidle_coupled_parallel_barrier(struct cpuidle_device *dev, atomic_t *a) | ||
| 199 | { | ||
| 200 | } | ||
| 197 | #endif | 201 | #endif |
| 198 | 202 | ||
| 199 | /****************************** | 203 | /****************************** |
diff --git a/include/linux/ktime.h b/include/linux/ktime.h index 603bec2913b0..06177ba10a16 100644 --- a/include/linux/ktime.h +++ b/include/linux/ktime.h | |||
| @@ -58,13 +58,6 @@ union ktime { | |||
| 58 | 58 | ||
| 59 | typedef union ktime ktime_t; /* Kill this */ | 59 | typedef union ktime ktime_t; /* Kill this */ |
| 60 | 60 | ||
| 61 | #define KTIME_MAX ((s64)~((u64)1 << 63)) | ||
| 62 | #if (BITS_PER_LONG == 64) | ||
| 63 | # define KTIME_SEC_MAX (KTIME_MAX / NSEC_PER_SEC) | ||
| 64 | #else | ||
| 65 | # define KTIME_SEC_MAX LONG_MAX | ||
| 66 | #endif | ||
| 67 | |||
| 68 | /* | 61 | /* |
| 69 | * ktime_t definitions when using the 64-bit scalar representation: | 62 | * ktime_t definitions when using the 64-bit scalar representation: |
| 70 | */ | 63 | */ |
diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h index 5b90e94399e1..c410d99bd667 100644 --- a/include/linux/mfd/dbx500-prcmu.h +++ b/include/linux/mfd/dbx500-prcmu.h | |||
| @@ -136,6 +136,7 @@ enum prcmu_clock { | |||
| 136 | PRCMU_TIMCLK, | 136 | PRCMU_TIMCLK, |
| 137 | PRCMU_PLLSOC0, | 137 | PRCMU_PLLSOC0, |
| 138 | PRCMU_PLLSOC1, | 138 | PRCMU_PLLSOC1, |
| 139 | PRCMU_ARMSS, | ||
| 139 | PRCMU_PLLDDR, | 140 | PRCMU_PLLDDR, |
| 140 | PRCMU_PLLDSI, | 141 | PRCMU_PLLDSI, |
| 141 | PRCMU_DSI0CLK, | 142 | PRCMU_DSI0CLK, |
diff --git a/include/linux/mv643xx_eth.h b/include/linux/mv643xx_eth.h index 51bf8ada6dc0..49258e0ed1c6 100644 --- a/include/linux/mv643xx_eth.h +++ b/include/linux/mv643xx_eth.h | |||
| @@ -15,6 +15,8 @@ | |||
| 15 | #define MV643XX_ETH_SIZE_REG_4 0x2224 | 15 | #define MV643XX_ETH_SIZE_REG_4 0x2224 |
| 16 | #define MV643XX_ETH_BASE_ADDR_ENABLE_REG 0x2290 | 16 | #define MV643XX_ETH_BASE_ADDR_ENABLE_REG 0x2290 |
| 17 | 17 | ||
| 18 | #define MV643XX_TX_CSUM_DEFAULT_LIMIT 0 | ||
| 19 | |||
| 18 | struct mv643xx_eth_shared_platform_data { | 20 | struct mv643xx_eth_shared_platform_data { |
| 19 | struct mbus_dram_target_info *dram; | 21 | struct mbus_dram_target_info *dram; |
| 20 | struct platform_device *shared_smi; | 22 | struct platform_device *shared_smi; |
diff --git a/include/linux/platform_data/clk-realview.h b/include/linux/platform_data/clk-realview.h new file mode 100644 index 000000000000..2e426a7dbc51 --- /dev/null +++ b/include/linux/platform_data/clk-realview.h | |||
| @@ -0,0 +1 @@ | |||
| void realview_clk_init(void __iomem *sysbase, bool is_pb1176); | |||
diff --git a/include/linux/platform_data/clk-ux500.h b/include/linux/platform_data/clk-ux500.h new file mode 100644 index 000000000000..3af0da1f3be5 --- /dev/null +++ b/include/linux/platform_data/clk-ux500.h | |||
| @@ -0,0 +1,17 @@ | |||
| 1 | /* | ||
| 2 | * Clock definitions for ux500 platforms | ||
| 3 | * | ||
| 4 | * Copyright (C) 2012 ST-Ericsson SA | ||
| 5 | * Author: Ulf Hansson <ulf.hansson@linaro.org> | ||
| 6 | * | ||
| 7 | * License terms: GNU General Public License (GPL) version 2 | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __CLK_UX500_H | ||
| 11 | #define __CLK_UX500_H | ||
| 12 | |||
| 13 | void u8500_clk_init(void); | ||
| 14 | void u9540_clk_init(void); | ||
| 15 | void u8540_clk_init(void); | ||
| 16 | |||
| 17 | #endif /* __CLK_UX500_H */ | ||
diff --git a/include/linux/time.h b/include/linux/time.h index c81c5e40fcb5..b51e664c83e7 100644 --- a/include/linux/time.h +++ b/include/linux/time.h | |||
| @@ -107,11 +107,36 @@ static inline struct timespec timespec_sub(struct timespec lhs, | |||
| 107 | return ts_delta; | 107 | return ts_delta; |
| 108 | } | 108 | } |
| 109 | 109 | ||
| 110 | #define KTIME_MAX ((s64)~((u64)1 << 63)) | ||
| 111 | #if (BITS_PER_LONG == 64) | ||
| 112 | # define KTIME_SEC_MAX (KTIME_MAX / NSEC_PER_SEC) | ||
| 113 | #else | ||
| 114 | # define KTIME_SEC_MAX LONG_MAX | ||
| 115 | #endif | ||
| 116 | |||
| 110 | /* | 117 | /* |
| 111 | * Returns true if the timespec is norm, false if denorm: | 118 | * Returns true if the timespec is norm, false if denorm: |
| 112 | */ | 119 | */ |
| 113 | #define timespec_valid(ts) \ | 120 | static inline bool timespec_valid(const struct timespec *ts) |
| 114 | (((ts)->tv_sec >= 0) && (((unsigned long) (ts)->tv_nsec) < NSEC_PER_SEC)) | 121 | { |
| 122 | /* Dates before 1970 are bogus */ | ||
| 123 | if (ts->tv_sec < 0) | ||
| 124 | return false; | ||
| 125 | /* Can't have more nanoseconds then a second */ | ||
| 126 | if ((unsigned long)ts->tv_nsec >= NSEC_PER_SEC) | ||
| 127 | return false; | ||
| 128 | return true; | ||
| 129 | } | ||
| 130 | |||
| 131 | static inline bool timespec_valid_strict(const struct timespec *ts) | ||
| 132 | { | ||
| 133 | if (!timespec_valid(ts)) | ||
| 134 | return false; | ||
| 135 | /* Disallow values that could overflow ktime_t */ | ||
| 136 | if ((unsigned long long)ts->tv_sec >= KTIME_SEC_MAX) | ||
| 137 | return false; | ||
| 138 | return true; | ||
| 139 | } | ||
| 115 | 140 | ||
| 116 | extern void read_persistent_clock(struct timespec *ts); | 141 | extern void read_persistent_clock(struct timespec *ts); |
| 117 | extern void read_boot_clock(struct timespec *ts); | 142 | extern void read_boot_clock(struct timespec *ts); |
diff --git a/include/xen/events.h b/include/xen/events.h index 9c641deb65d2..04399b28e821 100644 --- a/include/xen/events.h +++ b/include/xen/events.h | |||
| @@ -58,8 +58,6 @@ void notify_remote_via_irq(int irq); | |||
| 58 | 58 | ||
| 59 | void xen_irq_resume(void); | 59 | void xen_irq_resume(void); |
| 60 | 60 | ||
| 61 | void xen_hvm_prepare_kexec(struct shared_info *sip, unsigned long pfn); | ||
| 62 | |||
| 63 | /* Clear an irq's pending state, in preparation for polling on it */ | 61 | /* Clear an irq's pending state, in preparation for polling on it */ |
| 64 | void xen_clear_irq_pending(int irq); | 62 | void xen_clear_irq_pending(int irq); |
| 65 | void xen_set_irq_pending(int irq); | 63 | void xen_set_irq_pending(int irq); |
diff --git a/kernel/fork.c b/kernel/fork.c index 3bd2280d79f6..2c8857e12855 100644 --- a/kernel/fork.c +++ b/kernel/fork.c | |||
| @@ -455,8 +455,8 @@ static int dup_mmap(struct mm_struct *mm, struct mm_struct *oldmm) | |||
| 455 | if (retval) | 455 | if (retval) |
| 456 | goto out; | 456 | goto out; |
| 457 | 457 | ||
| 458 | if (file && uprobe_mmap(tmp)) | 458 | if (file) |
| 459 | goto out; | 459 | uprobe_mmap(tmp); |
| 460 | } | 460 | } |
| 461 | /* a new mm has just been created */ | 461 | /* a new mm has just been created */ |
| 462 | arch_dup_mmap(oldmm, mm); | 462 | arch_dup_mmap(oldmm, mm); |
diff --git a/kernel/time/timekeeping.c b/kernel/time/timekeeping.c index e16af197a2bc..34e5eac81424 100644 --- a/kernel/time/timekeeping.c +++ b/kernel/time/timekeeping.c | |||
| @@ -115,6 +115,7 @@ static void tk_xtime_add(struct timekeeper *tk, const struct timespec *ts) | |||
| 115 | { | 115 | { |
| 116 | tk->xtime_sec += ts->tv_sec; | 116 | tk->xtime_sec += ts->tv_sec; |
| 117 | tk->xtime_nsec += (u64)ts->tv_nsec << tk->shift; | 117 | tk->xtime_nsec += (u64)ts->tv_nsec << tk->shift; |
| 118 | tk_normalize_xtime(tk); | ||
| 118 | } | 119 | } |
| 119 | 120 | ||
| 120 | static void tk_set_wall_to_mono(struct timekeeper *tk, struct timespec wtm) | 121 | static void tk_set_wall_to_mono(struct timekeeper *tk, struct timespec wtm) |
| @@ -276,7 +277,7 @@ static void timekeeping_forward_now(struct timekeeper *tk) | |||
| 276 | tk->xtime_nsec += cycle_delta * tk->mult; | 277 | tk->xtime_nsec += cycle_delta * tk->mult; |
| 277 | 278 | ||
| 278 | /* If arch requires, add in gettimeoffset() */ | 279 | /* If arch requires, add in gettimeoffset() */ |
| 279 | tk->xtime_nsec += arch_gettimeoffset() << tk->shift; | 280 | tk->xtime_nsec += (u64)arch_gettimeoffset() << tk->shift; |
| 280 | 281 | ||
| 281 | tk_normalize_xtime(tk); | 282 | tk_normalize_xtime(tk); |
| 282 | 283 | ||
| @@ -427,7 +428,7 @@ int do_settimeofday(const struct timespec *tv) | |||
| 427 | struct timespec ts_delta, xt; | 428 | struct timespec ts_delta, xt; |
| 428 | unsigned long flags; | 429 | unsigned long flags; |
| 429 | 430 | ||
| 430 | if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC) | 431 | if (!timespec_valid_strict(tv)) |
| 431 | return -EINVAL; | 432 | return -EINVAL; |
| 432 | 433 | ||
| 433 | write_seqlock_irqsave(&tk->lock, flags); | 434 | write_seqlock_irqsave(&tk->lock, flags); |
| @@ -463,6 +464,8 @@ int timekeeping_inject_offset(struct timespec *ts) | |||
| 463 | { | 464 | { |
| 464 | struct timekeeper *tk = &timekeeper; | 465 | struct timekeeper *tk = &timekeeper; |
| 465 | unsigned long flags; | 466 | unsigned long flags; |
| 467 | struct timespec tmp; | ||
| 468 | int ret = 0; | ||
| 466 | 469 | ||
| 467 | if ((unsigned long)ts->tv_nsec >= NSEC_PER_SEC) | 470 | if ((unsigned long)ts->tv_nsec >= NSEC_PER_SEC) |
| 468 | return -EINVAL; | 471 | return -EINVAL; |
| @@ -471,10 +474,17 @@ int timekeeping_inject_offset(struct timespec *ts) | |||
| 471 | 474 | ||
| 472 | timekeeping_forward_now(tk); | 475 | timekeeping_forward_now(tk); |
| 473 | 476 | ||
| 477 | /* Make sure the proposed value is valid */ | ||
| 478 | tmp = timespec_add(tk_xtime(tk), *ts); | ||
| 479 | if (!timespec_valid_strict(&tmp)) { | ||
| 480 | ret = -EINVAL; | ||
| 481 | goto error; | ||
| 482 | } | ||
| 474 | 483 | ||
| 475 | tk_xtime_add(tk, ts); | 484 | tk_xtime_add(tk, ts); |
| 476 | tk_set_wall_to_mono(tk, timespec_sub(tk->wall_to_monotonic, *ts)); | 485 | tk_set_wall_to_mono(tk, timespec_sub(tk->wall_to_monotonic, *ts)); |
| 477 | 486 | ||
| 487 | error: /* even if we error out, we forwarded the time, so call update */ | ||
| 478 | timekeeping_update(tk, true); | 488 | timekeeping_update(tk, true); |
| 479 | 489 | ||
| 480 | write_sequnlock_irqrestore(&tk->lock, flags); | 490 | write_sequnlock_irqrestore(&tk->lock, flags); |
| @@ -482,7 +492,7 @@ int timekeeping_inject_offset(struct timespec *ts) | |||
| 482 | /* signal hrtimers about time change */ | 492 | /* signal hrtimers about time change */ |
| 483 | clock_was_set(); | 493 | clock_was_set(); |
| 484 | 494 | ||
| 485 | return 0; | 495 | return ret; |
| 486 | } | 496 | } |
| 487 | EXPORT_SYMBOL(timekeeping_inject_offset); | 497 | EXPORT_SYMBOL(timekeeping_inject_offset); |
| 488 | 498 | ||
| @@ -649,7 +659,20 @@ void __init timekeeping_init(void) | |||
| 649 | struct timespec now, boot, tmp; | 659 | struct timespec now, boot, tmp; |
| 650 | 660 | ||
| 651 | read_persistent_clock(&now); | 661 | read_persistent_clock(&now); |
| 662 | if (!timespec_valid_strict(&now)) { | ||
| 663 | pr_warn("WARNING: Persistent clock returned invalid value!\n" | ||
| 664 | " Check your CMOS/BIOS settings.\n"); | ||
| 665 | now.tv_sec = 0; | ||
| 666 | now.tv_nsec = 0; | ||
| 667 | } | ||
| 668 | |||
| 652 | read_boot_clock(&boot); | 669 | read_boot_clock(&boot); |
| 670 | if (!timespec_valid_strict(&boot)) { | ||
| 671 | pr_warn("WARNING: Boot clock returned invalid value!\n" | ||
| 672 | " Check your CMOS/BIOS settings.\n"); | ||
| 673 | boot.tv_sec = 0; | ||
| 674 | boot.tv_nsec = 0; | ||
| 675 | } | ||
| 653 | 676 | ||
| 654 | seqlock_init(&tk->lock); | 677 | seqlock_init(&tk->lock); |
| 655 | 678 | ||
| @@ -690,7 +713,7 @@ static struct timespec timekeeping_suspend_time; | |||
| 690 | static void __timekeeping_inject_sleeptime(struct timekeeper *tk, | 713 | static void __timekeeping_inject_sleeptime(struct timekeeper *tk, |
| 691 | struct timespec *delta) | 714 | struct timespec *delta) |
| 692 | { | 715 | { |
| 693 | if (!timespec_valid(delta)) { | 716 | if (!timespec_valid_strict(delta)) { |
| 694 | printk(KERN_WARNING "__timekeeping_inject_sleeptime: Invalid " | 717 | printk(KERN_WARNING "__timekeeping_inject_sleeptime: Invalid " |
| 695 | "sleep delta value!\n"); | 718 | "sleep delta value!\n"); |
| 696 | return; | 719 | return; |
| @@ -1129,6 +1152,10 @@ static void update_wall_time(void) | |||
| 1129 | offset = (clock->read(clock) - clock->cycle_last) & clock->mask; | 1152 | offset = (clock->read(clock) - clock->cycle_last) & clock->mask; |
| 1130 | #endif | 1153 | #endif |
| 1131 | 1154 | ||
| 1155 | /* Check if there's really nothing to do */ | ||
| 1156 | if (offset < tk->cycle_interval) | ||
| 1157 | goto out; | ||
| 1158 | |||
| 1132 | /* | 1159 | /* |
| 1133 | * With NO_HZ we may have to accumulate many cycle_intervals | 1160 | * With NO_HZ we may have to accumulate many cycle_intervals |
| 1134 | * (think "ticks") worth of time at once. To do this efficiently, | 1161 | * (think "ticks") worth of time at once. To do this efficiently, |
| @@ -1161,9 +1188,9 @@ static void update_wall_time(void) | |||
| 1161 | * the vsyscall implementations are converted to use xtime_nsec | 1188 | * the vsyscall implementations are converted to use xtime_nsec |
| 1162 | * (shifted nanoseconds), this can be killed. | 1189 | * (shifted nanoseconds), this can be killed. |
| 1163 | */ | 1190 | */ |
| 1164 | remainder = tk->xtime_nsec & ((1 << tk->shift) - 1); | 1191 | remainder = tk->xtime_nsec & ((1ULL << tk->shift) - 1); |
| 1165 | tk->xtime_nsec -= remainder; | 1192 | tk->xtime_nsec -= remainder; |
| 1166 | tk->xtime_nsec += 1 << tk->shift; | 1193 | tk->xtime_nsec += 1ULL << tk->shift; |
| 1167 | tk->ntp_error += remainder << tk->ntp_error_shift; | 1194 | tk->ntp_error += remainder << tk->ntp_error_shift; |
| 1168 | 1195 | ||
| 1169 | /* | 1196 | /* |
diff --git a/kernel/trace/trace_syscalls.c b/kernel/trace/trace_syscalls.c index 60e4d7875672..6b245f64c8dd 100644 --- a/kernel/trace/trace_syscalls.c +++ b/kernel/trace/trace_syscalls.c | |||
| @@ -506,6 +506,8 @@ static void perf_syscall_enter(void *ignore, struct pt_regs *regs, long id) | |||
| 506 | int size; | 506 | int size; |
| 507 | 507 | ||
| 508 | syscall_nr = syscall_get_nr(current, regs); | 508 | syscall_nr = syscall_get_nr(current, regs); |
| 509 | if (syscall_nr < 0) | ||
| 510 | return; | ||
| 509 | if (!test_bit(syscall_nr, enabled_perf_enter_syscalls)) | 511 | if (!test_bit(syscall_nr, enabled_perf_enter_syscalls)) |
| 510 | return; | 512 | return; |
| 511 | 513 | ||
| @@ -580,6 +582,8 @@ static void perf_syscall_exit(void *ignore, struct pt_regs *regs, long ret) | |||
| 580 | int size; | 582 | int size; |
| 581 | 583 | ||
| 582 | syscall_nr = syscall_get_nr(current, regs); | 584 | syscall_nr = syscall_get_nr(current, regs); |
| 585 | if (syscall_nr < 0) | ||
| 586 | return; | ||
| 583 | if (!test_bit(syscall_nr, enabled_perf_exit_syscalls)) | 587 | if (!test_bit(syscall_nr, enabled_perf_exit_syscalls)) |
| 584 | return; | 588 | return; |
| 585 | 589 | ||
diff --git a/mm/filemap.c b/mm/filemap.c index fa5ca304148e..384344575c37 100644 --- a/mm/filemap.c +++ b/mm/filemap.c | |||
| @@ -1412,12 +1412,8 @@ generic_file_aio_read(struct kiocb *iocb, const struct iovec *iov, | |||
| 1412 | retval = filemap_write_and_wait_range(mapping, pos, | 1412 | retval = filemap_write_and_wait_range(mapping, pos, |
| 1413 | pos + iov_length(iov, nr_segs) - 1); | 1413 | pos + iov_length(iov, nr_segs) - 1); |
| 1414 | if (!retval) { | 1414 | if (!retval) { |
| 1415 | struct blk_plug plug; | ||
| 1416 | |||
| 1417 | blk_start_plug(&plug); | ||
| 1418 | retval = mapping->a_ops->direct_IO(READ, iocb, | 1415 | retval = mapping->a_ops->direct_IO(READ, iocb, |
| 1419 | iov, pos, nr_segs); | 1416 | iov, pos, nr_segs); |
| 1420 | blk_finish_plug(&plug); | ||
| 1421 | } | 1417 | } |
| 1422 | if (retval > 0) { | 1418 | if (retval > 0) { |
| 1423 | *ppos = pos + retval; | 1419 | *ppos = pos + retval; |
| @@ -2527,14 +2523,12 @@ ssize_t generic_file_aio_write(struct kiocb *iocb, const struct iovec *iov, | |||
| 2527 | { | 2523 | { |
| 2528 | struct file *file = iocb->ki_filp; | 2524 | struct file *file = iocb->ki_filp; |
| 2529 | struct inode *inode = file->f_mapping->host; | 2525 | struct inode *inode = file->f_mapping->host; |
| 2530 | struct blk_plug plug; | ||
| 2531 | ssize_t ret; | 2526 | ssize_t ret; |
| 2532 | 2527 | ||
| 2533 | BUG_ON(iocb->ki_pos != pos); | 2528 | BUG_ON(iocb->ki_pos != pos); |
| 2534 | 2529 | ||
| 2535 | sb_start_write(inode->i_sb); | 2530 | sb_start_write(inode->i_sb); |
| 2536 | mutex_lock(&inode->i_mutex); | 2531 | mutex_lock(&inode->i_mutex); |
| 2537 | blk_start_plug(&plug); | ||
| 2538 | ret = __generic_file_aio_write(iocb, iov, nr_segs, &iocb->ki_pos); | 2532 | ret = __generic_file_aio_write(iocb, iov, nr_segs, &iocb->ki_pos); |
| 2539 | mutex_unlock(&inode->i_mutex); | 2533 | mutex_unlock(&inode->i_mutex); |
| 2540 | 2534 | ||
| @@ -2545,7 +2539,6 @@ ssize_t generic_file_aio_write(struct kiocb *iocb, const struct iovec *iov, | |||
| 2545 | if (err < 0 && ret > 0) | 2539 | if (err < 0 && ret > 0) |
| 2546 | ret = err; | 2540 | ret = err; |
| 2547 | } | 2541 | } |
| 2548 | blk_finish_plug(&plug); | ||
| 2549 | sb_end_write(inode->i_sb); | 2542 | sb_end_write(inode->i_sb); |
| 2550 | return ret; | 2543 | return ret; |
| 2551 | } | 2544 | } |
| @@ -1356,9 +1356,8 @@ out: | |||
| 1356 | } else if ((flags & MAP_POPULATE) && !(flags & MAP_NONBLOCK)) | 1356 | } else if ((flags & MAP_POPULATE) && !(flags & MAP_NONBLOCK)) |
| 1357 | make_pages_present(addr, addr + len); | 1357 | make_pages_present(addr, addr + len); |
| 1358 | 1358 | ||
| 1359 | if (file && uprobe_mmap(vma)) | 1359 | if (file) |
| 1360 | /* matching probes but cannot insert */ | 1360 | uprobe_mmap(vma); |
| 1361 | goto unmap_and_free_vma; | ||
| 1362 | 1361 | ||
| 1363 | return addr; | 1362 | return addr; |
| 1364 | 1363 | ||
| @@ -3260,6 +3260,7 @@ force_grow: | |||
| 3260 | 3260 | ||
| 3261 | /* cache_grow can reenable interrupts, then ac could change. */ | 3261 | /* cache_grow can reenable interrupts, then ac could change. */ |
| 3262 | ac = cpu_cache_get(cachep); | 3262 | ac = cpu_cache_get(cachep); |
| 3263 | node = numa_mem_id(); | ||
| 3263 | 3264 | ||
| 3264 | /* no objects in sight? abort */ | 3265 | /* no objects in sight? abort */ |
| 3265 | if (!x && (ac->avail == 0 || force_refill)) | 3266 | if (!x && (ac->avail == 0 || force_refill)) |
diff --git a/net/sunrpc/svc_xprt.c b/net/sunrpc/svc_xprt.c index 88f2bf671960..bac973a31367 100644 --- a/net/sunrpc/svc_xprt.c +++ b/net/sunrpc/svc_xprt.c | |||
| @@ -316,7 +316,6 @@ static bool svc_xprt_has_something_to_do(struct svc_xprt *xprt) | |||
| 316 | */ | 316 | */ |
| 317 | void svc_xprt_enqueue(struct svc_xprt *xprt) | 317 | void svc_xprt_enqueue(struct svc_xprt *xprt) |
| 318 | { | 318 | { |
| 319 | struct svc_serv *serv = xprt->xpt_server; | ||
| 320 | struct svc_pool *pool; | 319 | struct svc_pool *pool; |
| 321 | struct svc_rqst *rqstp; | 320 | struct svc_rqst *rqstp; |
| 322 | int cpu; | 321 | int cpu; |
| @@ -362,8 +361,6 @@ void svc_xprt_enqueue(struct svc_xprt *xprt) | |||
| 362 | rqstp, rqstp->rq_xprt); | 361 | rqstp, rqstp->rq_xprt); |
| 363 | rqstp->rq_xprt = xprt; | 362 | rqstp->rq_xprt = xprt; |
| 364 | svc_xprt_get(xprt); | 363 | svc_xprt_get(xprt); |
| 365 | rqstp->rq_reserved = serv->sv_max_mesg; | ||
| 366 | atomic_add(rqstp->rq_reserved, &xprt->xpt_reserved); | ||
| 367 | pool->sp_stats.threads_woken++; | 364 | pool->sp_stats.threads_woken++; |
| 368 | wake_up(&rqstp->rq_wait); | 365 | wake_up(&rqstp->rq_wait); |
| 369 | } else { | 366 | } else { |
| @@ -640,8 +637,6 @@ int svc_recv(struct svc_rqst *rqstp, long timeout) | |||
| 640 | if (xprt) { | 637 | if (xprt) { |
| 641 | rqstp->rq_xprt = xprt; | 638 | rqstp->rq_xprt = xprt; |
| 642 | svc_xprt_get(xprt); | 639 | svc_xprt_get(xprt); |
| 643 | rqstp->rq_reserved = serv->sv_max_mesg; | ||
| 644 | atomic_add(rqstp->rq_reserved, &xprt->xpt_reserved); | ||
| 645 | 640 | ||
| 646 | /* As there is a shortage of threads and this request | 641 | /* As there is a shortage of threads and this request |
| 647 | * had to be queued, don't allow the thread to wait so | 642 | * had to be queued, don't allow the thread to wait so |
| @@ -738,6 +733,8 @@ int svc_recv(struct svc_rqst *rqstp, long timeout) | |||
| 738 | else | 733 | else |
| 739 | len = xprt->xpt_ops->xpo_recvfrom(rqstp); | 734 | len = xprt->xpt_ops->xpo_recvfrom(rqstp); |
| 740 | dprintk("svc: got len=%d\n", len); | 735 | dprintk("svc: got len=%d\n", len); |
| 736 | rqstp->rq_reserved = serv->sv_max_mesg; | ||
| 737 | atomic_add(rqstp->rq_reserved, &xprt->xpt_reserved); | ||
| 741 | } | 738 | } |
| 742 | svc_xprt_received(xprt); | 739 | svc_xprt_received(xprt); |
| 743 | 740 | ||
| @@ -794,7 +791,8 @@ int svc_send(struct svc_rqst *rqstp) | |||
| 794 | 791 | ||
| 795 | /* Grab mutex to serialize outgoing data. */ | 792 | /* Grab mutex to serialize outgoing data. */ |
| 796 | mutex_lock(&xprt->xpt_mutex); | 793 | mutex_lock(&xprt->xpt_mutex); |
| 797 | if (test_bit(XPT_DEAD, &xprt->xpt_flags)) | 794 | if (test_bit(XPT_DEAD, &xprt->xpt_flags) |
| 795 | || test_bit(XPT_CLOSE, &xprt->xpt_flags)) | ||
| 798 | len = -ENOTCONN; | 796 | len = -ENOTCONN; |
| 799 | else | 797 | else |
| 800 | len = xprt->xpt_ops->xpo_sendto(rqstp); | 798 | len = xprt->xpt_ops->xpo_sendto(rqstp); |
diff --git a/net/sunrpc/svcsock.c b/net/sunrpc/svcsock.c index 18bc130255a7..998aa8c1807c 100644 --- a/net/sunrpc/svcsock.c +++ b/net/sunrpc/svcsock.c | |||
| @@ -1129,9 +1129,9 @@ static int svc_tcp_recvfrom(struct svc_rqst *rqstp) | |||
| 1129 | if (len >= 0) | 1129 | if (len >= 0) |
| 1130 | svsk->sk_tcplen += len; | 1130 | svsk->sk_tcplen += len; |
| 1131 | if (len != want) { | 1131 | if (len != want) { |
| 1132 | svc_tcp_save_pages(svsk, rqstp); | ||
| 1132 | if (len < 0 && len != -EAGAIN) | 1133 | if (len < 0 && len != -EAGAIN) |
| 1133 | goto err_other; | 1134 | goto err_other; |
| 1134 | svc_tcp_save_pages(svsk, rqstp); | ||
| 1135 | dprintk("svc: incomplete TCP record (%d of %d)\n", | 1135 | dprintk("svc: incomplete TCP record (%d of %d)\n", |
| 1136 | svsk->sk_tcplen, svsk->sk_reclen); | 1136 | svsk->sk_tcplen, svsk->sk_reclen); |
| 1137 | goto err_noclose; | 1137 | goto err_noclose; |
diff --git a/tools/perf/util/python-ext-sources b/tools/perf/util/python-ext-sources index 2884e67ee625..213362850abd 100644 --- a/tools/perf/util/python-ext-sources +++ b/tools/perf/util/python-ext-sources | |||
| @@ -10,10 +10,12 @@ util/ctype.c | |||
| 10 | util/evlist.c | 10 | util/evlist.c |
| 11 | util/evsel.c | 11 | util/evsel.c |
| 12 | util/cpumap.c | 12 | util/cpumap.c |
| 13 | util/hweight.c | ||
| 13 | util/thread_map.c | 14 | util/thread_map.c |
| 14 | util/util.c | 15 | util/util.c |
| 15 | util/xyarray.c | 16 | util/xyarray.c |
| 16 | util/cgroup.c | 17 | util/cgroup.c |
| 17 | util/debugfs.c | 18 | util/debugfs.c |
| 19 | util/rblist.c | ||
| 18 | util/strlist.c | 20 | util/strlist.c |
| 19 | ../../lib/rbtree.c | 21 | ../../lib/rbtree.c |
diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c index 246852397e30..d617f69131d7 100644 --- a/virt/kvm/kvm_main.c +++ b/virt/kvm/kvm_main.c | |||
| @@ -1976,9 +1976,10 @@ static long kvm_vcpu_compat_ioctl(struct file *filp, | |||
| 1976 | if (copy_from_user(&csigset, sigmask_arg->sigset, | 1976 | if (copy_from_user(&csigset, sigmask_arg->sigset, |
| 1977 | sizeof csigset)) | 1977 | sizeof csigset)) |
| 1978 | goto out; | 1978 | goto out; |
| 1979 | } | 1979 | sigset_from_compat(&sigset, &csigset); |
| 1980 | sigset_from_compat(&sigset, &csigset); | 1980 | r = kvm_vcpu_ioctl_set_sigmask(vcpu, &sigset); |
| 1981 | r = kvm_vcpu_ioctl_set_sigmask(vcpu, &sigset); | 1981 | } else |
| 1982 | r = kvm_vcpu_ioctl_set_sigmask(vcpu, NULL); | ||
| 1982 | break; | 1983 | break; |
| 1983 | } | 1984 | } |
| 1984 | default: | 1985 | default: |