18 files changed, 171 insertions, 78 deletions
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 1943fc333e7c..8a099bc10c1e 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -15,7 +15,7 @@
 / {
        compatible = "ti,am4372", "ti,am43";
-        interrupt-parent = <&gic>;
+        interrupt-parent = <&wakeupgen>;
        aliases {
@@ -48,6 +48,15 @@
                #interrupt-cells = <3>;
                reg = <0x48241000 0x1000>,
                      <0x48240100 0x0100>;
+                interrupt-parent = <&gic>;
+        };
+        wakeupgen: interrupt-controller@48281000 {
+                compatible = "ti,omap4-wugen-mpu";
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                reg = <0x48281000 0x1000>;
+                interrupt-parent = <&gic>;
        };
        l2-cache-controller@48242000 {
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index f84d9715a4a9..26956cb50835 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -352,7 +352,6 @@
                reg = <0x24>;
                compatible = "ti,tps65218";
                interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
-                interrupt-parent = <&gic>;
                interrupt-controller;
                #interrupt-cells = <2>;
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts
index 832d24318f62..8ae29c955c11 100644
--- a/arch/arm/boot/dts/am437x-sk-evm.dts
+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
@@ -392,7 +392,6 @@
        tps@24 {
                compatible = "ti,tps65218";
                reg = <0x24>;
-                interrupt-parent = <&gic>;
                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-controller;
                #interrupt-cells = <2>;
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index 257c099c347e..1d7109196872 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -369,7 +369,6 @@
                reg = <0x24>;
                compatible = "ti,tps65218";
                interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
-                interrupt-parent = <&gic>;
                interrupt-controller;
                #interrupt-cells = <2>;
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 850f949d409a..c65eea095afa 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -64,6 +64,14 @@
                interrupt-parent = <&gic>;
        };
+        wakeupgen: interrupt-controller@48281000 {
+                compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                reg = <0x48281000 0x1000>;
+                interrupt-parent = <&gic>;
+        };
        /*
         * The soc node represents the soc top level view. It is used for IPs
         * that are not memory mapped in the MPU view or for the MPU itself.
@@ -92,7 +100,7 @@
                reg = <0x44000000 0x1000000>,
                      <0x45000000 0x1000>;
                interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
-                                      <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+                                      <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
                prm: prm@4ae06000 {
                        compatible = "ti,dra7-prm";
@@ -1341,7 +1349,7 @@
                        compatible = "ti,irq-crossbar";
                        reg = <0x4a002a48 0x130>;
                        interrupt-controller;
-                        interrupt-parent = <&gic>;
+                        interrupt-parent = <&wakeupgen>;
                        #interrupt-cells = <3>;
                        ti,max-irqs = <160>;
                        ti,max-crossbar-sources = <MAX_SOURCES>;
diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi
index e782bf1dd863..f7fb0d0ef25a 100644
--- a/arch/arm/boot/dts/dra72x.dtsi
+++ b/arch/arm/boot/dts/dra72x.dtsi
@@ -25,7 +25,7 @@
        pmu {
                compatible = "arm,cortex-a15-pmu";
-                interrupt-parent = <&gic>;
+                interrupt-parent = <&wakeupgen>;
                interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
        };
 };
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index 0fc758db55f5..00eeed789b4b 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -41,7 +41,7 @@
        pmu {
                compatible = "arm,cortex-a15-pmu";
-                interrupt-parent = <&gic>;
+                interrupt-parent = <&wakeupgen>;
                interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
        };
diff --git a/arch/arm/boot/dts/omap4-duovero.dtsi b/arch/arm/boot/dts/omap4-duovero.dtsi
index e860ccd9d09c..f2a94fa62552 100644
--- a/arch/arm/boot/dts/omap4-duovero.dtsi
+++ b/arch/arm/boot/dts/omap4-duovero.dtsi
@@ -173,14 +173,12 @@
        twl: twl@48 {
                reg = <0x48>;
                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;           /* IRQ_SYS_1N cascaded to gic */
-                interrupt-parent = <&gic>;
        };
        twl6040: twl@4b {
                compatible = "ti,twl6040";
                reg = <0x4b>;
                interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;         /* IRQ_SYS_2N cascaded to gic */
-                interrupt-parent = <&gic>;
                ti,audpwron-gpio = <&gpio6 0 GPIO_ACTIVE_HIGH>;         /* gpio_160 */
                vio-supply = <&v1v8>;
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 150513506c19..7c15fb2e2fe4 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -372,7 +372,6 @@
                reg = <0x48>;
                /* IRQ# = 7 */
                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
-                interrupt-parent = <&gic>;
        };
        twl6040: twl@4b {
@@ -384,7 +383,6 @@
                /* IRQ# = 119 */
                interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
-                interrupt-parent = <&gic>;
                ti,audpwron-gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>;  /* gpio line 127 */
                vio-supply = <&v1v8>;
@@ -479,17 +477,17 @@
 };
 &uart2 {
-        interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH
+        interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH
                               &omap4_pmx_core OMAP4_UART2_RX>;
 };
 &uart3 {
-        interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
+        interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
                               &omap4_pmx_core OMAP4_UART3_RX>;
 };
 &uart4 {
-        interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
+        interrupts-extended = <&wakeupgen GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
                               &omap4_pmx_core OMAP4_UART4_RX>;
 };
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 3e1da43068f6..8aca8dae968a 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -363,7 +363,6 @@
                reg = <0x48>;
                /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
-                interrupt-parent = <&gic>;
        };
        twl6040: twl@4b {
@@ -375,7 +374,6 @@
                /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
                interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
-                interrupt-parent = <&gic>;
                ti,audpwron-gpio = <&gpio4 31 0>;  /* gpio line 127 */
                vio-supply = <&v1v8>;
@@ -570,21 +568,21 @@
 };
 &uart2 {
-        interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH
+        interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH
                               &omap4_pmx_core OMAP4_UART2_RX>;
        pinctrl-names = "default";
        pinctrl-0 = <&uart2_pins>;
 };
 &uart3 {
-        interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
+        interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
                               &omap4_pmx_core OMAP4_UART3_RX>;
        pinctrl-names = "default";
        pinctrl-0 = <&uart3_pins>;
 };
 &uart4 {
-        interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
+        interrupts-extended = <&wakeupgen GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
                               &omap4_pmx_core OMAP4_UART4_RX>;
        pinctrl-names = "default";
        pinctrl-0 = <&uart4_pins>;
diff --git a/arch/arm/boot/dts/omap4-var-som-om44.dtsi b/arch/arm/boot/dts/omap4-var-som-om44.dtsi
index 062701e1a898..a4f1ba2e1903 100644
--- a/arch/arm/boot/dts/omap4-var-som-om44.dtsi
+++ b/arch/arm/boot/dts/omap4-var-som-om44.dtsi
@@ -185,7 +185,6 @@
                reg = <0x48>;
                /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
-                interrupt-parent = <&gic>;
        };
        twl6040: twl@4b {
@@ -197,7 +196,6 @@
                /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
                interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
-                interrupt-parent = <&gic>;
                ti,audpwron-gpio = <&gpio6 22 0>; /* gpio 182 */
                vio-supply = <&v1v8>;
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 074147cebae4..7cb5236f751d 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -14,7 +14,7 @@
 / {
        compatible = "ti,omap4430", "ti,omap4";
-        interrupt-parent = <&gic>;
+        interrupt-parent = <&wakeupgen>;
        aliases {
                i2c0 = &i2c1;
@@ -56,6 +56,7 @@
                #interrupt-cells = <3>;
                reg = <0x48241000 0x1000>,
                      <0x48240100 0x0100>;
+                interrupt-parent = <&gic>;
        };
        L2: l2-cache-controller@48242000 {
@@ -70,6 +71,15 @@
                clocks = <&mpu_periphclk>;
                reg = <0x48240600 0x20>;
                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
+                interrupt-parent = <&gic>;
+        };
+        wakeupgen: interrupt-controller@48281000 {
+                compatible = "ti,omap4-wugen-mpu";
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                reg = <0x48281000 0x1000>;
+                interrupt-parent = <&gic>;
        };
        /*
@@ -319,7 +329,7 @@
                uart2: serial@4806c000 {
                        compatible = "ti,omap4-uart";
                        reg = <0x4806c000 0x100>;
-                        interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "uart2";
                        clock-frequency = <48000000>;
                };
@@ -327,7 +337,7 @@
                uart3: serial@48020000 {
                        compatible = "ti,omap4-uart";
                        reg = <0x48020000 0x100>;
-                        interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "uart3";
                        clock-frequency = <48000000>;
                };
@@ -335,7 +345,7 @@
                uart4: serial@4806e000 {
                        compatible = "ti,omap4-uart";
                        reg = <0x4806e000 0x100>;
-                        interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "uart4";
                        clock-frequency = <48000000>;
                };
diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts
index b54b271e153b..61ad2ea34720 100644
--- a/arch/arm/boot/dts/omap5-cm-t54.dts
+++ b/arch/arm/boot/dts/omap5-cm-t54.dts
@@ -412,7 +412,6 @@
        palmas: palmas@48 {
                compatible = "ti,palmas";
                interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
-                interrupt-parent = <&gic>;
                reg = <0x48>;
                interrupt-controller;
                #interrupt-cells = <2>;
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
index 159720d6c956..74777a6e200a 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -311,7 +311,6 @@
        palmas: palmas@48 {
                compatible = "ti,palmas";
                interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
-                interrupt-parent = <&gic>;
                reg = <0x48>;
                interrupt-controller;
                #interrupt-cells = <2>;
@@ -521,7 +520,6 @@
                pinctrl-0 = <&twl6040_pins>;
                interrupts = <GIC_SPI 119 IRQ_TYPE_NONE>; /* IRQ_SYS_2N cascaded to gic */
-                interrupt-parent = <&gic>;
                ti,audpwron-gpio = <&gpio5 13 0>;  /* gpio line 141 */
                vio-supply = <&smps7_reg>;
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index b321fdf42c9f..b056156e2a7a 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -18,7 +18,7 @@
        #size-cells = <1>;
        compatible = "ti,omap5";
-        interrupt-parent = <&gic>;
+        interrupt-parent = <&wakeupgen>;
        aliases {
                i2c0 = &i2c1;
@@ -79,6 +79,7 @@
                             <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
                             <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
                             <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
+                interrupt-parent = <&gic>;
        };
        pmu {
@@ -95,6 +96,15 @@
                      <0x48212000 0x1000>,
                      <0x48214000 0x2000>,
                      <0x48216000 0x2000>;
+                interrupt-parent = <&gic>;
+        };
+        wakeupgen: interrupt-controller@48281000 {
+                compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                reg = <0x48281000 0x1000>;
+                interrupt-parent = <&gic>;
        };
        /*
@@ -458,7 +468,7 @@
                uart1: serial@4806a000 {
                        compatible = "ti,omap4-uart";
                        reg = <0x4806a000 0x100>;
-                        interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "uart1";
                        clock-frequency = <48000000>;
                };
@@ -466,7 +476,7 @@
                uart2: serial@4806c000 {
                        compatible = "ti,omap4-uart";
                        reg = <0x4806c000 0x100>;
-                        interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "uart2";
                        clock-frequency = <48000000>;
                };
@@ -474,7 +484,7 @@
                uart3: serial@48020000 {
                        compatible = "ti,omap4-uart";
                        reg = <0x48020000 0x100>;
-                        interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "uart3";
                        clock-frequency = <48000000>;
                };
@@ -482,7 +492,7 @@
                uart4: serial@4806e000 {
                        compatible = "ti,omap4-uart";
                        reg = <0x4806e000 0x100>;
-                        interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "uart4";
                        clock-frequency = <48000000>;
                };
@@ -490,7 +500,7 @@
                uart5: serial@48066000 {
                        compatible = "ti,omap4-uart";
                        reg = <0x48066000 0x100>;
-                        interrupts-extended = <&gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "uart5";
                        clock-frequency = <48000000>;
                };
@@ -498,7 +508,7 @@
                uart6: serial@48068000 {
                        compatible = "ti,omap4-uart";
                        reg = <0x48068000 0x100>;
-                        interrupts-extended = <&gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "uart6";
                        clock-frequency = <48000000>;
                };
@@ -883,14 +893,12 @@
                        usbhsohci: ohci@4a064800 {
                                compatible = "ti,ohci-omap3";
                                reg = <0x4a064800 0x400>;
-                                interrupt-parent = <&gic>;
                                interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
                        };
                        usbhsehci: ehci@4a064c00 {
                                compatible = "ti,ehci-omap";
                                reg = <0x4a064c00 0x400>;
-                                interrupt-parent = <&gic>;
                                interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
                        };
                };
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index f961c46453b9..3b56722dfd8a 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -20,11 +20,12 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of_address.h>
 #include <linux/platform_device.h>
 #include <linux/cpu.h>
 #include <linux/notifier.h>
 #include <linux/cpu_pm.h>
-#include <linux/irqchip/arm-gic.h>
 #include "omap-wakeupgen.h"
 #include "omap-secure.h"
@@ -78,29 +79,12 @@ static inline void sar_writel(u32 val, u32 offset, u8 idx)
 static inline int _wakeupgen_get_irq_info(u32 irq, u32 *bit_posn, u8 *reg_index)
 {
-        unsigned int spi_irq;
-        /*
-         * PPIs and SGIs are not supported.
-         */
-        if (irq < OMAP44XX_IRQ_GIC_START)
-                return -EINVAL;
-        /*
-         * Subtract the GIC offset.
-         */
-        spi_irq = irq - OMAP44XX_IRQ_GIC_START;
-        if (spi_irq > MAX_IRQS) {
-                pr_err("omap wakeupGen: Invalid IRQ%d\n", irq);
-                return -EINVAL;
-        }
        /*
         * Each WakeupGen register controls 32 interrupt.
         * i.e. 1 bit per SPI IRQ
         */
-        *reg_index = spi_irq >> 5;
+        *reg_index = irq >> 5;
-        *bit_posn = spi_irq %= 32;
+        *bit_posn = irq %= 32;
        return 0;
 }
@@ -141,6 +125,7 @@ static void wakeupgen_mask(struct irq_data *d)
        raw_spin_lock_irqsave(&wakeupgen_lock, flags);
        _wakeupgen_clear(d->hwirq, irq_target_cpu[d->hwirq]);
        raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
+        irq_chip_mask_parent(d);
 }
 /*
@@ -153,6 +138,7 @@ static void wakeupgen_unmask(struct irq_data *d)
        raw_spin_lock_irqsave(&wakeupgen_lock, flags);
        _wakeupgen_set(d->hwirq, irq_target_cpu[d->hwirq]);
        raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
+        irq_chip_unmask_parent(d);
 }
 #ifdef CONFIG_HOTPLUG_CPU
@@ -400,15 +386,91 @@ int omap_secure_apis_support(void)
        return omap_secure_apis;
 }
+static struct irq_chip wakeupgen_chip = {
+        .name                   = "WUGEN",
+        .irq_eoi                = irq_chip_eoi_parent,
+        .irq_mask               = wakeupgen_mask,
+        .irq_unmask             = wakeupgen_unmask,
+        .irq_retrigger          = irq_chip_retrigger_hierarchy,
+        .flags                  = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
+#ifdef CONFIG_SMP
+        .irq_set_affinity       = irq_chip_set_affinity_parent,
+#endif
+};
+static int wakeupgen_domain_xlate(struct irq_domain *domain,
+                                  struct device_node *controller,
+                                  const u32 *intspec,
+                                  unsigned int intsize,
+                                  unsigned long *out_hwirq,
+                                  unsigned int *out_type)
+{
+        if (domain->of_node != controller)
+                return -EINVAL; /* Shouldn't happen, really... */
+        if (intsize != 3)
+                return -EINVAL; /* Not GIC compliant */
+        if (intspec[0] != 0)
+                return -EINVAL; /* No PPI should point to this domain */
+        *out_hwirq = intspec[1];
+        *out_type = intspec[2];
+        return 0;
+}
+static int wakeupgen_domain_alloc(struct irq_domain *domain,
+                                  unsigned int virq,
+                                  unsigned int nr_irqs, void *data)
+{
+        struct of_phandle_args *args = data;
+        struct of_phandle_args parent_args;
+        irq_hw_number_t hwirq;
+        int i;
+        if (args->args_count != 3)
+                return -EINVAL; /* Not GIC compliant */
+        if (args->args[0] != 0)
+                return -EINVAL; /* No PPI should point to this domain */
+        hwirq = args->args[1];
+        if (hwirq >= MAX_IRQS)
+                return -EINVAL; /* Can't deal with this */
+        for (i = 0; i < nr_irqs; i++)
+                irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
+                                              &wakeupgen_chip, NULL);
+        parent_args = *args;
+        parent_args.np = domain->parent->of_node;
+        return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &parent_args);
+}
+static struct irq_domain_ops wakeupgen_domain_ops = {
+        .xlate  = wakeupgen_domain_xlate,
+        .alloc  = wakeupgen_domain_alloc,
+        .free   = irq_domain_free_irqs_common,
+};
 /*
 * Initialise the wakeupgen module.
 */
-int __init omap_wakeupgen_init(void)
+static int __init wakeupgen_init(struct device_node *node,
+                                 struct device_node *parent)
 {
+        struct irq_domain *parent_domain, *domain;
        int i;
        unsigned int boot_cpu = smp_processor_id();
        u32 val;
+        if (!parent) {
+                pr_err("%s: no parent, giving up\n", node->full_name);
+                return -ENODEV;
+        }
+        parent_domain = irq_find_host(parent);
+        if (!parent_domain) {
+                pr_err("%s: unable to obtain parent domain\n", node->full_name);
+                return -ENXIO;
+        }
        /* Not supported on OMAP4 ES1.0 silicon */
        if (omap_rev() == OMAP4430_REV_ES1_0) {
                WARN(1, "WakeupGen: Not supported on OMAP4430 ES1.0\n");
@@ -416,7 +478,7 @@ int __init omap_wakeupgen_init(void)
        }
        /* Static mapping, never released */
-        wakeupgen_base = ioremap(OMAP_WKUPGEN_BASE, SZ_4K);
+        wakeupgen_base = of_iomap(node, 0);
        if (WARN_ON(!wakeupgen_base))
                return -ENOMEM;
@@ -429,6 +491,14 @@ int __init omap_wakeupgen_init(void)
                max_irqs = AM43XX_IRQS;
        }
+        domain = irq_domain_add_hierarchy(parent_domain, 0, max_irqs,
+                                          node, &wakeupgen_domain_ops,
+                                          NULL);
+        if (!domain) {
+                iounmap(wakeupgen_base);
+                return -ENOMEM;
+        }
        /* Clear all IRQ bitmasks at wakeupGen level */
        for (i = 0; i < irq_banks; i++) {
                wakeupgen_writel(0, i, CPU0_ID);
@@ -437,14 +507,6 @@ int __init omap_wakeupgen_init(void)
        }
        /*
-         * Override GIC architecture specific functions to add
-         * OMAP WakeupGen interrupt controller along with GIC
-         */
-        gic_arch_extn.irq_mask = wakeupgen_mask;
-        gic_arch_extn.irq_unmask = wakeupgen_unmask;
-        gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE;
-        /*
         * FIXME: Add support to set_smp_affinity() once the core
         * GIC code has necessary hooks in place.
         */
@@ -474,3 +536,9 @@ int __init omap_wakeupgen_init(void)
        return 0;
 }
+/*
+ * We cannot use the IRQCHIP_DECLARE macro that lives in
+ * drivers/irqchip, so we're forced to roll our own. Not very nice.
+ */
+OF_DECLARE_2(irqchip, ti_wakeupgen, "ti,omap4-wugen-mpu", wakeupgen_init);
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.h b/arch/arm/mach-omap2/omap-wakeupgen.h
index b3c8eccfae79..a3491ad12368 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.h
+++ b/arch/arm/mach-omap2/omap-wakeupgen.h
@@ -33,7 +33,6 @@
 #define OMAP_TIMESTAMPCYCLELO                   0xc08
 #define OMAP_TIMESTAMPCYCLEHI                   0xc0c
-extern int __init omap_wakeupgen_init(void);
 extern void __iomem *omap_get_wakeupgen_base(void);
 extern int omap_secure_apis_support(void);
 #endif
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index cf7aafb27fd1..7bb116a6f86f 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -241,26 +241,26 @@ static int __init omap4_sar_ram_init(void)
 }
 omap_early_initcall(omap4_sar_ram_init);
-static const struct of_device_id gic_match[] = {
+static const struct of_device_id intc_match[] = {
-        { .compatible = "arm,cortex-a9-gic", },
+        { .compatible = "ti,omap4-wugen-mpu", },
-        { .compatible = "arm,cortex-a15-gic", },
+        { .compatible = "ti,omap5-wugen-mpu", },
        { },
 };
-static struct device_node *gic_node;
+static struct device_node *intc_node;
 unsigned int omap4_xlate_irq(unsigned int hwirq)
 {
        struct of_phandle_args irq_data;
        unsigned int irq;
-        if (!gic_node)
+        if (!intc_node)
-                gic_node = of_find_matching_node(NULL, gic_match);
+                intc_node = of_find_matching_node(NULL, intc_match);
-        if (WARN_ON(!gic_node))
+        if (WARN_ON(!intc_node))
                return hwirq;
-        irq_data.np = gic_node;
+        irq_data.np = intc_node;
        irq_data.args_count = 3;
        irq_data.args[0] = 0;
        irq_data.args[1] = hwirq - OMAP44XX_IRQ_GIC_START;
@@ -277,6 +277,12 @@ void __init omap_gic_of_init(void)
 {
        struct device_node *np;
+        intc_node = of_find_matching_node(NULL, intc_match);
+        if (WARN_ON(!intc_node)) {
+                pr_err("No WUGEN found in DT, system will misbehave.\n");
+                pr_err("UPDATE YOUR DEVICE TREE!\n");
+        }
        /* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
        if (!cpu_is_omap446x())
                goto skip_errata_init;
@@ -290,6 +296,5 @@ void __init omap_gic_of_init(void)
        WARN_ON(!twd_base);
 skip_errata_init:
-        omap_wakeupgen_init();
        irqchip_init();
 }