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-rw-r--r--arch/arm/boot/dts/r8a7791.dtsi41
-rw-r--r--arch/arm/mach-shmobile/Kconfig6
-rw-r--r--arch/arm/mach-shmobile/Makefile2
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7778.c44
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7779.c2
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7790.c12
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7791.c237
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7778.h2
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7791.h8
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7778.c37
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7791.c149
11 files changed, 525 insertions, 15 deletions
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
new file mode 100644
index 000000000000..bbed43bd9be9
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -0,0 +1,41 @@
1/*
2 * Device Tree Source for the r8a7791 SoC
3 *
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013 Renesas Solutions Corp.
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12/ {
13 compatible = "renesas,r8a7791";
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 cpu0: cpu@0 {
23 device_type = "cpu";
24 compatible = "arm,cortex-a15";
25 reg = <0>;
26 clock-frequency = <1300000000>;
27 };
28 };
29
30 gic: interrupt-controller@f1001000 {
31 compatible = "arm,cortex-a15-gic";
32 #interrupt-cells = <3>;
33 #address-cells = <0>;
34 interrupt-controller;
35 reg = <0 0xf1001000 0 0x1000>,
36 <0 0xf1002000 0 0x1000>,
37 <0 0xf1004000 0 0x2000>,
38 <0 0xf1006000 0 0x2000>;
39 interrupts = <1 9 0xf04>;
40 };
41};
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 1f94c310c477..b45240512ce0 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -101,6 +101,12 @@ config ARCH_R8A7790
101 select SH_CLK_CPG 101 select SH_CLK_CPG
102 select RENESAS_IRQC 102 select RENESAS_IRQC
103 103
104config ARCH_R8A7791
105 bool "R-Car M2 (R8A77910)"
106 select ARM_GIC
107 select CPU_V7
108 select SH_CLK_CPG
109
104config ARCH_EMEV2 110config ARCH_EMEV2
105 bool "Emma Mobile EV2" 111 bool "Emma Mobile EV2"
106 select ARCH_WANT_OPTIONAL_GPIOLIB 112 select ARCH_WANT_OPTIONAL_GPIOLIB
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 2705bfa8c113..228193cc9a38 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o
15obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o 15obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o
16obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o 16obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o
17obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o 17obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o
18obj-$(CONFIG_ARCH_R8A7791) += setup-r8a7791.o
18obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o 19obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o
19 20
20# Clock objects 21# Clock objects
@@ -27,6 +28,7 @@ obj-$(CONFIG_ARCH_R8A7740) += clock-r8a7740.o
27obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o 28obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o
28obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o 29obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o
29obj-$(CONFIG_ARCH_R8A7790) += clock-r8a7790.o 30obj-$(CONFIG_ARCH_R8A7790) += clock-r8a7790.o
31obj-$(CONFIG_ARCH_R8A7791) += clock-r8a7791.o
30obj-$(CONFIG_ARCH_EMEV2) += clock-emev2.o 32obj-$(CONFIG_ARCH_EMEV2) += clock-emev2.o
31endif 33endif
32 34
diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c
index c4bf2d8fb111..fb6af83858e3 100644
--- a/arch/arm/mach-shmobile/clock-r8a7778.c
+++ b/arch/arm/mach-shmobile/clock-r8a7778.c
@@ -69,6 +69,15 @@ static struct clk extal_clk = {
69 .mapping = &cpg_mapping, 69 .mapping = &cpg_mapping,
70}; 70};
71 71
72static struct clk audio_clk_a = {
73};
74
75static struct clk audio_clk_b = {
76};
77
78static struct clk audio_clk_c = {
79};
80
72/* 81/*
73 * clock ratio of these clock will be updated 82 * clock ratio of these clock will be updated
74 * on r8a7778_clock_init() 83 * on r8a7778_clock_init()
@@ -100,18 +109,23 @@ static struct clk *main_clks[] = {
100 &p_clk, 109 &p_clk,
101 &g_clk, 110 &g_clk,
102 &z_clk, 111 &z_clk,
112 &audio_clk_a,
113 &audio_clk_b,
114 &audio_clk_c,
103}; 115};
104 116
105enum { 117enum {
106 MSTP331, 118 MSTP331,
107 MSTP323, MSTP322, MSTP321, 119 MSTP323, MSTP322, MSTP321,
120 MSTP311, MSTP310,
121 MSTP309, MSTP308, MSTP307,
108 MSTP114, 122 MSTP114,
109 MSTP110, MSTP109, 123 MSTP110, MSTP109,
110 MSTP100, 124 MSTP100,
111 MSTP030, 125 MSTP030,
112 MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, 126 MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
113 MSTP016, MSTP015, 127 MSTP016, MSTP015, MSTP012, MSTP011, MSTP010,
114 MSTP007, 128 MSTP009, MSTP008, MSTP007,
115 MSTP_NR }; 129 MSTP_NR };
116 130
117static struct clk mstp_clks[MSTP_NR] = { 131static struct clk mstp_clks[MSTP_NR] = {
@@ -119,6 +133,11 @@ static struct clk mstp_clks[MSTP_NR] = {
119 [MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */ 133 [MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */
120 [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */ 134 [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */
121 [MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */ 135 [MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */
136 [MSTP311] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 11, 0), /* SSI4 */
137 [MSTP310] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 10, 0), /* SSI5 */
138 [MSTP309] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 9, 0), /* SSI6 */
139 [MSTP308] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 8, 0), /* SSI7 */
140 [MSTP307] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 7, 0), /* SSI8 */
122 [MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */ 141 [MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */
123 [MSTP110] = SH_CLK_MSTP32(&s_clk, MSTPCR1, 10, 0), /* VIN0 */ 142 [MSTP110] = SH_CLK_MSTP32(&s_clk, MSTPCR1, 10, 0), /* VIN0 */
124 [MSTP109] = SH_CLK_MSTP32(&s_clk, MSTPCR1, 9, 0), /* VIN1 */ 143 [MSTP109] = SH_CLK_MSTP32(&s_clk, MSTPCR1, 9, 0), /* VIN1 */
@@ -135,11 +154,20 @@ static struct clk mstp_clks[MSTP_NR] = {
135 [MSTP021] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 21, 0), /* SCIF5 */ 154 [MSTP021] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 21, 0), /* SCIF5 */
136 [MSTP016] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 16, 0), /* TMU0 */ 155 [MSTP016] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 16, 0), /* TMU0 */
137 [MSTP015] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 15, 0), /* TMU1 */ 156 [MSTP015] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 15, 0), /* TMU1 */
157 [MSTP012] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 12, 0), /* SSI0 */
158 [MSTP011] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 11, 0), /* SSI1 */
159 [MSTP010] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 10, 0), /* SSI2 */
160 [MSTP009] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 9, 0), /* SSI3 */
161 [MSTP008] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 8, 0), /* SRU */
138 [MSTP007] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 7, 0), /* HSPI */ 162 [MSTP007] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 7, 0), /* HSPI */
139}; 163};
140 164
141static struct clk_lookup lookups[] = { 165static struct clk_lookup lookups[] = {
142 /* main */ 166 /* main */
167 CLKDEV_CON_ID("audio_clk_a", &audio_clk_a),
168 CLKDEV_CON_ID("audio_clk_b", &audio_clk_b),
169 CLKDEV_CON_ID("audio_clk_c", &audio_clk_c),
170 CLKDEV_CON_ID("audio_clk_internal", &s1_clk),
143 CLKDEV_CON_ID("shyway_clk", &s_clk), 171 CLKDEV_CON_ID("shyway_clk", &s_clk),
144 CLKDEV_CON_ID("peripheral_clk", &p_clk), 172 CLKDEV_CON_ID("peripheral_clk", &p_clk),
145 173
@@ -153,6 +181,7 @@ static struct clk_lookup lookups[] = {
153 CLKDEV_DEV_ID("r8a7778-vin.1", &mstp_clks[MSTP109]), /* VIN1 */ 181 CLKDEV_DEV_ID("r8a7778-vin.1", &mstp_clks[MSTP109]), /* VIN1 */
154 CLKDEV_DEV_ID("ehci-platform", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */ 182 CLKDEV_DEV_ID("ehci-platform", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
155 CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */ 183 CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */
184 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP100]), /* USB FUNC */
156 CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */ 185 CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */
157 CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */ 186 CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */
158 CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */ 187 CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */
@@ -168,6 +197,17 @@ static struct clk_lookup lookups[] = {
168 CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */ 197 CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */
169 CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */ 198 CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */
170 CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */ 199 CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */
200 CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP008]), /* SRU */
201
202 CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP012]),
203 CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP011]),
204 CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP010]),
205 CLKDEV_ICK_ID("ssi.3", "rcar_sound", &mstp_clks[MSTP009]),
206 CLKDEV_ICK_ID("ssi.4", "rcar_sound", &mstp_clks[MSTP311]),
207 CLKDEV_ICK_ID("ssi.5", "rcar_sound", &mstp_clks[MSTP310]),
208 CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP309]),
209 CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP308]),
210 CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP307]),
171}; 211};
172 212
173void __init r8a7778_clock_init(void) 213void __init r8a7778_clock_init(void)
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index bd6ad922eb7e..1f7080fab0a5 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -200,7 +200,7 @@ static struct clk_lookup lookups[] = {
200 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ 200 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
201 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ 201 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
202 CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */ 202 CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */
203 CLKDEV_DEV_ID("rcar-du.0", &mstp_clks[MSTP103]), /* DU */ 203 CLKDEV_DEV_ID("rcar-du-r8a7779", &mstp_clks[MSTP103]), /* DU */
204}; 204};
205 205
206void __init r8a7779_clock_init(void) 206void __init r8a7779_clock_init(void)
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index fc36d3db0b4d..d99b87bc76ea 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -182,7 +182,7 @@ static struct clk div6_clks[DIV6_NR] = {
182/* MSTP */ 182/* MSTP */
183enum { 183enum {
184 MSTP813, 184 MSTP813,
185 MSTP721, MSTP720, 185 MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
186 MSTP717, MSTP716, 186 MSTP717, MSTP716,
187 MSTP522, 187 MSTP522,
188 MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304, 188 MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
@@ -193,6 +193,11 @@ enum {
193 193
194static struct clk mstp_clks[MSTP_NR] = { 194static struct clk mstp_clks[MSTP_NR] = {
195 [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */ 195 [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
196 [MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */
197 [MSTP725] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 25, 0), /* LVDS1 */
198 [MSTP724] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 24, 0), /* DU0 */
199 [MSTP723] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 23, 0), /* DU1 */
200 [MSTP722] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 22, 0), /* DU2 */
196 [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ 201 [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
197 [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ 202 [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
198 [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */ 203 [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */
@@ -251,6 +256,11 @@ static struct clk_lookup lookups[] = {
251 CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]), 256 CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]),
252 257
253 /* MSTP */ 258 /* MSTP */
259 CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]),
260 CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]),
261 CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]),
262 CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]),
263 CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]),
254 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), 264 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
255 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), 265 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
256 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), 266 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c
new file mode 100644
index 000000000000..c9a26f16ce5b
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-r8a7791.c
@@ -0,0 +1,237 @@
1/*
2 * r8a7791 clock framework support
3 *
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013 Renesas Solutions Corp.
6 * Copyright (C) 2013 Magnus Damm
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21#include <linux/init.h>
22#include <linux/io.h>
23#include <linux/kernel.h>
24#include <linux/sh_clk.h>
25#include <linux/clkdev.h>
26#include <mach/clock.h>
27#include <mach/common.h>
28
29/*
30 * MD EXTAL PLL0 PLL1 PLL3
31 * 14 13 19 (MHz) *1 *1
32 *---------------------------------------------------
33 * 0 0 0 15 x 1 x172/2 x208/2 x106
34 * 0 0 1 15 x 1 x172/2 x208/2 x88
35 * 0 1 0 20 x 1 x130/2 x156/2 x80
36 * 0 1 1 20 x 1 x130/2 x156/2 x66
37 * 1 0 0 26 / 2 x200/2 x240/2 x122
38 * 1 0 1 26 / 2 x200/2 x240/2 x102
39 * 1 1 0 30 / 2 x172/2 x208/2 x106
40 * 1 1 1 30 / 2 x172/2 x208/2 x88
41 *
42 * *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
43 * see "p1 / 2" on R8A7791_CLOCK_ROOT() below
44 */
45
46#define MD(nr) (1 << nr)
47
48#define CPG_BASE 0xe6150000
49#define CPG_LEN 0x1000
50
51#define SMSTPCR0 0xE6150130
52#define SMSTPCR1 0xE6150134
53#define SMSTPCR2 0xe6150138
54#define SMSTPCR3 0xE615013C
55#define SMSTPCR5 0xE6150144
56#define SMSTPCR7 0xe615014c
57#define SMSTPCR8 0xE6150990
58#define SMSTPCR9 0xE6150994
59#define SMSTPCR10 0xE6150998
60#define SMSTPCR11 0xE615099C
61
62#define MODEMR 0xE6160060
63#define SDCKCR 0xE6150074
64#define SD2CKCR 0xE6150078
65#define SD3CKCR 0xE615007C
66#define MMC0CKCR 0xE6150240
67#define MMC1CKCR 0xE6150244
68#define SSPCKCR 0xE6150248
69#define SSPRSCKCR 0xE615024C
70
71static struct clk_mapping cpg_mapping = {
72 .phys = CPG_BASE,
73 .len = CPG_LEN,
74};
75
76static struct clk extal_clk = {
77 /* .rate will be updated on r8a7791_clock_init() */
78 .mapping = &cpg_mapping,
79};
80
81static struct sh_clk_ops followparent_clk_ops = {
82 .recalc = followparent_recalc,
83};
84
85static struct clk main_clk = {
86 /* .parent will be set r8a73a4_clock_init */
87 .ops = &followparent_clk_ops,
88};
89
90/*
91 * clock ratio of these clock will be updated
92 * on r8a7791_clock_init()
93 */
94SH_FIXED_RATIO_CLK_SET(pll1_clk, main_clk, 1, 1);
95SH_FIXED_RATIO_CLK_SET(pll3_clk, main_clk, 1, 1);
96
97/* fixed ratio clock */
98SH_FIXED_RATIO_CLK_SET(extal_div2_clk, extal_clk, 1, 2);
99SH_FIXED_RATIO_CLK_SET(cp_clk, extal_clk, 1, 2);
100
101SH_FIXED_RATIO_CLK_SET(pll1_div2_clk, pll1_clk, 1, 2);
102SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12);
103SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24);
104SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024));
105SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15);
106
107static struct clk *main_clks[] = {
108 &extal_clk,
109 &extal_div2_clk,
110 &main_clk,
111 &pll1_clk,
112 &pll1_div2_clk,
113 &pll3_clk,
114 &hp_clk,
115 &p_clk,
116 &rclk_clk,
117 &mp_clk,
118 &cp_clk,
119};
120
121/* MSTP */
122enum {
123 MSTP721, MSTP720,
124 MSTP719, MSTP718, MSTP715, MSTP714,
125 MSTP216, MSTP207, MSTP206,
126 MSTP204, MSTP203, MSTP202, MSTP1105, MSTP1106, MSTP1107,
127 MSTP124,
128 MSTP_NR
129};
130
131static struct clk mstp_clks[MSTP_NR] = {
132 [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
133 [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
134 [MSTP719] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 19, 0), /* SCIF2 */
135 [MSTP718] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 18, 0), /* SCIF3 */
136 [MSTP715] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 15, 0), /* SCIF4 */
137 [MSTP714] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 14, 0), /* SCIF5 */
138 [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
139 [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
140 [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
141 [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
142 [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
143 [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
144 [MSTP1105] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 5, 0), /* SCIFA3 */
145 [MSTP1106] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 6, 0), /* SCIFA4 */
146 [MSTP1107] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 7, 0), /* SCIFA5 */
147 [MSTP124] = SH_CLK_MSTP32(&rclk_clk, SMSTPCR1, 24, 0), /* CMT0 */
148};
149
150static struct clk_lookup lookups[] = {
151
152 /* main clocks */
153 CLKDEV_CON_ID("extal", &extal_clk),
154 CLKDEV_CON_ID("extal_div2", &extal_div2_clk),
155 CLKDEV_CON_ID("main", &main_clk),
156 CLKDEV_CON_ID("pll1", &pll1_clk),
157 CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk),
158 CLKDEV_CON_ID("pll3", &pll3_clk),
159 CLKDEV_CON_ID("hp", &hp_clk),
160 CLKDEV_CON_ID("p", &p_clk),
161 CLKDEV_CON_ID("rclk", &rclk_clk),
162 CLKDEV_CON_ID("mp", &mp_clk),
163 CLKDEV_CON_ID("cp", &cp_clk),
164 CLKDEV_CON_ID("peripheral_clk", &hp_clk),
165
166 /* MSTP */
167 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
168 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
169 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), /* SCIFB0 */
170 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]), /* SCIFB1 */
171 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), /* SCIFB2 */
172 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]), /* SCIFA2 */
173 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]), /* SCIF0 */
174 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), /* SCIF1 */
175 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP719]), /* SCIF2 */
176 CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP718]), /* SCIF3 */
177 CLKDEV_DEV_ID("sh-sci.10", &mstp_clks[MSTP715]), /* SCIF4 */
178 CLKDEV_DEV_ID("sh-sci.11", &mstp_clks[MSTP714]), /* SCIF5 */
179 CLKDEV_DEV_ID("sh-sci.12", &mstp_clks[MSTP1105]), /* SCIFA3 */
180 CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */
181 CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */
182 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
183};
184
185#define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
186 extal_clk.rate = e * 1000 * 1000; \
187 main_clk.parent = m; \
188 SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1); \
189 if (mode & MD(19)) \
190 SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1); \
191 else \
192 SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)
193
194
195void __init r8a7791_clock_init(void)
196{
197 void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
198 u32 mode;
199 int k, ret = 0;
200
201 BUG_ON(!modemr);
202 mode = ioread32(modemr);
203 iounmap(modemr);
204
205 switch (mode & (MD(14) | MD(13))) {
206 case 0:
207 R8A7791_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
208 break;
209 case MD(13):
210 R8A7791_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
211 break;
212 case MD(14):
213 R8A7791_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102);
214 break;
215 case MD(13) | MD(14):
216 R8A7791_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88);
217 break;
218 }
219
220 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
221 ret = clk_register(main_clks[k]);
222
223 if (!ret)
224 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
225
226 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
227
228 if (!ret)
229 shmobile_clk_init();
230 else
231 goto epanic;
232
233 return;
234
235epanic:
236 panic("failed to setup r8a7791 clocks\n");
237}
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h
index adfcf51b163d..ea1dca6880f4 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h
@@ -35,4 +35,6 @@ extern void r8a7778_clock_init(void);
35extern void r8a7778_init_irq_extpin(int irlm); 35extern void r8a7778_init_irq_extpin(int irlm);
36extern void r8a7778_pinmux_init(void); 36extern void r8a7778_pinmux_init(void);
37 37
38extern int r8a7778_usb_phy_power(bool enable);
39
38#endif /* __ASM_R8A7778_H__ */ 40#endif /* __ASM_R8A7778_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7791.h b/arch/arm/mach-shmobile/include/mach/r8a7791.h
new file mode 100644
index 000000000000..2e6d66131083
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/r8a7791.h
@@ -0,0 +1,8 @@
1#ifndef __ASM_R8A7791_H__
2#define __ASM_R8A7791_H__
3
4void r8a7791_add_dt_devices(void);
5void r8a7791_clock_init(void);
6void r8a7791_init_early(void);
7
8#endif /* __ASM_R8A7791_H__ */
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index 6a2657ebd197..e484d1420a01 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -95,29 +95,46 @@ static struct sh_timer_config sh_tmu1_platform_data __initdata = {
95 &sh_tmu##idx##_platform_data, \ 95 &sh_tmu##idx##_platform_data, \
96 sizeof(sh_tmu##idx##_platform_data)) 96 sizeof(sh_tmu##idx##_platform_data))
97 97
98/* USB */ 98int r8a7778_usb_phy_power(bool enable)
99static struct usb_phy *phy; 99{
100 static struct usb_phy *phy = NULL;
101 int ret = 0;
102
103 if (!phy)
104 phy = usb_get_phy(USB_PHY_TYPE_USB2);
105
106 if (IS_ERR(phy)) {
107 pr_err("kernel doesn't have usb phy driver\n");
108 return PTR_ERR(phy);
109 }
110
111 if (enable)
112 ret = usb_phy_init(phy);
113 else
114 usb_phy_shutdown(phy);
100 115
116 return ret;
117}
118
119/* USB */
101static int usb_power_on(struct platform_device *pdev) 120static int usb_power_on(struct platform_device *pdev)
102{ 121{
103 if (IS_ERR(phy)) 122 int ret = r8a7778_usb_phy_power(true);
104 return PTR_ERR(phy); 123
124 if (ret)
125 return ret;
105 126
106 pm_runtime_enable(&pdev->dev); 127 pm_runtime_enable(&pdev->dev);
107 pm_runtime_get_sync(&pdev->dev); 128 pm_runtime_get_sync(&pdev->dev);
108 129
109 usb_phy_init(phy);
110
111 return 0; 130 return 0;
112} 131}
113 132
114static void usb_power_off(struct platform_device *pdev) 133static void usb_power_off(struct platform_device *pdev)
115{ 134{
116 if (IS_ERR(phy)) 135 if (r8a7778_usb_phy_power(false))
117 return; 136 return;
118 137
119 usb_phy_shutdown(phy);
120
121 pm_runtime_put_sync(&pdev->dev); 138 pm_runtime_put_sync(&pdev->dev);
122 pm_runtime_disable(&pdev->dev); 139 pm_runtime_disable(&pdev->dev);
123} 140}
@@ -353,8 +370,6 @@ void __init r8a7778_add_standard_devices(void)
353 370
354void __init r8a7778_init_late(void) 371void __init r8a7778_init_late(void)
355{ 372{
356 phy = usb_get_phy(USB_PHY_TYPE_USB2);
357
358 platform_device_register_full(&ehci_info); 373 platform_device_register_full(&ehci_info);
359 platform_device_register_full(&ohci_info); 374 platform_device_register_full(&ohci_info);
360} 375}
diff --git a/arch/arm/mach-shmobile/setup-r8a7791.c b/arch/arm/mach-shmobile/setup-r8a7791.c
new file mode 100644
index 000000000000..b56399d2e1de
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-r8a7791.c
@@ -0,0 +1,149 @@
1/*
2 * r8a7791 processor support
3 *
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013 Renesas Solutions Corp.
6 * Copyright (C) 2013 Magnus Damm
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22#include <linux/irq.h>
23#include <linux/kernel.h>
24#include <linux/of_platform.h>
25#include <linux/serial_sci.h>
26#include <linux/sh_timer.h>
27#include <mach/common.h>
28#include <mach/irqs.h>
29#include <mach/r8a7791.h>
30#include <asm/mach/arch.h>
31
32#define SCIF_COMMON(scif_type, baseaddr, irq) \
33 .type = scif_type, \
34 .mapbase = baseaddr, \
35 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
36 .irqs = SCIx_IRQ_MUXED(irq)
37
38#define SCIFA_DATA(index, baseaddr, irq) \
39[index] = { \
40 SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
41 .scbrr_algo_id = SCBRR_ALGO_4, \
42 .scscr = SCSCR_RE | SCSCR_TE, \
43}
44
45#define SCIFB_DATA(index, baseaddr, irq) \
46[index] = { \
47 SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
48 .scbrr_algo_id = SCBRR_ALGO_4, \
49 .scscr = SCSCR_RE | SCSCR_TE, \
50}
51
52#define SCIF_DATA(index, baseaddr, irq) \
53[index] = { \
54 SCIF_COMMON(PORT_SCIF, baseaddr, irq), \
55 .scbrr_algo_id = SCBRR_ALGO_2, \
56 .scscr = SCSCR_RE | SCSCR_TE, \
57}
58
59#define HSCIF_DATA(index, baseaddr, irq) \
60[index] = { \
61 SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \
62 .scbrr_algo_id = SCBRR_ALGO_6, \
63 .scscr = SCSCR_RE | SCSCR_TE, \
64}
65
66enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1,
67 SCIF2, SCIF3, SCIF4, SCIF5, SCIFA3, SCIFA4, SCIFA5 };
68
69static const struct plat_sci_port scif[] __initconst = {
70 SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
71 SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
72 SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
73 SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
74 SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
75 SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
76 SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */
77 SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */
78 SCIF_DATA(SCIF2, 0xe6e58000, gic_spi(22)), /* SCIF2 */
79 SCIF_DATA(SCIF3, 0xe6ea8000, gic_spi(23)), /* SCIF3 */
80 SCIF_DATA(SCIF4, 0xe6ee0000, gic_spi(24)), /* SCIF4 */
81 SCIF_DATA(SCIF5, 0xe6ee8000, gic_spi(25)), /* SCIF5 */
82 SCIFA_DATA(SCIFA3, 0xe6c70000, gic_spi(29)), /* SCIFA3 */
83 SCIFA_DATA(SCIFA4, 0xe6c78000, gic_spi(30)), /* SCIFA4 */
84 SCIFA_DATA(SCIFA5, 0xe6c80000, gic_spi(31)), /* SCIFA5 */
85};
86
87static inline void r8a7791_register_scif(int idx)
88{
89 platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
90 sizeof(struct plat_sci_port));
91}
92
93static const struct sh_timer_config cmt00_platform_data __initconst = {
94 .name = "CMT00",
95 .timer_bit = 0,
96 .clockevent_rating = 80,
97};
98
99static const struct resource cmt00_resources[] __initconst = {
100 DEFINE_RES_MEM(0xffca0510, 0x0c),
101 DEFINE_RES_MEM(0xffca0500, 0x04),
102 DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */
103};
104
105#define r8a7791_register_cmt(idx) \
106 platform_device_register_resndata(&platform_bus, "sh_cmt", \
107 idx, cmt##idx##_resources, \
108 ARRAY_SIZE(cmt##idx##_resources), \
109 &cmt##idx##_platform_data, \
110 sizeof(struct sh_timer_config))
111
112void __init r8a7791_add_dt_devices(void)
113{
114 r8a7791_register_scif(SCIFA0);
115 r8a7791_register_scif(SCIFA1);
116 r8a7791_register_scif(SCIFB0);
117 r8a7791_register_scif(SCIFB1);
118 r8a7791_register_scif(SCIFB2);
119 r8a7791_register_scif(SCIFA2);
120 r8a7791_register_scif(SCIF0);
121 r8a7791_register_scif(SCIF1);
122 r8a7791_register_scif(SCIF2);
123 r8a7791_register_scif(SCIF3);
124 r8a7791_register_scif(SCIF4);
125 r8a7791_register_scif(SCIF5);
126 r8a7791_register_scif(SCIFA3);
127 r8a7791_register_scif(SCIFA4);
128 r8a7791_register_scif(SCIFA5);
129 r8a7791_register_cmt(00);
130}
131
132void __init r8a7791_init_early(void)
133{
134#ifndef CONFIG_ARM_ARCH_TIMER
135 shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */
136#endif
137}
138
139#ifdef CONFIG_USE_OF
140static const char *r8a7791_boards_compat_dt[] __initdata = {
141 "renesas,r8a7791",
142 NULL,
143};
144
145DT_MACHINE_START(R8A7791_DT, "Generic R8A7791 (Flattened Device Tree)")
146 .init_early = r8a7791_init_early,
147 .dt_compat = r8a7791_boards_compat_dt,
148MACHINE_END
149#endif /* CONFIG_USE_OF */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-15 21:00:05 -0400