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-rw-r--r--arch/powerpc/boot/dts/mpc8308_p1m.dts332
-rw-r--r--arch/powerpc/boot/dts/p1022ds.dts11
-rw-r--r--arch/powerpc/configs/e55xx_smp_defconfig84
-rw-r--r--arch/powerpc/configs/ppc64e_defconfig4
-rw-r--r--arch/powerpc/include/asm/fsl_85xx_cache_sram.h48
-rw-r--r--arch/powerpc/include/asm/kexec.h1
-rw-r--r--arch/powerpc/include/asm/mmu-book3e.h15
-rw-r--r--arch/powerpc/include/asm/pte-common.h7
-rw-r--r--arch/powerpc/kernel/Makefile4
-rw-r--r--arch/powerpc/kernel/asm-offsets.c4
-rw-r--r--arch/powerpc/kernel/cpu_setup_fsl_booke.S15
-rw-r--r--arch/powerpc/kernel/cputable.c28
-rw-r--r--arch/powerpc/kernel/crash.c13
-rw-r--r--arch/powerpc/kernel/head_fsl_booke.S10
-rw-r--r--arch/powerpc/kernel/machine_kexec.c24
-rw-r--r--arch/powerpc/kernel/machine_kexec_32.c4
-rw-r--r--arch/powerpc/kernel/paca.c2
-rw-r--r--arch/powerpc/kernel/setup_32.c2
-rw-r--r--arch/powerpc/kernel/time.c3
-rw-r--r--arch/powerpc/kernel/traps.c5
-rw-r--r--arch/powerpc/mm/Makefile2
-rw-r--r--arch/powerpc/mm/fsl_booke_mmu.c15
-rw-r--r--arch/powerpc/mm/mmu_decl.h5
-rw-r--r--arch/powerpc/mm/tlb_nohash.c56
-rw-r--r--arch/powerpc/mm/tlb_nohash_low.S2
-rw-r--r--arch/powerpc/oprofile/op_model_fsl_emb.c15
-rw-r--r--arch/powerpc/platforms/83xx/Kconfig4
-rw-r--r--arch/powerpc/platforms/83xx/mpc830x_rdb.c3
-rw-r--r--arch/powerpc/platforms/85xx/Kconfig28
-rw-r--r--arch/powerpc/platforms/85xx/Makefile2
-rw-r--r--arch/powerpc/platforms/85xx/p1022_ds.c2
-rw-r--r--arch/powerpc/platforms/85xx/p3041_ds.c64
-rw-r--r--arch/powerpc/platforms/85xx/p5020_ds.c69
-rw-r--r--arch/powerpc/platforms/85xx/smp.c76
-rw-r--r--arch/powerpc/platforms/Kconfig.cputype8
-rw-r--r--arch/powerpc/sysdev/Makefile1
-rw-r--r--arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h101
-rw-r--r--arch/powerpc/sysdev/fsl_85xx_cache_sram.c159
-rw-r--r--arch/powerpc/sysdev/fsl_85xx_l2ctlr.c231
-rw-r--r--arch/powerpc/sysdev/fsl_msi.c9
-rw-r--r--arch/powerpc/sysdev/fsl_pci.c60
-rw-r--r--arch/powerpc/sysdev/fsl_pci.h1
-rw-r--r--arch/powerpc/sysdev/fsl_rio.c65
-rw-r--r--arch/powerpc/sysdev/fsl_soc.c20
-rw-r--r--arch/powerpc/sysdev/mpc8xxx_gpio.c3
-rw-r--r--drivers/watchdog/Kconfig22
-rw-r--r--drivers/watchdog/booke_wdt.c47
-rw-r--r--include/linux/pci_ids.h8
48 files changed, 1582 insertions, 112 deletions
diff --git a/arch/powerpc/boot/dts/mpc8308_p1m.dts b/arch/powerpc/boot/dts/mpc8308_p1m.dts
new file mode 100644
index 000000000000..05a76ccfd499
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8308_p1m.dts
@@ -0,0 +1,332 @@
1/*
2 * mpc8308_p1m Device Tree Source
3 *
4 * Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 compatible = "denx,mpc8308_p1m";
16 #address-cells = <1>;
17 #size-cells = <1>;
18
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 serial0 = &serial0;
23 serial1 = &serial1;
24 pci0 = &pci0;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 PowerPC,8308@0 {
32 device_type = "cpu";
33 reg = <0x0>;
34 d-cache-line-size = <32>;
35 i-cache-line-size = <32>;
36 d-cache-size = <16384>;
37 i-cache-size = <16384>;
38 timebase-frequency = <0>; // from bootloader
39 bus-frequency = <0>; // from bootloader
40 clock-frequency = <0>; // from bootloader
41 };
42 };
43
44 memory {
45 device_type = "memory";
46 reg = <0x00000000 0x08000000>; // 128MB at 0
47 };
48
49 localbus@e0005000 {
50 #address-cells = <2>;
51 #size-cells = <1>;
52 compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
53 reg = <0xe0005000 0x1000>;
54 interrupts = <77 0x8>;
55 interrupt-parent = <&ipic>;
56
57 ranges = <0x0 0x0 0xfc000000 0x04000000
58 0x1 0x0 0xfbff0000 0x00008000
59 0x2 0x0 0xfbff8000 0x00008000>;
60
61 flash@0,0 {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "cfi-flash";
65 reg = <0x0 0x0 0x4000000>;
66 bank-width = <2>;
67 device-width = <1>;
68
69 u-boot@0 {
70 reg = <0x0 0x60000>;
71 read-only;
72 };
73 env@60000 {
74 reg = <0x60000 0x20000>;
75 };
76 env1@80000 {
77 reg = <0x80000 0x20000>;
78 };
79 kernel@a0000 {
80 reg = <0xa0000 0x200000>;
81 };
82 dtb@2a0000 {
83 reg = <0x2a0000 0x20000>;
84 };
85 ramdisk@2c0000 {
86 reg = <0x2c0000 0x640000>;
87 };
88 user@700000 {
89 reg = <0x700000 0x3900000>;
90 };
91 };
92
93 can@1,0 {
94 compatible = "nxp,sja1000";
95 reg = <0x1 0x0 0x80>;
96 interrupts = <18 0x8>;
97 interrups-parent = <&ipic>;
98 };
99
100 cpld@2,0 {
101 compatible = "denx,mpc8308_p1m-cpld";
102 reg = <0x2 0x0 0x8>;
103 interrupts = <48 0x8>;
104 interrups-parent = <&ipic>;
105 };
106 };
107
108 immr@e0000000 {
109 #address-cells = <1>;
110 #size-cells = <1>;
111 device_type = "soc";
112 compatible = "fsl,mpc8308-immr", "simple-bus";
113 ranges = <0 0xe0000000 0x00100000>;
114 reg = <0xe0000000 0x00000200>;
115 bus-frequency = <0>;
116
117 i2c@3000 {
118 #address-cells = <1>;
119 #size-cells = <0>;
120 compatible = "fsl-i2c";
121 reg = <0x3000 0x100>;
122 interrupts = <14 0x8>;
123 interrupt-parent = <&ipic>;
124 dfsrr;
125 fram@50 {
126 compatible = "ramtron,24c64";
127 reg = <0x50>;
128 };
129 };
130
131 i2c@3100 {
132 #address-cells = <1>;
133 #size-cells = <0>;
134 compatible = "fsl-i2c";
135 reg = <0x3100 0x100>;
136 interrupts = <15 0x8>;
137 interrupt-parent = <&ipic>;
138 dfsrr;
139 pwm@28 {
140 compatible = "maxim,ds1050";
141 reg = <0x28>;
142 };
143 sensor@48 {
144 compatible = "maxim,max6625";
145 reg = <0x48>;
146 };
147 sensor@49 {
148 compatible = "maxim,max6625";
149 reg = <0x49>;
150 };
151 sensor@4b {
152 compatible = "maxim,max6625";
153 reg = <0x4b>;
154 };
155 };
156
157 usb@23000 {
158 compatible = "fsl-usb2-dr";
159 reg = <0x23000 0x1000>;
160 #address-cells = <1>;
161 #size-cells = <0>;
162 interrupt-parent = <&ipic>;
163 interrupts = <38 0x8>;
164 dr_mode = "peripheral";
165 phy_type = "ulpi";
166 };
167
168 enet0: ethernet@24000 {
169 #address-cells = <1>;
170 #size-cells = <1>;
171 ranges = <0x0 0x24000 0x1000>;
172
173 cell-index = <0>;
174 device_type = "network";
175 model = "eTSEC";
176 compatible = "gianfar";
177 reg = <0x24000 0x1000>;
178 local-mac-address = [ 00 00 00 00 00 00 ];
179 interrupts = <32 0x8 33 0x8 34 0x8>;
180 interrupt-parent = <&ipic>;
181 phy-handle = < &phy1 >;
182
183 mdio@520 {
184 #address-cells = <1>;
185 #size-cells = <0>;
186 compatible = "fsl,gianfar-mdio";
187 reg = <0x520 0x20>;
188 phy1: ethernet-phy@1 {
189 interrupt-parent = <&ipic>;
190 interrupts = <17 0x8>;
191 reg = <0x1>;
192 device_type = "ethernet-phy";
193 };
194 phy2: ethernet-phy@2 {
195 interrupt-parent = <&ipic>;
196 interrupts = <19 0x8>;
197 reg = <0x2>;
198 device_type = "ethernet-phy";
199 };
200 tbi0: tbi-phy@11 {
201 reg = <0x11>;
202 device_type = "tbi-phy";
203 };
204 };
205 };
206
207 enet1: ethernet@25000 {
208 #address-cells = <1>;
209 #size-cells = <1>;
210 cell-index = <1>;
211 device_type = "network";
212 model = "eTSEC";
213 compatible = "gianfar";
214 reg = <0x25000 0x1000>;
215 ranges = <0x0 0x25000 0x1000>;
216 local-mac-address = [ 00 00 00 00 00 00 ];
217 interrupts = <35 0x8 36 0x8 37 0x8>;
218 interrupt-parent = <&ipic>;
219 phy-handle = < &phy2 >;
220
221 mdio@520 {
222 #address-cells = <1>;
223 #size-cells = <0>;
224 compatible = "fsl,gianfar-tbi";
225 reg = <0x520 0x20>;
226 tbi1: tbi-phy@11 {
227 reg = <0x11>;
228 device_type = "tbi-phy";
229 };
230 };
231 };
232
233 serial0: serial@4500 {
234 cell-index = <0>;
235 device_type = "serial";
236 compatible = "ns16550";
237 reg = <0x4500 0x100>;
238 clock-frequency = <133333333>;
239 interrupts = <9 0x8>;
240 interrupt-parent = <&ipic>;
241 };
242
243 serial1: serial@4600 {
244 cell-index = <1>;
245 device_type = "serial";
246 compatible = "ns16550";
247 reg = <0x4600 0x100>;
248 clock-frequency = <133333333>;
249 interrupts = <10 0x8>;
250 interrupt-parent = <&ipic>;
251 };
252
253 gpio@c00 {
254 #gpio-cells = <2>;
255 compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio";
256 reg = <0xc00 0x18>;
257 interrupts = <74 0x8>;
258 interrupt-parent = <&ipic>;
259 gpio-controller;
260 };
261
262 timer@500 {
263 compatible = "fsl,mpc8308-gtm", "fsl,gtm";
264 reg = <0x500 0x100>;
265 interrupts = <90 8 78 8 84 8 72 8>;
266 interrupt-parent = <&ipic>;
267 clock-frequency = <133333333>;
268 };
269
270 /* IPIC
271 * interrupts cell = <intr #, sense>
272 * sense values match linux IORESOURCE_IRQ_* defines:
273 * sense == 8: Level, low assertion
274 * sense == 2: Edge, high-to-low change
275 */
276 ipic: interrupt-controller@700 {
277 compatible = "fsl,ipic";
278 interrupt-controller;
279 #address-cells = <0>;
280 #interrupt-cells = <2>;
281 reg = <0x700 0x100>;
282 device_type = "ipic";
283 };
284
285 ipic-msi@7c0 {
286 compatible = "fsl,ipic-msi";
287 reg = <0x7c0 0x40>;
288 msi-available-ranges = <0x0 0x100>;
289 interrupts = < 0x43 0x8
290 0x4 0x8
291 0x51 0x8
292 0x52 0x8
293 0x56 0x8
294 0x57 0x8
295 0x58 0x8
296 0x59 0x8 >;
297 interrupt-parent = < &ipic >;
298 };
299
300 };
301
302 pci0: pcie@e0009000 {
303 #address-cells = <3>;
304 #size-cells = <2>;
305 #interrupt-cells = <1>;
306 device_type = "pci";
307 compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie";
308 reg = <0xe0009000 0x00001000
309 0xb0000000 0x01000000>;
310 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
311 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
312 bus-range = <0 0>;
313 interrupt-map-mask = <0 0 0 0>;
314 interrupt-map = <0 0 0 0 &ipic 1 8>;
315 interrupts = <0x1 0x8>;
316 interrupt-parent = <&ipic>;
317 clock-frequency = <0>;
318
319 pcie@0 {
320 #address-cells = <3>;
321 #size-cells = <2>;
322 device_type = "pci";
323 reg = <0 0 0 0 0>;
324 ranges = <0x02000000 0 0xa0000000
325 0x02000000 0 0xa0000000
326 0 0x10000000
327 0x01000000 0 0x00000000
328 0x01000000 0 0x00000000
329 0 0x00800000>;
330 };
331 };
332};
diff --git a/arch/powerpc/boot/dts/p1022ds.dts b/arch/powerpc/boot/dts/p1022ds.dts
index 8bcb10b92677..2bbecbb4cbf9 100644
--- a/arch/powerpc/boot/dts/p1022ds.dts
+++ b/arch/powerpc/boot/dts/p1022ds.dts
@@ -148,6 +148,17 @@
148 label = "reserved-nand"; 148 label = "reserved-nand";
149 }; 149 };
150 }; 150 };
151
152 board-control@3,0 {
153 compatible = "fsl,p1022ds-pixis";
154 reg = <3 0 0x30>;
155 interrupt-parent = <&mpic>;
156 /*
157 * IRQ8 is generated if the "EVENT" switch is pressed
158 * and PX_CTL[EVESEL] is set to 00.
159 */
160 interrupts = <8 8>;
161 };
151 }; 162 };
152 163
153 soc@fffe00000 { 164 soc@fffe00000 {
diff --git a/arch/powerpc/configs/e55xx_smp_defconfig b/arch/powerpc/configs/e55xx_smp_defconfig
new file mode 100644
index 000000000000..94d120ef99cf
--- /dev/null
+++ b/arch/powerpc/configs/e55xx_smp_defconfig
@@ -0,0 +1,84 @@
1CONFIG_PPC64=y
2CONFIG_PPC_BOOK3E_64=y
3# CONFIG_VIRT_CPU_ACCOUNTING is not set
4CONFIG_SMP=y
5CONFIG_NR_CPUS=2
6CONFIG_EXPERIMENTAL=y
7CONFIG_SYSVIPC=y
8CONFIG_BSD_PROCESS_ACCT=y
9CONFIG_IKCONFIG=y
10CONFIG_IKCONFIG_PROC=y
11CONFIG_LOG_BUF_SHIFT=14
12CONFIG_SYSFS_DEPRECATED_V2=y
13CONFIG_BLK_DEV_INITRD=y
14# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
15CONFIG_EMBEDDED=y
16CONFIG_KALLSYMS_ALL=y
17CONFIG_KALLSYMS_EXTRA_PASS=y
18CONFIG_MODULES=y
19CONFIG_MODULE_UNLOAD=y
20CONFIG_MODULE_FORCE_UNLOAD=y
21CONFIG_MODVERSIONS=y
22# CONFIG_BLK_DEV_BSG is not set
23CONFIG_P5020_DS=y
24# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
25CONFIG_NO_HZ=y
26CONFIG_HIGH_RES_TIMERS=y
27CONFIG_BINFMT_MISC=m
28CONFIG_SPARSE_IRQ=y
29# CONFIG_PCI is not set
30CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
31CONFIG_PROC_DEVICETREE=y
32CONFIG_BLK_DEV_LOOP=y
33CONFIG_BLK_DEV_RAM=y
34CONFIG_BLK_DEV_RAM_SIZE=131072
35CONFIG_EEPROM_LEGACY=y
36CONFIG_INPUT_FF_MEMLESS=m
37# CONFIG_INPUT_MOUSEDEV is not set
38# CONFIG_INPUT_KEYBOARD is not set
39# CONFIG_INPUT_MOUSE is not set
40CONFIG_SERIO_LIBPS2=y
41CONFIG_SERIAL_8250=y
42CONFIG_SERIAL_8250_CONSOLE=y
43CONFIG_SERIAL_8250_EXTENDED=y
44CONFIG_SERIAL_8250_MANY_PORTS=y
45CONFIG_SERIAL_8250_DETECT_IRQ=y
46CONFIG_SERIAL_8250_RSA=y
47CONFIG_I2C=y
48# CONFIG_HWMON is not set
49CONFIG_VIDEO_OUTPUT_CONTROL=y
50# CONFIG_HID_SUPPORT is not set
51# CONFIG_USB_SUPPORT is not set
52CONFIG_DMADEVICES=y
53CONFIG_FSL_DMA=y
54CONFIG_EXT2_FS=y
55CONFIG_EXT3_FS=y
56# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
57CONFIG_PROC_KCORE=y
58CONFIG_TMPFS=y
59# CONFIG_MISC_FILESYSTEMS is not set
60CONFIG_PARTITION_ADVANCED=y
61CONFIG_MAC_PARTITION=y
62CONFIG_NLS=y
63CONFIG_NLS_UTF8=m
64CONFIG_CRC_T10DIF=y
65CONFIG_CRC_ITU_T=m
66CONFIG_LIBCRC32C=m
67CONFIG_FRAME_WARN=1024
68CONFIG_DEBUG_FS=y
69CONFIG_DEBUG_KERNEL=y
70CONFIG_DETECT_HUNG_TASK=y
71# CONFIG_DEBUG_BUGVERBOSE is not set
72CONFIG_DEBUG_INFO=y
73# CONFIG_RCU_CPU_STALL_DETECTOR is not set
74CONFIG_SYSCTL_SYSCALL_CHECK=y
75CONFIG_VIRQ_DEBUG=y
76CONFIG_CRYPTO=y
77CONFIG_CRYPTO_CBC=y
78CONFIG_CRYPTO_PCBC=m
79CONFIG_CRYPTO_HMAC=y
80CONFIG_CRYPTO_MD5=y
81CONFIG_CRYPTO_SHA1=m
82CONFIG_CRYPTO_DES=y
83# CONFIG_CRYPTO_ANSI_CPRNG is not set
84CONFIG_CRYPTO_DEV_TALITOS=y
diff --git a/arch/powerpc/configs/ppc64e_defconfig b/arch/powerpc/configs/ppc64e_defconfig
index 04ae0740b6d0..7bd1763877ba 100644
--- a/arch/powerpc/configs/ppc64e_defconfig
+++ b/arch/powerpc/configs/ppc64e_defconfig
@@ -18,6 +18,7 @@ CONFIG_MODULES=y
18CONFIG_MODULE_UNLOAD=y 18CONFIG_MODULE_UNLOAD=y
19CONFIG_MODVERSIONS=y 19CONFIG_MODVERSIONS=y
20CONFIG_MODULE_SRCVERSION_ALL=y 20CONFIG_MODULE_SRCVERSION_ALL=y
21CONFIG_P5020_DS=y
21CONFIG_CPU_FREQ=y 22CONFIG_CPU_FREQ=y
22CONFIG_CPU_FREQ_GOV_POWERSAVE=y 23CONFIG_CPU_FREQ_GOV_POWERSAVE=y
23CONFIG_CPU_FREQ_GOV_USERSPACE=y 24CONFIG_CPU_FREQ_GOV_USERSPACE=y
@@ -256,7 +257,6 @@ CONFIG_HID_ZEROPLUS=y
256CONFIG_USB=y 257CONFIG_USB=y
257CONFIG_USB_DEVICEFS=y 258CONFIG_USB_DEVICEFS=y
258CONFIG_USB_EHCI_HCD=y 259CONFIG_USB_EHCI_HCD=y
259CONFIG_USB_EHCI_TT_NEWSCHED=y
260# CONFIG_USB_EHCI_HCD_PPC_OF is not set 260# CONFIG_USB_EHCI_HCD_PPC_OF is not set
261CONFIG_USB_OHCI_HCD=y 261CONFIG_USB_OHCI_HCD=y
262CONFIG_USB_STORAGE=m 262CONFIG_USB_STORAGE=m
@@ -290,7 +290,6 @@ CONFIG_JFS_POSIX_ACL=y
290CONFIG_JFS_SECURITY=y 290CONFIG_JFS_SECURITY=y
291CONFIG_XFS_FS=m 291CONFIG_XFS_FS=m
292CONFIG_XFS_POSIX_ACL=y 292CONFIG_XFS_POSIX_ACL=y
293CONFIG_INOTIFY=y
294CONFIG_AUTOFS4_FS=m 293CONFIG_AUTOFS4_FS=m
295CONFIG_ISO9660_FS=y 294CONFIG_ISO9660_FS=y
296CONFIG_UDF_FS=m 295CONFIG_UDF_FS=m
@@ -384,7 +383,6 @@ CONFIG_CRYPTO_TGR192=m
384CONFIG_CRYPTO_WP512=m 383CONFIG_CRYPTO_WP512=m
385CONFIG_CRYPTO_AES=m 384CONFIG_CRYPTO_AES=m
386CONFIG_CRYPTO_ANUBIS=m 385CONFIG_CRYPTO_ANUBIS=m
387CONFIG_CRYPTO_ARC4=m
388CONFIG_CRYPTO_BLOWFISH=m 386CONFIG_CRYPTO_BLOWFISH=m
389CONFIG_CRYPTO_CAST6=m 387CONFIG_CRYPTO_CAST6=m
390CONFIG_CRYPTO_KHAZAD=m 388CONFIG_CRYPTO_KHAZAD=m
diff --git a/arch/powerpc/include/asm/fsl_85xx_cache_sram.h b/arch/powerpc/include/asm/fsl_85xx_cache_sram.h
new file mode 100644
index 000000000000..2af2bdc37b2e
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_85xx_cache_sram.h
@@ -0,0 +1,48 @@
1/*
2 * Copyright 2009 Freescale Semiconductor, Inc.
3 *
4 * Cache SRAM handling for QorIQ platform
5 *
6 * Author: Vivek Mahajan <vivek.mahajan@freescale.com>
7
8 * This file is derived from the original work done
9 * by Sylvain Munaut for the Bestcomm SRAM allocator.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26#ifndef __ASM_POWERPC_FSL_85XX_CACHE_SRAM_H__
27#define __ASM_POWERPC_FSL_85XX_CACHE_SRAM_H__
28
29#include <asm/rheap.h>
30#include <linux/spinlock.h>
31
32/*
33 * Cache-SRAM
34 */
35
36struct mpc85xx_cache_sram {
37 phys_addr_t base_phys;
38 void *base_virt;
39 unsigned int size;
40 rh_info_t *rh;
41 spinlock_t lock;
42};
43
44extern void mpc85xx_cache_sram_free(void *ptr);
45extern void *mpc85xx_cache_sram_alloc(unsigned int size,
46 phys_addr_t *phys, unsigned int align);
47
48#endif /* __AMS_POWERPC_FSL_85XX_CACHE_SRAM_H__ */
diff --git a/arch/powerpc/include/asm/kexec.h b/arch/powerpc/include/asm/kexec.h
index 076327f2eff7..f54408d995b5 100644
--- a/arch/powerpc/include/asm/kexec.h
+++ b/arch/powerpc/include/asm/kexec.h
@@ -91,6 +91,7 @@ extern void machine_kexec_simple(struct kimage *image);
91extern void crash_kexec_secondary(struct pt_regs *regs); 91extern void crash_kexec_secondary(struct pt_regs *regs);
92extern int overlaps_crashkernel(unsigned long start, unsigned long size); 92extern int overlaps_crashkernel(unsigned long start, unsigned long size);
93extern void reserve_crashkernel(void); 93extern void reserve_crashkernel(void);
94extern void machine_kexec_mask_interrupts(void);
94 95
95#else /* !CONFIG_KEXEC */ 96#else /* !CONFIG_KEXEC */
96static inline int kexec_sr_activated(int cpu) { return 0; } 97static inline int kexec_sr_activated(int cpu) { return 0; }
diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h
index 87a1d787c5b6..8eaed81ea642 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -114,6 +114,17 @@
114 114
115#define MAS7_RPN 0xFFFFFFFF 115#define MAS7_RPN 0xFFFFFFFF
116 116
117/* Bit definitions for MMUCFG */
118#define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
119#define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
120#define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
121#define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
122#define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
123#define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
124#define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
125#define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
126#define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
127
117/* Bit definitions for MMUCSR0 */ 128/* Bit definitions for MMUCSR0 */
118#define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */ 129#define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
119#define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */ 130#define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
@@ -133,6 +144,10 @@
133#define TLBnCFG_GTWE 0x00010000 /* Guest can write */ 144#define TLBnCFG_GTWE 0x00010000 /* Guest can write */
134#define TLBnCFG_IND 0x00020000 /* IND entries supported */ 145#define TLBnCFG_IND 0x00020000 /* IND entries supported */
135#define TLBnCFG_PT 0x00040000 /* Can load from page table */ 146#define TLBnCFG_PT 0x00040000 /* Can load from page table */
147#define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
148#define TLBnCFG_MINSIZE_SHIFT 20
149#define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
150#define TLBnCFG_MAXSIZE_SHIFT 16
136#define TLBnCFG_ASSOC 0xff000000 /* Associativity */ 151#define TLBnCFG_ASSOC 0xff000000 /* Associativity */
137 152
138/* TLBnPS encoding */ 153/* TLBnPS encoding */
diff --git a/arch/powerpc/include/asm/pte-common.h b/arch/powerpc/include/asm/pte-common.h
index f2b370180a09..76bb195e4f24 100644
--- a/arch/powerpc/include/asm/pte-common.h
+++ b/arch/powerpc/include/asm/pte-common.h
@@ -171,6 +171,13 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
171/* Make modules code happy. We don't set RO yet */ 171/* Make modules code happy. We don't set RO yet */
172#define PAGE_KERNEL_EXEC PAGE_KERNEL_X 172#define PAGE_KERNEL_EXEC PAGE_KERNEL_X
173 173
174/*
175 * Don't just check for any non zero bits in __PAGE_USER, since for book3e
176 * and PTE_64BIT, PAGE_KERNEL_X contains _PAGE_BAP_SR which is also in
177 * _PAGE_USER. Need to explictly match _PAGE_BAP_UR bit in that case too.
178 */
179#define pte_user(val) ((val & _PAGE_USER) == _PAGE_USER)
180
174/* Advertise special mapping type for AGP */ 181/* Advertise special mapping type for AGP */
175#define PAGE_AGP (PAGE_KERNEL_NC) 182#define PAGE_AGP (PAGE_KERNEL_NC)
176#define HAVE_PAGE_AGP 183#define HAVE_PAGE_AGP
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 1dda70129141..4ed076a4db24 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -55,7 +55,9 @@ obj-$(CONFIG_IBMVIO) += vio.o
55obj-$(CONFIG_IBMEBUS) += ibmebus.o 55obj-$(CONFIG_IBMEBUS) += ibmebus.o
56obj-$(CONFIG_GENERIC_TBSYNC) += smp-tbsync.o 56obj-$(CONFIG_GENERIC_TBSYNC) += smp-tbsync.o
57obj-$(CONFIG_CRASH_DUMP) += crash_dump.o 57obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
58ifeq ($(CONFIG_PPC32),y)
58obj-$(CONFIG_E500) += idle_e500.o 59obj-$(CONFIG_E500) += idle_e500.o
60endif
59obj-$(CONFIG_6xx) += idle_6xx.o l2cr_6xx.o cpu_setup_6xx.o 61obj-$(CONFIG_6xx) += idle_6xx.o l2cr_6xx.o cpu_setup_6xx.o
60obj-$(CONFIG_TAU) += tau_6xx.o 62obj-$(CONFIG_TAU) += tau_6xx.o
61obj-$(CONFIG_HIBERNATION) += swsusp.o suspend.o 63obj-$(CONFIG_HIBERNATION) += swsusp.o suspend.o
@@ -67,7 +69,7 @@ endif
67obj64-$(CONFIG_HIBERNATION) += swsusp_asm64.o 69obj64-$(CONFIG_HIBERNATION) += swsusp_asm64.o
68obj-$(CONFIG_MODULES) += module.o module_$(CONFIG_WORD_SIZE).o 70obj-$(CONFIG_MODULES) += module.o module_$(CONFIG_WORD_SIZE).o
69obj-$(CONFIG_44x) += cpu_setup_44x.o 71obj-$(CONFIG_44x) += cpu_setup_44x.o
70obj-$(CONFIG_FSL_BOOKE) += cpu_setup_fsl_booke.o dbell.o 72obj-$(CONFIG_PPC_FSL_BOOK3E) += cpu_setup_fsl_booke.o dbell.o
71obj-$(CONFIG_PPC_BOOK3E_64) += dbell.o 73obj-$(CONFIG_PPC_BOOK3E_64) += dbell.o
72 74
73extra-y := head_$(CONFIG_WORD_SIZE).o 75extra-y := head_$(CONFIG_WORD_SIZE).o
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index c63494090854..c3e01945ad4f 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -61,7 +61,7 @@
61#endif 61#endif
62#endif 62#endif
63 63
64#if defined(CONFIG_FSL_BOOKE) 64#if defined(CONFIG_PPC_FSL_BOOK3E)
65#include "../mm/mmu_decl.h" 65#include "../mm/mmu_decl.h"
66#endif 66#endif
67 67
@@ -470,7 +470,7 @@ int main(void)
470 DEFINE(PGD_T_LOG2, PGD_T_LOG2); 470 DEFINE(PGD_T_LOG2, PGD_T_LOG2);
471 DEFINE(PTE_T_LOG2, PTE_T_LOG2); 471 DEFINE(PTE_T_LOG2, PTE_T_LOG2);
472#endif 472#endif
473#ifdef CONFIG_FSL_BOOKE 473#ifdef CONFIG_PPC_FSL_BOOK3E
474 DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam)); 474 DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam));
475 DEFINE(TLBCAM_MAS0, offsetof(struct tlbcam, MAS0)); 475 DEFINE(TLBCAM_MAS0, offsetof(struct tlbcam, MAS0));
476 DEFINE(TLBCAM_MAS1, offsetof(struct tlbcam, MAS1)); 476 DEFINE(TLBCAM_MAS1, offsetof(struct tlbcam, MAS1));
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index 0adb50ad8031..894e64fa481e 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -51,6 +51,7 @@ _GLOBAL(__e500_dcache_setup)
51 isync 51 isync
52 blr 52 blr
53 53
54#ifdef CONFIG_PPC32
54_GLOBAL(__setup_cpu_e200) 55_GLOBAL(__setup_cpu_e200)
55 /* enable dedicated debug exception handling resources (Debug APU) */ 56 /* enable dedicated debug exception handling resources (Debug APU) */
56 mfspr r3,SPRN_HID0 57 mfspr r3,SPRN_HID0
@@ -72,3 +73,17 @@ _GLOBAL(__setup_cpu_e500mc)
72 bl __setup_e500mc_ivors 73 bl __setup_e500mc_ivors
73 mtlr r4 74 mtlr r4
74 blr 75 blr
76#endif
77/* Right now, restore and setup are the same thing */
78_GLOBAL(__restore_cpu_e5500)
79_GLOBAL(__setup_cpu_e5500)
80 mflr r4
81 bl __e500_icache_setup
82 bl __e500_dcache_setup
83#ifdef CONFIG_PPC_BOOK3E_64
84 bl .__setup_base_ivors
85#else
86 bl __setup_e500mc_ivors
87#endif
88 mtlr r4
89 blr
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index b7ac795e5270..96a908f1cd87 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -67,6 +67,10 @@ extern void __restore_cpu_ppc970(void);
67extern void __setup_cpu_power7(unsigned long offset, struct cpu_spec* spec); 67extern void __setup_cpu_power7(unsigned long offset, struct cpu_spec* spec);
68extern void __restore_cpu_power7(void); 68extern void __restore_cpu_power7(void);
69#endif /* CONFIG_PPC64 */ 69#endif /* CONFIG_PPC64 */
70#if defined(CONFIG_E500)
71extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec);
72extern void __restore_cpu_e5500(void);
73#endif /* CONFIG_E500 */
70 74
71/* This table only contains "desktop" CPUs, it need to be filled with embedded 75/* This table only contains "desktop" CPUs, it need to be filled with embedded
72 * ones as well... 76 * ones as well...
@@ -1906,7 +1910,9 @@ static struct cpu_spec __initdata cpu_specs[] = {
1906 .platform = "ppc5554", 1910 .platform = "ppc5554",
1907 } 1911 }
1908#endif /* CONFIG_E200 */ 1912#endif /* CONFIG_E200 */
1913#endif /* CONFIG_PPC32 */
1909#ifdef CONFIG_E500 1914#ifdef CONFIG_E500
1915#ifdef CONFIG_PPC32
1910 { /* e500 */ 1916 { /* e500 */
1911 .pvr_mask = 0xffff0000, 1917 .pvr_mask = 0xffff0000,
1912 .pvr_value = 0x80200000, 1918 .pvr_value = 0x80200000,
@@ -1961,6 +1967,26 @@ static struct cpu_spec __initdata cpu_specs[] = {
1961 .machine_check = machine_check_e500mc, 1967 .machine_check = machine_check_e500mc,
1962 .platform = "ppce500mc", 1968 .platform = "ppce500mc",
1963 }, 1969 },
1970#endif /* CONFIG_PPC32 */
1971 { /* e5500 */
1972 .pvr_mask = 0xffff0000,
1973 .pvr_value = 0x80240000,
1974 .cpu_name = "e5500",
1975 .cpu_features = CPU_FTRS_E500MC,
1976 .cpu_user_features = COMMON_USER_BOOKE,
1977 .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
1978 MMU_FTR_USE_TLBILX,
1979 .icache_bsize = 64,
1980 .dcache_bsize = 64,
1981 .num_pmcs = 4,
1982 .oprofile_cpu_type = "ppc/e500mc",
1983 .oprofile_type = PPC_OPROFILE_FSL_EMB,
1984 .cpu_setup = __setup_cpu_e5500,
1985 .cpu_restore = __restore_cpu_e5500,
1986 .machine_check = machine_check_e500mc,
1987 .platform = "ppce5500",
1988 },
1989#ifdef CONFIG_PPC32
1964 { /* default match */ 1990 { /* default match */
1965 .pvr_mask = 0x00000000, 1991 .pvr_mask = 0x00000000,
1966 .pvr_value = 0x00000000, 1992 .pvr_value = 0x00000000,
@@ -1975,8 +2001,8 @@ static struct cpu_spec __initdata cpu_specs[] = {
1975 .machine_check = machine_check_e500, 2001 .machine_check = machine_check_e500,
1976 .platform = "powerpc", 2002 .platform = "powerpc",
1977 } 2003 }
1978#endif /* CONFIG_E500 */
1979#endif /* CONFIG_PPC32 */ 2004#endif /* CONFIG_PPC32 */
2005#endif /* CONFIG_E500 */
1980 2006
1981#ifdef CONFIG_PPC_BOOK3E_64 2007#ifdef CONFIG_PPC_BOOK3E_64
1982 { /* This is a default entry to get going, to be replaced by 2008 { /* This is a default entry to get going, to be replaced by
diff --git a/arch/powerpc/kernel/crash.c b/arch/powerpc/kernel/crash.c
index 4457382f8667..832c8c4db254 100644
--- a/arch/powerpc/kernel/crash.c
+++ b/arch/powerpc/kernel/crash.c
@@ -414,18 +414,7 @@ void default_machine_crash_shutdown(struct pt_regs *regs)
414 crash_kexec_wait_realmode(crashing_cpu); 414 crash_kexec_wait_realmode(crashing_cpu);
415#endif 415#endif
416 416
417 for_each_irq(i) { 417 machine_kexec_mask_interrupts();
418 struct irq_desc *desc = irq_to_desc(i);
419
420 if (!desc || !desc->chip || !desc->chip->eoi)
421 continue;
422
423 if (desc->status & IRQ_INPROGRESS)
424 desc->chip->eoi(i);
425
426 if (!(desc->status & IRQ_DISABLED))
427 desc->chip->shutdown(i);
428 }
429 418
430 /* 419 /*
431 * Call registered shutdown routines savely. Swap out 420 * Call registered shutdown routines savely. Swap out
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 4faeba247854..529b817f473b 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -152,8 +152,11 @@ _ENTRY(__early_start)
152 /* Check to see if we're the second processor, and jump 152 /* Check to see if we're the second processor, and jump
153 * to the secondary_start code if so 153 * to the secondary_start code if so
154 */ 154 */
155 mfspr r24,SPRN_PIR 155 lis r24, boot_cpuid@h
156 cmpwi r24,0 156 ori r24, r24, boot_cpuid@l
157 lwz r24, 0(r24)
158 cmpwi r24, -1
159 mfspr r24,SPRN_PIR
157 bne __secondary_start 160 bne __secondary_start
158#endif 161#endif
159 162
@@ -175,6 +178,9 @@ _ENTRY(__early_start)
175 li r0,0 178 li r0,0
176 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) 179 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
177 180
181 rlwinm r22,r1,0,0,31-THREAD_SHIFT /* current thread_info */
182 stw r24, TI_CPU(r22)
183
178 bl early_init 184 bl early_init
179 185
180#ifdef CONFIG_RELOCATABLE 186#ifdef CONFIG_RELOCATABLE
diff --git a/arch/powerpc/kernel/machine_kexec.c b/arch/powerpc/kernel/machine_kexec.c
index dd6c141f1662..df7e20c191cd 100644
--- a/arch/powerpc/kernel/machine_kexec.c
+++ b/arch/powerpc/kernel/machine_kexec.c
@@ -14,10 +14,34 @@
14#include <linux/threads.h> 14#include <linux/threads.h>
15#include <linux/memblock.h> 15#include <linux/memblock.h>
16#include <linux/of.h> 16#include <linux/of.h>
17#include <linux/irq.h>
18
17#include <asm/machdep.h> 19#include <asm/machdep.h>
18#include <asm/prom.h> 20#include <asm/prom.h>
19#include <asm/sections.h> 21#include <asm/sections.h>
20 22
23void machine_kexec_mask_interrupts(void) {
24 unsigned int i;
25
26 for_each_irq(i) {
27 struct irq_desc *desc = irq_to_desc(i);
28
29 if (!desc || !desc->chip)
30 continue;
31
32 if (desc->chip->eoi &&
33 desc->status & IRQ_INPROGRESS)
34 desc->chip->eoi(i);
35
36 if (desc->chip->mask)
37 desc->chip->mask(i);
38
39 if (desc->chip->disable &&
40 !(desc->status & IRQ_DISABLED))
41 desc->chip->disable(i);
42 }
43}
44
21void machine_crash_shutdown(struct pt_regs *regs) 45void machine_crash_shutdown(struct pt_regs *regs)
22{ 46{
23 if (ppc_md.machine_crash_shutdown) 47 if (ppc_md.machine_crash_shutdown)
diff --git a/arch/powerpc/kernel/machine_kexec_32.c b/arch/powerpc/kernel/machine_kexec_32.c
index ae63a964b858..e63f2e7d2efb 100644
--- a/arch/powerpc/kernel/machine_kexec_32.c
+++ b/arch/powerpc/kernel/machine_kexec_32.c
@@ -39,6 +39,10 @@ void default_machine_kexec(struct kimage *image)
39 /* Interrupts aren't acceptable while we reboot */ 39 /* Interrupts aren't acceptable while we reboot */
40 local_irq_disable(); 40 local_irq_disable();
41 41
42 /* mask each interrupt so we are in a more sane state for the
43 * kexec kernel */
44 machine_kexec_mask_interrupts();
45
42 page_list = image->head; 46 page_list = image->head;
43 47
44 /* we need both effective and real address here */ 48 /* we need both effective and real address here */
diff --git a/arch/powerpc/kernel/paca.c b/arch/powerpc/kernel/paca.c
index 1e068a46e6c3..cefc0df8f1e5 100644
--- a/arch/powerpc/kernel/paca.c
+++ b/arch/powerpc/kernel/paca.c
@@ -108,7 +108,7 @@ static void free_lppacas(void)
108 108
109#else 109#else
110 110
111static inline void allocate_lppacas(int, unsigned long) { } 111static inline void allocate_lppacas(int nr_cpus, unsigned long limit) { }
112static inline void free_lppacas(void) { } 112static inline void free_lppacas(void) { }
113 113
114#endif /* CONFIG_PPC_BOOK3S */ 114#endif /* CONFIG_PPC_BOOK3S */
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index 93666f9cabf1..8da1632f9fe7 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -46,7 +46,7 @@
46 46
47extern void bootx_init(unsigned long r4, unsigned long phys); 47extern void bootx_init(unsigned long r4, unsigned long phys);
48 48
49int boot_cpuid; 49int boot_cpuid = -1;
50EXPORT_SYMBOL_GPL(boot_cpuid); 50EXPORT_SYMBOL_GPL(boot_cpuid);
51int boot_cpuid_phys; 51int boot_cpuid_phys;
52 52
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index bcb738b9ff8c..644f9188d8e7 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -161,8 +161,9 @@ extern struct timezone sys_tz;
161static long timezone_offset; 161static long timezone_offset;
162 162
163unsigned long ppc_proc_freq; 163unsigned long ppc_proc_freq;
164EXPORT_SYMBOL(ppc_proc_freq); 164EXPORT_SYMBOL_GPL(ppc_proc_freq);
165unsigned long ppc_tb_freq; 165unsigned long ppc_tb_freq;
166EXPORT_SYMBOL_GPL(ppc_tb_freq);
166 167
167#ifdef CONFIG_VIRT_CPU_ACCOUNTING 168#ifdef CONFIG_VIRT_CPU_ACCOUNTING
168/* 169/*
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index a45a63c3a0c7..1b2cdc8eec90 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -538,6 +538,11 @@ int machine_check_e500(struct pt_regs *regs)
538 538
539 return 0; 539 return 0;
540} 540}
541
542int machine_check_generic(struct pt_regs *regs)
543{
544 return 0;
545}
541#elif defined(CONFIG_E200) 546#elif defined(CONFIG_E200)
542int machine_check_e200(struct pt_regs *regs) 547int machine_check_e200(struct pt_regs *regs)
543{ 548{
diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile
index 53102f306880..bdca46e08382 100644
--- a/arch/powerpc/mm/Makefile
+++ b/arch/powerpc/mm/Makefile
@@ -23,7 +23,7 @@ obj-$(CONFIG_PPC_STD_MMU) += hash_low_$(CONFIG_WORD_SIZE).o \
23 mmu_context_hash$(CONFIG_WORD_SIZE).o 23 mmu_context_hash$(CONFIG_WORD_SIZE).o
24obj-$(CONFIG_40x) += 40x_mmu.o 24obj-$(CONFIG_40x) += 40x_mmu.o
25obj-$(CONFIG_44x) += 44x_mmu.o 25obj-$(CONFIG_44x) += 44x_mmu.o
26obj-$(CONFIG_FSL_BOOKE) += fsl_booke_mmu.o 26obj-$(CONFIG_PPC_FSL_BOOK3E) += fsl_booke_mmu.o
27obj-$(CONFIG_NEED_MULTIPLE_NODES) += numa.o 27obj-$(CONFIG_NEED_MULTIPLE_NODES) += numa.o
28obj-$(CONFIG_PPC_MM_SLICES) += slice.o 28obj-$(CONFIG_PPC_MM_SLICES) += slice.o
29ifeq ($(CONFIG_HUGETLB_PAGE),y) 29ifeq ($(CONFIG_HUGETLB_PAGE),y)
diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c
index 4b66a1ece6d8..67bc8a7c7e0b 100644
--- a/arch/powerpc/mm/fsl_booke_mmu.c
+++ b/arch/powerpc/mm/fsl_booke_mmu.c
@@ -56,11 +56,6 @@
56 56
57unsigned int tlbcam_index; 57unsigned int tlbcam_index;
58 58
59
60#if defined(CONFIG_LOWMEM_CAM_NUM_BOOL) && (CONFIG_LOWMEM_CAM_NUM >= NUM_TLBCAMS)
61#error "LOWMEM_CAM_NUM must be less than NUM_TLBCAMS"
62#endif
63
64#define NUM_TLBCAMS (64) 59#define NUM_TLBCAMS (64)
65struct tlbcam TLBCAM[NUM_TLBCAMS]; 60struct tlbcam TLBCAM[NUM_TLBCAMS];
66 61
@@ -137,7 +132,8 @@ static void settlbcam(int index, unsigned long virt, phys_addr_t phys,
137 if (mmu_has_feature(MMU_FTR_BIG_PHYS)) 132 if (mmu_has_feature(MMU_FTR_BIG_PHYS))
138 TLBCAM[index].MAS7 = (u64)phys >> 32; 133 TLBCAM[index].MAS7 = (u64)phys >> 32;
139 134
140 if (flags & _PAGE_USER) { 135 /* Below is unlikely -- only for large user pages or similar */
136 if (pte_user(flags)) {
141 TLBCAM[index].MAS3 |= MAS3_UX | MAS3_UR; 137 TLBCAM[index].MAS3 |= MAS3_UX | MAS3_UR;
142 TLBCAM[index].MAS3 |= ((flags & _PAGE_RW) ? MAS3_UW : 0); 138 TLBCAM[index].MAS3 |= ((flags & _PAGE_RW) ? MAS3_UW : 0);
143 } 139 }
@@ -184,6 +180,12 @@ unsigned long map_mem_in_cams(unsigned long ram, int max_cam_idx)
184 return amount_mapped; 180 return amount_mapped;
185} 181}
186 182
183#ifdef CONFIG_PPC32
184
185#if defined(CONFIG_LOWMEM_CAM_NUM_BOOL) && (CONFIG_LOWMEM_CAM_NUM >= NUM_TLBCAMS)
186#error "LOWMEM_CAM_NUM must be less than NUM_TLBCAMS"
187#endif
188
187unsigned long __init mmu_mapin_ram(unsigned long top) 189unsigned long __init mmu_mapin_ram(unsigned long top)
188{ 190{
189 return tlbcam_addrs[tlbcam_index - 1].limit - PAGE_OFFSET + 1; 191 return tlbcam_addrs[tlbcam_index - 1].limit - PAGE_OFFSET + 1;
@@ -215,3 +217,4 @@ void __init adjust_total_lowmem(void)
215 217
216 __initial_memory_limit_addr = memstart_addr + __max_low_memory; 218 __initial_memory_limit_addr = memstart_addr + __max_low_memory;
217} 219}
220#endif
diff --git a/arch/powerpc/mm/mmu_decl.h b/arch/powerpc/mm/mmu_decl.h
index 63b84a0d3b10..dd0a2589591d 100644
--- a/arch/powerpc/mm/mmu_decl.h
+++ b/arch/powerpc/mm/mmu_decl.h
@@ -140,10 +140,13 @@ extern void wii_memory_fixups(void);
140extern void MMU_init_hw(void); 140extern void MMU_init_hw(void);
141extern unsigned long mmu_mapin_ram(unsigned long top); 141extern unsigned long mmu_mapin_ram(unsigned long top);
142 142
143#elif defined(CONFIG_FSL_BOOKE) 143#elif defined(CONFIG_PPC_FSL_BOOK3E)
144extern unsigned long map_mem_in_cams(unsigned long ram, int max_cam_idx);
145#ifdef CONFIG_PPC32
144extern void MMU_init_hw(void); 146extern void MMU_init_hw(void);
145extern unsigned long mmu_mapin_ram(unsigned long top); 147extern unsigned long mmu_mapin_ram(unsigned long top);
146extern void adjust_total_lowmem(void); 148extern void adjust_total_lowmem(void);
149#endif
147extern void loadcam_entry(unsigned int index); 150extern void loadcam_entry(unsigned int index);
148 151
149struct tlbcam { 152struct tlbcam {
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index fe391e942521..61fe32a256da 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -349,11 +349,47 @@ void tlb_flush_pgtable(struct mmu_gather *tlb, unsigned long address)
349 349
350static void setup_page_sizes(void) 350static void setup_page_sizes(void)
351{ 351{
352 unsigned int tlb0cfg = mfspr(SPRN_TLB0CFG); 352 unsigned int tlb0cfg;
353 unsigned int tlb0ps = mfspr(SPRN_TLB0PS); 353 unsigned int tlb0ps;
354 unsigned int eptcfg = mfspr(SPRN_EPTCFG); 354 unsigned int eptcfg;
355 int i, psize; 355 int i, psize;
356 356
357#ifdef CONFIG_PPC_FSL_BOOK3E
358 unsigned int mmucfg = mfspr(SPRN_MMUCFG);
359
360 if (((mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V1) &&
361 (mmu_has_feature(MMU_FTR_TYPE_FSL_E))) {
362 unsigned int tlb1cfg = mfspr(SPRN_TLB1CFG);
363 unsigned int min_pg, max_pg;
364
365 min_pg = (tlb1cfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
366 max_pg = (tlb1cfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
367
368 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
369 struct mmu_psize_def *def;
370 unsigned int shift;
371
372 def = &mmu_psize_defs[psize];
373 shift = def->shift;
374
375 if (shift == 0)
376 continue;
377
378 /* adjust to be in terms of 4^shift Kb */
379 shift = (shift - 10) >> 1;
380
381 if ((shift >= min_pg) && (shift <= max_pg))
382 def->flags |= MMU_PAGE_SIZE_DIRECT;
383 }
384
385 goto no_indirect;
386 }
387#endif
388
389 tlb0cfg = mfspr(SPRN_TLB0CFG);
390 tlb0ps = mfspr(SPRN_TLB0PS);
391 eptcfg = mfspr(SPRN_EPTCFG);
392
357 /* Look for supported direct sizes */ 393 /* Look for supported direct sizes */
358 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) { 394 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
359 struct mmu_psize_def *def = &mmu_psize_defs[psize]; 395 struct mmu_psize_def *def = &mmu_psize_defs[psize];
@@ -505,6 +541,20 @@ static void __early_init_mmu(int boot_cpu)
505 */ 541 */
506 linear_map_top = memblock_end_of_DRAM(); 542 linear_map_top = memblock_end_of_DRAM();
507 543
544#ifdef CONFIG_PPC_FSL_BOOK3E
545 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
546 unsigned int num_cams;
547
548 /* use a quarter of the TLBCAM for bolted linear map */
549 num_cams = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) / 4;
550 linear_map_top = map_mem_in_cams(linear_map_top, num_cams);
551
552 /* limit memory so we dont have linear faults */
553 memblock_enforce_memory_limit(linear_map_top);
554 memblock_analyze();
555 }
556#endif
557
508 /* A sync won't hurt us after mucking around with 558 /* A sync won't hurt us after mucking around with
509 * the MMU configuration 559 * the MMU configuration
510 */ 560 */
diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S
index b9d9fed8f36e..af405eefe48d 100644
--- a/arch/powerpc/mm/tlb_nohash_low.S
+++ b/arch/powerpc/mm/tlb_nohash_low.S
@@ -367,7 +367,7 @@ _GLOBAL(set_context)
367#error Unsupported processor type ! 367#error Unsupported processor type !
368#endif 368#endif
369 369
370#if defined(CONFIG_FSL_BOOKE) 370#if defined(CONFIG_PPC_FSL_BOOK3E)
371/* 371/*
372 * extern void loadcam_entry(unsigned int index) 372 * extern void loadcam_entry(unsigned int index)
373 * 373 *
diff --git a/arch/powerpc/oprofile/op_model_fsl_emb.c b/arch/powerpc/oprofile/op_model_fsl_emb.c
index 62312abffa28..d4e6507277b5 100644
--- a/arch/powerpc/oprofile/op_model_fsl_emb.c
+++ b/arch/powerpc/oprofile/op_model_fsl_emb.c
@@ -2,7 +2,7 @@
2 * Freescale Embedded oprofile support, based on ppc64 oprofile support 2 * Freescale Embedded oprofile support, based on ppc64 oprofile support
3 * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM 3 * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
4 * 4 *
5 * Copyright (c) 2004 Freescale Semiconductor, Inc 5 * Copyright (c) 2004, 2010 Freescale Semiconductor, Inc
6 * 6 *
7 * Author: Andy Fleming 7 * Author: Andy Fleming
8 * Maintainer: Kumar Gala <galak@kernel.crashing.org> 8 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
@@ -321,9 +321,6 @@ static void fsl_emb_handle_interrupt(struct pt_regs *regs,
321 int val; 321 int val;
322 int i; 322 int i;
323 323
324 /* set the PMM bit (see comment below) */
325 mtmsr(mfmsr() | MSR_PMM);
326
327 pc = regs->nip; 324 pc = regs->nip;
328 is_kernel = is_kernel_addr(pc); 325 is_kernel = is_kernel_addr(pc);
329 326
@@ -340,9 +337,13 @@ static void fsl_emb_handle_interrupt(struct pt_regs *regs,
340 } 337 }
341 338
342 /* The freeze bit was set by the interrupt. */ 339 /* The freeze bit was set by the interrupt. */
343 /* Clear the freeze bit, and reenable the interrupt. 340 /* Clear the freeze bit, and reenable the interrupt. The
344 * The counters won't actually start until the rfi clears 341 * counters won't actually start until the rfi clears the PMM
345 * the PMM bit */ 342 * bit. The PMM bit should not be set until after the interrupt
343 * is cleared to avoid it getting lost in some hypervisor
344 * environments.
345 */
346 mtmsr(mfmsr() | MSR_PMM);
346 pmc_start_ctrs(1); 347 pmc_start_ctrs(1);
347} 348}
348 349
diff --git a/arch/powerpc/platforms/83xx/Kconfig b/arch/powerpc/platforms/83xx/Kconfig
index 021763a32c2f..73f4135f3a1a 100644
--- a/arch/powerpc/platforms/83xx/Kconfig
+++ b/arch/powerpc/platforms/83xx/Kconfig
@@ -10,12 +10,12 @@ menuconfig PPC_83xx
10if PPC_83xx 10if PPC_83xx
11 11
12config MPC830x_RDB 12config MPC830x_RDB
13 bool "Freescale MPC830x RDB" 13 bool "Freescale MPC830x RDB and derivatives"
14 select DEFAULT_UIMAGE 14 select DEFAULT_UIMAGE
15 select PPC_MPC831x 15 select PPC_MPC831x
16 select FSL_GTM 16 select FSL_GTM
17 help 17 help
18 This option enables support for the MPC8308 RDB board. 18 This option enables support for the MPC8308 RDB and MPC8308 P1M boards.
19 19
20config MPC831x_RDB 20config MPC831x_RDB
21 bool "Freescale MPC831x RDB" 21 bool "Freescale MPC831x RDB"
diff --git a/arch/powerpc/platforms/83xx/mpc830x_rdb.c b/arch/powerpc/platforms/83xx/mpc830x_rdb.c
index ac102ee9abe8..846831d495b5 100644
--- a/arch/powerpc/platforms/83xx/mpc830x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc830x_rdb.c
@@ -65,7 +65,8 @@ static int __init mpc830x_rdb_probe(void)
65 unsigned long root = of_get_flat_dt_root(); 65 unsigned long root = of_get_flat_dt_root();
66 66
67 return of_flat_dt_is_compatible(root, "MPC8308RDB") || 67 return of_flat_dt_is_compatible(root, "MPC8308RDB") ||
68 of_flat_dt_is_compatible(root, "fsl,mpc8308rdb"); 68 of_flat_dt_is_compatible(root, "fsl,mpc8308rdb") ||
69 of_flat_dt_is_compatible(root, "denx,mpc8308_p1m");
69} 70}
70 71
71static struct of_device_id __initdata of_bus_ids[] = { 72static struct of_device_id __initdata of_bus_ids[] = {
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index bea1f5905ad4..b6976e1726e4 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -11,6 +11,8 @@ menuconfig FSL_SOC_BOOKE
11 11
12if FSL_SOC_BOOKE 12if FSL_SOC_BOOKE
13 13
14if PPC32
15
14config MPC8540_ADS 16config MPC8540_ADS
15 bool "Freescale MPC8540 ADS" 17 bool "Freescale MPC8540 ADS"
16 select DEFAULT_UIMAGE 18 select DEFAULT_UIMAGE
@@ -153,10 +155,20 @@ config SBC8560
153 help 155 help
154 This option enables support for the Wind River SBC8560 board 156 This option enables support for the Wind River SBC8560 board
155 157
158config P3041_DS
159 bool "Freescale P3041 DS"
160 select DEFAULT_UIMAGE
161 select PPC_E500MC
162 select PHYS_64BIT
163 select SWIOTLB
164 select MPC8xxx_GPIO
165 select HAS_RAPIDIO
166 help
167 This option enables support for the P3041 DS board
168
156config P4080_DS 169config P4080_DS
157 bool "Freescale P4080 DS" 170 bool "Freescale P4080 DS"
158 select DEFAULT_UIMAGE 171 select DEFAULT_UIMAGE
159 select PPC_FSL_BOOK3E
160 select PPC_E500MC 172 select PPC_E500MC
161 select PHYS_64BIT 173 select PHYS_64BIT
162 select SWIOTLB 174 select SWIOTLB
@@ -165,6 +177,20 @@ config P4080_DS
165 help 177 help
166 This option enables support for the P4080 DS board 178 This option enables support for the P4080 DS board
167 179
180endif # PPC32
181
182config P5020_DS
183 bool "Freescale P5020 DS"
184 select DEFAULT_UIMAGE
185 select E500
186 select PPC_E500MC
187 select PHYS_64BIT
188 select SWIOTLB
189 select MPC8xxx_GPIO
190 select HAS_RAPIDIO
191 help
192 This option enables support for the P5020 DS board
193
168endif # FSL_SOC_BOOKE 194endif # FSL_SOC_BOOKE
169 195
170config TQM85xx 196config TQM85xx
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index a2ec3f8f4d06..dd70db77d63e 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -11,7 +11,9 @@ obj-$(CONFIG_MPC85xx_DS) += mpc85xx_ds.o
11obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o 11obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
12obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o 12obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
13obj-$(CONFIG_P1022_DS) += p1022_ds.o 13obj-$(CONFIG_P1022_DS) += p1022_ds.o
14obj-$(CONFIG_P3041_DS) += p3041_ds.o corenet_ds.o
14obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o 15obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o
16obj-$(CONFIG_P5020_DS) += p5020_ds.o corenet_ds.o
15obj-$(CONFIG_STX_GP3) += stx_gp3.o 17obj-$(CONFIG_STX_GP3) += stx_gp3.o
16obj-$(CONFIG_TQM85xx) += tqm85xx.o 18obj-$(CONFIG_TQM85xx) += tqm85xx.o
17obj-$(CONFIG_SBC8560) += sbc8560.o 19obj-$(CONFIG_SBC8560) += sbc8560.o
diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c
index 34e00902ce86..2b390d19a1d1 100644
--- a/arch/powerpc/platforms/85xx/p1022_ds.c
+++ b/arch/powerpc/platforms/85xx/p1022_ds.c
@@ -112,6 +112,8 @@ static struct of_device_id __initdata p1022_ds_ids[] = {
112 { .compatible = "soc", }, 112 { .compatible = "soc", },
113 { .compatible = "simple-bus", }, 113 { .compatible = "simple-bus", },
114 { .compatible = "gianfar", }, 114 { .compatible = "gianfar", },
115 /* So that the DMA channel nodes can be probed individually: */
116 { .compatible = "fsl,eloplus-dma", },
115 {}, 117 {},
116}; 118};
117 119
diff --git a/arch/powerpc/platforms/85xx/p3041_ds.c b/arch/powerpc/platforms/85xx/p3041_ds.c
new file mode 100644
index 000000000000..0ed52e18298c
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/p3041_ds.c
@@ -0,0 +1,64 @@
1/*
2 * P3041 DS Setup
3 *
4 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
5 *
6 * Copyright 2009-2010 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/kdev_t.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/phy.h>
20
21#include <asm/system.h>
22#include <asm/time.h>
23#include <asm/machdep.h>
24#include <asm/pci-bridge.h>
25#include <mm/mmu_decl.h>
26#include <asm/prom.h>
27#include <asm/udbg.h>
28#include <asm/mpic.h>
29
30#include <linux/of_platform.h>
31#include <sysdev/fsl_soc.h>
32#include <sysdev/fsl_pci.h>
33
34#include "corenet_ds.h"
35
36/*
37 * Called very early, device-tree isn't unflattened
38 */
39static int __init p3041_ds_probe(void)
40{
41 unsigned long root = of_get_flat_dt_root();
42
43 return of_flat_dt_is_compatible(root, "fsl,P3041DS");
44}
45
46define_machine(p3041_ds) {
47 .name = "P3041 DS",
48 .probe = p3041_ds_probe,
49 .setup_arch = corenet_ds_setup_arch,
50 .init_IRQ = corenet_ds_pic_init,
51#ifdef CONFIG_PCI
52 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
53#endif
54 .get_irq = mpic_get_coreint_irq,
55 .restart = fsl_rstcr_restart,
56 .calibrate_decr = generic_calibrate_decr,
57 .progress = udbg_progress,
58};
59
60machine_device_initcall(p3041_ds, corenet_ds_publish_devices);
61
62#ifdef CONFIG_SWIOTLB
63machine_arch_initcall(p3041_ds, swiotlb_setup_bus_notifier);
64#endif
diff --git a/arch/powerpc/platforms/85xx/p5020_ds.c b/arch/powerpc/platforms/85xx/p5020_ds.c
new file mode 100644
index 000000000000..7467b712ee00
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/p5020_ds.c
@@ -0,0 +1,69 @@
1/*
2 * P5020 DS Setup
3 *
4 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
5 *
6 * Copyright 2009-2010 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/kdev_t.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/phy.h>
20
21#include <asm/system.h>
22#include <asm/time.h>
23#include <asm/machdep.h>
24#include <asm/pci-bridge.h>
25#include <mm/mmu_decl.h>
26#include <asm/prom.h>
27#include <asm/udbg.h>
28#include <asm/mpic.h>
29
30#include <linux/of_platform.h>
31#include <sysdev/fsl_soc.h>
32#include <sysdev/fsl_pci.h>
33
34#include "corenet_ds.h"
35
36/*
37 * Called very early, device-tree isn't unflattened
38 */
39static int __init p5020_ds_probe(void)
40{
41 unsigned long root = of_get_flat_dt_root();
42
43 return of_flat_dt_is_compatible(root, "fsl,P5020DS");
44}
45
46define_machine(p5020_ds) {
47 .name = "P5020 DS",
48 .probe = p5020_ds_probe,
49 .setup_arch = corenet_ds_setup_arch,
50 .init_IRQ = corenet_ds_pic_init,
51#ifdef CONFIG_PCI
52 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
53#endif
54/* coreint doesn't play nice with lazy EE, use legacy mpic for now */
55#ifdef CONFIG_PPC64
56 .get_irq = mpic_get_irq,
57#else
58 .get_irq = mpic_get_coreint_irq,
59#endif
60 .restart = fsl_rstcr_restart,
61 .calibrate_decr = generic_calibrate_decr,
62 .progress = udbg_progress,
63};
64
65machine_device_initcall(p5020_ds, corenet_ds_publish_devices);
66
67#ifdef CONFIG_SWIOTLB
68machine_arch_initcall(p5020_ds, swiotlb_setup_bus_notifier);
69#endif
diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c
index bd38b6a240de..5c91a992f02b 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -16,6 +16,7 @@
16#include <linux/delay.h> 16#include <linux/delay.h>
17#include <linux/of.h> 17#include <linux/of.h>
18#include <linux/kexec.h> 18#include <linux/kexec.h>
19#include <linux/highmem.h>
19 20
20#include <asm/machdep.h> 21#include <asm/machdep.h>
21#include <asm/pgtable.h> 22#include <asm/pgtable.h>
@@ -121,19 +122,15 @@ struct smp_ops_t smp_85xx_ops = {
121}; 122};
122 123
123#ifdef CONFIG_KEXEC 124#ifdef CONFIG_KEXEC
124static int kexec_down_cpus = 0; 125atomic_t kexec_down_cpus = ATOMIC_INIT(0);
125 126
126void mpc85xx_smp_kexec_cpu_down(int crash_shutdown, int secondary) 127void mpc85xx_smp_kexec_cpu_down(int crash_shutdown, int secondary)
127{ 128{
128 mpic_teardown_this_cpu(1); 129 local_irq_disable();
129
130 /* When crashing, this gets called on all CPU's we only
131 * take down the non-boot cpus */
132 if (smp_processor_id() != boot_cpuid)
133 {
134 local_irq_disable();
135 kexec_down_cpus++;
136 130
131 if (secondary) {
132 atomic_inc(&kexec_down_cpus);
133 /* loop forever */
137 while (1); 134 while (1);
138 } 135 }
139} 136}
@@ -144,16 +141,65 @@ static void mpc85xx_smp_kexec_down(void *arg)
144 ppc_md.kexec_cpu_down(0,1); 141 ppc_md.kexec_cpu_down(0,1);
145} 142}
146 143
147static void mpc85xx_smp_machine_kexec(struct kimage *image) 144static void map_and_flush(unsigned long paddr)
145{
146 struct page *page = pfn_to_page(paddr >> PAGE_SHIFT);
147 unsigned long kaddr = (unsigned long)kmap(page);
148
149 flush_dcache_range(kaddr, kaddr + PAGE_SIZE);
150 kunmap(page);
151}
152
153/**
154 * Before we reset the other cores, we need to flush relevant cache
155 * out to memory so we don't get anything corrupted, some of these flushes
156 * are performed out of an overabundance of caution as interrupts are not
157 * disabled yet and we can switch cores
158 */
159static void mpc85xx_smp_flush_dcache_kexec(struct kimage *image)
148{ 160{
149 int timeout = 2000; 161 kimage_entry_t *ptr, entry;
162 unsigned long paddr;
150 int i; 163 int i;
151 164
152 set_cpus_allowed(current, cpumask_of_cpu(boot_cpuid)); 165 if (image->type == KEXEC_TYPE_DEFAULT) {
166 /* normal kexec images are stored in temporary pages */
167 for (ptr = &image->head; (entry = *ptr) && !(entry & IND_DONE);
168 ptr = (entry & IND_INDIRECTION) ?
169 phys_to_virt(entry & PAGE_MASK) : ptr + 1) {
170 if (!(entry & IND_DESTINATION)) {
171 map_and_flush(entry);
172 }
173 }
174 /* flush out last IND_DONE page */
175 map_and_flush(entry);
176 } else {
177 /* crash type kexec images are copied to the crash region */
178 for (i = 0; i < image->nr_segments; i++) {
179 struct kexec_segment *seg = &image->segment[i];
180 for (paddr = seg->mem; paddr < seg->mem + seg->memsz;
181 paddr += PAGE_SIZE) {
182 map_and_flush(paddr);
183 }
184 }
185 }
186
187 /* also flush the kimage struct to be passed in as well */
188 flush_dcache_range((unsigned long)image,
189 (unsigned long)image + sizeof(*image));
190}
191
192static void mpc85xx_smp_machine_kexec(struct kimage *image)
193{
194 int timeout = INT_MAX;
195 int i, num_cpus = num_present_cpus();
196
197 mpc85xx_smp_flush_dcache_kexec(image);
153 198
154 smp_call_function(mpc85xx_smp_kexec_down, NULL, 0); 199 if (image->type == KEXEC_TYPE_DEFAULT)
200 smp_call_function(mpc85xx_smp_kexec_down, NULL, 0);
155 201
156 while ( (kexec_down_cpus != (num_online_cpus() - 1)) && 202 while ( (atomic_read(&kexec_down_cpus) != (num_cpus - 1)) &&
157 ( timeout > 0 ) ) 203 ( timeout > 0 ) )
158 { 204 {
159 timeout--; 205 timeout--;
@@ -162,7 +208,7 @@ static void mpc85xx_smp_machine_kexec(struct kimage *image)
162 if ( !timeout ) 208 if ( !timeout )
163 printk(KERN_ERR "Unable to bring down secondary cpu(s)"); 209 printk(KERN_ERR "Unable to bring down secondary cpu(s)");
164 210
165 for (i = 0; i < num_present_cpus(); i++) 211 for (i = 0; i < num_cpus; i++)
166 { 212 {
167 if ( i == smp_processor_id() ) continue; 213 if ( i == smp_processor_id() ) continue;
168 mpic_reset_core(i); 214 mpic_reset_core(i);
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index d361f8119b1e..111138c55f9c 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -125,6 +125,7 @@ config 8xx
125 125
126config E500 126config E500
127 select FSL_EMB_PERFMON 127 select FSL_EMB_PERFMON
128 select PPC_FSL_BOOK3E
128 bool 129 bool
129 130
130config PPC_E500MC 131config PPC_E500MC
@@ -166,9 +167,14 @@ config BOOKE
166 167
167config FSL_BOOKE 168config FSL_BOOKE
168 bool 169 bool
169 depends on E200 || E500 170 depends on (E200 || E500) && PPC32
170 default y 171 default y
171 172
173# this is for common code between PPC32 & PPC64 FSL BOOKE
174config PPC_FSL_BOOK3E
175 bool
176 select FSL_EMB_PERFMON
177 default y if FSL_BOOKE
172 178
173config PTE_64BIT 179config PTE_64BIT
174 bool 180 bool
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index c20ad6de33ee..0bef9dacb64e 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_FSL_PMC) += fsl_pmc.o
18obj-$(CONFIG_FSL_LBC) += fsl_lbc.o 18obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
19obj-$(CONFIG_FSL_GTM) += fsl_gtm.o 19obj-$(CONFIG_FSL_GTM) += fsl_gtm.o
20obj-$(CONFIG_MPC8xxx_GPIO) += mpc8xxx_gpio.o 20obj-$(CONFIG_MPC8xxx_GPIO) += mpc8xxx_gpio.o
21obj-$(CONFIG_FSL_85XX_CACHE_SRAM) += fsl_85xx_l2ctlr.o fsl_85xx_cache_sram.o
21obj-$(CONFIG_SIMPLE_GPIO) += simple_gpio.o 22obj-$(CONFIG_SIMPLE_GPIO) += simple_gpio.o
22obj-$(CONFIG_RAPIDIO) += fsl_rio.o 23obj-$(CONFIG_RAPIDIO) += fsl_rio.o
23obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o 24obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
diff --git a/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h b/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
new file mode 100644
index 000000000000..60c9c0bd5ba2
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
@@ -0,0 +1,101 @@
1/*
2 * Copyright 2009-2010 Freescale Semiconductor, Inc
3 *
4 * QorIQ based Cache Controller Memory Mapped Registers
5 *
6 * Author: Vivek Mahajan <vivek.mahajan@freescale.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef __FSL_85XX_CACHE_CTLR_H__
24#define __FSL_85XX_CACHE_CTLR_H__
25
26#define L2CR_L2FI 0x40000000 /* L2 flash invalidate */
27#define L2CR_L2IO 0x00200000 /* L2 instruction only */
28#define L2CR_SRAM_ZERO 0x00000000 /* L2SRAM zero size */
29#define L2CR_SRAM_FULL 0x00010000 /* L2SRAM full size */
30#define L2CR_SRAM_HALF 0x00020000 /* L2SRAM half size */
31#define L2CR_SRAM_TWO_HALFS 0x00030000 /* L2SRAM two half sizes */
32#define L2CR_SRAM_QUART 0x00040000 /* L2SRAM one quarter size */
33#define L2CR_SRAM_TWO_QUARTS 0x00050000 /* L2SRAM two quarter size */
34#define L2CR_SRAM_EIGHTH 0x00060000 /* L2SRAM one eighth size */
35#define L2CR_SRAM_TWO_EIGHTH 0x00070000 /* L2SRAM two eighth size */
36
37#define L2SRAM_OPTIMAL_SZ_SHIFT 0x00000003 /* Optimum size for L2SRAM */
38
39#define L2SRAM_BAR_MSK_LO18 0xFFFFC000 /* Lower 18 bits */
40#define L2SRAM_BARE_MSK_HI4 0x0000000F /* Upper 4 bits */
41
42enum cache_sram_lock_ways {
43 LOCK_WAYS_ZERO,
44 LOCK_WAYS_EIGHTH,
45 LOCK_WAYS_TWO_EIGHTH,
46 LOCK_WAYS_HALF = 4,
47 LOCK_WAYS_FULL = 8,
48};
49
50struct mpc85xx_l2ctlr {
51 u32 ctl; /* 0x000 - L2 control */
52 u8 res1[0xC];
53 u32 ewar0; /* 0x010 - External write address 0 */
54 u32 ewarea0; /* 0x014 - External write address extended 0 */
55 u32 ewcr0; /* 0x018 - External write ctrl */
56 u8 res2[4];
57 u32 ewar1; /* 0x020 - External write address 1 */
58 u32 ewarea1; /* 0x024 - External write address extended 1 */
59 u32 ewcr1; /* 0x028 - External write ctrl 1 */
60 u8 res3[4];
61 u32 ewar2; /* 0x030 - External write address 2 */
62 u32 ewarea2; /* 0x034 - External write address extended 2 */
63 u32 ewcr2; /* 0x038 - External write ctrl 2 */
64 u8 res4[4];
65 u32 ewar3; /* 0x040 - External write address 3 */
66 u32 ewarea3; /* 0x044 - External write address extended 3 */
67 u32 ewcr3; /* 0x048 - External write ctrl 3 */
68 u8 res5[0xB4];
69 u32 srbar0; /* 0x100 - SRAM base address 0 */
70 u32 srbarea0; /* 0x104 - SRAM base addr reg ext address 0 */
71 u32 srbar1; /* 0x108 - SRAM base address 1 */
72 u32 srbarea1; /* 0x10C - SRAM base addr reg ext address 1 */
73 u8 res6[0xCF0];
74 u32 errinjhi; /* 0xE00 - Error injection mask high */
75 u32 errinjlo; /* 0xE04 - Error injection mask low */
76 u32 errinjctl; /* 0xE08 - Error injection tag/ecc control */
77 u8 res7[0x14];
78 u32 captdatahi; /* 0xE20 - Error data high capture */
79 u32 captdatalo; /* 0xE24 - Error data low capture */
80 u32 captecc; /* 0xE28 - Error syndrome */
81 u8 res8[0x14];
82 u32 errdet; /* 0xE40 - Error detect */
83 u32 errdis; /* 0xE44 - Error disable */
84 u32 errinten; /* 0xE48 - Error interrupt enable */
85 u32 errattr; /* 0xE4c - Error attribute capture */
86 u32 erradrrl; /* 0xE50 - Error address capture low */
87 u32 erradrrh; /* 0xE54 - Error address capture high */
88 u32 errctl; /* 0xE58 - Error control */
89 u8 res9[0x1A4];
90};
91
92struct sram_parameters {
93 unsigned int sram_size;
94 uint64_t sram_offset;
95};
96
97extern int instantiate_cache_sram(struct platform_device *dev,
98 struct sram_parameters sram_params);
99extern void remove_cache_sram(struct platform_device *dev);
100
101#endif /* __FSL_85XX_CACHE_CTLR_H__ */
diff --git a/arch/powerpc/sysdev/fsl_85xx_cache_sram.c b/arch/powerpc/sysdev/fsl_85xx_cache_sram.c
new file mode 100644
index 000000000000..54fb1922fe30
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_85xx_cache_sram.c
@@ -0,0 +1,159 @@
1/*
2 * Copyright 2009-2010 Freescale Semiconductor, Inc.
3 *
4 * Simple memory allocator abstraction for QorIQ (P1/P2) based Cache-SRAM
5 *
6 * Author: Vivek Mahajan <vivek.mahajan@freescale.com>
7 *
8 * This file is derived from the original work done
9 * by Sylvain Munaut for the Bestcomm SRAM allocator.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26#include <linux/kernel.h>
27#include <linux/slab.h>
28#include <linux/err.h>
29#include <linux/of_platform.h>
30#include <asm/pgtable.h>
31#include <asm/fsl_85xx_cache_sram.h>
32
33#include "fsl_85xx_cache_ctlr.h"
34
35struct mpc85xx_cache_sram *cache_sram;
36
37void *mpc85xx_cache_sram_alloc(unsigned int size,
38 phys_addr_t *phys, unsigned int align)
39{
40 unsigned long offset;
41 unsigned long flags;
42
43 if (unlikely(cache_sram == NULL))
44 return NULL;
45
46 if (!size || (size > cache_sram->size) || (align > cache_sram->size)) {
47 pr_err("%s(): size(=%x) or align(=%x) zero or too big\n",
48 __func__, size, align);
49 return NULL;
50 }
51
52 if ((align & (align - 1)) || align <= 1) {
53 pr_err("%s(): align(=%x) must be power of two and >1\n",
54 __func__, align);
55 return NULL;
56 }
57
58 spin_lock_irqsave(&cache_sram->lock, flags);
59 offset = rh_alloc_align(cache_sram->rh, size, align, NULL);
60 spin_unlock_irqrestore(&cache_sram->lock, flags);
61
62 if (IS_ERR_VALUE(offset))
63 return NULL;
64
65 *phys = cache_sram->base_phys + offset;
66
67 return (unsigned char *)cache_sram->base_virt + offset;
68}
69EXPORT_SYMBOL(mpc85xx_cache_sram_alloc);
70
71void mpc85xx_cache_sram_free(void *ptr)
72{
73 unsigned long flags;
74 BUG_ON(!ptr);
75
76 spin_lock_irqsave(&cache_sram->lock, flags);
77 rh_free(cache_sram->rh, ptr - cache_sram->base_virt);
78 spin_unlock_irqrestore(&cache_sram->lock, flags);
79}
80EXPORT_SYMBOL(mpc85xx_cache_sram_free);
81
82int __init instantiate_cache_sram(struct platform_device *dev,
83 struct sram_parameters sram_params)
84{
85 int ret = 0;
86
87 if (cache_sram) {
88 dev_err(&dev->dev, "Already initialized cache-sram\n");
89 return -EBUSY;
90 }
91
92 cache_sram = kzalloc(sizeof(struct mpc85xx_cache_sram), GFP_KERNEL);
93 if (!cache_sram) {
94 dev_err(&dev->dev, "Out of memory for cache_sram structure\n");
95 return -ENOMEM;
96 }
97
98 cache_sram->base_phys = sram_params.sram_offset;
99 cache_sram->size = sram_params.sram_size;
100
101 if (!request_mem_region(cache_sram->base_phys, cache_sram->size,
102 "fsl_85xx_cache_sram")) {
103 dev_err(&dev->dev, "%s: request memory failed\n",
104 dev->dev.of_node->full_name);
105 ret = -ENXIO;
106 goto out_free;
107 }
108
109 cache_sram->base_virt = ioremap_flags(cache_sram->base_phys,
110 cache_sram->size, _PAGE_COHERENT | PAGE_KERNEL);
111 if (!cache_sram->base_virt) {
112 dev_err(&dev->dev, "%s: ioremap_flags failed\n",
113 dev->dev.of_node->full_name);
114 ret = -ENOMEM;
115 goto out_release;
116 }
117
118 cache_sram->rh = rh_create(sizeof(unsigned int));
119 if (IS_ERR(cache_sram->rh)) {
120 dev_err(&dev->dev, "%s: Unable to create remote heap\n",
121 dev->dev.of_node->full_name);
122 ret = PTR_ERR(cache_sram->rh);
123 goto out_unmap;
124 }
125
126 rh_attach_region(cache_sram->rh, 0, cache_sram->size);
127 spin_lock_init(&cache_sram->lock);
128
129 dev_info(&dev->dev, "[base:0x%llx, size:0x%x] configured and loaded\n",
130 (unsigned long long)cache_sram->base_phys, cache_sram->size);
131
132 return 0;
133
134out_unmap:
135 iounmap(cache_sram->base_virt);
136
137out_release:
138 release_mem_region(cache_sram->base_phys, cache_sram->size);
139
140out_free:
141 kfree(cache_sram);
142 return ret;
143}
144
145void remove_cache_sram(struct platform_device *dev)
146{
147 BUG_ON(!cache_sram);
148
149 rh_detach_region(cache_sram->rh, 0, cache_sram->size);
150 rh_destroy(cache_sram->rh);
151
152 iounmap(cache_sram->base_virt);
153 release_mem_region(cache_sram->base_phys, cache_sram->size);
154
155 kfree(cache_sram);
156 cache_sram = NULL;
157
158 dev_info(&dev->dev, "MPC85xx Cache-SRAM driver unloaded\n");
159}
diff --git a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
new file mode 100644
index 000000000000..cc8d6556d799
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
@@ -0,0 +1,231 @@
1/*
2 * Copyright 2009-2010 Freescale Semiconductor, Inc.
3 *
4 * QorIQ (P1/P2) L2 controller init for Cache-SRAM instantiation
5 *
6 * Author: Vivek Mahajan <vivek.mahajan@freescale.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/kernel.h>
24#include <linux/of_platform.h>
25#include <asm/io.h>
26
27#include "fsl_85xx_cache_ctlr.h"
28
29static char *sram_size;
30static char *sram_offset;
31struct mpc85xx_l2ctlr __iomem *l2ctlr;
32
33static long get_cache_sram_size(void)
34{
35 unsigned long val;
36
37 if (!sram_size || (strict_strtoul(sram_size, 0, &val) < 0))
38 return -EINVAL;
39
40 return val;
41}
42
43static long get_cache_sram_offset(void)
44{
45 unsigned long val;
46
47 if (!sram_offset || (strict_strtoul(sram_offset, 0, &val) < 0))
48 return -EINVAL;
49
50 return val;
51}
52
53static int __init get_size_from_cmdline(char *str)
54{
55 if (!str)
56 return 0;
57
58 sram_size = str;
59 return 1;
60}
61
62static int __init get_offset_from_cmdline(char *str)
63{
64 if (!str)
65 return 0;
66
67 sram_offset = str;
68 return 1;
69}
70
71__setup("cache-sram-size=", get_size_from_cmdline);
72__setup("cache-sram-offset=", get_offset_from_cmdline);
73
74static int __devinit mpc85xx_l2ctlr_of_probe(struct platform_device *dev,
75 const struct of_device_id *match)
76{
77 long rval;
78 unsigned int rem;
79 unsigned char ways;
80 const unsigned int *prop;
81 unsigned int l2cache_size;
82 struct sram_parameters sram_params;
83
84 if (!dev->dev.of_node) {
85 dev_err(&dev->dev, "Device's OF-node is NULL\n");
86 return -EINVAL;
87 }
88
89 prop = of_get_property(dev->dev.of_node, "cache-size", NULL);
90 if (!prop) {
91 dev_err(&dev->dev, "Missing L2 cache-size\n");
92 return -EINVAL;
93 }
94 l2cache_size = *prop;
95
96 sram_params.sram_size = get_cache_sram_size();
97 if (sram_params.sram_size <= 0) {
98 dev_err(&dev->dev,
99 "Entire L2 as cache, Aborting Cache-SRAM stuff\n");
100 return -EINVAL;
101 }
102
103 sram_params.sram_offset = get_cache_sram_offset();
104 if (sram_params.sram_offset <= 0) {
105 dev_err(&dev->dev,
106 "Entire L2 as cache, provide a valid sram offset\n");
107 return -EINVAL;
108 }
109
110
111 rem = l2cache_size % sram_params.sram_size;
112 ways = LOCK_WAYS_FULL * sram_params.sram_size / l2cache_size;
113 if (rem || (ways & (ways - 1))) {
114 dev_err(&dev->dev, "Illegal cache-sram-size in command line\n");
115 return -EINVAL;
116 }
117
118 l2ctlr = of_iomap(dev->dev.of_node, 0);
119 if (!l2ctlr) {
120 dev_err(&dev->dev, "Can't map L2 controller\n");
121 return -EINVAL;
122 }
123
124 /*
125 * Write bits[0-17] to srbar0
126 */
127 out_be32(&l2ctlr->srbar0,
128 sram_params.sram_offset & L2SRAM_BAR_MSK_LO18);
129
130 /*
131 * Write bits[18-21] to srbare0
132 */
133#ifdef CONFIG_PHYS_64BIT
134 out_be32(&l2ctlr->srbarea0,
135 (sram_params.sram_offset >> 32) & L2SRAM_BARE_MSK_HI4);
136#endif
137
138 clrsetbits_be32(&l2ctlr->ctl, L2CR_L2E, L2CR_L2FI);
139
140 switch (ways) {
141 case LOCK_WAYS_EIGHTH:
142 setbits32(&l2ctlr->ctl,
143 L2CR_L2E | L2CR_L2FI | L2CR_SRAM_EIGHTH);
144 break;
145
146 case LOCK_WAYS_TWO_EIGHTH:
147 setbits32(&l2ctlr->ctl,
148 L2CR_L2E | L2CR_L2FI | L2CR_SRAM_QUART);
149 break;
150
151 case LOCK_WAYS_HALF:
152 setbits32(&l2ctlr->ctl,
153 L2CR_L2E | L2CR_L2FI | L2CR_SRAM_HALF);
154 break;
155
156 case LOCK_WAYS_FULL:
157 default:
158 setbits32(&l2ctlr->ctl,
159 L2CR_L2E | L2CR_L2FI | L2CR_SRAM_FULL);
160 break;
161 }
162 eieio();
163
164 rval = instantiate_cache_sram(dev, sram_params);
165 if (rval < 0) {
166 dev_err(&dev->dev, "Can't instantiate Cache-SRAM\n");
167 iounmap(l2ctlr);
168 return -EINVAL;
169 }
170
171 return 0;
172}
173
174static int __devexit mpc85xx_l2ctlr_of_remove(struct platform_device *dev)
175{
176 BUG_ON(!l2ctlr);
177
178 iounmap(l2ctlr);
179 remove_cache_sram(dev);
180 dev_info(&dev->dev, "MPC85xx L2 controller unloaded\n");
181
182 return 0;
183}
184
185static struct of_device_id mpc85xx_l2ctlr_of_match[] = {
186 {
187 .compatible = "fsl,p2020-l2-cache-controller",
188 },
189 {
190 .compatible = "fsl,p2010-l2-cache-controller",
191 },
192 {
193 .compatible = "fsl,p1020-l2-cache-controller",
194 },
195 {
196 .compatible = "fsl,p1011-l2-cache-controller",
197 },
198 {
199 .compatible = "fsl,p1013-l2-cache-controller",
200 },
201 {
202 .compatible = "fsl,p1022-l2-cache-controller",
203 },
204 {},
205};
206
207static struct of_platform_driver mpc85xx_l2ctlr_of_platform_driver = {
208 .driver = {
209 .name = "fsl-l2ctlr",
210 .owner = THIS_MODULE,
211 .of_match_table = mpc85xx_l2ctlr_of_match,
212 },
213 .probe = mpc85xx_l2ctlr_of_probe,
214 .remove = __devexit_p(mpc85xx_l2ctlr_of_remove),
215};
216
217static __init int mpc85xx_l2ctlr_of_init(void)
218{
219 return of_register_platform_driver(&mpc85xx_l2ctlr_of_platform_driver);
220}
221
222static void __exit mpc85xx_l2ctlr_of_exit(void)
223{
224 of_unregister_platform_driver(&mpc85xx_l2ctlr_of_platform_driver);
225}
226
227subsys_initcall(mpc85xx_l2ctlr_of_init);
228module_exit(mpc85xx_l2ctlr_of_exit);
229
230MODULE_DESCRIPTION("Freescale MPC85xx L2 controller init");
231MODULE_LICENSE("GPL v2");
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index 87991d3abbab..20cdcd2b0eed 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -24,6 +24,7 @@
24#include <asm/ppc-pci.h> 24#include <asm/ppc-pci.h>
25#include <asm/mpic.h> 25#include <asm/mpic.h>
26#include "fsl_msi.h" 26#include "fsl_msi.h"
27#include "fsl_pci.h"
27 28
28LIST_HEAD(msi_head); 29LIST_HEAD(msi_head);
29 30
@@ -125,13 +126,11 @@ static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
125{ 126{
126 struct fsl_msi *msi_data = fsl_msi_data; 127 struct fsl_msi *msi_data = fsl_msi_data;
127 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 128 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
128 u32 base = 0; 129 u64 base = fsl_pci_immrbar_base(hose);
129 130
130 pci_bus_read_config_dword(hose->bus, 131 msg->address_lo = msi_data->msi_addr_lo + lower_32_bits(base);
131 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base); 132 msg->address_hi = msi_data->msi_addr_hi + upper_32_bits(base);
132 133
133 msg->address_lo = msi_data->msi_addr_lo + base;
134 msg->address_hi = msi_data->msi_addr_hi;
135 msg->data = hwirq; 134 msg->data = hwirq;
136 135
137 pr_debug("%s: allocated srs: %d, ibs: %d\n", 136 pr_debug("%s: allocated srs: %d, ibs: %d\n",
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 4ae933225251..818f7c6c8fa1 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC83xx/85xx/86xx PCI/PCIE support routing. 2 * MPC83xx/85xx/86xx PCI/PCIE support routing.
3 * 3 *
4 * Copyright 2007-2009 Freescale Semiconductor, Inc. 4 * Copyright 2007-2010 Freescale Semiconductor, Inc.
5 * Copyright 2008-2009 MontaVista Software, Inc. 5 * Copyright 2008-2009 MontaVista Software, Inc.
6 * 6 *
7 * Initial author: Xianghua Xiao <x.xiao@freescale.com> 7 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
@@ -34,7 +34,7 @@
34#include <sysdev/fsl_soc.h> 34#include <sysdev/fsl_soc.h>
35#include <sysdev/fsl_pci.h> 35#include <sysdev/fsl_pci.h>
36 36
37static int fsl_pcie_bus_fixup; 37static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
38 38
39static void __init quirk_fsl_pcie_header(struct pci_dev *dev) 39static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
40{ 40{
@@ -407,10 +407,18 @@ DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2010E, quirk_fsl_pcie_header);
407DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2010, quirk_fsl_pcie_header); 407DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2010, quirk_fsl_pcie_header);
408DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020E, quirk_fsl_pcie_header); 408DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020E, quirk_fsl_pcie_header);
409DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020, quirk_fsl_pcie_header); 409DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020, quirk_fsl_pcie_header);
410DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2040E, quirk_fsl_pcie_header);
411DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2040, quirk_fsl_pcie_header);
412DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P3041E, quirk_fsl_pcie_header);
413DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P3041, quirk_fsl_pcie_header);
410DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4040E, quirk_fsl_pcie_header); 414DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4040E, quirk_fsl_pcie_header);
411DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4040, quirk_fsl_pcie_header); 415DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4040, quirk_fsl_pcie_header);
412DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4080E, quirk_fsl_pcie_header); 416DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4080E, quirk_fsl_pcie_header);
413DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4080, quirk_fsl_pcie_header); 417DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4080, quirk_fsl_pcie_header);
418DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5010E, quirk_fsl_pcie_header);
419DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5010, quirk_fsl_pcie_header);
420DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5020E, quirk_fsl_pcie_header);
421DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5020, quirk_fsl_pcie_header);
414#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */ 422#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
415 423
416#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x) 424#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
@@ -430,6 +438,13 @@ struct mpc83xx_pcie_priv {
430 u32 dev_base; 438 u32 dev_base;
431}; 439};
432 440
441struct pex_inbound_window {
442 u32 ar;
443 u32 tar;
444 u32 barl;
445 u32 barh;
446};
447
433/* 448/*
434 * With the convention of u-boot, the PCIE outbound window 0 serves 449 * With the convention of u-boot, the PCIE outbound window 0 serves
435 * as configuration transactions outbound. 450 * as configuration transactions outbound.
@@ -437,6 +452,8 @@ struct mpc83xx_pcie_priv {
437#define PEX_OUTWIN0_BAR 0xCA4 452#define PEX_OUTWIN0_BAR 0xCA4
438#define PEX_OUTWIN0_TAL 0xCA8 453#define PEX_OUTWIN0_TAL 0xCA8
439#define PEX_OUTWIN0_TAH 0xCAC 454#define PEX_OUTWIN0_TAH 0xCAC
455#define PEX_RC_INWIN_BASE 0xE60
456#define PEX_RCIWARn_EN 0x1
440 457
441static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn) 458static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
442{ 459{
@@ -604,6 +621,8 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
604 const int *bus_range; 621 const int *bus_range;
605 int primary; 622 int primary;
606 623
624 is_mpc83xx_pci = 1;
625
607 if (!of_device_is_available(dev)) { 626 if (!of_device_is_available(dev)) {
608 pr_warning("%s: disabled by the firmware.\n", 627 pr_warning("%s: disabled by the firmware.\n",
609 dev->full_name); 628 dev->full_name);
@@ -683,3 +702,40 @@ err0:
683 return ret; 702 return ret;
684} 703}
685#endif /* CONFIG_PPC_83xx */ 704#endif /* CONFIG_PPC_83xx */
705
706u64 fsl_pci_immrbar_base(struct pci_controller *hose)
707{
708#ifdef CONFIG_PPC_83xx
709 if (is_mpc83xx_pci) {
710 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
711 struct pex_inbound_window *in;
712 int i;
713
714 /* Walk the Root Complex Inbound windows to match IMMR base */
715 in = pcie->cfg_type0 + PEX_RC_INWIN_BASE;
716 for (i = 0; i < 4; i++) {
717 /* not enabled, skip */
718 if (!in_le32(&in[i].ar) & PEX_RCIWARn_EN)
719 continue;
720
721 if (get_immrbase() == in_le32(&in[i].tar))
722 return (u64)in_le32(&in[i].barh) << 32 |
723 in_le32(&in[i].barl);
724 }
725
726 printk(KERN_WARNING "could not find PCI BAR matching IMMR\n");
727 }
728#endif
729
730#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
731 if (!is_mpc83xx_pci) {
732 u32 base;
733
734 pci_bus_read_config_dword(hose->bus,
735 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
736 return base;
737 }
738#endif
739
740 return 0;
741}
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index a9d8bbebed80..8ad72a11f77b 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -88,6 +88,7 @@ struct ccsr_pci {
88extern int fsl_add_bridge(struct device_node *dev, int is_primary); 88extern int fsl_add_bridge(struct device_node *dev, int is_primary);
89extern void fsl_pcibios_fixup_bus(struct pci_bus *bus); 89extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
90extern int mpc83xx_add_bridge(struct device_node *dev); 90extern int mpc83xx_add_bridge(struct device_node *dev);
91u64 fsl_pci_immrbar_base(struct pci_controller *hose);
91 92
92#endif /* __POWERPC_FSL_PCI_H */ 93#endif /* __POWERPC_FSL_PCI_H */
93#endif /* __KERNEL__ */ 94#endif /* __KERNEL__ */
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index 3017532319c8..412763672d23 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -117,44 +117,59 @@ struct rio_atmu_regs {
117}; 117};
118 118
119struct rio_msg_regs { 119struct rio_msg_regs {
120 u32 omr; 120 u32 omr; /* 0xD_3000 - Outbound message 0 mode register */
121 u32 osr; 121 u32 osr; /* 0xD_3004 - Outbound message 0 status register */
122 u32 pad1; 122 u32 pad1;
123 u32 odqdpar; 123 u32 odqdpar; /* 0xD_300C - Outbound message 0 descriptor queue
124 dequeue pointer address register */
124 u32 pad2; 125 u32 pad2;
125 u32 osar; 126 u32 osar; /* 0xD_3014 - Outbound message 0 source address
126 u32 odpr; 127 register */
127 u32 odatr; 128 u32 odpr; /* 0xD_3018 - Outbound message 0 destination port
128 u32 odcr; 129 register */
130 u32 odatr; /* 0xD_301C - Outbound message 0 destination attributes
131 Register*/
132 u32 odcr; /* 0xD_3020 - Outbound message 0 double-word count
133 register */
129 u32 pad3; 134 u32 pad3;
130 u32 odqepar; 135 u32 odqepar; /* 0xD_3028 - Outbound message 0 descriptor queue
136 enqueue pointer address register */
131 u32 pad4[13]; 137 u32 pad4[13];
132 u32 imr; 138 u32 imr; /* 0xD_3060 - Inbound message 0 mode register */
133 u32 isr; 139 u32 isr; /* 0xD_3064 - Inbound message 0 status register */
134 u32 pad5; 140 u32 pad5;
135 u32 ifqdpar; 141 u32 ifqdpar; /* 0xD_306C - Inbound message 0 frame queue dequeue
142 pointer address register*/
136 u32 pad6; 143 u32 pad6;
137 u32 ifqepar; 144 u32 ifqepar; /* 0xD_3074 - Inbound message 0 frame queue enqueue
145 pointer address register */
138 u32 pad7[226]; 146 u32 pad7[226];
139 u32 odmr; 147 u32 odmr; /* 0xD_3400 - Outbound doorbell mode register */
140 u32 odsr; 148 u32 odsr; /* 0xD_3404 - Outbound doorbell status register */
141 u32 res0[4]; 149 u32 res0[4];
142 u32 oddpr; 150 u32 oddpr; /* 0xD_3418 - Outbound doorbell destination port
143 u32 oddatr; 151 register */
152 u32 oddatr; /* 0xD_341c - Outbound doorbell destination attributes
153 register */
144 u32 res1[3]; 154 u32 res1[3];
145 u32 odretcr; 155 u32 odretcr; /* 0xD_342C - Outbound doorbell retry error threshold
156 configuration register */
146 u32 res2[12]; 157 u32 res2[12];
147 u32 dmr; 158 u32 dmr; /* 0xD_3460 - Inbound doorbell mode register */
148 u32 dsr; 159 u32 dsr; /* 0xD_3464 - Inbound doorbell status register */
149 u32 pad8; 160 u32 pad8;
150 u32 dqdpar; 161 u32 dqdpar; /* 0xD_346C - Inbound doorbell queue dequeue Pointer
162 address register */
151 u32 pad9; 163 u32 pad9;
152 u32 dqepar; 164 u32 dqepar; /* 0xD_3474 - Inbound doorbell Queue enqueue pointer
165 address register */
153 u32 pad10[26]; 166 u32 pad10[26];
154 u32 pwmr; 167 u32 pwmr; /* 0xD_34E0 - Inbound port-write mode register */
155 u32 pwsr; 168 u32 pwsr; /* 0xD_34E4 - Inbound port-write status register */
156 u32 epwqbar; 169 u32 epwqbar; /* 0xD_34E8 - Extended Port-Write Queue Base Address
157 u32 pwqbar; 170 register */
171 u32 pwqbar; /* 0xD_34EC - Inbound port-write queue base address
172 register */
158}; 173};
159 174
160struct rio_tx_desc { 175struct rio_tx_desc {
diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c
index b91f7acdda6f..6c67d9ebf166 100644
--- a/arch/powerpc/sysdev/fsl_soc.c
+++ b/arch/powerpc/sysdev/fsl_soc.c
@@ -378,17 +378,23 @@ static __be32 __iomem *rstcr;
378static int __init setup_rstcr(void) 378static int __init setup_rstcr(void)
379{ 379{
380 struct device_node *np; 380 struct device_node *np;
381 np = of_find_node_by_name(NULL, "global-utilities"); 381
382 if ((np && of_get_property(np, "fsl,has-rstcr", NULL))) { 382 for_each_node_by_name(np, "global-utilities") {
383 rstcr = of_iomap(np, 0) + 0xb0; 383 if ((of_get_property(np, "fsl,has-rstcr", NULL))) {
384 if (!rstcr) 384 rstcr = of_iomap(np, 0) + 0xb0;
385 printk (KERN_EMERG "Error: reset control register " 385 if (!rstcr)
386 "not mapped!\n"); 386 printk (KERN_ERR "Error: reset control "
387 } else if (ppc_md.restart == fsl_rstcr_restart) 387 "register not mapped!\n");
388 break;
389 }
390 }
391
392 if (!rstcr && ppc_md.restart == fsl_rstcr_restart)
388 printk(KERN_ERR "No RSTCR register, warm reboot won't work\n"); 393 printk(KERN_ERR "No RSTCR register, warm reboot won't work\n");
389 394
390 if (np) 395 if (np)
391 of_node_put(np); 396 of_node_put(np);
397
392 return 0; 398 return 0;
393} 399}
394 400
diff --git a/arch/powerpc/sysdev/mpc8xxx_gpio.c b/arch/powerpc/sysdev/mpc8xxx_gpio.c
index 2b69084d0f0c..c0ea05e87f1d 100644
--- a/arch/powerpc/sysdev/mpc8xxx_gpio.c
+++ b/arch/powerpc/sysdev/mpc8xxx_gpio.c
@@ -330,6 +330,9 @@ static int __init mpc8xxx_add_gpiochips(void)
330 for_each_compatible_node(np, NULL, "fsl,mpc8610-gpio") 330 for_each_compatible_node(np, NULL, "fsl,mpc8610-gpio")
331 mpc8xxx_add_controller(np); 331 mpc8xxx_add_controller(np);
332 332
333 for_each_compatible_node(np, NULL, "fsl,qoriq-gpio")
334 mpc8xxx_add_controller(np);
335
333 return 0; 336 return 0;
334} 337}
335arch_initcall(mpc8xxx_add_gpiochips); 338arch_initcall(mpc8xxx_add_gpiochips);
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 24efd8ea41bb..c356146bd712 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -957,12 +957,32 @@ config PIKA_WDT
957 the Warp platform. 957 the Warp platform.
958 958
959config BOOKE_WDT 959config BOOKE_WDT
960 bool "PowerPC Book-E Watchdog Timer" 960 tristate "PowerPC Book-E Watchdog Timer"
961 depends on BOOKE || 4xx 961 depends on BOOKE || 4xx
962 ---help--- 962 ---help---
963 Watchdog driver for PowerPC Book-E chips, such as the Freescale
964 MPC85xx SOCs and the IBM PowerPC 440.
965
963 Please see Documentation/watchdog/watchdog-api.txt for 966 Please see Documentation/watchdog/watchdog-api.txt for
964 more information. 967 more information.
965 968
969config BOOKE_WDT_DEFAULT_TIMEOUT
970 int "PowerPC Book-E Watchdog Timer Default Timeout"
971 depends on BOOKE_WDT
972 default 38 if FSL_BOOKE
973 range 0 63 if FSL_BOOKE
974 default 3 if !FSL_BOOKE
975 range 0 3 if !FSL_BOOKE
976 help
977 Select the default watchdog timer period to be used by the PowerPC
978 Book-E watchdog driver. A watchdog "event" occurs when the bit
979 position represented by this number transitions from zero to one.
980
981 For Freescale Book-E processors, this is a number between 0 and 63.
982 For other Book-E processors, this is a number between 0 and 3.
983
984 The value can be overidden by the wdt_period command-line parameter.
985
966# PPC64 Architecture 986# PPC64 Architecture
967 987
968config WATCHDOG_RTAS 988config WATCHDOG_RTAS
diff --git a/drivers/watchdog/booke_wdt.c b/drivers/watchdog/booke_wdt.c
index 3d49671cdf5a..d11ffb091b0d 100644
--- a/drivers/watchdog/booke_wdt.c
+++ b/drivers/watchdog/booke_wdt.c
@@ -4,7 +4,7 @@
4 * Author: Matthew McClintock 4 * Author: Matthew McClintock
5 * Maintainer: Kumar Gala <galak@kernel.crashing.org> 5 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
6 * 6 *
7 * Copyright 2005, 2008 Freescale Semiconductor Inc. 7 * Copyright 2005, 2008, 2010 Freescale Semiconductor Inc.
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify it 9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the 10 * under the terms of the GNU General Public License as published by the
@@ -33,14 +33,8 @@
33 * occur, and the final time the board will reset. 33 * occur, and the final time the board will reset.
34 */ 34 */
35 35
36#ifdef CONFIG_FSL_BOOKE
37#define WDT_PERIOD_DEFAULT 38 /* Ex. wdt_period=28 bus=333Mhz,reset=~40sec */
38#else
39#define WDT_PERIOD_DEFAULT 3 /* Refer to the PPC40x and PPC4xx manuals */
40#endif /* for timing information */
41
42u32 booke_wdt_enabled; 36u32 booke_wdt_enabled;
43u32 booke_wdt_period = WDT_PERIOD_DEFAULT; 37u32 booke_wdt_period = CONFIG_BOOKE_WDT_DEFAULT_TIMEOUT;
44 38
45#ifdef CONFIG_FSL_BOOKE 39#ifdef CONFIG_FSL_BOOKE
46#define WDTP(x) ((((x)&0x3)<<30)|(((x)&0x3c)<<15)) 40#define WDTP(x) ((((x)&0x3)<<30)|(((x)&0x3c)<<15))
@@ -114,6 +108,27 @@ static void __booke_wdt_enable(void *data)
114 mtspr(SPRN_TCR, val); 108 mtspr(SPRN_TCR, val);
115} 109}
116 110
111/**
112 * booke_wdt_disable - disable the watchdog on the given CPU
113 *
114 * This function is called on each CPU. It disables the watchdog on that CPU.
115 *
116 * TCR[WRC] cannot be changed once it has been set to non-zero, but we can
117 * effectively disable the watchdog by setting its period to the maximum value.
118 */
119static void __booke_wdt_disable(void *data)
120{
121 u32 val;
122
123 val = mfspr(SPRN_TCR);
124 val &= ~(TCR_WIE | WDTP_MASK);
125 mtspr(SPRN_TCR, val);
126
127 /* clear status to make sure nothing is pending */
128 __booke_wdt_ping(NULL);
129
130}
131
117static ssize_t booke_wdt_write(struct file *file, const char __user *buf, 132static ssize_t booke_wdt_write(struct file *file, const char __user *buf,
118 size_t count, loff_t *ppos) 133 size_t count, loff_t *ppos)
119{ 134{
@@ -193,12 +208,21 @@ static int booke_wdt_open(struct inode *inode, struct file *file)
193 return nonseekable_open(inode, file); 208 return nonseekable_open(inode, file);
194} 209}
195 210
211static int booke_wdt_release(struct inode *inode, struct file *file)
212{
213 on_each_cpu(__booke_wdt_disable, NULL, 0);
214 booke_wdt_enabled = 0;
215
216 return 0;
217}
218
196static const struct file_operations booke_wdt_fops = { 219static const struct file_operations booke_wdt_fops = {
197 .owner = THIS_MODULE, 220 .owner = THIS_MODULE,
198 .llseek = no_llseek, 221 .llseek = no_llseek,
199 .write = booke_wdt_write, 222 .write = booke_wdt_write,
200 .unlocked_ioctl = booke_wdt_ioctl, 223 .unlocked_ioctl = booke_wdt_ioctl,
201 .open = booke_wdt_open, 224 .open = booke_wdt_open,
225 .release = booke_wdt_release,
202}; 226};
203 227
204static struct miscdevice booke_wdt_miscdev = { 228static struct miscdevice booke_wdt_miscdev = {
@@ -237,4 +261,9 @@ static int __init booke_wdt_init(void)
237 261
238 return ret; 262 return ret;
239} 263}
240device_initcall(booke_wdt_init); 264
265module_init(booke_wdt_init);
266module_exit(booke_wdt_exit);
267
268MODULE_DESCRIPTION("PowerPC Book-E watchdog driver");
269MODULE_LICENSE("GPL");
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 570fddeb0388..f69dfe5e01ef 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2315,6 +2315,14 @@
2315#define PCI_DEVICE_ID_P4080 0x0401 2315#define PCI_DEVICE_ID_P4080 0x0401
2316#define PCI_DEVICE_ID_P4040E 0x0408 2316#define PCI_DEVICE_ID_P4040E 0x0408
2317#define PCI_DEVICE_ID_P4040 0x0409 2317#define PCI_DEVICE_ID_P4040 0x0409
2318#define PCI_DEVICE_ID_P2040E 0x0410
2319#define PCI_DEVICE_ID_P2040 0x0411
2320#define PCI_DEVICE_ID_P3041E 0x041E
2321#define PCI_DEVICE_ID_P3041 0x041F
2322#define PCI_DEVICE_ID_P5020E 0x0420
2323#define PCI_DEVICE_ID_P5020 0x0421
2324#define PCI_DEVICE_ID_P5010E 0x0428
2325#define PCI_DEVICE_ID_P5010 0x0429
2318#define PCI_DEVICE_ID_MPC8641 0x7010 2326#define PCI_DEVICE_ID_MPC8641 0x7010
2319#define PCI_DEVICE_ID_MPC8641D 0x7011 2327#define PCI_DEVICE_ID_MPC8641D 0x7011
2320#define PCI_DEVICE_ID_MPC8610 0x7018 2328#define PCI_DEVICE_ID_MPC8610 0x7018
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-12 12:26:03 -0400