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-rw-r--r--arch/powerpc/boot/4xx.c13
1 files changed, 6 insertions, 7 deletions
diff --git a/arch/powerpc/boot/4xx.c b/arch/powerpc/boot/4xx.c
index 1a83efe274c1..33f25b671340 100644
--- a/arch/powerpc/boot/4xx.c
+++ b/arch/powerpc/boot/4xx.c
@@ -243,7 +243,8 @@ void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1)
243 *emac1 = EMAC_RESET; 243 *emac1 = EMAC_RESET;
244 244
245 mtdcr(DCRN_MAL0_CFG, MAL_RESET); 245 mtdcr(DCRN_MAL0_CFG, MAL_RESET);
246 while (mfdcr(DCRN_MAL0_CFG) & MAL_RESET) {}; 246 while (mfdcr(DCRN_MAL0_CFG) & MAL_RESET)
247 ; /* loop until reset takes effect */
247} 248}
248 249
249/* Read 4xx EBC bus bridge registers to get mappings of the peripheral 250/* Read 4xx EBC bus bridge registers to get mappings of the peripheral
@@ -515,19 +516,17 @@ void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk)
515 opb = plb / opdv; 516 opb = plb / opdv;
516 ebc = plb / epdv; 517 ebc = plb / epdv;
517 518
518 if (cpc0_cr0 & 0x80) { 519 if (cpc0_cr0 & 0x80)
519 /* uart0 uses the external clock */ 520 /* uart0 uses the external clock */
520 uart0 = ser_clk; 521 uart0 = ser_clk;
521 } else { 522 else
522 uart0 = cpu / udiv; 523 uart0 = cpu / udiv;
523 }
524 524
525 if (cpc0_cr0 & 0x40) { 525 if (cpc0_cr0 & 0x40)
526 /* uart1 uses the external clock */ 526 /* uart1 uses the external clock */
527 uart1 = ser_clk; 527 uart1 = ser_clk;
528 } else { 528 else
529 uart1 = cpu / udiv; 529 uart1 = cpu / udiv;
530 }
531 530
532 /* setup the timebase clock to tick at the cpu frequency */ 531 /* setup the timebase clock to tick at the cpu frequency */
533 cpc0_cr1 = cpc0_cr1 & ~0x00800000; 532 cpc0_cr1 = cpc0_cr1 & ~0x00800000;