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-rw-r--r--Documentation/devicetree/bindings/clock/exynos5420-clock.txt3
-rw-r--r--drivers/clk/samsung/clk-exynos5420.c309
-rw-r--r--include/dt-bindings/clock/exynos5420.h4
3 files changed, 259 insertions, 57 deletions
diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
index ca88c97a8562..d54f42cf0440 100644
--- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
@@ -1,12 +1,13 @@
1* Samsung Exynos5420 Clock Controller 1* Samsung Exynos5420 Clock Controller
2 2
3The Exynos5420 clock controller generates and supplies clock to various 3The Exynos5420 clock controller generates and supplies clock to various
4controllers within the Exynos5420 SoC. 4controllers within the Exynos5420 SoC and for the Exynos5800 SoC.
5 5
6Required Properties: 6Required Properties:
7 7
8- compatible: should be one of the following. 8- compatible: should be one of the following.
9 - "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC. 9 - "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC.
10 - "samsung,exynos5800-clock" - controller compatible with Exynos5800 SoC.
10 11
11- reg: physical base address of the controller and length of memory mapped 12- reg: physical base address of the controller and length of memory mapped
12 region. 13 region.
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 1c3674ecc0dc..9d7d7eed03fd 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -57,15 +57,19 @@
57#define SRC_TOP5 0x10214 57#define SRC_TOP5 0x10214
58#define SRC_TOP6 0x10218 58#define SRC_TOP6 0x10218
59#define SRC_TOP7 0x1021c 59#define SRC_TOP7 0x1021c
60#define SRC_TOP8 0x10220 /* 5800 specific */
61#define SRC_TOP9 0x10224 /* 5800 specific */
60#define SRC_DISP10 0x1022c 62#define SRC_DISP10 0x1022c
61#define SRC_MAU 0x10240 63#define SRC_MAU 0x10240
62#define SRC_FSYS 0x10244 64#define SRC_FSYS 0x10244
63#define SRC_PERIC0 0x10250 65#define SRC_PERIC0 0x10250
64#define SRC_PERIC1 0x10254 66#define SRC_PERIC1 0x10254
65#define SRC_ISP 0x10270 67#define SRC_ISP 0x10270
68#define SRC_CAM 0x10274 /* 5800 specific */
66#define SRC_TOP10 0x10280 69#define SRC_TOP10 0x10280
67#define SRC_TOP11 0x10284 70#define SRC_TOP11 0x10284
68#define SRC_TOP12 0x10288 71#define SRC_TOP12 0x10288
72#define SRC_TOP13 0x1028c /* 5800 specific */
69#define SRC_MASK_TOP2 0x10308 73#define SRC_MASK_TOP2 0x10308
70#define SRC_MASK_TOP7 0x1031c 74#define SRC_MASK_TOP7 0x1031c
71#define SRC_MASK_DISP10 0x1032c 75#define SRC_MASK_DISP10 0x1032c
@@ -76,6 +80,8 @@
76#define DIV_TOP0 0x10500 80#define DIV_TOP0 0x10500
77#define DIV_TOP1 0x10504 81#define DIV_TOP1 0x10504
78#define DIV_TOP2 0x10508 82#define DIV_TOP2 0x10508
83#define DIV_TOP8 0x10520 /* 5800 specific */
84#define DIV_TOP9 0x10524 /* 5800 specific */
79#define DIV_DISP10 0x1052c 85#define DIV_DISP10 0x1052c
80#define DIV_MAU 0x10544 86#define DIV_MAU 0x10544
81#define DIV_FSYS0 0x10548 87#define DIV_FSYS0 0x10548
@@ -86,6 +92,7 @@
86#define DIV_PERIC2 0x10560 92#define DIV_PERIC2 0x10560
87#define DIV_PERIC3 0x10564 93#define DIV_PERIC3 0x10564
88#define DIV_PERIC4 0x10568 94#define DIV_PERIC4 0x10568
95#define DIV_CAM 0x10574 /* 5800 specific */
89#define SCLK_DIV_ISP0 0x10580 96#define SCLK_DIV_ISP0 0x10580
90#define SCLK_DIV_ISP1 0x10584 97#define SCLK_DIV_ISP1 0x10584
91#define DIV2_RATIO0 0x10590 98#define DIV2_RATIO0 0x10590
@@ -102,6 +109,7 @@
102#define GATE_TOP_SCLK_ISP 0x10870 109#define GATE_TOP_SCLK_ISP 0x10870
103#define GATE_IP_GSCL0 0x10910 110#define GATE_IP_GSCL0 0x10910
104#define GATE_IP_GSCL1 0x10920 111#define GATE_IP_GSCL1 0x10920
112#define GATE_IP_CAM 0x10924 /* 5800 specific */
105#define GATE_IP_MFC 0x1092c 113#define GATE_IP_MFC 0x1092c
106#define GATE_IP_DISP1 0x10928 114#define GATE_IP_DISP1 0x10928
107#define GATE_IP_G3D 0x10930 115#define GATE_IP_G3D 0x10930
@@ -123,23 +131,31 @@
123#define SRC_KFC 0x28200 131#define SRC_KFC 0x28200
124#define DIV_KFC0 0x28500 132#define DIV_KFC0 0x28500
125 133
134/* Exynos5x SoC type */
135enum exynos5x_soc {
136 EXYNOS5420,
137 EXYNOS5800,
138};
139
126/* list of PLLs */ 140/* list of PLLs */
127enum exynos5420_plls { 141enum exynos5x_plls {
128 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, 142 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll,
129 bpll, kpll, 143 bpll, kpll,
130 nr_plls /* number of PLLs */ 144 nr_plls /* number of PLLs */
131}; 145};
132 146
133static void __iomem *reg_base; 147static void __iomem *reg_base;
148static enum exynos5x_soc exynos5x_soc;
134 149
135#ifdef CONFIG_PM_SLEEP 150#ifdef CONFIG_PM_SLEEP
136static struct samsung_clk_reg_dump *exynos5420_save; 151static struct samsung_clk_reg_dump *exynos5x_save;
152static struct samsung_clk_reg_dump *exynos5800_save;
137 153
138/* 154/*
139 * list of controller registers to be saved and restored during a 155 * list of controller registers to be saved and restored during a
140 * suspend/resume cycle. 156 * suspend/resume cycle.
141 */ 157 */
142static unsigned long exynos5420_clk_regs[] __initdata = { 158static unsigned long exynos5x_clk_regs[] __initdata = {
143 SRC_CPU, 159 SRC_CPU,
144 DIV_CPU0, 160 DIV_CPU0,
145 DIV_CPU1, 161 DIV_CPU1,
@@ -222,18 +238,37 @@ static unsigned long exynos5420_clk_regs[] __initdata = {
222 DIV_KFC0, 238 DIV_KFC0,
223}; 239};
224 240
241static unsigned long exynos5800_clk_regs[] __initdata = {
242 SRC_TOP8,
243 SRC_TOP9,
244 SRC_CAM,
245 SRC_TOP1,
246 DIV_TOP8,
247 DIV_TOP9,
248 DIV_CAM,
249 GATE_IP_CAM,
250};
251
225static int exynos5420_clk_suspend(void) 252static int exynos5420_clk_suspend(void)
226{ 253{
227 samsung_clk_save(reg_base, exynos5420_save, 254 samsung_clk_save(reg_base, exynos5x_save,
228 ARRAY_SIZE(exynos5420_clk_regs)); 255 ARRAY_SIZE(exynos5x_clk_regs));
256
257 if (exynos5x_soc == EXYNOS5800)
258 samsung_clk_save(reg_base, exynos5800_save,
259 ARRAY_SIZE(exynos5800_clk_regs));
229 260
230 return 0; 261 return 0;
231} 262}
232 263
233static void exynos5420_clk_resume(void) 264static void exynos5420_clk_resume(void)
234{ 265{
235 samsung_clk_restore(reg_base, exynos5420_save, 266 samsung_clk_restore(reg_base, exynos5x_save,
236 ARRAY_SIZE(exynos5420_clk_regs)); 267 ARRAY_SIZE(exynos5x_clk_regs));
268
269 if (exynos5x_soc == EXYNOS5800)
270 samsung_clk_restore(reg_base, exynos5800_save,
271 ARRAY_SIZE(exynos5800_clk_regs));
237} 272}
238 273
239static struct syscore_ops exynos5420_clk_syscore_ops = { 274static struct syscore_ops exynos5420_clk_syscore_ops = {
@@ -243,15 +278,29 @@ static struct syscore_ops exynos5420_clk_syscore_ops = {
243 278
244static void exynos5420_clk_sleep_init(void) 279static void exynos5420_clk_sleep_init(void)
245{ 280{
246 exynos5420_save = samsung_clk_alloc_reg_dump(exynos5420_clk_regs, 281 exynos5x_save = samsung_clk_alloc_reg_dump(exynos5x_clk_regs,
247 ARRAY_SIZE(exynos5420_clk_regs)); 282 ARRAY_SIZE(exynos5x_clk_regs));
248 if (!exynos5420_save) { 283 if (!exynos5x_save) {
249 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", 284 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
250 __func__); 285 __func__);
251 return; 286 return;
252 } 287 }
253 288
289 if (exynos5x_soc == EXYNOS5800) {
290 exynos5800_save =
291 samsung_clk_alloc_reg_dump(exynos5800_clk_regs,
292 ARRAY_SIZE(exynos5800_clk_regs));
293 if (!exynos5800_save)
294 goto err_soc;
295 }
296
254 register_syscore_ops(&exynos5420_clk_syscore_ops); 297 register_syscore_ops(&exynos5420_clk_syscore_ops);
298 return;
299err_soc:
300 kfree(exynos5x_save);
301 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
302 __func__);
303 return;
255} 304}
256#else 305#else
257static void exynos5420_clk_sleep_init(void) {} 306static void exynos5420_clk_sleep_init(void) {}
@@ -369,14 +418,43 @@ PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll",
369 "mout_sclk_epll", "mout_sclk_rpll"}; 418 "mout_sclk_epll", "mout_sclk_rpll"};
370PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll", 419PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll",
371 "mout_sclk_mpll", "mout_sclk_spll"}; 420 "mout_sclk_mpll", "mout_sclk_spll"};
421/* List of parents specific to exynos5800 */
422PNAME(mout_epll2_5800_p) = { "mout_sclk_epll", "ff_dout_epll2" };
423PNAME(mout_group1_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
424 "mout_sclk_mpll", "ff_dout_spll2" };
425PNAME(mout_group2_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
426 "mout_sclk_mpll", "ff_dout_spll2",
427 "mout_epll2", "mout_sclk_ipll" };
428PNAME(mout_group3_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
429 "mout_sclk_mpll", "ff_dout_spll2",
430 "mout_epll2" };
431PNAME(mout_group5_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
432 "mout_sclk_mpll", "mout_sclk_spll" };
433PNAME(mout_group6_5800_p) = { "mout_sclk_ipll", "mout_sclk_dpll",
434 "mout_sclk_mpll", "ff_dout_spll2" };
435PNAME(mout_group7_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
436 "mout_sclk_mpll", "mout_sclk_spll",
437 "mout_epll2", "mout_sclk_ipll" };
438PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll",
439 "mout_sclk_mpll",
440 "ff_dout_spll2" };
441PNAME(mout_group8_5800_p) = { "dout_aclk432_scaler", "dout_sclk_sw" };
442PNAME(mout_group9_5800_p) = { "dout_osc_div", "mout_sw_aclk432_scaler" };
443PNAME(mout_group10_5800_p) = { "dout_aclk432_cam", "dout_sclk_sw" };
444PNAME(mout_group11_5800_p) = { "dout_osc_div", "mout_sw_aclk432_cam" };
445PNAME(mout_group12_5800_p) = { "dout_aclkfl1_550_cam", "dout_sclk_sw" };
446PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" };
447PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" };
448PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" };
372 449
373/* fixed rate clocks generated outside the soc */ 450/* fixed rate clocks generated outside the soc */
374static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = { 451static struct samsung_fixed_rate_clock
452 exynos5x_fixed_rate_ext_clks[] __initdata = {
375 FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0), 453 FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0),
376}; 454};
377 455
378/* fixed rate clocks generated inside the soc */ 456/* fixed rate clocks generated inside the soc */
379static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = { 457static struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initdata = {
380 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000), 458 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
381 FRATE(0, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000), 459 FRATE(0, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000),
382 FRATE(0, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000), 460 FRATE(0, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000),
@@ -384,52 +462,146 @@ static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata =
384 FRATE(0, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000), 462 FRATE(0, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000),
385}; 463};
386 464
387static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = { 465static struct samsung_fixed_factor_clock
466 exynos5x_fixed_factor_clks[] __initdata = {
388 FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0), 467 FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0),
389 FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0), 468 FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0),
390}; 469};
391 470
392static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { 471static struct samsung_fixed_factor_clock
393 MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p, 472 exynos5800_fixed_factor_clks[] __initdata = {
394 SRC_TOP7, 4, 1), 473 FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0),
395 MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2), 474 FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
396 MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2), 475};
397 MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2),
398 476
399 MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1), 477struct samsung_mux_clock exynos5800_mux_clks[] __initdata = {
400 MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), 478 MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
401 MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1), 479 MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
402 MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1), 480 MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3),
481 MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
482
483 MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2),
484 MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2),
485 MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2),
486 MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2),
487 MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2),
488
489 MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3),
490 MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2),
491 MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2),
492 MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2),
493 MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2),
494 MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2),
495
496 MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, SRC_TOP7,
497 20, 2),
498 MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
499 MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
500
501 MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
502 MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3),
503 MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2),
504 MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2),
505
506 MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p,
507 SRC_TOP9, 16, 1),
508 MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p,
509 SRC_TOP9, 20, 1),
510 MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p,
511 SRC_TOP9, 24, 1),
512 MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p,
513 SRC_TOP9, 28, 1),
514
515 MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1),
516 MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p,
517 SRC_TOP13, 20, 1),
518 MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p,
519 SRC_TOP13, 24, 1),
520 MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p,
521 SRC_TOP13, 28, 1),
522
523 MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3),
524};
403 525
526struct samsung_div_clock exynos5800_div_clks[] __initdata = {
527 DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore", DIV_TOP0, 16, 3),
528
529 DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
530 DIV_TOP8, 16, 3),
531 DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam",
532 DIV_TOP8, 20, 3),
533 DIV(0, "dout_aclk432_cam", "mout_aclk432_cam",
534 DIV_TOP8, 24, 3),
535 DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler",
536 DIV_TOP8, 28, 3),
537
538 DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3),
539 DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6),
540};
541
542struct samsung_gate_clock exynos5800_gate_clks[] __initdata = {
543 GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam",
544 GATE_BUS_TOP, 24, 0, 0),
545 GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler",
546 GATE_BUS_TOP, 27, 0, 0),
547};
548
549struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
404 MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1), 550 MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1),
551 MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p,
552 TOP_SPARE2, 4, 1),
405 553
406 MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2), 554 MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
407 MUX_A(0, "mout_aclk400_mscl", mout_group1_p, 555 MUX_A(0, "mout_aclk400_mscl", mout_group1_p,
408 SRC_TOP0, 4, 2, "aclk400_mscl"), 556 SRC_TOP0, 4, 2, "aclk400_mscl"),
409 MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
410 MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2),
411 MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2), 557 MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
412 MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2), 558 MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
413 MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2),
414 MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2),
415 559
416 MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2), 560 MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2),
417 MUX(0, "mout_aclk333_432_isp", mout_group4_p, 561 MUX(0, "mout_aclk333_432_isp", mout_group4_p,
418 SRC_TOP1, 4, 2), 562 SRC_TOP1, 4, 2),
419 MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2),
420 MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2), 563 MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2),
421 MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2), 564 MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2),
422 MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2),
423 MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2), 565 MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2),
424 566
425 MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2), 567 MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2),
426 MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2), 568 MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2),
427 MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2), 569 MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2),
428 MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1),
429 MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2), 570 MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2),
430 MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2), 571 MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2),
431 MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2), 572 MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2),
432 573
574 MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2),
575
576 MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1),
577};
578
579struct samsung_div_clock exynos5420_div_clks[] __initdata = {
580 DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore_bpll",
581 DIV_TOP0, 16, 3),
582};
583
584static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
585 MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p,
586 SRC_TOP7, 4, 1),
587 MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
588 MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
589
590 MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
591 MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
592 MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1),
593 MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
594
595 MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
596 MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2),
597 MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2),
598 MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2),
599
600 MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2),
601 MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2),
602
603 MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1),
604
433 MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p, 605 MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p,
434 SRC_TOP3, 0, 1), 606 SRC_TOP3, 0, 1),
435 MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p, 607 MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p,
@@ -529,15 +701,12 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
529 SRC_TOP12, 28, 1), 701 SRC_TOP12, 28, 1),
530 702
531 /* DISP1 Block */ 703 /* DISP1 Block */
532 MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1),
533 MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3), 704 MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3),
534 MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3), 705 MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3),
535 MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3), 706 MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3),
536 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1), 707 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1),
537 MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3), 708 MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3),
538 709
539 MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p,
540 TOP_SPARE2, 4, 1),
541 MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1), 710 MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1),
542 711
543 /* MAU Block */ 712 /* MAU Block */
@@ -574,7 +743,7 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
574 MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3), 743 MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3),
575}; 744};
576 745
577static struct samsung_div_clock exynos5420_div_clks[] __initdata = { 746static struct samsung_div_clock exynos5x_div_clks[] __initdata = {
578 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 747 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
579 DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 748 DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
580 DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3), 749 DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
@@ -585,8 +754,6 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
585 DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3), 754 DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3),
586 DIV(0, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3), 755 DIV(0, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3),
587 DIV(0, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3), 756 DIV(0, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3),
588 DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore_bpll",
589 DIV_TOP0, 16, 3),
590 DIV(0, "dout_aclk100_noc", "mout_aclk100_noc", DIV_TOP0, 20, 3), 757 DIV(0, "dout_aclk100_noc", "mout_aclk100_noc", DIV_TOP0, 20, 3),
591 DIV(0, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3), 758 DIV(0, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3),
592 DIV(0, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3), 759 DIV(0, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3),
@@ -692,7 +859,7 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
692 CLK_SET_RATE_PARENT, 0), 859 CLK_SET_RATE_PARENT, 0),
693}; 860};
694 861
695static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { 862static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = {
696 /* G2D */ 863 /* G2D */
697 GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0), 864 GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0),
698 GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0), 865 GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
@@ -975,7 +1142,7 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
975 GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), 1142 GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
976}; 1143};
977 1144
978static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = { 1145static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
979 [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, 1146 [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
980 APLL_CON0, NULL), 1147 APLL_CON0, NULL),
981 [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK, 1148 [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
@@ -1006,7 +1173,8 @@ static struct of_device_id ext_clk_match[] __initdata = {
1006}; 1173};
1007 1174
1008/* register exynos5420 clocks */ 1175/* register exynos5420 clocks */
1009static void __init exynos5420_clk_init(struct device_node *np) 1176static void __init exynos5x_clk_init(struct device_node *np,
1177 enum exynos5x_soc soc)
1010{ 1178{
1011 struct samsung_clk_provider *ctx; 1179 struct samsung_clk_provider *ctx;
1012 1180
@@ -1018,27 +1186,56 @@ static void __init exynos5420_clk_init(struct device_node *np)
1018 panic("%s: unable to determine soc\n", __func__); 1186 panic("%s: unable to determine soc\n", __func__);
1019 } 1187 }
1020 1188
1189 exynos5x_soc = soc;
1190
1021 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); 1191 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
1022 if (!ctx) 1192 if (!ctx)
1023 panic("%s: unable to allocate context.\n", __func__); 1193 panic("%s: unable to allocate context.\n", __func__);
1024 1194
1025 samsung_clk_of_register_fixed_ext(ctx, exynos5420_fixed_rate_ext_clks, 1195 samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
1026 ARRAY_SIZE(exynos5420_fixed_rate_ext_clks), 1196 ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
1027 ext_clk_match); 1197 ext_clk_match);
1028 samsung_clk_register_pll(ctx, exynos5420_plls, 1198 samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
1029 ARRAY_SIZE(exynos5420_plls), 1199 reg_base);
1030 reg_base); 1200 samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,
1031 samsung_clk_register_fixed_rate(ctx, exynos5420_fixed_rate_clks, 1201 ARRAY_SIZE(exynos5x_fixed_rate_clks));
1032 ARRAY_SIZE(exynos5420_fixed_rate_clks)); 1202 samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks,
1033 samsung_clk_register_fixed_factor(ctx, exynos5420_fixed_factor_clks, 1203 ARRAY_SIZE(exynos5x_fixed_factor_clks));
1034 ARRAY_SIZE(exynos5420_fixed_factor_clks)); 1204 samsung_clk_register_mux(ctx, exynos5x_mux_clks,
1035 samsung_clk_register_mux(ctx, exynos5420_mux_clks, 1205 ARRAY_SIZE(exynos5x_mux_clks));
1036 ARRAY_SIZE(exynos5420_mux_clks)); 1206 samsung_clk_register_div(ctx, exynos5x_div_clks,
1037 samsung_clk_register_div(ctx, exynos5420_div_clks, 1207 ARRAY_SIZE(exynos5x_div_clks));
1038 ARRAY_SIZE(exynos5420_div_clks)); 1208 samsung_clk_register_gate(ctx, exynos5x_gate_clks,
1039 samsung_clk_register_gate(ctx, exynos5420_gate_clks, 1209 ARRAY_SIZE(exynos5x_gate_clks));
1040 ARRAY_SIZE(exynos5420_gate_clks)); 1210
1211 if (soc == EXYNOS5420) {
1212 samsung_clk_register_mux(ctx, exynos5420_mux_clks,
1213 ARRAY_SIZE(exynos5420_mux_clks));
1214 samsung_clk_register_div(ctx, exynos5420_div_clks,
1215 ARRAY_SIZE(exynos5420_div_clks));
1216 } else {
1217 samsung_clk_register_fixed_factor(
1218 ctx, exynos5800_fixed_factor_clks,
1219 ARRAY_SIZE(exynos5800_fixed_factor_clks));
1220 samsung_clk_register_mux(ctx, exynos5800_mux_clks,
1221 ARRAY_SIZE(exynos5800_mux_clks));
1222 samsung_clk_register_div(ctx, exynos5800_div_clks,
1223 ARRAY_SIZE(exynos5800_div_clks));
1224 samsung_clk_register_gate(ctx, exynos5800_gate_clks,
1225 ARRAY_SIZE(exynos5800_gate_clks));
1226 }
1041 1227
1042 exynos5420_clk_sleep_init(); 1228 exynos5420_clk_sleep_init();
1043} 1229}
1230
1231static void __init exynos5420_clk_init(struct device_node *np)
1232{
1233 exynos5x_clk_init(np, EXYNOS5420);
1234}
1044CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init); 1235CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init);
1236
1237static void __init exynos5800_clk_init(struct device_node *np)
1238{
1239 exynos5x_clk_init(np, EXYNOS5800);
1240}
1241CLK_OF_DECLARE(exynos5800_clk, "samsung,exynos5800-clock", exynos5800_clk_init);
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 7dd1cc3b5c57..97dcb89d37d3 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -193,6 +193,10 @@
193#define CLK_SCLK_ISP_SENSOR0 514 193#define CLK_SCLK_ISP_SENSOR0 514
194#define CLK_SCLK_ISP_SENSOR1 515 194#define CLK_SCLK_ISP_SENSOR1 515
195#define CLK_SCLK_ISP_SENSOR2 516 195#define CLK_SCLK_ISP_SENSOR2 516
196#define CLK_ACLK432_SCALER 517
197#define CLK_ACLK432_CAM 518
198#define CLK_ACLK_FL1550_CAM 519
199#define CLK_ACLK550_CAM 520
196 200
197/* mux clocks */ 201/* mux clocks */
198#define CLK_MOUT_HDMI 640 202#define CLK_MOUT_HDMI 640
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-01 19:12:59 -0400