diff options
-rw-r--r-- | arch/arm/boot/dts/exynos5250-snow.dts | 4 | ||||
-rw-r--r-- | arch/arm/boot/dts/exynos5250.dtsi | 2 | ||||
-rw-r--r-- | arch/arm/configs/exynos_defconfig | 2 | ||||
-rw-r--r-- | arch/arm/mach-mvebu/coherency.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-tegra/irq.c | 22 |
5 files changed, 20 insertions, 12 deletions
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index e51fcef884a4..60429ad1c5d8 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts | |||
@@ -624,4 +624,8 @@ | |||
624 | num-cs = <1>; | 624 | num-cs = <1>; |
625 | }; | 625 | }; |
626 | 626 | ||
627 | &usbdrd_dwc3 { | ||
628 | dr_mode = "host"; | ||
629 | }; | ||
630 | |||
627 | #include "cros-ec-keyboard.dtsi" | 631 | #include "cros-ec-keyboard.dtsi" |
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index f21b9aa00fbb..d55c1a2eb798 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi | |||
@@ -555,7 +555,7 @@ | |||
555 | #size-cells = <1>; | 555 | #size-cells = <1>; |
556 | ranges; | 556 | ranges; |
557 | 557 | ||
558 | dwc3 { | 558 | usbdrd_dwc3: dwc3 { |
559 | compatible = "synopsys,dwc3"; | 559 | compatible = "synopsys,dwc3"; |
560 | reg = <0x12000000 0x10000>; | 560 | reg = <0x12000000 0x10000>; |
561 | interrupts = <0 72 0>; | 561 | interrupts = <0 72 0>; |
diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index 72058b8a6f4d..e21ef830a483 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig | |||
@@ -142,11 +142,13 @@ CONFIG_MMC_DW_IDMAC=y | |||
142 | CONFIG_MMC_DW_EXYNOS=y | 142 | CONFIG_MMC_DW_EXYNOS=y |
143 | CONFIG_RTC_CLASS=y | 143 | CONFIG_RTC_CLASS=y |
144 | CONFIG_RTC_DRV_MAX77686=y | 144 | CONFIG_RTC_DRV_MAX77686=y |
145 | CONFIG_RTC_DRV_MAX77802=y | ||
145 | CONFIG_RTC_DRV_S5M=y | 146 | CONFIG_RTC_DRV_S5M=y |
146 | CONFIG_RTC_DRV_S3C=y | 147 | CONFIG_RTC_DRV_S3C=y |
147 | CONFIG_DMADEVICES=y | 148 | CONFIG_DMADEVICES=y |
148 | CONFIG_PL330_DMA=y | 149 | CONFIG_PL330_DMA=y |
149 | CONFIG_COMMON_CLK_MAX77686=y | 150 | CONFIG_COMMON_CLK_MAX77686=y |
151 | CONFIG_COMMON_CLK_MAX77802=y | ||
150 | CONFIG_COMMON_CLK_S2MPS11=y | 152 | CONFIG_COMMON_CLK_S2MPS11=y |
151 | CONFIG_EXYNOS_IOMMU=y | 153 | CONFIG_EXYNOS_IOMMU=y |
152 | CONFIG_IIO=y | 154 | CONFIG_IIO=y |
diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c index 2bdc3233abe2..044b51185fcc 100644 --- a/arch/arm/mach-mvebu/coherency.c +++ b/arch/arm/mach-mvebu/coherency.c | |||
@@ -400,6 +400,8 @@ int __init coherency_init(void) | |||
400 | type == COHERENCY_FABRIC_TYPE_ARMADA_380) | 400 | type == COHERENCY_FABRIC_TYPE_ARMADA_380) |
401 | armada_375_380_coherency_init(np); | 401 | armada_375_380_coherency_init(np); |
402 | 402 | ||
403 | of_node_put(np); | ||
404 | |||
403 | return 0; | 405 | return 0; |
404 | } | 406 | } |
405 | 407 | ||
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index da7be13aecce..ab95f5391a2b 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c | |||
@@ -99,42 +99,42 @@ static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg) | |||
99 | 99 | ||
100 | static void tegra_mask(struct irq_data *d) | 100 | static void tegra_mask(struct irq_data *d) |
101 | { | 101 | { |
102 | if (d->irq < FIRST_LEGACY_IRQ) | 102 | if (d->hwirq < FIRST_LEGACY_IRQ) |
103 | return; | 103 | return; |
104 | 104 | ||
105 | tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_CLR); | 105 | tegra_irq_write_mask(d->hwirq, ICTLR_CPU_IER_CLR); |
106 | } | 106 | } |
107 | 107 | ||
108 | static void tegra_unmask(struct irq_data *d) | 108 | static void tegra_unmask(struct irq_data *d) |
109 | { | 109 | { |
110 | if (d->irq < FIRST_LEGACY_IRQ) | 110 | if (d->hwirq < FIRST_LEGACY_IRQ) |
111 | return; | 111 | return; |
112 | 112 | ||
113 | tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_SET); | 113 | tegra_irq_write_mask(d->hwirq, ICTLR_CPU_IER_SET); |
114 | } | 114 | } |
115 | 115 | ||
116 | static void tegra_ack(struct irq_data *d) | 116 | static void tegra_ack(struct irq_data *d) |
117 | { | 117 | { |
118 | if (d->irq < FIRST_LEGACY_IRQ) | 118 | if (d->hwirq < FIRST_LEGACY_IRQ) |
119 | return; | 119 | return; |
120 | 120 | ||
121 | tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR); | 121 | tegra_irq_write_mask(d->hwirq, ICTLR_CPU_IEP_FIR_CLR); |
122 | } | 122 | } |
123 | 123 | ||
124 | static void tegra_eoi(struct irq_data *d) | 124 | static void tegra_eoi(struct irq_data *d) |
125 | { | 125 | { |
126 | if (d->irq < FIRST_LEGACY_IRQ) | 126 | if (d->hwirq < FIRST_LEGACY_IRQ) |
127 | return; | 127 | return; |
128 | 128 | ||
129 | tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR); | 129 | tegra_irq_write_mask(d->hwirq, ICTLR_CPU_IEP_FIR_CLR); |
130 | } | 130 | } |
131 | 131 | ||
132 | static int tegra_retrigger(struct irq_data *d) | 132 | static int tegra_retrigger(struct irq_data *d) |
133 | { | 133 | { |
134 | if (d->irq < FIRST_LEGACY_IRQ) | 134 | if (d->hwirq < FIRST_LEGACY_IRQ) |
135 | return 0; | 135 | return 0; |
136 | 136 | ||
137 | tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_SET); | 137 | tegra_irq_write_mask(d->hwirq, ICTLR_CPU_IEP_FIR_SET); |
138 | 138 | ||
139 | return 1; | 139 | return 1; |
140 | } | 140 | } |
@@ -142,7 +142,7 @@ static int tegra_retrigger(struct irq_data *d) | |||
142 | #ifdef CONFIG_PM_SLEEP | 142 | #ifdef CONFIG_PM_SLEEP |
143 | static int tegra_set_wake(struct irq_data *d, unsigned int enable) | 143 | static int tegra_set_wake(struct irq_data *d, unsigned int enable) |
144 | { | 144 | { |
145 | u32 irq = d->irq; | 145 | u32 irq = d->hwirq; |
146 | u32 index, mask; | 146 | u32 index, mask; |
147 | 147 | ||
148 | if (irq < FIRST_LEGACY_IRQ || | 148 | if (irq < FIRST_LEGACY_IRQ || |