diff options
| -rw-r--r-- | arch/x86/include/asm/uv/uv_mmrs.h | 3474 |
1 files changed, 3366 insertions, 108 deletions
diff --git a/arch/x86/include/asm/uv/uv_mmrs.h b/arch/x86/include/asm/uv/uv_mmrs.h index cf1d73643f60..e1fa870ce782 100644 --- a/arch/x86/include/asm/uv/uv_mmrs.h +++ b/arch/x86/include/asm/uv/uv_mmrs.h | |||
| @@ -5,16 +5,25 @@ | |||
| 5 | * | 5 | * |
| 6 | * SGI UV MMR definitions | 6 | * SGI UV MMR definitions |
| 7 | * | 7 | * |
| 8 | * Copyright (C) 2007-2011 Silicon Graphics, Inc. All rights reserved. | 8 | * Copyright (C) 2007-2013 Silicon Graphics, Inc. All rights reserved. |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | #ifndef _ASM_X86_UV_UV_MMRS_H | 11 | #ifndef _ASM_X86_UV_UV_MMRS_H |
| 12 | #define _ASM_X86_UV_UV_MMRS_H | 12 | #define _ASM_X86_UV_UV_MMRS_H |
| 13 | 13 | ||
| 14 | /* | 14 | /* |
| 15 | * This file contains MMR definitions for both UV1 & UV2 hubs. | 15 | * This file contains MMR definitions for all UV hubs types. |
| 16 | * | 16 | * |
| 17 | * In general, MMR addresses and structures are identical on both hubs. | 17 | * To minimize coding differences between hub types, the symbols are |
| 18 | * grouped by architecture types. | ||
| 19 | * | ||
| 20 | * UVH - definitions common to all UV hub types. | ||
| 21 | * UVXH - definitions common to all UV eXtended hub types (currently 2 & 3). | ||
| 22 | * UV1H - definitions specific to UV type 1 hub. | ||
| 23 | * UV2H - definitions specific to UV type 2 hub. | ||
| 24 | * UV3H - definitions specific to UV type 3 hub. | ||
| 25 | * | ||
| 26 | * So in general, MMR addresses and structures are identical on all hubs types. | ||
| 18 | * These MMRs are identified as: | 27 | * These MMRs are identified as: |
| 19 | * #define UVH_xxx <address> | 28 | * #define UVH_xxx <address> |
| 20 | * union uvh_xxx { | 29 | * union uvh_xxx { |
| @@ -23,24 +32,36 @@ | |||
| 23 | * } s; | 32 | * } s; |
| 24 | * }; | 33 | * }; |
| 25 | * | 34 | * |
| 26 | * If the MMR exists on both hub type but has different addresses or | 35 | * If the MMR exists on all hub types but have different addresses: |
| 27 | * contents, the MMR definition is similar to: | 36 | * #define UV1Hxxx a |
| 28 | * #define UV1H_xxx <uv1 address> | 37 | * #define UV2Hxxx b |
| 29 | * #define UV2H_xxx <uv2address> | 38 | * #define UV3Hxxx c |
| 30 | * #define UVH_xxx (is_uv1_hub() ? UV1H_xxx : UV2H_xxx) | 39 | * #define UVHxxx (is_uv1_hub() ? UV1Hxxx : |
| 40 | * (is_uv2_hub() ? UV2Hxxx : | ||
| 41 | * UV3Hxxx)) | ||
| 42 | * | ||
| 43 | * If the MMR exists on all hub types > 1 but have different addresses: | ||
| 44 | * #define UV2Hxxx b | ||
| 45 | * #define UV3Hxxx c | ||
| 46 | * #define UVXHxxx (is_uv2_hub() ? UV2Hxxx : | ||
| 47 | * UV3Hxxx)) | ||
| 48 | * | ||
| 31 | * union uvh_xxx { | 49 | * union uvh_xxx { |
| 32 | * unsigned long v; | 50 | * unsigned long v; |
| 33 | * struct uv1h_int_cmpd_s { (Common fields only) | 51 | * struct uvh_xxx_s { # Common fields only |
| 34 | * } s; | 52 | * } s; |
| 35 | * struct uv1h_int_cmpd_s { (Full UV1 definition) | 53 | * struct uv1h_xxx_s { # Full UV1 definition (*) |
| 36 | * } s1; | 54 | * } s1; |
| 37 | * struct uv2h_int_cmpd_s { (Full UV2 definition) | 55 | * struct uv2h_xxx_s { # Full UV2 definition (*) |
| 38 | * } s2; | 56 | * } s2; |
| 57 | * struct uv3h_xxx_s { # Full UV3 definition (*) | ||
| 58 | * } s3; | ||
| 39 | * }; | 59 | * }; |
| 60 | * (* - if present and different than the common struct) | ||
| 40 | * | 61 | * |
| 41 | * Only essential difference are enumerated. For example, if the address is | 62 | * Only essential differences are enumerated. For example, if the address is |
| 42 | * the same for both UV1 & UV2, only a single #define is generated. Likewise, | 63 | * the same for all UV's, only a single #define is generated. Likewise, |
| 43 | * if the contents is the same for both hubs, only the "s" structure is | 64 | * if the contents is the same for all hubs, only the "s" structure is |
| 44 | * generated. | 65 | * generated. |
| 45 | * | 66 | * |
| 46 | * If the MMR exists on ONLY 1 type of hub, no generic definition is | 67 | * If the MMR exists on ONLY 1 type of hub, no generic definition is |
| @@ -51,6 +72,8 @@ | |||
| 51 | * struct uvh_int_cmpd_s { | 72 | * struct uvh_int_cmpd_s { |
| 52 | * } sn; | 73 | * } sn; |
| 53 | * }; | 74 | * }; |
| 75 | * | ||
| 76 | * (GEN Flags: mflags_opt=c undefs=0 UV23=UVXH) | ||
| 54 | */ | 77 | */ |
| 55 | 78 | ||
| 56 | #define UV_MMR_ENABLE (1UL << 63) | 79 | #define UV_MMR_ENABLE (1UL << 63) |
| @@ -58,32 +81,75 @@ | |||
| 58 | #define UV1_HUB_PART_NUMBER 0x88a5 | 81 | #define UV1_HUB_PART_NUMBER 0x88a5 |
| 59 | #define UV2_HUB_PART_NUMBER 0x8eb8 | 82 | #define UV2_HUB_PART_NUMBER 0x8eb8 |
| 60 | #define UV2_HUB_PART_NUMBER_X 0x1111 | 83 | #define UV2_HUB_PART_NUMBER_X 0x1111 |
| 84 | #define UV3_HUB_PART_NUMBER 0x9578 | ||
| 85 | #define UV3_HUB_PART_NUMBER_X 0x4321 | ||
| 61 | 86 | ||
| 62 | /* Compat: if this #define is present, UV headers support UV2 */ | 87 | /* Compat: Indicate which UV Hubs are supported. */ |
| 63 | #define UV2_HUB_IS_SUPPORTED 1 | 88 | #define UV2_HUB_IS_SUPPORTED 1 |
| 89 | #define UV3_HUB_IS_SUPPORTED 1 | ||
| 64 | 90 | ||
| 65 | /* ========================================================================= */ | 91 | /* ========================================================================= */ |
| 66 | /* UVH_BAU_DATA_BROADCAST */ | 92 | /* UVH_BAU_DATA_BROADCAST */ |
| 67 | /* ========================================================================= */ | 93 | /* ========================================================================= */ |
| 68 | #define UVH_BAU_DATA_BROADCAST 0x61688UL | 94 | #define UVH_BAU_DATA_BROADCAST 0x61688UL |
| 69 | #define UVH_BAU_DATA_BROADCAST_32 0x440 | 95 | #define UV1H_BAU_DATA_BROADCAST 0x61688UL |
| 96 | #define UV2H_BAU_DATA_BROADCAST 0x61688UL | ||
| 97 | #define UV3H_BAU_DATA_BROADCAST 0x61688UL | ||
| 98 | #define UVH_BAU_DATA_BROADCAST_32 0x440 | ||
| 99 | #define UV1H_BAU_DATA_BROADCAST_32 0x61688UL | ||
| 100 | #define UV2H_BAU_DATA_BROADCAST_32 0x61688UL | ||
| 101 | #define UV3H_BAU_DATA_BROADCAST_32 0x61688UL | ||
| 70 | 102 | ||
| 71 | #define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT 0 | 103 | #define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT 0 |
| 72 | #define UVH_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL | 104 | #define UVH_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL |
| 73 | 105 | ||
| 106 | #define UV1H_BAU_DATA_BROADCAST_ENABLE_SHFT 0 | ||
| 107 | #define UV1H_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL | ||
| 108 | |||
| 109 | #define UVXH_BAU_DATA_BROADCAST_ENABLE_SHFT 0 | ||
| 110 | #define UVXH_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL | ||
| 111 | |||
| 112 | #define UV2H_BAU_DATA_BROADCAST_ENABLE_SHFT 0 | ||
| 113 | #define UV2H_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL | ||
| 114 | |||
| 115 | #define UV3H_BAU_DATA_BROADCAST_ENABLE_SHFT 0 | ||
| 116 | #define UV3H_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL | ||
| 117 | |||
| 74 | union uvh_bau_data_broadcast_u { | 118 | union uvh_bau_data_broadcast_u { |
| 75 | unsigned long v; | 119 | unsigned long v; |
| 76 | struct uvh_bau_data_broadcast_s { | 120 | struct uvh_bau_data_broadcast_s { |
| 77 | unsigned long enable:1; /* RW */ | 121 | unsigned long enable:1; /* RW */ |
| 78 | unsigned long rsvd_1_63:63; | 122 | unsigned long rsvd_1_63:63; |
| 79 | } s; | 123 | } s; |
| 124 | struct uv1h_bau_data_broadcast_s { | ||
| 125 | unsigned long enable:1; /* RW */ | ||
| 126 | unsigned long rsvd_1_63:63; | ||
| 127 | } s1; | ||
| 128 | struct uvxh_bau_data_broadcast_s { | ||
| 129 | unsigned long enable:1; /* RW */ | ||
| 130 | unsigned long rsvd_1_63:63; | ||
| 131 | } sx; | ||
| 132 | struct uv2h_bau_data_broadcast_s { | ||
| 133 | unsigned long enable:1; /* RW */ | ||
| 134 | unsigned long rsvd_1_63:63; | ||
| 135 | } s2; | ||
| 136 | struct uv3h_bau_data_broadcast_s { | ||
| 137 | unsigned long enable:1; /* RW */ | ||
| 138 | unsigned long rsvd_1_63:63; | ||
| 139 | } s3; | ||
| 80 | }; | 140 | }; |
| 81 | 141 | ||
| 82 | /* ========================================================================= */ | 142 | /* ========================================================================= */ |
| 83 | /* UVH_BAU_DATA_CONFIG */ | 143 | /* UVH_BAU_DATA_CONFIG */ |
| 84 | /* ========================================================================= */ | 144 | /* ========================================================================= */ |
| 85 | #define UVH_BAU_DATA_CONFIG 0x61680UL | 145 | #define UVH_BAU_DATA_CONFIG 0x61680UL |
| 86 | #define UVH_BAU_DATA_CONFIG_32 0x438 | 146 | #define UV1H_BAU_DATA_CONFIG 0x61680UL |
| 147 | #define UV2H_BAU_DATA_CONFIG 0x61680UL | ||
| 148 | #define UV3H_BAU_DATA_CONFIG 0x61680UL | ||
| 149 | #define UVH_BAU_DATA_CONFIG_32 0x438 | ||
| 150 | #define UV1H_BAU_DATA_CONFIG_32 0x61680UL | ||
| 151 | #define UV2H_BAU_DATA_CONFIG_32 0x61680UL | ||
| 152 | #define UV3H_BAU_DATA_CONFIG_32 0x61680UL | ||
| 87 | 153 | ||
| 88 | #define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0 | 154 | #define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0 |
| 89 | #define UVH_BAU_DATA_CONFIG_DM_SHFT 8 | 155 | #define UVH_BAU_DATA_CONFIG_DM_SHFT 8 |
| @@ -102,6 +168,74 @@ union uvh_bau_data_broadcast_u { | |||
| 102 | #define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL | 168 | #define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL |
| 103 | #define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | 169 | #define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL |
| 104 | 170 | ||
| 171 | #define UV1H_BAU_DATA_CONFIG_VECTOR_SHFT 0 | ||
| 172 | #define UV1H_BAU_DATA_CONFIG_DM_SHFT 8 | ||
| 173 | #define UV1H_BAU_DATA_CONFIG_DESTMODE_SHFT 11 | ||
| 174 | #define UV1H_BAU_DATA_CONFIG_STATUS_SHFT 12 | ||
| 175 | #define UV1H_BAU_DATA_CONFIG_P_SHFT 13 | ||
| 176 | #define UV1H_BAU_DATA_CONFIG_T_SHFT 15 | ||
| 177 | #define UV1H_BAU_DATA_CONFIG_M_SHFT 16 | ||
| 178 | #define UV1H_BAU_DATA_CONFIG_APIC_ID_SHFT 32 | ||
| 179 | #define UV1H_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL | ||
| 180 | #define UV1H_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL | ||
| 181 | #define UV1H_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL | ||
| 182 | #define UV1H_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL | ||
| 183 | #define UV1H_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL | ||
| 184 | #define UV1H_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL | ||
| 185 | #define UV1H_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL | ||
| 186 | #define UV1H_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | ||
| 187 | |||
| 188 | #define UVXH_BAU_DATA_CONFIG_VECTOR_SHFT 0 | ||
| 189 | #define UVXH_BAU_DATA_CONFIG_DM_SHFT 8 | ||
| 190 | #define UVXH_BAU_DATA_CONFIG_DESTMODE_SHFT 11 | ||
| 191 | #define UVXH_BAU_DATA_CONFIG_STATUS_SHFT 12 | ||
| 192 | #define UVXH_BAU_DATA_CONFIG_P_SHFT 13 | ||
| 193 | #define UVXH_BAU_DATA_CONFIG_T_SHFT 15 | ||
| 194 | #define UVXH_BAU_DATA_CONFIG_M_SHFT 16 | ||
| 195 | #define UVXH_BAU_DATA_CONFIG_APIC_ID_SHFT 32 | ||
| 196 | #define UVXH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL | ||
| 197 | #define UVXH_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL | ||
| 198 | #define UVXH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL | ||
| 199 | #define UVXH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL | ||
| 200 | #define UVXH_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL | ||
| 201 | #define UVXH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL | ||
| 202 | #define UVXH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL | ||
| 203 | #define UVXH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | ||
| 204 | |||
| 205 | #define UV2H_BAU_DATA_CONFIG_VECTOR_SHFT 0 | ||
| 206 | #define UV2H_BAU_DATA_CONFIG_DM_SHFT 8 | ||
| 207 | #define UV2H_BAU_DATA_CONFIG_DESTMODE_SHFT 11 | ||
| 208 | #define UV2H_BAU_DATA_CONFIG_STATUS_SHFT 12 | ||
| 209 | #define UV2H_BAU_DATA_CONFIG_P_SHFT 13 | ||
| 210 | #define UV2H_BAU_DATA_CONFIG_T_SHFT 15 | ||
| 211 | #define UV2H_BAU_DATA_CONFIG_M_SHFT 16 | ||
| 212 | #define UV2H_BAU_DATA_CONFIG_APIC_ID_SHFT 32 | ||
| 213 | #define UV2H_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL | ||
| 214 | #define UV2H_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL | ||
| 215 | #define UV2H_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL | ||
| 216 | #define UV2H_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL | ||
| 217 | #define UV2H_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL | ||
| 218 | #define UV2H_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL | ||
| 219 | #define UV2H_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL | ||
| 220 | #define UV2H_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | ||
| 221 | |||
| 222 | #define UV3H_BAU_DATA_CONFIG_VECTOR_SHFT 0 | ||
| 223 | #define UV3H_BAU_DATA_CONFIG_DM_SHFT 8 | ||
| 224 | #define UV3H_BAU_DATA_CONFIG_DESTMODE_SHFT 11 | ||
| 225 | #define UV3H_BAU_DATA_CONFIG_STATUS_SHFT 12 | ||
| 226 | #define UV3H_BAU_DATA_CONFIG_P_SHFT 13 | ||
| 227 | #define UV3H_BAU_DATA_CONFIG_T_SHFT 15 | ||
| 228 | #define UV3H_BAU_DATA_CONFIG_M_SHFT 16 | ||
| 229 | #define UV3H_BAU_DATA_CONFIG_APIC_ID_SHFT 32 | ||
| 230 | #define UV3H_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL | ||
| 231 | #define UV3H_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL | ||
| 232 | #define UV3H_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL | ||
| 233 | #define UV3H_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL | ||
| 234 | #define UV3H_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL | ||
| 235 | #define UV3H_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL | ||
| 236 | #define UV3H_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL | ||
| 237 | #define UV3H_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | ||
| 238 | |||
| 105 | union uvh_bau_data_config_u { | 239 | union uvh_bau_data_config_u { |
| 106 | unsigned long v; | 240 | unsigned long v; |
| 107 | struct uvh_bau_data_config_s { | 241 | struct uvh_bau_data_config_s { |
| @@ -116,13 +250,72 @@ union uvh_bau_data_config_u { | |||
| 116 | unsigned long rsvd_17_31:15; | 250 | unsigned long rsvd_17_31:15; |
| 117 | unsigned long apic_id:32; /* RW */ | 251 | unsigned long apic_id:32; /* RW */ |
| 118 | } s; | 252 | } s; |
| 253 | struct uv1h_bau_data_config_s { | ||
| 254 | unsigned long vector_:8; /* RW */ | ||
| 255 | unsigned long dm:3; /* RW */ | ||
| 256 | unsigned long destmode:1; /* RW */ | ||
| 257 | unsigned long status:1; /* RO */ | ||
| 258 | unsigned long p:1; /* RO */ | ||
| 259 | unsigned long rsvd_14:1; | ||
| 260 | unsigned long t:1; /* RO */ | ||
| 261 | unsigned long m:1; /* RW */ | ||
| 262 | unsigned long rsvd_17_31:15; | ||
| 263 | unsigned long apic_id:32; /* RW */ | ||
| 264 | } s1; | ||
| 265 | struct uvxh_bau_data_config_s { | ||
| 266 | unsigned long vector_:8; /* RW */ | ||
| 267 | unsigned long dm:3; /* RW */ | ||
| 268 | unsigned long destmode:1; /* RW */ | ||
| 269 | unsigned long status:1; /* RO */ | ||
| 270 | unsigned long p:1; /* RO */ | ||
| 271 | unsigned long rsvd_14:1; | ||
| 272 | unsigned long t:1; /* RO */ | ||
| 273 | unsigned long m:1; /* RW */ | ||
| 274 | unsigned long rsvd_17_31:15; | ||
| 275 | unsigned long apic_id:32; /* RW */ | ||
| 276 | } sx; | ||
| 277 | struct uv2h_bau_data_config_s { | ||
| 278 | unsigned long vector_:8; /* RW */ | ||
| 279 | unsigned long dm:3; /* RW */ | ||
| 280 | unsigned long destmode:1; /* RW */ | ||
| 281 | unsigned long status:1; /* RO */ | ||
| 282 | unsigned long p:1; /* RO */ | ||
| 283 | unsigned long rsvd_14:1; | ||
| 284 | unsigned long t:1; /* RO */ | ||
| 285 | unsigned long m:1; /* RW */ | ||
| 286 | unsigned long rsvd_17_31:15; | ||
| 287 | unsigned long apic_id:32; /* RW */ | ||
| 288 | } s2; | ||
| 289 | struct uv3h_bau_data_config_s { | ||
| 290 | unsigned long vector_:8; /* RW */ | ||
| 291 | unsigned long dm:3; /* RW */ | ||
| 292 | unsigned long destmode:1; /* RW */ | ||
| 293 | unsigned long status:1; /* RO */ | ||
| 294 | unsigned long p:1; /* RO */ | ||
| 295 | unsigned long rsvd_14:1; | ||
| 296 | unsigned long t:1; /* RO */ | ||
| 297 | unsigned long m:1; /* RW */ | ||
| 298 | unsigned long rsvd_17_31:15; | ||
| 299 | unsigned long apic_id:32; /* RW */ | ||
| 300 | } s3; | ||
| 119 | }; | 301 | }; |
| 120 | 302 | ||
| 121 | /* ========================================================================= */ | 303 | /* ========================================================================= */ |
| 122 | /* UVH_EVENT_OCCURRED0 */ | 304 | /* UVH_EVENT_OCCURRED0 */ |
| 123 | /* ========================================================================= */ | 305 | /* ========================================================================= */ |
| 124 | #define UVH_EVENT_OCCURRED0 0x70000UL | 306 | #define UVH_EVENT_OCCURRED0 0x70000UL |
| 125 | #define UVH_EVENT_OCCURRED0_32 0x5e8 | 307 | #define UV1H_EVENT_OCCURRED0 0x70000UL |
| 308 | #define UV2H_EVENT_OCCURRED0 0x70000UL | ||
| 309 | #define UV3H_EVENT_OCCURRED0 0x70000UL | ||
| 310 | #define UVH_EVENT_OCCURRED0_32 0x5e8 | ||
| 311 | #define UV1H_EVENT_OCCURRED0_32 0x70000UL | ||
| 312 | #define UV2H_EVENT_OCCURRED0_32 0x70000UL | ||
| 313 | #define UV3H_EVENT_OCCURRED0_32 0x70000UL | ||
| 314 | |||
| 315 | #define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT 0 | ||
| 316 | #define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT 11 | ||
| 317 | #define UVH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL | ||
| 318 | #define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL | ||
| 126 | 319 | ||
| 127 | #define UV1H_EVENT_OCCURRED0_LB_HCERR_SHFT 0 | 320 | #define UV1H_EVENT_OCCURRED0_LB_HCERR_SHFT 0 |
| 128 | #define UV1H_EVENT_OCCURRED0_GR0_HCERR_SHFT 1 | 321 | #define UV1H_EVENT_OCCURRED0_GR0_HCERR_SHFT 1 |
| @@ -239,6 +432,125 @@ union uvh_bau_data_config_u { | |||
| 239 | #define UV1H_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL | 432 | #define UV1H_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL |
| 240 | #define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL | 433 | #define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL |
| 241 | 434 | ||
| 435 | #define UVXH_EVENT_OCCURRED0_LB_HCERR_SHFT 0 | ||
| 436 | #define UVXH_EVENT_OCCURRED0_QP_HCERR_SHFT 1 | ||
| 437 | #define UVXH_EVENT_OCCURRED0_RH_HCERR_SHFT 2 | ||
| 438 | #define UVXH_EVENT_OCCURRED0_LH0_HCERR_SHFT 3 | ||
| 439 | #define UVXH_EVENT_OCCURRED0_LH1_HCERR_SHFT 4 | ||
| 440 | #define UVXH_EVENT_OCCURRED0_GR0_HCERR_SHFT 5 | ||
| 441 | #define UVXH_EVENT_OCCURRED0_GR1_HCERR_SHFT 6 | ||
| 442 | #define UVXH_EVENT_OCCURRED0_NI0_HCERR_SHFT 7 | ||
| 443 | #define UVXH_EVENT_OCCURRED0_NI1_HCERR_SHFT 8 | ||
| 444 | #define UVXH_EVENT_OCCURRED0_LB_AOERR0_SHFT 9 | ||
| 445 | #define UVXH_EVENT_OCCURRED0_QP_AOERR0_SHFT 10 | ||
| 446 | #define UVXH_EVENT_OCCURRED0_RH_AOERR0_SHFT 11 | ||
| 447 | #define UVXH_EVENT_OCCURRED0_LH0_AOERR0_SHFT 12 | ||
| 448 | #define UVXH_EVENT_OCCURRED0_LH1_AOERR0_SHFT 13 | ||
| 449 | #define UVXH_EVENT_OCCURRED0_GR0_AOERR0_SHFT 14 | ||
| 450 | #define UVXH_EVENT_OCCURRED0_GR1_AOERR0_SHFT 15 | ||
| 451 | #define UVXH_EVENT_OCCURRED0_XB_AOERR0_SHFT 16 | ||
| 452 | #define UVXH_EVENT_OCCURRED0_RT_AOERR0_SHFT 17 | ||
| 453 | #define UVXH_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18 | ||
| 454 | #define UVXH_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19 | ||
| 455 | #define UVXH_EVENT_OCCURRED0_LB_AOERR1_SHFT 20 | ||
| 456 | #define UVXH_EVENT_OCCURRED0_QP_AOERR1_SHFT 21 | ||
| 457 | #define UVXH_EVENT_OCCURRED0_RH_AOERR1_SHFT 22 | ||
| 458 | #define UVXH_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23 | ||
| 459 | #define UVXH_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24 | ||
| 460 | #define UVXH_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25 | ||
| 461 | #define UVXH_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26 | ||
| 462 | #define UVXH_EVENT_OCCURRED0_XB_AOERR1_SHFT 27 | ||
| 463 | #define UVXH_EVENT_OCCURRED0_RT_AOERR1_SHFT 28 | ||
| 464 | #define UVXH_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29 | ||
| 465 | #define UVXH_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30 | ||
| 466 | #define UVXH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31 | ||
| 467 | #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32 | ||
| 468 | #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33 | ||
| 469 | #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34 | ||
| 470 | #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35 | ||
| 471 | #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36 | ||
| 472 | #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37 | ||
| 473 | #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38 | ||
| 474 | #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39 | ||
| 475 | #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40 | ||
| 476 | #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41 | ||
| 477 | #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42 | ||
| 478 | #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43 | ||
| 479 | #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44 | ||
| 480 | #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45 | ||
| 481 | #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46 | ||
| 482 | #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47 | ||
| 483 | #define UVXH_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48 | ||
| 484 | #define UVXH_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49 | ||
| 485 | #define UVXH_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50 | ||
| 486 | #define UVXH_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51 | ||
| 487 | #define UVXH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52 | ||
| 488 | #define UVXH_EVENT_OCCURRED0_IPI_INT_SHFT 53 | ||
| 489 | #define UVXH_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54 | ||
| 490 | #define UVXH_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55 | ||
| 491 | #define UVXH_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56 | ||
| 492 | #define UVXH_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57 | ||
| 493 | #define UVXH_EVENT_OCCURRED0_PROFILE_INT_SHFT 58 | ||
| 494 | #define UVXH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL | ||
| 495 | #define UVXH_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL | ||
| 496 | #define UVXH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000004UL | ||
| 497 | #define UVXH_EVENT_OCCURRED0_LH0_HCERR_MASK 0x0000000000000008UL | ||
| 498 | #define UVXH_EVENT_OCCURRED0_LH1_HCERR_MASK 0x0000000000000010UL | ||
| 499 | #define UVXH_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000020UL | ||
| 500 | #define UVXH_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000040UL | ||
| 501 | #define UVXH_EVENT_OCCURRED0_NI0_HCERR_MASK 0x0000000000000080UL | ||
| 502 | #define UVXH_EVENT_OCCURRED0_NI1_HCERR_MASK 0x0000000000000100UL | ||
| 503 | #define UVXH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000200UL | ||
| 504 | #define UVXH_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL | ||
| 505 | #define UVXH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL | ||
| 506 | #define UVXH_EVENT_OCCURRED0_LH0_AOERR0_MASK 0x0000000000001000UL | ||
| 507 | #define UVXH_EVENT_OCCURRED0_LH1_AOERR0_MASK 0x0000000000002000UL | ||
| 508 | #define UVXH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000004000UL | ||
| 509 | #define UVXH_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000008000UL | ||
| 510 | #define UVXH_EVENT_OCCURRED0_XB_AOERR0_MASK 0x0000000000010000UL | ||
| 511 | #define UVXH_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL | ||
| 512 | #define UVXH_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL | ||
| 513 | #define UVXH_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL | ||
| 514 | #define UVXH_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL | ||
| 515 | #define UVXH_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL | ||
| 516 | #define UVXH_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL | ||
| 517 | #define UVXH_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL | ||
| 518 | #define UVXH_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL | ||
| 519 | #define UVXH_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL | ||
| 520 | #define UVXH_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL | ||
| 521 | #define UVXH_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL | ||
| 522 | #define UVXH_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL | ||
| 523 | #define UVXH_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL | ||
| 524 | #define UVXH_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL | ||
| 525 | #define UVXH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL | ||
| 526 | #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL | ||
| 527 | #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL | ||
| 528 | #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL | ||
| 529 | #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL | ||
| 530 | #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL | ||
| 531 | #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL | ||
| 532 | #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL | ||
| 533 | #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL | ||
| 534 | #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL | ||
| 535 | #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL | ||
| 536 | #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL | ||
| 537 | #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL | ||
| 538 | #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL | ||
| 539 | #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL | ||
| 540 | #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL | ||
| 541 | #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL | ||
| 542 | #define UVXH_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL | ||
| 543 | #define UVXH_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL | ||
| 544 | #define UVXH_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL | ||
| 545 | #define UVXH_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL | ||
| 546 | #define UVXH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL | ||
| 547 | #define UVXH_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL | ||
| 548 | #define UVXH_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL | ||
| 549 | #define UVXH_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL | ||
| 550 | #define UVXH_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL | ||
| 551 | #define UVXH_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL | ||
| 552 | #define UVXH_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL | ||
| 553 | |||
| 242 | #define UV2H_EVENT_OCCURRED0_LB_HCERR_SHFT 0 | 554 | #define UV2H_EVENT_OCCURRED0_LB_HCERR_SHFT 0 |
| 243 | #define UV2H_EVENT_OCCURRED0_QP_HCERR_SHFT 1 | 555 | #define UV2H_EVENT_OCCURRED0_QP_HCERR_SHFT 1 |
| 244 | #define UV2H_EVENT_OCCURRED0_RH_HCERR_SHFT 2 | 556 | #define UV2H_EVENT_OCCURRED0_RH_HCERR_SHFT 2 |
| @@ -358,8 +670,133 @@ union uvh_bau_data_config_u { | |||
| 358 | #define UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL | 670 | #define UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL |
| 359 | #define UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL | 671 | #define UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL |
| 360 | 672 | ||
| 673 | #define UV3H_EVENT_OCCURRED0_LB_HCERR_SHFT 0 | ||
| 674 | #define UV3H_EVENT_OCCURRED0_QP_HCERR_SHFT 1 | ||
| 675 | #define UV3H_EVENT_OCCURRED0_RH_HCERR_SHFT 2 | ||
| 676 | #define UV3H_EVENT_OCCURRED0_LH0_HCERR_SHFT 3 | ||
| 677 | #define UV3H_EVENT_OCCURRED0_LH1_HCERR_SHFT 4 | ||
| 678 | #define UV3H_EVENT_OCCURRED0_GR0_HCERR_SHFT 5 | ||
| 679 | #define UV3H_EVENT_OCCURRED0_GR1_HCERR_SHFT 6 | ||
| 680 | #define UV3H_EVENT_OCCURRED0_NI0_HCERR_SHFT 7 | ||
| 681 | #define UV3H_EVENT_OCCURRED0_NI1_HCERR_SHFT 8 | ||
| 682 | #define UV3H_EVENT_OCCURRED0_LB_AOERR0_SHFT 9 | ||
| 683 | #define UV3H_EVENT_OCCURRED0_QP_AOERR0_SHFT 10 | ||
| 684 | #define UV3H_EVENT_OCCURRED0_RH_AOERR0_SHFT 11 | ||
| 685 | #define UV3H_EVENT_OCCURRED0_LH0_AOERR0_SHFT 12 | ||
| 686 | #define UV3H_EVENT_OCCURRED0_LH1_AOERR0_SHFT 13 | ||
| 687 | #define UV3H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 14 | ||
| 688 | #define UV3H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 15 | ||
| 689 | #define UV3H_EVENT_OCCURRED0_XB_AOERR0_SHFT 16 | ||
| 690 | #define UV3H_EVENT_OCCURRED0_RT_AOERR0_SHFT 17 | ||
| 691 | #define UV3H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18 | ||
| 692 | #define UV3H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19 | ||
| 693 | #define UV3H_EVENT_OCCURRED0_LB_AOERR1_SHFT 20 | ||
| 694 | #define UV3H_EVENT_OCCURRED0_QP_AOERR1_SHFT 21 | ||
| 695 | #define UV3H_EVENT_OCCURRED0_RH_AOERR1_SHFT 22 | ||
| 696 | #define UV3H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23 | ||
| 697 | #define UV3H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24 | ||
| 698 | #define UV3H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25 | ||
| 699 | #define UV3H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26 | ||
| 700 | #define UV3H_EVENT_OCCURRED0_XB_AOERR1_SHFT 27 | ||
| 701 | #define UV3H_EVENT_OCCURRED0_RT_AOERR1_SHFT 28 | ||
| 702 | #define UV3H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29 | ||
| 703 | #define UV3H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30 | ||
| 704 | #define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31 | ||
| 705 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32 | ||
| 706 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33 | ||
| 707 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34 | ||
| 708 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35 | ||
| 709 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36 | ||
| 710 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37 | ||
| 711 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38 | ||
| 712 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39 | ||
| 713 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40 | ||
| 714 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41 | ||
| 715 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42 | ||
| 716 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43 | ||
| 717 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44 | ||
| 718 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45 | ||
| 719 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46 | ||
| 720 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47 | ||
| 721 | #define UV3H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48 | ||
| 722 | #define UV3H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49 | ||
| 723 | #define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50 | ||
| 724 | #define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51 | ||
| 725 | #define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52 | ||
| 726 | #define UV3H_EVENT_OCCURRED0_IPI_INT_SHFT 53 | ||
| 727 | #define UV3H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54 | ||
| 728 | #define UV3H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55 | ||
| 729 | #define UV3H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56 | ||
| 730 | #define UV3H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57 | ||
| 731 | #define UV3H_EVENT_OCCURRED0_PROFILE_INT_SHFT 58 | ||
| 732 | #define UV3H_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL | ||
| 733 | #define UV3H_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL | ||
| 734 | #define UV3H_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000004UL | ||
| 735 | #define UV3H_EVENT_OCCURRED0_LH0_HCERR_MASK 0x0000000000000008UL | ||
| 736 | #define UV3H_EVENT_OCCURRED0_LH1_HCERR_MASK 0x0000000000000010UL | ||
| 737 | #define UV3H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000020UL | ||
| 738 | #define UV3H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000040UL | ||
| 739 | #define UV3H_EVENT_OCCURRED0_NI0_HCERR_MASK 0x0000000000000080UL | ||
| 740 | #define UV3H_EVENT_OCCURRED0_NI1_HCERR_MASK 0x0000000000000100UL | ||
| 741 | #define UV3H_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000200UL | ||
| 742 | #define UV3H_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL | ||
| 743 | #define UV3H_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL | ||
| 744 | #define UV3H_EVENT_OCCURRED0_LH0_AOERR0_MASK 0x0000000000001000UL | ||
| 745 | #define UV3H_EVENT_OCCURRED0_LH1_AOERR0_MASK 0x0000000000002000UL | ||
| 746 | #define UV3H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000004000UL | ||
| 747 | #define UV3H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000008000UL | ||
| 748 | #define UV3H_EVENT_OCCURRED0_XB_AOERR0_MASK 0x0000000000010000UL | ||
| 749 | #define UV3H_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL | ||
| 750 | #define UV3H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL | ||
| 751 | #define UV3H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL | ||
| 752 | #define UV3H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL | ||
| 753 | #define UV3H_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL | ||
| 754 | #define UV3H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL | ||
| 755 | #define UV3H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL | ||
| 756 | #define UV3H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL | ||
| 757 | #define UV3H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL | ||
| 758 | #define UV3H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL | ||
| 759 | #define UV3H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL | ||
| 760 | #define UV3H_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL | ||
| 761 | #define UV3H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL | ||
| 762 | #define UV3H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL | ||
| 763 | #define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL | ||
| 764 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL | ||
| 765 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL | ||
| 766 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL | ||
| 767 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL | ||
| 768 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL | ||
| 769 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL | ||
| 770 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL | ||
| 771 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL | ||
| 772 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL | ||
| 773 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL | ||
| 774 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL | ||
| 775 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL | ||
| 776 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL | ||
| 777 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL | ||
| 778 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL | ||
| 779 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL | ||
| 780 | #define UV3H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL | ||
| 781 | #define UV3H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL | ||
| 782 | #define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL | ||
| 783 | #define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL | ||
| 784 | #define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL | ||
| 785 | #define UV3H_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL | ||
| 786 | #define UV3H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL | ||
| 787 | #define UV3H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL | ||
| 788 | #define UV3H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL | ||
| 789 | #define UV3H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL | ||
| 790 | #define UV3H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL | ||
| 791 | |||
| 361 | union uvh_event_occurred0_u { | 792 | union uvh_event_occurred0_u { |
| 362 | unsigned long v; | 793 | unsigned long v; |
| 794 | struct uvh_event_occurred0_s { | ||
| 795 | unsigned long lb_hcerr:1; /* RW, W1C */ | ||
| 796 | unsigned long rsvd_1_10:10; | ||
| 797 | unsigned long rh_aoerr0:1; /* RW, W1C */ | ||
| 798 | unsigned long rsvd_12_63:52; | ||
| 799 | } s; | ||
| 363 | struct uv1h_event_occurred0_s { | 800 | struct uv1h_event_occurred0_s { |
| 364 | unsigned long lb_hcerr:1; /* RW, W1C */ | 801 | unsigned long lb_hcerr:1; /* RW, W1C */ |
| 365 | unsigned long gr0_hcerr:1; /* RW, W1C */ | 802 | unsigned long gr0_hcerr:1; /* RW, W1C */ |
| @@ -420,6 +857,68 @@ union uvh_event_occurred0_u { | |||
| 420 | unsigned long power_management_req:1; /* RW, W1C */ | 857 | unsigned long power_management_req:1; /* RW, W1C */ |
| 421 | unsigned long rsvd_57_63:7; | 858 | unsigned long rsvd_57_63:7; |
| 422 | } s1; | 859 | } s1; |
| 860 | struct uvxh_event_occurred0_s { | ||
| 861 | unsigned long lb_hcerr:1; /* RW */ | ||
| 862 | unsigned long qp_hcerr:1; /* RW */ | ||
| 863 | unsigned long rh_hcerr:1; /* RW */ | ||
| 864 | unsigned long lh0_hcerr:1; /* RW */ | ||
| 865 | unsigned long lh1_hcerr:1; /* RW */ | ||
| 866 | unsigned long gr0_hcerr:1; /* RW */ | ||
| 867 | unsigned long gr1_hcerr:1; /* RW */ | ||
| 868 | unsigned long ni0_hcerr:1; /* RW */ | ||
| 869 | unsigned long ni1_hcerr:1; /* RW */ | ||
| 870 | unsigned long lb_aoerr0:1; /* RW */ | ||
| 871 | unsigned long qp_aoerr0:1; /* RW */ | ||
| 872 | unsigned long rh_aoerr0:1; /* RW */ | ||
| 873 | unsigned long lh0_aoerr0:1; /* RW */ | ||
| 874 | unsigned long lh1_aoerr0:1; /* RW */ | ||
| 875 | unsigned long gr0_aoerr0:1; /* RW */ | ||
| 876 | unsigned long gr1_aoerr0:1; /* RW */ | ||
| 877 | unsigned long xb_aoerr0:1; /* RW */ | ||
| 878 | unsigned long rt_aoerr0:1; /* RW */ | ||
| 879 | unsigned long ni0_aoerr0:1; /* RW */ | ||
| 880 | unsigned long ni1_aoerr0:1; /* RW */ | ||
| 881 | unsigned long lb_aoerr1:1; /* RW */ | ||
| 882 | unsigned long qp_aoerr1:1; /* RW */ | ||
| 883 | unsigned long rh_aoerr1:1; /* RW */ | ||
| 884 | unsigned long lh0_aoerr1:1; /* RW */ | ||
| 885 | unsigned long lh1_aoerr1:1; /* RW */ | ||
| 886 | unsigned long gr0_aoerr1:1; /* RW */ | ||
| 887 | unsigned long gr1_aoerr1:1; /* RW */ | ||
| 888 | unsigned long xb_aoerr1:1; /* RW */ | ||
| 889 | unsigned long rt_aoerr1:1; /* RW */ | ||
| 890 | unsigned long ni0_aoerr1:1; /* RW */ | ||
| 891 | unsigned long ni1_aoerr1:1; /* RW */ | ||
| 892 | unsigned long system_shutdown_int:1; /* RW */ | ||
| 893 | unsigned long lb_irq_int_0:1; /* RW */ | ||
| 894 | unsigned long lb_irq_int_1:1; /* RW */ | ||
| 895 | unsigned long lb_irq_int_2:1; /* RW */ | ||
| 896 | unsigned long lb_irq_int_3:1; /* RW */ | ||
| 897 | unsigned long lb_irq_int_4:1; /* RW */ | ||
| 898 | unsigned long lb_irq_int_5:1; /* RW */ | ||
| 899 | unsigned long lb_irq_int_6:1; /* RW */ | ||
| 900 | unsigned long lb_irq_int_7:1; /* RW */ | ||
| 901 | unsigned long lb_irq_int_8:1; /* RW */ | ||
| 902 | unsigned long lb_irq_int_9:1; /* RW */ | ||
| 903 | unsigned long lb_irq_int_10:1; /* RW */ | ||
| 904 | unsigned long lb_irq_int_11:1; /* RW */ | ||
| 905 | unsigned long lb_irq_int_12:1; /* RW */ | ||
| 906 | unsigned long lb_irq_int_13:1; /* RW */ | ||
| 907 | unsigned long lb_irq_int_14:1; /* RW */ | ||
| 908 | unsigned long lb_irq_int_15:1; /* RW */ | ||
| 909 | unsigned long l1_nmi_int:1; /* RW */ | ||
| 910 | unsigned long stop_clock:1; /* RW */ | ||
| 911 | unsigned long asic_to_l1:1; /* RW */ | ||
| 912 | unsigned long l1_to_asic:1; /* RW */ | ||
| 913 | unsigned long la_seq_trigger:1; /* RW */ | ||
| 914 | unsigned long ipi_int:1; /* RW */ | ||
| 915 | unsigned long extio_int0:1; /* RW */ | ||
| 916 | unsigned long extio_int1:1; /* RW */ | ||
| 917 | unsigned long extio_int2:1; /* RW */ | ||
| 918 | unsigned long extio_int3:1; /* RW */ | ||
| 919 | unsigned long profile_int:1; /* RW */ | ||
| 920 | unsigned long rsvd_59_63:5; | ||
| 921 | } sx; | ||
| 423 | struct uv2h_event_occurred0_s { | 922 | struct uv2h_event_occurred0_s { |
| 424 | unsigned long lb_hcerr:1; /* RW */ | 923 | unsigned long lb_hcerr:1; /* RW */ |
| 425 | unsigned long qp_hcerr:1; /* RW */ | 924 | unsigned long qp_hcerr:1; /* RW */ |
| @@ -482,18 +981,90 @@ union uvh_event_occurred0_u { | |||
| 482 | unsigned long profile_int:1; /* RW */ | 981 | unsigned long profile_int:1; /* RW */ |
| 483 | unsigned long rsvd_59_63:5; | 982 | unsigned long rsvd_59_63:5; |
| 484 | } s2; | 983 | } s2; |
| 984 | struct uv3h_event_occurred0_s { | ||
| 985 | unsigned long lb_hcerr:1; /* RW */ | ||
| 986 | unsigned long qp_hcerr:1; /* RW */ | ||
| 987 | unsigned long rh_hcerr:1; /* RW */ | ||
| 988 | unsigned long lh0_hcerr:1; /* RW */ | ||
| 989 | unsigned long lh1_hcerr:1; /* RW */ | ||
| 990 | unsigned long gr0_hcerr:1; /* RW */ | ||
| 991 | unsigned long gr1_hcerr:1; /* RW */ | ||
| 992 | unsigned long ni0_hcerr:1; /* RW */ | ||
| 993 | unsigned long ni1_hcerr:1; /* RW */ | ||
| 994 | unsigned long lb_aoerr0:1; /* RW */ | ||
| 995 | unsigned long qp_aoerr0:1; /* RW */ | ||
| 996 | unsigned long rh_aoerr0:1; /* RW */ | ||
| 997 | unsigned long lh0_aoerr0:1; /* RW */ | ||
| 998 | unsigned long lh1_aoerr0:1; /* RW */ | ||
| 999 | unsigned long gr0_aoerr0:1; /* RW */ | ||
| 1000 | unsigned long gr1_aoerr0:1; /* RW */ | ||
| 1001 | unsigned long xb_aoerr0:1; /* RW */ | ||
| 1002 | unsigned long rt_aoerr0:1; /* RW */ | ||
| 1003 | unsigned long ni0_aoerr0:1; /* RW */ | ||
| 1004 | unsigned long ni1_aoerr0:1; /* RW */ | ||
| 1005 | unsigned long lb_aoerr1:1; /* RW */ | ||
| 1006 | unsigned long qp_aoerr1:1; /* RW */ | ||
| 1007 | unsigned long rh_aoerr1:1; /* RW */ | ||
| 1008 | unsigned long lh0_aoerr1:1; /* RW */ | ||
| 1009 | unsigned long lh1_aoerr1:1; /* RW */ | ||
| 1010 | unsigned long gr0_aoerr1:1; /* RW */ | ||
| 1011 | unsigned long gr1_aoerr1:1; /* RW */ | ||
| 1012 | unsigned long xb_aoerr1:1; /* RW */ | ||
| 1013 | unsigned long rt_aoerr1:1; /* RW */ | ||
| 1014 | unsigned long ni0_aoerr1:1; /* RW */ | ||
| 1015 | unsigned long ni1_aoerr1:1; /* RW */ | ||
| 1016 | unsigned long system_shutdown_int:1; /* RW */ | ||
| 1017 | unsigned long lb_irq_int_0:1; /* RW */ | ||
| 1018 | unsigned long lb_irq_int_1:1; /* RW */ | ||
| 1019 | unsigned long lb_irq_int_2:1; /* RW */ | ||
| 1020 | unsigned long lb_irq_int_3:1; /* RW */ | ||
| 1021 | unsigned long lb_irq_int_4:1; /* RW */ | ||
| 1022 | unsigned long lb_irq_int_5:1; /* RW */ | ||
| 1023 | unsigned long lb_irq_int_6:1; /* RW */ | ||
| 1024 | unsigned long lb_irq_int_7:1; /* RW */ | ||
| 1025 | unsigned long lb_irq_int_8:1; /* RW */ | ||
| 1026 | unsigned long lb_irq_int_9:1; /* RW */ | ||
| 1027 | unsigned long lb_irq_int_10:1; /* RW */ | ||
| 1028 | unsigned long lb_irq_int_11:1; /* RW */ | ||
| 1029 | unsigned long lb_irq_int_12:1; /* RW */ | ||
| 1030 | unsigned long lb_irq_int_13:1; /* RW */ | ||
| 1031 | unsigned long lb_irq_int_14:1; /* RW */ | ||
| 1032 | unsigned long lb_irq_int_15:1; /* RW */ | ||
| 1033 | unsigned long l1_nmi_int:1; /* RW */ | ||
| 1034 | unsigned long stop_clock:1; /* RW */ | ||
| 1035 | unsigned long asic_to_l1:1; /* RW */ | ||
| 1036 | unsigned long l1_to_asic:1; /* RW */ | ||
| 1037 | unsigned long la_seq_trigger:1; /* RW */ | ||
| 1038 | unsigned long ipi_int:1; /* RW */ | ||
| 1039 | unsigned long extio_int0:1; /* RW */ | ||
| 1040 | unsigned long extio_int1:1; /* RW */ | ||
| 1041 | unsigned long extio_int2:1; /* RW */ | ||
| 1042 | unsigned long extio_int3:1; /* RW */ | ||
| 1043 | unsigned long profile_int:1; /* RW */ | ||
| 1044 | unsigned long rsvd_59_63:5; | ||
| 1045 | } s3; | ||
| 485 | }; | 1046 | }; |
| 486 | 1047 | ||
| 487 | /* ========================================================================= */ | 1048 | /* ========================================================================= */ |
| 488 | /* UVH_EVENT_OCCURRED0_ALIAS */ | 1049 | /* UVH_EVENT_OCCURRED0_ALIAS */ |
| 489 | /* ========================================================================= */ | 1050 | /* ========================================================================= */ |
| 490 | #define UVH_EVENT_OCCURRED0_ALIAS 0x0000000000070008UL | 1051 | #define UVH_EVENT_OCCURRED0_ALIAS 0x70008UL |
| 491 | #define UVH_EVENT_OCCURRED0_ALIAS_32 0x5f0 | 1052 | #define UV1H_EVENT_OCCURRED0_ALIAS 0x70008UL |
| 1053 | #define UV2H_EVENT_OCCURRED0_ALIAS 0x70008UL | ||
| 1054 | #define UV3H_EVENT_OCCURRED0_ALIAS 0x70008UL | ||
| 1055 | #define UVH_EVENT_OCCURRED0_ALIAS_32 0x5f0 | ||
| 1056 | #define UV1H_EVENT_OCCURRED0_ALIAS_32 0x70008UL | ||
| 1057 | #define UV2H_EVENT_OCCURRED0_ALIAS_32 0x70008UL | ||
| 1058 | #define UV3H_EVENT_OCCURRED0_ALIAS_32 0x70008UL | ||
| 1059 | |||
| 492 | 1060 | ||
| 493 | /* ========================================================================= */ | 1061 | /* ========================================================================= */ |
| 494 | /* UVH_GR0_TLB_INT0_CONFIG */ | 1062 | /* UVH_GR0_TLB_INT0_CONFIG */ |
| 495 | /* ========================================================================= */ | 1063 | /* ========================================================================= */ |
| 496 | #define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL | 1064 | #define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL |
| 1065 | #define UV1H_GR0_TLB_INT0_CONFIG 0x61b00UL | ||
| 1066 | #define UV2H_GR0_TLB_INT0_CONFIG 0x61b00UL | ||
| 1067 | #define UV3H_GR0_TLB_INT0_CONFIG 0x61b00UL | ||
| 497 | 1068 | ||
| 498 | #define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0 | 1069 | #define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0 |
| 499 | #define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT 8 | 1070 | #define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT 8 |
| @@ -512,6 +1083,74 @@ union uvh_event_occurred0_u { | |||
| 512 | #define UVH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL | 1083 | #define UVH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL |
| 513 | #define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | 1084 | #define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL |
| 514 | 1085 | ||
| 1086 | #define UV1H_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0 | ||
| 1087 | #define UV1H_GR0_TLB_INT0_CONFIG_DM_SHFT 8 | ||
| 1088 | #define UV1H_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11 | ||
| 1089 | #define UV1H_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12 | ||
| 1090 | #define UV1H_GR0_TLB_INT0_CONFIG_P_SHFT 13 | ||
| 1091 | #define UV1H_GR0_TLB_INT0_CONFIG_T_SHFT 15 | ||
| 1092 | #define UV1H_GR0_TLB_INT0_CONFIG_M_SHFT 16 | ||
| 1093 | #define UV1H_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32 | ||
| 1094 | #define UV1H_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL | ||
| 1095 | #define UV1H_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL | ||
| 1096 | #define UV1H_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL | ||
| 1097 | #define UV1H_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL | ||
| 1098 | #define UV1H_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL | ||
| 1099 | #define UV1H_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL | ||
| 1100 | #define UV1H_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL | ||
| 1101 | #define UV1H_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | ||
| 1102 | |||
| 1103 | #define UVXH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0 | ||
| 1104 | #define UVXH_GR0_TLB_INT0_CONFIG_DM_SHFT 8 | ||
| 1105 | #define UVXH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11 | ||
| 1106 | #define UVXH_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12 | ||
| 1107 | #define UVXH_GR0_TLB_INT0_CONFIG_P_SHFT 13 | ||
| 1108 | #define UVXH_GR0_TLB_INT0_CONFIG_T_SHFT 15 | ||
| 1109 | #define UVXH_GR0_TLB_INT0_CONFIG_M_SHFT 16 | ||
| 1110 | #define UVXH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32 | ||
| 1111 | #define UVXH_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL | ||
| 1112 | #define UVXH_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL | ||
| 1113 | #define UVXH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL | ||
| 1114 | #define UVXH_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL | ||
| 1115 | #define UVXH_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL | ||
| 1116 | #define UVXH_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL | ||
| 1117 | #define UVXH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL | ||
| 1118 | #define UVXH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | ||
| 1119 | |||
| 1120 | #define UV2H_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0 | ||
| 1121 | #define UV2H_GR0_TLB_INT0_CONFIG_DM_SHFT 8 | ||
| 1122 | #define UV2H_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11 | ||
| 1123 | #define UV2H_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12 | ||
| 1124 | #define UV2H_GR0_TLB_INT0_CONFIG_P_SHFT 13 | ||
| 1125 | #define UV2H_GR0_TLB_INT0_CONFIG_T_SHFT 15 | ||
| 1126 | #define UV2H_GR0_TLB_INT0_CONFIG_M_SHFT 16 | ||
| 1127 | #define UV2H_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32 | ||
| 1128 | #define UV2H_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL | ||
| 1129 | #define UV2H_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL | ||
| 1130 | #define UV2H_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL | ||
| 1131 | #define UV2H_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL | ||
| 1132 | #define UV2H_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL | ||
| 1133 | #define UV2H_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL | ||
| 1134 | #define UV2H_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL | ||
| 1135 | #define UV2H_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | ||
| 1136 | |||
| 1137 | #define UV3H_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0 | ||
| 1138 | #define UV3H_GR0_TLB_INT0_CONFIG_DM_SHFT 8 | ||
| 1139 | #define UV3H_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11 | ||
| 1140 | #define UV3H_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12 | ||
| 1141 | #define UV3H_GR0_TLB_INT0_CONFIG_P_SHFT 13 | ||
| 1142 | #define UV3H_GR0_TLB_INT0_CONFIG_T_SHFT 15 | ||
| 1143 | #define UV3H_GR0_TLB_INT0_CONFIG_M_SHFT 16 | ||
| 1144 | #define UV3H_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32 | ||
| 1145 | #define UV3H_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL | ||
| 1146 | #define UV3H_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL | ||
| 1147 | #define UV3H_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL | ||
| 1148 | #define UV3H_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL | ||
| 1149 | #define UV3H_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL | ||
| 1150 | #define UV3H_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL | ||
| 1151 | #define UV3H_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL | ||
| 1152 | #define UV3H_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | ||
| 1153 | |||
| 515 | union uvh_gr0_tlb_int0_config_u { | 1154 | union uvh_gr0_tlb_int0_config_u { |
| 516 | unsigned long v; | 1155 | unsigned long v; |
| 517 | struct uvh_gr0_tlb_int0_config_s { | 1156 | struct uvh_gr0_tlb_int0_config_s { |
| @@ -526,12 +1165,63 @@ union uvh_gr0_tlb_int0_config_u { | |||
| 526 | unsigned long rsvd_17_31:15; | 1165 | unsigned long rsvd_17_31:15; |
| 527 | unsigned long apic_id:32; /* RW */ | 1166 | unsigned long apic_id:32; /* RW */ |
| 528 | } s; | 1167 | } s; |
| 1168 | struct uv1h_gr0_tlb_int0_config_s { | ||
| 1169 | unsigned long vector_:8; /* RW */ | ||
| 1170 | unsigned long dm:3; /* RW */ | ||
| 1171 | unsigned long destmode:1; /* RW */ | ||
| 1172 | unsigned long status:1; /* RO */ | ||
| 1173 | unsigned long p:1; /* RO */ | ||
| 1174 | unsigned long rsvd_14:1; | ||
| 1175 | unsigned long t:1; /* RO */ | ||
| 1176 | unsigned long m:1; /* RW */ | ||
| 1177 | unsigned long rsvd_17_31:15; | ||
| 1178 | unsigned long apic_id:32; /* RW */ | ||
| 1179 | } s1; | ||
| 1180 | struct uvxh_gr0_tlb_int0_config_s { | ||
| 1181 | unsigned long vector_:8; /* RW */ | ||
| 1182 | unsigned long dm:3; /* RW */ | ||
| 1183 | unsigned long destmode:1; /* RW */ | ||
| 1184 | unsigned long status:1; /* RO */ | ||
| 1185 | unsigned long p:1; /* RO */ | ||
| 1186 | unsigned long rsvd_14:1; | ||
| 1187 | unsigned long t:1; /* RO */ | ||
| 1188 | unsigned long m:1; /* RW */ | ||
| 1189 | unsigned long rsvd_17_31:15; | ||
| 1190 | unsigned long apic_id:32; /* RW */ | ||
| 1191 | } sx; | ||
| 1192 | struct uv2h_gr0_tlb_int0_config_s { | ||
| 1193 | unsigned long vector_:8; /* RW */ | ||
| 1194 | unsigned long dm:3; /* RW */ | ||
| 1195 | unsigned long destmode:1; /* RW */ | ||
| 1196 | unsigned long status:1; /* RO */ | ||
| 1197 | unsigned long p:1; /* RO */ | ||
| 1198 | unsigned long rsvd_14:1; | ||
| 1199 | unsigned long t:1; /* RO */ | ||
| 1200 | unsigned long m:1; /* RW */ | ||
| 1201 | unsigned long rsvd_17_31:15; | ||
| 1202 | unsigned long apic_id:32; /* RW */ | ||
| 1203 | } s2; | ||
| 1204 | struct uv3h_gr0_tlb_int0_config_s { | ||
| 1205 | unsigned long vector_:8; /* RW */ | ||
| 1206 | unsigned long dm:3; /* RW */ | ||
| 1207 | unsigned long destmode:1; /* RW */ | ||
| 1208 | unsigned long status:1; /* RO */ | ||
| 1209 | unsigned long p:1; /* RO */ | ||
| 1210 | unsigned long rsvd_14:1; | ||
| 1211 | unsigned long t:1; /* RO */ | ||
| 1212 | unsigned long m:1; /* RW */ | ||
| 1213 | unsigned long rsvd_17_31:15; | ||
| 1214 | unsigned long apic_id:32; /* RW */ | ||
| 1215 | } s3; | ||
| 529 | }; | 1216 | }; |
| 530 | 1217 | ||
| 531 | /* ========================================================================= */ | 1218 | /* ========================================================================= */ |
| 532 | /* UVH_GR0_TLB_INT1_CONFIG */ | 1219 | /* UVH_GR0_TLB_INT1_CONFIG */ |
| 533 | /* ========================================================================= */ | 1220 | /* ========================================================================= */ |
| 534 | #define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL | 1221 | #define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL |
| 1222 | #define UV1H_GR0_TLB_INT1_CONFIG 0x61b40UL | ||
| 1223 | #define UV2H_GR0_TLB_INT1_CONFIG 0x61b40UL | ||
| 1224 | #define UV3H_GR0_TLB_INT1_CONFIG 0x61b40UL | ||
| 535 | 1225 | ||
| 536 | #define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0 | 1226 | #define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0 |
| 537 | #define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT 8 | 1227 | #define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT 8 |
| @@ -550,6 +1240,74 @@ union uvh_gr0_tlb_int0_config_u { | |||
| 550 | #define UVH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL | 1240 | #define UVH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL |
| 551 | #define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | 1241 | #define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL |
| 552 | 1242 | ||
| 1243 | #define UV1H_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0 | ||
| 1244 | #define UV1H_GR0_TLB_INT1_CONFIG_DM_SHFT 8 | ||
| 1245 | #define UV1H_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT 11 | ||
| 1246 | #define UV1H_GR0_TLB_INT1_CONFIG_STATUS_SHFT 12 | ||
| 1247 | #define UV1H_GR0_TLB_INT1_CONFIG_P_SHFT 13 | ||
| 1248 | #define UV1H_GR0_TLB_INT1_CONFIG_T_SHFT 15 | ||
| 1249 | #define UV1H_GR0_TLB_INT1_CONFIG_M_SHFT 16 | ||
| 1250 | #define UV1H_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT 32 | ||
| 1251 | #define UV1H_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL | ||
| 1252 | #define UV1H_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL | ||
| 1253 | #define UV1H_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL | ||
| 1254 | #define UV1H_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL | ||
| 1255 | #define UV1H_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL | ||
| 1256 | #define UV1H_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL | ||
| 1257 | #define UV1H_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL | ||
| 1258 | #define UV1H_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | ||
| 1259 | |||
| 1260 | #define UVXH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0 | ||
| 1261 | #define UVXH_GR0_TLB_INT1_CONFIG_DM_SHFT 8 | ||
| 1262 | #define UVXH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT 11 | ||
| 1263 | #define UVXH_GR0_TLB_INT1_CONFIG_STATUS_SHFT 12 | ||
| 1264 | #define UVXH_GR0_TLB_INT1_CONFIG_P_SHFT 13 | ||
| 1265 | #define UVXH_GR0_TLB_INT1_CONFIG_T_SHFT 15 | ||
| 1266 | #define UVXH_GR0_TLB_INT1_CONFIG_M_SHFT 16 | ||
| 1267 | #define UVXH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT 32 | ||
| 1268 | #define UVXH_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL | ||
| 1269 | #define UVXH_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL | ||
| 1270 | #define UVXH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL | ||
| 1271 | #define UVXH_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL | ||
| 1272 | #define UVXH_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL | ||
| 1273 | #define UVXH_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL | ||
| 1274 | #define UVXH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL | ||
| 1275 | #define UVXH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | ||
| 1276 | |||
| 1277 | #define UV2H_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0 | ||
| 1278 | #define UV2H_GR0_TLB_INT1_CONFIG_DM_SHFT 8 | ||
| 1279 | #define UV2H_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT 11 | ||
| 1280 | #define UV2H_GR0_TLB_INT1_CONFIG_STATUS_SHFT 12 | ||
| 1281 | #define UV2H_GR0_TLB_INT1_CONFIG_P_SHFT 13 | ||
| 1282 | #define UV2H_GR0_TLB_INT1_CONFIG_T_SHFT 15 | ||
| 1283 | #define UV2H_GR0_TLB_INT1_CONFIG_M_SHFT 16 | ||
| 1284 | #define UV2H_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT 32 | ||
| 1285 | #define UV2H_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL | ||
| 1286 | #define UV2H_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL | ||
| 1287 | #define UV2H_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL | ||
| 1288 | #define UV2H_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL | ||
| 1289 | #define UV2H_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL | ||
| 1290 | #define UV2H_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL | ||
| 1291 | #define UV2H_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL | ||
| 1292 | #define UV2H_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | ||
| 1293 | |||
| 1294 | #define UV3H_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0 | ||
| 1295 | #define UV3H_GR0_TLB_INT1_CONFIG_DM_SHFT 8 | ||
| 1296 | #define UV3H_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT 11 | ||
| 1297 | #define UV3H_GR0_TLB_INT1_CONFIG_STATUS_SHFT 12 | ||
| 1298 | #define UV3H_GR0_TLB_INT1_CONFIG_P_SHFT 13 | ||
| 1299 | #define UV3H_GR0_TLB_INT1_CONFIG_T_SHFT 15 | ||
| 1300 | #define UV3H_GR0_TLB_INT1_CONFIG_M_SHFT 16 | ||
| 1301 | #define UV3H_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT 32 | ||
| 1302 | #define UV3H_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL | ||
| 1303 | #define UV3H_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL | ||
| 1304 | #define UV3H_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL | ||
| 1305 | #define UV3H_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL | ||
| 1306 | #define UV3H_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL | ||
| 1307 | #define UV3H_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL | ||
| 1308 | #define UV3H_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL | ||
| 1309 | #define UV3H_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | ||
| 1310 | |||
| 553 | union uvh_gr0_tlb_int1_config_u { | 1311 | union uvh_gr0_tlb_int1_config_u { |
| 554 | unsigned long v; | 1312 | unsigned long v; |
| 555 | struct uvh_gr0_tlb_int1_config_s { | 1313 | struct uvh_gr0_tlb_int1_config_s { |
| @@ -564,6 +1322,54 @@ union uvh_gr0_tlb_int1_config_u { | |||
| 564 | unsigned long rsvd_17_31:15; | 1322 | unsigned long rsvd_17_31:15; |
| 565 | unsigned long apic_id:32; /* RW */ | 1323 | unsigned long apic_id:32; /* RW */ |
| 566 | } s; | 1324 | } s; |
| 1325 | struct uv1h_gr0_tlb_int1_config_s { | ||
| 1326 | unsigned long vector_:8; /* RW */ | ||
| 1327 | unsigned long dm:3; /* RW */ | ||
| 1328 | unsigned long destmode:1; /* RW */ | ||
| 1329 | unsigned long status:1; /* RO */ | ||
| 1330 | unsigned long p:1; /* RO */ | ||
| 1331 | unsigned long rsvd_14:1; | ||
| 1332 | unsigned long t:1; /* RO */ | ||
| 1333 | unsigned long m:1; /* RW */ | ||
| 1334 | unsigned long rsvd_17_31:15; | ||
| 1335 | unsigned long apic_id:32; /* RW */ | ||
| 1336 | } s1; | ||
| 1337 | struct uvxh_gr0_tlb_int1_config_s { | ||
| 1338 | unsigned long vector_:8; /* RW */ | ||
| 1339 | unsigned long dm:3; /* RW */ | ||
| 1340 | unsigned long destmode:1; /* RW */ | ||
| 1341 | unsigned long status:1; /* RO */ | ||
| 1342 | unsigned long p:1; /* RO */ | ||
| 1343 | unsigned long rsvd_14:1; | ||
| 1344 | unsigned long t:1; /* RO */ | ||
| 1345 | unsigned long m:1; /* RW */ | ||
| 1346 | unsigned long rsvd_17_31:15; | ||
| 1347 | unsigned long apic_id:32; /* RW */ | ||
| 1348 | } sx; | ||
| 1349 | struct uv2h_gr0_tlb_int1_config_s { | ||
| 1350 | unsigned long vector_:8; /* RW */ | ||
| 1351 | unsigned long dm:3; /* RW */ | ||
| 1352 | unsigned long destmode:1; /* RW */ | ||
| 1353 | unsigned long status:1; /* RO */ | ||
| 1354 | unsigned long p:1; /* RO */ | ||
| 1355 | unsigned long rsvd_14:1; | ||
| 1356 | unsigned long t:1; /* RO */ | ||
| 1357 | unsigned long m:1; /* RW */ | ||
| 1358 | unsigned long rsvd_17_31:15; | ||
| 1359 | unsigned long apic_id:32; /* RW */ | ||
| 1360 | } s2; | ||
| 1361 | struct uv3h_gr0_tlb_int1_config_s { | ||
| 1362 | unsigned long vector_:8; /* RW */ | ||
| 1363 | unsigned long dm:3; /* RW */ | ||
| 1364 | unsigned long destmode:1; /* RW */ | ||
| 1365 | unsigned long status:1; /* RO */ | ||
| 1366 | unsigned long p:1; /* RO */ | ||
| 1367 | unsigned long rsvd_14:1; | ||
| 1368 | unsigned long t:1; /* RO */ | ||
| 1369 | unsigned long m:1; /* RW */ | ||
| 1370 | unsigned long rsvd_17_31:15; | ||
| 1371 | unsigned long apic_id:32; /* RW */ | ||
| 1372 | } s3; | ||
| 567 | }; | 1373 | }; |
| 568 | 1374 | ||
| 569 | /* ========================================================================= */ | 1375 | /* ========================================================================= */ |
| @@ -571,9 +1377,11 @@ union uvh_gr0_tlb_int1_config_u { | |||
| 571 | /* ========================================================================= */ | 1377 | /* ========================================================================= */ |
| 572 | #define UV1H_GR0_TLB_MMR_CONTROL 0x401080UL | 1378 | #define UV1H_GR0_TLB_MMR_CONTROL 0x401080UL |
| 573 | #define UV2H_GR0_TLB_MMR_CONTROL 0xc01080UL | 1379 | #define UV2H_GR0_TLB_MMR_CONTROL 0xc01080UL |
| 574 | #define UVH_GR0_TLB_MMR_CONTROL (is_uv1_hub() ? \ | 1380 | #define UV3H_GR0_TLB_MMR_CONTROL 0xc01080UL |
| 575 | UV1H_GR0_TLB_MMR_CONTROL : \ | 1381 | #define UVH_GR0_TLB_MMR_CONTROL \ |
| 576 | UV2H_GR0_TLB_MMR_CONTROL) | 1382 | (is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL : \ |
| 1383 | (is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL : \ | ||
| 1384 | UV3H_GR0_TLB_MMR_CONTROL)) | ||
| 577 | 1385 | ||
| 578 | #define UVH_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 | 1386 | #define UVH_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 |
| 579 | #define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 | 1387 | #define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 |
| @@ -611,6 +1419,21 @@ union uvh_gr0_tlb_int1_config_u { | |||
| 611 | #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK 0x0100000000000000UL | 1419 | #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK 0x0100000000000000UL |
| 612 | #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK 0x1000000000000000UL | 1420 | #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK 0x1000000000000000UL |
| 613 | 1421 | ||
| 1422 | #define UVXH_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 | ||
| 1423 | #define UVXH_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 | ||
| 1424 | #define UVXH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 | ||
| 1425 | #define UVXH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 | ||
| 1426 | #define UVXH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 | ||
| 1427 | #define UVXH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31 | ||
| 1428 | #define UVXH_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 | ||
| 1429 | #define UVXH_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL | ||
| 1430 | #define UVXH_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL | ||
| 1431 | #define UVXH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL | ||
| 1432 | #define UVXH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL | ||
| 1433 | #define UVXH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL | ||
| 1434 | #define UVXH_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL | ||
| 1435 | #define UVXH_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL | ||
| 1436 | |||
| 614 | #define UV2H_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 | 1437 | #define UV2H_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 |
| 615 | #define UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 | 1438 | #define UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 |
| 616 | #define UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 | 1439 | #define UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 |
| @@ -630,6 +1453,23 @@ union uvh_gr0_tlb_int1_config_u { | |||
| 630 | #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL | 1453 | #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL |
| 631 | #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL | 1454 | #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL |
| 632 | 1455 | ||
| 1456 | #define UV3H_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 | ||
| 1457 | #define UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 | ||
| 1458 | #define UV3H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 | ||
| 1459 | #define UV3H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 | ||
| 1460 | #define UV3H_GR0_TLB_MMR_CONTROL_ECC_SEL_SHFT 21 | ||
| 1461 | #define UV3H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 | ||
| 1462 | #define UV3H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31 | ||
| 1463 | #define UV3H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 | ||
| 1464 | #define UV3H_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL | ||
| 1465 | #define UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL | ||
| 1466 | #define UV3H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL | ||
| 1467 | #define UV3H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL | ||
| 1468 | #define UV3H_GR0_TLB_MMR_CONTROL_ECC_SEL_MASK 0x0000000000200000UL | ||
| 1469 | #define UV3H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL | ||
| 1470 | #define UV3H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL | ||
| 1471 | #define UV3H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL | ||
| 1472 | |||
| 633 | union uvh_gr0_tlb_mmr_control_u { | 1473 | union uvh_gr0_tlb_mmr_control_u { |
| 634 | unsigned long v; | 1474 | unsigned long v; |
| 635 | struct uvh_gr0_tlb_mmr_control_s { | 1475 | struct uvh_gr0_tlb_mmr_control_s { |
| @@ -642,7 +1482,9 @@ union uvh_gr0_tlb_mmr_control_u { | |||
| 642 | unsigned long rsvd_21_29:9; | 1482 | unsigned long rsvd_21_29:9; |
| 643 | unsigned long mmr_write:1; /* WP */ | 1483 | unsigned long mmr_write:1; /* WP */ |
| 644 | unsigned long mmr_read:1; /* WP */ | 1484 | unsigned long mmr_read:1; /* WP */ |
| 645 | unsigned long rsvd_32_63:32; | 1485 | unsigned long rsvd_32_48:17; |
| 1486 | unsigned long rsvd_49_51:3; | ||
| 1487 | unsigned long rsvd_52_63:12; | ||
| 646 | } s; | 1488 | } s; |
| 647 | struct uv1h_gr0_tlb_mmr_control_s { | 1489 | struct uv1h_gr0_tlb_mmr_control_s { |
| 648 | unsigned long index:12; /* RW */ | 1490 | unsigned long index:12; /* RW */ |
| @@ -666,6 +1508,23 @@ union uvh_gr0_tlb_mmr_control_u { | |||
| 666 | unsigned long mmr_inj_tlblruv:1; /* RW */ | 1508 | unsigned long mmr_inj_tlblruv:1; /* RW */ |
| 667 | unsigned long rsvd_61_63:3; | 1509 | unsigned long rsvd_61_63:3; |
| 668 | } s1; | 1510 | } s1; |
| 1511 | struct uvxh_gr0_tlb_mmr_control_s { | ||
| 1512 | unsigned long index:12; /* RW */ | ||
| 1513 | unsigned long mem_sel:2; /* RW */ | ||
| 1514 | unsigned long rsvd_14_15:2; | ||
| 1515 | unsigned long auto_valid_en:1; /* RW */ | ||
| 1516 | unsigned long rsvd_17_19:3; | ||
| 1517 | unsigned long mmr_hash_index_en:1; /* RW */ | ||
| 1518 | unsigned long rsvd_21_29:9; | ||
| 1519 | unsigned long mmr_write:1; /* WP */ | ||
| 1520 | unsigned long mmr_read:1; /* WP */ | ||
| 1521 | unsigned long mmr_op_done:1; /* RW */ | ||
| 1522 | unsigned long rsvd_33_47:15; | ||
| 1523 | unsigned long rsvd_48:1; | ||
| 1524 | unsigned long rsvd_49_51:3; | ||
| 1525 | unsigned long rsvd_52:1; | ||
| 1526 | unsigned long rsvd_53_63:11; | ||
| 1527 | } sx; | ||
| 669 | struct uv2h_gr0_tlb_mmr_control_s { | 1528 | struct uv2h_gr0_tlb_mmr_control_s { |
| 670 | unsigned long index:12; /* RW */ | 1529 | unsigned long index:12; /* RW */ |
| 671 | unsigned long mem_sel:2; /* RW */ | 1530 | unsigned long mem_sel:2; /* RW */ |
| @@ -683,6 +1542,24 @@ union uvh_gr0_tlb_mmr_control_u { | |||
| 683 | unsigned long mmr_inj_tlbram:1; /* RW */ | 1542 | unsigned long mmr_inj_tlbram:1; /* RW */ |
| 684 | unsigned long rsvd_53_63:11; | 1543 | unsigned long rsvd_53_63:11; |
| 685 | } s2; | 1544 | } s2; |
| 1545 | struct uv3h_gr0_tlb_mmr_control_s { | ||
| 1546 | unsigned long index:12; /* RW */ | ||
| 1547 | unsigned long mem_sel:2; /* RW */ | ||
| 1548 | unsigned long rsvd_14_15:2; | ||
| 1549 | unsigned long auto_valid_en:1; /* RW */ | ||
| 1550 | unsigned long rsvd_17_19:3; | ||
| 1551 | unsigned long mmr_hash_index_en:1; /* RW */ | ||
| 1552 | unsigned long ecc_sel:1; /* RW */ | ||
| 1553 | unsigned long rsvd_22_29:8; | ||
| 1554 | unsigned long mmr_write:1; /* WP */ | ||
| 1555 | unsigned long mmr_read:1; /* WP */ | ||
| 1556 | unsigned long mmr_op_done:1; /* RW */ | ||
| 1557 | unsigned long rsvd_33_47:15; | ||
| 1558 | unsigned long undef_48:1; /* Undefined */ | ||
| 1559 | unsigned long rsvd_49_51:3; | ||
| 1560 | unsigned long undef_52:1; /* Undefined */ | ||
| 1561 | unsigned long rsvd_53_63:11; | ||
| 1562 | } s3; | ||
| 686 | }; | 1563 | }; |
| 687 | 1564 | ||
| 688 | /* ========================================================================= */ | 1565 | /* ========================================================================= */ |
| @@ -690,9 +1567,11 @@ union uvh_gr0_tlb_mmr_control_u { | |||
| 690 | /* ========================================================================= */ | 1567 | /* ========================================================================= */ |
| 691 | #define UV1H_GR0_TLB_MMR_READ_DATA_HI 0x4010a0UL | 1568 | #define UV1H_GR0_TLB_MMR_READ_DATA_HI 0x4010a0UL |
| 692 | #define UV2H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL | 1569 | #define UV2H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL |
| 693 | #define UVH_GR0_TLB_MMR_READ_DATA_HI (is_uv1_hub() ? \ | 1570 | #define UV3H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL |
| 694 | UV1H_GR0_TLB_MMR_READ_DATA_HI : \ | 1571 | #define UVH_GR0_TLB_MMR_READ_DATA_HI \ |
| 695 | UV2H_GR0_TLB_MMR_READ_DATA_HI) | 1572 | (is_uv1_hub() ? UV1H_GR0_TLB_MMR_READ_DATA_HI : \ |
| 1573 | (is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_HI : \ | ||
| 1574 | UV3H_GR0_TLB_MMR_READ_DATA_HI)) | ||
| 696 | 1575 | ||
| 697 | #define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 | 1576 | #define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 |
| 698 | #define UVH_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 | 1577 | #define UVH_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 |
| @@ -703,6 +1582,46 @@ union uvh_gr0_tlb_mmr_control_u { | |||
| 703 | #define UVH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL | 1582 | #define UVH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL |
| 704 | #define UVH_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL | 1583 | #define UVH_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL |
| 705 | 1584 | ||
| 1585 | #define UV1H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 | ||
| 1586 | #define UV1H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 | ||
| 1587 | #define UV1H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 | ||
| 1588 | #define UV1H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 | ||
| 1589 | #define UV1H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL | ||
| 1590 | #define UV1H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL | ||
| 1591 | #define UV1H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL | ||
| 1592 | #define UV1H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL | ||
| 1593 | |||
| 1594 | #define UVXH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 | ||
| 1595 | #define UVXH_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 | ||
| 1596 | #define UVXH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 | ||
| 1597 | #define UVXH_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 | ||
| 1598 | #define UVXH_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL | ||
| 1599 | #define UVXH_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL | ||
| 1600 | #define UVXH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL | ||
| 1601 | #define UVXH_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL | ||
| 1602 | |||
| 1603 | #define UV2H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 | ||
| 1604 | #define UV2H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 | ||
| 1605 | #define UV2H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 | ||
| 1606 | #define UV2H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 | ||
| 1607 | #define UV2H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL | ||
| 1608 | #define UV2H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL | ||
| 1609 | #define UV2H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL | ||
| 1610 | #define UV2H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL | ||
| 1611 | |||
| 1612 | #define UV3H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 | ||
| 1613 | #define UV3H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 | ||
| 1614 | #define UV3H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 | ||
| 1615 | #define UV3H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 | ||
| 1616 | #define UV3H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT 45 | ||
| 1617 | #define UV3H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT 55 | ||
| 1618 | #define UV3H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL | ||
| 1619 | #define UV3H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL | ||
| 1620 | #define UV3H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL | ||
| 1621 | #define UV3H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL | ||
| 1622 | #define UV3H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_MASK 0x0000200000000000UL | ||
| 1623 | #define UV3H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK 0xff80000000000000UL | ||
| 1624 | |||
| 706 | union uvh_gr0_tlb_mmr_read_data_hi_u { | 1625 | union uvh_gr0_tlb_mmr_read_data_hi_u { |
| 707 | unsigned long v; | 1626 | unsigned long v; |
| 708 | struct uvh_gr0_tlb_mmr_read_data_hi_s { | 1627 | struct uvh_gr0_tlb_mmr_read_data_hi_s { |
| @@ -712,6 +1631,36 @@ union uvh_gr0_tlb_mmr_read_data_hi_u { | |||
| 712 | unsigned long larger:1; /* RO */ | 1631 | unsigned long larger:1; /* RO */ |
| 713 | unsigned long rsvd_45_63:19; | 1632 | unsigned long rsvd_45_63:19; |
| 714 | } s; | 1633 | } s; |
| 1634 | struct uv1h_gr0_tlb_mmr_read_data_hi_s { | ||
| 1635 | unsigned long pfn:41; /* RO */ | ||
| 1636 | unsigned long gaa:2; /* RO */ | ||
| 1637 | unsigned long dirty:1; /* RO */ | ||
| 1638 | unsigned long larger:1; /* RO */ | ||
| 1639 | unsigned long rsvd_45_63:19; | ||
| 1640 | } s1; | ||
| 1641 | struct uvxh_gr0_tlb_mmr_read_data_hi_s { | ||
| 1642 | unsigned long pfn:41; /* RO */ | ||
| 1643 | unsigned long gaa:2; /* RO */ | ||
| 1644 | unsigned long dirty:1; /* RO */ | ||
| 1645 | unsigned long larger:1; /* RO */ | ||
| 1646 | unsigned long rsvd_45_63:19; | ||
| 1647 | } sx; | ||
| 1648 | struct uv2h_gr0_tlb_mmr_read_data_hi_s { | ||
| 1649 | unsigned long pfn:41; /* RO */ | ||
| 1650 | unsigned long gaa:2; /* RO */ | ||
| 1651 | unsigned long dirty:1; /* RO */ | ||
| 1652 | unsigned long larger:1; /* RO */ | ||
| 1653 | unsigned long rsvd_45_63:19; | ||
| 1654 | } s2; | ||
| 1655 | struct uv3h_gr0_tlb_mmr_read_data_hi_s { | ||
| 1656 | unsigned long pfn:41; /* RO */ | ||
| 1657 | unsigned long gaa:2; /* RO */ | ||
| 1658 | unsigned long dirty:1; /* RO */ | ||
| 1659 | unsigned long larger:1; /* RO */ | ||
| 1660 | unsigned long aa_ext:1; /* RO */ | ||
| 1661 | unsigned long undef_46_54:9; /* Undefined */ | ||
| 1662 | unsigned long way_ecc:9; /* RO */ | ||
| 1663 | } s3; | ||
| 715 | }; | 1664 | }; |
| 716 | 1665 | ||
| 717 | /* ========================================================================= */ | 1666 | /* ========================================================================= */ |
| @@ -719,9 +1668,11 @@ union uvh_gr0_tlb_mmr_read_data_hi_u { | |||
| 719 | /* ========================================================================= */ | 1668 | /* ========================================================================= */ |
| 720 | #define UV1H_GR0_TLB_MMR_READ_DATA_LO 0x4010a8UL | 1669 | #define UV1H_GR0_TLB_MMR_READ_DATA_LO 0x4010a8UL |
| 721 | #define UV2H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL | 1670 | #define UV2H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL |
| 722 | #define UVH_GR0_TLB_MMR_READ_DATA_LO (is_uv1_hub() ? \ | 1671 | #define UV3H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL |
| 723 | UV1H_GR0_TLB_MMR_READ_DATA_LO : \ | 1672 | #define UVH_GR0_TLB_MMR_READ_DATA_LO \ |
| 724 | UV2H_GR0_TLB_MMR_READ_DATA_LO) | 1673 | (is_uv1_hub() ? UV1H_GR0_TLB_MMR_READ_DATA_LO : \ |
| 1674 | (is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_LO : \ | ||
| 1675 | UV3H_GR0_TLB_MMR_READ_DATA_LO)) | ||
| 725 | 1676 | ||
| 726 | #define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 | 1677 | #define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 |
| 727 | #define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 | 1678 | #define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 |
| @@ -730,6 +1681,34 @@ union uvh_gr0_tlb_mmr_read_data_hi_u { | |||
| 730 | #define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL | 1681 | #define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL |
| 731 | #define UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL | 1682 | #define UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL |
| 732 | 1683 | ||
| 1684 | #define UV1H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 | ||
| 1685 | #define UV1H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 | ||
| 1686 | #define UV1H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 | ||
| 1687 | #define UV1H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL | ||
| 1688 | #define UV1H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL | ||
| 1689 | #define UV1H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL | ||
| 1690 | |||
| 1691 | #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 | ||
| 1692 | #define UVXH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 | ||
| 1693 | #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 | ||
| 1694 | #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL | ||
| 1695 | #define UVXH_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL | ||
| 1696 | #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL | ||
| 1697 | |||
| 1698 | #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 | ||
| 1699 | #define UV2H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 | ||
| 1700 | #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 | ||
| 1701 | #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL | ||
| 1702 | #define UV2H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL | ||
| 1703 | #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL | ||
| 1704 | |||
| 1705 | #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 | ||
| 1706 | #define UV3H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 | ||
| 1707 | #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 | ||
| 1708 | #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL | ||
| 1709 | #define UV3H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL | ||
| 1710 | #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL | ||
| 1711 | |||
| 733 | union uvh_gr0_tlb_mmr_read_data_lo_u { | 1712 | union uvh_gr0_tlb_mmr_read_data_lo_u { |
| 734 | unsigned long v; | 1713 | unsigned long v; |
| 735 | struct uvh_gr0_tlb_mmr_read_data_lo_s { | 1714 | struct uvh_gr0_tlb_mmr_read_data_lo_s { |
| @@ -737,12 +1716,35 @@ union uvh_gr0_tlb_mmr_read_data_lo_u { | |||
| 737 | unsigned long asid:24; /* RO */ | 1716 | unsigned long asid:24; /* RO */ |
| 738 | unsigned long valid:1; /* RO */ | 1717 | unsigned long valid:1; /* RO */ |
| 739 | } s; | 1718 | } s; |
| 1719 | struct uv1h_gr0_tlb_mmr_read_data_lo_s { | ||
| 1720 | unsigned long vpn:39; /* RO */ | ||
| 1721 | unsigned long asid:24; /* RO */ | ||
| 1722 | unsigned long valid:1; /* RO */ | ||
| 1723 | } s1; | ||
| 1724 | struct uvxh_gr0_tlb_mmr_read_data_lo_s { | ||
| 1725 | unsigned long vpn:39; /* RO */ | ||
| 1726 | unsigned long asid:24; /* RO */ | ||
| 1727 | unsigned long valid:1; /* RO */ | ||
| 1728 | } sx; | ||
| 1729 | struct uv2h_gr0_tlb_mmr_read_data_lo_s { | ||
| 1730 | unsigned long vpn:39; /* RO */ | ||
| 1731 | unsigned long asid:24; /* RO */ | ||
| 1732 | unsigned long valid:1; /* RO */ | ||
| 1733 | } s2; | ||
| 1734 | struct uv3h_gr0_tlb_mmr_read_data_lo_s { | ||
| 1735 | unsigned long vpn:39; /* RO */ | ||
| 1736 | unsigned long asid:24; /* RO */ | ||
| 1737 | unsigned long valid:1; /* RO */ | ||
| 1738 | } s3; | ||
| 740 | }; | 1739 | }; |
| 741 | 1740 | ||
| 742 | /* ========================================================================= */ | 1741 | /* ========================================================================= */ |
| 743 | /* UVH_GR1_TLB_INT0_CONFIG */ | 1742 | /* UVH_GR1_TLB_INT0_CONFIG */ |
| 744 | /* ========================================================================= */ | 1743 | /* ========================================================================= */ |
| 745 | #define UVH_GR1_TLB_INT0_CONFIG 0x61f00UL | 1744 | #define UVH_GR1_TLB_INT0_CONFIG 0x61f00UL |
| 1745 | #define UV1H_GR1_TLB_INT0_CONFIG 0x61f00UL | ||
| 1746 | #define UV2H_GR1_TLB_INT0_CONFIG 0x61f00UL | ||
| 1747 | #define UV3H_GR1_TLB_INT0_CONFIG 0x61f00UL | ||
| 746 | 1748 | ||
| 747 | #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0 | 1749 | #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0 |
| 748 | #define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT 8 | 1750 | #define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT 8 |
| @@ -761,6 +1763,74 @@ union uvh_gr0_tlb_mmr_read_data_lo_u { | |||
| 761 | #define UVH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL | 1763 | #define UVH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL |
| 762 | #define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | 1764 | #define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL |
| 763 | 1765 | ||
| 1766 | #define UV1H_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0 | ||
| 1767 | #define UV1H_GR1_TLB_INT0_CONFIG_DM_SHFT 8 | ||
| 1768 | #define UV1H_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT 11 | ||
| 1769 | #define UV1H_GR1_TLB_INT0_CONFIG_STATUS_SHFT 12 | ||
| 1770 | #define UV1H_GR1_TLB_INT0_CONFIG_P_SHFT 13 | ||
| 1771 | #define UV1H_GR1_TLB_INT0_CONFIG_T_SHFT 15 | ||
| 1772 | #define UV1H_GR1_TLB_INT0_CONFIG_M_SHFT 16 | ||
| 1773 | #define UV1H_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT 32 | ||
| 1774 | #define UV1H_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL | ||
| 1775 | #define UV1H_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL | ||
| 1776 | #define UV1H_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL | ||
| 1777 | #define UV1H_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL | ||
| 1778 | #define UV1H_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL | ||
| 1779 | #define UV1H_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL | ||
| 1780 | #define UV1H_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL | ||
| 1781 | #define UV1H_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | ||
| 1782 | |||
| 1783 | #define UVXH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0 | ||
| 1784 | #define UVXH_GR1_TLB_INT0_CONFIG_DM_SHFT 8 | ||
| 1785 | #define UVXH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT 11 | ||
| 1786 | #define UVXH_GR1_TLB_INT0_CONFIG_STATUS_SHFT 12 | ||
| 1787 | #define UVXH_GR1_TLB_INT0_CONFIG_P_SHFT 13 | ||
| 1788 | #define UVXH_GR1_TLB_INT0_CONFIG_T_SHFT 15 | ||
| 1789 | #define UVXH_GR1_TLB_INT0_CONFIG_M_SHFT 16 | ||
| 1790 | #define UVXH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT 32 | ||
| 1791 | #define UVXH_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL | ||
| 1792 | #define UVXH_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL | ||
| 1793 | #define UVXH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL | ||
| 1794 | #define UVXH_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL | ||
| 1795 | #define UVXH_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL | ||
| 1796 | #define UVXH_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL | ||
| 1797 | #define UVXH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL | ||
| 1798 | #define UVXH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | ||
| 1799 | |||
| 1800 | #define UV2H_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0 | ||
| 1801 | #define UV2H_GR1_TLB_INT0_CONFIG_DM_SHFT 8 | ||
| 1802 | #define UV2H_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT 11 | ||
| 1803 | #define UV2H_GR1_TLB_INT0_CONFIG_STATUS_SHFT 12 | ||
| 1804 | #define UV2H_GR1_TLB_INT0_CONFIG_P_SHFT 13 | ||
| 1805 | #define UV2H_GR1_TLB_INT0_CONFIG_T_SHFT 15 | ||
| 1806 | #define UV2H_GR1_TLB_INT0_CONFIG_M_SHFT 16 | ||
| 1807 | #define UV2H_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT 32 | ||
| 1808 | #define UV2H_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL | ||
| 1809 | #define UV2H_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL | ||
| 1810 | #define UV2H_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL | ||
| 1811 | #define UV2H_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL | ||
| 1812 | #define UV2H_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL | ||
| 1813 | #define UV2H_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL | ||
| 1814 | #define UV2H_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL | ||
| 1815 | #define UV2H_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | ||
| 1816 | |||
| 1817 | #define UV3H_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0 | ||
| 1818 | #define UV3H_GR1_TLB_INT0_CONFIG_DM_SHFT 8 | ||
| 1819 | #define UV3H_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT 11 | ||
| 1820 | #define UV3H_GR1_TLB_INT0_CONFIG_STATUS_SHFT 12 | ||
| 1821 | #define UV3H_GR1_TLB_INT0_CONFIG_P_SHFT 13 | ||
| 1822 | #define UV3H_GR1_TLB_INT0_CONFIG_T_SHFT 15 | ||
| 1823 | #define UV3H_GR1_TLB_INT0_CONFIG_M_SHFT 16 | ||
| 1824 | #define UV3H_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT 32 | ||
| 1825 | #define UV3H_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL | ||
| 1826 | #define UV3H_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL | ||
| 1827 | #define UV3H_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL | ||
| 1828 | #define UV3H_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL | ||
| 1829 | #define UV3H_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL | ||
| 1830 | #define UV3H_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL | ||
| 1831 | #define UV3H_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL | ||
| 1832 | #define UV3H_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | ||
| 1833 | |||
| 764 | union uvh_gr1_tlb_int0_config_u { | 1834 | union uvh_gr1_tlb_int0_config_u { |
| 765 | unsigned long v; | 1835 | unsigned long v; |
| 766 | struct uvh_gr1_tlb_int0_config_s { | 1836 | struct uvh_gr1_tlb_int0_config_s { |
| @@ -775,12 +1845,63 @@ union uvh_gr1_tlb_int0_config_u { | |||
| 775 | unsigned long rsvd_17_31:15; | 1845 | unsigned long rsvd_17_31:15; |
| 776 | unsigned long apic_id:32; /* RW */ | 1846 | unsigned long apic_id:32; /* RW */ |
| 777 | } s; | 1847 | } s; |
| 1848 | struct uv1h_gr1_tlb_int0_config_s { | ||
| 1849 | unsigned long vector_:8; /* RW */ | ||
| 1850 | unsigned long dm:3; /* RW */ | ||
| 1851 | unsigned long destmode:1; /* RW */ | ||
| 1852 | unsigned long status:1; /* RO */ | ||
| 1853 | unsigned long p:1; /* RO */ | ||
| 1854 | unsigned long rsvd_14:1; | ||
| 1855 | unsigned long t:1; /* RO */ | ||
| 1856 | unsigned long m:1; /* RW */ | ||
| 1857 | unsigned long rsvd_17_31:15; | ||
| 1858 | unsigned long apic_id:32; /* RW */ | ||
| 1859 | } s1; | ||
| 1860 | struct uvxh_gr1_tlb_int0_config_s { | ||
| 1861 | unsigned long vector_:8; /* RW */ | ||
| 1862 | unsigned long dm:3; /* RW */ | ||
| 1863 | unsigned long destmode:1; /* RW */ | ||
| 1864 | unsigned long status:1; /* RO */ | ||
| 1865 | unsigned long p:1; /* RO */ | ||
| 1866 | unsigned long rsvd_14:1; | ||
| 1867 | unsigned long t:1; /* RO */ | ||
| 1868 | unsigned long m:1; /* RW */ | ||
| 1869 | unsigned long rsvd_17_31:15; | ||
| 1870 | unsigned long apic_id:32; /* RW */ | ||
| 1871 | } sx; | ||
| 1872 | struct uv2h_gr1_tlb_int0_config_s { | ||
| 1873 | unsigned long vector_:8; /* RW */ | ||
| 1874 | unsigned long dm:3; /* RW */ | ||
| 1875 | unsigned long destmode:1; /* RW */ | ||
| 1876 | unsigned long status:1; /* RO */ | ||
| 1877 | unsigned long p:1; /* RO */ | ||
| 1878 | unsigned long rsvd_14:1; | ||
| 1879 | unsigned long t:1; /* RO */ | ||
| 1880 | unsigned long m:1; /* RW */ | ||
| 1881 | unsigned long rsvd_17_31:15; | ||
| 1882 | unsigned long apic_id:32; /* RW */ | ||
| 1883 | } s2; | ||
| 1884 | struct uv3h_gr1_tlb_int0_config_s { | ||
| 1885 | unsigned long vector_:8; /* RW */ | ||
| 1886 | unsigned long dm:3; /* RW */ | ||
| 1887 | unsigned long destmode:1; /* RW */ | ||
| 1888 | unsigned long status:1; /* RO */ | ||
| 1889 | unsigned long p:1; /* RO */ | ||
| 1890 | unsigned long rsvd_14:1; | ||
| 1891 | unsigned long t:1; /* RO */ | ||
| 1892 | unsigned long m:1; /* RW */ | ||
| 1893 | unsigned long rsvd_17_31:15; | ||
| 1894 | unsigned long apic_id:32; /* RW */ | ||
| 1895 | } s3; | ||
| 778 | }; | 1896 | }; |
| 779 | 1897 | ||
| 780 | /* ========================================================================= */ | 1898 | /* ========================================================================= */ |
| 781 | /* UVH_GR1_TLB_INT1_CONFIG */ | 1899 | /* UVH_GR1_TLB_INT1_CONFIG */ |
| 782 | /* ========================================================================= */ | 1900 | /* ========================================================================= */ |
| 783 | #define UVH_GR1_TLB_INT1_CONFIG 0x61f40UL | 1901 | #define UVH_GR1_TLB_INT1_CONFIG 0x61f40UL |
| 1902 | #define UV1H_GR1_TLB_INT1_CONFIG 0x61f40UL | ||
| 1903 | #define UV2H_GR1_TLB_INT1_CONFIG 0x61f40UL | ||
| 1904 | #define UV3H_GR1_TLB_INT1_CONFIG 0x61f40UL | ||
| 784 | 1905 | ||
| 785 | #define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0 | 1906 | #define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0 |
| 786 | #define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT 8 | 1907 | #define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT 8 |
| @@ -799,6 +1920,74 @@ union uvh_gr1_tlb_int0_config_u { | |||
| 799 | #define UVH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL | 1920 | #define UVH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL |
| 800 | #define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | 1921 | #define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL |
| 801 | 1922 | ||
| 1923 | #define UV1H_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0 | ||
| 1924 | #define UV1H_GR1_TLB_INT1_CONFIG_DM_SHFT 8 | ||
| 1925 | #define UV1H_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT 11 | ||
| 1926 | #define UV1H_GR1_TLB_INT1_CONFIG_STATUS_SHFT 12 | ||
| 1927 | #define UV1H_GR1_TLB_INT1_CONFIG_P_SHFT 13 | ||
| 1928 | #define UV1H_GR1_TLB_INT1_CONFIG_T_SHFT 15 | ||
| 1929 | #define UV1H_GR1_TLB_INT1_CONFIG_M_SHFT 16 | ||
| 1930 | #define UV1H_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT 32 | ||
| 1931 | #define UV1H_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL | ||
| 1932 | #define UV1H_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL | ||
| 1933 | #define UV1H_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL | ||
| 1934 | #define UV1H_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL | ||
| 1935 | #define UV1H_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL | ||
| 1936 | #define UV1H_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL | ||
| 1937 | #define UV1H_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL | ||
| 1938 | #define UV1H_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | ||
| 1939 | |||
| 1940 | #define UVXH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0 | ||
| 1941 | #define UVXH_GR1_TLB_INT1_CONFIG_DM_SHFT 8 | ||
| 1942 | #define UVXH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT 11 | ||
| 1943 | #define UVXH_GR1_TLB_INT1_CONFIG_STATUS_SHFT 12 | ||
| 1944 | #define UVXH_GR1_TLB_INT1_CONFIG_P_SHFT 13 | ||
| 1945 | #define UVXH_GR1_TLB_INT1_CONFIG_T_SHFT 15 | ||
| 1946 | #define UVXH_GR1_TLB_INT1_CONFIG_M_SHFT 16 | ||
| 1947 | #define UVXH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT 32 | ||
| 1948 | #define UVXH_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL | ||
| 1949 | #define UVXH_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL | ||
| 1950 | #define UVXH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL | ||
| 1951 | #define UVXH_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL | ||
| 1952 | #define UVXH_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL | ||
| 1953 | #define UVXH_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL | ||
| 1954 | #define UVXH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL | ||
| 1955 | #define UVXH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | ||
| 1956 | |||
| 1957 | #define UV2H_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0 | ||
| 1958 | #define UV2H_GR1_TLB_INT1_CONFIG_DM_SHFT 8 | ||
| 1959 | #define UV2H_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT 11 | ||
| 1960 | #define UV2H_GR1_TLB_INT1_CONFIG_STATUS_SHFT 12 | ||
| 1961 | #define UV2H_GR1_TLB_INT1_CONFIG_P_SHFT 13 | ||
| 1962 | #define UV2H_GR1_TLB_INT1_CONFIG_T_SHFT 15 | ||
| 1963 | #define UV2H_GR1_TLB_INT1_CONFIG_M_SHFT 16 | ||
| 1964 | #define UV2H_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT 32 | ||
| 1965 | #define UV2H_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL | ||
| 1966 | #define UV2H_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL | ||
| 1967 | #define UV2H_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL | ||
| 1968 | #define UV2H_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL | ||
| 1969 | #define UV2H_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL | ||
| 1970 | #define UV2H_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL | ||
| 1971 | #define UV2H_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL | ||
| 1972 | #define UV2H_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | ||
| 1973 | |||
| 1974 | #define UV3H_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0 | ||
| 1975 | #define UV3H_GR1_TLB_INT1_CONFIG_DM_SHFT 8 | ||
| 1976 | #define UV3H_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT 11 | ||
| 1977 | #define UV3H_GR1_TLB_INT1_CONFIG_STATUS_SHFT 12 | ||
| 1978 | #define UV3H_GR1_TLB_INT1_CONFIG_P_SHFT 13 | ||
| 1979 | #define UV3H_GR1_TLB_INT1_CONFIG_T_SHFT 15 | ||
| 1980 | #define UV3H_GR1_TLB_INT1_CONFIG_M_SHFT 16 | ||
| 1981 | #define UV3H_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT 32 | ||
| 1982 | #define UV3H_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL | ||
| 1983 | #define UV3H_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL | ||
| 1984 | #define UV3H_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL | ||
| 1985 | #define UV3H_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL | ||
| 1986 | #define UV3H_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL | ||
| 1987 | #define UV3H_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL | ||
| 1988 | #define UV3H_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL | ||
| 1989 | #define UV3H_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | ||
| 1990 | |||
| 802 | union uvh_gr1_tlb_int1_config_u { | 1991 | union uvh_gr1_tlb_int1_config_u { |
| 803 | unsigned long v; | 1992 | unsigned long v; |
| 804 | struct uvh_gr1_tlb_int1_config_s { | 1993 | struct uvh_gr1_tlb_int1_config_s { |
| @@ -813,6 +2002,54 @@ union uvh_gr1_tlb_int1_config_u { | |||
| 813 | unsigned long rsvd_17_31:15; | 2002 | unsigned long rsvd_17_31:15; |
| 814 | unsigned long apic_id:32; /* RW */ | 2003 | unsigned long apic_id:32; /* RW */ |
| 815 | } s; | 2004 | } s; |
| 2005 | struct uv1h_gr1_tlb_int1_config_s { | ||
| 2006 | unsigned long vector_:8; /* RW */ | ||
| 2007 | unsigned long dm:3; /* RW */ | ||
| 2008 | unsigned long destmode:1; /* RW */ | ||
| 2009 | unsigned long status:1; /* RO */ | ||
| 2010 | unsigned long p:1; /* RO */ | ||
| 2011 | unsigned long rsvd_14:1; | ||
| 2012 | unsigned long t:1; /* RO */ | ||
| 2013 | unsigned long m:1; /* RW */ | ||
| 2014 | unsigned long rsvd_17_31:15; | ||
| 2015 | unsigned long apic_id:32; /* RW */ | ||
| 2016 | } s1; | ||
| 2017 | struct uvxh_gr1_tlb_int1_config_s { | ||
| 2018 | unsigned long vector_:8; /* RW */ | ||
| 2019 | unsigned long dm:3; /* RW */ | ||
| 2020 | unsigned long destmode:1; /* RW */ | ||
| 2021 | unsigned long status:1; /* RO */ | ||
| 2022 | unsigned long p:1; /* RO */ | ||
| 2023 | unsigned long rsvd_14:1; | ||
| 2024 | unsigned long t:1; /* RO */ | ||
| 2025 | unsigned long m:1; /* RW */ | ||
| 2026 | unsigned long rsvd_17_31:15; | ||
| 2027 | unsigned long apic_id:32; /* RW */ | ||
| 2028 | } sx; | ||
| 2029 | struct uv2h_gr1_tlb_int1_config_s { | ||
| 2030 | unsigned long vector_:8; /* RW */ | ||
| 2031 | unsigned long dm:3; /* RW */ | ||
| 2032 | unsigned long destmode:1; /* RW */ | ||
| 2033 | unsigned long status:1; /* RO */ | ||
| 2034 | unsigned long p:1; /* RO */ | ||
| 2035 | unsigned long rsvd_14:1; | ||
| 2036 | unsigned long t:1; /* RO */ | ||
| 2037 | unsigned long m:1; /* RW */ | ||
| 2038 | unsigned long rsvd_17_31:15; | ||
| 2039 | unsigned long apic_id:32; /* RW */ | ||
| 2040 | } s2; | ||
| 2041 | struct uv3h_gr1_tlb_int1_config_s { | ||
| 2042 | unsigned long vector_:8; /* RW */ | ||
| 2043 | unsigned long dm:3; /* RW */ | ||
| 2044 | unsigned long destmode:1; /* RW */ | ||
| 2045 | unsigned long status:1; /* RO */ | ||
| 2046 | unsigned long p:1; /* RO */ | ||
| 2047 | unsigned long rsvd_14:1; | ||
| 2048 | unsigned long t:1; /* RO */ | ||
| 2049 | unsigned long m:1; /* RW */ | ||
| 2050 | unsigned long rsvd_17_31:15; | ||
| 2051 | unsigned long apic_id:32; /* RW */ | ||
| 2052 | } s3; | ||
| 816 | }; | 2053 | }; |
| 817 | 2054 | ||
| 818 | /* ========================================================================= */ | 2055 | /* ========================================================================= */ |
| @@ -820,9 +2057,11 @@ union uvh_gr1_tlb_int1_config_u { | |||
| 820 | /* ========================================================================= */ | 2057 | /* ========================================================================= */ |
| 821 | #define UV1H_GR1_TLB_MMR_CONTROL 0x801080UL | 2058 | #define UV1H_GR1_TLB_MMR_CONTROL 0x801080UL |
| 822 | #define UV2H_GR1_TLB_MMR_CONTROL 0x1001080UL | 2059 | #define UV2H_GR1_TLB_MMR_CONTROL 0x1001080UL |
| 823 | #define UVH_GR1_TLB_MMR_CONTROL (is_uv1_hub() ? \ | 2060 | #define UV3H_GR1_TLB_MMR_CONTROL 0x1001080UL |
| 824 | UV1H_GR1_TLB_MMR_CONTROL : \ | 2061 | #define UVH_GR1_TLB_MMR_CONTROL \ |
| 825 | UV2H_GR1_TLB_MMR_CONTROL) | 2062 | (is_uv1_hub() ? UV1H_GR1_TLB_MMR_CONTROL : \ |
| 2063 | (is_uv2_hub() ? UV2H_GR1_TLB_MMR_CONTROL : \ | ||
| 2064 | UV3H_GR1_TLB_MMR_CONTROL)) | ||
| 826 | 2065 | ||
| 827 | #define UVH_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 | 2066 | #define UVH_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 |
| 828 | #define UVH_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 | 2067 | #define UVH_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 |
| @@ -860,6 +2099,21 @@ union uvh_gr1_tlb_int1_config_u { | |||
| 860 | #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK 0x0100000000000000UL | 2099 | #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK 0x0100000000000000UL |
| 861 | #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK 0x1000000000000000UL | 2100 | #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK 0x1000000000000000UL |
| 862 | 2101 | ||
| 2102 | #define UVXH_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 | ||
| 2103 | #define UVXH_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 | ||
| 2104 | #define UVXH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 | ||
| 2105 | #define UVXH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 | ||
| 2106 | #define UVXH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 | ||
| 2107 | #define UVXH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31 | ||
| 2108 | #define UVXH_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 | ||
| 2109 | #define UVXH_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL | ||
| 2110 | #define UVXH_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL | ||
| 2111 | #define UVXH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL | ||
| 2112 | #define UVXH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL | ||
| 2113 | #define UVXH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL | ||
| 2114 | #define UVXH_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL | ||
| 2115 | #define UVXH_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL | ||
| 2116 | |||
| 863 | #define UV2H_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 | 2117 | #define UV2H_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 |
| 864 | #define UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 | 2118 | #define UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 |
| 865 | #define UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 | 2119 | #define UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 |
| @@ -879,6 +2133,23 @@ union uvh_gr1_tlb_int1_config_u { | |||
| 879 | #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL | 2133 | #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL |
| 880 | #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL | 2134 | #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL |
| 881 | 2135 | ||
| 2136 | #define UV3H_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 | ||
| 2137 | #define UV3H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 | ||
| 2138 | #define UV3H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 | ||
| 2139 | #define UV3H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 | ||
| 2140 | #define UV3H_GR1_TLB_MMR_CONTROL_ECC_SEL_SHFT 21 | ||
| 2141 | #define UV3H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 | ||
| 2142 | #define UV3H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31 | ||
| 2143 | #define UV3H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 | ||
| 2144 | #define UV3H_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL | ||
| 2145 | #define UV3H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL | ||
| 2146 | #define UV3H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL | ||
| 2147 | #define UV3H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL | ||
| 2148 | #define UV3H_GR1_TLB_MMR_CONTROL_ECC_SEL_MASK 0x0000000000200000UL | ||
| 2149 | #define UV3H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL | ||
| 2150 | #define UV3H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL | ||
| 2151 | #define UV3H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL | ||
| 2152 | |||
| 882 | union uvh_gr1_tlb_mmr_control_u { | 2153 | union uvh_gr1_tlb_mmr_control_u { |
| 883 | unsigned long v; | 2154 | unsigned long v; |
| 884 | struct uvh_gr1_tlb_mmr_control_s { | 2155 | struct uvh_gr1_tlb_mmr_control_s { |
| @@ -891,7 +2162,9 @@ union uvh_gr1_tlb_mmr_control_u { | |||
| 891 | unsigned long rsvd_21_29:9; | 2162 | unsigned long rsvd_21_29:9; |
| 892 | unsigned long mmr_write:1; /* WP */ | 2163 | unsigned long mmr_write:1; /* WP */ |
| 893 | unsigned long mmr_read:1; /* WP */ | 2164 | unsigned long mmr_read:1; /* WP */ |
| 894 | unsigned long rsvd_32_63:32; | 2165 | unsigned long rsvd_32_48:17; |
| 2166 | unsigned long rsvd_49_51:3; | ||
| 2167 | unsigned long rsvd_52_63:12; | ||
| 895 | } s; | 2168 | } s; |
| 896 | struct uv1h_gr1_tlb_mmr_control_s { | 2169 | struct uv1h_gr1_tlb_mmr_control_s { |
| 897 | unsigned long index:12; /* RW */ | 2170 | unsigned long index:12; /* RW */ |
| @@ -915,6 +2188,23 @@ union uvh_gr1_tlb_mmr_control_u { | |||
| 915 | unsigned long mmr_inj_tlblruv:1; /* RW */ | 2188 | unsigned long mmr_inj_tlblruv:1; /* RW */ |
| 916 | unsigned long rsvd_61_63:3; | 2189 | unsigned long rsvd_61_63:3; |
| 917 | } s1; | 2190 | } s1; |
| 2191 | struct uvxh_gr1_tlb_mmr_control_s { | ||
| 2192 | unsigned long index:12; /* RW */ | ||
| 2193 | unsigned long mem_sel:2; /* RW */ | ||
| 2194 | unsigned long rsvd_14_15:2; | ||
| 2195 | unsigned long auto_valid_en:1; /* RW */ | ||
| 2196 | unsigned long rsvd_17_19:3; | ||
| 2197 | unsigned long mmr_hash_index_en:1; /* RW */ | ||
| 2198 | unsigned long rsvd_21_29:9; | ||
| 2199 | unsigned long mmr_write:1; /* WP */ | ||
| 2200 | unsigned long mmr_read:1; /* WP */ | ||
| 2201 | unsigned long mmr_op_done:1; /* RW */ | ||
| 2202 | unsigned long rsvd_33_47:15; | ||
| 2203 | unsigned long rsvd_48:1; | ||
| 2204 | unsigned long rsvd_49_51:3; | ||
| 2205 | unsigned long rsvd_52:1; | ||
| 2206 | unsigned long rsvd_53_63:11; | ||
| 2207 | } sx; | ||
| 918 | struct uv2h_gr1_tlb_mmr_control_s { | 2208 | struct uv2h_gr1_tlb_mmr_control_s { |
| 919 | unsigned long index:12; /* RW */ | 2209 | unsigned long index:12; /* RW */ |
| 920 | unsigned long mem_sel:2; /* RW */ | 2210 | unsigned long mem_sel:2; /* RW */ |
| @@ -932,6 +2222,24 @@ union uvh_gr1_tlb_mmr_control_u { | |||
| 932 | unsigned long mmr_inj_tlbram:1; /* RW */ | 2222 | unsigned long mmr_inj_tlbram:1; /* RW */ |
| 933 | unsigned long rsvd_53_63:11; | 2223 | unsigned long rsvd_53_63:11; |
| 934 | } s2; | 2224 | } s2; |
| 2225 | struct uv3h_gr1_tlb_mmr_control_s { | ||
| 2226 | unsigned long index:12; /* RW */ | ||
| 2227 | unsigned long mem_sel:2; /* RW */ | ||
| 2228 | unsigned long rsvd_14_15:2; | ||
| 2229 | unsigned long auto_valid_en:1; /* RW */ | ||
| 2230 | unsigned long rsvd_17_19:3; | ||
| 2231 | unsigned long mmr_hash_index_en:1; /* RW */ | ||
| 2232 | unsigned long ecc_sel:1; /* RW */ | ||
| 2233 | unsigned long rsvd_22_29:8; | ||
| 2234 | unsigned long mmr_write:1; /* WP */ | ||
| 2235 | unsigned long mmr_read:1; /* WP */ | ||
| 2236 | unsigned long mmr_op_done:1; /* RW */ | ||
| 2237 | unsigned long rsvd_33_47:15; | ||
| 2238 | unsigned long undef_48:1; /* Undefined */ | ||
| 2239 | unsigned long rsvd_49_51:3; | ||
| 2240 | unsigned long undef_52:1; /* Undefined */ | ||
| 2241 | unsigned long rsvd_53_63:11; | ||
| 2242 | } s3; | ||
| 935 | }; | 2243 | }; |
| 936 | 2244 | ||
| 937 | /* ========================================================================= */ | 2245 | /* ========================================================================= */ |
| @@ -939,9 +2247,11 @@ union uvh_gr1_tlb_mmr_control_u { | |||
| 939 | /* ========================================================================= */ | 2247 | /* ========================================================================= */ |
| 940 | #define UV1H_GR1_TLB_MMR_READ_DATA_HI 0x8010a0UL | 2248 | #define UV1H_GR1_TLB_MMR_READ_DATA_HI 0x8010a0UL |
| 941 | #define UV2H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL | 2249 | #define UV2H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL |
| 942 | #define UVH_GR1_TLB_MMR_READ_DATA_HI (is_uv1_hub() ? \ | 2250 | #define UV3H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL |
| 943 | UV1H_GR1_TLB_MMR_READ_DATA_HI : \ | 2251 | #define UVH_GR1_TLB_MMR_READ_DATA_HI \ |
| 944 | UV2H_GR1_TLB_MMR_READ_DATA_HI) | 2252 | (is_uv1_hub() ? UV1H_GR1_TLB_MMR_READ_DATA_HI : \ |
| 2253 | (is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_HI : \ | ||
| 2254 | UV3H_GR1_TLB_MMR_READ_DATA_HI)) | ||
| 945 | 2255 | ||
| 946 | #define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 | 2256 | #define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 |
| 947 | #define UVH_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 | 2257 | #define UVH_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 |
| @@ -952,6 +2262,46 @@ union uvh_gr1_tlb_mmr_control_u { | |||
| 952 | #define UVH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL | 2262 | #define UVH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL |
| 953 | #define UVH_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL | 2263 | #define UVH_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL |
| 954 | 2264 | ||
| 2265 | #define UV1H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 | ||
| 2266 | #define UV1H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 | ||
| 2267 | #define UV1H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 | ||
| 2268 | #define UV1H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 | ||
| 2269 | #define UV1H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL | ||
| 2270 | #define UV1H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL | ||
| 2271 | #define UV1H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL | ||
| 2272 | #define UV1H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL | ||
| 2273 | |||
| 2274 | #define UVXH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 | ||
| 2275 | #define UVXH_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 | ||
| 2276 | #define UVXH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 | ||
| 2277 | #define UVXH_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 | ||
| 2278 | #define UVXH_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL | ||
| 2279 | #define UVXH_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL | ||
| 2280 | #define UVXH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL | ||
| 2281 | #define UVXH_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL | ||
| 2282 | |||
| 2283 | #define UV2H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 | ||
| 2284 | #define UV2H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 | ||
| 2285 | #define UV2H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 | ||
| 2286 | #define UV2H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 | ||
| 2287 | #define UV2H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL | ||
| 2288 | #define UV2H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL | ||
| 2289 | #define UV2H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL | ||
| 2290 | #define UV2H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL | ||
| 2291 | |||
| 2292 | #define UV3H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 | ||
| 2293 | #define UV3H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 | ||
| 2294 | #define UV3H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 | ||
| 2295 | #define UV3H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 | ||
| 2296 | #define UV3H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT 45 | ||
| 2297 | #define UV3H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT 55 | ||
| 2298 | #define UV3H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL | ||
| 2299 | #define UV3H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL | ||
| 2300 | #define UV3H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL | ||
| 2301 | #define UV3H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL | ||
| 2302 | #define UV3H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_MASK 0x0000200000000000UL | ||
| 2303 | #define UV3H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK 0xff80000000000000UL | ||
| 2304 | |||
| 955 | union uvh_gr1_tlb_mmr_read_data_hi_u { | 2305 | union uvh_gr1_tlb_mmr_read_data_hi_u { |
| 956 | unsigned long v; | 2306 | unsigned long v; |
| 957 | struct uvh_gr1_tlb_mmr_read_data_hi_s { | 2307 | struct uvh_gr1_tlb_mmr_read_data_hi_s { |
| @@ -961,6 +2311,36 @@ union uvh_gr1_tlb_mmr_read_data_hi_u { | |||
| 961 | unsigned long larger:1; /* RO */ | 2311 | unsigned long larger:1; /* RO */ |
| 962 | unsigned long rsvd_45_63:19; | 2312 | unsigned long rsvd_45_63:19; |
| 963 | } s; | 2313 | } s; |
| 2314 | struct uv1h_gr1_tlb_mmr_read_data_hi_s { | ||
| 2315 | unsigned long pfn:41; /* RO */ | ||
| 2316 | unsigned long gaa:2; /* RO */ | ||
| 2317 | unsigned long dirty:1; /* RO */ | ||
| 2318 | unsigned long larger:1; /* RO */ | ||
| 2319 | unsigned long rsvd_45_63:19; | ||
| 2320 | } s1; | ||
| 2321 | struct uvxh_gr1_tlb_mmr_read_data_hi_s { | ||
| 2322 | unsigned long pfn:41; /* RO */ | ||
| 2323 | unsigned long gaa:2; /* RO */ | ||
| 2324 | unsigned long dirty:1; /* RO */ | ||
| 2325 | unsigned long larger:1; /* RO */ | ||
| 2326 | unsigned long rsvd_45_63:19; | ||
| 2327 | } sx; | ||
| 2328 | struct uv2h_gr1_tlb_mmr_read_data_hi_s { | ||
| 2329 | unsigned long pfn:41; /* RO */ | ||
| 2330 | unsigned long gaa:2; /* RO */ | ||
| 2331 | unsigned long dirty:1; /* RO */ | ||
| 2332 | unsigned long larger:1; /* RO */ | ||
| 2333 | unsigned long rsvd_45_63:19; | ||
| 2334 | } s2; | ||
| 2335 | struct uv3h_gr1_tlb_mmr_read_data_hi_s { | ||
| 2336 | unsigned long pfn:41; /* RO */ | ||
| 2337 | unsigned long gaa:2; /* RO */ | ||
| 2338 | unsigned long dirty:1; /* RO */ | ||
| 2339 | unsigned long larger:1; /* RO */ | ||
| 2340 | unsigned long aa_ext:1; /* RO */ | ||
| 2341 | unsigned long undef_46_54:9; /* Undefined */ | ||
| 2342 | unsigned long way_ecc:9; /* RO */ | ||
| 2343 | } s3; | ||
| 964 | }; | 2344 | }; |
| 965 | 2345 | ||
| 966 | /* ========================================================================= */ | 2346 | /* ========================================================================= */ |
| @@ -968,9 +2348,11 @@ union uvh_gr1_tlb_mmr_read_data_hi_u { | |||
| 968 | /* ========================================================================= */ | 2348 | /* ========================================================================= */ |
| 969 | #define UV1H_GR1_TLB_MMR_READ_DATA_LO 0x8010a8UL | 2349 | #define UV1H_GR1_TLB_MMR_READ_DATA_LO 0x8010a8UL |
| 970 | #define UV2H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL | 2350 | #define UV2H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL |
| 971 | #define UVH_GR1_TLB_MMR_READ_DATA_LO (is_uv1_hub() ? \ | 2351 | #define UV3H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL |
| 972 | UV1H_GR1_TLB_MMR_READ_DATA_LO : \ | 2352 | #define UVH_GR1_TLB_MMR_READ_DATA_LO \ |
| 973 | UV2H_GR1_TLB_MMR_READ_DATA_LO) | 2353 | (is_uv1_hub() ? UV1H_GR1_TLB_MMR_READ_DATA_LO : \ |
| 2354 | (is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_LO : \ | ||
| 2355 | UV3H_GR1_TLB_MMR_READ_DATA_LO)) | ||
| 974 | 2356 | ||
| 975 | #define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 | 2357 | #define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 |
| 976 | #define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 | 2358 | #define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 |
| @@ -979,6 +2361,34 @@ union uvh_gr1_tlb_mmr_read_data_hi_u { | |||
| 979 | #define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL | 2361 | #define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL |
| 980 | #define UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL | 2362 | #define UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL |
| 981 | 2363 | ||
| 2364 | #define UV1H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 | ||
| 2365 | #define UV1H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 | ||
| 2366 | #define UV1H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 | ||
| 2367 | #define UV1H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL | ||
| 2368 | #define UV1H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL | ||
| 2369 | #define UV1H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL | ||
| 2370 | |||
| 2371 | #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 | ||
| 2372 | #define UVXH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 | ||
| 2373 | #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 | ||
| 2374 | #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL | ||
| 2375 | #define UVXH_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL | ||
| 2376 | #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL | ||
| 2377 | |||
| 2378 | #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 | ||
| 2379 | #define UV2H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 | ||
| 2380 | #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 | ||
| 2381 | #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL | ||
| 2382 | #define UV2H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL | ||
| 2383 | #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL | ||
| 2384 | |||
| 2385 | #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 | ||
| 2386 | #define UV3H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 | ||
| 2387 | #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 | ||
| 2388 | #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL | ||
| 2389 | #define UV3H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL | ||
| 2390 | #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL | ||
| 2391 | |||
| 982 | union uvh_gr1_tlb_mmr_read_data_lo_u { | 2392 | union uvh_gr1_tlb_mmr_read_data_lo_u { |
| 983 | unsigned long v; | 2393 | unsigned long v; |
| 984 | struct uvh_gr1_tlb_mmr_read_data_lo_s { | 2394 | struct uvh_gr1_tlb_mmr_read_data_lo_s { |
| @@ -986,31 +2396,94 @@ union uvh_gr1_tlb_mmr_read_data_lo_u { | |||
| 986 | unsigned long asid:24; /* RO */ | 2396 | unsigned long asid:24; /* RO */ |
| 987 | unsigned long valid:1; /* RO */ | 2397 | unsigned long valid:1; /* RO */ |
| 988 | } s; | 2398 | } s; |
| 2399 | struct uv1h_gr1_tlb_mmr_read_data_lo_s { | ||
| 2400 | unsigned long vpn:39; /* RO */ | ||
| 2401 | unsigned long asid:24; /* RO */ | ||
| 2402 | unsigned long valid:1; /* RO */ | ||
| 2403 | } s1; | ||
| 2404 | struct uvxh_gr1_tlb_mmr_read_data_lo_s { | ||
| 2405 | unsigned long vpn:39; /* RO */ | ||
| 2406 | unsigned long asid:24; /* RO */ | ||
| 2407 | unsigned long valid:1; /* RO */ | ||
| 2408 | } sx; | ||
| 2409 | struct uv2h_gr1_tlb_mmr_read_data_lo_s { | ||
| 2410 | unsigned long vpn:39; /* RO */ | ||
| 2411 | unsigned long asid:24; /* RO */ | ||
| 2412 | unsigned long valid:1; /* RO */ | ||
| 2413 | } s2; | ||
| 2414 | struct uv3h_gr1_tlb_mmr_read_data_lo_s { | ||
| 2415 | unsigned long vpn:39; /* RO */ | ||
| 2416 | unsigned long asid:24; /* RO */ | ||
| 2417 | unsigned long valid:1; /* RO */ | ||
| 2418 | } s3; | ||
| 989 | }; | 2419 | }; |
| 990 | 2420 | ||
| 991 | /* ========================================================================= */ | 2421 | /* ========================================================================= */ |
| 992 | /* UVH_INT_CMPB */ | 2422 | /* UVH_INT_CMPB */ |
| 993 | /* ========================================================================= */ | 2423 | /* ========================================================================= */ |
| 994 | #define UVH_INT_CMPB 0x22080UL | 2424 | #define UVH_INT_CMPB 0x22080UL |
| 2425 | #define UV1H_INT_CMPB 0x22080UL | ||
| 2426 | #define UV2H_INT_CMPB 0x22080UL | ||
| 2427 | #define UV3H_INT_CMPB 0x22080UL | ||
| 995 | 2428 | ||
| 996 | #define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0 | 2429 | #define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0 |
| 997 | #define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL | 2430 | #define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL |
| 998 | 2431 | ||
| 2432 | #define UV1H_INT_CMPB_REAL_TIME_CMPB_SHFT 0 | ||
| 2433 | #define UV1H_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL | ||
| 2434 | |||
| 2435 | #define UVXH_INT_CMPB_REAL_TIME_CMPB_SHFT 0 | ||
| 2436 | #define UVXH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL | ||
| 2437 | |||
| 2438 | #define UV2H_INT_CMPB_REAL_TIME_CMPB_SHFT 0 | ||
| 2439 | #define UV2H_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL | ||
| 2440 | |||
| 2441 | #define UV3H_INT_CMPB_REAL_TIME_CMPB_SHFT 0 | ||
| 2442 | #define UV3H_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL | ||
| 2443 | |||
| 999 | union uvh_int_cmpb_u { | 2444 | union uvh_int_cmpb_u { |
| 1000 | unsigned long v; | 2445 | unsigned long v; |
| 1001 | struct uvh_int_cmpb_s { | 2446 | struct uvh_int_cmpb_s { |
| 1002 | unsigned long real_time_cmpb:56; /* RW */ | 2447 | unsigned long real_time_cmpb:56; /* RW */ |
| 1003 | unsigned long rsvd_56_63:8; | 2448 | unsigned long rsvd_56_63:8; |
| 1004 | } s; | 2449 | } s; |
| 2450 | struct uv1h_int_cmpb_s { | ||
| 2451 | unsigned long real_time_cmpb:56; /* RW */ | ||
| 2452 | unsigned long rsvd_56_63:8; | ||
| 2453 | } s1; | ||
| 2454 | struct uvxh_int_cmpb_s { | ||
| 2455 | unsigned long real_time_cmpb:56; /* RW */ | ||
| 2456 | unsigned long rsvd_56_63:8; | ||
| 2457 | } sx; | ||
| 2458 | struct uv2h_int_cmpb_s { | ||
| 2459 | unsigned long real_time_cmpb:56; /* RW */ | ||
| 2460 | unsigned long rsvd_56_63:8; | ||
| 2461 | } s2; | ||
| 2462 | struct uv3h_int_cmpb_s { | ||
| 2463 | unsigned long real_time_cmpb:56; /* RW */ | ||
| 2464 | unsigned long rsvd_56_63:8; | ||
| 2465 | } s3; | ||
| 1005 | }; | 2466 | }; |
| 1006 | 2467 | ||
| 1007 | /* ========================================================================= */ | 2468 | /* ========================================================================= */ |
| 1008 | /* UVH_INT_CMPC */ | 2469 | /* UVH_INT_CMPC */ |
| 1009 | /* ========================================================================= */ | 2470 | /* ========================================================================= */ |
| 1010 | #define UVH_INT_CMPC 0x22100UL | 2471 | #define UVH_INT_CMPC 0x22100UL |
| 2472 | #define UV1H_INT_CMPC 0x22100UL | ||
| 2473 | #define UV2H_INT_CMPC 0x22100UL | ||
| 2474 | #define UV3H_INT_CMPC 0x22100UL | ||
| 1011 | 2475 | ||
| 1012 | #define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT 0 | 2476 | #define UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT 0 |
| 1013 | #define UVH_INT_CMPC_REAL_TIME_CMPC_MASK 0xffffffffffffffUL | 2477 | #define UV1H_INT_CMPC_REAL_TIME_CMPC_MASK 0x00ffffffffffffffUL |
| 2478 | |||
| 2479 | #define UVXH_INT_CMPC_REAL_TIME_CMP_2_SHFT 0 | ||
| 2480 | #define UVXH_INT_CMPC_REAL_TIME_CMP_2_MASK 0x00ffffffffffffffUL | ||
| 2481 | |||
| 2482 | #define UV2H_INT_CMPC_REAL_TIME_CMP_2_SHFT 0 | ||
| 2483 | #define UV2H_INT_CMPC_REAL_TIME_CMP_2_MASK 0x00ffffffffffffffUL | ||
| 2484 | |||
| 2485 | #define UV3H_INT_CMPC_REAL_TIME_CMP_2_SHFT 0 | ||
| 2486 | #define UV3H_INT_CMPC_REAL_TIME_CMP_2_MASK 0x00ffffffffffffffUL | ||
| 1014 | 2487 | ||
| 1015 | union uvh_int_cmpc_u { | 2488 | union uvh_int_cmpc_u { |
| 1016 | unsigned long v; | 2489 | unsigned long v; |
| @@ -1018,15 +2491,43 @@ union uvh_int_cmpc_u { | |||
| 1018 | unsigned long real_time_cmpc:56; /* RW */ | 2491 | unsigned long real_time_cmpc:56; /* RW */ |
| 1019 | unsigned long rsvd_56_63:8; | 2492 | unsigned long rsvd_56_63:8; |
| 1020 | } s; | 2493 | } s; |
| 2494 | struct uv1h_int_cmpc_s { | ||
| 2495 | unsigned long real_time_cmpc:56; /* RW */ | ||
| 2496 | unsigned long rsvd_56_63:8; | ||
| 2497 | } s1; | ||
| 2498 | struct uvxh_int_cmpc_s { | ||
| 2499 | unsigned long real_time_cmpc:56; /* RW */ | ||
| 2500 | unsigned long rsvd_56_63:8; | ||
| 2501 | } sx; | ||
| 2502 | struct uv2h_int_cmpc_s { | ||
| 2503 | unsigned long real_time_cmpc:56; /* RW */ | ||
| 2504 | unsigned long rsvd_56_63:8; | ||
| 2505 | } s2; | ||
| 2506 | struct uv3h_int_cmpc_s { | ||
| 2507 | unsigned long real_time_cmpc:56; /* RW */ | ||
| 2508 | unsigned long rsvd_56_63:8; | ||
| 2509 | } s3; | ||
| 1021 | }; | 2510 | }; |
| 1022 | 2511 | ||
| 1023 | /* ========================================================================= */ | 2512 | /* ========================================================================= */ |
| 1024 | /* UVH_INT_CMPD */ | 2513 | /* UVH_INT_CMPD */ |
| 1025 | /* ========================================================================= */ | 2514 | /* ========================================================================= */ |
| 1026 | #define UVH_INT_CMPD 0x22180UL | 2515 | #define UVH_INT_CMPD 0x22180UL |
| 2516 | #define UV1H_INT_CMPD 0x22180UL | ||
| 2517 | #define UV2H_INT_CMPD 0x22180UL | ||
| 2518 | #define UV3H_INT_CMPD 0x22180UL | ||
| 1027 | 2519 | ||
| 1028 | #define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT 0 | 2520 | #define UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT 0 |
| 1029 | #define UVH_INT_CMPD_REAL_TIME_CMPD_MASK 0xffffffffffffffUL | 2521 | #define UV1H_INT_CMPD_REAL_TIME_CMPD_MASK 0x00ffffffffffffffUL |
| 2522 | |||
| 2523 | #define UVXH_INT_CMPD_REAL_TIME_CMP_3_SHFT 0 | ||
| 2524 | #define UVXH_INT_CMPD_REAL_TIME_CMP_3_MASK 0x00ffffffffffffffUL | ||
| 2525 | |||
| 2526 | #define UV2H_INT_CMPD_REAL_TIME_CMP_3_SHFT 0 | ||
| 2527 | #define UV2H_INT_CMPD_REAL_TIME_CMP_3_MASK 0x00ffffffffffffffUL | ||
| 2528 | |||
| 2529 | #define UV3H_INT_CMPD_REAL_TIME_CMP_3_SHFT 0 | ||
| 2530 | #define UV3H_INT_CMPD_REAL_TIME_CMP_3_MASK 0x00ffffffffffffffUL | ||
| 1030 | 2531 | ||
| 1031 | union uvh_int_cmpd_u { | 2532 | union uvh_int_cmpd_u { |
| 1032 | unsigned long v; | 2533 | unsigned long v; |
| @@ -1034,13 +2535,35 @@ union uvh_int_cmpd_u { | |||
| 1034 | unsigned long real_time_cmpd:56; /* RW */ | 2535 | unsigned long real_time_cmpd:56; /* RW */ |
| 1035 | unsigned long rsvd_56_63:8; | 2536 | unsigned long rsvd_56_63:8; |
| 1036 | } s; | 2537 | } s; |
| 2538 | struct uv1h_int_cmpd_s { | ||
| 2539 | unsigned long real_time_cmpd:56; /* RW */ | ||
| 2540 | unsigned long rsvd_56_63:8; | ||
| 2541 | } s1; | ||
| 2542 | struct uvxh_int_cmpd_s { | ||
| 2543 | unsigned long real_time_cmpd:56; /* RW */ | ||
| 2544 | unsigned long rsvd_56_63:8; | ||
| 2545 | } sx; | ||
| 2546 | struct uv2h_int_cmpd_s { | ||
| 2547 | unsigned long real_time_cmpd:56; /* RW */ | ||
| 2548 | unsigned long rsvd_56_63:8; | ||
| 2549 | } s2; | ||
| 2550 | struct uv3h_int_cmpd_s { | ||
| 2551 | unsigned long real_time_cmpd:56; /* RW */ | ||
| 2552 | unsigned long rsvd_56_63:8; | ||
| 2553 | } s3; | ||
| 1037 | }; | 2554 | }; |
| 1038 | 2555 | ||
| 1039 | /* ========================================================================= */ | 2556 | /* ========================================================================= */ |
| 1040 | /* UVH_IPI_INT */ | 2557 | /* UVH_IPI_INT */ |
| 1041 | /* ========================================================================= */ | 2558 | /* ========================================================================= */ |
| 1042 | #define UVH_IPI_INT 0x60500UL | 2559 | #define UVH_IPI_INT 0x60500UL |
| 1043 | #define UVH_IPI_INT_32 0x348 | 2560 | #define UV1H_IPI_INT 0x60500UL |
| 2561 | #define UV2H_IPI_INT 0x60500UL | ||
| 2562 | #define UV3H_IPI_INT 0x60500UL | ||
| 2563 | #define UVH_IPI_INT_32 0x348 | ||
| 2564 | #define UV1H_IPI_INT_32 0x60500UL | ||
| 2565 | #define UV2H_IPI_INT_32 0x60500UL | ||
| 2566 | #define UV3H_IPI_INT_32 0x60500UL | ||
| 1044 | 2567 | ||
| 1045 | #define UVH_IPI_INT_VECTOR_SHFT 0 | 2568 | #define UVH_IPI_INT_VECTOR_SHFT 0 |
| 1046 | #define UVH_IPI_INT_DELIVERY_MODE_SHFT 8 | 2569 | #define UVH_IPI_INT_DELIVERY_MODE_SHFT 8 |
| @@ -1053,6 +2576,50 @@ union uvh_int_cmpd_u { | |||
| 1053 | #define UVH_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL | 2576 | #define UVH_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL |
| 1054 | #define UVH_IPI_INT_SEND_MASK 0x8000000000000000UL | 2577 | #define UVH_IPI_INT_SEND_MASK 0x8000000000000000UL |
| 1055 | 2578 | ||
| 2579 | #define UV1H_IPI_INT_VECTOR_SHFT 0 | ||
| 2580 | #define UV1H_IPI_INT_DELIVERY_MODE_SHFT 8 | ||
| 2581 | #define UV1H_IPI_INT_DESTMODE_SHFT 11 | ||
| 2582 | #define UV1H_IPI_INT_APIC_ID_SHFT 16 | ||
| 2583 | #define UV1H_IPI_INT_SEND_SHFT 63 | ||
| 2584 | #define UV1H_IPI_INT_VECTOR_MASK 0x00000000000000ffUL | ||
| 2585 | #define UV1H_IPI_INT_DELIVERY_MODE_MASK 0x0000000000000700UL | ||
| 2586 | #define UV1H_IPI_INT_DESTMODE_MASK 0x0000000000000800UL | ||
| 2587 | #define UV1H_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL | ||
| 2588 | #define UV1H_IPI_INT_SEND_MASK 0x8000000000000000UL | ||
| 2589 | |||
| 2590 | #define UVXH_IPI_INT_VECTOR_SHFT 0 | ||
| 2591 | #define UVXH_IPI_INT_DELIVERY_MODE_SHFT 8 | ||
| 2592 | #define UVXH_IPI_INT_DESTMODE_SHFT 11 | ||
| 2593 | #define UVXH_IPI_INT_APIC_ID_SHFT 16 | ||
| 2594 | #define UVXH_IPI_INT_SEND_SHFT 63 | ||
| 2595 | #define UVXH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL | ||
| 2596 | #define UVXH_IPI_INT_DELIVERY_MODE_MASK 0x0000000000000700UL | ||
| 2597 | #define UVXH_IPI_INT_DESTMODE_MASK 0x0000000000000800UL | ||
| 2598 | #define UVXH_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL | ||
| 2599 | #define UVXH_IPI_INT_SEND_MASK 0x8000000000000000UL | ||
| 2600 | |||
| 2601 | #define UV2H_IPI_INT_VECTOR_SHFT 0 | ||
| 2602 | #define UV2H_IPI_INT_DELIVERY_MODE_SHFT 8 | ||
| 2603 | #define UV2H_IPI_INT_DESTMODE_SHFT 11 | ||
| 2604 | #define UV2H_IPI_INT_APIC_ID_SHFT 16 | ||
| 2605 | #define UV2H_IPI_INT_SEND_SHFT 63 | ||
| 2606 | #define UV2H_IPI_INT_VECTOR_MASK 0x00000000000000ffUL | ||
| 2607 | #define UV2H_IPI_INT_DELIVERY_MODE_MASK 0x0000000000000700UL | ||
| 2608 | #define UV2H_IPI_INT_DESTMODE_MASK 0x0000000000000800UL | ||
| 2609 | #define UV2H_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL | ||
| 2610 | #define UV2H_IPI_INT_SEND_MASK 0x8000000000000000UL | ||
| 2611 | |||
| 2612 | #define UV3H_IPI_INT_VECTOR_SHFT 0 | ||
| 2613 | #define UV3H_IPI_INT_DELIVERY_MODE_SHFT 8 | ||
| 2614 | #define UV3H_IPI_INT_DESTMODE_SHFT 11 | ||
| 2615 | #define UV3H_IPI_INT_APIC_ID_SHFT 16 | ||
| 2616 | #define UV3H_IPI_INT_SEND_SHFT 63 | ||
| 2617 | #define UV3H_IPI_INT_VECTOR_MASK 0x00000000000000ffUL | ||
| 2618 | #define UV3H_IPI_INT_DELIVERY_MODE_MASK 0x0000000000000700UL | ||
| 2619 | #define UV3H_IPI_INT_DESTMODE_MASK 0x0000000000000800UL | ||
| 2620 | #define UV3H_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL | ||
| 2621 | #define UV3H_IPI_INT_SEND_MASK 0x8000000000000000UL | ||
| 2622 | |||
| 1056 | union uvh_ipi_int_u { | 2623 | union uvh_ipi_int_u { |
| 1057 | unsigned long v; | 2624 | unsigned long v; |
| 1058 | struct uvh_ipi_int_s { | 2625 | struct uvh_ipi_int_s { |
| @@ -1064,19 +2631,81 @@ union uvh_ipi_int_u { | |||
| 1064 | unsigned long rsvd_48_62:15; | 2631 | unsigned long rsvd_48_62:15; |
| 1065 | unsigned long send:1; /* WP */ | 2632 | unsigned long send:1; /* WP */ |
| 1066 | } s; | 2633 | } s; |
| 2634 | struct uv1h_ipi_int_s { | ||
| 2635 | unsigned long vector_:8; /* RW */ | ||
| 2636 | unsigned long delivery_mode:3; /* RW */ | ||
| 2637 | unsigned long destmode:1; /* RW */ | ||
| 2638 | unsigned long rsvd_12_15:4; | ||
| 2639 | unsigned long apic_id:32; /* RW */ | ||
| 2640 | unsigned long rsvd_48_62:15; | ||
| 2641 | unsigned long send:1; /* WP */ | ||
| 2642 | } s1; | ||
| 2643 | struct uvxh_ipi_int_s { | ||
| 2644 | unsigned long vector_:8; /* RW */ | ||
| 2645 | unsigned long delivery_mode:3; /* RW */ | ||
| 2646 | unsigned long destmode:1; /* RW */ | ||
| 2647 | unsigned long rsvd_12_15:4; | ||
| 2648 | unsigned long apic_id:32; /* RW */ | ||
| 2649 | unsigned long rsvd_48_62:15; | ||
| 2650 | unsigned long send:1; /* WP */ | ||
| 2651 | } sx; | ||
| 2652 | struct uv2h_ipi_int_s { | ||
| 2653 | unsigned long vector_:8; /* RW */ | ||
| 2654 | unsigned long delivery_mode:3; /* RW */ | ||
| 2655 | unsigned long destmode:1; /* RW */ | ||
| 2656 | unsigned long rsvd_12_15:4; | ||
| 2657 | unsigned long apic_id:32; /* RW */ | ||
| 2658 | unsigned long rsvd_48_62:15; | ||
| 2659 | unsigned long send:1; /* WP */ | ||
| 2660 | } s2; | ||
| 2661 | struct uv3h_ipi_int_s { | ||
| 2662 | unsigned long vector_:8; /* RW */ | ||
| 2663 | unsigned long delivery_mode:3; /* RW */ | ||
| 2664 | unsigned long destmode:1; /* RW */ | ||
| 2665 | unsigned long rsvd_12_15:4; | ||
| 2666 | unsigned long apic_id:32; /* RW */ | ||
| 2667 | unsigned long rsvd_48_62:15; | ||
| 2668 | unsigned long send:1; /* WP */ | ||
| 2669 | } s3; | ||
| 1067 | }; | 2670 | }; |
| 1068 | 2671 | ||
| 1069 | /* ========================================================================= */ | 2672 | /* ========================================================================= */ |
| 1070 | /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST */ | 2673 | /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST */ |
| 1071 | /* ========================================================================= */ | 2674 | /* ========================================================================= */ |
| 1072 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL | 2675 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL |
| 1073 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x9c0 | 2676 | #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL |
| 2677 | #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL | ||
| 2678 | #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL | ||
| 2679 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x9c0 | ||
| 2680 | #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x320050UL | ||
| 2681 | #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x320050UL | ||
| 2682 | #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x320050UL | ||
| 1074 | 2683 | ||
| 1075 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4 | 2684 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4 |
| 1076 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49 | 2685 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49 |
| 1077 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL | 2686 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL |
| 1078 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL | 2687 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL |
| 1079 | 2688 | ||
| 2689 | #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4 | ||
| 2690 | #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49 | ||
| 2691 | #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL | ||
| 2692 | #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL | ||
| 2693 | |||
| 2694 | #define UVXH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4 | ||
| 2695 | #define UVXH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49 | ||
| 2696 | #define UVXH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL | ||
| 2697 | #define UVXH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL | ||
| 2698 | |||
| 2699 | #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4 | ||
| 2700 | #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49 | ||
| 2701 | #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL | ||
| 2702 | #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL | ||
| 2703 | |||
| 2704 | #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4 | ||
| 2705 | #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49 | ||
| 2706 | #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL | ||
| 2707 | #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL | ||
| 2708 | |||
| 1080 | union uvh_lb_bau_intd_payload_queue_first_u { | 2709 | union uvh_lb_bau_intd_payload_queue_first_u { |
| 1081 | unsigned long v; | 2710 | unsigned long v; |
| 1082 | struct uvh_lb_bau_intd_payload_queue_first_s { | 2711 | struct uvh_lb_bau_intd_payload_queue_first_s { |
| @@ -1086,17 +2715,63 @@ union uvh_lb_bau_intd_payload_queue_first_u { | |||
| 1086 | unsigned long node_id:14; /* RW */ | 2715 | unsigned long node_id:14; /* RW */ |
| 1087 | unsigned long rsvd_63:1; | 2716 | unsigned long rsvd_63:1; |
| 1088 | } s; | 2717 | } s; |
| 2718 | struct uv1h_lb_bau_intd_payload_queue_first_s { | ||
| 2719 | unsigned long rsvd_0_3:4; | ||
| 2720 | unsigned long address:39; /* RW */ | ||
| 2721 | unsigned long rsvd_43_48:6; | ||
| 2722 | unsigned long node_id:14; /* RW */ | ||
| 2723 | unsigned long rsvd_63:1; | ||
| 2724 | } s1; | ||
| 2725 | struct uvxh_lb_bau_intd_payload_queue_first_s { | ||
| 2726 | unsigned long rsvd_0_3:4; | ||
| 2727 | unsigned long address:39; /* RW */ | ||
| 2728 | unsigned long rsvd_43_48:6; | ||
| 2729 | unsigned long node_id:14; /* RW */ | ||
| 2730 | unsigned long rsvd_63:1; | ||
| 2731 | } sx; | ||
| 2732 | struct uv2h_lb_bau_intd_payload_queue_first_s { | ||
| 2733 | unsigned long rsvd_0_3:4; | ||
| 2734 | unsigned long address:39; /* RW */ | ||
| 2735 | unsigned long rsvd_43_48:6; | ||
| 2736 | unsigned long node_id:14; /* RW */ | ||
| 2737 | unsigned long rsvd_63:1; | ||
| 2738 | } s2; | ||
| 2739 | struct uv3h_lb_bau_intd_payload_queue_first_s { | ||
| 2740 | unsigned long rsvd_0_3:4; | ||
| 2741 | unsigned long address:39; /* RW */ | ||
| 2742 | unsigned long rsvd_43_48:6; | ||
| 2743 | unsigned long node_id:14; /* RW */ | ||
| 2744 | unsigned long rsvd_63:1; | ||
| 2745 | } s3; | ||
| 1089 | }; | 2746 | }; |
| 1090 | 2747 | ||
| 1091 | /* ========================================================================= */ | 2748 | /* ========================================================================= */ |
| 1092 | /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST */ | 2749 | /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST */ |
| 1093 | /* ========================================================================= */ | 2750 | /* ========================================================================= */ |
| 1094 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL | 2751 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL |
| 1095 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x9c8 | 2752 | #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL |
| 2753 | #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL | ||
| 2754 | #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL | ||
| 2755 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x9c8 | ||
| 2756 | #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x320060UL | ||
| 2757 | #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x320060UL | ||
| 2758 | #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x320060UL | ||
| 1096 | 2759 | ||
| 1097 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4 | 2760 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4 |
| 1098 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL | 2761 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL |
| 1099 | 2762 | ||
| 2763 | #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4 | ||
| 2764 | #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL | ||
| 2765 | |||
| 2766 | #define UVXH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4 | ||
| 2767 | #define UVXH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL | ||
| 2768 | |||
| 2769 | #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4 | ||
| 2770 | #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL | ||
| 2771 | |||
| 2772 | #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4 | ||
| 2773 | #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL | ||
| 2774 | |||
| 1100 | union uvh_lb_bau_intd_payload_queue_last_u { | 2775 | union uvh_lb_bau_intd_payload_queue_last_u { |
| 1101 | unsigned long v; | 2776 | unsigned long v; |
| 1102 | struct uvh_lb_bau_intd_payload_queue_last_s { | 2777 | struct uvh_lb_bau_intd_payload_queue_last_s { |
| @@ -1104,17 +2779,55 @@ union uvh_lb_bau_intd_payload_queue_last_u { | |||
| 1104 | unsigned long address:39; /* RW */ | 2779 | unsigned long address:39; /* RW */ |
| 1105 | unsigned long rsvd_43_63:21; | 2780 | unsigned long rsvd_43_63:21; |
| 1106 | } s; | 2781 | } s; |
| 2782 | struct uv1h_lb_bau_intd_payload_queue_last_s { | ||
| 2783 | unsigned long rsvd_0_3:4; | ||
| 2784 | unsigned long address:39; /* RW */ | ||
| 2785 | unsigned long rsvd_43_63:21; | ||
| 2786 | } s1; | ||
| 2787 | struct uvxh_lb_bau_intd_payload_queue_last_s { | ||
| 2788 | unsigned long rsvd_0_3:4; | ||
| 2789 | unsigned long address:39; /* RW */ | ||
| 2790 | unsigned long rsvd_43_63:21; | ||
| 2791 | } sx; | ||
| 2792 | struct uv2h_lb_bau_intd_payload_queue_last_s { | ||
| 2793 | unsigned long rsvd_0_3:4; | ||
| 2794 | unsigned long address:39; /* RW */ | ||
| 2795 | unsigned long rsvd_43_63:21; | ||
| 2796 | } s2; | ||
| 2797 | struct uv3h_lb_bau_intd_payload_queue_last_s { | ||
| 2798 | unsigned long rsvd_0_3:4; | ||
| 2799 | unsigned long address:39; /* RW */ | ||
| 2800 | unsigned long rsvd_43_63:21; | ||
| 2801 | } s3; | ||
| 1107 | }; | 2802 | }; |
| 1108 | 2803 | ||
| 1109 | /* ========================================================================= */ | 2804 | /* ========================================================================= */ |
| 1110 | /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL */ | 2805 | /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL */ |
| 1111 | /* ========================================================================= */ | 2806 | /* ========================================================================= */ |
| 1112 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL | 2807 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL |
| 1113 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x9d0 | 2808 | #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL |
| 2809 | #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL | ||
| 2810 | #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL | ||
| 2811 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x9d0 | ||
| 2812 | #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x320070UL | ||
| 2813 | #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x320070UL | ||
| 2814 | #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x320070UL | ||
| 1114 | 2815 | ||
| 1115 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4 | 2816 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4 |
| 1116 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL | 2817 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL |
| 1117 | 2818 | ||
| 2819 | #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4 | ||
| 2820 | #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL | ||
| 2821 | |||
| 2822 | #define UVXH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4 | ||
| 2823 | #define UVXH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL | ||
| 2824 | |||
| 2825 | #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4 | ||
| 2826 | #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL | ||
| 2827 | |||
| 2828 | #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4 | ||
| 2829 | #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL | ||
| 2830 | |||
| 1118 | union uvh_lb_bau_intd_payload_queue_tail_u { | 2831 | union uvh_lb_bau_intd_payload_queue_tail_u { |
| 1119 | unsigned long v; | 2832 | unsigned long v; |
| 1120 | struct uvh_lb_bau_intd_payload_queue_tail_s { | 2833 | struct uvh_lb_bau_intd_payload_queue_tail_s { |
| @@ -1122,13 +2835,39 @@ union uvh_lb_bau_intd_payload_queue_tail_u { | |||
| 1122 | unsigned long address:39; /* RW */ | 2835 | unsigned long address:39; /* RW */ |
| 1123 | unsigned long rsvd_43_63:21; | 2836 | unsigned long rsvd_43_63:21; |
| 1124 | } s; | 2837 | } s; |
| 2838 | struct uv1h_lb_bau_intd_payload_queue_tail_s { | ||
| 2839 | unsigned long rsvd_0_3:4; | ||
| 2840 | unsigned long address:39; /* RW */ | ||
| 2841 | unsigned long rsvd_43_63:21; | ||
| 2842 | } s1; | ||
| 2843 | struct uvxh_lb_bau_intd_payload_queue_tail_s { | ||
| 2844 | unsigned long rsvd_0_3:4; | ||
| 2845 | unsigned long address:39; /* RW */ | ||
| 2846 | unsigned long rsvd_43_63:21; | ||
| 2847 | } sx; | ||
| 2848 | struct uv2h_lb_bau_intd_payload_queue_tail_s { | ||
| 2849 | unsigned long rsvd_0_3:4; | ||
| 2850 | unsigned long address:39; /* RW */ | ||
| 2851 | unsigned long rsvd_43_63:21; | ||
| 2852 | } s2; | ||
| 2853 | struct uv3h_lb_bau_intd_payload_queue_tail_s { | ||
| 2854 | unsigned long rsvd_0_3:4; | ||
| 2855 | unsigned long address:39; /* RW */ | ||
| 2856 | unsigned long rsvd_43_63:21; | ||
| 2857 | } s3; | ||
| 1125 | }; | 2858 | }; |
| 1126 | 2859 | ||
| 1127 | /* ========================================================================= */ | 2860 | /* ========================================================================= */ |
| 1128 | /* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE */ | 2861 | /* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE */ |
| 1129 | /* ========================================================================= */ | 2862 | /* ========================================================================= */ |
| 1130 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL | 2863 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL |
| 1131 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0xa68 | 2864 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL |
| 2865 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL | ||
| 2866 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL | ||
| 2867 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0xa68 | ||
| 2868 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0x320080UL | ||
| 2869 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0x320080UL | ||
| 2870 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0x320080UL | ||
| 1132 | 2871 | ||
| 1133 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 | 2872 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 |
| 1134 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1 | 2873 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1 |
| @@ -1163,6 +2902,138 @@ union uvh_lb_bau_intd_payload_queue_tail_u { | |||
| 1163 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL | 2902 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL |
| 1164 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL | 2903 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL |
| 1165 | 2904 | ||
| 2905 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 | ||
| 2906 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1 | ||
| 2907 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2 | ||
| 2908 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3 | ||
| 2909 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4 | ||
| 2910 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5 | ||
| 2911 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6 | ||
| 2912 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7 | ||
| 2913 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8 | ||
| 2914 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9 | ||
| 2915 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10 | ||
| 2916 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11 | ||
| 2917 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12 | ||
| 2918 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13 | ||
| 2919 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14 | ||
| 2920 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15 | ||
| 2921 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL | ||
| 2922 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL | ||
| 2923 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL | ||
| 2924 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL | ||
| 2925 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL | ||
| 2926 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL | ||
| 2927 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL | ||
| 2928 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL | ||
| 2929 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL | ||
| 2930 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL | ||
| 2931 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL | ||
| 2932 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL | ||
| 2933 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL | ||
| 2934 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL | ||
| 2935 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL | ||
| 2936 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL | ||
| 2937 | |||
| 2938 | #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 | ||
| 2939 | #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1 | ||
| 2940 | #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2 | ||
| 2941 | #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3 | ||
| 2942 | #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4 | ||
| 2943 | #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5 | ||
| 2944 | #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6 | ||
| 2945 | #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7 | ||
| 2946 | #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8 | ||
| 2947 | #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9 | ||
| 2948 | #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10 | ||
| 2949 | #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11 | ||
| 2950 | #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12 | ||
| 2951 | #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13 | ||
| 2952 | #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14 | ||
| 2953 | #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15 | ||
| 2954 | #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL | ||
| 2955 | #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL | ||
| 2956 | #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL | ||
| 2957 | #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL | ||
| 2958 | #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL | ||
| 2959 | #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL | ||
| 2960 | #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL | ||
| 2961 | #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL | ||
| 2962 | #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL | ||
| 2963 | #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL | ||
| 2964 | #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL | ||
| 2965 | #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL | ||
| 2966 | #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL | ||
| 2967 | #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL | ||
| 2968 | #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL | ||
| 2969 | #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL | ||
| 2970 | |||
| 2971 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 | ||
| 2972 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1 | ||
| 2973 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2 | ||
| 2974 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3 | ||
| 2975 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4 | ||
| 2976 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5 | ||
| 2977 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6 | ||
| 2978 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7 | ||
| 2979 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8 | ||
| 2980 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9 | ||
| 2981 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10 | ||
| 2982 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11 | ||
| 2983 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12 | ||
| 2984 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13 | ||
| 2985 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14 | ||
| 2986 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15 | ||
| 2987 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL | ||
| 2988 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL | ||
| 2989 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL | ||
| 2990 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL | ||
| 2991 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL | ||
| 2992 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL | ||
| 2993 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL | ||
| 2994 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL | ||
| 2995 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL | ||
| 2996 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL | ||
| 2997 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL | ||
| 2998 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL | ||
| 2999 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL | ||
| 3000 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL | ||
| 3001 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL | ||
| 3002 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL | ||
| 3003 | |||
| 3004 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 | ||
| 3005 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1 | ||
| 3006 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2 | ||
| 3007 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3 | ||
| 3008 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4 | ||
| 3009 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5 | ||
| 3010 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6 | ||
| 3011 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7 | ||
| 3012 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8 | ||
| 3013 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9 | ||
| 3014 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10 | ||
| 3015 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11 | ||
| 3016 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12 | ||
| 3017 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13 | ||
| 3018 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14 | ||
| 3019 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15 | ||
| 3020 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL | ||
| 3021 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL | ||
| 3022 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL | ||
| 3023 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL | ||
| 3024 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL | ||
| 3025 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL | ||
| 3026 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL | ||
| 3027 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL | ||
| 3028 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL | ||
| 3029 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL | ||
| 3030 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL | ||
| 3031 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL | ||
| 3032 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL | ||
| 3033 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL | ||
| 3034 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL | ||
| 3035 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL | ||
| 3036 | |||
| 1166 | union uvh_lb_bau_intd_software_acknowledge_u { | 3037 | union uvh_lb_bau_intd_software_acknowledge_u { |
| 1167 | unsigned long v; | 3038 | unsigned long v; |
| 1168 | struct uvh_lb_bau_intd_software_acknowledge_s { | 3039 | struct uvh_lb_bau_intd_software_acknowledge_s { |
| @@ -1184,19 +3055,108 @@ union uvh_lb_bau_intd_software_acknowledge_u { | |||
| 1184 | unsigned long timeout_7:1; /* RW, W1C */ | 3055 | unsigned long timeout_7:1; /* RW, W1C */ |
| 1185 | unsigned long rsvd_16_63:48; | 3056 | unsigned long rsvd_16_63:48; |
| 1186 | } s; | 3057 | } s; |
| 3058 | struct uv1h_lb_bau_intd_software_acknowledge_s { | ||
| 3059 | unsigned long pending_0:1; /* RW, W1C */ | ||
| 3060 | unsigned long pending_1:1; /* RW, W1C */ | ||
| 3061 | unsigned long pending_2:1; /* RW, W1C */ | ||
| 3062 | unsigned long pending_3:1; /* RW, W1C */ | ||
| 3063 | unsigned long pending_4:1; /* RW, W1C */ | ||
| 3064 | unsigned long pending_5:1; /* RW, W1C */ | ||
| 3065 | unsigned long pending_6:1; /* RW, W1C */ | ||
| 3066 | unsigned long pending_7:1; /* RW, W1C */ | ||
| 3067 | unsigned long timeout_0:1; /* RW, W1C */ | ||
| 3068 | unsigned long timeout_1:1; /* RW, W1C */ | ||
| 3069 | unsigned long timeout_2:1; /* RW, W1C */ | ||
| 3070 | unsigned long timeout_3:1; /* RW, W1C */ | ||
| 3071 | unsigned long timeout_4:1; /* RW, W1C */ | ||
| 3072 | unsigned long timeout_5:1; /* RW, W1C */ | ||
| 3073 | unsigned long timeout_6:1; /* RW, W1C */ | ||
| 3074 | unsigned long timeout_7:1; /* RW, W1C */ | ||
| 3075 | unsigned long rsvd_16_63:48; | ||
| 3076 | } s1; | ||
| 3077 | struct uvxh_lb_bau_intd_software_acknowledge_s { | ||
| 3078 | unsigned long pending_0:1; /* RW */ | ||
| 3079 | unsigned long pending_1:1; /* RW */ | ||
| 3080 | unsigned long pending_2:1; /* RW */ | ||
| 3081 | unsigned long pending_3:1; /* RW */ | ||
| 3082 | unsigned long pending_4:1; /* RW */ | ||
| 3083 | unsigned long pending_5:1; /* RW */ | ||
| 3084 | unsigned long pending_6:1; /* RW */ | ||
| 3085 | unsigned long pending_7:1; /* RW */ | ||
| 3086 | unsigned long timeout_0:1; /* RW */ | ||
| 3087 | unsigned long timeout_1:1; /* RW */ | ||
| 3088 | unsigned long timeout_2:1; /* RW */ | ||
| 3089 | unsigned long timeout_3:1; /* RW */ | ||
| 3090 | unsigned long timeout_4:1; /* RW */ | ||
| 3091 | unsigned long timeout_5:1; /* RW */ | ||
| 3092 | unsigned long timeout_6:1; /* RW */ | ||
| 3093 | unsigned long timeout_7:1; /* RW */ | ||
| 3094 | unsigned long rsvd_16_63:48; | ||
| 3095 | } sx; | ||
| 3096 | struct uv2h_lb_bau_intd_software_acknowledge_s { | ||
| 3097 | unsigned long pending_0:1; /* RW */ | ||
| 3098 | unsigned long pending_1:1; /* RW */ | ||
| 3099 | unsigned long pending_2:1; /* RW */ | ||
| 3100 | unsigned long pending_3:1; /* RW */ | ||
| 3101 | unsigned long pending_4:1; /* RW */ | ||
| 3102 | unsigned long pending_5:1; /* RW */ | ||
| 3103 | unsigned long pending_6:1; /* RW */ | ||
| 3104 | unsigned long pending_7:1; /* RW */ | ||
| 3105 | unsigned long timeout_0:1; /* RW */ | ||
| 3106 | unsigned long timeout_1:1; /* RW */ | ||
| 3107 | unsigned long timeout_2:1; /* RW */ | ||
| 3108 | unsigned long timeout_3:1; /* RW */ | ||
| 3109 | unsigned long timeout_4:1; /* RW */ | ||
| 3110 | unsigned long timeout_5:1; /* RW */ | ||
| 3111 | unsigned long timeout_6:1; /* RW */ | ||
| 3112 | unsigned long timeout_7:1; /* RW */ | ||
| 3113 | unsigned long rsvd_16_63:48; | ||
| 3114 | } s2; | ||
| 3115 | struct uv3h_lb_bau_intd_software_acknowledge_s { | ||
| 3116 | unsigned long pending_0:1; /* RW */ | ||
| 3117 | unsigned long pending_1:1; /* RW */ | ||
| 3118 | unsigned long pending_2:1; /* RW */ | ||
| 3119 | unsigned long pending_3:1; /* RW */ | ||
| 3120 | unsigned long pending_4:1; /* RW */ | ||
| 3121 | unsigned long pending_5:1; /* RW */ | ||
| 3122 | unsigned long pending_6:1; /* RW */ | ||
| 3123 | unsigned long pending_7:1; /* RW */ | ||
| 3124 | unsigned long timeout_0:1; /* RW */ | ||
| 3125 | unsigned long timeout_1:1; /* RW */ | ||
| 3126 | unsigned long timeout_2:1; /* RW */ | ||
| 3127 | unsigned long timeout_3:1; /* RW */ | ||
| 3128 | unsigned long timeout_4:1; /* RW */ | ||
| 3129 | unsigned long timeout_5:1; /* RW */ | ||
| 3130 | unsigned long timeout_6:1; /* RW */ | ||
| 3131 | unsigned long timeout_7:1; /* RW */ | ||
| 3132 | unsigned long rsvd_16_63:48; | ||
| 3133 | } s3; | ||
| 1187 | }; | 3134 | }; |
| 1188 | 3135 | ||
| 1189 | /* ========================================================================= */ | 3136 | /* ========================================================================= */ |
| 1190 | /* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS */ | 3137 | /* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS */ |
| 1191 | /* ========================================================================= */ | 3138 | /* ========================================================================= */ |
| 1192 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x0000000000320088UL | 3139 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL |
| 1193 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0xa70 | 3140 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL |
| 3141 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL | ||
| 3142 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL | ||
| 3143 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0xa70 | ||
| 3144 | #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0x320088UL | ||
| 3145 | #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0x320088UL | ||
| 3146 | #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0x320088UL | ||
| 3147 | |||
| 1194 | 3148 | ||
| 1195 | /* ========================================================================= */ | 3149 | /* ========================================================================= */ |
| 1196 | /* UVH_LB_BAU_MISC_CONTROL */ | 3150 | /* UVH_LB_BAU_MISC_CONTROL */ |
| 1197 | /* ========================================================================= */ | 3151 | /* ========================================================================= */ |
| 1198 | #define UVH_LB_BAU_MISC_CONTROL 0x320170UL | 3152 | #define UVH_LB_BAU_MISC_CONTROL 0x320170UL |
| 1199 | #define UVH_LB_BAU_MISC_CONTROL_32 0xa10 | 3153 | #define UV1H_LB_BAU_MISC_CONTROL 0x320170UL |
| 3154 | #define UV2H_LB_BAU_MISC_CONTROL 0x320170UL | ||
| 3155 | #define UV3H_LB_BAU_MISC_CONTROL 0x320170UL | ||
| 3156 | #define UVH_LB_BAU_MISC_CONTROL_32 0xa10 | ||
| 3157 | #define UV1H_LB_BAU_MISC_CONTROL_32 0x320170UL | ||
| 3158 | #define UV2H_LB_BAU_MISC_CONTROL_32 0x320170UL | ||
| 3159 | #define UV3H_LB_BAU_MISC_CONTROL_32 0x320170UL | ||
| 1200 | 3160 | ||
| 1201 | #define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 | 3161 | #define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 |
| 1202 | #define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 | 3162 | #define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 |
| @@ -1213,6 +3173,7 @@ union uvh_lb_bau_intd_software_acknowledge_u { | |||
| 1213 | #define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 | 3173 | #define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 |
| 1214 | #define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 | 3174 | #define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 |
| 1215 | #define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 | 3175 | #define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 |
| 3176 | #define UVH_LB_BAU_MISC_CONTROL_FUN_SHFT 48 | ||
| 1216 | #define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL | 3177 | #define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL |
| 1217 | #define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL | 3178 | #define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL |
| 1218 | #define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL | 3179 | #define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL |
| @@ -1228,6 +3189,7 @@ union uvh_lb_bau_intd_software_acknowledge_u { | |||
| 1228 | #define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL | 3189 | #define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL |
| 1229 | #define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL | 3190 | #define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL |
| 1230 | #define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL | 3191 | #define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL |
| 3192 | #define UVH_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL | ||
| 1231 | 3193 | ||
| 1232 | #define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 | 3194 | #define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 |
| 1233 | #define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 | 3195 | #define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 |
| @@ -1262,6 +3224,53 @@ union uvh_lb_bau_intd_software_acknowledge_u { | |||
| 1262 | #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL | 3224 | #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL |
| 1263 | #define UV1H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL | 3225 | #define UV1H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL |
| 1264 | 3226 | ||
| 3227 | #define UVXH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 | ||
| 3228 | #define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 | ||
| 3229 | #define UVXH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 | ||
| 3230 | #define UVXH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 | ||
| 3231 | #define UVXH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 | ||
| 3232 | #define UVXH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 | ||
| 3233 | #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15 | ||
| 3234 | #define UVXH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16 | ||
| 3235 | #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 | ||
| 3236 | #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 | ||
| 3237 | #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 | ||
| 3238 | #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 | ||
| 3239 | #define UVXH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 | ||
| 3240 | #define UVXH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 | ||
| 3241 | #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 | ||
| 3242 | #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29 | ||
| 3243 | #define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT 30 | ||
| 3244 | #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31 | ||
| 3245 | #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32 | ||
| 3246 | #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33 | ||
| 3247 | #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34 | ||
| 3248 | #define UVXH_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35 | ||
| 3249 | #define UVXH_LB_BAU_MISC_CONTROL_FUN_SHFT 48 | ||
| 3250 | #define UVXH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL | ||
| 3251 | #define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL | ||
| 3252 | #define UVXH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL | ||
| 3253 | #define UVXH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL | ||
| 3254 | #define UVXH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL | ||
| 3255 | #define UVXH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL | ||
| 3256 | #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL | ||
| 3257 | #define UVXH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL | ||
| 3258 | #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL | ||
| 3259 | #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL | ||
| 3260 | #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL | ||
| 3261 | #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL | ||
| 3262 | #define UVXH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL | ||
| 3263 | #define UVXH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL | ||
| 3264 | #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL | ||
| 3265 | #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL | ||
| 3266 | #define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK 0x0000000040000000UL | ||
| 3267 | #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL | ||
| 3268 | #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL | ||
| 3269 | #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL | ||
| 3270 | #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL | ||
| 3271 | #define UVXH_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL | ||
| 3272 | #define UVXH_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL | ||
| 3273 | |||
| 1265 | #define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 | 3274 | #define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 |
| 1266 | #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 | 3275 | #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 |
| 1267 | #define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 | 3276 | #define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 |
| @@ -1309,6 +3318,59 @@ union uvh_lb_bau_intd_software_acknowledge_u { | |||
| 1309 | #define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL | 3318 | #define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL |
| 1310 | #define UV2H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL | 3319 | #define UV2H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL |
| 1311 | 3320 | ||
| 3321 | #define UV3H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 | ||
| 3322 | #define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 | ||
| 3323 | #define UV3H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 | ||
| 3324 | #define UV3H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 | ||
| 3325 | #define UV3H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 | ||
| 3326 | #define UV3H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 | ||
| 3327 | #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15 | ||
| 3328 | #define UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16 | ||
| 3329 | #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 | ||
| 3330 | #define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 | ||
| 3331 | #define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 | ||
| 3332 | #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 | ||
| 3333 | #define UV3H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 | ||
| 3334 | #define UV3H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 | ||
| 3335 | #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 | ||
| 3336 | #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29 | ||
| 3337 | #define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT 30 | ||
| 3338 | #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31 | ||
| 3339 | #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32 | ||
| 3340 | #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33 | ||
| 3341 | #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34 | ||
| 3342 | #define UV3H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35 | ||
| 3343 | #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_SHFT 36 | ||
| 3344 | #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_PREFETCH_HINT_SHFT 37 | ||
| 3345 | #define UV3H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_SHFT 38 | ||
| 3346 | #define UV3H_LB_BAU_MISC_CONTROL_FUN_SHFT 48 | ||
| 3347 | #define UV3H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL | ||
| 3348 | #define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL | ||
| 3349 | #define UV3H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL | ||
| 3350 | #define UV3H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL | ||
| 3351 | #define UV3H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL | ||
| 3352 | #define UV3H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL | ||
| 3353 | #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL | ||
| 3354 | #define UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL | ||
| 3355 | #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL | ||
| 3356 | #define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL | ||
| 3357 | #define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL | ||
| 3358 | #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL | ||
| 3359 | #define UV3H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL | ||
| 3360 | #define UV3H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL | ||
| 3361 | #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL | ||
| 3362 | #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL | ||
| 3363 | #define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK 0x0000000040000000UL | ||
| 3364 | #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL | ||
| 3365 | #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL | ||
| 3366 | #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL | ||
| 3367 | #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL | ||
| 3368 | #define UV3H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL | ||
| 3369 | #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_MASK 0x0000001000000000UL | ||
| 3370 | #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_PREFETCH_HINT_MASK 0x0000002000000000UL | ||
| 3371 | #define UV3H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_MASK 0x00003fc000000000UL | ||
| 3372 | #define UV3H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL | ||
| 3373 | |||
| 1312 | union uvh_lb_bau_misc_control_u { | 3374 | union uvh_lb_bau_misc_control_u { |
| 1313 | unsigned long v; | 3375 | unsigned long v; |
| 1314 | struct uvh_lb_bau_misc_control_s { | 3376 | struct uvh_lb_bau_misc_control_s { |
| @@ -1327,7 +3389,8 @@ union uvh_lb_bau_misc_control_u { | |||
| 1327 | unsigned long programmed_initial_priority:3; /* RW */ | 3389 | unsigned long programmed_initial_priority:3; /* RW */ |
| 1328 | unsigned long use_incoming_priority:1; /* RW */ | 3390 | unsigned long use_incoming_priority:1; /* RW */ |
| 1329 | unsigned long enable_programmed_initial_priority:1;/* RW */ | 3391 | unsigned long enable_programmed_initial_priority:1;/* RW */ |
| 1330 | unsigned long rsvd_29_63:35; | 3392 | unsigned long rsvd_29_47:19; |
| 3393 | unsigned long fun:16; /* RW */ | ||
| 1331 | } s; | 3394 | } s; |
| 1332 | struct uv1h_lb_bau_misc_control_s { | 3395 | struct uv1h_lb_bau_misc_control_s { |
| 1333 | unsigned long rejection_delay:8; /* RW */ | 3396 | unsigned long rejection_delay:8; /* RW */ |
| @@ -1348,6 +3411,32 @@ union uvh_lb_bau_misc_control_u { | |||
| 1348 | unsigned long rsvd_29_47:19; | 3411 | unsigned long rsvd_29_47:19; |
| 1349 | unsigned long fun:16; /* RW */ | 3412 | unsigned long fun:16; /* RW */ |
| 1350 | } s1; | 3413 | } s1; |
| 3414 | struct uvxh_lb_bau_misc_control_s { | ||
| 3415 | unsigned long rejection_delay:8; /* RW */ | ||
| 3416 | unsigned long apic_mode:1; /* RW */ | ||
| 3417 | unsigned long force_broadcast:1; /* RW */ | ||
| 3418 | unsigned long force_lock_nop:1; /* RW */ | ||
| 3419 | unsigned long qpi_agent_presence_vector:3; /* RW */ | ||
| 3420 | unsigned long descriptor_fetch_mode:1; /* RW */ | ||
| 3421 | unsigned long enable_intd_soft_ack_mode:1; /* RW */ | ||
| 3422 | unsigned long intd_soft_ack_timeout_period:4; /* RW */ | ||
| 3423 | unsigned long enable_dual_mapping_mode:1; /* RW */ | ||
| 3424 | unsigned long vga_io_port_decode_enable:1; /* RW */ | ||
| 3425 | unsigned long vga_io_port_16_bit_decode:1; /* RW */ | ||
| 3426 | unsigned long suppress_dest_registration:1; /* RW */ | ||
| 3427 | unsigned long programmed_initial_priority:3; /* RW */ | ||
| 3428 | unsigned long use_incoming_priority:1; /* RW */ | ||
| 3429 | unsigned long enable_programmed_initial_priority:1;/* RW */ | ||
| 3430 | unsigned long enable_automatic_apic_mode_selection:1;/* RW */ | ||
| 3431 | unsigned long apic_mode_status:1; /* RO */ | ||
| 3432 | unsigned long suppress_interrupts_to_self:1; /* RW */ | ||
| 3433 | unsigned long enable_lock_based_system_flush:1;/* RW */ | ||
| 3434 | unsigned long enable_extended_sb_status:1; /* RW */ | ||
| 3435 | unsigned long suppress_int_prio_udt_to_self:1;/* RW */ | ||
| 3436 | unsigned long use_legacy_descriptor_formats:1;/* RW */ | ||
| 3437 | unsigned long rsvd_36_47:12; | ||
| 3438 | unsigned long fun:16; /* RW */ | ||
| 3439 | } sx; | ||
| 1351 | struct uv2h_lb_bau_misc_control_s { | 3440 | struct uv2h_lb_bau_misc_control_s { |
| 1352 | unsigned long rejection_delay:8; /* RW */ | 3441 | unsigned long rejection_delay:8; /* RW */ |
| 1353 | unsigned long apic_mode:1; /* RW */ | 3442 | unsigned long apic_mode:1; /* RW */ |
| @@ -1374,13 +3463,48 @@ union uvh_lb_bau_misc_control_u { | |||
| 1374 | unsigned long rsvd_36_47:12; | 3463 | unsigned long rsvd_36_47:12; |
| 1375 | unsigned long fun:16; /* RW */ | 3464 | unsigned long fun:16; /* RW */ |
| 1376 | } s2; | 3465 | } s2; |
| 3466 | struct uv3h_lb_bau_misc_control_s { | ||
| 3467 | unsigned long rejection_delay:8; /* RW */ | ||
| 3468 | unsigned long apic_mode:1; /* RW */ | ||
| 3469 | unsigned long force_broadcast:1; /* RW */ | ||
| 3470 | unsigned long force_lock_nop:1; /* RW */ | ||
| 3471 | unsigned long qpi_agent_presence_vector:3; /* RW */ | ||
| 3472 | unsigned long descriptor_fetch_mode:1; /* RW */ | ||
| 3473 | unsigned long enable_intd_soft_ack_mode:1; /* RW */ | ||
| 3474 | unsigned long intd_soft_ack_timeout_period:4; /* RW */ | ||
| 3475 | unsigned long enable_dual_mapping_mode:1; /* RW */ | ||
| 3476 | unsigned long vga_io_port_decode_enable:1; /* RW */ | ||
| 3477 | unsigned long vga_io_port_16_bit_decode:1; /* RW */ | ||
| 3478 | unsigned long suppress_dest_registration:1; /* RW */ | ||
| 3479 | unsigned long programmed_initial_priority:3; /* RW */ | ||
| 3480 | unsigned long use_incoming_priority:1; /* RW */ | ||
| 3481 | unsigned long enable_programmed_initial_priority:1;/* RW */ | ||
| 3482 | unsigned long enable_automatic_apic_mode_selection:1;/* RW */ | ||
| 3483 | unsigned long apic_mode_status:1; /* RO */ | ||
| 3484 | unsigned long suppress_interrupts_to_self:1; /* RW */ | ||
| 3485 | unsigned long enable_lock_based_system_flush:1;/* RW */ | ||
| 3486 | unsigned long enable_extended_sb_status:1; /* RW */ | ||
| 3487 | unsigned long suppress_int_prio_udt_to_self:1;/* RW */ | ||
| 3488 | unsigned long use_legacy_descriptor_formats:1;/* RW */ | ||
| 3489 | unsigned long suppress_quiesce_msgs_to_qpi:1; /* RW */ | ||
| 3490 | unsigned long enable_intd_prefetch_hint:1; /* RW */ | ||
| 3491 | unsigned long thread_kill_timebase:8; /* RW */ | ||
| 3492 | unsigned long rsvd_46_47:2; | ||
| 3493 | unsigned long fun:16; /* RW */ | ||
| 3494 | } s3; | ||
| 1377 | }; | 3495 | }; |
| 1378 | 3496 | ||
| 1379 | /* ========================================================================= */ | 3497 | /* ========================================================================= */ |
| 1380 | /* UVH_LB_BAU_SB_ACTIVATION_CONTROL */ | 3498 | /* UVH_LB_BAU_SB_ACTIVATION_CONTROL */ |
| 1381 | /* ========================================================================= */ | 3499 | /* ========================================================================= */ |
| 1382 | #define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL | 3500 | #define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL |
| 1383 | #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8 | 3501 | #define UV1H_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL |
| 3502 | #define UV2H_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL | ||
| 3503 | #define UV3H_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL | ||
| 3504 | #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8 | ||
| 3505 | #define UV1H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x320020UL | ||
| 3506 | #define UV2H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x320020UL | ||
| 3507 | #define UV3H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x320020UL | ||
| 1384 | 3508 | ||
| 1385 | #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0 | 3509 | #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0 |
| 1386 | #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62 | 3510 | #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62 |
| @@ -1389,6 +3513,34 @@ union uvh_lb_bau_misc_control_u { | |||
| 1389 | #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL | 3513 | #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL |
| 1390 | #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL | 3514 | #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL |
| 1391 | 3515 | ||
| 3516 | #define UV1H_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0 | ||
| 3517 | #define UV1H_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62 | ||
| 3518 | #define UV1H_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT 63 | ||
| 3519 | #define UV1H_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL | ||
| 3520 | #define UV1H_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL | ||
| 3521 | #define UV1H_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL | ||
| 3522 | |||
| 3523 | #define UVXH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0 | ||
| 3524 | #define UVXH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62 | ||
| 3525 | #define UVXH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT 63 | ||
| 3526 | #define UVXH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL | ||
| 3527 | #define UVXH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL | ||
| 3528 | #define UVXH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL | ||
| 3529 | |||
| 3530 | #define UV2H_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0 | ||
| 3531 | #define UV2H_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62 | ||
| 3532 | #define UV2H_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT 63 | ||
| 3533 | #define UV2H_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL | ||
| 3534 | #define UV2H_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL | ||
| 3535 | #define UV2H_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL | ||
| 3536 | |||
| 3537 | #define UV3H_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0 | ||
| 3538 | #define UV3H_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62 | ||
| 3539 | #define UV3H_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT 63 | ||
| 3540 | #define UV3H_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL | ||
| 3541 | #define UV3H_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL | ||
| 3542 | #define UV3H_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL | ||
| 3543 | |||
| 1392 | union uvh_lb_bau_sb_activation_control_u { | 3544 | union uvh_lb_bau_sb_activation_control_u { |
| 1393 | unsigned long v; | 3545 | unsigned long v; |
| 1394 | struct uvh_lb_bau_sb_activation_control_s { | 3546 | struct uvh_lb_bau_sb_activation_control_s { |
| @@ -1397,51 +3549,161 @@ union uvh_lb_bau_sb_activation_control_u { | |||
| 1397 | unsigned long push:1; /* WP */ | 3549 | unsigned long push:1; /* WP */ |
| 1398 | unsigned long init:1; /* WP */ | 3550 | unsigned long init:1; /* WP */ |
| 1399 | } s; | 3551 | } s; |
| 3552 | struct uv1h_lb_bau_sb_activation_control_s { | ||
| 3553 | unsigned long index:6; /* RW */ | ||
| 3554 | unsigned long rsvd_6_61:56; | ||
| 3555 | unsigned long push:1; /* WP */ | ||
| 3556 | unsigned long init:1; /* WP */ | ||
| 3557 | } s1; | ||
| 3558 | struct uvxh_lb_bau_sb_activation_control_s { | ||
| 3559 | unsigned long index:6; /* RW */ | ||
| 3560 | unsigned long rsvd_6_61:56; | ||
| 3561 | unsigned long push:1; /* WP */ | ||
| 3562 | unsigned long init:1; /* WP */ | ||
| 3563 | } sx; | ||
| 3564 | struct uv2h_lb_bau_sb_activation_control_s { | ||
| 3565 | unsigned long index:6; /* RW */ | ||
| 3566 | unsigned long rsvd_6_61:56; | ||
| 3567 | unsigned long push:1; /* WP */ | ||
| 3568 | unsigned long init:1; /* WP */ | ||
| 3569 | } s2; | ||
| 3570 | struct uv3h_lb_bau_sb_activation_control_s { | ||
| 3571 | unsigned long index:6; /* RW */ | ||
| 3572 | unsigned long rsvd_6_61:56; | ||
| 3573 | unsigned long push:1; /* WP */ | ||
| 3574 | unsigned long init:1; /* WP */ | ||
| 3575 | } s3; | ||
| 1400 | }; | 3576 | }; |
| 1401 | 3577 | ||
| 1402 | /* ========================================================================= */ | 3578 | /* ========================================================================= */ |
| 1403 | /* UVH_LB_BAU_SB_ACTIVATION_STATUS_0 */ | 3579 | /* UVH_LB_BAU_SB_ACTIVATION_STATUS_0 */ |
| 1404 | /* ========================================================================= */ | 3580 | /* ========================================================================= */ |
| 1405 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL | 3581 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL |
| 1406 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0 | 3582 | #define UV1H_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL |
| 3583 | #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL | ||
| 3584 | #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL | ||
| 3585 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0 | ||
| 3586 | #define UV1H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x320030UL | ||
| 3587 | #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x320030UL | ||
| 3588 | #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x320030UL | ||
| 1407 | 3589 | ||
| 1408 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0 | 3590 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0 |
| 1409 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL | 3591 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL |
| 1410 | 3592 | ||
| 3593 | #define UV1H_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0 | ||
| 3594 | #define UV1H_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL | ||
| 3595 | |||
| 3596 | #define UVXH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0 | ||
| 3597 | #define UVXH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL | ||
| 3598 | |||
| 3599 | #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0 | ||
| 3600 | #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL | ||
| 3601 | |||
| 3602 | #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0 | ||
| 3603 | #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL | ||
| 3604 | |||
| 1411 | union uvh_lb_bau_sb_activation_status_0_u { | 3605 | union uvh_lb_bau_sb_activation_status_0_u { |
| 1412 | unsigned long v; | 3606 | unsigned long v; |
| 1413 | struct uvh_lb_bau_sb_activation_status_0_s { | 3607 | struct uvh_lb_bau_sb_activation_status_0_s { |
| 1414 | unsigned long status:64; /* RW */ | 3608 | unsigned long status:64; /* RW */ |
| 1415 | } s; | 3609 | } s; |
| 3610 | struct uv1h_lb_bau_sb_activation_status_0_s { | ||
| 3611 | unsigned long status:64; /* RW */ | ||
| 3612 | } s1; | ||
| 3613 | struct uvxh_lb_bau_sb_activation_status_0_s { | ||
| 3614 | unsigned long status:64; /* RW */ | ||
| 3615 | } sx; | ||
| 3616 | struct uv2h_lb_bau_sb_activation_status_0_s { | ||
| 3617 | unsigned long status:64; /* RW */ | ||
| 3618 | } s2; | ||
| 3619 | struct uv3h_lb_bau_sb_activation_status_0_s { | ||
| 3620 | unsigned long status:64; /* RW */ | ||
| 3621 | } s3; | ||
| 1416 | }; | 3622 | }; |
| 1417 | 3623 | ||
| 1418 | /* ========================================================================= */ | 3624 | /* ========================================================================= */ |
| 1419 | /* UVH_LB_BAU_SB_ACTIVATION_STATUS_1 */ | 3625 | /* UVH_LB_BAU_SB_ACTIVATION_STATUS_1 */ |
| 1420 | /* ========================================================================= */ | 3626 | /* ========================================================================= */ |
| 1421 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL | 3627 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL |
| 1422 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8 | 3628 | #define UV1H_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL |
| 3629 | #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL | ||
| 3630 | #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL | ||
| 3631 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8 | ||
| 3632 | #define UV1H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x320040UL | ||
| 3633 | #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x320040UL | ||
| 3634 | #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x320040UL | ||
| 1423 | 3635 | ||
| 1424 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0 | 3636 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0 |
| 1425 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL | 3637 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL |
| 1426 | 3638 | ||
| 3639 | #define UV1H_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0 | ||
| 3640 | #define UV1H_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL | ||
| 3641 | |||
| 3642 | #define UVXH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0 | ||
| 3643 | #define UVXH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL | ||
| 3644 | |||
| 3645 | #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0 | ||
| 3646 | #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL | ||
| 3647 | |||
| 3648 | #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0 | ||
| 3649 | #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL | ||
| 3650 | |||
| 1427 | union uvh_lb_bau_sb_activation_status_1_u { | 3651 | union uvh_lb_bau_sb_activation_status_1_u { |
| 1428 | unsigned long v; | 3652 | unsigned long v; |
| 1429 | struct uvh_lb_bau_sb_activation_status_1_s { | 3653 | struct uvh_lb_bau_sb_activation_status_1_s { |
| 1430 | unsigned long status:64; /* RW */ | 3654 | unsigned long status:64; /* RW */ |
| 1431 | } s; | 3655 | } s; |
| 3656 | struct uv1h_lb_bau_sb_activation_status_1_s { | ||
| 3657 | unsigned long status:64; /* RW */ | ||
| 3658 | } s1; | ||
| 3659 | struct uvxh_lb_bau_sb_activation_status_1_s { | ||
| 3660 | unsigned long status:64; /* RW */ | ||
| 3661 | } sx; | ||
| 3662 | struct uv2h_lb_bau_sb_activation_status_1_s { | ||
| 3663 | unsigned long status:64; /* RW */ | ||
| 3664 | } s2; | ||
| 3665 | struct uv3h_lb_bau_sb_activation_status_1_s { | ||
| 3666 | unsigned long status:64; /* RW */ | ||
| 3667 | } s3; | ||
| 1432 | }; | 3668 | }; |
| 1433 | 3669 | ||
| 1434 | /* ========================================================================= */ | 3670 | /* ========================================================================= */ |
| 1435 | /* UVH_LB_BAU_SB_DESCRIPTOR_BASE */ | 3671 | /* UVH_LB_BAU_SB_DESCRIPTOR_BASE */ |
| 1436 | /* ========================================================================= */ | 3672 | /* ========================================================================= */ |
| 1437 | #define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL | 3673 | #define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL |
| 1438 | #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0 | 3674 | #define UV1H_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL |
| 3675 | #define UV2H_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL | ||
| 3676 | #define UV3H_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL | ||
| 3677 | #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0 | ||
| 3678 | #define UV1H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x320010UL | ||
| 3679 | #define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x320010UL | ||
| 3680 | #define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x320010UL | ||
| 1439 | 3681 | ||
| 1440 | #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12 | 3682 | #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12 |
| 1441 | #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49 | 3683 | #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49 |
| 1442 | #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL | 3684 | #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL |
| 1443 | #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL | 3685 | #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL |
| 1444 | 3686 | ||
| 3687 | #define UV1H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12 | ||
| 3688 | #define UV1H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49 | ||
| 3689 | #define UV1H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL | ||
| 3690 | #define UV1H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL | ||
| 3691 | |||
| 3692 | #define UVXH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12 | ||
| 3693 | #define UVXH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49 | ||
| 3694 | #define UVXH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL | ||
| 3695 | #define UVXH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL | ||
| 3696 | |||
| 3697 | #define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12 | ||
| 3698 | #define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49 | ||
| 3699 | #define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL | ||
| 3700 | #define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL | ||
| 3701 | |||
| 3702 | #define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12 | ||
| 3703 | #define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49 | ||
| 3704 | #define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL | ||
| 3705 | #define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL | ||
| 3706 | |||
| 1445 | union uvh_lb_bau_sb_descriptor_base_u { | 3707 | union uvh_lb_bau_sb_descriptor_base_u { |
| 1446 | unsigned long v; | 3708 | unsigned long v; |
| 1447 | struct uvh_lb_bau_sb_descriptor_base_s { | 3709 | struct uvh_lb_bau_sb_descriptor_base_s { |
| @@ -1451,12 +3713,43 @@ union uvh_lb_bau_sb_descriptor_base_u { | |||
| 1451 | unsigned long node_id:14; /* RW */ | 3713 | unsigned long node_id:14; /* RW */ |
| 1452 | unsigned long rsvd_63:1; | 3714 | unsigned long rsvd_63:1; |
| 1453 | } s; | 3715 | } s; |
| 3716 | struct uv1h_lb_bau_sb_descriptor_base_s { | ||
| 3717 | unsigned long rsvd_0_11:12; | ||
| 3718 | unsigned long page_address:31; /* RW */ | ||
| 3719 | unsigned long rsvd_43_48:6; | ||
| 3720 | unsigned long node_id:14; /* RW */ | ||
| 3721 | unsigned long rsvd_63:1; | ||
| 3722 | } s1; | ||
| 3723 | struct uvxh_lb_bau_sb_descriptor_base_s { | ||
| 3724 | unsigned long rsvd_0_11:12; | ||
| 3725 | unsigned long page_address:31; /* RW */ | ||
| 3726 | unsigned long rsvd_43_48:6; | ||
| 3727 | unsigned long node_id:14; /* RW */ | ||
| 3728 | unsigned long rsvd_63:1; | ||
| 3729 | } sx; | ||
| 3730 | struct uv2h_lb_bau_sb_descriptor_base_s { | ||
| 3731 | unsigned long rsvd_0_11:12; | ||
| 3732 | unsigned long page_address:31; /* RW */ | ||
| 3733 | unsigned long rsvd_43_48:6; | ||
| 3734 | unsigned long node_id:14; /* RW */ | ||
| 3735 | unsigned long rsvd_63:1; | ||
| 3736 | } s2; | ||
| 3737 | struct uv3h_lb_bau_sb_descriptor_base_s { | ||
| 3738 | unsigned long rsvd_0_11:12; | ||
| 3739 | unsigned long page_address:31; /* RW */ | ||
| 3740 | unsigned long rsvd_43_48:6; | ||
| 3741 | unsigned long node_id:14; /* RW */ | ||
| 3742 | unsigned long rsvd_63:1; | ||
| 3743 | } s3; | ||
| 1454 | }; | 3744 | }; |
| 1455 | 3745 | ||
| 1456 | /* ========================================================================= */ | 3746 | /* ========================================================================= */ |
| 1457 | /* UVH_NODE_ID */ | 3747 | /* UVH_NODE_ID */ |
| 1458 | /* ========================================================================= */ | 3748 | /* ========================================================================= */ |
| 1459 | #define UVH_NODE_ID 0x0UL | 3749 | #define UVH_NODE_ID 0x0UL |
| 3750 | #define UV1H_NODE_ID 0x0UL | ||
| 3751 | #define UV2H_NODE_ID 0x0UL | ||
| 3752 | #define UV3H_NODE_ID 0x0UL | ||
| 1460 | 3753 | ||
| 1461 | #define UVH_NODE_ID_FORCE1_SHFT 0 | 3754 | #define UVH_NODE_ID_FORCE1_SHFT 0 |
| 1462 | #define UVH_NODE_ID_MANUFACTURER_SHFT 1 | 3755 | #define UVH_NODE_ID_MANUFACTURER_SHFT 1 |
| @@ -1484,6 +3777,21 @@ union uvh_lb_bau_sb_descriptor_base_u { | |||
| 1484 | #define UV1H_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL | 3777 | #define UV1H_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL |
| 1485 | #define UV1H_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL | 3778 | #define UV1H_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL |
| 1486 | 3779 | ||
| 3780 | #define UVXH_NODE_ID_FORCE1_SHFT 0 | ||
| 3781 | #define UVXH_NODE_ID_MANUFACTURER_SHFT 1 | ||
| 3782 | #define UVXH_NODE_ID_PART_NUMBER_SHFT 12 | ||
| 3783 | #define UVXH_NODE_ID_REVISION_SHFT 28 | ||
| 3784 | #define UVXH_NODE_ID_NODE_ID_SHFT 32 | ||
| 3785 | #define UVXH_NODE_ID_NODES_PER_BIT_SHFT 50 | ||
| 3786 | #define UVXH_NODE_ID_NI_PORT_SHFT 57 | ||
| 3787 | #define UVXH_NODE_ID_FORCE1_MASK 0x0000000000000001UL | ||
| 3788 | #define UVXH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL | ||
| 3789 | #define UVXH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL | ||
| 3790 | #define UVXH_NODE_ID_REVISION_MASK 0x00000000f0000000UL | ||
| 3791 | #define UVXH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL | ||
| 3792 | #define UVXH_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL | ||
| 3793 | #define UVXH_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL | ||
| 3794 | |||
| 1487 | #define UV2H_NODE_ID_FORCE1_SHFT 0 | 3795 | #define UV2H_NODE_ID_FORCE1_SHFT 0 |
| 1488 | #define UV2H_NODE_ID_MANUFACTURER_SHFT 1 | 3796 | #define UV2H_NODE_ID_MANUFACTURER_SHFT 1 |
| 1489 | #define UV2H_NODE_ID_PART_NUMBER_SHFT 12 | 3797 | #define UV2H_NODE_ID_PART_NUMBER_SHFT 12 |
| @@ -1499,6 +3807,25 @@ union uvh_lb_bau_sb_descriptor_base_u { | |||
| 1499 | #define UV2H_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL | 3807 | #define UV2H_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL |
| 1500 | #define UV2H_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL | 3808 | #define UV2H_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL |
| 1501 | 3809 | ||
| 3810 | #define UV3H_NODE_ID_FORCE1_SHFT 0 | ||
| 3811 | #define UV3H_NODE_ID_MANUFACTURER_SHFT 1 | ||
| 3812 | #define UV3H_NODE_ID_PART_NUMBER_SHFT 12 | ||
| 3813 | #define UV3H_NODE_ID_REVISION_SHFT 28 | ||
| 3814 | #define UV3H_NODE_ID_NODE_ID_SHFT 32 | ||
| 3815 | #define UV3H_NODE_ID_ROUTER_SELECT_SHFT 48 | ||
| 3816 | #define UV3H_NODE_ID_RESERVED_2_SHFT 49 | ||
| 3817 | #define UV3H_NODE_ID_NODES_PER_BIT_SHFT 50 | ||
| 3818 | #define UV3H_NODE_ID_NI_PORT_SHFT 57 | ||
| 3819 | #define UV3H_NODE_ID_FORCE1_MASK 0x0000000000000001UL | ||
| 3820 | #define UV3H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL | ||
| 3821 | #define UV3H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL | ||
| 3822 | #define UV3H_NODE_ID_REVISION_MASK 0x00000000f0000000UL | ||
| 3823 | #define UV3H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL | ||
| 3824 | #define UV3H_NODE_ID_ROUTER_SELECT_MASK 0x0001000000000000UL | ||
| 3825 | #define UV3H_NODE_ID_RESERVED_2_MASK 0x0002000000000000UL | ||
| 3826 | #define UV3H_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL | ||
| 3827 | #define UV3H_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL | ||
| 3828 | |||
| 1502 | union uvh_node_id_u { | 3829 | union uvh_node_id_u { |
| 1503 | unsigned long v; | 3830 | unsigned long v; |
| 1504 | struct uvh_node_id_s { | 3831 | struct uvh_node_id_s { |
| @@ -1521,6 +3848,17 @@ union uvh_node_id_u { | |||
| 1521 | unsigned long ni_port:4; /* RO */ | 3848 | unsigned long ni_port:4; /* RO */ |
| 1522 | unsigned long rsvd_60_63:4; | 3849 | unsigned long rsvd_60_63:4; |
| 1523 | } s1; | 3850 | } s1; |
| 3851 | struct uvxh_node_id_s { | ||
| 3852 | unsigned long force1:1; /* RO */ | ||
| 3853 | unsigned long manufacturer:11; /* RO */ | ||
| 3854 | unsigned long part_number:16; /* RO */ | ||
| 3855 | unsigned long revision:4; /* RO */ | ||
| 3856 | unsigned long node_id:15; /* RW */ | ||
| 3857 | unsigned long rsvd_47_49:3; | ||
| 3858 | unsigned long nodes_per_bit:7; /* RO */ | ||
| 3859 | unsigned long ni_port:5; /* RO */ | ||
| 3860 | unsigned long rsvd_62_63:2; | ||
| 3861 | } sx; | ||
| 1524 | struct uv2h_node_id_s { | 3862 | struct uv2h_node_id_s { |
| 1525 | unsigned long force1:1; /* RO */ | 3863 | unsigned long force1:1; /* RO */ |
| 1526 | unsigned long manufacturer:11; /* RO */ | 3864 | unsigned long manufacturer:11; /* RO */ |
| @@ -1532,28 +3870,74 @@ union uvh_node_id_u { | |||
| 1532 | unsigned long ni_port:5; /* RO */ | 3870 | unsigned long ni_port:5; /* RO */ |
| 1533 | unsigned long rsvd_62_63:2; | 3871 | unsigned long rsvd_62_63:2; |
| 1534 | } s2; | 3872 | } s2; |
| 3873 | struct uv3h_node_id_s { | ||
| 3874 | unsigned long force1:1; /* RO */ | ||
| 3875 | unsigned long manufacturer:11; /* RO */ | ||
| 3876 | unsigned long part_number:16; /* RO */ | ||
| 3877 | unsigned long revision:4; /* RO */ | ||
| 3878 | unsigned long node_id:15; /* RW */ | ||
| 3879 | unsigned long rsvd_47:1; | ||
| 3880 | unsigned long router_select:1; /* RO */ | ||
| 3881 | unsigned long rsvd_49:1; | ||
| 3882 | unsigned long nodes_per_bit:7; /* RO */ | ||
| 3883 | unsigned long ni_port:5; /* RO */ | ||
| 3884 | unsigned long rsvd_62_63:2; | ||
| 3885 | } s3; | ||
| 1535 | }; | 3886 | }; |
| 1536 | 3887 | ||
| 1537 | /* ========================================================================= */ | 3888 | /* ========================================================================= */ |
| 1538 | /* UVH_NODE_PRESENT_TABLE */ | 3889 | /* UVH_NODE_PRESENT_TABLE */ |
| 1539 | /* ========================================================================= */ | 3890 | /* ========================================================================= */ |
| 1540 | #define UVH_NODE_PRESENT_TABLE 0x1400UL | 3891 | #define UVH_NODE_PRESENT_TABLE 0x1400UL |
| 1541 | #define UVH_NODE_PRESENT_TABLE_DEPTH 16 | 3892 | #define UV1H_NODE_PRESENT_TABLE 0x1400UL |
| 3893 | #define UV2H_NODE_PRESENT_TABLE 0x1400UL | ||
| 3894 | #define UV3H_NODE_PRESENT_TABLE 0x1400UL | ||
| 3895 | #define UVH_NODE_PRESENT_TABLE_DEPTH 16 | ||
| 3896 | #define UV1H_NODE_PRESENT_TABLE_DEPTH 0x1400UL | ||
| 3897 | #define UV2H_NODE_PRESENT_TABLE_DEPTH 0x1400UL | ||
| 3898 | #define UV3H_NODE_PRESENT_TABLE_DEPTH 0x1400UL | ||
| 1542 | 3899 | ||
| 1543 | #define UVH_NODE_PRESENT_TABLE_NODES_SHFT 0 | 3900 | #define UVH_NODE_PRESENT_TABLE_NODES_SHFT 0 |
| 1544 | #define UVH_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL | 3901 | #define UVH_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL |
| 1545 | 3902 | ||
| 3903 | #define UV1H_NODE_PRESENT_TABLE_NODES_SHFT 0 | ||
| 3904 | #define UV1H_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL | ||
| 3905 | |||
| 3906 | #define UVXH_NODE_PRESENT_TABLE_NODES_SHFT 0 | ||
| 3907 | #define UVXH_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL | ||
| 3908 | |||
| 3909 | #define UV2H_NODE_PRESENT_TABLE_NODES_SHFT 0 | ||
| 3910 | #define UV2H_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL | ||
| 3911 | |||
| 3912 | #define UV3H_NODE_PRESENT_TABLE_NODES_SHFT 0 | ||
| 3913 | #define UV3H_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL | ||
| 3914 | |||
| 1546 | union uvh_node_present_table_u { | 3915 | union uvh_node_present_table_u { |
| 1547 | unsigned long v; | 3916 | unsigned long v; |
| 1548 | struct uvh_node_present_table_s { | 3917 | struct uvh_node_present_table_s { |
| 1549 | unsigned long nodes:64; /* RW */ | 3918 | unsigned long nodes:64; /* RW */ |
| 1550 | } s; | 3919 | } s; |
| 3920 | struct uv1h_node_present_table_s { | ||
| 3921 | unsigned long nodes:64; /* RW */ | ||
| 3922 | } s1; | ||
| 3923 | struct uvxh_node_present_table_s { | ||
| 3924 | unsigned long nodes:64; /* RW */ | ||
| 3925 | } sx; | ||
| 3926 | struct uv2h_node_present_table_s { | ||
| 3927 | unsigned long nodes:64; /* RW */ | ||
| 3928 | } s2; | ||
| 3929 | struct uv3h_node_present_table_s { | ||
| 3930 | unsigned long nodes:64; /* RW */ | ||
| 3931 | } s3; | ||
| 1551 | }; | 3932 | }; |
| 1552 | 3933 | ||
| 1553 | /* ========================================================================= */ | 3934 | /* ========================================================================= */ |
| 1554 | /* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR */ | 3935 | /* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR */ |
| 1555 | /* ========================================================================= */ | 3936 | /* ========================================================================= */ |
| 1556 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL | 3937 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL |
| 3938 | #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL | ||
| 3939 | #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL | ||
| 3940 | #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL | ||
| 1557 | 3941 | ||
| 1558 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24 | 3942 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24 |
| 1559 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48 | 3943 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48 |
| @@ -1562,6 +3946,34 @@ union uvh_node_present_table_u { | |||
| 1562 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL | 3946 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL |
| 1563 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL | 3947 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL |
| 1564 | 3948 | ||
| 3949 | #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24 | ||
| 3950 | #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48 | ||
| 3951 | #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63 | ||
| 3952 | #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL | ||
| 3953 | #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL | ||
| 3954 | #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL | ||
| 3955 | |||
| 3956 | #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24 | ||
| 3957 | #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48 | ||
| 3958 | #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63 | ||
| 3959 | #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL | ||
| 3960 | #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL | ||
| 3961 | #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL | ||
| 3962 | |||
| 3963 | #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24 | ||
| 3964 | #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48 | ||
| 3965 | #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63 | ||
| 3966 | #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL | ||
| 3967 | #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL | ||
| 3968 | #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL | ||
| 3969 | |||
| 3970 | #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24 | ||
| 3971 | #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48 | ||
| 3972 | #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63 | ||
| 3973 | #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL | ||
| 3974 | #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL | ||
| 3975 | #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL | ||
| 3976 | |||
| 1565 | union uvh_rh_gam_alias210_overlay_config_0_mmr_u { | 3977 | union uvh_rh_gam_alias210_overlay_config_0_mmr_u { |
| 1566 | unsigned long v; | 3978 | unsigned long v; |
| 1567 | struct uvh_rh_gam_alias210_overlay_config_0_mmr_s { | 3979 | struct uvh_rh_gam_alias210_overlay_config_0_mmr_s { |
| @@ -1572,12 +3984,47 @@ union uvh_rh_gam_alias210_overlay_config_0_mmr_u { | |||
| 1572 | unsigned long rsvd_53_62:10; | 3984 | unsigned long rsvd_53_62:10; |
| 1573 | unsigned long enable:1; /* RW */ | 3985 | unsigned long enable:1; /* RW */ |
| 1574 | } s; | 3986 | } s; |
| 3987 | struct uv1h_rh_gam_alias210_overlay_config_0_mmr_s { | ||
| 3988 | unsigned long rsvd_0_23:24; | ||
| 3989 | unsigned long base:8; /* RW */ | ||
| 3990 | unsigned long rsvd_32_47:16; | ||
| 3991 | unsigned long m_alias:5; /* RW */ | ||
| 3992 | unsigned long rsvd_53_62:10; | ||
| 3993 | unsigned long enable:1; /* RW */ | ||
| 3994 | } s1; | ||
| 3995 | struct uvxh_rh_gam_alias210_overlay_config_0_mmr_s { | ||
| 3996 | unsigned long rsvd_0_23:24; | ||
| 3997 | unsigned long base:8; /* RW */ | ||
| 3998 | unsigned long rsvd_32_47:16; | ||
| 3999 | unsigned long m_alias:5; /* RW */ | ||
| 4000 | unsigned long rsvd_53_62:10; | ||
| 4001 | unsigned long enable:1; /* RW */ | ||
| 4002 | } sx; | ||
| 4003 | struct uv2h_rh_gam_alias210_overlay_config_0_mmr_s { | ||
| 4004 | unsigned long rsvd_0_23:24; | ||
| 4005 | unsigned long base:8; /* RW */ | ||
| 4006 | unsigned long rsvd_32_47:16; | ||
| 4007 | unsigned long m_alias:5; /* RW */ | ||
| 4008 | unsigned long rsvd_53_62:10; | ||
| 4009 | unsigned long enable:1; /* RW */ | ||
| 4010 | } s2; | ||
| 4011 | struct uv3h_rh_gam_alias210_overlay_config_0_mmr_s { | ||
| 4012 | unsigned long rsvd_0_23:24; | ||
| 4013 | unsigned long base:8; /* RW */ | ||
| 4014 | unsigned long rsvd_32_47:16; | ||
| 4015 | unsigned long m_alias:5; /* RW */ | ||
| 4016 | unsigned long rsvd_53_62:10; | ||
| 4017 | unsigned long enable:1; /* RW */ | ||
| 4018 | } s3; | ||
| 1575 | }; | 4019 | }; |
| 1576 | 4020 | ||
| 1577 | /* ========================================================================= */ | 4021 | /* ========================================================================= */ |
| 1578 | /* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR */ | 4022 | /* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR */ |
| 1579 | /* ========================================================================= */ | 4023 | /* ========================================================================= */ |
| 1580 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL | 4024 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL |
| 4025 | #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL | ||
| 4026 | #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL | ||
| 4027 | #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL | ||
| 1581 | 4028 | ||
| 1582 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24 | 4029 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24 |
| 1583 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48 | 4030 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48 |
| @@ -1586,6 +4033,34 @@ union uvh_rh_gam_alias210_overlay_config_0_mmr_u { | |||
| 1586 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL | 4033 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL |
| 1587 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL | 4034 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL |
| 1588 | 4035 | ||
| 4036 | #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24 | ||
| 4037 | #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48 | ||
| 4038 | #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63 | ||
| 4039 | #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL | ||
| 4040 | #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL | ||
| 4041 | #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL | ||
| 4042 | |||
| 4043 | #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24 | ||
| 4044 | #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48 | ||
| 4045 | #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63 | ||
| 4046 | #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL | ||
| 4047 | #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL | ||
| 4048 | #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL | ||
| 4049 | |||
| 4050 | #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24 | ||
| 4051 | #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48 | ||
| 4052 | #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63 | ||
| 4053 | #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL | ||
| 4054 | #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL | ||
| 4055 | #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL | ||
| 4056 | |||
| 4057 | #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24 | ||
| 4058 | #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48 | ||
| 4059 | #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63 | ||
| 4060 | #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL | ||
| 4061 | #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL | ||
| 4062 | #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL | ||
| 4063 | |||
| 1589 | union uvh_rh_gam_alias210_overlay_config_1_mmr_u { | 4064 | union uvh_rh_gam_alias210_overlay_config_1_mmr_u { |
| 1590 | unsigned long v; | 4065 | unsigned long v; |
| 1591 | struct uvh_rh_gam_alias210_overlay_config_1_mmr_s { | 4066 | struct uvh_rh_gam_alias210_overlay_config_1_mmr_s { |
| @@ -1596,12 +4071,47 @@ union uvh_rh_gam_alias210_overlay_config_1_mmr_u { | |||
| 1596 | unsigned long rsvd_53_62:10; | 4071 | unsigned long rsvd_53_62:10; |
| 1597 | unsigned long enable:1; /* RW */ | 4072 | unsigned long enable:1; /* RW */ |
| 1598 | } s; | 4073 | } s; |
| 4074 | struct uv1h_rh_gam_alias210_overlay_config_1_mmr_s { | ||
| 4075 | unsigned long rsvd_0_23:24; | ||
| 4076 | unsigned long base:8; /* RW */ | ||
| 4077 | unsigned long rsvd_32_47:16; | ||
| 4078 | unsigned long m_alias:5; /* RW */ | ||
| 4079 | unsigned long rsvd_53_62:10; | ||
| 4080 | unsigned long enable:1; /* RW */ | ||
| 4081 | } s1; | ||
| 4082 | struct uvxh_rh_gam_alias210_overlay_config_1_mmr_s { | ||
| 4083 | unsigned long rsvd_0_23:24; | ||
| 4084 | unsigned long base:8; /* RW */ | ||
| 4085 | unsigned long rsvd_32_47:16; | ||
| 4086 | unsigned long m_alias:5; /* RW */ | ||
| 4087 | unsigned long rsvd_53_62:10; | ||
| 4088 | unsigned long enable:1; /* RW */ | ||
| 4089 | } sx; | ||
| 4090 | struct uv2h_rh_gam_alias210_overlay_config_1_mmr_s { | ||
| 4091 | unsigned long rsvd_0_23:24; | ||
| 4092 | unsigned long base:8; /* RW */ | ||
| 4093 | unsigned long rsvd_32_47:16; | ||
| 4094 | unsigned long m_alias:5; /* RW */ | ||
| 4095 | unsigned long rsvd_53_62:10; | ||
| 4096 | unsigned long enable:1; /* RW */ | ||
| 4097 | } s2; | ||
| 4098 | struct uv3h_rh_gam_alias210_overlay_config_1_mmr_s { | ||
| 4099 | unsigned long rsvd_0_23:24; | ||
| 4100 | unsigned long base:8; /* RW */ | ||
| 4101 | unsigned long rsvd_32_47:16; | ||
| 4102 | unsigned long m_alias:5; /* RW */ | ||
| 4103 | unsigned long rsvd_53_62:10; | ||
| 4104 | unsigned long enable:1; /* RW */ | ||
| 4105 | } s3; | ||
| 1599 | }; | 4106 | }; |
| 1600 | 4107 | ||
| 1601 | /* ========================================================================= */ | 4108 | /* ========================================================================= */ |
| 1602 | /* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR */ | 4109 | /* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR */ |
| 1603 | /* ========================================================================= */ | 4110 | /* ========================================================================= */ |
| 1604 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL | 4111 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL |
| 4112 | #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL | ||
| 4113 | #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL | ||
| 4114 | #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL | ||
| 1605 | 4115 | ||
| 1606 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24 | 4116 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24 |
| 1607 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48 | 4117 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48 |
| @@ -1610,6 +4120,34 @@ union uvh_rh_gam_alias210_overlay_config_1_mmr_u { | |||
| 1610 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL | 4120 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL |
| 1611 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL | 4121 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL |
| 1612 | 4122 | ||
| 4123 | #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24 | ||
| 4124 | #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48 | ||
| 4125 | #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63 | ||
| 4126 | #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL | ||
| 4127 | #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL | ||
| 4128 | #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL | ||
| 4129 | |||
| 4130 | #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24 | ||
| 4131 | #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48 | ||
| 4132 | #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63 | ||
| 4133 | #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL | ||
| 4134 | #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL | ||
| 4135 | #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL | ||
| 4136 | |||
| 4137 | #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24 | ||
| 4138 | #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48 | ||
| 4139 | #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63 | ||
| 4140 | #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL | ||
| 4141 | #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL | ||
| 4142 | #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL | ||
| 4143 | |||
| 4144 | #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24 | ||
| 4145 | #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48 | ||
| 4146 | #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63 | ||
| 4147 | #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL | ||
| 4148 | #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL | ||
| 4149 | #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL | ||
| 4150 | |||
| 1613 | union uvh_rh_gam_alias210_overlay_config_2_mmr_u { | 4151 | union uvh_rh_gam_alias210_overlay_config_2_mmr_u { |
| 1614 | unsigned long v; | 4152 | unsigned long v; |
| 1615 | struct uvh_rh_gam_alias210_overlay_config_2_mmr_s { | 4153 | struct uvh_rh_gam_alias210_overlay_config_2_mmr_s { |
| @@ -1620,16 +4158,63 @@ union uvh_rh_gam_alias210_overlay_config_2_mmr_u { | |||
| 1620 | unsigned long rsvd_53_62:10; | 4158 | unsigned long rsvd_53_62:10; |
| 1621 | unsigned long enable:1; /* RW */ | 4159 | unsigned long enable:1; /* RW */ |
| 1622 | } s; | 4160 | } s; |
| 4161 | struct uv1h_rh_gam_alias210_overlay_config_2_mmr_s { | ||
| 4162 | unsigned long rsvd_0_23:24; | ||
| 4163 | unsigned long base:8; /* RW */ | ||
| 4164 | unsigned long rsvd_32_47:16; | ||
| 4165 | unsigned long m_alias:5; /* RW */ | ||
| 4166 | unsigned long rsvd_53_62:10; | ||
| 4167 | unsigned long enable:1; /* RW */ | ||
| 4168 | } s1; | ||
| 4169 | struct uvxh_rh_gam_alias210_overlay_config_2_mmr_s { | ||
| 4170 | unsigned long rsvd_0_23:24; | ||
| 4171 | unsigned long base:8; /* RW */ | ||
| 4172 | unsigned long rsvd_32_47:16; | ||
| 4173 | unsigned long m_alias:5; /* RW */ | ||
| 4174 | unsigned long rsvd_53_62:10; | ||
| 4175 | unsigned long enable:1; /* RW */ | ||
| 4176 | } sx; | ||
| 4177 | struct uv2h_rh_gam_alias210_overlay_config_2_mmr_s { | ||
| 4178 | unsigned long rsvd_0_23:24; | ||
| 4179 | unsigned long base:8; /* RW */ | ||
| 4180 | unsigned long rsvd_32_47:16; | ||
| 4181 | unsigned long m_alias:5; /* RW */ | ||
| 4182 | unsigned long rsvd_53_62:10; | ||
| 4183 | unsigned long enable:1; /* RW */ | ||
| 4184 | } s2; | ||
| 4185 | struct uv3h_rh_gam_alias210_overlay_config_2_mmr_s { | ||
| 4186 | unsigned long rsvd_0_23:24; | ||
| 4187 | unsigned long base:8; /* RW */ | ||
| 4188 | unsigned long rsvd_32_47:16; | ||
| 4189 | unsigned long m_alias:5; /* RW */ | ||
| 4190 | unsigned long rsvd_53_62:10; | ||
| 4191 | unsigned long enable:1; /* RW */ | ||
| 4192 | } s3; | ||
| 1623 | }; | 4193 | }; |
| 1624 | 4194 | ||
| 1625 | /* ========================================================================= */ | 4195 | /* ========================================================================= */ |
| 1626 | /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */ | 4196 | /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */ |
| 1627 | /* ========================================================================= */ | 4197 | /* ========================================================================= */ |
| 1628 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL | 4198 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL |
| 4199 | #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL | ||
| 4200 | #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL | ||
| 4201 | #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL | ||
| 1629 | 4202 | ||
| 1630 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 | 4203 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 |
| 1631 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL | 4204 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL |
| 1632 | 4205 | ||
| 4206 | #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 | ||
| 4207 | #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL | ||
| 4208 | |||
| 4209 | #define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 | ||
| 4210 | #define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL | ||
| 4211 | |||
| 4212 | #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 | ||
| 4213 | #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL | ||
| 4214 | |||
| 4215 | #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 | ||
| 4216 | #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL | ||
| 4217 | |||
| 1633 | union uvh_rh_gam_alias210_redirect_config_0_mmr_u { | 4218 | union uvh_rh_gam_alias210_redirect_config_0_mmr_u { |
| 1634 | unsigned long v; | 4219 | unsigned long v; |
| 1635 | struct uvh_rh_gam_alias210_redirect_config_0_mmr_s { | 4220 | struct uvh_rh_gam_alias210_redirect_config_0_mmr_s { |
| @@ -1637,16 +4222,51 @@ union uvh_rh_gam_alias210_redirect_config_0_mmr_u { | |||
| 1637 | unsigned long dest_base:22; /* RW */ | 4222 | unsigned long dest_base:22; /* RW */ |
| 1638 | unsigned long rsvd_46_63:18; | 4223 | unsigned long rsvd_46_63:18; |
| 1639 | } s; | 4224 | } s; |
| 4225 | struct uv1h_rh_gam_alias210_redirect_config_0_mmr_s { | ||
| 4226 | unsigned long rsvd_0_23:24; | ||
| 4227 | unsigned long dest_base:22; /* RW */ | ||
| 4228 | unsigned long rsvd_46_63:18; | ||
| 4229 | } s1; | ||
| 4230 | struct uvxh_rh_gam_alias210_redirect_config_0_mmr_s { | ||
| 4231 | unsigned long rsvd_0_23:24; | ||
| 4232 | unsigned long dest_base:22; /* RW */ | ||
| 4233 | unsigned long rsvd_46_63:18; | ||
| 4234 | } sx; | ||
| 4235 | struct uv2h_rh_gam_alias210_redirect_config_0_mmr_s { | ||
| 4236 | unsigned long rsvd_0_23:24; | ||
| 4237 | unsigned long dest_base:22; /* RW */ | ||
| 4238 | unsigned long rsvd_46_63:18; | ||
| 4239 | } s2; | ||
| 4240 | struct uv3h_rh_gam_alias210_redirect_config_0_mmr_s { | ||
| 4241 | unsigned long rsvd_0_23:24; | ||
| 4242 | unsigned long dest_base:22; /* RW */ | ||
| 4243 | unsigned long rsvd_46_63:18; | ||
| 4244 | } s3; | ||
| 1640 | }; | 4245 | }; |
| 1641 | 4246 | ||
| 1642 | /* ========================================================================= */ | 4247 | /* ========================================================================= */ |
| 1643 | /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */ | 4248 | /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */ |
| 1644 | /* ========================================================================= */ | 4249 | /* ========================================================================= */ |
| 1645 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL | 4250 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL |
| 4251 | #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL | ||
| 4252 | #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL | ||
| 4253 | #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL | ||
| 1646 | 4254 | ||
| 1647 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 | 4255 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 |
| 1648 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL | 4256 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL |
| 1649 | 4257 | ||
| 4258 | #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 | ||
| 4259 | #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL | ||
| 4260 | |||
| 4261 | #define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 | ||
| 4262 | #define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL | ||
| 4263 | |||
| 4264 | #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 | ||
| 4265 | #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL | ||
| 4266 | |||
| 4267 | #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 | ||
| 4268 | #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL | ||
| 4269 | |||
| 1650 | union uvh_rh_gam_alias210_redirect_config_1_mmr_u { | 4270 | union uvh_rh_gam_alias210_redirect_config_1_mmr_u { |
| 1651 | unsigned long v; | 4271 | unsigned long v; |
| 1652 | struct uvh_rh_gam_alias210_redirect_config_1_mmr_s { | 4272 | struct uvh_rh_gam_alias210_redirect_config_1_mmr_s { |
| @@ -1654,16 +4274,51 @@ union uvh_rh_gam_alias210_redirect_config_1_mmr_u { | |||
| 1654 | unsigned long dest_base:22; /* RW */ | 4274 | unsigned long dest_base:22; /* RW */ |
| 1655 | unsigned long rsvd_46_63:18; | 4275 | unsigned long rsvd_46_63:18; |
| 1656 | } s; | 4276 | } s; |
| 4277 | struct uv1h_rh_gam_alias210_redirect_config_1_mmr_s { | ||
| 4278 | unsigned long rsvd_0_23:24; | ||
| 4279 | unsigned long dest_base:22; /* RW */ | ||
| 4280 | unsigned long rsvd_46_63:18; | ||
| 4281 | } s1; | ||
| 4282 | struct uvxh_rh_gam_alias210_redirect_config_1_mmr_s { | ||
| 4283 | unsigned long rsvd_0_23:24; | ||
| 4284 | unsigned long dest_base:22; /* RW */ | ||
| 4285 | unsigned long rsvd_46_63:18; | ||
| 4286 | } sx; | ||
| 4287 | struct uv2h_rh_gam_alias210_redirect_config_1_mmr_s { | ||
| 4288 | unsigned long rsvd_0_23:24; | ||
| 4289 | unsigned long dest_base:22; /* RW */ | ||
| 4290 | unsigned long rsvd_46_63:18; | ||
| 4291 | } s2; | ||
| 4292 | struct uv3h_rh_gam_alias210_redirect_config_1_mmr_s { | ||
| 4293 | unsigned long rsvd_0_23:24; | ||
| 4294 | unsigned long dest_base:22; /* RW */ | ||
| 4295 | unsigned long rsvd_46_63:18; | ||
| 4296 | } s3; | ||
| 1657 | }; | 4297 | }; |
| 1658 | 4298 | ||
| 1659 | /* ========================================================================= */ | 4299 | /* ========================================================================= */ |
| 1660 | /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */ | 4300 | /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */ |
| 1661 | /* ========================================================================= */ | 4301 | /* ========================================================================= */ |
| 1662 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL | 4302 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL |
| 4303 | #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL | ||
| 4304 | #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL | ||
| 4305 | #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL | ||
| 1663 | 4306 | ||
| 1664 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 | 4307 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 |
| 1665 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL | 4308 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL |
| 1666 | 4309 | ||
| 4310 | #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 | ||
| 4311 | #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL | ||
| 4312 | |||
| 4313 | #define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 | ||
| 4314 | #define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL | ||
| 4315 | |||
| 4316 | #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 | ||
| 4317 | #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL | ||
| 4318 | |||
| 4319 | #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 | ||
| 4320 | #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL | ||
| 4321 | |||
| 1667 | union uvh_rh_gam_alias210_redirect_config_2_mmr_u { | 4322 | union uvh_rh_gam_alias210_redirect_config_2_mmr_u { |
| 1668 | unsigned long v; | 4323 | unsigned long v; |
| 1669 | struct uvh_rh_gam_alias210_redirect_config_2_mmr_s { | 4324 | struct uvh_rh_gam_alias210_redirect_config_2_mmr_s { |
| @@ -1671,12 +4326,35 @@ union uvh_rh_gam_alias210_redirect_config_2_mmr_u { | |||
| 1671 | unsigned long dest_base:22; /* RW */ | 4326 | unsigned long dest_base:22; /* RW */ |
| 1672 | unsigned long rsvd_46_63:18; | 4327 | unsigned long rsvd_46_63:18; |
| 1673 | } s; | 4328 | } s; |
| 4329 | struct uv1h_rh_gam_alias210_redirect_config_2_mmr_s { | ||
| 4330 | unsigned long rsvd_0_23:24; | ||
| 4331 | unsigned long dest_base:22; /* RW */ | ||
| 4332 | unsigned long rsvd_46_63:18; | ||
| 4333 | } s1; | ||
| 4334 | struct uvxh_rh_gam_alias210_redirect_config_2_mmr_s { | ||
| 4335 | unsigned long rsvd_0_23:24; | ||
| 4336 | unsigned long dest_base:22; /* RW */ | ||
| 4337 | unsigned long rsvd_46_63:18; | ||
| 4338 | } sx; | ||
| 4339 | struct uv2h_rh_gam_alias210_redirect_config_2_mmr_s { | ||
| 4340 | unsigned long rsvd_0_23:24; | ||
| 4341 | unsigned long dest_base:22; /* RW */ | ||
| 4342 | unsigned long rsvd_46_63:18; | ||
| 4343 | } s2; | ||
| 4344 | struct uv3h_rh_gam_alias210_redirect_config_2_mmr_s { | ||
| 4345 | unsigned long rsvd_0_23:24; | ||
| 4346 | unsigned long dest_base:22; /* RW */ | ||
| 4347 | unsigned long rsvd_46_63:18; | ||
| 4348 | } s3; | ||
| 1674 | }; | 4349 | }; |
| 1675 | 4350 | ||
| 1676 | /* ========================================================================= */ | 4351 | /* ========================================================================= */ |
| 1677 | /* UVH_RH_GAM_CONFIG_MMR */ | 4352 | /* UVH_RH_GAM_CONFIG_MMR */ |
| 1678 | /* ========================================================================= */ | 4353 | /* ========================================================================= */ |
| 1679 | #define UVH_RH_GAM_CONFIG_MMR 0x1600000UL | 4354 | #define UVH_RH_GAM_CONFIG_MMR 0x1600000UL |
| 4355 | #define UV1H_RH_GAM_CONFIG_MMR 0x1600000UL | ||
| 4356 | #define UV2H_RH_GAM_CONFIG_MMR 0x1600000UL | ||
| 4357 | #define UV3H_RH_GAM_CONFIG_MMR 0x1600000UL | ||
| 1680 | 4358 | ||
| 1681 | #define UVH_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 | 4359 | #define UVH_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 |
| 1682 | #define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 | 4360 | #define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 |
| @@ -1690,11 +4368,21 @@ union uvh_rh_gam_alias210_redirect_config_2_mmr_u { | |||
| 1690 | #define UV1H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL | 4368 | #define UV1H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL |
| 1691 | #define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK 0x0000000000001000UL | 4369 | #define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK 0x0000000000001000UL |
| 1692 | 4370 | ||
| 4371 | #define UVXH_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 | ||
| 4372 | #define UVXH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 | ||
| 4373 | #define UVXH_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL | ||
| 4374 | #define UVXH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL | ||
| 4375 | |||
| 1693 | #define UV2H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 | 4376 | #define UV2H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 |
| 1694 | #define UV2H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 | 4377 | #define UV2H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 |
| 1695 | #define UV2H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL | 4378 | #define UV2H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL |
| 1696 | #define UV2H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL | 4379 | #define UV2H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL |
| 1697 | 4380 | ||
| 4381 | #define UV3H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 | ||
| 4382 | #define UV3H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 | ||
| 4383 | #define UV3H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL | ||
| 4384 | #define UV3H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL | ||
| 4385 | |||
| 1698 | union uvh_rh_gam_config_mmr_u { | 4386 | union uvh_rh_gam_config_mmr_u { |
| 1699 | unsigned long v; | 4387 | unsigned long v; |
| 1700 | struct uvh_rh_gam_config_mmr_s { | 4388 | struct uvh_rh_gam_config_mmr_s { |
| @@ -1709,20 +4397,37 @@ union uvh_rh_gam_config_mmr_u { | |||
| 1709 | unsigned long mmiol_cfg:1; /* RW */ | 4397 | unsigned long mmiol_cfg:1; /* RW */ |
| 1710 | unsigned long rsvd_13_63:51; | 4398 | unsigned long rsvd_13_63:51; |
| 1711 | } s1; | 4399 | } s1; |
| 4400 | struct uvxh_rh_gam_config_mmr_s { | ||
| 4401 | unsigned long m_skt:6; /* RW */ | ||
| 4402 | unsigned long n_skt:4; /* RW */ | ||
| 4403 | unsigned long rsvd_10_63:54; | ||
| 4404 | } sx; | ||
| 1712 | struct uv2h_rh_gam_config_mmr_s { | 4405 | struct uv2h_rh_gam_config_mmr_s { |
| 1713 | unsigned long m_skt:6; /* RW */ | 4406 | unsigned long m_skt:6; /* RW */ |
| 1714 | unsigned long n_skt:4; /* RW */ | 4407 | unsigned long n_skt:4; /* RW */ |
| 1715 | unsigned long rsvd_10_63:54; | 4408 | unsigned long rsvd_10_63:54; |
| 1716 | } s2; | 4409 | } s2; |
| 4410 | struct uv3h_rh_gam_config_mmr_s { | ||
| 4411 | unsigned long m_skt:6; /* RW */ | ||
| 4412 | unsigned long n_skt:4; /* RW */ | ||
| 4413 | unsigned long rsvd_10_63:54; | ||
| 4414 | } s3; | ||
| 1717 | }; | 4415 | }; |
| 1718 | 4416 | ||
| 1719 | /* ========================================================================= */ | 4417 | /* ========================================================================= */ |
| 1720 | /* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */ | 4418 | /* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */ |
| 1721 | /* ========================================================================= */ | 4419 | /* ========================================================================= */ |
| 1722 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL | 4420 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL |
| 4421 | #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL | ||
| 4422 | #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL | ||
| 4423 | #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL | ||
| 1723 | 4424 | ||
| 1724 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 | 4425 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 |
| 4426 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 | ||
| 4427 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 | ||
| 1725 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL | 4428 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL |
| 4429 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL | ||
| 4430 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL | ||
| 1726 | 4431 | ||
| 1727 | #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 | 4432 | #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 |
| 1728 | #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48 | 4433 | #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48 |
| @@ -1733,6 +4438,13 @@ union uvh_rh_gam_config_mmr_u { | |||
| 1733 | #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL | 4438 | #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL |
| 1734 | #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL | 4439 | #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL |
| 1735 | 4440 | ||
| 4441 | #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 | ||
| 4442 | #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 | ||
| 4443 | #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 | ||
| 4444 | #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL | ||
| 4445 | #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL | ||
| 4446 | #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL | ||
| 4447 | |||
| 1736 | #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 | 4448 | #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 |
| 1737 | #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 | 4449 | #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 |
| 1738 | #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 | 4450 | #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 |
| @@ -1740,12 +4452,23 @@ union uvh_rh_gam_config_mmr_u { | |||
| 1740 | #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL | 4452 | #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL |
| 1741 | #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL | 4453 | #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL |
| 1742 | 4454 | ||
| 4455 | #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 | ||
| 4456 | #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 | ||
| 4457 | #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_MODE_SHFT 62 | ||
| 4458 | #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 | ||
| 4459 | #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL | ||
| 4460 | #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL | ||
| 4461 | #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_MODE_MASK 0x4000000000000000UL | ||
| 4462 | #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL | ||
| 4463 | |||
| 1743 | union uvh_rh_gam_gru_overlay_config_mmr_u { | 4464 | union uvh_rh_gam_gru_overlay_config_mmr_u { |
| 1744 | unsigned long v; | 4465 | unsigned long v; |
| 1745 | struct uvh_rh_gam_gru_overlay_config_mmr_s { | 4466 | struct uvh_rh_gam_gru_overlay_config_mmr_s { |
| 1746 | unsigned long rsvd_0_27:28; | 4467 | unsigned long rsvd_0_27:28; |
| 1747 | unsigned long base:18; /* RW */ | 4468 | unsigned long base:18; /* RW */ |
| 1748 | unsigned long rsvd_46_62:17; | 4469 | unsigned long rsvd_46_51:6; |
| 4470 | unsigned long n_gru:4; /* RW */ | ||
| 4471 | unsigned long rsvd_56_62:7; | ||
| 1749 | unsigned long enable:1; /* RW */ | 4472 | unsigned long enable:1; /* RW */ |
| 1750 | } s; | 4473 | } s; |
| 1751 | struct uv1h_rh_gam_gru_overlay_config_mmr_s { | 4474 | struct uv1h_rh_gam_gru_overlay_config_mmr_s { |
| @@ -1758,6 +4481,14 @@ union uvh_rh_gam_gru_overlay_config_mmr_u { | |||
| 1758 | unsigned long rsvd_56_62:7; | 4481 | unsigned long rsvd_56_62:7; |
| 1759 | unsigned long enable:1; /* RW */ | 4482 | unsigned long enable:1; /* RW */ |
| 1760 | } s1; | 4483 | } s1; |
| 4484 | struct uvxh_rh_gam_gru_overlay_config_mmr_s { | ||
| 4485 | unsigned long rsvd_0_27:28; | ||
| 4486 | unsigned long base:18; /* RW */ | ||
| 4487 | unsigned long rsvd_46_51:6; | ||
| 4488 | unsigned long n_gru:4; /* RW */ | ||
| 4489 | unsigned long rsvd_56_62:7; | ||
| 4490 | unsigned long enable:1; /* RW */ | ||
| 4491 | } sx; | ||
| 1761 | struct uv2h_rh_gam_gru_overlay_config_mmr_s { | 4492 | struct uv2h_rh_gam_gru_overlay_config_mmr_s { |
| 1762 | unsigned long rsvd_0_27:28; | 4493 | unsigned long rsvd_0_27:28; |
| 1763 | unsigned long base:18; /* RW */ | 4494 | unsigned long base:18; /* RW */ |
| @@ -1766,12 +4497,25 @@ union uvh_rh_gam_gru_overlay_config_mmr_u { | |||
| 1766 | unsigned long rsvd_56_62:7; | 4497 | unsigned long rsvd_56_62:7; |
| 1767 | unsigned long enable:1; /* RW */ | 4498 | unsigned long enable:1; /* RW */ |
| 1768 | } s2; | 4499 | } s2; |
| 4500 | struct uv3h_rh_gam_gru_overlay_config_mmr_s { | ||
| 4501 | unsigned long rsvd_0_27:28; | ||
| 4502 | unsigned long base:18; /* RW */ | ||
| 4503 | unsigned long rsvd_46_51:6; | ||
| 4504 | unsigned long n_gru:4; /* RW */ | ||
| 4505 | unsigned long rsvd_56_61:6; | ||
| 4506 | unsigned long mode:1; /* RW */ | ||
| 4507 | unsigned long enable:1; /* RW */ | ||
| 4508 | } s3; | ||
| 1769 | }; | 4509 | }; |
| 1770 | 4510 | ||
| 1771 | /* ========================================================================= */ | 4511 | /* ========================================================================= */ |
| 1772 | /* UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR */ | 4512 | /* UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR */ |
| 1773 | /* ========================================================================= */ | 4513 | /* ========================================================================= */ |
| 1774 | #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL | 4514 | #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL |
| 4515 | #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL | ||
| 4516 | #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR \ | ||
| 4517 | (is_uv1_hub() ? UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR : \ | ||
| 4518 | UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR) | ||
| 1775 | 4519 | ||
| 1776 | #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30 | 4520 | #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30 |
| 1777 | #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46 | 4521 | #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46 |
| @@ -1814,10 +4558,15 @@ union uvh_rh_gam_mmioh_overlay_config_mmr_u { | |||
| 1814 | /* ========================================================================= */ | 4558 | /* ========================================================================= */ |
| 1815 | /* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */ | 4559 | /* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */ |
| 1816 | /* ========================================================================= */ | 4560 | /* ========================================================================= */ |
| 1817 | #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL | 4561 | #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL |
| 4562 | #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL | ||
| 4563 | #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL | ||
| 4564 | #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL | ||
| 1818 | 4565 | ||
| 1819 | #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 | 4566 | #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 |
| 4567 | #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 | ||
| 1820 | #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL | 4568 | #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL |
| 4569 | #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL | ||
| 1821 | 4570 | ||
| 1822 | #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 | 4571 | #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 |
| 1823 | #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46 | 4572 | #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46 |
| @@ -1826,11 +4575,21 @@ union uvh_rh_gam_mmioh_overlay_config_mmr_u { | |||
| 1826 | #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL | 4575 | #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL |
| 1827 | #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL | 4576 | #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL |
| 1828 | 4577 | ||
| 4578 | #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 | ||
| 4579 | #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 | ||
| 4580 | #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL | ||
| 4581 | #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL | ||
| 4582 | |||
| 1829 | #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 | 4583 | #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 |
| 1830 | #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 | 4584 | #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 |
| 1831 | #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL | 4585 | #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL |
| 1832 | #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL | 4586 | #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL |
| 1833 | 4587 | ||
| 4588 | #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 | ||
| 4589 | #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 | ||
| 4590 | #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL | ||
| 4591 | #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL | ||
| 4592 | |||
| 1834 | union uvh_rh_gam_mmr_overlay_config_mmr_u { | 4593 | union uvh_rh_gam_mmr_overlay_config_mmr_u { |
| 1835 | unsigned long v; | 4594 | unsigned long v; |
| 1836 | struct uvh_rh_gam_mmr_overlay_config_mmr_s { | 4595 | struct uvh_rh_gam_mmr_overlay_config_mmr_s { |
| @@ -1846,34 +4605,80 @@ union uvh_rh_gam_mmr_overlay_config_mmr_u { | |||
| 1846 | unsigned long rsvd_47_62:16; | 4605 | unsigned long rsvd_47_62:16; |
| 1847 | unsigned long enable:1; /* RW */ | 4606 | unsigned long enable:1; /* RW */ |
| 1848 | } s1; | 4607 | } s1; |
| 4608 | struct uvxh_rh_gam_mmr_overlay_config_mmr_s { | ||
| 4609 | unsigned long rsvd_0_25:26; | ||
| 4610 | unsigned long base:20; /* RW */ | ||
| 4611 | unsigned long rsvd_46_62:17; | ||
| 4612 | unsigned long enable:1; /* RW */ | ||
| 4613 | } sx; | ||
| 1849 | struct uv2h_rh_gam_mmr_overlay_config_mmr_s { | 4614 | struct uv2h_rh_gam_mmr_overlay_config_mmr_s { |
| 1850 | unsigned long rsvd_0_25:26; | 4615 | unsigned long rsvd_0_25:26; |
| 1851 | unsigned long base:20; /* RW */ | 4616 | unsigned long base:20; /* RW */ |
| 1852 | unsigned long rsvd_46_62:17; | 4617 | unsigned long rsvd_46_62:17; |
| 1853 | unsigned long enable:1; /* RW */ | 4618 | unsigned long enable:1; /* RW */ |
| 1854 | } s2; | 4619 | } s2; |
| 4620 | struct uv3h_rh_gam_mmr_overlay_config_mmr_s { | ||
| 4621 | unsigned long rsvd_0_25:26; | ||
| 4622 | unsigned long base:20; /* RW */ | ||
| 4623 | unsigned long rsvd_46_62:17; | ||
| 4624 | unsigned long enable:1; /* RW */ | ||
| 4625 | } s3; | ||
| 1855 | }; | 4626 | }; |
| 1856 | 4627 | ||
| 1857 | /* ========================================================================= */ | 4628 | /* ========================================================================= */ |
| 1858 | /* UVH_RTC */ | 4629 | /* UVH_RTC */ |
| 1859 | /* ========================================================================= */ | 4630 | /* ========================================================================= */ |
| 1860 | #define UVH_RTC 0x340000UL | 4631 | #define UVH_RTC 0x340000UL |
| 4632 | #define UV1H_RTC 0x340000UL | ||
| 4633 | #define UV2H_RTC 0x340000UL | ||
| 4634 | #define UV3H_RTC 0x340000UL | ||
| 1861 | 4635 | ||
| 1862 | #define UVH_RTC_REAL_TIME_CLOCK_SHFT 0 | 4636 | #define UVH_RTC_REAL_TIME_CLOCK_SHFT 0 |
| 1863 | #define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL | 4637 | #define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL |
| 1864 | 4638 | ||
| 4639 | #define UV1H_RTC_REAL_TIME_CLOCK_SHFT 0 | ||
| 4640 | #define UV1H_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL | ||
| 4641 | |||
| 4642 | #define UVXH_RTC_REAL_TIME_CLOCK_SHFT 0 | ||
| 4643 | #define UVXH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL | ||
| 4644 | |||
| 4645 | #define UV2H_RTC_REAL_TIME_CLOCK_SHFT 0 | ||
| 4646 | #define UV2H_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL | ||
| 4647 | |||
| 4648 | #define UV3H_RTC_REAL_TIME_CLOCK_SHFT 0 | ||
| 4649 | #define UV3H_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL | ||
| 4650 | |||
| 1865 | union uvh_rtc_u { | 4651 | union uvh_rtc_u { |
| 1866 | unsigned long v; | 4652 | unsigned long v; |
| 1867 | struct uvh_rtc_s { | 4653 | struct uvh_rtc_s { |
| 1868 | unsigned long real_time_clock:56; /* RW */ | 4654 | unsigned long real_time_clock:56; /* RW */ |
| 1869 | unsigned long rsvd_56_63:8; | 4655 | unsigned long rsvd_56_63:8; |
| 1870 | } s; | 4656 | } s; |
| 4657 | struct uv1h_rtc_s { | ||
| 4658 | unsigned long real_time_clock:56; /* RW */ | ||
| 4659 | unsigned long rsvd_56_63:8; | ||
| 4660 | } s1; | ||
| 4661 | struct uvxh_rtc_s { | ||
| 4662 | unsigned long real_time_clock:56; /* RW */ | ||
| 4663 | unsigned long rsvd_56_63:8; | ||
| 4664 | } sx; | ||
| 4665 | struct uv2h_rtc_s { | ||
| 4666 | unsigned long real_time_clock:56; /* RW */ | ||
| 4667 | unsigned long rsvd_56_63:8; | ||
| 4668 | } s2; | ||
| 4669 | struct uv3h_rtc_s { | ||
| 4670 | unsigned long real_time_clock:56; /* RW */ | ||
| 4671 | unsigned long rsvd_56_63:8; | ||
| 4672 | } s3; | ||
| 1871 | }; | 4673 | }; |
| 1872 | 4674 | ||
| 1873 | /* ========================================================================= */ | 4675 | /* ========================================================================= */ |
| 1874 | /* UVH_RTC1_INT_CONFIG */ | 4676 | /* UVH_RTC1_INT_CONFIG */ |
| 1875 | /* ========================================================================= */ | 4677 | /* ========================================================================= */ |
| 1876 | #define UVH_RTC1_INT_CONFIG 0x615c0UL | 4678 | #define UVH_RTC1_INT_CONFIG 0x615c0UL |
| 4679 | #define UV1H_RTC1_INT_CONFIG 0x615c0UL | ||
| 4680 | #define UV2H_RTC1_INT_CONFIG 0x615c0UL | ||
| 4681 | #define UV3H_RTC1_INT_CONFIG 0x615c0UL | ||
| 1877 | 4682 | ||
| 1878 | #define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0 | 4683 | #define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0 |
| 1879 | #define UVH_RTC1_INT_CONFIG_DM_SHFT 8 | 4684 | #define UVH_RTC1_INT_CONFIG_DM_SHFT 8 |
| @@ -1892,6 +4697,74 @@ union uvh_rtc_u { | |||
| 1892 | #define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL | 4697 | #define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL |
| 1893 | #define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | 4698 | #define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL |
| 1894 | 4699 | ||
| 4700 | #define UV1H_RTC1_INT_CONFIG_VECTOR_SHFT 0 | ||
| 4701 | #define UV1H_RTC1_INT_CONFIG_DM_SHFT 8 | ||
| 4702 | #define UV1H_RTC1_INT_CONFIG_DESTMODE_SHFT 11 | ||
| 4703 | #define UV1H_RTC1_INT_CONFIG_STATUS_SHFT 12 | ||
| 4704 | #define UV1H_RTC1_INT_CONFIG_P_SHFT 13 | ||
| 4705 | #define UV1H_RTC1_INT_CONFIG_T_SHFT 15 | ||
| 4706 | #define UV1H_RTC1_INT_CONFIG_M_SHFT 16 | ||
| 4707 | #define UV1H_RTC1_INT_CONFIG_APIC_ID_SHFT 32 | ||
| 4708 | #define UV1H_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL | ||
| 4709 | #define UV1H_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL | ||
| 4710 | #define UV1H_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL | ||
| 4711 | #define UV1H_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL | ||
| 4712 | #define UV1H_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL | ||
| 4713 | #define UV1H_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL | ||
| 4714 | #define UV1H_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL | ||
| 4715 | #define UV1H_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | ||
| 4716 | |||
| 4717 | #define UVXH_RTC1_INT_CONFIG_VECTOR_SHFT 0 | ||
| 4718 | #define UVXH_RTC1_INT_CONFIG_DM_SHFT 8 | ||
| 4719 | #define UVXH_RTC1_INT_CONFIG_DESTMODE_SHFT 11 | ||
| 4720 | #define UVXH_RTC1_INT_CONFIG_STATUS_SHFT 12 | ||
| 4721 | #define UVXH_RTC1_INT_CONFIG_P_SHFT 13 | ||
| 4722 | #define UVXH_RTC1_INT_CONFIG_T_SHFT 15 | ||
| 4723 | #define UVXH_RTC1_INT_CONFIG_M_SHFT 16 | ||
| 4724 | #define UVXH_RTC1_INT_CONFIG_APIC_ID_SHFT 32 | ||
| 4725 | #define UVXH_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL | ||
| 4726 | #define UVXH_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL | ||
| 4727 | #define UVXH_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL | ||
| 4728 | #define UVXH_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL | ||
| 4729 | #define UVXH_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL | ||
| 4730 | #define UVXH_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL | ||
| 4731 | #define UVXH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL | ||
| 4732 | #define UVXH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | ||
| 4733 | |||
| 4734 | #define UV2H_RTC1_INT_CONFIG_VECTOR_SHFT 0 | ||
| 4735 | #define UV2H_RTC1_INT_CONFIG_DM_SHFT 8 | ||
| 4736 | #define UV2H_RTC1_INT_CONFIG_DESTMODE_SHFT 11 | ||
| 4737 | #define UV2H_RTC1_INT_CONFIG_STATUS_SHFT 12 | ||
| 4738 | #define UV2H_RTC1_INT_CONFIG_P_SHFT 13 | ||
| 4739 | #define UV2H_RTC1_INT_CONFIG_T_SHFT 15 | ||
| 4740 | #define UV2H_RTC1_INT_CONFIG_M_SHFT 16 | ||
| 4741 | #define UV2H_RTC1_INT_CONFIG_APIC_ID_SHFT 32 | ||
| 4742 | #define UV2H_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL | ||
| 4743 | #define UV2H_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL | ||
| 4744 | #define UV2H_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL | ||
| 4745 | #define UV2H_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL | ||
| 4746 | #define UV2H_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL | ||
| 4747 | #define UV2H_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL | ||
| 4748 | #define UV2H_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL | ||
| 4749 | #define UV2H_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | ||
| 4750 | |||
| 4751 | #define UV3H_RTC1_INT_CONFIG_VECTOR_SHFT 0 | ||
| 4752 | #define UV3H_RTC1_INT_CONFIG_DM_SHFT 8 | ||
| 4753 | #define UV3H_RTC1_INT_CONFIG_DESTMODE_SHFT 11 | ||
| 4754 | #define UV3H_RTC1_INT_CONFIG_STATUS_SHFT 12 | ||
| 4755 | #define UV3H_RTC1_INT_CONFIG_P_SHFT 13 | ||
| 4756 | #define UV3H_RTC1_INT_CONFIG_T_SHFT 15 | ||
| 4757 | #define UV3H_RTC1_INT_CONFIG_M_SHFT 16 | ||
| 4758 | #define UV3H_RTC1_INT_CONFIG_APIC_ID_SHFT 32 | ||
| 4759 | #define UV3H_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL | ||
| 4760 | #define UV3H_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL | ||
| 4761 | #define UV3H_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL | ||
| 4762 | #define UV3H_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL | ||
| 4763 | #define UV3H_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL | ||
| 4764 | #define UV3H_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL | ||
| 4765 | #define UV3H_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL | ||
| 4766 | #define UV3H_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | ||
| 4767 | |||
| 1895 | union uvh_rtc1_int_config_u { | 4768 | union uvh_rtc1_int_config_u { |
| 1896 | unsigned long v; | 4769 | unsigned long v; |
| 1897 | struct uvh_rtc1_int_config_s { | 4770 | struct uvh_rtc1_int_config_s { |
| @@ -1906,29 +4779,176 @@ union uvh_rtc1_int_config_u { | |||
| 1906 | unsigned long rsvd_17_31:15; | 4779 | unsigned long rsvd_17_31:15; |
| 1907 | unsigned long apic_id:32; /* RW */ | 4780 | unsigned long apic_id:32; /* RW */ |
| 1908 | } s; | 4781 | } s; |
| 4782 | struct uv1h_rtc1_int_config_s { | ||
| 4783 | unsigned long vector_:8; /* RW */ | ||
| 4784 | unsigned long dm:3; /* RW */ | ||
| 4785 | unsigned long destmode:1; /* RW */ | ||
| 4786 | unsigned long status:1; /* RO */ | ||
| 4787 | unsigned long p:1; /* RO */ | ||
| 4788 | unsigned long rsvd_14:1; | ||
| 4789 | unsigned long t:1; /* RO */ | ||
| 4790 | unsigned long m:1; /* RW */ | ||
| 4791 | unsigned long rsvd_17_31:15; | ||
| 4792 | unsigned long apic_id:32; /* RW */ | ||
| 4793 | } s1; | ||
| 4794 | struct uvxh_rtc1_int_config_s { | ||
| 4795 | unsigned long vector_:8; /* RW */ | ||
| 4796 | unsigned long dm:3; /* RW */ | ||
| 4797 | unsigned long destmode:1; /* RW */ | ||
| 4798 | unsigned long status:1; /* RO */ | ||
| 4799 | unsigned long p:1; /* RO */ | ||
| 4800 | unsigned long rsvd_14:1; | ||
| 4801 | unsigned long t:1; /* RO */ | ||
| 4802 | unsigned long m:1; /* RW */ | ||
| 4803 | unsigned long rsvd_17_31:15; | ||
| 4804 | unsigned long apic_id:32; /* RW */ | ||
| 4805 | } sx; | ||
| 4806 | struct uv2h_rtc1_int_config_s { | ||
| 4807 | unsigned long vector_:8; /* RW */ | ||
| 4808 | unsigned long dm:3; /* RW */ | ||
| 4809 | unsigned long destmode:1; /* RW */ | ||
| 4810 | unsigned long status:1; /* RO */ | ||
| 4811 | unsigned long p:1; /* RO */ | ||
| 4812 | unsigned long rsvd_14:1; | ||
| 4813 | unsigned long t:1; /* RO */ | ||
| 4814 | unsigned long m:1; /* RW */ | ||
| 4815 | unsigned long rsvd_17_31:15; | ||
| 4816 | unsigned long apic_id:32; /* RW */ | ||
| 4817 | } s2; | ||
| 4818 | struct uv3h_rtc1_int_config_s { | ||
| 4819 | unsigned long vector_:8; /* RW */ | ||
| 4820 | unsigned long dm:3; /* RW */ | ||
| 4821 | unsigned long destmode:1; /* RW */ | ||
| 4822 | unsigned long status:1; /* RO */ | ||
| 4823 | unsigned long p:1; /* RO */ | ||
| 4824 | unsigned long rsvd_14:1; | ||
| 4825 | unsigned long t:1; /* RO */ | ||
| 4826 | unsigned long m:1; /* RW */ | ||
| 4827 | unsigned long rsvd_17_31:15; | ||
| 4828 | unsigned long apic_id:32; /* RW */ | ||
| 4829 | } s3; | ||
| 1909 | }; | 4830 | }; |
| 1910 | 4831 | ||
| 1911 | /* ========================================================================= */ | 4832 | /* ========================================================================= */ |
| 1912 | /* UVH_SCRATCH5 */ | 4833 | /* UVH_SCRATCH5 */ |
| 1913 | /* ========================================================================= */ | 4834 | /* ========================================================================= */ |
| 1914 | #define UVH_SCRATCH5 0x2d0200UL | 4835 | #define UVH_SCRATCH5 0x2d0200UL |
| 1915 | #define UVH_SCRATCH5_32 0x778 | 4836 | #define UV1H_SCRATCH5 0x2d0200UL |
| 4837 | #define UV2H_SCRATCH5 0x2d0200UL | ||
| 4838 | #define UV3H_SCRATCH5 0x2d0200UL | ||
| 4839 | #define UVH_SCRATCH5_32 0x778 | ||
| 4840 | #define UV1H_SCRATCH5_32 0x2d0200UL | ||
| 4841 | #define UV2H_SCRATCH5_32 0x2d0200UL | ||
| 4842 | #define UV3H_SCRATCH5_32 0x2d0200UL | ||
| 1916 | 4843 | ||
| 1917 | #define UVH_SCRATCH5_SCRATCH5_SHFT 0 | 4844 | #define UVH_SCRATCH5_SCRATCH5_SHFT 0 |
| 1918 | #define UVH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL | 4845 | #define UVH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL |
| 1919 | 4846 | ||
| 4847 | #define UV1H_SCRATCH5_SCRATCH5_SHFT 0 | ||
| 4848 | #define UV1H_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL | ||
| 4849 | |||
| 4850 | #define UVXH_SCRATCH5_SCRATCH5_SHFT 0 | ||
| 4851 | #define UVXH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL | ||
| 4852 | |||
| 4853 | #define UV2H_SCRATCH5_SCRATCH5_SHFT 0 | ||
| 4854 | #define UV2H_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL | ||
| 4855 | |||
| 4856 | #define UV3H_SCRATCH5_SCRATCH5_SHFT 0 | ||
| 4857 | #define UV3H_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL | ||
| 4858 | |||
| 1920 | union uvh_scratch5_u { | 4859 | union uvh_scratch5_u { |
| 1921 | unsigned long v; | 4860 | unsigned long v; |
| 1922 | struct uvh_scratch5_s { | 4861 | struct uvh_scratch5_s { |
| 1923 | unsigned long scratch5:64; /* RW, W1CS */ | 4862 | unsigned long scratch5:64; /* RW, W1CS */ |
| 1924 | } s; | 4863 | } s; |
| 4864 | struct uv1h_scratch5_s { | ||
| 4865 | unsigned long scratch5:64; /* RW, W1CS */ | ||
| 4866 | } s1; | ||
| 4867 | struct uvxh_scratch5_s { | ||
| 4868 | unsigned long scratch5:64; /* RW */ | ||
| 4869 | } sx; | ||
| 4870 | struct uv2h_scratch5_s { | ||
| 4871 | unsigned long scratch5:64; /* RW */ | ||
| 4872 | } s2; | ||
| 4873 | struct uv3h_scratch5_s { | ||
| 4874 | unsigned long scratch5:64; /* RW */ | ||
| 4875 | } s3; | ||
| 1925 | }; | 4876 | }; |
| 1926 | 4877 | ||
| 1927 | /* ========================================================================= */ | 4878 | /* ========================================================================= */ |
| 1928 | /* UV2H_EVENT_OCCURRED2 */ | 4879 | /* UVXH_EVENT_OCCURRED2 */ |
| 1929 | /* ========================================================================= */ | 4880 | /* ========================================================================= */ |
| 1930 | #define UV2H_EVENT_OCCURRED2 0x70100UL | 4881 | #define UVXH_EVENT_OCCURRED2 0x70100UL |
| 1931 | #define UV2H_EVENT_OCCURRED2_32 0xb68 | 4882 | #define UV2H_EVENT_OCCURRED2 0x70100UL |
| 4883 | #define UV3H_EVENT_OCCURRED2 0x70100UL | ||
| 4884 | #define UVXH_EVENT_OCCURRED2_32 0xb68 | ||
| 4885 | #define UV2H_EVENT_OCCURRED2_32 0x70100UL | ||
| 4886 | #define UV3H_EVENT_OCCURRED2_32 0x70100UL | ||
| 4887 | |||
| 4888 | #define UVXH_EVENT_OCCURRED2_RTC_0_SHFT 0 | ||
| 4889 | #define UVXH_EVENT_OCCURRED2_RTC_1_SHFT 1 | ||
| 4890 | #define UVXH_EVENT_OCCURRED2_RTC_2_SHFT 2 | ||
| 4891 | #define UVXH_EVENT_OCCURRED2_RTC_3_SHFT 3 | ||
| 4892 | #define UVXH_EVENT_OCCURRED2_RTC_4_SHFT 4 | ||
| 4893 | #define UVXH_EVENT_OCCURRED2_RTC_5_SHFT 5 | ||
| 4894 | #define UVXH_EVENT_OCCURRED2_RTC_6_SHFT 6 | ||
| 4895 | #define UVXH_EVENT_OCCURRED2_RTC_7_SHFT 7 | ||
| 4896 | #define UVXH_EVENT_OCCURRED2_RTC_8_SHFT 8 | ||
| 4897 | #define UVXH_EVENT_OCCURRED2_RTC_9_SHFT 9 | ||
| 4898 | #define UVXH_EVENT_OCCURRED2_RTC_10_SHFT 10 | ||
| 4899 | #define UVXH_EVENT_OCCURRED2_RTC_11_SHFT 11 | ||
| 4900 | #define UVXH_EVENT_OCCURRED2_RTC_12_SHFT 12 | ||
| 4901 | #define UVXH_EVENT_OCCURRED2_RTC_13_SHFT 13 | ||
| 4902 | #define UVXH_EVENT_OCCURRED2_RTC_14_SHFT 14 | ||
| 4903 | #define UVXH_EVENT_OCCURRED2_RTC_15_SHFT 15 | ||
| 4904 | #define UVXH_EVENT_OCCURRED2_RTC_16_SHFT 16 | ||
| 4905 | #define UVXH_EVENT_OCCURRED2_RTC_17_SHFT 17 | ||
| 4906 | #define UVXH_EVENT_OCCURRED2_RTC_18_SHFT 18 | ||
| 4907 | #define UVXH_EVENT_OCCURRED2_RTC_19_SHFT 19 | ||
| 4908 | #define UVXH_EVENT_OCCURRED2_RTC_20_SHFT 20 | ||
| 4909 | #define UVXH_EVENT_OCCURRED2_RTC_21_SHFT 21 | ||
| 4910 | #define UVXH_EVENT_OCCURRED2_RTC_22_SHFT 22 | ||
| 4911 | #define UVXH_EVENT_OCCURRED2_RTC_23_SHFT 23 | ||
| 4912 | #define UVXH_EVENT_OCCURRED2_RTC_24_SHFT 24 | ||
| 4913 | #define UVXH_EVENT_OCCURRED2_RTC_25_SHFT 25 | ||
| 4914 | #define UVXH_EVENT_OCCURRED2_RTC_26_SHFT 26 | ||
| 4915 | #define UVXH_EVENT_OCCURRED2_RTC_27_SHFT 27 | ||
| 4916 | #define UVXH_EVENT_OCCURRED2_RTC_28_SHFT 28 | ||
| 4917 | #define UVXH_EVENT_OCCURRED2_RTC_29_SHFT 29 | ||
| 4918 | #define UVXH_EVENT_OCCURRED2_RTC_30_SHFT 30 | ||
| 4919 | #define UVXH_EVENT_OCCURRED2_RTC_31_SHFT 31 | ||
| 4920 | #define UVXH_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL | ||
| 4921 | #define UVXH_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL | ||
| 4922 | #define UVXH_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL | ||
| 4923 | #define UVXH_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL | ||
| 4924 | #define UVXH_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL | ||
| 4925 | #define UVXH_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL | ||
| 4926 | #define UVXH_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL | ||
| 4927 | #define UVXH_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL | ||
| 4928 | #define UVXH_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL | ||
| 4929 | #define UVXH_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL | ||
| 4930 | #define UVXH_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL | ||
| 4931 | #define UVXH_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL | ||
| 4932 | #define UVXH_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL | ||
| 4933 | #define UVXH_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL | ||
| 4934 | #define UVXH_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL | ||
| 4935 | #define UVXH_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL | ||
| 4936 | #define UVXH_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL | ||
| 4937 | #define UVXH_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL | ||
| 4938 | #define UVXH_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL | ||
| 4939 | #define UVXH_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL | ||
| 4940 | #define UVXH_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL | ||
| 4941 | #define UVXH_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL | ||
| 4942 | #define UVXH_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL | ||
| 4943 | #define UVXH_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL | ||
| 4944 | #define UVXH_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL | ||
| 4945 | #define UVXH_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL | ||
| 4946 | #define UVXH_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL | ||
| 4947 | #define UVXH_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL | ||
| 4948 | #define UVXH_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL | ||
| 4949 | #define UVXH_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL | ||
| 4950 | #define UVXH_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL | ||
| 4951 | #define UVXH_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL | ||
| 1932 | 4952 | ||
| 1933 | #define UV2H_EVENT_OCCURRED2_RTC_0_SHFT 0 | 4953 | #define UV2H_EVENT_OCCURRED2_RTC_0_SHFT 0 |
| 1934 | #define UV2H_EVENT_OCCURRED2_RTC_1_SHFT 1 | 4954 | #define UV2H_EVENT_OCCURRED2_RTC_1_SHFT 1 |
| @@ -1995,8 +5015,108 @@ union uvh_scratch5_u { | |||
| 1995 | #define UV2H_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL | 5015 | #define UV2H_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL |
| 1996 | #define UV2H_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL | 5016 | #define UV2H_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL |
| 1997 | 5017 | ||
| 1998 | union uv2h_event_occurred2_u { | 5018 | #define UV3H_EVENT_OCCURRED2_RTC_0_SHFT 0 |
| 5019 | #define UV3H_EVENT_OCCURRED2_RTC_1_SHFT 1 | ||
| 5020 | #define UV3H_EVENT_OCCURRED2_RTC_2_SHFT 2 | ||
| 5021 | #define UV3H_EVENT_OCCURRED2_RTC_3_SHFT 3 | ||
| 5022 | #define UV3H_EVENT_OCCURRED2_RTC_4_SHFT 4 | ||
| 5023 | #define UV3H_EVENT_OCCURRED2_RTC_5_SHFT 5 | ||
| 5024 | #define UV3H_EVENT_OCCURRED2_RTC_6_SHFT 6 | ||
| 5025 | #define UV3H_EVENT_OCCURRED2_RTC_7_SHFT 7 | ||
| 5026 | #define UV3H_EVENT_OCCURRED2_RTC_8_SHFT 8 | ||
| 5027 | #define UV3H_EVENT_OCCURRED2_RTC_9_SHFT 9 | ||
| 5028 | #define UV3H_EVENT_OCCURRED2_RTC_10_SHFT 10 | ||
| 5029 | #define UV3H_EVENT_OCCURRED2_RTC_11_SHFT 11 | ||
| 5030 | #define UV3H_EVENT_OCCURRED2_RTC_12_SHFT 12 | ||
| 5031 | #define UV3H_EVENT_OCCURRED2_RTC_13_SHFT 13 | ||
| 5032 | #define UV3H_EVENT_OCCURRED2_RTC_14_SHFT 14 | ||
| 5033 | #define UV3H_EVENT_OCCURRED2_RTC_15_SHFT 15 | ||
| 5034 | #define UV3H_EVENT_OCCURRED2_RTC_16_SHFT 16 | ||
| 5035 | #define UV3H_EVENT_OCCURRED2_RTC_17_SHFT 17 | ||
| 5036 | #define UV3H_EVENT_OCCURRED2_RTC_18_SHFT 18 | ||
| 5037 | #define UV3H_EVENT_OCCURRED2_RTC_19_SHFT 19 | ||
| 5038 | #define UV3H_EVENT_OCCURRED2_RTC_20_SHFT 20 | ||
| 5039 | #define UV3H_EVENT_OCCURRED2_RTC_21_SHFT 21 | ||
| 5040 | #define UV3H_EVENT_OCCURRED2_RTC_22_SHFT 22 | ||
| 5041 | #define UV3H_EVENT_OCCURRED2_RTC_23_SHFT 23 | ||
| 5042 | #define UV3H_EVENT_OCCURRED2_RTC_24_SHFT 24 | ||
| 5043 | #define UV3H_EVENT_OCCURRED2_RTC_25_SHFT 25 | ||
| 5044 | #define UV3H_EVENT_OCCURRED2_RTC_26_SHFT 26 | ||
| 5045 | #define UV3H_EVENT_OCCURRED2_RTC_27_SHFT 27 | ||
| 5046 | #define UV3H_EVENT_OCCURRED2_RTC_28_SHFT 28 | ||
| 5047 | #define UV3H_EVENT_OCCURRED2_RTC_29_SHFT 29 | ||
| 5048 | #define UV3H_EVENT_OCCURRED2_RTC_30_SHFT 30 | ||
| 5049 | #define UV3H_EVENT_OCCURRED2_RTC_31_SHFT 31 | ||
| 5050 | #define UV3H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL | ||
| 5051 | #define UV3H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL | ||
| 5052 | #define UV3H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL | ||
| 5053 | #define UV3H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL | ||
| 5054 | #define UV3H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL | ||
| 5055 | #define UV3H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL | ||
| 5056 | #define UV3H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL | ||
| 5057 | #define UV3H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL | ||
| 5058 | #define UV3H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL | ||
| 5059 | #define UV3H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL | ||
| 5060 | #define UV3H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL | ||
| 5061 | #define UV3H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL | ||
| 5062 | #define UV3H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL | ||
| 5063 | #define UV3H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL | ||
| 5064 | #define UV3H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL | ||
| 5065 | #define UV3H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL | ||
| 5066 | #define UV3H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL | ||
| 5067 | #define UV3H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL | ||
| 5068 | #define UV3H_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL | ||
| 5069 | #define UV3H_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL | ||
| 5070 | #define UV3H_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL | ||
| 5071 | #define UV3H_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL | ||
| 5072 | #define UV3H_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL | ||
| 5073 | #define UV3H_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL | ||
| 5074 | #define UV3H_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL | ||
| 5075 | #define UV3H_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL | ||
| 5076 | #define UV3H_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL | ||
| 5077 | #define UV3H_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL | ||
| 5078 | #define UV3H_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL | ||
| 5079 | #define UV3H_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL | ||
| 5080 | #define UV3H_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL | ||
| 5081 | #define UV3H_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL | ||
| 5082 | |||
| 5083 | union uvxh_event_occurred2_u { | ||
| 1999 | unsigned long v; | 5084 | unsigned long v; |
| 5085 | struct uvxh_event_occurred2_s { | ||
| 5086 | unsigned long rtc_0:1; /* RW */ | ||
| 5087 | unsigned long rtc_1:1; /* RW */ | ||
| 5088 | unsigned long rtc_2:1; /* RW */ | ||
| 5089 | unsigned long rtc_3:1; /* RW */ | ||
| 5090 | unsigned long rtc_4:1; /* RW */ | ||
| 5091 | unsigned long rtc_5:1; /* RW */ | ||
| 5092 | unsigned long rtc_6:1; /* RW */ | ||
| 5093 | unsigned long rtc_7:1; /* RW */ | ||
| 5094 | unsigned long rtc_8:1; /* RW */ | ||
| 5095 | unsigned long rtc_9:1; /* RW */ | ||
| 5096 | unsigned long rtc_10:1; /* RW */ | ||
| 5097 | unsigned long rtc_11:1; /* RW */ | ||
| 5098 | unsigned long rtc_12:1; /* RW */ | ||
| 5099 | unsigned long rtc_13:1; /* RW */ | ||
| 5100 | unsigned long rtc_14:1; /* RW */ | ||
| 5101 | unsigned long rtc_15:1; /* RW */ | ||
| 5102 | unsigned long rtc_16:1; /* RW */ | ||
| 5103 | unsigned long rtc_17:1; /* RW */ | ||
| 5104 | unsigned long rtc_18:1; /* RW */ | ||
| 5105 | unsigned long rtc_19:1; /* RW */ | ||
| 5106 | unsigned long rtc_20:1; /* RW */ | ||
| 5107 | unsigned long rtc_21:1; /* RW */ | ||
| 5108 | unsigned long rtc_22:1; /* RW */ | ||
| 5109 | unsigned long rtc_23:1; /* RW */ | ||
| 5110 | unsigned long rtc_24:1; /* RW */ | ||
| 5111 | unsigned long rtc_25:1; /* RW */ | ||
| 5112 | unsigned long rtc_26:1; /* RW */ | ||
| 5113 | unsigned long rtc_27:1; /* RW */ | ||
| 5114 | unsigned long rtc_28:1; /* RW */ | ||
| 5115 | unsigned long rtc_29:1; /* RW */ | ||
| 5116 | unsigned long rtc_30:1; /* RW */ | ||
| 5117 | unsigned long rtc_31:1; /* RW */ | ||
| 5118 | unsigned long rsvd_32_63:32; | ||
| 5119 | } sx; | ||
| 2000 | struct uv2h_event_occurred2_s { | 5120 | struct uv2h_event_occurred2_s { |
| 2001 | unsigned long rtc_0:1; /* RW */ | 5121 | unsigned long rtc_0:1; /* RW */ |
| 2002 | unsigned long rtc_1:1; /* RW */ | 5122 | unsigned long rtc_1:1; /* RW */ |
| @@ -2031,29 +5151,85 @@ union uv2h_event_occurred2_u { | |||
| 2031 | unsigned long rtc_30:1; /* RW */ | 5151 | unsigned long rtc_30:1; /* RW */ |
| 2032 | unsigned long rtc_31:1; /* RW */ | 5152 | unsigned long rtc_31:1; /* RW */ |
| 2033 | unsigned long rsvd_32_63:32; | 5153 | unsigned long rsvd_32_63:32; |
| 2034 | } s1; | 5154 | } s2; |
| 5155 | struct uv3h_event_occurred2_s { | ||
| 5156 | unsigned long rtc_0:1; /* RW */ | ||
| 5157 | unsigned long rtc_1:1; /* RW */ | ||
| 5158 | unsigned long rtc_2:1; /* RW */ | ||
| 5159 | unsigned long rtc_3:1; /* RW */ | ||
| 5160 | unsigned long rtc_4:1; /* RW */ | ||
| 5161 | unsigned long rtc_5:1; /* RW */ | ||
| 5162 | unsigned long rtc_6:1; /* RW */ | ||
| 5163 | unsigned long rtc_7:1; /* RW */ | ||
| 5164 | unsigned long rtc_8:1; /* RW */ | ||
| 5165 | unsigned long rtc_9:1; /* RW */ | ||
| 5166 | unsigned long rtc_10:1; /* RW */ | ||
| 5167 | unsigned long rtc_11:1; /* RW */ | ||
| 5168 | unsigned long rtc_12:1; /* RW */ | ||
| 5169 | unsigned long rtc_13:1; /* RW */ | ||
| 5170 | unsigned long rtc_14:1; /* RW */ | ||
| 5171 | unsigned long rtc_15:1; /* RW */ | ||
| 5172 | unsigned long rtc_16:1; /* RW */ | ||
| 5173 | unsigned long rtc_17:1; /* RW */ | ||
| 5174 | unsigned long rtc_18:1; /* RW */ | ||
| 5175 | unsigned long rtc_19:1; /* RW */ | ||
| 5176 | unsigned long rtc_20:1; /* RW */ | ||
| 5177 | unsigned long rtc_21:1; /* RW */ | ||
| 5178 | unsigned long rtc_22:1; /* RW */ | ||
| 5179 | unsigned long rtc_23:1; /* RW */ | ||
| 5180 | unsigned long rtc_24:1; /* RW */ | ||
| 5181 | unsigned long rtc_25:1; /* RW */ | ||
| 5182 | unsigned long rtc_26:1; /* RW */ | ||
| 5183 | unsigned long rtc_27:1; /* RW */ | ||
| 5184 | unsigned long rtc_28:1; /* RW */ | ||
| 5185 | unsigned long rtc_29:1; /* RW */ | ||
| 5186 | unsigned long rtc_30:1; /* RW */ | ||
| 5187 | unsigned long rtc_31:1; /* RW */ | ||
| 5188 | unsigned long rsvd_32_63:32; | ||
| 5189 | } s3; | ||
| 2035 | }; | 5190 | }; |
| 2036 | 5191 | ||
| 2037 | /* ========================================================================= */ | 5192 | /* ========================================================================= */ |
| 2038 | /* UV2H_EVENT_OCCURRED2_ALIAS */ | 5193 | /* UVXH_EVENT_OCCURRED2_ALIAS */ |
| 2039 | /* ========================================================================= */ | 5194 | /* ========================================================================= */ |
| 2040 | #define UV2H_EVENT_OCCURRED2_ALIAS 0x70108UL | 5195 | #define UVXH_EVENT_OCCURRED2_ALIAS 0x70108UL |
| 2041 | #define UV2H_EVENT_OCCURRED2_ALIAS_32 0xb70 | 5196 | #define UV2H_EVENT_OCCURRED2_ALIAS 0x70108UL |
| 5197 | #define UV3H_EVENT_OCCURRED2_ALIAS 0x70108UL | ||
| 5198 | #define UVXH_EVENT_OCCURRED2_ALIAS_32 0xb70 | ||
| 5199 | #define UV2H_EVENT_OCCURRED2_ALIAS_32 0x70108UL | ||
| 5200 | #define UV3H_EVENT_OCCURRED2_ALIAS_32 0x70108UL | ||
| 5201 | |||
| 2042 | 5202 | ||
| 2043 | /* ========================================================================= */ | 5203 | /* ========================================================================= */ |
| 2044 | /* UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 */ | 5204 | /* UVXH_LB_BAU_SB_ACTIVATION_STATUS_2 */ |
| 2045 | /* ========================================================================= */ | 5205 | /* ========================================================================= */ |
| 2046 | #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL | 5206 | #define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL |
| 2047 | #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0 | 5207 | #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL |
| 5208 | #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL | ||
| 5209 | #define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0 | ||
| 5210 | #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x320130UL | ||
| 5211 | #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x320130UL | ||
| 5212 | |||
| 5213 | #define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0 | ||
| 5214 | #define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL | ||
| 2048 | 5215 | ||
| 2049 | #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0 | 5216 | #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0 |
| 2050 | #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL | 5217 | #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL |
| 2051 | 5218 | ||
| 2052 | union uv2h_lb_bau_sb_activation_status_2_u { | 5219 | #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0 |
| 5220 | #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL | ||
| 5221 | |||
| 5222 | union uvxh_lb_bau_sb_activation_status_2_u { | ||
| 2053 | unsigned long v; | 5223 | unsigned long v; |
| 5224 | struct uvxh_lb_bau_sb_activation_status_2_s { | ||
| 5225 | unsigned long aux_error:64; /* RW */ | ||
| 5226 | } sx; | ||
| 2054 | struct uv2h_lb_bau_sb_activation_status_2_s { | 5227 | struct uv2h_lb_bau_sb_activation_status_2_s { |
| 2055 | unsigned long aux_error:64; /* RW */ | 5228 | unsigned long aux_error:64; /* RW */ |
| 2056 | } s1; | 5229 | } s2; |
| 5230 | struct uv3h_lb_bau_sb_activation_status_2_s { | ||
| 5231 | unsigned long aux_error:64; /* RW */ | ||
| 5232 | } s3; | ||
| 2057 | }; | 5233 | }; |
| 2058 | 5234 | ||
| 2059 | /* ========================================================================= */ | 5235 | /* ========================================================================= */ |
| @@ -2073,5 +5249,87 @@ union uv1h_lb_target_physical_apic_id_mask_u { | |||
| 2073 | } s1; | 5249 | } s1; |
| 2074 | }; | 5250 | }; |
| 2075 | 5251 | ||
| 5252 | /* ========================================================================= */ | ||
| 5253 | /* UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR */ | ||
| 5254 | /* ========================================================================= */ | ||
| 5255 | #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR 0x1603000UL | ||
| 5256 | |||
| 5257 | #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT 26 | ||
| 5258 | #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT 46 | ||
| 5259 | #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_SHFT 63 | ||
| 5260 | #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK 0x00003ffffc000000UL | ||
| 5261 | #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK 0x000fc00000000000UL | ||
| 5262 | #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK 0x8000000000000000UL | ||
| 5263 | |||
| 5264 | union uv3h_rh_gam_mmioh_overlay_config0_mmr_u { | ||
| 5265 | unsigned long v; | ||
| 5266 | struct uv3h_rh_gam_mmioh_overlay_config0_mmr_s { | ||
| 5267 | unsigned long rsvd_0_25:26; | ||
| 5268 | unsigned long base:20; /* RW */ | ||
| 5269 | unsigned long m_io:6; /* RW */ | ||
| 5270 | unsigned long n_io:4; | ||
| 5271 | unsigned long rsvd_56_62:7; | ||
| 5272 | unsigned long enable:1; /* RW */ | ||
| 5273 | } s3; | ||
| 5274 | }; | ||
| 5275 | |||
| 5276 | /* ========================================================================= */ | ||
| 5277 | /* UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR */ | ||
| 5278 | /* ========================================================================= */ | ||
| 5279 | #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR 0x1604000UL | ||
| 5280 | |||
| 5281 | #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_SHFT 26 | ||
| 5282 | #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT 46 | ||
| 5283 | #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_SHFT 63 | ||
| 5284 | #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK 0x00003ffffc000000UL | ||
| 5285 | #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK 0x000fc00000000000UL | ||
| 5286 | #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_MASK 0x8000000000000000UL | ||
| 5287 | |||
| 5288 | union uv3h_rh_gam_mmioh_overlay_config1_mmr_u { | ||
| 5289 | unsigned long v; | ||
| 5290 | struct uv3h_rh_gam_mmioh_overlay_config1_mmr_s { | ||
| 5291 | unsigned long rsvd_0_25:26; | ||
| 5292 | unsigned long base:20; /* RW */ | ||
| 5293 | unsigned long m_io:6; /* RW */ | ||
| 5294 | unsigned long n_io:4; | ||
| 5295 | unsigned long rsvd_56_62:7; | ||
| 5296 | unsigned long enable:1; /* RW */ | ||
| 5297 | } s3; | ||
| 5298 | }; | ||
| 5299 | |||
| 5300 | /* ========================================================================= */ | ||
| 5301 | /* UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR */ | ||
| 5302 | /* ========================================================================= */ | ||
| 5303 | #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR 0x1603800UL | ||
| 5304 | #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH 128 | ||
| 5305 | |||
| 5306 | #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_SHFT 0 | ||
| 5307 | #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK 0x0000000000007fffUL | ||
| 5308 | |||
| 5309 | union uv3h_rh_gam_mmioh_redirect_config0_mmr_u { | ||
| 5310 | unsigned long v; | ||
| 5311 | struct uv3h_rh_gam_mmioh_redirect_config0_mmr_s { | ||
| 5312 | unsigned long nasid:15; /* RW */ | ||
| 5313 | unsigned long rsvd_15_63:49; | ||
| 5314 | } s3; | ||
| 5315 | }; | ||
| 5316 | |||
| 5317 | /* ========================================================================= */ | ||
| 5318 | /* UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR */ | ||
| 5319 | /* ========================================================================= */ | ||
| 5320 | #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR 0x1604800UL | ||
| 5321 | #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH 128 | ||
| 5322 | |||
| 5323 | #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_SHFT 0 | ||
| 5324 | #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK 0x0000000000007fffUL | ||
| 5325 | |||
| 5326 | union uv3h_rh_gam_mmioh_redirect_config1_mmr_u { | ||
| 5327 | unsigned long v; | ||
| 5328 | struct uv3h_rh_gam_mmioh_redirect_config1_mmr_s { | ||
| 5329 | unsigned long nasid:15; /* RW */ | ||
| 5330 | unsigned long rsvd_15_63:49; | ||
| 5331 | } s3; | ||
| 5332 | }; | ||
| 5333 | |||
| 2076 | 5334 | ||
| 2077 | #endif /* _ASM_X86_UV_UV_MMRS_H */ | 5335 | #endif /* _ASM_X86_UV_UV_MMRS_H */ |