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-rw-r--r--drivers/gpu/drm/i915/i915_drv.h2
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c2
-rw-r--r--drivers/gpu/drm/i915/intel_display.c337
3 files changed, 195 insertions, 146 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0cf65a4350c0..581395e581eb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -209,12 +209,12 @@ struct drm_i915_display_funcs {
209 int x, int y, 209 int x, int y,
210 struct drm_framebuffer *old_fb); 210 struct drm_framebuffer *old_fb);
211 void (*fdi_link_train)(struct drm_crtc *crtc); 211 void (*fdi_link_train)(struct drm_crtc *crtc);
212 void (*init_clock_gating)(struct drm_device *dev);
212 /* clock updates for mode set */ 213 /* clock updates for mode set */
213 /* cursor updates */ 214 /* cursor updates */
214 /* render clock increase/decrease */ 215 /* render clock increase/decrease */
215 /* display clock increase/decrease */ 216 /* display clock increase/decrease */
216 /* pll clock increase/decrease */ 217 /* pll clock increase/decrease */
217 /* clock gating init */
218}; 218};
219 219
220struct intel_device_info { 220struct intel_device_info {
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index da474153a0a2..6cb27ff51891 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -864,7 +864,7 @@ int i915_restore_state(struct drm_device *dev)
864 } 864 }
865 865
866 /* Clock gating state */ 866 /* Clock gating state */
867 intel_enable_clock_gating(dev); 867 dev_priv->display.init_clock_gating(dev);
868 868
869 if (IS_IRONLAKE_M(dev)) { 869 if (IS_IRONLAKE_M(dev)) {
870 ironlake_enable_drps(dev); 870 ironlake_enable_drps(dev);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 18888a2fefa2..7eeffaf775ed 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7211,161 +7211,194 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
7211 mutex_unlock(&dev_priv->dev->struct_mutex); 7211 mutex_unlock(&dev_priv->dev->struct_mutex);
7212} 7212}
7213 7213
7214void intel_enable_clock_gating(struct drm_device *dev) 7214static void ironlake_init_clock_gating(struct drm_device *dev)
7215{
7216 struct drm_i915_private *dev_priv = dev->dev_private;
7217 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7218
7219 /* Required for FBC */
7220 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7221 DPFCRUNIT_CLOCK_GATE_DISABLE |
7222 DPFDUNIT_CLOCK_GATE_DISABLE;
7223 /* Required for CxSR */
7224 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7225
7226 I915_WRITE(PCH_3DCGDIS0,
7227 MARIUNIT_CLOCK_GATE_DISABLE |
7228 SVSMUNIT_CLOCK_GATE_DISABLE);
7229 I915_WRITE(PCH_3DCGDIS1,
7230 VFMUNIT_CLOCK_GATE_DISABLE);
7231
7232 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7233
7234 /*
7235 * On Ibex Peak and Cougar Point, we need to disable clock
7236 * gating for the panel power sequencer or it will fail to
7237 * start up when no ports are active.
7238 */
7239 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7240
7241 /*
7242 * According to the spec the following bits should be set in
7243 * order to enable memory self-refresh
7244 * The bit 22/21 of 0x42004
7245 * The bit 5 of 0x42020
7246 * The bit 15 of 0x45000
7247 */
7248 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7249 (I915_READ(ILK_DISPLAY_CHICKEN2) |
7250 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7251 I915_WRITE(ILK_DSPCLK_GATE,
7252 (I915_READ(ILK_DSPCLK_GATE) |
7253 ILK_DPARB_CLK_GATE));
7254 I915_WRITE(DISP_ARB_CTL,
7255 (I915_READ(DISP_ARB_CTL) |
7256 DISP_FBC_WM_DIS));
7257 I915_WRITE(WM3_LP_ILK, 0);
7258 I915_WRITE(WM2_LP_ILK, 0);
7259 I915_WRITE(WM1_LP_ILK, 0);
7260
7261 /*
7262 * Based on the document from hardware guys the following bits
7263 * should be set unconditionally in order to enable FBC.
7264 * The bit 22 of 0x42000
7265 * The bit 22 of 0x42004
7266 * The bit 7,8,9 of 0x42020.
7267 */
7268 if (IS_IRONLAKE_M(dev)) {
7269 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7270 I915_READ(ILK_DISPLAY_CHICKEN1) |
7271 ILK_FBCQ_DIS);
7272 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7273 I915_READ(ILK_DISPLAY_CHICKEN2) |
7274 ILK_DPARB_GATE);
7275 I915_WRITE(ILK_DSPCLK_GATE,
7276 I915_READ(ILK_DSPCLK_GATE) |
7277 ILK_DPFC_DIS1 |
7278 ILK_DPFC_DIS2 |
7279 ILK_CLK_FBC);
7280 }
7281
7282 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7283 I915_READ(ILK_DISPLAY_CHICKEN2) |
7284 ILK_ELPIN_409_SELECT);
7285 I915_WRITE(_3D_CHICKEN2,
7286 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7287 _3D_CHICKEN2_WM_READ_PIPELINED);
7288}
7289
7290static void gen6_init_clock_gating(struct drm_device *dev)
7215{ 7291{
7216 struct drm_i915_private *dev_priv = dev->dev_private; 7292 struct drm_i915_private *dev_priv = dev->dev_private;
7217 int pipe; 7293 int pipe;
7294 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7295
7296 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7218 7297
7219 /* 7298 /*
7220 * Disable clock gating reported to work incorrectly according to the 7299 * On Ibex Peak and Cougar Point, we need to disable clock
7221 * specs, but enable as much else as we can. 7300 * gating for the panel power sequencer or it will fail to
7301 * start up when no ports are active.
7222 */ 7302 */
7223 if (HAS_PCH_SPLIT(dev)) { 7303 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7224 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7225 7304
7226 if (IS_GEN5(dev)) { 7305 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7227 /* Required for FBC */ 7306 I915_READ(ILK_DISPLAY_CHICKEN2) |
7228 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE | 7307 ILK_ELPIN_409_SELECT);
7229 DPFCRUNIT_CLOCK_GATE_DISABLE |
7230 DPFDUNIT_CLOCK_GATE_DISABLE;
7231 /* Required for CxSR */
7232 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7233
7234 I915_WRITE(PCH_3DCGDIS0,
7235 MARIUNIT_CLOCK_GATE_DISABLE |
7236 SVSMUNIT_CLOCK_GATE_DISABLE);
7237 I915_WRITE(PCH_3DCGDIS1,
7238 VFMUNIT_CLOCK_GATE_DISABLE);
7239 }
7240 7308
7241 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); 7309 I915_WRITE(WM3_LP_ILK, 0);
7310 I915_WRITE(WM2_LP_ILK, 0);
7311 I915_WRITE(WM1_LP_ILK, 0);
7242 7312
7243 /* 7313 /*
7244 * On Ibex Peak and Cougar Point, we need to disable clock 7314 * According to the spec the following bits should be
7245 * gating for the panel power sequencer or it will fail to 7315 * set in order to enable memory self-refresh and fbc:
7246 * start up when no ports are active. 7316 * The bit21 and bit22 of 0x42000
7247 */ 7317 * The bit21 and bit22 of 0x42004
7248 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); 7318 * The bit5 and bit7 of 0x42020
7319 * The bit14 of 0x70180
7320 * The bit14 of 0x71180
7321 */
7322 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7323 I915_READ(ILK_DISPLAY_CHICKEN1) |
7324 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7325 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7326 I915_READ(ILK_DISPLAY_CHICKEN2) |
7327 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7328 I915_WRITE(ILK_DSPCLK_GATE,
7329 I915_READ(ILK_DSPCLK_GATE) |
7330 ILK_DPARB_CLK_GATE |
7331 ILK_DPFD_CLK_GATE);
7249 7332
7250 /* 7333 for_each_pipe(pipe)
7251 * According to the spec the following bits should be set in 7334 I915_WRITE(DSPCNTR(pipe),
7252 * order to enable memory self-refresh 7335 I915_READ(DSPCNTR(pipe)) |
7253 * The bit 22/21 of 0x42004 7336 DISPPLANE_TRICKLE_FEED_DISABLE);
7254 * The bit 5 of 0x42020 7337}
7255 * The bit 15 of 0x45000
7256 */
7257 if (IS_GEN5(dev)) {
7258 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7259 (I915_READ(ILK_DISPLAY_CHICKEN2) |
7260 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7261 I915_WRITE(ILK_DSPCLK_GATE,
7262 (I915_READ(ILK_DSPCLK_GATE) |
7263 ILK_DPARB_CLK_GATE));
7264 I915_WRITE(DISP_ARB_CTL,
7265 (I915_READ(DISP_ARB_CTL) |
7266 DISP_FBC_WM_DIS));
7267 I915_WRITE(WM3_LP_ILK, 0);
7268 I915_WRITE(WM2_LP_ILK, 0);
7269 I915_WRITE(WM1_LP_ILK, 0);
7270 }
7271 /*
7272 * Based on the document from hardware guys the following bits
7273 * should be set unconditionally in order to enable FBC.
7274 * The bit 22 of 0x42000
7275 * The bit 22 of 0x42004
7276 * The bit 7,8,9 of 0x42020.
7277 */
7278 if (IS_IRONLAKE_M(dev)) {
7279 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7280 I915_READ(ILK_DISPLAY_CHICKEN1) |
7281 ILK_FBCQ_DIS);
7282 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7283 I915_READ(ILK_DISPLAY_CHICKEN2) |
7284 ILK_DPARB_GATE);
7285 I915_WRITE(ILK_DSPCLK_GATE,
7286 I915_READ(ILK_DSPCLK_GATE) |
7287 ILK_DPFC_DIS1 |
7288 ILK_DPFC_DIS2 |
7289 ILK_CLK_FBC);
7290 }
7291 7338
7292 I915_WRITE(ILK_DISPLAY_CHICKEN2, 7339static void g4x_init_clock_gating(struct drm_device *dev)
7293 I915_READ(ILK_DISPLAY_CHICKEN2) | 7340{
7294 ILK_ELPIN_409_SELECT); 7341 struct drm_i915_private *dev_priv = dev->dev_private;
7342 uint32_t dspclk_gate;
7295 7343
7296 if (IS_GEN5(dev)) { 7344 I915_WRITE(RENCLK_GATE_D1, 0);
7297 I915_WRITE(_3D_CHICKEN2, 7345 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7298 _3D_CHICKEN2_WM_READ_PIPELINED << 16 | 7346 GS_UNIT_CLOCK_GATE_DISABLE |
7299 _3D_CHICKEN2_WM_READ_PIPELINED); 7347 CL_UNIT_CLOCK_GATE_DISABLE);
7300 } 7348 I915_WRITE(RAMCLK_GATE_D, 0);
7349 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7350 OVRUNIT_CLOCK_GATE_DISABLE |
7351 OVCUNIT_CLOCK_GATE_DISABLE;
7352 if (IS_GM45(dev))
7353 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7354 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7355}
7301 7356
7302 if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) { 7357static void crestline_init_clock_gating(struct drm_device *dev)
7303 I915_WRITE(WM3_LP_ILK, 0); 7358{
7304 I915_WRITE(WM2_LP_ILK, 0); 7359 struct drm_i915_private *dev_priv = dev->dev_private;
7305 I915_WRITE(WM1_LP_ILK, 0);
7306 7360
7307 /* 7361 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7308 * According to the spec the following bits should be 7362 I915_WRITE(RENCLK_GATE_D2, 0);
7309 * set in order to enable memory self-refresh and fbc: 7363 I915_WRITE(DSPCLK_GATE_D, 0);
7310 * The bit21 and bit22 of 0x42000 7364 I915_WRITE(RAMCLK_GATE_D, 0);
7311 * The bit21 and bit22 of 0x42004 7365 I915_WRITE16(DEUC, 0);
7312 * The bit5 and bit7 of 0x42020 7366}
7313 * The bit14 of 0x70180
7314 * The bit14 of 0x71180
7315 */
7316 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7317 I915_READ(ILK_DISPLAY_CHICKEN1) |
7318 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7319 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7320 I915_READ(ILK_DISPLAY_CHICKEN2) |
7321 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7322 I915_WRITE(ILK_DSPCLK_GATE,
7323 I915_READ(ILK_DSPCLK_GATE) |
7324 ILK_DPARB_CLK_GATE |
7325 ILK_DPFD_CLK_GATE);
7326
7327 for_each_pipe(pipe)
7328 I915_WRITE(DSPCNTR(pipe),
7329 I915_READ(DSPCNTR(pipe)) |
7330 DISPPLANE_TRICKLE_FEED_DISABLE);
7331 }
7332 } else if (IS_G4X(dev)) {
7333 uint32_t dspclk_gate;
7334 I915_WRITE(RENCLK_GATE_D1, 0);
7335 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7336 GS_UNIT_CLOCK_GATE_DISABLE |
7337 CL_UNIT_CLOCK_GATE_DISABLE);
7338 I915_WRITE(RAMCLK_GATE_D, 0);
7339 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7340 OVRUNIT_CLOCK_GATE_DISABLE |
7341 OVCUNIT_CLOCK_GATE_DISABLE;
7342 if (IS_GM45(dev))
7343 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7344 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7345 } else if (IS_CRESTLINE(dev)) {
7346 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7347 I915_WRITE(RENCLK_GATE_D2, 0);
7348 I915_WRITE(DSPCLK_GATE_D, 0);
7349 I915_WRITE(RAMCLK_GATE_D, 0);
7350 I915_WRITE16(DEUC, 0);
7351 } else if (IS_BROADWATER(dev)) {
7352 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7353 I965_RCC_CLOCK_GATE_DISABLE |
7354 I965_RCPB_CLOCK_GATE_DISABLE |
7355 I965_ISC_CLOCK_GATE_DISABLE |
7356 I965_FBC_CLOCK_GATE_DISABLE);
7357 I915_WRITE(RENCLK_GATE_D2, 0);
7358 } else if (IS_GEN3(dev)) {
7359 u32 dstate = I915_READ(D_STATE);
7360 7367
7361 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | 7368static void broadwater_init_clock_gating(struct drm_device *dev)
7362 DSTATE_DOT_CLOCK_GATING; 7369{
7363 I915_WRITE(D_STATE, dstate); 7370 struct drm_i915_private *dev_priv = dev->dev_private;
7364 } else if (IS_I85X(dev) || IS_I865G(dev)) { 7371
7365 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); 7372 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7366 } else if (IS_I830(dev)) { 7373 I965_RCC_CLOCK_GATE_DISABLE |
7367 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); 7374 I965_RCPB_CLOCK_GATE_DISABLE |
7368 } 7375 I965_ISC_CLOCK_GATE_DISABLE |
7376 I965_FBC_CLOCK_GATE_DISABLE);
7377 I915_WRITE(RENCLK_GATE_D2, 0);
7378}
7379
7380static void gen3_init_clock_gating(struct drm_device *dev)
7381{
7382 struct drm_i915_private *dev_priv = dev->dev_private;
7383 u32 dstate = I915_READ(D_STATE);
7384
7385 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7386 DSTATE_DOT_CLOCK_GATING;
7387 I915_WRITE(D_STATE, dstate);
7388}
7389
7390static void i85x_init_clock_gating(struct drm_device *dev)
7391{
7392 struct drm_i915_private *dev_priv = dev->dev_private;
7393
7394 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7395}
7396
7397static void i830_init_clock_gating(struct drm_device *dev)
7398{
7399 struct drm_i915_private *dev_priv = dev->dev_private;
7400
7401 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7369} 7402}
7370 7403
7371static void ironlake_teardown_rc6(struct drm_device *dev) 7404static void ironlake_teardown_rc6(struct drm_device *dev)
@@ -7549,6 +7582,7 @@ static void intel_init_display(struct drm_device *dev)
7549 dev_priv->display.update_wm = NULL; 7582 dev_priv->display.update_wm = NULL;
7550 } 7583 }
7551 dev_priv->display.fdi_link_train = ironlake_fdi_link_train; 7584 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
7585 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7552 } else if (IS_GEN6(dev)) { 7586 } else if (IS_GEN6(dev)) {
7553 if (SNB_READ_WM0_LATENCY()) { 7587 if (SNB_READ_WM0_LATENCY()) {
7554 dev_priv->display.update_wm = sandybridge_update_wm; 7588 dev_priv->display.update_wm = sandybridge_update_wm;
@@ -7558,6 +7592,7 @@ static void intel_init_display(struct drm_device *dev)
7558 dev_priv->display.update_wm = NULL; 7592 dev_priv->display.update_wm = NULL;
7559 } 7593 }
7560 dev_priv->display.fdi_link_train = gen6_fdi_link_train; 7594 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
7595 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7561 } else if (IS_IVYBRIDGE(dev)) { 7596 } else if (IS_IVYBRIDGE(dev)) {
7562 /* FIXME: detect B0+ stepping and use auto training */ 7597 /* FIXME: detect B0+ stepping and use auto training */
7563 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; 7598 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
@@ -7568,6 +7603,8 @@ static void intel_init_display(struct drm_device *dev)
7568 "Disable CxSR\n"); 7603 "Disable CxSR\n");
7569 dev_priv->display.update_wm = NULL; 7604 dev_priv->display.update_wm = NULL;
7570 } 7605 }
7606 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7607
7571 } else 7608 } else
7572 dev_priv->display.update_wm = NULL; 7609 dev_priv->display.update_wm = NULL;
7573 } else if (IS_PINEVIEW(dev)) { 7610 } else if (IS_PINEVIEW(dev)) {
@@ -7585,18 +7622,30 @@ static void intel_init_display(struct drm_device *dev)
7585 dev_priv->display.update_wm = NULL; 7622 dev_priv->display.update_wm = NULL;
7586 } else 7623 } else
7587 dev_priv->display.update_wm = pineview_update_wm; 7624 dev_priv->display.update_wm = pineview_update_wm;
7588 } else if (IS_G4X(dev)) 7625 } else if (IS_G4X(dev)) {
7589 dev_priv->display.update_wm = g4x_update_wm; 7626 dev_priv->display.update_wm = g4x_update_wm;
7590 else if (IS_GEN4(dev)) 7627 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7628 } else if (IS_GEN4(dev)) {
7591 dev_priv->display.update_wm = i965_update_wm; 7629 dev_priv->display.update_wm = i965_update_wm;
7592 else if (IS_GEN3(dev)) { 7630 if (IS_CRESTLINE(dev))
7631 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7632 else if (IS_BROADWATER(dev))
7633 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7634 } else if (IS_GEN3(dev)) {
7593 dev_priv->display.update_wm = i9xx_update_wm; 7635 dev_priv->display.update_wm = i9xx_update_wm;
7594 dev_priv->display.get_fifo_size = i9xx_get_fifo_size; 7636 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7637 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7638 } else if (IS_I865G(dev)) {
7639 dev_priv->display.update_wm = i830_update_wm;
7640 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7641 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7595 } else if (IS_I85X(dev)) { 7642 } else if (IS_I85X(dev)) {
7596 dev_priv->display.update_wm = i9xx_update_wm; 7643 dev_priv->display.update_wm = i9xx_update_wm;
7597 dev_priv->display.get_fifo_size = i85x_get_fifo_size; 7644 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
7645 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7598 } else { 7646 } else {
7599 dev_priv->display.update_wm = i830_update_wm; 7647 dev_priv->display.update_wm = i830_update_wm;
7648 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7600 if (IS_845G(dev)) 7649 if (IS_845G(dev))
7601 dev_priv->display.get_fifo_size = i845_get_fifo_size; 7650 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7602 else 7651 else
@@ -7726,7 +7775,7 @@ void intel_modeset_init(struct drm_device *dev)
7726 i915_disable_vga(dev); 7775 i915_disable_vga(dev);
7727 intel_setup_outputs(dev); 7776 intel_setup_outputs(dev);
7728 7777
7729 intel_enable_clock_gating(dev); 7778 dev_priv->display.init_clock_gating(dev);
7730 7779
7731 if (IS_IRONLAKE_M(dev)) { 7780 if (IS_IRONLAKE_M(dev)) {
7732 ironlake_enable_drps(dev); 7781 ironlake_enable_drps(dev);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-12 21:48:14 -0500