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-rw-r--r--Documentation/devicetree/bindings/mfd/da9063.txt93
-rw-r--r--Documentation/devicetree/bindings/mfd/qcom-rpm.txt70
-rw-r--r--drivers/mfd/88pm860x-core.c2
-rw-r--r--drivers/mfd/Kconfig39
-rw-r--r--drivers/mfd/Makefile4
-rw-r--r--drivers/mfd/da9063-core.c2
-rw-r--r--drivers/mfd/da9063-i2c.c9
-rw-r--r--drivers/mfd/da9150-core.c413
-rw-r--r--drivers/mfd/davinci_voicecodec.c2
-rw-r--r--drivers/mfd/db8500-prcmu.c9
-rw-r--r--drivers/mfd/dln2.c71
-rw-r--r--drivers/mfd/hi6421-pmic-core.c2
-rw-r--r--drivers/mfd/intel_soc_pmic_core.c3
-rw-r--r--drivers/mfd/intel_soc_pmic_core.h2
-rw-r--r--drivers/mfd/intel_soc_pmic_crc.c2
-rw-r--r--drivers/mfd/lm3533-core.c2
-rw-r--r--drivers/mfd/lpc_sch.c1
-rw-r--r--drivers/mfd/max77686.c29
-rw-r--r--drivers/mfd/mc13xxx-i2c.c2
-rw-r--r--drivers/mfd/mc13xxx-spi.c2
-rw-r--r--drivers/mfd/omap-usb-host.c10
-rw-r--r--drivers/mfd/pcf50633-core.c2
-rw-r--r--drivers/mfd/qcom_rpm.c581
-rw-r--r--drivers/mfd/retu-mfd.c2
-rw-r--r--drivers/mfd/rt5033.c142
-rw-r--r--drivers/mfd/rtsx_usb.c18
-rw-r--r--drivers/mfd/smsc-ece1099.c2
-rw-r--r--drivers/mfd/sun6i-prcm.c14
-rw-r--r--drivers/mfd/tps65217.c2
-rw-r--r--drivers/mfd/tps65218.c2
-rw-r--r--drivers/mfd/twl-core.c8
-rw-r--r--drivers/mfd/twl6040.c4
-rw-r--r--drivers/mfd/wm8994-core.c6
-rw-r--r--drivers/regulator/qcom_rpm-regulator.c1
-rw-r--r--include/dt-bindings/mfd/qcom-rpm.h154
-rw-r--r--include/linux/mfd/axp20x.h43
-rw-r--r--include/linux/mfd/da9063/core.h1
-rw-r--r--include/linux/mfd/da9150/core.h68
-rw-r--r--include/linux/mfd/da9150/registers.h1155
-rw-r--r--include/linux/mfd/max77686-private.h1
-rw-r--r--include/linux/mfd/max77686.h28
-rw-r--r--include/linux/mfd/qcom_rpm.h13
-rw-r--r--include/linux/mfd/rt5033-private.h260
-rw-r--r--include/linux/mfd/rt5033.h62
44 files changed, 3229 insertions, 109 deletions
diff --git a/Documentation/devicetree/bindings/mfd/da9063.txt b/Documentation/devicetree/bindings/mfd/da9063.txt
new file mode 100644
index 000000000000..42c6fa6f1c9a
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/da9063.txt
@@ -0,0 +1,93 @@
1* Dialog DA9063 Power Management Integrated Circuit (PMIC)
2
3DA9093 consists of a large and varied group of sub-devices (I2C Only):
4
5Device Supply Names Description
6------ ------------ -----------
7da9063-regulator : : LDOs & BUCKs
8da9063-rtc : : Real-Time Clock
9da9063-watchdog : : Watchdog
10
11======
12
13Required properties:
14
15- compatible : Should be "dlg,da9063"
16- reg : Specifies the I2C slave address (this defaults to 0x58 but it can be
17 modified to match the chip's OTP settings).
18- interrupt-parent : Specifies the reference to the interrupt controller for
19 the DA9063.
20- interrupts : IRQ line information.
21- interrupt-controller
22
23Sub-nodes:
24
25- regulators : This node defines the settings for the LDOs and BUCKs. The
26 DA9063 regulators are bound using their names listed below:
27
28 bcore1 : BUCK CORE1
29 bcore2 : BUCK CORE2
30 bpro : BUCK PRO
31 bmem : BUCK MEM
32 bio : BUCK IO
33 bperi : BUCK PERI
34 ldo1 : LDO_1
35 ldo2 : LDO_2
36 ldo3 : LDO_3
37 ldo4 : LDO_4
38 ldo5 : LDO_5
39 ldo6 : LDO_6
40 ldo7 : LDO_7
41 ldo8 : LDO_8
42 ldo9 : LDO_9
43 ldo10 : LDO_10
44 ldo11 : LDO_11
45
46 The component follows the standard regulator framework and the bindings
47 details of individual regulator device can be found in:
48 Documentation/devicetree/bindings/regulator/regulator.txt
49
50- rtc : This node defines settings for the Real-Time Clock associated with
51 the DA9063. There are currently no entries in this binding, however
52 compatible = "dlg,da9063-rtc" should be added if a node is created.
53
54- watchdog : This node defines settings for the Watchdog timer associated
55 with the DA9063. There are currently no entries in this binding, however
56 compatible = "dlg,da9063-watchdog" should be added if a node is created.
57
58
59Example:
60
61 pmic0: da9063@58 {
62 compatible = "dlg,da9063"
63 reg = <0x58>;
64 interrupt-parent = <&gpio6>;
65 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
66 interrupt-controller;
67
68 rtc {
69 compatible = "dlg,da9063-rtc";
70 };
71
72 wdt {
73 compatible = "dlg,da9063-watchdog";
74 };
75
76 regulators {
77 DA9063_BCORE1: bcore1 {
78 regulator-name = "BCORE1";
79 regulator-min-microvolt = <300000>;
80 regulator-max-microvolt = <1570000>;
81 regulator-min-microamp = <500000>;
82 regulator-max-microamp = <2000000>;
83 regulator-boot-on;
84 };
85 DA9063_LDO11: ldo11 {
86 regulator-name = "LDO_11";
87 regulator-min-microvolt = <900000>;
88 regulator-max-microvolt = <3600000>;
89 regulator-boot-on;
90 };
91 };
92 };
93
diff --git a/Documentation/devicetree/bindings/mfd/qcom-rpm.txt b/Documentation/devicetree/bindings/mfd/qcom-rpm.txt
new file mode 100644
index 000000000000..85e31980017a
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/qcom-rpm.txt
@@ -0,0 +1,70 @@
1Qualcomm Resource Power Manager (RPM)
2
3This driver is used to interface with the Resource Power Manager (RPM) found in
4various Qualcomm platforms. The RPM allows each component in the system to vote
5for state of the system resources, such as clocks, regulators and bus
6frequencies.
7
8- compatible:
9 Usage: required
10 Value type: <string>
11 Definition: must be one of:
12 "qcom,rpm-apq8064"
13 "qcom,rpm-msm8660"
14 "qcom,rpm-msm8960"
15
16- reg:
17 Usage: required
18 Value type: <prop-encoded-array>
19 Definition: base address and size of the RPM's message ram
20
21- interrupts:
22 Usage: required
23 Value type: <prop-encoded-array>
24 Definition: three entries specifying the RPM's:
25 1. acknowledgement interrupt
26 2. error interrupt
27 3. wakeup interrupt
28
29- interrupt-names:
30 Usage: required
31 Value type: <string-array>
32 Definition: must be the three strings "ack", "err" and "wakeup", in order
33
34- #address-cells:
35 Usage: required
36 Value type: <u32>
37 Definition: must be 1
38
39- #size-cells:
40 Usage: required
41 Value type: <u32>
42 Definition: must be 0
43
44- qcom,ipc:
45 Usage: required
46 Value type: <prop-encoded-array>
47
48 Definition: three entries specifying the outgoing ipc bit used for
49 signaling the RPM:
50 - phandle to a syscon node representing the apcs registers
51 - u32 representing offset to the register within the syscon
52 - u32 representing the ipc bit within the register
53
54
55= EXAMPLE
56
57 #include <dt-bindings/mfd/qcom-rpm.h>
58
59 rpm@108000 {
60 compatible = "qcom,rpm-msm8960";
61 reg = <0x108000 0x1000>;
62 qcom,ipc = <&apcs 0x8 2>;
63
64 interrupts = <0 19 0>, <0 21 0>, <0 22 0>;
65 interrupt-names = "ack", "err", "wakeup";
66
67 #address-cells = <1>;
68 #size-cells = <0>;
69 };
70
diff --git a/drivers/mfd/88pm860x-core.c b/drivers/mfd/88pm860x-core.c
index 3a2604580164..d2a85cde68da 100644
--- a/drivers/mfd/88pm860x-core.c
+++ b/drivers/mfd/88pm860x-core.c
@@ -1111,7 +1111,7 @@ static int verify_addr(struct i2c_client *i2c)
1111 return 0; 1111 return 0;
1112} 1112}
1113 1113
1114static struct regmap_config pm860x_regmap_config = { 1114static const struct regmap_config pm860x_regmap_config = {
1115 .reg_bits = 8, 1115 .reg_bits = 8,
1116 .val_bits = 8, 1116 .val_bits = 8,
1117}; 1117};
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 2e6b7311fabc..38356e39adba 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -195,6 +195,18 @@ config MFD_DA9063
195 Additional drivers must be enabled in order to use the functionality 195 Additional drivers must be enabled in order to use the functionality
196 of the device. 196 of the device.
197 197
198config MFD_DA9150
199 tristate "Dialog Semiconductor DA9150 Charger Fuel-Gauge chip"
200 depends on I2C=y
201 select MFD_CORE
202 select REGMAP_I2C
203 select REGMAP_IRQ
204 help
205 This adds support for the DA9150 integrated charger and fuel-gauge
206 chip. This driver provides common support for accessing the device.
207 Additional drivers must be enabled in order to use the specific
208 features of the device.
209
198config MFD_DLN2 210config MFD_DLN2
199 tristate "Diolan DLN2 support" 211 tristate "Diolan DLN2 support"
200 select MFD_CORE 212 select MFD_CORE
@@ -417,6 +429,7 @@ config MFD_MAX14577
417config MFD_MAX77686 429config MFD_MAX77686
418 bool "Maxim Semiconductor MAX77686/802 PMIC Support" 430 bool "Maxim Semiconductor MAX77686/802 PMIC Support"
419 depends on I2C=y 431 depends on I2C=y
432 depends on OF
420 select MFD_CORE 433 select MFD_CORE
421 select REGMAP_I2C 434 select REGMAP_I2C
422 select REGMAP_IRQ 435 select REGMAP_IRQ
@@ -589,6 +602,20 @@ config MFD_PM8921_CORE
589 Say M here if you want to include support for PM8921 chip as a module. 602 Say M here if you want to include support for PM8921 chip as a module.
590 This will build a module called "pm8921-core". 603 This will build a module called "pm8921-core".
591 604
605config MFD_QCOM_RPM
606 tristate "Qualcomm Resource Power Manager (RPM)"
607 depends on ARCH_QCOM && OF
608 help
609 If you say yes to this option, support will be included for the
610 Resource Power Manager system found in the Qualcomm 8660, 8960 and
611 8064 based devices.
612
613 This is required to access many regulators, clocks and bus
614 frequencies controlled by the RPM on these devices.
615
616 Say M here if you want to include support for the Qualcomm RPM as a
617 module. This will build a module called "qcom_rpm".
618
592config MFD_SPMI_PMIC 619config MFD_SPMI_PMIC
593 tristate "Qualcomm SPMI PMICs" 620 tristate "Qualcomm SPMI PMICs"
594 depends on ARCH_QCOM || COMPILE_TEST 621 depends on ARCH_QCOM || COMPILE_TEST
@@ -623,6 +650,18 @@ config MFD_RTSX_PCI
623 types of memory cards, such as Memory Stick, Memory Stick Pro, 650 types of memory cards, such as Memory Stick, Memory Stick Pro,
624 Secure Digital and MultiMediaCard. 651 Secure Digital and MultiMediaCard.
625 652
653config MFD_RT5033
654 tristate "Richtek RT5033 Power Management IC"
655 depends on I2C=y
656 select MFD_CORE
657 select REGMAP_I2C
658 help
659 This driver provides for the Richtek RT5033 Power Management IC,
660 which includes the I2C driver and the Core APIs. This driver provides
661 common support for accessing the device. The device supports multiple
662 sub-devices like charger, fuel gauge, flash LED, current source,
663 LDO and Buck.
664
626config MFD_RTSX_USB 665config MFD_RTSX_USB
627 tristate "Realtek USB card reader" 666 tristate "Realtek USB card reader"
628 depends on USB 667 depends on USB
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 53467e211381..19f3d744e3bd 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -113,7 +113,7 @@ obj-$(CONFIG_MFD_DA9055) += da9055.o
113 113
114da9063-objs := da9063-core.o da9063-irq.o da9063-i2c.o 114da9063-objs := da9063-core.o da9063-irq.o da9063-i2c.o
115obj-$(CONFIG_MFD_DA9063) += da9063.o 115obj-$(CONFIG_MFD_DA9063) += da9063.o
116 116obj-$(CONFIG_MFD_DA9150) += da9150-core.o
117obj-$(CONFIG_MFD_MAX14577) += max14577.o 117obj-$(CONFIG_MFD_MAX14577) += max14577.o
118obj-$(CONFIG_MFD_MAX77686) += max77686.o 118obj-$(CONFIG_MFD_MAX77686) += max77686.o
119obj-$(CONFIG_MFD_MAX77693) += max77693.o 119obj-$(CONFIG_MFD_MAX77693) += max77693.o
@@ -153,6 +153,7 @@ obj-$(CONFIG_MFD_SI476X_CORE) += si476x-core.o
153obj-$(CONFIG_MFD_CS5535) += cs5535-mfd.o 153obj-$(CONFIG_MFD_CS5535) += cs5535-mfd.o
154obj-$(CONFIG_MFD_OMAP_USB_HOST) += omap-usb-host.o omap-usb-tll.o 154obj-$(CONFIG_MFD_OMAP_USB_HOST) += omap-usb-host.o omap-usb-tll.o
155obj-$(CONFIG_MFD_PM8921_CORE) += pm8921-core.o ssbi.o 155obj-$(CONFIG_MFD_PM8921_CORE) += pm8921-core.o ssbi.o
156obj-$(CONFIG_MFD_QCOM_RPM) += qcom_rpm.o
156obj-$(CONFIG_MFD_SPMI_PMIC) += qcom-spmi-pmic.o 157obj-$(CONFIG_MFD_SPMI_PMIC) += qcom-spmi-pmic.o
157obj-$(CONFIG_TPS65911_COMPARATOR) += tps65911-comparator.o 158obj-$(CONFIG_TPS65911_COMPARATOR) += tps65911-comparator.o
158obj-$(CONFIG_MFD_TPS65090) += tps65090.o 159obj-$(CONFIG_MFD_TPS65090) += tps65090.o
@@ -176,6 +177,7 @@ obj-$(CONFIG_MFD_IPAQ_MICRO) += ipaq-micro.o
176obj-$(CONFIG_MFD_MENF21BMC) += menf21bmc.o 177obj-$(CONFIG_MFD_MENF21BMC) += menf21bmc.o
177obj-$(CONFIG_MFD_HI6421_PMIC) += hi6421-pmic-core.o 178obj-$(CONFIG_MFD_HI6421_PMIC) += hi6421-pmic-core.o
178obj-$(CONFIG_MFD_DLN2) += dln2.o 179obj-$(CONFIG_MFD_DLN2) += dln2.o
180obj-$(CONFIG_MFD_RT5033) += rt5033.o
179 181
180intel-soc-pmic-objs := intel_soc_pmic_core.o intel_soc_pmic_crc.o 182intel-soc-pmic-objs := intel_soc_pmic_core.o intel_soc_pmic_crc.o
181obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o 183obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
diff --git a/drivers/mfd/da9063-core.c b/drivers/mfd/da9063-core.c
index f38bc98a3c57..facd3610ac77 100644
--- a/drivers/mfd/da9063-core.c
+++ b/drivers/mfd/da9063-core.c
@@ -86,6 +86,7 @@ static const struct mfd_cell da9063_devs[] = {
86 }, 86 },
87 { 87 {
88 .name = DA9063_DRVNAME_WATCHDOG, 88 .name = DA9063_DRVNAME_WATCHDOG,
89 .of_compatible = "dlg,da9063-watchdog",
89 }, 90 },
90 { 91 {
91 .name = DA9063_DRVNAME_HWMON, 92 .name = DA9063_DRVNAME_HWMON,
@@ -101,6 +102,7 @@ static const struct mfd_cell da9063_devs[] = {
101 .name = DA9063_DRVNAME_RTC, 102 .name = DA9063_DRVNAME_RTC,
102 .num_resources = ARRAY_SIZE(da9063_rtc_resources), 103 .num_resources = ARRAY_SIZE(da9063_rtc_resources),
103 .resources = da9063_rtc_resources, 104 .resources = da9063_rtc_resources,
105 .of_compatible = "dlg,da9063-rtc",
104 }, 106 },
105 { 107 {
106 .name = DA9063_DRVNAME_VIBRATION, 108 .name = DA9063_DRVNAME_VIBRATION,
diff --git a/drivers/mfd/da9063-i2c.c b/drivers/mfd/da9063-i2c.c
index 21fd8d9a217b..6f3a7c0001f9 100644
--- a/drivers/mfd/da9063-i2c.c
+++ b/drivers/mfd/da9063-i2c.c
@@ -25,6 +25,9 @@
25#include <linux/mfd/da9063/pdata.h> 25#include <linux/mfd/da9063/pdata.h>
26#include <linux/mfd/da9063/registers.h> 26#include <linux/mfd/da9063/registers.h>
27 27
28#include <linux/of.h>
29#include <linux/regulator/of_regulator.h>
30
28static const struct regmap_range da9063_ad_readable_ranges[] = { 31static const struct regmap_range da9063_ad_readable_ranges[] = {
29 { 32 {
30 .range_min = DA9063_REG_PAGE_CON, 33 .range_min = DA9063_REG_PAGE_CON,
@@ -203,6 +206,11 @@ static struct regmap_config da9063_regmap_config = {
203 .cache_type = REGCACHE_RBTREE, 206 .cache_type = REGCACHE_RBTREE,
204}; 207};
205 208
209static const struct of_device_id da9063_dt_ids[] = {
210 { .compatible = "dlg,da9063", },
211 { }
212};
213MODULE_DEVICE_TABLE(of, da9063_dt_ids);
206static int da9063_i2c_probe(struct i2c_client *i2c, 214static int da9063_i2c_probe(struct i2c_client *i2c,
207 const struct i2c_device_id *id) 215 const struct i2c_device_id *id)
208{ 216{
@@ -257,6 +265,7 @@ static struct i2c_driver da9063_i2c_driver = {
257 .driver = { 265 .driver = {
258 .name = "da9063", 266 .name = "da9063",
259 .owner = THIS_MODULE, 267 .owner = THIS_MODULE,
268 .of_match_table = of_match_ptr(da9063_dt_ids),
260 }, 269 },
261 .probe = da9063_i2c_probe, 270 .probe = da9063_i2c_probe,
262 .remove = da9063_i2c_remove, 271 .remove = da9063_i2c_remove,
diff --git a/drivers/mfd/da9150-core.c b/drivers/mfd/da9150-core.c
new file mode 100644
index 000000000000..4d757b97ef9a
--- /dev/null
+++ b/drivers/mfd/da9150-core.c
@@ -0,0 +1,413 @@
1/*
2 * DA9150 Core MFD Driver
3 *
4 * Copyright (c) 2014 Dialog Semiconductor
5 *
6 * Author: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/platform_device.h>
17#include <linux/i2c.h>
18#include <linux/regmap.h>
19#include <linux/slab.h>
20#include <linux/irq.h>
21#include <linux/interrupt.h>
22#include <linux/mfd/core.h>
23#include <linux/mfd/da9150/core.h>
24#include <linux/mfd/da9150/registers.h>
25
26static bool da9150_volatile_reg(struct device *dev, unsigned int reg)
27{
28 switch (reg) {
29 case DA9150_PAGE_CON:
30 case DA9150_STATUS_A:
31 case DA9150_STATUS_B:
32 case DA9150_STATUS_C:
33 case DA9150_STATUS_D:
34 case DA9150_STATUS_E:
35 case DA9150_STATUS_F:
36 case DA9150_STATUS_G:
37 case DA9150_STATUS_H:
38 case DA9150_STATUS_I:
39 case DA9150_STATUS_J:
40 case DA9150_STATUS_K:
41 case DA9150_STATUS_L:
42 case DA9150_STATUS_N:
43 case DA9150_FAULT_LOG_A:
44 case DA9150_FAULT_LOG_B:
45 case DA9150_EVENT_E:
46 case DA9150_EVENT_F:
47 case DA9150_EVENT_G:
48 case DA9150_EVENT_H:
49 case DA9150_CONTROL_B:
50 case DA9150_CONTROL_C:
51 case DA9150_GPADC_MAN:
52 case DA9150_GPADC_RES_A:
53 case DA9150_GPADC_RES_B:
54 case DA9150_ADETVB_CFG_C:
55 case DA9150_ADETD_STAT:
56 case DA9150_ADET_CMPSTAT:
57 case DA9150_ADET_CTRL_A:
58 case DA9150_PPR_TCTR_B:
59 case DA9150_COREBTLD_STAT_A:
60 case DA9150_CORE_DATA_A:
61 case DA9150_CORE_DATA_B:
62 case DA9150_CORE_DATA_C:
63 case DA9150_CORE_DATA_D:
64 case DA9150_CORE2WIRE_STAT_A:
65 case DA9150_FW_CTRL_C:
66 case DA9150_FG_CTRL_B:
67 case DA9150_FW_CTRL_B:
68 case DA9150_GPADC_CMAN:
69 case DA9150_GPADC_CRES_A:
70 case DA9150_GPADC_CRES_B:
71 case DA9150_CC_ICHG_RES_A:
72 case DA9150_CC_ICHG_RES_B:
73 case DA9150_CC_IAVG_RES_A:
74 case DA9150_CC_IAVG_RES_B:
75 case DA9150_TAUX_CTRL_A:
76 case DA9150_TAUX_VALUE_H:
77 case DA9150_TAUX_VALUE_L:
78 case DA9150_TBAT_RES_A:
79 case DA9150_TBAT_RES_B:
80 return true;
81 default:
82 return false;
83 }
84}
85
86static const struct regmap_range_cfg da9150_range_cfg[] = {
87 {
88 .range_min = DA9150_PAGE_CON,
89 .range_max = DA9150_TBAT_RES_B,
90 .selector_reg = DA9150_PAGE_CON,
91 .selector_mask = DA9150_I2C_PAGE_MASK,
92 .selector_shift = DA9150_I2C_PAGE_SHIFT,
93 .window_start = 0,
94 .window_len = 256,
95 },
96};
97
98static struct regmap_config da9150_regmap_config = {
99 .reg_bits = 8,
100 .val_bits = 8,
101 .ranges = da9150_range_cfg,
102 .num_ranges = ARRAY_SIZE(da9150_range_cfg),
103 .max_register = DA9150_TBAT_RES_B,
104
105 .cache_type = REGCACHE_RBTREE,
106
107 .volatile_reg = da9150_volatile_reg,
108};
109
110u8 da9150_reg_read(struct da9150 *da9150, u16 reg)
111{
112 int val, ret;
113
114 ret = regmap_read(da9150->regmap, reg, &val);
115 if (ret)
116 dev_err(da9150->dev, "Failed to read from reg 0x%x: %d\n",
117 reg, ret);
118
119 return (u8) val;
120}
121EXPORT_SYMBOL_GPL(da9150_reg_read);
122
123void da9150_reg_write(struct da9150 *da9150, u16 reg, u8 val)
124{
125 int ret;
126
127 ret = regmap_write(da9150->regmap, reg, val);
128 if (ret)
129 dev_err(da9150->dev, "Failed to write to reg 0x%x: %d\n",
130 reg, ret);
131}
132EXPORT_SYMBOL_GPL(da9150_reg_write);
133
134void da9150_set_bits(struct da9150 *da9150, u16 reg, u8 mask, u8 val)
135{
136 int ret;
137
138 ret = regmap_update_bits(da9150->regmap, reg, mask, val);
139 if (ret)
140 dev_err(da9150->dev, "Failed to set bits in reg 0x%x: %d\n",
141 reg, ret);
142}
143EXPORT_SYMBOL_GPL(da9150_set_bits);
144
145void da9150_bulk_read(struct da9150 *da9150, u16 reg, int count, u8 *buf)
146{
147 int ret;
148
149 ret = regmap_bulk_read(da9150->regmap, reg, buf, count);
150 if (ret)
151 dev_err(da9150->dev, "Failed to bulk read from reg 0x%x: %d\n",
152 reg, ret);
153}
154EXPORT_SYMBOL_GPL(da9150_bulk_read);
155
156void da9150_bulk_write(struct da9150 *da9150, u16 reg, int count, const u8 *buf)
157{
158 int ret;
159
160 ret = regmap_raw_write(da9150->regmap, reg, buf, count);
161 if (ret)
162 dev_err(da9150->dev, "Failed to bulk write to reg 0x%x %d\n",
163 reg, ret);
164}
165EXPORT_SYMBOL_GPL(da9150_bulk_write);
166
167static struct regmap_irq da9150_irqs[] = {
168 [DA9150_IRQ_VBUS] = {
169 .reg_offset = 0,
170 .mask = DA9150_E_VBUS_MASK,
171 },
172 [DA9150_IRQ_CHG] = {
173 .reg_offset = 0,
174 .mask = DA9150_E_CHG_MASK,
175 },
176 [DA9150_IRQ_TCLASS] = {
177 .reg_offset = 0,
178 .mask = DA9150_E_TCLASS_MASK,
179 },
180 [DA9150_IRQ_TJUNC] = {
181 .reg_offset = 0,
182 .mask = DA9150_E_TJUNC_MASK,
183 },
184 [DA9150_IRQ_VFAULT] = {
185 .reg_offset = 0,
186 .mask = DA9150_E_VFAULT_MASK,
187 },
188 [DA9150_IRQ_CONF] = {
189 .reg_offset = 1,
190 .mask = DA9150_E_CONF_MASK,
191 },
192 [DA9150_IRQ_DAT] = {
193 .reg_offset = 1,
194 .mask = DA9150_E_DAT_MASK,
195 },
196 [DA9150_IRQ_DTYPE] = {
197 .reg_offset = 1,
198 .mask = DA9150_E_DTYPE_MASK,
199 },
200 [DA9150_IRQ_ID] = {
201 .reg_offset = 1,
202 .mask = DA9150_E_ID_MASK,
203 },
204 [DA9150_IRQ_ADP] = {
205 .reg_offset = 1,
206 .mask = DA9150_E_ADP_MASK,
207 },
208 [DA9150_IRQ_SESS_END] = {
209 .reg_offset = 1,
210 .mask = DA9150_E_SESS_END_MASK,
211 },
212 [DA9150_IRQ_SESS_VLD] = {
213 .reg_offset = 1,
214 .mask = DA9150_E_SESS_VLD_MASK,
215 },
216 [DA9150_IRQ_FG] = {
217 .reg_offset = 2,
218 .mask = DA9150_E_FG_MASK,
219 },
220 [DA9150_IRQ_GP] = {
221 .reg_offset = 2,
222 .mask = DA9150_E_GP_MASK,
223 },
224 [DA9150_IRQ_TBAT] = {
225 .reg_offset = 2,
226 .mask = DA9150_E_TBAT_MASK,
227 },
228 [DA9150_IRQ_GPIOA] = {
229 .reg_offset = 2,
230 .mask = DA9150_E_GPIOA_MASK,
231 },
232 [DA9150_IRQ_GPIOB] = {
233 .reg_offset = 2,
234 .mask = DA9150_E_GPIOB_MASK,
235 },
236 [DA9150_IRQ_GPIOC] = {
237 .reg_offset = 2,
238 .mask = DA9150_E_GPIOC_MASK,
239 },
240 [DA9150_IRQ_GPIOD] = {
241 .reg_offset = 2,
242 .mask = DA9150_E_GPIOD_MASK,
243 },
244 [DA9150_IRQ_GPADC] = {
245 .reg_offset = 2,
246 .mask = DA9150_E_GPADC_MASK,
247 },
248 [DA9150_IRQ_WKUP] = {
249 .reg_offset = 3,
250 .mask = DA9150_E_WKUP_MASK,
251 },
252};
253
254static struct regmap_irq_chip da9150_regmap_irq_chip = {
255 .name = "da9150_irq",
256 .status_base = DA9150_EVENT_E,
257 .mask_base = DA9150_IRQ_MASK_E,
258 .ack_base = DA9150_EVENT_E,
259 .num_regs = DA9150_NUM_IRQ_REGS,
260 .irqs = da9150_irqs,
261 .num_irqs = ARRAY_SIZE(da9150_irqs),
262};
263
264static struct resource da9150_gpadc_resources[] = {
265 {
266 .name = "GPADC",
267 .start = DA9150_IRQ_GPADC,
268 .end = DA9150_IRQ_GPADC,
269 .flags = IORESOURCE_IRQ,
270 },
271};
272
273static struct resource da9150_charger_resources[] = {
274 {
275 .name = "CHG_STATUS",
276 .start = DA9150_IRQ_CHG,
277 .end = DA9150_IRQ_CHG,
278 .flags = IORESOURCE_IRQ,
279 },
280 {
281 .name = "CHG_TJUNC",
282 .start = DA9150_IRQ_TJUNC,
283 .end = DA9150_IRQ_TJUNC,
284 .flags = IORESOURCE_IRQ,
285 },
286 {
287 .name = "CHG_VFAULT",
288 .start = DA9150_IRQ_VFAULT,
289 .end = DA9150_IRQ_VFAULT,
290 .flags = IORESOURCE_IRQ,
291 },
292 {
293 .name = "CHG_VBUS",
294 .start = DA9150_IRQ_VBUS,
295 .end = DA9150_IRQ_VBUS,
296 .flags = IORESOURCE_IRQ,
297 },
298};
299
300static struct mfd_cell da9150_devs[] = {
301 {
302 .name = "da9150-gpadc",
303 .of_compatible = "dlg,da9150-gpadc",
304 .resources = da9150_gpadc_resources,
305 .num_resources = ARRAY_SIZE(da9150_gpadc_resources),
306 },
307 {
308 .name = "da9150-charger",
309 .of_compatible = "dlg,da9150-charger",
310 .resources = da9150_charger_resources,
311 .num_resources = ARRAY_SIZE(da9150_charger_resources),
312 },
313};
314
315static int da9150_probe(struct i2c_client *client,
316 const struct i2c_device_id *id)
317{
318 struct da9150 *da9150;
319 struct da9150_pdata *pdata = dev_get_platdata(&client->dev);
320 int ret;
321
322 da9150 = devm_kzalloc(&client->dev, sizeof(*da9150), GFP_KERNEL);
323 if (!da9150)
324 return -ENOMEM;
325
326 da9150->dev = &client->dev;
327 da9150->irq = client->irq;
328 i2c_set_clientdata(client, da9150);
329
330 da9150->regmap = devm_regmap_init_i2c(client, &da9150_regmap_config);
331 if (IS_ERR(da9150->regmap)) {
332 ret = PTR_ERR(da9150->regmap);
333 dev_err(da9150->dev, "Failed to allocate register map: %d\n",
334 ret);
335 return ret;
336 }
337
338 da9150->irq_base = pdata ? pdata->irq_base : -1;
339
340 ret = regmap_add_irq_chip(da9150->regmap, da9150->irq,
341 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
342 da9150->irq_base, &da9150_regmap_irq_chip,
343 &da9150->regmap_irq_data);
344 if (ret)
345 return ret;
346
347 da9150->irq_base = regmap_irq_chip_get_base(da9150->regmap_irq_data);
348 enable_irq_wake(da9150->irq);
349
350 ret = mfd_add_devices(da9150->dev, -1, da9150_devs,
351 ARRAY_SIZE(da9150_devs), NULL,
352 da9150->irq_base, NULL);
353 if (ret) {
354 dev_err(da9150->dev, "Failed to add child devices: %d\n", ret);
355 regmap_del_irq_chip(da9150->irq, da9150->regmap_irq_data);
356 return ret;
357 }
358
359 return 0;
360}
361
362static int da9150_remove(struct i2c_client *client)
363{
364 struct da9150 *da9150 = i2c_get_clientdata(client);
365
366 regmap_del_irq_chip(da9150->irq, da9150->regmap_irq_data);
367 mfd_remove_devices(da9150->dev);
368
369 return 0;
370}
371
372static void da9150_shutdown(struct i2c_client *client)
373{
374 struct da9150 *da9150 = i2c_get_clientdata(client);
375
376 /* Make sure we have a wakup source for the device */
377 da9150_set_bits(da9150, DA9150_CONFIG_D,
378 DA9150_WKUP_PM_EN_MASK,
379 DA9150_WKUP_PM_EN_MASK);
380
381 /* Set device to DISABLED mode */
382 da9150_set_bits(da9150, DA9150_CONTROL_C,
383 DA9150_DISABLE_MASK, DA9150_DISABLE_MASK);
384}
385
386static const struct i2c_device_id da9150_i2c_id[] = {
387 { "da9150", },
388 { }
389};
390MODULE_DEVICE_TABLE(i2c, da9150_i2c_id);
391
392static const struct of_device_id da9150_of_match[] = {
393 { .compatible = "dlg,da9150", },
394 { }
395};
396MODULE_DEVICE_TABLE(of, da9150_of_match);
397
398static struct i2c_driver da9150_driver = {
399 .driver = {
400 .name = "da9150",
401 .of_match_table = of_match_ptr(da9150_of_match),
402 },
403 .probe = da9150_probe,
404 .remove = da9150_remove,
405 .shutdown = da9150_shutdown,
406 .id_table = da9150_i2c_id,
407};
408
409module_i2c_driver(da9150_driver);
410
411MODULE_DESCRIPTION("MFD Core Driver for DA9150");
412MODULE_AUTHOR("Adam Thomson <Adam.Thomson.Opensource@diasemi.com>");
413MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/davinci_voicecodec.c b/drivers/mfd/davinci_voicecodec.c
index c835e85539b2..9bbc642a7b9d 100644
--- a/drivers/mfd/davinci_voicecodec.c
+++ b/drivers/mfd/davinci_voicecodec.c
@@ -33,7 +33,7 @@
33 33
34#include <linux/mfd/davinci_voicecodec.h> 34#include <linux/mfd/davinci_voicecodec.h>
35 35
36static struct regmap_config davinci_vc_regmap = { 36static const struct regmap_config davinci_vc_regmap = {
37 .reg_bits = 32, 37 .reg_bits = 32,
38 .val_bits = 32, 38 .val_bits = 32,
39}; 39};
diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c
index 16162bf43656..cc1a404328c2 100644
--- a/drivers/mfd/db8500-prcmu.c
+++ b/drivers/mfd/db8500-prcmu.c
@@ -675,15 +675,6 @@ bool prcmu_has_arm_maxopp(void)
675} 675}
676 676
677/** 677/**
678 * prcmu_get_boot_status - PRCMU boot status checking
679 * Returns: the current PRCMU boot status
680 */
681int prcmu_get_boot_status(void)
682{
683 return readb(tcdm_base + PRCM_BOOT_STATUS);
684}
685
686/**
687 * prcmu_set_rc_a2p - This function is used to run few power state sequences 678 * prcmu_set_rc_a2p - This function is used to run few power state sequences
688 * @val: Value to be set, i.e. transition requested 679 * @val: Value to be set, i.e. transition requested
689 * Returns: 0 on success, -EINVAL on invalid argument 680 * Returns: 0 on success, -EINVAL on invalid argument
diff --git a/drivers/mfd/dln2.c b/drivers/mfd/dln2.c
index 6d49685d4ee4..1be9bd1c046d 100644
--- a/drivers/mfd/dln2.c
+++ b/drivers/mfd/dln2.c
@@ -587,12 +587,19 @@ static void dln2_free_rx_urbs(struct dln2_dev *dln2)
587 int i; 587 int i;
588 588
589 for (i = 0; i < DLN2_MAX_URBS; i++) { 589 for (i = 0; i < DLN2_MAX_URBS; i++) {
590 usb_kill_urb(dln2->rx_urb[i]);
591 usb_free_urb(dln2->rx_urb[i]); 590 usb_free_urb(dln2->rx_urb[i]);
592 kfree(dln2->rx_buf[i]); 591 kfree(dln2->rx_buf[i]);
593 } 592 }
594} 593}
595 594
595static void dln2_stop_rx_urbs(struct dln2_dev *dln2)
596{
597 int i;
598
599 for (i = 0; i < DLN2_MAX_URBS; i++)
600 usb_kill_urb(dln2->rx_urb[i]);
601}
602
596static void dln2_free(struct dln2_dev *dln2) 603static void dln2_free(struct dln2_dev *dln2)
597{ 604{
598 dln2_free_rx_urbs(dln2); 605 dln2_free_rx_urbs(dln2);
@@ -604,9 +611,7 @@ static int dln2_setup_rx_urbs(struct dln2_dev *dln2,
604 struct usb_host_interface *hostif) 611 struct usb_host_interface *hostif)
605{ 612{
606 int i; 613 int i;
607 int ret;
608 const int rx_max_size = DLN2_RX_BUF_SIZE; 614 const int rx_max_size = DLN2_RX_BUF_SIZE;
609 struct device *dev = &dln2->interface->dev;
610 615
611 for (i = 0; i < DLN2_MAX_URBS; i++) { 616 for (i = 0; i < DLN2_MAX_URBS; i++) {
612 dln2->rx_buf[i] = kmalloc(rx_max_size, GFP_KERNEL); 617 dln2->rx_buf[i] = kmalloc(rx_max_size, GFP_KERNEL);
@@ -620,8 +625,19 @@ static int dln2_setup_rx_urbs(struct dln2_dev *dln2,
620 usb_fill_bulk_urb(dln2->rx_urb[i], dln2->usb_dev, 625 usb_fill_bulk_urb(dln2->rx_urb[i], dln2->usb_dev,
621 usb_rcvbulkpipe(dln2->usb_dev, dln2->ep_in), 626 usb_rcvbulkpipe(dln2->usb_dev, dln2->ep_in),
622 dln2->rx_buf[i], rx_max_size, dln2_rx, dln2); 627 dln2->rx_buf[i], rx_max_size, dln2_rx, dln2);
628 }
623 629
624 ret = usb_submit_urb(dln2->rx_urb[i], GFP_KERNEL); 630 return 0;
631}
632
633static int dln2_start_rx_urbs(struct dln2_dev *dln2, gfp_t gfp)
634{
635 struct device *dev = &dln2->interface->dev;
636 int ret;
637 int i;
638
639 for (i = 0; i < DLN2_MAX_URBS; i++) {
640 ret = usb_submit_urb(dln2->rx_urb[i], gfp);
625 if (ret < 0) { 641 if (ret < 0) {
626 dev_err(dev, "failed to submit RX URB: %d\n", ret); 642 dev_err(dev, "failed to submit RX URB: %d\n", ret);
627 return ret; 643 return ret;
@@ -665,9 +681,8 @@ static const struct mfd_cell dln2_devs[] = {
665 }, 681 },
666}; 682};
667 683
668static void dln2_disconnect(struct usb_interface *interface) 684static void dln2_stop(struct dln2_dev *dln2)
669{ 685{
670 struct dln2_dev *dln2 = usb_get_intfdata(interface);
671 int i, j; 686 int i, j;
672 687
673 /* don't allow starting new transfers */ 688 /* don't allow starting new transfers */
@@ -696,6 +711,15 @@ static void dln2_disconnect(struct usb_interface *interface)
696 /* wait for transfers to end */ 711 /* wait for transfers to end */
697 wait_event(dln2->disconnect_wq, !dln2->active_transfers); 712 wait_event(dln2->disconnect_wq, !dln2->active_transfers);
698 713
714 dln2_stop_rx_urbs(dln2);
715}
716
717static void dln2_disconnect(struct usb_interface *interface)
718{
719 struct dln2_dev *dln2 = usb_get_intfdata(interface);
720
721 dln2_stop(dln2);
722
699 mfd_remove_devices(&interface->dev); 723 mfd_remove_devices(&interface->dev);
700 724
701 dln2_free(dln2); 725 dln2_free(dln2);
@@ -738,28 +762,53 @@ static int dln2_probe(struct usb_interface *interface,
738 762
739 ret = dln2_setup_rx_urbs(dln2, hostif); 763 ret = dln2_setup_rx_urbs(dln2, hostif);
740 if (ret) 764 if (ret)
741 goto out_cleanup; 765 goto out_free;
766
767 ret = dln2_start_rx_urbs(dln2, GFP_KERNEL);
768 if (ret)
769 goto out_stop_rx;
742 770
743 ret = dln2_hw_init(dln2); 771 ret = dln2_hw_init(dln2);
744 if (ret < 0) { 772 if (ret < 0) {
745 dev_err(dev, "failed to initialize hardware\n"); 773 dev_err(dev, "failed to initialize hardware\n");
746 goto out_cleanup; 774 goto out_stop_rx;
747 } 775 }
748 776
749 ret = mfd_add_hotplug_devices(dev, dln2_devs, ARRAY_SIZE(dln2_devs)); 777 ret = mfd_add_hotplug_devices(dev, dln2_devs, ARRAY_SIZE(dln2_devs));
750 if (ret != 0) { 778 if (ret != 0) {
751 dev_err(dev, "failed to add mfd devices to core\n"); 779 dev_err(dev, "failed to add mfd devices to core\n");
752 goto out_cleanup; 780 goto out_stop_rx;
753 } 781 }
754 782
755 return 0; 783 return 0;
756 784
757out_cleanup: 785out_stop_rx:
786 dln2_stop_rx_urbs(dln2);
787
788out_free:
758 dln2_free(dln2); 789 dln2_free(dln2);
759 790
760 return ret; 791 return ret;
761} 792}
762 793
794static int dln2_suspend(struct usb_interface *iface, pm_message_t message)
795{
796 struct dln2_dev *dln2 = usb_get_intfdata(iface);
797
798 dln2_stop(dln2);
799
800 return 0;
801}
802
803static int dln2_resume(struct usb_interface *iface)
804{
805 struct dln2_dev *dln2 = usb_get_intfdata(iface);
806
807 dln2->disconnect = false;
808
809 return dln2_start_rx_urbs(dln2, GFP_NOIO);
810}
811
763static const struct usb_device_id dln2_table[] = { 812static const struct usb_device_id dln2_table[] = {
764 { USB_DEVICE(0xa257, 0x2013) }, 813 { USB_DEVICE(0xa257, 0x2013) },
765 { } 814 { }
@@ -772,6 +821,8 @@ static struct usb_driver dln2_driver = {
772 .probe = dln2_probe, 821 .probe = dln2_probe,
773 .disconnect = dln2_disconnect, 822 .disconnect = dln2_disconnect,
774 .id_table = dln2_table, 823 .id_table = dln2_table,
824 .suspend = dln2_suspend,
825 .resume = dln2_resume,
775}; 826};
776 827
777module_usb_driver(dln2_driver); 828module_usb_driver(dln2_driver);
diff --git a/drivers/mfd/hi6421-pmic-core.c b/drivers/mfd/hi6421-pmic-core.c
index 321a2656fd00..7210ae28bf81 100644
--- a/drivers/mfd/hi6421-pmic-core.c
+++ b/drivers/mfd/hi6421-pmic-core.c
@@ -35,7 +35,7 @@ static const struct mfd_cell hi6421_devs[] = {
35 { .name = "hi6421-regulator", }, 35 { .name = "hi6421-regulator", },
36}; 36};
37 37
38static struct regmap_config hi6421_regmap_config = { 38static const struct regmap_config hi6421_regmap_config = {
39 .reg_bits = 32, 39 .reg_bits = 32,
40 .reg_stride = 4, 40 .reg_stride = 4,
41 .val_bits = 8, 41 .val_bits = 8,
diff --git a/drivers/mfd/intel_soc_pmic_core.c b/drivers/mfd/intel_soc_pmic_core.c
index df7b0642a5b4..80cef048b904 100644
--- a/drivers/mfd/intel_soc_pmic_core.c
+++ b/drivers/mfd/intel_soc_pmic_core.c
@@ -64,6 +64,9 @@ static int intel_soc_pmic_i2c_probe(struct i2c_client *i2c,
64 config = (struct intel_soc_pmic_config *)id->driver_data; 64 config = (struct intel_soc_pmic_config *)id->driver_data;
65 65
66 pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL); 66 pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
67 if (!pmic)
68 return -ENOMEM;
69
67 dev_set_drvdata(dev, pmic); 70 dev_set_drvdata(dev, pmic);
68 71
69 pmic->regmap = devm_regmap_init_i2c(i2c, config->regmap_config); 72 pmic->regmap = devm_regmap_init_i2c(i2c, config->regmap_config);
diff --git a/drivers/mfd/intel_soc_pmic_core.h b/drivers/mfd/intel_soc_pmic_core.h
index 33aacd9baddc..9498d6719847 100644
--- a/drivers/mfd/intel_soc_pmic_core.h
+++ b/drivers/mfd/intel_soc_pmic_core.h
@@ -23,7 +23,7 @@ struct intel_soc_pmic_config {
23 unsigned long irq_flags; 23 unsigned long irq_flags;
24 struct mfd_cell *cell_dev; 24 struct mfd_cell *cell_dev;
25 int n_cell_devs; 25 int n_cell_devs;
26 struct regmap_config *regmap_config; 26 const struct regmap_config *regmap_config;
27 struct regmap_irq_chip *irq_chip; 27 struct regmap_irq_chip *irq_chip;
28}; 28};
29 29
diff --git a/drivers/mfd/intel_soc_pmic_crc.c b/drivers/mfd/intel_soc_pmic_crc.c
index c85e2ecb868a..4cc1b324e971 100644
--- a/drivers/mfd/intel_soc_pmic_crc.c
+++ b/drivers/mfd/intel_soc_pmic_crc.c
@@ -111,7 +111,7 @@ static struct mfd_cell crystal_cove_dev[] = {
111 }, 111 },
112}; 112};
113 113
114static struct regmap_config crystal_cove_regmap_config = { 114static const struct regmap_config crystal_cove_regmap_config = {
115 .reg_bits = 8, 115 .reg_bits = 8,
116 .val_bits = 8, 116 .val_bits = 8,
117 117
diff --git a/drivers/mfd/lm3533-core.c b/drivers/mfd/lm3533-core.c
index 8c29f7b27324..d42fbb667d8c 100644
--- a/drivers/mfd/lm3533-core.c
+++ b/drivers/mfd/lm3533-core.c
@@ -583,7 +583,7 @@ static bool lm3533_precious_register(struct device *dev, unsigned int reg)
583 } 583 }
584} 584}
585 585
586static struct regmap_config regmap_config = { 586static const struct regmap_config regmap_config = {
587 .reg_bits = 8, 587 .reg_bits = 8,
588 .val_bits = 8, 588 .val_bits = 8,
589 .max_register = LM3533_REG_MAX, 589 .max_register = LM3533_REG_MAX,
diff --git a/drivers/mfd/lpc_sch.c b/drivers/mfd/lpc_sch.c
index 5c38df35a84d..a56e4ba5227b 100644
--- a/drivers/mfd/lpc_sch.c
+++ b/drivers/mfd/lpc_sch.c
@@ -75,6 +75,7 @@ static struct lpc_sch_info sch_chipset_info[] = {
75 [LPC_QUARK_X1000] = { 75 [LPC_QUARK_X1000] = {
76 .io_size_gpio = GPIO_IO_SIZE, 76 .io_size_gpio = GPIO_IO_SIZE,
77 .irq_gpio = GPIO_IRQ_QUARK_X1000, 77 .irq_gpio = GPIO_IRQ_QUARK_X1000,
78 .io_size_wdt = WDT_IO_SIZE,
78 }, 79 },
79}; 80};
80 81
diff --git a/drivers/mfd/max77686.c b/drivers/mfd/max77686.c
index 929795eae9fc..760d08d7923d 100644
--- a/drivers/mfd/max77686.c
+++ b/drivers/mfd/max77686.c
@@ -111,17 +111,17 @@ static bool max77802_is_volatile_reg(struct device *dev, unsigned int reg)
111 max77802_rtc_is_volatile_reg(dev, reg)); 111 max77802_rtc_is_volatile_reg(dev, reg));
112} 112}
113 113
114static struct regmap_config max77686_regmap_config = { 114static const struct regmap_config max77686_regmap_config = {
115 .reg_bits = 8, 115 .reg_bits = 8,
116 .val_bits = 8, 116 .val_bits = 8,
117}; 117};
118 118
119static struct regmap_config max77686_rtc_regmap_config = { 119static const struct regmap_config max77686_rtc_regmap_config = {
120 .reg_bits = 8, 120 .reg_bits = 8,
121 .val_bits = 8, 121 .val_bits = 8,
122}; 122};
123 123
124static struct regmap_config max77802_regmap_config = { 124static const struct regmap_config max77802_regmap_config = {
125 .reg_bits = 8, 125 .reg_bits = 8,
126 .val_bits = 8, 126 .val_bits = 8,
127 .writeable_reg = max77802_is_accessible_reg, 127 .writeable_reg = max77802_is_accessible_reg,
@@ -205,24 +205,10 @@ static const struct of_device_id max77686_pmic_dt_match[] = {
205 { }, 205 { },
206}; 206};
207 207
208static struct max77686_platform_data *max77686_i2c_parse_dt_pdata(struct device
209 *dev)
210{
211 struct max77686_platform_data *pd;
212
213 pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
214 if (!pd)
215 return NULL;
216
217 dev->platform_data = pd;
218 return pd;
219}
220
221static int max77686_i2c_probe(struct i2c_client *i2c, 208static int max77686_i2c_probe(struct i2c_client *i2c,
222 const struct i2c_device_id *id) 209 const struct i2c_device_id *id)
223{ 210{
224 struct max77686_dev *max77686 = NULL; 211 struct max77686_dev *max77686 = NULL;
225 struct max77686_platform_data *pdata = dev_get_platdata(&i2c->dev);
226 const struct of_device_id *match; 212 const struct of_device_id *match;
227 unsigned int data; 213 unsigned int data;
228 int ret = 0; 214 int ret = 0;
@@ -233,14 +219,6 @@ static int max77686_i2c_probe(struct i2c_client *i2c,
233 const struct mfd_cell *cells; 219 const struct mfd_cell *cells;
234 int n_devs; 220 int n_devs;
235 221
236 if (IS_ENABLED(CONFIG_OF) && i2c->dev.of_node && !pdata)
237 pdata = max77686_i2c_parse_dt_pdata(&i2c->dev);
238
239 if (!pdata) {
240 dev_err(&i2c->dev, "No platform data found.\n");
241 return -EINVAL;
242 }
243
244 max77686 = devm_kzalloc(&i2c->dev, 222 max77686 = devm_kzalloc(&i2c->dev,
245 sizeof(struct max77686_dev), GFP_KERNEL); 223 sizeof(struct max77686_dev), GFP_KERNEL);
246 if (!max77686) 224 if (!max77686)
@@ -259,7 +237,6 @@ static int max77686_i2c_probe(struct i2c_client *i2c,
259 max77686->dev = &i2c->dev; 237 max77686->dev = &i2c->dev;
260 max77686->i2c = i2c; 238 max77686->i2c = i2c;
261 239
262 max77686->wakeup = pdata->wakeup;
263 max77686->irq = i2c->irq; 240 max77686->irq = i2c->irq;
264 241
265 if (max77686->type == TYPE_MAX77686) { 242 if (max77686->type == TYPE_MAX77686) {
diff --git a/drivers/mfd/mc13xxx-i2c.c b/drivers/mfd/mc13xxx-i2c.c
index ae3addb153a2..68b844811566 100644
--- a/drivers/mfd/mc13xxx-i2c.c
+++ b/drivers/mfd/mc13xxx-i2c.c
@@ -46,7 +46,7 @@ static const struct of_device_id mc13xxx_dt_ids[] = {
46}; 46};
47MODULE_DEVICE_TABLE(of, mc13xxx_dt_ids); 47MODULE_DEVICE_TABLE(of, mc13xxx_dt_ids);
48 48
49static struct regmap_config mc13xxx_regmap_i2c_config = { 49static const struct regmap_config mc13xxx_regmap_i2c_config = {
50 .reg_bits = 8, 50 .reg_bits = 8,
51 .val_bits = 24, 51 .val_bits = 24,
52 52
diff --git a/drivers/mfd/mc13xxx-spi.c b/drivers/mfd/mc13xxx-spi.c
index 702925e242c9..58a170e45d88 100644
--- a/drivers/mfd/mc13xxx-spi.c
+++ b/drivers/mfd/mc13xxx-spi.c
@@ -48,7 +48,7 @@ static const struct of_device_id mc13xxx_dt_ids[] = {
48}; 48};
49MODULE_DEVICE_TABLE(of, mc13xxx_dt_ids); 49MODULE_DEVICE_TABLE(of, mc13xxx_dt_ids);
50 50
51static struct regmap_config mc13xxx_regmap_spi_config = { 51static const struct regmap_config mc13xxx_regmap_spi_config = {
52 .reg_bits = 7, 52 .reg_bits = 7,
53 .pad_bits = 1, 53 .pad_bits = 1,
54 .val_bits = 24, 54 .val_bits = 24,
diff --git a/drivers/mfd/omap-usb-host.c b/drivers/mfd/omap-usb-host.c
index 04cd54dd507c..1d924d1533c0 100644
--- a/drivers/mfd/omap-usb-host.c
+++ b/drivers/mfd/omap-usb-host.c
@@ -129,16 +129,6 @@ static inline u32 usbhs_read(void __iomem *base, u32 reg)
129 return readl_relaxed(base + reg); 129 return readl_relaxed(base + reg);
130} 130}
131 131
132static inline void usbhs_writeb(void __iomem *base, u8 reg, u8 val)
133{
134 writeb_relaxed(val, base + reg);
135}
136
137static inline u8 usbhs_readb(void __iomem *base, u8 reg)
138{
139 return readb_relaxed(base + reg);
140}
141
142/*-------------------------------------------------------------------------*/ 132/*-------------------------------------------------------------------------*/
143 133
144/** 134/**
diff --git a/drivers/mfd/pcf50633-core.c b/drivers/mfd/pcf50633-core.c
index 43664eb69c93..6155d123a84e 100644
--- a/drivers/mfd/pcf50633-core.c
+++ b/drivers/mfd/pcf50633-core.c
@@ -183,7 +183,7 @@ static int pcf50633_resume(struct device *dev)
183 183
184static SIMPLE_DEV_PM_OPS(pcf50633_pm, pcf50633_suspend, pcf50633_resume); 184static SIMPLE_DEV_PM_OPS(pcf50633_pm, pcf50633_suspend, pcf50633_resume);
185 185
186static struct regmap_config pcf50633_regmap_config = { 186static const struct regmap_config pcf50633_regmap_config = {
187 .reg_bits = 8, 187 .reg_bits = 8,
188 .val_bits = 8, 188 .val_bits = 8,
189}; 189};
diff --git a/drivers/mfd/qcom_rpm.c b/drivers/mfd/qcom_rpm.c
new file mode 100644
index 000000000000..f696328c2933
--- /dev/null
+++ b/drivers/mfd/qcom_rpm.c
@@ -0,0 +1,581 @@
1/*
2 * Copyright (c) 2014, Sony Mobile Communications AB.
3 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 * Author: Bjorn Andersson <bjorn.andersson@sonymobile.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 and
8 * only version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/module.h>
17#include <linux/platform_device.h>
18#include <linux/of_platform.h>
19#include <linux/io.h>
20#include <linux/interrupt.h>
21#include <linux/mfd/qcom_rpm.h>
22#include <linux/mfd/syscon.h>
23#include <linux/regmap.h>
24
25#include <dt-bindings/mfd/qcom-rpm.h>
26
27struct qcom_rpm_resource {
28 unsigned target_id;
29 unsigned status_id;
30 unsigned select_id;
31 unsigned size;
32};
33
34struct qcom_rpm_data {
35 u32 version;
36 const struct qcom_rpm_resource *resource_table;
37 unsigned n_resources;
38};
39
40struct qcom_rpm {
41 struct device *dev;
42 struct regmap *ipc_regmap;
43 unsigned ipc_offset;
44 unsigned ipc_bit;
45
46 struct completion ack;
47 struct mutex lock;
48
49 void __iomem *status_regs;
50 void __iomem *ctrl_regs;
51 void __iomem *req_regs;
52
53 u32 ack_status;
54
55 const struct qcom_rpm_data *data;
56};
57
58#define RPM_STATUS_REG(rpm, i) ((rpm)->status_regs + (i) * 4)
59#define RPM_CTRL_REG(rpm, i) ((rpm)->ctrl_regs + (i) * 4)
60#define RPM_REQ_REG(rpm, i) ((rpm)->req_regs + (i) * 4)
61
62#define RPM_REQUEST_TIMEOUT (5 * HZ)
63
64#define RPM_REQUEST_CONTEXT 3
65#define RPM_REQ_SELECT 11
66#define RPM_ACK_CONTEXT 15
67#define RPM_ACK_SELECTOR 23
68#define RPM_SELECT_SIZE 7
69
70#define RPM_NOTIFICATION BIT(30)
71#define RPM_REJECTED BIT(31)
72
73#define RPM_SIGNAL BIT(2)
74
75static const struct qcom_rpm_resource apq8064_rpm_resource_table[] = {
76 [QCOM_RPM_CXO_CLK] = { 25, 9, 5, 1 },
77 [QCOM_RPM_PXO_CLK] = { 26, 10, 6, 1 },
78 [QCOM_RPM_APPS_FABRIC_CLK] = { 27, 11, 8, 1 },
79 [QCOM_RPM_SYS_FABRIC_CLK] = { 28, 12, 9, 1 },
80 [QCOM_RPM_MM_FABRIC_CLK] = { 29, 13, 10, 1 },
81 [QCOM_RPM_DAYTONA_FABRIC_CLK] = { 30, 14, 11, 1 },
82 [QCOM_RPM_SFPB_CLK] = { 31, 15, 12, 1 },
83 [QCOM_RPM_CFPB_CLK] = { 32, 16, 13, 1 },
84 [QCOM_RPM_MMFPB_CLK] = { 33, 17, 14, 1 },
85 [QCOM_RPM_EBI1_CLK] = { 34, 18, 16, 1 },
86 [QCOM_RPM_APPS_FABRIC_HALT] = { 35, 19, 18, 1 },
87 [QCOM_RPM_APPS_FABRIC_MODE] = { 37, 20, 19, 1 },
88 [QCOM_RPM_APPS_FABRIC_IOCTL] = { 40, 21, 20, 1 },
89 [QCOM_RPM_APPS_FABRIC_ARB] = { 41, 22, 21, 12 },
90 [QCOM_RPM_SYS_FABRIC_HALT] = { 53, 23, 22, 1 },
91 [QCOM_RPM_SYS_FABRIC_MODE] = { 55, 24, 23, 1 },
92 [QCOM_RPM_SYS_FABRIC_IOCTL] = { 58, 25, 24, 1 },
93 [QCOM_RPM_SYS_FABRIC_ARB] = { 59, 26, 25, 30 },
94 [QCOM_RPM_MM_FABRIC_HALT] = { 89, 27, 26, 1 },
95 [QCOM_RPM_MM_FABRIC_MODE] = { 91, 28, 27, 1 },
96 [QCOM_RPM_MM_FABRIC_IOCTL] = { 94, 29, 28, 1 },
97 [QCOM_RPM_MM_FABRIC_ARB] = { 95, 30, 29, 21 },
98 [QCOM_RPM_PM8921_SMPS1] = { 116, 31, 30, 2 },
99 [QCOM_RPM_PM8921_SMPS2] = { 118, 33, 31, 2 },
100 [QCOM_RPM_PM8921_SMPS3] = { 120, 35, 32, 2 },
101 [QCOM_RPM_PM8921_SMPS4] = { 122, 37, 33, 2 },
102 [QCOM_RPM_PM8921_SMPS5] = { 124, 39, 34, 2 },
103 [QCOM_RPM_PM8921_SMPS6] = { 126, 41, 35, 2 },
104 [QCOM_RPM_PM8921_SMPS7] = { 128, 43, 36, 2 },
105 [QCOM_RPM_PM8921_SMPS8] = { 130, 45, 37, 2 },
106 [QCOM_RPM_PM8921_LDO1] = { 132, 47, 38, 2 },
107 [QCOM_RPM_PM8921_LDO2] = { 134, 49, 39, 2 },
108 [QCOM_RPM_PM8921_LDO3] = { 136, 51, 40, 2 },
109 [QCOM_RPM_PM8921_LDO4] = { 138, 53, 41, 2 },
110 [QCOM_RPM_PM8921_LDO5] = { 140, 55, 42, 2 },
111 [QCOM_RPM_PM8921_LDO6] = { 142, 57, 43, 2 },
112 [QCOM_RPM_PM8921_LDO7] = { 144, 59, 44, 2 },
113 [QCOM_RPM_PM8921_LDO8] = { 146, 61, 45, 2 },
114 [QCOM_RPM_PM8921_LDO9] = { 148, 63, 46, 2 },
115 [QCOM_RPM_PM8921_LDO10] = { 150, 65, 47, 2 },
116 [QCOM_RPM_PM8921_LDO11] = { 152, 67, 48, 2 },
117 [QCOM_RPM_PM8921_LDO12] = { 154, 69, 49, 2 },
118 [QCOM_RPM_PM8921_LDO13] = { 156, 71, 50, 2 },
119 [QCOM_RPM_PM8921_LDO14] = { 158, 73, 51, 2 },
120 [QCOM_RPM_PM8921_LDO15] = { 160, 75, 52, 2 },
121 [QCOM_RPM_PM8921_LDO16] = { 162, 77, 53, 2 },
122 [QCOM_RPM_PM8921_LDO17] = { 164, 79, 54, 2 },
123 [QCOM_RPM_PM8921_LDO18] = { 166, 81, 55, 2 },
124 [QCOM_RPM_PM8921_LDO19] = { 168, 83, 56, 2 },
125 [QCOM_RPM_PM8921_LDO20] = { 170, 85, 57, 2 },
126 [QCOM_RPM_PM8921_LDO21] = { 172, 87, 58, 2 },
127 [QCOM_RPM_PM8921_LDO22] = { 174, 89, 59, 2 },
128 [QCOM_RPM_PM8921_LDO23] = { 176, 91, 60, 2 },
129 [QCOM_RPM_PM8921_LDO24] = { 178, 93, 61, 2 },
130 [QCOM_RPM_PM8921_LDO25] = { 180, 95, 62, 2 },
131 [QCOM_RPM_PM8921_LDO26] = { 182, 97, 63, 2 },
132 [QCOM_RPM_PM8921_LDO27] = { 184, 99, 64, 2 },
133 [QCOM_RPM_PM8921_LDO28] = { 186, 101, 65, 2 },
134 [QCOM_RPM_PM8921_LDO29] = { 188, 103, 66, 2 },
135 [QCOM_RPM_PM8921_CLK1] = { 190, 105, 67, 2 },
136 [QCOM_RPM_PM8921_CLK2] = { 192, 107, 68, 2 },
137 [QCOM_RPM_PM8921_LVS1] = { 194, 109, 69, 1 },
138 [QCOM_RPM_PM8921_LVS2] = { 195, 110, 70, 1 },
139 [QCOM_RPM_PM8921_LVS3] = { 196, 111, 71, 1 },
140 [QCOM_RPM_PM8921_LVS4] = { 197, 112, 72, 1 },
141 [QCOM_RPM_PM8921_LVS5] = { 198, 113, 73, 1 },
142 [QCOM_RPM_PM8921_LVS6] = { 199, 114, 74, 1 },
143 [QCOM_RPM_PM8921_LVS7] = { 200, 115, 75, 1 },
144 [QCOM_RPM_PM8821_SMPS1] = { 201, 116, 76, 2 },
145 [QCOM_RPM_PM8821_SMPS2] = { 203, 118, 77, 2 },
146 [QCOM_RPM_PM8821_LDO1] = { 205, 120, 78, 2 },
147 [QCOM_RPM_PM8921_NCP] = { 207, 122, 80, 2 },
148 [QCOM_RPM_CXO_BUFFERS] = { 209, 124, 81, 1 },
149 [QCOM_RPM_USB_OTG_SWITCH] = { 210, 125, 82, 1 },
150 [QCOM_RPM_HDMI_SWITCH] = { 211, 126, 83, 1 },
151 [QCOM_RPM_DDR_DMM] = { 212, 127, 84, 2 },
152 [QCOM_RPM_VDDMIN_GPIO] = { 215, 131, 89, 1 },
153};
154
155static const struct qcom_rpm_data apq8064_template = {
156 .version = 3,
157 .resource_table = apq8064_rpm_resource_table,
158 .n_resources = ARRAY_SIZE(apq8064_rpm_resource_table),
159};
160
161static const struct qcom_rpm_resource msm8660_rpm_resource_table[] = {
162 [QCOM_RPM_CXO_CLK] = { 32, 12, 5, 1 },
163 [QCOM_RPM_PXO_CLK] = { 33, 13, 6, 1 },
164 [QCOM_RPM_PLL_4] = { 34, 14, 7, 1 },
165 [QCOM_RPM_APPS_FABRIC_CLK] = { 35, 15, 8, 1 },
166 [QCOM_RPM_SYS_FABRIC_CLK] = { 36, 16, 9, 1 },
167 [QCOM_RPM_MM_FABRIC_CLK] = { 37, 17, 10, 1 },
168 [QCOM_RPM_DAYTONA_FABRIC_CLK] = { 38, 18, 11, 1 },
169 [QCOM_RPM_SFPB_CLK] = { 39, 19, 12, 1 },
170 [QCOM_RPM_CFPB_CLK] = { 40, 20, 13, 1 },
171 [QCOM_RPM_MMFPB_CLK] = { 41, 21, 14, 1 },
172 [QCOM_RPM_SMI_CLK] = { 42, 22, 15, 1 },
173 [QCOM_RPM_EBI1_CLK] = { 43, 23, 16, 1 },
174 [QCOM_RPM_APPS_L2_CACHE_CTL] = { 44, 24, 17, 1 },
175 [QCOM_RPM_APPS_FABRIC_HALT] = { 45, 25, 18, 2 },
176 [QCOM_RPM_APPS_FABRIC_MODE] = { 47, 26, 19, 3 },
177 [QCOM_RPM_APPS_FABRIC_ARB] = { 51, 28, 21, 6 },
178 [QCOM_RPM_SYS_FABRIC_HALT] = { 63, 29, 22, 2 },
179 [QCOM_RPM_SYS_FABRIC_MODE] = { 65, 30, 23, 3 },
180 [QCOM_RPM_SYS_FABRIC_ARB] = { 69, 32, 25, 22 },
181 [QCOM_RPM_MM_FABRIC_HALT] = { 105, 33, 26, 2 },
182 [QCOM_RPM_MM_FABRIC_MODE] = { 107, 34, 27, 3 },
183 [QCOM_RPM_MM_FABRIC_ARB] = { 111, 36, 29, 23 },
184 [QCOM_RPM_PM8901_SMPS0] = { 134, 37, 30, 2 },
185 [QCOM_RPM_PM8901_SMPS1] = { 136, 39, 31, 2 },
186 [QCOM_RPM_PM8901_SMPS2] = { 138, 41, 32, 2 },
187 [QCOM_RPM_PM8901_SMPS3] = { 140, 43, 33, 2 },
188 [QCOM_RPM_PM8901_SMPS4] = { 142, 45, 34, 2 },
189 [QCOM_RPM_PM8901_LDO0] = { 144, 47, 35, 2 },
190 [QCOM_RPM_PM8901_LDO1] = { 146, 49, 36, 2 },
191 [QCOM_RPM_PM8901_LDO2] = { 148, 51, 37, 2 },
192 [QCOM_RPM_PM8901_LDO3] = { 150, 53, 38, 2 },
193 [QCOM_RPM_PM8901_LDO4] = { 152, 55, 39, 2 },
194 [QCOM_RPM_PM8901_LDO5] = { 154, 57, 40, 2 },
195 [QCOM_RPM_PM8901_LDO6] = { 156, 59, 41, 2 },
196 [QCOM_RPM_PM8901_LVS0] = { 158, 61, 42, 1 },
197 [QCOM_RPM_PM8901_LVS1] = { 159, 62, 43, 1 },
198 [QCOM_RPM_PM8901_LVS2] = { 160, 63, 44, 1 },
199 [QCOM_RPM_PM8901_LVS3] = { 161, 64, 45, 1 },
200 [QCOM_RPM_PM8901_MVS] = { 162, 65, 46, 1 },
201 [QCOM_RPM_PM8058_SMPS0] = { 163, 66, 47, 2 },
202 [QCOM_RPM_PM8058_SMPS1] = { 165, 68, 48, 2 },
203 [QCOM_RPM_PM8058_SMPS2] = { 167, 70, 49, 2 },
204 [QCOM_RPM_PM8058_SMPS3] = { 169, 72, 50, 2 },
205 [QCOM_RPM_PM8058_SMPS4] = { 171, 74, 51, 2 },
206 [QCOM_RPM_PM8058_LDO0] = { 173, 76, 52, 2 },
207 [QCOM_RPM_PM8058_LDO1] = { 175, 78, 53, 2 },
208 [QCOM_RPM_PM8058_LDO2] = { 177, 80, 54, 2 },
209 [QCOM_RPM_PM8058_LDO3] = { 179, 82, 55, 2 },
210 [QCOM_RPM_PM8058_LDO4] = { 181, 84, 56, 2 },
211 [QCOM_RPM_PM8058_LDO5] = { 183, 86, 57, 2 },
212 [QCOM_RPM_PM8058_LDO6] = { 185, 88, 58, 2 },
213 [QCOM_RPM_PM8058_LDO7] = { 187, 90, 59, 2 },
214 [QCOM_RPM_PM8058_LDO8] = { 189, 92, 60, 2 },
215 [QCOM_RPM_PM8058_LDO9] = { 191, 94, 61, 2 },
216 [QCOM_RPM_PM8058_LDO10] = { 193, 96, 62, 2 },
217 [QCOM_RPM_PM8058_LDO11] = { 195, 98, 63, 2 },
218 [QCOM_RPM_PM8058_LDO12] = { 197, 100, 64, 2 },
219 [QCOM_RPM_PM8058_LDO13] = { 199, 102, 65, 2 },
220 [QCOM_RPM_PM8058_LDO14] = { 201, 104, 66, 2 },
221 [QCOM_RPM_PM8058_LDO15] = { 203, 106, 67, 2 },
222 [QCOM_RPM_PM8058_LDO16] = { 205, 108, 68, 2 },
223 [QCOM_RPM_PM8058_LDO17] = { 207, 110, 69, 2 },
224 [QCOM_RPM_PM8058_LDO18] = { 209, 112, 70, 2 },
225 [QCOM_RPM_PM8058_LDO19] = { 211, 114, 71, 2 },
226 [QCOM_RPM_PM8058_LDO20] = { 213, 116, 72, 2 },
227 [QCOM_RPM_PM8058_LDO21] = { 215, 118, 73, 2 },
228 [QCOM_RPM_PM8058_LDO22] = { 217, 120, 74, 2 },
229 [QCOM_RPM_PM8058_LDO23] = { 219, 122, 75, 2 },
230 [QCOM_RPM_PM8058_LDO24] = { 221, 124, 76, 2 },
231 [QCOM_RPM_PM8058_LDO25] = { 223, 126, 77, 2 },
232 [QCOM_RPM_PM8058_LVS0] = { 225, 128, 78, 1 },
233 [QCOM_RPM_PM8058_LVS1] = { 226, 129, 79, 1 },
234 [QCOM_RPM_PM8058_NCP] = { 227, 130, 80, 2 },
235 [QCOM_RPM_CXO_BUFFERS] = { 229, 132, 81, 1 },
236};
237
238static const struct qcom_rpm_data msm8660_template = {
239 .version = 2,
240 .resource_table = msm8660_rpm_resource_table,
241 .n_resources = ARRAY_SIZE(msm8660_rpm_resource_table),
242};
243
244static const struct qcom_rpm_resource msm8960_rpm_resource_table[] = {
245 [QCOM_RPM_CXO_CLK] = { 25, 9, 5, 1 },
246 [QCOM_RPM_PXO_CLK] = { 26, 10, 6, 1 },
247 [QCOM_RPM_APPS_FABRIC_CLK] = { 27, 11, 8, 1 },
248 [QCOM_RPM_SYS_FABRIC_CLK] = { 28, 12, 9, 1 },
249 [QCOM_RPM_MM_FABRIC_CLK] = { 29, 13, 10, 1 },
250 [QCOM_RPM_DAYTONA_FABRIC_CLK] = { 30, 14, 11, 1 },
251 [QCOM_RPM_SFPB_CLK] = { 31, 15, 12, 1 },
252 [QCOM_RPM_CFPB_CLK] = { 32, 16, 13, 1 },
253 [QCOM_RPM_MMFPB_CLK] = { 33, 17, 14, 1 },
254 [QCOM_RPM_EBI1_CLK] = { 34, 18, 16, 1 },
255 [QCOM_RPM_APPS_FABRIC_HALT] = { 35, 19, 18, 1 },
256 [QCOM_RPM_APPS_FABRIC_MODE] = { 37, 20, 19, 1 },
257 [QCOM_RPM_APPS_FABRIC_IOCTL] = { 40, 21, 20, 1 },
258 [QCOM_RPM_APPS_FABRIC_ARB] = { 41, 22, 21, 12 },
259 [QCOM_RPM_SYS_FABRIC_HALT] = { 53, 23, 22, 1 },
260 [QCOM_RPM_SYS_FABRIC_MODE] = { 55, 24, 23, 1 },
261 [QCOM_RPM_SYS_FABRIC_IOCTL] = { 58, 25, 24, 1 },
262 [QCOM_RPM_SYS_FABRIC_ARB] = { 59, 26, 25, 29 },
263 [QCOM_RPM_MM_FABRIC_HALT] = { 88, 27, 26, 1 },
264 [QCOM_RPM_MM_FABRIC_MODE] = { 90, 28, 27, 1 },
265 [QCOM_RPM_MM_FABRIC_IOCTL] = { 93, 29, 28, 1 },
266 [QCOM_RPM_MM_FABRIC_ARB] = { 94, 30, 29, 23 },
267 [QCOM_RPM_PM8921_SMPS1] = { 117, 31, 30, 2 },
268 [QCOM_RPM_PM8921_SMPS2] = { 119, 33, 31, 2 },
269 [QCOM_RPM_PM8921_SMPS3] = { 121, 35, 32, 2 },
270 [QCOM_RPM_PM8921_SMPS4] = { 123, 37, 33, 2 },
271 [QCOM_RPM_PM8921_SMPS5] = { 125, 39, 34, 2 },
272 [QCOM_RPM_PM8921_SMPS6] = { 127, 41, 35, 2 },
273 [QCOM_RPM_PM8921_SMPS7] = { 129, 43, 36, 2 },
274 [QCOM_RPM_PM8921_SMPS8] = { 131, 45, 37, 2 },
275 [QCOM_RPM_PM8921_LDO1] = { 133, 47, 38, 2 },
276 [QCOM_RPM_PM8921_LDO2] = { 135, 49, 39, 2 },
277 [QCOM_RPM_PM8921_LDO3] = { 137, 51, 40, 2 },
278 [QCOM_RPM_PM8921_LDO4] = { 139, 53, 41, 2 },
279 [QCOM_RPM_PM8921_LDO5] = { 141, 55, 42, 2 },
280 [QCOM_RPM_PM8921_LDO6] = { 143, 57, 43, 2 },
281 [QCOM_RPM_PM8921_LDO7] = { 145, 59, 44, 2 },
282 [QCOM_RPM_PM8921_LDO8] = { 147, 61, 45, 2 },
283 [QCOM_RPM_PM8921_LDO9] = { 149, 63, 46, 2 },
284 [QCOM_RPM_PM8921_LDO10] = { 151, 65, 47, 2 },
285 [QCOM_RPM_PM8921_LDO11] = { 153, 67, 48, 2 },
286 [QCOM_RPM_PM8921_LDO12] = { 155, 69, 49, 2 },
287 [QCOM_RPM_PM8921_LDO13] = { 157, 71, 50, 2 },
288 [QCOM_RPM_PM8921_LDO14] = { 159, 73, 51, 2 },
289 [QCOM_RPM_PM8921_LDO15] = { 161, 75, 52, 2 },
290 [QCOM_RPM_PM8921_LDO16] = { 163, 77, 53, 2 },
291 [QCOM_RPM_PM8921_LDO17] = { 165, 79, 54, 2 },
292 [QCOM_RPM_PM8921_LDO18] = { 167, 81, 55, 2 },
293 [QCOM_RPM_PM8921_LDO19] = { 169, 83, 56, 2 },
294 [QCOM_RPM_PM8921_LDO20] = { 171, 85, 57, 2 },
295 [QCOM_RPM_PM8921_LDO21] = { 173, 87, 58, 2 },
296 [QCOM_RPM_PM8921_LDO22] = { 175, 89, 59, 2 },
297 [QCOM_RPM_PM8921_LDO23] = { 177, 91, 60, 2 },
298 [QCOM_RPM_PM8921_LDO24] = { 179, 93, 61, 2 },
299 [QCOM_RPM_PM8921_LDO25] = { 181, 95, 62, 2 },
300 [QCOM_RPM_PM8921_LDO26] = { 183, 97, 63, 2 },
301 [QCOM_RPM_PM8921_LDO27] = { 185, 99, 64, 2 },
302 [QCOM_RPM_PM8921_LDO28] = { 187, 101, 65, 2 },
303 [QCOM_RPM_PM8921_LDO29] = { 189, 103, 66, 2 },
304 [QCOM_RPM_PM8921_CLK1] = { 191, 105, 67, 2 },
305 [QCOM_RPM_PM8921_CLK2] = { 193, 107, 68, 2 },
306 [QCOM_RPM_PM8921_LVS1] = { 195, 109, 69, 1 },
307 [QCOM_RPM_PM8921_LVS2] = { 196, 110, 70, 1 },
308 [QCOM_RPM_PM8921_LVS3] = { 197, 111, 71, 1 },
309 [QCOM_RPM_PM8921_LVS4] = { 198, 112, 72, 1 },
310 [QCOM_RPM_PM8921_LVS5] = { 199, 113, 73, 1 },
311 [QCOM_RPM_PM8921_LVS6] = { 200, 114, 74, 1 },
312 [QCOM_RPM_PM8921_LVS7] = { 201, 115, 75, 1 },
313 [QCOM_RPM_PM8921_NCP] = { 202, 116, 80, 2 },
314 [QCOM_RPM_CXO_BUFFERS] = { 204, 118, 81, 1 },
315 [QCOM_RPM_USB_OTG_SWITCH] = { 205, 119, 82, 1 },
316 [QCOM_RPM_HDMI_SWITCH] = { 206, 120, 83, 1 },
317 [QCOM_RPM_DDR_DMM] = { 207, 121, 84, 2 },
318};
319
320static const struct qcom_rpm_data msm8960_template = {
321 .version = 3,
322 .resource_table = msm8960_rpm_resource_table,
323 .n_resources = ARRAY_SIZE(msm8960_rpm_resource_table),
324};
325
326static const struct of_device_id qcom_rpm_of_match[] = {
327 { .compatible = "qcom,rpm-apq8064", .data = &apq8064_template },
328 { .compatible = "qcom,rpm-msm8660", .data = &msm8660_template },
329 { .compatible = "qcom,rpm-msm8960", .data = &msm8960_template },
330 { }
331};
332MODULE_DEVICE_TABLE(of, qcom_rpm_of_match);
333
334int qcom_rpm_write(struct qcom_rpm *rpm,
335 int state,
336 int resource,
337 u32 *buf, size_t count)
338{
339 const struct qcom_rpm_resource *res;
340 const struct qcom_rpm_data *data = rpm->data;
341 u32 sel_mask[RPM_SELECT_SIZE] = { 0 };
342 int left;
343 int ret = 0;
344 int i;
345
346 if (WARN_ON(resource < 0 || resource >= data->n_resources))
347 return -EINVAL;
348
349 res = &data->resource_table[resource];
350 if (WARN_ON(res->size != count))
351 return -EINVAL;
352
353 mutex_lock(&rpm->lock);
354
355 for (i = 0; i < res->size; i++)
356 writel_relaxed(buf[i], RPM_REQ_REG(rpm, res->target_id + i));
357
358 bitmap_set((unsigned long *)sel_mask, res->select_id, 1);
359 for (i = 0; i < ARRAY_SIZE(sel_mask); i++) {
360 writel_relaxed(sel_mask[i],
361 RPM_CTRL_REG(rpm, RPM_REQ_SELECT + i));
362 }
363
364 writel_relaxed(BIT(state), RPM_CTRL_REG(rpm, RPM_REQUEST_CONTEXT));
365
366 reinit_completion(&rpm->ack);
367 regmap_write(rpm->ipc_regmap, rpm->ipc_offset, BIT(rpm->ipc_bit));
368
369 left = wait_for_completion_timeout(&rpm->ack, RPM_REQUEST_TIMEOUT);
370 if (!left)
371 ret = -ETIMEDOUT;
372 else if (rpm->ack_status & RPM_REJECTED)
373 ret = -EIO;
374
375 mutex_unlock(&rpm->lock);
376
377 return ret;
378}
379EXPORT_SYMBOL(qcom_rpm_write);
380
381static irqreturn_t qcom_rpm_ack_interrupt(int irq, void *dev)
382{
383 struct qcom_rpm *rpm = dev;
384 u32 ack;
385 int i;
386
387 ack = readl_relaxed(RPM_CTRL_REG(rpm, RPM_ACK_CONTEXT));
388 for (i = 0; i < RPM_SELECT_SIZE; i++)
389 writel_relaxed(0, RPM_CTRL_REG(rpm, RPM_ACK_SELECTOR + i));
390 writel(0, RPM_CTRL_REG(rpm, RPM_ACK_CONTEXT));
391
392 if (ack & RPM_NOTIFICATION) {
393 dev_warn(rpm->dev, "ignoring notification!\n");
394 } else {
395 rpm->ack_status = ack;
396 complete(&rpm->ack);
397 }
398
399 return IRQ_HANDLED;
400}
401
402static irqreturn_t qcom_rpm_err_interrupt(int irq, void *dev)
403{
404 struct qcom_rpm *rpm = dev;
405
406 regmap_write(rpm->ipc_regmap, rpm->ipc_offset, BIT(rpm->ipc_bit));
407 dev_err(rpm->dev, "RPM triggered fatal error\n");
408
409 return IRQ_HANDLED;
410}
411
412static irqreturn_t qcom_rpm_wakeup_interrupt(int irq, void *dev)
413{
414 return IRQ_HANDLED;
415}
416
417static int qcom_rpm_probe(struct platform_device *pdev)
418{
419 const struct of_device_id *match;
420 struct device_node *syscon_np;
421 struct resource *res;
422 struct qcom_rpm *rpm;
423 u32 fw_version[3];
424 int irq_wakeup;
425 int irq_ack;
426 int irq_err;
427 int ret;
428
429 rpm = devm_kzalloc(&pdev->dev, sizeof(*rpm), GFP_KERNEL);
430 if (!rpm)
431 return -ENOMEM;
432
433 rpm->dev = &pdev->dev;
434 mutex_init(&rpm->lock);
435 init_completion(&rpm->ack);
436
437 irq_ack = platform_get_irq_byname(pdev, "ack");
438 if (irq_ack < 0) {
439 dev_err(&pdev->dev, "required ack interrupt missing\n");
440 return irq_ack;
441 }
442
443 irq_err = platform_get_irq_byname(pdev, "err");
444 if (irq_err < 0) {
445 dev_err(&pdev->dev, "required err interrupt missing\n");
446 return irq_err;
447 }
448
449 irq_wakeup = platform_get_irq_byname(pdev, "wakeup");
450 if (irq_wakeup < 0) {
451 dev_err(&pdev->dev, "required wakeup interrupt missing\n");
452 return irq_wakeup;
453 }
454
455 match = of_match_device(qcom_rpm_of_match, &pdev->dev);
456 rpm->data = match->data;
457
458 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
459 rpm->status_regs = devm_ioremap_resource(&pdev->dev, res);
460 if (IS_ERR(rpm->status_regs))
461 return PTR_ERR(rpm->status_regs);
462 rpm->ctrl_regs = rpm->status_regs + 0x400;
463 rpm->req_regs = rpm->status_regs + 0x600;
464
465 syscon_np = of_parse_phandle(pdev->dev.of_node, "qcom,ipc", 0);
466 if (!syscon_np) {
467 dev_err(&pdev->dev, "no qcom,ipc node\n");
468 return -ENODEV;
469 }
470
471 rpm->ipc_regmap = syscon_node_to_regmap(syscon_np);
472 if (IS_ERR(rpm->ipc_regmap))
473 return PTR_ERR(rpm->ipc_regmap);
474
475 ret = of_property_read_u32_index(pdev->dev.of_node, "qcom,ipc", 1,
476 &rpm->ipc_offset);
477 if (ret < 0) {
478 dev_err(&pdev->dev, "no offset in qcom,ipc\n");
479 return -EINVAL;
480 }
481
482 ret = of_property_read_u32_index(pdev->dev.of_node, "qcom,ipc", 2,
483 &rpm->ipc_bit);
484 if (ret < 0) {
485 dev_err(&pdev->dev, "no bit in qcom,ipc\n");
486 return -EINVAL;
487 }
488
489 dev_set_drvdata(&pdev->dev, rpm);
490
491 fw_version[0] = readl(RPM_STATUS_REG(rpm, 0));
492 fw_version[1] = readl(RPM_STATUS_REG(rpm, 1));
493 fw_version[2] = readl(RPM_STATUS_REG(rpm, 2));
494 if (fw_version[0] != rpm->data->version) {
495 dev_err(&pdev->dev,
496 "RPM version %u.%u.%u incompatible with driver version %u",
497 fw_version[0],
498 fw_version[1],
499 fw_version[2],
500 rpm->data->version);
501 return -EFAULT;
502 }
503
504 dev_info(&pdev->dev, "RPM firmware %u.%u.%u\n", fw_version[0],
505 fw_version[1],
506 fw_version[2]);
507
508 ret = devm_request_irq(&pdev->dev,
509 irq_ack,
510 qcom_rpm_ack_interrupt,
511 IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND,
512 "qcom_rpm_ack",
513 rpm);
514 if (ret) {
515 dev_err(&pdev->dev, "failed to request ack interrupt\n");
516 return ret;
517 }
518
519 ret = irq_set_irq_wake(irq_ack, 1);
520 if (ret)
521 dev_warn(&pdev->dev, "failed to mark ack irq as wakeup\n");
522
523 ret = devm_request_irq(&pdev->dev,
524 irq_err,
525 qcom_rpm_err_interrupt,
526 IRQF_TRIGGER_RISING,
527 "qcom_rpm_err",
528 rpm);
529 if (ret) {
530 dev_err(&pdev->dev, "failed to request err interrupt\n");
531 return ret;
532 }
533
534 ret = devm_request_irq(&pdev->dev,
535 irq_wakeup,
536 qcom_rpm_wakeup_interrupt,
537 IRQF_TRIGGER_RISING,
538 "qcom_rpm_wakeup",
539 rpm);
540 if (ret) {
541 dev_err(&pdev->dev, "failed to request wakeup interrupt\n");
542 return ret;
543 }
544
545 ret = irq_set_irq_wake(irq_wakeup, 1);
546 if (ret)
547 dev_warn(&pdev->dev, "failed to mark wakeup irq as wakeup\n");
548
549 return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
550}
551
552static int qcom_rpm_remove(struct platform_device *pdev)
553{
554 of_platform_depopulate(&pdev->dev);
555 return 0;
556}
557
558static struct platform_driver qcom_rpm_driver = {
559 .probe = qcom_rpm_probe,
560 .remove = qcom_rpm_remove,
561 .driver = {
562 .name = "qcom_rpm",
563 .of_match_table = qcom_rpm_of_match,
564 },
565};
566
567static int __init qcom_rpm_init(void)
568{
569 return platform_driver_register(&qcom_rpm_driver);
570}
571arch_initcall(qcom_rpm_init);
572
573static void __exit qcom_rpm_exit(void)
574{
575 platform_driver_unregister(&qcom_rpm_driver);
576}
577module_exit(qcom_rpm_exit)
578
579MODULE_DESCRIPTION("Qualcomm Resource Power Manager driver");
580MODULE_LICENSE("GPL v2");
581MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");
diff --git a/drivers/mfd/retu-mfd.c b/drivers/mfd/retu-mfd.c
index 663f8a37aa6b..2d64430c719b 100644
--- a/drivers/mfd/retu-mfd.c
+++ b/drivers/mfd/retu-mfd.c
@@ -222,7 +222,7 @@ static struct regmap_bus retu_bus = {
222 .val_format_endian_default = REGMAP_ENDIAN_NATIVE, 222 .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
223}; 223};
224 224
225static struct regmap_config retu_config = { 225static const struct regmap_config retu_config = {
226 .reg_bits = 8, 226 .reg_bits = 8,
227 .val_bits = 16, 227 .val_bits = 16,
228}; 228};
diff --git a/drivers/mfd/rt5033.c b/drivers/mfd/rt5033.c
new file mode 100644
index 000000000000..db395a6c52bc
--- /dev/null
+++ b/drivers/mfd/rt5033.c
@@ -0,0 +1,142 @@
1/*
2 * MFD core driver for the Richtek RT5033.
3 *
4 * RT5033 comprises multiple sub-devices switcing charger, fuel gauge,
5 * flash LED, current source, LDO and BUCK regulators.
6 *
7 * Copyright (C) 2014 Samsung Electronics, Co., Ltd.
8 * Author: Beomho Seo <beomho.seo@samsung.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published bythe Free Software Foundation.
13 */
14
15#include <linux/err.h>
16#include <linux/module.h>
17#include <linux/interrupt.h>
18#include <linux/of_device.h>
19#include <linux/mfd/core.h>
20#include <linux/mfd/rt5033.h>
21#include <linux/mfd/rt5033-private.h>
22
23static const struct regmap_irq rt5033_irqs[] = {
24 { .mask = RT5033_PMIC_IRQ_BUCKOCP, },
25 { .mask = RT5033_PMIC_IRQ_BUCKLV, },
26 { .mask = RT5033_PMIC_IRQ_SAFELDOLV, },
27 { .mask = RT5033_PMIC_IRQ_LDOLV, },
28 { .mask = RT5033_PMIC_IRQ_OT, },
29 { .mask = RT5033_PMIC_IRQ_VDDA_UV, },
30};
31
32static const struct regmap_irq_chip rt5033_irq_chip = {
33 .name = "rt5033",
34 .status_base = RT5033_REG_PMIC_IRQ_STAT,
35 .mask_base = RT5033_REG_PMIC_IRQ_CTRL,
36 .mask_invert = true,
37 .num_regs = 1,
38 .irqs = rt5033_irqs,
39 .num_irqs = ARRAY_SIZE(rt5033_irqs),
40};
41
42static const struct mfd_cell rt5033_devs[] = {
43 { .name = "rt5033-regulator", },
44 {
45 .name = "rt5033-charger",
46 .of_compatible = "richtek,rt5033-charger",
47 }, {
48 .name = "rt5033-battery",
49 .of_compatible = "richtek,rt5033-battery",
50 },
51};
52
53static const struct regmap_config rt5033_regmap_config = {
54 .reg_bits = 8,
55 .val_bits = 8,
56 .max_register = RT5033_REG_END,
57};
58
59static int rt5033_i2c_probe(struct i2c_client *i2c,
60 const struct i2c_device_id *id)
61{
62 struct rt5033_dev *rt5033;
63 unsigned int dev_id;
64 int ret;
65
66 rt5033 = devm_kzalloc(&i2c->dev, sizeof(*rt5033), GFP_KERNEL);
67 if (!rt5033)
68 return -ENOMEM;
69
70 i2c_set_clientdata(i2c, rt5033);
71 rt5033->dev = &i2c->dev;
72 rt5033->irq = i2c->irq;
73 rt5033->wakeup = true;
74
75 rt5033->regmap = devm_regmap_init_i2c(i2c, &rt5033_regmap_config);
76 if (IS_ERR(rt5033->regmap)) {
77 dev_err(&i2c->dev, "Failed to allocate register map.\n");
78 return PTR_ERR(rt5033->regmap);
79 }
80
81 ret = regmap_read(rt5033->regmap, RT5033_REG_DEVICE_ID, &dev_id);
82 if (ret) {
83 dev_err(&i2c->dev, "Device not found\n");
84 return -ENODEV;
85 }
86 dev_info(&i2c->dev, "Device found Device ID: %04x\n", dev_id);
87
88 ret = regmap_add_irq_chip(rt5033->regmap, rt5033->irq,
89 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
90 0, &rt5033_irq_chip, &rt5033->irq_data);
91 if (ret) {
92 dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",
93 rt5033->irq, ret);
94 return ret;
95 }
96
97 ret = mfd_add_devices(rt5033->dev, -1, rt5033_devs,
98 ARRAY_SIZE(rt5033_devs), NULL, 0,
99 regmap_irq_get_domain(rt5033->irq_data));
100 if (ret < 0) {
101 dev_err(&i2c->dev, "Failed to add RT5033 child devices.\n");
102 return ret;
103 }
104
105 device_init_wakeup(rt5033->dev, rt5033->wakeup);
106
107 return 0;
108}
109
110static int rt5033_i2c_remove(struct i2c_client *i2c)
111{
112 mfd_remove_devices(&i2c->dev);
113
114 return 0;
115}
116
117static const struct i2c_device_id rt5033_i2c_id[] = {
118 { "rt5033", },
119 { }
120};
121MODULE_DEVICE_TABLE(i2c, rt5033_i2c_id);
122
123static const struct of_device_id rt5033_dt_match[] = {
124 { .compatible = "richtek,rt5033", },
125 { }
126};
127
128static struct i2c_driver rt5033_driver = {
129 .driver = {
130 .name = "rt5033",
131 .of_match_table = of_match_ptr(rt5033_dt_match),
132 },
133 .probe = rt5033_i2c_probe,
134 .remove = rt5033_i2c_remove,
135 .id_table = rt5033_i2c_id,
136};
137module_i2c_driver(rt5033_driver);
138
139MODULE_ALIAS("i2c:rt5033");
140MODULE_DESCRIPTION("Richtek RT5033 multi-function core driver");
141MODULE_AUTHOR("Beomho Seo <beomho.seo@samsung.com>");
142MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/rtsx_usb.c b/drivers/mfd/rtsx_usb.c
index 210d1f85679e..ede50244f265 100644
--- a/drivers/mfd/rtsx_usb.c
+++ b/drivers/mfd/rtsx_usb.c
@@ -681,9 +681,27 @@ static void rtsx_usb_disconnect(struct usb_interface *intf)
681#ifdef CONFIG_PM 681#ifdef CONFIG_PM
682static int rtsx_usb_suspend(struct usb_interface *intf, pm_message_t message) 682static int rtsx_usb_suspend(struct usb_interface *intf, pm_message_t message)
683{ 683{
684 struct rtsx_ucr *ucr =
685 (struct rtsx_ucr *)usb_get_intfdata(intf);
686 u16 val = 0;
687
684 dev_dbg(&intf->dev, "%s called with pm message 0x%04x\n", 688 dev_dbg(&intf->dev, "%s called with pm message 0x%04x\n",
685 __func__, message.event); 689 __func__, message.event);
686 690
691 if (PMSG_IS_AUTO(message)) {
692 if (mutex_trylock(&ucr->dev_mutex)) {
693 rtsx_usb_get_card_status(ucr, &val);
694 mutex_unlock(&ucr->dev_mutex);
695
696 /* Defer the autosuspend if card exists */
697 if (val & (SD_CD | MS_CD))
698 return -EAGAIN;
699 } else {
700 /* There is an ongoing operation*/
701 return -EAGAIN;
702 }
703 }
704
687 return 0; 705 return 0;
688} 706}
689 707
diff --git a/drivers/mfd/smsc-ece1099.c b/drivers/mfd/smsc-ece1099.c
index 90112d4cc905..03246880d484 100644
--- a/drivers/mfd/smsc-ece1099.c
+++ b/drivers/mfd/smsc-ece1099.c
@@ -24,7 +24,7 @@
24#include <linux/mfd/smsc.h> 24#include <linux/mfd/smsc.h>
25#include <linux/of_platform.h> 25#include <linux/of_platform.h>
26 26
27static struct regmap_config smsc_regmap_config = { 27static const struct regmap_config smsc_regmap_config = {
28 .reg_bits = 8, 28 .reg_bits = 8,
29 .val_bits = 8, 29 .val_bits = 8,
30 .max_register = SMSC_VEN_ID_H, 30 .max_register = SMSC_VEN_ID_H,
diff --git a/drivers/mfd/sun6i-prcm.c b/drivers/mfd/sun6i-prcm.c
index 2f2e9f062571..191173166d65 100644
--- a/drivers/mfd/sun6i-prcm.c
+++ b/drivers/mfd/sun6i-prcm.c
@@ -41,6 +41,14 @@ static const struct resource sun6i_a31_apb0_gates_clk_res[] = {
41 }, 41 },
42}; 42};
43 43
44static const struct resource sun6i_a31_ir_clk_res[] = {
45 {
46 .start = 0x54,
47 .end = 0x57,
48 .flags = IORESOURCE_MEM,
49 },
50};
51
44static const struct resource sun6i_a31_apb0_rstc_res[] = { 52static const struct resource sun6i_a31_apb0_rstc_res[] = {
45 { 53 {
46 .start = 0xb0, 54 .start = 0xb0,
@@ -69,6 +77,12 @@ static const struct mfd_cell sun6i_a31_prcm_subdevs[] = {
69 .resources = sun6i_a31_apb0_gates_clk_res, 77 .resources = sun6i_a31_apb0_gates_clk_res,
70 }, 78 },
71 { 79 {
80 .name = "sun6i-a31-ir-clk",
81 .of_compatible = "allwinner,sun4i-a10-mod0-clk",
82 .num_resources = ARRAY_SIZE(sun6i_a31_ir_clk_res),
83 .resources = sun6i_a31_ir_clk_res,
84 },
85 {
72 .name = "sun6i-a31-apb0-clock-reset", 86 .name = "sun6i-a31-apb0-clock-reset",
73 .of_compatible = "allwinner,sun6i-a31-clock-reset", 87 .of_compatible = "allwinner,sun6i-a31-clock-reset",
74 .num_resources = ARRAY_SIZE(sun6i_a31_apb0_rstc_res), 88 .num_resources = ARRAY_SIZE(sun6i_a31_apb0_rstc_res),
diff --git a/drivers/mfd/tps65217.c b/drivers/mfd/tps65217.c
index 80a919a8ca97..7d1cfc1d3ce0 100644
--- a/drivers/mfd/tps65217.c
+++ b/drivers/mfd/tps65217.c
@@ -145,7 +145,7 @@ int tps65217_clear_bits(struct tps65217 *tps, unsigned int reg,
145} 145}
146EXPORT_SYMBOL_GPL(tps65217_clear_bits); 146EXPORT_SYMBOL_GPL(tps65217_clear_bits);
147 147
148static struct regmap_config tps65217_regmap_config = { 148static const struct regmap_config tps65217_regmap_config = {
149 .reg_bits = 8, 149 .reg_bits = 8,
150 .val_bits = 8, 150 .val_bits = 8,
151 151
diff --git a/drivers/mfd/tps65218.c b/drivers/mfd/tps65218.c
index d6b764349f9d..7af11a8b9753 100644
--- a/drivers/mfd/tps65218.c
+++ b/drivers/mfd/tps65218.c
@@ -135,7 +135,7 @@ static const struct regmap_access_table tps65218_volatile_table = {
135 .n_yes_ranges = ARRAY_SIZE(tps65218_yes_ranges), 135 .n_yes_ranges = ARRAY_SIZE(tps65218_yes_ranges),
136}; 136};
137 137
138static struct regmap_config tps65218_regmap_config = { 138static const struct regmap_config tps65218_regmap_config = {
139 .reg_bits = 8, 139 .reg_bits = 8,
140 .val_bits = 8, 140 .val_bits = 8,
141 .cache_type = REGCACHE_RBTREE, 141 .cache_type = REGCACHE_RBTREE,
diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c
index db11b4f40611..489674a2497e 100644
--- a/drivers/mfd/twl-core.c
+++ b/drivers/mfd/twl-core.c
@@ -207,7 +207,7 @@ static struct twl_mapping twl4030_map[] = {
207 { 2, TWL5031_BASEADD_INTERRUPTS }, 207 { 2, TWL5031_BASEADD_INTERRUPTS },
208}; 208};
209 209
210static struct reg_default twl4030_49_defaults[] = { 210static const struct reg_default twl4030_49_defaults[] = {
211 /* Audio Registers */ 211 /* Audio Registers */
212 { 0x01, 0x00}, /* CODEC_MODE */ 212 { 0x01, 0x00}, /* CODEC_MODE */
213 { 0x02, 0x00}, /* OPTION */ 213 { 0x02, 0x00}, /* OPTION */
@@ -306,7 +306,7 @@ static const struct regmap_access_table twl4030_49_volatile_table = {
306 .n_yes_ranges = ARRAY_SIZE(twl4030_49_volatile_ranges), 306 .n_yes_ranges = ARRAY_SIZE(twl4030_49_volatile_ranges),
307}; 307};
308 308
309static struct regmap_config twl4030_regmap_config[4] = { 309static const struct regmap_config twl4030_regmap_config[4] = {
310 { 310 {
311 /* Address 0x48 */ 311 /* Address 0x48 */
312 .reg_bits = 8, 312 .reg_bits = 8,
@@ -369,7 +369,7 @@ static struct twl_mapping twl6030_map[] = {
369 { 1, TWL6030_BASEADD_GASGAUGE }, 369 { 1, TWL6030_BASEADD_GASGAUGE },
370}; 370};
371 371
372static struct regmap_config twl6030_regmap_config[3] = { 372static const struct regmap_config twl6030_regmap_config[3] = {
373 { 373 {
374 /* Address 0x48 */ 374 /* Address 0x48 */
375 .reg_bits = 8, 375 .reg_bits = 8,
@@ -1087,7 +1087,7 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
1087 struct twl4030_platform_data *pdata = dev_get_platdata(&client->dev); 1087 struct twl4030_platform_data *pdata = dev_get_platdata(&client->dev);
1088 struct device_node *node = client->dev.of_node; 1088 struct device_node *node = client->dev.of_node;
1089 struct platform_device *pdev; 1089 struct platform_device *pdev;
1090 struct regmap_config *twl_regmap_config; 1090 const struct regmap_config *twl_regmap_config;
1091 int irq_base = 0; 1091 int irq_base = 0;
1092 int status; 1092 int status;
1093 unsigned i, num_slaves; 1093 unsigned i, num_slaves;
diff --git a/drivers/mfd/twl6040.c b/drivers/mfd/twl6040.c
index 9687645162ae..f71ee3dbc2a2 100644
--- a/drivers/mfd/twl6040.c
+++ b/drivers/mfd/twl6040.c
@@ -44,7 +44,7 @@
44#define VIBRACTRL_MEMBER(reg) ((reg == TWL6040_REG_VIBCTLL) ? 0 : 1) 44#define VIBRACTRL_MEMBER(reg) ((reg == TWL6040_REG_VIBCTLL) ? 0 : 1)
45#define TWL6040_NUM_SUPPLIES (2) 45#define TWL6040_NUM_SUPPLIES (2)
46 46
47static struct reg_default twl6040_defaults[] = { 47static const struct reg_default twl6040_defaults[] = {
48 { 0x01, 0x4B }, /* REG_ASICID (ro) */ 48 { 0x01, 0x4B }, /* REG_ASICID (ro) */
49 { 0x02, 0x00 }, /* REG_ASICREV (ro) */ 49 { 0x02, 0x00 }, /* REG_ASICREV (ro) */
50 { 0x03, 0x00 }, /* REG_INTID */ 50 { 0x03, 0x00 }, /* REG_INTID */
@@ -580,7 +580,7 @@ static bool twl6040_writeable_reg(struct device *dev, unsigned int reg)
580 } 580 }
581} 581}
582 582
583static struct regmap_config twl6040_regmap_config = { 583static const struct regmap_config twl6040_regmap_config = {
584 .reg_bits = 8, 584 .reg_bits = 8,
585 .val_bits = 8, 585 .val_bits = 8,
586 586
diff --git a/drivers/mfd/wm8994-core.c b/drivers/mfd/wm8994-core.c
index 6ca9d25cc3f0..53ae5af5d6e4 100644
--- a/drivers/mfd/wm8994-core.c
+++ b/drivers/mfd/wm8994-core.c
@@ -36,12 +36,12 @@
36static const struct mfd_cell wm8994_regulator_devs[] = { 36static const struct mfd_cell wm8994_regulator_devs[] = {
37 { 37 {
38 .name = "wm8994-ldo", 38 .name = "wm8994-ldo",
39 .id = 1, 39 .id = 0,
40 .pm_runtime_no_callbacks = true, 40 .pm_runtime_no_callbacks = true,
41 }, 41 },
42 { 42 {
43 .name = "wm8994-ldo", 43 .name = "wm8994-ldo",
44 .id = 2, 44 .id = 1,
45 .pm_runtime_no_callbacks = true, 45 .pm_runtime_no_callbacks = true,
46 }, 46 },
47}; 47};
@@ -344,7 +344,7 @@ static int wm8994_device_init(struct wm8994 *wm8994, int irq)
344 dev_set_drvdata(wm8994->dev, wm8994); 344 dev_set_drvdata(wm8994->dev, wm8994);
345 345
346 /* Add the on-chip regulators first for bootstrapping */ 346 /* Add the on-chip regulators first for bootstrapping */
347 ret = mfd_add_devices(wm8994->dev, -1, 347 ret = mfd_add_devices(wm8994->dev, 0,
348 wm8994_regulator_devs, 348 wm8994_regulator_devs,
349 ARRAY_SIZE(wm8994_regulator_devs), 349 ARRAY_SIZE(wm8994_regulator_devs),
350 NULL, 0, NULL); 350 NULL, 0, NULL);
diff --git a/drivers/regulator/qcom_rpm-regulator.c b/drivers/regulator/qcom_rpm-regulator.c
index e8647f7cf25e..00c5cc3d9546 100644
--- a/drivers/regulator/qcom_rpm-regulator.c
+++ b/drivers/regulator/qcom_rpm-regulator.c
@@ -205,6 +205,7 @@ static int rpm_reg_write(struct qcom_rpm_reg *vreg,
205 vreg->val[req->word] |= value << req->shift; 205 vreg->val[req->word] |= value << req->shift;
206 206
207 return qcom_rpm_write(vreg->rpm, 207 return qcom_rpm_write(vreg->rpm,
208 QCOM_RPM_ACTIVE_STATE,
208 vreg->resource, 209 vreg->resource,
209 vreg->val, 210 vreg->val,
210 vreg->parts->request_len); 211 vreg->parts->request_len);
diff --git a/include/dt-bindings/mfd/qcom-rpm.h b/include/dt-bindings/mfd/qcom-rpm.h
new file mode 100644
index 000000000000..388a6f3d6165
--- /dev/null
+++ b/include/dt-bindings/mfd/qcom-rpm.h
@@ -0,0 +1,154 @@
1/*
2 * This header provides constants for the Qualcomm RPM bindings.
3 */
4
5#ifndef _DT_BINDINGS_MFD_QCOM_RPM_H
6#define _DT_BINDINGS_MFD_QCOM_RPM_H
7
8/*
9 * Constants use to identify individual resources in the RPM.
10 */
11#define QCOM_RPM_APPS_FABRIC_ARB 1
12#define QCOM_RPM_APPS_FABRIC_CLK 2
13#define QCOM_RPM_APPS_FABRIC_HALT 3
14#define QCOM_RPM_APPS_FABRIC_IOCTL 4
15#define QCOM_RPM_APPS_FABRIC_MODE 5
16#define QCOM_RPM_APPS_L2_CACHE_CTL 6
17#define QCOM_RPM_CFPB_CLK 7
18#define QCOM_RPM_CXO_BUFFERS 8
19#define QCOM_RPM_CXO_CLK 9
20#define QCOM_RPM_DAYTONA_FABRIC_CLK 10
21#define QCOM_RPM_DDR_DMM 11
22#define QCOM_RPM_EBI1_CLK 12
23#define QCOM_RPM_HDMI_SWITCH 13
24#define QCOM_RPM_MMFPB_CLK 14
25#define QCOM_RPM_MM_FABRIC_ARB 15
26#define QCOM_RPM_MM_FABRIC_CLK 16
27#define QCOM_RPM_MM_FABRIC_HALT 17
28#define QCOM_RPM_MM_FABRIC_IOCTL 18
29#define QCOM_RPM_MM_FABRIC_MODE 19
30#define QCOM_RPM_PLL_4 20
31#define QCOM_RPM_PM8058_LDO0 21
32#define QCOM_RPM_PM8058_LDO1 22
33#define QCOM_RPM_PM8058_LDO2 23
34#define QCOM_RPM_PM8058_LDO3 24
35#define QCOM_RPM_PM8058_LDO4 25
36#define QCOM_RPM_PM8058_LDO5 26
37#define QCOM_RPM_PM8058_LDO6 27
38#define QCOM_RPM_PM8058_LDO7 28
39#define QCOM_RPM_PM8058_LDO8 29
40#define QCOM_RPM_PM8058_LDO9 30
41#define QCOM_RPM_PM8058_LDO10 31
42#define QCOM_RPM_PM8058_LDO11 32
43#define QCOM_RPM_PM8058_LDO12 33
44#define QCOM_RPM_PM8058_LDO13 34
45#define QCOM_RPM_PM8058_LDO14 35
46#define QCOM_RPM_PM8058_LDO15 36
47#define QCOM_RPM_PM8058_LDO16 37
48#define QCOM_RPM_PM8058_LDO17 38
49#define QCOM_RPM_PM8058_LDO18 39
50#define QCOM_RPM_PM8058_LDO19 40
51#define QCOM_RPM_PM8058_LDO20 41
52#define QCOM_RPM_PM8058_LDO21 42
53#define QCOM_RPM_PM8058_LDO22 43
54#define QCOM_RPM_PM8058_LDO23 44
55#define QCOM_RPM_PM8058_LDO24 45
56#define QCOM_RPM_PM8058_LDO25 46
57#define QCOM_RPM_PM8058_LVS0 47
58#define QCOM_RPM_PM8058_LVS1 48
59#define QCOM_RPM_PM8058_NCP 49
60#define QCOM_RPM_PM8058_SMPS0 50
61#define QCOM_RPM_PM8058_SMPS1 51
62#define QCOM_RPM_PM8058_SMPS2 52
63#define QCOM_RPM_PM8058_SMPS3 53
64#define QCOM_RPM_PM8058_SMPS4 54
65#define QCOM_RPM_PM8821_LDO1 55
66#define QCOM_RPM_PM8821_SMPS1 56
67#define QCOM_RPM_PM8821_SMPS2 57
68#define QCOM_RPM_PM8901_LDO0 58
69#define QCOM_RPM_PM8901_LDO1 59
70#define QCOM_RPM_PM8901_LDO2 60
71#define QCOM_RPM_PM8901_LDO3 61
72#define QCOM_RPM_PM8901_LDO4 62
73#define QCOM_RPM_PM8901_LDO5 63
74#define QCOM_RPM_PM8901_LDO6 64
75#define QCOM_RPM_PM8901_LVS0 65
76#define QCOM_RPM_PM8901_LVS1 66
77#define QCOM_RPM_PM8901_LVS2 67
78#define QCOM_RPM_PM8901_LVS3 68
79#define QCOM_RPM_PM8901_MVS 69
80#define QCOM_RPM_PM8901_SMPS0 70
81#define QCOM_RPM_PM8901_SMPS1 71
82#define QCOM_RPM_PM8901_SMPS2 72
83#define QCOM_RPM_PM8901_SMPS3 73
84#define QCOM_RPM_PM8901_SMPS4 74
85#define QCOM_RPM_PM8921_CLK1 75
86#define QCOM_RPM_PM8921_CLK2 76
87#define QCOM_RPM_PM8921_LDO1 77
88#define QCOM_RPM_PM8921_LDO2 78
89#define QCOM_RPM_PM8921_LDO3 79
90#define QCOM_RPM_PM8921_LDO4 80
91#define QCOM_RPM_PM8921_LDO5 81
92#define QCOM_RPM_PM8921_LDO6 82
93#define QCOM_RPM_PM8921_LDO7 83
94#define QCOM_RPM_PM8921_LDO8 84
95#define QCOM_RPM_PM8921_LDO9 85
96#define QCOM_RPM_PM8921_LDO10 86
97#define QCOM_RPM_PM8921_LDO11 87
98#define QCOM_RPM_PM8921_LDO12 88
99#define QCOM_RPM_PM8921_LDO13 89
100#define QCOM_RPM_PM8921_LDO14 90
101#define QCOM_RPM_PM8921_LDO15 91
102#define QCOM_RPM_PM8921_LDO16 92
103#define QCOM_RPM_PM8921_LDO17 93
104#define QCOM_RPM_PM8921_LDO18 94
105#define QCOM_RPM_PM8921_LDO19 95
106#define QCOM_RPM_PM8921_LDO20 96
107#define QCOM_RPM_PM8921_LDO21 97
108#define QCOM_RPM_PM8921_LDO22 98
109#define QCOM_RPM_PM8921_LDO23 99
110#define QCOM_RPM_PM8921_LDO24 100
111#define QCOM_RPM_PM8921_LDO25 101
112#define QCOM_RPM_PM8921_LDO26 102
113#define QCOM_RPM_PM8921_LDO27 103
114#define QCOM_RPM_PM8921_LDO28 104
115#define QCOM_RPM_PM8921_LDO29 105
116#define QCOM_RPM_PM8921_LVS1 106
117#define QCOM_RPM_PM8921_LVS2 107
118#define QCOM_RPM_PM8921_LVS3 108
119#define QCOM_RPM_PM8921_LVS4 109
120#define QCOM_RPM_PM8921_LVS5 110
121#define QCOM_RPM_PM8921_LVS6 111
122#define QCOM_RPM_PM8921_LVS7 112
123#define QCOM_RPM_PM8921_MVS 113
124#define QCOM_RPM_PM8921_NCP 114
125#define QCOM_RPM_PM8921_SMPS1 115
126#define QCOM_RPM_PM8921_SMPS2 116
127#define QCOM_RPM_PM8921_SMPS3 117
128#define QCOM_RPM_PM8921_SMPS4 118
129#define QCOM_RPM_PM8921_SMPS5 119
130#define QCOM_RPM_PM8921_SMPS6 120
131#define QCOM_RPM_PM8921_SMPS7 121
132#define QCOM_RPM_PM8921_SMPS8 122
133#define QCOM_RPM_PXO_CLK 123
134#define QCOM_RPM_QDSS_CLK 124
135#define QCOM_RPM_SFPB_CLK 125
136#define QCOM_RPM_SMI_CLK 126
137#define QCOM_RPM_SYS_FABRIC_ARB 127
138#define QCOM_RPM_SYS_FABRIC_CLK 128
139#define QCOM_RPM_SYS_FABRIC_HALT 129
140#define QCOM_RPM_SYS_FABRIC_IOCTL 130
141#define QCOM_RPM_SYS_FABRIC_MODE 131
142#define QCOM_RPM_USB_OTG_SWITCH 132
143#define QCOM_RPM_VDDMIN_GPIO 133
144
145/*
146 * Constants used to select force mode for regulators.
147 */
148#define QCOM_RPM_FORCE_MODE_NONE 0
149#define QCOM_RPM_FORCE_MODE_LPM 1
150#define QCOM_RPM_FORCE_MODE_HPM 2
151#define QCOM_RPM_FORCE_MODE_AUTO 3
152#define QCOM_RPM_FORCE_MODE_BYPASS 4
153
154#endif
diff --git a/include/linux/mfd/axp20x.h b/include/linux/mfd/axp20x.h
index 81589d176ae8..dfabd6db7ddf 100644
--- a/include/linux/mfd/axp20x.h
+++ b/include/linux/mfd/axp20x.h
@@ -124,10 +124,27 @@ enum {
124#define AXP288_PMIC_ADC_H 0x56 124#define AXP288_PMIC_ADC_H 0x56
125#define AXP288_PMIC_ADC_L 0x57 125#define AXP288_PMIC_ADC_L 0x57
126#define AXP288_ADC_TS_PIN_CTRL 0x84 126#define AXP288_ADC_TS_PIN_CTRL 0x84
127
128#define AXP288_PMIC_ADC_EN 0x84 127#define AXP288_PMIC_ADC_EN 0x84
129#define AXP288_FG_TUNE5 0xed
130 128
129/* Fuel Gauge */
130#define AXP288_FG_RDC1_REG 0xba
131#define AXP288_FG_RDC0_REG 0xbb
132#define AXP288_FG_OCVH_REG 0xbc
133#define AXP288_FG_OCVL_REG 0xbd
134#define AXP288_FG_OCV_CURVE_REG 0xc0
135#define AXP288_FG_DES_CAP1_REG 0xe0
136#define AXP288_FG_DES_CAP0_REG 0xe1
137#define AXP288_FG_CC_MTR1_REG 0xe2
138#define AXP288_FG_CC_MTR0_REG 0xe3
139#define AXP288_FG_OCV_CAP_REG 0xe4
140#define AXP288_FG_CC_CAP_REG 0xe5
141#define AXP288_FG_LOW_CAP_REG 0xe6
142#define AXP288_FG_TUNE0 0xe8
143#define AXP288_FG_TUNE1 0xe9
144#define AXP288_FG_TUNE2 0xea
145#define AXP288_FG_TUNE3 0xeb
146#define AXP288_FG_TUNE4 0xec
147#define AXP288_FG_TUNE5 0xed
131 148
132/* Regulators IDs */ 149/* Regulators IDs */
133enum { 150enum {
@@ -236,4 +253,26 @@ struct axp20x_dev {
236 const struct regmap_irq_chip *regmap_irq_chip; 253 const struct regmap_irq_chip *regmap_irq_chip;
237}; 254};
238 255
256#define BATTID_LEN 64
257#define OCV_CURVE_SIZE 32
258#define MAX_THERM_CURVE_SIZE 25
259#define PD_DEF_MIN_TEMP 0
260#define PD_DEF_MAX_TEMP 55
261
262struct axp20x_fg_pdata {
263 char battid[BATTID_LEN + 1];
264 int design_cap;
265 int min_volt;
266 int max_volt;
267 int max_temp;
268 int min_temp;
269 int cap1;
270 int cap0;
271 int rdc1;
272 int rdc0;
273 int ocv_curve[OCV_CURVE_SIZE];
274 int tcsz;
275 int thermistor_curve[MAX_THERM_CURVE_SIZE][2];
276};
277
239#endif /* __LINUX_MFD_AXP20X_H */ 278#endif /* __LINUX_MFD_AXP20X_H */
diff --git a/include/linux/mfd/da9063/core.h b/include/linux/mfd/da9063/core.h
index b92a3262f8f6..79f4d822ba13 100644
--- a/include/linux/mfd/da9063/core.h
+++ b/include/linux/mfd/da9063/core.h
@@ -36,6 +36,7 @@ enum da9063_models {
36enum da9063_variant_codes { 36enum da9063_variant_codes {
37 PMIC_DA9063_AD = 0x3, 37 PMIC_DA9063_AD = 0x3,
38 PMIC_DA9063_BB = 0x5, 38 PMIC_DA9063_BB = 0x5,
39 PMIC_DA9063_CA = 0x6,
39}; 40};
40 41
41/* Interrupts */ 42/* Interrupts */
diff --git a/include/linux/mfd/da9150/core.h b/include/linux/mfd/da9150/core.h
new file mode 100644
index 000000000000..76e668933a77
--- /dev/null
+++ b/include/linux/mfd/da9150/core.h
@@ -0,0 +1,68 @@
1/*
2 * DA9150 MFD Driver - Core Data
3 *
4 * Copyright (c) 2014 Dialog Semiconductor
5 *
6 * Author: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#ifndef __DA9150_CORE_H
15#define __DA9150_CORE_H
16
17#include <linux/device.h>
18#include <linux/interrupt.h>
19#include <linux/regmap.h>
20
21/* I2C address paging */
22#define DA9150_REG_PAGE_SHIFT 8
23#define DA9150_REG_PAGE_MASK 0xFF
24
25/* IRQs */
26#define DA9150_NUM_IRQ_REGS 4
27#define DA9150_IRQ_VBUS 0
28#define DA9150_IRQ_CHG 1
29#define DA9150_IRQ_TCLASS 2
30#define DA9150_IRQ_TJUNC 3
31#define DA9150_IRQ_VFAULT 4
32#define DA9150_IRQ_CONF 5
33#define DA9150_IRQ_DAT 6
34#define DA9150_IRQ_DTYPE 7
35#define DA9150_IRQ_ID 8
36#define DA9150_IRQ_ADP 9
37#define DA9150_IRQ_SESS_END 10
38#define DA9150_IRQ_SESS_VLD 11
39#define DA9150_IRQ_FG 12
40#define DA9150_IRQ_GP 13
41#define DA9150_IRQ_TBAT 14
42#define DA9150_IRQ_GPIOA 15
43#define DA9150_IRQ_GPIOB 16
44#define DA9150_IRQ_GPIOC 17
45#define DA9150_IRQ_GPIOD 18
46#define DA9150_IRQ_GPADC 19
47#define DA9150_IRQ_WKUP 20
48
49struct da9150_pdata {
50 int irq_base;
51};
52
53struct da9150 {
54 struct device *dev;
55 struct regmap *regmap;
56 struct regmap_irq_chip_data *regmap_irq_data;
57 int irq;
58 int irq_base;
59};
60
61/* Device I/O */
62u8 da9150_reg_read(struct da9150 *da9150, u16 reg);
63void da9150_reg_write(struct da9150 *da9150, u16 reg, u8 val);
64void da9150_set_bits(struct da9150 *da9150, u16 reg, u8 mask, u8 val);
65
66void da9150_bulk_read(struct da9150 *da9150, u16 reg, int count, u8 *buf);
67void da9150_bulk_write(struct da9150 *da9150, u16 reg, int count, const u8 *buf);
68#endif /* __DA9150_CORE_H */
diff --git a/include/linux/mfd/da9150/registers.h b/include/linux/mfd/da9150/registers.h
new file mode 100644
index 000000000000..27ca6ee4d840
--- /dev/null
+++ b/include/linux/mfd/da9150/registers.h
@@ -0,0 +1,1155 @@
1/*
2 * DA9150 MFD Driver - Registers
3 *
4 * Copyright (c) 2014 Dialog Semiconductor
5 *
6 * Author: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#ifndef __DA9150_REGISTERS_H
15#define __DA9150_REGISTERS_H
16
17#include <linux/bitops.h>
18
19/* Registers */
20#define DA9150_PAGE_CON 0x000
21#define DA9150_STATUS_A 0x068
22#define DA9150_STATUS_B 0x069
23#define DA9150_STATUS_C 0x06A
24#define DA9150_STATUS_D 0x06B
25#define DA9150_STATUS_E 0x06C
26#define DA9150_STATUS_F 0x06D
27#define DA9150_STATUS_G 0x06E
28#define DA9150_STATUS_H 0x06F
29#define DA9150_STATUS_I 0x070
30#define DA9150_STATUS_J 0x071
31#define DA9150_STATUS_K 0x072
32#define DA9150_STATUS_L 0x073
33#define DA9150_STATUS_N 0x074
34#define DA9150_FAULT_LOG_A 0x076
35#define DA9150_FAULT_LOG_B 0x077
36#define DA9150_EVENT_E 0x078
37#define DA9150_EVENT_F 0x079
38#define DA9150_EVENT_G 0x07A
39#define DA9150_EVENT_H 0x07B
40#define DA9150_IRQ_MASK_E 0x07C
41#define DA9150_IRQ_MASK_F 0x07D
42#define DA9150_IRQ_MASK_G 0x07E
43#define DA9150_IRQ_MASK_H 0x07F
44#define DA9150_PAGE_CON_1 0x080
45#define DA9150_CONFIG_A 0x0E0
46#define DA9150_CONFIG_B 0x0E1
47#define DA9150_CONFIG_C 0x0E2
48#define DA9150_CONFIG_D 0x0E3
49#define DA9150_CONFIG_E 0x0E4
50#define DA9150_CONTROL_A 0x0E5
51#define DA9150_CONTROL_B 0x0E6
52#define DA9150_CONTROL_C 0x0E7
53#define DA9150_GPIO_A_B 0x0E8
54#define DA9150_GPIO_C_D 0x0E9
55#define DA9150_GPIO_MODE_CONT 0x0EA
56#define DA9150_GPIO_CTRL_B 0x0EB
57#define DA9150_GPIO_CTRL_A 0x0EC
58#define DA9150_GPIO_CTRL_C 0x0ED
59#define DA9150_GPIO_CFG_A 0x0EE
60#define DA9150_GPIO_CFG_B 0x0EF
61#define DA9150_GPIO_CFG_C 0x0F0
62#define DA9150_GPADC_MAN 0x0F2
63#define DA9150_GPADC_RES_A 0x0F4
64#define DA9150_GPADC_RES_B 0x0F5
65#define DA9150_PAGE_CON_2 0x100
66#define DA9150_OTP_CONT_SHARED 0x101
67#define DA9150_INTERFACE_SHARED 0x105
68#define DA9150_CONFIG_A_SHARED 0x106
69#define DA9150_CONFIG_D_SHARED 0x109
70#define DA9150_ADETVB_CFG_C 0x150
71#define DA9150_ADETD_STAT 0x151
72#define DA9150_ADET_CMPSTAT 0x152
73#define DA9150_ADET_CTRL_A 0x153
74#define DA9150_ADETVB_CFG_B 0x154
75#define DA9150_ADETVB_CFG_A 0x155
76#define DA9150_ADETAC_CFG_A 0x156
77#define DA9150_ADDETAC_CFG_B 0x157
78#define DA9150_ADETAC_CFG_C 0x158
79#define DA9150_ADETAC_CFG_D 0x159
80#define DA9150_ADETVB_CFG_D 0x15A
81#define DA9150_ADETID_CFG_A 0x15B
82#define DA9150_ADET_RID_PT_CHG_H 0x15C
83#define DA9150_ADET_RID_PT_CHG_L 0x15D
84#define DA9150_PPR_TCTR_B 0x160
85#define DA9150_PPR_BKCTRL_A 0x163
86#define DA9150_PPR_BKCFG_A 0x164
87#define DA9150_PPR_BKCFG_B 0x165
88#define DA9150_PPR_CHGCTRL_A 0x166
89#define DA9150_PPR_CHGCTRL_B 0x167
90#define DA9150_PPR_CHGCTRL_C 0x168
91#define DA9150_PPR_TCTR_A 0x169
92#define DA9150_PPR_CHGCTRL_D 0x16A
93#define DA9150_PPR_CHGCTRL_E 0x16B
94#define DA9150_PPR_CHGCTRL_F 0x16C
95#define DA9150_PPR_CHGCTRL_G 0x16D
96#define DA9150_PPR_CHGCTRL_H 0x16E
97#define DA9150_PPR_CHGCTRL_I 0x16F
98#define DA9150_PPR_CHGCTRL_J 0x170
99#define DA9150_PPR_CHGCTRL_K 0x171
100#define DA9150_PPR_CHGCTRL_L 0x172
101#define DA9150_PPR_CHGCTRL_M 0x173
102#define DA9150_PPR_THYST_A 0x174
103#define DA9150_PPR_THYST_B 0x175
104#define DA9150_PPR_THYST_C 0x176
105#define DA9150_PPR_THYST_D 0x177
106#define DA9150_PPR_THYST_E 0x178
107#define DA9150_PPR_THYST_F 0x179
108#define DA9150_PPR_THYST_G 0x17A
109#define DA9150_PAGE_CON_3 0x180
110#define DA9150_PAGE_CON_4 0x200
111#define DA9150_PAGE_CON_5 0x280
112#define DA9150_PAGE_CON_6 0x300
113#define DA9150_COREBTLD_STAT_A 0x302
114#define DA9150_COREBTLD_CTRL_A 0x303
115#define DA9150_CORE_CONFIG_A 0x304
116#define DA9150_CORE_CONFIG_C 0x305
117#define DA9150_CORE_CONFIG_B 0x306
118#define DA9150_CORE_CFG_DATA_A 0x307
119#define DA9150_CORE_CFG_DATA_B 0x308
120#define DA9150_CORE_CMD_A 0x309
121#define DA9150_CORE_DATA_A 0x30A
122#define DA9150_CORE_DATA_B 0x30B
123#define DA9150_CORE_DATA_C 0x30C
124#define DA9150_CORE_DATA_D 0x30D
125#define DA9150_CORE2WIRE_STAT_A 0x310
126#define DA9150_CORE2WIRE_CTRL_A 0x311
127#define DA9150_FW_CTRL_A 0x312
128#define DA9150_FW_CTRL_C 0x313
129#define DA9150_FW_CTRL_D 0x314
130#define DA9150_FG_CTRL_A 0x315
131#define DA9150_FG_CTRL_B 0x316
132#define DA9150_FW_CTRL_E 0x317
133#define DA9150_FW_CTRL_B 0x318
134#define DA9150_GPADC_CMAN 0x320
135#define DA9150_GPADC_CRES_A 0x322
136#define DA9150_GPADC_CRES_B 0x323
137#define DA9150_CC_CFG_A 0x328
138#define DA9150_CC_CFG_B 0x329
139#define DA9150_CC_ICHG_RES_A 0x32A
140#define DA9150_CC_ICHG_RES_B 0x32B
141#define DA9150_CC_IAVG_RES_A 0x32C
142#define DA9150_CC_IAVG_RES_B 0x32D
143#define DA9150_TAUX_CTRL_A 0x330
144#define DA9150_TAUX_RELOAD_H 0x332
145#define DA9150_TAUX_RELOAD_L 0x333
146#define DA9150_TAUX_VALUE_H 0x334
147#define DA9150_TAUX_VALUE_L 0x335
148#define DA9150_AUX_DATA_0 0x338
149#define DA9150_AUX_DATA_1 0x339
150#define DA9150_AUX_DATA_2 0x33A
151#define DA9150_AUX_DATA_3 0x33B
152#define DA9150_BIF_CTRL 0x340
153#define DA9150_TBAT_CTRL_A 0x342
154#define DA9150_TBAT_CTRL_B 0x343
155#define DA9150_TBAT_RES_A 0x344
156#define DA9150_TBAT_RES_B 0x345
157
158/* DA9150_PAGE_CON = 0x000 */
159#define DA9150_PAGE_SHIFT 0
160#define DA9150_PAGE_MASK (0x3f << 0)
161#define DA9150_I2C_PAGE_SHIFT 1
162#define DA9150_I2C_PAGE_MASK (0x1f << 1)
163#define DA9150_WRITE_MODE_SHIFT 6
164#define DA9150_WRITE_MODE_MASK BIT(6)
165#define DA9150_REVERT_SHIFT 7
166#define DA9150_REVERT_MASK BIT(7)
167
168/* DA9150_STATUS_A = 0x068 */
169#define DA9150_WKUP_STAT_SHIFT 2
170#define DA9150_WKUP_STAT_MASK (0x0f << 2)
171#define DA9150_SLEEP_STAT_SHIFT 6
172#define DA9150_SLEEP_STAT_MASK (0x03 << 6)
173
174/* DA9150_STATUS_B = 0x069 */
175#define DA9150_VFAULT_STAT_SHIFT 0
176#define DA9150_VFAULT_STAT_MASK BIT(0)
177#define DA9150_TFAULT_STAT_SHIFT 1
178#define DA9150_TFAULT_STAT_MASK BIT(1)
179
180/* DA9150_STATUS_C = 0x06A */
181#define DA9150_VDD33_STAT_SHIFT 0
182#define DA9150_VDD33_STAT_MASK BIT(0)
183#define DA9150_VDD33_SLEEP_SHIFT 1
184#define DA9150_VDD33_SLEEP_MASK BIT(1)
185#define DA9150_LFOSC_STAT_SHIFT 7
186#define DA9150_LFOSC_STAT_MASK BIT(7)
187
188/* DA9150_STATUS_D = 0x06B */
189#define DA9150_GPIOA_STAT_SHIFT 0
190#define DA9150_GPIOA_STAT_MASK BIT(0)
191#define DA9150_GPIOB_STAT_SHIFT 1
192#define DA9150_GPIOB_STAT_MASK BIT(1)
193#define DA9150_GPIOC_STAT_SHIFT 2
194#define DA9150_GPIOC_STAT_MASK BIT(2)
195#define DA9150_GPIOD_STAT_SHIFT 3
196#define DA9150_GPIOD_STAT_MASK BIT(3)
197
198/* DA9150_STATUS_E = 0x06C */
199#define DA9150_DTYPE_SHIFT 0
200#define DA9150_DTYPE_MASK (0x1f << 0)
201#define DA9150_DTYPE_DT_NIL (0x00 << 0)
202#define DA9150_DTYPE_DT_USB_OTG BIT(0)
203#define DA9150_DTYPE_DT_USB_STD (0x02 << 0)
204#define DA9150_DTYPE_DT_USB_CHG (0x03 << 0)
205#define DA9150_DTYPE_DT_ACA_CHG (0x04 << 0)
206#define DA9150_DTYPE_DT_ACA_OTG (0x05 << 0)
207#define DA9150_DTYPE_DT_ACA_DOC (0x06 << 0)
208#define DA9150_DTYPE_DT_DED_CHG (0x07 << 0)
209#define DA9150_DTYPE_DT_CR5_CHG (0x08 << 0)
210#define DA9150_DTYPE_DT_CR4_CHG (0x0c << 0)
211#define DA9150_DTYPE_DT_PT_CHG (0x11 << 0)
212#define DA9150_DTYPE_DT_NN_ACC (0x16 << 0)
213#define DA9150_DTYPE_DT_NN_CHG (0x17 << 0)
214
215/* DA9150_STATUS_F = 0x06D */
216#define DA9150_SESS_VLD_SHIFT 0
217#define DA9150_SESS_VLD_MASK BIT(0)
218#define DA9150_ID_ERR_SHIFT 1
219#define DA9150_ID_ERR_MASK BIT(1)
220#define DA9150_PT_CHG_SHIFT 2
221#define DA9150_PT_CHG_MASK BIT(2)
222
223/* DA9150_STATUS_G = 0x06E */
224#define DA9150_RID_SHIFT 0
225#define DA9150_RID_MASK (0xff << 0)
226
227/* DA9150_STATUS_H = 0x06F */
228#define DA9150_VBUS_STAT_SHIFT 0
229#define DA9150_VBUS_STAT_MASK (0x07 << 0)
230#define DA9150_VBUS_STAT_OFF (0x00 << 0)
231#define DA9150_VBUS_STAT_WAIT BIT(0)
232#define DA9150_VBUS_STAT_CHG (0x02 << 0)
233#define DA9150_VBUS_TRED_SHIFT 3
234#define DA9150_VBUS_TRED_MASK BIT(3)
235#define DA9150_VBUS_DROP_STAT_SHIFT 4
236#define DA9150_VBUS_DROP_STAT_MASK (0x0f << 4)
237
238/* DA9150_STATUS_I = 0x070 */
239#define DA9150_VBUS_ISET_STAT_SHIFT 0
240#define DA9150_VBUS_ISET_STAT_MASK (0x1f << 0)
241#define DA9150_VBUS_OT_SHIFT 7
242#define DA9150_VBUS_OT_MASK BIT(7)
243
244/* DA9150_STATUS_J = 0x071 */
245#define DA9150_CHG_STAT_SHIFT 0
246#define DA9150_CHG_STAT_MASK (0x0f << 0)
247#define DA9150_CHG_STAT_OFF (0x00 << 0)
248#define DA9150_CHG_STAT_SUSP BIT(0)
249#define DA9150_CHG_STAT_ACT (0x02 << 0)
250#define DA9150_CHG_STAT_PRE (0x03 << 0)
251#define DA9150_CHG_STAT_CC (0x04 << 0)
252#define DA9150_CHG_STAT_CV (0x05 << 0)
253#define DA9150_CHG_STAT_FULL (0x06 << 0)
254#define DA9150_CHG_STAT_TEMP (0x07 << 0)
255#define DA9150_CHG_STAT_TIME (0x08 << 0)
256#define DA9150_CHG_STAT_BAT (0x09 << 0)
257#define DA9150_CHG_TEMP_SHIFT 4
258#define DA9150_CHG_TEMP_MASK (0x07 << 4)
259#define DA9150_CHG_TEMP_UNDER (0x06 << 4)
260#define DA9150_CHG_TEMP_OVER (0x07 << 4)
261#define DA9150_CHG_IEND_STAT_SHIFT 7
262#define DA9150_CHG_IEND_STAT_MASK BIT(7)
263
264/* DA9150_STATUS_K = 0x072 */
265#define DA9150_CHG_IAV_H_SHIFT 0
266#define DA9150_CHG_IAV_H_MASK (0xff << 0)
267
268/* DA9150_STATUS_L = 0x073 */
269#define DA9150_CHG_IAV_L_SHIFT 5
270#define DA9150_CHG_IAV_L_MASK (0x07 << 5)
271
272/* DA9150_STATUS_N = 0x074 */
273#define DA9150_CHG_TIME_SHIFT 1
274#define DA9150_CHG_TIME_MASK BIT(1)
275#define DA9150_CHG_TRED_SHIFT 2
276#define DA9150_CHG_TRED_MASK BIT(2)
277#define DA9150_CHG_TJUNC_CLASS_SHIFT 3
278#define DA9150_CHG_TJUNC_CLASS_MASK (0x07 << 3)
279#define DA9150_CHG_TJUNC_CLASS_6 (0x06 << 3)
280#define DA9150_EBS_STAT_SHIFT 6
281#define DA9150_EBS_STAT_MASK BIT(6)
282#define DA9150_CHG_BAT_REMOVED_SHIFT 7
283#define DA9150_CHG_BAT_REMOVED_MASK BIT(7)
284
285/* DA9150_FAULT_LOG_A = 0x076 */
286#define DA9150_TEMP_FAULT_SHIFT 0
287#define DA9150_TEMP_FAULT_MASK BIT(0)
288#define DA9150_VSYS_FAULT_SHIFT 1
289#define DA9150_VSYS_FAULT_MASK BIT(1)
290#define DA9150_START_FAULT_SHIFT 2
291#define DA9150_START_FAULT_MASK BIT(2)
292#define DA9150_EXT_FAULT_SHIFT 3
293#define DA9150_EXT_FAULT_MASK BIT(3)
294#define DA9150_POR_FAULT_SHIFT 4
295#define DA9150_POR_FAULT_MASK BIT(4)
296
297/* DA9150_FAULT_LOG_B = 0x077 */
298#define DA9150_VBUS_FAULT_SHIFT 0
299#define DA9150_VBUS_FAULT_MASK BIT(0)
300#define DA9150_OTG_FAULT_SHIFT 1
301#define DA9150_OTG_FAULT_MASK BIT(1)
302
303/* DA9150_EVENT_E = 0x078 */
304#define DA9150_E_VBUS_SHIFT 0
305#define DA9150_E_VBUS_MASK BIT(0)
306#define DA9150_E_CHG_SHIFT 1
307#define DA9150_E_CHG_MASK BIT(1)
308#define DA9150_E_TCLASS_SHIFT 2
309#define DA9150_E_TCLASS_MASK BIT(2)
310#define DA9150_E_TJUNC_SHIFT 3
311#define DA9150_E_TJUNC_MASK BIT(3)
312#define DA9150_E_VFAULT_SHIFT 4
313#define DA9150_E_VFAULT_MASK BIT(4)
314#define DA9150_EVENTS_H_SHIFT 5
315#define DA9150_EVENTS_H_MASK BIT(5)
316#define DA9150_EVENTS_G_SHIFT 6
317#define DA9150_EVENTS_G_MASK BIT(6)
318#define DA9150_EVENTS_F_SHIFT 7
319#define DA9150_EVENTS_F_MASK BIT(7)
320
321/* DA9150_EVENT_F = 0x079 */
322#define DA9150_E_CONF_SHIFT 0
323#define DA9150_E_CONF_MASK BIT(0)
324#define DA9150_E_DAT_SHIFT 1
325#define DA9150_E_DAT_MASK BIT(1)
326#define DA9150_E_DTYPE_SHIFT 3
327#define DA9150_E_DTYPE_MASK BIT(3)
328#define DA9150_E_ID_SHIFT 4
329#define DA9150_E_ID_MASK BIT(4)
330#define DA9150_E_ADP_SHIFT 5
331#define DA9150_E_ADP_MASK BIT(5)
332#define DA9150_E_SESS_END_SHIFT 6
333#define DA9150_E_SESS_END_MASK BIT(6)
334#define DA9150_E_SESS_VLD_SHIFT 7
335#define DA9150_E_SESS_VLD_MASK BIT(7)
336
337/* DA9150_EVENT_G = 0x07A */
338#define DA9150_E_FG_SHIFT 0
339#define DA9150_E_FG_MASK BIT(0)
340#define DA9150_E_GP_SHIFT 1
341#define DA9150_E_GP_MASK BIT(1)
342#define DA9150_E_TBAT_SHIFT 2
343#define DA9150_E_TBAT_MASK BIT(2)
344#define DA9150_E_GPIOA_SHIFT 3
345#define DA9150_E_GPIOA_MASK BIT(3)
346#define DA9150_E_GPIOB_SHIFT 4
347#define DA9150_E_GPIOB_MASK BIT(4)
348#define DA9150_E_GPIOC_SHIFT 5
349#define DA9150_E_GPIOC_MASK BIT(5)
350#define DA9150_E_GPIOD_SHIFT 6
351#define DA9150_E_GPIOD_MASK BIT(6)
352#define DA9150_E_GPADC_SHIFT 7
353#define DA9150_E_GPADC_MASK BIT(7)
354
355/* DA9150_EVENT_H = 0x07B */
356#define DA9150_E_WKUP_SHIFT 0
357#define DA9150_E_WKUP_MASK BIT(0)
358
359/* DA9150_IRQ_MASK_E = 0x07C */
360#define DA9150_M_VBUS_SHIFT 0
361#define DA9150_M_VBUS_MASK BIT(0)
362#define DA9150_M_CHG_SHIFT 1
363#define DA9150_M_CHG_MASK BIT(1)
364#define DA9150_M_TJUNC_SHIFT 3
365#define DA9150_M_TJUNC_MASK BIT(3)
366#define DA9150_M_VFAULT_SHIFT 4
367#define DA9150_M_VFAULT_MASK BIT(4)
368
369/* DA9150_IRQ_MASK_F = 0x07D */
370#define DA9150_M_CONF_SHIFT 0
371#define DA9150_M_CONF_MASK BIT(0)
372#define DA9150_M_DAT_SHIFT 1
373#define DA9150_M_DAT_MASK BIT(1)
374#define DA9150_M_DTYPE_SHIFT 3
375#define DA9150_M_DTYPE_MASK BIT(3)
376#define DA9150_M_ID_SHIFT 4
377#define DA9150_M_ID_MASK BIT(4)
378#define DA9150_M_ADP_SHIFT 5
379#define DA9150_M_ADP_MASK BIT(5)
380#define DA9150_M_SESS_END_SHIFT 6
381#define DA9150_M_SESS_END_MASK BIT(6)
382#define DA9150_M_SESS_VLD_SHIFT 7
383#define DA9150_M_SESS_VLD_MASK BIT(7)
384
385/* DA9150_IRQ_MASK_G = 0x07E */
386#define DA9150_M_FG_SHIFT 0
387#define DA9150_M_FG_MASK BIT(0)
388#define DA9150_M_GP_SHIFT 1
389#define DA9150_M_GP_MASK BIT(1)
390#define DA9150_M_TBAT_SHIFT 2
391#define DA9150_M_TBAT_MASK BIT(2)
392#define DA9150_M_GPIOA_SHIFT 3
393#define DA9150_M_GPIOA_MASK BIT(3)
394#define DA9150_M_GPIOB_SHIFT 4
395#define DA9150_M_GPIOB_MASK BIT(4)
396#define DA9150_M_GPIOC_SHIFT 5
397#define DA9150_M_GPIOC_MASK BIT(5)
398#define DA9150_M_GPIOD_SHIFT 6
399#define DA9150_M_GPIOD_MASK BIT(6)
400#define DA9150_M_GPADC_SHIFT 7
401#define DA9150_M_GPADC_MASK BIT(7)
402
403/* DA9150_IRQ_MASK_H = 0x07F */
404#define DA9150_M_WKUP_SHIFT 0
405#define DA9150_M_WKUP_MASK BIT(0)
406
407/* DA9150_PAGE_CON_1 = 0x080 */
408#define DA9150_PAGE_SHIFT 0
409#define DA9150_PAGE_MASK (0x3f << 0)
410#define DA9150_WRITE_MODE_SHIFT 6
411#define DA9150_WRITE_MODE_MASK BIT(6)
412#define DA9150_REVERT_SHIFT 7
413#define DA9150_REVERT_MASK BIT(7)
414
415/* DA9150_CONFIG_A = 0x0E0 */
416#define DA9150_RESET_DUR_SHIFT 0
417#define DA9150_RESET_DUR_MASK (0x03 << 0)
418#define DA9150_RESET_EXT_SHIFT 2
419#define DA9150_RESET_EXT_MASK (0x03 << 2)
420#define DA9150_START_MAX_SHIFT 4
421#define DA9150_START_MAX_MASK (0x03 << 4)
422#define DA9150_PS_WAIT_EN_SHIFT 6
423#define DA9150_PS_WAIT_EN_MASK BIT(6)
424#define DA9150_PS_DISABLE_DIRECT_SHIFT 7
425#define DA9150_PS_DISABLE_DIRECT_MASK BIT(7)
426
427/* DA9150_CONFIG_B = 0x0E1 */
428#define DA9150_VFAULT_ADJ_SHIFT 0
429#define DA9150_VFAULT_ADJ_MASK (0x0f << 0)
430#define DA9150_VFAULT_HYST_SHIFT 4
431#define DA9150_VFAULT_HYST_MASK (0x07 << 4)
432#define DA9150_VFAULT_EN_SHIFT 7
433#define DA9150_VFAULT_EN_MASK BIT(7)
434
435/* DA9150_CONFIG_C = 0x0E2 */
436#define DA9150_VSYS_MIN_SHIFT 3
437#define DA9150_VSYS_MIN_MASK (0x1f << 3)
438
439/* DA9150_CONFIG_D = 0x0E3 */
440#define DA9150_LFOSC_EXT_SHIFT 0
441#define DA9150_LFOSC_EXT_MASK BIT(0)
442#define DA9150_VDD33_DWN_SHIFT 1
443#define DA9150_VDD33_DWN_MASK BIT(1)
444#define DA9150_WKUP_PM_EN_SHIFT 2
445#define DA9150_WKUP_PM_EN_MASK BIT(2)
446#define DA9150_WKUP_CE_SEL_SHIFT 3
447#define DA9150_WKUP_CE_SEL_MASK (0x03 << 3)
448#define DA9150_WKUP_CLK32K_EN_SHIFT 5
449#define DA9150_WKUP_CLK32K_EN_MASK BIT(5)
450#define DA9150_DISABLE_DEL_SHIFT 7
451#define DA9150_DISABLE_DEL_MASK BIT(7)
452
453/* DA9150_CONFIG_E = 0x0E4 */
454#define DA9150_PM_SPKSUP_DIS_SHIFT 0
455#define DA9150_PM_SPKSUP_DIS_MASK BIT(0)
456#define DA9150_PM_MERGE_SHIFT 1
457#define DA9150_PM_MERGE_MASK BIT(1)
458#define DA9150_PM_SR_OFF_SHIFT 2
459#define DA9150_PM_SR_OFF_MASK BIT(2)
460#define DA9150_PM_TIMEOUT_EN_SHIFT 3
461#define DA9150_PM_TIMEOUT_EN_MASK BIT(3)
462#define DA9150_PM_DLY_SEL_SHIFT 4
463#define DA9150_PM_DLY_SEL_MASK (0x07 << 4)
464#define DA9150_PM_OUT_DLY_SEL_SHIFT 7
465#define DA9150_PM_OUT_DLY_SEL_MASK BIT(7)
466
467/* DA9150_CONTROL_A = 0x0E5 */
468#define DA9150_VDD33_SL_SHIFT 0
469#define DA9150_VDD33_SL_MASK BIT(0)
470#define DA9150_VDD33_LPM_SHIFT 1
471#define DA9150_VDD33_LPM_MASK (0x03 << 1)
472#define DA9150_VDD33_EN_SHIFT 3
473#define DA9150_VDD33_EN_MASK BIT(3)
474#define DA9150_GPI_LPM_SHIFT 6
475#define DA9150_GPI_LPM_MASK BIT(6)
476#define DA9150_PM_IF_LPM_SHIFT 7
477#define DA9150_PM_IF_LPM_MASK BIT(7)
478
479/* DA9150_CONTROL_B = 0x0E6 */
480#define DA9150_LPM_SHIFT 0
481#define DA9150_LPM_MASK BIT(0)
482#define DA9150_RESET_SHIFT 1
483#define DA9150_RESET_MASK BIT(1)
484#define DA9150_RESET_USRCONF_EN_SHIFT 2
485#define DA9150_RESET_USRCONF_EN_MASK BIT(2)
486
487/* DA9150_CONTROL_C = 0x0E7 */
488#define DA9150_DISABLE_SHIFT 0
489#define DA9150_DISABLE_MASK BIT(0)
490
491/* DA9150_GPIO_A_B = 0x0E8 */
492#define DA9150_GPIOA_PIN_SHIFT 0
493#define DA9150_GPIOA_PIN_MASK (0x07 << 0)
494#define DA9150_GPIOA_PIN_GPI (0x00 << 0)
495#define DA9150_GPIOA_PIN_GPO_OD BIT(0)
496#define DA9150_GPIOA_TYPE_SHIFT 3
497#define DA9150_GPIOA_TYPE_MASK BIT(3)
498#define DA9150_GPIOB_PIN_SHIFT 4
499#define DA9150_GPIOB_PIN_MASK (0x07 << 4)
500#define DA9150_GPIOB_PIN_GPI (0x00 << 4)
501#define DA9150_GPIOB_PIN_GPO_OD BIT(4)
502#define DA9150_GPIOB_TYPE_SHIFT 7
503#define DA9150_GPIOB_TYPE_MASK BIT(7)
504
505/* DA9150_GPIO_C_D = 0x0E9 */
506#define DA9150_GPIOC_PIN_SHIFT 0
507#define DA9150_GPIOC_PIN_MASK (0x07 << 0)
508#define DA9150_GPIOC_PIN_GPI (0x00 << 0)
509#define DA9150_GPIOC_PIN_GPO_OD BIT(0)
510#define DA9150_GPIOC_TYPE_SHIFT 3
511#define DA9150_GPIOC_TYPE_MASK BIT(3)
512#define DA9150_GPIOD_PIN_SHIFT 4
513#define DA9150_GPIOD_PIN_MASK (0x07 << 4)
514#define DA9150_GPIOD_PIN_GPI (0x00 << 4)
515#define DA9150_GPIOD_PIN_GPO_OD BIT(4)
516#define DA9150_GPIOD_TYPE_SHIFT 7
517#define DA9150_GPIOD_TYPE_MASK BIT(7)
518
519/* DA9150_GPIO_MODE_CONT = 0x0EA */
520#define DA9150_GPIOA_MODE_SHIFT 0
521#define DA9150_GPIOA_MODE_MASK BIT(0)
522#define DA9150_GPIOB_MODE_SHIFT 1
523#define DA9150_GPIOB_MODE_MASK BIT(1)
524#define DA9150_GPIOC_MODE_SHIFT 2
525#define DA9150_GPIOC_MODE_MASK BIT(2)
526#define DA9150_GPIOD_MODE_SHIFT 3
527#define DA9150_GPIOD_MODE_MASK BIT(3)
528#define DA9150_GPIOA_CONT_SHIFT 4
529#define DA9150_GPIOA_CONT_MASK BIT(4)
530#define DA9150_GPIOB_CONT_SHIFT 5
531#define DA9150_GPIOB_CONT_MASK BIT(5)
532#define DA9150_GPIOC_CONT_SHIFT 6
533#define DA9150_GPIOC_CONT_MASK BIT(6)
534#define DA9150_GPIOD_CONT_SHIFT 7
535#define DA9150_GPIOD_CONT_MASK BIT(7)
536
537/* DA9150_GPIO_CTRL_B = 0x0EB */
538#define DA9150_WAKE_PIN_SHIFT 0
539#define DA9150_WAKE_PIN_MASK (0x03 << 0)
540#define DA9150_WAKE_MODE_SHIFT 2
541#define DA9150_WAKE_MODE_MASK BIT(2)
542#define DA9150_WAKE_CONT_SHIFT 3
543#define DA9150_WAKE_CONT_MASK BIT(3)
544#define DA9150_WAKE_DLY_SHIFT 4
545#define DA9150_WAKE_DLY_MASK BIT(4)
546
547/* DA9150_GPIO_CTRL_A = 0x0EC */
548#define DA9150_GPIOA_ANAEN_SHIFT 0
549#define DA9150_GPIOA_ANAEN_MASK BIT(0)
550#define DA9150_GPIOB_ANAEN_SHIFT 1
551#define DA9150_GPIOB_ANAEN_MASK BIT(1)
552#define DA9150_GPIOC_ANAEN_SHIFT 2
553#define DA9150_GPIOC_ANAEN_MASK BIT(2)
554#define DA9150_GPIOD_ANAEN_SHIFT 3
555#define DA9150_GPIOD_ANAEN_MASK BIT(3)
556#define DA9150_GPIO_ANAEN 0x01
557#define DA9150_GPIO_ANAEN_MASK 0x0F
558#define DA9150_CHGLED_PIN_SHIFT 5
559#define DA9150_CHGLED_PIN_MASK (0x07 << 5)
560
561/* DA9150_GPIO_CTRL_C = 0x0ED */
562#define DA9150_CHGBL_DUR_SHIFT 0
563#define DA9150_CHGBL_DUR_MASK (0x03 << 0)
564#define DA9150_CHGBL_DBL_SHIFT 2
565#define DA9150_CHGBL_DBL_MASK BIT(2)
566#define DA9150_CHGBL_FRQ_SHIFT 3
567#define DA9150_CHGBL_FRQ_MASK (0x03 << 3)
568#define DA9150_CHGBL_FLKR_SHIFT 5
569#define DA9150_CHGBL_FLKR_MASK BIT(5)
570
571/* DA9150_GPIO_CFG_A = 0x0EE */
572#define DA9150_CE_LPM_DEB_SHIFT 0
573#define DA9150_CE_LPM_DEB_MASK (0x07 << 0)
574
575/* DA9150_GPIO_CFG_B = 0x0EF */
576#define DA9150_GPIOA_PUPD_SHIFT 0
577#define DA9150_GPIOA_PUPD_MASK BIT(0)
578#define DA9150_GPIOB_PUPD_SHIFT 1
579#define DA9150_GPIOB_PUPD_MASK BIT(1)
580#define DA9150_GPIOC_PUPD_SHIFT 2
581#define DA9150_GPIOC_PUPD_MASK BIT(2)
582#define DA9150_GPIOD_PUPD_SHIFT 3
583#define DA9150_GPIOD_PUPD_MASK BIT(3)
584#define DA9150_GPIO_PUPD_MASK (0xF << 0)
585#define DA9150_GPI_DEB_SHIFT 4
586#define DA9150_GPI_DEB_MASK (0x07 << 4)
587#define DA9150_LPM_EN_SHIFT 7
588#define DA9150_LPM_EN_MASK BIT(7)
589
590/* DA9150_GPIO_CFG_C = 0x0F0 */
591#define DA9150_GPI_V_SHIFT 0
592#define DA9150_GPI_V_MASK BIT(0)
593#define DA9150_VDDIO_INT_SHIFT 1
594#define DA9150_VDDIO_INT_MASK BIT(1)
595#define DA9150_FAULT_PIN_SHIFT 3
596#define DA9150_FAULT_PIN_MASK (0x07 << 3)
597#define DA9150_FAULT_TYPE_SHIFT 6
598#define DA9150_FAULT_TYPE_MASK BIT(6)
599#define DA9150_NIRQ_PUPD_SHIFT 7
600#define DA9150_NIRQ_PUPD_MASK BIT(7)
601
602/* DA9150_GPADC_MAN = 0x0F2 */
603#define DA9150_GPADC_EN_SHIFT 0
604#define DA9150_GPADC_EN_MASK BIT(0)
605#define DA9150_GPADC_MUX_SHIFT 1
606#define DA9150_GPADC_MUX_MASK (0x1f << 1)
607
608/* DA9150_GPADC_RES_A = 0x0F4 */
609#define DA9150_GPADC_RES_H_SHIFT 0
610#define DA9150_GPADC_RES_H_MASK (0xff << 0)
611
612/* DA9150_GPADC_RES_B = 0x0F5 */
613#define DA9150_GPADC_RUN_SHIFT 0
614#define DA9150_GPADC_RUN_MASK BIT(0)
615#define DA9150_GPADC_RES_L_SHIFT 6
616#define DA9150_GPADC_RES_L_MASK (0x03 << 6)
617#define DA9150_GPADC_RES_L_BITS 2
618
619/* DA9150_PAGE_CON_2 = 0x100 */
620#define DA9150_PAGE_SHIFT 0
621#define DA9150_PAGE_MASK (0x3f << 0)
622#define DA9150_WRITE_MODE_SHIFT 6
623#define DA9150_WRITE_MODE_MASK BIT(6)
624#define DA9150_REVERT_SHIFT 7
625#define DA9150_REVERT_MASK BIT(7)
626
627/* DA9150_OTP_CONT_SHARED = 0x101 */
628#define DA9150_PC_DONE_SHIFT 3
629#define DA9150_PC_DONE_MASK BIT(3)
630
631/* DA9150_INTERFACE_SHARED = 0x105 */
632#define DA9150_IF_BASE_ADDR_SHIFT 4
633#define DA9150_IF_BASE_ADDR_MASK (0x0f << 4)
634
635/* DA9150_CONFIG_A_SHARED = 0x106 */
636#define DA9150_NIRQ_VDD_SHIFT 1
637#define DA9150_NIRQ_VDD_MASK BIT(1)
638#define DA9150_NIRQ_PIN_SHIFT 2
639#define DA9150_NIRQ_PIN_MASK BIT(2)
640#define DA9150_NIRQ_TYPE_SHIFT 3
641#define DA9150_NIRQ_TYPE_MASK BIT(3)
642#define DA9150_PM_IF_V_SHIFT 4
643#define DA9150_PM_IF_V_MASK BIT(4)
644#define DA9150_PM_IF_FMP_SHIFT 5
645#define DA9150_PM_IF_FMP_MASK BIT(5)
646#define DA9150_PM_IF_HSM_SHIFT 6
647#define DA9150_PM_IF_HSM_MASK BIT(6)
648
649/* DA9150_CONFIG_D_SHARED = 0x109 */
650#define DA9150_NIRQ_MODE_SHIFT 1
651#define DA9150_NIRQ_MODE_MASK BIT(1)
652
653/* DA9150_ADETVB_CFG_C = 0x150 */
654#define DA9150_TADP_RISE_SHIFT 0
655#define DA9150_TADP_RISE_MASK (0xff << 0)
656
657/* DA9150_ADETD_STAT = 0x151 */
658#define DA9150_DCD_STAT_SHIFT 0
659#define DA9150_DCD_STAT_MASK BIT(0)
660#define DA9150_PCD_STAT_SHIFT 1
661#define DA9150_PCD_STAT_MASK (0x03 << 1)
662#define DA9150_SCD_STAT_SHIFT 3
663#define DA9150_SCD_STAT_MASK (0x03 << 3)
664#define DA9150_DP_STAT_SHIFT 5
665#define DA9150_DP_STAT_MASK BIT(5)
666#define DA9150_DM_STAT_SHIFT 6
667#define DA9150_DM_STAT_MASK BIT(6)
668
669/* DA9150_ADET_CMPSTAT = 0x152 */
670#define DA9150_DP_COMP_SHIFT 1
671#define DA9150_DP_COMP_MASK BIT(1)
672#define DA9150_DM_COMP_SHIFT 2
673#define DA9150_DM_COMP_MASK BIT(2)
674#define DA9150_ADP_SNS_COMP_SHIFT 3
675#define DA9150_ADP_SNS_COMP_MASK BIT(3)
676#define DA9150_ADP_PRB_COMP_SHIFT 4
677#define DA9150_ADP_PRB_COMP_MASK BIT(4)
678#define DA9150_ID_COMP_SHIFT 5
679#define DA9150_ID_COMP_MASK BIT(5)
680
681/* DA9150_ADET_CTRL_A = 0x153 */
682#define DA9150_AID_DAT_SHIFT 0
683#define DA9150_AID_DAT_MASK BIT(0)
684#define DA9150_AID_ID_SHIFT 1
685#define DA9150_AID_ID_MASK BIT(1)
686#define DA9150_AID_TRIG_SHIFT 2
687#define DA9150_AID_TRIG_MASK BIT(2)
688
689/* DA9150_ADETVB_CFG_B = 0x154 */
690#define DA9150_VB_MODE_SHIFT 0
691#define DA9150_VB_MODE_MASK (0x03 << 0)
692#define DA9150_VB_MODE_VB_SESS BIT(0)
693
694#define DA9150_TADP_PRB_SHIFT 2
695#define DA9150_TADP_PRB_MASK BIT(2)
696#define DA9150_DAT_RPD_EXT_SHIFT 5
697#define DA9150_DAT_RPD_EXT_MASK BIT(5)
698#define DA9150_CONF_RPD_SHIFT 6
699#define DA9150_CONF_RPD_MASK BIT(6)
700#define DA9150_CONF_SRP_SHIFT 7
701#define DA9150_CONF_SRP_MASK BIT(7)
702
703/* DA9150_ADETVB_CFG_A = 0x155 */
704#define DA9150_AID_MODE_SHIFT 0
705#define DA9150_AID_MODE_MASK (0x03 << 0)
706#define DA9150_AID_EXT_POL_SHIFT 2
707#define DA9150_AID_EXT_POL_MASK BIT(2)
708
709/* DA9150_ADETAC_CFG_A = 0x156 */
710#define DA9150_ISET_CDP_SHIFT 0
711#define DA9150_ISET_CDP_MASK (0x1f << 0)
712#define DA9150_CONF_DBP_SHIFT 5
713#define DA9150_CONF_DBP_MASK BIT(5)
714
715/* DA9150_ADDETAC_CFG_B = 0x157 */
716#define DA9150_ISET_DCHG_SHIFT 0
717#define DA9150_ISET_DCHG_MASK (0x1f << 0)
718#define DA9150_CONF_GPIOA_SHIFT 5
719#define DA9150_CONF_GPIOA_MASK BIT(5)
720#define DA9150_CONF_GPIOB_SHIFT 6
721#define DA9150_CONF_GPIOB_MASK BIT(6)
722#define DA9150_AID_VB_SHIFT 7
723#define DA9150_AID_VB_MASK BIT(7)
724
725/* DA9150_ADETAC_CFG_C = 0x158 */
726#define DA9150_ISET_DEF_SHIFT 0
727#define DA9150_ISET_DEF_MASK (0x1f << 0)
728#define DA9150_CONF_MODE_SHIFT 5
729#define DA9150_CONF_MODE_MASK (0x03 << 5)
730#define DA9150_AID_CR_DIS_SHIFT 7
731#define DA9150_AID_CR_DIS_MASK BIT(7)
732
733/* DA9150_ADETAC_CFG_D = 0x159 */
734#define DA9150_ISET_UNIT_SHIFT 0
735#define DA9150_ISET_UNIT_MASK (0x1f << 0)
736#define DA9150_AID_UNCLAMP_SHIFT 5
737#define DA9150_AID_UNCLAMP_MASK BIT(5)
738
739/* DA9150_ADETVB_CFG_D = 0x15A */
740#define DA9150_ID_MODE_SHIFT 0
741#define DA9150_ID_MODE_MASK (0x03 << 0)
742#define DA9150_DAT_MODE_SHIFT 2
743#define DA9150_DAT_MODE_MASK (0x0f << 2)
744#define DA9150_DAT_SWP_SHIFT 6
745#define DA9150_DAT_SWP_MASK BIT(6)
746#define DA9150_DAT_CLAMP_EXT_SHIFT 7
747#define DA9150_DAT_CLAMP_EXT_MASK BIT(7)
748
749/* DA9150_ADETID_CFG_A = 0x15B */
750#define DA9150_TID_POLL_SHIFT 0
751#define DA9150_TID_POLL_MASK (0x07 << 0)
752#define DA9150_RID_CONV_SHIFT 3
753#define DA9150_RID_CONV_MASK BIT(3)
754
755/* DA9150_ADET_RID_PT_CHG_H = 0x15C */
756#define DA9150_RID_PT_CHG_H_SHIFT 0
757#define DA9150_RID_PT_CHG_H_MASK (0xff << 0)
758
759/* DA9150_ADET_RID_PT_CHG_L = 0x15D */
760#define DA9150_RID_PT_CHG_L_SHIFT 6
761#define DA9150_RID_PT_CHG_L_MASK (0x03 << 6)
762
763/* DA9150_PPR_TCTR_B = 0x160 */
764#define DA9150_CHG_TCTR_VAL_SHIFT 0
765#define DA9150_CHG_TCTR_VAL_MASK (0xff << 0)
766
767/* DA9150_PPR_BKCTRL_A = 0x163 */
768#define DA9150_VBUS_MODE_SHIFT 0
769#define DA9150_VBUS_MODE_MASK (0x03 << 0)
770#define DA9150_VBUS_MODE_CHG BIT(0)
771#define DA9150_VBUS_MODE_OTG (0x02 << 0)
772#define DA9150_VBUS_LPM_SHIFT 2
773#define DA9150_VBUS_LPM_MASK (0x03 << 2)
774#define DA9150_VBUS_SUSP_SHIFT 4
775#define DA9150_VBUS_SUSP_MASK BIT(4)
776#define DA9150_VBUS_PWM_SHIFT 5
777#define DA9150_VBUS_PWM_MASK BIT(5)
778#define DA9150_VBUS_ISO_SHIFT 6
779#define DA9150_VBUS_ISO_MASK BIT(6)
780#define DA9150_VBUS_LDO_SHIFT 7
781#define DA9150_VBUS_LDO_MASK BIT(7)
782
783/* DA9150_PPR_BKCFG_A = 0x164 */
784#define DA9150_VBUS_ISET_SHIFT 0
785#define DA9150_VBUS_ISET_MASK (0x1f << 0)
786#define DA9150_VBUS_IMAX_SHIFT 5
787#define DA9150_VBUS_IMAX_MASK BIT(5)
788#define DA9150_VBUS_IOTG_SHIFT 6
789#define DA9150_VBUS_IOTG_MASK (0x03 << 6)
790
791/* DA9150_PPR_BKCFG_B = 0x165 */
792#define DA9150_VBUS_DROP_SHIFT 0
793#define DA9150_VBUS_DROP_MASK (0x0f << 0)
794#define DA9150_VBUS_FAULT_DIS_SHIFT 6
795#define DA9150_VBUS_FAULT_DIS_MASK BIT(6)
796#define DA9150_OTG_FAULT_DIS_SHIFT 7
797#define DA9150_OTG_FAULT_DIS_MASK BIT(7)
798
799/* DA9150_PPR_CHGCTRL_A = 0x166 */
800#define DA9150_CHG_EN_SHIFT 0
801#define DA9150_CHG_EN_MASK BIT(0)
802
803/* DA9150_PPR_CHGCTRL_B = 0x167 */
804#define DA9150_CHG_VBAT_SHIFT 0
805#define DA9150_CHG_VBAT_MASK (0x1f << 0)
806#define DA9150_CHG_VDROP_SHIFT 6
807#define DA9150_CHG_VDROP_MASK (0x03 << 6)
808
809/* DA9150_PPR_CHGCTRL_C = 0x168 */
810#define DA9150_CHG_VFAULT_SHIFT 0
811#define DA9150_CHG_VFAULT_MASK (0x0f << 0)
812#define DA9150_CHG_IPRE_SHIFT 4
813#define DA9150_CHG_IPRE_MASK (0x03 << 4)
814
815/* DA9150_PPR_TCTR_A = 0x169 */
816#define DA9150_CHG_TCTR_SHIFT 0
817#define DA9150_CHG_TCTR_MASK (0x07 << 0)
818#define DA9150_CHG_TCTR_MODE_SHIFT 4
819#define DA9150_CHG_TCTR_MODE_MASK BIT(4)
820
821/* DA9150_PPR_CHGCTRL_D = 0x16A */
822#define DA9150_CHG_IBAT_SHIFT 0
823#define DA9150_CHG_IBAT_MASK (0xff << 0)
824
825/* DA9150_PPR_CHGCTRL_E = 0x16B */
826#define DA9150_CHG_IEND_SHIFT 0
827#define DA9150_CHG_IEND_MASK (0xff << 0)
828
829/* DA9150_PPR_CHGCTRL_F = 0x16C */
830#define DA9150_CHG_VCOLD_SHIFT 0
831#define DA9150_CHG_VCOLD_MASK (0x1f << 0)
832#define DA9150_TBAT_TQA_EN_SHIFT 6
833#define DA9150_TBAT_TQA_EN_MASK BIT(6)
834#define DA9150_TBAT_TDP_EN_SHIFT 7
835#define DA9150_TBAT_TDP_EN_MASK BIT(7)
836
837/* DA9150_PPR_CHGCTRL_G = 0x16D */
838#define DA9150_CHG_VWARM_SHIFT 0
839#define DA9150_CHG_VWARM_MASK (0x1f << 0)
840
841/* DA9150_PPR_CHGCTRL_H = 0x16E */
842#define DA9150_CHG_VHOT_SHIFT 0
843#define DA9150_CHG_VHOT_MASK (0x1f << 0)
844
845/* DA9150_PPR_CHGCTRL_I = 0x16F */
846#define DA9150_CHG_ICOLD_SHIFT 0
847#define DA9150_CHG_ICOLD_MASK (0xff << 0)
848
849/* DA9150_PPR_CHGCTRL_J = 0x170 */
850#define DA9150_CHG_IWARM_SHIFT 0
851#define DA9150_CHG_IWARM_MASK (0xff << 0)
852
853/* DA9150_PPR_CHGCTRL_K = 0x171 */
854#define DA9150_CHG_IHOT_SHIFT 0
855#define DA9150_CHG_IHOT_MASK (0xff << 0)
856
857/* DA9150_PPR_CHGCTRL_L = 0x172 */
858#define DA9150_CHG_IBAT_TRED_SHIFT 0
859#define DA9150_CHG_IBAT_TRED_MASK (0xff << 0)
860
861/* DA9150_PPR_CHGCTRL_M = 0x173 */
862#define DA9150_CHG_VFLOAT_SHIFT 0
863#define DA9150_CHG_VFLOAT_MASK (0x0f << 0)
864#define DA9150_CHG_LPM_SHIFT 5
865#define DA9150_CHG_LPM_MASK BIT(5)
866#define DA9150_CHG_NBLO_SHIFT 6
867#define DA9150_CHG_NBLO_MASK BIT(6)
868#define DA9150_EBS_EN_SHIFT 7
869#define DA9150_EBS_EN_MASK BIT(7)
870
871/* DA9150_PPR_THYST_A = 0x174 */
872#define DA9150_TBAT_T1_SHIFT 0
873#define DA9150_TBAT_T1_MASK (0xff << 0)
874
875/* DA9150_PPR_THYST_B = 0x175 */
876#define DA9150_TBAT_T2_SHIFT 0
877#define DA9150_TBAT_T2_MASK (0xff << 0)
878
879/* DA9150_PPR_THYST_C = 0x176 */
880#define DA9150_TBAT_T3_SHIFT 0
881#define DA9150_TBAT_T3_MASK (0xff << 0)
882
883/* DA9150_PPR_THYST_D = 0x177 */
884#define DA9150_TBAT_T4_SHIFT 0
885#define DA9150_TBAT_T4_MASK (0xff << 0)
886
887/* DA9150_PPR_THYST_E = 0x178 */
888#define DA9150_TBAT_T5_SHIFT 0
889#define DA9150_TBAT_T5_MASK (0xff << 0)
890
891/* DA9150_PPR_THYST_F = 0x179 */
892#define DA9150_TBAT_H1_SHIFT 0
893#define DA9150_TBAT_H1_MASK (0xff << 0)
894
895/* DA9150_PPR_THYST_G = 0x17A */
896#define DA9150_TBAT_H5_SHIFT 0
897#define DA9150_TBAT_H5_MASK (0xff << 0)
898
899/* DA9150_PAGE_CON_3 = 0x180 */
900#define DA9150_PAGE_SHIFT 0
901#define DA9150_PAGE_MASK (0x3f << 0)
902#define DA9150_WRITE_MODE_SHIFT 6
903#define DA9150_WRITE_MODE_MASK BIT(6)
904#define DA9150_REVERT_SHIFT 7
905#define DA9150_REVERT_MASK BIT(7)
906
907/* DA9150_PAGE_CON_4 = 0x200 */
908#define DA9150_PAGE_SHIFT 0
909#define DA9150_PAGE_MASK (0x3f << 0)
910#define DA9150_WRITE_MODE_SHIFT 6
911#define DA9150_WRITE_MODE_MASK BIT(6)
912#define DA9150_REVERT_SHIFT 7
913#define DA9150_REVERT_MASK BIT(7)
914
915/* DA9150_PAGE_CON_5 = 0x280 */
916#define DA9150_PAGE_SHIFT 0
917#define DA9150_PAGE_MASK (0x3f << 0)
918#define DA9150_WRITE_MODE_SHIFT 6
919#define DA9150_WRITE_MODE_MASK BIT(6)
920#define DA9150_REVERT_SHIFT 7
921#define DA9150_REVERT_MASK BIT(7)
922
923/* DA9150_PAGE_CON_6 = 0x300 */
924#define DA9150_PAGE_SHIFT 0
925#define DA9150_PAGE_MASK (0x3f << 0)
926#define DA9150_WRITE_MODE_SHIFT 6
927#define DA9150_WRITE_MODE_MASK BIT(6)
928#define DA9150_REVERT_SHIFT 7
929#define DA9150_REVERT_MASK BIT(7)
930
931/* DA9150_COREBTLD_STAT_A = 0x302 */
932#define DA9150_BOOTLD_STAT_SHIFT 0
933#define DA9150_BOOTLD_STAT_MASK (0x03 << 0)
934#define DA9150_CORE_LOCKUP_SHIFT 2
935#define DA9150_CORE_LOCKUP_MASK BIT(2)
936
937/* DA9150_COREBTLD_CTRL_A = 0x303 */
938#define DA9150_CORE_RESET_SHIFT 0
939#define DA9150_CORE_RESET_MASK BIT(0)
940#define DA9150_CORE_STOP_SHIFT 1
941#define DA9150_CORE_STOP_MASK BIT(1)
942
943/* DA9150_CORE_CONFIG_A = 0x304 */
944#define DA9150_CORE_MEMMUX_SHIFT 0
945#define DA9150_CORE_MEMMUX_MASK (0x03 << 0)
946#define DA9150_WDT_AUTO_START_SHIFT 2
947#define DA9150_WDT_AUTO_START_MASK BIT(2)
948#define DA9150_WDT_AUTO_LOCK_SHIFT 3
949#define DA9150_WDT_AUTO_LOCK_MASK BIT(3)
950#define DA9150_WDT_HLT_NO_CLK_SHIFT 4
951#define DA9150_WDT_HLT_NO_CLK_MASK BIT(4)
952
953/* DA9150_CORE_CONFIG_C = 0x305 */
954#define DA9150_CORE_SW_SIZE_SHIFT 0
955#define DA9150_CORE_SW_SIZE_MASK (0xff << 0)
956
957/* DA9150_CORE_CONFIG_B = 0x306 */
958#define DA9150_BOOTLD_EN_SHIFT 0
959#define DA9150_BOOTLD_EN_MASK BIT(0)
960#define DA9150_CORE_EN_SHIFT 2
961#define DA9150_CORE_EN_MASK BIT(2)
962#define DA9150_CORE_SW_SRC_SHIFT 3
963#define DA9150_CORE_SW_SRC_MASK (0x07 << 3)
964#define DA9150_DEEP_SLEEP_EN_SHIFT 7
965#define DA9150_DEEP_SLEEP_EN_MASK BIT(7)
966
967/* DA9150_CORE_CFG_DATA_A = 0x307 */
968#define DA9150_CORE_CFG_DT_A_SHIFT 0
969#define DA9150_CORE_CFG_DT_A_MASK (0xff << 0)
970
971/* DA9150_CORE_CFG_DATA_B = 0x308 */
972#define DA9150_CORE_CFG_DT_B_SHIFT 0
973#define DA9150_CORE_CFG_DT_B_MASK (0xff << 0)
974
975/* DA9150_CORE_CMD_A = 0x309 */
976#define DA9150_CORE_CMD_SHIFT 0
977#define DA9150_CORE_CMD_MASK (0xff << 0)
978
979/* DA9150_CORE_DATA_A = 0x30A */
980#define DA9150_CORE_DATA_0_SHIFT 0
981#define DA9150_CORE_DATA_0_MASK (0xff << 0)
982
983/* DA9150_CORE_DATA_B = 0x30B */
984#define DA9150_CORE_DATA_1_SHIFT 0
985#define DA9150_CORE_DATA_1_MASK (0xff << 0)
986
987/* DA9150_CORE_DATA_C = 0x30C */
988#define DA9150_CORE_DATA_2_SHIFT 0
989#define DA9150_CORE_DATA_2_MASK (0xff << 0)
990
991/* DA9150_CORE_DATA_D = 0x30D */
992#define DA9150_CORE_DATA_3_SHIFT 0
993#define DA9150_CORE_DATA_3_MASK (0xff << 0)
994
995/* DA9150_CORE2WIRE_STAT_A = 0x310 */
996#define DA9150_FW_FWDL_ERR_SHIFT 7
997#define DA9150_FW_FWDL_ERR_MASK BIT(7)
998
999/* DA9150_CORE2WIRE_CTRL_A = 0x311 */
1000#define DA9150_FW_FWDL_EN_SHIFT 0
1001#define DA9150_FW_FWDL_EN_MASK BIT(0)
1002#define DA9150_FG_QIF_EN_SHIFT 1
1003#define DA9150_FG_QIF_EN_MASK BIT(1)
1004#define DA9150_CORE_BASE_ADDR_SHIFT 4
1005#define DA9150_CORE_BASE_ADDR_MASK (0x0f << 4)
1006
1007/* DA9150_FW_CTRL_A = 0x312 */
1008#define DA9150_FW_SEAL_SHIFT 0
1009#define DA9150_FW_SEAL_MASK (0xff << 0)
1010
1011/* DA9150_FW_CTRL_C = 0x313 */
1012#define DA9150_FW_FWDL_CRC_SHIFT 0
1013#define DA9150_FW_FWDL_CRC_MASK (0xff << 0)
1014
1015/* DA9150_FW_CTRL_D = 0x314 */
1016#define DA9150_FW_FWDL_BASE_SHIFT 0
1017#define DA9150_FW_FWDL_BASE_MASK (0x0f << 0)
1018
1019/* DA9150_FG_CTRL_A = 0x315 */
1020#define DA9150_FG_QIF_CODE_SHIFT 0
1021#define DA9150_FG_QIF_CODE_MASK (0xff << 0)
1022
1023/* DA9150_FG_CTRL_B = 0x316 */
1024#define DA9150_FG_QIF_VALUE_SHIFT 0
1025#define DA9150_FG_QIF_VALUE_MASK (0xff << 0)
1026
1027/* DA9150_FW_CTRL_E = 0x317 */
1028#define DA9150_FW_FWDL_SEG_SHIFT 0
1029#define DA9150_FW_FWDL_SEG_MASK (0xff << 0)
1030
1031/* DA9150_FW_CTRL_B = 0x318 */
1032#define DA9150_FW_FWDL_VALUE_SHIFT 0
1033#define DA9150_FW_FWDL_VALUE_MASK (0xff << 0)
1034
1035/* DA9150_GPADC_CMAN = 0x320 */
1036#define DA9150_GPADC_CEN_SHIFT 0
1037#define DA9150_GPADC_CEN_MASK BIT(0)
1038#define DA9150_GPADC_CMUX_SHIFT 1
1039#define DA9150_GPADC_CMUX_MASK (0x1f << 1)
1040
1041/* DA9150_GPADC_CRES_A = 0x322 */
1042#define DA9150_GPADC_CRES_H_SHIFT 0
1043#define DA9150_GPADC_CRES_H_MASK (0xff << 0)
1044
1045/* DA9150_GPADC_CRES_B = 0x323 */
1046#define DA9150_GPADC_CRUN_SHIFT 0
1047#define DA9150_GPADC_CRUN_MASK BIT(0)
1048#define DA9150_GPADC_CRES_L_SHIFT 6
1049#define DA9150_GPADC_CRES_L_MASK (0x03 << 6)
1050
1051/* DA9150_CC_CFG_A = 0x328 */
1052#define DA9150_CC_EN_SHIFT 0
1053#define DA9150_CC_EN_MASK BIT(0)
1054#define DA9150_CC_TIMEBASE_SHIFT 1
1055#define DA9150_CC_TIMEBASE_MASK (0x03 << 1)
1056#define DA9150_CC_CFG_SHIFT 5
1057#define DA9150_CC_CFG_MASK (0x03 << 5)
1058#define DA9150_CC_ENDLESS_MODE_SHIFT 7
1059#define DA9150_CC_ENDLESS_MODE_MASK BIT(7)
1060
1061/* DA9150_CC_CFG_B = 0x329 */
1062#define DA9150_CC_OPT_SHIFT 0
1063#define DA9150_CC_OPT_MASK (0x03 << 0)
1064#define DA9150_CC_PREAMP_SHIFT 2
1065#define DA9150_CC_PREAMP_MASK (0x03 << 2)
1066
1067/* DA9150_CC_ICHG_RES_A = 0x32A */
1068#define DA9150_CC_ICHG_RES_H_SHIFT 0
1069#define DA9150_CC_ICHG_RES_H_MASK (0xff << 0)
1070
1071/* DA9150_CC_ICHG_RES_B = 0x32B */
1072#define DA9150_CC_ICHG_RES_L_SHIFT 3
1073#define DA9150_CC_ICHG_RES_L_MASK (0x1f << 3)
1074
1075/* DA9150_CC_IAVG_RES_A = 0x32C */
1076#define DA9150_CC_IAVG_RES_H_SHIFT 0
1077#define DA9150_CC_IAVG_RES_H_MASK (0xff << 0)
1078
1079/* DA9150_CC_IAVG_RES_B = 0x32D */
1080#define DA9150_CC_IAVG_RES_L_SHIFT 0
1081#define DA9150_CC_IAVG_RES_L_MASK (0xff << 0)
1082
1083/* DA9150_TAUX_CTRL_A = 0x330 */
1084#define DA9150_TAUX_EN_SHIFT 0
1085#define DA9150_TAUX_EN_MASK BIT(0)
1086#define DA9150_TAUX_MOD_SHIFT 1
1087#define DA9150_TAUX_MOD_MASK BIT(1)
1088#define DA9150_TAUX_UPDATE_SHIFT 2
1089#define DA9150_TAUX_UPDATE_MASK BIT(2)
1090
1091/* DA9150_TAUX_RELOAD_H = 0x332 */
1092#define DA9150_TAUX_RLD_H_SHIFT 0
1093#define DA9150_TAUX_RLD_H_MASK (0xff << 0)
1094
1095/* DA9150_TAUX_RELOAD_L = 0x333 */
1096#define DA9150_TAUX_RLD_L_SHIFT 3
1097#define DA9150_TAUX_RLD_L_MASK (0x1f << 3)
1098
1099/* DA9150_TAUX_VALUE_H = 0x334 */
1100#define DA9150_TAUX_VAL_H_SHIFT 0
1101#define DA9150_TAUX_VAL_H_MASK (0xff << 0)
1102
1103/* DA9150_TAUX_VALUE_L = 0x335 */
1104#define DA9150_TAUX_VAL_L_SHIFT 3
1105#define DA9150_TAUX_VAL_L_MASK (0x1f << 3)
1106
1107/* DA9150_AUX_DATA_0 = 0x338 */
1108#define DA9150_AUX_DAT_0_SHIFT 0
1109#define DA9150_AUX_DAT_0_MASK (0xff << 0)
1110
1111/* DA9150_AUX_DATA_1 = 0x339 */
1112#define DA9150_AUX_DAT_1_SHIFT 0
1113#define DA9150_AUX_DAT_1_MASK (0xff << 0)
1114
1115/* DA9150_AUX_DATA_2 = 0x33A */
1116#define DA9150_AUX_DAT_2_SHIFT 0
1117#define DA9150_AUX_DAT_2_MASK (0xff << 0)
1118
1119/* DA9150_AUX_DATA_3 = 0x33B */
1120#define DA9150_AUX_DAT_3_SHIFT 0
1121#define DA9150_AUX_DAT_3_MASK (0xff << 0)
1122
1123/* DA9150_BIF_CTRL = 0x340 */
1124#define DA9150_BIF_ISRC_EN_SHIFT 0
1125#define DA9150_BIF_ISRC_EN_MASK BIT(0)
1126
1127/* DA9150_TBAT_CTRL_A = 0x342 */
1128#define DA9150_TBAT_EN_SHIFT 0
1129#define DA9150_TBAT_EN_MASK BIT(0)
1130#define DA9150_TBAT_SW1_SHIFT 1
1131#define DA9150_TBAT_SW1_MASK BIT(1)
1132#define DA9150_TBAT_SW2_SHIFT 2
1133#define DA9150_TBAT_SW2_MASK BIT(2)
1134
1135/* DA9150_TBAT_CTRL_B = 0x343 */
1136#define DA9150_TBAT_SW_FRC_SHIFT 0
1137#define DA9150_TBAT_SW_FRC_MASK BIT(0)
1138#define DA9150_TBAT_STAT_SW1_SHIFT 1
1139#define DA9150_TBAT_STAT_SW1_MASK BIT(1)
1140#define DA9150_TBAT_STAT_SW2_SHIFT 2
1141#define DA9150_TBAT_STAT_SW2_MASK BIT(2)
1142#define DA9150_TBAT_HIGH_CURR_SHIFT 3
1143#define DA9150_TBAT_HIGH_CURR_MASK BIT(3)
1144
1145/* DA9150_TBAT_RES_A = 0x344 */
1146#define DA9150_TBAT_RES_H_SHIFT 0
1147#define DA9150_TBAT_RES_H_MASK (0xff << 0)
1148
1149/* DA9150_TBAT_RES_B = 0x345 */
1150#define DA9150_TBAT_RES_DIS_SHIFT 0
1151#define DA9150_TBAT_RES_DIS_MASK BIT(0)
1152#define DA9150_TBAT_RES_L_SHIFT 6
1153#define DA9150_TBAT_RES_L_MASK (0x03 << 6)
1154
1155#endif /* __DA9150_REGISTERS_H */
diff --git a/include/linux/mfd/max77686-private.h b/include/linux/mfd/max77686-private.h
index 960b92ad450d..f5043490d67c 100644
--- a/include/linux/mfd/max77686-private.h
+++ b/include/linux/mfd/max77686-private.h
@@ -447,7 +447,6 @@ struct max77686_dev {
447 struct regmap_irq_chip_data *rtc_irq_data; 447 struct regmap_irq_chip_data *rtc_irq_data;
448 448
449 int irq; 449 int irq;
450 bool wakeup;
451 struct mutex irqlock; 450 struct mutex irqlock;
452 int irq_masks_cur[MAX77686_IRQ_GROUP_NR]; 451 int irq_masks_cur[MAX77686_IRQ_GROUP_NR];
453 int irq_masks_cache[MAX77686_IRQ_GROUP_NR]; 452 int irq_masks_cache[MAX77686_IRQ_GROUP_NR];
diff --git a/include/linux/mfd/max77686.h b/include/linux/mfd/max77686.h
index 553f7d09258a..bb995ab9a575 100644
--- a/include/linux/mfd/max77686.h
+++ b/include/linux/mfd/max77686.h
@@ -119,12 +119,6 @@ enum max77802_regulators {
119 MAX77802_REG_MAX, 119 MAX77802_REG_MAX,
120}; 120};
121 121
122struct max77686_regulator_data {
123 int id;
124 struct regulator_init_data *initdata;
125 struct device_node *of_node;
126};
127
128enum max77686_opmode { 122enum max77686_opmode {
129 MAX77686_OPMODE_NORMAL, 123 MAX77686_OPMODE_NORMAL,
130 MAX77686_OPMODE_LP, 124 MAX77686_OPMODE_LP,
@@ -136,26 +130,4 @@ struct max77686_opmode_data {
136 int mode; 130 int mode;
137}; 131};
138 132
139struct max77686_platform_data {
140 int ono;
141 int wakeup;
142
143 /* ---- PMIC ---- */
144 struct max77686_regulator_data *regulators;
145 int num_regulators;
146
147 struct max77686_opmode_data *opmode_data;
148
149 /*
150 * GPIO-DVS feature is not enabled with the current version of
151 * MAX77686 driver. Buck2/3/4_voltages[0] is used as the default
152 * voltage at probe. DVS/SELB gpios are set as OUTPUT-LOW.
153 */
154 int buck234_gpio_dvs[3]; /* GPIO of [0]DVS1, [1]DVS2, [2]DVS3 */
155 int buck234_gpio_selb[3]; /* [0]SELB2, [1]SELB3, [2]SELB4 */
156 unsigned int buck2_voltage[8]; /* buckx_voltage in uV */
157 unsigned int buck3_voltage[8];
158 unsigned int buck4_voltage[8];
159};
160
161#endif /* __LINUX_MFD_MAX77686_H */ 133#endif /* __LINUX_MFD_MAX77686_H */
diff --git a/include/linux/mfd/qcom_rpm.h b/include/linux/mfd/qcom_rpm.h
new file mode 100644
index 000000000000..742ebf1b76ca
--- /dev/null
+++ b/include/linux/mfd/qcom_rpm.h
@@ -0,0 +1,13 @@
1#ifndef __QCOM_RPM_H__
2#define __QCOM_RPM_H__
3
4#include <linux/types.h>
5
6struct qcom_rpm;
7
8#define QCOM_RPM_ACTIVE_STATE 0
9#define QCOM_RPM_SLEEP_STATE 1
10
11int qcom_rpm_write(struct qcom_rpm *rpm, int state, int resource, u32 *buf, size_t count);
12
13#endif
diff --git a/include/linux/mfd/rt5033-private.h b/include/linux/mfd/rt5033-private.h
new file mode 100644
index 000000000000..1b63fc2f42d1
--- /dev/null
+++ b/include/linux/mfd/rt5033-private.h
@@ -0,0 +1,260 @@
1/*
2 * MFD core driver for Richtek RT5033
3 *
4 * Copyright (C) 2014 Samsung Electronics, Co., Ltd.
5 * Author: Beomho Seo <beomho.seo@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published bythe Free Software Foundation.
10 */
11
12#ifndef __RT5033_PRIVATE_H__
13#define __RT5033_PRIVATE_H__
14
15enum rt5033_reg {
16 RT5033_REG_CHG_STAT = 0x00,
17 RT5033_REG_CHG_CTRL1 = 0x01,
18 RT5033_REG_CHG_CTRL2 = 0x02,
19 RT5033_REG_DEVICE_ID = 0x03,
20 RT5033_REG_CHG_CTRL3 = 0x04,
21 RT5033_REG_CHG_CTRL4 = 0x05,
22 RT5033_REG_CHG_CTRL5 = 0x06,
23 RT5033_REG_RT_CTRL0 = 0x07,
24 RT5033_REG_CHG_RESET = 0x08,
25 /* Reserved 0x09~0x18 */
26 RT5033_REG_RT_CTRL1 = 0x19,
27 /* Reserved 0x1A~0x20 */
28 RT5033_REG_FLED_FUNCTION1 = 0x21,
29 RT5033_REG_FLED_FUNCTION2 = 0x22,
30 RT5033_REG_FLED_STROBE_CTRL1 = 0x23,
31 RT5033_REG_FLED_STROBE_CTRL2 = 0x24,
32 RT5033_REG_FLED_CTRL1 = 0x25,
33 RT5033_REG_FLED_CTRL2 = 0x26,
34 RT5033_REG_FLED_CTRL3 = 0x27,
35 RT5033_REG_FLED_CTRL4 = 0x28,
36 RT5033_REG_FLED_CTRL5 = 0x29,
37 /* Reserved 0x2A~0x40 */
38 RT5033_REG_CTRL = 0x41,
39 RT5033_REG_BUCK_CTRL = 0x42,
40 RT5033_REG_LDO_CTRL = 0x43,
41 /* Reserved 0x44~0x46 */
42 RT5033_REG_MANUAL_RESET_CTRL = 0x47,
43 /* Reserved 0x48~0x5F */
44 RT5033_REG_CHG_IRQ1 = 0x60,
45 RT5033_REG_CHG_IRQ2 = 0x61,
46 RT5033_REG_CHG_IRQ3 = 0x62,
47 RT5033_REG_CHG_IRQ1_CTRL = 0x63,
48 RT5033_REG_CHG_IRQ2_CTRL = 0x64,
49 RT5033_REG_CHG_IRQ3_CTRL = 0x65,
50 RT5033_REG_LED_IRQ_STAT = 0x66,
51 RT5033_REG_LED_IRQ_CTRL = 0x67,
52 RT5033_REG_PMIC_IRQ_STAT = 0x68,
53 RT5033_REG_PMIC_IRQ_CTRL = 0x69,
54 RT5033_REG_SHDN_CTRL = 0x6A,
55 RT5033_REG_OFF_EVENT = 0x6B,
56
57 RT5033_REG_END,
58};
59
60/* RT5033 Charger state register */
61#define RT5033_CHG_STAT_MASK 0x20
62#define RT5033_CHG_STAT_DISCHARGING 0x00
63#define RT5033_CHG_STAT_FULL 0x10
64#define RT5033_CHG_STAT_CHARGING 0x20
65#define RT5033_CHG_STAT_NOT_CHARGING 0x30
66#define RT5033_CHG_STAT_TYPE_MASK 0x60
67#define RT5033_CHG_STAT_TYPE_PRE 0x20
68#define RT5033_CHG_STAT_TYPE_FAST 0x60
69
70/* RT5033 CHGCTRL1 register */
71#define RT5033_CHGCTRL1_IAICR_MASK 0xe0
72#define RT5033_CHGCTRL1_MODE_MASK 0x01
73
74/* RT5033 CHGCTRL2 register */
75#define RT5033_CHGCTRL2_CV_MASK 0xfc
76
77/* RT5033 CHGCTRL3 register */
78#define RT5033_CHGCTRL3_CFO_EN_MASK 0x40
79#define RT5033_CHGCTRL3_TIMER_MASK 0x38
80#define RT5033_CHGCTRL3_TIMER_EN_MASK 0x01
81
82/* RT5033 CHGCTRL4 register */
83#define RT5033_CHGCTRL4_EOC_MASK 0x07
84#define RT5033_CHGCTRL4_IPREC_MASK 0x18
85
86/* RT5033 CHGCTRL5 register */
87#define RT5033_CHGCTRL5_VPREC_MASK 0x0f
88#define RT5033_CHGCTRL5_ICHG_MASK 0xf0
89#define RT5033_CHGCTRL5_ICHG_SHIFT 0x04
90#define RT5033_CHG_MAX_CURRENT 0x0d
91
92/* RT5033 RT CTRL1 register */
93#define RT5033_RT_CTRL1_UUG_MASK 0x02
94#define RT5033_RT_HZ_MASK 0x01
95
96/* RT5033 control register */
97#define RT5033_CTRL_FCCM_BUCK_MASK 0x00
98#define RT5033_CTRL_BUCKOMS_MASK 0x01
99#define RT5033_CTRL_LDOOMS_MASK 0x02
100#define RT5033_CTRL_SLDOOMS_MASK 0x03
101#define RT5033_CTRL_EN_BUCK_MASK 0x04
102#define RT5033_CTRL_EN_LDO_MASK 0x05
103#define RT5033_CTRL_EN_SAFE_LDO_MASK 0x06
104#define RT5033_CTRL_LDO_SLEEP_MASK 0x07
105
106/* RT5033 BUCK control register */
107#define RT5033_BUCK_CTRL_MASK 0x1f
108
109/* RT5033 LDO control register */
110#define RT5033_LDO_CTRL_MASK 0x1f
111
112/* RT5033 charger property - model, manufacturer */
113
114#define RT5033_CHARGER_MODEL "RT5033WSC Charger"
115#define RT5033_MANUFACTURER "Richtek Technology Corporation"
116
117/*
118 * RT5033 charger fast-charge current lmits (as in CHGCTRL1 register),
119 * AICR mode limits the input current for example,
120 * the AIRC 100 mode limits the input current to 100 mA.
121 */
122#define RT5033_AICR_100_MODE 0x20
123#define RT5033_AICR_500_MODE 0x40
124#define RT5033_AICR_700_MODE 0x60
125#define RT5033_AICR_900_MODE 0x80
126#define RT5033_AICR_1500_MODE 0xc0
127#define RT5033_AICR_2000_MODE 0xe0
128#define RT5033_AICR_MODE_MASK 0xe0
129
130/* RT5033 use internal timer need to set time */
131#define RT5033_FAST_CHARGE_TIMER4 0x00
132#define RT5033_FAST_CHARGE_TIMER6 0x01
133#define RT5033_FAST_CHARGE_TIMER8 0x02
134#define RT5033_FAST_CHARGE_TIMER9 0x03
135#define RT5033_FAST_CHARGE_TIMER12 0x04
136#define RT5033_FAST_CHARGE_TIMER14 0x05
137#define RT5033_FAST_CHARGE_TIMER16 0x06
138
139#define RT5033_INT_TIMER_ENABLE 0x01
140
141/* RT5033 charger termination enable mask */
142#define RT5033_TE_ENABLE_MASK 0x08
143
144/*
145 * RT5033 charger opa mode. RT50300 have two opa mode charger mode
146 * and boost mode for OTG
147 */
148
149#define RT5033_CHARGER_MODE 0x00
150#define RT5033_BOOST_MODE 0x01
151
152/* RT5033 charger termination enable */
153#define RT5033_TE_ENABLE 0x08
154
155/* RT5033 charger CFO enable */
156#define RT5033_CFO_ENABLE 0x40
157
158/* RT5033 charger constant charge voltage (as in CHGCTRL2 register), uV */
159#define RT5033_CHARGER_CONST_VOLTAGE_LIMIT_MIN 3650000U
160#define RT5033_CHARGER_CONST_VOLTAGE_STEP_NUM 25000U
161#define RT5033_CHARGER_CONST_VOLTAGE_LIMIT_MAX 4400000U
162
163/* RT5033 charger pre-charge current limits (as in CHGCTRL4 register), uA */
164#define RT5033_CHARGER_PRE_CURRENT_LIMIT_MIN 350000U
165#define RT5033_CHARGER_PRE_CURRENT_STEP_NUM 100000U
166#define RT5033_CHARGER_PRE_CURRENT_LIMIT_MAX 650000U
167
168/* RT5033 charger fast-charge current (as in CHGCTRL5 register), uA */
169#define RT5033_CHARGER_FAST_CURRENT_MIN 700000U
170#define RT5033_CHARGER_FAST_CURRENT_STEP_NUM 100000U
171#define RT5033_CHARGER_FAST_CURRENT_MAX 2000000U
172
173/*
174 * RT5033 charger const-charge end of charger current (
175 * as in CHGCTRL4 register), uA
176 */
177#define RT5033_CHARGER_EOC_MIN 150000U
178#define RT5033_CHARGER_EOC_REF 300000U
179#define RT5033_CHARGER_EOC_STEP_NUM1 50000U
180#define RT5033_CHARGER_EOC_STEP_NUM2 100000U
181#define RT5033_CHARGER_EOC_MAX 600000U
182
183/*
184 * RT5033 charger pre-charge threshold volt limits
185 * (as in CHGCTRL5 register), uV
186 */
187
188#define RT5033_CHARGER_PRE_THRESHOLD_LIMIT_MIN 2300000U
189#define RT5033_CHARGER_PRE_THRESHOLD_STEP_NUM 100000U
190#define RT5033_CHARGER_PRE_THRESHOLD_LIMIT_MAX 3800000U
191
192/*
193 * RT5033 charger enable UUG, If UUG enable MOS auto control by H/W charger
194 * circuit.
195 */
196#define RT5033_CHARGER_UUG_ENABLE 0x02
197
198/* RT5033 charger High impedance mode */
199#define RT5033_CHARGER_HZ_DISABLE 0x00
200#define RT5033_CHARGER_HZ_ENABLE 0x01
201
202/* RT5033 regulator BUCK output voltage uV */
203#define RT5033_REGULATOR_BUCK_VOLTAGE_MIN 1000000U
204#define RT5033_REGULATOR_BUCK_VOLTAGE_MAX 3000000U
205#define RT5033_REGULATOR_BUCK_VOLTAGE_STEP 100000U
206#define RT5033_REGULATOR_BUCK_VOLTAGE_STEP_NUM 32
207
208/* RT5033 regulator LDO output voltage uV */
209#define RT5033_REGULATOR_LDO_VOLTAGE_MIN 1200000U
210#define RT5033_REGULATOR_LDO_VOLTAGE_MAX 3000000U
211#define RT5033_REGULATOR_LDO_VOLTAGE_STEP 100000U
212#define RT5033_REGULATOR_LDO_VOLTAGE_STEP_NUM 32
213
214/* RT5033 regulator SAFE LDO output voltage uV */
215#define RT5033_REGULATOR_SAFE_LDO_VOLTAGE 4900000U
216
217enum rt5033_fuel_reg {
218 RT5033_FUEL_REG_OCV_H = 0x00,
219 RT5033_FUEL_REG_OCV_L = 0x01,
220 RT5033_FUEL_REG_VBAT_H = 0x02,
221 RT5033_FUEL_REG_VBAT_L = 0x03,
222 RT5033_FUEL_REG_SOC_H = 0x04,
223 RT5033_FUEL_REG_SOC_L = 0x05,
224 RT5033_FUEL_REG_CTRL_H = 0x06,
225 RT5033_FUEL_REG_CTRL_L = 0x07,
226 RT5033_FUEL_REG_CRATE = 0x08,
227 RT5033_FUEL_REG_DEVICE_ID = 0x09,
228 RT5033_FUEL_REG_AVG_VOLT_H = 0x0A,
229 RT5033_FUEL_REG_AVG_VOLT_L = 0x0B,
230 RT5033_FUEL_REG_CONFIG_H = 0x0C,
231 RT5033_FUEL_REG_CONFIG_L = 0x0D,
232 /* Reserved 0x0E~0x0F */
233 RT5033_FUEL_REG_IRQ_CTRL = 0x10,
234 RT5033_FUEL_REG_IRQ_FLAG = 0x11,
235 RT5033_FUEL_VMIN = 0x12,
236 RT5033_FUEL_SMIN = 0x13,
237 /* Reserved 0x14~0x1F */
238 RT5033_FUEL_VGCOMP1 = 0x20,
239 RT5033_FUEL_VGCOMP2 = 0x21,
240 RT5033_FUEL_VGCOMP3 = 0x22,
241 RT5033_FUEL_VGCOMP4 = 0x23,
242 /* Reserved 0x24~0xFD */
243 RT5033_FUEL_MFA_H = 0xFE,
244 RT5033_FUEL_MFA_L = 0xFF,
245
246 RT5033_FUEL_REG_END,
247};
248
249/* RT5033 fuel gauge battery present property */
250#define RT5033_FUEL_BAT_PRESENT 0x02
251
252/* RT5033 PMIC interrupts */
253#define RT5033_PMIC_IRQ_BUCKOCP 2
254#define RT5033_PMIC_IRQ_BUCKLV 3
255#define RT5033_PMIC_IRQ_SAFELDOLV 4
256#define RT5033_PMIC_IRQ_LDOLV 5
257#define RT5033_PMIC_IRQ_OT 6
258#define RT5033_PMIC_IRQ_VDDA_UV 7
259
260#endif /* __RT5033_PRIVATE_H__ */
diff --git a/include/linux/mfd/rt5033.h b/include/linux/mfd/rt5033.h
new file mode 100644
index 000000000000..010cff49a98e
--- /dev/null
+++ b/include/linux/mfd/rt5033.h
@@ -0,0 +1,62 @@
1/*
2 * MFD core driver for the RT5033
3 *
4 * Copyright (C) 2014 Samsung Electronics
5 * Author: Beomho Seo <beomho.seo@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published bythe Free Software Foundation.
10 */
11
12#ifndef __RT5033_H__
13#define __RT5033_H__
14
15#include <linux/regulator/consumer.h>
16#include <linux/i2c.h>
17#include <linux/regmap.h>
18#include <linux/power_supply.h>
19
20/* RT5033 regulator IDs */
21enum rt5033_regulators {
22 RT5033_BUCK = 0,
23 RT5033_LDO,
24 RT5033_SAFE_LDO,
25
26 RT5033_REGULATOR_NUM,
27};
28
29struct rt5033_dev {
30 struct device *dev;
31
32 struct regmap *regmap;
33 struct regmap_irq_chip_data *irq_data;
34 int irq;
35 bool wakeup;
36};
37
38struct rt5033_battery {
39 struct i2c_client *client;
40 struct rt5033_dev *rt5033;
41 struct regmap *regmap;
42 struct power_supply psy;
43};
44
45/* RT5033 charger platform data */
46struct rt5033_charger_data {
47 unsigned int pre_uamp;
48 unsigned int pre_uvolt;
49 unsigned int const_uvolt;
50 unsigned int eoc_uamp;
51 unsigned int fast_uamp;
52};
53
54struct rt5033_charger {
55 struct device *dev;
56 struct rt5033_dev *rt5033;
57 struct power_supply psy;
58
59 struct rt5033_charger_data *chg;
60};
61
62#endif /* __RT5033_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-28 16:11:59 -0500