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-rw-r--r--arch/arm/boot/dts/tegra114-dalmore.dts566
-rw-r--r--arch/arm/boot/dts/tegra114.dtsi25
-rw-r--r--arch/arm/boot/dts/tegra124-venice2.dts433
-rw-r--r--arch/arm/boot/dts/tegra124.dtsi418
-rw-r--r--arch/arm/boot/dts/tegra20-colibri-512.dtsi200
-rw-r--r--arch/arm/boot/dts/tegra20-harmony.dts279
-rw-r--r--arch/arm/boot/dts/tegra20-iris-512.dts30
-rw-r--r--arch/arm/boot/dts/tegra20-medcom-wide.dts2
-rw-r--r--arch/arm/boot/dts/tegra20-paz00.dts45
-rw-r--r--arch/arm/boot/dts/tegra20-plutux.dts4
-rw-r--r--arch/arm/boot/dts/tegra20-seaboard.dts348
-rw-r--r--arch/arm/boot/dts/tegra20-tamonten.dtsi42
-rw-r--r--arch/arm/boot/dts/tegra20-tec.dts6
-rw-r--r--arch/arm/boot/dts/tegra20-trimslice.dts49
-rw-r--r--arch/arm/boot/dts/tegra20-ventana.dts57
-rw-r--r--arch/arm/boot/dts/tegra20-whistler.dts79
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi55
-rw-r--r--arch/arm/boot/dts/tegra30-beaver.dts112
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu-a02.dts14
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu-a04.dts14
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu.dtsi62
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi51
-rw-r--r--include/dt-bindings/gpio/tegra-gpio.h1
-rw-r--r--include/dt-bindings/pinctrl/pinctrl-tegra.h45
24 files changed, 1922 insertions, 1015 deletions
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index cb5ec23b03a7..88be40cf8845 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -11,7 +11,7 @@
11 reg = <0x80000000 0x40000000>; 11 reg = <0x80000000 0x40000000>;
12 }; 12 };
13 13
14 pinmux { 14 pinmux@70000868 {
15 pinctrl-names = "default"; 15 pinctrl-names = "default";
16 pinctrl-0 = <&state_default>; 16 pinctrl-0 = <&state_default>;
17 17
@@ -19,41 +19,41 @@
19 clk1_out_pw4 { 19 clk1_out_pw4 {
20 nvidia,pins = "clk1_out_pw4"; 20 nvidia,pins = "clk1_out_pw4";
21 nvidia,function = "extperiph1"; 21 nvidia,function = "extperiph1";
22 nvidia,pull = <0>; 22 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
23 nvidia,tristate = <0>; 23 nvidia,tristate = <TEGRA_PIN_DISABLE>;
24 nvidia,enable-input = <0>; 24 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
25 }; 25 };
26 dap1_din_pn1 { 26 dap1_din_pn1 {
27 nvidia,pins = "dap1_din_pn1"; 27 nvidia,pins = "dap1_din_pn1";
28 nvidia,function = "i2s0"; 28 nvidia,function = "i2s0";
29 nvidia,pull = <0>; 29 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
30 nvidia,tristate = <1>; 30 nvidia,tristate = <TEGRA_PIN_ENABLE>;
31 nvidia,enable-input = <1>; 31 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
32 }; 32 };
33 dap1_dout_pn2 { 33 dap1_dout_pn2 {
34 nvidia,pins = "dap1_dout_pn2", 34 nvidia,pins = "dap1_dout_pn2",
35 "dap1_fs_pn0", 35 "dap1_fs_pn0",
36 "dap1_sclk_pn3"; 36 "dap1_sclk_pn3";
37 nvidia,function = "i2s0"; 37 nvidia,function = "i2s0";
38 nvidia,pull = <0>; 38 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
39 nvidia,tristate = <0>; 39 nvidia,tristate = <TEGRA_PIN_DISABLE>;
40 nvidia,enable-input = <1>; 40 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
41 }; 41 };
42 dap2_din_pa4 { 42 dap2_din_pa4 {
43 nvidia,pins = "dap2_din_pa4"; 43 nvidia,pins = "dap2_din_pa4";
44 nvidia,function = "i2s1"; 44 nvidia,function = "i2s1";
45 nvidia,pull = <0>; 45 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
46 nvidia,tristate = <1>; 46 nvidia,tristate = <TEGRA_PIN_ENABLE>;
47 nvidia,enable-input = <1>; 47 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
48 }; 48 };
49 dap2_dout_pa5 { 49 dap2_dout_pa5 {
50 nvidia,pins = "dap2_dout_pa5", 50 nvidia,pins = "dap2_dout_pa5",
51 "dap2_fs_pa2", 51 "dap2_fs_pa2",
52 "dap2_sclk_pa3"; 52 "dap2_sclk_pa3";
53 nvidia,function = "i2s1"; 53 nvidia,function = "i2s1";
54 nvidia,pull = <0>; 54 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
55 nvidia,tristate = <0>; 55 nvidia,tristate = <TEGRA_PIN_DISABLE>;
56 nvidia,enable-input = <1>; 56 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
57 }; 57 };
58 dap4_din_pp5 { 58 dap4_din_pp5 {
59 nvidia,pins = "dap4_din_pp5", 59 nvidia,pins = "dap4_din_pp5",
@@ -61,17 +61,17 @@
61 "dap4_fs_pp4", 61 "dap4_fs_pp4",
62 "dap4_sclk_pp7"; 62 "dap4_sclk_pp7";
63 nvidia,function = "i2s3"; 63 nvidia,function = "i2s3";
64 nvidia,pull = <0>; 64 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
65 nvidia,tristate = <0>; 65 nvidia,tristate = <TEGRA_PIN_DISABLE>;
66 nvidia,enable-input = <1>; 66 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
67 }; 67 };
68 dvfs_pwm_px0 { 68 dvfs_pwm_px0 {
69 nvidia,pins = "dvfs_pwm_px0", 69 nvidia,pins = "dvfs_pwm_px0",
70 "dvfs_clk_px2"; 70 "dvfs_clk_px2";
71 nvidia,function = "cldvfs"; 71 nvidia,function = "cldvfs";
72 nvidia,pull = <0>; 72 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
73 nvidia,tristate = <0>; 73 nvidia,tristate = <TEGRA_PIN_DISABLE>;
74 nvidia,enable-input = <0>; 74 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
75 }; 75 };
76 ulpi_clk_py0 { 76 ulpi_clk_py0 {
77 nvidia,pins = "ulpi_clk_py0", 77 nvidia,pins = "ulpi_clk_py0",
@@ -84,128 +84,128 @@
84 "ulpi_data6_po7", 84 "ulpi_data6_po7",
85 "ulpi_data7_po0"; 85 "ulpi_data7_po0";
86 nvidia,function = "ulpi"; 86 nvidia,function = "ulpi";
87 nvidia,pull = <0>; 87 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
88 nvidia,tristate = <0>; 88 nvidia,tristate = <TEGRA_PIN_DISABLE>;
89 nvidia,enable-input = <1>; 89 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
90 }; 90 };
91 ulpi_dir_py1 { 91 ulpi_dir_py1 {
92 nvidia,pins = "ulpi_dir_py1", 92 nvidia,pins = "ulpi_dir_py1",
93 "ulpi_nxt_py2"; 93 "ulpi_nxt_py2";
94 nvidia,function = "ulpi"; 94 nvidia,function = "ulpi";
95 nvidia,pull = <0>; 95 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
96 nvidia,tristate = <1>; 96 nvidia,tristate = <TEGRA_PIN_ENABLE>;
97 nvidia,enable-input = <1>; 97 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
98 }; 98 };
99 ulpi_stp_py3 { 99 ulpi_stp_py3 {
100 nvidia,pins = "ulpi_stp_py3"; 100 nvidia,pins = "ulpi_stp_py3";
101 nvidia,function = "ulpi"; 101 nvidia,function = "ulpi";
102 nvidia,pull = <0>; 102 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
103 nvidia,tristate = <0>; 103 nvidia,tristate = <TEGRA_PIN_DISABLE>;
104 nvidia,enable-input = <0>; 104 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
105 }; 105 };
106 cam_i2c_scl_pbb1 { 106 cam_i2c_scl_pbb1 {
107 nvidia,pins = "cam_i2c_scl_pbb1", 107 nvidia,pins = "cam_i2c_scl_pbb1",
108 "cam_i2c_sda_pbb2"; 108 "cam_i2c_sda_pbb2";
109 nvidia,function = "i2c3"; 109 nvidia,function = "i2c3";
110 nvidia,pull = <0>; 110 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
111 nvidia,tristate = <0>; 111 nvidia,tristate = <TEGRA_PIN_DISABLE>;
112 nvidia,enable-input = <1>; 112 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
113 nvidia,lock = <0>; 113 nvidia,lock = <TEGRA_PIN_DISABLE>;
114 nvidia,open-drain = <0>; 114 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
115 }; 115 };
116 cam_mclk_pcc0 { 116 cam_mclk_pcc0 {
117 nvidia,pins = "cam_mclk_pcc0", 117 nvidia,pins = "cam_mclk_pcc0",
118 "pbb0"; 118 "pbb0";
119 nvidia,function = "vi_alt3"; 119 nvidia,function = "vi_alt3";
120 nvidia,pull = <0>; 120 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
121 nvidia,tristate = <0>; 121 nvidia,tristate = <TEGRA_PIN_DISABLE>;
122 nvidia,enable-input = <0>; 122 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
123 nvidia,lock = <0>; 123 nvidia,lock = <TEGRA_PIN_DISABLE>;
124 }; 124 };
125 gen2_i2c_scl_pt5 { 125 gen2_i2c_scl_pt5 {
126 nvidia,pins = "gen2_i2c_scl_pt5", 126 nvidia,pins = "gen2_i2c_scl_pt5",
127 "gen2_i2c_sda_pt6"; 127 "gen2_i2c_sda_pt6";
128 nvidia,function = "i2c2"; 128 nvidia,function = "i2c2";
129 nvidia,pull = <0>; 129 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
130 nvidia,tristate = <0>; 130 nvidia,tristate = <TEGRA_PIN_DISABLE>;
131 nvidia,enable-input = <1>; 131 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
132 nvidia,lock = <0>; 132 nvidia,lock = <TEGRA_PIN_DISABLE>;
133 nvidia,open-drain = <0>; 133 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
134 }; 134 };
135 gmi_a16_pj7 { 135 gmi_a16_pj7 {
136 nvidia,pins = "gmi_a16_pj7"; 136 nvidia,pins = "gmi_a16_pj7";
137 nvidia,function = "uartd"; 137 nvidia,function = "uartd";
138 nvidia,pull = <0>; 138 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
139 nvidia,tristate = <0>; 139 nvidia,tristate = <TEGRA_PIN_DISABLE>;
140 nvidia,enable-input = <0>; 140 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
141 }; 141 };
142 gmi_a17_pb0 { 142 gmi_a17_pb0 {
143 nvidia,pins = "gmi_a17_pb0", 143 nvidia,pins = "gmi_a17_pb0",
144 "gmi_a18_pb1"; 144 "gmi_a18_pb1";
145 nvidia,function = "uartd"; 145 nvidia,function = "uartd";
146 nvidia,pull = <0>; 146 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
147 nvidia,tristate = <1>; 147 nvidia,tristate = <TEGRA_PIN_ENABLE>;
148 nvidia,enable-input = <1>; 148 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
149 }; 149 };
150 gmi_a19_pk7 { 150 gmi_a19_pk7 {
151 nvidia,pins = "gmi_a19_pk7"; 151 nvidia,pins = "gmi_a19_pk7";
152 nvidia,function = "uartd"; 152 nvidia,function = "uartd";
153 nvidia,pull = <0>; 153 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
154 nvidia,tristate = <0>; 154 nvidia,tristate = <TEGRA_PIN_DISABLE>;
155 nvidia,enable-input = <0>; 155 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
156 }; 156 };
157 gmi_ad5_pg5 { 157 gmi_ad5_pg5 {
158 nvidia,pins = "gmi_ad5_pg5", 158 nvidia,pins = "gmi_ad5_pg5",
159 "gmi_cs6_n_pi3", 159 "gmi_cs6_n_pi3",
160 "gmi_wr_n_pi0"; 160 "gmi_wr_n_pi0";
161 nvidia,function = "spi4"; 161 nvidia,function = "spi4";
162 nvidia,pull = <0>; 162 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
163 nvidia,tristate = <0>; 163 nvidia,tristate = <TEGRA_PIN_DISABLE>;
164 nvidia,enable-input = <1>; 164 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
165 }; 165 };
166 gmi_ad6_pg6 { 166 gmi_ad6_pg6 {
167 nvidia,pins = "gmi_ad6_pg6", 167 nvidia,pins = "gmi_ad6_pg6",
168 "gmi_ad7_pg7"; 168 "gmi_ad7_pg7";
169 nvidia,function = "spi4"; 169 nvidia,function = "spi4";
170 nvidia,pull = <2>; 170 nvidia,pull = <TEGRA_PIN_PULL_UP>;
171 nvidia,tristate = <0>; 171 nvidia,tristate = <TEGRA_PIN_DISABLE>;
172 nvidia,enable-input = <1>; 172 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
173 }; 173 };
174 gmi_ad12_ph4 { 174 gmi_ad12_ph4 {
175 nvidia,pins = "gmi_ad12_ph4"; 175 nvidia,pins = "gmi_ad12_ph4";
176 nvidia,function = "rsvd4"; 176 nvidia,function = "rsvd4";
177 nvidia,pull = <0>; 177 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
178 nvidia,tristate = <0>; 178 nvidia,tristate = <TEGRA_PIN_DISABLE>;
179 nvidia,enable-input = <0>; 179 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
180 }; 180 };
181 gmi_ad9_ph1 { 181 gmi_ad9_ph1 {
182 nvidia,pins = "gmi_ad9_ph1"; 182 nvidia,pins = "gmi_ad9_ph1";
183 nvidia,function = "pwm1"; 183 nvidia,function = "pwm1";
184 nvidia,pull = <0>; 184 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
185 nvidia,tristate = <0>; 185 nvidia,tristate = <TEGRA_PIN_DISABLE>;
186 nvidia,enable-input = <0>; 186 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
187 }; 187 };
188 gmi_cs1_n_pj2 { 188 gmi_cs1_n_pj2 {
189 nvidia,pins = "gmi_cs1_n_pj2", 189 nvidia,pins = "gmi_cs1_n_pj2",
190 "gmi_oe_n_pi1"; 190 "gmi_oe_n_pi1";
191 nvidia,function = "soc"; 191 nvidia,function = "soc";
192 nvidia,pull = <0>; 192 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
193 nvidia,tristate = <1>; 193 nvidia,tristate = <TEGRA_PIN_ENABLE>;
194 nvidia,enable-input = <1>; 194 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
195 }; 195 };
196 clk2_out_pw5 { 196 clk2_out_pw5 {
197 nvidia,pins = "clk2_out_pw5"; 197 nvidia,pins = "clk2_out_pw5";
198 nvidia,function = "extperiph2"; 198 nvidia,function = "extperiph2";
199 nvidia,pull = <0>; 199 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
200 nvidia,tristate = <0>; 200 nvidia,tristate = <TEGRA_PIN_DISABLE>;
201 nvidia,enable-input = <0>; 201 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
202 }; 202 };
203 sdmmc1_clk_pz0 { 203 sdmmc1_clk_pz0 {
204 nvidia,pins = "sdmmc1_clk_pz0"; 204 nvidia,pins = "sdmmc1_clk_pz0";
205 nvidia,function = "sdmmc1"; 205 nvidia,function = "sdmmc1";
206 nvidia,pull = <0>; 206 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
207 nvidia,tristate = <0>; 207 nvidia,tristate = <TEGRA_PIN_DISABLE>;
208 nvidia,enable-input = <1>; 208 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
209 }; 209 };
210 sdmmc1_cmd_pz1 { 210 sdmmc1_cmd_pz1 {
211 nvidia,pins = "sdmmc1_cmd_pz1", 211 nvidia,pins = "sdmmc1_cmd_pz1",
@@ -214,23 +214,23 @@
214 "sdmmc1_dat2_py5", 214 "sdmmc1_dat2_py5",
215 "sdmmc1_dat3_py4"; 215 "sdmmc1_dat3_py4";
216 nvidia,function = "sdmmc1"; 216 nvidia,function = "sdmmc1";
217 nvidia,pull = <2>; 217 nvidia,pull = <TEGRA_PIN_PULL_UP>;
218 nvidia,tristate = <0>; 218 nvidia,tristate = <TEGRA_PIN_DISABLE>;
219 nvidia,enable-input = <1>; 219 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
220 }; 220 };
221 sdmmc1_wp_n_pv3 { 221 sdmmc1_wp_n_pv3 {
222 nvidia,pins = "sdmmc1_wp_n_pv3"; 222 nvidia,pins = "sdmmc1_wp_n_pv3";
223 nvidia,function = "spi4"; 223 nvidia,function = "spi4";
224 nvidia,pull = <2>; 224 nvidia,pull = <TEGRA_PIN_PULL_UP>;
225 nvidia,tristate = <0>; 225 nvidia,tristate = <TEGRA_PIN_DISABLE>;
226 nvidia,enable-input = <0>; 226 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
227 }; 227 };
228 sdmmc3_clk_pa6 { 228 sdmmc3_clk_pa6 {
229 nvidia,pins = "sdmmc3_clk_pa6"; 229 nvidia,pins = "sdmmc3_clk_pa6";
230 nvidia,function = "sdmmc3"; 230 nvidia,function = "sdmmc3";
231 nvidia,pull = <0>; 231 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
232 nvidia,tristate = <0>; 232 nvidia,tristate = <TEGRA_PIN_DISABLE>;
233 nvidia,enable-input = <1>; 233 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
234 }; 234 };
235 sdmmc3_cmd_pa7 { 235 sdmmc3_cmd_pa7 {
236 nvidia,pins = "sdmmc3_cmd_pa7", 236 nvidia,pins = "sdmmc3_cmd_pa7",
@@ -242,16 +242,16 @@
242 "sdmmc3_clk_lb_out_pee4", 242 "sdmmc3_clk_lb_out_pee4",
243 "sdmmc3_clk_lb_in_pee5"; 243 "sdmmc3_clk_lb_in_pee5";
244 nvidia,function = "sdmmc3"; 244 nvidia,function = "sdmmc3";
245 nvidia,pull = <2>; 245 nvidia,pull = <TEGRA_PIN_PULL_UP>;
246 nvidia,tristate = <0>; 246 nvidia,tristate = <TEGRA_PIN_DISABLE>;
247 nvidia,enable-input = <1>; 247 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
248 }; 248 };
249 sdmmc4_clk_pcc4 { 249 sdmmc4_clk_pcc4 {
250 nvidia,pins = "sdmmc4_clk_pcc4"; 250 nvidia,pins = "sdmmc4_clk_pcc4";
251 nvidia,function = "sdmmc4"; 251 nvidia,function = "sdmmc4";
252 nvidia,pull = <0>; 252 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
253 nvidia,tristate = <0>; 253 nvidia,tristate = <TEGRA_PIN_DISABLE>;
254 nvidia,enable-input = <1>; 254 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
255 }; 255 };
256 sdmmc4_cmd_pt7 { 256 sdmmc4_cmd_pt7 {
257 nvidia,pins = "sdmmc4_cmd_pt7", 257 nvidia,pins = "sdmmc4_cmd_pt7",
@@ -264,16 +264,16 @@
264 "sdmmc4_dat6_paa6", 264 "sdmmc4_dat6_paa6",
265 "sdmmc4_dat7_paa7"; 265 "sdmmc4_dat7_paa7";
266 nvidia,function = "sdmmc4"; 266 nvidia,function = "sdmmc4";
267 nvidia,pull = <2>; 267 nvidia,pull = <TEGRA_PIN_PULL_UP>;
268 nvidia,tristate = <0>; 268 nvidia,tristate = <TEGRA_PIN_DISABLE>;
269 nvidia,enable-input = <1>; 269 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
270 }; 270 };
271 clk_32k_out_pa0 { 271 clk_32k_out_pa0 {
272 nvidia,pins = "clk_32k_out_pa0"; 272 nvidia,pins = "clk_32k_out_pa0";
273 nvidia,function = "blink"; 273 nvidia,function = "blink";
274 nvidia,pull = <0>; 274 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
275 nvidia,tristate = <0>; 275 nvidia,tristate = <TEGRA_PIN_DISABLE>;
276 nvidia,enable-input = <0>; 276 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
277 }; 277 };
278 kb_col0_pq0 { 278 kb_col0_pq0 {
279 nvidia,pins = "kb_col0_pq0", 279 nvidia,pins = "kb_col0_pq0",
@@ -283,265 +283,265 @@
283 "kb_row1_pr1", 283 "kb_row1_pr1",
284 "kb_row2_pr2"; 284 "kb_row2_pr2";
285 nvidia,function = "kbc"; 285 nvidia,function = "kbc";
286 nvidia,pull = <2>; 286 nvidia,pull = <TEGRA_PIN_PULL_UP>;
287 nvidia,tristate = <0>; 287 nvidia,tristate = <TEGRA_PIN_DISABLE>;
288 nvidia,enable-input = <1>; 288 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
289 }; 289 };
290 dap3_din_pp1 { 290 dap3_din_pp1 {
291 nvidia,pins = "dap3_din_pp1", 291 nvidia,pins = "dap3_din_pp1",
292 "dap3_sclk_pp3"; 292 "dap3_sclk_pp3";
293 nvidia,function = "displayb"; 293 nvidia,function = "displayb";
294 nvidia,pull = <0>; 294 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
295 nvidia,tristate = <1>; 295 nvidia,tristate = <TEGRA_PIN_ENABLE>;
296 nvidia,enable-input = <0>; 296 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
297 }; 297 };
298 pv0 { 298 pv0 {
299 nvidia,pins = "pv0"; 299 nvidia,pins = "pv0";
300 nvidia,function = "rsvd4"; 300 nvidia,function = "rsvd4";
301 nvidia,pull = <0>; 301 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
302 nvidia,tristate = <1>; 302 nvidia,tristate = <TEGRA_PIN_ENABLE>;
303 nvidia,enable-input = <0>; 303 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
304 }; 304 };
305 kb_row7_pr7 { 305 kb_row7_pr7 {
306 nvidia,pins = "kb_row7_pr7"; 306 nvidia,pins = "kb_row7_pr7";
307 nvidia,function = "rsvd2"; 307 nvidia,function = "rsvd2";
308 nvidia,pull = <2>; 308 nvidia,pull = <TEGRA_PIN_PULL_UP>;
309 nvidia,tristate = <0>; 309 nvidia,tristate = <TEGRA_PIN_DISABLE>;
310 nvidia,enable-input = <1>; 310 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
311 }; 311 };
312 kb_row10_ps2 { 312 kb_row10_ps2 {
313 nvidia,pins = "kb_row10_ps2"; 313 nvidia,pins = "kb_row10_ps2";
314 nvidia,function = "uarta"; 314 nvidia,function = "uarta";
315 nvidia,pull = <0>; 315 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
316 nvidia,tristate = <1>; 316 nvidia,tristate = <TEGRA_PIN_ENABLE>;
317 nvidia,enable-input = <1>; 317 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
318 }; 318 };
319 kb_row9_ps1 { 319 kb_row9_ps1 {
320 nvidia,pins = "kb_row9_ps1"; 320 nvidia,pins = "kb_row9_ps1";
321 nvidia,function = "uarta"; 321 nvidia,function = "uarta";
322 nvidia,pull = <0>; 322 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
323 nvidia,tristate = <0>; 323 nvidia,tristate = <TEGRA_PIN_DISABLE>;
324 nvidia,enable-input = <0>; 324 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
325 }; 325 };
326 pwr_i2c_scl_pz6 { 326 pwr_i2c_scl_pz6 {
327 nvidia,pins = "pwr_i2c_scl_pz6", 327 nvidia,pins = "pwr_i2c_scl_pz6",
328 "pwr_i2c_sda_pz7"; 328 "pwr_i2c_sda_pz7";
329 nvidia,function = "i2cpwr"; 329 nvidia,function = "i2cpwr";
330 nvidia,pull = <0>; 330 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
331 nvidia,tristate = <0>; 331 nvidia,tristate = <TEGRA_PIN_DISABLE>;
332 nvidia,enable-input = <1>; 332 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
333 nvidia,lock = <0>; 333 nvidia,lock = <TEGRA_PIN_DISABLE>;
334 nvidia,open-drain = <0>; 334 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
335 }; 335 };
336 sys_clk_req_pz5 { 336 sys_clk_req_pz5 {
337 nvidia,pins = "sys_clk_req_pz5"; 337 nvidia,pins = "sys_clk_req_pz5";
338 nvidia,function = "sysclk"; 338 nvidia,function = "sysclk";
339 nvidia,pull = <0>; 339 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
340 nvidia,tristate = <0>; 340 nvidia,tristate = <TEGRA_PIN_DISABLE>;
341 nvidia,enable-input = <0>; 341 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
342 }; 342 };
343 core_pwr_req { 343 core_pwr_req {
344 nvidia,pins = "core_pwr_req"; 344 nvidia,pins = "core_pwr_req";
345 nvidia,function = "pwron"; 345 nvidia,function = "pwron";
346 nvidia,pull = <0>; 346 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
347 nvidia,tristate = <0>; 347 nvidia,tristate = <TEGRA_PIN_DISABLE>;
348 nvidia,enable-input = <0>; 348 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
349 }; 349 };
350 cpu_pwr_req { 350 cpu_pwr_req {
351 nvidia,pins = "cpu_pwr_req"; 351 nvidia,pins = "cpu_pwr_req";
352 nvidia,function = "cpu"; 352 nvidia,function = "cpu";
353 nvidia,pull = <0>; 353 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
354 nvidia,tristate = <0>; 354 nvidia,tristate = <TEGRA_PIN_DISABLE>;
355 nvidia,enable-input = <0>; 355 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
356 }; 356 };
357 pwr_int_n { 357 pwr_int_n {
358 nvidia,pins = "pwr_int_n"; 358 nvidia,pins = "pwr_int_n";
359 nvidia,function = "pmi"; 359 nvidia,function = "pmi";
360 nvidia,pull = <0>; 360 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
361 nvidia,tristate = <1>; 361 nvidia,tristate = <TEGRA_PIN_ENABLE>;
362 nvidia,enable-input = <1>; 362 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
363 }; 363 };
364 reset_out_n { 364 reset_out_n {
365 nvidia,pins = "reset_out_n"; 365 nvidia,pins = "reset_out_n";
366 nvidia,function = "reset_out_n"; 366 nvidia,function = "reset_out_n";
367 nvidia,pull = <0>; 367 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
368 nvidia,tristate = <0>; 368 nvidia,tristate = <TEGRA_PIN_DISABLE>;
369 nvidia,enable-input = <0>; 369 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
370 }; 370 };
371 clk3_out_pee0 { 371 clk3_out_pee0 {
372 nvidia,pins = "clk3_out_pee0"; 372 nvidia,pins = "clk3_out_pee0";
373 nvidia,function = "extperiph3"; 373 nvidia,function = "extperiph3";
374 nvidia,pull = <0>; 374 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
375 nvidia,tristate = <0>; 375 nvidia,tristate = <TEGRA_PIN_DISABLE>;
376 nvidia,enable-input = <0>; 376 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
377 }; 377 };
378 gen1_i2c_scl_pc4 { 378 gen1_i2c_scl_pc4 {
379 nvidia,pins = "gen1_i2c_scl_pc4", 379 nvidia,pins = "gen1_i2c_scl_pc4",
380 "gen1_i2c_sda_pc5"; 380 "gen1_i2c_sda_pc5";
381 nvidia,function = "i2c1"; 381 nvidia,function = "i2c1";
382 nvidia,pull = <0>; 382 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
383 nvidia,tristate = <0>; 383 nvidia,tristate = <TEGRA_PIN_DISABLE>;
384 nvidia,enable-input = <1>; 384 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
385 nvidia,lock = <0>; 385 nvidia,lock = <TEGRA_PIN_DISABLE>;
386 nvidia,open-drain = <0>; 386 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
387 }; 387 };
388 uart2_cts_n_pj5 { 388 uart2_cts_n_pj5 {
389 nvidia,pins = "uart2_cts_n_pj5"; 389 nvidia,pins = "uart2_cts_n_pj5";
390 nvidia,function = "uartb"; 390 nvidia,function = "uartb";
391 nvidia,pull = <0>; 391 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
392 nvidia,tristate = <1>; 392 nvidia,tristate = <TEGRA_PIN_ENABLE>;
393 nvidia,enable-input = <1>; 393 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
394 }; 394 };
395 uart2_rts_n_pj6 { 395 uart2_rts_n_pj6 {
396 nvidia,pins = "uart2_rts_n_pj6"; 396 nvidia,pins = "uart2_rts_n_pj6";
397 nvidia,function = "uartb"; 397 nvidia,function = "uartb";
398 nvidia,pull = <0>; 398 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
399 nvidia,tristate = <0>; 399 nvidia,tristate = <TEGRA_PIN_DISABLE>;
400 nvidia,enable-input = <0>; 400 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
401 }; 401 };
402 uart2_rxd_pc3 { 402 uart2_rxd_pc3 {
403 nvidia,pins = "uart2_rxd_pc3"; 403 nvidia,pins = "uart2_rxd_pc3";
404 nvidia,function = "irda"; 404 nvidia,function = "irda";
405 nvidia,pull = <0>; 405 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
406 nvidia,tristate = <1>; 406 nvidia,tristate = <TEGRA_PIN_ENABLE>;
407 nvidia,enable-input = <1>; 407 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
408 }; 408 };
409 uart2_txd_pc2 { 409 uart2_txd_pc2 {
410 nvidia,pins = "uart2_txd_pc2"; 410 nvidia,pins = "uart2_txd_pc2";
411 nvidia,function = "irda"; 411 nvidia,function = "irda";
412 nvidia,pull = <0>; 412 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
413 nvidia,tristate = <0>; 413 nvidia,tristate = <TEGRA_PIN_DISABLE>;
414 nvidia,enable-input = <0>; 414 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
415 }; 415 };
416 uart3_cts_n_pa1 { 416 uart3_cts_n_pa1 {
417 nvidia,pins = "uart3_cts_n_pa1", 417 nvidia,pins = "uart3_cts_n_pa1",
418 "uart3_rxd_pw7"; 418 "uart3_rxd_pw7";
419 nvidia,function = "uartc"; 419 nvidia,function = "uartc";
420 nvidia,pull = <0>; 420 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
421 nvidia,tristate = <1>; 421 nvidia,tristate = <TEGRA_PIN_ENABLE>;
422 nvidia,enable-input = <1>; 422 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
423 }; 423 };
424 uart3_rts_n_pc0 { 424 uart3_rts_n_pc0 {
425 nvidia,pins = "uart3_rts_n_pc0", 425 nvidia,pins = "uart3_rts_n_pc0",
426 "uart3_txd_pw6"; 426 "uart3_txd_pw6";
427 nvidia,function = "uartc"; 427 nvidia,function = "uartc";
428 nvidia,pull = <0>; 428 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
429 nvidia,tristate = <0>; 429 nvidia,tristate = <TEGRA_PIN_DISABLE>;
430 nvidia,enable-input = <0>; 430 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
431 }; 431 };
432 owr { 432 owr {
433 nvidia,pins = "owr"; 433 nvidia,pins = "owr";
434 nvidia,function = "owr"; 434 nvidia,function = "owr";
435 nvidia,pull = <0>; 435 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
436 nvidia,tristate = <0>; 436 nvidia,tristate = <TEGRA_PIN_DISABLE>;
437 nvidia,enable-input = <1>; 437 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
438 }; 438 };
439 hdmi_cec_pee3 { 439 hdmi_cec_pee3 {
440 nvidia,pins = "hdmi_cec_pee3"; 440 nvidia,pins = "hdmi_cec_pee3";
441 nvidia,function = "cec"; 441 nvidia,function = "cec";
442 nvidia,pull = <0>; 442 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
443 nvidia,tristate = <0>; 443 nvidia,tristate = <TEGRA_PIN_DISABLE>;
444 nvidia,enable-input = <1>; 444 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
445 nvidia,lock = <0>; 445 nvidia,lock = <TEGRA_PIN_DISABLE>;
446 nvidia,open-drain = <0>; 446 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
447 }; 447 };
448 ddc_scl_pv4 { 448 ddc_scl_pv4 {
449 nvidia,pins = "ddc_scl_pv4", 449 nvidia,pins = "ddc_scl_pv4",
450 "ddc_sda_pv5"; 450 "ddc_sda_pv5";
451 nvidia,function = "i2c4"; 451 nvidia,function = "i2c4";
452 nvidia,pull = <0>; 452 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
453 nvidia,tristate = <0>; 453 nvidia,tristate = <TEGRA_PIN_DISABLE>;
454 nvidia,enable-input = <1>; 454 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
455 nvidia,lock = <0>; 455 nvidia,lock = <TEGRA_PIN_DISABLE>;
456 nvidia,rcv-sel = <1>; 456 nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
457 }; 457 };
458 spdif_in_pk6 { 458 spdif_in_pk6 {
459 nvidia,pins = "spdif_in_pk6"; 459 nvidia,pins = "spdif_in_pk6";
460 nvidia,function = "usb"; 460 nvidia,function = "usb";
461 nvidia,pull = <2>; 461 nvidia,pull = <TEGRA_PIN_PULL_UP>;
462 nvidia,tristate = <0>; 462 nvidia,tristate = <TEGRA_PIN_DISABLE>;
463 nvidia,enable-input = <1>; 463 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
464 nvidia,lock = <0>; 464 nvidia,lock = <TEGRA_PIN_DISABLE>;
465 }; 465 };
466 usb_vbus_en0_pn4 { 466 usb_vbus_en0_pn4 {
467 nvidia,pins = "usb_vbus_en0_pn4"; 467 nvidia,pins = "usb_vbus_en0_pn4";
468 nvidia,function = "usb"; 468 nvidia,function = "usb";
469 nvidia,pull = <2>; 469 nvidia,pull = <TEGRA_PIN_PULL_UP>;
470 nvidia,tristate = <0>; 470 nvidia,tristate = <TEGRA_PIN_DISABLE>;
471 nvidia,enable-input = <1>; 471 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
472 nvidia,lock = <0>; 472 nvidia,lock = <TEGRA_PIN_DISABLE>;
473 nvidia,open-drain = <1>; 473 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
474 }; 474 };
475 gpio_x6_aud_px6 { 475 gpio_x6_aud_px6 {
476 nvidia,pins = "gpio_x6_aud_px6"; 476 nvidia,pins = "gpio_x6_aud_px6";
477 nvidia,function = "spi6"; 477 nvidia,function = "spi6";
478 nvidia,pull = <2>; 478 nvidia,pull = <TEGRA_PIN_PULL_UP>;
479 nvidia,tristate = <1>; 479 nvidia,tristate = <TEGRA_PIN_ENABLE>;
480 nvidia,enable-input = <1>; 480 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
481 }; 481 };
482 gpio_x4_aud_px4 { 482 gpio_x4_aud_px4 {
483 nvidia,pins = "gpio_x4_aud_px4", 483 nvidia,pins = "gpio_x4_aud_px4",
484 "gpio_x7_aud_px7"; 484 "gpio_x7_aud_px7";
485 nvidia,function = "rsvd1"; 485 nvidia,function = "rsvd1";
486 nvidia,pull = <1>; 486 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
487 nvidia,tristate = <0>; 487 nvidia,tristate = <TEGRA_PIN_DISABLE>;
488 nvidia,enable-input = <0>; 488 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
489 }; 489 };
490 gpio_x5_aud_px5 { 490 gpio_x5_aud_px5 {
491 nvidia,pins = "gpio_x5_aud_px5"; 491 nvidia,pins = "gpio_x5_aud_px5";
492 nvidia,function = "rsvd1"; 492 nvidia,function = "rsvd1";
493 nvidia,pull = <2>; 493 nvidia,pull = <TEGRA_PIN_PULL_UP>;
494 nvidia,tristate = <0>; 494 nvidia,tristate = <TEGRA_PIN_DISABLE>;
495 nvidia,enable-input = <1>; 495 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
496 }; 496 };
497 gpio_w2_aud_pw2 { 497 gpio_w2_aud_pw2 {
498 nvidia,pins = "gpio_w2_aud_pw2"; 498 nvidia,pins = "gpio_w2_aud_pw2";
499 nvidia,function = "rsvd2"; 499 nvidia,function = "rsvd2";
500 nvidia,pull = <2>; 500 nvidia,pull = <TEGRA_PIN_PULL_UP>;
501 nvidia,tristate = <0>; 501 nvidia,tristate = <TEGRA_PIN_DISABLE>;
502 nvidia,enable-input = <1>; 502 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
503 }; 503 };
504 gpio_w3_aud_pw3 { 504 gpio_w3_aud_pw3 {
505 nvidia,pins = "gpio_w3_aud_pw3"; 505 nvidia,pins = "gpio_w3_aud_pw3";
506 nvidia,function = "spi6"; 506 nvidia,function = "spi6";
507 nvidia,pull = <2>; 507 nvidia,pull = <TEGRA_PIN_PULL_UP>;
508 nvidia,tristate = <0>; 508 nvidia,tristate = <TEGRA_PIN_DISABLE>;
509 nvidia,enable-input = <1>; 509 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
510 }; 510 };
511 gpio_x1_aud_px1 { 511 gpio_x1_aud_px1 {
512 nvidia,pins = "gpio_x1_aud_px1"; 512 nvidia,pins = "gpio_x1_aud_px1";
513 nvidia,function = "rsvd4"; 513 nvidia,function = "rsvd4";
514 nvidia,pull = <1>; 514 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
515 nvidia,tristate = <0>; 515 nvidia,tristate = <TEGRA_PIN_DISABLE>;
516 nvidia,enable-input = <1>; 516 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
517 }; 517 };
518 gpio_x3_aud_px3 { 518 gpio_x3_aud_px3 {
519 nvidia,pins = "gpio_x3_aud_px3"; 519 nvidia,pins = "gpio_x3_aud_px3";
520 nvidia,function = "rsvd4"; 520 nvidia,function = "rsvd4";
521 nvidia,pull = <2>; 521 nvidia,pull = <TEGRA_PIN_PULL_UP>;
522 nvidia,tristate = <0>; 522 nvidia,tristate = <TEGRA_PIN_DISABLE>;
523 nvidia,enable-input = <1>; 523 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
524 }; 524 };
525 dap3_fs_pp0 { 525 dap3_fs_pp0 {
526 nvidia,pins = "dap3_fs_pp0"; 526 nvidia,pins = "dap3_fs_pp0";
527 nvidia,function = "i2s2"; 527 nvidia,function = "i2s2";
528 nvidia,pull = <1>; 528 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
529 nvidia,tristate = <0>; 529 nvidia,tristate = <TEGRA_PIN_DISABLE>;
530 nvidia,enable-input = <0>; 530 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
531 }; 531 };
532 dap3_dout_pp2 { 532 dap3_dout_pp2 {
533 nvidia,pins = "dap3_dout_pp2"; 533 nvidia,pins = "dap3_dout_pp2";
534 nvidia,function = "i2s2"; 534 nvidia,function = "i2s2";
535 nvidia,pull = <1>; 535 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
536 nvidia,tristate = <0>; 536 nvidia,tristate = <TEGRA_PIN_DISABLE>;
537 nvidia,enable-input = <0>; 537 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
538 }; 538 };
539 pv1 { 539 pv1 {
540 nvidia,pins = "pv1"; 540 nvidia,pins = "pv1";
541 nvidia,function = "rsvd1"; 541 nvidia,function = "rsvd1";
542 nvidia,pull = <0>; 542 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
543 nvidia,tristate = <0>; 543 nvidia,tristate = <TEGRA_PIN_DISABLE>;
544 nvidia,enable-input = <1>; 544 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
545 }; 545 };
546 pbb3 { 546 pbb3 {
547 nvidia,pins = "pbb3", 547 nvidia,pins = "pbb3",
@@ -549,25 +549,25 @@
549 "pbb6", 549 "pbb6",
550 "pbb7"; 550 "pbb7";
551 nvidia,function = "rsvd4"; 551 nvidia,function = "rsvd4";
552 nvidia,pull = <1>; 552 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
553 nvidia,tristate = <0>; 553 nvidia,tristate = <TEGRA_PIN_DISABLE>;
554 nvidia,enable-input = <0>; 554 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
555 }; 555 };
556 pcc1 { 556 pcc1 {
557 nvidia,pins = "pcc1", 557 nvidia,pins = "pcc1",
558 "pcc2"; 558 "pcc2";
559 nvidia,function = "rsvd4"; 559 nvidia,function = "rsvd4";
560 nvidia,pull = <1>; 560 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
561 nvidia,tristate = <0>; 561 nvidia,tristate = <TEGRA_PIN_DISABLE>;
562 nvidia,enable-input = <1>; 562 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
563 }; 563 };
564 gmi_ad0_pg0 { 564 gmi_ad0_pg0 {
565 nvidia,pins = "gmi_ad0_pg0", 565 nvidia,pins = "gmi_ad0_pg0",
566 "gmi_ad1_pg1"; 566 "gmi_ad1_pg1";
567 nvidia,function = "gmi"; 567 nvidia,function = "gmi";
568 nvidia,pull = <0>; 568 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
569 nvidia,tristate = <0>; 569 nvidia,tristate = <TEGRA_PIN_DISABLE>;
570 nvidia,enable-input = <0>; 570 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
571 }; 571 };
572 gmi_ad10_ph2 { 572 gmi_ad10_ph2 {
573 nvidia,pins = "gmi_ad10_ph2", 573 nvidia,pins = "gmi_ad10_ph2",
@@ -576,17 +576,17 @@
576 "gmi_ad8_ph0", 576 "gmi_ad8_ph0",
577 "gmi_clk_pk1"; 577 "gmi_clk_pk1";
578 nvidia,function = "gmi"; 578 nvidia,function = "gmi";
579 nvidia,pull = <1>; 579 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
580 nvidia,tristate = <0>; 580 nvidia,tristate = <TEGRA_PIN_DISABLE>;
581 nvidia,enable-input = <0>; 581 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
582 }; 582 };
583 gmi_ad2_pg2 { 583 gmi_ad2_pg2 {
584 nvidia,pins = "gmi_ad2_pg2", 584 nvidia,pins = "gmi_ad2_pg2",
585 "gmi_ad3_pg3"; 585 "gmi_ad3_pg3";
586 nvidia,function = "gmi"; 586 nvidia,function = "gmi";
587 nvidia,pull = <0>; 587 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
588 nvidia,tristate = <0>; 588 nvidia,tristate = <TEGRA_PIN_DISABLE>;
589 nvidia,enable-input = <1>; 589 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
590 }; 590 };
591 gmi_adv_n_pk0 { 591 gmi_adv_n_pk0 {
592 nvidia,pins = "gmi_adv_n_pk0", 592 nvidia,pins = "gmi_adv_n_pk0",
@@ -598,39 +598,39 @@
598 "gmi_iordy_pi5", 598 "gmi_iordy_pi5",
599 "gmi_wp_n_pc7"; 599 "gmi_wp_n_pc7";
600 nvidia,function = "gmi"; 600 nvidia,function = "gmi";
601 nvidia,pull = <2>; 601 nvidia,pull = <TEGRA_PIN_PULL_UP>;
602 nvidia,tristate = <0>; 602 nvidia,tristate = <TEGRA_PIN_DISABLE>;
603 nvidia,enable-input = <1>; 603 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
604 }; 604 };
605 gmi_cs3_n_pk4 { 605 gmi_cs3_n_pk4 {
606 nvidia,pins = "gmi_cs3_n_pk4"; 606 nvidia,pins = "gmi_cs3_n_pk4";
607 nvidia,function = "gmi"; 607 nvidia,function = "gmi";
608 nvidia,pull = <2>; 608 nvidia,pull = <TEGRA_PIN_PULL_UP>;
609 nvidia,tristate = <0>; 609 nvidia,tristate = <TEGRA_PIN_DISABLE>;
610 nvidia,enable-input = <0>; 610 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
611 }; 611 };
612 clk2_req_pcc5 { 612 clk2_req_pcc5 {
613 nvidia,pins = "clk2_req_pcc5"; 613 nvidia,pins = "clk2_req_pcc5";
614 nvidia,function = "rsvd4"; 614 nvidia,function = "rsvd4";
615 nvidia,pull = <0>; 615 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
616 nvidia,tristate = <0>; 616 nvidia,tristate = <TEGRA_PIN_DISABLE>;
617 nvidia,enable-input = <0>; 617 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
618 }; 618 };
619 kb_col3_pq3 { 619 kb_col3_pq3 {
620 nvidia,pins = "kb_col3_pq3", 620 nvidia,pins = "kb_col3_pq3",
621 "kb_col6_pq6", 621 "kb_col6_pq6",
622 "kb_col7_pq7"; 622 "kb_col7_pq7";
623 nvidia,function = "kbc"; 623 nvidia,function = "kbc";
624 nvidia,pull = <2>; 624 nvidia,pull = <TEGRA_PIN_PULL_UP>;
625 nvidia,tristate = <0>; 625 nvidia,tristate = <TEGRA_PIN_DISABLE>;
626 nvidia,enable-input = <0>; 626 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
627 }; 627 };
628 kb_col5_pq5 { 628 kb_col5_pq5 {
629 nvidia,pins = "kb_col5_pq5"; 629 nvidia,pins = "kb_col5_pq5";
630 nvidia,function = "kbc"; 630 nvidia,function = "kbc";
631 nvidia,pull = <2>; 631 nvidia,pull = <TEGRA_PIN_PULL_UP>;
632 nvidia,tristate = <0>; 632 nvidia,tristate = <TEGRA_PIN_DISABLE>;
633 nvidia,enable-input = <1>; 633 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
634 }; 634 };
635 kb_row3_pr3 { 635 kb_row3_pr3 {
636 nvidia,pins = "kb_row3_pr3", 636 nvidia,pins = "kb_row3_pr3",
@@ -638,77 +638,77 @@
638 "kb_row6_pr6", 638 "kb_row6_pr6",
639 "kb_row8_ps0"; 639 "kb_row8_ps0";
640 nvidia,function = "kbc"; 640 nvidia,function = "kbc";
641 nvidia,pull = <1>; 641 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
642 nvidia,tristate = <0>; 642 nvidia,tristate = <TEGRA_PIN_DISABLE>;
643 nvidia,enable-input = <1>; 643 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
644 }; 644 };
645 clk3_req_pee1 { 645 clk3_req_pee1 {
646 nvidia,pins = "clk3_req_pee1"; 646 nvidia,pins = "clk3_req_pee1";
647 nvidia,function = "rsvd4"; 647 nvidia,function = "rsvd4";
648 nvidia,pull = <0>; 648 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
649 nvidia,tristate = <0>; 649 nvidia,tristate = <TEGRA_PIN_DISABLE>;
650 nvidia,enable-input = <0>; 650 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
651 }; 651 };
652 pu4 { 652 pu4 {
653 nvidia,pins = "pu4"; 653 nvidia,pins = "pu4";
654 nvidia,function = "displayb"; 654 nvidia,function = "displayb";
655 nvidia,pull = <0>; 655 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
656 nvidia,tristate = <0>; 656 nvidia,tristate = <TEGRA_PIN_DISABLE>;
657 nvidia,enable-input = <0>; 657 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
658 }; 658 };
659 pu5 { 659 pu5 {
660 nvidia,pins = "pu5", 660 nvidia,pins = "pu5",
661 "pu6"; 661 "pu6";
662 nvidia,function = "displayb"; 662 nvidia,function = "displayb";
663 nvidia,pull = <0>; 663 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
664 nvidia,tristate = <0>; 664 nvidia,tristate = <TEGRA_PIN_DISABLE>;
665 nvidia,enable-input = <1>; 665 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
666 }; 666 };
667 hdmi_int_pn7 { 667 hdmi_int_pn7 {
668 nvidia,pins = "hdmi_int_pn7"; 668 nvidia,pins = "hdmi_int_pn7";
669 nvidia,function = "rsvd1"; 669 nvidia,function = "rsvd1";
670 nvidia,pull = <1>; 670 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
671 nvidia,tristate = <0>; 671 nvidia,tristate = <TEGRA_PIN_DISABLE>;
672 nvidia,enable-input = <1>; 672 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
673 }; 673 };
674 clk1_req_pee2 { 674 clk1_req_pee2 {
675 nvidia,pins = "clk1_req_pee2", 675 nvidia,pins = "clk1_req_pee2",
676 "usb_vbus_en1_pn5"; 676 "usb_vbus_en1_pn5";
677 nvidia,function = "rsvd4"; 677 nvidia,function = "rsvd4";
678 nvidia,pull = <1>; 678 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
679 nvidia,tristate = <1>; 679 nvidia,tristate = <TEGRA_PIN_ENABLE>;
680 nvidia,enable-input = <0>; 680 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
681 }; 681 };
682 682
683 drive_sdio1 { 683 drive_sdio1 {
684 nvidia,pins = "drive_sdio1"; 684 nvidia,pins = "drive_sdio1";
685 nvidia,high-speed-mode = <1>; 685 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
686 nvidia,schmitt = <0>; 686 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
687 nvidia,low-power-mode = <3>; 687 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
688 nvidia,pull-down-strength = <36>; 688 nvidia,pull-down-strength = <36>;
689 nvidia,pull-up-strength = <20>; 689 nvidia,pull-up-strength = <20>;
690 nvidia,slew-rate-rising = <2>; 690 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
691 nvidia,slew-rate-falling = <2>; 691 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
692 }; 692 };
693 drive_sdio3 { 693 drive_sdio3 {
694 nvidia,pins = "drive_sdio3"; 694 nvidia,pins = "drive_sdio3";
695 nvidia,high-speed-mode = <1>; 695 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
696 nvidia,schmitt = <0>; 696 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
697 nvidia,low-power-mode = <3>; 697 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
698 nvidia,pull-down-strength = <22>; 698 nvidia,pull-down-strength = <22>;
699 nvidia,pull-up-strength = <36>; 699 nvidia,pull-up-strength = <36>;
700 nvidia,slew-rate-rising = <0>; 700 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
701 nvidia,slew-rate-falling = <0>; 701 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
702 }; 702 };
703 drive_gma { 703 drive_gma {
704 nvidia,pins = "drive_gma"; 704 nvidia,pins = "drive_gma";
705 nvidia,high-speed-mode = <1>; 705 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
706 nvidia,schmitt = <0>; 706 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
707 nvidia,low-power-mode = <3>; 707 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
708 nvidia,pull-down-strength = <2>; 708 nvidia,pull-down-strength = <2>;
709 nvidia,pull-up-strength = <1>; 709 nvidia,pull-up-strength = <1>;
710 nvidia,slew-rate-rising = <0>; 710 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
711 nvidia,slew-rate-falling = <0>; 711 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
712 nvidia,drive-type = <1>; 712 nvidia,drive-type = <1>;
713 }; 713 };
714 }; 714 };
@@ -722,7 +722,7 @@
722 status = "okay"; 722 status = "okay";
723 clock-frequency = <100000>; 723 clock-frequency = <100000>;
724 724
725 battery: smart-battery { 725 battery: smart-battery@b {
726 compatible = "ti,bq20z45", "sbs,sbs-battery"; 726 compatible = "ti,bq20z45", "sbs,sbs-battery";
727 reg = <0xb>; 727 reg = <0xb>;
728 battery-name = "battery"; 728 battery-name = "battery";
@@ -731,7 +731,7 @@
731 power-supplies = <&charger>; 731 power-supplies = <&charger>;
732 }; 732 };
733 733
734 rt5640: rt5640 { 734 rt5640: rt5640@1c {
735 compatible = "realtek,rt5640"; 735 compatible = "realtek,rt5640";
736 reg = <0x1c>; 736 reg = <0x1c>;
737 interrupt-parent = <&gpio>; 737 interrupt-parent = <&gpio>;
@@ -753,7 +753,7 @@
753 status = "okay"; 753 status = "okay";
754 clock-frequency = <400000>; 754 clock-frequency = <400000>;
755 755
756 tps51632 { 756 tps51632@43 {
757 compatible = "ti,tps51632"; 757 compatible = "ti,tps51632";
758 reg = <0x43>; 758 reg = <0x43>;
759 regulator-name = "vdd-cpu"; 759 regulator-name = "vdd-cpu";
@@ -763,7 +763,7 @@
763 regulator-always-on; 763 regulator-always-on;
764 }; 764 };
765 765
766 tps65090 { 766 tps65090@48 {
767 compatible = "ti,tps65090"; 767 compatible = "ti,tps65090";
768 reg = <0x48>; 768 reg = <0x48>;
769 interrupt-parent = <&gpio>; 769 interrupt-parent = <&gpio>;
@@ -846,7 +846,7 @@
846 }; 846 };
847 }; 847 };
848 848
849 palmas: tps65913 { 849 palmas: tps65913@58 {
850 compatible = "ti,palmas"; 850 compatible = "ti,palmas";
851 reg = <0x58>; 851 reg = <0x58>;
852 interrupts = <0 86 IRQ_TYPE_LEVEL_LOW>; 852 interrupts = <0 86 IRQ_TYPE_LEVEL_LOW>;
@@ -1046,7 +1046,7 @@
1046 }; 1046 };
1047 }; 1047 };
1048 1048
1049 pmc { 1049 pmc@7000e400 {
1050 nvidia,invert-interrupt; 1050 nvidia,invert-interrupt;
1051 nvidia,suspend-mode = <1>; 1051 nvidia,suspend-mode = <1>;
1052 nvidia,cpu-pwr-good-time = <500>; 1052 nvidia,cpu-pwr-good-time = <500>;
@@ -1057,7 +1057,7 @@
1057 nvidia,sys-clock-req-active-high; 1057 nvidia,sys-clock-req-active-high;
1058 }; 1058 };
1059 1059
1060 ahub { 1060 ahub@70080000 {
1061 i2s@70080400 { 1061 i2s@70080400 {
1062 status = "okay"; 1062 status = "okay";
1063 }; 1063 };
@@ -1089,7 +1089,7 @@
1089 #address-cells = <1>; 1089 #address-cells = <1>;
1090 #size-cells = <0>; 1090 #size-cells = <0>;
1091 1091
1092 clk32k_in: clock { 1092 clk32k_in: clock@0 {
1093 compatible = "fixed-clock"; 1093 compatible = "fixed-clock";
1094 reg=<0>; 1094 reg=<0>;
1095 #clock-cells = <0>; 1095 #clock-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 731249fbe206..ae855ec60bbd 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -1,5 +1,6 @@
1#include <dt-bindings/clock/tegra114-car.h> 1#include <dt-bindings/clock/tegra114-car.h>
2#include <dt-bindings/gpio/tegra-gpio.h> 2#include <dt-bindings/gpio/tegra-gpio.h>
3#include <dt-bindings/pinctrl/pinctrl-tegra.h>
3#include <dt-bindings/interrupt-controller/arm-gic.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h>
4 5
5#include "skeleton.dtsi" 6#include "skeleton.dtsi"
@@ -15,7 +16,7 @@
15 serial3 = &uartd; 16 serial3 = &uartd;
16 }; 17 };
17 18
18 gic: interrupt-controller { 19 gic: interrupt-controller@50041000 {
19 compatible = "arm,cortex-a15-gic"; 20 compatible = "arm,cortex-a15-gic";
20 #interrupt-cells = <3>; 21 #interrupt-cells = <3>;
21 interrupt-controller; 22 interrupt-controller;
@@ -39,14 +40,14 @@
39 clocks = <&tegra_car TEGRA114_CLK_TIMER>; 40 clocks = <&tegra_car TEGRA114_CLK_TIMER>;
40 }; 41 };
41 42
42 tegra_car: clock { 43 tegra_car: clock@60006000 {
43 compatible = "nvidia,tegra114-car"; 44 compatible = "nvidia,tegra114-car";
44 reg = <0x60006000 0x1000>; 45 reg = <0x60006000 0x1000>;
45 #clock-cells = <1>; 46 #clock-cells = <1>;
46 #reset-cells = <1>; 47 #reset-cells = <1>;
47 }; 48 };
48 49
49 apbdma: dma { 50 apbdma: dma@6000a000 {
50 compatible = "nvidia,tegra114-apbdma"; 51 compatible = "nvidia,tegra114-apbdma";
51 reg = <0x6000a000 0x1400>; 52 reg = <0x6000a000 0x1400>;
52 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 53 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
@@ -87,12 +88,12 @@
87 #dma-cells = <1>; 88 #dma-cells = <1>;
88 }; 89 };
89 90
90 ahb: ahb { 91 ahb: ahb@6000c004 {
91 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; 92 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
92 reg = <0x6000c004 0x14c>; 93 reg = <0x6000c004 0x14c>;
93 }; 94 };
94 95
95 gpio: gpio { 96 gpio: gpio@6000d000 {
96 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; 97 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
97 reg = <0x6000d000 0x1000>; 98 reg = <0x6000d000 0x1000>;
98 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 99 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
@@ -109,7 +110,7 @@
109 interrupt-controller; 110 interrupt-controller;
110 }; 111 };
111 112
112 pinmux: pinmux { 113 pinmux: pinmux@70000868 {
113 compatible = "nvidia,tegra114-pinmux"; 114 compatible = "nvidia,tegra114-pinmux";
114 reg = <0x70000868 0x148 /* Pad control registers */ 115 reg = <0x70000868 0x148 /* Pad control registers */
115 0x70003000 0x40c>; /* Mux registers */ 116 0x70003000 0x40c>; /* Mux registers */
@@ -175,7 +176,7 @@
175 status = "disabled"; 176 status = "disabled";
176 }; 177 };
177 178
178 pwm: pwm { 179 pwm: pwm@7000a000 {
179 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; 180 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
180 reg = <0x7000a000 0x100>; 181 reg = <0x7000a000 0x100>;
181 #pwm-cells = <2>; 182 #pwm-cells = <2>;
@@ -350,14 +351,14 @@
350 status = "disabled"; 351 status = "disabled";
351 }; 352 };
352 353
353 rtc { 354 rtc@7000e000 {
354 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; 355 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
355 reg = <0x7000e000 0x100>; 356 reg = <0x7000e000 0x100>;
356 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 357 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&tegra_car TEGRA114_CLK_RTC>; 358 clocks = <&tegra_car TEGRA114_CLK_RTC>;
358 }; 359 };
359 360
360 kbc { 361 kbc@7000e200 {
361 compatible = "nvidia,tegra114-kbc"; 362 compatible = "nvidia,tegra114-kbc";
362 reg = <0x7000e200 0x100>; 363 reg = <0x7000e200 0x100>;
363 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 364 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
@@ -367,14 +368,14 @@
367 status = "disabled"; 368 status = "disabled";
368 }; 369 };
369 370
370 pmc { 371 pmc@7000e400 {
371 compatible = "nvidia,tegra114-pmc"; 372 compatible = "nvidia,tegra114-pmc";
372 reg = <0x7000e400 0x400>; 373 reg = <0x7000e400 0x400>;
373 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; 374 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
374 clock-names = "pclk", "clk32k_in"; 375 clock-names = "pclk", "clk32k_in";
375 }; 376 };
376 377
377 iommu { 378 iommu@70019010 {
378 compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu"; 379 compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
379 reg = <0x70019010 0x02c 380 reg = <0x70019010 0x02c
380 0x700191f0 0x010 381 0x700191f0 0x010
@@ -385,7 +386,7 @@
385 nvidia,ahb = <&ahb>; 386 nvidia,ahb = <&ahb>;
386 }; 387 };
387 388
388 ahub { 389 ahub@70080000 {
389 compatible = "nvidia,tegra114-ahub"; 390 compatible = "nvidia,tegra114-ahub";
390 reg = <0x70080000 0x200>, 391 reg = <0x70080000 0x200>,
391 <0x70080200 0x100>, 392 <0x70080200 0x100>,
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
index 431d67a2b413..d6bb25c78c62 100644
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -10,10 +10,390 @@
10 reg = <0x80000000 0x80000000>; 10 reg = <0x80000000 0x80000000>;
11 }; 11 };
12 12
13 pinmux: pinmux@70000868 {
14 pinctrl-names = "default";
15 pinctrl-0 = <&pinmux_default>;
16
17 pinmux_default: common {
18 dap_mclk1_pw4 {
19 nvidia,pins = "dap_mclk1_pw4";
20 nvidia,function = "extperiph1";
21 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
22 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
23 nvidia,tristate = <TEGRA_PIN_DISABLE>;
24 };
25 dap1_din_pn1 {
26 nvidia,pins = "dap1_din_pn1",
27 "dap1_dout_pn2",
28 "dap1_fs_pn0",
29 "dap1_sclk_pn3";
30 nvidia,function = "i2s0";
31 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
32 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
33 nvidia,tristate = <TEGRA_PIN_ENABLE>;
34 };
35 dap2_din_pa4 {
36 nvidia,pins = "dap2_din_pa4",
37 "dap2_dout_pa5",
38 "dap2_fs_pa2",
39 "dap2_sclk_pa3";
40 nvidia,function = "i2s1";
41 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
42 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
43 nvidia,tristate = <TEGRA_PIN_DISABLE>;
44 };
45 dvfs_pwm_px0 {
46 nvidia,pins = "dvfs_pwm_px0";
47 nvidia,function = "cldvfs";
48 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
49 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
50 nvidia,tristate = <TEGRA_PIN_ENABLE>;
51 };
52 dvfs_clk_px2 {
53 nvidia,pins = "dvfs_clk_px2";
54 nvidia,function = "cldvfs";
55 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
56 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
57 nvidia,tristate = <TEGRA_PIN_DISABLE>;
58 };
59 ulpi_clk_py0 {
60 nvidia,pins = "ulpi_clk_py0",
61 "ulpi_dir_py1",
62 "ulpi_nxt_py2",
63 "ulpi_stp_py3";
64 nvidia,function = "spi1";
65 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
66 nvidia,pull = <TEGRA_PIN_PULL_UP>;
67 nvidia,tristate = <TEGRA_PIN_DISABLE>;
68 };
69 cam_i2c_scl_pbb1 {
70 nvidia,pins = "cam_i2c_scl_pbb1",
71 "cam_i2c_sda_pbb2";
72 nvidia,function = "i2c3";
73 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
74 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
75 nvidia,tristate = <TEGRA_PIN_DISABLE>;
76 nvidia,lock = <TEGRA_PIN_DISABLE>;
77 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
78 };
79 gen2_i2c_scl_pt5 {
80 nvidia,pins = "gen2_i2c_scl_pt5",
81 "gen2_i2c_sda_pt6";
82 nvidia,function = "i2c2";
83 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
84 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
85 nvidia,tristate = <TEGRA_PIN_DISABLE>;
86 nvidia,lock = <TEGRA_PIN_DISABLE>;
87 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
88 };
89 pg4 {
90 nvidia,pins = "pg4",
91 "pg5",
92 "pg6",
93 "pg7",
94 "pi3";
95 nvidia,function = "spi4";
96 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
97 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
98 nvidia,tristate = <TEGRA_PIN_DISABLE>;
99 };
100 ph0 {
101 nvidia,pins = "ph0";
102 nvidia,function = "pwm0";
103 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
104 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
105 nvidia,tristate = <TEGRA_PIN_ENABLE>;
106 };
107 ph1 {
108 nvidia,pins = "ph1";
109 nvidia,function = "pwm1";
110 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
111 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
112 nvidia,tristate = <TEGRA_PIN_DISABLE>;
113 };
114 ph2 {
115 nvidia,pins = "ph2";
116 nvidia,function = "gmi";
117 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
118 nvidia,tristate = <TEGRA_PIN_DISABLE>;
119 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
120 };
121 sdmmc1_clk_pz0 {
122 nvidia,pins = "sdmmc1_clk_pz0",
123 "sdmmc1_cmd_pz1",
124 "sdmmc1_dat0_py7",
125 "sdmmc1_dat1_py6",
126 "sdmmc1_dat2_py5",
127 "sdmmc1_dat3_py4";
128 nvidia,function = "sdmmc1";
129 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
130 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
131 nvidia,tristate = <TEGRA_PIN_DISABLE>;
132 };
133 sdmmc3_clk_pa6 {
134 nvidia,pins = "sdmmc3_clk_pa6";
135 nvidia,function = "sdmmc3";
136 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
137 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
138 nvidia,tristate = <TEGRA_PIN_DISABLE>;
139 };
140 sdmmc3_cmd_pa7 {
141 nvidia,pins = "sdmmc3_cmd_pa7",
142 "sdmmc3_dat0_pb7",
143 "sdmmc3_dat1_pb6",
144 "sdmmc3_dat2_pb5",
145 "sdmmc3_dat3_pb4",
146 "sdmmc3_clk_lb_out_pee4",
147 "sdmmc3_clk_lb_in_pee5";
148 nvidia,function = "sdmmc3";
149 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
150 nvidia,pull = <TEGRA_PIN_PULL_UP>;
151 nvidia,tristate = <TEGRA_PIN_DISABLE>;
152 };
153 sdmmc4_clk_pcc4 {
154 nvidia,pins = "sdmmc4_clk_pcc4";
155 nvidia,function = "sdmmc4";
156 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
157 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
158 nvidia,tristate = <TEGRA_PIN_DISABLE>;
159 };
160 sdmmc4_cmd_pt7 {
161 nvidia,pins = "sdmmc4_cmd_pt7",
162 "sdmmc4_dat0_paa0",
163 "sdmmc4_dat1_paa1",
164 "sdmmc4_dat2_paa2",
165 "sdmmc4_dat3_paa3",
166 "sdmmc4_dat4_paa4",
167 "sdmmc4_dat5_paa5",
168 "sdmmc4_dat6_paa6",
169 "sdmmc4_dat7_paa7";
170 nvidia,function = "sdmmc4";
171 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
172 nvidia,pull = <TEGRA_PIN_PULL_UP>;
173 nvidia,tristate = <TEGRA_PIN_DISABLE>;
174 };
175 pwr_i2c_scl_pz6 {
176 nvidia,pins = "pwr_i2c_scl_pz6",
177 "pwr_i2c_sda_pz7";
178 nvidia,function = "i2cpwr";
179 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
180 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
181 nvidia,tristate = <TEGRA_PIN_DISABLE>;
182 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
183 };
184 jtag_rtck {
185 nvidia,pins = "jtag_rtck";
186 nvidia,function = "rtck";
187 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
188 nvidia,pull = <TEGRA_PIN_PULL_UP>;
189 nvidia,tristate = <TEGRA_PIN_DISABLE>;
190 };
191 clk_32k_in {
192 nvidia,pins = "clk_32k_in";
193 nvidia,function = "clk";
194 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
195 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
196 nvidia,tristate = <TEGRA_PIN_DISABLE>;
197 };
198 core_pwr_req {
199 nvidia,pins = "core_pwr_req";
200 nvidia,function = "pwron";
201 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
202 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
203 nvidia,tristate = <TEGRA_PIN_DISABLE>;
204 };
205 cpu_pwr_req {
206 nvidia,pins = "cpu_pwr_req";
207 nvidia,function = "cpu";
208 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
209 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
210 nvidia,tristate = <TEGRA_PIN_DISABLE>;
211 };
212 pwr_int_n {
213 nvidia,pins = "pwr_int_n";
214 nvidia,function = "pmi";
215 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
216 nvidia,pull = <TEGRA_PIN_PULL_UP>;
217 nvidia,tristate = <TEGRA_PIN_DISABLE>;
218 };
219 reset_out_n {
220 nvidia,pins = "reset_out_n";
221 nvidia,function = "reset_out_n";
222 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
223 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
224 nvidia,tristate = <TEGRA_PIN_DISABLE>;
225 };
226 clk3_out_pee0 {
227 nvidia,pins = "clk3_out_pee0";
228 nvidia,function = "extperiph3";
229 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
230 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
231 nvidia,tristate = <TEGRA_PIN_DISABLE>;
232 };
233 dap4_din_pp5 {
234 nvidia,pins = "dap4_din_pp5",
235 "dap4_dout_pp6",
236 "dap4_fs_pp4",
237 "dap4_sclk_pp7";
238 nvidia,function = "i2s3";
239 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
240 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
241 nvidia,tristate = <TEGRA_PIN_ENABLE>;
242 };
243 gen1_i2c_sda_pc5 {
244 nvidia,pins = "gen1_i2c_sda_pc5",
245 "gen1_i2c_scl_pc4";
246 nvidia,function = "i2c1";
247 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
248 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
249 nvidia,tristate = <TEGRA_PIN_DISABLE>;
250 nvidia,lock = <TEGRA_PIN_DISABLE>;
251 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
252 };
253 pu0 {
254 nvidia,pins = "pu0",
255 "pu1",
256 "pu2",
257 "pu3";
258 nvidia,function = "uarta";
259 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
260 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
261 nvidia,tristate = <TEGRA_PIN_DISABLE>;
262 };
263 uart2_cts_n_pj5 {
264 nvidia,pins = "uart2_cts_n_pj5",
265 "uart2_rts_n_pj6";
266 nvidia,function = "uartb";
267 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
268 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
269 nvidia,tristate = <TEGRA_PIN_DISABLE>;
270 };
271 uart2_rxd_pc3 {
272 nvidia,pins = "uart2_rxd_pc3",
273 "uart2_txd_pc2";
274 nvidia,function = "irda";
275 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
276 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
277 nvidia,tristate = <TEGRA_PIN_DISABLE>;
278 };
279 uart3_cts_n_pa1 {
280 nvidia,pins = "uart3_cts_n_pa1",
281 "uart3_rts_n_pc0",
282 "uart3_rxd_pw7",
283 "uart3_txd_pw6";
284 nvidia,function = "uartc";
285 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
286 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
287 nvidia,tristate = <TEGRA_PIN_DISABLE>;
288 };
289 hdmi_cec_pee3 {
290 nvidia,pins = "hdmi_cec_pee3";
291 nvidia,function = "cec";
292 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
293 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
294 nvidia,tristate = <TEGRA_PIN_DISABLE>;
295 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
296 };
297 ddc_scl_pv4 {
298 nvidia,pins = "ddc_scl_pv4",
299 "ddc_sda_pv5";
300 nvidia,function = "i2c4";
301 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
302 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
303 nvidia,tristate = <TEGRA_PIN_DISABLE>;
304 };
305 usb_vbus_en0_pn4 {
306 nvidia,pins = "usb_vbus_en0_pn4";
307 nvidia,function = "usb";
308 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
309 nvidia,pull = <TEGRA_PIN_PULL_UP>;
310 nvidia,tristate = <TEGRA_PIN_DISABLE>;
311 nvidia,lock = <TEGRA_PIN_DISABLE>;
312 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
313 };
314 usb_vbus_en1_pn5 {
315 nvidia,pins = "usb_vbus_en1_pn5";
316 nvidia,function = "usb";
317 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
318 nvidia,pull = <TEGRA_PIN_PULL_UP>;
319 nvidia,tristate = <TEGRA_PIN_DISABLE>;
320 nvidia,lock = <TEGRA_PIN_DISABLE>;
321 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
322 };
323 drive_sdio1 {
324 nvidia,pins = "drive_sdio1";
325 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
326 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
327 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
328 nvidia,pull-down-strength = <32>;
329 nvidia,pull-up-strength = <42>;
330 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
331 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
332 };
333 drive_sdio3 {
334 nvidia,pins = "drive_sdio3";
335 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
336 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
337 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
338 nvidia,pull-down-strength = <20>;
339 nvidia,pull-up-strength = <36>;
340 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
341 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
342 };
343 drive_gma {
344 nvidia,pins = "drive_gma";
345 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
346 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
347 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
348 nvidia,pull-down-strength = <1>;
349 nvidia,pull-up-strength = <2>;
350 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
351 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
352 nvidia,drive-type = <1>;
353 };
354 };
355 };
356
13 serial@70006000 { 357 serial@70006000 {
14 status = "okay"; 358 status = "okay";
15 }; 359 };
16 360
361 pwm: pwm@7000a000 {
362 status = "okay";
363 };
364
365 i2c@7000c000 {
366 status = "okay";
367 clock-frequency = <100000>;
368
369 acodec: audio-codec@10 {
370 compatible = "maxim,max98090";
371 reg = <0x10>;
372 interrupt-parent = <&gpio>;
373 interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
374 };
375 };
376
377 i2c@7000c400 {
378 status = "okay";
379 clock-frequency = <100000>;
380 };
381
382 i2c@7000c500 {
383 status = "okay";
384 clock-frequency = <100000>;
385 };
386
387 i2c@7000c700 {
388 status = "okay";
389 clock-frequency = <100000>;
390 };
391
392 i2c@7000d000 {
393 status = "okay";
394 clock-frequency = <100000>;
395 };
396
17 pmc@7000e400 { 397 pmc@7000e400 {
18 nvidia,invert-interrupt; 398 nvidia,invert-interrupt;
19 nvidia,suspend-mode = <1>; 399 nvidia,suspend-mode = <1>;
@@ -24,4 +404,57 @@
24 nvidia,core-power-req-active-high; 404 nvidia,core-power-req-active-high;
25 nvidia,sys-clock-req-active-high; 405 nvidia,sys-clock-req-active-high;
26 }; 406 };
407
408 sdhci@700b0400 {
409 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
410 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
411 status = "okay";
412 bus-width = <4>;
413 };
414
415 sdhci@700b0600 {
416 status = "okay";
417 bus-width = <8>;
418 };
419
420 ahub@70300000 {
421 i2s@70301100 {
422 status = "okay";
423 };
424 };
425
426 clocks {
427 compatible = "simple-bus";
428 #address-cells = <1>;
429 #size-cells = <0>;
430
431 clk32k_in: clock@0 {
432 compatible = "fixed-clock";
433 reg=<0>;
434 #clock-cells = <0>;
435 clock-frequency = <32768>;
436 };
437 };
438
439 sound {
440 compatible = "nvidia,tegra-audio-max98090-venice2",
441 "nvidia,tegra-audio-max98090";
442 nvidia,model = "NVIDIA Tegra Venice2";
443
444 nvidia,audio-routing =
445 "Headphones", "HPR",
446 "Headphones", "HPL",
447 "Speakers", "SPKR",
448 "Speakers", "SPKL",
449 "Mic Jack", "MICBIAS",
450 "IN34", "Mic Jack";
451
452 nvidia,i2s-controller = <&tegra_i2s1>;
453 nvidia,audio-codec = <&acodec>;
454
455 clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
456 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
457 <&tegra_car TEGRA124_CLK_EXTERN1>;
458 clock-names = "pll_a", "pll_a_out0", "mclk";
459 };
27}; 460};
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index b7413004ee77..ec0698a8354a 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -1,4 +1,6 @@
1#include <dt-bindings/clock/tegra124-car.h>
1#include <dt-bindings/gpio/tegra-gpio.h> 2#include <dt-bindings/gpio/tegra-gpio.h>
3#include <dt-bindings/pinctrl/pinctrl-tegra.h>
2#include <dt-bindings/interrupt-controller/arm-gic.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h>
3 5
4#include "skeleton.dtsi" 6#include "skeleton.dtsi"
@@ -28,6 +30,14 @@
28 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
29 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
30 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 32 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
33 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
34 };
35
36 tegra_car: clock@60006000 {
37 compatible = "nvidia,tegra124-car";
38 reg = <0x60006000 0x1000>;
39 #clock-cells = <1>;
40 #reset-cells = <1>;
31 }; 41 };
32 42
33 gpio: gpio@6000d000 { 43 gpio: gpio@6000d000 {
@@ -47,6 +57,53 @@
47 interrupt-controller; 57 interrupt-controller;
48 }; 58 };
49 59
60 apbdma: dma@60020000 {
61 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
62 reg = <0x60020000 0x1400>;
63 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
64 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
65 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
66 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
68 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
69 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
70 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
72 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
73 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
74 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
75 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
78 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
88 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
89 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
90 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
91 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
92 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
95 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
96 resets = <&tegra_car 34>;
97 reset-names = "dma";
98 #dma-cells = <1>;
99 };
100
101 pinmux: pinmux@70000868 {
102 compatible = "nvidia,tegra124-pinmux";
103 reg = <0x70000868 0x164>, /* Pad control registers */
104 <0x70003000 0x434>; /* Mux registers */
105 };
106
50 /* 107 /*
51 * There are two serial driver i.e. 8250 based simple serial 108 * There are two serial driver i.e. 8250 based simple serial
52 * driver and APB DMA based serial driver for higher baudrate 109 * driver and APB DMA based serial driver for higher baudrate
@@ -60,6 +117,11 @@
60 reg = <0x70006000 0x40>; 117 reg = <0x70006000 0x40>;
61 reg-shift = <2>; 118 reg-shift = <2>;
62 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 119 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
120 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
121 resets = <&tegra_car 6>;
122 reset-names = "serial";
123 dmas = <&apbdma 8>, <&apbdma 8>;
124 dma-names = "rx", "tx";
63 status = "disabled"; 125 status = "disabled";
64 }; 126 };
65 127
@@ -68,6 +130,11 @@
68 reg = <0x70006040 0x40>; 130 reg = <0x70006040 0x40>;
69 reg-shift = <2>; 131 reg-shift = <2>;
70 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 132 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
133 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
134 resets = <&tegra_car 7>;
135 reset-names = "serial";
136 dmas = <&apbdma 9>, <&apbdma 9>;
137 dma-names = "rx", "tx";
71 status = "disabled"; 138 status = "disabled";
72 }; 139 };
73 140
@@ -76,6 +143,11 @@
76 reg = <0x70006200 0x40>; 143 reg = <0x70006200 0x40>;
77 reg-shift = <2>; 144 reg-shift = <2>;
78 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 145 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
147 resets = <&tegra_car 55>;
148 reset-names = "serial";
149 dmas = <&apbdma 10>, <&apbdma 10>;
150 dma-names = "rx", "tx";
79 status = "disabled"; 151 status = "disabled";
80 }; 152 };
81 153
@@ -84,6 +156,11 @@
84 reg = <0x70006300 0x40>; 156 reg = <0x70006300 0x40>;
85 reg-shift = <2>; 157 reg-shift = <2>;
86 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 158 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
159 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
160 resets = <&tegra_car 65>;
161 reset-names = "serial";
162 dmas = <&apbdma 19>, <&apbdma 19>;
163 dma-names = "rx", "tx";
87 status = "disabled"; 164 status = "disabled";
88 }; 165 };
89 166
@@ -92,6 +169,201 @@
92 reg = <0x70006400 0x40>; 169 reg = <0x70006400 0x40>;
93 reg-shift = <2>; 170 reg-shift = <2>;
94 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 171 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
172 clocks = <&tegra_car TEGRA124_CLK_UARTE>;
173 resets = <&tegra_car 66>;
174 reset-names = "serial";
175 dmas = <&apbdma 20>, <&apbdma 20>;
176 dma-names = "rx", "tx";
177 status = "disabled";
178 };
179
180 pwm@7000a000 {
181 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
182 reg = <0x7000a000 0x100>;
183 #pwm-cells = <2>;
184 clocks = <&tegra_car TEGRA124_CLK_PWM>;
185 resets = <&tegra_car 17>;
186 reset-names = "pwm";
187 status = "disabled";
188 };
189
190 i2c@7000c000 {
191 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
192 reg = <0x7000c000 0x100>;
193 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
194 #address-cells = <1>;
195 #size-cells = <0>;
196 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
197 clock-names = "div-clk";
198 resets = <&tegra_car 12>;
199 reset-names = "i2c";
200 dmas = <&apbdma 21>, <&apbdma 21>;
201 dma-names = "rx", "tx";
202 status = "disabled";
203 };
204
205 i2c@7000c400 {
206 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
207 reg = <0x7000c400 0x100>;
208 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
209 #address-cells = <1>;
210 #size-cells = <0>;
211 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
212 clock-names = "div-clk";
213 resets = <&tegra_car 54>;
214 reset-names = "i2c";
215 dmas = <&apbdma 22>, <&apbdma 22>;
216 dma-names = "rx", "tx";
217 status = "disabled";
218 };
219
220 i2c@7000c500 {
221 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
222 reg = <0x7000c500 0x100>;
223 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
224 #address-cells = <1>;
225 #size-cells = <0>;
226 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
227 clock-names = "div-clk";
228 resets = <&tegra_car 67>;
229 reset-names = "i2c";
230 dmas = <&apbdma 23>, <&apbdma 23>;
231 dma-names = "rx", "tx";
232 status = "disabled";
233 };
234
235 i2c@7000c700 {
236 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
237 reg = <0x7000c700 0x100>;
238 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
239 #address-cells = <1>;
240 #size-cells = <0>;
241 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
242 clock-names = "div-clk";
243 resets = <&tegra_car 103>;
244 reset-names = "i2c";
245 dmas = <&apbdma 26>, <&apbdma 26>;
246 dma-names = "rx", "tx";
247 status = "disabled";
248 };
249
250 i2c@7000d000 {
251 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
252 reg = <0x7000d000 0x100>;
253 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
254 #address-cells = <1>;
255 #size-cells = <0>;
256 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
257 clock-names = "div-clk";
258 resets = <&tegra_car 47>;
259 reset-names = "i2c";
260 dmas = <&apbdma 24>, <&apbdma 24>;
261 dma-names = "rx", "tx";
262 status = "disabled";
263 };
264
265 i2c@7000d100 {
266 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
267 reg = <0x7000d100 0x100>;
268 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
269 #address-cells = <1>;
270 #size-cells = <0>;
271 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
272 clock-names = "div-clk";
273 resets = <&tegra_car 166>;
274 reset-names = "i2c";
275 dmas = <&apbdma 30>, <&apbdma 30>;
276 dma-names = "rx", "tx";
277 status = "disabled";
278 };
279
280 spi@7000d400 {
281 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
282 reg = <0x7000d400 0x200>;
283 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
284 #address-cells = <1>;
285 #size-cells = <0>;
286 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
287 clock-names = "spi";
288 resets = <&tegra_car 41>;
289 reset-names = "spi";
290 dmas = <&apbdma 15>, <&apbdma 15>;
291 dma-names = "rx", "tx";
292 status = "disabled";
293 };
294
295 spi@7000d600 {
296 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
297 reg = <0x7000d600 0x200>;
298 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
299 #address-cells = <1>;
300 #size-cells = <0>;
301 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
302 clock-names = "spi";
303 resets = <&tegra_car 44>;
304 reset-names = "spi";
305 dmas = <&apbdma 16>, <&apbdma 16>;
306 dma-names = "rx", "tx";
307 status = "disabled";
308 };
309
310 spi@7000d800 {
311 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
312 reg = <0x7000d800 0x200>;
313 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
314 #address-cells = <1>;
315 #size-cells = <0>;
316 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
317 clock-names = "spi";
318 resets = <&tegra_car 46>;
319 reset-names = "spi";
320 dmas = <&apbdma 17>, <&apbdma 17>;
321 dma-names = "rx", "tx";
322 status = "disabled";
323 };
324
325 spi@7000da00 {
326 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
327 reg = <0x7000da00 0x200>;
328 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
329 #address-cells = <1>;
330 #size-cells = <0>;
331 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
332 clock-names = "spi";
333 resets = <&tegra_car 68>;
334 reset-names = "spi";
335 dmas = <&apbdma 18>, <&apbdma 18>;
336 dma-names = "rx", "tx";
337 status = "disabled";
338 };
339
340 spi@7000dc00 {
341 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
342 reg = <0x7000dc00 0x200>;
343 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
344 #address-cells = <1>;
345 #size-cells = <0>;
346 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
347 clock-names = "spi";
348 resets = <&tegra_car 104>;
349 reset-names = "spi";
350 dmas = <&apbdma 27>, <&apbdma 27>;
351 dma-names = "rx", "tx";
352 status = "disabled";
353 };
354
355 spi@7000de00 {
356 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
357 reg = <0x7000de00 0x200>;
358 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
359 #address-cells = <1>;
360 #size-cells = <0>;
361 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
362 clock-names = "spi";
363 resets = <&tegra_car 105>;
364 reset-names = "spi";
365 dmas = <&apbdma 28>, <&apbdma 28>;
366 dma-names = "rx", "tx";
95 status = "disabled"; 367 status = "disabled";
96 }; 368 };
97 369
@@ -99,11 +371,157 @@
99 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; 371 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
100 reg = <0x7000e000 0x100>; 372 reg = <0x7000e000 0x100>;
101 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 373 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&tegra_car TEGRA124_CLK_RTC>;
102 }; 375 };
103 376
104 pmc@7000e400 { 377 pmc@7000e400 {
105 compatible = "nvidia,tegra124-pmc"; 378 compatible = "nvidia,tegra124-pmc";
106 reg = <0x7000e400 0x400>; 379 reg = <0x7000e400 0x400>;
380 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
381 clock-names = "pclk", "clk32k_in";
382 };
383
384 sdhci@700b0000 {
385 compatible = "nvidia,tegra124-sdhci";
386 reg = <0x700b0000 0x200>;
387 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
389 resets = <&tegra_car 14>;
390 reset-names = "sdhci";
391 status = "disable";
392 };
393
394 sdhci@700b0200 {
395 compatible = "nvidia,tegra124-sdhci";
396 reg = <0x700b0200 0x200>;
397 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
399 resets = <&tegra_car 9>;
400 reset-names = "sdhci";
401 status = "disable";
402 };
403
404 sdhci@700b0400 {
405 compatible = "nvidia,tegra124-sdhci";
406 reg = <0x700b0400 0x200>;
407 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
409 resets = <&tegra_car 69>;
410 reset-names = "sdhci";
411 status = "disable";
412 };
413
414 sdhci@700b0600 {
415 compatible = "nvidia,tegra124-sdhci";
416 reg = <0x700b0600 0x200>;
417 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
419 resets = <&tegra_car 15>;
420 reset-names = "sdhci";
421 status = "disable";
422 };
423
424 ahub@70300000 {
425 compatible = "nvidia,tegra124-ahub";
426 reg = <0x70300000 0x200>,
427 <0x70300800 0x800>,
428 <0x70300200 0x600>;
429 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
431 <&tegra_car TEGRA124_CLK_APBIF>;
432 clock-names = "d_audio", "apbif";
433 resets = <&tegra_car 106>, /* d_audio */
434 <&tegra_car 107>, /* apbif */
435 <&tegra_car 30>, /* i2s0 */
436 <&tegra_car 11>, /* i2s1 */
437 <&tegra_car 18>, /* i2s2 */
438 <&tegra_car 101>, /* i2s3 */
439 <&tegra_car 102>, /* i2s4 */
440 <&tegra_car 108>, /* dam0 */
441 <&tegra_car 109>, /* dam1 */
442 <&tegra_car 110>, /* dam2 */
443 <&tegra_car 10>, /* spdif */
444 <&tegra_car 153>, /* amx */
445 <&tegra_car 185>, /* amx1 */
446 <&tegra_car 154>, /* adx */
447 <&tegra_car 180>, /* adx1 */
448 <&tegra_car 186>, /* afc0 */
449 <&tegra_car 187>, /* afc1 */
450 <&tegra_car 188>, /* afc2 */
451 <&tegra_car 189>, /* afc3 */
452 <&tegra_car 190>, /* afc4 */
453 <&tegra_car 191>; /* afc5 */
454 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
455 "i2s3", "i2s4", "dam0", "dam1", "dam2",
456 "spdif", "amx", "amx1", "adx", "adx1",
457 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
458 dmas = <&apbdma 1>, <&apbdma 1>,
459 <&apbdma 2>, <&apbdma 2>,
460 <&apbdma 3>, <&apbdma 3>,
461 <&apbdma 4>, <&apbdma 4>,
462 <&apbdma 6>, <&apbdma 6>,
463 <&apbdma 7>, <&apbdma 7>,
464 <&apbdma 12>, <&apbdma 12>,
465 <&apbdma 13>, <&apbdma 13>,
466 <&apbdma 14>, <&apbdma 14>,
467 <&apbdma 29>, <&apbdma 29>;
468 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
469 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
470 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
471 "rx9", "tx9";
472 ranges;
473 #address-cells = <1>;
474 #size-cells = <1>;
475
476 tegra_i2s0: i2s@70301000 {
477 compatible = "nvidia,tegra124-i2s";
478 reg = <0x70301000 0x100>;
479 nvidia,ahub-cif-ids = <4 4>;
480 clocks = <&tegra_car TEGRA124_CLK_I2S0>;
481 resets = <&tegra_car 30>;
482 reset-names = "i2s";
483 status = "disabled";
484 };
485
486 tegra_i2s1: i2s@70301100 {
487 compatible = "nvidia,tegra124-i2s";
488 reg = <0x70301100 0x100>;
489 nvidia,ahub-cif-ids = <5 5>;
490 clocks = <&tegra_car TEGRA124_CLK_I2S1>;
491 resets = <&tegra_car 11>;
492 reset-names = "i2s";
493 status = "disabled";
494 };
495
496 tegra_i2s2: i2s@70301200 {
497 compatible = "nvidia,tegra124-i2s";
498 reg = <0x70301200 0x100>;
499 nvidia,ahub-cif-ids = <6 6>;
500 clocks = <&tegra_car TEGRA124_CLK_I2S2>;
501 resets = <&tegra_car 18>;
502 reset-names = "i2s";
503 status = "disabled";
504 };
505
506 tegra_i2s3: i2s@70301300 {
507 compatible = "nvidia,tegra124-i2s";
508 reg = <0x70301300 0x100>;
509 nvidia,ahub-cif-ids = <7 7>;
510 clocks = <&tegra_car TEGRA124_CLK_I2S3>;
511 resets = <&tegra_car 101>;
512 reset-names = "i2s";
513 status = "disabled";
514 };
515
516 tegra_i2s4: i2s@70301400 {
517 compatible = "nvidia,tegra124-i2s";
518 reg = <0x70301400 0x100>;
519 nvidia,ahub-cif-ids = <8 8>;
520 clocks = <&tegra_car TEGRA124_CLK_I2S4>;
521 resets = <&tegra_car 102>;
522 reset-names = "i2s";
523 status = "disabled";
524 };
107 }; 525 };
108 526
109 cpus { 527 cpus {
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index d5c9bca01232..81c2c902580a 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -8,8 +8,8 @@
8 reg = <0x00000000 0x20000000>; 8 reg = <0x00000000 0x20000000>;
9 }; 9 };
10 10
11 host1x { 11 host1x@50000000 {
12 hdmi { 12 hdmi@54280000 {
13 vdd-supply = <&hdmi_vdd_reg>; 13 vdd-supply = <&hdmi_vdd_reg>;
14 pll-supply = <&hdmi_pll_reg>; 14 pll-supply = <&hdmi_pll_reg>;
15 15
@@ -19,7 +19,7 @@
19 }; 19 };
20 }; 20 };
21 21
22 pinmux { 22 pinmux@70000014 {
23 pinctrl-names = "default"; 23 pinctrl-names = "default";
24 pinctrl-0 = <&state_default>; 24 pinctrl-0 = <&state_default>;
25 25
@@ -27,20 +27,20 @@
27 audio_refclk { 27 audio_refclk {
28 nvidia,pins = "cdev1"; 28 nvidia,pins = "cdev1";
29 nvidia,function = "plla_out"; 29 nvidia,function = "plla_out";
30 nvidia,pull = <0>; 30 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
31 nvidia,tristate = <0>; 31 nvidia,tristate = <TEGRA_PIN_DISABLE>;
32 }; 32 };
33 crt { 33 crt {
34 nvidia,pins = "crtp"; 34 nvidia,pins = "crtp";
35 nvidia,function = "crt"; 35 nvidia,function = "crt";
36 nvidia,pull = <0>; 36 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
37 nvidia,tristate = <1>; 37 nvidia,tristate = <TEGRA_PIN_ENABLE>;
38 }; 38 };
39 dap3 { 39 dap3 {
40 nvidia,pins = "dap3"; 40 nvidia,pins = "dap3";
41 nvidia,function = "dap3"; 41 nvidia,function = "dap3";
42 nvidia,pull = <0>; 42 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
43 nvidia,tristate = <0>; 43 nvidia,tristate = <TEGRA_PIN_DISABLE>;
44 }; 44 };
45 displaya { 45 displaya {
46 nvidia,pins = "ld0", "ld1", "ld2", "ld3", 46 nvidia,pins = "ld0", "ld1", "ld2", "ld3",
@@ -50,155 +50,163 @@
50 "lhs", "lpw0", "lpw2", "lsc0", 50 "lhs", "lpw0", "lpw2", "lsc0",
51 "lsc1", "lsck", "lsda", "lspi", "lvs"; 51 "lsc1", "lsck", "lsda", "lspi", "lvs";
52 nvidia,function = "displaya"; 52 nvidia,function = "displaya";
53 nvidia,tristate = <1>; 53 nvidia,tristate = <TEGRA_PIN_ENABLE>;
54 }; 54 };
55 gpio_dte { 55 gpio_dte {
56 nvidia,pins = "dte"; 56 nvidia,pins = "dte";
57 nvidia,function = "rsvd1"; 57 nvidia,function = "rsvd1";
58 nvidia,pull = <0>; 58 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
59 nvidia,tristate = <0>; 59 nvidia,tristate = <TEGRA_PIN_DISABLE>;
60 }; 60 };
61 gpio_gmi { 61 gpio_gmi {
62 nvidia,pins = "ata", "atc", "atd", "ate", 62 nvidia,pins = "ata", "atc", "atd", "ate",
63 "dap1", "dap2", "dap4", "gpu", "irrx", 63 "dap1", "dap2", "dap4", "gpu", "irrx",
64 "irtx", "spia", "spib", "spic"; 64 "irtx", "spia", "spib", "spic";
65 nvidia,function = "gmi"; 65 nvidia,function = "gmi";
66 nvidia,pull = <0>; 66 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
67 nvidia,tristate = <0>; 67 nvidia,tristate = <TEGRA_PIN_DISABLE>;
68 }; 68 };
69 gpio_pta { 69 gpio_pta {
70 nvidia,pins = "pta"; 70 nvidia,pins = "pta";
71 nvidia,function = "rsvd4"; 71 nvidia,function = "rsvd4";
72 nvidia,pull = <0>; 72 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
73 nvidia,tristate = <0>; 73 nvidia,tristate = <TEGRA_PIN_DISABLE>;
74 }; 74 };
75 gpio_uac { 75 gpio_uac {
76 nvidia,pins = "uac"; 76 nvidia,pins = "uac";
77 nvidia,function = "rsvd2"; 77 nvidia,function = "rsvd2";
78 nvidia,pull = <0>; 78 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
79 nvidia,tristate = <0>; 79 nvidia,tristate = <TEGRA_PIN_DISABLE>;
80 }; 80 };
81 hdint { 81 hdint {
82 nvidia,pins = "hdint"; 82 nvidia,pins = "hdint";
83 nvidia,function = "hdmi"; 83 nvidia,function = "hdmi";
84 nvidia,tristate = <1>; 84 nvidia,tristate = <TEGRA_PIN_ENABLE>;
85 }; 85 };
86 i2c1 { 86 i2c1 {
87 nvidia,pins = "rm"; 87 nvidia,pins = "rm";
88 nvidia,function = "i2c1"; 88 nvidia,function = "i2c1";
89 nvidia,pull = <0>; 89 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
90 nvidia,tristate = <1>; 90 nvidia,tristate = <TEGRA_PIN_ENABLE>;
91 }; 91 };
92 i2c3 { 92 i2c3 {
93 nvidia,pins = "dtf"; 93 nvidia,pins = "dtf";
94 nvidia,function = "i2c3"; 94 nvidia,function = "i2c3";
95 nvidia,pull = <0>; 95 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
96 nvidia,tristate = <1>; 96 nvidia,tristate = <TEGRA_PIN_ENABLE>;
97 }; 97 };
98 i2cddc { 98 i2cddc {
99 nvidia,pins = "ddc"; 99 nvidia,pins = "ddc";
100 nvidia,function = "i2c2"; 100 nvidia,function = "i2c2";
101 nvidia,pull = <2>; 101 nvidia,pull = <TEGRA_PIN_PULL_UP>;
102 nvidia,tristate = <1>; 102 nvidia,tristate = <TEGRA_PIN_ENABLE>;
103 }; 103 };
104 i2cp { 104 i2cp {
105 nvidia,pins = "i2cp"; 105 nvidia,pins = "i2cp";
106 nvidia,function = "i2cp"; 106 nvidia,function = "i2cp";
107 nvidia,pull = <0>; 107 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
108 nvidia,tristate = <0>; 108 nvidia,tristate = <TEGRA_PIN_DISABLE>;
109 }; 109 };
110 irda { 110 irda {
111 nvidia,pins = "uad"; 111 nvidia,pins = "uad";
112 nvidia,function = "irda"; 112 nvidia,function = "irda";
113 nvidia,pull = <0>; 113 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
114 nvidia,tristate = <1>; 114 nvidia,tristate = <TEGRA_PIN_ENABLE>;
115 }; 115 };
116 nand { 116 nand {
117 nvidia,pins = "kbca", "kbcc", "kbcd", 117 nvidia,pins = "kbca", "kbcc", "kbcd",
118 "kbce", "kbcf"; 118 "kbce", "kbcf";
119 nvidia,function = "nand"; 119 nvidia,function = "nand";
120 nvidia,pull = <0>; 120 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
121 nvidia,tristate = <0>; 121 nvidia,tristate = <TEGRA_PIN_DISABLE>;
122 }; 122 };
123 owc { 123 owc {
124 nvidia,pins = "owc"; 124 nvidia,pins = "owc";
125 nvidia,function = "owr"; 125 nvidia,function = "owr";
126 nvidia,pull = <0>; 126 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
127 nvidia,tristate = <1>; 127 nvidia,tristate = <TEGRA_PIN_ENABLE>;
128 }; 128 };
129 pmc { 129 pmc {
130 nvidia,pins = "pmc"; 130 nvidia,pins = "pmc";
131 nvidia,function = "pwr_on"; 131 nvidia,function = "pwr_on";
132 nvidia,tristate = <0>; 132 nvidia,tristate = <TEGRA_PIN_DISABLE>;
133 }; 133 };
134 pwm { 134 pwm {
135 nvidia,pins = "sdb", "sdc", "sdd"; 135 nvidia,pins = "sdb", "sdc", "sdd";
136 nvidia,function = "pwm"; 136 nvidia,function = "pwm";
137 nvidia,tristate = <1>; 137 nvidia,tristate = <TEGRA_PIN_ENABLE>;
138 }; 138 };
139 sdio4 { 139 sdio4 {
140 nvidia,pins = "atb", "gma", "gme"; 140 nvidia,pins = "atb", "gma", "gme";
141 nvidia,function = "sdio4"; 141 nvidia,function = "sdio4";
142 nvidia,pull = <0>; 142 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
143 nvidia,tristate = <1>; 143 nvidia,tristate = <TEGRA_PIN_ENABLE>;
144 }; 144 };
145 spi1 { 145 spi1 {
146 nvidia,pins = "spid", "spie", "spif"; 146 nvidia,pins = "spid", "spie", "spif";
147 nvidia,function = "spi1"; 147 nvidia,function = "spi1";
148 nvidia,pull = <0>; 148 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
149 nvidia,tristate = <1>; 149 nvidia,tristate = <TEGRA_PIN_ENABLE>;
150 }; 150 };
151 spi4 { 151 spi4 {
152 nvidia,pins = "slxa", "slxc", "slxd", "slxk"; 152 nvidia,pins = "slxa", "slxc", "slxd", "slxk";
153 nvidia,function = "spi4"; 153 nvidia,function = "spi4";
154 nvidia,pull = <0>; 154 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
155 nvidia,tristate = <1>; 155 nvidia,tristate = <TEGRA_PIN_ENABLE>;
156 }; 156 };
157 uarta { 157 uarta {
158 nvidia,pins = "sdio1"; 158 nvidia,pins = "sdio1";
159 nvidia,function = "uarta"; 159 nvidia,function = "uarta";
160 nvidia,pull = <0>; 160 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
161 nvidia,tristate = <1>; 161 nvidia,tristate = <TEGRA_PIN_ENABLE>;
162 }; 162 };
163 uartd { 163 uartd {
164 nvidia,pins = "gmc"; 164 nvidia,pins = "gmc";
165 nvidia,function = "uartd"; 165 nvidia,function = "uartd";
166 nvidia,pull = <0>; 166 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
167 nvidia,tristate = <1>; 167 nvidia,tristate = <TEGRA_PIN_ENABLE>;
168 }; 168 };
169 ulpi { 169 ulpi {
170 nvidia,pins = "uaa", "uab", "uda"; 170 nvidia,pins = "uaa", "uab", "uda";
171 nvidia,function = "ulpi"; 171 nvidia,function = "ulpi";
172 nvidia,pull = <0>; 172 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
173 nvidia,tristate = <0>; 173 nvidia,tristate = <TEGRA_PIN_DISABLE>;
174 }; 174 };
175 ulpi_refclk { 175 ulpi_refclk {
176 nvidia,pins = "cdev2"; 176 nvidia,pins = "cdev2";
177 nvidia,function = "pllp_out4"; 177 nvidia,function = "pllp_out4";
178 nvidia,pull = <0>; 178 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
179 nvidia,tristate = <0>; 179 nvidia,tristate = <TEGRA_PIN_DISABLE>;
180 }; 180 };
181 usb_gpio { 181 usb_gpio {
182 nvidia,pins = "spig", "spih"; 182 nvidia,pins = "spig", "spih";
183 nvidia,function = "spi2_alt"; 183 nvidia,function = "spi2_alt";
184 nvidia,pull = <0>; 184 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
185 nvidia,tristate = <0>; 185 nvidia,tristate = <TEGRA_PIN_DISABLE>;
186 }; 186 };
187 vi { 187 vi {
188 nvidia,pins = "dta", "dtb", "dtc", "dtd"; 188 nvidia,pins = "dta", "dtb", "dtc", "dtd";
189 nvidia,function = "vi"; 189 nvidia,function = "vi";
190 nvidia,pull = <0>; 190 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
191 nvidia,tristate = <1>; 191 nvidia,tristate = <TEGRA_PIN_ENABLE>;
192 }; 192 };
193 vi_sc { 193 vi_sc {
194 nvidia,pins = "csus"; 194 nvidia,pins = "csus";
195 nvidia,function = "vi_sensor_clk"; 195 nvidia,function = "vi_sensor_clk";
196 nvidia,pull = <0>; 196 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
197 nvidia,tristate = <1>; 197 nvidia,tristate = <TEGRA_PIN_ENABLE>;
198 }; 198 };
199 }; 199 };
200 }; 200 };
201 201
202 ac97: ac97@70002000 {
203 status = "okay";
204 nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
205 GPIO_ACTIVE_HIGH>;
206 nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
207 GPIO_ACTIVE_HIGH>;
208 };
209
202 i2c@7000c000 { 210 i2c@7000c000 {
203 clock-frequency = <400000>; 211 clock-frequency = <400000>;
204 }; 212 };
@@ -225,15 +233,15 @@
225 #gpio-cells = <2>; 233 #gpio-cells = <2>;
226 gpio-controller; 234 gpio-controller;
227 235
228 sys-supply = <&vdd_5v0_reg>; 236 sys-supply = <&vdd_3v3_reg>;
229 vin-sm0-supply = <&sys_reg>; 237 vin-sm0-supply = <&sys_reg>;
230 vin-sm1-supply = <&sys_reg>; 238 vin-sm1-supply = <&sys_reg>;
231 vin-sm2-supply = <&sys_reg>; 239 vin-sm2-supply = <&sys_reg>;
232 vinldo01-supply = <&sm2_reg>; 240 vinldo01-supply = <&sm2_reg>;
233 vinldo23-supply = <&sm2_reg>; 241 vinldo23-supply = <&vdd_3v3_reg>;
234 vinldo4-supply = <&sm2_reg>; 242 vinldo4-supply = <&vdd_3v3_reg>;
235 vinldo678-supply = <&sm2_reg>; 243 vinldo678-supply = <&vdd_3v3_reg>;
236 vinldo9-supply = <&sm2_reg>; 244 vinldo9-supply = <&vdd_3v3_reg>;
237 245
238 regulators { 246 regulators {
239 #address-cells = <1>; 247 #address-cells = <1>;
@@ -250,8 +258,8 @@
250 reg = <1>; 258 reg = <1>;
251 regulator-compatible = "sm0"; 259 regulator-compatible = "sm0";
252 regulator-name = "vdd_sm0,vdd_core"; 260 regulator-name = "vdd_sm0,vdd_core";
253 regulator-min-microvolt = <1275000>; 261 regulator-min-microvolt = <1200000>;
254 regulator-max-microvolt = <1275000>; 262 regulator-max-microvolt = <1200000>;
255 regulator-always-on; 263 regulator-always-on;
256 }; 264 };
257 265
@@ -259,8 +267,8 @@
259 reg = <2>; 267 reg = <2>;
260 regulator-compatible = "sm1"; 268 regulator-compatible = "sm1";
261 regulator-name = "vdd_sm1,vdd_cpu"; 269 regulator-name = "vdd_sm1,vdd_cpu";
262 regulator-min-microvolt = <1100000>; 270 regulator-min-microvolt = <1000000>;
263 regulator-max-microvolt = <1100000>; 271 regulator-max-microvolt = <1000000>;
264 regulator-always-on; 272 regulator-always-on;
265 }; 273 };
266 274
@@ -316,8 +324,8 @@
316 reg = <10>; 324 reg = <10>;
317 regulator-compatible = "ldo6"; 325 regulator-compatible = "ldo6";
318 regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam"; 326 regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
319 regulator-min-microvolt = <1800000>; 327 regulator-min-microvolt = <2850000>;
320 regulator-max-microvolt = <1800000>; 328 regulator-max-microvolt = <2850000>;
321 }; 329 };
322 330
323 hdmi_vdd_reg: regulator@11 { 331 hdmi_vdd_reg: regulator@11 {
@@ -362,7 +370,7 @@
362 }; 370 };
363 }; 371 };
364 372
365 pmc { 373 pmc@7000e400 {
366 nvidia,suspend-mode = <1>; 374 nvidia,suspend-mode = <1>;
367 nvidia,cpu-pwr-good-time = <5000>; 375 nvidia,cpu-pwr-good-time = <5000>;
368 nvidia,cpu-pwr-off-time = <5000>; 376 nvidia,cpu-pwr-off-time = <5000>;
@@ -442,14 +450,6 @@
442 }; 450 };
443 }; 451 };
444 452
445 ac97: ac97 {
446 status = "okay";
447 nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
448 GPIO_ACTIVE_HIGH>;
449 nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
450 GPIO_ACTIVE_HIGH>;
451 };
452
453 usb@c5004000 { 453 usb@c5004000 {
454 status = "okay"; 454 status = "okay";
455 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 455 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
@@ -471,7 +471,7 @@
471 #address-cells = <1>; 471 #address-cells = <1>;
472 #size-cells = <0>; 472 #size-cells = <0>;
473 473
474 clk32k_in: clock { 474 clk32k_in: clock@0 {
475 compatible = "fixed-clock"; 475 compatible = "fixed-clock";
476 reg=<0>; 476 reg=<0>;
477 #clock-cells = <0>; 477 #clock-cells = <0>;
@@ -479,37 +479,17 @@
479 }; 479 };
480 }; 480 };
481 481
482 sound {
483 compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
484 "nvidia,tegra-audio-wm9712";
485 nvidia,model = "Colibri T20 AC97 Audio";
486
487 nvidia,audio-routing =
488 "Headphone", "HPOUTL",
489 "Headphone", "HPOUTR",
490 "LineIn", "LINEINL",
491 "LineIn", "LINEINR",
492 "Mic", "MIC1";
493
494 nvidia,ac97-controller = <&ac97>;
495
496 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
497 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
498 <&tegra_car TEGRA20_CLK_CDEV1>;
499 clock-names = "pll_a", "pll_a_out0", "mclk";
500 };
501
502 regulators { 482 regulators {
503 compatible = "simple-bus"; 483 compatible = "simple-bus";
504 #address-cells = <1>; 484 #address-cells = <1>;
505 #size-cells = <0>; 485 #size-cells = <0>;
506 486
507 vdd_5v0_reg: regulator@100 { 487 vdd_3v3_reg: regulator@100 {
508 compatible = "regulator-fixed"; 488 compatible = "regulator-fixed";
509 reg = <100>; 489 reg = <100>;
510 regulator-name = "vdd_5v0"; 490 regulator-name = "vdd_3v3";
511 regulator-min-microvolt = <5000000>; 491 regulator-min-microvolt = <3300000>;
512 regulator-max-microvolt = <5000000>; 492 regulator-max-microvolt = <3300000>;
513 regulator-always-on; 493 regulator-always-on;
514 }; 494 };
515 495
@@ -525,4 +505,24 @@
525 gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>; 505 gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
526 }; 506 };
527 }; 507 };
508
509 sound {
510 compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
511 "nvidia,tegra-audio-wm9712";
512 nvidia,model = "Colibri T20 AC97 Audio";
513
514 nvidia,audio-routing =
515 "Headphone", "HPOUTL",
516 "Headphone", "HPOUTR",
517 "LineIn", "LINEINL",
518 "LineIn", "LINEINR",
519 "Mic", "MIC1";
520
521 nvidia,ac97-controller = <&ac97>;
522
523 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
524 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
525 <&tegra_car TEGRA20_CLK_CDEV1>;
526 clock-names = "pll_a", "pll_a_out0", "mclk";
527 };
528}; 528};
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index e156ab30e763..b02653da8bd7 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -1,5 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3#include <dt-bindings/input/input.h>
3#include "tegra20.dtsi" 4#include "tegra20.dtsi"
4 5
5/ { 6/ {
@@ -10,8 +11,8 @@
10 reg = <0x00000000 0x40000000>; 11 reg = <0x00000000 0x40000000>;
11 }; 12 };
12 13
13 host1x { 14 host1x@50000000 {
14 hdmi { 15 hdmi@54280000 {
15 status = "okay"; 16 status = "okay";
16 17
17 vdd-supply = <&hdmi_vdd_reg>; 18 vdd-supply = <&hdmi_vdd_reg>;
@@ -23,7 +24,7 @@
23 }; 24 };
24 }; 25 };
25 26
26 pinmux { 27 pinmux@70000014 {
27 pinctrl-names = "default"; 28 pinctrl-names = "default";
28 pinctrl-0 = <&state_default>; 29 pinctrl-0 = <&state_default>;
29 30
@@ -184,50 +185,50 @@
184 "gmb", "gmc", "gmd", "gme", "gpu7", 185 "gmb", "gmc", "gmd", "gme", "gpu7",
185 "gpv", "i2cp", "pta", "rm", "slxa", 186 "gpv", "i2cp", "pta", "rm", "slxa",
186 "slxk", "spia", "spib", "uac"; 187 "slxk", "spia", "spib", "uac";
187 nvidia,pull = <0>; 188 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
188 nvidia,tristate = <0>; 189 nvidia,tristate = <TEGRA_PIN_DISABLE>;
189 }; 190 };
190 conf_ck32 { 191 conf_ck32 {
191 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", 192 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
192 "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; 193 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
193 nvidia,pull = <0>; 194 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
194 }; 195 };
195 conf_csus { 196 conf_csus {
196 nvidia,pins = "csus", "spid", "spif"; 197 nvidia,pins = "csus", "spid", "spif";
197 nvidia,pull = <1>; 198 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
198 nvidia,tristate = <1>; 199 nvidia,tristate = <TEGRA_PIN_ENABLE>;
199 }; 200 };
200 conf_crtp { 201 conf_crtp {
201 nvidia,pins = "crtp", "dap2", "dap3", "dap4", 202 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
202 "dtc", "dte", "dtf", "gpu", "sdio1", 203 "dtc", "dte", "dtf", "gpu", "sdio1",
203 "slxc", "slxd", "spdi", "spdo", "spig", 204 "slxc", "slxd", "spdi", "spdo", "spig",
204 "uda"; 205 "uda";
205 nvidia,pull = <0>; 206 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
206 nvidia,tristate = <1>; 207 nvidia,tristate = <TEGRA_PIN_ENABLE>;
207 }; 208 };
208 conf_ddc { 209 conf_ddc {
209 nvidia,pins = "ddc", "dta", "dtd", "kbca", 210 nvidia,pins = "ddc", "dta", "dtd", "kbca",
210 "kbcb", "kbcc", "kbcd", "kbce", "kbcf", 211 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
211 "sdc"; 212 "sdc";
212 nvidia,pull = <2>; 213 nvidia,pull = <TEGRA_PIN_PULL_UP>;
213 nvidia,tristate = <0>; 214 nvidia,tristate = <TEGRA_PIN_DISABLE>;
214 }; 215 };
215 conf_hdint { 216 conf_hdint {
216 nvidia,pins = "hdint", "lcsn", "ldc", "lm1", 217 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
217 "lpw1", "lsc1", "lsck", "lsda", "lsdi", 218 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
218 "lvp0", "owc", "sdb"; 219 "lvp0", "owc", "sdb";
219 nvidia,tristate = <1>; 220 nvidia,tristate = <TEGRA_PIN_ENABLE>;
220 }; 221 };
221 conf_irrx { 222 conf_irrx {
222 nvidia,pins = "irrx", "irtx", "sdd", "spic", 223 nvidia,pins = "irrx", "irtx", "sdd", "spic",
223 "spie", "spih", "uaa", "uab", "uad", 224 "spie", "spih", "uaa", "uab", "uad",
224 "uca", "ucb"; 225 "uca", "ucb";
225 nvidia,pull = <2>; 226 nvidia,pull = <TEGRA_PIN_PULL_UP>;
226 nvidia,tristate = <1>; 227 nvidia,tristate = <TEGRA_PIN_ENABLE>;
227 }; 228 };
228 conf_lc { 229 conf_lc {
229 nvidia,pins = "lc", "ls"; 230 nvidia,pins = "lc", "ls";
230 nvidia,pull = <2>; 231 nvidia,pull = <TEGRA_PIN_PULL_UP>;
231 }; 232 };
232 conf_ld0 { 233 conf_ld0 {
233 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", 234 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
@@ -237,12 +238,12 @@
237 "lhp1", "lhp2", "lhs", "lm0", "lpp", 238 "lhp1", "lhp2", "lhs", "lm0", "lpp",
238 "lpw0", "lpw2", "lsc0", "lspi", "lvp1", 239 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
239 "lvs", "pmc"; 240 "lvs", "pmc";
240 nvidia,tristate = <0>; 241 nvidia,tristate = <TEGRA_PIN_DISABLE>;
241 }; 242 };
242 conf_ld17_0 { 243 conf_ld17_0 {
243 nvidia,pins = "ld17_0", "ld19_18", "ld21_20", 244 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
244 "ld23_22"; 245 "ld23_22";
245 nvidia,pull = <1>; 246 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
246 }; 247 };
247 }; 248 };
248 }; 249 };
@@ -415,7 +416,124 @@
415 }; 416 };
416 }; 417 };
417 418
418 pmc { 419 kbc@7000e200 {
420 status = "okay";
421 nvidia,debounce-delay-ms = <2>;
422 nvidia,repeat-delay-ms = <160>;
423 nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
424 nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
425 linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W)
426 MATRIX_KEY(0x00, 0x03, KEY_S)
427 MATRIX_KEY(0x00, 0x04, KEY_A)
428 MATRIX_KEY(0x00, 0x05, KEY_Z)
429 MATRIX_KEY(0x00, 0x07, KEY_FN)
430 MATRIX_KEY(0x01, 0x07, KEY_MENU)
431 MATRIX_KEY(0x02, 0x06, KEY_LEFTALT)
432 MATRIX_KEY(0x02, 0x07, KEY_RIGHTALT)
433 MATRIX_KEY(0x03, 0x00, KEY_5)
434 MATRIX_KEY(0x03, 0x01, KEY_4)
435 MATRIX_KEY(0x03, 0x02, KEY_R)
436 MATRIX_KEY(0x03, 0x03, KEY_E)
437 MATRIX_KEY(0x03, 0x04, KEY_F)
438 MATRIX_KEY(0x03, 0x05, KEY_D)
439 MATRIX_KEY(0x03, 0x06, KEY_X)
440 MATRIX_KEY(0x04, 0x00, KEY_7)
441 MATRIX_KEY(0x04, 0x01, KEY_6)
442 MATRIX_KEY(0x04, 0x02, KEY_T)
443 MATRIX_KEY(0x04, 0x03, KEY_H)
444 MATRIX_KEY(0x04, 0x04, KEY_G)
445 MATRIX_KEY(0x04, 0x05, KEY_V)
446 MATRIX_KEY(0x04, 0x06, KEY_C)
447 MATRIX_KEY(0x04, 0x07, KEY_SPACE)
448 MATRIX_KEY(0x05, 0x00, KEY_9)
449 MATRIX_KEY(0x05, 0x01, KEY_8)
450 MATRIX_KEY(0x05, 0x02, KEY_U)
451 MATRIX_KEY(0x05, 0x03, KEY_Y)
452 MATRIX_KEY(0x05, 0x04, KEY_J)
453 MATRIX_KEY(0x05, 0x05, KEY_N)
454 MATRIX_KEY(0x05, 0x06, KEY_B)
455 MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH)
456 MATRIX_KEY(0x06, 0x00, KEY_MINUS)
457 MATRIX_KEY(0x06, 0x01, KEY_0)
458 MATRIX_KEY(0x06, 0x02, KEY_O)
459 MATRIX_KEY(0x06, 0x03, KEY_I)
460 MATRIX_KEY(0x06, 0x04, KEY_L)
461 MATRIX_KEY(0x06, 0x05, KEY_K)
462 MATRIX_KEY(0x06, 0x06, KEY_COMMA)
463 MATRIX_KEY(0x06, 0x07, KEY_M)
464 MATRIX_KEY(0x07, 0x01, KEY_EQUAL)
465 MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE)
466 MATRIX_KEY(0x07, 0x03, KEY_ENTER)
467 MATRIX_KEY(0x07, 0x07, KEY_MENU)
468 MATRIX_KEY(0x08, 0x04, KEY_LEFTSHIFT)
469 MATRIX_KEY(0x08, 0x05, KEY_RIGHTSHIFT)
470 MATRIX_KEY(0x09, 0x05, KEY_LEFTCTRL)
471 MATRIX_KEY(0x09, 0x07, KEY_RIGHTCTRL)
472 MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE)
473 MATRIX_KEY(0x0B, 0x01, KEY_P)
474 MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE)
475 MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON)
476 MATRIX_KEY(0x0B, 0x04, KEY_SLASH)
477 MATRIX_KEY(0x0B, 0x05, KEY_DOT)
478 MATRIX_KEY(0x0C, 0x00, KEY_F10)
479 MATRIX_KEY(0x0C, 0x01, KEY_F9)
480 MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE)
481 MATRIX_KEY(0x0C, 0x03, KEY_3)
482 MATRIX_KEY(0x0C, 0x04, KEY_2)
483 MATRIX_KEY(0x0C, 0x05, KEY_UP)
484 MATRIX_KEY(0x0C, 0x06, KEY_PRINT)
485 MATRIX_KEY(0x0C, 0x07, KEY_PAUSE)
486 MATRIX_KEY(0x0D, 0x00, KEY_INSERT)
487 MATRIX_KEY(0x0D, 0x01, KEY_DELETE)
488 MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP )
489 MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN)
490 MATRIX_KEY(0x0D, 0x05, KEY_RIGHT)
491 MATRIX_KEY(0x0D, 0x06, KEY_DOWN)
492 MATRIX_KEY(0x0D, 0x07, KEY_LEFT)
493 MATRIX_KEY(0x0E, 0x00, KEY_F11)
494 MATRIX_KEY(0x0E, 0x01, KEY_F12)
495 MATRIX_KEY(0x0E, 0x02, KEY_F8)
496 MATRIX_KEY(0x0E, 0x03, KEY_Q)
497 MATRIX_KEY(0x0E, 0x04, KEY_F4)
498 MATRIX_KEY(0x0E, 0x05, KEY_F3)
499 MATRIX_KEY(0x0E, 0x06, KEY_1)
500 MATRIX_KEY(0x0E, 0x07, KEY_F7)
501 MATRIX_KEY(0x0F, 0x00, KEY_ESC)
502 MATRIX_KEY(0x0F, 0x01, KEY_GRAVE)
503 MATRIX_KEY(0x0F, 0x02, KEY_F5)
504 MATRIX_KEY(0x0F, 0x03, KEY_TAB)
505 MATRIX_KEY(0x0F, 0x04, KEY_F1)
506 MATRIX_KEY(0x0F, 0x05, KEY_F2)
507 MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK)
508 MATRIX_KEY(0x0F, 0x07, KEY_F6)
509 MATRIX_KEY(0x14, 0x00, KEY_KP7)
510 MATRIX_KEY(0x15, 0x00, KEY_KP9)
511 MATRIX_KEY(0x15, 0x01, KEY_KP8)
512 MATRIX_KEY(0x15, 0x02, KEY_KP4)
513 MATRIX_KEY(0x15, 0x04, KEY_KP1)
514 MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
515 MATRIX_KEY(0x16, 0x02, KEY_KP6)
516 MATRIX_KEY(0x16, 0x03, KEY_KP5)
517 MATRIX_KEY(0x16, 0x04, KEY_KP3)
518 MATRIX_KEY(0x16, 0x05, KEY_KP2)
519 MATRIX_KEY(0x16, 0x07, KEY_KP0)
520 MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK)
521 MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS)
522 MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS)
523 MATRIX_KEY(0x1B, 0x05, KEY_KPDOT)
524 MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP)
525 MATRIX_KEY(0x1D, 0x03, KEY_HOME)
526 MATRIX_KEY(0x1D, 0x04, KEY_END)
527 MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSUP)
528 MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN)
529 MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSDOWN)
530 MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK)
531 MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK)
532 MATRIX_KEY(0x1E, 0x02, KEY_MUTE)
533 MATRIX_KEY(0x1F, 0x04, KEY_QUESTION)>;
534 };
535
536 pmc@7000e400 {
419 nvidia,invert-interrupt; 537 nvidia,invert-interrupt;
420 nvidia,suspend-mode = <1>; 538 nvidia,suspend-mode = <1>;
421 nvidia,cpu-pwr-good-time = <5000>; 539 nvidia,cpu-pwr-good-time = <5000>;
@@ -425,7 +543,7 @@
425 nvidia,sys-clock-req-active-high; 543 nvidia,sys-clock-req-active-high;
426 }; 544 };
427 545
428 pcie-controller { 546 pcie-controller@80003000 {
429 pex-clk-supply = <&pci_clk_reg>; 547 pex-clk-supply = <&pci_clk_reg>;
430 vdd-supply = <&pci_vdd_reg>; 548 vdd-supply = <&pci_vdd_reg>;
431 status = "okay"; 549 status = "okay";
@@ -488,7 +606,7 @@
488 #address-cells = <1>; 606 #address-cells = <1>;
489 #size-cells = <0>; 607 #size-cells = <0>;
490 608
491 clk32k_in: clock { 609 clk32k_in: clock@0 {
492 compatible = "fixed-clock"; 610 compatible = "fixed-clock";
493 reg=<0>; 611 reg=<0>;
494 #clock-cells = <0>; 612 #clock-cells = <0>;
@@ -502,128 +620,11 @@
502 power { 620 power {
503 label = "Power"; 621 label = "Power";
504 gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; 622 gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
505 linux,code = <116>; /* KEY_POWER */ 623 linux,code = <KEY_POWER>;
506 gpio-key,wakeup; 624 gpio-key,wakeup;
507 }; 625 };
508 }; 626 };
509 627
510 kbc {
511 status = "okay";
512 nvidia,debounce-delay-ms = <2>;
513 nvidia,repeat-delay-ms = <160>;
514 nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
515 nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
516 linux,keymap = <0x00020011 /* KEY_W */
517 0x0003001F /* KEY_S */
518 0x0004001E /* KEY_A */
519 0x0005002C /* KEY_Z */
520 0x000701D0 /* KEY_FN */
521 0x0107008B /* KEY_MENU */
522 0x02060038 /* KEY_LEFTALT */
523 0x02070064 /* KEY_RIGHTALT */
524 0x03000006 /* KEY_5 */
525 0x03010005 /* KEY_4 */
526 0x03020013 /* KEY_R */
527 0x03030012 /* KEY_E */
528 0x03040021 /* KEY_F */
529 0x03050020 /* KEY_D */
530 0x0306002D /* KEY_X */
531 0x04000008 /* KEY_7 */
532 0x04010007 /* KEY_6 */
533 0x04020014 /* KEY_T */
534 0x04030023 /* KEY_H */
535 0x04040022 /* KEY_G */
536 0x0405002F /* KEY_V */
537 0x0406002E /* KEY_C */
538 0x04070039 /* KEY_SPACE */
539 0x0500000A /* KEY_9 */
540 0x05010009 /* KEY_8 */
541 0x05020016 /* KEY_U */
542 0x05030015 /* KEY_Y */
543 0x05040024 /* KEY_J */
544 0x05050031 /* KEY_N */
545 0x05060030 /* KEY_B */
546 0x0507002B /* KEY_BACKSLASH */
547 0x0600000C /* KEY_MINUS */
548 0x0601000B /* KEY_0 */
549 0x06020018 /* KEY_O */
550 0x06030017 /* KEY_I */
551 0x06040026 /* KEY_L */
552 0x06050025 /* KEY_K */
553 0x06060033 /* KEY_COMMA */
554 0x06070032 /* KEY_M */
555 0x0701000D /* KEY_EQUAL */
556 0x0702001B /* KEY_RIGHTBRACE */
557 0x0703001C /* KEY_ENTER */
558 0x0707008B /* KEY_MENU */
559 0x0804002A /* KEY_LEFTSHIFT */
560 0x08050036 /* KEY_RIGHTSHIFT */
561 0x0905001D /* KEY_LEFTCTRL */
562 0x09070061 /* KEY_RIGHTCTRL */
563 0x0B00001A /* KEY_LEFTBRACE */
564 0x0B010019 /* KEY_P */
565 0x0B020028 /* KEY_APOSTROPHE */
566 0x0B030027 /* KEY_SEMICOLON */
567 0x0B040035 /* KEY_SLASH */
568 0x0B050034 /* KEY_DOT */
569 0x0C000044 /* KEY_F10 */
570 0x0C010043 /* KEY_F9 */
571 0x0C02000E /* KEY_BACKSPACE */
572 0x0C030004 /* KEY_3 */
573 0x0C040003 /* KEY_2 */
574 0x0C050067 /* KEY_UP */
575 0x0C0600D2 /* KEY_PRINT */
576 0x0C070077 /* KEY_PAUSE */
577 0x0D00006E /* KEY_INSERT */
578 0x0D01006F /* KEY_DELETE */
579 0x0D030068 /* KEY_PAGEUP */
580 0x0D04006D /* KEY_PAGEDOWN */
581 0x0D05006A /* KEY_RIGHT */
582 0x0D06006C /* KEY_DOWN */
583 0x0D070069 /* KEY_LEFT */
584 0x0E000057 /* KEY_F11 */
585 0x0E010058 /* KEY_F12 */
586 0x0E020042 /* KEY_F8 */
587 0x0E030010 /* KEY_Q */
588 0x0E04003E /* KEY_F4 */
589 0x0E05003D /* KEY_F3 */
590 0x0E060002 /* KEY_1 */
591 0x0E070041 /* KEY_F7 */
592 0x0F000001 /* KEY_ESC */
593 0x0F010029 /* KEY_GRAVE */
594 0x0F02003F /* KEY_F5 */
595 0x0F03000F /* KEY_TAB */
596 0x0F04003B /* KEY_F1 */
597 0x0F05003C /* KEY_F2 */
598 0x0F06003A /* KEY_CAPSLOCK */
599 0x0F070040 /* KEY_F6 */
600 0x14000047 /* KEY_KP7 */
601 0x15000049 /* KEY_KP9 */
602 0x15010048 /* KEY_KP8 */
603 0x1502004B /* KEY_KP4 */
604 0x1504004F /* KEY_KP1 */
605 0x1601004E /* KEY_KPSLASH */
606 0x1602004D /* KEY_KP6 */
607 0x1603004C /* KEY_KP5 */
608 0x16040051 /* KEY_KP3 */
609 0x16050050 /* KEY_KP2 */
610 0x16070052 /* KEY_KP0 */
611 0x1B010037 /* KEY_KPASTERISK */
612 0x1B03004A /* KEY_KPMINUS */
613 0x1B04004E /* KEY_KPPLUS */
614 0x1B050053 /* KEY_KPDOT */
615 0x1C050073 /* KEY_VOLUMEUP */
616 0x1D030066 /* KEY_HOME */
617 0x1D04006B /* KEY_END */
618 0x1D0500E1 /* KEY_BRIGHTNESSUP */
619 0x1D060072 /* KEY_VOLUMEDOWN */
620 0x1D0700E0 /* KEY_BRIGHTNESSDOWN */
621 0x1E000045 /* KEY_NUMLOCK */
622 0x1E010046 /* KEY_SCROLLLOCK */
623 0x1E020071 /* KEY_MUTE */
624 0x1F0400D6>; /* KEY_QUESTION */
625 };
626
627 regulators { 628 regulators {
628 compatible = "simple-bus"; 629 compatible = "simple-bus";
629 #address-cells = <1>; 630 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts
index f2222bd74eab..8cfb83f42e1f 100644
--- a/arch/arm/boot/dts/tegra20-iris-512.dts
+++ b/arch/arm/boot/dts/tegra20-iris-512.dts
@@ -6,61 +6,61 @@
6 model = "Toradex Colibri T20 512MB on Iris"; 6 model = "Toradex Colibri T20 512MB on Iris";
7 compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20"; 7 compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20";
8 8
9 host1x { 9 host1x@50000000 {
10 hdmi { 10 hdmi@54280000 {
11 status = "okay"; 11 status = "okay";
12 }; 12 };
13 }; 13 };
14 14
15 pinmux { 15 pinmux@70000014 {
16 state_default: pinmux { 16 state_default: pinmux {
17 hdint { 17 hdint {
18 nvidia,tristate = <0>; 18 nvidia,tristate = <TEGRA_PIN_DISABLE>;
19 }; 19 };
20 20
21 i2cddc { 21 i2cddc {
22 nvidia,tristate = <0>; 22 nvidia,tristate = <TEGRA_PIN_DISABLE>;
23 }; 23 };
24 24
25 sdio4 { 25 sdio4 {
26 nvidia,tristate = <0>; 26 nvidia,tristate = <TEGRA_PIN_DISABLE>;
27 }; 27 };
28 28
29 uarta { 29 uarta {
30 nvidia,tristate = <0>; 30 nvidia,tristate = <TEGRA_PIN_DISABLE>;
31 }; 31 };
32 32
33 uartd { 33 uartd {
34 nvidia,tristate = <0>; 34 nvidia,tristate = <TEGRA_PIN_DISABLE>;
35 }; 35 };
36 }; 36 };
37 }; 37 };
38 38
39 usb@c5000000 { 39 serial@70006000 {
40 status = "okay"; 40 status = "okay";
41 }; 41 };
42 42
43 usb-phy@c5000000 { 43 serial@70006300 {
44 status = "okay"; 44 status = "okay";
45 }; 45 };
46 46
47 usb@c5008000 { 47 i2c_ddc: i2c@7000c400 {
48 status = "okay"; 48 status = "okay";
49 }; 49 };
50 50
51 usb-phy@c5008000 { 51 usb@c5000000 {
52 status = "okay"; 52 status = "okay";
53 }; 53 };
54 54
55 serial@70006000 { 55 usb-phy@c5000000 {
56 status = "okay"; 56 status = "okay";
57 }; 57 };
58 58
59 serial@70006300 { 59 usb@c5008000 {
60 status = "okay"; 60 status = "okay";
61 }; 61 };
62 62
63 i2c_ddc: i2c@7000c400 { 63 usb-phy@c5008000 {
64 status = "okay"; 64 status = "okay";
65 }; 65 };
66 66
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
index 7580578903cf..6d3a4cbc36cc 100644
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dts
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
@@ -6,7 +6,7 @@
6 model = "Avionic Design Medcom-Wide board"; 6 model = "Avionic Design Medcom-Wide board";
7 compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20"; 7 compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20";
8 8
9 pwm { 9 pwm@7000a000 {
10 status = "okay"; 10 status = "okay";
11 }; 11 };
12 12
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index e57fb3aefc2a..02923fb96fed 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -1,5 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3#include <dt-bindings/input/input.h>
3#include "tegra20.dtsi" 4#include "tegra20.dtsi"
4 5
5/ { 6/ {
@@ -10,8 +11,8 @@
10 reg = <0x00000000 0x20000000>; 11 reg = <0x00000000 0x20000000>;
11 }; 12 };
12 13
13 host1x { 14 host1x@50000000 {
14 hdmi { 15 hdmi@54280000 {
15 status = "okay"; 16 status = "okay";
16 17
17 vdd-supply = <&hdmi_vdd_reg>; 18 vdd-supply = <&hdmi_vdd_reg>;
@@ -23,7 +24,7 @@
23 }; 24 };
24 }; 25 };
25 26
26 pinmux { 27 pinmux@70000014 {
27 pinctrl-names = "default"; 28 pinctrl-names = "default";
28 pinctrl-0 = <&state_default>; 29 pinctrl-0 = <&state_default>;
29 30
@@ -177,39 +178,39 @@
177 "gpu", "gpu7", "gpv", "i2cp", "pta", 178 "gpu", "gpu7", "gpv", "i2cp", "pta",
178 "rm", "sdio1", "slxk", "spdo", "uac", 179 "rm", "sdio1", "slxk", "spdo", "uac",
179 "uda"; 180 "uda";
180 nvidia,pull = <0>; 181 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
181 nvidia,tristate = <0>; 182 nvidia,tristate = <TEGRA_PIN_DISABLE>;
182 }; 183 };
183 conf_ck32 { 184 conf_ck32 {
184 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", 185 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
185 "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; 186 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
186 nvidia,pull = <0>; 187 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
187 }; 188 };
188 conf_crtp { 189 conf_crtp {
189 nvidia,pins = "crtp", "dap3", "dap4", "dtb", 190 nvidia,pins = "crtp", "dap3", "dap4", "dtb",
190 "dtc", "dte", "slxa", "slxc", "slxd", 191 "dtc", "dte", "slxa", "slxc", "slxd",
191 "spdi"; 192 "spdi";
192 nvidia,pull = <0>; 193 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
193 nvidia,tristate = <1>; 194 nvidia,tristate = <TEGRA_PIN_ENABLE>;
194 }; 195 };
195 conf_csus { 196 conf_csus {
196 nvidia,pins = "csus", "spia", "spib", "spid", 197 nvidia,pins = "csus", "spia", "spib", "spid",
197 "spif"; 198 "spif";
198 nvidia,pull = <1>; 199 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
199 nvidia,tristate = <1>; 200 nvidia,tristate = <TEGRA_PIN_ENABLE>;
200 }; 201 };
201 conf_ddc { 202 conf_ddc {
202 nvidia,pins = "ddc", "irrx", "irtx", "kbca", 203 nvidia,pins = "ddc", "irrx", "irtx", "kbca",
203 "kbcb", "kbcc", "kbcd", "kbce", "kbcf", 204 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
204 "spic", "spig", "uaa", "uab"; 205 "spic", "spig", "uaa", "uab";
205 nvidia,pull = <2>; 206 nvidia,pull = <TEGRA_PIN_PULL_UP>;
206 nvidia,tristate = <0>; 207 nvidia,tristate = <TEGRA_PIN_DISABLE>;
207 }; 208 };
208 conf_dta { 209 conf_dta {
209 nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd", 210 nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
210 "spie", "spih", "uad", "uca", "ucb"; 211 "spie", "spih", "uad", "uca", "ucb";
211 nvidia,pull = <2>; 212 nvidia,pull = <TEGRA_PIN_PULL_UP>;
212 nvidia,tristate = <1>; 213 nvidia,tristate = <TEGRA_PIN_ENABLE>;
213 }; 214 };
214 conf_hdint { 215 conf_hdint {
215 nvidia,pins = "hdint", "ld0", "ld1", "ld2", 216 nvidia,pins = "hdint", "ld0", "ld1", "ld2",
@@ -218,23 +219,23 @@
218 "ld13", "ld14", "ld15", "ld16", "ld17", 219 "ld13", "ld14", "ld15", "ld16", "ld17",
219 "ldc", "ldi", "lhs", "lsc0", "lspi", 220 "ldc", "ldi", "lhs", "lsc0", "lspi",
220 "lvs", "pmc"; 221 "lvs", "pmc";
221 nvidia,tristate = <0>; 222 nvidia,tristate = <TEGRA_PIN_DISABLE>;
222 }; 223 };
223 conf_lc { 224 conf_lc {
224 nvidia,pins = "lc", "ls"; 225 nvidia,pins = "lc", "ls";
225 nvidia,pull = <2>; 226 nvidia,pull = <TEGRA_PIN_PULL_UP>;
226 }; 227 };
227 conf_lcsn { 228 conf_lcsn {
228 nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2", 229 nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
229 "lm0", "lm1", "lpp", "lpw0", "lpw1", 230 "lm0", "lm1", "lpp", "lpw0", "lpw1",
230 "lpw2", "lsc1", "lsck", "lsda", "lsdi", 231 "lpw2", "lsc1", "lsck", "lsda", "lsdi",
231 "lvp0", "lvp1", "sdb"; 232 "lvp0", "lvp1", "sdb";
232 nvidia,tristate = <1>; 233 nvidia,tristate = <TEGRA_PIN_ENABLE>;
233 }; 234 };
234 conf_ld17_0 { 235 conf_ld17_0 {
235 nvidia,pins = "ld17_0", "ld19_18", "ld21_20", 236 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
236 "ld23_22"; 237 "ld23_22";
237 nvidia,pull = <1>; 238 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
238 }; 239 };
239 }; 240 };
240 }; 241 };
@@ -268,7 +269,7 @@
268 clock-frequency = <100000>; 269 clock-frequency = <100000>;
269 }; 270 };
270 271
271 nvec { 272 nvec@7000c500 {
272 compatible = "nvidia,nvec"; 273 compatible = "nvidia,nvec";
273 reg = <0x7000c500 0x100>; 274 reg = <0x7000c500 0x100>;
274 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 275 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
@@ -417,7 +418,7 @@
417 }; 418 };
418 }; 419 };
419 420
420 pmc { 421 pmc@7000e400 {
421 nvidia,invert-interrupt; 422 nvidia,invert-interrupt;
422 nvidia,suspend-mode = <1>; 423 nvidia,suspend-mode = <1>;
423 nvidia,cpu-pwr-good-time = <2000>; 424 nvidia,cpu-pwr-good-time = <2000>;
@@ -474,7 +475,7 @@
474 #address-cells = <1>; 475 #address-cells = <1>;
475 #size-cells = <0>; 476 #size-cells = <0>;
476 477
477 clk32k_in: clock { 478 clk32k_in: clock@0 {
478 compatible = "fixed-clock"; 479 compatible = "fixed-clock";
479 reg=<0>; 480 reg=<0>;
480 #clock-cells = <0>; 481 #clock-cells = <0>;
@@ -488,7 +489,7 @@
488 power { 489 power {
489 label = "Power"; 490 label = "Power";
490 gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>; 491 gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
491 linux,code = <116>; /* KEY_POWER */ 492 linux,code = <KEY_POWER>;
492 gpio-key,wakeup; 493 gpio-key,wakeup;
493 }; 494 };
494 }; 495 };
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
index d7a358a6a647..29051a2ae0ae 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dts
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -6,8 +6,8 @@
6 model = "Avionic Design Plutux board"; 6 model = "Avionic Design Plutux board";
7 compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20"; 7 compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20";
8 8
9 host1x { 9 host1x@50000000 {
10 hdmi { 10 hdmi@54280000 {
11 status = "okay"; 11 status = "okay";
12 }; 12 };
13 }; 13 };
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 315aae26c3cd..1204738dbf29 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -1,5 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3#include <dt-bindings/input/input.h>
3#include "tegra20.dtsi" 4#include "tegra20.dtsi"
4 5
5/ { 6/ {
@@ -10,8 +11,8 @@
10 reg = <0x00000000 0x40000000>; 11 reg = <0x00000000 0x40000000>;
11 }; 12 };
12 13
13 host1x { 14 host1x@50000000 {
14 hdmi { 15 hdmi@54280000 {
15 status = "okay"; 16 status = "okay";
16 17
17 vdd-supply = <&hdmi_vdd_reg>; 18 vdd-supply = <&hdmi_vdd_reg>;
@@ -23,7 +24,7 @@
23 }; 24 };
24 }; 25 };
25 26
26 pinmux { 27 pinmux@70000014 {
27 pinctrl-names = "default"; 28 pinctrl-names = "default";
28 pinctrl-0 = <&state_default>; 29 pinctrl-0 = <&state_default>;
29 30
@@ -189,53 +190,53 @@
189 "irtx", "pta", "rm", "sdc", "sdd", 190 "irtx", "pta", "rm", "sdc", "sdd",
190 "slxd", "slxk", "spdi", "spdo", "uac", 191 "slxd", "slxk", "spdi", "spdo", "uac",
191 "uad", "uca", "ucb", "uda"; 192 "uad", "uca", "ucb", "uda";
192 nvidia,pull = <0>; 193 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
193 nvidia,tristate = <0>; 194 nvidia,tristate = <TEGRA_PIN_DISABLE>;
194 }; 195 };
195 conf_ate { 196 conf_ate {
196 nvidia,pins = "ate", "csus", "dap3", 197 nvidia,pins = "ate", "csus", "dap3",
197 "gpv", "owc", "slxc", "spib", "spid", 198 "gpv", "owc", "slxc", "spib", "spid",
198 "spie"; 199 "spie";
199 nvidia,pull = <0>; 200 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
200 nvidia,tristate = <1>; 201 nvidia,tristate = <TEGRA_PIN_ENABLE>;
201 }; 202 };
202 conf_ck32 { 203 conf_ck32 {
203 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", 204 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
204 "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; 205 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
205 nvidia,pull = <0>; 206 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
206 }; 207 };
207 conf_crtp { 208 conf_crtp {
208 nvidia,pins = "crtp", "gmb", "slxa", "spia", 209 nvidia,pins = "crtp", "gmb", "slxa", "spia",
209 "spig", "spih"; 210 "spig", "spih";
210 nvidia,pull = <2>; 211 nvidia,pull = <TEGRA_PIN_PULL_UP>;
211 nvidia,tristate = <1>; 212 nvidia,tristate = <TEGRA_PIN_ENABLE>;
212 }; 213 };
213 conf_dta { 214 conf_dta {
214 nvidia,pins = "dta", "dtb", "dtc", "dtd"; 215 nvidia,pins = "dta", "dtb", "dtc", "dtd";
215 nvidia,pull = <1>; 216 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
216 nvidia,tristate = <0>; 217 nvidia,tristate = <TEGRA_PIN_DISABLE>;
217 }; 218 };
218 conf_dte { 219 conf_dte {
219 nvidia,pins = "dte", "spif"; 220 nvidia,pins = "dte", "spif";
220 nvidia,pull = <1>; 221 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
221 nvidia,tristate = <1>; 222 nvidia,tristate = <TEGRA_PIN_ENABLE>;
222 }; 223 };
223 conf_hdint { 224 conf_hdint {
224 nvidia,pins = "hdint", "lcsn", "ldc", "lm1", 225 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
225 "lpw1", "lsc1", "lsck", "lsda", "lsdi", 226 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
226 "lvp0"; 227 "lvp0";
227 nvidia,tristate = <1>; 228 nvidia,tristate = <TEGRA_PIN_ENABLE>;
228 }; 229 };
229 conf_kbca { 230 conf_kbca {
230 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", 231 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
231 "kbce", "kbcf", "sdio1", "spic", "uaa", 232 "kbce", "kbcf", "sdio1", "spic", "uaa",
232 "uab"; 233 "uab";
233 nvidia,pull = <2>; 234 nvidia,pull = <TEGRA_PIN_PULL_UP>;
234 nvidia,tristate = <0>; 235 nvidia,tristate = <TEGRA_PIN_DISABLE>;
235 }; 236 };
236 conf_lc { 237 conf_lc {
237 nvidia,pins = "lc", "ls"; 238 nvidia,pins = "lc", "ls";
238 nvidia,pull = <2>; 239 nvidia,pull = <TEGRA_PIN_PULL_UP>;
239 }; 240 };
240 conf_ld0 { 241 conf_ld0 {
241 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", 242 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
@@ -245,22 +246,22 @@
245 "lhp1", "lhp2", "lhs", "lm0", "lpp", 246 "lhp1", "lhp2", "lhs", "lm0", "lpp",
246 "lpw0", "lpw2", "lsc0", "lspi", "lvp1", 247 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
247 "lvs", "pmc", "sdb"; 248 "lvs", "pmc", "sdb";
248 nvidia,tristate = <0>; 249 nvidia,tristate = <TEGRA_PIN_DISABLE>;
249 }; 250 };
250 conf_ld17_0 { 251 conf_ld17_0 {
251 nvidia,pins = "ld17_0", "ld19_18", "ld21_20", 252 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
252 "ld23_22"; 253 "ld23_22";
253 nvidia,pull = <1>; 254 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
254 }; 255 };
255 drive_sdio1 { 256 drive_sdio1 {
256 nvidia,pins = "drive_sdio1"; 257 nvidia,pins = "drive_sdio1";
257 nvidia,high-speed-mode = <0>; 258 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
258 nvidia,schmitt = <0>; 259 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
259 nvidia,low-power-mode = <3>; 260 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
260 nvidia,pull-down-strength = <31>; 261 nvidia,pull-down-strength = <31>;
261 nvidia,pull-up-strength = <31>; 262 nvidia,pull-up-strength = <31>;
262 nvidia,slew-rate-rising = <3>; 263 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
263 nvidia,slew-rate-falling = <3>; 264 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
264 }; 265 };
265 }; 266 };
266 267
@@ -386,6 +387,13 @@
386 status = "okay"; 387 status = "okay";
387 clock-frequency = <400000>; 388 clock-frequency = <400000>;
388 389
390 magnetometer@c {
391 compatible = "ak,ak8975";
392 reg = <0xc>;
393 interrupt-parent = <&gpio>;
394 interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>;
395 };
396
389 pmic: tps6586x@34 { 397 pmic: tps6586x@34 {
390 compatible = "ti,tps6586x"; 398 compatible = "ti,tps6586x";
391 reg = <0x34>; 399 reg = <0x34>;
@@ -507,16 +515,149 @@
507 compatible = "onnn,nct1008"; 515 compatible = "onnn,nct1008";
508 reg = <0x4c>; 516 reg = <0x4c>;
509 }; 517 };
518 };
510 519
511 magnetometer@c { 520 kbc@7000e200 {
512 compatible = "ak,ak8975"; 521 status = "okay";
513 reg = <0xc>; 522 nvidia,debounce-delay-ms = <32>;
514 interrupt-parent = <&gpio>; 523 nvidia,repeat-delay-ms = <160>;
515 interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>; 524 nvidia,ghost-filter;
516 }; 525 nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
526 nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
527 linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W)
528 MATRIX_KEY(0x00, 0x03, KEY_S)
529 MATRIX_KEY(0x00, 0x04, KEY_A)
530 MATRIX_KEY(0x00, 0x05, KEY_Z)
531 MATRIX_KEY(0x00, 0x07, KEY_FN)
532
533 MATRIX_KEY(0x01, 0x07, KEY_LEFTMETA)
534 MATRIX_KEY(0x02, 0x06, KEY_RIGHTALT)
535 MATRIX_KEY(0x02, 0x07, KEY_LEFTALT)
536
537 MATRIX_KEY(0x03, 0x00, KEY_5)
538 MATRIX_KEY(0x03, 0x01, KEY_4)
539 MATRIX_KEY(0x03, 0x02, KEY_R)
540 MATRIX_KEY(0x03, 0x03, KEY_E)
541 MATRIX_KEY(0x03, 0x04, KEY_F)
542 MATRIX_KEY(0x03, 0x05, KEY_D)
543 MATRIX_KEY(0x03, 0x06, KEY_X)
544
545 MATRIX_KEY(0x04, 0x00, KEY_7)
546 MATRIX_KEY(0x04, 0x01, KEY_6)
547 MATRIX_KEY(0x04, 0x02, KEY_T)
548 MATRIX_KEY(0x04, 0x03, KEY_H)
549 MATRIX_KEY(0x04, 0x04, KEY_G)
550 MATRIX_KEY(0x04, 0x05, KEY_V)
551 MATRIX_KEY(0x04, 0x06, KEY_C)
552 MATRIX_KEY(0x04, 0x07, KEY_SPACE)
553
554 MATRIX_KEY(0x05, 0x00, KEY_9)
555 MATRIX_KEY(0x05, 0x01, KEY_8)
556 MATRIX_KEY(0x05, 0x02, KEY_U)
557 MATRIX_KEY(0x05, 0x03, KEY_Y)
558 MATRIX_KEY(0x05, 0x04, KEY_J)
559 MATRIX_KEY(0x05, 0x05, KEY_N)
560 MATRIX_KEY(0x05, 0x06, KEY_B)
561 MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH)
562
563 MATRIX_KEY(0x06, 0x00, KEY_MINUS)
564 MATRIX_KEY(0x06, 0x01, KEY_0)
565 MATRIX_KEY(0x06, 0x02, KEY_O)
566 MATRIX_KEY(0x06, 0x03, KEY_I)
567 MATRIX_KEY(0x06, 0x04, KEY_L)
568 MATRIX_KEY(0x06, 0x05, KEY_K)
569 MATRIX_KEY(0x06, 0x06, KEY_COMMA)
570 MATRIX_KEY(0x06, 0x07, KEY_M)
571
572 MATRIX_KEY(0x07, 0x01, KEY_EQUAL)
573 MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE)
574 MATRIX_KEY(0x07, 0x03, KEY_ENTER)
575 MATRIX_KEY(0x07, 0x07, KEY_MENU)
576
577 MATRIX_KEY(0x08, 0x04, KEY_RIGHTSHIFT)
578 MATRIX_KEY(0x08, 0x05, KEY_LEFTSHIFT)
579
580 MATRIX_KEY(0x09, 0x05, KEY_RIGHTCTRL)
581 MATRIX_KEY(0x09, 0x07, KEY_LEFTCTRL)
582
583 MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE)
584 MATRIX_KEY(0x0B, 0x01, KEY_P)
585 MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE)
586 MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON)
587 MATRIX_KEY(0x0B, 0x04, KEY_SLASH)
588 MATRIX_KEY(0x0B, 0x05, KEY_DOT)
589
590 MATRIX_KEY(0x0C, 0x00, KEY_F10)
591 MATRIX_KEY(0x0C, 0x01, KEY_F9)
592 MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE)
593 MATRIX_KEY(0x0C, 0x03, KEY_3)
594 MATRIX_KEY(0x0C, 0x04, KEY_2)
595 MATRIX_KEY(0x0C, 0x05, KEY_UP)
596 MATRIX_KEY(0x0C, 0x06, KEY_PRINT)
597 MATRIX_KEY(0x0C, 0x07, KEY_PAUSE)
598
599 MATRIX_KEY(0x0D, 0x00, KEY_INSERT)
600 MATRIX_KEY(0x0D, 0x01, KEY_DELETE)
601 MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP )
602 MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN)
603 MATRIX_KEY(0x0D, 0x05, KEY_RIGHT)
604 MATRIX_KEY(0x0D, 0x06, KEY_DOWN)
605 MATRIX_KEY(0x0D, 0x07, KEY_LEFT)
606
607 MATRIX_KEY(0x0E, 0x00, KEY_F11)
608 MATRIX_KEY(0x0E, 0x01, KEY_F12)
609 MATRIX_KEY(0x0E, 0x02, KEY_F8)
610 MATRIX_KEY(0x0E, 0x03, KEY_Q)
611 MATRIX_KEY(0x0E, 0x04, KEY_F4)
612 MATRIX_KEY(0x0E, 0x05, KEY_F3)
613 MATRIX_KEY(0x0E, 0x06, KEY_1)
614 MATRIX_KEY(0x0E, 0x07, KEY_F7)
615
616 MATRIX_KEY(0x0F, 0x00, KEY_ESC)
617 MATRIX_KEY(0x0F, 0x01, KEY_GRAVE)
618 MATRIX_KEY(0x0F, 0x02, KEY_F5)
619 MATRIX_KEY(0x0F, 0x03, KEY_TAB)
620 MATRIX_KEY(0x0F, 0x04, KEY_F1)
621 MATRIX_KEY(0x0F, 0x05, KEY_F2)
622 MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK)
623 MATRIX_KEY(0x0F, 0x07, KEY_F6)
624
625 /* Software Handled Function Keys */
626 MATRIX_KEY(0x14, 0x00, KEY_KP7)
627
628 MATRIX_KEY(0x15, 0x00, KEY_KP9)
629 MATRIX_KEY(0x15, 0x01, KEY_KP8)
630 MATRIX_KEY(0x15, 0x02, KEY_KP4)
631 MATRIX_KEY(0x15, 0x04, KEY_KP1)
632
633 MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
634 MATRIX_KEY(0x16, 0x02, KEY_KP6)
635 MATRIX_KEY(0x16, 0x03, KEY_KP5)
636 MATRIX_KEY(0x16, 0x04, KEY_KP3)
637 MATRIX_KEY(0x16, 0x05, KEY_KP2)
638 MATRIX_KEY(0x16, 0x07, KEY_KP0)
639
640 MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK)
641 MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS)
642 MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS)
643 MATRIX_KEY(0x1B, 0x05, KEY_KPDOT)
644
645 MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP)
646
647 MATRIX_KEY(0x1D, 0x03, KEY_HOME)
648 MATRIX_KEY(0x1D, 0x04, KEY_END)
649 MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSDOWN)
650 MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN)
651 MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSUP)
652
653 MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK)
654 MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK)
655 MATRIX_KEY(0x1E, 0x02, KEY_MUTE)
656
657 MATRIX_KEY(0x1F, 0x04, KEY_HELP)>;
517 }; 658 };
518 659
519 pmc { 660 pmc@7000e400 {
520 nvidia,invert-interrupt; 661 nvidia,invert-interrupt;
521 nvidia,suspend-mode = <1>; 662 nvidia,suspend-mode = <1>;
522 nvidia,cpu-pwr-good-time = <5000>; 663 nvidia,cpu-pwr-good-time = <5000>;
@@ -621,7 +762,7 @@
621 #address-cells = <1>; 762 #address-cells = <1>;
622 #size-cells = <0>; 763 #size-cells = <0>;
623 764
624 clk32k_in: clock { 765 clk32k_in: clock@0 {
625 compatible = "fixed-clock"; 766 compatible = "fixed-clock";
626 reg=<0>; 767 reg=<0>;
627 #clock-cells = <0>; 768 #clock-cells = <0>;
@@ -635,7 +776,7 @@
635 power { 776 power {
636 label = "Power"; 777 label = "Power";
637 gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; 778 gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
638 linux,code = <116>; /* KEY_POWER */ 779 linux,code = <KEY_POWER>;
639 gpio-key,wakeup; 780 gpio-key,wakeup;
640 }; 781 };
641 782
@@ -649,145 +790,6 @@
649 }; 790 };
650 }; 791 };
651 792
652 kbc {
653 status = "okay";
654 nvidia,debounce-delay-ms = <32>;
655 nvidia,repeat-delay-ms = <160>;
656 nvidia,ghost-filter;
657 nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
658 nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
659 linux,keymap = <0x00020011 /* KEY_W */
660 0x0003001F /* KEY_S */
661 0x0004001E /* KEY_A */
662 0x0005002C /* KEY_Z */
663 0x000701d0 /* KEY_FN */
664
665 0x0107007D /* KEY_LEFTMETA */
666 0x02060064 /* KEY_RIGHTALT */
667 0x02070038 /* KEY_LEFTALT */
668
669 0x03000006 /* KEY_5 */
670 0x03010005 /* KEY_4 */
671 0x03020013 /* KEY_R */
672 0x03030012 /* KEY_E */
673 0x03040021 /* KEY_F */
674 0x03050020 /* KEY_D */
675 0x0306002D /* KEY_X */
676
677 0x04000008 /* KEY_7 */
678 0x04010007 /* KEY_6 */
679 0x04020014 /* KEY_T */
680 0x04030023 /* KEY_H */
681 0x04040022 /* KEY_G */
682 0x0405002F /* KEY_V */
683 0x0406002E /* KEY_C */
684 0x04070039 /* KEY_SPACE */
685
686 0x0500000A /* KEY_9 */
687 0x05010009 /* KEY_8 */
688 0x05020016 /* KEY_U */
689 0x05030015 /* KEY_Y */
690 0x05040024 /* KEY_J */
691 0x05050031 /* KEY_N */
692 0x05060030 /* KEY_B */
693 0x0507002B /* KEY_BACKSLASH */
694
695 0x0600000C /* KEY_MINUS */
696 0x0601000B /* KEY_0 */
697 0x06020018 /* KEY_O */
698 0x06030017 /* KEY_I */
699 0x06040026 /* KEY_L */
700 0x06050025 /* KEY_K */
701 0x06060033 /* KEY_COMMA */
702 0x06070032 /* KEY_M */
703
704 0x0701000D /* KEY_EQUAL */
705 0x0702001B /* KEY_RIGHTBRACE */
706 0x0703001C /* KEY_ENTER */
707 0x0707008B /* KEY_MENU */
708
709 0x08040036 /* KEY_RIGHTSHIFT */
710 0x0805002A /* KEY_LEFTSHIFT */
711
712 0x09050061 /* KEY_RIGHTCTRL */
713 0x0907001D /* KEY_LEFTCTRL */
714
715 0x0B00001A /* KEY_LEFTBRACE */
716 0x0B010019 /* KEY_P */
717 0x0B020028 /* KEY_APOSTROPHE */
718 0x0B030027 /* KEY_SEMICOLON */
719 0x0B040035 /* KEY_SLASH */
720 0x0B050034 /* KEY_DOT */
721
722 0x0C000044 /* KEY_F10 */
723 0x0C010043 /* KEY_F9 */
724 0x0C02000E /* KEY_BACKSPACE */
725 0x0C030004 /* KEY_3 */
726 0x0C040003 /* KEY_2 */
727 0x0C050067 /* KEY_UP */
728 0x0C0600D2 /* KEY_PRINT */
729 0x0C070077 /* KEY_PAUSE */
730
731 0x0D00006E /* KEY_INSERT */
732 0x0D01006F /* KEY_DELETE */
733 0x0D030068 /* KEY_PAGEUP */
734 0x0D04006D /* KEY_PAGEDOWN */
735 0x0D05006A /* KEY_RIGHT */
736 0x0D06006C /* KEY_DOWN */
737 0x0D070069 /* KEY_LEFT */
738
739 0x0E000057 /* KEY_F11 */
740 0x0E010058 /* KEY_F12 */
741 0x0E020042 /* KEY_F8 */
742 0x0E030010 /* KEY_Q */
743 0x0E04003E /* KEY_F4 */
744 0x0E05003D /* KEY_F3 */
745 0x0E060002 /* KEY_1 */
746 0x0E070041 /* KEY_F7 */
747
748 0x0F000001 /* KEY_ESC */
749 0x0F010029 /* KEY_GRAVE */
750 0x0F02003F /* KEY_F5 */
751 0x0F03000F /* KEY_TAB */
752 0x0F04003B /* KEY_F1 */
753 0x0F05003C /* KEY_F2 */
754 0x0F06003A /* KEY_CAPSLOCK */
755 0x0F070040 /* KEY_F6 */
756
757 /* Software Handled Function Keys */
758 0x14000047 /* KEY_KP7 */
759
760 0x15000049 /* KEY_KP9 */
761 0x15010048 /* KEY_KP8 */
762 0x1502004B /* KEY_KP4 */
763 0x1504004F /* KEY_KP1 */
764
765 0x1601004E /* KEY_KPSLASH */
766 0x1602004D /* KEY_KP6 */
767 0x1603004C /* KEY_KP5 */
768 0x16040051 /* KEY_KP3 */
769 0x16050050 /* KEY_KP2 */
770 0x16070052 /* KEY_KP0 */
771
772 0x1B010037 /* KEY_KPASTERISK */
773 0x1B03004A /* KEY_KPMINUS */
774 0x1B04004E /* KEY_KPPLUS */
775 0x1B050053 /* KEY_KPDOT */
776
777 0x1C050073 /* KEY_VOLUMEUP */
778
779 0x1D030066 /* KEY_HOME */
780 0x1D04006B /* KEY_END */
781 0x1D0500E0 /* KEY_BRIGHTNESSDOWN */
782 0x1D060072 /* KEY_VOLUMEDOWN */
783 0x1D0700E1 /* KEY_BRIGHTNESSUP */
784
785 0x1E000045 /* KEY_NUMLOCK */
786 0x1E010046 /* KEY_SCROLLLOCK */
787 0x1E020071 /* KEY_MUTE */
788
789 0x1F04008A>; /* KEY_HELP */
790 };
791 regulators { 793 regulators {
792 compatible = "simple-bus"; 794 compatible = "simple-bus";
793 #address-cells = <1>; 795 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index 7726dab3d08d..eb2f9aa211a2 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -8,8 +8,8 @@
8 reg = <0x00000000 0x20000000>; 8 reg = <0x00000000 0x20000000>;
9 }; 9 };
10 10
11 host1x { 11 host1x@50000000 {
12 hdmi { 12 hdmi@54280000 {
13 vdd-supply = <&hdmi_vdd_reg>; 13 vdd-supply = <&hdmi_vdd_reg>;
14 pll-supply = <&hdmi_pll_reg>; 14 pll-supply = <&hdmi_pll_reg>;
15 15
@@ -19,7 +19,7 @@
19 }; 19 };
20 }; 20 };
21 21
22 pinmux { 22 pinmux@70000014 {
23 pinctrl-names = "default"; 23 pinctrl-names = "default";
24 pinctrl-0 = <&state_default>; 24 pinctrl-0 = <&state_default>;
25 25
@@ -176,50 +176,50 @@
176 "gmb", "gmc", "gmd", "gme", "gpu7", 176 "gmb", "gmc", "gmd", "gme", "gpu7",
177 "gpv", "i2cp", "pta", "rm", "slxa", 177 "gpv", "i2cp", "pta", "rm", "slxa",
178 "slxk", "spia", "spib", "uac"; 178 "slxk", "spia", "spib", "uac";
179 nvidia,pull = <0>; 179 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
180 nvidia,tristate = <0>; 180 nvidia,tristate = <TEGRA_PIN_DISABLE>;
181 }; 181 };
182 conf_ck32 { 182 conf_ck32 {
183 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", 183 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
184 "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; 184 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
185 nvidia,pull = <0>; 185 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
186 }; 186 };
187 conf_csus { 187 conf_csus {
188 nvidia,pins = "csus", "spid", "spif"; 188 nvidia,pins = "csus", "spid", "spif";
189 nvidia,pull = <1>; 189 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
190 nvidia,tristate = <1>; 190 nvidia,tristate = <TEGRA_PIN_ENABLE>;
191 }; 191 };
192 conf_crtp { 192 conf_crtp {
193 nvidia,pins = "crtp", "dap2", "dap3", "dap4", 193 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
194 "dtc", "dte", "dtf", "gpu", "sdio1", 194 "dtc", "dte", "dtf", "gpu", "sdio1",
195 "slxc", "slxd", "spdi", "spdo", "spig", 195 "slxc", "slxd", "spdi", "spdo", "spig",
196 "uda"; 196 "uda";
197 nvidia,pull = <0>; 197 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
198 nvidia,tristate = <1>; 198 nvidia,tristate = <TEGRA_PIN_ENABLE>;
199 }; 199 };
200 conf_ddc { 200 conf_ddc {
201 nvidia,pins = "ddc", "dta", "dtd", "kbca", 201 nvidia,pins = "ddc", "dta", "dtd", "kbca",
202 "kbcb", "kbcc", "kbcd", "kbce", "kbcf", 202 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
203 "sdc"; 203 "sdc";
204 nvidia,pull = <2>; 204 nvidia,pull = <TEGRA_PIN_PULL_UP>;
205 nvidia,tristate = <0>; 205 nvidia,tristate = <TEGRA_PIN_DISABLE>;
206 }; 206 };
207 conf_hdint { 207 conf_hdint {
208 nvidia,pins = "hdint", "lcsn", "ldc", "lm1", 208 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
209 "lpw1", "lsc1", "lsck", "lsda", "lsdi", 209 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
210 "lvp0", "owc", "sdb"; 210 "lvp0", "owc", "sdb";
211 nvidia,tristate = <1>; 211 nvidia,tristate = <TEGRA_PIN_ENABLE>;
212 }; 212 };
213 conf_irrx { 213 conf_irrx {
214 nvidia,pins = "irrx", "irtx", "sdd", "spic", 214 nvidia,pins = "irrx", "irtx", "sdd", "spic",
215 "spie", "spih", "uaa", "uab", "uad", 215 "spie", "spih", "uaa", "uab", "uad",
216 "uca", "ucb"; 216 "uca", "ucb";
217 nvidia,pull = <2>; 217 nvidia,pull = <TEGRA_PIN_PULL_UP>;
218 nvidia,tristate = <1>; 218 nvidia,tristate = <TEGRA_PIN_ENABLE>;
219 }; 219 };
220 conf_lc { 220 conf_lc {
221 nvidia,pins = "lc", "ls"; 221 nvidia,pins = "lc", "ls";
222 nvidia,pull = <2>; 222 nvidia,pull = <TEGRA_PIN_PULL_UP>;
223 }; 223 };
224 conf_ld0 { 224 conf_ld0 {
225 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", 225 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
@@ -229,12 +229,12 @@
229 "lhp1", "lhp2", "lhs", "lm0", "lpp", 229 "lhp1", "lhp2", "lhs", "lm0", "lpp",
230 "lpw0", "lpw2", "lsc0", "lspi", "lvp1", 230 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
231 "lvs", "pmc"; 231 "lvs", "pmc";
232 nvidia,tristate = <0>; 232 nvidia,tristate = <TEGRA_PIN_DISABLE>;
233 }; 233 };
234 conf_ld17_0 { 234 conf_ld17_0 {
235 nvidia,pins = "ld17_0", "ld19_18", "ld21_20", 235 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
236 "ld23_22"; 236 "ld23_22";
237 nvidia,pull = <1>; 237 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
238 }; 238 };
239 }; 239 };
240 240
@@ -457,7 +457,7 @@
457 }; 457 };
458 }; 458 };
459 459
460 pmc { 460 pmc@7000e400 {
461 nvidia,invert-interrupt; 461 nvidia,invert-interrupt;
462 nvidia,suspend-mode = <1>; 462 nvidia,suspend-mode = <1>;
463 nvidia,cpu-pwr-good-time = <5000>; 463 nvidia,cpu-pwr-good-time = <5000>;
@@ -467,7 +467,7 @@
467 nvidia,sys-clock-req-active-high; 467 nvidia,sys-clock-req-active-high;
468 }; 468 };
469 469
470 pcie-controller { 470 pcie-controller@80003000 {
471 pex-clk-supply = <&pci_clk_reg>; 471 pex-clk-supply = <&pci_clk_reg>;
472 vdd-supply = <&pci_vdd_reg>; 472 vdd-supply = <&pci_vdd_reg>;
473 }; 473 };
@@ -492,7 +492,7 @@
492 #address-cells = <1>; 492 #address-cells = <1>;
493 #size-cells = <0>; 493 #size-cells = <0>;
494 494
495 clk32k_in: clock { 495 clk32k_in: clock@0 {
496 compatible = "fixed-clock"; 496 compatible = "fixed-clock";
497 reg=<0>; 497 reg=<0>;
498 #clock-cells = <0>; 498 #clock-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
index 3ada3cb67f07..890562c667fb 100644
--- a/arch/arm/boot/dts/tegra20-tec.dts
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -6,8 +6,8 @@
6 model = "Avionic Design Tamonten Evaluation Carrier"; 6 model = "Avionic Design Tamonten Evaluation Carrier";
7 compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20"; 7 compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20";
8 8
9 host1x { 9 host1x@50000000 {
10 hdmi { 10 hdmi@54280000 {
11 status = "okay"; 11 status = "okay";
12 }; 12 };
13 }; 13 };
@@ -32,7 +32,7 @@
32 }; 32 };
33 }; 33 };
34 34
35 pcie-controller { 35 pcie-controller@80003000 {
36 status = "okay"; 36 status = "okay";
37 37
38 pci@1,0 { 38 pci@1,0 {
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 78deea5c0d21..ec36fafb0f90 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -1,5 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3#include <dt-bindings/input/input.h>
3#include "tegra20.dtsi" 4#include "tegra20.dtsi"
4 5
5/ { 6/ {
@@ -10,8 +11,8 @@
10 reg = <0x00000000 0x40000000>; 11 reg = <0x00000000 0x40000000>;
11 }; 12 };
12 13
13 host1x { 14 host1x@50000000 {
14 hdmi { 15 hdmi@54280000 {
15 status = "okay"; 16 status = "okay";
16 17
17 vdd-supply = <&hdmi_vdd_reg>; 18 vdd-supply = <&hdmi_vdd_reg>;
@@ -23,7 +24,7 @@
23 }; 24 };
24 }; 25 };
25 26
26 pinmux { 27 pinmux@70000014 {
27 pinctrl-names = "default"; 28 pinctrl-names = "default";
28 pinctrl-0 = <&state_default>; 29 pinctrl-0 = <&state_default>;
29 30
@@ -191,49 +192,49 @@
191 "dtb", "dtc", "dtd", "dte", "gmb", 192 "dtb", "dtc", "dtd", "dte", "gmb",
192 "gme", "i2cp", "pta", "slxc", "slxd", 193 "gme", "i2cp", "pta", "slxc", "slxd",
193 "spdi", "spdo", "uda"; 194 "spdi", "spdo", "uda";
194 nvidia,pull = <0>; 195 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
195 nvidia,tristate = <1>; 196 nvidia,tristate = <TEGRA_PIN_ENABLE>;
196 }; 197 };
197 conf_atb { 198 conf_atb {
198 nvidia,pins = "atb", "cdev1", "cdev2", "dap1", 199 nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
199 "gma", "gmc", "gmd", "gpu", "gpu7", 200 "gma", "gmc", "gmd", "gpu", "gpu7",
200 "gpv", "sdio1", "slxa", "slxk", "uac"; 201 "gpv", "sdio1", "slxa", "slxk", "uac";
201 nvidia,pull = <0>; 202 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
202 nvidia,tristate = <0>; 203 nvidia,tristate = <TEGRA_PIN_DISABLE>;
203 }; 204 };
204 conf_ck32 { 205 conf_ck32 {
205 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", 206 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
206 "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; 207 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
207 nvidia,pull = <0>; 208 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
208 }; 209 };
209 conf_csus { 210 conf_csus {
210 nvidia,pins = "csus", "spia", "spib", 211 nvidia,pins = "csus", "spia", "spib",
211 "spid", "spif"; 212 "spid", "spif";
212 nvidia,pull = <1>; 213 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
213 nvidia,tristate = <1>; 214 nvidia,tristate = <TEGRA_PIN_ENABLE>;
214 }; 215 };
215 conf_ddc { 216 conf_ddc {
216 nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd"; 217 nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
217 nvidia,pull = <2>; 218 nvidia,pull = <TEGRA_PIN_PULL_UP>;
218 nvidia,tristate = <0>; 219 nvidia,tristate = <TEGRA_PIN_DISABLE>;
219 }; 220 };
220 conf_hdint { 221 conf_hdint {
221 nvidia,pins = "hdint", "lcsn", "ldc", "lm1", 222 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
222 "lpw1", "lsc1", "lsck", "lsda", "lsdi", 223 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
223 "lvp0", "pmc"; 224 "lvp0", "pmc";
224 nvidia,tristate = <1>; 225 nvidia,tristate = <TEGRA_PIN_ENABLE>;
225 }; 226 };
226 conf_irrx { 227 conf_irrx {
227 nvidia,pins = "irrx", "irtx", "kbca", "kbcb", 228 nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
228 "kbcc", "kbcd", "kbce", "kbcf", "owc", 229 "kbcc", "kbcd", "kbce", "kbcf", "owc",
229 "spic", "spie", "spig", "spih", "uaa", 230 "spic", "spie", "spig", "spih", "uaa",
230 "uab", "uad", "uca", "ucb"; 231 "uab", "uad", "uca", "ucb";
231 nvidia,pull = <2>; 232 nvidia,pull = <TEGRA_PIN_PULL_UP>;
232 nvidia,tristate = <1>; 233 nvidia,tristate = <TEGRA_PIN_ENABLE>;
233 }; 234 };
234 conf_lc { 235 conf_lc {
235 nvidia,pins = "lc", "ls"; 236 nvidia,pins = "lc", "ls";
236 nvidia,pull = <2>; 237 nvidia,pull = <TEGRA_PIN_PULL_UP>;
237 }; 238 };
238 conf_ld0 { 239 conf_ld0 {
239 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", 240 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
@@ -243,17 +244,17 @@
243 "lhp1", "lhp2", "lhs", "lm0", "lpp", 244 "lhp1", "lhp2", "lhs", "lm0", "lpp",
244 "lpw0", "lpw2", "lsc0", "lspi", "lvp1", 245 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
245 "lvs", "sdb"; 246 "lvs", "sdb";
246 nvidia,tristate = <0>; 247 nvidia,tristate = <TEGRA_PIN_DISABLE>;
247 }; 248 };
248 conf_ld17_0 { 249 conf_ld17_0 {
249 nvidia,pins = "ld17_0", "ld19_18", "ld21_20", 250 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
250 "ld23_22"; 251 "ld23_22";
251 nvidia,pull = <1>; 252 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
252 }; 253 };
253 conf_spif { 254 conf_spif {
254 nvidia,pins = "spif"; 255 nvidia,pins = "spif";
255 nvidia,pull = <1>; 256 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
256 nvidia,tristate = <0>; 257 nvidia,tristate = <TEGRA_PIN_DISABLE>;
257 }; 258 };
258 }; 259 };
259 }; 260 };
@@ -301,7 +302,7 @@
301 }; 302 };
302 }; 303 };
303 304
304 pmc { 305 pmc@7000e400 {
305 nvidia,suspend-mode = <1>; 306 nvidia,suspend-mode = <1>;
306 nvidia,cpu-pwr-good-time = <5000>; 307 nvidia,cpu-pwr-good-time = <5000>;
307 nvidia,cpu-pwr-off-time = <5000>; 308 nvidia,cpu-pwr-off-time = <5000>;
@@ -310,7 +311,7 @@
310 nvidia,sys-clock-req-active-high; 311 nvidia,sys-clock-req-active-high;
311 }; 312 };
312 313
313 pcie-controller { 314 pcie-controller@80003000 {
314 status = "okay"; 315 status = "okay";
315 pex-clk-supply = <&pci_clk_reg>; 316 pex-clk-supply = <&pci_clk_reg>;
316 vdd-supply = <&pci_vdd_reg>; 317 vdd-supply = <&pci_vdd_reg>;
@@ -366,7 +367,7 @@
366 #address-cells = <1>; 367 #address-cells = <1>;
367 #size-cells = <0>; 368 #size-cells = <0>;
368 369
369 clk32k_in: clock { 370 clk32k_in: clock@0 {
370 compatible = "fixed-clock"; 371 compatible = "fixed-clock";
371 reg=<0>; 372 reg=<0>;
372 #clock-cells = <0>; 373 #clock-cells = <0>;
@@ -380,7 +381,7 @@
380 power { 381 power {
381 label = "Power"; 382 label = "Power";
382 gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; 383 gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
383 linux,code = <116>; /* KEY_POWER */ 384 linux,code = <KEY_POWER>;
384 gpio-key,wakeup; 385 gpio-key,wakeup;
385 }; 386 };
386 }; 387 };
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index aab872cd0530..0d83062b9be4 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -1,5 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3#include <dt-bindings/input/input.h>
3#include "tegra20.dtsi" 4#include "tegra20.dtsi"
4 5
5/ { 6/ {
@@ -10,8 +11,8 @@
10 reg = <0x00000000 0x40000000>; 11 reg = <0x00000000 0x40000000>;
11 }; 12 };
12 13
13 host1x { 14 host1x@50000000 {
14 hdmi { 15 hdmi@54280000 {
15 status = "okay"; 16 status = "okay";
16 17
17 vdd-supply = <&hdmi_vdd_reg>; 18 vdd-supply = <&hdmi_vdd_reg>;
@@ -23,7 +24,7 @@
23 }; 24 };
24 }; 25 };
25 26
26 pinmux { 27 pinmux@70000014 {
27 pinctrl-names = "default"; 28 pinctrl-names = "default";
28 pinctrl-0 = <&state_default>; 29 pinctrl-0 = <&state_default>;
29 30
@@ -189,50 +190,50 @@
189 "irtx", "pta", "rm", "sdc", "sdd", 190 "irtx", "pta", "rm", "sdc", "sdd",
190 "slxc", "slxd", "slxk", "spdi", "spdo", 191 "slxc", "slxd", "slxk", "spdi", "spdo",
191 "uac", "uad", "uca", "ucb", "uda"; 192 "uac", "uad", "uca", "ucb", "uda";
192 nvidia,pull = <0>; 193 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
193 nvidia,tristate = <0>; 194 nvidia,tristate = <TEGRA_PIN_DISABLE>;
194 }; 195 };
195 conf_ate { 196 conf_ate {
196 nvidia,pins = "ate", "csus", "dap3", "gmd", 197 nvidia,pins = "ate", "csus", "dap3", "gmd",
197 "gpv", "owc", "spia", "spib", "spic", 198 "gpv", "owc", "spia", "spib", "spic",
198 "spid", "spie", "spig"; 199 "spid", "spie", "spig";
199 nvidia,pull = <0>; 200 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
200 nvidia,tristate = <1>; 201 nvidia,tristate = <TEGRA_PIN_ENABLE>;
201 }; 202 };
202 conf_ck32 { 203 conf_ck32 {
203 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", 204 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
204 "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; 205 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
205 nvidia,pull = <0>; 206 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
206 }; 207 };
207 conf_crtp { 208 conf_crtp {
208 nvidia,pins = "crtp", "gmb", "slxa", "spih"; 209 nvidia,pins = "crtp", "gmb", "slxa", "spih";
209 nvidia,pull = <2>; 210 nvidia,pull = <TEGRA_PIN_PULL_UP>;
210 nvidia,tristate = <1>; 211 nvidia,tristate = <TEGRA_PIN_ENABLE>;
211 }; 212 };
212 conf_dta { 213 conf_dta {
213 nvidia,pins = "dta", "dtb", "dtc", "dtd"; 214 nvidia,pins = "dta", "dtb", "dtc", "dtd";
214 nvidia,pull = <1>; 215 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
215 nvidia,tristate = <0>; 216 nvidia,tristate = <TEGRA_PIN_DISABLE>;
216 }; 217 };
217 conf_dte { 218 conf_dte {
218 nvidia,pins = "dte", "spif"; 219 nvidia,pins = "dte", "spif";
219 nvidia,pull = <1>; 220 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
220 nvidia,tristate = <1>; 221 nvidia,tristate = <TEGRA_PIN_ENABLE>;
221 }; 222 };
222 conf_hdint { 223 conf_hdint {
223 nvidia,pins = "hdint", "lcsn", "ldc", "lm1", 224 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
224 "lpw1", "lsck", "lsda", "lsdi", "lvp0"; 225 "lpw1", "lsck", "lsda", "lsdi", "lvp0";
225 nvidia,tristate = <1>; 226 nvidia,tristate = <TEGRA_PIN_ENABLE>;
226 }; 227 };
227 conf_kbca { 228 conf_kbca {
228 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", 229 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
229 "kbce", "kbcf", "sdio1", "uaa", "uab"; 230 "kbce", "kbcf", "sdio1", "uaa", "uab";
230 nvidia,pull = <2>; 231 nvidia,pull = <TEGRA_PIN_PULL_UP>;
231 nvidia,tristate = <0>; 232 nvidia,tristate = <TEGRA_PIN_DISABLE>;
232 }; 233 };
233 conf_lc { 234 conf_lc {
234 nvidia,pins = "lc", "ls"; 235 nvidia,pins = "lc", "ls";
235 nvidia,pull = <2>; 236 nvidia,pull = <TEGRA_PIN_PULL_UP>;
236 }; 237 };
237 conf_ld0 { 238 conf_ld0 {
238 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", 239 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
@@ -242,22 +243,22 @@
242 "lhp1", "lhp2", "lhs", "lm0", "lpp", 243 "lhp1", "lhp2", "lhs", "lm0", "lpp",
243 "lpw0", "lpw2", "lsc0", "lsc1", "lspi", 244 "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
244 "lvp1", "lvs", "pmc", "sdb"; 245 "lvp1", "lvs", "pmc", "sdb";
245 nvidia,tristate = <0>; 246 nvidia,tristate = <TEGRA_PIN_DISABLE>;
246 }; 247 };
247 conf_ld17_0 { 248 conf_ld17_0 {
248 nvidia,pins = "ld17_0", "ld19_18", "ld21_20", 249 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
249 "ld23_22"; 250 "ld23_22";
250 nvidia,pull = <1>; 251 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
251 }; 252 };
252 drive_sdio1 { 253 drive_sdio1 {
253 nvidia,pins = "drive_sdio1"; 254 nvidia,pins = "drive_sdio1";
254 nvidia,high-speed-mode = <0>; 255 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
255 nvidia,schmitt = <1>; 256 nvidia,schmitt = <TEGRA_PIN_ENABLE>;
256 nvidia,low-power-mode = <3>; 257 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
257 nvidia,pull-down-strength = <31>; 258 nvidia,pull-down-strength = <31>;
258 nvidia,pull-up-strength = <31>; 259 nvidia,pull-up-strength = <31>;
259 nvidia,slew-rate-rising = <3>; 260 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
260 nvidia,slew-rate-falling = <3>; 261 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
261 }; 262 };
262 }; 263 };
263 264
@@ -492,7 +493,7 @@
492 }; 493 };
493 }; 494 };
494 495
495 pmc { 496 pmc@7000e400 {
496 nvidia,invert-interrupt; 497 nvidia,invert-interrupt;
497 nvidia,suspend-mode = <1>; 498 nvidia,suspend-mode = <1>;
498 nvidia,cpu-pwr-good-time = <2000>; 499 nvidia,cpu-pwr-good-time = <2000>;
@@ -556,7 +557,7 @@
556 #address-cells = <1>; 557 #address-cells = <1>;
557 #size-cells = <0>; 558 #size-cells = <0>;
558 559
559 clk32k_in: clock { 560 clk32k_in: clock@0 {
560 compatible = "fixed-clock"; 561 compatible = "fixed-clock";
561 reg=<0>; 562 reg=<0>;
562 #clock-cells = <0>; 563 #clock-cells = <0>;
@@ -570,7 +571,7 @@
570 power { 571 power {
571 label = "Power"; 572 label = "Power";
572 gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; 573 gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
573 linux,code = <116>; /* KEY_POWER */ 574 linux,code = <KEY_POWER>;
574 gpio-key,wakeup; 575 gpio-key,wakeup;
575 }; 576 };
576 }; 577 };
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index d33a73cf167c..813b04ef8717 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -1,5 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3#include <dt-bindings/input/input.h>
3#include "tegra20.dtsi" 4#include "tegra20.dtsi"
4 5
5/ { 6/ {
@@ -10,8 +11,8 @@
10 reg = <0x00000000 0x20000000>; 11 reg = <0x00000000 0x20000000>;
11 }; 12 };
12 13
13 host1x { 14 host1x@50000000 {
14 hdmi { 15 hdmi@54280000 {
15 status = "okay"; 16 status = "okay";
16 17
17 vdd-supply = <&hdmi_vdd_reg>; 18 vdd-supply = <&hdmi_vdd_reg>;
@@ -23,7 +24,7 @@
23 }; 24 };
24 }; 25 };
25 26
26 pinmux { 27 pinmux@70000014 {
27 pinctrl-names = "default"; 28 pinctrl-names = "default";
28 pinctrl-0 = <&state_default>; 29 pinctrl-0 = <&state_default>;
29 30
@@ -189,8 +190,8 @@
189 "kbcf", "sdc", "sdd", "spie", "spig", 190 "kbcf", "sdc", "sdd", "spie", "spig",
190 "spih", "uaa", "uab", "uad", "uca", 191 "spih", "uaa", "uab", "uad", "uca",
191 "ucb"; 192 "ucb";
192 nvidia,pull = <2>; 193 nvidia,pull = <TEGRA_PIN_PULL_UP>;
193 nvidia,tristate = <0>; 194 nvidia,tristate = <TEGRA_PIN_DISABLE>;
194 }; 195 };
195 conf_atd { 196 conf_atd {
196 nvidia,pins = "atd", "ate", "cdev1", "csus", 197 nvidia,pins = "atd", "ate", "cdev1", "csus",
@@ -198,54 +199,54 @@
198 "dtf", "gpu", "gpu7", "gpv", "i2cp", 199 "dtf", "gpu", "gpu7", "gpv", "i2cp",
199 "rm", "sdio1", "slxa", "slxc", "slxd", 200 "rm", "sdio1", "slxa", "slxc", "slxd",
200 "slxk", "spdi", "spdo", "uac", "uda"; 201 "slxk", "spdi", "spdo", "uac", "uda";
201 nvidia,pull = <0>; 202 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
202 nvidia,tristate = <0>; 203 nvidia,tristate = <TEGRA_PIN_DISABLE>;
203 }; 204 };
204 conf_cdev2 { 205 conf_cdev2 {
205 nvidia,pins = "cdev2", "spia", "spib"; 206 nvidia,pins = "cdev2", "spia", "spib";
206 nvidia,pull = <1>; 207 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
207 nvidia,tristate = <1>; 208 nvidia,tristate = <TEGRA_PIN_ENABLE>;
208 }; 209 };
209 conf_ck32 { 210 conf_ck32 {
210 nvidia,pins = "ck32", "ddrc", "lc", "pmca", 211 nvidia,pins = "ck32", "ddrc", "lc", "pmca",
211 "pmcb", "pmcc", "pmcd", "xm2c", 212 "pmcb", "pmcc", "pmcd", "xm2c",
212 "xm2d"; 213 "xm2d";
213 nvidia,pull = <0>; 214 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
214 }; 215 };
215 conf_crtp { 216 conf_crtp {
216 nvidia,pins = "crtp"; 217 nvidia,pins = "crtp";
217 nvidia,pull = <0>; 218 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
218 nvidia,tristate = <1>; 219 nvidia,tristate = <TEGRA_PIN_ENABLE>;
219 }; 220 };
220 conf_dta { 221 conf_dta {
221 nvidia,pins = "dta", "dtb", "dtc", "dtd", 222 nvidia,pins = "dta", "dtb", "dtc", "dtd",
222 "spid", "spif"; 223 "spid", "spif";
223 nvidia,pull = <1>; 224 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
224 nvidia,tristate = <0>; 225 nvidia,tristate = <TEGRA_PIN_DISABLE>;
225 }; 226 };
226 conf_gme { 227 conf_gme {
227 nvidia,pins = "gme", "owc", "pta", "spic"; 228 nvidia,pins = "gme", "owc", "pta", "spic";
228 nvidia,pull = <2>; 229 nvidia,pull = <TEGRA_PIN_PULL_UP>;
229 nvidia,tristate = <1>; 230 nvidia,tristate = <TEGRA_PIN_ENABLE>;
230 }; 231 };
231 conf_ld17_0 { 232 conf_ld17_0 {
232 nvidia,pins = "ld17_0", "ld19_18", "ld21_20", 233 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
233 "ld23_22"; 234 "ld23_22";
234 nvidia,pull = <1>; 235 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
235 }; 236 };
236 conf_ls { 237 conf_ls {
237 nvidia,pins = "ls", "pmce"; 238 nvidia,pins = "ls", "pmce";
238 nvidia,pull = <2>; 239 nvidia,pull = <TEGRA_PIN_PULL_UP>;
239 }; 240 };
240 drive_dap1 { 241 drive_dap1 {
241 nvidia,pins = "drive_dap1"; 242 nvidia,pins = "drive_dap1";
242 nvidia,high-speed-mode = <0>; 243 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
243 nvidia,schmitt = <1>; 244 nvidia,schmitt = <TEGRA_PIN_ENABLE>;
244 nvidia,low-power-mode = <0>; 245 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_8>;
245 nvidia,pull-down-strength = <0>; 246 nvidia,pull-down-strength = <0>;
246 nvidia,pull-up-strength = <0>; 247 nvidia,pull-up-strength = <0>;
247 nvidia,slew-rate-rising = <0>; 248 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
248 nvidia,slew-rate-falling = <0>; 249 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
249 }; 250 };
250 }; 251 };
251 }; 252 };
@@ -495,7 +496,20 @@
495 }; 496 };
496 }; 497 };
497 498
498 pmc { 499 kbc@7000e200 {
500 status = "okay";
501 nvidia,debounce-delay-ms = <20>;
502 nvidia,repeat-delay-ms = <160>;
503 nvidia,kbc-row-pins = <0 1 2>;
504 nvidia,kbc-col-pins = <16 17>;
505 nvidia,wakeup-source;
506 linux,keymap = <MATRIX_KEY(0x00, 0x00, KEY_POWER)
507 MATRIX_KEY(0x01, 0x00, KEY_HOME)
508 MATRIX_KEY(0x01, 0x01, KEY_BACK)
509 MATRIX_KEY(0x02, 0x01, KEY_MENU)>;
510 };
511
512 pmc@7000e400 {
499 nvidia,invert-interrupt; 513 nvidia,invert-interrupt;
500 nvidia,suspend-mode = <1>; 514 nvidia,suspend-mode = <1>;
501 nvidia,cpu-pwr-good-time = <2000>; 515 nvidia,cpu-pwr-good-time = <2000>;
@@ -543,7 +557,7 @@
543 #address-cells = <1>; 557 #address-cells = <1>;
544 #size-cells = <0>; 558 #size-cells = <0>;
545 559
546 clk32k_in: clock { 560 clk32k_in: clock@0 {
547 compatible = "fixed-clock"; 561 compatible = "fixed-clock";
548 reg=<0>; 562 reg=<0>;
549 #clock-cells = <0>; 563 #clock-cells = <0>;
@@ -551,25 +565,12 @@
551 }; 565 };
552 }; 566 };
553 567
554 kbc {
555 status = "okay";
556 nvidia,debounce-delay-ms = <20>;
557 nvidia,repeat-delay-ms = <160>;
558 nvidia,kbc-row-pins = <0 1 2>;
559 nvidia,kbc-col-pins = <16 17>;
560 nvidia,wakeup-source;
561 linux,keymap = <0x00000074 /* KEY_POWER */
562 0x01000066 /* KEY_HOME */
563 0x0101009E /* KEY_BACK */
564 0x0201008B>; /* KEY_MENU */
565 };
566
567 regulators { 568 regulators {
568 compatible = "simple-bus"; 569 compatible = "simple-bus";
569 #address-cells = <1>; 570 #address-cells = <1>;
570 #size-cells = <0>; 571 #size-cells = <0>;
571 572
572 usb0_vbus_reg: regulator { 573 usb0_vbus_reg: regulator@0 {
573 compatible = "regulator-fixed"; 574 compatible = "regulator-fixed";
574 reg = <0>; 575 reg = <0>;
575 regulator-name = "usb0_vbus"; 576 regulator-name = "usb0_vbus";
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index c90d0aac3afe..480ecda3416b 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -1,5 +1,6 @@
1#include <dt-bindings/clock/tegra20-car.h> 1#include <dt-bindings/clock/tegra20-car.h>
2#include <dt-bindings/gpio/tegra-gpio.h> 2#include <dt-bindings/gpio/tegra-gpio.h>
3#include <dt-bindings/pinctrl/pinctrl-tegra.h>
3#include <dt-bindings/interrupt-controller/arm-gic.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h>
4 5
5#include "skeleton.dtsi" 6#include "skeleton.dtsi"
@@ -16,7 +17,7 @@
16 serial4 = &uarte; 17 serial4 = &uarte;
17 }; 18 };
18 19
19 host1x { 20 host1x@50000000 {
20 compatible = "nvidia,tegra20-host1x", "simple-bus"; 21 compatible = "nvidia,tegra20-host1x", "simple-bus";
21 reg = <0x50000000 0x00024000>; 22 reg = <0x50000000 0x00024000>;
22 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 23 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
@@ -30,7 +31,7 @@
30 31
31 ranges = <0x54000000 0x54000000 0x04000000>; 32 ranges = <0x54000000 0x54000000 0x04000000>;
32 33
33 mpe { 34 mpe@54040000 {
34 compatible = "nvidia,tegra20-mpe"; 35 compatible = "nvidia,tegra20-mpe";
35 reg = <0x54040000 0x00040000>; 36 reg = <0x54040000 0x00040000>;
36 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 37 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
@@ -39,7 +40,7 @@
39 reset-names = "mpe"; 40 reset-names = "mpe";
40 }; 41 };
41 42
42 vi { 43 vi@54080000 {
43 compatible = "nvidia,tegra20-vi"; 44 compatible = "nvidia,tegra20-vi";
44 reg = <0x54080000 0x00040000>; 45 reg = <0x54080000 0x00040000>;
45 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 46 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
@@ -48,7 +49,7 @@
48 reset-names = "vi"; 49 reset-names = "vi";
49 }; 50 };
50 51
51 epp { 52 epp@540c0000 {
52 compatible = "nvidia,tegra20-epp"; 53 compatible = "nvidia,tegra20-epp";
53 reg = <0x540c0000 0x00040000>; 54 reg = <0x540c0000 0x00040000>;
54 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 55 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
@@ -57,7 +58,7 @@
57 reset-names = "epp"; 58 reset-names = "epp";
58 }; 59 };
59 60
60 isp { 61 isp@54100000 {
61 compatible = "nvidia,tegra20-isp"; 62 compatible = "nvidia,tegra20-isp";
62 reg = <0x54100000 0x00040000>; 63 reg = <0x54100000 0x00040000>;
63 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 64 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
@@ -66,7 +67,7 @@
66 reset-names = "isp"; 67 reset-names = "isp";
67 }; 68 };
68 69
69 gr2d { 70 gr2d@54140000 {
70 compatible = "nvidia,tegra20-gr2d"; 71 compatible = "nvidia,tegra20-gr2d";
71 reg = <0x54140000 0x00040000>; 72 reg = <0x54140000 0x00040000>;
72 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 73 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
@@ -75,9 +76,9 @@
75 reset-names = "2d"; 76 reset-names = "2d";
76 }; 77 };
77 78
78 gr3d { 79 gr3d@54140000 {
79 compatible = "nvidia,tegra20-gr3d"; 80 compatible = "nvidia,tegra20-gr3d";
80 reg = <0x54180000 0x00040000>; 81 reg = <0x54140000 0x00040000>;
81 clocks = <&tegra_car TEGRA20_CLK_GR3D>; 82 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
82 resets = <&tegra_car 24>; 83 resets = <&tegra_car 24>;
83 reset-names = "3d"; 84 reset-names = "3d";
@@ -113,7 +114,7 @@
113 }; 114 };
114 }; 115 };
115 116
116 hdmi { 117 hdmi@54280000 {
117 compatible = "nvidia,tegra20-hdmi"; 118 compatible = "nvidia,tegra20-hdmi";
118 reg = <0x54280000 0x00040000>; 119 reg = <0x54280000 0x00040000>;
119 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 120 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
@@ -125,7 +126,7 @@
125 status = "disabled"; 126 status = "disabled";
126 }; 127 };
127 128
128 tvo { 129 tvo@542c0000 {
129 compatible = "nvidia,tegra20-tvo"; 130 compatible = "nvidia,tegra20-tvo";
130 reg = <0x542c0000 0x00040000>; 131 reg = <0x542c0000 0x00040000>;
131 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 132 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
@@ -133,9 +134,9 @@
133 status = "disabled"; 134 status = "disabled";
134 }; 135 };
135 136
136 dsi { 137 dsi@542c0000 {
137 compatible = "nvidia,tegra20-dsi"; 138 compatible = "nvidia,tegra20-dsi";
138 reg = <0x54300000 0x00040000>; 139 reg = <0x542c0000 0x00040000>;
139 clocks = <&tegra_car TEGRA20_CLK_DSI>; 140 clocks = <&tegra_car TEGRA20_CLK_DSI>;
140 resets = <&tegra_car 48>; 141 resets = <&tegra_car 48>;
141 reset-names = "dsi"; 142 reset-names = "dsi";
@@ -151,7 +152,7 @@
151 clocks = <&tegra_car TEGRA20_CLK_TWD>; 152 clocks = <&tegra_car TEGRA20_CLK_TWD>;
152 }; 153 };
153 154
154 intc: interrupt-controller { 155 intc: interrupt-controller@50041000 {
155 compatible = "arm,cortex-a9-gic"; 156 compatible = "arm,cortex-a9-gic";
156 reg = <0x50041000 0x1000 157 reg = <0x50041000 0x1000
157 0x50040100 0x0100>; 158 0x50040100 0x0100>;
@@ -159,7 +160,7 @@
159 #interrupt-cells = <3>; 160 #interrupt-cells = <3>;
160 }; 161 };
161 162
162 cache-controller { 163 cache-controller@50043000 {
163 compatible = "arm,pl310-cache"; 164 compatible = "arm,pl310-cache";
164 reg = <0x50043000 0x1000>; 165 reg = <0x50043000 0x1000>;
165 arm,data-latency = <5 5 2>; 166 arm,data-latency = <5 5 2>;
@@ -178,14 +179,14 @@
178 clocks = <&tegra_car TEGRA20_CLK_TIMER>; 179 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
179 }; 180 };
180 181
181 tegra_car: clock { 182 tegra_car: clock@60006000 {
182 compatible = "nvidia,tegra20-car"; 183 compatible = "nvidia,tegra20-car";
183 reg = <0x60006000 0x1000>; 184 reg = <0x60006000 0x1000>;
184 #clock-cells = <1>; 185 #clock-cells = <1>;
185 #reset-cells = <1>; 186 #reset-cells = <1>;
186 }; 187 };
187 188
188 apbdma: dma { 189 apbdma: dma@6000a000 {
189 compatible = "nvidia,tegra20-apbdma"; 190 compatible = "nvidia,tegra20-apbdma";
190 reg = <0x6000a000 0x1200>; 191 reg = <0x6000a000 0x1200>;
191 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 192 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
@@ -210,12 +211,12 @@
210 #dma-cells = <1>; 211 #dma-cells = <1>;
211 }; 212 };
212 213
213 ahb { 214 ahb@6000c004 {
214 compatible = "nvidia,tegra20-ahb"; 215 compatible = "nvidia,tegra20-ahb";
215 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */ 216 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
216 }; 217 };
217 218
218 gpio: gpio { 219 gpio: gpio@6000d000 {
219 compatible = "nvidia,tegra20-gpio"; 220 compatible = "nvidia,tegra20-gpio";
220 reg = <0x6000d000 0x1000>; 221 reg = <0x6000d000 0x1000>;
221 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 222 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
@@ -231,7 +232,7 @@
231 interrupt-controller; 232 interrupt-controller;
232 }; 233 };
233 234
234 pinmux: pinmux { 235 pinmux: pinmux@70000014 {
235 compatible = "nvidia,tegra20-pinmux"; 236 compatible = "nvidia,tegra20-pinmux";
236 reg = <0x70000014 0x10 /* Tri-state registers */ 237 reg = <0x70000014 0x10 /* Tri-state registers */
237 0x70000080 0x20 /* Mux registers */ 238 0x70000080 0x20 /* Mux registers */
@@ -239,12 +240,12 @@
239 0x70000868 0xa8>; /* Pad control registers */ 240 0x70000868 0xa8>; /* Pad control registers */
240 }; 241 };
241 242
242 das { 243 das@70000c00 {
243 compatible = "nvidia,tegra20-das"; 244 compatible = "nvidia,tegra20-das";
244 reg = <0x70000c00 0x80>; 245 reg = <0x70000c00 0x80>;
245 }; 246 };
246 247
247 tegra_ac97: ac97 { 248 tegra_ac97: ac97@70002000 {
248 compatible = "nvidia,tegra20-ac97"; 249 compatible = "nvidia,tegra20-ac97";
249 reg = <0x70002000 0x200>; 250 reg = <0x70002000 0x200>;
250 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 251 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
@@ -352,7 +353,7 @@
352 status = "disabled"; 353 status = "disabled";
353 }; 354 };
354 355
355 pwm: pwm { 356 pwm: pwm@7000a000 {
356 compatible = "nvidia,tegra20-pwm"; 357 compatible = "nvidia,tegra20-pwm";
357 reg = <0x7000a000 0x100>; 358 reg = <0x7000a000 0x100>;
358 #pwm-cells = <2>; 359 #pwm-cells = <2>;
@@ -362,7 +363,7 @@
362 status = "disabled"; 363 status = "disabled";
363 }; 364 };
364 365
365 rtc { 366 rtc@7000e000 {
366 compatible = "nvidia,tegra20-rtc"; 367 compatible = "nvidia,tegra20-rtc";
367 reg = <0x7000e000 0x100>; 368 reg = <0x7000e000 0x100>;
368 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 369 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
@@ -503,7 +504,7 @@
503 status = "disabled"; 504 status = "disabled";
504 }; 505 };
505 506
506 kbc { 507 kbc@7000e200 {
507 compatible = "nvidia,tegra20-kbc"; 508 compatible = "nvidia,tegra20-kbc";
508 reg = <0x7000e200 0x100>; 509 reg = <0x7000e200 0x100>;
509 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 510 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
@@ -513,7 +514,7 @@
513 status = "disabled"; 514 status = "disabled";
514 }; 515 };
515 516
516 pmc { 517 pmc@7000e400 {
517 compatible = "nvidia,tegra20-pmc"; 518 compatible = "nvidia,tegra20-pmc";
518 reg = <0x7000e400 0x400>; 519 reg = <0x7000e400 0x400>;
519 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>; 520 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
@@ -527,7 +528,7 @@
527 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 528 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
528 }; 529 };
529 530
530 iommu { 531 iommu@7000f024 {
531 compatible = "nvidia,tegra20-gart"; 532 compatible = "nvidia,tegra20-gart";
532 reg = <0x7000f024 0x00000018 /* controller registers */ 533 reg = <0x7000f024 0x00000018 /* controller registers */
533 0x58000000 0x02000000>; /* GART aperture */ 534 0x58000000 0x02000000>; /* GART aperture */
@@ -540,7 +541,7 @@
540 #size-cells = <0>; 541 #size-cells = <0>;
541 }; 542 };
542 543
543 pcie-controller { 544 pcie-controller@80003000 {
544 compatible = "nvidia,tegra20-pcie"; 545 compatible = "nvidia,tegra20-pcie";
545 device_type = "pci"; 546 device_type = "pci";
546 reg = <0x80003000 0x00000800 /* PADS registers */ 547 reg = <0x80003000 0x00000800 /* PADS registers */
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 08cad696e89f..7e8562a8507d 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -10,7 +10,7 @@
10 reg = <0x80000000 0x7ff00000>; 10 reg = <0x80000000 0x7ff00000>;
11 }; 11 };
12 12
13 pcie-controller { 13 pcie-controller@00003000 {
14 status = "okay"; 14 status = "okay";
15 pex-clk-supply = <&sys_3v3_pexs_reg>; 15 pex-clk-supply = <&sys_3v3_pexs_reg>;
16 vdd-supply = <&ldo1_reg>; 16 vdd-supply = <&ldo1_reg>;
@@ -31,8 +31,8 @@
31 }; 31 };
32 }; 32 };
33 33
34 host1x { 34 host1x@50000000 {
35 hdmi { 35 hdmi@54280000 {
36 status = "okay"; 36 status = "okay";
37 37
38 vdd-supply = <&sys_3v3_reg>; 38 vdd-supply = <&sys_3v3_reg>;
@@ -44,7 +44,7 @@
44 }; 44 };
45 }; 45 };
46 46
47 pinmux { 47 pinmux@70000868 {
48 pinctrl-names = "default"; 48 pinctrl-names = "default";
49 pinctrl-0 = <&state_default>; 49 pinctrl-0 = <&state_default>;
50 50
@@ -52,8 +52,8 @@
52 sdmmc1_clk_pz0 { 52 sdmmc1_clk_pz0 {
53 nvidia,pins = "sdmmc1_clk_pz0"; 53 nvidia,pins = "sdmmc1_clk_pz0";
54 nvidia,function = "sdmmc1"; 54 nvidia,function = "sdmmc1";
55 nvidia,pull = <0>; 55 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
56 nvidia,tristate = <0>; 56 nvidia,tristate = <TEGRA_PIN_DISABLE>;
57 }; 57 };
58 sdmmc1_cmd_pz1 { 58 sdmmc1_cmd_pz1 {
59 nvidia,pins = "sdmmc1_cmd_pz1", 59 nvidia,pins = "sdmmc1_cmd_pz1",
@@ -62,14 +62,14 @@
62 "sdmmc1_dat2_py5", 62 "sdmmc1_dat2_py5",
63 "sdmmc1_dat3_py4"; 63 "sdmmc1_dat3_py4";
64 nvidia,function = "sdmmc1"; 64 nvidia,function = "sdmmc1";
65 nvidia,pull = <2>; 65 nvidia,pull = <TEGRA_PIN_PULL_UP>;
66 nvidia,tristate = <0>; 66 nvidia,tristate = <TEGRA_PIN_DISABLE>;
67 }; 67 };
68 sdmmc3_clk_pa6 { 68 sdmmc3_clk_pa6 {
69 nvidia,pins = "sdmmc3_clk_pa6"; 69 nvidia,pins = "sdmmc3_clk_pa6";
70 nvidia,function = "sdmmc3"; 70 nvidia,function = "sdmmc3";
71 nvidia,pull = <0>; 71 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
72 nvidia,tristate = <0>; 72 nvidia,tristate = <TEGRA_PIN_DISABLE>;
73 }; 73 };
74 sdmmc3_cmd_pa7 { 74 sdmmc3_cmd_pa7 {
75 nvidia,pins = "sdmmc3_cmd_pa7", 75 nvidia,pins = "sdmmc3_cmd_pa7",
@@ -78,15 +78,15 @@
78 "sdmmc3_dat2_pb5", 78 "sdmmc3_dat2_pb5",
79 "sdmmc3_dat3_pb4"; 79 "sdmmc3_dat3_pb4";
80 nvidia,function = "sdmmc3"; 80 nvidia,function = "sdmmc3";
81 nvidia,pull = <2>; 81 nvidia,pull = <TEGRA_PIN_PULL_UP>;
82 nvidia,tristate = <0>; 82 nvidia,tristate = <TEGRA_PIN_DISABLE>;
83 }; 83 };
84 sdmmc4_clk_pcc4 { 84 sdmmc4_clk_pcc4 {
85 nvidia,pins = "sdmmc4_clk_pcc4", 85 nvidia,pins = "sdmmc4_clk_pcc4",
86 "sdmmc4_rst_n_pcc3"; 86 "sdmmc4_rst_n_pcc3";
87 nvidia,function = "sdmmc4"; 87 nvidia,function = "sdmmc4";
88 nvidia,pull = <0>; 88 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
89 nvidia,tristate = <0>; 89 nvidia,tristate = <TEGRA_PIN_DISABLE>;
90 }; 90 };
91 sdmmc4_dat0_paa0 { 91 sdmmc4_dat0_paa0 {
92 nvidia,pins = "sdmmc4_dat0_paa0", 92 nvidia,pins = "sdmmc4_dat0_paa0",
@@ -98,8 +98,8 @@
98 "sdmmc4_dat6_paa6", 98 "sdmmc4_dat6_paa6",
99 "sdmmc4_dat7_paa7"; 99 "sdmmc4_dat7_paa7";
100 nvidia,function = "sdmmc4"; 100 nvidia,function = "sdmmc4";
101 nvidia,pull = <2>; 101 nvidia,pull = <TEGRA_PIN_PULL_UP>;
102 nvidia,tristate = <0>; 102 nvidia,tristate = <TEGRA_PIN_DISABLE>;
103 }; 103 };
104 dap2_fs_pa2 { 104 dap2_fs_pa2 {
105 nvidia,pins = "dap2_fs_pa2", 105 nvidia,pins = "dap2_fs_pa2",
@@ -107,18 +107,18 @@
107 "dap2_din_pa4", 107 "dap2_din_pa4",
108 "dap2_dout_pa5"; 108 "dap2_dout_pa5";
109 nvidia,function = "i2s1"; 109 nvidia,function = "i2s1";
110 nvidia,pull = <0>; 110 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
111 nvidia,tristate = <0>; 111 nvidia,tristate = <TEGRA_PIN_DISABLE>;
112 }; 112 };
113 pex_l1_prsnt_n_pdd4 { 113 pex_l1_prsnt_n_pdd4 {
114 nvidia,pins = "pex_l1_prsnt_n_pdd4", 114 nvidia,pins = "pex_l1_prsnt_n_pdd4",
115 "pex_l1_clkreq_n_pdd6"; 115 "pex_l1_clkreq_n_pdd6";
116 nvidia,pull = <2>; 116 nvidia,pull = <TEGRA_PIN_PULL_UP>;
117 }; 117 };
118 sdio3 { 118 sdio3 {
119 nvidia,pins = "drive_sdio3"; 119 nvidia,pins = "drive_sdio3";
120 nvidia,high-speed-mode = <0>; 120 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
121 nvidia,schmitt = <0>; 121 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
122 nvidia,pull-down-strength = <46>; 122 nvidia,pull-down-strength = <46>;
123 nvidia,pull-up-strength = <42>; 123 nvidia,pull-up-strength = <42>;
124 nvidia,slew-rate-rising = <1>; 124 nvidia,slew-rate-rising = <1>;
@@ -159,7 +159,7 @@
159 status = "okay"; 159 status = "okay";
160 clock-frequency = <100000>; 160 clock-frequency = <100000>;
161 161
162 rt5640: rt5640 { 162 rt5640: rt5640@1c {
163 compatible = "realtek,rt5640"; 163 compatible = "realtek,rt5640";
164 reg = <0x1c>; 164 reg = <0x1c>;
165 interrupt-parent = <&gpio>; 165 interrupt-parent = <&gpio>;
@@ -168,19 +168,6 @@
168 <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>; 168 <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>;
169 }; 169 };
170 170
171 tps62361 {
172 compatible = "ti,tps62361";
173 reg = <0x60>;
174
175 regulator-name = "tps62361-vout";
176 regulator-min-microvolt = <500000>;
177 regulator-max-microvolt = <1500000>;
178 regulator-boot-on;
179 regulator-always-on;
180 ti,vsel0-state-high;
181 ti,vsel1-state-high;
182 };
183
184 pmic: tps65911@2d { 171 pmic: tps65911@2d {
185 compatible = "ti,tps65911"; 172 compatible = "ti,tps65911";
186 reg = <0x2d>; 173 reg = <0x2d>;
@@ -284,6 +271,19 @@
284 }; 271 };
285 }; 272 };
286 }; 273 };
274
275 tps62361@60 {
276 compatible = "ti,tps62361";
277 reg = <0x60>;
278
279 regulator-name = "tps62361-vout";
280 regulator-min-microvolt = <500000>;
281 regulator-max-microvolt = <1500000>;
282 regulator-boot-on;
283 regulator-always-on;
284 ti,vsel0-state-high;
285 ti,vsel1-state-high;
286 };
287 }; 287 };
288 288
289 spi@7000da00 { 289 spi@7000da00 {
@@ -296,13 +296,7 @@
296 }; 296 };
297 }; 297 };
298 298
299 ahub { 299 pmc@7000e400 {
300 i2s@70080400 {
301 status = "okay";
302 };
303 };
304
305 pmc {
306 status = "okay"; 300 status = "okay";
307 nvidia,invert-interrupt; 301 nvidia,invert-interrupt;
308 nvidia,suspend-mode = <1>; 302 nvidia,suspend-mode = <1>;
@@ -314,6 +308,12 @@
314 nvidia,sys-clock-req-active-high; 308 nvidia,sys-clock-req-active-high;
315 }; 309 };
316 310
311 ahub@70080000 {
312 i2s@70080400 {
313 status = "okay";
314 };
315 };
316
317 sdhci@78000000 { 317 sdhci@78000000 {
318 status = "okay"; 318 status = "okay";
319 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; 319 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
@@ -342,7 +342,7 @@
342 #address-cells = <1>; 342 #address-cells = <1>;
343 #size-cells = <0>; 343 #size-cells = <0>;
344 344
345 clk32k_in: clock { 345 clk32k_in: clock@0 {
346 compatible = "fixed-clock"; 346 compatible = "fixed-clock";
347 reg=<0>; 347 reg=<0>;
348 #clock-cells = <0>; 348 #clock-cells = <0>;
@@ -350,6 +350,19 @@
350 }; 350 };
351 }; 351 };
352 352
353 gpio-leds {
354 compatible = "gpio-leds";
355
356 gpled1 {
357 label = "LED1"; /* CR5A1 (blue) */
358 gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>;
359 };
360 gpled2 {
361 label = "LED2"; /* CR4A2 (green) */
362 gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>;
363 };
364 };
365
353 regulators { 366 regulators {
354 compatible = "simple-bus"; 367 compatible = "simple-bus";
355 #address-cells = <1>; 368 #address-cells = <1>;
@@ -453,19 +466,6 @@
453 }; 466 };
454 }; 467 };
455 468
456 gpio-leds {
457 compatible = "gpio-leds";
458
459 gpled1 {
460 label = "LED1"; /* CR5A1 (blue) */
461 gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>;
462 };
463 gpled2 {
464 label = "LED2"; /* CR4A2 (green) */
465 gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>;
466 };
467 };
468
469 sound { 469 sound {
470 compatible = "nvidia,tegra-audio-rt5640-beaver", 470 compatible = "nvidia,tegra-audio-rt5640-beaver",
471 "nvidia,tegra-audio-rt5640"; 471 "nvidia,tegra-audio-rt5640";
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
index 1082c5ed90d1..c9bfedcca6ed 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
@@ -8,6 +8,13 @@
8 model = "NVIDIA Tegra30 Cardhu A02 evaluation board"; 8 model = "NVIDIA Tegra30 Cardhu A02 evaluation board";
9 compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30"; 9 compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30";
10 10
11 sdhci@78000400 {
12 status = "okay";
13 power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
14 bus-width = <4>;
15 keep-power-in-suspend;
16 };
17
11 regulators { 18 regulators {
12 compatible = "simple-bus"; 19 compatible = "simple-bus";
13 #address-cells = <1>; 20 #address-cells = <1>;
@@ -83,12 +90,5 @@
83 gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>; 90 gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>;
84 }; 91 };
85 }; 92 };
86
87 sdhci@78000400 {
88 status = "okay";
89 power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
90 bus-width = <4>;
91 keep-power-in-suspend;
92 };
93}; 93};
94 94
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
index bf012bddaafb..fadf55e46b2b 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
@@ -8,6 +8,13 @@
8 model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board"; 8 model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board";
9 compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30"; 9 compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30";
10 10
11 sdhci@78000400 {
12 status = "okay";
13 power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
14 bus-width = <4>;
15 keep-power-in-suspend;
16 };
17
11 regulators { 18 regulators {
12 compatible = "simple-bus"; 19 compatible = "simple-bus";
13 #address-cells = <1>; 20 #address-cells = <1>;
@@ -95,11 +102,4 @@
95 gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>; 102 gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
96 }; 103 };
97 }; 104 };
98
99 sdhci@78000400 {
100 status = "okay";
101 power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
102 bus-width = <4>;
103 keep-power-in-suspend;
104 };
105}; 105};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 5ea7dfa4d9fa..f3aab9eb6453 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -31,7 +31,7 @@
31 reg = <0x80000000 0x40000000>; 31 reg = <0x80000000 0x40000000>;
32 }; 32 };
33 33
34 pcie-controller { 34 pcie-controller@00003000 {
35 status = "okay"; 35 status = "okay";
36 pex-clk-supply = <&pex_hvdd_3v3_reg>; 36 pex-clk-supply = <&pex_hvdd_3v3_reg>;
37 vdd-supply = <&ldo1_reg>; 37 vdd-supply = <&ldo1_reg>;
@@ -51,7 +51,7 @@
51 }; 51 };
52 }; 52 };
53 53
54 pinmux { 54 pinmux@70000868 {
55 pinctrl-names = "default"; 55 pinctrl-names = "default";
56 pinctrl-0 = <&state_default>; 56 pinctrl-0 = <&state_default>;
57 57
@@ -59,8 +59,8 @@
59 sdmmc1_clk_pz0 { 59 sdmmc1_clk_pz0 {
60 nvidia,pins = "sdmmc1_clk_pz0"; 60 nvidia,pins = "sdmmc1_clk_pz0";
61 nvidia,function = "sdmmc1"; 61 nvidia,function = "sdmmc1";
62 nvidia,pull = <0>; 62 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
63 nvidia,tristate = <0>; 63 nvidia,tristate = <TEGRA_PIN_DISABLE>;
64 }; 64 };
65 sdmmc1_cmd_pz1 { 65 sdmmc1_cmd_pz1 {
66 nvidia,pins = "sdmmc1_cmd_pz1", 66 nvidia,pins = "sdmmc1_cmd_pz1",
@@ -69,14 +69,14 @@
69 "sdmmc1_dat2_py5", 69 "sdmmc1_dat2_py5",
70 "sdmmc1_dat3_py4"; 70 "sdmmc1_dat3_py4";
71 nvidia,function = "sdmmc1"; 71 nvidia,function = "sdmmc1";
72 nvidia,pull = <2>; 72 nvidia,pull = <TEGRA_PIN_PULL_UP>;
73 nvidia,tristate = <0>; 73 nvidia,tristate = <TEGRA_PIN_DISABLE>;
74 }; 74 };
75 sdmmc3_clk_pa6 { 75 sdmmc3_clk_pa6 {
76 nvidia,pins = "sdmmc3_clk_pa6"; 76 nvidia,pins = "sdmmc3_clk_pa6";
77 nvidia,function = "sdmmc3"; 77 nvidia,function = "sdmmc3";
78 nvidia,pull = <0>; 78 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
79 nvidia,tristate = <0>; 79 nvidia,tristate = <TEGRA_PIN_DISABLE>;
80 }; 80 };
81 sdmmc3_cmd_pa7 { 81 sdmmc3_cmd_pa7 {
82 nvidia,pins = "sdmmc3_cmd_pa7", 82 nvidia,pins = "sdmmc3_cmd_pa7",
@@ -85,15 +85,15 @@
85 "sdmmc3_dat2_pb5", 85 "sdmmc3_dat2_pb5",
86 "sdmmc3_dat3_pb4"; 86 "sdmmc3_dat3_pb4";
87 nvidia,function = "sdmmc3"; 87 nvidia,function = "sdmmc3";
88 nvidia,pull = <2>; 88 nvidia,pull = <TEGRA_PIN_PULL_UP>;
89 nvidia,tristate = <0>; 89 nvidia,tristate = <TEGRA_PIN_DISABLE>;
90 }; 90 };
91 sdmmc4_clk_pcc4 { 91 sdmmc4_clk_pcc4 {
92 nvidia,pins = "sdmmc4_clk_pcc4", 92 nvidia,pins = "sdmmc4_clk_pcc4",
93 "sdmmc4_rst_n_pcc3"; 93 "sdmmc4_rst_n_pcc3";
94 nvidia,function = "sdmmc4"; 94 nvidia,function = "sdmmc4";
95 nvidia,pull = <0>; 95 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
96 nvidia,tristate = <0>; 96 nvidia,tristate = <TEGRA_PIN_DISABLE>;
97 }; 97 };
98 sdmmc4_dat0_paa0 { 98 sdmmc4_dat0_paa0 {
99 nvidia,pins = "sdmmc4_dat0_paa0", 99 nvidia,pins = "sdmmc4_dat0_paa0",
@@ -105,8 +105,8 @@
105 "sdmmc4_dat6_paa6", 105 "sdmmc4_dat6_paa6",
106 "sdmmc4_dat7_paa7"; 106 "sdmmc4_dat7_paa7";
107 nvidia,function = "sdmmc4"; 107 nvidia,function = "sdmmc4";
108 nvidia,pull = <2>; 108 nvidia,pull = <TEGRA_PIN_PULL_UP>;
109 nvidia,tristate = <0>; 109 nvidia,tristate = <TEGRA_PIN_DISABLE>;
110 }; 110 };
111 dap2_fs_pa2 { 111 dap2_fs_pa2 {
112 nvidia,pins = "dap2_fs_pa2", 112 nvidia,pins = "dap2_fs_pa2",
@@ -114,17 +114,17 @@
114 "dap2_din_pa4", 114 "dap2_din_pa4",
115 "dap2_dout_pa5"; 115 "dap2_dout_pa5";
116 nvidia,function = "i2s1"; 116 nvidia,function = "i2s1";
117 nvidia,pull = <0>; 117 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
118 nvidia,tristate = <0>; 118 nvidia,tristate = <TEGRA_PIN_DISABLE>;
119 }; 119 };
120 sdio3 { 120 sdio3 {
121 nvidia,pins = "drive_sdio3"; 121 nvidia,pins = "drive_sdio3";
122 nvidia,high-speed-mode = <0>; 122 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
123 nvidia,schmitt = <0>; 123 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
124 nvidia,pull-down-strength = <46>; 124 nvidia,pull-down-strength = <46>;
125 nvidia,pull-up-strength = <42>; 125 nvidia,pull-up-strength = <42>;
126 nvidia,slew-rate-rising = <1>; 126 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
127 nvidia,slew-rate-falling = <1>; 127 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
128 }; 128 };
129 uart3_txd_pw6 { 129 uart3_txd_pw6 {
130 nvidia,pins = "uart3_txd_pw6", 130 nvidia,pins = "uart3_txd_pw6",
@@ -132,8 +132,8 @@
132 "uart3_rts_n_pc0", 132 "uart3_rts_n_pc0",
133 "uart3_rxd_pw7"; 133 "uart3_rxd_pw7";
134 nvidia,function = "uartc"; 134 nvidia,function = "uartc";
135 nvidia,pull = <0>; 135 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
136 nvidia,tristate = <0>; 136 nvidia,tristate = <TEGRA_PIN_DISABLE>;
137 }; 137 };
138 }; 138 };
139 }; 139 };
@@ -302,7 +302,7 @@
302 interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>; 302 interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
303 }; 303 };
304 304
305 tps62361 { 305 tps62361@60 {
306 compatible = "ti,tps62361"; 306 compatible = "ti,tps62361";
307 reg = <0x60>; 307 reg = <0x60>;
308 308
@@ -326,13 +326,7 @@
326 }; 326 };
327 }; 327 };
328 328
329 ahub { 329 pmc@7000e400 {
330 i2s@70080400 {
331 status = "okay";
332 };
333 };
334
335 pmc {
336 status = "okay"; 330 status = "okay";
337 nvidia,invert-interrupt; 331 nvidia,invert-interrupt;
338 nvidia,suspend-mode = <1>; 332 nvidia,suspend-mode = <1>;
@@ -344,6 +338,12 @@
344 nvidia,sys-clock-req-active-high; 338 nvidia,sys-clock-req-active-high;
345 }; 339 };
346 340
341 ahub@70080000 {
342 i2s@70080400 {
343 status = "okay";
344 };
345 };
346
347 sdhci@78000000 { 347 sdhci@78000000 {
348 status = "okay"; 348 status = "okay";
349 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; 349 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
@@ -372,7 +372,7 @@
372 #address-cells = <1>; 372 #address-cells = <1>;
373 #size-cells = <0>; 373 #size-cells = <0>;
374 374
375 clk32k_in: clock { 375 clk32k_in: clock@0 {
376 compatible = "fixed-clock"; 376 compatible = "fixed-clock";
377 reg=<0>; 377 reg=<0>;
378 #clock-cells = <0>; 378 #clock-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 31259b09e7cc..ee5e9d8bf194 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -1,5 +1,6 @@
1#include <dt-bindings/clock/tegra30-car.h> 1#include <dt-bindings/clock/tegra30-car.h>
2#include <dt-bindings/gpio/tegra-gpio.h> 2#include <dt-bindings/gpio/tegra-gpio.h>
3#include <dt-bindings/pinctrl/pinctrl-tegra.h>
3#include <dt-bindings/interrupt-controller/arm-gic.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h>
4 5
5#include "skeleton.dtsi" 6#include "skeleton.dtsi"
@@ -16,7 +17,7 @@
16 serial4 = &uarte; 17 serial4 = &uarte;
17 }; 18 };
18 19
19 pcie-controller { 20 pcie-controller@00003000 {
20 compatible = "nvidia,tegra30-pcie"; 21 compatible = "nvidia,tegra30-pcie";
21 device_type = "pci"; 22 device_type = "pci";
22 reg = <0x00003000 0x00000800 /* PADS registers */ 23 reg = <0x00003000 0x00000800 /* PADS registers */
@@ -89,7 +90,7 @@
89 }; 90 };
90 }; 91 };
91 92
92 host1x { 93 host1x@50000000 {
93 compatible = "nvidia,tegra30-host1x", "simple-bus"; 94 compatible = "nvidia,tegra30-host1x", "simple-bus";
94 reg = <0x50000000 0x00024000>; 95 reg = <0x50000000 0x00024000>;
95 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 96 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
@@ -103,7 +104,7 @@
103 104
104 ranges = <0x54000000 0x54000000 0x04000000>; 105 ranges = <0x54000000 0x54000000 0x04000000>;
105 106
106 mpe { 107 mpe@54040000 {
107 compatible = "nvidia,tegra30-mpe"; 108 compatible = "nvidia,tegra30-mpe";
108 reg = <0x54040000 0x00040000>; 109 reg = <0x54040000 0x00040000>;
109 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 110 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
@@ -112,7 +113,7 @@
112 reset-names = "mpe"; 113 reset-names = "mpe";
113 }; 114 };
114 115
115 vi { 116 vi@54080000 {
116 compatible = "nvidia,tegra30-vi"; 117 compatible = "nvidia,tegra30-vi";
117 reg = <0x54080000 0x00040000>; 118 reg = <0x54080000 0x00040000>;
118 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 119 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
@@ -121,7 +122,7 @@
121 reset-names = "vi"; 122 reset-names = "vi";
122 }; 123 };
123 124
124 epp { 125 epp@540c0000 {
125 compatible = "nvidia,tegra30-epp"; 126 compatible = "nvidia,tegra30-epp";
126 reg = <0x540c0000 0x00040000>; 127 reg = <0x540c0000 0x00040000>;
127 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 128 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
@@ -130,7 +131,7 @@
130 reset-names = "epp"; 131 reset-names = "epp";
131 }; 132 };
132 133
133 isp { 134 isp@54100000 {
134 compatible = "nvidia,tegra30-isp"; 135 compatible = "nvidia,tegra30-isp";
135 reg = <0x54100000 0x00040000>; 136 reg = <0x54100000 0x00040000>;
136 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 137 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
@@ -139,7 +140,7 @@
139 reset-names = "isp"; 140 reset-names = "isp";
140 }; 141 };
141 142
142 gr2d { 143 gr2d@54140000 {
143 compatible = "nvidia,tegra30-gr2d"; 144 compatible = "nvidia,tegra30-gr2d";
144 reg = <0x54140000 0x00040000>; 145 reg = <0x54140000 0x00040000>;
145 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 146 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
@@ -148,7 +149,7 @@
148 clocks = <&tegra_car TEGRA30_CLK_GR2D>; 149 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
149 }; 150 };
150 151
151 gr3d { 152 gr3d@54180000 {
152 compatible = "nvidia,tegra30-gr3d"; 153 compatible = "nvidia,tegra30-gr3d";
153 reg = <0x54180000 0x00040000>; 154 reg = <0x54180000 0x00040000>;
154 clocks = <&tegra_car TEGRA30_CLK_GR3D 155 clocks = <&tegra_car TEGRA30_CLK_GR3D
@@ -189,7 +190,7 @@
189 }; 190 };
190 }; 191 };
191 192
192 hdmi { 193 hdmi@54280000 {
193 compatible = "nvidia,tegra30-hdmi"; 194 compatible = "nvidia,tegra30-hdmi";
194 reg = <0x54280000 0x00040000>; 195 reg = <0x54280000 0x00040000>;
195 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 196 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
@@ -201,7 +202,7 @@
201 status = "disabled"; 202 status = "disabled";
202 }; 203 };
203 204
204 tvo { 205 tvo@542c0000 {
205 compatible = "nvidia,tegra30-tvo"; 206 compatible = "nvidia,tegra30-tvo";
206 reg = <0x542c0000 0x00040000>; 207 reg = <0x542c0000 0x00040000>;
207 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 208 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
@@ -209,7 +210,7 @@
209 status = "disabled"; 210 status = "disabled";
210 }; 211 };
211 212
212 dsi { 213 dsi@54300000 {
213 compatible = "nvidia,tegra30-dsi"; 214 compatible = "nvidia,tegra30-dsi";
214 reg = <0x54300000 0x00040000>; 215 reg = <0x54300000 0x00040000>;
215 clocks = <&tegra_car TEGRA30_CLK_DSIA>; 216 clocks = <&tegra_car TEGRA30_CLK_DSIA>;
@@ -227,7 +228,7 @@
227 clocks = <&tegra_car TEGRA30_CLK_TWD>; 228 clocks = <&tegra_car TEGRA30_CLK_TWD>;
228 }; 229 };
229 230
230 intc: interrupt-controller { 231 intc: interrupt-controller@50041000 {
231 compatible = "arm,cortex-a9-gic"; 232 compatible = "arm,cortex-a9-gic";
232 reg = <0x50041000 0x1000 233 reg = <0x50041000 0x1000
233 0x50040100 0x0100>; 234 0x50040100 0x0100>;
@@ -235,7 +236,7 @@
235 #interrupt-cells = <3>; 236 #interrupt-cells = <3>;
236 }; 237 };
237 238
238 cache-controller { 239 cache-controller@50043000 {
239 compatible = "arm,pl310-cache"; 240 compatible = "arm,pl310-cache";
240 reg = <0x50043000 0x1000>; 241 reg = <0x50043000 0x1000>;
241 arm,data-latency = <6 6 2>; 242 arm,data-latency = <6 6 2>;
@@ -256,14 +257,14 @@
256 clocks = <&tegra_car TEGRA30_CLK_TIMER>; 257 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
257 }; 258 };
258 259
259 tegra_car: clock { 260 tegra_car: clock@60006000 {
260 compatible = "nvidia,tegra30-car"; 261 compatible = "nvidia,tegra30-car";
261 reg = <0x60006000 0x1000>; 262 reg = <0x60006000 0x1000>;
262 #clock-cells = <1>; 263 #clock-cells = <1>;
263 #reset-cells = <1>; 264 #reset-cells = <1>;
264 }; 265 };
265 266
266 apbdma: dma { 267 apbdma: dma@6000a000 {
267 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; 268 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
268 reg = <0x6000a000 0x1400>; 269 reg = <0x6000a000 0x1400>;
269 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 270 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
@@ -304,12 +305,12 @@
304 #dma-cells = <1>; 305 #dma-cells = <1>;
305 }; 306 };
306 307
307 ahb: ahb { 308 ahb: ahb@6000c004 {
308 compatible = "nvidia,tegra30-ahb"; 309 compatible = "nvidia,tegra30-ahb";
309 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */ 310 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
310 }; 311 };
311 312
312 gpio: gpio { 313 gpio: gpio@6000d000 {
313 compatible = "nvidia,tegra30-gpio"; 314 compatible = "nvidia,tegra30-gpio";
314 reg = <0x6000d000 0x1000>; 315 reg = <0x6000d000 0x1000>;
315 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 316 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
@@ -326,7 +327,7 @@
326 interrupt-controller; 327 interrupt-controller;
327 }; 328 };
328 329
329 pinmux: pinmux { 330 pinmux: pinmux@70000868 {
330 compatible = "nvidia,tegra30-pinmux"; 331 compatible = "nvidia,tegra30-pinmux";
331 reg = <0x70000868 0xd4 /* Pad control registers */ 332 reg = <0x70000868 0xd4 /* Pad control registers */
332 0x70003000 0x3e4>; /* Mux registers */ 333 0x70003000 0x3e4>; /* Mux registers */
@@ -405,7 +406,7 @@
405 status = "disabled"; 406 status = "disabled";
406 }; 407 };
407 408
408 pwm: pwm { 409 pwm: pwm@7000a000 {
409 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; 410 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
410 reg = <0x7000a000 0x100>; 411 reg = <0x7000a000 0x100>;
411 #pwm-cells = <2>; 412 #pwm-cells = <2>;
@@ -415,7 +416,7 @@
415 status = "disabled"; 416 status = "disabled";
416 }; 417 };
417 418
418 rtc { 419 rtc@7000e000 {
419 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; 420 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
420 reg = <0x7000e000 0x100>; 421 reg = <0x7000e000 0x100>;
421 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 422 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
@@ -586,7 +587,7 @@
586 status = "disabled"; 587 status = "disabled";
587 }; 588 };
588 589
589 kbc { 590 kbc@7000e200 {
590 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; 591 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
591 reg = <0x7000e200 0x100>; 592 reg = <0x7000e200 0x100>;
592 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 593 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
@@ -596,14 +597,14 @@
596 status = "disabled"; 597 status = "disabled";
597 }; 598 };
598 599
599 pmc { 600 pmc@7000e400 {
600 compatible = "nvidia,tegra30-pmc"; 601 compatible = "nvidia,tegra30-pmc";
601 reg = <0x7000e400 0x400>; 602 reg = <0x7000e400 0x400>;
602 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; 603 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
603 clock-names = "pclk", "clk32k_in"; 604 clock-names = "pclk", "clk32k_in";
604 }; 605 };
605 606
606 memory-controller { 607 memory-controller@7000f000 {
607 compatible = "nvidia,tegra30-mc"; 608 compatible = "nvidia,tegra30-mc";
608 reg = <0x7000f000 0x010 609 reg = <0x7000f000 0x010
609 0x7000f03c 0x1b4 610 0x7000f03c 0x1b4
@@ -612,7 +613,7 @@
612 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 613 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
613 }; 614 };
614 615
615 iommu { 616 iommu@7000f010 {
616 compatible = "nvidia,tegra30-smmu"; 617 compatible = "nvidia,tegra30-smmu";
617 reg = <0x7000f010 0x02c 618 reg = <0x7000f010 0x02c
618 0x7000f1f0 0x010 619 0x7000f1f0 0x010
@@ -622,7 +623,7 @@
622 nvidia,ahb = <&ahb>; 623 nvidia,ahb = <&ahb>;
623 }; 624 };
624 625
625 ahub { 626 ahub@70080000 {
626 compatible = "nvidia,tegra30-ahub"; 627 compatible = "nvidia,tegra30-ahub";
627 reg = <0x70080000 0x200 628 reg = <0x70080000 0x200
628 0x70080200 0x100>; 629 0x70080200 0x100>;
diff --git a/include/dt-bindings/gpio/tegra-gpio.h b/include/dt-bindings/gpio/tegra-gpio.h
index 4d179c00f081..197dc28b676e 100644
--- a/include/dt-bindings/gpio/tegra-gpio.h
+++ b/include/dt-bindings/gpio/tegra-gpio.h
@@ -43,6 +43,7 @@
43#define TEGRA_GPIO_BANK_ID_CC 28 43#define TEGRA_GPIO_BANK_ID_CC 28
44#define TEGRA_GPIO_BANK_ID_DD 29 44#define TEGRA_GPIO_BANK_ID_DD 29
45#define TEGRA_GPIO_BANK_ID_EE 30 45#define TEGRA_GPIO_BANK_ID_EE 30
46#define TEGRA_GPIO_BANK_ID_FF 31
46 47
47#define TEGRA_GPIO(bank, offset) \ 48#define TEGRA_GPIO(bank, offset) \
48 ((TEGRA_GPIO_BANK_ID_##bank * 8) + offset) 49 ((TEGRA_GPIO_BANK_ID_##bank * 8) + offset)
diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra.h b/include/dt-bindings/pinctrl/pinctrl-tegra.h
new file mode 100644
index 000000000000..ebafa498be0f
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-tegra.h
@@ -0,0 +1,45 @@
1/*
2 * This header provides constants for Tegra pinctrl bindings.
3 *
4 * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Author: Laxman Dewangan <ldewangan@nvidia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 */
17
18#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H
19#define _DT_BINDINGS_PINCTRL_TEGRA_H
20
21/*
22 * Enable/disable for diffeent dt properties. This is applicable for
23 * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain,
24 * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt.
25 */
26#define TEGRA_PIN_DISABLE 0
27#define TEGRA_PIN_ENABLE 1
28
29#define TEGRA_PIN_PULL_NONE 0
30#define TEGRA_PIN_PULL_DOWN 1
31#define TEGRA_PIN_PULL_UP 2
32
33/* Low power mode driver */
34#define TEGRA_PIN_LP_DRIVE_DIV_8 0
35#define TEGRA_PIN_LP_DRIVE_DIV_4 1
36#define TEGRA_PIN_LP_DRIVE_DIV_2 2
37#define TEGRA_PIN_LP_DRIVE_DIV_1 3
38
39/* Rising/Falling slew rate */
40#define TEGRA_PIN_SLEW_RATE_FASTEST 0
41#define TEGRA_PIN_SLEW_RATE_FAST 1
42#define TEGRA_PIN_SLEW_RATE_SLOW 2
43#define TEGRA_PIN_SLEW_RATE_SLOWEST 3
44
45#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-28 03:55:13 -0400