diff options
-rw-r--r-- | arch/mips/include/asm/mach-netlogic/multi-node.h | 1 | ||||
-rw-r--r-- | arch/mips/include/asm/netlogic/xlp-hal/iomap.h | 45 | ||||
-rw-r--r-- | arch/mips/netlogic/xlp/nlm_hal.c | 4 |
3 files changed, 48 insertions, 2 deletions
diff --git a/arch/mips/include/asm/mach-netlogic/multi-node.h b/arch/mips/include/asm/mach-netlogic/multi-node.h index beeb36b9f9f8..df9869d13afd 100644 --- a/arch/mips/include/asm/mach-netlogic/multi-node.h +++ b/arch/mips/include/asm/mach-netlogic/multi-node.h | |||
@@ -59,6 +59,7 @@ struct nlm_soc_info { | |||
59 | uint64_t picbase; /* PIC block base */ | 59 | uint64_t picbase; /* PIC block base */ |
60 | spinlock_t piclock; /* lock for PIC access */ | 60 | spinlock_t piclock; /* lock for PIC access */ |
61 | cpumask_t cpumask; /* logical cpu mask for node */ | 61 | cpumask_t cpumask; /* logical cpu mask for node */ |
62 | unsigned int socbus; | ||
62 | }; | 63 | }; |
63 | 64 | ||
64 | extern struct nlm_soc_info nlm_nodes[NLM_NR_NODES]; | 65 | extern struct nlm_soc_info nlm_nodes[NLM_NR_NODES]; |
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h index 55eee77adaca..92fd8669f6dd 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h | |||
@@ -48,8 +48,10 @@ | |||
48 | #define XLP_IO_SIZE (64 << 20) /* ECFG space size */ | 48 | #define XLP_IO_SIZE (64 << 20) /* ECFG space size */ |
49 | #define XLP_IO_PCI_HDRSZ 0x100 | 49 | #define XLP_IO_PCI_HDRSZ 0x100 |
50 | #define XLP_IO_DEV(node, dev) ((dev) + (node) * 8) | 50 | #define XLP_IO_DEV(node, dev) ((dev) + (node) * 8) |
51 | #define XLP_HDR_OFFSET(node, bus, dev, fn) (((bus) << 20) | \ | 51 | #define XLP_IO_PCI_OFFSET(b, d, f) (((b) << 20) | ((d) << 15) | ((f) << 12)) |
52 | ((XLP_IO_DEV(node, dev)) << 15) | ((fn) << 12)) | 52 | |
53 | #define XLP_HDR_OFFSET(node, bus, dev, fn) \ | ||
54 | XLP_IO_PCI_OFFSET(bus, XLP_IO_DEV(node, dev), fn) | ||
53 | 55 | ||
54 | #define XLP_IO_BRIDGE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 0) | 56 | #define XLP_IO_BRIDGE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 0) |
55 | /* coherent inter chip */ | 57 | /* coherent inter chip */ |
@@ -109,6 +111,36 @@ | |||
109 | #define XLP_IO_MMC_OFFSET(node, slot) \ | 111 | #define XLP_IO_MMC_OFFSET(node, slot) \ |
110 | ((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ) | 112 | ((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ) |
111 | 113 | ||
114 | /* Things have changed drastically in XLP 9XX */ | ||
115 | #define XLP9XX_HDR_OFFSET(n, d, f) \ | ||
116 | XLP_IO_PCI_OFFSET(xlp9xx_get_socbus(n), d, f) | ||
117 | |||
118 | #define XLP9XX_IO_BRIDGE_OFFSET(node) XLP_IO_PCI_OFFSET(0, 0, node) | ||
119 | #define XLP9XX_IO_PIC_OFFSET(node) XLP9XX_HDR_OFFSET(node, 2, 0) | ||
120 | #define XLP9XX_IO_UART_OFFSET(node) XLP9XX_HDR_OFFSET(node, 2, 2) | ||
121 | #define XLP9XX_IO_SYS_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 0) | ||
122 | #define XLP9XX_IO_FUSE_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 1) | ||
123 | #define XLP9XX_IO_JTAG_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 4) | ||
124 | |||
125 | #define XLP9XX_IO_PCIE_OFFSET(node, i) XLP9XX_HDR_OFFSET(node, 1, i) | ||
126 | #define XLP9XX_IO_PCIE0_OFFSET(node) XLP9XX_HDR_OFFSET(node, 1, 0) | ||
127 | #define XLP9XX_IO_PCIE2_OFFSET(node) XLP9XX_HDR_OFFSET(node, 1, 2) | ||
128 | #define XLP9XX_IO_PCIE3_OFFSET(node) XLP9XX_HDR_OFFSET(node, 1, 3) | ||
129 | |||
130 | /* XLP9xx USB block */ | ||
131 | #define XLP9XX_IO_USB_OFFSET(node, i) XLP9XX_HDR_OFFSET(node, 4, i) | ||
132 | #define XLP9XX_IO_USB_XHCI0_OFFSET(node) XLP9XX_HDR_OFFSET(node, 4, 1) | ||
133 | #define XLP9XX_IO_USB_XHCI1_OFFSET(node) XLP9XX_HDR_OFFSET(node, 4, 2) | ||
134 | |||
135 | /* XLP9XX on-chip SATA controller */ | ||
136 | #define XLP9XX_IO_SATA_OFFSET(node) XLP9XX_HDR_OFFSET(node, 3, 2) | ||
137 | |||
138 | #define XLP9XX_IO_NOR_OFFSET(node) XLP9XX_HDR_OFFSET(node, 7, 0) | ||
139 | #define XLP9XX_IO_NAND_OFFSET(node) XLP9XX_HDR_OFFSET(node, 7, 1) | ||
140 | #define XLP9XX_IO_SPI_OFFSET(node) XLP9XX_HDR_OFFSET(node, 7, 2) | ||
141 | /* SD flash */ | ||
142 | #define XLP9XX_IO_MMCSD_OFFSET(node) XLP9XX_HDR_OFFSET(node, 7, 3) | ||
143 | |||
112 | /* PCI config header register id's */ | 144 | /* PCI config header register id's */ |
113 | #define XLP_PCI_CFGREG0 0x00 | 145 | #define XLP_PCI_CFGREG0 0x00 |
114 | #define XLP_PCI_CFGREG1 0x01 | 146 | #define XLP_PCI_CFGREG1 0x01 |
@@ -161,6 +193,15 @@ | |||
161 | #define nlm_read_pci_reg(b, r) nlm_read_reg(b, r) | 193 | #define nlm_read_pci_reg(b, r) nlm_read_reg(b, r) |
162 | #define nlm_write_pci_reg(b, r, v) nlm_write_reg(b, r, v) | 194 | #define nlm_write_pci_reg(b, r, v) nlm_write_reg(b, r, v) |
163 | 195 | ||
196 | static inline int xlp9xx_get_socbus(int node) | ||
197 | { | ||
198 | uint64_t socbridge; | ||
199 | |||
200 | if (node == 0) | ||
201 | return 1; | ||
202 | socbridge = nlm_pcicfg_base(XLP9XX_IO_BRIDGE_OFFSET(node)); | ||
203 | return (nlm_read_pci_reg(socbridge, 0x6) >> 8) & 0xff; | ||
204 | } | ||
164 | #endif /* !__ASSEMBLY */ | 205 | #endif /* !__ASSEMBLY */ |
165 | 206 | ||
166 | #endif /* __NLM_HAL_IOMAP_H__ */ | 207 | #endif /* __NLM_HAL_IOMAP_H__ */ |
diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c index 56930219964b..5f191f54f9c0 100644 --- a/arch/mips/netlogic/xlp/nlm_hal.c +++ b/arch/mips/netlogic/xlp/nlm_hal.c | |||
@@ -57,6 +57,10 @@ void nlm_node_init(int node) | |||
57 | nodep->sysbase = nlm_get_sys_regbase(node); | 57 | nodep->sysbase = nlm_get_sys_regbase(node); |
58 | nodep->picbase = nlm_get_pic_regbase(node); | 58 | nodep->picbase = nlm_get_pic_regbase(node); |
59 | nodep->ebase = read_c0_ebase() & (~((1 << 12) - 1)); | 59 | nodep->ebase = read_c0_ebase() & (~((1 << 12) - 1)); |
60 | if (cpu_is_xlp9xx()) | ||
61 | nodep->socbus = xlp9xx_get_socbus(node); | ||
62 | else | ||
63 | nodep->socbus = 0; | ||
60 | spin_lock_init(&nodep->piclock); | 64 | spin_lock_init(&nodep->piclock); |
61 | } | 65 | } |
62 | 66 | ||