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-rw-r--r--arch/mips/ralink/mt7620.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
index 0018b1a661f6..ccdec5a68c18 100644
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
@@ -214,16 +214,19 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
214 214
215 switch (dram_type) { 215 switch (dram_type) {
216 case SYSCFG0_DRAM_TYPE_SDRAM: 216 case SYSCFG0_DRAM_TYPE_SDRAM:
217 pr_info("Board has SDRAM\n");
217 soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN; 218 soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
218 soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX; 219 soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
219 break; 220 break;
220 221
221 case SYSCFG0_DRAM_TYPE_DDR1: 222 case SYSCFG0_DRAM_TYPE_DDR1:
223 pr_info("Board has DDR1\n");
222 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN; 224 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
223 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX; 225 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
224 break; 226 break;
225 227
226 case SYSCFG0_DRAM_TYPE_DDR2: 228 case SYSCFG0_DRAM_TYPE_DDR2:
229 pr_info("Board has DDR2\n");
227 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN; 230 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
228 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX; 231 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
229 break; 232 break;