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-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt108
-rw-r--r--drivers/pinctrl/spear/Kconfig20
-rw-r--r--drivers/pinctrl/spear/Makefile4
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear300.c708
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear310.c431
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear320.c3468
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear3xx.c588
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear3xx.h92
8 files changed, 5419 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt
new file mode 100644
index 000000000000..3664d37e6799
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt
@@ -0,0 +1,108 @@
1ST Microelectronics, SPEAr pinmux controller
2
3Required properties:
4- compatible : "st,spear300-pinmux"
5 : "st,spear310-pinmux"
6 : "st,spear320-pinmux"
7- reg : Address range of the pinctrl registers
8- st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
9 - Its values for SPEAr300:
10 - NAND_MODE : <0>
11 - NOR_MODE : <1>
12 - PHOTO_FRAME_MODE : <2>
13 - LEND_IP_PHONE_MODE : <3>
14 - HEND_IP_PHONE_MODE : <4>
15 - LEND_WIFI_PHONE_MODE : <5>
16 - HEND_WIFI_PHONE_MODE : <6>
17 - ATA_PABX_WI2S_MODE : <7>
18 - ATA_PABX_I2S_MODE : <8>
19 - CAML_LCDW_MODE : <9>
20 - CAMU_LCD_MODE : <10>
21 - CAMU_WLCD_MODE : <11>
22 - CAML_LCD_MODE : <12>
23 - Its values for SPEAr320:
24 - AUTO_NET_SMII_MODE : <0>
25 - AUTO_NET_MII_MODE : <1>
26 - AUTO_EXP_MODE : <2>
27 - SMALL_PRINTERS_MODE : <3>
28 - EXTENDED_MODE : <4>
29
30Please refer to pinctrl-bindings.txt in this directory for details of the common
31pinctrl bindings used by client devices.
32
33SPEAr's pinmux nodes act as a container for an abitrary number of subnodes. Each
34of these subnodes represents muxing for a pin, a group, or a list of pins or
35groups.
36
37The name of each subnode is not important; all subnodes should be enumerated
38and processed purely based on their content.
39
40Required subnode-properties:
41- st,pins : An array of strings. Each string contains the name of a pin or
42 group.
43- st,function: A string containing the name of the function to mux to the pin or
44 group. See the SPEAr's TRM to determine which are valid for each pin or group.
45
46 Valid values for group and function names can be found from looking at the
47 group and function arrays in driver files:
48 drivers/pinctrl/spear/pinctrl-spear3*0.c
49
50Valid values for group names are:
51For All SPEAr3xx machines:
52 "firda_grp", "i2c0_grp", "ssp_cs_grp", "ssp0_grp", "mii0_grp",
53 "gpio0_pin0_grp", "gpio0_pin1_grp", "gpio0_pin2_grp", "gpio0_pin3_grp",
54 "gpio0_pin4_grp", "gpio0_pin5_grp", "uart0_ext_grp", "uart0_grp",
55 "timer_0_1_grp", timer_0_1_pins, "timer_2_3_grp"
56
57For SPEAr300 machines:
58 "fsmc_2chips_grp", "fsmc_4chips_grp", "clcd_lcdmode_grp",
59 "clcd_pfmode_grp", "tdm_grp", "i2c_clk_grp_grp", "caml_grp", "camu_grp",
60 "dac_grp", "i2s_grp", "sdhci_4bit_grp", "sdhci_8bit_grp",
61 "gpio1_0_to_3_grp", "gpio1_4_to_7_grp"
62
63For SPEAr310 machines:
64 "emi_cs_0_to_5_grp", "uart1_grp", "uart2_grp", "uart3_grp", "uart4_grp",
65 "uart5_grp", "fsmc_grp", "rs485_0_grp", "rs485_1_grp", "tdm_grp"
66
67For SPEAr320 machines:
68 "clcd_grp", "emi_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "spp_grp",
69 "sdhci_led_grp", "sdhci_cd_12_grp", "sdhci_cd_51_grp", "i2s_grp",
70 "uart1_grp", "uart1_modem_2_to_7_grp", "uart1_modem_31_to_36_grp",
71 "uart1_modem_34_to_45_grp", "uart1_modem_80_to_85_grp", "uart2_grp",
72 "uart3_8_9_grp", "uart3_15_16_grp", "uart3_41_42_grp",
73 "uart3_52_53_grp", "uart3_73_74_grp", "uart3_94_95_grp",
74 "uart3_98_99_grp", "uart4_6_7_grp", "uart4_13_14_grp",
75 "uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp",
76 "uart4_100_101_grp", "uart5_4_5_grp", "uart5_37_38_grp",
77 "uart5_69_70_grp", "uart5_90_91_grp", "uart6_2_3_grp",
78 "uart6_88_89_grp", "rs485_grp", "touchscreen_grp", "can0_grp",
79 "can1_grp", "pwm0_1_pin_8_9_grp", "pwm0_1_pin_14_15_grp",
80 "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp", "pwm0_1_pin_42_43_grp",
81 "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp", "pwm2_pin_7_grp",
82 "pwm2_pin_13_grp", "pwm2_pin_29_grp", "pwm2_pin_34_grp",
83 "pwm2_pin_41_grp", "pwm2_pin_58_grp", "pwm2_pin_87_grp",
84 "pwm3_pin_6_grp", "pwm3_pin_12_grp", "pwm3_pin_28_grp",
85 "pwm3_pin_40_grp", "pwm3_pin_57_grp", "pwm3_pin_86_grp",
86 "ssp1_17_20_grp", "ssp1_36_39_grp", "ssp1_48_51_grp", "ssp1_65_68_grp",
87 "ssp1_94_97_grp", "ssp2_13_16_grp", "ssp2_32_35_grp", "ssp2_44_47_grp",
88 "ssp2_61_64_grp", "ssp2_90_93_grp", "mii2_grp", "smii0_1_grp",
89 "rmii0_1_grp", "i2c1_8_9_grp", "i2c1_98_99_grp", "i2c2_0_1_grp",
90 "i2c2_2_3_grp", "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp"
91
92Valid values for function names are:
93For All SPEAr3xx machines:
94 "firda", "i2c0", "ssp_cs", "ssp0", "mii0", "gpio0", "uart0_ext",
95 "uart0", "timer_0_1", "timer_2_3"
96
97For SPEAr300 machines:
98 "fsmc", "clcd", "tdm", "i2c1", "cam", "dac", "i2s", "sdhci", "gpio1"
99
100For SPEAr310 machines:
101 "emi", "uart1", "uart2", "uart3", "uart4", "uart5", "fsmc", "rs485_0",
102 "rs485_1", "tdm"
103
104For SPEAr320 machines:
105 "clcd", "emi", "fsmc", "spp", "sdhci", "i2s", "uart1", "uart1_modem",
106 "uart2", "uart3", "uart4", "uart5", "uart6", "rs485", "touchscreen",
107 "can0", "can1", "pwm0_1", "pwm2", "pwm3", "ssp1", "ssp2", "mii2",
108 "mii0_1", "i2c1", "i2c2"
diff --git a/drivers/pinctrl/spear/Kconfig b/drivers/pinctrl/spear/Kconfig
index 47a0e2954922..6a2596b4f359 100644
--- a/drivers/pinctrl/spear/Kconfig
+++ b/drivers/pinctrl/spear/Kconfig
@@ -11,4 +11,24 @@ config PINCTRL_SPEAR
11 help 11 help
12 This enables pin control drivers for SPEAr Platform 12 This enables pin control drivers for SPEAr Platform
13 13
14config PINCTRL_SPEAR3XX
15 bool
16 depends on ARCH_SPEAR3XX
17 select PINCTRL_SPEAR
18
19config PINCTRL_SPEAR300
20 bool "ST Microelectronics SPEAr300 SoC pin controller driver"
21 depends on MACH_SPEAR300
22 select PINCTRL_SPEAR3XX
23
24config PINCTRL_SPEAR310
25 bool "ST Microelectronics SPEAr310 SoC pin controller driver"
26 depends on MACH_SPEAR310
27 select PINCTRL_SPEAR3XX
28
29config PINCTRL_SPEAR320
30 bool "ST Microelectronics SPEAr320 SoC pin controller driver"
31 depends on MACH_SPEAR320
32 select PINCTRL_SPEAR3XX
33
14endif 34endif
diff --git a/drivers/pinctrl/spear/Makefile b/drivers/pinctrl/spear/Makefile
index 69c1a51e19d3..15dcb85da22d 100644
--- a/drivers/pinctrl/spear/Makefile
+++ b/drivers/pinctrl/spear/Makefile
@@ -1,3 +1,7 @@
1# SPEAr pinmux support 1# SPEAr pinmux support
2 2
3obj-$(CONFIG_PINCTRL_SPEAR) += pinctrl-spear.o 3obj-$(CONFIG_PINCTRL_SPEAR) += pinctrl-spear.o
4obj-$(CONFIG_PINCTRL_SPEAR3XX) += pinctrl-spear3xx.o
5obj-$(CONFIG_PINCTRL_SPEAR300) += pinctrl-spear300.o
6obj-$(CONFIG_PINCTRL_SPEAR310) += pinctrl-spear310.o
7obj-$(CONFIG_PINCTRL_SPEAR320) += pinctrl-spear320.o
diff --git a/drivers/pinctrl/spear/pinctrl-spear300.c b/drivers/pinctrl/spear/pinctrl-spear300.c
new file mode 100644
index 000000000000..9c82a35e4e78
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear300.c
@@ -0,0 +1,708 @@
1/*
2 * Driver for the ST Microelectronics SPEAr300 pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/of_device.h>
16#include <linux/platform_device.h>
17#include "pinctrl-spear3xx.h"
18
19#define DRIVER_NAME "spear300-pinmux"
20
21/* addresses */
22#define PMX_CONFIG_REG 0x00
23#define MODE_CONFIG_REG 0x04
24
25/* modes */
26#define NAND_MODE (1 << 0)
27#define NOR_MODE (1 << 1)
28#define PHOTO_FRAME_MODE (1 << 2)
29#define LEND_IP_PHONE_MODE (1 << 3)
30#define HEND_IP_PHONE_MODE (1 << 4)
31#define LEND_WIFI_PHONE_MODE (1 << 5)
32#define HEND_WIFI_PHONE_MODE (1 << 6)
33#define ATA_PABX_WI2S_MODE (1 << 7)
34#define ATA_PABX_I2S_MODE (1 << 8)
35#define CAML_LCDW_MODE (1 << 9)
36#define CAMU_LCD_MODE (1 << 10)
37#define CAMU_WLCD_MODE (1 << 11)
38#define CAML_LCD_MODE (1 << 12)
39
40static struct spear_pmx_mode pmx_mode_nand = {
41 .name = "nand",
42 .mode = NAND_MODE,
43 .reg = MODE_CONFIG_REG,
44 .mask = 0x0000000F,
45 .val = 0x00,
46};
47
48static struct spear_pmx_mode pmx_mode_nor = {
49 .name = "nor",
50 .mode = NOR_MODE,
51 .reg = MODE_CONFIG_REG,
52 .mask = 0x0000000F,
53 .val = 0x01,
54};
55
56static struct spear_pmx_mode pmx_mode_photo_frame = {
57 .name = "photo frame mode",
58 .mode = PHOTO_FRAME_MODE,
59 .reg = MODE_CONFIG_REG,
60 .mask = 0x0000000F,
61 .val = 0x02,
62};
63
64static struct spear_pmx_mode pmx_mode_lend_ip_phone = {
65 .name = "lend ip phone mode",
66 .mode = LEND_IP_PHONE_MODE,
67 .reg = MODE_CONFIG_REG,
68 .mask = 0x0000000F,
69 .val = 0x03,
70};
71
72static struct spear_pmx_mode pmx_mode_hend_ip_phone = {
73 .name = "hend ip phone mode",
74 .mode = HEND_IP_PHONE_MODE,
75 .reg = MODE_CONFIG_REG,
76 .mask = 0x0000000F,
77 .val = 0x04,
78};
79
80static struct spear_pmx_mode pmx_mode_lend_wifi_phone = {
81 .name = "lend wifi phone mode",
82 .mode = LEND_WIFI_PHONE_MODE,
83 .reg = MODE_CONFIG_REG,
84 .mask = 0x0000000F,
85 .val = 0x05,
86};
87
88static struct spear_pmx_mode pmx_mode_hend_wifi_phone = {
89 .name = "hend wifi phone mode",
90 .mode = HEND_WIFI_PHONE_MODE,
91 .reg = MODE_CONFIG_REG,
92 .mask = 0x0000000F,
93 .val = 0x06,
94};
95
96static struct spear_pmx_mode pmx_mode_ata_pabx_wi2s = {
97 .name = "ata pabx wi2s mode",
98 .mode = ATA_PABX_WI2S_MODE,
99 .reg = MODE_CONFIG_REG,
100 .mask = 0x0000000F,
101 .val = 0x07,
102};
103
104static struct spear_pmx_mode pmx_mode_ata_pabx_i2s = {
105 .name = "ata pabx i2s mode",
106 .mode = ATA_PABX_I2S_MODE,
107 .reg = MODE_CONFIG_REG,
108 .mask = 0x0000000F,
109 .val = 0x08,
110};
111
112static struct spear_pmx_mode pmx_mode_caml_lcdw = {
113 .name = "caml lcdw mode",
114 .mode = CAML_LCDW_MODE,
115 .reg = MODE_CONFIG_REG,
116 .mask = 0x0000000F,
117 .val = 0x0C,
118};
119
120static struct spear_pmx_mode pmx_mode_camu_lcd = {
121 .name = "camu lcd mode",
122 .mode = CAMU_LCD_MODE,
123 .reg = MODE_CONFIG_REG,
124 .mask = 0x0000000F,
125 .val = 0x0D,
126};
127
128static struct spear_pmx_mode pmx_mode_camu_wlcd = {
129 .name = "camu wlcd mode",
130 .mode = CAMU_WLCD_MODE,
131 .reg = MODE_CONFIG_REG,
132 .mask = 0x0000000F,
133 .val = 0xE,
134};
135
136static struct spear_pmx_mode pmx_mode_caml_lcd = {
137 .name = "caml lcd mode",
138 .mode = CAML_LCD_MODE,
139 .reg = MODE_CONFIG_REG,
140 .mask = 0x0000000F,
141 .val = 0x0F,
142};
143
144static struct spear_pmx_mode *spear300_pmx_modes[] = {
145 &pmx_mode_nand,
146 &pmx_mode_nor,
147 &pmx_mode_photo_frame,
148 &pmx_mode_lend_ip_phone,
149 &pmx_mode_hend_ip_phone,
150 &pmx_mode_lend_wifi_phone,
151 &pmx_mode_hend_wifi_phone,
152 &pmx_mode_ata_pabx_wi2s,
153 &pmx_mode_ata_pabx_i2s,
154 &pmx_mode_caml_lcdw,
155 &pmx_mode_camu_lcd,
156 &pmx_mode_camu_wlcd,
157 &pmx_mode_caml_lcd,
158};
159
160/* fsmc_2chips_pins */
161static const unsigned fsmc_2chips_pins[] = { 1, 97 };
162static struct spear_muxreg fsmc_2chips_muxreg[] = {
163 {
164 .reg = PMX_CONFIG_REG,
165 .mask = PMX_FIRDA_MASK,
166 .val = 0,
167 },
168};
169
170static struct spear_modemux fsmc_2chips_modemux[] = {
171 {
172 .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
173 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
174 .muxregs = fsmc_2chips_muxreg,
175 .nmuxregs = ARRAY_SIZE(fsmc_2chips_muxreg),
176 },
177};
178
179static struct spear_pingroup fsmc_2chips_pingroup = {
180 .name = "fsmc_2chips_grp",
181 .pins = fsmc_2chips_pins,
182 .npins = ARRAY_SIZE(fsmc_2chips_pins),
183 .modemuxs = fsmc_2chips_modemux,
184 .nmodemuxs = ARRAY_SIZE(fsmc_2chips_modemux),
185};
186
187/* fsmc_4chips_pins */
188static const unsigned fsmc_4chips_pins[] = { 1, 2, 3, 97 };
189static struct spear_muxreg fsmc_4chips_muxreg[] = {
190 {
191 .reg = PMX_CONFIG_REG,
192 .mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
193 .val = 0,
194 },
195};
196
197static struct spear_modemux fsmc_4chips_modemux[] = {
198 {
199 .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
200 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
201 .muxregs = fsmc_4chips_muxreg,
202 .nmuxregs = ARRAY_SIZE(fsmc_4chips_muxreg),
203 },
204};
205
206static struct spear_pingroup fsmc_4chips_pingroup = {
207 .name = "fsmc_4chips_grp",
208 .pins = fsmc_4chips_pins,
209 .npins = ARRAY_SIZE(fsmc_4chips_pins),
210 .modemuxs = fsmc_4chips_modemux,
211 .nmodemuxs = ARRAY_SIZE(fsmc_4chips_modemux),
212};
213
214static const char *const fsmc_grps[] = { "fsmc_2chips_grp", "fsmc_4chips_grp"
215};
216static struct spear_function fsmc_function = {
217 .name = "fsmc",
218 .groups = fsmc_grps,
219 .ngroups = ARRAY_SIZE(fsmc_grps),
220};
221
222/* clcd_lcdmode_pins */
223static const unsigned clcd_lcdmode_pins[] = { 49, 50 };
224static struct spear_muxreg clcd_lcdmode_muxreg[] = {
225 {
226 .reg = PMX_CONFIG_REG,
227 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
228 .val = 0,
229 },
230};
231
232static struct spear_modemux clcd_lcdmode_modemux[] = {
233 {
234 .modes = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
235 CAMU_LCD_MODE | CAML_LCD_MODE,
236 .muxregs = clcd_lcdmode_muxreg,
237 .nmuxregs = ARRAY_SIZE(clcd_lcdmode_muxreg),
238 },
239};
240
241static struct spear_pingroup clcd_lcdmode_pingroup = {
242 .name = "clcd_lcdmode_grp",
243 .pins = clcd_lcdmode_pins,
244 .npins = ARRAY_SIZE(clcd_lcdmode_pins),
245 .modemuxs = clcd_lcdmode_modemux,
246 .nmodemuxs = ARRAY_SIZE(clcd_lcdmode_modemux),
247};
248
249/* clcd_pfmode_pins */
250static const unsigned clcd_pfmode_pins[] = { 47, 48, 49, 50 };
251static struct spear_muxreg clcd_pfmode_muxreg[] = {
252 {
253 .reg = PMX_CONFIG_REG,
254 .mask = PMX_TIMER_2_3_MASK,
255 .val = 0,
256 },
257};
258
259static struct spear_modemux clcd_pfmode_modemux[] = {
260 {
261 .modes = PHOTO_FRAME_MODE,
262 .muxregs = clcd_pfmode_muxreg,
263 .nmuxregs = ARRAY_SIZE(clcd_pfmode_muxreg),
264 },
265};
266
267static struct spear_pingroup clcd_pfmode_pingroup = {
268 .name = "clcd_pfmode_grp",
269 .pins = clcd_pfmode_pins,
270 .npins = ARRAY_SIZE(clcd_pfmode_pins),
271 .modemuxs = clcd_pfmode_modemux,
272 .nmodemuxs = ARRAY_SIZE(clcd_pfmode_modemux),
273};
274
275static const char *const clcd_grps[] = { "clcd_lcdmode_grp", "clcd_pfmode_grp"
276};
277static struct spear_function clcd_function = {
278 .name = "clcd",
279 .groups = clcd_grps,
280 .ngroups = ARRAY_SIZE(clcd_grps),
281};
282
283/* tdm_pins */
284static const unsigned tdm_pins[] = { 34, 35, 36, 37, 38 };
285static struct spear_muxreg tdm_muxreg[] = {
286 {
287 .reg = PMX_CONFIG_REG,
288 .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
289 .val = 0,
290 },
291};
292
293static struct spear_modemux tdm_modemux[] = {
294 {
295 .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
296 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
297 | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
298 | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
299 | CAMU_WLCD_MODE | CAML_LCD_MODE,
300 .muxregs = tdm_muxreg,
301 .nmuxregs = ARRAY_SIZE(tdm_muxreg),
302 },
303};
304
305static struct spear_pingroup tdm_pingroup = {
306 .name = "tdm_grp",
307 .pins = tdm_pins,
308 .npins = ARRAY_SIZE(tdm_pins),
309 .modemuxs = tdm_modemux,
310 .nmodemuxs = ARRAY_SIZE(tdm_modemux),
311};
312
313static const char *const tdm_grps[] = { "tdm_grp" };
314static struct spear_function tdm_function = {
315 .name = "tdm",
316 .groups = tdm_grps,
317 .ngroups = ARRAY_SIZE(tdm_grps),
318};
319
320/* i2c_clk_pins */
321static const unsigned i2c_clk_pins[] = { 45, 46, 47, 48 };
322static struct spear_muxreg i2c_clk_muxreg[] = {
323 {
324 .reg = PMX_CONFIG_REG,
325 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
326 .val = 0,
327 },
328};
329
330static struct spear_modemux i2c_clk_modemux[] = {
331 {
332 .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
333 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
334 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE | CAML_LCDW_MODE
335 | CAML_LCD_MODE,
336 .muxregs = i2c_clk_muxreg,
337 .nmuxregs = ARRAY_SIZE(i2c_clk_muxreg),
338 },
339};
340
341static struct spear_pingroup i2c_clk_pingroup = {
342 .name = "i2c_clk_grp_grp",
343 .pins = i2c_clk_pins,
344 .npins = ARRAY_SIZE(i2c_clk_pins),
345 .modemuxs = i2c_clk_modemux,
346 .nmodemuxs = ARRAY_SIZE(i2c_clk_modemux),
347};
348
349static const char *const i2c_grps[] = { "i2c_clk_grp" };
350static struct spear_function i2c_function = {
351 .name = "i2c1",
352 .groups = i2c_grps,
353 .ngroups = ARRAY_SIZE(i2c_grps),
354};
355
356/* caml_pins */
357static const unsigned caml_pins[] = { 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 };
358static struct spear_muxreg caml_muxreg[] = {
359 {
360 .reg = PMX_CONFIG_REG,
361 .mask = PMX_MII_MASK,
362 .val = 0,
363 },
364};
365
366static struct spear_modemux caml_modemux[] = {
367 {
368 .modes = CAML_LCDW_MODE | CAML_LCD_MODE,
369 .muxregs = caml_muxreg,
370 .nmuxregs = ARRAY_SIZE(caml_muxreg),
371 },
372};
373
374static struct spear_pingroup caml_pingroup = {
375 .name = "caml_grp",
376 .pins = caml_pins,
377 .npins = ARRAY_SIZE(caml_pins),
378 .modemuxs = caml_modemux,
379 .nmodemuxs = ARRAY_SIZE(caml_modemux),
380};
381
382/* camu_pins */
383static const unsigned camu_pins[] = { 16, 17, 18, 19, 20, 21, 45, 46, 47, 48 };
384static struct spear_muxreg camu_muxreg[] = {
385 {
386 .reg = PMX_CONFIG_REG,
387 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK | PMX_MII_MASK,
388 .val = 0,
389 },
390};
391
392static struct spear_modemux camu_modemux[] = {
393 {
394 .modes = CAMU_LCD_MODE | CAMU_WLCD_MODE,
395 .muxregs = camu_muxreg,
396 .nmuxregs = ARRAY_SIZE(camu_muxreg),
397 },
398};
399
400static struct spear_pingroup camu_pingroup = {
401 .name = "camu_grp",
402 .pins = camu_pins,
403 .npins = ARRAY_SIZE(camu_pins),
404 .modemuxs = camu_modemux,
405 .nmodemuxs = ARRAY_SIZE(camu_modemux),
406};
407
408static const char *const cam_grps[] = { "caml_grp", "camu_grp" };
409static struct spear_function cam_function = {
410 .name = "cam",
411 .groups = cam_grps,
412 .ngroups = ARRAY_SIZE(cam_grps),
413};
414
415/* dac_pins */
416static const unsigned dac_pins[] = { 43, 44 };
417static struct spear_muxreg dac_muxreg[] = {
418 {
419 .reg = PMX_CONFIG_REG,
420 .mask = PMX_TIMER_0_1_MASK,
421 .val = 0,
422 },
423};
424
425static struct spear_modemux dac_modemux[] = {
426 {
427 .modes = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
428 | CAMU_WLCD_MODE | CAML_LCD_MODE,
429 .muxregs = dac_muxreg,
430 .nmuxregs = ARRAY_SIZE(dac_muxreg),
431 },
432};
433
434static struct spear_pingroup dac_pingroup = {
435 .name = "dac_grp",
436 .pins = dac_pins,
437 .npins = ARRAY_SIZE(dac_pins),
438 .modemuxs = dac_modemux,
439 .nmodemuxs = ARRAY_SIZE(dac_modemux),
440};
441
442static const char *const dac_grps[] = { "dac_grp" };
443static struct spear_function dac_function = {
444 .name = "dac",
445 .groups = dac_grps,
446 .ngroups = ARRAY_SIZE(dac_grps),
447};
448
449/* i2s_pins */
450static const unsigned i2s_pins[] = { 39, 40, 41, 42 };
451static struct spear_muxreg i2s_muxreg[] = {
452 {
453 .reg = PMX_CONFIG_REG,
454 .mask = PMX_UART0_MODEM_MASK,
455 .val = 0,
456 },
457};
458
459static struct spear_modemux i2s_modemux[] = {
460 {
461 .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
462 | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
463 ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
464 | CAMU_WLCD_MODE | CAML_LCD_MODE,
465 .muxregs = i2s_muxreg,
466 .nmuxregs = ARRAY_SIZE(i2s_muxreg),
467 },
468};
469
470static struct spear_pingroup i2s_pingroup = {
471 .name = "i2s_grp",
472 .pins = i2s_pins,
473 .npins = ARRAY_SIZE(i2s_pins),
474 .modemuxs = i2s_modemux,
475 .nmodemuxs = ARRAY_SIZE(i2s_modemux),
476};
477
478static const char *const i2s_grps[] = { "i2s_grp" };
479static struct spear_function i2s_function = {
480 .name = "i2s",
481 .groups = i2s_grps,
482 .ngroups = ARRAY_SIZE(i2s_grps),
483};
484
485/* sdhci_4bit_pins */
486static const unsigned sdhci_4bit_pins[] = { 28, 29, 30, 31, 32, 33 };
487static struct spear_muxreg sdhci_4bit_muxreg[] = {
488 {
489 .reg = PMX_CONFIG_REG,
490 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
491 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
492 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
493 .val = 0,
494 },
495};
496
497static struct spear_modemux sdhci_4bit_modemux[] = {
498 {
499 .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
500 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
501 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
502 CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE,
503 .muxregs = sdhci_4bit_muxreg,
504 .nmuxregs = ARRAY_SIZE(sdhci_4bit_muxreg),
505 },
506};
507
508static struct spear_pingroup sdhci_4bit_pingroup = {
509 .name = "sdhci_4bit_grp",
510 .pins = sdhci_4bit_pins,
511 .npins = ARRAY_SIZE(sdhci_4bit_pins),
512 .modemuxs = sdhci_4bit_modemux,
513 .nmodemuxs = ARRAY_SIZE(sdhci_4bit_modemux),
514};
515
516/* sdhci_8bit_pins */
517static const unsigned sdhci_8bit_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32,
518 33 };
519static struct spear_muxreg sdhci_8bit_muxreg[] = {
520 {
521 .reg = PMX_CONFIG_REG,
522 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
523 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
524 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
525 .val = 0,
526 },
527};
528
529static struct spear_modemux sdhci_8bit_modemux[] = {
530 {
531 .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
532 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
533 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
534 CAMU_WLCD_MODE | CAML_LCD_MODE,
535 .muxregs = sdhci_8bit_muxreg,
536 .nmuxregs = ARRAY_SIZE(sdhci_8bit_muxreg),
537 },
538};
539
540static struct spear_pingroup sdhci_8bit_pingroup = {
541 .name = "sdhci_8bit_grp",
542 .pins = sdhci_8bit_pins,
543 .npins = ARRAY_SIZE(sdhci_8bit_pins),
544 .modemuxs = sdhci_8bit_modemux,
545 .nmodemuxs = ARRAY_SIZE(sdhci_8bit_modemux),
546};
547
548static const char *const sdhci_grps[] = { "sdhci_4bit_grp", "sdhci_8bit_grp" };
549static struct spear_function sdhci_function = {
550 .name = "sdhci",
551 .groups = sdhci_grps,
552 .ngroups = ARRAY_SIZE(sdhci_grps),
553};
554
555/* gpio1_0_to_3_pins */
556static const unsigned gpio1_0_to_3_pins[] = { 39, 40, 41, 42 };
557static struct spear_muxreg gpio1_0_to_3_muxreg[] = {
558 {
559 .reg = PMX_CONFIG_REG,
560 .mask = PMX_UART0_MODEM_MASK,
561 .val = 0,
562 },
563};
564
565static struct spear_modemux gpio1_0_to_3_modemux[] = {
566 {
567 .modes = PHOTO_FRAME_MODE,
568 .muxregs = gpio1_0_to_3_muxreg,
569 .nmuxregs = ARRAY_SIZE(gpio1_0_to_3_muxreg),
570 },
571};
572
573static struct spear_pingroup gpio1_0_to_3_pingroup = {
574 .name = "gpio1_0_to_3_grp",
575 .pins = gpio1_0_to_3_pins,
576 .npins = ARRAY_SIZE(gpio1_0_to_3_pins),
577 .modemuxs = gpio1_0_to_3_modemux,
578 .nmodemuxs = ARRAY_SIZE(gpio1_0_to_3_modemux),
579};
580
581/* gpio1_4_to_7_pins */
582static const unsigned gpio1_4_to_7_pins[] = { 43, 44, 45, 46 };
583
584static struct spear_muxreg gpio1_4_to_7_muxreg[] = {
585 {
586 .reg = PMX_CONFIG_REG,
587 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
588 .val = 0,
589 },
590};
591
592static struct spear_modemux gpio1_4_to_7_modemux[] = {
593 {
594 .modes = PHOTO_FRAME_MODE,
595 .muxregs = gpio1_4_to_7_muxreg,
596 .nmuxregs = ARRAY_SIZE(gpio1_4_to_7_muxreg),
597 },
598};
599
600static struct spear_pingroup gpio1_4_to_7_pingroup = {
601 .name = "gpio1_4_to_7_grp",
602 .pins = gpio1_4_to_7_pins,
603 .npins = ARRAY_SIZE(gpio1_4_to_7_pins),
604 .modemuxs = gpio1_4_to_7_modemux,
605 .nmodemuxs = ARRAY_SIZE(gpio1_4_to_7_modemux),
606};
607
608static const char *const gpio1_grps[] = { "gpio1_0_to_3_grp", "gpio1_4_to_7_grp"
609};
610static struct spear_function gpio1_function = {
611 .name = "gpio1",
612 .groups = gpio1_grps,
613 .ngroups = ARRAY_SIZE(gpio1_grps),
614};
615
616/* pingroups */
617static struct spear_pingroup *spear300_pingroups[] = {
618 SPEAR3XX_COMMON_PINGROUPS,
619 &fsmc_2chips_pingroup,
620 &fsmc_4chips_pingroup,
621 &clcd_lcdmode_pingroup,
622 &clcd_pfmode_pingroup,
623 &tdm_pingroup,
624 &i2c_clk_pingroup,
625 &caml_pingroup,
626 &camu_pingroup,
627 &dac_pingroup,
628 &i2s_pingroup,
629 &sdhci_4bit_pingroup,
630 &sdhci_8bit_pingroup,
631 &gpio1_0_to_3_pingroup,
632 &gpio1_4_to_7_pingroup,
633};
634
635/* functions */
636static struct spear_function *spear300_functions[] = {
637 SPEAR3XX_COMMON_FUNCTIONS,
638 &fsmc_function,
639 &clcd_function,
640 &tdm_function,
641 &i2c_function,
642 &cam_function,
643 &dac_function,
644 &i2s_function,
645 &sdhci_function,
646 &gpio1_function,
647};
648
649static struct of_device_id spear300_pinctrl_of_match[] __devinitdata = {
650 {
651 .compatible = "st,spear300-pinmux",
652 },
653 {},
654};
655
656static int __devinit spear300_pinctrl_probe(struct platform_device *pdev)
657{
658 int ret;
659
660 spear3xx_machdata.groups = spear300_pingroups;
661 spear3xx_machdata.ngroups = ARRAY_SIZE(spear300_pingroups);
662 spear3xx_machdata.functions = spear300_functions;
663 spear3xx_machdata.nfunctions = ARRAY_SIZE(spear300_functions);
664
665 spear3xx_machdata.modes_supported = true;
666 spear3xx_machdata.pmx_modes = spear300_pmx_modes;
667 spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear300_pmx_modes);
668
669 pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
670
671 ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
672 if (ret)
673 return ret;
674
675 return 0;
676}
677
678static int __devexit spear300_pinctrl_remove(struct platform_device *pdev)
679{
680 return spear_pinctrl_remove(pdev);
681}
682
683static struct platform_driver spear300_pinctrl_driver = {
684 .driver = {
685 .name = DRIVER_NAME,
686 .owner = THIS_MODULE,
687 .of_match_table = spear300_pinctrl_of_match,
688 },
689 .probe = spear300_pinctrl_probe,
690 .remove = __devexit_p(spear300_pinctrl_remove),
691};
692
693static int __init spear300_pinctrl_init(void)
694{
695 return platform_driver_register(&spear300_pinctrl_driver);
696}
697arch_initcall(spear300_pinctrl_init);
698
699static void __exit spear300_pinctrl_exit(void)
700{
701 platform_driver_unregister(&spear300_pinctrl_driver);
702}
703module_exit(spear300_pinctrl_exit);
704
705MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
706MODULE_DESCRIPTION("ST Microelectronics SPEAr300 pinctrl driver");
707MODULE_LICENSE("GPL v2");
708MODULE_DEVICE_TABLE(of, spear300_pinctrl_of_match);
diff --git a/drivers/pinctrl/spear/pinctrl-spear310.c b/drivers/pinctrl/spear/pinctrl-spear310.c
new file mode 100644
index 000000000000..1a9707605125
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear310.c
@@ -0,0 +1,431 @@
1/*
2 * Driver for the ST Microelectronics SPEAr310 pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/of_device.h>
16#include <linux/platform_device.h>
17#include "pinctrl-spear3xx.h"
18
19#define DRIVER_NAME "spear310-pinmux"
20
21/* addresses */
22#define PMX_CONFIG_REG 0x08
23
24/* emi_cs_0_to_5_pins */
25static const unsigned emi_cs_0_to_5_pins[] = { 45, 46, 47, 48, 49, 50 };
26static struct spear_muxreg emi_cs_0_to_5_muxreg[] = {
27 {
28 .reg = PMX_CONFIG_REG,
29 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
30 .val = 0,
31 },
32};
33
34static struct spear_modemux emi_cs_0_to_5_modemux[] = {
35 {
36 .muxregs = emi_cs_0_to_5_muxreg,
37 .nmuxregs = ARRAY_SIZE(emi_cs_0_to_5_muxreg),
38 },
39};
40
41static struct spear_pingroup emi_cs_0_to_5_pingroup = {
42 .name = "emi_cs_0_to_5_grp",
43 .pins = emi_cs_0_to_5_pins,
44 .npins = ARRAY_SIZE(emi_cs_0_to_5_pins),
45 .modemuxs = emi_cs_0_to_5_modemux,
46 .nmodemuxs = ARRAY_SIZE(emi_cs_0_to_5_modemux),
47};
48
49static const char *const emi_cs_0_to_5_grps[] = { "emi_cs_0_to_5_grp" };
50static struct spear_function emi_cs_0_to_5_function = {
51 .name = "emi",
52 .groups = emi_cs_0_to_5_grps,
53 .ngroups = ARRAY_SIZE(emi_cs_0_to_5_grps),
54};
55
56/* uart1_pins */
57static const unsigned uart1_pins[] = { 0, 1 };
58static struct spear_muxreg uart1_muxreg[] = {
59 {
60 .reg = PMX_CONFIG_REG,
61 .mask = PMX_FIRDA_MASK,
62 .val = 0,
63 },
64};
65
66static struct spear_modemux uart1_modemux[] = {
67 {
68 .muxregs = uart1_muxreg,
69 .nmuxregs = ARRAY_SIZE(uart1_muxreg),
70 },
71};
72
73static struct spear_pingroup uart1_pingroup = {
74 .name = "uart1_grp",
75 .pins = uart1_pins,
76 .npins = ARRAY_SIZE(uart1_pins),
77 .modemuxs = uart1_modemux,
78 .nmodemuxs = ARRAY_SIZE(uart1_modemux),
79};
80
81static const char *const uart1_grps[] = { "uart1_grp" };
82static struct spear_function uart1_function = {
83 .name = "uart1",
84 .groups = uart1_grps,
85 .ngroups = ARRAY_SIZE(uart1_grps),
86};
87
88/* uart2_pins */
89static const unsigned uart2_pins[] = { 43, 44 };
90static struct spear_muxreg uart2_muxreg[] = {
91 {
92 .reg = PMX_CONFIG_REG,
93 .mask = PMX_TIMER_0_1_MASK,
94 .val = 0,
95 },
96};
97
98static struct spear_modemux uart2_modemux[] = {
99 {
100 .muxregs = uart2_muxreg,
101 .nmuxregs = ARRAY_SIZE(uart2_muxreg),
102 },
103};
104
105static struct spear_pingroup uart2_pingroup = {
106 .name = "uart2_grp",
107 .pins = uart2_pins,
108 .npins = ARRAY_SIZE(uart2_pins),
109 .modemuxs = uart2_modemux,
110 .nmodemuxs = ARRAY_SIZE(uart2_modemux),
111};
112
113static const char *const uart2_grps[] = { "uart2_grp" };
114static struct spear_function uart2_function = {
115 .name = "uart2",
116 .groups = uart2_grps,
117 .ngroups = ARRAY_SIZE(uart2_grps),
118};
119
120/* uart3_pins */
121static const unsigned uart3_pins[] = { 37, 38 };
122static struct spear_muxreg uart3_muxreg[] = {
123 {
124 .reg = PMX_CONFIG_REG,
125 .mask = PMX_UART0_MODEM_MASK,
126 .val = 0,
127 },
128};
129
130static struct spear_modemux uart3_modemux[] = {
131 {
132 .muxregs = uart3_muxreg,
133 .nmuxregs = ARRAY_SIZE(uart3_muxreg),
134 },
135};
136
137static struct spear_pingroup uart3_pingroup = {
138 .name = "uart3_grp",
139 .pins = uart3_pins,
140 .npins = ARRAY_SIZE(uart3_pins),
141 .modemuxs = uart3_modemux,
142 .nmodemuxs = ARRAY_SIZE(uart3_modemux),
143};
144
145static const char *const uart3_grps[] = { "uart3_grp" };
146static struct spear_function uart3_function = {
147 .name = "uart3",
148 .groups = uart3_grps,
149 .ngroups = ARRAY_SIZE(uart3_grps),
150};
151
152/* uart4_pins */
153static const unsigned uart4_pins[] = { 39, 40 };
154static struct spear_muxreg uart4_muxreg[] = {
155 {
156 .reg = PMX_CONFIG_REG,
157 .mask = PMX_UART0_MODEM_MASK,
158 .val = 0,
159 },
160};
161
162static struct spear_modemux uart4_modemux[] = {
163 {
164 .muxregs = uart4_muxreg,
165 .nmuxregs = ARRAY_SIZE(uart4_muxreg),
166 },
167};
168
169static struct spear_pingroup uart4_pingroup = {
170 .name = "uart4_grp",
171 .pins = uart4_pins,
172 .npins = ARRAY_SIZE(uart4_pins),
173 .modemuxs = uart4_modemux,
174 .nmodemuxs = ARRAY_SIZE(uart4_modemux),
175};
176
177static const char *const uart4_grps[] = { "uart4_grp" };
178static struct spear_function uart4_function = {
179 .name = "uart4",
180 .groups = uart4_grps,
181 .ngroups = ARRAY_SIZE(uart4_grps),
182};
183
184/* uart5_pins */
185static const unsigned uart5_pins[] = { 41, 42 };
186static struct spear_muxreg uart5_muxreg[] = {
187 {
188 .reg = PMX_CONFIG_REG,
189 .mask = PMX_UART0_MODEM_MASK,
190 .val = 0,
191 },
192};
193
194static struct spear_modemux uart5_modemux[] = {
195 {
196 .muxregs = uart5_muxreg,
197 .nmuxregs = ARRAY_SIZE(uart5_muxreg),
198 },
199};
200
201static struct spear_pingroup uart5_pingroup = {
202 .name = "uart5_grp",
203 .pins = uart5_pins,
204 .npins = ARRAY_SIZE(uart5_pins),
205 .modemuxs = uart5_modemux,
206 .nmodemuxs = ARRAY_SIZE(uart5_modemux),
207};
208
209static const char *const uart5_grps[] = { "uart5_grp" };
210static struct spear_function uart5_function = {
211 .name = "uart5",
212 .groups = uart5_grps,
213 .ngroups = ARRAY_SIZE(uart5_grps),
214};
215
216/* fsmc_pins */
217static const unsigned fsmc_pins[] = { 34, 35, 36 };
218static struct spear_muxreg fsmc_muxreg[] = {
219 {
220 .reg = PMX_CONFIG_REG,
221 .mask = PMX_SSP_CS_MASK,
222 .val = 0,
223 },
224};
225
226static struct spear_modemux fsmc_modemux[] = {
227 {
228 .muxregs = fsmc_muxreg,
229 .nmuxregs = ARRAY_SIZE(fsmc_muxreg),
230 },
231};
232
233static struct spear_pingroup fsmc_pingroup = {
234 .name = "fsmc_grp",
235 .pins = fsmc_pins,
236 .npins = ARRAY_SIZE(fsmc_pins),
237 .modemuxs = fsmc_modemux,
238 .nmodemuxs = ARRAY_SIZE(fsmc_modemux),
239};
240
241static const char *const fsmc_grps[] = { "fsmc_grp" };
242static struct spear_function fsmc_function = {
243 .name = "fsmc",
244 .groups = fsmc_grps,
245 .ngroups = ARRAY_SIZE(fsmc_grps),
246};
247
248/* rs485_0_pins */
249static const unsigned rs485_0_pins[] = { 19, 20, 21, 22, 23 };
250static struct spear_muxreg rs485_0_muxreg[] = {
251 {
252 .reg = PMX_CONFIG_REG,
253 .mask = PMX_MII_MASK,
254 .val = 0,
255 },
256};
257
258static struct spear_modemux rs485_0_modemux[] = {
259 {
260 .muxregs = rs485_0_muxreg,
261 .nmuxregs = ARRAY_SIZE(rs485_0_muxreg),
262 },
263};
264
265static struct spear_pingroup rs485_0_pingroup = {
266 .name = "rs485_0_grp",
267 .pins = rs485_0_pins,
268 .npins = ARRAY_SIZE(rs485_0_pins),
269 .modemuxs = rs485_0_modemux,
270 .nmodemuxs = ARRAY_SIZE(rs485_0_modemux),
271};
272
273static const char *const rs485_0_grps[] = { "rs485_0" };
274static struct spear_function rs485_0_function = {
275 .name = "rs485_0",
276 .groups = rs485_0_grps,
277 .ngroups = ARRAY_SIZE(rs485_0_grps),
278};
279
280/* rs485_1_pins */
281static const unsigned rs485_1_pins[] = { 14, 15, 16, 17, 18 };
282static struct spear_muxreg rs485_1_muxreg[] = {
283 {
284 .reg = PMX_CONFIG_REG,
285 .mask = PMX_MII_MASK,
286 .val = 0,
287 },
288};
289
290static struct spear_modemux rs485_1_modemux[] = {
291 {
292 .muxregs = rs485_1_muxreg,
293 .nmuxregs = ARRAY_SIZE(rs485_1_muxreg),
294 },
295};
296
297static struct spear_pingroup rs485_1_pingroup = {
298 .name = "rs485_1_grp",
299 .pins = rs485_1_pins,
300 .npins = ARRAY_SIZE(rs485_1_pins),
301 .modemuxs = rs485_1_modemux,
302 .nmodemuxs = ARRAY_SIZE(rs485_1_modemux),
303};
304
305static const char *const rs485_1_grps[] = { "rs485_1" };
306static struct spear_function rs485_1_function = {
307 .name = "rs485_1",
308 .groups = rs485_1_grps,
309 .ngroups = ARRAY_SIZE(rs485_1_grps),
310};
311
312/* tdm_pins */
313static const unsigned tdm_pins[] = { 10, 11, 12, 13 };
314static struct spear_muxreg tdm_muxreg[] = {
315 {
316 .reg = PMX_CONFIG_REG,
317 .mask = PMX_MII_MASK,
318 .val = 0,
319 },
320};
321
322static struct spear_modemux tdm_modemux[] = {
323 {
324 .muxregs = tdm_muxreg,
325 .nmuxregs = ARRAY_SIZE(tdm_muxreg),
326 },
327};
328
329static struct spear_pingroup tdm_pingroup = {
330 .name = "tdm_grp",
331 .pins = tdm_pins,
332 .npins = ARRAY_SIZE(tdm_pins),
333 .modemuxs = tdm_modemux,
334 .nmodemuxs = ARRAY_SIZE(tdm_modemux),
335};
336
337static const char *const tdm_grps[] = { "tdm_grp" };
338static struct spear_function tdm_function = {
339 .name = "tdm",
340 .groups = tdm_grps,
341 .ngroups = ARRAY_SIZE(tdm_grps),
342};
343
344/* pingroups */
345static struct spear_pingroup *spear310_pingroups[] = {
346 SPEAR3XX_COMMON_PINGROUPS,
347 &emi_cs_0_to_5_pingroup,
348 &uart1_pingroup,
349 &uart2_pingroup,
350 &uart3_pingroup,
351 &uart4_pingroup,
352 &uart5_pingroup,
353 &fsmc_pingroup,
354 &rs485_0_pingroup,
355 &rs485_1_pingroup,
356 &tdm_pingroup,
357};
358
359/* functions */
360static struct spear_function *spear310_functions[] = {
361 SPEAR3XX_COMMON_FUNCTIONS,
362 &emi_cs_0_to_5_function,
363 &uart1_function,
364 &uart2_function,
365 &uart3_function,
366 &uart4_function,
367 &uart5_function,
368 &fsmc_function,
369 &rs485_0_function,
370 &rs485_1_function,
371 &tdm_function,
372};
373
374static struct of_device_id spear310_pinctrl_of_match[] __devinitdata = {
375 {
376 .compatible = "st,spear310-pinmux",
377 },
378 {},
379};
380
381static int __devinit spear310_pinctrl_probe(struct platform_device *pdev)
382{
383 int ret;
384
385 spear3xx_machdata.groups = spear310_pingroups;
386 spear3xx_machdata.ngroups = ARRAY_SIZE(spear310_pingroups);
387 spear3xx_machdata.functions = spear310_functions;
388 spear3xx_machdata.nfunctions = ARRAY_SIZE(spear310_functions);
389
390 pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
391
392 spear3xx_machdata.modes_supported = false;
393
394 ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
395 if (ret)
396 return ret;
397
398 return 0;
399}
400
401static int __devexit spear310_pinctrl_remove(struct platform_device *pdev)
402{
403 return spear_pinctrl_remove(pdev);
404}
405
406static struct platform_driver spear310_pinctrl_driver = {
407 .driver = {
408 .name = DRIVER_NAME,
409 .owner = THIS_MODULE,
410 .of_match_table = spear310_pinctrl_of_match,
411 },
412 .probe = spear310_pinctrl_probe,
413 .remove = __devexit_p(spear310_pinctrl_remove),
414};
415
416static int __init spear310_pinctrl_init(void)
417{
418 return platform_driver_register(&spear310_pinctrl_driver);
419}
420arch_initcall(spear310_pinctrl_init);
421
422static void __exit spear310_pinctrl_exit(void)
423{
424 platform_driver_unregister(&spear310_pinctrl_driver);
425}
426module_exit(spear310_pinctrl_exit);
427
428MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
429MODULE_DESCRIPTION("ST Microelectronics SPEAr310 pinctrl driver");
430MODULE_LICENSE("GPL v2");
431MODULE_DEVICE_TABLE(of, SPEAr310_pinctrl_of_match);
diff --git a/drivers/pinctrl/spear/pinctrl-spear320.c b/drivers/pinctrl/spear/pinctrl-spear320.c
new file mode 100644
index 000000000000..de726e6c283a
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear320.c
@@ -0,0 +1,3468 @@
1/*
2 * Driver for the ST Microelectronics SPEAr320 pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/of_device.h>
16#include <linux/platform_device.h>
17#include "pinctrl-spear3xx.h"
18
19#define DRIVER_NAME "spear320-pinmux"
20
21/* addresses */
22#define PMX_CONFIG_REG 0x0C
23#define MODE_CONFIG_REG 0x10
24#define MODE_EXT_CONFIG_REG 0x18
25
26/* modes */
27#define AUTO_NET_SMII_MODE (1 << 0)
28#define AUTO_NET_MII_MODE (1 << 1)
29#define AUTO_EXP_MODE (1 << 2)
30#define SMALL_PRINTERS_MODE (1 << 3)
31#define EXTENDED_MODE (1 << 4)
32
33static struct spear_pmx_mode pmx_mode_auto_net_smii = {
34 .name = "Automation Networking SMII mode",
35 .mode = AUTO_NET_SMII_MODE,
36 .reg = MODE_CONFIG_REG,
37 .mask = 0x00000007,
38 .val = 0x0,
39};
40
41static struct spear_pmx_mode pmx_mode_auto_net_mii = {
42 .name = "Automation Networking MII mode",
43 .mode = AUTO_NET_MII_MODE,
44 .reg = MODE_CONFIG_REG,
45 .mask = 0x00000007,
46 .val = 0x1,
47};
48
49static struct spear_pmx_mode pmx_mode_auto_exp = {
50 .name = "Automation Expanded mode",
51 .mode = AUTO_EXP_MODE,
52 .reg = MODE_CONFIG_REG,
53 .mask = 0x00000007,
54 .val = 0x2,
55};
56
57static struct spear_pmx_mode pmx_mode_small_printers = {
58 .name = "Small Printers mode",
59 .mode = SMALL_PRINTERS_MODE,
60 .reg = MODE_CONFIG_REG,
61 .mask = 0x00000007,
62 .val = 0x3,
63};
64
65static struct spear_pmx_mode pmx_mode_extended = {
66 .name = "extended mode",
67 .mode = EXTENDED_MODE,
68 .reg = MODE_EXT_CONFIG_REG,
69 .mask = 0x00000001,
70 .val = 0x1,
71};
72
73static struct spear_pmx_mode *spear320_pmx_modes[] = {
74 &pmx_mode_auto_net_smii,
75 &pmx_mode_auto_net_mii,
76 &pmx_mode_auto_exp,
77 &pmx_mode_small_printers,
78 &pmx_mode_extended,
79};
80
81/* Extended mode registers and their offsets */
82#define EXT_CTRL_REG 0x0018
83 #define MII_MDIO_MASK (1 << 4)
84 #define MII_MDIO_10_11_VAL 0
85 #define MII_MDIO_81_VAL (1 << 4)
86 #define EMI_FSMC_DYNAMIC_MUX_MASK (1 << 5)
87 #define MAC_MODE_MII 0
88 #define MAC_MODE_RMII 1
89 #define MAC_MODE_SMII 2
90 #define MAC_MODE_SS_SMII 3
91 #define MAC_MODE_MASK 0x3
92 #define MAC1_MODE_SHIFT 16
93 #define MAC2_MODE_SHIFT 18
94
95#define IP_SEL_PAD_0_9_REG 0x00A4
96 #define PMX_PL_0_1_MASK (0x3F << 0)
97 #define PMX_UART2_PL_0_1_VAL 0x0
98 #define PMX_I2C2_PL_0_1_VAL (0x4 | (0x4 << 3))
99
100 #define PMX_PL_2_3_MASK (0x3F << 6)
101 #define PMX_I2C2_PL_2_3_VAL 0x0
102 #define PMX_UART6_PL_2_3_VAL ((0x1 << 6) | (0x1 << 9))
103 #define PMX_UART1_ENH_PL_2_3_VAL ((0x4 << 6) | (0x4 << 9))
104
105 #define PMX_PL_4_5_MASK (0x3F << 12)
106 #define PMX_UART5_PL_4_5_VAL ((0x1 << 12) | (0x1 << 15))
107 #define PMX_UART1_ENH_PL_4_5_VAL ((0x4 << 12) | (0x4 << 15))
108 #define PMX_PL_5_MASK (0x7 << 15)
109 #define PMX_TOUCH_Y_PL_5_VAL 0x0
110
111 #define PMX_PL_6_7_MASK (0x3F << 18)
112 #define PMX_PL_6_MASK (0x7 << 18)
113 #define PMX_PL_7_MASK (0x7 << 21)
114 #define PMX_UART4_PL_6_7_VAL ((0x1 << 18) | (0x1 << 21))
115 #define PMX_PWM_3_PL_6_VAL (0x2 << 18)
116 #define PMX_PWM_2_PL_7_VAL (0x2 << 21)
117 #define PMX_UART1_ENH_PL_6_7_VAL ((0x4 << 18) | (0x4 << 21))
118
119 #define PMX_PL_8_9_MASK (0x3F << 24)
120 #define PMX_UART3_PL_8_9_VAL ((0x1 << 24) | (0x1 << 27))
121 #define PMX_PWM_0_1_PL_8_9_VAL ((0x2 << 24) | (0x2 << 27))
122 #define PMX_I2C1_PL_8_9_VAL ((0x4 << 24) | (0x4 << 27))
123
124#define IP_SEL_PAD_10_19_REG 0x00A8
125 #define PMX_PL_10_11_MASK (0x3F << 0)
126 #define PMX_SMII_PL_10_11_VAL 0
127 #define PMX_RMII_PL_10_11_VAL ((0x4 << 0) | (0x4 << 3))
128
129 #define PMX_PL_12_MASK (0x7 << 6)
130 #define PMX_PWM3_PL_12_VAL 0
131 #define PMX_SDHCI_CD_PL_12_VAL (0x4 << 6)
132
133 #define PMX_PL_13_14_MASK (0x3F << 9)
134 #define PMX_PL_13_MASK (0x7 << 9)
135 #define PMX_PL_14_MASK (0x7 << 12)
136 #define PMX_SSP2_PL_13_14_15_16_VAL 0
137 #define PMX_UART4_PL_13_14_VAL ((0x1 << 9) | (0x1 << 12))
138 #define PMX_RMII_PL_13_14_VAL ((0x4 << 9) | (0x4 << 12))
139 #define PMX_PWM2_PL_13_VAL (0x2 << 9)
140 #define PMX_PWM1_PL_14_VAL (0x2 << 12)
141
142 #define PMX_PL_15_MASK (0x7 << 15)
143 #define PMX_PWM0_PL_15_VAL (0x2 << 15)
144 #define PMX_PL_15_16_MASK (0x3F << 15)
145 #define PMX_UART3_PL_15_16_VAL ((0x1 << 15) | (0x1 << 18))
146 #define PMX_RMII_PL_15_16_VAL ((0x4 << 15) | (0x4 << 18))
147
148 #define PMX_PL_17_18_MASK (0x3F << 21)
149 #define PMX_SSP1_PL_17_18_19_20_VAL 0
150 #define PMX_RMII_PL_17_18_VAL ((0x4 << 21) | (0x4 << 24))
151
152 #define PMX_PL_19_MASK (0x7 << 27)
153 #define PMX_I2C2_PL_19_VAL (0x1 << 27)
154 #define PMX_RMII_PL_19_VAL (0x4 << 27)
155
156#define IP_SEL_PAD_20_29_REG 0x00AC
157 #define PMX_PL_20_MASK (0x7 << 0)
158 #define PMX_I2C2_PL_20_VAL (0x1 << 0)
159 #define PMX_RMII_PL_20_VAL (0x4 << 0)
160
161 #define PMX_PL_21_TO_27_MASK (0x1FFFFF << 3)
162 #define PMX_SMII_PL_21_TO_27_VAL 0
163 #define PMX_RMII_PL_21_TO_27_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15) | (0x4 << 18) | (0x4 << 21))
164
165 #define PMX_PL_28_29_MASK (0x3F << 24)
166 #define PMX_PL_28_MASK (0x7 << 24)
167 #define PMX_PL_29_MASK (0x7 << 27)
168 #define PMX_UART1_PL_28_29_VAL 0
169 #define PMX_PWM_3_PL_28_VAL (0x4 << 24)
170 #define PMX_PWM_2_PL_29_VAL (0x4 << 27)
171
172#define IP_SEL_PAD_30_39_REG 0x00B0
173 #define PMX_PL_30_31_MASK (0x3F << 0)
174 #define PMX_CAN1_PL_30_31_VAL (0)
175 #define PMX_PL_30_MASK (0x7 << 0)
176 #define PMX_PL_31_MASK (0x7 << 3)
177 #define PMX_PWM1_EXT_PL_30_VAL (0x4 << 0)
178 #define PMX_PWM0_EXT_PL_31_VAL (0x4 << 3)
179 #define PMX_UART1_ENH_PL_31_VAL (0x3 << 3)
180
181 #define PMX_PL_32_33_MASK (0x3F << 6)
182 #define PMX_CAN0_PL_32_33_VAL 0
183 #define PMX_UART1_ENH_PL_32_33_VAL ((0x3 << 6) | (0x3 << 9))
184 #define PMX_SSP2_PL_32_33_VAL ((0x4 << 6) | (0x4 << 9))
185
186 #define PMX_PL_34_MASK (0x7 << 12)
187 #define PMX_PWM2_PL_34_VAL 0
188 #define PMX_UART1_ENH_PL_34_VAL (0x2 << 12)
189 #define PMX_SSP2_PL_34_VAL (0x4 << 12)
190
191 #define PMX_PL_35_MASK (0x7 << 15)
192 #define PMX_I2S_REF_CLK_PL_35_VAL 0
193 #define PMX_UART1_ENH_PL_35_VAL (0x2 << 15)
194 #define PMX_SSP2_PL_35_VAL (0x4 << 15)
195
196 #define PMX_PL_36_MASK (0x7 << 18)
197 #define PMX_TOUCH_X_PL_36_VAL 0
198 #define PMX_UART1_ENH_PL_36_VAL (0x2 << 18)
199 #define PMX_SSP1_PL_36_VAL (0x4 << 18)
200
201 #define PMX_PL_37_38_MASK (0x3F << 21)
202 #define PMX_PWM0_1_PL_37_38_VAL 0
203 #define PMX_UART5_PL_37_38_VAL ((0x2 << 21) | (0x2 << 24))
204 #define PMX_SSP1_PL_37_38_VAL ((0x4 << 21) | (0x4 << 24))
205
206 #define PMX_PL_39_MASK (0x7 << 27)
207 #define PMX_I2S_PL_39_VAL 0
208 #define PMX_UART4_PL_39_VAL (0x2 << 27)
209 #define PMX_SSP1_PL_39_VAL (0x4 << 27)
210
211#define IP_SEL_PAD_40_49_REG 0x00B4
212 #define PMX_PL_40_MASK (0x7 << 0)
213 #define PMX_I2S_PL_40_VAL 0
214 #define PMX_UART4_PL_40_VAL (0x2 << 0)
215 #define PMX_PWM3_PL_40_VAL (0x4 << 0)
216
217 #define PMX_PL_41_42_MASK (0x3F << 3)
218 #define PMX_PL_41_MASK (0x7 << 3)
219 #define PMX_PL_42_MASK (0x7 << 6)
220 #define PMX_I2S_PL_41_42_VAL 0
221 #define PMX_UART3_PL_41_42_VAL ((0x2 << 3) | (0x2 << 6))
222 #define PMX_PWM2_PL_41_VAL (0x4 << 3)
223 #define PMX_PWM1_PL_42_VAL (0x4 << 6)
224
225 #define PMX_PL_43_MASK (0x7 << 9)
226 #define PMX_SDHCI_PL_43_VAL 0
227 #define PMX_UART1_ENH_PL_43_VAL (0x2 << 9)
228 #define PMX_PWM0_PL_43_VAL (0x4 << 9)
229
230 #define PMX_PL_44_45_MASK (0x3F << 12)
231 #define PMX_SDHCI_PL_44_45_VAL 0
232 #define PMX_UART1_ENH_PL_44_45_VAL ((0x2 << 12) | (0x2 << 15))
233 #define PMX_SSP2_PL_44_45_VAL ((0x4 << 12) | (0x4 << 15))
234
235 #define PMX_PL_46_47_MASK (0x3F << 18)
236 #define PMX_SDHCI_PL_46_47_VAL 0
237 #define PMX_FSMC_EMI_PL_46_47_VAL ((0x2 << 18) | (0x2 << 21))
238 #define PMX_SSP2_PL_46_47_VAL ((0x4 << 18) | (0x4 << 21))
239
240 #define PMX_PL_48_49_MASK (0x3F << 24)
241 #define PMX_SDHCI_PL_48_49_VAL 0
242 #define PMX_FSMC_EMI_PL_48_49_VAL ((0x2 << 24) | (0x2 << 27))
243 #define PMX_SSP1_PL_48_49_VAL ((0x4 << 24) | (0x4 << 27))
244
245#define IP_SEL_PAD_50_59_REG 0x00B8
246 #define PMX_PL_50_51_MASK (0x3F << 0)
247 #define PMX_EMI_PL_50_51_VAL ((0x2 << 0) | (0x2 << 3))
248 #define PMX_SSP1_PL_50_51_VAL ((0x4 << 0) | (0x4 << 3))
249 #define PMX_PL_50_MASK (0x7 << 0)
250 #define PMX_PL_51_MASK (0x7 << 3)
251 #define PMX_SDHCI_PL_50_VAL 0
252 #define PMX_SDHCI_CD_PL_51_VAL 0
253
254 #define PMX_PL_52_53_MASK (0x3F << 6)
255 #define PMX_FSMC_PL_52_53_VAL 0
256 #define PMX_EMI_PL_52_53_VAL ((0x2 << 6) | (0x2 << 9))
257 #define PMX_UART3_PL_52_53_VAL ((0x4 << 6) | (0x4 << 9))
258
259 #define PMX_PL_54_55_56_MASK (0x1FF << 12)
260 #define PMX_FSMC_EMI_PL_54_55_56_VAL ((0x2 << 12) | (0x2 << 15) | (0x2 << 18))
261
262 #define PMX_PL_57_MASK (0x7 << 21)
263 #define PMX_FSMC_PL_57_VAL 0
264 #define PMX_PWM3_PL_57_VAL (0x4 << 21)
265
266 #define PMX_PL_58_59_MASK (0x3F << 24)
267 #define PMX_PL_58_MASK (0x7 << 24)
268 #define PMX_PL_59_MASK (0x7 << 27)
269 #define PMX_FSMC_EMI_PL_58_59_VAL ((0x2 << 24) | (0x2 << 27))
270 #define PMX_PWM2_PL_58_VAL (0x4 << 24)
271 #define PMX_PWM1_PL_59_VAL (0x4 << 27)
272
273#define IP_SEL_PAD_60_69_REG 0x00BC
274 #define PMX_PL_60_MASK (0x7 << 0)
275 #define PMX_FSMC_PL_60_VAL 0
276 #define PMX_PWM0_PL_60_VAL (0x4 << 0)
277
278 #define PMX_PL_61_TO_64_MASK (0xFFF << 3)
279 #define PMX_FSMC_PL_61_TO_64_VAL ((0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12))
280 #define PMX_SSP2_PL_61_TO_64_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12))
281
282 #define PMX_PL_65_TO_68_MASK (0xFFF << 15)
283 #define PMX_FSMC_PL_65_TO_68_VAL ((0x2 << 15) | (0x2 << 18) | (0x2 << 21) | (0x2 << 24))
284 #define PMX_SSP1_PL_65_TO_68_VAL ((0x4 << 15) | (0x4 << 18) | (0x4 << 21) | (0x4 << 24))
285
286 #define PMX_PL_69_MASK (0x7 << 27)
287 #define PMX_CLCD_PL_69_VAL (0)
288 #define PMX_EMI_PL_69_VAL (0x2 << 27)
289 #define PMX_SPP_PL_69_VAL (0x3 << 27)
290 #define PMX_UART5_PL_69_VAL (0x4 << 27)
291
292#define IP_SEL_PAD_70_79_REG 0x00C0
293 #define PMX_PL_70_MASK (0x7 << 0)
294 #define PMX_CLCD_PL_70_VAL (0)
295 #define PMX_FSMC_EMI_PL_70_VAL (0x2 << 0)
296 #define PMX_SPP_PL_70_VAL (0x3 << 0)
297 #define PMX_UART5_PL_70_VAL (0x4 << 0)
298
299 #define PMX_PL_71_72_MASK (0x3F << 3)
300 #define PMX_CLCD_PL_71_72_VAL (0)
301 #define PMX_FSMC_EMI_PL_71_72_VAL ((0x2 << 3) | (0x2 << 6))
302 #define PMX_SPP_PL_71_72_VAL ((0x3 << 3) | (0x3 << 6))
303 #define PMX_UART4_PL_71_72_VAL ((0x4 << 3) | (0x4 << 6))
304
305 #define PMX_PL_73_MASK (0x7 << 9)
306 #define PMX_CLCD_PL_73_VAL (0)
307 #define PMX_FSMC_EMI_PL_73_VAL (0x2 << 9)
308 #define PMX_SPP_PL_73_VAL (0x3 << 9)
309 #define PMX_UART3_PL_73_VAL (0x4 << 9)
310
311 #define PMX_PL_74_MASK (0x7 << 12)
312 #define PMX_CLCD_PL_74_VAL (0)
313 #define PMX_EMI_PL_74_VAL (0x2 << 12)
314 #define PMX_SPP_PL_74_VAL (0x3 << 12)
315 #define PMX_UART3_PL_74_VAL (0x4 << 12)
316
317 #define PMX_PL_75_76_MASK (0x3F << 15)
318 #define PMX_CLCD_PL_75_76_VAL (0)
319 #define PMX_EMI_PL_75_76_VAL ((0x2 << 15) | (0x2 << 18))
320 #define PMX_SPP_PL_75_76_VAL ((0x3 << 15) | (0x3 << 18))
321 #define PMX_I2C2_PL_75_76_VAL ((0x4 << 15) | (0x4 << 18))
322
323 #define PMX_PL_77_78_79_MASK (0x1FF << 21)
324 #define PMX_CLCD_PL_77_78_79_VAL (0)
325 #define PMX_EMI_PL_77_78_79_VAL ((0x2 << 21) | (0x2 << 24) | (0x2 << 27))
326 #define PMX_SPP_PL_77_78_79_VAL ((0x3 << 21) | (0x3 << 24) | (0x3 << 27))
327 #define PMX_RS485_PL_77_78_79_VAL ((0x4 << 21) | (0x4 << 24) | (0x4 << 27))
328
329#define IP_SEL_PAD_80_89_REG 0x00C4
330 #define PMX_PL_80_TO_85_MASK (0x3FFFF << 0)
331 #define PMX_CLCD_PL_80_TO_85_VAL 0
332 #define PMX_MII2_PL_80_TO_85_VAL ((0x1 << 0) | (0x1 << 3) | (0x1 << 6) | (0x1 << 9) | (0x1 << 12) | (0x1 << 15))
333 #define PMX_EMI_PL_80_TO_85_VAL ((0x2 << 0) | (0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12) | (0x2 << 15))
334 #define PMX_SPP_PL_80_TO_85_VAL ((0x3 << 0) | (0x3 << 3) | (0x3 << 6) | (0x3 << 9) | (0x3 << 12) | (0x3 << 15))
335 #define PMX_UART1_ENH_PL_80_TO_85_VAL ((0x4 << 0) | (0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15))
336
337 #define PMX_PL_86_87_MASK (0x3F << 18)
338 #define PMX_PL_86_MASK (0x7 << 18)
339 #define PMX_PL_87_MASK (0x7 << 21)
340 #define PMX_CLCD_PL_86_87_VAL 0
341 #define PMX_MII2_PL_86_87_VAL ((0x1 << 18) | (0x1 << 21))
342 #define PMX_EMI_PL_86_87_VAL ((0x2 << 18) | (0x2 << 21))
343 #define PMX_PWM3_PL_86_VAL (0x4 << 18)
344 #define PMX_PWM2_PL_87_VAL (0x4 << 21)
345
346 #define PMX_PL_88_89_MASK (0x3F << 24)
347 #define PMX_CLCD_PL_88_89_VAL 0
348 #define PMX_MII2_PL_88_89_VAL ((0x1 << 24) | (0x1 << 27))
349 #define PMX_EMI_PL_88_89_VAL ((0x2 << 24) | (0x2 << 27))
350 #define PMX_UART6_PL_88_89_VAL ((0x3 << 24) | (0x3 << 27))
351 #define PMX_PWM0_1_PL_88_89_VAL ((0x4 << 24) | (0x4 << 27))
352
353#define IP_SEL_PAD_90_99_REG 0x00C8
354 #define PMX_PL_90_91_MASK (0x3F << 0)
355 #define PMX_CLCD_PL_90_91_VAL 0
356 #define PMX_MII2_PL_90_91_VAL ((0x1 << 0) | (0x1 << 3))
357 #define PMX_EMI1_PL_90_91_VAL ((0x2 << 0) | (0x2 << 3))
358 #define PMX_UART5_PL_90_91_VAL ((0x3 << 0) | (0x3 << 3))
359 #define PMX_SSP2_PL_90_91_VAL ((0x4 << 0) | (0x4 << 3))
360
361 #define PMX_PL_92_93_MASK (0x3F << 6)
362 #define PMX_CLCD_PL_92_93_VAL 0
363 #define PMX_MII2_PL_92_93_VAL ((0x1 << 6) | (0x1 << 9))
364 #define PMX_EMI1_PL_92_93_VAL ((0x2 << 6) | (0x2 << 9))
365 #define PMX_UART4_PL_92_93_VAL ((0x3 << 6) | (0x3 << 9))
366 #define PMX_SSP2_PL_92_93_VAL ((0x4 << 6) | (0x4 << 9))
367
368 #define PMX_PL_94_95_MASK (0x3F << 12)
369 #define PMX_CLCD_PL_94_95_VAL 0
370 #define PMX_MII2_PL_94_95_VAL ((0x1 << 12) | (0x1 << 15))
371 #define PMX_EMI1_PL_94_95_VAL ((0x2 << 12) | (0x2 << 15))
372 #define PMX_UART3_PL_94_95_VAL ((0x3 << 12) | (0x3 << 15))
373 #define PMX_SSP1_PL_94_95_VAL ((0x4 << 12) | (0x4 << 15))
374
375 #define PMX_PL_96_97_MASK (0x3F << 18)
376 #define PMX_CLCD_PL_96_97_VAL 0
377 #define PMX_MII2_PL_96_97_VAL ((0x1 << 18) | (0x1 << 21))
378 #define PMX_EMI1_PL_96_97_VAL ((0x2 << 18) | (0x2 << 21))
379 #define PMX_I2C2_PL_96_97_VAL ((0x3 << 18) | (0x3 << 21))
380 #define PMX_SSP1_PL_96_97_VAL ((0x4 << 18) | (0x4 << 21))
381
382 #define PMX_PL_98_MASK (0x7 << 24)
383 #define PMX_CLCD_PL_98_VAL 0
384 #define PMX_I2C1_PL_98_VAL (0x2 << 24)
385 #define PMX_UART3_PL_98_VAL (0x4 << 24)
386
387 #define PMX_PL_99_MASK (0x7 << 27)
388 #define PMX_SDHCI_PL_99_VAL 0
389 #define PMX_I2C1_PL_99_VAL (0x2 << 27)
390 #define PMX_UART3_PL_99_VAL (0x4 << 27)
391
392#define IP_SEL_MIX_PAD_REG 0x00CC
393 #define PMX_PL_100_101_MASK (0x3F << 0)
394 #define PMX_SDHCI_PL_100_101_VAL 0
395 #define PMX_UART4_PL_100_101_VAL ((0x4 << 0) | (0x4 << 3))
396
397 #define PMX_SSP1_PORT_SEL_MASK (0x7 << 8)
398 #define PMX_SSP1_PORT_94_TO_97_VAL 0
399 #define PMX_SSP1_PORT_65_TO_68_VAL (0x1 << 8)
400 #define PMX_SSP1_PORT_48_TO_51_VAL (0x2 << 8)
401 #define PMX_SSP1_PORT_36_TO_39_VAL (0x3 << 8)
402 #define PMX_SSP1_PORT_17_TO_20_VAL (0x4 << 8)
403
404 #define PMX_SSP2_PORT_SEL_MASK (0x7 << 11)
405 #define PMX_SSP2_PORT_90_TO_93_VAL 0
406 #define PMX_SSP2_PORT_61_TO_64_VAL (0x1 << 11)
407 #define PMX_SSP2_PORT_44_TO_47_VAL (0x2 << 11)
408 #define PMX_SSP2_PORT_32_TO_35_VAL (0x3 << 11)
409 #define PMX_SSP2_PORT_13_TO_16_VAL (0x4 << 11)
410
411 #define PMX_UART1_ENH_PORT_SEL_MASK (0x3 << 14)
412 #define PMX_UART1_ENH_PORT_81_TO_85_VAL 0
413 #define PMX_UART1_ENH_PORT_44_45_34_36_VAL (0x1 << 14)
414 #define PMX_UART1_ENH_PORT_32_TO_34_36_VAL (0x2 << 14)
415 #define PMX_UART1_ENH_PORT_3_TO_5_7_VAL (0x3 << 14)
416
417 #define PMX_UART3_PORT_SEL_MASK (0x7 << 16)
418 #define PMX_UART3_PORT_94_VAL 0
419 #define PMX_UART3_PORT_73_VAL (0x1 << 16)
420 #define PMX_UART3_PORT_52_VAL (0x2 << 16)
421 #define PMX_UART3_PORT_41_VAL (0x3 << 16)
422 #define PMX_UART3_PORT_15_VAL (0x4 << 16)
423 #define PMX_UART3_PORT_8_VAL (0x5 << 16)
424 #define PMX_UART3_PORT_99_VAL (0x6 << 16)
425
426 #define PMX_UART4_PORT_SEL_MASK (0x7 << 19)
427 #define PMX_UART4_PORT_92_VAL 0
428 #define PMX_UART4_PORT_71_VAL (0x1 << 19)
429 #define PMX_UART4_PORT_39_VAL (0x2 << 19)
430 #define PMX_UART4_PORT_13_VAL (0x3 << 19)
431 #define PMX_UART4_PORT_6_VAL (0x4 << 19)
432 #define PMX_UART4_PORT_101_VAL (0x5 << 19)
433
434 #define PMX_UART5_PORT_SEL_MASK (0x3 << 22)
435 #define PMX_UART5_PORT_90_VAL 0
436 #define PMX_UART5_PORT_69_VAL (0x1 << 22)
437 #define PMX_UART5_PORT_37_VAL (0x2 << 22)
438 #define PMX_UART5_PORT_4_VAL (0x3 << 22)
439
440 #define PMX_UART6_PORT_SEL_MASK (0x1 << 24)
441 #define PMX_UART6_PORT_88_VAL 0
442 #define PMX_UART6_PORT_2_VAL (0x1 << 24)
443
444 #define PMX_I2C1_PORT_SEL_MASK (0x1 << 25)
445 #define PMX_I2C1_PORT_8_9_VAL 0
446 #define PMX_I2C1_PORT_98_99_VAL (0x1 << 25)
447
448 #define PMX_I2C2_PORT_SEL_MASK (0x3 << 26)
449 #define PMX_I2C2_PORT_96_97_VAL 0
450 #define PMX_I2C2_PORT_75_76_VAL (0x1 << 26)
451 #define PMX_I2C2_PORT_19_20_VAL (0x2 << 26)
452 #define PMX_I2C2_PORT_2_3_VAL (0x3 << 26)
453 #define PMX_I2C2_PORT_0_1_VAL (0x4 << 26)
454
455 #define PMX_SDHCI_CD_PORT_SEL_MASK (0x1 << 29)
456 #define PMX_SDHCI_CD_PORT_12_VAL 0
457 #define PMX_SDHCI_CD_PORT_51_VAL (0x1 << 29)
458
459/* Pad multiplexing for CLCD device */
460static const unsigned clcd_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78,
461 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96,
462 97 };
463static struct spear_muxreg clcd_muxreg[] = {
464 {
465 .reg = IP_SEL_PAD_60_69_REG,
466 .mask = PMX_PL_69_MASK,
467 .val = PMX_CLCD_PL_69_VAL,
468 }, {
469 .reg = IP_SEL_PAD_70_79_REG,
470 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
471 PMX_PL_74_MASK | PMX_PL_75_76_MASK |
472 PMX_PL_77_78_79_MASK,
473 .val = PMX_CLCD_PL_70_VAL | PMX_CLCD_PL_71_72_VAL |
474 PMX_CLCD_PL_73_VAL | PMX_CLCD_PL_74_VAL |
475 PMX_CLCD_PL_75_76_VAL | PMX_CLCD_PL_77_78_79_VAL,
476 }, {
477 .reg = IP_SEL_PAD_80_89_REG,
478 .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
479 PMX_PL_88_89_MASK,
480 .val = PMX_CLCD_PL_80_TO_85_VAL | PMX_CLCD_PL_86_87_VAL |
481 PMX_CLCD_PL_88_89_VAL,
482 }, {
483 .reg = IP_SEL_PAD_90_99_REG,
484 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
485 PMX_PL_94_95_MASK | PMX_PL_96_97_MASK | PMX_PL_98_MASK,
486 .val = PMX_CLCD_PL_90_91_VAL | PMX_CLCD_PL_92_93_VAL |
487 PMX_CLCD_PL_94_95_VAL | PMX_CLCD_PL_96_97_VAL |
488 PMX_CLCD_PL_98_VAL,
489 },
490};
491
492static struct spear_modemux clcd_modemux[] = {
493 {
494 .modes = EXTENDED_MODE,
495 .muxregs = clcd_muxreg,
496 .nmuxregs = ARRAY_SIZE(clcd_muxreg),
497 },
498};
499
500static struct spear_pingroup clcd_pingroup = {
501 .name = "clcd_grp",
502 .pins = clcd_pins,
503 .npins = ARRAY_SIZE(clcd_pins),
504 .modemuxs = clcd_modemux,
505 .nmodemuxs = ARRAY_SIZE(clcd_modemux),
506};
507
508static const char *const clcd_grps[] = { "clcd_grp" };
509static struct spear_function clcd_function = {
510 .name = "clcd",
511 .groups = clcd_grps,
512 .ngroups = ARRAY_SIZE(clcd_grps),
513};
514
515/* Pad multiplexing for EMI (Parallel NOR flash) device */
516static const unsigned emi_pins[] = { 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56,
517 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74,
518 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92,
519 93, 94, 95, 96, 97 };
520static struct spear_muxreg emi_muxreg[] = {
521 {
522 .reg = PMX_CONFIG_REG,
523 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
524 .val = 0,
525 },
526};
527
528static struct spear_muxreg emi_ext_muxreg[] = {
529 {
530 .reg = IP_SEL_PAD_40_49_REG,
531 .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
532 .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL,
533 }, {
534 .reg = IP_SEL_PAD_50_59_REG,
535 .mask = PMX_PL_50_51_MASK | PMX_PL_52_53_MASK |
536 PMX_PL_54_55_56_MASK | PMX_PL_58_59_MASK,
537 .val = PMX_EMI_PL_50_51_VAL | PMX_EMI_PL_52_53_VAL |
538 PMX_FSMC_EMI_PL_54_55_56_VAL |
539 PMX_FSMC_EMI_PL_58_59_VAL,
540 }, {
541 .reg = IP_SEL_PAD_60_69_REG,
542 .mask = PMX_PL_69_MASK,
543 .val = PMX_EMI_PL_69_VAL,
544 }, {
545 .reg = IP_SEL_PAD_70_79_REG,
546 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
547 PMX_PL_74_MASK | PMX_PL_75_76_MASK |
548 PMX_PL_77_78_79_MASK,
549 .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
550 PMX_FSMC_EMI_PL_73_VAL | PMX_EMI_PL_74_VAL |
551 PMX_EMI_PL_75_76_VAL | PMX_EMI_PL_77_78_79_VAL,
552 }, {
553 .reg = IP_SEL_PAD_80_89_REG,
554 .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
555 PMX_PL_88_89_MASK,
556 .val = PMX_EMI_PL_80_TO_85_VAL | PMX_EMI_PL_86_87_VAL |
557 PMX_EMI_PL_88_89_VAL,
558 }, {
559 .reg = IP_SEL_PAD_90_99_REG,
560 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
561 PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
562 .val = PMX_EMI1_PL_90_91_VAL | PMX_EMI1_PL_92_93_VAL |
563 PMX_EMI1_PL_94_95_VAL | PMX_EMI1_PL_96_97_VAL,
564 }, {
565 .reg = EXT_CTRL_REG,
566 .mask = EMI_FSMC_DYNAMIC_MUX_MASK,
567 .val = EMI_FSMC_DYNAMIC_MUX_MASK,
568 },
569};
570
571static struct spear_modemux emi_modemux[] = {
572 {
573 .modes = AUTO_EXP_MODE | EXTENDED_MODE,
574 .muxregs = emi_muxreg,
575 .nmuxregs = ARRAY_SIZE(emi_muxreg),
576 }, {
577 .modes = EXTENDED_MODE,
578 .muxregs = emi_ext_muxreg,
579 .nmuxregs = ARRAY_SIZE(emi_ext_muxreg),
580 },
581};
582
583static struct spear_pingroup emi_pingroup = {
584 .name = "emi_grp",
585 .pins = emi_pins,
586 .npins = ARRAY_SIZE(emi_pins),
587 .modemuxs = emi_modemux,
588 .nmodemuxs = ARRAY_SIZE(emi_modemux),
589};
590
591static const char *const emi_grps[] = { "emi_grp" };
592static struct spear_function emi_function = {
593 .name = "emi",
594 .groups = emi_grps,
595 .ngroups = ARRAY_SIZE(emi_grps),
596};
597
598/* Pad multiplexing for FSMC (NAND flash) device */
599static const unsigned fsmc_8bit_pins[] = { 52, 53, 54, 55, 56, 57, 58, 59, 60,
600 61, 62, 63, 64, 65, 66, 67, 68 };
601static struct spear_muxreg fsmc_8bit_muxreg[] = {
602 {
603 .reg = IP_SEL_PAD_50_59_REG,
604 .mask = PMX_PL_52_53_MASK | PMX_PL_54_55_56_MASK |
605 PMX_PL_57_MASK | PMX_PL_58_59_MASK,
606 .val = PMX_FSMC_PL_52_53_VAL | PMX_FSMC_EMI_PL_54_55_56_VAL |
607 PMX_FSMC_PL_57_VAL | PMX_FSMC_EMI_PL_58_59_VAL,
608 }, {
609 .reg = IP_SEL_PAD_60_69_REG,
610 .mask = PMX_PL_60_MASK | PMX_PL_61_TO_64_MASK |
611 PMX_PL_65_TO_68_MASK,
612 .val = PMX_FSMC_PL_60_VAL | PMX_FSMC_PL_61_TO_64_VAL |
613 PMX_FSMC_PL_65_TO_68_VAL,
614 }, {
615 .reg = EXT_CTRL_REG,
616 .mask = EMI_FSMC_DYNAMIC_MUX_MASK,
617 .val = EMI_FSMC_DYNAMIC_MUX_MASK,
618 },
619};
620
621static struct spear_modemux fsmc_8bit_modemux[] = {
622 {
623 .modes = EXTENDED_MODE,
624 .muxregs = fsmc_8bit_muxreg,
625 .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
626 },
627};
628
629static struct spear_pingroup fsmc_8bit_pingroup = {
630 .name = "fsmc_8bit_grp",
631 .pins = fsmc_8bit_pins,
632 .npins = ARRAY_SIZE(fsmc_8bit_pins),
633 .modemuxs = fsmc_8bit_modemux,
634 .nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux),
635};
636
637static const unsigned fsmc_16bit_pins[] = { 46, 47, 48, 49, 52, 53, 54, 55, 56,
638 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 70, 71, 72, 73 };
639static struct spear_muxreg fsmc_16bit_autoexp_muxreg[] = {
640 {
641 .reg = PMX_CONFIG_REG,
642 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
643 .val = 0,
644 },
645};
646
647static struct spear_muxreg fsmc_16bit_muxreg[] = {
648 {
649 .reg = IP_SEL_PAD_40_49_REG,
650 .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
651 .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL,
652 }, {
653 .reg = IP_SEL_PAD_70_79_REG,
654 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK,
655 .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
656 PMX_FSMC_EMI_PL_73_VAL,
657 }
658};
659
660static struct spear_modemux fsmc_16bit_modemux[] = {
661 {
662 .modes = EXTENDED_MODE,
663 .muxregs = fsmc_8bit_muxreg,
664 .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
665 }, {
666 .modes = AUTO_EXP_MODE | EXTENDED_MODE,
667 .muxregs = fsmc_16bit_autoexp_muxreg,
668 .nmuxregs = ARRAY_SIZE(fsmc_16bit_autoexp_muxreg),
669 }, {
670 .modes = EXTENDED_MODE,
671 .muxregs = fsmc_16bit_muxreg,
672 .nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg),
673 },
674};
675
676static struct spear_pingroup fsmc_16bit_pingroup = {
677 .name = "fsmc_16bit_grp",
678 .pins = fsmc_16bit_pins,
679 .npins = ARRAY_SIZE(fsmc_16bit_pins),
680 .modemuxs = fsmc_16bit_modemux,
681 .nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux),
682};
683
684static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp" };
685static struct spear_function fsmc_function = {
686 .name = "fsmc",
687 .groups = fsmc_grps,
688 .ngroups = ARRAY_SIZE(fsmc_grps),
689};
690
691/* Pad multiplexing for SPP device */
692static const unsigned spp_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
693 80, 81, 82, 83, 84, 85 };
694static struct spear_muxreg spp_muxreg[] = {
695 {
696 .reg = IP_SEL_PAD_60_69_REG,
697 .mask = PMX_PL_69_MASK,
698 .val = PMX_SPP_PL_69_VAL,
699 }, {
700 .reg = IP_SEL_PAD_70_79_REG,
701 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
702 PMX_PL_74_MASK | PMX_PL_75_76_MASK |
703 PMX_PL_77_78_79_MASK,
704 .val = PMX_SPP_PL_70_VAL | PMX_SPP_PL_71_72_VAL |
705 PMX_SPP_PL_73_VAL | PMX_SPP_PL_74_VAL |
706 PMX_SPP_PL_75_76_VAL | PMX_SPP_PL_77_78_79_VAL,
707 }, {
708 .reg = IP_SEL_PAD_80_89_REG,
709 .mask = PMX_PL_80_TO_85_MASK,
710 .val = PMX_SPP_PL_80_TO_85_VAL,
711 },
712};
713
714static struct spear_modemux spp_modemux[] = {
715 {
716 .modes = EXTENDED_MODE,
717 .muxregs = spp_muxreg,
718 .nmuxregs = ARRAY_SIZE(spp_muxreg),
719 },
720};
721
722static struct spear_pingroup spp_pingroup = {
723 .name = "spp_grp",
724 .pins = spp_pins,
725 .npins = ARRAY_SIZE(spp_pins),
726 .modemuxs = spp_modemux,
727 .nmodemuxs = ARRAY_SIZE(spp_modemux),
728};
729
730static const char *const spp_grps[] = { "spp_grp" };
731static struct spear_function spp_function = {
732 .name = "spp",
733 .groups = spp_grps,
734 .ngroups = ARRAY_SIZE(spp_grps),
735};
736
737/* Pad multiplexing for SDHCI device */
738static const unsigned sdhci_led_pins[] = { 34 };
739static struct spear_muxreg sdhci_led_muxreg[] = {
740 {
741 .reg = PMX_CONFIG_REG,
742 .mask = PMX_SSP_CS_MASK,
743 .val = 0,
744 },
745};
746
747static struct spear_muxreg sdhci_led_ext_muxreg[] = {
748 {
749 .reg = IP_SEL_PAD_30_39_REG,
750 .mask = PMX_PL_34_MASK,
751 .val = PMX_PWM2_PL_34_VAL,
752 },
753};
754
755static struct spear_modemux sdhci_led_modemux[] = {
756 {
757 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
758 .muxregs = sdhci_led_muxreg,
759 .nmuxregs = ARRAY_SIZE(sdhci_led_muxreg),
760 }, {
761 .modes = EXTENDED_MODE,
762 .muxregs = sdhci_led_ext_muxreg,
763 .nmuxregs = ARRAY_SIZE(sdhci_led_ext_muxreg),
764 },
765};
766
767static struct spear_pingroup sdhci_led_pingroup = {
768 .name = "sdhci_led_grp",
769 .pins = sdhci_led_pins,
770 .npins = ARRAY_SIZE(sdhci_led_pins),
771 .modemuxs = sdhci_led_modemux,
772 .nmodemuxs = ARRAY_SIZE(sdhci_led_modemux),
773};
774
775static const unsigned sdhci_cd_12_pins[] = { 12, 43, 44, 45, 46, 47, 48, 49,
776 50};
777static const unsigned sdhci_cd_51_pins[] = { 43, 44, 45, 46, 47, 48, 49, 50, 51
778};
779static struct spear_muxreg sdhci_muxreg[] = {
780 {
781 .reg = PMX_CONFIG_REG,
782 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
783 .val = 0,
784 },
785};
786
787static struct spear_muxreg sdhci_ext_muxreg[] = {
788 {
789 .reg = IP_SEL_PAD_40_49_REG,
790 .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK | PMX_PL_46_47_MASK |
791 PMX_PL_48_49_MASK,
792 .val = PMX_SDHCI_PL_43_VAL | PMX_SDHCI_PL_44_45_VAL |
793 PMX_SDHCI_PL_46_47_VAL | PMX_SDHCI_PL_48_49_VAL,
794 }, {
795 .reg = IP_SEL_PAD_50_59_REG,
796 .mask = PMX_PL_50_MASK,
797 .val = PMX_SDHCI_PL_50_VAL,
798 }, {
799 .reg = IP_SEL_PAD_90_99_REG,
800 .mask = PMX_PL_99_MASK,
801 .val = PMX_SDHCI_PL_99_VAL,
802 }, {
803 .reg = IP_SEL_MIX_PAD_REG,
804 .mask = PMX_PL_100_101_MASK,
805 .val = PMX_SDHCI_PL_100_101_VAL,
806 },
807};
808
809static struct spear_muxreg sdhci_cd_12_muxreg[] = {
810 {
811 .reg = PMX_CONFIG_REG,
812 .mask = PMX_MII_MASK,
813 .val = 0,
814 }, {
815 .reg = IP_SEL_PAD_10_19_REG,
816 .mask = PMX_PL_12_MASK,
817 .val = PMX_SDHCI_CD_PL_12_VAL,
818 }, {
819 .reg = IP_SEL_MIX_PAD_REG,
820 .mask = PMX_SDHCI_CD_PORT_SEL_MASK,
821 .val = PMX_SDHCI_CD_PORT_12_VAL,
822 },
823};
824
825static struct spear_muxreg sdhci_cd_51_muxreg[] = {
826 {
827 .reg = IP_SEL_PAD_50_59_REG,
828 .mask = PMX_PL_51_MASK,
829 .val = PMX_SDHCI_CD_PL_51_VAL,
830 }, {
831 .reg = IP_SEL_MIX_PAD_REG,
832 .mask = PMX_SDHCI_CD_PORT_SEL_MASK,
833 .val = PMX_SDHCI_CD_PORT_51_VAL,
834 },
835};
836
837#define pmx_sdhci_common_modemux \
838 { \
839 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | \
840 SMALL_PRINTERS_MODE | EXTENDED_MODE, \
841 .muxregs = sdhci_muxreg, \
842 .nmuxregs = ARRAY_SIZE(sdhci_muxreg), \
843 }, { \
844 .modes = EXTENDED_MODE, \
845 .muxregs = sdhci_ext_muxreg, \
846 .nmuxregs = ARRAY_SIZE(sdhci_ext_muxreg), \
847 }
848
849static struct spear_modemux sdhci_modemux[][3] = {
850 {
851 /* select pin 12 for cd */
852 pmx_sdhci_common_modemux,
853 {
854 .modes = EXTENDED_MODE,
855 .muxregs = sdhci_cd_12_muxreg,
856 .nmuxregs = ARRAY_SIZE(sdhci_cd_12_muxreg),
857 },
858 }, {
859 /* select pin 51 for cd */
860 pmx_sdhci_common_modemux,
861 {
862 .modes = EXTENDED_MODE,
863 .muxregs = sdhci_cd_51_muxreg,
864 .nmuxregs = ARRAY_SIZE(sdhci_cd_51_muxreg),
865 },
866 }
867};
868
869static struct spear_pingroup sdhci_pingroup[] = {
870 {
871 .name = "sdhci_cd_12_grp",
872 .pins = sdhci_cd_12_pins,
873 .npins = ARRAY_SIZE(sdhci_cd_12_pins),
874 .modemuxs = sdhci_modemux[0],
875 .nmodemuxs = ARRAY_SIZE(sdhci_modemux[0]),
876 }, {
877 .name = "sdhci_cd_51_grp",
878 .pins = sdhci_cd_51_pins,
879 .npins = ARRAY_SIZE(sdhci_cd_51_pins),
880 .modemuxs = sdhci_modemux[1],
881 .nmodemuxs = ARRAY_SIZE(sdhci_modemux[1]),
882 },
883};
884
885static const char *const sdhci_grps[] = { "sdhci_cd_12_grp", "sdhci_cd_51_grp",
886 "sdhci_led_grp" };
887
888static struct spear_function sdhci_function = {
889 .name = "sdhci",
890 .groups = sdhci_grps,
891 .ngroups = ARRAY_SIZE(sdhci_grps),
892};
893
894/* Pad multiplexing for I2S device */
895static const unsigned i2s_pins[] = { 35, 39, 40, 41, 42 };
896static struct spear_muxreg i2s_muxreg[] = {
897 {
898 .reg = PMX_CONFIG_REG,
899 .mask = PMX_SSP_CS_MASK,
900 .val = 0,
901 }, {
902 .reg = PMX_CONFIG_REG,
903 .mask = PMX_UART0_MODEM_MASK,
904 .val = 0,
905 },
906};
907
908static struct spear_muxreg i2s_ext_muxreg[] = {
909 {
910 .reg = IP_SEL_PAD_30_39_REG,
911 .mask = PMX_PL_35_MASK | PMX_PL_39_MASK,
912 .val = PMX_I2S_REF_CLK_PL_35_VAL | PMX_I2S_PL_39_VAL,
913 }, {
914 .reg = IP_SEL_PAD_40_49_REG,
915 .mask = PMX_PL_40_MASK | PMX_PL_41_42_MASK,
916 .val = PMX_I2S_PL_40_VAL | PMX_I2S_PL_41_42_VAL,
917 },
918};
919
920static struct spear_modemux i2s_modemux[] = {
921 {
922 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
923 .muxregs = i2s_muxreg,
924 .nmuxregs = ARRAY_SIZE(i2s_muxreg),
925 }, {
926 .modes = EXTENDED_MODE,
927 .muxregs = i2s_ext_muxreg,
928 .nmuxregs = ARRAY_SIZE(i2s_ext_muxreg),
929 },
930};
931
932static struct spear_pingroup i2s_pingroup = {
933 .name = "i2s_grp",
934 .pins = i2s_pins,
935 .npins = ARRAY_SIZE(i2s_pins),
936 .modemuxs = i2s_modemux,
937 .nmodemuxs = ARRAY_SIZE(i2s_modemux),
938};
939
940static const char *const i2s_grps[] = { "i2s_grp" };
941static struct spear_function i2s_function = {
942 .name = "i2s",
943 .groups = i2s_grps,
944 .ngroups = ARRAY_SIZE(i2s_grps),
945};
946
947/* Pad multiplexing for UART1 device */
948static const unsigned uart1_pins[] = { 28, 29 };
949static struct spear_muxreg uart1_muxreg[] = {
950 {
951 .reg = PMX_CONFIG_REG,
952 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
953 .val = 0,
954 },
955};
956
957static struct spear_muxreg uart1_ext_muxreg[] = {
958 {
959 .reg = IP_SEL_PAD_20_29_REG,
960 .mask = PMX_PL_28_29_MASK,
961 .val = PMX_UART1_PL_28_29_VAL,
962 },
963};
964
965static struct spear_modemux uart1_modemux[] = {
966 {
967 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
968 | SMALL_PRINTERS_MODE | EXTENDED_MODE,
969 .muxregs = uart1_muxreg,
970 .nmuxregs = ARRAY_SIZE(uart1_muxreg),
971 }, {
972 .modes = EXTENDED_MODE,
973 .muxregs = uart1_ext_muxreg,
974 .nmuxregs = ARRAY_SIZE(uart1_ext_muxreg),
975 },
976};
977
978static struct spear_pingroup uart1_pingroup = {
979 .name = "uart1_grp",
980 .pins = uart1_pins,
981 .npins = ARRAY_SIZE(uart1_pins),
982 .modemuxs = uart1_modemux,
983 .nmodemuxs = ARRAY_SIZE(uart1_modemux),
984};
985
986static const char *const uart1_grps[] = { "uart1_grp" };
987static struct spear_function uart1_function = {
988 .name = "uart1",
989 .groups = uart1_grps,
990 .ngroups = ARRAY_SIZE(uart1_grps),
991};
992
993/* Pad multiplexing for UART1 Modem device */
994static const unsigned uart1_modem_2_to_7_pins[] = { 2, 3, 4, 5, 6, 7 };
995static const unsigned uart1_modem_31_to_36_pins[] = { 31, 32, 33, 34, 35, 36 };
996static const unsigned uart1_modem_34_to_45_pins[] = { 34, 35, 36, 43, 44, 45 };
997static const unsigned uart1_modem_80_to_85_pins[] = { 80, 81, 82, 83, 84, 85 };
998
999static struct spear_muxreg uart1_modem_ext_2_to_7_muxreg[] = {
1000 {
1001 .reg = PMX_CONFIG_REG,
1002 .mask = PMX_UART0_MASK | PMX_I2C_MASK | PMX_SSP_MASK,
1003 .val = 0,
1004 }, {
1005 .reg = IP_SEL_PAD_0_9_REG,
1006 .mask = PMX_PL_2_3_MASK | PMX_PL_6_7_MASK,
1007 .val = PMX_UART1_ENH_PL_2_3_VAL | PMX_UART1_ENH_PL_4_5_VAL |
1008 PMX_UART1_ENH_PL_6_7_VAL,
1009 }, {
1010 .reg = IP_SEL_MIX_PAD_REG,
1011 .mask = PMX_UART1_ENH_PORT_SEL_MASK,
1012 .val = PMX_UART1_ENH_PORT_3_TO_5_7_VAL,
1013 },
1014};
1015
1016static struct spear_muxreg uart1_modem_31_to_36_muxreg[] = {
1017 {
1018 .reg = PMX_CONFIG_REG,
1019 .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
1020 PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
1021 .val = 0,
1022 },
1023};
1024
1025static struct spear_muxreg uart1_modem_ext_31_to_36_muxreg[] = {
1026 {
1027 .reg = IP_SEL_PAD_30_39_REG,
1028 .mask = PMX_PL_31_MASK | PMX_PL_32_33_MASK | PMX_PL_34_MASK |
1029 PMX_PL_35_MASK | PMX_PL_36_MASK,
1030 .val = PMX_UART1_ENH_PL_31_VAL | PMX_UART1_ENH_PL_32_33_VAL |
1031 PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
1032 PMX_UART1_ENH_PL_36_VAL,
1033 }, {
1034 .reg = IP_SEL_MIX_PAD_REG,
1035 .mask = PMX_UART1_ENH_PORT_SEL_MASK,
1036 .val = PMX_UART1_ENH_PORT_32_TO_34_36_VAL,
1037 },
1038};
1039
1040static struct spear_muxreg uart1_modem_34_to_45_muxreg[] = {
1041 {
1042 .reg = PMX_CONFIG_REG,
1043 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK |
1044 PMX_SSP_CS_MASK,
1045 .val = 0,
1046 },
1047};
1048
1049static struct spear_muxreg uart1_modem_ext_34_to_45_muxreg[] = {
1050 {
1051 .reg = IP_SEL_PAD_30_39_REG,
1052 .mask = PMX_PL_34_MASK | PMX_PL_35_MASK | PMX_PL_36_MASK,
1053 .val = PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
1054 PMX_UART1_ENH_PL_36_VAL,
1055 }, {
1056 .reg = IP_SEL_PAD_40_49_REG,
1057 .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
1058 .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL,
1059 }, {
1060 .reg = IP_SEL_MIX_PAD_REG,
1061 .mask = PMX_UART1_ENH_PORT_SEL_MASK,
1062 .val = PMX_UART1_ENH_PORT_44_45_34_36_VAL,
1063 },
1064};
1065
1066static struct spear_muxreg uart1_modem_ext_80_to_85_muxreg[] = {
1067 {
1068 .reg = IP_SEL_PAD_80_89_REG,
1069 .mask = PMX_PL_80_TO_85_MASK,
1070 .val = PMX_UART1_ENH_PL_80_TO_85_VAL,
1071 }, {
1072 .reg = IP_SEL_PAD_40_49_REG,
1073 .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
1074 .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL,
1075 }, {
1076 .reg = IP_SEL_MIX_PAD_REG,
1077 .mask = PMX_UART1_ENH_PORT_SEL_MASK,
1078 .val = PMX_UART1_ENH_PORT_81_TO_85_VAL,
1079 },
1080};
1081
1082static struct spear_modemux uart1_modem_2_to_7_modemux[] = {
1083 {
1084 .modes = EXTENDED_MODE,
1085 .muxregs = uart1_modem_ext_2_to_7_muxreg,
1086 .nmuxregs = ARRAY_SIZE(uart1_modem_ext_2_to_7_muxreg),
1087 },
1088};
1089
1090static struct spear_modemux uart1_modem_31_to_36_modemux[] = {
1091 {
1092 .modes = SMALL_PRINTERS_MODE | EXTENDED_MODE,
1093 .muxregs = uart1_modem_31_to_36_muxreg,
1094 .nmuxregs = ARRAY_SIZE(uart1_modem_31_to_36_muxreg),
1095 }, {
1096 .modes = EXTENDED_MODE,
1097 .muxregs = uart1_modem_ext_31_to_36_muxreg,
1098 .nmuxregs = ARRAY_SIZE(uart1_modem_ext_31_to_36_muxreg),
1099 },
1100};
1101
1102static struct spear_modemux uart1_modem_34_to_45_modemux[] = {
1103 {
1104 .modes = AUTO_EXP_MODE | EXTENDED_MODE,
1105 .muxregs = uart1_modem_34_to_45_muxreg,
1106 .nmuxregs = ARRAY_SIZE(uart1_modem_34_to_45_muxreg),
1107 }, {
1108 .modes = EXTENDED_MODE,
1109 .muxregs = uart1_modem_ext_34_to_45_muxreg,
1110 .nmuxregs = ARRAY_SIZE(uart1_modem_ext_34_to_45_muxreg),
1111 },
1112};
1113
1114static struct spear_modemux uart1_modem_80_to_85_modemux[] = {
1115 {
1116 .modes = EXTENDED_MODE,
1117 .muxregs = uart1_modem_ext_80_to_85_muxreg,
1118 .nmuxregs = ARRAY_SIZE(uart1_modem_ext_80_to_85_muxreg),
1119 },
1120};
1121
1122static struct spear_pingroup uart1_modem_pingroup[] = {
1123 {
1124 .name = "uart1_modem_2_to_7_grp",
1125 .pins = uart1_modem_2_to_7_pins,
1126 .npins = ARRAY_SIZE(uart1_modem_2_to_7_pins),
1127 .modemuxs = uart1_modem_2_to_7_modemux,
1128 .nmodemuxs = ARRAY_SIZE(uart1_modem_2_to_7_modemux),
1129 }, {
1130 .name = "uart1_modem_31_to_36_grp",
1131 .pins = uart1_modem_31_to_36_pins,
1132 .npins = ARRAY_SIZE(uart1_modem_31_to_36_pins),
1133 .modemuxs = uart1_modem_31_to_36_modemux,
1134 .nmodemuxs = ARRAY_SIZE(uart1_modem_31_to_36_modemux),
1135 }, {
1136 .name = "uart1_modem_34_to_45_grp",
1137 .pins = uart1_modem_34_to_45_pins,
1138 .npins = ARRAY_SIZE(uart1_modem_34_to_45_pins),
1139 .modemuxs = uart1_modem_34_to_45_modemux,
1140 .nmodemuxs = ARRAY_SIZE(uart1_modem_34_to_45_modemux),
1141 }, {
1142 .name = "uart1_modem_80_to_85_grp",
1143 .pins = uart1_modem_80_to_85_pins,
1144 .npins = ARRAY_SIZE(uart1_modem_80_to_85_pins),
1145 .modemuxs = uart1_modem_80_to_85_modemux,
1146 .nmodemuxs = ARRAY_SIZE(uart1_modem_80_to_85_modemux),
1147 },
1148};
1149
1150static const char *const uart1_modem_grps[] = { "uart1_modem_2_to_7_grp",
1151 "uart1_modem_31_to_36_grp", "uart1_modem_34_to_45_grp",
1152 "uart1_modem_80_to_85_grp" };
1153static struct spear_function uart1_modem_function = {
1154 .name = "uart1_modem",
1155 .groups = uart1_modem_grps,
1156 .ngroups = ARRAY_SIZE(uart1_modem_grps),
1157};
1158
1159/* Pad multiplexing for UART2 device */
1160static const unsigned uart2_pins[] = { 0, 1 };
1161static struct spear_muxreg uart2_muxreg[] = {
1162 {
1163 .reg = PMX_CONFIG_REG,
1164 .mask = PMX_FIRDA_MASK,
1165 .val = 0,
1166 },
1167};
1168
1169static struct spear_muxreg uart2_ext_muxreg[] = {
1170 {
1171 .reg = IP_SEL_PAD_0_9_REG,
1172 .mask = PMX_PL_0_1_MASK,
1173 .val = PMX_UART2_PL_0_1_VAL,
1174 },
1175};
1176
1177static struct spear_modemux uart2_modemux[] = {
1178 {
1179 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
1180 | SMALL_PRINTERS_MODE | EXTENDED_MODE,
1181 .muxregs = uart2_muxreg,
1182 .nmuxregs = ARRAY_SIZE(uart2_muxreg),
1183 }, {
1184 .modes = EXTENDED_MODE,
1185 .muxregs = uart2_ext_muxreg,
1186 .nmuxregs = ARRAY_SIZE(uart2_ext_muxreg),
1187 },
1188};
1189
1190static struct spear_pingroup uart2_pingroup = {
1191 .name = "uart2_grp",
1192 .pins = uart2_pins,
1193 .npins = ARRAY_SIZE(uart2_pins),
1194 .modemuxs = uart2_modemux,
1195 .nmodemuxs = ARRAY_SIZE(uart2_modemux),
1196};
1197
1198static const char *const uart2_grps[] = { "uart2_grp" };
1199static struct spear_function uart2_function = {
1200 .name = "uart2",
1201 .groups = uart2_grps,
1202 .ngroups = ARRAY_SIZE(uart2_grps),
1203};
1204
1205/* Pad multiplexing for uart3 device */
1206static const unsigned uart3_pins[][2] = { { 8, 9 }, { 15, 16 }, { 41, 42 },
1207 { 52, 53 }, { 73, 74 }, { 94, 95 }, { 98, 99 } };
1208
1209static struct spear_muxreg uart3_ext_8_9_muxreg[] = {
1210 {
1211 .reg = PMX_CONFIG_REG,
1212 .mask = PMX_SSP_MASK,
1213 .val = 0,
1214 }, {
1215 .reg = IP_SEL_PAD_0_9_REG,
1216 .mask = PMX_PL_8_9_MASK,
1217 .val = PMX_UART3_PL_8_9_VAL,
1218 }, {
1219 .reg = IP_SEL_MIX_PAD_REG,
1220 .mask = PMX_UART3_PORT_SEL_MASK,
1221 .val = PMX_UART3_PORT_8_VAL,
1222 },
1223};
1224
1225static struct spear_muxreg uart3_ext_15_16_muxreg[] = {
1226 {
1227 .reg = PMX_CONFIG_REG,
1228 .mask = PMX_MII_MASK,
1229 .val = 0,
1230 }, {
1231 .reg = IP_SEL_PAD_10_19_REG,
1232 .mask = PMX_PL_15_16_MASK,
1233 .val = PMX_UART3_PL_15_16_VAL,
1234 }, {
1235 .reg = IP_SEL_MIX_PAD_REG,
1236 .mask = PMX_UART3_PORT_SEL_MASK,
1237 .val = PMX_UART3_PORT_15_VAL,
1238 },
1239};
1240
1241static struct spear_muxreg uart3_ext_41_42_muxreg[] = {
1242 {
1243 .reg = PMX_CONFIG_REG,
1244 .mask = PMX_UART0_MODEM_MASK,
1245 .val = 0,
1246 }, {
1247 .reg = IP_SEL_PAD_40_49_REG,
1248 .mask = PMX_PL_41_42_MASK,
1249 .val = PMX_UART3_PL_41_42_VAL,
1250 }, {
1251 .reg = IP_SEL_MIX_PAD_REG,
1252 .mask = PMX_UART3_PORT_SEL_MASK,
1253 .val = PMX_UART3_PORT_41_VAL,
1254 },
1255};
1256
1257static struct spear_muxreg uart3_ext_52_53_muxreg[] = {
1258 {
1259 .reg = IP_SEL_PAD_50_59_REG,
1260 .mask = PMX_PL_52_53_MASK,
1261 .val = PMX_UART3_PL_52_53_VAL,
1262 }, {
1263 .reg = IP_SEL_MIX_PAD_REG,
1264 .mask = PMX_UART3_PORT_SEL_MASK,
1265 .val = PMX_UART3_PORT_52_VAL,
1266 },
1267};
1268
1269static struct spear_muxreg uart3_ext_73_74_muxreg[] = {
1270 {
1271 .reg = IP_SEL_PAD_70_79_REG,
1272 .mask = PMX_PL_73_MASK | PMX_PL_74_MASK,
1273 .val = PMX_UART3_PL_73_VAL | PMX_UART3_PL_74_VAL,
1274 }, {
1275 .reg = IP_SEL_MIX_PAD_REG,
1276 .mask = PMX_UART3_PORT_SEL_MASK,
1277 .val = PMX_UART3_PORT_73_VAL,
1278 },
1279};
1280
1281static struct spear_muxreg uart3_ext_94_95_muxreg[] = {
1282 {
1283 .reg = IP_SEL_PAD_90_99_REG,
1284 .mask = PMX_PL_94_95_MASK,
1285 .val = PMX_UART3_PL_94_95_VAL,
1286 }, {
1287 .reg = IP_SEL_MIX_PAD_REG,
1288 .mask = PMX_UART3_PORT_SEL_MASK,
1289 .val = PMX_UART3_PORT_94_VAL,
1290 },
1291};
1292
1293static struct spear_muxreg uart3_ext_98_99_muxreg[] = {
1294 {
1295 .reg = IP_SEL_PAD_90_99_REG,
1296 .mask = PMX_PL_98_MASK | PMX_PL_99_MASK,
1297 .val = PMX_UART3_PL_98_VAL | PMX_UART3_PL_99_VAL,
1298 }, {
1299 .reg = IP_SEL_MIX_PAD_REG,
1300 .mask = PMX_UART3_PORT_SEL_MASK,
1301 .val = PMX_UART3_PORT_99_VAL,
1302 },
1303};
1304
1305static struct spear_modemux uart3_modemux[][1] = {
1306 {
1307 /* Select signals on pins 8_9 */
1308 {
1309 .modes = EXTENDED_MODE,
1310 .muxregs = uart3_ext_8_9_muxreg,
1311 .nmuxregs = ARRAY_SIZE(uart3_ext_8_9_muxreg),
1312 },
1313 }, {
1314 /* Select signals on pins 15_16 */
1315 {
1316 .modes = EXTENDED_MODE,
1317 .muxregs = uart3_ext_15_16_muxreg,
1318 .nmuxregs = ARRAY_SIZE(uart3_ext_15_16_muxreg),
1319 },
1320 }, {
1321 /* Select signals on pins 41_42 */
1322 {
1323 .modes = EXTENDED_MODE,
1324 .muxregs = uart3_ext_41_42_muxreg,
1325 .nmuxregs = ARRAY_SIZE(uart3_ext_41_42_muxreg),
1326 },
1327 }, {
1328 /* Select signals on pins 52_53 */
1329 {
1330 .modes = EXTENDED_MODE,
1331 .muxregs = uart3_ext_52_53_muxreg,
1332 .nmuxregs = ARRAY_SIZE(uart3_ext_52_53_muxreg),
1333 },
1334 }, {
1335 /* Select signals on pins 73_74 */
1336 {
1337 .modes = EXTENDED_MODE,
1338 .muxregs = uart3_ext_73_74_muxreg,
1339 .nmuxregs = ARRAY_SIZE(uart3_ext_73_74_muxreg),
1340 },
1341 }, {
1342 /* Select signals on pins 94_95 */
1343 {
1344 .modes = EXTENDED_MODE,
1345 .muxregs = uart3_ext_94_95_muxreg,
1346 .nmuxregs = ARRAY_SIZE(uart3_ext_94_95_muxreg),
1347 },
1348 }, {
1349 /* Select signals on pins 98_99 */
1350 {
1351 .modes = EXTENDED_MODE,
1352 .muxregs = uart3_ext_98_99_muxreg,
1353 .nmuxregs = ARRAY_SIZE(uart3_ext_98_99_muxreg),
1354 },
1355 },
1356};
1357
1358static struct spear_pingroup uart3_pingroup[] = {
1359 {
1360 .name = "uart3_8_9_grp",
1361 .pins = uart3_pins[0],
1362 .npins = ARRAY_SIZE(uart3_pins[0]),
1363 .modemuxs = uart3_modemux[0],
1364 .nmodemuxs = ARRAY_SIZE(uart3_modemux[0]),
1365 }, {
1366 .name = "uart3_15_16_grp",
1367 .pins = uart3_pins[1],
1368 .npins = ARRAY_SIZE(uart3_pins[1]),
1369 .modemuxs = uart3_modemux[1],
1370 .nmodemuxs = ARRAY_SIZE(uart3_modemux[1]),
1371 }, {
1372 .name = "uart3_41_42_grp",
1373 .pins = uart3_pins[2],
1374 .npins = ARRAY_SIZE(uart3_pins[2]),
1375 .modemuxs = uart3_modemux[2],
1376 .nmodemuxs = ARRAY_SIZE(uart3_modemux[2]),
1377 }, {
1378 .name = "uart3_52_53_grp",
1379 .pins = uart3_pins[3],
1380 .npins = ARRAY_SIZE(uart3_pins[3]),
1381 .modemuxs = uart3_modemux[3],
1382 .nmodemuxs = ARRAY_SIZE(uart3_modemux[3]),
1383 }, {
1384 .name = "uart3_73_74_grp",
1385 .pins = uart3_pins[4],
1386 .npins = ARRAY_SIZE(uart3_pins[4]),
1387 .modemuxs = uart3_modemux[4],
1388 .nmodemuxs = ARRAY_SIZE(uart3_modemux[4]),
1389 }, {
1390 .name = "uart3_94_95_grp",
1391 .pins = uart3_pins[5],
1392 .npins = ARRAY_SIZE(uart3_pins[5]),
1393 .modemuxs = uart3_modemux[5],
1394 .nmodemuxs = ARRAY_SIZE(uart3_modemux[5]),
1395 }, {
1396 .name = "uart3_98_99_grp",
1397 .pins = uart3_pins[6],
1398 .npins = ARRAY_SIZE(uart3_pins[6]),
1399 .modemuxs = uart3_modemux[6],
1400 .nmodemuxs = ARRAY_SIZE(uart3_modemux[6]),
1401 },
1402};
1403
1404static const char *const uart3_grps[] = { "uart3_8_9_grp", "uart3_15_16_grp",
1405 "uart3_41_42_grp", "uart3_52_53_grp", "uart3_73_74_grp",
1406 "uart3_94_95_grp", "uart3_98_99_grp" };
1407
1408static struct spear_function uart3_function = {
1409 .name = "uart3",
1410 .groups = uart3_grps,
1411 .ngroups = ARRAY_SIZE(uart3_grps),
1412};
1413
1414/* Pad multiplexing for uart4 device */
1415static const unsigned uart4_pins[][2] = { { 6, 7 }, { 13, 14 }, { 39, 40 },
1416 { 71, 72 }, { 92, 93 }, { 100, 101 } };
1417
1418static struct spear_muxreg uart4_ext_6_7_muxreg[] = {
1419 {
1420 .reg = PMX_CONFIG_REG,
1421 .mask = PMX_SSP_MASK,
1422 .val = 0,
1423 }, {
1424 .reg = IP_SEL_PAD_0_9_REG,
1425 .mask = PMX_PL_6_7_MASK,
1426 .val = PMX_UART4_PL_6_7_VAL,
1427 }, {
1428 .reg = IP_SEL_MIX_PAD_REG,
1429 .mask = PMX_UART4_PORT_SEL_MASK,
1430 .val = PMX_UART4_PORT_6_VAL,
1431 },
1432};
1433
1434static struct spear_muxreg uart4_ext_13_14_muxreg[] = {
1435 {
1436 .reg = PMX_CONFIG_REG,
1437 .mask = PMX_MII_MASK,
1438 .val = 0,
1439 }, {
1440 .reg = IP_SEL_PAD_10_19_REG,
1441 .mask = PMX_PL_13_14_MASK,
1442 .val = PMX_UART4_PL_13_14_VAL,
1443 }, {
1444 .reg = IP_SEL_MIX_PAD_REG,
1445 .mask = PMX_UART4_PORT_SEL_MASK,
1446 .val = PMX_UART4_PORT_13_VAL,
1447 },
1448};
1449
1450static struct spear_muxreg uart4_ext_39_40_muxreg[] = {
1451 {
1452 .reg = PMX_CONFIG_REG,
1453 .mask = PMX_UART0_MODEM_MASK,
1454 .val = 0,
1455 }, {
1456 .reg = IP_SEL_PAD_30_39_REG,
1457 .mask = PMX_PL_39_MASK,
1458 .val = PMX_UART4_PL_39_VAL,
1459 }, {
1460 .reg = IP_SEL_PAD_40_49_REG,
1461 .mask = PMX_PL_40_MASK,
1462 .val = PMX_UART4_PL_40_VAL,
1463 }, {
1464 .reg = IP_SEL_MIX_PAD_REG,
1465 .mask = PMX_UART4_PORT_SEL_MASK,
1466 .val = PMX_UART4_PORT_39_VAL,
1467 },
1468};
1469
1470static struct spear_muxreg uart4_ext_71_72_muxreg[] = {
1471 {
1472 .reg = IP_SEL_PAD_70_79_REG,
1473 .mask = PMX_PL_71_72_MASK,
1474 .val = PMX_UART4_PL_71_72_VAL,
1475 }, {
1476 .reg = IP_SEL_MIX_PAD_REG,
1477 .mask = PMX_UART4_PORT_SEL_MASK,
1478 .val = PMX_UART4_PORT_71_VAL,
1479 },
1480};
1481
1482static struct spear_muxreg uart4_ext_92_93_muxreg[] = {
1483 {
1484 .reg = IP_SEL_PAD_90_99_REG,
1485 .mask = PMX_PL_92_93_MASK,
1486 .val = PMX_UART4_PL_92_93_VAL,
1487 }, {
1488 .reg = IP_SEL_MIX_PAD_REG,
1489 .mask = PMX_UART4_PORT_SEL_MASK,
1490 .val = PMX_UART4_PORT_92_VAL,
1491 },
1492};
1493
1494static struct spear_muxreg uart4_ext_100_101_muxreg[] = {
1495 {
1496 .reg = IP_SEL_MIX_PAD_REG,
1497 .mask = PMX_PL_100_101_MASK |
1498 PMX_UART4_PORT_SEL_MASK,
1499 .val = PMX_UART4_PL_100_101_VAL |
1500 PMX_UART4_PORT_101_VAL,
1501 },
1502};
1503
1504static struct spear_modemux uart4_modemux[][1] = {
1505 {
1506 /* Select signals on pins 6_7 */
1507 {
1508 .modes = EXTENDED_MODE,
1509 .muxregs = uart4_ext_6_7_muxreg,
1510 .nmuxregs = ARRAY_SIZE(uart4_ext_6_7_muxreg),
1511 },
1512 }, {
1513 /* Select signals on pins 13_14 */
1514 {
1515 .modes = EXTENDED_MODE,
1516 .muxregs = uart4_ext_13_14_muxreg,
1517 .nmuxregs = ARRAY_SIZE(uart4_ext_13_14_muxreg),
1518 },
1519 }, {
1520 /* Select signals on pins 39_40 */
1521 {
1522 .modes = EXTENDED_MODE,
1523 .muxregs = uart4_ext_39_40_muxreg,
1524 .nmuxregs = ARRAY_SIZE(uart4_ext_39_40_muxreg),
1525 },
1526 }, {
1527 /* Select signals on pins 71_72 */
1528 {
1529 .modes = EXTENDED_MODE,
1530 .muxregs = uart4_ext_71_72_muxreg,
1531 .nmuxregs = ARRAY_SIZE(uart4_ext_71_72_muxreg),
1532 },
1533 }, {
1534 /* Select signals on pins 92_93 */
1535 {
1536 .modes = EXTENDED_MODE,
1537 .muxregs = uart4_ext_92_93_muxreg,
1538 .nmuxregs = ARRAY_SIZE(uart4_ext_92_93_muxreg),
1539 },
1540 }, {
1541 /* Select signals on pins 100_101_ */
1542 {
1543 .modes = EXTENDED_MODE,
1544 .muxregs = uart4_ext_100_101_muxreg,
1545 .nmuxregs = ARRAY_SIZE(uart4_ext_100_101_muxreg),
1546 },
1547 },
1548};
1549
1550static struct spear_pingroup uart4_pingroup[] = {
1551 {
1552 .name = "uart4_6_7_grp",
1553 .pins = uart4_pins[0],
1554 .npins = ARRAY_SIZE(uart4_pins[0]),
1555 .modemuxs = uart4_modemux[0],
1556 .nmodemuxs = ARRAY_SIZE(uart4_modemux[0]),
1557 }, {
1558 .name = "uart4_13_14_grp",
1559 .pins = uart4_pins[1],
1560 .npins = ARRAY_SIZE(uart4_pins[1]),
1561 .modemuxs = uart4_modemux[1],
1562 .nmodemuxs = ARRAY_SIZE(uart4_modemux[1]),
1563 }, {
1564 .name = "uart4_39_40_grp",
1565 .pins = uart4_pins[2],
1566 .npins = ARRAY_SIZE(uart4_pins[2]),
1567 .modemuxs = uart4_modemux[2],
1568 .nmodemuxs = ARRAY_SIZE(uart4_modemux[2]),
1569 }, {
1570 .name = "uart4_71_72_grp",
1571 .pins = uart4_pins[3],
1572 .npins = ARRAY_SIZE(uart4_pins[3]),
1573 .modemuxs = uart4_modemux[3],
1574 .nmodemuxs = ARRAY_SIZE(uart4_modemux[3]),
1575 }, {
1576 .name = "uart4_92_93_grp",
1577 .pins = uart4_pins[4],
1578 .npins = ARRAY_SIZE(uart4_pins[4]),
1579 .modemuxs = uart4_modemux[4],
1580 .nmodemuxs = ARRAY_SIZE(uart4_modemux[4]),
1581 }, {
1582 .name = "uart4_100_101_grp",
1583 .pins = uart4_pins[5],
1584 .npins = ARRAY_SIZE(uart4_pins[5]),
1585 .modemuxs = uart4_modemux[5],
1586 .nmodemuxs = ARRAY_SIZE(uart4_modemux[5]),
1587 },
1588};
1589
1590static const char *const uart4_grps[] = { "uart4_6_7_grp", "uart4_13_14_grp",
1591 "uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp",
1592 "uart4_100_101_grp" };
1593
1594static struct spear_function uart4_function = {
1595 .name = "uart4",
1596 .groups = uart4_grps,
1597 .ngroups = ARRAY_SIZE(uart4_grps),
1598};
1599
1600/* Pad multiplexing for uart5 device */
1601static const unsigned uart5_pins[][2] = { { 4, 5 }, { 37, 38 }, { 69, 70 },
1602 { 90, 91 } };
1603
1604static struct spear_muxreg uart5_ext_4_5_muxreg[] = {
1605 {
1606 .reg = PMX_CONFIG_REG,
1607 .mask = PMX_I2C_MASK,
1608 .val = 0,
1609 }, {
1610 .reg = IP_SEL_PAD_0_9_REG,
1611 .mask = PMX_PL_4_5_MASK,
1612 .val = PMX_UART5_PL_4_5_VAL,
1613 }, {
1614 .reg = IP_SEL_MIX_PAD_REG,
1615 .mask = PMX_UART5_PORT_SEL_MASK,
1616 .val = PMX_UART5_PORT_4_VAL,
1617 },
1618};
1619
1620static struct spear_muxreg uart5_ext_37_38_muxreg[] = {
1621 {
1622 .reg = PMX_CONFIG_REG,
1623 .mask = PMX_UART0_MODEM_MASK,
1624 .val = 0,
1625 }, {
1626 .reg = IP_SEL_PAD_30_39_REG,
1627 .mask = PMX_PL_37_38_MASK,
1628 .val = PMX_UART5_PL_37_38_VAL,
1629 }, {
1630 .reg = IP_SEL_MIX_PAD_REG,
1631 .mask = PMX_UART5_PORT_SEL_MASK,
1632 .val = PMX_UART5_PORT_37_VAL,
1633 },
1634};
1635
1636static struct spear_muxreg uart5_ext_69_70_muxreg[] = {
1637 {
1638 .reg = IP_SEL_PAD_60_69_REG,
1639 .mask = PMX_PL_69_MASK,
1640 .val = PMX_UART5_PL_69_VAL,
1641 }, {
1642 .reg = IP_SEL_PAD_70_79_REG,
1643 .mask = PMX_PL_70_MASK,
1644 .val = PMX_UART5_PL_70_VAL,
1645 }, {
1646 .reg = IP_SEL_MIX_PAD_REG,
1647 .mask = PMX_UART5_PORT_SEL_MASK,
1648 .val = PMX_UART5_PORT_69_VAL,
1649 },
1650};
1651
1652static struct spear_muxreg uart5_ext_90_91_muxreg[] = {
1653 {
1654 .reg = IP_SEL_PAD_90_99_REG,
1655 .mask = PMX_PL_90_91_MASK,
1656 .val = PMX_UART5_PL_90_91_VAL,
1657 }, {
1658 .reg = IP_SEL_MIX_PAD_REG,
1659 .mask = PMX_UART5_PORT_SEL_MASK,
1660 .val = PMX_UART5_PORT_90_VAL,
1661 },
1662};
1663
1664static struct spear_modemux uart5_modemux[][1] = {
1665 {
1666 /* Select signals on pins 4_5 */
1667 {
1668 .modes = EXTENDED_MODE,
1669 .muxregs = uart5_ext_4_5_muxreg,
1670 .nmuxregs = ARRAY_SIZE(uart5_ext_4_5_muxreg),
1671 },
1672 }, {
1673 /* Select signals on pins 37_38 */
1674 {
1675 .modes = EXTENDED_MODE,
1676 .muxregs = uart5_ext_37_38_muxreg,
1677 .nmuxregs = ARRAY_SIZE(uart5_ext_37_38_muxreg),
1678 },
1679 }, {
1680 /* Select signals on pins 69_70 */
1681 {
1682 .modes = EXTENDED_MODE,
1683 .muxregs = uart5_ext_69_70_muxreg,
1684 .nmuxregs = ARRAY_SIZE(uart5_ext_69_70_muxreg),
1685 },
1686 }, {
1687 /* Select signals on pins 90_91 */
1688 {
1689 .modes = EXTENDED_MODE,
1690 .muxregs = uart5_ext_90_91_muxreg,
1691 .nmuxregs = ARRAY_SIZE(uart5_ext_90_91_muxreg),
1692 },
1693 },
1694};
1695
1696static struct spear_pingroup uart5_pingroup[] = {
1697 {
1698 .name = "uart5_4_5_grp",
1699 .pins = uart5_pins[0],
1700 .npins = ARRAY_SIZE(uart5_pins[0]),
1701 .modemuxs = uart5_modemux[0],
1702 .nmodemuxs = ARRAY_SIZE(uart5_modemux[0]),
1703 }, {
1704 .name = "uart5_37_38_grp",
1705 .pins = uart5_pins[1],
1706 .npins = ARRAY_SIZE(uart5_pins[1]),
1707 .modemuxs = uart5_modemux[1],
1708 .nmodemuxs = ARRAY_SIZE(uart5_modemux[1]),
1709 }, {
1710 .name = "uart5_69_70_grp",
1711 .pins = uart5_pins[2],
1712 .npins = ARRAY_SIZE(uart5_pins[2]),
1713 .modemuxs = uart5_modemux[2],
1714 .nmodemuxs = ARRAY_SIZE(uart5_modemux[2]),
1715 }, {
1716 .name = "uart5_90_91_grp",
1717 .pins = uart5_pins[3],
1718 .npins = ARRAY_SIZE(uart5_pins[3]),
1719 .modemuxs = uart5_modemux[3],
1720 .nmodemuxs = ARRAY_SIZE(uart5_modemux[3]),
1721 },
1722};
1723
1724static const char *const uart5_grps[] = { "uart5_4_5_grp", "uart5_37_38_grp",
1725 "uart5_69_70_grp", "uart5_90_91_grp" };
1726static struct spear_function uart5_function = {
1727 .name = "uart5",
1728 .groups = uart5_grps,
1729 .ngroups = ARRAY_SIZE(uart5_grps),
1730};
1731
1732/* Pad multiplexing for uart6 device */
1733static const unsigned uart6_pins[][2] = { { 2, 3 }, { 88, 89 } };
1734static struct spear_muxreg uart6_ext_2_3_muxreg[] = {
1735 {
1736 .reg = PMX_CONFIG_REG,
1737 .mask = PMX_UART0_MASK,
1738 .val = 0,
1739 }, {
1740 .reg = IP_SEL_PAD_0_9_REG,
1741 .mask = PMX_PL_2_3_MASK,
1742 .val = PMX_UART6_PL_2_3_VAL,
1743 }, {
1744 .reg = IP_SEL_MIX_PAD_REG,
1745 .mask = PMX_UART6_PORT_SEL_MASK,
1746 .val = PMX_UART6_PORT_2_VAL,
1747 },
1748};
1749
1750static struct spear_muxreg uart6_ext_88_89_muxreg[] = {
1751 {
1752 .reg = IP_SEL_PAD_80_89_REG,
1753 .mask = PMX_PL_88_89_MASK,
1754 .val = PMX_UART6_PL_88_89_VAL,
1755 }, {
1756 .reg = IP_SEL_MIX_PAD_REG,
1757 .mask = PMX_UART6_PORT_SEL_MASK,
1758 .val = PMX_UART6_PORT_88_VAL,
1759 },
1760};
1761
1762static struct spear_modemux uart6_modemux[][1] = {
1763 {
1764 /* Select signals on pins 2_3 */
1765 {
1766 .modes = EXTENDED_MODE,
1767 .muxregs = uart6_ext_2_3_muxreg,
1768 .nmuxregs = ARRAY_SIZE(uart6_ext_2_3_muxreg),
1769 },
1770 }, {
1771 /* Select signals on pins 88_89 */
1772 {
1773 .modes = EXTENDED_MODE,
1774 .muxregs = uart6_ext_88_89_muxreg,
1775 .nmuxregs = ARRAY_SIZE(uart6_ext_88_89_muxreg),
1776 },
1777 },
1778};
1779
1780static struct spear_pingroup uart6_pingroup[] = {
1781 {
1782 .name = "uart6_2_3_grp",
1783 .pins = uart6_pins[0],
1784 .npins = ARRAY_SIZE(uart6_pins[0]),
1785 .modemuxs = uart6_modemux[0],
1786 .nmodemuxs = ARRAY_SIZE(uart6_modemux[0]),
1787 }, {
1788 .name = "uart6_88_89_grp",
1789 .pins = uart6_pins[1],
1790 .npins = ARRAY_SIZE(uart6_pins[1]),
1791 .modemuxs = uart6_modemux[1],
1792 .nmodemuxs = ARRAY_SIZE(uart6_modemux[1]),
1793 },
1794};
1795
1796static const char *const uart6_grps[] = { "uart6_2_3_grp", "uart6_88_89_grp" };
1797static struct spear_function uart6_function = {
1798 .name = "uart6",
1799 .groups = uart6_grps,
1800 .ngroups = ARRAY_SIZE(uart6_grps),
1801};
1802
1803/* UART - RS485 pmx */
1804static const unsigned rs485_pins[] = { 77, 78, 79 };
1805static struct spear_muxreg rs485_muxreg[] = {
1806 {
1807 .reg = IP_SEL_PAD_70_79_REG,
1808 .mask = PMX_PL_77_78_79_MASK,
1809 .val = PMX_RS485_PL_77_78_79_VAL,
1810 },
1811};
1812
1813static struct spear_modemux rs485_modemux[] = {
1814 {
1815 .modes = EXTENDED_MODE,
1816 .muxregs = rs485_muxreg,
1817 .nmuxregs = ARRAY_SIZE(rs485_muxreg),
1818 },
1819};
1820
1821static struct spear_pingroup rs485_pingroup = {
1822 .name = "rs485_grp",
1823 .pins = rs485_pins,
1824 .npins = ARRAY_SIZE(rs485_pins),
1825 .modemuxs = rs485_modemux,
1826 .nmodemuxs = ARRAY_SIZE(rs485_modemux),
1827};
1828
1829static const char *const rs485_grps[] = { "rs485_grp" };
1830static struct spear_function rs485_function = {
1831 .name = "rs485",
1832 .groups = rs485_grps,
1833 .ngroups = ARRAY_SIZE(rs485_grps),
1834};
1835
1836/* Pad multiplexing for Touchscreen device */
1837static const unsigned touchscreen_pins[] = { 5, 36 };
1838static struct spear_muxreg touchscreen_muxreg[] = {
1839 {
1840 .reg = PMX_CONFIG_REG,
1841 .mask = PMX_I2C_MASK | PMX_SSP_CS_MASK,
1842 .val = 0,
1843 },
1844};
1845
1846static struct spear_muxreg touchscreen_ext_muxreg[] = {
1847 {
1848 .reg = IP_SEL_PAD_0_9_REG,
1849 .mask = PMX_PL_5_MASK,
1850 .val = PMX_TOUCH_Y_PL_5_VAL,
1851 }, {
1852 .reg = IP_SEL_PAD_30_39_REG,
1853 .mask = PMX_PL_36_MASK,
1854 .val = PMX_TOUCH_X_PL_36_VAL,
1855 },
1856};
1857
1858static struct spear_modemux touchscreen_modemux[] = {
1859 {
1860 .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE,
1861 .muxregs = touchscreen_muxreg,
1862 .nmuxregs = ARRAY_SIZE(touchscreen_muxreg),
1863 }, {
1864 .modes = EXTENDED_MODE,
1865 .muxregs = touchscreen_ext_muxreg,
1866 .nmuxregs = ARRAY_SIZE(touchscreen_ext_muxreg),
1867 },
1868};
1869
1870static struct spear_pingroup touchscreen_pingroup = {
1871 .name = "touchscreen_grp",
1872 .pins = touchscreen_pins,
1873 .npins = ARRAY_SIZE(touchscreen_pins),
1874 .modemuxs = touchscreen_modemux,
1875 .nmodemuxs = ARRAY_SIZE(touchscreen_modemux),
1876};
1877
1878static const char *const touchscreen_grps[] = { "touchscreen_grp" };
1879static struct spear_function touchscreen_function = {
1880 .name = "touchscreen",
1881 .groups = touchscreen_grps,
1882 .ngroups = ARRAY_SIZE(touchscreen_grps),
1883};
1884
1885/* Pad multiplexing for CAN device */
1886static const unsigned can0_pins[] = { 32, 33 };
1887static struct spear_muxreg can0_muxreg[] = {
1888 {
1889 .reg = PMX_CONFIG_REG,
1890 .mask = PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
1891 .val = 0,
1892 },
1893};
1894
1895static struct spear_muxreg can0_ext_muxreg[] = {
1896 {
1897 .reg = IP_SEL_PAD_30_39_REG,
1898 .mask = PMX_PL_32_33_MASK,
1899 .val = PMX_CAN0_PL_32_33_VAL,
1900 },
1901};
1902
1903static struct spear_modemux can0_modemux[] = {
1904 {
1905 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
1906 | EXTENDED_MODE,
1907 .muxregs = can0_muxreg,
1908 .nmuxregs = ARRAY_SIZE(can0_muxreg),
1909 }, {
1910 .modes = EXTENDED_MODE,
1911 .muxregs = can0_ext_muxreg,
1912 .nmuxregs = ARRAY_SIZE(can0_ext_muxreg),
1913 },
1914};
1915
1916static struct spear_pingroup can0_pingroup = {
1917 .name = "can0_grp",
1918 .pins = can0_pins,
1919 .npins = ARRAY_SIZE(can0_pins),
1920 .modemuxs = can0_modemux,
1921 .nmodemuxs = ARRAY_SIZE(can0_modemux),
1922};
1923
1924static const char *const can0_grps[] = { "can0_grp" };
1925static struct spear_function can0_function = {
1926 .name = "can0",
1927 .groups = can0_grps,
1928 .ngroups = ARRAY_SIZE(can0_grps),
1929};
1930
1931static const unsigned can1_pins[] = { 30, 31 };
1932static struct spear_muxreg can1_muxreg[] = {
1933 {
1934 .reg = PMX_CONFIG_REG,
1935 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK,
1936 .val = 0,
1937 },
1938};
1939
1940static struct spear_muxreg can1_ext_muxreg[] = {
1941 {
1942 .reg = IP_SEL_PAD_30_39_REG,
1943 .mask = PMX_PL_30_31_MASK,
1944 .val = PMX_CAN1_PL_30_31_VAL,
1945 },
1946};
1947
1948static struct spear_modemux can1_modemux[] = {
1949 {
1950 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
1951 | EXTENDED_MODE,
1952 .muxregs = can1_muxreg,
1953 .nmuxregs = ARRAY_SIZE(can1_muxreg),
1954 }, {
1955 .modes = EXTENDED_MODE,
1956 .muxregs = can1_ext_muxreg,
1957 .nmuxregs = ARRAY_SIZE(can1_ext_muxreg),
1958 },
1959};
1960
1961static struct spear_pingroup can1_pingroup = {
1962 .name = "can1_grp",
1963 .pins = can1_pins,
1964 .npins = ARRAY_SIZE(can1_pins),
1965 .modemuxs = can1_modemux,
1966 .nmodemuxs = ARRAY_SIZE(can1_modemux),
1967};
1968
1969static const char *const can1_grps[] = { "can1_grp" };
1970static struct spear_function can1_function = {
1971 .name = "can1",
1972 .groups = can1_grps,
1973 .ngroups = ARRAY_SIZE(can1_grps),
1974};
1975
1976/* Pad multiplexing for PWM0_1 device */
1977static const unsigned pwm0_1_pins[][2] = { { 37, 38 }, { 14, 15 }, { 8, 9 },
1978 { 30, 31 }, { 42, 43 }, { 59, 60 }, { 88, 89 } };
1979
1980static struct spear_muxreg pwm0_1_pin_8_9_muxreg[] = {
1981 {
1982 .reg = PMX_CONFIG_REG,
1983 .mask = PMX_SSP_MASK,
1984 .val = 0,
1985 }, {
1986 .reg = IP_SEL_PAD_0_9_REG,
1987 .mask = PMX_PL_8_9_MASK,
1988 .val = PMX_PWM_0_1_PL_8_9_VAL,
1989 },
1990};
1991
1992static struct spear_muxreg pwm0_1_autoexpsmallpri_muxreg[] = {
1993 {
1994 .reg = PMX_CONFIG_REG,
1995 .mask = PMX_MII_MASK,
1996 .val = 0,
1997 },
1998};
1999
2000static struct spear_muxreg pwm0_1_pin_14_15_muxreg[] = {
2001 {
2002 .reg = IP_SEL_PAD_10_19_REG,
2003 .mask = PMX_PL_14_MASK | PMX_PL_15_MASK,
2004 .val = PMX_PWM1_PL_14_VAL | PMX_PWM0_PL_15_VAL,
2005 },
2006};
2007
2008static struct spear_muxreg pwm0_1_pin_30_31_muxreg[] = {
2009 {
2010 .reg = PMX_CONFIG_REG,
2011 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK,
2012 .val = 0,
2013 }, {
2014 .reg = IP_SEL_PAD_30_39_REG,
2015 .mask = PMX_PL_30_MASK | PMX_PL_31_MASK,
2016 .val = PMX_PWM1_EXT_PL_30_VAL | PMX_PWM0_EXT_PL_31_VAL,
2017 },
2018};
2019
2020static struct spear_muxreg pwm0_1_net_muxreg[] = {
2021 {
2022 .reg = PMX_CONFIG_REG,
2023 .mask = PMX_UART0_MODEM_MASK,
2024 .val = 0,
2025 },
2026};
2027
2028static struct spear_muxreg pwm0_1_pin_37_38_muxreg[] = {
2029 {
2030 .reg = IP_SEL_PAD_30_39_REG,
2031 .mask = PMX_PL_37_38_MASK,
2032 .val = PMX_PWM0_1_PL_37_38_VAL,
2033 },
2034};
2035
2036static struct spear_muxreg pwm0_1_pin_42_43_muxreg[] = {
2037 {
2038 .reg = PMX_CONFIG_REG,
2039 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_0_1_MASK ,
2040 .val = 0,
2041 }, {
2042 .reg = IP_SEL_PAD_40_49_REG,
2043 .mask = PMX_PL_42_MASK | PMX_PL_43_MASK,
2044 .val = PMX_PWM1_PL_42_VAL |
2045 PMX_PWM0_PL_43_VAL,
2046 },
2047};
2048
2049static struct spear_muxreg pwm0_1_pin_59_60_muxreg[] = {
2050 {
2051 .reg = IP_SEL_PAD_50_59_REG,
2052 .mask = PMX_PL_59_MASK,
2053 .val = PMX_PWM1_PL_59_VAL,
2054 }, {
2055 .reg = IP_SEL_PAD_60_69_REG,
2056 .mask = PMX_PL_60_MASK,
2057 .val = PMX_PWM0_PL_60_VAL,
2058 },
2059};
2060
2061static struct spear_muxreg pwm0_1_pin_88_89_muxreg[] = {
2062 {
2063 .reg = IP_SEL_PAD_80_89_REG,
2064 .mask = PMX_PL_88_89_MASK,
2065 .val = PMX_PWM0_1_PL_88_89_VAL,
2066 },
2067};
2068
2069static struct spear_modemux pwm0_1_pin_8_9_modemux[] = {
2070 {
2071 .modes = EXTENDED_MODE,
2072 .muxregs = pwm0_1_pin_8_9_muxreg,
2073 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_8_9_muxreg),
2074 },
2075};
2076
2077static struct spear_modemux pwm0_1_pin_14_15_modemux[] = {
2078 {
2079 .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE,
2080 .muxregs = pwm0_1_autoexpsmallpri_muxreg,
2081 .nmuxregs = ARRAY_SIZE(pwm0_1_autoexpsmallpri_muxreg),
2082 }, {
2083 .modes = EXTENDED_MODE,
2084 .muxregs = pwm0_1_pin_14_15_muxreg,
2085 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_14_15_muxreg),
2086 },
2087};
2088
2089static struct spear_modemux pwm0_1_pin_30_31_modemux[] = {
2090 {
2091 .modes = EXTENDED_MODE,
2092 .muxregs = pwm0_1_pin_30_31_muxreg,
2093 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_30_31_muxreg),
2094 },
2095};
2096
2097static struct spear_modemux pwm0_1_pin_37_38_modemux[] = {
2098 {
2099 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
2100 .muxregs = pwm0_1_net_muxreg,
2101 .nmuxregs = ARRAY_SIZE(pwm0_1_net_muxreg),
2102 }, {
2103 .modes = EXTENDED_MODE,
2104 .muxregs = pwm0_1_pin_37_38_muxreg,
2105 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_37_38_muxreg),
2106 },
2107};
2108
2109static struct spear_modemux pwm0_1_pin_42_43_modemux[] = {
2110 {
2111 .modes = EXTENDED_MODE,
2112 .muxregs = pwm0_1_pin_42_43_muxreg,
2113 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_42_43_muxreg),
2114 },
2115};
2116
2117static struct spear_modemux pwm0_1_pin_59_60_modemux[] = {
2118 {
2119 .modes = EXTENDED_MODE,
2120 .muxregs = pwm0_1_pin_59_60_muxreg,
2121 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_59_60_muxreg),
2122 },
2123};
2124
2125static struct spear_modemux pwm0_1_pin_88_89_modemux[] = {
2126 {
2127 .modes = EXTENDED_MODE,
2128 .muxregs = pwm0_1_pin_88_89_muxreg,
2129 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_88_89_muxreg),
2130 },
2131};
2132
2133static struct spear_pingroup pwm0_1_pingroup[] = {
2134 {
2135 .name = "pwm0_1_pin_8_9_grp",
2136 .pins = pwm0_1_pins[0],
2137 .npins = ARRAY_SIZE(pwm0_1_pins[0]),
2138 .modemuxs = pwm0_1_pin_8_9_modemux,
2139 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_8_9_modemux),
2140 }, {
2141 .name = "pwm0_1_pin_14_15_grp",
2142 .pins = pwm0_1_pins[1],
2143 .npins = ARRAY_SIZE(pwm0_1_pins[1]),
2144 .modemuxs = pwm0_1_pin_14_15_modemux,
2145 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_14_15_modemux),
2146 }, {
2147 .name = "pwm0_1_pin_30_31_grp",
2148 .pins = pwm0_1_pins[2],
2149 .npins = ARRAY_SIZE(pwm0_1_pins[2]),
2150 .modemuxs = pwm0_1_pin_30_31_modemux,
2151 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_30_31_modemux),
2152 }, {
2153 .name = "pwm0_1_pin_37_38_grp",
2154 .pins = pwm0_1_pins[3],
2155 .npins = ARRAY_SIZE(pwm0_1_pins[3]),
2156 .modemuxs = pwm0_1_pin_37_38_modemux,
2157 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_37_38_modemux),
2158 }, {
2159 .name = "pwm0_1_pin_42_43_grp",
2160 .pins = pwm0_1_pins[4],
2161 .npins = ARRAY_SIZE(pwm0_1_pins[4]),
2162 .modemuxs = pwm0_1_pin_42_43_modemux,
2163 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_42_43_modemux),
2164 }, {
2165 .name = "pwm0_1_pin_59_60_grp",
2166 .pins = pwm0_1_pins[5],
2167 .npins = ARRAY_SIZE(pwm0_1_pins[5]),
2168 .modemuxs = pwm0_1_pin_59_60_modemux,
2169 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_59_60_modemux),
2170 }, {
2171 .name = "pwm0_1_pin_88_89_grp",
2172 .pins = pwm0_1_pins[6],
2173 .npins = ARRAY_SIZE(pwm0_1_pins[6]),
2174 .modemuxs = pwm0_1_pin_88_89_modemux,
2175 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_88_89_modemux),
2176 },
2177};
2178
2179static const char *const pwm0_1_grps[] = { "pwm0_1_pin_8_9_grp",
2180 "pwm0_1_pin_14_15_grp", "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp",
2181 "pwm0_1_pin_42_43_grp", "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp"
2182};
2183
2184static struct spear_function pwm0_1_function = {
2185 .name = "pwm0_1",
2186 .groups = pwm0_1_grps,
2187 .ngroups = ARRAY_SIZE(pwm0_1_grps),
2188};
2189
2190/* Pad multiplexing for PWM2 device */
2191static const unsigned pwm2_pins[][1] = { { 7 }, { 13 }, { 29 }, { 34 }, { 41 },
2192 { 58 }, { 87 } };
2193static struct spear_muxreg pwm2_net_muxreg[] = {
2194 {
2195 .reg = PMX_CONFIG_REG,
2196 .mask = PMX_SSP_CS_MASK,
2197 .val = 0,
2198 },
2199};
2200
2201static struct spear_muxreg pwm2_pin_7_muxreg[] = {
2202 {
2203 .reg = IP_SEL_PAD_0_9_REG,
2204 .mask = PMX_PL_7_MASK,
2205 .val = PMX_PWM_2_PL_7_VAL,
2206 },
2207};
2208
2209static struct spear_muxreg pwm2_autoexpsmallpri_muxreg[] = {
2210 {
2211 .reg = PMX_CONFIG_REG,
2212 .mask = PMX_MII_MASK,
2213 .val = 0,
2214 },
2215};
2216
2217static struct spear_muxreg pwm2_pin_13_muxreg[] = {
2218 {
2219 .reg = IP_SEL_PAD_10_19_REG,
2220 .mask = PMX_PL_13_MASK,
2221 .val = PMX_PWM2_PL_13_VAL,
2222 },
2223};
2224
2225static struct spear_muxreg pwm2_pin_29_muxreg[] = {
2226 {
2227 .reg = PMX_CONFIG_REG,
2228 .mask = PMX_GPIO_PIN1_MASK,
2229 .val = 0,
2230 }, {
2231 .reg = IP_SEL_PAD_20_29_REG,
2232 .mask = PMX_PL_29_MASK,
2233 .val = PMX_PWM_2_PL_29_VAL,
2234 },
2235};
2236
2237static struct spear_muxreg pwm2_pin_34_muxreg[] = {
2238 {
2239 .reg = PMX_CONFIG_REG,
2240 .mask = PMX_SSP_CS_MASK,
2241 .val = 0,
2242 }, {
2243 .reg = IP_SEL_PAD_30_39_REG,
2244 .mask = PMX_PL_34_MASK,
2245 .val = PMX_PWM2_PL_34_VAL,
2246 },
2247};
2248
2249static struct spear_muxreg pwm2_pin_41_muxreg[] = {
2250 {
2251 .reg = PMX_CONFIG_REG,
2252 .mask = PMX_UART0_MODEM_MASK,
2253 .val = 0,
2254 }, {
2255 .reg = IP_SEL_PAD_40_49_REG,
2256 .mask = PMX_PL_41_MASK,
2257 .val = PMX_PWM2_PL_41_VAL,
2258 },
2259};
2260
2261static struct spear_muxreg pwm2_pin_58_muxreg[] = {
2262 {
2263 .reg = IP_SEL_PAD_50_59_REG,
2264 .mask = PMX_PL_58_MASK,
2265 .val = PMX_PWM2_PL_58_VAL,
2266 },
2267};
2268
2269static struct spear_muxreg pwm2_pin_87_muxreg[] = {
2270 {
2271 .reg = IP_SEL_PAD_80_89_REG,
2272 .mask = PMX_PL_87_MASK,
2273 .val = PMX_PWM2_PL_87_VAL,
2274 },
2275};
2276
2277static struct spear_modemux pwm2_pin_7_modemux[] = {
2278 {
2279 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
2280 .muxregs = pwm2_net_muxreg,
2281 .nmuxregs = ARRAY_SIZE(pwm2_net_muxreg),
2282 }, {
2283 .modes = EXTENDED_MODE,
2284 .muxregs = pwm2_pin_7_muxreg,
2285 .nmuxregs = ARRAY_SIZE(pwm2_pin_7_muxreg),
2286 },
2287};
2288static struct spear_modemux pwm2_pin_13_modemux[] = {
2289 {
2290 .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE,
2291 .muxregs = pwm2_autoexpsmallpri_muxreg,
2292 .nmuxregs = ARRAY_SIZE(pwm2_autoexpsmallpri_muxreg),
2293 }, {
2294 .modes = EXTENDED_MODE,
2295 .muxregs = pwm2_pin_13_muxreg,
2296 .nmuxregs = ARRAY_SIZE(pwm2_pin_13_muxreg),
2297 },
2298};
2299static struct spear_modemux pwm2_pin_29_modemux[] = {
2300 {
2301 .modes = EXTENDED_MODE,
2302 .muxregs = pwm2_pin_29_muxreg,
2303 .nmuxregs = ARRAY_SIZE(pwm2_pin_29_muxreg),
2304 },
2305};
2306static struct spear_modemux pwm2_pin_34_modemux[] = {
2307 {
2308 .modes = EXTENDED_MODE,
2309 .muxregs = pwm2_pin_34_muxreg,
2310 .nmuxregs = ARRAY_SIZE(pwm2_pin_34_muxreg),
2311 },
2312};
2313
2314static struct spear_modemux pwm2_pin_41_modemux[] = {
2315 {
2316 .modes = EXTENDED_MODE,
2317 .muxregs = pwm2_pin_41_muxreg,
2318 .nmuxregs = ARRAY_SIZE(pwm2_pin_41_muxreg),
2319 },
2320};
2321
2322static struct spear_modemux pwm2_pin_58_modemux[] = {
2323 {
2324 .modes = EXTENDED_MODE,
2325 .muxregs = pwm2_pin_58_muxreg,
2326 .nmuxregs = ARRAY_SIZE(pwm2_pin_58_muxreg),
2327 },
2328};
2329
2330static struct spear_modemux pwm2_pin_87_modemux[] = {
2331 {
2332 .modes = EXTENDED_MODE,
2333 .muxregs = pwm2_pin_87_muxreg,
2334 .nmuxregs = ARRAY_SIZE(pwm2_pin_87_muxreg),
2335 },
2336};
2337
2338static struct spear_pingroup pwm2_pingroup[] = {
2339 {
2340 .name = "pwm2_pin_7_grp",
2341 .pins = pwm2_pins[0],
2342 .npins = ARRAY_SIZE(pwm2_pins[0]),
2343 .modemuxs = pwm2_pin_7_modemux,
2344 .nmodemuxs = ARRAY_SIZE(pwm2_pin_7_modemux),
2345 }, {
2346 .name = "pwm2_pin_13_grp",
2347 .pins = pwm2_pins[1],
2348 .npins = ARRAY_SIZE(pwm2_pins[1]),
2349 .modemuxs = pwm2_pin_13_modemux,
2350 .nmodemuxs = ARRAY_SIZE(pwm2_pin_13_modemux),
2351 }, {
2352 .name = "pwm2_pin_29_grp",
2353 .pins = pwm2_pins[2],
2354 .npins = ARRAY_SIZE(pwm2_pins[2]),
2355 .modemuxs = pwm2_pin_29_modemux,
2356 .nmodemuxs = ARRAY_SIZE(pwm2_pin_29_modemux),
2357 }, {
2358 .name = "pwm2_pin_34_grp",
2359 .pins = pwm2_pins[3],
2360 .npins = ARRAY_SIZE(pwm2_pins[3]),
2361 .modemuxs = pwm2_pin_34_modemux,
2362 .nmodemuxs = ARRAY_SIZE(pwm2_pin_34_modemux),
2363 }, {
2364 .name = "pwm2_pin_41_grp",
2365 .pins = pwm2_pins[4],
2366 .npins = ARRAY_SIZE(pwm2_pins[4]),
2367 .modemuxs = pwm2_pin_41_modemux,
2368 .nmodemuxs = ARRAY_SIZE(pwm2_pin_41_modemux),
2369 }, {
2370 .name = "pwm2_pin_58_grp",
2371 .pins = pwm2_pins[5],
2372 .npins = ARRAY_SIZE(pwm2_pins[5]),
2373 .modemuxs = pwm2_pin_58_modemux,
2374 .nmodemuxs = ARRAY_SIZE(pwm2_pin_58_modemux),
2375 }, {
2376 .name = "pwm2_pin_87_grp",
2377 .pins = pwm2_pins[6],
2378 .npins = ARRAY_SIZE(pwm2_pins[6]),
2379 .modemuxs = pwm2_pin_87_modemux,
2380 .nmodemuxs = ARRAY_SIZE(pwm2_pin_87_modemux),
2381 },
2382};
2383
2384static const char *const pwm2_grps[] = { "pwm2_pin_7_grp", "pwm2_pin_13_grp",
2385 "pwm2_pin_29_grp", "pwm2_pin_34_grp", "pwm2_pin_41_grp",
2386 "pwm2_pin_58_grp", "pwm2_pin_87_grp" };
2387static struct spear_function pwm2_function = {
2388 .name = "pwm2",
2389 .groups = pwm2_grps,
2390 .ngroups = ARRAY_SIZE(pwm2_grps),
2391};
2392
2393/* Pad multiplexing for PWM3 device */
2394static const unsigned pwm3_pins[][1] = { { 6 }, { 12 }, { 28 }, { 40 }, { 57 },
2395 { 86 } };
2396static struct spear_muxreg pwm3_pin_6_muxreg[] = {
2397 {
2398 .reg = PMX_CONFIG_REG,
2399 .mask = PMX_SSP_MASK,
2400 .val = 0,
2401 }, {
2402 .reg = IP_SEL_PAD_0_9_REG,
2403 .mask = PMX_PL_6_MASK,
2404 .val = PMX_PWM_3_PL_6_VAL,
2405 },
2406};
2407
2408static struct spear_muxreg pwm3_muxreg[] = {
2409 {
2410 .reg = PMX_CONFIG_REG,
2411 .mask = PMX_MII_MASK,
2412 .val = 0,
2413 },
2414};
2415
2416static struct spear_muxreg pwm3_pin_12_muxreg[] = {
2417 {
2418 .reg = IP_SEL_PAD_10_19_REG,
2419 .mask = PMX_PL_12_MASK,
2420 .val = PMX_PWM3_PL_12_VAL,
2421 },
2422};
2423
2424static struct spear_muxreg pwm3_pin_28_muxreg[] = {
2425 {
2426 .reg = PMX_CONFIG_REG,
2427 .mask = PMX_GPIO_PIN0_MASK,
2428 .val = 0,
2429 }, {
2430 .reg = IP_SEL_PAD_20_29_REG,
2431 .mask = PMX_PL_28_MASK,
2432 .val = PMX_PWM_3_PL_28_VAL,
2433 },
2434};
2435
2436static struct spear_muxreg pwm3_pin_40_muxreg[] = {
2437 {
2438 .reg = PMX_CONFIG_REG,
2439 .mask = PMX_UART0_MODEM_MASK,
2440 .val = 0,
2441 }, {
2442 .reg = IP_SEL_PAD_40_49_REG,
2443 .mask = PMX_PL_40_MASK,
2444 .val = PMX_PWM3_PL_40_VAL,
2445 },
2446};
2447
2448static struct spear_muxreg pwm3_pin_57_muxreg[] = {
2449 {
2450 .reg = IP_SEL_PAD_50_59_REG,
2451 .mask = PMX_PL_57_MASK,
2452 .val = PMX_PWM3_PL_57_VAL,
2453 },
2454};
2455
2456static struct spear_muxreg pwm3_pin_86_muxreg[] = {
2457 {
2458 .reg = IP_SEL_PAD_80_89_REG,
2459 .mask = PMX_PL_86_MASK,
2460 .val = PMX_PWM3_PL_86_VAL,
2461 },
2462};
2463
2464static struct spear_modemux pwm3_pin_6_modemux[] = {
2465 {
2466 .modes = EXTENDED_MODE,
2467 .muxregs = pwm3_pin_6_muxreg,
2468 .nmuxregs = ARRAY_SIZE(pwm3_pin_6_muxreg),
2469 },
2470};
2471
2472static struct spear_modemux pwm3_pin_12_modemux[] = {
2473 {
2474 .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE |
2475 AUTO_NET_SMII_MODE | EXTENDED_MODE,
2476 .muxregs = pwm3_muxreg,
2477 .nmuxregs = ARRAY_SIZE(pwm3_muxreg),
2478 }, {
2479 .modes = EXTENDED_MODE,
2480 .muxregs = pwm3_pin_12_muxreg,
2481 .nmuxregs = ARRAY_SIZE(pwm3_pin_12_muxreg),
2482 },
2483};
2484
2485static struct spear_modemux pwm3_pin_28_modemux[] = {
2486 {
2487 .modes = EXTENDED_MODE,
2488 .muxregs = pwm3_pin_28_muxreg,
2489 .nmuxregs = ARRAY_SIZE(pwm3_pin_28_muxreg),
2490 },
2491};
2492
2493static struct spear_modemux pwm3_pin_40_modemux[] = {
2494 {
2495 .modes = EXTENDED_MODE,
2496 .muxregs = pwm3_pin_40_muxreg,
2497 .nmuxregs = ARRAY_SIZE(pwm3_pin_40_muxreg),
2498 },
2499};
2500
2501static struct spear_modemux pwm3_pin_57_modemux[] = {
2502 {
2503 .modes = EXTENDED_MODE,
2504 .muxregs = pwm3_pin_57_muxreg,
2505 .nmuxregs = ARRAY_SIZE(pwm3_pin_57_muxreg),
2506 },
2507};
2508
2509static struct spear_modemux pwm3_pin_86_modemux[] = {
2510 {
2511 .modes = EXTENDED_MODE,
2512 .muxregs = pwm3_pin_86_muxreg,
2513 .nmuxregs = ARRAY_SIZE(pwm3_pin_86_muxreg),
2514 },
2515};
2516
2517static struct spear_pingroup pwm3_pingroup[] = {
2518 {
2519 .name = "pwm3_pin_6_grp",
2520 .pins = pwm3_pins[0],
2521 .npins = ARRAY_SIZE(pwm3_pins[0]),
2522 .modemuxs = pwm3_pin_6_modemux,
2523 .nmodemuxs = ARRAY_SIZE(pwm3_pin_6_modemux),
2524 }, {
2525 .name = "pwm3_pin_12_grp",
2526 .pins = pwm3_pins[1],
2527 .npins = ARRAY_SIZE(pwm3_pins[1]),
2528 .modemuxs = pwm3_pin_12_modemux,
2529 .nmodemuxs = ARRAY_SIZE(pwm3_pin_12_modemux),
2530 }, {
2531 .name = "pwm3_pin_28_grp",
2532 .pins = pwm3_pins[2],
2533 .npins = ARRAY_SIZE(pwm3_pins[2]),
2534 .modemuxs = pwm3_pin_28_modemux,
2535 .nmodemuxs = ARRAY_SIZE(pwm3_pin_28_modemux),
2536 }, {
2537 .name = "pwm3_pin_40_grp",
2538 .pins = pwm3_pins[3],
2539 .npins = ARRAY_SIZE(pwm3_pins[3]),
2540 .modemuxs = pwm3_pin_40_modemux,
2541 .nmodemuxs = ARRAY_SIZE(pwm3_pin_40_modemux),
2542 }, {
2543 .name = "pwm3_pin_57_grp",
2544 .pins = pwm3_pins[4],
2545 .npins = ARRAY_SIZE(pwm3_pins[4]),
2546 .modemuxs = pwm3_pin_57_modemux,
2547 .nmodemuxs = ARRAY_SIZE(pwm3_pin_57_modemux),
2548 }, {
2549 .name = "pwm3_pin_86_grp",
2550 .pins = pwm3_pins[5],
2551 .npins = ARRAY_SIZE(pwm3_pins[5]),
2552 .modemuxs = pwm3_pin_86_modemux,
2553 .nmodemuxs = ARRAY_SIZE(pwm3_pin_86_modemux),
2554 },
2555};
2556
2557static const char *const pwm3_grps[] = { "pwm3_pin_6_grp", "pwm3_pin_12_grp",
2558 "pwm3_pin_28_grp", "pwm3_pin_40_grp", "pwm3_pin_57_grp",
2559 "pwm3_pin_86_grp" };
2560static struct spear_function pwm3_function = {
2561 .name = "pwm3",
2562 .groups = pwm3_grps,
2563 .ngroups = ARRAY_SIZE(pwm3_grps),
2564};
2565
2566/* Pad multiplexing for SSP1 device */
2567static const unsigned ssp1_pins[][2] = { { 17, 20 }, { 36, 39 }, { 48, 51 },
2568 { 65, 68 }, { 94, 97 } };
2569static struct spear_muxreg ssp1_muxreg[] = {
2570 {
2571 .reg = PMX_CONFIG_REG,
2572 .mask = PMX_MII_MASK,
2573 .val = 0,
2574 },
2575};
2576
2577static struct spear_muxreg ssp1_ext_17_20_muxreg[] = {
2578 {
2579 .reg = IP_SEL_PAD_10_19_REG,
2580 .mask = PMX_PL_17_18_MASK | PMX_PL_19_MASK,
2581 .val = PMX_SSP1_PL_17_18_19_20_VAL,
2582 }, {
2583 .reg = IP_SEL_PAD_20_29_REG,
2584 .mask = PMX_PL_20_MASK,
2585 .val = PMX_SSP1_PL_17_18_19_20_VAL,
2586 }, {
2587 .reg = IP_SEL_MIX_PAD_REG,
2588 .mask = PMX_SSP1_PORT_SEL_MASK,
2589 .val = PMX_SSP1_PORT_17_TO_20_VAL,
2590 },
2591};
2592
2593static struct spear_muxreg ssp1_ext_36_39_muxreg[] = {
2594 {
2595 .reg = PMX_CONFIG_REG,
2596 .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
2597 .val = 0,
2598 }, {
2599 .reg = IP_SEL_PAD_30_39_REG,
2600 .mask = PMX_PL_36_MASK | PMX_PL_37_38_MASK | PMX_PL_39_MASK,
2601 .val = PMX_SSP1_PL_36_VAL | PMX_SSP1_PL_37_38_VAL |
2602 PMX_SSP1_PL_39_VAL,
2603 }, {
2604 .reg = IP_SEL_MIX_PAD_REG,
2605 .mask = PMX_SSP1_PORT_SEL_MASK,
2606 .val = PMX_SSP1_PORT_36_TO_39_VAL,
2607 },
2608};
2609
2610static struct spear_muxreg ssp1_ext_48_51_muxreg[] = {
2611 {
2612 .reg = PMX_CONFIG_REG,
2613 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
2614 .val = 0,
2615 }, {
2616 .reg = IP_SEL_PAD_40_49_REG,
2617 .mask = PMX_PL_48_49_MASK,
2618 .val = PMX_SSP1_PL_48_49_VAL,
2619 }, {
2620 .reg = IP_SEL_PAD_50_59_REG,
2621 .mask = PMX_PL_50_51_MASK,
2622 .val = PMX_SSP1_PL_50_51_VAL,
2623 }, {
2624 .reg = IP_SEL_MIX_PAD_REG,
2625 .mask = PMX_SSP1_PORT_SEL_MASK,
2626 .val = PMX_SSP1_PORT_48_TO_51_VAL,
2627 },
2628};
2629
2630static struct spear_muxreg ssp1_ext_65_68_muxreg[] = {
2631 {
2632 .reg = IP_SEL_PAD_60_69_REG,
2633 .mask = PMX_PL_65_TO_68_MASK,
2634 .val = PMX_SSP1_PL_65_TO_68_VAL,
2635 }, {
2636 .reg = IP_SEL_MIX_PAD_REG,
2637 .mask = PMX_SSP1_PORT_SEL_MASK,
2638 .val = PMX_SSP1_PORT_65_TO_68_VAL,
2639 },
2640};
2641
2642static struct spear_muxreg ssp1_ext_94_97_muxreg[] = {
2643 {
2644 .reg = IP_SEL_PAD_90_99_REG,
2645 .mask = PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
2646 .val = PMX_SSP1_PL_94_95_VAL | PMX_SSP1_PL_96_97_VAL,
2647 }, {
2648 .reg = IP_SEL_MIX_PAD_REG,
2649 .mask = PMX_SSP1_PORT_SEL_MASK,
2650 .val = PMX_SSP1_PORT_94_TO_97_VAL,
2651 },
2652};
2653
2654static struct spear_modemux ssp1_17_20_modemux[] = {
2655 {
2656 .modes = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE |
2657 EXTENDED_MODE,
2658 .muxregs = ssp1_muxreg,
2659 .nmuxregs = ARRAY_SIZE(ssp1_muxreg),
2660 }, {
2661 .modes = EXTENDED_MODE,
2662 .muxregs = ssp1_ext_17_20_muxreg,
2663 .nmuxregs = ARRAY_SIZE(ssp1_ext_17_20_muxreg),
2664 },
2665};
2666
2667static struct spear_modemux ssp1_36_39_modemux[] = {
2668 {
2669 .modes = EXTENDED_MODE,
2670 .muxregs = ssp1_ext_36_39_muxreg,
2671 .nmuxregs = ARRAY_SIZE(ssp1_ext_36_39_muxreg),
2672 },
2673};
2674
2675static struct spear_modemux ssp1_48_51_modemux[] = {
2676 {
2677 .modes = EXTENDED_MODE,
2678 .muxregs = ssp1_ext_48_51_muxreg,
2679 .nmuxregs = ARRAY_SIZE(ssp1_ext_48_51_muxreg),
2680 },
2681};
2682static struct spear_modemux ssp1_65_68_modemux[] = {
2683 {
2684 .modes = EXTENDED_MODE,
2685 .muxregs = ssp1_ext_65_68_muxreg,
2686 .nmuxregs = ARRAY_SIZE(ssp1_ext_65_68_muxreg),
2687 },
2688};
2689
2690static struct spear_modemux ssp1_94_97_modemux[] = {
2691 {
2692 .modes = EXTENDED_MODE,
2693 .muxregs = ssp1_ext_94_97_muxreg,
2694 .nmuxregs = ARRAY_SIZE(ssp1_ext_94_97_muxreg),
2695 },
2696};
2697
2698static struct spear_pingroup ssp1_pingroup[] = {
2699 {
2700 .name = "ssp1_17_20_grp",
2701 .pins = ssp1_pins[0],
2702 .npins = ARRAY_SIZE(ssp1_pins[0]),
2703 .modemuxs = ssp1_17_20_modemux,
2704 .nmodemuxs = ARRAY_SIZE(ssp1_17_20_modemux),
2705 }, {
2706 .name = "ssp1_36_39_grp",
2707 .pins = ssp1_pins[1],
2708 .npins = ARRAY_SIZE(ssp1_pins[1]),
2709 .modemuxs = ssp1_36_39_modemux,
2710 .nmodemuxs = ARRAY_SIZE(ssp1_36_39_modemux),
2711 }, {
2712 .name = "ssp1_48_51_grp",
2713 .pins = ssp1_pins[2],
2714 .npins = ARRAY_SIZE(ssp1_pins[2]),
2715 .modemuxs = ssp1_48_51_modemux,
2716 .nmodemuxs = ARRAY_SIZE(ssp1_48_51_modemux),
2717 }, {
2718 .name = "ssp1_65_68_grp",
2719 .pins = ssp1_pins[3],
2720 .npins = ARRAY_SIZE(ssp1_pins[3]),
2721 .modemuxs = ssp1_65_68_modemux,
2722 .nmodemuxs = ARRAY_SIZE(ssp1_65_68_modemux),
2723 }, {
2724 .name = "ssp1_94_97_grp",
2725 .pins = ssp1_pins[4],
2726 .npins = ARRAY_SIZE(ssp1_pins[4]),
2727 .modemuxs = ssp1_94_97_modemux,
2728 .nmodemuxs = ARRAY_SIZE(ssp1_94_97_modemux),
2729 },
2730};
2731
2732static const char *const ssp1_grps[] = { "ssp1_17_20_grp", "ssp1_36_39_grp",
2733 "ssp1_48_51_grp", "ssp1_65_68_grp", "ssp1_94_97_grp"
2734};
2735static struct spear_function ssp1_function = {
2736 .name = "ssp1",
2737 .groups = ssp1_grps,
2738 .ngroups = ARRAY_SIZE(ssp1_grps),
2739};
2740
2741/* Pad multiplexing for SSP2 device */
2742static const unsigned ssp2_pins[][2] = { { 13, 16 }, { 32, 35 }, { 44, 47 },
2743 { 61, 64 }, { 90, 93 } };
2744static struct spear_muxreg ssp2_muxreg[] = {
2745 {
2746 .reg = PMX_CONFIG_REG,
2747 .mask = PMX_MII_MASK,
2748 .val = 0,
2749 },
2750};
2751
2752static struct spear_muxreg ssp2_ext_13_16_muxreg[] = {
2753 {
2754 .reg = IP_SEL_PAD_10_19_REG,
2755 .mask = PMX_PL_13_14_MASK | PMX_PL_15_16_MASK,
2756 .val = PMX_SSP2_PL_13_14_15_16_VAL,
2757 }, {
2758 .reg = IP_SEL_MIX_PAD_REG,
2759 .mask = PMX_SSP2_PORT_SEL_MASK,
2760 .val = PMX_SSP2_PORT_13_TO_16_VAL,
2761 },
2762};
2763
2764static struct spear_muxreg ssp2_ext_32_35_muxreg[] = {
2765 {
2766 .reg = PMX_CONFIG_REG,
2767 .mask = PMX_SSP_CS_MASK | PMX_GPIO_PIN4_MASK |
2768 PMX_GPIO_PIN5_MASK,
2769 .val = 0,
2770 }, {
2771 .reg = IP_SEL_PAD_30_39_REG,
2772 .mask = PMX_PL_32_33_MASK | PMX_PL_34_MASK | PMX_PL_35_MASK,
2773 .val = PMX_SSP2_PL_32_33_VAL | PMX_SSP2_PL_34_VAL |
2774 PMX_SSP2_PL_35_VAL,
2775 }, {
2776 .reg = IP_SEL_MIX_PAD_REG,
2777 .mask = PMX_SSP2_PORT_SEL_MASK,
2778 .val = PMX_SSP2_PORT_32_TO_35_VAL,
2779 },
2780};
2781
2782static struct spear_muxreg ssp2_ext_44_47_muxreg[] = {
2783 {
2784 .reg = PMX_CONFIG_REG,
2785 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
2786 .val = 0,
2787 }, {
2788 .reg = IP_SEL_PAD_40_49_REG,
2789 .mask = PMX_PL_44_45_MASK | PMX_PL_46_47_MASK,
2790 .val = PMX_SSP2_PL_44_45_VAL | PMX_SSP2_PL_46_47_VAL,
2791 }, {
2792 .reg = IP_SEL_MIX_PAD_REG,
2793 .mask = PMX_SSP2_PORT_SEL_MASK,
2794 .val = PMX_SSP2_PORT_44_TO_47_VAL,
2795 },
2796};
2797
2798static struct spear_muxreg ssp2_ext_61_64_muxreg[] = {
2799 {
2800 .reg = IP_SEL_PAD_60_69_REG,
2801 .mask = PMX_PL_61_TO_64_MASK,
2802 .val = PMX_SSP2_PL_61_TO_64_VAL,
2803 }, {
2804 .reg = IP_SEL_MIX_PAD_REG,
2805 .mask = PMX_SSP2_PORT_SEL_MASK,
2806 .val = PMX_SSP2_PORT_61_TO_64_VAL,
2807 },
2808};
2809
2810static struct spear_muxreg ssp2_ext_90_93_muxreg[] = {
2811 {
2812 .reg = IP_SEL_PAD_90_99_REG,
2813 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK,
2814 .val = PMX_SSP2_PL_90_91_VAL | PMX_SSP2_PL_92_93_VAL,
2815 }, {
2816 .reg = IP_SEL_MIX_PAD_REG,
2817 .mask = PMX_SSP2_PORT_SEL_MASK,
2818 .val = PMX_SSP2_PORT_90_TO_93_VAL,
2819 },
2820};
2821
2822static struct spear_modemux ssp2_13_16_modemux[] = {
2823 {
2824 .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE,
2825 .muxregs = ssp2_muxreg,
2826 .nmuxregs = ARRAY_SIZE(ssp2_muxreg),
2827 }, {
2828 .modes = EXTENDED_MODE,
2829 .muxregs = ssp2_ext_13_16_muxreg,
2830 .nmuxregs = ARRAY_SIZE(ssp2_ext_13_16_muxreg),
2831 },
2832};
2833
2834static struct spear_modemux ssp2_32_35_modemux[] = {
2835 {
2836 .modes = EXTENDED_MODE,
2837 .muxregs = ssp2_ext_32_35_muxreg,
2838 .nmuxregs = ARRAY_SIZE(ssp2_ext_32_35_muxreg),
2839 },
2840};
2841
2842static struct spear_modemux ssp2_44_47_modemux[] = {
2843 {
2844 .modes = EXTENDED_MODE,
2845 .muxregs = ssp2_ext_44_47_muxreg,
2846 .nmuxregs = ARRAY_SIZE(ssp2_ext_44_47_muxreg),
2847 },
2848};
2849
2850static struct spear_modemux ssp2_61_64_modemux[] = {
2851 {
2852 .modes = EXTENDED_MODE,
2853 .muxregs = ssp2_ext_61_64_muxreg,
2854 .nmuxregs = ARRAY_SIZE(ssp2_ext_61_64_muxreg),
2855 },
2856};
2857
2858static struct spear_modemux ssp2_90_93_modemux[] = {
2859 {
2860 .modes = EXTENDED_MODE,
2861 .muxregs = ssp2_ext_90_93_muxreg,
2862 .nmuxregs = ARRAY_SIZE(ssp2_ext_90_93_muxreg),
2863 },
2864};
2865
2866static struct spear_pingroup ssp2_pingroup[] = {
2867 {
2868 .name = "ssp2_13_16_grp",
2869 .pins = ssp2_pins[0],
2870 .npins = ARRAY_SIZE(ssp2_pins[0]),
2871 .modemuxs = ssp2_13_16_modemux,
2872 .nmodemuxs = ARRAY_SIZE(ssp2_13_16_modemux),
2873 }, {
2874 .name = "ssp2_32_35_grp",
2875 .pins = ssp2_pins[1],
2876 .npins = ARRAY_SIZE(ssp2_pins[1]),
2877 .modemuxs = ssp2_32_35_modemux,
2878 .nmodemuxs = ARRAY_SIZE(ssp2_32_35_modemux),
2879 }, {
2880 .name = "ssp2_44_47_grp",
2881 .pins = ssp2_pins[2],
2882 .npins = ARRAY_SIZE(ssp2_pins[2]),
2883 .modemuxs = ssp2_44_47_modemux,
2884 .nmodemuxs = ARRAY_SIZE(ssp2_44_47_modemux),
2885 }, {
2886 .name = "ssp2_61_64_grp",
2887 .pins = ssp2_pins[3],
2888 .npins = ARRAY_SIZE(ssp2_pins[3]),
2889 .modemuxs = ssp2_61_64_modemux,
2890 .nmodemuxs = ARRAY_SIZE(ssp2_61_64_modemux),
2891 }, {
2892 .name = "ssp2_90_93_grp",
2893 .pins = ssp2_pins[4],
2894 .npins = ARRAY_SIZE(ssp2_pins[4]),
2895 .modemuxs = ssp2_90_93_modemux,
2896 .nmodemuxs = ARRAY_SIZE(ssp2_90_93_modemux),
2897 },
2898};
2899
2900static const char *const ssp2_grps[] = { "ssp2_13_16_grp", "ssp2_32_35_grp",
2901 "ssp2_44_47_grp", "ssp2_61_64_grp", "ssp2_90_93_grp" };
2902static struct spear_function ssp2_function = {
2903 .name = "ssp2",
2904 .groups = ssp2_grps,
2905 .ngroups = ARRAY_SIZE(ssp2_grps),
2906};
2907
2908/* Pad multiplexing for cadence mii2 as mii device */
2909static const unsigned mii2_pins[] = { 80, 81, 82, 83, 84, 85, 86, 87, 88, 89,
2910 90, 91, 92, 93, 94, 95, 96, 97 };
2911static struct spear_muxreg mii2_muxreg[] = {
2912 {
2913 .reg = IP_SEL_PAD_80_89_REG,
2914 .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
2915 PMX_PL_88_89_MASK,
2916 .val = PMX_MII2_PL_80_TO_85_VAL | PMX_MII2_PL_86_87_VAL |
2917 PMX_MII2_PL_88_89_VAL,
2918 }, {
2919 .reg = IP_SEL_PAD_90_99_REG,
2920 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
2921 PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
2922 .val = PMX_MII2_PL_90_91_VAL | PMX_MII2_PL_92_93_VAL |
2923 PMX_MII2_PL_94_95_VAL | PMX_MII2_PL_96_97_VAL,
2924 }, {
2925 .reg = EXT_CTRL_REG,
2926 .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
2927 (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
2928 MII_MDIO_MASK,
2929 .val = (MAC_MODE_MII << MAC2_MODE_SHIFT) |
2930 (MAC_MODE_MII << MAC1_MODE_SHIFT) |
2931 MII_MDIO_81_VAL,
2932 },
2933};
2934
2935static struct spear_modemux mii2_modemux[] = {
2936 {
2937 .modes = EXTENDED_MODE,
2938 .muxregs = mii2_muxreg,
2939 .nmuxregs = ARRAY_SIZE(mii2_muxreg),
2940 },
2941};
2942
2943static struct spear_pingroup mii2_pingroup = {
2944 .name = "mii2_grp",
2945 .pins = mii2_pins,
2946 .npins = ARRAY_SIZE(mii2_pins),
2947 .modemuxs = mii2_modemux,
2948 .nmodemuxs = ARRAY_SIZE(mii2_modemux),
2949};
2950
2951static const char *const mii2_grps[] = { "mii2_grp" };
2952static struct spear_function mii2_function = {
2953 .name = "mii2",
2954 .groups = mii2_grps,
2955 .ngroups = ARRAY_SIZE(mii2_grps),
2956};
2957
2958/* Pad multiplexing for cadence mii 1_2 as smii or rmii device */
2959static const unsigned smii0_1_pins[] = { 10, 11, 13, 14, 15, 16, 17, 18, 19, 20,
2960 21, 22, 23, 24, 25, 26, 27 };
2961static const unsigned rmii0_1_pins[] = { 10, 11, 21, 22, 23, 24, 25, 26, 27 };
2962static struct spear_muxreg mii0_1_muxreg[] = {
2963 {
2964 .reg = PMX_CONFIG_REG,
2965 .mask = PMX_MII_MASK,
2966 .val = 0,
2967 },
2968};
2969
2970static struct spear_muxreg smii0_1_ext_muxreg[] = {
2971 {
2972 .reg = IP_SEL_PAD_10_19_REG,
2973 .mask = PMX_PL_10_11_MASK,
2974 .val = PMX_SMII_PL_10_11_VAL,
2975 }, {
2976 .reg = IP_SEL_PAD_20_29_REG,
2977 .mask = PMX_PL_21_TO_27_MASK,
2978 .val = PMX_SMII_PL_21_TO_27_VAL,
2979 }, {
2980 .reg = EXT_CTRL_REG,
2981 .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
2982 (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
2983 MII_MDIO_MASK,
2984 .val = (MAC_MODE_SMII << MAC2_MODE_SHIFT)
2985 | (MAC_MODE_SMII << MAC1_MODE_SHIFT)
2986 | MII_MDIO_10_11_VAL,
2987 },
2988};
2989
2990static struct spear_muxreg rmii0_1_ext_muxreg[] = {
2991 {
2992 .reg = IP_SEL_PAD_10_19_REG,
2993 .mask = PMX_PL_10_11_MASK | PMX_PL_13_14_MASK |
2994 PMX_PL_15_16_MASK | PMX_PL_17_18_MASK | PMX_PL_19_MASK,
2995 .val = PMX_RMII_PL_10_11_VAL | PMX_RMII_PL_13_14_VAL |
2996 PMX_RMII_PL_15_16_VAL | PMX_RMII_PL_17_18_VAL |
2997 PMX_RMII_PL_19_VAL,
2998 }, {
2999 .reg = IP_SEL_PAD_20_29_REG,
3000 .mask = PMX_PL_20_MASK | PMX_PL_21_TO_27_MASK,
3001 .val = PMX_RMII_PL_20_VAL | PMX_RMII_PL_21_TO_27_VAL,
3002 }, {
3003 .reg = EXT_CTRL_REG,
3004 .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
3005 (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
3006 MII_MDIO_MASK,
3007 .val = (MAC_MODE_RMII << MAC2_MODE_SHIFT)
3008 | (MAC_MODE_RMII << MAC1_MODE_SHIFT)
3009 | MII_MDIO_10_11_VAL,
3010 },
3011};
3012
3013static struct spear_modemux mii0_1_modemux[][2] = {
3014 {
3015 /* configure as smii */
3016 {
3017 .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE |
3018 SMALL_PRINTERS_MODE | EXTENDED_MODE,
3019 .muxregs = mii0_1_muxreg,
3020 .nmuxregs = ARRAY_SIZE(mii0_1_muxreg),
3021 }, {
3022 .modes = EXTENDED_MODE,
3023 .muxregs = smii0_1_ext_muxreg,
3024 .nmuxregs = ARRAY_SIZE(smii0_1_ext_muxreg),
3025 },
3026 }, {
3027 /* configure as rmii */
3028 {
3029 .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE |
3030 SMALL_PRINTERS_MODE | EXTENDED_MODE,
3031 .muxregs = mii0_1_muxreg,
3032 .nmuxregs = ARRAY_SIZE(mii0_1_muxreg),
3033 }, {
3034 .modes = EXTENDED_MODE,
3035 .muxregs = rmii0_1_ext_muxreg,
3036 .nmuxregs = ARRAY_SIZE(rmii0_1_ext_muxreg),
3037 },
3038 },
3039};
3040
3041static struct spear_pingroup mii0_1_pingroup[] = {
3042 {
3043 .name = "smii0_1_grp",
3044 .pins = smii0_1_pins,
3045 .npins = ARRAY_SIZE(smii0_1_pins),
3046 .modemuxs = mii0_1_modemux[0],
3047 .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[0]),
3048 }, {
3049 .name = "rmii0_1_grp",
3050 .pins = rmii0_1_pins,
3051 .npins = ARRAY_SIZE(rmii0_1_pins),
3052 .modemuxs = mii0_1_modemux[1],
3053 .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[1]),
3054 },
3055};
3056
3057static const char *const mii0_1_grps[] = { "smii0_1_grp", "rmii0_1_grp" };
3058static struct spear_function mii0_1_function = {
3059 .name = "mii0_1",
3060 .groups = mii0_1_grps,
3061 .ngroups = ARRAY_SIZE(mii0_1_grps),
3062};
3063
3064/* Pad multiplexing for i2c1 device */
3065static const unsigned i2c1_pins[][2] = { { 8, 9 }, { 98, 99 } };
3066static struct spear_muxreg i2c1_ext_8_9_muxreg[] = {
3067 {
3068 .reg = PMX_CONFIG_REG,
3069 .mask = PMX_SSP_CS_MASK,
3070 .val = 0,
3071 }, {
3072 .reg = IP_SEL_PAD_0_9_REG,
3073 .mask = PMX_PL_8_9_MASK,
3074 .val = PMX_I2C1_PL_8_9_VAL,
3075 }, {
3076 .reg = IP_SEL_MIX_PAD_REG,
3077 .mask = PMX_I2C1_PORT_SEL_MASK,
3078 .val = PMX_I2C1_PORT_8_9_VAL,
3079 },
3080};
3081
3082static struct spear_muxreg i2c1_ext_98_99_muxreg[] = {
3083 {
3084 .reg = IP_SEL_PAD_90_99_REG,
3085 .mask = PMX_PL_98_MASK | PMX_PL_99_MASK,
3086 .val = PMX_I2C1_PL_98_VAL | PMX_I2C1_PL_99_VAL,
3087 }, {
3088 .reg = IP_SEL_MIX_PAD_REG,
3089 .mask = PMX_I2C1_PORT_SEL_MASK,
3090 .val = PMX_I2C1_PORT_98_99_VAL,
3091 },
3092};
3093
3094static struct spear_modemux i2c1_modemux[][1] = {
3095 {
3096 /* Select signals on pins 8-9 */
3097 {
3098 .modes = EXTENDED_MODE,
3099 .muxregs = i2c1_ext_8_9_muxreg,
3100 .nmuxregs = ARRAY_SIZE(i2c1_ext_8_9_muxreg),
3101 },
3102 }, {
3103 /* Select signals on pins 98-99 */
3104 {
3105 .modes = EXTENDED_MODE,
3106 .muxregs = i2c1_ext_98_99_muxreg,
3107 .nmuxregs = ARRAY_SIZE(i2c1_ext_98_99_muxreg),
3108 },
3109 },
3110};
3111
3112static struct spear_pingroup i2c1_pingroup[] = {
3113 {
3114 .name = "i2c1_8_9_grp",
3115 .pins = i2c1_pins[0],
3116 .npins = ARRAY_SIZE(i2c1_pins[0]),
3117 .modemuxs = i2c1_modemux[0],
3118 .nmodemuxs = ARRAY_SIZE(i2c1_modemux[0]),
3119 }, {
3120 .name = "i2c1_98_99_grp",
3121 .pins = i2c1_pins[1],
3122 .npins = ARRAY_SIZE(i2c1_pins[1]),
3123 .modemuxs = i2c1_modemux[1],
3124 .nmodemuxs = ARRAY_SIZE(i2c1_modemux[1]),
3125 },
3126};
3127
3128static const char *const i2c1_grps[] = { "i2c1_8_9_grp", "i2c1_98_99_grp" };
3129static struct spear_function i2c1_function = {
3130 .name = "i2c1",
3131 .groups = i2c1_grps,
3132 .ngroups = ARRAY_SIZE(i2c1_grps),
3133};
3134
3135/* Pad multiplexing for i2c2 device */
3136static const unsigned i2c2_pins[][2] = { { 0, 1 }, { 2, 3 }, { 19, 20 },
3137 { 75, 76 }, { 96, 97 } };
3138static struct spear_muxreg i2c2_ext_0_1_muxreg[] = {
3139 {
3140 .reg = PMX_CONFIG_REG,
3141 .mask = PMX_FIRDA_MASK,
3142 .val = 0,
3143 }, {
3144 .reg = IP_SEL_PAD_0_9_REG,
3145 .mask = PMX_PL_0_1_MASK,
3146 .val = PMX_I2C2_PL_0_1_VAL,
3147 }, {
3148 .reg = IP_SEL_MIX_PAD_REG,
3149 .mask = PMX_I2C2_PORT_SEL_MASK,
3150 .val = PMX_I2C2_PORT_0_1_VAL,
3151 },
3152};
3153
3154static struct spear_muxreg i2c2_ext_2_3_muxreg[] = {
3155 {
3156 .reg = PMX_CONFIG_REG,
3157 .mask = PMX_UART0_MASK,
3158 .val = 0,
3159 }, {
3160 .reg = IP_SEL_PAD_0_9_REG,
3161 .mask = PMX_PL_2_3_MASK,
3162 .val = PMX_I2C2_PL_2_3_VAL,
3163 }, {
3164 .reg = IP_SEL_MIX_PAD_REG,
3165 .mask = PMX_I2C2_PORT_SEL_MASK,
3166 .val = PMX_I2C2_PORT_2_3_VAL,
3167 },
3168};
3169
3170static struct spear_muxreg i2c2_ext_19_20_muxreg[] = {
3171 {
3172 .reg = PMX_CONFIG_REG,
3173 .mask = PMX_MII_MASK,
3174 .val = 0,
3175 }, {
3176 .reg = IP_SEL_PAD_10_19_REG,
3177 .mask = PMX_PL_19_MASK,
3178 .val = PMX_I2C2_PL_19_VAL,
3179 }, {
3180 .reg = IP_SEL_PAD_20_29_REG,
3181 .mask = PMX_PL_20_MASK,
3182 .val = PMX_I2C2_PL_20_VAL,
3183 }, {
3184 .reg = IP_SEL_MIX_PAD_REG,
3185 .mask = PMX_I2C2_PORT_SEL_MASK,
3186 .val = PMX_I2C2_PORT_19_20_VAL,
3187 },
3188};
3189
3190static struct spear_muxreg i2c2_ext_75_76_muxreg[] = {
3191 {
3192 .reg = IP_SEL_PAD_70_79_REG,
3193 .mask = PMX_PL_75_76_MASK,
3194 .val = PMX_I2C2_PL_75_76_VAL,
3195 }, {
3196 .reg = IP_SEL_MIX_PAD_REG,
3197 .mask = PMX_I2C2_PORT_SEL_MASK,
3198 .val = PMX_I2C2_PORT_75_76_VAL,
3199 },
3200};
3201
3202static struct spear_muxreg i2c2_ext_96_97_muxreg[] = {
3203 {
3204 .reg = IP_SEL_PAD_90_99_REG,
3205 .mask = PMX_PL_96_97_MASK,
3206 .val = PMX_I2C2_PL_96_97_VAL,
3207 }, {
3208 .reg = IP_SEL_MIX_PAD_REG,
3209 .mask = PMX_I2C2_PORT_SEL_MASK,
3210 .val = PMX_I2C2_PORT_96_97_VAL,
3211 },
3212};
3213
3214static struct spear_modemux i2c2_modemux[][1] = {
3215 {
3216 /* Select signals on pins 0_1 */
3217 {
3218 .modes = EXTENDED_MODE,
3219 .muxregs = i2c2_ext_0_1_muxreg,
3220 .nmuxregs = ARRAY_SIZE(i2c2_ext_0_1_muxreg),
3221 },
3222 }, {
3223 /* Select signals on pins 2_3 */
3224 {
3225 .modes = EXTENDED_MODE,
3226 .muxregs = i2c2_ext_2_3_muxreg,
3227 .nmuxregs = ARRAY_SIZE(i2c2_ext_2_3_muxreg),
3228 },
3229 }, {
3230 /* Select signals on pins 19_20 */
3231 {
3232 .modes = EXTENDED_MODE,
3233 .muxregs = i2c2_ext_19_20_muxreg,
3234 .nmuxregs = ARRAY_SIZE(i2c2_ext_19_20_muxreg),
3235 },
3236 }, {
3237 /* Select signals on pins 75_76 */
3238 {
3239 .modes = EXTENDED_MODE,
3240 .muxregs = i2c2_ext_75_76_muxreg,
3241 .nmuxregs = ARRAY_SIZE(i2c2_ext_75_76_muxreg),
3242 },
3243 }, {
3244 /* Select signals on pins 96_97 */
3245 {
3246 .modes = EXTENDED_MODE,
3247 .muxregs = i2c2_ext_96_97_muxreg,
3248 .nmuxregs = ARRAY_SIZE(i2c2_ext_96_97_muxreg),
3249 },
3250 },
3251};
3252
3253static struct spear_pingroup i2c2_pingroup[] = {
3254 {
3255 .name = "i2c2_0_1_grp",
3256 .pins = i2c2_pins[0],
3257 .npins = ARRAY_SIZE(i2c2_pins[0]),
3258 .modemuxs = i2c2_modemux[0],
3259 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[0]),
3260 }, {
3261 .name = "i2c2_2_3_grp",
3262 .pins = i2c2_pins[1],
3263 .npins = ARRAY_SIZE(i2c2_pins[1]),
3264 .modemuxs = i2c2_modemux[1],
3265 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[1]),
3266 }, {
3267 .name = "i2c2_19_20_grp",
3268 .pins = i2c2_pins[2],
3269 .npins = ARRAY_SIZE(i2c2_pins[2]),
3270 .modemuxs = i2c2_modemux[2],
3271 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[2]),
3272 }, {
3273 .name = "i2c2_75_76_grp",
3274 .pins = i2c2_pins[3],
3275 .npins = ARRAY_SIZE(i2c2_pins[3]),
3276 .modemuxs = i2c2_modemux[3],
3277 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[3]),
3278 }, {
3279 .name = "i2c2_96_97_grp",
3280 .pins = i2c2_pins[4],
3281 .npins = ARRAY_SIZE(i2c2_pins[4]),
3282 .modemuxs = i2c2_modemux[4],
3283 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[4]),
3284 },
3285};
3286
3287static const char *const i2c2_grps[] = { "i2c2_0_1_grp", "i2c2_2_3_grp",
3288 "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp" };
3289static struct spear_function i2c2_function = {
3290 .name = "i2c2",
3291 .groups = i2c2_grps,
3292 .ngroups = ARRAY_SIZE(i2c2_grps),
3293};
3294
3295/* pingroups */
3296static struct spear_pingroup *spear320_pingroups[] = {
3297 SPEAR3XX_COMMON_PINGROUPS,
3298 &clcd_pingroup,
3299 &emi_pingroup,
3300 &fsmc_8bit_pingroup,
3301 &fsmc_16bit_pingroup,
3302 &spp_pingroup,
3303 &sdhci_led_pingroup,
3304 &sdhci_pingroup[0],
3305 &sdhci_pingroup[1],
3306 &i2s_pingroup,
3307 &uart1_pingroup,
3308 &uart1_modem_pingroup[0],
3309 &uart1_modem_pingroup[1],
3310 &uart1_modem_pingroup[2],
3311 &uart1_modem_pingroup[3],
3312 &uart2_pingroup,
3313 &uart3_pingroup[0],
3314 &uart3_pingroup[1],
3315 &uart3_pingroup[2],
3316 &uart3_pingroup[3],
3317 &uart3_pingroup[4],
3318 &uart3_pingroup[5],
3319 &uart3_pingroup[6],
3320 &uart4_pingroup[0],
3321 &uart4_pingroup[1],
3322 &uart4_pingroup[2],
3323 &uart4_pingroup[3],
3324 &uart4_pingroup[4],
3325 &uart4_pingroup[5],
3326 &uart5_pingroup[0],
3327 &uart5_pingroup[1],
3328 &uart5_pingroup[2],
3329 &uart5_pingroup[3],
3330 &uart6_pingroup[0],
3331 &uart6_pingroup[1],
3332 &rs485_pingroup,
3333 &touchscreen_pingroup,
3334 &can0_pingroup,
3335 &can1_pingroup,
3336 &pwm0_1_pingroup[0],
3337 &pwm0_1_pingroup[1],
3338 &pwm0_1_pingroup[2],
3339 &pwm0_1_pingroup[3],
3340 &pwm0_1_pingroup[4],
3341 &pwm0_1_pingroup[5],
3342 &pwm0_1_pingroup[6],
3343 &pwm2_pingroup[0],
3344 &pwm2_pingroup[1],
3345 &pwm2_pingroup[2],
3346 &pwm2_pingroup[3],
3347 &pwm2_pingroup[4],
3348 &pwm2_pingroup[5],
3349 &pwm2_pingroup[6],
3350 &pwm3_pingroup[0],
3351 &pwm3_pingroup[1],
3352 &pwm3_pingroup[2],
3353 &pwm3_pingroup[3],
3354 &pwm3_pingroup[4],
3355 &pwm3_pingroup[5],
3356 &ssp1_pingroup[0],
3357 &ssp1_pingroup[1],
3358 &ssp1_pingroup[2],
3359 &ssp1_pingroup[3],
3360 &ssp1_pingroup[4],
3361 &ssp2_pingroup[0],
3362 &ssp2_pingroup[1],
3363 &ssp2_pingroup[2],
3364 &ssp2_pingroup[3],
3365 &ssp2_pingroup[4],
3366 &mii2_pingroup,
3367 &mii0_1_pingroup[0],
3368 &mii0_1_pingroup[1],
3369 &i2c1_pingroup[0],
3370 &i2c1_pingroup[1],
3371 &i2c2_pingroup[0],
3372 &i2c2_pingroup[1],
3373 &i2c2_pingroup[2],
3374 &i2c2_pingroup[3],
3375 &i2c2_pingroup[4],
3376};
3377
3378/* functions */
3379static struct spear_function *spear320_functions[] = {
3380 SPEAR3XX_COMMON_FUNCTIONS,
3381 &clcd_function,
3382 &emi_function,
3383 &fsmc_function,
3384 &spp_function,
3385 &sdhci_function,
3386 &i2s_function,
3387 &uart1_function,
3388 &uart1_modem_function,
3389 &uart2_function,
3390 &uart3_function,
3391 &uart4_function,
3392 &uart5_function,
3393 &uart6_function,
3394 &rs485_function,
3395 &touchscreen_function,
3396 &can0_function,
3397 &can1_function,
3398 &pwm0_1_function,
3399 &pwm2_function,
3400 &pwm3_function,
3401 &ssp1_function,
3402 &ssp2_function,
3403 &mii2_function,
3404 &mii0_1_function,
3405 &i2c1_function,
3406 &i2c2_function,
3407};
3408
3409static struct of_device_id spear320_pinctrl_of_match[] __devinitdata = {
3410 {
3411 .compatible = "st,spear320-pinmux",
3412 },
3413 {},
3414};
3415
3416static int __devinit spear320_pinctrl_probe(struct platform_device *pdev)
3417{
3418 int ret;
3419
3420 spear3xx_machdata.groups = spear320_pingroups;
3421 spear3xx_machdata.ngroups = ARRAY_SIZE(spear320_pingroups);
3422 spear3xx_machdata.functions = spear320_functions;
3423 spear3xx_machdata.nfunctions = ARRAY_SIZE(spear320_functions);
3424
3425 spear3xx_machdata.modes_supported = true;
3426 spear3xx_machdata.pmx_modes = spear320_pmx_modes;
3427 spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear320_pmx_modes);
3428
3429 pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
3430
3431 ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
3432 if (ret)
3433 return ret;
3434
3435 return 0;
3436}
3437
3438static int __devexit spear320_pinctrl_remove(struct platform_device *pdev)
3439{
3440 return spear_pinctrl_remove(pdev);
3441}
3442
3443static struct platform_driver spear320_pinctrl_driver = {
3444 .driver = {
3445 .name = DRIVER_NAME,
3446 .owner = THIS_MODULE,
3447 .of_match_table = spear320_pinctrl_of_match,
3448 },
3449 .probe = spear320_pinctrl_probe,
3450 .remove = __devexit_p(spear320_pinctrl_remove),
3451};
3452
3453static int __init spear320_pinctrl_init(void)
3454{
3455 return platform_driver_register(&spear320_pinctrl_driver);
3456}
3457arch_initcall(spear320_pinctrl_init);
3458
3459static void __exit spear320_pinctrl_exit(void)
3460{
3461 platform_driver_unregister(&spear320_pinctrl_driver);
3462}
3463module_exit(spear320_pinctrl_exit);
3464
3465MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
3466MODULE_DESCRIPTION("ST Microelectronics SPEAr320 pinctrl driver");
3467MODULE_LICENSE("GPL v2");
3468MODULE_DEVICE_TABLE(of, spear320_pinctrl_of_match);
diff --git a/drivers/pinctrl/spear/pinctrl-spear3xx.c b/drivers/pinctrl/spear/pinctrl-spear3xx.c
new file mode 100644
index 000000000000..832049a8b1c9
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear3xx.c
@@ -0,0 +1,588 @@
1/*
2 * Driver for the ST Microelectronics SPEAr3xx pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/pinctrl/pinctrl.h>
13
14#include "pinctrl-spear3xx.h"
15
16/* pins */
17static const struct pinctrl_pin_desc spear3xx_pins[] = {
18 PINCTRL_PIN(0, "PLGPIO0"),
19 PINCTRL_PIN(1, "PLGPIO1"),
20 PINCTRL_PIN(2, "PLGPIO2"),
21 PINCTRL_PIN(3, "PLGPIO3"),
22 PINCTRL_PIN(4, "PLGPIO4"),
23 PINCTRL_PIN(5, "PLGPIO5"),
24 PINCTRL_PIN(6, "PLGPIO6"),
25 PINCTRL_PIN(7, "PLGPIO7"),
26 PINCTRL_PIN(8, "PLGPIO8"),
27 PINCTRL_PIN(9, "PLGPIO9"),
28 PINCTRL_PIN(10, "PLGPIO10"),
29 PINCTRL_PIN(11, "PLGPIO11"),
30 PINCTRL_PIN(12, "PLGPIO12"),
31 PINCTRL_PIN(13, "PLGPIO13"),
32 PINCTRL_PIN(14, "PLGPIO14"),
33 PINCTRL_PIN(15, "PLGPIO15"),
34 PINCTRL_PIN(16, "PLGPIO16"),
35 PINCTRL_PIN(17, "PLGPIO17"),
36 PINCTRL_PIN(18, "PLGPIO18"),
37 PINCTRL_PIN(19, "PLGPIO19"),
38 PINCTRL_PIN(20, "PLGPIO20"),
39 PINCTRL_PIN(21, "PLGPIO21"),
40 PINCTRL_PIN(22, "PLGPIO22"),
41 PINCTRL_PIN(23, "PLGPIO23"),
42 PINCTRL_PIN(24, "PLGPIO24"),
43 PINCTRL_PIN(25, "PLGPIO25"),
44 PINCTRL_PIN(26, "PLGPIO26"),
45 PINCTRL_PIN(27, "PLGPIO27"),
46 PINCTRL_PIN(28, "PLGPIO28"),
47 PINCTRL_PIN(29, "PLGPIO29"),
48 PINCTRL_PIN(30, "PLGPIO30"),
49 PINCTRL_PIN(31, "PLGPIO31"),
50 PINCTRL_PIN(32, "PLGPIO32"),
51 PINCTRL_PIN(33, "PLGPIO33"),
52 PINCTRL_PIN(34, "PLGPIO34"),
53 PINCTRL_PIN(35, "PLGPIO35"),
54 PINCTRL_PIN(36, "PLGPIO36"),
55 PINCTRL_PIN(37, "PLGPIO37"),
56 PINCTRL_PIN(38, "PLGPIO38"),
57 PINCTRL_PIN(39, "PLGPIO39"),
58 PINCTRL_PIN(40, "PLGPIO40"),
59 PINCTRL_PIN(41, "PLGPIO41"),
60 PINCTRL_PIN(42, "PLGPIO42"),
61 PINCTRL_PIN(43, "PLGPIO43"),
62 PINCTRL_PIN(44, "PLGPIO44"),
63 PINCTRL_PIN(45, "PLGPIO45"),
64 PINCTRL_PIN(46, "PLGPIO46"),
65 PINCTRL_PIN(47, "PLGPIO47"),
66 PINCTRL_PIN(48, "PLGPIO48"),
67 PINCTRL_PIN(49, "PLGPIO49"),
68 PINCTRL_PIN(50, "PLGPIO50"),
69 PINCTRL_PIN(51, "PLGPIO51"),
70 PINCTRL_PIN(52, "PLGPIO52"),
71 PINCTRL_PIN(53, "PLGPIO53"),
72 PINCTRL_PIN(54, "PLGPIO54"),
73 PINCTRL_PIN(55, "PLGPIO55"),
74 PINCTRL_PIN(56, "PLGPIO56"),
75 PINCTRL_PIN(57, "PLGPIO57"),
76 PINCTRL_PIN(58, "PLGPIO58"),
77 PINCTRL_PIN(59, "PLGPIO59"),
78 PINCTRL_PIN(60, "PLGPIO60"),
79 PINCTRL_PIN(61, "PLGPIO61"),
80 PINCTRL_PIN(62, "PLGPIO62"),
81 PINCTRL_PIN(63, "PLGPIO63"),
82 PINCTRL_PIN(64, "PLGPIO64"),
83 PINCTRL_PIN(65, "PLGPIO65"),
84 PINCTRL_PIN(66, "PLGPIO66"),
85 PINCTRL_PIN(67, "PLGPIO67"),
86 PINCTRL_PIN(68, "PLGPIO68"),
87 PINCTRL_PIN(69, "PLGPIO69"),
88 PINCTRL_PIN(70, "PLGPIO70"),
89 PINCTRL_PIN(71, "PLGPIO71"),
90 PINCTRL_PIN(72, "PLGPIO72"),
91 PINCTRL_PIN(73, "PLGPIO73"),
92 PINCTRL_PIN(74, "PLGPIO74"),
93 PINCTRL_PIN(75, "PLGPIO75"),
94 PINCTRL_PIN(76, "PLGPIO76"),
95 PINCTRL_PIN(77, "PLGPIO77"),
96 PINCTRL_PIN(78, "PLGPIO78"),
97 PINCTRL_PIN(79, "PLGPIO79"),
98 PINCTRL_PIN(80, "PLGPIO80"),
99 PINCTRL_PIN(81, "PLGPIO81"),
100 PINCTRL_PIN(82, "PLGPIO82"),
101 PINCTRL_PIN(83, "PLGPIO83"),
102 PINCTRL_PIN(84, "PLGPIO84"),
103 PINCTRL_PIN(85, "PLGPIO85"),
104 PINCTRL_PIN(86, "PLGPIO86"),
105 PINCTRL_PIN(87, "PLGPIO87"),
106 PINCTRL_PIN(88, "PLGPIO88"),
107 PINCTRL_PIN(89, "PLGPIO89"),
108 PINCTRL_PIN(90, "PLGPIO90"),
109 PINCTRL_PIN(91, "PLGPIO91"),
110 PINCTRL_PIN(92, "PLGPIO92"),
111 PINCTRL_PIN(93, "PLGPIO93"),
112 PINCTRL_PIN(94, "PLGPIO94"),
113 PINCTRL_PIN(95, "PLGPIO95"),
114 PINCTRL_PIN(96, "PLGPIO96"),
115 PINCTRL_PIN(97, "PLGPIO97"),
116 PINCTRL_PIN(98, "PLGPIO98"),
117 PINCTRL_PIN(99, "PLGPIO99"),
118 PINCTRL_PIN(100, "PLGPIO100"),
119 PINCTRL_PIN(101, "PLGPIO101"),
120};
121
122/* firda_pins */
123static const unsigned firda_pins[] = { 0, 1 };
124static struct spear_muxreg firda_muxreg[] = {
125 {
126 .reg = -1,
127 .mask = PMX_FIRDA_MASK,
128 .val = PMX_FIRDA_MASK,
129 },
130};
131
132static struct spear_modemux firda_modemux[] = {
133 {
134 .modes = ~0,
135 .muxregs = firda_muxreg,
136 .nmuxregs = ARRAY_SIZE(firda_muxreg),
137 },
138};
139
140struct spear_pingroup spear3xx_firda_pingroup = {
141 .name = "firda_grp",
142 .pins = firda_pins,
143 .npins = ARRAY_SIZE(firda_pins),
144 .modemuxs = firda_modemux,
145 .nmodemuxs = ARRAY_SIZE(firda_modemux),
146};
147
148static const char *const firda_grps[] = { "firda_grp" };
149struct spear_function spear3xx_firda_function = {
150 .name = "firda",
151 .groups = firda_grps,
152 .ngroups = ARRAY_SIZE(firda_grps),
153};
154
155/* i2c_pins */
156static const unsigned i2c_pins[] = { 4, 5 };
157static struct spear_muxreg i2c_muxreg[] = {
158 {
159 .reg = -1,
160 .mask = PMX_I2C_MASK,
161 .val = PMX_I2C_MASK,
162 },
163};
164
165static struct spear_modemux i2c_modemux[] = {
166 {
167 .modes = ~0,
168 .muxregs = i2c_muxreg,
169 .nmuxregs = ARRAY_SIZE(i2c_muxreg),
170 },
171};
172
173struct spear_pingroup spear3xx_i2c_pingroup = {
174 .name = "i2c0_grp",
175 .pins = i2c_pins,
176 .npins = ARRAY_SIZE(i2c_pins),
177 .modemuxs = i2c_modemux,
178 .nmodemuxs = ARRAY_SIZE(i2c_modemux),
179};
180
181static const char *const i2c_grps[] = { "i2c0_grp" };
182struct spear_function spear3xx_i2c_function = {
183 .name = "i2c0",
184 .groups = i2c_grps,
185 .ngroups = ARRAY_SIZE(i2c_grps),
186};
187
188/* ssp_cs_pins */
189static const unsigned ssp_cs_pins[] = { 34, 35, 36 };
190static struct spear_muxreg ssp_cs_muxreg[] = {
191 {
192 .reg = -1,
193 .mask = PMX_SSP_CS_MASK,
194 .val = PMX_SSP_CS_MASK,
195 },
196};
197
198static struct spear_modemux ssp_cs_modemux[] = {
199 {
200 .modes = ~0,
201 .muxregs = ssp_cs_muxreg,
202 .nmuxregs = ARRAY_SIZE(ssp_cs_muxreg),
203 },
204};
205
206struct spear_pingroup spear3xx_ssp_cs_pingroup = {
207 .name = "ssp_cs_grp",
208 .pins = ssp_cs_pins,
209 .npins = ARRAY_SIZE(ssp_cs_pins),
210 .modemuxs = ssp_cs_modemux,
211 .nmodemuxs = ARRAY_SIZE(ssp_cs_modemux),
212};
213
214static const char *const ssp_cs_grps[] = { "ssp_cs_grp" };
215struct spear_function spear3xx_ssp_cs_function = {
216 .name = "ssp_cs",
217 .groups = ssp_cs_grps,
218 .ngroups = ARRAY_SIZE(ssp_cs_grps),
219};
220
221/* ssp_pins */
222static const unsigned ssp_pins[] = { 6, 7, 8, 9 };
223static struct spear_muxreg ssp_muxreg[] = {
224 {
225 .reg = -1,
226 .mask = PMX_SSP_MASK,
227 .val = PMX_SSP_MASK,
228 },
229};
230
231static struct spear_modemux ssp_modemux[] = {
232 {
233 .modes = ~0,
234 .muxregs = ssp_muxreg,
235 .nmuxregs = ARRAY_SIZE(ssp_muxreg),
236 },
237};
238
239struct spear_pingroup spear3xx_ssp_pingroup = {
240 .name = "ssp0_grp",
241 .pins = ssp_pins,
242 .npins = ARRAY_SIZE(ssp_pins),
243 .modemuxs = ssp_modemux,
244 .nmodemuxs = ARRAY_SIZE(ssp_modemux),
245};
246
247static const char *const ssp_grps[] = { "ssp0_grp" };
248struct spear_function spear3xx_ssp_function = {
249 .name = "ssp0",
250 .groups = ssp_grps,
251 .ngroups = ARRAY_SIZE(ssp_grps),
252};
253
254/* mii_pins */
255static const unsigned mii_pins[] = { 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
256 21, 22, 23, 24, 25, 26, 27 };
257static struct spear_muxreg mii_muxreg[] = {
258 {
259 .reg = -1,
260 .mask = PMX_MII_MASK,
261 .val = PMX_MII_MASK,
262 },
263};
264
265static struct spear_modemux mii_modemux[] = {
266 {
267 .modes = ~0,
268 .muxregs = mii_muxreg,
269 .nmuxregs = ARRAY_SIZE(mii_muxreg),
270 },
271};
272
273struct spear_pingroup spear3xx_mii_pingroup = {
274 .name = "mii0_grp",
275 .pins = mii_pins,
276 .npins = ARRAY_SIZE(mii_pins),
277 .modemuxs = mii_modemux,
278 .nmodemuxs = ARRAY_SIZE(mii_modemux),
279};
280
281static const char *const mii_grps[] = { "mii0_grp" };
282struct spear_function spear3xx_mii_function = {
283 .name = "mii0",
284 .groups = mii_grps,
285 .ngroups = ARRAY_SIZE(mii_grps),
286};
287
288/* gpio0_pin0_pins */
289static const unsigned gpio0_pin0_pins[] = { 28 };
290static struct spear_muxreg gpio0_pin0_muxreg[] = {
291 {
292 .reg = -1,
293 .mask = PMX_GPIO_PIN0_MASK,
294 .val = PMX_GPIO_PIN0_MASK,
295 },
296};
297
298static struct spear_modemux gpio0_pin0_modemux[] = {
299 {
300 .modes = ~0,
301 .muxregs = gpio0_pin0_muxreg,
302 .nmuxregs = ARRAY_SIZE(gpio0_pin0_muxreg),
303 },
304};
305
306struct spear_pingroup spear3xx_gpio0_pin0_pingroup = {
307 .name = "gpio0_pin0_grp",
308 .pins = gpio0_pin0_pins,
309 .npins = ARRAY_SIZE(gpio0_pin0_pins),
310 .modemuxs = gpio0_pin0_modemux,
311 .nmodemuxs = ARRAY_SIZE(gpio0_pin0_modemux),
312};
313
314/* gpio0_pin1_pins */
315static const unsigned gpio0_pin1_pins[] = { 29 };
316static struct spear_muxreg gpio0_pin1_muxreg[] = {
317 {
318 .reg = -1,
319 .mask = PMX_GPIO_PIN1_MASK,
320 .val = PMX_GPIO_PIN1_MASK,
321 },
322};
323
324static struct spear_modemux gpio0_pin1_modemux[] = {
325 {
326 .modes = ~0,
327 .muxregs = gpio0_pin1_muxreg,
328 .nmuxregs = ARRAY_SIZE(gpio0_pin1_muxreg),
329 },
330};
331
332struct spear_pingroup spear3xx_gpio0_pin1_pingroup = {
333 .name = "gpio0_pin1_grp",
334 .pins = gpio0_pin1_pins,
335 .npins = ARRAY_SIZE(gpio0_pin1_pins),
336 .modemuxs = gpio0_pin1_modemux,
337 .nmodemuxs = ARRAY_SIZE(gpio0_pin1_modemux),
338};
339
340/* gpio0_pin2_pins */
341static const unsigned gpio0_pin2_pins[] = { 30 };
342static struct spear_muxreg gpio0_pin2_muxreg[] = {
343 {
344 .reg = -1,
345 .mask = PMX_GPIO_PIN2_MASK,
346 .val = PMX_GPIO_PIN2_MASK,
347 },
348};
349
350static struct spear_modemux gpio0_pin2_modemux[] = {
351 {
352 .modes = ~0,
353 .muxregs = gpio0_pin2_muxreg,
354 .nmuxregs = ARRAY_SIZE(gpio0_pin2_muxreg),
355 },
356};
357
358struct spear_pingroup spear3xx_gpio0_pin2_pingroup = {
359 .name = "gpio0_pin2_grp",
360 .pins = gpio0_pin2_pins,
361 .npins = ARRAY_SIZE(gpio0_pin2_pins),
362 .modemuxs = gpio0_pin2_modemux,
363 .nmodemuxs = ARRAY_SIZE(gpio0_pin2_modemux),
364};
365
366/* gpio0_pin3_pins */
367static const unsigned gpio0_pin3_pins[] = { 31 };
368static struct spear_muxreg gpio0_pin3_muxreg[] = {
369 {
370 .reg = -1,
371 .mask = PMX_GPIO_PIN3_MASK,
372 .val = PMX_GPIO_PIN3_MASK,
373 },
374};
375
376static struct spear_modemux gpio0_pin3_modemux[] = {
377 {
378 .modes = ~0,
379 .muxregs = gpio0_pin3_muxreg,
380 .nmuxregs = ARRAY_SIZE(gpio0_pin3_muxreg),
381 },
382};
383
384struct spear_pingroup spear3xx_gpio0_pin3_pingroup = {
385 .name = "gpio0_pin3_grp",
386 .pins = gpio0_pin3_pins,
387 .npins = ARRAY_SIZE(gpio0_pin3_pins),
388 .modemuxs = gpio0_pin3_modemux,
389 .nmodemuxs = ARRAY_SIZE(gpio0_pin3_modemux),
390};
391
392/* gpio0_pin4_pins */
393static const unsigned gpio0_pin4_pins[] = { 32 };
394static struct spear_muxreg gpio0_pin4_muxreg[] = {
395 {
396 .reg = -1,
397 .mask = PMX_GPIO_PIN4_MASK,
398 .val = PMX_GPIO_PIN4_MASK,
399 },
400};
401
402static struct spear_modemux gpio0_pin4_modemux[] = {
403 {
404 .modes = ~0,
405 .muxregs = gpio0_pin4_muxreg,
406 .nmuxregs = ARRAY_SIZE(gpio0_pin4_muxreg),
407 },
408};
409
410struct spear_pingroup spear3xx_gpio0_pin4_pingroup = {
411 .name = "gpio0_pin4_grp",
412 .pins = gpio0_pin4_pins,
413 .npins = ARRAY_SIZE(gpio0_pin4_pins),
414 .modemuxs = gpio0_pin4_modemux,
415 .nmodemuxs = ARRAY_SIZE(gpio0_pin4_modemux),
416};
417
418/* gpio0_pin5_pins */
419static const unsigned gpio0_pin5_pins[] = { 33 };
420static struct spear_muxreg gpio0_pin5_muxreg[] = {
421 {
422 .reg = -1,
423 .mask = PMX_GPIO_PIN5_MASK,
424 .val = PMX_GPIO_PIN5_MASK,
425 },
426};
427
428static struct spear_modemux gpio0_pin5_modemux[] = {
429 {
430 .modes = ~0,
431 .muxregs = gpio0_pin5_muxreg,
432 .nmuxregs = ARRAY_SIZE(gpio0_pin5_muxreg),
433 },
434};
435
436struct spear_pingroup spear3xx_gpio0_pin5_pingroup = {
437 .name = "gpio0_pin5_grp",
438 .pins = gpio0_pin5_pins,
439 .npins = ARRAY_SIZE(gpio0_pin5_pins),
440 .modemuxs = gpio0_pin5_modemux,
441 .nmodemuxs = ARRAY_SIZE(gpio0_pin5_modemux),
442};
443
444static const char *const gpio0_grps[] = { "gpio0_pin0_grp", "gpio0_pin1_grp",
445 "gpio0_pin2_grp", "gpio0_pin3_grp", "gpio0_pin4_grp", "gpio0_pin5_grp",
446};
447struct spear_function spear3xx_gpio0_function = {
448 .name = "gpio0",
449 .groups = gpio0_grps,
450 .ngroups = ARRAY_SIZE(gpio0_grps),
451};
452
453/* uart0_ext_pins */
454static const unsigned uart0_ext_pins[] = { 37, 38, 39, 40, 41, 42 };
455static struct spear_muxreg uart0_ext_muxreg[] = {
456 {
457 .reg = -1,
458 .mask = PMX_UART0_MODEM_MASK,
459 .val = PMX_UART0_MODEM_MASK,
460 },
461};
462
463static struct spear_modemux uart0_ext_modemux[] = {
464 {
465 .modes = ~0,
466 .muxregs = uart0_ext_muxreg,
467 .nmuxregs = ARRAY_SIZE(uart0_ext_muxreg),
468 },
469};
470
471struct spear_pingroup spear3xx_uart0_ext_pingroup = {
472 .name = "uart0_ext_grp",
473 .pins = uart0_ext_pins,
474 .npins = ARRAY_SIZE(uart0_ext_pins),
475 .modemuxs = uart0_ext_modemux,
476 .nmodemuxs = ARRAY_SIZE(uart0_ext_modemux),
477};
478
479static const char *const uart0_ext_grps[] = { "uart0_ext_grp" };
480struct spear_function spear3xx_uart0_ext_function = {
481 .name = "uart0_ext",
482 .groups = uart0_ext_grps,
483 .ngroups = ARRAY_SIZE(uart0_ext_grps),
484};
485
486/* uart0_pins */
487static const unsigned uart0_pins[] = { 2, 3 };
488static struct spear_muxreg uart0_muxreg[] = {
489 {
490 .reg = -1,
491 .mask = PMX_UART0_MASK,
492 .val = PMX_UART0_MASK,
493 },
494};
495
496static struct spear_modemux uart0_modemux[] = {
497 {
498 .modes = ~0,
499 .muxregs = uart0_muxreg,
500 .nmuxregs = ARRAY_SIZE(uart0_muxreg),
501 },
502};
503
504struct spear_pingroup spear3xx_uart0_pingroup = {
505 .name = "uart0_grp",
506 .pins = uart0_pins,
507 .npins = ARRAY_SIZE(uart0_pins),
508 .modemuxs = uart0_modemux,
509 .nmodemuxs = ARRAY_SIZE(uart0_modemux),
510};
511
512static const char *const uart0_grps[] = { "uart0_grp" };
513struct spear_function spear3xx_uart0_function = {
514 .name = "uart0",
515 .groups = uart0_grps,
516 .ngroups = ARRAY_SIZE(uart0_grps),
517};
518
519/* timer_0_1_pins */
520static const unsigned timer_0_1_pins[] = { 43, 44, 47, 48 };
521static struct spear_muxreg timer_0_1_muxreg[] = {
522 {
523 .reg = -1,
524 .mask = PMX_TIMER_0_1_MASK,
525 .val = PMX_TIMER_0_1_MASK,
526 },
527};
528
529static struct spear_modemux timer_0_1_modemux[] = {
530 {
531 .modes = ~0,
532 .muxregs = timer_0_1_muxreg,
533 .nmuxregs = ARRAY_SIZE(timer_0_1_muxreg),
534 },
535};
536
537struct spear_pingroup spear3xx_timer_0_1_pingroup = {
538 .name = "timer_0_1_grp",
539 .pins = timer_0_1_pins,
540 .npins = ARRAY_SIZE(timer_0_1_pins),
541 .modemuxs = timer_0_1_modemux,
542 .nmodemuxs = ARRAY_SIZE(timer_0_1_modemux),
543};
544
545static const char *const timer_0_1_grps[] = { "timer_0_1_grp" };
546struct spear_function spear3xx_timer_0_1_function = {
547 .name = "timer_0_1",
548 .groups = timer_0_1_grps,
549 .ngroups = ARRAY_SIZE(timer_0_1_grps),
550};
551
552/* timer_2_3_pins */
553static const unsigned timer_2_3_pins[] = { 45, 46, 49, 50 };
554static struct spear_muxreg timer_2_3_muxreg[] = {
555 {
556 .reg = -1,
557 .mask = PMX_TIMER_2_3_MASK,
558 .val = PMX_TIMER_2_3_MASK,
559 },
560};
561
562static struct spear_modemux timer_2_3_modemux[] = {
563 {
564 .modes = ~0,
565 .muxregs = timer_2_3_muxreg,
566 .nmuxregs = ARRAY_SIZE(timer_2_3_muxreg),
567 },
568};
569
570struct spear_pingroup spear3xx_timer_2_3_pingroup = {
571 .name = "timer_2_3_grp",
572 .pins = timer_2_3_pins,
573 .npins = ARRAY_SIZE(timer_2_3_pins),
574 .modemuxs = timer_2_3_modemux,
575 .nmodemuxs = ARRAY_SIZE(timer_2_3_modemux),
576};
577
578static const char *const timer_2_3_grps[] = { "timer_2_3_grp" };
579struct spear_function spear3xx_timer_2_3_function = {
580 .name = "timer_2_3",
581 .groups = timer_2_3_grps,
582 .ngroups = ARRAY_SIZE(timer_2_3_grps),
583};
584
585struct spear_pinctrl_machdata spear3xx_machdata = {
586 .pins = spear3xx_pins,
587 .npins = ARRAY_SIZE(spear3xx_pins),
588};
diff --git a/drivers/pinctrl/spear/pinctrl-spear3xx.h b/drivers/pinctrl/spear/pinctrl-spear3xx.h
new file mode 100644
index 000000000000..5d5fdd8df7b8
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear3xx.h
@@ -0,0 +1,92 @@
1/*
2 * Header file for the ST Microelectronics SPEAr3xx pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#ifndef __PINMUX_SPEAR3XX_H__
13#define __PINMUX_SPEAR3XX_H__
14
15#include "pinctrl-spear.h"
16
17/* pad mux declarations */
18#define PMX_FIRDA_MASK (1 << 14)
19#define PMX_I2C_MASK (1 << 13)
20#define PMX_SSP_CS_MASK (1 << 12)
21#define PMX_SSP_MASK (1 << 11)
22#define PMX_MII_MASK (1 << 10)
23#define PMX_GPIO_PIN0_MASK (1 << 9)
24#define PMX_GPIO_PIN1_MASK (1 << 8)
25#define PMX_GPIO_PIN2_MASK (1 << 7)
26#define PMX_GPIO_PIN3_MASK (1 << 6)
27#define PMX_GPIO_PIN4_MASK (1 << 5)
28#define PMX_GPIO_PIN5_MASK (1 << 4)
29#define PMX_UART0_MODEM_MASK (1 << 3)
30#define PMX_UART0_MASK (1 << 2)
31#define PMX_TIMER_2_3_MASK (1 << 1)
32#define PMX_TIMER_0_1_MASK (1 << 0)
33
34extern struct spear_pingroup spear3xx_firda_pingroup;
35extern struct spear_pingroup spear3xx_gpio0_pin0_pingroup;
36extern struct spear_pingroup spear3xx_gpio0_pin1_pingroup;
37extern struct spear_pingroup spear3xx_gpio0_pin2_pingroup;
38extern struct spear_pingroup spear3xx_gpio0_pin3_pingroup;
39extern struct spear_pingroup spear3xx_gpio0_pin4_pingroup;
40extern struct spear_pingroup spear3xx_gpio0_pin5_pingroup;
41extern struct spear_pingroup spear3xx_i2c_pingroup;
42extern struct spear_pingroup spear3xx_mii_pingroup;
43extern struct spear_pingroup spear3xx_ssp_cs_pingroup;
44extern struct spear_pingroup spear3xx_ssp_pingroup;
45extern struct spear_pingroup spear3xx_timer_0_1_pingroup;
46extern struct spear_pingroup spear3xx_timer_2_3_pingroup;
47extern struct spear_pingroup spear3xx_uart0_ext_pingroup;
48extern struct spear_pingroup spear3xx_uart0_pingroup;
49
50#define SPEAR3XX_COMMON_PINGROUPS \
51 &spear3xx_firda_pingroup, \
52 &spear3xx_gpio0_pin0_pingroup, \
53 &spear3xx_gpio0_pin1_pingroup, \
54 &spear3xx_gpio0_pin2_pingroup, \
55 &spear3xx_gpio0_pin3_pingroup, \
56 &spear3xx_gpio0_pin4_pingroup, \
57 &spear3xx_gpio0_pin5_pingroup, \
58 &spear3xx_i2c_pingroup, \
59 &spear3xx_mii_pingroup, \
60 &spear3xx_ssp_cs_pingroup, \
61 &spear3xx_ssp_pingroup, \
62 &spear3xx_timer_0_1_pingroup, \
63 &spear3xx_timer_2_3_pingroup, \
64 &spear3xx_uart0_ext_pingroup, \
65 &spear3xx_uart0_pingroup
66
67extern struct spear_function spear3xx_firda_function;
68extern struct spear_function spear3xx_gpio0_function;
69extern struct spear_function spear3xx_i2c_function;
70extern struct spear_function spear3xx_mii_function;
71extern struct spear_function spear3xx_ssp_cs_function;
72extern struct spear_function spear3xx_ssp_function;
73extern struct spear_function spear3xx_timer_0_1_function;
74extern struct spear_function spear3xx_timer_2_3_function;
75extern struct spear_function spear3xx_uart0_ext_function;
76extern struct spear_function spear3xx_uart0_function;
77
78#define SPEAR3XX_COMMON_FUNCTIONS \
79 &spear3xx_firda_function, \
80 &spear3xx_gpio0_function, \
81 &spear3xx_i2c_function, \
82 &spear3xx_mii_function, \
83 &spear3xx_ssp_cs_function, \
84 &spear3xx_ssp_function, \
85 &spear3xx_timer_0_1_function, \
86 &spear3xx_timer_2_3_function, \
87 &spear3xx_uart0_ext_function, \
88 &spear3xx_uart0_function
89
90extern struct spear_pinctrl_machdata spear3xx_machdata;
91
92#endif /* __PINMUX_SPEAR3XX_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-10 21:35:43 -0400