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-rw-r--r--arch/powerpc/boot/dts/mpc8569mds.dts514
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_mds.c23
2 files changed, 537 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/mpc8569mds.dts b/arch/powerpc/boot/dts/mpc8569mds.dts
new file mode 100644
index 000000000000..e16a5d4cbc26
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8569mds.dts
@@ -0,0 +1,514 @@
1/*
2 * MPC8569E MDS Device Tree Source
3 *
4 * Copyright (C) 2009 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 model = "MPC8569EMDS";
16 compatible = "fsl,MPC8569EMDS";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 serial0 = &serial0;
22 serial1 = &serial1;
23 ethernet0 = &enet0;
24 ethernet1 = &enet1;
25 ethernet2 = &enet2;
26 ethernet3 = &enet3;
27 pci1 = &pci1;
28 };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 PowerPC,8569@0 {
35 device_type = "cpu";
36 reg = <0x0>;
37 d-cache-line-size = <32>; // 32 bytes
38 i-cache-line-size = <32>; // 32 bytes
39 d-cache-size = <0x8000>; // L1, 32K
40 i-cache-size = <0x8000>; // L1, 32K
41 timebase-frequency = <0>;
42 bus-frequency = <0>;
43 clock-frequency = <0>;
44 next-level-cache = <&L2>;
45 };
46 };
47
48 memory {
49 device_type = "memory";
50 };
51
52 localbus@e0005000 {
53 #address-cells = <2>;
54 #size-cells = <1>;
55 compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
56 reg = <0 0xe0005000 0 0x1000>;
57 interrupt = <19 2>;
58 interrupt-parent = <&mpic>;
59
60 ranges = <0x0 0x0 0xfe000000 0x02000000
61 0x1 0x0 0xf8000000 0x00008000
62 0x2 0x0 0xf0000000 0x04000000
63 0x4 0x0 0xf8008000 0x00008000
64 0x5 0x0 0xf8010000 0x00008000>;
65
66 nor@0,0 {
67 #address-cells = <1>;
68 #size-cells = <1>;
69 compatible = "cfi-flash";
70 reg = <0x0 0x0 0x02000000>;
71 bank-width = <2>;
72 device-width = <1>;
73 };
74
75 bcsr@1,0 {
76 compatible = "fsl,mpc8569mds-bcsr";
77 reg = <1 0 0x8000>;
78 };
79
80 pib@4,0 {
81 compatible = "fsl,mpc8569mds-pib";
82 reg = <4 0 0x8000>;
83 };
84
85 pib@5,0 {
86 compatible = "fsl,mpc8569mds-pib";
87 reg = <5 0 0x8000>;
88 };
89 };
90
91 soc@e0000000 {
92 #address-cells = <1>;
93 #size-cells = <1>;
94 device_type = "soc";
95 compatible = "fsl,mpc8569-immr", "simple-bus";
96 ranges = <0x0 0xe0000000 0x100000>;
97 reg = <0xe0000000 0x1000>;
98 bus-frequency = <0>;
99
100 ecm-law@0 {
101 compatible = "fsl,ecm-law";
102 reg = <0x0 0x1000>;
103 fsl,num-laws = <10>;
104 };
105
106 ecm@1000 {
107 compatible = "fsl,mpc8569-ecm", "fsl,ecm";
108 reg = <0x1000 0x1000>;
109 interrupts = <17 2>;
110 interrupt-parent = <&mpic>;
111 };
112
113 memory-controller@2000 {
114 compatible = "fsl,mpc8569-memory-controller";
115 reg = <0x2000 0x1000>;
116 interrupt-parent = <&mpic>;
117 interrupts = <18 2>;
118 };
119
120 i2c@3000 {
121 #address-cells = <1>;
122 #size-cells = <0>;
123 cell-index = <0>;
124 compatible = "fsl-i2c";
125 reg = <0x3000 0x100>;
126 interrupts = <43 2>;
127 interrupt-parent = <&mpic>;
128 dfsrr;
129
130 rtc@68 {
131 compatible = "dallas,ds1374";
132 reg = <0x68>;
133 };
134 };
135
136 i2c@3100 {
137 #address-cells = <1>;
138 #size-cells = <0>;
139 cell-index = <1>;
140 compatible = "fsl-i2c";
141 reg = <0x3100 0x100>;
142 interrupts = <43 2>;
143 interrupt-parent = <&mpic>;
144 dfsrr;
145 };
146
147 serial0: serial@4500 {
148 cell-index = <0>;
149 device_type = "serial";
150 compatible = "ns16550";
151 reg = <0x4500 0x100>;
152 clock-frequency = <0>;
153 interrupts = <42 2>;
154 interrupt-parent = <&mpic>;
155 };
156
157 serial1: serial@4600 {
158 cell-index = <1>;
159 device_type = "serial";
160 compatible = "ns16550";
161 reg = <0x4600 0x100>;
162 clock-frequency = <0>;
163 interrupts = <42 2>;
164 interrupt-parent = <&mpic>;
165 };
166
167 L2: l2-cache-controller@20000 {
168 compatible = "fsl,mpc8569-l2-cache-controller";
169 reg = <0x20000 0x1000>;
170 cache-line-size = <32>; // 32 bytes
171 cache-size = <0x80000>; // L2, 512K
172 interrupt-parent = <&mpic>;
173 interrupts = <16 2>;
174 };
175
176 dma@21300 {
177 #address-cells = <1>;
178 #size-cells = <1>;
179 compatible = "fsl,mpc8569-dma", "fsl,eloplus-dma";
180 reg = <0x21300 0x4>;
181 ranges = <0x0 0x21100 0x200>;
182 cell-index = <0>;
183 dma-channel@0 {
184 compatible = "fsl,mpc8569-dma-channel",
185 "fsl,eloplus-dma-channel";
186 reg = <0x0 0x80>;
187 cell-index = <0>;
188 interrupt-parent = <&mpic>;
189 interrupts = <20 2>;
190 };
191 dma-channel@80 {
192 compatible = "fsl,mpc8569-dma-channel",
193 "fsl,eloplus-dma-channel";
194 reg = <0x80 0x80>;
195 cell-index = <1>;
196 interrupt-parent = <&mpic>;
197 interrupts = <21 2>;
198 };
199 dma-channel@100 {
200 compatible = "fsl,mpc8569-dma-channel",
201 "fsl,eloplus-dma-channel";
202 reg = <0x100 0x80>;
203 cell-index = <2>;
204 interrupt-parent = <&mpic>;
205 interrupts = <22 2>;
206 };
207 dma-channel@180 {
208 compatible = "fsl,mpc8569-dma-channel",
209 "fsl,eloplus-dma-channel";
210 reg = <0x180 0x80>;
211 cell-index = <3>;
212 interrupt-parent = <&mpic>;
213 interrupts = <23 2>;
214 };
215 };
216
217 crypto@30000 {
218 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
219 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
220 reg = <0x30000 0x10000>;
221 interrupts = <45 2 58 2>;
222 interrupt-parent = <&mpic>;
223 fsl,num-channels = <4>;
224 fsl,channel-fifo-len = <24>;
225 fsl,exec-units-mask = <0x9fe>;
226 fsl,descriptor-types-mask = <0x3ab0ebf>;
227 };
228
229 mpic: pic@40000 {
230 interrupt-controller;
231 #address-cells = <0>;
232 #interrupt-cells = <2>;
233 reg = <0x40000 0x40000>;
234 compatible = "chrp,open-pic";
235 device_type = "open-pic";
236 };
237
238 global-utilities@e0000 {
239 compatible = "fsl,mpc8569-guts";
240 reg = <0xe0000 0x1000>;
241 fsl,has-rstcr;
242 };
243
244 par_io@e0100 {
245 reg = <0xe0100 0x100>;
246 device_type = "par_io";
247 num-ports = <7>;
248
249 pio1: ucc_pin@01 {
250 pio-map = <
251 /* port pin dir open_drain assignment has_irq */
252 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
253 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
254 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
255 0x0 0x0 0x1 0x0 0x3 0x0 /* ENET1_TXD0_SER1_TXD0 */
256 0x0 0x1 0x1 0x0 0x3 0x0 /* ENET1_TXD1_SER1_TXD1 */
257 0x0 0x2 0x1 0x0 0x1 0x0 /* ENET1_TXD2_SER1_TXD2 */
258 0x0 0x3 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
259 0x0 0x6 0x2 0x0 0x3 0x0 /* ENET1_RXD0_SER1_RXD0 */
260 0x0 0x7 0x2 0x0 0x1 0x0 /* ENET1_RXD1_SER1_RXD1 */
261 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
262 0x0 0x9 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
263 0x0 0x4 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
264 0x0 0xc 0x2 0x0 0x3 0x0 /* ENET1_RX_DV_SER1_CTS_B */
265 0x2 0x8 0x2 0x0 0x1 0x0 /* ENET1_GRXCLK */
266 0x2 0x14 0x1 0x0 0x2 0x0>; /* ENET1_GTXCLK */
267 };
268
269 pio2: ucc_pin@02 {
270 pio-map = <
271 /* port pin dir open_drain assignment has_irq */
272 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
273 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
274 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
275 0x0 0xe 0x1 0x0 0x2 0x0 /* ENET2_TXD0_SER2_TXD0 */
276 0x0 0xf 0x1 0x0 0x2 0x0 /* ENET2_TXD1_SER2_TXD1 */
277 0x0 0x10 0x1 0x0 0x1 0x0 /* ENET2_TXD2_SER2_TXD2 */
278 0x0 0x11 0x1 0x0 0x1 0x0 /* ENET2_TXD3_SER2_TXD3 */
279 0x0 0x14 0x2 0x0 0x2 0x0 /* ENET2_RXD0_SER2_RXD0 */
280 0x0 0x15 0x2 0x0 0x1 0x0 /* ENET2_RXD1_SER2_RXD1 */
281 0x0 0x16 0x2 0x0 0x1 0x0 /* ENET2_RXD2_SER2_RXD2 */
282 0x0 0x17 0x2 0x0 0x1 0x0 /* ENET2_RXD3_SER2_RXD3 */
283 0x0 0x12 0x1 0x0 0x2 0x0 /* ENET2_TX_EN_SER2_RTS_B */
284 0x0 0x1a 0x2 0x0 0x3 0x0 /* ENET2_RX_DV_SER2_CTS_B */
285 0x2 0x3 0x2 0x0 0x1 0x0 /* ENET2_GRXCLK */
286 0x2 0x2 0x1 0x0 0x2 0x0>; /* ENET2_GTXCLK */
287 };
288
289 pio3: ucc_pin@03 {
290 pio-map = <
291 /* port pin dir open_drain assignment has_irq */
292 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
293 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
294 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
295 0x0 0x1d 0x1 0x0 0x2 0x0 /* ENET3_TXD0_SER3_TXD0 */
296 0x0 0x1e 0x1 0x0 0x3 0x0 /* ENET3_TXD1_SER3_TXD1 */
297 0x0 0x1f 0x1 0x0 0x2 0x0 /* ENET3_TXD2_SER3_TXD2 */
298 0x1 0x0 0x1 0x0 0x3 0x0 /* ENET3_TXD3_SER3_TXD3 */
299 0x1 0x3 0x2 0x0 0x3 0x0 /* ENET3_RXD0_SER3_RXD0 */
300 0x1 0x4 0x2 0x0 0x1 0x0 /* ENET3_RXD1_SER3_RXD1 */
301 0x1 0x5 0x2 0x0 0x2 0x0 /* ENET3_RXD2_SER3_RXD2 */
302 0x1 0x6 0x2 0x0 0x3 0x0 /* ENET3_RXD3_SER3_RXD3 */
303 0x1 0x1 0x1 0x0 0x1 0x0 /* ENET3_TX_EN_SER3_RTS_B */
304 0x1 0x9 0x2 0x0 0x3 0x0 /* ENET3_RX_DV_SER3_CTS_B */
305 0x2 0x9 0x2 0x0 0x2 0x0 /* ENET3_GRXCLK */
306 0x2 0x19 0x1 0x0 0x2 0x0>; /* ENET3_GTXCLK */
307 };
308
309 pio4: ucc_pin@04 {
310 pio-map = <
311 /* port pin dir open_drain assignment has_irq */
312 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
313 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
314 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
315 0x1 0xc 0x1 0x0 0x2 0x0 /* ENET4_TXD0_SER4_TXD0 */
316 0x1 0xd 0x1 0x0 0x2 0x0 /* ENET4_TXD1_SER4_TXD1 */
317 0x1 0xe 0x1 0x0 0x1 0x0 /* ENET4_TXD2_SER4_TXD2 */
318 0x1 0xf 0x1 0x0 0x2 0x0 /* ENET4_TXD3_SER4_TXD3 */
319 0x1 0x12 0x2 0x0 0x2 0x0 /* ENET4_RXD0_SER4_RXD0 */
320 0x1 0x13 0x2 0x0 0x1 0x0 /* ENET4_RXD1_SER4_RXD1 */
321 0x1 0x14 0x2 0x0 0x1 0x0 /* ENET4_RXD2_SER4_RXD2 */
322 0x1 0x15 0x2 0x0 0x2 0x0 /* ENET4_RXD3_SER4_RXD3 */
323 0x1 0x10 0x1 0x0 0x2 0x0 /* ENET4_TX_EN_SER4_RTS_B */
324 0x1 0x18 0x2 0x0 0x3 0x0 /* ENET4_RX_DV_SER4_CTS_B */
325 0x2 0x11 0x2 0x0 0x2 0x0 /* ENET4_GRXCLK */
326 0x2 0x18 0x1 0x0 0x2 0x0>; /* ENET4_GTXCLK */
327 };
328 };
329 };
330
331 qe@e0080000 {
332 #address-cells = <1>;
333 #size-cells = <1>;
334 device_type = "qe";
335 compatible = "fsl,qe";
336 ranges = <0x0 0xe0080000 0x40000>;
337 reg = <0xe0080000 0x480>;
338 brg-frequency = <0>;
339 bus-frequency = <0>;
340 fsl,qe-num-riscs = <4>;
341 fsl,qe-num-snums = <46>;
342
343 qeic: interrupt-controller@80 {
344 interrupt-controller;
345 compatible = "fsl,qe-ic";
346 #address-cells = <0>;
347 #interrupt-cells = <1>;
348 reg = <0x80 0x80>;
349 interrupts = <46 2 46 2>; //high:30 low:30
350 interrupt-parent = <&mpic>;
351 };
352
353 spi@4c0 {
354 cell-index = <0>;
355 compatible = "fsl,spi";
356 reg = <0x4c0 0x40>;
357 interrupts = <2>;
358 interrupt-parent = <&qeic>;
359 mode = "cpu";
360 };
361
362 spi@500 {
363 cell-index = <1>;
364 compatible = "fsl,spi";
365 reg = <0x500 0x40>;
366 interrupts = <1>;
367 interrupt-parent = <&qeic>;
368 mode = "cpu";
369 };
370
371 enet0: ucc@2000 {
372 device_type = "network";
373 compatible = "ucc_geth";
374 cell-index = <1>;
375 reg = <0x2000 0x200>;
376 interrupts = <32>;
377 interrupt-parent = <&qeic>;
378 local-mac-address = [ 00 00 00 00 00 00 ];
379 rx-clock-name = "none";
380 tx-clock-name = "clk12";
381 pio-handle = <&pio1>;
382 phy-handle = <&qe_phy0>;
383 phy-connection-type = "rgmii-id";
384 };
385
386 mdio@2120 {
387 #address-cells = <1>;
388 #size-cells = <0>;
389 reg = <0x2120 0x18>;
390 compatible = "fsl,ucc-mdio";
391
392 qe_phy0: ethernet-phy@07 {
393 interrupt-parent = <&mpic>;
394 interrupts = <1 1>;
395 reg = <0x7>;
396 device_type = "ethernet-phy";
397 };
398 qe_phy1: ethernet-phy@01 {
399 interrupt-parent = <&mpic>;
400 interrupts = <2 1>;
401 reg = <0x1>;
402 device_type = "ethernet-phy";
403 };
404 qe_phy2: ethernet-phy@02 {
405 interrupt-parent = <&mpic>;
406 interrupts = <3 1>;
407 reg = <0x2>;
408 device_type = "ethernet-phy";
409 };
410 qe_phy3: ethernet-phy@03 {
411 interrupt-parent = <&mpic>;
412 interrupts = <4 1>;
413 reg = <0x3>;
414 device_type = "ethernet-phy";
415 };
416 };
417
418 enet2: ucc@2200 {
419 device_type = "network";
420 compatible = "ucc_geth";
421 cell-index = <3>;
422 reg = <0x2200 0x200>;
423 interrupts = <34>;
424 interrupt-parent = <&qeic>;
425 local-mac-address = [ 00 00 00 00 00 00 ];
426 rx-clock-name = "none";
427 tx-clock-name = "clk12";
428 pio-handle = <&pio3>;
429 phy-handle = <&qe_phy2>;
430 phy-connection-type = "rgmii-id";
431 };
432
433 enet1: ucc@3000 {
434 device_type = "network";
435 compatible = "ucc_geth";
436 cell-index = <2>;
437 reg = <0x3000 0x200>;
438 interrupts = <33>;
439 interrupt-parent = <&qeic>;
440 local-mac-address = [ 00 00 00 00 00 00 ];
441 rx-clock-name = "none";
442 tx-clock-name = "clk17";
443 pio-handle = <&pio2>;
444 phy-handle = <&qe_phy1>;
445 phy-connection-type = "rgmii-id";
446 };
447
448 enet3: ucc@3200 {
449 device_type = "network";
450 compatible = "ucc_geth";
451 cell-index = <4>;
452 reg = <0x3200 0x200>;
453 interrupts = <35>;
454 interrupt-parent = <&qeic>;
455 local-mac-address = [ 00 00 00 00 00 00 ];
456 rx-clock-name = "none";
457 tx-clock-name = "clk17";
458 pio-handle = <&pio4>;
459 phy-handle = <&qe_phy3>;
460 phy-connection-type = "rgmii-id";
461 };
462
463 muram@10000 {
464 #address-cells = <1>;
465 #size-cells = <1>;
466 compatible = "fsl,qe-muram", "fsl,cpm-muram";
467 ranges = <0x0 0x10000 0x20000>;
468
469 data-only@0 {
470 compatible = "fsl,qe-muram-data",
471 "fsl,cpm-muram-data";
472 reg = <0x0 0x20000>;
473 };
474 };
475
476 };
477
478 /* PCI Express */
479 pci1: pcie@e000a000 {
480 compatible = "fsl,mpc8548-pcie";
481 device_type = "pci";
482 #interrupt-cells = <1>;
483 #size-cells = <2>;
484 #address-cells = <3>;
485 reg = <0xe000a000 0x1000>;
486 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
487 interrupt-map = <
488 /* IDSEL 0x0 (PEX) */
489 00000 0x0 0x0 0x1 &mpic 0x0 0x1
490 00000 0x0 0x0 0x2 &mpic 0x1 0x1
491 00000 0x0 0x0 0x3 &mpic 0x2 0x1
492 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
493
494 interrupt-parent = <&mpic>;
495 interrupts = <26 2>;
496 bus-range = <0 255>;
497 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
498 0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>;
499 clock-frequency = <33333333>;
500 pcie@0 {
501 reg = <0x0 0x0 0x0 0x0 0x0>;
502 #size-cells = <2>;
503 #address-cells = <3>;
504 device_type = "pci";
505 ranges = <0x2000000 0x0 0xa0000000
506 0x2000000 0x0 0xa0000000
507 0x0 0x10000000
508
509 0x1000000 0x0 0x0
510 0x1000000 0x0 0x0
511 0x0 0x800000>;
512 };
513 };
514};
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index d34d29acbd3d..b2c0a4319973 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -259,6 +259,7 @@ static int __init board_fixups(void)
259 return 0; 259 return 0;
260} 260}
261machine_arch_initcall(mpc8568_mds, board_fixups); 261machine_arch_initcall(mpc8568_mds, board_fixups);
262machine_arch_initcall(mpc8569_mds, board_fixups);
262 263
263static struct of_device_id mpc85xx_ids[] = { 264static struct of_device_id mpc85xx_ids[] = {
264 { .type = "soc", }, 265 { .type = "soc", },
@@ -278,6 +279,7 @@ static int __init mpc85xx_publish_devices(void)
278 return 0; 279 return 0;
279} 280}
280machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices); 281machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
282machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices);
281 283
282static void __init mpc85xx_mds_pic_init(void) 284static void __init mpc85xx_mds_pic_init(void)
283{ 285{
@@ -335,3 +337,24 @@ define_machine(mpc8568_mds) {
335 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 337 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
336#endif 338#endif
337}; 339};
340
341static int __init mpc8569_mds_probe(void)
342{
343 unsigned long root = of_get_flat_dt_root();
344
345 return of_flat_dt_is_compatible(root, "fsl,MPC8569EMDS");
346}
347
348define_machine(mpc8569_mds) {
349 .name = "MPC8569 MDS",
350 .probe = mpc8569_mds_probe,
351 .setup_arch = mpc85xx_mds_setup_arch,
352 .init_IRQ = mpc85xx_mds_pic_init,
353 .get_irq = mpic_get_irq,
354 .restart = fsl_rstcr_restart,
355 .calibrate_decr = generic_calibrate_decr,
356 .progress = udbg_progress,
357#ifdef CONFIG_PCI
358 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
359#endif
360};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-23 04:47:27 -0500