122 files changed, 12914 insertions, 5968 deletions

diff --git a/Documentation/arm/SPEAr/overview.txt b/Documentation/arm/SPEAr/overview.txt
index 253a35c6f782..28a9af953b9d 100644
--- a/Documentation/arm/SPEAr/overview.txt
+++ b/Documentation/arm/SPEAr/overview.txt
@@ -17,14 +17,14 @@ Introduction
   SPEAr (Platform)
         - SPEAr3XX (3XX SOC series, based on ARM9)
                 - SPEAr300 (SOC)
-                        - SPEAr300_EVB (Evaluation Board)
+                        - SPEAr300 Evaluation Board
                 - SPEAr310 (SOC)
-                        - SPEAr310_EVB (Evaluation Board)
+                        - SPEAr310 Evaluation Board
                 - SPEAr320 (SOC)
-                        - SPEAr320_EVB (Evaluation Board)
+                        - SPEAr320 Evaluation Board
         - SPEAr6XX (6XX SOC series, based on ARM9)
                 - SPEAr600 (SOC)
-                        - SPEAr600_EVB (Evaluation Board)
+                        - SPEAr600 Evaluation Board
         - SPEAr13XX (13XX SOC series, based on ARM CORTEXA9)
                 - SPEAr1300 (SOC)
 
@@ -51,10 +51,11 @@ Introduction
   Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c and for
   spear6xx is mach-spear6xx/spear6xx.c. mach-spear* also contain soc/machine
   specific files, like spear300.c, spear310.c, spear320.c and spear600.c.
-  mach-spear* also contains board specific files for each machine type.
+  mach-spear* doesn't contains board specific files as they fully support
+  Flattened Device Tree.
 
 
   Document Author
   ---------------
 
-  Viresh Kumar, (c) 2010 ST Microelectronics
+  Viresh Kumar <viresh.kumar@st.com>, (c) 2010-2012 ST Microelectronics
diff --git a/Documentation/devicetree/bindings/arm/spear.txt b/Documentation/devicetree/bindings/arm/spear.txt
index f8e54f092328..aa5f355cc947 100644
--- a/Documentation/devicetree/bindings/arm/spear.txt
+++ b/Documentation/devicetree/bindings/arm/spear.txt
@@ -6,3 +6,21 @@ Boards with the ST SPEAr600 SoC shall have the following properties:
 Required root node property:
 
 compatible = "st,spear600";
+
+Boards with the ST SPEAr300 SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "st,spear300";
+
+Boards with the ST SPEAr310 SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "st,spear310";
+
+Boards with the ST SPEAr320 SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "st,spear320";
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt
new file mode 100644
index 000000000000..c8e578263ce2
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt
@@ -0,0 +1,132 @@
+NVIDIA Tegra20 pinmux controller
+
+Required properties:
+- compatible: "nvidia,tegra20-pinmux"
+- reg: Should contain the register physical address and length for each of
+  the tri-state, mux, pull-up/down, and pad control register sets.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+Tegra's pin configuration nodes act as a container for an abitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, tristate, drive strength, etc.
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function or tristate parameter. For this
+reason, even seemingly boolean values are actually tristates in this binding:
+unspecified, off, or on. Unspecified is represented as an absent property,
+and off/on are represented as integer values 0 and 1.
+
+Required subnode-properties:
+- nvidia,pins : An array of strings. Each string contains the name of a pin or
+    group. Valid values for these names are listed below.
+
+Optional subnode-properties:
+- nvidia,function: A string containing the name of the function to mux to the
+  pin or group. Valid values for function names are listed below. See the Tegra
+  TRM to determine which are valid for each pin or group.
+- nvidia,pull: Integer, representing the pull-down/up to apply to the pin.
+    0: none, 1: down, 2: up.
+- nvidia,tristate: Integer.
+    0: drive, 1: tristate.
+- nvidia,high-speed-mode: Integer. Enable high speed mode the pins.
+    0: no, 1: yes.
+- nvidia,schmitt: Integer. Enables Schmitt Trigger on the input.
+    0: no, 1: yes.
+- nvidia,low-power-mode: Integer. Valid values 0-3. 0 is least power, 3 is
+    most power. Controls the drive power or current. See "Low Power Mode"
+    or "LPMD1" and "LPMD0" in the Tegra TRM.
+- nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest.
+    The range of valid values depends on the pingroup. See "CAL_DRVDN" in the
+    Tegra TRM.
+- nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest.
+    The range of valid values depends on the pingroup. See "CAL_DRVUP" in the
+    Tegra TRM.
+- nvidia,slew-rate-rising: Integer. Controls rising signal slew rate. 0 is
+    fastest. The range of valid values depends on the pingroup. See
+    "DRVDN_SLWR" in the Tegra TRM.
+- nvidia,slew-rate-falling: Integer. Controls falling signal slew rate. 0 is
+    fastest. The range of valid values depends on the pingroup. See
+    "DRVUP_SLWF" in the Tegra TRM.
+
+Note that many of these properties are only valid for certain specific pins
+or groups. See the Tegra TRM and various pinmux spreadsheets for complete
+details regarding which groups support which functionality. The Linux pinctrl
+driver may also be a useful reference, since it consolidates, disambiguates,
+and corrects data from all those sources.
+
+Valid values for pin and group names are:
+
+  mux groups:
+
+    These all support nvidia,function, nvidia,tristate, and many support
+    nvidia,pull.
+
+    ata, atb, atc, atd, ate, cdev1, cdev2, crtp, csus, dap1, dap2, dap3, dap4,
+    ddc, dta, dtb, dtc, dtd, dte, dtf, gma, gmb, gmc, gmd, gme, gpu, gpu7,
+    gpv, hdint, i2cp, irrx, irtx, kbca, kbcb, kbcc, kbcd, kbce, kbcf, lcsn,
+    ld0, ld1, ld2, ld3, ld4, ld5, ld6, ld7, ld8, ld9, ld10, ld11, ld12, ld13,
+    ld14, ld15, ld16, ld17, ldc, ldi, lhp0, lhp1, lhp2, lhs, lm0, lm1, lpp,
+    lpw0, lpw1, lpw2, lsc0, lsc1, lsck, lsda, lsdi, lspi, lvp0, lvp1, lvs,
+    owc, pmc, pta, rm, sdb, sdc, sdd, sdio1, slxa, slxc, slxd, slxk, spdi,
+    spdo, spia, spib, spic, spid, spie, spif, spig, spih, uaa, uab, uac, uad,
+    uca, ucb, uda.
+
+  tristate groups:
+
+    These only support nvidia,pull.
+
+    ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls, lc, ld17_0,
+    ld19_18, ld21_20, ld23_22.
+
+  drive groups:
+
+    With some exceptions, these support nvidia,high-speed-mode,
+    nvidia,schmitt, nvidia,low-power-mode, nvidia,pull-down-strength,
+    nvidia,pull-up-strength, nvidia,slew_rate-rising, nvidia,slew_rate-falling.
+
+    drive_ao1, drive_ao2, drive_at1, drive_at2, drive_cdev1, drive_cdev2,
+    drive_csus, drive_dap1, drive_dap2, drive_dap3, drive_dap4, drive_dbg,
+    drive_lcd1, drive_lcd2, drive_sdmmc2, drive_sdmmc3, drive_spi, drive_uaa,
+    drive_uab, drive_uart2, drive_uart3, drive_vi1, drive_vi2, drive_xm2a,
+    drive_xm2c, drive_xm2d, drive_xm2clk, drive_sdio1, drive_crt, drive_ddc,
+    drive_gma, drive_gmb, drive_gmc, drive_gmd, drive_gme, drive_owr,
+    drive_uda.
+
+Example:
+
+        pinctrl@70000000 {
+                compatible = "nvidia,tegra20-pinmux";
+                reg = < 0x70000014 0x10    /* Tri-state registers */
+                        0x70000080 0x20    /* Mux registers */
+                        0x700000a0 0x14    /* Pull-up/down registers */
+                        0x70000868 0xa8 >; /* Pad control registers */
+        };
+
+Example board file extract:
+
+        pinctrl@70000000 {
+                sdio4_default: sdio4_default {
+                        atb {
+                                nvidia,pins = "atb", "gma", "gme";
+                                nvidia,function = "sdio4";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                };
+        };
+
+        sdhci@c8000600 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&sdio4_default>;
+        };
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt
new file mode 100644
index 000000000000..c275b70349c1
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt
@@ -0,0 +1,132 @@
+NVIDIA Tegra30 pinmux controller
+
+The Tegra30 pinctrl binding is very similar to the Tegra20 pinctrl binding,
+as described in nvidia,tegra20-pinmux.txt. In fact, this document assumes
+that binding as a baseline, and only documents the differences between the
+two bindings.
+
+Required properties:
+- compatible: "nvidia,tegra30-pinmux"
+- reg: Should contain the register physical address and length for each of
+  the pad control and mux registers.
+
+Tegra30 adds the following optional properties for pin configuration subnodes:
+- nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
+- nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
+- nvidia,lock: Integer. Lock the pin configuration against further changes
+    until reset. 0: no, 1: yes.
+- nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
+
+As with Tegra20, see the Tegra TRM for complete details regarding which groups
+support which functionality.
+
+Valid values for pin and group names are:
+
+  per-pin mux groups:
+
+    These all support nvidia,function, nvidia,tristate, nvidia,pull,
+    nvidia,enable-input, nvidia,lock. Some support nvidia,open-drain,
+    nvidia,io-reset.
+
+    clk_32k_out_pa0, uart3_cts_n_pa1, dap2_fs_pa2, dap2_sclk_pa3,
+    dap2_din_pa4, dap2_dout_pa5, sdmmc3_clk_pa6, sdmmc3_cmd_pa7, gmi_a17_pb0,
+    gmi_a18_pb1, lcd_pwr0_pb2, lcd_pclk_pb3, sdmmc3_dat3_pb4, sdmmc3_dat2_pb5,
+    sdmmc3_dat1_pb6, sdmmc3_dat0_pb7, uart3_rts_n_pc0, lcd_pwr1_pc1,
+    uart2_txd_pc2, uart2_rxd_pc3, gen1_i2c_scl_pc4, gen1_i2c_sda_pc5,
+    lcd_pwr2_pc6, gmi_wp_n_pc7, sdmmc3_dat5_pd0, sdmmc3_dat4_pd1, lcd_dc1_pd2,
+    sdmmc3_dat6_pd3, sdmmc3_dat7_pd4, vi_d1_pd5, vi_vsync_pd6, vi_hsync_pd7,
+    lcd_d0_pe0, lcd_d1_pe1, lcd_d2_pe2, lcd_d3_pe3, lcd_d4_pe4, lcd_d5_pe5,
+    lcd_d6_pe6, lcd_d7_pe7, lcd_d8_pf0, lcd_d9_pf1, lcd_d10_pf2, lcd_d11_pf3,
+    lcd_d12_pf4, lcd_d13_pf5, lcd_d14_pf6, lcd_d15_pf7, gmi_ad0_pg0,
+    gmi_ad1_pg1, gmi_ad2_pg2, gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5,
+    gmi_ad6_pg6, gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2,
+    gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6, gmi_ad15_ph7,
+    gmi_wr_n_pi0, gmi_oe_n_pi1, gmi_dqs_pi2, gmi_cs6_n_pi3, gmi_rst_n_pi4,
+    gmi_iordy_pi5, gmi_cs7_n_pi6, gmi_wait_pi7, gmi_cs0_n_pj0, lcd_de_pj1,
+    gmi_cs1_n_pj2, lcd_hsync_pj3, lcd_vsync_pj4, uart2_cts_n_pj5,
+    uart2_rts_n_pj6, gmi_a16_pj7, gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs4_n_pk2,
+    gmi_cs2_n_pk3, gmi_cs3_n_pk4, spdif_out_pk5, spdif_in_pk6, gmi_a19_pk7,
+    vi_d2_pl0, vi_d3_pl1, vi_d4_pl2, vi_d5_pl3, vi_d6_pl4, vi_d7_pl5,
+    vi_d8_pl6, vi_d9_pl7, lcd_d16_pm0, lcd_d17_pm1, lcd_d18_pm2, lcd_d19_pm3,
+    lcd_d20_pm4, lcd_d21_pm5, lcd_d22_pm6, lcd_d23_pm7, dap1_fs_pn0,
+    dap1_din_pn1, dap1_dout_pn2, dap1_sclk_pn3, lcd_cs0_n_pn4, lcd_sdout_pn5,
+    lcd_dc0_pn6, hdmi_int_pn7, ulpi_data7_po0, ulpi_data0_po1, ulpi_data1_po2,
+    ulpi_data2_po3, ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6,
+    ulpi_data6_po7, dap3_fs_pp0, dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3,
+    dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, kb_col0_pq0,
+    kb_col1_pq1, kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5,
+    kb_col6_pq6, kb_col7_pq7, kb_row0_pr0, kb_row1_pr1, kb_row2_pr2,
+    kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7,
+    kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3, kb_row12_ps4,
+    kb_row13_ps5, kb_row14_ps6, kb_row15_ps7, vi_pclk_pt0, vi_mclk_pt1,
+    vi_d10_pt2, vi_d11_pt3, vi_d0_pt4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6,
+    sdmmc4_cmd_pt7, pu0, pu1, pu2, pu3, pu4, pu5, pu6, jtag_rtck_pu7, pv0,
+    pv1, pv2, pv3, ddc_scl_pv4, ddc_sda_pv5, crt_hsync_pv6, crt_vsync_pv7,
+    lcd_cs1_n_pw0, lcd_m1_pw1, spi2_cs1_n_pw2, spi2_cs2_n_pw3, clk1_out_pw4,
+    clk2_out_pw5, uart3_txd_pw6, uart3_rxd_pw7, spi2_mosi_px0, spi2_miso_px1,
+    spi2_sck_px2, spi2_cs0_n_px3, spi1_mosi_px4, spi1_sck_px5, spi1_cs0_n_px6,
+    spi1_miso_px7, ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3,
+    sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6, sdmmc1_dat0_py7,
+    sdmmc1_clk_pz0, sdmmc1_cmd_pz1, lcd_sdin_pz2, lcd_wr_n_pz3, lcd_sck_pz4,
+    sys_clk_req_pz5, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, sdmmc4_dat0_paa0,
+    sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4,
+    sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, pbb0,
+    cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, pbb7,
+    cam_mclk_pcc0, pcc1, pcc2, sdmmc4_rst_n_pcc3, sdmmc4_clk_pcc4,
+    clk2_req_pcc5, pex_l2_rst_n_pcc6, pex_l2_clkreq_n_pcc7,
+    pex_l0_prsnt_n_pdd0, pex_l0_rst_n_pdd1, pex_l0_clkreq_n_pdd2,
+    pex_wake_n_pdd3, pex_l1_prsnt_n_pdd4, pex_l1_rst_n_pdd5,
+    pex_l1_clkreq_n_pdd6, pex_l2_prsnt_n_pdd7, clk3_out_pee0, clk3_req_pee1,
+    clk1_req_pee2, hdmi_cec_pee3, clk_32k_in, core_pwr_req, cpu_pwr_req, owr,
+    pwr_int_n.
+
+  drive groups:
+
+    These all support nvidia,pull-down-strength, nvidia,pull-up-strength,
+    nvidia,slew_rate-rising, nvidia,slew_rate-falling. Most but not all
+    support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode.
+
+    ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, cec, crt, csus, dap1,
+    dap2, dap3, dap4, dbg, ddc, dev3, gma, gmb, gmc, gmd, gme, gmf, gmg,
+    gmh, gpv, lcd1, lcd2, owr, sdio1, sdio2, sdio3, spi, uaa, uab, uart2,
+    uart3, uda, vi1.
+
+Example:
+
+        pinctrl@70000000 {
+                compatible = "nvidia,tegra30-pinmux";
+                reg = < 0x70000868 0xd0     /* Pad control registers */
+                        0x70003000 0x3e0 >; /* Mux registers */
+        };
+
+Example board file extract:
+
+        pinctrl@70000000 {
+                sdmmc4_default: pinmux {
+                        sdmmc4_clk_pcc4 {
+                                nvidia,pins =   "sdmmc4_clk_pcc4",
+                                                "sdmmc4_rst_n_pcc3";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        sdmmc4_dat0_paa0 {
+                                nvidia,pins =   "sdmmc4_dat0_paa0",
+                                                "sdmmc4_dat1_paa1",
+                                                "sdmmc4_dat2_paa2",
+                                                "sdmmc4_dat3_paa3",
+                                                "sdmmc4_dat4_paa4",
+                                                "sdmmc4_dat5_paa5",
+                                                "sdmmc4_dat6_paa6",
+                                                "sdmmc4_dat7_paa7";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <0>;
+                        };
+                };
+        };
+
+        sdhci@78000400 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&sdmmc4_default>;
+        };
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
new file mode 100644
index 000000000000..c95ea8278f87
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
@@ -0,0 +1,128 @@
+== Introduction ==
+
+Hardware modules that control pin multiplexing or configuration parameters
+such as pull-up/down, tri-state, drive-strength etc are designated as pin
+controllers. Each pin controller must be represented as a node in device tree,
+just like any other hardware module.
+
+Hardware modules whose signals are affected by pin configuration are
+designated client devices. Again, each client device must be represented as a
+node in device tree, just like any other hardware module.
+
+For a client device to operate correctly, certain pin controllers must
+set up certain specific pin configurations. Some client devices need a
+single static pin configuration, e.g. set up during initialization. Others
+need to reconfigure pins at run-time, for example to tri-state pins when the
+device is inactive. Hence, each client device can define a set of named
+states. The number and names of those states is defined by the client device's
+own binding.
+
+The common pinctrl bindings defined in this file provide an infrastructure
+for client device device tree nodes to map those state names to the pin
+configuration used by those states.
+
+Note that pin controllers themselves may also be client devices of themselves.
+For example, a pin controller may set up its own "active" state when the
+driver loads. This would allow representing a board's static pin configuration
+in a single place, rather than splitting it across multiple client device
+nodes. The decision to do this or not somewhat rests with the author of
+individual board device tree files, and any requirements imposed by the
+bindings for the individual client devices in use by that board, i.e. whether
+they require certain specific named states for dynamic pin configuration.
+
+== Pinctrl client devices ==
+
+For each client device individually, every pin state is assigned an integer
+ID. These numbers start at 0, and are contiguous. For each state ID, a unique
+property exists to define the pin configuration. Each state may also be
+assigned a name. When names are used, another property exists to map from
+those names to the integer IDs.
+
+Each client device's own binding determines the set of states the must be
+defined in its device tree node, and whether to define the set of state
+IDs that must be provided, or whether to define the set of state names that
+must be provided.
+
+Required properties:
+pinctrl-0:      List of phandles, each pointing at a pin configuration
+                node. These referenced pin configuration nodes must be child
+                nodes of the pin controller that they configure. Multiple
+                entries may exist in this list so that multiple pin
+                controllers may be configured, or so that a state may be built
+                from multiple nodes for a single pin controller, each
+                contributing part of the overall configuration. See the next
+                section of this document for details of the format of these
+                pin configuration nodes.
+
+                In some cases, it may be useful to define a state, but for it
+                to be empty. This may be required when a common IP block is
+                used in an SoC either without a pin controller, or where the
+                pin controller does not affect the HW module in question. If
+                the binding for that IP block requires certain pin states to
+                exist, they must still be defined, but may be left empty.
+
+Optional properties:
+pinctrl-1:      List of phandles, each pointing at a pin configuration
+                node within a pin controller.
+...
+pinctrl-n:      List of phandles, each pointing at a pin configuration
+                node within a pin controller.
+pinctrl-names:  The list of names to assign states. List entry 0 defines the
+                name for integer state ID 0, list entry 1 for state ID 1, and
+                so on.
+
+For example:
+
+        /* For a client device requiring named states */
+        device {
+                pinctrl-names = "active", "idle";
+                pinctrl-0 = <&state_0_node_a>;
+                pinctrl-1 = <&state_1_node_a &state_1_node_b>;
+        };
+
+        /* For the same device if using state IDs */
+        device {
+                pinctrl-0 = <&state_0_node_a>;
+                pinctrl-1 = <&state_1_node_a &state_1_node_b>;
+        };
+
+        /*
+         * For an IP block whose binding supports pin configuration,
+         * but in use on an SoC that doesn't have any pin control hardware
+         */
+        device {
+                pinctrl-names = "active", "idle";
+                pinctrl-0 = <>;
+                pinctrl-1 = <>;
+        };
+
+== Pin controller devices ==
+
+Pin controller devices should contain the pin configuration nodes that client
+devices reference.
+
+For example:
+
+        pincontroller {
+                ... /* Standard DT properties for the device itself elided */
+
+                state_0_node_a {
+                        ...
+                };
+                state_1_node_a {
+                        ...
+                };
+                state_1_node_b {
+                        ...
+                };
+        }
+
+The contents of each of those pin configuration child nodes is defined
+entirely by the binding for the individual pin controller device. There
+exists no common standard for this content.
+
+The pin configuration nodes need not be direct children of the pin controller
+device; they may be grandchildren, for example. Whether this is legal, and
+whether there is any interaction between the child and intermediate parent
+nodes, is again defined entirely by the binding for the individual pin
+controller device.
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt
new file mode 100644
index 000000000000..3664d37e6799
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt
@@ -0,0 +1,108 @@
+ST Microelectronics, SPEAr pinmux controller
+
+Required properties:
+- compatible    : "st,spear300-pinmux"
+                : "st,spear310-pinmux"
+                : "st,spear320-pinmux"
+- reg           : Address range of the pinctrl registers
+- st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
+        - Its values for SPEAr300:
+                - NAND_MODE             : <0>
+                - NOR_MODE              : <1>
+                - PHOTO_FRAME_MODE      : <2>
+                - LEND_IP_PHONE_MODE    : <3>
+                - HEND_IP_PHONE_MODE    : <4>
+                - LEND_WIFI_PHONE_MODE  : <5>
+                - HEND_WIFI_PHONE_MODE  : <6>
+                - ATA_PABX_WI2S_MODE    : <7>
+                - ATA_PABX_I2S_MODE     : <8>
+                - CAML_LCDW_MODE        : <9>
+                - CAMU_LCD_MODE         : <10>
+                - CAMU_WLCD_MODE        : <11>
+                - CAML_LCD_MODE         : <12>
+        - Its values for SPEAr320:
+                - AUTO_NET_SMII_MODE    : <0>
+                - AUTO_NET_MII_MODE     : <1>
+                - AUTO_EXP_MODE         : <2>
+                - SMALL_PRINTERS_MODE   : <3>
+                - EXTENDED_MODE         : <4>
+
+Please refer to pinctrl-bindings.txt in this directory for details of the common
+pinctrl bindings used by client devices.
+
+SPEAr's pinmux nodes act as a container for an abitrary number of subnodes. Each
+of these subnodes represents muxing for a pin, a group, or a list of pins or
+groups.
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Required subnode-properties:
+- st,pins : An array of strings. Each string contains the name of a pin or
+  group.
+- st,function: A string containing the name of the function to mux to the pin or
+  group. See the SPEAr's TRM to determine which are valid for each pin or group.
+
+  Valid values for group and function names can be found from looking at the
+  group and function arrays in driver files:
+  drivers/pinctrl/spear/pinctrl-spear3*0.c
+
+Valid values for group names are:
+For All SPEAr3xx machines:
+        "firda_grp", "i2c0_grp", "ssp_cs_grp", "ssp0_grp", "mii0_grp",
+        "gpio0_pin0_grp", "gpio0_pin1_grp", "gpio0_pin2_grp", "gpio0_pin3_grp",
+        "gpio0_pin4_grp", "gpio0_pin5_grp", "uart0_ext_grp", "uart0_grp",
+        "timer_0_1_grp", timer_0_1_pins, "timer_2_3_grp"
+
+For SPEAr300 machines:
+        "fsmc_2chips_grp", "fsmc_4chips_grp", "clcd_lcdmode_grp",
+        "clcd_pfmode_grp", "tdm_grp", "i2c_clk_grp_grp", "caml_grp", "camu_grp",
+        "dac_grp", "i2s_grp", "sdhci_4bit_grp", "sdhci_8bit_grp",
+        "gpio1_0_to_3_grp", "gpio1_4_to_7_grp"
+
+For SPEAr310 machines:
+        "emi_cs_0_to_5_grp", "uart1_grp", "uart2_grp", "uart3_grp", "uart4_grp",
+        "uart5_grp", "fsmc_grp", "rs485_0_grp", "rs485_1_grp", "tdm_grp"
+
+For SPEAr320 machines:
+        "clcd_grp", "emi_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "spp_grp",
+        "sdhci_led_grp", "sdhci_cd_12_grp", "sdhci_cd_51_grp", "i2s_grp",
+        "uart1_grp", "uart1_modem_2_to_7_grp", "uart1_modem_31_to_36_grp",
+        "uart1_modem_34_to_45_grp", "uart1_modem_80_to_85_grp", "uart2_grp",
+        "uart3_8_9_grp", "uart3_15_16_grp", "uart3_41_42_grp",
+        "uart3_52_53_grp", "uart3_73_74_grp", "uart3_94_95_grp",
+        "uart3_98_99_grp", "uart4_6_7_grp", "uart4_13_14_grp",
+        "uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp",
+        "uart4_100_101_grp", "uart5_4_5_grp", "uart5_37_38_grp",
+        "uart5_69_70_grp", "uart5_90_91_grp", "uart6_2_3_grp",
+        "uart6_88_89_grp", "rs485_grp", "touchscreen_grp", "can0_grp",
+        "can1_grp", "pwm0_1_pin_8_9_grp", "pwm0_1_pin_14_15_grp",
+        "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp", "pwm0_1_pin_42_43_grp",
+        "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp", "pwm2_pin_7_grp",
+        "pwm2_pin_13_grp", "pwm2_pin_29_grp", "pwm2_pin_34_grp",
+        "pwm2_pin_41_grp", "pwm2_pin_58_grp", "pwm2_pin_87_grp",
+        "pwm3_pin_6_grp", "pwm3_pin_12_grp", "pwm3_pin_28_grp",
+        "pwm3_pin_40_grp", "pwm3_pin_57_grp", "pwm3_pin_86_grp",
+        "ssp1_17_20_grp", "ssp1_36_39_grp", "ssp1_48_51_grp", "ssp1_65_68_grp",
+        "ssp1_94_97_grp", "ssp2_13_16_grp", "ssp2_32_35_grp", "ssp2_44_47_grp",
+        "ssp2_61_64_grp", "ssp2_90_93_grp", "mii2_grp", "smii0_1_grp",
+        "rmii0_1_grp", "i2c1_8_9_grp", "i2c1_98_99_grp", "i2c2_0_1_grp",
+        "i2c2_2_3_grp", "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp"
+
+Valid values for function names are:
+For All SPEAr3xx machines:
+        "firda", "i2c0", "ssp_cs", "ssp0", "mii0", "gpio0", "uart0_ext",
+        "uart0", "timer_0_1", "timer_2_3"
+
+For SPEAr300 machines:
+        "fsmc", "clcd", "tdm", "i2c1", "cam", "dac", "i2s", "sdhci", "gpio1"
+
+For SPEAr310 machines:
+        "emi", "uart1", "uart2", "uart3", "uart4", "uart5", "fsmc", "rs485_0",
+        "rs485_1", "tdm"
+
+For SPEAr320 machines:
+        "clcd", "emi", "fsmc", "spp", "sdhci", "i2s", "uart1", "uart1_modem",
+        "uart2", "uart3", "uart4", "uart5", "uart6", "rs485", "touchscreen",
+        "can0", "can1", "pwm0_1", "pwm2", "pwm3", "ssp1", "ssp2", "mii2",
+        "mii0_1", "i2c1", "i2c2"
diff --git a/Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt b/Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt
deleted file mode 100644
index 36f82dbdd14d..000000000000
--- a/Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-NVIDIA Tegra 2 pinmux controller
-
-Required properties:
-- compatible : "nvidia,tegra20-pinmux"
-
diff --git a/Documentation/driver-model/devres.txt b/Documentation/driver-model/devres.txt
index 2a596a4fc23e..ef4fa7b423d2 100644
--- a/Documentation/driver-model/devres.txt
+++ b/Documentation/driver-model/devres.txt
@@ -276,3 +276,7 @@ REGULATOR
   devm_regulator_get()
   devm_regulator_put()
   devm_regulator_bulk_get()
+
+PINCTRL
+  devm_pinctrl_get()
+  devm_pinctrl_put()
diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt
index d97bccf46147..e40f4b4e1977 100644
--- a/Documentation/pinctrl.txt
+++ b/Documentation/pinctrl.txt
@@ -152,11 +152,9 @@ static const struct foo_group foo_groups[] = {
 };
 
 
-static int foo_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
+static int foo_get_groups_count(struct pinctrl_dev *pctldev)
 {
-        if (selector >= ARRAY_SIZE(foo_groups))
-                return -EINVAL;
-        return 0;
+        return ARRAY_SIZE(foo_groups);
 }
 
 static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
@@ -175,7 +173,7 @@ static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
 }
 
 static struct pinctrl_ops foo_pctrl_ops = {
-        .list_groups = foo_list_groups,
+        .get_groups_count = foo_get_groups_count,
         .get_group_name = foo_get_group_name,
         .get_group_pins = foo_get_group_pins,
 };
@@ -186,13 +184,12 @@ static struct pinctrl_desc foo_desc = {
        .pctlops = &foo_pctrl_ops,
 };
 
-The pin control subsystem will call the .list_groups() function repeatedly
-beginning on 0 until it returns non-zero to determine legal selectors, then
-it will call the other functions to retrieve the name and pins of the group.
-Maintaining the data structure of the groups is up to the driver, this is
-just a simple example - in practice you may need more entries in your group
-structure, for example specific register ranges associated with each group
-and so on.
+The pin control subsystem will call the .get_groups_count() function to
+determine total number of legal selectors, then it will call the other functions
+to retrieve the name and pins of the group. Maintaining the data structure of
+the groups is up to the driver, this is just a simple example - in practice you
+may need more entries in your group structure, for example specific register
+ranges associated with each group and so on.
 
 
 Pin configuration
@@ -606,11 +603,9 @@ static const struct foo_group foo_groups[] = {
 };
 
 
-static int foo_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
+static int foo_get_groups_count(struct pinctrl_dev *pctldev)
 {
-        if (selector >= ARRAY_SIZE(foo_groups))
-                return -EINVAL;
-        return 0;
+        return ARRAY_SIZE(foo_groups);
 }
 
 static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
@@ -629,7 +624,7 @@ static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
 }
 
 static struct pinctrl_ops foo_pctrl_ops = {
-        .list_groups = foo_list_groups,
+        .get_groups_count = foo_get_groups_count,
         .get_group_name = foo_get_group_name,
         .get_group_pins = foo_get_group_pins,
 };
@@ -640,7 +635,7 @@ struct foo_pmx_func {
         const unsigned num_groups;
 };
 
-static const char * const spi0_groups[] = { "spi0_1_grp" };
+static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" };
 static const char * const i2c0_groups[] = { "i2c0_grp" };
 static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp",
                                         "mmc0_3_grp" };
@@ -663,11 +658,9 @@ static const struct foo_pmx_func foo_functions[] = {
         },
 };
 
-int foo_list_funcs(struct pinctrl_dev *pctldev, unsigned selector)
+int foo_get_functions_count(struct pinctrl_dev *pctldev)
 {
-        if (selector >= ARRAY_SIZE(foo_functions))
-                return -EINVAL;
-        return 0;
+        return ARRAY_SIZE(foo_functions);
 }
 
 const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
@@ -703,7 +696,7 @@ void foo_disable(struct pinctrl_dev *pctldev, unsigned selector,
 }
 
 struct pinmux_ops foo_pmxops = {
-        .list_functions = foo_list_funcs,
+        .get_functions_count = foo_get_functions_count,
         .get_function_name = foo_get_fname,
         .get_function_groups = foo_get_groups,
         .enable = foo_enable,
@@ -786,7 +779,7 @@ and spi on the second function mapping:
 
 #include <linux/pinctrl/machine.h>
 
-static const struct pinctrl_map __initdata mapping[] = {
+static const struct pinctrl_map mapping[] __initconst = {
         {
                 .dev_name = "foo-spi.0",
                 .name = PINCTRL_STATE_DEFAULT,
@@ -952,13 +945,13 @@ case), we define a mapping like this:
 The result of grabbing this mapping from the device with something like
 this (see next paragraph):
 
-        p = pinctrl_get(dev);
+        p = devm_pinctrl_get(dev);
         s = pinctrl_lookup_state(p, "8bit");
         ret = pinctrl_select_state(p, s);
 
 or more simply:
 
-        p = pinctrl_get_select(dev, "8bit");
+        p = devm_pinctrl_get_select(dev, "8bit");
 
 Will be that you activate all the three bottom records in the mapping at
 once. Since they share the same name, pin controller device, function and
@@ -992,7 +985,7 @@ foo_probe()
         /* Allocate a state holder named "foo" etc */
         struct foo_state *foo = ...;
 
-        foo->p = pinctrl_get(&device);
+        foo->p = devm_pinctrl_get(&device);
         if (IS_ERR(foo->p)) {
                 /* FIXME: clean up "foo" here */
                 return PTR_ERR(foo->p);
@@ -1000,24 +993,17 @@ foo_probe()
 
         foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT);
         if (IS_ERR(foo->s)) {
-                pinctrl_put(foo->p);
                 /* FIXME: clean up "foo" here */
                 return PTR_ERR(s);
         }
 
         ret = pinctrl_select_state(foo->s);
         if (ret < 0) {
-                pinctrl_put(foo->p);
                 /* FIXME: clean up "foo" here */
                 return ret;
         }
 }
 
-foo_remove()
-{
-        pinctrl_put(state->p);
-}
-
 This get/lookup/select/put sequence can just as well be handled by bus drivers
 if you don't want each and every driver to handle it and you know the
 arrangement on your bus.
@@ -1029,6 +1015,11 @@ The semantics of the pinctrl APIs are:
   kernel memory to hold the pinmux state. All mapping table parsing or similar
   slow operations take place within this API.
 
+- devm_pinctrl_get() is a variant of pinctrl_get() that causes pinctrl_put()
+  to be called automatically on the retrieved pointer when the associated
+  device is removed. It is recommended to use this function over plain
+  pinctrl_get().
+
 - pinctrl_lookup_state() is called in process context to obtain a handle to a
   specific state for a the client device. This operation may be slow too.
 
@@ -1041,14 +1032,30 @@ The semantics of the pinctrl APIs are:
 
 - pinctrl_put() frees all information associated with a pinctrl handle.
 
+- devm_pinctrl_put() is a variant of pinctrl_put() that may be used to
+  explicitly destroy a pinctrl object returned by devm_pinctrl_get().
+  However, use of this function will be rare, due to the automatic cleanup
+  that will occur even without calling it.
+
+  pinctrl_get() must be paired with a plain pinctrl_put().
+  pinctrl_get() may not be paired with devm_pinctrl_put().
+  devm_pinctrl_get() can optionally be paired with devm_pinctrl_put().
+  devm_pinctrl_get() may not be paired with plain pinctrl_put().
+
 Usually the pin control core handled the get/put pair and call out to the
 device drivers bookkeeping operations, like checking available functions and
 the associated pins, whereas the enable/disable pass on to the pin controller
 driver which takes care of activating and/or deactivating the mux setting by
 quickly poking some registers.
 
-The pins are allocated for your device when you issue the pinctrl_get() call,
-after this you should be able to see this in the debugfs listing of all pins.
+The pins are allocated for your device when you issue the devm_pinctrl_get()
+call, after this you should be able to see this in the debugfs listing of all
+pins.
+
+NOTE: the pinctrl system will return -EPROBE_DEFER if it cannot find the
+requested pinctrl handles, for example if the pinctrl driver has not yet
+registered. Thus make sure that the error path in your driver gracefully
+cleans up and is ready to retry the probing later in the startup process.
 
 
 System pin control hogging
@@ -1094,13 +1101,13 @@ it, disables and releases it, and muxes it in on the pins defined by group B:
 
 #include <linux/pinctrl/consumer.h>
 
-foo_switch()
-{
-        struct pinctrl *p;
-        struct pinctrl_state *s1, *s2;
+struct pinctrl *p;
+struct pinctrl_state *s1, *s2;
 
+foo_probe()
+{
         /* Setup */
-        p = pinctrl_get(&device);
+        p = devm_pinctrl_get(&device);
         if (IS_ERR(p))
                 ...
 
@@ -1111,7 +1118,10 @@ foo_switch()
         s2 = pinctrl_lookup_state(foo->p, "pos-B");
         if (IS_ERR(s2))
                 ...
+}
 
+foo_switch()
+{
         /* Enable on position A */
         ret = pinctrl_select_state(s1);
         if (ret < 0)
@@ -1125,8 +1135,6 @@ foo_switch()
             ...
 
         ...
-
-        pinctrl_put(p);
 }
 
 The above has to be done from process context.
diff --git a/MAINTAINERS b/MAINTAINERS
index bb76fc42fc42..35d2339dbc0b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5235,6 +5235,14 @@ M:	Linus Walleij <linus.walleij@linaro.org>
 S:      Maintained
 F:      drivers/pinctrl/
 
+PIN CONTROLLER - ST SPEAR
+M:      Viresh Kumar <viresh.kumar@st.com>
+L:      spear-devel@list.st.com
+L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+W:      http://www.st.com/spear
+S:      Maintained
+F:      driver/pinctrl/spear/
+
 PKTCDVD DRIVER
 M:      Peter Osterlund <petero2@telia.com>
 S:      Maintained
@@ -6331,21 +6339,6 @@ F:	arch/arm/mach-spear*/clock.c
 F:      arch/arm/plat-spear/clock.c
 F:      arch/arm/plat-spear/include/plat/clock.h
 
-SPEAR PAD MULTIPLEXING SUPPORT
-M:      Viresh Kumar <viresh.kumar@st.com>
-L:      spear-devel@list.st.com
-L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-W:      http://www.st.com/spear
-S:      Maintained
-F:      arch/arm/plat-spear/include/plat/padmux.h
-F:      arch/arm/plat-spear/padmux.c
-F:      arch/arm/mach-spear*/spear*xx.c
-F:      arch/arm/mach-spear*/include/mach/generic.h
-F:      arch/arm/mach-spear3xx/spear3*0.c
-F:      arch/arm/mach-spear3xx/spear3*0_evb.c
-F:      arch/arm/mach-spear6xx/spear600.c
-F:      arch/arm/mach-spear6xx/spear600_evb.c
-
 SPI SUBSYSTEM
 M:      Grant Likely <grant.likely@secretlab.ca>
 L:      spi-devel-general@lists.sourceforge.net
diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts
new file mode 100644
index 000000000000..402ca0d55011
--- /dev/null
+++ b/arch/arm/boot/dts/spear300-evb.dts
@@ -0,0 +1,221 @@
+/*
+ * DTS file for SPEAr300 Evaluation Baord
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear300.dtsi"
+
+/ {
+        model = "ST SPEAr300 Evaluation Board";
+        compatible = "st,spear300-evb", "st,spear300";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        memory {
+                reg = <0 0x40000000>;
+        };
+
+        ahb {
+                pinmux@99000000 {
+                        st,pinmux-mode = <2>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&state_default>;
+
+                        state_default: pinmux {
+                                i2c0 {
+                                        st,pins = "i2c0_grp";
+                                        st,function = "i2c0";
+                                };
+                                ssp0 {
+                                        st,pins = "ssp0_grp";
+                                        st,function = "ssp0";
+                                };
+                                mii0 {
+                                        st,pins = "mii0_grp";
+                                        st,function = "mii0";
+                                };
+                                uart0 {
+                                        st,pins = "uart0_grp";
+                                        st,function = "uart0";
+                                };
+                                clcd {
+                                        st,pins = "clcd_pfmode_grp";
+                                        st,function = "clcd";
+                                };
+                                sdhci {
+                                        st,pins = "sdhci_4bit_grp";
+                                        st,function = "sdhci";
+                                };
+                                gpio1 {
+                                        st,pins = "gpio1_4_to_7_grp",
+                                                "gpio1_0_to_3_grp";
+                                        st,function = "gpio1";
+                                };
+                        };
+                };
+
+                clcd@60000000 {
+                        status = "okay";
+                };
+
+                dma@fc400000 {
+                        status = "okay";
+                };
+
+                fsmc: flash@94000000 {
+                        status = "okay";
+                };
+
+                gmac: eth@e0800000 {
+                        status = "okay";
+                };
+
+                sdhci@70000000 {
+                        int-gpio = <&gpio1 0 0>;
+                        power-gpio = <&gpio1 2 1>;
+                        status = "okay";
+                };
+
+                smi: flash@fc000000 {
+                        status = "okay";
+                };
+
+                spi0: spi@d0100000 {
+                        status = "okay";
+                };
+
+                ehci@e1800000 {
+                        status = "okay";
+                };
+
+                ohci@e1900000 {
+                        status = "okay";
+                };
+
+                ohci@e2100000 {
+                        status = "okay";
+                };
+
+                apb {
+                        gpio0: gpio@fc980000 {
+                               status = "okay";
+                        };
+
+                        gpio1: gpio@a9000000 {
+                               status = "okay";
+                        };
+
+                        i2c0: i2c@d0180000 {
+                               status = "okay";
+                        };
+
+                        kbd@a0000000 {
+                                linux,keymap = < 0x00010000
+                                                 0x00020100
+                                                 0x00030200
+                                                 0x00040300
+                                                 0x00050400
+                                                 0x00060500
+                                                 0x00070600
+                                                 0x00080700
+                                                 0x00090800
+                                                 0x000a0001
+                                                 0x000c0101
+                                                 0x000d0201
+                                                 0x000e0301
+                                                 0x000f0401
+                                                 0x00100501
+                                                 0x00110601
+                                                 0x00120701
+                                                 0x00130801
+                                                 0x00140002
+                                                 0x00150102
+                                                 0x00160202
+                                                 0x00170302
+                                                 0x00180402
+                                                 0x00190502
+                                                 0x001a0602
+                                                 0x001b0702
+                                                 0x001c0802
+                                                 0x001d0003
+                                                 0x001e0103
+                                                 0x001f0203
+                                                 0x00200303
+                                                 0x00210403
+                                                 0x00220503
+                                                 0x00230603
+                                                 0x00240703
+                                                 0x00250803
+                                                 0x00260004
+                                                 0x00270104
+                                                 0x00280204
+                                                 0x00290304
+                                                 0x002a0404
+                                                 0x002b0504
+                                                 0x002c0604
+                                                 0x002d0704
+                                                 0x002e0804
+                                                 0x002f0005
+                                                 0x00300105
+                                                 0x00310205
+                                                 0x00320305
+                                                 0x00330405
+                                                 0x00340505
+                                                 0x00350605
+                                                 0x00360705
+                                                 0x00370805
+                                                 0x00380006
+                                                 0x00390106
+                                                 0x003a0206
+                                                 0x003b0306
+                                                 0x003c0406
+                                                 0x003d0506
+                                                 0x003e0606
+                                                 0x003f0706
+                                                 0x00400806
+                                                 0x00410007
+                                                 0x00420107
+                                                 0x00430207
+                                                 0x00440307
+                                                 0x00450407
+                                                 0x00460507
+                                                 0x00470607
+                                                 0x00480707
+                                                 0x00490807
+                                                 0x004a0008
+                                                 0x004b0108
+                                                 0x004c0208
+                                                 0x004d0308
+                                                 0x004e0408
+                                                 0x004f0508
+                                                 0x00500608
+                                                 0x00510708
+                                                 0x00520808 >;
+                               autorepeat;
+                               st,mode = <0>;
+                               status = "okay";
+                        };
+
+                        rtc@fc900000 {
+                               status = "okay";
+                        };
+
+                        serial@d0000000 {
+                               status = "okay";
+                        };
+
+                        wdt@fc880000 {
+                               status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear300.dtsi b/arch/arm/boot/dts/spear300.dtsi
new file mode 100644
index 000000000000..01c5e358fdb2
--- /dev/null
+++ b/arch/arm/boot/dts/spear300.dtsi
@@ -0,0 +1,77 @@
+/*
+ * DTS file for SPEAr300 SoC
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "spear3xx.dtsi"
+
+/ {
+        ahb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges = <0x60000000 0x60000000 0x50000000
+                          0xd0000000 0xd0000000 0x30000000>;
+
+                pinmux@99000000 {
+                        compatible = "st,spear300-pinmux";
+                        reg = <0x99000000 0x1000>;
+                };
+
+                clcd@60000000 {
+                        compatible = "arm,clcd-pl110", "arm,primecell";
+                        reg = <0x60000000 0x1000>;
+                        interrupts = <30>;
+                        status = "disabled";
+                };
+
+                fsmc: flash@94000000 {
+                        compatible = "st,spear600-fsmc-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x94000000 0x1000        /* FSMC Register */
+                               0x80000000 0x0010>;      /* NAND Base */
+                        reg-names = "fsmc_regs", "nand_data";
+                        st,ale-off = <0x20000>;
+                        st,cle-off = <0x10000>;
+                        status = "disabled";
+                };
+
+                sdhci@70000000 {
+                        compatible = "st,sdhci-spear";
+                        reg = <0x70000000 0x100>;
+                        interrupts = <1>;
+                        status = "disabled";
+                };
+
+                apb {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        ranges = <0xa0000000 0xa0000000 0x10000000
+                                  0xd0000000 0xd0000000 0x30000000>;
+
+                        gpio1: gpio@a9000000 {
+                                #gpio-cells = <2>;
+                                compatible = "arm,pl061", "arm,primecell";
+                                gpio-controller;
+                                reg = <0xa9000000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        kbd@a0000000 {
+                                compatible = "st,spear300-kbd";
+                                reg = <0xa0000000 0x1000>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts
new file mode 100644
index 000000000000..6d95317100ad
--- /dev/null
+++ b/arch/arm/boot/dts/spear310-evb.dts
@@ -0,0 +1,172 @@
+/*
+ * DTS file for SPEAr310 Evaluation Baord
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear310.dtsi"
+
+/ {
+        model = "ST SPEAr310 Evaluation Board";
+        compatible = "st,spear310-evb", "st,spear310";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        memory {
+                reg = <0 0x40000000>;
+        };
+
+        ahb {
+                pinmux@b4000000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&state_default>;
+
+                        state_default: pinmux {
+                                gpio0 {
+                                        st,pins = "gpio0_pin0_grp",
+                                                "gpio0_pin1_grp",
+                                                "gpio0_pin2_grp",
+                                                "gpio0_pin3_grp",
+                                                "gpio0_pin4_grp",
+                                                "gpio0_pin5_grp";
+                                        st,function = "gpio0";
+                                };
+                                i2c0 {
+                                        st,pins = "i2c0_grp";
+                                        st,function = "i2c0";
+                                };
+                                mii0 {
+                                        st,pins = "mii0_grp";
+                                        st,function = "mii0";
+                                };
+                                ssp0 {
+                                        st,pins = "ssp0_grp";
+                                        st,function = "ssp0";
+                                };
+                                uart0 {
+                                        st,pins = "uart0_grp";
+                                        st,function = "uart0";
+                                };
+                                emi {
+                                        st,pins = "emi_cs_0_to_5_grp";
+                                        st,function = "emi";
+                                };
+                                fsmc {
+                                        st,pins = "fsmc_grp";
+                                        st,function = "fsmc";
+                                };
+                                uart1 {
+                                        st,pins = "uart1_grp";
+                                        st,function = "uart1";
+                                };
+                                uart2 {
+                                        st,pins = "uart2_grp";
+                                        st,function = "uart2";
+                                };
+                                uart3 {
+                                        st,pins = "uart3_grp";
+                                        st,function = "uart3";
+                                };
+                                uart4 {
+                                        st,pins = "uart4_grp";
+                                        st,function = "uart4";
+                                };
+                                uart5 {
+                                        st,pins = "uart5_grp";
+                                        st,function = "uart5";
+                                };
+                        };
+                };
+
+                dma@fc400000 {
+                        status = "okay";
+                };
+
+                fsmc: flash@44000000 {
+                        status = "okay";
+                };
+
+                gmac: eth@e0800000 {
+                        status = "okay";
+                };
+
+                smi: flash@fc000000 {
+                        status = "okay";
+                        clock-rate=<50000000>;
+
+                        flash@f8000000 {
+                                label = "m25p64";
+                                reg = <0xf8000000 0x800000>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                st,smi-fast-mode;
+                        };
+                };
+
+                spi0: spi@d0100000 {
+                        status = "okay";
+                };
+
+                ehci@e1800000 {
+                        status = "okay";
+                };
+
+                ohci@e1900000 {
+                        status = "okay";
+                };
+
+                ohci@e2100000 {
+                        status = "okay";
+                };
+
+                apb {
+                        gpio0: gpio@fc980000 {
+                               status = "okay";
+                        };
+
+                        i2c0: i2c@d0180000 {
+                               status = "okay";
+                        };
+
+                        rtc@fc900000 {
+                               status = "okay";
+                        };
+
+                        serial@d0000000 {
+                               status = "okay";
+                        };
+
+                        serial@b2000000 {
+                               status = "okay";
+                        };
+
+                        serial@b2080000 {
+                               status = "okay";
+                        };
+
+                        serial@b2100000 {
+                               status = "okay";
+                        };
+
+                        serial@b2180000 {
+                               status = "okay";
+                        };
+
+                        serial@b2200000 {
+                               status = "okay";
+                        };
+
+                        wdt@fc880000 {
+                               status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi
new file mode 100644
index 000000000000..e47081c494d9
--- /dev/null
+++ b/arch/arm/boot/dts/spear310.dtsi
@@ -0,0 +1,80 @@
+/*
+ * DTS file for SPEAr310 SoC
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "spear3xx.dtsi"
+
+/ {
+        ahb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges = <0x40000000 0x40000000 0x10000000
+                          0xb0000000 0xb0000000 0x10000000
+                          0xd0000000 0xd0000000 0x30000000>;
+
+                pinmux@b4000000 {
+                        compatible = "st,spear310-pinmux";
+                        reg = <0xb4000000 0x1000>;
+                };
+
+                fsmc: flash@44000000 {
+                        compatible = "st,spear600-fsmc-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x44000000 0x1000        /* FSMC Register */
+                               0x40000000 0x0010>;      /* NAND Base */
+                        reg-names = "fsmc_regs", "nand_data";
+                        st,ale-off = <0x10000>;
+                        st,cle-off = <0x20000>;
+                        status = "disabled";
+                };
+
+                apb {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        ranges = <0xb0000000 0xb0000000 0x10000000
+                                  0xd0000000 0xd0000000 0x30000000>;
+
+                        serial@b2000000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xb2000000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        serial@b2080000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xb2080000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        serial@b2100000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xb2100000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        serial@b2180000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xb2180000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        serial@b2200000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xb2200000 0x1000>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
new file mode 100644
index 000000000000..0c6463b71a37
--- /dev/null
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -0,0 +1,173 @@
+/*
+ * DTS file for SPEAr320 Evaluation Baord
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear320.dtsi"
+
+/ {
+        model = "ST SPEAr300 Evaluation Board";
+        compatible = "st,spear300-evb", "st,spear300";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        memory {
+                reg = <0 0x40000000>;
+        };
+
+        ahb {
+                pinmux@b3000000 {
+                        st,pinmux-mode = <3>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&state_default>;
+
+                        state_default: pinmux {
+                                i2c0 {
+                                        st,pins = "i2c0_grp";
+                                        st,function = "i2c0";
+                                };
+                                mii0 {
+                                        st,pins = "mii0_grp";
+                                        st,function = "mii0";
+                                };
+                                ssp0 {
+                                        st,pins = "ssp0_grp";
+                                        st,function = "ssp0";
+                                };
+                                uart0 {
+                                        st,pins = "uart0_grp";
+                                        st,function = "uart0";
+                                };
+                                sdhci {
+                                        st,pins = "sdhci_cd_51_grp";
+                                        st,function = "sdhci";
+                                };
+                                i2s {
+                                        st,pins = "i2s_grp";
+                                        st,function = "i2s";
+                                };
+                                uart1 {
+                                        st,pins = "uart1_grp";
+                                        st,function = "uart1";
+                                };
+                                uart2 {
+                                        st,pins = "uart2_grp";
+                                        st,function = "uart2";
+                                };
+                                can0 {
+                                        st,pins = "can0_grp";
+                                        st,function = "can0";
+                                };
+                                can1 {
+                                        st,pins = "can1_grp";
+                                        st,function = "can1";
+                                };
+                                mii2 {
+                                        st,pins = "mii2_grp";
+                                        st,function = "mii2";
+                                };
+                                pwm0_1 {
+                                        st,pins = "pwm0_1_pin_14_15_grp";
+                                        st,function = "pwm0_1";
+                                };
+                                pwm2 {
+                                        st,pins = "pwm2_pin_13_grp";
+                                        st,function = "pwm2";
+                                };
+                        };
+                };
+
+                clcd@90000000 {
+                        status = "okay";
+                };
+
+                dma@fc400000 {
+                        status = "okay";
+                };
+
+                fsmc: flash@4c000000 {
+                        status = "okay";
+                };
+
+                gmac: eth@e0800000 {
+                        status = "okay";
+                };
+
+                sdhci@70000000 {
+                        power-gpio = <&gpio0 2 1>;
+                        power_always_enb;
+                        status = "okay";
+                };
+
+                smi: flash@fc000000 {
+                        status = "okay";
+                };
+
+                spi0: spi@d0100000 {
+                        status = "okay";
+                };
+
+                spi1: spi@a5000000 {
+                        status = "okay";
+                };
+
+                spi2: spi@a6000000 {
+                        status = "okay";
+                };
+
+                ehci@e1800000 {
+                        status = "okay";
+                };
+
+                ohci@e1900000 {
+                        status = "okay";
+                };
+
+                ohci@e2100000 {
+                        status = "okay";
+                };
+
+                apb {
+                        gpio0: gpio@fc980000 {
+                               status = "okay";
+                        };
+
+                        i2c0: i2c@d0180000 {
+                               status = "okay";
+                        };
+
+                        i2c1: i2c@a7000000 {
+                               status = "okay";
+                        };
+
+                        rtc@fc900000 {
+                               status = "okay";
+                        };
+
+                        serial@d0000000 {
+                               status = "okay";
+                        };
+
+                        serial@a3000000 {
+                               status = "okay";
+                        };
+
+                        serial@a4000000 {
+                               status = "okay";
+                        };
+
+                        wdt@fc880000 {
+                               status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi
new file mode 100644
index 000000000000..5372ca399b1f
--- /dev/null
+++ b/arch/arm/boot/dts/spear320.dtsi
@@ -0,0 +1,95 @@
+/*
+ * DTS file for SPEAr320 SoC
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "spear3xx.dtsi"
+
+/ {
+        ahb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges = <0x40000000 0x40000000 0x80000000
+                          0xd0000000 0xd0000000 0x30000000>;
+
+                pinmux@b3000000 {
+                        compatible = "st,spear320-pinmux";
+                        reg = <0xb3000000 0x1000>;
+                };
+
+                clcd@90000000 {
+                        compatible = "arm,clcd-pl110", "arm,primecell";
+                        reg = <0x90000000 0x1000>;
+                        interrupts = <33>;
+                        status = "disabled";
+                };
+
+                fsmc: flash@4c000000 {
+                        compatible = "st,spear600-fsmc-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x4c000000 0x1000        /* FSMC Register */
+                               0x50000000 0x0010>;      /* NAND Base */
+                        reg-names = "fsmc_regs", "nand_data";
+                        st,ale-off = <0x20000>;
+                        st,cle-off = <0x10000>;
+                        status = "disabled";
+                };
+
+                sdhci@70000000 {
+                        compatible = "st,sdhci-spear";
+                        reg = <0x70000000 0x100>;
+                        interrupts = <29>;
+                        status = "disabled";
+                };
+
+                spi1: spi@a5000000 {
+                        compatible = "arm,pl022", "arm,primecell";
+                        reg = <0xa5000000 0x1000>;
+                        status = "disabled";
+                };
+
+                spi2: spi@a6000000 {
+                        compatible = "arm,pl022", "arm,primecell";
+                        reg = <0xa6000000 0x1000>;
+                        status = "disabled";
+                };
+
+                apb {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        ranges = <0xa0000000 0xa0000000 0x10000000
+                                  0xd0000000 0xd0000000 0x30000000>;
+
+                        i2c1: i2c@a7000000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "snps,designware-i2c";
+                                reg = <0xa7000000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        serial@a3000000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xa3000000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        serial@a4000000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xa4000000 0x1000>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
new file mode 100644
index 000000000000..0ae7c8e86311
--- /dev/null
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -0,0 +1,144 @@
+/*
+ * DTS file for all SPEAr3xx SoCs
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        interrupt-parent = <&vic>;
+
+        cpus {
+                cpu@0 {
+                        compatible = "arm,arm926ejs";
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0 0x40000000>;
+        };
+
+        ahb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges = <0xd0000000 0xd0000000 0x30000000>;
+
+                vic: interrupt-controller@f1100000 {
+                        compatible = "arm,pl190-vic";
+                        interrupt-controller;
+                        reg = <0xf1100000 0x1000>;
+                        #interrupt-cells = <1>;
+                };
+
+                dma@fc400000 {
+                        compatible = "arm,pl080", "arm,primecell";
+                        reg = <0xfc400000 0x1000>;
+                        interrupt-parent = <&vic>;
+                        interrupts = <8>;
+                        status = "disabled";
+                };
+
+                gmac: eth@e0800000 {
+                        compatible = "st,spear600-gmac";
+                        reg = <0xe0800000 0x8000>;
+                        interrupts = <23 22>;
+                        interrupt-names = "macirq", "eth_wake_irq";
+                        status = "disabled";
+                };
+
+                smi: flash@fc000000 {
+                        compatible = "st,spear600-smi";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0xfc000000 0x1000>;
+                        interrupts = <9>;
+                        status = "disabled";
+                };
+
+                spi0: spi@d0100000 {
+                        compatible = "arm,pl022", "arm,primecell";
+                        reg = <0xd0100000 0x1000>;
+                        interrupts = <20>;
+                        status = "disabled";
+                };
+
+                ehci@e1800000 {
+                        compatible = "st,spear600-ehci", "usb-ehci";
+                        reg = <0xe1800000 0x1000>;
+                        interrupts = <26>;
+                        status = "disabled";
+                };
+
+                ohci@e1900000 {
+                        compatible = "st,spear600-ohci", "usb-ohci";
+                        reg = <0xe1900000 0x1000>;
+                        interrupts = <25>;
+                        status = "disabled";
+                };
+
+                ohci@e2100000 {
+                        compatible = "st,spear600-ohci", "usb-ohci";
+                        reg = <0xe2100000 0x1000>;
+                        interrupts = <27>;
+                        status = "disabled";
+                };
+
+                apb {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        ranges = <0xd0000000 0xd0000000 0x30000000>;
+
+                        gpio0: gpio@fc980000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xfc980000 0x1000>;
+                                interrupts = <11>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+
+                        i2c0: i2c@d0180000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "snps,designware-i2c";
+                                reg = <0xd0180000 0x1000>;
+                                interrupts = <21>;
+                                status = "disabled";
+                        };
+
+                        rtc@fc900000 {
+                                compatible = "st,spear-rtc";
+                                reg = <0xfc900000 0x1000>;
+                                interrupts = <10>;
+                                status = "disabled";
+                        };
+
+                        serial@d0000000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xd0000000 0x1000>;
+                                interrupts = <19>;
+                                status = "disabled";
+                        };
+
+                        wdt@fc880000 {
+                                compatible = "arm,sp805", "arm,primecell";
+                                reg = <0xfc880000 0x1000>;
+                                interrupts = <12>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
index 636292e18c90..790a7a8a5ccd 100644
--- a/arch/arm/boot/dts/spear600-evb.dts
+++ b/arch/arm/boot/dts/spear600-evb.dts
@@ -24,6 +24,10 @@
         };
 
         ahb {
+                dma@fc400000 {
+                        status = "okay";
+                };
+
                 gmac: ethernet@e0800000 {
                         phy-mode = "gmii";
                         status = "okay";
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index ebe0885a2b98..d777e3a6f178 100644
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -45,6 +45,14 @@
                         #interrupt-cells = <1>;
                 };
 
+                dma@fc400000 {
+                        compatible = "arm,pl080", "arm,primecell";
+                        reg = <0xfc400000 0x1000>;
+                        interrupt-parent = <&vic1>;
+                        interrupts = <10>;
+                        status = "disabled";
+                };
+
                 gmac: ethernet@e0800000 {
                         compatible = "st,spear600-gmac";
                         reg = <0xe0800000 0x8000>;
diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts
index ac3fb7558459..0a9f34a2c3aa 100644
--- a/arch/arm/boot/dts/tegra-cardhu.dts
+++ b/arch/arm/boot/dts/tegra-cardhu.dts
@@ -10,6 +10,50 @@
                 reg = < 0x80000000 0x40000000 >;
         };
 
+        pinmux@70000000 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&state_default>;
+
+                state_default: pinmux {
+                        sdmmc1_clk_pz0 {
+                                nvidia,pins = "sdmmc1_clk_pz0";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        sdmmc1_cmd_pz1 {
+                                nvidia,pins =   "sdmmc1_cmd_pz1",
+                                                "sdmmc1_dat0_py7",
+                                                "sdmmc1_dat1_py6",
+                                                "sdmmc1_dat2_py5",
+                                                "sdmmc1_dat3_py4";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <0>;
+                        };
+                        sdmmc4_clk_pcc4 {
+                                nvidia,pins =   "sdmmc4_clk_pcc4",
+                                                "sdmmc4_rst_n_pcc3";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        sdmmc4_dat0_paa0 {
+                                nvidia,pins =   "sdmmc4_dat0_paa0",
+                                                "sdmmc4_dat1_paa1",
+                                                "sdmmc4_dat2_paa2",
+                                                "sdmmc4_dat3_paa3",
+                                                "sdmmc4_dat4_paa4",
+                                                "sdmmc4_dat5_paa5",
+                                                "sdmmc4_dat6_paa6",
+                                                "sdmmc4_dat7_paa7";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <0>;
+                        };
+                };
+        };
+
         serial@70006000 {
                 clock-frequency = < 408000000 >;
         };
diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts
index 6e8447dc0202..1a0b1f182944 100644
--- a/arch/arm/boot/dts/tegra-harmony.dts
+++ b/arch/arm/boot/dts/tegra-harmony.dts
@@ -10,6 +10,230 @@
                 reg = < 0x00000000 0x40000000 >;
         };
 
+        pinmux@70000000 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&state_default>;
+
+                state_default: pinmux {
+                        ata {
+                                nvidia,pins = "ata";
+                                nvidia,function = "ide";
+                        };
+                        atb {
+                                nvidia,pins = "atb", "gma", "gme";
+                                nvidia,function = "sdio4";
+                        };
+                        atc {
+                                nvidia,pins = "atc";
+                                nvidia,function = "nand";
+                        };
+                        atd {
+                                nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
+                                        "spia", "spib", "spic";
+                                nvidia,function = "gmi";
+                        };
+                        cdev1 {
+                                nvidia,pins = "cdev1";
+                                nvidia,function = "plla_out";
+                        };
+                        cdev2 {
+                                nvidia,pins = "cdev2";
+                                nvidia,function = "pllp_out4";
+                        };
+                        crtp {
+                                nvidia,pins = "crtp";
+                                nvidia,function = "crt";
+                        };
+                        csus {
+                                nvidia,pins = "csus";
+                                nvidia,function = "vi_sensor_clk";
+                        };
+                        dap1 {
+                                nvidia,pins = "dap1";
+                                nvidia,function = "dap1";
+                        };
+                        dap2 {
+                                nvidia,pins = "dap2";
+                                nvidia,function = "dap2";
+                        };
+                        dap3 {
+                                nvidia,pins = "dap3";
+                                nvidia,function = "dap3";
+                        };
+                        dap4 {
+                                nvidia,pins = "dap4";
+                                nvidia,function = "dap4";
+                        };
+                        ddc {
+                                nvidia,pins = "ddc";
+                                nvidia,function = "i2c2";
+                        };
+                        dta {
+                                nvidia,pins = "dta", "dtd";
+                                nvidia,function = "sdio2";
+                        };
+                        dtb {
+                                nvidia,pins = "dtb", "dtc", "dte";
+                                nvidia,function = "rsvd1";
+                        };
+                        dtf {
+                                nvidia,pins = "dtf";
+                                nvidia,function = "i2c3";
+                        };
+                        gmc {
+                                nvidia,pins = "gmc";
+                                nvidia,function = "uartd";
+                        };
+                        gpu7 {
+                                nvidia,pins = "gpu7";
+                                nvidia,function = "rtck";
+                        };
+                        gpv {
+                                nvidia,pins = "gpv", "slxa", "slxk";
+                                nvidia,function = "pcie";
+                        };
+                        hdint {
+                                nvidia,pins = "hdint", "pta";
+                                nvidia,function = "hdmi";
+                        };
+                        i2cp {
+                                nvidia,pins = "i2cp";
+                                nvidia,function = "i2cp";
+                        };
+                        irrx {
+                                nvidia,pins = "irrx", "irtx";
+                                nvidia,function = "uarta";
+                        };
+                        kbca {
+                                nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+                                        "kbce", "kbcf";
+                                nvidia,function = "kbc";
+                        };
+                        lcsn {
+                                nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
+                                        "ld3", "ld4", "ld5", "ld6", "ld7",
+                                        "ld8", "ld9", "ld10", "ld11", "ld12",
+                                        "ld13", "ld14", "ld15", "ld16", "ld17",
+                                        "ldc", "ldi", "lhp0", "lhp1", "lhp2",
+                                        "lhs", "lm0", "lm1", "lpp", "lpw0",
+                                        "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
+                                        "lsda", "lsdi", "lspi", "lvp0", "lvp1",
+                                        "lvs";
+                                nvidia,function = "displaya";
+                        };
+                        owc {
+                                nvidia,pins = "owc", "spdi", "spdo", "uac";
+                                nvidia,function = "rsvd2";
+                        };
+                        pmc {
+                                nvidia,pins = "pmc";
+                                nvidia,function = "pwr_on";
+                        };
+                        rm {
+                                nvidia,pins = "rm";
+                                nvidia,function = "i2c1";
+                        };
+                        sdb {
+                                nvidia,pins = "sdb", "sdc", "sdd";
+                                nvidia,function = "pwm";
+                        };
+                        sdio1 {
+                                nvidia,pins = "sdio1";
+                                nvidia,function = "sdio1";
+                        };
+                        slxc {
+                                nvidia,pins = "slxc", "slxd";
+                                nvidia,function = "spdif";
+                        };
+                        spid {
+                                nvidia,pins = "spid", "spie", "spif";
+                                nvidia,function = "spi1";
+                        };
+                        spig {
+                                nvidia,pins = "spig", "spih";
+                                nvidia,function = "spi2_alt";
+                        };
+                        uaa {
+                                nvidia,pins = "uaa", "uab", "uda";
+                                nvidia,function = "ulpi";
+                        };
+                        uad {
+                                nvidia,pins = "uad";
+                                nvidia,function = "irda";
+                        };
+                        uca {
+                                nvidia,pins = "uca", "ucb";
+                                nvidia,function = "uartc";
+                        };
+                        conf_ata {
+                                nvidia,pins = "ata", "atb", "atc", "atd", "ate",
+                                        "cdev1", "dap1", "dtb", "gma", "gmb",
+                                        "gmc", "gmd", "gme", "gpu7", "gpv",
+                                        "i2cp", "pta", "rm", "slxa", "slxk",
+                                        "spia", "spib";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_cdev2 {
+                                nvidia,pins = "cdev2", "csus", "spid", "spif";
+                                nvidia,pull = <1>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_ck32 {
+                                nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+                                        "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+                                nvidia,pull = <0>;
+                        };
+                        conf_crtp {
+                                nvidia,pins = "crtp", "dap2", "dap3", "dap4",
+                                        "dtc", "dte", "dtf", "gpu", "sdio1",
+                                        "slxc", "slxd", "spdi", "spdo", "spig",
+                                        "uac", "uda";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_ddc {
+                                nvidia,pins = "ddc", "dta", "dtd", "kbca",
+                                        "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
+                                        "sdc";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_hdint {
+                                nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+                                        "lpw1", "lsc1", "lsck", "lsda", "lsdi",
+                                        "lvp0", "owc", "sdb";
+                                nvidia,tristate = <1>;
+                        };
+                        conf_irrx {
+                                nvidia,pins = "irrx", "irtx", "sdd", "spic",
+                                        "spie", "spih", "uaa", "uab", "uad",
+                                        "uca", "ucb";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_lc {
+                                nvidia,pins = "lc", "ls";
+                                nvidia,pull = <2>;
+                        };
+                        conf_ld0 {
+                                nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+                                        "ld5", "ld6", "ld7", "ld8", "ld9",
+                                        "ld10", "ld11", "ld12", "ld13", "ld14",
+                                        "ld15", "ld16", "ld17", "ldi", "lhp0",
+                                        "lhp1", "lhp2", "lhs", "lm0", "lpp",
+                                        "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
+                                        "lvs", "pmc";
+                                nvidia,tristate = <0>;
+                        };
+                        conf_ld17_0 {
+                                nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+                                        "ld23_22";
+                                nvidia,pull = <1>;
+                        };
+                };
+        };
+
         pmc@7000f400 {
                 nvidia,invert-interrupt;
         };
diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts
index 6c02abb469d4..10943fb2561c 100644
--- a/arch/arm/boot/dts/tegra-paz00.dts
+++ b/arch/arm/boot/dts/tegra-paz00.dts
@@ -10,6 +10,226 @@
                 reg = <0x00000000 0x20000000>;
         };
 
+        pinmux@70000000 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&state_default>;
+
+                state_default: pinmux {
+                        ata {
+                                nvidia,pins = "ata", "atc", "atd", "ate",
+                                        "dap2", "gmb", "gmc", "gmd", "spia",
+                                        "spib", "spic", "spid", "spie";
+                                nvidia,function = "gmi";
+                        };
+                        atb {
+                                nvidia,pins = "atb", "gma", "gme";
+                                nvidia,function = "sdio4";
+                        };
+                        cdev1 {
+                                nvidia,pins = "cdev1";
+                                nvidia,function = "plla_out";
+                        };
+                        cdev2 {
+                                nvidia,pins = "cdev2";
+                                nvidia,function = "pllp_out4";
+                        };
+                        crtp {
+                                nvidia,pins = "crtp";
+                                nvidia,function = "crt";
+                        };
+                        csus {
+                                nvidia,pins = "csus";
+                                nvidia,function = "pllc_out1";
+                        };
+                        dap1 {
+                                nvidia,pins = "dap1";
+                                nvidia,function = "dap1";
+                        };
+                        dap3 {
+                                nvidia,pins = "dap3";
+                                nvidia,function = "dap3";
+                        };
+                        dap4 {
+                                nvidia,pins = "dap4";
+                                nvidia,function = "dap4";
+                        };
+                        ddc {
+                                nvidia,pins = "ddc";
+                                nvidia,function = "i2c2";
+                        };
+                        dta {
+                                nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
+                                nvidia,function = "rsvd1";
+                        };
+                        dtf {
+                                nvidia,pins = "dtf";
+                                nvidia,function = "i2c3";
+                        };
+                        gpu {
+                                nvidia,pins = "gpu", "sdb", "sdd";
+                                nvidia,function = "pwm";
+                        };
+                        gpu7 {
+                                nvidia,pins = "gpu7";
+                                nvidia,function = "rtck";
+                        };
+                        gpv {
+                                nvidia,pins = "gpv", "slxa", "slxk";
+                                nvidia,function = "pcie";
+                        };
+                        hdint {
+                                nvidia,pins = "hdint", "pta";
+                                nvidia,function = "hdmi";
+                        };
+                        i2cp {
+                                nvidia,pins = "i2cp";
+                                nvidia,function = "i2cp";
+                        };
+                        irrx {
+                                nvidia,pins = "irrx", "irtx";
+                                nvidia,function = "uarta";
+                        };
+                        kbca {
+                                nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
+                                nvidia,function = "kbc";
+                        };
+                        kbcb {
+                                nvidia,pins = "kbcb", "kbcd";
+                                nvidia,function = "sdio2";
+                        };
+                        lcsn {
+                                nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
+                                        "ld3", "ld4", "ld5", "ld6", "ld7",
+                                        "ld8", "ld9", "ld10", "ld11", "ld12",
+                                        "ld13", "ld14", "ld15", "ld16", "ld17",
+                                        "ldc", "ldi", "lhp0", "lhp1", "lhp2",
+                                        "lhs", "lm0", "lm1", "lpp", "lpw0",
+                                        "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
+                                        "lsda", "lsdi", "lspi", "lvp0", "lvp1",
+                                        "lvs";
+                                nvidia,function = "displaya";
+                        };
+                        owc {
+                                nvidia,pins = "owc";
+                                nvidia,function = "owr";
+                        };
+                        pmc {
+                                nvidia,pins = "pmc";
+                                nvidia,function = "pwr_on";
+                        };
+                        rm {
+                                nvidia,pins = "rm";
+                                nvidia,function = "i2c1";
+                        };
+                        sdc {
+                                nvidia,pins = "sdc";
+                                nvidia,function = "twc";
+                        };
+                        sdio1 {
+                                nvidia,pins = "sdio1";
+                                nvidia,function = "sdio1";
+                        };
+                        slxc {
+                                nvidia,pins = "slxc", "slxd";
+                                nvidia,function = "spi4";
+                        };
+                        spdi {
+                                nvidia,pins = "spdi", "spdo";
+                                nvidia,function = "rsvd2";
+                        };
+                        spif {
+                                nvidia,pins = "spif", "uac";
+                                nvidia,function = "rsvd4";
+                        };
+                        spig {
+                                nvidia,pins = "spig", "spih";
+                                nvidia,function = "spi2_alt";
+                        };
+                        uaa {
+                                nvidia,pins = "uaa", "uab", "uda";
+                                nvidia,function = "ulpi";
+                        };
+                        uad {
+                                nvidia,pins = "uad";
+                                nvidia,function = "spdif";
+                        };
+                        uca {
+                                nvidia,pins = "uca", "ucb";
+                                nvidia,function = "uartc";
+                        };
+                        conf_ata {
+                                nvidia,pins = "ata", "atb", "atc", "atd", "ate",
+                                        "cdev1", "dap1", "dap2", "dtf", "gma",
+                                        "gmb", "gmc", "gmd", "gme", "gpu",
+                                        "gpu7", "gpv", "i2cp", "pta", "rm",
+                                        "sdio1", "slxk", "spdo", "uac", "uda";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_cdev2 {
+                                nvidia,pins = "cdev2";
+                                nvidia,pull = <1>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_ck32 {
+                                nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+                                        "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+                                nvidia,pull = <0>;
+                        };
+                        conf_crtp {
+                                nvidia,pins = "crtp", "dap3", "dap4", "dtb",
+                                        "dtc", "dte", "slxa", "slxc", "slxd",
+                                        "spdi";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_csus {
+                                nvidia,pins = "csus", "spia", "spib", "spid",
+                                        "spif";
+                                nvidia,pull = <1>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_ddc {
+                                nvidia,pins = "ddc", "irrx", "irtx", "kbca",
+                                        "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
+                                        "spic", "spig", "uaa", "uab";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_dta {
+                                nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
+                                        "spie", "spih", "uad", "uca", "ucb";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_hdint {
+                                nvidia,pins = "hdint", "ld0", "ld1", "ld2",
+                                        "ld3", "ld4", "ld5", "ld6", "ld7",
+                                        "ld8", "ld9", "ld10", "ld11", "ld12",
+                                        "ld13", "ld14", "ld15", "ld16", "ld17",
+                                        "ldc", "ldi", "lhs", "lsc0", "lspi",
+                                        "lvs", "pmc";
+                                nvidia,tristate = <0>;
+                        };
+                        conf_lc {
+                                nvidia,pins = "lc", "ls";
+                                nvidia,pull = <2>;
+                        };
+                        conf_lcsn {
+                                nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
+                                        "lm0", "lm1", "lpp", "lpw0", "lpw1",
+                                        "lpw2", "lsc1", "lsck", "lsda", "lsdi",
+                                        "lvp0", "lvp1", "sdb";
+                                nvidia,tristate = <1>;
+                        };
+                        conf_ld17_0 {
+                                nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+                                        "ld23_22";
+                                nvidia,pull = <1>;
+                        };
+                };
+        };
+
         i2c@7000c000 {
                 clock-frequency = <400000>;
 
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
index dbf1c5a171c2..ec33116f5df9 100644
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -11,6 +11,249 @@
                 reg = < 0x00000000 0x40000000 >;
         };
 
+        pinmux@70000000 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&state_default>;
+
+                state_default: pinmux {
+                        ata {
+                                nvidia,pins = "ata";
+                                nvidia,function = "ide";
+                        };
+                        atb {
+                                nvidia,pins = "atb", "gma", "gme";
+                                nvidia,function = "sdio4";
+                        };
+                        atc {
+                                nvidia,pins = "atc";
+                                nvidia,function = "nand";
+                        };
+                        atd {
+                                nvidia,pins = "atd", "ate", "gmb", "spia",
+                                        "spib", "spic";
+                                nvidia,function = "gmi";
+                        };
+                        cdev1 {
+                                nvidia,pins = "cdev1";
+                                nvidia,function = "plla_out";
+                        };
+                        cdev2 {
+                                nvidia,pins = "cdev2";
+                                nvidia,function = "pllp_out4";
+                        };
+                        crtp {
+                                nvidia,pins = "crtp", "lm1";
+                                nvidia,function = "crt";
+                        };
+                        csus {
+                                nvidia,pins = "csus";
+                                nvidia,function = "vi_sensor_clk";
+                        };
+                        dap1 {
+                                nvidia,pins = "dap1";
+                                nvidia,function = "dap1";
+                        };
+                        dap2 {
+                                nvidia,pins = "dap2";
+                                nvidia,function = "dap2";
+                        };
+                        dap3 {
+                                nvidia,pins = "dap3";
+                                nvidia,function = "dap3";
+                        };
+                        dap4 {
+                                nvidia,pins = "dap4";
+                                nvidia,function = "dap4";
+                        };
+                        ddc {
+                                nvidia,pins = "ddc", "owc", "spdi", "spdo",
+                                        "uac";
+                                nvidia,function = "rsvd2";
+                        };
+                        dta {
+                                nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
+                                nvidia,function = "vi";
+                        };
+                        dtf {
+                                nvidia,pins = "dtf";
+                                nvidia,function = "i2c3";
+                        };
+                        gmc {
+                                nvidia,pins = "gmc";
+                                nvidia,function = "uartd";
+                        };
+                        gmd {
+                                nvidia,pins = "gmd";
+                                nvidia,function = "sflash";
+                        };
+                        gpu {
+                                nvidia,pins = "gpu";
+                                nvidia,function = "pwm";
+                        };
+                        gpu7 {
+                                nvidia,pins = "gpu7";
+                                nvidia,function = "rtck";
+                        };
+                        gpv {
+                                nvidia,pins = "gpv", "slxa", "slxk";
+                                nvidia,function = "pcie";
+                        };
+                        hdint {
+                                nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
+                                        "lsck", "lsda", "pta";
+                                nvidia,function = "hdmi";
+                        };
+                        i2cp {
+                                nvidia,pins = "i2cp";
+                                nvidia,function = "i2cp";
+                        };
+                        irrx {
+                                nvidia,pins = "irrx", "irtx";
+                                nvidia,function = "uartb";
+                        };
+                        kbca {
+                                nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+                                        "kbce", "kbcf";
+                                nvidia,function = "kbc";
+                        };
+                        lcsn {
+                                nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
+                                        "lsdi", "lvp0";
+                                nvidia,function = "rsvd4";
+                        };
+                        ld0 {
+                                nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+                                        "ld5", "ld6", "ld7", "ld8", "ld9",
+                                        "ld10", "ld11", "ld12", "ld13", "ld14",
+                                        "ld15", "ld16", "ld17", "ldi", "lhp0",
+                                        "lhp1", "lhp2", "lhs", "lpp", "lsc0",
+                                        "lspi", "lvp1", "lvs";
+                                nvidia,function = "displaya";
+                        };
+                        pmc {
+                                nvidia,pins = "pmc";
+                                nvidia,function = "pwr_on";
+                        };
+                        rm {
+                                nvidia,pins = "rm";
+                                nvidia,function = "i2c1";
+                        };
+                        sdb {
+                                nvidia,pins = "sdb", "sdc", "sdd";
+                                nvidia,function = "sdio3";
+                        };
+                        sdio1 {
+                                nvidia,pins = "sdio1";
+                                nvidia,function = "sdio1";
+                        };
+                        slxc {
+                                nvidia,pins = "slxc", "slxd";
+                                nvidia,function = "spdif";
+                        };
+                        spid {
+                                nvidia,pins = "spid", "spie", "spif";
+                                nvidia,function = "spi1";
+                        };
+                        spig {
+                                nvidia,pins = "spig", "spih";
+                                nvidia,function = "spi2_alt";
+                        };
+                        uaa {
+                                nvidia,pins = "uaa", "uab", "uda";
+                                nvidia,function = "ulpi";
+                        };
+                        uad {
+                                nvidia,pins = "uad";
+                                nvidia,function = "irda";
+                        };
+                        uca {
+                                nvidia,pins = "uca", "ucb";
+                                nvidia,function = "uartc";
+                        };
+                        conf_ata {
+                                nvidia,pins = "ata", "atb", "atc", "atd",
+                                        "cdev1", "cdev2", "dap1", "dap2",
+                                        "dap4", "dtf", "gma", "gmc", "gmd",
+                                        "gme", "gpu", "gpu7", "i2cp", "irrx",
+                                        "irtx", "pta", "rm", "sdc", "sdd",
+                                        "slxd", "slxk", "spdi", "spdo", "uac",
+                                        "uad", "uca", "ucb", "uda";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_ate {
+                                nvidia,pins = "ate", "csus", "dap3", "ddc",
+                                        "gpv", "owc", "slxc", "spib", "spid",
+                                        "spie";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_ck32 {
+                                nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+                                        "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+                                nvidia,pull = <0>;
+                        };
+                        conf_crtp {
+                                nvidia,pins = "crtp", "gmb", "slxa", "spia",
+                                        "spig", "spih";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_dta {
+                                nvidia,pins = "dta", "dtb", "dtc", "dtd";
+                                nvidia,pull = <1>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_dte {
+                                nvidia,pins = "dte", "spif";
+                                nvidia,pull = <1>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_hdint {
+                                nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+                                        "lpw1", "lsc1", "lsck", "lsda", "lsdi",
+                                        "lvp0";
+                                nvidia,tristate = <1>;
+                        };
+                        conf_kbca {
+                                nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+                                        "kbce", "kbcf", "sdio1", "spic", "uaa",
+                                        "uab";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_lc {
+                                nvidia,pins = "lc", "ls";
+                                nvidia,pull = <2>;
+                        };
+                        conf_ld0 {
+                                nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+                                        "ld5", "ld6", "ld7", "ld8", "ld9",
+                                        "ld10", "ld11", "ld12", "ld13", "ld14",
+                                        "ld15", "ld16", "ld17", "ldi", "lhp0",
+                                        "lhp1", "lhp2", "lhs", "lm0", "lpp",
+                                        "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
+                                        "lvs", "pmc", "sdb";
+                                nvidia,tristate = <0>;
+                        };
+                        conf_ld17_0 {
+                                nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+                                        "ld23_22";
+                                nvidia,pull = <1>;
+                        };
+                        drive_sdio1 {
+                                nvidia,pins = "drive_sdio1";
+                                nvidia,high-speed-mode = <0>;
+                                nvidia,schmitt = <0>;
+                                nvidia,low-power-mode = <3>;
+                                nvidia,pull-down-strength = <31>;
+                                nvidia,pull-up-strength = <31>;
+                                nvidia,slew-rate-rising = <3>;
+                                nvidia,slew-rate-falling = <3>;
+                        };
+                };
+        };
+
         i2c@7000c000 {
                 clock-frequency = <400000>;
 
diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts
index 252476867b54..98efd5b0d7f9 100644
--- a/arch/arm/boot/dts/tegra-trimslice.dts
+++ b/arch/arm/boot/dts/tegra-trimslice.dts
@@ -10,6 +10,236 @@
                 reg = < 0x00000000 0x40000000 >;
         };
 
+        pinmux@70000000 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&state_default>;
+
+                state_default: pinmux {
+                        ata {
+                                nvidia,pins = "ata";
+                                nvidia,function = "ide";
+                        };
+                        atb {
+                                nvidia,pins = "atb", "gma";
+                                nvidia,function = "sdio4";
+                        };
+                        atc {
+                                nvidia,pins = "atc", "gmb";
+                                nvidia,function = "nand";
+                        };
+                        atd {
+                                nvidia,pins = "atd", "ate", "gme", "pta";
+                                nvidia,function = "gmi";
+                        };
+                        cdev1 {
+                                nvidia,pins = "cdev1";
+                                nvidia,function = "plla_out";
+                        };
+                        cdev2 {
+                                nvidia,pins = "cdev2";
+                                nvidia,function = "pllp_out4";
+                        };
+                        crtp {
+                                nvidia,pins = "crtp";
+                                nvidia,function = "crt";
+                        };
+                        csus {
+                                nvidia,pins = "csus";
+                                nvidia,function = "vi_sensor_clk";
+                        };
+                        dap1 {
+                                nvidia,pins = "dap1";
+                                nvidia,function = "dap1";
+                        };
+                        dap2 {
+                                nvidia,pins = "dap2";
+                                nvidia,function = "dap2";
+                        };
+                        dap3 {
+                                nvidia,pins = "dap3";
+                                nvidia,function = "dap3";
+                        };
+                        dap4 {
+                                nvidia,pins = "dap4";
+                                nvidia,function = "dap4";
+                        };
+                        ddc {
+                                nvidia,pins = "ddc";
+                                nvidia,function = "i2c2";
+                        };
+                        dta {
+                                nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
+                                nvidia,function = "vi";
+                        };
+                        dtf {
+                                nvidia,pins = "dtf";
+                                nvidia,function = "i2c3";
+                        };
+                        gmc {
+                                nvidia,pins = "gmc", "gmd";
+                                nvidia,function = "sflash";
+                        };
+                        gpu {
+                                nvidia,pins = "gpu";
+                                nvidia,function = "uarta";
+                        };
+                        gpu7 {
+                                nvidia,pins = "gpu7";
+                                nvidia,function = "rtck";
+                        };
+                        gpv {
+                                nvidia,pins = "gpv", "slxa", "slxk";
+                                nvidia,function = "pcie";
+                        };
+                        hdint {
+                                nvidia,pins = "hdint";
+                                nvidia,function = "hdmi";
+                        };
+                        i2cp {
+                                nvidia,pins = "i2cp";
+                                nvidia,function = "i2cp";
+                        };
+                        irrx {
+                                nvidia,pins = "irrx", "irtx";
+                                nvidia,function = "uartb";
+                        };
+                        kbca {
+                                nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+                                        "kbce", "kbcf";
+                                nvidia,function = "kbc";
+                        };
+                        lcsn {
+                                nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
+                                        "ld3", "ld4", "ld5", "ld6", "ld7",
+                                        "ld8", "ld9", "ld10", "ld11", "ld12",
+                                        "ld13", "ld14", "ld15", "ld16", "ld17",
+                                        "ldc", "ldi", "lhp0", "lhp1", "lhp2",
+                                        "lhs", "lm0", "lm1", "lpp", "lpw0",
+                                        "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
+                                        "lsda", "lsdi", "lspi", "lvp0", "lvp1",
+                                        "lvs";
+                                nvidia,function = "displaya";
+                        };
+                        owc {
+                                nvidia,pins = "owc", "uac";
+                                nvidia,function = "rsvd2";
+                        };
+                        pmc {
+                                nvidia,pins = "pmc";
+                                nvidia,function = "pwr_on";
+                        };
+                        rm {
+                                nvidia,pins = "rm";
+                                nvidia,function = "i2c1";
+                        };
+                        sdb {
+                                nvidia,pins = "sdb", "sdc", "sdd";
+                                nvidia,function = "pwm";
+                        };
+                        sdio1 {
+                                nvidia,pins = "sdio1";
+                                nvidia,function = "sdio1";
+                        };
+                        slxc {
+                                nvidia,pins = "slxc", "slxd";
+                                nvidia,function = "sdio3";
+                        };
+                        spdi {
+                                nvidia,pins = "spdi", "spdo";
+                                nvidia,function = "spdif";
+                        };
+                        spia {
+                                nvidia,pins = "spia", "spib", "spic";
+                                nvidia,function = "spi2";
+                        };
+                        spid {
+                                nvidia,pins = "spid", "spie", "spif";
+                                nvidia,function = "spi1";
+                        };
+                        spig {
+                                nvidia,pins = "spig", "spih";
+                                nvidia,function = "spi2_alt";
+                        };
+                        uaa {
+                                nvidia,pins = "uaa", "uab", "uda";
+                                nvidia,function = "ulpi";
+                        };
+                        uad {
+                                nvidia,pins = "uad";
+                                nvidia,function = "irda";
+                        };
+                        uca {
+                                nvidia,pins = "uca", "ucb";
+                                nvidia,function = "uartc";
+                        };
+                        conf_ata {
+                                nvidia,pins = "ata", "atc", "atd", "ate",
+                                        "crtp", "dap2", "dap3", "dap4", "dta",
+                                        "dtb", "dtc", "dtd", "dte", "gmb",
+                                        "gme", "i2cp", "pta", "slxc", "slxd",
+                                        "spdi", "spdo", "uda";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_atb {
+                                nvidia,pins = "atb", "cdev1", "dap1", "gma",
+                                        "gmc", "gmd", "gpu", "gpu7", "gpv",
+                                        "sdio1", "slxa", "slxk", "uac";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_cdev2 {
+                                nvidia,pins = "cdev2", "csus", "spia", "spib",
+                                        "spid", "spif";
+                                nvidia,pull = <1>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_ck32 {
+                                nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+                                        "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+                                nvidia,pull = <0>;
+                        };
+                        conf_ddc {
+                                nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_hdint {
+                                nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+                                        "lpw1", "lsc1", "lsck", "lsda", "lsdi",
+                                        "lvp0", "pmc";
+                                nvidia,tristate = <1>;
+                        };
+                        conf_irrx {
+                                nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
+                                        "kbcc", "kbcd", "kbce", "kbcf", "owc",
+                                        "spic", "spie", "spig", "spih", "uaa",
+                                        "uab", "uad", "uca", "ucb";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_lc {
+                                nvidia,pins = "lc", "ls";
+                                nvidia,pull = <2>;
+                        };
+                        conf_ld0 {
+                                nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+                                        "ld5", "ld6", "ld7", "ld8", "ld9",
+                                        "ld10", "ld11", "ld12", "ld13", "ld14",
+                                        "ld15", "ld16", "ld17", "ldi", "lhp0",
+                                        "lhp1", "lhp2", "lhs", "lm0", "lpp",
+                                        "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
+                                        "lvs", "sdb";
+                                nvidia,tristate = <0>;
+                        };
+                        conf_ld17_0 {
+                                nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+                                        "ld23_22";
+                                nvidia,pull = <1>;
+                        };
+                };
+        };
+
         i2c@7000c000 {
                 clock-frequency = <400000>;
         };
diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts
index 2dcff8728e90..71eb2e50a668 100644
--- a/arch/arm/boot/dts/tegra-ventana.dts
+++ b/arch/arm/boot/dts/tegra-ventana.dts
@@ -10,6 +10,236 @@
                 reg = < 0x00000000 0x40000000 >;
         };
 
+        pinmux@70000000 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&state_default>;
+
+                state_default: pinmux {
+                        ata {
+                                nvidia,pins = "ata";
+                                nvidia,function = "ide";
+                        };
+                        atb {
+                                nvidia,pins = "atb", "gma", "gme";
+                                nvidia,function = "sdio4";
+                        };
+                        atc {
+                                nvidia,pins = "atc";
+                                nvidia,function = "nand";
+                        };
+                        atd {
+                                nvidia,pins = "atd", "ate", "gmb", "spia",
+                                        "spib", "spic";
+                                nvidia,function = "gmi";
+                        };
+                        cdev1 {
+                                nvidia,pins = "cdev1";
+                                nvidia,function = "plla_out";
+                        };
+                        cdev2 {
+                                nvidia,pins = "cdev2";
+                                nvidia,function = "pllp_out4";
+                        };
+                        crtp {
+                                nvidia,pins = "crtp", "lm1";
+                                nvidia,function = "crt";
+                        };
+                        csus {
+                                nvidia,pins = "csus";
+                                nvidia,function = "vi_sensor_clk";
+                        };
+                        dap1 {
+                                nvidia,pins = "dap1";
+                                nvidia,function = "dap1";
+                        };
+                        dap2 {
+                                nvidia,pins = "dap2";
+                                nvidia,function = "dap2";
+                        };
+                        dap3 {
+                                nvidia,pins = "dap3";
+                                nvidia,function = "dap3";
+                        };
+                        dap4 {
+                                nvidia,pins = "dap4";
+                                nvidia,function = "dap4";
+                        };
+                        ddc {
+                                nvidia,pins = "ddc", "owc", "spdi", "spdo",
+                                        "uac";
+                                nvidia,function = "rsvd2";
+                        };
+                        dta {
+                                nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
+                                nvidia,function = "vi";
+                        };
+                        dtf {
+                                nvidia,pins = "dtf";
+                                nvidia,function = "i2c3";
+                        };
+                        gmc {
+                                nvidia,pins = "gmc";
+                                nvidia,function = "uartd";
+                        };
+                        gmd {
+                                nvidia,pins = "gmd";
+                                nvidia,function = "sflash";
+                        };
+                        gpu {
+                                nvidia,pins = "gpu";
+                                nvidia,function = "pwm";
+                        };
+                        gpu7 {
+                                nvidia,pins = "gpu7";
+                                nvidia,function = "rtck";
+                        };
+                        gpv {
+                                nvidia,pins = "gpv", "slxa", "slxk";
+                                nvidia,function = "pcie";
+                        };
+                        hdint {
+                                nvidia,pins = "hdint", "pta";
+                                nvidia,function = "hdmi";
+                        };
+                        i2cp {
+                                nvidia,pins = "i2cp";
+                                nvidia,function = "i2cp";
+                        };
+                        irrx {
+                                nvidia,pins = "irrx", "irtx";
+                                nvidia,function = "uartb";
+                        };
+                        kbca {
+                                nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+                                        "kbce", "kbcf";
+                                nvidia,function = "kbc";
+                        };
+                        lcsn {
+                                nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
+                                        "lsdi", "lvp0";
+                                nvidia,function = "rsvd4";
+                        };
+                        ld0 {
+                                nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+                                        "ld5", "ld6", "ld7", "ld8", "ld9",
+                                        "ld10", "ld11", "ld12", "ld13", "ld14",
+                                        "ld15", "ld16", "ld17", "ldi", "lhp0",
+                                        "lhp1", "lhp2", "lhs", "lpp", "lpw0",
+                                        "lpw2", "lsc0", "lsc1", "lsck", "lsda",
+                                        "lspi", "lvp1", "lvs";
+                                nvidia,function = "displaya";
+                        };
+                        pmc {
+                                nvidia,pins = "pmc";
+                                nvidia,function = "pwr_on";
+                        };
+                        rm {
+                                nvidia,pins = "rm";
+                                nvidia,function = "i2c1";
+                        };
+                        sdb {
+                                nvidia,pins = "sdb", "sdc", "sdd", "slxc";
+                                nvidia,function = "sdio3";
+                        };
+                        sdio1 {
+                                nvidia,pins = "sdio1";
+                                nvidia,function = "sdio1";
+                        };
+                        slxd {
+                                nvidia,pins = "slxd";
+                                nvidia,function = "spdif";
+                        };
+                        spid {
+                                nvidia,pins = "spid", "spie", "spif";
+                                nvidia,function = "spi1";
+                        };
+                        spig {
+                                nvidia,pins = "spig", "spih";
+                                nvidia,function = "spi2_alt";
+                        };
+                        uaa {
+                                nvidia,pins = "uaa", "uab", "uda";
+                                nvidia,function = "ulpi";
+                        };
+                        uad {
+                                nvidia,pins = "uad";
+                                nvidia,function = "irda";
+                        };
+                        uca {
+                                nvidia,pins = "uca", "ucb";
+                                nvidia,function = "uartc";
+                        };
+                        conf_ata {
+                                nvidia,pins = "ata", "atb", "atc", "atd",
+                                        "cdev1", "cdev2", "dap1", "dap2",
+                                        "dap4", "ddc", "dtf", "gma", "gmc",
+                                        "gme", "gpu", "gpu7", "i2cp", "irrx",
+                                        "irtx", "pta", "rm", "sdc", "sdd",
+                                        "slxc", "slxd", "slxk", "spdi", "spdo",
+                                        "uac", "uad", "uca", "ucb", "uda";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_ate {
+                                nvidia,pins = "ate", "csus", "dap3", "gmd",
+                                        "gpv", "owc", "spia", "spib", "spic",
+                                        "spid", "spie", "spig";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_ck32 {
+                                nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+                                        "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+                                nvidia,pull = <0>;
+                        };
+                        conf_crtp {
+                                nvidia,pins = "crtp", "gmb", "slxa", "spih";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_dta {
+                                nvidia,pins = "dta", "dtb", "dtc", "dtd";
+                                nvidia,pull = <1>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_dte {
+                                nvidia,pins = "dte", "spif";
+                                nvidia,pull = <1>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_hdint {
+                                nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+                                        "lpw1", "lsck", "lsda", "lsdi", "lvp0";
+                                nvidia,tristate = <1>;
+                        };
+                        conf_kbca {
+                                nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+                                        "kbce", "kbcf", "sdio1", "uaa", "uab";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_lc {
+                                nvidia,pins = "lc", "ls";
+                                nvidia,pull = <2>;
+                        };
+                        conf_ld0 {
+                                nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+                                        "ld5", "ld6", "ld7", "ld8", "ld9",
+                                        "ld10", "ld11", "ld12", "ld13", "ld14",
+                                        "ld15", "ld16", "ld17", "ldi", "lhp0",
+                                        "lhp1", "lhp2", "lhs", "lm0", "lpp",
+                                        "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
+                                        "lvp1", "lvs", "pmc", "sdb";
+                                nvidia,tristate = <0>;
+                        };
+                        conf_ld17_0 {
+                                nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+                                        "ld23_22";
+                                nvidia,pull = <1>;
+                        };
+                };
+        };
+
         i2c@7000c000 {
                 clock-frequency = <400000>;
 
diff --git a/arch/arm/configs/spear3xx_defconfig b/arch/arm/configs/spear3xx_defconfig
index fea7e1f026a3..7ed42912d69a 100644
--- a/arch/arm/configs/spear3xx_defconfig
+++ b/arch/arm/configs/spear3xx_defconfig
@@ -2,33 +2,67 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
 CONFIG_PLAT_SPEAR=y
-CONFIG_BOARD_SPEAR300_EVB=y
-CONFIG_BOARD_SPEAR310_EVB=y
-CONFIG_BOARD_SPEAR320_EVB=y
+CONFIG_MACH_SPEAR300=y
+CONFIG_MACH_SPEAR310=y
+CONFIG_MACH_SPEAR320=y
 CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSMC=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_WLAN is not set
 CONFIG_INPUT_FF_MEMLESS=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_SPEAR=y
 # CONFIG_INPUT_MOUSE is not set
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_RAW_DRIVER=y
 CONFIG_MAX_RAW_DEVS=8192
+CONFIG_I2C=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_PL061=y
 # CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
 # CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SPEAR=y
+CONFIG_RTC_CLASS=y
+CONFIG_DMADEVICES=y
+CONFIG_AMBA_PL08X=y
+CONFIG_DMATEST=m
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_SECURITY=y
@@ -39,8 +73,6 @@ CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
 CONFIG_TMPFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="utf8"
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=m
@@ -48,6 +80,4 @@ CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/spear6xx_defconfig b/arch/arm/configs/spear6xx_defconfig
index cef2e836afd2..cf94bc73a0e0 100644
--- a/arch/arm/configs/spear6xx_defconfig
+++ b/arch/arm/configs/spear6xx_defconfig
@@ -2,29 +2,58 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
 CONFIG_PLAT_SPEAR=y
 CONFIG_ARCH_SPEAR6XX=y
-CONFIG_BOARD_SPEAR600_EVB=y
+CONFIG_BOARD_SPEAR600_DT=y
 CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSMC=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_WLAN is not set
 CONFIG_INPUT_FF_MEMLESS=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
 CONFIG_RAW_DRIVER=y
 CONFIG_MAX_RAW_DEVS=8192
+CONFIG_I2C=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_PL061=y
 # CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
 # CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_RTC_CLASS=y
+CONFIG_DMADEVICES=y
+CONFIG_AMBA_PL08X=y
+CONFIG_DMATEST=m
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_SECURITY=y
@@ -35,8 +64,6 @@ CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
 CONFIG_TMPFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="utf8"
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=m
@@ -44,6 +71,4 @@ CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig
index 2cee6b0de371..8bd37291fa4f 100644
--- a/arch/arm/mach-spear3xx/Kconfig
+++ b/arch/arm/mach-spear3xx/Kconfig
@@ -5,39 +5,22 @@
 if ARCH_SPEAR3XX
 
 menu "SPEAr3xx Implementations"
-config BOARD_SPEAR300_EVB
-        bool "SPEAr300 Evaluation Board"
-        select MACH_SPEAR300
-        help
-          Supports ST SPEAr300 Evaluation Board
-
-config BOARD_SPEAR310_EVB
-        bool "SPEAr310 Evaluation Board"
-        select MACH_SPEAR310
-        help
-          Supports ST SPEAr310 Evaluation Board
-
-config BOARD_SPEAR320_EVB
-        bool "SPEAr320 Evaluation Board"
-        select MACH_SPEAR320
-        help
-          Supports ST SPEAr320 Evaluation Board
-
-endmenu
-
 config MACH_SPEAR300
-        bool "SPEAr300"
+        bool "SPEAr300 Machine support with Device Tree"
+        select PINCTRL_SPEAR300
         help
-          Supports ST SPEAr300 Machine
+          Supports ST SPEAr300 machine configured via the device-tree
 
 config MACH_SPEAR310
-        bool "SPEAr310"
+        bool "SPEAr310 Machine support with Device Tree"
+        select PINCTRL_SPEAR310
         help
-          Supports ST SPEAr310 Machine
+          Supports ST SPEAr310 machine configured via the device-tree
 
 config MACH_SPEAR320
-        bool "SPEAr320"
+        bool "SPEAr320 Machine support with Device Tree"
+        select PINCTRL_SPEAR320
         help
-          Supports ST SPEAr320 Machine
-
+          Supports ST SPEAr320 machine configured via the device-tree
+endmenu
 endif #ARCH_SPEAR3XX
diff --git a/arch/arm/mach-spear3xx/Makefile b/arch/arm/mach-spear3xx/Makefile
index b24862489704..17b5d83cf2d5 100644
--- a/arch/arm/mach-spear3xx/Makefile
+++ b/arch/arm/mach-spear3xx/Makefile
@@ -3,24 +3,13 @@
 #
 
 # common files
-obj-y   += spear3xx.o clock.o
+obj-$(CONFIG_ARCH_SPEAR3XX)     += spear3xx.o clock.o
 
 # spear300 specific files
 obj-$(CONFIG_MACH_SPEAR300) += spear300.o
 
-# spear300 boards files
-obj-$(CONFIG_BOARD_SPEAR300_EVB) += spear300_evb.o
-
-
 # spear310 specific files
 obj-$(CONFIG_MACH_SPEAR310) += spear310.o
 
-# spear310 boards files
-obj-$(CONFIG_BOARD_SPEAR310_EVB) += spear310_evb.o
-
-
 # spear320 specific files
 obj-$(CONFIG_MACH_SPEAR320) += spear320.o
-
-# spear320 boards files
-obj-$(CONFIG_BOARD_SPEAR320_EVB) += spear320_evb.o
diff --git a/arch/arm/mach-spear3xx/Makefile.boot b/arch/arm/mach-spear3xx/Makefile.boot
index 4674a4c221db..d93e2177e6ec 100644
--- a/arch/arm/mach-spear3xx/Makefile.boot
+++ b/arch/arm/mach-spear3xx/Makefile.boot
@@ -1,3 +1,7 @@
 zreladdr-y      += 0x00008000
 params_phys-y   := 0x00000100
 initrd_phys-y   := 0x00800000
+
+dtb-$(CONFIG_MACH_SPEAR300)     += spear300-evb.dtb
+dtb-$(CONFIG_MACH_SPEAR310)     += spear310-evb.dtb
+dtb-$(CONFIG_MACH_SPEAR320)     += spear320-evb.dtb
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index 6c4841f55223..eeafe38eab25 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -11,9 +11,11 @@
  * warranty of any kind, whether express or implied.
  */
 
+#include <linux/clkdev.h>
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/of_platform.h>
 #include <asm/mach-types.h>
 #include <plat/clock.h>
 #include <mach/misc_regs.h>
@@ -411,6 +413,21 @@ static struct clk usbd_clk = {
         .recalc = &follow_parent,
 };
 
+/* clock derived from usbh clk */
+/* usbh0 clock */
+static struct clk usbh0_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &usbh_clk,
+        .recalc = &follow_parent,
+};
+
+/* usbh1 clock */
+static struct clk usbh1_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &usbh_clk,
+        .recalc = &follow_parent,
+};
+
 /* clock derived from ahb clk */
 /* apb masks structure */
 static struct bus_clk_masks apb_masks = {
@@ -652,109 +669,126 @@ static struct clk pwm_clk = {
 
 /* array of all spear 3xx clock lookups */
 static struct clk_lookup spear_clk_lookups[] = {
-        { .con_id = "apb_pclk",         .clk = &dummy_apb_pclk},
+        CLKDEV_INIT(NULL, "apb_pclk", &dummy_apb_pclk),
         /* root clks */
-        { .con_id = "osc_32k_clk",      .clk = &osc_32k_clk},
-        { .con_id = "osc_24m_clk",      .clk = &osc_24m_clk},
+        CLKDEV_INIT(NULL, "osc_32k_clk", &osc_32k_clk),
+        CLKDEV_INIT(NULL, "osc_24m_clk", &osc_24m_clk),
         /* clock derived from 32 KHz osc clk */
-        { .dev_id = "rtc-spear",        .clk = &rtc_clk},
+        CLKDEV_INIT("fc900000.rtc", NULL, &rtc_clk),
         /* clock derived from 24 MHz osc clk */
-        { .con_id = "pll1_clk",         .clk = &pll1_clk},
-        { .con_id = "pll3_48m_clk",     .clk = &pll3_48m_clk},
-        { .dev_id = "wdt",              .clk = &wdt_clk},
+        CLKDEV_INIT(NULL, "pll1_clk", &pll1_clk),
+        CLKDEV_INIT(NULL, "pll3_48m_clk", &pll3_48m_clk),
+        CLKDEV_INIT("fc880000.wdt", NULL, &wdt_clk),
         /* clock derived from pll1 clk */
-        { .con_id = "cpu_clk",          .clk = &cpu_clk},
-        { .con_id = "ahb_clk",          .clk = &ahb_clk},
-        { .con_id = "uart_synth_clk",   .clk = &uart_synth_clk},
-        { .con_id = "firda_synth_clk",  .clk = &firda_synth_clk},
-        { .con_id = "gpt0_synth_clk",   .clk = &gpt0_synth_clk},
-        { .con_id = "gpt1_synth_clk",   .clk = &gpt1_synth_clk},
-        { .con_id = "gpt2_synth_clk",   .clk = &gpt2_synth_clk},
-        { .dev_id = "uart",             .clk = &uart_clk},
-        { .dev_id = "firda",            .clk = &firda_clk},
-        { .dev_id = "gpt0",             .clk = &gpt0_clk},
-        { .dev_id = "gpt1",             .clk = &gpt1_clk},
-        { .dev_id = "gpt2",             .clk = &gpt2_clk},
+        CLKDEV_INIT(NULL, "cpu_clk", &cpu_clk),
+        CLKDEV_INIT(NULL, "ahb_clk", &ahb_clk),
+        CLKDEV_INIT(NULL, "uart_synth_clk", &uart_synth_clk),
+        CLKDEV_INIT(NULL, "firda_synth_clk", &firda_synth_clk),
+        CLKDEV_INIT(NULL, "gpt0_synth_clk", &gpt0_synth_clk),
+        CLKDEV_INIT(NULL, "gpt1_synth_clk", &gpt1_synth_clk),
+        CLKDEV_INIT(NULL, "gpt2_synth_clk", &gpt2_synth_clk),
+        CLKDEV_INIT("d0000000.serial", NULL, &uart_clk),
+        CLKDEV_INIT("firda", NULL, &firda_clk),
+        CLKDEV_INIT("gpt0", NULL, &gpt0_clk),
+        CLKDEV_INIT("gpt1", NULL, &gpt1_clk),
+        CLKDEV_INIT("gpt2", NULL, &gpt2_clk),
         /* clock derived from pll3 clk */
-        { .dev_id = "designware_udc",   .clk = &usbd_clk},
-        { .con_id = "usbh_clk",         .clk = &usbh_clk},
+        CLKDEV_INIT("designware_udc", NULL, &usbd_clk),
+        CLKDEV_INIT(NULL, "usbh_clk", &usbh_clk),
+        /* clock derived from usbh clk */
+        CLKDEV_INIT(NULL, "usbh.0_clk", &usbh0_clk),
+        CLKDEV_INIT(NULL, "usbh.1_clk", &usbh1_clk),
         /* clock derived from ahb clk */
-        { .con_id = "apb_clk",          .clk = &apb_clk},
-        { .dev_id = "i2c_designware.0", .clk = &i2c_clk},
-        { .dev_id = "dma",              .clk = &dma_clk},
-        { .dev_id = "jpeg",             .clk = &jpeg_clk},
-        { .dev_id = "gmac",             .clk = &gmac_clk},
-        { .dev_id = "smi",              .clk = &smi_clk},
-        { .dev_id = "c3",               .clk = &c3_clk},
+        CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
+        CLKDEV_INIT("d0180000.i2c", NULL, &i2c_clk),
+        CLKDEV_INIT("fc400000.dma", NULL, &dma_clk),
+        CLKDEV_INIT("jpeg", NULL, &jpeg_clk),
+        CLKDEV_INIT("e0800000.eth", NULL, &gmac_clk),
+        CLKDEV_INIT("fc000000.flash", NULL, &smi_clk),
+        CLKDEV_INIT("c3", NULL, &c3_clk),
         /* clock derived from apb clk */
-        { .dev_id = "adc",              .clk = &adc_clk},
-        { .dev_id = "ssp-pl022.0",      .clk = &ssp0_clk},
-        { .dev_id = "gpio",             .clk = &gpio_clk},
+        CLKDEV_INIT("adc", NULL, &adc_clk),
+        CLKDEV_INIT("d0100000.spi", NULL, &ssp0_clk),
+        CLKDEV_INIT("fc980000.gpio", NULL, &gpio_clk),
 };
 
 /* array of all spear 300 clock lookups */
 #ifdef CONFIG_MACH_SPEAR300
 static struct clk_lookup spear300_clk_lookups[] = {
-        { .dev_id = "clcd",             .clk = &clcd_clk},
-        { .con_id = "fsmc",             .clk = &fsmc_clk},
-        { .dev_id = "gpio1",            .clk = &gpio1_clk},
-        { .dev_id = "keyboard",         .clk = &kbd_clk},
-        { .dev_id = "sdhci",            .clk = &sdhci_clk},
+        CLKDEV_INIT("60000000.clcd", NULL, &clcd_clk),
+        CLKDEV_INIT("94000000.flash", NULL, &fsmc_clk),
+        CLKDEV_INIT("a9000000.gpio", NULL, &gpio1_clk),
+        CLKDEV_INIT("a0000000.kbd", NULL, &kbd_clk),
+        CLKDEV_INIT("70000000.sdhci", NULL, &sdhci_clk),
 };
+
+void __init spear300_clk_init(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
+                clk_register(&spear_clk_lookups[i]);
+
+        for (i = 0; i < ARRAY_SIZE(spear300_clk_lookups); i++)
+                clk_register(&spear300_clk_lookups[i]);
+
+        clk_init();
+}
 #endif
 
 /* array of all spear 310 clock lookups */
 #ifdef CONFIG_MACH_SPEAR310
 static struct clk_lookup spear310_clk_lookups[] = {
-        { .con_id = "fsmc",             .clk = &fsmc_clk},
-        { .con_id = "emi",              .clk = &emi_clk},
-        { .dev_id = "uart1",            .clk = &uart1_clk},
-        { .dev_id = "uart2",            .clk = &uart2_clk},
-        { .dev_id = "uart3",            .clk = &uart3_clk},
-        { .dev_id = "uart4",            .clk = &uart4_clk},
-        { .dev_id = "uart5",            .clk = &uart5_clk},
+        CLKDEV_INIT("44000000.flash", NULL, &fsmc_clk),
+        CLKDEV_INIT(NULL, "emi", &emi_clk),
+        CLKDEV_INIT("b2000000.serial", NULL, &uart1_clk),
+        CLKDEV_INIT("b2080000.serial", NULL, &uart2_clk),
+        CLKDEV_INIT("b2100000.serial", NULL, &uart3_clk),
+        CLKDEV_INIT("b2180000.serial", NULL, &uart4_clk),
+        CLKDEV_INIT("b2200000.serial", NULL, &uart5_clk),
 };
+
+void __init spear310_clk_init(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
+                clk_register(&spear_clk_lookups[i]);
+
+        for (i = 0; i < ARRAY_SIZE(spear310_clk_lookups); i++)
+                clk_register(&spear310_clk_lookups[i]);
+
+        clk_init();
+}
 #endif
 
 /* array of all spear 320 clock lookups */
 #ifdef CONFIG_MACH_SPEAR320
 static struct clk_lookup spear320_clk_lookups[] = {
-        { .dev_id = "clcd",             .clk = &clcd_clk},
-        { .con_id = "fsmc",             .clk = &fsmc_clk},
-        { .dev_id = "i2c_designware.1", .clk = &i2c1_clk},
-        { .con_id = "emi",              .clk = &emi_clk},
-        { .dev_id = "pwm",              .clk = &pwm_clk},
-        { .dev_id = "sdhci",            .clk = &sdhci_clk},
-        { .dev_id = "c_can_platform.0", .clk = &can0_clk},
-        { .dev_id = "c_can_platform.1", .clk = &can1_clk},
-        { .dev_id = "ssp-pl022.1",      .clk = &ssp1_clk},
-        { .dev_id = "ssp-pl022.2",      .clk = &ssp2_clk},
-        { .dev_id = "uart1",            .clk = &uart1_clk},
-        { .dev_id = "uart2",            .clk = &uart2_clk},
-};
-#endif
-
-void __init spear3xx_clk_init(void)
+        CLKDEV_INIT("90000000.clcd", NULL, &clcd_clk),
+        CLKDEV_INIT("4c000000.flash", NULL, &fsmc_clk),
+        CLKDEV_INIT("a7000000.i2c", NULL, &i2c1_clk),
+        CLKDEV_INIT(NULL, "emi", &emi_clk),
+        CLKDEV_INIT("pwm", NULL, &pwm_clk),
+        CLKDEV_INIT("70000000.sdhci", NULL, &sdhci_clk),
+        CLKDEV_INIT("c_can_platform.0", NULL, &can0_clk),
+        CLKDEV_INIT("c_can_platform.1", NULL, &can1_clk),
+        CLKDEV_INIT("a5000000.spi", NULL, &ssp1_clk),
+        CLKDEV_INIT("a6000000.spi", NULL, &ssp2_clk),
+        CLKDEV_INIT("a3000000.serial", NULL, &uart1_clk),
+        CLKDEV_INIT("a4000000.serial", NULL, &uart2_clk),
+};
+
+void __init spear320_clk_init(void)
 {
-        int i, cnt;
-        struct clk_lookup *lookups;
-
-        if (machine_is_spear300()) {
-                cnt = ARRAY_SIZE(spear300_clk_lookups);
-                lookups = spear300_clk_lookups;
-        } else if (machine_is_spear310()) {
-                cnt = ARRAY_SIZE(spear310_clk_lookups);
-                lookups = spear310_clk_lookups;
-        } else {
-                cnt = ARRAY_SIZE(spear320_clk_lookups);
-                lookups = spear320_clk_lookups;
-        }
+        int i;
 
         for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
                 clk_register(&spear_clk_lookups[i]);
 
-        for (i = 0; i < cnt; i++)
-                clk_register(&lookups[i]);
+        for (i = 0; i < ARRAY_SIZE(spear320_clk_lookups); i++)
+                clk_register(&spear320_clk_lookups[i]);
 
         clk_init();
 }
+#endif
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 14276e5a98d2..9603bf4d5119 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -14,12 +14,12 @@
 #ifndef __MACH_GENERIC_H
 #define __MACH_GENERIC_H
 
+#include <linux/amba/pl08x.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/amba/bus.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <plat/padmux.h>
 
 /* spear3xx declarations */
 /*
@@ -31,171 +31,32 @@
 #define SPEAR_GPT0_CHAN1_IRQ    SPEAR3XX_IRQ_CPU_GPT1_2
 
 /* Add spear3xx family device structure declarations here */
-extern struct amba_device spear3xx_gpio_device;
-extern struct amba_device spear3xx_uart_device;
 extern struct sys_timer spear3xx_timer;
+extern struct pl022_ssp_controller pl022_plat_data;
+extern struct pl08x_platform_data pl080_plat_data;
 
 /* Add spear3xx family function declarations here */
-void __init spear3xx_clk_init(void);
 void __init spear_setup_timer(void);
 void __init spear3xx_map_io(void);
-void __init spear3xx_init_irq(void);
-void __init spear3xx_init(void);
+void __init spear3xx_dt_init_irq(void);
 
 void spear_restart(char, const char *);
 
-/* pad mux declarations */
-#define PMX_FIRDA_MASK          (1 << 14)
-#define PMX_I2C_MASK            (1 << 13)
-#define PMX_SSP_CS_MASK         (1 << 12)
-#define PMX_SSP_MASK            (1 << 11)
-#define PMX_MII_MASK            (1 << 10)
-#define PMX_GPIO_PIN0_MASK      (1 << 9)
-#define PMX_GPIO_PIN1_MASK      (1 << 8)
-#define PMX_GPIO_PIN2_MASK      (1 << 7)
-#define PMX_GPIO_PIN3_MASK      (1 << 6)
-#define PMX_GPIO_PIN4_MASK      (1 << 5)
-#define PMX_GPIO_PIN5_MASK      (1 << 4)
-#define PMX_UART0_MODEM_MASK    (1 << 3)
-#define PMX_UART0_MASK          (1 << 2)
-#define PMX_TIMER_3_4_MASK      (1 << 1)
-#define PMX_TIMER_1_2_MASK      (1 << 0)
-
-/* pad mux devices */
-extern struct pmx_dev spear3xx_pmx_firda;
-extern struct pmx_dev spear3xx_pmx_i2c;
-extern struct pmx_dev spear3xx_pmx_ssp_cs;
-extern struct pmx_dev spear3xx_pmx_ssp;
-extern struct pmx_dev spear3xx_pmx_mii;
-extern struct pmx_dev spear3xx_pmx_gpio_pin0;
-extern struct pmx_dev spear3xx_pmx_gpio_pin1;
-extern struct pmx_dev spear3xx_pmx_gpio_pin2;
-extern struct pmx_dev spear3xx_pmx_gpio_pin3;
-extern struct pmx_dev spear3xx_pmx_gpio_pin4;
-extern struct pmx_dev spear3xx_pmx_gpio_pin5;
-extern struct pmx_dev spear3xx_pmx_uart0_modem;
-extern struct pmx_dev spear3xx_pmx_uart0;
-extern struct pmx_dev spear3xx_pmx_timer_3_4;
-extern struct pmx_dev spear3xx_pmx_timer_1_2;
-
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
-/* padmux plgpio devices */
-extern struct pmx_dev spear3xx_pmx_plgpio_0_1;
-extern struct pmx_dev spear3xx_pmx_plgpio_2_3;
-extern struct pmx_dev spear3xx_pmx_plgpio_4_5;
-extern struct pmx_dev spear3xx_pmx_plgpio_6_9;
-extern struct pmx_dev spear3xx_pmx_plgpio_10_27;
-extern struct pmx_dev spear3xx_pmx_plgpio_28;
-extern struct pmx_dev spear3xx_pmx_plgpio_29;
-extern struct pmx_dev spear3xx_pmx_plgpio_30;
-extern struct pmx_dev spear3xx_pmx_plgpio_31;
-extern struct pmx_dev spear3xx_pmx_plgpio_32;
-extern struct pmx_dev spear3xx_pmx_plgpio_33;
-extern struct pmx_dev spear3xx_pmx_plgpio_34_36;
-extern struct pmx_dev spear3xx_pmx_plgpio_37_42;
-extern struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48;
-extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50;
-#endif
-
 /* spear300 declarations */
 #ifdef CONFIG_MACH_SPEAR300
-/* Add spear300 machine device structure declarations here */
-extern struct amba_device spear300_gpio1_device;
-
-/* pad mux modes */
-extern struct pmx_mode spear300_nand_mode;
-extern struct pmx_mode spear300_nor_mode;
-extern struct pmx_mode spear300_photo_frame_mode;
-extern struct pmx_mode spear300_lend_ip_phone_mode;
-extern struct pmx_mode spear300_hend_ip_phone_mode;
-extern struct pmx_mode spear300_lend_wifi_phone_mode;
-extern struct pmx_mode spear300_hend_wifi_phone_mode;
-extern struct pmx_mode spear300_ata_pabx_wi2s_mode;
-extern struct pmx_mode spear300_ata_pabx_i2s_mode;
-extern struct pmx_mode spear300_caml_lcdw_mode;
-extern struct pmx_mode spear300_camu_lcd_mode;
-extern struct pmx_mode spear300_camu_wlcd_mode;
-extern struct pmx_mode spear300_caml_lcd_mode;
-
-/* pad mux devices */
-extern struct pmx_dev spear300_pmx_fsmc_2_chips;
-extern struct pmx_dev spear300_pmx_fsmc_4_chips;
-extern struct pmx_dev spear300_pmx_keyboard;
-extern struct pmx_dev spear300_pmx_clcd;
-extern struct pmx_dev spear300_pmx_telecom_gpio;
-extern struct pmx_dev spear300_pmx_telecom_tdm;
-extern struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk;
-extern struct pmx_dev spear300_pmx_telecom_camera;
-extern struct pmx_dev spear300_pmx_telecom_dac;
-extern struct pmx_dev spear300_pmx_telecom_i2s;
-extern struct pmx_dev spear300_pmx_telecom_boot_pins;
-extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit;
-extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit;
-extern struct pmx_dev spear300_pmx_gpio1;
-
-/* Add spear300 machine function declarations here */
-void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-                u8 pmx_dev_count);
+void __init spear300_clk_init(void);
 
 #endif /* CONFIG_MACH_SPEAR300 */
 
 /* spear310 declarations */
 #ifdef CONFIG_MACH_SPEAR310
-/* Add spear310 machine device structure declarations here */
-
-/* pad mux devices */
-extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5;
-extern struct pmx_dev spear310_pmx_emi_cs_2_3;
-extern struct pmx_dev spear310_pmx_uart1;
-extern struct pmx_dev spear310_pmx_uart2;
-extern struct pmx_dev spear310_pmx_uart3_4_5;
-extern struct pmx_dev spear310_pmx_fsmc;
-extern struct pmx_dev spear310_pmx_rs485_0_1;
-extern struct pmx_dev spear310_pmx_tdm0;
-
-/* Add spear310 machine function declarations here */
-void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-                u8 pmx_dev_count);
+void __init spear310_clk_init(void);
 
 #endif /* CONFIG_MACH_SPEAR310 */
 
 /* spear320 declarations */
 #ifdef CONFIG_MACH_SPEAR320
-/* Add spear320 machine device structure declarations here */
-
-/* pad mux modes */
-extern struct pmx_mode spear320_auto_net_smii_mode;
-extern struct pmx_mode spear320_auto_net_mii_mode;
-extern struct pmx_mode spear320_auto_exp_mode;
-extern struct pmx_mode spear320_small_printers_mode;
-
-/* pad mux devices */
-extern struct pmx_dev spear320_pmx_clcd;
-extern struct pmx_dev spear320_pmx_emi;
-extern struct pmx_dev spear320_pmx_fsmc;
-extern struct pmx_dev spear320_pmx_spp;
-extern struct pmx_dev spear320_pmx_sdhci;
-extern struct pmx_dev spear320_pmx_i2s;
-extern struct pmx_dev spear320_pmx_uart1;
-extern struct pmx_dev spear320_pmx_uart1_modem;
-extern struct pmx_dev spear320_pmx_uart2;
-extern struct pmx_dev spear320_pmx_touchscreen;
-extern struct pmx_dev spear320_pmx_can;
-extern struct pmx_dev spear320_pmx_sdhci_led;
-extern struct pmx_dev spear320_pmx_pwm0;
-extern struct pmx_dev spear320_pmx_pwm1;
-extern struct pmx_dev spear320_pmx_pwm2;
-extern struct pmx_dev spear320_pmx_pwm3;
-extern struct pmx_dev spear320_pmx_ssp1;
-extern struct pmx_dev spear320_pmx_ssp2;
-extern struct pmx_dev spear320_pmx_mii1;
-extern struct pmx_dev spear320_pmx_smii0;
-extern struct pmx_dev spear320_pmx_smii1;
-extern struct pmx_dev spear320_pmx_i2c1;
-
-/* Add spear320 machine function declarations here */
-void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-                u8 pmx_dev_count);
+void __init spear320_clk_init(void);
 
 #endif /* CONFIG_MACH_SPEAR320 */
 
diff --git a/arch/arm/mach-spear3xx/include/mach/hardware.h b/arch/arm/mach-spear3xx/include/mach/hardware.h
index 4660c0d8ec0d..defa374f5bee 100644
--- a/arch/arm/mach-spear3xx/include/mach/hardware.h
+++ b/arch/arm/mach-spear3xx/include/mach/hardware.h
@@ -17,7 +17,4 @@
 #include <plat/hardware.h>
 #include <mach/spear.h>
 
-/* Vitual to physical translation of statically mapped space */
-#define IO_ADDRESS(x)           (x | 0xF0000000)
-
 #endif /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h
index 63fd98356919..8e3900aa0d45 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear.h
@@ -25,8 +25,9 @@
 
 /* ICM1 - Low speed connection */
 #define SPEAR3XX_ICM1_2_BASE            UL(0xD0000000)
+#define VA_SPEAR3XX_ICM1_2_BASE         UL(0xFD000000)
 #define SPEAR3XX_ICM1_UART_BASE         UL(0xD0000000)
-#define VA_SPEAR3XX_ICM1_UART_BASE      IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE)
+#define VA_SPEAR3XX_ICM1_UART_BASE      (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE)
 #define SPEAR3XX_ICM1_ADC_BASE          UL(0xD0080000)
 #define SPEAR3XX_ICM1_SSP_BASE          UL(0xD0100000)
 #define SPEAR3XX_ICM1_I2C_BASE          UL(0xD0180000)
@@ -53,11 +54,11 @@
 #define SPEAR3XX_ICM3_ML1_2_BASE        UL(0xF0000000)
 #define SPEAR3XX_ML1_TMR_BASE           UL(0xF0000000)
 #define SPEAR3XX_ML1_VIC_BASE           UL(0xF1100000)
-#define VA_SPEAR3XX_ML1_VIC_BASE        IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE)
 
 /* ICM3 - Basic Subsystem */
 #define SPEAR3XX_ICM3_SMEM_BASE         UL(0xF8000000)
 #define SPEAR3XX_ICM3_SMI_CTRL_BASE     UL(0xFC000000)
+#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE  UL(0xFC000000)
 #define SPEAR3XX_ICM3_DMA_BASE          UL(0xFC400000)
 #define SPEAR3XX_ICM3_SDRAM_CTRL_BASE   UL(0xFC600000)
 #define SPEAR3XX_ICM3_TMR0_BASE         UL(0xFC800000)
@@ -65,9 +66,9 @@
 #define SPEAR3XX_ICM3_RTC_BASE          UL(0xFC900000)
 #define SPEAR3XX_ICM3_GPIO_BASE         UL(0xFC980000)
 #define SPEAR3XX_ICM3_SYS_CTRL_BASE     UL(0xFCA00000)
-#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE  IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE)
+#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE  (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE)
 #define SPEAR3XX_ICM3_MISC_REG_BASE     UL(0xFCA80000)
-#define VA_SPEAR3XX_ICM3_MISC_REG_BASE  IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE)
+#define VA_SPEAR3XX_ICM3_MISC_REG_BASE  (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE)
 #define SPEAR3XX_ICM3_TMR1_BASE         UL(0xFCB00000)
 
 /* Debug uart for linux, will be used for debug and uncompress messages */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index f7db66812abb..2db0bd14e481 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -3,373 +3,24 @@
  *
  * SPEAr300 machine source file
  *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
-#include <linux/types.h>
-#include <linux/amba/pl061.h>
-#include <linux/ptrace.h>
-#include <asm/irq.h>
+#define pr_fmt(fmt) "SPEAr300: " fmt
+
+#include <linux/amba/pl08x.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/vic.h>
+#include <asm/mach/arch.h>
 #include <plat/shirq.h>
 #include <mach/generic.h>
 #include <mach/hardware.h>
 
-/* pad multiplexing support */
-/* muxing registers */
-#define PAD_MUX_CONFIG_REG      0x00
-#define MODE_CONFIG_REG         0x04
-
-/* modes */
-#define NAND_MODE                       (1 << 0)
-#define NOR_MODE                        (1 << 1)
-#define PHOTO_FRAME_MODE                (1 << 2)
-#define LEND_IP_PHONE_MODE              (1 << 3)
-#define HEND_IP_PHONE_MODE              (1 << 4)
-#define LEND_WIFI_PHONE_MODE            (1 << 5)
-#define HEND_WIFI_PHONE_MODE            (1 << 6)
-#define ATA_PABX_WI2S_MODE              (1 << 7)
-#define ATA_PABX_I2S_MODE               (1 << 8)
-#define CAML_LCDW_MODE                  (1 << 9)
-#define CAMU_LCD_MODE                   (1 << 10)
-#define CAMU_WLCD_MODE                  (1 << 11)
-#define CAML_LCD_MODE                   (1 << 12)
-#define ALL_MODES                       0x1FFF
-
-struct pmx_mode spear300_nand_mode = {
-        .id = NAND_MODE,
-        .name = "nand mode",
-        .mask = 0x00,
-};
-
-struct pmx_mode spear300_nor_mode = {
-        .id = NOR_MODE,
-        .name = "nor mode",
-        .mask = 0x01,
-};
-
-struct pmx_mode spear300_photo_frame_mode = {
-        .id = PHOTO_FRAME_MODE,
-        .name = "photo frame mode",
-        .mask = 0x02,
-};
-
-struct pmx_mode spear300_lend_ip_phone_mode = {
-        .id = LEND_IP_PHONE_MODE,
-        .name = "lend ip phone mode",
-        .mask = 0x03,
-};
-
-struct pmx_mode spear300_hend_ip_phone_mode = {
-        .id = HEND_IP_PHONE_MODE,
-        .name = "hend ip phone mode",
-        .mask = 0x04,
-};
-
-struct pmx_mode spear300_lend_wifi_phone_mode = {
-        .id = LEND_WIFI_PHONE_MODE,
-        .name = "lend wifi phone mode",
-        .mask = 0x05,
-};
-
-struct pmx_mode spear300_hend_wifi_phone_mode = {
-        .id = HEND_WIFI_PHONE_MODE,
-        .name = "hend wifi phone mode",
-        .mask = 0x06,
-};
-
-struct pmx_mode spear300_ata_pabx_wi2s_mode = {
-        .id = ATA_PABX_WI2S_MODE,
-        .name = "ata pabx wi2s mode",
-        .mask = 0x07,
-};
-
-struct pmx_mode spear300_ata_pabx_i2s_mode = {
-        .id = ATA_PABX_I2S_MODE,
-        .name = "ata pabx i2s mode",
-        .mask = 0x08,
-};
-
-struct pmx_mode spear300_caml_lcdw_mode = {
-        .id = CAML_LCDW_MODE,
-        .name = "caml lcdw mode",
-        .mask = 0x0C,
-};
-
-struct pmx_mode spear300_camu_lcd_mode = {
-        .id = CAMU_LCD_MODE,
-        .name = "camu lcd mode",
-        .mask = 0x0D,
-};
-
-struct pmx_mode spear300_camu_wlcd_mode = {
-        .id = CAMU_WLCD_MODE,
-        .name = "camu wlcd mode",
-        .mask = 0x0E,
-};
-
-struct pmx_mode spear300_caml_lcd_mode = {
-        .id = CAML_LCD_MODE,
-        .name = "caml lcd mode",
-        .mask = 0x0F,
-};
-
-/* devices */
-static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
-        {
-                .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
-                        ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
-                .mask = PMX_FIRDA_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_fsmc_2_chips = {
-        .name = "fsmc_2_chips",
-        .modes = pmx_fsmc_2_chips_modes,
-        .mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
-        {
-                .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
-                        ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
-                .mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_fsmc_4_chips = {
-        .name = "fsmc_4_chips",
-        .modes = pmx_fsmc_4_chips_modes,
-        .mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_keyboard_modes[] = {
-        {
-                .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
-                        LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
-                        CAML_LCDW_MODE | CAMU_LCD_MODE | CAMU_WLCD_MODE |
-                        CAML_LCD_MODE,
-                .mask = 0x0,
-        },
-};
-
-struct pmx_dev spear300_pmx_keyboard = {
-        .name = "keyboard",
-        .modes = pmx_keyboard_modes,
-        .mode_count = ARRAY_SIZE(pmx_keyboard_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_clcd_modes[] = {
-        {
-                .ids = PHOTO_FRAME_MODE,
-                .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK ,
-        }, {
-                .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
-                        CAMU_LCD_MODE | CAML_LCD_MODE,
-                .mask = PMX_TIMER_3_4_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_clcd = {
-        .name = "clcd",
-        .modes = pmx_clcd_modes,
-        .mode_count = ARRAY_SIZE(pmx_clcd_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
-        {
-                .ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE,
-                .mask = PMX_MII_MASK,
-        }, {
-                .ids = LEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE,
-                .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
-        }, {
-                .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_WLCD_MODE,
-                .mask = PMX_MII_MASK | PMX_TIMER_3_4_MASK,
-        }, {
-                .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE,
-                .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK,
-        }, {
-                .ids = ATA_PABX_WI2S_MODE,
-                .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK
-                        | PMX_UART0_MODEM_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_telecom_gpio = {
-        .name = "telecom_gpio",
-        .modes = pmx_telecom_gpio_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
-        {
-                .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
-                        HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
-                        | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
-                        | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
-                        | CAMU_WLCD_MODE | CAML_LCD_MODE,
-                .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_telecom_tdm = {
-        .name = "telecom_tdm",
-        .modes = pmx_telecom_tdm_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
-        {
-                .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
-                        LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE
-                        | ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE |
-                        CAML_LCDW_MODE | CAML_LCD_MODE,
-                .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk = {
-        .name = "telecom_spi_cs_i2c_clk",
-        .modes = pmx_telecom_spi_cs_i2c_clk_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_camera_modes[] = {
-        {
-                .ids = CAML_LCDW_MODE | CAML_LCD_MODE,
-                .mask = PMX_MII_MASK,
-        }, {
-                .ids = CAMU_LCD_MODE | CAMU_WLCD_MODE,
-                .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_telecom_camera = {
-        .name = "telecom_camera",
-        .modes = pmx_telecom_camera_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_camera_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_dac_modes[] = {
-        {
-                .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
-                        | CAMU_WLCD_MODE | CAML_LCD_MODE,
-                .mask = PMX_TIMER_1_2_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_telecom_dac = {
-        .name = "telecom_dac",
-        .modes = pmx_telecom_dac_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_dac_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
-        {
-                .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
-                        | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
-                        ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
-                        | CAMU_WLCD_MODE | CAML_LCD_MODE,
-                .mask = PMX_UART0_MODEM_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_telecom_i2s = {
-        .name = "telecom_i2s",
-        .modes = pmx_telecom_i2s_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
-        {
-                .ids = NAND_MODE | NOR_MODE,
-                .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
-                        PMX_TIMER_3_4_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_telecom_boot_pins = {
-        .name = "telecom_boot_pins",
-        .modes = pmx_telecom_boot_pins_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = {
-        {
-                .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
-                        HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
-                        HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
-                        CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE |
-                        ATA_PABX_I2S_MODE,
-                .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
-                        PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
-                        PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_telecom_sdhci_4bit = {
-        .name = "telecom_sdhci_4bit",
-        .modes = pmx_telecom_sdhci_4bit_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = {
-        {
-                .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
-                        HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
-                        HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
-                        CAMU_WLCD_MODE | CAML_LCD_MODE,
-                .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
-                        PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
-                        PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_telecom_sdhci_8bit = {
-        .name = "telecom_sdhci_8bit",
-        .modes = pmx_telecom_sdhci_8bit_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_gpio1_modes[] = {
-        {
-                .ids = PHOTO_FRAME_MODE,
-                .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
-                        PMX_TIMER_3_4_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_gpio1 = {
-        .name = "arm gpio1",
-        .modes = pmx_gpio1_modes,
-        .mode_count = ARRAY_SIZE(pmx_gpio1_modes),
-        .enb_on_reset = 1,
-};
-
-/* pmx driver structure */
-static struct pmx_driver pmx_driver = {
-        .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f},
-        .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
-};
-
 /* spear3xx shared irq */
 static struct shirq_dev_config shirq_ras1_config[] = {
         {
@@ -423,45 +74,239 @@ static struct spear_shirq shirq_ras1 = {
         },
 };
 
-/* Add spear300 specific devices here */
-/* arm gpio1 device registration */
-static struct pl061_platform_data gpio1_plat_data = {
-        .gpio_base      = 8,
-        .irq_base       = SPEAR300_GPIO1_INT_BASE,
+/* DMAC platform data's slave info */
+struct pl08x_channel_data spear300_dma_info[] = {
+        {
+                .bus_id = "uart0_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart0_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "irda",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "adc",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "to_jpeg",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "from_jpeg",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras0_rx",
+                .min_signal = 0,
+                .max_signal = 0,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras0_tx",
+                .min_signal = 1,
+                .max_signal = 1,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras1_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras1_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras2_rx",
+                .min_signal = 4,
+                .max_signal = 4,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras2_tx",
+                .min_signal = 5,
+                .max_signal = 5,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras3_rx",
+                .min_signal = 6,
+                .max_signal = 6,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras3_tx",
+                .min_signal = 7,
+                .max_signal = 7,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras4_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras4_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras5_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras5_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras6_rx",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras6_tx",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras7_rx",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras7_tx",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        },
 };
 
-AMBA_APB_DEVICE(spear300_gpio1, "gpio1", 0, SPEAR300_GPIO_BASE,
-        {SPEAR300_VIRQ_GPIO1}, &gpio1_plat_data);
+/* Add SPEAr300 auxdata to pass platform data */
+static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
+                        &pl022_plat_data),
+        OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+                        &pl080_plat_data),
+        {}
+};
 
-/* spear300 routines */
-void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-                u8 pmx_dev_count)
+static void __init spear300_dt_init(void)
 {
-        int ret = 0;
+        int ret;
+
+        pl080_plat_data.slave_channels = spear300_dma_info;
+        pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info);
 
-        /* call spear3xx family common init function */
-        spear3xx_init();
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        spear300_auxdata_lookup, NULL);
 
         /* shared irq registration */
         shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K);
         if (shirq_ras1.regs.base) {
                 ret = spear_shirq_register(&shirq_ras1);
                 if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ\n");
+                        pr_err("Error registering Shared IRQ\n");
         }
+}
 
-        /* pmx initialization */
-        pmx_driver.mode = pmx_mode;
-        pmx_driver.devs = pmx_devs;
-        pmx_driver.devs_count = pmx_dev_count;
+static const char * const spear300_dt_board_compat[] = {
+        "st,spear300",
+        "st,spear300-evb",
+        NULL,
+};
 
-        pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K);
-        if (pmx_driver.base) {
-                ret = pmx_register(&pmx_driver);
-                if (ret)
-                        printk(KERN_ERR "padmux: registration failed. err no"
-                                        ": %d\n", ret);
-                /* Free Mapping, device selection already done */
-                iounmap(pmx_driver.base);
-        }
+static void __init spear300_map_io(void)
+{
+        spear3xx_map_io();
+        spear300_clk_init();
 }
+
+DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree")
+        .map_io         =       spear300_map_io,
+        .init_irq       =       spear3xx_dt_init_irq,
+        .handle_irq     =       vic_handle_irq,
+        .timer          =       &spear3xx_timer,
+        .init_machine   =       spear300_dt_init,
+        .restart        =       spear_restart,
+        .dt_compat      =       spear300_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
deleted file mode 100644
index 3462ab9d6122..000000000000
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/spear300_evb.c
- *
- * SPEAr300 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* padmux devices to enable */
-static struct pmx_dev *pmx_devs[] = {
-        /* spear3xx specific devices */
-        &spear3xx_pmx_i2c,
-        &spear3xx_pmx_ssp_cs,
-        &spear3xx_pmx_ssp,
-        &spear3xx_pmx_mii,
-        &spear3xx_pmx_uart0,
-
-        /* spear300 specific devices */
-        &spear300_pmx_fsmc_2_chips,
-        &spear300_pmx_clcd,
-        &spear300_pmx_telecom_sdhci_4bit,
-        &spear300_pmx_gpio1,
-};
-
-static struct amba_device *amba_devs[] __initdata = {
-        /* spear3xx specific devices */
-        &spear3xx_gpio_device,
-        &spear3xx_uart_device,
-
-        /* spear300 specific devices */
-        &spear300_gpio1_device,
-};
-
-static struct platform_device *plat_devs[] __initdata = {
-        /* spear3xx specific devices */
-
-        /* spear300 specific devices */
-};
-
-static void __init spear300_evb_init(void)
-{
-        unsigned int i;
-
-        /* call spear300 machine init function */
-        spear300_init(&spear300_photo_frame_mode, pmx_devs,
-                        ARRAY_SIZE(pmx_devs));
-
-        /* Add Platform Devices */
-        platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-
-        /* Add Amba Devices */
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-                amba_device_register(amba_devs[i], &iomem_resource);
-}
-
-MACHINE_START(SPEAR300, "ST-SPEAR300-EVB")
-        .atag_offset    =       0x100,
-        .map_io         =       spear3xx_map_io,
-        .init_irq       =       spear3xx_init_irq,
-        .handle_irq     =       vic_handle_irq,
-        .timer          =       &spear3xx_timer,
-        .init_machine   =       spear300_evb_init,
-        .restart        =       spear_restart,
-MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index febaa6fcfb6a..aec07c951205 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -3,142 +3,25 @@
  *
  * SPEAr310 machine source file
  *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
-#include <linux/ptrace.h>
-#include <asm/irq.h>
+#define pr_fmt(fmt) "SPEAr310: " fmt
+
+#include <linux/amba/pl08x.h>
+#include <linux/amba/serial.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/vic.h>
+#include <asm/mach/arch.h>
 #include <plat/shirq.h>
 #include <mach/generic.h>
 #include <mach/hardware.h>
 
-/* pad multiplexing support */
-/* muxing registers */
-#define PAD_MUX_CONFIG_REG      0x08
-
-/* devices */
-static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_TIMER_3_4_MASK,
-        },
-};
-
-struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = {
-        .name = "emi_cs_0_1_4_5",
-        .modes = pmx_emi_cs_0_1_4_5_modes,
-        .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_TIMER_1_2_MASK,
-        },
-};
-
-struct pmx_dev spear310_pmx_emi_cs_2_3 = {
-        .name = "emi_cs_2_3",
-        .modes = pmx_emi_cs_2_3_modes,
-        .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_uart1_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_FIRDA_MASK,
-        },
-};
-
-struct pmx_dev spear310_pmx_uart1 = {
-        .name = "uart1",
-        .modes = pmx_uart1_modes,
-        .mode_count = ARRAY_SIZE(pmx_uart1_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_uart2_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_TIMER_1_2_MASK,
-        },
-};
-
-struct pmx_dev spear310_pmx_uart2 = {
-        .name = "uart2",
-        .modes = pmx_uart2_modes,
-        .mode_count = ARRAY_SIZE(pmx_uart2_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_UART0_MODEM_MASK,
-        },
-};
-
-struct pmx_dev spear310_pmx_uart3_4_5 = {
-        .name = "uart3_4_5",
-        .modes = pmx_uart3_4_5_modes,
-        .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_fsmc_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_SSP_CS_MASK,
-        },
-};
-
-struct pmx_dev spear310_pmx_fsmc = {
-        .name = "fsmc",
-        .modes = pmx_fsmc_modes,
-        .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear310_pmx_rs485_0_1 = {
-        .name = "rs485_0_1",
-        .modes = pmx_rs485_0_1_modes,
-        .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_tdm0_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear310_pmx_tdm0 = {
-        .name = "tdm0",
-        .modes = pmx_tdm0_modes,
-        .mode_count = ARRAY_SIZE(pmx_tdm0_modes),
-        .enb_on_reset = 1,
-};
-
-/* pmx driver structure */
-static struct pmx_driver pmx_driver = {
-        .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
-};
-
 /* spear3xx shared irq */
 static struct shirq_dev_config shirq_ras1_config[] = {
         {
@@ -255,17 +138,247 @@ static struct spear_shirq shirq_intrcomm_ras = {
         },
 };
 
-/* Add spear310 specific devices here */
+/* DMAC platform data's slave info */
+struct pl08x_channel_data spear310_dma_info[] = {
+        {
+                .bus_id = "uart0_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart0_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "irda",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "adc",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "to_jpeg",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "from_jpeg",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart1_rx",
+                .min_signal = 0,
+                .max_signal = 0,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart1_tx",
+                .min_signal = 1,
+                .max_signal = 1,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart2_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart2_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart3_rx",
+                .min_signal = 4,
+                .max_signal = 4,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart3_tx",
+                .min_signal = 5,
+                .max_signal = 5,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart4_rx",
+                .min_signal = 6,
+                .max_signal = 6,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart4_tx",
+                .min_signal = 7,
+                .max_signal = 7,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart5_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart5_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras5_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras5_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras6_rx",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras6_tx",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras7_rx",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras7_tx",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        },
+};
 
-/* spear310 routines */
-void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-                u8 pmx_dev_count)
+/* uart devices plat data */
+static struct amba_pl011_data spear310_uart_data[] = {
+        {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart1_tx",
+                .dma_rx_param = "uart1_rx",
+        }, {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart2_tx",
+                .dma_rx_param = "uart2_rx",
+        }, {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart3_tx",
+                .dma_rx_param = "uart3_rx",
+        }, {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart4_tx",
+                .dma_rx_param = "uart4_rx",
+        }, {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart5_tx",
+                .dma_rx_param = "uart5_rx",
+        },
+};
+
+/* Add SPEAr310 auxdata to pass platform data */
+static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
+                        &pl022_plat_data),
+        OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+                        &pl080_plat_data),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL,
+                        &spear310_uart_data[0]),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL,
+                        &spear310_uart_data[1]),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART3_BASE, NULL,
+                        &spear310_uart_data[2]),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART4_BASE, NULL,
+                        &spear310_uart_data[3]),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART5_BASE, NULL,
+                        &spear310_uart_data[4]),
+        {}
+};
+
+static void __init spear310_dt_init(void)
 {
         void __iomem *base;
-        int ret = 0;
+        int ret;
 
-        /* call spear3xx family common init function */
-        spear3xx_init();
+        pl080_plat_data.slave_channels = spear310_dma_info;
+        pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info);
+
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        spear310_auxdata_lookup, NULL);
 
         /* shared irq registration */
         base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K);
@@ -274,35 +387,46 @@ void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
                 shirq_ras1.regs.base = base;
                 ret = spear_shirq_register(&shirq_ras1);
                 if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 1\n");
+                        pr_err("Error registering Shared IRQ 1\n");
 
                 /* shirq 2 */
                 shirq_ras2.regs.base = base;
                 ret = spear_shirq_register(&shirq_ras2);
                 if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 2\n");
+                        pr_err("Error registering Shared IRQ 2\n");
 
                 /* shirq 3 */
                 shirq_ras3.regs.base = base;
                 ret = spear_shirq_register(&shirq_ras3);
                 if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 3\n");
+                        pr_err("Error registering Shared IRQ 3\n");
 
                 /* shirq 4 */
                 shirq_intrcomm_ras.regs.base = base;
                 ret = spear_shirq_register(&shirq_intrcomm_ras);
                 if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 4\n");
+                        pr_err("Error registering Shared IRQ 4\n");
         }
+}
 
-        /* pmx initialization */
-        pmx_driver.base = base;
-        pmx_driver.mode = pmx_mode;
-        pmx_driver.devs = pmx_devs;
-        pmx_driver.devs_count = pmx_dev_count;
+static const char * const spear310_dt_board_compat[] = {
+        "st,spear310",
+        "st,spear310-evb",
+        NULL,
+};
 
-        ret = pmx_register(&pmx_driver);
-        if (ret)
-                printk(KERN_ERR "padmux: registration failed. err no: %d\n",
-                                ret);
+static void __init spear310_map_io(void)
+{
+        spear3xx_map_io();
+        spear310_clk_init();
 }
+
+DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree")
+        .map_io         =       spear310_map_io,
+        .init_irq       =       spear3xx_dt_init_irq,
+        .handle_irq     =       vic_handle_irq,
+        .timer          =       &spear3xx_timer,
+        .init_machine   =       spear310_dt_init,
+        .restart        =       spear_restart,
+        .dt_compat      =       spear310_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
deleted file mode 100644
index f92c4993f65a..000000000000
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/spear310_evb.c
- *
- * SPEAr310 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* padmux devices to enable */
-static struct pmx_dev *pmx_devs[] = {
-        /* spear3xx specific devices */
-        &spear3xx_pmx_i2c,
-        &spear3xx_pmx_ssp,
-        &spear3xx_pmx_gpio_pin0,
-        &spear3xx_pmx_gpio_pin1,
-        &spear3xx_pmx_gpio_pin2,
-        &spear3xx_pmx_gpio_pin3,
-        &spear3xx_pmx_gpio_pin4,
-        &spear3xx_pmx_gpio_pin5,
-        &spear3xx_pmx_uart0,
-
-        /* spear310 specific devices */
-        &spear310_pmx_emi_cs_0_1_4_5,
-        &spear310_pmx_emi_cs_2_3,
-        &spear310_pmx_uart1,
-        &spear310_pmx_uart2,
-        &spear310_pmx_uart3_4_5,
-        &spear310_pmx_fsmc,
-        &spear310_pmx_rs485_0_1,
-        &spear310_pmx_tdm0,
-};
-
-static struct amba_device *amba_devs[] __initdata = {
-        /* spear3xx specific devices */
-        &spear3xx_gpio_device,
-        &spear3xx_uart_device,
-
-        /* spear310 specific devices */
-};
-
-static struct platform_device *plat_devs[] __initdata = {
-        /* spear3xx specific devices */
-
-        /* spear310 specific devices */
-};
-
-static void __init spear310_evb_init(void)
-{
-        unsigned int i;
-
-        /* call spear310 machine init function */
-        spear310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs));
-
-        /* Add Platform Devices */
-        platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-
-        /* Add Amba Devices */
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-                amba_device_register(amba_devs[i], &iomem_resource);
-}
-
-MACHINE_START(SPEAR310, "ST-SPEAR310-EVB")
-        .atag_offset    =       0x100,
-        .map_io         =       spear3xx_map_io,
-        .init_irq       =       spear3xx_init_irq,
-        .handle_irq     =       vic_handle_irq,
-        .timer          =       &spear3xx_timer,
-        .init_machine   =       spear310_evb_init,
-        .restart        =       spear_restart,
-MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index deaaf199612c..4812c692ca35 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -3,387 +3,26 @@
  *
  * SPEAr320 machine source file
  *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
-#include <linux/ptrace.h>
-#include <asm/irq.h>
+#define pr_fmt(fmt) "SPEAr320: " fmt
+
+#include <linux/amba/pl022.h>
+#include <linux/amba/pl08x.h>
+#include <linux/amba/serial.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/vic.h>
+#include <asm/mach/arch.h>
 #include <plat/shirq.h>
 #include <mach/generic.h>
 #include <mach/hardware.h>
 
-/* pad multiplexing support */
-/* muxing registers */
-#define PAD_MUX_CONFIG_REG      0x0C
-#define MODE_CONFIG_REG         0x10
-
-/* modes */
-#define AUTO_NET_SMII_MODE      (1 << 0)
-#define AUTO_NET_MII_MODE       (1 << 1)
-#define AUTO_EXP_MODE           (1 << 2)
-#define SMALL_PRINTERS_MODE     (1 << 3)
-#define ALL_MODES               0xF
-
-struct pmx_mode spear320_auto_net_smii_mode = {
-        .id = AUTO_NET_SMII_MODE,
-        .name = "Automation Networking SMII Mode",
-        .mask = 0x00,
-};
-
-struct pmx_mode spear320_auto_net_mii_mode = {
-        .id = AUTO_NET_MII_MODE,
-        .name = "Automation Networking MII Mode",
-        .mask = 0x01,
-};
-
-struct pmx_mode spear320_auto_exp_mode = {
-        .id = AUTO_EXP_MODE,
-        .name = "Automation Expanded Mode",
-        .mask = 0x02,
-};
-
-struct pmx_mode spear320_small_printers_mode = {
-        .id = SMALL_PRINTERS_MODE,
-        .name = "Small Printers Mode",
-        .mask = 0x03,
-};
-
-/* devices */
-static struct pmx_dev_mode pmx_clcd_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE,
-                .mask = 0x0,
-        },
-};
-
-struct pmx_dev spear320_pmx_clcd = {
-        .name = "clcd",
-        .modes = pmx_clcd_modes,
-        .mode_count = ARRAY_SIZE(pmx_clcd_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_emi_modes[] = {
-        {
-                .ids = AUTO_EXP_MODE,
-                .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_emi = {
-        .name = "emi",
-        .modes = pmx_emi_modes,
-        .mode_count = ARRAY_SIZE(pmx_emi_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_fsmc_modes[] = {
-        {
-                .ids = ALL_MODES,
-                .mask = 0x0,
-        },
-};
-
-struct pmx_dev spear320_pmx_fsmc = {
-        .name = "fsmc",
-        .modes = pmx_fsmc_modes,
-        .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_spp_modes[] = {
-        {
-                .ids = SMALL_PRINTERS_MODE,
-                .mask = 0x0,
-        },
-};
-
-struct pmx_dev spear320_pmx_spp = {
-        .name = "spp",
-        .modes = pmx_spp_modes,
-        .mode_count = ARRAY_SIZE(pmx_spp_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_sdhci_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
-                        SMALL_PRINTERS_MODE,
-                .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_sdhci = {
-        .name = "sdhci",
-        .modes = pmx_sdhci_modes,
-        .mode_count = ARRAY_SIZE(pmx_sdhci_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_i2s_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
-                .mask = PMX_UART0_MODEM_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_i2s = {
-        .name = "i2s",
-        .modes = pmx_i2s_modes,
-        .mode_count = ARRAY_SIZE(pmx_i2s_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_uart1_modes[] = {
-        {
-                .ids = ALL_MODES,
-                .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_uart1 = {
-        .name = "uart1",
-        .modes = pmx_uart1_modes,
-        .mode_count = ARRAY_SIZE(pmx_uart1_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
-        {
-                .ids = AUTO_EXP_MODE,
-                .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
-                        PMX_SSP_CS_MASK,
-        }, {
-                .ids = SMALL_PRINTERS_MODE,
-                .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
-                        PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_uart1_modem = {
-        .name = "uart1_modem",
-        .modes = pmx_uart1_modem_modes,
-        .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_uart2_modes[] = {
-        {
-                .ids = ALL_MODES,
-                .mask = PMX_FIRDA_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_uart2 = {
-        .name = "uart2",
-        .modes = pmx_uart2_modes,
-        .mode_count = ARRAY_SIZE(pmx_uart2_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_touchscreen_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE,
-                .mask = PMX_SSP_CS_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_touchscreen = {
-        .name = "touchscreen",
-        .modes = pmx_touchscreen_modes,
-        .mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_can_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
-                .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
-                        PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_can = {
-        .name = "can",
-        .modes = pmx_can_modes,
-        .mode_count = ARRAY_SIZE(pmx_can_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_sdhci_led_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
-                .mask = PMX_SSP_CS_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_sdhci_led = {
-        .name = "sdhci_led",
-        .modes = pmx_sdhci_led_modes,
-        .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_pwm0_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
-                .mask = PMX_UART0_MODEM_MASK,
-        }, {
-                .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_pwm0 = {
-        .name = "pwm0",
-        .modes = pmx_pwm0_modes,
-        .mode_count = ARRAY_SIZE(pmx_pwm0_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_pwm1_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
-                .mask = PMX_UART0_MODEM_MASK,
-        }, {
-                .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_pwm1 = {
-        .name = "pwm1",
-        .modes = pmx_pwm1_modes,
-        .mode_count = ARRAY_SIZE(pmx_pwm1_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_pwm2_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
-                .mask = PMX_SSP_CS_MASK,
-        }, {
-                .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_pwm2 = {
-        .name = "pwm2",
-        .modes = pmx_pwm2_modes,
-        .mode_count = ARRAY_SIZE(pmx_pwm2_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_pwm3_modes[] = {
-        {
-                .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_pwm3 = {
-        .name = "pwm3",
-        .modes = pmx_pwm3_modes,
-        .mode_count = ARRAY_SIZE(pmx_pwm3_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_ssp1_modes[] = {
-        {
-                .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_ssp1 = {
-        .name = "ssp1",
-        .modes = pmx_ssp1_modes,
-        .mode_count = ARRAY_SIZE(pmx_ssp1_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_ssp2_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_ssp2 = {
-        .name = "ssp2",
-        .modes = pmx_ssp2_modes,
-        .mode_count = ARRAY_SIZE(pmx_ssp2_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_mii1_modes[] = {
-        {
-                .ids = AUTO_NET_MII_MODE,
-                .mask = 0x0,
-        },
-};
-
-struct pmx_dev spear320_pmx_mii1 = {
-        .name = "mii1",
-        .modes = pmx_mii1_modes,
-        .mode_count = ARRAY_SIZE(pmx_mii1_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_smii0_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_smii0 = {
-        .name = "smii0",
-        .modes = pmx_smii0_modes,
-        .mode_count = ARRAY_SIZE(pmx_smii0_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_smii1_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_smii1 = {
-        .name = "smii1",
-        .modes = pmx_smii1_modes,
-        .mode_count = ARRAY_SIZE(pmx_smii1_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_i2c1_modes[] = {
-        {
-                .ids = AUTO_EXP_MODE,
-                .mask = 0x0,
-        },
-};
-
-struct pmx_dev spear320_pmx_i2c1 = {
-        .name = "i2c1",
-        .modes = pmx_i2c1_modes,
-        .mode_count = ARRAY_SIZE(pmx_i2c1_modes),
-        .enb_on_reset = 1,
-};
-
-/* pmx driver structure */
-static struct pmx_driver pmx_driver = {
-        .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
-        .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
-};
-
 /* spear3xx shared irq */
 static struct shirq_dev_config shirq_ras1_config[] = {
         {
@@ -508,17 +147,250 @@ static struct spear_shirq shirq_intrcomm_ras = {
         },
 };
 
-/* Add spear320 specific devices here */
+/* DMAC platform data's slave info */
+struct pl08x_channel_data spear320_dma_info[] = {
+        {
+                .bus_id = "uart0_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart0_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c0_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c0_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "irda",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "adc",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "to_jpeg",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "from_jpeg",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp1_rx",
+                .min_signal = 0,
+                .max_signal = 0,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ssp1_tx",
+                .min_signal = 1,
+                .max_signal = 1,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ssp2_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ssp2_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "uart1_rx",
+                .min_signal = 4,
+                .max_signal = 4,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "uart1_tx",
+                .min_signal = 5,
+                .max_signal = 5,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "uart2_rx",
+                .min_signal = 6,
+                .max_signal = 6,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "uart2_tx",
+                .min_signal = 7,
+                .max_signal = 7,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2c1_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2c1_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2c2_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2c2_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2s_rx",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2s_tx",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "rs485_rx",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "rs485_tx",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        },
+};
+
+static struct pl022_ssp_controller spear320_ssp_data[] = {
+        {
+                .bus_id = 1,
+                .enable_dma = 1,
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "ssp1_tx",
+                .dma_rx_param = "ssp1_rx",
+                .num_chipselect = 2,
+        }, {
+                .bus_id = 2,
+                .enable_dma = 1,
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "ssp2_tx",
+                .dma_rx_param = "ssp2_rx",
+                .num_chipselect = 2,
+        }
+};
+
+static struct amba_pl011_data spear320_uart_data[] = {
+        {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart1_tx",
+                .dma_rx_param = "uart1_rx",
+        }, {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart2_tx",
+                .dma_rx_param = "uart2_rx",
+        },
+};
 
-/* spear320 routines */
-void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-                u8 pmx_dev_count)
+/* Add SPEAr310 auxdata to pass platform data */
+static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
+                        &pl022_plat_data),
+        OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+                        &pl080_plat_data),
+        OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
+                        &spear320_ssp_data[0]),
+        OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL,
+                        &spear320_ssp_data[1]),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL,
+                        &spear320_uart_data[0]),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL,
+                        &spear320_uart_data[1]),
+        {}
+};
+
+static void __init spear320_dt_init(void)
 {
         void __iomem *base;
-        int ret = 0;
+        int ret;
+
+        pl080_plat_data.slave_channels = spear320_dma_info;
+        pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
 
-        /* call spear3xx family common init function */
-        spear3xx_init();
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        spear320_auxdata_lookup, NULL);
 
         /* shared irq registration */
         base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
@@ -527,29 +399,40 @@ void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
                 shirq_ras1.regs.base = base;
                 ret = spear_shirq_register(&shirq_ras1);
                 if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 1\n");
+                        pr_err("Error registering Shared IRQ 1\n");
 
                 /* shirq 3 */
                 shirq_ras3.regs.base = base;
                 ret = spear_shirq_register(&shirq_ras3);
                 if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 3\n");
+                        pr_err("Error registering Shared IRQ 3\n");
 
                 /* shirq 4 */
                 shirq_intrcomm_ras.regs.base = base;
                 ret = spear_shirq_register(&shirq_intrcomm_ras);
                 if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 4\n");
+                        pr_err("Error registering Shared IRQ 4\n");
         }
+}
 
-        /* pmx initialization */
-        pmx_driver.base = base;
-        pmx_driver.mode = pmx_mode;
-        pmx_driver.devs = pmx_devs;
-        pmx_driver.devs_count = pmx_dev_count;
+static const char * const spear320_dt_board_compat[] = {
+        "st,spear320",
+        "st,spear320-evb",
+        NULL,
+};
 
-        ret = pmx_register(&pmx_driver);
-        if (ret)
-                printk(KERN_ERR "padmux: registration failed. err no: %d\n",
-                                ret);
+static void __init spear320_map_io(void)
+{
+        spear3xx_map_io();
+        spear320_clk_init();
 }
+
+DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
+        .map_io         =       spear320_map_io,
+        .init_irq       =       spear3xx_dt_init_irq,
+        .handle_irq     =       vic_handle_irq,
+        .timer          =       &spear3xx_timer,
+        .init_machine   =       spear320_dt_init,
+        .restart        =       spear_restart,
+        .dt_compat      =       spear320_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
deleted file mode 100644
index 105334ab7021..000000000000
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/spear320_evb.c
- *
- * SPEAr320 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* padmux devices to enable */
-static struct pmx_dev *pmx_devs[] = {
-        /* spear3xx specific devices */
-        &spear3xx_pmx_i2c,
-        &spear3xx_pmx_ssp,
-        &spear3xx_pmx_mii,
-        &spear3xx_pmx_uart0,
-
-        /* spear320 specific devices */
-        &spear320_pmx_fsmc,
-        &spear320_pmx_sdhci,
-        &spear320_pmx_i2s,
-        &spear320_pmx_uart1,
-        &spear320_pmx_uart2,
-        &spear320_pmx_can,
-        &spear320_pmx_pwm0,
-        &spear320_pmx_pwm1,
-        &spear320_pmx_pwm2,
-        &spear320_pmx_mii1,
-};
-
-static struct amba_device *amba_devs[] __initdata = {
-        /* spear3xx specific devices */
-        &spear3xx_gpio_device,
-        &spear3xx_uart_device,
-
-        /* spear320 specific devices */
-};
-
-static struct platform_device *plat_devs[] __initdata = {
-        /* spear3xx specific devices */
-
-        /* spear320 specific devices */
-};
-
-static void __init spear320_evb_init(void)
-{
-        unsigned int i;
-
-        /* call spear320 machine init function */
-        spear320_init(&spear320_auto_net_mii_mode, pmx_devs,
-                        ARRAY_SIZE(pmx_devs));
-
-        /* Add Platform Devices */
-        platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-
-        /* Add Amba Devices */
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-                amba_device_register(amba_devs[i], &iomem_resource);
-}
-
-MACHINE_START(SPEAR320, "ST-SPEAR320-EVB")
-        .atag_offset    =       0x100,
-        .map_io         =       spear3xx_map_io,
-        .init_irq       =       spear3xx_init_irq,
-        .handle_irq     =       vic_handle_irq,
-        .timer          =       &spear3xx_timer,
-        .init_machine   =       spear320_evb_init,
-        .restart        =       spear_restart,
-MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index b1733c37f209..12bf879a9ef1 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -3,71 +3,78 @@
  *
  * SPEAr3XX machines common source file
  *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
-#include <linux/types.h>
-#include <linux/amba/pl061.h>
-#include <linux/ptrace.h>
+#define pr_fmt(fmt) "SPEAr3xx: " fmt
+
+#include <linux/amba/pl022.h>
+#include <linux/amba/pl08x.h>
+#include <linux/of_irq.h>
 #include <linux/io.h>
+#include <asm/hardware/pl080.h>
 #include <asm/hardware/vic.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
+#include <plat/pl080.h>
 #include <mach/generic.h>
 #include <mach/hardware.h>
 
-/* Add spear3xx machines common devices here */
-/* gpio device registration */
-static struct pl061_platform_data gpio_plat_data = {
-        .gpio_base      = 0,
-        .irq_base       = SPEAR3XX_GPIO_INT_BASE,
+/* ssp device registration */
+struct pl022_ssp_controller pl022_plat_data = {
+        .bus_id = 0,
+        .enable_dma = 1,
+        .dma_filter = pl08x_filter_id,
+        .dma_tx_param = "ssp0_tx",
+        .dma_rx_param = "ssp0_rx",
+        /*
+         * This is number of spi devices that can be connected to spi. There are
+         * two type of chipselects on which slave devices can work. One is chip
+         * select provided by spi masters other is controlled through external
+         * gpio's. We can't use chipselect provided from spi master (because as
+         * soon as FIFO becomes empty, CS is disabled and transfer ends). So
+         * this number now depends on number of gpios available for spi. each
+         * slave on each master requires a separate gpio pin.
+         */
+        .num_chipselect = 2,
+};
+
+/* dmac device registration */
+struct pl08x_platform_data pl080_plat_data = {
+        .memcpy_channel = {
+                .bus_id = "memcpy",
+                .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
+                        PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
+                        PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
+                        PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
+                        PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
+                        PL080_CONTROL_PROT_SYS),
+        },
+        .lli_buses = PL08X_AHB1,
+        .mem_buses = PL08X_AHB1,
+        .get_signal = pl080_get_signal,
+        .put_signal = pl080_put_signal,
 };
 
-AMBA_APB_DEVICE(spear3xx_gpio, "gpio", 0, SPEAR3XX_ICM3_GPIO_BASE,
-        {SPEAR3XX_IRQ_BASIC_GPIO}, &gpio_plat_data);
-
-/* uart device registration */
-AMBA_APB_DEVICE(spear3xx_uart, "uart", 0, SPEAR3XX_ICM1_UART_BASE,
-        {SPEAR3XX_IRQ_UART}, NULL);
-
-/* Do spear3xx familiy common initialization part here */
-void __init spear3xx_init(void)
-{
-        /* nothing to do for now */
-}
-
-/* This will initialize vic */
-void __init spear3xx_init_irq(void)
-{
-        vic_init((void __iomem *)VA_SPEAR3XX_ML1_VIC_BASE, 0, ~0, 0);
-}
-
-/* Following will create static virtual/physical mappings */
+/*
+ * Following will create 16MB static virtual/physical mappings
+ * PHYSICAL             VIRTUAL
+ * 0xD0000000           0xFD000000
+ * 0xFC000000           0xFC000000
+ */
 struct map_desc spear3xx_io_desc[] __initdata = {
         {
-                .virtual        = VA_SPEAR3XX_ICM1_UART_BASE,
-                .pfn            = __phys_to_pfn(SPEAR3XX_ICM1_UART_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
-        }, {
-                .virtual        = VA_SPEAR3XX_ML1_VIC_BASE,
-                .pfn            = __phys_to_pfn(SPEAR3XX_ML1_VIC_BASE),
-                .length         = SZ_4K,
+                .virtual        = VA_SPEAR3XX_ICM1_2_BASE,
+                .pfn            = __phys_to_pfn(SPEAR3XX_ICM1_2_BASE),
+                .length         = SZ_16M,
                 .type           = MT_DEVICE
         }, {
-                .virtual        = VA_SPEAR3XX_ICM3_SYS_CTRL_BASE,
-                .pfn            = __phys_to_pfn(SPEAR3XX_ICM3_SYS_CTRL_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
-        }, {
-                .virtual        = VA_SPEAR3XX_ICM3_MISC_REG_BASE,
-                .pfn            = __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE),
-                .length         = SZ_4K,
+                .virtual        = VA_SPEAR3XX_ICM3_SMI_CTRL_BASE,
+                .pfn            = __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE),
+                .length         = SZ_16M,
                 .type           = MT_DEVICE
         },
 };
@@ -76,436 +83,8 @@ struct map_desc spear3xx_io_desc[] __initdata = {
 void __init spear3xx_map_io(void)
 {
         iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
-
-        /* This will initialize clock framework */
-        spear3xx_clk_init();
 }
 
-/* pad multiplexing support */
-/* devices */
-static struct pmx_dev_mode pmx_firda_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_FIRDA_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_firda = {
-        .name = "firda",
-        .modes = pmx_firda_modes,
-        .mode_count = ARRAY_SIZE(pmx_firda_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_i2c_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_I2C_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_i2c = {
-        .name = "i2c",
-        .modes = pmx_i2c_modes,
-        .mode_count = ARRAY_SIZE(pmx_i2c_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_ssp_cs_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_SSP_CS_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_ssp_cs = {
-        .name = "ssp_chip_selects",
-        .modes = pmx_ssp_cs_modes,
-        .mode_count = ARRAY_SIZE(pmx_ssp_cs_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_ssp_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_SSP_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_ssp = {
-        .name = "ssp",
-        .modes = pmx_ssp_modes,
-        .mode_count = ARRAY_SIZE(pmx_ssp_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_mii_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_mii = {
-        .name = "mii",
-        .modes = pmx_mii_modes,
-        .mode_count = ARRAY_SIZE(pmx_mii_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_GPIO_PIN0_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_gpio_pin0 = {
-        .name = "gpio_pin0",
-        .modes = pmx_gpio_pin0_modes,
-        .mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_GPIO_PIN1_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_gpio_pin1 = {
-        .name = "gpio_pin1",
-        .modes = pmx_gpio_pin1_modes,
-        .mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_GPIO_PIN2_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_gpio_pin2 = {
-        .name = "gpio_pin2",
-        .modes = pmx_gpio_pin2_modes,
-        .mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_GPIO_PIN3_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_gpio_pin3 = {
-        .name = "gpio_pin3",
-        .modes = pmx_gpio_pin3_modes,
-        .mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_GPIO_PIN4_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_gpio_pin4 = {
-        .name = "gpio_pin4",
-        .modes = pmx_gpio_pin4_modes,
-        .mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_GPIO_PIN5_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_gpio_pin5 = {
-        .name = "gpio_pin5",
-        .modes = pmx_gpio_pin5_modes,
-        .mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_uart0_modem_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_UART0_MODEM_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_uart0_modem = {
-        .name = "uart0_modem",
-        .modes = pmx_uart0_modem_modes,
-        .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_uart0_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_UART0_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_uart0 = {
-        .name = "uart0",
-        .modes = pmx_uart0_modes,
-        .mode_count = ARRAY_SIZE(pmx_uart0_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_timer_3_4_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_TIMER_3_4_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_timer_3_4 = {
-        .name = "timer_3_4",
-        .modes = pmx_timer_3_4_modes,
-        .mode_count = ARRAY_SIZE(pmx_timer_3_4_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_timer_1_2_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_TIMER_1_2_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_timer_1_2 = {
-        .name = "timer_1_2",
-        .modes = pmx_timer_1_2_modes,
-        .mode_count = ARRAY_SIZE(pmx_timer_1_2_modes),
-        .enb_on_reset = 0,
-};
-
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
-/* plgpios devices */
-static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_FIRDA_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_0_1 = {
-        .name = "plgpio 0 and 1",
-        .modes = pmx_plgpio_0_1_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_UART0_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_2_3 = {
-        .name = "plgpio 2 and 3",
-        .modes = pmx_plgpio_2_3_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_I2C_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_4_5 = {
-        .name = "plgpio 4 and 5",
-        .modes = pmx_plgpio_4_5_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_SSP_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_6_9 = {
-        .name = "plgpio 6 to 9",
-        .modes = pmx_plgpio_6_9_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_10_27 = {
-        .name = "plgpio 10 to 27",
-        .modes = pmx_plgpio_10_27_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_28_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_GPIO_PIN0_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_28 = {
-        .name = "plgpio 28",
-        .modes = pmx_plgpio_28_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_28_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_29_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_GPIO_PIN1_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_29 = {
-        .name = "plgpio 29",
-        .modes = pmx_plgpio_29_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_29_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_30_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_GPIO_PIN2_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_30 = {
-        .name = "plgpio 30",
-        .modes = pmx_plgpio_30_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_30_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_31_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_GPIO_PIN3_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_31 = {
-        .name = "plgpio 31",
-        .modes = pmx_plgpio_31_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_31_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_32_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_GPIO_PIN4_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_32 = {
-        .name = "plgpio 32",
-        .modes = pmx_plgpio_32_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_32_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_33_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_GPIO_PIN5_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_33 = {
-        .name = "plgpio 33",
-        .modes = pmx_plgpio_33_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_33_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_SSP_CS_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_34_36 = {
-        .name = "plgpio 34 to 36",
-        .modes = pmx_plgpio_34_36_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_UART0_MODEM_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_37_42 = {
-        .name = "plgpio 37 to 42",
-        .modes = pmx_plgpio_37_42_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_TIMER_1_2_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = {
-        .name = "plgpio 43, 44, 47 and 48",
-        .modes = pmx_plgpio_43_44_47_48_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_TIMER_3_4_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = {
-        .name = "plgpio 45, 46, 49 and 50",
-        .modes = pmx_plgpio_45_46_49_50_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
-        .enb_on_reset = 1,
-};
-#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
-
 static void __init spear3xx_timer_init(void)
 {
         char pclk_name[] = "pll3_48m_clk";
@@ -536,3 +115,13 @@ static void __init spear3xx_timer_init(void)
 struct sys_timer spear3xx_timer = {
         .init = spear3xx_timer_init,
 };
+
+static const struct of_device_id vic_of_match[] __initconst = {
+        { .compatible = "arm,pl190-vic", .data = vic_of_init, },
+        { /* Sentinel */ }
+};
+
+void __init spear3xx_dt_init_irq(void)
+{
+        of_irq_init(vic_of_match);
+}
diff --git a/arch/arm/mach-spear6xx/Makefile.boot b/arch/arm/mach-spear6xx/Makefile.boot
index 4674a4c221db..af493da37ab6 100644
--- a/arch/arm/mach-spear6xx/Makefile.boot
+++ b/arch/arm/mach-spear6xx/Makefile.boot
@@ -1,3 +1,5 @@
 zreladdr-y      += 0x00008000
 params_phys-y   := 0x00000100
 initrd_phys-y   := 0x00800000
+
+dtb-$(CONFIG_BOARD_SPEAR600_DT) += spear600-evb.dtb
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
index a86499a8a15f..adadef2b27b4 100644
--- a/arch/arm/mach-spear6xx/clock.c
+++ b/arch/arm/mach-spear6xx/clock.c
@@ -623,53 +623,53 @@ static struct clk dummy_apb_pclk;
 
 /* array of all spear 6xx clock lookups */
 static struct clk_lookup spear_clk_lookups[] = {
-        { .con_id = "apb_pclk",         .clk = &dummy_apb_pclk},
+        CLKDEV_INIT(NULL, "apb_pclk", &dummy_apb_pclk),
         /* root clks */
-        { .con_id = "osc_32k_clk",      .clk = &osc_32k_clk},
-        { .con_id = "osc_30m_clk",      .clk = &osc_30m_clk},
+        CLKDEV_INIT(NULL, "osc_32k_clk", &osc_32k_clk),
+        CLKDEV_INIT(NULL, "osc_30m_clk", &osc_30m_clk),
         /* clock derived from 32 KHz os          clk */
-        { .dev_id = "rtc-spear",        .clk = &rtc_clk},
+        CLKDEV_INIT("rtc-spear", NULL, &rtc_clk),
         /* clock derived from 30 MHz os          clk */
-        { .con_id = "pll1_clk",         .clk = &pll1_clk},
-        { .con_id = "pll3_48m_clk",     .clk = &pll3_48m_clk},
-        { .dev_id = "wdt",              .clk = &wdt_clk},
+        CLKDEV_INIT(NULL, "pll1_clk", &pll1_clk),
+        CLKDEV_INIT(NULL, "pll3_48m_clk", &pll3_48m_clk),
+        CLKDEV_INIT("wdt", NULL, &wdt_clk),
         /* clock derived from pll1 clk */
-        { .con_id = "cpu_clk",          .clk = &cpu_clk},
-        { .con_id = "ahb_clk",          .clk = &ahb_clk},
-        { .con_id = "uart_synth_clk",   .clk = &uart_synth_clk},
-        { .con_id = "firda_synth_clk",  .clk = &firda_synth_clk},
-        { .con_id = "clcd_synth_clk",   .clk = &clcd_synth_clk},
-        { .con_id = "gpt0_synth_clk",   .clk = &gpt0_synth_clk},
-        { .con_id = "gpt2_synth_clk",   .clk = &gpt2_synth_clk},
-        { .con_id = "gpt3_synth_clk",   .clk = &gpt3_synth_clk},
-        { .dev_id = "d0000000.serial",  .clk = &uart0_clk},
-        { .dev_id = "d0080000.serial",  .clk = &uart1_clk},
-        { .dev_id = "firda",            .clk = &firda_clk},
-        { .dev_id = "clcd",             .clk = &clcd_clk},
-        { .dev_id = "gpt0",             .clk = &gpt0_clk},
-        { .dev_id = "gpt1",             .clk = &gpt1_clk},
-        { .dev_id = "gpt2",             .clk = &gpt2_clk},
-        { .dev_id = "gpt3",             .clk = &gpt3_clk},
+        CLKDEV_INIT(NULL, "cpu_clk", &cpu_clk),
+        CLKDEV_INIT(NULL, "ahb_clk", &ahb_clk),
+        CLKDEV_INIT(NULL, "uart_synth_clk", &uart_synth_clk),
+        CLKDEV_INIT(NULL, "firda_synth_clk", &firda_synth_clk),
+        CLKDEV_INIT(NULL, "clcd_synth_clk", &clcd_synth_clk),
+        CLKDEV_INIT(NULL, "gpt0_synth_clk", &gpt0_synth_clk),
+        CLKDEV_INIT(NULL, "gpt2_synth_clk", &gpt2_synth_clk),
+        CLKDEV_INIT(NULL, "gpt3_synth_clk", &gpt3_synth_clk),
+        CLKDEV_INIT("d0000000.serial", NULL, &uart0_clk),
+        CLKDEV_INIT("d0080000.serial", NULL, &uart1_clk),
+        CLKDEV_INIT("firda", NULL, &firda_clk),
+        CLKDEV_INIT("clcd", NULL, &clcd_clk),
+        CLKDEV_INIT("gpt0", NULL, &gpt0_clk),
+        CLKDEV_INIT("gpt1", NULL, &gpt1_clk),
+        CLKDEV_INIT("gpt2", NULL, &gpt2_clk),
+        CLKDEV_INIT("gpt3", NULL, &gpt3_clk),
         /* clock derived from pll3 clk */
-        { .dev_id = "designware_udc",   .clk = &usbd_clk},
-        { .con_id = "usbh.0_clk",       .clk = &usbh0_clk},
-        { .con_id = "usbh.1_clk",       .clk = &usbh1_clk},
+        CLKDEV_INIT("designware_udc", NULL, &usbd_clk),
+        CLKDEV_INIT(NULL, "usbh.0_clk", &usbh0_clk),
+        CLKDEV_INIT(NULL, "usbh.1_clk", &usbh1_clk),
         /* clock derived from ahb clk */
-        { .con_id = "apb_clk",          .clk = &apb_clk},
-        { .dev_id = "d0200000.i2c",     .clk = &i2c_clk},
-        { .dev_id = "dma",              .clk = &dma_clk},
-        { .dev_id = "jpeg",             .clk = &jpeg_clk},
-        { .dev_id = "gmac",             .clk = &gmac_clk},
-        { .dev_id = "smi",              .clk = &smi_clk},
-        { .dev_id = "fsmc-nand",        .clk = &fsmc_clk},
+        CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
+        CLKDEV_INIT("d0200000.i2c", NULL, &i2c_clk),
+        CLKDEV_INIT("fc400000.dma", NULL, &dma_clk),
+        CLKDEV_INIT("jpeg", NULL, &jpeg_clk),
+        CLKDEV_INIT("gmac", NULL, &gmac_clk),
+        CLKDEV_INIT("fc000000.flash", NULL, &smi_clk),
+        CLKDEV_INIT("d1800000.flash", NULL, &fsmc_clk),
         /* clock derived from apb clk */
-        { .dev_id = "adc",              .clk = &adc_clk},
-        { .dev_id = "ssp-pl022.0",      .clk = &ssp0_clk},
-        { .dev_id = "ssp-pl022.1",      .clk = &ssp1_clk},
-        { .dev_id = "ssp-pl022.2",      .clk = &ssp2_clk},
-        { .dev_id = "f0100000.gpio",    .clk = &gpio0_clk},
-        { .dev_id = "fc980000.gpio",    .clk = &gpio1_clk},
-        { .dev_id = "d8100000.gpio",    .clk = &gpio2_clk},
+        CLKDEV_INIT("adc", NULL, &adc_clk),
+        CLKDEV_INIT("ssp-pl022.0", NULL, &ssp0_clk),
+        CLKDEV_INIT("ssp-pl022.1", NULL, &ssp1_clk),
+        CLKDEV_INIT("ssp-pl022.2", NULL, &ssp2_clk),
+        CLKDEV_INIT("f0100000.gpio", NULL, &gpio0_clk),
+        CLKDEV_INIT("fc980000.gpio", NULL, &gpio1_clk),
+        CLKDEV_INIT("d8100000.gpio", NULL, &gpio2_clk),
 };
 
 void __init spear6xx_clk_init(void)
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 2ed8b14c82c8..5b9e30f54cdb 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -13,15 +13,377 @@
  * warranty of any kind, whether express or implied.
  */
 
+#include <linux/amba/pl08x.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <asm/hardware/pl080.h>
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
+#include <plat/pl080.h>
 #include <mach/generic.h>
 #include <mach/hardware.h>
 
+/* dmac device registration */
+static struct pl08x_channel_data spear600_dma_info[] = {
+        {
+                .bus_id = "ssp1_rx",
+                .min_signal = 0,
+                .max_signal = 0,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp1_tx",
+                .min_signal = 1,
+                .max_signal = 1,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart0_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart0_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart1_rx",
+                .min_signal = 4,
+                .max_signal = 4,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart1_tx",
+                .min_signal = 5,
+                .max_signal = 5,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp2_rx",
+                .min_signal = 6,
+                .max_signal = 6,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ssp2_tx",
+                .min_signal = 7,
+                .max_signal = 7,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ssp0_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "irda",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "adc",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "to_jpeg",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "from_jpeg",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras0_rx",
+                .min_signal = 0,
+                .max_signal = 0,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras0_tx",
+                .min_signal = 1,
+                .max_signal = 1,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras1_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras1_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras2_rx",
+                .min_signal = 4,
+                .max_signal = 4,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras2_tx",
+                .min_signal = 5,
+                .max_signal = 5,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras3_rx",
+                .min_signal = 6,
+                .max_signal = 6,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras3_tx",
+                .min_signal = 7,
+                .max_signal = 7,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras4_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras4_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras5_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras5_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras6_rx",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras6_tx",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras7_rx",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras7_tx",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ext0_rx",
+                .min_signal = 0,
+                .max_signal = 0,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext0_tx",
+                .min_signal = 1,
+                .max_signal = 1,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext1_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext1_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext2_rx",
+                .min_signal = 4,
+                .max_signal = 4,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext2_tx",
+                .min_signal = 5,
+                .max_signal = 5,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext3_rx",
+                .min_signal = 6,
+                .max_signal = 6,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext3_tx",
+                .min_signal = 7,
+                .max_signal = 7,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext4_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext4_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext5_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext5_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext6_rx",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext6_tx",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext7_rx",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext7_tx",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        },
+};
+
+struct pl08x_platform_data pl080_plat_data = {
+        .memcpy_channel = {
+                .bus_id = "memcpy",
+                .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
+                        PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
+                        PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
+                        PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
+                        PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
+                        PL080_CONTROL_PROT_SYS),
+        },
+        .lli_buses = PL08X_AHB1,
+        .mem_buses = PL08X_AHB1,
+        .get_signal = pl080_get_signal,
+        .put_signal = pl080_put_signal,
+        .slave_channels = spear600_dma_info,
+        .num_slave_channels = ARRAY_SIZE(spear600_dma_info),
+};
+
 /* Following will create static virtual/physical mappings */
 static struct map_desc spear6xx_io_desc[] __initdata = {
         {
@@ -92,9 +454,17 @@ struct sys_timer spear6xx_timer = {
         .init = spear6xx_timer_init,
 };
 
+/* Add auxdata to pass platform data */
+struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL,
+                        &pl080_plat_data),
+        {}
+};
+
 static void __init spear600_dt_init(void)
 {
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        spear6xx_auxdata_lookup, NULL);
 }
 
 static const char *spear600_dt_board_compat[] = {
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index d87d968115ec..2eb4445ddb14 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -5,7 +5,6 @@ obj-y                                   += io.o
 obj-y                                   += irq.o
 obj-y                                   += clock.o
 obj-y                                   += timer.o
-obj-y                                   += pinmux.o
 obj-y                                   += fuse.o
 obj-y                                   += pmc.o
 obj-y                                   += flowctrl.o
@@ -14,8 +13,6 @@ obj-$(CONFIG_CPU_IDLE)			+= sleep.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += powergate.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_emc.o
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += pinmux-tegra20-tables.o
-obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += pinmux-tegra30-tables.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += board-dt-tegra30.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += tegra30_clocks.o
 obj-$(CONFIG_SMP)                       += platsmp.o headsmp.o
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index 0952494f481a..5b9d5f4c0686 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -47,15 +47,7 @@
 #include "clock.h"
 #include "devices.h"
 
-void harmony_pinmux_init(void);
-void paz00_pinmux_init(void);
-void seaboard_pinmux_init(void);
-void trimslice_pinmux_init(void);
-void ventana_pinmux_init(void);
-
 struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
-        OF_DEV_AUXDATA("nvidia,tegra20-pinmux", TEGRA_APB_MISC_BASE + 0x14, "tegra-pinmux", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-gpio", TEGRA_GPIO_BASE, "tegra-gpio", NULL),
         OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
         OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL),
         OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL),
@@ -95,33 +87,10 @@ static struct of_device_id tegra_dt_match_table[] __initdata = {
         {}
 };
 
-static struct {
-        char *machine;
-        void (*init)(void);
-} pinmux_configs[] = {
-        { "compulab,trimslice", trimslice_pinmux_init },
-        { "nvidia,harmony", harmony_pinmux_init },
-        { "compal,paz00", paz00_pinmux_init },
-        { "nvidia,seaboard", seaboard_pinmux_init },
-        { "nvidia,ventana", ventana_pinmux_init },
-};
-
 static void __init tegra_dt_init(void)
 {
-        int i;
-
         tegra_clk_init_from_table(tegra_dt_clk_init_table);
 
-        for (i = 0; i < ARRAY_SIZE(pinmux_configs); i++) {
-                if (of_machine_is_compatible(pinmux_configs[i].machine)) {
-                        pinmux_configs[i].init();
-                        break;
-                }
-        }
-
-        WARN(i == ARRAY_SIZE(pinmux_configs),
-                "Unknown platform! Pinmuxing not initialized\n");
-
         /*
          * Finished with the static registrations now; fill in the missing
          * devices
diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c
index 1af85bccc0f1..83d420fbc58c 100644
--- a/arch/arm/mach-tegra/board-harmony-pinmux.c
+++ b/arch/arm/mach-tegra/board-harmony-pinmux.c
@@ -2,6 +2,7 @@
  * arch/arm/mach-tegra/board-harmony-pinmux.c
  *
  * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -15,153 +16,138 @@
  */
 
 #include <linux/kernel.h>
-#include <linux/gpio.h>
-#include <linux/of.h>
 
-#include <mach/pinmux.h>
-#include <mach/pinmux-tegra20.h>
-
-#include "gpio-names.h"
 #include "board-harmony.h"
 #include "board-pinmux.h"
 
-static struct tegra_pingroup_config harmony_pinmux[] = {
-        {TEGRA_PINGROUP_ATA,   TEGRA_MUX_IDE,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_ATB,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_ATC,   TEGRA_MUX_NAND,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_ATD,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_ATE,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4,     TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_CRTP,  TEGRA_MUX_CRT,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_CSUS,  TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_DAP1,  TEGRA_MUX_DAP1,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DAP2,  TEGRA_MUX_DAP2,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_DAP3,  TEGRA_MUX_DAP3,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_DAP4,  TEGRA_MUX_DAP4,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_DDC,   TEGRA_MUX_I2C2,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DTA,   TEGRA_MUX_SDIO2,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DTB,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DTC,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_DTD,   TEGRA_MUX_SDIO2,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DTE,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_DTF,   TEGRA_MUX_I2C3,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_GMA,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GMB,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GMC,   TEGRA_MUX_UARTD,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GMD,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GME,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GPU,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_GPU7,  TEGRA_MUX_RTCK,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GPV,   TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_I2CP,  TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_IRRX,  TEGRA_MUX_UARTA,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_IRTX,  TEGRA_MUX_UARTA,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_KBCA,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_KBCB,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_KBCC,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_KBCD,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_KBCE,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_KBCF,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LCSN,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LD0,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD1,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD10,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD11,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD12,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD13,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD14,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD15,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD16,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD17,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD2,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD3,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD4,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD5,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD6,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD7,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD8,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD9,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LDC,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LDI,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LHP0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LHP1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LHP2,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LHS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LM0,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LM1,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LPP,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LPW0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LPW1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LPW2,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LSC0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LSC1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LSCK,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LSDA,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LSDI,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LSPI,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LVP0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LVP1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LVS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_OWC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_PMC,   TEGRA_MUX_PWR_ON,        TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_PTA,   TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_RM,    TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SDB,   TEGRA_MUX_PWM,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SDC,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SDD,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SLXA,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SLXC,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SLXD,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SLXK,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SPDI,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPDO,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIA,  TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SPIB,  TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SPIC,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPID,  TEGRA_MUX_SPI1,          TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIE,  TEGRA_MUX_SPI1,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIF,  TEGRA_MUX_SPI1,          TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIG,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIH,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_UAA,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_UAB,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_UAC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_UAD,   TEGRA_MUX_IRDA,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_UCA,   TEGRA_MUX_UARTC,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_UCB,   TEGRA_MUX_UARTC,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_UDA,   TEGRA_MUX_ULPI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_CK32,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DDRC,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_PMCA,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_PMCB,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_PMCC,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_PMCD,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_PMCE,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_XM2C,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-};
-
-static struct tegra_gpio_table gpio_table[] = {
-        { .gpio = TEGRA_GPIO_SD2_CD,            .enable = true  },
-        { .gpio = TEGRA_GPIO_SD2_WP,            .enable = true  },
-        { .gpio = TEGRA_GPIO_SD2_POWER,         .enable = true  },
-        { .gpio = TEGRA_GPIO_SD4_CD,            .enable = true  },
-        { .gpio = TEGRA_GPIO_SD4_WP,            .enable = true  },
-        { .gpio = TEGRA_GPIO_SD4_POWER,         .enable = true  },
-        { .gpio = TEGRA_GPIO_CDC_IRQ,           .enable = true  },
-        { .gpio = TEGRA_GPIO_HP_DET,            .enable = true  },
-        { .gpio = TEGRA_GPIO_INT_MIC_EN,        .enable = true  },
-        { .gpio = TEGRA_GPIO_EXT_MIC_EN,        .enable = true  },
+static struct pinctrl_map harmony_map[] = {
+        TEGRA_MAP_MUXCONF("ata",   "ide",           none, driven),
+        TEGRA_MAP_MUXCONF("atb",   "sdio4",         none, driven),
+        TEGRA_MAP_MUXCONF("atc",   "nand",          none, driven),
+        TEGRA_MAP_MUXCONF("atd",   "gmi",           none, driven),
+        TEGRA_MAP_MUXCONF("ate",   "gmi",           none, driven),
+        TEGRA_MAP_MUXCONF("cdev1", "plla_out",      none, driven),
+        TEGRA_MAP_MUXCONF("cdev2", "pllp_out4",     down, tristate),
+        TEGRA_MAP_MUXCONF("crtp",  "crt",           none, tristate),
+        TEGRA_MAP_MUXCONF("csus",  "vi_sensor_clk", down, tristate),
+        TEGRA_MAP_MUXCONF("dap1",  "dap1",          none, driven),
+        TEGRA_MAP_MUXCONF("dap2",  "dap2",          none, tristate),
+        TEGRA_MAP_MUXCONF("dap3",  "dap3",          none, tristate),
+        TEGRA_MAP_MUXCONF("dap4",  "dap4",          none, tristate),
+        TEGRA_MAP_MUXCONF("ddc",   "i2c2",          up,   driven),
+        TEGRA_MAP_MUXCONF("dta",   "sdio2",         up,   driven),
+        TEGRA_MAP_MUXCONF("dtb",   "rsvd1",         none, driven),
+        TEGRA_MAP_MUXCONF("dtc",   "rsvd1",         none, tristate),
+        TEGRA_MAP_MUXCONF("dtd",   "sdio2",         up,   driven),
+        TEGRA_MAP_MUXCONF("dte",   "rsvd1",         none, tristate),
+        TEGRA_MAP_MUXCONF("dtf",   "i2c3",          none, tristate),
+        TEGRA_MAP_MUXCONF("gma",   "sdio4",         none, driven),
+        TEGRA_MAP_MUXCONF("gmb",   "gmi",           none, driven),
+        TEGRA_MAP_MUXCONF("gmc",   "uartd",         none, driven),
+        TEGRA_MAP_MUXCONF("gmd",   "gmi",           none, driven),
+        TEGRA_MAP_MUXCONF("gme",   "sdio4",         none, driven),
+        TEGRA_MAP_MUXCONF("gpu",   "gmi",           none, tristate),
+        TEGRA_MAP_MUXCONF("gpu7",  "rtck",          none, driven),
+        TEGRA_MAP_MUXCONF("gpv",   "pcie",          none, driven),
+        TEGRA_MAP_MUXCONF("hdint", "hdmi",          na,   tristate),
+        TEGRA_MAP_MUXCONF("i2cp",  "i2cp",          none, driven),
+        TEGRA_MAP_MUXCONF("irrx",  "uarta",         up,   tristate),
+        TEGRA_MAP_MUXCONF("irtx",  "uarta",         up,   tristate),
+        TEGRA_MAP_MUXCONF("kbca",  "kbc",           up,   driven),
+        TEGRA_MAP_MUXCONF("kbcb",  "kbc",           up,   driven),
+        TEGRA_MAP_MUXCONF("kbcc",  "kbc",           up,   driven),
+        TEGRA_MAP_MUXCONF("kbcd",  "kbc",           up,   driven),
+        TEGRA_MAP_MUXCONF("kbce",  "kbc",           up,   driven),
+        TEGRA_MAP_MUXCONF("kbcf",  "kbc",           up,   driven),
+        TEGRA_MAP_MUXCONF("lcsn",  "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("ld0",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld1",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld10",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld11",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld12",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld13",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld14",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld15",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld16",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld17",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld2",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld3",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld4",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld5",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld6",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld7",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld8",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld9",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ldc",   "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("ldi",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lhp0",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lhp1",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lhp2",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lhs",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lm0",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lm1",   "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("lpp",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lpw0",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lpw1",  "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("lpw2",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lsc0",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lsc1",  "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("lsck",  "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("lsda",  "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("lsdi",  "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("lspi",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lvp0",  "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("lvp1",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lvs",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("owc",   "rsvd2",         na,   tristate),
+        TEGRA_MAP_MUXCONF("pmc",   "pwr_on",        na,   driven),
+        TEGRA_MAP_MUXCONF("pta",   "hdmi",          none, driven),
+        TEGRA_MAP_MUXCONF("rm",    "i2c1",          none, driven),
+        TEGRA_MAP_MUXCONF("sdb",   "pwm",           na,   tristate),
+        TEGRA_MAP_MUXCONF("sdc",   "pwm",           up,   driven),
+        TEGRA_MAP_MUXCONF("sdd",   "pwm",           up,   tristate),
+        TEGRA_MAP_MUXCONF("sdio1", "sdio1",         none, tristate),
+        TEGRA_MAP_MUXCONF("slxa",  "pcie",          none, driven),
+        TEGRA_MAP_MUXCONF("slxc",  "spdif",         none, tristate),
+        TEGRA_MAP_MUXCONF("slxd",  "spdif",         none, tristate),
+        TEGRA_MAP_MUXCONF("slxk",  "pcie",          none, driven),
+        TEGRA_MAP_MUXCONF("spdi",  "rsvd2",         none, tristate),
+        TEGRA_MAP_MUXCONF("spdo",  "rsvd2",         none, tristate),
+        TEGRA_MAP_MUXCONF("spia",  "gmi",           none, driven),
+        TEGRA_MAP_MUXCONF("spib",  "gmi",           none, driven),
+        TEGRA_MAP_MUXCONF("spic",  "gmi",           up,   tristate),
+        TEGRA_MAP_MUXCONF("spid",  "spi1",          down, tristate),
+        TEGRA_MAP_MUXCONF("spie",  "spi1",          up,   tristate),
+        TEGRA_MAP_MUXCONF("spif",  "spi1",          down, tristate),
+        TEGRA_MAP_MUXCONF("spig",  "spi2_alt",      none, tristate),
+        TEGRA_MAP_MUXCONF("spih",  "spi2_alt",      up,   tristate),
+        TEGRA_MAP_MUXCONF("uaa",   "ulpi",          up,   tristate),
+        TEGRA_MAP_MUXCONF("uab",   "ulpi",          up,   tristate),
+        TEGRA_MAP_MUXCONF("uac",   "rsvd2",         none, tristate),
+        TEGRA_MAP_MUXCONF("uad",   "irda",          up,   tristate),
+        TEGRA_MAP_MUXCONF("uca",   "uartc",         up,   tristate),
+        TEGRA_MAP_MUXCONF("ucb",   "uartc",         up,   tristate),
+        TEGRA_MAP_MUXCONF("uda",   "ulpi",          none, tristate),
+        TEGRA_MAP_CONF("ck32",    none, na),
+        TEGRA_MAP_CONF("ddrc",    none, na),
+        TEGRA_MAP_CONF("pmca",    none, na),
+        TEGRA_MAP_CONF("pmcb",    none, na),
+        TEGRA_MAP_CONF("pmcc",    none, na),
+        TEGRA_MAP_CONF("pmcd",    none, na),
+        TEGRA_MAP_CONF("pmce",    none, na),
+        TEGRA_MAP_CONF("xm2c",    none, na),
+        TEGRA_MAP_CONF("xm2d",    none, na),
+        TEGRA_MAP_CONF("ls",      up,   na),
+        TEGRA_MAP_CONF("lc",      up,   na),
+        TEGRA_MAP_CONF("ld17_0",  down, na),
+        TEGRA_MAP_CONF("ld19_18", down, na),
+        TEGRA_MAP_CONF("ld21_20", down, na),
+        TEGRA_MAP_CONF("ld23_22", down, na),
 };
 
 static struct tegra_board_pinmux_conf conf = {
-        .pgs = harmony_pinmux,
-        .pg_count = ARRAY_SIZE(harmony_pinmux),
-        .gpios = gpio_table,
-        .gpio_count = ARRAY_SIZE(gpio_table),
+        .maps = harmony_map,
+        .map_count = ARRAY_SIZE(harmony_map),
 };
 
 void harmony_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-paz00-pinmux.c b/arch/arm/mach-tegra/board-paz00-pinmux.c
index c775572dcea4..6f1111b48e7c 100644
--- a/arch/arm/mach-tegra/board-paz00-pinmux.c
+++ b/arch/arm/mach-tegra/board-paz00-pinmux.c
@@ -2,6 +2,7 @@
  * arch/arm/mach-tegra/board-paz00-pinmux.c
  *
  * Copyright (C) 2010 Marc Dietrich <marvin24@gmx.de>
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -15,150 +16,138 @@
  */
 
 #include <linux/kernel.h>
-#include <linux/gpio.h>
-#include <linux/of.h>
 
-#include <mach/pinmux.h>
-#include <mach/pinmux-tegra20.h>
-
-#include "gpio-names.h"
 #include "board-paz00.h"
 #include "board-pinmux.h"
 
-static struct tegra_pingroup_config paz00_pinmux[] = {
-        {TEGRA_PINGROUP_ATA,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_ATB,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_ATC,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_ATD,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_ATE,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4,     TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_CRTP,  TEGRA_MUX_CRT,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_CSUS,  TEGRA_MUX_PLLC_OUT1,     TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_DAP1,  TEGRA_MUX_DAP1,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DAP2,  TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DAP3,  TEGRA_MUX_DAP3,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_DAP4,  TEGRA_MUX_DAP4,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_DDC,   TEGRA_MUX_I2C2,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DTA,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_DTB,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_DTC,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_DTD,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_DTE,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_DTF,   TEGRA_MUX_I2C3,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GMA,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GMB,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GMC,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GMD,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GME,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GPU,   TEGRA_MUX_PWM,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GPU7,  TEGRA_MUX_RTCK,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GPV,   TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_I2CP,  TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_IRRX,  TEGRA_MUX_UARTA,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_IRTX,  TEGRA_MUX_UARTA,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_KBCA,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_KBCB,  TEGRA_MUX_SDIO2,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_KBCC,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_KBCD,  TEGRA_MUX_SDIO2,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_KBCE,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_KBCF,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LCSN,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LD0,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD1,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD10,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD11,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD12,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD13,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD14,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD15,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD16,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD17,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD2,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD3,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD4,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD5,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD6,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD7,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD8,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD9,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LDC,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LDI,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LHP0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LHP1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LHP2,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LHS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LM0,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LM1,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LPP,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LPW0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LPW1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LPW2,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LSC0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LSC1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LSCK,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LSDA,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LSDI,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LSPI,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LVP0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LVP1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LVS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_OWC,   TEGRA_MUX_OWR,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_PMC,   TEGRA_MUX_PWR_ON,        TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_PTA,   TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_RM,    TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SDB,   TEGRA_MUX_PWM,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SDC,   TEGRA_MUX_TWC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SDD,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SLXA,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SLXC,  TEGRA_MUX_SPI4,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SLXD,  TEGRA_MUX_SPI4,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SLXK,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SPDI,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPDO,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SPIA,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIB,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIC,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SPID,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIE,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIF,  TEGRA_MUX_RSVD4,         TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIG,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SPIH,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_UAA,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_UAB,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_UAC,   TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_UAD,   TEGRA_MUX_SPDIF,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_UCA,   TEGRA_MUX_UARTC,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_UCB,   TEGRA_MUX_UARTC,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_UDA,   TEGRA_MUX_ULPI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_CK32,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DDRC,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_PMCA,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_PMCB,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_PMCC,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_PMCD,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_PMCE,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_XM2C,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-};
-
-static struct tegra_gpio_table gpio_table[] = {
-        { .gpio = TEGRA_GPIO_SD1_CD,    .enable = true },
-        { .gpio = TEGRA_GPIO_SD1_WP,    .enable = true },
-        { .gpio = TEGRA_GPIO_SD1_POWER, .enable = true },
-        { .gpio = TEGRA_ULPI_RST,       .enable = true },
-        { .gpio = TEGRA_WIFI_PWRN,      .enable = true },
-        { .gpio = TEGRA_WIFI_RST,       .enable = true },
-        { .gpio = TEGRA_WIFI_LED,       .enable = true },
+static struct pinctrl_map paz00_map[] = {
+        TEGRA_MAP_MUXCONF("ata",   "gmi",           none, driven),
+        TEGRA_MAP_MUXCONF("atb",   "sdio4",         none, driven),
+        TEGRA_MAP_MUXCONF("atc",   "gmi",           none, driven),
+        TEGRA_MAP_MUXCONF("atd",   "gmi",           none, driven),
+        TEGRA_MAP_MUXCONF("ate",   "gmi",           none, driven),
+        TEGRA_MAP_MUXCONF("cdev1", "plla_out",      none, driven),
+        TEGRA_MAP_MUXCONF("cdev2", "pllp_out4",     down, driven),
+        TEGRA_MAP_MUXCONF("crtp",  "crt",           none, tristate),
+        TEGRA_MAP_MUXCONF("csus",  "pllc_out1",     down, tristate),
+        TEGRA_MAP_MUXCONF("dap1",  "dap1",          none, driven),
+        TEGRA_MAP_MUXCONF("dap2",  "gmi",           none, driven),
+        TEGRA_MAP_MUXCONF("dap3",  "dap3",          none, tristate),
+        TEGRA_MAP_MUXCONF("dap4",  "dap4",          none, tristate),
+        TEGRA_MAP_MUXCONF("ddc",   "i2c2",          up,   driven),
+        TEGRA_MAP_MUXCONF("dta",   "rsvd1",         up,   tristate),
+        TEGRA_MAP_MUXCONF("dtb",   "rsvd1",         none, tristate),
+        TEGRA_MAP_MUXCONF("dtc",   "rsvd1",         none, tristate),
+        TEGRA_MAP_MUXCONF("dtd",   "rsvd1",         up,   tristate),
+        TEGRA_MAP_MUXCONF("dte",   "rsvd1",         none, tristate),
+        TEGRA_MAP_MUXCONF("dtf",   "i2c3",          none, driven),
+        TEGRA_MAP_MUXCONF("gma",   "sdio4",         none, driven),
+        TEGRA_MAP_MUXCONF("gmb",   "gmi",           none, driven),
+        TEGRA_MAP_MUXCONF("gmc",   "gmi",           none, driven),
+        TEGRA_MAP_MUXCONF("gmd",   "gmi",           none, driven),
+        TEGRA_MAP_MUXCONF("gme",   "sdio4",         none, driven),
+        TEGRA_MAP_MUXCONF("gpu",   "pwm",           none, driven),
+        TEGRA_MAP_MUXCONF("gpu7",  "rtck",          none, driven),
+        TEGRA_MAP_MUXCONF("gpv",   "pcie",          none, driven),
+        TEGRA_MAP_MUXCONF("hdint", "hdmi",          na,   driven),
+        TEGRA_MAP_MUXCONF("i2cp",  "i2cp",          none, driven),
+        TEGRA_MAP_MUXCONF("irrx",  "uarta",         up,   driven),
+        TEGRA_MAP_MUXCONF("irtx",  "uarta",         up,   driven),
+        TEGRA_MAP_MUXCONF("kbca",  "kbc",           up,   driven),
+        TEGRA_MAP_MUXCONF("kbcb",  "sdio2",         up,   driven),
+        TEGRA_MAP_MUXCONF("kbcc",  "kbc",           up,   driven),
+        TEGRA_MAP_MUXCONF("kbcd",  "sdio2",         up,   driven),
+        TEGRA_MAP_MUXCONF("kbce",  "kbc",           up,   driven),
+        TEGRA_MAP_MUXCONF("kbcf",  "kbc",           up,   driven),
+        TEGRA_MAP_MUXCONF("lcsn",  "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("ld0",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld1",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld10",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld11",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld12",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld13",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld14",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld15",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld16",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld17",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld2",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld3",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld4",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld5",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld6",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld7",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld8",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld9",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ldc",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ldi",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lhp0",  "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("lhp1",  "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("lhp2",  "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("lhs",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lm0",   "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("lm1",   "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("lpp",   "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("lpw0",  "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("lpw1",  "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("lpw2",  "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("lsc0",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lsc1",  "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("lsck",  "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("lsda",  "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("lsdi",  "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("lspi",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lvp0",  "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("lvp1",  "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("lvs",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("owc",   "owr",           up,   tristate),
+        TEGRA_MAP_MUXCONF("pmc",   "pwr_on",        na,   driven),
+        TEGRA_MAP_MUXCONF("pta",   "hdmi",          none, driven),
+        TEGRA_MAP_MUXCONF("rm",    "i2c1",          none, driven),
+        TEGRA_MAP_MUXCONF("sdb",   "pwm",           na,   tristate),
+        TEGRA_MAP_MUXCONF("sdc",   "twc",           up,   tristate),
+        TEGRA_MAP_MUXCONF("sdd",   "pwm",           up,   tristate),
+        TEGRA_MAP_MUXCONF("sdio1", "sdio1",         none, driven),
+        TEGRA_MAP_MUXCONF("slxa",  "pcie",          none, tristate),
+        TEGRA_MAP_MUXCONF("slxc",  "spi4",          none, tristate),
+        TEGRA_MAP_MUXCONF("slxd",  "spi4",          none, tristate),
+        TEGRA_MAP_MUXCONF("slxk",  "pcie",          none, driven),
+        TEGRA_MAP_MUXCONF("spdi",  "rsvd2",         none, tristate),
+        TEGRA_MAP_MUXCONF("spdo",  "rsvd2",         none, driven),
+        TEGRA_MAP_MUXCONF("spia",  "gmi",           down, tristate),
+        TEGRA_MAP_MUXCONF("spib",  "gmi",           down, tristate),
+        TEGRA_MAP_MUXCONF("spic",  "gmi",           up,   driven),
+        TEGRA_MAP_MUXCONF("spid",  "gmi",           down, tristate),
+        TEGRA_MAP_MUXCONF("spie",  "gmi",           up,   tristate),
+        TEGRA_MAP_MUXCONF("spif",  "rsvd4",         down, tristate),
+        TEGRA_MAP_MUXCONF("spig",  "spi2_alt",      up,   driven),
+        TEGRA_MAP_MUXCONF("spih",  "spi2_alt",      up,   tristate),
+        TEGRA_MAP_MUXCONF("uaa",   "ulpi",          up,   driven),
+        TEGRA_MAP_MUXCONF("uab",   "ulpi",          up,   driven),
+        TEGRA_MAP_MUXCONF("uac",   "rsvd4",         none, driven),
+        TEGRA_MAP_MUXCONF("uad",   "spdif",         up,   tristate),
+        TEGRA_MAP_MUXCONF("uca",   "uartc",         up,   tristate),
+        TEGRA_MAP_MUXCONF("ucb",   "uartc",         up,   tristate),
+        TEGRA_MAP_MUXCONF("uda",   "ulpi",          none, driven),
+        TEGRA_MAP_CONF("ck32",    none, na),
+        TEGRA_MAP_CONF("ddrc",    none, na),
+        TEGRA_MAP_CONF("pmca",    none, na),
+        TEGRA_MAP_CONF("pmcb",    none, na),
+        TEGRA_MAP_CONF("pmcc",    none, na),
+        TEGRA_MAP_CONF("pmcd",    none, na),
+        TEGRA_MAP_CONF("pmce",    none, na),
+        TEGRA_MAP_CONF("xm2c",    none, na),
+        TEGRA_MAP_CONF("xm2d",    none, na),
+        TEGRA_MAP_CONF("ls",      up,   na),
+        TEGRA_MAP_CONF("lc",      up,   na),
+        TEGRA_MAP_CONF("ld17_0",  down, na),
+        TEGRA_MAP_CONF("ld19_18", down, na),
+        TEGRA_MAP_CONF("ld21_20", down, na),
+        TEGRA_MAP_CONF("ld23_22", down, na),
 };
 
 static struct tegra_board_pinmux_conf conf = {
-        .pgs = paz00_pinmux,
-        .pg_count = ARRAY_SIZE(paz00_pinmux),
-        .gpios = gpio_table,
-        .gpio_count = ARRAY_SIZE(gpio_table),
+        .maps = paz00_map,
+        .map_count = ARRAY_SIZE(paz00_map),
 };
 
 void paz00_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-pinmux.c b/arch/arm/mach-tegra/board-pinmux.c
index adc3efe979b3..a5574c71b931 100644
--- a/arch/arm/mach-tegra/board-pinmux.c
+++ b/arch/arm/mach-tegra/board-pinmux.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011,2012, NVIDIA CORPORATION.  All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -15,75 +15,59 @@
 #include <linux/device.h>
 #include <linux/kernel.h>
 #include <linux/notifier.h>
-#include <linux/of.h>
 #include <linux/string.h>
 
-#include <mach/gpio-tegra.h>
-#include <mach/pinmux.h>
-
 #include "board-pinmux.h"
 #include "devices.h"
 
-struct tegra_board_pinmux_conf *confs[2];
-
-static void tegra_board_pinmux_setup_gpios(void)
-{
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(confs); i++) {
-                if (!confs[i])
-                        continue;
-
-                tegra_gpio_config(confs[i]->gpios, confs[i]->gpio_count);
-        }
-}
-
-static void tegra_board_pinmux_setup_pinmux(void)
-{
-        int i;
+unsigned long tegra_pincfg_pullnone_driven[2] = {
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
+};
 
-        for (i = 0; i < ARRAY_SIZE(confs); i++) {
-                if (!confs[i])
-                        continue;
+unsigned long tegra_pincfg_pullnone_tristate[2] = {
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
+};
 
-                tegra_pinmux_config_table(confs[i]->pgs, confs[i]->pg_count);
+unsigned long tegra_pincfg_pullnone_na[1] = {
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
+};
 
-                if (confs[i]->drives)
-                        tegra_drive_pinmux_config_table(confs[i]->drives,
-                                                        confs[i]->drive_count);
-        }
-}
+unsigned long tegra_pincfg_pullup_driven[2] = {
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
+};
 
-static int tegra_board_pinmux_bus_notify(struct notifier_block *nb,
-                                         unsigned long event, void *vdev)
-{
-        static bool had_gpio;
-        static bool had_pinmux;
+unsigned long tegra_pincfg_pullup_tristate[2] = {
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
+};
 
-        struct device *dev = vdev;
-        const char *devname;
+unsigned long tegra_pincfg_pullup_na[1] = {
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
+};
 
-        if (event != BUS_NOTIFY_BOUND_DRIVER)
-                return NOTIFY_DONE;
+unsigned long tegra_pincfg_pulldown_driven[2] = {
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
+};
 
-        devname = dev_name(dev);
+unsigned long tegra_pincfg_pulldown_tristate[2] = {
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
+};
 
-        if (!had_gpio && !strcmp(devname, GPIO_DEV)) {
-                tegra_board_pinmux_setup_gpios();
-                had_gpio = true;
-        } else if (!had_pinmux && !strcmp(devname, PINMUX_DEV)) {
-                tegra_board_pinmux_setup_pinmux();
-                had_pinmux = true;
-        }
+unsigned long tegra_pincfg_pulldown_na[1] = {
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
+};
 
-        if (had_gpio && had_pinmux)
-                return NOTIFY_STOP_MASK;
-        else
-                return NOTIFY_DONE;
-}
+unsigned long tegra_pincfg_pullna_driven[1] = {
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
+};
 
-static struct notifier_block nb = {
-        .notifier_call = tegra_board_pinmux_bus_notify,
+unsigned long tegra_pincfg_pullna_tristate[1] = {
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
 };
 
 static struct platform_device *devices[] = {
@@ -94,11 +78,10 @@ static struct platform_device *devices[] = {
 void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
                              struct tegra_board_pinmux_conf *conf_b)
 {
-        confs[0] = conf_a;
-        confs[1] = conf_b;
-
-        bus_register_notifier(&platform_bus_type, &nb);
+        if (conf_a)
+                pinctrl_register_mappings(conf_a->maps, conf_a->map_count);
+        if (conf_b)
+                pinctrl_register_mappings(conf_b->maps, conf_b->map_count);
 
-        if (!of_machine_is_compatible("nvidia,tegra20"))
-                platform_add_devices(devices, ARRAY_SIZE(devices));
+        platform_add_devices(devices, ARRAY_SIZE(devices));
 }
diff --git a/arch/arm/mach-tegra/board-pinmux.h b/arch/arm/mach-tegra/board-pinmux.h
index 4aac73546f54..c5f3f3381e86 100644
--- a/arch/arm/mach-tegra/board-pinmux.h
+++ b/arch/arm/mach-tegra/board-pinmux.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011,2012, NVIDIA CORPORATION.  All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -15,21 +15,37 @@
 #ifndef __MACH_TEGRA_BOARD_PINMUX_H
 #define __MACH_TEGRA_BOARD_PINMUX_H
 
-#define GPIO_DEV "tegra-gpio"
-#define PINMUX_DEV "tegra-pinmux"
+#include <linux/pinctrl/machine.h>
 
-struct tegra_pingroup_config;
-struct tegra_gpio_table;
+#include <mach/pinconf-tegra.h>
 
-struct tegra_board_pinmux_conf {
-        struct tegra_pingroup_config *pgs;
-        int pg_count;
+#define PINMUX_DEV "tegra20-pinctrl"
+
+#define TEGRA_MAP_MUX(_group_, _function_) \
+        PIN_MAP_MUX_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, _function_)
+
+#define TEGRA_MAP_CONF(_group_, _pull_, _drive_) \
+        PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, tegra_pincfg_pull##_pull_##_##_drive_)
 
-        struct tegra_drive_pingroup_config *drives;
-        int drive_count;
+#define TEGRA_MAP_MUXCONF(_group_, _function_, _pull_, _drive_) \
+        TEGRA_MAP_MUX(_group_, _function_), \
+        TEGRA_MAP_CONF(_group_, _pull_, _drive_)
 
-        struct tegra_gpio_table *gpios;
-        int gpio_count;
+extern unsigned long tegra_pincfg_pullnone_driven[2];
+extern unsigned long tegra_pincfg_pullnone_tristate[2];
+extern unsigned long tegra_pincfg_pullnone_na[1];
+extern unsigned long tegra_pincfg_pullup_driven[2];
+extern unsigned long tegra_pincfg_pullup_tristate[2];
+extern unsigned long tegra_pincfg_pullup_na[1];
+extern unsigned long tegra_pincfg_pulldown_driven[2];
+extern unsigned long tegra_pincfg_pulldown_tristate[2];
+extern unsigned long tegra_pincfg_pulldown_na[1];
+extern unsigned long tegra_pincfg_pullna_driven[1];
+extern unsigned long tegra_pincfg_pullna_tristate[1];
+
+struct tegra_board_pinmux_conf {
+        struct pinctrl_map *maps;
+        int map_count;
 };
 
 void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
diff --git a/arch/arm/mach-tegra/board-seaboard-pinmux.c b/arch/arm/mach-tegra/board-seaboard-pinmux.c
index 55e7e43a14ad..11fc8a568c64 100644
--- a/arch/arm/mach-tegra/board-seaboard-pinmux.c
+++ b/arch/arm/mach-tegra/board-seaboard-pinmux.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2010,2011 NVIDIA Corporation
+ * Copyright (C) 2010-2012 NVIDIA Corporation
  * Copyright (C) 2011 Google, Inc.
  *
  * This software is licensed under the terms of the GNU General Public
@@ -14,216 +14,176 @@
  */
 
 #include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/of.h>
 
-#include <mach/pinmux.h>
-#include <mach/pinmux-tegra20.h>
-
-#include "gpio-names.h"
-#include "board-pinmux.h"
 #include "board-seaboard.h"
+#include "board-pinmux.h"
 
-#define DEFAULT_DRIVE(_name)                                    \
-        {                                                       \
-                .pingroup = TEGRA_DRIVE_PINGROUP_##_name,       \
-                .hsm = TEGRA_HSM_DISABLE,                       \
-                .schmitt = TEGRA_SCHMITT_ENABLE,                \
-                .drive = TEGRA_DRIVE_DIV_1,                     \
-                .pull_down = TEGRA_PULL_31,                     \
-                .pull_up = TEGRA_PULL_31,                       \
-                .slew_rising = TEGRA_SLEW_SLOWEST,              \
-                .slew_falling = TEGRA_SLEW_SLOWEST,             \
-        }
-
-static struct tegra_drive_pingroup_config seaboard_drive_pinmux[] = {
-        DEFAULT_DRIVE(SDIO1),
-};
-
-static struct tegra_pingroup_config common_pinmux[] = {
-        {TEGRA_PINGROUP_ATA,   TEGRA_MUX_IDE,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_ATB,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_ATC,   TEGRA_MUX_NAND,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_ATD,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_ATE,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4,     TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_CRTP,  TEGRA_MUX_CRT,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_CSUS,  TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_DAP1,  TEGRA_MUX_DAP1,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DAP2,  TEGRA_MUX_DAP2,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DAP3,  TEGRA_MUX_DAP3,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_DAP4,  TEGRA_MUX_DAP4,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DTA,   TEGRA_MUX_VI,            TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DTB,   TEGRA_MUX_VI,            TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DTC,   TEGRA_MUX_VI,            TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DTD,   TEGRA_MUX_VI,            TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DTE,   TEGRA_MUX_VI,            TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_DTF,   TEGRA_MUX_I2C3,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GMA,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GMB,   TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_GMC,   TEGRA_MUX_UARTD,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GME,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GPU,   TEGRA_MUX_PWM,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GPU7,  TEGRA_MUX_RTCK,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GPV,   TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_I2CP,  TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_IRRX,  TEGRA_MUX_UARTB,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_IRTX,  TEGRA_MUX_UARTB,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_KBCA,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_KBCB,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_KBCC,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_KBCD,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_KBCE,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_KBCF,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LCSN,  TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LD0,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD1,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD10,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD11,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD12,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD13,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD14,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD15,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD16,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD17,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD2,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD3,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD4,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD5,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD6,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD7,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD8,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD9,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LDC,   TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LDI,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LHP0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LHP1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LHP2,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LHS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LM0,   TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LM1,   TEGRA_MUX_CRT,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LPP,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LPW1,  TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LSC0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LSDI,  TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LSPI,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LVP0,  TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LVP1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LVS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_OWC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_PMC,   TEGRA_MUX_PWR_ON,        TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_RM,    TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SDB,   TEGRA_MUX_SDIO3,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SDC,   TEGRA_MUX_SDIO3,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SDD,   TEGRA_MUX_SDIO3,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SLXA,  TEGRA_MUX_PCIE,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SLXD,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SPDI,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SPDO,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SPIB,  TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPID,  TEGRA_MUX_SPI1,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIE,  TEGRA_MUX_SPI1,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIF,  TEGRA_MUX_SPI1,          TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIH,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_UAA,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_UAB,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_UAC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_UAD,   TEGRA_MUX_IRDA,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_UCA,   TEGRA_MUX_UARTC,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_UCB,   TEGRA_MUX_UARTC,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_UDA,   TEGRA_MUX_ULPI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_CK32,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DDRC,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_PMCA,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_PMCB,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_PMCC,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_PMCD,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_PMCE,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_XM2C,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-};
-
-static struct tegra_pingroup_config seaboard_pinmux[] = {
-        {TEGRA_PINGROUP_DDC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_GMD,   TEGRA_MUX_SFLASH,        TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LPW0,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LPW2,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LSC1,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LSCK,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LSDA,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_PTA,   TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SLXC,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SLXK,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SPIA,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIC,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SPIG,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-};
-
-static struct tegra_pingroup_config ventana_pinmux[] = {
-        {TEGRA_PINGROUP_DDC,  TEGRA_MUX_RSVD2,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GMD,  TEGRA_MUX_SFLASH,   TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LPW0, TEGRA_MUX_RSVD4,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LPW2, TEGRA_MUX_RSVD4,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LSC1, TEGRA_MUX_RSVD4,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LSCK, TEGRA_MUX_RSVD4,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LSDA, TEGRA_MUX_RSVD4,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_PTA,  TEGRA_MUX_RSVD2,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SDIO3,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SLXK, TEGRA_MUX_SDIO3,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+static unsigned long seaboard_pincfg_drive_sdio1[] = {
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE, 0),
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SCHMITT, 0),
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_LOW_POWER_MODE, 3),
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH, 31),
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH, 31),
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING, 3),
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SLEW_RATE_RISING, 3),
 };
 
-static struct tegra_gpio_table common_gpio_table[] = {
-        { .gpio = TEGRA_GPIO_SD2_CD,            .enable = true },
-        { .gpio = TEGRA_GPIO_SD2_WP,            .enable = true },
-        { .gpio = TEGRA_GPIO_SD2_POWER,         .enable = true },
-        { .gpio = TEGRA_GPIO_CDC_IRQ,           .enable = true },
+static struct pinctrl_map common_map[] = {
+        TEGRA_MAP_MUXCONF("ata",   "ide",           none, driven),
+        TEGRA_MAP_MUXCONF("atb",   "sdio4",         none, driven),
+        TEGRA_MAP_MUXCONF("atc",   "nand",          none, driven),
+        TEGRA_MAP_MUXCONF("atd",   "gmi",           none, driven),
+        TEGRA_MAP_MUXCONF("ate",   "gmi",           none, tristate),
+        TEGRA_MAP_MUXCONF("cdev1", "plla_out",      none, driven),
+        TEGRA_MAP_MUXCONF("cdev2", "pllp_out4",     none, driven),
+        TEGRA_MAP_MUXCONF("crtp",  "crt",           up,   tristate),
+        TEGRA_MAP_MUXCONF("csus",  "vi_sensor_clk", none, tristate),
+        TEGRA_MAP_MUXCONF("dap1",  "dap1",          none, driven),
+        TEGRA_MAP_MUXCONF("dap2",  "dap2",          none, driven),
+        TEGRA_MAP_MUXCONF("dap3",  "dap3",          none, tristate),
+        TEGRA_MAP_MUXCONF("dap4",  "dap4",          none, driven),
+        TEGRA_MAP_MUXCONF("dta",   "vi",            down, driven),
+        TEGRA_MAP_MUXCONF("dtb",   "vi",            down, driven),
+        TEGRA_MAP_MUXCONF("dtc",   "vi",            down, driven),
+        TEGRA_MAP_MUXCONF("dtd",   "vi",            down, driven),
+        TEGRA_MAP_MUXCONF("dte",   "vi",            down, tristate),
+        TEGRA_MAP_MUXCONF("dtf",   "i2c3",          none, driven),
+        TEGRA_MAP_MUXCONF("gma",   "sdio4",         none, driven),
+        TEGRA_MAP_MUXCONF("gmb",   "gmi",           up,   tristate),
+        TEGRA_MAP_MUXCONF("gmc",   "uartd",         none, driven),
+        TEGRA_MAP_MUXCONF("gme",   "sdio4",         none, driven),
+        TEGRA_MAP_MUXCONF("gpu",   "pwm",           none, driven),
+        TEGRA_MAP_MUXCONF("gpu7",  "rtck",          none, driven),
+        TEGRA_MAP_MUXCONF("gpv",   "pcie",          none, tristate),
+        TEGRA_MAP_MUXCONF("hdint", "hdmi",          na,   tristate),
+        TEGRA_MAP_MUXCONF("i2cp",  "i2cp",          none, driven),
+        TEGRA_MAP_MUXCONF("irrx",  "uartb",         none, driven),
+        TEGRA_MAP_MUXCONF("irtx",  "uartb",         none, driven),
+        TEGRA_MAP_MUXCONF("kbca",  "kbc",           up,   driven),
+        TEGRA_MAP_MUXCONF("kbcb",  "kbc",           up,   driven),
+        TEGRA_MAP_MUXCONF("kbcc",  "kbc",           up,   driven),
+        TEGRA_MAP_MUXCONF("kbcd",  "kbc",           up,   driven),
+        TEGRA_MAP_MUXCONF("kbce",  "kbc",           up,   driven),
+        TEGRA_MAP_MUXCONF("kbcf",  "kbc",           up,   driven),
+        TEGRA_MAP_MUXCONF("lcsn",  "rsvd4",         na,   tristate),
+        TEGRA_MAP_MUXCONF("ld0",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld1",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld10",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld11",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld12",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld13",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld14",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld15",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld16",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld17",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld2",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld3",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld4",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld5",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld6",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld7",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld8",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld9",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ldc",   "rsvd4",         na,   tristate),
+        TEGRA_MAP_MUXCONF("ldi",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lhp0",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lhp1",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lhp2",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lhs",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lm0",   "rsvd4",         na,   driven),
+        TEGRA_MAP_MUXCONF("lm1",   "crt",           na,   tristate),
+        TEGRA_MAP_MUXCONF("lpp",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lpw1",  "rsvd4",         na,   tristate),
+        TEGRA_MAP_MUXCONF("lsc0",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lsdi",  "rsvd4",         na,   tristate),
+        TEGRA_MAP_MUXCONF("lspi",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lvp0",  "rsvd4",         na,   tristate),
+        TEGRA_MAP_MUXCONF("lvp1",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lvs",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("owc",   "rsvd2",         none, tristate),
+        TEGRA_MAP_MUXCONF("pmc",   "pwr_on",        na,   driven),
+        TEGRA_MAP_MUXCONF("pta",   "hdmi",          none, driven),
+        TEGRA_MAP_MUXCONF("rm",    "i2c1",          none, driven),
+        TEGRA_MAP_MUXCONF("sdb",   "sdio3",         na,   driven),
+        TEGRA_MAP_MUXCONF("sdc",   "sdio3",         none, driven),
+        TEGRA_MAP_MUXCONF("sdd",   "sdio3",         none, driven),
+        TEGRA_MAP_MUXCONF("sdio1", "sdio1",         up,   driven),
+        TEGRA_MAP_MUXCONF("slxa",  "pcie",          up,   tristate),
+        TEGRA_MAP_MUXCONF("slxd",  "spdif",         none, driven),
+        TEGRA_MAP_MUXCONF("slxk",  "pcie",          none, driven),
+        TEGRA_MAP_MUXCONF("spdi",  "rsvd2",         none, driven),
+        TEGRA_MAP_MUXCONF("spdo",  "rsvd2",         none, driven),
+        TEGRA_MAP_MUXCONF("spib",  "gmi",           none, tristate),
+        TEGRA_MAP_MUXCONF("spid",  "spi1",          none, tristate),
+        TEGRA_MAP_MUXCONF("spie",  "spi1",          none, tristate),
+        TEGRA_MAP_MUXCONF("spif",  "spi1",          down, tristate),
+        TEGRA_MAP_MUXCONF("spih",  "spi2_alt",      up,   tristate),
+        TEGRA_MAP_MUXCONF("uaa",   "ulpi",          up,   driven),
+        TEGRA_MAP_MUXCONF("uab",   "ulpi",          up,   driven),
+        TEGRA_MAP_MUXCONF("uac",   "rsvd2",         none, driven),
+        TEGRA_MAP_MUXCONF("uad",   "irda",          none, driven),
+        TEGRA_MAP_MUXCONF("uca",   "uartc",         none, driven),
+        TEGRA_MAP_MUXCONF("ucb",   "uartc",         none, driven),
+        TEGRA_MAP_MUXCONF("uda",   "ulpi",          none, driven),
+        TEGRA_MAP_CONF("ck32",    none, na),
+        TEGRA_MAP_CONF("ddrc",    none, na),
+        TEGRA_MAP_CONF("pmca",    none, na),
+        TEGRA_MAP_CONF("pmcb",    none, na),
+        TEGRA_MAP_CONF("pmcc",    none, na),
+        TEGRA_MAP_CONF("pmcd",    none, na),
+        TEGRA_MAP_CONF("pmce",    none, na),
+        TEGRA_MAP_CONF("xm2c",    none, na),
+        TEGRA_MAP_CONF("xm2d",    none, na),
+        TEGRA_MAP_CONF("ls",      up,   na),
+        TEGRA_MAP_CONF("lc",      up,   na),
+        TEGRA_MAP_CONF("ld17_0",  down, na),
+        TEGRA_MAP_CONF("ld19_18", down, na),
+        TEGRA_MAP_CONF("ld21_20", down, na),
+        TEGRA_MAP_CONF("ld23_22", down, na),
 };
 
-static struct tegra_gpio_table seaboard_gpio_table[] = {
-        { .gpio = TEGRA_GPIO_LIDSWITCH,         .enable = true },
-        { .gpio = TEGRA_GPIO_POWERKEY,          .enable = true },
-        { .gpio = TEGRA_GPIO_HP_DET,            .enable = true },
-        { .gpio = TEGRA_GPIO_ISL29018_IRQ,      .enable = true },
-        { .gpio = TEGRA_GPIO_USB1,              .enable = true },
+static struct pinctrl_map seaboard_map[] = {
+        TEGRA_MAP_MUXCONF("ddc",   "rsvd2",         none, tristate),
+        TEGRA_MAP_MUXCONF("gmd",   "sflash",        none, driven),
+        TEGRA_MAP_MUXCONF("lpw0",  "hdmi",          na,   driven),
+        TEGRA_MAP_MUXCONF("lpw2",  "hdmi",          na,   driven),
+        TEGRA_MAP_MUXCONF("lsc1",  "hdmi",          na,   tristate),
+        TEGRA_MAP_MUXCONF("lsck",  "hdmi",          na,   tristate),
+        TEGRA_MAP_MUXCONF("lsda",  "hdmi",          na,   tristate),
+        TEGRA_MAP_MUXCONF("slxc",  "spdif",         none, tristate),
+        TEGRA_MAP_MUXCONF("spia",  "gmi",           up,   tristate),
+        TEGRA_MAP_MUXCONF("spic",  "gmi",           up,   driven),
+        TEGRA_MAP_MUXCONF("spig",  "spi2_alt",      up,   tristate),
+        PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(PINMUX_DEV, "drive_sdio1", seaboard_pincfg_drive_sdio1),
 };
 
-static struct tegra_gpio_table ventana_gpio_table[] = {
-        /* hp_det */
-        { .gpio = TEGRA_GPIO_PW2,               .enable = true },
-        /* int_mic_en */
-        { .gpio = TEGRA_GPIO_PX0,               .enable = true },
-        /* ext_mic_en */
-        { .gpio = TEGRA_GPIO_PX1,               .enable = true },
+static struct pinctrl_map ventana_map[] = {
+        TEGRA_MAP_MUXCONF("ddc",   "rsvd2",         none, driven),
+        TEGRA_MAP_MUXCONF("gmd",   "sflash",        none, tristate),
+        TEGRA_MAP_MUXCONF("lpw0",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lpw2",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lsc1",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lsck",  "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("lsda",  "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("slxc",  "sdio3",         none, driven),
+        TEGRA_MAP_MUXCONF("spia",  "gmi",           none, tristate),
+        TEGRA_MAP_MUXCONF("spic",  "gmi",           none, tristate),
+        TEGRA_MAP_MUXCONF("spig",  "spi2_alt",      none, tristate),
 };
 
 static struct tegra_board_pinmux_conf common_conf = {
-        .pgs = common_pinmux,
-        .pg_count = ARRAY_SIZE(common_pinmux),
-        .gpios = common_gpio_table,
-        .gpio_count = ARRAY_SIZE(common_gpio_table),
+        .maps = common_map,
+        .map_count = ARRAY_SIZE(common_map),
 };
 
 static struct tegra_board_pinmux_conf seaboard_conf = {
-        .pgs = seaboard_pinmux,
-        .pg_count = ARRAY_SIZE(seaboard_pinmux),
-        .drives = seaboard_drive_pinmux,
-        .drive_count = ARRAY_SIZE(seaboard_drive_pinmux),
-        .gpios = seaboard_gpio_table,
-        .gpio_count = ARRAY_SIZE(seaboard_gpio_table),
+        .maps = seaboard_map,
+        .map_count = ARRAY_SIZE(seaboard_map),
 };
 
 static struct tegra_board_pinmux_conf ventana_conf = {
-        .pgs = ventana_pinmux,
-        .pg_count = ARRAY_SIZE(ventana_pinmux),
-        .gpios = ventana_gpio_table,
-        .gpio_count = ARRAY_SIZE(ventana_gpio_table),
+        .maps = ventana_map,
+        .map_count = ARRAY_SIZE(ventana_map),
 };
 
 void seaboard_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c
index d669847f0485..a0184fb44222 100644
--- a/arch/arm/mach-tegra/board-seaboard.c
+++ b/arch/arm/mach-tegra/board-seaboard.c
@@ -24,6 +24,7 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
+#include <linux/platform_data/tegra_usb.h>
 
 #include <sound/wm8903.h>
 
@@ -186,20 +187,10 @@ static struct i2c_board_info __initdata wm8903_device = {
 
 static int seaboard_ehci_init(void)
 {
-        int gpio_status;
+        struct tegra_ehci_platform_data *pdata;
 
-        gpio_status = gpio_request(TEGRA_GPIO_USB1, "VBUS_USB1");
-        if (gpio_status < 0) {
-                pr_err("VBUS_USB1 request GPIO FAILED\n");
-                WARN_ON(1);
-        }
-
-        gpio_status = gpio_direction_output(TEGRA_GPIO_USB1, 1);
-        if (gpio_status < 0) {
-                pr_err("VBUS_USB1 request GPIO DIRECTION FAILED\n");
-                WARN_ON(1);
-        }
-        gpio_set_value(TEGRA_GPIO_USB1, 1);
+        pdata = tegra_ehci1_device.dev.platform_data;
+        pdata->vbus_gpio = TEGRA_GPIO_USB1;
 
         platform_device_register(&tegra_ehci1_device);
         platform_device_register(&tegra_ehci3_device);
@@ -209,9 +200,6 @@ static int seaboard_ehci_init(void)
 
 static void __init seaboard_i2c_init(void)
 {
-        gpio_request(TEGRA_GPIO_ISL29018_IRQ, "isl29018");
-        gpio_direction_input(TEGRA_GPIO_ISL29018_IRQ);
-
         isl29018_device.irq = gpio_to_irq(TEGRA_GPIO_ISL29018_IRQ);
         i2c_register_board_info(0, &isl29018_device, 1);
 
@@ -261,7 +249,6 @@ static void __init tegra_kaen_init(void)
         debug_uart_platform_data[0].irq = INT_UARTB;
 
         seaboard_audio_pdata.gpio_hp_mute = TEGRA_GPIO_KAEN_HP_MUTE;
-        tegra_gpio_enable(TEGRA_GPIO_KAEN_HP_MUTE);
 
         seaboard_common_init();
 
diff --git a/arch/arm/mach-tegra/board-trimslice-pinmux.c b/arch/arm/mach-tegra/board-trimslice-pinmux.c
index a21a2be57cb6..7b39511c0d4d 100644
--- a/arch/arm/mach-tegra/board-trimslice-pinmux.c
+++ b/arch/arm/mach-tegra/board-trimslice-pinmux.c
@@ -2,6 +2,7 @@
  * arch/arm/mach-tegra/board-trimslice-pinmux.c
  *
  * Copyright (C) 2011 CompuLab, Ltd.
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -13,150 +14,139 @@
  * GNU General Public License for more details.
  *
  */
-#include <linux/gpio.h>
 #include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/of.h>
 
-#include <mach/pinmux.h>
-#include <mach/pinmux-tegra20.h>
-
-#include "gpio-names.h"
-#include "board-pinmux.h"
 #include "board-trimslice.h"
+#include "board-pinmux.h"
 
-static struct tegra_pingroup_config trimslice_pinmux[] = {
-        {TEGRA_PINGROUP_ATA,   TEGRA_MUX_IDE,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_ATB,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_ATC,   TEGRA_MUX_NAND,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_ATD,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_ATE,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT,      TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4,     TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_CRTP,  TEGRA_MUX_CRT,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_CSUS,  TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_DAP1,  TEGRA_MUX_DAP1,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DAP2,  TEGRA_MUX_DAP2,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_DAP3,  TEGRA_MUX_DAP3,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_DAP4,  TEGRA_MUX_DAP4,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_DDC,   TEGRA_MUX_I2C2,          TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DTA,   TEGRA_MUX_VI,            TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_DTB,   TEGRA_MUX_VI,            TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_DTC,   TEGRA_MUX_VI,            TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_DTD,   TEGRA_MUX_VI,            TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_DTE,   TEGRA_MUX_VI,            TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_DTF,   TEGRA_MUX_I2C3,          TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GMA,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GMB,   TEGRA_MUX_NAND,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_GMC,   TEGRA_MUX_SFLASH,        TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GMD,   TEGRA_MUX_SFLASH,        TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GME,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_GPU,   TEGRA_MUX_UARTA,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GPU7,  TEGRA_MUX_RTCK,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GPV,   TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI,          TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_I2CP,  TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_IRRX,  TEGRA_MUX_UARTB,         TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_IRTX,  TEGRA_MUX_UARTB,         TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_KBCA,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_KBCB,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_KBCC,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_KBCD,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_KBCE,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_KBCF,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LCSN,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LD0,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD1,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD2,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD3,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD4,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD5,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD6,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD7,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD8,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD9,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD10,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD11,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD12,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD13,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD14,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD15,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD16,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD17,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LDC,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LDI,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LHP0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LHP1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LHP2,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LHS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LM0,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LM1,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LPP,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LPW0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LPW1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LPW2,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LSC0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LSC1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LSCK,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LSDA,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LSDI,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LSPI,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LVP0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LVP1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LVS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_OWC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_PMC,   TEGRA_MUX_PWR_ON,        TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_PTA,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_RM,    TEGRA_MUX_I2C,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SDB,   TEGRA_MUX_PWM,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SDC,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SDD,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SLXA,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SLXC,  TEGRA_MUX_SDIO3,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SLXD,  TEGRA_MUX_SDIO3,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SLXK,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SPDI,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPDO,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIA,  TEGRA_MUX_SPI2,          TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIB,  TEGRA_MUX_SPI2,          TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIC,  TEGRA_MUX_SPI2,          TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPID,  TEGRA_MUX_SPI1,          TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIE,  TEGRA_MUX_SPI1,          TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIF,  TEGRA_MUX_SPI1,          TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIG,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIH,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_UAA,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_UAB,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_UAC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_UAD,   TEGRA_MUX_IRDA,          TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_UCA,   TEGRA_MUX_UARTC,         TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_UCB,   TEGRA_MUX_UARTC,         TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_UDA,   TEGRA_MUX_ULPI,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_CK32,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DDRC,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_PMCA,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_PMCB,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_PMCC,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_PMCD,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_PMCE,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_XM2C,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-};
-
-static struct tegra_gpio_table gpio_table[] = {
-        { .gpio = TRIMSLICE_GPIO_SD4_CD, .enable = true }, /* mmc4 cd */
-        { .gpio = TRIMSLICE_GPIO_SD4_WP, .enable = true }, /* mmc4 wp */
-
-        { .gpio = TRIMSLICE_GPIO_USB1_MODE, .enable = true }, /* USB1 mode */
-        { .gpio = TRIMSLICE_GPIO_USB2_RST,  .enable = true }, /* USB2 PHY rst */
+static struct pinctrl_map trimslice_map[] = {
+        TEGRA_MAP_MUXCONF("ata",   "ide",           none, tristate),
+        TEGRA_MAP_MUXCONF("atb",   "sdio4",         none, driven),
+        TEGRA_MAP_MUXCONF("atc",   "nand",          none, tristate),
+        TEGRA_MAP_MUXCONF("atd",   "gmi",           none, tristate),
+        TEGRA_MAP_MUXCONF("ate",   "gmi",           none, tristate),
+        TEGRA_MAP_MUXCONF("cdev1", "plla_out",      none, driven),
+        TEGRA_MAP_MUXCONF("cdev2", "pllp_out4",     down, tristate),
+        TEGRA_MAP_MUXCONF("crtp",  "crt",           none, tristate),
+        TEGRA_MAP_MUXCONF("csus",  "vi_sensor_clk", down, tristate),
+        TEGRA_MAP_MUXCONF("dap1",  "dap1",          none, driven),
+        TEGRA_MAP_MUXCONF("dap2",  "dap2",          none, tristate),
+        TEGRA_MAP_MUXCONF("dap3",  "dap3",          none, tristate),
+        TEGRA_MAP_MUXCONF("dap4",  "dap4",          none, tristate),
+        TEGRA_MAP_MUXCONF("ddc",   "i2c2",          up,   driven),
+        TEGRA_MAP_MUXCONF("dta",   "vi",            none, tristate),
+        TEGRA_MAP_MUXCONF("dtb",   "vi",            none, tristate),
+        TEGRA_MAP_MUXCONF("dtc",   "vi",            none, tristate),
+        TEGRA_MAP_MUXCONF("dtd",   "vi",            none, tristate),
+        TEGRA_MAP_MUXCONF("dte",   "vi",            none, tristate),
+        TEGRA_MAP_MUXCONF("dtf",   "i2c3",          up,   driven),
+        TEGRA_MAP_MUXCONF("gma",   "sdio4",         none, driven),
+        TEGRA_MAP_MUXCONF("gmb",   "nand",          none, tristate),
+        TEGRA_MAP_MUXCONF("gmc",   "sflash",        none, driven),
+        TEGRA_MAP_MUXCONF("gmd",   "sflash",        none, driven),
+        TEGRA_MAP_MUXCONF("gme",   "gmi",           none, tristate),
+        TEGRA_MAP_MUXCONF("gpu",   "uarta",         none, driven),
+        TEGRA_MAP_MUXCONF("gpu7",  "rtck",          none, driven),
+        TEGRA_MAP_MUXCONF("gpv",   "pcie",          none, driven),
+        TEGRA_MAP_MUXCONF("hdint", "hdmi",          na,   tristate),
+        TEGRA_MAP_MUXCONF("i2cp",  "i2cp",          none, tristate),
+        TEGRA_MAP_MUXCONF("irrx",  "uartb",         up,   tristate),
+        TEGRA_MAP_MUXCONF("irtx",  "uartb",         up,   tristate),
+        TEGRA_MAP_MUXCONF("kbca",  "kbc",           up,   tristate),
+        TEGRA_MAP_MUXCONF("kbcb",  "kbc",           up,   tristate),
+        TEGRA_MAP_MUXCONF("kbcc",  "kbc",           up,   tristate),
+        TEGRA_MAP_MUXCONF("kbcd",  "kbc",           up,   tristate),
+        TEGRA_MAP_MUXCONF("kbce",  "kbc",           up,   tristate),
+        TEGRA_MAP_MUXCONF("kbcf",  "kbc",           up,   tristate),
+        TEGRA_MAP_MUXCONF("lcsn",  "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("ld0",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld1",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld10",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld11",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld12",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld13",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld14",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld15",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld16",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld17",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld2",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld3",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld4",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld5",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld6",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld7",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld8",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld9",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ldc",   "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("ldi",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lhp0",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lhp1",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lhp2",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lhs",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lm0",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lm1",   "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("lpp",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lpw0",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lpw1",  "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("lpw2",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lsc0",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lsc1",  "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("lsck",  "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("lsda",  "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("lsdi",  "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("lspi",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lvp0",  "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("lvp1",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lvs",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("owc",   "rsvd2",         up,   tristate),
+        TEGRA_MAP_MUXCONF("pmc",   "pwr_on",        na,   tristate),
+        TEGRA_MAP_MUXCONF("pta",   "gmi",           none, tristate),
+        TEGRA_MAP_MUXCONF("rm",    "i2c1",          up,   driven),
+        TEGRA_MAP_MUXCONF("sdb",   "pwm",           na,   driven),
+        TEGRA_MAP_MUXCONF("sdc",   "pwm",           up,   driven),
+        TEGRA_MAP_MUXCONF("sdd",   "pwm",           up,   driven),
+        TEGRA_MAP_MUXCONF("sdio1", "sdio1",         none, driven),
+        TEGRA_MAP_MUXCONF("slxa",  "pcie",          none, driven),
+        TEGRA_MAP_MUXCONF("slxc",  "sdio3",         none, tristate),
+        TEGRA_MAP_MUXCONF("slxd",  "sdio3",         none, tristate),
+        TEGRA_MAP_MUXCONF("slxk",  "pcie",          none, driven),
+        TEGRA_MAP_MUXCONF("spdi",  "spdif",         none, tristate),
+        TEGRA_MAP_MUXCONF("spdo",  "spdif",         none, tristate),
+        TEGRA_MAP_MUXCONF("spia",  "spi2",          down, tristate),
+        TEGRA_MAP_MUXCONF("spib",  "spi2",          down, tristate),
+        TEGRA_MAP_MUXCONF("spic",  "spi2",          up,   tristate),
+        TEGRA_MAP_MUXCONF("spid",  "spi1",          down, tristate),
+        TEGRA_MAP_MUXCONF("spie",  "spi1",          up,   tristate),
+        TEGRA_MAP_MUXCONF("spif",  "spi1",          down, tristate),
+        TEGRA_MAP_MUXCONF("spig",  "spi2_alt",      up,   tristate),
+        TEGRA_MAP_MUXCONF("spih",  "spi2_alt",      up,   tristate),
+        TEGRA_MAP_MUXCONF("uaa",   "ulpi",          up,   tristate),
+        TEGRA_MAP_MUXCONF("uab",   "ulpi",          up,   tristate),
+        TEGRA_MAP_MUXCONF("uac",   "rsvd2",         none, driven),
+        TEGRA_MAP_MUXCONF("uad",   "irda",          up,   tristate),
+        TEGRA_MAP_MUXCONF("uca",   "uartc",         up,   tristate),
+        TEGRA_MAP_MUXCONF("ucb",   "uartc",         up,   tristate),
+        TEGRA_MAP_MUXCONF("uda",   "ulpi",          none, tristate),
+        TEGRA_MAP_CONF("ck32",    none, na),
+        TEGRA_MAP_CONF("ddrc",    none, na),
+        TEGRA_MAP_CONF("pmca",    none, na),
+        TEGRA_MAP_CONF("pmcb",    none, na),
+        TEGRA_MAP_CONF("pmcc",    none, na),
+        TEGRA_MAP_CONF("pmcd",    none, na),
+        TEGRA_MAP_CONF("pmce",    none, na),
+        TEGRA_MAP_CONF("xm2c",    none, na),
+        TEGRA_MAP_CONF("xm2d",    none, na),
+        TEGRA_MAP_CONF("ls",      up,   na),
+        TEGRA_MAP_CONF("lc",      up,   na),
+        TEGRA_MAP_CONF("ld17_0",  down, na),
+        TEGRA_MAP_CONF("ld19_18", down, na),
+        TEGRA_MAP_CONF("ld21_20", down, na),
+        TEGRA_MAP_CONF("ld23_22", down, na),
 };
 
 static struct tegra_board_pinmux_conf conf = {
-        .pgs = trimslice_pinmux,
-        .pg_count = ARRAY_SIZE(trimslice_pinmux),
-        .gpios = gpio_table,
-        .gpio_count = ARRAY_SIZE(gpio_table),
+        .maps = trimslice_map,
+        .map_count = ARRAY_SIZE(trimslice_map),
 };
 
 void trimslice_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
index cd52820a3e37..f6f5b6a11325 100644
--- a/arch/arm/mach-tegra/board-trimslice.c
+++ b/arch/arm/mach-tegra/board-trimslice.c
@@ -25,6 +25,7 @@
 #include <linux/io.h>
 #include <linux/i2c.h>
 #include <linux/gpio.h>
+#include <linux/platform_data/tegra_usb.h>
 
 #include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
@@ -111,19 +112,13 @@ static void trimslice_i2c_init(void)
 
 static void trimslice_usb_init(void)
 {
-        int err;
+        struct tegra_ehci_platform_data *pdata;
 
-        platform_device_register(&tegra_ehci3_device);
+        pdata = tegra_ehci1_device.dev.platform_data;
+        pdata->vbus_gpio = TRIMSLICE_GPIO_USB1_MODE;
 
+        platform_device_register(&tegra_ehci3_device);
         platform_device_register(&tegra_ehci2_device);
-
-        err = gpio_request_one(TRIMSLICE_GPIO_USB1_MODE, GPIOF_OUT_INIT_HIGH,
-                               "usb1mode");
-        if (err) {
-                pr_err("TrimSlice: failed to obtain USB1 mode gpio: %d\n", err);
-                return;
-        }
-
         platform_device_register(&tegra_ehci1_device);
 }
 
diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
index 5f6b867e20b4..bd3035e0cea1 100644
--- a/arch/arm/mach-tegra/devices.c
+++ b/arch/arm/mach-tegra/devices.c
@@ -110,7 +110,7 @@ static struct resource pinmux_resource[] = {
 };
 
 struct platform_device tegra_pinmux_device = {
-        .name           = "tegra-pinmux",
+        .name           = "tegra20-pinctrl",
         .id             = -1,
         .resource       = pinmux_resource,
         .num_resources  = ARRAY_SIZE(pinmux_resource),
@@ -448,17 +448,20 @@ static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
 struct tegra_ehci_platform_data tegra_ehci1_pdata = {
         .operating_mode = TEGRA_USB_OTG,
         .power_down_on_bus_suspend = 1,
+        .vbus_gpio = -1,
 };
 
 struct tegra_ehci_platform_data tegra_ehci2_pdata = {
         .phy_config = &tegra_ehci2_ulpi_phy_config,
         .operating_mode = TEGRA_USB_HOST,
         .power_down_on_bus_suspend = 1,
+        .vbus_gpio = -1,
 };
 
 struct tegra_ehci_platform_data tegra_ehci3_pdata = {
         .operating_mode = TEGRA_USB_HOST,
         .power_down_on_bus_suspend = 1,
+        .vbus_gpio = -1,
 };
 
 static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
diff --git a/arch/arm/mach-tegra/include/mach/gpio-tegra.h b/arch/arm/mach-tegra/include/mach/gpio-tegra.h
index 6140820555e1..a978b3cc3a8d 100644
--- a/arch/arm/mach-tegra/include/mach/gpio-tegra.h
+++ b/arch/arm/mach-tegra/include/mach/gpio-tegra.h
@@ -25,13 +25,4 @@
 
 #define TEGRA_NR_GPIOS          INT_GPIO_NR
 
-struct tegra_gpio_table {
-        int     gpio;   /* GPIO number */
-        bool    enable; /* Enable for GPIO at init? */
-};
-
-void tegra_gpio_config(struct tegra_gpio_table *table, int num);
-void tegra_gpio_enable(int gpio);
-void tegra_gpio_disable(int gpio);
-
 #endif
diff --git a/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h b/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
deleted file mode 100644
index 6a40c1dbab17..000000000000
--- a/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * linux/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_TEGRA_PINMUX_TEGRA20_H
-#define __MACH_TEGRA_PINMUX_TEGRA20_H
-
-enum tegra_pingroup {
-        TEGRA_PINGROUP_ATA = 0,
-        TEGRA_PINGROUP_ATB,
-        TEGRA_PINGROUP_ATC,
-        TEGRA_PINGROUP_ATD,
-        TEGRA_PINGROUP_ATE,
-        TEGRA_PINGROUP_CDEV1,
-        TEGRA_PINGROUP_CDEV2,
-        TEGRA_PINGROUP_CRTP,
-        TEGRA_PINGROUP_CSUS,
-        TEGRA_PINGROUP_DAP1,
-        TEGRA_PINGROUP_DAP2,
-        TEGRA_PINGROUP_DAP3,
-        TEGRA_PINGROUP_DAP4,
-        TEGRA_PINGROUP_DDC,
-        TEGRA_PINGROUP_DTA,
-        TEGRA_PINGROUP_DTB,
-        TEGRA_PINGROUP_DTC,
-        TEGRA_PINGROUP_DTD,
-        TEGRA_PINGROUP_DTE,
-        TEGRA_PINGROUP_DTF,
-        TEGRA_PINGROUP_GMA,
-        TEGRA_PINGROUP_GMB,
-        TEGRA_PINGROUP_GMC,
-        TEGRA_PINGROUP_GMD,
-        TEGRA_PINGROUP_GME,
-        TEGRA_PINGROUP_GPU,
-        TEGRA_PINGROUP_GPU7,
-        TEGRA_PINGROUP_GPV,
-        TEGRA_PINGROUP_HDINT,
-        TEGRA_PINGROUP_I2CP,
-        TEGRA_PINGROUP_IRRX,
-        TEGRA_PINGROUP_IRTX,
-        TEGRA_PINGROUP_KBCA,
-        TEGRA_PINGROUP_KBCB,
-        TEGRA_PINGROUP_KBCC,
-        TEGRA_PINGROUP_KBCD,
-        TEGRA_PINGROUP_KBCE,
-        TEGRA_PINGROUP_KBCF,
-        TEGRA_PINGROUP_LCSN,
-        TEGRA_PINGROUP_LD0,
-        TEGRA_PINGROUP_LD1,
-        TEGRA_PINGROUP_LD10,
-        TEGRA_PINGROUP_LD11,
-        TEGRA_PINGROUP_LD12,
-        TEGRA_PINGROUP_LD13,
-        TEGRA_PINGROUP_LD14,
-        TEGRA_PINGROUP_LD15,
-        TEGRA_PINGROUP_LD16,
-        TEGRA_PINGROUP_LD17,
-        TEGRA_PINGROUP_LD2,
-        TEGRA_PINGROUP_LD3,
-        TEGRA_PINGROUP_LD4,
-        TEGRA_PINGROUP_LD5,
-        TEGRA_PINGROUP_LD6,
-        TEGRA_PINGROUP_LD7,
-        TEGRA_PINGROUP_LD8,
-        TEGRA_PINGROUP_LD9,
-        TEGRA_PINGROUP_LDC,
-        TEGRA_PINGROUP_LDI,
-        TEGRA_PINGROUP_LHP0,
-        TEGRA_PINGROUP_LHP1,
-        TEGRA_PINGROUP_LHP2,
-        TEGRA_PINGROUP_LHS,
-        TEGRA_PINGROUP_LM0,
-        TEGRA_PINGROUP_LM1,
-        TEGRA_PINGROUP_LPP,
-        TEGRA_PINGROUP_LPW0,
-        TEGRA_PINGROUP_LPW1,
-        TEGRA_PINGROUP_LPW2,
-        TEGRA_PINGROUP_LSC0,
-        TEGRA_PINGROUP_LSC1,
-        TEGRA_PINGROUP_LSCK,
-        TEGRA_PINGROUP_LSDA,
-        TEGRA_PINGROUP_LSDI,
-        TEGRA_PINGROUP_LSPI,
-        TEGRA_PINGROUP_LVP0,
-        TEGRA_PINGROUP_LVP1,
-        TEGRA_PINGROUP_LVS,
-        TEGRA_PINGROUP_OWC,
-        TEGRA_PINGROUP_PMC,
-        TEGRA_PINGROUP_PTA,
-        TEGRA_PINGROUP_RM,
-        TEGRA_PINGROUP_SDB,
-        TEGRA_PINGROUP_SDC,
-        TEGRA_PINGROUP_SDD,
-        TEGRA_PINGROUP_SDIO1,
-        TEGRA_PINGROUP_SLXA,
-        TEGRA_PINGROUP_SLXC,
-        TEGRA_PINGROUP_SLXD,
-        TEGRA_PINGROUP_SLXK,
-        TEGRA_PINGROUP_SPDI,
-        TEGRA_PINGROUP_SPDO,
-        TEGRA_PINGROUP_SPIA,
-        TEGRA_PINGROUP_SPIB,
-        TEGRA_PINGROUP_SPIC,
-        TEGRA_PINGROUP_SPID,
-        TEGRA_PINGROUP_SPIE,
-        TEGRA_PINGROUP_SPIF,
-        TEGRA_PINGROUP_SPIG,
-        TEGRA_PINGROUP_SPIH,
-        TEGRA_PINGROUP_UAA,
-        TEGRA_PINGROUP_UAB,
-        TEGRA_PINGROUP_UAC,
-        TEGRA_PINGROUP_UAD,
-        TEGRA_PINGROUP_UCA,
-        TEGRA_PINGROUP_UCB,
-        TEGRA_PINGROUP_UDA,
-        /* these pin groups only have pullup and pull down control */
-        TEGRA_PINGROUP_CK32,
-        TEGRA_PINGROUP_DDRC,
-        TEGRA_PINGROUP_PMCA,
-        TEGRA_PINGROUP_PMCB,
-        TEGRA_PINGROUP_PMCC,
-        TEGRA_PINGROUP_PMCD,
-        TEGRA_PINGROUP_PMCE,
-        TEGRA_PINGROUP_XM2C,
-        TEGRA_PINGROUP_XM2D,
-        TEGRA_MAX_PINGROUP,
-};
-
-enum tegra_drive_pingroup {
-        TEGRA_DRIVE_PINGROUP_AO1 = 0,
-        TEGRA_DRIVE_PINGROUP_AO2,
-        TEGRA_DRIVE_PINGROUP_AT1,
-        TEGRA_DRIVE_PINGROUP_AT2,
-        TEGRA_DRIVE_PINGROUP_CDEV1,
-        TEGRA_DRIVE_PINGROUP_CDEV2,
-        TEGRA_DRIVE_PINGROUP_CSUS,
-        TEGRA_DRIVE_PINGROUP_DAP1,
-        TEGRA_DRIVE_PINGROUP_DAP2,
-        TEGRA_DRIVE_PINGROUP_DAP3,
-        TEGRA_DRIVE_PINGROUP_DAP4,
-        TEGRA_DRIVE_PINGROUP_DBG,
-        TEGRA_DRIVE_PINGROUP_LCD1,
-        TEGRA_DRIVE_PINGROUP_LCD2,
-        TEGRA_DRIVE_PINGROUP_SDMMC2,
-        TEGRA_DRIVE_PINGROUP_SDMMC3,
-        TEGRA_DRIVE_PINGROUP_SPI,
-        TEGRA_DRIVE_PINGROUP_UAA,
-        TEGRA_DRIVE_PINGROUP_UAB,
-        TEGRA_DRIVE_PINGROUP_UART2,
-        TEGRA_DRIVE_PINGROUP_UART3,
-        TEGRA_DRIVE_PINGROUP_VI1,
-        TEGRA_DRIVE_PINGROUP_VI2,
-        TEGRA_DRIVE_PINGROUP_XM2A,
-        TEGRA_DRIVE_PINGROUP_XM2C,
-        TEGRA_DRIVE_PINGROUP_XM2D,
-        TEGRA_DRIVE_PINGROUP_XM2CLK,
-        TEGRA_DRIVE_PINGROUP_MEMCOMP,
-        TEGRA_DRIVE_PINGROUP_SDIO1,
-        TEGRA_DRIVE_PINGROUP_CRT,
-        TEGRA_DRIVE_PINGROUP_DDC,
-        TEGRA_DRIVE_PINGROUP_GMA,
-        TEGRA_DRIVE_PINGROUP_GMB,
-        TEGRA_DRIVE_PINGROUP_GMC,
-        TEGRA_DRIVE_PINGROUP_GMD,
-        TEGRA_DRIVE_PINGROUP_GME,
-        TEGRA_DRIVE_PINGROUP_OWR,
-        TEGRA_DRIVE_PINGROUP_UAD,
-        TEGRA_MAX_DRIVE_PINGROUP,
-};
-
-#endif
-
diff --git a/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h b/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
deleted file mode 100644
index c1aee3eb2df1..000000000000
--- a/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
+++ /dev/null
@@ -1,320 +0,0 @@
-/*
- * linux/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
- *
- * Copyright (C) 2010 Google, Inc.
- * Copyright (C) 2010,2011 Nvidia, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_TEGRA_PINMUX_TEGRA30_H
-#define __MACH_TEGRA_PINMUX_TEGRA30_H
-
-enum tegra_pingroup {
-        TEGRA_PINGROUP_ULPI_DATA0 = 0,
-        TEGRA_PINGROUP_ULPI_DATA1,
-        TEGRA_PINGROUP_ULPI_DATA2,
-        TEGRA_PINGROUP_ULPI_DATA3,
-        TEGRA_PINGROUP_ULPI_DATA4,
-        TEGRA_PINGROUP_ULPI_DATA5,
-        TEGRA_PINGROUP_ULPI_DATA6,
-        TEGRA_PINGROUP_ULPI_DATA7,
-        TEGRA_PINGROUP_ULPI_CLK,
-        TEGRA_PINGROUP_ULPI_DIR,
-        TEGRA_PINGROUP_ULPI_NXT,
-        TEGRA_PINGROUP_ULPI_STP,
-        TEGRA_PINGROUP_DAP3_FS,
-        TEGRA_PINGROUP_DAP3_DIN,
-        TEGRA_PINGROUP_DAP3_DOUT,
-        TEGRA_PINGROUP_DAP3_SCLK,
-        TEGRA_PINGROUP_GPIO_PV0,
-        TEGRA_PINGROUP_GPIO_PV1,
-        TEGRA_PINGROUP_SDMMC1_CLK,
-        TEGRA_PINGROUP_SDMMC1_CMD,
-        TEGRA_PINGROUP_SDMMC1_DAT3,
-        TEGRA_PINGROUP_SDMMC1_DAT2,
-        TEGRA_PINGROUP_SDMMC1_DAT1,
-        TEGRA_PINGROUP_SDMMC1_DAT0,
-        TEGRA_PINGROUP_GPIO_PV2,
-        TEGRA_PINGROUP_GPIO_PV3,
-        TEGRA_PINGROUP_CLK2_OUT,
-        TEGRA_PINGROUP_CLK2_REQ,
-        TEGRA_PINGROUP_LCD_PWR1,
-        TEGRA_PINGROUP_LCD_PWR2,
-        TEGRA_PINGROUP_LCD_SDIN,
-        TEGRA_PINGROUP_LCD_SDOUT,
-        TEGRA_PINGROUP_LCD_WR_N,
-        TEGRA_PINGROUP_LCD_CS0_N,
-        TEGRA_PINGROUP_LCD_DC0,
-        TEGRA_PINGROUP_LCD_SCK,
-        TEGRA_PINGROUP_LCD_PWR0,
-        TEGRA_PINGROUP_LCD_PCLK,
-        TEGRA_PINGROUP_LCD_DE,
-        TEGRA_PINGROUP_LCD_HSYNC,
-        TEGRA_PINGROUP_LCD_VSYNC,
-        TEGRA_PINGROUP_LCD_D0,
-        TEGRA_PINGROUP_LCD_D1,
-        TEGRA_PINGROUP_LCD_D2,
-        TEGRA_PINGROUP_LCD_D3,
-        TEGRA_PINGROUP_LCD_D4,
-        TEGRA_PINGROUP_LCD_D5,
-        TEGRA_PINGROUP_LCD_D6,
-        TEGRA_PINGROUP_LCD_D7,
-        TEGRA_PINGROUP_LCD_D8,
-        TEGRA_PINGROUP_LCD_D9,
-        TEGRA_PINGROUP_LCD_D10,
-        TEGRA_PINGROUP_LCD_D11,
-        TEGRA_PINGROUP_LCD_D12,
-        TEGRA_PINGROUP_LCD_D13,
-        TEGRA_PINGROUP_LCD_D14,
-        TEGRA_PINGROUP_LCD_D15,
-        TEGRA_PINGROUP_LCD_D16,
-        TEGRA_PINGROUP_LCD_D17,
-        TEGRA_PINGROUP_LCD_D18,
-        TEGRA_PINGROUP_LCD_D19,
-        TEGRA_PINGROUP_LCD_D20,
-        TEGRA_PINGROUP_LCD_D21,
-        TEGRA_PINGROUP_LCD_D22,
-        TEGRA_PINGROUP_LCD_D23,
-        TEGRA_PINGROUP_LCD_CS1_N,
-        TEGRA_PINGROUP_LCD_M1,
-        TEGRA_PINGROUP_LCD_DC1,
-        TEGRA_PINGROUP_HDMI_INT,
-        TEGRA_PINGROUP_DDC_SCL,
-        TEGRA_PINGROUP_DDC_SDA,
-        TEGRA_PINGROUP_CRT_HSYNC,
-        TEGRA_PINGROUP_CRT_VSYNC,
-        TEGRA_PINGROUP_VI_D0,
-        TEGRA_PINGROUP_VI_D1,
-        TEGRA_PINGROUP_VI_D2,
-        TEGRA_PINGROUP_VI_D3,
-        TEGRA_PINGROUP_VI_D4,
-        TEGRA_PINGROUP_VI_D5,
-        TEGRA_PINGROUP_VI_D6,
-        TEGRA_PINGROUP_VI_D7,
-        TEGRA_PINGROUP_VI_D8,
-        TEGRA_PINGROUP_VI_D9,
-        TEGRA_PINGROUP_VI_D10,
-        TEGRA_PINGROUP_VI_D11,
-        TEGRA_PINGROUP_VI_PCLK,
-        TEGRA_PINGROUP_VI_MCLK,
-        TEGRA_PINGROUP_VI_VSYNC,
-        TEGRA_PINGROUP_VI_HSYNC,
-        TEGRA_PINGROUP_UART2_RXD,
-        TEGRA_PINGROUP_UART2_TXD,
-        TEGRA_PINGROUP_UART2_RTS_N,
-        TEGRA_PINGROUP_UART2_CTS_N,
-        TEGRA_PINGROUP_UART3_TXD,
-        TEGRA_PINGROUP_UART3_RXD,
-        TEGRA_PINGROUP_UART3_CTS_N,
-        TEGRA_PINGROUP_UART3_RTS_N,
-        TEGRA_PINGROUP_GPIO_PU0,
-        TEGRA_PINGROUP_GPIO_PU1,
-        TEGRA_PINGROUP_GPIO_PU2,
-        TEGRA_PINGROUP_GPIO_PU3,
-        TEGRA_PINGROUP_GPIO_PU4,
-        TEGRA_PINGROUP_GPIO_PU5,
-        TEGRA_PINGROUP_GPIO_PU6,
-        TEGRA_PINGROUP_GEN1_I2C_SDA,
-        TEGRA_PINGROUP_GEN1_I2C_SCL,
-        TEGRA_PINGROUP_DAP4_FS,
-        TEGRA_PINGROUP_DAP4_DIN,
-        TEGRA_PINGROUP_DAP4_DOUT,
-        TEGRA_PINGROUP_DAP4_SCLK,
-        TEGRA_PINGROUP_CLK3_OUT,
-        TEGRA_PINGROUP_CLK3_REQ,
-        TEGRA_PINGROUP_GMI_WP_N,
-        TEGRA_PINGROUP_GMI_IORDY,
-        TEGRA_PINGROUP_GMI_WAIT,
-        TEGRA_PINGROUP_GMI_ADV_N,
-        TEGRA_PINGROUP_GMI_CLK,
-        TEGRA_PINGROUP_GMI_CS0_N,
-        TEGRA_PINGROUP_GMI_CS1_N,
-        TEGRA_PINGROUP_GMI_CS2_N,
-        TEGRA_PINGROUP_GMI_CS3_N,
-        TEGRA_PINGROUP_GMI_CS4_N,
-        TEGRA_PINGROUP_GMI_CS6_N,
-        TEGRA_PINGROUP_GMI_CS7_N,
-        TEGRA_PINGROUP_GMI_AD0,
-        TEGRA_PINGROUP_GMI_AD1,
-        TEGRA_PINGROUP_GMI_AD2,
-        TEGRA_PINGROUP_GMI_AD3,
-        TEGRA_PINGROUP_GMI_AD4,
-        TEGRA_PINGROUP_GMI_AD5,
-        TEGRA_PINGROUP_GMI_AD6,
-        TEGRA_PINGROUP_GMI_AD7,
-        TEGRA_PINGROUP_GMI_AD8,
-        TEGRA_PINGROUP_GMI_AD9,
-        TEGRA_PINGROUP_GMI_AD10,
-        TEGRA_PINGROUP_GMI_AD11,
-        TEGRA_PINGROUP_GMI_AD12,
-        TEGRA_PINGROUP_GMI_AD13,
-        TEGRA_PINGROUP_GMI_AD14,
-        TEGRA_PINGROUP_GMI_AD15,
-        TEGRA_PINGROUP_GMI_A16,
-        TEGRA_PINGROUP_GMI_A17,
-        TEGRA_PINGROUP_GMI_A18,
-        TEGRA_PINGROUP_GMI_A19,
-        TEGRA_PINGROUP_GMI_WR_N,
-        TEGRA_PINGROUP_GMI_OE_N,
-        TEGRA_PINGROUP_GMI_DQS,
-        TEGRA_PINGROUP_GMI_RST_N,
-        TEGRA_PINGROUP_GEN2_I2C_SCL,
-        TEGRA_PINGROUP_GEN2_I2C_SDA,
-        TEGRA_PINGROUP_SDMMC4_CLK,
-        TEGRA_PINGROUP_SDMMC4_CMD,
-        TEGRA_PINGROUP_SDMMC4_DAT0,
-        TEGRA_PINGROUP_SDMMC4_DAT1,
-        TEGRA_PINGROUP_SDMMC4_DAT2,
-        TEGRA_PINGROUP_SDMMC4_DAT3,
-        TEGRA_PINGROUP_SDMMC4_DAT4,
-        TEGRA_PINGROUP_SDMMC4_DAT5,
-        TEGRA_PINGROUP_SDMMC4_DAT6,
-        TEGRA_PINGROUP_SDMMC4_DAT7,
-        TEGRA_PINGROUP_SDMMC4_RST_N,
-        TEGRA_PINGROUP_CAM_MCLK,
-        TEGRA_PINGROUP_GPIO_PCC1,
-        TEGRA_PINGROUP_GPIO_PBB0,
-        TEGRA_PINGROUP_CAM_I2C_SCL,
-        TEGRA_PINGROUP_CAM_I2C_SDA,
-        TEGRA_PINGROUP_GPIO_PBB3,
-        TEGRA_PINGROUP_GPIO_PBB4,
-        TEGRA_PINGROUP_GPIO_PBB5,
-        TEGRA_PINGROUP_GPIO_PBB6,
-        TEGRA_PINGROUP_GPIO_PBB7,
-        TEGRA_PINGROUP_GPIO_PCC2,
-        TEGRA_PINGROUP_JTAG_RTCK,
-        TEGRA_PINGROUP_PWR_I2C_SCL,
-        TEGRA_PINGROUP_PWR_I2C_SDA,
-        TEGRA_PINGROUP_KB_ROW0,
-        TEGRA_PINGROUP_KB_ROW1,
-        TEGRA_PINGROUP_KB_ROW2,
-        TEGRA_PINGROUP_KB_ROW3,
-        TEGRA_PINGROUP_KB_ROW4,
-        TEGRA_PINGROUP_KB_ROW5,
-        TEGRA_PINGROUP_KB_ROW6,
-        TEGRA_PINGROUP_KB_ROW7,
-        TEGRA_PINGROUP_KB_ROW8,
-        TEGRA_PINGROUP_KB_ROW9,
-        TEGRA_PINGROUP_KB_ROW10,
-        TEGRA_PINGROUP_KB_ROW11,
-        TEGRA_PINGROUP_KB_ROW12,
-        TEGRA_PINGROUP_KB_ROW13,
-        TEGRA_PINGROUP_KB_ROW14,
-        TEGRA_PINGROUP_KB_ROW15,
-        TEGRA_PINGROUP_KB_COL0,
-        TEGRA_PINGROUP_KB_COL1,
-        TEGRA_PINGROUP_KB_COL2,
-        TEGRA_PINGROUP_KB_COL3,
-        TEGRA_PINGROUP_KB_COL4,
-        TEGRA_PINGROUP_KB_COL5,
-        TEGRA_PINGROUP_KB_COL6,
-        TEGRA_PINGROUP_KB_COL7,
-        TEGRA_PINGROUP_CLK_32K_OUT,
-        TEGRA_PINGROUP_SYS_CLK_REQ,
-        TEGRA_PINGROUP_CORE_PWR_REQ,
-        TEGRA_PINGROUP_CPU_PWR_REQ,
-        TEGRA_PINGROUP_PWR_INT_N,
-        TEGRA_PINGROUP_CLK_32K_IN,
-        TEGRA_PINGROUP_OWR,
-        TEGRA_PINGROUP_DAP1_FS,
-        TEGRA_PINGROUP_DAP1_DIN,
-        TEGRA_PINGROUP_DAP1_DOUT,
-        TEGRA_PINGROUP_DAP1_SCLK,
-        TEGRA_PINGROUP_CLK1_REQ,
-        TEGRA_PINGROUP_CLK1_OUT,
-        TEGRA_PINGROUP_SPDIF_IN,
-        TEGRA_PINGROUP_SPDIF_OUT,
-        TEGRA_PINGROUP_DAP2_FS,
-        TEGRA_PINGROUP_DAP2_DIN,
-        TEGRA_PINGROUP_DAP2_DOUT,
-        TEGRA_PINGROUP_DAP2_SCLK,
-        TEGRA_PINGROUP_SPI2_MOSI,
-        TEGRA_PINGROUP_SPI2_MISO,
-        TEGRA_PINGROUP_SPI2_CS0_N,
-        TEGRA_PINGROUP_SPI2_SCK,
-        TEGRA_PINGROUP_SPI1_MOSI,
-        TEGRA_PINGROUP_SPI1_SCK,
-        TEGRA_PINGROUP_SPI1_CS0_N,
-        TEGRA_PINGROUP_SPI1_MISO,
-        TEGRA_PINGROUP_SPI2_CS1_N,
-        TEGRA_PINGROUP_SPI2_CS2_N,
-        TEGRA_PINGROUP_SDMMC3_CLK,
-        TEGRA_PINGROUP_SDMMC3_CMD,
-        TEGRA_PINGROUP_SDMMC3_DAT0,
-        TEGRA_PINGROUP_SDMMC3_DAT1,
-        TEGRA_PINGROUP_SDMMC3_DAT2,
-        TEGRA_PINGROUP_SDMMC3_DAT3,
-        TEGRA_PINGROUP_SDMMC3_DAT4,
-        TEGRA_PINGROUP_SDMMC3_DAT5,
-        TEGRA_PINGROUP_SDMMC3_DAT6,
-        TEGRA_PINGROUP_SDMMC3_DAT7,
-        TEGRA_PINGROUP_PEX_L0_PRSNT_N,
-        TEGRA_PINGROUP_PEX_L0_RST_N,
-        TEGRA_PINGROUP_PEX_L0_CLKREQ_N,
-        TEGRA_PINGROUP_PEX_WAKE_N,
-        TEGRA_PINGROUP_PEX_L1_PRSNT_N,
-        TEGRA_PINGROUP_PEX_L1_RST_N,
-        TEGRA_PINGROUP_PEX_L1_CLKREQ_N,
-        TEGRA_PINGROUP_PEX_L2_PRSNT_N,
-        TEGRA_PINGROUP_PEX_L2_RST_N,
-        TEGRA_PINGROUP_PEX_L2_CLKREQ_N,
-        TEGRA_PINGROUP_HDMI_CEC,
-        TEGRA_MAX_PINGROUP,
-};
-
-enum tegra_drive_pingroup {
-        TEGRA_DRIVE_PINGROUP_AO1 = 0,
-        TEGRA_DRIVE_PINGROUP_AO2,
-        TEGRA_DRIVE_PINGROUP_AT1,
-        TEGRA_DRIVE_PINGROUP_AT2,
-        TEGRA_DRIVE_PINGROUP_AT3,
-        TEGRA_DRIVE_PINGROUP_AT4,
-        TEGRA_DRIVE_PINGROUP_AT5,
-        TEGRA_DRIVE_PINGROUP_CDEV1,
-        TEGRA_DRIVE_PINGROUP_CDEV2,
-        TEGRA_DRIVE_PINGROUP_CSUS,
-        TEGRA_DRIVE_PINGROUP_DAP1,
-        TEGRA_DRIVE_PINGROUP_DAP2,
-        TEGRA_DRIVE_PINGROUP_DAP3,
-        TEGRA_DRIVE_PINGROUP_DAP4,
-        TEGRA_DRIVE_PINGROUP_DBG,
-        TEGRA_DRIVE_PINGROUP_LCD1,
-        TEGRA_DRIVE_PINGROUP_LCD2,
-        TEGRA_DRIVE_PINGROUP_SDIO2,
-        TEGRA_DRIVE_PINGROUP_SDIO3,
-        TEGRA_DRIVE_PINGROUP_SPI,
-        TEGRA_DRIVE_PINGROUP_UAA,
-        TEGRA_DRIVE_PINGROUP_UAB,
-        TEGRA_DRIVE_PINGROUP_UART2,
-        TEGRA_DRIVE_PINGROUP_UART3,
-        TEGRA_DRIVE_PINGROUP_VI1,
-        TEGRA_DRIVE_PINGROUP_SDIO1,
-        TEGRA_DRIVE_PINGROUP_CRT,
-        TEGRA_DRIVE_PINGROUP_DDC,
-        TEGRA_DRIVE_PINGROUP_GMA,
-        TEGRA_DRIVE_PINGROUP_GMB,
-        TEGRA_DRIVE_PINGROUP_GMC,
-        TEGRA_DRIVE_PINGROUP_GMD,
-        TEGRA_DRIVE_PINGROUP_GME,
-        TEGRA_DRIVE_PINGROUP_GMF,
-        TEGRA_DRIVE_PINGROUP_GMG,
-        TEGRA_DRIVE_PINGROUP_GMH,
-        TEGRA_DRIVE_PINGROUP_OWR,
-        TEGRA_DRIVE_PINGROUP_UAD,
-        TEGRA_DRIVE_PINGROUP_GPV,
-        TEGRA_DRIVE_PINGROUP_DEV3,
-        TEGRA_DRIVE_PINGROUP_CEC,
-        TEGRA_MAX_DRIVE_PINGROUP,
-};
-
-#endif
-
diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h
deleted file mode 100644
index 055f1792c8ff..000000000000
--- a/arch/arm/mach-tegra/include/mach/pinmux.h
+++ /dev/null
@@ -1,302 +0,0 @@
-/*
- * linux/arch/arm/mach-tegra/include/mach/pinmux.h
- *
- * Copyright (C) 2010 Google, Inc.
- * Copyright (C) 2010,2011 Nvidia, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_TEGRA_PINMUX_H
-#define __MACH_TEGRA_PINMUX_H
-
-enum tegra_mux_func {
-        TEGRA_MUX_RSVD = 0x8000,
-        TEGRA_MUX_RSVD1 = 0x8000,
-        TEGRA_MUX_RSVD2 = 0x8001,
-        TEGRA_MUX_RSVD3 = 0x8002,
-        TEGRA_MUX_RSVD4 = 0x8003,
-        TEGRA_MUX_INVALID = 0x4000,
-        TEGRA_MUX_NONE = -1,
-        TEGRA_MUX_AHB_CLK,
-        TEGRA_MUX_APB_CLK,
-        TEGRA_MUX_AUDIO_SYNC,
-        TEGRA_MUX_CRT,
-        TEGRA_MUX_DAP1,
-        TEGRA_MUX_DAP2,
-        TEGRA_MUX_DAP3,
-        TEGRA_MUX_DAP4,
-        TEGRA_MUX_DAP5,
-        TEGRA_MUX_DISPLAYA,
-        TEGRA_MUX_DISPLAYB,
-        TEGRA_MUX_EMC_TEST0_DLL,
-        TEGRA_MUX_EMC_TEST1_DLL,
-        TEGRA_MUX_GMI,
-        TEGRA_MUX_GMI_INT,
-        TEGRA_MUX_HDMI,
-        TEGRA_MUX_I2C,
-        TEGRA_MUX_I2C2,
-        TEGRA_MUX_I2C3,
-        TEGRA_MUX_IDE,
-        TEGRA_MUX_IRDA,
-        TEGRA_MUX_KBC,
-        TEGRA_MUX_MIO,
-        TEGRA_MUX_MIPI_HS,
-        TEGRA_MUX_NAND,
-        TEGRA_MUX_OSC,
-        TEGRA_MUX_OWR,
-        TEGRA_MUX_PCIE,
-        TEGRA_MUX_PLLA_OUT,
-        TEGRA_MUX_PLLC_OUT1,
-        TEGRA_MUX_PLLM_OUT1,
-        TEGRA_MUX_PLLP_OUT2,
-        TEGRA_MUX_PLLP_OUT3,
-        TEGRA_MUX_PLLP_OUT4,
-        TEGRA_MUX_PWM,
-        TEGRA_MUX_PWR_INTR,
-        TEGRA_MUX_PWR_ON,
-        TEGRA_MUX_RTCK,
-        TEGRA_MUX_SDIO1,
-        TEGRA_MUX_SDIO2,
-        TEGRA_MUX_SDIO3,
-        TEGRA_MUX_SDIO4,
-        TEGRA_MUX_SFLASH,
-        TEGRA_MUX_SPDIF,
-        TEGRA_MUX_SPI1,
-        TEGRA_MUX_SPI2,
-        TEGRA_MUX_SPI2_ALT,
-        TEGRA_MUX_SPI3,
-        TEGRA_MUX_SPI4,
-        TEGRA_MUX_TRACE,
-        TEGRA_MUX_TWC,
-        TEGRA_MUX_UARTA,
-        TEGRA_MUX_UARTB,
-        TEGRA_MUX_UARTC,
-        TEGRA_MUX_UARTD,
-        TEGRA_MUX_UARTE,
-        TEGRA_MUX_ULPI,
-        TEGRA_MUX_VI,
-        TEGRA_MUX_VI_SENSOR_CLK,
-        TEGRA_MUX_XIO,
-        TEGRA_MUX_BLINK,
-        TEGRA_MUX_CEC,
-        TEGRA_MUX_CLK12,
-        TEGRA_MUX_DAP,
-        TEGRA_MUX_DAPSDMMC2,
-        TEGRA_MUX_DDR,
-        TEGRA_MUX_DEV3,
-        TEGRA_MUX_DTV,
-        TEGRA_MUX_VI_ALT1,
-        TEGRA_MUX_VI_ALT2,
-        TEGRA_MUX_VI_ALT3,
-        TEGRA_MUX_EMC_DLL,
-        TEGRA_MUX_EXTPERIPH1,
-        TEGRA_MUX_EXTPERIPH2,
-        TEGRA_MUX_EXTPERIPH3,
-        TEGRA_MUX_GMI_ALT,
-        TEGRA_MUX_HDA,
-        TEGRA_MUX_HSI,
-        TEGRA_MUX_I2C4,
-        TEGRA_MUX_I2C5,
-        TEGRA_MUX_I2CPWR,
-        TEGRA_MUX_I2S0,
-        TEGRA_MUX_I2S1,
-        TEGRA_MUX_I2S2,
-        TEGRA_MUX_I2S3,
-        TEGRA_MUX_I2S4,
-        TEGRA_MUX_NAND_ALT,
-        TEGRA_MUX_POPSDIO4,
-        TEGRA_MUX_POPSDMMC4,
-        TEGRA_MUX_PWM0,
-        TEGRA_MUX_PWM1,
-        TEGRA_MUX_PWM2,
-        TEGRA_MUX_PWM3,
-        TEGRA_MUX_SATA,
-        TEGRA_MUX_SPI5,
-        TEGRA_MUX_SPI6,
-        TEGRA_MUX_SYSCLK,
-        TEGRA_MUX_VGP1,
-        TEGRA_MUX_VGP2,
-        TEGRA_MUX_VGP3,
-        TEGRA_MUX_VGP4,
-        TEGRA_MUX_VGP5,
-        TEGRA_MUX_VGP6,
-        TEGRA_MUX_SAFE,
-        TEGRA_MAX_MUX,
-};
-
-enum tegra_pullupdown {
-        TEGRA_PUPD_NORMAL = 0,
-        TEGRA_PUPD_PULL_DOWN,
-        TEGRA_PUPD_PULL_UP,
-};
-
-enum tegra_tristate {
-        TEGRA_TRI_NORMAL = 0,
-        TEGRA_TRI_TRISTATE = 1,
-};
-
-enum tegra_pin_io {
-        TEGRA_PIN_OUTPUT = 0,
-        TEGRA_PIN_INPUT = 1,
-};
-
-enum tegra_vddio {
-        TEGRA_VDDIO_BB = 0,
-        TEGRA_VDDIO_LCD,
-        TEGRA_VDDIO_VI,
-        TEGRA_VDDIO_UART,
-        TEGRA_VDDIO_DDR,
-        TEGRA_VDDIO_NAND,
-        TEGRA_VDDIO_SYS,
-        TEGRA_VDDIO_AUDIO,
-        TEGRA_VDDIO_SD,
-        TEGRA_VDDIO_CAM,
-        TEGRA_VDDIO_GMI,
-        TEGRA_VDDIO_PEXCTL,
-        TEGRA_VDDIO_SDMMC1,
-        TEGRA_VDDIO_SDMMC3,
-        TEGRA_VDDIO_SDMMC4,
-};
-
-struct tegra_pingroup_config {
-        int pingroup;
-        enum tegra_mux_func     func;
-        enum tegra_pullupdown   pupd;
-        enum tegra_tristate     tristate;
-};
-
-enum tegra_slew {
-        TEGRA_SLEW_FASTEST = 0,
-        TEGRA_SLEW_FAST,
-        TEGRA_SLEW_SLOW,
-        TEGRA_SLEW_SLOWEST,
-        TEGRA_MAX_SLEW,
-};
-
-enum tegra_pull_strength {
-        TEGRA_PULL_0 = 0,
-        TEGRA_PULL_1,
-        TEGRA_PULL_2,
-        TEGRA_PULL_3,
-        TEGRA_PULL_4,
-        TEGRA_PULL_5,
-        TEGRA_PULL_6,
-        TEGRA_PULL_7,
-        TEGRA_PULL_8,
-        TEGRA_PULL_9,
-        TEGRA_PULL_10,
-        TEGRA_PULL_11,
-        TEGRA_PULL_12,
-        TEGRA_PULL_13,
-        TEGRA_PULL_14,
-        TEGRA_PULL_15,
-        TEGRA_PULL_16,
-        TEGRA_PULL_17,
-        TEGRA_PULL_18,
-        TEGRA_PULL_19,
-        TEGRA_PULL_20,
-        TEGRA_PULL_21,
-        TEGRA_PULL_22,
-        TEGRA_PULL_23,
-        TEGRA_PULL_24,
-        TEGRA_PULL_25,
-        TEGRA_PULL_26,
-        TEGRA_PULL_27,
-        TEGRA_PULL_28,
-        TEGRA_PULL_29,
-        TEGRA_PULL_30,
-        TEGRA_PULL_31,
-        TEGRA_MAX_PULL,
-};
-
-enum tegra_drive {
-        TEGRA_DRIVE_DIV_8 = 0,
-        TEGRA_DRIVE_DIV_4,
-        TEGRA_DRIVE_DIV_2,
-        TEGRA_DRIVE_DIV_1,
-        TEGRA_MAX_DRIVE,
-};
-
-enum tegra_hsm {
-        TEGRA_HSM_DISABLE = 0,
-        TEGRA_HSM_ENABLE,
-};
-
-enum tegra_schmitt {
-        TEGRA_SCHMITT_DISABLE = 0,
-        TEGRA_SCHMITT_ENABLE,
-};
-
-struct tegra_drive_pingroup_config {
-        int pingroup;
-        enum tegra_hsm hsm;
-        enum tegra_schmitt schmitt;
-        enum tegra_drive drive;
-        enum tegra_pull_strength pull_down;
-        enum tegra_pull_strength pull_up;
-        enum tegra_slew slew_rising;
-        enum tegra_slew slew_falling;
-};
-
-struct tegra_drive_pingroup_desc {
-        const char *name;
-        s16 reg_bank;
-        s16 reg;
-};
-
-struct tegra_pingroup_desc {
-        const char *name;
-        int funcs[4];
-        int func_safe;
-        int vddio;
-        enum tegra_pin_io io_default;
-        s16 tri_bank;   /* Register bank the tri_reg exists within */
-        s16 mux_bank;   /* Register bank the mux_reg exists within */
-        s16 pupd_bank;  /* Register bank the pupd_reg exists within */
-        s16 tri_reg;    /* offset into the TRISTATE_REG_* register bank */
-        s16 mux_reg;    /* offset into the PIN_MUX_CTL_* register bank */
-        s16 pupd_reg;   /* offset into the PULL_UPDOWN_REG_* register bank */
-        s8 tri_bit;     /* offset into the TRISTATE_REG_* register bit */
-        s8 mux_bit;     /* offset into the PIN_MUX_CTL_* register bit */
-        s8 pupd_bit;    /* offset into the PULL_UPDOWN_REG_* register bit */
-        s8 lock_bit;    /* offset of the LOCK bit into mux register bit */
-        s8 od_bit;      /* offset of the OD bit into mux register bit */
-        s8 ioreset_bit; /* offset of the IO_RESET bit into mux register bit */
-};
-
-typedef void (*pinmux_init) (const struct tegra_pingroup_desc **pg,
-        int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
-        int *pgdrive_max);
-
-void tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
-        const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
-
-void tegra30_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
-        const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
-
-int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate);
-int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd);
-
-void tegra_pinmux_config_table(const struct tegra_pingroup_config *config,
-        int len);
-
-void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
-        int len);
-void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
-        int len);
-void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
-        int len);
-void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
-        int len, enum tegra_tristate tristate);
-void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
-        int len, enum tegra_pullupdown pupd);
-#endif
diff --git a/arch/arm/mach-tegra/pinmux-tegra20-tables.c b/arch/arm/mach-tegra/pinmux-tegra20-tables.c
deleted file mode 100644
index 734add1280b7..000000000000
--- a/arch/arm/mach-tegra/pinmux-tegra20-tables.c
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
- * linux/arch/arm/mach-tegra/pinmux-tegra20-tables.c
- *
- * Common pinmux configurations for Tegra20 SoCs
- *
- * Copyright (C) 2010 NVIDIA Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/spinlock.h>
-#include <linux/io.h>
-#include <linux/init.h>
-#include <linux/string.h>
-
-#include <mach/iomap.h>
-#include <mach/pinmux.h>
-#include <mach/pinmux-tegra20.h>
-#include <mach/suspend.h>
-
-#define TRISTATE_REG_A          0x14
-#define PIN_MUX_CTL_REG_A       0x80
-#define PULLUPDOWN_REG_A        0xa0
-#define PINGROUP_REG_A          0x868
-
-#define DRIVE_PINGROUP(pg_name, r)                              \
-        [TEGRA_DRIVE_PINGROUP_ ## pg_name] = {                  \
-                .name = #pg_name,                               \
-                .reg_bank = 3,                                  \
-                .reg = ((r) - PINGROUP_REG_A)                   \
-        }
-
-static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
-        DRIVE_PINGROUP(AO1,             0x868),
-        DRIVE_PINGROUP(AO2,             0x86c),
-        DRIVE_PINGROUP(AT1,             0x870),
-        DRIVE_PINGROUP(AT2,             0x874),
-        DRIVE_PINGROUP(CDEV1,           0x878),
-        DRIVE_PINGROUP(CDEV2,           0x87c),
-        DRIVE_PINGROUP(CSUS,            0x880),
-        DRIVE_PINGROUP(DAP1,            0x884),
-        DRIVE_PINGROUP(DAP2,            0x888),
-        DRIVE_PINGROUP(DAP3,            0x88c),
-        DRIVE_PINGROUP(DAP4,            0x890),
-        DRIVE_PINGROUP(DBG,             0x894),
-        DRIVE_PINGROUP(LCD1,            0x898),
-        DRIVE_PINGROUP(LCD2,            0x89c),
-        DRIVE_PINGROUP(SDMMC2,          0x8a0),
-        DRIVE_PINGROUP(SDMMC3,          0x8a4),
-        DRIVE_PINGROUP(SPI,             0x8a8),
-        DRIVE_PINGROUP(UAA,             0x8ac),
-        DRIVE_PINGROUP(UAB,             0x8b0),
-        DRIVE_PINGROUP(UART2,           0x8b4),
-        DRIVE_PINGROUP(UART3,           0x8b8),
-        DRIVE_PINGROUP(VI1,             0x8bc),
-        DRIVE_PINGROUP(VI2,             0x8c0),
-        DRIVE_PINGROUP(XM2A,            0x8c4),
-        DRIVE_PINGROUP(XM2C,            0x8c8),
-        DRIVE_PINGROUP(XM2D,            0x8cc),
-        DRIVE_PINGROUP(XM2CLK,          0x8d0),
-        DRIVE_PINGROUP(MEMCOMP,         0x8d4),
-        DRIVE_PINGROUP(SDIO1,           0x8e0),
-        DRIVE_PINGROUP(CRT,             0x8ec),
-        DRIVE_PINGROUP(DDC,             0x8f0),
-        DRIVE_PINGROUP(GMA,             0x8f4),
-        DRIVE_PINGROUP(GMB,             0x8f8),
-        DRIVE_PINGROUP(GMC,             0x8fc),
-        DRIVE_PINGROUP(GMD,             0x900),
-        DRIVE_PINGROUP(GME,             0x904),
-        DRIVE_PINGROUP(OWR,             0x908),
-        DRIVE_PINGROUP(UAD,             0x90c),
-};
-
-#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, f_safe,          \
-                 tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b)    \
-        [TEGRA_PINGROUP_ ## pg_name] = {                        \
-                .name = #pg_name,                               \
-                .vddio = TEGRA_VDDIO_ ## vdd,                   \
-                .funcs = {                                      \
-                        TEGRA_MUX_ ## f0,                       \
-                        TEGRA_MUX_ ## f1,                       \
-                        TEGRA_MUX_ ## f2,                       \
-                        TEGRA_MUX_ ## f3,                       \
-                },                                              \
-                .func_safe = TEGRA_MUX_ ## f_safe,              \
-                .tri_bank = 0,                                  \
-                .tri_reg = ((tri_r) - TRISTATE_REG_A),          \
-                .tri_bit = tri_b,                               \
-                .mux_bank = 1,                                  \
-                .mux_reg = ((mux_r) - PIN_MUX_CTL_REG_A),       \
-                .mux_bit = mux_b,                               \
-                .pupd_bank = 2,                         \
-                .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A),      \
-                .pupd_bit = pupd_b,                             \
-                .lock_bit = -1,                                 \
-                .od_bit = -1,                                   \
-                .ioreset_bit = -1,                              \
-                .io_default = -1,                               \
-        }
-
-static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
-        PINGROUP(ATA,   NAND,  IDE,       NAND,      GMI,       RSVD,          IDE,       0x14, 0,  0x80, 24, 0xA0, 0),
-        PINGROUP(ATB,   NAND,  IDE,       NAND,      GMI,       SDIO4,         IDE,       0x14, 1,  0x80, 16, 0xA0, 2),
-        PINGROUP(ATC,   NAND,  IDE,       NAND,      GMI,       SDIO4,         IDE,       0x14, 2,  0x80, 22, 0xA0, 4),
-        PINGROUP(ATD,   NAND,  IDE,       NAND,      GMI,       SDIO4,         IDE,       0x14, 3,  0x80, 20, 0xA0, 6),
-        PINGROUP(ATE,   NAND,  IDE,       NAND,      GMI,       RSVD,          IDE,       0x18, 25, 0x80, 12, 0xA0, 8),
-        PINGROUP(CDEV1, AUDIO, OSC,       PLLA_OUT,  PLLM_OUT1, AUDIO_SYNC,    OSC,       0x14, 4,  0x88, 2,  0xA8, 0),
-        PINGROUP(CDEV2, AUDIO, OSC,       AHB_CLK,   APB_CLK,   PLLP_OUT4,     OSC,       0x14, 5,  0x88, 4,  0xA8, 2),
-        PINGROUP(CRTP,  LCD,   CRT,       RSVD,      RSVD,      RSVD,          RSVD,      0x20, 14, 0x98, 20, 0xA4, 24),
-        PINGROUP(CSUS,  VI,    PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, PLLC_OUT1, 0x14, 6,  0x88, 6,  0xAC, 24),
-        PINGROUP(DAP1,  AUDIO, DAP1,      RSVD,      GMI,       SDIO2,         DAP1,      0x14, 7,  0x88, 20, 0xA0, 10),
-        PINGROUP(DAP2,  AUDIO, DAP2,      TWC,       RSVD,      GMI,           DAP2,      0x14, 8,  0x88, 22, 0xA0, 12),
-        PINGROUP(DAP3,  BB,    DAP3,      RSVD,      RSVD,      RSVD,          DAP3,      0x14, 9,  0x88, 24, 0xA0, 14),
-        PINGROUP(DAP4,  UART,  DAP4,      RSVD,      GMI,       RSVD,          DAP4,      0x14, 10, 0x88, 26, 0xA0, 16),
-        PINGROUP(DDC,   LCD,   I2C2,      RSVD,      RSVD,      RSVD,          RSVD4,     0x18, 31, 0x88, 0,  0xB0, 28),
-        PINGROUP(DTA,   VI,    RSVD,      SDIO2,     VI,        RSVD,          RSVD4,     0x14, 11, 0x84, 20, 0xA0, 18),
-        PINGROUP(DTB,   VI,    RSVD,      RSVD,      VI,        SPI1,          RSVD1,     0x14, 12, 0x84, 22, 0xA0, 20),
-        PINGROUP(DTC,   VI,    RSVD,      RSVD,      VI,        RSVD,          RSVD1,     0x14, 13, 0x84, 26, 0xA0, 22),
-        PINGROUP(DTD,   VI,    RSVD,      SDIO2,     VI,        RSVD,          RSVD1,     0x14, 14, 0x84, 28, 0xA0, 24),
-        PINGROUP(DTE,   VI,    RSVD,      RSVD,      VI,        SPI1,          RSVD1,     0x14, 15, 0x84, 30, 0xA0, 26),
-        PINGROUP(DTF,   VI,    I2C3,      RSVD,      VI,        RSVD,          RSVD4,     0x20, 12, 0x98, 30, 0xA0, 28),
-        PINGROUP(GMA,   NAND,  UARTE,     SPI3,      GMI,       SDIO4,         SPI3,      0x14, 28, 0x84, 0,  0xB0, 20),
-        PINGROUP(GMB,   NAND,  IDE,       NAND,      GMI,       GMI_INT,       GMI,       0x18, 29, 0x88, 28, 0xB0, 22),
-        PINGROUP(GMC,   NAND,  UARTD,     SPI4,      GMI,       SFLASH,        SPI4,      0x14, 29, 0x84, 2,  0xB0, 24),
-        PINGROUP(GMD,   NAND,  RSVD,      NAND,      GMI,       SFLASH,        GMI,       0x18, 30, 0x88, 30, 0xB0, 26),
-        PINGROUP(GME,   NAND,  RSVD,      DAP5,      GMI,       SDIO4,         GMI,       0x18, 0,  0x8C, 0,  0xA8, 24),
-        PINGROUP(GPU,   UART,  PWM,       UARTA,     GMI,       RSVD,          RSVD4,     0x14, 16, 0x8C, 4,  0xA4, 20),
-        PINGROUP(GPU7,  SYS,   RTCK,      RSVD,      RSVD,      RSVD,          RTCK,      0x20, 11, 0x98, 28, 0xA4, 6),
-        PINGROUP(GPV,   SD,    PCIE,      RSVD,      RSVD,      RSVD,          PCIE,      0x14, 17, 0x8C, 2,  0xA0, 30),
-        PINGROUP(HDINT, LCD,   HDMI,      RSVD,      RSVD,      RSVD,          HDMI,      0x1C, 23, 0x84, 4,  0xAC, 22),
-        PINGROUP(I2CP,  SYS,   I2C,       RSVD,      RSVD,      RSVD,          RSVD4,     0x14, 18, 0x88, 8,  0xA4, 2),
-        PINGROUP(IRRX,  UART,  UARTA,     UARTB,     GMI,       SPI4,          UARTB,     0x14, 20, 0x88, 18, 0xA8, 22),
-        PINGROUP(IRTX,  UART,  UARTA,     UARTB,     GMI,       SPI4,          UARTB,     0x14, 19, 0x88, 16, 0xA8, 20),
-        PINGROUP(KBCA,  SYS,   KBC,       NAND,      SDIO2,     EMC_TEST0_DLL, KBC,       0x14, 22, 0x88, 10, 0xA4, 8),
-        PINGROUP(KBCB,  SYS,   KBC,       NAND,      SDIO2,     MIO,           KBC,       0x14, 21, 0x88, 12, 0xA4, 10),
-        PINGROUP(KBCC,  SYS,   KBC,       NAND,      TRACE,     EMC_TEST1_DLL, KBC,       0x18, 26, 0x88, 14, 0xA4, 12),
-        PINGROUP(KBCD,  SYS,   KBC,       NAND,      SDIO2,     MIO,           KBC,       0x20, 10, 0x98, 26, 0xA4, 14),
-        PINGROUP(KBCE,  SYS,   KBC,       NAND,      OWR,       RSVD,          KBC,       0x14, 26, 0x80, 28, 0xB0, 2),
-        PINGROUP(KBCF,  SYS,   KBC,       NAND,      TRACE,     MIO,           KBC,       0x14, 27, 0x80, 26, 0xB0, 0),
-        PINGROUP(LCSN,  LCD,   DISPLAYA,  DISPLAYB,  SPI3,      RSVD,          RSVD4,     0x1C, 31, 0x90, 12, 0xAC, 20),
-        PINGROUP(LD0,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 0,  0x94, 0,  0xAC, 12),
-        PINGROUP(LD1,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 1,  0x94, 2,  0xAC, 12),
-        PINGROUP(LD10,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 10, 0x94, 20, 0xAC, 12),
-        PINGROUP(LD11,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 11, 0x94, 22, 0xAC, 12),
-        PINGROUP(LD12,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 12, 0x94, 24, 0xAC, 12),
-        PINGROUP(LD13,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 13, 0x94, 26, 0xAC, 12),
-        PINGROUP(LD14,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 14, 0x94, 28, 0xAC, 12),
-        PINGROUP(LD15,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 15, 0x94, 30, 0xAC, 12),
-        PINGROUP(LD16,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 16, 0x98, 0,  0xAC, 12),
-        PINGROUP(LD17,  LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x1C, 17, 0x98, 2,  0xAC, 12),
-        PINGROUP(LD2,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 2,  0x94, 4,  0xAC, 12),
-        PINGROUP(LD3,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 3,  0x94, 6,  0xAC, 12),
-        PINGROUP(LD4,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 4,  0x94, 8,  0xAC, 12),
-        PINGROUP(LD5,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 5,  0x94, 10, 0xAC, 12),
-        PINGROUP(LD6,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 6,  0x94, 12, 0xAC, 12),
-        PINGROUP(LD7,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 7,  0x94, 14, 0xAC, 12),
-        PINGROUP(LD8,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 8,  0x94, 16, 0xAC, 12),
-        PINGROUP(LD9,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 9,  0x94, 18, 0xAC, 12),
-        PINGROUP(LDC,   LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x1C, 30, 0x90, 14, 0xAC, 20),
-        PINGROUP(LDI,   LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x20, 6,  0x98, 16, 0xAC, 18),
-        PINGROUP(LHP0,  LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x1C, 18, 0x98, 10, 0xAC, 16),
-        PINGROUP(LHP1,  LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x1C, 19, 0x98, 4,  0xAC, 14),
-        PINGROUP(LHP2,  LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x1C, 20, 0x98, 6,  0xAC, 14),
-        PINGROUP(LHS,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x20, 7,  0x90, 22, 0xAC, 22),
-        PINGROUP(LM0,   LCD,   DISPLAYA,  DISPLAYB,  SPI3,      RSVD,          RSVD4,     0x1C, 24, 0x90, 26, 0xAC, 22),
-        PINGROUP(LM1,   LCD,   DISPLAYA,  DISPLAYB,  RSVD,      CRT,           RSVD3,     0x1C, 25, 0x90, 28, 0xAC, 22),
-        PINGROUP(LPP,   LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x20, 8,  0x98, 14, 0xAC, 18),
-        PINGROUP(LPW0,  LCD,   DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          DISPLAYA,  0x20, 3,  0x90, 0,  0xAC, 20),
-        PINGROUP(LPW1,  LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x20, 4,  0x90, 2,  0xAC, 20),
-        PINGROUP(LPW2,  LCD,   DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          DISPLAYA,  0x20, 5,  0x90, 4,  0xAC, 20),
-        PINGROUP(LSC0,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 27, 0x90, 18, 0xAC, 22),
-        PINGROUP(LSC1,  LCD,   DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          DISPLAYA,  0x1C, 28, 0x90, 20, 0xAC, 20),
-        PINGROUP(LSCK,  LCD,   DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          DISPLAYA,  0x1C, 29, 0x90, 16, 0xAC, 20),
-        PINGROUP(LSDA,  LCD,   DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          DISPLAYA,  0x20, 1,  0x90, 8,  0xAC, 20),
-        PINGROUP(LSDI,  LCD,   DISPLAYA,  DISPLAYB,  SPI3,      RSVD,          DISPLAYA,  0x20, 2,  0x90, 6,  0xAC, 20),
-        PINGROUP(LSPI,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       HDMI,          DISPLAYA,  0x20, 0,  0x90, 10, 0xAC, 22),
-        PINGROUP(LVP0,  LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x1C, 21, 0x90, 30, 0xAC, 22),
-        PINGROUP(LVP1,  LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x1C, 22, 0x98, 8,  0xAC, 16),
-        PINGROUP(LVS,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 26, 0x90, 24, 0xAC, 22),
-        PINGROUP(OWC,   SYS,   OWR,       RSVD,      RSVD,      RSVD,          OWR,       0x14, 31, 0x84, 8,  0xB0, 30),
-        PINGROUP(PMC,   SYS,   PWR_ON,    PWR_INTR,  RSVD,      RSVD,          PWR_ON,    0x14, 23, 0x98, 18, -1,   -1),
-        PINGROUP(PTA,   NAND,  I2C2,      HDMI,      GMI,       RSVD,          RSVD4,     0x14, 24, 0x98, 22, 0xA4, 4),
-        PINGROUP(RM,    UART,  I2C,       RSVD,      RSVD,      RSVD,          RSVD4,     0x14, 25, 0x80, 14, 0xA4, 0),
-        PINGROUP(SDB,   SD,    UARTA,     PWM,       SDIO3,     SPI2,          PWM,       0x20, 15, 0x8C, 10, -1,   -1),
-        PINGROUP(SDC,   SD,    PWM,       TWC,       SDIO3,     SPI3,          TWC,       0x18, 1,  0x8C, 12, 0xAC, 28),
-        PINGROUP(SDD,   SD,    UARTA,     PWM,       SDIO3,     SPI3,          PWM,       0x18, 2,  0x8C, 14, 0xAC, 30),
-        PINGROUP(SDIO1, BB,    SDIO1,     RSVD,      UARTE,     UARTA,         RSVD2,     0x14, 30, 0x80, 30, 0xB0, 18),
-        PINGROUP(SLXA,  SD,    PCIE,      SPI4,      SDIO3,     SPI2,          PCIE,      0x18, 3,  0x84, 6,  0xA4, 22),
-        PINGROUP(SLXC,  SD,    SPDIF,     SPI4,      SDIO3,     SPI2,          SPI4,      0x18, 5,  0x84, 10, 0xA4, 26),
-        PINGROUP(SLXD,  SD,    SPDIF,     SPI4,      SDIO3,     SPI2,          SPI4,      0x18, 6,  0x84, 12, 0xA4, 28),
-        PINGROUP(SLXK,  SD,    PCIE,      SPI4,      SDIO3,     SPI2,          PCIE,      0x18, 7,  0x84, 14, 0xA4, 30),
-        PINGROUP(SPDI,  AUDIO, SPDIF,     RSVD,      I2C,       SDIO2,         RSVD2,     0x18, 8,  0x8C, 8,  0xA4, 16),
-        PINGROUP(SPDO,  AUDIO, SPDIF,     RSVD,      I2C,       SDIO2,         RSVD2,     0x18, 9,  0x8C, 6,  0xA4, 18),
-        PINGROUP(SPIA,  AUDIO, SPI1,      SPI2,      SPI3,      GMI,           GMI,       0x18, 10, 0x8C, 30, 0xA8, 4),
-        PINGROUP(SPIB,  AUDIO, SPI1,      SPI2,      SPI3,      GMI,           GMI,       0x18, 11, 0x8C, 28, 0xA8, 6),
-        PINGROUP(SPIC,  AUDIO, SPI1,      SPI2,      SPI3,      GMI,           GMI,       0x18, 12, 0x8C, 26, 0xA8, 8),
-        PINGROUP(SPID,  AUDIO, SPI2,      SPI1,      SPI2_ALT,  GMI,           GMI,       0x18, 13, 0x8C, 24, 0xA8, 10),
-        PINGROUP(SPIE,  AUDIO, SPI2,      SPI1,      SPI2_ALT,  GMI,           GMI,       0x18, 14, 0x8C, 22, 0xA8, 12),
-        PINGROUP(SPIF,  AUDIO, SPI3,      SPI1,      SPI2,      RSVD,          RSVD4,     0x18, 15, 0x8C, 20, 0xA8, 14),
-        PINGROUP(SPIG,  AUDIO, SPI3,      SPI2,      SPI2_ALT,  I2C,           SPI2_ALT,  0x18, 16, 0x8C, 18, 0xA8, 16),
-        PINGROUP(SPIH,  AUDIO, SPI3,      SPI2,      SPI2_ALT,  I2C,           SPI2_ALT,  0x18, 17, 0x8C, 16, 0xA8, 18),
-        PINGROUP(UAA,   BB,    SPI3,      MIPI_HS,   UARTA,     ULPI,          MIPI_HS,   0x18, 18, 0x80, 0,  0xAC, 0),
-        PINGROUP(UAB,   BB,    SPI2,      MIPI_HS,   UARTA,     ULPI,          MIPI_HS,   0x18, 19, 0x80, 2,  0xAC, 2),
-        PINGROUP(UAC,   BB,    OWR,       RSVD,      RSVD,      RSVD,          RSVD4,     0x18, 20, 0x80, 4,  0xAC, 4),
-        PINGROUP(UAD,   UART,  IRDA,      SPDIF,     UARTA,     SPI4,          SPDIF,     0x18, 21, 0x80, 6,  0xAC, 6),
-        PINGROUP(UCA,   UART,  UARTC,     RSVD,      GMI,       RSVD,          RSVD4,     0x18, 22, 0x84, 16, 0xAC, 8),
-        PINGROUP(UCB,   UART,  UARTC,     PWM,       GMI,       RSVD,          RSVD4,     0x18, 23, 0x84, 18, 0xAC, 10),
-        PINGROUP(UDA,   BB,    SPI1,      RSVD,      UARTD,     ULPI,          RSVD2,     0x20, 13, 0x80, 8,  0xB0, 16),
-        /* these pin groups only have pullup and pull down control */
-        PINGROUP(CK32,  SYS,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xB0, 14),
-        PINGROUP(DDRC,  DDR,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xAC, 26),
-        PINGROUP(PMCA,  SYS,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xB0, 4),
-        PINGROUP(PMCB,  SYS,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xB0, 6),
-        PINGROUP(PMCC,  SYS,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xB0, 8),
-        PINGROUP(PMCD,  SYS,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xB0, 10),
-        PINGROUP(PMCE,  SYS,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xB0, 12),
-        PINGROUP(XM2C,  DDR,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xA8, 30),
-        PINGROUP(XM2D,  DDR,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xA8, 28),
-};
-
-void __devinit tegra20_pinmux_init(const struct tegra_pingroup_desc **pg,
-                int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
-                int *pgdrive_max)
-{
-        *pg = tegra_soc_pingroups;
-        *pg_max = TEGRA_MAX_PINGROUP;
-        *pgdrive = tegra_soc_drive_pingroups;
-        *pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
-}
-
diff --git a/arch/arm/mach-tegra/pinmux-tegra30-tables.c b/arch/arm/mach-tegra/pinmux-tegra30-tables.c
deleted file mode 100644
index 14fc0e4c1c44..000000000000
--- a/arch/arm/mach-tegra/pinmux-tegra30-tables.c
+++ /dev/null
@@ -1,376 +0,0 @@
-/*
- * linux/arch/arm/mach-tegra/pinmux-tegra30-tables.c
- *
- * Common pinmux configurations for Tegra30 SoCs
- *
- * Copyright (C) 2010,2011 NVIDIA Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/spinlock.h>
-#include <linux/io.h>
-#include <linux/init.h>
-#include <linux/string.h>
-
-#include <mach/iomap.h>
-#include <mach/pinmux.h>
-#include <mach/pinmux-tegra30.h>
-#include <mach/suspend.h>
-
-#define PINGROUP_REG_A  0x868
-#define MUXCTL_REG_A    0x3000
-
-#define DRIVE_PINGROUP(pg_name, r)              \
-        [TEGRA_DRIVE_PINGROUP_ ## pg_name] = {  \
-                .name = #pg_name,               \
-                .reg_bank = 0,                  \
-                .reg = ((r) - PINGROUP_REG_A)   \
-        }
-
-static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
-        DRIVE_PINGROUP(AO1,             0x868),
-        DRIVE_PINGROUP(AO2,             0x86c),
-        DRIVE_PINGROUP(AT1,             0x870),
-        DRIVE_PINGROUP(AT2,             0x874),
-        DRIVE_PINGROUP(AT3,             0x878),
-        DRIVE_PINGROUP(AT4,             0x87c),
-        DRIVE_PINGROUP(AT5,             0x880),
-        DRIVE_PINGROUP(CDEV1,           0x884),
-        DRIVE_PINGROUP(CDEV2,           0x888),
-        DRIVE_PINGROUP(CSUS,            0x88c),
-        DRIVE_PINGROUP(DAP1,            0x890),
-        DRIVE_PINGROUP(DAP2,            0x894),
-        DRIVE_PINGROUP(DAP3,            0x898),
-        DRIVE_PINGROUP(DAP4,            0x89c),
-        DRIVE_PINGROUP(DBG,             0x8a0),
-        DRIVE_PINGROUP(LCD1,            0x8a4),
-        DRIVE_PINGROUP(LCD2,            0x8a8),
-        DRIVE_PINGROUP(SDIO2,           0x8ac),
-        DRIVE_PINGROUP(SDIO3,           0x8b0),
-        DRIVE_PINGROUP(SPI,             0x8b4),
-        DRIVE_PINGROUP(UAA,             0x8b8),
-        DRIVE_PINGROUP(UAB,             0x8bc),
-        DRIVE_PINGROUP(UART2,           0x8c0),
-        DRIVE_PINGROUP(UART3,           0x8c4),
-        DRIVE_PINGROUP(VI1,             0x8c8),
-        DRIVE_PINGROUP(SDIO1,           0x8ec),
-        DRIVE_PINGROUP(CRT,             0x8f8),
-        DRIVE_PINGROUP(DDC,             0x8fc),
-        DRIVE_PINGROUP(GMA,             0x900),
-        DRIVE_PINGROUP(GMB,             0x904),
-        DRIVE_PINGROUP(GMC,             0x908),
-        DRIVE_PINGROUP(GMD,             0x90c),
-        DRIVE_PINGROUP(GME,             0x910),
-        DRIVE_PINGROUP(GMF,             0x914),
-        DRIVE_PINGROUP(GMG,             0x918),
-        DRIVE_PINGROUP(GMH,             0x91c),
-        DRIVE_PINGROUP(OWR,             0x920),
-        DRIVE_PINGROUP(UAD,             0x924),
-        DRIVE_PINGROUP(GPV,             0x928),
-        DRIVE_PINGROUP(DEV3,            0x92c),
-        DRIVE_PINGROUP(CEC,             0x938),
-};
-
-#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, fs, iod, reg)    \
-        [TEGRA_PINGROUP_ ## pg_name] = {                        \
-                .name = #pg_name,                               \
-                .vddio = TEGRA_VDDIO_ ## vdd,                   \
-                .funcs = {                                      \
-                        TEGRA_MUX_ ## f0,                       \
-                        TEGRA_MUX_ ## f1,                       \
-                        TEGRA_MUX_ ## f2,                       \
-                        TEGRA_MUX_ ## f3,                       \
-                },                                              \
-                .func_safe = TEGRA_MUX_ ## fs,                  \
-                .tri_bank = 1,                                  \
-                .tri_reg = ((reg) - MUXCTL_REG_A),              \
-                .tri_bit = 4,                                   \
-                .mux_bank = 1,                                  \
-                .mux_reg = ((reg) - MUXCTL_REG_A),              \
-                .mux_bit = 0,                                   \
-                .pupd_bank = 1,                                 \
-                .pupd_reg = ((reg) - MUXCTL_REG_A),             \
-                .pupd_bit = 2,                                  \
-                .io_default = TEGRA_PIN_ ## iod,                \
-                .od_bit = 6,                                    \
-                .lock_bit = 7,                                  \
-                .ioreset_bit = 8,                               \
-        }
-
-static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
-        /*       NAME             VDD       f0          f1          f2          f3          fSafe       io      reg */
-        PINGROUP(ULPI_DATA0,      BB,       SPI3,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3000),
-        PINGROUP(ULPI_DATA1,      BB,       SPI3,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3004),
-        PINGROUP(ULPI_DATA2,      BB,       SPI3,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3008),
-        PINGROUP(ULPI_DATA3,      BB,       SPI3,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x300c),
-        PINGROUP(ULPI_DATA4,      BB,       SPI2,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3010),
-        PINGROUP(ULPI_DATA5,      BB,       SPI2,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3014),
-        PINGROUP(ULPI_DATA6,      BB,       SPI2,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3018),
-        PINGROUP(ULPI_DATA7,      BB,       SPI2,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x301c),
-        PINGROUP(ULPI_CLK,        BB,       SPI1,       RSVD,       UARTD,      ULPI,       RSVD,       INPUT,  0x3020),
-        PINGROUP(ULPI_DIR,        BB,       SPI1,       RSVD,       UARTD,      ULPI,       RSVD,       INPUT,  0x3024),
-        PINGROUP(ULPI_NXT,        BB,       SPI1,       RSVD,       UARTD,      ULPI,       RSVD,       INPUT,  0x3028),
-        PINGROUP(ULPI_STP,        BB,       SPI1,       RSVD,       UARTD,      ULPI,       RSVD,       INPUT,  0x302c),
-        PINGROUP(DAP3_FS,         BB,       I2S2,       RSVD1,      DISPLAYA,   DISPLAYB,   RSVD,       INPUT,  0x3030),
-        PINGROUP(DAP3_DIN,        BB,       I2S2,       RSVD1,      DISPLAYA,   DISPLAYB,   RSVD,       INPUT,  0x3034),
-        PINGROUP(DAP3_DOUT,       BB,       I2S2,       RSVD1,      DISPLAYA,   DISPLAYB,   RSVD,       INPUT,  0x3038),
-        PINGROUP(DAP3_SCLK,       BB,       I2S2,       RSVD1,      DISPLAYA,   DISPLAYB,   RSVD,       INPUT,  0x303c),
-        PINGROUP(GPIO_PV0,        BB,       RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3040),
-        PINGROUP(GPIO_PV1,        BB,       RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3044),
-        PINGROUP(SDMMC1_CLK,      SDMMC1,   SDIO1,      RSVD1,      RSVD2,      INVALID,    RSVD,       INPUT,  0x3048),
-        PINGROUP(SDMMC1_CMD,      SDMMC1,   SDIO1,      RSVD1,      RSVD2,      INVALID,    RSVD,       INPUT,  0x304c),
-        PINGROUP(SDMMC1_DAT3,     SDMMC1,   SDIO1,      RSVD1,      UARTE,      INVALID,    RSVD,       INPUT,  0x3050),
-        PINGROUP(SDMMC1_DAT2,     SDMMC1,   SDIO1,      RSVD1,      UARTE,      INVALID,    RSVD,       INPUT,  0x3054),
-        PINGROUP(SDMMC1_DAT1,     SDMMC1,   SDIO1,      RSVD1,      UARTE,      INVALID,    RSVD,       INPUT,  0x3058),
-        PINGROUP(SDMMC1_DAT0,     SDMMC1,   SDIO1,      RSVD1,      UARTE,      INVALID,    RSVD,       INPUT,  0x305c),
-        PINGROUP(GPIO_PV2,        SDMMC1,   OWR,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3060),
-        PINGROUP(GPIO_PV3,        SDMMC1,   INVALID,    RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3064),
-        PINGROUP(CLK2_OUT,        SDMMC1,   EXTPERIPH2, RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3068),
-        PINGROUP(CLK2_REQ,        SDMMC1,   DAP,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x306c),
-        PINGROUP(LCD_PWR1,        LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x3070),
-        PINGROUP(LCD_PWR2,        LCD,      DISPLAYA,   DISPLAYB,   SPI5,       INVALID,    RSVD,       OUTPUT, 0x3074),
-        PINGROUP(LCD_SDIN,        LCD,      DISPLAYA,   DISPLAYB,   SPI5,       RSVD,       RSVD,       OUTPUT, 0x3078),
-        PINGROUP(LCD_SDOUT,       LCD,      DISPLAYA,   DISPLAYB,   SPI5,       INVALID,    RSVD,       OUTPUT, 0x307c),
-        PINGROUP(LCD_WR_N,        LCD,      DISPLAYA,   DISPLAYB,   SPI5,       INVALID,    RSVD,       OUTPUT, 0x3080),
-        PINGROUP(LCD_CS0_N,       LCD,      DISPLAYA,   DISPLAYB,   SPI5,       RSVD,       RSVD,       OUTPUT, 0x3084),
-        PINGROUP(LCD_DC0,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x3088),
-        PINGROUP(LCD_SCK,         LCD,      DISPLAYA,   DISPLAYB,   SPI5,       INVALID,    RSVD,       OUTPUT, 0x308c),
-        PINGROUP(LCD_PWR0,        LCD,      DISPLAYA,   DISPLAYB,   SPI5,       INVALID,    RSVD,       OUTPUT, 0x3090),
-        PINGROUP(LCD_PCLK,        LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x3094),
-        PINGROUP(LCD_DE,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x3098),
-        PINGROUP(LCD_HSYNC,       LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x309c),
-        PINGROUP(LCD_VSYNC,       LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30a0),
-        PINGROUP(LCD_D0,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30a4),
-        PINGROUP(LCD_D1,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30a8),
-        PINGROUP(LCD_D2,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30ac),
-        PINGROUP(LCD_D3,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30b0),
-        PINGROUP(LCD_D4,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30b4),
-        PINGROUP(LCD_D5,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30b8),
-        PINGROUP(LCD_D6,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30bc),
-        PINGROUP(LCD_D7,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30c0),
-        PINGROUP(LCD_D8,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30c4),
-        PINGROUP(LCD_D9,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30c8),
-        PINGROUP(LCD_D10,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30cc),
-        PINGROUP(LCD_D11,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30d0),
-        PINGROUP(LCD_D12,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30d4),
-        PINGROUP(LCD_D13,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30d8),
-        PINGROUP(LCD_D14,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30dc),
-        PINGROUP(LCD_D15,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30e0),
-        PINGROUP(LCD_D16,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30e4),
-        PINGROUP(LCD_D17,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30e8),
-        PINGROUP(LCD_D18,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30ec),
-        PINGROUP(LCD_D19,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30f0),
-        PINGROUP(LCD_D20,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30f4),
-        PINGROUP(LCD_D21,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30f8),
-        PINGROUP(LCD_D22,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30fc),
-        PINGROUP(LCD_D23,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x3100),
-        PINGROUP(LCD_CS1_N,       LCD,      DISPLAYA,   DISPLAYB,   SPI5,       RSVD2,      RSVD,       OUTPUT, 0x3104),
-        PINGROUP(LCD_M1,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x3108),
-        PINGROUP(LCD_DC1,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x310c),
-        PINGROUP(HDMI_INT,        LCD,      RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3110),
-        PINGROUP(DDC_SCL,         LCD,      I2C4,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3114),
-        PINGROUP(DDC_SDA,         LCD,      I2C4,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3118),
-        PINGROUP(CRT_HSYNC,       LCD,      CRT,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x311c),
-        PINGROUP(CRT_VSYNC,       LCD,      CRT,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3120),
-        PINGROUP(VI_D0,           VI,       INVALID,    RSVD1,      VI,         RSVD2,      RSVD,       INPUT,  0x3124),
-        PINGROUP(VI_D1,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3128),
-        PINGROUP(VI_D2,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x312c),
-        PINGROUP(VI_D3,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3130),
-        PINGROUP(VI_D4,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3134),
-        PINGROUP(VI_D5,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3138),
-        PINGROUP(VI_D6,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x313c),
-        PINGROUP(VI_D7,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3140),
-        PINGROUP(VI_D8,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3144),
-        PINGROUP(VI_D9,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3148),
-        PINGROUP(VI_D10,          VI,       INVALID,    RSVD1,      VI,         RSVD2,      RSVD,       INPUT,  0x314c),
-        PINGROUP(VI_D11,          VI,       INVALID,    RSVD1,      VI,         RSVD2,      RSVD,       INPUT,  0x3150),
-        PINGROUP(VI_PCLK,         VI,       RSVD1,      SDIO2,      VI,         RSVD2,      RSVD,       INPUT,  0x3154),
-        PINGROUP(VI_MCLK,         VI,       VI,         INVALID,    INVALID,    INVALID,    RSVD,       INPUT,  0x3158),
-        PINGROUP(VI_VSYNC,        VI,       INVALID,    RSVD1,      VI,         RSVD2,      RSVD,       INPUT,  0x315c),
-        PINGROUP(VI_HSYNC,        VI,       INVALID,    RSVD1,      VI,         RSVD2,      RSVD,       INPUT,  0x3160),
-        PINGROUP(UART2_RXD,       UART,     IRDA,       SPDIF,      UARTA,      SPI4,       RSVD,       INPUT,  0x3164),
-        PINGROUP(UART2_TXD,       UART,     IRDA,       SPDIF,      UARTA,      SPI4,       RSVD,       INPUT,  0x3168),
-        PINGROUP(UART2_RTS_N,     UART,     UARTA,      UARTB,      GMI,        SPI4,       RSVD,       INPUT,  0x316c),
-        PINGROUP(UART2_CTS_N,     UART,     UARTA,      UARTB,      GMI,        SPI4,       RSVD,       INPUT,  0x3170),
-        PINGROUP(UART3_TXD,       UART,     UARTC,      RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x3174),
-        PINGROUP(UART3_RXD,       UART,     UARTC,      RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x3178),
-        PINGROUP(UART3_CTS_N,     UART,     UARTC,      RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x317c),
-        PINGROUP(UART3_RTS_N,     UART,     UARTC,      PWM0,       GMI,        RSVD2,      RSVD,       INPUT,  0x3180),
-        PINGROUP(GPIO_PU0,        UART,     OWR,        UARTA,      GMI,        RSVD1,      RSVD,       INPUT,  0x3184),
-        PINGROUP(GPIO_PU1,        UART,     RSVD1,      UARTA,      GMI,        RSVD2,      RSVD,       INPUT,  0x3188),
-        PINGROUP(GPIO_PU2,        UART,     RSVD1,      UARTA,      GMI,        RSVD2,      RSVD,       INPUT,  0x318c),
-        PINGROUP(GPIO_PU3,        UART,     PWM0,       UARTA,      GMI,        RSVD1,      RSVD,       INPUT,  0x3190),
-        PINGROUP(GPIO_PU4,        UART,     PWM1,       UARTA,      GMI,        RSVD1,      RSVD,       INPUT,  0x3194),
-        PINGROUP(GPIO_PU5,        UART,     PWM2,       UARTA,      GMI,        RSVD1,      RSVD,       INPUT,  0x3198),
-        PINGROUP(GPIO_PU6,        UART,     PWM3,       UARTA,      GMI,        RSVD1,      RSVD,       INPUT,  0x319c),
-        PINGROUP(GEN1_I2C_SDA,    UART,     I2C,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x31a0),
-        PINGROUP(GEN1_I2C_SCL,    UART,     I2C,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x31a4),
-        PINGROUP(DAP4_FS,         UART,     I2S3,       RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x31a8),
-        PINGROUP(DAP4_DIN,        UART,     I2S3,       RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x31ac),
-        PINGROUP(DAP4_DOUT,       UART,     I2S3,       RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x31b0),
-        PINGROUP(DAP4_SCLK,       UART,     I2S3,       RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x31b4),
-        PINGROUP(CLK3_OUT,        UART,     EXTPERIPH3, RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x31b8),
-        PINGROUP(CLK3_REQ,        UART,     DEV3,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x31bc),
-        PINGROUP(GMI_WP_N,        GMI,      RSVD1,      NAND,       GMI,        GMI_ALT,    RSVD,       INPUT,  0x31c0),
-        PINGROUP(GMI_IORDY,       GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31c4),
-        PINGROUP(GMI_WAIT,        GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31c8),
-        PINGROUP(GMI_ADV_N,       GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31cc),
-        PINGROUP(GMI_CLK,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31d0),
-        PINGROUP(GMI_CS0_N,       GMI,      RSVD1,      NAND,       GMI,        INVALID,    RSVD,       INPUT,  0x31d4),
-        PINGROUP(GMI_CS1_N,       GMI,      RSVD1,      NAND,       GMI,        DTV,        RSVD,       INPUT,  0x31d8),
-        PINGROUP(GMI_CS2_N,       GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31dc),
-        PINGROUP(GMI_CS3_N,       GMI,      RSVD1,      NAND,       GMI,        GMI_ALT,    RSVD,       INPUT,  0x31e0),
-        PINGROUP(GMI_CS4_N,       GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31e4),
-        PINGROUP(GMI_CS6_N,       GMI,      NAND,       NAND_ALT,   GMI,        SATA,       RSVD,       INPUT,  0x31e8),
-        PINGROUP(GMI_CS7_N,       GMI,      NAND,       NAND_ALT,   GMI,        GMI_ALT,    RSVD,       INPUT,  0x31ec),
-        PINGROUP(GMI_AD0,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31f0),
-        PINGROUP(GMI_AD1,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31f4),
-        PINGROUP(GMI_AD2,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31f8),
-        PINGROUP(GMI_AD3,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31fc),
-        PINGROUP(GMI_AD4,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3200),
-        PINGROUP(GMI_AD5,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3204),
-        PINGROUP(GMI_AD6,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3208),
-        PINGROUP(GMI_AD7,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x320c),
-        PINGROUP(GMI_AD8,         GMI,      PWM0,       NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3210),
-        PINGROUP(GMI_AD9,         GMI,      PWM1,       NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3214),
-        PINGROUP(GMI_AD10,        GMI,      PWM2,       NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3218),
-        PINGROUP(GMI_AD11,        GMI,      PWM3,       NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x321c),
-        PINGROUP(GMI_AD12,        GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3220),
-        PINGROUP(GMI_AD13,        GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3224),
-        PINGROUP(GMI_AD14,        GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3228),
-        PINGROUP(GMI_AD15,        GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x322c),
-        PINGROUP(GMI_A16,         GMI,      UARTD,      SPI4,       GMI,        GMI_ALT,    RSVD,       INPUT,  0x3230),
-        PINGROUP(GMI_A17,         GMI,      UARTD,      SPI4,       GMI,        INVALID,    RSVD,       INPUT,  0x3234),
-        PINGROUP(GMI_A18,         GMI,      UARTD,      SPI4,       GMI,        INVALID,    RSVD,       INPUT,  0x3238),
-        PINGROUP(GMI_A19,         GMI,      UARTD,      SPI4,       GMI,        RSVD3,      RSVD,       INPUT,  0x323c),
-        PINGROUP(GMI_WR_N,        GMI,      RSVD1,      NAND,       GMI,        RSVD3,      RSVD,       INPUT,  0x3240),
-        PINGROUP(GMI_OE_N,        GMI,      RSVD1,      NAND,       GMI,        RSVD3,      RSVD,       INPUT,  0x3244),
-        PINGROUP(GMI_DQS,         GMI,      RSVD1,      NAND,       GMI,        RSVD3,      RSVD,       INPUT,  0x3248),
-        PINGROUP(GMI_RST_N,       GMI,      NAND,       NAND_ALT,   GMI,        RSVD3,      RSVD,       INPUT,  0x324c),
-        PINGROUP(GEN2_I2C_SCL,    GMI,      I2C2,       INVALID,    GMI,        RSVD3,      RSVD,       INPUT,  0x3250),
-        PINGROUP(GEN2_I2C_SDA,    GMI,      I2C2,       INVALID,    GMI,        RSVD3,      RSVD,       INPUT,  0x3254),
-        PINGROUP(SDMMC4_CLK,      SDMMC4,   INVALID,    NAND,       GMI,        SDIO4,      RSVD,       INPUT,  0x3258),
-        PINGROUP(SDMMC4_CMD,      SDMMC4,   I2C3,       NAND,       GMI,        SDIO4,      RSVD,       INPUT,  0x325c),
-        PINGROUP(SDMMC4_DAT0,     SDMMC4,   UARTE,      SPI3,       GMI,        SDIO4,      RSVD,       INPUT,  0x3260),
-        PINGROUP(SDMMC4_DAT1,     SDMMC4,   UARTE,      SPI3,       GMI,        SDIO4,      RSVD,       INPUT,  0x3264),
-        PINGROUP(SDMMC4_DAT2,     SDMMC4,   UARTE,      SPI3,       GMI,        SDIO4,      RSVD,       INPUT,  0x3268),
-        PINGROUP(SDMMC4_DAT3,     SDMMC4,   UARTE,      SPI3,       GMI,        SDIO4,      RSVD,       INPUT,  0x326c),
-        PINGROUP(SDMMC4_DAT4,     SDMMC4,   I2C3,       I2S4,       GMI,        SDIO4,      RSVD,       INPUT,  0x3270),
-        PINGROUP(SDMMC4_DAT5,     SDMMC4,   VGP3,       I2S4,       GMI,        SDIO4,      RSVD,       INPUT,  0x3274),
-        PINGROUP(SDMMC4_DAT6,     SDMMC4,   VGP4,       I2S4,       GMI,        SDIO4,      RSVD,       INPUT,  0x3278),
-        PINGROUP(SDMMC4_DAT7,     SDMMC4,   VGP5,       I2S4,       GMI,        SDIO4,      RSVD,       INPUT,  0x327c),
-        PINGROUP(SDMMC4_RST_N,    SDMMC4,   VGP6,       RSVD1,      RSVD2,      POPSDMMC4,  RSVD,       INPUT,  0x3280),
-        PINGROUP(CAM_MCLK,        CAM,      VI,         INVALID,    VI_ALT2,    POPSDMMC4,  RSVD,       INPUT,  0x3284),
-        PINGROUP(GPIO_PCC1,       CAM,      I2S4,       RSVD1,      RSVD2,      POPSDMMC4,  RSVD,       INPUT,  0x3288),
-        PINGROUP(GPIO_PBB0,       CAM,      I2S4,       RSVD1,      RSVD2,      POPSDMMC4,  RSVD,       INPUT,  0x328c),
-        PINGROUP(CAM_I2C_SCL,     CAM,      INVALID,    I2C3,       RSVD2,      POPSDMMC4,  RSVD,       INPUT,  0x3290),
-        PINGROUP(CAM_I2C_SDA,     CAM,      INVALID,    I2C3,       RSVD2,      POPSDMMC4,  RSVD,       INPUT,  0x3294),
-        PINGROUP(GPIO_PBB3,       CAM,      VGP3,       DISPLAYA,   DISPLAYB,   POPSDMMC4,  RSVD,       INPUT,  0x3298),
-        PINGROUP(GPIO_PBB4,       CAM,      VGP4,       DISPLAYA,   DISPLAYB,   POPSDMMC4,  RSVD,       INPUT,  0x329c),
-        PINGROUP(GPIO_PBB5,       CAM,      VGP5,       DISPLAYA,   DISPLAYB,   POPSDMMC4,  RSVD,       INPUT,  0x32a0),
-        PINGROUP(GPIO_PBB6,       CAM,      VGP6,       DISPLAYA,   DISPLAYB,   POPSDMMC4,  RSVD,       INPUT,  0x32a4),
-        PINGROUP(GPIO_PBB7,       CAM,      I2S4,       RSVD1,      RSVD2,      POPSDMMC4,  RSVD,       INPUT,  0x32a8),
-        PINGROUP(GPIO_PCC2,       CAM,      I2S4,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x32ac),
-        PINGROUP(JTAG_RTCK,       SYS,      RTCK,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x32b0),
-        PINGROUP(PWR_I2C_SCL,     SYS,      I2CPWR,     RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x32b4),
-        PINGROUP(PWR_I2C_SDA,     SYS,      I2CPWR,     RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x32b8),
-        PINGROUP(KB_ROW0,         SYS,      KBC,        INVALID,    RSVD2,      RSVD3,      RSVD,       INPUT,  0x32bc),
-        PINGROUP(KB_ROW1,         SYS,      KBC,        INVALID,    RSVD2,      RSVD3,      RSVD,       INPUT,  0x32c0),
-        PINGROUP(KB_ROW2,         SYS,      KBC,        INVALID,    RSVD2,      RSVD3,      RSVD,       INPUT,  0x32c4),
-        PINGROUP(KB_ROW3,         SYS,      KBC,        INVALID,    RSVD2,      INVALID,    RSVD,       INPUT,  0x32c8),
-        PINGROUP(KB_ROW4,         SYS,      KBC,        INVALID,    TRACE,      RSVD3,      RSVD,       INPUT,  0x32cc),
-        PINGROUP(KB_ROW5,         SYS,      KBC,        INVALID,    TRACE,      OWR,        RSVD,       INPUT,  0x32d0),
-        PINGROUP(KB_ROW6,         SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32d4),
-        PINGROUP(KB_ROW7,         SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32d8),
-        PINGROUP(KB_ROW8,         SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32dc),
-        PINGROUP(KB_ROW9,         SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32e0),
-        PINGROUP(KB_ROW10,        SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32e4),
-        PINGROUP(KB_ROW11,        SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32e8),
-        PINGROUP(KB_ROW12,        SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32ec),
-        PINGROUP(KB_ROW13,        SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32f0),
-        PINGROUP(KB_ROW14,        SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32f4),
-        PINGROUP(KB_ROW15,        SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32f8),
-        PINGROUP(KB_COL0,         SYS,      KBC,        INVALID,    TRACE,      INVALID,    RSVD,       INPUT,  0x32fc),
-        PINGROUP(KB_COL1,         SYS,      KBC,        INVALID,    TRACE,      INVALID,    RSVD,       INPUT,  0x3300),
-        PINGROUP(KB_COL2,         SYS,      KBC,        INVALID,    TRACE,      RSVD,       RSVD,       INPUT,  0x3304),
-        PINGROUP(KB_COL3,         SYS,      KBC,        INVALID,    TRACE,      RSVD,       RSVD,       INPUT,  0x3308),
-        PINGROUP(KB_COL4,         SYS,      KBC,        INVALID,    TRACE,      RSVD,       RSVD,       INPUT,  0x330c),
-        PINGROUP(KB_COL5,         SYS,      KBC,        INVALID,    TRACE,      RSVD,       RSVD,       INPUT,  0x3310),
-        PINGROUP(KB_COL6,         SYS,      KBC,        INVALID,    TRACE,      INVALID,    RSVD,       INPUT,  0x3314),
-        PINGROUP(KB_COL7,         SYS,      KBC,        INVALID,    TRACE,      INVALID,    RSVD,       INPUT,  0x3318),
-        PINGROUP(CLK_32K_OUT,     SYS,      BLINK,      RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x331c),
-        PINGROUP(SYS_CLK_REQ,     SYS,      SYSCLK,     RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3320),
-        PINGROUP(CORE_PWR_REQ,    SYS,      RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3324),
-        PINGROUP(CPU_PWR_REQ,     SYS,      RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3328),
-        PINGROUP(PWR_INT_N,       SYS,      RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x332c),
-        PINGROUP(CLK_32K_IN,      SYS,      RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3330),
-        PINGROUP(OWR,             SYS,      OWR,        RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3334),
-        PINGROUP(DAP1_FS,         AUDIO,    I2S0,       HDA,        GMI,        SDIO2,      RSVD,       INPUT,  0x3338),
-        PINGROUP(DAP1_DIN,        AUDIO,    I2S0,       HDA,        GMI,        SDIO2,      RSVD,       INPUT,  0x333c),
-        PINGROUP(DAP1_DOUT,       AUDIO,    I2S0,       HDA,        GMI,        SDIO2,      RSVD,       INPUT,  0x3340),
-        PINGROUP(DAP1_SCLK,       AUDIO,    I2S0,       HDA,        GMI,        SDIO2,      RSVD,       INPUT,  0x3344),
-        PINGROUP(CLK1_REQ,        AUDIO,    DAP,        HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x3348),
-        PINGROUP(CLK1_OUT,        AUDIO,    EXTPERIPH1, RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x334c),
-        PINGROUP(SPDIF_IN,        AUDIO,    SPDIF,      HDA,        INVALID,    DAPSDMMC2,  RSVD,       INPUT,  0x3350),
-        PINGROUP(SPDIF_OUT,       AUDIO,    SPDIF,      RSVD1,      INVALID,    DAPSDMMC2,  RSVD,       INPUT,  0x3354),
-        PINGROUP(DAP2_FS,         AUDIO,    I2S1,       HDA,        RSVD2,      GMI,        RSVD,       INPUT,  0x3358),
-        PINGROUP(DAP2_DIN,        AUDIO,    I2S1,       HDA,        RSVD2,      GMI,        RSVD,       INPUT,  0x335c),
-        PINGROUP(DAP2_DOUT,       AUDIO,    I2S1,       HDA,        RSVD2,      GMI,        RSVD,       INPUT,  0x3360),
-        PINGROUP(DAP2_SCLK,       AUDIO,    I2S1,       HDA,        RSVD2,      GMI,        RSVD,       INPUT,  0x3364),
-        PINGROUP(SPI2_MOSI,       AUDIO,    SPI6,       SPI2,       INVALID,    GMI,        RSVD,       INPUT,  0x3368),
-        PINGROUP(SPI2_MISO,       AUDIO,    SPI6,       SPI2,       INVALID,    GMI,        RSVD,       INPUT,  0x336c),
-        PINGROUP(SPI2_CS0_N,      AUDIO,    SPI6,       SPI2,       INVALID,    GMI,        RSVD,       INPUT,  0x3370),
-        PINGROUP(SPI2_SCK,        AUDIO,    SPI6,       SPI2,       INVALID,    GMI,        RSVD,       INPUT,  0x3374),
-        PINGROUP(SPI1_MOSI,       AUDIO,    SPI2,       SPI1,       INVALID,    GMI,        RSVD,       INPUT,  0x3378),
-        PINGROUP(SPI1_SCK,        AUDIO,    SPI2,       SPI1,       INVALID,    GMI,        RSVD,       INPUT,  0x337c),
-        PINGROUP(SPI1_CS0_N,      AUDIO,    SPI2,       SPI1,       INVALID,    GMI,        RSVD,       INPUT,  0x3380),
-        PINGROUP(SPI1_MISO,       AUDIO,    INVALID,    SPI1,       INVALID,    RSVD3,      RSVD,       INPUT,  0x3384),
-        PINGROUP(SPI2_CS1_N,      AUDIO,    INVALID,    SPI2,       INVALID,    INVALID,    RSVD,       INPUT,  0x3388),
-        PINGROUP(SPI2_CS2_N,      AUDIO,    INVALID,    SPI2,       INVALID,    INVALID,    RSVD,       INPUT,  0x338c),
-        PINGROUP(SDMMC3_CLK,      SDMMC3,   UARTA,      PWM2,       SDIO3,      INVALID,    RSVD,       INPUT,  0x3390),
-        PINGROUP(SDMMC3_CMD,      SDMMC3,   UARTA,      PWM3,       SDIO3,      INVALID,    RSVD,       INPUT,  0x3394),
-        PINGROUP(SDMMC3_DAT0,     SDMMC3,   RSVD,       RSVD1,      SDIO3,      INVALID,    RSVD,       INPUT,  0x3398),
-        PINGROUP(SDMMC3_DAT1,     SDMMC3,   RSVD,       RSVD1,      SDIO3,      INVALID,    RSVD,       INPUT,  0x339c),
-        PINGROUP(SDMMC3_DAT2,     SDMMC3,   RSVD,       PWM1,       SDIO3,      INVALID,    RSVD,       INPUT,  0x33a0),
-        PINGROUP(SDMMC3_DAT3,     SDMMC3,   RSVD,       PWM0,       SDIO3,      INVALID,    RSVD,       INPUT,  0x33a4),
-        PINGROUP(SDMMC3_DAT4,     SDMMC3,   PWM1,       INVALID,    SDIO3,      INVALID,    RSVD,       INPUT,  0x33a8),
-        PINGROUP(SDMMC3_DAT5,     SDMMC3,   PWM0,       INVALID,    SDIO3,      INVALID,    RSVD,       INPUT,  0x33ac),
-        PINGROUP(SDMMC3_DAT6,     SDMMC3,   SPDIF,      INVALID,    SDIO3,      INVALID,    RSVD,       INPUT,  0x33b0),
-        PINGROUP(SDMMC3_DAT7,     SDMMC3,   SPDIF,      INVALID,    SDIO3,      INVALID,    RSVD,       INPUT,  0x33b4),
-        PINGROUP(PEX_L0_PRSNT_N,  PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33b8),
-        PINGROUP(PEX_L0_RST_N,    PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33bc),
-        PINGROUP(PEX_L0_CLKREQ_N, PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33c0),
-        PINGROUP(PEX_WAKE_N,      PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33c4),
-        PINGROUP(PEX_L1_PRSNT_N,  PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33c8),
-        PINGROUP(PEX_L1_RST_N,    PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33cc),
-        PINGROUP(PEX_L1_CLKREQ_N, PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33d0),
-        PINGROUP(PEX_L2_PRSNT_N,  PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33d4),
-        PINGROUP(PEX_L2_RST_N,    PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33d8),
-        PINGROUP(PEX_L2_CLKREQ_N, PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33dc),
-        PINGROUP(HDMI_CEC,        SYS,      CEC,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x33e0),
-};
-
-void __devinit tegra30_pinmux_init(const struct tegra_pingroup_desc **pg,
-                int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
-                int *pgdrive_max)
-{
-        *pg = tegra_soc_pingroups;
-        *pg_max = TEGRA_MAX_PINGROUP;
-        *pgdrive = tegra_soc_drive_pingroups;
-        *pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
-}
-
diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c
deleted file mode 100644
index ac35d2b76850..000000000000
--- a/arch/arm/mach-tegra/pinmux.c
+++ /dev/null
@@ -1,987 +0,0 @@
-/*
- * linux/arch/arm/mach-tegra/pinmux.c
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/spinlock.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <linux/of_device.h>
-
-#include <mach/iomap.h>
-#include <mach/pinmux.h>
-
-#define HSM_EN(reg)     (((reg) >> 2) & 0x1)
-#define SCHMT_EN(reg)   (((reg) >> 3) & 0x1)
-#define LPMD(reg)       (((reg) >> 4) & 0x3)
-#define DRVDN(reg)      (((reg) >> 12) & 0x1f)
-#define DRVUP(reg)      (((reg) >> 20) & 0x1f)
-#define SLWR(reg)       (((reg) >> 28) & 0x3)
-#define SLWF(reg)       (((reg) >> 30) & 0x3)
-
-static const struct tegra_pingroup_desc *pingroups;
-static const struct tegra_drive_pingroup_desc *drive_pingroups;
-static int pingroup_max;
-static int drive_max;
-
-static char *tegra_mux_names[TEGRA_MAX_MUX] = {
-        [TEGRA_MUX_AHB_CLK] = "AHB_CLK",
-        [TEGRA_MUX_APB_CLK] = "APB_CLK",
-        [TEGRA_MUX_AUDIO_SYNC] = "AUDIO_SYNC",
-        [TEGRA_MUX_CRT] = "CRT",
-        [TEGRA_MUX_DAP1] = "DAP1",
-        [TEGRA_MUX_DAP2] = "DAP2",
-        [TEGRA_MUX_DAP3] = "DAP3",
-        [TEGRA_MUX_DAP4] = "DAP4",
-        [TEGRA_MUX_DAP5] = "DAP5",
-        [TEGRA_MUX_DISPLAYA] = "DISPLAYA",
-        [TEGRA_MUX_DISPLAYB] = "DISPLAYB",
-        [TEGRA_MUX_EMC_TEST0_DLL] = "EMC_TEST0_DLL",
-        [TEGRA_MUX_EMC_TEST1_DLL] = "EMC_TEST1_DLL",
-        [TEGRA_MUX_GMI] = "GMI",
-        [TEGRA_MUX_GMI_INT] = "GMI_INT",
-        [TEGRA_MUX_HDMI] = "HDMI",
-        [TEGRA_MUX_I2C] = "I2C",
-        [TEGRA_MUX_I2C2] = "I2C2",
-        [TEGRA_MUX_I2C3] = "I2C3",
-        [TEGRA_MUX_IDE] = "IDE",
-        [TEGRA_MUX_IRDA] = "IRDA",
-        [TEGRA_MUX_KBC] = "KBC",
-        [TEGRA_MUX_MIO] = "MIO",
-        [TEGRA_MUX_MIPI_HS] = "MIPI_HS",
-        [TEGRA_MUX_NAND] = "NAND",
-        [TEGRA_MUX_OSC] = "OSC",
-        [TEGRA_MUX_OWR] = "OWR",
-        [TEGRA_MUX_PCIE] = "PCIE",
-        [TEGRA_MUX_PLLA_OUT] = "PLLA_OUT",
-        [TEGRA_MUX_PLLC_OUT1] = "PLLC_OUT1",
-        [TEGRA_MUX_PLLM_OUT1] = "PLLM_OUT1",
-        [TEGRA_MUX_PLLP_OUT2] = "PLLP_OUT2",
-        [TEGRA_MUX_PLLP_OUT3] = "PLLP_OUT3",
-        [TEGRA_MUX_PLLP_OUT4] = "PLLP_OUT4",
-        [TEGRA_MUX_PWM] = "PWM",
-        [TEGRA_MUX_PWR_INTR] = "PWR_INTR",
-        [TEGRA_MUX_PWR_ON] = "PWR_ON",
-        [TEGRA_MUX_RTCK] = "RTCK",
-        [TEGRA_MUX_SDIO1] = "SDIO1",
-        [TEGRA_MUX_SDIO2] = "SDIO2",
-        [TEGRA_MUX_SDIO3] = "SDIO3",
-        [TEGRA_MUX_SDIO4] = "SDIO4",
-        [TEGRA_MUX_SFLASH] = "SFLASH",
-        [TEGRA_MUX_SPDIF] = "SPDIF",
-        [TEGRA_MUX_SPI1] = "SPI1",
-        [TEGRA_MUX_SPI2] = "SPI2",
-        [TEGRA_MUX_SPI2_ALT] = "SPI2_ALT",
-        [TEGRA_MUX_SPI3] = "SPI3",
-        [TEGRA_MUX_SPI4] = "SPI4",
-        [TEGRA_MUX_TRACE] = "TRACE",
-        [TEGRA_MUX_TWC] = "TWC",
-        [TEGRA_MUX_UARTA] = "UARTA",
-        [TEGRA_MUX_UARTB] = "UARTB",
-        [TEGRA_MUX_UARTC] = "UARTC",
-        [TEGRA_MUX_UARTD] = "UARTD",
-        [TEGRA_MUX_UARTE] = "UARTE",
-        [TEGRA_MUX_ULPI] = "ULPI",
-        [TEGRA_MUX_VI] = "VI",
-        [TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK",
-        [TEGRA_MUX_XIO] = "XIO",
-        [TEGRA_MUX_BLINK] = "BLINK",
-        [TEGRA_MUX_CEC] = "CEC",
-        [TEGRA_MUX_CLK12] = "CLK12",
-        [TEGRA_MUX_DAP] = "DAP",
-        [TEGRA_MUX_DAPSDMMC2] = "DAPSDMMC2",
-        [TEGRA_MUX_DDR] = "DDR",
-        [TEGRA_MUX_DEV3] = "DEV3",
-        [TEGRA_MUX_DTV] = "DTV",
-        [TEGRA_MUX_VI_ALT1] = "VI_ALT1",
-        [TEGRA_MUX_VI_ALT2] = "VI_ALT2",
-        [TEGRA_MUX_VI_ALT3] = "VI_ALT3",
-        [TEGRA_MUX_EMC_DLL] = "EMC_DLL",
-        [TEGRA_MUX_EXTPERIPH1] = "EXTPERIPH1",
-        [TEGRA_MUX_EXTPERIPH2] = "EXTPERIPH2",
-        [TEGRA_MUX_EXTPERIPH3] = "EXTPERIPH3",
-        [TEGRA_MUX_GMI_ALT] = "GMI_ALT",
-        [TEGRA_MUX_HDA] = "HDA",
-        [TEGRA_MUX_HSI] = "HSI",
-        [TEGRA_MUX_I2C4] = "I2C4",
-        [TEGRA_MUX_I2C5] = "I2C5",
-        [TEGRA_MUX_I2CPWR] = "I2CPWR",
-        [TEGRA_MUX_I2S0] = "I2S0",
-        [TEGRA_MUX_I2S1] = "I2S1",
-        [TEGRA_MUX_I2S2] = "I2S2",
-        [TEGRA_MUX_I2S3] = "I2S3",
-        [TEGRA_MUX_I2S4] = "I2S4",
-        [TEGRA_MUX_NAND_ALT] = "NAND_ALT",
-        [TEGRA_MUX_POPSDIO4] = "POPSDIO4",
-        [TEGRA_MUX_POPSDMMC4] = "POPSDMMC4",
-        [TEGRA_MUX_PWM0] = "PWM0",
-        [TEGRA_MUX_PWM1] = "PWM2",
-        [TEGRA_MUX_PWM2] = "PWM2",
-        [TEGRA_MUX_PWM3] = "PWM3",
-        [TEGRA_MUX_SATA] = "SATA",
-        [TEGRA_MUX_SPI5] = "SPI5",
-        [TEGRA_MUX_SPI6] = "SPI6",
-        [TEGRA_MUX_SYSCLK] = "SYSCLK",
-        [TEGRA_MUX_VGP1] = "VGP1",
-        [TEGRA_MUX_VGP2] = "VGP2",
-        [TEGRA_MUX_VGP3] = "VGP3",
-        [TEGRA_MUX_VGP4] = "VGP4",
-        [TEGRA_MUX_VGP5] = "VGP5",
-        [TEGRA_MUX_VGP6] = "VGP6",
-        [TEGRA_MUX_SAFE] = "<safe>",
-};
-
-static const char *tegra_drive_names[TEGRA_MAX_DRIVE] = {
-        [TEGRA_DRIVE_DIV_8] = "DIV_8",
-        [TEGRA_DRIVE_DIV_4] = "DIV_4",
-        [TEGRA_DRIVE_DIV_2] = "DIV_2",
-        [TEGRA_DRIVE_DIV_1] = "DIV_1",
-};
-
-static const char *tegra_slew_names[TEGRA_MAX_SLEW] = {
-        [TEGRA_SLEW_FASTEST] = "FASTEST",
-        [TEGRA_SLEW_FAST] = "FAST",
-        [TEGRA_SLEW_SLOW] = "SLOW",
-        [TEGRA_SLEW_SLOWEST] = "SLOWEST",
-};
-
-static DEFINE_SPINLOCK(mux_lock);
-
-static const char *pingroup_name(int pg)
-{
-        if (pg < 0 || pg >=  pingroup_max)
-                return "<UNKNOWN>";
-
-        return pingroups[pg].name;
-}
-
-static const char *func_name(enum tegra_mux_func func)
-{
-        if (func == TEGRA_MUX_RSVD1)
-                return "RSVD1";
-
-        if (func == TEGRA_MUX_RSVD2)
-                return "RSVD2";
-
-        if (func == TEGRA_MUX_RSVD3)
-                return "RSVD3";
-
-        if (func == TEGRA_MUX_RSVD4)
-                return "RSVD4";
-
-        if (func == TEGRA_MUX_NONE)
-                return "NONE";
-
-        if (func < 0 || func >=  TEGRA_MAX_MUX)
-                return "<UNKNOWN>";
-
-        return tegra_mux_names[func];
-}
-
-
-static const char *tri_name(unsigned long val)
-{
-        return val ? "TRISTATE" : "NORMAL";
-}
-
-static const char *pupd_name(unsigned long val)
-{
-        switch (val) {
-        case 0:
-                return "NORMAL";
-
-        case 1:
-                return "PULL_DOWN";
-
-        case 2:
-                return "PULL_UP";
-
-        default:
-                return "RSVD";
-        }
-}
-
-static int nbanks;
-static void __iomem **regs;
-
-static inline u32 pg_readl(u32 bank, u32 reg)
-{
-        return readl(regs[bank] + reg);
-}
-
-static inline void pg_writel(u32 val, u32 bank, u32 reg)
-{
-        writel(val, regs[bank] + reg);
-}
-
-static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
-{
-        int mux = -1;
-        int i;
-        unsigned long reg;
-        unsigned long flags;
-        int pg = config->pingroup;
-        enum tegra_mux_func func = config->func;
-
-        if (pg < 0 || pg >=  pingroup_max)
-                return -ERANGE;
-
-        if (pingroups[pg].mux_reg < 0)
-                return -EINVAL;
-
-        if (func < 0)
-                return -ERANGE;
-
-        if (func == TEGRA_MUX_SAFE)
-                func = pingroups[pg].func_safe;
-
-        if (func & TEGRA_MUX_RSVD) {
-                mux = func & 0x3;
-        } else {
-                for (i = 0; i < 4; i++) {
-                        if (pingroups[pg].funcs[i] == func) {
-                                mux = i;
-                                break;
-                        }
-                }
-        }
-
-        if (mux < 0)
-                return -EINVAL;
-
-        spin_lock_irqsave(&mux_lock, flags);
-
-        reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
-        reg &= ~(0x3 << pingroups[pg].mux_bit);
-        reg |= mux << pingroups[pg].mux_bit;
-        pg_writel(reg, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
-
-        spin_unlock_irqrestore(&mux_lock, flags);
-
-        return 0;
-}
-
-int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate)
-{
-        unsigned long reg;
-        unsigned long flags;
-
-        if (pg < 0 || pg >=  pingroup_max)
-                return -ERANGE;
-
-        if (pingroups[pg].tri_reg < 0)
-                return -EINVAL;
-
-        spin_lock_irqsave(&mux_lock, flags);
-
-        reg = pg_readl(pingroups[pg].tri_bank, pingroups[pg].tri_reg);
-        reg &= ~(0x1 << pingroups[pg].tri_bit);
-        if (tristate)
-                reg |= 1 << pingroups[pg].tri_bit;
-        pg_writel(reg, pingroups[pg].tri_bank, pingroups[pg].tri_reg);
-
-        spin_unlock_irqrestore(&mux_lock, flags);
-
-        return 0;
-}
-
-int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd)
-{
-        unsigned long reg;
-        unsigned long flags;
-
-        if (pg < 0 || pg >=  pingroup_max)
-                return -ERANGE;
-
-        if (pingroups[pg].pupd_reg < 0)
-                return -EINVAL;
-
-        if (pupd != TEGRA_PUPD_NORMAL &&
-            pupd != TEGRA_PUPD_PULL_DOWN &&
-            pupd != TEGRA_PUPD_PULL_UP)
-                return -EINVAL;
-
-
-        spin_lock_irqsave(&mux_lock, flags);
-
-        reg = pg_readl(pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
-        reg &= ~(0x3 << pingroups[pg].pupd_bit);
-        reg |= pupd << pingroups[pg].pupd_bit;
-        pg_writel(reg, pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
-
-        spin_unlock_irqrestore(&mux_lock, flags);
-
-        return 0;
-}
-
-static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config)
-{
-        int pingroup = config->pingroup;
-        enum tegra_mux_func func     = config->func;
-        enum tegra_pullupdown pupd   = config->pupd;
-        enum tegra_tristate tristate = config->tristate;
-        int err;
-
-        if (pingroups[pingroup].mux_reg >= 0) {
-                err = tegra_pinmux_set_func(config);
-                if (err < 0)
-                        pr_err("pinmux: can't set pingroup %s func to %s: %d\n",
-                               pingroup_name(pingroup), func_name(func), err);
-        }
-
-        if (pingroups[pingroup].pupd_reg >= 0) {
-                err = tegra_pinmux_set_pullupdown(pingroup, pupd);
-                if (err < 0)
-                        pr_err("pinmux: can't set pingroup %s pullupdown to %s: %d\n",
-                               pingroup_name(pingroup), pupd_name(pupd), err);
-        }
-
-        if (pingroups[pingroup].tri_reg >= 0) {
-                err = tegra_pinmux_set_tristate(pingroup, tristate);
-                if (err < 0)
-                        pr_err("pinmux: can't set pingroup %s tristate to %s: %d\n",
-                               pingroup_name(pingroup), tri_name(func), err);
-        }
-}
-
-void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int len)
-{
-        int i;
-
-        for (i = 0; i < len; i++)
-                tegra_pinmux_config_pingroup(&config[i]);
-}
-
-static const char *drive_pinmux_name(int pg)
-{
-        if (pg < 0 || pg >=  drive_max)
-                return "<UNKNOWN>";
-
-        return drive_pingroups[pg].name;
-}
-
-static const char *enable_name(unsigned long val)
-{
-        return val ? "ENABLE" : "DISABLE";
-}
-
-static const char *drive_name(unsigned long val)
-{
-        if (val >= TEGRA_MAX_DRIVE)
-                return "<UNKNOWN>";
-
-        return tegra_drive_names[val];
-}
-
-static const char *slew_name(unsigned long val)
-{
-        if (val >= TEGRA_MAX_SLEW)
-                return "<UNKNOWN>";
-
-        return tegra_slew_names[val];
-}
-
-static int tegra_drive_pinmux_set_hsm(int pg, enum tegra_hsm hsm)
-{
-        unsigned long flags;
-        u32 reg;
-        if (pg < 0 || pg >=  drive_max)
-                return -ERANGE;
-
-        if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE)
-                return -EINVAL;
-
-        spin_lock_irqsave(&mux_lock, flags);
-
-        reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-        if (hsm == TEGRA_HSM_ENABLE)
-                reg |= (1 << 2);
-        else
-                reg &= ~(1 << 2);
-        pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-
-        spin_unlock_irqrestore(&mux_lock, flags);
-
-        return 0;
-}
-
-static int tegra_drive_pinmux_set_schmitt(int pg, enum tegra_schmitt schmitt)
-{
-        unsigned long flags;
-        u32 reg;
-        if (pg < 0 || pg >=  drive_max)
-                return -ERANGE;
-
-        if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE)
-                return -EINVAL;
-
-        spin_lock_irqsave(&mux_lock, flags);
-
-        reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-        if (schmitt == TEGRA_SCHMITT_ENABLE)
-                reg |= (1 << 3);
-        else
-                reg &= ~(1 << 3);
-        pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-
-        spin_unlock_irqrestore(&mux_lock, flags);
-
-        return 0;
-}
-
-static int tegra_drive_pinmux_set_drive(int pg, enum tegra_drive drive)
-{
-        unsigned long flags;
-        u32 reg;
-        if (pg < 0 || pg >=  drive_max)
-                return -ERANGE;
-
-        if (drive < 0 || drive >= TEGRA_MAX_DRIVE)
-                return -EINVAL;
-
-        spin_lock_irqsave(&mux_lock, flags);
-
-        reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-        reg &= ~(0x3 << 4);
-        reg |= drive << 4;
-        pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-
-        spin_unlock_irqrestore(&mux_lock, flags);
-
-        return 0;
-}
-
-static int tegra_drive_pinmux_set_pull_down(int pg,
-        enum tegra_pull_strength pull_down)
-{
-        unsigned long flags;
-        u32 reg;
-        if (pg < 0 || pg >=  drive_max)
-                return -ERANGE;
-
-        if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL)
-                return -EINVAL;
-
-        spin_lock_irqsave(&mux_lock, flags);
-
-        reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-        reg &= ~(0x1f << 12);
-        reg |= pull_down << 12;
-        pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-
-        spin_unlock_irqrestore(&mux_lock, flags);
-
-        return 0;
-}
-
-static int tegra_drive_pinmux_set_pull_up(int pg,
-        enum tegra_pull_strength pull_up)
-{
-        unsigned long flags;
-        u32 reg;
-        if (pg < 0 || pg >=  drive_max)
-                return -ERANGE;
-
-        if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL)
-                return -EINVAL;
-
-        spin_lock_irqsave(&mux_lock, flags);
-
-        reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-        reg &= ~(0x1f << 12);
-        reg |= pull_up << 12;
-        pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-
-        spin_unlock_irqrestore(&mux_lock, flags);
-
-        return 0;
-}
-
-static int tegra_drive_pinmux_set_slew_rising(int pg,
-        enum tegra_slew slew_rising)
-{
-        unsigned long flags;
-        u32 reg;
-        if (pg < 0 || pg >=  drive_max)
-                return -ERANGE;
-
-        if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW)
-                return -EINVAL;
-
-        spin_lock_irqsave(&mux_lock, flags);
-
-        reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-        reg &= ~(0x3 << 28);
-        reg |= slew_rising << 28;
-        pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-
-        spin_unlock_irqrestore(&mux_lock, flags);
-
-        return 0;
-}
-
-static int tegra_drive_pinmux_set_slew_falling(int pg,
-        enum tegra_slew slew_falling)
-{
-        unsigned long flags;
-        u32 reg;
-        if (pg < 0 || pg >=  drive_max)
-                return -ERANGE;
-
-        if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW)
-                return -EINVAL;
-
-        spin_lock_irqsave(&mux_lock, flags);
-
-        reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-        reg &= ~(0x3 << 30);
-        reg |= slew_falling << 30;
-        pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-
-        spin_unlock_irqrestore(&mux_lock, flags);
-
-        return 0;
-}
-
-static void tegra_drive_pinmux_config_pingroup(int pingroup,
-                                          enum tegra_hsm hsm,
-                                          enum tegra_schmitt schmitt,
-                                          enum tegra_drive drive,
-                                          enum tegra_pull_strength pull_down,
-                                          enum tegra_pull_strength pull_up,
-                                          enum tegra_slew slew_rising,
-                                          enum tegra_slew slew_falling)
-{
-        int err;
-
-        err = tegra_drive_pinmux_set_hsm(pingroup, hsm);
-        if (err < 0)
-                pr_err("pinmux: can't set pingroup %s hsm to %s: %d\n",
-                        drive_pinmux_name(pingroup),
-                        enable_name(hsm), err);
-
-        err = tegra_drive_pinmux_set_schmitt(pingroup, schmitt);
-        if (err < 0)
-                pr_err("pinmux: can't set pingroup %s schmitt to %s: %d\n",
-                        drive_pinmux_name(pingroup),
-                        enable_name(schmitt), err);
-
-        err = tegra_drive_pinmux_set_drive(pingroup, drive);
-        if (err < 0)
-                pr_err("pinmux: can't set pingroup %s drive to %s: %d\n",
-                        drive_pinmux_name(pingroup),
-                        drive_name(drive), err);
-
-        err = tegra_drive_pinmux_set_pull_down(pingroup, pull_down);
-        if (err < 0)
-                pr_err("pinmux: can't set pingroup %s pull down to %d: %d\n",
-                        drive_pinmux_name(pingroup),
-                        pull_down, err);
-
-        err = tegra_drive_pinmux_set_pull_up(pingroup, pull_up);
-        if (err < 0)
-                pr_err("pinmux: can't set pingroup %s pull up to %d: %d\n",
-                        drive_pinmux_name(pingroup),
-                        pull_up, err);
-
-        err = tegra_drive_pinmux_set_slew_rising(pingroup, slew_rising);
-        if (err < 0)
-                pr_err("pinmux: can't set pingroup %s rising slew to %s: %d\n",
-                        drive_pinmux_name(pingroup),
-                        slew_name(slew_rising), err);
-
-        err = tegra_drive_pinmux_set_slew_falling(pingroup, slew_falling);
-        if (err < 0)
-                pr_err("pinmux: can't set pingroup %s falling slew to %s: %d\n",
-                        drive_pinmux_name(pingroup),
-                        slew_name(slew_falling), err);
-}
-
-void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
-        int len)
-{
-        int i;
-
-        for (i = 0; i < len; i++)
-                tegra_drive_pinmux_config_pingroup(config[i].pingroup,
-                                                     config[i].hsm,
-                                                     config[i].schmitt,
-                                                     config[i].drive,
-                                                     config[i].pull_down,
-                                                     config[i].pull_up,
-                                                     config[i].slew_rising,
-                                                     config[i].slew_falling);
-}
-
-void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
-        int len)
-{
-        int i;
-        struct tegra_pingroup_config c;
-
-        for (i = 0; i < len; i++) {
-                int err;
-                c = config[i];
-                if (c.pingroup < 0 || c.pingroup >= pingroup_max) {
-                        WARN_ON(1);
-                        continue;
-                }
-                c.func = pingroups[c.pingroup].func_safe;
-                err = tegra_pinmux_set_func(&c);
-                if (err < 0)
-                        pr_err("%s: tegra_pinmux_set_func returned %d setting "
-                               "%s to %s\n", __func__, err,
-                               pingroup_name(c.pingroup), func_name(c.func));
-        }
-}
-
-void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
-        int len)
-{
-        int i;
-
-        for (i = 0; i < len; i++) {
-                int err;
-                if (config[i].pingroup < 0 ||
-                    config[i].pingroup >= pingroup_max) {
-                        WARN_ON(1);
-                        continue;
-                }
-                err = tegra_pinmux_set_func(&config[i]);
-                if (err < 0)
-                        pr_err("%s: tegra_pinmux_set_func returned %d setting "
-                               "%s to %s\n", __func__, err,
-                               pingroup_name(config[i].pingroup),
-                               func_name(config[i].func));
-        }
-}
-
-void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
-        int len, enum tegra_tristate tristate)
-{
-        int i;
-        int err;
-        int pingroup;
-
-        for (i = 0; i < len; i++) {
-                pingroup = config[i].pingroup;
-                if (pingroups[pingroup].tri_reg >= 0) {
-                        err = tegra_pinmux_set_tristate(pingroup, tristate);
-                        if (err < 0)
-                                pr_err("pinmux: can't set pingroup %s tristate"
-                                        " to %s: %d\n", pingroup_name(pingroup),
-                                        tri_name(tristate), err);
-                }
-        }
-}
-
-void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
-        int len, enum tegra_pullupdown pupd)
-{
-        int i;
-        int err;
-        int pingroup;
-
-        for (i = 0; i < len; i++) {
-                pingroup = config[i].pingroup;
-                if (pingroups[pingroup].pupd_reg >= 0) {
-                        err = tegra_pinmux_set_pullupdown(pingroup, pupd);
-                        if (err < 0)
-                                pr_err("pinmux: can't set pingroup %s pullupdown"
-                                        " to %s: %d\n", pingroup_name(pingroup),
-                                        pupd_name(pupd), err);
-                }
-        }
-}
-
-static struct of_device_id tegra_pinmux_of_match[] __devinitdata = {
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-        { .compatible = "nvidia,tegra20-pinmux", tegra20_pinmux_init },
-#endif
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
-        { .compatible = "nvidia,tegra30-pinmux", tegra30_pinmux_init },
-#endif
-        { },
-};
-
-static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
-{
-        struct resource *res;
-        int i;
-        int config_bad = 0;
-        const struct of_device_id *match;
-
-        match = of_match_device(tegra_pinmux_of_match, &pdev->dev);
-
-        if (match)
-                ((pinmux_init)(match->data))(&pingroups, &pingroup_max,
-                        &drive_pingroups, &drive_max);
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-        else
-                /* no device tree available, so we must be on tegra20 */
-                tegra20_pinmux_init(&pingroups, &pingroup_max,
-                                        &drive_pingroups, &drive_max);
-#else
-        pr_warn("non Tegra20 platform requires pinmux devicetree node\n");
-#endif
-
-        for (i = 0; ; i++) {
-                res = platform_get_resource(pdev, IORESOURCE_MEM, i);
-                if (!res)
-                        break;
-        }
-        nbanks = i;
-
-        for (i = 0; i < pingroup_max; i++) {
-                if (pingroups[i].tri_bank >= nbanks) {
-                        dev_err(&pdev->dev, "pingroup %d: bad tri_bank\n", i);
-                        config_bad = 1;
-                }
-
-                if (pingroups[i].mux_bank >= nbanks) {
-                        dev_err(&pdev->dev, "pingroup %d: bad mux_bank\n", i);
-                        config_bad = 1;
-                }
-
-                if (pingroups[i].pupd_bank >= nbanks) {
-                        dev_err(&pdev->dev, "pingroup %d: bad pupd_bank\n", i);
-                        config_bad = 1;
-                }
-        }
-
-        for (i = 0; i < drive_max; i++) {
-                if (drive_pingroups[i].reg_bank >= nbanks) {
-                        dev_err(&pdev->dev,
-                                "drive pingroup %d: bad reg_bank\n", i);
-                        config_bad = 1;
-                }
-        }
-
-        if (config_bad)
-                return -ENODEV;
-
-        regs = devm_kzalloc(&pdev->dev, nbanks * sizeof(*regs), GFP_KERNEL);
-        if (!regs) {
-                dev_err(&pdev->dev, "Can't alloc regs pointer\n");
-                return -ENODEV;
-        }
-
-        for (i = 0; i < nbanks; i++) {
-                res = platform_get_resource(pdev, IORESOURCE_MEM, i);
-                if (!res) {
-                        dev_err(&pdev->dev, "Missing MEM resource\n");
-                        return -ENODEV;
-                }
-
-                if (!devm_request_mem_region(&pdev->dev, res->start,
-                                            resource_size(res),
-                                            dev_name(&pdev->dev))) {
-                        dev_err(&pdev->dev,
-                                "Couldn't request MEM resource %d\n", i);
-                        return -ENODEV;
-                }
-
-                regs[i] = devm_ioremap(&pdev->dev, res->start,
-                                        resource_size(res));
-                if (!regs) {
-                        dev_err(&pdev->dev, "Couldn't ioremap regs %d\n", i);
-                        return -ENODEV;
-                }
-        }
-
-        return 0;
-}
-
-static struct platform_driver tegra_pinmux_driver = {
-        .driver         = {
-                .name   = "tegra-pinmux",
-                .owner  = THIS_MODULE,
-                .of_match_table = tegra_pinmux_of_match,
-        },
-        .probe          = tegra_pinmux_probe,
-};
-
-static int __init tegra_pinmux_init(void)
-{
-        return platform_driver_register(&tegra_pinmux_driver);
-}
-postcore_initcall(tegra_pinmux_init);
-
-#ifdef  CONFIG_DEBUG_FS
-
-#include <linux/debugfs.h>
-#include <linux/seq_file.h>
-
-static void dbg_pad_field(struct seq_file *s, int len)
-{
-        seq_putc(s, ',');
-
-        while (len-- > -1)
-                seq_putc(s, ' ');
-}
-
-static int dbg_pinmux_show(struct seq_file *s, void *unused)
-{
-        int i;
-        int len;
-
-        for (i = 0; i < pingroup_max; i++) {
-                unsigned long reg;
-                unsigned long tri;
-                unsigned long mux;
-                unsigned long pupd;
-
-                seq_printf(s, "\t{TEGRA_PINGROUP_%s", pingroups[i].name);
-                len = strlen(pingroups[i].name);
-                dbg_pad_field(s, 5 - len);
-
-                if (pingroups[i].mux_reg < 0) {
-                        seq_printf(s, "TEGRA_MUX_NONE");
-                        len = strlen("NONE");
-                } else {
-                        reg = pg_readl(pingroups[i].mux_bank,
-                                        pingroups[i].mux_reg);
-                        mux = (reg >> pingroups[i].mux_bit) & 0x3;
-                        if (pingroups[i].funcs[mux] == TEGRA_MUX_RSVD) {
-                                seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux+1);
-                                len = 5;
-                        } else {
-                                seq_printf(s, "TEGRA_MUX_%s",
-                                           tegra_mux_names[pingroups[i].funcs[mux]]);
-                                len = strlen(tegra_mux_names[pingroups[i].funcs[mux]]);
-                        }
-                }
-                dbg_pad_field(s, 13-len);
-
-                if (pingroups[i].pupd_reg < 0) {
-                        seq_printf(s, "TEGRA_PUPD_NORMAL");
-                        len = strlen("NORMAL");
-                } else {
-                        reg = pg_readl(pingroups[i].pupd_bank,
-                                        pingroups[i].pupd_reg);
-                        pupd = (reg >> pingroups[i].pupd_bit) & 0x3;
-                        seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd));
-                        len = strlen(pupd_name(pupd));
-                }
-                dbg_pad_field(s, 9 - len);
-
-                if (pingroups[i].tri_reg < 0) {
-                        seq_printf(s, "TEGRA_TRI_NORMAL");
-                } else {
-                        reg = pg_readl(pingroups[i].tri_bank,
-                                        pingroups[i].tri_reg);
-                        tri = (reg >> pingroups[i].tri_bit) & 0x1;
-
-                        seq_printf(s, "TEGRA_TRI_%s", tri_name(tri));
-                }
-                seq_printf(s, "},\n");
-        }
-        return 0;
-}
-
-static int dbg_pinmux_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, dbg_pinmux_show, &inode->i_private);
-}
-
-static const struct file_operations debug_fops = {
-        .open           = dbg_pinmux_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-};
-
-static int dbg_drive_pinmux_show(struct seq_file *s, void *unused)
-{
-        int i;
-        int len;
-
-        for (i = 0; i < drive_max; i++) {
-                u32 reg;
-
-                seq_printf(s, "\t{TEGRA_DRIVE_PINGROUP_%s",
-                        drive_pingroups[i].name);
-                len = strlen(drive_pingroups[i].name);
-                dbg_pad_field(s, 7 - len);
-
-
-                reg = pg_readl(drive_pingroups[i].reg_bank,
-                                drive_pingroups[i].reg);
-                if (HSM_EN(reg)) {
-                        seq_printf(s, "TEGRA_HSM_ENABLE");
-                        len = 16;
-                } else {
-                        seq_printf(s, "TEGRA_HSM_DISABLE");
-                        len = 17;
-                }
-                dbg_pad_field(s, 17 - len);
-
-                if (SCHMT_EN(reg)) {
-                        seq_printf(s, "TEGRA_SCHMITT_ENABLE");
-                        len = 21;
-                } else {
-                        seq_printf(s, "TEGRA_SCHMITT_DISABLE");
-                        len = 22;
-                }
-                dbg_pad_field(s, 22 - len);
-
-                seq_printf(s, "TEGRA_DRIVE_%s", drive_name(LPMD(reg)));
-                len = strlen(drive_name(LPMD(reg)));
-                dbg_pad_field(s, 5 - len);
-
-                seq_printf(s, "TEGRA_PULL_%d", DRVDN(reg));
-                len = DRVDN(reg) < 10 ? 1 : 2;
-                dbg_pad_field(s, 2 - len);
-
-                seq_printf(s, "TEGRA_PULL_%d", DRVUP(reg));
-                len = DRVUP(reg) < 10 ? 1 : 2;
-                dbg_pad_field(s, 2 - len);
-
-                seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWR(reg)));
-                len = strlen(slew_name(SLWR(reg)));
-                dbg_pad_field(s, 7 - len);
-
-                seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWF(reg)));
-
-                seq_printf(s, "},\n");
-        }
-        return 0;
-}
-
-static int dbg_drive_pinmux_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, dbg_drive_pinmux_show, &inode->i_private);
-}
-
-static const struct file_operations debug_drive_fops = {
-        .open           = dbg_drive_pinmux_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-};
-
-static int __init tegra_pinmux_debuginit(void)
-{
-        (void) debugfs_create_file("tegra_pinmux", S_IRUGO,
-                                        NULL, NULL, &debug_fops);
-        (void) debugfs_create_file("tegra_pinmux_drive", S_IRUGO,
-                                        NULL, NULL, &debug_drive_fops);
-        return 0;
-}
-late_initcall(tegra_pinmux_debuginit);
-#endif
diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c
index c5b2ac04e2a0..d71d2fed6721 100644
--- a/arch/arm/mach-tegra/usb_phy.c
+++ b/arch/arm/mach-tegra/usb_phy.c
@@ -711,7 +711,6 @@ struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs,
                         err = -ENXIO;
                         goto err1;
                 }
-                tegra_gpio_enable(ulpi_config->reset_gpio);
                 gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b");
                 gpio_direction_output(ulpi_config->reset_gpio, 0);
                 phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 465b9ec9510a..015932c6bf08 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -3,7 +3,7 @@
 #
 
 obj-y                           := clock.o cpu.o devices.o devices-common.o \
-                                   id.o usb.o timer.o
+                                   id.o pins.o usb.o timer.o
 obj-$(CONFIG_CACHE_L2X0)        += cache-l2x0.o
 obj-$(CONFIG_UX500_SOC_DB5500)  += cpu-db5500.o dma-db5500.o
 obj-$(CONFIG_UX500_SOC_DB8500)  += cpu-db8500.o devices-db8500.o
@@ -11,7 +11,8 @@ obj-$(CONFIG_MACH_MOP500)	+= board-mop500.o board-mop500-sdi.o \
                                 board-mop500-regulators.o \
                                 board-mop500-uib.o board-mop500-stuib.o \
                                 board-mop500-u8500uib.o \
-                                board-mop500-pins.o
+                                board-mop500-pins.o \
+                                board-mop500-msp.o
 obj-$(CONFIG_MACH_U5500)        += board-u5500.o board-u5500-sdi.o
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-msp.c
new file mode 100644
index 000000000000..c8f6300cb7d2
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-msp.c
@@ -0,0 +1,250 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <plat/gpio-nomadik.h>
+
+#include <plat/pincfg.h>
+#include <plat/ste_dma40.h>
+
+#include <mach/devices.h>
+#include <ste-dma40-db8500.h>
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <mach/msp.h>
+
+#include "board-mop500.h"
+#include "devices-db8500.h"
+#include "pins-db8500.h"
+
+/* MSP1/3 Tx/Rx usage protection */
+static DEFINE_SPINLOCK(msp_rxtx_lock);
+
+/* Reference Count */
+static int msp_rxtx_ref;
+
+static pin_cfg_t mop500_msp1_pins_init[] = {
+                GPIO33_MSP1_TXD | PIN_OUTPUT_LOW   | PIN_SLPM_WAKEUP_DISABLE,
+                GPIO34_MSP1_TFS | PIN_INPUT_NOPULL | PIN_SLPM_WAKEUP_DISABLE,
+                GPIO35_MSP1_TCK | PIN_INPUT_NOPULL | PIN_SLPM_WAKEUP_DISABLE,
+                GPIO36_MSP1_RXD | PIN_INPUT_NOPULL | PIN_SLPM_WAKEUP_DISABLE,
+};
+
+static pin_cfg_t mop500_msp1_pins_exit[] = {
+                GPIO33_MSP1_TXD | PIN_OUTPUT_LOW   | PIN_SLPM_WAKEUP_ENABLE,
+                GPIO34_MSP1_TFS | PIN_INPUT_NOPULL | PIN_SLPM_WAKEUP_ENABLE,
+                GPIO35_MSP1_TCK | PIN_INPUT_NOPULL | PIN_SLPM_WAKEUP_ENABLE,
+                GPIO36_MSP1_RXD | PIN_INPUT_NOPULL | PIN_SLPM_WAKEUP_ENABLE,
+};
+
+int msp13_i2s_init(void)
+{
+        int retval = 0;
+        unsigned long flags;
+
+        spin_lock_irqsave(&msp_rxtx_lock, flags);
+        if (msp_rxtx_ref == 0)
+                retval = nmk_config_pins(
+                                ARRAY_AND_SIZE(mop500_msp1_pins_init));
+        if (!retval)
+                msp_rxtx_ref++;
+        spin_unlock_irqrestore(&msp_rxtx_lock, flags);
+
+        return retval;
+}
+
+int msp13_i2s_exit(void)
+{
+        int retval = 0;
+        unsigned long flags;
+
+        spin_lock_irqsave(&msp_rxtx_lock, flags);
+        WARN_ON(!msp_rxtx_ref);
+        msp_rxtx_ref--;
+        if (msp_rxtx_ref == 0)
+                retval = nmk_config_pins_sleep(
+                                ARRAY_AND_SIZE(mop500_msp1_pins_exit));
+        spin_unlock_irqrestore(&msp_rxtx_lock, flags);
+
+        return retval;
+}
+
+static struct stedma40_chan_cfg msp0_dma_rx = {
+        .high_priority = true,
+        .dir = STEDMA40_PERIPH_TO_MEM,
+
+        .src_dev_type = DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX,
+        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+
+        .src_info.psize = STEDMA40_PSIZE_LOG_4,
+        .dst_info.psize = STEDMA40_PSIZE_LOG_4,
+
+        /* data_width is set during configuration */
+};
+
+static struct stedma40_chan_cfg msp0_dma_tx = {
+        .high_priority = true,
+        .dir = STEDMA40_MEM_TO_PERIPH,
+
+        .src_dev_type = STEDMA40_DEV_DST_MEMORY,
+        .dst_dev_type = DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX,
+
+        .src_info.psize = STEDMA40_PSIZE_LOG_4,
+        .dst_info.psize = STEDMA40_PSIZE_LOG_4,
+
+        /* data_width is set during configuration */
+};
+
+static struct msp_i2s_platform_data msp0_platform_data = {
+        .id = MSP_I2S_0,
+        .msp_i2s_dma_rx = &msp0_dma_rx,
+        .msp_i2s_dma_tx = &msp0_dma_tx,
+};
+
+static struct stedma40_chan_cfg msp1_dma_rx = {
+        .high_priority = true,
+        .dir = STEDMA40_PERIPH_TO_MEM,
+
+        .src_dev_type = DB8500_DMA_DEV30_MSP3_RX,
+        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+
+        .src_info.psize = STEDMA40_PSIZE_LOG_4,
+        .dst_info.psize = STEDMA40_PSIZE_LOG_4,
+
+        /* data_width is set during configuration */
+};
+
+static struct stedma40_chan_cfg msp1_dma_tx = {
+        .high_priority = true,
+        .dir = STEDMA40_MEM_TO_PERIPH,
+
+        .src_dev_type = STEDMA40_DEV_DST_MEMORY,
+        .dst_dev_type = DB8500_DMA_DEV30_MSP1_TX,
+
+        .src_info.psize = STEDMA40_PSIZE_LOG_4,
+        .dst_info.psize = STEDMA40_PSIZE_LOG_4,
+
+        /* data_width is set during configuration */
+};
+
+static struct msp_i2s_platform_data msp1_platform_data = {
+        .id = MSP_I2S_1,
+        .msp_i2s_dma_rx = NULL,
+        .msp_i2s_dma_tx = &msp1_dma_tx,
+        .msp_i2s_init = msp13_i2s_init,
+        .msp_i2s_exit = msp13_i2s_exit,
+};
+
+static struct stedma40_chan_cfg msp2_dma_rx = {
+        .high_priority = true,
+        .dir = STEDMA40_PERIPH_TO_MEM,
+
+        .src_dev_type = DB8500_DMA_DEV14_MSP2_RX,
+        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+
+        /* MSP2 DMA doesn't work with PSIZE == 4 on DB8500v2 */
+        .src_info.psize = STEDMA40_PSIZE_LOG_1,
+        .dst_info.psize = STEDMA40_PSIZE_LOG_1,
+
+        /* data_width is set during configuration */
+};
+
+static struct stedma40_chan_cfg msp2_dma_tx = {
+        .high_priority = true,
+        .dir = STEDMA40_MEM_TO_PERIPH,
+
+        .src_dev_type = STEDMA40_DEV_DST_MEMORY,
+        .dst_dev_type = DB8500_DMA_DEV14_MSP2_TX,
+
+        .src_info.psize = STEDMA40_PSIZE_LOG_4,
+        .dst_info.psize = STEDMA40_PSIZE_LOG_4,
+
+        .use_fixed_channel = true,
+        .phy_channel = 1,
+
+        /* data_width is set during configuration */
+};
+
+static int db8500_add_msp_i2s(struct device *parent, int id,
+                        resource_size_t base, int irq,
+                        struct msp_i2s_platform_data *pdata)
+{
+        struct platform_device *pdev;
+        struct resource res[] = {
+                DEFINE_RES_MEM(base, SZ_4K),
+                DEFINE_RES_IRQ(irq),
+        };
+
+        pr_info("Register platform-device 'ux500-msp-i2s', id %d, irq %d\n",
+                id, irq);
+        pdev = platform_device_register_resndata(parent, "ux500-msp-i2s", id,
+                                                res, ARRAY_SIZE(res),
+                                                pdata, sizeof(*pdata));
+        if (!pdev) {
+                pr_err("Failed to register platform-device 'ux500-msp-i2s.%d'!\n",
+                        id);
+                return -EIO;
+        }
+
+        return 0;
+}
+
+/* Platform device for ASoC U8500 machine */
+static struct platform_device snd_soc_u8500 = {
+                .name = "snd-soc-u8500",
+                .id = 0,
+                .dev = {
+                        .platform_data = NULL,
+                },
+};
+
+/* Platform device for Ux500-PCM */
+static struct platform_device ux500_pcm = {
+                .name = "ux500-pcm",
+                .id = 0,
+                .dev = {
+                        .platform_data = NULL,
+                },
+};
+
+static struct msp_i2s_platform_data msp2_platform_data = {
+        .id = MSP_I2S_2,
+        .msp_i2s_dma_rx = &msp2_dma_rx,
+        .msp_i2s_dma_tx = &msp2_dma_tx,
+};
+
+static struct msp_i2s_platform_data msp3_platform_data = {
+        .id             = MSP_I2S_3,
+        .msp_i2s_dma_rx = &msp1_dma_rx,
+        .msp_i2s_dma_tx = NULL,
+        .msp_i2s_init = msp13_i2s_init,
+        .msp_i2s_exit = msp13_i2s_exit,
+};
+
+int mop500_msp_init(struct device *parent)
+{
+        int ret;
+
+        pr_info("%s: Register platform-device 'snd-soc-u8500'.\n", __func__);
+        platform_device_register(&snd_soc_u8500);
+
+        pr_info("Initialize MSP I2S-devices.\n");
+        ret = db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
+                                &msp0_platform_data);
+        ret |= db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1,
+                                &msp1_platform_data);
+        ret |= db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2,
+                                &msp2_platform_data);
+        ret |= db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1,
+                                &msp3_platform_data);
+
+        pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
+        platform_device_register(&ux500_pcm);
+
+        return ret;
+}
diff --git a/arch/arm/mach-ux500/board-mop500-msp.h b/arch/arm/mach-ux500/board-mop500-msp.h
new file mode 100644
index 000000000000..6fcfb5e2cc94
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-msp.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2012
+ *
+ * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
+ *         for ST-Ericsson.
+ *
+ * License terms:
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+void mop500_msp_init(struct device *parent);
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index f5413dca532c..df5b190d331c 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -7,109 +7,47 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/bug.h>
+#include <linux/string.h>
 
 #include <asm/mach-types.h>
 #include <plat/pincfg.h>
 #include <plat/gpio-nomadik.h>
+
 #include <mach/hardware.h>
 
 #include "pins-db8500.h"
+#include "pins.h"
+#include "board-mop500.h"
+
+enum custom_pin_cfg_t {
+        PINS_FOR_DEFAULT,
+        PINS_FOR_U9500,
+};
+
+static enum custom_pin_cfg_t pinsfor;
 
 static pin_cfg_t mop500_pins_common[] = {
-        /* I2C */
-        GPIO147_I2C0_SCL,
-        GPIO148_I2C0_SDA,
-        GPIO16_I2C1_SCL,
-        GPIO17_I2C1_SDA,
-        GPIO10_I2C2_SDA,
-        GPIO11_I2C2_SCL,
-        GPIO229_I2C3_SDA,
-        GPIO230_I2C3_SCL,
-
-        /* MSP0 */
+        /* uMSP0 */
         GPIO12_MSP0_TXD,
         GPIO13_MSP0_TFS,
         GPIO14_MSP0_TCK,
         GPIO15_MSP0_RXD,
 
         /* MSP2: HDMI */
-        GPIO193_MSP2_TXD,
-        GPIO194_MSP2_TCK,
-        GPIO195_MSP2_TFS,
+        GPIO193_MSP2_TXD | PIN_INPUT_PULLDOWN,
+        GPIO194_MSP2_TCK | PIN_INPUT_PULLDOWN,
+        GPIO195_MSP2_TFS | PIN_INPUT_PULLDOWN,
         GPIO196_MSP2_RXD | PIN_OUTPUT_LOW,
 
+        /* LCD TE0 */
+        GPIO68_LCD_VSI0 | PIN_INPUT_PULLUP,
+
         /* Touch screen INTERFACE */
         GPIO84_GPIO     | PIN_INPUT_PULLUP, /* TOUCH_INT1 */
 
         /* STMPE1601/tc35893 keypad  IRQ */
         GPIO218_GPIO    | PIN_INPUT_PULLUP,
 
-        /* MMC0 (MicroSD card) */
-        GPIO18_MC0_CMDDIR       | PIN_OUTPUT_HIGH,
-        GPIO19_MC0_DAT0DIR      | PIN_OUTPUT_HIGH,
-        GPIO20_MC0_DAT2DIR      | PIN_OUTPUT_HIGH,
-
-        GPIO22_MC0_FBCLK        | PIN_INPUT_NOPULL,
-        GPIO23_MC0_CLK          | PIN_OUTPUT_LOW,
-        GPIO24_MC0_CMD          | PIN_INPUT_PULLUP,
-        GPIO25_MC0_DAT0         | PIN_INPUT_PULLUP,
-        GPIO26_MC0_DAT1         | PIN_INPUT_PULLUP,
-        GPIO27_MC0_DAT2         | PIN_INPUT_PULLUP,
-        GPIO28_MC0_DAT3         | PIN_INPUT_PULLUP,
-
-        /* SDI1 (SDIO) */
-        GPIO208_MC1_CLK         | PIN_OUTPUT_LOW,
-        GPIO209_MC1_FBCLK       | PIN_INPUT_NOPULL,
-        GPIO210_MC1_CMD         | PIN_INPUT_PULLUP,
-        GPIO211_MC1_DAT0        | PIN_INPUT_PULLUP,
-        GPIO212_MC1_DAT1        | PIN_INPUT_PULLUP,
-        GPIO213_MC1_DAT2        | PIN_INPUT_PULLUP,
-        GPIO214_MC1_DAT3        | PIN_INPUT_PULLUP,
-
-        /* MMC2 (On-board DATA INTERFACE eMMC) */
-        GPIO128_MC2_CLK         | PIN_OUTPUT_LOW,
-        GPIO129_MC2_CMD         | PIN_INPUT_PULLUP,
-        GPIO130_MC2_FBCLK       | PIN_INPUT_NOPULL,
-        GPIO131_MC2_DAT0        | PIN_INPUT_PULLUP,
-        GPIO132_MC2_DAT1        | PIN_INPUT_PULLUP,
-        GPIO133_MC2_DAT2        | PIN_INPUT_PULLUP,
-        GPIO134_MC2_DAT3        | PIN_INPUT_PULLUP,
-        GPIO135_MC2_DAT4        | PIN_INPUT_PULLUP,
-        GPIO136_MC2_DAT5        | PIN_INPUT_PULLUP,
-        GPIO137_MC2_DAT6        | PIN_INPUT_PULLUP,
-        GPIO138_MC2_DAT7        | PIN_INPUT_PULLUP,
-
-        /* MMC4 (On-board STORAGE INTERFACE eMMC) */
-        GPIO197_MC4_DAT3        | PIN_INPUT_PULLUP,
-        GPIO198_MC4_DAT2        | PIN_INPUT_PULLUP,
-        GPIO199_MC4_DAT1        | PIN_INPUT_PULLUP,
-        GPIO200_MC4_DAT0        | PIN_INPUT_PULLUP,
-        GPIO201_MC4_CMD         | PIN_INPUT_PULLUP,
-        GPIO202_MC4_FBCLK       | PIN_INPUT_NOPULL,
-        GPIO203_MC4_CLK         | PIN_OUTPUT_LOW,
-        GPIO204_MC4_DAT7        | PIN_INPUT_PULLUP,
-        GPIO205_MC4_DAT6        | PIN_INPUT_PULLUP,
-        GPIO206_MC4_DAT5        | PIN_INPUT_PULLUP,
-        GPIO207_MC4_DAT4        | PIN_INPUT_PULLUP,
-
-        /* SKE keypad */
-        GPIO153_KP_I7,
-        GPIO154_KP_I6,
-        GPIO155_KP_I5,
-        GPIO156_KP_I4,
-        GPIO157_KP_O7,
-        GPIO158_KP_O6,
-        GPIO159_KP_O5,
-        GPIO160_KP_O4,
-        GPIO161_KP_I3,
-        GPIO162_KP_I2,
-        GPIO163_KP_I1,
-        GPIO164_KP_I0,
-        GPIO165_KP_O3,
-        GPIO166_KP_O2,
-        GPIO167_KP_O1,
-        GPIO168_KP_O0,
-
         /* UART */
         /* uart-0 pins gpio configuration should be
          * kept intact to prevent glitch in tx line
@@ -128,10 +66,6 @@ static pin_cfg_t mop500_pins_common[] = {
         GPIO30_U2_TXD   | PIN_OUTPUT_HIGH,
         GPIO31_U2_CTSn  | PIN_INPUT_PULLUP,
         GPIO32_U2_RTSn  | PIN_OUTPUT_HIGH,
-
-        /* Display & HDMI HW sync */
-        GPIO68_LCD_VSI0 | PIN_INPUT_PULLUP,
-        GPIO69_LCD_VSI1 | PIN_INPUT_PULLUP,
 };
 
 static pin_cfg_t mop500_pins_default[] = {
@@ -141,10 +75,13 @@ static pin_cfg_t mop500_pins_default[] = {
         GPIO145_SSP0_RXD | PIN_PULL_DOWN,
         GPIO146_SSP0_TXD,
 
+        /* XENON Flashgun INTERFACE */
+        GPIO6_IP_GPIO0  | PIN_INPUT_PULLUP,/* XENON_FLASH_ID */
+        GPIO7_IP_GPIO1  | PIN_INPUT_PULLUP,/* XENON_READY */
 
         GPIO217_GPIO    | PIN_INPUT_PULLUP, /* TC35892 IRQ */
 
-        /* SDI0 (MicroSD card) */
+        /* sdi0 (removable MMC/SD/SDIO cards) not handled by pm_runtime */
         GPIO21_MC0_DAT31DIR     | PIN_OUTPUT_HIGH,
 
         /* UART */
@@ -156,13 +93,11 @@ static pin_cfg_t mop500_pins_default[] = {
 
 static pin_cfg_t hrefv60_pins[] = {
         /* WLAN */
-        GPIO4_GPIO              | PIN_INPUT_PULLUP,/* WLAN_IRQ */
         GPIO85_GPIO             | PIN_OUTPUT_LOW,/* WLAN_ENA */
 
         /* XENON Flashgun INTERFACE */
         GPIO6_IP_GPIO0  | PIN_INPUT_PULLUP,/* XENON_FLASH_ID */
         GPIO7_IP_GPIO1  | PIN_INPUT_PULLUP,/* XENON_READY */
-        GPIO170_GPIO    | PIN_OUTPUT_LOW, /* XENON_CHARGE */
 
         /* Assistant LED INTERFACE */
         GPIO21_GPIO | PIN_OUTPUT_LOW,  /* XENON_EN1 */
@@ -173,7 +108,7 @@ static pin_cfg_t hrefv60_pins[] = {
         GPIO32_GPIO | PIN_INPUT_PULLDOWN, /* Magnetometer DRDY */
 
         /* Display Interface */
-        GPIO65_GPIO             | PIN_OUTPUT_LOW, /* DISP1 RST */
+        GPIO65_GPIO             | PIN_OUTPUT_HIGH, /* DISP1 NO RST */
         GPIO66_GPIO             | PIN_OUTPUT_LOW, /* DISP2 RST */
 
         /* Touch screen INTERFACE */
@@ -215,11 +150,8 @@ static pin_cfg_t hrefv60_pins[] = {
         /* DiPro Sensor Interface */
         GPIO139_GPIO    | PIN_INPUT_PULLUP, /* DIPRO_INT */
 
-        /* HAL SWITCH INTERFACE */
-        GPIO145_GPIO    | PIN_INPUT_PULLDOWN,/* HAL_SW */
-
         /* Audio Amplifier Interface */
-        GPIO149_GPIO    | PIN_OUTPUT_LOW, /* VAUDIO_HF_EN */
+        GPIO149_GPIO    | PIN_OUTPUT_HIGH, /* VAUDIO_HF_EN, enable MAX8968 */
 
         /* GBF INTERFACE */
         GPIO171_GPIO    | PIN_OUTPUT_LOW, /* GBF_ENA_RESET */
@@ -231,10 +163,29 @@ static pin_cfg_t hrefv60_pins[] = {
         GPIO82_GPIO             | PIN_INPUT_PULLUP, /* ACC_INT1 */
         GPIO83_GPIO             | PIN_INPUT_PULLUP, /* ACC_INT2 */
 
-        /* Proximity Sensor */
-        GPIO217_GPIO            | PIN_INPUT_PULLUP,
+        /* SD card detect */
+        GPIO95_GPIO     | PIN_INPUT_PULLUP,
+};
 
+static pin_cfg_t u9500_pins[] = {
+        GPIO4_U1_RXD    | PIN_INPUT_PULLUP,
+        GPIO5_U1_TXD    | PIN_OUTPUT_HIGH,
+        GPIO144_GPIO    | PIN_INPUT_PULLUP,/* WLAN_IRQ */
+
+        /* HSI */
+        GPIO219_HSIR_FLA0 | PIN_INPUT_PULLDOWN,
+        GPIO220_HSIR_DAT0 | PIN_INPUT_PULLDOWN,
+        GPIO221_HSIR_RDY0 | PIN_OUTPUT_LOW,
+        GPIO222_HSIT_FLA0 | PIN_OUTPUT_LOW,
+        GPIO223_HSIT_DAT0 | PIN_OUTPUT_LOW,
+        GPIO224_HSIT_RDY0 | PIN_INPUT_PULLDOWN,
+        GPIO225_HSIT_CAWAKE0 | PIN_INPUT_PULLDOWN, /* CA_WAKE0 */
+        GPIO226_GPIO    | PIN_OUTPUT_HIGH, /* AC_WAKE0 */
+};
 
+static pin_cfg_t u8500_pins[] = {
+        GPIO226_GPIO    | PIN_OUTPUT_LOW, /* WLAN_PMU_EN */
+        GPIO4_GPIO              | PIN_INPUT_PULLUP,/* WLAN_IRQ */
 };
 
 static pin_cfg_t snowball_pins[] = {
@@ -275,13 +226,245 @@ static pin_cfg_t snowball_pins[] = {
 
         /* RSTn_LAN */
         GPIO141_GPIO            | PIN_OUTPUT_HIGH,
+
+        /*  Accelerometer/Magnetometer */
+        GPIO163_GPIO            | PIN_INPUT_PULLUP, /* ACCEL_IRQ1 */
+        GPIO164_GPIO            | PIN_INPUT_PULLUP, /* ACCEL_IRQ2 */
+        GPIO165_GPIO            | PIN_INPUT_PULLUP, /* MAG_DRDY */
+
+        /* WLAN/GBF */
+        GPIO161_GPIO            | PIN_OUTPUT_LOW, /* WLAN_PMU_EN */
+        GPIO171_GPIO            | PIN_OUTPUT_HIGH,/* GBF_ENA */
+        GPIO215_GPIO            | PIN_OUTPUT_LOW,/* WLAN_ENA */
+        GPIO216_GPIO            | PIN_INPUT_PULLUP,/* WLAN_IRQ */
+};
+
+/*
+ * I2C
+ */
+
+static UX500_PINS(mop500_pins_i2c0,
+        GPIO147_I2C0_SCL |
+                PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
+        GPIO148_I2C0_SDA |
+                PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
+);
+
+static UX500_PINS(mop500_pins_i2c1,
+        GPIO16_I2C1_SCL |
+                PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
+        GPIO17_I2C1_SDA |
+                PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
+);
+
+static UX500_PINS(mop500_pins_i2c2,
+        GPIO10_I2C2_SDA |
+                PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
+        GPIO11_I2C2_SCL |
+                PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
+);
+
+static UX500_PINS(mop500_pins_i2c3,
+        GPIO229_I2C3_SDA |
+                PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
+        GPIO230_I2C3_SCL |
+                PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
+);
+
+static UX500_PINS(mop500_pins_mcde_tvout,
+        GPIO78_LCD_D8,
+        GPIO79_LCD_D9,
+        GPIO80_LCD_D10,
+        GPIO81_LCD_D11,
+        GPIO150_LCDA_CLK,
+);
+
+static UX500_PINS(mop500_pins_mcde_hdmi,
+        GPIO69_LCD_VSI1 | PIN_INPUT_PULLUP,
+);
+
+static UX500_PINS(mop500_pins_ske,
+        GPIO153_KP_I7 | PIN_INPUT_PULLDOWN | PIN_SLPM_INPUT_PULLUP,
+        GPIO154_KP_I6 | PIN_INPUT_PULLDOWN | PIN_SLPM_INPUT_PULLUP,
+        GPIO155_KP_I5 | PIN_INPUT_PULLDOWN | PIN_SLPM_INPUT_PULLUP,
+        GPIO156_KP_I4 | PIN_INPUT_PULLDOWN | PIN_SLPM_INPUT_PULLUP,
+        GPIO161_KP_I3 | PIN_INPUT_PULLDOWN | PIN_SLPM_INPUT_PULLUP,
+        GPIO162_KP_I2 | PIN_INPUT_PULLDOWN | PIN_SLPM_INPUT_PULLUP,
+        GPIO163_KP_I1 | PIN_INPUT_PULLDOWN | PIN_SLPM_INPUT_PULLUP,
+        GPIO164_KP_I0 | PIN_INPUT_PULLDOWN | PIN_SLPM_INPUT_PULLUP,
+        GPIO157_KP_O7 | PIN_INPUT_PULLUP | PIN_SLPM_OUTPUT_LOW,
+        GPIO158_KP_O6 | PIN_INPUT_PULLUP | PIN_SLPM_OUTPUT_LOW,
+        GPIO159_KP_O5 | PIN_INPUT_PULLUP | PIN_SLPM_OUTPUT_LOW,
+        GPIO160_KP_O4 | PIN_INPUT_PULLUP | PIN_SLPM_OUTPUT_LOW,
+        GPIO165_KP_O3 | PIN_INPUT_PULLUP | PIN_SLPM_OUTPUT_LOW,
+        GPIO166_KP_O2 | PIN_INPUT_PULLUP | PIN_SLPM_OUTPUT_LOW,
+        GPIO167_KP_O1 | PIN_INPUT_PULLUP | PIN_SLPM_OUTPUT_LOW,
+        GPIO168_KP_O0 | PIN_INPUT_PULLUP | PIN_SLPM_OUTPUT_LOW,
+);
+
+/* sdi0 (removable MMC/SD/SDIO cards) */
+static UX500_PINS(mop500_pins_sdi0,
+        GPIO18_MC0_CMDDIR       | PIN_OUTPUT_HIGH,
+        GPIO19_MC0_DAT0DIR      | PIN_OUTPUT_HIGH,
+        GPIO20_MC0_DAT2DIR      | PIN_OUTPUT_HIGH,
+
+        GPIO22_MC0_FBCLK        | PIN_INPUT_NOPULL,
+        GPIO23_MC0_CLK          | PIN_OUTPUT_LOW,
+        GPIO24_MC0_CMD          | PIN_INPUT_PULLUP,
+        GPIO25_MC0_DAT0         | PIN_INPUT_PULLUP,
+        GPIO26_MC0_DAT1         | PIN_INPUT_PULLUP,
+        GPIO27_MC0_DAT2         | PIN_INPUT_PULLUP,
+        GPIO28_MC0_DAT3         | PIN_INPUT_PULLUP,
+);
+
+/* sdi1 (WLAN CW1200) */
+static UX500_PINS(mop500_pins_sdi1,
+        GPIO208_MC1_CLK         | PIN_OUTPUT_LOW,
+        GPIO209_MC1_FBCLK       | PIN_INPUT_NOPULL,
+        GPIO210_MC1_CMD         | PIN_INPUT_PULLUP,
+        GPIO211_MC1_DAT0        | PIN_INPUT_PULLUP,
+        GPIO212_MC1_DAT1        | PIN_INPUT_PULLUP,
+        GPIO213_MC1_DAT2        | PIN_INPUT_PULLUP,
+        GPIO214_MC1_DAT3        | PIN_INPUT_PULLUP,
+);
+
+/* sdi2 (POP eMMC) */
+static UX500_PINS(mop500_pins_sdi2,
+        GPIO128_MC2_CLK         | PIN_OUTPUT_LOW,
+        GPIO129_MC2_CMD         | PIN_INPUT_PULLUP,
+        GPIO130_MC2_FBCLK       | PIN_INPUT_NOPULL,
+        GPIO131_MC2_DAT0        | PIN_INPUT_PULLUP,
+        GPIO132_MC2_DAT1        | PIN_INPUT_PULLUP,
+        GPIO133_MC2_DAT2        | PIN_INPUT_PULLUP,
+        GPIO134_MC2_DAT3        | PIN_INPUT_PULLUP,
+        GPIO135_MC2_DAT4        | PIN_INPUT_PULLUP,
+        GPIO136_MC2_DAT5        | PIN_INPUT_PULLUP,
+        GPIO137_MC2_DAT6        | PIN_INPUT_PULLUP,
+        GPIO138_MC2_DAT7        | PIN_INPUT_PULLUP,
+);
+
+/* sdi4 (PCB eMMC) */
+static UX500_PINS(mop500_pins_sdi4,
+        GPIO197_MC4_DAT3        | PIN_INPUT_PULLUP,
+        GPIO198_MC4_DAT2        | PIN_INPUT_PULLUP,
+        GPIO199_MC4_DAT1        | PIN_INPUT_PULLUP,
+        GPIO200_MC4_DAT0        | PIN_INPUT_PULLUP,
+        GPIO201_MC4_CMD         | PIN_INPUT_PULLUP,
+        GPIO202_MC4_FBCLK       | PIN_INPUT_NOPULL,
+        GPIO203_MC4_CLK         | PIN_OUTPUT_LOW,
+        GPIO204_MC4_DAT7        | PIN_INPUT_PULLUP,
+        GPIO205_MC4_DAT6        | PIN_INPUT_PULLUP,
+        GPIO206_MC4_DAT5        | PIN_INPUT_PULLUP,
+        GPIO207_MC4_DAT4        | PIN_INPUT_PULLUP,
+);
+
+/* USB */
+static UX500_PINS(mop500_pins_usb,
+        GPIO256_USB_NXT,
+        GPIO257_USB_STP         | PIN_OUTPUT_HIGH,
+        GPIO258_USB_XCLK,
+        GPIO259_USB_DIR,
+        GPIO260_USB_DAT7,
+        GPIO261_USB_DAT6,
+        GPIO262_USB_DAT5,
+        GPIO263_USB_DAT4,
+        GPIO264_USB_DAT3,
+        GPIO265_USB_DAT2,
+        GPIO266_USB_DAT1,
+        GPIO267_USB_DAT0,
+);
+
+/* SPI2 */
+static UX500_PINS(mop500_pins_spi2,
+        GPIO216_GPIO    | PIN_OUTPUT_HIGH,
+        GPIO218_SPI2_RXD        | PIN_INPUT_PULLDOWN,
+        GPIO215_SPI2_TXD        | PIN_OUTPUT_LOW,
+        GPIO217_SPI2_CLK        | PIN_OUTPUT_LOW,
+);
+
+static UX500_PINS(mop500_pins_sensors1p_v60,
+        GPIO217_GPIO| PIN_INPUT_PULLUP |
+                  PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
+        GPIO145_GPIO | PIN_INPUT_PULLDOWN |
+                  PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
+        GPIO139_GPIO | PIN_INPUT_PULLUP |
+                  PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
+);
+
+static UX500_PINS(mop500_pins_sensors1p,
+        PIN_CFG_INPUT(GPIO_PROX_SENSOR, GPIO, NOPULL),
+        PIN_CFG_INPUT(GPIO_HAL_SENSOR, GPIO, NOPULL),
+);
+
+static struct ux500_pin_lookup mop500_runtime_pins[] = {
+        PIN_LOOKUP("mcde-tvout", &mop500_pins_mcde_tvout),
+        PIN_LOOKUP("av8100-hdmi", &mop500_pins_mcde_hdmi),
+        PIN_LOOKUP("nmk-i2c.0", &mop500_pins_i2c0),
+        PIN_LOOKUP("nmk-i2c.1", &mop500_pins_i2c1),
+        PIN_LOOKUP("nmk-i2c.2", &mop500_pins_i2c2),
+        PIN_LOOKUP("nmk-i2c.3", &mop500_pins_i2c3),
+        PIN_LOOKUP("sdi0", &mop500_pins_sdi0),
+        PIN_LOOKUP("sdi1", &mop500_pins_sdi1),
+        PIN_LOOKUP("sdi2", &mop500_pins_sdi2),
+        PIN_LOOKUP("sdi4", &mop500_pins_sdi4),
+        PIN_LOOKUP("musb-ux500.0", &mop500_pins_usb),
+        PIN_LOOKUP("spi2", &mop500_pins_spi2),
 };
 
+static struct ux500_pin_lookup mop500_runtime_pins_v60[] = {
+        PIN_LOOKUP("ske", &mop500_pins_ske),
+        PIN_LOOKUP("gpio-keys.0", &mop500_pins_sensors1p_v60),
+};
+
+static struct ux500_pin_lookup mop500_runtime_pins_pre_v60[] = {
+        PIN_LOOKUP("ske", &mop500_pins_ske),
+        PIN_LOOKUP("gpio-keys.0", &mop500_pins_sensors1p),
+};
+
+/*
+ * passing "pinsfor=" in kernel cmdline allows for custom
+ * configuration of GPIOs on u8500 derived boards.
+ */
+static int __init early_pinsfor(char *p)
+{
+        pinsfor = PINS_FOR_DEFAULT;
+
+        if (strcmp(p, "u9500-21") == 0)
+                pinsfor = PINS_FOR_U9500;
+
+        return 0;
+}
+early_param("pinsfor", early_pinsfor);
+
+int pins_for_u9500(void)
+{
+        if (pinsfor == PINS_FOR_U9500)
+                return 1;
+
+        return 0;
+}
+
 void __init mop500_pins_init(void)
 {
         nmk_config_pins(mop500_pins_common,
                         ARRAY_SIZE(mop500_pins_common));
 
+        ux500_pins_add(mop500_runtime_pins, ARRAY_SIZE(mop500_runtime_pins));
+
+        ux500_pins_add(mop500_runtime_pins_pre_v60,
+                       ARRAY_SIZE(mop500_runtime_pins_pre_v60));
+
+        switch (pinsfor) {
+        case PINS_FOR_U9500:
+                nmk_config_pins(u9500_pins, ARRAY_SIZE(u9500_pins));
+                break;
+
+        case PINS_FOR_DEFAULT:
+                nmk_config_pins(u8500_pins, ARRAY_SIZE(u8500_pins));
+        default:
+                break;
+        }
+
         nmk_config_pins(mop500_pins_default,
                         ARRAY_SIZE(mop500_pins_default));
 }
@@ -291,8 +474,11 @@ void __init snowball_pins_init(void)
         nmk_config_pins(mop500_pins_common,
                         ARRAY_SIZE(mop500_pins_common));
 
-        nmk_config_pins(snowball_pins,
-                        ARRAY_SIZE(snowball_pins));
+        ux500_pins_add(mop500_runtime_pins, ARRAY_SIZE(mop500_runtime_pins));
+
+        nmk_config_pins(u8500_pins, ARRAY_SIZE(u8500_pins));
+
+        nmk_config_pins(snowball_pins, ARRAY_SIZE(snowball_pins));
 }
 
 void __init hrefv60_pins_init(void)
@@ -300,6 +486,22 @@ void __init hrefv60_pins_init(void)
         nmk_config_pins(mop500_pins_common,
                         ARRAY_SIZE(mop500_pins_common));
 
+        ux500_pins_add(mop500_runtime_pins, ARRAY_SIZE(mop500_runtime_pins));
+
+        ux500_pins_add(mop500_runtime_pins_v60,
+                       ARRAY_SIZE(mop500_runtime_pins_v60));
+
         nmk_config_pins(hrefv60_pins,
                         ARRAY_SIZE(hrefv60_pins));
+
+        switch (pinsfor) {
+        case PINS_FOR_U9500:
+                nmk_config_pins(u9500_pins, ARRAY_SIZE(u9500_pins));
+                break;
+
+        case PINS_FOR_DEFAULT:
+                nmk_config_pins(u8500_pins, ARRAY_SIZE(u8500_pins));
+        default:
+                break;
+        }
 }
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 77d03c1fbd04..ca0d62599f70 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -53,6 +53,7 @@
 #include "devices-db8500.h"
 #include "board-mop500.h"
 #include "board-mop500-regulators.h"
+#include "board-mop500-msp.h"
 
 static struct gpio_led snowball_led_array[] = {
         {
@@ -631,6 +632,7 @@ static void __init mop500_init_machine(void)
         mop500_i2c_init(parent);
         mop500_sdi_init(parent);
         mop500_spi_init(parent);
+        mop500_msp_init(parent);
         mop500_uart_init(parent);
 
         i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
@@ -662,6 +664,7 @@ static void __init snowball_init_machine(void)
         mop500_i2c_init(parent);
         snowball_sdi_init(parent);
         mop500_spi_init(parent);
+        mop500_msp_init(parent);
         mop500_uart_init(parent);
 
         i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
@@ -699,6 +702,7 @@ static void __init hrefv60_init_machine(void)
         mop500_i2c_init(parent);
         hrefv60_sdi_init(parent);
         mop500_spi_init(parent);
+        mop500_msp_init(parent);
         mop500_uart_init(parent);
 
         i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
@@ -746,10 +750,22 @@ MACHINE_END
 #ifdef CONFIG_MACH_UX500_DT
 
 struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
+        /* Requires DMA and call-back bindings. */
         OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
         OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
         OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat),
+        /* Requires DMA bindings. */
         OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
+        /* Requires clock name bindings. */
+        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL),
+        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL),
+        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e000, "gpio.2", NULL),
+        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e080, "gpio.3", NULL),
+        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e100, "gpio.4", NULL),
+        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e180, "gpio.5", NULL),
+        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL),
+        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL),
+        OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL),
         {},
 };
 
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index fdcfa8721bb4..91dc63fe101b 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -7,6 +7,9 @@
 #ifndef __BOARD_MOP500_H
 #define __BOARD_MOP500_H
 
+/* For NOMADIK_NR_GPIO */
+#include <mach/irqs.h>
+
 /* Snowball specific GPIO assignments, this board has no GPIO expander */
 #define SNOWBALL_ACCEL_INT1_GPIO        163
 #define SNOWBALL_ACCEL_INT2_GPIO        164
@@ -73,6 +76,7 @@
 #define SNOWBALL_PME_ETH_GPIO           MOP500_AB8500_PIN_GPIO(24)      /* SYSCLKREQ7/GPIO24 */
 #define SNOWBALL_EN_3V3_ETH_GPIO        MOP500_AB8500_PIN_GPIO(26)      /* GPIO26 */
 
+struct device;
 struct i2c_board_info;
 
 extern void mop500_sdi_init(struct device *parent);
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index ec35f0aa5665..700042cb6681 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -336,6 +336,7 @@ static DEFINE_PRCMU_CLK(uiccclk,	0x4, 1, UICCCLK); /* v1 */
  */
 
 /* Peripheral Cluster #1 */
+static DEFINE_PRCC_CLK(1, msp3,         11, 10, &clk_msp1clk);
 static DEFINE_PRCC_CLK(1, i2c4,         10, 9, &clk_i2cclk);
 static DEFINE_PRCC_CLK(1, gpio0,        9, -1, NULL);
 static DEFINE_PRCC_CLK(1, slimbus0,     8,  8, &clk_slimclk);
@@ -405,7 +406,7 @@ static struct clk_lookup u8500_clks[] = {
         CLK(slimbus0,   "slimbus0",     NULL),
         CLK(i2c2,       "nmk-i2c.2",    NULL),
         CLK(sdi0,       "sdi0",         NULL),
-        CLK(msp0,       "msp0",         NULL),
+        CLK(msp0,       "ux500-msp-i2s.0",      NULL),
         CLK(i2c1,       "nmk-i2c.1",    NULL),
         CLK(uart1,      "uart1",        NULL),
         CLK(uart0,      "uart0",        NULL),
@@ -455,7 +456,8 @@ static struct clk_lookup u8500_clks[] = {
         /* Peripheral Cluster #1 */
         CLK(i2c4,       "nmk-i2c.4",    NULL),
         CLK(spi3,       "spi3",         NULL),
-        CLK(msp1,       "msp1",         NULL),
+        CLK(msp1,       "ux500-msp-i2s.1",      NULL),
+        CLK(msp3,       "ux500-msp-i2s.3",      NULL),
 
         /* Peripheral Cluster #2 */
         CLK(gpio1,      "gpio.6",       NULL),
@@ -465,7 +467,7 @@ static struct clk_lookup u8500_clks[] = {
         CLK(spi0,       "spi0",         NULL),
         CLK(sdi3,       "sdi3",         NULL),
         CLK(sdi1,       "sdi1",         NULL),
-        CLK(msp2,       "msp2",         NULL),
+        CLK(msp2,       "ux500-msp-i2s.2",      NULL),
         CLK(sdi4,       "sdi4",         NULL),
         CLK(pwl,        "pwl",          NULL),
         CLK(spi1,       "spi1",         NULL),
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index d11f3892a27d..f6522f9f129c 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -30,6 +30,18 @@
 
 void __iomem *_PRCMU_BASE;
 
+/*
+ * FIXME: Should we set up the GPIO domain here?
+ *
+ * The problem is that we cannot put the interrupt resources into the platform
+ * device until the irqdomain has been added. Right now, we set the GIC interrupt
+ * domain from init_irq(), then load the gpio driver from
+ * core_initcall(nmk_gpio_init) and add the platform devices from
+ * arch_initcall(customize_machine).
+ *
+ * This feels fragile because it depends on the gpio device getting probed
+ * _before_ any device uses the gpio interrupts.
+*/
 static const struct of_device_id ux500_dt_irq_match[] = {
         { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
         {},
diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h
index 9fd93e9da529..e22b78626068 100644
--- a/arch/arm/mach-ux500/devices-db8500.h
+++ b/arch/arm/mach-ux500/devices-db8500.h
@@ -34,7 +34,6 @@ db8500_add_ssp(struct device *parent, const char *name, resource_size_t base,
         return dbx500_add_amba_device(parent, name, base, irq, pdata, 0);
 }
 
-
 #define db8500_add_i2c0(parent, pdata) \
         dbx500_add_i2c(parent, 0, U8500_I2C0_BASE, IRQ_DB8500_I2C0, pdata)
 #define db8500_add_i2c1(parent, pdata) \
@@ -46,15 +45,6 @@ db8500_add_ssp(struct device *parent, const char *name, resource_size_t base,
 #define db8500_add_i2c4(parent, pdata) \
         dbx500_add_i2c(parent, 4, U8500_I2C4_BASE, IRQ_DB8500_I2C4, pdata)
 
-#define db8500_add_msp0_i2s(parent, pdata) \
-        dbx500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0, pdata)
-#define db8500_add_msp1_i2s(parent, pdata) \
-        dbx500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1, pdata)
-#define db8500_add_msp2_i2s(parent, pdata) \
-        dbx500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2, pdata)
-#define db8500_add_msp3_i2s(parent, pdata) \
-        dbx500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1, pdata)
-
 #define db8500_add_msp0_spi(parent, pdata) \
         dbx500_add_msp_spi(parent, "msp0", U8500_MSP0_BASE, \
                            IRQ_DB8500_MSP0, pdata)
diff --git a/arch/arm/mach-ux500/include/mach/msp.h b/arch/arm/mach-ux500/include/mach/msp.h
new file mode 100644
index 000000000000..798be19129ef
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/msp.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
+ * License terms: GNU General Public License (GPL), version 2.
+ */
+
+#ifndef __MSP_H
+#define __MSP_H
+
+#include <plat/ste_dma40.h>
+
+enum msp_i2s_id {
+        MSP_I2S_0 = 0,
+        MSP_I2S_1,
+        MSP_I2S_2,
+        MSP_I2S_3,
+};
+
+/* Platform data structure for a MSP I2S-device */
+struct msp_i2s_platform_data {
+        enum msp_i2s_id id;
+        struct stedma40_chan_cfg *msp_i2s_dma_rx;
+        struct stedma40_chan_cfg *msp_i2s_dma_tx;
+        int (*msp_i2s_init) (void);
+        int (*msp_i2s_exit) (void);
+};
+
+#endif
diff --git a/arch/arm/mach-ux500/pins-db8500.h b/arch/arm/mach-ux500/pins-db8500.h
index 8b1d1a7a679e..062c7acf4576 100644
--- a/arch/arm/mach-ux500/pins-db8500.h
+++ b/arch/arm/mach-ux500/pins-db8500.h
@@ -35,40 +35,40 @@
 
 #define GPIO4_GPIO              PIN_CFG(4, GPIO)
 #define GPIO4_U1_RXD            PIN_CFG(4, ALT_A)
-#define GPIO4_I2C4_SCL          PIN_CFG_INPUT(4, ALT_B, PULLUP)
+#define GPIO4_I2C4_SCL          PIN_CFG(4, ALT_B)
 #define GPIO4_IP_TRSTn          PIN_CFG(4, ALT_C)
 
 #define GPIO5_GPIO              PIN_CFG(5, GPIO)
 #define GPIO5_U1_TXD            PIN_CFG(5, ALT_A)
-#define GPIO5_I2C4_SDA          PIN_CFG_INPUT(5, ALT_B, PULLUP)
+#define GPIO5_I2C4_SDA          PIN_CFG(5, ALT_B)
 #define GPIO5_IP_GPIO6          PIN_CFG(5, ALT_C)
 
 #define GPIO6_GPIO              PIN_CFG(6, GPIO)
 #define GPIO6_U1_CTSn           PIN_CFG(6, ALT_A)
-#define GPIO6_I2C1_SCL          PIN_CFG_INPUT(6, ALT_B, PULLUP)
+#define GPIO6_I2C1_SCL          PIN_CFG(6, ALT_B)
 #define GPIO6_IP_GPIO0          PIN_CFG(6, ALT_C)
 
 #define GPIO7_GPIO              PIN_CFG(7, GPIO)
 #define GPIO7_U1_RTSn           PIN_CFG(7, ALT_A)
-#define GPIO7_I2C1_SDA          PIN_CFG_INPUT(7, ALT_B, PULLUP)
+#define GPIO7_I2C1_SDA          PIN_CFG(7, ALT_B)
 #define GPIO7_IP_GPIO1          PIN_CFG(7, ALT_C)
 
 #define GPIO8_GPIO              PIN_CFG(8, GPIO)
-#define GPIO8_IPI2C_SDA         PIN_CFG_INPUT(8, ALT_A, PULLUP)
-#define GPIO8_I2C2_SDA          PIN_CFG_INPUT(8, ALT_B, PULLUP)
+#define GPIO8_IPI2C_SDA         PIN_CFG(8, ALT_A)
+#define GPIO8_I2C2_SDA          PIN_CFG(8, ALT_B)
 
 #define GPIO9_GPIO              PIN_CFG(9, GPIO)
-#define GPIO9_IPI2C_SCL         PIN_CFG_INPUT(9, ALT_A, PULLUP)
-#define GPIO9_I2C2_SCL          PIN_CFG_INPUT(9, ALT_B, PULLUP)
+#define GPIO9_IPI2C_SCL         PIN_CFG(9, ALT_A)
+#define GPIO9_I2C2_SCL          PIN_CFG(9, ALT_B)
 
 #define GPIO10_GPIO             PIN_CFG(10, GPIO)
-#define GPIO10_IPI2C_SDA        PIN_CFG_INPUT(10, ALT_A, PULLUP)
-#define GPIO10_I2C2_SDA         PIN_CFG_INPUT(10, ALT_B, PULLUP)
+#define GPIO10_IPI2C_SDA        PIN_CFG(10, ALT_A)
+#define GPIO10_I2C2_SDA         PIN_CFG(10, ALT_B)
 #define GPIO10_IP_GPIO3         PIN_CFG(10, ALT_C)
 
 #define GPIO11_GPIO             PIN_CFG(11, GPIO)
-#define GPIO11_IPI2C_SCL        PIN_CFG_INPUT(11, ALT_A, PULLUP)
-#define GPIO11_I2C2_SCL         PIN_CFG_INPUT(11, ALT_B, PULLUP)
+#define GPIO11_IPI2C_SCL        PIN_CFG(11, ALT_A)
+#define GPIO11_I2C2_SCL         PIN_CFG(11, ALT_B)
 #define GPIO11_IP_GPIO2         PIN_CFG(11, ALT_C)
 
 #define GPIO12_GPIO             PIN_CFG(12, GPIO)
@@ -87,12 +87,12 @@
 
 #define GPIO16_GPIO             PIN_CFG(16, GPIO)
 #define GPIO16_MSP0_RFS         PIN_CFG(16, ALT_A)
-#define GPIO16_I2C1_SCL         PIN_CFG_INPUT(16, ALT_B, PULLUP)
+#define GPIO16_I2C1_SCL         PIN_CFG(16, ALT_B)
 #define GPIO16_SLIM0_DAT        PIN_CFG(16, ALT_C)
 
 #define GPIO17_GPIO             PIN_CFG(17, GPIO)
 #define GPIO17_MSP0_RCK         PIN_CFG(17, ALT_A)
-#define GPIO17_I2C1_SDA         PIN_CFG_INPUT(17, ALT_B, PULLUP)
+#define GPIO17_I2C1_SDA         PIN_CFG(17, ALT_B)
 #define GPIO17_SLIM0_CLK        PIN_CFG(17, ALT_C)
 
 #define GPIO18_GPIO             PIN_CFG(18, GPIO)
@@ -434,10 +434,10 @@
 #define GPIO146_SSP0_TXD        PIN_CFG(146, ALT_A)
 
 #define GPIO147_GPIO            PIN_CFG(147, GPIO)
-#define GPIO147_I2C0_SCL        PIN_CFG_INPUT(147, ALT_A, PULLUP)
+#define GPIO147_I2C0_SCL        PIN_CFG(147, ALT_A)
 
 #define GPIO148_GPIO            PIN_CFG(148, GPIO)
-#define GPIO148_I2C0_SDA        PIN_CFG_INPUT(148, ALT_A, PULLUP)
+#define GPIO148_I2C0_SDA        PIN_CFG(148, ALT_A)
 
 #define GPIO149_GPIO            PIN_CFG(149, GPIO)
 #define GPIO149_IP_GPIO0        PIN_CFG(149, ALT_A)
@@ -459,82 +459,82 @@
 #define GPIO152_KP_O9           PIN_CFG(152, ALT_C)
 
 #define GPIO153_GPIO            PIN_CFG(153, GPIO)
-#define GPIO153_KP_I7           PIN_CFG_INPUT(153, ALT_A, PULLDOWN)
+#define GPIO153_KP_I7           PIN_CFG(153, ALT_A)
 #define GPIO153_LCD_D24         PIN_CFG(153, ALT_B)
 #define GPIO153_U2_RXD          PIN_CFG(153, ALT_C)
 
 #define GPIO154_GPIO            PIN_CFG(154, GPIO)
-#define GPIO154_KP_I6           PIN_CFG_INPUT(154, ALT_A, PULLDOWN)
+#define GPIO154_KP_I6           PIN_CFG(154, ALT_A)
 #define GPIO154_LCD_D25         PIN_CFG(154, ALT_B)
 #define GPIO154_U2_TXD          PIN_CFG(154, ALT_C)
 
 #define GPIO155_GPIO            PIN_CFG(155, GPIO)
-#define GPIO155_KP_I5           PIN_CFG_INPUT(155, ALT_A, PULLDOWN)
+#define GPIO155_KP_I5           PIN_CFG(155, ALT_A)
 #define GPIO155_LCD_D26         PIN_CFG(155, ALT_B)
 #define GPIO155_STMAPE_CLK      PIN_CFG(155, ALT_C)
 
 #define GPIO156_GPIO            PIN_CFG(156, GPIO)
-#define GPIO156_KP_I4           PIN_CFG_INPUT(156, ALT_A, PULLDOWN)
+#define GPIO156_KP_I4           PIN_CFG(156, ALT_A)
 #define GPIO156_LCD_D27         PIN_CFG(156, ALT_B)
 #define GPIO156_STMAPE_DAT3     PIN_CFG(156, ALT_C)
 
 #define GPIO157_GPIO            PIN_CFG(157, GPIO)
-#define GPIO157_KP_O7           PIN_CFG_INPUT(157, ALT_A, PULLUP)
+#define GPIO157_KP_O7           PIN_CFG(157, ALT_A)
 #define GPIO157_LCD_D28         PIN_CFG(157, ALT_B)
 #define GPIO157_STMAPE_DAT2     PIN_CFG(157, ALT_C)
 
 #define GPIO158_GPIO            PIN_CFG(158, GPIO)
-#define GPIO158_KP_O6           PIN_CFG_INPUT(158, ALT_A, PULLUP)
+#define GPIO158_KP_O6           PIN_CFG(158, ALT_A)
 #define GPIO158_LCD_D29         PIN_CFG(158, ALT_B)
 #define GPIO158_STMAPE_DAT1     PIN_CFG(158, ALT_C)
 
 #define GPIO159_GPIO            PIN_CFG(159, GPIO)
-#define GPIO159_KP_O5           PIN_CFG_INPUT(159, ALT_A, PULLUP)
+#define GPIO159_KP_O5           PIN_CFG(159, ALT_A)
 #define GPIO159_LCD_D30         PIN_CFG(159, ALT_B)
 #define GPIO159_STMAPE_DAT0     PIN_CFG(159, ALT_C)
 
 #define GPIO160_GPIO            PIN_CFG(160, GPIO)
-#define GPIO160_KP_O4           PIN_CFG_INPUT(160, ALT_A, PULLUP)
+#define GPIO160_KP_O4           PIN_CFG(160, ALT_A)
 #define GPIO160_LCD_D31         PIN_CFG(160, ALT_B)
 #define GPIO160_NONE            PIN_CFG(160, ALT_C)
 
 #define GPIO161_GPIO            PIN_CFG(161, GPIO)
-#define GPIO161_KP_I3           PIN_CFG_INPUT(161, ALT_A, PULLDOWN)
+#define GPIO161_KP_I3           PIN_CFG(161, ALT_A)
 #define GPIO161_LCD_D32         PIN_CFG(161, ALT_B)
 #define GPIO161_UARTMOD_RXD     PIN_CFG(161, ALT_C)
 
 #define GPIO162_GPIO            PIN_CFG(162, GPIO)
-#define GPIO162_KP_I2           PIN_CFG_INPUT(162, ALT_A, PULLDOWN)
+#define GPIO162_KP_I2           PIN_CFG(162, ALT_A)
 #define GPIO162_LCD_D33         PIN_CFG(162, ALT_B)
 #define GPIO162_UARTMOD_TXD     PIN_CFG(162, ALT_C)
 
 #define GPIO163_GPIO            PIN_CFG(163, GPIO)
-#define GPIO163_KP_I1           PIN_CFG_INPUT(163, ALT_A, PULLDOWN)
+#define GPIO163_KP_I1           PIN_CFG(163, ALT_A)
 #define GPIO163_LCD_D34         PIN_CFG(163, ALT_B)
 #define GPIO163_STMMOD_CLK      PIN_CFG(163, ALT_C)
 
 #define GPIO164_GPIO            PIN_CFG(164, GPIO)
-#define GPIO164_KP_I0           PIN_CFG_INPUT(164, ALT_A, PULLUP)
+#define GPIO164_KP_I0           PIN_CFG(164, ALT_A)
 #define GPIO164_LCD_D35         PIN_CFG(164, ALT_B)
 #define GPIO164_STMMOD_DAT3     PIN_CFG(164, ALT_C)
 
 #define GPIO165_GPIO            PIN_CFG(165, GPIO)
-#define GPIO165_KP_O3           PIN_CFG_INPUT(165, ALT_A, PULLUP)
+#define GPIO165_KP_O3           PIN_CFG(165, ALT_A)
 #define GPIO165_LCD_D36         PIN_CFG(165, ALT_B)
 #define GPIO165_STMMOD_DAT2     PIN_CFG(165, ALT_C)
 
 #define GPIO166_GPIO            PIN_CFG(166, GPIO)
-#define GPIO166_KP_O2           PIN_CFG_INPUT(166, ALT_A, PULLUP)
+#define GPIO166_KP_O2           PIN_CFG(166, ALT_A)
 #define GPIO166_LCD_D37         PIN_CFG(166, ALT_B)
 #define GPIO166_STMMOD_DAT1     PIN_CFG(166, ALT_C)
 
 #define GPIO167_GPIO            PIN_CFG(167, GPIO)
-#define GPIO167_KP_O1           PIN_CFG_INPUT(167, ALT_A, PULLUP)
+#define GPIO167_KP_O1           PIN_CFG(167, ALT_A)
 #define GPIO167_LCD_D38         PIN_CFG(167, ALT_B)
 #define GPIO167_STMMOD_DAT0     PIN_CFG(167, ALT_C)
 
 #define GPIO168_GPIO            PIN_CFG(168, GPIO)
-#define GPIO168_KP_O0           PIN_CFG_INPUT(168, ALT_A, PULLUP)
+#define GPIO168_KP_O0           PIN_CFG(168, ALT_A)
 #define GPIO168_LCD_D39         PIN_CFG(168, ALT_B)
 #define GPIO168_NONE            PIN_CFG(168, ALT_C)
 
@@ -637,7 +637,7 @@
 #define GPIO216_GPIO            PIN_CFG(216, GPIO)
 #define GPIO216_MC1_DAT2DIR     PIN_CFG(216, ALT_A)
 #define GPIO216_MC3_CMDDIR      PIN_CFG(216, ALT_B)
-#define GPIO216_I2C3_SDA        PIN_CFG_INPUT(216, ALT_C, PULLUP)
+#define GPIO216_I2C3_SDA        PIN_CFG(216, ALT_C)
 #define GPIO216_SPI2_FRM        PIN_CFG(216, ALT_C)
 
 #define GPIO217_GPIO            PIN_CFG(217, GPIO)
@@ -649,7 +649,7 @@
 #define GPIO218_GPIO            PIN_CFG(218, GPIO)
 #define GPIO218_MC1_DAT31DIR    PIN_CFG(218, ALT_A)
 #define GPIO218_MC3_DAT0DIR     PIN_CFG(218, ALT_B)
-#define GPIO218_I2C3_SCL        PIN_CFG_INPUT(218, ALT_C, PULLUP)
+#define GPIO218_I2C3_SCL        PIN_CFG(218, ALT_C)
 #define GPIO218_SPI2_RXD        PIN_CFG(218, ALT_C)
 
 #define GPIO219_GPIO            PIN_CFG(219, GPIO)
@@ -698,12 +698,12 @@
 #define GPIO229_GPIO            PIN_CFG(229, GPIO)
 #define GPIO229_CLKOUT1         PIN_CFG(229, ALT_A)
 #define GPIO229_PWL             PIN_CFG(229, ALT_B)
-#define GPIO229_I2C3_SDA        PIN_CFG_INPUT(229, ALT_C, PULLUP)
+#define GPIO229_I2C3_SDA        PIN_CFG(229, ALT_C)
 
 #define GPIO230_GPIO            PIN_CFG(230, GPIO)
 #define GPIO230_CLKOUT2         PIN_CFG(230, ALT_A)
 #define GPIO230_PWL             PIN_CFG(230, ALT_B)
-#define GPIO230_I2C3_SCL        PIN_CFG_INPUT(230, ALT_C, PULLUP)
+#define GPIO230_I2C3_SCL        PIN_CFG(230, ALT_C)
 
 #define GPIO256_GPIO            PIN_CFG(256, GPIO)
 #define GPIO256_USB_NXT         PIN_CFG(256, ALT_A)
diff --git a/arch/arm/mach-ux500/pins.c b/arch/arm/mach-ux500/pins.c
new file mode 100644
index 000000000000..38c1d47b29a1
--- /dev/null
+++ b/arch/arm/mach-ux500/pins.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/device.h>
+#include <linux/mutex.h>
+#include <linux/spinlock.h>
+#include <linux/err.h>
+#include <plat/pincfg.h>
+
+#include "pins.h"
+
+static LIST_HEAD(pin_lookups);
+static DEFINE_MUTEX(pin_lookups_mutex);
+static DEFINE_SPINLOCK(pins_lock);
+
+void __init ux500_pins_add(struct ux500_pin_lookup *pl, size_t num)
+{
+        mutex_lock(&pin_lookups_mutex);
+
+        while (num--) {
+                list_add_tail(&pl->node, &pin_lookups);
+                pl++;
+        }
+
+        mutex_unlock(&pin_lookups_mutex);
+}
+
+struct ux500_pins *ux500_pins_get(const char *name)
+{
+        struct ux500_pins *pins = NULL;
+        struct ux500_pin_lookup *pl;
+
+        mutex_lock(&pin_lookups_mutex);
+
+        list_for_each_entry(pl, &pin_lookups, node) {
+                if (!strcmp(pl->name, name)) {
+                        pins = pl->pins;
+                        goto out;
+                }
+        }
+
+out:
+        mutex_unlock(&pin_lookups_mutex);
+        return pins;
+}
+
+int ux500_pins_enable(struct ux500_pins *pins)
+{
+        unsigned long flags;
+        int ret = 0;
+
+        spin_lock_irqsave(&pins_lock, flags);
+
+        if (pins->usage++ == 0)
+                ret = nmk_config_pins(pins->cfg, pins->num);
+
+        spin_unlock_irqrestore(&pins_lock, flags);
+        return ret;
+}
+
+int ux500_pins_disable(struct ux500_pins *pins)
+{
+        unsigned long flags;
+        int ret = 0;
+
+        spin_lock_irqsave(&pins_lock, flags);
+
+        if (WARN_ON(pins->usage == 0))
+                goto out;
+
+        if (--pins->usage == 0)
+                ret = nmk_config_pins_sleep(pins->cfg, pins->num);
+
+out:
+        spin_unlock_irqrestore(&pins_lock, flags);
+        return ret;
+}
+
+void ux500_pins_put(struct ux500_pins *pins)
+{
+        WARN_ON(!pins);
+}
diff --git a/arch/arm/mach-ux500/pins.h b/arch/arm/mach-ux500/pins.h
new file mode 100644
index 000000000000..0d36af2e7d92
--- /dev/null
+++ b/arch/arm/mach-ux500/pins.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+#ifndef __MACH_UX500_PINS_H
+#define __MACH_UX500_PINS_H
+
+#include <linux/list.h>
+#include <plat/pincfg.h>
+
+#define PIN_LOOKUP(_name, _pins)        \
+{                                       \
+        .name   = _name,                \
+        .pins   = _pins,                \
+}
+
+#define UX500_PINS(name, pins...)                       \
+struct ux500_pins name = {                              \
+        .cfg = (pin_cfg_t[]) {pins},                    \
+        .num = ARRAY_SIZE(((pin_cfg_t[]) {pins})),      \
+}
+
+struct ux500_pins {
+        int usage;
+        int num;
+        pin_cfg_t *cfg;
+};
+
+struct ux500_pin_lookup {
+        struct list_head        node;
+        const char              *name;
+        struct ux500_pins       *pins;
+};
+
+void __init ux500_pins_add(struct ux500_pin_lookup *pl, size_t num);
+void __init ux500_offchip_gpio_init(struct ux500_pins *pins);
+struct ux500_pins *ux500_pins_get(const char *name);
+int ux500_pins_enable(struct ux500_pins *pins);
+int ux500_pins_disable(struct ux500_pins *pins);
+void ux500_pins_put(struct ux500_pins *pins);
+int pins_for_u9500(void);
+
+#endif
diff --git a/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h b/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h
index 9605bf227df9..3e8b7f16fb78 100644
--- a/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h
+++ b/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h
@@ -29,6 +29,7 @@
 #define NMK_GPIO_SLPC   0x1c
 #define NMK_GPIO_AFSLA  0x20
 #define NMK_GPIO_AFSLB  0x24
+#define NMK_GPIO_LOWEMI 0x28
 
 #define NMK_GPIO_RIMSC  0x40
 #define NMK_GPIO_FIMSC  0x44
diff --git a/arch/arm/plat-nomadik/include/plat/pincfg.h b/arch/arm/plat-nomadik/include/plat/pincfg.h
index 22cb97d2d8ad..c015133a7ad3 100644
--- a/arch/arm/plat-nomadik/include/plat/pincfg.h
+++ b/arch/arm/plat-nomadik/include/plat/pincfg.h
@@ -24,6 +24,7 @@
  *      bit 16..18 - SLPM pull up/down state
  *      bit 19..20 - SLPM direction
  *      bit 21..22 - SLPM Value (if output)
+ *      bit 23..25 - PDIS value (if input)
  *
  * to facilitate the definition, the following macros are provided
  *
@@ -67,6 +68,10 @@ typedef unsigned long pin_cfg_t;
 /* These two replace the above in DB8500v2+ */
 #define PIN_SLPM_WAKEUP_ENABLE  (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
 #define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
+#define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE
+
+#define PIN_SLPM_GPIO  PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */
+#define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */
 
 #define PIN_DIR_SHIFT           14
 #define PIN_DIR_MASK            (0x1 << PIN_DIR_SHIFT)
@@ -105,6 +110,20 @@ typedef unsigned long pin_cfg_t;
 #define PIN_SLPM_VAL_LOW        ((1 + 0) << PIN_SLPM_VAL_SHIFT)
 #define PIN_SLPM_VAL_HIGH       ((1 + 1) << PIN_SLPM_VAL_SHIFT)
 
+#define PIN_SLPM_PDIS_SHIFT             23
+#define PIN_SLPM_PDIS_MASK              (0x3 << PIN_SLPM_PDIS_SHIFT)
+#define PIN_SLPM_PDIS(x)        \
+        (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)
+#define PIN_SLPM_PDIS_NO_CHANGE         (0 << PIN_SLPM_PDIS_SHIFT)
+#define PIN_SLPM_PDIS_DISABLED          (1 << PIN_SLPM_PDIS_SHIFT)
+#define PIN_SLPM_PDIS_ENABLED           (2 << PIN_SLPM_PDIS_SHIFT)
+
+#define PIN_LOWEMI_SHIFT        25
+#define PIN_LOWEMI_MASK         (0x1 << PIN_LOWEMI_SHIFT)
+#define PIN_LOWEMI(x)           (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)
+#define PIN_LOWEMI_DISABLED     (0 << PIN_LOWEMI_SHIFT)
+#define PIN_LOWEMI_ENABLED      (1 << PIN_LOWEMI_SHIFT)
+
 /* Shortcuts.  Use these instead of separate DIR, PULL, and VAL.  */
 #define PIN_INPUT_PULLDOWN      (PIN_DIR_INPUT | PIN_PULL_DOWN)
 #define PIN_INPUT_PULLUP        (PIN_DIR_INPUT | PIN_PULL_UP)
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
index 1bb3dbce8810..387655b5ce05 100644
--- a/arch/arm/plat-spear/Kconfig
+++ b/arch/arm/plat-spear/Kconfig
@@ -9,9 +9,11 @@ choice
         default ARCH_SPEAR3XX
 
 config ARCH_SPEAR3XX
-        bool "SPEAr3XX"
+        bool "ST SPEAr3xx with Device Tree"
         select ARM_VIC
         select CPU_ARM926T
+        select USE_OF
+        select PINCTRL
         help
           Supports for ARM's SPEAR3XX family
 
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index e0f2e5b9530c..7744802c83e7 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -3,6 +3,6 @@
 #
 
 # Common support
-obj-y   := clock.o restart.o time.o
+obj-y   := clock.o restart.o time.o pl080.o
 
-obj-$(CONFIG_ARCH_SPEAR3XX)     += shirq.o padmux.o
+obj-$(CONFIG_ARCH_SPEAR3XX)     += shirq.o
diff --git a/arch/arm/plat-spear/include/plat/padmux.h b/arch/arm/plat-spear/include/plat/padmux.h
deleted file mode 100644
index 877f3adcf610..000000000000
--- a/arch/arm/plat-spear/include/plat/padmux.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * arch/arm/plat-spear/include/plat/padmux.h
- *
- * SPEAr platform specific gpio pads muxing file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __PLAT_PADMUX_H
-#define __PLAT_PADMUX_H
-
-#include <linux/types.h>
-
-/*
- * struct pmx_reg: configuration structure for mode reg and mux reg
- *
- * offset: offset of mode reg
- * mask: mask of mode reg
- */
-struct pmx_reg {
-        u32 offset;
-        u32 mask;
-};
-
-/*
- * struct pmx_dev_mode: configuration structure every group of modes of a device
- *
- * ids: all modes for this configuration
- * mask: mask for supported mode
- */
-struct pmx_dev_mode {
-        u32 ids;
-        u32 mask;
-};
-
-/*
- * struct pmx_mode: mode definition structure
- *
- * name: mode name
- * mask: mode mask
- */
-struct pmx_mode {
-        char *name;
-        u32 id;
-        u32 mask;
-};
-
-/*
- * struct pmx_dev: device definition structure
- *
- * name: device name
- * modes: device configuration array for different modes supported
- * mode_count: size of modes array
- * is_active: is peripheral active/enabled
- * enb_on_reset: if 1, mask bits to be cleared in reg otherwise to be set in reg
- */
-struct pmx_dev {
-        char *name;
-        struct pmx_dev_mode *modes;
-        u8 mode_count;
-        bool is_active;
-        bool enb_on_reset;
-};
-
-/*
- * struct pmx_driver: driver definition structure
- *
- * mode: mode to be set
- * devs: array of pointer to pmx devices
- * devs_count: ARRAY_SIZE of devs
- * base: base address of soc config registers
- * mode_reg: structure of mode config register
- * mux_reg: structure of device mux config register
- */
-struct pmx_driver {
-        struct pmx_mode *mode;
-        struct pmx_dev **devs;
-        u8 devs_count;
-        u32 *base;
-        struct pmx_reg mode_reg;
-        struct pmx_reg mux_reg;
-};
-
-/* pmx functions */
-int pmx_register(struct pmx_driver *driver);
-
-#endif /* __PLAT_PADMUX_H */
diff --git a/arch/arm/plat-spear/include/plat/pl080.h b/arch/arm/plat-spear/include/plat/pl080.h
new file mode 100644
index 000000000000..e14a3e4932f9
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/pl080.h
@@ -0,0 +1,21 @@
+/*
+ * arch/arm/plat-spear/include/plat/pl080.h
+ *
+ * DMAC pl080 definitions for SPEAr platform
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_PL080_H
+#define __PLAT_PL080_H
+
+struct pl08x_dma_chan;
+int pl080_get_signal(struct pl08x_dma_chan *ch);
+void pl080_put_signal(struct pl08x_dma_chan *ch);
+
+#endif /* __PLAT_PL080_H */
diff --git a/arch/arm/plat-spear/padmux.c b/arch/arm/plat-spear/padmux.c
deleted file mode 100644
index 555eec6dc1cb..000000000000
--- a/arch/arm/plat-spear/padmux.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * arch/arm/plat-spear/include/plat/padmux.c
- *
- * SPEAr platform specific gpio pads muxing source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <plat/padmux.h>
-
-/*
- * struct pmx: pmx definition structure
- *
- * base: base address of configuration registers
- * mode_reg: mode configurations
- * mux_reg: muxing configurations
- * active_mode: pointer to current active mode
- */
-struct pmx {
-        u32 base;
-        struct pmx_reg mode_reg;
-        struct pmx_reg mux_reg;
-        struct pmx_mode *active_mode;
-};
-
-static struct pmx *pmx;
-
-/**
- * pmx_mode_set - Enables an multiplexing mode
- * @mode - pointer to pmx mode
- *
- * It will set mode of operation in hardware.
- * Returns -ve on Err otherwise 0
- */
-static int pmx_mode_set(struct pmx_mode *mode)
-{
-        u32 val;
-
-        if (!mode->name)
-                return -EFAULT;
-
-        pmx->active_mode = mode;
-
-        val = readl(pmx->base + pmx->mode_reg.offset);
-        val &= ~pmx->mode_reg.mask;
-        val |= mode->mask & pmx->mode_reg.mask;
-        writel(val, pmx->base + pmx->mode_reg.offset);
-
-        return 0;
-}
-
-/**
- * pmx_devs_enable - Enables list of devices
- * @devs - pointer to pmx device array
- * @count - number of devices to enable
- *
- * It will enable pads for all required peripherals once and only once.
- * If peripheral is not supported by current mode then request is rejected.
- * Conflicts between peripherals are not handled and peripherals will be
- * enabled in the order they are present in pmx_dev array.
- * In case of conflicts last peripheral enabled will be present.
- * Returns -ve on Err otherwise 0
- */
-static int pmx_devs_enable(struct pmx_dev **devs, u8 count)
-{
-        u32 val, i, mask;
-
-        if (!count)
-                return -EINVAL;
-
-        val = readl(pmx->base + pmx->mux_reg.offset);
-        for (i = 0; i < count; i++) {
-                u8 j = 0;
-
-                if (!devs[i]->name || !devs[i]->modes) {
-                        printk(KERN_ERR "padmux: dev name or modes is null\n");
-                        continue;
-                }
-                /* check if peripheral exists in active mode */
-                if (pmx->active_mode) {
-                        bool found = false;
-                        for (j = 0; j < devs[i]->mode_count; j++) {
-                                if (devs[i]->modes[j].ids &
-                                                pmx->active_mode->id) {
-                                        found = true;
-                                        break;
-                                }
-                        }
-                        if (found == false) {
-                                printk(KERN_ERR "%s device not available in %s"\
-                                                "mode\n", devs[i]->name,
-                                                pmx->active_mode->name);
-                                continue;
-                        }
-                }
-
-                /* enable peripheral */
-                mask = devs[i]->modes[j].mask & pmx->mux_reg.mask;
-                if (devs[i]->enb_on_reset)
-                        val &= ~mask;
-                else
-                        val |= mask;
-
-                devs[i]->is_active = true;
-        }
-        writel(val, pmx->base + pmx->mux_reg.offset);
-        kfree(pmx);
-
-        /* this will ensure that multiplexing can't be changed now */
-        pmx = (struct pmx *)-1;
-
-        return 0;
-}
-
-/**
- * pmx_register - registers a platform requesting pad mux feature
- * @driver - pointer to driver structure containing driver specific parameters
- *
- * Also this must be called only once. This will allocate memory for pmx
- * structure, will call pmx_mode_set, will call pmx_devs_enable.
- * Returns -ve on Err otherwise 0
- */
-int pmx_register(struct pmx_driver *driver)
-{
-        int ret = 0;
-
-        if (pmx)
-                return -EPERM;
-        if (!driver->base || !driver->devs)
-                return -EFAULT;
-
-        pmx = kzalloc(sizeof(*pmx), GFP_KERNEL);
-        if (!pmx)
-                return -ENOMEM;
-
-        pmx->base = (u32)driver->base;
-        pmx->mode_reg.offset = driver->mode_reg.offset;
-        pmx->mode_reg.mask = driver->mode_reg.mask;
-        pmx->mux_reg.offset = driver->mux_reg.offset;
-        pmx->mux_reg.mask = driver->mux_reg.mask;
-
-        /* choose mode to enable */
-        if (driver->mode) {
-                ret = pmx_mode_set(driver->mode);
-                if (ret)
-                        goto pmx_fail;
-        }
-        ret = pmx_devs_enable(driver->devs, driver->devs_count);
-        if (ret)
-                goto pmx_fail;
-
-        return 0;
-
-pmx_fail:
-        return ret;
-}
diff --git a/arch/arm/plat-spear/pl080.c b/arch/arm/plat-spear/pl080.c
new file mode 100644
index 000000000000..d53d75e1af5e
--- /dev/null
+++ b/arch/arm/plat-spear/pl080.c
@@ -0,0 +1,79 @@
+/*
+ * arch/arm/plat-spear/pl080.c
+ *
+ * DMAC pl080 definitions for SPEAr platform
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/amba/pl08x.h>
+#include <linux/amba/bus.h>
+#include <linux/bug.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/spinlock_types.h>
+#include <mach/misc_regs.h>
+
+static spinlock_t lock = __SPIN_LOCK_UNLOCKED(x);
+
+struct {
+        unsigned char busy;
+        unsigned char val;
+} signals[16] = {{0, 0}, };
+
+int pl080_get_signal(struct pl08x_dma_chan *ch)
+{
+        const struct pl08x_channel_data *cd = ch->cd;
+        unsigned int signal = cd->min_signal, val;
+        unsigned long flags;
+
+        spin_lock_irqsave(&lock, flags);
+
+        /* Return if signal is already acquired by somebody else */
+        if (signals[signal].busy &&
+                        (signals[signal].val != cd->muxval)) {
+                spin_unlock_irqrestore(&lock, flags);
+                return -EBUSY;
+        }
+
+        /* If acquiring for the first time, configure it */
+        if (!signals[signal].busy) {
+                val = readl(DMA_CHN_CFG);
+
+                /*
+                 * Each request line has two bits in DMA_CHN_CFG register. To
+                 * goto the bits of current request line, do left shift of
+                 * value by 2 * signal number.
+                 */
+                val &= ~(0x3 << (signal * 2));
+                val |= cd->muxval << (signal * 2);
+                writel(val, DMA_CHN_CFG);
+        }
+
+        signals[signal].busy++;
+        signals[signal].val = cd->muxval;
+        spin_unlock_irqrestore(&lock, flags);
+
+        return signal;
+}
+
+void pl080_put_signal(struct pl08x_dma_chan *ch)
+{
+        const struct pl08x_channel_data *cd = ch->cd;
+        unsigned long flags;
+
+        spin_lock_irqsave(&lock, flags);
+
+        /* if signal is not used */
+        if (!signals[cd->min_signal].busy)
+                BUG();
+
+        signals[cd->min_signal].busy--;
+
+        spin_unlock_irqrestore(&lock, flags);
+}
diff --git a/drivers/gpio/gpio-nomadik.c b/drivers/gpio/gpio-nomadik.c
index 839624f9fe6a..9b126b6d79cc 100644
--- a/drivers/gpio/gpio-nomadik.c
+++ b/drivers/gpio/gpio-nomadik.c
@@ -22,14 +22,13 @@
 #include <linux/spinlock.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
 #include <linux/slab.h>
 
 #include <asm/mach/irq.h>
 
 #include <plat/pincfg.h>
 #include <plat/gpio-nomadik.h>
-#include <mach/hardware.h>
-#include <asm/gpio.h>
 
 /*
  * The GPIO module in the Nomadik family of Systems-on-Chip is an
@@ -43,6 +42,7 @@
 
 struct nmk_gpio_chip {
         struct gpio_chip chip;
+        struct irq_domain *domain;
         void __iomem *addr;
         struct clk *clk;
         unsigned int bank;
@@ -58,8 +58,10 @@ struct nmk_gpio_chip {
         u32 real_wake;
         u32 rwimsc;
         u32 fwimsc;
-        u32 slpm;
+        u32 rimsc;
+        u32 fimsc;
         u32 pull_up;
+        u32 lowemi;
 };
 
 static struct nmk_gpio_chip *
@@ -124,6 +126,24 @@ static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
         }
 }
 
+static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
+                                  unsigned offset, bool lowemi)
+{
+        u32 bit = BIT(offset);
+        bool enabled = nmk_chip->lowemi & bit;
+
+        if (lowemi == enabled)
+                return;
+
+        if (lowemi)
+                nmk_chip->lowemi |= bit;
+        else
+                nmk_chip->lowemi &= ~bit;
+
+        writel_relaxed(nmk_chip->lowemi,
+                       nmk_chip->addr + NMK_GPIO_LOWEMI);
+}
+
 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
                                   unsigned offset)
 {
@@ -150,8 +170,8 @@ static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
                                      unsigned offset, int gpio_mode,
                                      bool glitch)
 {
-        u32 rwimsc = readl(nmk_chip->addr + NMK_GPIO_RWIMSC);
-        u32 fwimsc = readl(nmk_chip->addr + NMK_GPIO_FWIMSC);
+        u32 rwimsc = nmk_chip->rwimsc;
+        u32 fwimsc = nmk_chip->fwimsc;
 
         if (glitch && nmk_chip->set_ioforce) {
                 u32 bit = BIT(offset);
@@ -173,6 +193,36 @@ static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
         }
 }
 
+static void
+nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
+{
+        u32 falling = nmk_chip->fimsc & BIT(offset);
+        u32 rising = nmk_chip->rimsc & BIT(offset);
+        int gpio = nmk_chip->chip.base + offset;
+        int irq = NOMADIK_GPIO_TO_IRQ(gpio);
+        struct irq_data *d = irq_get_irq_data(irq);
+
+        if (!rising && !falling)
+                return;
+
+        if (!d || !irqd_irq_disabled(d))
+                return;
+
+        if (rising) {
+                nmk_chip->rimsc &= ~BIT(offset);
+                writel_relaxed(nmk_chip->rimsc,
+                               nmk_chip->addr + NMK_GPIO_RIMSC);
+        }
+
+        if (falling) {
+                nmk_chip->fimsc &= ~BIT(offset);
+                writel_relaxed(nmk_chip->fimsc,
+                               nmk_chip->addr + NMK_GPIO_FIMSC);
+        }
+
+        dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio);
+}
+
 static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
                              pin_cfg_t cfg, bool sleep, unsigned int *slpmregs)
 {
@@ -238,6 +288,17 @@ static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
                 __nmk_gpio_set_pull(nmk_chip, offset, pull);
         }
 
+        __nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg));
+
+        /*
+         * If the pin is switching to altfunc, and there was an interrupt
+         * installed on it which has been lazy disabled, actually mask the
+         * interrupt to prevent spurious interrupts that would occur while the
+         * pin is under control of the peripheral.  Only SKE does this.
+         */
+        if (af != NMK_GPIO_ALT_GPIO)
+                nmk_gpio_disable_lazy_irq(nmk_chip, offset);
+
         /*
          * If we've backed up the SLPM registers (glitch workaround), modify
          * the backups since they will be restored.
@@ -334,7 +395,7 @@ static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
                 struct nmk_gpio_chip *nmk_chip;
                 int pin = PIN_NUM(cfgs[i]);
 
-                nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(pin));
+                nmk_chip = nmk_gpio_chips[pin / NMK_GPIO_PER_CHIP];
                 if (!nmk_chip) {
                         ret = -EINVAL;
                         break;
@@ -342,7 +403,7 @@ static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
 
                 clk_enable(nmk_chip->clk);
                 spin_lock(&nmk_chip->lock);
-                __nmk_config_pin(nmk_chip, pin - nmk_chip->chip.base,
+                __nmk_config_pin(nmk_chip, pin % NMK_GPIO_PER_CHIP,
                                  cfgs[i], sleep, glitch ? slpm : NULL);
                 spin_unlock(&nmk_chip->lock);
                 clk_disable(nmk_chip->clk);
@@ -426,7 +487,7 @@ int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
         struct nmk_gpio_chip *nmk_chip;
         unsigned long flags;
 
-        nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
+        nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
         if (!nmk_chip)
                 return -EINVAL;
 
@@ -434,7 +495,7 @@ int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
         spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
         spin_lock(&nmk_chip->lock);
 
-        __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode);
+        __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, mode);
 
         spin_unlock(&nmk_chip->lock);
         spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
@@ -461,13 +522,13 @@ int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
         struct nmk_gpio_chip *nmk_chip;
         unsigned long flags;
 
-        nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
+        nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
         if (!nmk_chip)
                 return -EINVAL;
 
         clk_enable(nmk_chip->clk);
         spin_lock_irqsave(&nmk_chip->lock, flags);
-        __nmk_gpio_set_pull(nmk_chip, gpio - nmk_chip->chip.base, pull);
+        __nmk_gpio_set_pull(nmk_chip, gpio % NMK_GPIO_PER_CHIP, pull);
         spin_unlock_irqrestore(&nmk_chip->lock, flags);
         clk_disable(nmk_chip->clk);
 
@@ -489,13 +550,13 @@ int nmk_gpio_set_mode(int gpio, int gpio_mode)
         struct nmk_gpio_chip *nmk_chip;
         unsigned long flags;
 
-        nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
+        nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
         if (!nmk_chip)
                 return -EINVAL;
 
         clk_enable(nmk_chip->clk);
         spin_lock_irqsave(&nmk_chip->lock, flags);
-        __nmk_gpio_set_mode(nmk_chip, gpio - nmk_chip->chip.base, gpio_mode);
+        __nmk_gpio_set_mode(nmk_chip, gpio % NMK_GPIO_PER_CHIP, gpio_mode);
         spin_unlock_irqrestore(&nmk_chip->lock, flags);
         clk_disable(nmk_chip->clk);
 
@@ -508,11 +569,11 @@ int nmk_gpio_get_mode(int gpio)
         struct nmk_gpio_chip *nmk_chip;
         u32 afunc, bfunc, bit;
 
-        nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
+        nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
         if (!nmk_chip)
                 return -EINVAL;
 
-        bit = 1 << (gpio - nmk_chip->chip.base);
+        bit = 1 << (gpio % NMK_GPIO_PER_CHIP);
 
         clk_enable(nmk_chip->clk);
 
@@ -529,21 +590,19 @@ EXPORT_SYMBOL(nmk_gpio_get_mode);
 /* IRQ functions */
 static inline int nmk_gpio_get_bitmask(int gpio)
 {
-        return 1 << (gpio % 32);
+        return 1 << (gpio % NMK_GPIO_PER_CHIP);
 }
 
 static void nmk_gpio_irq_ack(struct irq_data *d)
 {
-        int gpio;
         struct nmk_gpio_chip *nmk_chip;
 
-        gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
         nmk_chip = irq_data_get_irq_chip_data(d);
         if (!nmk_chip)
                 return;
 
         clk_enable(nmk_chip->clk);
-        writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC);
+        writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
         clk_disable(nmk_chip->clk);
 }
 
@@ -556,37 +615,52 @@ static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
                                   int gpio, enum nmk_gpio_irq_type which,
                                   bool enable)
 {
-        u32 rimsc = which == WAKE ? NMK_GPIO_RWIMSC : NMK_GPIO_RIMSC;
-        u32 fimsc = which == WAKE ? NMK_GPIO_FWIMSC : NMK_GPIO_FIMSC;
         u32 bitmask = nmk_gpio_get_bitmask(gpio);
-        u32 reg;
+        u32 *rimscval;
+        u32 *fimscval;
+        u32 rimscreg;
+        u32 fimscreg;
+
+        if (which == NORMAL) {
+                rimscreg = NMK_GPIO_RIMSC;
+                fimscreg = NMK_GPIO_FIMSC;
+                rimscval = &nmk_chip->rimsc;
+                fimscval = &nmk_chip->fimsc;
+        } else  {
+                rimscreg = NMK_GPIO_RWIMSC;
+                fimscreg = NMK_GPIO_FWIMSC;
+                rimscval = &nmk_chip->rwimsc;
+                fimscval = &nmk_chip->fwimsc;
+        }
 
         /* we must individually set/clear the two edges */
         if (nmk_chip->edge_rising & bitmask) {
-                reg = readl(nmk_chip->addr + rimsc);
                 if (enable)
-                        reg |= bitmask;
+                        *rimscval |= bitmask;
                 else
-                        reg &= ~bitmask;
-                writel(reg, nmk_chip->addr + rimsc);
+                        *rimscval &= ~bitmask;
+                writel(*rimscval, nmk_chip->addr + rimscreg);
         }
         if (nmk_chip->edge_falling & bitmask) {
-                reg = readl(nmk_chip->addr + fimsc);
                 if (enable)
-                        reg |= bitmask;
+                        *fimscval |= bitmask;
                 else
-                        reg &= ~bitmask;
-                writel(reg, nmk_chip->addr + fimsc);
+                        *fimscval &= ~bitmask;
+                writel(*fimscval, nmk_chip->addr + fimscreg);
         }
 }
 
 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
                                 int gpio, bool on)
 {
-        if (nmk_chip->sleepmode) {
-                __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base,
-                                    on ? NMK_GPIO_SLPM_WAKEUP_ENABLE
-                                    : NMK_GPIO_SLPM_WAKEUP_DISABLE);
+        /*
+         * Ensure WAKEUP_ENABLE is on.  No need to disable it if wakeup is
+         * disabled, since setting SLPM to 1 increases power consumption, and
+         * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
+         */
+        if (nmk_chip->sleepmode && on) {
+                __nmk_gpio_set_slpm(nmk_chip, gpio % nmk_chip->chip.base,
+                                    NMK_GPIO_SLPM_WAKEUP_ENABLE);
         }
 
         __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
@@ -594,14 +668,12 @@ static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
 
 static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
 {
-        int gpio;
         struct nmk_gpio_chip *nmk_chip;
         unsigned long flags;
         u32 bitmask;
 
-        gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
         nmk_chip = irq_data_get_irq_chip_data(d);
-        bitmask = nmk_gpio_get_bitmask(gpio);
+        bitmask = nmk_gpio_get_bitmask(d->hwirq);
         if (!nmk_chip)
                 return -EINVAL;
 
@@ -609,10 +681,10 @@ static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
         spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
         spin_lock(&nmk_chip->lock);
 
-        __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, enable);
+        __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
 
         if (!(nmk_chip->real_wake & bitmask))
-                __nmk_gpio_set_wake(nmk_chip, gpio, enable);
+                __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
 
         spin_unlock(&nmk_chip->lock);
         spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
@@ -636,20 +708,18 @@ static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
         struct nmk_gpio_chip *nmk_chip;
         unsigned long flags;
         u32 bitmask;
-        int gpio;
 
-        gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
         nmk_chip = irq_data_get_irq_chip_data(d);
         if (!nmk_chip)
                 return -EINVAL;
-        bitmask = nmk_gpio_get_bitmask(gpio);
+        bitmask = nmk_gpio_get_bitmask(d->hwirq);
 
         clk_enable(nmk_chip->clk);
         spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
         spin_lock(&nmk_chip->lock);
 
         if (irqd_irq_disabled(d))
-                __nmk_gpio_set_wake(nmk_chip, gpio, on);
+                __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
 
         if (on)
                 nmk_chip->real_wake |= bitmask;
@@ -667,17 +737,14 @@ static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 {
         bool enabled = !irqd_irq_disabled(d);
         bool wake = irqd_is_wakeup_set(d);
-        int gpio;
         struct nmk_gpio_chip *nmk_chip;
         unsigned long flags;
         u32 bitmask;
 
-        gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
         nmk_chip = irq_data_get_irq_chip_data(d);
-        bitmask = nmk_gpio_get_bitmask(gpio);
+        bitmask = nmk_gpio_get_bitmask(d->hwirq);
         if (!nmk_chip)
                 return -EINVAL;
-
         if (type & IRQ_TYPE_LEVEL_HIGH)
                 return -EINVAL;
         if (type & IRQ_TYPE_LEVEL_LOW)
@@ -687,10 +754,10 @@ static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
         spin_lock_irqsave(&nmk_chip->lock, flags);
 
         if (enabled)
-                __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false);
+                __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
 
         if (enabled || wake)
-                __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false);
+                __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
 
         nmk_chip->edge_rising &= ~bitmask;
         if (type & IRQ_TYPE_EDGE_RISING)
@@ -701,10 +768,10 @@ static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
                 nmk_chip->edge_falling |= bitmask;
 
         if (enabled)
-                __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true);
+                __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
 
         if (enabled || wake)
-                __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true);
+                __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
 
         spin_unlock_irqrestore(&nmk_chip->lock, flags);
         clk_disable(nmk_chip->clk);
@@ -750,7 +817,7 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
         chained_irq_enter(host_chip, desc);
 
         nmk_chip = irq_get_handler_data(irq);
-        first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
+        first_irq = nmk_chip->domain->revmap_data.legacy.first_irq;
         while (status) {
                 int bit = __ffs(status);
 
@@ -784,18 +851,6 @@ static void nmk_gpio_secondary_irq_handler(unsigned int irq,
 
 static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
 {
-        unsigned int first_irq;
-        int i;
-
-        first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
-        for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) {
-                irq_set_chip_and_handler(i, &nmk_gpio_irq_chip,
-                                         handle_edge_irq);
-                set_irq_flags(i, IRQF_VALID);
-                irq_set_chip_data(i, nmk_chip);
-                irq_set_irq_type(i, IRQ_TYPE_EDGE_FALLING);
-        }
-
         irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
         irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
 
@@ -872,7 +927,7 @@ static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
         struct nmk_gpio_chip *nmk_chip =
                 container_of(chip, struct nmk_gpio_chip, chip);
 
-        return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset;
+        return irq_find_mapping(nmk_chip->domain, offset);
 }
 
 #ifdef CONFIG_DEBUG_FS
@@ -1008,21 +1063,11 @@ void nmk_gpio_wakeups_suspend(void)
 
                 clk_enable(chip->clk);
 
-                chip->rwimsc = readl(chip->addr + NMK_GPIO_RWIMSC);
-                chip->fwimsc = readl(chip->addr + NMK_GPIO_FWIMSC);
-
                 writel(chip->rwimsc & chip->real_wake,
                        chip->addr + NMK_GPIO_RWIMSC);
                 writel(chip->fwimsc & chip->real_wake,
                        chip->addr + NMK_GPIO_FWIMSC);
 
-                if (chip->sleepmode) {
-                        chip->slpm = readl(chip->addr + NMK_GPIO_SLPC);
-
-                        /* 0 -> wakeup enable */
-                        writel(~chip->real_wake, chip->addr + NMK_GPIO_SLPC);
-                }
-
                 clk_disable(chip->clk);
         }
 }
@@ -1042,9 +1087,6 @@ void nmk_gpio_wakeups_resume(void)
                 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
                 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
 
-                if (chip->sleepmode)
-                        writel(chip->slpm, chip->addr + NMK_GPIO_SLPC);
-
                 clk_disable(chip->clk);
         }
 }
@@ -1068,19 +1110,62 @@ void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
         }
 }
 
+int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq,
+                          irq_hw_number_t hwirq)
+{
+        struct nmk_gpio_chip *nmk_chip = d->host_data;
+
+        if (!nmk_chip)
+                return -EINVAL;
+
+        irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq);
+        set_irq_flags(irq, IRQF_VALID);
+        irq_set_chip_data(irq, nmk_chip);
+        irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING);
+
+        return 0;
+}
+
+const struct irq_domain_ops nmk_gpio_irq_simple_ops = {
+        .map = nmk_gpio_irq_map,
+        .xlate = irq_domain_xlate_twocell,
+};
+
 static int __devinit nmk_gpio_probe(struct platform_device *dev)
 {
         struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
+        struct device_node *np = dev->dev.of_node;
         struct nmk_gpio_chip *nmk_chip;
         struct gpio_chip *chip;
         struct resource *res;
         struct clk *clk;
         int secondary_irq;
+        void __iomem *base;
         int irq;
         int ret;
 
-        if (!pdata)
+        if (!pdata && !np) {
+                dev_err(&dev->dev, "No platform data or device tree found\n");
                 return -ENODEV;
+        }
+
+        if (np) {
+                pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
+                if (!pdata)
+                        return -ENOMEM;
+
+                if (of_get_property(np, "supports-sleepmode", NULL))
+                        pdata->supports_sleepmode = true;
+
+                if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
+                        dev_err(&dev->dev, "gpio-bank property not found\n");
+                        ret = -EINVAL;
+                        goto out;
+                }
+
+                pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP;
+                pdata->num_gpio   = NMK_GPIO_PER_CHIP;
+        }
 
         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
         if (!res) {
@@ -1106,10 +1191,16 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
                 goto out;
         }
 
+        base = ioremap(res->start, resource_size(res));
+        if (!base) {
+                ret = -ENOMEM;
+                goto out_release;
+        }
+
         clk = clk_get(&dev->dev, NULL);
         if (IS_ERR(clk)) {
                 ret = PTR_ERR(clk);
-                goto out_release;
+                goto out_unmap;
         }
 
         nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL);
@@ -1117,13 +1208,14 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
                 ret = -ENOMEM;
                 goto out_clk;
         }
+
         /*
          * The virt address in nmk_chip->addr is in the nomadik register space,
          * so we can simply convert the resource address, without remapping
          */
         nmk_chip->bank = dev->id;
         nmk_chip->clk = clk;
-        nmk_chip->addr = io_p2v(res->start);
+        nmk_chip->addr = base;
         nmk_chip->chip = nmk_gpio_template;
         nmk_chip->parent_irq = irq;
         nmk_chip->secondary_parent_irq = secondary_irq;
@@ -1139,6 +1231,12 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
         chip->dev = &dev->dev;
         chip->owner = THIS_MODULE;
 
+        clk_enable(nmk_chip->clk);
+        nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
+        clk_disable(nmk_chip->clk);
+
+        chip->of_node = np;
+
         ret = gpiochip_add(&nmk_chip->chip);
         if (ret)
                 goto out_free;
@@ -1146,12 +1244,22 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
         BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
 
         nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
+
         platform_set_drvdata(dev, nmk_chip);
 
+        nmk_chip->domain = irq_domain_add_legacy(np, NMK_GPIO_PER_CHIP,
+                                                NOMADIK_GPIO_TO_IRQ(pdata->first_gpio),
+                                                0, &nmk_gpio_irq_simple_ops, nmk_chip);
+        if (!nmk_chip->domain) {
+                pr_err("%s: Failed to create irqdomain\n", np->full_name);
+                ret = -ENOSYS;
+                goto out_free;
+        }
+
         nmk_gpio_init_irq(nmk_chip);
 
-        dev_info(&dev->dev, "at address %p\n",
-                 nmk_chip->addr);
+        dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);
+
         return 0;
 
 out_free:
@@ -1159,18 +1267,29 @@ out_free:
 out_clk:
         clk_disable(clk);
         clk_put(clk);
+out_unmap:
+        iounmap(base);
 out_release:
         release_mem_region(res->start, resource_size(res));
 out:
         dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret,
                   pdata->first_gpio, pdata->first_gpio+31);
+        if (np)
+                kfree(pdata);
+
         return ret;
 }
 
+static const struct of_device_id nmk_gpio_match[] = {
+        { .compatible = "st,nomadik-gpio", },
+        {}
+};
+
 static struct platform_driver nmk_gpio_driver = {
         .driver = {
                 .owner = THIS_MODULE,
                 .name = "gpio",
+                .of_match_table = nmk_gpio_match,
         },
         .probe = nmk_gpio_probe,
 };
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index 12f349b3830d..dc5184d57892 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -26,10 +26,10 @@
 #include <linux/platform_device.h>
 #include <linux/module.h>
 #include <linux/irqdomain.h>
+#include <linux/pinctrl/consumer.h>
 
 #include <asm/mach/irq.h>
 
-#include <mach/gpio-tegra.h>
 #include <mach/iomap.h>
 #include <mach/suspend.h>
 
@@ -108,18 +108,29 @@ static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
         tegra_gpio_writel(val, reg);
 }
 
-void tegra_gpio_enable(int gpio)
+static void tegra_gpio_enable(int gpio)
 {
         tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
 }
 EXPORT_SYMBOL_GPL(tegra_gpio_enable);
 
-void tegra_gpio_disable(int gpio)
+static void tegra_gpio_disable(int gpio)
 {
         tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
 }
 EXPORT_SYMBOL_GPL(tegra_gpio_disable);
 
+int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+        return pinctrl_request_gpio(offset);
+}
+
+void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+        pinctrl_free_gpio(offset);
+        tegra_gpio_disable(offset);
+}
+
 static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 {
         tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
@@ -133,6 +144,7 @@ static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
 static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 {
         tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
+        tegra_gpio_enable(offset);
         return 0;
 }
 
@@ -141,6 +153,7 @@ static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
 {
         tegra_gpio_set(chip, offset, value);
         tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
+        tegra_gpio_enable(offset);
         return 0;
 }
 
@@ -151,13 +164,14 @@ static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 
 static struct gpio_chip tegra_gpio_chip = {
         .label                  = "tegra-gpio",
+        .request                = tegra_gpio_request,
+        .free                   = tegra_gpio_free,
         .direction_input        = tegra_gpio_direction_input,
         .get                    = tegra_gpio_get,
         .direction_output       = tegra_gpio_direction_output,
         .set                    = tegra_gpio_set,
         .to_irq                 = tegra_gpio_to_irq,
         .base                   = 0,
-        .ngpio                  = TEGRA_NR_GPIOS,
 };
 
 static void tegra_gpio_irq_ack(struct irq_data *d)
@@ -224,6 +238,9 @@ static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 
         spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
 
+        tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0);
+        tegra_gpio_enable(gpio);
+
         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
                 __irq_set_handler_locked(d->irq, handle_level_irq);
         else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
@@ -490,20 +507,6 @@ static int __init tegra_gpio_init(void)
 }
 postcore_initcall(tegra_gpio_init);
 
-void tegra_gpio_config(struct tegra_gpio_table *table, int num)
-{
-        int i;
-
-        for (i = 0; i < num; i++) {
-                int gpio = table[i].gpio;
-
-                if (table[i].enable)
-                        tegra_gpio_enable(gpio);
-                else
-                        tegra_gpio_disable(gpio);
-        }
-}
-
 #ifdef  CONFIG_DEBUG_FS
 
 #include <linux/debugfs.h>
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 53b26502f6e2..ff5a16991939 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -269,7 +269,6 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
                                 "failed to allocate power gpio\n");
                         goto err_power_req;
                 }
-                tegra_gpio_enable(plat->power_gpio);
                 gpio_direction_output(plat->power_gpio, 1);
         }
 
@@ -280,7 +279,6 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
                                 "failed to allocate cd gpio\n");
                         goto err_cd_req;
                 }
-                tegra_gpio_enable(plat->cd_gpio);
                 gpio_direction_input(plat->cd_gpio);
 
                 rc = request_irq(gpio_to_irq(plat->cd_gpio), carddetect_irq,
@@ -301,7 +299,6 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
                                 "failed to allocate wp gpio\n");
                         goto err_wp_req;
                 }
-                tegra_gpio_enable(plat->wp_gpio);
                 gpio_direction_input(plat->wp_gpio);
         }
 
@@ -329,23 +326,17 @@ err_add_host:
         clk_disable(pltfm_host->clk);
         clk_put(pltfm_host->clk);
 err_clk_get:
-        if (gpio_is_valid(plat->wp_gpio)) {
-                tegra_gpio_disable(plat->wp_gpio);
+        if (gpio_is_valid(plat->wp_gpio))
                 gpio_free(plat->wp_gpio);
-        }
 err_wp_req:
         if (gpio_is_valid(plat->cd_gpio))
                 free_irq(gpio_to_irq(plat->cd_gpio), host);
 err_cd_irq_req:
-        if (gpio_is_valid(plat->cd_gpio)) {
-                tegra_gpio_disable(plat->cd_gpio);
+        if (gpio_is_valid(plat->cd_gpio))
                 gpio_free(plat->cd_gpio);
-        }
 err_cd_req:
-        if (gpio_is_valid(plat->power_gpio)) {
-                tegra_gpio_disable(plat->power_gpio);
+        if (gpio_is_valid(plat->power_gpio))
                 gpio_free(plat->power_gpio);
-        }
 err_power_req:
 err_no_plat:
         sdhci_pltfm_free(pdev);
@@ -362,21 +353,16 @@ static int __devexit sdhci_tegra_remove(struct platform_device *pdev)
 
         sdhci_remove_host(host, dead);
 
-        if (gpio_is_valid(plat->wp_gpio)) {
-                tegra_gpio_disable(plat->wp_gpio);
+        if (gpio_is_valid(plat->wp_gpio))
                 gpio_free(plat->wp_gpio);
-        }
 
         if (gpio_is_valid(plat->cd_gpio)) {
                 free_irq(gpio_to_irq(plat->cd_gpio), host);
-                tegra_gpio_disable(plat->cd_gpio);
                 gpio_free(plat->cd_gpio);
         }
 
-        if (gpio_is_valid(plat->power_gpio)) {
-                tegra_gpio_disable(plat->power_gpio);
+        if (gpio_is_valid(plat->power_gpio))
                 gpio_free(plat->power_gpio);
-        }
 
         clk_disable(pltfm_host->clk);
         clk_put(pltfm_host->clk);
diff --git a/drivers/of/base.c b/drivers/of/base.c
index 580644986945..d9bfd49b1935 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -1260,3 +1260,44 @@ int of_alias_get_id(struct device_node *np, const char *stem)
         return id;
 }
 EXPORT_SYMBOL_GPL(of_alias_get_id);
+
+const __be32 *of_prop_next_u32(struct property *prop, const __be32 *cur,
+                               u32 *pu)
+{
+        const void *curv = cur;
+
+        if (!prop)
+                return NULL;
+
+        if (!cur) {
+                curv = prop->value;
+                goto out_val;
+        }
+
+        curv += sizeof(*cur);
+        if (curv >= prop->value + prop->length)
+                return NULL;
+
+out_val:
+        *pu = be32_to_cpup(curv);
+        return curv;
+}
+EXPORT_SYMBOL_GPL(of_prop_next_u32);
+
+const char *of_prop_next_string(struct property *prop, const char *cur)
+{
+        const void *curv = cur;
+
+        if (!prop)
+                return NULL;
+
+        if (!cur)
+                return prop->value;
+
+        curv += strlen(cur) + 1;
+        if (curv >= prop->value + prop->length)
+                return NULL;
+
+        return curv;
+}
+EXPORT_SYMBOL_GPL(of_prop_next_string);
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index abfb96408779..de6e68459605 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -4,7 +4,6 @@
 
 config PINCTRL
         bool
-        depends on EXPERIMENTAL
 
 if PINCTRL
 
@@ -84,6 +83,8 @@ config PINCTRL_COH901
           COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
           ports of 8 GPIO pins each.
 
+source "drivers/pinctrl/spear/Kconfig"
+
 endmenu
 
 endif
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 6d4150b4eced..03c97e2052bb 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -5,6 +5,9 @@ ccflags-$(CONFIG_DEBUG_PINCTRL)	+= -DDEBUG
 obj-$(CONFIG_PINCTRL)           += core.o
 obj-$(CONFIG_PINMUX)            += pinmux.o
 obj-$(CONFIG_PINCONF)           += pinconf.o
+ifeq ($(CONFIG_OF),y)
+obj-$(CONFIG_PINCTRL)           += devicetree.o
+endif
 obj-$(CONFIG_GENERIC_PINCONF)   += pinconf-generic.o
 obj-$(CONFIG_PINCTRL_PXA3xx)    += pinctrl-pxa3xx.o
 obj-$(CONFIG_PINCTRL_MMP2)      += pinctrl-mmp2.o
@@ -16,3 +19,5 @@ obj-$(CONFIG_PINCTRL_TEGRA20)	+= pinctrl-tegra20.o
 obj-$(CONFIG_PINCTRL_TEGRA30)   += pinctrl-tegra30.o
 obj-$(CONFIG_PINCTRL_U300)      += pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_COH901)    += pinctrl-coh901.o
+
+obj-$(CONFIG_PLAT_SPEAR)        += spear/
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index df6296c5f47b..5cd5a5a3a403 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -23,9 +23,11 @@
 #include <linux/sysfs.h>
 #include <linux/debugfs.h>
 #include <linux/seq_file.h>
+#include <linux/pinctrl/consumer.h>
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/machine.h>
 #include "core.h"
+#include "devicetree.h"
 #include "pinmux.h"
 #include "pinconf.h"
 
@@ -45,7 +47,7 @@ struct pinctrl_maps {
 DEFINE_MUTEX(pinctrl_mutex);
 
 /* Global list of pin control devices (struct pinctrl_dev) */
-static LIST_HEAD(pinctrldev_list);
+LIST_HEAD(pinctrldev_list);
 
 /* List of pin controller handles (struct pinctrl) */
 static LIST_HEAD(pinctrl_list);
@@ -124,6 +126,25 @@ int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name)
 }
 
 /**
+ * pin_get_name_from_id() - look up a pin name from a pin id
+ * @pctldev: the pin control device to lookup the pin on
+ * @name: the name of the pin to look up
+ */
+const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin)
+{
+        const struct pin_desc *desc;
+
+        desc = pin_desc_get(pctldev, pin);
+        if (desc == NULL) {
+                dev_err(pctldev->dev, "failed to get pin(%d) name\n",
+                        pin);
+                return NULL;
+        }
+
+        return desc->name;
+}
+
+/**
  * pin_is_valid() - check if pin exists on controller
  * @pctldev: the pin control device to check the pin on
  * @pin: pin to check, use the local pin controller index number
@@ -318,9 +339,10 @@ int pinctrl_get_group_selector(struct pinctrl_dev *pctldev,
                                const char *pin_group)
 {
         const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
+        unsigned ngroups = pctlops->get_groups_count(pctldev);
         unsigned group_selector = 0;
 
-        while (pctlops->list_groups(pctldev, group_selector) >= 0) {
+        while (group_selector < ngroups) {
                 const char *gname = pctlops->get_group_name(pctldev,
                                                             group_selector);
                 if (!strcmp(gname, pin_group)) {
@@ -516,11 +538,14 @@ static int add_setting(struct pinctrl *p, struct pinctrl_map const *map)
 
         setting->pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name);
         if (setting->pctldev == NULL) {
-                dev_err(p->dev, "unknown pinctrl device %s in map entry",
+                dev_info(p->dev, "unknown pinctrl device %s in map entry, deferring probe",
                         map->ctrl_dev_name);
                 kfree(setting);
-                /* Eventually, this should trigger deferred probe */
-                return -ENODEV;
+                /*
+                 * OK let us guess that the driver is not there yet, and
+                 * let's defer obtaining this pinctrl handle to later...
+                 */
+                return -EPROBE_DEFER;
         }
 
         switch (map->type) {
@@ -579,6 +604,13 @@ static struct pinctrl *create_pinctrl(struct device *dev)
         }
         p->dev = dev;
         INIT_LIST_HEAD(&p->states);
+        INIT_LIST_HEAD(&p->dt_maps);
+
+        ret = pinctrl_dt_to_map(p);
+        if (ret < 0) {
+                kfree(p);
+                return ERR_PTR(ret);
+        }
 
         devname = dev_name(dev);
 
@@ -662,6 +694,8 @@ static void pinctrl_put_locked(struct pinctrl *p, bool inlist)
                 kfree(state);
         }
 
+        pinctrl_dt_free_maps(p);
+
         if (inlist)
                 list_del(&p->node);
         kfree(p);
@@ -787,15 +821,63 @@ int pinctrl_select_state(struct pinctrl *p, struct pinctrl_state *state)
 }
 EXPORT_SYMBOL_GPL(pinctrl_select_state);
 
+static void devm_pinctrl_release(struct device *dev, void *res)
+{
+        pinctrl_put(*(struct pinctrl **)res);
+}
+
 /**
- * pinctrl_register_mappings() - register a set of pin controller mappings
- * @maps: the pincontrol mappings table to register. This should probably be
- *      marked with __initdata so it can be discarded after boot. This
- *      function will perform a shallow copy for the mapping entries.
- * @num_maps: the number of maps in the mapping table
+ * struct devm_pinctrl_get() - Resource managed pinctrl_get()
+ * @dev: the device to obtain the handle for
+ *
+ * If there is a need to explicitly destroy the returned struct pinctrl,
+ * devm_pinctrl_put() should be used, rather than plain pinctrl_put().
  */
-int pinctrl_register_mappings(struct pinctrl_map const *maps,
-                              unsigned num_maps)
+struct pinctrl *devm_pinctrl_get(struct device *dev)
+{
+        struct pinctrl **ptr, *p;
+
+        ptr = devres_alloc(devm_pinctrl_release, sizeof(*ptr), GFP_KERNEL);
+        if (!ptr)
+                return ERR_PTR(-ENOMEM);
+
+        p = pinctrl_get(dev);
+        if (!IS_ERR(p)) {
+                *ptr = p;
+                devres_add(dev, ptr);
+        } else {
+                devres_free(ptr);
+        }
+
+        return p;
+}
+EXPORT_SYMBOL_GPL(devm_pinctrl_get);
+
+static int devm_pinctrl_match(struct device *dev, void *res, void *data)
+{
+        struct pinctrl **p = res;
+
+        return *p == data;
+}
+
+/**
+ * devm_pinctrl_put() - Resource managed pinctrl_put()
+ * @p: the pinctrl handle to release
+ *
+ * Deallocate a struct pinctrl obtained via devm_pinctrl_get(). Normally
+ * this function will not need to be called and the resource management
+ * code will ensure that the resource is freed.
+ */
+void devm_pinctrl_put(struct pinctrl *p)
+{
+        WARN_ON(devres_destroy(p->dev, devm_pinctrl_release,
+                               devm_pinctrl_match, p));
+        pinctrl_put(p);
+}
+EXPORT_SYMBOL_GPL(devm_pinctrl_put);
+
+int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps,
+                         bool dup, bool locked)
 {
         int i, ret;
         struct pinctrl_maps *maps_node;
@@ -851,20 +933,52 @@ int pinctrl_register_mappings(struct pinctrl_map const *maps,
         }
 
         maps_node->num_maps = num_maps;
-        maps_node->maps = kmemdup(maps, sizeof(*maps) * num_maps, GFP_KERNEL);
-        if (!maps_node->maps) {
-                pr_err("failed to duplicate mapping table\n");
-                kfree(maps_node);
-                return -ENOMEM;
+        if (dup) {
+                maps_node->maps = kmemdup(maps, sizeof(*maps) * num_maps,
+                                          GFP_KERNEL);
+                if (!maps_node->maps) {
+                        pr_err("failed to duplicate mapping table\n");
+                        kfree(maps_node);
+                        return -ENOMEM;
+                }
+        } else {
+                maps_node->maps = maps;
         }
 
-        mutex_lock(&pinctrl_mutex);
+        if (!locked)
+                mutex_lock(&pinctrl_mutex);
         list_add_tail(&maps_node->node, &pinctrl_maps);
-        mutex_unlock(&pinctrl_mutex);
+        if (!locked)
+                mutex_unlock(&pinctrl_mutex);
 
         return 0;
 }
 
+/**
+ * pinctrl_register_mappings() - register a set of pin controller mappings
+ * @maps: the pincontrol mappings table to register. This should probably be
+ *      marked with __initdata so it can be discarded after boot. This
+ *      function will perform a shallow copy for the mapping entries.
+ * @num_maps: the number of maps in the mapping table
+ */
+int pinctrl_register_mappings(struct pinctrl_map const *maps,
+                              unsigned num_maps)
+{
+        return pinctrl_register_map(maps, num_maps, true, false);
+}
+
+void pinctrl_unregister_map(struct pinctrl_map const *map)
+{
+        struct pinctrl_maps *maps_node;
+
+        list_for_each_entry(maps_node, &pinctrl_maps, node) {
+                if (maps_node->maps == map) {
+                        list_del(&maps_node->node);
+                        return;
+                }
+        }
+}
+
 #ifdef CONFIG_DEBUG_FS
 
 static int pinctrl_pins_show(struct seq_file *s, void *what)
@@ -906,15 +1020,17 @@ static int pinctrl_groups_show(struct seq_file *s, void *what)
 {
         struct pinctrl_dev *pctldev = s->private;
         const struct pinctrl_ops *ops = pctldev->desc->pctlops;
-        unsigned selector = 0;
+        unsigned ngroups, selector = 0;
 
+        ngroups = ops->get_groups_count(pctldev);
         mutex_lock(&pinctrl_mutex);
 
         seq_puts(s, "registered pin groups:\n");
-        while (ops->list_groups(pctldev, selector) >= 0) {
+        while (selector < ngroups) {
                 const unsigned *pins;
                 unsigned num_pins;
                 const char *gname = ops->get_group_name(pctldev, selector);
+                const char *pname;
                 int ret;
                 int i;
 
@@ -924,10 +1040,14 @@ static int pinctrl_groups_show(struct seq_file *s, void *what)
                         seq_printf(s, "%s [ERROR GETTING PINS]\n",
                                    gname);
                 else {
-                        seq_printf(s, "group: %s, pins = [ ", gname);
-                        for (i = 0; i < num_pins; i++)
-                                seq_printf(s, "%d ", pins[i]);
-                        seq_puts(s, "]\n");
+                        seq_printf(s, "group: %s\n", gname);
+                        for (i = 0; i < num_pins; i++) {
+                                pname = pin_get_name(pctldev, pins[i]);
+                                if (WARN_ON(!pname))
+                                        return -EINVAL;
+                                seq_printf(s, "pin %d (%s)\n", pins[i], pname);
+                        }
+                        seq_puts(s, "\n");
                 }
                 selector++;
         }
@@ -1226,11 +1346,14 @@ static int pinctrl_check_ops(struct pinctrl_dev *pctldev)
         const struct pinctrl_ops *ops = pctldev->desc->pctlops;
 
         if (!ops ||
-            !ops->list_groups ||
+            !ops->get_groups_count ||
             !ops->get_group_name ||
             !ops->get_group_pins)
                 return -EINVAL;
 
+        if (ops->dt_node_to_map && !ops->dt_free_map)
+                return -EINVAL;
+
         return 0;
 }
 
diff --git a/drivers/pinctrl/core.h b/drivers/pinctrl/core.h
index 17ecf651b123..1f40ff68a8c4 100644
--- a/drivers/pinctrl/core.h
+++ b/drivers/pinctrl/core.h
@@ -52,12 +52,15 @@ struct pinctrl_dev {
  * @dev: the device using this pin control handle
  * @states: a list of states for this device
  * @state: the current state
+ * @dt_maps: the mapping table chunks dynamically parsed from device tree for
+ *      this device, if any
  */
 struct pinctrl {
         struct list_head node;
         struct device *dev;
         struct list_head states;
         struct pinctrl_state *state;
+        struct list_head dt_maps;
 };
 
 /**
@@ -100,7 +103,8 @@ struct pinctrl_setting_configs {
  * struct pinctrl_setting - an individual mux or config setting
  * @node: list node for struct pinctrl_settings's @settings field
  * @type: the type of setting
- * @pctldev: pin control device handling to be programmed
+ * @pctldev: pin control device handling to be programmed. Not used for
+ *   PIN_MAP_TYPE_DUMMY_STATE.
  * @data: Data specific to the setting type
  */
 struct pinctrl_setting {
@@ -144,6 +148,7 @@ struct pin_desc {
 
 struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *dev_name);
 int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name);
+const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin);
 int pinctrl_get_group_selector(struct pinctrl_dev *pctldev,
                                const char *pin_group);
 
@@ -153,4 +158,9 @@ static inline struct pin_desc *pin_desc_get(struct pinctrl_dev *pctldev,
         return radix_tree_lookup(&pctldev->pin_desc_tree, pin);
 }
 
+int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps,
+                         bool dup, bool locked);
+void pinctrl_unregister_map(struct pinctrl_map const *map);
+
 extern struct mutex pinctrl_mutex;
+extern struct list_head pinctrldev_list;
diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c
new file mode 100644
index 000000000000..fcb1de45473c
--- /dev/null
+++ b/drivers/pinctrl/devicetree.c
@@ -0,0 +1,249 @@
+/*
+ * Device tree integration for the pin control subsystem
+ *
+ * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/device.h>
+#include <linux/of.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/slab.h>
+
+#include "core.h"
+#include "devicetree.h"
+
+/**
+ * struct pinctrl_dt_map - mapping table chunk parsed from device tree
+ * @node: list node for struct pinctrl's @dt_maps field
+ * @pctldev: the pin controller that allocated this struct, and will free it
+ * @maps: the mapping table entries
+ */
+struct pinctrl_dt_map {
+        struct list_head node;
+        struct pinctrl_dev *pctldev;
+        struct pinctrl_map *map;
+        unsigned num_maps;
+};
+
+static void dt_free_map(struct pinctrl_dev *pctldev,
+                     struct pinctrl_map *map, unsigned num_maps)
+{
+        if (pctldev) {
+                struct pinctrl_ops *ops = pctldev->desc->pctlops;
+                ops->dt_free_map(pctldev, map, num_maps);
+        } else {
+                /* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */
+                kfree(map);
+        }
+}
+
+void pinctrl_dt_free_maps(struct pinctrl *p)
+{
+        struct pinctrl_dt_map *dt_map, *n1;
+
+        list_for_each_entry_safe(dt_map, n1, &p->dt_maps, node) {
+                pinctrl_unregister_map(dt_map->map);
+                list_del(&dt_map->node);
+                dt_free_map(dt_map->pctldev, dt_map->map,
+                            dt_map->num_maps);
+                kfree(dt_map);
+        }
+
+        of_node_put(p->dev->of_node);
+}
+
+static int dt_remember_or_free_map(struct pinctrl *p, const char *statename,
+                                   struct pinctrl_dev *pctldev,
+                                   struct pinctrl_map *map, unsigned num_maps)
+{
+        int i;
+        struct pinctrl_dt_map *dt_map;
+
+        /* Initialize common mapping table entry fields */
+        for (i = 0; i < num_maps; i++) {
+                map[i].dev_name = dev_name(p->dev);
+                map[i].name = statename;
+                if (pctldev)
+                        map[i].ctrl_dev_name = dev_name(pctldev->dev);
+        }
+
+        /* Remember the converted mapping table entries */
+        dt_map = kzalloc(sizeof(*dt_map), GFP_KERNEL);
+        if (!dt_map) {
+                dev_err(p->dev, "failed to alloc struct pinctrl_dt_map\n");
+                dt_free_map(pctldev, map, num_maps);
+                return -ENOMEM;
+        }
+
+        dt_map->pctldev = pctldev;
+        dt_map->map = map;
+        dt_map->num_maps = num_maps;
+        list_add_tail(&dt_map->node, &p->dt_maps);
+
+        return pinctrl_register_map(map, num_maps, false, true);
+}
+
+static struct pinctrl_dev *find_pinctrl_by_of_node(struct device_node *np)
+{
+        struct pinctrl_dev *pctldev;
+
+        list_for_each_entry(pctldev, &pinctrldev_list, node)
+                if (pctldev->dev->of_node == np)
+                        return pctldev;
+
+        return NULL;
+}
+
+static int dt_to_map_one_config(struct pinctrl *p, const char *statename,
+                                struct device_node *np_config)
+{
+        struct device_node *np_pctldev;
+        struct pinctrl_dev *pctldev;
+        struct pinctrl_ops *ops;
+        int ret;
+        struct pinctrl_map *map;
+        unsigned num_maps;
+
+        /* Find the pin controller containing np_config */
+        np_pctldev = of_node_get(np_config);
+        for (;;) {
+                np_pctldev = of_get_next_parent(np_pctldev);
+                if (!np_pctldev || of_node_is_root(np_pctldev)) {
+                        dev_info(p->dev, "could not find pctldev for node %s, deferring probe\n",
+                                np_config->full_name);
+                        of_node_put(np_pctldev);
+                        /* OK let's just assume this will appear later then */
+                        return -EPROBE_DEFER;
+                }
+                pctldev = find_pinctrl_by_of_node(np_pctldev);
+                if (pctldev)
+                        break;
+        }
+        of_node_put(np_pctldev);
+
+        /*
+         * Call pinctrl driver to parse device tree node, and
+         * generate mapping table entries
+         */
+        ops = pctldev->desc->pctlops;
+        if (!ops->dt_node_to_map) {
+                dev_err(p->dev, "pctldev %s doesn't support DT\n",
+                        dev_name(pctldev->dev));
+                return -ENODEV;
+        }
+        ret = ops->dt_node_to_map(pctldev, np_config, &map, &num_maps);
+        if (ret < 0)
+                return ret;
+
+        /* Stash the mapping table chunk away for later use */
+        return dt_remember_or_free_map(p, statename, pctldev, map, num_maps);
+}
+
+static int dt_remember_dummy_state(struct pinctrl *p, const char *statename)
+{
+        struct pinctrl_map *map;
+
+        map = kzalloc(sizeof(*map), GFP_KERNEL);
+        if (!map) {
+                dev_err(p->dev, "failed to alloc struct pinctrl_map\n");
+                return -ENOMEM;
+        }
+
+        /* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */
+        map->type = PIN_MAP_TYPE_DUMMY_STATE;
+
+        return dt_remember_or_free_map(p, statename, NULL, map, 1);
+}
+
+int pinctrl_dt_to_map(struct pinctrl *p)
+{
+        struct device_node *np = p->dev->of_node;
+        int state, ret;
+        char *propname;
+        struct property *prop;
+        const char *statename;
+        const __be32 *list;
+        int size, config;
+        phandle phandle;
+        struct device_node *np_config;
+
+        /* CONFIG_OF enabled, p->dev not instantiated from DT */
+        if (!np) {
+                dev_dbg(p->dev, "no of_node; not parsing pinctrl DT\n");
+                return 0;
+        }
+
+        /* We may store pointers to property names within the node */
+        of_node_get(np);
+
+        /* For each defined state ID */
+        for (state = 0; ; state++) {
+                /* Retrieve the pinctrl-* property */
+                propname = kasprintf(GFP_KERNEL, "pinctrl-%d", state);
+                prop = of_find_property(np, propname, &size);
+                kfree(propname);
+                if (!prop)
+                        break;
+                list = prop->value;
+                size /= sizeof(*list);
+
+                /* Determine whether pinctrl-names property names the state */
+                ret = of_property_read_string_index(np, "pinctrl-names",
+                                                    state, &statename);
+                /*
+                 * If not, statename is just the integer state ID. But rather
+                 * than dynamically allocate it and have to free it later,
+                 * just point part way into the property name for the string.
+                 */
+                if (ret < 0) {
+                        /* strlen("pinctrl-") == 8 */
+                        statename = prop->name + 8;
+                }
+
+                /* For every referenced pin configuration node in it */
+                for (config = 0; config < size; config++) {
+                        phandle = be32_to_cpup(list++);
+
+                        /* Look up the pin configuration node */
+                        np_config = of_find_node_by_phandle(phandle);
+                        if (!np_config) {
+                                dev_err(p->dev,
+                                        "prop %s index %i invalid phandle\n",
+                                        prop->name, config);
+                                ret = -EINVAL;
+                                goto err;
+                        }
+
+                        /* Parse the node */
+                        ret = dt_to_map_one_config(p, statename, np_config);
+                        of_node_put(np_config);
+                        if (ret < 0)
+                                goto err;
+                }
+
+                /* No entries in DT? Generate a dummy state table entry */
+                if (!size) {
+                        ret = dt_remember_dummy_state(p, statename);
+                        if (ret < 0)
+                                goto err;
+                }
+        }
+
+        return 0;
+
+err:
+        pinctrl_dt_free_maps(p);
+        return ret;
+}
diff --git a/drivers/pinctrl/devicetree.h b/drivers/pinctrl/devicetree.h
new file mode 100644
index 000000000000..760bc4960f58
--- /dev/null
+++ b/drivers/pinctrl/devicetree.h
@@ -0,0 +1,35 @@
+/*
+ * Internal interface to pinctrl device tree integration
+ *
+ * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifdef CONFIG_OF
+
+void pinctrl_dt_free_maps(struct pinctrl *p);
+int pinctrl_dt_to_map(struct pinctrl *p);
+
+#else
+
+static inline int pinctrl_dt_to_map(struct pinctrl *p)
+{
+        return 0;
+}
+
+static inline void pinctrl_dt_free_maps(struct pinctrl *p)
+{
+}
+
+#endif
diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c
index 7321e8601294..14f48c96b20d 100644
--- a/drivers/pinctrl/pinconf.c
+++ b/drivers/pinctrl/pinconf.c
@@ -379,8 +379,16 @@ int pinconf_apply_setting(struct pinctrl_setting const *setting)
 
 void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map)
 {
+        struct pinctrl_dev *pctldev;
+        const struct pinconf_ops *confops;
         int i;
 
+        pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name);
+        if (pctldev)
+                confops = pctldev->desc->confops;
+        else
+                confops = NULL;
+
         switch (map->type) {
         case PIN_MAP_TYPE_CONFIGS_PIN:
                 seq_printf(s, "pin ");
@@ -394,8 +402,15 @@ void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map)
 
         seq_printf(s, "%s\n", map->data.configs.group_or_pin);
 
-        for (i = 0; i < map->data.configs.num_configs; i++)
-                seq_printf(s, "config %08lx\n", map->data.configs.configs[i]);
+        for (i = 0; i < map->data.configs.num_configs; i++) {
+                seq_printf(s, "config ");
+                if (confops && confops->pin_config_config_dbg_show)
+                        confops->pin_config_config_dbg_show(pctldev, s,
+                                                map->data.configs.configs[i]);
+                else
+                        seq_printf(s, "%08lx", map->data.configs.configs[i]);
+                seq_printf(s, "\n");
+        }
 }
 
 void pinconf_show_setting(struct seq_file *s,
@@ -403,6 +418,7 @@ void pinconf_show_setting(struct seq_file *s,
 {
         struct pinctrl_dev *pctldev = setting->pctldev;
         const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
+        const struct pinconf_ops *confops = pctldev->desc->confops;
         struct pin_desc *desc;
         int i;
 
@@ -428,8 +444,15 @@ void pinconf_show_setting(struct seq_file *s,
          * FIXME: We should really get the pin controler to dump the config
          * values, so they can be decoded to something meaningful.
          */
-        for (i = 0; i < setting->data.configs.num_configs; i++)
-                seq_printf(s, " %08lx", setting->data.configs.configs[i]);
+        for (i = 0; i < setting->data.configs.num_configs; i++) {
+                seq_printf(s, " ");
+                if (confops && confops->pin_config_config_dbg_show)
+                        confops->pin_config_config_dbg_show(pctldev, s,
+                                setting->data.configs.configs[i]);
+                else
+                        seq_printf(s, "%08lx",
+                                   setting->data.configs.configs[i]);
+        }
 
         seq_printf(s, "\n");
 }
@@ -448,10 +471,14 @@ static void pinconf_dump_pin(struct pinctrl_dev *pctldev,
 static int pinconf_pins_show(struct seq_file *s, void *what)
 {
         struct pinctrl_dev *pctldev = s->private;
+        const struct pinconf_ops *ops = pctldev->desc->confops;
         unsigned i, pin;
 
+        if (!ops || !ops->pin_config_get)
+                return 0;
+
         seq_puts(s, "Pin config settings per pin\n");
-        seq_puts(s, "Format: pin (name): pinmux setting array\n");
+        seq_puts(s, "Format: pin (name): configs\n");
 
         mutex_lock(&pinctrl_mutex);
 
@@ -495,17 +522,18 @@ static int pinconf_groups_show(struct seq_file *s, void *what)
         struct pinctrl_dev *pctldev = s->private;
         const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
         const struct pinconf_ops *ops = pctldev->desc->confops;
+        unsigned ngroups = pctlops->get_groups_count(pctldev);
         unsigned selector = 0;
 
         if (!ops || !ops->pin_config_group_get)
                 return 0;
 
         seq_puts(s, "Pin config settings per pin group\n");
-        seq_puts(s, "Format: group (name): pinmux setting array\n");
+        seq_puts(s, "Format: group (name): configs\n");
 
         mutex_lock(&pinctrl_mutex);
 
-        while (pctlops->list_groups(pctldev, selector) >= 0) {
+        while (selector < ngroups) {
                 const char *gname = pctlops->get_group_name(pctldev, selector);
 
                 seq_printf(s, "%u (%s):", selector, gname);
diff --git a/drivers/pinctrl/pinconf.h b/drivers/pinctrl/pinconf.h
index 54510de5e8c6..e3ed8cb072a5 100644
--- a/drivers/pinctrl/pinconf.h
+++ b/drivers/pinctrl/pinconf.h
@@ -19,11 +19,6 @@ int pinconf_map_to_setting(struct pinctrl_map const *map,
                           struct pinctrl_setting *setting);
 void pinconf_free_setting(struct pinctrl_setting const *setting);
 int pinconf_apply_setting(struct pinctrl_setting const *setting);
-void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map);
-void pinconf_show_setting(struct seq_file *s,
-                          struct pinctrl_setting const *setting);
-void pinconf_init_device_debugfs(struct dentry *devroot,
-                                 struct pinctrl_dev *pctldev);
 
 /*
  * You will only be interested in these if you're using PINCONF
@@ -61,6 +56,18 @@ static inline int pinconf_apply_setting(struct pinctrl_setting const *setting)
         return 0;
 }
 
+#endif
+
+#if defined(CONFIG_PINCONF) && defined(CONFIG_DEBUG_FS)
+
+void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map);
+void pinconf_show_setting(struct seq_file *s,
+                          struct pinctrl_setting const *setting);
+void pinconf_init_device_debugfs(struct dentry *devroot,
+                                 struct pinctrl_dev *pctldev);
+
+#else
+
 static inline void pinconf_show_map(struct seq_file *s,
                                     struct pinctrl_map const *map)
 {
diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c
index 0797eba3e33a..55697a5d7482 100644
--- a/drivers/pinctrl/pinctrl-coh901.c
+++ b/drivers/pinctrl/pinctrl-coh901.c
@@ -174,7 +174,7 @@ struct u300_gpio_confdata {
 
 
 /* Initial configuration */
-static const struct __initdata u300_gpio_confdata
+static const struct __initconst u300_gpio_confdata
 bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
         /* Port 0, pins 0-7 */
         {
@@ -255,7 +255,7 @@ bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
         }
 };
 
-static const struct __initdata u300_gpio_confdata
+static const struct __initconst u300_gpio_confdata
 bs365_gpio_config[BS365_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
         /* Port 0, pins 0-7 */
         {
diff --git a/drivers/pinctrl/pinctrl-pxa3xx.c b/drivers/pinctrl/pinctrl-pxa3xx.c
index 079dce0e93e9..7644e42ac211 100644
--- a/drivers/pinctrl/pinctrl-pxa3xx.c
+++ b/drivers/pinctrl/pinctrl-pxa3xx.c
@@ -25,20 +25,18 @@ static struct pinctrl_gpio_range pxa3xx_pinctrl_gpio_range = {
         .pin_base       = 0,
 };
 
-static int pxa3xx_list_groups(struct pinctrl_dev *pctrldev, unsigned selector)
+static int pxa3xx_get_groups_count(struct pinctrl_dev *pctrldev)
 {
         struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
-        if (selector >= info->num_grps)
-                return -EINVAL;
-        return 0;
+
+        return info->num_grps;
 }
 
 static const char *pxa3xx_get_group_name(struct pinctrl_dev *pctrldev,
                                          unsigned selector)
 {
         struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
-        if (selector >= info->num_grps)
-                return NULL;
+
         return info->grps[selector].name;
 }
 
@@ -48,25 +46,23 @@ static int pxa3xx_get_group_pins(struct pinctrl_dev *pctrldev,
                                  unsigned *num_pins)
 {
         struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
-        if (selector >= info->num_grps)
-                return -EINVAL;
+
         *pins = info->grps[selector].pins;
         *num_pins = info->grps[selector].npins;
         return 0;
 }
 
 static struct pinctrl_ops pxa3xx_pctrl_ops = {
-        .list_groups    = pxa3xx_list_groups,
+        .get_groups_count = pxa3xx_get_groups_count,
         .get_group_name = pxa3xx_get_group_name,
         .get_group_pins = pxa3xx_get_group_pins,
 };
 
-static int pxa3xx_pmx_list_func(struct pinctrl_dev *pctrldev, unsigned func)
+static int pxa3xx_pmx_get_funcs_count(struct pinctrl_dev *pctrldev)
 {
         struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
-        if (func >= info->num_funcs)
-                return -EINVAL;
-        return 0;
+
+        return info->num_funcs;
 }
 
 static const char *pxa3xx_pmx_get_func_name(struct pinctrl_dev *pctrldev,
@@ -170,7 +166,7 @@ static int pxa3xx_pmx_request_gpio(struct pinctrl_dev *pctrldev,
 }
 
 static struct pinmux_ops pxa3xx_pmx_ops = {
-        .list_functions         = pxa3xx_pmx_list_func,
+        .get_functions_count    = pxa3xx_pmx_get_funcs_count,
         .get_function_name      = pxa3xx_pmx_get_func_name,
         .get_function_groups    = pxa3xx_pmx_get_groups,
         .enable                 = pxa3xx_pmx_enable,
diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/pinctrl-sirf.c
index 6b3534cc051a..ba15b1a29e52 100644
--- a/drivers/pinctrl/pinctrl-sirf.c
+++ b/drivers/pinctrl/pinctrl-sirf.c
@@ -853,18 +853,14 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
         SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
 };
 
-static int sirfsoc_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
+static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev)
 {
-        if (selector >= ARRAY_SIZE(sirfsoc_pin_groups))
-                return -EINVAL;
-        return 0;
+        return ARRAY_SIZE(sirfsoc_pin_groups);
 }
 
 static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
                                        unsigned selector)
 {
-        if (selector >= ARRAY_SIZE(sirfsoc_pin_groups))
-                return NULL;
         return sirfsoc_pin_groups[selector].name;
 }
 
@@ -872,8 +868,6 @@ static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector
                                const unsigned **pins,
                                unsigned *num_pins)
 {
-        if (selector >= ARRAY_SIZE(sirfsoc_pin_groups))
-                return -EINVAL;
         *pins = sirfsoc_pin_groups[selector].pins;
         *num_pins = sirfsoc_pin_groups[selector].num_pins;
         return 0;
@@ -886,7 +880,7 @@ static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s
 }
 
 static struct pinctrl_ops sirfsoc_pctrl_ops = {
-        .list_groups = sirfsoc_list_groups,
+        .get_groups_count = sirfsoc_get_groups_count,
         .get_group_name = sirfsoc_get_group_name,
         .get_group_pins = sirfsoc_get_group_pins,
         .pin_dbg_show = sirfsoc_pin_dbg_show,
@@ -1033,11 +1027,9 @@ static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector
         sirfsoc_pinmux_endisable(spmx, selector, false);
 }
 
-static int sirfsoc_pinmux_list_funcs(struct pinctrl_dev *pmxdev, unsigned selector)
+static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
 {
-        if (selector >= ARRAY_SIZE(sirfsoc_pmx_functions))
-                return -EINVAL;
-        return 0;
+        return ARRAY_SIZE(sirfsoc_pmx_functions);
 }
 
 static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
@@ -1074,9 +1066,9 @@ static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
 }
 
 static struct pinmux_ops sirfsoc_pinmux_ops = {
-        .list_functions = sirfsoc_pinmux_list_funcs,
         .enable = sirfsoc_pinmux_enable,
         .disable = sirfsoc_pinmux_disable,
+        .get_functions_count = sirfsoc_pinmux_get_funcs_count,
         .get_function_name = sirfsoc_pinmux_get_func_name,
         .get_function_groups = sirfsoc_pinmux_get_groups,
         .gpio_request_enable = sirfsoc_pinmux_request_gpio,
diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c
index 9b329688120c..b6934867d8d3 100644
--- a/drivers/pinctrl/pinctrl-tegra.c
+++ b/drivers/pinctrl/pinctrl-tegra.c
@@ -1,7 +1,7 @@
 /*
  * Driver for the NVIDIA Tegra pinmux
  *
- * Copyright (c) 2011, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
  *
  * Derived from code:
  * Copyright (C) 2010 Google, Inc.
@@ -22,17 +22,19 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/pinmux.h>
 #include <linux/pinctrl/pinconf.h>
+#include <linux/slab.h>
 
 #include <mach/pinconf-tegra.h>
 
+#include "core.h"
 #include "pinctrl-tegra.h"
 
-#define DRIVER_NAME "tegra-pinmux-disabled"
-
 struct tegra_pmx {
         struct device *dev;
         struct pinctrl_dev *pctl;
@@ -53,15 +55,11 @@ static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
         writel(val, pmx->regs[bank] + reg);
 }
 
-static int tegra_pinctrl_list_groups(struct pinctrl_dev *pctldev,
-                                     unsigned group)
+static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
 {
         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 
-        if (group >= pmx->soc->ngroups)
-                return -EINVAL;
-
-        return 0;
+        return pmx->soc->ngroups;
 }
 
 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
@@ -69,9 +67,6 @@ static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
 {
         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 
-        if (group >= pmx->soc->ngroups)
-                return NULL;
-
         return pmx->soc->groups[group].name;
 }
 
@@ -82,38 +77,259 @@ static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
 {
         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 
-        if (group >= pmx->soc->ngroups)
-                return -EINVAL;
-
         *pins = pmx->soc->groups[group].pins;
         *num_pins = pmx->soc->groups[group].npins;
 
         return 0;
 }
 
+#ifdef CONFIG_DEBUG_FS
 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
                                        struct seq_file *s,
                                        unsigned offset)
 {
-        seq_printf(s, " " DRIVER_NAME);
+        seq_printf(s, " %s", dev_name(pctldev->dev));
+}
+#endif
+
+static int reserve_map(struct device *dev, struct pinctrl_map **map,
+                       unsigned *reserved_maps, unsigned *num_maps,
+                       unsigned reserve)
+{
+        unsigned old_num = *reserved_maps;
+        unsigned new_num = *num_maps + reserve;
+        struct pinctrl_map *new_map;
+
+        if (old_num >= new_num)
+                return 0;
+
+        new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
+        if (!new_map) {
+                dev_err(dev, "krealloc(map) failed\n");
+                return -ENOMEM;
+        }
+
+        memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
+
+        *map = new_map;
+        *reserved_maps = new_num;
+
+        return 0;
+}
+
+static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
+                       unsigned *num_maps, const char *group,
+                       const char *function)
+{
+        if (WARN_ON(*num_maps == *reserved_maps))
+                return -ENOSPC;
+
+        (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
+        (*map)[*num_maps].data.mux.group = group;
+        (*map)[*num_maps].data.mux.function = function;
+        (*num_maps)++;
+
+        return 0;
+}
+
+static int add_map_configs(struct device *dev, struct pinctrl_map **map,
+                           unsigned *reserved_maps, unsigned *num_maps,
+                           const char *group, unsigned long *configs,
+                           unsigned num_configs)
+{
+        unsigned long *dup_configs;
+
+        if (WARN_ON(*num_maps == *reserved_maps))
+                return -ENOSPC;
+
+        dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
+                              GFP_KERNEL);
+        if (!dup_configs) {
+                dev_err(dev, "kmemdup(configs) failed\n");
+                return -ENOMEM;
+        }
+
+        (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
+        (*map)[*num_maps].data.configs.group_or_pin = group;
+        (*map)[*num_maps].data.configs.configs = dup_configs;
+        (*map)[*num_maps].data.configs.num_configs = num_configs;
+        (*num_maps)++;
+
+        return 0;
+}
+
+static int add_config(struct device *dev, unsigned long **configs,
+                      unsigned *num_configs, unsigned long config)
+{
+        unsigned old_num = *num_configs;
+        unsigned new_num = old_num + 1;
+        unsigned long *new_configs;
+
+        new_configs = krealloc(*configs, sizeof(*new_configs) * new_num,
+                               GFP_KERNEL);
+        if (!new_configs) {
+                dev_err(dev, "krealloc(configs) failed\n");
+                return -ENOMEM;
+        }
+
+        new_configs[old_num] = config;
+
+        *configs = new_configs;
+        *num_configs = new_num;
+
+        return 0;
+}
+
+void tegra_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
+                               struct pinctrl_map *map, unsigned num_maps)
+{
+        int i;
+
+        for (i = 0; i < num_maps; i++)
+                if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
+                        kfree(map[i].data.configs.configs);
+
+        kfree(map);
+}
+
+static const struct cfg_param {
+        const char *property;
+        enum tegra_pinconf_param param;
+} cfg_params[] = {
+        {"nvidia,pull",                 TEGRA_PINCONF_PARAM_PULL},
+        {"nvidia,tristate",             TEGRA_PINCONF_PARAM_TRISTATE},
+        {"nvidia,enable-input",         TEGRA_PINCONF_PARAM_ENABLE_INPUT},
+        {"nvidia,open-drain",           TEGRA_PINCONF_PARAM_OPEN_DRAIN},
+        {"nvidia,lock",                 TEGRA_PINCONF_PARAM_LOCK},
+        {"nvidia,io-reset",             TEGRA_PINCONF_PARAM_IORESET},
+        {"nvidia,high-speed-mode",      TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
+        {"nvidia,schmitt",              TEGRA_PINCONF_PARAM_SCHMITT},
+        {"nvidia,low-power-mode",       TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
+        {"nvidia,pull-down-strength",   TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
+        {"nvidia,pull-up-strength",     TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
+        {"nvidia,slew-rate-falling",    TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
+        {"nvidia,slew-rate-rising",     TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
+};
+
+int tegra_pinctrl_dt_subnode_to_map(struct device *dev,
+                                    struct device_node *np,
+                                    struct pinctrl_map **map,
+                                    unsigned *reserved_maps,
+                                    unsigned *num_maps)
+{
+        int ret, i;
+        const char *function;
+        u32 val;
+        unsigned long config;
+        unsigned long *configs = NULL;
+        unsigned num_configs = 0;
+        unsigned reserve;
+        struct property *prop;
+        const char *group;
+
+        ret = of_property_read_string(np, "nvidia,function", &function);
+        if (ret < 0) {
+                /* EINVAL=missing, which is fine since it's optional */
+                if (ret != -EINVAL)
+                        dev_err(dev,
+                                "could not parse property nvidia,function\n");
+                function = NULL;
+        }
+
+        for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
+                ret = of_property_read_u32(np, cfg_params[i].property, &val);
+                if (!ret) {
+                        config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
+                        ret = add_config(dev, &configs, &num_configs, config);
+                        if (ret < 0)
+                                goto exit;
+                /* EINVAL=missing, which is fine since it's optional */
+                } else if (ret != -EINVAL) {
+                        dev_err(dev, "could not parse property %s\n",
+                                cfg_params[i].property);
+                }
+        }
+
+        reserve = 0;
+        if (function != NULL)
+                reserve++;
+        if (num_configs)
+                reserve++;
+        ret = of_property_count_strings(np, "nvidia,pins");
+        if (ret < 0) {
+                dev_err(dev, "could not parse property nvidia,pins\n");
+                goto exit;
+        }
+        reserve *= ret;
+
+        ret = reserve_map(dev, map, reserved_maps, num_maps, reserve);
+        if (ret < 0)
+                goto exit;
+
+        of_property_for_each_string(np, "nvidia,pins", prop, group) {
+                if (function) {
+                        ret = add_map_mux(map, reserved_maps, num_maps,
+                                          group, function);
+                        if (ret < 0)
+                                goto exit;
+                }
+
+                if (num_configs) {
+                        ret = add_map_configs(dev, map, reserved_maps,
+                                              num_maps, group, configs,
+                                              num_configs);
+                        if (ret < 0)
+                                goto exit;
+                }
+        }
+
+        ret = 0;
+
+exit:
+        kfree(configs);
+        return ret;
+}
+
+int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
+                                 struct device_node *np_config,
+                                 struct pinctrl_map **map, unsigned *num_maps)
+{
+        unsigned reserved_maps;
+        struct device_node *np;
+        int ret;
+
+        reserved_maps = 0;
+        *map = NULL;
+        *num_maps = 0;
+
+        for_each_child_of_node(np_config, np) {
+                ret = tegra_pinctrl_dt_subnode_to_map(pctldev->dev, np, map,
+                                                      &reserved_maps, num_maps);
+                if (ret < 0) {
+                        tegra_pinctrl_dt_free_map(pctldev, *map, *num_maps);
+                        return ret;
+                }
+        }
+
+        return 0;
 }
 
 static struct pinctrl_ops tegra_pinctrl_ops = {
-        .list_groups = tegra_pinctrl_list_groups,
+        .get_groups_count = tegra_pinctrl_get_groups_count,
         .get_group_name = tegra_pinctrl_get_group_name,
         .get_group_pins = tegra_pinctrl_get_group_pins,
+#ifdef CONFIG_DEBUG_FS
         .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
+#endif
+        .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
+        .dt_free_map = tegra_pinctrl_dt_free_map,
 };
 
-static int tegra_pinctrl_list_funcs(struct pinctrl_dev *pctldev,
-                                    unsigned function)
+static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
 {
         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 
-        if (function >= pmx->soc->nfunctions)
-                return -EINVAL;
-
-        return 0;
+        return pmx->soc->nfunctions;
 }
 
 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
@@ -121,9 +337,6 @@ static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
 {
         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 
-        if (function >= pmx->soc->nfunctions)
-                return NULL;
-
         return pmx->soc->functions[function].name;
 }
 
@@ -134,9 +347,6 @@ static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
 {
         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 
-        if (function >= pmx->soc->nfunctions)
-                return -EINVAL;
-
         *groups = pmx->soc->functions[function].groups;
         *num_groups = pmx->soc->functions[function].ngroups;
 
@@ -151,18 +361,16 @@ static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
         int i;
         u32 val;
 
-        if (group >= pmx->soc->ngroups)
-                return -EINVAL;
         g = &pmx->soc->groups[group];
 
-        if (g->mux_reg < 0)
+        if (WARN_ON(g->mux_reg < 0))
                 return -EINVAL;
 
         for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
                 if (g->funcs[i] == function)
                         break;
         }
-        if (i == ARRAY_SIZE(g->funcs))
+        if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
                 return -EINVAL;
 
         val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
@@ -180,11 +388,9 @@ static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
         const struct tegra_pingroup *g;
         u32 val;
 
-        if (group >= pmx->soc->ngroups)
-                return;
         g = &pmx->soc->groups[group];
 
-        if (g->mux_reg < 0)
+        if (WARN_ON(g->mux_reg < 0))
                 return;
 
         val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
@@ -194,7 +400,7 @@ static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
 }
 
 static struct pinmux_ops tegra_pinmux_ops = {
-        .list_functions = tegra_pinctrl_list_funcs,
+        .get_functions_count = tegra_pinctrl_get_funcs_count,
         .get_function_name = tegra_pinctrl_get_func_name,
         .get_function_groups = tegra_pinctrl_get_func_groups,
         .enable = tegra_pinctrl_enable,
@@ -204,6 +410,7 @@ static struct pinmux_ops tegra_pinmux_ops = {
 static int tegra_pinconf_reg(struct tegra_pmx *pmx,
                              const struct tegra_pingroup *g,
                              enum tegra_pinconf_param param,
+                             bool report_err,
                              s8 *bank, s16 *reg, s8 *bit, s8 *width)
 {
         switch (param) {
@@ -291,9 +498,10 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
         }
 
         if (*reg < 0) {
-                dev_err(pmx->dev,
-                        "Config param %04x not supported on group %s\n",
-                        param, g->name);
+                if (report_err)
+                        dev_err(pmx->dev,
+                                "Config param %04x not supported on group %s\n",
+                                param, g->name);
                 return -ENOTSUPP;
         }
 
@@ -303,12 +511,14 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
 static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
                              unsigned pin, unsigned long *config)
 {
+        dev_err(pctldev->dev, "pin_config_get op not supported\n");
         return -ENOTSUPP;
 }
 
 static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
                              unsigned pin, unsigned long config)
 {
+        dev_err(pctldev->dev, "pin_config_set op not supported\n");
         return -ENOTSUPP;
 }
 
@@ -324,11 +534,10 @@ static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
         s16 reg;
         u32 val, mask;
 
-        if (group >= pmx->soc->ngroups)
-                return -EINVAL;
         g = &pmx->soc->groups[group];
 
-        ret = tegra_pinconf_reg(pmx, g, param, &bank, &reg, &bit, &width);
+        ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
+                                &width);
         if (ret < 0)
                 return ret;
 
@@ -353,11 +562,10 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
         s16 reg;
         u32 val, mask;
 
-        if (group >= pmx->soc->ngroups)
-                return -EINVAL;
         g = &pmx->soc->groups[group];
 
-        ret = tegra_pinconf_reg(pmx, g, param, &bank, &reg, &bit, &width);
+        ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
+                                &width);
         if (ret < 0)
                 return ret;
 
@@ -365,8 +573,10 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
 
         /* LOCK can't be cleared */
         if (param == TEGRA_PINCONF_PARAM_LOCK) {
-                if ((val & BIT(bit)) && !arg)
+                if ((val & BIT(bit)) && !arg) {
+                        dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
                         return -EINVAL;
+                }
         }
 
         /* Special-case Boolean values; allow any non-zero as true */
@@ -375,8 +585,12 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
 
         /* Range-check user-supplied value */
         mask = (1 << width) - 1;
-        if (arg & ~mask)
+        if (arg & ~mask) {
+                dev_err(pctldev->dev,
+                        "config %lx: %x too big for %d bit register\n",
+                        config, arg, width);
                 return -EINVAL;
+        }
 
         /* Update register */
         val &= ~(mask << bit);
@@ -386,23 +600,78 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
         return 0;
 }
 
+#ifdef CONFIG_DEBUG_FS
 static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
                                    struct seq_file *s, unsigned offset)
 {
 }
 
+static const char *strip_prefix(const char *s)
+{
+        const char *comma = strchr(s, ',');
+        if (!comma)
+                return s;
+
+        return comma + 1;
+}
+
 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
-                                         struct seq_file *s, unsigned selector)
+                                         struct seq_file *s, unsigned group)
 {
+        struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+        const struct tegra_pingroup *g;
+        int i, ret;
+        s8 bank, bit, width;
+        s16 reg;
+        u32 val;
+
+        g = &pmx->soc->groups[group];
+
+        for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
+                ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
+                                        &bank, &reg, &bit, &width);
+                if (ret < 0)
+                        continue;
+
+                val = pmx_readl(pmx, bank, reg);
+                val >>= bit;
+                val &= (1 << width) - 1;
+
+                seq_printf(s, "\n\t%s=%u",
+                           strip_prefix(cfg_params[i].property), val);
+        }
 }
 
+static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
+                                          struct seq_file *s,
+                                          unsigned long config)
+{
+        enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
+        u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
+        const char *pname = "unknown";
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
+                if (cfg_params[i].param == param) {
+                        pname = cfg_params[i].property;
+                        break;
+                }
+        }
+
+        seq_printf(s, "%s=%d", strip_prefix(pname), arg);
+}
+#endif
+
 struct pinconf_ops tegra_pinconf_ops = {
         .pin_config_get = tegra_pinconf_get,
         .pin_config_set = tegra_pinconf_set,
         .pin_config_group_get = tegra_pinconf_group_get,
         .pin_config_group_set = tegra_pinconf_group_set,
+#ifdef CONFIG_DEBUG_FS
         .pin_config_dbg_show = tegra_pinconf_dbg_show,
         .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
+        .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
+#endif
 };
 
 static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
@@ -412,60 +681,29 @@ static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
 };
 
 static struct pinctrl_desc tegra_pinctrl_desc = {
-        .name = DRIVER_NAME,
         .pctlops = &tegra_pinctrl_ops,
         .pmxops = &tegra_pinmux_ops,
         .confops = &tegra_pinconf_ops,
         .owner = THIS_MODULE,
 };
 
-static struct of_device_id tegra_pinctrl_of_match[] __devinitdata = {
-#ifdef CONFIG_PINCTRL_TEGRA20
-        {
-                .compatible = "nvidia,tegra20-pinmux-disabled",
-                .data = tegra20_pinctrl_init,
-        },
-#endif
-#ifdef CONFIG_PINCTRL_TEGRA30
-        {
-                .compatible = "nvidia,tegra30-pinmux-disabled",
-                .data = tegra30_pinctrl_init,
-        },
-#endif
-        {},
-};
-
-static int __devinit tegra_pinctrl_probe(struct platform_device *pdev)
+int __devinit tegra_pinctrl_probe(struct platform_device *pdev,
+                        const struct tegra_pinctrl_soc_data *soc_data)
 {
-        const struct of_device_id *match;
-        tegra_pinctrl_soc_initf initf = NULL;
         struct tegra_pmx *pmx;
         struct resource *res;
         int i;
 
-        match = of_match_device(tegra_pinctrl_of_match, &pdev->dev);
-        if (match)
-                initf = (tegra_pinctrl_soc_initf)match->data;
-#ifdef CONFIG_PINCTRL_TEGRA20
-        if (!initf)
-                initf = tegra20_pinctrl_init;
-#endif
-        if (!initf) {
-                dev_err(&pdev->dev,
-                        "Could not determine SoC-specific init func\n");
-                return -EINVAL;
-        }
-
         pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
         if (!pmx) {
                 dev_err(&pdev->dev, "Can't alloc tegra_pmx\n");
                 return -ENOMEM;
         }
         pmx->dev = &pdev->dev;
-
-        (*initf)(&pmx->soc);
+        pmx->soc = soc_data;
 
         tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
+        tegra_pinctrl_desc.name = dev_name(&pdev->dev);
         tegra_pinctrl_desc.pins = pmx->soc->pins;
         tegra_pinctrl_desc.npins = pmx->soc->npins;
 
@@ -520,8 +758,9 @@ static int __devinit tegra_pinctrl_probe(struct platform_device *pdev)
 
         return 0;
 }
+EXPORT_SYMBOL_GPL(tegra_pinctrl_probe);
 
-static int __devexit tegra_pinctrl_remove(struct platform_device *pdev)
+int __devexit tegra_pinctrl_remove(struct platform_device *pdev)
 {
         struct tegra_pmx *pmx = platform_get_drvdata(pdev);
 
@@ -530,30 +769,4 @@ static int __devexit tegra_pinctrl_remove(struct platform_device *pdev)
 
         return 0;
 }
-
-static struct platform_driver tegra_pinctrl_driver = {
-        .driver = {
-                .name = DRIVER_NAME,
-                .owner = THIS_MODULE,
-                .of_match_table = tegra_pinctrl_of_match,
-        },
-        .probe = tegra_pinctrl_probe,
-        .remove = __devexit_p(tegra_pinctrl_remove),
-};
-
-static int __init tegra_pinctrl_init(void)
-{
-        return platform_driver_register(&tegra_pinctrl_driver);
-}
-arch_initcall(tegra_pinctrl_init);
-
-static void __exit tegra_pinctrl_exit(void)
-{
-        platform_driver_unregister(&tegra_pinctrl_driver);
-}
-module_exit(tegra_pinctrl_exit);
-
-MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
-MODULE_DESCRIPTION("NVIDIA Tegra pinctrl driver");
-MODULE_LICENSE("GPL v2");
-MODULE_DEVICE_TABLE(of, tegra_pinctrl_of_match);
+EXPORT_SYMBOL_GPL(tegra_pinctrl_remove);
diff --git a/drivers/pinctrl/pinctrl-tegra.h b/drivers/pinctrl/pinctrl-tegra.h
index 782c795326ef..705c007a38cc 100644
--- a/drivers/pinctrl/pinctrl-tegra.h
+++ b/drivers/pinctrl/pinctrl-tegra.h
@@ -139,25 +139,8 @@ struct tegra_pinctrl_soc_data {
         unsigned ngroups;
 };
 
-/**
- * tegra_pinctrl_soc_initf() - Retrieve pin controller details for a SoC.
- * @soc_data:   This pointer must be updated to point at a struct containing
- *              details of the SoC.
- */
-typedef void (*tegra_pinctrl_soc_initf)(
-                        const struct tegra_pinctrl_soc_data **soc_data);
-
-/**
- * tegra20_pinctrl_init() - Retrieve pin controller details for Tegra20
- * @soc_data:   This pointer will be updated to point at a struct containing
- *              details of Tegra20's pin controller.
- */
-void tegra20_pinctrl_init(const struct tegra_pinctrl_soc_data **soc_data);
-/**
- * tegra30_pinctrl_init() - Retrieve pin controller details for Tegra20
- * @soc_data:   This pointer will be updated to point at a struct containing
- *              details of Tegra30's pin controller.
- */
-void tegra30_pinctrl_init(const struct tegra_pinctrl_soc_data **soc_data);
+int tegra_pinctrl_probe(struct platform_device *pdev,
+                        const struct tegra_pinctrl_soc_data *soc_data);
+int tegra_pinctrl_remove(struct platform_device *pdev);
 
 #endif
diff --git a/drivers/pinctrl/pinctrl-tegra20.c b/drivers/pinctrl/pinctrl-tegra20.c
index f69ff96aa292..a74f9a568536 100644
--- a/drivers/pinctrl/pinctrl-tegra20.c
+++ b/drivers/pinctrl/pinctrl-tegra20.c
@@ -1,7 +1,7 @@
 /*
  * Pinctrl data for the NVIDIA Tegra20 pinmux
  *
- * Copyright (c) 2011, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
  *
  * Derived from code:
  * Copyright (C) 2010 Google, Inc.
@@ -17,6 +17,8 @@
  * more details.
  */
 
+#include <linux/module.h>
+#include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/pinmux.h>
@@ -2854,7 +2856,39 @@ static const struct tegra_pinctrl_soc_data tegra20_pinctrl = {
         .ngroups = ARRAY_SIZE(tegra20_groups),
 };
 
-void __devinit tegra20_pinctrl_init(const struct tegra_pinctrl_soc_data **soc)
+static int __devinit tegra20_pinctrl_probe(struct platform_device *pdev)
 {
-        *soc = &tegra20_pinctrl;
+        return tegra_pinctrl_probe(pdev, &tegra20_pinctrl);
 }
+
+static struct of_device_id tegra20_pinctrl_of_match[] __devinitdata = {
+        { .compatible = "nvidia,tegra20-pinmux", },
+        { },
+};
+
+static struct platform_driver tegra20_pinctrl_driver = {
+        .driver = {
+                .name = "tegra20-pinctrl",
+                .owner = THIS_MODULE,
+                .of_match_table = tegra20_pinctrl_of_match,
+        },
+        .probe = tegra20_pinctrl_probe,
+        .remove = __devexit_p(tegra_pinctrl_remove),
+};
+
+static int __init tegra20_pinctrl_init(void)
+{
+        return platform_driver_register(&tegra20_pinctrl_driver);
+}
+arch_initcall(tegra20_pinctrl_init);
+
+static void __exit tegra20_pinctrl_exit(void)
+{
+        platform_driver_unregister(&tegra20_pinctrl_driver);
+}
+module_exit(tegra20_pinctrl_exit);
+
+MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
+MODULE_DESCRIPTION("NVIDIA Tegra20 pinctrl driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, tegra20_pinctrl_of_match);
diff --git a/drivers/pinctrl/pinctrl-tegra30.c b/drivers/pinctrl/pinctrl-tegra30.c
index 4d7571d4a431..0386fdf0da16 100644
--- a/drivers/pinctrl/pinctrl-tegra30.c
+++ b/drivers/pinctrl/pinctrl-tegra30.c
@@ -1,7 +1,7 @@
 /*
  * Pinctrl data for the NVIDIA Tegra30 pinmux
  *
- * Copyright (c) 2011, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -13,6 +13,8 @@
  * more details.
  */
 
+#include <linux/module.h>
+#include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/pinmux.h>
@@ -3720,7 +3722,39 @@ static const struct tegra_pinctrl_soc_data tegra30_pinctrl = {
         .ngroups = ARRAY_SIZE(tegra30_groups),
 };
 
-void __devinit tegra30_pinctrl_init(const struct tegra_pinctrl_soc_data **soc)
+static int __devinit tegra30_pinctrl_probe(struct platform_device *pdev)
 {
-        *soc = &tegra30_pinctrl;
+        return tegra_pinctrl_probe(pdev, &tegra30_pinctrl);
 }
+
+static struct of_device_id tegra30_pinctrl_of_match[] __devinitdata = {
+        { .compatible = "nvidia,tegra30-pinmux", },
+        { },
+};
+
+static struct platform_driver tegra30_pinctrl_driver = {
+        .driver = {
+                .name = "tegra30-pinctrl",
+                .owner = THIS_MODULE,
+                .of_match_table = tegra30_pinctrl_of_match,
+        },
+        .probe = tegra30_pinctrl_probe,
+        .remove = __devexit_p(tegra_pinctrl_remove),
+};
+
+static int __init tegra30_pinctrl_init(void)
+{
+        return platform_driver_register(&tegra30_pinctrl_driver);
+}
+arch_initcall(tegra30_pinctrl_init);
+
+static void __exit tegra30_pinctrl_exit(void)
+{
+        platform_driver_unregister(&tegra30_pinctrl_driver);
+}
+module_exit(tegra30_pinctrl_exit);
+
+MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
+MODULE_DESCRIPTION("NVIDIA Tegra30 pinctrl driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, tegra30_pinctrl_of_match);
diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c
index 26eb8ccd72d5..05d029911be6 100644
--- a/drivers/pinctrl/pinctrl-u300.c
+++ b/drivers/pinctrl/pinctrl-u300.c
@@ -836,18 +836,14 @@ static const struct u300_pin_group u300_pin_groups[] = {
         },
 };
 
-static int u300_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
+static int u300_get_groups_count(struct pinctrl_dev *pctldev)
 {
-        if (selector >= ARRAY_SIZE(u300_pin_groups))
-                return -EINVAL;
-        return 0;
+        return ARRAY_SIZE(u300_pin_groups);
 }
 
 static const char *u300_get_group_name(struct pinctrl_dev *pctldev,
                                        unsigned selector)
 {
-        if (selector >= ARRAY_SIZE(u300_pin_groups))
-                return NULL;
         return u300_pin_groups[selector].name;
 }
 
@@ -855,8 +851,6 @@ static int u300_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
                                const unsigned **pins,
                                unsigned *num_pins)
 {
-        if (selector >= ARRAY_SIZE(u300_pin_groups))
-                return -EINVAL;
         *pins = u300_pin_groups[selector].pins;
         *num_pins = u300_pin_groups[selector].num_pins;
         return 0;
@@ -869,7 +863,7 @@ static void u300_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 }
 
 static struct pinctrl_ops u300_pctrl_ops = {
-        .list_groups = u300_list_groups,
+        .get_groups_count = u300_get_groups_count,
         .get_group_name = u300_get_group_name,
         .get_group_pins = u300_get_group_pins,
         .pin_dbg_show = u300_pin_dbg_show,
@@ -991,11 +985,9 @@ static void u300_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
         u300_pmx_endisable(upmx, selector, false);
 }
 
-static int u300_pmx_list_funcs(struct pinctrl_dev *pctldev, unsigned selector)
+static int u300_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 {
-        if (selector >= ARRAY_SIZE(u300_pmx_functions))
-                return -EINVAL;
-        return 0;
+        return ARRAY_SIZE(u300_pmx_functions);
 }
 
 static const char *u300_pmx_get_func_name(struct pinctrl_dev *pctldev,
@@ -1014,7 +1006,7 @@ static int u300_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
 }
 
 static struct pinmux_ops u300_pmx_ops = {
-        .list_functions = u300_pmx_list_funcs,
+        .get_functions_count = u300_pmx_get_funcs_count,
         .get_function_name = u300_pmx_get_func_name,
         .get_function_groups = u300_pmx_get_groups,
         .enable = u300_pmx_enable,
diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c
index 4e62783a573a..fa0357bd88ff 100644
--- a/drivers/pinctrl/pinmux.c
+++ b/drivers/pinctrl/pinmux.c
@@ -33,10 +33,12 @@
 int pinmux_check_ops(struct pinctrl_dev *pctldev)
 {
         const struct pinmux_ops *ops = pctldev->desc->pmxops;
+        unsigned nfuncs;
         unsigned selector = 0;
 
         /* Check that we implement required operations */
-        if (!ops->list_functions ||
+        if (!ops ||
+            !ops->get_functions_count ||
             !ops->get_function_name ||
             !ops->get_function_groups ||
             !ops->enable ||
@@ -44,11 +46,12 @@ int pinmux_check_ops(struct pinctrl_dev *pctldev)
                 return -EINVAL;
 
         /* Check that all functions registered have names */
-        while (ops->list_functions(pctldev, selector) >= 0) {
+        nfuncs = ops->get_functions_count(pctldev);
+        while (selector < nfuncs) {
                 const char *fname = ops->get_function_name(pctldev,
                                                            selector);
                 if (!fname) {
-                        pr_err("pinmux ops has no name for function%u\n",
+                        dev_err(pctldev->dev, "pinmux ops has no name for function%u\n",
                                 selector);
                         return -EINVAL;
                 }
@@ -85,8 +88,6 @@ static int pin_request(struct pinctrl_dev *pctldev,
         const struct pinmux_ops *ops = pctldev->desc->pmxops;
         int status = -EINVAL;
 
-        dev_dbg(pctldev->dev, "request pin %d for %s\n", pin, owner);
-
         desc = pin_desc_get(pctldev, pin);
         if (desc == NULL) {
                 dev_err(pctldev->dev,
@@ -94,6 +95,9 @@ static int pin_request(struct pinctrl_dev *pctldev,
                 goto out;
         }
 
+        dev_dbg(pctldev->dev, "request pin %d (%s) for %s\n",
+                pin, desc->name, owner);
+
         if (gpio_range) {
                 /* There's no need to support multiple GPIO requests */
                 if (desc->gpio_owner) {
@@ -287,10 +291,11 @@ static int pinmux_func_name_to_selector(struct pinctrl_dev *pctldev,
                                         const char *function)
 {
         const struct pinmux_ops *ops = pctldev->desc->pmxops;
+        unsigned nfuncs = ops->get_functions_count(pctldev);
         unsigned selector = 0;
 
         /* See if this pctldev has this function */
-        while (ops->list_functions(pctldev, selector) >= 0) {
+        while (selector < nfuncs) {
                 const char *fname = ops->get_function_name(pctldev,
                                                            selector);
 
@@ -319,6 +324,11 @@ int pinmux_map_to_setting(struct pinctrl_map const *map,
         const unsigned *pins;
         unsigned num_pins;
 
+        if (!pmxops) {
+                dev_err(pctldev->dev, "does not support mux function\n");
+                return -EINVAL;
+        }
+
         setting->data.mux.func =
                 pinmux_func_name_to_selector(pctldev, map->data.mux.function);
         if (setting->data.mux.func < 0)
@@ -477,11 +487,15 @@ static int pinmux_functions_show(struct seq_file *s, void *what)
 {
         struct pinctrl_dev *pctldev = s->private;
         const struct pinmux_ops *pmxops = pctldev->desc->pmxops;
+        unsigned nfuncs;
         unsigned func_selector = 0;
 
-        mutex_lock(&pinctrl_mutex);
+        if (!pmxops)
+                return 0;
 
-        while (pmxops->list_functions(pctldev, func_selector) >= 0) {
+        mutex_lock(&pinctrl_mutex);
+        nfuncs = pmxops->get_functions_count(pctldev);
+        while (func_selector < nfuncs) {
                 const char *func = pmxops->get_function_name(pctldev,
                                                           func_selector);
                 const char * const *groups;
@@ -515,6 +529,9 @@ static int pinmux_pins_show(struct seq_file *s, void *what)
         const struct pinmux_ops *pmxops = pctldev->desc->pmxops;
         unsigned i, pin;
 
+        if (!pmxops)
+                return 0;
+
         seq_puts(s, "Pinmux settings per pin\n");
         seq_puts(s, "Format: pin (name): mux_owner gpio_owner hog?\n");
 
diff --git a/drivers/pinctrl/pinmux.h b/drivers/pinctrl/pinmux.h
index 6fc47003e95d..d1a98b1c9fce 100644
--- a/drivers/pinctrl/pinmux.h
+++ b/drivers/pinctrl/pinmux.h
@@ -31,12 +31,6 @@ void pinmux_free_setting(struct pinctrl_setting const *setting);
 int pinmux_enable_setting(struct pinctrl_setting const *setting);
 void pinmux_disable_setting(struct pinctrl_setting const *setting);
 
-void pinmux_show_map(struct seq_file *s, struct pinctrl_map const *map);
-void pinmux_show_setting(struct seq_file *s,
-                         struct pinctrl_setting const *setting);
-void pinmux_init_device_debugfs(struct dentry *devroot,
-                                struct pinctrl_dev *pctldev);
-
 #else
 
 static inline int pinmux_check_ops(struct pinctrl_dev *pctldev)
@@ -89,6 +83,18 @@ static inline void pinmux_disable_setting(
 {
 }
 
+#endif
+
+#if defined(CONFIG_PINMUX) && defined(CONFIG_DEBUG_FS)
+
+void pinmux_show_map(struct seq_file *s, struct pinctrl_map const *map);
+void pinmux_show_setting(struct seq_file *s,
+                         struct pinctrl_setting const *setting);
+void pinmux_init_device_debugfs(struct dentry *devroot,
+                                struct pinctrl_dev *pctldev);
+
+#else
+
 static inline void pinmux_show_map(struct seq_file *s,
                                    struct pinctrl_map const *map)
 {
diff --git a/drivers/pinctrl/spear/Kconfig b/drivers/pinctrl/spear/Kconfig
new file mode 100644
index 000000000000..6a2596b4f359
--- /dev/null
+++ b/drivers/pinctrl/spear/Kconfig
@@ -0,0 +1,34 @@
+#
+# ST Microelectronics SPEAr PINCTRL drivers
+#
+
+if PLAT_SPEAR
+
+config PINCTRL_SPEAR
+        bool
+        depends on OF
+        select PINMUX
+        help
+          This enables pin control drivers for SPEAr Platform
+
+config PINCTRL_SPEAR3XX
+        bool
+        depends on ARCH_SPEAR3XX
+        select PINCTRL_SPEAR
+
+config PINCTRL_SPEAR300
+        bool "ST Microelectronics SPEAr300 SoC pin controller driver"
+        depends on MACH_SPEAR300
+        select PINCTRL_SPEAR3XX
+
+config PINCTRL_SPEAR310
+        bool "ST Microelectronics SPEAr310 SoC pin controller driver"
+        depends on MACH_SPEAR310
+        select PINCTRL_SPEAR3XX
+
+config PINCTRL_SPEAR320
+        bool "ST Microelectronics SPEAr320 SoC pin controller driver"
+        depends on MACH_SPEAR320
+        select PINCTRL_SPEAR3XX
+
+endif
diff --git a/drivers/pinctrl/spear/Makefile b/drivers/pinctrl/spear/Makefile
new file mode 100644
index 000000000000..15dcb85da22d
--- /dev/null
+++ b/drivers/pinctrl/spear/Makefile
@@ -0,0 +1,7 @@
+# SPEAr pinmux support
+
+obj-$(CONFIG_PINCTRL_SPEAR)     += pinctrl-spear.o
+obj-$(CONFIG_PINCTRL_SPEAR3XX)  += pinctrl-spear3xx.o
+obj-$(CONFIG_PINCTRL_SPEAR300)  += pinctrl-spear300.o
+obj-$(CONFIG_PINCTRL_SPEAR310)  += pinctrl-spear310.o
+obj-$(CONFIG_PINCTRL_SPEAR320)  += pinctrl-spear320.o
diff --git a/drivers/pinctrl/spear/pinctrl-spear.c b/drivers/pinctrl/spear/pinctrl-spear.c
new file mode 100644
index 000000000000..5ae50aadf885
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear.c
@@ -0,0 +1,354 @@
+/*
+ * Driver for the ST Microelectronics SPEAr pinmux
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * Inspired from:
+ * - U300 Pinctl drivers
+ * - Tegra Pinctl drivers
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "pinctrl-spear.h"
+
+#define DRIVER_NAME "spear-pinmux"
+
+static inline u32 pmx_readl(struct spear_pmx *pmx, u32 reg)
+{
+        return readl_relaxed(pmx->vbase + reg);
+}
+
+static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg)
+{
+        writel_relaxed(val, pmx->vbase + reg);
+}
+
+static int set_mode(struct spear_pmx *pmx, int mode)
+{
+        struct spear_pmx_mode *pmx_mode = NULL;
+        int i;
+        u32 val;
+
+        if (!pmx->machdata->pmx_modes || !pmx->machdata->npmx_modes)
+                return -EINVAL;
+
+        for (i = 0; i < pmx->machdata->npmx_modes; i++) {
+                if (pmx->machdata->pmx_modes[i]->mode == (1 << mode)) {
+                        pmx_mode = pmx->machdata->pmx_modes[i];
+                        break;
+                }
+        }
+
+        if (!pmx_mode)
+                return -EINVAL;
+
+        val = pmx_readl(pmx, pmx_mode->reg);
+        val &= ~pmx_mode->mask;
+        val |= pmx_mode->val;
+        pmx_writel(pmx, val, pmx_mode->reg);
+
+        pmx->machdata->mode = pmx_mode->mode;
+        dev_info(pmx->dev, "Configured Mode: %s with id: %x\n\n",
+                        pmx_mode->name ? pmx_mode->name : "no_name",
+                        pmx_mode->reg);
+
+        return 0;
+}
+
+void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg)
+{
+        struct spear_pingroup *pgroup;
+        struct spear_modemux *modemux;
+        int i, j, group;
+
+        for (group = 0; group < machdata->ngroups; group++) {
+                pgroup = machdata->groups[group];
+
+                for (i = 0; i < pgroup->nmodemuxs; i++) {
+                        modemux = &pgroup->modemuxs[i];
+
+                        for (j = 0; j < modemux->nmuxregs; j++)
+                                if (modemux->muxregs[j].reg == 0xFFFF)
+                                        modemux->muxregs[j].reg = reg;
+                }
+        }
+}
+
+static int spear_pinctrl_get_groups_cnt(struct pinctrl_dev *pctldev)
+{
+        struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+
+        return pmx->machdata->ngroups;
+}
+
+static const char *spear_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
+                unsigned group)
+{
+        struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+
+        return pmx->machdata->groups[group]->name;
+}
+
+static int spear_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
+                unsigned group, const unsigned **pins, unsigned *num_pins)
+{
+        struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+
+        *pins = pmx->machdata->groups[group]->pins;
+        *num_pins = pmx->machdata->groups[group]->npins;
+
+        return 0;
+}
+
+static void spear_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
+                struct seq_file *s, unsigned offset)
+{
+        seq_printf(s, " " DRIVER_NAME);
+}
+
+int spear_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
+                                 struct device_node *np_config,
+                                 struct pinctrl_map **map, unsigned *num_maps)
+{
+        struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+        struct device_node *np;
+        struct property *prop;
+        const char *function, *group;
+        int ret, index = 0, count = 0;
+
+        /* calculate number of maps required */
+        for_each_child_of_node(np_config, np) {
+                ret = of_property_read_string(np, "st,function", &function);
+                if (ret < 0)
+                        return ret;
+
+                ret = of_property_count_strings(np, "st,pins");
+                if (ret < 0)
+                        return ret;
+
+                count += ret;
+        }
+
+        if (!count) {
+                dev_err(pmx->dev, "No child nodes passed via DT\n");
+                return -ENODEV;
+        }
+
+        *map = kzalloc(sizeof(**map) * count, GFP_KERNEL);
+        if (!*map)
+                return -ENOMEM;
+
+        for_each_child_of_node(np_config, np) {
+                of_property_read_string(np, "st,function", &function);
+                of_property_for_each_string(np, "st,pins", prop, group) {
+                        (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
+                        (*map)[index].data.mux.group = group;
+                        (*map)[index].data.mux.function = function;
+                        index++;
+                }
+        }
+
+        *num_maps = count;
+
+        return 0;
+}
+
+void spear_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
+                struct pinctrl_map *map, unsigned num_maps)
+{
+        kfree(map);
+}
+
+static struct pinctrl_ops spear_pinctrl_ops = {
+        .get_groups_count = spear_pinctrl_get_groups_cnt,
+        .get_group_name = spear_pinctrl_get_group_name,
+        .get_group_pins = spear_pinctrl_get_group_pins,
+        .pin_dbg_show = spear_pinctrl_pin_dbg_show,
+        .dt_node_to_map = spear_pinctrl_dt_node_to_map,
+        .dt_free_map = spear_pinctrl_dt_free_map,
+};
+
+static int spear_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+        struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+
+        return pmx->machdata->nfunctions;
+}
+
+static const char *spear_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
+                unsigned function)
+{
+        struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+
+        return pmx->machdata->functions[function]->name;
+}
+
+static int spear_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
+                unsigned function, const char *const **groups,
+                unsigned * const ngroups)
+{
+        struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+
+        *groups = pmx->machdata->functions[function]->groups;
+        *ngroups = pmx->machdata->functions[function]->ngroups;
+
+        return 0;
+}
+
+static int spear_pinctrl_endisable(struct pinctrl_dev *pctldev,
+                unsigned function, unsigned group, bool enable)
+{
+        struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+        const struct spear_pingroup *pgroup;
+        const struct spear_modemux *modemux;
+        struct spear_muxreg *muxreg;
+        u32 val, temp;
+        int i, j;
+        bool found = false;
+
+        pgroup = pmx->machdata->groups[group];
+
+        for (i = 0; i < pgroup->nmodemuxs; i++) {
+                modemux = &pgroup->modemuxs[i];
+
+                /* SoC have any modes */
+                if (pmx->machdata->modes_supported) {
+                        if (!(pmx->machdata->mode & modemux->modes))
+                                continue;
+                }
+
+                found = true;
+                for (j = 0; j < modemux->nmuxregs; j++) {
+                        muxreg = &modemux->muxregs[j];
+
+                        val = pmx_readl(pmx, muxreg->reg);
+                        val &= ~muxreg->mask;
+
+                        if (enable)
+                                temp = muxreg->val;
+                        else
+                                temp = ~muxreg->val;
+
+                        val |= temp;
+                        pmx_writel(pmx, val, muxreg->reg);
+                }
+        }
+
+        if (!found) {
+                dev_err(pmx->dev, "pinmux group: %s not supported\n",
+                                pgroup->name);
+                return -ENODEV;
+        }
+
+        return 0;
+}
+
+static int spear_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
+                unsigned group)
+{
+        return spear_pinctrl_endisable(pctldev, function, group, true);
+}
+
+static void spear_pinctrl_disable(struct pinctrl_dev *pctldev,
+                unsigned function, unsigned group)
+{
+        spear_pinctrl_endisable(pctldev, function, group, false);
+}
+
+static struct pinmux_ops spear_pinmux_ops = {
+        .get_functions_count = spear_pinctrl_get_funcs_count,
+        .get_function_name = spear_pinctrl_get_func_name,
+        .get_function_groups = spear_pinctrl_get_func_groups,
+        .enable = spear_pinctrl_enable,
+        .disable = spear_pinctrl_disable,
+};
+
+static struct pinctrl_desc spear_pinctrl_desc = {
+        .name = DRIVER_NAME,
+        .pctlops = &spear_pinctrl_ops,
+        .pmxops = &spear_pinmux_ops,
+        .owner = THIS_MODULE,
+};
+
+int __devinit spear_pinctrl_probe(struct platform_device *pdev,
+                struct spear_pinctrl_machdata *machdata)
+{
+        struct device_node *np = pdev->dev.of_node;
+        struct resource *res;
+        struct spear_pmx *pmx;
+
+        if (!machdata)
+                return -ENODEV;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res)
+                return -EINVAL;
+
+        pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
+        if (!pmx) {
+                dev_err(&pdev->dev, "Can't alloc spear_pmx\n");
+                return -ENOMEM;
+        }
+
+        pmx->vbase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+        if (!pmx->vbase) {
+                dev_err(&pdev->dev, "Couldn't ioremap at index 0\n");
+                return -ENODEV;
+        }
+
+        pmx->dev = &pdev->dev;
+        pmx->machdata = machdata;
+
+        /* configure mode, if supported by SoC */
+        if (machdata->modes_supported) {
+                int mode = 0;
+
+                if (of_property_read_u32(np, "st,pinmux-mode", &mode)) {
+                        dev_err(&pdev->dev, "OF: pinmux mode not passed\n");
+                        return -EINVAL;
+                }
+
+                if (set_mode(pmx, mode)) {
+                        dev_err(&pdev->dev, "OF: Couldn't configure mode: %x\n",
+                                        mode);
+                        return -EINVAL;
+                }
+        }
+
+        platform_set_drvdata(pdev, pmx);
+
+        spear_pinctrl_desc.pins = machdata->pins;
+        spear_pinctrl_desc.npins = machdata->npins;
+
+        pmx->pctl = pinctrl_register(&spear_pinctrl_desc, &pdev->dev, pmx);
+        if (IS_ERR(pmx->pctl)) {
+                dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
+                return PTR_ERR(pmx->pctl);
+        }
+
+        return 0;
+}
+
+int __devexit spear_pinctrl_remove(struct platform_device *pdev)
+{
+        struct spear_pmx *pmx = platform_get_drvdata(pdev);
+
+        pinctrl_unregister(pmx->pctl);
+
+        return 0;
+}
diff --git a/drivers/pinctrl/spear/pinctrl-spear.h b/drivers/pinctrl/spear/pinctrl-spear.h
new file mode 100644
index 000000000000..47a6b5b72f90
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear.h
@@ -0,0 +1,142 @@
+/*
+ * Driver header file for the ST Microelectronics SPEAr pinmux
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PINMUX_SPEAR_H__
+#define __PINMUX_SPEAR_H__
+
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/types.h>
+
+struct platform_device;
+struct device;
+
+/**
+ * struct spear_pmx_mode - SPEAr pmx mode
+ * @name: name of pmx mode
+ * @mode: mode id
+ * @reg: register for configuring this mode
+ * @mask: mask of this mode in reg
+ * @val: val to be configured at reg after doing (val & mask)
+ */
+struct spear_pmx_mode {
+        const char *const name;
+        u16 mode;
+        u16 reg;
+        u16 mask;
+        u32 val;
+};
+
+/**
+ * struct spear_muxreg - SPEAr mux reg configuration
+ * @reg: register offset
+ * @mask: mask bits
+ * @val: val to be written on mask bits
+ */
+struct spear_muxreg {
+        u16 reg;
+        u32 mask;
+        u32 val;
+};
+
+/**
+ * struct spear_modemux - SPEAr mode mux configuration
+ * @modes: mode ids supported by this group of muxregs
+ * @nmuxregs: number of muxreg configurations to be done for modes
+ * @muxregs: array of muxreg configurations to be done for modes
+ */
+struct spear_modemux {
+        u16 modes;
+        u8 nmuxregs;
+        struct spear_muxreg *muxregs;
+};
+
+/**
+ * struct spear_pingroup - SPEAr pin group configurations
+ * @name: name of pin group
+ * @pins: array containing pin numbers
+ * @npins: size of pins array
+ * @modemuxs: array of modemux configurations for this pin group
+ * @nmodemuxs: size of array modemuxs
+ *
+ * A representation of a group of pins in the SPEAr pin controller. Each group
+ * allows some parameter or parameters to be configured.
+ */
+struct spear_pingroup {
+        const char *name;
+        const unsigned *pins;
+        unsigned npins;
+        struct spear_modemux *modemuxs;
+        unsigned nmodemuxs;
+};
+
+/**
+ * struct spear_function - SPEAr pinctrl mux function
+ * @name: The name of the function, exported to pinctrl core.
+ * @groups: An array of pin groups that may select this function.
+ * @ngroups: The number of entries in @groups.
+ */
+struct spear_function {
+        const char *name;
+        const char *const *groups;
+        unsigned ngroups;
+};
+
+/**
+ * struct spear_pinctrl_machdata - SPEAr pin controller machine driver
+ *      configuration
+ * @pins: An array describing all pins the pin controller affects.
+ *      All pins which are also GPIOs must be listed first within the *array,
+ *      and be numbered identically to the GPIO controller's *numbering.
+ * @npins: The numbmer of entries in @pins.
+ * @functions: An array describing all mux functions the SoC supports.
+ * @nfunctions: The numbmer of entries in @functions.
+ * @groups: An array describing all pin groups the pin SoC supports.
+ * @ngroups: The numbmer of entries in @groups.
+ *
+ * @modes_supported: Does SoC support modes
+ * @mode: mode configured from probe
+ * @pmx_modes: array of modes supported by SoC
+ * @npmx_modes: number of entries in pmx_modes.
+ */
+struct spear_pinctrl_machdata {
+        const struct pinctrl_pin_desc *pins;
+        unsigned npins;
+        struct spear_function **functions;
+        unsigned nfunctions;
+        struct spear_pingroup **groups;
+        unsigned ngroups;
+
+        bool modes_supported;
+        u16 mode;
+        struct spear_pmx_mode **pmx_modes;
+        unsigned npmx_modes;
+};
+
+/**
+ * struct spear_pmx - SPEAr pinctrl mux
+ * @dev: pointer to struct dev of platform_device registered
+ * @pctl: pointer to struct pinctrl_dev
+ * @machdata: pointer to SoC or machine specific structure
+ * @vbase: virtual base address of pinmux controller
+ */
+struct spear_pmx {
+        struct device *dev;
+        struct pinctrl_dev *pctl;
+        struct spear_pinctrl_machdata *machdata;
+        void __iomem *vbase;
+};
+
+/* exported routines */
+void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg);
+int __devinit spear_pinctrl_probe(struct platform_device *pdev,
+                struct spear_pinctrl_machdata *machdata);
+int __devexit spear_pinctrl_remove(struct platform_device *pdev);
+#endif /* __PINMUX_SPEAR_H__ */
diff --git a/drivers/pinctrl/spear/pinctrl-spear300.c b/drivers/pinctrl/spear/pinctrl-spear300.c
new file mode 100644
index 000000000000..9c82a35e4e78
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear300.c
@@ -0,0 +1,708 @@
+/*
+ * Driver for the ST Microelectronics SPEAr300 pinmux
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include "pinctrl-spear3xx.h"
+
+#define DRIVER_NAME "spear300-pinmux"
+
+/* addresses */
+#define PMX_CONFIG_REG                  0x00
+#define MODE_CONFIG_REG                 0x04
+
+/* modes */
+#define NAND_MODE                       (1 << 0)
+#define NOR_MODE                        (1 << 1)
+#define PHOTO_FRAME_MODE                (1 << 2)
+#define LEND_IP_PHONE_MODE              (1 << 3)
+#define HEND_IP_PHONE_MODE              (1 << 4)
+#define LEND_WIFI_PHONE_MODE            (1 << 5)
+#define HEND_WIFI_PHONE_MODE            (1 << 6)
+#define ATA_PABX_WI2S_MODE              (1 << 7)
+#define ATA_PABX_I2S_MODE               (1 << 8)
+#define CAML_LCDW_MODE                  (1 << 9)
+#define CAMU_LCD_MODE                   (1 << 10)
+#define CAMU_WLCD_MODE                  (1 << 11)
+#define CAML_LCD_MODE                   (1 << 12)
+
+static struct spear_pmx_mode pmx_mode_nand = {
+        .name = "nand",
+        .mode = NAND_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x0000000F,
+        .val = 0x00,
+};
+
+static struct spear_pmx_mode pmx_mode_nor = {
+        .name = "nor",
+        .mode = NOR_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x0000000F,
+        .val = 0x01,
+};
+
+static struct spear_pmx_mode pmx_mode_photo_frame = {
+        .name = "photo frame mode",
+        .mode = PHOTO_FRAME_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x0000000F,
+        .val = 0x02,
+};
+
+static struct spear_pmx_mode pmx_mode_lend_ip_phone = {
+        .name = "lend ip phone mode",
+        .mode = LEND_IP_PHONE_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x0000000F,
+        .val = 0x03,
+};
+
+static struct spear_pmx_mode pmx_mode_hend_ip_phone = {
+        .name = "hend ip phone mode",
+        .mode = HEND_IP_PHONE_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x0000000F,
+        .val = 0x04,
+};
+
+static struct spear_pmx_mode pmx_mode_lend_wifi_phone = {
+        .name = "lend wifi phone mode",
+        .mode = LEND_WIFI_PHONE_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x0000000F,
+        .val = 0x05,
+};
+
+static struct spear_pmx_mode pmx_mode_hend_wifi_phone = {
+        .name = "hend wifi phone mode",
+        .mode = HEND_WIFI_PHONE_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x0000000F,
+        .val = 0x06,
+};
+
+static struct spear_pmx_mode pmx_mode_ata_pabx_wi2s = {
+        .name = "ata pabx wi2s mode",
+        .mode = ATA_PABX_WI2S_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x0000000F,
+        .val = 0x07,
+};
+
+static struct spear_pmx_mode pmx_mode_ata_pabx_i2s = {
+        .name = "ata pabx i2s mode",
+        .mode = ATA_PABX_I2S_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x0000000F,
+        .val = 0x08,
+};
+
+static struct spear_pmx_mode pmx_mode_caml_lcdw = {
+        .name = "caml lcdw mode",
+        .mode = CAML_LCDW_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x0000000F,
+        .val = 0x0C,
+};
+
+static struct spear_pmx_mode pmx_mode_camu_lcd = {
+        .name = "camu lcd mode",
+        .mode = CAMU_LCD_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x0000000F,
+        .val = 0x0D,
+};
+
+static struct spear_pmx_mode pmx_mode_camu_wlcd = {
+        .name = "camu wlcd mode",
+        .mode = CAMU_WLCD_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x0000000F,
+        .val = 0xE,
+};
+
+static struct spear_pmx_mode pmx_mode_caml_lcd = {
+        .name = "caml lcd mode",
+        .mode = CAML_LCD_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x0000000F,
+        .val = 0x0F,
+};
+
+static struct spear_pmx_mode *spear300_pmx_modes[] = {
+        &pmx_mode_nand,
+        &pmx_mode_nor,
+        &pmx_mode_photo_frame,
+        &pmx_mode_lend_ip_phone,
+        &pmx_mode_hend_ip_phone,
+        &pmx_mode_lend_wifi_phone,
+        &pmx_mode_hend_wifi_phone,
+        &pmx_mode_ata_pabx_wi2s,
+        &pmx_mode_ata_pabx_i2s,
+        &pmx_mode_caml_lcdw,
+        &pmx_mode_camu_lcd,
+        &pmx_mode_camu_wlcd,
+        &pmx_mode_caml_lcd,
+};
+
+/* fsmc_2chips_pins */
+static const unsigned fsmc_2chips_pins[] = { 1, 97 };
+static struct spear_muxreg fsmc_2chips_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_FIRDA_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux fsmc_2chips_modemux[] = {
+        {
+                .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
+                        ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
+                .muxregs = fsmc_2chips_muxreg,
+                .nmuxregs = ARRAY_SIZE(fsmc_2chips_muxreg),
+        },
+};
+
+static struct spear_pingroup fsmc_2chips_pingroup = {
+        .name = "fsmc_2chips_grp",
+        .pins = fsmc_2chips_pins,
+        .npins = ARRAY_SIZE(fsmc_2chips_pins),
+        .modemuxs = fsmc_2chips_modemux,
+        .nmodemuxs = ARRAY_SIZE(fsmc_2chips_modemux),
+};
+
+/* fsmc_4chips_pins */
+static const unsigned fsmc_4chips_pins[] = { 1, 2, 3, 97 };
+static struct spear_muxreg fsmc_4chips_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux fsmc_4chips_modemux[] = {
+        {
+                .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
+                        ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
+                .muxregs = fsmc_4chips_muxreg,
+                .nmuxregs = ARRAY_SIZE(fsmc_4chips_muxreg),
+        },
+};
+
+static struct spear_pingroup fsmc_4chips_pingroup = {
+        .name = "fsmc_4chips_grp",
+        .pins = fsmc_4chips_pins,
+        .npins = ARRAY_SIZE(fsmc_4chips_pins),
+        .modemuxs = fsmc_4chips_modemux,
+        .nmodemuxs = ARRAY_SIZE(fsmc_4chips_modemux),
+};
+
+static const char *const fsmc_grps[] = { "fsmc_2chips_grp", "fsmc_4chips_grp"
+};
+static struct spear_function fsmc_function = {
+        .name = "fsmc",
+        .groups = fsmc_grps,
+        .ngroups = ARRAY_SIZE(fsmc_grps),
+};
+
+/* clcd_lcdmode_pins */
+static const unsigned clcd_lcdmode_pins[] = { 49, 50 };
+static struct spear_muxreg clcd_lcdmode_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux clcd_lcdmode_modemux[] = {
+        {
+                .modes = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
+                        CAMU_LCD_MODE | CAML_LCD_MODE,
+                .muxregs = clcd_lcdmode_muxreg,
+                .nmuxregs = ARRAY_SIZE(clcd_lcdmode_muxreg),
+        },
+};
+
+static struct spear_pingroup clcd_lcdmode_pingroup = {
+        .name = "clcd_lcdmode_grp",
+        .pins = clcd_lcdmode_pins,
+        .npins = ARRAY_SIZE(clcd_lcdmode_pins),
+        .modemuxs = clcd_lcdmode_modemux,
+        .nmodemuxs = ARRAY_SIZE(clcd_lcdmode_modemux),
+};
+
+/* clcd_pfmode_pins */
+static const unsigned clcd_pfmode_pins[] = { 47, 48, 49, 50 };
+static struct spear_muxreg clcd_pfmode_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_TIMER_2_3_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux clcd_pfmode_modemux[] = {
+        {
+                .modes = PHOTO_FRAME_MODE,
+                .muxregs = clcd_pfmode_muxreg,
+                .nmuxregs = ARRAY_SIZE(clcd_pfmode_muxreg),
+        },
+};
+
+static struct spear_pingroup clcd_pfmode_pingroup = {
+        .name = "clcd_pfmode_grp",
+        .pins = clcd_pfmode_pins,
+        .npins = ARRAY_SIZE(clcd_pfmode_pins),
+        .modemuxs = clcd_pfmode_modemux,
+        .nmodemuxs = ARRAY_SIZE(clcd_pfmode_modemux),
+};
+
+static const char *const clcd_grps[] = { "clcd_lcdmode_grp", "clcd_pfmode_grp"
+};
+static struct spear_function clcd_function = {
+        .name = "clcd",
+        .groups = clcd_grps,
+        .ngroups = ARRAY_SIZE(clcd_grps),
+};
+
+/* tdm_pins */
+static const unsigned tdm_pins[] = { 34, 35, 36, 37, 38 };
+static struct spear_muxreg tdm_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux tdm_modemux[] = {
+        {
+                .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
+                        HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
+                        | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
+                        | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
+                        | CAMU_WLCD_MODE | CAML_LCD_MODE,
+                .muxregs = tdm_muxreg,
+                .nmuxregs = ARRAY_SIZE(tdm_muxreg),
+        },
+};
+
+static struct spear_pingroup tdm_pingroup = {
+        .name = "tdm_grp",
+        .pins = tdm_pins,
+        .npins = ARRAY_SIZE(tdm_pins),
+        .modemuxs = tdm_modemux,
+        .nmodemuxs = ARRAY_SIZE(tdm_modemux),
+};
+
+static const char *const tdm_grps[] = { "tdm_grp" };
+static struct spear_function tdm_function = {
+        .name = "tdm",
+        .groups = tdm_grps,
+        .ngroups = ARRAY_SIZE(tdm_grps),
+};
+
+/* i2c_clk_pins */
+static const unsigned i2c_clk_pins[] = { 45, 46, 47, 48 };
+static struct spear_muxreg i2c_clk_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux i2c_clk_modemux[] = {
+        {
+                .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
+                        LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
+                        ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE | CAML_LCDW_MODE
+                        | CAML_LCD_MODE,
+                .muxregs = i2c_clk_muxreg,
+                .nmuxregs = ARRAY_SIZE(i2c_clk_muxreg),
+        },
+};
+
+static struct spear_pingroup i2c_clk_pingroup = {
+        .name = "i2c_clk_grp_grp",
+        .pins = i2c_clk_pins,
+        .npins = ARRAY_SIZE(i2c_clk_pins),
+        .modemuxs = i2c_clk_modemux,
+        .nmodemuxs = ARRAY_SIZE(i2c_clk_modemux),
+};
+
+static const char *const i2c_grps[] = { "i2c_clk_grp" };
+static struct spear_function i2c_function = {
+        .name = "i2c1",
+        .groups = i2c_grps,
+        .ngroups = ARRAY_SIZE(i2c_grps),
+};
+
+/* caml_pins */
+static const unsigned caml_pins[] = { 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 };
+static struct spear_muxreg caml_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_MII_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux caml_modemux[] = {
+        {
+                .modes = CAML_LCDW_MODE | CAML_LCD_MODE,
+                .muxregs = caml_muxreg,
+                .nmuxregs = ARRAY_SIZE(caml_muxreg),
+        },
+};
+
+static struct spear_pingroup caml_pingroup = {
+        .name = "caml_grp",
+        .pins = caml_pins,
+        .npins = ARRAY_SIZE(caml_pins),
+        .modemuxs = caml_modemux,
+        .nmodemuxs = ARRAY_SIZE(caml_modemux),
+};
+
+/* camu_pins */
+static const unsigned camu_pins[] = { 16, 17, 18, 19, 20, 21, 45, 46, 47, 48 };
+static struct spear_muxreg camu_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK | PMX_MII_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux camu_modemux[] = {
+        {
+                .modes = CAMU_LCD_MODE | CAMU_WLCD_MODE,
+                .muxregs = camu_muxreg,
+                .nmuxregs = ARRAY_SIZE(camu_muxreg),
+        },
+};
+
+static struct spear_pingroup camu_pingroup = {
+        .name = "camu_grp",
+        .pins = camu_pins,
+        .npins = ARRAY_SIZE(camu_pins),
+        .modemuxs = camu_modemux,
+        .nmodemuxs = ARRAY_SIZE(camu_modemux),
+};
+
+static const char *const cam_grps[] = { "caml_grp", "camu_grp" };
+static struct spear_function cam_function = {
+        .name = "cam",
+        .groups = cam_grps,
+        .ngroups = ARRAY_SIZE(cam_grps),
+};
+
+/* dac_pins */
+static const unsigned dac_pins[] = { 43, 44 };
+static struct spear_muxreg dac_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_TIMER_0_1_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux dac_modemux[] = {
+        {
+                .modes = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
+                        | CAMU_WLCD_MODE | CAML_LCD_MODE,
+                .muxregs = dac_muxreg,
+                .nmuxregs = ARRAY_SIZE(dac_muxreg),
+        },
+};
+
+static struct spear_pingroup dac_pingroup = {
+        .name = "dac_grp",
+        .pins = dac_pins,
+        .npins = ARRAY_SIZE(dac_pins),
+        .modemuxs = dac_modemux,
+        .nmodemuxs = ARRAY_SIZE(dac_modemux),
+};
+
+static const char *const dac_grps[] = { "dac_grp" };
+static struct spear_function dac_function = {
+        .name = "dac",
+        .groups = dac_grps,
+        .ngroups = ARRAY_SIZE(dac_grps),
+};
+
+/* i2s_pins */
+static const unsigned i2s_pins[] = { 39, 40, 41, 42 };
+static struct spear_muxreg i2s_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MODEM_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux i2s_modemux[] = {
+        {
+                .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
+                        | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
+                        ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
+                        | CAMU_WLCD_MODE | CAML_LCD_MODE,
+                .muxregs = i2s_muxreg,
+                .nmuxregs = ARRAY_SIZE(i2s_muxreg),
+        },
+};
+
+static struct spear_pingroup i2s_pingroup = {
+        .name = "i2s_grp",
+        .pins = i2s_pins,
+        .npins = ARRAY_SIZE(i2s_pins),
+        .modemuxs = i2s_modemux,
+        .nmodemuxs = ARRAY_SIZE(i2s_modemux),
+};
+
+static const char *const i2s_grps[] = { "i2s_grp" };
+static struct spear_function i2s_function = {
+        .name = "i2s",
+        .groups = i2s_grps,
+        .ngroups = ARRAY_SIZE(i2s_grps),
+};
+
+/* sdhci_4bit_pins */
+static const unsigned sdhci_4bit_pins[] = { 28, 29, 30, 31, 32, 33 };
+static struct spear_muxreg sdhci_4bit_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
+                        PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
+                        PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux sdhci_4bit_modemux[] = {
+        {
+                .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
+                        HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
+                        HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
+                        CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE,
+                .muxregs = sdhci_4bit_muxreg,
+                .nmuxregs = ARRAY_SIZE(sdhci_4bit_muxreg),
+        },
+};
+
+static struct spear_pingroup sdhci_4bit_pingroup = {
+        .name = "sdhci_4bit_grp",
+        .pins = sdhci_4bit_pins,
+        .npins = ARRAY_SIZE(sdhci_4bit_pins),
+        .modemuxs = sdhci_4bit_modemux,
+        .nmodemuxs = ARRAY_SIZE(sdhci_4bit_modemux),
+};
+
+/* sdhci_8bit_pins */
+static const unsigned sdhci_8bit_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32,
+        33 };
+static struct spear_muxreg sdhci_8bit_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
+                        PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
+                        PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux sdhci_8bit_modemux[] = {
+        {
+                .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
+                        HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
+                        HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
+                        CAMU_WLCD_MODE | CAML_LCD_MODE,
+                .muxregs = sdhci_8bit_muxreg,
+                .nmuxregs = ARRAY_SIZE(sdhci_8bit_muxreg),
+        },
+};
+
+static struct spear_pingroup sdhci_8bit_pingroup = {
+        .name = "sdhci_8bit_grp",
+        .pins = sdhci_8bit_pins,
+        .npins = ARRAY_SIZE(sdhci_8bit_pins),
+        .modemuxs = sdhci_8bit_modemux,
+        .nmodemuxs = ARRAY_SIZE(sdhci_8bit_modemux),
+};
+
+static const char *const sdhci_grps[] = { "sdhci_4bit_grp", "sdhci_8bit_grp" };
+static struct spear_function sdhci_function = {
+        .name = "sdhci",
+        .groups = sdhci_grps,
+        .ngroups = ARRAY_SIZE(sdhci_grps),
+};
+
+/* gpio1_0_to_3_pins */
+static const unsigned gpio1_0_to_3_pins[] = { 39, 40, 41, 42 };
+static struct spear_muxreg gpio1_0_to_3_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MODEM_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux gpio1_0_to_3_modemux[] = {
+        {
+                .modes = PHOTO_FRAME_MODE,
+                .muxregs = gpio1_0_to_3_muxreg,
+                .nmuxregs = ARRAY_SIZE(gpio1_0_to_3_muxreg),
+        },
+};
+
+static struct spear_pingroup gpio1_0_to_3_pingroup = {
+        .name = "gpio1_0_to_3_grp",
+        .pins = gpio1_0_to_3_pins,
+        .npins = ARRAY_SIZE(gpio1_0_to_3_pins),
+        .modemuxs = gpio1_0_to_3_modemux,
+        .nmodemuxs = ARRAY_SIZE(gpio1_0_to_3_modemux),
+};
+
+/* gpio1_4_to_7_pins */
+static const unsigned gpio1_4_to_7_pins[] = { 43, 44, 45, 46 };
+
+static struct spear_muxreg gpio1_4_to_7_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux gpio1_4_to_7_modemux[] = {
+        {
+                .modes = PHOTO_FRAME_MODE,
+                .muxregs = gpio1_4_to_7_muxreg,
+                .nmuxregs = ARRAY_SIZE(gpio1_4_to_7_muxreg),
+        },
+};
+
+static struct spear_pingroup gpio1_4_to_7_pingroup = {
+        .name = "gpio1_4_to_7_grp",
+        .pins = gpio1_4_to_7_pins,
+        .npins = ARRAY_SIZE(gpio1_4_to_7_pins),
+        .modemuxs = gpio1_4_to_7_modemux,
+        .nmodemuxs = ARRAY_SIZE(gpio1_4_to_7_modemux),
+};
+
+static const char *const gpio1_grps[] = { "gpio1_0_to_3_grp", "gpio1_4_to_7_grp"
+};
+static struct spear_function gpio1_function = {
+        .name = "gpio1",
+        .groups = gpio1_grps,
+        .ngroups = ARRAY_SIZE(gpio1_grps),
+};
+
+/* pingroups */
+static struct spear_pingroup *spear300_pingroups[] = {
+        SPEAR3XX_COMMON_PINGROUPS,
+        &fsmc_2chips_pingroup,
+        &fsmc_4chips_pingroup,
+        &clcd_lcdmode_pingroup,
+        &clcd_pfmode_pingroup,
+        &tdm_pingroup,
+        &i2c_clk_pingroup,
+        &caml_pingroup,
+        &camu_pingroup,
+        &dac_pingroup,
+        &i2s_pingroup,
+        &sdhci_4bit_pingroup,
+        &sdhci_8bit_pingroup,
+        &gpio1_0_to_3_pingroup,
+        &gpio1_4_to_7_pingroup,
+};
+
+/* functions */
+static struct spear_function *spear300_functions[] = {
+        SPEAR3XX_COMMON_FUNCTIONS,
+        &fsmc_function,
+        &clcd_function,
+        &tdm_function,
+        &i2c_function,
+        &cam_function,
+        &dac_function,
+        &i2s_function,
+        &sdhci_function,
+        &gpio1_function,
+};
+
+static struct of_device_id spear300_pinctrl_of_match[] __devinitdata = {
+        {
+                .compatible = "st,spear300-pinmux",
+        },
+        {},
+};
+
+static int __devinit spear300_pinctrl_probe(struct platform_device *pdev)
+{
+        int ret;
+
+        spear3xx_machdata.groups = spear300_pingroups;
+        spear3xx_machdata.ngroups = ARRAY_SIZE(spear300_pingroups);
+        spear3xx_machdata.functions = spear300_functions;
+        spear3xx_machdata.nfunctions = ARRAY_SIZE(spear300_functions);
+
+        spear3xx_machdata.modes_supported = true;
+        spear3xx_machdata.pmx_modes = spear300_pmx_modes;
+        spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear300_pmx_modes);
+
+        pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
+
+        ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
+        if (ret)
+                return ret;
+
+        return 0;
+}
+
+static int __devexit spear300_pinctrl_remove(struct platform_device *pdev)
+{
+        return spear_pinctrl_remove(pdev);
+}
+
+static struct platform_driver spear300_pinctrl_driver = {
+        .driver = {
+                .name = DRIVER_NAME,
+                .owner = THIS_MODULE,
+                .of_match_table = spear300_pinctrl_of_match,
+        },
+        .probe = spear300_pinctrl_probe,
+        .remove = __devexit_p(spear300_pinctrl_remove),
+};
+
+static int __init spear300_pinctrl_init(void)
+{
+        return platform_driver_register(&spear300_pinctrl_driver);
+}
+arch_initcall(spear300_pinctrl_init);
+
+static void __exit spear300_pinctrl_exit(void)
+{
+        platform_driver_unregister(&spear300_pinctrl_driver);
+}
+module_exit(spear300_pinctrl_exit);
+
+MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
+MODULE_DESCRIPTION("ST Microelectronics SPEAr300 pinctrl driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, spear300_pinctrl_of_match);
diff --git a/drivers/pinctrl/spear/pinctrl-spear310.c b/drivers/pinctrl/spear/pinctrl-spear310.c
new file mode 100644
index 000000000000..1a9707605125
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear310.c
@@ -0,0 +1,431 @@
+/*
+ * Driver for the ST Microelectronics SPEAr310 pinmux
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include "pinctrl-spear3xx.h"
+
+#define DRIVER_NAME "spear310-pinmux"
+
+/* addresses */
+#define PMX_CONFIG_REG                  0x08
+
+/* emi_cs_0_to_5_pins */
+static const unsigned emi_cs_0_to_5_pins[] = { 45, 46, 47, 48, 49, 50 };
+static struct spear_muxreg emi_cs_0_to_5_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux emi_cs_0_to_5_modemux[] = {
+        {
+                .muxregs = emi_cs_0_to_5_muxreg,
+                .nmuxregs = ARRAY_SIZE(emi_cs_0_to_5_muxreg),
+        },
+};
+
+static struct spear_pingroup emi_cs_0_to_5_pingroup = {
+        .name = "emi_cs_0_to_5_grp",
+        .pins = emi_cs_0_to_5_pins,
+        .npins = ARRAY_SIZE(emi_cs_0_to_5_pins),
+        .modemuxs = emi_cs_0_to_5_modemux,
+        .nmodemuxs = ARRAY_SIZE(emi_cs_0_to_5_modemux),
+};
+
+static const char *const emi_cs_0_to_5_grps[] = { "emi_cs_0_to_5_grp" };
+static struct spear_function emi_cs_0_to_5_function = {
+        .name = "emi",
+        .groups = emi_cs_0_to_5_grps,
+        .ngroups = ARRAY_SIZE(emi_cs_0_to_5_grps),
+};
+
+/* uart1_pins */
+static const unsigned uart1_pins[] = { 0, 1 };
+static struct spear_muxreg uart1_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_FIRDA_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux uart1_modemux[] = {
+        {
+                .muxregs = uart1_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart1_muxreg),
+        },
+};
+
+static struct spear_pingroup uart1_pingroup = {
+        .name = "uart1_grp",
+        .pins = uart1_pins,
+        .npins = ARRAY_SIZE(uart1_pins),
+        .modemuxs = uart1_modemux,
+        .nmodemuxs = ARRAY_SIZE(uart1_modemux),
+};
+
+static const char *const uart1_grps[] = { "uart1_grp" };
+static struct spear_function uart1_function = {
+        .name = "uart1",
+        .groups = uart1_grps,
+        .ngroups = ARRAY_SIZE(uart1_grps),
+};
+
+/* uart2_pins */
+static const unsigned uart2_pins[] = { 43, 44 };
+static struct spear_muxreg uart2_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_TIMER_0_1_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux uart2_modemux[] = {
+        {
+                .muxregs = uart2_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart2_muxreg),
+        },
+};
+
+static struct spear_pingroup uart2_pingroup = {
+        .name = "uart2_grp",
+        .pins = uart2_pins,
+        .npins = ARRAY_SIZE(uart2_pins),
+        .modemuxs = uart2_modemux,
+        .nmodemuxs = ARRAY_SIZE(uart2_modemux),
+};
+
+static const char *const uart2_grps[] = { "uart2_grp" };
+static struct spear_function uart2_function = {
+        .name = "uart2",
+        .groups = uart2_grps,
+        .ngroups = ARRAY_SIZE(uart2_grps),
+};
+
+/* uart3_pins */
+static const unsigned uart3_pins[] = { 37, 38 };
+static struct spear_muxreg uart3_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MODEM_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux uart3_modemux[] = {
+        {
+                .muxregs = uart3_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart3_muxreg),
+        },
+};
+
+static struct spear_pingroup uart3_pingroup = {
+        .name = "uart3_grp",
+        .pins = uart3_pins,
+        .npins = ARRAY_SIZE(uart3_pins),
+        .modemuxs = uart3_modemux,
+        .nmodemuxs = ARRAY_SIZE(uart3_modemux),
+};
+
+static const char *const uart3_grps[] = { "uart3_grp" };
+static struct spear_function uart3_function = {
+        .name = "uart3",
+        .groups = uart3_grps,
+        .ngroups = ARRAY_SIZE(uart3_grps),
+};
+
+/* uart4_pins */
+static const unsigned uart4_pins[] = { 39, 40 };
+static struct spear_muxreg uart4_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MODEM_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux uart4_modemux[] = {
+        {
+                .muxregs = uart4_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart4_muxreg),
+        },
+};
+
+static struct spear_pingroup uart4_pingroup = {
+        .name = "uart4_grp",
+        .pins = uart4_pins,
+        .npins = ARRAY_SIZE(uart4_pins),
+        .modemuxs = uart4_modemux,
+        .nmodemuxs = ARRAY_SIZE(uart4_modemux),
+};
+
+static const char *const uart4_grps[] = { "uart4_grp" };
+static struct spear_function uart4_function = {
+        .name = "uart4",
+        .groups = uart4_grps,
+        .ngroups = ARRAY_SIZE(uart4_grps),
+};
+
+/* uart5_pins */
+static const unsigned uart5_pins[] = { 41, 42 };
+static struct spear_muxreg uart5_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MODEM_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux uart5_modemux[] = {
+        {
+                .muxregs = uart5_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart5_muxreg),
+        },
+};
+
+static struct spear_pingroup uart5_pingroup = {
+        .name = "uart5_grp",
+        .pins = uart5_pins,
+        .npins = ARRAY_SIZE(uart5_pins),
+        .modemuxs = uart5_modemux,
+        .nmodemuxs = ARRAY_SIZE(uart5_modemux),
+};
+
+static const char *const uart5_grps[] = { "uart5_grp" };
+static struct spear_function uart5_function = {
+        .name = "uart5",
+        .groups = uart5_grps,
+        .ngroups = ARRAY_SIZE(uart5_grps),
+};
+
+/* fsmc_pins */
+static const unsigned fsmc_pins[] = { 34, 35, 36 };
+static struct spear_muxreg fsmc_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_SSP_CS_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux fsmc_modemux[] = {
+        {
+                .muxregs = fsmc_muxreg,
+                .nmuxregs = ARRAY_SIZE(fsmc_muxreg),
+        },
+};
+
+static struct spear_pingroup fsmc_pingroup = {
+        .name = "fsmc_grp",
+        .pins = fsmc_pins,
+        .npins = ARRAY_SIZE(fsmc_pins),
+        .modemuxs = fsmc_modemux,
+        .nmodemuxs = ARRAY_SIZE(fsmc_modemux),
+};
+
+static const char *const fsmc_grps[] = { "fsmc_grp" };
+static struct spear_function fsmc_function = {
+        .name = "fsmc",
+        .groups = fsmc_grps,
+        .ngroups = ARRAY_SIZE(fsmc_grps),
+};
+
+/* rs485_0_pins */
+static const unsigned rs485_0_pins[] = { 19, 20, 21, 22, 23 };
+static struct spear_muxreg rs485_0_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_MII_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux rs485_0_modemux[] = {
+        {
+                .muxregs = rs485_0_muxreg,
+                .nmuxregs = ARRAY_SIZE(rs485_0_muxreg),
+        },
+};
+
+static struct spear_pingroup rs485_0_pingroup = {
+        .name = "rs485_0_grp",
+        .pins = rs485_0_pins,
+        .npins = ARRAY_SIZE(rs485_0_pins),
+        .modemuxs = rs485_0_modemux,
+        .nmodemuxs = ARRAY_SIZE(rs485_0_modemux),
+};
+
+static const char *const rs485_0_grps[] = { "rs485_0" };
+static struct spear_function rs485_0_function = {
+        .name = "rs485_0",
+        .groups = rs485_0_grps,
+        .ngroups = ARRAY_SIZE(rs485_0_grps),
+};
+
+/* rs485_1_pins */
+static const unsigned rs485_1_pins[] = { 14, 15, 16, 17, 18 };
+static struct spear_muxreg rs485_1_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_MII_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux rs485_1_modemux[] = {
+        {
+                .muxregs = rs485_1_muxreg,
+                .nmuxregs = ARRAY_SIZE(rs485_1_muxreg),
+        },
+};
+
+static struct spear_pingroup rs485_1_pingroup = {
+        .name = "rs485_1_grp",
+        .pins = rs485_1_pins,
+        .npins = ARRAY_SIZE(rs485_1_pins),
+        .modemuxs = rs485_1_modemux,
+        .nmodemuxs = ARRAY_SIZE(rs485_1_modemux),
+};
+
+static const char *const rs485_1_grps[] = { "rs485_1" };
+static struct spear_function rs485_1_function = {
+        .name = "rs485_1",
+        .groups = rs485_1_grps,
+        .ngroups = ARRAY_SIZE(rs485_1_grps),
+};
+
+/* tdm_pins */
+static const unsigned tdm_pins[] = { 10, 11, 12, 13 };
+static struct spear_muxreg tdm_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_MII_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux tdm_modemux[] = {
+        {
+                .muxregs = tdm_muxreg,
+                .nmuxregs = ARRAY_SIZE(tdm_muxreg),
+        },
+};
+
+static struct spear_pingroup tdm_pingroup = {
+        .name = "tdm_grp",
+        .pins = tdm_pins,
+        .npins = ARRAY_SIZE(tdm_pins),
+        .modemuxs = tdm_modemux,
+        .nmodemuxs = ARRAY_SIZE(tdm_modemux),
+};
+
+static const char *const tdm_grps[] = { "tdm_grp" };
+static struct spear_function tdm_function = {
+        .name = "tdm",
+        .groups = tdm_grps,
+        .ngroups = ARRAY_SIZE(tdm_grps),
+};
+
+/* pingroups */
+static struct spear_pingroup *spear310_pingroups[] = {
+        SPEAR3XX_COMMON_PINGROUPS,
+        &emi_cs_0_to_5_pingroup,
+        &uart1_pingroup,
+        &uart2_pingroup,
+        &uart3_pingroup,
+        &uart4_pingroup,
+        &uart5_pingroup,
+        &fsmc_pingroup,
+        &rs485_0_pingroup,
+        &rs485_1_pingroup,
+        &tdm_pingroup,
+};
+
+/* functions */
+static struct spear_function *spear310_functions[] = {
+        SPEAR3XX_COMMON_FUNCTIONS,
+        &emi_cs_0_to_5_function,
+        &uart1_function,
+        &uart2_function,
+        &uart3_function,
+        &uart4_function,
+        &uart5_function,
+        &fsmc_function,
+        &rs485_0_function,
+        &rs485_1_function,
+        &tdm_function,
+};
+
+static struct of_device_id spear310_pinctrl_of_match[] __devinitdata = {
+        {
+                .compatible = "st,spear310-pinmux",
+        },
+        {},
+};
+
+static int __devinit spear310_pinctrl_probe(struct platform_device *pdev)
+{
+        int ret;
+
+        spear3xx_machdata.groups = spear310_pingroups;
+        spear3xx_machdata.ngroups = ARRAY_SIZE(spear310_pingroups);
+        spear3xx_machdata.functions = spear310_functions;
+        spear3xx_machdata.nfunctions = ARRAY_SIZE(spear310_functions);
+
+        pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
+
+        spear3xx_machdata.modes_supported = false;
+
+        ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
+        if (ret)
+                return ret;
+
+        return 0;
+}
+
+static int __devexit spear310_pinctrl_remove(struct platform_device *pdev)
+{
+        return spear_pinctrl_remove(pdev);
+}
+
+static struct platform_driver spear310_pinctrl_driver = {
+        .driver = {
+                .name = DRIVER_NAME,
+                .owner = THIS_MODULE,
+                .of_match_table = spear310_pinctrl_of_match,
+        },
+        .probe = spear310_pinctrl_probe,
+        .remove = __devexit_p(spear310_pinctrl_remove),
+};
+
+static int __init spear310_pinctrl_init(void)
+{
+        return platform_driver_register(&spear310_pinctrl_driver);
+}
+arch_initcall(spear310_pinctrl_init);
+
+static void __exit spear310_pinctrl_exit(void)
+{
+        platform_driver_unregister(&spear310_pinctrl_driver);
+}
+module_exit(spear310_pinctrl_exit);
+
+MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
+MODULE_DESCRIPTION("ST Microelectronics SPEAr310 pinctrl driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, SPEAr310_pinctrl_of_match);
diff --git a/drivers/pinctrl/spear/pinctrl-spear320.c b/drivers/pinctrl/spear/pinctrl-spear320.c
new file mode 100644
index 000000000000..de726e6c283a
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear320.c
@@ -0,0 +1,3468 @@
+/*
+ * Driver for the ST Microelectronics SPEAr320 pinmux
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include "pinctrl-spear3xx.h"
+
+#define DRIVER_NAME "spear320-pinmux"
+
+/* addresses */
+#define PMX_CONFIG_REG                  0x0C
+#define MODE_CONFIG_REG                 0x10
+#define MODE_EXT_CONFIG_REG             0x18
+
+/* modes */
+#define AUTO_NET_SMII_MODE      (1 << 0)
+#define AUTO_NET_MII_MODE       (1 << 1)
+#define AUTO_EXP_MODE           (1 << 2)
+#define SMALL_PRINTERS_MODE     (1 << 3)
+#define EXTENDED_MODE           (1 << 4)
+
+static struct spear_pmx_mode pmx_mode_auto_net_smii = {
+        .name = "Automation Networking SMII mode",
+        .mode = AUTO_NET_SMII_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x00000007,
+        .val = 0x0,
+};
+
+static struct spear_pmx_mode pmx_mode_auto_net_mii = {
+        .name = "Automation Networking MII mode",
+        .mode = AUTO_NET_MII_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x00000007,
+        .val = 0x1,
+};
+
+static struct spear_pmx_mode pmx_mode_auto_exp = {
+        .name = "Automation Expanded mode",
+        .mode = AUTO_EXP_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x00000007,
+        .val = 0x2,
+};
+
+static struct spear_pmx_mode pmx_mode_small_printers = {
+        .name = "Small Printers mode",
+        .mode = SMALL_PRINTERS_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x00000007,
+        .val = 0x3,
+};
+
+static struct spear_pmx_mode pmx_mode_extended = {
+        .name = "extended mode",
+        .mode = EXTENDED_MODE,
+        .reg = MODE_EXT_CONFIG_REG,
+        .mask = 0x00000001,
+        .val = 0x1,
+};
+
+static struct spear_pmx_mode *spear320_pmx_modes[] = {
+        &pmx_mode_auto_net_smii,
+        &pmx_mode_auto_net_mii,
+        &pmx_mode_auto_exp,
+        &pmx_mode_small_printers,
+        &pmx_mode_extended,
+};
+
+/* Extended mode registers and their offsets */
+#define EXT_CTRL_REG                            0x0018
+        #define MII_MDIO_MASK                   (1 << 4)
+        #define MII_MDIO_10_11_VAL              0
+        #define MII_MDIO_81_VAL                 (1 << 4)
+        #define EMI_FSMC_DYNAMIC_MUX_MASK       (1 << 5)
+        #define MAC_MODE_MII                    0
+        #define MAC_MODE_RMII                   1
+        #define MAC_MODE_SMII                   2
+        #define MAC_MODE_SS_SMII                3
+        #define MAC_MODE_MASK                   0x3
+        #define MAC1_MODE_SHIFT                 16
+        #define MAC2_MODE_SHIFT                 18
+
+#define IP_SEL_PAD_0_9_REG                      0x00A4
+        #define PMX_PL_0_1_MASK                 (0x3F << 0)
+        #define PMX_UART2_PL_0_1_VAL            0x0
+        #define PMX_I2C2_PL_0_1_VAL             (0x4 | (0x4 << 3))
+
+        #define PMX_PL_2_3_MASK                 (0x3F << 6)
+        #define PMX_I2C2_PL_2_3_VAL             0x0
+        #define PMX_UART6_PL_2_3_VAL            ((0x1 << 6) | (0x1 << 9))
+        #define PMX_UART1_ENH_PL_2_3_VAL        ((0x4 << 6) | (0x4 << 9))
+
+        #define PMX_PL_4_5_MASK                 (0x3F << 12)
+        #define PMX_UART5_PL_4_5_VAL            ((0x1 << 12) | (0x1 << 15))
+        #define PMX_UART1_ENH_PL_4_5_VAL        ((0x4 << 12) | (0x4 << 15))
+        #define PMX_PL_5_MASK                   (0x7 << 15)
+        #define PMX_TOUCH_Y_PL_5_VAL            0x0
+
+        #define PMX_PL_6_7_MASK                 (0x3F << 18)
+        #define PMX_PL_6_MASK                   (0x7 << 18)
+        #define PMX_PL_7_MASK                   (0x7 << 21)
+        #define PMX_UART4_PL_6_7_VAL            ((0x1 << 18) | (0x1 << 21))
+        #define PMX_PWM_3_PL_6_VAL              (0x2 << 18)
+        #define PMX_PWM_2_PL_7_VAL              (0x2 << 21)
+        #define PMX_UART1_ENH_PL_6_7_VAL        ((0x4 << 18) | (0x4 << 21))
+
+        #define PMX_PL_8_9_MASK                 (0x3F << 24)
+        #define PMX_UART3_PL_8_9_VAL            ((0x1 << 24) | (0x1 << 27))
+        #define PMX_PWM_0_1_PL_8_9_VAL          ((0x2 << 24) | (0x2 << 27))
+        #define PMX_I2C1_PL_8_9_VAL             ((0x4 << 24) | (0x4 << 27))
+
+#define IP_SEL_PAD_10_19_REG                    0x00A8
+        #define PMX_PL_10_11_MASK               (0x3F << 0)
+        #define PMX_SMII_PL_10_11_VAL           0
+        #define PMX_RMII_PL_10_11_VAL           ((0x4 << 0) | (0x4 << 3))
+
+        #define PMX_PL_12_MASK                  (0x7 << 6)
+        #define PMX_PWM3_PL_12_VAL              0
+        #define PMX_SDHCI_CD_PL_12_VAL          (0x4 << 6)
+
+        #define PMX_PL_13_14_MASK               (0x3F << 9)
+        #define PMX_PL_13_MASK                  (0x7 << 9)
+        #define PMX_PL_14_MASK                  (0x7 << 12)
+        #define PMX_SSP2_PL_13_14_15_16_VAL     0
+        #define PMX_UART4_PL_13_14_VAL          ((0x1 << 9) | (0x1 << 12))
+        #define PMX_RMII_PL_13_14_VAL           ((0x4 << 9) | (0x4 << 12))
+        #define PMX_PWM2_PL_13_VAL              (0x2 << 9)
+        #define PMX_PWM1_PL_14_VAL              (0x2 << 12)
+
+        #define PMX_PL_15_MASK                  (0x7 << 15)
+        #define PMX_PWM0_PL_15_VAL              (0x2 << 15)
+        #define PMX_PL_15_16_MASK               (0x3F << 15)
+        #define PMX_UART3_PL_15_16_VAL          ((0x1 << 15) | (0x1 << 18))
+        #define PMX_RMII_PL_15_16_VAL           ((0x4 << 15) | (0x4 << 18))
+
+        #define PMX_PL_17_18_MASK               (0x3F << 21)
+        #define PMX_SSP1_PL_17_18_19_20_VAL     0
+        #define PMX_RMII_PL_17_18_VAL           ((0x4 << 21) | (0x4 << 24))
+
+        #define PMX_PL_19_MASK                  (0x7 << 27)
+        #define PMX_I2C2_PL_19_VAL              (0x1 << 27)
+        #define PMX_RMII_PL_19_VAL              (0x4 << 27)
+
+#define IP_SEL_PAD_20_29_REG                    0x00AC
+        #define PMX_PL_20_MASK                  (0x7 << 0)
+        #define PMX_I2C2_PL_20_VAL              (0x1 << 0)
+        #define PMX_RMII_PL_20_VAL              (0x4 << 0)
+
+        #define PMX_PL_21_TO_27_MASK            (0x1FFFFF << 3)
+        #define PMX_SMII_PL_21_TO_27_VAL        0
+        #define PMX_RMII_PL_21_TO_27_VAL        ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15) | (0x4 << 18) | (0x4 << 21))
+
+        #define PMX_PL_28_29_MASK               (0x3F << 24)
+        #define PMX_PL_28_MASK                  (0x7 << 24)
+        #define PMX_PL_29_MASK                  (0x7 << 27)
+        #define PMX_UART1_PL_28_29_VAL          0
+        #define PMX_PWM_3_PL_28_VAL             (0x4 << 24)
+        #define PMX_PWM_2_PL_29_VAL             (0x4 << 27)
+
+#define IP_SEL_PAD_30_39_REG                    0x00B0
+        #define PMX_PL_30_31_MASK               (0x3F << 0)
+        #define PMX_CAN1_PL_30_31_VAL           (0)
+        #define PMX_PL_30_MASK                  (0x7 << 0)
+        #define PMX_PL_31_MASK                  (0x7 << 3)
+        #define PMX_PWM1_EXT_PL_30_VAL          (0x4 << 0)
+        #define PMX_PWM0_EXT_PL_31_VAL          (0x4 << 3)
+        #define PMX_UART1_ENH_PL_31_VAL         (0x3 << 3)
+
+        #define PMX_PL_32_33_MASK               (0x3F << 6)
+        #define PMX_CAN0_PL_32_33_VAL           0
+        #define PMX_UART1_ENH_PL_32_33_VAL      ((0x3 << 6) | (0x3 << 9))
+        #define PMX_SSP2_PL_32_33_VAL           ((0x4 << 6) | (0x4 << 9))
+
+        #define PMX_PL_34_MASK                  (0x7 << 12)
+        #define PMX_PWM2_PL_34_VAL              0
+        #define PMX_UART1_ENH_PL_34_VAL         (0x2 << 12)
+        #define PMX_SSP2_PL_34_VAL              (0x4 << 12)
+
+        #define PMX_PL_35_MASK                  (0x7 << 15)
+        #define PMX_I2S_REF_CLK_PL_35_VAL       0
+        #define PMX_UART1_ENH_PL_35_VAL         (0x2 << 15)
+        #define PMX_SSP2_PL_35_VAL              (0x4 << 15)
+
+        #define PMX_PL_36_MASK                  (0x7 << 18)
+        #define PMX_TOUCH_X_PL_36_VAL           0
+        #define PMX_UART1_ENH_PL_36_VAL         (0x2 << 18)
+        #define PMX_SSP1_PL_36_VAL              (0x4 << 18)
+
+        #define PMX_PL_37_38_MASK               (0x3F << 21)
+        #define PMX_PWM0_1_PL_37_38_VAL         0
+        #define PMX_UART5_PL_37_38_VAL          ((0x2 << 21) | (0x2 << 24))
+        #define PMX_SSP1_PL_37_38_VAL           ((0x4 << 21) | (0x4 << 24))
+
+        #define PMX_PL_39_MASK                  (0x7 << 27)
+        #define PMX_I2S_PL_39_VAL               0
+        #define PMX_UART4_PL_39_VAL             (0x2 << 27)
+        #define PMX_SSP1_PL_39_VAL              (0x4 << 27)
+
+#define IP_SEL_PAD_40_49_REG                    0x00B4
+        #define PMX_PL_40_MASK                  (0x7 << 0)
+        #define PMX_I2S_PL_40_VAL               0
+        #define PMX_UART4_PL_40_VAL             (0x2 << 0)
+        #define PMX_PWM3_PL_40_VAL              (0x4 << 0)
+
+        #define PMX_PL_41_42_MASK               (0x3F << 3)
+        #define PMX_PL_41_MASK                  (0x7 << 3)
+        #define PMX_PL_42_MASK                  (0x7 << 6)
+        #define PMX_I2S_PL_41_42_VAL            0
+        #define PMX_UART3_PL_41_42_VAL          ((0x2 << 3) | (0x2 << 6))
+        #define PMX_PWM2_PL_41_VAL              (0x4 << 3)
+        #define PMX_PWM1_PL_42_VAL              (0x4 << 6)
+
+        #define PMX_PL_43_MASK                  (0x7 << 9)
+        #define PMX_SDHCI_PL_43_VAL             0
+        #define PMX_UART1_ENH_PL_43_VAL         (0x2 << 9)
+        #define PMX_PWM0_PL_43_VAL              (0x4 << 9)
+
+        #define PMX_PL_44_45_MASK               (0x3F << 12)
+        #define PMX_SDHCI_PL_44_45_VAL  0
+        #define PMX_UART1_ENH_PL_44_45_VAL      ((0x2 << 12) | (0x2 << 15))
+        #define PMX_SSP2_PL_44_45_VAL           ((0x4 << 12) | (0x4 << 15))
+
+        #define PMX_PL_46_47_MASK               (0x3F << 18)
+        #define PMX_SDHCI_PL_46_47_VAL  0
+        #define PMX_FSMC_EMI_PL_46_47_VAL       ((0x2 << 18) | (0x2 << 21))
+        #define PMX_SSP2_PL_46_47_VAL           ((0x4 << 18) | (0x4 << 21))
+
+        #define PMX_PL_48_49_MASK               (0x3F << 24)
+        #define PMX_SDHCI_PL_48_49_VAL  0
+        #define PMX_FSMC_EMI_PL_48_49_VAL       ((0x2 << 24) | (0x2 << 27))
+        #define PMX_SSP1_PL_48_49_VAL           ((0x4 << 24) | (0x4 << 27))
+
+#define IP_SEL_PAD_50_59_REG                    0x00B8
+        #define PMX_PL_50_51_MASK               (0x3F << 0)
+        #define PMX_EMI_PL_50_51_VAL            ((0x2 << 0) | (0x2 << 3))
+        #define PMX_SSP1_PL_50_51_VAL           ((0x4 << 0) | (0x4 << 3))
+        #define PMX_PL_50_MASK                  (0x7 << 0)
+        #define PMX_PL_51_MASK                  (0x7 << 3)
+        #define PMX_SDHCI_PL_50_VAL             0
+        #define PMX_SDHCI_CD_PL_51_VAL          0
+
+        #define PMX_PL_52_53_MASK               (0x3F << 6)
+        #define PMX_FSMC_PL_52_53_VAL           0
+        #define PMX_EMI_PL_52_53_VAL            ((0x2 << 6) | (0x2 << 9))
+        #define PMX_UART3_PL_52_53_VAL          ((0x4 << 6) | (0x4 << 9))
+
+        #define PMX_PL_54_55_56_MASK            (0x1FF << 12)
+        #define PMX_FSMC_EMI_PL_54_55_56_VAL    ((0x2 << 12) | (0x2 << 15) | (0x2 << 18))
+
+        #define PMX_PL_57_MASK                  (0x7 << 21)
+        #define PMX_FSMC_PL_57_VAL              0
+        #define PMX_PWM3_PL_57_VAL              (0x4 << 21)
+
+        #define PMX_PL_58_59_MASK               (0x3F << 24)
+        #define PMX_PL_58_MASK                  (0x7 << 24)
+        #define PMX_PL_59_MASK                  (0x7 << 27)
+        #define PMX_FSMC_EMI_PL_58_59_VAL       ((0x2 << 24) | (0x2 << 27))
+        #define PMX_PWM2_PL_58_VAL              (0x4 << 24)
+        #define PMX_PWM1_PL_59_VAL              (0x4 << 27)
+
+#define IP_SEL_PAD_60_69_REG                    0x00BC
+        #define PMX_PL_60_MASK                  (0x7 << 0)
+        #define PMX_FSMC_PL_60_VAL              0
+        #define PMX_PWM0_PL_60_VAL              (0x4 << 0)
+
+        #define PMX_PL_61_TO_64_MASK            (0xFFF << 3)
+        #define PMX_FSMC_PL_61_TO_64_VAL        ((0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12))
+        #define PMX_SSP2_PL_61_TO_64_VAL        ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12))
+
+        #define PMX_PL_65_TO_68_MASK            (0xFFF << 15)
+        #define PMX_FSMC_PL_65_TO_68_VAL        ((0x2 << 15) | (0x2 << 18) | (0x2 << 21) | (0x2 << 24))
+        #define PMX_SSP1_PL_65_TO_68_VAL        ((0x4 << 15) | (0x4 << 18) | (0x4 << 21) | (0x4 << 24))
+
+        #define PMX_PL_69_MASK                  (0x7 << 27)
+        #define PMX_CLCD_PL_69_VAL              (0)
+        #define PMX_EMI_PL_69_VAL               (0x2 << 27)
+        #define PMX_SPP_PL_69_VAL               (0x3 << 27)
+        #define PMX_UART5_PL_69_VAL             (0x4 << 27)
+
+#define IP_SEL_PAD_70_79_REG                    0x00C0
+        #define PMX_PL_70_MASK                  (0x7 << 0)
+        #define PMX_CLCD_PL_70_VAL              (0)
+        #define PMX_FSMC_EMI_PL_70_VAL          (0x2 << 0)
+        #define PMX_SPP_PL_70_VAL               (0x3 << 0)
+        #define PMX_UART5_PL_70_VAL             (0x4 << 0)
+
+        #define PMX_PL_71_72_MASK               (0x3F << 3)
+        #define PMX_CLCD_PL_71_72_VAL           (0)
+        #define PMX_FSMC_EMI_PL_71_72_VAL       ((0x2 << 3) | (0x2 << 6))
+        #define PMX_SPP_PL_71_72_VAL            ((0x3 << 3) | (0x3 << 6))
+        #define PMX_UART4_PL_71_72_VAL          ((0x4 << 3) | (0x4 << 6))
+
+        #define PMX_PL_73_MASK                  (0x7 << 9)
+        #define PMX_CLCD_PL_73_VAL              (0)
+        #define PMX_FSMC_EMI_PL_73_VAL          (0x2 << 9)
+        #define PMX_SPP_PL_73_VAL               (0x3 << 9)
+        #define PMX_UART3_PL_73_VAL             (0x4 << 9)
+
+        #define PMX_PL_74_MASK                  (0x7 << 12)
+        #define PMX_CLCD_PL_74_VAL              (0)
+        #define PMX_EMI_PL_74_VAL               (0x2 << 12)
+        #define PMX_SPP_PL_74_VAL               (0x3 << 12)
+        #define PMX_UART3_PL_74_VAL             (0x4 << 12)
+
+        #define PMX_PL_75_76_MASK               (0x3F << 15)
+        #define PMX_CLCD_PL_75_76_VAL           (0)
+        #define PMX_EMI_PL_75_76_VAL            ((0x2 << 15) | (0x2 << 18))
+        #define PMX_SPP_PL_75_76_VAL            ((0x3 << 15) | (0x3 << 18))
+        #define PMX_I2C2_PL_75_76_VAL           ((0x4 << 15) | (0x4 << 18))
+
+        #define PMX_PL_77_78_79_MASK            (0x1FF << 21)
+        #define PMX_CLCD_PL_77_78_79_VAL        (0)
+        #define PMX_EMI_PL_77_78_79_VAL         ((0x2 << 21) | (0x2 << 24) | (0x2 << 27))
+        #define PMX_SPP_PL_77_78_79_VAL         ((0x3 << 21) | (0x3 << 24) | (0x3 << 27))
+        #define PMX_RS485_PL_77_78_79_VAL       ((0x4 << 21) | (0x4 << 24) | (0x4 << 27))
+
+#define IP_SEL_PAD_80_89_REG                    0x00C4
+        #define PMX_PL_80_TO_85_MASK            (0x3FFFF << 0)
+        #define PMX_CLCD_PL_80_TO_85_VAL        0
+        #define PMX_MII2_PL_80_TO_85_VAL        ((0x1 << 0) | (0x1 << 3) | (0x1 << 6) | (0x1 << 9) | (0x1 << 12) | (0x1 << 15))
+        #define PMX_EMI_PL_80_TO_85_VAL         ((0x2 << 0) | (0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12) | (0x2 << 15))
+        #define PMX_SPP_PL_80_TO_85_VAL         ((0x3 << 0) | (0x3 << 3) | (0x3 << 6) | (0x3 << 9) | (0x3 << 12) | (0x3 << 15))
+        #define PMX_UART1_ENH_PL_80_TO_85_VAL   ((0x4 << 0) | (0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15))
+
+        #define PMX_PL_86_87_MASK               (0x3F << 18)
+        #define PMX_PL_86_MASK                  (0x7 << 18)
+        #define PMX_PL_87_MASK                  (0x7 << 21)
+        #define PMX_CLCD_PL_86_87_VAL           0
+        #define PMX_MII2_PL_86_87_VAL           ((0x1 << 18) | (0x1 << 21))
+        #define PMX_EMI_PL_86_87_VAL            ((0x2 << 18) | (0x2 << 21))
+        #define PMX_PWM3_PL_86_VAL              (0x4 << 18)
+        #define PMX_PWM2_PL_87_VAL              (0x4 << 21)
+
+        #define PMX_PL_88_89_MASK               (0x3F << 24)
+        #define PMX_CLCD_PL_88_89_VAL           0
+        #define PMX_MII2_PL_88_89_VAL           ((0x1 << 24) | (0x1 << 27))
+        #define PMX_EMI_PL_88_89_VAL            ((0x2 << 24) | (0x2 << 27))
+        #define PMX_UART6_PL_88_89_VAL          ((0x3 << 24) | (0x3 << 27))
+        #define PMX_PWM0_1_PL_88_89_VAL         ((0x4 << 24) | (0x4 << 27))
+
+#define IP_SEL_PAD_90_99_REG                    0x00C8
+        #define PMX_PL_90_91_MASK               (0x3F << 0)
+        #define PMX_CLCD_PL_90_91_VAL           0
+        #define PMX_MII2_PL_90_91_VAL           ((0x1 << 0) | (0x1 << 3))
+        #define PMX_EMI1_PL_90_91_VAL           ((0x2 << 0) | (0x2 << 3))
+        #define PMX_UART5_PL_90_91_VAL          ((0x3 << 0) | (0x3 << 3))
+        #define PMX_SSP2_PL_90_91_VAL           ((0x4 << 0) | (0x4 << 3))
+
+        #define PMX_PL_92_93_MASK               (0x3F << 6)
+        #define PMX_CLCD_PL_92_93_VAL           0
+        #define PMX_MII2_PL_92_93_VAL           ((0x1 << 6) | (0x1 << 9))
+        #define PMX_EMI1_PL_92_93_VAL           ((0x2 << 6) | (0x2 << 9))
+        #define PMX_UART4_PL_92_93_VAL          ((0x3 << 6) | (0x3 << 9))
+        #define PMX_SSP2_PL_92_93_VAL           ((0x4 << 6) | (0x4 << 9))
+
+        #define PMX_PL_94_95_MASK               (0x3F << 12)
+        #define PMX_CLCD_PL_94_95_VAL           0
+        #define PMX_MII2_PL_94_95_VAL           ((0x1 << 12) | (0x1 << 15))
+        #define PMX_EMI1_PL_94_95_VAL           ((0x2 << 12) | (0x2 << 15))
+        #define PMX_UART3_PL_94_95_VAL          ((0x3 << 12) | (0x3 << 15))
+        #define PMX_SSP1_PL_94_95_VAL           ((0x4 << 12) | (0x4 << 15))
+
+        #define PMX_PL_96_97_MASK               (0x3F << 18)
+        #define PMX_CLCD_PL_96_97_VAL           0
+        #define PMX_MII2_PL_96_97_VAL           ((0x1 << 18) | (0x1 << 21))
+        #define PMX_EMI1_PL_96_97_VAL           ((0x2 << 18) | (0x2 << 21))
+        #define PMX_I2C2_PL_96_97_VAL           ((0x3 << 18) | (0x3 << 21))
+        #define PMX_SSP1_PL_96_97_VAL           ((0x4 << 18) | (0x4 << 21))
+
+        #define PMX_PL_98_MASK                  (0x7 << 24)
+        #define PMX_CLCD_PL_98_VAL              0
+        #define PMX_I2C1_PL_98_VAL              (0x2 << 24)
+        #define PMX_UART3_PL_98_VAL             (0x4 << 24)
+
+        #define PMX_PL_99_MASK                  (0x7 << 27)
+        #define PMX_SDHCI_PL_99_VAL             0
+        #define PMX_I2C1_PL_99_VAL              (0x2 << 27)
+        #define PMX_UART3_PL_99_VAL             (0x4 << 27)
+
+#define IP_SEL_MIX_PAD_REG                      0x00CC
+        #define PMX_PL_100_101_MASK             (0x3F << 0)
+        #define PMX_SDHCI_PL_100_101_VAL        0
+        #define PMX_UART4_PL_100_101_VAL        ((0x4 << 0) | (0x4 << 3))
+
+        #define PMX_SSP1_PORT_SEL_MASK          (0x7 << 8)
+        #define PMX_SSP1_PORT_94_TO_97_VAL      0
+        #define PMX_SSP1_PORT_65_TO_68_VAL      (0x1 << 8)
+        #define PMX_SSP1_PORT_48_TO_51_VAL      (0x2 << 8)
+        #define PMX_SSP1_PORT_36_TO_39_VAL      (0x3 << 8)
+        #define PMX_SSP1_PORT_17_TO_20_VAL      (0x4 << 8)
+
+        #define PMX_SSP2_PORT_SEL_MASK          (0x7 << 11)
+        #define PMX_SSP2_PORT_90_TO_93_VAL      0
+        #define PMX_SSP2_PORT_61_TO_64_VAL      (0x1 << 11)
+        #define PMX_SSP2_PORT_44_TO_47_VAL      (0x2 << 11)
+        #define PMX_SSP2_PORT_32_TO_35_VAL      (0x3 << 11)
+        #define PMX_SSP2_PORT_13_TO_16_VAL      (0x4 << 11)
+
+        #define PMX_UART1_ENH_PORT_SEL_MASK             (0x3 << 14)
+        #define PMX_UART1_ENH_PORT_81_TO_85_VAL         0
+        #define PMX_UART1_ENH_PORT_44_45_34_36_VAL      (0x1 << 14)
+        #define PMX_UART1_ENH_PORT_32_TO_34_36_VAL      (0x2 << 14)
+        #define PMX_UART1_ENH_PORT_3_TO_5_7_VAL         (0x3 << 14)
+
+        #define PMX_UART3_PORT_SEL_MASK         (0x7 << 16)
+        #define PMX_UART3_PORT_94_VAL           0
+        #define PMX_UART3_PORT_73_VAL           (0x1 << 16)
+        #define PMX_UART3_PORT_52_VAL           (0x2 << 16)
+        #define PMX_UART3_PORT_41_VAL           (0x3 << 16)
+        #define PMX_UART3_PORT_15_VAL           (0x4 << 16)
+        #define PMX_UART3_PORT_8_VAL            (0x5 << 16)
+        #define PMX_UART3_PORT_99_VAL           (0x6 << 16)
+
+        #define PMX_UART4_PORT_SEL_MASK         (0x7 << 19)
+        #define PMX_UART4_PORT_92_VAL           0
+        #define PMX_UART4_PORT_71_VAL           (0x1 << 19)
+        #define PMX_UART4_PORT_39_VAL           (0x2 << 19)
+        #define PMX_UART4_PORT_13_VAL           (0x3 << 19)
+        #define PMX_UART4_PORT_6_VAL            (0x4 << 19)
+        #define PMX_UART4_PORT_101_VAL          (0x5 << 19)
+
+        #define PMX_UART5_PORT_SEL_MASK         (0x3 << 22)
+        #define PMX_UART5_PORT_90_VAL           0
+        #define PMX_UART5_PORT_69_VAL           (0x1 << 22)
+        #define PMX_UART5_PORT_37_VAL           (0x2 << 22)
+        #define PMX_UART5_PORT_4_VAL            (0x3 << 22)
+
+        #define PMX_UART6_PORT_SEL_MASK         (0x1 << 24)
+        #define PMX_UART6_PORT_88_VAL           0
+        #define PMX_UART6_PORT_2_VAL            (0x1 << 24)
+
+        #define PMX_I2C1_PORT_SEL_MASK          (0x1 << 25)
+        #define PMX_I2C1_PORT_8_9_VAL           0
+        #define PMX_I2C1_PORT_98_99_VAL         (0x1 << 25)
+
+        #define PMX_I2C2_PORT_SEL_MASK          (0x3 << 26)
+        #define PMX_I2C2_PORT_96_97_VAL         0
+        #define PMX_I2C2_PORT_75_76_VAL         (0x1 << 26)
+        #define PMX_I2C2_PORT_19_20_VAL         (0x2 << 26)
+        #define PMX_I2C2_PORT_2_3_VAL           (0x3 << 26)
+        #define PMX_I2C2_PORT_0_1_VAL           (0x4 << 26)
+
+        #define PMX_SDHCI_CD_PORT_SEL_MASK      (0x1 << 29)
+        #define PMX_SDHCI_CD_PORT_12_VAL        0
+        #define PMX_SDHCI_CD_PORT_51_VAL        (0x1 << 29)
+
+/* Pad multiplexing for CLCD device */
+static const unsigned clcd_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78,
+        79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96,
+        97 };
+static struct spear_muxreg clcd_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_60_69_REG,
+                .mask = PMX_PL_69_MASK,
+                .val = PMX_CLCD_PL_69_VAL,
+        }, {
+                .reg = IP_SEL_PAD_70_79_REG,
+                .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
+                        PMX_PL_74_MASK | PMX_PL_75_76_MASK |
+                        PMX_PL_77_78_79_MASK,
+                .val = PMX_CLCD_PL_70_VAL | PMX_CLCD_PL_71_72_VAL |
+                        PMX_CLCD_PL_73_VAL | PMX_CLCD_PL_74_VAL |
+                        PMX_CLCD_PL_75_76_VAL | PMX_CLCD_PL_77_78_79_VAL,
+        }, {
+                .reg = IP_SEL_PAD_80_89_REG,
+                .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
+                        PMX_PL_88_89_MASK,
+                .val = PMX_CLCD_PL_80_TO_85_VAL | PMX_CLCD_PL_86_87_VAL |
+                        PMX_CLCD_PL_88_89_VAL,
+        }, {
+                .reg = IP_SEL_PAD_90_99_REG,
+                .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
+                        PMX_PL_94_95_MASK | PMX_PL_96_97_MASK | PMX_PL_98_MASK,
+                .val = PMX_CLCD_PL_90_91_VAL | PMX_CLCD_PL_92_93_VAL |
+                        PMX_CLCD_PL_94_95_VAL | PMX_CLCD_PL_96_97_VAL |
+                        PMX_CLCD_PL_98_VAL,
+        },
+};
+
+static struct spear_modemux clcd_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = clcd_muxreg,
+                .nmuxregs = ARRAY_SIZE(clcd_muxreg),
+        },
+};
+
+static struct spear_pingroup clcd_pingroup = {
+        .name = "clcd_grp",
+        .pins = clcd_pins,
+        .npins = ARRAY_SIZE(clcd_pins),
+        .modemuxs = clcd_modemux,
+        .nmodemuxs = ARRAY_SIZE(clcd_modemux),
+};
+
+static const char *const clcd_grps[] = { "clcd_grp" };
+static struct spear_function clcd_function = {
+        .name = "clcd",
+        .groups = clcd_grps,
+        .ngroups = ARRAY_SIZE(clcd_grps),
+};
+
+/* Pad multiplexing for EMI (Parallel NOR flash) device */
+static const unsigned emi_pins[] = { 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56,
+        57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74,
+        75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92,
+        93, 94, 95, 96, 97 };
+static struct spear_muxreg emi_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg emi_ext_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_40_49_REG,
+                .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
+                .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL,
+        }, {
+                .reg = IP_SEL_PAD_50_59_REG,
+                .mask = PMX_PL_50_51_MASK | PMX_PL_52_53_MASK |
+                        PMX_PL_54_55_56_MASK | PMX_PL_58_59_MASK,
+                .val = PMX_EMI_PL_50_51_VAL | PMX_EMI_PL_52_53_VAL |
+                        PMX_FSMC_EMI_PL_54_55_56_VAL |
+                        PMX_FSMC_EMI_PL_58_59_VAL,
+        }, {
+                .reg = IP_SEL_PAD_60_69_REG,
+                .mask = PMX_PL_69_MASK,
+                .val = PMX_EMI_PL_69_VAL,
+        }, {
+                .reg = IP_SEL_PAD_70_79_REG,
+                .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
+                        PMX_PL_74_MASK | PMX_PL_75_76_MASK |
+                        PMX_PL_77_78_79_MASK,
+                .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
+                        PMX_FSMC_EMI_PL_73_VAL | PMX_EMI_PL_74_VAL |
+                        PMX_EMI_PL_75_76_VAL | PMX_EMI_PL_77_78_79_VAL,
+        }, {
+                .reg = IP_SEL_PAD_80_89_REG,
+                .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
+                        PMX_PL_88_89_MASK,
+                .val = PMX_EMI_PL_80_TO_85_VAL | PMX_EMI_PL_86_87_VAL |
+                        PMX_EMI_PL_88_89_VAL,
+        }, {
+                .reg = IP_SEL_PAD_90_99_REG,
+                .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
+                        PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
+                .val = PMX_EMI1_PL_90_91_VAL | PMX_EMI1_PL_92_93_VAL |
+                        PMX_EMI1_PL_94_95_VAL | PMX_EMI1_PL_96_97_VAL,
+        }, {
+                .reg = EXT_CTRL_REG,
+                .mask = EMI_FSMC_DYNAMIC_MUX_MASK,
+                .val = EMI_FSMC_DYNAMIC_MUX_MASK,
+        },
+};
+
+static struct spear_modemux emi_modemux[] = {
+        {
+                .modes = AUTO_EXP_MODE | EXTENDED_MODE,
+                .muxregs = emi_muxreg,
+                .nmuxregs = ARRAY_SIZE(emi_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = emi_ext_muxreg,
+                .nmuxregs = ARRAY_SIZE(emi_ext_muxreg),
+        },
+};
+
+static struct spear_pingroup emi_pingroup = {
+        .name = "emi_grp",
+        .pins = emi_pins,
+        .npins = ARRAY_SIZE(emi_pins),
+        .modemuxs = emi_modemux,
+        .nmodemuxs = ARRAY_SIZE(emi_modemux),
+};
+
+static const char *const emi_grps[] = { "emi_grp" };
+static struct spear_function emi_function = {
+        .name = "emi",
+        .groups = emi_grps,
+        .ngroups = ARRAY_SIZE(emi_grps),
+};
+
+/* Pad multiplexing for FSMC (NAND flash) device */
+static const unsigned fsmc_8bit_pins[] = { 52, 53, 54, 55, 56, 57, 58, 59, 60,
+        61, 62, 63, 64, 65, 66, 67, 68 };
+static struct spear_muxreg fsmc_8bit_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_50_59_REG,
+                .mask = PMX_PL_52_53_MASK | PMX_PL_54_55_56_MASK |
+                        PMX_PL_57_MASK | PMX_PL_58_59_MASK,
+                .val = PMX_FSMC_PL_52_53_VAL | PMX_FSMC_EMI_PL_54_55_56_VAL |
+                        PMX_FSMC_PL_57_VAL | PMX_FSMC_EMI_PL_58_59_VAL,
+        }, {
+                .reg = IP_SEL_PAD_60_69_REG,
+                .mask = PMX_PL_60_MASK | PMX_PL_61_TO_64_MASK |
+                        PMX_PL_65_TO_68_MASK,
+                .val = PMX_FSMC_PL_60_VAL | PMX_FSMC_PL_61_TO_64_VAL |
+                        PMX_FSMC_PL_65_TO_68_VAL,
+        }, {
+                .reg = EXT_CTRL_REG,
+                .mask = EMI_FSMC_DYNAMIC_MUX_MASK,
+                .val = EMI_FSMC_DYNAMIC_MUX_MASK,
+        },
+};
+
+static struct spear_modemux fsmc_8bit_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = fsmc_8bit_muxreg,
+                .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
+        },
+};
+
+static struct spear_pingroup fsmc_8bit_pingroup = {
+        .name = "fsmc_8bit_grp",
+        .pins = fsmc_8bit_pins,
+        .npins = ARRAY_SIZE(fsmc_8bit_pins),
+        .modemuxs = fsmc_8bit_modemux,
+        .nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux),
+};
+
+static const unsigned fsmc_16bit_pins[] = { 46, 47, 48, 49, 52, 53, 54, 55, 56,
+        57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 70, 71, 72, 73 };
+static struct spear_muxreg fsmc_16bit_autoexp_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg fsmc_16bit_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_40_49_REG,
+                .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
+                .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL,
+        }, {
+                .reg = IP_SEL_PAD_70_79_REG,
+                .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK,
+                .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
+                        PMX_FSMC_EMI_PL_73_VAL,
+        }
+};
+
+static struct spear_modemux fsmc_16bit_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = fsmc_8bit_muxreg,
+                .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
+        }, {
+                .modes = AUTO_EXP_MODE | EXTENDED_MODE,
+                .muxregs = fsmc_16bit_autoexp_muxreg,
+                .nmuxregs = ARRAY_SIZE(fsmc_16bit_autoexp_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = fsmc_16bit_muxreg,
+                .nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg),
+        },
+};
+
+static struct spear_pingroup fsmc_16bit_pingroup = {
+        .name = "fsmc_16bit_grp",
+        .pins = fsmc_16bit_pins,
+        .npins = ARRAY_SIZE(fsmc_16bit_pins),
+        .modemuxs = fsmc_16bit_modemux,
+        .nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux),
+};
+
+static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp" };
+static struct spear_function fsmc_function = {
+        .name = "fsmc",
+        .groups = fsmc_grps,
+        .ngroups = ARRAY_SIZE(fsmc_grps),
+};
+
+/* Pad multiplexing for SPP device */
+static const unsigned spp_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
+        80, 81, 82, 83, 84, 85 };
+static struct spear_muxreg spp_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_60_69_REG,
+                .mask = PMX_PL_69_MASK,
+                .val = PMX_SPP_PL_69_VAL,
+        }, {
+                .reg = IP_SEL_PAD_70_79_REG,
+                .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
+                        PMX_PL_74_MASK | PMX_PL_75_76_MASK |
+                        PMX_PL_77_78_79_MASK,
+                .val = PMX_SPP_PL_70_VAL | PMX_SPP_PL_71_72_VAL |
+                        PMX_SPP_PL_73_VAL | PMX_SPP_PL_74_VAL |
+                        PMX_SPP_PL_75_76_VAL | PMX_SPP_PL_77_78_79_VAL,
+        }, {
+                .reg = IP_SEL_PAD_80_89_REG,
+                .mask = PMX_PL_80_TO_85_MASK,
+                .val = PMX_SPP_PL_80_TO_85_VAL,
+        },
+};
+
+static struct spear_modemux spp_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = spp_muxreg,
+                .nmuxregs = ARRAY_SIZE(spp_muxreg),
+        },
+};
+
+static struct spear_pingroup spp_pingroup = {
+        .name = "spp_grp",
+        .pins = spp_pins,
+        .npins = ARRAY_SIZE(spp_pins),
+        .modemuxs = spp_modemux,
+        .nmodemuxs = ARRAY_SIZE(spp_modemux),
+};
+
+static const char *const spp_grps[] = { "spp_grp" };
+static struct spear_function spp_function = {
+        .name = "spp",
+        .groups = spp_grps,
+        .ngroups = ARRAY_SIZE(spp_grps),
+};
+
+/* Pad multiplexing for SDHCI device */
+static const unsigned sdhci_led_pins[] = { 34 };
+static struct spear_muxreg sdhci_led_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_SSP_CS_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg sdhci_led_ext_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_30_39_REG,
+                .mask = PMX_PL_34_MASK,
+                .val = PMX_PWM2_PL_34_VAL,
+        },
+};
+
+static struct spear_modemux sdhci_led_modemux[] = {
+        {
+                .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
+                .muxregs = sdhci_led_muxreg,
+                .nmuxregs = ARRAY_SIZE(sdhci_led_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = sdhci_led_ext_muxreg,
+                .nmuxregs = ARRAY_SIZE(sdhci_led_ext_muxreg),
+        },
+};
+
+static struct spear_pingroup sdhci_led_pingroup = {
+        .name = "sdhci_led_grp",
+        .pins = sdhci_led_pins,
+        .npins = ARRAY_SIZE(sdhci_led_pins),
+        .modemuxs = sdhci_led_modemux,
+        .nmodemuxs = ARRAY_SIZE(sdhci_led_modemux),
+};
+
+static const unsigned sdhci_cd_12_pins[] = { 12, 43, 44, 45, 46, 47, 48, 49,
+        50};
+static const unsigned sdhci_cd_51_pins[] = { 43, 44, 45, 46, 47, 48, 49, 50, 51
+};
+static struct spear_muxreg sdhci_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg sdhci_ext_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_40_49_REG,
+                .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK | PMX_PL_46_47_MASK |
+                        PMX_PL_48_49_MASK,
+                .val = PMX_SDHCI_PL_43_VAL | PMX_SDHCI_PL_44_45_VAL |
+                        PMX_SDHCI_PL_46_47_VAL | PMX_SDHCI_PL_48_49_VAL,
+        }, {
+                .reg = IP_SEL_PAD_50_59_REG,
+                .mask = PMX_PL_50_MASK,
+                .val = PMX_SDHCI_PL_50_VAL,
+        }, {
+                .reg = IP_SEL_PAD_90_99_REG,
+                .mask = PMX_PL_99_MASK,
+                .val = PMX_SDHCI_PL_99_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_PL_100_101_MASK,
+                .val = PMX_SDHCI_PL_100_101_VAL,
+        },
+};
+
+static struct spear_muxreg sdhci_cd_12_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_MII_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_10_19_REG,
+                .mask = PMX_PL_12_MASK,
+                .val = PMX_SDHCI_CD_PL_12_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_SDHCI_CD_PORT_SEL_MASK,
+                .val = PMX_SDHCI_CD_PORT_12_VAL,
+        },
+};
+
+static struct spear_muxreg sdhci_cd_51_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_50_59_REG,
+                .mask = PMX_PL_51_MASK,
+                .val = PMX_SDHCI_CD_PL_51_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_SDHCI_CD_PORT_SEL_MASK,
+                .val = PMX_SDHCI_CD_PORT_51_VAL,
+        },
+};
+
+#define pmx_sdhci_common_modemux                                        \
+        {                                                               \
+                .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |       \
+                        SMALL_PRINTERS_MODE | EXTENDED_MODE,            \
+                .muxregs = sdhci_muxreg,                                \
+                .nmuxregs = ARRAY_SIZE(sdhci_muxreg),                   \
+        }, {                                                            \
+                .modes = EXTENDED_MODE,                                 \
+                .muxregs = sdhci_ext_muxreg,                            \
+                .nmuxregs = ARRAY_SIZE(sdhci_ext_muxreg),               \
+        }
+
+static struct spear_modemux sdhci_modemux[][3] = {
+        {
+                /* select pin 12 for cd */
+                pmx_sdhci_common_modemux,
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = sdhci_cd_12_muxreg,
+                        .nmuxregs = ARRAY_SIZE(sdhci_cd_12_muxreg),
+                },
+        }, {
+                /* select pin 51 for cd */
+                pmx_sdhci_common_modemux,
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = sdhci_cd_51_muxreg,
+                        .nmuxregs = ARRAY_SIZE(sdhci_cd_51_muxreg),
+                },
+        }
+};
+
+static struct spear_pingroup sdhci_pingroup[] = {
+        {
+                .name = "sdhci_cd_12_grp",
+                .pins = sdhci_cd_12_pins,
+                .npins = ARRAY_SIZE(sdhci_cd_12_pins),
+                .modemuxs = sdhci_modemux[0],
+                .nmodemuxs = ARRAY_SIZE(sdhci_modemux[0]),
+        }, {
+                .name = "sdhci_cd_51_grp",
+                .pins = sdhci_cd_51_pins,
+                .npins = ARRAY_SIZE(sdhci_cd_51_pins),
+                .modemuxs = sdhci_modemux[1],
+                .nmodemuxs = ARRAY_SIZE(sdhci_modemux[1]),
+        },
+};
+
+static const char *const sdhci_grps[] = { "sdhci_cd_12_grp", "sdhci_cd_51_grp",
+        "sdhci_led_grp" };
+
+static struct spear_function sdhci_function = {
+        .name = "sdhci",
+        .groups = sdhci_grps,
+        .ngroups = ARRAY_SIZE(sdhci_grps),
+};
+
+/* Pad multiplexing for I2S device */
+static const unsigned i2s_pins[] = { 35, 39, 40, 41, 42 };
+static struct spear_muxreg i2s_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_SSP_CS_MASK,
+                .val = 0,
+        }, {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MODEM_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg i2s_ext_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_30_39_REG,
+                .mask = PMX_PL_35_MASK | PMX_PL_39_MASK,
+                .val = PMX_I2S_REF_CLK_PL_35_VAL | PMX_I2S_PL_39_VAL,
+        }, {
+                .reg = IP_SEL_PAD_40_49_REG,
+                .mask = PMX_PL_40_MASK | PMX_PL_41_42_MASK,
+                .val = PMX_I2S_PL_40_VAL | PMX_I2S_PL_41_42_VAL,
+        },
+};
+
+static struct spear_modemux i2s_modemux[] = {
+        {
+                .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
+                .muxregs = i2s_muxreg,
+                .nmuxregs = ARRAY_SIZE(i2s_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = i2s_ext_muxreg,
+                .nmuxregs = ARRAY_SIZE(i2s_ext_muxreg),
+        },
+};
+
+static struct spear_pingroup i2s_pingroup = {
+        .name = "i2s_grp",
+        .pins = i2s_pins,
+        .npins = ARRAY_SIZE(i2s_pins),
+        .modemuxs = i2s_modemux,
+        .nmodemuxs = ARRAY_SIZE(i2s_modemux),
+};
+
+static const char *const i2s_grps[] = { "i2s_grp" };
+static struct spear_function i2s_function = {
+        .name = "i2s",
+        .groups = i2s_grps,
+        .ngroups = ARRAY_SIZE(i2s_grps),
+};
+
+/* Pad multiplexing for UART1 device */
+static const unsigned uart1_pins[] = { 28, 29 };
+static struct spear_muxreg uart1_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg uart1_ext_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_20_29_REG,
+                .mask = PMX_PL_28_29_MASK,
+                .val = PMX_UART1_PL_28_29_VAL,
+        },
+};
+
+static struct spear_modemux uart1_modemux[] = {
+        {
+                .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
+                        | SMALL_PRINTERS_MODE | EXTENDED_MODE,
+                .muxregs = uart1_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart1_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = uart1_ext_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart1_ext_muxreg),
+        },
+};
+
+static struct spear_pingroup uart1_pingroup = {
+        .name = "uart1_grp",
+        .pins = uart1_pins,
+        .npins = ARRAY_SIZE(uart1_pins),
+        .modemuxs = uart1_modemux,
+        .nmodemuxs = ARRAY_SIZE(uart1_modemux),
+};
+
+static const char *const uart1_grps[] = { "uart1_grp" };
+static struct spear_function uart1_function = {
+        .name = "uart1",
+        .groups = uart1_grps,
+        .ngroups = ARRAY_SIZE(uart1_grps),
+};
+
+/* Pad multiplexing for UART1 Modem device */
+static const unsigned uart1_modem_2_to_7_pins[] = { 2, 3, 4, 5, 6, 7 };
+static const unsigned uart1_modem_31_to_36_pins[] = { 31, 32, 33, 34, 35, 36 };
+static const unsigned uart1_modem_34_to_45_pins[] = { 34, 35, 36, 43, 44, 45 };
+static const unsigned uart1_modem_80_to_85_pins[] = { 80, 81, 82, 83, 84, 85 };
+
+static struct spear_muxreg uart1_modem_ext_2_to_7_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MASK | PMX_I2C_MASK | PMX_SSP_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_0_9_REG,
+                .mask = PMX_PL_2_3_MASK | PMX_PL_6_7_MASK,
+                .val = PMX_UART1_ENH_PL_2_3_VAL | PMX_UART1_ENH_PL_4_5_VAL |
+                        PMX_UART1_ENH_PL_6_7_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART1_ENH_PORT_SEL_MASK,
+                .val = PMX_UART1_ENH_PORT_3_TO_5_7_VAL,
+        },
+};
+
+static struct spear_muxreg uart1_modem_31_to_36_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
+                        PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg uart1_modem_ext_31_to_36_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_30_39_REG,
+                .mask = PMX_PL_31_MASK | PMX_PL_32_33_MASK | PMX_PL_34_MASK |
+                        PMX_PL_35_MASK | PMX_PL_36_MASK,
+                .val = PMX_UART1_ENH_PL_31_VAL | PMX_UART1_ENH_PL_32_33_VAL |
+                        PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
+                        PMX_UART1_ENH_PL_36_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART1_ENH_PORT_SEL_MASK,
+                .val = PMX_UART1_ENH_PORT_32_TO_34_36_VAL,
+        },
+};
+
+static struct spear_muxreg uart1_modem_34_to_45_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK |
+                        PMX_SSP_CS_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg uart1_modem_ext_34_to_45_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_30_39_REG,
+                .mask = PMX_PL_34_MASK | PMX_PL_35_MASK | PMX_PL_36_MASK,
+                .val = PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
+                        PMX_UART1_ENH_PL_36_VAL,
+        }, {
+                .reg = IP_SEL_PAD_40_49_REG,
+                .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
+                .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART1_ENH_PORT_SEL_MASK,
+                .val = PMX_UART1_ENH_PORT_44_45_34_36_VAL,
+        },
+};
+
+static struct spear_muxreg uart1_modem_ext_80_to_85_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_80_89_REG,
+                .mask = PMX_PL_80_TO_85_MASK,
+                .val = PMX_UART1_ENH_PL_80_TO_85_VAL,
+        }, {
+                .reg = IP_SEL_PAD_40_49_REG,
+                .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
+                .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART1_ENH_PORT_SEL_MASK,
+                .val = PMX_UART1_ENH_PORT_81_TO_85_VAL,
+        },
+};
+
+static struct spear_modemux uart1_modem_2_to_7_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = uart1_modem_ext_2_to_7_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart1_modem_ext_2_to_7_muxreg),
+        },
+};
+
+static struct spear_modemux uart1_modem_31_to_36_modemux[] = {
+        {
+                .modes = SMALL_PRINTERS_MODE | EXTENDED_MODE,
+                .muxregs = uart1_modem_31_to_36_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart1_modem_31_to_36_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = uart1_modem_ext_31_to_36_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart1_modem_ext_31_to_36_muxreg),
+        },
+};
+
+static struct spear_modemux uart1_modem_34_to_45_modemux[] = {
+        {
+                .modes = AUTO_EXP_MODE | EXTENDED_MODE,
+                .muxregs = uart1_modem_34_to_45_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart1_modem_34_to_45_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = uart1_modem_ext_34_to_45_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart1_modem_ext_34_to_45_muxreg),
+        },
+};
+
+static struct spear_modemux uart1_modem_80_to_85_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = uart1_modem_ext_80_to_85_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart1_modem_ext_80_to_85_muxreg),
+        },
+};
+
+static struct spear_pingroup uart1_modem_pingroup[] = {
+        {
+                .name = "uart1_modem_2_to_7_grp",
+                .pins = uart1_modem_2_to_7_pins,
+                .npins = ARRAY_SIZE(uart1_modem_2_to_7_pins),
+                .modemuxs = uart1_modem_2_to_7_modemux,
+                .nmodemuxs = ARRAY_SIZE(uart1_modem_2_to_7_modemux),
+        }, {
+                .name = "uart1_modem_31_to_36_grp",
+                .pins = uart1_modem_31_to_36_pins,
+                .npins = ARRAY_SIZE(uart1_modem_31_to_36_pins),
+                .modemuxs = uart1_modem_31_to_36_modemux,
+                .nmodemuxs = ARRAY_SIZE(uart1_modem_31_to_36_modemux),
+        }, {
+                .name = "uart1_modem_34_to_45_grp",
+                .pins = uart1_modem_34_to_45_pins,
+                .npins = ARRAY_SIZE(uart1_modem_34_to_45_pins),
+                .modemuxs = uart1_modem_34_to_45_modemux,
+                .nmodemuxs = ARRAY_SIZE(uart1_modem_34_to_45_modemux),
+        }, {
+                .name = "uart1_modem_80_to_85_grp",
+                .pins = uart1_modem_80_to_85_pins,
+                .npins = ARRAY_SIZE(uart1_modem_80_to_85_pins),
+                .modemuxs = uart1_modem_80_to_85_modemux,
+                .nmodemuxs = ARRAY_SIZE(uart1_modem_80_to_85_modemux),
+        },
+};
+
+static const char *const uart1_modem_grps[] = { "uart1_modem_2_to_7_grp",
+        "uart1_modem_31_to_36_grp", "uart1_modem_34_to_45_grp",
+        "uart1_modem_80_to_85_grp" };
+static struct spear_function uart1_modem_function = {
+        .name = "uart1_modem",
+        .groups = uart1_modem_grps,
+        .ngroups = ARRAY_SIZE(uart1_modem_grps),
+};
+
+/* Pad multiplexing for UART2 device */
+static const unsigned uart2_pins[] = { 0, 1 };
+static struct spear_muxreg uart2_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_FIRDA_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg uart2_ext_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_0_9_REG,
+                .mask = PMX_PL_0_1_MASK,
+                .val = PMX_UART2_PL_0_1_VAL,
+        },
+};
+
+static struct spear_modemux uart2_modemux[] = {
+        {
+                .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
+                        | SMALL_PRINTERS_MODE | EXTENDED_MODE,
+                .muxregs = uart2_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart2_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = uart2_ext_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart2_ext_muxreg),
+        },
+};
+
+static struct spear_pingroup uart2_pingroup = {
+        .name = "uart2_grp",
+        .pins = uart2_pins,
+        .npins = ARRAY_SIZE(uart2_pins),
+        .modemuxs = uart2_modemux,
+        .nmodemuxs = ARRAY_SIZE(uart2_modemux),
+};
+
+static const char *const uart2_grps[] = { "uart2_grp" };
+static struct spear_function uart2_function = {
+        .name = "uart2",
+        .groups = uart2_grps,
+        .ngroups = ARRAY_SIZE(uart2_grps),
+};
+
+/* Pad multiplexing for uart3 device */
+static const unsigned uart3_pins[][2] = { { 8, 9 }, { 15, 16 }, { 41, 42 },
+        { 52, 53 }, { 73, 74 }, { 94, 95 }, { 98, 99 } };
+
+static struct spear_muxreg uart3_ext_8_9_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_SSP_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_0_9_REG,
+                .mask = PMX_PL_8_9_MASK,
+                .val = PMX_UART3_PL_8_9_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART3_PORT_SEL_MASK,
+                .val = PMX_UART3_PORT_8_VAL,
+        },
+};
+
+static struct spear_muxreg uart3_ext_15_16_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_MII_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_10_19_REG,
+                .mask = PMX_PL_15_16_MASK,
+                .val = PMX_UART3_PL_15_16_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART3_PORT_SEL_MASK,
+                .val = PMX_UART3_PORT_15_VAL,
+        },
+};
+
+static struct spear_muxreg uart3_ext_41_42_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MODEM_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_40_49_REG,
+                .mask = PMX_PL_41_42_MASK,
+                .val = PMX_UART3_PL_41_42_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART3_PORT_SEL_MASK,
+                .val = PMX_UART3_PORT_41_VAL,
+        },
+};
+
+static struct spear_muxreg uart3_ext_52_53_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_50_59_REG,
+                .mask = PMX_PL_52_53_MASK,
+                .val = PMX_UART3_PL_52_53_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART3_PORT_SEL_MASK,
+                .val = PMX_UART3_PORT_52_VAL,
+        },
+};
+
+static struct spear_muxreg uart3_ext_73_74_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_70_79_REG,
+                .mask = PMX_PL_73_MASK | PMX_PL_74_MASK,
+                .val = PMX_UART3_PL_73_VAL | PMX_UART3_PL_74_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART3_PORT_SEL_MASK,
+                .val = PMX_UART3_PORT_73_VAL,
+        },
+};
+
+static struct spear_muxreg uart3_ext_94_95_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_90_99_REG,
+                .mask = PMX_PL_94_95_MASK,
+                .val = PMX_UART3_PL_94_95_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART3_PORT_SEL_MASK,
+                .val = PMX_UART3_PORT_94_VAL,
+        },
+};
+
+static struct spear_muxreg uart3_ext_98_99_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_90_99_REG,
+                .mask = PMX_PL_98_MASK | PMX_PL_99_MASK,
+                .val = PMX_UART3_PL_98_VAL | PMX_UART3_PL_99_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART3_PORT_SEL_MASK,
+                .val = PMX_UART3_PORT_99_VAL,
+        },
+};
+
+static struct spear_modemux uart3_modemux[][1] = {
+        {
+                /* Select signals on pins 8_9 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart3_ext_8_9_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart3_ext_8_9_muxreg),
+                },
+        }, {
+                /* Select signals on pins 15_16 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart3_ext_15_16_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart3_ext_15_16_muxreg),
+                },
+        }, {
+                /* Select signals on pins 41_42 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart3_ext_41_42_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart3_ext_41_42_muxreg),
+                },
+        }, {
+                /* Select signals on pins 52_53 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart3_ext_52_53_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart3_ext_52_53_muxreg),
+                },
+        }, {
+                /* Select signals on pins 73_74 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart3_ext_73_74_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart3_ext_73_74_muxreg),
+                },
+        }, {
+                /* Select signals on pins 94_95 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart3_ext_94_95_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart3_ext_94_95_muxreg),
+                },
+        }, {
+                /* Select signals on pins 98_99 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart3_ext_98_99_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart3_ext_98_99_muxreg),
+                },
+        },
+};
+
+static struct spear_pingroup uart3_pingroup[] = {
+        {
+                .name = "uart3_8_9_grp",
+                .pins = uart3_pins[0],
+                .npins = ARRAY_SIZE(uart3_pins[0]),
+                .modemuxs = uart3_modemux[0],
+                .nmodemuxs = ARRAY_SIZE(uart3_modemux[0]),
+        }, {
+                .name = "uart3_15_16_grp",
+                .pins = uart3_pins[1],
+                .npins = ARRAY_SIZE(uart3_pins[1]),
+                .modemuxs = uart3_modemux[1],
+                .nmodemuxs = ARRAY_SIZE(uart3_modemux[1]),
+        }, {
+                .name = "uart3_41_42_grp",
+                .pins = uart3_pins[2],
+                .npins = ARRAY_SIZE(uart3_pins[2]),
+                .modemuxs = uart3_modemux[2],
+                .nmodemuxs = ARRAY_SIZE(uart3_modemux[2]),
+        }, {
+                .name = "uart3_52_53_grp",
+                .pins = uart3_pins[3],
+                .npins = ARRAY_SIZE(uart3_pins[3]),
+                .modemuxs = uart3_modemux[3],
+                .nmodemuxs = ARRAY_SIZE(uart3_modemux[3]),
+        }, {
+                .name = "uart3_73_74_grp",
+                .pins = uart3_pins[4],
+                .npins = ARRAY_SIZE(uart3_pins[4]),
+                .modemuxs = uart3_modemux[4],
+                .nmodemuxs = ARRAY_SIZE(uart3_modemux[4]),
+        }, {
+                .name = "uart3_94_95_grp",
+                .pins = uart3_pins[5],
+                .npins = ARRAY_SIZE(uart3_pins[5]),
+                .modemuxs = uart3_modemux[5],
+                .nmodemuxs = ARRAY_SIZE(uart3_modemux[5]),
+        }, {
+                .name = "uart3_98_99_grp",
+                .pins = uart3_pins[6],
+                .npins = ARRAY_SIZE(uart3_pins[6]),
+                .modemuxs = uart3_modemux[6],
+                .nmodemuxs = ARRAY_SIZE(uart3_modemux[6]),
+        },
+};
+
+static const char *const uart3_grps[] = { "uart3_8_9_grp", "uart3_15_16_grp",
+        "uart3_41_42_grp", "uart3_52_53_grp", "uart3_73_74_grp",
+        "uart3_94_95_grp", "uart3_98_99_grp" };
+
+static struct spear_function uart3_function = {
+        .name = "uart3",
+        .groups = uart3_grps,
+        .ngroups = ARRAY_SIZE(uart3_grps),
+};
+
+/* Pad multiplexing for uart4 device */
+static const unsigned uart4_pins[][2] = { { 6, 7 }, { 13, 14 }, { 39, 40 },
+        { 71, 72 }, { 92, 93 }, { 100, 101 } };
+
+static struct spear_muxreg uart4_ext_6_7_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_SSP_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_0_9_REG,
+                .mask = PMX_PL_6_7_MASK,
+                .val = PMX_UART4_PL_6_7_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART4_PORT_SEL_MASK,
+                .val = PMX_UART4_PORT_6_VAL,
+        },
+};
+
+static struct spear_muxreg uart4_ext_13_14_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_MII_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_10_19_REG,
+                .mask = PMX_PL_13_14_MASK,
+                .val = PMX_UART4_PL_13_14_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART4_PORT_SEL_MASK,
+                .val = PMX_UART4_PORT_13_VAL,
+        },
+};
+
+static struct spear_muxreg uart4_ext_39_40_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MODEM_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_30_39_REG,
+                .mask = PMX_PL_39_MASK,
+                .val = PMX_UART4_PL_39_VAL,
+        }, {
+                .reg = IP_SEL_PAD_40_49_REG,
+                .mask = PMX_PL_40_MASK,
+                .val = PMX_UART4_PL_40_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART4_PORT_SEL_MASK,
+                .val = PMX_UART4_PORT_39_VAL,
+        },
+};
+
+static struct spear_muxreg uart4_ext_71_72_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_70_79_REG,
+                .mask = PMX_PL_71_72_MASK,
+                .val = PMX_UART4_PL_71_72_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART4_PORT_SEL_MASK,
+                .val = PMX_UART4_PORT_71_VAL,
+        },
+};
+
+static struct spear_muxreg uart4_ext_92_93_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_90_99_REG,
+                .mask = PMX_PL_92_93_MASK,
+                .val = PMX_UART4_PL_92_93_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART4_PORT_SEL_MASK,
+                .val = PMX_UART4_PORT_92_VAL,
+        },
+};
+
+static struct spear_muxreg uart4_ext_100_101_muxreg[] = {
+        {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_PL_100_101_MASK |
+                        PMX_UART4_PORT_SEL_MASK,
+                .val = PMX_UART4_PL_100_101_VAL |
+                        PMX_UART4_PORT_101_VAL,
+        },
+};
+
+static struct spear_modemux uart4_modemux[][1] = {
+        {
+                /* Select signals on pins 6_7 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart4_ext_6_7_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart4_ext_6_7_muxreg),
+                },
+        }, {
+                /* Select signals on pins 13_14 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart4_ext_13_14_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart4_ext_13_14_muxreg),
+                },
+        }, {
+                /* Select signals on pins 39_40 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart4_ext_39_40_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart4_ext_39_40_muxreg),
+                },
+        }, {
+                /* Select signals on pins 71_72 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart4_ext_71_72_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart4_ext_71_72_muxreg),
+                },
+        }, {
+                /* Select signals on pins 92_93 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart4_ext_92_93_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart4_ext_92_93_muxreg),
+                },
+        }, {
+                /* Select signals on pins 100_101_ */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart4_ext_100_101_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart4_ext_100_101_muxreg),
+                },
+        },
+};
+
+static struct spear_pingroup uart4_pingroup[] = {
+        {
+                .name = "uart4_6_7_grp",
+                .pins = uart4_pins[0],
+                .npins = ARRAY_SIZE(uart4_pins[0]),
+                .modemuxs = uart4_modemux[0],
+                .nmodemuxs = ARRAY_SIZE(uart4_modemux[0]),
+        }, {
+                .name = "uart4_13_14_grp",
+                .pins = uart4_pins[1],
+                .npins = ARRAY_SIZE(uart4_pins[1]),
+                .modemuxs = uart4_modemux[1],
+                .nmodemuxs = ARRAY_SIZE(uart4_modemux[1]),
+        }, {
+                .name = "uart4_39_40_grp",
+                .pins = uart4_pins[2],
+                .npins = ARRAY_SIZE(uart4_pins[2]),
+                .modemuxs = uart4_modemux[2],
+                .nmodemuxs = ARRAY_SIZE(uart4_modemux[2]),
+        }, {
+                .name = "uart4_71_72_grp",
+                .pins = uart4_pins[3],
+                .npins = ARRAY_SIZE(uart4_pins[3]),
+                .modemuxs = uart4_modemux[3],
+                .nmodemuxs = ARRAY_SIZE(uart4_modemux[3]),
+        }, {
+                .name = "uart4_92_93_grp",
+                .pins = uart4_pins[4],
+                .npins = ARRAY_SIZE(uart4_pins[4]),
+                .modemuxs = uart4_modemux[4],
+                .nmodemuxs = ARRAY_SIZE(uart4_modemux[4]),
+        }, {
+                .name = "uart4_100_101_grp",
+                .pins = uart4_pins[5],
+                .npins = ARRAY_SIZE(uart4_pins[5]),
+                .modemuxs = uart4_modemux[5],
+                .nmodemuxs = ARRAY_SIZE(uart4_modemux[5]),
+        },
+};
+
+static const char *const uart4_grps[] = { "uart4_6_7_grp", "uart4_13_14_grp",
+        "uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp",
+        "uart4_100_101_grp" };
+
+static struct spear_function uart4_function = {
+        .name = "uart4",
+        .groups = uart4_grps,
+        .ngroups = ARRAY_SIZE(uart4_grps),
+};
+
+/* Pad multiplexing for uart5 device */
+static const unsigned uart5_pins[][2] = { { 4, 5 }, { 37, 38 }, { 69, 70 },
+        { 90, 91 } };
+
+static struct spear_muxreg uart5_ext_4_5_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_I2C_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_0_9_REG,
+                .mask = PMX_PL_4_5_MASK,
+                .val = PMX_UART5_PL_4_5_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART5_PORT_SEL_MASK,
+                .val = PMX_UART5_PORT_4_VAL,
+        },
+};
+
+static struct spear_muxreg uart5_ext_37_38_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MODEM_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_30_39_REG,
+                .mask = PMX_PL_37_38_MASK,
+                .val = PMX_UART5_PL_37_38_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART5_PORT_SEL_MASK,
+                .val = PMX_UART5_PORT_37_VAL,
+        },
+};
+
+static struct spear_muxreg uart5_ext_69_70_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_60_69_REG,
+                .mask = PMX_PL_69_MASK,
+                .val = PMX_UART5_PL_69_VAL,
+        }, {
+                .reg = IP_SEL_PAD_70_79_REG,
+                .mask = PMX_PL_70_MASK,
+                .val = PMX_UART5_PL_70_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART5_PORT_SEL_MASK,
+                .val = PMX_UART5_PORT_69_VAL,
+        },
+};
+
+static struct spear_muxreg uart5_ext_90_91_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_90_99_REG,
+                .mask = PMX_PL_90_91_MASK,
+                .val = PMX_UART5_PL_90_91_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART5_PORT_SEL_MASK,
+                .val = PMX_UART5_PORT_90_VAL,
+        },
+};
+
+static struct spear_modemux uart5_modemux[][1] = {
+        {
+                /* Select signals on pins 4_5 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart5_ext_4_5_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart5_ext_4_5_muxreg),
+                },
+        }, {
+                /* Select signals on pins 37_38 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart5_ext_37_38_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart5_ext_37_38_muxreg),
+                },
+        }, {
+                /* Select signals on pins 69_70 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart5_ext_69_70_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart5_ext_69_70_muxreg),
+                },
+        }, {
+                /* Select signals on pins 90_91 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart5_ext_90_91_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart5_ext_90_91_muxreg),
+                },
+        },
+};
+
+static struct spear_pingroup uart5_pingroup[] = {
+        {
+                .name = "uart5_4_5_grp",
+                .pins = uart5_pins[0],
+                .npins = ARRAY_SIZE(uart5_pins[0]),
+                .modemuxs = uart5_modemux[0],
+                .nmodemuxs = ARRAY_SIZE(uart5_modemux[0]),
+        }, {
+                .name = "uart5_37_38_grp",
+                .pins = uart5_pins[1],
+                .npins = ARRAY_SIZE(uart5_pins[1]),
+                .modemuxs = uart5_modemux[1],
+                .nmodemuxs = ARRAY_SIZE(uart5_modemux[1]),
+        }, {
+                .name = "uart5_69_70_grp",
+                .pins = uart5_pins[2],
+                .npins = ARRAY_SIZE(uart5_pins[2]),
+                .modemuxs = uart5_modemux[2],
+                .nmodemuxs = ARRAY_SIZE(uart5_modemux[2]),
+        }, {
+                .name = "uart5_90_91_grp",
+                .pins = uart5_pins[3],
+                .npins = ARRAY_SIZE(uart5_pins[3]),
+                .modemuxs = uart5_modemux[3],
+                .nmodemuxs = ARRAY_SIZE(uart5_modemux[3]),
+        },
+};
+
+static const char *const uart5_grps[] = { "uart5_4_5_grp", "uart5_37_38_grp",
+        "uart5_69_70_grp", "uart5_90_91_grp" };
+static struct spear_function uart5_function = {
+        .name = "uart5",
+        .groups = uart5_grps,
+        .ngroups = ARRAY_SIZE(uart5_grps),
+};
+
+/* Pad multiplexing for uart6 device */
+static const unsigned uart6_pins[][2] = { { 2, 3 }, { 88, 89 } };
+static struct spear_muxreg uart6_ext_2_3_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_0_9_REG,
+                .mask = PMX_PL_2_3_MASK,
+                .val = PMX_UART6_PL_2_3_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART6_PORT_SEL_MASK,
+                .val = PMX_UART6_PORT_2_VAL,
+        },
+};
+
+static struct spear_muxreg uart6_ext_88_89_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_80_89_REG,
+                .mask = PMX_PL_88_89_MASK,
+                .val = PMX_UART6_PL_88_89_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART6_PORT_SEL_MASK,
+                .val = PMX_UART6_PORT_88_VAL,
+        },
+};
+
+static struct spear_modemux uart6_modemux[][1] = {
+        {
+                /* Select signals on pins 2_3 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart6_ext_2_3_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart6_ext_2_3_muxreg),
+                },
+        }, {
+                /* Select signals on pins 88_89 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart6_ext_88_89_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart6_ext_88_89_muxreg),
+                },
+        },
+};
+
+static struct spear_pingroup uart6_pingroup[] = {
+        {
+                .name = "uart6_2_3_grp",
+                .pins = uart6_pins[0],
+                .npins = ARRAY_SIZE(uart6_pins[0]),
+                .modemuxs = uart6_modemux[0],
+                .nmodemuxs = ARRAY_SIZE(uart6_modemux[0]),
+        }, {
+                .name = "uart6_88_89_grp",
+                .pins = uart6_pins[1],
+                .npins = ARRAY_SIZE(uart6_pins[1]),
+                .modemuxs = uart6_modemux[1],
+                .nmodemuxs = ARRAY_SIZE(uart6_modemux[1]),
+        },
+};
+
+static const char *const uart6_grps[] = { "uart6_2_3_grp", "uart6_88_89_grp" };
+static struct spear_function uart6_function = {
+        .name = "uart6",
+        .groups = uart6_grps,
+        .ngroups = ARRAY_SIZE(uart6_grps),
+};
+
+/* UART - RS485 pmx */
+static const unsigned rs485_pins[] = { 77, 78, 79 };
+static struct spear_muxreg rs485_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_70_79_REG,
+                .mask = PMX_PL_77_78_79_MASK,
+                .val = PMX_RS485_PL_77_78_79_VAL,
+        },
+};
+
+static struct spear_modemux rs485_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = rs485_muxreg,
+                .nmuxregs = ARRAY_SIZE(rs485_muxreg),
+        },
+};
+
+static struct spear_pingroup rs485_pingroup = {
+        .name = "rs485_grp",
+        .pins = rs485_pins,
+        .npins = ARRAY_SIZE(rs485_pins),
+        .modemuxs = rs485_modemux,
+        .nmodemuxs = ARRAY_SIZE(rs485_modemux),
+};
+
+static const char *const rs485_grps[] = { "rs485_grp" };
+static struct spear_function rs485_function = {
+        .name = "rs485",
+        .groups = rs485_grps,
+        .ngroups = ARRAY_SIZE(rs485_grps),
+};
+
+/* Pad multiplexing for Touchscreen device */
+static const unsigned touchscreen_pins[] = { 5, 36 };
+static struct spear_muxreg touchscreen_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_I2C_MASK | PMX_SSP_CS_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg touchscreen_ext_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_0_9_REG,
+                .mask = PMX_PL_5_MASK,
+                .val = PMX_TOUCH_Y_PL_5_VAL,
+        }, {
+                .reg = IP_SEL_PAD_30_39_REG,
+                .mask = PMX_PL_36_MASK,
+                .val = PMX_TOUCH_X_PL_36_VAL,
+        },
+};
+
+static struct spear_modemux touchscreen_modemux[] = {
+        {
+                .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE,
+                .muxregs = touchscreen_muxreg,
+                .nmuxregs = ARRAY_SIZE(touchscreen_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = touchscreen_ext_muxreg,
+                .nmuxregs = ARRAY_SIZE(touchscreen_ext_muxreg),
+        },
+};
+
+static struct spear_pingroup touchscreen_pingroup = {
+        .name = "touchscreen_grp",
+        .pins = touchscreen_pins,
+        .npins = ARRAY_SIZE(touchscreen_pins),
+        .modemuxs = touchscreen_modemux,
+        .nmodemuxs = ARRAY_SIZE(touchscreen_modemux),
+};
+
+static const char *const touchscreen_grps[] = { "touchscreen_grp" };
+static struct spear_function touchscreen_function = {
+        .name = "touchscreen",
+        .groups = touchscreen_grps,
+        .ngroups = ARRAY_SIZE(touchscreen_grps),
+};
+
+/* Pad multiplexing for CAN device */
+static const unsigned can0_pins[] = { 32, 33 };
+static struct spear_muxreg can0_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg can0_ext_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_30_39_REG,
+                .mask = PMX_PL_32_33_MASK,
+                .val = PMX_CAN0_PL_32_33_VAL,
+        },
+};
+
+static struct spear_modemux can0_modemux[] = {
+        {
+                .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
+                        | EXTENDED_MODE,
+                .muxregs = can0_muxreg,
+                .nmuxregs = ARRAY_SIZE(can0_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = can0_ext_muxreg,
+                .nmuxregs = ARRAY_SIZE(can0_ext_muxreg),
+        },
+};
+
+static struct spear_pingroup can0_pingroup = {
+        .name = "can0_grp",
+        .pins = can0_pins,
+        .npins = ARRAY_SIZE(can0_pins),
+        .modemuxs = can0_modemux,
+        .nmodemuxs = ARRAY_SIZE(can0_modemux),
+};
+
+static const char *const can0_grps[] = { "can0_grp" };
+static struct spear_function can0_function = {
+        .name = "can0",
+        .groups = can0_grps,
+        .ngroups = ARRAY_SIZE(can0_grps),
+};
+
+static const unsigned can1_pins[] = { 30, 31 };
+static struct spear_muxreg can1_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg can1_ext_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_30_39_REG,
+                .mask = PMX_PL_30_31_MASK,
+                .val = PMX_CAN1_PL_30_31_VAL,
+        },
+};
+
+static struct spear_modemux can1_modemux[] = {
+        {
+                .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
+                        | EXTENDED_MODE,
+                .muxregs = can1_muxreg,
+                .nmuxregs = ARRAY_SIZE(can1_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = can1_ext_muxreg,
+                .nmuxregs = ARRAY_SIZE(can1_ext_muxreg),
+        },
+};
+
+static struct spear_pingroup can1_pingroup = {
+        .name = "can1_grp",
+        .pins = can1_pins,
+        .npins = ARRAY_SIZE(can1_pins),
+        .modemuxs = can1_modemux,
+        .nmodemuxs = ARRAY_SIZE(can1_modemux),
+};
+
+static const char *const can1_grps[] = { "can1_grp" };
+static struct spear_function can1_function = {
+        .name = "can1",
+        .groups = can1_grps,
+        .ngroups = ARRAY_SIZE(can1_grps),
+};
+
+/* Pad multiplexing for PWM0_1 device */
+static const unsigned pwm0_1_pins[][2] = { { 37, 38 }, { 14, 15 }, { 8, 9 },
+        { 30, 31 }, { 42, 43 }, { 59, 60 }, { 88, 89 } };
+
+static struct spear_muxreg pwm0_1_pin_8_9_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_SSP_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_0_9_REG,
+                .mask = PMX_PL_8_9_MASK,
+                .val = PMX_PWM_0_1_PL_8_9_VAL,
+        },
+};
+
+static struct spear_muxreg pwm0_1_autoexpsmallpri_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_MII_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg pwm0_1_pin_14_15_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_10_19_REG,
+                .mask = PMX_PL_14_MASK | PMX_PL_15_MASK,
+                .val = PMX_PWM1_PL_14_VAL | PMX_PWM0_PL_15_VAL,
+        },
+};
+
+static struct spear_muxreg pwm0_1_pin_30_31_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_30_39_REG,
+                .mask = PMX_PL_30_MASK | PMX_PL_31_MASK,
+                .val = PMX_PWM1_EXT_PL_30_VAL | PMX_PWM0_EXT_PL_31_VAL,
+        },
+};
+
+static struct spear_muxreg pwm0_1_net_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MODEM_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg pwm0_1_pin_37_38_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_30_39_REG,
+                .mask = PMX_PL_37_38_MASK,
+                .val = PMX_PWM0_1_PL_37_38_VAL,
+        },
+};
+
+static struct spear_muxreg pwm0_1_pin_42_43_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_0_1_MASK ,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_40_49_REG,
+                .mask = PMX_PL_42_MASK | PMX_PL_43_MASK,
+                .val = PMX_PWM1_PL_42_VAL |
+                        PMX_PWM0_PL_43_VAL,
+        },
+};
+
+static struct spear_muxreg pwm0_1_pin_59_60_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_50_59_REG,
+                .mask = PMX_PL_59_MASK,
+                .val = PMX_PWM1_PL_59_VAL,
+        }, {
+                .reg = IP_SEL_PAD_60_69_REG,
+                .mask = PMX_PL_60_MASK,
+                .val = PMX_PWM0_PL_60_VAL,
+        },
+};
+
+static struct spear_muxreg pwm0_1_pin_88_89_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_80_89_REG,
+                .mask = PMX_PL_88_89_MASK,
+                .val = PMX_PWM0_1_PL_88_89_VAL,
+        },
+};
+
+static struct spear_modemux pwm0_1_pin_8_9_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm0_1_pin_8_9_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm0_1_pin_8_9_muxreg),
+        },
+};
+
+static struct spear_modemux pwm0_1_pin_14_15_modemux[] = {
+        {
+                .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE,
+                .muxregs = pwm0_1_autoexpsmallpri_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm0_1_autoexpsmallpri_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm0_1_pin_14_15_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm0_1_pin_14_15_muxreg),
+        },
+};
+
+static struct spear_modemux pwm0_1_pin_30_31_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm0_1_pin_30_31_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm0_1_pin_30_31_muxreg),
+        },
+};
+
+static struct spear_modemux pwm0_1_pin_37_38_modemux[] = {
+        {
+                .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
+                .muxregs = pwm0_1_net_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm0_1_net_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm0_1_pin_37_38_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm0_1_pin_37_38_muxreg),
+        },
+};
+
+static struct spear_modemux pwm0_1_pin_42_43_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm0_1_pin_42_43_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm0_1_pin_42_43_muxreg),
+        },
+};
+
+static struct spear_modemux pwm0_1_pin_59_60_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm0_1_pin_59_60_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm0_1_pin_59_60_muxreg),
+        },
+};
+
+static struct spear_modemux pwm0_1_pin_88_89_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm0_1_pin_88_89_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm0_1_pin_88_89_muxreg),
+        },
+};
+
+static struct spear_pingroup pwm0_1_pingroup[] = {
+        {
+                .name = "pwm0_1_pin_8_9_grp",
+                .pins = pwm0_1_pins[0],
+                .npins = ARRAY_SIZE(pwm0_1_pins[0]),
+                .modemuxs = pwm0_1_pin_8_9_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_8_9_modemux),
+        }, {
+                .name = "pwm0_1_pin_14_15_grp",
+                .pins = pwm0_1_pins[1],
+                .npins = ARRAY_SIZE(pwm0_1_pins[1]),
+                .modemuxs = pwm0_1_pin_14_15_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_14_15_modemux),
+        }, {
+                .name = "pwm0_1_pin_30_31_grp",
+                .pins = pwm0_1_pins[2],
+                .npins = ARRAY_SIZE(pwm0_1_pins[2]),
+                .modemuxs = pwm0_1_pin_30_31_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_30_31_modemux),
+        }, {
+                .name = "pwm0_1_pin_37_38_grp",
+                .pins = pwm0_1_pins[3],
+                .npins = ARRAY_SIZE(pwm0_1_pins[3]),
+                .modemuxs = pwm0_1_pin_37_38_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_37_38_modemux),
+        }, {
+                .name = "pwm0_1_pin_42_43_grp",
+                .pins = pwm0_1_pins[4],
+                .npins = ARRAY_SIZE(pwm0_1_pins[4]),
+                .modemuxs = pwm0_1_pin_42_43_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_42_43_modemux),
+        }, {
+                .name = "pwm0_1_pin_59_60_grp",
+                .pins = pwm0_1_pins[5],
+                .npins = ARRAY_SIZE(pwm0_1_pins[5]),
+                .modemuxs = pwm0_1_pin_59_60_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_59_60_modemux),
+        }, {
+                .name = "pwm0_1_pin_88_89_grp",
+                .pins = pwm0_1_pins[6],
+                .npins = ARRAY_SIZE(pwm0_1_pins[6]),
+                .modemuxs = pwm0_1_pin_88_89_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_88_89_modemux),
+        },
+};
+
+static const char *const pwm0_1_grps[] = { "pwm0_1_pin_8_9_grp",
+        "pwm0_1_pin_14_15_grp", "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp",
+        "pwm0_1_pin_42_43_grp", "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp"
+};
+
+static struct spear_function pwm0_1_function = {
+        .name = "pwm0_1",
+        .groups = pwm0_1_grps,
+        .ngroups = ARRAY_SIZE(pwm0_1_grps),
+};
+
+/* Pad multiplexing for PWM2 device */
+static const unsigned pwm2_pins[][1] = { { 7 }, { 13 }, { 29 }, { 34 }, { 41 },
+        { 58 }, { 87 } };
+static struct spear_muxreg pwm2_net_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_SSP_CS_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg pwm2_pin_7_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_0_9_REG,
+                .mask = PMX_PL_7_MASK,
+                .val = PMX_PWM_2_PL_7_VAL,
+        },
+};
+
+static struct spear_muxreg pwm2_autoexpsmallpri_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_MII_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg pwm2_pin_13_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_10_19_REG,
+                .mask = PMX_PL_13_MASK,
+                .val = PMX_PWM2_PL_13_VAL,
+        },
+};
+
+static struct spear_muxreg pwm2_pin_29_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_GPIO_PIN1_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_20_29_REG,
+                .mask = PMX_PL_29_MASK,
+                .val = PMX_PWM_2_PL_29_VAL,
+        },
+};
+
+static struct spear_muxreg pwm2_pin_34_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_SSP_CS_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_30_39_REG,
+                .mask = PMX_PL_34_MASK,
+                .val = PMX_PWM2_PL_34_VAL,
+        },
+};
+
+static struct spear_muxreg pwm2_pin_41_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MODEM_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_40_49_REG,
+                .mask = PMX_PL_41_MASK,
+                .val = PMX_PWM2_PL_41_VAL,
+        },
+};
+
+static struct spear_muxreg pwm2_pin_58_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_50_59_REG,
+                .mask = PMX_PL_58_MASK,
+                .val = PMX_PWM2_PL_58_VAL,
+        },
+};
+
+static struct spear_muxreg pwm2_pin_87_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_80_89_REG,
+                .mask = PMX_PL_87_MASK,
+                .val = PMX_PWM2_PL_87_VAL,
+        },
+};
+
+static struct spear_modemux pwm2_pin_7_modemux[] = {
+        {
+                .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
+                .muxregs = pwm2_net_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm2_net_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm2_pin_7_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm2_pin_7_muxreg),
+        },
+};
+static struct spear_modemux pwm2_pin_13_modemux[] = {
+        {
+                .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE,
+                .muxregs = pwm2_autoexpsmallpri_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm2_autoexpsmallpri_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm2_pin_13_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm2_pin_13_muxreg),
+        },
+};
+static struct spear_modemux pwm2_pin_29_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm2_pin_29_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm2_pin_29_muxreg),
+        },
+};
+static struct spear_modemux pwm2_pin_34_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm2_pin_34_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm2_pin_34_muxreg),
+        },
+};
+
+static struct spear_modemux pwm2_pin_41_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm2_pin_41_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm2_pin_41_muxreg),
+        },
+};
+
+static struct spear_modemux pwm2_pin_58_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm2_pin_58_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm2_pin_58_muxreg),
+        },
+};
+
+static struct spear_modemux pwm2_pin_87_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm2_pin_87_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm2_pin_87_muxreg),
+        },
+};
+
+static struct spear_pingroup pwm2_pingroup[] = {
+        {
+                .name = "pwm2_pin_7_grp",
+                .pins = pwm2_pins[0],
+                .npins = ARRAY_SIZE(pwm2_pins[0]),
+                .modemuxs = pwm2_pin_7_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm2_pin_7_modemux),
+        }, {
+                .name = "pwm2_pin_13_grp",
+                .pins = pwm2_pins[1],
+                .npins = ARRAY_SIZE(pwm2_pins[1]),
+                .modemuxs = pwm2_pin_13_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm2_pin_13_modemux),
+        }, {
+                .name = "pwm2_pin_29_grp",
+                .pins = pwm2_pins[2],
+                .npins = ARRAY_SIZE(pwm2_pins[2]),
+                .modemuxs = pwm2_pin_29_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm2_pin_29_modemux),
+        }, {
+                .name = "pwm2_pin_34_grp",
+                .pins = pwm2_pins[3],
+                .npins = ARRAY_SIZE(pwm2_pins[3]),
+                .modemuxs = pwm2_pin_34_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm2_pin_34_modemux),
+        }, {
+                .name = "pwm2_pin_41_grp",
+                .pins = pwm2_pins[4],
+                .npins = ARRAY_SIZE(pwm2_pins[4]),
+                .modemuxs = pwm2_pin_41_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm2_pin_41_modemux),
+        }, {
+                .name = "pwm2_pin_58_grp",
+                .pins = pwm2_pins[5],
+                .npins = ARRAY_SIZE(pwm2_pins[5]),
+                .modemuxs = pwm2_pin_58_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm2_pin_58_modemux),
+        }, {
+                .name = "pwm2_pin_87_grp",
+                .pins = pwm2_pins[6],
+                .npins = ARRAY_SIZE(pwm2_pins[6]),
+                .modemuxs = pwm2_pin_87_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm2_pin_87_modemux),
+        },
+};
+
+static const char *const pwm2_grps[] = { "pwm2_pin_7_grp", "pwm2_pin_13_grp",
+        "pwm2_pin_29_grp", "pwm2_pin_34_grp", "pwm2_pin_41_grp",
+        "pwm2_pin_58_grp", "pwm2_pin_87_grp" };
+static struct spear_function pwm2_function = {
+        .name = "pwm2",
+        .groups = pwm2_grps,
+        .ngroups = ARRAY_SIZE(pwm2_grps),
+};
+
+/* Pad multiplexing for PWM3 device */
+static const unsigned pwm3_pins[][1] = { { 6 }, { 12 }, { 28 }, { 40 }, { 57 },
+        { 86 } };
+static struct spear_muxreg pwm3_pin_6_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_SSP_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_0_9_REG,
+                .mask = PMX_PL_6_MASK,
+                .val = PMX_PWM_3_PL_6_VAL,
+        },
+};
+
+static struct spear_muxreg pwm3_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_MII_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg pwm3_pin_12_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_10_19_REG,
+                .mask = PMX_PL_12_MASK,
+                .val = PMX_PWM3_PL_12_VAL,
+        },
+};
+
+static struct spear_muxreg pwm3_pin_28_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_GPIO_PIN0_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_20_29_REG,
+                .mask = PMX_PL_28_MASK,
+                .val = PMX_PWM_3_PL_28_VAL,
+        },
+};
+
+static struct spear_muxreg pwm3_pin_40_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MODEM_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_40_49_REG,
+                .mask = PMX_PL_40_MASK,
+                .val = PMX_PWM3_PL_40_VAL,
+        },
+};
+
+static struct spear_muxreg pwm3_pin_57_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_50_59_REG,
+                .mask = PMX_PL_57_MASK,
+                .val = PMX_PWM3_PL_57_VAL,
+        },
+};
+
+static struct spear_muxreg pwm3_pin_86_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_80_89_REG,
+                .mask = PMX_PL_86_MASK,
+                .val = PMX_PWM3_PL_86_VAL,
+        },
+};
+
+static struct spear_modemux pwm3_pin_6_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm3_pin_6_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm3_pin_6_muxreg),
+        },
+};
+
+static struct spear_modemux pwm3_pin_12_modemux[] = {
+        {
+                .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE |
+                        AUTO_NET_SMII_MODE | EXTENDED_MODE,
+                .muxregs = pwm3_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm3_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm3_pin_12_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm3_pin_12_muxreg),
+        },
+};
+
+static struct spear_modemux pwm3_pin_28_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm3_pin_28_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm3_pin_28_muxreg),
+        },
+};
+
+static struct spear_modemux pwm3_pin_40_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm3_pin_40_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm3_pin_40_muxreg),
+        },
+};
+
+static struct spear_modemux pwm3_pin_57_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm3_pin_57_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm3_pin_57_muxreg),
+        },
+};
+
+static struct spear_modemux pwm3_pin_86_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm3_pin_86_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm3_pin_86_muxreg),
+        },
+};
+
+static struct spear_pingroup pwm3_pingroup[] = {
+        {
+                .name = "pwm3_pin_6_grp",
+                .pins = pwm3_pins[0],
+                .npins = ARRAY_SIZE(pwm3_pins[0]),
+                .modemuxs = pwm3_pin_6_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm3_pin_6_modemux),
+        }, {
+                .name = "pwm3_pin_12_grp",
+                .pins = pwm3_pins[1],
+                .npins = ARRAY_SIZE(pwm3_pins[1]),
+                .modemuxs = pwm3_pin_12_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm3_pin_12_modemux),
+        }, {
+                .name = "pwm3_pin_28_grp",
+                .pins = pwm3_pins[2],
+                .npins = ARRAY_SIZE(pwm3_pins[2]),
+                .modemuxs = pwm3_pin_28_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm3_pin_28_modemux),
+        }, {
+                .name = "pwm3_pin_40_grp",
+                .pins = pwm3_pins[3],
+                .npins = ARRAY_SIZE(pwm3_pins[3]),
+                .modemuxs = pwm3_pin_40_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm3_pin_40_modemux),
+        }, {
+                .name = "pwm3_pin_57_grp",
+                .pins = pwm3_pins[4],
+                .npins = ARRAY_SIZE(pwm3_pins[4]),
+                .modemuxs = pwm3_pin_57_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm3_pin_57_modemux),
+        }, {
+                .name = "pwm3_pin_86_grp",
+                .pins = pwm3_pins[5],
+                .npins = ARRAY_SIZE(pwm3_pins[5]),
+                .modemuxs = pwm3_pin_86_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm3_pin_86_modemux),
+        },
+};
+
+static const char *const pwm3_grps[] = { "pwm3_pin_6_grp", "pwm3_pin_12_grp",
+        "pwm3_pin_28_grp", "pwm3_pin_40_grp", "pwm3_pin_57_grp",
+        "pwm3_pin_86_grp" };
+static struct spear_function pwm3_function = {
+        .name = "pwm3",
+        .groups = pwm3_grps,
+        .ngroups = ARRAY_SIZE(pwm3_grps),
+};
+
+/* Pad multiplexing for SSP1 device */
+static const unsigned ssp1_pins[][2] = { { 17, 20 }, { 36, 39 }, { 48, 51 },
+        { 65, 68 }, { 94, 97 } };
+static struct spear_muxreg ssp1_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_MII_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg ssp1_ext_17_20_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_10_19_REG,
+                .mask = PMX_PL_17_18_MASK | PMX_PL_19_MASK,
+                .val = PMX_SSP1_PL_17_18_19_20_VAL,
+        }, {
+                .reg = IP_SEL_PAD_20_29_REG,
+                .mask = PMX_PL_20_MASK,
+                .val = PMX_SSP1_PL_17_18_19_20_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_SSP1_PORT_SEL_MASK,
+                .val = PMX_SSP1_PORT_17_TO_20_VAL,
+        },
+};
+
+static struct spear_muxreg ssp1_ext_36_39_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_30_39_REG,
+                .mask = PMX_PL_36_MASK | PMX_PL_37_38_MASK | PMX_PL_39_MASK,
+                .val = PMX_SSP1_PL_36_VAL | PMX_SSP1_PL_37_38_VAL |
+                        PMX_SSP1_PL_39_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_SSP1_PORT_SEL_MASK,
+                .val = PMX_SSP1_PORT_36_TO_39_VAL,
+        },
+};
+
+static struct spear_muxreg ssp1_ext_48_51_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_40_49_REG,
+                .mask = PMX_PL_48_49_MASK,
+                .val = PMX_SSP1_PL_48_49_VAL,
+        }, {
+                .reg = IP_SEL_PAD_50_59_REG,
+                .mask = PMX_PL_50_51_MASK,
+                .val = PMX_SSP1_PL_50_51_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_SSP1_PORT_SEL_MASK,
+                .val = PMX_SSP1_PORT_48_TO_51_VAL,
+        },
+};
+
+static struct spear_muxreg ssp1_ext_65_68_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_60_69_REG,
+                .mask = PMX_PL_65_TO_68_MASK,
+                .val = PMX_SSP1_PL_65_TO_68_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_SSP1_PORT_SEL_MASK,
+                .val = PMX_SSP1_PORT_65_TO_68_VAL,
+        },
+};
+
+static struct spear_muxreg ssp1_ext_94_97_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_90_99_REG,
+                .mask = PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
+                .val = PMX_SSP1_PL_94_95_VAL | PMX_SSP1_PL_96_97_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_SSP1_PORT_SEL_MASK,
+                .val = PMX_SSP1_PORT_94_TO_97_VAL,
+        },
+};
+
+static struct spear_modemux ssp1_17_20_modemux[] = {
+        {
+                .modes = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE |
+                        EXTENDED_MODE,
+                .muxregs = ssp1_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp1_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = ssp1_ext_17_20_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp1_ext_17_20_muxreg),
+        },
+};
+
+static struct spear_modemux ssp1_36_39_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = ssp1_ext_36_39_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp1_ext_36_39_muxreg),
+        },
+};
+
+static struct spear_modemux ssp1_48_51_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = ssp1_ext_48_51_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp1_ext_48_51_muxreg),
+        },
+};
+static struct spear_modemux ssp1_65_68_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = ssp1_ext_65_68_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp1_ext_65_68_muxreg),
+        },
+};
+
+static struct spear_modemux ssp1_94_97_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = ssp1_ext_94_97_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp1_ext_94_97_muxreg),
+        },
+};
+
+static struct spear_pingroup ssp1_pingroup[] = {
+        {
+                .name = "ssp1_17_20_grp",
+                .pins = ssp1_pins[0],
+                .npins = ARRAY_SIZE(ssp1_pins[0]),
+                .modemuxs = ssp1_17_20_modemux,
+                .nmodemuxs = ARRAY_SIZE(ssp1_17_20_modemux),
+        }, {
+                .name = "ssp1_36_39_grp",
+                .pins = ssp1_pins[1],
+                .npins = ARRAY_SIZE(ssp1_pins[1]),
+                .modemuxs = ssp1_36_39_modemux,
+                .nmodemuxs = ARRAY_SIZE(ssp1_36_39_modemux),
+        }, {
+                .name = "ssp1_48_51_grp",
+                .pins = ssp1_pins[2],
+                .npins = ARRAY_SIZE(ssp1_pins[2]),
+                .modemuxs = ssp1_48_51_modemux,
+                .nmodemuxs = ARRAY_SIZE(ssp1_48_51_modemux),
+        }, {
+                .name = "ssp1_65_68_grp",
+                .pins = ssp1_pins[3],
+                .npins = ARRAY_SIZE(ssp1_pins[3]),
+                .modemuxs = ssp1_65_68_modemux,
+                .nmodemuxs = ARRAY_SIZE(ssp1_65_68_modemux),
+        }, {
+                .name = "ssp1_94_97_grp",
+                .pins = ssp1_pins[4],
+                .npins = ARRAY_SIZE(ssp1_pins[4]),
+                .modemuxs = ssp1_94_97_modemux,
+                .nmodemuxs = ARRAY_SIZE(ssp1_94_97_modemux),
+        },
+};
+
+static const char *const ssp1_grps[] = { "ssp1_17_20_grp", "ssp1_36_39_grp",
+        "ssp1_48_51_grp", "ssp1_65_68_grp", "ssp1_94_97_grp"
+};
+static struct spear_function ssp1_function = {
+        .name = "ssp1",
+        .groups = ssp1_grps,
+        .ngroups = ARRAY_SIZE(ssp1_grps),
+};
+
+/* Pad multiplexing for SSP2 device */
+static const unsigned ssp2_pins[][2] = { { 13, 16 }, { 32, 35 }, { 44, 47 },
+        { 61, 64 }, { 90, 93 } };
+static struct spear_muxreg ssp2_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_MII_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg ssp2_ext_13_16_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_10_19_REG,
+                .mask = PMX_PL_13_14_MASK | PMX_PL_15_16_MASK,
+                .val = PMX_SSP2_PL_13_14_15_16_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_SSP2_PORT_SEL_MASK,
+                .val = PMX_SSP2_PORT_13_TO_16_VAL,
+        },
+};
+
+static struct spear_muxreg ssp2_ext_32_35_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_SSP_CS_MASK | PMX_GPIO_PIN4_MASK |
+                        PMX_GPIO_PIN5_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_30_39_REG,
+                .mask = PMX_PL_32_33_MASK | PMX_PL_34_MASK | PMX_PL_35_MASK,
+                .val = PMX_SSP2_PL_32_33_VAL | PMX_SSP2_PL_34_VAL |
+                        PMX_SSP2_PL_35_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_SSP2_PORT_SEL_MASK,
+                .val = PMX_SSP2_PORT_32_TO_35_VAL,
+        },
+};
+
+static struct spear_muxreg ssp2_ext_44_47_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_40_49_REG,
+                .mask = PMX_PL_44_45_MASK | PMX_PL_46_47_MASK,
+                .val = PMX_SSP2_PL_44_45_VAL | PMX_SSP2_PL_46_47_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_SSP2_PORT_SEL_MASK,
+                .val = PMX_SSP2_PORT_44_TO_47_VAL,
+        },
+};
+
+static struct spear_muxreg ssp2_ext_61_64_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_60_69_REG,
+                .mask = PMX_PL_61_TO_64_MASK,
+                .val = PMX_SSP2_PL_61_TO_64_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_SSP2_PORT_SEL_MASK,
+                .val = PMX_SSP2_PORT_61_TO_64_VAL,
+        },
+};
+
+static struct spear_muxreg ssp2_ext_90_93_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_90_99_REG,
+                .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK,
+                .val = PMX_SSP2_PL_90_91_VAL | PMX_SSP2_PL_92_93_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_SSP2_PORT_SEL_MASK,
+                .val = PMX_SSP2_PORT_90_TO_93_VAL,
+        },
+};
+
+static struct spear_modemux ssp2_13_16_modemux[] = {
+        {
+                .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE,
+                .muxregs = ssp2_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp2_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = ssp2_ext_13_16_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp2_ext_13_16_muxreg),
+        },
+};
+
+static struct spear_modemux ssp2_32_35_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = ssp2_ext_32_35_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp2_ext_32_35_muxreg),
+        },
+};
+
+static struct spear_modemux ssp2_44_47_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = ssp2_ext_44_47_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp2_ext_44_47_muxreg),
+        },
+};
+
+static struct spear_modemux ssp2_61_64_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = ssp2_ext_61_64_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp2_ext_61_64_muxreg),
+        },
+};
+
+static struct spear_modemux ssp2_90_93_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = ssp2_ext_90_93_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp2_ext_90_93_muxreg),
+        },
+};
+
+static struct spear_pingroup ssp2_pingroup[] = {
+        {
+                .name = "ssp2_13_16_grp",
+                .pins = ssp2_pins[0],
+                .npins = ARRAY_SIZE(ssp2_pins[0]),
+                .modemuxs = ssp2_13_16_modemux,
+                .nmodemuxs = ARRAY_SIZE(ssp2_13_16_modemux),
+        }, {
+                .name = "ssp2_32_35_grp",
+                .pins = ssp2_pins[1],
+                .npins = ARRAY_SIZE(ssp2_pins[1]),
+                .modemuxs = ssp2_32_35_modemux,
+                .nmodemuxs = ARRAY_SIZE(ssp2_32_35_modemux),
+        }, {
+                .name = "ssp2_44_47_grp",
+                .pins = ssp2_pins[2],
+                .npins = ARRAY_SIZE(ssp2_pins[2]),
+                .modemuxs = ssp2_44_47_modemux,
+                .nmodemuxs = ARRAY_SIZE(ssp2_44_47_modemux),
+        }, {
+                .name = "ssp2_61_64_grp",
+                .pins = ssp2_pins[3],
+                .npins = ARRAY_SIZE(ssp2_pins[3]),
+                .modemuxs = ssp2_61_64_modemux,
+                .nmodemuxs = ARRAY_SIZE(ssp2_61_64_modemux),
+        }, {
+                .name = "ssp2_90_93_grp",
+                .pins = ssp2_pins[4],
+                .npins = ARRAY_SIZE(ssp2_pins[4]),
+                .modemuxs = ssp2_90_93_modemux,
+                .nmodemuxs = ARRAY_SIZE(ssp2_90_93_modemux),
+        },
+};
+
+static const char *const ssp2_grps[] = { "ssp2_13_16_grp", "ssp2_32_35_grp",
+        "ssp2_44_47_grp", "ssp2_61_64_grp", "ssp2_90_93_grp" };
+static struct spear_function ssp2_function = {
+        .name = "ssp2",
+        .groups = ssp2_grps,
+        .ngroups = ARRAY_SIZE(ssp2_grps),
+};
+
+/* Pad multiplexing for cadence mii2 as mii device */
+static const unsigned mii2_pins[] = { 80, 81, 82, 83, 84, 85, 86, 87, 88, 89,
+        90, 91, 92, 93, 94, 95, 96, 97 };
+static struct spear_muxreg mii2_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_80_89_REG,
+                .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
+                        PMX_PL_88_89_MASK,
+                .val = PMX_MII2_PL_80_TO_85_VAL | PMX_MII2_PL_86_87_VAL |
+                        PMX_MII2_PL_88_89_VAL,
+        }, {
+                .reg = IP_SEL_PAD_90_99_REG,
+                .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
+                        PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
+                .val = PMX_MII2_PL_90_91_VAL | PMX_MII2_PL_92_93_VAL |
+                        PMX_MII2_PL_94_95_VAL | PMX_MII2_PL_96_97_VAL,
+        }, {
+                .reg = EXT_CTRL_REG,
+                .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
+                        (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
+                        MII_MDIO_MASK,
+                .val = (MAC_MODE_MII << MAC2_MODE_SHIFT) |
+                        (MAC_MODE_MII << MAC1_MODE_SHIFT) |
+                        MII_MDIO_81_VAL,
+        },
+};
+
+static struct spear_modemux mii2_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = mii2_muxreg,
+                .nmuxregs = ARRAY_SIZE(mii2_muxreg),
+        },
+};
+
+static struct spear_pingroup mii2_pingroup = {
+        .name = "mii2_grp",
+        .pins = mii2_pins,
+        .npins = ARRAY_SIZE(mii2_pins),
+        .modemuxs = mii2_modemux,
+        .nmodemuxs = ARRAY_SIZE(mii2_modemux),
+};
+
+static const char *const mii2_grps[] = { "mii2_grp" };
+static struct spear_function mii2_function = {
+        .name = "mii2",
+        .groups = mii2_grps,
+        .ngroups = ARRAY_SIZE(mii2_grps),
+};
+
+/* Pad multiplexing for cadence mii 1_2 as smii or rmii device */
+static const unsigned smii0_1_pins[] = { 10, 11, 13, 14, 15, 16, 17, 18, 19, 20,
+        21, 22, 23, 24, 25, 26, 27 };
+static const unsigned rmii0_1_pins[] = { 10, 11, 21, 22, 23, 24, 25, 26, 27 };
+static struct spear_muxreg mii0_1_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_MII_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg smii0_1_ext_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_10_19_REG,
+                .mask = PMX_PL_10_11_MASK,
+                .val = PMX_SMII_PL_10_11_VAL,
+        }, {
+                .reg = IP_SEL_PAD_20_29_REG,
+                .mask = PMX_PL_21_TO_27_MASK,
+                .val = PMX_SMII_PL_21_TO_27_VAL,
+        }, {
+                .reg = EXT_CTRL_REG,
+                .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
+                        (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
+                        MII_MDIO_MASK,
+                .val = (MAC_MODE_SMII << MAC2_MODE_SHIFT)
+                        | (MAC_MODE_SMII << MAC1_MODE_SHIFT)
+                        | MII_MDIO_10_11_VAL,
+        },
+};
+
+static struct spear_muxreg rmii0_1_ext_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_10_19_REG,
+                .mask = PMX_PL_10_11_MASK | PMX_PL_13_14_MASK |
+                        PMX_PL_15_16_MASK | PMX_PL_17_18_MASK | PMX_PL_19_MASK,
+                .val = PMX_RMII_PL_10_11_VAL | PMX_RMII_PL_13_14_VAL |
+                        PMX_RMII_PL_15_16_VAL | PMX_RMII_PL_17_18_VAL |
+                        PMX_RMII_PL_19_VAL,
+        }, {
+                .reg = IP_SEL_PAD_20_29_REG,
+                .mask = PMX_PL_20_MASK | PMX_PL_21_TO_27_MASK,
+                .val = PMX_RMII_PL_20_VAL | PMX_RMII_PL_21_TO_27_VAL,
+        }, {
+                .reg = EXT_CTRL_REG,
+                .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
+                        (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
+                        MII_MDIO_MASK,
+                .val = (MAC_MODE_RMII << MAC2_MODE_SHIFT)
+                        | (MAC_MODE_RMII << MAC1_MODE_SHIFT)
+                        | MII_MDIO_10_11_VAL,
+        },
+};
+
+static struct spear_modemux mii0_1_modemux[][2] = {
+        {
+                /* configure as smii */
+                {
+                        .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE |
+                                SMALL_PRINTERS_MODE | EXTENDED_MODE,
+                        .muxregs = mii0_1_muxreg,
+                        .nmuxregs = ARRAY_SIZE(mii0_1_muxreg),
+                }, {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = smii0_1_ext_muxreg,
+                        .nmuxregs = ARRAY_SIZE(smii0_1_ext_muxreg),
+                },
+        }, {
+                /* configure as rmii */
+                {
+                        .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE |
+                                SMALL_PRINTERS_MODE | EXTENDED_MODE,
+                        .muxregs = mii0_1_muxreg,
+                        .nmuxregs = ARRAY_SIZE(mii0_1_muxreg),
+                }, {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = rmii0_1_ext_muxreg,
+                        .nmuxregs = ARRAY_SIZE(rmii0_1_ext_muxreg),
+                },
+        },
+};
+
+static struct spear_pingroup mii0_1_pingroup[] = {
+        {
+                .name = "smii0_1_grp",
+                .pins = smii0_1_pins,
+                .npins = ARRAY_SIZE(smii0_1_pins),
+                .modemuxs = mii0_1_modemux[0],
+                .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[0]),
+        }, {
+                .name = "rmii0_1_grp",
+                .pins = rmii0_1_pins,
+                .npins = ARRAY_SIZE(rmii0_1_pins),
+                .modemuxs = mii0_1_modemux[1],
+                .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[1]),
+        },
+};
+
+static const char *const mii0_1_grps[] = { "smii0_1_grp", "rmii0_1_grp" };
+static struct spear_function mii0_1_function = {
+        .name = "mii0_1",
+        .groups = mii0_1_grps,
+        .ngroups = ARRAY_SIZE(mii0_1_grps),
+};
+
+/* Pad multiplexing for i2c1 device */
+static const unsigned i2c1_pins[][2] = { { 8, 9 }, { 98, 99 } };
+static struct spear_muxreg i2c1_ext_8_9_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_SSP_CS_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_0_9_REG,
+                .mask = PMX_PL_8_9_MASK,
+                .val = PMX_I2C1_PL_8_9_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_I2C1_PORT_SEL_MASK,
+                .val = PMX_I2C1_PORT_8_9_VAL,
+        },
+};
+
+static struct spear_muxreg i2c1_ext_98_99_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_90_99_REG,
+                .mask = PMX_PL_98_MASK | PMX_PL_99_MASK,
+                .val = PMX_I2C1_PL_98_VAL | PMX_I2C1_PL_99_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_I2C1_PORT_SEL_MASK,
+                .val = PMX_I2C1_PORT_98_99_VAL,
+        },
+};
+
+static struct spear_modemux i2c1_modemux[][1] = {
+        {
+                /* Select signals on pins 8-9 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = i2c1_ext_8_9_muxreg,
+                        .nmuxregs = ARRAY_SIZE(i2c1_ext_8_9_muxreg),
+                },
+        }, {
+                /* Select signals on pins 98-99 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = i2c1_ext_98_99_muxreg,
+                        .nmuxregs = ARRAY_SIZE(i2c1_ext_98_99_muxreg),
+                },
+        },
+};
+
+static struct spear_pingroup i2c1_pingroup[] = {
+        {
+                .name = "i2c1_8_9_grp",
+                .pins = i2c1_pins[0],
+                .npins = ARRAY_SIZE(i2c1_pins[0]),
+                .modemuxs = i2c1_modemux[0],
+                .nmodemuxs = ARRAY_SIZE(i2c1_modemux[0]),
+        }, {
+                .name = "i2c1_98_99_grp",
+                .pins = i2c1_pins[1],
+                .npins = ARRAY_SIZE(i2c1_pins[1]),
+                .modemuxs = i2c1_modemux[1],
+                .nmodemuxs = ARRAY_SIZE(i2c1_modemux[1]),
+        },
+};
+
+static const char *const i2c1_grps[] = { "i2c1_8_9_grp", "i2c1_98_99_grp" };
+static struct spear_function i2c1_function = {
+        .name = "i2c1",
+        .groups = i2c1_grps,
+        .ngroups = ARRAY_SIZE(i2c1_grps),
+};
+
+/* Pad multiplexing for i2c2 device */
+static const unsigned i2c2_pins[][2] = { { 0, 1 }, { 2, 3 }, { 19, 20 },
+        { 75, 76 }, { 96, 97 } };
+static struct spear_muxreg i2c2_ext_0_1_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_FIRDA_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_0_9_REG,
+                .mask = PMX_PL_0_1_MASK,
+                .val = PMX_I2C2_PL_0_1_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_I2C2_PORT_SEL_MASK,
+                .val = PMX_I2C2_PORT_0_1_VAL,
+        },
+};
+
+static struct spear_muxreg i2c2_ext_2_3_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_0_9_REG,
+                .mask = PMX_PL_2_3_MASK,
+                .val = PMX_I2C2_PL_2_3_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_I2C2_PORT_SEL_MASK,
+                .val = PMX_I2C2_PORT_2_3_VAL,
+        },
+};
+
+static struct spear_muxreg i2c2_ext_19_20_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_MII_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_10_19_REG,
+                .mask = PMX_PL_19_MASK,
+                .val = PMX_I2C2_PL_19_VAL,
+        }, {
+                .reg = IP_SEL_PAD_20_29_REG,
+                .mask = PMX_PL_20_MASK,
+                .val = PMX_I2C2_PL_20_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_I2C2_PORT_SEL_MASK,
+                .val = PMX_I2C2_PORT_19_20_VAL,
+        },
+};
+
+static struct spear_muxreg i2c2_ext_75_76_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_70_79_REG,
+                .mask = PMX_PL_75_76_MASK,
+                .val = PMX_I2C2_PL_75_76_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_I2C2_PORT_SEL_MASK,
+                .val = PMX_I2C2_PORT_75_76_VAL,
+        },
+};
+
+static struct spear_muxreg i2c2_ext_96_97_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_90_99_REG,
+                .mask = PMX_PL_96_97_MASK,
+                .val = PMX_I2C2_PL_96_97_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_I2C2_PORT_SEL_MASK,
+                .val = PMX_I2C2_PORT_96_97_VAL,
+        },
+};
+
+static struct spear_modemux i2c2_modemux[][1] = {
+        {
+                /* Select signals on pins 0_1 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = i2c2_ext_0_1_muxreg,
+                        .nmuxregs = ARRAY_SIZE(i2c2_ext_0_1_muxreg),
+                },
+        }, {
+                /* Select signals on pins 2_3 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = i2c2_ext_2_3_muxreg,
+                        .nmuxregs = ARRAY_SIZE(i2c2_ext_2_3_muxreg),
+                },
+        }, {
+                /* Select signals on pins 19_20 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = i2c2_ext_19_20_muxreg,
+                        .nmuxregs = ARRAY_SIZE(i2c2_ext_19_20_muxreg),
+                },
+        }, {
+                /* Select signals on pins 75_76 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = i2c2_ext_75_76_muxreg,
+                        .nmuxregs = ARRAY_SIZE(i2c2_ext_75_76_muxreg),
+                },
+        }, {
+                /* Select signals on pins 96_97 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = i2c2_ext_96_97_muxreg,
+                        .nmuxregs = ARRAY_SIZE(i2c2_ext_96_97_muxreg),
+                },
+        },
+};
+
+static struct spear_pingroup i2c2_pingroup[] = {
+        {
+                .name = "i2c2_0_1_grp",
+                .pins = i2c2_pins[0],
+                .npins = ARRAY_SIZE(i2c2_pins[0]),
+                .modemuxs = i2c2_modemux[0],
+                .nmodemuxs = ARRAY_SIZE(i2c2_modemux[0]),
+        }, {
+                .name = "i2c2_2_3_grp",
+                .pins = i2c2_pins[1],
+                .npins = ARRAY_SIZE(i2c2_pins[1]),
+                .modemuxs = i2c2_modemux[1],
+                .nmodemuxs = ARRAY_SIZE(i2c2_modemux[1]),
+        }, {
+                .name = "i2c2_19_20_grp",
+                .pins = i2c2_pins[2],
+                .npins = ARRAY_SIZE(i2c2_pins[2]),
+                .modemuxs = i2c2_modemux[2],
+                .nmodemuxs = ARRAY_SIZE(i2c2_modemux[2]),
+        }, {
+                .name = "i2c2_75_76_grp",
+                .pins = i2c2_pins[3],
+                .npins = ARRAY_SIZE(i2c2_pins[3]),
+                .modemuxs = i2c2_modemux[3],
+                .nmodemuxs = ARRAY_SIZE(i2c2_modemux[3]),
+        }, {
+                .name = "i2c2_96_97_grp",
+                .pins = i2c2_pins[4],
+                .npins = ARRAY_SIZE(i2c2_pins[4]),
+                .modemuxs = i2c2_modemux[4],
+                .nmodemuxs = ARRAY_SIZE(i2c2_modemux[4]),
+        },
+};
+
+static const char *const i2c2_grps[] = { "i2c2_0_1_grp", "i2c2_2_3_grp",
+        "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp" };
+static struct spear_function i2c2_function = {
+        .name = "i2c2",
+        .groups = i2c2_grps,
+        .ngroups = ARRAY_SIZE(i2c2_grps),
+};
+
+/* pingroups */
+static struct spear_pingroup *spear320_pingroups[] = {
+        SPEAR3XX_COMMON_PINGROUPS,
+        &clcd_pingroup,
+        &emi_pingroup,
+        &fsmc_8bit_pingroup,
+        &fsmc_16bit_pingroup,
+        &spp_pingroup,
+        &sdhci_led_pingroup,
+        &sdhci_pingroup[0],
+        &sdhci_pingroup[1],
+        &i2s_pingroup,
+        &uart1_pingroup,
+        &uart1_modem_pingroup[0],
+        &uart1_modem_pingroup[1],
+        &uart1_modem_pingroup[2],
+        &uart1_modem_pingroup[3],
+        &uart2_pingroup,
+        &uart3_pingroup[0],
+        &uart3_pingroup[1],
+        &uart3_pingroup[2],
+        &uart3_pingroup[3],
+        &uart3_pingroup[4],
+        &uart3_pingroup[5],
+        &uart3_pingroup[6],
+        &uart4_pingroup[0],
+        &uart4_pingroup[1],
+        &uart4_pingroup[2],
+        &uart4_pingroup[3],
+        &uart4_pingroup[4],
+        &uart4_pingroup[5],
+        &uart5_pingroup[0],
+        &uart5_pingroup[1],
+        &uart5_pingroup[2],
+        &uart5_pingroup[3],
+        &uart6_pingroup[0],
+        &uart6_pingroup[1],
+        &rs485_pingroup,
+        &touchscreen_pingroup,
+        &can0_pingroup,
+        &can1_pingroup,
+        &pwm0_1_pingroup[0],
+        &pwm0_1_pingroup[1],
+        &pwm0_1_pingroup[2],
+        &pwm0_1_pingroup[3],
+        &pwm0_1_pingroup[4],
+        &pwm0_1_pingroup[5],
+        &pwm0_1_pingroup[6],
+        &pwm2_pingroup[0],
+        &pwm2_pingroup[1],
+        &pwm2_pingroup[2],
+        &pwm2_pingroup[3],
+        &pwm2_pingroup[4],
+        &pwm2_pingroup[5],
+        &pwm2_pingroup[6],
+        &pwm3_pingroup[0],
+        &pwm3_pingroup[1],
+        &pwm3_pingroup[2],
+        &pwm3_pingroup[3],
+        &pwm3_pingroup[4],
+        &pwm3_pingroup[5],
+        &ssp1_pingroup[0],
+        &ssp1_pingroup[1],
+        &ssp1_pingroup[2],
+        &ssp1_pingroup[3],
+        &ssp1_pingroup[4],
+        &ssp2_pingroup[0],
+        &ssp2_pingroup[1],
+        &ssp2_pingroup[2],
+        &ssp2_pingroup[3],
+        &ssp2_pingroup[4],
+        &mii2_pingroup,
+        &mii0_1_pingroup[0],
+        &mii0_1_pingroup[1],
+        &i2c1_pingroup[0],
+        &i2c1_pingroup[1],
+        &i2c2_pingroup[0],
+        &i2c2_pingroup[1],
+        &i2c2_pingroup[2],
+        &i2c2_pingroup[3],
+        &i2c2_pingroup[4],
+};
+
+/* functions */
+static struct spear_function *spear320_functions[] = {
+        SPEAR3XX_COMMON_FUNCTIONS,
+        &clcd_function,
+        &emi_function,
+        &fsmc_function,
+        &spp_function,
+        &sdhci_function,
+        &i2s_function,
+        &uart1_function,
+        &uart1_modem_function,
+        &uart2_function,
+        &uart3_function,
+        &uart4_function,
+        &uart5_function,
+        &uart6_function,
+        &rs485_function,
+        &touchscreen_function,
+        &can0_function,
+        &can1_function,
+        &pwm0_1_function,
+        &pwm2_function,
+        &pwm3_function,
+        &ssp1_function,
+        &ssp2_function,
+        &mii2_function,
+        &mii0_1_function,
+        &i2c1_function,
+        &i2c2_function,
+};
+
+static struct of_device_id spear320_pinctrl_of_match[] __devinitdata = {
+        {
+                .compatible = "st,spear320-pinmux",
+        },
+        {},
+};
+
+static int __devinit spear320_pinctrl_probe(struct platform_device *pdev)
+{
+        int ret;
+
+        spear3xx_machdata.groups = spear320_pingroups;
+        spear3xx_machdata.ngroups = ARRAY_SIZE(spear320_pingroups);
+        spear3xx_machdata.functions = spear320_functions;
+        spear3xx_machdata.nfunctions = ARRAY_SIZE(spear320_functions);
+
+        spear3xx_machdata.modes_supported = true;
+        spear3xx_machdata.pmx_modes = spear320_pmx_modes;
+        spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear320_pmx_modes);
+
+        pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
+
+        ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
+        if (ret)
+                return ret;
+
+        return 0;
+}
+
+static int __devexit spear320_pinctrl_remove(struct platform_device *pdev)
+{
+        return spear_pinctrl_remove(pdev);
+}
+
+static struct platform_driver spear320_pinctrl_driver = {
+        .driver = {
+                .name = DRIVER_NAME,
+                .owner = THIS_MODULE,
+                .of_match_table = spear320_pinctrl_of_match,
+        },
+        .probe = spear320_pinctrl_probe,
+        .remove = __devexit_p(spear320_pinctrl_remove),
+};
+
+static int __init spear320_pinctrl_init(void)
+{
+        return platform_driver_register(&spear320_pinctrl_driver);
+}
+arch_initcall(spear320_pinctrl_init);
+
+static void __exit spear320_pinctrl_exit(void)
+{
+        platform_driver_unregister(&spear320_pinctrl_driver);
+}
+module_exit(spear320_pinctrl_exit);
+
+MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
+MODULE_DESCRIPTION("ST Microelectronics SPEAr320 pinctrl driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, spear320_pinctrl_of_match);
diff --git a/drivers/pinctrl/spear/pinctrl-spear3xx.c b/drivers/pinctrl/spear/pinctrl-spear3xx.c
new file mode 100644
index 000000000000..832049a8b1c9
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear3xx.c
@@ -0,0 +1,588 @@
+/*
+ * Driver for the ST Microelectronics SPEAr3xx pinmux
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-spear3xx.h"
+
+/* pins */
+static const struct pinctrl_pin_desc spear3xx_pins[] = {
+        PINCTRL_PIN(0, "PLGPIO0"),
+        PINCTRL_PIN(1, "PLGPIO1"),
+        PINCTRL_PIN(2, "PLGPIO2"),
+        PINCTRL_PIN(3, "PLGPIO3"),
+        PINCTRL_PIN(4, "PLGPIO4"),
+        PINCTRL_PIN(5, "PLGPIO5"),
+        PINCTRL_PIN(6, "PLGPIO6"),
+        PINCTRL_PIN(7, "PLGPIO7"),
+        PINCTRL_PIN(8, "PLGPIO8"),
+        PINCTRL_PIN(9, "PLGPIO9"),
+        PINCTRL_PIN(10, "PLGPIO10"),
+        PINCTRL_PIN(11, "PLGPIO11"),
+        PINCTRL_PIN(12, "PLGPIO12"),
+        PINCTRL_PIN(13, "PLGPIO13"),
+        PINCTRL_PIN(14, "PLGPIO14"),
+        PINCTRL_PIN(15, "PLGPIO15"),
+        PINCTRL_PIN(16, "PLGPIO16"),
+        PINCTRL_PIN(17, "PLGPIO17"),
+        PINCTRL_PIN(18, "PLGPIO18"),
+        PINCTRL_PIN(19, "PLGPIO19"),
+        PINCTRL_PIN(20, "PLGPIO20"),
+        PINCTRL_PIN(21, "PLGPIO21"),
+        PINCTRL_PIN(22, "PLGPIO22"),
+        PINCTRL_PIN(23, "PLGPIO23"),
+        PINCTRL_PIN(24, "PLGPIO24"),
+        PINCTRL_PIN(25, "PLGPIO25"),
+        PINCTRL_PIN(26, "PLGPIO26"),
+        PINCTRL_PIN(27, "PLGPIO27"),
+        PINCTRL_PIN(28, "PLGPIO28"),
+        PINCTRL_PIN(29, "PLGPIO29"),
+        PINCTRL_PIN(30, "PLGPIO30"),
+        PINCTRL_PIN(31, "PLGPIO31"),
+        PINCTRL_PIN(32, "PLGPIO32"),
+        PINCTRL_PIN(33, "PLGPIO33"),
+        PINCTRL_PIN(34, "PLGPIO34"),
+        PINCTRL_PIN(35, "PLGPIO35"),
+        PINCTRL_PIN(36, "PLGPIO36"),
+        PINCTRL_PIN(37, "PLGPIO37"),
+        PINCTRL_PIN(38, "PLGPIO38"),
+        PINCTRL_PIN(39, "PLGPIO39"),
+        PINCTRL_PIN(40, "PLGPIO40"),
+        PINCTRL_PIN(41, "PLGPIO41"),
+        PINCTRL_PIN(42, "PLGPIO42"),
+        PINCTRL_PIN(43, "PLGPIO43"),
+        PINCTRL_PIN(44, "PLGPIO44"),
+        PINCTRL_PIN(45, "PLGPIO45"),
+        PINCTRL_PIN(46, "PLGPIO46"),
+        PINCTRL_PIN(47, "PLGPIO47"),
+        PINCTRL_PIN(48, "PLGPIO48"),
+        PINCTRL_PIN(49, "PLGPIO49"),
+        PINCTRL_PIN(50, "PLGPIO50"),
+        PINCTRL_PIN(51, "PLGPIO51"),
+        PINCTRL_PIN(52, "PLGPIO52"),
+        PINCTRL_PIN(53, "PLGPIO53"),
+        PINCTRL_PIN(54, "PLGPIO54"),
+        PINCTRL_PIN(55, "PLGPIO55"),
+        PINCTRL_PIN(56, "PLGPIO56"),
+        PINCTRL_PIN(57, "PLGPIO57"),
+        PINCTRL_PIN(58, "PLGPIO58"),
+        PINCTRL_PIN(59, "PLGPIO59"),
+        PINCTRL_PIN(60, "PLGPIO60"),
+        PINCTRL_PIN(61, "PLGPIO61"),
+        PINCTRL_PIN(62, "PLGPIO62"),
+        PINCTRL_PIN(63, "PLGPIO63"),
+        PINCTRL_PIN(64, "PLGPIO64"),
+        PINCTRL_PIN(65, "PLGPIO65"),
+        PINCTRL_PIN(66, "PLGPIO66"),
+        PINCTRL_PIN(67, "PLGPIO67"),
+        PINCTRL_PIN(68, "PLGPIO68"),
+        PINCTRL_PIN(69, "PLGPIO69"),
+        PINCTRL_PIN(70, "PLGPIO70"),
+        PINCTRL_PIN(71, "PLGPIO71"),
+        PINCTRL_PIN(72, "PLGPIO72"),
+        PINCTRL_PIN(73, "PLGPIO73"),
+        PINCTRL_PIN(74, "PLGPIO74"),
+        PINCTRL_PIN(75, "PLGPIO75"),
+        PINCTRL_PIN(76, "PLGPIO76"),
+        PINCTRL_PIN(77, "PLGPIO77"),
+        PINCTRL_PIN(78, "PLGPIO78"),
+        PINCTRL_PIN(79, "PLGPIO79"),
+        PINCTRL_PIN(80, "PLGPIO80"),
+        PINCTRL_PIN(81, "PLGPIO81"),
+        PINCTRL_PIN(82, "PLGPIO82"),
+        PINCTRL_PIN(83, "PLGPIO83"),
+        PINCTRL_PIN(84, "PLGPIO84"),
+        PINCTRL_PIN(85, "PLGPIO85"),
+        PINCTRL_PIN(86, "PLGPIO86"),
+        PINCTRL_PIN(87, "PLGPIO87"),
+        PINCTRL_PIN(88, "PLGPIO88"),
+        PINCTRL_PIN(89, "PLGPIO89"),
+        PINCTRL_PIN(90, "PLGPIO90"),
+        PINCTRL_PIN(91, "PLGPIO91"),
+        PINCTRL_PIN(92, "PLGPIO92"),
+        PINCTRL_PIN(93, "PLGPIO93"),
+        PINCTRL_PIN(94, "PLGPIO94"),
+        PINCTRL_PIN(95, "PLGPIO95"),
+        PINCTRL_PIN(96, "PLGPIO96"),
+        PINCTRL_PIN(97, "PLGPIO97"),
+        PINCTRL_PIN(98, "PLGPIO98"),
+        PINCTRL_PIN(99, "PLGPIO99"),
+        PINCTRL_PIN(100, "PLGPIO100"),
+        PINCTRL_PIN(101, "PLGPIO101"),
+};
+
+/* firda_pins */
+static const unsigned firda_pins[] = { 0, 1 };
+static struct spear_muxreg firda_muxreg[] = {
+        {
+                .reg = -1,
+                .mask = PMX_FIRDA_MASK,
+                .val = PMX_FIRDA_MASK,
+        },
+};
+
+static struct spear_modemux firda_modemux[] = {
+        {
+                .modes = ~0,
+                .muxregs = firda_muxreg,
+                .nmuxregs = ARRAY_SIZE(firda_muxreg),
+        },
+};
+
+struct spear_pingroup spear3xx_firda_pingroup = {
+        .name = "firda_grp",
+        .pins = firda_pins,
+        .npins = ARRAY_SIZE(firda_pins),
+        .modemuxs = firda_modemux,
+        .nmodemuxs = ARRAY_SIZE(firda_modemux),
+};
+
+static const char *const firda_grps[] = { "firda_grp" };
+struct spear_function spear3xx_firda_function = {
+        .name = "firda",
+        .groups = firda_grps,
+        .ngroups = ARRAY_SIZE(firda_grps),
+};
+
+/* i2c_pins */
+static const unsigned i2c_pins[] = { 4, 5 };
+static struct spear_muxreg i2c_muxreg[] = {
+        {
+                .reg = -1,
+                .mask = PMX_I2C_MASK,
+                .val = PMX_I2C_MASK,
+        },
+};
+
+static struct spear_modemux i2c_modemux[] = {
+        {
+                .modes = ~0,
+                .muxregs = i2c_muxreg,
+                .nmuxregs = ARRAY_SIZE(i2c_muxreg),
+        },
+};
+
+struct spear_pingroup spear3xx_i2c_pingroup = {
+        .name = "i2c0_grp",
+        .pins = i2c_pins,
+        .npins = ARRAY_SIZE(i2c_pins),
+        .modemuxs = i2c_modemux,
+        .nmodemuxs = ARRAY_SIZE(i2c_modemux),
+};
+
+static const char *const i2c_grps[] = { "i2c0_grp" };
+struct spear_function spear3xx_i2c_function = {
+        .name = "i2c0",
+        .groups = i2c_grps,
+        .ngroups = ARRAY_SIZE(i2c_grps),
+};
+
+/* ssp_cs_pins */
+static const unsigned ssp_cs_pins[] = { 34, 35, 36 };
+static struct spear_muxreg ssp_cs_muxreg[] = {
+        {
+                .reg = -1,
+                .mask = PMX_SSP_CS_MASK,
+                .val = PMX_SSP_CS_MASK,
+        },
+};
+
+static struct spear_modemux ssp_cs_modemux[] = {
+        {
+                .modes = ~0,
+                .muxregs = ssp_cs_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp_cs_muxreg),
+        },
+};
+
+struct spear_pingroup spear3xx_ssp_cs_pingroup = {
+        .name = "ssp_cs_grp",
+        .pins = ssp_cs_pins,
+        .npins = ARRAY_SIZE(ssp_cs_pins),
+        .modemuxs = ssp_cs_modemux,
+        .nmodemuxs = ARRAY_SIZE(ssp_cs_modemux),
+};
+
+static const char *const ssp_cs_grps[] = { "ssp_cs_grp" };
+struct spear_function spear3xx_ssp_cs_function = {
+        .name = "ssp_cs",
+        .groups = ssp_cs_grps,
+        .ngroups = ARRAY_SIZE(ssp_cs_grps),
+};
+
+/* ssp_pins */
+static const unsigned ssp_pins[] = { 6, 7, 8, 9 };
+static struct spear_muxreg ssp_muxreg[] = {
+        {
+                .reg = -1,
+                .mask = PMX_SSP_MASK,
+                .val = PMX_SSP_MASK,
+        },
+};
+
+static struct spear_modemux ssp_modemux[] = {
+        {
+                .modes = ~0,
+                .muxregs = ssp_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp_muxreg),
+        },
+};
+
+struct spear_pingroup spear3xx_ssp_pingroup = {
+        .name = "ssp0_grp",
+        .pins = ssp_pins,
+        .npins = ARRAY_SIZE(ssp_pins),
+        .modemuxs = ssp_modemux,
+        .nmodemuxs = ARRAY_SIZE(ssp_modemux),
+};
+
+static const char *const ssp_grps[] = { "ssp0_grp" };
+struct spear_function spear3xx_ssp_function = {
+        .name = "ssp0",
+        .groups = ssp_grps,
+        .ngroups = ARRAY_SIZE(ssp_grps),
+};
+
+/* mii_pins */
+static const unsigned mii_pins[] = { 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
+        21, 22, 23, 24, 25, 26, 27 };
+static struct spear_muxreg mii_muxreg[] = {
+        {
+                .reg = -1,
+                .mask = PMX_MII_MASK,
+                .val = PMX_MII_MASK,
+        },
+};
+
+static struct spear_modemux mii_modemux[] = {
+        {
+                .modes = ~0,
+                .muxregs = mii_muxreg,
+                .nmuxregs = ARRAY_SIZE(mii_muxreg),
+        },
+};
+
+struct spear_pingroup spear3xx_mii_pingroup = {
+        .name = "mii0_grp",
+        .pins = mii_pins,
+        .npins = ARRAY_SIZE(mii_pins),
+        .modemuxs = mii_modemux,
+        .nmodemuxs = ARRAY_SIZE(mii_modemux),
+};
+
+static const char *const mii_grps[] = { "mii0_grp" };
+struct spear_function spear3xx_mii_function = {
+        .name = "mii0",
+        .groups = mii_grps,
+        .ngroups = ARRAY_SIZE(mii_grps),
+};
+
+/* gpio0_pin0_pins */
+static const unsigned gpio0_pin0_pins[] = { 28 };
+static struct spear_muxreg gpio0_pin0_muxreg[] = {
+        {
+                .reg = -1,
+                .mask = PMX_GPIO_PIN0_MASK,
+                .val = PMX_GPIO_PIN0_MASK,
+        },
+};
+
+static struct spear_modemux gpio0_pin0_modemux[] = {
+        {
+                .modes = ~0,
+                .muxregs = gpio0_pin0_muxreg,
+                .nmuxregs = ARRAY_SIZE(gpio0_pin0_muxreg),
+        },
+};
+
+struct spear_pingroup spear3xx_gpio0_pin0_pingroup = {
+        .name = "gpio0_pin0_grp",
+        .pins = gpio0_pin0_pins,
+        .npins = ARRAY_SIZE(gpio0_pin0_pins),
+        .modemuxs = gpio0_pin0_modemux,
+        .nmodemuxs = ARRAY_SIZE(gpio0_pin0_modemux),
+};
+
+/* gpio0_pin1_pins */
+static const unsigned gpio0_pin1_pins[] = { 29 };
+static struct spear_muxreg gpio0_pin1_muxreg[] = {
+        {
+                .reg = -1,
+                .mask = PMX_GPIO_PIN1_MASK,
+                .val = PMX_GPIO_PIN1_MASK,
+        },
+};
+
+static struct spear_modemux gpio0_pin1_modemux[] = {
+        {
+                .modes = ~0,
+                .muxregs = gpio0_pin1_muxreg,
+                .nmuxregs = ARRAY_SIZE(gpio0_pin1_muxreg),
+        },
+};
+
+struct spear_pingroup spear3xx_gpio0_pin1_pingroup = {
+        .name = "gpio0_pin1_grp",
+        .pins = gpio0_pin1_pins,
+        .npins = ARRAY_SIZE(gpio0_pin1_pins),
+        .modemuxs = gpio0_pin1_modemux,
+        .nmodemuxs = ARRAY_SIZE(gpio0_pin1_modemux),
+};
+
+/* gpio0_pin2_pins */
+static const unsigned gpio0_pin2_pins[] = { 30 };
+static struct spear_muxreg gpio0_pin2_muxreg[] = {
+        {
+                .reg = -1,
+                .mask = PMX_GPIO_PIN2_MASK,
+                .val = PMX_GPIO_PIN2_MASK,
+        },
+};
+
+static struct spear_modemux gpio0_pin2_modemux[] = {
+        {
+                .modes = ~0,
+                .muxregs = gpio0_pin2_muxreg,
+                .nmuxregs = ARRAY_SIZE(gpio0_pin2_muxreg),
+        },
+};
+
+struct spear_pingroup spear3xx_gpio0_pin2_pingroup = {
+        .name = "gpio0_pin2_grp",
+        .pins = gpio0_pin2_pins,
+        .npins = ARRAY_SIZE(gpio0_pin2_pins),
+        .modemuxs = gpio0_pin2_modemux,
+        .nmodemuxs = ARRAY_SIZE(gpio0_pin2_modemux),
+};
+
+/* gpio0_pin3_pins */
+static const unsigned gpio0_pin3_pins[] = { 31 };
+static struct spear_muxreg gpio0_pin3_muxreg[] = {
+        {
+                .reg = -1,
+                .mask = PMX_GPIO_PIN3_MASK,
+                .val = PMX_GPIO_PIN3_MASK,
+        },
+};
+
+static struct spear_modemux gpio0_pin3_modemux[] = {
+        {
+                .modes = ~0,
+                .muxregs = gpio0_pin3_muxreg,
+                .nmuxregs = ARRAY_SIZE(gpio0_pin3_muxreg),
+        },
+};
+
+struct spear_pingroup spear3xx_gpio0_pin3_pingroup = {
+        .name = "gpio0_pin3_grp",
+        .pins = gpio0_pin3_pins,
+        .npins = ARRAY_SIZE(gpio0_pin3_pins),
+        .modemuxs = gpio0_pin3_modemux,
+        .nmodemuxs = ARRAY_SIZE(gpio0_pin3_modemux),
+};
+
+/* gpio0_pin4_pins */
+static const unsigned gpio0_pin4_pins[] = { 32 };
+static struct spear_muxreg gpio0_pin4_muxreg[] = {
+        {
+                .reg = -1,
+                .mask = PMX_GPIO_PIN4_MASK,
+                .val = PMX_GPIO_PIN4_MASK,
+        },
+};
+
+static struct spear_modemux gpio0_pin4_modemux[] = {
+        {
+                .modes = ~0,
+                .muxregs = gpio0_pin4_muxreg,
+                .nmuxregs = ARRAY_SIZE(gpio0_pin4_muxreg),
+        },
+};
+
+struct spear_pingroup spear3xx_gpio0_pin4_pingroup = {
+        .name = "gpio0_pin4_grp",
+        .pins = gpio0_pin4_pins,
+        .npins = ARRAY_SIZE(gpio0_pin4_pins),
+        .modemuxs = gpio0_pin4_modemux,
+        .nmodemuxs = ARRAY_SIZE(gpio0_pin4_modemux),
+};
+
+/* gpio0_pin5_pins */
+static const unsigned gpio0_pin5_pins[] = { 33 };
+static struct spear_muxreg gpio0_pin5_muxreg[] = {
+        {
+                .reg = -1,
+                .mask = PMX_GPIO_PIN5_MASK,
+                .val = PMX_GPIO_PIN5_MASK,
+        },
+};
+
+static struct spear_modemux gpio0_pin5_modemux[] = {
+        {
+                .modes = ~0,
+                .muxregs = gpio0_pin5_muxreg,
+                .nmuxregs = ARRAY_SIZE(gpio0_pin5_muxreg),
+        },
+};
+
+struct spear_pingroup spear3xx_gpio0_pin5_pingroup = {
+        .name = "gpio0_pin5_grp",
+        .pins = gpio0_pin5_pins,
+        .npins = ARRAY_SIZE(gpio0_pin5_pins),
+        .modemuxs = gpio0_pin5_modemux,
+        .nmodemuxs = ARRAY_SIZE(gpio0_pin5_modemux),
+};
+
+static const char *const gpio0_grps[] = { "gpio0_pin0_grp", "gpio0_pin1_grp",
+        "gpio0_pin2_grp", "gpio0_pin3_grp", "gpio0_pin4_grp", "gpio0_pin5_grp",
+};
+struct spear_function spear3xx_gpio0_function = {
+        .name = "gpio0",
+        .groups = gpio0_grps,
+        .ngroups = ARRAY_SIZE(gpio0_grps),
+};
+
+/* uart0_ext_pins */
+static const unsigned uart0_ext_pins[] = { 37, 38, 39, 40, 41, 42 };
+static struct spear_muxreg uart0_ext_muxreg[] = {
+        {
+                .reg = -1,
+                .mask = PMX_UART0_MODEM_MASK,
+                .val = PMX_UART0_MODEM_MASK,
+        },
+};
+
+static struct spear_modemux uart0_ext_modemux[] = {
+        {
+                .modes = ~0,
+                .muxregs = uart0_ext_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart0_ext_muxreg),
+        },
+};
+
+struct spear_pingroup spear3xx_uart0_ext_pingroup = {
+        .name = "uart0_ext_grp",
+        .pins = uart0_ext_pins,
+        .npins = ARRAY_SIZE(uart0_ext_pins),
+        .modemuxs = uart0_ext_modemux,
+        .nmodemuxs = ARRAY_SIZE(uart0_ext_modemux),
+};
+
+static const char *const uart0_ext_grps[] = { "uart0_ext_grp" };
+struct spear_function spear3xx_uart0_ext_function = {
+        .name = "uart0_ext",
+        .groups = uart0_ext_grps,
+        .ngroups = ARRAY_SIZE(uart0_ext_grps),
+};
+
+/* uart0_pins */
+static const unsigned uart0_pins[] = { 2, 3 };
+static struct spear_muxreg uart0_muxreg[] = {
+        {
+                .reg = -1,
+                .mask = PMX_UART0_MASK,
+                .val = PMX_UART0_MASK,
+        },
+};
+
+static struct spear_modemux uart0_modemux[] = {
+        {
+                .modes = ~0,
+                .muxregs = uart0_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart0_muxreg),
+        },
+};
+
+struct spear_pingroup spear3xx_uart0_pingroup = {
+        .name = "uart0_grp",
+        .pins = uart0_pins,
+        .npins = ARRAY_SIZE(uart0_pins),
+        .modemuxs = uart0_modemux,
+        .nmodemuxs = ARRAY_SIZE(uart0_modemux),
+};
+
+static const char *const uart0_grps[] = { "uart0_grp" };
+struct spear_function spear3xx_uart0_function = {
+        .name = "uart0",
+        .groups = uart0_grps,
+        .ngroups = ARRAY_SIZE(uart0_grps),
+};
+
+/* timer_0_1_pins */
+static const unsigned timer_0_1_pins[] = { 43, 44, 47, 48 };
+static struct spear_muxreg timer_0_1_muxreg[] = {
+        {
+                .reg = -1,
+                .mask = PMX_TIMER_0_1_MASK,
+                .val = PMX_TIMER_0_1_MASK,
+        },
+};
+
+static struct spear_modemux timer_0_1_modemux[] = {
+        {
+                .modes = ~0,
+                .muxregs = timer_0_1_muxreg,
+                .nmuxregs = ARRAY_SIZE(timer_0_1_muxreg),
+        },
+};
+
+struct spear_pingroup spear3xx_timer_0_1_pingroup = {
+        .name = "timer_0_1_grp",
+        .pins = timer_0_1_pins,
+        .npins = ARRAY_SIZE(timer_0_1_pins),
+        .modemuxs = timer_0_1_modemux,
+        .nmodemuxs = ARRAY_SIZE(timer_0_1_modemux),
+};
+
+static const char *const timer_0_1_grps[] = { "timer_0_1_grp" };
+struct spear_function spear3xx_timer_0_1_function = {
+        .name = "timer_0_1",
+        .groups = timer_0_1_grps,
+        .ngroups = ARRAY_SIZE(timer_0_1_grps),
+};
+
+/* timer_2_3_pins */
+static const unsigned timer_2_3_pins[] = { 45, 46, 49, 50 };
+static struct spear_muxreg timer_2_3_muxreg[] = {
+        {
+                .reg = -1,
+                .mask = PMX_TIMER_2_3_MASK,
+                .val = PMX_TIMER_2_3_MASK,
+        },
+};
+
+static struct spear_modemux timer_2_3_modemux[] = {
+        {
+                .modes = ~0,
+                .muxregs = timer_2_3_muxreg,
+                .nmuxregs = ARRAY_SIZE(timer_2_3_muxreg),
+        },
+};
+
+struct spear_pingroup spear3xx_timer_2_3_pingroup = {
+        .name = "timer_2_3_grp",
+        .pins = timer_2_3_pins,
+        .npins = ARRAY_SIZE(timer_2_3_pins),
+        .modemuxs = timer_2_3_modemux,
+        .nmodemuxs = ARRAY_SIZE(timer_2_3_modemux),
+};
+
+static const char *const timer_2_3_grps[] = { "timer_2_3_grp" };
+struct spear_function spear3xx_timer_2_3_function = {
+        .name = "timer_2_3",
+        .groups = timer_2_3_grps,
+        .ngroups = ARRAY_SIZE(timer_2_3_grps),
+};
+
+struct spear_pinctrl_machdata spear3xx_machdata = {
+        .pins = spear3xx_pins,
+        .npins = ARRAY_SIZE(spear3xx_pins),
+};
diff --git a/drivers/pinctrl/spear/pinctrl-spear3xx.h b/drivers/pinctrl/spear/pinctrl-spear3xx.h
new file mode 100644
index 000000000000..5d5fdd8df7b8
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear3xx.h
@@ -0,0 +1,92 @@
+/*
+ * Header file for the ST Microelectronics SPEAr3xx pinmux
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PINMUX_SPEAR3XX_H__
+#define __PINMUX_SPEAR3XX_H__
+
+#include "pinctrl-spear.h"
+
+/* pad mux declarations */
+#define PMX_FIRDA_MASK          (1 << 14)
+#define PMX_I2C_MASK            (1 << 13)
+#define PMX_SSP_CS_MASK         (1 << 12)
+#define PMX_SSP_MASK            (1 << 11)
+#define PMX_MII_MASK            (1 << 10)
+#define PMX_GPIO_PIN0_MASK      (1 << 9)
+#define PMX_GPIO_PIN1_MASK      (1 << 8)
+#define PMX_GPIO_PIN2_MASK      (1 << 7)
+#define PMX_GPIO_PIN3_MASK      (1 << 6)
+#define PMX_GPIO_PIN4_MASK      (1 << 5)
+#define PMX_GPIO_PIN5_MASK      (1 << 4)
+#define PMX_UART0_MODEM_MASK    (1 << 3)
+#define PMX_UART0_MASK          (1 << 2)
+#define PMX_TIMER_2_3_MASK      (1 << 1)
+#define PMX_TIMER_0_1_MASK      (1 << 0)
+
+extern struct spear_pingroup spear3xx_firda_pingroup;
+extern struct spear_pingroup spear3xx_gpio0_pin0_pingroup;
+extern struct spear_pingroup spear3xx_gpio0_pin1_pingroup;
+extern struct spear_pingroup spear3xx_gpio0_pin2_pingroup;
+extern struct spear_pingroup spear3xx_gpio0_pin3_pingroup;
+extern struct spear_pingroup spear3xx_gpio0_pin4_pingroup;
+extern struct spear_pingroup spear3xx_gpio0_pin5_pingroup;
+extern struct spear_pingroup spear3xx_i2c_pingroup;
+extern struct spear_pingroup spear3xx_mii_pingroup;
+extern struct spear_pingroup spear3xx_ssp_cs_pingroup;
+extern struct spear_pingroup spear3xx_ssp_pingroup;
+extern struct spear_pingroup spear3xx_timer_0_1_pingroup;
+extern struct spear_pingroup spear3xx_timer_2_3_pingroup;
+extern struct spear_pingroup spear3xx_uart0_ext_pingroup;
+extern struct spear_pingroup spear3xx_uart0_pingroup;
+
+#define SPEAR3XX_COMMON_PINGROUPS               \
+        &spear3xx_firda_pingroup,               \
+        &spear3xx_gpio0_pin0_pingroup,          \
+        &spear3xx_gpio0_pin1_pingroup,          \
+        &spear3xx_gpio0_pin2_pingroup,          \
+        &spear3xx_gpio0_pin3_pingroup,          \
+        &spear3xx_gpio0_pin4_pingroup,          \
+        &spear3xx_gpio0_pin5_pingroup,          \
+        &spear3xx_i2c_pingroup,                 \
+        &spear3xx_mii_pingroup,                 \
+        &spear3xx_ssp_cs_pingroup,              \
+        &spear3xx_ssp_pingroup,                 \
+        &spear3xx_timer_0_1_pingroup,           \
+        &spear3xx_timer_2_3_pingroup,           \
+        &spear3xx_uart0_ext_pingroup,           \
+        &spear3xx_uart0_pingroup
+
+extern struct spear_function spear3xx_firda_function;
+extern struct spear_function spear3xx_gpio0_function;
+extern struct spear_function spear3xx_i2c_function;
+extern struct spear_function spear3xx_mii_function;
+extern struct spear_function spear3xx_ssp_cs_function;
+extern struct spear_function spear3xx_ssp_function;
+extern struct spear_function spear3xx_timer_0_1_function;
+extern struct spear_function spear3xx_timer_2_3_function;
+extern struct spear_function spear3xx_uart0_ext_function;
+extern struct spear_function spear3xx_uart0_function;
+
+#define SPEAR3XX_COMMON_FUNCTIONS               \
+        &spear3xx_firda_function,               \
+        &spear3xx_gpio0_function,               \
+        &spear3xx_i2c_function,                 \
+        &spear3xx_mii_function,                 \
+        &spear3xx_ssp_cs_function,              \
+        &spear3xx_ssp_function,                 \
+        &spear3xx_timer_0_1_function,           \
+        &spear3xx_timer_2_3_function,           \
+        &spear3xx_uart0_ext_function,           \
+        &spear3xx_uart0_function
+
+extern struct spear_pinctrl_machdata spear3xx_machdata;
+
+#endif /* __PINMUX_SPEAR3XX_H__ */
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index 86183366647f..826c2fd8c402 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -581,15 +581,16 @@ static const struct hc_driver tegra_ehci_hc_driver = {
         .port_handed_over       = ehci_port_handed_over,
 };
 
-static int setup_vbus_gpio(struct platform_device *pdev)
+static int setup_vbus_gpio(struct platform_device *pdev,
+                           struct tegra_ehci_platform_data *pdata)
 {
         int err = 0;
         int gpio;
 
-        if (!pdev->dev.of_node)
-                return 0;
-
-        gpio = of_get_named_gpio(pdev->dev.of_node, "nvidia,vbus-gpio", 0);
+        gpio = pdata->vbus_gpio;
+        if (!gpio_is_valid(gpio))
+                gpio = of_get_named_gpio(pdev->dev.of_node,
+                                         "nvidia,vbus-gpio", 0);
         if (!gpio_is_valid(gpio))
                 return 0;
 
@@ -633,7 +634,7 @@ static int tegra_ehci_probe(struct platform_device *pdev)
         if (!pdev->dev.dma_mask)
                 pdev->dev.dma_mask = &tegra_ehci_dma_mask;
 
-        setup_vbus_gpio(pdev);
+        setup_vbus_gpio(pdev, pdata);
 
         tegra = kzalloc(sizeof(struct tegra_ehci_hcd), GFP_KERNEL);
         if (!tegra)
diff --git a/include/linux/of.h b/include/linux/of.h
index fa7fb1d97458..e3f942d9da89 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -259,6 +259,37 @@ extern void of_detach_node(struct device_node *);
 #endif
 
 #define of_match_ptr(_ptr)      (_ptr)
+
+/*
+ * struct property *prop;
+ * const __be32 *p;
+ * u32 u;
+ *
+ * of_property_for_each_u32(np, "propname", prop, p, u)
+ *         printk("U32 value: %x\n", u);
+ */
+const __be32 *of_prop_next_u32(struct property *prop, const __be32 *cur,
+                               u32 *pu);
+#define of_property_for_each_u32(np, propname, prop, p, u)      \
+        for (prop = of_find_property(np, propname, NULL),       \
+                p = of_prop_next_u32(prop, NULL, &u);           \
+                p;                                              \
+                p = of_prop_next_u32(prop, p, &u))
+
+/*
+ * struct property *prop;
+ * const char *s;
+ *
+ * of_property_for_each_string(np, "propname", prop, s)
+ *         printk("String value: %s\n", s);
+ */
+const char *of_prop_next_string(struct property *prop, const char *cur);
+#define of_property_for_each_string(np, propname, prop, s)      \
+        for (prop = of_find_property(np, propname, NULL),       \
+                s = of_prop_next_string(prop, NULL);            \
+                s;                                              \
+                s = of_prop_next_string(prop, s))
+
 #else /* CONFIG_OF */
 
 static inline bool of_have_populated_dt(void)
@@ -349,6 +380,10 @@ static inline int of_machine_is_compatible(const char *compat)
 
 #define of_match_ptr(_ptr)      NULL
 #define of_match_node(_matches, _node)  NULL
+#define of_property_for_each_u32(np, propname, prop, p, u) \
+        while (0)
+#define of_property_for_each_string(np, propname, prop, s) \
+        while (0)
 #endif /* CONFIG_OF */
 
 /**
diff --git a/include/linux/pinctrl/consumer.h b/include/linux/pinctrl/consumer.h
index 191e72688481..6dd96fb45482 100644
--- a/include/linux/pinctrl/consumer.h
+++ b/include/linux/pinctrl/consumer.h
@@ -36,6 +36,9 @@ extern struct pinctrl_state * __must_check pinctrl_lookup_state(
                                                         const char *name);
 extern int pinctrl_select_state(struct pinctrl *p, struct pinctrl_state *s);
 
+extern struct pinctrl * __must_check devm_pinctrl_get(struct device *dev);
+extern void devm_pinctrl_put(struct pinctrl *p);
+
 #else /* !CONFIG_PINCTRL */
 
 static inline int pinctrl_request_gpio(unsigned gpio)
@@ -79,6 +82,15 @@ static inline int pinctrl_select_state(struct pinctrl *p,
         return 0;
 }
 
+static inline struct pinctrl * __must_check devm_pinctrl_get(struct device *dev)
+{
+        return NULL;
+}
+
+static inline void devm_pinctrl_put(struct pinctrl *p)
+{
+}
+
 #endif /* CONFIG_PINCTRL */
 
 static inline struct pinctrl * __must_check pinctrl_get_select(
@@ -113,6 +125,38 @@ static inline struct pinctrl * __must_check pinctrl_get_select_default(
         return pinctrl_get_select(dev, PINCTRL_STATE_DEFAULT);
 }
 
+static inline struct pinctrl * __must_check devm_pinctrl_get_select(
+                                        struct device *dev, const char *name)
+{
+        struct pinctrl *p;
+        struct pinctrl_state *s;
+        int ret;
+
+        p = devm_pinctrl_get(dev);
+        if (IS_ERR(p))
+                return p;
+
+        s = pinctrl_lookup_state(p, name);
+        if (IS_ERR(s)) {
+                devm_pinctrl_put(p);
+                return ERR_PTR(PTR_ERR(s));
+        }
+
+        ret = pinctrl_select_state(p, s);
+        if (ret < 0) {
+                devm_pinctrl_put(p);
+                return ERR_PTR(ret);
+        }
+
+        return p;
+}
+
+static inline struct pinctrl * __must_check devm_pinctrl_get_select_default(
+                                        struct device *dev)
+{
+        return devm_pinctrl_get_select(dev, PINCTRL_STATE_DEFAULT);
+}
+
 #ifdef CONFIG_PINCONF
 
 extern int pin_config_get(const char *dev_name, const char *name,
diff --git a/include/linux/pinctrl/pinconf.h b/include/linux/pinctrl/pinconf.h
index ec431f03362d..7b9d5f00ed37 100644
--- a/include/linux/pinctrl/pinconf.h
+++ b/include/linux/pinctrl/pinconf.h
@@ -33,6 +33,8 @@ struct seq_file;
  *      per-device info for a certain pin in debugfs
  * @pin_config_group_dbg_show: optional debugfs display hook that will provide
  *      per-device info for a certain group in debugfs
+ * @pin_config_config_dbg_show: optional debugfs display hook that will decode
+ *      and display a driver's pin configuration parameter
  */
 struct pinconf_ops {
 #ifdef CONFIG_GENERIC_PINCONF
@@ -56,6 +58,9 @@ struct pinconf_ops {
         void (*pin_config_group_dbg_show) (struct pinctrl_dev *pctldev,
                                            struct seq_file *s,
                                            unsigned selector);
+        void (*pin_config_config_dbg_show) (struct pinctrl_dev *pctldev,
+                                            struct seq_file *s,
+                                            unsigned long config);
 };
 
 #endif
diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h
index 4e9f0788c221..c22d0409d2ef 100644
--- a/include/linux/pinctrl/pinctrl.h
+++ b/include/linux/pinctrl/pinctrl.h
@@ -21,9 +21,11 @@
 
 struct device;
 struct pinctrl_dev;
+struct pinctrl_map;
 struct pinmux_ops;
 struct pinconf_ops;
 struct gpio_chip;
+struct device_node;
 
 /**
  * struct pinctrl_pin_desc - boards/machines provide information on their
@@ -64,9 +66,7 @@ struct pinctrl_gpio_range {
 /**
  * struct pinctrl_ops - global pin control operations, to be implemented by
  * pin controller drivers.
- * @list_groups: list the number of selectable named groups available
- *      in this pinmux driver, the core will begin on 0 and call this
- *      repeatedly as long as it returns >= 0 to enumerate the groups
+ * @get_groups_count: Returns the count of total number of groups registered.
  * @get_group_name: return the group name of the pin group
  * @get_group_pins: return an array of pins corresponding to a certain
  *      group selector @pins, and the size of the array in @num_pins
@@ -74,7 +74,7 @@ struct pinctrl_gpio_range {
  *      info for a certain pin in debugfs
  */
 struct pinctrl_ops {
-        int (*list_groups) (struct pinctrl_dev *pctldev, unsigned selector);
+        int (*get_groups_count) (struct pinctrl_dev *pctldev);
         const char *(*get_group_name) (struct pinctrl_dev *pctldev,
                                        unsigned selector);
         int (*get_group_pins) (struct pinctrl_dev *pctldev,
@@ -83,6 +83,11 @@ struct pinctrl_ops {
                                unsigned *num_pins);
         void (*pin_dbg_show) (struct pinctrl_dev *pctldev, struct seq_file *s,
                           unsigned offset);
+        int (*dt_node_to_map) (struct pinctrl_dev *pctldev,
+                               struct device_node *np_config,
+                               struct pinctrl_map **map, unsigned *num_maps);
+        void (*dt_free_map) (struct pinctrl_dev *pctldev,
+                             struct pinctrl_map *map, unsigned num_maps);
 };
 
 /**
diff --git a/include/linux/pinctrl/pinmux.h b/include/linux/pinctrl/pinmux.h
index 47e9237edd47..dd7bef61d066 100644
--- a/include/linux/pinctrl/pinmux.h
+++ b/include/linux/pinctrl/pinmux.h
@@ -29,9 +29,8 @@ struct pinctrl_dev;
  *      is allowed to answer "no" by returning a negative error code
  * @free: the reverse function of the request() callback, frees a pin after
  *      being requested
- * @list_functions: list the number of selectable named functions available
- *      in this pinmux driver, the core will begin on 0 and call this
- *      repeatedly as long as it returns >= 0 to enumerate mux settings
+ * @get_functions_count: returns number of selectable named functions available
+ *      in this pinmux driver
  * @get_function_name: return the function name of the muxing selector,
  *      called by the core to figure out which mux setting it shall map a
  *      certain device to
@@ -62,7 +61,7 @@ struct pinctrl_dev;
 struct pinmux_ops {
         int (*request) (struct pinctrl_dev *pctldev, unsigned offset);
         int (*free) (struct pinctrl_dev *pctldev, unsigned offset);
-        int (*list_functions) (struct pinctrl_dev *pctldev, unsigned selector);
+        int (*get_functions_count) (struct pinctrl_dev *pctldev);
         const char *(*get_function_name) (struct pinctrl_dev *pctldev,
                                           unsigned selector);
         int (*get_function_groups) (struct pinctrl_dev *pctldev,
diff --git a/include/linux/platform_data/tegra_usb.h b/include/linux/platform_data/tegra_usb.h
index 6bca5b569acb..66c673fef408 100644
--- a/include/linux/platform_data/tegra_usb.h
+++ b/include/linux/platform_data/tegra_usb.h
@@ -26,6 +26,7 @@ struct tegra_ehci_platform_data {
         /* power down the phy on bus suspend */
         int power_down_on_bus_suspend;
         void *phy_config;
+        int vbus_gpio;
 };
 
 #endif /* _TEGRA_USB_H_ */