3 files changed, 24 insertions, 7 deletions

diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index c67f684ee3e5..09a87e61ffcf 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -520,7 +520,7 @@ fail:
          */
         if (have_imager()) {
                 label = "HD imager";
-                mux |= 1;
+                mux |= 2;
 
                 /* externally mux MMC1/ENET/AIC33 to imager */
                 mux |= BIT(6) | BIT(5) | BIT(3);
@@ -540,7 +540,7 @@ fail:
                 resets &= ~BIT(1);
 
                 if (have_tvp7002()) {
-                        mux |= 2;
+                        mux |= 1;
                         resets &= ~BIT(2);
                         label = "tvp7002 HD";
                 } else {
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index e7221398e5af..cafbe13a82a5 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -254,8 +254,10 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 {
         struct davinci_gpio_regs __iomem *g;
         u32 mask = 0xffff;
+        struct davinci_gpio_controller *d;
 
-        g = (__force struct davinci_gpio_regs __iomem *) irq_desc_get_handler_data(desc);
+        d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc);
+        g = (struct davinci_gpio_regs __iomem *)d->regs;
 
         /* we only care about one bank */
         if (irq & 1)
@@ -274,11 +276,14 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
                 if (!status)
                         break;
                 __raw_writel(status, &g->intstat);
-                if (irq & 1)
-                        status >>= 16;
 
                 /* now demux them to the right lowlevel handler */
-                n = (int)irq_get_handler_data(irq);
+                n = d->irq_base;
+                if (irq & 1) {
+                        n += 16;
+                        status >>= 16;
+                }
+
                 while (status) {
                         res = ffs(status);
                         n += res;
@@ -424,7 +429,13 @@ static int __init davinci_gpio_irq_setup(void)
 
                 /* set up all irqs in this bank */
                 irq_set_chained_handler(bank_irq, gpio_irq_handler);
-                irq_set_handler_data(bank_irq, (__force void *)g);
+
+                /*
+                 * Each chip handles 32 gpios, and each irq bank consists of 16
+                 * gpio irqs. Pass the irq bank's corresponding controller to
+                 * the chained irq handler.
+                 */
+                irq_set_handler_data(bank_irq, &chips[gpio / 32]);
 
                 for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
                         irq_set_chip(irq, &gpio_irqchip);
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c
index d8c1af025931..952dc126c390 100644
--- a/arch/arm/mach-davinci/irq.c
+++ b/arch/arm/mach-davinci/irq.c
@@ -52,6 +52,12 @@ davinci_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
         struct irq_chip_type *ct;
 
         gc = irq_alloc_generic_chip("AINTC", 1, irq_start, base, handle_edge_irq);
+        if (!gc) {
+                pr_err("%s: irq_alloc_generic_chip for IRQ %u failed\n",
+                       __func__, irq_start);
+                return;
+        }
+
         ct = gc->chip_types;
         ct->chip.irq_ack = irq_gc_ack_set_bit;
         ct->chip.irq_mask = irq_gc_mask_clr_bit;