319 files changed, 3715 insertions, 13811 deletions

diff --git a/Documentation/ABI/testing/sysfs-driver-tegra-fuse b/Documentation/ABI/testing/sysfs-driver-tegra-fuse
new file mode 100644
index 000000000000..69f5af632657
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-driver-tegra-fuse
@@ -0,0 +1,11 @@
+What:           /sys/devices/*/<our-device>/fuse
+Date:           February 2014
+Contact:        Peter De Schrijver <pdeschrijver@nvidia.com>
+Description:    read-only access to the efuses on Tegra20, Tegra30, Tegra114
+                and Tegra124 SoC's from NVIDIA. The efuses contain write once
+                data programmed at the factory. The data is layed out in 32bit
+                words in LSB first format. Each bit represents a single value
+                as decoded from the fuse registers. Bits order/assignment
+                exactly matches the HW registers, including any unused bits.
+Users:          any user space application which wants to read the efuses on
+                Tegra SoC's
diff --git a/Documentation/arm/Samsung/Overview.txt b/Documentation/arm/Samsung/Overview.txt
index 658abb258cef..8f7309bad460 100644
--- a/Documentation/arm/Samsung/Overview.txt
+++ b/Documentation/arm/Samsung/Overview.txt
@@ -13,8 +13,6 @@ Introduction
 
   - S3C24XX: See Documentation/arm/Samsung-S3C24XX/Overview.txt for full list
   - S3C64XX: S3C6400 and S3C6410
-  - S5P6440
-  - S5PC100
   - S5PC110 / S5PV210
 
 
@@ -34,8 +32,6 @@ Configuration
   A number of configurations are supplied, as there is no current way of
   unifying all the SoCs into one kernel.
 
-  s5p6440_defconfig - S5P6440 specific default configuration
-  s5pc100_defconfig - S5PC100 specific default configuration
   s5pc110_defconfig - S5PC110 specific default configuration
   s5pv210_defconfig - S5PV210 specific default configuration
 
@@ -67,13 +63,6 @@ Layout changes
   where to simplify the include and dependency issues involved with having
   so many different platform directories.
 
-  It was decided to remove plat-s5pc1xx as some of the support was already
-  in plat-s5p or plat-samsung, with the S5PC110 support added with S5PV210
-  the only user was the S5PC100. The S5PC100 specific items where moved to
-  arch/arm/mach-s5pc100.
-
-
-
 
 Port Contributors
 -----------------
diff --git a/Documentation/arm/Samsung/clksrc-change-registers.awk b/Documentation/arm/Samsung/clksrc-change-registers.awk
index 0c50220851fb..d9174fabe37e 100755
--- a/Documentation/arm/Samsung/clksrc-change-registers.awk
+++ b/Documentation/arm/Samsung/clksrc-change-registers.awk
@@ -68,7 +68,6 @@ BEGIN {
 
     while (getline line < ARGV[1] > 0) {
         if (line ~ /\#define.*_MASK/ &&
-            !(line ~ /S5PC100_EPLL_MASK/) &&
             !(line ~ /USB_SIG_MASK/)) {
             splitdefine(line, fields)
             name = fields[0]
diff --git a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt
new file mode 100644
index 000000000000..d8c98c7614d0
--- /dev/null
+++ b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt
@@ -0,0 +1,40 @@
+NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block.
+
+Required properties:
+- compatible : should be:
+        "nvidia,tegra20-efuse"
+        "nvidia,tegra30-efuse"
+        "nvidia,tegra114-efuse"
+        "nvidia,tegra124-efuse"
+  Details:
+  nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data
+        due to a hardware bug. Tegra20 also lacks certain information which is
+        available in later generations such as fab code, lot code, wafer id,..
+  nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse:
+        The differences between these SoCs are the size of the efuse array,
+        the location of the spare (OEM programmable) bits and the location of
+        the speedo data.
+- reg: Should contain 1 entry: the entry gives the physical address and length
+       of the fuse registers.
+- clocks: Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
+- clock-names: Must include the following entries:
+  - fuse
+- resets: Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names: Must include the following entries:
+ - fuse
+
+Example:
+
+        fuse@7000f800 {
+                compatible = "nvidia,tegra20-efuse";
+                reg = <0x7000F800 0x400>,
+                      <0x70000000 0x400>;
+                clocks = <&tegra_car TEGRA20_CLK_FUSE>;
+                clock-names = "fuse";
+                resets = <&tegra_car 39>;
+                reset-names = "fuse";
+        };
+
+
diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt
new file mode 100644
index 000000000000..b97b8bef1fe5
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt
@@ -0,0 +1,13 @@
+NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 apbmisc block
+
+Required properties:
+- compatible : should be:
+       "nvidia,tegra20-apbmisc"
+       "nvidia,tegra30-apbmisc"
+       "nvidia,tegra114-apbmisc"
+       "nvidia,tegra124-apbmisc"
+- reg: Should contain 2 entries: the first entry gives the physical address
+       and length of the registers which contain revision and debug features.
+       The second entry gives the physical address and length of the
+       registers indicating the strapping options.
+
diff --git a/Documentation/devicetree/bindings/spi/spi-samsung.txt b/Documentation/devicetree/bindings/spi/spi-samsung.txt
index 792efbaedc54..1e8a8578148f 100644
--- a/Documentation/devicetree/bindings/spi/spi-samsung.txt
+++ b/Documentation/devicetree/bindings/spi/spi-samsung.txt
@@ -8,7 +8,6 @@ Required SoC Specific Properties:
 - compatible: should be one of the following.
     - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms
     - samsung,s3c6410-spi: for s3c6410 platforms
-    - samsung,s5p6440-spi: for s5p6440 and s5p6450 platforms
     - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms
     - samsung,exynos4210-spi: for exynos4 and exynos5 platforms
 
diff --git a/Documentation/devicetree/bindings/video/samsung-fimd.txt b/Documentation/devicetree/bindings/video/samsung-fimd.txt
index 8428fcff8037..ecc899b9817b 100644
--- a/Documentation/devicetree/bindings/video/samsung-fimd.txt
+++ b/Documentation/devicetree/bindings/video/samsung-fimd.txt
@@ -8,8 +8,6 @@ Required properties:
 - compatible: value should be one of the following
                 "samsung,s3c2443-fimd"; /* for S3C24XX SoCs */
                 "samsung,s3c6400-fimd"; /* for S3C64XX SoCs */
-                "samsung,s5p6440-fimd"; /* for S5P64X0 SoCs */
-                "samsung,s5pc100-fimd"; /* for S5PC100 SoC  */
                 "samsung,s5pv210-fimd"; /* for S5PV210 SoC */
                 "samsung,exynos4210-fimd"; /* for Exynos4 SoCs */
                 "samsung,exynos5250-fimd"; /* for Exynos5 SoCs */
diff --git a/MAINTAINERS b/MAINTAINERS
index 8b0c4e22119c..28f2e65d738e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1116,14 +1116,13 @@ L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:      Maintained
 F:      arch/arm/mach-berlin/
 
-ARM/Marvell Dove/Kirkwood/MV78xx0/Orion SOC support
+ARM/Marvell Dove/MV78xx0/Orion SOC support
 M:      Jason Cooper <jason@lakedaemon.net>
 M:      Andrew Lunn <andrew@lunn.ch>
 M:      Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
 L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:      Maintained
 F:      arch/arm/mach-dove/
-F:      arch/arm/mach-kirkwood/
 F:      arch/arm/mach-mv78xx0/
 F:      arch/arm/mach-orion5x/
 F:      arch/arm/plat-orion/
@@ -1376,6 +1375,7 @@ F:	drivers/pinctrl/pinctrl-st.c
 F:      drivers/media/rc/st_rc.c
 F:      drivers/i2c/busses/i2c-st.c
 F:      drivers/tty/serial/st-asc.c
+F:      drivers/mmc/host/sdhci-st.c
 
 ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT
 M:      Lennert Buytenhek <kernel@wantstofly.org>
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d31c500653a2..31b17f3fe2b4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -239,13 +239,6 @@ config ARM_PATCH_PHYS_VIRT
           this feature (eg, building a kernel for a single machine) and
           you need to shrink the kernel to the minimal size.
 
-config NEED_MACH_GPIO_H
-        bool
-        help
-          Select this when mach/gpio.h is required to provide special
-          definitions for this platform. The need for mach/gpio.h should
-          be avoided when possible.
-
 config NEED_MACH_IO_H
         bool
         help
@@ -334,7 +327,6 @@ config ARCH_INTEGRATOR
         select HAVE_TCM
         select ICST
         select MULTI_IRQ_HANDLER
-        select NEED_MACH_MEMORY_H
         select PLAT_VERSATILE
         select SPARSE_IRQ
         select USE_OF
@@ -354,7 +346,6 @@ config ARCH_REALVIEW
         select ICST
         select NEED_MACH_MEMORY_H
         select PLAT_VERSATILE
-        select PLAT_VERSATILE_CLCD
         help
           This enables support for ARM Ltd RealView boards.
 
@@ -369,7 +360,6 @@ config ARCH_VERSATILE
         select HAVE_MACH_CLKDEV
         select ICST
         select PLAT_VERSATILE
-        select PLAT_VERSATILE_CLCD
         select PLAT_VERSATILE_CLOCK
         select VERSATILE_FPGA_IRQ
         help
@@ -772,42 +762,6 @@ config ARCH_S3C64XX
         help
           Samsung S3C64XX series based systems
 
-config ARCH_S5P64X0
-        bool "Samsung S5P6440 S5P6450"
-        select ATAGS
-        select CLKDEV_LOOKUP
-        select CLKSRC_SAMSUNG_PWM
-        select CPU_V6
-        select GENERIC_CLOCKEVENTS
-        select GPIO_SAMSUNG
-        select HAVE_S3C2410_I2C if I2C
-        select HAVE_S3C2410_WATCHDOG if WATCHDOG
-        select HAVE_S3C_RTC if RTC_CLASS
-        select NEED_MACH_GPIO_H
-        select SAMSUNG_ATAGS
-        select SAMSUNG_WDT_RESET
-        help
-          Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
-          SMDK6450.
-
-config ARCH_S5PC100
-        bool "Samsung S5PC100"
-        select ARCH_REQUIRE_GPIOLIB
-        select ATAGS
-        select CLKDEV_LOOKUP
-        select CLKSRC_SAMSUNG_PWM
-        select CPU_V7
-        select GENERIC_CLOCKEVENTS
-        select GPIO_SAMSUNG
-        select HAVE_S3C2410_I2C if I2C
-        select HAVE_S3C2410_WATCHDOG if WATCHDOG
-        select HAVE_S3C_RTC if RTC_CLASS
-        select NEED_MACH_GPIO_H
-        select SAMSUNG_ATAGS
-        select SAMSUNG_WDT_RESET
-        help
-          Samsung S5PC100 series based systems
-
 config ARCH_S5PV210
         bool "Samsung S5PV210/S5PC110"
         select ARCH_HAS_HOLES_MEMORYMODEL
@@ -821,7 +775,6 @@ config ARCH_S5PV210
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
         select HAVE_S3C_RTC if RTC_CLASS
-        select NEED_MACH_GPIO_H
         select NEED_MACH_MEMORY_H
         select SAMSUNG_ATAGS
         help
@@ -1018,10 +971,6 @@ source "arch/arm/mach-s3c24xx/Kconfig"
 
 source "arch/arm/mach-s3c64xx/Kconfig"
 
-source "arch/arm/mach-s5p64x0/Kconfig"
-
-source "arch/arm/mach-s5pc100/Kconfig"
-
 source "arch/arm/mach-s5pv210/Kconfig"
 
 source "arch/arm/mach-exynos/Kconfig"
@@ -1583,7 +1532,7 @@ source kernel/Kconfig.preempt
 
 config HZ_FIXED
         int
-        default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
+        default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
                 ARCH_S5PV210 || ARCH_EXYNOS4
         default AT91_TIMER_HZ if ARCH_AT91
         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
@@ -2208,7 +2157,6 @@ menu "Power management options"
 source "kernel/power/Kconfig"
 
 config ARCH_SUSPEND_POSSIBLE
-        depends on !ARCH_S5PC100
         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
         def_bool y
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 8f90595069a1..b24b5dc720e4 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -617,53 +617,41 @@ choice
                 depends on PLAT_SAMSUNG
                 select DEBUG_EXYNOS_UART if ARCH_EXYNOS
                 select DEBUG_S3C24XX_UART if ARCH_S3C24XX
-                bool "Use S3C UART 0 for low-level debug"
+                bool "Use Samsung S3C UART 0 for low-level debug"
                 help
                   Say Y here if you want the debug print routines to direct
                   their output to UART 0. The port must have been initialised
                   by the boot-loader before use.
 
-                  The uncompressor code port configuration is now handled
-                  by CONFIG_S3C_LOWLEVEL_UART_PORT.
-
         config DEBUG_S3C_UART1
                 depends on PLAT_SAMSUNG
                 select DEBUG_EXYNOS_UART if ARCH_EXYNOS
                 select DEBUG_S3C24XX_UART if ARCH_S3C24XX
-                bool "Use S3C UART 1 for low-level debug"
+                bool "Use Samsung S3C UART 1 for low-level debug"
                 help
                   Say Y here if you want the debug print routines to direct
                   their output to UART 1. The port must have been initialised
                   by the boot-loader before use.
 
-                  The uncompressor code port configuration is now handled
-                  by CONFIG_S3C_LOWLEVEL_UART_PORT.
-
         config DEBUG_S3C_UART2
                 depends on PLAT_SAMSUNG
                 select DEBUG_EXYNOS_UART if ARCH_EXYNOS
                 select DEBUG_S3C24XX_UART if ARCH_S3C24XX
-                bool "Use S3C UART 2 for low-level debug"
+                bool "Use Samsung S3C UART 2 for low-level debug"
                 help
                   Say Y here if you want the debug print routines to direct
                   their output to UART 2. The port must have been initialised
                   by the boot-loader before use.
 
-                  The uncompressor code port configuration is now handled
-                  by CONFIG_S3C_LOWLEVEL_UART_PORT.
-
         config DEBUG_S3C_UART3
                 depends on PLAT_SAMSUNG && ARCH_EXYNOS
                 select DEBUG_EXYNOS_UART
-                bool "Use S3C UART 3 for low-level debug"
+                bool "Use Samsung S3C UART 3 for low-level debug"
                 help
                   Say Y here if you want the debug print routines to direct
                   their output to UART 3. The port must have been initialised
                   by the boot-loader before use.
 
-                  The uncompressor code port configuration is now handled
-                  by CONFIG_S3C_LOWLEVEL_UART_PORT.
-
         config DEBUG_S3C2410_UART0
                 depends on ARCH_S3C24XX
                 select DEBUG_S3C2410_UART
@@ -991,6 +979,7 @@ config DEBUG_STI_UART
 config DEBUG_LL_INCLUDE
         string
         default "debug/8250.S" if DEBUG_LL_UART_8250 || DEBUG_UART_8250
+        default "debug/clps711x.S" if DEBUG_CLPS711X_UART1 || DEBUG_CLPS711X_UART2
         default "debug/pl01x.S" if DEBUG_LL_UART_PL01X || DEBUG_UART_PL01X
         default "debug/exynos.S" if DEBUG_EXYNOS_UART
         default "debug/efm32.S" if DEBUG_LL_UART_EFM32
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 718913dfe815..1e42de45110b 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -190,8 +190,6 @@ machine-$(CONFIG_ARCH_ROCKCHIP)		+= rockchip
 machine-$(CONFIG_ARCH_RPC)              += rpc
 machine-$(CONFIG_ARCH_S3C24XX)          += s3c24xx
 machine-$(CONFIG_ARCH_S3C64XX)          += s3c64xx
-machine-$(CONFIG_ARCH_S5P64X0)          += s5p64x0
-machine-$(CONFIG_ARCH_S5PC100)          += s5pc100
 machine-$(CONFIG_ARCH_S5PV210)          += s5pv210
 machine-$(CONFIG_ARCH_SA1100)           += sa1100
 machine-$(CONFIG_ARCH_SHMOBILE)         += shmobile
diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi
index e37985fa10e2..00eeed3721b6 100644
--- a/arch/arm/boot/dts/emev2.dtsi
+++ b/arch/arm/boot/dts/emev2.dtsi
@@ -31,11 +31,13 @@
                         device_type = "cpu";
                         compatible = "arm,cortex-a9";
                         reg = <0>;
+                        clock-frequency = <533000000>;
                 };
                 cpu@1 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a9";
                         reg = <1>;
+                        clock-frequency = <533000000>;
                 };
         };
 
diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts
index b10e6351da53..cf06e32ee108 100644
--- a/arch/arm/boot/dts/integratorap.dts
+++ b/arch/arm/boot/dts/integratorap.dts
@@ -8,6 +8,7 @@
 / {
         model = "ARM Integrator/AP";
         compatible = "arm,integrator-ap";
+        dma-ranges = <0x80000000 0x0 0x80000000>;
 
         aliases {
                 arm,timer-primary = &timer2;
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index a4ed54988866..8eee6fbef7ad 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -985,6 +985,66 @@
                                 dma-names = "audio_tx";
                         };
                 };
+
+                abb_mpu: regulator-abb-mpu {
+                        compatible = "ti,abb-v2";
+                        regulator-name = "abb_mpu";
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        clocks = <&sys_clkin>;
+                        ti,settling-time = <50>;
+                        ti,clock-cycles = <16>;
+
+                        reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
+                              <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
+                        reg-names = "base-address", "int-address",
+                                    "efuse-address", "ldo-address";
+                        ti,tranxdone-status-mask = <0x80>;
+                        /* LDOVBBMPU_MUX_CTRL */
+                        ti,ldovbb-override-mask = <0x400>;
+                        /* LDOVBBMPU_VSET_OUT */
+                        ti,ldovbb-vset-mask = <0x1F>;
+
+                        /*
+                         * NOTE: only FBB mode used but actual vset will
+                         * determine final biasing
+                         */
+                        ti,abb_info = <
+                        /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
+                        1060000         0       0x0     0 0x02000000 0x01F00000
+                        1250000         0       0x4     0 0x02000000 0x01F00000
+                        >;
+                };
+
+                abb_mm: regulator-abb-mm {
+                        compatible = "ti,abb-v2";
+                        regulator-name = "abb_mm";
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        clocks = <&sys_clkin>;
+                        ti,settling-time = <50>;
+                        ti,clock-cycles = <16>;
+
+                        reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
+                              <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
+                        reg-names = "base-address", "int-address",
+                                    "efuse-address", "ldo-address";
+                        ti,tranxdone-status-mask = <0x80000000>;
+                        /* LDOVBBMM_MUX_CTRL */
+                        ti,ldovbb-override-mask = <0x400>;
+                        /* LDOVBBMM_VSET_OUT */
+                        ti,ldovbb-vset-mask = <0x1F>;
+
+                        /*
+                         * NOTE: only FBB mode used but actual vset will
+                         * determine final biasing
+                         */
+                        ti,abb_info = <
+                        /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
+                        1025000         0       0x0     0 0x02000000 0x01F00000
+                        1120000         0       0x4     0 0x02000000 0x01F00000
+                        >;
+                };
         };
 };
 
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index f50fbc8f3bd9..bdee22541189 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -144,6 +144,7 @@
                         device_type = "cpu";
                         compatible = "arm,cortex-a9";
                         reg = <0>;
+                        clock-frequency = <400000000>;
                 };
         };
 
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 7da20ca633dd..80b8eddb4105 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -220,6 +220,12 @@
                 interrupt-controller;
         };
 
+        apbmisc@70000800 {
+                compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";
+                reg = <0x70000800 0x64   /* Chip revision */
+                       0x70000008 0x04>; /* Strapping options */
+        };
+
         pinmux: pinmux@70000868 {
                 compatible = "nvidia,tegra114-pinmux";
                 reg = <0x70000868 0x148         /* Pad control registers */
@@ -485,6 +491,15 @@
                 clock-names = "pclk", "clk32k_in";
         };
 
+        fuse@7000f800 {
+                compatible = "nvidia,tegra114-efuse";
+                reg = <0x7000f800 0x400>;
+                clocks = <&tegra_car TEGRA114_CLK_FUSE>;
+                clock-names = "fuse";
+                resets = <&tegra_car 39>;
+                reset-names = "fuse";
+        };
+
         iommu@70019010 {
                 compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
                 reg = <0x70019010 0x02c
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index aa8753a7c211..d44e9b91e207 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -179,6 +179,12 @@
                 #dma-cells = <1>;
         };
 
+        apbmisc@0,70000800 {
+                compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
+                reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */
+                      <0x0 0x7000E864 0x0 0x04>;   /* Strapping options */
+        };
+
         pinmux: pinmux@0,70000868 {
                 compatible = "nvidia,tegra124-pinmux";
                 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
@@ -449,6 +455,15 @@
                 clock-names = "pclk", "clk32k_in";
         };
 
+        fuse@0,7000f800 {
+                compatible = "nvidia,tegra124-efuse";
+                reg = <0x0 0x7000f800 0x0 0x400>;
+                clocks = <&tegra_car TEGRA124_CLK_FUSE>;
+                clock-names = "fuse";
+                resets = <&tegra_car 39>;
+                reset-names = "fuse";
+        };
+
         sdhci@0,700b0000 {
                 compatible = "nvidia,tegra124-sdhci";
                 reg = <0x0 0x700b0000 0x0 0x200>;
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 935df8906f25..1908f6937e53 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -236,6 +236,12 @@
                 interrupt-controller;
         };
 
+        apbmisc@70000800 {
+                compatible = "nvidia,tegra20-apbmisc";
+                reg = <0x70000800 0x64   /* Chip revision */
+                       0x70000008 0x04>; /* Strapping options */
+        };
+
         pinmux: pinmux@70000014 {
                 compatible = "nvidia,tegra20-pinmux";
                 reg = <0x70000014 0x10   /* Tri-state registers */
@@ -545,6 +551,15 @@
                 #size-cells = <0>;
         };
 
+        fuse@7000f800 {
+                compatible = "nvidia,tegra20-efuse";
+                reg = <0x7000F800 0x400>;
+                clocks = <&tegra_car TEGRA20_CLK_FUSE>;
+                clock-names = "fuse";
+                resets = <&tegra_car 39>;
+                reset-names = "fuse";
+        };
+
         pcie-controller@80003000 {
                 compatible = "nvidia,tegra20-pcie";
                 device_type = "pci";
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 54805ce5efe0..6b35c29278d7 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -335,6 +335,12 @@
                 interrupt-controller;
         };
 
+        apbmisc@70000800 {
+                compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
+                reg = <0x70000800 0x64   /* Chip revision */
+                       0x70000008 0x04>; /* Strapping options */
+        };
+
         pinmux: pinmux@70000868 {
                 compatible = "nvidia,tegra30-pinmux";
                 reg = <0x70000868 0xd4    /* Pad control registers */
@@ -631,6 +637,15 @@
                 nvidia,ahb = <&ahb>;
         };
 
+        fuse@7000f800 {
+                compatible = "nvidia,tegra30-efuse";
+                reg = <0x7000f800 0x400>;
+                clocks = <&tegra_car TEGRA30_CLK_FUSE>;
+                clock-names = "fuse";
+                resets = <&tegra_car 39>;
+                reset-names = "fuse";
+        };
+
         ahub@70080000 {
                 compatible = "nvidia,tegra30-ahub";
                 reg = <0x70080000 0x200
diff --git a/arch/arm/configs/s5p64x0_defconfig b/arch/arm/configs/s5p64x0_defconfig
deleted file mode 100644
index ad6b61b0bd11..000000000000
--- a/arch/arm/configs/s5p64x0_defconfig
+++ /dev/null
@@ -1,68 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_S5P64X0=y
-CONFIG_S3C_BOOT_ERROR_RESET=y
-CONFIG_S3C_LOWLEVEL_UART_PORT=1
-CONFIG_MACH_SMDK6440=y
-CONFIG_MACH_SMDK6450=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_CPU_32v6K=y
-CONFIG_AEABI=y
-CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc"
-CONFIG_FPE_NWFPE=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-# CONFIG_MISC_DEVICES is not set
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_SG=y
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_NR_UARTS=3
-CONFIG_SERIAL_SAMSUNG=y
-CONFIG_SERIAL_SAMSUNG_CONSOLE=y
-CONFIG_HW_RANDOM=y
-# CONFIG_HWMON is not set
-CONFIG_DISPLAY_SUPPORT=y
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_INOTIFY=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_CRAMFS=y
-CONFIG_ROMFS_FS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_RT_MUTEXES=y
-CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_MUTEXES=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_S3C_UART=1
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/s5pc100_defconfig b/arch/arm/configs/s5pc100_defconfig
deleted file mode 100644
index 41bafc94dd85..000000000000
--- a/arch/arm/configs/s5pc100_defconfig
+++ /dev/null
@@ -1,49 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_S5PC100=y
-CONFIG_MACH_SMDKC100=y
-CONFIG_AEABI=y
-CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=cramfs init=/linuxrc console=ttySAC2,115200 mem=128M"
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_EEPROM_AT24=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_SAMSUNG=y
-CONFIG_SERIAL_SAMSUNG_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_MMC=y
-CONFIG_MMC_DEBUG=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_SDIO_UART=y
-CONFIG_MMC_SDHCI=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_INOTIFY=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_CRAMFS=y
-CONFIG_ROMFS_FS=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_RT_MUTEXES=y
-CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_MUTEXES=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-CONFIG_DEBUG_LL=y
diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h
index 477e0206e016..504dcddebfcc 100644
--- a/arch/arm/include/asm/gpio.h
+++ b/arch/arm/include/asm/gpio.h
@@ -5,12 +5,6 @@
 #define ARCH_NR_GPIOS CONFIG_ARCH_NR_GPIO
 #endif
 
-/* not all ARM platforms necessarily support this API ... */
-#ifdef CONFIG_NEED_MACH_GPIO_H
-#include <mach/gpio.h>
-#endif
-
-#ifndef __ARM_GPIOLIB_COMPLEX
 /* Note: this may rely upon the value of ARCH_NR_GPIOS set in mach/gpio.h */
 #include <asm-generic/gpio.h>
 
@@ -18,7 +12,6 @@
 #define gpio_get_value  __gpio_get_value
 #define gpio_set_value  __gpio_set_value
 #define gpio_cansleep   __gpio_cansleep
-#endif
 
 /*
  * Provide a default gpio_to_irq() which should satisfy every case.
diff --git a/arch/arm/include/debug/clps711x.S b/arch/arm/include/debug/clps711x.S
new file mode 100644
index 000000000000..abe225436686
--- /dev/null
+++ b/arch/arm/include/debug/clps711x.S
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef CONFIG_DEBUG_CLPS711X_UART2
+#define CLPS711X_UART_PADDR     (0x80000000 + 0x0000)
+#define CLPS711X_UART_VADDR     (0xfeff0000 + 0x0000)
+#else
+#define CLPS711X_UART_PADDR     (0x80000000 + 0x1000)
+#define CLPS711X_UART_VADDR     (0xfeff0000 + 0x1000)
+#endif
+
+#define SYSFLG          (0x0140)
+#define SYSFLG_UBUSY    (1 << 11)
+#define UARTDR          (0x0480)
+
+        .macro  addruart, rp, rv, tmp
+        ldr     \rv, =CLPS711X_UART_VADDR
+        ldr     \rp, =CLPS711X_UART_PADDR
+        .endm
+
+        .macro  waituart,rd,rx
+        .endm
+
+        .macro  senduart,rd,rx
+        str     \rd, [\rx, #UARTDR]
+        .endm
+
+        .macro  busyuart,rd,rx
+1001:   ldr     \rd, [\rx, #SYSFLG]
+        tst     \rd, #SYSFLG_UBUSY
+        bne     1001b
+        .endm
diff --git a/arch/arm/mach-clps711x/board-autcpu12.c b/arch/arm/mach-clps711x/board-autcpu12.c
index d62ca16d5394..45abf6bd5f68 100644
--- a/arch/arm/mach-clps711x/board-autcpu12.c
+++ b/arch/arm/mach-clps711x/board-autcpu12.c
@@ -266,7 +266,6 @@ MACHINE_START(AUTCPU12, "autronix autcpu12")
         /* Maintainer: Thomas Gleixner */
         .atag_offset    = 0x20000,
         .map_io         = clps711x_map_io,
-        .init_early     = clps711x_init_early,
         .init_irq       = clps711x_init_irq,
         .init_time      = clps711x_timer_init,
         .init_machine   = autcpu12_init,
diff --git a/arch/arm/mach-clps711x/board-cdb89712.c b/arch/arm/mach-clps711x/board-cdb89712.c
index e261a47f2aff..1ec378c334e5 100644
--- a/arch/arm/mach-clps711x/board-cdb89712.c
+++ b/arch/arm/mach-clps711x/board-cdb89712.c
@@ -140,7 +140,6 @@ MACHINE_START(CDB89712, "Cirrus-CDB89712")
         /* Maintainer: Ray Lehtiniemi */
         .atag_offset    = 0x100,
         .map_io         = clps711x_map_io,
-        .init_early     = clps711x_init_early,
         .init_irq       = clps711x_init_irq,
         .init_time      = clps711x_timer_init,
         .init_machine   = cdb89712_init,
diff --git a/arch/arm/mach-clps711x/board-clep7312.c b/arch/arm/mach-clps711x/board-clep7312.c
index 94a7add88a3f..f9ca22b646bf 100644
--- a/arch/arm/mach-clps711x/board-clep7312.c
+++ b/arch/arm/mach-clps711x/board-clep7312.c
@@ -25,6 +25,7 @@
 #include <asm/mach/arch.h>
 
 #include "common.h"
+#include "devices.h"
 
 static void __init
 fixup_clep7312(struct tag *tags, char **cmdline)
@@ -37,8 +38,8 @@ MACHINE_START(CLEP7212, "Cirrus Logic 7212/7312")
         .atag_offset    = 0x0100,
         .fixup          = fixup_clep7312,
         .map_io         = clps711x_map_io,
-        .init_early     = clps711x_init_early,
         .init_irq       = clps711x_init_irq,
         .init_time      = clps711x_timer_init,
+        .init_machine   = clps711x_devices_init,
         .restart        = clps711x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-clps711x/board-edb7211.c b/arch/arm/mach-clps711x/board-edb7211.c
index 6144fb5cdc36..fdf54d40909a 100644
--- a/arch/arm/mach-clps711x/board-edb7211.c
+++ b/arch/arm/mach-clps711x/board-edb7211.c
@@ -148,11 +148,6 @@ fixup_edb7211(struct tag *tags, char **cmdline)
         memblock_add(0xc1000000, SZ_8M);
 }
 
-static void __init edb7211_init(void)
-{
-        clps711x_devices_init();
-}
-
 static void __init edb7211_init_late(void)
 {
         gpio_request_array(edb7211_gpios, ARRAY_SIZE(edb7211_gpios));
@@ -178,10 +173,9 @@ MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
         .fixup          = fixup_edb7211,
         .reserve        = edb7211_reserve,
         .map_io         = clps711x_map_io,
-        .init_early     = clps711x_init_early,
         .init_irq       = clps711x_init_irq,
         .init_time      = clps711x_timer_init,
-        .init_machine   = edb7211_init,
+        .init_machine   = clps711x_devices_init,
         .init_late      = edb7211_init_late,
         .restart        = clps711x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-clps711x/board-p720t.c b/arch/arm/mach-clps711x/board-p720t.c
index 96bcc76c4437..e68dd629bda2 100644
--- a/arch/arm/mach-clps711x/board-p720t.c
+++ b/arch/arm/mach-clps711x/board-p720t.c
@@ -365,7 +365,6 @@ MACHINE_START(P720T, "ARM-Prospector720T")
         .atag_offset    = 0x100,
         .fixup          = fixup_p720t,
         .map_io         = clps711x_map_io,
-        .init_early     = clps711x_init_early,
         .init_irq       = clps711x_init_irq,
         .init_time      = clps711x_timer_init,
         .init_machine   = p720t_init,
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index aee81fa46ccf..2a6323b15782 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -193,15 +193,3 @@ void clps711x_restart(enum reboot_mode mode, const char *cmd)
 {
         soft_restart(0);
 }
-
-static void clps711x_idle(void)
-{
-        clps_writel(1, HALT);
-        asm("mov r0, r0");
-        asm("mov r0, r0");
-}
-
-void __init clps711x_init_early(void)
-{
-        arm_pm_idle = clps711x_idle;
-}
diff --git a/arch/arm/mach-clps711x/common.h b/arch/arm/mach-clps711x/common.h
index 7489139d5d63..f88189963898 100644
--- a/arch/arm/mach-clps711x/common.h
+++ b/arch/arm/mach-clps711x/common.h
@@ -13,7 +13,6 @@ extern void clps711x_map_io(void);
 extern void clps711x_init_irq(void);
 extern void clps711x_timer_init(void);
 extern void clps711x_restart(enum reboot_mode mode, const char *cmd);
-extern void clps711x_init_early(void);
 
 /* drivers/irqchip/irq-clps711x.c */
 void clps711x_intc_init(phys_addr_t, resource_size_t);
diff --git a/arch/arm/mach-clps711x/devices.c b/arch/arm/mach-clps711x/devices.c
index 2001488a5ef2..0c689d3a6710 100644
--- a/arch/arm/mach-clps711x/devices.c
+++ b/arch/arm/mach-clps711x/devices.c
@@ -14,6 +14,15 @@
 
 #include <mach/hardware.h>
 
+static const struct resource clps711x_cpuidle_res __initconst =
+        DEFINE_RES_MEM(CLPS711X_PHYS_BASE + HALT, SZ_128);
+
+static void __init clps711x_add_cpuidle(void)
+{
+        platform_device_register_simple("clps711x-cpuidle", PLATFORM_DEVID_NONE,
+                                        &clps711x_cpuidle_res, 1);
+}
+
 static const phys_addr_t clps711x_gpios[][2] __initconst = {
         { PADR, PADDR },
         { PBDR, PBDDR },
@@ -83,6 +92,7 @@ static void __init clps711x_add_uart(void)
 
 void __init clps711x_devices_init(void)
 {
+        clps711x_add_cpuidle();
         clps711x_add_gpio();
         clps711x_add_syscon();
         clps711x_add_uart();
diff --git a/arch/arm/mach-clps711x/include/mach/debug-macro.S b/arch/arm/mach-clps711x/include/mach/debug-macro.S
deleted file mode 100644
index cb3684f8dae0..000000000000
--- a/arch/arm/mach-clps711x/include/mach/debug-macro.S
+++ /dev/null
@@ -1,38 +0,0 @@
-/* arch/arm/mach-clps711x/include/mach/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-#include <mach/hardware.h>
-
-                .macro  addruart, rp, rv, tmp
-#ifndef CONFIG_DEBUG_CLPS711X_UART2
-                mov     \rp, #0x0000    @ UART1
-#else
-                mov     \rp, #0x1000    @ UART2
-#endif
-                orr     \rv, \rp, #CLPS711X_VIRT_BASE
-                orr     \rp, \rp, #CLPS711X_PHYS_BASE
-                .endm
-
-                .macro  senduart,rd,rx
-                str     \rd, [\rx, #0x0480]     @ UARTDR
-                .endm
-
-                .macro  waituart,rd,rx
-                .endm
-
-                .macro  busyuart,rd,rx
-1001:           ldr     \rd, [\rx, #0x0140]     @ SYSFLGx
-                tst     \rd, #1 << 11           @ UBUSYx
-                bne     1001b
-                .endm
-
diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h
index 5d6afda1c0e8..833129c9f798 100644
--- a/arch/arm/mach-clps711x/include/mach/hardware.h
+++ b/arch/arm/mach-clps711x/include/mach/hardware.h
@@ -24,10 +24,7 @@
 
 #include <mach/clps711x.h>
 
-#define IO_ADDRESS(x)           (0xdc000000 + (((x) & 0x03ffffff) | \
-                                (((x) >> 2) & 0x3c000000)))
-
-#define CLPS711X_VIRT_BASE      IOMEM(IO_ADDRESS(CLPS711X_PHYS_BASE))
+#define CLPS711X_VIRT_BASE      IOMEM(0xfeff0000)
 
 #ifndef __ASSEMBLY__
 #define clps_readb(off)         readb(CLPS711X_VIRT_BASE + (off))
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 1ee91763fa7c..f8daa9cc5617 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -111,25 +111,14 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK)
 #define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5410() || \
                           soc_is_exynos5420() || soc_is_exynos5800())
 
-void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1);
-
-struct map_desc;
 extern void __iomem *sysram_ns_base_addr;
 extern void __iomem *sysram_base_addr;
-void exynos_init_io(void);
-void exynos_restart(enum reboot_mode mode, const char *cmd);
+extern void __iomem *pmu_base_addr;
 void exynos_sysram_init(void);
-void exynos_cpuidle_init(void);
-void exynos_cpufreq_init(void);
-void exynos_init_late(void);
 
 void exynos_firmware_init(void);
 
-#ifdef CONFIG_PINCTRL_EXYNOS
 extern u32 exynos_get_eint_wake_mask(void);
-#else
-static inline u32 exynos_get_eint_wake_mask(void) { return 0xffffffff; }
-#endif
 
 #ifdef CONFIG_PM_SLEEP
 extern void __init exynos_pm_init(void);
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 66c9b9614f3c..3164ef2e6b6c 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -19,6 +19,7 @@
 #include <linux/of_platform.h>
 #include <linux/platform_device.h>
 #include <linux/pm_domain.h>
+#include <linux/irqchip.h>
 
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
@@ -29,6 +30,9 @@
 #include "common.h"
 #include "mfc.h"
 #include "regs-pmu.h"
+#include "regs-sys.h"
+
+void __iomem *pmu_base_addr;
 
 static struct map_desc exynos4_iodesc[] __initdata = {
         {
@@ -143,7 +147,7 @@ static struct map_desc exynos5_iodesc[] __initdata = {
         },
 };
 
-void exynos_restart(enum reboot_mode mode, const char *cmd)
+static void exynos_restart(enum reboot_mode mode, const char *cmd)
 {
         struct device_node *np;
         u32 val = 0x1;
@@ -204,7 +208,7 @@ void __init exynos_sysram_init(void)
         }
 }
 
-void __init exynos_init_late(void)
+static void __init exynos_init_late(void)
 {
         if (of_machine_is_compatible("samsung,exynos5440"))
                 /* to be supported later */
@@ -251,7 +255,7 @@ static void __init exynos_map_io(void)
                 iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 }
 
-void __init exynos_init_io(void)
+static void __init exynos_init_io(void)
 {
         debug_ll_io_init();
 
@@ -263,6 +267,39 @@ void __init exynos_init_io(void)
         exynos_map_io();
 }
 
+static const struct of_device_id exynos_dt_pmu_match[] = {
+        { .compatible = "samsung,exynos3250-pmu" },
+        { .compatible = "samsung,exynos4210-pmu" },
+        { .compatible = "samsung,exynos4212-pmu" },
+        { .compatible = "samsung,exynos4412-pmu" },
+        { .compatible = "samsung,exynos5250-pmu" },
+        { .compatible = "samsung,exynos5420-pmu" },
+        { /*sentinel*/ },
+};
+
+static void exynos_map_pmu(void)
+{
+        struct device_node *np;
+
+        np = of_find_matching_node(NULL, exynos_dt_pmu_match);
+        if (np)
+                pmu_base_addr = of_iomap(np, 0);
+
+        if (!pmu_base_addr)
+                panic("failed to find exynos pmu register\n");
+}
+
+static void __init exynos_init_irq(void)
+{
+        irqchip_init();
+        /*
+         * Since platsmp.c needs pmu base address by the time
+         * DT is not unflatten so we can't use DT APIs before
+         * init_irq
+         */
+        exynos_map_pmu();
+}
+
 static void __init exynos_dt_machine_init(void)
 {
         struct device_node *i2c_np;
@@ -352,6 +389,7 @@ DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
         .smp            = smp_ops(exynos_smp_ops),
         .map_io         = exynos_init_io,
         .init_early     = exynos_firmware_init,
+        .init_irq       = exynos_init_irq,
         .init_machine   = exynos_dt_machine_init,
         .init_late      = exynos_init_late,
         .dt_compat      = exynos_dt_compat,
diff --git a/arch/arm/mach-exynos/headsmp.S b/arch/arm/mach-exynos/headsmp.S
index cdd9d91e9933..b54f9701e421 100644
--- a/arch/arm/mach-exynos/headsmp.S
+++ b/arch/arm/mach-exynos/headsmp.S
@@ -1,5 +1,4 @@
 /*
- *  linux/arch/arm/mach-exynos4/headsmp.S
  *
  *  Cloned from linux/arch/arm/mach-realview/headsmp.S
  *
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 920a4baa53cd..4d86961a7957 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -1,5 +1,4 @@
-/* linux arch/arm/mach-exynos4/hotplug.c
- *
+/*
  *  Cloned from linux/arch/arm/mach-realview/hotplug.c
  *
  *  Copyright (C) 2002 ARM Ltd.
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 548269a60634..963002fb15c3 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -1,5 +1,4 @@
-/* linux/arch/arm/mach-exynos/include/mach/map.h
- *
+/*
  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com/
  *
diff --git a/arch/arm/mach-exynos/include/mach/memory.h b/arch/arm/mach-exynos/include/mach/memory.h
index 2a4cdb7cb326..e19df1f18c0d 100644
--- a/arch/arm/mach-exynos/include/mach/memory.h
+++ b/arch/arm/mach-exynos/include/mach/memory.h
@@ -1,5 +1,4 @@
-/* linux/arch/arm/mach-exynos4/include/mach/memory.h
- *
+/*
  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
  *
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 70d1e65a51d8..e5a8d764f24c 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/mach-exynos4/platsmp.c
- *
+ /*
  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
  *
@@ -32,6 +31,72 @@
 
 extern void exynos4_secondary_startup(void);
 
+/**
+ * exynos_core_power_down : power down the specified cpu
+ * @cpu : the cpu to power down
+ *
+ * Power down the specified cpu. The sequence must be finished by a
+ * call to cpu_do_idle()
+ *
+ */
+void exynos_cpu_power_down(int cpu)
+{
+        __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+}
+
+/**
+ * exynos_cpu_power_up : power up the specified cpu
+ * @cpu : the cpu to power up
+ *
+ * Power up the specified cpu
+ */
+void exynos_cpu_power_up(int cpu)
+{
+        __raw_writel(S5P_CORE_LOCAL_PWR_EN,
+                     EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+}
+
+/**
+ * exynos_cpu_power_state : returns the power state of the cpu
+ * @cpu : the cpu to retrieve the power state from
+ *
+ */
+int exynos_cpu_power_state(int cpu)
+{
+        return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
+                        S5P_CORE_LOCAL_PWR_EN);
+}
+
+/**
+ * exynos_cluster_power_down : power down the specified cluster
+ * @cluster : the cluster to power down
+ */
+void exynos_cluster_power_down(int cluster)
+{
+        __raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
+}
+
+/**
+ * exynos_cluster_power_up : power up the specified cluster
+ * @cluster : the cluster to power up
+ */
+void exynos_cluster_power_up(int cluster)
+{
+        __raw_writel(S5P_CORE_LOCAL_PWR_EN,
+                     EXYNOS_COMMON_CONFIGURATION(cluster));
+}
+
+/**
+ * exynos_cluster_power_state : returns the power state of the cluster
+ * @cluster : the cluster to retrieve the power state from
+ *
+ */
+int exynos_cluster_power_state(int cluster)
+{
+        return (__raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
+                        S5P_CORE_LOCAL_PWR_EN);
+}
+
 static inline void __iomem *cpu_boot_reg_base(void)
 {
         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 67d383de614f..6ab68a068e93 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -35,6 +35,7 @@
 
 #include "common.h"
 #include "regs-pmu.h"
+#include "regs-sys.h"
 
 /**
  * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
@@ -100,72 +101,6 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
         return -ENOENT;
 }
 
-/**
- * exynos_core_power_down : power down the specified cpu
- * @cpu : the cpu to power down
- *
- * Power down the specified cpu. The sequence must be finished by a
- * call to cpu_do_idle()
- *
- */
-void exynos_cpu_power_down(int cpu)
-{
-        __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
-}
-
-/**
- * exynos_cpu_power_up : power up the specified cpu
- * @cpu : the cpu to power up
- *
- * Power up the specified cpu
- */
-void exynos_cpu_power_up(int cpu)
-{
-        __raw_writel(S5P_CORE_LOCAL_PWR_EN,
-                     EXYNOS_ARM_CORE_CONFIGURATION(cpu));
-}
-
-/**
- * exynos_cpu_power_state : returns the power state of the cpu
- * @cpu : the cpu to retrieve the power state from
- *
- */
-int exynos_cpu_power_state(int cpu)
-{
-        return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
-                        S5P_CORE_LOCAL_PWR_EN);
-}
-
-/**
- * exynos_cluster_power_down : power down the specified cluster
- * @cluster : the cluster to power down
- */
-void exynos_cluster_power_down(int cluster)
-{
-        __raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
-}
-
-/**
- * exynos_cluster_power_up : power up the specified cluster
- * @cluster : the cluster to power up
- */
-void exynos_cluster_power_up(int cluster)
-{
-        __raw_writel(S5P_CORE_LOCAL_PWR_EN,
-                     EXYNOS_COMMON_CONFIGURATION(cluster));
-}
-
-/**
- * exynos_cluster_power_state : returns the power state of the cluster
- * @cluster : the cluster to retrieve the power state from
- *
- */
-int exynos_cluster_power_state(int cluster)
-{
-        return (__raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
-                        S5P_CORE_LOCAL_PWR_EN);
-}
-
 #define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
                         S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
                         (sysram_base_addr + 0x24) : S5P_INFORM0))
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
index 797cb134bfff..fd76e1b5a471 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -23,8 +23,7 @@
 #include <linux/of_platform.h>
 #include <linux/sched.h>
 
-#include "regs-pmu.h"
-
+#define INT_LOCAL_PWR_EN        0x7
 #define MAX_CLK_PER_DOMAIN      4
 
 /*
@@ -63,13 +62,13 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
                 }
         }
 
-        pwr = power_on ? S5P_INT_LOCAL_PWR_EN : 0;
+        pwr = power_on ? INT_LOCAL_PWR_EN : 0;
         __raw_writel(pwr, base);
 
         /* Wait max 1ms */
         timeout = 10;
 
-        while ((__raw_readl(base + 0x4) & S5P_INT_LOCAL_PWR_EN) != pwr) {
+        while ((__raw_readl(base + 0x4) & INT_LOCAL_PWR_EN) != pwr) {
                 if (!timeout) {
                         op = (power_on) ? "enable" : "disable";
                         pr_err("Power domain %s %s failed\n", domain->name, op);
@@ -231,7 +230,7 @@ static __init int exynos4_pm_init_power_domain(void)
 no_clk:
                 platform_set_drvdata(pdev, pd);
 
-                on = __raw_readl(pd->base + 0x4) & S5P_INT_LOCAL_PWR_EN;
+                on = __raw_readl(pd->base + 0x4) & INT_LOCAL_PWR_EN;
 
                 pm_genpd_init(&pd->pd, NULL, !on);
         }
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index fb0deda3b3a4..dcfcb44c3c55 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -11,7 +11,6 @@
 
 #include <linux/io.h>
 #include <linux/kernel.h>
-#include <linux/bug.h>
 
 #include "common.h"
 #include "regs-pmu.h"
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 1d13b08708f0..1993e6bd5388 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -15,7 +15,6 @@
 #include <mach/map.h>
 
 #define S5P_PMUREG(x)                           (S5P_VA_PMU + (x))
-#define S5P_SYSREG(x)                           (S3C_VA_SYS + (x))
 
 #define S5P_CENTRAL_SEQ_CONFIGURATION           S5P_PMUREG(0x0200)
 
@@ -127,7 +126,6 @@
 #define S5P_PAD_RET_EBIB_OPTION                 S5P_PMUREG(0x31A8)
 
 #define S5P_CORE_LOCAL_PWR_EN                   0x3
-#define S5P_INT_LOCAL_PWR_EN                    0x7
 
 /* Only for EXYNOS4210 */
 #define S5P_CMU_CLKSTOP_LCD1_LOWPWR     S5P_PMUREG(0x1154)
@@ -188,8 +186,6 @@
 
 /* For EXYNOS5 */
 
-#define EXYNOS5_SYS_I2C_CFG                                     S5P_SYSREG(0x0234)
-
 #define EXYNOS5_AUTO_WDTRESET_DISABLE                           S5P_PMUREG(0x0408)
 #define EXYNOS5_MASK_WDTRESET_REQUEST                           S5P_PMUREG(0x040C)
 
diff --git a/arch/arm/mach-exynos/regs-sys.h b/arch/arm/mach-exynos/regs-sys.h
new file mode 100644
index 000000000000..84332b0dd7a6
--- /dev/null
+++ b/arch/arm/mach-exynos/regs-sys.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * EXYNOS - system register definition
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_SYS_H
+#define __ASM_ARCH_REGS_SYS_H __FILE__
+
+#include <mach/map.h>
+
+#define S5P_SYSREG(x)                          (S3C_VA_SYS + (x))
+
+/* For EXYNOS5 */
+#define EXYNOS5_SYS_I2C_CFG                    S5P_SYSREG(0x0234)
+
+#endif /* __ASM_ARCH_REGS_SYS_H */
diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig
index 64f8e2564a37..c455e974bbfe 100644
--- a/arch/arm/mach-integrator/Kconfig
+++ b/arch/arm/mach-integrator/Kconfig
@@ -17,7 +17,6 @@ config ARCH_INTEGRATOR_CP
         bool "Support Integrator/CP platform"
         select ARCH_CINTEGRATOR
         select ARM_TIMER_SP804
-        select PLAT_VERSATILE_CLCD
         select SERIAL_AMBA_PL011 if TTY
         select SERIAL_AMBA_PL011_CONSOLE if TTY
         select SOC_BUS
diff --git a/arch/arm/mach-integrator/include/mach/memory.h b/arch/arm/mach-integrator/include/mach/memory.h
deleted file mode 100644
index 7268cb50ded0..000000000000
--- a/arch/arm/mach-integrator/include/mach/memory.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- *  arch/arm/mach-integrator/include/mach/memory.h
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-#define BUS_OFFSET      UL(0x80000000)
-#define __virt_to_bus(x)        ((x) - PAGE_OFFSET + BUS_OFFSET)
-#define __bus_to_virt(x)        ((x) - BUS_OFFSET + PAGE_OFFSET)
-#define __pfn_to_bus(x)         (__pfn_to_phys(x) + (BUS_OFFSET - PHYS_OFFSET))
-#define __bus_to_pfn(x)         __phys_to_pfn((x) - (BUS_OFFSET - PHYS_OFFSET))
-
-#endif
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 0e57f8f820a5..e39097068cf9 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -18,6 +18,7 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/kmi.h>
 #include <linux/amba/clcd.h>
+#include <linux/platform_data/video-clcd-versatile.h>
 #include <linux/amba/mmci.h>
 #include <linux/io.h>
 #include <linux/irqchip/versatile-fpga.h>
@@ -36,8 +37,6 @@
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 
-#include <plat/clcd.h>
-
 #include "hardware.h"
 #include "cm.h"
 #include "common.h"
diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
index fbd7ee8e4897..8c78f2b16452 100644
--- a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
+++ b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
@@ -23,7 +23,6 @@
 #define SM_nCS0_nCS0            MFP_CFG(SM_nCS0, AF0)
 #define SM_ADV_SM_ADV           MFP_CFG(SM_ADV, AF0)
 #define SM_SCLK_SM_SCLK         MFP_CFG(SM_SCLK, AF0)
-#define SM_SCLK_SM_SCLK         MFP_CFG(SM_SCLK, AF0)
 #define SM_BE0_SM_BE0           MFP_CFG(SM_BE0, AF1)
 #define SM_BE1_SM_BE1           MFP_CFG(SM_BE1, AF1)
 
diff --git a/arch/arm/mach-omap1/ocpi.c b/arch/arm/mach-omap1/ocpi.c
index 238170cab5b7..44a3d19eb481 100644
--- a/arch/arm/mach-omap1/ocpi.c
+++ b/arch/arm/mach-omap1/ocpi.c
@@ -55,7 +55,6 @@ static struct clk *ocpi_ck;
 
 /*
  * Enables device access to OMAP buses via the OCPI bridge
- * FIXME: Add locking
  */
 int ocpi_enable(void)
 {
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 67fd26a18441..b2ff6cd7ca9f 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -21,10 +21,7 @@
 
 #include <asm/div64.h>
 
-#include "soc.h"
 #include "clock.h"
-#include "cm-regbits-24xx.h"
-#include "cm-regbits-34xx.h"
 
 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
 #define DPLL_MIN_MULTIPLIER             2
@@ -44,20 +41,12 @@
 #define DPLL_ROUNDING_VAL               ((DPLL_SCALE_BASE / 2) * \
                                          (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
 
-/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
-#define OMAP3430_DPLL_FINT_BAND1_MIN    750000
-#define OMAP3430_DPLL_FINT_BAND1_MAX    2100000
-#define OMAP3430_DPLL_FINT_BAND2_MIN    7500000
-#define OMAP3430_DPLL_FINT_BAND2_MAX    21000000
-
 /*
  * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
  * From device data manual section 4.3 "DPLL and DLL Specifications".
  */
 #define OMAP3PLUS_DPLL_FINT_JTYPE_MIN   500000
 #define OMAP3PLUS_DPLL_FINT_JTYPE_MAX   2500000
-#define OMAP3PLUS_DPLL_FINT_MIN         32000
-#define OMAP3PLUS_DPLL_FINT_MAX         52000000
 
 /* _dpll_test_fint() return codes */
 #define DPLL_FINT_UNDERFLOW             -1
@@ -87,33 +76,31 @@ static int _dpll_test_fint(struct clk_hw_omap *clk, unsigned int n)
         /* DPLL divider must result in a valid jitter correction val */
         fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n;
 
-        if (cpu_is_omap24xx()) {
-                /* Should not be called for OMAP2, so warn if it is called */
-                WARN(1, "No fint limits available for OMAP2!\n");
-                return DPLL_FINT_INVALID;
-        } else if (cpu_is_omap3430()) {
-                fint_min = OMAP3430_DPLL_FINT_BAND1_MIN;
-                fint_max = OMAP3430_DPLL_FINT_BAND2_MAX;
-        } else if (dd->flags & DPLL_J_TYPE) {
+        if (dd->flags & DPLL_J_TYPE) {
                 fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN;
                 fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX;
         } else {
-                fint_min = OMAP3PLUS_DPLL_FINT_MIN;
-                fint_max = OMAP3PLUS_DPLL_FINT_MAX;
+                fint_min = ti_clk_features.fint_min;
+                fint_max = ti_clk_features.fint_max;
         }
 
-        if (fint < fint_min) {
+        if (!fint_min || !fint_max) {
+                WARN(1, "No fint limits available!\n");
+                return DPLL_FINT_INVALID;
+        }
+
+        if (fint < ti_clk_features.fint_min) {
                 pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n",
                          n);
                 dd->max_divider = n;
                 ret = DPLL_FINT_UNDERFLOW;
-        } else if (fint > fint_max) {
+        } else if (fint > ti_clk_features.fint_max) {
                 pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n",
                          n);
                 dd->min_divider = n;
                 ret = DPLL_FINT_INVALID;
-        } else if (cpu_is_omap3430() && fint > OMAP3430_DPLL_FINT_BAND1_MAX &&
-                   fint < OMAP3430_DPLL_FINT_BAND2_MIN) {
+        } else if (fint > ti_clk_features.fint_band1_max &&
+                   fint < ti_clk_features.fint_band2_min) {
                 pr_debug("rejecting n=%d due to Fint failure\n", n);
                 ret = DPLL_FINT_INVALID;
         }
@@ -185,6 +172,34 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
         return r;
 }
 
+/**
+ * _omap2_dpll_is_in_bypass - check if DPLL is in bypass mode or not
+ * @v: bitfield value of the DPLL enable
+ *
+ * Checks given DPLL enable bitfield to see whether the DPLL is in bypass
+ * mode or not. Returns 1 if the DPLL is in bypass, 0 otherwise.
+ */
+static int _omap2_dpll_is_in_bypass(u32 v)
+{
+        u8 mask, val;
+
+        mask = ti_clk_features.dpll_bypass_vals;
+
+        /*
+         * Each set bit in the mask corresponds to a bypass value equal
+         * to the bitshift. Go through each set-bit in the mask and
+         * compare against the given register value.
+         */
+        while (mask) {
+                val = __ffs(mask);
+                mask ^= (1 << val);
+                if (v == val)
+                        return 1;
+        }
+
+        return 0;
+}
+
 /* Public functions */
 u8 omap2_init_dpll_parent(struct clk_hw *hw)
 {
@@ -201,20 +216,9 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw)
         v >>= __ffs(dd->enable_mask);
 
         /* Reparent the struct clk in case the dpll is in bypass */
-        if (cpu_is_omap24xx()) {
-                if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
-                    v == OMAP2XXX_EN_DPLL_FRBYPASS)
-                        return 1;
-        } else if (cpu_is_omap34xx()) {
-                if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
-                    v == OMAP3XXX_EN_DPLL_FRBYPASS)
-                        return 1;
-        } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) {
-                if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
-                    v == OMAP4XXX_EN_DPLL_FRBYPASS ||
-                    v == OMAP4XXX_EN_DPLL_MNBYPASS)
-                        return 1;
-        }
+        if (_omap2_dpll_is_in_bypass(v))
+                return 1;
+
         return 0;
 }
 
@@ -247,20 +251,8 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
         v &= dd->enable_mask;
         v >>= __ffs(dd->enable_mask);
 
-        if (cpu_is_omap24xx()) {
-                if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
-                    v == OMAP2XXX_EN_DPLL_FRBYPASS)
-                        return __clk_get_rate(dd->clk_bypass);
-        } else if (cpu_is_omap34xx()) {
-                if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
-                    v == OMAP3XXX_EN_DPLL_FRBYPASS)
-                        return __clk_get_rate(dd->clk_bypass);
-        } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) {
-                if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
-                    v == OMAP4XXX_EN_DPLL_FRBYPASS ||
-                    v == OMAP4XXX_EN_DPLL_MNBYPASS)
-                        return __clk_get_rate(dd->clk_bypass);
-        }
+        if (_omap2_dpll_is_in_bypass(v))
+                return __clk_get_rate(dd->clk_bypass);
 
         v = omap2_clk_readl(clk, dd->mult_div1_reg);
         dpll_mult = v & dd->mult_mask;
diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c
index 333f0a666171..55eb579aeae1 100644
--- a/arch/arm/mach-omap2/clkt_iclk.c
+++ b/arch/arm/mach-omap2/clkt_iclk.c
@@ -14,11 +14,11 @@
 #include <linux/clk-provider.h>
 #include <linux/io.h>
 
-
 #include "clock.h"
-#include "clock2xxx.h"
-#include "cm2xxx_3xxx.h"
-#include "cm-regbits-24xx.h"
+
+/* Register offsets */
+#define CM_AUTOIDLE                     0x30
+#define CM_ICLKEN                       0x10
 
 /* Private functions */
 
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 591581a66532..5a0cac93d9ec 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -47,6 +47,24 @@
 u16 cpu_mask;
 
 /*
+ * Clock features setup. Used instead of CPU type checks.
+ */
+struct ti_clk_features ti_clk_features;
+
+/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
+#define OMAP3430_DPLL_FINT_BAND1_MIN    750000
+#define OMAP3430_DPLL_FINT_BAND1_MAX    2100000
+#define OMAP3430_DPLL_FINT_BAND2_MIN    7500000
+#define OMAP3430_DPLL_FINT_BAND2_MAX    21000000
+
+/*
+ * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
+ * From device data manual section 4.3 "DPLL and DLL Specifications".
+ */
+#define OMAP3PLUS_DPLL_FINT_MIN         32000
+#define OMAP3PLUS_DPLL_FINT_MAX         52000000
+
+/*
  * clkdm_control: if true, then when a clock is enabled in the
  * hardware, its clockdomain will first be enabled; and when a clock
  * is disabled in the hardware, its clockdomain will be disabled
@@ -287,13 +305,7 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
          * 34xx reverses this, just to keep us on our toes
          * AM35xx uses both, depending on the module.
          */
-        if (cpu_is_omap24xx())
-                *idlest_val = OMAP24XX_CM_IDLEST_VAL;
-        else if (cpu_is_omap34xx())
-                *idlest_val = OMAP34XX_CM_IDLEST_VAL;
-        else
-                BUG();
-
+        *idlest_val = ti_clk_features.cm_idlest_val;
 }
 
 /**
@@ -731,3 +743,53 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
                 (clk_get_rate(core_ck) / 1000000),
                 (clk_get_rate(mpu_ck) / 1000000));
 }
+
+/**
+ * ti_clk_init_features - init clock features struct for the SoC
+ *
+ * Initializes the clock features struct based on the SoC type.
+ */
+void __init ti_clk_init_features(void)
+{
+        /* Fint setup for DPLLs */
+        if (cpu_is_omap3430()) {
+                ti_clk_features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN;
+                ti_clk_features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX;
+                ti_clk_features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX;
+                ti_clk_features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN;
+        } else {
+                ti_clk_features.fint_min = OMAP3PLUS_DPLL_FINT_MIN;
+                ti_clk_features.fint_max = OMAP3PLUS_DPLL_FINT_MAX;
+        }
+
+        /* Bypass value setup for DPLLs */
+        if (cpu_is_omap24xx()) {
+                ti_clk_features.dpll_bypass_vals |=
+                        (1 << OMAP2XXX_EN_DPLL_LPBYPASS) |
+                        (1 << OMAP2XXX_EN_DPLL_FRBYPASS);
+        } else if (cpu_is_omap34xx()) {
+                ti_clk_features.dpll_bypass_vals |=
+                        (1 << OMAP3XXX_EN_DPLL_LPBYPASS) |
+                        (1 << OMAP3XXX_EN_DPLL_FRBYPASS);
+        } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() ||
+                   soc_is_omap54xx() || soc_is_dra7xx()) {
+                ti_clk_features.dpll_bypass_vals |=
+                        (1 << OMAP4XXX_EN_DPLL_LPBYPASS) |
+                        (1 << OMAP4XXX_EN_DPLL_FRBYPASS) |
+                        (1 << OMAP4XXX_EN_DPLL_MNBYPASS);
+        }
+
+        /* Jitter correction only available on OMAP343X */
+        if (cpu_is_omap343x())
+                ti_clk_features.flags |= TI_CLK_DPLL_HAS_FREQSEL;
+
+        /* Idlest value for interface clocks.
+         * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
+         * 34xx reverses this, just to keep us on our toes
+         * AM35xx uses both, depending on the module.
+         */
+        if (cpu_is_omap24xx())
+                ti_clk_features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL;
+        else if (cpu_is_omap34xx())
+                ti_clk_features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL;
+}
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 12f54d428d7c..0f100dc4e97f 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -101,31 +101,6 @@ struct clockdomain;
         };                                                      \
         DEFINE_STRUCT_CLK(_name, _parent_names, _ops);
 
-#define DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name,          \
-                                _parent_ptr, _flags,            \
-                                _clksel_reg, _clksel_mask)      \
-        static const struct clksel _name##_div[] = {            \
-                {                                               \
-                        .parent = _parent_ptr,                  \
-                        .rates = div31_1to31_rates              \
-                },                                              \
-                { .parent = NULL },                             \
-        };                                                      \
-        static struct clk _name;                                \
-        static const char *_name##_parent_names[] = {           \
-                _parent_name,                                   \
-        };                                                      \
-        static struct clk_hw_omap _name##_hw = {                \
-                .hw = {                                         \
-                        .clk = &_name,                          \
-                },                                              \
-                .clksel         = _name##_div,                  \
-                .clksel_reg     = _clksel_reg,                  \
-                .clksel_mask    = _clksel_mask,                 \
-                .ops            = &clkhwops_omap4_dpllmx,       \
-        };                                                      \
-        DEFINE_STRUCT_CLK(_name, _name##_parent_names, omap_hsdivider_ops);
-
 /* struct clksel_rate.flags possibilities */
 #define RATE_IN_242X            (1 << 0)
 #define RATE_IN_243X            (1 << 1)
@@ -248,6 +223,23 @@ void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg);
 
 extern u16 cpu_mask;
 
+/*
+ * Clock features setup. Used instead of CPU type checks.
+ */
+struct ti_clk_features {
+        u32 flags;
+        long fint_min;
+        long fint_max;
+        long fint_band1_max;
+        long fint_band2_min;
+        u8 dpll_bypass_vals;
+        u8 cm_idlest_val;
+};
+
+#define TI_CLK_DPLL_HAS_FREQSEL         (1 << 0)
+
+extern struct ti_clk_features ti_clk_features;
+
 extern const struct clkops clkops_omap2_dflt_wait;
 extern const struct clkops clkops_dummy;
 extern const struct clkops clkops_omap2_dflt;
@@ -286,4 +278,6 @@ extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
 extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
 
 extern void omap_clocks_register(struct omap_clk *oclks, int cnt);
+
+void __init ti_clk_init_features(void);
 #endif
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 751f3549bf6f..f4796c002070 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -44,8 +44,7 @@ struct omap3_scratchpad {
 };
 
 struct omap3_scratchpad_prcm_block {
-        u32 prm_clksrc_ctrl;
-        u32 prm_clksel;
+        u32 prm_contents[2];
         u32 cm_contents[11];
         u32 prcm_block_size;
 };
@@ -282,13 +281,9 @@ void omap3_clear_scratchpad_contents(void)
         void __iomem *v_addr;
         u32 offset = 0;
         v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
-        if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
-            OMAP3430_GLOBAL_COLD_RST_MASK) {
+        if (omap3xxx_prm_clear_global_cold_reset()) {
                 for ( ; offset <= max_offset; offset += 0x4)
                         writel_relaxed(0x0, (v_addr + offset));
-                omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
-                                           OMAP3430_GR_MOD,
-                                           OMAP3_PRM_RSTST_OFFSET);
         }
 }
 
@@ -331,13 +326,7 @@ void omap3_save_scratchpad_contents(void)
         scratchpad_contents.sdrc_block_offset = 0x64;
 
         /* Populate the PRCM block contents */
-        prcm_block_contents.prm_clksrc_ctrl =
-                omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
-                                       OMAP3_PRM_CLKSRC_CTRL_OFFSET);
-        prcm_block_contents.prm_clksel =
-                omap2_prm_read_mod_reg(OMAP3430_CCR_MOD,
-                                       OMAP3_PRM_CLKSEL_OFFSET);
-
+        omap3_prm_save_scratchpad_contents(prcm_block_contents.prm_contents);
         omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents);
 
         prcm_block_contents.prcm_block_size = 0x0;
@@ -575,9 +564,50 @@ int omap3_ctrl_save_padconf(void)
  * Sets the bootmode for IVA2 to idle. This is needed by the PM code to
  * force disable IVA2 so that it does not prevent any low-power states.
  */
-void omap3_ctrl_set_iva_bootmode_idle(void)
+static void __init omap3_ctrl_set_iva_bootmode_idle(void)
 {
         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 }
+
+/**
+ * omap3_ctrl_setup_d2d_padconf - setup stacked modem pads for idle
+ *
+ * Sets up the pads controlling the stacked modem in such way that the
+ * device can enter idle.
+ */
+static void __init omap3_ctrl_setup_d2d_padconf(void)
+{
+        u16 mask, padconf;
+
+        /*
+         * In a stand alone OMAP3430 where there is not a stacked
+         * modem for the D2D Idle Ack and D2D MStandby must be pulled
+         * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
+         * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up.
+         */
+        mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
+        padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
+        padconf |= mask;
+        omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
+
+        padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
+        padconf |= mask;
+        omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
+}
+
+/**
+ * omap3_ctrl_init - does static initializations for control module
+ *
+ * Initializes system control module. This sets up the sysconfig autoidle,
+ * and sets up modem and iva2 so that they can be idled properly.
+ */
+void __init omap3_ctrl_init(void)
+{
+        omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
+
+        omap3_ctrl_set_iva_bootmode_idle();
+
+        omap3_ctrl_setup_d2d_padconf();
+}
 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index da054801b114..a3c013345c45 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -16,11 +16,6 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H
 #define __ARCH_ARM_MACH_OMAP2_CONTROL_H
 
-#include "ctrl_module_core_44xx.h"
-#include "ctrl_module_wkup_44xx.h"
-#include "ctrl_module_pad_core_44xx.h"
-#include "ctrl_module_pad_wkup_44xx.h"
-
 #include "am33xx.h"
 
 #ifndef __ASSEMBLY__
@@ -254,6 +249,39 @@
 /* TI81XX CONTROL_DEVCONF register offsets */
 #define TI81XX_CONTROL_DEVICE_ID        (TI81XX_CONTROL_DEVCONF + 0x000)
 
+/* OMAP4 CONTROL MODULE */
+#define OMAP4_CTRL_MODULE_PAD_WKUP                      0x4a31e000
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2        0x0604
+#define OMAP4_CTRL_MODULE_CORE_STATUS                   0x02c4
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1       0x0218
+#define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR             0x0304
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY       0x0618
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX    0x0608
+
+/* OMAP4 CONTROL_DSIPHY */
+#define OMAP4_DSI2_LANEENABLE_SHIFT                     29
+#define OMAP4_DSI2_LANEENABLE_MASK                      (0x7 << 29)
+#define OMAP4_DSI1_LANEENABLE_SHIFT                     24
+#define OMAP4_DSI1_LANEENABLE_MASK                      (0x1f << 24)
+#define OMAP4_DSI1_PIPD_SHIFT                           19
+#define OMAP4_DSI1_PIPD_MASK                            (0x1f << 19)
+#define OMAP4_DSI2_PIPD_SHIFT                           14
+#define OMAP4_DSI2_PIPD_MASK                            (0x1f << 14)
+
+/* OMAP4 CONTROL_CAMERA_RX */
+#define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT           24
+#define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK            (0x1f << 24)
+#define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT           29
+#define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK            (0x3 << 29)
+#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT            21
+#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK             (1 << 21)
+#define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT              19
+#define OMAP4_CAMERARX_CSI22_CAMMODE_MASK               (0x3 << 19)
+#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT            18
+#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK             (1 << 18)
+#define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT              16
+#define OMAP4_CAMERARX_CSI21_CAMMODE_MASK               (0x3 << 16)
+
 /* OMAP54XX CONTROL STATUS register */
 #define OMAP5XXX_CONTROL_STATUS                0x134
 #define OMAP5_DEVICETYPE_MASK          (0x7 << 6)
@@ -427,7 +455,7 @@ extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr);
 extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
 extern void omap3630_ctrl_disable_rta(void);
 extern int omap3_ctrl_save_padconf(void);
-extern void omap3_ctrl_set_iva_bootmode_idle(void);
+void omap3_ctrl_init(void);
 extern void omap2_set_globals_control(void __iomem *ctrl,
                                       void __iomem *ctrl_pad);
 #else
diff --git a/arch/arm/mach-omap2/ctrl_module_core_44xx.h b/arch/arm/mach-omap2/ctrl_module_core_44xx.h
deleted file mode 100644
index 01970824e0e5..000000000000
--- a/arch/arm/mach-omap2/ctrl_module_core_44xx.h
+++ /dev/null
@@ -1,392 +0,0 @@
-/*
- * OMAP44xx CTRL_MODULE_CORE registers and bitfields
- *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
- *
- * Benoit Cousson (b-cousson@ti.com)
- * Santosh Shilimkar (santosh.shilimkar@ti.com)
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap@vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
-#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
-
-
-/* Base address */
-#define OMAP4_CTRL_MODULE_CORE                                  0x4a002000
-
-/* Registers offset */
-#define OMAP4_CTRL_MODULE_CORE_IP_REVISION                      0x0000
-#define OMAP4_CTRL_MODULE_CORE_IP_HWINFO                        0x0004
-#define OMAP4_CTRL_MODULE_CORE_IP_SYSCONFIG                     0x0010
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_0                0x0200
-#define OMAP4_CTRL_MODULE_CORE_ID_CODE                          0x0204
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_1                0x0208
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_2                0x020c
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_3                0x0210
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_0               0x0214
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1               0x0218
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_USB_CONF                0x021c
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_VDD_WKUP            0x0228
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_BGAP                0x0260
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_0              0x0264
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1              0x0268
-#define OMAP4_CTRL_MODULE_CORE_STATUS                           0x02c4
-#define OMAP4_CTRL_MODULE_CORE_DEV_CONF                         0x0300
-#define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR                     0x0304
-#define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL          0x0314
-#define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL          0x0318
-#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL         0x0320
-#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_MPU_VOLTAGE_CTRL         0x0324
-#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_CORE_VOLTAGE_CTRL        0x0328
-#define OMAP4_CTRL_MODULE_CORE_TEMP_SENSOR                      0x032c
-#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_0                0x0330
-#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_1                0x0334
-#define OMAP4_CTRL_MODULE_CORE_USBOTGHS_CONTROL                 0x033c
-#define OMAP4_CTRL_MODULE_CORE_DSS_CONTROL                      0x0340
-#define OMAP4_CTRL_MODULE_CORE_HWOBS_CONTROL                    0x0350
-#define OMAP4_CTRL_MODULE_CORE_DEBOBS_FINAL_MUX_SEL             0x0400
-#define OMAP4_CTRL_MODULE_CORE_DEBOBS_MMR_MPU                   0x0408
-#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL0               0x042c
-#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL1               0x0430
-#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL2               0x0434
-#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL3               0x0438
-#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL0                    0x0440
-#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL1                    0x0444
-#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL2                    0x0448
-#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_FREQLOCK_SEL           0x044c
-#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_TINITZ_SEL             0x0450
-#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_PHASELOCK_SEL          0x0454
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_0             0x0480
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_1             0x0484
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_2             0x0488
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_3             0x048c
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_4             0x0490
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_5             0x0494
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_6             0x0498
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_7             0x049c
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_8             0x04a0
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_9             0x04a4
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_10            0x04a8
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_11            0x04ac
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_12            0x04b0
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_13            0x04b4
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_14            0x04b8
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_15            0x04bc
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_16            0x04c0
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_17            0x04c4
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_18            0x04c8
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_19            0x04cc
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_20            0x04d0
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_21            0x04d4
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_22            0x04d8
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_23            0x04dc
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_24            0x04e0
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_25            0x04e4
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_26            0x04e8
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_27            0x04ec
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_28            0x04f0
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_29            0x04f4
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_30            0x04f8
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_31            0x04fc
-
-/* Registers shifts and masks */
-
-/* IP_REVISION */
-#define OMAP4_IP_REV_SCHEME_SHIFT                       30
-#define OMAP4_IP_REV_SCHEME_MASK                        (0x3 << 30)
-#define OMAP4_IP_REV_FUNC_SHIFT                         16
-#define OMAP4_IP_REV_FUNC_MASK                          (0xfff << 16)
-#define OMAP4_IP_REV_RTL_SHIFT                          11
-#define OMAP4_IP_REV_RTL_MASK                           (0x1f << 11)
-#define OMAP4_IP_REV_MAJOR_SHIFT                        8
-#define OMAP4_IP_REV_MAJOR_MASK                         (0x7 << 8)
-#define OMAP4_IP_REV_CUSTOM_SHIFT                       6
-#define OMAP4_IP_REV_CUSTOM_MASK                        (0x3 << 6)
-#define OMAP4_IP_REV_MINOR_SHIFT                        0
-#define OMAP4_IP_REV_MINOR_MASK                         (0x3f << 0)
-
-/* IP_HWINFO */
-#define OMAP4_IP_HWINFO_SHIFT                           0
-#define OMAP4_IP_HWINFO_MASK                            (0xffffffff << 0)
-
-/* IP_SYSCONFIG */
-#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT               2
-#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK                (0x3 << 2)
-
-/* STD_FUSE_DIE_ID_0 */
-#define OMAP4_STD_FUSE_DIE_ID_0_SHIFT                   0
-#define OMAP4_STD_FUSE_DIE_ID_0_MASK                    (0xffffffff << 0)
-
-/* ID_CODE */
-#define OMAP4_STD_FUSE_IDCODE_SHIFT                     0
-#define OMAP4_STD_FUSE_IDCODE_MASK                      (0xffffffff << 0)
-
-/* STD_FUSE_DIE_ID_1 */
-#define OMAP4_STD_FUSE_DIE_ID_1_SHIFT                   0
-#define OMAP4_STD_FUSE_DIE_ID_1_MASK                    (0xffffffff << 0)
-
-/* STD_FUSE_DIE_ID_2 */
-#define OMAP4_STD_FUSE_DIE_ID_2_SHIFT                   0
-#define OMAP4_STD_FUSE_DIE_ID_2_MASK                    (0xffffffff << 0)
-
-/* STD_FUSE_DIE_ID_3 */
-#define OMAP4_STD_FUSE_DIE_ID_3_SHIFT                   0
-#define OMAP4_STD_FUSE_DIE_ID_3_MASK                    (0xffffffff << 0)
-
-/* STD_FUSE_PROD_ID_0 */
-#define OMAP4_STD_FUSE_PROD_ID_0_SHIFT                  0
-#define OMAP4_STD_FUSE_PROD_ID_0_MASK                   (0xffffffff << 0)
-
-/* STD_FUSE_PROD_ID_1 */
-#define OMAP4_STD_FUSE_PROD_ID_1_SHIFT                  0
-#define OMAP4_STD_FUSE_PROD_ID_1_MASK                   (0xffffffff << 0)
-
-/* STD_FUSE_USB_CONF */
-#define OMAP4_USB_PROD_ID_SHIFT                         16
-#define OMAP4_USB_PROD_ID_MASK                          (0xffff << 16)
-#define OMAP4_USB_VENDOR_ID_SHIFT                       0
-#define OMAP4_USB_VENDOR_ID_MASK                        (0xffff << 0)
-
-/* STD_FUSE_OPP_VDD_WKUP */
-#define OMAP4_STD_FUSE_OPP_VDD_WKUP_SHIFT               0
-#define OMAP4_STD_FUSE_OPP_VDD_WKUP_MASK                (0xffffffff << 0)
-
-/* STD_FUSE_OPP_BGAP */
-#define OMAP4_STD_FUSE_OPP_BGAP_SHIFT                   0
-#define OMAP4_STD_FUSE_OPP_BGAP_MASK                    (0xffffffff << 0)
-
-/* STD_FUSE_OPP_DPLL_0 */
-#define OMAP4_STD_FUSE_OPP_DPLL_0_SHIFT                 0
-#define OMAP4_STD_FUSE_OPP_DPLL_0_MASK                  (0xffffffff << 0)
-
-/* STD_FUSE_OPP_DPLL_1 */
-#define OMAP4_STD_FUSE_OPP_DPLL_1_SHIFT                 0
-#define OMAP4_STD_FUSE_OPP_DPLL_1_MASK                  (0xffffffff << 0)
-
-/* STATUS */
-#define OMAP4_ATTILA_CONF_SHIFT                         11
-#define OMAP4_ATTILA_CONF_MASK                          (0x3 << 11)
-#define OMAP4_DEVICE_TYPE_SHIFT                         8
-#define OMAP4_DEVICE_TYPE_MASK                          (0x7 << 8)
-#define OMAP4_SYS_BOOT_SHIFT                            0
-#define OMAP4_SYS_BOOT_MASK                             (0xff << 0)
-
-/* DEV_CONF */
-#define OMAP4_DEV_CONF_SHIFT                            1
-#define OMAP4_DEV_CONF_MASK                             (0x7fffffff << 1)
-#define OMAP4_USBPHY_PD_SHIFT                           0
-#define OMAP4_USBPHY_PD_MASK                            (1 << 0)
-
-/* LDOVBB_IVA_VOLTAGE_CTRL */
-#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_SHIFT              26
-#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_MASK               (1 << 26)
-#define OMAP4_LDOVBBIVA_RBB_VSET_IN_SHIFT               21
-#define OMAP4_LDOVBBIVA_RBB_VSET_IN_MASK                (0x1f << 21)
-#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_SHIFT              16
-#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_MASK               (0x1f << 16)
-#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_SHIFT              10
-#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_MASK               (1 << 10)
-#define OMAP4_LDOVBBIVA_FBB_VSET_IN_SHIFT               5
-#define OMAP4_LDOVBBIVA_FBB_VSET_IN_MASK                (0x1f << 5)
-#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_SHIFT              0
-#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_MASK               (0x1f << 0)
-
-/* LDOVBB_MPU_VOLTAGE_CTRL */
-#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_SHIFT              26
-#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_MASK               (1 << 26)
-#define OMAP4_LDOVBBMPU_RBB_VSET_IN_SHIFT               21
-#define OMAP4_LDOVBBMPU_RBB_VSET_IN_MASK                (0x1f << 21)
-#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_SHIFT              16
-#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_MASK               (0x1f << 16)
-#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_SHIFT              10
-#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_MASK               (1 << 10)
-#define OMAP4_LDOVBBMPU_FBB_VSET_IN_SHIFT               5
-#define OMAP4_LDOVBBMPU_FBB_VSET_IN_MASK                (0x1f << 5)
-#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_SHIFT              0
-#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_MASK               (0x1f << 0)
-
-/* LDOSRAM_IVA_VOLTAGE_CTRL */
-#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_SHIFT         26
-#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_MASK          (1 << 26)
-#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_SHIFT          21
-#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_MASK           (0x1f << 21)
-#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_SHIFT         16
-#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_MASK          (0x1f << 16)
-#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_SHIFT         10
-#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_MASK          (1 << 10)
-#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_SHIFT          5
-#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_MASK           (0x1f << 5)
-#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_SHIFT         0
-#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_MASK          (0x1f << 0)
-
-/* LDOSRAM_MPU_VOLTAGE_CTRL */
-#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_SHIFT         26
-#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_MASK          (1 << 26)
-#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_SHIFT          21
-#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_MASK           (0x1f << 21)
-#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_SHIFT         16
-#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_MASK          (0x1f << 16)
-#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_SHIFT         10
-#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_MASK          (1 << 10)
-#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_SHIFT          5
-#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_MASK           (0x1f << 5)
-#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_SHIFT         0
-#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_MASK          (0x1f << 0)
-
-/* LDOSRAM_CORE_VOLTAGE_CTRL */
-#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_SHIFT        26
-#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_MASK         (1 << 26)
-#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_SHIFT         21
-#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_MASK          (0x1f << 21)
-#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_SHIFT        16
-#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_MASK         (0x1f << 16)
-#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_SHIFT        10
-#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_MASK         (1 << 10)
-#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_SHIFT         5
-#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_MASK          (0x1f << 5)
-#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_SHIFT        0
-#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_MASK         (0x1f << 0)
-
-/* TEMP_SENSOR */
-#define OMAP4_BGAP_TEMPSOFF_SHIFT                       12
-#define OMAP4_BGAP_TEMPSOFF_MASK                        (1 << 12)
-#define OMAP4_BGAP_TSHUT_SHIFT                          11
-#define OMAP4_BGAP_TSHUT_MASK                           (1 << 11)
-#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT           10
-#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK            (1 << 10)
-#define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT                9
-#define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK                 (1 << 9)
-#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT               8
-#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK                (1 << 8)
-#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT              0
-#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK               (0xff << 0)
-
-/* DPLL_NWELL_TRIM_0 */
-#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_SHIFT        29
-#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_MASK         (1 << 29)
-#define OMAP4_DPLL_ABE_NWELL_TRIM_SHIFT                 24
-#define OMAP4_DPLL_ABE_NWELL_TRIM_MASK                  (0x1f << 24)
-#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_SHIFT        23
-#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_MASK         (1 << 23)
-#define OMAP4_DPLL_PER_NWELL_TRIM_SHIFT                 18
-#define OMAP4_DPLL_PER_NWELL_TRIM_MASK                  (0x1f << 18)
-#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_SHIFT       17
-#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_MASK        (1 << 17)
-#define OMAP4_DPLL_CORE_NWELL_TRIM_SHIFT                12
-#define OMAP4_DPLL_CORE_NWELL_TRIM_MASK                 (0x1f << 12)
-#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_SHIFT        11
-#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_MASK         (1 << 11)
-#define OMAP4_DPLL_IVA_NWELL_TRIM_SHIFT                 6
-#define OMAP4_DPLL_IVA_NWELL_TRIM_MASK                  (0x1f << 6)
-#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_SHIFT        5
-#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_MASK         (1 << 5)
-#define OMAP4_DPLL_MPU_NWELL_TRIM_SHIFT                 0
-#define OMAP4_DPLL_MPU_NWELL_TRIM_MASK                  (0x1f << 0)
-
-/* DPLL_NWELL_TRIM_1 */
-#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_SHIFT     29
-#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_MASK      (1 << 29)
-#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_SHIFT              24
-#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MASK               (0x1f << 24)
-#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_SHIFT        23
-#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_MASK         (1 << 23)
-#define OMAP4_DPLL_USB_NWELL_TRIM_SHIFT                 18
-#define OMAP4_DPLL_USB_NWELL_TRIM_MASK                  (0x1f << 18)
-#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_SHIFT       17
-#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_MASK        (1 << 17)
-#define OMAP4_DPLL_HDMI_NWELL_TRIM_SHIFT                12
-#define OMAP4_DPLL_HDMI_NWELL_TRIM_MASK                 (0x1f << 12)
-#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_SHIFT       11
-#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_MASK        (1 << 11)
-#define OMAP4_DPLL_DSI2_NWELL_TRIM_SHIFT                6
-#define OMAP4_DPLL_DSI2_NWELL_TRIM_MASK                 (0x1f << 6)
-#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_SHIFT       5
-#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_MASK        (1 << 5)
-#define OMAP4_DPLL_DSI1_NWELL_TRIM_SHIFT                0
-#define OMAP4_DPLL_DSI1_NWELL_TRIM_MASK                 (0x1f << 0)
-
-/* USBOTGHS_CONTROL */
-#define OMAP4_DISCHRGVBUS_SHIFT                         8
-#define OMAP4_DISCHRGVBUS_MASK                          (1 << 8)
-#define OMAP4_CHRGVBUS_SHIFT                            7
-#define OMAP4_CHRGVBUS_MASK                             (1 << 7)
-#define OMAP4_DRVVBUS_SHIFT                             6
-#define OMAP4_DRVVBUS_MASK                              (1 << 6)
-#define OMAP4_IDPULLUP_SHIFT                            5
-#define OMAP4_IDPULLUP_MASK                             (1 << 5)
-#define OMAP4_IDDIG_SHIFT                               4
-#define OMAP4_IDDIG_MASK                                (1 << 4)
-#define OMAP4_SESSEND_SHIFT                             3
-#define OMAP4_SESSEND_MASK                              (1 << 3)
-#define OMAP4_VBUSVALID_SHIFT                           2
-#define OMAP4_VBUSVALID_MASK                            (1 << 2)
-#define OMAP4_BVALID_SHIFT                              1
-#define OMAP4_BVALID_MASK                               (1 << 1)
-#define OMAP4_AVALID_SHIFT                              0
-#define OMAP4_AVALID_MASK                               (1 << 0)
-
-/* DSS_CONTROL */
-#define OMAP4_DSS_MUX6_SELECT_SHIFT                     0
-#define OMAP4_DSS_MUX6_SELECT_MASK                      (1 << 0)
-
-/* HWOBS_CONTROL */
-#define OMAP4_HWOBS_CLKDIV_SEL_SHIFT                    3
-#define OMAP4_HWOBS_CLKDIV_SEL_MASK                     (0x1f << 3)
-#define OMAP4_HWOBS_ALL_ZERO_MODE_SHIFT                 2
-#define OMAP4_HWOBS_ALL_ZERO_MODE_MASK                  (1 << 2)
-#define OMAP4_HWOBS_ALL_ONE_MODE_SHIFT                  1
-#define OMAP4_HWOBS_ALL_ONE_MODE_MASK                   (1 << 1)
-#define OMAP4_HWOBS_MACRO_ENABLE_SHIFT                  0
-#define OMAP4_HWOBS_MACRO_ENABLE_MASK                   (1 << 0)
-
-/* DEBOBS_FINAL_MUX_SEL */
-#define OMAP4_SELECT_SHIFT                              0
-#define OMAP4_SELECT_MASK                               (0xffffffff << 0)
-
-/* DEBOBS_MMR_MPU */
-#define OMAP4_SELECT_DEBOBS_MMR_MPU_SHIFT               0
-#define OMAP4_SELECT_DEBOBS_MMR_MPU_MASK                (0xf << 0)
-
-/* CONF_SDMA_REQ_SEL0 */
-#define OMAP4_MULT_SHIFT                                0
-#define OMAP4_MULT_MASK                                 (0x7f << 0)
-
-/* CONF_CLK_SEL0 */
-#define OMAP4_MULT_CONF_CLK_SEL0_SHIFT                  0
-#define OMAP4_MULT_CONF_CLK_SEL0_MASK                   (0x7 << 0)
-
-/* CONF_CLK_SEL1 */
-#define OMAP4_MULT_CONF_CLK_SEL1_SHIFT                  0
-#define OMAP4_MULT_CONF_CLK_SEL1_MASK                   (0x7 << 0)
-
-/* CONF_CLK_SEL2 */
-#define OMAP4_MULT_CONF_CLK_SEL2_SHIFT                  0
-#define OMAP4_MULT_CONF_CLK_SEL2_MASK                   (0x7 << 0)
-
-/* CONF_DPLL_FREQLOCK_SEL */
-#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_SHIFT         0
-#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_MASK          (0x7 << 0)
-
-/* CONF_DPLL_TINITZ_SEL */
-#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_SHIFT           0
-#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_MASK            (0x7 << 0)
-
-/* CONF_DPLL_PHASELOCK_SEL */
-#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_SHIFT        0
-#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_MASK         (0x7 << 0)
-
-/* CONF_DEBUG_SEL_TST_0 */
-#define OMAP4_MODE_SHIFT                                0
-#define OMAP4_MODE_MASK                                 (0xf << 0)
-
-#endif
diff --git a/arch/arm/mach-omap2/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/ctrl_module_pad_core_44xx.h
deleted file mode 100644
index c88420de1151..000000000000
--- a/arch/arm/mach-omap2/ctrl_module_pad_core_44xx.h
+++ /dev/null
@@ -1,1409 +0,0 @@
-/*
- * OMAP44xx CTRL_MODULE_PAD_CORE registers and bitfields
- *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
- *
- * Benoit Cousson (b-cousson@ti.com)
- * Santosh Shilimkar (santosh.shilimkar@ti.com)
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap@vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
-#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
-
-
-/* Base address */
-#define OMAP4_CTRL_MODULE_PAD_CORE                              0x4a100000
-
-/* Registers offset */
-#define OMAP4_CTRL_MODULE_PAD_CORE_IP_REVISION                  0x0000
-#define OMAP4_CTRL_MODULE_PAD_CORE_IP_HWINFO                    0x0004
-#define OMAP4_CTRL_MODULE_PAD_CORE_IP_SYSCONFIG                 0x0010
-#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_0        0x01d8
-#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_1        0x01dc
-#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_2        0x01e0
-#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_3        0x01e4
-#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_4        0x01e8
-#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_5        0x01ec
-#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_6        0x01f0
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_GLOBAL       0x05a0
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_MODE         0x05a4
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_0   0x05a8
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_1   0x05ac
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_0   0x05b0
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_1   0x05b4
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_0   0x05b8
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_1   0x05bc
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_2   0x05c0
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USBB_HSIC            0x05c4
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SLIMBUS              0x05c8
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE            0x0600
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0                0x0604
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX            0x0608
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_AVDAC                0x060c
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDMI_TX_PHY          0x0610
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC2                 0x0614
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY               0x0618
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP              0x061c
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB2PHYCORE          0x0620
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1                0x0624
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1                 0x0628
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HSI                  0x062c
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB                  0x0630
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDQ                  0x0634
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_0          0x0638
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_1          0x063c
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_2          0x0640
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_3          0x0644
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_0          0x0648
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_1          0x064c
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_2          0x0650
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_3          0x0654
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_BUS_HOLD             0x0658
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_C2C                  0x065c
-#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_RW        0x0660
-#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R         0x0664
-#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R_C0      0x0668
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_1              0x0700
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_2              0x0704
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_3              0x0708
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_4              0x070c
-
-/* Registers shifts and masks */
-
-/* IP_REVISION */
-#define OMAP4_IP_REV_SCHEME_SHIFT                               30
-#define OMAP4_IP_REV_SCHEME_MASK                                (0x3 << 30)
-#define OMAP4_IP_REV_FUNC_SHIFT                                 16
-#define OMAP4_IP_REV_FUNC_MASK                                  (0xfff << 16)
-#define OMAP4_IP_REV_RTL_SHIFT                                  11
-#define OMAP4_IP_REV_RTL_MASK                                   (0x1f << 11)
-#define OMAP4_IP_REV_MAJOR_SHIFT                                8
-#define OMAP4_IP_REV_MAJOR_MASK                                 (0x7 << 8)
-#define OMAP4_IP_REV_CUSTOM_SHIFT                               6
-#define OMAP4_IP_REV_CUSTOM_MASK                                (0x3 << 6)
-#define OMAP4_IP_REV_MINOR_SHIFT                                0
-#define OMAP4_IP_REV_MINOR_MASK                                 (0x3f << 0)
-
-/* IP_HWINFO */
-#define OMAP4_IP_HWINFO_SHIFT                                   0
-#define OMAP4_IP_HWINFO_MASK                                    (0xffffffff << 0)
-
-/* IP_SYSCONFIG */
-#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT                       2
-#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK                        (0x3 << 2)
-
-/* PADCONF_WAKEUPEVENT_0 */
-#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_SHIFT               31
-#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_MASK                (1 << 31)
-#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_SHIFT               30
-#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_MASK                (1 << 30)
-#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_SHIFT              29
-#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_MASK               (1 << 29)
-#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_SHIFT              28
-#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_MASK               (1 << 28)
-#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_SHIFT              27
-#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_MASK               (1 << 27)
-#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_SHIFT              26
-#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_MASK               (1 << 26)
-#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_SHIFT               25
-#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_MASK                (1 << 25)
-#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_SHIFT               24
-#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_MASK                (1 << 24)
-#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_SHIFT               23
-#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_MASK                (1 << 23)
-#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_SHIFT               22
-#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_MASK                (1 << 22)
-#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_SHIFT               21
-#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_MASK                (1 << 21)
-#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_SHIFT               20
-#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_MASK                (1 << 20)
-#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_SHIFT               19
-#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_MASK                (1 << 19)
-#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_SHIFT               18
-#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_MASK                (1 << 18)
-#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_SHIFT               17
-#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_MASK                (1 << 17)
-#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_SHIFT               16
-#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_MASK                (1 << 16)
-#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_SHIFT              15
-#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_MASK               (1 << 15)
-#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_SHIFT              14
-#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_MASK               (1 << 14)
-#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_SHIFT              13
-#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_MASK               (1 << 13)
-#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_SHIFT              12
-#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_MASK               (1 << 12)
-#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_SHIFT              11
-#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_MASK               (1 << 11)
-#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_SHIFT              10
-#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_MASK               (1 << 10)
-#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_SHIFT               9
-#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_MASK                (1 << 9)
-#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_SHIFT               8
-#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_MASK                (1 << 8)
-#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_SHIFT               7
-#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_MASK                (1 << 7)
-#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_SHIFT               6
-#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_MASK                (1 << 6)
-#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_SHIFT               5
-#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_MASK                (1 << 5)
-#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_SHIFT               4
-#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_MASK                (1 << 4)
-#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_SHIFT               3
-#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_MASK                (1 << 3)
-#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_SHIFT               2
-#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_MASK                (1 << 2)
-#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_SHIFT               1
-#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_MASK                (1 << 1)
-#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_SHIFT               0
-#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_MASK                (1 << 0)
-
-/* PADCONF_WAKEUPEVENT_1 */
-#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_SHIFT             31
-#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_MASK              (1 << 31)
-#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_SHIFT            30
-#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_MASK             (1 << 30)
-#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_SHIFT              29
-#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_MASK               (1 << 29)
-#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_SHIFT              28
-#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_MASK               (1 << 28)
-#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_SHIFT              27
-#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_MASK               (1 << 27)
-#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_SHIFT              26
-#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_MASK               (1 << 26)
-#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_SHIFT              25
-#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_MASK               (1 << 25)
-#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_SHIFT              24
-#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_MASK               (1 << 24)
-#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_SHIFT              23
-#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_MASK               (1 << 23)
-#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_SHIFT              22
-#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_MASK               (1 << 22)
-#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_SHIFT              21
-#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_MASK               (1 << 21)
-#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_SHIFT              20
-#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_MASK               (1 << 20)
-#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_SHIFT              19
-#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_MASK               (1 << 19)
-#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_SHIFT              18
-#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_MASK               (1 << 18)
-#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_SHIFT              17
-#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_MASK               (1 << 17)
-#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_SHIFT              16
-#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_MASK               (1 << 16)
-#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_SHIFT           15
-#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_MASK            (1 << 15)
-#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_SHIFT           14
-#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_MASK            (1 << 14)
-#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_SHIFT               13
-#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_MASK                (1 << 13)
-#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_SHIFT               12
-#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_MASK                (1 << 12)
-#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_SHIFT             11
-#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_MASK              (1 << 11)
-#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_SHIFT             10
-#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_MASK              (1 << 10)
-#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_SHIFT             9
-#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_MASK              (1 << 9)
-#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_SHIFT             8
-#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_MASK              (1 << 8)
-#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_SHIFT             7
-#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_MASK              (1 << 7)
-#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_SHIFT             6
-#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_MASK              (1 << 6)
-#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_SHIFT             5
-#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_MASK              (1 << 5)
-#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_SHIFT              4
-#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_MASK               (1 << 4)
-#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_SHIFT          3
-#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_MASK           (1 << 3)
-#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_SHIFT               2
-#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_MASK                (1 << 2)
-#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_SHIFT               1
-#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_MASK                (1 << 1)
-#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_SHIFT          0
-#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_MASK           (1 << 0)
-
-/* PADCONF_WAKEUPEVENT_2 */
-#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_SHIFT        31
-#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_MASK         (1 << 31)
-#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_SHIFT         30
-#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_MASK          (1 << 30)
-#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_SHIFT          29
-#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_MASK           (1 << 29)
-#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_SHIFT          28
-#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_MASK           (1 << 28)
-#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_SHIFT        27
-#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_MASK         (1 << 27)
-#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_SHIFT            26
-#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_MASK             (1 << 26)
-#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_SHIFT            25
-#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_MASK             (1 << 25)
-#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_SHIFT            24
-#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_MASK             (1 << 24)
-#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_SHIFT            23
-#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_MASK             (1 << 23)
-#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_SHIFT            22
-#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_MASK             (1 << 22)
-#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_SHIFT            21
-#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_MASK             (1 << 21)
-#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_SHIFT            20
-#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_MASK             (1 << 20)
-#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_SHIFT            19
-#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_MASK             (1 << 19)
-#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_SHIFT             18
-#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_MASK              (1 << 18)
-#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_SHIFT             17
-#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_MASK              (1 << 17)
-#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_SHIFT         16
-#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_MASK          (1 << 16)
-#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_SHIFT         15
-#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_MASK          (1 << 15)
-#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT      14
-#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK       (1 << 14)
-#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT        13
-#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK         (1 << 13)
-#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT     12
-#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK      (1 << 12)
-#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT     11
-#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK      (1 << 11)
-#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT     10
-#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK      (1 << 10)
-#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT     9
-#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK      (1 << 9)
-#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT     8
-#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK      (1 << 8)
-#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT     7
-#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK      (1 << 7)
-#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT     6
-#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK      (1 << 6)
-#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT     5
-#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK      (1 << 5)
-#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT      4
-#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK       (1 << 4)
-#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT      3
-#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK       (1 << 3)
-#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT      2
-#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK       (1 << 2)
-#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT      1
-#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK       (1 << 1)
-#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_SHIFT        0
-#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_MASK         (1 << 0)
-
-/* PADCONF_WAKEUPEVENT_3 */
-#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_SHIFT             31
-#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_MASK              (1 << 31)
-#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_SHIFT             30
-#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_MASK              (1 << 30)
-#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_SHIFT             29
-#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_MASK              (1 << 29)
-#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_SHIFT             28
-#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_MASK              (1 << 28)
-#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_SHIFT            27
-#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_MASK             (1 << 27)
-#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_SHIFT            26
-#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_MASK             (1 << 26)
-#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_SHIFT             25
-#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_MASK              (1 << 25)
-#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_SHIFT               24
-#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_MASK                (1 << 24)
-#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_SHIFT               23
-#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_MASK                (1 << 23)
-#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_SHIFT               22
-#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_MASK                (1 << 22)
-#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_SHIFT               21
-#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_MASK                (1 << 21)
-#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_SHIFT               20
-#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_MASK                (1 << 20)
-#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_SHIFT               19
-#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_MASK                (1 << 19)
-#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_SHIFT               18
-#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_MASK                (1 << 18)
-#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_SHIFT               17
-#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_MASK                (1 << 17)
-#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_SHIFT                16
-#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_MASK                 (1 << 16)
-#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_SHIFT               15
-#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_MASK                (1 << 15)
-#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_SHIFT               14
-#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_MASK                (1 << 14)
-#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_SHIFT              13
-#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_MASK               (1 << 13)
-#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_SHIFT              12
-#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_MASK               (1 << 12)
-#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_SHIFT          11
-#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_MASK           (1 << 11)
-#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_SHIFT          10
-#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_MASK           (1 << 10)
-#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_SHIFT          9
-#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_MASK           (1 << 9)
-#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_SHIFT          8
-#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_MASK           (1 << 8)
-#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_SHIFT               7
-#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_MASK                (1 << 7)
-#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_SHIFT         6
-#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_MASK          (1 << 6)
-#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_SHIFT          5
-#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_MASK           (1 << 5)
-#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_SHIFT        4
-#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_MASK         (1 << 4)
-#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_SHIFT        3
-#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_MASK         (1 << 3)
-#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_SHIFT         2
-#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_MASK          (1 << 2)
-#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_SHIFT          1
-#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_MASK           (1 << 1)
-#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_SHIFT          0
-#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_MASK           (1 << 0)
-
-/* PADCONF_WAKEUPEVENT_4 */
-#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_SHIFT             31
-#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_MASK              (1 << 31)
-#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_SHIFT             30
-#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_MASK              (1 << 30)
-#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT      29
-#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK       (1 << 29)
-#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT        28
-#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK         (1 << 28)
-#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT     27
-#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK      (1 << 27)
-#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT     26
-#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK      (1 << 26)
-#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT     25
-#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK      (1 << 25)
-#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT     24
-#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK      (1 << 24)
-#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT     23
-#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK      (1 << 23)
-#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT     22
-#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK      (1 << 22)
-#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT     21
-#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK      (1 << 21)
-#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT     20
-#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK      (1 << 20)
-#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT      19
-#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK       (1 << 19)
-#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT      18
-#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK       (1 << 18)
-#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT      17
-#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK       (1 << 17)
-#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT      16
-#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK       (1 << 16)
-#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_SHIFT               15
-#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_MASK                (1 << 15)
-#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_SHIFT               14
-#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_MASK                (1 << 14)
-#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_SHIFT             13
-#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_MASK              (1 << 13)
-#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_SHIFT            12
-#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_MASK             (1 << 12)
-#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_SHIFT            11
-#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_MASK             (1 << 11)
-#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_SHIFT             10
-#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_MASK              (1 << 10)
-#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_SHIFT            9
-#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_MASK             (1 << 9)
-#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_SHIFT            8
-#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_MASK             (1 << 8)
-#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_SHIFT            7
-#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_MASK             (1 << 7)
-#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_SHIFT            6
-#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_MASK             (1 << 6)
-#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_SHIFT             5
-#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_MASK              (1 << 5)
-#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_SHIFT             4
-#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_MASK              (1 << 4)
-#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_SHIFT          3
-#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_MASK           (1 << 3)
-#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_SHIFT          2
-#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_MASK           (1 << 2)
-#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_SHIFT           1
-#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_MASK            (1 << 1)
-#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_SHIFT         0
-#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_MASK          (1 << 0)
-
-/* PADCONF_WAKEUPEVENT_5 */
-#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_SHIFT              31
-#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_MASK               (1 << 31)
-#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_SHIFT              30
-#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_MASK               (1 << 30)
-#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_SHIFT               29
-#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_MASK                (1 << 29)
-#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_SHIFT               28
-#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_MASK                (1 << 28)
-#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_SHIFT               27
-#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_MASK                (1 << 27)
-#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_SHIFT               26
-#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_MASK                (1 << 26)
-#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_SHIFT               25
-#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_MASK                (1 << 25)
-#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_SHIFT               24
-#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_MASK                (1 << 24)
-#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_SHIFT               23
-#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_MASK                (1 << 23)
-#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_SHIFT               22
-#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_MASK                (1 << 22)
-#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_SHIFT               21
-#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_MASK                (1 << 21)
-#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_SHIFT               20
-#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_MASK                (1 << 20)
-#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_SHIFT              19
-#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_MASK               (1 << 19)
-#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_SHIFT              18
-#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_MASK               (1 << 18)
-#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_SHIFT              17
-#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_MASK               (1 << 17)
-#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_SHIFT              16
-#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_MASK               (1 << 16)
-#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_SHIFT              15
-#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_MASK               (1 << 15)
-#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_SHIFT              14
-#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_MASK               (1 << 14)
-#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_SHIFT              13
-#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_MASK               (1 << 13)
-#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_SHIFT              12
-#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_MASK               (1 << 12)
-#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_SHIFT          11
-#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_MASK           (1 << 11)
-#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_SHIFT          10
-#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_MASK           (1 << 10)
-#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_SHIFT             9
-#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_MASK              (1 << 9)
-#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_SHIFT             8
-#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_MASK              (1 << 8)
-#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_SHIFT             7
-#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_MASK              (1 << 7)
-#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_SHIFT             6
-#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_MASK              (1 << 6)
-#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_SHIFT             5
-#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_MASK              (1 << 5)
-#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_SHIFT             4
-#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_MASK              (1 << 4)
-#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_SHIFT             3
-#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_MASK              (1 << 3)
-#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_SHIFT             2
-#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_MASK              (1 << 2)
-#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_SHIFT             1
-#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_MASK              (1 << 1)
-#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_SHIFT             0
-#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_MASK              (1 << 0)
-
-/* PADCONF_WAKEUPEVENT_6 */
-#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_SHIFT              7
-#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_MASK               (1 << 7)
-#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_SHIFT              6
-#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_MASK               (1 << 6)
-#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_SHIFT              5
-#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_MASK               (1 << 5)
-#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_SHIFT              4
-#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_MASK               (1 << 4)
-#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_SHIFT              3
-#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_MASK               (1 << 3)
-#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_SHIFT              2
-#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_MASK               (1 << 2)
-#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_SHIFT              1
-#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_MASK               (1 << 1)
-#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_SHIFT              0
-#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_MASK               (1 << 0)
-
-/* CONTROL_PADCONF_GLOBAL */
-#define OMAP4_FORCE_OFFMODE_EN_SHIFT                            31
-#define OMAP4_FORCE_OFFMODE_EN_MASK                             (1 << 31)
-
-/* CONTROL_PADCONF_MODE */
-#define OMAP4_VDDS_DV_BANK0_SHIFT                               31
-#define OMAP4_VDDS_DV_BANK0_MASK                                (1 << 31)
-#define OMAP4_VDDS_DV_BANK1_SHIFT                               30
-#define OMAP4_VDDS_DV_BANK1_MASK                                (1 << 30)
-#define OMAP4_VDDS_DV_BANK3_SHIFT                               29
-#define OMAP4_VDDS_DV_BANK3_MASK                                (1 << 29)
-#define OMAP4_VDDS_DV_BANK4_SHIFT                               28
-#define OMAP4_VDDS_DV_BANK4_MASK                                (1 << 28)
-#define OMAP4_VDDS_DV_BANK5_SHIFT                               27
-#define OMAP4_VDDS_DV_BANK5_MASK                                (1 << 27)
-#define OMAP4_VDDS_DV_BANK6_SHIFT                               26
-#define OMAP4_VDDS_DV_BANK6_MASK                                (1 << 26)
-#define OMAP4_VDDS_DV_C2C_SHIFT                                 25
-#define OMAP4_VDDS_DV_C2C_MASK                                  (1 << 25)
-#define OMAP4_VDDS_DV_CAM_SHIFT                                 24
-#define OMAP4_VDDS_DV_CAM_MASK                                  (1 << 24)
-#define OMAP4_VDDS_DV_GPMC_SHIFT                                23
-#define OMAP4_VDDS_DV_GPMC_MASK                                 (1 << 23)
-#define OMAP4_VDDS_DV_SDMMC2_SHIFT                              22
-#define OMAP4_VDDS_DV_SDMMC2_MASK                               (1 << 22)
-
-/* CONTROL_SMART1IO_PADCONF_0 */
-#define OMAP4_ABE_DR0_SC_SHIFT                                  30
-#define OMAP4_ABE_DR0_SC_MASK                                   (0x3 << 30)
-#define OMAP4_CAM_DR0_SC_SHIFT                                  28
-#define OMAP4_CAM_DR0_SC_MASK                                   (0x3 << 28)
-#define OMAP4_FREF_DR2_SC_SHIFT                                 26
-#define OMAP4_FREF_DR2_SC_MASK                                  (0x3 << 26)
-#define OMAP4_FREF_DR3_SC_SHIFT                                 24
-#define OMAP4_FREF_DR3_SC_MASK                                  (0x3 << 24)
-#define OMAP4_GPIO_DR8_SC_SHIFT                                 22
-#define OMAP4_GPIO_DR8_SC_MASK                                  (0x3 << 22)
-#define OMAP4_GPIO_DR9_SC_SHIFT                                 20
-#define OMAP4_GPIO_DR9_SC_MASK                                  (0x3 << 20)
-#define OMAP4_GPMC_DR2_SC_SHIFT                                 18
-#define OMAP4_GPMC_DR2_SC_MASK                                  (0x3 << 18)
-#define OMAP4_GPMC_DR3_SC_SHIFT                                 16
-#define OMAP4_GPMC_DR3_SC_MASK                                  (0x3 << 16)
-#define OMAP4_GPMC_DR6_SC_SHIFT                                 14
-#define OMAP4_GPMC_DR6_SC_MASK                                  (0x3 << 14)
-#define OMAP4_HDMI_DR0_SC_SHIFT                                 12
-#define OMAP4_HDMI_DR0_SC_MASK                                  (0x3 << 12)
-#define OMAP4_MCSPI1_DR0_SC_SHIFT                               10
-#define OMAP4_MCSPI1_DR0_SC_MASK                                (0x3 << 10)
-#define OMAP4_UART1_DR0_SC_SHIFT                                8
-#define OMAP4_UART1_DR0_SC_MASK                                 (0x3 << 8)
-#define OMAP4_UART3_DR0_SC_SHIFT                                6
-#define OMAP4_UART3_DR0_SC_MASK                                 (0x3 << 6)
-#define OMAP4_UART3_DR1_SC_SHIFT                                4
-#define OMAP4_UART3_DR1_SC_MASK                                 (0x3 << 4)
-#define OMAP4_UNIPRO_DR0_SC_SHIFT                               2
-#define OMAP4_UNIPRO_DR0_SC_MASK                                (0x3 << 2)
-#define OMAP4_UNIPRO_DR1_SC_SHIFT                               0
-#define OMAP4_UNIPRO_DR1_SC_MASK                                (0x3 << 0)
-
-/* CONTROL_SMART1IO_PADCONF_1 */
-#define OMAP4_ABE_DR0_LB_SHIFT                                  30
-#define OMAP4_ABE_DR0_LB_MASK                                   (0x3 << 30)
-#define OMAP4_CAM_DR0_LB_SHIFT                                  28
-#define OMAP4_CAM_DR0_LB_MASK                                   (0x3 << 28)
-#define OMAP4_FREF_DR2_LB_SHIFT                                 26
-#define OMAP4_FREF_DR2_LB_MASK                                  (0x3 << 26)
-#define OMAP4_FREF_DR3_LB_SHIFT                                 24
-#define OMAP4_FREF_DR3_LB_MASK                                  (0x3 << 24)
-#define OMAP4_GPIO_DR8_LB_SHIFT                                 22
-#define OMAP4_GPIO_DR8_LB_MASK                                  (0x3 << 22)
-#define OMAP4_GPIO_DR9_LB_SHIFT                                 20
-#define OMAP4_GPIO_DR9_LB_MASK                                  (0x3 << 20)
-#define OMAP4_GPMC_DR2_LB_SHIFT                                 18
-#define OMAP4_GPMC_DR2_LB_MASK                                  (0x3 << 18)
-#define OMAP4_GPMC_DR3_LB_SHIFT                                 16
-#define OMAP4_GPMC_DR3_LB_MASK                                  (0x3 << 16)
-#define OMAP4_GPMC_DR6_LB_SHIFT                                 14
-#define OMAP4_GPMC_DR6_LB_MASK                                  (0x3 << 14)
-#define OMAP4_HDMI_DR0_LB_SHIFT                                 12
-#define OMAP4_HDMI_DR0_LB_MASK                                  (0x3 << 12)
-#define OMAP4_MCSPI1_DR0_LB_SHIFT                               10
-#define OMAP4_MCSPI1_DR0_LB_MASK                                (0x3 << 10)
-#define OMAP4_UART1_DR0_LB_SHIFT                                8
-#define OMAP4_UART1_DR0_LB_MASK                                 (0x3 << 8)
-#define OMAP4_UART3_DR0_LB_SHIFT                                6
-#define OMAP4_UART3_DR0_LB_MASK                                 (0x3 << 6)
-#define OMAP4_UART3_DR1_LB_SHIFT                                4
-#define OMAP4_UART3_DR1_LB_MASK                                 (0x3 << 4)
-#define OMAP4_UNIPRO_DR0_LB_SHIFT                               2
-#define OMAP4_UNIPRO_DR0_LB_MASK                                (0x3 << 2)
-#define OMAP4_UNIPRO_DR1_LB_SHIFT                               0
-#define OMAP4_UNIPRO_DR1_LB_MASK                                (0x3 << 0)
-
-/* CONTROL_SMART2IO_PADCONF_0 */
-#define OMAP4_C2C_DR0_LB_SHIFT                                  31
-#define OMAP4_C2C_DR0_LB_MASK                                   (1 << 31)
-#define OMAP4_DPM_DR1_LB_SHIFT                                  30
-#define OMAP4_DPM_DR1_LB_MASK                                   (1 << 30)
-#define OMAP4_DPM_DR2_LB_SHIFT                                  29
-#define OMAP4_DPM_DR2_LB_MASK                                   (1 << 29)
-#define OMAP4_DPM_DR3_LB_SHIFT                                  28
-#define OMAP4_DPM_DR3_LB_MASK                                   (1 << 28)
-#define OMAP4_GPIO_DR0_LB_SHIFT                                 27
-#define OMAP4_GPIO_DR0_LB_MASK                                  (1 << 27)
-#define OMAP4_GPIO_DR1_LB_SHIFT                                 26
-#define OMAP4_GPIO_DR1_LB_MASK                                  (1 << 26)
-#define OMAP4_GPIO_DR10_LB_SHIFT                                25
-#define OMAP4_GPIO_DR10_LB_MASK                                 (1 << 25)
-#define OMAP4_GPIO_DR2_LB_SHIFT                                 24
-#define OMAP4_GPIO_DR2_LB_MASK                                  (1 << 24)
-#define OMAP4_GPMC_DR0_LB_SHIFT                                 23
-#define OMAP4_GPMC_DR0_LB_MASK                                  (1 << 23)
-#define OMAP4_GPMC_DR1_LB_SHIFT                                 22
-#define OMAP4_GPMC_DR1_LB_MASK                                  (1 << 22)
-#define OMAP4_GPMC_DR4_LB_SHIFT                                 21
-#define OMAP4_GPMC_DR4_LB_MASK                                  (1 << 21)
-#define OMAP4_GPMC_DR5_LB_SHIFT                                 20
-#define OMAP4_GPMC_DR5_LB_MASK                                  (1 << 20)
-#define OMAP4_GPMC_DR7_LB_SHIFT                                 19
-#define OMAP4_GPMC_DR7_LB_MASK                                  (1 << 19)
-#define OMAP4_HSI2_DR0_LB_SHIFT                                 18
-#define OMAP4_HSI2_DR0_LB_MASK                                  (1 << 18)
-#define OMAP4_HSI2_DR1_LB_SHIFT                                 17
-#define OMAP4_HSI2_DR1_LB_MASK                                  (1 << 17)
-#define OMAP4_HSI2_DR2_LB_SHIFT                                 16
-#define OMAP4_HSI2_DR2_LB_MASK                                  (1 << 16)
-#define OMAP4_KPD_DR0_LB_SHIFT                                  15
-#define OMAP4_KPD_DR0_LB_MASK                                   (1 << 15)
-#define OMAP4_KPD_DR1_LB_SHIFT                                  14
-#define OMAP4_KPD_DR1_LB_MASK                                   (1 << 14)
-#define OMAP4_PDM_DR0_LB_SHIFT                                  13
-#define OMAP4_PDM_DR0_LB_MASK                                   (1 << 13)
-#define OMAP4_SDMMC2_DR0_LB_SHIFT                               12
-#define OMAP4_SDMMC2_DR0_LB_MASK                                (1 << 12)
-#define OMAP4_SDMMC3_DR0_LB_SHIFT                               11
-#define OMAP4_SDMMC3_DR0_LB_MASK                                (1 << 11)
-#define OMAP4_SDMMC4_DR0_LB_SHIFT                               10
-#define OMAP4_SDMMC4_DR0_LB_MASK                                (1 << 10)
-#define OMAP4_SDMMC4_DR1_LB_SHIFT                               9
-#define OMAP4_SDMMC4_DR1_LB_MASK                                (1 << 9)
-#define OMAP4_SPI3_DR0_LB_SHIFT                                 8
-#define OMAP4_SPI3_DR0_LB_MASK                                  (1 << 8)
-#define OMAP4_SPI3_DR1_LB_SHIFT                                 7
-#define OMAP4_SPI3_DR1_LB_MASK                                  (1 << 7)
-#define OMAP4_UART3_DR2_LB_SHIFT                                6
-#define OMAP4_UART3_DR2_LB_MASK                                 (1 << 6)
-#define OMAP4_UART3_DR3_LB_SHIFT                                5
-#define OMAP4_UART3_DR3_LB_MASK                                 (1 << 5)
-#define OMAP4_UART3_DR4_LB_SHIFT                                4
-#define OMAP4_UART3_DR4_LB_MASK                                 (1 << 4)
-#define OMAP4_UART3_DR5_LB_SHIFT                                3
-#define OMAP4_UART3_DR5_LB_MASK                                 (1 << 3)
-#define OMAP4_USBA0_DR1_LB_SHIFT                                2
-#define OMAP4_USBA0_DR1_LB_MASK                                 (1 << 2)
-#define OMAP4_USBA_DR2_LB_SHIFT                                 1
-#define OMAP4_USBA_DR2_LB_MASK                                  (1 << 1)
-
-/* CONTROL_SMART2IO_PADCONF_1 */
-#define OMAP4_USBB1_DR0_LB_SHIFT                                31
-#define OMAP4_USBB1_DR0_LB_MASK                                 (1 << 31)
-#define OMAP4_USBB2_DR0_LB_SHIFT                                30
-#define OMAP4_USBB2_DR0_LB_MASK                                 (1 << 30)
-#define OMAP4_USBA0_DR0_LB_SHIFT                                29
-#define OMAP4_USBA0_DR0_LB_MASK                                 (1 << 29)
-
-/* CONTROL_SMART3IO_PADCONF_0 */
-#define OMAP4_DMIC_DR0_MB_SHIFT                                 30
-#define OMAP4_DMIC_DR0_MB_MASK                                  (0x3 << 30)
-#define OMAP4_GPIO_DR3_MB_SHIFT                                 28
-#define OMAP4_GPIO_DR3_MB_MASK                                  (0x3 << 28)
-#define OMAP4_GPIO_DR4_MB_SHIFT                                 26
-#define OMAP4_GPIO_DR4_MB_MASK                                  (0x3 << 26)
-#define OMAP4_GPIO_DR5_MB_SHIFT                                 24
-#define OMAP4_GPIO_DR5_MB_MASK                                  (0x3 << 24)
-#define OMAP4_GPIO_DR6_MB_SHIFT                                 22
-#define OMAP4_GPIO_DR6_MB_MASK                                  (0x3 << 22)
-#define OMAP4_HSI_DR1_MB_SHIFT                                  20
-#define OMAP4_HSI_DR1_MB_MASK                                   (0x3 << 20)
-#define OMAP4_HSI_DR2_MB_SHIFT                                  18
-#define OMAP4_HSI_DR2_MB_MASK                                   (0x3 << 18)
-#define OMAP4_HSI_DR3_MB_SHIFT                                  16
-#define OMAP4_HSI_DR3_MB_MASK                                   (0x3 << 16)
-#define OMAP4_MCBSP2_DR0_MB_SHIFT                               14
-#define OMAP4_MCBSP2_DR0_MB_MASK                                (0x3 << 14)
-#define OMAP4_MCSPI4_DR0_MB_SHIFT                               12
-#define OMAP4_MCSPI4_DR0_MB_MASK                                (0x3 << 12)
-#define OMAP4_MCSPI4_DR1_MB_SHIFT                               10
-#define OMAP4_MCSPI4_DR1_MB_MASK                                (0x3 << 10)
-#define OMAP4_SDMMC3_DR0_MB_SHIFT                               8
-#define OMAP4_SDMMC3_DR0_MB_MASK                                (0x3 << 8)
-#define OMAP4_SPI2_DR0_MB_SHIFT                                 0
-#define OMAP4_SPI2_DR0_MB_MASK                                  (0x3 << 0)
-
-/* CONTROL_SMART3IO_PADCONF_1 */
-#define OMAP4_SPI2_DR1_MB_SHIFT                                 30
-#define OMAP4_SPI2_DR1_MB_MASK                                  (0x3 << 30)
-#define OMAP4_SPI2_DR2_MB_SHIFT                                 28
-#define OMAP4_SPI2_DR2_MB_MASK                                  (0x3 << 28)
-#define OMAP4_UART2_DR0_MB_SHIFT                                26
-#define OMAP4_UART2_DR0_MB_MASK                                 (0x3 << 26)
-#define OMAP4_UART2_DR1_MB_SHIFT                                24
-#define OMAP4_UART2_DR1_MB_MASK                                 (0x3 << 24)
-#define OMAP4_UART4_DR0_MB_SHIFT                                22
-#define OMAP4_UART4_DR0_MB_MASK                                 (0x3 << 22)
-#define OMAP4_HSI_DR0_MB_SHIFT                                  20
-#define OMAP4_HSI_DR0_MB_MASK                                   (0x3 << 20)
-
-/* CONTROL_SMART3IO_PADCONF_2 */
-#define OMAP4_DMIC_DR0_LB_SHIFT                                 31
-#define OMAP4_DMIC_DR0_LB_MASK                                  (1 << 31)
-#define OMAP4_GPIO_DR3_LB_SHIFT                                 30
-#define OMAP4_GPIO_DR3_LB_MASK                                  (1 << 30)
-#define OMAP4_GPIO_DR4_LB_SHIFT                                 29
-#define OMAP4_GPIO_DR4_LB_MASK                                  (1 << 29)
-#define OMAP4_GPIO_DR5_LB_SHIFT                                 28
-#define OMAP4_GPIO_DR5_LB_MASK                                  (1 << 28)
-#define OMAP4_GPIO_DR6_LB_SHIFT                                 27
-#define OMAP4_GPIO_DR6_LB_MASK                                  (1 << 27)
-#define OMAP4_HSI_DR1_LB_SHIFT                                  26
-#define OMAP4_HSI_DR1_LB_MASK                                   (1 << 26)
-#define OMAP4_HSI_DR2_LB_SHIFT                                  25
-#define OMAP4_HSI_DR2_LB_MASK                                   (1 << 25)
-#define OMAP4_HSI_DR3_LB_SHIFT                                  24
-#define OMAP4_HSI_DR3_LB_MASK                                   (1 << 24)
-#define OMAP4_MCBSP2_DR0_LB_SHIFT                               23
-#define OMAP4_MCBSP2_DR0_LB_MASK                                (1 << 23)
-#define OMAP4_MCSPI4_DR0_LB_SHIFT                               22
-#define OMAP4_MCSPI4_DR0_LB_MASK                                (1 << 22)
-#define OMAP4_MCSPI4_DR1_LB_SHIFT                               21
-#define OMAP4_MCSPI4_DR1_LB_MASK                                (1 << 21)
-#define OMAP4_SLIMBUS2_DR0_LB_SHIFT                             18
-#define OMAP4_SLIMBUS2_DR0_LB_MASK                              (1 << 18)
-#define OMAP4_SPI2_DR0_LB_SHIFT                                 16
-#define OMAP4_SPI2_DR0_LB_MASK                                  (1 << 16)
-#define OMAP4_SPI2_DR1_LB_SHIFT                                 15
-#define OMAP4_SPI2_DR1_LB_MASK                                  (1 << 15)
-#define OMAP4_SPI2_DR2_LB_SHIFT                                 14
-#define OMAP4_SPI2_DR2_LB_MASK                                  (1 << 14)
-#define OMAP4_UART2_DR0_LB_SHIFT                                13
-#define OMAP4_UART2_DR0_LB_MASK                                 (1 << 13)
-#define OMAP4_UART2_DR1_LB_SHIFT                                12
-#define OMAP4_UART2_DR1_LB_MASK                                 (1 << 12)
-#define OMAP4_UART4_DR0_LB_SHIFT                                11
-#define OMAP4_UART4_DR0_LB_MASK                                 (1 << 11)
-#define OMAP4_HSI_DR0_LB_SHIFT                                  10
-#define OMAP4_HSI_DR0_LB_MASK                                   (1 << 10)
-
-/* CONTROL_USBB_HSIC */
-#define OMAP4_USBB2_DR1_SR_SHIFT                                30
-#define OMAP4_USBB2_DR1_SR_MASK                                 (0x3 << 30)
-#define OMAP4_USBB2_DR1_I_SHIFT                                 27
-#define OMAP4_USBB2_DR1_I_MASK                                  (0x7 << 27)
-#define OMAP4_USBB1_DR1_SR_SHIFT                                25
-#define OMAP4_USBB1_DR1_SR_MASK                                 (0x3 << 25)
-#define OMAP4_USBB1_DR1_I_SHIFT                                 22
-#define OMAP4_USBB1_DR1_I_MASK                                  (0x7 << 22)
-#define OMAP4_USBB1_HSIC_DATA_WD_SHIFT                          20
-#define OMAP4_USBB1_HSIC_DATA_WD_MASK                           (0x3 << 20)
-#define OMAP4_USBB1_HSIC_STROBE_WD_SHIFT                        18
-#define OMAP4_USBB1_HSIC_STROBE_WD_MASK                         (0x3 << 18)
-#define OMAP4_USBB2_HSIC_DATA_WD_SHIFT                          16
-#define OMAP4_USBB2_HSIC_DATA_WD_MASK                           (0x3 << 16)
-#define OMAP4_USBB2_HSIC_STROBE_WD_SHIFT                        14
-#define OMAP4_USBB2_HSIC_STROBE_WD_MASK                         (0x3 << 14)
-#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT           13
-#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_MASK            (1 << 13)
-#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_SHIFT                  11
-#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_MASK                   (0x3 << 11)
-#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT         10
-#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK          (1 << 10)
-#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_SHIFT                8
-#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_MASK                 (0x3 << 8)
-#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT           7
-#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_MASK            (1 << 7)
-#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_SHIFT                  5
-#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_MASK                   (0x3 << 5)
-#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT         4
-#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK          (1 << 4)
-#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_SHIFT                2
-#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_MASK                 (0x3 << 2)
-
-/* CONTROL_SLIMBUS */
-#define OMAP4_SLIMBUS1_DR0_MB_SHIFT                             30
-#define OMAP4_SLIMBUS1_DR0_MB_MASK                              (0x3 << 30)
-#define OMAP4_SLIMBUS1_DR1_MB_SHIFT                             28
-#define OMAP4_SLIMBUS1_DR1_MB_MASK                              (0x3 << 28)
-#define OMAP4_SLIMBUS2_DR0_MB_SHIFT                             26
-#define OMAP4_SLIMBUS2_DR0_MB_MASK                              (0x3 << 26)
-#define OMAP4_SLIMBUS2_DR1_MB_SHIFT                             24
-#define OMAP4_SLIMBUS2_DR1_MB_MASK                              (0x3 << 24)
-#define OMAP4_SLIMBUS2_DR2_MB_SHIFT                             22
-#define OMAP4_SLIMBUS2_DR2_MB_MASK                              (0x3 << 22)
-#define OMAP4_SLIMBUS2_DR3_MB_SHIFT                             20
-#define OMAP4_SLIMBUS2_DR3_MB_MASK                              (0x3 << 20)
-#define OMAP4_SLIMBUS1_DR0_LB_SHIFT                             19
-#define OMAP4_SLIMBUS1_DR0_LB_MASK                              (1 << 19)
-#define OMAP4_SLIMBUS2_DR1_LB_SHIFT                             18
-#define OMAP4_SLIMBUS2_DR1_LB_MASK                              (1 << 18)
-
-/* CONTROL_PBIASLITE */
-#define OMAP4_USIM_PBIASLITE_HIZ_MODE_SHIFT                     31
-#define OMAP4_USIM_PBIASLITE_HIZ_MODE_MASK                      (1 << 31)
-#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_SHIFT                30
-#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_MASK                 (1 << 30)
-#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_SHIFT                  29
-#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_MASK                   (1 << 29)
-#define OMAP4_USIM_PBIASLITE_PWRDNZ_SHIFT                       28
-#define OMAP4_USIM_PBIASLITE_PWRDNZ_MASK                        (1 << 28)
-#define OMAP4_USIM_PBIASLITE_VMODE_SHIFT                        27
-#define OMAP4_USIM_PBIASLITE_VMODE_MASK                         (1 << 27)
-#define OMAP4_MMC1_PWRDNZ_SHIFT                                 26
-#define OMAP4_MMC1_PWRDNZ_MASK                                  (1 << 26)
-#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_SHIFT                     25
-#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_MASK                      (1 << 25)
-#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_SHIFT                24
-#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_MASK                 (1 << 24)
-#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_SHIFT                  23
-#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK                   (1 << 23)
-#define OMAP4_MMC1_PBIASLITE_PWRDNZ_SHIFT                       22
-#define OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK                        (1 << 22)
-#define OMAP4_MMC1_PBIASLITE_VMODE_SHIFT                        21
-#define OMAP4_MMC1_PBIASLITE_VMODE_MASK                         (1 << 21)
-#define OMAP4_USBC1_ICUSB_PWRDNZ_SHIFT                          20
-#define OMAP4_USBC1_ICUSB_PWRDNZ_MASK                           (1 << 20)
-
-/* CONTROL_I2C_0 */
-#define OMAP4_I2C4_SDA_GLFENB_SHIFT                             31
-#define OMAP4_I2C4_SDA_GLFENB_MASK                              (1 << 31)
-#define OMAP4_I2C4_SDA_LOAD_BITS_SHIFT                          29
-#define OMAP4_I2C4_SDA_LOAD_BITS_MASK                           (0x3 << 29)
-#define OMAP4_I2C4_SDA_PULLUPRESX_SHIFT                         28
-#define OMAP4_I2C4_SDA_PULLUPRESX_MASK                          (1 << 28)
-#define OMAP4_I2C3_SDA_GLFENB_SHIFT                             27
-#define OMAP4_I2C3_SDA_GLFENB_MASK                              (1 << 27)
-#define OMAP4_I2C3_SDA_LOAD_BITS_SHIFT                          25
-#define OMAP4_I2C3_SDA_LOAD_BITS_MASK                           (0x3 << 25)
-#define OMAP4_I2C3_SDA_PULLUPRESX_SHIFT                         24
-#define OMAP4_I2C3_SDA_PULLUPRESX_MASK                          (1 << 24)
-#define OMAP4_I2C2_SDA_GLFENB_SHIFT                             23
-#define OMAP4_I2C2_SDA_GLFENB_MASK                              (1 << 23)
-#define OMAP4_I2C2_SDA_LOAD_BITS_SHIFT                          21
-#define OMAP4_I2C2_SDA_LOAD_BITS_MASK                           (0x3 << 21)
-#define OMAP4_I2C2_SDA_PULLUPRESX_SHIFT                         20
-#define OMAP4_I2C2_SDA_PULLUPRESX_MASK                          (1 << 20)
-#define OMAP4_I2C1_SDA_GLFENB_SHIFT                             19
-#define OMAP4_I2C1_SDA_GLFENB_MASK                              (1 << 19)
-#define OMAP4_I2C1_SDA_LOAD_BITS_SHIFT                          17
-#define OMAP4_I2C1_SDA_LOAD_BITS_MASK                           (0x3 << 17)
-#define OMAP4_I2C1_SDA_PULLUPRESX_SHIFT                         16
-#define OMAP4_I2C1_SDA_PULLUPRESX_MASK                          (1 << 16)
-#define OMAP4_I2C4_SCL_GLFENB_SHIFT                             15
-#define OMAP4_I2C4_SCL_GLFENB_MASK                              (1 << 15)
-#define OMAP4_I2C4_SCL_LOAD_BITS_SHIFT                          13
-#define OMAP4_I2C4_SCL_LOAD_BITS_MASK                           (0x3 << 13)
-#define OMAP4_I2C4_SCL_PULLUPRESX_SHIFT                         12
-#define OMAP4_I2C4_SCL_PULLUPRESX_MASK                          (1 << 12)
-#define OMAP4_I2C3_SCL_GLFENB_SHIFT                             11
-#define OMAP4_I2C3_SCL_GLFENB_MASK                              (1 << 11)
-#define OMAP4_I2C3_SCL_LOAD_BITS_SHIFT                          9
-#define OMAP4_I2C3_SCL_LOAD_BITS_MASK                           (0x3 << 9)
-#define OMAP4_I2C3_SCL_PULLUPRESX_SHIFT                         8
-#define OMAP4_I2C3_SCL_PULLUPRESX_MASK                          (1 << 8)
-#define OMAP4_I2C2_SCL_GLFENB_SHIFT                             7
-#define OMAP4_I2C2_SCL_GLFENB_MASK                              (1 << 7)
-#define OMAP4_I2C2_SCL_LOAD_BITS_SHIFT                          5
-#define OMAP4_I2C2_SCL_LOAD_BITS_MASK                           (0x3 << 5)
-#define OMAP4_I2C2_SCL_PULLUPRESX_SHIFT                         4
-#define OMAP4_I2C2_SCL_PULLUPRESX_MASK                          (1 << 4)
-#define OMAP4_I2C1_SCL_GLFENB_SHIFT                             3
-#define OMAP4_I2C1_SCL_GLFENB_MASK                              (1 << 3)
-#define OMAP4_I2C1_SCL_LOAD_BITS_SHIFT                          1
-#define OMAP4_I2C1_SCL_LOAD_BITS_MASK                           (0x3 << 1)
-#define OMAP4_I2C1_SCL_PULLUPRESX_SHIFT                         0
-#define OMAP4_I2C1_SCL_PULLUPRESX_MASK                          (1 << 0)
-
-/* CONTROL_CAMERA_RX */
-#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_SHIFT                   31
-#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_MASK                    (1 << 31)
-#define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT                   29
-#define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK                    (0x3 << 29)
-#define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT                   24
-#define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK                    (0x1f << 24)
-#define OMAP4_CAMERARX_UNIPRO_CAMMODE_SHIFT                     22
-#define OMAP4_CAMERARX_UNIPRO_CAMMODE_MASK                      (0x3 << 22)
-#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT                    21
-#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK                     (1 << 21)
-#define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT                      19
-#define OMAP4_CAMERARX_CSI22_CAMMODE_MASK                       (0x3 << 19)
-#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT                    18
-#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK                     (1 << 18)
-#define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT                      16
-#define OMAP4_CAMERARX_CSI21_CAMMODE_MASK                       (0x3 << 16)
-
-/* CONTROL_AVDAC */
-#define OMAP4_AVDAC_ACEN_SHIFT                                  31
-#define OMAP4_AVDAC_ACEN_MASK                                   (1 << 31)
-#define OMAP4_AVDAC_TVOUTBYPASS_SHIFT                           30
-#define OMAP4_AVDAC_TVOUTBYPASS_MASK                            (1 << 30)
-#define OMAP4_AVDAC_INPUTINV_SHIFT                              29
-#define OMAP4_AVDAC_INPUTINV_MASK                               (1 << 29)
-#define OMAP4_AVDAC_CTL_SHIFT                                   13
-#define OMAP4_AVDAC_CTL_MASK                                    (0xffff << 13)
-#define OMAP4_AVDAC_CTL_WR_ACK_SHIFT                            12
-#define OMAP4_AVDAC_CTL_WR_ACK_MASK                             (1 << 12)
-
-/* CONTROL_HDMI_TX_PHY */
-#define OMAP4_HDMITXPHY_PADORDER_SHIFT                          31
-#define OMAP4_HDMITXPHY_PADORDER_MASK                           (1 << 31)
-#define OMAP4_HDMITXPHY_TXVALID_SHIFT                           30
-#define OMAP4_HDMITXPHY_TXVALID_MASK                            (1 << 30)
-#define OMAP4_HDMITXPHY_ENBYPASSCLK_SHIFT                       29
-#define OMAP4_HDMITXPHY_ENBYPASSCLK_MASK                        (1 << 29)
-#define OMAP4_HDMITXPHY_PD_PULLUPDET_SHIFT                      28
-#define OMAP4_HDMITXPHY_PD_PULLUPDET_MASK                       (1 << 28)
-
-/* CONTROL_MMC2 */
-#define OMAP4_MMC2_FEEDBACK_CLK_SEL_SHIFT                       31
-#define OMAP4_MMC2_FEEDBACK_CLK_SEL_MASK                        (1 << 31)
-
-/* CONTROL_DSIPHY */
-#define OMAP4_DSI2_LANEENABLE_SHIFT                             29
-#define OMAP4_DSI2_LANEENABLE_MASK                              (0x7 << 29)
-#define OMAP4_DSI1_LANEENABLE_SHIFT                             24
-#define OMAP4_DSI1_LANEENABLE_MASK                              (0x1f << 24)
-#define OMAP4_DSI1_PIPD_SHIFT                                   19
-#define OMAP4_DSI1_PIPD_MASK                                    (0x1f << 19)
-#define OMAP4_DSI2_PIPD_SHIFT                                   14
-#define OMAP4_DSI2_PIPD_MASK                                    (0x1f << 14)
-
-/* CONTROL_MCBSPLP */
-#define OMAP4_ALBCTRLRX_FSX_SHIFT                               31
-#define OMAP4_ALBCTRLRX_FSX_MASK                                (1 << 31)
-#define OMAP4_ALBCTRLRX_CLKX_SHIFT                              30
-#define OMAP4_ALBCTRLRX_CLKX_MASK                               (1 << 30)
-#define OMAP4_ABE_MCBSP1_DR_EN_SHIFT                            29
-#define OMAP4_ABE_MCBSP1_DR_EN_MASK                             (1 << 29)
-
-/* CONTROL_USB2PHYCORE */
-#define OMAP4_USB2PHY_AUTORESUME_EN_SHIFT                       31
-#define OMAP4_USB2PHY_AUTORESUME_EN_MASK                        (1 << 31)
-#define OMAP4_USB2PHY_DISCHGDET_SHIFT                           30
-#define OMAP4_USB2PHY_DISCHGDET_MASK                            (1 << 30)
-#define OMAP4_USB2PHY_GPIOMODE_SHIFT                            29
-#define OMAP4_USB2PHY_GPIOMODE_MASK                             (1 << 29)
-#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_SHIFT                     28
-#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_MASK                      (1 << 28)
-#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_SHIFT                    27
-#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_MASK                     (1 << 27)
-#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_SHIFT                    26
-#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_MASK                     (1 << 26)
-#define OMAP4_USB2PHY_CHG_VSRC_EN_SHIFT                         25
-#define OMAP4_USB2PHY_CHG_VSRC_EN_MASK                          (1 << 25)
-#define OMAP4_USB2PHY_CHG_ISINK_EN_SHIFT                        24
-#define OMAP4_USB2PHY_CHG_ISINK_EN_MASK                         (1 << 24)
-#define OMAP4_USB2PHY_CHG_DET_STATUS_SHIFT                      21
-#define OMAP4_USB2PHY_CHG_DET_STATUS_MASK                       (0x7 << 21)
-#define OMAP4_USB2PHY_CHG_DET_DM_COMP_SHIFT                     20
-#define OMAP4_USB2PHY_CHG_DET_DM_COMP_MASK                      (1 << 20)
-#define OMAP4_USB2PHY_CHG_DET_DP_COMP_SHIFT                     19
-#define OMAP4_USB2PHY_CHG_DET_DP_COMP_MASK                      (1 << 19)
-#define OMAP4_USB2PHY_DATADET_SHIFT                             18
-#define OMAP4_USB2PHY_DATADET_MASK                              (1 << 18)
-#define OMAP4_USB2PHY_SINKONDP_SHIFT                            17
-#define OMAP4_USB2PHY_SINKONDP_MASK                             (1 << 17)
-#define OMAP4_USB2PHY_SRCONDM_SHIFT                             16
-#define OMAP4_USB2PHY_SRCONDM_MASK                              (1 << 16)
-#define OMAP4_USB2PHY_RESTARTCHGDET_SHIFT                       15
-#define OMAP4_USB2PHY_RESTARTCHGDET_MASK                        (1 << 15)
-#define OMAP4_USB2PHY_CHGDETDONE_SHIFT                          14
-#define OMAP4_USB2PHY_CHGDETDONE_MASK                           (1 << 14)
-#define OMAP4_USB2PHY_CHGDETECTED_SHIFT                         13
-#define OMAP4_USB2PHY_CHGDETECTED_MASK                          (1 << 13)
-#define OMAP4_USB2PHY_MCPCPUEN_SHIFT                            12
-#define OMAP4_USB2PHY_MCPCPUEN_MASK                             (1 << 12)
-#define OMAP4_USB2PHY_MCPCMODEEN_SHIFT                          11
-#define OMAP4_USB2PHY_MCPCMODEEN_MASK                           (1 << 11)
-#define OMAP4_USB2PHY_RESETDONEMCLK_SHIFT                       10
-#define OMAP4_USB2PHY_RESETDONEMCLK_MASK                        (1 << 10)
-#define OMAP4_USB2PHY_UTMIRESETDONE_SHIFT                       9
-#define OMAP4_USB2PHY_UTMIRESETDONE_MASK                        (1 << 9)
-#define OMAP4_USB2PHY_TXBITSTUFFENABLE_SHIFT                    8
-#define OMAP4_USB2PHY_TXBITSTUFFENABLE_MASK                     (1 << 8)
-#define OMAP4_USB2PHY_DATAPOLARITYN_SHIFT                       7
-#define OMAP4_USB2PHY_DATAPOLARITYN_MASK                        (1 << 7)
-#define OMAP4_USBDPLL_FREQLOCK_SHIFT                            6
-#define OMAP4_USBDPLL_FREQLOCK_MASK                             (1 << 6)
-#define OMAP4_USB2PHY_RESETDONETCLK_SHIFT                       5
-#define OMAP4_USB2PHY_RESETDONETCLK_MASK                        (1 << 5)
-
-/* CONTROL_I2C_1 */
-#define OMAP4_HDMI_DDC_SDA_GLFENB_SHIFT                         31
-#define OMAP4_HDMI_DDC_SDA_GLFENB_MASK                          (1 << 31)
-#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_SHIFT                      29
-#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_MASK                       (0x3 << 29)
-#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_SHIFT                     28
-#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK                      (1 << 28)
-#define OMAP4_HDMI_DDC_SCL_GLFENB_SHIFT                         27
-#define OMAP4_HDMI_DDC_SCL_GLFENB_MASK                          (1 << 27)
-#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_SHIFT                      25
-#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_MASK                       (0x3 << 25)
-#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_SHIFT                     24
-#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK                      (1 << 24)
-#define OMAP4_HDMI_DDC_SDA_HSMODE_SHIFT                         23
-#define OMAP4_HDMI_DDC_SDA_HSMODE_MASK                          (1 << 23)
-#define OMAP4_HDMI_DDC_SDA_NMODE_SHIFT                          22
-#define OMAP4_HDMI_DDC_SDA_NMODE_MASK                           (1 << 22)
-#define OMAP4_HDMI_DDC_SCL_HSMODE_SHIFT                         21
-#define OMAP4_HDMI_DDC_SCL_HSMODE_MASK                          (1 << 21)
-#define OMAP4_HDMI_DDC_SCL_NMODE_SHIFT                          20
-#define OMAP4_HDMI_DDC_SCL_NMODE_MASK                           (1 << 20)
-
-/* CONTROL_MMC1 */
-#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_SHIFT                      31
-#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK                       (1 << 31)
-#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_SHIFT                      30
-#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK                       (1 << 30)
-#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_SHIFT                      29
-#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK                       (1 << 29)
-#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_SHIFT                      28
-#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK                       (1 << 28)
-#define OMAP4_SDMMC1_DR0_SPEEDCTRL_SHIFT                        27
-#define OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK                         (1 << 27)
-#define OMAP4_SDMMC1_DR1_SPEEDCTRL_SHIFT                        26
-#define OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK                         (1 << 26)
-#define OMAP4_SDMMC1_DR2_SPEEDCTRL_SHIFT                        25
-#define OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK                         (1 << 25)
-#define OMAP4_USBC1_DR0_SPEEDCTRL_SHIFT                         24
-#define OMAP4_USBC1_DR0_SPEEDCTRL_MASK                          (1 << 24)
-#define OMAP4_USB_FD_CDEN_SHIFT                                 23
-#define OMAP4_USB_FD_CDEN_MASK                                  (1 << 23)
-#define OMAP4_USBC1_ICUSB_DP_PDDIS_SHIFT                        22
-#define OMAP4_USBC1_ICUSB_DP_PDDIS_MASK                         (1 << 22)
-#define OMAP4_USBC1_ICUSB_DM_PDDIS_SHIFT                        21
-#define OMAP4_USBC1_ICUSB_DM_PDDIS_MASK                         (1 << 21)
-
-/* CONTROL_HSI */
-#define OMAP4_HSI1_CALLOOP_SEL_SHIFT                            31
-#define OMAP4_HSI1_CALLOOP_SEL_MASK                             (1 << 31)
-#define OMAP4_HSI1_CALMUX_SEL_SHIFT                             30
-#define OMAP4_HSI1_CALMUX_SEL_MASK                              (1 << 30)
-#define OMAP4_HSI2_CALLOOP_SEL_SHIFT                            29
-#define OMAP4_HSI2_CALLOOP_SEL_MASK                             (1 << 29)
-#define OMAP4_HSI2_CALMUX_SEL_SHIFT                             28
-#define OMAP4_HSI2_CALMUX_SEL_MASK                              (1 << 28)
-
-/* CONTROL_USB */
-#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_SHIFT           31
-#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_MASK            (1 << 31)
-#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_SHIFT           30
-#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_MASK            (1 << 30)
-
-/* CONTROL_HDQ */
-#define OMAP4_HDQ_SIO_PWRDNZ_SHIFT                              31
-#define OMAP4_HDQ_SIO_PWRDNZ_MASK                               (1 << 31)
-
-/* CONTROL_LPDDR2IO1_0 */
-#define OMAP4_LPDDR2IO1_GR4_SR_SHIFT                            30
-#define OMAP4_LPDDR2IO1_GR4_SR_MASK                             (0x3 << 30)
-#define OMAP4_LPDDR2IO1_GR4_I_SHIFT                             27
-#define OMAP4_LPDDR2IO1_GR4_I_MASK                              (0x7 << 27)
-#define OMAP4_LPDDR2IO1_GR4_WD_SHIFT                            25
-#define OMAP4_LPDDR2IO1_GR4_WD_MASK                             (0x3 << 25)
-#define OMAP4_LPDDR2IO1_GR3_SR_SHIFT                            22
-#define OMAP4_LPDDR2IO1_GR3_SR_MASK                             (0x3 << 22)
-#define OMAP4_LPDDR2IO1_GR3_I_SHIFT                             19
-#define OMAP4_LPDDR2IO1_GR3_I_MASK                              (0x7 << 19)
-#define OMAP4_LPDDR2IO1_GR3_WD_SHIFT                            17
-#define OMAP4_LPDDR2IO1_GR3_WD_MASK                             (0x3 << 17)
-#define OMAP4_LPDDR2IO1_GR2_SR_SHIFT                            14
-#define OMAP4_LPDDR2IO1_GR2_SR_MASK                             (0x3 << 14)
-#define OMAP4_LPDDR2IO1_GR2_I_SHIFT                             11
-#define OMAP4_LPDDR2IO1_GR2_I_MASK                              (0x7 << 11)
-#define OMAP4_LPDDR2IO1_GR2_WD_SHIFT                            9
-#define OMAP4_LPDDR2IO1_GR2_WD_MASK                             (0x3 << 9)
-#define OMAP4_LPDDR2IO1_GR1_SR_SHIFT                            6
-#define OMAP4_LPDDR2IO1_GR1_SR_MASK                             (0x3 << 6)
-#define OMAP4_LPDDR2IO1_GR1_I_SHIFT                             3
-#define OMAP4_LPDDR2IO1_GR1_I_MASK                              (0x7 << 3)
-#define OMAP4_LPDDR2IO1_GR1_WD_SHIFT                            1
-#define OMAP4_LPDDR2IO1_GR1_WD_MASK                             (0x3 << 1)
-
-/* CONTROL_LPDDR2IO1_1 */
-#define OMAP4_LPDDR2IO1_GR8_SR_SHIFT                            30
-#define OMAP4_LPDDR2IO1_GR8_SR_MASK                             (0x3 << 30)
-#define OMAP4_LPDDR2IO1_GR8_I_SHIFT                             27
-#define OMAP4_LPDDR2IO1_GR8_I_MASK                              (0x7 << 27)
-#define OMAP4_LPDDR2IO1_GR8_WD_SHIFT                            25
-#define OMAP4_LPDDR2IO1_GR8_WD_MASK                             (0x3 << 25)
-#define OMAP4_LPDDR2IO1_GR7_SR_SHIFT                            22
-#define OMAP4_LPDDR2IO1_GR7_SR_MASK                             (0x3 << 22)
-#define OMAP4_LPDDR2IO1_GR7_I_SHIFT                             19
-#define OMAP4_LPDDR2IO1_GR7_I_MASK                              (0x7 << 19)
-#define OMAP4_LPDDR2IO1_GR7_WD_SHIFT                            17
-#define OMAP4_LPDDR2IO1_GR7_WD_MASK                             (0x3 << 17)
-#define OMAP4_LPDDR2IO1_GR6_SR_SHIFT                            14
-#define OMAP4_LPDDR2IO1_GR6_SR_MASK                             (0x3 << 14)
-#define OMAP4_LPDDR2IO1_GR6_I_SHIFT                             11
-#define OMAP4_LPDDR2IO1_GR6_I_MASK                              (0x7 << 11)
-#define OMAP4_LPDDR2IO1_GR6_WD_SHIFT                            9
-#define OMAP4_LPDDR2IO1_GR6_WD_MASK                             (0x3 << 9)
-#define OMAP4_LPDDR2IO1_GR5_SR_SHIFT                            6
-#define OMAP4_LPDDR2IO1_GR5_SR_MASK                             (0x3 << 6)
-#define OMAP4_LPDDR2IO1_GR5_I_SHIFT                             3
-#define OMAP4_LPDDR2IO1_GR5_I_MASK                              (0x7 << 3)
-#define OMAP4_LPDDR2IO1_GR5_WD_SHIFT                            1
-#define OMAP4_LPDDR2IO1_GR5_WD_MASK                             (0x3 << 1)
-
-/* CONTROL_LPDDR2IO1_2 */
-#define OMAP4_LPDDR2IO1_GR11_SR_SHIFT                           30
-#define OMAP4_LPDDR2IO1_GR11_SR_MASK                            (0x3 << 30)
-#define OMAP4_LPDDR2IO1_GR11_I_SHIFT                            27
-#define OMAP4_LPDDR2IO1_GR11_I_MASK                             (0x7 << 27)
-#define OMAP4_LPDDR2IO1_GR11_WD_SHIFT                           25
-#define OMAP4_LPDDR2IO1_GR11_WD_MASK                            (0x3 << 25)
-#define OMAP4_LPDDR2IO1_GR10_SR_SHIFT                           22
-#define OMAP4_LPDDR2IO1_GR10_SR_MASK                            (0x3 << 22)
-#define OMAP4_LPDDR2IO1_GR10_I_SHIFT                            19
-#define OMAP4_LPDDR2IO1_GR10_I_MASK                             (0x7 << 19)
-#define OMAP4_LPDDR2IO1_GR10_WD_SHIFT                           17
-#define OMAP4_LPDDR2IO1_GR10_WD_MASK                            (0x3 << 17)
-#define OMAP4_LPDDR2IO1_GR9_SR_SHIFT                            14
-#define OMAP4_LPDDR2IO1_GR9_SR_MASK                             (0x3 << 14)
-#define OMAP4_LPDDR2IO1_GR9_I_SHIFT                             11
-#define OMAP4_LPDDR2IO1_GR9_I_MASK                              (0x7 << 11)
-#define OMAP4_LPDDR2IO1_GR9_WD_SHIFT                            9
-#define OMAP4_LPDDR2IO1_GR9_WD_MASK                             (0x3 << 9)
-
-/* CONTROL_LPDDR2IO1_3 */
-#define OMAP4_LPDDR21_VREF_CA_CCAP0_SHIFT                       31
-#define OMAP4_LPDDR21_VREF_CA_CCAP0_MASK                        (1 << 31)
-#define OMAP4_LPDDR21_VREF_CA_CCAP1_SHIFT                       30
-#define OMAP4_LPDDR21_VREF_CA_CCAP1_MASK                        (1 << 30)
-#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_SHIFT                   29
-#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_MASK                    (1 << 29)
-#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_SHIFT                   28
-#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_MASK                    (1 << 28)
-#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_SHIFT                    27
-#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_MASK                     (1 << 27)
-#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_SHIFT                    26
-#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_MASK                     (1 << 26)
-#define OMAP4_LPDDR21_VREF_CA_TAP0_SHIFT                        25
-#define OMAP4_LPDDR21_VREF_CA_TAP0_MASK                         (1 << 25)
-#define OMAP4_LPDDR21_VREF_CA_TAP1_SHIFT                        24
-#define OMAP4_LPDDR21_VREF_CA_TAP1_MASK                         (1 << 24)
-#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_SHIFT                  23
-#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_MASK                   (1 << 23)
-#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_SHIFT                  22
-#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_MASK                   (1 << 22)
-#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_SHIFT                   21
-#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_MASK                    (1 << 21)
-#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_SHIFT                   20
-#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_MASK                    (1 << 20)
-#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_SHIFT                  19
-#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_MASK                   (1 << 19)
-#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_SHIFT                  18
-#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_MASK                   (1 << 18)
-#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_SHIFT                   17
-#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_MASK                    (1 << 17)
-#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_SHIFT                   16
-#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_MASK                    (1 << 16)
-#define OMAP4_LPDDR21_VREF_DQ_CCAP0_SHIFT                       15
-#define OMAP4_LPDDR21_VREF_DQ_CCAP0_MASK                        (1 << 15)
-#define OMAP4_LPDDR21_VREF_DQ_CCAP1_SHIFT                       14
-#define OMAP4_LPDDR21_VREF_DQ_CCAP1_MASK                        (1 << 14)
-#define OMAP4_LPDDR21_VREF_DQ_TAP0_SHIFT                        13
-#define OMAP4_LPDDR21_VREF_DQ_TAP0_MASK                         (1 << 13)
-#define OMAP4_LPDDR21_VREF_DQ_TAP1_SHIFT                        12
-#define OMAP4_LPDDR21_VREF_DQ_TAP1_MASK                         (1 << 12)
-
-/* CONTROL_LPDDR2IO2_0 */
-#define OMAP4_LPDDR2IO2_GR4_SR_SHIFT                            30
-#define OMAP4_LPDDR2IO2_GR4_SR_MASK                             (0x3 << 30)
-#define OMAP4_LPDDR2IO2_GR4_I_SHIFT                             27
-#define OMAP4_LPDDR2IO2_GR4_I_MASK                              (0x7 << 27)
-#define OMAP4_LPDDR2IO2_GR4_WD_SHIFT                            25
-#define OMAP4_LPDDR2IO2_GR4_WD_MASK                             (0x3 << 25)
-#define OMAP4_LPDDR2IO2_GR3_SR_SHIFT                            22
-#define OMAP4_LPDDR2IO2_GR3_SR_MASK                             (0x3 << 22)
-#define OMAP4_LPDDR2IO2_GR3_I_SHIFT                             19
-#define OMAP4_LPDDR2IO2_GR3_I_MASK                              (0x7 << 19)
-#define OMAP4_LPDDR2IO2_GR3_WD_SHIFT                            17
-#define OMAP4_LPDDR2IO2_GR3_WD_MASK                             (0x3 << 17)
-#define OMAP4_LPDDR2IO2_GR2_SR_SHIFT                            14
-#define OMAP4_LPDDR2IO2_GR2_SR_MASK                             (0x3 << 14)
-#define OMAP4_LPDDR2IO2_GR2_I_SHIFT                             11
-#define OMAP4_LPDDR2IO2_GR2_I_MASK                              (0x7 << 11)
-#define OMAP4_LPDDR2IO2_GR2_WD_SHIFT                            9
-#define OMAP4_LPDDR2IO2_GR2_WD_MASK                             (0x3 << 9)
-#define OMAP4_LPDDR2IO2_GR1_SR_SHIFT                            6
-#define OMAP4_LPDDR2IO2_GR1_SR_MASK                             (0x3 << 6)
-#define OMAP4_LPDDR2IO2_GR1_I_SHIFT                             3
-#define OMAP4_LPDDR2IO2_GR1_I_MASK                              (0x7 << 3)
-#define OMAP4_LPDDR2IO2_GR1_WD_SHIFT                            1
-#define OMAP4_LPDDR2IO2_GR1_WD_MASK                             (0x3 << 1)
-
-/* CONTROL_LPDDR2IO2_1 */
-#define OMAP4_LPDDR2IO2_GR8_SR_SHIFT                            30
-#define OMAP4_LPDDR2IO2_GR8_SR_MASK                             (0x3 << 30)
-#define OMAP4_LPDDR2IO2_GR8_I_SHIFT                             27
-#define OMAP4_LPDDR2IO2_GR8_I_MASK                              (0x7 << 27)
-#define OMAP4_LPDDR2IO2_GR8_WD_SHIFT                            25
-#define OMAP4_LPDDR2IO2_GR8_WD_MASK                             (0x3 << 25)
-#define OMAP4_LPDDR2IO2_GR7_SR_SHIFT                            22
-#define OMAP4_LPDDR2IO2_GR7_SR_MASK                             (0x3 << 22)
-#define OMAP4_LPDDR2IO2_GR7_I_SHIFT                             19
-#define OMAP4_LPDDR2IO2_GR7_I_MASK                              (0x7 << 19)
-#define OMAP4_LPDDR2IO2_GR7_WD_SHIFT                            17
-#define OMAP4_LPDDR2IO2_GR7_WD_MASK                             (0x3 << 17)
-#define OMAP4_LPDDR2IO2_GR6_SR_SHIFT                            14
-#define OMAP4_LPDDR2IO2_GR6_SR_MASK                             (0x3 << 14)
-#define OMAP4_LPDDR2IO2_GR6_I_SHIFT                             11
-#define OMAP4_LPDDR2IO2_GR6_I_MASK                              (0x7 << 11)
-#define OMAP4_LPDDR2IO2_GR6_WD_SHIFT                            9
-#define OMAP4_LPDDR2IO2_GR6_WD_MASK                             (0x3 << 9)
-#define OMAP4_LPDDR2IO2_GR5_SR_SHIFT                            6
-#define OMAP4_LPDDR2IO2_GR5_SR_MASK                             (0x3 << 6)
-#define OMAP4_LPDDR2IO2_GR5_I_SHIFT                             3
-#define OMAP4_LPDDR2IO2_GR5_I_MASK                              (0x7 << 3)
-#define OMAP4_LPDDR2IO2_GR5_WD_SHIFT                            1
-#define OMAP4_LPDDR2IO2_GR5_WD_MASK                             (0x3 << 1)
-
-/* CONTROL_LPDDR2IO2_2 */
-#define OMAP4_LPDDR2IO2_GR11_SR_SHIFT                           30
-#define OMAP4_LPDDR2IO2_GR11_SR_MASK                            (0x3 << 30)
-#define OMAP4_LPDDR2IO2_GR11_I_SHIFT                            27
-#define OMAP4_LPDDR2IO2_GR11_I_MASK                             (0x7 << 27)
-#define OMAP4_LPDDR2IO2_GR11_WD_SHIFT                           25
-#define OMAP4_LPDDR2IO2_GR11_WD_MASK                            (0x3 << 25)
-#define OMAP4_LPDDR2IO2_GR10_SR_SHIFT                           22
-#define OMAP4_LPDDR2IO2_GR10_SR_MASK                            (0x3 << 22)
-#define OMAP4_LPDDR2IO2_GR10_I_SHIFT                            19
-#define OMAP4_LPDDR2IO2_GR10_I_MASK                             (0x7 << 19)
-#define OMAP4_LPDDR2IO2_GR10_WD_SHIFT                           17
-#define OMAP4_LPDDR2IO2_GR10_WD_MASK                            (0x3 << 17)
-#define OMAP4_LPDDR2IO2_GR9_SR_SHIFT                            14
-#define OMAP4_LPDDR2IO2_GR9_SR_MASK                             (0x3 << 14)
-#define OMAP4_LPDDR2IO2_GR9_I_SHIFT                             11
-#define OMAP4_LPDDR2IO2_GR9_I_MASK                              (0x7 << 11)
-#define OMAP4_LPDDR2IO2_GR9_WD_SHIFT                            9
-#define OMAP4_LPDDR2IO2_GR9_WD_MASK                             (0x3 << 9)
-
-/* CONTROL_LPDDR2IO2_3 */
-#define OMAP4_LPDDR22_VREF_CA_CCAP0_SHIFT                       31
-#define OMAP4_LPDDR22_VREF_CA_CCAP0_MASK                        (1 << 31)
-#define OMAP4_LPDDR22_VREF_CA_CCAP1_SHIFT                       30
-#define OMAP4_LPDDR22_VREF_CA_CCAP1_MASK                        (1 << 30)
-#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_SHIFT                   29
-#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_MASK                    (1 << 29)
-#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_SHIFT                   28
-#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_MASK                    (1 << 28)
-#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_SHIFT                    27
-#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_MASK                     (1 << 27)
-#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_SHIFT                    26
-#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_MASK                     (1 << 26)
-#define OMAP4_LPDDR22_VREF_CA_TAP0_SHIFT                        25
-#define OMAP4_LPDDR22_VREF_CA_TAP0_MASK                         (1 << 25)
-#define OMAP4_LPDDR22_VREF_CA_TAP1_SHIFT                        24
-#define OMAP4_LPDDR22_VREF_CA_TAP1_MASK                         (1 << 24)
-#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_SHIFT                  23
-#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_MASK                   (1 << 23)
-#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_SHIFT                  22
-#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_MASK                   (1 << 22)
-#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_SHIFT                   21
-#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_MASK                    (1 << 21)
-#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_SHIFT                   20
-#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_MASK                    (1 << 20)
-#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_SHIFT                  19
-#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_MASK                   (1 << 19)
-#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_SHIFT                  18
-#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_MASK                   (1 << 18)
-#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_SHIFT                   17
-#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_MASK                    (1 << 17)
-#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_SHIFT                   16
-#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_MASK                    (1 << 16)
-#define OMAP4_LPDDR22_VREF_DQ_CCAP0_SHIFT                       15
-#define OMAP4_LPDDR22_VREF_DQ_CCAP0_MASK                        (1 << 15)
-#define OMAP4_LPDDR22_VREF_DQ_CCAP1_SHIFT                       14
-#define OMAP4_LPDDR22_VREF_DQ_CCAP1_MASK                        (1 << 14)
-#define OMAP4_LPDDR22_VREF_DQ_TAP0_SHIFT                        13
-#define OMAP4_LPDDR22_VREF_DQ_TAP0_MASK                         (1 << 13)
-#define OMAP4_LPDDR22_VREF_DQ_TAP1_SHIFT                        12
-#define OMAP4_LPDDR22_VREF_DQ_TAP1_MASK                         (1 << 12)
-
-/* CONTROL_BUS_HOLD */
-#define OMAP4_ABE_DMIC_DIN3_EN_SHIFT                            31
-#define OMAP4_ABE_DMIC_DIN3_EN_MASK                             (1 << 31)
-#define OMAP4_MCSPI1_CS3_EN_SHIFT                               30
-#define OMAP4_MCSPI1_CS3_EN_MASK                                (1 << 30)
-
-/* CONTROL_C2C */
-#define OMAP4_MIRROR_MODE_EN_SHIFT                              31
-#define OMAP4_MIRROR_MODE_EN_MASK                               (1 << 31)
-#define OMAP4_C2C_SPARE_SHIFT                                   24
-#define OMAP4_C2C_SPARE_MASK                                    (0x7f << 24)
-
-/* CORE_CONTROL_SPARE_RW */
-#define OMAP4_CORE_CONTROL_SPARE_RW_SHIFT                       0
-#define OMAP4_CORE_CONTROL_SPARE_RW_MASK                        (0xffffffff << 0)
-
-/* CORE_CONTROL_SPARE_R */
-#define OMAP4_CORE_CONTROL_SPARE_R_SHIFT                        0
-#define OMAP4_CORE_CONTROL_SPARE_R_MASK                         (0xffffffff << 0)
-
-/* CORE_CONTROL_SPARE_R_C0 */
-#define OMAP4_CORE_CONTROL_SPARE_R_C0_SHIFT                     31
-#define OMAP4_CORE_CONTROL_SPARE_R_C0_MASK                      (1 << 31)
-#define OMAP4_CORE_CONTROL_SPARE_R_C1_SHIFT                     30
-#define OMAP4_CORE_CONTROL_SPARE_R_C1_MASK                      (1 << 30)
-#define OMAP4_CORE_CONTROL_SPARE_R_C2_SHIFT                     29
-#define OMAP4_CORE_CONTROL_SPARE_R_C2_MASK                      (1 << 29)
-#define OMAP4_CORE_CONTROL_SPARE_R_C3_SHIFT                     28
-#define OMAP4_CORE_CONTROL_SPARE_R_C3_MASK                      (1 << 28)
-#define OMAP4_CORE_CONTROL_SPARE_R_C4_SHIFT                     27
-#define OMAP4_CORE_CONTROL_SPARE_R_C4_MASK                      (1 << 27)
-#define OMAP4_CORE_CONTROL_SPARE_R_C5_SHIFT                     26
-#define OMAP4_CORE_CONTROL_SPARE_R_C5_MASK                      (1 << 26)
-#define OMAP4_CORE_CONTROL_SPARE_R_C6_SHIFT                     25
-#define OMAP4_CORE_CONTROL_SPARE_R_C6_MASK                      (1 << 25)
-#define OMAP4_CORE_CONTROL_SPARE_R_C7_SHIFT                     24
-#define OMAP4_CORE_CONTROL_SPARE_R_C7_MASK                      (1 << 24)
-
-/* CONTROL_EFUSE_1 */
-#define OMAP4_AVDAC_TRIM_BYTE3_SHIFT                            24
-#define OMAP4_AVDAC_TRIM_BYTE3_MASK                             (0x7f << 24)
-#define OMAP4_AVDAC_TRIM_BYTE2_SHIFT                            16
-#define OMAP4_AVDAC_TRIM_BYTE2_MASK                             (0xff << 16)
-#define OMAP4_AVDAC_TRIM_BYTE1_SHIFT                            8
-#define OMAP4_AVDAC_TRIM_BYTE1_MASK                             (0xff << 8)
-#define OMAP4_AVDAC_TRIM_BYTE0_SHIFT                            0
-#define OMAP4_AVDAC_TRIM_BYTE0_MASK                             (0xff << 0)
-
-/* CONTROL_EFUSE_2 */
-#define OMAP4_EFUSE_SMART2TEST_P0_SHIFT                         31
-#define OMAP4_EFUSE_SMART2TEST_P0_MASK                          (1 << 31)
-#define OMAP4_EFUSE_SMART2TEST_P1_SHIFT                         30
-#define OMAP4_EFUSE_SMART2TEST_P1_MASK                          (1 << 30)
-#define OMAP4_EFUSE_SMART2TEST_P2_SHIFT                         29
-#define OMAP4_EFUSE_SMART2TEST_P2_MASK                          (1 << 29)
-#define OMAP4_EFUSE_SMART2TEST_P3_SHIFT                         28
-#define OMAP4_EFUSE_SMART2TEST_P3_MASK                          (1 << 28)
-#define OMAP4_EFUSE_SMART2TEST_N0_SHIFT                         27
-#define OMAP4_EFUSE_SMART2TEST_N0_MASK                          (1 << 27)
-#define OMAP4_EFUSE_SMART2TEST_N1_SHIFT                         26
-#define OMAP4_EFUSE_SMART2TEST_N1_MASK                          (1 << 26)
-#define OMAP4_EFUSE_SMART2TEST_N2_SHIFT                         25
-#define OMAP4_EFUSE_SMART2TEST_N2_MASK                          (1 << 25)
-#define OMAP4_EFUSE_SMART2TEST_N3_SHIFT                         24
-#define OMAP4_EFUSE_SMART2TEST_N3_MASK                          (1 << 24)
-#define OMAP4_LPDDR2_PTV_N1_SHIFT                               23
-#define OMAP4_LPDDR2_PTV_N1_MASK                                (1 << 23)
-#define OMAP4_LPDDR2_PTV_N2_SHIFT                               22
-#define OMAP4_LPDDR2_PTV_N2_MASK                                (1 << 22)
-#define OMAP4_LPDDR2_PTV_N3_SHIFT                               21
-#define OMAP4_LPDDR2_PTV_N3_MASK                                (1 << 21)
-#define OMAP4_LPDDR2_PTV_N4_SHIFT                               20
-#define OMAP4_LPDDR2_PTV_N4_MASK                                (1 << 20)
-#define OMAP4_LPDDR2_PTV_N5_SHIFT                               19
-#define OMAP4_LPDDR2_PTV_N5_MASK                                (1 << 19)
-#define OMAP4_LPDDR2_PTV_P1_SHIFT                               18
-#define OMAP4_LPDDR2_PTV_P1_MASK                                (1 << 18)
-#define OMAP4_LPDDR2_PTV_P2_SHIFT                               17
-#define OMAP4_LPDDR2_PTV_P2_MASK                                (1 << 17)
-#define OMAP4_LPDDR2_PTV_P3_SHIFT                               16
-#define OMAP4_LPDDR2_PTV_P3_MASK                                (1 << 16)
-#define OMAP4_LPDDR2_PTV_P4_SHIFT                               15
-#define OMAP4_LPDDR2_PTV_P4_MASK                                (1 << 15)
-#define OMAP4_LPDDR2_PTV_P5_SHIFT                               14
-#define OMAP4_LPDDR2_PTV_P5_MASK                                (1 << 14)
-
-/* CONTROL_EFUSE_3 */
-#define OMAP4_STD_FUSE_SPARE_1_SHIFT                            24
-#define OMAP4_STD_FUSE_SPARE_1_MASK                             (0xff << 24)
-#define OMAP4_STD_FUSE_SPARE_2_SHIFT                            16
-#define OMAP4_STD_FUSE_SPARE_2_MASK                             (0xff << 16)
-#define OMAP4_STD_FUSE_SPARE_3_SHIFT                            8
-#define OMAP4_STD_FUSE_SPARE_3_MASK                             (0xff << 8)
-#define OMAP4_STD_FUSE_SPARE_4_SHIFT                            0
-#define OMAP4_STD_FUSE_SPARE_4_MASK                             (0xff << 0)
-
-/* CONTROL_EFUSE_4 */
-#define OMAP4_STD_FUSE_SPARE_5_SHIFT                            24
-#define OMAP4_STD_FUSE_SPARE_5_MASK                             (0xff << 24)
-#define OMAP4_STD_FUSE_SPARE_6_SHIFT                            16
-#define OMAP4_STD_FUSE_SPARE_6_MASK                             (0xff << 16)
-#define OMAP4_STD_FUSE_SPARE_7_SHIFT                            8
-#define OMAP4_STD_FUSE_SPARE_7_MASK                             (0xff << 8)
-#define OMAP4_STD_FUSE_SPARE_8_SHIFT                            0
-#define OMAP4_STD_FUSE_SPARE_8_MASK                             (0xff << 0)
-
-#endif
diff --git a/arch/arm/mach-omap2/ctrl_module_pad_wkup_44xx.h b/arch/arm/mach-omap2/ctrl_module_pad_wkup_44xx.h
deleted file mode 100644
index 17c9b37042c0..000000000000
--- a/arch/arm/mach-omap2/ctrl_module_pad_wkup_44xx.h
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * OMAP44xx CTRL_MODULE_PAD_WKUP registers and bitfields
- *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
- *
- * Benoit Cousson (b-cousson@ti.com)
- * Santosh Shilimkar (santosh.shilimkar@ti.com)
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap@vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
-#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
-
-
-/* Base address */
-#define OMAP4_CTRL_MODULE_PAD_WKUP                                      0x4a31e000
-
-/* Registers offset */
-#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_REVISION                          0x0000
-#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_HWINFO                            0x0004
-#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_SYSCONFIG                         0x0010
-#define OMAP4_CTRL_MODULE_PAD_WKUP_PADCONF_WAKEUPEVENT_0                0x007c
-#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_0       0x05a0
-#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_1       0x05a4
-#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_PADCONF_MODE                 0x05a8
-#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_XTAL_OSCILLATOR              0x05ac
-#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_USIMIO                       0x0600
-#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2                        0x0604
-#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_JTAG                         0x0608
-#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SYS                          0x060c
-#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_RW                0x0614
-#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R                 0x0618
-#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R_C0              0x061c
-
-/* Registers shifts and masks */
-
-/* IP_REVISION */
-#define OMAP4_IP_REV_SCHEME_SHIFT                               30
-#define OMAP4_IP_REV_SCHEME_MASK                                (0x3 << 30)
-#define OMAP4_IP_REV_FUNC_SHIFT                                 16
-#define OMAP4_IP_REV_FUNC_MASK                                  (0xfff << 16)
-#define OMAP4_IP_REV_RTL_SHIFT                                  11
-#define OMAP4_IP_REV_RTL_MASK                                   (0x1f << 11)
-#define OMAP4_IP_REV_MAJOR_SHIFT                                8
-#define OMAP4_IP_REV_MAJOR_MASK                                 (0x7 << 8)
-#define OMAP4_IP_REV_CUSTOM_SHIFT                               6
-#define OMAP4_IP_REV_CUSTOM_MASK                                (0x3 << 6)
-#define OMAP4_IP_REV_MINOR_SHIFT                                0
-#define OMAP4_IP_REV_MINOR_MASK                                 (0x3f << 0)
-
-/* IP_HWINFO */
-#define OMAP4_IP_HWINFO_SHIFT                                   0
-#define OMAP4_IP_HWINFO_MASK                                    (0xffffffff << 0)
-
-/* IP_SYSCONFIG */
-#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT                       2
-#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK                        (0x3 << 2)
-
-/* PADCONF_WAKEUPEVENT_0 */
-#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_SHIFT               24
-#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_MASK                (1 << 24)
-#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_SHIFT               23
-#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_MASK                (1 << 23)
-#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_SHIFT          22
-#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_MASK           (1 << 22)
-#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_SHIFT              21
-#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_MASK               (1 << 21)
-#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_SHIFT               20
-#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_MASK                (1 << 20)
-#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_SHIFT             19
-#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_MASK              (1 << 19)
-#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_SHIFT              18
-#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_MASK               (1 << 18)
-#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_SHIFT              17
-#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_MASK               (1 << 17)
-#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_SHIFT    16
-#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_MASK     (1 << 16)
-#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_SHIFT            15
-#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_MASK             (1 << 15)
-#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_SHIFT           14
-#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_MASK            (1 << 14)
-#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_SHIFT                13
-#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_MASK                 (1 << 13)
-#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_SHIFT          12
-#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_MASK           (1 << 12)
-#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_SHIFT          11
-#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_MASK           (1 << 11)
-#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_SHIFT          10
-#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_MASK           (1 << 10)
-#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_SHIFT          9
-#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_MASK           (1 << 9)
-#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_SHIFT          8
-#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_MASK           (1 << 8)
-#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_SHIFT         7
-#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_MASK          (1 << 7)
-#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_SHIFT                 6
-#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_MASK                  (1 << 6)
-#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_SHIFT                 5
-#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_MASK                  (1 << 5)
-#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_SHIFT            4
-#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_MASK             (1 << 4)
-#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_SHIFT                 3
-#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_MASK                  (1 << 3)
-#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_SHIFT              2
-#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_MASK               (1 << 2)
-#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_SHIFT                1
-#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_MASK                 (1 << 1)
-#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_SHIFT                 0
-#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_MASK                  (1 << 0)
-
-/* CONTROL_SMART1NOPMIO_PADCONF_0 */
-#define OMAP4_FREF_DR0_SC_SHIFT                                 30
-#define OMAP4_FREF_DR0_SC_MASK                                  (0x3 << 30)
-#define OMAP4_FREF_DR1_SC_SHIFT                                 28
-#define OMAP4_FREF_DR1_SC_MASK                                  (0x3 << 28)
-#define OMAP4_FREF_DR4_SC_SHIFT                                 26
-#define OMAP4_FREF_DR4_SC_MASK                                  (0x3 << 26)
-#define OMAP4_FREF_DR5_SC_SHIFT                                 24
-#define OMAP4_FREF_DR5_SC_MASK                                  (0x3 << 24)
-#define OMAP4_FREF_DR6_SC_SHIFT                                 22
-#define OMAP4_FREF_DR6_SC_MASK                                  (0x3 << 22)
-#define OMAP4_FREF_DR7_SC_SHIFT                                 20
-#define OMAP4_FREF_DR7_SC_MASK                                  (0x3 << 20)
-#define OMAP4_GPIO_DR7_SC_SHIFT                                 18
-#define OMAP4_GPIO_DR7_SC_MASK                                  (0x3 << 18)
-#define OMAP4_DPM_DR0_SC_SHIFT                                  14
-#define OMAP4_DPM_DR0_SC_MASK                                   (0x3 << 14)
-#define OMAP4_SIM_DR0_SC_SHIFT                                  12
-#define OMAP4_SIM_DR0_SC_MASK                                   (0x3 << 12)
-
-/* CONTROL_SMART1NOPMIO_PADCONF_1 */
-#define OMAP4_FREF_DR0_LB_SHIFT                                 30
-#define OMAP4_FREF_DR0_LB_MASK                                  (0x3 << 30)
-#define OMAP4_FREF_DR1_LB_SHIFT                                 28
-#define OMAP4_FREF_DR1_LB_MASK                                  (0x3 << 28)
-#define OMAP4_FREF_DR4_LB_SHIFT                                 26
-#define OMAP4_FREF_DR4_LB_MASK                                  (0x3 << 26)
-#define OMAP4_FREF_DR5_LB_SHIFT                                 24
-#define OMAP4_FREF_DR5_LB_MASK                                  (0x3 << 24)
-#define OMAP4_FREF_DR6_LB_SHIFT                                 22
-#define OMAP4_FREF_DR6_LB_MASK                                  (0x3 << 22)
-#define OMAP4_FREF_DR7_LB_SHIFT                                 20
-#define OMAP4_FREF_DR7_LB_MASK                                  (0x3 << 20)
-#define OMAP4_GPIO_DR7_LB_SHIFT                                 18
-#define OMAP4_GPIO_DR7_LB_MASK                                  (0x3 << 18)
-#define OMAP4_DPM_DR0_LB_SHIFT                                  14
-#define OMAP4_DPM_DR0_LB_MASK                                   (0x3 << 14)
-#define OMAP4_SIM_DR0_LB_SHIFT                                  12
-#define OMAP4_SIM_DR0_LB_MASK                                   (0x3 << 12)
-
-/* CONTROL_PADCONF_MODE */
-#define OMAP4_VDDS_DV_FREF_SHIFT                                31
-#define OMAP4_VDDS_DV_FREF_MASK                                 (1 << 31)
-#define OMAP4_VDDS_DV_BANK2_SHIFT                               30
-#define OMAP4_VDDS_DV_BANK2_MASK                                (1 << 30)
-
-/* CONTROL_XTAL_OSCILLATOR */
-#define OMAP4_OSCILLATOR_BOOST_SHIFT                            31
-#define OMAP4_OSCILLATOR_BOOST_MASK                             (1 << 31)
-#define OMAP4_OSCILLATOR_OS_OUT_SHIFT                           30
-#define OMAP4_OSCILLATOR_OS_OUT_MASK                            (1 << 30)
-
-/* CONTROL_USIMIO */
-#define OMAP4_PAD_USIM_CLK_LOW_SHIFT                            31
-#define OMAP4_PAD_USIM_CLK_LOW_MASK                             (1 << 31)
-#define OMAP4_PAD_USIM_RST_LOW_SHIFT                            29
-#define OMAP4_PAD_USIM_RST_LOW_MASK                             (1 << 29)
-#define OMAP4_USIM_PWRDNZ_SHIFT                                 28
-#define OMAP4_USIM_PWRDNZ_MASK                                  (1 << 28)
-
-/* CONTROL_I2C_2 */
-#define OMAP4_SR_SDA_GLFENB_SHIFT                               31
-#define OMAP4_SR_SDA_GLFENB_MASK                                (1 << 31)
-#define OMAP4_SR_SDA_LOAD_BITS_SHIFT                            29
-#define OMAP4_SR_SDA_LOAD_BITS_MASK                             (0x3 << 29)
-#define OMAP4_SR_SDA_PULLUPRESX_SHIFT                           28
-#define OMAP4_SR_SDA_PULLUPRESX_MASK                            (1 << 28)
-#define OMAP4_SR_SCL_GLFENB_SHIFT                               27
-#define OMAP4_SR_SCL_GLFENB_MASK                                (1 << 27)
-#define OMAP4_SR_SCL_LOAD_BITS_SHIFT                            25
-#define OMAP4_SR_SCL_LOAD_BITS_MASK                             (0x3 << 25)
-#define OMAP4_SR_SCL_PULLUPRESX_SHIFT                           24
-#define OMAP4_SR_SCL_PULLUPRESX_MASK                            (1 << 24)
-
-/* CONTROL_JTAG */
-#define OMAP4_JTAG_NTRST_EN_SHIFT                               31
-#define OMAP4_JTAG_NTRST_EN_MASK                                (1 << 31)
-#define OMAP4_JTAG_TCK_EN_SHIFT                                 30
-#define OMAP4_JTAG_TCK_EN_MASK                                  (1 << 30)
-#define OMAP4_JTAG_RTCK_EN_SHIFT                                29
-#define OMAP4_JTAG_RTCK_EN_MASK                                 (1 << 29)
-#define OMAP4_JTAG_TDI_EN_SHIFT                                 28
-#define OMAP4_JTAG_TDI_EN_MASK                                  (1 << 28)
-#define OMAP4_JTAG_TDO_EN_SHIFT                                 27
-#define OMAP4_JTAG_TDO_EN_MASK                                  (1 << 27)
-
-/* CONTROL_SYS */
-#define OMAP4_SYS_NRESWARM_PIPU_SHIFT                           31
-#define OMAP4_SYS_NRESWARM_PIPU_MASK                            (1 << 31)
-
-/* WKUP_CONTROL_SPARE_RW */
-#define OMAP4_WKUP_CONTROL_SPARE_RW_SHIFT                       0
-#define OMAP4_WKUP_CONTROL_SPARE_RW_MASK                        (0xffffffff << 0)
-
-/* WKUP_CONTROL_SPARE_R */
-#define OMAP4_WKUP_CONTROL_SPARE_R_SHIFT                        0
-#define OMAP4_WKUP_CONTROL_SPARE_R_MASK                         (0xffffffff << 0)
-
-/* WKUP_CONTROL_SPARE_R_C0 */
-#define OMAP4_WKUP_CONTROL_SPARE_R_C0_SHIFT                     31
-#define OMAP4_WKUP_CONTROL_SPARE_R_C0_MASK                      (1 << 31)
-#define OMAP4_WKUP_CONTROL_SPARE_R_C1_SHIFT                     30
-#define OMAP4_WKUP_CONTROL_SPARE_R_C1_MASK                      (1 << 30)
-#define OMAP4_WKUP_CONTROL_SPARE_R_C2_SHIFT                     29
-#define OMAP4_WKUP_CONTROL_SPARE_R_C2_MASK                      (1 << 29)
-#define OMAP4_WKUP_CONTROL_SPARE_R_C3_SHIFT                     28
-#define OMAP4_WKUP_CONTROL_SPARE_R_C3_MASK                      (1 << 28)
-#define OMAP4_WKUP_CONTROL_SPARE_R_C4_SHIFT                     27
-#define OMAP4_WKUP_CONTROL_SPARE_R_C4_MASK                      (1 << 27)
-#define OMAP4_WKUP_CONTROL_SPARE_R_C5_SHIFT                     26
-#define OMAP4_WKUP_CONTROL_SPARE_R_C5_MASK                      (1 << 26)
-#define OMAP4_WKUP_CONTROL_SPARE_R_C6_SHIFT                     25
-#define OMAP4_WKUP_CONTROL_SPARE_R_C6_MASK                      (1 << 25)
-#define OMAP4_WKUP_CONTROL_SPARE_R_C7_SHIFT                     24
-#define OMAP4_WKUP_CONTROL_SPARE_R_C7_MASK                      (1 << 24)
-
-#endif
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 6d7ba37e2257..cd5f3a0b97bd 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -28,11 +28,8 @@
 #include <linux/bitops.h>
 #include <linux/clkdev.h>
 
-#include "soc.h"
 #include "clockdomain.h"
 #include "clock.h"
-#include "cm2xxx_3xxx.h"
-#include "cm-regbits-34xx.h"
 
 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
 #define DPLL_AUTOIDLE_DISABLE                   0x0
@@ -310,7 +307,7 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
          * Set jitter correction. Jitter correction applicable for OMAP343X
          * only since freqsel field is no longer present on other devices.
          */
-        if (cpu_is_omap343x()) {
+        if (ti_clk_features.flags & TI_CLK_DPLL_HAS_FREQSEL) {
                 v = omap2_clk_readl(clk, dd->control_reg);
                 v &= ~dd->freqsel_mask;
                 v |= freqsel << __ffs(dd->freqsel_mask);
@@ -512,7 +509,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
                         return -EINVAL;
 
                 /* Freqsel is available only on OMAP343X devices */
-                if (cpu_is_omap343x()) {
+                if (ti_clk_features.flags & TI_CLK_DPLL_HAS_FREQSEL) {
                         freqsel = _omap3_dpll_compute_freqsel(clk,
                                                 dd->last_rounded_n);
                         WARN_ON(!freqsel);
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
index 52f9438b92f2..4613f1e86988 100644
--- a/arch/arm/mach-omap2/dpll44xx.c
+++ b/arch/arm/mach-omap2/dpll44xx.c
@@ -15,10 +15,7 @@
 #include <linux/io.h>
 #include <linux/bitops.h>
 
-#include "soc.h"
 #include "clock.h"
-#include "clock44xx.h"
-#include "cm-regbits-44xx.h"
 
 /*
  * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that
@@ -29,13 +26,23 @@
 #define OMAP4_DPLL_LP_FINT_MAX  1000000
 #define OMAP4_DPLL_LP_FOUT_MAX  100000000
 
+/*
+ * Bitfield declarations
+ */
+#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK             (1 << 8)
+#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK           (1 << 10)
+#define OMAP4430_DPLL_REGM4XEN_MASK                     (1 << 11)
+
+/* Static rate multiplier for OMAP4 REGM4XEN clocks */
+#define OMAP4430_REGM4XEN_MULT                          4
+
 /* Supported only on OMAP4 */
 int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk)
 {
         u32 v;
         u32 mask;
 
-        if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
+        if (!clk || !clk->clksel_reg)
                 return -EINVAL;
 
         mask = clk->flags & CLOCK_CLKOUTX2 ?
@@ -54,7 +61,7 @@ void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)
         u32 v;
         u32 mask;
 
-        if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
+        if (!clk || !clk->clksel_reg)
                 return;
 
         mask = clk->flags & CLOCK_CLKOUTX2 ?
@@ -72,7 +79,7 @@ void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
         u32 v;
         u32 mask;
 
-        if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
+        if (!clk || !clk->clksel_reg)
                 return;
 
         mask = clk->flags & CLOCK_CLKOUTX2 ?
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 93914d220069..8897ad7035fd 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -24,25 +24,6 @@
 /* minimum size for IO mapping */
 #define NAND_IO_SIZE    4
 
-static struct resource gpmc_nand_resource[] = {
-        {
-                .flags          = IORESOURCE_MEM,
-        },
-        {
-                .flags          = IORESOURCE_IRQ,
-        },
-        {
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device gpmc_nand_device = {
-        .name           = "omap2-nand",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(gpmc_nand_resource),
-        .resource       = gpmc_nand_resource,
-};
-
 static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
 {
         /* platforms which support all ECC schemes */
@@ -95,43 +76,41 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
 {
         int err = 0;
         struct gpmc_settings s;
-        struct device *dev = &gpmc_nand_device.dev;
-
-        memset(&s, 0, sizeof(struct gpmc_settings));
+        struct platform_device *pdev;
+        struct resource gpmc_nand_res[] = {
+                { .flags = IORESOURCE_MEM, },
+                { .flags = IORESOURCE_IRQ, },
+                { .flags = IORESOURCE_IRQ, },
+        };
 
-        gpmc_nand_device.dev.platform_data = gpmc_nand_data;
+        BUG_ON(gpmc_nand_data->cs >= GPMC_CS_NUM);
 
         err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
-                                (unsigned long *)&gpmc_nand_resource[0].start);
+                              (unsigned long *)&gpmc_nand_res[0].start);
         if (err < 0) {
-                dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
-                        gpmc_nand_data->cs, err);
+                pr_err("omap2-gpmc: Cannot request GPMC CS %d, error %d\n",
+                       gpmc_nand_data->cs, err);
                 return err;
         }
-
-        gpmc_nand_resource[0].end = gpmc_nand_resource[0].start +
-                                                        NAND_IO_SIZE - 1;
-
-        gpmc_nand_resource[1].start =
-                                gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE);
-        gpmc_nand_resource[2].start =
-                                gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
+        gpmc_nand_res[0].end = gpmc_nand_res[0].start + NAND_IO_SIZE - 1;
+        gpmc_nand_res[1].start = gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE);
+        gpmc_nand_res[2].start = gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
 
         if (gpmc_t) {
                 err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t);
                 if (err < 0) {
-                        dev_err(dev, "Unable to set gpmc timings: %d\n", err);
+                        pr_err("omap2-gpmc: Unable to set gpmc timings: %d\n", err);
                         return err;
                 }
         }
 
+        memset(&s, 0, sizeof(struct gpmc_settings));
         if (gpmc_nand_data->of_node)
                 gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
         else
                 gpmc_set_legacy(gpmc_nand_data, &s);
 
         s.device_nand = true;
-
         err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s);
         if (err < 0)
                 goto out_free_cs;
@@ -143,18 +122,34 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
         gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
 
         if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) {
-                dev_err(dev, "Unsupported NAND ECC scheme selected\n");
-                return -EINVAL;
+                pr_err("omap2-nand: Unsupported NAND ECC scheme selected\n");
+                err = -EINVAL;
+                goto out_free_cs;
         }
 
-        err = platform_device_register(&gpmc_nand_device);
-        if (err < 0) {
-                dev_err(dev, "Unable to register NAND device\n");
-                goto out_free_cs;
+
+        pdev = platform_device_alloc("omap2-nand", gpmc_nand_data->cs);
+        if (pdev) {
+                err = platform_device_add_resources(pdev, gpmc_nand_res,
+                                                    ARRAY_SIZE(gpmc_nand_res));
+                if (!err)
+                        pdev->dev.platform_data = gpmc_nand_data;
+        } else {
+                err = -ENOMEM;
+        }
+        if (err)
+                goto out_free_pdev;
+
+        err = platform_device_add(pdev);
+        if (err) {
+                dev_err(&pdev->dev, "Unable to register NAND device\n");
+                goto out_free_pdev;
         }
 
         return 0;
 
+out_free_pdev:
+        platform_device_put(pdev);
 out_free_cs:
         gpmc_cs_free(gpmc_nand_data->cs);
 
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 8f559450c876..1fae5c123f79 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -728,6 +728,8 @@ int __init omap_clk_init(void)
         if (!omap_clk_soc_init)
                 return 0;
 
+        ti_clk_init_features();
+
         ret = of_prcm_init();
         if (!ret)
                 ret = omap_clk_soc_init();
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index a5ea988ff340..d76694b7a591 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -75,9 +75,9 @@ static int omap2_enter_full_retention(void)
 
         /* Clear old wake-up events */
         /* REVISIT: These write to reserved bits? */
-        omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
-        omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
-        omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
+        omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
+        omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
+        omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
 
         pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
@@ -104,23 +104,18 @@ no_sleep:
         clk_enable(osc_ck);
 
         /* clear CORE wake-up events */
-        omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
-        omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
+        omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
+        omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
 
         /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
-        omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
+        omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, 0x4 | 0x1);
 
         /* MPU domain wake events */
-        l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
-        if (l & 0x01)
-                omap2_prm_write_mod_reg(0x01, OCP_MOD,
-                                  OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
-        if (l & 0x20)
-                omap2_prm_write_mod_reg(0x20, OCP_MOD,
-                                  OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
+        omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET,
+                                    0x1);
 
-        /* Mask future PRCM-to-MPU interrupts */
-        omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
+        omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET,
+                                    0x20);
 
         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
         pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON);
@@ -148,9 +143,9 @@ static void omap2_enter_mpu_retention(void)
          * it is in retention mode. */
         if (omap2_allow_mpu_retention()) {
                 /* REVISIT: These write to reserved bits? */
-                omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
-                omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
-                omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
+                omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
+                omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
+                omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
 
                 /* Try to enter MPU retention */
                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 507d8eeaab95..3f80929a5f7e 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -133,60 +133,13 @@ static void omap3_save_secure_ram_context(void)
         }
 }
 
-/*
- * PRCM Interrupt Handler Helper Function
- *
- * The purpose of this function is to clear any wake-up events latched
- * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
- * may occur whilst attempting to clear a PM_WKST_x register and thus
- * set another bit in this register. A while loop is used to ensure
- * that any peripheral wake-up events occurring while attempting to
- * clear the PM_WKST_x are detected and cleared.
- */
-static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
-{
-        u32 wkst, fclk, iclk, clken;
-        u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
-        u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
-        u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
-        u16 grpsel_off = (regs == 3) ?
-                OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
-        int c = 0;
-
-        wkst = omap2_prm_read_mod_reg(module, wkst_off);
-        wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
-        wkst &= ~ignore_bits;
-        if (wkst) {
-                iclk = omap2_cm_read_mod_reg(module, iclk_off);
-                fclk = omap2_cm_read_mod_reg(module, fclk_off);
-                while (wkst) {
-                        clken = wkst;
-                        omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
-                        /*
-                         * For USBHOST, we don't know whether HOST1 or
-                         * HOST2 woke us up, so enable both f-clocks
-                         */
-                        if (module == OMAP3430ES2_USBHOST_MOD)
-                                clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
-                        omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
-                        omap2_prm_write_mod_reg(wkst, module, wkst_off);
-                        wkst = omap2_prm_read_mod_reg(module, wkst_off);
-                        wkst &= ~ignore_bits;
-                        c++;
-                }
-                omap2_cm_write_mod_reg(iclk, module, iclk_off);
-                omap2_cm_write_mod_reg(fclk, module, fclk_off);
-        }
-
-        return c;
-}
-
 static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
 {
         int c;
 
-        c = prcm_clear_mod_irqs(WKUP_MOD, 1,
-                ~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK));
+        c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1,
+                                        ~(OMAP3430_ST_IO_MASK |
+                                          OMAP3430_ST_IO_CHAIN_MASK));
 
         return c ? IRQ_HANDLED : IRQ_NONE;
 }
@@ -200,13 +153,14 @@ static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
          * these are handled in a separate handler to avoid acking
          * IO events before parsing in mux code
          */
-        c = prcm_clear_mod_irqs(WKUP_MOD, 1,
-                OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK);
-        c += prcm_clear_mod_irqs(CORE_MOD, 1, 0);
-        c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
+        c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1,
+                                        OMAP3430_ST_IO_MASK |
+                                        OMAP3430_ST_IO_CHAIN_MASK);
+        c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 1, 0);
+        c += omap3xxx_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
         if (omap_rev() > OMAP3430_REV_ES1_0) {
-                c += prcm_clear_mod_irqs(CORE_MOD, 3, 0);
-                c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
+                c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 3, 0);
+                c += omap3xxx_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
         }
 
         return c ? IRQ_HANDLED : IRQ_NONE;
@@ -399,159 +353,11 @@ restore:
 #define omap3_pm_suspend NULL
 #endif /* CONFIG_SUSPEND */
 
-
-/**
- * omap3_iva_idle(): ensure IVA is in idle so it can be put into
- *                   retention
- *
- * In cases where IVA2 is activated by bootcode, it may prevent
- * full-chip retention or off-mode because it is not idle.  This
- * function forces the IVA2 into idle state so it can go
- * into retention/off and thus allow full-chip retention/off.
- *
- **/
-static void __init omap3_iva_idle(void)
-{
-        /* ensure IVA2 clock is disabled */
-        omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
-
-        /* if no clock activity, nothing else to do */
-        if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
-              OMAP3430_CLKACTIVITY_IVA2_MASK))
-                return;
-
-        /* Reset IVA2 */
-        omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
-                          OMAP3430_RST2_IVA2_MASK |
-                          OMAP3430_RST3_IVA2_MASK,
-                          OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
-
-        /* Enable IVA2 clock */
-        omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
-                         OMAP3430_IVA2_MOD, CM_FCLKEN);
-
-        /* Set IVA2 boot mode to 'idle' */
-        omap3_ctrl_set_iva_bootmode_idle();
-
-        /* Un-reset IVA2 */
-        omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
-
-        /* Disable IVA2 clock */
-        omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
-
-        /* Reset IVA2 */
-        omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
-                          OMAP3430_RST2_IVA2_MASK |
-                          OMAP3430_RST3_IVA2_MASK,
-                          OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
-}
-
-static void __init omap3_d2d_idle(void)
-{
-        u16 mask, padconf;
-
-        /* In a stand alone OMAP3430 where there is not a stacked
-         * modem for the D2D Idle Ack and D2D MStandby must be pulled
-         * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
-         * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
-        mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
-        padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
-        padconf |= mask;
-        omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
-
-        padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
-        padconf |= mask;
-        omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
-
-        /* reset modem */
-        omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
-                          OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
-                          CORE_MOD, OMAP2_RM_RSTCTRL);
-        omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
-}
-
 static void __init prcm_setup_regs(void)
 {
-        u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
-                                        OMAP3630_EN_UART4_MASK : 0;
-        u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
-                                        OMAP3630_GRPSEL_UART4_MASK : 0;
-
-        /* XXX This should be handled by hwmod code or SCM init code */
-        omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
-
-        /*
-         * Enable control of expternal oscillator through
-         * sys_clkreq. In the long run clock framework should
-         * take care of this.
-         */
-        omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
-                             1 << OMAP_AUTOEXTCLKMODE_SHIFT,
-                             OMAP3430_GR_MOD,
-                             OMAP3_PRM_CLKSRC_CTRL_OFFSET);
-
-        /* setup wakup source */
-        omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
-                          OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
-                          WKUP_MOD, PM_WKEN);
-        /* No need to write EN_IO, that is always enabled */
-        omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
-                          OMAP3430_GRPSEL_GPT1_MASK |
-                          OMAP3430_GRPSEL_GPT12_MASK,
-                          WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
-
-        /* Enable PM_WKEN to support DSS LPR */
-        omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
-                                OMAP3430_DSS_MOD, PM_WKEN);
-
-        /* Enable wakeups in PER */
-        omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
-                          OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
-                          OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
-                          OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
-                          OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
-                          OMAP3430_EN_MCBSP4_MASK,
-                          OMAP3430_PER_MOD, PM_WKEN);
-        /* and allow them to wake up MPU */
-        omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
-                          OMAP3430_GRPSEL_GPIO2_MASK |
-                          OMAP3430_GRPSEL_GPIO3_MASK |
-                          OMAP3430_GRPSEL_GPIO4_MASK |
-                          OMAP3430_GRPSEL_GPIO5_MASK |
-                          OMAP3430_GRPSEL_GPIO6_MASK |
-                          OMAP3430_GRPSEL_UART3_MASK |
-                          OMAP3430_GRPSEL_MCBSP2_MASK |
-                          OMAP3430_GRPSEL_MCBSP3_MASK |
-                          OMAP3430_GRPSEL_MCBSP4_MASK,
-                          OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
-
-        /* Don't attach IVA interrupts */
-        if (omap3_has_iva()) {
-                omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
-                omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
-                omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
-                omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD,
-                                        OMAP3430_PM_IVAGRPSEL);
-        }
-
-        /* Clear any pending 'reset' flags */
-        omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
-        omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
-        omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
-        omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
-        omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
-        omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
-        omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
-
-        /* Clear any pending PRCM interrupts */
-        omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
-
-        /*
-         * We need to idle iva2_pwrdm even on am3703 with no iva2.
-         */
-        omap3_iva_idle();
+        omap3_ctrl_init();
 
-        omap3_d2d_idle();
+        omap3_prm_init_pm(cpu_is_omap3630(), omap3_has_iva());
 }
 
 void omap3_pm_off_mode_enable(int enable)
diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c
index a3a3cca2bcc4..86958050547a 100644
--- a/arch/arm/mach-omap2/prm2xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx.c
@@ -114,6 +114,24 @@ void omap2xxx_prm_dpll_reset(void)
         omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTCTRL);
 }
 
+/**
+ * omap2xxx_prm_clear_mod_irqs - clear wakeup status bits for a module
+ * @module: PRM module to clear wakeups from
+ * @regs: register offset to clear
+ * @wkst_mask: wakeup status mask to clear
+ *
+ * Clears wakeup status bits for a given module, so that the device can
+ * re-enter idle.
+ */
+void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
+{
+        u32 wkst;
+
+        wkst = omap2_prm_read_mod_reg(module, regs);
+        wkst &= wkst_mask;
+        omap2_prm_write_mod_reg(wkst, module, regs);
+}
+
 int omap2xxx_clkdm_sleep(struct clockdomain *clkdm)
 {
         omap2_prm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
diff --git a/arch/arm/mach-omap2/prm2xxx.h b/arch/arm/mach-omap2/prm2xxx.h
index d2cb6365716f..d73414139292 100644
--- a/arch/arm/mach-omap2/prm2xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx.h
@@ -125,6 +125,7 @@ extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm);
 extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm);
 
 extern void omap2xxx_prm_dpll_reset(void);
+void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask);
 
 extern int __init omap2xxx_prm_init(void);
 
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index 4bd7a2dca8af..2458be6fc67b 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -26,6 +26,8 @@
 #include "prm2xxx_3xxx.h"
 #include "cm2xxx_3xxx.h"
 #include "prm-regbits-34xx.h"
+#include "cm3xxx.h"
+#include "cm-regbits-34xx.h"
 
 static const struct omap_prcm_irq omap3_prcm_irqs[] = {
         OMAP_PRCM_IRQ("wkup",   0,      0),
@@ -206,6 +208,167 @@ void omap3xxx_prm_restore_irqen(u32 *saved_mask)
 }
 
 /**
+ * omap3xxx_prm_clear_mod_irqs - clear wake-up events from PRCM interrupt
+ * @module: PRM module to clear wakeups from
+ * @regs: register set to clear, 1 or 3
+ * @ignore_bits: wakeup status bits to ignore
+ *
+ * The purpose of this function is to clear any wake-up events latched
+ * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
+ * may occur whilst attempting to clear a PM_WKST_x register and thus
+ * set another bit in this register. A while loop is used to ensure
+ * that any peripheral wake-up events occurring while attempting to
+ * clear the PM_WKST_x are detected and cleared.
+ */
+int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
+{
+        u32 wkst, fclk, iclk, clken;
+        u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
+        u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
+        u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
+        u16 grpsel_off = (regs == 3) ?
+                OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
+        int c = 0;
+
+        wkst = omap2_prm_read_mod_reg(module, wkst_off);
+        wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
+        wkst &= ~ignore_bits;
+        if (wkst) {
+                iclk = omap2_cm_read_mod_reg(module, iclk_off);
+                fclk = omap2_cm_read_mod_reg(module, fclk_off);
+                while (wkst) {
+                        clken = wkst;
+                        omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
+                        /*
+                         * For USBHOST, we don't know whether HOST1 or
+                         * HOST2 woke us up, so enable both f-clocks
+                         */
+                        if (module == OMAP3430ES2_USBHOST_MOD)
+                                clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
+                        omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
+                        omap2_prm_write_mod_reg(wkst, module, wkst_off);
+                        wkst = omap2_prm_read_mod_reg(module, wkst_off);
+                        wkst &= ~ignore_bits;
+                        c++;
+                }
+                omap2_cm_write_mod_reg(iclk, module, iclk_off);
+                omap2_cm_write_mod_reg(fclk, module, fclk_off);
+        }
+
+        return c;
+}
+
+/**
+ * omap3_prm_reset_modem - toggle reset signal for modem
+ *
+ * Toggles the reset signal to modem IP block. Required to allow
+ * OMAP3430 without stacked modem to idle properly.
+ */
+void __init omap3_prm_reset_modem(void)
+{
+        omap2_prm_write_mod_reg(
+                OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
+                OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
+                                CORE_MOD, OMAP2_RM_RSTCTRL);
+        omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
+}
+
+/**
+ * omap3_prm_init_pm - initialize PM related registers for PRM
+ * @has_uart4: SoC has UART4
+ * @has_iva: SoC has IVA
+ *
+ * Initializes PRM registers for PM use. Called from PM init.
+ */
+void __init omap3_prm_init_pm(bool has_uart4, bool has_iva)
+{
+        u32 en_uart4_mask;
+        u32 grpsel_uart4_mask;
+
+        /*
+         * Enable control of expternal oscillator through
+         * sys_clkreq. In the long run clock framework should
+         * take care of this.
+         */
+        omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
+                                   1 << OMAP_AUTOEXTCLKMODE_SHIFT,
+                                   OMAP3430_GR_MOD,
+                                   OMAP3_PRM_CLKSRC_CTRL_OFFSET);
+
+        /* setup wakup source */
+        omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
+                                OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
+                                WKUP_MOD, PM_WKEN);
+        /* No need to write EN_IO, that is always enabled */
+        omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
+                                OMAP3430_GRPSEL_GPT1_MASK |
+                                OMAP3430_GRPSEL_GPT12_MASK,
+                                WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
+
+        /* Enable PM_WKEN to support DSS LPR */
+        omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
+                                OMAP3430_DSS_MOD, PM_WKEN);
+
+        if (has_uart4) {
+                en_uart4_mask = OMAP3630_EN_UART4_MASK;
+                grpsel_uart4_mask = OMAP3630_GRPSEL_UART4_MASK;
+        }
+
+        /* Enable wakeups in PER */
+        omap2_prm_write_mod_reg(en_uart4_mask |
+                                OMAP3430_EN_GPIO2_MASK |
+                                OMAP3430_EN_GPIO3_MASK |
+                                OMAP3430_EN_GPIO4_MASK |
+                                OMAP3430_EN_GPIO5_MASK |
+                                OMAP3430_EN_GPIO6_MASK |
+                                OMAP3430_EN_UART3_MASK |
+                                OMAP3430_EN_MCBSP2_MASK |
+                                OMAP3430_EN_MCBSP3_MASK |
+                                OMAP3430_EN_MCBSP4_MASK,
+                                OMAP3430_PER_MOD, PM_WKEN);
+
+        /* and allow them to wake up MPU */
+        omap2_prm_write_mod_reg(grpsel_uart4_mask |
+                                OMAP3430_GRPSEL_GPIO2_MASK |
+                                OMAP3430_GRPSEL_GPIO3_MASK |
+                                OMAP3430_GRPSEL_GPIO4_MASK |
+                                OMAP3430_GRPSEL_GPIO5_MASK |
+                                OMAP3430_GRPSEL_GPIO6_MASK |
+                                OMAP3430_GRPSEL_UART3_MASK |
+                                OMAP3430_GRPSEL_MCBSP2_MASK |
+                                OMAP3430_GRPSEL_MCBSP3_MASK |
+                                OMAP3430_GRPSEL_MCBSP4_MASK,
+                                OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
+
+        /* Don't attach IVA interrupts */
+        if (has_iva) {
+                omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
+                omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
+                omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
+                omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD,
+                                        OMAP3430_PM_IVAGRPSEL);
+        }
+
+        /* Clear any pending 'reset' flags */
+        omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
+        omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
+        omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
+        omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
+        omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
+        omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
+        omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD,
+                                OMAP2_RM_RSTST);
+
+        /* Clear any pending PRCM interrupts */
+        omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+
+        /* We need to idle iva2_pwrdm even on am3703 with no iva2. */
+        omap3xxx_prm_iva_idle();
+
+        omap3_prm_reset_modem();
+}
+
+/**
  * omap3xxx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
  *
  * Clear any previously-latched I/O wakeup events and ensure that the
@@ -276,6 +439,76 @@ static u32 omap3xxx_prm_read_reset_sources(void)
         return r;
 }
 
+/**
+ * omap3xxx_prm_iva_idle - ensure IVA is in idle so it can be put into retention
+ *
+ * In cases where IVA2 is activated by bootcode, it may prevent
+ * full-chip retention or off-mode because it is not idle.  This
+ * function forces the IVA2 into idle state so it can go
+ * into retention/off and thus allow full-chip retention/off.
+ */
+void omap3xxx_prm_iva_idle(void)
+{
+        /* ensure IVA2 clock is disabled */
+        omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
+
+        /* if no clock activity, nothing else to do */
+        if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
+              OMAP3430_CLKACTIVITY_IVA2_MASK))
+                return;
+
+        /* Reset IVA2 */
+        omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
+                                OMAP3430_RST2_IVA2_MASK |
+                                OMAP3430_RST3_IVA2_MASK,
+                                OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
+
+        /* Enable IVA2 clock */
+        omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
+                               OMAP3430_IVA2_MOD, CM_FCLKEN);
+
+        /* Un-reset IVA2 */
+        omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
+
+        /* Disable IVA2 clock */
+        omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
+
+        /* Reset IVA2 */
+        omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
+                                OMAP3430_RST2_IVA2_MASK |
+                                OMAP3430_RST3_IVA2_MASK,
+                                OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
+}
+
+/**
+ * omap3xxx_prm_clear_global_cold_reset - checks the global cold reset status
+ *                                        and clears it if asserted
+ *
+ * Checks if cold-reset has occurred and clears the status bit if yes. Returns
+ * 1 if cold-reset has occurred, 0 otherwise.
+ */
+int omap3xxx_prm_clear_global_cold_reset(void)
+{
+        if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
+            OMAP3430_GLOBAL_COLD_RST_MASK) {
+                omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
+                                           OMAP3430_GR_MOD,
+                                           OMAP3_PRM_RSTST_OFFSET);
+                return 1;
+        }
+
+        return 0;
+}
+
+void omap3_prm_save_scratchpad_contents(u32 *ptr)
+{
+        *ptr++ = omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
+                                        OMAP3_PRM_CLKSRC_CTRL_OFFSET);
+
+        *ptr++ = omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
+                                        OMAP3_PRM_CLKSEL_OFFSET);
+}
+
 /* Powerdomain low-level functions */
 
 static int omap3_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
index 1dacfc5b1959..bc37d42a8704 100644
--- a/arch/arm/mach-omap2/prm3xxx.h
+++ b/arch/arm/mach-omap2/prm3xxx.h
@@ -162,6 +162,12 @@ extern void omap3xxx_prm_dpll3_reset(void);
 
 extern int __init omap3xxx_prm_init(void);
 extern u32 omap3xxx_prm_get_reset_sources(void);
+int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits);
+void omap3xxx_prm_iva_idle(void);
+void omap3_prm_reset_modem(void);
+int omap3xxx_prm_clear_global_cold_reset(void);
+void omap3_prm_save_scratchpad_contents(u32 *ptr);
+void omap3_prm_init_pm(bool has_uart4, bool has_iva);
 
 #endif /* __ASSEMBLER */
 
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index e832bc7b8e2d..8333400898fb 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -95,7 +95,6 @@ static int tusb_set_sync_mode(unsigned sysclk_ps)
         dev_t.t_avdp_w = t_scsnh_advnh;
         dev_t.cyc_aavdh_we = 3;
         dev_t.cyc_wpl = 6;
-        dev_t.t_ce_rdyz = 7000;
 
         gpmc_calc_timings(&t, &tusb_sync, &dev_t);
 
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 91dd1c7cdbcd..06022b235730 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -514,7 +514,7 @@ static struct pxa2xx_udc_mach_info udc_info __initdata = {
         .gpio_pullup            = CORGI_GPIO_USB_PULLUP,
 };
 
-#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MASTER)
+#if IS_ENABLED(CONFIG_SPI_PXA2XX)
 static struct pxa2xx_spi_master corgi_spi_info = {
         .num_chipselect = 3,
 };
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index 6f38e1af45af..630fa916bbc6 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -90,19 +90,15 @@ EXPORT_SYMBOL(get_clk_frequency_khz);
  */
 static struct map_desc common_io_desc[] __initdata = {
         {       /* Devs */
-                .virtual        =  0xf2000000,
-                .pfn            = __phys_to_pfn(0x40000000),
-                .length         = 0x02000000,
-                .type           = MT_DEVICE
-        }, {    /* UNCACHED_PHYS_0 */
-                .virtual        = 0xff000000,
-                .pfn            = __phys_to_pfn(0x00000000),
-                .length         = 0x00100000,
+                .virtual        = (unsigned long)PERIPH_VIRT,
+                .pfn            = __phys_to_pfn(PERIPH_PHYS),
+                .length         = PERIPH_SIZE,
                 .type           = MT_DEVICE
         }
 };
 
 void __init pxa_map_io(void)
 {
+        debug_ll_io_init();
         iotable_init(ARRAY_AND_SIZE(common_io_desc));
 }
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
index ccb06e485520..8d63c211b22f 100644
--- a/arch/arm/mach-pxa/include/mach/hardware.h
+++ b/arch/arm/mach-pxa/include/mach/hardware.h
@@ -19,8 +19,8 @@
  * Workarounds for at least 2 errata so far require this.
  * The mapping is set in mach-pxa/generic.c.
  */
-#define UNCACHED_PHYS_0         0xff000000
-#define UNCACHED_ADDR           UNCACHED_PHYS_0
+#define UNCACHED_PHYS_0         0xfe000000
+#define UNCACHED_PHYS_0_SIZE    0x00100000
 
 /*
  * Intel PXA2xx internal register mapping:
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index f2c28972084d..66e4a2b6316e 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -331,7 +331,12 @@ static struct map_desc pxa25x_io_desc[] __initdata = {
         {       /* Mem Ctl */
                 .virtual        = (unsigned long)SMEMC_VIRT,
                 .pfn            = __phys_to_pfn(PXA2XX_SMEMC_BASE),
-                .length         = 0x00200000,
+                .length         = SMEMC_SIZE,
+                .type           = MT_DEVICE
+        }, {    /* UNCACHED_PHYS_0 */
+                .virtual        = UNCACHED_PHYS_0,
+                .pfn            = __phys_to_pfn(0x00000000),
+                .length         = UNCACHED_PHYS_0_SIZE,
                 .type           = MT_DEVICE
         },
 };
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 301471a07a10..b040d7d14888 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -402,12 +402,12 @@ static struct map_desc pxa27x_io_desc[] __initdata = {
         {       /* Mem Ctl */
                 .virtual        = (unsigned long)SMEMC_VIRT,
                 .pfn            = __phys_to_pfn(PXA2XX_SMEMC_BASE),
-                .length         = 0x00200000,
+                .length         = SMEMC_SIZE,
                 .type           = MT_DEVICE
-        }, {    /* IMem ctl */
-                .virtual        =  0xfe000000,
-                .pfn            = __phys_to_pfn(0x58000000),
-                .length         = 0x00100000,
+        }, {    /* UNCACHED_PHYS_0 */
+                .virtual        = UNCACHED_PHYS_0,
+                .pfn            = __phys_to_pfn(0x00000000),
+                .length         = UNCACHED_PHYS_0_SIZE,
                 .type           = MT_DEVICE
         },
 };
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 87011f3de69d..593ccd35ca97 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -416,7 +416,7 @@ static struct map_desc pxa3xx_io_desc[] __initdata = {
         {       /* Mem Ctl */
                 .virtual        = (unsigned long)SMEMC_VIRT,
                 .pfn            = __phys_to_pfn(PXA3XX_SMEMC_BASE),
-                .length         = 0x00200000,
+                .length         = SMEMC_SIZE,
                 .type           = MT_DEVICE
         }
 };
diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S
index 1e544be9905d..6c5b3ffd2cd3 100644
--- a/arch/arm/mach-pxa/sleep.S
+++ b/arch/arm/mach-pxa/sleep.S
@@ -157,7 +157,7 @@ pxa_cpu_do_suspend:
         @ Do not reorder...
         @ Intel PXA270 Specification Update notes problems performing
         @ external accesses after SDRAM is put in self-refresh mode
-        @ (see Errata 39 ...hangs when entering self-refresh mode)
+        @ (see Errata 38 ...hangs when entering self-refresh mode)
 
         @ force address lines low by reading at physical address 0
         ldr     r3, [r2]
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 8c1b39a0caa0..850e506926df 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -25,6 +25,7 @@
 #include <linux/interrupt.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
+#include <linux/platform_data/video-clcd-versatile.h>
 #include <linux/io.h>
 #include <linux/smsc911x.h>
 #include <linux/ata_platform.h>
@@ -48,7 +49,6 @@
 #include <mach/irqs.h>
 #include <asm/hardware/timer-sp.h>
 
-#include <plat/clcd.h>
 #include <plat/sched_clock.h>
 
 #include "core.h"
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
deleted file mode 100644
index 26003e23796d..000000000000
--- a/arch/arm/mach-s5p64x0/Kconfig
+++ /dev/null
@@ -1,102 +0,0 @@
-# arch/arm/mach-s5p64x0/Kconfig
-#
-# Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
-#               http://www.samsung.com/
-#
-# Licensed under GPLv2
-
-if ARCH_S5P64X0
-
-config CPU_S5P6440
-        bool
-        select ARM_AMBA
-        select PL330_DMA if DMADEVICES
-        select S5P_SLEEP if PM
-        select SAMSUNG_WAKEMASK if PM
-        help
-          Enable S5P6440 CPU support
-
-config CPU_S5P6450
-        bool
-        select ARM_AMBA
-        select PL330_DMA if DMADEVICES
-        select S5P_SLEEP if PM
-        select SAMSUNG_WAKEMASK if PM
-        help
-          Enable S5P6450 CPU support
-
-config S5P64X0_SETUP_FB_24BPP
-        bool
-        help
-          Common setup code for S5P64X0 based boards with a LCD display
-          through RGB interface.
-
-config S5P64X0_SETUP_I2C1
-        bool
-        help
-          Common setup code for i2c bus 1.
-
-config S5P64X0_SETUP_SPI
-        bool
-        help
-          Common setup code for SPI GPIO configurations
-
-config S5P64X0_SETUP_SDHCI_GPIO
-        bool
-        help
-          Common setup code for SDHCI gpio.
-
-# machine support
-
-config MACH_SMDK6440
-        bool "SMDK6440"
-        select CPU_S5P6440
-        select S3C_DEV_FB
-        select S3C_DEV_HSMMC
-        select S3C_DEV_HSMMC1
-        select S3C_DEV_HSMMC2
-        select S3C_DEV_I2C1
-        select S3C_DEV_RTC
-        select S3C_DEV_WDT
-        select S5P64X0_SETUP_FB_24BPP
-        select S5P64X0_SETUP_I2C1
-        select S5P64X0_SETUP_SDHCI_GPIO
-        select SAMSUNG_DEV_ADC
-        select SAMSUNG_DEV_BACKLIGHT
-        select SAMSUNG_DEV_PWM
-        select SAMSUNG_DEV_TS
-        help
-          Machine support for the Samsung SMDK6440
-
-config MACH_SMDK6450
-        bool "SMDK6450"
-        select CPU_S5P6450
-        select S3C_DEV_FB
-        select S3C_DEV_HSMMC
-        select S3C_DEV_HSMMC1
-        select S3C_DEV_HSMMC2
-        select S3C_DEV_I2C1
-        select S3C_DEV_RTC
-        select S3C_DEV_WDT
-        select S5P64X0_SETUP_FB_24BPP
-        select S5P64X0_SETUP_I2C1
-        select S5P64X0_SETUP_SDHCI_GPIO
-        select SAMSUNG_DEV_ADC
-        select SAMSUNG_DEV_BACKLIGHT
-        select SAMSUNG_DEV_PWM
-        select SAMSUNG_DEV_TS
-        help
-          Machine support for the Samsung SMDK6450
-
-menu "Use 8-bit SDHCI bus width"
-
-config S5P64X0_SD_CH1_8BIT
-        bool "SDHCI Channel 1 (Slot 1)"
-        depends on MACH_SMDK6450 || MACH_SMDK6440
-        help
-          Support SDHCI Channel 1 8-bit bus.
-          If selected, Channel 2 is disabled.
-
-endmenu
-
-endif
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile
deleted file mode 100644
index 12bb951187a4..000000000000
--- a/arch/arm/mach-s5p64x0/Makefile
+++ /dev/null
@@ -1,36 +0,0 @@
-# arch/arm/mach-s5p64x0/Makefile
-#
-# Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
-#               http://www.samsung.com
-#
-# Licensed under GPLv2
-
-obj-y                           :=
-obj-m                           :=
-obj-n                           :=
-obj-                            :=
-
-# Core
-
-obj-y                           += common.o clock.o
-obj-$(CONFIG_CPU_S5P6440)       += clock-s5p6440.o
-obj-$(CONFIG_CPU_S5P6450)       += clock-s5p6450.o
-
-obj-$(CONFIG_PM)                += pm.o irq-pm.o
-
-obj-y                           += dma.o
-
-# machine support
-
-obj-$(CONFIG_MACH_SMDK6440)     += mach-smdk6440.o
-obj-$(CONFIG_MACH_SMDK6450)     += mach-smdk6450.o
-
-# device support
-
-obj-y                           += dev-audio.o
-
-obj-y                                   += setup-i2c0.o
-obj-$(CONFIG_S5P64X0_SETUP_I2C1)        += setup-i2c1.o
-obj-$(CONFIG_S5P64X0_SETUP_FB_24BPP)    += setup-fb-24bpp.o
-obj-$(CONFIG_S5P64X0_SETUP_SPI)         += setup-spi.o
-obj-$(CONFIG_S5P64X0_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
diff --git a/arch/arm/mach-s5p64x0/Makefile.boot b/arch/arm/mach-s5p64x0/Makefile.boot
deleted file mode 100644
index 79ece4055b02..000000000000
--- a/arch/arm/mach-s5p64x0/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
-   zreladdr-y   += 0x20008000
-params_phys-y   := 0x20000100
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
deleted file mode 100644
index ae34a1d5e10a..000000000000
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ /dev/null
@@ -1,632 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/clock-s5p6440.c
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * S5P6440 - Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/device.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-
-#include "clock.h"
-#include "common.h"
-
-static u32 epll_div[][5] = {
-        { 36000000,     0,      48, 1, 4 },
-        { 48000000,     0,      32, 1, 3 },
-        { 60000000,     0,      40, 1, 3 },
-        { 72000000,     0,      48, 1, 3 },
-        { 84000000,     0,      28, 1, 2 },
-        { 96000000,     0,      32, 1, 2 },
-        { 32768000,     45264,  43, 1, 4 },
-        { 45158000,     6903,   30, 1, 3 },
-        { 49152000,     50332,  32, 1, 3 },
-        { 67738000,     10398,  45, 1, 3 },
-        { 73728000,     9961,   49, 1, 3 }
-};
-
-static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned int epll_con, epll_con_k;
-        unsigned int i;
-
-        if (clk->rate == rate)  /* Return if nothing changed */
-                return 0;
-
-        epll_con = __raw_readl(S5P64X0_EPLL_CON);
-        epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
-
-        epll_con_k &= ~(PLL90XX_KDIV_MASK);
-        epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
-
-        for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
-                 if (epll_div[i][0] == rate) {
-                        epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
-                        epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
-                                    (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
-                                    (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
-                        break;
-                }
-        }
-
-        if (i == ARRAY_SIZE(epll_div)) {
-                printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
-                return -EINVAL;
-        }
-
-        __raw_writel(epll_con, S5P64X0_EPLL_CON);
-        __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
-
-        printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
-                        clk->rate, rate);
-
-        clk->rate = rate;
-
-        return 0;
-}
-
-static struct clk_ops s5p6440_epll_ops = {
-        .get_rate = s5p_epll_get_rate,
-        .set_rate = s5p6440_epll_set_rate,
-};
-
-static struct clksrc_clk clk_hclk = {
-        .clk    = {
-                .name           = "clk_hclk",
-                .parent         = &clk_armclk.clk,
-        },
-        .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
-};
-
-static struct clksrc_clk clk_pclk = {
-        .clk    = {
-                .name           = "clk_pclk",
-                .parent         = &clk_hclk.clk,
-        },
-        .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
-};
-static struct clksrc_clk clk_hclk_low = {
-        .clk    = {
-                .name           = "clk_hclk_low",
-        },
-        .sources        = &clkset_hclk_low,
-        .reg_src        = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 },
-        .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
-};
-
-static struct clksrc_clk clk_pclk_low = {
-        .clk    = {
-                .name           = "clk_pclk_low",
-                .parent         = &clk_hclk_low.clk,
-        },
-        .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
-};
-
-/*
- * The following clocks will be disabled during clock initialization. It is
- * recommended to keep the following clocks disabled until the driver requests
- * for enabling the clock.
- */
-static struct clk init_clocks_off[] = {
-        {
-                .name           = "nand",
-                .parent         = &clk_hclk.clk,
-                .enable         = s5p64x0_mem_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "post",
-                .parent         = &clk_hclk_low.clk,
-                .enable         = s5p64x0_hclk0_ctrl,
-                .ctrlbit        = (1 << 5)
-        }, {
-                .name           = "2d",
-                .parent         = &clk_hclk.clk,
-                .enable         = s5p64x0_hclk0_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "dma",
-                .devname        = "dma-pl330",
-                .parent         = &clk_hclk_low.clk,
-                .enable         = s5p64x0_hclk0_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.0",
-                .parent         = &clk_hclk_low.clk,
-                .enable         = s5p64x0_hclk0_ctrl,
-                .ctrlbit        = (1 << 17),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.1",
-                .parent         = &clk_hclk_low.clk,
-                .enable         = s5p64x0_hclk0_ctrl,
-                .ctrlbit        = (1 << 18),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.2",
-                .parent         = &clk_hclk_low.clk,
-                .enable         = s5p64x0_hclk0_ctrl,
-                .ctrlbit        = (1 << 19),
-        }, {
-                .name           = "otg",
-                .parent         = &clk_hclk_low.clk,
-                .enable         = s5p64x0_hclk0_ctrl,
-                .ctrlbit        = (1 << 20)
-        }, {
-                .name           = "irom",
-                .parent         = &clk_hclk.clk,
-                .enable         = s5p64x0_hclk0_ctrl,
-                .ctrlbit        = (1 << 25),
-        }, {
-                .name           = "lcd",
-                .parent         = &clk_hclk_low.clk,
-                .enable         = s5p64x0_hclk1_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "hclk_fimgvg",
-                .parent         = &clk_hclk.clk,
-                .enable         = s5p64x0_hclk1_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "tsi",
-                .parent         = &clk_hclk_low.clk,
-                .enable         = s5p64x0_hclk1_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "watchdog",
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p64x0_pclk_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
-                .name           = "rtc",
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p64x0_pclk_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "timers",
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p64x0_pclk_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "pcm",
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p64x0_pclk_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "adc",
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p64x0_pclk_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "i2c",
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p64x0_pclk_ctrl,
-                .ctrlbit        = (1 << 17),
-        }, {
-                .name           = "spi",
-                .devname        = "s5p64x0-spi.0",
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p64x0_pclk_ctrl,
-                .ctrlbit        = (1 << 21),
-        }, {
-                .name           = "spi",
-                .devname        = "s5p64x0-spi.1",
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p64x0_pclk_ctrl,
-                .ctrlbit        = (1 << 22),
-        }, {
-                .name           = "gps",
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p64x0_pclk_ctrl,
-                .ctrlbit        = (1 << 25),
-        }, {
-                .name           = "dsim",
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p64x0_pclk_ctrl,
-                .ctrlbit        = (1 << 28),
-        }, {
-                .name           = "etm",
-                .parent         = &clk_pclk.clk,
-                .enable         = s5p64x0_pclk_ctrl,
-                .ctrlbit        = (1 << 29),
-        }, {
-                .name           = "dmc0",
-                .parent         = &clk_pclk.clk,
-                .enable         = s5p64x0_pclk_ctrl,
-                .ctrlbit        = (1 << 30),
-        }, {
-                .name           = "pclk_fimgvg",
-                .parent         = &clk_pclk.clk,
-                .enable         = s5p64x0_pclk_ctrl,
-                .ctrlbit        = (1 << 31),
-        }, {
-                .name           = "mmc_48m",
-                .devname        = "s3c-sdhci.0",
-                .parent         = &clk_48m,
-                .enable         = s5p64x0_sclk_ctrl,
-                .ctrlbit        = (1 << 27),
-        }, {
-                .name           = "mmc_48m",
-                .devname        = "s3c-sdhci.1",
-                .parent         = &clk_48m,
-                .enable         = s5p64x0_sclk_ctrl,
-                .ctrlbit        = (1 << 28),
-        }, {
-                .name           = "mmc_48m",
-                .devname        = "s3c-sdhci.2",
-                .parent         = &clk_48m,
-                .enable         = s5p64x0_sclk_ctrl,
-                .ctrlbit        = (1 << 29),
-        },
-};
-
-/*
- * The following clocks will be enabled during clock initialization.
- */
-static struct clk init_clocks[] = {
-        {
-                .name           = "intc",
-                .parent         = &clk_hclk.clk,
-                .enable         = s5p64x0_hclk0_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "mem",
-                .parent         = &clk_hclk.clk,
-                .enable         = s5p64x0_hclk0_ctrl,
-                .ctrlbit        = (1 << 21),
-        }, {
-                .name           = "uart",
-                .devname        = "s3c6400-uart.0",
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p64x0_pclk_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "uart",
-                .devname        = "s3c6400-uart.1",
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p64x0_pclk_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "uart",
-                .devname        = "s3c6400-uart.2",
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p64x0_pclk_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "uart",
-                .devname        = "s3c6400-uart.3",
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p64x0_pclk_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "gpio",
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p64x0_pclk_ctrl,
-                .ctrlbit        = (1 << 18),
-        },
-};
-
-static struct clk clk_iis_cd_v40 = {
-        .name           = "iis_cdclk_v40",
-};
-
-static struct clk clk_pcm_cd = {
-        .name           = "pcm_cdclk",
-};
-
-static struct clk *clkset_group1_list[] = {
-        &clk_mout_epll.clk,
-        &clk_dout_mpll.clk,
-        &clk_fin_epll,
-};
-
-static struct clksrc_sources clkset_group1 = {
-        .sources        = clkset_group1_list,
-        .nr_sources     = ARRAY_SIZE(clkset_group1_list),
-};
-
-static struct clk *clkset_uart_list[] = {
-        &clk_mout_epll.clk,
-        &clk_dout_mpll.clk,
-};
-
-static struct clksrc_sources clkset_uart = {
-        .sources        = clkset_uart_list,
-        .nr_sources     = ARRAY_SIZE(clkset_uart_list),
-};
-
-static struct clk *clkset_audio_list[] = {
-        &clk_mout_epll.clk,
-        &clk_dout_mpll.clk,
-        &clk_fin_epll,
-        &clk_iis_cd_v40,
-        &clk_pcm_cd,
-};
-
-static struct clksrc_sources clkset_audio = {
-        .sources        = clkset_audio_list,
-        .nr_sources     = ARRAY_SIZE(clkset_audio_list),
-};
-
-static struct clksrc_clk clksrcs[] = {
-        {
-                .clk    = {
-                        .name           = "sclk_post",
-                        .ctrlbit        = (1 << 10),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_dispcon",
-                        .ctrlbit        = (1 << 1),
-                        .enable         = s5p64x0_sclk1_ctrl,
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimgvg",
-                        .ctrlbit        = (1 << 2),
-                        .enable         = s5p64x0_sclk1_ctrl,
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
-        },
-};
-
-static struct clksrc_clk clk_sclk_mmc0 = {
-        .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.0",
-                .ctrlbit        = (1 << 24),
-                .enable         = s5p64x0_sclk_ctrl,
-        },
-        .sources = &clkset_group1,
-        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
-        .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_mmc1 = {
-        .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.1",
-                .ctrlbit        = (1 << 25),
-                .enable         = s5p64x0_sclk_ctrl,
-        },
-        .sources = &clkset_group1,
-        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
-        .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_mmc2 = {
-        .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.2",
-                .ctrlbit        = (1 << 26),
-                .enable         = s5p64x0_sclk_ctrl,
-        },
-        .sources = &clkset_group1,
-        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
-        .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_uclk = {
-        .clk    = {
-                .name           = "uclk1",
-                .ctrlbit        = (1 << 5),
-                .enable         = s5p64x0_sclk_ctrl,
-        },
-        .sources = &clkset_uart,
-        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
-        .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
-};
-
-static struct clk clk_i2s0 = {
-        .name           = "iis",
-        .devname        = "samsung-i2s.0",
-        .parent         = &clk_pclk_low.clk,
-        .enable         = s5p64x0_pclk_ctrl,
-        .ctrlbit        = (1 << 26),
-};
-
-static struct clksrc_clk clk_audio_bus2 = {
-        .clk    = {
-                .name           = "sclk_audio2",
-                .devname        = "samsung-i2s.0",
-                .ctrlbit        = (1 << 11),
-                .enable         = s5p64x0_sclk_ctrl,
-        },
-        .sources = &clkset_audio,
-        .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 0, .size = 3 },
-        .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 24, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_spi0 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "s5p64x0-spi.0",
-                .ctrlbit        = (1 << 20),
-                .enable         = s5p64x0_sclk_ctrl,
-        },
-        .sources = &clkset_group1,
-        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
-        .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_spi1 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "s5p64x0-spi.1",
-                .ctrlbit        = (1 << 21),
-                .enable         = s5p64x0_sclk_ctrl,
-        },
-        .sources = &clkset_group1,
-        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
-        .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
-};
-
-/* Clock initialization code */
-static struct clksrc_clk *sysclks[] = {
-        &clk_mout_apll,
-        &clk_mout_epll,
-        &clk_mout_mpll,
-        &clk_dout_mpll,
-        &clk_armclk,
-        &clk_hclk,
-        &clk_pclk,
-        &clk_hclk_low,
-        &clk_pclk_low,
-};
-
-static struct clk dummy_apb_pclk = {
-        .name           = "apb_pclk",
-        .id             = -1,
-};
-
-static struct clk *clk_cdev[] = {
-        &clk_i2s0,
-};
-
-static struct clksrc_clk *clksrc_cdev[] = {
-        &clk_sclk_uclk,
-        &clk_sclk_spi0,
-        &clk_sclk_spi1,
-        &clk_sclk_mmc0,
-        &clk_sclk_mmc1,
-        &clk_sclk_mmc2,
-        &clk_audio_bus2,
-};
-
-static struct clk_lookup s5p6440_clk_lookup[] = {
-        CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
-        CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
-        CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
-        CLKDEV_INIT("s5p64x0-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
-        CLKDEV_INIT("s5p64x0-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
-        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
-        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
-        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
-        CLKDEV_INIT("samsung-i2s.0", "i2s_opclk0", &clk_i2s0),
-        CLKDEV_INIT("samsung-i2s.0", "i2s_opclk1", &clk_audio_bus2.clk),
-};
-
-void __init_or_cpufreq s5p6440_setup_clocks(void)
-{
-        struct clk *xtal_clk;
-
-        unsigned long xtal;
-        unsigned long fclk;
-        unsigned long hclk;
-        unsigned long hclk_low;
-        unsigned long pclk;
-        unsigned long pclk_low;
-
-        unsigned long apll;
-        unsigned long mpll;
-        unsigned long epll;
-        unsigned int ptr;
-
-        /* Set S5P6440 functions for clk_fout_epll */
-
-        clk_fout_epll.enable = s5p_epll_enable;
-        clk_fout_epll.ops = &s5p6440_epll_ops;
-
-        clk_48m.enable = s5p64x0_clk48m_ctrl;
-
-        xtal_clk = clk_get(NULL, "ext_xtal");
-        BUG_ON(IS_ERR(xtal_clk));
-
-        xtal = clk_get_rate(xtal_clk);
-        clk_put(xtal_clk);
-
-        apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
-        mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
-        epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
-                                __raw_readl(S5P64X0_EPLL_CON_K));
-
-        clk_fout_apll.rate = apll;
-        clk_fout_mpll.rate = mpll;
-        clk_fout_epll.rate = epll;
-
-        printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
-                        " E=%ld.%ldMHz\n",
-                        print_mhz(apll), print_mhz(mpll), print_mhz(epll));
-
-        fclk = clk_get_rate(&clk_armclk.clk);
-        hclk = clk_get_rate(&clk_hclk.clk);
-        pclk = clk_get_rate(&clk_pclk.clk);
-        hclk_low = clk_get_rate(&clk_hclk_low.clk);
-        pclk_low = clk_get_rate(&clk_pclk_low.clk);
-
-        printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
-                        " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
-                        print_mhz(hclk), print_mhz(hclk_low),
-                        print_mhz(pclk), print_mhz(pclk_low));
-
-        clk_f.rate = fclk;
-        clk_h.rate = hclk;
-        clk_p.rate = pclk;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
-                s3c_set_clksrc(&clksrcs[ptr], true);
-}
-
-static struct clk *clks[] __initdata = {
-        &clk_ext,
-        &clk_iis_cd_v40,
-        &clk_pcm_cd,
-};
-
-void __init s5p6440_register_clocks(void)
-{
-        int ptr;
-        unsigned int cnt;
-
-        s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
-
-        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
-                s3c_register_clksrc(sysclks[ptr], 1);
-
-        s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
-        for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++)
-                s3c_disable_clocks(clk_cdev[cnt], 1);
-
-        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
-        s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
-        for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
-                s3c_register_clksrc(clksrc_cdev[ptr], 1);
-
-        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        clkdev_add_table(s5p6440_clk_lookup, ARRAY_SIZE(s5p6440_clk_lookup));
-
-        s3c24xx_register_clock(&dummy_apb_pclk);
-}
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
deleted file mode 100644
index 0b3ca2ed53e9..000000000000
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ /dev/null
@@ -1,701 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/clock-s5p6450.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * S5P6450 - Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/device.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-
-#include "clock.h"
-#include "common.h"
-
-static struct clksrc_clk clk_mout_dpll = {
-        .clk    = {
-                .name           = "mout_dpll",
-        },
-        .sources        = &clk_src_dpll,
-        .reg_src        = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 },
-};
-
-static u32 epll_div[][5] = {
-        { 133000000,    27307,  55, 2, 2 },
-        { 100000000,    43691,  41, 2, 2 },
-        { 480000000,    0,      80, 2, 0 },
-};
-
-static int s5p6450_epll_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned int epll_con, epll_con_k;
-        unsigned int i;
-
-        if (clk->rate == rate)  /* Return if nothing changed */
-                return 0;
-
-        epll_con = __raw_readl(S5P64X0_EPLL_CON);
-        epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
-
-        epll_con_k &= ~(PLL90XX_KDIV_MASK);
-        epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
-
-        for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
-                 if (epll_div[i][0] == rate) {
-                        epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
-                        epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
-                                    (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
-                                    (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
-                        break;
-                }
-        }
-
-        if (i == ARRAY_SIZE(epll_div)) {
-                printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
-                return -EINVAL;
-        }
-
-        __raw_writel(epll_con, S5P64X0_EPLL_CON);
-        __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
-
-        printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
-                        clk->rate, rate);
-
-        clk->rate = rate;
-
-        return 0;
-}
-
-static struct clk_ops s5p6450_epll_ops = {
-        .get_rate = s5p_epll_get_rate,
-        .set_rate = s5p6450_epll_set_rate,
-};
-
-static struct clksrc_clk clk_dout_epll = {
-        .clk    = {
-                .name           = "dout_epll",
-                .parent         = &clk_mout_epll.clk,
-        },
-        .reg_div        = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 },
-};
-
-static struct clksrc_clk clk_mout_hclk_sel = {
-        .clk    = {
-                .name           = "mout_hclk_sel",
-        },
-        .sources        = &clkset_hclk_low,
-        .reg_src        = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 },
-};
-
-static struct clk *clkset_hclk_list[] = {
-        &clk_mout_hclk_sel.clk,
-        &clk_armclk.clk,
-};
-
-static struct clksrc_sources clkset_hclk = {
-        .sources        = clkset_hclk_list,
-        .nr_sources     = ARRAY_SIZE(clkset_hclk_list),
-};
-
-static struct clksrc_clk clk_hclk = {
-        .clk    = {
-                .name           = "clk_hclk",
-        },
-        .sources        = &clkset_hclk,
-        .reg_src        = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 },
-        .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
-};
-
-static struct clksrc_clk clk_pclk = {
-        .clk    = {
-                .name           = "clk_pclk",
-                .parent         = &clk_hclk.clk,
-        },
-        .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
-};
-static struct clksrc_clk clk_dout_pwm_ratio0 = {
-        .clk    = {
-                .name           = "clk_dout_pwm_ratio0",
-                .parent         = &clk_mout_hclk_sel.clk,
-        },
-        .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk clk_pclk_to_wdt_pwm = {
-        .clk    = {
-                .name           = "clk_pclk_to_wdt_pwm",
-                .parent         = &clk_dout_pwm_ratio0.clk,
-        },
-        .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 },
-};
-
-static struct clksrc_clk clk_hclk_low = {
-        .clk    = {
-                .name           = "clk_hclk_low",
-        },
-        .sources        = &clkset_hclk_low,
-        .reg_src        = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 },
-        .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
-};
-
-static struct clksrc_clk clk_pclk_low = {
-        .clk    = {
-                .name           = "clk_pclk_low",
-                .parent         = &clk_hclk_low.clk,
-        },
-        .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
-};
-
-/*
- * The following clocks will be disabled during clock initialization. It is
- * recommended to keep the following clocks disabled until the driver requests
- * for enabling the clock.
- */
-static struct clk init_clocks_off[] = {
-        {
-                .name           = "usbhost",
-                .parent         = &clk_hclk_low.clk,
-                .enable         = s5p64x0_hclk0_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "dma",
-                .devname        = "dma-pl330",
-                .parent         = &clk_hclk_low.clk,
-                .enable         = s5p64x0_hclk0_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.0",
-                .parent         = &clk_hclk_low.clk,
-                .enable         = s5p64x0_hclk0_ctrl,
-                .ctrlbit        = (1 << 17),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.1",
-                .parent         = &clk_hclk_low.clk,
-                .enable         = s5p64x0_hclk0_ctrl,
-                .ctrlbit        = (1 << 18),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.2",
-                .parent         = &clk_hclk_low.clk,
-                .enable         = s5p64x0_hclk0_ctrl,
-                .ctrlbit        = (1 << 19),
-        }, {
-                .name           = "usbotg",
-                .parent         = &clk_hclk_low.clk,
-                .enable         = s5p64x0_hclk0_ctrl,
-                .ctrlbit        = (1 << 20),
-        }, {
-                .name           = "lcd",
-                .parent         = &clk_h,
-                .enable         = s5p64x0_hclk1_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "watchdog",
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p64x0_pclk_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
-                .name           = "rtc",
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p64x0_pclk_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "adc",
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p64x0_pclk_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.0",
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p64x0_pclk_ctrl,
-                .ctrlbit        = (1 << 17),
-        }, {
-                .name           = "spi",
-                .devname        = "s5p64x0-spi.0",
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p64x0_pclk_ctrl,
-                .ctrlbit        = (1 << 21),
-        }, {
-                .name           = "spi",
-                .devname        = "s5p64x0-spi.1",
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p64x0_pclk_ctrl,
-                .ctrlbit        = (1 << 22),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.1",
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p64x0_pclk_ctrl,
-                .ctrlbit        = (1 << 27),
-        }, {
-                .name           = "dmc0",
-                .parent         = &clk_pclk.clk,
-                .enable         = s5p64x0_pclk_ctrl,
-                .ctrlbit        = (1 << 30),
-        }
-};
-
-/*
- * The following clocks will be enabled during clock initialization.
- */
-static struct clk init_clocks[] = {
-        {
-                .name           = "intc",
-                .parent         = &clk_hclk.clk,
-                .enable         = s5p64x0_hclk0_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "mem",
-                .parent         = &clk_hclk.clk,
-                .enable         = s5p64x0_hclk0_ctrl,
-                .ctrlbit        = (1 << 21),
-        }, {
-                .name           = "uart",
-                .devname        = "s3c6400-uart.0",
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p64x0_pclk_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "uart",
-                .devname        = "s3c6400-uart.1",
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p64x0_pclk_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "uart",
-                .devname        = "s3c6400-uart.2",
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p64x0_pclk_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "uart",
-                .devname        = "s3c6400-uart.3",
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p64x0_pclk_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "timers",
-                .parent         = &clk_pclk_to_wdt_pwm.clk,
-                .enable         = s5p64x0_pclk_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "gpio",
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p64x0_pclk_ctrl,
-                .ctrlbit        = (1 << 18),
-        },
-};
-
-static struct clk *clkset_uart_list[] = {
-        &clk_dout_epll.clk,
-        &clk_dout_mpll.clk,
-};
-
-static struct clksrc_sources clkset_uart = {
-        .sources        = clkset_uart_list,
-        .nr_sources     = ARRAY_SIZE(clkset_uart_list),
-};
-
-static struct clk *clkset_mali_list[] = {
-        &clk_mout_epll.clk,
-        &clk_mout_apll.clk,
-        &clk_mout_mpll.clk,
-};
-
-static struct clksrc_sources clkset_mali = {
-        .sources        = clkset_mali_list,
-        .nr_sources     = ARRAY_SIZE(clkset_mali_list),
-};
-
-static struct clk *clkset_group2_list[] = {
-        &clk_dout_epll.clk,
-        &clk_dout_mpll.clk,
-        &clk_ext_xtal_mux,
-};
-
-static struct clksrc_sources clkset_group2 = {
-        .sources        = clkset_group2_list,
-        .nr_sources     = ARRAY_SIZE(clkset_group2_list),
-};
-
-static struct clk *clkset_dispcon_list[] = {
-        &clk_dout_epll.clk,
-        &clk_dout_mpll.clk,
-        &clk_ext_xtal_mux,
-        &clk_mout_dpll.clk,
-};
-
-static struct clksrc_sources clkset_dispcon = {
-        .sources        = clkset_dispcon_list,
-        .nr_sources     = ARRAY_SIZE(clkset_dispcon_list),
-};
-
-static struct clk *clkset_hsmmc44_list[] = {
-        &clk_dout_epll.clk,
-        &clk_dout_mpll.clk,
-        &clk_ext_xtal_mux,
-        &s5p_clk_27m,
-        &clk_48m,
-};
-
-static struct clksrc_sources clkset_hsmmc44 = {
-        .sources        = clkset_hsmmc44_list,
-        .nr_sources     = ARRAY_SIZE(clkset_hsmmc44_list),
-};
-
-static struct clk *clkset_sclk_audio0_list[] = {
-        [0] = &clk_dout_epll.clk,
-        [1] = &clk_dout_mpll.clk,
-        [2] = &clk_ext_xtal_mux,
-        [3] = NULL,
-        [4] = NULL,
-};
-
-static struct clksrc_sources clkset_sclk_audio0 = {
-        .sources        = clkset_sclk_audio0_list,
-        .nr_sources     = ARRAY_SIZE(clkset_sclk_audio0_list),
-};
-
-static struct clksrc_clk clk_sclk_audio0 = {
-        .clk            = {
-                .name           = "audio-bus",
-                .devname        = "samsung-i2s.0",
-                .enable         = s5p64x0_sclk_ctrl,
-                .ctrlbit        = (1 << 8),
-                .parent         = &clk_dout_epll.clk,
-        },
-        .sources        = &clkset_sclk_audio0,
-        .reg_src        = { .reg = S5P64X0_CLK_SRC1, .shift = 10, .size = 3 },
-        .reg_div        = { .reg = S5P64X0_CLK_DIV2, .shift = 8, .size = 4 },
-};
-
-static struct clksrc_clk clksrcs[] = {
-        {
-                .clk    = {
-                        .name           = "sclk_fimc",
-                        .ctrlbit        = (1 << 10),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "aclk_mali",
-                        .ctrlbit        = (1 << 2),
-                        .enable         = s5p64x0_sclk1_ctrl,
-                },
-                .sources = &clkset_mali,
-                .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_2d",
-                        .ctrlbit        = (1 << 12),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_mali,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 30, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 20, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_usi",
-                        .ctrlbit        = (1 << 7),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 10, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 16, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_camif",
-                        .ctrlbit        = (1 << 6),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 28, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 20, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_dispcon",
-                        .ctrlbit        = (1 << 1),
-                        .enable         = s5p64x0_sclk1_ctrl,
-                },
-                .sources = &clkset_dispcon,
-                .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_hsmmc44",
-                        .ctrlbit        = (1 << 30),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_hsmmc44,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 6, .size = 3 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 28, .size = 4 },
-        },
-};
-
-static struct clksrc_clk clk_sclk_mmc0 = {
-        .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.0",
-                .ctrlbit        = (1 << 24),
-                .enable         = s5p64x0_sclk_ctrl,
-        },
-        .sources = &clkset_group2,
-        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
-        .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_mmc1 = {
-        .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.1",
-                .ctrlbit        = (1 << 25),
-                .enable         = s5p64x0_sclk_ctrl,
-        },
-        .sources = &clkset_group2,
-        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
-        .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_mmc2 = {
-        .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.2",
-                .ctrlbit        = (1 << 26),
-                .enable         = s5p64x0_sclk_ctrl,
-        },
-        .sources = &clkset_group2,
-        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
-        .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_uclk = {
-        .clk    = {
-                .name           = "uclk1",
-                .ctrlbit        = (1 << 5),
-                .enable         = s5p64x0_sclk_ctrl,
-        },
-        .sources = &clkset_uart,
-        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
-        .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_spi0 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "s5p64x0-spi.0",
-                .ctrlbit        = (1 << 20),
-                .enable         = s5p64x0_sclk_ctrl,
-        },
-        .sources = &clkset_group2,
-        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
-        .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_spi1 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "s5p64x0-spi.1",
-                .ctrlbit        = (1 << 21),
-                .enable         = s5p64x0_sclk_ctrl,
-        },
-        .sources = &clkset_group2,
-        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
-        .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
-};
-
-static struct clk clk_i2s0 = {
-        .name           = "iis",
-        .devname        = "samsung-i2s.0",
-        .parent         = &clk_pclk_low.clk,
-        .enable         = s5p64x0_pclk_ctrl,
-        .ctrlbit        = (1 << 26),
-};
-
-static struct clk clk_i2s1 = {
-        .name           = "iis",
-        .devname        = "samsung-i2s.1",
-        .parent         = &clk_pclk_low.clk,
-        .enable         = s5p64x0_pclk_ctrl,
-        .ctrlbit        = (1 << 15),
-};
-
-static struct clk clk_i2s2 = {
-        .name           = "iis",
-        .devname        = "samsung-i2s.2",
-        .parent         = &clk_pclk_low.clk,
-        .enable         = s5p64x0_pclk_ctrl,
-        .ctrlbit        = (1 << 16),
-};
-
-static struct clk *clk_cdev[] = {
-        &clk_i2s0,
-        &clk_i2s1,
-        &clk_i2s2,
-};
-
-static struct clksrc_clk *clksrc_cdev[] = {
-        &clk_sclk_uclk,
-        &clk_sclk_spi0,
-        &clk_sclk_spi1,
-        &clk_sclk_mmc0,
-        &clk_sclk_mmc1,
-        &clk_sclk_mmc2,
-        &clk_sclk_audio0,
-};
-
-static struct clk_lookup s5p6450_clk_lookup[] = {
-        CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
-        CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
-        CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
-        CLKDEV_INIT("s5p64x0-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
-        CLKDEV_INIT("s5p64x0-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
-        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
-        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
-        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
-        CLKDEV_INIT("samsung-i2s.0", "i2s_opclk0", &clk_i2s0),
-        CLKDEV_INIT("samsung-i2s.0", "i2s_opclk1", &clk_sclk_audio0.clk),
-        CLKDEV_INIT("samsung-i2s.1", "i2s_opclk0", &clk_i2s1),
-        CLKDEV_INIT("samsung-i2s.2", "i2s_opclk0", &clk_i2s2),
-};
-
-/* Clock initialization code */
-static struct clksrc_clk *sysclks[] = {
-        &clk_mout_apll,
-        &clk_mout_epll,
-        &clk_dout_epll,
-        &clk_mout_mpll,
-        &clk_dout_mpll,
-        &clk_armclk,
-        &clk_mout_hclk_sel,
-        &clk_dout_pwm_ratio0,
-        &clk_pclk_to_wdt_pwm,
-        &clk_hclk,
-        &clk_pclk,
-        &clk_hclk_low,
-        &clk_pclk_low,
-};
-
-static struct clk dummy_apb_pclk = {
-        .name           = "apb_pclk",
-        .id             = -1,
-};
-
-void __init_or_cpufreq s5p6450_setup_clocks(void)
-{
-        struct clk *xtal_clk;
-
-        unsigned long xtal;
-        unsigned long fclk;
-        unsigned long hclk;
-        unsigned long hclk_low;
-        unsigned long pclk;
-        unsigned long pclk_low;
-
-        unsigned long apll;
-        unsigned long mpll;
-        unsigned long epll;
-        unsigned long dpll;
-        unsigned int ptr;
-
-        /* Set S5P6450 functions for clk_fout_epll */
-
-        clk_fout_epll.enable = s5p_epll_enable;
-        clk_fout_epll.ops = &s5p6450_epll_ops;
-
-        clk_48m.enable = s5p64x0_clk48m_ctrl;
-
-        xtal_clk = clk_get(NULL, "ext_xtal");
-        BUG_ON(IS_ERR(xtal_clk));
-
-        xtal = clk_get_rate(xtal_clk);
-        clk_put(xtal_clk);
-
-        apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
-        mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
-        epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
-                                __raw_readl(S5P64X0_EPLL_CON_K));
-        dpll = s5p_get_pll46xx(xtal, __raw_readl(S5P6450_DPLL_CON),
-                                __raw_readl(S5P6450_DPLL_CON_K), pll_4650c);
-
-        clk_fout_apll.rate = apll;
-        clk_fout_mpll.rate = mpll;
-        clk_fout_epll.rate = epll;
-        clk_fout_dpll.rate = dpll;
-
-        printk(KERN_INFO "S5P6450: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
-                        " E=%ld.%ldMHz, D=%ld.%ldMHz\n",
-                        print_mhz(apll), print_mhz(mpll), print_mhz(epll),
-                        print_mhz(dpll));
-
-        fclk = clk_get_rate(&clk_armclk.clk);
-        hclk = clk_get_rate(&clk_hclk.clk);
-        pclk = clk_get_rate(&clk_pclk.clk);
-        hclk_low = clk_get_rate(&clk_hclk_low.clk);
-        pclk_low = clk_get_rate(&clk_pclk_low.clk);
-
-        printk(KERN_INFO "S5P6450: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
-                        " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
-                        print_mhz(hclk), print_mhz(hclk_low),
-                        print_mhz(pclk), print_mhz(pclk_low));
-
-        clk_f.rate = fclk;
-        clk_h.rate = hclk;
-        clk_p.rate = pclk;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
-                s3c_set_clksrc(&clksrcs[ptr], true);
-}
-
-void __init s5p6450_register_clocks(void)
-{
-        int ptr;
-        unsigned int cnt;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
-                s3c_register_clksrc(sysclks[ptr], 1);
-
-
-        s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
-        for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++)
-                s3c_disable_clocks(clk_cdev[cnt], 1);
-
-        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
-        s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
-        for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
-                s3c_register_clksrc(clksrc_cdev[ptr], 1);
-
-        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        clkdev_add_table(s5p6450_clk_lookup, ARRAY_SIZE(s5p6450_clk_lookup));
-
-        s3c24xx_register_clock(&dummy_apb_pclk);
-}
diff --git a/arch/arm/mach-s5p64x0/clock.c b/arch/arm/mach-s5p64x0/clock.c
deleted file mode 100644
index 57e718957ef3..000000000000
--- a/arch/arm/mach-s5p64x0/clock.c
+++ /dev/null
@@ -1,236 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/clock.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * S5P64X0 - Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/device.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-
-#include "common.h"
-
-struct clksrc_clk clk_mout_apll = {
-        .clk    = {
-                .name           = "mout_apll",
-                .id             = -1,
-        },
-        .sources        = &clk_src_apll,
-        .reg_src        = { .reg = S5P64X0_CLK_SRC0, .shift = 0, .size = 1 },
-};
-
-struct clksrc_clk clk_mout_mpll = {
-        .clk    = {
-                .name           = "mout_mpll",
-                .id             = -1,
-        },
-        .sources        = &clk_src_mpll,
-        .reg_src        = { .reg = S5P64X0_CLK_SRC0, .shift = 1, .size = 1 },
-};
-
-struct clksrc_clk clk_mout_epll = {
-        .clk    = {
-                .name           = "mout_epll",
-                .id             = -1,
-        },
-        .sources        = &clk_src_epll,
-        .reg_src        = { .reg = S5P64X0_CLK_SRC0, .shift = 2, .size = 1 },
-};
-
-enum perf_level {
-        L0 = 532*1000,
-        L1 = 266*1000,
-        L2 = 133*1000,
-};
-
-static const u32 clock_table[][3] = {
-        /*{ARM_CLK, DIVarm, DIVhclk}*/
-        {L0 * 1000, (0 << ARM_DIV_RATIO_SHIFT), (3 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
-        {L1 * 1000, (1 << ARM_DIV_RATIO_SHIFT), (1 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
-        {L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
-};
-
-static unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
-{
-        unsigned long rate = clk_get_rate(clk->parent);
-        u32 clkdiv;
-
-        /* divisor mask starts at bit0, so no need to shift */
-        clkdiv = __raw_readl(ARM_CLK_DIV) & ARM_DIV_MASK;
-
-        return rate / (clkdiv + 1);
-}
-
-static unsigned long s5p64x0_armclk_round_rate(struct clk *clk,
-                                               unsigned long rate)
-{
-        u32 iter;
-
-        for (iter = 1 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
-                if (rate > clock_table[iter][0])
-                        return clock_table[iter-1][0];
-        }
-
-        return clock_table[ARRAY_SIZE(clock_table) - 1][0];
-}
-
-static int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate)
-{
-        u32 round_tmp;
-        u32 iter;
-        u32 clk_div0_tmp;
-        u32 cur_rate = clk->ops->get_rate(clk);
-        unsigned long flags;
-
-        round_tmp = clk->ops->round_rate(clk, rate);
-        if (round_tmp == cur_rate)
-                return 0;
-
-
-        for (iter = 0 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
-                if (round_tmp == clock_table[iter][0])
-                        break;
-        }
-
-        if (iter >= ARRAY_SIZE(clock_table))
-                iter = ARRAY_SIZE(clock_table) - 1;
-
-        local_irq_save(flags);
-        if (cur_rate > round_tmp) {
-                /* Frequency Down */
-                clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
-                clk_div0_tmp |= clock_table[iter][1];
-                __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
-
-                clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
-                                ~(S5P64X0_CLKDIV0_HCLK_MASK);
-                clk_div0_tmp |= clock_table[iter][2];
-                __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
-
-
-        } else {
-                /* Frequency Up */
-                clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
-                                ~(S5P64X0_CLKDIV0_HCLK_MASK);
-                clk_div0_tmp |= clock_table[iter][2];
-                __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
-
-                clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
-                clk_div0_tmp |= clock_table[iter][1];
-                __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
-        }
-        local_irq_restore(flags);
-
-        clk->rate = clock_table[iter][0];
-
-        return 0;
-}
-
-static struct clk_ops s5p64x0_clkarm_ops = {
-        .get_rate       = s5p64x0_armclk_get_rate,
-        .set_rate       = s5p64x0_armclk_set_rate,
-        .round_rate     = s5p64x0_armclk_round_rate,
-};
-
-struct clksrc_clk clk_armclk = {
-        .clk    = {
-                .name           = "armclk",
-                .id             = 1,
-                .parent         = &clk_mout_apll.clk,
-                .ops            = &s5p64x0_clkarm_ops,
-        },
-        .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 0, .size = 4 },
-};
-
-struct clksrc_clk clk_dout_mpll = {
-        .clk    = {
-                .name           = "dout_mpll",
-                .id             = -1,
-                .parent         = &clk_mout_mpll.clk,
-        },
-        .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 4, .size = 1 },
-};
-
-static struct clk *clkset_hclk_low_list[] = {
-        &clk_mout_apll.clk,
-        &clk_mout_mpll.clk,
-};
-
-struct clksrc_sources clkset_hclk_low = {
-        .sources        = clkset_hclk_low_list,
-        .nr_sources     = ARRAY_SIZE(clkset_hclk_low_list),
-};
-
-int s5p64x0_pclk_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P64X0_CLK_GATE_PCLK, clk, enable);
-}
-
-int s5p64x0_hclk0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P64X0_CLK_GATE_HCLK0, clk, enable);
-}
-
-int s5p64x0_hclk1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P64X0_CLK_GATE_HCLK1, clk, enable);
-}
-
-int s5p64x0_sclk_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P64X0_CLK_GATE_SCLK0, clk, enable);
-}
-
-int s5p64x0_sclk1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P64X0_CLK_GATE_SCLK1, clk, enable);
-}
-
-int s5p64x0_mem_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P64X0_CLK_GATE_MEM0, clk, enable);
-}
-
-int s5p64x0_clk48m_ctrl(struct clk *clk, int enable)
-{
-        unsigned long flags;
-        u32 val;
-
-        /* can't rely on clock lock, this register has other usages */
-        local_irq_save(flags);
-
-        val = __raw_readl(S5P64X0_OTHERS);
-        if (enable)
-                val |= S5P64X0_OTHERS_USB_SIG_MASK;
-        else
-                val &= ~S5P64X0_OTHERS_USB_SIG_MASK;
-
-        __raw_writel(val, S5P64X0_OTHERS);
-
-        local_irq_restore(flags);
-
-        return 0;
-}
diff --git a/arch/arm/mach-s5p64x0/clock.h b/arch/arm/mach-s5p64x0/clock.h
deleted file mode 100644
index 28b8e3c6bd24..000000000000
--- a/arch/arm/mach-s5p64x0/clock.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Header file for s5p64x0 clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __MACH_S5P64X0_CLOCK_H
-#define __MACH_S5P64X0_CLOCK_H __FILE__
-
-#include <linux/clk.h>
-
-extern struct clksrc_clk clk_mout_apll;
-extern struct clksrc_clk clk_mout_mpll;
-extern struct clksrc_clk clk_mout_epll;
-
-extern int s5p64x0_epll_enable(struct clk *clk, int enable);
-extern unsigned long s5p64x0_epll_get_rate(struct clk *clk);
-
-extern struct clksrc_clk clk_armclk;
-extern struct clksrc_clk clk_dout_mpll;
-
-extern struct clksrc_sources clkset_hclk_low;
-
-extern int s5p64x0_pclk_ctrl(struct clk *clk, int enable);
-extern int s5p64x0_hclk0_ctrl(struct clk *clk, int enable);
-extern int s5p64x0_hclk1_ctrl(struct clk *clk, int enable);
-extern int s5p64x0_sclk_ctrl(struct clk *clk, int enable);
-extern int s5p64x0_sclk1_ctrl(struct clk *clk, int enable);
-extern int s5p64x0_mem_ctrl(struct clk *clk, int enable);
-
-extern int s5p64x0_clk48m_ctrl(struct clk *clk, int enable);
-
-#endif /* __MACH_S5P64X0_CLOCK_H */
diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c
deleted file mode 100644
index 9a43be002d78..000000000000
--- a/arch/arm/mach-s5p64x0/common.c
+++ /dev/null
@@ -1,490 +0,0 @@
-/*
- * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Common Codes for S5P64X0 machines
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/device.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <clocksource/samsung_pwm.h>
-#include <linux/platform_device.h>
-#include <linux/sched.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/reboot.h>
-
-#include <asm/irq.h>
-#include <asm/proc-fns.h>
-#include <asm/system_misc.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include <mach/map.h>
-#include <mach/hardware.h>
-#include <mach/regs-clock.h>
-#include <mach/regs-gpio.h>
-
-#include <plat/cpu.h>
-#include <plat/clock.h>
-#include <plat/devs.h>
-#include <plat/pm.h>
-#include <plat/sdhci.h>
-#include <plat/adc-core.h>
-#include <plat/fb-core.h>
-#include <plat/spi-core.h>
-#include <plat/gpio-cfg.h>
-#include <plat/pwm-core.h>
-#include <plat/regs-irqtype.h>
-#include <plat/watchdog-reset.h>
-
-#include "common.h"
-
-static const char name_s5p6440[] = "S5P6440";
-static const char name_s5p6450[] = "S5P6450";
-
-static struct cpu_table cpu_ids[] __initdata = {
-        {
-                .idcode         = S5P6440_CPU_ID,
-                .idmask         = S5P64XX_CPU_MASK,
-                .map_io         = s5p6440_map_io,
-                .init_clocks    = s5p6440_init_clocks,
-                .init_uarts     = s5p6440_init_uarts,
-                .init           = s5p64x0_init,
-                .name           = name_s5p6440,
-        }, {
-                .idcode         = S5P6450_CPU_ID,
-                .idmask         = S5P64XX_CPU_MASK,
-                .map_io         = s5p6450_map_io,
-                .init_clocks    = s5p6450_init_clocks,
-                .init_uarts     = s5p6450_init_uarts,
-                .init           = s5p64x0_init,
-                .name           = name_s5p6450,
-        },
-};
-
-/* Initial IO mappings */
-
-static struct map_desc s5p64x0_iodesc[] __initdata = {
-        {
-                .virtual        = (unsigned long)S5P_VA_CHIPID,
-                .pfn            = __phys_to_pfn(S5P64X0_PA_CHIPID),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S3C_VA_SYS,
-                .pfn            = __phys_to_pfn(S5P64X0_PA_SYSCON),
-                .length         = SZ_64K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S3C_VA_TIMER,
-                .pfn            = __phys_to_pfn(S5P64X0_PA_TIMER),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S3C_VA_WATCHDOG,
-                .pfn            = __phys_to_pfn(S5P64X0_PA_WDT),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5P_VA_SROMC,
-                .pfn            = __phys_to_pfn(S5P64X0_PA_SROMC),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5P_VA_GPIO,
-                .pfn            = __phys_to_pfn(S5P64X0_PA_GPIO),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)VA_VIC0,
-                .pfn            = __phys_to_pfn(S5P64X0_PA_VIC0),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)VA_VIC1,
-                .pfn            = __phys_to_pfn(S5P64X0_PA_VIC1),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        },
-};
-
-static struct map_desc s5p6440_iodesc[] __initdata = {
-        {
-                .virtual        = (unsigned long)S3C_VA_UART,
-                .pfn            = __phys_to_pfn(S5P6440_PA_UART(0)),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        },
-};
-
-static struct map_desc s5p6450_iodesc[] __initdata = {
-        {
-                .virtual        = (unsigned long)S3C_VA_UART,
-                .pfn            = __phys_to_pfn(S5P6450_PA_UART(0)),
-                .length         = SZ_512K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S3C_VA_UART + SZ_512K,
-                .pfn            = __phys_to_pfn(S5P6450_PA_UART(5)),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        },
-};
-
-static void s5p64x0_idle(void)
-{
-        unsigned long val;
-
-        val = __raw_readl(S5P64X0_PWR_CFG);
-        val &= ~(0x3 << 5);
-        val |= (0x1 << 5);
-        __raw_writel(val, S5P64X0_PWR_CFG);
-
-        cpu_do_idle();
-}
-
-static struct samsung_pwm_variant s5p64x0_pwm_variant = {
-        .bits           = 32,
-        .div_base       = 0,
-        .has_tint_cstat = true,
-        .tclk_mask      = 0,
-};
-
-void __init samsung_set_timer_source(unsigned int event, unsigned int source)
-{
-        s5p64x0_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
-        s5p64x0_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
-}
-
-void __init samsung_timer_init(void)
-{
-        unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
-                IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
-                IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
-        };
-
-        samsung_pwm_clocksource_init(S3C_VA_TIMER,
-                                        timer_irqs, &s5p64x0_pwm_variant);
-}
-
-/*
- * s5p64x0_map_io
- *
- * register the standard CPU IO areas
- */
-
-void __init s5p64x0_init_io(struct map_desc *mach_desc, int size)
-{
-        /* initialize the io descriptors we need for initialization */
-        iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
-        if (mach_desc)
-                iotable_init(mach_desc, size);
-
-        /* detect cpu id and rev. */
-        s5p_init_cpu(S5P64X0_SYS_ID);
-
-        s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
-        samsung_wdt_reset_init(S3C_VA_WATCHDOG);
-
-        samsung_pwm_set_platdata(&s5p64x0_pwm_variant);
-}
-
-#ifdef CONFIG_CPU_S5P6440
-void __init s5p6440_map_io(void)
-{
-        /* initialize any device information early */
-        s3c_adc_setname("s3c64xx-adc");
-        s3c_fb_setname("s5p64x0-fb");
-        s3c64xx_spi_setname("s5p64x0-spi");
-
-        s5p64x0_default_sdhci0();
-        s5p64x0_default_sdhci1();
-        s5p6440_default_sdhci2();
-
-        iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
-}
-#endif
-
-#ifdef CONFIG_CPU_S5P6450
-void __init s5p6450_map_io(void)
-{
-        /* initialize any device information early */
-        s3c_adc_setname("s3c64xx-adc");
-        s3c_fb_setname("s5p64x0-fb");
-        s3c64xx_spi_setname("s5p64x0-spi");
-
-        s5p64x0_default_sdhci0();
-        s5p64x0_default_sdhci1();
-        s5p6450_default_sdhci2();
-
-        iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
-}
-#endif
-
-/*
- * s5p64x0_init_clocks
- *
- * register and setup the CPU clocks
- */
-#ifdef CONFIG_CPU_S5P6440
-void __init s5p6440_init_clocks(int xtal)
-{
-        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
-
-        s3c24xx_register_baseclocks(xtal);
-        s5p_register_clocks(xtal);
-        s5p6440_register_clocks();
-        s5p6440_setup_clocks();
-}
-#endif
-
-#ifdef CONFIG_CPU_S5P6450
-void __init s5p6450_init_clocks(int xtal)
-{
-        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
-
-        s3c24xx_register_baseclocks(xtal);
-        s5p_register_clocks(xtal);
-        s5p6450_register_clocks();
-        s5p6450_setup_clocks();
-}
-#endif
-
-/*
- * s5p64x0_init_irq
- *
- * register the CPU interrupts
- */
-#ifdef CONFIG_CPU_S5P6440
-void __init s5p6440_init_irq(void)
-{
-        /* S5P6440 supports 2 VIC */
-        u32 vic[2];
-
-        /*
-         * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
-         * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
-         */
-        vic[0] = 0xff800ae7;
-        vic[1] = 0xffbf23e5;
-
-        s5p_init_irq(vic, ARRAY_SIZE(vic));
-}
-#endif
-
-#ifdef CONFIG_CPU_S5P6450
-void __init s5p6450_init_irq(void)
-{
-        /* S5P6450 supports only 2 VIC */
-        u32 vic[2];
-
-        /*
-         * VIC0 is missing IRQ_VIC0[(13-15), (21-22)]
-         * VIC1 is missing IRQ VIC1[12, 14, 23]
-         */
-        vic[0] = 0xff9f1fff;
-        vic[1] = 0xff7fafff;
-
-        s5p_init_irq(vic, ARRAY_SIZE(vic));
-}
-#endif
-
-struct bus_type s5p64x0_subsys = {
-        .name           = "s5p64x0-core",
-        .dev_name       = "s5p64x0-core",
-};
-
-static struct device s5p64x0_dev = {
-        .bus    = &s5p64x0_subsys,
-};
-
-static int __init s5p64x0_core_init(void)
-{
-        return subsys_system_register(&s5p64x0_subsys, NULL);
-}
-core_initcall(s5p64x0_core_init);
-
-int __init s5p64x0_init(void)
-{
-        printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
-
-        /* set idle function */
-        arm_pm_idle = s5p64x0_idle;
-
-        return device_register(&s5p64x0_dev);
-}
-
-/* uart registration process */
-#ifdef CONFIG_CPU_S5P6440
-void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
-{
-        int uart;
-
-        for (uart = 0; uart < no; uart++) {
-                s5p_uart_resources[uart].resources->start = S5P6440_PA_UART(uart);
-                s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART;
-        }
-
-        s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
-}
-#endif
-
-#ifdef CONFIG_CPU_S5P6450
-void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
-{
-        s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
-}
-#endif
-
-#define eint_offset(irq)        ((irq) - IRQ_EINT(0))
-
-static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
-{
-        int offs = eint_offset(data->irq);
-        int shift;
-        u32 ctrl, mask;
-        u32 newvalue = 0;
-
-        if (offs > 15)
-                return -EINVAL;
-
-        switch (type) {
-        case IRQ_TYPE_NONE:
-                printk(KERN_WARNING "No edge setting!\n");
-                break;
-        case IRQ_TYPE_EDGE_RISING:
-                newvalue = S3C2410_EXTINT_RISEEDGE;
-                break;
-        case IRQ_TYPE_EDGE_FALLING:
-                newvalue = S3C2410_EXTINT_FALLEDGE;
-                break;
-        case IRQ_TYPE_EDGE_BOTH:
-                newvalue = S3C2410_EXTINT_BOTHEDGE;
-                break;
-        case IRQ_TYPE_LEVEL_LOW:
-                newvalue = S3C2410_EXTINT_LOWLEV;
-                break;
-        case IRQ_TYPE_LEVEL_HIGH:
-                newvalue = S3C2410_EXTINT_HILEV;
-                break;
-        default:
-                printk(KERN_ERR "No such irq type %d", type);
-                return -EINVAL;
-        }
-
-        shift = (offs / 2) * 4;
-        mask = 0x7 << shift;
-
-        ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask;
-        ctrl |= newvalue << shift;
-        __raw_writel(ctrl, S5P64X0_EINT0CON0);
-
-        /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
-        if (soc_is_s5p6450())
-                s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
-        else
-                s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
-
-        return 0;
-}
-
-/*
- * s5p64x0_irq_demux_eint
- *
- * This function demuxes the IRQ from the group0 external interrupts,
- * from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into
- * the specific handlers s5p64x0_irq_demux_eintX_Y.
- */
-static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned int end)
-{
-        u32 status = __raw_readl(S5P64X0_EINT0PEND);
-        u32 mask = __raw_readl(S5P64X0_EINT0MASK);
-        unsigned int irq;
-
-        status &= ~mask;
-        status >>= start;
-        status &= (1 << (end - start + 1)) - 1;
-
-        for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
-                if (status & 1)
-                        generic_handle_irq(irq);
-                status >>= 1;
-        }
-}
-
-static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
-{
-        s5p64x0_irq_demux_eint(0, 3);
-}
-
-static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
-{
-        s5p64x0_irq_demux_eint(4, 11);
-}
-
-static void s5p64x0_irq_demux_eint12_15(unsigned int irq,
-                                        struct irq_desc *desc)
-{
-        s5p64x0_irq_demux_eint(12, 15);
-}
-
-static int s5p64x0_alloc_gc(void)
-{
-        struct irq_chip_generic *gc;
-        struct irq_chip_type *ct;
-
-        gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE,
-                                    S5P_VA_GPIO, handle_level_irq);
-        if (!gc) {
-                printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0"
-                        "external interrupts failed\n", __func__);
-                return -EINVAL;
-        }
-
-        ct = gc->chip_types;
-        ct->chip.irq_ack = irq_gc_ack_set_bit;
-        ct->chip.irq_mask = irq_gc_mask_set_bit;
-        ct->chip.irq_unmask = irq_gc_mask_clr_bit;
-        ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
-        ct->chip.irq_set_wake = s3c_irqext_wake;
-        ct->regs.ack = EINT0PEND_OFFSET;
-        ct->regs.mask = EINT0MASK_OFFSET;
-        irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
-                               IRQ_NOREQUEST | IRQ_NOPROBE, 0);
-        return 0;
-}
-
-static int __init s5p64x0_init_irq_eint(void)
-{
-        int ret = s5p64x0_alloc_gc();
-        irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3);
-        irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11);
-        irq_set_chained_handler(IRQ_EINT12_15, s5p64x0_irq_demux_eint12_15);
-
-        return ret;
-}
-arch_initcall(s5p64x0_init_irq_eint);
-
-void s5p64x0_restart(enum reboot_mode mode, const char *cmd)
-{
-        if (mode != REBOOT_SOFT)
-                samsung_wdt_reset();
-
-        soft_restart(0);
-}
diff --git a/arch/arm/mach-s5p64x0/common.h b/arch/arm/mach-s5p64x0/common.h
deleted file mode 100644
index cbe7f3d731d0..000000000000
--- a/arch/arm/mach-s5p64x0/common.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Common Header for S5P64X0 machines
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ARCH_ARM_MACH_S5P64X0_COMMON_H
-#define __ARCH_ARM_MACH_S5P64X0_COMMON_H
-
-#include <linux/reboot.h>
-
-void s5p6440_init_irq(void);
-void s5p6450_init_irq(void);
-void s5p64x0_init_io(struct map_desc *mach_desc, int size);
-
-void s5p6440_register_clocks(void);
-void s5p6440_setup_clocks(void);
-
-void s5p6450_register_clocks(void);
-void s5p6450_setup_clocks(void);
-
-void s5p64x0_restart(enum reboot_mode mode, const char *cmd);
-extern  int s5p64x0_init(void);
-
-#ifdef CONFIG_CPU_S5P6440
-
-extern void s5p6440_map_io(void);
-extern void s5p6440_init_clocks(int xtal);
-
-extern void s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-#else
-#define s5p6440_init_clocks NULL
-#define s5p6440_init_uarts NULL
-#define s5p6440_map_io NULL
-#endif
-
-#ifdef CONFIG_CPU_S5P6450
-
-extern void s5p6450_map_io(void);
-extern void s5p6450_init_clocks(int xtal);
-
-extern void s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-#else
-#define s5p6450_init_clocks NULL
-#define s5p6450_init_uarts NULL
-#define s5p6450_map_io NULL
-#endif
-
-#endif /* __ARCH_ARM_MACH_S5P64X0_COMMON_H */
diff --git a/arch/arm/mach-s5p64x0/dev-audio.c b/arch/arm/mach-s5p64x0/dev-audio.c
deleted file mode 100644
index 723d4773c323..000000000000
--- a/arch/arm/mach-s5p64x0/dev-audio.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/dev-audio.c
- *
- * Copyright (c) 2010 Samsung Electronics Co. Ltd
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-
-#include <plat/gpio-cfg.h>
-#include <linux/platform_data/asoc-s3c.h>
-
-#include <mach/map.h>
-#include <mach/dma.h>
-#include <mach/irqs.h>
-
-static int s5p6440_cfg_i2s(struct platform_device *pdev)
-{
-        switch (pdev->id) {
-        case 0:
-                s3c_gpio_cfgpin_range(S5P6440_GPC(4), 2, S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin(S5P6440_GPC(7), S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin_range(S5P6440_GPH(6), 4, S3C_GPIO_SFN(5));
-                break;
-        default:
-                printk(KERN_ERR "Invalid Device %d\n", pdev->id);
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
-static struct s3c_audio_pdata s5p6440_i2s_pdata = {
-        .cfg_gpio = s5p6440_cfg_i2s,
-        .type = {
-                .i2s = {
-                        .quirks = QUIRK_PRI_6CHAN,
-                },
-        },
-};
-
-static struct resource s5p64x0_i2s0_resource[] = {
-        [0] = DEFINE_RES_MEM(S5P64X0_PA_I2S, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_I2S0_TX),
-        [2] = DEFINE_RES_DMA(DMACH_I2S0_RX),
-};
-
-struct platform_device s5p6440_device_iis = {
-        .name           = "samsung-i2s",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(s5p64x0_i2s0_resource),
-        .resource       = s5p64x0_i2s0_resource,
-        .dev = {
-                .platform_data = &s5p6440_i2s_pdata,
-        },
-};
-
-static int s5p6450_cfg_i2s(struct platform_device *pdev)
-{
-        switch (pdev->id) {
-        case 0:
-                s3c_gpio_cfgpin_range(S5P6450_GPR(4), 5, S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin_range(S5P6450_GPR(13), 2, S3C_GPIO_SFN(5));
-                break;
-        case 1:
-                s3c_gpio_cfgpin(S5P6440_GPB(4), S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin_range(S5P6450_GPC(0), 4, S3C_GPIO_SFN(5));
-                break;
-        case 2:
-                s3c_gpio_cfgpin_range(S5P6450_GPK(0), 5, S3C_GPIO_SFN(5));
-                break;
-        default:
-                printk(KERN_ERR "Invalid Device %d\n", pdev->id);
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
-static struct s3c_audio_pdata s5p6450_i2s0_pdata = {
-        .cfg_gpio = s5p6450_cfg_i2s,
-        .type = {
-                .i2s = {
-                        .quirks = QUIRK_PRI_6CHAN,
-                },
-        },
-};
-
-struct platform_device s5p6450_device_iis0 = {
-        .name           = "samsung-i2s",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(s5p64x0_i2s0_resource),
-        .resource       = s5p64x0_i2s0_resource,
-        .dev = {
-                .platform_data = &s5p6450_i2s0_pdata,
-        },
-};
-
-static struct s3c_audio_pdata s5p6450_i2s_pdata = {
-        .cfg_gpio = s5p6450_cfg_i2s,
-};
-
-static struct resource s5p6450_i2s1_resource[] = {
-        [0] = DEFINE_RES_MEM(S5P6450_PA_I2S1, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_I2S1_TX),
-        [2] = DEFINE_RES_DMA(DMACH_I2S1_RX),
-};
-
-struct platform_device s5p6450_device_iis1 = {
-        .name           = "samsung-i2s",
-        .id             = 1,
-        .num_resources  = ARRAY_SIZE(s5p6450_i2s1_resource),
-        .resource       = s5p6450_i2s1_resource,
-        .dev = {
-                .platform_data = &s5p6450_i2s_pdata,
-        },
-};
-
-static struct resource s5p6450_i2s2_resource[] = {
-        [0] = DEFINE_RES_MEM(S5P6450_PA_I2S2, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_I2S2_TX),
-        [2] = DEFINE_RES_DMA(DMACH_I2S2_RX),
-};
-
-struct platform_device s5p6450_device_iis2 = {
-        .name           = "samsung-i2s",
-        .id             = 2,
-        .num_resources  = ARRAY_SIZE(s5p6450_i2s2_resource),
-        .resource       = s5p6450_i2s2_resource,
-        .dev = {
-                .platform_data = &s5p6450_i2s_pdata,
-        },
-};
-
-/* PCM Controller platform_devices */
-
-static int s5p6440_pcm_cfg_gpio(struct platform_device *pdev)
-{
-        switch (pdev->id) {
-        case 0:
-                s3c_gpio_cfgpin_range(S5P6440_GPR(6), 3, S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin_range(S5P6440_GPR(13), 2, S3C_GPIO_SFN(2));
-                break;
-
-        default:
-                printk(KERN_DEBUG "Invalid PCM Controller number!");
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
-static struct s3c_audio_pdata s5p6440_pcm_pdata = {
-        .cfg_gpio = s5p6440_pcm_cfg_gpio,
-};
-
-static struct resource s5p6440_pcm0_resource[] = {
-        [0] = DEFINE_RES_MEM(S5P64X0_PA_PCM, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_PCM0_TX),
-        [2] = DEFINE_RES_DMA(DMACH_PCM0_RX),
-};
-
-struct platform_device s5p6440_device_pcm = {
-        .name           = "samsung-pcm",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(s5p6440_pcm0_resource),
-        .resource       = s5p6440_pcm0_resource,
-        .dev = {
-                .platform_data = &s5p6440_pcm_pdata,
-        },
-};
diff --git a/arch/arm/mach-s5p64x0/dma.c b/arch/arm/mach-s5p64x0/dma.c
deleted file mode 100644
index 9c4ce085f585..000000000000
--- a/arch/arm/mach-s5p64x0/dma.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/dma.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-*/
-
-#include <linux/dma-mapping.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/pl330.h>
-
-#include <asm/irq.h>
-
-#include <mach/map.h>
-#include <mach/irqs.h>
-#include <mach/regs-clock.h>
-#include <mach/dma.h>
-
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/irqs.h>
-
-static u8 s5p6440_pdma_peri[] = {
-        DMACH_UART0_RX,
-        DMACH_UART0_TX,
-        DMACH_UART1_RX,
-        DMACH_UART1_TX,
-        DMACH_UART2_RX,
-        DMACH_UART2_TX,
-        DMACH_UART3_RX,
-        DMACH_UART3_TX,
-        DMACH_MAX,
-        DMACH_MAX,
-        DMACH_PCM0_TX,
-        DMACH_PCM0_RX,
-        DMACH_I2S0_TX,
-        DMACH_I2S0_RX,
-        DMACH_SPI0_TX,
-        DMACH_SPI0_RX,
-        DMACH_MAX,
-        DMACH_MAX,
-        DMACH_MAX,
-        DMACH_MAX,
-        DMACH_SPI1_TX,
-        DMACH_SPI1_RX,
-};
-
-static struct dma_pl330_platdata s5p6440_pdma_pdata = {
-        .nr_valid_peri = ARRAY_SIZE(s5p6440_pdma_peri),
-        .peri_id = s5p6440_pdma_peri,
-};
-
-static u8 s5p6450_pdma_peri[] = {
-        DMACH_UART0_RX,
-        DMACH_UART0_TX,
-        DMACH_UART1_RX,
-        DMACH_UART1_TX,
-        DMACH_UART2_RX,
-        DMACH_UART2_TX,
-        DMACH_UART3_RX,
-        DMACH_UART3_TX,
-        DMACH_UART4_RX,
-        DMACH_UART4_TX,
-        DMACH_PCM0_TX,
-        DMACH_PCM0_RX,
-        DMACH_I2S0_TX,
-        DMACH_I2S0_RX,
-        DMACH_SPI0_TX,
-        DMACH_SPI0_RX,
-        DMACH_PCM1_TX,
-        DMACH_PCM1_RX,
-        DMACH_PCM2_TX,
-        DMACH_PCM2_RX,
-        DMACH_SPI1_TX,
-        DMACH_SPI1_RX,
-        DMACH_USI_TX,
-        DMACH_USI_RX,
-        DMACH_MAX,
-        DMACH_I2S1_TX,
-        DMACH_I2S1_RX,
-        DMACH_I2S2_TX,
-        DMACH_I2S2_RX,
-        DMACH_PWM,
-        DMACH_UART5_RX,
-        DMACH_UART5_TX,
-};
-
-static struct dma_pl330_platdata s5p6450_pdma_pdata = {
-        .nr_valid_peri = ARRAY_SIZE(s5p6450_pdma_peri),
-        .peri_id = s5p6450_pdma_peri,
-};
-
-static AMBA_AHB_DEVICE(s5p64x0_pdma, "dma-pl330", 0x00041330,
-        S5P64X0_PA_PDMA, {IRQ_DMA0}, NULL);
-
-static int __init s5p64x0_dma_init(void)
-{
-        if (soc_is_s5p6450()) {
-                dma_cap_set(DMA_SLAVE, s5p6450_pdma_pdata.cap_mask);
-                dma_cap_set(DMA_CYCLIC, s5p6450_pdma_pdata.cap_mask);
-                s5p64x0_pdma_device.dev.platform_data = &s5p6450_pdma_pdata;
-        } else {
-                dma_cap_set(DMA_SLAVE, s5p6440_pdma_pdata.cap_mask);
-                dma_cap_set(DMA_CYCLIC, s5p6440_pdma_pdata.cap_mask);
-                s5p64x0_pdma_device.dev.platform_data = &s5p6440_pdma_pdata;
-        }
-
-        amba_device_register(&s5p64x0_pdma_device, &iomem_resource);
-
-        return 0;
-}
-arch_initcall(s5p64x0_dma_init);
diff --git a/arch/arm/mach-s5p64x0/i2c.h b/arch/arm/mach-s5p64x0/i2c.h
deleted file mode 100644
index 1e5bb4ea200d..000000000000
--- a/arch/arm/mach-s5p64x0/i2c.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * S5P64X0 I2C configuration
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-extern void s5p6440_i2c0_cfg_gpio(struct platform_device *dev);
-extern void s5p6440_i2c1_cfg_gpio(struct platform_device *dev);
-
-extern void s5p6450_i2c0_cfg_gpio(struct platform_device *dev);
-extern void s5p6450_i2c1_cfg_gpio(struct platform_device *dev);
diff --git a/arch/arm/mach-s5p64x0/include/mach/debug-macro.S b/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
deleted file mode 100644
index 8759e7882bcb..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
+++ /dev/null
@@ -1,32 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* pull in the relevant register and map files. */
-
-#include <linux/serial_s3c.h>
-#include <plat/map-base.h>
-#include <plat/map-s5p.h>
-
-        .macro addruart, rp, rv, tmp
-                mov     \rp, #0xE0000000
-                orr     \rp, \rp, #0x00100000
-                ldr     \rp, [\rp, #0x118 ]
-                and     \rp, \rp, #0xff000
-                teq     \rp, #0x50000           @@ S5P6450
-                ldreq   \rp, =0xEC800000
-                movne   \rp, #0xEC000000        @@ S5P6440
-                ldrne   \rv, = S3C_VA_UART
-#if CONFIG_DEBUG_S3C_UART != 0
-                add     \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
-                add     \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
-#endif
-        .endm
-
-#include <debug/samsung.S>
diff --git a/arch/arm/mach-s5p64x0/include/mach/dma.h b/arch/arm/mach-s5p64x0/include/mach/dma.h
deleted file mode 100644
index 5a622af461d7..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/dma.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __MACH_DMA_H
-#define __MACH_DMA_H
-
-/* This platform uses the common common DMA API driver for PL330 */
-#include <plat/dma-pl330.h>
-
-#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/gpio.h b/arch/arm/mach-s5p64x0/include/mach/gpio.h
deleted file mode 100644
index 06cd3c9b16ac..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/gpio.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/include/mach/gpio.h
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * S5P64X0 - GPIO lib support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H __FILE__
-
-/* GPIO bank sizes */
-
-#define S5P6440_GPIO_A_NR       (6)
-#define S5P6440_GPIO_B_NR       (7)
-#define S5P6440_GPIO_C_NR       (8)
-#define S5P6440_GPIO_F_NR       (16)
-#define S5P6440_GPIO_G_NR       (7)
-#define S5P6440_GPIO_H_NR       (10)
-#define S5P6440_GPIO_I_NR       (16)
-#define S5P6440_GPIO_J_NR       (12)
-#define S5P6440_GPIO_N_NR       (16)
-#define S5P6440_GPIO_P_NR       (8)
-#define S5P6440_GPIO_R_NR       (15)
-
-#define S5P6450_GPIO_A_NR       (6)
-#define S5P6450_GPIO_B_NR       (7)
-#define S5P6450_GPIO_C_NR       (8)
-#define S5P6450_GPIO_D_NR       (8)
-#define S5P6450_GPIO_F_NR       (16)
-#define S5P6450_GPIO_G_NR       (14)
-#define S5P6450_GPIO_H_NR       (10)
-#define S5P6450_GPIO_I_NR       (16)
-#define S5P6450_GPIO_J_NR       (12)
-#define S5P6450_GPIO_K_NR       (5)
-#define S5P6450_GPIO_N_NR       (16)
-#define S5P6450_GPIO_P_NR       (11)
-#define S5P6450_GPIO_Q_NR       (14)
-#define S5P6450_GPIO_R_NR       (15)
-#define S5P6450_GPIO_S_NR       (8)
-
-/* GPIO bank numbers */
-
-/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
- * space for debugging purposes so that any accidental
- * change from one gpio bank to another can be caught.
-*/
-
-#define S5P64X0_GPIO_NEXT(__gpio) \
-        ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
-
-enum s5p6440_gpio_number {
-        S5P6440_GPIO_A_START    = 0,
-        S5P6440_GPIO_B_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_A),
-        S5P6440_GPIO_C_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_B),
-        S5P6440_GPIO_F_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_C),
-        S5P6440_GPIO_G_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_F),
-        S5P6440_GPIO_H_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_G),
-        S5P6440_GPIO_I_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_H),
-        S5P6440_GPIO_J_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_I),
-        S5P6440_GPIO_N_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_J),
-        S5P6440_GPIO_P_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_N),
-        S5P6440_GPIO_R_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_P),
-};
-
-enum s5p6450_gpio_number {
-        S5P6450_GPIO_A_START    = 0,
-        S5P6450_GPIO_B_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_A),
-        S5P6450_GPIO_C_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_B),
-        S5P6450_GPIO_D_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_C),
-        S5P6450_GPIO_F_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_D),
-        S5P6450_GPIO_G_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_F),
-        S5P6450_GPIO_H_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_G),
-        S5P6450_GPIO_I_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_H),
-        S5P6450_GPIO_J_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_I),
-        S5P6450_GPIO_K_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_J),
-        S5P6450_GPIO_N_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_K),
-        S5P6450_GPIO_P_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_N),
-        S5P6450_GPIO_Q_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_P),
-        S5P6450_GPIO_R_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_Q),
-        S5P6450_GPIO_S_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_R),
-};
-
-/* GPIO number definitions */
-
-#define S5P6440_GPA(_nr)        (S5P6440_GPIO_A_START + (_nr))
-#define S5P6440_GPB(_nr)        (S5P6440_GPIO_B_START + (_nr))
-#define S5P6440_GPC(_nr)        (S5P6440_GPIO_C_START + (_nr))
-#define S5P6440_GPF(_nr)        (S5P6440_GPIO_F_START + (_nr))
-#define S5P6440_GPG(_nr)        (S5P6440_GPIO_G_START + (_nr))
-#define S5P6440_GPH(_nr)        (S5P6440_GPIO_H_START + (_nr))
-#define S5P6440_GPI(_nr)        (S5P6440_GPIO_I_START + (_nr))
-#define S5P6440_GPJ(_nr)        (S5P6440_GPIO_J_START + (_nr))
-#define S5P6440_GPN(_nr)        (S5P6440_GPIO_N_START + (_nr))
-#define S5P6440_GPP(_nr)        (S5P6440_GPIO_P_START + (_nr))
-#define S5P6440_GPR(_nr)        (S5P6440_GPIO_R_START + (_nr))
-
-#define S5P6450_GPA(_nr)        (S5P6450_GPIO_A_START + (_nr))
-#define S5P6450_GPB(_nr)        (S5P6450_GPIO_B_START + (_nr))
-#define S5P6450_GPC(_nr)        (S5P6450_GPIO_C_START + (_nr))
-#define S5P6450_GPD(_nr)        (S5P6450_GPIO_D_START + (_nr))
-#define S5P6450_GPF(_nr)        (S5P6450_GPIO_F_START + (_nr))
-#define S5P6450_GPG(_nr)        (S5P6450_GPIO_G_START + (_nr))
-#define S5P6450_GPH(_nr)        (S5P6450_GPIO_H_START + (_nr))
-#define S5P6450_GPI(_nr)        (S5P6450_GPIO_I_START + (_nr))
-#define S5P6450_GPJ(_nr)        (S5P6450_GPIO_J_START + (_nr))
-#define S5P6450_GPK(_nr)        (S5P6450_GPIO_K_START + (_nr))
-#define S5P6450_GPN(_nr)        (S5P6450_GPIO_N_START + (_nr))
-#define S5P6450_GPP(_nr)        (S5P6450_GPIO_P_START + (_nr))
-#define S5P6450_GPQ(_nr)        (S5P6450_GPIO_Q_START + (_nr))
-#define S5P6450_GPR(_nr)        (S5P6450_GPIO_R_START + (_nr))
-#define S5P6450_GPS(_nr)        (S5P6450_GPIO_S_START + (_nr))
-
-/* the end of the S5P64X0 specific gpios */
-
-#define S5P6440_GPIO_END        (S5P6440_GPR(S5P6440_GPIO_R_NR) + 1)
-#define S5P6450_GPIO_END        (S5P6450_GPS(S5P6450_GPIO_S_NR) + 1)
-
-#define S5P64X0_GPIO_END        (S5P6440_GPIO_END > S5P6450_GPIO_END ?  \
-                                 S5P6440_GPIO_END : S5P6450_GPIO_END)
-
-#define S3C_GPIO_END            S5P64X0_GPIO_END
-
-/* define the number of gpios we need to the one after the last GPIO range */
-
-#define ARCH_NR_GPIOS           (S5P64X0_GPIO_END + CONFIG_SAMSUNG_GPIO_EXTRA)
-
-#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/hardware.h b/arch/arm/mach-s5p64x0/include/mach/hardware.h
deleted file mode 100644
index d3e87996dd9a..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/hardware.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/include/mach/hardware.h
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * S5P64X0 - Hardware support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H __FILE__
-
-/* currently nothing here, placeholder */
-
-#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/irqs.h b/arch/arm/mach-s5p64x0/include/mach/irqs.h
deleted file mode 100644
index 53982db9d259..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/irqs.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/include/mach/irqs.h
- *
- * Copyright 2009-2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * S5P64X0 - IRQ definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H __FILE__
-
-#include <plat/irqs.h>
-
-/* VIC0 */
-
-#define IRQ_EINT0_3             S5P_IRQ_VIC0(0)
-#define IRQ_EINT4_11            S5P_IRQ_VIC0(1)
-#define IRQ_RTC_TIC             S5P_IRQ_VIC0(2)
-#define IRQ_IIS1                S5P_IRQ_VIC0(3) /* for only S5P6450 */
-#define IRQ_IIS2                S5P_IRQ_VIC0(4) /* for only S5P6450 */
-#define IRQ_IIC1                S5P_IRQ_VIC0(5)
-#define IRQ_I2SV40              S5P_IRQ_VIC0(6)
-#define IRQ_GPS                 S5P_IRQ_VIC0(7) /* for only S5P6450 */
-
-#define IRQ_2D                  S5P_IRQ_VIC0(11)
-#define IRQ_TIMER0_VIC          S5P_IRQ_VIC0(23)
-#define IRQ_TIMER1_VIC          S5P_IRQ_VIC0(24)
-#define IRQ_TIMER2_VIC          S5P_IRQ_VIC0(25)
-#define IRQ_WDT                 S5P_IRQ_VIC0(26)
-#define IRQ_TIMER3_VIC          S5P_IRQ_VIC0(27)
-#define IRQ_TIMER4_VIC          S5P_IRQ_VIC0(28)
-#define IRQ_DISPCON0            S5P_IRQ_VIC0(29)
-#define IRQ_DISPCON1            S5P_IRQ_VIC0(30)
-#define IRQ_DISPCON2            S5P_IRQ_VIC0(31)
-
-/* VIC1 */
-
-#define IRQ_EINT12_15           S5P_IRQ_VIC1(0)
-#define IRQ_PCM0                S5P_IRQ_VIC1(2)
-#define IRQ_PCM1                S5P_IRQ_VIC1(3) /* for only S5P6450 */
-#define IRQ_PCM2                S5P_IRQ_VIC1(4) /* for only S5P6450 */
-#define IRQ_UART0               S5P_IRQ_VIC1(5)
-#define IRQ_UART1               S5P_IRQ_VIC1(6)
-#define IRQ_UART2               S5P_IRQ_VIC1(7)
-#define IRQ_UART3               S5P_IRQ_VIC1(8)
-#define IRQ_DMA0                S5P_IRQ_VIC1(9)
-#define IRQ_UART4               S5P_IRQ_VIC1(10)        /* S5P6450 */
-#define IRQ_UART5               S5P_IRQ_VIC1(11)        /* S5P6450 */
-#define IRQ_NFC                 S5P_IRQ_VIC1(13)
-#define IRQ_USI                 S5P_IRQ_VIC1(15)        /* S5P6450 */
-#define IRQ_SPI0                S5P_IRQ_VIC1(16)
-#define IRQ_SPI1                S5P_IRQ_VIC1(17)
-#define IRQ_HSMMC2              S5P_IRQ_VIC1(17)        /* Shared */
-#define IRQ_IIC                 S5P_IRQ_VIC1(18)
-#define IRQ_DISPCON3            S5P_IRQ_VIC1(19)
-#define IRQ_EINT_GROUPS         S5P_IRQ_VIC1(21)
-#define IRQ_PMU                 S5P_IRQ_VIC1(23)        /* S5P6440 */
-#define IRQ_HSMMC0              S5P_IRQ_VIC1(24)
-#define IRQ_HSMMC1              S5P_IRQ_VIC1(25)
-#define IRQ_OTG                 S5P_IRQ_VIC1(26)
-#define IRQ_DSI                 S5P_IRQ_VIC1(27)
-#define IRQ_RTC_ALARM           S5P_IRQ_VIC1(28)
-#define IRQ_TSI                 S5P_IRQ_VIC1(29)
-#define IRQ_PENDN               S5P_IRQ_VIC1(30)
-#define IRQ_TC                  IRQ_PENDN
-#define IRQ_ADC                 S5P_IRQ_VIC1(31)
-
-/* UART interrupts, S5P6450 has 5 UARTs */
-#define IRQ_S5P_UART_BASE4      (96)
-#define IRQ_S5P_UART_BASE5      (100)
-
-#define IRQ_S5P_UART_RX4        (IRQ_S5P_UART_BASE4 + UART_IRQ_RXD)
-#define IRQ_S5P_UART_TX4        (IRQ_S5P_UART_BASE4 + UART_IRQ_TXD)
-#define IRQ_S5P_UART_ERR4       (IRQ_S5P_UART_BASE4 + UART_IRQ_ERR)
-
-#define IRQ_S5P_UART_RX5        (IRQ_S5P_UART_BASE5 + UART_IRQ_RXD)
-#define IRQ_S5P_UART_TX5        (IRQ_S5P_UART_BASE5 + UART_IRQ_TXD)
-#define IRQ_S5P_UART_ERR5       (IRQ_S5P_UART_BASE5 + UART_IRQ_ERR)
-
-/* S3C compatibilty defines */
-#define IRQ_S3CUART_RX4         IRQ_S5P_UART_RX4
-#define IRQ_S3CUART_RX5         IRQ_S5P_UART_RX5
-
-#define IRQ_I2S0                IRQ_I2SV40
-
-#define IRQ_LCD_FIFO            IRQ_DISPCON0
-#define IRQ_LCD_VSYNC           IRQ_DISPCON1
-#define IRQ_LCD_SYSTEM          IRQ_DISPCON2
-
-/* S5P6450 EINT feature will be added */
-
-/*
- * Since the IRQ_EINT(x) are a linear mapping on s5p6440 we just defined
- * them as an IRQ_EINT(x) macro from S5P_IRQ_EINT_BASE which we place
- * after the pair of VICs.
- */
-
-#define S5P_IRQ_EINT_BASE       (S5P_IRQ_VIC1(31) + 6)
-
-#define S5P_EINT(x)             ((x) + S5P_IRQ_EINT_BASE)
-
-#define S5P_EINT_BASE1          (S5P_IRQ_EINT_BASE)
-/*
- * S5P6440 has 0-15 external interrupts in group 0. Only these can be used
- * to wake up from sleep. If request is beyond this range, by mistake, a large
- * return value for an irq number should be indication of something amiss.
- */
-#define S5P_EINT_BASE2          (0xf0000000)
-
-/*
- * Next the external interrupt groups. These are similar to the IRQ_EINT(x)
- * that they are sourced from the GPIO pins but with a different scheme for
- * priority and source indication.
- *
- * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO
- * interrupts, but for historical reasons they are kept apart from these
- * next interrupts.
- *
- * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the
- * machine specific support files.
- */
-
-/* Actually, #6 and #7 are missing in the EINT_GROUP1 */
-#define IRQ_EINT_GROUP1_NR      (15)
-#define IRQ_EINT_GROUP2_NR      (8)
-#define IRQ_EINT_GROUP5_NR      (7)
-#define IRQ_EINT_GROUP6_NR      (10)
-/* Actually, #0, #1 and #2 are missing in the EINT_GROUP8 */
-#define IRQ_EINT_GROUP8_NR      (11)
-
-#define IRQ_EINT_GROUP_BASE     S5P_EINT(16)
-#define IRQ_EINT_GROUP1_BASE    (IRQ_EINT_GROUP_BASE + 0)
-#define IRQ_EINT_GROUP2_BASE    (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR)
-#define IRQ_EINT_GROUP5_BASE    (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR)
-#define IRQ_EINT_GROUP6_BASE    (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR)
-#define IRQ_EINT_GROUP8_BASE    (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR)
-
-#define IRQ_EINT_GROUP(grp, x)  (IRQ_EINT_GROUP##grp##_BASE + (x))
-
-/* Set the default NR_IRQS */
-
-#define NR_IRQS                 (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
-
-#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h
deleted file mode 100644
index 50a6e96d6389..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/map.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/include/mach/map.h
- *
- * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * S5P64X0 - Memory map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_MAP_H
-#define __ASM_ARCH_MAP_H __FILE__
-
-#include <plat/map-base.h>
-#include <plat/map-s5p.h>
-
-#define S5P64X0_PA_SDRAM        0x20000000
-
-#define S5P64X0_PA_CHIPID       0xE0000000
-
-#define S5P64X0_PA_SYSCON       0xE0100000
-
-#define S5P64X0_PA_GPIO         0xE0308000
-
-#define S5P64X0_PA_VIC0         0xE4000000
-#define S5P64X0_PA_VIC1         0xE4100000
-
-#define S5P64X0_PA_SROMC        0xE7000000
-
-#define S5P64X0_PA_PDMA         0xE9000000
-
-#define S5P64X0_PA_TIMER        0xEA000000
-#define S5P64X0_PA_RTC          0xEA100000
-#define S5P64X0_PA_WDT          0xEA200000
-
-#define S5P6440_PA_IIC0         0xEC104000
-#define S5P6440_PA_IIC1         0xEC20F000
-#define S5P6450_PA_IIC0         0xEC100000
-#define S5P6450_PA_IIC1         0xEC200000
-
-#define S5P64X0_PA_SPI0         0xEC400000
-#define S5P64X0_PA_SPI1         0xEC500000
-
-#define S5P64X0_PA_HSOTG        0xED100000
-
-#define S5P64X0_PA_HSMMC(x)     (0xED800000 + ((x) * 0x100000))
-
-#define S5P64X0_PA_FB           0xEE000000
-
-#define S5P64X0_PA_I2S          0xF2000000
-#define S5P6450_PA_I2S1         0xF2800000
-#define S5P6450_PA_I2S2         0xF2900000
-
-#define S5P64X0_PA_PCM          0xF2100000
-
-#define S5P64X0_PA_ADC          0xF3000000
-
-/* Compatibiltiy Defines */
-
-#define S3C_PA_HSMMC0           S5P64X0_PA_HSMMC(0)
-#define S3C_PA_HSMMC1           S5P64X0_PA_HSMMC(1)
-#define S3C_PA_HSMMC2           S5P64X0_PA_HSMMC(2)
-#define S3C_PA_IIC              S5P6440_PA_IIC0
-#define S3C_PA_IIC1             S5P6440_PA_IIC1
-#define S3C_PA_RTC              S5P64X0_PA_RTC
-#define S3C_PA_WDT              S5P64X0_PA_WDT
-#define S3C_PA_FB               S5P64X0_PA_FB
-#define S3C_PA_SPI0             S5P64X0_PA_SPI0
-#define S3C_PA_SPI1             S5P64X0_PA_SPI1
-
-#define S5P_PA_CHIPID           S5P64X0_PA_CHIPID
-#define S5P_PA_SROMC            S5P64X0_PA_SROMC
-#define S5P_PA_SYSCON           S5P64X0_PA_SYSCON
-#define S5P_PA_TIMER            S5P64X0_PA_TIMER
-
-#define SAMSUNG_PA_ADC          S5P64X0_PA_ADC
-#define SAMSUNG_PA_TIMER        S5P64X0_PA_TIMER
-
-/* UART */
-
-#define S5P6440_PA_UART(x)      (0xEC000000 + ((x) * S3C_UART_OFFSET))
-#define S5P6450_PA_UART(x)      ((x < 5) ? (0xEC800000 + ((x) * S3C_UART_OFFSET)) : (0xEC000000))
-
-#define S5P_PA_UART0            S5P6450_PA_UART(0)
-#define S5P_PA_UART1            S5P6450_PA_UART(1)
-#define S5P_PA_UART2            S5P6450_PA_UART(2)
-#define S5P_PA_UART3            S5P6450_PA_UART(3)
-#define S5P_PA_UART4            S5P6450_PA_UART(4)
-#define S5P_PA_UART5            S5P6450_PA_UART(5)
-
-#define S5P_SZ_UART             SZ_256
-#define S3C_VA_UARTx(x)         (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
-
-#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/pm-core.h b/arch/arm/mach-s5p64x0/include/mach/pm-core.h
deleted file mode 100644
index 1e0eb65b2b82..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/pm-core.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/include/mach/pm-core.h
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * S5P64X0 - PM core support for arch/arm/plat-samsung/pm.c
- *
- * Based on PM core support for S3C64XX by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/serial_s3c.h>
-
-#include <mach/regs-gpio.h>
-
-static inline void s3c_pm_debug_init_uart(void)
-{
-        u32 tmp = __raw_readl(S5P64X0_CLK_GATE_PCLK);
-
-        /*
-         * As a note, since the S5P64X0 UARTs generally have multiple
-         * clock sources, we simply enable PCLK at the moment and hope
-         * that the resume settings for the UART are suitable for the
-         * use with PCLK.
-         */
-        tmp |= S5P64X0_CLK_GATE_PCLK_UART0;
-        tmp |= S5P64X0_CLK_GATE_PCLK_UART1;
-        tmp |= S5P64X0_CLK_GATE_PCLK_UART2;
-        tmp |= S5P64X0_CLK_GATE_PCLK_UART3;
-
-        __raw_writel(tmp, S5P64X0_CLK_GATE_PCLK);
-        udelay(10);
-}
-
-static inline void s3c_pm_arch_prepare_irqs(void)
-{
-        /* VIC should have already been taken care of */
-
-        /* clear any pending EINT0 interrupts */
-        __raw_writel(__raw_readl(S5P64X0_EINT0PEND), S5P64X0_EINT0PEND);
-}
-
-static inline void s3c_pm_arch_stop_clocks(void) { }
-static inline void s3c_pm_arch_show_resume_irqs(void) { }
-
-/*
- * make these defines, we currently do not have any need to change
- * the IRQ wake controls depending on the CPU we are running on
- */
-#define s3c_irqwake_eintallow   ((1 << 16) - 1)
-#define s3c_irqwake_intallow    (~0)
-
-static inline void s3c_pm_arch_update_uart(void __iomem *regs,
-                                        struct pm_uart_save *save)
-{
-        u32 ucon = __raw_readl(regs + S3C2410_UCON);
-        u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK;
-        u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK;
-        u32 new_ucon;
-        u32 delta;
-
-        /*
-         * S5P64X0 UART blocks only support level interrupts, so ensure that
-         * when we restore unused UART blocks we force the level interrupt
-         * settings.
-         */
-        save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL;
-
-        /*
-         * We have a constraint on changing the clock type of the UART
-         * between UCLKx and PCLK, so ensure that when we restore UCON
-         * that the CLK field is correctly modified if the bootloader
-         * has changed anything.
-         */
-        if (ucon_clk != save_clk) {
-                new_ucon = save->ucon;
-                delta = ucon_clk ^ save_clk;
-
-                /*
-                 * change from UCLKx => wrong PCLK,
-                 * either UCLK can be tested for by a bit-test
-                 * with UCLK0
-                 */
-                if (ucon_clk & S3C6400_UCON_UCLK0 &&
-                !(save_clk & S3C6400_UCON_UCLK0) &&
-                delta & S3C6400_UCON_PCLK2) {
-                        new_ucon &= ~S3C6400_UCON_UCLK0;
-                } else if (delta == S3C6400_UCON_PCLK2) {
-                        /*
-                         * as a precaution, don't change from
-                         * PCLK2 => PCLK or vice-versa
-                         */
-                        new_ucon ^= S3C6400_UCON_PCLK2;
-                }
-
-                S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n",
-                        ucon, new_ucon, save->ucon);
-                save->ucon = new_ucon;
-        }
-}
-
-static inline void s3c_pm_restored_gpios(void)
-{
-        /* ensure sleep mode has been cleared from the system */
-        __raw_writel(0, S5P64X0_SLPEN);
-}
-
-static inline void samsung_pm_saved_gpios(void)
-{
-        /*
-         * turn on the sleep mode and keep it there, as it seems that during
-         * suspend the xCON registers get re-set and thus you can end up with
-         * problems between going to sleep and resuming.
-         */
-        __raw_writel(S5P64X0_SLPEN_USE_xSLP, S5P64X0_SLPEN);
-}
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
deleted file mode 100644
index bd91112c813c..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * S5P64X0 - Clock register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_CLOCK_H
-#define __ASM_ARCH_REGS_CLOCK_H __FILE__
-
-#include <mach/map.h>
-
-#define S5P_CLKREG(x)                   (S3C_VA_SYS + (x))
-
-#define S5P64X0_APLL_CON                S5P_CLKREG(0x0C)
-#define S5P64X0_MPLL_CON                S5P_CLKREG(0x10)
-#define S5P64X0_EPLL_CON                S5P_CLKREG(0x14)
-#define S5P64X0_EPLL_CON_K              S5P_CLKREG(0x18)
-
-#define S5P64X0_CLK_SRC0                S5P_CLKREG(0x1C)
-
-#define S5P64X0_CLK_DIV0                S5P_CLKREG(0x20)
-#define S5P64X0_CLK_DIV1                S5P_CLKREG(0x24)
-#define S5P64X0_CLK_DIV2                S5P_CLKREG(0x28)
-
-#define S5P64X0_CLK_GATE_HCLK0          S5P_CLKREG(0x30)
-#define S5P64X0_CLK_GATE_PCLK           S5P_CLKREG(0x34)
-#define S5P64X0_CLK_GATE_SCLK0          S5P_CLKREG(0x38)
-#define S5P64X0_CLK_GATE_MEM0           S5P_CLKREG(0x3C)
-
-#define S5P64X0_CLK_DIV3                S5P_CLKREG(0x40)
-
-#define S5P64X0_CLK_GATE_HCLK1          S5P_CLKREG(0x44)
-#define S5P64X0_CLK_GATE_SCLK1          S5P_CLKREG(0x48)
-
-#define S5P6450_DPLL_CON                S5P_CLKREG(0x50)
-#define S5P6450_DPLL_CON_K              S5P_CLKREG(0x54)
-
-#define S5P64X0_AHB_CON0                S5P_CLKREG(0x100)
-#define S5P64X0_CLK_SRC1                S5P_CLKREG(0x10C)
-
-#define S5P64X0_SYS_ID                  S5P_CLKREG(0x118)
-#define S5P64X0_SYS_OTHERS              S5P_CLKREG(0x11C)
-
-#define S5P64X0_PWR_CFG                 S5P_CLKREG(0x804)
-#define S5P64X0_EINT_WAKEUP_MASK        S5P_CLKREG(0x808)
-#define S5P64X0_SLEEP_CFG               S5P_CLKREG(0x818)
-#define S5P64X0_PWR_STABLE              S5P_CLKREG(0x828)
-
-#define S5P64X0_OTHERS                  S5P_CLKREG(0x900)
-#define S5P64X0_WAKEUP_STAT             S5P_CLKREG(0x908)
-
-#define S5P64X0_INFORM0                 S5P_CLKREG(0xA00)
-
-#define S5P64X0_CLKDIV0_HCLK_SHIFT      (8)
-#define S5P64X0_CLKDIV0_HCLK_MASK       (0xF << S5P64X0_CLKDIV0_HCLK_SHIFT)
-
-/* HCLK GATE Registers */
-#define S5P64X0_CLK_GATE_HCLK1_FIMGVG   (1 << 2)
-#define S5P64X0_CLK_GATE_SCLK1_FIMGVG   (1 << 2)
-
-/* PCLK GATE Registers */
-#define S5P64X0_CLK_GATE_PCLK_UART3     (1 << 4)
-#define S5P64X0_CLK_GATE_PCLK_UART2     (1 << 3)
-#define S5P64X0_CLK_GATE_PCLK_UART1     (1 << 2)
-#define S5P64X0_CLK_GATE_PCLK_UART0     (1 << 1)
-
-#define S5P64X0_PWR_CFG_MMC1_DISABLE            (1 << 15)
-#define S5P64X0_PWR_CFG_MMC0_DISABLE            (1 << 14)
-#define S5P64X0_PWR_CFG_RTC_TICK_DISABLE        (1 << 11)
-#define S5P64X0_PWR_CFG_RTC_ALRM_DISABLE        (1 << 10)
-#define S5P64X0_PWR_CFG_WFI_MASK                (3 << 5)
-#define S5P64X0_PWR_CFG_WFI_SLEEP               (3 << 5)
-
-#define S5P64X0_SLEEP_CFG_OSC_EN        (1 << 0)
-
-#define S5P64X0_PWR_STABLE_PWR_CNT_VAL4 (4 << 0)
-
-#define S5P6450_OTHERS_DISABLE_INT      (1 << 31)
-#define S5P64X0_OTHERS_RET_UART         (1 << 26)
-#define S5P64X0_OTHERS_RET_MMC1         (1 << 25)
-#define S5P64X0_OTHERS_RET_MMC0         (1 << 24)
-#define S5P64X0_OTHERS_USB_SIG_MASK     (1 << 16)
-
-/* Compatibility defines */
-
-#define ARM_CLK_DIV                     S5P64X0_CLK_DIV0
-#define ARM_DIV_RATIO_SHIFT             0
-#define ARM_DIV_MASK                    (0xF << ARM_DIV_RATIO_SHIFT)
-
-#define S5P_EPLL_CON                    S5P64X0_EPLL_CON
-
-#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
deleted file mode 100644
index cfdfa4fdadf2..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * S5P64X0 - GPIO register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_GPIO_H
-#define __ASM_ARCH_REGS_GPIO_H __FILE__
-
-#include <mach/map.h>
-
-/* Base addresses for each of the banks */
-
-#define S5P64X0_GPA_BASE                (S5P_VA_GPIO + 0x0000)
-#define S5P64X0_GPB_BASE                (S5P_VA_GPIO + 0x0020)
-#define S5P64X0_GPC_BASE                (S5P_VA_GPIO + 0x0040)
-#define S5P64X0_GPF_BASE                (S5P_VA_GPIO + 0x00A0)
-#define S5P64X0_GPG_BASE                (S5P_VA_GPIO + 0x00C0)
-#define S5P64X0_GPH_BASE                (S5P_VA_GPIO + 0x00E0)
-#define S5P64X0_GPI_BASE                (S5P_VA_GPIO + 0x0100)
-#define S5P64X0_GPJ_BASE                (S5P_VA_GPIO + 0x0120)
-#define S5P64X0_GPN_BASE                (S5P_VA_GPIO + 0x0830)
-#define S5P64X0_GPP_BASE                (S5P_VA_GPIO + 0x0160)
-#define S5P64X0_GPR_BASE                (S5P_VA_GPIO + 0x0290)
-
-#define S5P6450_GPD_BASE                (S5P_VA_GPIO + 0x0060)
-#define S5P6450_GPK_BASE                (S5P_VA_GPIO + 0x0140)
-#define S5P6450_GPQ_BASE                (S5P_VA_GPIO + 0x0180)
-#define S5P6450_GPS_BASE                (S5P_VA_GPIO + 0x0300)
-
-#define S5P64X0_SPCON0                  (S5P_VA_GPIO + 0x1A0)
-#define S5P64X0_SPCON0_LCD_SEL_MASK     (0x3 << 0)
-#define S5P64X0_SPCON0_LCD_SEL_RGB      (0x1 << 0)
-#define S5P64X0_SPCON1                  (S5P_VA_GPIO + 0x2B0)
-
-#define S5P64X0_MEM0CONSLP0             (S5P_VA_GPIO + 0x1C0)
-#define S5P64X0_MEM0CONSLP1             (S5P_VA_GPIO + 0x1C4)
-#define S5P64X0_MEM0DRVCON              (S5P_VA_GPIO + 0x1D0)
-#define S5P64X0_MEM1DRVCON              (S5P_VA_GPIO + 0x1D4)
-
-#define S5P64X0_EINT12CON               (S5P_VA_GPIO + 0x200)
-#define S5P64X0_EINT12FLTCON            (S5P_VA_GPIO + 0x220)
-#define S5P64X0_EINT12MASK              (S5P_VA_GPIO + 0x240)
-
-/* External interrupt control registers for group0 */
-
-#define EINT0CON0_OFFSET                (0x900)
-#define EINT0FLTCON0_OFFSET             (0x910)
-#define EINT0FLTCON1_OFFSET             (0x914)
-#define EINT0MASK_OFFSET                (0x920)
-#define EINT0PEND_OFFSET                (0x924)
-
-#define S5P64X0_EINT0CON0               (S5P_VA_GPIO + EINT0CON0_OFFSET)
-#define S5P64X0_EINT0FLTCON0            (S5P_VA_GPIO + EINT0FLTCON0_OFFSET)
-#define S5P64X0_EINT0FLTCON1            (S5P_VA_GPIO + EINT0FLTCON1_OFFSET)
-#define S5P64X0_EINT0MASK               (S5P_VA_GPIO + EINT0MASK_OFFSET)
-#define S5P64X0_EINT0PEND               (S5P_VA_GPIO + EINT0PEND_OFFSET)
-
-#define S5P64X0_SLPEN                   (S5P_VA_GPIO + 0x930)
-#define S5P64X0_SLPEN_USE_xSLP          (1 << 0)
-
-#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-irq.h b/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
deleted file mode 100644
index d60397d1ff40..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * S5P64X0 - IRQ register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_IRQ_H
-#define __ASM_ARCH_REGS_IRQ_H __FILE__
-
-#include <mach/map.h>
-
-#endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-s5p64x0/irq-pm.c b/arch/arm/mach-s5p64x0/irq-pm.c
deleted file mode 100644
index 2ed921e095dc..000000000000
--- a/arch/arm/mach-s5p64x0/irq-pm.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/irq-pm.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * S5P64X0 - Interrupt handling Power Management
- *
- * Based on arch/arm/mach-s3c64xx/irq-pm.c by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/syscore_ops.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <linux/io.h>
-
-#include <plat/pm.h>
-
-#include <mach/regs-gpio.h>
-
-static struct sleep_save irq_save[] = {
-        SAVE_ITEM(S5P64X0_EINT0CON0),
-        SAVE_ITEM(S5P64X0_EINT0FLTCON0),
-        SAVE_ITEM(S5P64X0_EINT0FLTCON1),
-        SAVE_ITEM(S5P64X0_EINT0MASK),
-};
-
-static struct irq_grp_save {
-        u32     con;
-        u32     fltcon;
-        u32     mask;
-} eint_grp_save[4];
-
-#ifdef CONFIG_SERIAL_SAMSUNG
-static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS];
-#endif
-
-static int s5p64x0_irq_pm_suspend(void)
-{
-        struct irq_grp_save *grp = eint_grp_save;
-        int i;
-
-        S3C_PMDBG("%s: suspending IRQs\n", __func__);
-
-        s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
-
-#ifdef CONFIG_SERIAL_SAMSUNG
-        for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
-                irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM);
-#endif
-
-        for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
-                grp->con = __raw_readl(S5P64X0_EINT12CON + (i * 4));
-                grp->mask = __raw_readl(S5P64X0_EINT12MASK + (i * 4));
-                grp->fltcon = __raw_readl(S5P64X0_EINT12FLTCON + (i * 4));
-        }
-
-        return 0;
-}
-
-static void s5p64x0_irq_pm_resume(void)
-{
-        struct irq_grp_save *grp = eint_grp_save;
-        int i;
-
-        S3C_PMDBG("%s: resuming IRQs\n", __func__);
-
-        s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
-
-#ifdef CONFIG_SERIAL_SAMSUNG
-        for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
-                __raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM);
-#endif
-
-        for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
-                __raw_writel(grp->con, S5P64X0_EINT12CON + (i * 4));
-                __raw_writel(grp->mask, S5P64X0_EINT12MASK + (i * 4));
-                __raw_writel(grp->fltcon, S5P64X0_EINT12FLTCON + (i * 4));
-        }
-
-        S3C_PMDBG("%s: IRQ configuration restored\n", __func__);
-}
-
-static struct syscore_ops s5p64x0_irq_syscore_ops = {
-        .suspend = s5p64x0_irq_pm_suspend,
-        .resume  = s5p64x0_irq_pm_resume,
-};
-
-static int __init s5p64x0_syscore_init(void)
-{
-        register_syscore_ops(&s5p64x0_irq_syscore_ops);
-
-        return 0;
-}
-core_initcall(s5p64x0_syscore_init);
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
deleted file mode 100644
index 6840e197cb2d..000000000000
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ /dev/null
@@ -1,280 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/mach-smdk6440.c
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/i2c.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/clk.h>
-#include <linux/gpio.h>
-#include <linux/pwm_backlight.h>
-#include <linux/fb.h>
-#include <linux/mmc/host.h>
-
-#include <video/platform_lcd.h>
-#include <video/samsung_fimd.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-#include <mach/regs-gpio.h>
-
-#include <plat/gpio-cfg.h>
-#include <plat/clock.h>
-#include <plat/devs.h>
-#include <plat/cpu.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/pll.h>
-#include <plat/adc.h>
-#include <linux/platform_data/touchscreen-s3c2410.h>
-#include <plat/samsung-time.h>
-#include <plat/backlight.h>
-#include <plat/fb.h>
-#include <plat/sdhci.h>
-
-#include "common.h"
-#include "i2c.h"
-
-#define SMDK6440_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
-                                S3C2410_UCON_RXILEVEL |         \
-                                S3C2410_UCON_TXIRQMODE |        \
-                                S3C2410_UCON_RXIRQMODE |        \
-                                S3C2410_UCON_RXFIFO_TOI |       \
-                                S3C2443_UCON_RXERR_IRQEN)
-
-#define SMDK6440_ULCON_DEFAULT  S3C2410_LCON_CS8
-
-#define SMDK6440_UFCON_DEFAULT  (S3C2410_UFCON_FIFOMODE |       \
-                                S3C2440_UFCON_TXTRIG16 |        \
-                                S3C2410_UFCON_RXTRIG8)
-
-static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = {
-        [0] = {
-                .hwport         = 0,
-                .flags          = 0,
-                .ucon           = SMDK6440_UCON_DEFAULT,
-                .ulcon          = SMDK6440_ULCON_DEFAULT,
-                .ufcon          = SMDK6440_UFCON_DEFAULT,
-        },
-        [1] = {
-                .hwport         = 1,
-                .flags          = 0,
-                .ucon           = SMDK6440_UCON_DEFAULT,
-                .ulcon          = SMDK6440_ULCON_DEFAULT,
-                .ufcon          = SMDK6440_UFCON_DEFAULT,
-        },
-        [2] = {
-                .hwport         = 2,
-                .flags          = 0,
-                .ucon           = SMDK6440_UCON_DEFAULT,
-                .ulcon          = SMDK6440_ULCON_DEFAULT,
-                .ufcon          = SMDK6440_UFCON_DEFAULT,
-        },
-        [3] = {
-                .hwport         = 3,
-                .flags          = 0,
-                .ucon           = SMDK6440_UCON_DEFAULT,
-                .ulcon          = SMDK6440_ULCON_DEFAULT,
-                .ufcon          = SMDK6440_UFCON_DEFAULT,
-        },
-};
-
-/* Frame Buffer */
-static struct s3c_fb_pd_win smdk6440_fb_win0 = {
-        .max_bpp        = 32,
-        .default_bpp    = 24,
-        .xres           = 800,
-        .yres           = 480,
-};
-
-static struct fb_videomode smdk6440_lcd_timing = {
-        .left_margin    = 8,
-        .right_margin   = 13,
-        .upper_margin   = 7,
-        .lower_margin   = 5,
-        .hsync_len      = 3,
-        .vsync_len      = 1,
-        .xres           = 800,
-        .yres           = 480,
-};
-
-static struct s3c_fb_platdata smdk6440_lcd_pdata __initdata = {
-        .win[0]         = &smdk6440_fb_win0,
-        .vtiming        = &smdk6440_lcd_timing,
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-        .setup_gpio     = s5p64x0_fb_gpio_setup_24bpp,
-};
-
-/* LCD power controller */
-static void smdk6440_lte480_reset_power(struct plat_lcd_data *pd,
-                                         unsigned int power)
-{
-        int err;
-
-        if (power) {
-                err = gpio_request(S5P6440_GPN(5), "GPN");
-                if (err) {
-                        printk(KERN_ERR "failed to request GPN for lcd reset\n");
-                        return;
-                }
-
-                gpio_direction_output(S5P6440_GPN(5), 1);
-                gpio_set_value(S5P6440_GPN(5), 0);
-                gpio_set_value(S5P6440_GPN(5), 1);
-                gpio_free(S5P6440_GPN(5));
-        }
-}
-
-static struct plat_lcd_data smdk6440_lcd_power_data = {
-        .set_power      = smdk6440_lte480_reset_power,
-};
-
-static struct platform_device smdk6440_lcd_lte480wv = {
-        .name                   = "platform-lcd",
-        .dev.parent             = &s3c_device_fb.dev,
-        .dev.platform_data      = &smdk6440_lcd_power_data,
-};
-
-static struct platform_device *smdk6440_devices[] __initdata = {
-        &s3c_device_adc,
-        &s3c_device_rtc,
-        &s3c_device_i2c0,
-        &s3c_device_i2c1,
-        &samsung_device_pwm,
-        &s3c_device_ts,
-        &s3c_device_wdt,
-        &s5p6440_device_iis,
-        &s3c_device_fb,
-        &smdk6440_lcd_lte480wv,
-        &s3c_device_hsmmc0,
-        &s3c_device_hsmmc1,
-        &s3c_device_hsmmc2,
-};
-
-static struct s3c_sdhci_platdata smdk6440_hsmmc0_pdata __initdata = {
-        .cd_type        = S3C_SDHCI_CD_NONE,
-};
-
-static struct s3c_sdhci_platdata smdk6440_hsmmc1_pdata __initdata = {
-        .cd_type        = S3C_SDHCI_CD_INTERNAL,
-#if defined(CONFIG_S5P64X0_SD_CH1_8BIT)
-        .max_width      = 8,
-        .host_caps      = MMC_CAP_8_BIT_DATA,
-#endif
-};
-
-static struct s3c_sdhci_platdata smdk6440_hsmmc2_pdata __initdata = {
-        .cd_type        = S3C_SDHCI_CD_NONE,
-};
-
-static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = {
-        .flags          = 0,
-        .slave_addr     = 0x10,
-        .frequency      = 100*1000,
-        .sda_delay      = 100,
-        .cfg_gpio       = s5p6440_i2c0_cfg_gpio,
-};
-
-static struct s3c2410_platform_i2c s5p6440_i2c1_data __initdata = {
-        .flags          = 0,
-        .bus_num        = 1,
-        .slave_addr     = 0x10,
-        .frequency      = 100*1000,
-        .sda_delay      = 100,
-        .cfg_gpio       = s5p6440_i2c1_cfg_gpio,
-};
-
-static struct i2c_board_info smdk6440_i2c_devs0[] __initdata = {
-        { I2C_BOARD_INFO("24c08", 0x50), },
-        { I2C_BOARD_INFO("wm8580", 0x1b), },
-};
-
-static struct i2c_board_info smdk6440_i2c_devs1[] __initdata = {
-        /* To be populated */
-};
-
-/* LCD Backlight data */
-static struct samsung_bl_gpio_info smdk6440_bl_gpio_info = {
-        .no = S5P6440_GPF(15),
-        .func = S3C_GPIO_SFN(2),
-};
-
-static struct platform_pwm_backlight_data smdk6440_bl_data = {
-        .pwm_id = 1,
-        .enable_gpio = -1,
-};
-
-static void __init smdk6440_map_io(void)
-{
-        s5p64x0_init_io(NULL, 0);
-        s3c24xx_init_clocks(12000000);
-        s3c24xx_init_uarts(smdk6440_uartcfgs, ARRAY_SIZE(smdk6440_uartcfgs));
-        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
-}
-
-static void s5p6440_set_lcd_interface(void)
-{
-        unsigned int cfg;
-
-        /* select TFT LCD type (RGB I/F) */
-        cfg = __raw_readl(S5P64X0_SPCON0);
-        cfg &= ~S5P64X0_SPCON0_LCD_SEL_MASK;
-        cfg |= S5P64X0_SPCON0_LCD_SEL_RGB;
-        __raw_writel(cfg, S5P64X0_SPCON0);
-}
-
-static void __init smdk6440_machine_init(void)
-{
-        s3c24xx_ts_set_platdata(NULL);
-
-        s3c_i2c0_set_platdata(&s5p6440_i2c0_data);
-        s3c_i2c1_set_platdata(&s5p6440_i2c1_data);
-        i2c_register_board_info(0, smdk6440_i2c_devs0,
-                        ARRAY_SIZE(smdk6440_i2c_devs0));
-        i2c_register_board_info(1, smdk6440_i2c_devs1,
-                        ARRAY_SIZE(smdk6440_i2c_devs1));
-
-        s5p6440_set_lcd_interface();
-        s3c_fb_set_platdata(&smdk6440_lcd_pdata);
-
-        s3c_sdhci0_set_platdata(&smdk6440_hsmmc0_pdata);
-        s3c_sdhci1_set_platdata(&smdk6440_hsmmc1_pdata);
-        s3c_sdhci2_set_platdata(&smdk6440_hsmmc2_pdata);
-
-        platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices));
-
-        samsung_bl_set(&smdk6440_bl_gpio_info, &smdk6440_bl_data);
-}
-
-MACHINE_START(SMDK6440, "SMDK6440")
-        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        .atag_offset    = 0x100,
-
-        .init_irq       = s5p6440_init_irq,
-        .map_io         = smdk6440_map_io,
-        .init_machine   = smdk6440_machine_init,
-        .init_time      = samsung_timer_init,
-        .restart        = s5p64x0_restart,
-MACHINE_END
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
deleted file mode 100644
index fa1341c074ca..000000000000
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ /dev/null
@@ -1,299 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/mach-smdk6450.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/i2c.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/clk.h>
-#include <linux/gpio.h>
-#include <linux/pwm_backlight.h>
-#include <linux/fb.h>
-#include <linux/mmc/host.h>
-
-#include <video/platform_lcd.h>
-#include <video/samsung_fimd.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-#include <mach/regs-gpio.h>
-
-#include <plat/gpio-cfg.h>
-#include <plat/clock.h>
-#include <plat/devs.h>
-#include <plat/cpu.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/pll.h>
-#include <plat/adc.h>
-#include <linux/platform_data/touchscreen-s3c2410.h>
-#include <plat/samsung-time.h>
-#include <plat/backlight.h>
-#include <plat/fb.h>
-#include <plat/sdhci.h>
-
-#include "common.h"
-#include "i2c.h"
-
-#define SMDK6450_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
-                                S3C2410_UCON_RXILEVEL |         \
-                                S3C2410_UCON_TXIRQMODE |        \
-                                S3C2410_UCON_RXIRQMODE |        \
-                                S3C2410_UCON_RXFIFO_TOI |       \
-                                S3C2443_UCON_RXERR_IRQEN)
-
-#define SMDK6450_ULCON_DEFAULT  S3C2410_LCON_CS8
-
-#define SMDK6450_UFCON_DEFAULT  (S3C2410_UFCON_FIFOMODE |       \
-                                S3C2440_UFCON_TXTRIG16 |        \
-                                S3C2410_UFCON_RXTRIG8)
-
-static struct s3c2410_uartcfg smdk6450_uartcfgs[] __initdata = {
-        [0] = {
-                .hwport         = 0,
-                .flags          = 0,
-                .ucon           = SMDK6450_UCON_DEFAULT,
-                .ulcon          = SMDK6450_ULCON_DEFAULT,
-                .ufcon          = SMDK6450_UFCON_DEFAULT,
-        },
-        [1] = {
-                .hwport         = 1,
-                .flags          = 0,
-                .ucon           = SMDK6450_UCON_DEFAULT,
-                .ulcon          = SMDK6450_ULCON_DEFAULT,
-                .ufcon          = SMDK6450_UFCON_DEFAULT,
-        },
-        [2] = {
-                .hwport         = 2,
-                .flags          = 0,
-                .ucon           = SMDK6450_UCON_DEFAULT,
-                .ulcon          = SMDK6450_ULCON_DEFAULT,
-                .ufcon          = SMDK6450_UFCON_DEFAULT,
-        },
-        [3] = {
-                .hwport         = 3,
-                .flags          = 0,
-                .ucon           = SMDK6450_UCON_DEFAULT,
-                .ulcon          = SMDK6450_ULCON_DEFAULT,
-                .ufcon          = SMDK6450_UFCON_DEFAULT,
-        },
-#if CONFIG_SERIAL_SAMSUNG_UARTS > 4
-        [4] = {
-                .hwport         = 4,
-                .flags          = 0,
-                .ucon           = SMDK6450_UCON_DEFAULT,
-                .ulcon          = SMDK6450_ULCON_DEFAULT,
-                .ufcon          = SMDK6450_UFCON_DEFAULT,
-        },
-#endif
-#if CONFIG_SERIAL_SAMSUNG_UARTS > 5
-        [5] = {
-                .hwport         = 5,
-                .flags          = 0,
-                .ucon           = SMDK6450_UCON_DEFAULT,
-                .ulcon          = SMDK6450_ULCON_DEFAULT,
-                .ufcon          = SMDK6450_UFCON_DEFAULT,
-        },
-#endif
-};
-
-/* Frame Buffer */
-static struct s3c_fb_pd_win smdk6450_fb_win0 = {
-        .max_bpp        = 32,
-        .default_bpp    = 24,
-        .xres           = 800,
-        .yres           = 480,
-};
-
-static struct fb_videomode smdk6450_lcd_timing = {
-        .left_margin    = 8,
-        .right_margin   = 13,
-        .upper_margin   = 7,
-        .lower_margin   = 5,
-        .hsync_len      = 3,
-        .vsync_len      = 1,
-        .xres           = 800,
-        .yres           = 480,
-};
-
-static struct s3c_fb_platdata smdk6450_lcd_pdata __initdata = {
-        .win[0]         = &smdk6450_fb_win0,
-        .vtiming        = &smdk6450_lcd_timing,
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-        .setup_gpio     = s5p64x0_fb_gpio_setup_24bpp,
-};
-
-/* LCD power controller */
-static void smdk6450_lte480_reset_power(struct plat_lcd_data *pd,
-                                         unsigned int power)
-{
-        int err;
-
-        if (power) {
-                err = gpio_request(S5P6450_GPN(5), "GPN");
-                if (err) {
-                        printk(KERN_ERR "failed to request GPN for lcd reset\n");
-                        return;
-                }
-
-                gpio_direction_output(S5P6450_GPN(5), 1);
-                gpio_set_value(S5P6450_GPN(5), 0);
-                gpio_set_value(S5P6450_GPN(5), 1);
-                gpio_free(S5P6450_GPN(5));
-        }
-}
-
-static struct plat_lcd_data smdk6450_lcd_power_data = {
-        .set_power      = smdk6450_lte480_reset_power,
-};
-
-static struct platform_device smdk6450_lcd_lte480wv = {
-        .name                   = "platform-lcd",
-        .dev.parent             = &s3c_device_fb.dev,
-        .dev.platform_data      = &smdk6450_lcd_power_data,
-};
-
-static struct platform_device *smdk6450_devices[] __initdata = {
-        &s3c_device_adc,
-        &s3c_device_rtc,
-        &s3c_device_i2c0,
-        &s3c_device_i2c1,
-        &samsung_device_pwm,
-        &s3c_device_ts,
-        &s3c_device_wdt,
-        &s5p6450_device_iis0,
-        &s3c_device_fb,
-        &smdk6450_lcd_lte480wv,
-        &s3c_device_hsmmc0,
-        &s3c_device_hsmmc1,
-        &s3c_device_hsmmc2,
-        /* s5p6450_device_spi0 will be added */
-};
-
-static struct s3c_sdhci_platdata smdk6450_hsmmc0_pdata __initdata = {
-        .cd_type        = S3C_SDHCI_CD_NONE,
-};
-
-static struct s3c_sdhci_platdata smdk6450_hsmmc1_pdata __initdata = {
-        .cd_type        = S3C_SDHCI_CD_NONE,
-#if defined(CONFIG_S5P64X0_SD_CH1_8BIT)
-        .max_width      = 8,
-        .host_caps      = MMC_CAP_8_BIT_DATA,
-#endif
-};
-
-static struct s3c_sdhci_platdata smdk6450_hsmmc2_pdata __initdata = {
-        .cd_type        = S3C_SDHCI_CD_NONE,
-};
-
-static struct s3c2410_platform_i2c s5p6450_i2c0_data __initdata = {
-        .flags          = 0,
-        .slave_addr     = 0x10,
-        .frequency      = 100*1000,
-        .sda_delay      = 100,
-        .cfg_gpio       = s5p6450_i2c0_cfg_gpio,
-};
-
-static struct s3c2410_platform_i2c s5p6450_i2c1_data __initdata = {
-        .flags          = 0,
-        .bus_num        = 1,
-        .slave_addr     = 0x10,
-        .frequency      = 100*1000,
-        .sda_delay      = 100,
-        .cfg_gpio       = s5p6450_i2c1_cfg_gpio,
-};
-
-static struct i2c_board_info smdk6450_i2c_devs0[] __initdata = {
-        { I2C_BOARD_INFO("wm8580", 0x1b), },
-        { I2C_BOARD_INFO("24c08", 0x50), },     /* Samsung KS24C080C EEPROM */
-};
-
-static struct i2c_board_info smdk6450_i2c_devs1[] __initdata = {
-        { I2C_BOARD_INFO("24c128", 0x57), },/* Samsung S524AD0XD1 EEPROM */
-};
-
-/* LCD Backlight data */
-static struct samsung_bl_gpio_info smdk6450_bl_gpio_info = {
-        .no = S5P6450_GPF(15),
-        .func = S3C_GPIO_SFN(2),
-};
-
-static struct platform_pwm_backlight_data smdk6450_bl_data = {
-        .pwm_id = 1,
-        .enable_gpio = -1,
-};
-
-static void __init smdk6450_map_io(void)
-{
-        s5p64x0_init_io(NULL, 0);
-        s3c24xx_init_clocks(19200000);
-        s3c24xx_init_uarts(smdk6450_uartcfgs, ARRAY_SIZE(smdk6450_uartcfgs));
-        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
-}
-
-static void s5p6450_set_lcd_interface(void)
-{
-        unsigned int cfg;
-
-        /* select TFT LCD type (RGB I/F) */
-        cfg = __raw_readl(S5P64X0_SPCON0);
-        cfg &= ~S5P64X0_SPCON0_LCD_SEL_MASK;
-        cfg |= S5P64X0_SPCON0_LCD_SEL_RGB;
-        __raw_writel(cfg, S5P64X0_SPCON0);
-}
-
-static void __init smdk6450_machine_init(void)
-{
-        s3c24xx_ts_set_platdata(NULL);
-
-        s3c_i2c0_set_platdata(&s5p6450_i2c0_data);
-        s3c_i2c1_set_platdata(&s5p6450_i2c1_data);
-        i2c_register_board_info(0, smdk6450_i2c_devs0,
-                        ARRAY_SIZE(smdk6450_i2c_devs0));
-        i2c_register_board_info(1, smdk6450_i2c_devs1,
-                        ARRAY_SIZE(smdk6450_i2c_devs1));
-
-        s5p6450_set_lcd_interface();
-        s3c_fb_set_platdata(&smdk6450_lcd_pdata);
-
-        s3c_sdhci0_set_platdata(&smdk6450_hsmmc0_pdata);
-        s3c_sdhci1_set_platdata(&smdk6450_hsmmc1_pdata);
-        s3c_sdhci2_set_platdata(&smdk6450_hsmmc2_pdata);
-
-        platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices));
-
-        samsung_bl_set(&smdk6450_bl_gpio_info, &smdk6450_bl_data);
-}
-
-MACHINE_START(SMDK6450, "SMDK6450")
-        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        .atag_offset    = 0x100,
-
-        .init_irq       = s5p6450_init_irq,
-        .map_io         = smdk6450_map_io,
-        .init_machine   = smdk6450_machine_init,
-        .init_time      = samsung_timer_init,
-        .restart        = s5p64x0_restart,
-MACHINE_END
diff --git a/arch/arm/mach-s5p64x0/pm.c b/arch/arm/mach-s5p64x0/pm.c
deleted file mode 100644
index ec8229cee716..000000000000
--- a/arch/arm/mach-s5p64x0/pm.c
+++ /dev/null
@@ -1,202 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/pm.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * S5P64X0 Power Management Support
- *
- * Based on arch/arm/mach-s3c64xx/pm.c by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/suspend.h>
-#include <linux/syscore_ops.h>
-#include <linux/io.h>
-
-#include <plat/cpu.h>
-#include <plat/pm.h>
-#include <plat/wakeup-mask.h>
-
-#include <mach/regs-clock.h>
-#include <mach/regs-gpio.h>
-
-static struct sleep_save s5p64x0_core_save[] = {
-        SAVE_ITEM(S5P64X0_APLL_CON),
-        SAVE_ITEM(S5P64X0_MPLL_CON),
-        SAVE_ITEM(S5P64X0_EPLL_CON),
-        SAVE_ITEM(S5P64X0_EPLL_CON_K),
-        SAVE_ITEM(S5P64X0_CLK_SRC0),
-        SAVE_ITEM(S5P64X0_CLK_SRC1),
-        SAVE_ITEM(S5P64X0_CLK_DIV0),
-        SAVE_ITEM(S5P64X0_CLK_DIV1),
-        SAVE_ITEM(S5P64X0_CLK_DIV2),
-        SAVE_ITEM(S5P64X0_CLK_DIV3),
-        SAVE_ITEM(S5P64X0_CLK_GATE_MEM0),
-        SAVE_ITEM(S5P64X0_CLK_GATE_HCLK1),
-        SAVE_ITEM(S5P64X0_CLK_GATE_SCLK1),
-};
-
-static struct sleep_save s5p64x0_misc_save[] = {
-        SAVE_ITEM(S5P64X0_AHB_CON0),
-        SAVE_ITEM(S5P64X0_SPCON0),
-        SAVE_ITEM(S5P64X0_SPCON1),
-        SAVE_ITEM(S5P64X0_MEM0CONSLP0),
-        SAVE_ITEM(S5P64X0_MEM0CONSLP1),
-        SAVE_ITEM(S5P64X0_MEM0DRVCON),
-        SAVE_ITEM(S5P64X0_MEM1DRVCON),
-};
-
-/* DPLL is present only in S5P6450 */
-static struct sleep_save s5p6450_core_save[] = {
-        SAVE_ITEM(S5P6450_DPLL_CON),
-        SAVE_ITEM(S5P6450_DPLL_CON_K),
-};
-
-void s3c_pm_configure_extint(void)
-{
-        __raw_writel(s3c_irqwake_eintmask, S5P64X0_EINT_WAKEUP_MASK);
-}
-
-void s3c_pm_restore_core(void)
-{
-        __raw_writel(0, S5P64X0_EINT_WAKEUP_MASK);
-
-        s3c_pm_do_restore_core(s5p64x0_core_save,
-                                ARRAY_SIZE(s5p64x0_core_save));
-
-        if (soc_is_s5p6450())
-                s3c_pm_do_restore_core(s5p6450_core_save,
-                                ARRAY_SIZE(s5p6450_core_save));
-
-        s3c_pm_do_restore(s5p64x0_misc_save, ARRAY_SIZE(s5p64x0_misc_save));
-}
-
-void s3c_pm_save_core(void)
-{
-        s3c_pm_do_save(s5p64x0_misc_save, ARRAY_SIZE(s5p64x0_misc_save));
-
-        if (soc_is_s5p6450())
-                s3c_pm_do_save(s5p6450_core_save,
-                                ARRAY_SIZE(s5p6450_core_save));
-
-        s3c_pm_do_save(s5p64x0_core_save, ARRAY_SIZE(s5p64x0_core_save));
-}
-
-static int s5p64x0_cpu_suspend(unsigned long arg)
-{
-        unsigned long tmp = 0;
-
-        /*
-         * Issue the standby signal into the pm unit. Note, we
-         * issue a write-buffer drain just in case.
-         */
-        asm("b 1f\n\t"
-            ".align 5\n\t"
-            "1:\n\t"
-            "mcr p15, 0, %0, c7, c10, 5\n\t"
-            "mcr p15, 0, %0, c7, c10, 4\n\t"
-            "mcr p15, 0, %0, c7, c0, 4" : : "r" (tmp));
-
-        pr_info("Failed to suspend the system\n");
-        return 1; /* Aborting suspend */
-}
-
-/* mapping of interrupts to parts of the wakeup mask */
-static struct samsung_wakeup_mask s5p64x0_wake_irqs[] = {
-        { .irq = IRQ_RTC_ALARM, .bit = S5P64X0_PWR_CFG_RTC_ALRM_DISABLE, },
-        { .irq = IRQ_RTC_TIC,   .bit = S5P64X0_PWR_CFG_RTC_TICK_DISABLE, },
-        { .irq = IRQ_HSMMC0,    .bit = S5P64X0_PWR_CFG_MMC0_DISABLE, },
-        { .irq = IRQ_HSMMC1,    .bit = S5P64X0_PWR_CFG_MMC1_DISABLE, },
-};
-
-static void s5p64x0_pm_prepare(void)
-{
-        u32 tmp;
-
-        samsung_sync_wakemask(S5P64X0_PWR_CFG,
-                        s5p64x0_wake_irqs, ARRAY_SIZE(s5p64x0_wake_irqs));
-
-        /* store the resume address in INFORM0 register */
-        __raw_writel(virt_to_phys(s3c_cpu_resume), S5P64X0_INFORM0);
-
-        /* setup clock gating for FIMGVG block */
-        __raw_writel((__raw_readl(S5P64X0_CLK_GATE_HCLK1) | \
-                (S5P64X0_CLK_GATE_HCLK1_FIMGVG)), S5P64X0_CLK_GATE_HCLK1);
-        __raw_writel((__raw_readl(S5P64X0_CLK_GATE_SCLK1) | \
-                (S5P64X0_CLK_GATE_SCLK1_FIMGVG)), S5P64X0_CLK_GATE_SCLK1);
-
-        /* Configure the stabilization counter with wait time required */
-        __raw_writel(S5P64X0_PWR_STABLE_PWR_CNT_VAL4, S5P64X0_PWR_STABLE);
-
-        /* set WFI to SLEEP mode configuration */
-        tmp = __raw_readl(S5P64X0_SLEEP_CFG);
-        tmp &= ~(S5P64X0_SLEEP_CFG_OSC_EN);
-        __raw_writel(tmp, S5P64X0_SLEEP_CFG);
-
-        tmp = __raw_readl(S5P64X0_PWR_CFG);
-        tmp &= ~(S5P64X0_PWR_CFG_WFI_MASK);
-        tmp |= S5P64X0_PWR_CFG_WFI_SLEEP;
-        __raw_writel(tmp, S5P64X0_PWR_CFG);
-
-        /*
-         * set OTHERS register to disable interrupt before going to
-         * sleep. This bit is present only in S5P6450, it is reserved
-         * in S5P6440.
-         */
-        if (soc_is_s5p6450()) {
-                tmp = __raw_readl(S5P64X0_OTHERS);
-                tmp |= S5P6450_OTHERS_DISABLE_INT;
-                __raw_writel(tmp, S5P64X0_OTHERS);
-        }
-
-        /* ensure previous wakeup state is cleared before sleeping */
-        __raw_writel(__raw_readl(S5P64X0_WAKEUP_STAT), S5P64X0_WAKEUP_STAT);
-
-}
-
-static int s5p64x0_pm_add(struct device *dev, struct subsys_interface *sif)
-{
-        pm_cpu_prep = s5p64x0_pm_prepare;
-        pm_cpu_sleep = s5p64x0_cpu_suspend;
-
-        return 0;
-}
-
-static struct subsys_interface s5p64x0_pm_interface = {
-        .name           = "s5p64x0_pm",
-        .subsys         = &s5p64x0_subsys,
-        .add_dev        = s5p64x0_pm_add,
-};
-
-static __init int s5p64x0_pm_drvinit(void)
-{
-        s3c_pm_init();
-
-        return subsys_interface_register(&s5p64x0_pm_interface);
-}
-arch_initcall(s5p64x0_pm_drvinit);
-
-static void s5p64x0_pm_resume(void)
-{
-        u32 tmp;
-
-        tmp = __raw_readl(S5P64X0_OTHERS);
-        tmp |= (S5P64X0_OTHERS_RET_MMC0 | S5P64X0_OTHERS_RET_MMC1 | \
-                        S5P64X0_OTHERS_RET_UART);
-        __raw_writel(tmp , S5P64X0_OTHERS);
-}
-
-static struct syscore_ops s5p64x0_pm_syscore_ops = {
-        .resume         = s5p64x0_pm_resume,
-};
-
-static __init int s5p64x0_pm_syscore_init(void)
-{
-        register_syscore_ops(&s5p64x0_pm_syscore_ops);
-
-        return 0;
-}
-arch_initcall(s5p64x0_pm_syscore_init);
diff --git a/arch/arm/mach-s5p64x0/setup-fb-24bpp.c b/arch/arm/mach-s5p64x0/setup-fb-24bpp.c
deleted file mode 100644
index f346ee4af54d..000000000000
--- a/arch/arm/mach-s5p64x0/setup-fb-24bpp.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/setup-fb-24bpp.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com/
- *
- * Base S5P64X0 GPIO setup information for LCD framebuffer
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/fb.h>
-#include <linux/gpio.h>
-
-#include <plat/cpu.h>
-#include <plat/fb.h>
-#include <plat/gpio-cfg.h>
-
-void s5p64x0_fb_gpio_setup_24bpp(void)
-{
-        if (soc_is_s5p6440()) {
-                s3c_gpio_cfgrange_nopull(S5P6440_GPI(0), 16, S3C_GPIO_SFN(2));
-                s3c_gpio_cfgrange_nopull(S5P6440_GPJ(0), 12, S3C_GPIO_SFN(2));
-        } else if (soc_is_s5p6450()) {
-                s3c_gpio_cfgrange_nopull(S5P6450_GPI(0), 16, S3C_GPIO_SFN(2));
-                s3c_gpio_cfgrange_nopull(S5P6450_GPJ(0), 12, S3C_GPIO_SFN(2));
-        }
-}
diff --git a/arch/arm/mach-s5p64x0/setup-i2c0.c b/arch/arm/mach-s5p64x0/setup-i2c0.c
deleted file mode 100644
index 569b76ac98cb..000000000000
--- a/arch/arm/mach-s5p64x0/setup-i2c0.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/setup-i2c0.c
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * I2C0 GPIO configuration.
- *
- * Based on plat-s3c64x0/setup-i2c0.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/gpio.h>
-
-struct platform_device; /* don't need the contents */
-
-#include <plat/gpio-cfg.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-
-#include "i2c.h"
-
-void s5p6440_i2c0_cfg_gpio(struct platform_device *dev)
-{
-        s3c_gpio_cfgall_range(S5P6440_GPB(5), 2,
-                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-}
-
-void s5p6450_i2c0_cfg_gpio(struct platform_device *dev)
-{
-        s3c_gpio_cfgall_range(S5P6450_GPB(5), 2,
-                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-}
-
-void s3c_i2c0_cfg_gpio(struct platform_device *dev) { }
diff --git a/arch/arm/mach-s5p64x0/setup-i2c1.c b/arch/arm/mach-s5p64x0/setup-i2c1.c
deleted file mode 100644
index 867374e6d0bc..000000000000
--- a/arch/arm/mach-s5p64x0/setup-i2c1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/* linux/arch/arm/mach-s5p64xx/setup-i2c1.c
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * I2C1 GPIO configuration.
- *
- * Based on plat-s3c64xx/setup-i2c0.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/gpio.h>
-
-struct platform_device; /* don't need the contents */
-
-#include <plat/gpio-cfg.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-
-#include "i2c.h"
-
-void s5p6440_i2c1_cfg_gpio(struct platform_device *dev)
-{
-        s3c_gpio_cfgall_range(S5P6440_GPR(9), 2,
-                              S3C_GPIO_SFN(6), S3C_GPIO_PULL_UP);
-}
-
-void s5p6450_i2c1_cfg_gpio(struct platform_device *dev)
-{
-        s3c_gpio_cfgall_range(S5P6450_GPR(9), 2,
-                              S3C_GPIO_SFN(6), S3C_GPIO_PULL_UP);
-}
-
-void s3c_i2c1_cfg_gpio(struct platform_device *dev) { }
diff --git a/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c b/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
deleted file mode 100644
index 8410af0d12bf..000000000000
--- a/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5P64X0 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-
-#include <mach/regs-gpio.h>
-#include <mach/regs-clock.h>
-
-#include <plat/gpio-cfg.h>
-#include <plat/sdhci.h>
-#include <plat/cpu.h>
-
-void s5p64x0_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
-{
-        struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-
-        /* Set all the necessary GPG pins to special-function 2 */
-        if (soc_is_s5p6450())
-                s3c_gpio_cfgrange_nopull(S5P6450_GPG(0), 2 + width,
-                                         S3C_GPIO_SFN(2));
-        else
-                s3c_gpio_cfgrange_nopull(S5P6440_GPG(0), 2 + width,
-                                         S3C_GPIO_SFN(2));
-
-        /* Set GPG[6] pin to special-function 2 - MMC0 CDn */
-        if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
-                if (soc_is_s5p6450()) {
-                        s3c_gpio_setpull(S5P6450_GPG(6), S3C_GPIO_PULL_UP);
-                        s3c_gpio_cfgpin(S5P6450_GPG(6), S3C_GPIO_SFN(2));
-                } else {
-                        s3c_gpio_setpull(S5P6440_GPG(6), S3C_GPIO_PULL_UP);
-                        s3c_gpio_cfgpin(S5P6440_GPG(6), S3C_GPIO_SFN(2));
-                }
-        }
-}
-
-void s5p64x0_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
-{
-        struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-
-        /* Set GPH[0:1] pins to special-function 2 - CLK and CMD */
-        if (soc_is_s5p6450())
-                s3c_gpio_cfgrange_nopull(S5P6450_GPH(0), 2, S3C_GPIO_SFN(2));
-        else
-                s3c_gpio_cfgrange_nopull(S5P6440_GPH(0), 2 , S3C_GPIO_SFN(2));
-
-        switch (width) {
-        case 8:
-                /* Set data pins GPH[6:9] special-function 2 */
-                if (soc_is_s5p6450())
-                        s3c_gpio_cfgrange_nopull(S5P6450_GPH(6), 4,
-                                                 S3C_GPIO_SFN(2));
-                else
-                        s3c_gpio_cfgrange_nopull(S5P6440_GPH(6), 4,
-                                                 S3C_GPIO_SFN(2));
-        case 4:
-                /* set data pins GPH[2:5] special-function 2 */
-                if (soc_is_s5p6450())
-                        s3c_gpio_cfgrange_nopull(S5P6450_GPH(2), 4,
-                                                 S3C_GPIO_SFN(2));
-                else
-                        s3c_gpio_cfgrange_nopull(S5P6440_GPH(2), 4,
-                                                 S3C_GPIO_SFN(2));
-        default:
-                break;
-        }
-
-        /* Set GPG[6] pin to special-funtion 3 : MMC1 CDn */
-        if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
-                if (soc_is_s5p6450()) {
-                        s3c_gpio_setpull(S5P6450_GPG(6), S3C_GPIO_PULL_UP);
-                        s3c_gpio_cfgpin(S5P6450_GPG(6), S3C_GPIO_SFN(3));
-                } else {
-                        s3c_gpio_setpull(S5P6440_GPG(6), S3C_GPIO_PULL_UP);
-                        s3c_gpio_cfgpin(S5P6440_GPG(6), S3C_GPIO_SFN(3));
-                }
-        }
-}
-
-void s5p6440_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
-{
-        /* Set GPC[4:5] pins to special-function 3 - CLK and CMD */
-        s3c_gpio_cfgrange_nopull(S5P6440_GPC(4), 2, S3C_GPIO_SFN(3));
-
-        /* Set data pins GPH[6:9] pins to special-function 3 */
-        s3c_gpio_cfgrange_nopull(S5P6440_GPH(6), 4, S3C_GPIO_SFN(3));
-}
-
-void s5p6450_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
-{
-        /* Set all the necessary GPG pins to special-function 3 */
-        s3c_gpio_cfgrange_nopull(S5P6450_GPG(7), 2 + width, S3C_GPIO_SFN(3));
-}
diff --git a/arch/arm/mach-s5p64x0/setup-spi.c b/arch/arm/mach-s5p64x0/setup-spi.c
deleted file mode 100644
index 7664356720ca..000000000000
--- a/arch/arm/mach-s5p64x0/setup-spi.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/setup-spi.c
- *
- * Copyright (C) 2011 Samsung Electronics Ltd.
- *              http://www.samsung.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/gpio.h>
-#include <plat/gpio-cfg.h>
-
-#ifdef CONFIG_S3C64XX_DEV_SPI0
-int s3c64xx_spi0_cfg_gpio(void)
-{
-        if (soc_is_s5p6450())
-                s3c_gpio_cfgall_range(S5P6450_GPC(0), 3,
-                                        S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-        else
-                s3c_gpio_cfgall_range(S5P6440_GPC(0), 3,
-                                        S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-        return 0;
-}
-#endif
-
-#ifdef CONFIG_S3C64XX_DEV_SPI1
-int s3c64xx_spi1_cfg_gpio(void)
-{
-        if (soc_is_s5p6450())
-                s3c_gpio_cfgall_range(S5P6450_GPC(4), 3,
-                                        S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-        else
-                s3c_gpio_cfgall_range(S5P6440_GPC(4), 3,
-                                        S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-        return 0;
-}
-#endif
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
deleted file mode 100644
index c5e3a969b063..000000000000
--- a/arch/arm/mach-s5pc100/Kconfig
+++ /dev/null
@@ -1,81 +0,0 @@
-# Copyright 2009 Samsung Electronics Co.
-#       Byungho Min <bhmin@samsung.com>
-#
-# Licensed under GPLv2
-
-# Configuration options for the S5PC100 CPU
-
-if ARCH_S5PC100
-
-config CPU_S5PC100
-        bool
-        select ARM_AMBA
-        select PL330_DMA if DMADEVICES
-        select S5P_EXT_INT
-        help
-          Enable S5PC100 CPU support
-
-config S5PC100_SETUP_FB_24BPP
-        bool
-        help
-          Common setup code for S5PC1XX with an 24bpp RGB display helper.
-
-config S5PC100_SETUP_I2C1
-        bool
-        help
-          Common setup code for i2c bus 1.
-
-config S5PC100_SETUP_IDE
-        bool
-        help
-          Common setup code for S5PC100 IDE GPIO configurations
-
-config S5PC100_SETUP_KEYPAD
-        bool
-        help
-          Common setup code for KEYPAD GPIO configurations.
-
-config S5PC100_SETUP_SDHCI
-        bool
-        select S5PC100_SETUP_SDHCI_GPIO
-        help
-          Internal helper functions for S5PC100 based SDHCI systems
-
-config S5PC100_SETUP_SDHCI_GPIO
-        bool
-        help
-          Common setup code for SDHCI gpio.
-
-config S5PC100_SETUP_SPI
-        bool
-        help
-          Common setup code for SPI GPIO configurations.
-
-config MACH_SMDKC100
-        bool "SMDKC100"
-        select CPU_S5PC100
-        select S3C_DEV_FB
-        select S3C_DEV_HSMMC
-        select S3C_DEV_HSMMC1
-        select S3C_DEV_HSMMC2
-        select S3C_DEV_I2C1
-        select S3C_DEV_RTC
-        select S3C_DEV_WDT
-        select S5PC100_SETUP_FB_24BPP
-        select S5PC100_SETUP_I2C1
-        select S5PC100_SETUP_IDE
-        select S5PC100_SETUP_KEYPAD
-        select S5PC100_SETUP_SDHCI
-        select S5P_DEV_FIMC0
-        select S5P_DEV_FIMC1
-        select S5P_DEV_FIMC2
-        select SAMSUNG_DEV_ADC
-        select SAMSUNG_DEV_BACKLIGHT
-        select SAMSUNG_DEV_IDE
-        select SAMSUNG_DEV_KEYPAD
-        select SAMSUNG_DEV_PWM
-        select SAMSUNG_DEV_TS
-        help
-          Machine support for the Samsung SMDKC100
-
-endif
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
deleted file mode 100644
index 118c711f74e8..000000000000
--- a/arch/arm/mach-s5pc100/Makefile
+++ /dev/null
@@ -1,32 +0,0 @@
-# arch/arm/mach-s5pc100/Makefile
-#
-# Copyright 2009 Samsung Electronics Co.
-#
-# Licensed under GPLv2
-
-obj-y                           :=
-obj-m                           :=
-obj-n                           :=
-obj-                            :=
-
-# Core
-
-obj-y                           += common.o clock.o
-
-obj-y                           += dma.o
-
-# machine support
-
-obj-$(CONFIG_MACH_SMDKC100)     += mach-smdkc100.o
-
-# device support
-
-obj-y                           += dev-audio.o
-
-obj-y                                   += setup-i2c0.o
-obj-$(CONFIG_S5PC100_SETUP_FB_24BPP)    += setup-fb-24bpp.o
-obj-$(CONFIG_S5PC100_SETUP_I2C1)        += setup-i2c1.o
-obj-$(CONFIG_S5PC100_SETUP_IDE)         += setup-ide.o
-obj-$(CONFIG_S5PC100_SETUP_KEYPAD)      += setup-keypad.o
-obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
-obj-$(CONFIG_S5PC100_SETUP_SPI)         += setup-spi.o
diff --git a/arch/arm/mach-s5pc100/Makefile.boot b/arch/arm/mach-s5pc100/Makefile.boot
deleted file mode 100644
index 79ece4055b02..000000000000
--- a/arch/arm/mach-s5pc100/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
-   zreladdr-y   += 0x20008000
-params_phys-y   := 0x20000100
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
deleted file mode 100644
index d0dc10ee7729..000000000000
--- a/arch/arm/mach-s5pc100/clock.c
+++ /dev/null
@@ -1,1361 +0,0 @@
-/* linux/arch/arm/mach-s5pc100/clock.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5PC100 - Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-
-#include <mach/map.h>
-
-#include <plat/cpu-freq.h>
-#include <mach/regs-clock.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-
-#include "common.h"
-
-static struct clk s5p_clk_otgphy = {
-        .name           = "otg_phy",
-};
-
-static struct clk dummy_apb_pclk = {
-        .name           = "apb_pclk",
-        .id             = -1,
-};
-
-static struct clk *clk_src_mout_href_list[] = {
-        [0] = &s5p_clk_27m,
-        [1] = &clk_fin_hpll,
-};
-
-static struct clksrc_sources clk_src_mout_href = {
-        .sources        = clk_src_mout_href_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_mout_href_list),
-};
-
-static struct clksrc_clk clk_mout_href = {
-        .clk = {
-                .name           = "mout_href",
-        },
-        .sources        = &clk_src_mout_href,
-        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
-};
-
-static struct clk *clk_src_mout_48m_list[] = {
-        [0] = &clk_xusbxti,
-        [1] = &s5p_clk_otgphy,
-};
-
-static struct clksrc_sources clk_src_mout_48m = {
-        .sources        = clk_src_mout_48m_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_mout_48m_list),
-};
-
-static struct clksrc_clk clk_mout_48m = {
-        .clk = {
-                .name           = "mout_48m",
-        },
-        .sources        = &clk_src_mout_48m,
-        .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 },
-};
-
-static struct clksrc_clk clk_mout_mpll = {
-        .clk = {
-                .name           = "mout_mpll",
-        },
-        .sources        = &clk_src_mpll,
-        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
-};
-
-
-static struct clksrc_clk clk_mout_apll = {
-        .clk    = {
-                .name           = "mout_apll",
-        },
-        .sources        = &clk_src_apll,
-        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
-};
-
-static struct clksrc_clk clk_mout_epll = {
-        .clk    = {
-                .name           = "mout_epll",
-        },
-        .sources        = &clk_src_epll,
-        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
-};
-
-static struct clk *clk_src_mout_hpll_list[] = {
-        [0] = &s5p_clk_27m,
-};
-
-static struct clksrc_sources clk_src_mout_hpll = {
-        .sources        = clk_src_mout_hpll_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_mout_hpll_list),
-};
-
-static struct clksrc_clk clk_mout_hpll = {
-        .clk    = {
-                .name           = "mout_hpll",
-        },
-        .sources        = &clk_src_mout_hpll,
-        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
-};
-
-static struct clksrc_clk clk_div_apll = {
-        .clk    = {
-                .name   = "div_apll",
-                .parent = &clk_mout_apll.clk,
-        },
-        .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 },
-};
-
-static struct clksrc_clk clk_div_arm = {
-        .clk    = {
-                .name   = "div_arm",
-                .parent = &clk_div_apll.clk,
-        },
-        .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
-};
-
-static struct clksrc_clk clk_div_d0_bus = {
-        .clk    = {
-                .name   = "div_d0_bus",
-                .parent = &clk_div_arm.clk,
-        },
-        .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
-};
-
-static struct clksrc_clk clk_div_pclkd0 = {
-        .clk    = {
-                .name   = "div_pclkd0",
-                .parent = &clk_div_d0_bus.clk,
-        },
-        .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
-};
-
-static struct clksrc_clk clk_div_secss = {
-        .clk    = {
-                .name   = "div_secss",
-                .parent = &clk_div_d0_bus.clk,
-        },
-        .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 },
-};
-
-static struct clksrc_clk clk_div_apll2 = {
-        .clk    = {
-                .name   = "div_apll2",
-                .parent = &clk_mout_apll.clk,
-        },
-        .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 },
-};
-
-static struct clk *clk_src_mout_am_list[] = {
-        [0] = &clk_mout_mpll.clk,
-        [1] = &clk_div_apll2.clk,
-};
-
-static struct clksrc_sources clk_src_mout_am = {
-        .sources        = clk_src_mout_am_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_mout_am_list),
-};
-
-static struct clksrc_clk clk_mout_am = {
-        .clk    = {
-                .name   = "mout_am",
-        },
-        .sources = &clk_src_mout_am,
-        .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
-};
-
-static struct clksrc_clk clk_div_d1_bus = {
-        .clk    = {
-                .name   = "div_d1_bus",
-                .parent = &clk_mout_am.clk,
-        },
-        .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 },
-};
-
-static struct clksrc_clk clk_div_mpll2 = {
-        .clk    = {
-                .name   = "div_mpll2",
-                .parent = &clk_mout_am.clk,
-        },
-        .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 },
-};
-
-static struct clksrc_clk clk_div_mpll = {
-        .clk    = {
-                .name   = "div_mpll",
-                .parent = &clk_mout_am.clk,
-        },
-        .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 },
-};
-
-static struct clk *clk_src_mout_onenand_list[] = {
-        [0] = &clk_div_d0_bus.clk,
-        [1] = &clk_div_d1_bus.clk,
-};
-
-static struct clksrc_sources clk_src_mout_onenand = {
-        .sources        = clk_src_mout_onenand_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_mout_onenand_list),
-};
-
-static struct clksrc_clk clk_mout_onenand = {
-        .clk    = {
-                .name   = "mout_onenand",
-        },
-        .sources = &clk_src_mout_onenand,
-        .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
-};
-
-static struct clksrc_clk clk_div_onenand = {
-        .clk    = {
-                .name   = "div_onenand",
-                .parent = &clk_mout_onenand.clk,
-        },
-        .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 },
-};
-
-static struct clksrc_clk clk_div_pclkd1 = {
-        .clk    = {
-                .name   = "div_pclkd1",
-                .parent = &clk_div_d1_bus.clk,
-        },
-        .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 },
-};
-
-static struct clksrc_clk clk_div_cam = {
-        .clk    = {
-                .name   = "div_cam",
-                .parent = &clk_div_mpll2.clk,
-        },
-        .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 },
-};
-
-static struct clksrc_clk clk_div_hdmi = {
-        .clk    = {
-                .name   = "div_hdmi",
-                .parent = &clk_mout_hpll.clk,
-        },
-        .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 },
-};
-
-static u32 epll_div[][4] = {
-        { 32750000,     131, 3, 4 },
-        { 32768000,     131, 3, 4 },
-        { 36000000,     72,  3, 3 },
-        { 45000000,     90,  3, 3 },
-        { 45158000,     90,  3, 3 },
-        { 45158400,     90,  3, 3 },
-        { 48000000,     96,  3, 3 },
-        { 49125000,     131, 4, 3 },
-        { 49152000,     131, 4, 3 },
-        { 60000000,     120, 3, 3 },
-        { 67737600,     226, 5, 3 },
-        { 67738000,     226, 5, 3 },
-        { 73800000,     246, 5, 3 },
-        { 73728000,     246, 5, 3 },
-        { 72000000,     144, 3, 3 },
-        { 84000000,     168, 3, 3 },
-        { 96000000,     96,  3, 2 },
-        { 144000000,    144, 3, 2 },
-        { 192000000,    96,  3, 1 }
-};
-
-static int s5pc100_epll_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned int epll_con;
-        unsigned int i;
-
-        if (clk->rate == rate)  /* Return if nothing changed */
-                return 0;
-
-        epll_con = __raw_readl(S5P_EPLL_CON);
-
-        epll_con &= ~(PLL65XX_MDIV_MASK | PLL65XX_PDIV_MASK | PLL65XX_SDIV_MASK);
-
-        for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
-                if (epll_div[i][0] == rate) {
-                        epll_con |= (epll_div[i][1] << PLL65XX_MDIV_SHIFT) |
-                                    (epll_div[i][2] << PLL65XX_PDIV_SHIFT) |
-                                    (epll_div[i][3] << PLL65XX_SDIV_SHIFT);
-                        break;
-                }
-        }
-
-        if (i == ARRAY_SIZE(epll_div)) {
-                printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
-                return -EINVAL;
-        }
-
-        __raw_writel(epll_con, S5P_EPLL_CON);
-
-        printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
-                        clk->rate, rate);
-
-        clk->rate = rate;
-
-        return 0;
-}
-
-static struct clk_ops s5pc100_epll_ops = {
-        .get_rate = s5p_epll_get_rate,
-        .set_rate = s5pc100_epll_set_rate,
-};
-
-static int s5pc100_d0_0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_D00, clk, enable);
-}
-
-static int s5pc100_d0_1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_D01, clk, enable);
-}
-
-static int s5pc100_d0_2_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_D02, clk, enable);
-}
-
-static int s5pc100_d1_0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_D10, clk, enable);
-}
-
-static int s5pc100_d1_1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_D11, clk, enable);
-}
-
-static int s5pc100_d1_2_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_D12, clk, enable);
-}
-
-static int s5pc100_d1_3_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_D13, clk, enable);
-}
-
-static int s5pc100_d1_4_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_D14, clk, enable);
-}
-
-static int s5pc100_d1_5_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_D15, clk, enable);
-}
-
-static int s5pc100_sclk0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_SCLK0, clk, enable);
-}
-
-static int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_SCLK1, clk, enable);
-}
-
-/*
- * The following clocks will be disabled during clock initialization. It is
- * recommended to keep the following clocks disabled until the driver requests
- * for enabling the clock.
- */
-static struct clk init_clocks_off[] = {
-        {
-                .name           = "cssys",
-                .parent         = &clk_div_d0_bus.clk,
-                .enable         = s5pc100_d0_0_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "secss",
-                .parent         = &clk_div_d0_bus.clk,
-                .enable         = s5pc100_d0_0_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
-                .name           = "g2d",
-                .parent         = &clk_div_d0_bus.clk,
-                .enable         = s5pc100_d0_0_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "mdma",
-                .parent         = &clk_div_d0_bus.clk,
-                .enable         = s5pc100_d0_0_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "cfcon",
-                .parent         = &clk_div_d0_bus.clk,
-                .enable         = s5pc100_d0_0_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "nfcon",
-                .parent         = &clk_div_d0_bus.clk,
-                .enable         = s5pc100_d0_1_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "onenandc",
-                .parent         = &clk_div_d0_bus.clk,
-                .enable         = s5pc100_d0_1_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "sdm",
-                .parent         = &clk_div_d0_bus.clk,
-                .enable         = s5pc100_d0_2_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "seckey",
-                .parent         = &clk_div_d0_bus.clk,
-                .enable         = s5pc100_d0_2_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "modemif",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_0_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "otg",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_0_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "usbhost",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_0_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "dma",
-                .devname        = "dma-pl330.1",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_0_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "dma",
-                .devname        = "dma-pl330.0",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_0_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "lcd",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_1_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "rotator",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_1_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "fimc",
-                .devname        = "s5p-fimc.0",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_1_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "fimc",
-                .devname        = "s5p-fimc.1",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_1_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "fimc",
-                .devname        = "s5p-fimc.2",
-                .enable         = s5pc100_d1_1_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "jpeg",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_1_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
-                .name           = "mipi-dsim",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_1_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "mipi-csis",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_1_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "g3d",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_0_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "tv",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_2_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "vp",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_2_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "mixer",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_2_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "hdmi",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_2_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "mfc",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_2_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "apc",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_3_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "iec",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_3_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "systimer",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_3_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "watchdog",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_3_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "rtc",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_3_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.0",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_4_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.1",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_4_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
-                .name           = "spi",
-                .devname        = "s5pc100-spi.0",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_4_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "spi",
-                .devname        = "s5pc100-spi.1",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_4_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "spi",
-                .devname        = "s5pc100-spi.2",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_4_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "irda",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_4_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "ccan",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_4_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "ccan",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_4_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "hsitx",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_4_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "hsirx",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_4_ctrl,
-                .ctrlbit        = (1 << 13),
-        }, {
-                .name           = "ac97",
-                .parent         = &clk_div_pclkd1.clk,
-                .enable         = s5pc100_d1_5_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "pcm",
-                .devname        = "samsung-pcm.0",
-                .parent         = &clk_div_pclkd1.clk,
-                .enable         = s5pc100_d1_5_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "pcm",
-                .devname        = "samsung-pcm.1",
-                .parent         = &clk_div_pclkd1.clk,
-                .enable         = s5pc100_d1_5_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
-                .name           = "spdif",
-                .parent         = &clk_div_pclkd1.clk,
-                .enable         = s5pc100_d1_5_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "adc",
-                .parent         = &clk_div_pclkd1.clk,
-                .enable         = s5pc100_d1_5_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "keypad",
-                .parent         = &clk_div_pclkd1.clk,
-                .enable         = s5pc100_d1_5_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "mmc_48m",
-                .devname        = "s3c-sdhci.0",
-                .parent         = &clk_mout_48m.clk,
-                .enable         = s5pc100_sclk0_ctrl,
-                .ctrlbit        = (1 << 15),
-        }, {
-                .name           = "mmc_48m",
-                .devname        = "s3c-sdhci.1",
-                .parent         = &clk_mout_48m.clk,
-                .enable         = s5pc100_sclk0_ctrl,
-                .ctrlbit        = (1 << 16),
-        }, {
-                .name           = "mmc_48m",
-                .devname        = "s3c-sdhci.2",
-                .parent         = &clk_mout_48m.clk,
-                .enable         = s5pc100_sclk0_ctrl,
-                .ctrlbit        = (1 << 17),
-        },
-};
-
-static struct clk clk_hsmmc2 = {
-        .name           = "hsmmc",
-        .devname        = "s3c-sdhci.2",
-        .parent         = &clk_div_d1_bus.clk,
-        .enable         = s5pc100_d1_0_ctrl,
-        .ctrlbit        = (1 << 7),
-};
-
-static struct clk clk_hsmmc1 = {
-        .name           = "hsmmc",
-        .devname        = "s3c-sdhci.1",
-        .parent         = &clk_div_d1_bus.clk,
-        .enable         = s5pc100_d1_0_ctrl,
-        .ctrlbit        = (1 << 6),
-};
-
-static struct clk clk_hsmmc0 = {
-        .name           = "hsmmc",
-        .devname        = "s3c-sdhci.0",
-        .parent         = &clk_div_d1_bus.clk,
-        .enable         = s5pc100_d1_0_ctrl,
-        .ctrlbit        = (1 << 5),
-};
-
-static struct clk clk_48m_spi0 = {
-        .name           = "spi_48m",
-        .devname        = "s5pc100-spi.0",
-        .parent         = &clk_mout_48m.clk,
-        .enable         = s5pc100_sclk0_ctrl,
-        .ctrlbit        = (1 << 7),
-};
-
-static struct clk clk_48m_spi1 = {
-        .name           = "spi_48m",
-        .devname        = "s5pc100-spi.1",
-        .parent         = &clk_mout_48m.clk,
-        .enable         = s5pc100_sclk0_ctrl,
-        .ctrlbit        = (1 << 8),
-};
-
-static struct clk clk_48m_spi2 = {
-        .name           = "spi_48m",
-        .devname        = "s5pc100-spi.2",
-        .parent         = &clk_mout_48m.clk,
-        .enable         = s5pc100_sclk0_ctrl,
-        .ctrlbit        = (1 << 9),
-};
-
-static struct clk clk_i2s0 = {
-        .name           = "iis",
-        .devname        = "samsung-i2s.0",
-        .parent         = &clk_div_pclkd1.clk,
-        .enable         = s5pc100_d1_5_ctrl,
-        .ctrlbit        = (1 << 0),
-};
-
-static struct clk clk_i2s1 = {
-        .name           = "iis",
-        .devname        = "samsung-i2s.1",
-        .parent         = &clk_div_pclkd1.clk,
-        .enable         = s5pc100_d1_5_ctrl,
-        .ctrlbit        = (1 << 1),
-};
-
-static struct clk clk_i2s2 = {
-        .name           = "iis",
-        .devname        = "samsung-i2s.2",
-        .parent         = &clk_div_pclkd1.clk,
-        .enable         = s5pc100_d1_5_ctrl,
-        .ctrlbit        = (1 << 2),
-};
-
-static struct clk clk_vclk54m = {
-        .name           = "vclk_54m",
-        .rate           = 54000000,
-};
-
-static struct clk clk_i2scdclk0 = {
-        .name           = "i2s_cdclk0",
-};
-
-static struct clk clk_i2scdclk1 = {
-        .name           = "i2s_cdclk1",
-};
-
-static struct clk clk_i2scdclk2 = {
-        .name           = "i2s_cdclk2",
-};
-
-static struct clk clk_pcmcdclk0 = {
-        .name           = "pcm_cdclk0",
-};
-
-static struct clk clk_pcmcdclk1 = {
-        .name           = "pcm_cdclk1",
-};
-
-static struct clk *clk_src_group1_list[] = {
-        [0] = &clk_mout_epll.clk,
-        [1] = &clk_div_mpll2.clk,
-        [2] = &clk_fin_epll,
-        [3] = &clk_mout_hpll.clk,
-};
-
-static struct clksrc_sources clk_src_group1 = {
-        .sources        = clk_src_group1_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_group1_list),
-};
-
-static struct clk *clk_src_group2_list[] = {
-        [0] = &clk_mout_epll.clk,
-        [1] = &clk_div_mpll.clk,
-};
-
-static struct clksrc_sources clk_src_group2 = {
-        .sources        = clk_src_group2_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_group2_list),
-};
-
-static struct clk *clk_src_group3_list[] = {
-        [0] = &clk_mout_epll.clk,
-        [1] = &clk_div_mpll.clk,
-        [2] = &clk_fin_epll,
-        [3] = &clk_i2scdclk0,
-        [4] = &clk_pcmcdclk0,
-        [5] = &clk_mout_hpll.clk,
-};
-
-static struct clksrc_sources clk_src_group3 = {
-        .sources        = clk_src_group3_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_group3_list),
-};
-
-static struct clksrc_clk clk_sclk_audio0 = {
-        .clk    = {
-                .name           = "sclk_audio",
-                .devname        = "samsung-pcm.0",
-                .ctrlbit        = (1 << 8),
-                .enable         = s5pc100_sclk1_ctrl,
-        },
-        .sources = &clk_src_group3,
-        .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 },
-        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
-};
-
-static struct clk *clk_src_group4_list[] = {
-        [0] = &clk_mout_epll.clk,
-        [1] = &clk_div_mpll.clk,
-        [2] = &clk_fin_epll,
-        [3] = &clk_i2scdclk1,
-        [4] = &clk_pcmcdclk1,
-        [5] = &clk_mout_hpll.clk,
-};
-
-static struct clksrc_sources clk_src_group4 = {
-        .sources        = clk_src_group4_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_group4_list),
-};
-
-static struct clksrc_clk clk_sclk_audio1 = {
-        .clk    = {
-                .name           = "sclk_audio",
-                .devname        = "samsung-pcm.1",
-                .ctrlbit        = (1 << 9),
-                .enable         = s5pc100_sclk1_ctrl,
-        },
-        .sources = &clk_src_group4,
-        .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 },
-        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
-};
-
-static struct clk *clk_src_group5_list[] = {
-        [0] = &clk_mout_epll.clk,
-        [1] = &clk_div_mpll.clk,
-        [2] = &clk_fin_epll,
-        [3] = &clk_i2scdclk2,
-        [4] = &clk_mout_hpll.clk,
-};
-
-static struct clksrc_sources clk_src_group5 = {
-        .sources        = clk_src_group5_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_group5_list),
-};
-
-static struct clksrc_clk clk_sclk_audio2 = {
-        .clk    = {
-                .name           = "sclk_audio",
-                .devname        = "samsung-pcm.2",
-                .ctrlbit        = (1 << 10),
-                .enable         = s5pc100_sclk1_ctrl,
-        },
-        .sources = &clk_src_group5,
-        .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 },
-        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
-};
-
-static struct clk *clk_src_group6_list[] = {
-        [0] = &s5p_clk_27m,
-        [1] = &clk_vclk54m,
-        [2] = &clk_div_hdmi.clk,
-};
-
-static struct clksrc_sources clk_src_group6 = {
-        .sources        = clk_src_group6_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_group6_list),
-};
-
-static struct clk *clk_src_group7_list[] = {
-        [0] = &clk_mout_epll.clk,
-        [1] = &clk_div_mpll.clk,
-        [2] = &clk_mout_hpll.clk,
-        [3] = &clk_vclk54m,
-};
-
-static struct clksrc_sources clk_src_group7 = {
-        .sources        = clk_src_group7_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_group7_list),
-};
-
-static struct clk *clk_src_mmc0_list[] = {
-        [0] = &clk_mout_epll.clk,
-        [1] = &clk_div_mpll.clk,
-        [2] = &clk_fin_epll,
-};
-
-static struct clksrc_sources clk_src_mmc0 = {
-        .sources        = clk_src_mmc0_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_mmc0_list),
-};
-
-static struct clk *clk_src_mmc12_list[] = {
-        [0] = &clk_mout_epll.clk,
-        [1] = &clk_div_mpll.clk,
-        [2] = &clk_fin_epll,
-        [3] = &clk_mout_hpll.clk,
-};
-
-static struct clksrc_sources clk_src_mmc12 = {
-        .sources        = clk_src_mmc12_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_mmc12_list),
-};
-
-static struct clk *clk_src_irda_usb_list[] = {
-        [0] = &clk_mout_epll.clk,
-        [1] = &clk_div_mpll.clk,
-        [2] = &clk_fin_epll,
-        [3] = &clk_mout_hpll.clk,
-};
-
-static struct clksrc_sources clk_src_irda_usb = {
-        .sources        = clk_src_irda_usb_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_irda_usb_list),
-};
-
-static struct clk *clk_src_pwi_list[] = {
-        [0] = &clk_fin_epll,
-        [1] = &clk_mout_epll.clk,
-        [2] = &clk_div_mpll.clk,
-};
-
-static struct clksrc_sources clk_src_pwi = {
-        .sources        = clk_src_pwi_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_pwi_list),
-};
-
-static struct clk *clk_sclk_spdif_list[] = {
-        [0] = &clk_sclk_audio0.clk,
-        [1] = &clk_sclk_audio1.clk,
-        [2] = &clk_sclk_audio2.clk,
-};
-
-static struct clksrc_sources clk_src_sclk_spdif = {
-        .sources        = clk_sclk_spdif_list,
-        .nr_sources     = ARRAY_SIZE(clk_sclk_spdif_list),
-};
-
-static struct clksrc_clk clk_sclk_spdif = {
-        .clk    = {
-                .name           = "sclk_spdif",
-                .ctrlbit        = (1 << 11),
-                .enable         = s5pc100_sclk1_ctrl,
-                .ops            = &s5p_sclk_spdif_ops,
-        },
-        .sources = &clk_src_sclk_spdif,
-        .reg_src = { .reg = S5P_CLK_SRC3, .shift = 24, .size = 2 },
-};
-
-static struct clksrc_clk clksrcs[] = {
-        {
-                .clk    = {
-                        .name           = "sclk_mixer",
-                        .ctrlbit        = (1 << 6),
-                        .enable         = s5pc100_sclk0_ctrl,
-
-                },
-                .sources = &clk_src_group6,
-                .reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_lcd",
-                        .ctrlbit        = (1 << 0),
-                        .enable         = s5pc100_sclk1_ctrl,
-
-                },
-                .sources = &clk_src_group7,
-                .reg_src = { .reg = S5P_CLK_SRC2, .shift = 12, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimc",
-                        .devname        = "s5p-fimc.0",
-                        .ctrlbit        = (1 << 1),
-                        .enable         = s5pc100_sclk1_ctrl,
-
-                },
-                .sources = &clk_src_group7,
-                .reg_src = { .reg = S5P_CLK_SRC2, .shift = 16, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimc",
-                        .devname        = "s5p-fimc.1",
-                        .ctrlbit        = (1 << 2),
-                        .enable         = s5pc100_sclk1_ctrl,
-
-                },
-                .sources = &clk_src_group7,
-                .reg_src = { .reg = S5P_CLK_SRC2, .shift = 20, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimc",
-                        .devname        = "s5p-fimc.2",
-                        .ctrlbit        = (1 << 3),
-                        .enable         = s5pc100_sclk1_ctrl,
-
-                },
-                .sources = &clk_src_group7,
-                .reg_src = { .reg = S5P_CLK_SRC2, .shift = 24, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_irda",
-                        .ctrlbit        = (1 << 10),
-                        .enable         = s5pc100_sclk0_ctrl,
-
-                },
-                .sources = &clk_src_irda_usb,
-                .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_irda",
-                        .ctrlbit        = (1 << 10),
-                        .enable         = s5pc100_sclk0_ctrl,
-
-                },
-                .sources = &clk_src_mmc12,
-                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_pwi",
-                        .ctrlbit        = (1 << 1),
-                        .enable         = s5pc100_sclk0_ctrl,
-
-                },
-                .sources = &clk_src_pwi,
-                .reg_src = { .reg = S5P_CLK_SRC3, .shift = 0, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 3 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_uhost",
-                        .ctrlbit        = (1 << 11),
-                        .enable         = s5pc100_sclk0_ctrl,
-
-                },
-                .sources = &clk_src_irda_usb,
-                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV2, .shift = 20, .size = 4 },
-        },
-};
-
-static struct clksrc_clk clk_sclk_uart = {
-        .clk    = {
-                .name           = "uclk1",
-                .ctrlbit        = (1 << 3),
-                .enable         = s5pc100_sclk0_ctrl,
-        },
-        .sources = &clk_src_group2,
-        .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
-        .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_mmc0 = {
-        .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.0",
-                .ctrlbit        = (1 << 12),
-                .enable         = s5pc100_sclk1_ctrl,
-        },
-        .sources = &clk_src_mmc0,
-        .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
-        .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_mmc1 = {
-        .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.1",
-                .ctrlbit        = (1 << 13),
-                .enable         = s5pc100_sclk1_ctrl,
-        },
-        .sources = &clk_src_mmc12,
-        .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
-        .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_mmc2 = {
-        .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.2",
-                .ctrlbit        = (1 << 14),
-                .enable         = s5pc100_sclk1_ctrl,
-        },
-        .sources = &clk_src_mmc12,
-        .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
-        .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_spi0 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "s5pc100-spi.0",
-                .ctrlbit        = (1 << 4),
-                .enable         = s5pc100_sclk0_ctrl,
-        },
-        .sources = &clk_src_group1,
-        .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
-        .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_spi1 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "s5pc100-spi.1",
-                .ctrlbit        = (1 << 5),
-                .enable         = s5pc100_sclk0_ctrl,
-        },
-        .sources = &clk_src_group1,
-        .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
-        .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_spi2 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "s5pc100-spi.2",
-                .ctrlbit        = (1 << 6),
-                .enable         = s5pc100_sclk0_ctrl,
-        },
-        .sources = &clk_src_group1,
-        .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
-        .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
-};
-
-/* Clock initialisation code */
-static struct clksrc_clk *sysclks[] = {
-        &clk_mout_apll,
-        &clk_mout_epll,
-        &clk_mout_mpll,
-        &clk_mout_hpll,
-        &clk_mout_href,
-        &clk_mout_48m,
-        &clk_div_apll,
-        &clk_div_arm,
-        &clk_div_d0_bus,
-        &clk_div_pclkd0,
-        &clk_div_secss,
-        &clk_div_apll2,
-        &clk_mout_am,
-        &clk_div_d1_bus,
-        &clk_div_mpll2,
-        &clk_div_mpll,
-        &clk_mout_onenand,
-        &clk_div_onenand,
-        &clk_div_pclkd1,
-        &clk_div_cam,
-        &clk_div_hdmi,
-        &clk_sclk_audio0,
-        &clk_sclk_audio1,
-        &clk_sclk_audio2,
-        &clk_sclk_spdif,
-};
-
-static struct clk *clk_cdev[] = {
-        &clk_hsmmc0,
-        &clk_hsmmc1,
-        &clk_hsmmc2,
-        &clk_48m_spi0,
-        &clk_48m_spi1,
-        &clk_48m_spi2,
-        &clk_i2s0,
-        &clk_i2s1,
-        &clk_i2s2,
-};
-
-static struct clksrc_clk *clksrc_cdev[] = {
-        &clk_sclk_uart,
-        &clk_sclk_mmc0,
-        &clk_sclk_mmc1,
-        &clk_sclk_mmc2,
-        &clk_sclk_spi0,
-        &clk_sclk_spi1,
-        &clk_sclk_spi2,
-};
-
-void __init_or_cpufreq s5pc100_setup_clocks(void)
-{
-        unsigned long xtal;
-        unsigned long arm;
-        unsigned long hclkd0;
-        unsigned long hclkd1;
-        unsigned long pclkd0;
-        unsigned long pclkd1;
-        unsigned long apll;
-        unsigned long mpll;
-        unsigned long epll;
-        unsigned long hpll;
-        unsigned int ptr;
-
-        /* Set S5PC100 functions for clk_fout_epll */
-        clk_fout_epll.enable = s5p_epll_enable;
-        clk_fout_epll.ops = &s5pc100_epll_ops;
-
-        printk(KERN_DEBUG "%s: registering clocks\n", __func__);
-
-        xtal = clk_get_rate(&clk_xtal);
-
-        printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
-
-        apll = s5p_get_pll65xx(xtal, __raw_readl(S5P_APLL_CON));
-        mpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_MPLL_CON));
-        epll = s5p_get_pll65xx(xtal, __raw_readl(S5P_EPLL_CON));
-        hpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_HPLL_CON));
-
-        printk(KERN_INFO "S5PC100: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz, E=%ld.%ldMHz, H=%ld.%ldMHz\n",
-                        print_mhz(apll), print_mhz(mpll), print_mhz(epll), print_mhz(hpll));
-
-        clk_fout_apll.rate = apll;
-        clk_fout_mpll.rate = mpll;
-        clk_fout_epll.rate = epll;
-        clk_mout_hpll.clk.rate = hpll;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
-                s3c_set_clksrc(&clksrcs[ptr], true);
-
-        arm = clk_get_rate(&clk_div_arm.clk);
-        hclkd0 = clk_get_rate(&clk_div_d0_bus.clk);
-        pclkd0 = clk_get_rate(&clk_div_pclkd0.clk);
-        hclkd1 = clk_get_rate(&clk_div_d1_bus.clk);
-        pclkd1 = clk_get_rate(&clk_div_pclkd1.clk);
-
-        printk(KERN_INFO "S5PC100: HCLKD0=%ld.%ldMHz, HCLKD1=%ld.%ldMHz, PCLKD0=%ld.%ldMHz, PCLKD1=%ld.%ldMHz\n",
-                        print_mhz(hclkd0), print_mhz(hclkd1), print_mhz(pclkd0), print_mhz(pclkd1));
-
-        clk_f.rate = arm;
-        clk_h.rate = hclkd1;
-        clk_p.rate = pclkd1;
-}
-
-/*
- * The following clocks will be enabled during clock initialization.
- */
-static struct clk init_clocks[] = {
-        {
-                .name           = "tzic",
-                .parent         = &clk_div_d0_bus.clk,
-                .enable         = s5pc100_d0_0_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "intc",
-                .parent         = &clk_div_d0_bus.clk,
-                .enable         = s5pc100_d0_0_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "ebi",
-                .parent         = &clk_div_d0_bus.clk,
-                .enable         = s5pc100_d0_1_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
-                .name           = "intmem",
-                .parent         = &clk_div_d0_bus.clk,
-                .enable         = s5pc100_d0_1_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "sromc",
-                .parent         = &clk_div_d0_bus.clk,
-                .enable         = s5pc100_d0_1_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "dmc",
-                .parent         = &clk_div_d0_bus.clk,
-                .enable         = s5pc100_d0_1_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "chipid",
-                .parent         = &clk_div_d0_bus.clk,
-                .enable         = s5pc100_d0_1_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "gpio",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_3_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "uart",
-                .devname        = "s3c6400-uart.0",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_4_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "uart",
-                .devname        = "s3c6400-uart.1",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_4_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "uart",
-                .devname        = "s3c6400-uart.2",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_4_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "uart",
-                .devname        = "s3c6400-uart.3",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_4_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "timers",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_3_ctrl,
-                .ctrlbit        = (1 << 6),
-        },
-};
-
-static struct clk *clks[] __initdata = {
-        &clk_ext,
-        &clk_i2scdclk0,
-        &clk_i2scdclk1,
-        &clk_i2scdclk2,
-        &clk_pcmcdclk0,
-        &clk_pcmcdclk1,
-};
-
-static struct clk_lookup s5pc100_clk_lookup[] = {
-        CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
-        CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uart.clk),
-        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
-        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
-        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
-        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
-        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
-        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
-        CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
-        CLKDEV_INIT("s5pc100-spi.0", "spi_busclk1", &clk_48m_spi0),
-        CLKDEV_INIT("s5pc100-spi.0", "spi_busclk2", &clk_sclk_spi0.clk),
-        CLKDEV_INIT("s5pc100-spi.1", "spi_busclk1", &clk_48m_spi1),
-        CLKDEV_INIT("s5pc100-spi.1", "spi_busclk2", &clk_sclk_spi1.clk),
-        CLKDEV_INIT("s5pc100-spi.2", "spi_busclk1", &clk_48m_spi2),
-        CLKDEV_INIT("s5pc100-spi.2", "spi_busclk2", &clk_sclk_spi2.clk),
-        CLKDEV_INIT("samsung-i2s.0", "i2s_opclk0", &clk_i2s0),
-        CLKDEV_INIT("samsung-i2s.1", "i2s_opclk0", &clk_i2s1),
-        CLKDEV_INIT("samsung-i2s.2", "i2s_opclk0", &clk_i2s2),
-};
-
-void __init s5pc100_register_clocks(void)
-{
-        int ptr;
-
-        s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
-
-        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
-                s3c_register_clksrc(sysclks[ptr], 1);
-
-        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
-        s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
-        for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
-                s3c_register_clksrc(clksrc_cdev[ptr], 1);
-
-        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        clkdev_add_table(s5pc100_clk_lookup, ARRAY_SIZE(s5pc100_clk_lookup));
-
-        s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
-        for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
-                s3c_disable_clocks(clk_cdev[ptr], 1);
-
-        s3c24xx_register_clock(&dummy_apb_pclk);
-}
diff --git a/arch/arm/mach-s5pc100/common.c b/arch/arm/mach-s5pc100/common.c
deleted file mode 100644
index 6a41bf7dacf6..000000000000
--- a/arch/arm/mach-s5pc100/common.c
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Copyright 2009 Samsung Electronics Co.
- *      Byungho Min <bhmin@samsung.com>
- *
- * Common Codes for S5PC100
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/device.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <clocksource/samsung_pwm.h>
-#include <linux/platform_device.h>
-#include <linux/sched.h>
-#include <linux/reboot.h>
-
-#include <asm/irq.h>
-#include <asm/proc-fns.h>
-#include <asm/system_misc.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include <mach/map.h>
-#include <mach/hardware.h>
-#include <mach/regs-clock.h>
-
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/clock.h>
-#include <plat/sdhci.h>
-#include <plat/adc-core.h>
-#include <plat/ata-core.h>
-#include <plat/fb-core.h>
-#include <plat/iic-core.h>
-#include <plat/onenand-core.h>
-#include <plat/pwm-core.h>
-#include <plat/spi-core.h>
-#include <plat/watchdog-reset.h>
-
-#include "common.h"
-
-static const char name_s5pc100[] = "S5PC100";
-
-static struct cpu_table cpu_ids[] __initdata = {
-        {
-                .idcode         = S5PC100_CPU_ID,
-                .idmask         = S5PC100_CPU_MASK,
-                .map_io         = s5pc100_map_io,
-                .init_clocks    = s5pc100_init_clocks,
-                .init_uarts     = s5pc100_init_uarts,
-                .init           = s5pc100_init,
-                .name           = name_s5pc100,
-        },
-};
-
-/* Initial IO mappings */
-
-static struct map_desc s5pc100_iodesc[] __initdata = {
-        {
-                .virtual        = (unsigned long)S5P_VA_CHIPID,
-                .pfn            = __phys_to_pfn(S5PC100_PA_CHIPID),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S3C_VA_SYS,
-                .pfn            = __phys_to_pfn(S5PC100_PA_SYSCON),
-                .length         = SZ_64K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S3C_VA_TIMER,
-                .pfn            = __phys_to_pfn(S5PC100_PA_TIMER),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S3C_VA_WATCHDOG,
-                .pfn            = __phys_to_pfn(S5PC100_PA_WATCHDOG),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5P_VA_SROMC,
-                .pfn            = __phys_to_pfn(S5PC100_PA_SROMC),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5P_VA_SYSTIMER,
-                .pfn            = __phys_to_pfn(S5PC100_PA_SYSTIMER),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5P_VA_GPIO,
-                .pfn            = __phys_to_pfn(S5PC100_PA_GPIO),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)VA_VIC0,
-                .pfn            = __phys_to_pfn(S5PC100_PA_VIC0),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)VA_VIC1,
-                .pfn            = __phys_to_pfn(S5PC100_PA_VIC1),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)VA_VIC2,
-                .pfn            = __phys_to_pfn(S5PC100_PA_VIC2),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S3C_VA_UART,
-                .pfn            = __phys_to_pfn(S3C_PA_UART),
-                .length         = SZ_512K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5PC100_VA_OTHERS,
-                .pfn            = __phys_to_pfn(S5PC100_PA_OTHERS),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }
-};
-
-static struct samsung_pwm_variant s5pc100_pwm_variant = {
-        .bits           = 32,
-        .div_base       = 0,
-        .has_tint_cstat = true,
-        .tclk_mask      = (1 << 5),
-};
-
-void __init samsung_set_timer_source(unsigned int event, unsigned int source)
-{
-        s5pc100_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
-        s5pc100_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
-}
-
-void __init samsung_timer_init(void)
-{
-        unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
-                IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
-                IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
-        };
-
-        samsung_pwm_clocksource_init(S3C_VA_TIMER,
-                                        timer_irqs, &s5pc100_pwm_variant);
-}
-
-/*
- * s5pc100_map_io
- *
- * register the standard CPU IO areas
- */
-
-void __init s5pc100_init_io(struct map_desc *mach_desc, int size)
-{
-        /* initialize the io descriptors we need for initialization */
-        iotable_init(s5pc100_iodesc, ARRAY_SIZE(s5pc100_iodesc));
-        if (mach_desc)
-                iotable_init(mach_desc, size);
-
-        /* detect cpu id and rev. */
-        s5p_init_cpu(S5P_VA_CHIPID);
-
-        s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
-
-        samsung_pwm_set_platdata(&s5pc100_pwm_variant);
-}
-
-void __init s5pc100_map_io(void)
-{
-        /* initialise device information early */
-        s5pc100_default_sdhci0();
-        s5pc100_default_sdhci1();
-        s5pc100_default_sdhci2();
-
-        s3c_adc_setname("s3c64xx-adc");
-
-        /* the i2c devices are directly compatible with s3c2440 */
-        s3c_i2c0_setname("s3c2440-i2c");
-        s3c_i2c1_setname("s3c2440-i2c");
-
-        s3c_onenand_setname("s5pc100-onenand");
-        s3c_fb_setname("s5pc100-fb");
-        s3c_cfcon_setname("s5pc100-pata");
-
-        s3c64xx_spi_setname("s5pc100-spi");
-}
-
-void __init s5pc100_init_clocks(int xtal)
-{
-        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
-
-        s3c24xx_register_baseclocks(xtal);
-        s5p_register_clocks(xtal);
-        s5pc100_register_clocks();
-        s5pc100_setup_clocks();
-        samsung_wdt_reset_init(S3C_VA_WATCHDOG);
-}
-
-void __init s5pc100_init_irq(void)
-{
-        u32 vic[] = {~0, ~0, ~0};
-
-        /* VIC0, VIC1, and VIC2 are fully populated. */
-        s5p_init_irq(vic, ARRAY_SIZE(vic));
-}
-
-static struct bus_type s5pc100_subsys = {
-        .name           = "s5pc100-core",
-        .dev_name       = "s5pc100-core",
-};
-
-static struct device s5pc100_dev = {
-        .bus    = &s5pc100_subsys,
-};
-
-static int __init s5pc100_core_init(void)
-{
-        return subsys_system_register(&s5pc100_subsys, NULL);
-}
-core_initcall(s5pc100_core_init);
-
-int __init s5pc100_init(void)
-{
-        printk(KERN_INFO "S5PC100: Initializing architecture\n");
-        return device_register(&s5pc100_dev);
-}
-
-/* uart registration process */
-
-void __init s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no)
-{
-        s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
-}
-
-void s5pc100_restart(enum reboot_mode mode, const char *cmd)
-{
-        if (mode != REBOOT_SOFT)
-                samsung_wdt_reset();
-
-        soft_restart(0);
-}
diff --git a/arch/arm/mach-s5pc100/common.h b/arch/arm/mach-s5pc100/common.h
deleted file mode 100644
index 08d782d65d7b..000000000000
--- a/arch/arm/mach-s5pc100/common.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Common Header for S5PC100 machines
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ARCH_ARM_MACH_S5PC100_COMMON_H
-#define __ARCH_ARM_MACH_S5PC100_COMMON_H
-
-#include <linux/reboot.h>
-
-void s5pc100_init_io(struct map_desc *mach_desc, int size);
-void s5pc100_init_irq(void);
-
-void s5pc100_register_clocks(void);
-void s5pc100_setup_clocks(void);
-
-void s5pc100_restart(enum reboot_mode mode, const char *cmd);
-
-extern  int s5pc100_init(void);
-extern void s5pc100_map_io(void);
-extern void s5pc100_init_clocks(int xtal);
-extern void s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-#endif /* __ARCH_ARM_MACH_S5PC100_COMMON_H */
diff --git a/arch/arm/mach-s5pc100/dev-audio.c b/arch/arm/mach-s5pc100/dev-audio.c
deleted file mode 100644
index 46f488b09391..000000000000
--- a/arch/arm/mach-s5pc100/dev-audio.c
+++ /dev/null
@@ -1,239 +0,0 @@
-/* linux/arch/arm/mach-s5pc100/dev-audio.c
- *
- * Copyright (c) 2010 Samsung Electronics Co. Ltd
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-
-#include <plat/gpio-cfg.h>
-#include <linux/platform_data/asoc-s3c.h>
-
-#include <mach/map.h>
-#include <mach/dma.h>
-#include <mach/irqs.h>
-
-static int s5pc100_cfg_i2s(struct platform_device *pdev)
-{
-        /* configure GPIO for i2s port */
-        switch (pdev->id) {
-        case 0: /* Dedicated pins */
-                break;
-        case 1:
-                s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(2));
-                break;
-        case 2:
-                s3c_gpio_cfgpin_range(S5PC100_GPG3(0), 5, S3C_GPIO_SFN(4));
-                break;
-        default:
-                printk(KERN_ERR "Invalid Device %d\n", pdev->id);
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
-static struct s3c_audio_pdata i2sv5_pdata = {
-        .cfg_gpio = s5pc100_cfg_i2s,
-        .type = {
-                .i2s = {
-                        .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
-                                         | QUIRK_NEED_RSTCLR,
-                },
-        },
-};
-
-static struct resource s5pc100_iis0_resource[] = {
-        [0] = DEFINE_RES_MEM(S5PC100_PA_I2S0, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_I2S0_TX),
-        [2] = DEFINE_RES_DMA(DMACH_I2S0_RX),
-        [3] = DEFINE_RES_DMA(DMACH_I2S0S_TX),
-};
-
-struct platform_device s5pc100_device_iis0 = {
-        .name = "samsung-i2s",
-        .id = 0,
-        .num_resources    = ARRAY_SIZE(s5pc100_iis0_resource),
-        .resource         = s5pc100_iis0_resource,
-        .dev = {
-                .platform_data = &i2sv5_pdata,
-        },
-};
-
-static struct s3c_audio_pdata i2sv3_pdata = {
-        .cfg_gpio = s5pc100_cfg_i2s,
-};
-
-static struct resource s5pc100_iis1_resource[] = {
-        [0] = DEFINE_RES_MEM(S5PC100_PA_I2S1, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_I2S1_TX),
-        [2] = DEFINE_RES_DMA(DMACH_I2S1_RX),
-};
-
-struct platform_device s5pc100_device_iis1 = {
-        .name             = "samsung-i2s",
-        .id               = 1,
-        .num_resources    = ARRAY_SIZE(s5pc100_iis1_resource),
-        .resource         = s5pc100_iis1_resource,
-        .dev = {
-                .platform_data = &i2sv3_pdata,
-        },
-};
-
-static struct resource s5pc100_iis2_resource[] = {
-        [0] = DEFINE_RES_MEM(S5PC100_PA_I2S2, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_I2S2_TX),
-        [2] = DEFINE_RES_DMA(DMACH_I2S2_RX),
-};
-
-struct platform_device s5pc100_device_iis2 = {
-        .name             = "samsung-i2s",
-        .id               = 2,
-        .num_resources    = ARRAY_SIZE(s5pc100_iis2_resource),
-        .resource         = s5pc100_iis2_resource,
-        .dev = {
-                .platform_data = &i2sv3_pdata,
-        },
-};
-
-/* PCM Controller platform_devices */
-
-static int s5pc100_pcm_cfg_gpio(struct platform_device *pdev)
-{
-        switch (pdev->id) {
-        case 0:
-                s3c_gpio_cfgpin_range(S5PC100_GPG3(0), 5, S3C_GPIO_SFN(5));
-                break;
-
-        case 1:
-                s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(3));
-                break;
-
-        default:
-                printk(KERN_DEBUG "Invalid PCM Controller number!");
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
-static struct s3c_audio_pdata s3c_pcm_pdata = {
-        .cfg_gpio = s5pc100_pcm_cfg_gpio,
-};
-
-static struct resource s5pc100_pcm0_resource[] = {
-        [0] = DEFINE_RES_MEM(S5PC100_PA_PCM0, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_PCM0_TX),
-        [2] = DEFINE_RES_DMA(DMACH_PCM0_RX),
-};
-
-struct platform_device s5pc100_device_pcm0 = {
-        .name             = "samsung-pcm",
-        .id               = 0,
-        .num_resources    = ARRAY_SIZE(s5pc100_pcm0_resource),
-        .resource         = s5pc100_pcm0_resource,
-        .dev = {
-                .platform_data = &s3c_pcm_pdata,
-        },
-};
-
-static struct resource s5pc100_pcm1_resource[] = {
-        [0] = DEFINE_RES_MEM(S5PC100_PA_PCM1, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_PCM1_TX),
-        [2] = DEFINE_RES_DMA(DMACH_PCM1_RX),
-};
-
-struct platform_device s5pc100_device_pcm1 = {
-        .name             = "samsung-pcm",
-        .id               = 1,
-        .num_resources    = ARRAY_SIZE(s5pc100_pcm1_resource),
-        .resource         = s5pc100_pcm1_resource,
-        .dev = {
-                .platform_data = &s3c_pcm_pdata,
-        },
-};
-
-/* AC97 Controller platform devices */
-
-static int s5pc100_ac97_cfg_gpio(struct platform_device *pdev)
-{
-        return s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(4));
-}
-
-static struct resource s5pc100_ac97_resource[] = {
-        [0] = DEFINE_RES_MEM(S5PC100_PA_AC97, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_AC97_PCMOUT),
-        [2] = DEFINE_RES_DMA(DMACH_AC97_PCMIN),
-        [3] = DEFINE_RES_DMA(DMACH_AC97_MICIN),
-        [4] = DEFINE_RES_IRQ(IRQ_AC97),
-};
-
-static struct s3c_audio_pdata s3c_ac97_pdata = {
-        .cfg_gpio = s5pc100_ac97_cfg_gpio,
-};
-
-static u64 s5pc100_ac97_dmamask = DMA_BIT_MASK(32);
-
-struct platform_device s5pc100_device_ac97 = {
-        .name             = "samsung-ac97",
-        .id               = -1,
-        .num_resources    = ARRAY_SIZE(s5pc100_ac97_resource),
-        .resource         = s5pc100_ac97_resource,
-        .dev = {
-                .platform_data = &s3c_ac97_pdata,
-                .dma_mask = &s5pc100_ac97_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-};
-
-/* S/PDIF Controller platform_device */
-static int s5pc100_spdif_cfg_gpd(struct platform_device *pdev)
-{
-        s3c_gpio_cfgpin_range(S5PC100_GPD(5), 2, S3C_GPIO_SFN(3));
-
-        return 0;
-}
-
-static int s5pc100_spdif_cfg_gpg3(struct platform_device *pdev)
-{
-        s3c_gpio_cfgpin_range(S5PC100_GPG3(5), 2, S3C_GPIO_SFN(3));
-
-        return 0;
-}
-
-static struct resource s5pc100_spdif_resource[] = {
-        [0] = DEFINE_RES_MEM(S5PC100_PA_SPDIF, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_SPDIF),
-};
-
-static struct s3c_audio_pdata s5p_spdif_pdata = {
-        .cfg_gpio = s5pc100_spdif_cfg_gpd,
-};
-
-static u64 s5pc100_spdif_dmamask = DMA_BIT_MASK(32);
-
-struct platform_device s5pc100_device_spdif = {
-        .name           = "samsung-spdif",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(s5pc100_spdif_resource),
-        .resource       = s5pc100_spdif_resource,
-        .dev = {
-                .platform_data = &s5p_spdif_pdata,
-                .dma_mask = &s5pc100_spdif_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-};
-
-void __init s5pc100_spdif_setup_gpio(int gpio)
-{
-        if (gpio == S5PC100_SPDIF_GPD)
-                s5p_spdif_pdata.cfg_gpio = s5pc100_spdif_cfg_gpd;
-        else
-                s5p_spdif_pdata.cfg_gpio = s5pc100_spdif_cfg_gpg3;
-}
diff --git a/arch/arm/mach-s5pc100/dma.c b/arch/arm/mach-s5pc100/dma.c
deleted file mode 100644
index b1418409709e..000000000000
--- a/arch/arm/mach-s5pc100/dma.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/* linux/arch/arm/mach-s5pc100/dma.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/dma-mapping.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/pl330.h>
-
-#include <asm/irq.h>
-#include <plat/devs.h>
-#include <plat/irqs.h>
-
-#include <mach/map.h>
-#include <mach/irqs.h>
-#include <mach/dma.h>
-
-static u8 pdma0_peri[] = {
-        DMACH_UART0_RX,
-        DMACH_UART0_TX,
-        DMACH_UART1_RX,
-        DMACH_UART1_TX,
-        DMACH_UART2_RX,
-        DMACH_UART2_TX,
-        DMACH_UART3_RX,
-        DMACH_UART3_TX,
-        DMACH_IRDA,
-        DMACH_I2S0_RX,
-        DMACH_I2S0_TX,
-        DMACH_I2S0S_TX,
-        DMACH_I2S1_RX,
-        DMACH_I2S1_TX,
-        DMACH_I2S2_RX,
-        DMACH_I2S2_TX,
-        DMACH_SPI0_RX,
-        DMACH_SPI0_TX,
-        DMACH_SPI1_RX,
-        DMACH_SPI1_TX,
-        DMACH_SPI2_RX,
-        DMACH_SPI2_TX,
-        DMACH_AC97_MICIN,
-        DMACH_AC97_PCMIN,
-        DMACH_AC97_PCMOUT,
-        DMACH_EXTERNAL,
-        DMACH_PWM,
-        DMACH_SPDIF,
-        DMACH_HSI_RX,
-        DMACH_HSI_TX,
-};
-
-static struct dma_pl330_platdata s5pc100_pdma0_pdata = {
-        .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
-        .peri_id = pdma0_peri,
-};
-
-static AMBA_AHB_DEVICE(s5pc100_pdma0,  "dma-pl330.0", 0x00041330,
-        S5PC100_PA_PDMA0, {IRQ_PDMA0}, &s5pc100_pdma0_pdata);
-
-static u8 pdma1_peri[] = {
-        DMACH_UART0_RX,
-        DMACH_UART0_TX,
-        DMACH_UART1_RX,
-        DMACH_UART1_TX,
-        DMACH_UART2_RX,
-        DMACH_UART2_TX,
-        DMACH_UART3_RX,
-        DMACH_UART3_TX,
-        DMACH_IRDA,
-        DMACH_I2S0_RX,
-        DMACH_I2S0_TX,
-        DMACH_I2S0S_TX,
-        DMACH_I2S1_RX,
-        DMACH_I2S1_TX,
-        DMACH_I2S2_RX,
-        DMACH_I2S2_TX,
-        DMACH_SPI0_RX,
-        DMACH_SPI0_TX,
-        DMACH_SPI1_RX,
-        DMACH_SPI1_TX,
-        DMACH_SPI2_RX,
-        DMACH_SPI2_TX,
-        DMACH_PCM0_RX,
-        DMACH_PCM0_TX,
-        DMACH_PCM1_RX,
-        DMACH_PCM1_TX,
-        DMACH_MSM_REQ0,
-        DMACH_MSM_REQ1,
-        DMACH_MSM_REQ2,
-        DMACH_MSM_REQ3,
-};
-
-static struct dma_pl330_platdata s5pc100_pdma1_pdata = {
-        .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
-        .peri_id = pdma1_peri,
-};
-
-static AMBA_AHB_DEVICE(s5pc100_pdma1, "dma-pl330.1", 0x00041330,
-        S5PC100_PA_PDMA1, {IRQ_PDMA1}, &s5pc100_pdma1_pdata);
-
-static int __init s5pc100_dma_init(void)
-{
-        dma_cap_set(DMA_SLAVE, s5pc100_pdma0_pdata.cap_mask);
-        dma_cap_set(DMA_CYCLIC, s5pc100_pdma0_pdata.cap_mask);
-        amba_device_register(&s5pc100_pdma0_device, &iomem_resource);
-
-        dma_cap_set(DMA_SLAVE, s5pc100_pdma1_pdata.cap_mask);
-        dma_cap_set(DMA_CYCLIC, s5pc100_pdma1_pdata.cap_mask);
-        amba_device_register(&s5pc100_pdma1_device, &iomem_resource);
-
-        return 0;
-}
-arch_initcall(s5pc100_dma_init);
diff --git a/arch/arm/mach-s5pc100/include/mach/debug-macro.S b/arch/arm/mach-s5pc100/include/mach/debug-macro.S
deleted file mode 100644
index 22c23859e45e..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/debug-macro.S
+++ /dev/null
@@ -1,39 +0,0 @@
-/* arch/arm/mach-s5pc100/include/mach/debug-macro.S
- *
- * Copyright 2009 Samsung Electronics Co.
- *      Byungho Min <bhmin@samsung.com>
- *
- *
- * Based on mach-s3c6400/include/mach/debug-macro.S
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* pull in the relevant register and map files. */
-
-#include <linux/serial_s3c.h>
-#include <mach/map.h>
-
-        /* note, for the boot process to work we have to keep the UART
-         * virtual address aligned to an 1MiB boundary for the L1
-         * mapping the head code makes. We keep the UART virtual address
-         * aligned and add in the offset when we load the value here.
-         */
-
-        .macro addruart, rp, rv, tmp
-                ldr     \rp, = S3C_PA_UART
-                ldr     \rv, = S3C_VA_UART
-#if CONFIG_DEBUG_S3C_UART != 0
-                add     \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
-                add     \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
-#endif
-        .endm
-
-/* include the reset of the code which will do the work, we're only
- * compiling for a single cpu processor type so the default of s3c2440
- * will be fine with us.
- */
-
-#include <debug/samsung.S>
diff --git a/arch/arm/mach-s5pc100/include/mach/dma.h b/arch/arm/mach-s5pc100/include/mach/dma.h
deleted file mode 100644
index 201842a3769e..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/dma.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __MACH_DMA_H
-#define __MACH_DMA_H
-
-/* This platform uses the common DMA API driver for PL330 */
-#include <plat/dma-pl330.h>
-
-#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/entry-macro.S b/arch/arm/mach-s5pc100/include/mach/entry-macro.S
deleted file mode 100644
index bad0700457db..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/entry-macro.S
+++ /dev/null
@@ -1,19 +0,0 @@
-/* arch/arm/mach-s5pc100/include/mach/entry-macro.S
- *
- * Copyright 2009 Samsung Electronics Co.
- *      Byungho Min <bhmin@samsung.com>
- *
- * Based on mach-s3c6400/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for the Samsung S5PC1XX series
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
-*/
-
-        .macro  get_irqnr_preamble, base, tmp
-        .endm
-
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        .endm
diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h
deleted file mode 100644
index 5e1a924b595f..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/gpio.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/* arch/arm/mach-s5pc100/include/mach/gpio.h
- *
- * Copyright 2009 Samsung Electronics Co.
- *      Byungho Min <bhmin@samsung.com>
- *
- * S5PC100 - GPIO lib support
- *
- * Base on mach-s3c6400/include/mach/gpio.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H __FILE__
-
-/* GPIO bank sizes */
-#define S5PC100_GPIO_A0_NR      (8)
-#define S5PC100_GPIO_A1_NR      (5)
-#define S5PC100_GPIO_B_NR       (8)
-#define S5PC100_GPIO_C_NR       (5)
-#define S5PC100_GPIO_D_NR       (7)
-#define S5PC100_GPIO_E0_NR      (8)
-#define S5PC100_GPIO_E1_NR      (6)
-#define S5PC100_GPIO_F0_NR      (8)
-#define S5PC100_GPIO_F1_NR      (8)
-#define S5PC100_GPIO_F2_NR      (8)
-#define S5PC100_GPIO_F3_NR      (4)
-#define S5PC100_GPIO_G0_NR      (8)
-#define S5PC100_GPIO_G1_NR      (3)
-#define S5PC100_GPIO_G2_NR      (7)
-#define S5PC100_GPIO_G3_NR      (7)
-#define S5PC100_GPIO_H0_NR      (8)
-#define S5PC100_GPIO_H1_NR      (8)
-#define S5PC100_GPIO_H2_NR      (8)
-#define S5PC100_GPIO_H3_NR      (8)
-#define S5PC100_GPIO_I_NR       (8)
-#define S5PC100_GPIO_J0_NR      (8)
-#define S5PC100_GPIO_J1_NR      (5)
-#define S5PC100_GPIO_J2_NR      (8)
-#define S5PC100_GPIO_J3_NR      (8)
-#define S5PC100_GPIO_J4_NR      (4)
-#define S5PC100_GPIO_K0_NR      (8)
-#define S5PC100_GPIO_K1_NR      (6)
-#define S5PC100_GPIO_K2_NR      (8)
-#define S5PC100_GPIO_K3_NR      (8)
-#define S5PC100_GPIO_L0_NR      (8)
-#define S5PC100_GPIO_L1_NR      (8)
-#define S5PC100_GPIO_L2_NR      (8)
-#define S5PC100_GPIO_L3_NR      (8)
-#define S5PC100_GPIO_L4_NR      (8)
-
-/* GPIO bank numbes */
-
-/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
- * space for debugging purposes so that any accidental
- * change from one gpio bank to another can be caught.
-*/
-
-#define S5PC100_GPIO_NEXT(__gpio) \
-        ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
-
-enum s5p_gpio_number {
-        S5PC100_GPIO_A0_START   = 0,
-        S5PC100_GPIO_A1_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_A0),
-        S5PC100_GPIO_B_START    = S5PC100_GPIO_NEXT(S5PC100_GPIO_A1),
-        S5PC100_GPIO_C_START    = S5PC100_GPIO_NEXT(S5PC100_GPIO_B),
-        S5PC100_GPIO_D_START    = S5PC100_GPIO_NEXT(S5PC100_GPIO_C),
-        S5PC100_GPIO_E0_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_D),
-        S5PC100_GPIO_E1_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_E0),
-        S5PC100_GPIO_F0_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_E1),
-        S5PC100_GPIO_F1_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_F0),
-        S5PC100_GPIO_F2_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_F1),
-        S5PC100_GPIO_F3_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_F2),
-        S5PC100_GPIO_G0_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_F3),
-        S5PC100_GPIO_G1_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_G0),
-        S5PC100_GPIO_G2_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_G1),
-        S5PC100_GPIO_G3_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_G2),
-        S5PC100_GPIO_H0_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_G3),
-        S5PC100_GPIO_H1_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_H0),
-        S5PC100_GPIO_H2_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_H1),
-        S5PC100_GPIO_H3_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_H2),
-        S5PC100_GPIO_I_START    = S5PC100_GPIO_NEXT(S5PC100_GPIO_H3),
-        S5PC100_GPIO_J0_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_I),
-        S5PC100_GPIO_J1_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_J0),
-        S5PC100_GPIO_J2_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_J1),
-        S5PC100_GPIO_J3_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_J2),
-        S5PC100_GPIO_J4_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_J3),
-        S5PC100_GPIO_K0_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_J4),
-        S5PC100_GPIO_K1_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_K0),
-        S5PC100_GPIO_K2_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_K1),
-        S5PC100_GPIO_K3_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_K2),
-        S5PC100_GPIO_L0_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_K3),
-        S5PC100_GPIO_L1_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_L0),
-        S5PC100_GPIO_L2_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_L1),
-        S5PC100_GPIO_L3_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_L2),
-        S5PC100_GPIO_L4_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_L3),
-        S5PC100_GPIO_END        = S5PC100_GPIO_NEXT(S5PC100_GPIO_L4),
-};
-
-/* S5PC100 GPIO number definitions. */
-#define S5PC100_GPA0(_nr)       (S5PC100_GPIO_A0_START + (_nr))
-#define S5PC100_GPA1(_nr)       (S5PC100_GPIO_A1_START + (_nr))
-#define S5PC100_GPB(_nr)        (S5PC100_GPIO_B_START + (_nr))
-#define S5PC100_GPC(_nr)        (S5PC100_GPIO_C_START + (_nr))
-#define S5PC100_GPD(_nr)        (S5PC100_GPIO_D_START + (_nr))
-#define S5PC100_GPE0(_nr)       (S5PC100_GPIO_E0_START + (_nr))
-#define S5PC100_GPE1(_nr)       (S5PC100_GPIO_E1_START + (_nr))
-#define S5PC100_GPF0(_nr)       (S5PC100_GPIO_F0_START + (_nr))
-#define S5PC100_GPF1(_nr)       (S5PC100_GPIO_F1_START + (_nr))
-#define S5PC100_GPF2(_nr)       (S5PC100_GPIO_F2_START + (_nr))
-#define S5PC100_GPF3(_nr)       (S5PC100_GPIO_F3_START + (_nr))
-#define S5PC100_GPG0(_nr)       (S5PC100_GPIO_G0_START + (_nr))
-#define S5PC100_GPG1(_nr)       (S5PC100_GPIO_G1_START + (_nr))
-#define S5PC100_GPG2(_nr)       (S5PC100_GPIO_G2_START + (_nr))
-#define S5PC100_GPG3(_nr)       (S5PC100_GPIO_G3_START + (_nr))
-#define S5PC100_GPH0(_nr)       (S5PC100_GPIO_H0_START + (_nr))
-#define S5PC100_GPH1(_nr)       (S5PC100_GPIO_H1_START + (_nr))
-#define S5PC100_GPH2(_nr)       (S5PC100_GPIO_H2_START + (_nr))
-#define S5PC100_GPH3(_nr)       (S5PC100_GPIO_H3_START + (_nr))
-#define S5PC100_GPI(_nr)        (S5PC100_GPIO_I_START + (_nr))
-#define S5PC100_GPJ0(_nr)       (S5PC100_GPIO_J0_START + (_nr))
-#define S5PC100_GPJ1(_nr)       (S5PC100_GPIO_J1_START + (_nr))
-#define S5PC100_GPJ2(_nr)       (S5PC100_GPIO_J2_START + (_nr))
-#define S5PC100_GPJ3(_nr)       (S5PC100_GPIO_J3_START + (_nr))
-#define S5PC100_GPJ4(_nr)       (S5PC100_GPIO_J4_START + (_nr))
-#define S5PC100_GPK0(_nr)       (S5PC100_GPIO_K0_START + (_nr))
-#define S5PC100_GPK1(_nr)       (S5PC100_GPIO_K1_START + (_nr))
-#define S5PC100_GPK2(_nr)       (S5PC100_GPIO_K2_START + (_nr))
-#define S5PC100_GPK3(_nr)       (S5PC100_GPIO_K3_START + (_nr))
-#define S5PC100_GPL0(_nr)       (S5PC100_GPIO_L0_START + (_nr))
-#define S5PC100_GPL1(_nr)       (S5PC100_GPIO_L1_START + (_nr))
-#define S5PC100_GPL2(_nr)       (S5PC100_GPIO_L2_START + (_nr))
-#define S5PC100_GPL3(_nr)       (S5PC100_GPIO_L3_START + (_nr))
-#define S5PC100_GPL4(_nr)       (S5PC100_GPIO_L4_START + (_nr))
-
-/* It used the end of the S5PC100 gpios */
-#define S3C_GPIO_END            S5PC100_GPIO_END
-
-/* define the number of gpios we need to the one after the MP04() range */
-#define ARCH_NR_GPIOS           (S5PC100_GPIO_END + 1)
-
-#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/hardware.h b/arch/arm/mach-s5pc100/include/mach/hardware.h
deleted file mode 100644
index 6b38618c2fd9..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/hardware.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* linux/arch/arm/mach-s5pc100/include/mach/hardware.h
- *
- * Copyright 2009 Samsung Electronics Co.
- *      Byungho Min <bhmin@samsung.com>
- *
- * S5PC100 - Hardware support
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H __FILE__
-
-/* currently nothing here, placeholder */
-
-#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h
deleted file mode 100644
index d2eb4757381f..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/irqs.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/* linux/arch/arm/mach-s5pc100/include/mach/irqs.h
- *
- * Copyright 2009 Samsung Electronics Co.
- *      Byungho Min <bhmin@samsung.com>
- *
- * S5PC100 - IRQ definitions
- */
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H __FILE__
-
-#include <plat/irqs.h>
-
-/* VIC0: system, DMA, timer */
-#define IRQ_EINT16_31           S5P_IRQ_VIC0(16)
-#define IRQ_BATF                S5P_IRQ_VIC0(17)
-#define IRQ_MDMA                S5P_IRQ_VIC0(18)
-#define IRQ_PDMA0               S5P_IRQ_VIC0(19)
-#define IRQ_PDMA1               S5P_IRQ_VIC0(20)
-#define IRQ_TIMER0_VIC          S5P_IRQ_VIC0(21)
-#define IRQ_TIMER1_VIC          S5P_IRQ_VIC0(22)
-#define IRQ_TIMER2_VIC          S5P_IRQ_VIC0(23)
-#define IRQ_TIMER3_VIC          S5P_IRQ_VIC0(24)
-#define IRQ_TIMER4_VIC          S5P_IRQ_VIC0(25)
-#define IRQ_SYSTIMER            S5P_IRQ_VIC0(26)
-#define IRQ_WDT                 S5P_IRQ_VIC0(27)
-#define IRQ_RTC_ALARM           S5P_IRQ_VIC0(28)
-#define IRQ_RTC_TIC             S5P_IRQ_VIC0(29)
-#define IRQ_GPIOINT             S5P_IRQ_VIC0(30)
-
-/* VIC1: ARM, power, memory, connectivity */
-#define IRQ_PMU                 S5P_IRQ_VIC1(0)
-#define IRQ_CORTEX1             S5P_IRQ_VIC1(1)
-#define IRQ_CORTEX2             S5P_IRQ_VIC1(2)
-#define IRQ_CORTEX3             S5P_IRQ_VIC1(3)
-#define IRQ_CORTEX4             S5P_IRQ_VIC1(4)
-#define IRQ_IEMAPC              S5P_IRQ_VIC1(5)
-#define IRQ_IEMIEC              S5P_IRQ_VIC1(6)
-#define IRQ_ONENAND             S5P_IRQ_VIC1(7)
-#define IRQ_NFC                 S5P_IRQ_VIC1(8)
-#define IRQ_CFCON               S5P_IRQ_VIC1(9)
-#define IRQ_UART0               S5P_IRQ_VIC1(10)
-#define IRQ_UART1               S5P_IRQ_VIC1(11)
-#define IRQ_UART2               S5P_IRQ_VIC1(12)
-#define IRQ_UART3               S5P_IRQ_VIC1(13)
-#define IRQ_IIC                 S5P_IRQ_VIC1(14)
-#define IRQ_SPI0                S5P_IRQ_VIC1(15)
-#define IRQ_SPI1                S5P_IRQ_VIC1(16)
-#define IRQ_SPI2                S5P_IRQ_VIC1(17)
-#define IRQ_IRDA                S5P_IRQ_VIC1(18)
-#define IRQ_IIC2                S5P_IRQ_VIC1(19)
-#define IRQ_IIC3                S5P_IRQ_VIC1(20)
-#define IRQ_HSIRX               S5P_IRQ_VIC1(21)
-#define IRQ_HSITX               S5P_IRQ_VIC1(22)
-#define IRQ_UHOST               S5P_IRQ_VIC1(23)
-#define IRQ_OTG                 S5P_IRQ_VIC1(24)
-#define IRQ_MSM                 S5P_IRQ_VIC1(25)
-#define IRQ_HSMMC0              S5P_IRQ_VIC1(26)
-#define IRQ_HSMMC1              S5P_IRQ_VIC1(27)
-#define IRQ_HSMMC2              S5P_IRQ_VIC1(28)
-#define IRQ_MIPICSI             S5P_IRQ_VIC1(29)
-#define IRQ_MIPIDSI             S5P_IRQ_VIC1(30)
-
-/* VIC2: multimedia, audio, security */
-#define IRQ_LCD0                S5P_IRQ_VIC2(0)
-#define IRQ_LCD1                S5P_IRQ_VIC2(1)
-#define IRQ_LCD2                S5P_IRQ_VIC2(2)
-#define IRQ_LCD3                S5P_IRQ_VIC2(3)
-#define IRQ_ROTATOR             S5P_IRQ_VIC2(4)
-#define IRQ_FIMC0               S5P_IRQ_VIC2(5)
-#define IRQ_FIMC1               S5P_IRQ_VIC2(6)
-#define IRQ_FIMC2               S5P_IRQ_VIC2(7)
-#define IRQ_JPEG                S5P_IRQ_VIC2(8)
-#define IRQ_2D                  S5P_IRQ_VIC2(9)
-#define IRQ_3D                  S5P_IRQ_VIC2(10)
-#define IRQ_MIXER               S5P_IRQ_VIC2(11)
-#define IRQ_HDMI                S5P_IRQ_VIC2(12)
-#define IRQ_IIC1                S5P_IRQ_VIC2(13)
-#define IRQ_MFC                 S5P_IRQ_VIC2(14)
-#define IRQ_TVENC               S5P_IRQ_VIC2(15)
-#define IRQ_I2S0                S5P_IRQ_VIC2(16)
-#define IRQ_I2S1                S5P_IRQ_VIC2(17)
-#define IRQ_I2S2                S5P_IRQ_VIC2(18)
-#define IRQ_AC97                S5P_IRQ_VIC2(19)
-#define IRQ_PCM0                S5P_IRQ_VIC2(20)
-#define IRQ_PCM1                S5P_IRQ_VIC2(21)
-#define IRQ_SPDIF               S5P_IRQ_VIC2(22)
-#define IRQ_ADC                 S5P_IRQ_VIC2(23)
-#define IRQ_PENDN               S5P_IRQ_VIC2(24)
-#define IRQ_TC                  IRQ_PENDN
-#define IRQ_KEYPAD              S5P_IRQ_VIC2(25)
-#define IRQ_CG                  S5P_IRQ_VIC2(26)
-#define IRQ_SEC                 S5P_IRQ_VIC2(27)
-#define IRQ_SECRX               S5P_IRQ_VIC2(28)
-#define IRQ_SECTX               S5P_IRQ_VIC2(29)
-#define IRQ_SDMIRQ              S5P_IRQ_VIC2(30)
-#define IRQ_SDMFIQ              S5P_IRQ_VIC2(31)
-#define IRQ_VIC_END             S5P_IRQ_VIC2(31)
-
-#define S5P_EINT_BASE1          (S5P_IRQ_VIC0(0))
-#define S5P_EINT_BASE2          (IRQ_VIC_END + 1)
-
-/* GPIO interrupt */
-#define S5P_GPIOINT_BASE        (IRQ_EINT(31) + 1)
-#define S5P_GPIOINT_GROUP_MAXNR 21
-
-/* Set the default NR_IRQS */
-#define NR_IRQS                 (IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
-
-/* Compatibility */
-#define IRQ_LCD_FIFO            IRQ_LCD0
-#define IRQ_LCD_VSYNC           IRQ_LCD1
-#define IRQ_LCD_SYSTEM          IRQ_LCD2
-
-#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
deleted file mode 100644
index 2550b6112b82..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/* linux/arch/arm/mach-s5pc100/include/mach/map.h
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * Copyright 2009 Samsung Electronics Co.
- *      Byungho Min <bhmin@samsung.com>
- *
- * S5PC100 - Memory map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_MAP_H
-#define __ASM_ARCH_MAP_H __FILE__
-
-#include <plat/map-base.h>
-#include <plat/map-s5p.h>
-
-#define S5PC100_PA_SDRAM                0x20000000
-
-#define S5PC100_PA_ONENAND              0xE7100000
-#define S5PC100_PA_ONENAND_BUF          0xB0000000
-
-#define S5PC100_PA_CHIPID               0xE0000000
-
-#define S5PC100_PA_SYSCON               0xE0100000
-
-#define S5PC100_PA_OTHERS               0xE0200000
-
-#define S5PC100_PA_GPIO                 0xE0300000
-
-#define S5PC100_PA_VIC0                 0xE4000000
-#define S5PC100_PA_VIC1                 0xE4100000
-#define S5PC100_PA_VIC2                 0xE4200000
-
-#define S5PC100_PA_SROMC                0xE7000000
-
-#define S5PC100_PA_CFCON                0xE7800000
-
-#define S5PC100_PA_MDMA                 0xE8100000
-#define S5PC100_PA_PDMA0                0xE9000000
-#define S5PC100_PA_PDMA1                0xE9200000
-
-#define S5PC100_PA_TIMER                0xEA000000
-#define S5PC100_PA_SYSTIMER             0xEA100000
-#define S5PC100_PA_WATCHDOG             0xEA200000
-#define S5PC100_PA_RTC                  0xEA300000
-
-#define S5PC100_PA_UART                 0xEC000000
-
-#define S5PC100_PA_IIC0                 0xEC100000
-#define S5PC100_PA_IIC1                 0xEC200000
-
-#define S5PC100_PA_SPI0                 0xEC300000
-#define S5PC100_PA_SPI1                 0xEC400000
-#define S5PC100_PA_SPI2                 0xEC500000
-
-#define S5PC100_PA_USB_HSOTG            0xED200000
-#define S5PC100_PA_USB_HSPHY            0xED300000
-
-#define S5PC100_PA_HSMMC(x)             (0xED800000 + ((x) * 0x100000))
-
-#define S5PC100_PA_FB                   0xEE000000
-
-#define S5PC100_PA_FIMC0                0xEE200000
-#define S5PC100_PA_FIMC1                0xEE300000
-#define S5PC100_PA_FIMC2                0xEE400000
-
-#define S5PC100_PA_I2S0                 0xF2000000
-#define S5PC100_PA_I2S1                 0xF2100000
-#define S5PC100_PA_I2S2                 0xF2200000
-
-#define S5PC100_PA_AC97                 0xF2300000
-
-#define S5PC100_PA_PCM0                 0xF2400000
-#define S5PC100_PA_PCM1                 0xF2500000
-
-#define S5PC100_PA_SPDIF                0xF2600000
-
-#define S5PC100_PA_TSADC                0xF3000000
-
-#define S5PC100_PA_KEYPAD               0xF3100000
-
-/* Compatibiltiy Defines */
-
-#define S3C_PA_FB                       S5PC100_PA_FB
-#define S3C_PA_HSMMC0                   S5PC100_PA_HSMMC(0)
-#define S3C_PA_HSMMC1                   S5PC100_PA_HSMMC(1)
-#define S3C_PA_HSMMC2                   S5PC100_PA_HSMMC(2)
-#define S3C_PA_IIC                      S5PC100_PA_IIC0
-#define S3C_PA_IIC1                     S5PC100_PA_IIC1
-#define S3C_PA_KEYPAD                   S5PC100_PA_KEYPAD
-#define S3C_PA_ONENAND                  S5PC100_PA_ONENAND
-#define S3C_PA_ONENAND_BUF              S5PC100_PA_ONENAND_BUF
-#define S3C_PA_RTC                      S5PC100_PA_RTC
-#define S3C_PA_TSADC                    S5PC100_PA_TSADC
-#define S3C_PA_USB_HSOTG                S5PC100_PA_USB_HSOTG
-#define S3C_PA_USB_HSPHY                S5PC100_PA_USB_HSPHY
-#define S3C_PA_WDT                      S5PC100_PA_WATCHDOG
-#define S3C_PA_SPI0                     S5PC100_PA_SPI0
-#define S3C_PA_SPI1                     S5PC100_PA_SPI1
-#define S3C_PA_SPI2                     S5PC100_PA_SPI2
-
-#define S5P_PA_CHIPID                   S5PC100_PA_CHIPID
-#define S5P_PA_FIMC0                    S5PC100_PA_FIMC0
-#define S5P_PA_FIMC1                    S5PC100_PA_FIMC1
-#define S5P_PA_FIMC2                    S5PC100_PA_FIMC2
-#define S5P_PA_SDRAM                    S5PC100_PA_SDRAM
-#define S5P_PA_SROMC                    S5PC100_PA_SROMC
-#define S5P_PA_SYSCON                   S5PC100_PA_SYSCON
-#define S5P_PA_TIMER                    S5PC100_PA_TIMER
-
-#define SAMSUNG_PA_ADC                  S5PC100_PA_TSADC
-#define SAMSUNG_PA_CFCON                S5PC100_PA_CFCON
-#define SAMSUNG_PA_KEYPAD               S5PC100_PA_KEYPAD
-#define SAMSUNG_PA_TIMER                S5PC100_PA_TIMER
-
-#define S5PC100_VA_OTHERS               (S3C_VA_SYS + 0x10000)
-
-#define S3C_SZ_ONENAND_BUF              (SZ_256M - SZ_32M)
-
-/* UART */
-
-#define S3C_PA_UART                     S5PC100_PA_UART
-
-#define S5P_PA_UART(x)                  (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
-#define S5P_PA_UART0                    S5P_PA_UART(0)
-#define S5P_PA_UART1                    S5P_PA_UART(1)
-#define S5P_PA_UART2                    S5P_PA_UART(2)
-#define S5P_PA_UART3                    S5P_PA_UART(3)
-
-#define S5P_SZ_UART                     SZ_256
-
-#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-clock.h b/arch/arm/mach-s5pc100/include/mach/regs-clock.h
deleted file mode 100644
index bc92da2e0ba2..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/regs-clock.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* linux/arch/arm/mach-s5pc100/include/mach/regs-clock.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5PC100 - Clock register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_CLOCK_H
-#define __ASM_ARCH_REGS_CLOCK_H __FILE__
-
-#include <mach/map.h>
-
-#define S5P_CLKREG(x)           (S3C_VA_SYS + (x))
-
-#define S5PC100_REG_OTHERS(x)   (S5PC100_VA_OTHERS + (x))
-
-#define S5P_APLL_LOCK           S5P_CLKREG(0x00)
-#define S5P_MPLL_LOCK           S5P_CLKREG(0x04)
-#define S5P_EPLL_LOCK           S5P_CLKREG(0x08)
-#define S5P_HPLL_LOCK           S5P_CLKREG(0x0C)
-
-#define S5P_APLL_CON            S5P_CLKREG(0x100)
-#define S5P_MPLL_CON            S5P_CLKREG(0x104)
-#define S5P_EPLL_CON            S5P_CLKREG(0x108)
-#define S5P_HPLL_CON            S5P_CLKREG(0x10C)
-
-#define S5P_CLK_SRC0            S5P_CLKREG(0x200)
-#define S5P_CLK_SRC1            S5P_CLKREG(0x204)
-#define S5P_CLK_SRC2            S5P_CLKREG(0x208)
-#define S5P_CLK_SRC3            S5P_CLKREG(0x20C)
-
-#define S5P_CLK_DIV0            S5P_CLKREG(0x300)
-#define S5P_CLK_DIV1            S5P_CLKREG(0x304)
-#define S5P_CLK_DIV2            S5P_CLKREG(0x308)
-#define S5P_CLK_DIV3            S5P_CLKREG(0x30C)
-#define S5P_CLK_DIV4            S5P_CLKREG(0x310)
-
-#define S5P_CLK_OUT             S5P_CLKREG(0x400)
-
-#define S5P_CLKGATE_D00         S5P_CLKREG(0x500)
-#define S5P_CLKGATE_D01         S5P_CLKREG(0x504)
-#define S5P_CLKGATE_D02         S5P_CLKREG(0x508)
-
-#define S5P_CLKGATE_D10         S5P_CLKREG(0x520)
-#define S5P_CLKGATE_D11         S5P_CLKREG(0x524)
-#define S5P_CLKGATE_D12         S5P_CLKREG(0x528)
-#define S5P_CLKGATE_D13         S5P_CLKREG(0x52C)
-#define S5P_CLKGATE_D14         S5P_CLKREG(0x530)
-#define S5P_CLKGATE_D15         S5P_CLKREG(0x534)
-
-#define S5P_CLKGATE_D20         S5P_CLKREG(0x540)
-
-#define S5P_CLKGATE_SCLK0       S5P_CLKREG(0x560)
-#define S5P_CLKGATE_SCLK1       S5P_CLKREG(0x564)
-
-/* CLKDIV0 */
-#define S5P_CLKDIV0_D0_MASK             (0x7<<8)
-#define S5P_CLKDIV0_D0_SHIFT            (8)
-#define S5P_CLKDIV0_PCLKD0_MASK         (0x7<<12)
-#define S5P_CLKDIV0_PCLKD0_SHIFT        (12)
-
-/* CLKDIV1 */
-#define S5P_CLKDIV1_D1_MASK             (0x7<<12)
-#define S5P_CLKDIV1_D1_SHIFT            (12)
-#define S5P_CLKDIV1_PCLKD1_MASK         (0x7<<16)
-#define S5P_CLKDIV1_PCLKD1_SHIFT        (16)
-
-#define S5PC100_SWRESET         S5PC100_REG_OTHERS(0x000)
-#define S5PC100_MEM_SYS_CFG     S5PC100_REG_OTHERS(0x200)
-
-#define S5PC100_SWRESET_RESETVAL        0xc100
-
-#define MEM_SYS_CFG_EBI_FIX_PRI_CFCON   0x30
-
-#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
deleted file mode 100644
index 0bf73209ec7b..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* linux/arch/arm/plat-s5pc100/include/plat/regs-gpio.h
- *
- * Copyright 2009 Samsung Electronics Co.
- *      Byungho Min <bhmin@samsung.com>
- *
- * S5PC100 - GPIO register definitions
- */
-
-#ifndef __ASM_MACH_S5PC100_REGS_GPIO_H
-#define __ASM_MACH_S5PC100_REGS_GPIO_H __FILE__
-
-#include <mach/map.h>
-
-#define S5PC100EINT30CON                (S5P_VA_GPIO + 0xE00)
-#define S5P_EINT_CON(x)                 (S5PC100EINT30CON + ((x) * 0x4))
-
-#define S5PC100EINT30FLTCON0            (S5P_VA_GPIO + 0xE80)
-#define S5P_EINT_FLTCON(x)              (S5PC100EINT30FLTCON0 + ((x) * 0x4))
-
-#define S5PC100EINT30MASK               (S5P_VA_GPIO + 0xF00)
-#define S5P_EINT_MASK(x)                (S5PC100EINT30MASK + ((x) * 0x4))
-
-#define S5PC100EINT30PEND               (S5P_VA_GPIO + 0xF40)
-#define S5P_EINT_PEND(x)                (S5PC100EINT30PEND + ((x) * 0x4))
-
-#define EINT_REG_NR(x)                  (EINT_OFFSET(x) >> 3)
-
-#define eint_irq_to_bit(irq)            (1 << (EINT_OFFSET(irq) & 0x7))
-
-#define EINT_MODE               S3C_GPIO_SFN(0x2)
-
-#define EINT_GPIO_0(x)          S5PC100_GPH0(x)
-#define EINT_GPIO_1(x)          S5PC100_GPH1(x)
-#define EINT_GPIO_2(x)          S5PC100_GPH2(x)
-#define EINT_GPIO_3(x)          S5PC100_GPH3(x)
-
-#endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */
-
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-irq.h b/arch/arm/mach-s5pc100/include/mach/regs-irq.h
deleted file mode 100644
index 761627897f30..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/regs-irq.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* linux/arch/arm/mach-s5pc100/include/mach/regs-irq.h
- *
- * Copyright 2009 Samsung Electronics Co.
- *      Byungho Min <bhmin@samsung.com>
- *
- * S5PC100 - IRQ register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_IRQ_H
-#define __ASM_ARCH_REGS_IRQ_H __FILE__
-
-#include <mach/map.h>
-
-#endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
deleted file mode 100644
index 668af3ac31f3..000000000000
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ /dev/null
@@ -1,264 +0,0 @@
-/* linux/arch/arm/mach-s5pc100/mach-smdkc100.c
- *
- * Copyright 2009 Samsung Electronics Co.
- * Author: Byungho Min <bhmin@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/i2c.h>
-#include <linux/fb.h>
-#include <linux/delay.h>
-#include <linux/input.h>
-#include <linux/pwm_backlight.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include <mach/map.h>
-#include <mach/regs-gpio.h>
-
-#include <video/platform_lcd.h>
-#include <video/samsung_fimd.h>
-
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-
-#include <plat/gpio-cfg.h>
-
-#include <plat/clock.h>
-#include <plat/devs.h>
-#include <plat/cpu.h>
-#include <plat/fb.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <linux/platform_data/ata-samsung_cf.h>
-#include <plat/adc.h>
-#include <plat/keypad.h>
-#include <linux/platform_data/touchscreen-s3c2410.h>
-#include <linux/platform_data/asoc-s3c.h>
-#include <plat/backlight.h>
-#include <plat/samsung-time.h>
-
-#include "common.h"
-
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define SMDKC100_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
-                                 S3C2410_UCON_RXILEVEL |        \
-                                 S3C2410_UCON_TXIRQMODE |       \
-                                 S3C2410_UCON_RXIRQMODE |       \
-                                 S3C2410_UCON_RXFIFO_TOI |      \
-                                 S3C2443_UCON_RXERR_IRQEN)
-
-#define SMDKC100_ULCON_DEFAULT  S3C2410_LCON_CS8
-
-#define SMDKC100_UFCON_DEFAULT  (S3C2410_UFCON_FIFOMODE |       \
-                                 S3C2440_UFCON_RXTRIG8 |        \
-                                 S3C2440_UFCON_TXTRIG16)
-
-static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = {
-        [0] = {
-                .hwport      = 0,
-                .flags       = 0,
-                .ucon        = SMDKC100_UCON_DEFAULT,
-                .ulcon       = SMDKC100_ULCON_DEFAULT,
-                .ufcon       = SMDKC100_UFCON_DEFAULT,
-        },
-        [1] = {
-                .hwport      = 1,
-                .flags       = 0,
-                .ucon        = SMDKC100_UCON_DEFAULT,
-                .ulcon       = SMDKC100_ULCON_DEFAULT,
-                .ufcon       = SMDKC100_UFCON_DEFAULT,
-        },
-        [2] = {
-                .hwport      = 2,
-                .flags       = 0,
-                .ucon        = SMDKC100_UCON_DEFAULT,
-                .ulcon       = SMDKC100_ULCON_DEFAULT,
-                .ufcon       = SMDKC100_UFCON_DEFAULT,
-        },
-        [3] = {
-                .hwport      = 3,
-                .flags       = 0,
-                .ucon        = SMDKC100_UCON_DEFAULT,
-                .ulcon       = SMDKC100_ULCON_DEFAULT,
-                .ufcon       = SMDKC100_UFCON_DEFAULT,
-        },
-};
-
-/* I2C0 */
-static struct i2c_board_info i2c_devs0[] __initdata = {
-        {I2C_BOARD_INFO("wm8580", 0x1b),},
-};
-
-/* I2C1 */
-static struct i2c_board_info i2c_devs1[] __initdata = {
-};
-
-/* LCD power controller */
-static void smdkc100_lcd_power_set(struct plat_lcd_data *pd,
-                                   unsigned int power)
-{
-        if (power) {
-                /* module reset */
-                gpio_direction_output(S5PC100_GPH0(6), 1);
-                mdelay(100);
-                gpio_direction_output(S5PC100_GPH0(6), 0);
-                mdelay(10);
-                gpio_direction_output(S5PC100_GPH0(6), 1);
-                mdelay(10);
-        }
-}
-
-static struct plat_lcd_data smdkc100_lcd_power_data = {
-        .set_power      = smdkc100_lcd_power_set,
-};
-
-static struct platform_device smdkc100_lcd_powerdev = {
-        .name                   = "platform-lcd",
-        .dev.parent             = &s3c_device_fb.dev,
-        .dev.platform_data      = &smdkc100_lcd_power_data,
-};
-
-/* Frame Buffer */
-static struct s3c_fb_pd_win smdkc100_fb_win0 = {
-        .max_bpp        = 32,
-        .default_bpp    = 16,
-        .xres           = 800,
-        .yres           = 480,
-};
-
-static struct fb_videomode smdkc100_lcd_timing = {
-        .left_margin    = 8,
-        .right_margin   = 13,
-        .upper_margin   = 7,
-        .lower_margin   = 5,
-        .hsync_len      = 3,
-        .vsync_len      = 1,
-        .xres           = 800,
-        .yres           = 480,
-        .refresh        = 80,
-};
-
-static struct s3c_fb_platdata smdkc100_lcd_pdata __initdata = {
-        .win[0]         = &smdkc100_fb_win0,
-        .vtiming        = &smdkc100_lcd_timing,
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-        .setup_gpio     = s5pc100_fb_gpio_setup_24bpp,
-};
-
-static struct s3c_ide_platdata smdkc100_ide_pdata __initdata = {
-        .setup_gpio     = s5pc100_ide_setup_gpio,
-};
-
-static uint32_t smdkc100_keymap[] __initdata = {
-        /* KEY(row, col, keycode) */
-        KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3),
-        KEY(0, 6, KEY_4), KEY(0, 7, KEY_5),
-        KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C),
-        KEY(1, 6, KEY_D), KEY(1, 7, KEY_E)
-};
-
-static struct matrix_keymap_data smdkc100_keymap_data __initdata = {
-        .keymap         = smdkc100_keymap,
-        .keymap_size    = ARRAY_SIZE(smdkc100_keymap),
-};
-
-static struct samsung_keypad_platdata smdkc100_keypad_data __initdata = {
-        .keymap_data    = &smdkc100_keymap_data,
-        .rows           = 2,
-        .cols           = 8,
-};
-
-static struct platform_device *smdkc100_devices[] __initdata = {
-        &s3c_device_adc,
-        &s3c_device_cfcon,
-        &s3c_device_i2c0,
-        &s3c_device_i2c1,
-        &s3c_device_fb,
-        &s3c_device_hsmmc0,
-        &s3c_device_hsmmc1,
-        &s3c_device_hsmmc2,
-        &samsung_device_pwm,
-        &s3c_device_ts,
-        &s3c_device_wdt,
-        &smdkc100_lcd_powerdev,
-        &s5pc100_device_iis0,
-        &samsung_device_keypad,
-        &s5pc100_device_ac97,
-        &s3c_device_rtc,
-        &s5p_device_fimc0,
-        &s5p_device_fimc1,
-        &s5p_device_fimc2,
-        &s5pc100_device_spdif,
-};
-
-/* LCD Backlight data */
-static struct samsung_bl_gpio_info smdkc100_bl_gpio_info = {
-        .no = S5PC100_GPD(0),
-        .func = S3C_GPIO_SFN(2),
-};
-
-static struct platform_pwm_backlight_data smdkc100_bl_data = {
-        .pwm_id = 0,
-        .enable_gpio = -1,
-};
-
-static void __init smdkc100_map_io(void)
-{
-        s5pc100_init_io(NULL, 0);
-        s3c24xx_init_clocks(12000000);
-        s3c24xx_init_uarts(smdkc100_uartcfgs, ARRAY_SIZE(smdkc100_uartcfgs));
-        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
-}
-
-static void __init smdkc100_machine_init(void)
-{
-        s3c24xx_ts_set_platdata(NULL);
-
-        /* I2C */
-        s3c_i2c0_set_platdata(NULL);
-        s3c_i2c1_set_platdata(NULL);
-        i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
-        i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
-
-        s3c_fb_set_platdata(&smdkc100_lcd_pdata);
-        s3c_ide_set_platdata(&smdkc100_ide_pdata);
-
-        samsung_keypad_set_platdata(&smdkc100_keypad_data);
-
-        s5pc100_spdif_setup_gpio(S5PC100_SPDIF_GPD);
-
-        /* LCD init */
-        gpio_request(S5PC100_GPH0(6), "GPH0");
-        smdkc100_lcd_power_set(&smdkc100_lcd_power_data, 0);
-
-        platform_add_devices(smdkc100_devices, ARRAY_SIZE(smdkc100_devices));
-
-        samsung_bl_set(&smdkc100_bl_gpio_info, &smdkc100_bl_data);
-}
-
-MACHINE_START(SMDKC100, "SMDKC100")
-        /* Maintainer: Byungho Min <bhmin@samsung.com> */
-        .atag_offset    = 0x100,
-        .init_irq       = s5pc100_init_irq,
-        .map_io         = smdkc100_map_io,
-        .init_machine   = smdkc100_machine_init,
-        .init_time      = samsung_timer_init,
-        .restart        = s5pc100_restart,
-MACHINE_END
diff --git a/arch/arm/mach-s5pc100/setup-fb-24bpp.c b/arch/arm/mach-s5pc100/setup-fb-24bpp.c
deleted file mode 100644
index 8978e4cf9ed5..000000000000
--- a/arch/arm/mach-s5pc100/setup-fb-24bpp.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * linux/arch/arm/mach-s5pc100/setup-fb-24bpp.c
- *
- * Copyright 2009 Samsung Electronics
- *
- * Base S5PC100 setup information for 24bpp LCD framebuffer
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/fb.h>
-#include <linux/gpio.h>
-
-#include <mach/map.h>
-#include <plat/fb.h>
-#include <plat/gpio-cfg.h>
-
-#define DISR_OFFSET     0x7008
-
-static void s5pc100_fb_setgpios(unsigned int base, unsigned int nr)
-{
-        s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(2));
-}
-
-void s5pc100_fb_gpio_setup_24bpp(void)
-{
-        s5pc100_fb_setgpios(S5PC100_GPF0(0), 8);
-        s5pc100_fb_setgpios(S5PC100_GPF1(0), 8);
-        s5pc100_fb_setgpios(S5PC100_GPF2(0), 8);
-        s5pc100_fb_setgpios(S5PC100_GPF3(0), 4);
-}
diff --git a/arch/arm/mach-s5pc100/setup-i2c0.c b/arch/arm/mach-s5pc100/setup-i2c0.c
deleted file mode 100644
index 89a6a769d622..000000000000
--- a/arch/arm/mach-s5pc100/setup-i2c0.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* linux/arch/arm/mach-s5pc100/setup-i2c0.c
- *
- * Copyright 2009 Samsung Electronics Co.
- *      Byungho Min <bhmin@samsung.com>
- *
- * Base S5PC100 I2C bus 0 gpio configuration
- *
- * Based on plat-s3c64xx/setup-i2c0.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-
-struct platform_device; /* don't need the contents */
-
-#include <linux/gpio.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-
-void s3c_i2c0_cfg_gpio(struct platform_device *dev)
-{
-        s3c_gpio_cfgall_range(S5PC100_GPD(3), 2,
-                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-s5pc100/setup-i2c1.c b/arch/arm/mach-s5pc100/setup-i2c1.c
deleted file mode 100644
index faa667ef02cb..000000000000
--- a/arch/arm/mach-s5pc100/setup-i2c1.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* linux/arch/arm/mach-s5pc100/setup-i2c1.c
- *
- * Copyright 2009 Samsung Electronics Co.
- *      Byungho Min <bhmin@samsung.com>
- *
- * Base S5PC100 I2C bus 1 gpio configuration
- *
- * Based on plat-s3c64xx/setup-i2c1.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-
-struct platform_device; /* don't need the contents */
-
-#include <linux/gpio.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-
-void s3c_i2c1_cfg_gpio(struct platform_device *dev)
-{
-        s3c_gpio_cfgall_range(S5PC100_GPD(5), 2,
-                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-s5pc100/setup-ide.c b/arch/arm/mach-s5pc100/setup-ide.c
deleted file mode 100644
index 223aae044466..000000000000
--- a/arch/arm/mach-s5pc100/setup-ide.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/* linux/arch/arm/mach-s5pc100/setup-ide.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * S5PC100 setup information for IDE
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/gpio.h>
-#include <linux/io.h>
-
-#include <mach/regs-clock.h>
-#include <plat/gpio-cfg.h>
-
-static void s5pc100_ide_cfg_gpios(unsigned int base, unsigned int nr)
-{
-        s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(4));
-
-        for (; nr > 0; nr--, base++)
-                s5p_gpio_set_drvstr(base, S5P_GPIO_DRVSTR_LV4);
-}
-
-void s5pc100_ide_setup_gpio(void)
-{
-        u32 reg;
-
-        /* Independent CF interface, CF chip select configuration */
-        reg = readl(S5PC100_MEM_SYS_CFG) & (~0x3f);
-        writel(reg | MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S5PC100_MEM_SYS_CFG);
-
-        /* CF_Add[0 - 2], CF_IORDY, CF_INTRQ, CF_DMARQ, CF_DMARST, CF_DMACK */
-        s5pc100_ide_cfg_gpios(S5PC100_GPJ0(0), 8);
-
-        /*CF_Data[0 - 7] */
-        s5pc100_ide_cfg_gpios(S5PC100_GPJ2(0), 8);
-
-        /* CF_Data[8 - 15] */
-        s5pc100_ide_cfg_gpios(S5PC100_GPJ3(0), 8);
-
-        /* CF_CS0, CF_CS1, CF_IORD, CF_IOWR */
-        s5pc100_ide_cfg_gpios(S5PC100_GPJ4(0), 4);
-
-        /* EBI_OE, EBI_WE */
-        s3c_gpio_cfgpin_range(S5PC100_GPK0(6), 2, S3C_GPIO_SFN(0));
-
-        /* CF_OE, CF_WE */
-        s3c_gpio_cfgrange_nopull(S5PC100_GPK1(6), 8, S3C_GPIO_SFN(2));
-
-        /* CF_CD */
-        s3c_gpio_cfgpin(S5PC100_GPK3(5), S3C_GPIO_SFN(2));
-        s3c_gpio_setpull(S5PC100_GPK3(5), S3C_GPIO_PULL_NONE);
-}
diff --git a/arch/arm/mach-s5pc100/setup-keypad.c b/arch/arm/mach-s5pc100/setup-keypad.c
deleted file mode 100644
index ada377f0c206..000000000000
--- a/arch/arm/mach-s5pc100/setup-keypad.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/* linux/arch/arm/mach-s5pc100/setup-keypad.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * GPIO configuration for S5PC100 KeyPad device
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/gpio.h>
-#include <plat/gpio-cfg.h>
-
-void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
-{
-        /* Set all the necessary GPH3 pins to special-function 3: KP_ROW[x] */
-        s3c_gpio_cfgrange_nopull(S5PC100_GPH3(0), rows, S3C_GPIO_SFN(3));
-
-        /* Set all the necessary GPH2 pins to special-function 3: KP_COL[x] */
-        s3c_gpio_cfgrange_nopull(S5PC100_GPH2(0), cols, S3C_GPIO_SFN(3));
-}
diff --git a/arch/arm/mach-s5pc100/setup-sdhci-gpio.c b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
deleted file mode 100644
index 6010c0310cb5..000000000000
--- a/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/* linux/arch/arm/plat-s5pc100/setup-sdhci-gpio.c
- *
- * Copyright 2009 Samsung Eletronics
- *
- * S5PC100 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/mmc/host.h>
-#include <linux/mmc/card.h>
-
-#include <plat/gpio-cfg.h>
-#include <plat/sdhci.h>
-
-void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
-{
-        struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-        unsigned int num;
-
-        num = width;
-        /* In case of 8 width, we should decrease the 2 */
-        if (width == 8)
-                num = width - 2;
-
-        /* Set all the necessary GPG0/GPG1 pins to special-function 0 */
-        s3c_gpio_cfgrange_nopull(S5PC100_GPG0(0), 2 + num, S3C_GPIO_SFN(2));
-
-        if (width == 8)
-                s3c_gpio_cfgrange_nopull(S5PC100_GPG1(0), 2, S3C_GPIO_SFN(2));
-
-        if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
-                s3c_gpio_setpull(S5PC100_GPG1(2), S3C_GPIO_PULL_UP);
-                s3c_gpio_cfgpin(S5PC100_GPG1(2), S3C_GPIO_SFN(2));
-        }
-}
-
-void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
-{
-        struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-
-        /* Set all the necessary GPG2 pins to special-function 2 */
-        s3c_gpio_cfgrange_nopull(S5PC100_GPG2(0), 2 + width, S3C_GPIO_SFN(2));
-
-        if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
-                s3c_gpio_setpull(S5PC100_GPG2(6), S3C_GPIO_PULL_UP);
-                s3c_gpio_cfgpin(S5PC100_GPG2(6), S3C_GPIO_SFN(2));
-        }
-}
-
-void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
-{
-        struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-
-        /* Set all the necessary GPG3 pins to special-function 2 */
-        s3c_gpio_cfgrange_nopull(S5PC100_GPG3(0), 2 + width, S3C_GPIO_SFN(2));
-
-        if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
-                s3c_gpio_setpull(S5PC100_GPG3(6), S3C_GPIO_PULL_UP);
-                s3c_gpio_cfgpin(S5PC100_GPG3(6), S3C_GPIO_SFN(2));
-        }
-}
diff --git a/arch/arm/mach-s5pc100/setup-spi.c b/arch/arm/mach-s5pc100/setup-spi.c
deleted file mode 100644
index 183567961de1..000000000000
--- a/arch/arm/mach-s5pc100/setup-spi.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* linux/arch/arm/mach-s5pc100/setup-spi.c
- *
- * Copyright (C) 2011 Samsung Electronics Ltd.
- *              http://www.samsung.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/gpio.h>
-#include <plat/gpio-cfg.h>
-
-#ifdef CONFIG_S3C64XX_DEV_SPI0
-int s3c64xx_spi0_cfg_gpio(void)
-{
-        s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,
-                                S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-        return 0;
-}
-#endif
-
-#ifdef CONFIG_S3C64XX_DEV_SPI1
-int s3c64xx_spi1_cfg_gpio(void)
-{
-        s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,
-                                S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-        return 0;
-}
-#endif
-
-#ifdef CONFIG_S3C64XX_DEV_SPI2
-int s3c64xx_spi2_cfg_gpio(void)
-{
-        s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
-        s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);
-        s3c_gpio_cfgall_range(S5PC100_GPB(2), 2,
-                                S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
-        return 0;
-}
-#endif
diff --git a/arch/arm/mach-s5pv210/dev-audio.c b/arch/arm/mach-s5pv210/dev-audio.c
index 2d67361ef431..90356ad10c54 100644
--- a/arch/arm/mach-s5pv210/dev-audio.c
+++ b/arch/arm/mach-s5pv210/dev-audio.c
@@ -10,7 +10,6 @@
 
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
-#include <linux/gpio.h>
 
 #include <plat/gpio-cfg.h>
 #include <linux/platform_data/asoc-s3c.h>
@@ -18,6 +17,7 @@
 #include <mach/map.h>
 #include <mach/dma.h>
 #include <mach/irqs.h>
+#include <mach/gpio-samsung.h>
 
 #define S5PV210_AUDSS_INT_MEM   (0xC0000000)
 
diff --git a/arch/arm/mach-s5pv210/include/mach/gpio.h b/arch/arm/mach-s5pv210/include/mach/gpio-samsung.h
index 6c8b903c02e4..e193b891e7b2 100644
--- a/arch/arm/mach-s5pv210/include/mach/gpio.h
+++ b/arch/arm/mach-s5pv210/include/mach/gpio-samsung.h
@@ -1,5 +1,4 @@
-/* linux/arch/arm/mach-s5pv210/include/mach/gpio.h
- *
+/*
  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com/
  *
@@ -133,8 +132,4 @@ enum s5p_gpio_number {
 #define S5PV210_GPIO_END        (S5PV210_MP05(S5PV210_GPIO_MP05_NR) + 1)
 #define S3C_GPIO_END            S5PV210_GPIO_END
 
-/* define the number of gpios we need to the one after the MP05() range */
-#define ARCH_NR_GPIOS           (S5PV210_MP05(S5PV210_GPIO_MP05_NR) +   \
-                                 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
-
 #endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index cc37edacda26..4262d8ff1988 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -31,6 +31,7 @@
 #include <video/samsung_fimd.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
+#include <mach/gpio-samsung.h>
 
 #include <plat/gpio-cfg.h>
 #include <plat/devs.h>
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index c1ce921c4088..096a8173a1d9 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -38,6 +38,7 @@
 #include <video/samsung_fimd.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
+#include <mach/gpio-samsung.h>
 
 #include <plat/gpio-cfg.h>
 #include <plat/devs.h>
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 2a6655fb63e7..a146089c9ee6 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -32,6 +32,7 @@
 
 #include <mach/map.h>
 #include <mach/regs-clock.h>
+#include <mach/gpio-samsung.h>
 
 #include <plat/regs-srom.h>
 #include <plat/gpio-cfg.h>
diff --git a/arch/arm/mach-s5pv210/setup-fb-24bpp.c b/arch/arm/mach-s5pv210/setup-fb-24bpp.c
index 55103c8220b3..815e329f70c4 100644
--- a/arch/arm/mach-s5pv210/setup-fb-24bpp.c
+++ b/arch/arm/mach-s5pv210/setup-fb-24bpp.c
@@ -13,12 +13,12 @@
 #include <linux/kernel.h>
 #include <linux/types.h>
 #include <linux/fb.h>
-#include <linux/gpio.h>
 
 #include <mach/map.h>
 #include <plat/fb.h>
 #include <mach/regs-clock.h>
 #include <plat/gpio-cfg.h>
+#include <mach/gpio-samsung.h>
 
 static void s5pv210_fb_cfg_gpios(unsigned int base, unsigned int nr)
 {
diff --git a/arch/arm/mach-s5pv210/setup-fimc.c b/arch/arm/mach-s5pv210/setup-fimc.c
index 54cc5b11be0b..36945ec437f8 100644
--- a/arch/arm/mach-s5pv210/setup-fimc.c
+++ b/arch/arm/mach-s5pv210/setup-fimc.c
@@ -8,9 +8,10 @@
  * published by the Free Software Foundation.
  */
 
-#include <linux/gpio.h>
+#include <linux/kernel.h>
 #include <plat/gpio-cfg.h>
 #include <plat/camport.h>
+#include <mach/gpio-samsung.h>
 
 int s5pv210_fimc_setup_gpio(enum s5p_camport_id id)
 {
diff --git a/arch/arm/mach-s5pv210/setup-i2c0.c b/arch/arm/mach-s5pv210/setup-i2c0.c
index 4a15849766c0..b0f2b69ac743 100644
--- a/arch/arm/mach-s5pv210/setup-i2c0.c
+++ b/arch/arm/mach-s5pv210/setup-i2c0.c
@@ -14,12 +14,12 @@
 
 #include <linux/kernel.h>
 #include <linux/types.h>
-#include <linux/gpio.h>
 
 struct platform_device; /* don't need the contents */
 
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
+#include <mach/gpio-samsung.h>
 
 void s3c_i2c0_cfg_gpio(struct platform_device *dev)
 {
diff --git a/arch/arm/mach-s5pv210/setup-i2c1.c b/arch/arm/mach-s5pv210/setup-i2c1.c
index 4777f6b97a92..aac1da7b9071 100644
--- a/arch/arm/mach-s5pv210/setup-i2c1.c
+++ b/arch/arm/mach-s5pv210/setup-i2c1.c
@@ -14,12 +14,12 @@
 
 #include <linux/kernel.h>
 #include <linux/types.h>
-#include <linux/gpio.h>
 
 struct platform_device; /* don't need the contents */
 
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
+#include <mach/gpio-samsung.h>
 
 void s3c_i2c1_cfg_gpio(struct platform_device *dev)
 {
diff --git a/arch/arm/mach-s5pv210/setup-i2c2.c b/arch/arm/mach-s5pv210/setup-i2c2.c
index bbce6c74b915..eff4503b903f 100644
--- a/arch/arm/mach-s5pv210/setup-i2c2.c
+++ b/arch/arm/mach-s5pv210/setup-i2c2.c
@@ -14,12 +14,12 @@
 
 #include <linux/kernel.h>
 #include <linux/types.h>
-#include <linux/gpio.h>
 
 struct platform_device; /* don't need the contents */
 
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
+#include <mach/gpio-samsung.h>
 
 void s3c_i2c2_cfg_gpio(struct platform_device *dev)
 {
diff --git a/arch/arm/mach-s5pv210/setup-ide.c b/arch/arm/mach-s5pv210/setup-ide.c
index ea123d546bd2..5b6042d97892 100644
--- a/arch/arm/mach-s5pv210/setup-ide.c
+++ b/arch/arm/mach-s5pv210/setup-ide.c
@@ -11,9 +11,9 @@
 */
 
 #include <linux/kernel.h>
-#include <linux/gpio.h>
 
 #include <plat/gpio-cfg.h>
+#include <mach/gpio-samsung.h>
 
 static void s5pv210_ide_cfg_gpios(unsigned int base, unsigned int nr)
 {
diff --git a/arch/arm/mach-s5pv210/setup-keypad.c b/arch/arm/mach-s5pv210/setup-keypad.c
index c56420a52f48..faf6178f3a1b 100644
--- a/arch/arm/mach-s5pv210/setup-keypad.c
+++ b/arch/arm/mach-s5pv210/setup-keypad.c
@@ -11,8 +11,8 @@
  *
  */
 
-#include <linux/gpio.h>
 #include <plat/gpio-cfg.h>
+#include <mach/gpio-samsung.h>
 
 void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
 {
diff --git a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
index 0512ada00522..0dd055b47579 100644
--- a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
+++ b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
@@ -15,12 +15,12 @@
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
-#include <linux/gpio.h>
 #include <linux/mmc/host.h>
 #include <linux/mmc/card.h>
 
 #include <plat/gpio-cfg.h>
 #include <plat/sdhci.h>
+#include <mach/gpio-samsung.h>
 
 void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
 {
diff --git a/arch/arm/mach-s5pv210/setup-spi.c b/arch/arm/mach-s5pv210/setup-spi.c
index 81aecc162f82..e1faf8ea4502 100644
--- a/arch/arm/mach-s5pv210/setup-spi.c
+++ b/arch/arm/mach-s5pv210/setup-spi.c
@@ -8,8 +8,8 @@
  * published by the Free Software Foundation.
  */
 
-#include <linux/gpio.h>
 #include <plat/gpio-cfg.h>
+#include <mach/gpio-samsung.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
 int s3c64xx_spi0_cfg_gpio(void)
diff --git a/arch/arm/mach-shmobile/board-ape6evm-reference.c b/arch/arm/mach-shmobile/board-ape6evm-reference.c
index 3276afcf3cc9..2f7723e5fe91 100644
--- a/arch/arm/mach-shmobile/board-ape6evm-reference.c
+++ b/arch/arm/mach-shmobile/board-ape6evm-reference.c
@@ -24,11 +24,13 @@
 #include <linux/pinctrl/machine.h>
 #include <linux/platform_device.h>
 #include <linux/sh_clk.h>
-#include <mach/common.h>
-#include <mach/r8a73a4.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include "common.h"
+#include "r8a73a4.h"
+
 static void __init ape6evm_add_standard_devices(void)
 {
 
diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c
index 7ab99a4972a0..1585b8830b13 100644
--- a/arch/arm/mach-shmobile/board-ape6evm.c
+++ b/arch/arm/mach-shmobile/board-ape6evm.c
@@ -33,12 +33,14 @@
 #include <linux/regulator/machine.h>
 #include <linux/sh_clk.h>
 #include <linux/smsc911x.h>
-#include <mach/common.h>
-#include <mach/irqs.h>
-#include <mach/r8a73a4.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include "common.h"
+#include "irqs.h"
+#include "r8a73a4.h"
+
 /* LEDS */
 static struct gpio_led ape6evm_leds[] = {
         {
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
index f660fbb96e0b..208576667b22 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
@@ -24,11 +24,13 @@
 #include <linux/kernel.h>
 #include <linux/gpio.h>
 #include <linux/io.h>
-#include <mach/common.h>
-#include <mach/r8a7740.h>
+
 #include <asm/mach/arch.h>
 #include <asm/hardware/cache-l2x0.h>
 
+#include "common.h"
+#include "r8a7740.h"
+
 /*
  * CON1         Camera Module
  * CON2         Extension Bus
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 689c121157ec..42b6afaa69af 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -45,9 +45,7 @@
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/i2c-gpio.h>
 #include <linux/reboot.h>
-#include <mach/common.h>
-#include <mach/irqs.h>
-#include <mach/r8a7740.h>
+
 #include <media/mt9t112.h>
 #include <media/sh_mobile_ceu.h>
 #include <media/soc_camera.h>
@@ -62,6 +60,10 @@
 #include <sound/sh_fsi.h>
 #include <sound/simple_card.h>
 
+#include "common.h"
+#include "irqs.h"
+#include "pm-rmobile.h"
+#include "r8a7740.h"
 #include "sh-gpio.h"
 
 /*
diff --git a/arch/arm/mach-shmobile/board-bockw-reference.c b/arch/arm/mach-shmobile/board-bockw-reference.c
index 027373f8de82..ba840cd333b9 100644
--- a/arch/arm/mach-shmobile/board-bockw-reference.c
+++ b/arch/arm/mach-shmobile/board-bockw-reference.c
@@ -19,10 +19,12 @@
  */
 
 #include <linux/of_platform.h>
-#include <mach/common.h>
-#include <mach/r8a7778.h>
+
 #include <asm/mach/arch.h>
 
+#include "common.h"
+#include "r8a7778.h"
+
 /*
  *      see board-bock.c for checking detail of dip-switch
  */
diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c
index 3ec82a4c35c5..8a83eb39d3f1 100644
--- a/arch/arm/mach-shmobile/board-bockw.c
+++ b/arch/arm/mach-shmobile/board-bockw.c
@@ -34,14 +34,16 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 #include <linux/usb/renesas_usbhs.h>
+
 #include <media/soc_camera.h>
-#include <mach/common.h>
-#include <mach/irqs.h>
-#include <mach/r8a7778.h>
 #include <asm/mach/arch.h>
 #include <sound/rcar_snd.h>
 #include <sound/simple_card.h>
 
+#include "common.h"
+#include "irqs.h"
+#include "r8a7778.h"
+
 #define FPGA    0x18200000
 #define IRQ0MR  0x30
 #define COMCTLR 0x101c
diff --git a/arch/arm/mach-shmobile/board-genmai-reference.c b/arch/arm/mach-shmobile/board-genmai-reference.c
index 2ff6ad6e608e..e5448f7b868a 100644
--- a/arch/arm/mach-shmobile/board-genmai-reference.c
+++ b/arch/arm/mach-shmobile/board-genmai-reference.c
@@ -20,12 +20,14 @@
 
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
-#include <mach/clock.h>
-#include <mach/common.h>
-#include <mach/r7s72100.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include "clock.h"
+#include "common.h"
+#include "r7s72100.h"
+
 /*
  * This is a really crude hack to provide clkdev support to platform
  * devices until they get moved to DT.
@@ -47,7 +49,7 @@ static const char * const genmai_boards_compat_dt[] __initconst = {
 };
 
 DT_MACHINE_START(GENMAI_DT, "genmai")
-        .init_early     = r7s72100_init_early,
+        .init_early     = shmobile_init_delay,
         .init_machine   = genmai_add_standard_devices,
         .dt_compat      = genmai_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-genmai.c b/arch/arm/mach-shmobile/board-genmai.c
index 37184ff8c5c2..7bf2d8057535 100644
--- a/arch/arm/mach-shmobile/board-genmai.c
+++ b/arch/arm/mach-shmobile/board-genmai.c
@@ -25,12 +25,14 @@
 #include <linux/sh_eth.h>
 #include <linux/spi/rspi.h>
 #include <linux/spi/spi.h>
-#include <mach/common.h>
-#include <mach/irqs.h>
-#include <mach/r7s72100.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include "common.h"
+#include "irqs.h"
+#include "r7s72100.h"
+
 /* Ether */
 static const struct sh_eth_plat_data ether_pdata __initconst = {
         .phy                    = 0x00, /* PD60610 */
@@ -153,7 +155,7 @@ static const char * const genmai_boards_compat_dt[] __initconst = {
 };
 
 DT_MACHINE_START(GENMAI_DT, "genmai")
-        .init_early     = r7s72100_init_early,
+        .init_early     = shmobile_init_delay,
         .init_machine   = genmai_add_standard_devices,
         .dt_compat      = genmai_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-koelsch-reference.c b/arch/arm/mach-shmobile/board-koelsch-reference.c
index d322a162b4b0..1d3f67d4ccd6 100644
--- a/arch/arm/mach-shmobile/board-koelsch-reference.c
+++ b/arch/arm/mach-shmobile/board-koelsch-reference.c
@@ -23,12 +23,12 @@
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
 #include <linux/platform_data/rcar-du.h>
-#include <mach/clock.h>
-#include <mach/common.h>
-#include <mach/irqs.h>
-#include <mach/rcar-gen2.h>
 #include <mach/r8a7791.h>
 #include <asm/mach/arch.h>
+#include "clock.h"
+#include "common.h"
+#include "irqs.h"
+#include "rcar-gen2.h"
 
 /* DU */
 static struct rcar_du_encoder_data koelsch_du_encoders[] = {
diff --git a/arch/arm/mach-shmobile/board-koelsch.c b/arch/arm/mach-shmobile/board-koelsch.c
index d3aa6ae05eeb..c932f2ca85b1 100644
--- a/arch/arm/mach-shmobile/board-koelsch.c
+++ b/arch/arm/mach-shmobile/board-koelsch.c
@@ -45,12 +45,12 @@
 #include <linux/spi/flash.h>
 #include <linux/spi/rspi.h>
 #include <linux/spi/spi.h>
-#include <mach/common.h>
-#include <mach/irqs.h>
 #include <mach/r8a7791.h>
-#include <mach/rcar-gen2.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include "common.h"
+#include "irqs.h"
+#include "rcar-gen2.h"
 
 /* DU */
 static struct rcar_du_encoder_data koelsch_du_encoders[] = {
diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
index a735a1d80c28..5d2621f202d1 100644
--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c
+++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
@@ -25,12 +25,14 @@
 #include <linux/irq.h>
 #include <linux/input.h>
 #include <linux/of_platform.h>
-#include <mach/sh73a0.h>
-#include <mach/common.h>
+
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include "common.h"
+#include "sh73a0.h"
+
 static void __init kzm_init(void)
 {
         sh73a0_add_standard_devices_dt();
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index 01e0d1386db7..f8bc7f8f86ad 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -41,16 +41,18 @@
 #include <linux/usb/r8a66597.h>
 #include <linux/usb/renesas_usbhs.h>
 #include <linux/videodev2.h>
+
 #include <sound/sh_fsi.h>
 #include <sound/simple_card.h>
-#include <mach/irqs.h>
-#include <mach/sh73a0.h>
-#include <mach/common.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <video/sh_mobile_lcdc.h>
 
+#include "common.h"
+#include "irqs.h"
+#include "sh73a0.h"
+
 /*
  * external GPIO
  */
diff --git a/arch/arm/mach-shmobile/board-lager-reference.c b/arch/arm/mach-shmobile/board-lager-reference.c
index 749832e3f33c..8dcff51a8f45 100644
--- a/arch/arm/mach-shmobile/board-lager-reference.c
+++ b/arch/arm/mach-shmobile/board-lager-reference.c
@@ -22,13 +22,15 @@
 #include <linux/init.h>
 #include <linux/of_platform.h>
 #include <linux/platform_data/rcar-du.h>
-#include <mach/clock.h>
-#include <mach/common.h>
-#include <mach/irqs.h>
-#include <mach/rcar-gen2.h>
-#include <mach/r8a7790.h>
+
 #include <asm/mach/arch.h>
 
+#include "clock.h"
+#include "common.h"
+#include "irqs.h"
+#include "r8a7790.h"
+#include "rcar-gen2.h"
+
 /* DU */
 static struct rcar_du_encoder_data lager_du_encoders[] = {
         {
@@ -129,7 +131,7 @@ static const char *lager_boards_compat_dt[] __initdata = {
 
 DT_MACHINE_START(LAGER_DT, "lager")
         .smp            = smp_ops(r8a7790_smp_ops),
-        .init_early     = r8a7790_init_early,
+        .init_early     = shmobile_init_delay,
         .init_time      = rcar_gen2_timer_init,
         .init_machine   = lager_add_standard_devices,
         .init_late      = shmobile_init_late,
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index d18296164e89..18331ac375f1 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -31,6 +31,8 @@
 #include <linux/mmc/host.h>
 #include <linux/mmc/sh_mmcif.h>
 #include <linux/mmc/sh_mobile_sdhi.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/mtd.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/platform_data/camera-rcar.h>
 #include <linux/platform_data/gpio-rcar.h>
@@ -43,22 +45,23 @@
 #include <linux/regulator/gpio-regulator.h>
 #include <linux/regulator/machine.h>
 #include <linux/sh_eth.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/rspi.h>
+#include <linux/spi/spi.h>
 #include <linux/usb/phy.h>
 #include <linux/usb/renesas_usbhs.h>
-#include <mach/common.h>
-#include <mach/irqs.h>
-#include <mach/r8a7790.h>
+
 #include <media/soc_camera.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/mtd.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/rspi.h>
-#include <linux/spi/spi.h>
 #include <sound/rcar_snd.h>
 #include <sound/simple_card.h>
 
+#include "common.h"
+#include "irqs.h"
+#include "r8a7790.h"
+#include "rcar-gen2.h"
+
 /*
  * SSI-AK4643
  *
@@ -880,7 +883,7 @@ static const char * const lager_boards_compat_dt[] __initconst = {
 
 DT_MACHINE_START(LAGER_DT, "lager")
         .smp            = smp_ops(r8a7790_smp_ops),
-        .init_early     = r8a7790_init_early,
+        .init_early     = shmobile_init_delay,
         .init_time      = rcar_gen2_timer_init,
         .init_machine   = lager_init,
         .init_late      = shmobile_init_late,
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 112553f0f9bf..79f448e93abb 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -47,10 +47,11 @@
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
-#include <linux/sh_intc.h>
+#include <linux/sh_clk.h>
 #include <linux/tca6416_keypad.h>
 #include <linux/usb/renesas_usbhs.h>
 #include <linux/dma-mapping.h>
+
 #include <video/sh_mobile_hdmi.h>
 #include <video/sh_mobile_lcdc.h>
 #include <media/sh_mobile_ceu.h>
@@ -58,15 +59,14 @@
 #include <media/soc_camera_platform.h>
 #include <sound/sh_fsi.h>
 #include <sound/simple_card.h>
-
-#include <mach/common.h>
-#include <mach/irqs.h>
-#include <mach/sh7372.h>
-
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
+#include "common.h"
+#include "irqs.h"
+#include "pm-rmobile.h"
 #include "sh-gpio.h"
+#include "sh7372.h"
 
 /*
  * Address      Interface               BusWidth        note
diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index 2773936bf7dc..94bd57203ff5 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -20,10 +20,10 @@
  */
 
 #include <mach/r8a7779.h>
-#include <mach/common.h>
-#include <mach/irqs.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
+#include "common.h"
+#include "irqs.h"
 
 static void __init marzen_init(void)
 {
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index 6ed324ce848f..d0b5b746fe05 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -43,11 +43,11 @@
 #include <linux/mfd/tmio.h>
 #include <media/soc_camera.h>
 #include <mach/r8a7779.h>
-#include <mach/common.h>
-#include <mach/irqs.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/traps.h>
+#include "common.h"
+#include "irqs.h"
 
 /* Fixed 3.3V regulator to be used by SDHI0 */
 static struct regulator_consumer_supply fixed3v3_power_consumers[] = {
diff --git a/arch/arm/mach-shmobile/clock-r7s72100.c b/arch/arm/mach-shmobile/clock-r7s72100.c
index df187484de5d..3eb2ec401e0c 100644
--- a/arch/arm/mach-shmobile/clock-r7s72100.c
+++ b/arch/arm/mach-shmobile/clock-r7s72100.c
@@ -19,8 +19,9 @@
 #include <linux/io.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
-#include <mach/common.h>
-#include <mach/r7s72100.h>
+
+#include "common.h"
+#include "r7s72100.h"
 
 /* Frequency Control Registers */
 #define FRQCR           0xfcfe0010
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
index b5bc22c6a858..0f431498229b 100644
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -22,8 +22,8 @@
 #include <linux/kernel.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
-#include <mach/clock.h>
-#include <mach/common.h>
+#include "common.h"
+#include "clock.h"
 
 #define CPG_BASE 0xe6150000
 #define CPG_LEN 0x270
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index 50931e3c97c7..789091cfa37a 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -22,9 +22,10 @@
 #include <linux/io.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
-#include <mach/clock.h>
-#include <mach/common.h>
-#include <mach/r8a7740.h>
+
+#include "clock.h"
+#include "common.h"
+#include "r8a7740.h"
 
 /*
  *        |  MDx  |  XTAL1/EXTAL1   |  System   | EXTALR |
diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c
index 13f8f3ab8840..16bbc94a1520 100644
--- a/arch/arm/mach-shmobile/clock-r8a7778.c
+++ b/arch/arm/mach-shmobile/clock-r8a7778.c
@@ -39,8 +39,8 @@
 #include <linux/io.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
-#include <mach/clock.h>
-#include <mach/common.h>
+#include "clock.h"
+#include "common.h"
 
 #define MSTPCR0         IOMEM(0xffc80030)
 #define MSTPCR1         IOMEM(0xffc80034)
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index a13298bd37a8..d81539a26dbd 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -23,8 +23,8 @@
 #include <linux/io.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
-#include <mach/clock.h>
-#include <mach/common.h>
+#include "clock.h"
+#include "common.h"
 
 /*
  *              MD1 = 1                 MD1 = 0
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index 296a057109e4..17435c1aa2fe 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -22,9 +22,11 @@
 #include <linux/kernel.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
-#include <mach/clock.h>
-#include <mach/common.h>
-#include <mach/r8a7790.h>
+
+#include "clock.h"
+#include "common.h"
+#include "r8a7790.h"
+#include "rcar-gen2.h"
 
 /*
  *   MD         EXTAL           PLL0    PLL1    PLL3
diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c
index e2fdfcc14436..10e193d707f5 100644
--- a/arch/arm/mach-shmobile/clock-r8a7791.c
+++ b/arch/arm/mach-shmobile/clock-r8a7791.c
@@ -23,9 +23,9 @@
 #include <linux/kernel.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
-#include <mach/clock.h>
-#include <mach/common.h>
-#include <mach/rcar-gen2.h>
+#include "clock.h"
+#include "common.h"
+#include "rcar-gen2.h"
 
 /*
  *   MD         EXTAL           PLL0    PLL1    PLL3
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index d16d9ca7f79e..7071676145c4 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -21,8 +21,8 @@
 #include <linux/io.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
-#include <mach/clock.h>
-#include <mach/common.h>
+#include "clock.h"
+#include "common.h"
 
 /* SH7372 registers */
 #define FRQCRA          IOMEM(0xe6150000)
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 0d9cd1fe0212..37f48383e05a 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -22,8 +22,8 @@
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
 #include <asm/processor.h>
-#include <mach/clock.h>
-#include <mach/common.h>
+#include "clock.h"
+#include "common.h"
 
 #define FRQCRA          IOMEM(0xe6150000)
 #define FRQCRB          IOMEM(0xe6150004)
diff --git a/arch/arm/mach-shmobile/clock.c b/arch/arm/mach-shmobile/clock.c
index e7232a0373b9..806f94038cc4 100644
--- a/arch/arm/mach-shmobile/clock.c
+++ b/arch/arm/mach-shmobile/clock.c
@@ -25,7 +25,7 @@
 #ifdef CONFIG_COMMON_CLK
 #include <linux/clk.h>
 #include <linux/clkdev.h>
-#include <mach/clock.h>
+#include "clock.h"
 
 void __init shmobile_clk_workaround(const struct clk_name *clks,
                                     int nr_clks, bool enable)
@@ -49,8 +49,8 @@ void __init shmobile_clk_workaround(const struct clk_name *clks,
 #else /* CONFIG_COMMON_CLK */
 #include <linux/sh_clk.h>
 #include <linux/export.h>
-#include <mach/clock.h>
-#include <mach/common.h>
+#include "clock.h"
+#include "common.h"
 
 unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk)
 {
diff --git a/arch/arm/mach-shmobile/include/mach/clock.h b/arch/arm/mach-shmobile/clock.h
index 31b6417463e6..31b6417463e6 100644
--- a/arch/arm/mach-shmobile/include/mach/clock.h
+++ b/arch/arm/mach-shmobile/clock.h
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/common.h
index f7a360edcc35..f7a360edcc35 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/common.h
diff --git a/arch/arm/mach-shmobile/console.c b/arch/arm/mach-shmobile/console.c
index 9411a5bf4fd6..f2e79f2376e1 100644
--- a/arch/arm/mach-shmobile/console.c
+++ b/arch/arm/mach-shmobile/console.c
@@ -19,8 +19,8 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <mach/common.h>
 #include <asm/mach/map.h>
+#include "common.h"
 
 void __init shmobile_setup_console(void)
 {
diff --git a/arch/arm/mach-shmobile/include/mach/dma-register.h b/arch/arm/mach-shmobile/dma-register.h
index 97c40bd9b94f..97c40bd9b94f 100644
--- a/arch/arm/mach-shmobile/include/mach/dma-register.h
+++ b/arch/arm/mach-shmobile/dma-register.h
diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h
index d241bfd6926d..5aee83f079e2 100644
--- a/arch/arm/mach-shmobile/include/mach/irqs.h
+++ b/arch/arm/mach-shmobile/include/mach/irqs.h
@@ -1,24 +1,10 @@
 #ifndef __ASM_MACH_IRQS_H
 #define __ASM_MACH_IRQS_H
 
-#include <linux/sh_intc.h>
-
-/* GIC */
-#define gic_spi(nr)             ((nr) + 32)
-#define gic_iid(nr)             (nr) /* ICCIAR / interrupt ID */
-
-/* INTCS */
-#define INTCS_VECT_BASE         0x3400
-#define INTCS_VECT(n, vect)     INTC_VECT((n), INTCS_VECT_BASE + (vect))
-#define intcs_evt2irq(evt)      evt2irq(INTCS_VECT_BASE + (evt))
+/* Stuck here until drivers/pinctl/sh-pfc gets rid of legacy code */
 
 /* External IRQ pins */
 #define IRQPIN_BASE             2000
 #define irq_pin(nr)             ((nr) + IRQPIN_BASE)
 
-/* GPIO IRQ */
-#define _GPIO_IRQ_BASE          2500
-#define GPIO_IRQ_BASE(x)        (_GPIO_IRQ_BASE + (32 * x))
-#define GPIO_IRQ(x, y)          (_GPIO_IRQ_BASE + (32 * x) + y)
-
 #endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index 88eeceaf1088..def10a29e09a 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -2,8 +2,6 @@
 #define __ASM_R8A7779_H__
 
 #include <linux/sh_clk.h>
-#include <linux/pm_domain.h>
-#include <mach/pm-rcar.h>
 
 /* HPB-DMA slave IDs */
 enum {
@@ -12,16 +10,6 @@ enum {
         HPBDMA_SLAVE_SDHI0_RX,
 };
 
-struct r8a7779_pm_domain {
-        struct generic_pm_domain genpd;
-        struct rcar_sysc_ch ch;
-};
-
-static inline struct rcar_sysc_ch *to_r8a7779_ch(struct generic_pm_domain *d)
-{
-        return &container_of(d, struct r8a7779_pm_domain, genpd)->ch;
-}
-
 extern void r8a7779_init_delay(void);
 extern void r8a7779_init_irq_extpin(int irlm);
 extern void r8a7779_init_irq_extpin_dt(int irlm);
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
index a91caad7db7c..e2af00b1bd9d 100644
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -22,11 +22,10 @@
 #include <linux/module.h>
 #include <linux/irq.h>
 #include <linux/io.h>
-#include <linux/sh_intc.h>
-#include <mach/intc.h>
-#include <mach/irqs.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include "intc.h"
+#include "irqs.h"
 
 enum {
         UNUSED_INTCA = 0,
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c
index 19a26f4579b3..44457a94897b 100644
--- a/arch/arm/mach-shmobile/intc-sh73a0.c
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -22,15 +22,16 @@
 #include <linux/module.h>
 #include <linux/irq.h>
 #include <linux/io.h>
-#include <linux/sh_intc.h>
 #include <linux/irqchip.h>
 #include <linux/irqchip/arm-gic.h>
-#include <mach/intc.h>
-#include <mach/irqs.h>
-#include <mach/sh73a0.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include "intc.h"
+#include "irqs.h"
+#include "sh73a0.h"
+
 enum {
         UNUSED = 0,
 
diff --git a/arch/arm/mach-shmobile/include/mach/intc.h b/arch/arm/mach-shmobile/intc.h
index a5603c76cfe0..a5603c76cfe0 100644
--- a/arch/arm/mach-shmobile/include/mach/intc.h
+++ b/arch/arm/mach-shmobile/intc.h
diff --git a/arch/arm/mach-shmobile/irqs.h b/arch/arm/mach-shmobile/irqs.h
new file mode 100644
index 000000000000..4ff2d2aa94f0
--- /dev/null
+++ b/arch/arm/mach-shmobile/irqs.h
@@ -0,0 +1,21 @@
+#ifndef __SHMOBILE_IRQS_H
+#define __SHMOBILE_IRQS_H
+
+#include <linux/sh_intc.h>
+#include <mach/irqs.h>
+
+/* GIC */
+#define gic_spi(nr)             ((nr) + 32)
+#define gic_iid(nr)             (nr) /* ICCIAR / interrupt ID */
+
+/* INTCS */
+#define INTCS_VECT_BASE         0x3400
+#define INTCS_VECT(n, vect)     INTC_VECT((n), INTCS_VECT_BASE + (vect))
+#define intcs_evt2irq(evt)      evt2irq(INTCS_VECT_BASE + (evt))
+
+/* GPIO IRQ */
+#define _GPIO_IRQ_BASE          2500
+#define GPIO_IRQ_BASE(x)        (_GPIO_IRQ_BASE + (32 * x))
+#define GPIO_IRQ(x, y)          (_GPIO_IRQ_BASE + (32 * x) + y)
+
+#endif /* __SHMOBILE_IRQS_H */
diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c
index 8cb641c00fdb..fe648f5d8f06 100644
--- a/arch/arm/mach-shmobile/platsmp-apmu.c
+++ b/arch/arm/mach-shmobile/platsmp-apmu.c
@@ -16,7 +16,7 @@
 #include <asm/cacheflush.h>
 #include <asm/cp15.h>
 #include <asm/smp_plat.h>
-#include <mach/common.h>
+#include "common.h"
 
 static struct {
         void __iomem *iomem;
diff --git a/arch/arm/mach-shmobile/platsmp-scu.c b/arch/arm/mach-shmobile/platsmp-scu.c
index 673ad6e80869..64663110ab6c 100644
--- a/arch/arm/mach-shmobile/platsmp-scu.c
+++ b/arch/arm/mach-shmobile/platsmp-scu.c
@@ -15,7 +15,7 @@
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
-#include <mach/common.h>
+#include "common.h"
 
 static int shmobile_smp_scu_notifier_call(struct notifier_block *nfb,
                                           unsigned long action, void *hcpu)
diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c
index 9ebc246b8d7d..3923e09e966d 100644
--- a/arch/arm/mach-shmobile/platsmp.c
+++ b/arch/arm/mach-shmobile/platsmp.c
@@ -13,7 +13,7 @@
 #include <linux/init.h>
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
-#include <mach/common.h>
+#include "common.h"
 
 extern unsigned long shmobile_smp_fn[];
 extern unsigned long shmobile_smp_arg[];
diff --git a/arch/arm/mach-shmobile/pm-r8a7740.c b/arch/arm/mach-shmobile/pm-r8a7740.c
index 40b87aa1d448..a0d44d537fa0 100644
--- a/arch/arm/mach-shmobile/pm-r8a7740.c
+++ b/arch/arm/mach-shmobile/pm-r8a7740.c
@@ -10,8 +10,8 @@
  */
 #include <linux/console.h>
 #include <linux/suspend.h>
-#include <mach/pm-rmobile.h>
-#include <mach/common.h>
+#include "common.h"
+#include "pm-rmobile.h"
 
 #ifdef CONFIG_PM
 static int r8a7740_pd_a4s_suspend(void)
diff --git a/arch/arm/mach-shmobile/pm-r8a7779.c b/arch/arm/mach-shmobile/pm-r8a7779.c
index d6fe189b2df6..f0f36cb5ffe7 100644
--- a/arch/arm/mach-shmobile/pm-r8a7779.c
+++ b/arch/arm/mach-shmobile/pm-r8a7779.c
@@ -13,20 +13,31 @@
 #include <linux/suspend.h>
 #include <linux/err.h>
 #include <linux/pm_clock.h>
+#include <linux/pm_domain.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/irq.h>
 #include <linux/interrupt.h>
 #include <linux/console.h>
 #include <asm/io.h>
-#include <mach/common.h>
-#include <mach/pm-rcar.h>
 #include <mach/r8a7779.h>
+#include "common.h"
+#include "pm-rcar.h"
 
 /* SYSC */
 #define SYSCIER 0x0c
 #define SYSCIMR 0x10
 
+struct r8a7779_pm_domain {
+        struct generic_pm_domain genpd;
+        struct rcar_sysc_ch ch;
+};
+
+static inline struct rcar_sysc_ch *to_r8a7779_ch(struct generic_pm_domain *d)
+{
+        return &container_of(d, struct r8a7779_pm_domain, genpd)->ch;
+}
+
 #if defined(CONFIG_PM) || defined(CONFIG_SMP)
 
 static void __init r8a7779_sysc_init(void)
diff --git a/arch/arm/mach-shmobile/pm-r8a7790.c b/arch/arm/mach-shmobile/pm-r8a7790.c
index fc82839e2c2a..8845433a00b3 100644
--- a/arch/arm/mach-shmobile/pm-r8a7790.c
+++ b/arch/arm/mach-shmobile/pm-r8a7790.c
@@ -11,9 +11,11 @@
  */
 
 #include <linux/kernel.h>
+
 #include <asm/io.h>
-#include <mach/pm-rcar.h>
-#include <mach/r8a7790.h>
+
+#include "pm-rcar.h"
+#include "r8a7790.h"
 
 /* SYSC */
 #define SYSCIER 0x0c
diff --git a/arch/arm/mach-shmobile/pm-rcar.c b/arch/arm/mach-shmobile/pm-rcar.c
index 1f465a12d1b1..34b8a5674f85 100644
--- a/arch/arm/mach-shmobile/pm-rcar.c
+++ b/arch/arm/mach-shmobile/pm-rcar.c
@@ -13,7 +13,7 @@
 #include <linux/mm.h>
 #include <linux/spinlock.h>
 #include <asm/io.h>
-#include <mach/pm-rcar.h>
+#include "pm-rcar.h"
 
 /* SYSC */
 #define SYSCSR 0x00
diff --git a/arch/arm/mach-shmobile/include/mach/pm-rcar.h b/arch/arm/mach-shmobile/pm-rcar.h
index ef3a1ef628f1..ef3a1ef628f1 100644
--- a/arch/arm/mach-shmobile/include/mach/pm-rcar.h
+++ b/arch/arm/mach-shmobile/pm-rcar.h
diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c
index f710235aff2f..ebdd16e94a84 100644
--- a/arch/arm/mach-shmobile/pm-rmobile.c
+++ b/arch/arm/mach-shmobile/pm-rmobile.c
@@ -17,7 +17,7 @@
 #include <linux/pm.h>
 #include <linux/pm_clock.h>
 #include <asm/io.h>
-#include <mach/pm-rmobile.h>
+#include "pm-rmobile.h"
 
 /* SYSC */
 #define SPDCR           IOMEM(0xe6180008)
diff --git a/arch/arm/mach-shmobile/include/mach/pm-rmobile.h b/arch/arm/mach-shmobile/pm-rmobile.h
index 690553a06887..690553a06887 100644
--- a/arch/arm/mach-shmobile/include/mach/pm-rmobile.h
+++ b/arch/arm/mach-shmobile/pm-rmobile.h
diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c
index 0de75fd394b9..7e5c2676c489 100644
--- a/arch/arm/mach-shmobile/pm-sh7372.c
+++ b/arch/arm/mach-shmobile/pm-sh7372.c
@@ -21,13 +21,15 @@
 #include <linux/irq.h>
 #include <linux/bitrev.h>
 #include <linux/console.h>
+
 #include <asm/cpuidle.h>
 #include <asm/io.h>
 #include <asm/tlbflush.h>
 #include <asm/suspend.h>
-#include <mach/common.h>
-#include <mach/sh7372.h>
-#include <mach/pm-rmobile.h>
+
+#include "common.h"
+#include "pm-rmobile.h"
+#include "sh7372.h"
 
 /* DBG */
 #define DBGREG1 IOMEM(0xe6100020)
diff --git a/arch/arm/mach-shmobile/pm-sh73a0.c b/arch/arm/mach-shmobile/pm-sh73a0.c
index 99086e98fbbc..a7e466817965 100644
--- a/arch/arm/mach-shmobile/pm-sh73a0.c
+++ b/arch/arm/mach-shmobile/pm-sh73a0.c
@@ -9,7 +9,7 @@
  */
 
 #include <linux/suspend.h>
-#include <mach/common.h>
+#include "common.h"
 
 #ifdef CONFIG_SUSPEND
 static int sh73a0_enter_suspend(suspend_state_t suspend_state)
diff --git a/arch/arm/mach-shmobile/include/mach/r7s72100.h b/arch/arm/mach-shmobile/r7s72100.h
index 5f34b20ecd4a..efb723c88dd0 100644
--- a/arch/arm/mach-shmobile/include/mach/r7s72100.h
+++ b/arch/arm/mach-shmobile/r7s72100.h
@@ -3,6 +3,5 @@
 
 void r7s72100_add_dt_devices(void);
 void r7s72100_clock_init(void);
-void r7s72100_init_early(void);
 
 #endif /* __ASM_R7S72100_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/r8a73a4.h
index ce8bdd1d8a8a..ce8bdd1d8a8a 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h
+++ b/arch/arm/mach-shmobile/r8a73a4.h
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/r8a7740.h
index 5e3c9ec06303..1d1a5fd78b6b 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/r8a7740.h
@@ -19,8 +19,6 @@
 #ifndef __ASM_R8A7740_H__
 #define __ASM_R8A7740_H__
 
-#include <mach/pm-rmobile.h>
-
 /*
  * MD_CKx pin
  */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/r8a7778.h
index f4076a50e970..f4076a50e970 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h
+++ b/arch/arm/mach-shmobile/r8a7778.h
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/r8a7790.h
index 0b95babe84ba..459827f1369b 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7790.h
+++ b/arch/arm/mach-shmobile/r8a7790.h
@@ -1,8 +1,6 @@
 #ifndef __ASM_R8A7790_H__
 #define __ASM_R8A7790_H__
 
-#include <mach/rcar-gen2.h>
-
 /* DMA slave IDs */
 enum {
         RCAR_DMA_SLAVE_INVALID,
@@ -33,7 +31,6 @@ void r8a7790_add_dt_devices(void);
 void r8a7790_clock_init(void);
 void r8a7790_pinmux_init(void);
 void r8a7790_pm_init(void);
-void r8a7790_init_early(void);
 extern struct smp_operations r8a7790_smp_ops;
 
 #endif /* __ASM_R8A7790_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/rcar-gen2.h b/arch/arm/mach-shmobile/rcar-gen2.h
index 43f606eb2d82..43f606eb2d82 100644
--- a/arch/arm/mach-shmobile/include/mach/rcar-gen2.h
+++ b/arch/arm/mach-shmobile/rcar-gen2.h
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
index d953ff6e78a2..b06a9e8f59a5 100644
--- a/arch/arm/mach-shmobile/setup-emev2.c
+++ b/arch/arm/mach-shmobile/setup-emev2.c
@@ -16,14 +16,13 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
-#include <linux/clk-provider.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/of_platform.h>
-#include <mach/common.h>
+#include <linux/mm.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include "common.h"
 
 static struct map_desc emev2_io_desc[] __initdata = {
 #ifdef CONFIG_SMP
@@ -42,17 +41,6 @@ static void __init emev2_map_io(void)
         iotable_init(emev2_io_desc, ARRAY_SIZE(emev2_io_desc));
 }
 
-static void __init emev2_init_delay(void)
-{
-        shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */
-}
-
-static void __init emev2_add_standard_devices_dt(void)
-{
-        of_clk_init(NULL);
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-
 static const char *emev2_boards_compat_dt[] __initconst = {
         "renesas,emev2",
         NULL,
@@ -63,8 +51,7 @@ extern struct smp_operations emev2_smp_ops;
 DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)")
         .smp            = smp_ops(emev2_smp_ops),
         .map_io         = emev2_map_io,
-        .init_early     = emev2_init_delay,
-        .init_machine   = emev2_add_standard_devices_dt,
+        .init_early     = shmobile_init_delay,
         .init_late      = shmobile_init_late,
         .dt_compat      = emev2_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-r7s72100.c b/arch/arm/mach-shmobile/setup-r7s72100.c
index 3885a598c66b..f3b3b14ba972 100644
--- a/arch/arm/mach-shmobile/setup-r7s72100.c
+++ b/arch/arm/mach-shmobile/setup-r7s72100.c
@@ -22,11 +22,13 @@
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
 #include <linux/sh_timer.h>
-#include <mach/common.h>
-#include <mach/irqs.h>
-#include <mach/r7s72100.h>
+
 #include <asm/mach/arch.h>
 
+#include "common.h"
+#include "irqs.h"
+#include "r7s72100.h"
+
 static struct resource mtu2_resources[] __initdata = {
         DEFINE_RES_MEM(0xfcff0000, 0x400),
         DEFINE_RES_IRQ_NAMED(gic_iid(139), "tgi0a"),
@@ -43,11 +45,6 @@ void __init r7s72100_add_dt_devices(void)
         r7s72100_register_mtu2();
 }
 
-void __init r7s72100_init_early(void)
-{
-        shmobile_setup_delay(400, 1, 3); /* Cortex-A9 @ 400MHz */
-}
-
 #ifdef CONFIG_USE_OF
 static const char *r7s72100_boards_compat_dt[] __initdata = {
         "renesas,r7s72100",
@@ -55,7 +52,7 @@ static const char *r7s72100_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(R7S72100_DT, "Generic R7S72100 (Flattened Device Tree)")
-        .init_early     = r7s72100_init_early,
+        .init_early     = shmobile_init_delay,
         .dt_compat      = r7s72100_boards_compat_dt,
 MACHINE_END
 #endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
index aaaaf6e8b706..cc9823246847 100644
--- a/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -24,12 +24,14 @@
 #include <linux/serial_sci.h>
 #include <linux/sh_dma.h>
 #include <linux/sh_timer.h>
-#include <mach/common.h>
-#include <mach/dma-register.h>
-#include <mach/irqs.h>
-#include <mach/r8a73a4.h>
+
 #include <asm/mach/arch.h>
 
+#include "common.h"
+#include "dma-register.h"
+#include "irqs.h"
+#include "r8a73a4.h"
+
 static const struct resource pfc_resources[] = {
         DEFINE_RES_MEM(0xe6050000, 0x9000),
 };
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 35dec233301e..348af358a239 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -31,16 +31,18 @@
 #include <linux/sh_dma.h>
 #include <linux/sh_timer.h>
 #include <linux/platform_data/sh_ipmmu.h>
-#include <mach/dma-register.h>
-#include <mach/r8a7740.h>
-#include <mach/pm-rmobile.h>
-#include <mach/common.h>
-#include <mach/irqs.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 
+#include "common.h"
+#include "dma-register.h"
+#include "irqs.h"
+#include "pm-rmobile.h"
+#include "r8a7740.h"
+
 static struct map_desc r8a7740_io_desc[] __initdata = {
          /*
           * for CPGA/INTC/PFC
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index 5de7b33295d4..18490af0d0a0 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -37,12 +37,14 @@
 #include <linux/usb/ehci_pdriver.h>
 #include <linux/usb/ohci_pdriver.h>
 #include <linux/dma-mapping.h>
-#include <mach/irqs.h>
-#include <mach/r8a7778.h>
-#include <mach/common.h>
+
 #include <asm/mach/arch.h>
 #include <asm/hardware/cache-l2x0.h>
 
+#include "common.h"
+#include "irqs.h"
+#include "r8a7778.h"
+
 /* SCIF */
 #define R8A7778_SCIF(index, baseaddr, irq)                      \
 static struct plat_sci_port scif##index##_platform_data = {     \
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 9c79182d0568..280303cef702 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -40,14 +40,14 @@
 #include <linux/usb/ehci_pdriver.h>
 #include <linux/usb/ohci_pdriver.h>
 #include <linux/pm_runtime.h>
-#include <mach/irqs.h>
 #include <mach/r8a7779.h>
-#include <mach/common.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 #include <asm/hardware/cache-l2x0.h>
+#include "common.h"
+#include "irqs.h"
 
 static struct map_desc r8a7779_io_desc[] __initdata = {
         /* 2M entity map for 0xf0000000 (MPCORE) */
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index 10e6768968f7..240411b42424 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -26,12 +26,15 @@
 #include <linux/serial_sci.h>
 #include <linux/sh_dma.h>
 #include <linux/sh_timer.h>
-#include <mach/common.h>
-#include <mach/dma-register.h>
-#include <mach/irqs.h>
-#include <mach/r8a7790.h>
+
 #include <asm/mach/arch.h>
 
+#include "common.h"
+#include "dma-register.h"
+#include "irqs.h"
+#include "r8a7790.h"
+#include "rcar-gen2.h"
+
 /* Audio-DMAC */
 #define AUDIO_DMAC_SLAVE(_id, _addr, t, r)                      \
 {                                                               \
@@ -307,13 +310,6 @@ void __init r8a7790_add_standard_devices(void)
         r8a7790_register_audio_dmac(1);
 }
 
-void __init r8a7790_init_early(void)
-{
-#ifndef CONFIG_ARM_ARCH_TIMER
-        shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */
-#endif
-}
-
 #ifdef CONFIG_USE_OF
 
 static const char * const r8a7790_boards_compat_dt[] __initconst = {
@@ -323,7 +319,7 @@ static const char * const r8a7790_boards_compat_dt[] __initconst = {
 
 DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
         .smp            = smp_ops(r8a7790_smp_ops),
-        .init_early     = r8a7790_init_early,
+        .init_early     = shmobile_init_delay,
         .init_time      = rcar_gen2_timer_init,
         .dt_compat      = r8a7790_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-r8a7791.c b/arch/arm/mach-shmobile/setup-r8a7791.c
index fd5443715b8d..004b11a8fd88 100644
--- a/arch/arm/mach-shmobile/setup-r8a7791.c
+++ b/arch/arm/mach-shmobile/setup-r8a7791.c
@@ -26,11 +26,11 @@
 #include <linux/platform_data/irq-renesas-irqc.h>
 #include <linux/serial_sci.h>
 #include <linux/sh_timer.h>
-#include <mach/common.h>
-#include <mach/irqs.h>
 #include <mach/r8a7791.h>
-#include <mach/rcar-gen2.h>
 #include <asm/mach/arch.h>
+#include "common.h"
+#include "irqs.h"
+#include "rcar-gen2.h"
 
 static const struct resource pfc_resources[] __initconst = {
         DEFINE_RES_MEM(0xe6060000, 0x250),
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index 542c5a47173f..fdc714ebc4cd 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -22,9 +22,9 @@
 #include <linux/clocksource.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
-#include <mach/common.h>
-#include <mach/rcar-gen2.h>
 #include <asm/mach/arch.h>
+#include "common.h"
+#include "rcar-gen2.h"
 
 #define MODEMR 0xe6160060
 
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 2a8b9f2a2f54..9cdfcdfd38fc 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -29,20 +29,22 @@
 #include <linux/io.h>
 #include <linux/serial_sci.h>
 #include <linux/sh_dma.h>
-#include <linux/sh_intc.h>
 #include <linux/sh_timer.h>
 #include <linux/pm_domain.h>
 #include <linux/dma-mapping.h>
 #include <linux/platform_data/sh_ipmmu.h>
-#include <mach/dma-register.h>
-#include <mach/irqs.h>
-#include <mach/sh7372.h>
-#include <mach/common.h>
+
 #include <asm/mach/map.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 
+#include "common.h"
+#include "dma-register.h"
+#include "irqs.h"
+#include "pm-rmobile.h"
+#include "sh7372.h"
+
 static struct map_desc sh7372_io_desc[] __initdata = {
         /* create a 1:1 entity map for 0xe6xxxxxx
          * used by CPGA, INTC and PFC.
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index ad00724a2269..224882151667 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -29,19 +29,20 @@
 #include <linux/io.h>
 #include <linux/serial_sci.h>
 #include <linux/sh_dma.h>
-#include <linux/sh_intc.h>
 #include <linux/sh_timer.h>
 #include <linux/platform_data/sh_ipmmu.h>
 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
-#include <mach/dma-register.h>
-#include <mach/irqs.h>
-#include <mach/sh73a0.h>
-#include <mach/common.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 
+#include "common.h"
+#include "dma-register.h"
+#include "irqs.h"
+#include "sh73a0.h"
+
 static struct map_desc sh73a0_io_desc[] __initdata = {
         /* create a 1:1 entity map for 0xe6xxxxxx
          * used by CPGA, INTC and PFC.
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/sh7372.h
index 854a9f0ca040..4ad960d5075b 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/sh7372.h
@@ -11,10 +11,6 @@
 #ifndef __ASM_SH7372_H__
 #define __ASM_SH7372_H__
 
-#include <linux/sh_clk.h>
-#include <linux/pm_domain.h>
-#include <mach/pm-rmobile.h>
-
 /* DMA slave IDs */
 enum {
         SHDMA_SLAVE_INVALID,
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/sh73a0.h
index 359b582dc270..359b582dc270 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/sh73a0.h
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index 2dfd748da7f3..6ff1df1df9a7 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -23,9 +23,9 @@
 #include <linux/spinlock.h>
 #include <linux/io.h>
 #include <linux/delay.h>
-#include <mach/common.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
+#include "common.h"
 
 #define EMEV2_SCU_BASE 0x1e000000
 #define EMEV2_SMU_BASE 0xe0110000
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index e7a3201473d0..c230fc0c3fef 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -23,13 +23,13 @@
 #include <linux/spinlock.h>
 #include <linux/io.h>
 #include <linux/delay.h>
-#include <mach/common.h>
-#include <mach/pm-rcar.h>
 #include <mach/r8a7779.h>
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
 #include <asm/smp_twd.h>
+#include "common.h"
+#include "pm-rcar.h"
 
 #define AVECR IOMEM(0xfe700040)
 #define R8A7779_SCU_BASE 0xf0000000
diff --git a/arch/arm/mach-shmobile/smp-r8a7790.c b/arch/arm/mach-shmobile/smp-r8a7790.c
index 591052799e8f..c256fdfbb5b0 100644
--- a/arch/arm/mach-shmobile/smp-r8a7790.c
+++ b/arch/arm/mach-shmobile/smp-r8a7790.c
@@ -17,10 +17,12 @@
 #include <linux/init.h>
 #include <linux/smp.h>
 #include <linux/io.h>
+
 #include <asm/smp_plat.h>
-#include <mach/common.h>
-#include <mach/pm-rcar.h>
-#include <mach/r8a7790.h>
+
+#include "common.h"
+#include "pm-rcar.h"
+#include "r8a7790.h"
 
 #define RST             0xe6160000
 #define CA15BAR         0x0020
diff --git a/arch/arm/mach-shmobile/smp-r8a7791.c b/arch/arm/mach-shmobile/smp-r8a7791.c
index ec979529f30f..2648d68650e4 100644
--- a/arch/arm/mach-shmobile/smp-r8a7791.c
+++ b/arch/arm/mach-shmobile/smp-r8a7791.c
@@ -18,9 +18,9 @@
 #include <linux/smp.h>
 #include <linux/io.h>
 #include <asm/smp_plat.h>
-#include <mach/common.h>
 #include <mach/r8a7791.h>
-#include <mach/rcar-gen2.h>
+#include "common.h"
+#include "rcar-gen2.h"
 
 #define RST             0xe6160000
 #define CA15BAR         0x0020
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index 13ba36a6831f..22d8f87b23e9 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -22,11 +22,13 @@
 #include <linux/smp.h>
 #include <linux/io.h>
 #include <linux/delay.h>
-#include <mach/common.h>
-#include <mach/sh73a0.h>
+
 #include <asm/smp_plat.h>
 #include <asm/smp_twd.h>
 
+#include "common.h"
+#include "sh73a0.h"
+
 #define WUPCR           IOMEM(0xe6151010)
 #define SRESCR          IOMEM(0xe6151018)
 #define PSTR            IOMEM(0xe6151040)
diff --git a/arch/arm/mach-spear/spear1310.c b/arch/arm/mach-spear/spear1310.c
index 824b12a56a42..d9ce4d8000f0 100644
--- a/arch/arm/mach-spear/spear1310.c
+++ b/arch/arm/mach-spear/spear1310.c
@@ -42,7 +42,7 @@ static const char * const spear1310_dt_board_compat[] = {
  * PHYSICAL             VIRTUAL
  * 0xD8000000           0xFA000000
  */
-struct map_desc spear1310_io_desc[] __initdata = {
+static struct map_desc spear1310_io_desc[] __initdata = {
         {
                 .virtual        = VA_SPEAR1310_RAS_GRP1_BASE,
                 .pfn            = __phys_to_pfn(SPEAR1310_RAS_GRP1_BASE),
diff --git a/arch/arm/mach-spear/spear1340.c b/arch/arm/mach-spear/spear1340.c
index 7b6bff7154e1..c601799b4aea 100644
--- a/arch/arm/mach-spear/spear1340.c
+++ b/arch/arm/mach-spear/spear1340.c
@@ -93,7 +93,7 @@ static int sata_miphy_init(struct device *dev, void __iomem *addr)
         return 0;
 }
 
-void sata_miphy_exit(struct device *dev)
+static void sata_miphy_exit(struct device *dev)
 {
         writel(0, SPEAR1340_PCIE_SATA_CFG);
         writel(0, SPEAR1340_PCIE_MIPHY_CFG);
@@ -107,7 +107,7 @@ void sata_miphy_exit(struct device *dev)
         msleep(20);
 }
 
-int sata_suspend(struct device *dev)
+static int sata_suspend(struct device *dev)
 {
         if (dev->power.power_state.event == PM_EVENT_FREEZE)
                 return 0;
@@ -117,7 +117,7 @@ int sata_suspend(struct device *dev)
         return 0;
 }
 
-int sata_resume(struct device *dev)
+static int sata_resume(struct device *dev)
 {
         if (dev->power.power_state.event == PM_EVENT_THAW)
                 return 0;
diff --git a/arch/arm/mach-spear/spear13xx.c b/arch/arm/mach-spear/spear13xx.c
index c9897ea38980..8b56fe61a492 100644
--- a/arch/arm/mach-spear/spear13xx.c
+++ b/arch/arm/mach-spear/spear13xx.c
@@ -57,7 +57,7 @@ void __init spear13xx_l2x0_init(void)
  * 0xEC000000           0xFC000000
  * 0xED000000           0xFB000000
  */
-struct map_desc spear13xx_io_desc[] __initdata = {
+static struct map_desc spear13xx_io_desc[] __initdata = {
         {
                 .virtual        = (unsigned long)VA_PERIP_GRP2_BASE,
                 .pfn            = __phys_to_pfn(PERIP_GRP2_BASE),
diff --git a/arch/arm/mach-sti/platsmp.c b/arch/arm/mach-sti/platsmp.c
index fa2c33ffac04..d4b624f8dfcb 100644
--- a/arch/arm/mach-sti/platsmp.c
+++ b/arch/arm/mach-sti/platsmp.c
@@ -36,7 +36,7 @@ static void write_pen_release(int val)
 
 static DEFINE_SPINLOCK(boot_lock);
 
-void sti_secondary_init(unsigned int cpu)
+static void sti_secondary_init(unsigned int cpu)
 {
         trace_hardirqs_off();
 
@@ -53,7 +53,7 @@ void sti_secondary_init(unsigned int cpu)
         spin_unlock(&boot_lock);
 }
 
-int sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         unsigned long timeout;
 
@@ -97,7 +97,7 @@ int sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
         return pen_release != -1 ? -ENOSYS : 0;
 }
 
-void __init sti_smp_prepare_cpus(unsigned int max_cpus)
+static void __init sti_smp_prepare_cpus(unsigned int max_cpus)
 {
         void __iomem *scu_base = NULL;
         struct device_node *np = of_find_compatible_node(
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 6fbfbb77dcd9..e48a74458c25 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -2,24 +2,18 @@ asflags-y				+= -march=armv7-a
 
 obj-y                                   += io.o
 obj-y                                   += irq.o
-obj-y                                   += fuse.o
-obj-y                                   += pmc.o
 obj-y                                   += flowctrl.o
-obj-y                                   += powergate.o
-obj-y                                   += apbio.o
 obj-y                                   += pm.o
 obj-y                                   += reset.o
 obj-y                                   += reset-handler.o
 obj-y                                   += sleep.o
 obj-y                                   += tegra.o
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_speedo.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += sleep-tegra20.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += pm-tegra20.o
 ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += cpuidle-tegra20.o
 endif
-obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += tegra30_speedo.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += sleep-tegra30.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += pm-tegra30.o
 ifeq ($(CONFIG_CPU_IDLE),y)
@@ -28,7 +22,6 @@ endif
 obj-$(CONFIG_SMP)                       += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 
-obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += tegra114_speedo.o
 obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += sleep-tegra30.o
 obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += pm-tegra30.o
 ifeq ($(CONFIG_CPU_IDLE),y)
diff --git a/arch/arm/mach-tegra/apbio.c b/arch/arm/mach-tegra/apbio.c
deleted file mode 100644
index bc471973cf04..000000000000
--- a/arch/arm/mach-tegra/apbio.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
- * Copyright (C) 2010 NVIDIA Corporation.
- * Copyright (C) 2010 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/dmaengine.h>
-#include <linux/dma-mapping.h>
-#include <linux/spinlock.h>
-#include <linux/completion.h>
-#include <linux/sched.h>
-#include <linux/mutex.h>
-
-#include "apbio.h"
-#include "iomap.h"
-
-#if defined(CONFIG_TEGRA20_APB_DMA)
-static DEFINE_MUTEX(tegra_apb_dma_lock);
-static u32 *tegra_apb_bb;
-static dma_addr_t tegra_apb_bb_phys;
-static DECLARE_COMPLETION(tegra_apb_wait);
-
-static u32 tegra_apb_readl_direct(unsigned long offset);
-static void tegra_apb_writel_direct(u32 value, unsigned long offset);
-
-static struct dma_chan *tegra_apb_dma_chan;
-static struct dma_slave_config dma_sconfig;
-
-static bool tegra_apb_dma_init(void)
-{
-        dma_cap_mask_t mask;
-
-        mutex_lock(&tegra_apb_dma_lock);
-
-        /* Check to see if we raced to setup */
-        if (tegra_apb_dma_chan)
-                goto skip_init;
-
-        dma_cap_zero(mask);
-        dma_cap_set(DMA_SLAVE, mask);
-        tegra_apb_dma_chan = dma_request_channel(mask, NULL, NULL);
-        if (!tegra_apb_dma_chan) {
-                /*
-                 * This is common until the device is probed, so don't
-                 * shout about it.
-                 */
-                pr_debug("%s: can not allocate dma channel\n", __func__);
-                goto err_dma_alloc;
-        }
-
-        tegra_apb_bb = dma_alloc_coherent(NULL, sizeof(u32),
-                &tegra_apb_bb_phys, GFP_KERNEL);
-        if (!tegra_apb_bb) {
-                pr_err("%s: can not allocate bounce buffer\n", __func__);
-                goto err_buff_alloc;
-        }
-
-        dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
-        dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
-        dma_sconfig.src_maxburst = 1;
-        dma_sconfig.dst_maxburst = 1;
-
-skip_init:
-        mutex_unlock(&tegra_apb_dma_lock);
-        return true;
-
-err_buff_alloc:
-        dma_release_channel(tegra_apb_dma_chan);
-        tegra_apb_dma_chan = NULL;
-
-err_dma_alloc:
-        mutex_unlock(&tegra_apb_dma_lock);
-        return false;
-}
-
-static void apb_dma_complete(void *args)
-{
-        complete(&tegra_apb_wait);
-}
-
-static int do_dma_transfer(unsigned long apb_add,
-                enum dma_transfer_direction dir)
-{
-        struct dma_async_tx_descriptor *dma_desc;
-        int ret;
-
-        if (dir == DMA_DEV_TO_MEM)
-                dma_sconfig.src_addr = apb_add;
-        else
-                dma_sconfig.dst_addr = apb_add;
-
-        ret = dmaengine_slave_config(tegra_apb_dma_chan, &dma_sconfig);
-        if (ret)
-                return ret;
-
-        dma_desc = dmaengine_prep_slave_single(tegra_apb_dma_chan,
-                        tegra_apb_bb_phys, sizeof(u32), dir,
-                        DMA_PREP_INTERRUPT |  DMA_CTRL_ACK);
-        if (!dma_desc)
-                return -EINVAL;
-
-        dma_desc->callback = apb_dma_complete;
-        dma_desc->callback_param = NULL;
-
-        reinit_completion(&tegra_apb_wait);
-
-        dmaengine_submit(dma_desc);
-        dma_async_issue_pending(tegra_apb_dma_chan);
-        ret = wait_for_completion_timeout(&tegra_apb_wait,
-                msecs_to_jiffies(50));
-
-        if (WARN(ret == 0, "apb read dma timed out")) {
-                dmaengine_terminate_all(tegra_apb_dma_chan);
-                return -EFAULT;
-        }
-        return 0;
-}
-
-static u32 tegra_apb_readl_using_dma(unsigned long offset)
-{
-        int ret;
-
-        if (!tegra_apb_dma_chan && !tegra_apb_dma_init())
-                return tegra_apb_readl_direct(offset);
-
-        mutex_lock(&tegra_apb_dma_lock);
-        ret = do_dma_transfer(offset, DMA_DEV_TO_MEM);
-        if (ret < 0) {
-                pr_err("error in reading offset 0x%08lx using dma\n", offset);
-                *(u32 *)tegra_apb_bb = 0;
-        }
-        mutex_unlock(&tegra_apb_dma_lock);
-        return *((u32 *)tegra_apb_bb);
-}
-
-static void tegra_apb_writel_using_dma(u32 value, unsigned long offset)
-{
-        int ret;
-
-        if (!tegra_apb_dma_chan && !tegra_apb_dma_init()) {
-                tegra_apb_writel_direct(value, offset);
-                return;
-        }
-
-        mutex_lock(&tegra_apb_dma_lock);
-        *((u32 *)tegra_apb_bb) = value;
-        ret = do_dma_transfer(offset, DMA_MEM_TO_DEV);
-        if (ret < 0)
-                pr_err("error in writing offset 0x%08lx using dma\n", offset);
-        mutex_unlock(&tegra_apb_dma_lock);
-}
-#else
-#define tegra_apb_readl_using_dma tegra_apb_readl_direct
-#define tegra_apb_writel_using_dma tegra_apb_writel_direct
-#endif
-
-typedef u32 (*apbio_read_fptr)(unsigned long offset);
-typedef void (*apbio_write_fptr)(u32 value, unsigned long offset);
-
-static apbio_read_fptr apbio_read;
-static apbio_write_fptr apbio_write;
-
-static u32 tegra_apb_readl_direct(unsigned long offset)
-{
-        return readl(IO_ADDRESS(offset));
-}
-
-static void tegra_apb_writel_direct(u32 value, unsigned long offset)
-{
-        writel(value, IO_ADDRESS(offset));
-}
-
-void tegra_apb_io_init(void)
-{
-        /* Need to use dma only when it is Tegra20 based platform */
-        if (of_machine_is_compatible("nvidia,tegra20") ||
-                        !of_have_populated_dt()) {
-                apbio_read = tegra_apb_readl_using_dma;
-                apbio_write = tegra_apb_writel_using_dma;
-        } else {
-                apbio_read = tegra_apb_readl_direct;
-                apbio_write = tegra_apb_writel_direct;
-        }
-}
-
-u32 tegra_apb_readl(unsigned long offset)
-{
-        return apbio_read(offset);
-}
-
-void tegra_apb_writel(u32 value, unsigned long offset)
-{
-        apbio_write(value, offset);
-}
diff --git a/arch/arm/mach-tegra/apbio.h b/arch/arm/mach-tegra/apbio.h
deleted file mode 100644
index f05d71c303c7..000000000000
--- a/arch/arm/mach-tegra/apbio.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (C) 2010 NVIDIA Corporation.
- * Copyright (C) 2010 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_TEGRA_APBIO_H
-#define __MACH_TEGRA_APBIO_H
-
-void tegra_apb_io_init(void);
-u32 tegra_apb_readl(unsigned long offset);
-void tegra_apb_writel(u32 value, unsigned long offset);
-#endif
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index 9c6029ba526f..bb4782a32713 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -17,9 +17,10 @@
  *
  */
 
-#include <linux/platform_device.h>
 #include <linux/gpio/driver.h>
+#include <linux/platform_device.h>
 #include <linux/rfkill-gpio.h>
+
 #include "board.h"
 
 static struct rfkill_gpio_platform_data wifi_rfkill_platform_data = {
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index bcf5dbf69d58..da90c89296b9 100644
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -28,13 +28,6 @@
 void __init tegra_map_common_io(void);
 void __init tegra_init_irq(void);
 
-int __init tegra_powergate_init(void);
-#if defined(CONFIG_ARCH_TEGRA_2x_SOC) && defined(CONFIG_DEBUG_FS)
-int __init tegra_powergate_debugfs_init(void);
-#else
-static inline int tegra_powergate_debugfs_init(void) { return 0; }
-#endif
-
 void __init tegra_paz00_wifikill_init(void);
 
 #endif
diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c
index b5fb7c110c64..e3ebdce3e71f 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra114.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra114.c
@@ -14,16 +14,16 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#include <linux/kernel.h>
-#include <linux/module.h>
+#include <asm/firmware.h>
+#include <linux/clockchips.h>
 #include <linux/cpuidle.h>
 #include <linux/cpu_pm.h>
-#include <linux/clockchips.h>
-#include <asm/firmware.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
 
 #include <asm/cpuidle.h>
-#include <asm/suspend.h>
 #include <asm/smp_plat.h>
+#include <asm/suspend.h>
 
 #include "pm.h"
 #include "sleep.h"
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
index b82dcaee2ef4..b30bf5cba65b 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra20.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
@@ -19,23 +19,23 @@
  * more details.
  */
 
-#include <linux/kernel.h>
-#include <linux/module.h>
+#include <linux/clk/tegra.h>
+#include <linux/clockchips.h>
 #include <linux/cpuidle.h>
 #include <linux/cpu_pm.h>
-#include <linux/clockchips.h>
-#include <linux/clk/tegra.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
 
 #include <asm/cpuidle.h>
 #include <asm/proc-fns.h>
-#include <asm/suspend.h>
 #include <asm/smp_plat.h>
+#include <asm/suspend.h>
 
-#include "pm.h"
-#include "sleep.h"
+#include "flowctrl.h"
 #include "iomap.h"
 #include "irq.h"
-#include "flowctrl.h"
+#include "pm.h"
+#include "sleep.h"
 
 #ifdef CONFIG_PM_SLEEP
 static bool abort_flag;
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c
index ed2a2a7bae4d..35561274f6cf 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra30.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra30.c
@@ -19,17 +19,17 @@
  * more details.
  */
 
-#include <linux/kernel.h>
-#include <linux/module.h>
+#include <linux/clk/tegra.h>
+#include <linux/clockchips.h>
 #include <linux/cpuidle.h>
 #include <linux/cpu_pm.h>
-#include <linux/clockchips.h>
-#include <linux/clk/tegra.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
 
 #include <asm/cpuidle.h>
 #include <asm/proc-fns.h>
-#include <asm/suspend.h>
 #include <asm/smp_plat.h>
+#include <asm/suspend.h>
 
 #include "pm.h"
 #include "sleep.h"
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c
index 7bc5d8d667fe..316563141add 100644
--- a/arch/arm/mach-tegra/cpuidle.c
+++ b/arch/arm/mach-tegra/cpuidle.c
@@ -24,12 +24,13 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 
-#include "fuse.h"
+#include <soc/tegra/fuse.h>
+
 #include "cpuidle.h"
 
 void __init tegra_cpuidle_init(void)
 {
-        switch (tegra_chip_id) {
+        switch (tegra_get_chip_id()) {
         case TEGRA20:
                 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
                         tegra20_cpuidle_init();
@@ -49,7 +50,7 @@ void __init tegra_cpuidle_init(void)
 
 void tegra_cpuidle_pcie_irqs_in_use(void)
 {
-        switch (tegra_chip_id) {
+        switch (tegra_get_chip_id()) {
         case TEGRA20:
                 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
                         tegra20_cpuidle_pcie_irqs_in_use();
diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c
index ce8ab8abf061..ec55d1de1b55 100644
--- a/arch/arm/mach-tegra/flowctrl.c
+++ b/arch/arm/mach-tegra/flowctrl.c
@@ -18,14 +18,15 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#include <linux/cpumask.h>
 #include <linux/init.h>
-#include <linux/kernel.h>
 #include <linux/io.h>
-#include <linux/cpumask.h>
+#include <linux/kernel.h>
+
+#include <soc/tegra/fuse.h>
 
 #include "flowctrl.h"
 #include "iomap.h"
-#include "fuse.h"
 
 static u8 flowctrl_offset_halt_cpu[] = {
         FLOW_CTRL_HALT_CPU0_EVENTS,
@@ -76,7 +77,7 @@ void flowctrl_cpu_suspend_enter(unsigned int cpuid)
         int i;
 
         reg = flowctrl_read_cpu_csr(cpuid);
-        switch (tegra_chip_id) {
+        switch (tegra_get_chip_id()) {
         case TEGRA20:
                 /* clear wfe bitmap */
                 reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
@@ -117,7 +118,7 @@ void flowctrl_cpu_suspend_exit(unsigned int cpuid)
 
         /* Disable powergating via flow controller for CPU0 */
         reg = flowctrl_read_cpu_csr(cpuid);
-        switch (tegra_chip_id) {
+        switch (tegra_get_chip_id()) {
         case TEGRA20:
                 /* clear wfe bitmap */
                 reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
deleted file mode 100644
index c9ac23b385be..000000000000
--- a/arch/arm/mach-tegra/fuse.c
+++ /dev/null
@@ -1,252 +0,0 @@
-/*
- * arch/arm/mach-tegra/fuse.c
- *
- * Copyright (C) 2010 Google, Inc.
- * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
- *
- * Author:
- *      Colin Cross <ccross@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/export.h>
-#include <linux/random.h>
-#include <linux/clk.h>
-#include <linux/tegra-soc.h>
-
-#include "fuse.h"
-#include "iomap.h"
-#include "apbio.h"
-
-/* Tegra20 only */
-#define FUSE_UID_LOW            0x108
-#define FUSE_UID_HIGH           0x10c
-
-/* Tegra30 and later */
-#define FUSE_VENDOR_CODE        0x200
-#define FUSE_FAB_CODE           0x204
-#define FUSE_LOT_CODE_0         0x208
-#define FUSE_LOT_CODE_1         0x20c
-#define FUSE_WAFER_ID           0x210
-#define FUSE_X_COORDINATE       0x214
-#define FUSE_Y_COORDINATE       0x218
-
-#define FUSE_SKU_INFO           0x110
-
-#define TEGRA20_FUSE_SPARE_BIT          0x200
-#define TEGRA30_FUSE_SPARE_BIT          0x244
-
-int tegra_sku_id;
-int tegra_cpu_process_id;
-int tegra_core_process_id;
-int tegra_chip_id;
-int tegra_cpu_speedo_id;                /* only exist in Tegra30 and later */
-int tegra_soc_speedo_id;
-enum tegra_revision tegra_revision;
-
-static struct clk *fuse_clk;
-static int tegra_fuse_spare_bit;
-static void (*tegra_init_speedo_data)(void);
-
-/* The BCT to use at boot is specified by board straps that can be read
- * through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.
- */
-int tegra_bct_strapping;
-
-#define STRAP_OPT 0x008
-#define GMI_AD0 (1 << 4)
-#define GMI_AD1 (1 << 5)
-#define RAM_ID_MASK (GMI_AD0 | GMI_AD1)
-#define RAM_CODE_SHIFT 4
-
-static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
-        [TEGRA_REVISION_UNKNOWN] = "unknown",
-        [TEGRA_REVISION_A01]     = "A01",
-        [TEGRA_REVISION_A02]     = "A02",
-        [TEGRA_REVISION_A03]     = "A03",
-        [TEGRA_REVISION_A03p]    = "A03 prime",
-        [TEGRA_REVISION_A04]     = "A04",
-};
-
-static void tegra_fuse_enable_clk(void)
-{
-        if (IS_ERR(fuse_clk))
-                fuse_clk = clk_get_sys(NULL, "fuse");
-        if (IS_ERR(fuse_clk))
-                return;
-        clk_prepare_enable(fuse_clk);
-}
-
-static void tegra_fuse_disable_clk(void)
-{
-        if (IS_ERR(fuse_clk))
-                return;
-        clk_disable_unprepare(fuse_clk);
-}
-
-u32 tegra_fuse_readl(unsigned long offset)
-{
-        return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
-}
-
-bool tegra_spare_fuse(int bit)
-{
-        bool ret;
-
-        tegra_fuse_enable_clk();
-
-        ret = tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4);
-
-        tegra_fuse_disable_clk();
-
-        return ret;
-}
-
-static enum tegra_revision tegra_get_revision(u32 id)
-{
-        u32 minor_rev = (id >> 16) & 0xf;
-
-        switch (minor_rev) {
-        case 1:
-                return TEGRA_REVISION_A01;
-        case 2:
-                return TEGRA_REVISION_A02;
-        case 3:
-                if (tegra_chip_id == TEGRA20 &&
-                        (tegra_spare_fuse(18) || tegra_spare_fuse(19)))
-                        return TEGRA_REVISION_A03p;
-                else
-                        return TEGRA_REVISION_A03;
-        case 4:
-                return TEGRA_REVISION_A04;
-        default:
-                return TEGRA_REVISION_UNKNOWN;
-        }
-}
-
-static void tegra_get_process_id(void)
-{
-        u32 reg;
-
-        tegra_fuse_enable_clk();
-
-        reg = tegra_fuse_readl(tegra_fuse_spare_bit);
-        tegra_cpu_process_id = (reg >> 6) & 3;
-        reg = tegra_fuse_readl(tegra_fuse_spare_bit);
-        tegra_core_process_id = (reg >> 12) & 3;
-
-        tegra_fuse_disable_clk();
-}
-
-u32 tegra_read_chipid(void)
-{
-        return readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
-}
-
-static void __init tegra20_fuse_init_randomness(void)
-{
-        u32 randomness[2];
-
-        randomness[0] = tegra_fuse_readl(FUSE_UID_LOW);
-        randomness[1] = tegra_fuse_readl(FUSE_UID_HIGH);
-
-        add_device_randomness(randomness, sizeof(randomness));
-}
-
-/* Applies to Tegra30 or later */
-static void __init tegra30_fuse_init_randomness(void)
-{
-        u32 randomness[7];
-
-        randomness[0] = tegra_fuse_readl(FUSE_VENDOR_CODE);
-        randomness[1] = tegra_fuse_readl(FUSE_FAB_CODE);
-        randomness[2] = tegra_fuse_readl(FUSE_LOT_CODE_0);
-        randomness[3] = tegra_fuse_readl(FUSE_LOT_CODE_1);
-        randomness[4] = tegra_fuse_readl(FUSE_WAFER_ID);
-        randomness[5] = tegra_fuse_readl(FUSE_X_COORDINATE);
-        randomness[6] = tegra_fuse_readl(FUSE_Y_COORDINATE);
-
-        add_device_randomness(randomness, sizeof(randomness));
-}
-
-void __init tegra_init_fuse(void)
-{
-        u32 id;
-        u32 randomness[5];
-
-        u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
-        reg |= 1 << 28;
-        writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
-
-        /*
-         * Enable FUSE clock. This needs to be hardcoded because the clock
-         * subsystem is not active during early boot.
-         */
-        reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x14));
-        reg |= 1 << 7;
-        writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x14));
-        fuse_clk = ERR_PTR(-EINVAL);
-
-        reg = tegra_fuse_readl(FUSE_SKU_INFO);
-        randomness[0] = reg;
-        tegra_sku_id = reg & 0xFF;
-
-        reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
-        randomness[1] = reg;
-        tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
-
-        id = tegra_read_chipid();
-        randomness[2] = id;
-        tegra_chip_id = (id >> 8) & 0xff;
-
-        switch (tegra_chip_id) {
-        case TEGRA20:
-                tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
-                tegra_init_speedo_data = &tegra20_init_speedo_data;
-                break;
-        case TEGRA30:
-                tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT;
-                tegra_init_speedo_data = &tegra30_init_speedo_data;
-                break;
-        case TEGRA114:
-                tegra_init_speedo_data = &tegra114_init_speedo_data;
-                break;
-        default:
-                pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id);
-                tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
-                tegra_init_speedo_data = &tegra_get_process_id;
-        }
-
-        tegra_revision = tegra_get_revision(id);
-        tegra_init_speedo_data();
-        randomness[3] = (tegra_cpu_process_id << 16) | tegra_core_process_id;
-        randomness[4] = (tegra_cpu_speedo_id << 16) | tegra_soc_speedo_id;
-
-        add_device_randomness(randomness, sizeof(randomness));
-        switch (tegra_chip_id) {
-        case TEGRA20:
-                tegra20_fuse_init_randomness();
-                break;
-        case TEGRA30:
-        case TEGRA114:
-        default:
-                tegra30_fuse_init_randomness();
-                break;
-        }
-
-        pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
-                tegra_revision_name[tegra_revision],
-                tegra_sku_id, tegra_cpu_process_id,
-                tegra_core_process_id);
-}
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
deleted file mode 100644
index c01d04785d67..000000000000
--- a/arch/arm/mach-tegra/fuse.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Copyright (C) 2010 Google, Inc.
- * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
- *
- * Author:
- *      Colin Cross <ccross@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_TEGRA_FUSE_H
-#define __MACH_TEGRA_FUSE_H
-
-#define SKU_ID_T20      8
-#define SKU_ID_T25SE    20
-#define SKU_ID_AP25     23
-#define SKU_ID_T25      24
-#define SKU_ID_AP25E    27
-#define SKU_ID_T25E     28
-
-#define TEGRA20         0x20
-#define TEGRA30         0x30
-#define TEGRA114        0x35
-#define TEGRA124        0x40
-
-#ifndef __ASSEMBLY__
-enum tegra_revision {
-        TEGRA_REVISION_UNKNOWN = 0,
-        TEGRA_REVISION_A01,
-        TEGRA_REVISION_A02,
-        TEGRA_REVISION_A03,
-        TEGRA_REVISION_A03p,
-        TEGRA_REVISION_A04,
-        TEGRA_REVISION_MAX,
-};
-
-extern int tegra_sku_id;
-extern int tegra_cpu_process_id;
-extern int tegra_core_process_id;
-extern int tegra_chip_id;
-extern int tegra_cpu_speedo_id;         /* only exist in Tegra30 and later */
-extern int tegra_soc_speedo_id;
-extern enum tegra_revision tegra_revision;
-
-extern int tegra_bct_strapping;
-
-unsigned long long tegra_chip_uid(void);
-void tegra_init_fuse(void);
-bool tegra_spare_fuse(int bit);
-u32 tegra_fuse_readl(unsigned long offset);
-
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-void tegra20_init_speedo_data(void);
-#else
-static inline void tegra20_init_speedo_data(void) {}
-#endif
-
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
-void tegra30_init_speedo_data(void);
-#else
-static inline void tegra30_init_speedo_data(void) {}
-#endif
-
-#ifdef CONFIG_ARCH_TEGRA_114_SOC
-void tegra114_init_speedo_data(void);
-#else
-static inline void tegra114_init_speedo_data(void) {}
-#endif
-#endif /* __ASSEMBLY__ */
-
-#endif
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index ff26af26bd0c..6fc71f1534b0 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -7,13 +7,16 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+
+#include <linux/clk/tegra.h>
 #include <linux/kernel.h>
 #include <linux/smp.h>
-#include <linux/clk/tegra.h>
+
+#include <soc/tegra/common.h>
+#include <soc/tegra/fuse.h>
 
 #include <asm/smp_plat.h>
 
-#include "fuse.h"
 #include "sleep.h"
 
 static void (*tegra_hotplug_shutdown)(void);
@@ -36,6 +39,11 @@ int tegra_cpu_kill(unsigned cpu)
  */
 void __ref tegra_cpu_die(unsigned int cpu)
 {
+        if (!tegra_hotplug_shutdown) {
+                WARN(1, "hotplug is not yet initialized\n");
+                return;
+        }
+
         /* Clean L1 data cache */
         tegra_disable_clean_inv_dcache(TEGRA_FLUSH_CACHE_LOUIS);
 
@@ -46,17 +54,23 @@ void __ref tegra_cpu_die(unsigned int cpu)
         BUG();
 }
 
-void __init tegra_hotplug_init(void)
+static int __init tegra_hotplug_init(void)
 {
         if (!IS_ENABLED(CONFIG_HOTPLUG_CPU))
-                return;
+                return 0;
 
-        if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && tegra_chip_id == TEGRA20)
+        if (!soc_is_tegra())
+                return 0;
+
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && tegra_get_chip_id() == TEGRA20)
                 tegra_hotplug_shutdown = tegra20_hotplug_shutdown;
-        if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30)
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_get_chip_id() == TEGRA30)
                 tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
-        if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114)
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_get_chip_id() == TEGRA114)
                 tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
-        if (IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) && tegra_chip_id == TEGRA124)
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) && tegra_get_chip_id() == TEGRA124)
                 tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
+
+        return 0;
 }
+pure_initcall(tegra_hotplug_init);
diff --git a/arch/arm/mach-tegra/io.c b/arch/arm/mach-tegra/io.c
index bb9c9c29d181..352de159d2c5 100644
--- a/arch/arm/mach-tegra/io.c
+++ b/arch/arm/mach-tegra/io.c
@@ -18,14 +18,14 @@
  *
  */
 
-#include <linux/kernel.h>
-#include <linux/module.h>
 #include <linux/init.h>
-#include <linux/mm.h>
 #include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/module.h>
 
-#include <asm/page.h>
 #include <asm/mach/map.h>
+#include <asm/page.h>
 
 #include "board.h"
 #include "iomap.h"
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 1a74d562dca1..da7be13aecce 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -17,14 +17,14 @@
  *
  */
 
-#include <linux/kernel.h>
 #include <linux/cpu_pm.h>
 #include <linux/interrupt.h>
-#include <linux/irq.h>
 #include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
 #include <linux/irqchip/arm-gic.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/of_address.h>
+#include <linux/of.h>
 #include <linux/syscore_ops.h>
 
 #include "board.h"
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 929d1046e2b4..b45086666648 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -11,27 +11,28 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-#include <linux/init.h>
-#include <linux/errno.h>
+
+#include <linux/clk/tegra.h>
 #include <linux/delay.h>
 #include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/io.h>
 #include <linux/jiffies.h>
 #include <linux/smp.h>
-#include <linux/io.h>
-#include <linux/clk/tegra.h>
+
+#include <soc/tegra/fuse.h>
+#include <soc/tegra/pmc.h>
 
 #include <asm/cacheflush.h>
 #include <asm/mach-types.h>
-#include <asm/smp_scu.h>
 #include <asm/smp_plat.h>
-
-#include "fuse.h"
-#include "flowctrl.h"
-#include "reset.h"
-#include "pmc.h"
+#include <asm/smp_scu.h>
 
 #include "common.h"
+#include "flowctrl.h"
 #include "iomap.h"
+#include "reset.h"
 
 static cpumask_t tegra_cpu_init_mask;
 
@@ -170,13 +171,13 @@ static int tegra114_boot_secondary(unsigned int cpu, struct task_struct *idle)
 static int tegra_boot_secondary(unsigned int cpu,
                                           struct task_struct *idle)
 {
-        if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && tegra_chip_id == TEGRA20)
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && tegra_get_chip_id() == TEGRA20)
                 return tegra20_boot_secondary(cpu, idle);
-        if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30)
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_get_chip_id() == TEGRA30)
                 return tegra30_boot_secondary(cpu, idle);
-        if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114)
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_get_chip_id() == TEGRA114)
                 return tegra114_boot_secondary(cpu, idle);
-        if (IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) && tegra_chip_id == TEGRA124)
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) && tegra_get_chip_id() == TEGRA124)
                 return tegra114_boot_secondary(cpu, idle);
 
         return -EINVAL;
diff --git a/arch/arm/mach-tegra/pm-tegra20.c b/arch/arm/mach-tegra/pm-tegra20.c
index d65e1d786400..39ac2b723f2e 100644
--- a/arch/arm/mach-tegra/pm-tegra20.c
+++ b/arch/arm/mach-tegra/pm-tegra20.c
@@ -13,6 +13,7 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
+
 #include <linux/kernel.h>
 
 #include "pm.h"
diff --git a/arch/arm/mach-tegra/pm-tegra30.c b/arch/arm/mach-tegra/pm-tegra30.c
index 8fa326d6ff1a..46cc19de9916 100644
--- a/arch/arm/mach-tegra/pm-tegra30.c
+++ b/arch/arm/mach-tegra/pm-tegra30.c
@@ -13,6 +13,7 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
+
 #include <linux/kernel.h>
 
 #include "pm.h"
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index f55b05a29b55..b0f48a3946fa 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -16,30 +16,32 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#include <linux/kernel.h>
-#include <linux/spinlock.h>
-#include <linux/io.h>
+#include <linux/clk/tegra.h>
 #include <linux/cpumask.h>
-#include <linux/delay.h>
 #include <linux/cpu_pm.h>
-#include <linux/suspend.h>
+#include <linux/delay.h>
 #include <linux/err.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
 #include <linux/slab.h>
-#include <linux/clk/tegra.h>
+#include <linux/spinlock.h>
+#include <linux/suspend.h>
+
+#include <soc/tegra/fuse.h>
+#include <soc/tegra/pm.h>
+#include <soc/tegra/pmc.h>
 
-#include <asm/smp_plat.h>
 #include <asm/cacheflush.h>
-#include <asm/suspend.h>
 #include <asm/idmap.h>
 #include <asm/proc-fns.h>
+#include <asm/smp_plat.h>
+#include <asm/suspend.h>
 #include <asm/tlbflush.h>
 
-#include "iomap.h"
-#include "reset.h"
 #include "flowctrl.h"
-#include "fuse.h"
+#include "iomap.h"
 #include "pm.h"
-#include "pmc.h"
+#include "reset.h"
 #include "sleep.h"
 
 #ifdef CONFIG_PM_SLEEP
@@ -53,7 +55,7 @@ static int (*tegra_sleep_func)(unsigned long v2p);
 
 static void tegra_tear_down_cpu_init(void)
 {
-        switch (tegra_chip_id) {
+        switch (tegra_get_chip_id()) {
         case TEGRA20:
                 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
                         tegra_tear_down_cpu = tegra20_tear_down_cpu;
@@ -143,7 +145,7 @@ bool tegra_set_cpu_in_lp2(void)
 
         if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask))
                 last_cpu = true;
-        else if (tegra_chip_id == TEGRA20 && phy_cpu_id == 1)
+        else if (tegra_get_chip_id() == TEGRA20 && phy_cpu_id == 1)
                 tegra20_cpu_set_resettable_soon();
 
         spin_unlock(&tegra_lp2_lock);
@@ -166,9 +168,29 @@ static int tegra_sleep_cpu(unsigned long v2p)
         return 0;
 }
 
+static void tegra_pm_set(enum tegra_suspend_mode mode)
+{
+        u32 value;
+
+        switch (tegra_get_chip_id()) {
+        case TEGRA20:
+        case TEGRA30:
+                break;
+        default:
+                /* Turn off CRAIL */
+                value = flowctrl_read_cpu_csr(0);
+                value &= ~FLOW_CTRL_CSR_ENABLE_EXT_MASK;
+                value |= FLOW_CTRL_CSR_ENABLE_EXT_CRAIL;
+                flowctrl_write_cpu_csr(0, value);
+                break;
+        }
+
+        tegra_pmc_enter_suspend_mode(mode);
+}
+
 void tegra_idle_lp2_last(void)
 {
-        tegra_pmc_pm_set(TEGRA_SUSPEND_LP2);
+        tegra_pm_set(TEGRA_SUSPEND_LP2);
 
         cpu_cluster_pm_enter();
         suspend_cpu_complex();
@@ -212,7 +234,7 @@ static int tegra_sleep_core(unsigned long v2p)
  */
 static bool tegra_lp1_iram_hook(void)
 {
-        switch (tegra_chip_id) {
+        switch (tegra_get_chip_id()) {
         case TEGRA20:
                 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
                         tegra20_lp1_iram_hook();
@@ -242,7 +264,7 @@ static bool tegra_lp1_iram_hook(void)
 
 static bool tegra_sleep_core_init(void)
 {
-        switch (tegra_chip_id) {
+        switch (tegra_get_chip_id()) {
         case TEGRA20:
                 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
                         tegra20_sleep_core_init();
@@ -267,8 +289,6 @@ static bool tegra_sleep_core_init(void)
 
 static void tegra_suspend_enter_lp1(void)
 {
-        tegra_pmc_suspend();
-
         /* copy the reset vector & SDRAM shutdown code into IRAM */
         memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA),
                 iram_save_size);
@@ -280,8 +300,6 @@ static void tegra_suspend_enter_lp1(void)
 
 static void tegra_suspend_exit_lp1(void)
 {
-        tegra_pmc_resume();
-
         /* restore IRAM */
         memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), iram_save_addr,
                 iram_save_size);
@@ -306,7 +324,7 @@ static int tegra_suspend_enter(suspend_state_t state)
 
         pr_info("Entering suspend state %s\n", lp_state[mode]);
 
-        tegra_pmc_pm_set(mode);
+        tegra_pm_set(mode);
 
         local_fiq_disable();
 
@@ -354,7 +372,6 @@ void __init tegra_init_suspend(void)
                 return;
 
         tegra_tear_down_cpu_init();
-        tegra_pmc_suspend_init();
 
         if (mode >= TEGRA_SUSPEND_LP1) {
                 if (!tegra_lp1_iram_hook() || !tegra_sleep_core_init()) {
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h
index f4a89698e5b0..83bc87583446 100644
--- a/arch/arm/mach-tegra/pm.h
+++ b/arch/arm/mach-tegra/pm.h
@@ -21,12 +21,11 @@
 #ifndef _MACH_TEGRA_PM_H_
 #define _MACH_TEGRA_PM_H_
 
-#include "pmc.h"
-
 struct tegra_lp1_iram {
         void    *start_addr;
         void    *end_addr;
 };
+
 extern struct tegra_lp1_iram tegra_lp1_iram;
 extern void (*tegra_sleep_core_finish)(unsigned long v2p);
 
@@ -42,15 +41,8 @@ void tegra_idle_lp2_last(void);
 extern void (*tegra_tear_down_cpu)(void);
 
 #ifdef CONFIG_PM_SLEEP
-enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
-                                enum tegra_suspend_mode mode);
 void tegra_init_suspend(void);
 #else
-static inline enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
-                                enum tegra_suspend_mode mode)
-{
-        return TEGRA_SUSPEND_NONE;
-}
 static inline void tegra_init_suspend(void) {}
 #endif
 
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c
deleted file mode 100644
index 7c7123e7557b..000000000000
--- a/arch/arm/mach-tegra/pmc.c
+++ /dev/null
@@ -1,413 +0,0 @@
-/*
- * Copyright (C) 2012,2013 NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/tegra-powergate.h>
-
-#include "flowctrl.h"
-#include "fuse.h"
-#include "pm.h"
-#include "pmc.h"
-#include "sleep.h"
-
-#define TEGRA_POWER_SYSCLK_POLARITY     (1 << 10)  /* sys clk polarity */
-#define TEGRA_POWER_SYSCLK_OE           (1 << 11)  /* system clock enable */
-#define TEGRA_POWER_EFFECT_LP0          (1 << 14)  /* LP0 when CPU pwr gated */
-#define TEGRA_POWER_CPU_PWRREQ_POLARITY (1 << 15)  /* CPU pwr req polarity */
-#define TEGRA_POWER_CPU_PWRREQ_OE       (1 << 16)  /* CPU pwr req enable */
-
-#define PMC_CTRL                        0x0
-#define PMC_CTRL_INTR_LOW               (1 << 17)
-#define PMC_PWRGATE_TOGGLE              0x30
-#define PMC_PWRGATE_TOGGLE_START        (1 << 8)
-#define PMC_REMOVE_CLAMPING             0x34
-#define PMC_PWRGATE_STATUS              0x38
-
-#define PMC_SCRATCH0                    0x50
-#define PMC_SCRATCH0_MODE_RECOVERY      (1 << 31)
-#define PMC_SCRATCH0_MODE_BOOTLOADER    (1 << 30)
-#define PMC_SCRATCH0_MODE_RCM           (1 << 1)
-#define PMC_SCRATCH0_MODE_MASK          (PMC_SCRATCH0_MODE_RECOVERY | \
-                                         PMC_SCRATCH0_MODE_BOOTLOADER | \
-                                         PMC_SCRATCH0_MODE_RCM)
-
-#define PMC_CPUPWRGOOD_TIMER    0xc8
-#define PMC_CPUPWROFF_TIMER     0xcc
-
-static u8 tegra_cpu_domains[] = {
-        0xFF,                   /* not available for CPU0 */
-        TEGRA_POWERGATE_CPU1,
-        TEGRA_POWERGATE_CPU2,
-        TEGRA_POWERGATE_CPU3,
-};
-static DEFINE_SPINLOCK(tegra_powergate_lock);
-
-static void __iomem *tegra_pmc_base;
-static bool tegra_pmc_invert_interrupt;
-static struct clk *tegra_pclk;
-
-struct pmc_pm_data {
-        u32 cpu_good_time;      /* CPU power good time in uS */
-        u32 cpu_off_time;       /* CPU power off time in uS */
-        u32 core_osc_time;      /* Core power good osc time in uS */
-        u32 core_pmu_time;      /* Core power good pmu time in uS */
-        u32 core_off_time;      /* Core power off time in uS */
-        bool corereq_high;      /* Core power request active-high */
-        bool sysclkreq_high;    /* System clock request active-high */
-        bool combined_req;      /* Combined pwr req for CPU & Core */
-        bool cpu_pwr_good_en;   /* CPU power good signal is enabled */
-        u32 lp0_vec_phy_addr;   /* The phy addr of LP0 warm boot code */
-        u32 lp0_vec_size;       /* The size of LP0 warm boot code */
-        enum tegra_suspend_mode suspend_mode;
-};
-static struct pmc_pm_data pmc_pm_data;
-
-static inline u32 tegra_pmc_readl(u32 reg)
-{
-        return readl(tegra_pmc_base + reg);
-}
-
-static inline void tegra_pmc_writel(u32 val, u32 reg)
-{
-        writel(val, tegra_pmc_base + reg);
-}
-
-static int tegra_pmc_get_cpu_powerdomain_id(int cpuid)
-{
-        if (cpuid <= 0 || cpuid >= num_possible_cpus())
-                return -EINVAL;
-        return tegra_cpu_domains[cpuid];
-}
-
-static bool tegra_pmc_powergate_is_powered(int id)
-{
-        return (tegra_pmc_readl(PMC_PWRGATE_STATUS) >> id) & 1;
-}
-
-static int tegra_pmc_powergate_set(int id, bool new_state)
-{
-        bool old_state;
-        unsigned long flags;
-
-        spin_lock_irqsave(&tegra_powergate_lock, flags);
-
-        old_state = tegra_pmc_powergate_is_powered(id);
-        WARN_ON(old_state == new_state);
-
-        tegra_pmc_writel(PMC_PWRGATE_TOGGLE_START | id, PMC_PWRGATE_TOGGLE);
-
-        spin_unlock_irqrestore(&tegra_powergate_lock, flags);
-
-        return 0;
-}
-
-static int tegra_pmc_powergate_remove_clamping(int id)
-{
-        u32 mask;
-
-        /*
-         * Tegra has a bug where PCIE and VDE clamping masks are
-         * swapped relatively to the partition ids.
-         */
-        if (id ==  TEGRA_POWERGATE_VDEC)
-                mask = (1 << TEGRA_POWERGATE_PCIE);
-        else if (id == TEGRA_POWERGATE_PCIE)
-                mask = (1 << TEGRA_POWERGATE_VDEC);
-        else
-                mask = (1 << id);
-
-        tegra_pmc_writel(mask, PMC_REMOVE_CLAMPING);
-
-        return 0;
-}
-
-bool tegra_pmc_cpu_is_powered(int cpuid)
-{
-        int id;
-
-        id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
-        if (id < 0)
-                return false;
-        return tegra_pmc_powergate_is_powered(id);
-}
-
-int tegra_pmc_cpu_power_on(int cpuid)
-{
-        int id;
-
-        id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
-        if (id < 0)
-                return id;
-        return tegra_pmc_powergate_set(id, true);
-}
-
-int tegra_pmc_cpu_remove_clamping(int cpuid)
-{
-        int id;
-
-        id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
-        if (id < 0)
-                return id;
-        return tegra_pmc_powergate_remove_clamping(id);
-}
-
-void tegra_pmc_restart(enum reboot_mode mode, const char *cmd)
-{
-        u32 val;
-
-        val = tegra_pmc_readl(PMC_SCRATCH0);
-        val &= ~PMC_SCRATCH0_MODE_MASK;
-
-        if (cmd) {
-                if (strcmp(cmd, "recovery") == 0)
-                        val |= PMC_SCRATCH0_MODE_RECOVERY;
-
-                if (strcmp(cmd, "bootloader") == 0)
-                        val |= PMC_SCRATCH0_MODE_BOOTLOADER;
-
-                if (strcmp(cmd, "forced-recovery") == 0)
-                        val |= PMC_SCRATCH0_MODE_RCM;
-        }
-
-        tegra_pmc_writel(val, PMC_SCRATCH0);
-
-        val = tegra_pmc_readl(0);
-        val |= 0x10;
-        tegra_pmc_writel(val, 0);
-}
-
-#ifdef CONFIG_PM_SLEEP
-static void set_power_timers(u32 us_on, u32 us_off, unsigned long rate)
-{
-        unsigned long long ticks;
-        unsigned long long pclk;
-        static unsigned long tegra_last_pclk;
-
-        if (WARN_ON_ONCE(rate <= 0))
-                pclk = 100000000;
-        else
-                pclk = rate;
-
-        if ((rate != tegra_last_pclk)) {
-                ticks = (us_on * pclk) + 999999ull;
-                do_div(ticks, 1000000);
-                tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWRGOOD_TIMER);
-
-                ticks = (us_off * pclk) + 999999ull;
-                do_div(ticks, 1000000);
-                tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWROFF_TIMER);
-                wmb();
-        }
-        tegra_last_pclk = pclk;
-}
-
-enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
-{
-        return pmc_pm_data.suspend_mode;
-}
-
-void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
-{
-        if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
-                return;
-
-        pmc_pm_data.suspend_mode = mode;
-}
-
-void tegra_pmc_suspend(void)
-{
-        tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41);
-}
-
-void tegra_pmc_resume(void)
-{
-        tegra_pmc_writel(0x0, PMC_SCRATCH41);
-}
-
-void tegra_pmc_pm_set(enum tegra_suspend_mode mode)
-{
-        u32 reg, csr_reg;
-        unsigned long rate = 0;
-
-        reg = tegra_pmc_readl(PMC_CTRL);
-        reg |= TEGRA_POWER_CPU_PWRREQ_OE;
-        reg &= ~TEGRA_POWER_EFFECT_LP0;
-
-        switch (tegra_chip_id) {
-        case TEGRA20:
-        case TEGRA30:
-                break;
-        default:
-                /* Turn off CRAIL */
-                csr_reg = flowctrl_read_cpu_csr(0);
-                csr_reg &= ~FLOW_CTRL_CSR_ENABLE_EXT_MASK;
-                csr_reg |= FLOW_CTRL_CSR_ENABLE_EXT_CRAIL;
-                flowctrl_write_cpu_csr(0, csr_reg);
-                break;
-        }
-
-        switch (mode) {
-        case TEGRA_SUSPEND_LP1:
-                rate = 32768;
-                break;
-        case TEGRA_SUSPEND_LP2:
-                rate = clk_get_rate(tegra_pclk);
-                break;
-        default:
-                break;
-        }
-
-        set_power_timers(pmc_pm_data.cpu_good_time, pmc_pm_data.cpu_off_time,
-                         rate);
-
-        tegra_pmc_writel(reg, PMC_CTRL);
-}
-
-void tegra_pmc_suspend_init(void)
-{
-        u32 reg;
-
-        /* Always enable CPU power request */
-        reg = tegra_pmc_readl(PMC_CTRL);
-        reg |= TEGRA_POWER_CPU_PWRREQ_OE;
-        tegra_pmc_writel(reg, PMC_CTRL);
-
-        reg = tegra_pmc_readl(PMC_CTRL);
-
-        if (!pmc_pm_data.sysclkreq_high)
-                reg |= TEGRA_POWER_SYSCLK_POLARITY;
-        else
-                reg &= ~TEGRA_POWER_SYSCLK_POLARITY;
-
-        /* configure the output polarity while the request is tristated */
-        tegra_pmc_writel(reg, PMC_CTRL);
-
-        /* now enable the request */
-        reg |= TEGRA_POWER_SYSCLK_OE;
-        tegra_pmc_writel(reg, PMC_CTRL);
-}
-#endif
-
-static const struct of_device_id matches[] __initconst = {
-        { .compatible = "nvidia,tegra124-pmc" },
-        { .compatible = "nvidia,tegra114-pmc" },
-        { .compatible = "nvidia,tegra30-pmc" },
-        { .compatible = "nvidia,tegra20-pmc" },
-        { }
-};
-
-void __init tegra_pmc_init_irq(void)
-{
-        struct device_node *np;
-        u32 val;
-
-        np = of_find_matching_node(NULL, matches);
-        BUG_ON(!np);
-
-        tegra_pmc_base = of_iomap(np, 0);
-
-        tegra_pmc_invert_interrupt = of_property_read_bool(np,
-                                     "nvidia,invert-interrupt");
-
-        val = tegra_pmc_readl(PMC_CTRL);
-        if (tegra_pmc_invert_interrupt)
-                val |= PMC_CTRL_INTR_LOW;
-        else
-                val &= ~PMC_CTRL_INTR_LOW;
-        tegra_pmc_writel(val, PMC_CTRL);
-}
-
-void __init tegra_pmc_init(void)
-{
-        struct device_node *np;
-        u32 prop;
-        enum tegra_suspend_mode suspend_mode;
-        u32 core_good_time[2] = {0, 0};
-        u32 lp0_vec[2] = {0, 0};
-
-        np = of_find_matching_node(NULL, matches);
-        BUG_ON(!np);
-
-        tegra_pclk = of_clk_get_by_name(np, "pclk");
-        WARN_ON(IS_ERR(tegra_pclk));
-
-        /* Grabbing the power management configurations */
-        if (of_property_read_u32(np, "nvidia,suspend-mode", &prop)) {
-                suspend_mode = TEGRA_SUSPEND_NONE;
-        } else {
-                switch (prop) {
-                case 0:
-                        suspend_mode = TEGRA_SUSPEND_LP0;
-                        break;
-                case 1:
-                        suspend_mode = TEGRA_SUSPEND_LP1;
-                        break;
-                case 2:
-                        suspend_mode = TEGRA_SUSPEND_LP2;
-                        break;
-                default:
-                        suspend_mode = TEGRA_SUSPEND_NONE;
-                        break;
-                }
-        }
-        suspend_mode = tegra_pm_validate_suspend_mode(suspend_mode);
-
-        if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &prop))
-                suspend_mode = TEGRA_SUSPEND_NONE;
-        pmc_pm_data.cpu_good_time = prop;
-
-        if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &prop))
-                suspend_mode = TEGRA_SUSPEND_NONE;
-        pmc_pm_data.cpu_off_time = prop;
-
-        if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
-                        core_good_time, ARRAY_SIZE(core_good_time)))
-                suspend_mode = TEGRA_SUSPEND_NONE;
-        pmc_pm_data.core_osc_time = core_good_time[0];
-        pmc_pm_data.core_pmu_time = core_good_time[1];
-
-        if (of_property_read_u32(np, "nvidia,core-pwr-off-time",
-                                 &prop))
-                suspend_mode = TEGRA_SUSPEND_NONE;
-        pmc_pm_data.core_off_time = prop;
-
-        pmc_pm_data.corereq_high = of_property_read_bool(np,
-                                "nvidia,core-power-req-active-high");
-
-        pmc_pm_data.sysclkreq_high = of_property_read_bool(np,
-                                "nvidia,sys-clock-req-active-high");
-
-        pmc_pm_data.combined_req = of_property_read_bool(np,
-                                "nvidia,combined-power-req");
-
-        pmc_pm_data.cpu_pwr_good_en = of_property_read_bool(np,
-                                "nvidia,cpu-pwr-good-en");
-
-        if (of_property_read_u32_array(np, "nvidia,lp0-vec", lp0_vec,
-                                       ARRAY_SIZE(lp0_vec)))
-                if (suspend_mode == TEGRA_SUSPEND_LP0)
-                        suspend_mode = TEGRA_SUSPEND_LP1;
-
-        pmc_pm_data.lp0_vec_phy_addr = lp0_vec[0];
-        pmc_pm_data.lp0_vec_size = lp0_vec[1];
-
-        pmc_pm_data.suspend_mode = suspend_mode;
-}
diff --git a/arch/arm/mach-tegra/pmc.h b/arch/arm/mach-tegra/pmc.h
deleted file mode 100644
index 59e19c344298..000000000000
--- a/arch/arm/mach-tegra/pmc.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- *
- */
-
-#ifndef __MACH_TEGRA_PMC_H
-#define __MACH_TEGRA_PMC_H
-
-#include <linux/reboot.h>
-
-enum tegra_suspend_mode {
-        TEGRA_SUSPEND_NONE = 0,
-        TEGRA_SUSPEND_LP2,      /* CPU voltage off */
-        TEGRA_SUSPEND_LP1,      /* CPU voltage off, DRAM self-refresh */
-        TEGRA_SUSPEND_LP0,      /* CPU + core voltage off, DRAM self-refresh */
-        TEGRA_MAX_SUSPEND_MODE,
-};
-
-#ifdef CONFIG_PM_SLEEP
-enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
-void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode);
-void tegra_pmc_suspend(void);
-void tegra_pmc_resume(void);
-void tegra_pmc_pm_set(enum tegra_suspend_mode mode);
-void tegra_pmc_suspend_init(void);
-#endif
-
-bool tegra_pmc_cpu_is_powered(int cpuid);
-int tegra_pmc_cpu_power_on(int cpuid);
-int tegra_pmc_cpu_remove_clamping(int cpuid);
-
-void tegra_pmc_restart(enum reboot_mode mode, const char *cmd);
-
-void tegra_pmc_init_irq(void);
-void tegra_pmc_init(void);
-
-#endif
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
deleted file mode 100644
index 4cefc5cd6bed..000000000000
--- a/arch/arm/mach-tegra/powergate.c
+++ /dev/null
@@ -1,515 +0,0 @@
-/*
- * drivers/powergate/tegra-powergate.c
- *
- * Copyright (c) 2010 Google, Inc
- *
- * Author:
- *      Colin Cross <ccross@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/clk.h>
-#include <linux/debugfs.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/export.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/reset.h>
-#include <linux/seq_file.h>
-#include <linux/spinlock.h>
-#include <linux/clk/tegra.h>
-#include <linux/tegra-powergate.h>
-
-#include "fuse.h"
-#include "iomap.h"
-
-#define DPD_SAMPLE              0x020
-#define  DPD_SAMPLE_ENABLE      (1 << 0)
-#define  DPD_SAMPLE_DISABLE     (0 << 0)
-
-#define PWRGATE_TOGGLE          0x30
-#define  PWRGATE_TOGGLE_START   (1 << 8)
-
-#define REMOVE_CLAMPING         0x34
-
-#define PWRGATE_STATUS          0x38
-
-#define IO_DPD_REQ              0x1b8
-#define  IO_DPD_REQ_CODE_IDLE   (0 << 30)
-#define  IO_DPD_REQ_CODE_OFF    (1 << 30)
-#define  IO_DPD_REQ_CODE_ON     (2 << 30)
-#define  IO_DPD_REQ_CODE_MASK   (3 << 30)
-
-#define IO_DPD_STATUS           0x1bc
-#define IO_DPD2_REQ             0x1c0
-#define IO_DPD2_STATUS          0x1c4
-#define SEL_DPD_TIM             0x1c8
-
-#define GPU_RG_CNTRL            0x2d4
-
-static int tegra_num_powerdomains;
-static int tegra_num_cpu_domains;
-static const u8 *tegra_cpu_domains;
-
-static const u8 tegra30_cpu_domains[] = {
-        TEGRA_POWERGATE_CPU,
-        TEGRA_POWERGATE_CPU1,
-        TEGRA_POWERGATE_CPU2,
-        TEGRA_POWERGATE_CPU3,
-};
-
-static const u8 tegra114_cpu_domains[] = {
-        TEGRA_POWERGATE_CPU0,
-        TEGRA_POWERGATE_CPU1,
-        TEGRA_POWERGATE_CPU2,
-        TEGRA_POWERGATE_CPU3,
-};
-
-static const u8 tegra124_cpu_domains[] = {
-        TEGRA_POWERGATE_CPU0,
-        TEGRA_POWERGATE_CPU1,
-        TEGRA_POWERGATE_CPU2,
-        TEGRA_POWERGATE_CPU3,
-};
-
-static DEFINE_SPINLOCK(tegra_powergate_lock);
-
-static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
-
-static u32 pmc_read(unsigned long reg)
-{
-        return readl(pmc + reg);
-}
-
-static void pmc_write(u32 val, unsigned long reg)
-{
-        writel(val, pmc + reg);
-}
-
-static int tegra_powergate_set(int id, bool new_state)
-{
-        bool status;
-        unsigned long flags;
-
-        spin_lock_irqsave(&tegra_powergate_lock, flags);
-
-        status = pmc_read(PWRGATE_STATUS) & (1 << id);
-
-        if (status == new_state) {
-                spin_unlock_irqrestore(&tegra_powergate_lock, flags);
-                return 0;
-        }
-
-        pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
-
-        spin_unlock_irqrestore(&tegra_powergate_lock, flags);
-
-        return 0;
-}
-
-int tegra_powergate_power_on(int id)
-{
-        if (id < 0 || id >= tegra_num_powerdomains)
-                return -EINVAL;
-
-        return tegra_powergate_set(id, true);
-}
-
-int tegra_powergate_power_off(int id)
-{
-        if (id < 0 || id >= tegra_num_powerdomains)
-                return -EINVAL;
-
-        return tegra_powergate_set(id, false);
-}
-EXPORT_SYMBOL(tegra_powergate_power_off);
-
-int tegra_powergate_is_powered(int id)
-{
-        u32 status;
-
-        if (id < 0 || id >= tegra_num_powerdomains)
-                return -EINVAL;
-
-        status = pmc_read(PWRGATE_STATUS) & (1 << id);
-        return !!status;
-}
-
-int tegra_powergate_remove_clamping(int id)
-{
-        u32 mask;
-
-        if (id < 0 || id >= tegra_num_powerdomains)
-                return -EINVAL;
-
-        /*
-         * The Tegra124 GPU has a separate register (with different semantics)
-         * to remove clamps.
-         */
-        if (tegra_chip_id == TEGRA124) {
-                if (id == TEGRA_POWERGATE_3D) {
-                        pmc_write(0, GPU_RG_CNTRL);
-                        return 0;
-                }
-        }
-
-        /*
-         * Tegra 2 has a bug where PCIE and VDE clamping masks are
-         * swapped relatively to the partition ids
-         */
-        if (id == TEGRA_POWERGATE_VDEC)
-                mask = (1 << TEGRA_POWERGATE_PCIE);
-        else if (id == TEGRA_POWERGATE_PCIE)
-                mask = (1 << TEGRA_POWERGATE_VDEC);
-        else
-                mask = (1 << id);
-
-        pmc_write(mask, REMOVE_CLAMPING);
-
-        return 0;
-}
-EXPORT_SYMBOL(tegra_powergate_remove_clamping);
-
-/* Must be called with clk disabled, and returns with clk enabled */
-int tegra_powergate_sequence_power_up(int id, struct clk *clk,
-                                        struct reset_control *rst)
-{
-        int ret;
-
-        reset_control_assert(rst);
-
-        ret = tegra_powergate_power_on(id);
-        if (ret)
-                goto err_power;
-
-        ret = clk_prepare_enable(clk);
-        if (ret)
-                goto err_clk;
-
-        udelay(10);
-
-        ret = tegra_powergate_remove_clamping(id);
-        if (ret)
-                goto err_clamp;
-
-        udelay(10);
-        reset_control_deassert(rst);
-
-        return 0;
-
-err_clamp:
-        clk_disable_unprepare(clk);
-err_clk:
-        tegra_powergate_power_off(id);
-err_power:
-        return ret;
-}
-EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
-
-int tegra_cpu_powergate_id(int cpuid)
-{
-        if (cpuid > 0 && cpuid < tegra_num_cpu_domains)
-                return tegra_cpu_domains[cpuid];
-
-        return -EINVAL;
-}
-
-int __init tegra_powergate_init(void)
-{
-        switch (tegra_chip_id) {
-        case TEGRA20:
-                tegra_num_powerdomains = 7;
-                break;
-        case TEGRA30:
-                tegra_num_powerdomains = 14;
-                tegra_num_cpu_domains = 4;
-                tegra_cpu_domains = tegra30_cpu_domains;
-                break;
-        case TEGRA114:
-                tegra_num_powerdomains = 23;
-                tegra_num_cpu_domains = 4;
-                tegra_cpu_domains = tegra114_cpu_domains;
-                break;
-        case TEGRA124:
-                tegra_num_powerdomains = 25;
-                tegra_num_cpu_domains = 4;
-                tegra_cpu_domains = tegra124_cpu_domains;
-                break;
-        default:
-                /* Unknown Tegra variant. Disable powergating */
-                tegra_num_powerdomains = 0;
-                break;
-        }
-
-        return 0;
-}
-
-#ifdef CONFIG_DEBUG_FS
-
-static const char * const *powergate_name;
-
-static const char * const powergate_name_t20[] = {
-        [TEGRA_POWERGATE_CPU]   = "cpu",
-        [TEGRA_POWERGATE_3D]    = "3d",
-        [TEGRA_POWERGATE_VENC]  = "venc",
-        [TEGRA_POWERGATE_VDEC]  = "vdec",
-        [TEGRA_POWERGATE_PCIE]  = "pcie",
-        [TEGRA_POWERGATE_L2]    = "l2",
-        [TEGRA_POWERGATE_MPE]   = "mpe",
-};
-
-static const char * const powergate_name_t30[] = {
-        [TEGRA_POWERGATE_CPU]   = "cpu0",
-        [TEGRA_POWERGATE_3D]    = "3d0",
-        [TEGRA_POWERGATE_VENC]  = "venc",
-        [TEGRA_POWERGATE_VDEC]  = "vdec",
-        [TEGRA_POWERGATE_PCIE]  = "pcie",
-        [TEGRA_POWERGATE_L2]    = "l2",
-        [TEGRA_POWERGATE_MPE]   = "mpe",
-        [TEGRA_POWERGATE_HEG]   = "heg",
-        [TEGRA_POWERGATE_SATA]  = "sata",
-        [TEGRA_POWERGATE_CPU1]  = "cpu1",
-        [TEGRA_POWERGATE_CPU2]  = "cpu2",
-        [TEGRA_POWERGATE_CPU3]  = "cpu3",
-        [TEGRA_POWERGATE_CELP]  = "celp",
-        [TEGRA_POWERGATE_3D1]   = "3d1",
-};
-
-static const char * const powergate_name_t114[] = {
-        [TEGRA_POWERGATE_CPU]   = "crail",
-        [TEGRA_POWERGATE_3D]    = "3d",
-        [TEGRA_POWERGATE_VENC]  = "venc",
-        [TEGRA_POWERGATE_VDEC]  = "vdec",
-        [TEGRA_POWERGATE_MPE]   = "mpe",
-        [TEGRA_POWERGATE_HEG]   = "heg",
-        [TEGRA_POWERGATE_CPU1]  = "cpu1",
-        [TEGRA_POWERGATE_CPU2]  = "cpu2",
-        [TEGRA_POWERGATE_CPU3]  = "cpu3",
-        [TEGRA_POWERGATE_CELP]  = "celp",
-        [TEGRA_POWERGATE_CPU0]  = "cpu0",
-        [TEGRA_POWERGATE_C0NC]  = "c0nc",
-        [TEGRA_POWERGATE_C1NC]  = "c1nc",
-        [TEGRA_POWERGATE_DIS]   = "dis",
-        [TEGRA_POWERGATE_DISB]  = "disb",
-        [TEGRA_POWERGATE_XUSBA] = "xusba",
-        [TEGRA_POWERGATE_XUSBB] = "xusbb",
-        [TEGRA_POWERGATE_XUSBC] = "xusbc",
-};
-
-static const char * const powergate_name_t124[] = {
-        [TEGRA_POWERGATE_CPU]   = "crail",
-        [TEGRA_POWERGATE_3D]    = "3d",
-        [TEGRA_POWERGATE_VENC]  = "venc",
-        [TEGRA_POWERGATE_PCIE]  = "pcie",
-        [TEGRA_POWERGATE_VDEC]  = "vdec",
-        [TEGRA_POWERGATE_L2]    = "l2",
-        [TEGRA_POWERGATE_MPE]   = "mpe",
-        [TEGRA_POWERGATE_HEG]   = "heg",
-        [TEGRA_POWERGATE_SATA]  = "sata",
-        [TEGRA_POWERGATE_CPU1]  = "cpu1",
-        [TEGRA_POWERGATE_CPU2]  = "cpu2",
-        [TEGRA_POWERGATE_CPU3]  = "cpu3",
-        [TEGRA_POWERGATE_CELP]  = "celp",
-        [TEGRA_POWERGATE_CPU0]  = "cpu0",
-        [TEGRA_POWERGATE_C0NC]  = "c0nc",
-        [TEGRA_POWERGATE_C1NC]  = "c1nc",
-        [TEGRA_POWERGATE_SOR]   = "sor",
-        [TEGRA_POWERGATE_DIS]   = "dis",
-        [TEGRA_POWERGATE_DISB]  = "disb",
-        [TEGRA_POWERGATE_XUSBA] = "xusba",
-        [TEGRA_POWERGATE_XUSBB] = "xusbb",
-        [TEGRA_POWERGATE_XUSBC] = "xusbc",
-        [TEGRA_POWERGATE_VIC]   = "vic",
-        [TEGRA_POWERGATE_IRAM]  = "iram",
-};
-
-static int powergate_show(struct seq_file *s, void *data)
-{
-        int i;
-
-        seq_printf(s, " powergate powered\n");
-        seq_printf(s, "------------------\n");
-
-        for (i = 0; i < tegra_num_powerdomains; i++) {
-                if (!powergate_name[i])
-                        continue;
-
-                seq_printf(s, " %9s %7s\n", powergate_name[i],
-                        tegra_powergate_is_powered(i) ? "yes" : "no");
-        }
-
-        return 0;
-}
-
-static int powergate_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, powergate_show, inode->i_private);
-}
-
-static const struct file_operations powergate_fops = {
-        .open           = powergate_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-};
-
-int __init tegra_powergate_debugfs_init(void)
-{
-        struct dentry *d;
-
-        switch (tegra_chip_id) {
-        case TEGRA20:
-                powergate_name = powergate_name_t20;
-                break;
-        case TEGRA30:
-                powergate_name = powergate_name_t30;
-                break;
-        case TEGRA114:
-                powergate_name = powergate_name_t114;
-                break;
-        case TEGRA124:
-                powergate_name = powergate_name_t124;
-                break;
-        }
-
-        if (powergate_name) {
-                d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
-                        &powergate_fops);
-                if (!d)
-                        return -ENOMEM;
-        }
-
-        return 0;
-}
-
-#endif
-
-static int tegra_io_rail_prepare(int id, unsigned long *request,
-                                 unsigned long *status, unsigned int *bit)
-{
-        unsigned long rate, value;
-        struct clk *clk;
-
-        *bit = id % 32;
-
-        /*
-         * There are two sets of 30 bits to select IO rails, but bits 30 and
-         * 31 are control bits rather than IO rail selection bits.
-         */
-        if (id > 63 || *bit == 30 || *bit == 31)
-                return -EINVAL;
-
-        if (id < 32) {
-                *status = IO_DPD_STATUS;
-                *request = IO_DPD_REQ;
-        } else {
-                *status = IO_DPD2_STATUS;
-                *request = IO_DPD2_REQ;
-        }
-
-        clk = clk_get_sys(NULL, "pclk");
-        if (IS_ERR(clk))
-                return PTR_ERR(clk);
-
-        rate = clk_get_rate(clk);
-        clk_put(clk);
-
-        pmc_write(DPD_SAMPLE_ENABLE, DPD_SAMPLE);
-
-        /* must be at least 200 ns, in APB (PCLK) clock cycles */
-        value = DIV_ROUND_UP(1000000000, rate);
-        value = DIV_ROUND_UP(200, value);
-        pmc_write(value, SEL_DPD_TIM);
-
-        return 0;
-}
-
-static int tegra_io_rail_poll(unsigned long offset, unsigned long mask,
-                              unsigned long val, unsigned long timeout)
-{
-        unsigned long value;
-
-        timeout = jiffies + msecs_to_jiffies(timeout);
-
-        while (time_after(timeout, jiffies)) {
-                value = pmc_read(offset);
-                if ((value & mask) == val)
-                        return 0;
-
-                usleep_range(250, 1000);
-        }
-
-        return -ETIMEDOUT;
-}
-
-static void tegra_io_rail_unprepare(void)
-{
-        pmc_write(DPD_SAMPLE_DISABLE, DPD_SAMPLE);
-}
-
-int tegra_io_rail_power_on(int id)
-{
-        unsigned long request, status, value;
-        unsigned int bit, mask;
-        int err;
-
-        err = tegra_io_rail_prepare(id, &request, &status, &bit);
-        if (err < 0)
-                return err;
-
-        mask = 1 << bit;
-
-        value = pmc_read(request);
-        value |= mask;
-        value &= ~IO_DPD_REQ_CODE_MASK;
-        value |= IO_DPD_REQ_CODE_OFF;
-        pmc_write(value, request);
-
-        err = tegra_io_rail_poll(status, mask, 0, 250);
-        if (err < 0)
-                return err;
-
-        tegra_io_rail_unprepare();
-
-        return 0;
-}
-EXPORT_SYMBOL(tegra_io_rail_power_on);
-
-int tegra_io_rail_power_off(int id)
-{
-        unsigned long request, status, value;
-        unsigned int bit, mask;
-        int err;
-
-        err = tegra_io_rail_prepare(id, &request, &status, &bit);
-        if (err < 0)
-                return err;
-
-        mask = 1 << bit;
-
-        value = pmc_read(request);
-        value |= mask;
-        value &= ~IO_DPD_REQ_CODE_MASK;
-        value |= IO_DPD_REQ_CODE_ON;
-        pmc_write(value, request);
-
-        err = tegra_io_rail_poll(status, mask, mask, 250);
-        if (err < 0)
-                return err;
-
-        tegra_io_rail_unprepare();
-
-        return 0;
-}
-EXPORT_SYMBOL(tegra_io_rail_power_off);
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index 578d4d1ad648..7b2baab0f0bd 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -14,14 +14,15 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#include <linux/linkage.h>
 #include <linux/init.h>
+#include <linux/linkage.h>
+
+#include <soc/tegra/fuse.h>
 
-#include <asm/cache.h>
 #include <asm/asm-offsets.h>
+#include <asm/cache.h>
 
 #include "flowctrl.h"
-#include "fuse.h"
 #include "iomap.h"
 #include "reset.h"
 #include "sleep.h"
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
index 146fe8e0ae7c..894c5c472184 100644
--- a/arch/arm/mach-tegra/reset.c
+++ b/arch/arm/mach-tegra/reset.c
@@ -14,20 +14,21 @@
  *
  */
 
+#include <linux/bitops.h>
+#include <linux/cpumask.h>
 #include <linux/init.h>
 #include <linux/io.h>
-#include <linux/cpumask.h>
-#include <linux/bitops.h>
+
+#include <soc/tegra/fuse.h>
 
 #include <asm/cacheflush.h>
-#include <asm/hardware/cache-l2x0.h>
 #include <asm/firmware.h>
+#include <asm/hardware/cache-l2x0.h>
 
 #include "iomap.h"
 #include "irammap.h"
 #include "reset.h"
 #include "sleep.h"
-#include "fuse.h"
 
 #define TEGRA_IRAM_RESET_BASE (TEGRA_IRAM_BASE + \
                                 TEGRA_IRAM_RESET_HANDLER_OFFSET)
@@ -53,12 +54,10 @@ static void __init tegra_cpu_reset_handler_set(const u32 reset_address)
          * Prevent further modifications to the physical reset vector.
          *  NOTE: Has no effect on chips prior to Tegra30.
          */
-        if (tegra_chip_id != TEGRA20) {
-                reg = readl(sb_ctrl);
-                reg |= 2;
-                writel(reg, sb_ctrl);
-                wmb();
-        }
+        reg = readl(sb_ctrl);
+        reg |= 2;
+        writel(reg, sb_ctrl);
+        wmb();
 }
 
 static void __init tegra_cpu_reset_handler_enable(void)
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index 09cad9b071de..5d8d13aeab93 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -16,14 +16,15 @@
 
 #include <linux/linkage.h>
 
-#include <asm/assembler.h>
+#include <soc/tegra/fuse.h>
+
 #include <asm/asm-offsets.h>
+#include <asm/assembler.h>
 #include <asm/cache.h>
 
+#include "flowctrl.h"
 #include "irammap.h"
-#include "fuse.h"
 #include "sleep.h"
-#include "flowctrl.h"
 
 #define EMC_CFG                         0xc
 #define EMC_ADR_CFG                     0x10
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 339fe42cd6fb..92d46ec1361a 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -130,9 +130,6 @@ void tegra_disable_clean_inv_dcache(u32 flag);
 #ifdef CONFIG_HOTPLUG_CPU
 void tegra20_hotplug_shutdown(void);
 void tegra30_hotplug_shutdown(void);
-void tegra_hotplug_init(void);
-#else
-static inline void tegra_hotplug_init(void) {}
 #endif
 
 void tegra20_cpu_shutdown(int cpu);
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index 15ac9fcc96b1..5ef5173dec83 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -16,40 +16,40 @@
  *
  */
 
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
 #include <linux/clk.h>
+#include <linux/clk/tegra.h>
 #include <linux/dma-mapping.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irqchip.h>
 #include <linux/irqdomain.h>
-#include <linux/of.h>
+#include <linux/kernel.h>
 #include <linux/of_address.h>
 #include <linux/of_fdt.h>
+#include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/pda_power.h>
-#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
 #include <linux/slab.h>
 #include <linux/sys_soc.h>
 #include <linux/usb/tegra_usb_phy.h>
-#include <linux/clk/tegra.h>
-#include <linux/irqchip.h>
+
+#include <soc/tegra/fuse.h>
+#include <soc/tegra/pmc.h>
 
 #include <asm/hardware/cache-l2x0.h>
-#include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
+#include <asm/mach-types.h>
 #include <asm/setup.h>
 #include <asm/trusted_foundations.h>
 
-#include "apbio.h"
 #include "board.h"
 #include "common.h"
 #include "cpuidle.h"
-#include "fuse.h"
 #include "iomap.h"
 #include "irq.h"
-#include "pmc.h"
 #include "pm.h"
 #include "reset.h"
 #include "sleep.h"
@@ -73,16 +73,11 @@ u32 tegra_uart_config[3] = {
 static void __init tegra_init_early(void)
 {
         of_register_trusted_foundations();
-        tegra_apb_io_init();
-        tegra_init_fuse();
         tegra_cpu_reset_handler_init();
-        tegra_powergate_init();
-        tegra_hotplug_init();
 }
 
 static void __init tegra_dt_init_irq(void)
 {
-        tegra_pmc_init_irq();
         tegra_init_irq();
         irqchip_init();
         tegra_legacy_irq_syscore_init();
@@ -94,8 +89,6 @@ static void __init tegra_dt_init(void)
         struct soc_device *soc_dev;
         struct device *parent = NULL;
 
-        tegra_pmc_init();
-
         tegra_clocks_apply_init_table();
 
         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
@@ -103,8 +96,9 @@ static void __init tegra_dt_init(void)
                 goto out;
 
         soc_dev_attr->family = kasprintf(GFP_KERNEL, "Tegra");
-        soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d", tegra_revision);
-        soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%d", tegra_chip_id);
+        soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d",
+                                           tegra_sku_info.revision);
+        soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id());
 
         soc_dev = soc_device_register(soc_dev_attr);
         if (IS_ERR(soc_dev)) {
@@ -144,7 +138,6 @@ static void __init tegra_dt_init_late(void)
 
         tegra_init_suspend();
         tegra_cpuidle_init();
-        tegra_powergate_debugfs_init();
 
         for (i = 0; i < ARRAY_SIZE(board_init_funcs); i++) {
                 if (of_machine_is_compatible(board_init_funcs[i].machine)) {
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
index a4e139aa2441..32d744e91ec2 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.c
+++ b/arch/arm/mach-ux500/board-mop500-regulators.c
@@ -796,7 +796,7 @@ static struct ab8500_regulator_reg_init ab8505_reg_init[] = {
         INIT_REGULATOR_REGISTER(AB8505_CTRLVAUX6,              0x00, 0x00),
 };
 
-struct regulator_init_data ab8505_regulators[AB8505_NUM_REGULATORS] = {
+static struct regulator_init_data ab8505_regulators[AB8505_NUM_REGULATORS] = {
         /* supplies to the display/camera */
         [AB8505_LDO_AUX1] = {
                 .constraints = {
diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
index 842ebedbdd1c..e97ee556f92f 100644
--- a/arch/arm/mach-ux500/cache-l2x0.c
+++ b/arch/arm/mach-ux500/cache-l2x0.c
@@ -7,17 +7,15 @@
 #include <linux/io.h>
 #include <linux/of.h>
 
-#include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
 
 #include "db8500-regs.h"
 #include "id.h"
 
-static void __iomem *l2x0_base;
-
 static int __init ux500_l2x0_unlock(void)
 {
         int i;
+        void __iomem *l2x0_base = __io_address(U8500_L2CC_BASE);
 
         /*
          * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions
@@ -45,23 +43,15 @@ static void ux500_l2c310_write_sec(unsigned long val, unsigned reg)
 
 static int __init ux500_l2x0_init(void)
 {
-        if (cpu_is_u8500_family() || cpu_is_ux540_family())
-                l2x0_base = __io_address(U8500_L2CC_BASE);
-        else
-                /* Non-Ux500 platform */
+        /* Multiplatform guard */
+        if (!((cpu_is_u8500_family() || cpu_is_ux540_family())))
                 return -ENODEV;
 
         /* Unlock before init */
         ux500_l2x0_unlock();
-
         outer_cache.write_sec = ux500_l2c310_write_sec;
-
-        if (of_have_populated_dt())
-                l2x0_of_init(0, ~0);
-        else
-                l2x0_init(l2x0_base, 0, ~0);
+        l2x0_of_init(0, ~0);
 
         return 0;
 }
-
 early_initcall(ux500_l2x0_init);
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index fa308f07fae5..6f63954c8bde 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -33,11 +33,11 @@
 #include "db8500-regs.h"
 #include "id.h"
 
-struct ab8500_platform_data ab8500_platdata = {
+static struct ab8500_platform_data ab8500_platdata = {
         .regulator      = &ab8500_regulator_plat_data,
 };
 
-struct prcmu_pdata db8500_prcmu_pdata = {
+static struct prcmu_pdata db8500_prcmu_pdata = {
         .ab_platdata    = &ab8500_platdata,
         .version_offset = DB8500_PRCMU_FW_VERSION_OFFSET,
         .legacy_offset  = DB8500_PRCMU_LEGACY_OFFSET,
@@ -82,7 +82,7 @@ static struct map_desc u9540_io_desc[] __initdata = {
         __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K + SZ_8K),
 };
 
-void __init u8500_map_io(void)
+static void __init u8500_map_io(void)
 {
         /*
          * Map the UARTs early so that the DEBUG_LL stuff continues to work.
@@ -119,7 +119,7 @@ static irqreturn_t db8500_pmu_handler(int irq, void *dev, irq_handler_t handler)
         return ret;
 }
 
-struct arm_pmu_platdata db8500_pmu_platdata = {
+static struct arm_pmu_platdata db8500_pmu_platdata = {
         .handle_irq             = db8500_pmu_handler,
 };
 
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index db16b5a04ad5..dbb2970ee7da 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -125,7 +125,7 @@ static void __init soc_info_populate(struct soc_device_attribute *soc_dev_attr,
         soc_dev_attr->revision = ux500_get_revision();
 }
 
-struct device_attribute ux500_soc_attr =
+static const struct device_attribute ux500_soc_attr =
         __ATTR(process,  S_IRUGO, ux500_get_process,  NULL);
 
 struct device * __init ux500_soc_device_init(const char *soc_id)
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
index 87efda0aa348..ff28d8ad1ed7 100644
--- a/arch/arm/mach-ux500/timer.c
+++ b/arch/arm/mach-ux500/timer.c
@@ -16,7 +16,7 @@
 #include "db8500-regs.h"
 #include "id.h"
 
-const static struct of_device_id prcmu_timer_of_match[] __initconst = {
+static const struct of_device_id prcmu_timer_of_match[] __initconst = {
         { .compatible = "stericsson,db8500-prcmu-timer-4", },
         { },
 };
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index be83ba25f81b..08fb8c89f414 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -28,6 +28,7 @@
 #include <linux/of_platform.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
+#include <linux/platform_data/video-clcd-versatile.h>
 #include <linux/amba/pl061.h>
 #include <linux/amba/mmci.h>
 #include <linux/amba/pl022.h>
@@ -53,7 +54,6 @@
 #include <mach/platform.h>
 #include <asm/hardware/timer-sp.h>
 
-#include <plat/clcd.h>
 #include <plat/sched_clock.h>
 
 #include "core.h"
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 1af70329b88d..b2cfba16c4e8 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -13,7 +13,6 @@ menuconfig ARCH_VEXPRESS
         select ICST
         select NO_IOPORT_MAP
         select PLAT_VERSATILE
-        select PLAT_VERSATILE_CLCD
         select POWER_RESET
         select POWER_RESET_VEXPRESS
         select POWER_SUPPLY
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index 86150d7a2e7d..27bea049380a 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -8,6 +8,7 @@
 #include <linux/platform_device.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
+#include <linux/platform_data/video-clcd-versatile.h>
 #include <linux/clkdev.h>
 #include <linux/vexpress.h>
 #include <linux/irqchip/arm-gic.h>
@@ -29,8 +30,6 @@
 #include <mach/motherboard.h>
 #include <mach/irqs.h>
 
-#include <plat/clcd.h>
-
 static struct map_desc ct_ca9x4_io_desc[] __initdata = {
         {
                 .virtual        = V2T_PERIPH,
diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c
index 4a73464cb11b..2da7be31e7e2 100644
--- a/arch/arm/mach-vt8500/vt8500.c
+++ b/arch/arm/mach-vt8500/vt8500.c
@@ -44,7 +44,7 @@
 
 static void __iomem *pmc_base;
 
-void vt8500_restart(enum reboot_mode mode, const char *cmd)
+static void vt8500_restart(enum reboot_mode mode, const char *cmd)
 {
         if (pmc_base)
                 writel(1, pmc_base + VT8500_PMSR_REG);
@@ -60,7 +60,7 @@ static struct map_desc vt8500_io_desc[] __initdata = {
         },
 };
 
-void __init vt8500_map_io(void)
+static void __init vt8500_map_io(void)
 {
         iotable_init(vt8500_io_desc, ARRAY_SIZE(vt8500_io_desc));
 }
@@ -72,7 +72,7 @@ static void vt8500_power_off(void)
         asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0));
 }
 
-void __init vt8500_init(void)
+static void __init vt8500_init(void)
 {
         struct device_node *np;
 #if defined(CONFIG_FB_VT8500) || defined(CONFIG_FB_WM8505)
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 301b892d97d9..6910c8669742 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -15,7 +15,7 @@ config PLAT_SAMSUNG
 
 config PLAT_S5P
         bool
-        depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210)
+        depends on ARCH_S5PV210
         default y
         select ARCH_REQUIRE_GPIOLIB
         select ARM_VIC
@@ -29,7 +29,7 @@ config PLAT_S5P
 
 config SAMSUNG_PM
         bool
-        depends on PM && (PLAT_S3C24XX || ARCH_S3C64XX || ARCH_S5P64X0 || S5P_PM)
+        depends on PM && (PLAT_S3C24XX || ARCH_S3C64XX || S5P_PM)
         default y
         help
           Base platform power management code for samsung code
@@ -78,14 +78,14 @@ config SAMSUNG_CLKSRC
           used by newer systems such as the S3C64XX.
 
 config S5P_CLOCK
-        def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210)
+        def_bool ARCH_S5PV210
         help
           Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs
 
 # options for IRQ support
 
 config S5P_IRQ
-        def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210)
+        def_bool ARCH_S5PV210
         help
           Support common interrupt part for ARCH_S5P SoCs
 
@@ -93,7 +93,6 @@ config S5P_EXT_INT
         bool
         help
           Use the external interrupts (other than GPIO interrupts.)
-          Note: Do not choose this for S5P6440 and S5P6450.
 
 config S5P_GPIO_INT
         bool
@@ -108,22 +107,6 @@ config S5P_GPIO_DRVSTR
           Internal configuration to get and set correct GPIO driver strength
           helper
 
-config SAMSUNG_GPIO_EXTRA
-        int "Number of additional GPIO pins"
-        default 128 if SAMSUNG_GPIO_EXTRA128
-        default 64 if SAMSUNG_GPIO_EXTRA64
-        default 0
-        help
-          Use additional GPIO space in addition to the GPIO's the SOC
-          provides. This allows expanding the GPIO space for use with
-          GPIO expanders.
-
-config SAMSUNG_GPIO_EXTRA64
-        bool
-
-config SAMSUNG_GPIO_EXTRA128
-        bool
-
 config S3C_GPIO_SPACE
         int "Space between gpio banks"
         default 0
@@ -143,7 +126,7 @@ config S3C_GPIO_TRACK
 
 config S5P_DEV_UART
         def_bool y
-        depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210)
+        depends on ARCH_S5PV210
 
 # ADC driver
 
@@ -397,7 +380,7 @@ config SAMSUNG_PM_GPIO
 
 config SAMSUNG_DMADEV
         bool "Use legacy Samsung DMA abstraction"
-        depends on CPU_S5PV210 || CPU_S5PC100 || ARCH_S5P64X0 || ARCH_S3C64XX
+        depends on CPU_S5PV210 || ARCH_S3C64XX
         select DMADEVICES
         default y
         help
@@ -474,7 +457,6 @@ config S5P_PM
         bool
         help
           Common code for power management support on S5P and newer SoCs
-          Note: Do not select this for S5P6440 and S5P6450.
 
 config S5P_SLEEP
         bool
diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
index 79690f2f6d3f..468352633101 100644
--- a/arch/arm/plat-samsung/adc.c
+++ b/arch/arm/plat-samsung/adc.c
@@ -43,7 +43,7 @@ enum s3c_cpu_type {
         TYPE_ADCV1, /* S3C24XX */
         TYPE_ADCV11, /* S3C2443 */
         TYPE_ADCV12, /* S3C2416, S3C2450 */
-        TYPE_ADCV2, /* S3C64XX, S5P64X0, S5PC100 */
+        TYPE_ADCV2, /* S3C64XX */
         TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */
 };
 
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 5a237db9f9eb..d1d4659025bb 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -33,13 +33,6 @@ extern unsigned long samsung_cpu_id;
 #define S3C6410_CPU_ID          0x36410000
 #define S3C64XX_CPU_MASK        0xFFFFF000
 
-#define S5P6440_CPU_ID          0x56440000
-#define S5P6450_CPU_ID          0x36450000
-#define S5P64XX_CPU_MASK        0xFFFFF000
-
-#define S5PC100_CPU_ID          0x43100000
-#define S5PC100_CPU_MASK        0xFFFFF000
-
 #define S5PV210_CPU_ID          0x43110000
 #define S5PV210_CPU_MASK        0xFFFFF000
 
@@ -54,9 +47,6 @@ IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK)
 IS_SAMSUNG_CPU(s3c2412, S3C2412_CPU_ID, S3C2412_CPU_MASK)
 IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK)
 IS_SAMSUNG_CPU(s3c6410, S3C6410_CPU_ID, S3C64XX_CPU_MASK)
-IS_SAMSUNG_CPU(s5p6440, S5P6440_CPU_ID, S5P64XX_CPU_MASK)
-IS_SAMSUNG_CPU(s5p6450, S5P6450_CPU_ID, S5P64XX_CPU_MASK)
-IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK)
 IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
 
 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
@@ -86,24 +76,6 @@ IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
 # define soc_is_s3c64xx()       0
 #endif
 
-#if defined(CONFIG_CPU_S5P6440)
-# define soc_is_s5p6440()       is_samsung_s5p6440()
-#else
-# define soc_is_s5p6440()       0
-#endif
-
-#if defined(CONFIG_CPU_S5P6450)
-# define soc_is_s5p6450()       is_samsung_s5p6450()
-#else
-# define soc_is_s5p6450()       0
-#endif
-
-#if defined(CONFIG_CPU_S5PC100)
-# define soc_is_s5pc100()       is_samsung_s5pc100()
-#else
-# define soc_is_s5pc100()       0
-#endif
-
 #if defined(CONFIG_CPU_S5PV210)
 # define soc_is_s5pv210()       is_samsung_s5pv210()
 #else
@@ -177,7 +149,6 @@ extern struct bus_type s3c2440_subsys;
 extern struct bus_type s3c2442_subsys;
 extern struct bus_type s3c2443_subsys;
 extern struct bus_type s3c6410_subsys;
-extern struct bus_type s5p64x0_subsys;
 extern struct bus_type s5pv210_subsys;
 
 extern void (*s5pc1xx_idle)(void);
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index eece188ed188..5f5a28d08c2e 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -94,23 +94,6 @@ extern struct platform_device s5p_device_mixer;
 extern struct platform_device s5p_device_onenand;
 extern struct platform_device s5p_device_sdo;
 
-extern struct platform_device s5p6440_device_iis;
-extern struct platform_device s5p6440_device_pcm;
-
-extern struct platform_device s5p6450_device_iis0;
-extern struct platform_device s5p6450_device_iis1;
-extern struct platform_device s5p6450_device_iis2;
-extern struct platform_device s5p6450_device_pcm0;
-
-
-extern struct platform_device s5pc100_device_ac97;
-extern struct platform_device s5pc100_device_iis0;
-extern struct platform_device s5pc100_device_iis1;
-extern struct platform_device s5pc100_device_iis2;
-extern struct platform_device s5pc100_device_pcm0;
-extern struct platform_device s5pc100_device_pcm1;
-extern struct platform_device s5pc100_device_spdif;
-
 extern struct platform_device s5pv210_device_ac97;
 extern struct platform_device s5pv210_device_iis0;
 extern struct platform_device s5pv210_device_iis1;
diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h
index 9ae507270785..5a0e26afb961 100644
--- a/arch/arm/plat-samsung/include/plat/fb.h
+++ b/arch/arm/plat-samsung/include/plat/fb.h
@@ -41,13 +41,6 @@ extern void s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd);
 extern void s3c64xx_fb_gpio_setup_24bpp(void);
 
 /**
- * s5pc100_fb_gpio_setup_24bpp() - S5PC100 setup function for 24bpp LCD
- *
- * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
- */
-extern void s5pc100_fb_gpio_setup_24bpp(void);
-
-/**
  * s5pv210_fb_gpio_setup_24bpp() - S5PV210/S5PC110 setup function for 24bpp LCD
  *
  * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
@@ -61,11 +54,4 @@ extern void s5pv210_fb_gpio_setup_24bpp(void);
  */
 extern void exynos4_fimd0_gpio_setup_24bpp(void);
 
-/**
- * s5p64x0_fb_gpio_setup_24bpp() - S5P6440/S5P6450 setup function for 24bpp LCD
- *
- * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
- */
-extern void s5p64x0_fb_gpio_setup_24bpp(void);
-
 #endif /* __PLAT_S3C_FB_H */
diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h
index cf5aae5b0975..6ce11bfdc37e 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-core.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-core.h
@@ -14,6 +14,9 @@
 #ifndef __PLAT_SAMSUNG_GPIO_CORE_H
 #define __PLAT_SAMSUNG_GPIO_CORE_H
 
+/* Bring in machine-local definitions, especially S3C_GPIO_END */
+#include <mach/gpio-samsung.h>
+
 #define GPIOCON_OFF     (0x00)
 #define GPIODAT_OFF     (0x04)
 
diff --git a/arch/arm/plat-samsung/include/plat/s5p-clock.h b/arch/arm/plat-samsung/include/plat/s5p-clock.h
index 8364b4bea8b8..acacc4b88a39 100644
--- a/arch/arm/plat-samsung/include/plat/s5p-clock.h
+++ b/arch/arm/plat-samsung/include/plat/s5p-clock.h
@@ -57,7 +57,7 @@ extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable);
 extern int s5p_epll_enable(struct clk *clk, int enable);
 extern unsigned long s5p_epll_get_rate(struct clk *clk);
 
-/* SPDIF clk operations common for S5PC100/V210/C110 and Exynos4 */
+/* SPDIF clk operations common for S5PV210/C110 and Exynos4 */
 extern int s5p_spdif_set_rate(struct clk *clk, unsigned long rate);
 extern unsigned long s5p_spdif_get_rate(struct clk *clk);
 
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index bf650218b40e..f84b6cbc8745 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -56,9 +56,6 @@ extern void s3c2416_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
 extern void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
 extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
 extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
-extern void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
-extern void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
-extern void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
 extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
 extern void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
 extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
@@ -68,10 +65,6 @@ extern void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
 extern void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
 extern void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
 extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
-extern void s5p64x0_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
-extern void s5p64x0_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
-extern void s5p6440_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
-extern void s5p6450_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
 
 /* S3C2416 SDHCI setup */
 
@@ -151,76 +144,6 @@ static inline void s3c6400_default_sdhci2(void) { }
 
 #endif /* CONFIG_S3C64XX_SETUP_SDHCI */
 
-/* S5P64X0 SDHCI setup */
-
-#ifdef CONFIG_S5P64X0_SETUP_SDHCI_GPIO
-static inline void s5p64x0_default_sdhci0(void)
-{
-#ifdef CONFIG_S3C_DEV_HSMMC
-        s3c_hsmmc0_def_platdata.cfg_gpio = s5p64x0_setup_sdhci0_cfg_gpio;
-#endif
-}
-
-static inline void s5p64x0_default_sdhci1(void)
-{
-#ifdef CONFIG_S3C_DEV_HSMMC1
-        s3c_hsmmc1_def_platdata.cfg_gpio = s5p64x0_setup_sdhci1_cfg_gpio;
-#endif
-}
-
-static inline void s5p6440_default_sdhci2(void)
-{
-#ifdef CONFIG_S3C_DEV_HSMMC2
-        s3c_hsmmc2_def_platdata.cfg_gpio = s5p6440_setup_sdhci2_cfg_gpio;
-#endif
-}
-
-static inline void s5p6450_default_sdhci2(void)
-{
-#ifdef CONFIG_S3C_DEV_HSMMC2
-        s3c_hsmmc2_def_platdata.cfg_gpio = s5p6450_setup_sdhci2_cfg_gpio;
-#endif
-}
-
-#else
-static inline void s5p64x0_default_sdhci0(void) { }
-static inline void s5p64x0_default_sdhci1(void) { }
-static inline void s5p6440_default_sdhci2(void) { }
-static inline void s5p6450_default_sdhci2(void) { }
-
-#endif /* CONFIG_S5P64X0_SETUP_SDHCI_GPIO */
-
-/* S5PC100 SDHCI setup */
-
-#ifdef CONFIG_S5PC100_SETUP_SDHCI
-static inline void s5pc100_default_sdhci0(void)
-{
-#ifdef CONFIG_S3C_DEV_HSMMC
-        s3c_hsmmc0_def_platdata.cfg_gpio = s5pc100_setup_sdhci0_cfg_gpio;
-#endif
-}
-
-static inline void s5pc100_default_sdhci1(void)
-{
-#ifdef CONFIG_S3C_DEV_HSMMC1
-        s3c_hsmmc1_def_platdata.cfg_gpio = s5pc100_setup_sdhci1_cfg_gpio;
-#endif
-}
-
-static inline void s5pc100_default_sdhci2(void)
-{
-#ifdef CONFIG_S3C_DEV_HSMMC2
-        s3c_hsmmc2_def_platdata.cfg_gpio = s5pc100_setup_sdhci2_cfg_gpio;
-#endif
-}
-
-#else
-static inline void s5pc100_default_sdhci0(void) { }
-static inline void s5pc100_default_sdhci1(void) { }
-static inline void s5pc100_default_sdhci2(void) { }
-
-#endif /* CONFIG_S5PC100_SETUP_SDHCI */
-
 /* S5PV210 SDHCI setup */
 
 #ifdef CONFIG_S5PV210_SETUP_SDHCI
diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c
index da268813901b..adc91662f72b 100644
--- a/arch/arm/plat-samsung/pm-gpio.c
+++ b/arch/arm/plat-samsung/pm-gpio.c
@@ -19,9 +19,7 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 
-#if defined(CONFIG_ARCH_S3C24XX) || defined(CONFIG_ARCH_S3C64XX)
 #include <mach/gpio-samsung.h>
-#endif
 
 #include <plat/gpio-core.h>
 #include <plat/pm.h>
diff --git a/arch/arm/plat-samsung/s5p-irq-eint.c b/arch/arm/plat-samsung/s5p-irq-eint.c
index ebee4dc11a94..dcd8c2cbf5bb 100644
--- a/arch/arm/plat-samsung/s5p-irq-eint.c
+++ b/arch/arm/plat-samsung/s5p-irq-eint.c
@@ -14,7 +14,6 @@
 #include <linux/irq.h>
 #include <linux/io.h>
 #include <linux/device.h>
-#include <linux/gpio.h>
 #include <linux/irqchip/arm-vic.h>
 #include <linux/of.h>
 
@@ -26,6 +25,7 @@
 
 #include <plat/gpio-cfg.h>
 #include <mach/regs-gpio.h>
+#include <mach/gpio-samsung.h>
 
 static inline void s5p_irq_eint_mask(struct irq_data *data)
 {
diff --git a/arch/arm/plat-versatile/Kconfig b/arch/arm/plat-versatile/Kconfig
index fce41e93b6a4..a301ca2c7d00 100644
--- a/arch/arm/plat-versatile/Kconfig
+++ b/arch/arm/plat-versatile/Kconfig
@@ -3,9 +3,6 @@ if PLAT_VERSATILE
 config PLAT_VERSATILE_CLOCK
         bool
 
-config PLAT_VERSATILE_CLCD
-        bool
-
 config PLAT_VERSATILE_SCHED_CLOCK
         def_bool y
 
diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile
index 2e0c472958ae..03c4900ac3f4 100644
--- a/arch/arm/plat-versatile/Makefile
+++ b/arch/arm/plat-versatile/Makefile
@@ -1,6 +1,5 @@
 ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
 
 obj-$(CONFIG_PLAT_VERSATILE_CLOCK) += clock.o
-obj-$(CONFIG_PLAT_VERSATILE_CLCD) += clcd.o
 obj-$(CONFIG_PLAT_VERSATILE_SCHED_CLOCK) += sched-clock.o
 obj-$(CONFIG_SMP) += headsmp.o platsmp.o
diff --git a/arch/arm/plat-versatile/include/plat/clcd.h b/arch/arm/plat-versatile/include/plat/clcd.h
deleted file mode 100644
index 6bb6a1d2019b..000000000000
--- a/arch/arm/plat-versatile/include/plat/clcd.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef PLAT_CLCD_H
-#define PLAT_CLCD_H
-
-struct clcd_panel *versatile_clcd_get_panel(const char *);
-int versatile_clcd_setup_dma(struct clcd_fb *, unsigned long);
-int versatile_clcd_mmap_dma(struct clcd_fb *, struct vm_area_struct *);
-void versatile_clcd_remove_dma(struct clcd_fb *);
-
-#endif
diff --git a/drivers/amba/tegra-ahb.c b/drivers/amba/tegra-ahb.c
index 558a239954e8..d8961ef4d2e7 100644
--- a/drivers/amba/tegra-ahb.c
+++ b/drivers/amba/tegra-ahb.c
@@ -25,7 +25,8 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
-#include <linux/tegra-ahb.h>
+
+#include <soc/tegra/ahb.h>
 
 #define DRV_NAME "tegra-ahb"
 
diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c
index 5a86da97a70b..7af78df241f2 100644
--- a/drivers/bus/arm-cci.c
+++ b/drivers/bus/arm-cci.c
@@ -397,7 +397,8 @@ static irqreturn_t pmu_handle_irq(int irq_num, void *dev)
                 hw_counter = &event->hw;
 
                 /* Did this counter overflow? */
-                if (!pmu_read_register(idx, CCI_PMU_OVRFLW) & CCI_PMU_OVRFLW_FLAG)
+                if (!(pmu_read_register(idx, CCI_PMU_OVRFLW) &
+                      CCI_PMU_OVRFLW_FLAG))
                         continue;
 
                 pmu_write_register(CCI_PMU_OVRFLW_FLAG, idx, CCI_PMU_OVRFLW);
diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
index 507015314827..0aa8830ae7cc 100644
--- a/drivers/clk/tegra/clk-periph-gate.c
+++ b/drivers/clk/tegra/clk-periph-gate.c
@@ -20,7 +20,8 @@
 #include <linux/io.h>
 #include <linux/delay.h>
 #include <linux/err.h>
-#include <linux/tegra-soc.h>
+
+#include <soc/tegra/fuse.h>
 
 #include "clk.h"
 
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 8b10c38b6e3c..5bbacd01094f 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -22,8 +22,11 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/clk/tegra.h>
-#include <linux/tegra-powergate.h>
+
+#include <soc/tegra/pmc.h>
+
 #include <dt-bindings/clock/tegra30-car.h>
+
 #include "clk.h"
 #include "clk-id.h"
 
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
index bf452b62beb8..f87c609e8f72 100644
--- a/drivers/clk/tegra/clk.c
+++ b/drivers/clk/tegra/clk.c
@@ -19,7 +19,8 @@
 #include <linux/of.h>
 #include <linux/clk/tegra.h>
 #include <linux/reset-controller.h>
-#include <linux/tegra-soc.h>
+
+#include <soc/tegra/fuse.h>
 
 #include "clk.h"
 
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index 07105ee5c9ae..d9cff026827e 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -32,10 +32,7 @@
 
 #include <mach/map.h>
 #include <mach/regs-gpio.h>
-
-#if defined(CONFIG_ARCH_S3C24XX) || defined(CONFIG_ARCH_S3C64XX)
 #include <mach/gpio-samsung.h>
-#endif
 
 #include <plat/cpu.h>
 #include <plat/gpio-core.h>
@@ -358,47 +355,6 @@ static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip,
 }
 #endif
 
-#if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
-static int s5p64x0_gpio_setcfg_rbank(struct samsung_gpio_chip *chip,
-                                     unsigned int off, unsigned int cfg)
-{
-        void __iomem *reg = chip->base;
-        unsigned int shift;
-        u32 con;
-
-        switch (off) {
-        case 0:
-        case 1:
-        case 2:
-        case 3:
-        case 4:
-        case 5:
-                shift = (off & 7) * 4;
-                reg -= 4;
-                break;
-        case 6:
-                shift = ((off + 1) & 7) * 4;
-                reg -= 4;
-                break;
-        default:
-                shift = ((off + 1) & 7) * 4;
-                break;
-        }
-
-        if (samsung_gpio_is_cfg_special(cfg)) {
-                cfg &= 0xf;
-                cfg <<= shift;
-        }
-
-        con = __raw_readl(reg);
-        con &= ~(0xf << shift);
-        con |= cfg;
-        __raw_writel(con, reg);
-
-        return 0;
-}
-#endif
-
 static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg,
                                            int nr_chips)
 {
@@ -426,16 +382,6 @@ static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
 };
 #endif
 
-#if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
-static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = {
-        .cfg_eint       = 0x3,
-        .set_config     = s5p64x0_gpio_setcfg_rbank,
-        .get_config     = samsung_gpio_getcfg_4bit,
-        .set_pull       = samsung_gpio_setpull_updown,
-        .get_pull       = samsung_gpio_getpull_updown,
-};
-#endif
-
 static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
         [0] = {
                 .cfg_eint       = 0x0,
@@ -708,91 +654,6 @@ static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
 }
 #endif
 
-/* The next set of routines are for the case of s5p64x0 bank r */
-
-static int s5p64x0_gpiolib_rbank_input(struct gpio_chip *chip,
-                                       unsigned int offset)
-{
-        struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
-        void __iomem *base = ourchip->base;
-        void __iomem *regcon = base;
-        unsigned long con;
-        unsigned long flags;
-
-        switch (offset) {
-        case 6:
-                offset += 1;
-        case 0:
-        case 1:
-        case 2:
-        case 3:
-        case 4:
-        case 5:
-                regcon -= 4;
-                break;
-        default:
-                offset -= 7;
-                break;
-        }
-
-        samsung_gpio_lock(ourchip, flags);
-
-        con = __raw_readl(regcon);
-        con &= ~(0xf << con_4bit_shift(offset));
-        __raw_writel(con, regcon);
-
-        samsung_gpio_unlock(ourchip, flags);
-
-        return 0;
-}
-
-static int s5p64x0_gpiolib_rbank_output(struct gpio_chip *chip,
-                                        unsigned int offset, int value)
-{
-        struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
-        void __iomem *base = ourchip->base;
-        void __iomem *regcon = base;
-        unsigned long con;
-        unsigned long dat;
-        unsigned long flags;
-        unsigned con_offset  = offset;
-
-        switch (con_offset) {
-        case 6:
-                con_offset += 1;
-        case 0:
-        case 1:
-        case 2:
-        case 3:
-        case 4:
-        case 5:
-                regcon -= 4;
-                break;
-        default:
-                con_offset -= 7;
-                break;
-        }
-
-        samsung_gpio_lock(ourchip, flags);
-
-        con = __raw_readl(regcon);
-        con &= ~(0xf << con_4bit_shift(con_offset));
-        con |= 0x1 << con_4bit_shift(con_offset);
-
-        dat = __raw_readl(base + GPIODAT_OFF);
-        if (value)
-                dat |= 1 << offset;
-        else
-                dat &= ~(1 << offset);
-
-        __raw_writel(con, regcon);
-        __raw_writel(dat, base + GPIODAT_OFF);
-
-        samsung_gpio_unlock(ourchip, flags);
-
-        return 0;
-}
-
 static void samsung_gpiolib_set(struct gpio_chip *chip,
                                 unsigned offset, int value)
 {
@@ -999,20 +860,6 @@ static void __init samsung_gpiolib_add_4bit2_chips(struct samsung_gpio_chip *chi
         }
 }
 
-static void __init s5p64x0_gpiolib_add_rbank(struct samsung_gpio_chip *chip,
-                                             int nr_chips)
-{
-        for (; nr_chips > 0; nr_chips--, chip++) {
-                chip->chip.direction_input = s5p64x0_gpiolib_rbank_input;
-                chip->chip.direction_output = s5p64x0_gpiolib_rbank_output;
-
-                if (!chip->pm)
-                        chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
-
-                samsung_gpiolib_add(chip);
-        }
-}
-
 int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
 {
         struct samsung_gpio_chip *samsung_chip = container_of(chip, struct samsung_gpio_chip, chip);
@@ -1320,545 +1167,6 @@ static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
 };
 
 /*
- * S5P6440 GPIO bank summary:
- *
- * Bank GPIOs   Style   SlpCon  ExtInt Group
- * A    6       4Bit    Yes     1
- * B    7       4Bit    Yes     1
- * C    8       4Bit    Yes     2
- * F    2       2Bit    Yes     4 [1]
- * G    7       4Bit    Yes     5
- * H    10      4Bit[2] Yes     6
- * I    16      2Bit    Yes     None
- * J    12      2Bit    Yes     None
- * N    16      2Bit    No      IRQ_EINT
- * P    8       2Bit    Yes     8
- * R    15      4Bit[2] Yes     8
- */
-
-static struct samsung_gpio_chip s5p6440_gpios_4bit[] = {
-#ifdef CONFIG_CPU_S5P6440
-        {
-                .chip   = {
-                        .base   = S5P6440_GPA(0),
-                        .ngpio  = S5P6440_GPIO_A_NR,
-                        .label  = "GPA",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5P6440_GPB(0),
-                        .ngpio  = S5P6440_GPIO_B_NR,
-                        .label  = "GPB",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5P6440_GPC(0),
-                        .ngpio  = S5P6440_GPIO_C_NR,
-                        .label  = "GPC",
-                },
-        }, {
-                .base   = S5P64X0_GPG_BASE,
-                .chip   = {
-                        .base   = S5P6440_GPG(0),
-                        .ngpio  = S5P6440_GPIO_G_NR,
-                        .label  = "GPG",
-                },
-        },
-#endif
-};
-
-static struct samsung_gpio_chip s5p6440_gpios_4bit2[] = {
-#ifdef CONFIG_CPU_S5P6440
-        {
-                .base   = S5P64X0_GPH_BASE + 0x4,
-                .chip   = {
-                        .base   = S5P6440_GPH(0),
-                        .ngpio  = S5P6440_GPIO_H_NR,
-                        .label  = "GPH",
-                },
-        },
-#endif
-};
-
-static struct samsung_gpio_chip s5p6440_gpios_rbank[] = {
-#ifdef CONFIG_CPU_S5P6440
-        {
-                .base   = S5P64X0_GPR_BASE + 0x4,
-                .config = &s5p64x0_gpio_cfg_rbank,
-                .chip   = {
-                        .base   = S5P6440_GPR(0),
-                        .ngpio  = S5P6440_GPIO_R_NR,
-                        .label  = "GPR",
-                },
-        },
-#endif
-};
-
-static struct samsung_gpio_chip s5p6440_gpios_2bit[] = {
-#ifdef CONFIG_CPU_S5P6440
-        {
-                .base   = S5P64X0_GPF_BASE,
-                .config = &samsung_gpio_cfgs[6],
-                .chip   = {
-                        .base   = S5P6440_GPF(0),
-                        .ngpio  = S5P6440_GPIO_F_NR,
-                        .label  = "GPF",
-                },
-        }, {
-                .base   = S5P64X0_GPI_BASE,
-                .config = &samsung_gpio_cfgs[4],
-                .chip   = {
-                        .base   = S5P6440_GPI(0),
-                        .ngpio  = S5P6440_GPIO_I_NR,
-                        .label  = "GPI",
-                },
-        }, {
-                .base   = S5P64X0_GPJ_BASE,
-                .config = &samsung_gpio_cfgs[4],
-                .chip   = {
-                        .base   = S5P6440_GPJ(0),
-                        .ngpio  = S5P6440_GPIO_J_NR,
-                        .label  = "GPJ",
-                },
-        }, {
-                .base   = S5P64X0_GPN_BASE,
-                .config = &samsung_gpio_cfgs[5],
-                .chip   = {
-                        .base   = S5P6440_GPN(0),
-                        .ngpio  = S5P6440_GPIO_N_NR,
-                        .label  = "GPN",
-                },
-        }, {
-                .base   = S5P64X0_GPP_BASE,
-                .config = &samsung_gpio_cfgs[6],
-                .chip   = {
-                        .base   = S5P6440_GPP(0),
-                        .ngpio  = S5P6440_GPIO_P_NR,
-                        .label  = "GPP",
-                },
-        },
-#endif
-};
-
-/*
- * S5P6450 GPIO bank summary:
- *
- * Bank GPIOs   Style   SlpCon  ExtInt Group
- * A    6       4Bit    Yes     1
- * B    7       4Bit    Yes     1
- * C    8       4Bit    Yes     2
- * D    8       4Bit    Yes     None
- * F    2       2Bit    Yes     None
- * G    14      4Bit[2] Yes     5
- * H    10      4Bit[2] Yes     6
- * I    16      2Bit    Yes     None
- * J    12      2Bit    Yes     None
- * K    5       4Bit    Yes     None
- * N    16      2Bit    No      IRQ_EINT
- * P    11      2Bit    Yes     8
- * Q    14      2Bit    Yes     None
- * R    15      4Bit[2] Yes     None
- * S    8       2Bit    Yes     None
- *
- * [1] BANKF pins 14,15 do not form part of the external interrupt sources
- * [2] BANK has two control registers, GPxCON0 and GPxCON1
- */
-
-static struct samsung_gpio_chip s5p6450_gpios_4bit[] = {
-#ifdef CONFIG_CPU_S5P6450
-        {
-                .chip   = {
-                        .base   = S5P6450_GPA(0),
-                        .ngpio  = S5P6450_GPIO_A_NR,
-                        .label  = "GPA",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5P6450_GPB(0),
-                        .ngpio  = S5P6450_GPIO_B_NR,
-                        .label  = "GPB",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5P6450_GPC(0),
-                        .ngpio  = S5P6450_GPIO_C_NR,
-                        .label  = "GPC",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5P6450_GPD(0),
-                        .ngpio  = S5P6450_GPIO_D_NR,
-                        .label  = "GPD",
-                },
-        }, {
-                .base   = S5P6450_GPK_BASE,
-                .chip   = {
-                        .base   = S5P6450_GPK(0),
-                        .ngpio  = S5P6450_GPIO_K_NR,
-                        .label  = "GPK",
-                },
-        },
-#endif
-};
-
-static struct samsung_gpio_chip s5p6450_gpios_4bit2[] = {
-#ifdef CONFIG_CPU_S5P6450
-        {
-                .base   = S5P64X0_GPG_BASE + 0x4,
-                .chip   = {
-                        .base   = S5P6450_GPG(0),
-                        .ngpio  = S5P6450_GPIO_G_NR,
-                        .label  = "GPG",
-                },
-        }, {
-                .base   = S5P64X0_GPH_BASE + 0x4,
-                .chip   = {
-                        .base   = S5P6450_GPH(0),
-                        .ngpio  = S5P6450_GPIO_H_NR,
-                        .label  = "GPH",
-                },
-        },
-#endif
-};
-
-static struct samsung_gpio_chip s5p6450_gpios_rbank[] = {
-#ifdef CONFIG_CPU_S5P6450
-        {
-                .base   = S5P64X0_GPR_BASE + 0x4,
-                .config = &s5p64x0_gpio_cfg_rbank,
-                .chip   = {
-                        .base   = S5P6450_GPR(0),
-                        .ngpio  = S5P6450_GPIO_R_NR,
-                        .label  = "GPR",
-                },
-        },
-#endif
-};
-
-static struct samsung_gpio_chip s5p6450_gpios_2bit[] = {
-#ifdef CONFIG_CPU_S5P6450
-        {
-                .base   = S5P64X0_GPF_BASE,
-                .config = &samsung_gpio_cfgs[6],
-                .chip   = {
-                        .base   = S5P6450_GPF(0),
-                        .ngpio  = S5P6450_GPIO_F_NR,
-                        .label  = "GPF",
-                },
-        }, {
-                .base   = S5P64X0_GPI_BASE,
-                .config = &samsung_gpio_cfgs[4],
-                .chip   = {
-                        .base   = S5P6450_GPI(0),
-                        .ngpio  = S5P6450_GPIO_I_NR,
-                        .label  = "GPI",
-                },
-        }, {
-                .base   = S5P64X0_GPJ_BASE,
-                .config = &samsung_gpio_cfgs[4],
-                .chip   = {
-                        .base   = S5P6450_GPJ(0),
-                        .ngpio  = S5P6450_GPIO_J_NR,
-                        .label  = "GPJ",
-                },
-        }, {
-                .base   = S5P64X0_GPN_BASE,
-                .config = &samsung_gpio_cfgs[5],
-                .chip   = {
-                        .base   = S5P6450_GPN(0),
-                        .ngpio  = S5P6450_GPIO_N_NR,
-                        .label  = "GPN",
-                },
-        }, {
-                .base   = S5P64X0_GPP_BASE,
-                .config = &samsung_gpio_cfgs[6],
-                .chip   = {
-                        .base   = S5P6450_GPP(0),
-                        .ngpio  = S5P6450_GPIO_P_NR,
-                        .label  = "GPP",
-                },
-        }, {
-                .base   = S5P6450_GPQ_BASE,
-                .config = &samsung_gpio_cfgs[5],
-                .chip   = {
-                        .base   = S5P6450_GPQ(0),
-                        .ngpio  = S5P6450_GPIO_Q_NR,
-                        .label  = "GPQ",
-                },
-        }, {
-                .base   = S5P6450_GPS_BASE,
-                .config = &samsung_gpio_cfgs[6],
-                .chip   = {
-                        .base   = S5P6450_GPS(0),
-                        .ngpio  = S5P6450_GPIO_S_NR,
-                        .label  = "GPS",
-                },
-        },
-#endif
-};
-
-/*
- * S5PC100 GPIO bank summary:
- *
- * Bank GPIOs   Style   INT Type
- * A0   8       4Bit    GPIO_INT0
- * A1   5       4Bit    GPIO_INT1
- * B    8       4Bit    GPIO_INT2
- * C    5       4Bit    GPIO_INT3
- * D    7       4Bit    GPIO_INT4
- * E0   8       4Bit    GPIO_INT5
- * E1   6       4Bit    GPIO_INT6
- * F0   8       4Bit    GPIO_INT7
- * F1   8       4Bit    GPIO_INT8
- * F2   8       4Bit    GPIO_INT9
- * F3   4       4Bit    GPIO_INT10
- * G0   8       4Bit    GPIO_INT11
- * G1   3       4Bit    GPIO_INT12
- * G2   7       4Bit    GPIO_INT13
- * G3   7       4Bit    GPIO_INT14
- * H0   8       4Bit    WKUP_INT
- * H1   8       4Bit    WKUP_INT
- * H2   8       4Bit    WKUP_INT
- * H3   8       4Bit    WKUP_INT
- * I    8       4Bit    GPIO_INT15
- * J0   8       4Bit    GPIO_INT16
- * J1   5       4Bit    GPIO_INT17
- * J2   8       4Bit    GPIO_INT18
- * J3   8       4Bit    GPIO_INT19
- * J4   4       4Bit    GPIO_INT20
- * K0   8       4Bit    None
- * K1   6       4Bit    None
- * K2   8       4Bit    None
- * K3   8       4Bit    None
- * L0   8       4Bit    None
- * L1   8       4Bit    None
- * L2   8       4Bit    None
- * L3   8       4Bit    None
- */
-
-static struct samsung_gpio_chip s5pc100_gpios_4bit[] = {
-#ifdef CONFIG_CPU_S5PC100
-        {
-                .chip   = {
-                        .base   = S5PC100_GPA0(0),
-                        .ngpio  = S5PC100_GPIO_A0_NR,
-                        .label  = "GPA0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPA1(0),
-                        .ngpio  = S5PC100_GPIO_A1_NR,
-                        .label  = "GPA1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPB(0),
-                        .ngpio  = S5PC100_GPIO_B_NR,
-                        .label  = "GPB",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPC(0),
-                        .ngpio  = S5PC100_GPIO_C_NR,
-                        .label  = "GPC",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPD(0),
-                        .ngpio  = S5PC100_GPIO_D_NR,
-                        .label  = "GPD",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPE0(0),
-                        .ngpio  = S5PC100_GPIO_E0_NR,
-                        .label  = "GPE0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPE1(0),
-                        .ngpio  = S5PC100_GPIO_E1_NR,
-                        .label  = "GPE1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPF0(0),
-                        .ngpio  = S5PC100_GPIO_F0_NR,
-                        .label  = "GPF0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPF1(0),
-                        .ngpio  = S5PC100_GPIO_F1_NR,
-                        .label  = "GPF1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPF2(0),
-                        .ngpio  = S5PC100_GPIO_F2_NR,
-                        .label  = "GPF2",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPF3(0),
-                        .ngpio  = S5PC100_GPIO_F3_NR,
-                        .label  = "GPF3",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPG0(0),
-                        .ngpio  = S5PC100_GPIO_G0_NR,
-                        .label  = "GPG0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPG1(0),
-                        .ngpio  = S5PC100_GPIO_G1_NR,
-                        .label  = "GPG1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPG2(0),
-                        .ngpio  = S5PC100_GPIO_G2_NR,
-                        .label  = "GPG2",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPG3(0),
-                        .ngpio  = S5PC100_GPIO_G3_NR,
-                        .label  = "GPG3",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPI(0),
-                        .ngpio  = S5PC100_GPIO_I_NR,
-                        .label  = "GPI",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPJ0(0),
-                        .ngpio  = S5PC100_GPIO_J0_NR,
-                        .label  = "GPJ0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPJ1(0),
-                        .ngpio  = S5PC100_GPIO_J1_NR,
-                        .label  = "GPJ1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPJ2(0),
-                        .ngpio  = S5PC100_GPIO_J2_NR,
-                        .label  = "GPJ2",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPJ3(0),
-                        .ngpio  = S5PC100_GPIO_J3_NR,
-                        .label  = "GPJ3",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPJ4(0),
-                        .ngpio  = S5PC100_GPIO_J4_NR,
-                        .label  = "GPJ4",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPK0(0),
-                        .ngpio  = S5PC100_GPIO_K0_NR,
-                        .label  = "GPK0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPK1(0),
-                        .ngpio  = S5PC100_GPIO_K1_NR,
-                        .label  = "GPK1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPK2(0),
-                        .ngpio  = S5PC100_GPIO_K2_NR,
-                        .label  = "GPK2",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPK3(0),
-                        .ngpio  = S5PC100_GPIO_K3_NR,
-                        .label  = "GPK3",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPL0(0),
-                        .ngpio  = S5PC100_GPIO_L0_NR,
-                        .label  = "GPL0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPL1(0),
-                        .ngpio  = S5PC100_GPIO_L1_NR,
-                        .label  = "GPL1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPL2(0),
-                        .ngpio  = S5PC100_GPIO_L2_NR,
-                        .label  = "GPL2",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPL3(0),
-                        .ngpio  = S5PC100_GPIO_L3_NR,
-                        .label  = "GPL3",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPL4(0),
-                        .ngpio  = S5PC100_GPIO_L4_NR,
-                        .label  = "GPL4",
-                },
-        }, {
-                .base   = (S5P_VA_GPIO + 0xC00),
-                .irq_base = IRQ_EINT(0),
-                .chip   = {
-                        .base   = S5PC100_GPH0(0),
-                        .ngpio  = S5PC100_GPIO_H0_NR,
-                        .label  = "GPH0",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        }, {
-                .base   = (S5P_VA_GPIO + 0xC20),
-                .irq_base = IRQ_EINT(8),
-                .chip   = {
-                        .base   = S5PC100_GPH1(0),
-                        .ngpio  = S5PC100_GPIO_H1_NR,
-                        .label  = "GPH1",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        }, {
-                .base   = (S5P_VA_GPIO + 0xC40),
-                .irq_base = IRQ_EINT(16),
-                .chip   = {
-                        .base   = S5PC100_GPH2(0),
-                        .ngpio  = S5PC100_GPIO_H2_NR,
-                        .label  = "GPH2",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        }, {
-                .base   = (S5P_VA_GPIO + 0xC60),
-                .irq_base = IRQ_EINT(24),
-                .chip   = {
-                        .base   = S5PC100_GPH3(0),
-                        .ngpio  = S5PC100_GPIO_H3_NR,
-                        .label  = "GPH3",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        },
-#endif
-};
-
-/*
  * Followings are the gpio banks in S5PV210/S5PC110
  *
  * The 'config' member when left to NULL, is initialized to the default
@@ -2109,39 +1417,6 @@ static __init int samsung_gpiolib_init(void)
                                 S3C64XX_VA_GPIO);
                 samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
                                 ARRAY_SIZE(s3c64xx_gpios_4bit2));
-        } else if (soc_is_s5p6440()) {
-                samsung_gpiolib_add_2bit_chips(s5p6440_gpios_2bit,
-                                ARRAY_SIZE(s5p6440_gpios_2bit), NULL, 0x0);
-                samsung_gpiolib_add_4bit_chips(s5p6440_gpios_4bit,
-                                ARRAY_SIZE(s5p6440_gpios_4bit), S5P_VA_GPIO);
-                samsung_gpiolib_add_4bit2_chips(s5p6440_gpios_4bit2,
-                                ARRAY_SIZE(s5p6440_gpios_4bit2));
-                s5p64x0_gpiolib_add_rbank(s5p6440_gpios_rbank,
-                                ARRAY_SIZE(s5p6440_gpios_rbank));
-        } else if (soc_is_s5p6450()) {
-                samsung_gpiolib_add_2bit_chips(s5p6450_gpios_2bit,
-                                ARRAY_SIZE(s5p6450_gpios_2bit), NULL, 0x0);
-                samsung_gpiolib_add_4bit_chips(s5p6450_gpios_4bit,
-                                ARRAY_SIZE(s5p6450_gpios_4bit), S5P_VA_GPIO);
-                samsung_gpiolib_add_4bit2_chips(s5p6450_gpios_4bit2,
-                                ARRAY_SIZE(s5p6450_gpios_4bit2));
-                s5p64x0_gpiolib_add_rbank(s5p6450_gpios_rbank,
-                                ARRAY_SIZE(s5p6450_gpios_rbank));
-        } else if (soc_is_s5pc100()) {
-                group = 0;
-                chip = s5pc100_gpios_4bit;
-                nr_chips = ARRAY_SIZE(s5pc100_gpios_4bit);
-
-                for (i = 0; i < nr_chips; i++, chip++) {
-                        if (!chip->config) {
-                                chip->config = &samsung_gpio_cfgs[3];
-                                chip->group = group++;
-                        }
-                }
-                samsung_gpiolib_add_4bit_chips(s5pc100_gpios_4bit, nr_chips, S5P_VA_GPIO);
-#if defined(CONFIG_CPU_S5PC100) && defined(CONFIG_S5P_GPIO_INT)
-                s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
-#endif
         } else if (soc_is_s5pv210()) {
                 group = 0;
                 chip = s5pv210_gpios_4bit;
diff --git a/drivers/gpu/drm/tegra/gr3d.c b/drivers/gpu/drm/tegra/gr3d.c
index 2bea2b2d204e..0b3f2b977ba0 100644
--- a/drivers/gpu/drm/tegra/gr3d.c
+++ b/drivers/gpu/drm/tegra/gr3d.c
@@ -12,7 +12,8 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/reset.h>
-#include <linux/tegra-powergate.h>
+
+#include <soc/tegra/pmc.h>
 
 #include "drm.h"
 #include "gem.h"
diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c
index 0410e467b828..7829e81f065d 100644
--- a/drivers/gpu/drm/tegra/sor.c
+++ b/drivers/gpu/drm/tegra/sor.c
@@ -11,7 +11,8 @@
 #include <linux/io.h>
 #include <linux/platform_device.h>
 #include <linux/reset.h>
-#include <linux/tegra-powergate.h>
+
+#include <soc/tegra/pmc.h>
 
 #include <drm/drm_dp_helper.h>
 
diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c
index 792da5ea6d12..3ded3894623c 100644
--- a/drivers/iommu/tegra-smmu.c
+++ b/drivers/iommu/tegra-smmu.c
@@ -35,7 +35,8 @@
 #include <linux/of_iommu.h>
 #include <linux/debugfs.h>
 #include <linux/seq_file.h>
-#include <linux/tegra-ahb.h>
+
+#include <soc/tegra/ahb.h>
 
 #include <asm/page.h>
 #include <asm/cacheflush.h>
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 4e230e7c76ee..b8632bf9a7f3 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -28,7 +28,6 @@ config ARM_VIC
 config ARM_VIC_NR
         int
         default 4 if ARCH_S5PV210
-        default 3 if ARCH_S5PC100
         default 2
         depends on ARM_VIC
         help
diff --git a/drivers/misc/fuse/Makefile b/drivers/misc/fuse/Makefile
new file mode 100644
index 000000000000..0679c4febc89
--- /dev/null
+++ b/drivers/misc/fuse/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_ARCH_TEGRA)        += tegra/
diff --git a/drivers/mtd/onenand/Kconfig b/drivers/mtd/onenand/Kconfig
index ab2607273e80..dcae2f6a2b11 100644
--- a/drivers/mtd/onenand/Kconfig
+++ b/drivers/mtd/onenand/Kconfig
@@ -32,10 +32,10 @@ config MTD_ONENAND_OMAP2
 
 config MTD_ONENAND_SAMSUNG
         tristate "OneNAND on Samsung SOC controller support"
-        depends on ARCH_S3C64XX || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS4
+        depends on ARCH_S3C64XX || ARCH_S5PV210 || ARCH_EXYNOS4
         help
           Support for a OneNAND flash device connected to an Samsung SOC.
-          S3C64XX/S5PC100 use command mapping method.
+          S3C64XX uses command mapping method.
           S5PC110/S5PC210 use generic OneNAND method.
 
 config MTD_ONENAND_OTP
diff --git a/drivers/mtd/onenand/samsung.c b/drivers/mtd/onenand/samsung.c
index efb819c3df2f..19cfb97adbc0 100644
--- a/drivers/mtd/onenand/samsung.c
+++ b/drivers/mtd/onenand/samsung.c
@@ -10,7 +10,7 @@
  * published by the Free Software Foundation.
  *
  * Implementation:
- *      S3C64XX and S5PC100: emulate the pseudo BufferRAM
+ *      S3C64XX: emulate the pseudo BufferRAM
  *      S5PC110: use DMA
  */
 
@@ -32,7 +32,6 @@
 enum soc_type {
         TYPE_S3C6400,
         TYPE_S3C6410,
-        TYPE_S5PC100,
         TYPE_S5PC110,
 };
 
@@ -59,7 +58,6 @@ enum soc_type {
 #define MAP_11                          (0x3)
 
 #define S3C64XX_CMD_MAP_SHIFT           24
-#define S5PC100_CMD_MAP_SHIFT           26
 
 #define S3C6400_FBA_SHIFT               10
 #define S3C6400_FPA_SHIFT               4
@@ -69,10 +67,6 @@ enum soc_type {
 #define S3C6410_FPA_SHIFT               6
 #define S3C6410_FSA_SHIFT               4
 
-#define S5PC100_FBA_SHIFT               13
-#define S5PC100_FPA_SHIFT               7
-#define S5PC100_FSA_SHIFT               5
-
 /* S5PC110 specific definitions */
 #define S5PC110_DMA_SRC_ADDR            0x400
 #define S5PC110_DMA_SRC_CFG             0x404
@@ -195,11 +189,6 @@ static unsigned int s3c64xx_cmd_map(unsigned type, unsigned val)
         return (type << S3C64XX_CMD_MAP_SHIFT) | val;
 }
 
-static unsigned int s5pc1xx_cmd_map(unsigned type, unsigned val)
-{
-        return (type << S5PC100_CMD_MAP_SHIFT) | val;
-}
-
 static unsigned int s3c6400_mem_addr(int fba, int fpa, int fsa)
 {
         return (fba << S3C6400_FBA_SHIFT) | (fpa << S3C6400_FPA_SHIFT) |
@@ -212,12 +201,6 @@ static unsigned int s3c6410_mem_addr(int fba, int fpa, int fsa)
                 (fsa << S3C6410_FSA_SHIFT);
 }
 
-static unsigned int s5pc100_mem_addr(int fba, int fpa, int fsa)
-{
-        return (fba << S5PC100_FBA_SHIFT) | (fpa << S5PC100_FPA_SHIFT) |
-                (fsa << S5PC100_FSA_SHIFT);
-}
-
 static void s3c_onenand_reset(void)
 {
         unsigned long timeout = 0x10000;
@@ -835,9 +818,6 @@ static void s3c_onenand_setup(struct mtd_info *mtd)
         } else if (onenand->type == TYPE_S3C6410) {
                 onenand->mem_addr = s3c6410_mem_addr;
                 onenand->cmd_map = s3c64xx_cmd_map;
-        } else if (onenand->type == TYPE_S5PC100) {
-                onenand->mem_addr = s5pc100_mem_addr;
-                onenand->cmd_map = s5pc1xx_cmd_map;
         } else if (onenand->type == TYPE_S5PC110) {
                 /* Use generic onenand functions */
                 this->read_bufferram = s5pc110_read_bufferram;
@@ -1111,9 +1091,6 @@ static struct platform_device_id s3c_onenand_driver_ids[] = {
                 .name           = "s3c6410-onenand",
                 .driver_data    = TYPE_S3C6410,
         }, {
-                .name           = "s5pc100-onenand",
-                .driver_data    = TYPE_S5PC100,
-        }, {
                 .name           = "s5pc110-onenand",
                 .driver_data    = TYPE_S5PC110,
         }, { },
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index c284e841e3ea..60a7299e9632 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -41,11 +41,12 @@
 #include <linux/reset.h>
 #include <linux/sizes.h>
 #include <linux/slab.h>
-#include <linux/tegra-cpuidle.h>
-#include <linux/tegra-powergate.h>
 #include <linux/vmalloc.h>
 #include <linux/regulator/consumer.h>
 
+#include <soc/tegra/cpuidle.h>
+#include <soc/tegra/pmc.h>
+
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
 #include <asm/mach/pci.h>
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 0f7c44793b29..3b1b95d932d1 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -3,3 +3,4 @@
 #
 
 obj-$(CONFIG_ARCH_QCOM)         += qcom/
+obj-$(CONFIG_ARCH_TEGRA)        += tegra/
diff --git a/drivers/soc/tegra/Makefile b/drivers/soc/tegra/Makefile
new file mode 100644
index 000000000000..cdaad9d53a05
--- /dev/null
+++ b/drivers/soc/tegra/Makefile
@@ -0,0 +1,4 @@
+obj-$(CONFIG_ARCH_TEGRA) += fuse/
+
+obj-$(CONFIG_ARCH_TEGRA) += common.o
+obj-$(CONFIG_ARCH_TEGRA) += pmc.o
diff --git a/drivers/soc/tegra/common.c b/drivers/soc/tegra/common.c
new file mode 100644
index 000000000000..a71cb74f3674
--- /dev/null
+++ b/drivers/soc/tegra/common.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/of.h>
+
+#include <soc/tegra/common.h>
+
+static const struct of_device_id tegra_machine_match[] = {
+        { .compatible = "nvidia,tegra20", },
+        { .compatible = "nvidia,tegra30", },
+        { .compatible = "nvidia,tegra114", },
+        { .compatible = "nvidia,tegra124", },
+        { }
+};
+
+bool soc_is_tegra(void)
+{
+        struct device_node *root;
+
+        root = of_find_node_by_path("/");
+        if (!root)
+                return false;
+
+        return of_match_node(tegra_machine_match, root) != NULL;
+}
diff --git a/drivers/soc/tegra/fuse/Makefile b/drivers/soc/tegra/fuse/Makefile
new file mode 100644
index 000000000000..3af357da91f3
--- /dev/null
+++ b/drivers/soc/tegra/fuse/Makefile
@@ -0,0 +1,8 @@
+obj-y                                   += fuse-tegra.o
+obj-y                                   += fuse-tegra30.o
+obj-y                                   += tegra-apbmisc.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += fuse-tegra20.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += speedo-tegra20.o
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += speedo-tegra30.o
+obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += speedo-tegra114.o
+obj-$(CONFIG_ARCH_TEGRA_124_SOC)        += speedo-tegra124.o
diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c
new file mode 100644
index 000000000000..11a5043959dc
--- /dev/null
+++ b/drivers/soc/tegra/fuse/fuse-tegra.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/kobject.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#include <soc/tegra/common.h>
+#include <soc/tegra/fuse.h>
+
+#include "fuse.h"
+
+static u32 (*fuse_readl)(const unsigned int offset);
+static int fuse_size;
+struct tegra_sku_info tegra_sku_info;
+
+static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
+        [TEGRA_REVISION_UNKNOWN] = "unknown",
+        [TEGRA_REVISION_A01]     = "A01",
+        [TEGRA_REVISION_A02]     = "A02",
+        [TEGRA_REVISION_A03]     = "A03",
+        [TEGRA_REVISION_A03p]    = "A03 prime",
+        [TEGRA_REVISION_A04]     = "A04",
+};
+
+static u8 fuse_readb(const unsigned int offset)
+{
+        u32 val;
+
+        val = fuse_readl(round_down(offset, 4));
+        val >>= (offset % 4) * 8;
+        val &= 0xff;
+
+        return val;
+}
+
+static ssize_t fuse_read(struct file *fd, struct kobject *kobj,
+                        struct bin_attribute *attr, char *buf,
+                        loff_t pos, size_t size)
+{
+        int i;
+
+        if (pos < 0 || pos >= fuse_size)
+                return 0;
+
+        if (size > fuse_size - pos)
+                size = fuse_size - pos;
+
+        for (i = 0; i < size; i++)
+                buf[i] = fuse_readb(pos + i);
+
+        return i;
+}
+
+static struct bin_attribute fuse_bin_attr = {
+        .attr = { .name = "fuse", .mode = S_IRUGO, },
+        .read = fuse_read,
+};
+
+static const struct of_device_id car_match[] __initconst = {
+        { .compatible = "nvidia,tegra20-car", },
+        { .compatible = "nvidia,tegra30-car", },
+        { .compatible = "nvidia,tegra114-car", },
+        { .compatible = "nvidia,tegra124-car", },
+        {},
+};
+
+static void tegra_enable_fuse_clk(void __iomem *base)
+{
+        u32 reg;
+
+        reg = readl_relaxed(base + 0x48);
+        reg |= 1 << 28;
+        writel(reg, base + 0x48);
+
+        /*
+         * Enable FUSE clock. This needs to be hardcoded because the clock
+         * subsystem is not active during early boot.
+         */
+        reg = readl(base + 0x14);
+        reg |= 1 << 7;
+        writel(reg, base + 0x14);
+}
+
+int tegra_fuse_readl(unsigned long offset, u32 *value)
+{
+        if (!fuse_readl)
+                return -EPROBE_DEFER;
+
+        *value = fuse_readl(offset);
+
+        return 0;
+}
+EXPORT_SYMBOL(tegra_fuse_readl);
+
+int tegra_fuse_create_sysfs(struct device *dev, int size,
+                     u32 (*readl)(const unsigned int offset))
+{
+        if (fuse_size)
+                return -ENODEV;
+
+        fuse_bin_attr.size = size;
+        fuse_bin_attr.read = fuse_read;
+
+        fuse_size = size;
+        fuse_readl = readl;
+
+        return device_create_bin_file(dev, &fuse_bin_attr);
+}
+
+static int __init tegra_init_fuse(void)
+{
+        struct device_node *np;
+        void __iomem *car_base;
+
+        if (!soc_is_tegra())
+                return 0;
+
+        tegra_init_apbmisc();
+
+        np = of_find_matching_node(NULL, car_match);
+        car_base = of_iomap(np, 0);
+        if (car_base) {
+                tegra_enable_fuse_clk(car_base);
+                iounmap(car_base);
+        } else {
+                pr_err("Could not enable fuse clk. ioremap tegra car failed.\n");
+                return -ENXIO;
+        }
+
+        if (tegra_get_chip_id() == TEGRA20)
+                tegra20_init_fuse_early();
+        else
+                tegra30_init_fuse_early();
+
+        pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
+                tegra_revision_name[tegra_sku_info.revision],
+                tegra_sku_info.sku_id, tegra_sku_info.cpu_process_id,
+                tegra_sku_info.core_process_id);
+        pr_debug("Tegra CPU Speedo ID %d, Soc Speedo ID %d\n",
+                tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id);
+
+        return 0;
+}
+early_initcall(tegra_init_fuse);
diff --git a/drivers/soc/tegra/fuse/fuse-tegra20.c b/drivers/soc/tegra/fuse/fuse-tegra20.c
new file mode 100644
index 000000000000..7cb63ab6aac2
--- /dev/null
+++ b/drivers/soc/tegra/fuse/fuse-tegra20.c
@@ -0,0 +1,215 @@
+/*
+ * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Based on drivers/misc/eeprom/sunxi_sid.c
+ */
+
+#include <linux/device.h>
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/kobject.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/random.h>
+
+#include <soc/tegra/fuse.h>
+
+#include "fuse.h"
+
+#define FUSE_BEGIN      0x100
+#define FUSE_SIZE       0x1f8
+#define FUSE_UID_LOW    0x08
+#define FUSE_UID_HIGH   0x0c
+
+static phys_addr_t fuse_phys;
+static struct clk *fuse_clk;
+static void __iomem __initdata *fuse_base;
+
+static DEFINE_MUTEX(apb_dma_lock);
+static DECLARE_COMPLETION(apb_dma_wait);
+static struct dma_chan *apb_dma_chan;
+static struct dma_slave_config dma_sconfig;
+static u32 *apb_buffer;
+static dma_addr_t apb_buffer_phys;
+
+static void apb_dma_complete(void *args)
+{
+        complete(&apb_dma_wait);
+}
+
+static u32 tegra20_fuse_readl(const unsigned int offset)
+{
+        int ret;
+        u32 val = 0;
+        struct dma_async_tx_descriptor *dma_desc;
+
+        mutex_lock(&apb_dma_lock);
+
+        dma_sconfig.src_addr = fuse_phys + FUSE_BEGIN + offset;
+        ret = dmaengine_slave_config(apb_dma_chan, &dma_sconfig);
+        if (ret)
+                goto out;
+
+        dma_desc = dmaengine_prep_slave_single(apb_dma_chan, apb_buffer_phys,
+                        sizeof(u32), DMA_DEV_TO_MEM,
+                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+        if (!dma_desc)
+                goto out;
+
+        dma_desc->callback = apb_dma_complete;
+        dma_desc->callback_param = NULL;
+
+        reinit_completion(&apb_dma_wait);
+
+        clk_prepare_enable(fuse_clk);
+
+        dmaengine_submit(dma_desc);
+        dma_async_issue_pending(apb_dma_chan);
+        ret = wait_for_completion_timeout(&apb_dma_wait, msecs_to_jiffies(50));
+
+        if (WARN(ret == 0, "apb read dma timed out"))
+                dmaengine_terminate_all(apb_dma_chan);
+        else
+                val = *apb_buffer;
+
+        clk_disable_unprepare(fuse_clk);
+out:
+        mutex_unlock(&apb_dma_lock);
+
+        return val;
+}
+
+static const struct of_device_id tegra20_fuse_of_match[] = {
+        { .compatible = "nvidia,tegra20-efuse" },
+        {},
+};
+
+static int apb_dma_init(void)
+{
+        dma_cap_mask_t mask;
+
+        dma_cap_zero(mask);
+        dma_cap_set(DMA_SLAVE, mask);
+        apb_dma_chan = dma_request_channel(mask, NULL, NULL);
+        if (!apb_dma_chan)
+                return -EPROBE_DEFER;
+
+        apb_buffer = dma_alloc_coherent(NULL, sizeof(u32), &apb_buffer_phys,
+                                        GFP_KERNEL);
+        if (!apb_buffer) {
+                dma_release_channel(apb_dma_chan);
+                return -ENOMEM;
+        }
+
+        dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+        dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+        dma_sconfig.src_maxburst = 1;
+        dma_sconfig.dst_maxburst = 1;
+
+        return 0;
+}
+
+static int tegra20_fuse_probe(struct platform_device *pdev)
+{
+        struct resource *res;
+        int err;
+
+        fuse_clk = devm_clk_get(&pdev->dev, NULL);
+        if (IS_ERR(fuse_clk)) {
+                dev_err(&pdev->dev, "missing clock");
+                return PTR_ERR(fuse_clk);
+        }
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res)
+                return -EINVAL;
+        fuse_phys = res->start;
+
+        err = apb_dma_init();
+        if (err)
+                return err;
+
+        if (tegra_fuse_create_sysfs(&pdev->dev, FUSE_SIZE, tegra20_fuse_readl))
+                return -ENODEV;
+
+        dev_dbg(&pdev->dev, "loaded\n");
+
+        return 0;
+}
+
+static struct platform_driver tegra20_fuse_driver = {
+        .probe = tegra20_fuse_probe,
+        .driver = {
+                .name = "tegra20_fuse",
+                .owner = THIS_MODULE,
+                .of_match_table = tegra20_fuse_of_match,
+        }
+};
+
+static int __init tegra20_fuse_init(void)
+{
+        return platform_driver_register(&tegra20_fuse_driver);
+}
+postcore_initcall(tegra20_fuse_init);
+
+/* Early boot code. This code is called before the devices are created */
+
+u32 __init tegra20_fuse_early(const unsigned int offset)
+{
+        return readl_relaxed(fuse_base + FUSE_BEGIN + offset);
+}
+
+bool __init tegra20_spare_fuse_early(int spare_bit)
+{
+        u32 offset = spare_bit * 4;
+        bool value;
+
+        value = tegra20_fuse_early(offset + 0x100);
+
+        return value;
+}
+
+static void __init tegra20_fuse_add_randomness(void)
+{
+        u32 randomness[7];
+
+        randomness[0] = tegra_sku_info.sku_id;
+        randomness[1] = tegra_read_straps();
+        randomness[2] = tegra_read_chipid();
+        randomness[3] = tegra_sku_info.cpu_process_id << 16;
+        randomness[3] |= tegra_sku_info.core_process_id;
+        randomness[4] = tegra_sku_info.cpu_speedo_id << 16;
+        randomness[4] |= tegra_sku_info.soc_speedo_id;
+        randomness[5] = tegra20_fuse_early(FUSE_UID_LOW);
+        randomness[6] = tegra20_fuse_early(FUSE_UID_HIGH);
+
+        add_device_randomness(randomness, sizeof(randomness));
+}
+
+void __init tegra20_init_fuse_early(void)
+{
+        fuse_base = ioremap(TEGRA_FUSE_BASE, TEGRA_FUSE_SIZE);
+
+        tegra_init_revision();
+        tegra20_init_speedo_data(&tegra_sku_info);
+        tegra20_fuse_add_randomness();
+
+        iounmap(fuse_base);
+}
diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse/fuse-tegra30.c
new file mode 100644
index 000000000000..5999cf34ab70
--- /dev/null
+++ b/drivers/soc/tegra/fuse/fuse-tegra30.c
@@ -0,0 +1,224 @@
+/*
+ * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/random.h>
+
+#include <soc/tegra/fuse.h>
+
+#include "fuse.h"
+
+#define FUSE_BEGIN      0x100
+
+/* Tegra30 and later */
+#define FUSE_VENDOR_CODE        0x100
+#define FUSE_FAB_CODE           0x104
+#define FUSE_LOT_CODE_0         0x108
+#define FUSE_LOT_CODE_1         0x10c
+#define FUSE_WAFER_ID           0x110
+#define FUSE_X_COORDINATE       0x114
+#define FUSE_Y_COORDINATE       0x118
+
+#define FUSE_HAS_REVISION_INFO  BIT(0)
+
+enum speedo_idx {
+        SPEEDO_TEGRA30 = 0,
+        SPEEDO_TEGRA114,
+        SPEEDO_TEGRA124,
+};
+
+struct tegra_fuse_info {
+        int             size;
+        int             spare_bit;
+        enum speedo_idx speedo_idx;
+};
+
+static void __iomem *fuse_base;
+static struct clk *fuse_clk;
+static struct tegra_fuse_info *fuse_info;
+
+u32 tegra30_fuse_readl(const unsigned int offset)
+{
+        u32 val;
+
+        /*
+         * early in the boot, the fuse clock will be enabled by
+         * tegra_init_fuse()
+         */
+
+        if (fuse_clk)
+                clk_prepare_enable(fuse_clk);
+
+        val = readl_relaxed(fuse_base + FUSE_BEGIN + offset);
+
+        if (fuse_clk)
+                clk_disable_unprepare(fuse_clk);
+
+        return val;
+}
+
+static struct tegra_fuse_info tegra30_info = {
+        .size                   = 0x2a4,
+        .spare_bit              = 0x144,
+        .speedo_idx             = SPEEDO_TEGRA30,
+};
+
+static struct tegra_fuse_info tegra114_info = {
+        .size                   = 0x2a0,
+        .speedo_idx             = SPEEDO_TEGRA114,
+};
+
+static struct tegra_fuse_info tegra124_info = {
+        .size                   = 0x300,
+        .speedo_idx             = SPEEDO_TEGRA124,
+};
+
+static const struct of_device_id tegra30_fuse_of_match[] = {
+        { .compatible = "nvidia,tegra30-efuse", .data = &tegra30_info },
+        { .compatible = "nvidia,tegra114-efuse", .data = &tegra114_info },
+        { .compatible = "nvidia,tegra124-efuse", .data = &tegra124_info },
+        {},
+};
+
+static int tegra30_fuse_probe(struct platform_device *pdev)
+{
+        const struct of_device_id *of_dev_id;
+
+        of_dev_id = of_match_device(tegra30_fuse_of_match, &pdev->dev);
+        if (!of_dev_id)
+                return -ENODEV;
+
+        fuse_clk = devm_clk_get(&pdev->dev, NULL);
+        if (IS_ERR(fuse_clk)) {
+                dev_err(&pdev->dev, "missing clock");
+                return PTR_ERR(fuse_clk);
+        }
+
+        platform_set_drvdata(pdev, NULL);
+
+        if (tegra_fuse_create_sysfs(&pdev->dev, fuse_info->size,
+                                    tegra30_fuse_readl))
+                return -ENODEV;
+
+        dev_dbg(&pdev->dev, "loaded\n");
+
+        return 0;
+}
+
+static struct platform_driver tegra30_fuse_driver = {
+        .probe = tegra30_fuse_probe,
+        .driver = {
+                .name = "tegra_fuse",
+                .owner = THIS_MODULE,
+                .of_match_table = tegra30_fuse_of_match,
+        }
+};
+
+static int __init tegra30_fuse_init(void)
+{
+        return platform_driver_register(&tegra30_fuse_driver);
+}
+postcore_initcall(tegra30_fuse_init);
+
+/* Early boot code. This code is called before the devices are created */
+
+typedef void (*speedo_f)(struct tegra_sku_info *sku_info);
+
+static speedo_f __initdata speedo_tbl[] = {
+        [SPEEDO_TEGRA30]        = tegra30_init_speedo_data,
+        [SPEEDO_TEGRA114]       = tegra114_init_speedo_data,
+        [SPEEDO_TEGRA124]       = tegra124_init_speedo_data,
+};
+
+static void __init tegra30_fuse_add_randomness(void)
+{
+        u32 randomness[12];
+
+        randomness[0] = tegra_sku_info.sku_id;
+        randomness[1] = tegra_read_straps();
+        randomness[2] = tegra_read_chipid();
+        randomness[3] = tegra_sku_info.cpu_process_id << 16;
+        randomness[3] |= tegra_sku_info.core_process_id;
+        randomness[4] = tegra_sku_info.cpu_speedo_id << 16;
+        randomness[4] |= tegra_sku_info.soc_speedo_id;
+        randomness[5] = tegra30_fuse_readl(FUSE_VENDOR_CODE);
+        randomness[6] = tegra30_fuse_readl(FUSE_FAB_CODE);
+        randomness[7] = tegra30_fuse_readl(FUSE_LOT_CODE_0);
+        randomness[8] = tegra30_fuse_readl(FUSE_LOT_CODE_1);
+        randomness[9] = tegra30_fuse_readl(FUSE_WAFER_ID);
+        randomness[10] = tegra30_fuse_readl(FUSE_X_COORDINATE);
+        randomness[11] = tegra30_fuse_readl(FUSE_Y_COORDINATE);
+
+        add_device_randomness(randomness, sizeof(randomness));
+}
+
+static void __init legacy_fuse_init(void)
+{
+        switch (tegra_get_chip_id()) {
+        case TEGRA30:
+                fuse_info = &tegra30_info;
+                break;
+        case TEGRA114:
+                fuse_info = &tegra114_info;
+                break;
+        case TEGRA124:
+                fuse_info = &tegra124_info;
+                break;
+        default:
+                return;
+        }
+
+        fuse_base = ioremap(TEGRA_FUSE_BASE, TEGRA_FUSE_SIZE);
+}
+
+bool __init tegra30_spare_fuse(int spare_bit)
+{
+        u32 offset = fuse_info->spare_bit + spare_bit * 4;
+
+        return tegra30_fuse_readl(offset) & 1;
+}
+
+void __init tegra30_init_fuse_early(void)
+{
+        struct device_node *np;
+        const struct of_device_id *of_match;
+
+        np = of_find_matching_node_and_match(NULL, tegra30_fuse_of_match,
+                                                &of_match);
+        if (np) {
+                fuse_base = of_iomap(np, 0);
+                fuse_info = (struct tegra_fuse_info *)of_match->data;
+        } else
+                legacy_fuse_init();
+
+        if (!fuse_base) {
+                pr_warn("fuse DT node missing and unknown chip id: 0x%02x\n",
+                        tegra_get_chip_id());
+                return;
+        }
+
+        tegra_init_revision();
+        speedo_tbl[fuse_info->speedo_idx](&tegra_sku_info);
+        tegra30_fuse_add_randomness();
+}
diff --git a/drivers/soc/tegra/fuse/fuse.h b/drivers/soc/tegra/fuse/fuse.h
new file mode 100644
index 000000000000..3a398bf3572c
--- /dev/null
+++ b/drivers/soc/tegra/fuse/fuse.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Author:
+ *      Colin Cross <ccross@android.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __DRIVERS_MISC_TEGRA_FUSE_H
+#define __DRIVERS_MISC_TEGRA_FUSE_H
+
+#define TEGRA_FUSE_BASE 0x7000f800
+#define TEGRA_FUSE_SIZE 0x400
+
+int tegra_fuse_create_sysfs(struct device *dev, int size,
+                     u32 (*readl)(const unsigned int offset));
+
+bool tegra30_spare_fuse(int bit);
+u32 tegra30_fuse_readl(const unsigned int offset);
+void tegra30_init_fuse_early(void);
+void tegra_init_revision(void);
+void tegra_init_apbmisc(void);
+
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+void tegra20_init_speedo_data(struct tegra_sku_info *sku_info);
+bool tegra20_spare_fuse_early(int spare_bit);
+void tegra20_init_fuse_early(void);
+u32 tegra20_fuse_early(const unsigned int offset);
+#else
+static inline void tegra20_init_speedo_data(struct tegra_sku_info *sku_info) {}
+static inline bool tegra20_spare_fuse_early(int spare_bit)
+{
+        return false;
+}
+static inline void tegra20_init_fuse_early(void) {}
+static inline u32 tegra20_fuse_early(const unsigned int offset)
+{
+        return 0;
+}
+#endif
+
+
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+void tegra30_init_speedo_data(struct tegra_sku_info *sku_info);
+#else
+static inline void tegra30_init_speedo_data(struct tegra_sku_info *sku_info) {}
+#endif
+
+#ifdef CONFIG_ARCH_TEGRA_114_SOC
+void tegra114_init_speedo_data(struct tegra_sku_info *sku_info);
+#else
+static inline void tegra114_init_speedo_data(struct tegra_sku_info *sku_info) {}
+#endif
+
+#ifdef CONFIG_ARCH_TEGRA_124_SOC
+void tegra124_init_speedo_data(struct tegra_sku_info *sku_info);
+#else
+static inline void tegra124_init_speedo_data(struct tegra_sku_info *sku_info) {}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/tegra114_speedo.c b/drivers/soc/tegra/fuse/speedo-tegra114.c
index 5218d4853cd3..2a6ca036f09f 100644
--- a/arch/arm/mach-tegra/tegra114_speedo.c
+++ b/drivers/soc/tegra/fuse/speedo-tegra114.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -14,13 +14,16 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#include <linux/kernel.h>
 #include <linux/bug.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+
+#include <soc/tegra/fuse.h>
 
 #include "fuse.h"
 
-#define CORE_PROCESS_CORNERS_NUM        2
-#define CPU_PROCESS_CORNERS_NUM         2
+#define CORE_PROCESS_CORNERS    2
+#define CPU_PROCESS_CORNERS     2
 
 enum {
         THRESHOLD_INDEX_0,
@@ -28,54 +31,57 @@ enum {
         THRESHOLD_INDEX_COUNT,
 };
 
-static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = {
+static const u32 __initconst core_process_speedos[][CORE_PROCESS_CORNERS] = {
         {1123,     UINT_MAX},
         {0,        UINT_MAX},
 };
 
-static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = {
+static const u32 __initconst cpu_process_speedos[][CPU_PROCESS_CORNERS] = {
         {1695,     UINT_MAX},
         {0,        UINT_MAX},
 };
 
-static void rev_sku_to_speedo_ids(int rev, int sku, int *threshold)
+static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info,
+                                         int *threshold)
 {
         u32 tmp;
+        u32 sku = sku_info->sku_id;
+        enum tegra_revision rev = sku_info->revision;
 
         switch (sku) {
         case 0x00:
         case 0x10:
         case 0x05:
         case 0x06:
-                tegra_cpu_speedo_id = 1;
-                tegra_soc_speedo_id = 0;
+                sku_info->cpu_speedo_id = 1;
+                sku_info->soc_speedo_id = 0;
                 *threshold = THRESHOLD_INDEX_0;
                 break;
 
         case 0x03:
         case 0x04:
-                tegra_cpu_speedo_id = 2;
-                tegra_soc_speedo_id = 1;
+                sku_info->cpu_speedo_id = 2;
+                sku_info->soc_speedo_id = 1;
                 *threshold = THRESHOLD_INDEX_1;
                 break;
 
         default:
-                pr_err("Tegra114 Unknown SKU %d\n", sku);
-                tegra_cpu_speedo_id = 0;
-                tegra_soc_speedo_id = 0;
+                pr_err("Tegra Unknown SKU %d\n", sku);
+                sku_info->cpu_speedo_id = 0;
+                sku_info->soc_speedo_id = 0;
                 *threshold = THRESHOLD_INDEX_0;
                 break;
         }
 
         if (rev == TEGRA_REVISION_A01) {
-                tmp = tegra_fuse_readl(0x270) << 1;
-                tmp |= tegra_fuse_readl(0x26c);
+                tmp = tegra30_fuse_readl(0x270) << 1;
+                tmp |= tegra30_fuse_readl(0x26c);
                 if (!tmp)
-                        tegra_cpu_speedo_id = 0;
+                        sku_info->cpu_speedo_id = 0;
         }
 }
 
-void tegra114_init_speedo_data(void)
+void __init tegra114_init_speedo_data(struct tegra_sku_info *sku_info)
 {
         u32 cpu_speedo_val;
         u32 core_speedo_val;
@@ -87,18 +93,18 @@ void tegra114_init_speedo_data(void)
         BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) !=
                         THRESHOLD_INDEX_COUNT);
 
-        rev_sku_to_speedo_ids(tegra_revision, tegra_sku_id, &threshold);
+        rev_sku_to_speedo_ids(sku_info, &threshold);
 
-        cpu_speedo_val = tegra_fuse_readl(0x12c) + 1024;
-        core_speedo_val = tegra_fuse_readl(0x134);
+        cpu_speedo_val = tegra30_fuse_readl(0x12c) + 1024;
+        core_speedo_val = tegra30_fuse_readl(0x134);
 
-        for (i = 0; i < CPU_PROCESS_CORNERS_NUM; i++)
+        for (i = 0; i < CPU_PROCESS_CORNERS; i++)
                 if (cpu_speedo_val < cpu_process_speedos[threshold][i])
                         break;
-        tegra_cpu_process_id = i;
+        sku_info->cpu_process_id = i;
 
-        for (i = 0; i < CORE_PROCESS_CORNERS_NUM; i++)
+        for (i = 0; i < CORE_PROCESS_CORNERS; i++)
                 if (core_speedo_val < core_process_speedos[threshold][i])
                         break;
-        tegra_core_process_id = i;
+        sku_info->core_process_id = i;
 }
diff --git a/drivers/soc/tegra/fuse/speedo-tegra124.c b/drivers/soc/tegra/fuse/speedo-tegra124.c
new file mode 100644
index 000000000000..46362387d974
--- /dev/null
+++ b/drivers/soc/tegra/fuse/speedo-tegra124.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/bug.h>
+
+#include <soc/tegra/fuse.h>
+
+#include "fuse.h"
+
+#define CPU_PROCESS_CORNERS     2
+#define GPU_PROCESS_CORNERS     2
+#define CORE_PROCESS_CORNERS    2
+
+#define FUSE_CPU_SPEEDO_0       0x14
+#define FUSE_CPU_SPEEDO_1       0x2c
+#define FUSE_CPU_SPEEDO_2       0x30
+#define FUSE_SOC_SPEEDO_0       0x34
+#define FUSE_SOC_SPEEDO_1       0x38
+#define FUSE_SOC_SPEEDO_2       0x3c
+#define FUSE_CPU_IDDQ           0x18
+#define FUSE_SOC_IDDQ           0x40
+#define FUSE_GPU_IDDQ           0x128
+#define FUSE_FT_REV             0x28
+
+enum {
+        THRESHOLD_INDEX_0,
+        THRESHOLD_INDEX_1,
+        THRESHOLD_INDEX_COUNT,
+};
+
+static const u32 __initconst cpu_process_speedos[][CPU_PROCESS_CORNERS] = {
+        {2190,  UINT_MAX},
+        {0,     UINT_MAX},
+};
+
+static const u32 __initconst gpu_process_speedos[][GPU_PROCESS_CORNERS] = {
+        {1965,  UINT_MAX},
+        {0,     UINT_MAX},
+};
+
+static const u32 __initconst core_process_speedos[][CORE_PROCESS_CORNERS] = {
+        {2101,  UINT_MAX},
+        {0,     UINT_MAX},
+};
+
+static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info,
+                                         int *threshold)
+{
+        int sku = sku_info->sku_id;
+
+        /* Assign to default */
+        sku_info->cpu_speedo_id = 0;
+        sku_info->soc_speedo_id = 0;
+        sku_info->gpu_speedo_id = 0;
+        *threshold = THRESHOLD_INDEX_0;
+
+        switch (sku) {
+        case 0x00: /* Eng sku */
+        case 0x0F:
+        case 0x23:
+                /* Using the default */
+                break;
+        case 0x83:
+                sku_info->cpu_speedo_id = 2;
+                break;
+
+        case 0x1F:
+        case 0x87:
+        case 0x27:
+                sku_info->cpu_speedo_id = 2;
+                sku_info->soc_speedo_id = 0;
+                sku_info->gpu_speedo_id = 1;
+                *threshold = THRESHOLD_INDEX_0;
+                break;
+        case 0x81:
+        case 0x21:
+        case 0x07:
+                sku_info->cpu_speedo_id = 1;
+                sku_info->soc_speedo_id = 1;
+                sku_info->gpu_speedo_id = 1;
+                *threshold = THRESHOLD_INDEX_1;
+                break;
+        case 0x49:
+        case 0x4A:
+        case 0x48:
+                sku_info->cpu_speedo_id = 4;
+                sku_info->soc_speedo_id = 2;
+                sku_info->gpu_speedo_id = 3;
+                *threshold = THRESHOLD_INDEX_1;
+                break;
+        default:
+                pr_err("Tegra Unknown SKU %d\n", sku);
+                /* Using the default for the error case */
+                break;
+        }
+}
+
+void __init tegra124_init_speedo_data(struct tegra_sku_info *sku_info)
+{
+        int i, threshold, cpu_speedo_0_value, soc_speedo_0_value;
+        int cpu_iddq_value, gpu_iddq_value, soc_iddq_value;
+
+        BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
+                        THRESHOLD_INDEX_COUNT);
+        BUILD_BUG_ON(ARRAY_SIZE(gpu_process_speedos) !=
+                        THRESHOLD_INDEX_COUNT);
+        BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) !=
+                        THRESHOLD_INDEX_COUNT);
+
+        cpu_speedo_0_value = tegra30_fuse_readl(FUSE_CPU_SPEEDO_0);
+
+        /* GPU Speedo is stored in CPU_SPEEDO_2 */
+        sku_info->gpu_speedo_value = tegra30_fuse_readl(FUSE_CPU_SPEEDO_2);
+
+        soc_speedo_0_value = tegra30_fuse_readl(FUSE_SOC_SPEEDO_0);
+
+        cpu_iddq_value = tegra30_fuse_readl(FUSE_CPU_IDDQ);
+        soc_iddq_value = tegra30_fuse_readl(FUSE_SOC_IDDQ);
+        gpu_iddq_value = tegra30_fuse_readl(FUSE_GPU_IDDQ);
+
+        sku_info->cpu_speedo_value = cpu_speedo_0_value;
+
+        if (sku_info->cpu_speedo_value == 0) {
+                pr_warn("Tegra Warning: Speedo value not fused.\n");
+                WARN_ON(1);
+                return;
+        }
+
+        rev_sku_to_speedo_ids(sku_info, &threshold);
+
+        sku_info->cpu_iddq_value = tegra30_fuse_readl(FUSE_CPU_IDDQ);
+
+        for (i = 0; i < GPU_PROCESS_CORNERS; i++)
+                if (sku_info->gpu_speedo_value <
+                        gpu_process_speedos[threshold][i])
+                        break;
+        sku_info->gpu_process_id = i;
+
+        for (i = 0; i < CPU_PROCESS_CORNERS; i++)
+                if (sku_info->cpu_speedo_value <
+                        cpu_process_speedos[threshold][i])
+                                break;
+        sku_info->cpu_process_id = i;
+
+        for (i = 0; i < CORE_PROCESS_CORNERS; i++)
+                if (soc_speedo_0_value <
+                        core_process_speedos[threshold][i])
+                        break;
+        sku_info->core_process_id = i;
+
+        pr_debug("Tegra GPU Speedo ID=%d, Speedo Value=%d\n",
+                 sku_info->gpu_speedo_id, sku_info->gpu_speedo_value);
+}
diff --git a/arch/arm/mach-tegra/tegra20_speedo.c b/drivers/soc/tegra/fuse/speedo-tegra20.c
index fa6eb570623f..eff1b63f330d 100644
--- a/arch/arm/mach-tegra/tegra20_speedo.c
+++ b/drivers/soc/tegra/fuse/speedo-tegra20.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2012-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -14,8 +14,11 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#include <linux/kernel.h>
 #include <linux/bug.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+
+#include <soc/tegra/fuse.h>
 
 #include "fuse.h"
 
@@ -47,19 +50,19 @@ enum {
         SPEEDO_ID_COUNT,
 };
 
-static const u32 cpu_process_speedos[][PROCESS_CORNERS_NUM] = {
+static const u32 __initconst cpu_process_speedos[][PROCESS_CORNERS_NUM] = {
         {315, 366, 420, UINT_MAX},
         {303, 368, 419, UINT_MAX},
         {316, 331, 383, UINT_MAX},
 };
 
-static const u32 core_process_speedos[][PROCESS_CORNERS_NUM] = {
+static const u32 __initconst core_process_speedos[][PROCESS_CORNERS_NUM] = {
         {165, 195, 224, UINT_MAX},
         {165, 195, 224, UINT_MAX},
         {165, 195, 224, UINT_MAX},
 };
 
-void tegra20_init_speedo_data(void)
+void __init tegra20_init_speedo_data(struct tegra_sku_info *sku_info)
 {
         u32 reg;
         u32 val;
@@ -68,42 +71,40 @@ void tegra20_init_speedo_data(void)
         BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) != SPEEDO_ID_COUNT);
         BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) != SPEEDO_ID_COUNT);
 
-        if (SPEEDO_ID_SELECT_0(tegra_revision))
-                tegra_soc_speedo_id = SPEEDO_ID_0;
-        else if (SPEEDO_ID_SELECT_1(tegra_sku_id))
-                tegra_soc_speedo_id = SPEEDO_ID_1;
+        if (SPEEDO_ID_SELECT_0(sku_info->revision))
+                sku_info->soc_speedo_id = SPEEDO_ID_0;
+        else if (SPEEDO_ID_SELECT_1(sku_info->sku_id))
+                sku_info->soc_speedo_id = SPEEDO_ID_1;
         else
-                tegra_soc_speedo_id = SPEEDO_ID_2;
+                sku_info->soc_speedo_id = SPEEDO_ID_2;
 
         val = 0;
         for (i = CPU_SPEEDO_MSBIT; i >= CPU_SPEEDO_LSBIT; i--) {
-                reg = tegra_spare_fuse(i) |
-                        tegra_spare_fuse(i + CPU_SPEEDO_REDUND_OFFS);
+                reg = tegra20_spare_fuse_early(i) |
+                        tegra20_spare_fuse_early(i + CPU_SPEEDO_REDUND_OFFS);
                 val = (val << 1) | (reg & 0x1);
         }
         val = val * SPEEDO_MULT;
-        pr_debug("%s CPU speedo value %u\n", __func__, val);
+        pr_debug("Tegra CPU speedo value %u\n", val);
 
         for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) {
-                if (val <= cpu_process_speedos[tegra_soc_speedo_id][i])
+                if (val <= cpu_process_speedos[sku_info->soc_speedo_id][i])
                         break;
         }
-        tegra_cpu_process_id = i;
+        sku_info->cpu_process_id = i;
 
         val = 0;
         for (i = CORE_SPEEDO_MSBIT; i >= CORE_SPEEDO_LSBIT; i--) {
-                reg = tegra_spare_fuse(i) |
-                        tegra_spare_fuse(i + CORE_SPEEDO_REDUND_OFFS);
+                reg = tegra20_spare_fuse_early(i) |
+                        tegra20_spare_fuse_early(i + CORE_SPEEDO_REDUND_OFFS);
                 val = (val << 1) | (reg & 0x1);
         }
         val = val * SPEEDO_MULT;
-        pr_debug("%s Core speedo value %u\n", __func__, val);
+        pr_debug("Core speedo value %u\n", val);
 
         for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) {
-                if (val <= core_process_speedos[tegra_soc_speedo_id][i])
+                if (val <= core_process_speedos[sku_info->soc_speedo_id][i])
                         break;
         }
-        tegra_core_process_id = i;
-
-        pr_info("Tegra20 Soc Speedo ID %d", tegra_soc_speedo_id);
+        sku_info->core_process_id = i;
 }
diff --git a/arch/arm/mach-tegra/tegra30_speedo.c b/drivers/soc/tegra/fuse/speedo-tegra30.c
index 125cb16424a6..b17f0dcdfebe 100644
--- a/arch/arm/mach-tegra/tegra30_speedo.c
+++ b/drivers/soc/tegra/fuse/speedo-tegra30.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2012-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -14,17 +14,20 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#include <linux/kernel.h>
 #include <linux/bug.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+
+#include <soc/tegra/fuse.h>
 
 #include "fuse.h"
 
-#define CORE_PROCESS_CORNERS_NUM        1
-#define CPU_PROCESS_CORNERS_NUM         6
+#define CORE_PROCESS_CORNERS    1
+#define CPU_PROCESS_CORNERS     6
 
-#define FUSE_SPEEDO_CALIB_0     0x114
-#define FUSE_PACKAGE_INFO       0X1FC
-#define FUSE_TEST_PROG_VER      0X128
+#define FUSE_SPEEDO_CALIB_0     0x14
+#define FUSE_PACKAGE_INFO       0XFC
+#define FUSE_TEST_PROG_VER      0X28
 
 #define G_SPEEDO_BIT_MINUS1     58
 #define G_SPEEDO_BIT_MINUS1_R   59
@@ -51,7 +54,7 @@ enum {
         THRESHOLD_INDEX_COUNT,
 };
 
-static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = {
+static const u32 __initconst core_process_speedos[][CORE_PROCESS_CORNERS] = {
         {180},
         {170},
         {195},
@@ -66,7 +69,7 @@ static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = {
         {180},
 };
 
-static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = {
+static const u32 __initconst cpu_process_speedos[][CPU_PROCESS_CORNERS] = {
         {306, 338, 360, 376, UINT_MAX},
         {295, 336, 358, 375, UINT_MAX},
         {325, 325, 358, 375, UINT_MAX},
@@ -81,35 +84,34 @@ static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = {
         {295, 336, 358, 375, 391, UINT_MAX},
 };
 
-static int threshold_index;
-static int package_id;
+static int threshold_index __initdata;
 
-static void fuse_speedo_calib(u32 *speedo_g, u32 *speedo_lp)
+static void __init fuse_speedo_calib(u32 *speedo_g, u32 *speedo_lp)
 {
         u32 reg;
         int ate_ver;
         int bit_minus1;
         int bit_minus2;
 
-        reg = tegra_fuse_readl(FUSE_SPEEDO_CALIB_0);
+        reg = tegra30_fuse_readl(FUSE_SPEEDO_CALIB_0);
 
         *speedo_lp = (reg & 0xFFFF) * 4;
         *speedo_g = ((reg >> 16) & 0xFFFF) * 4;
 
-        ate_ver = tegra_fuse_readl(FUSE_TEST_PROG_VER);
-        pr_info("%s: ATE prog ver %d.%d\n", __func__, ate_ver/10, ate_ver%10);
+        ate_ver = tegra30_fuse_readl(FUSE_TEST_PROG_VER);
+        pr_debug("Tegra ATE prog ver %d.%d\n", ate_ver/10, ate_ver%10);
 
         if (ate_ver >= 26) {
-                bit_minus1 = tegra_spare_fuse(LP_SPEEDO_BIT_MINUS1);
-                bit_minus1 |= tegra_spare_fuse(LP_SPEEDO_BIT_MINUS1_R);
-                bit_minus2 = tegra_spare_fuse(LP_SPEEDO_BIT_MINUS2);
-                bit_minus2 |= tegra_spare_fuse(LP_SPEEDO_BIT_MINUS2_R);
+                bit_minus1 = tegra30_spare_fuse(LP_SPEEDO_BIT_MINUS1);
+                bit_minus1 |= tegra30_spare_fuse(LP_SPEEDO_BIT_MINUS1_R);
+                bit_minus2 = tegra30_spare_fuse(LP_SPEEDO_BIT_MINUS2);
+                bit_minus2 |= tegra30_spare_fuse(LP_SPEEDO_BIT_MINUS2_R);
                 *speedo_lp |= (bit_minus1 << 1) | bit_minus2;
 
-                bit_minus1 = tegra_spare_fuse(G_SPEEDO_BIT_MINUS1);
-                bit_minus1 |= tegra_spare_fuse(G_SPEEDO_BIT_MINUS1_R);
-                bit_minus2 = tegra_spare_fuse(G_SPEEDO_BIT_MINUS2);
-                bit_minus2 |= tegra_spare_fuse(G_SPEEDO_BIT_MINUS2_R);
+                bit_minus1 = tegra30_spare_fuse(G_SPEEDO_BIT_MINUS1);
+                bit_minus1 |= tegra30_spare_fuse(G_SPEEDO_BIT_MINUS1_R);
+                bit_minus2 = tegra30_spare_fuse(G_SPEEDO_BIT_MINUS2);
+                bit_minus2 |= tegra30_spare_fuse(G_SPEEDO_BIT_MINUS2_R);
                 *speedo_g |= (bit_minus1 << 1) | bit_minus2;
         } else {
                 *speedo_lp |= 0x3;
@@ -117,133 +119,131 @@ static void fuse_speedo_calib(u32 *speedo_g, u32 *speedo_lp)
         }
 }
 
-static void rev_sku_to_speedo_ids(int rev, int sku)
+static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info)
 {
-        switch (rev) {
+        int package_id = tegra30_fuse_readl(FUSE_PACKAGE_INFO) & 0x0F;
+
+        switch (sku_info->revision) {
         case TEGRA_REVISION_A01:
-                tegra_cpu_speedo_id = 0;
-                tegra_soc_speedo_id = 0;
+                sku_info->cpu_speedo_id = 0;
+                sku_info->soc_speedo_id = 0;
                 threshold_index = THRESHOLD_INDEX_0;
                 break;
         case TEGRA_REVISION_A02:
         case TEGRA_REVISION_A03:
-                switch (sku) {
+                switch (sku_info->sku_id) {
                 case 0x87:
                 case 0x82:
-                        tegra_cpu_speedo_id = 1;
-                        tegra_soc_speedo_id = 1;
+                        sku_info->cpu_speedo_id = 1;
+                        sku_info->soc_speedo_id = 1;
                         threshold_index = THRESHOLD_INDEX_1;
                         break;
                 case 0x81:
                         switch (package_id) {
                         case 1:
-                                tegra_cpu_speedo_id = 2;
-                                tegra_soc_speedo_id = 2;
+                                sku_info->cpu_speedo_id = 2;
+                                sku_info->soc_speedo_id = 2;
                                 threshold_index = THRESHOLD_INDEX_2;
                                 break;
                         case 2:
-                                tegra_cpu_speedo_id = 4;
-                                tegra_soc_speedo_id = 1;
+                                sku_info->cpu_speedo_id = 4;
+                                sku_info->soc_speedo_id = 1;
                                 threshold_index = THRESHOLD_INDEX_7;
                                 break;
                         default:
-                                pr_err("Tegra30: Unknown pkg %d\n", package_id);
-                                BUG();
+                                pr_err("Tegra Unknown pkg %d\n", package_id);
                                 break;
                         }
                         break;
                 case 0x80:
                         switch (package_id) {
                         case 1:
-                                tegra_cpu_speedo_id = 5;
-                                tegra_soc_speedo_id = 2;
+                                sku_info->cpu_speedo_id = 5;
+                                sku_info->soc_speedo_id = 2;
                                 threshold_index = THRESHOLD_INDEX_8;
                                 break;
                         case 2:
-                                tegra_cpu_speedo_id = 6;
-                                tegra_soc_speedo_id = 2;
+                                sku_info->cpu_speedo_id = 6;
+                                sku_info->soc_speedo_id = 2;
                                 threshold_index = THRESHOLD_INDEX_9;
                                 break;
                         default:
-                                pr_err("Tegra30: Unknown pkg %d\n", package_id);
-                                BUG();
+                                pr_err("Tegra Unknown pkg %d\n", package_id);
                                 break;
                         }
                         break;
                 case 0x83:
                         switch (package_id) {
                         case 1:
-                                tegra_cpu_speedo_id = 7;
-                                tegra_soc_speedo_id = 1;
+                                sku_info->cpu_speedo_id = 7;
+                                sku_info->soc_speedo_id = 1;
                                 threshold_index = THRESHOLD_INDEX_10;
                                 break;
                         case 2:
-                                tegra_cpu_speedo_id = 3;
-                                tegra_soc_speedo_id = 2;
+                                sku_info->cpu_speedo_id = 3;
+                                sku_info->soc_speedo_id = 2;
                                 threshold_index = THRESHOLD_INDEX_3;
                                 break;
                         default:
-                                pr_err("Tegra30: Unknown pkg %d\n", package_id);
-                                BUG();
+                                pr_err("Tegra Unknown pkg %d\n", package_id);
                                 break;
                         }
                         break;
                 case 0x8F:
-                        tegra_cpu_speedo_id = 8;
-                        tegra_soc_speedo_id = 1;
+                        sku_info->cpu_speedo_id = 8;
+                        sku_info->soc_speedo_id = 1;
                         threshold_index = THRESHOLD_INDEX_11;
                         break;
                 case 0x08:
-                        tegra_cpu_speedo_id = 1;
-                        tegra_soc_speedo_id = 1;
+                        sku_info->cpu_speedo_id = 1;
+                        sku_info->soc_speedo_id = 1;
                         threshold_index = THRESHOLD_INDEX_4;
                         break;
                 case 0x02:
-                        tegra_cpu_speedo_id = 2;
-                        tegra_soc_speedo_id = 2;
+                        sku_info->cpu_speedo_id = 2;
+                        sku_info->soc_speedo_id = 2;
                         threshold_index = THRESHOLD_INDEX_5;
                         break;
                 case 0x04:
-                        tegra_cpu_speedo_id = 3;
-                        tegra_soc_speedo_id = 2;
+                        sku_info->cpu_speedo_id = 3;
+                        sku_info->soc_speedo_id = 2;
                         threshold_index = THRESHOLD_INDEX_6;
                         break;
                 case 0:
                         switch (package_id) {
                         case 1:
-                                tegra_cpu_speedo_id = 2;
-                                tegra_soc_speedo_id = 2;
+                                sku_info->cpu_speedo_id = 2;
+                                sku_info->soc_speedo_id = 2;
                                 threshold_index = THRESHOLD_INDEX_2;
                                 break;
                         case 2:
-                                tegra_cpu_speedo_id = 3;
-                                tegra_soc_speedo_id = 2;
+                                sku_info->cpu_speedo_id = 3;
+                                sku_info->soc_speedo_id = 2;
                                 threshold_index = THRESHOLD_INDEX_3;
                                 break;
                         default:
-                                pr_err("Tegra30: Unknown pkg %d\n", package_id);
-                                BUG();
+                                pr_err("Tegra Unknown pkg %d\n", package_id);
                                 break;
                         }
                         break;
                 default:
-                        pr_warn("Tegra30: Unknown SKU %d\n", sku);
-                        tegra_cpu_speedo_id = 0;
-                        tegra_soc_speedo_id = 0;
+                        pr_warn("Tegra Unknown SKU %d\n", sku_info->sku_id);
+                        sku_info->cpu_speedo_id = 0;
+                        sku_info->soc_speedo_id = 0;
                         threshold_index = THRESHOLD_INDEX_0;
                         break;
                 }
                 break;
         default:
-                pr_warn("Tegra30: Unknown chip rev %d\n", rev);
-                tegra_cpu_speedo_id = 0;
-                tegra_soc_speedo_id = 0;
+                pr_warn("Tegra Unknown chip rev %d\n", sku_info->revision);
+                sku_info->cpu_speedo_id = 0;
+                sku_info->soc_speedo_id = 0;
                 threshold_index = THRESHOLD_INDEX_0;
                 break;
         }
 }
 
-void tegra30_init_speedo_data(void)
+void __init tegra30_init_speedo_data(struct tegra_sku_info *sku_info)
 {
         u32 cpu_speedo_val;
         u32 core_speedo_val;
@@ -254,39 +254,35 @@ void tegra30_init_speedo_data(void)
         BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) !=
                         THRESHOLD_INDEX_COUNT);
 
-        package_id = tegra_fuse_readl(FUSE_PACKAGE_INFO) & 0x0F;
 
-        rev_sku_to_speedo_ids(tegra_revision, tegra_sku_id);
+        rev_sku_to_speedo_ids(sku_info);
         fuse_speedo_calib(&cpu_speedo_val, &core_speedo_val);
-        pr_debug("%s CPU speedo value %u\n", __func__, cpu_speedo_val);
-        pr_debug("%s Core speedo value %u\n", __func__, core_speedo_val);
+        pr_debug("Tegra CPU speedo value %u\n", cpu_speedo_val);
+        pr_debug("Tegra Core speedo value %u\n", core_speedo_val);
 
-        for (i = 0; i < CPU_PROCESS_CORNERS_NUM; i++) {
+        for (i = 0; i < CPU_PROCESS_CORNERS; i++) {
                 if (cpu_speedo_val < cpu_process_speedos[threshold_index][i])
                         break;
         }
-        tegra_cpu_process_id = i - 1;
+        sku_info->cpu_process_id = i - 1;
 
-        if (tegra_cpu_process_id == -1) {
-                pr_warn("Tegra30: CPU speedo value %3d out of range",
-                       cpu_speedo_val);
-                tegra_cpu_process_id = 0;
-                tegra_cpu_speedo_id = 1;
+        if (sku_info->cpu_process_id == -1) {
+                pr_warn("Tegra CPU speedo value %3d out of range",
+                         cpu_speedo_val);
+                sku_info->cpu_process_id = 0;
+                sku_info->cpu_speedo_id = 1;
         }
 
-        for (i = 0; i < CORE_PROCESS_CORNERS_NUM; i++) {
+        for (i = 0; i < CORE_PROCESS_CORNERS; i++) {
                 if (core_speedo_val < core_process_speedos[threshold_index][i])
                         break;
         }
-        tegra_core_process_id = i - 1;
+        sku_info->core_process_id = i - 1;
 
-        if (tegra_core_process_id == -1) {
-                pr_warn("Tegra30: CORE speedo value %3d out of range",
-                       core_speedo_val);
-                tegra_core_process_id = 0;
-                tegra_soc_speedo_id = 1;
+        if (sku_info->core_process_id == -1) {
+                pr_warn("Tegra CORE speedo value %3d out of range",
+                                 core_speedo_val);
+                sku_info->core_process_id = 0;
+                sku_info->soc_speedo_id = 1;
         }
-
-        pr_info("Tegra30: CPU Speedo ID %d, Soc Speedo ID %d",
-                tegra_cpu_speedo_id, tegra_soc_speedo_id);
 }
diff --git a/drivers/soc/tegra/fuse/tegra-apbmisc.c b/drivers/soc/tegra/fuse/tegra-apbmisc.c
new file mode 100644
index 000000000000..3bf5aba4caaa
--- /dev/null
+++ b/drivers/soc/tegra/fuse/tegra-apbmisc.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#include <soc/tegra/fuse.h>
+
+#include "fuse.h"
+
+#define APBMISC_BASE    0x70000800
+#define APBMISC_SIZE    0x64
+#define FUSE_SKU_INFO   0x10
+
+static void __iomem *apbmisc_base;
+static void __iomem *strapping_base;
+
+u32 tegra_read_chipid(void)
+{
+        return readl_relaxed(apbmisc_base + 4);
+}
+
+u8 tegra_get_chip_id(void)
+{
+        if (!apbmisc_base) {
+                WARN(1, "Tegra Chip ID not yet available\n");
+                return 0;
+        }
+
+        return (tegra_read_chipid() >> 8) & 0xff;
+}
+
+u32 tegra_read_straps(void)
+{
+        if (strapping_base)
+                return readl_relaxed(strapping_base);
+        else
+                return 0;
+}
+
+static const struct of_device_id apbmisc_match[] __initconst = {
+        { .compatible = "nvidia,tegra20-apbmisc", },
+        {},
+};
+
+void __init tegra_init_revision(void)
+{
+        u32 id, chip_id, minor_rev;
+        int rev;
+
+        id = tegra_read_chipid();
+        chip_id = (id >> 8) & 0xff;
+        minor_rev = (id >> 16) & 0xf;
+
+        switch (minor_rev) {
+        case 1:
+                rev = TEGRA_REVISION_A01;
+                break;
+        case 2:
+                rev = TEGRA_REVISION_A02;
+                break;
+        case 3:
+                if (chip_id == TEGRA20 && (tegra20_spare_fuse_early(18) ||
+                                           tegra20_spare_fuse_early(19)))
+                        rev = TEGRA_REVISION_A03p;
+                else
+                        rev = TEGRA_REVISION_A03;
+                break;
+        case 4:
+                rev = TEGRA_REVISION_A04;
+                break;
+        default:
+                rev = TEGRA_REVISION_UNKNOWN;
+        }
+
+        tegra_sku_info.revision = rev;
+
+        if (chip_id == TEGRA20)
+                tegra_sku_info.sku_id = tegra20_fuse_early(FUSE_SKU_INFO);
+        else
+                tegra_sku_info.sku_id = tegra30_fuse_readl(FUSE_SKU_INFO);
+}
+
+void __init tegra_init_apbmisc(void)
+{
+        struct device_node *np;
+
+        np = of_find_matching_node(NULL, apbmisc_match);
+        apbmisc_base = of_iomap(np, 0);
+        if (!apbmisc_base) {
+                pr_warn("ioremap tegra apbmisc failed. using %08x instead\n",
+                        APBMISC_BASE);
+                apbmisc_base = ioremap(APBMISC_BASE, APBMISC_SIZE);
+        }
+
+        strapping_base = of_iomap(np, 1);
+        if (!strapping_base)
+                pr_err("ioremap tegra strapping_base failed\n");
+}
diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
new file mode 100644
index 000000000000..a2c0ceb95f8f
--- /dev/null
+++ b/drivers/soc/tegra/pmc.c
@@ -0,0 +1,957 @@
+/*
+ * drivers/soc/tegra/pmc.c
+ *
+ * Copyright (c) 2010 Google, Inc
+ *
+ * Author:
+ *      Colin Cross <ccross@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/clk/tegra.h>
+#include <linux/debugfs.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/export.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/reboot.h>
+#include <linux/reset.h>
+#include <linux/seq_file.h>
+#include <linux/spinlock.h>
+
+#include <soc/tegra/common.h>
+#include <soc/tegra/fuse.h>
+#include <soc/tegra/pmc.h>
+
+#define PMC_CNTRL                       0x0
+#define  PMC_CNTRL_SYSCLK_POLARITY      (1 << 10)  /* sys clk polarity */
+#define  PMC_CNTRL_SYSCLK_OE            (1 << 11)  /* system clock enable */
+#define  PMC_CNTRL_SIDE_EFFECT_LP0      (1 << 14)  /* LP0 when CPU pwr gated */
+#define  PMC_CNTRL_CPU_PWRREQ_POLARITY  (1 << 15)  /* CPU pwr req polarity */
+#define  PMC_CNTRL_CPU_PWRREQ_OE        (1 << 16)  /* CPU pwr req enable */
+#define  PMC_CNTRL_INTR_POLARITY        (1 << 17)  /* inverts INTR polarity */
+
+#define DPD_SAMPLE                      0x020
+#define  DPD_SAMPLE_ENABLE              (1 << 0)
+#define  DPD_SAMPLE_DISABLE             (0 << 0)
+
+#define PWRGATE_TOGGLE                  0x30
+#define  PWRGATE_TOGGLE_START           (1 << 8)
+
+#define REMOVE_CLAMPING                 0x34
+
+#define PWRGATE_STATUS                  0x38
+
+#define PMC_SCRATCH0                    0x50
+#define  PMC_SCRATCH0_MODE_RECOVERY     (1 << 31)
+#define  PMC_SCRATCH0_MODE_BOOTLOADER   (1 << 30)
+#define  PMC_SCRATCH0_MODE_RCM          (1 << 1)
+#define  PMC_SCRATCH0_MODE_MASK         (PMC_SCRATCH0_MODE_RECOVERY | \
+                                         PMC_SCRATCH0_MODE_BOOTLOADER | \
+                                         PMC_SCRATCH0_MODE_RCM)
+
+#define PMC_CPUPWRGOOD_TIMER            0xc8
+#define PMC_CPUPWROFF_TIMER             0xcc
+
+#define PMC_SCRATCH41                   0x140
+
+#define IO_DPD_REQ                      0x1b8
+#define  IO_DPD_REQ_CODE_IDLE           (0 << 30)
+#define  IO_DPD_REQ_CODE_OFF            (1 << 30)
+#define  IO_DPD_REQ_CODE_ON             (2 << 30)
+#define  IO_DPD_REQ_CODE_MASK           (3 << 30)
+
+#define IO_DPD_STATUS                   0x1bc
+#define IO_DPD2_REQ                     0x1c0
+#define IO_DPD2_STATUS                  0x1c4
+#define SEL_DPD_TIM                     0x1c8
+
+#define GPU_RG_CNTRL                    0x2d4
+
+struct tegra_pmc_soc {
+        unsigned int num_powergates;
+        const char *const *powergates;
+        unsigned int num_cpu_powergates;
+        const u8 *cpu_powergates;
+};
+
+/**
+ * struct tegra_pmc - NVIDIA Tegra PMC
+ * @base: pointer to I/O remapped register region
+ * @clk: pointer to pclk clock
+ * @rate: currently configured rate of pclk
+ * @suspend_mode: lowest suspend mode available
+ * @cpu_good_time: CPU power good time (in microseconds)
+ * @cpu_off_time: CPU power off time (in microsecends)
+ * @core_osc_time: core power good OSC time (in microseconds)
+ * @core_pmu_time: core power good PMU time (in microseconds)
+ * @core_off_time: core power off time (in microseconds)
+ * @corereq_high: core power request is active-high
+ * @sysclkreq_high: system clock request is active-high
+ * @combined_req: combined power request for CPU & core
+ * @cpu_pwr_good_en: CPU power good signal is enabled
+ * @lp0_vec_phys: physical base address of the LP0 warm boot code
+ * @lp0_vec_size: size of the LP0 warm boot code
+ * @powergates_lock: mutex for power gate register access
+ */
+struct tegra_pmc {
+        void __iomem *base;
+        struct clk *clk;
+
+        const struct tegra_pmc_soc *soc;
+
+        unsigned long rate;
+
+        enum tegra_suspend_mode suspend_mode;
+        u32 cpu_good_time;
+        u32 cpu_off_time;
+        u32 core_osc_time;
+        u32 core_pmu_time;
+        u32 core_off_time;
+        bool corereq_high;
+        bool sysclkreq_high;
+        bool combined_req;
+        bool cpu_pwr_good_en;
+        u32 lp0_vec_phys;
+        u32 lp0_vec_size;
+
+        struct mutex powergates_lock;
+};
+
+static struct tegra_pmc *pmc = &(struct tegra_pmc) {
+        .base = NULL,
+        .suspend_mode = TEGRA_SUSPEND_NONE,
+};
+
+static u32 tegra_pmc_readl(unsigned long offset)
+{
+        return readl(pmc->base + offset);
+}
+
+static void tegra_pmc_writel(u32 value, unsigned long offset)
+{
+        writel(value, pmc->base + offset);
+}
+
+/**
+ * tegra_powergate_set() - set the state of a partition
+ * @id: partition ID
+ * @new_state: new state of the partition
+ */
+static int tegra_powergate_set(int id, bool new_state)
+{
+        bool status;
+
+        mutex_lock(&pmc->powergates_lock);
+
+        status = tegra_pmc_readl(PWRGATE_STATUS) & (1 << id);
+
+        if (status == new_state) {
+                mutex_unlock(&pmc->powergates_lock);
+                return 0;
+        }
+
+        tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
+
+        mutex_unlock(&pmc->powergates_lock);
+
+        return 0;
+}
+
+/**
+ * tegra_powergate_power_on() - power on partition
+ * @id: partition ID
+ */
+int tegra_powergate_power_on(int id)
+{
+        if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates)
+                return -EINVAL;
+
+        return tegra_powergate_set(id, true);
+}
+
+/**
+ * tegra_powergate_power_off() - power off partition
+ * @id: partition ID
+ */
+int tegra_powergate_power_off(int id)
+{
+        if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates)
+                return -EINVAL;
+
+        return tegra_powergate_set(id, false);
+}
+EXPORT_SYMBOL(tegra_powergate_power_off);
+
+/**
+ * tegra_powergate_is_powered() - check if partition is powered
+ * @id: partition ID
+ */
+int tegra_powergate_is_powered(int id)
+{
+        u32 status;
+
+        if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates)
+                return -EINVAL;
+
+        status = tegra_pmc_readl(PWRGATE_STATUS) & (1 << id);
+        return !!status;
+}
+
+/**
+ * tegra_powergate_remove_clamping() - remove power clamps for partition
+ * @id: partition ID
+ */
+int tegra_powergate_remove_clamping(int id)
+{
+        u32 mask;
+
+        if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates)
+                return -EINVAL;
+
+        /*
+         * The Tegra124 GPU has a separate register (with different semantics)
+         * to remove clamps.
+         */
+        if (tegra_get_chip_id() == TEGRA124) {
+                if (id == TEGRA_POWERGATE_3D) {
+                        tegra_pmc_writel(0, GPU_RG_CNTRL);
+                        return 0;
+                }
+        }
+
+        /*
+         * Tegra 2 has a bug where PCIE and VDE clamping masks are
+         * swapped relatively to the partition ids
+         */
+        if (id == TEGRA_POWERGATE_VDEC)
+                mask = (1 << TEGRA_POWERGATE_PCIE);
+        else if (id == TEGRA_POWERGATE_PCIE)
+                mask = (1 << TEGRA_POWERGATE_VDEC);
+        else
+                mask = (1 << id);
+
+        tegra_pmc_writel(mask, REMOVE_CLAMPING);
+
+        return 0;
+}
+EXPORT_SYMBOL(tegra_powergate_remove_clamping);
+
+/**
+ * tegra_powergate_sequence_power_up() - power up partition
+ * @id: partition ID
+ * @clk: clock for partition
+ * @rst: reset for partition
+ *
+ * Must be called with clk disabled, and returns with clk enabled.
+ */
+int tegra_powergate_sequence_power_up(int id, struct clk *clk,
+                                      struct reset_control *rst)
+{
+        int ret;
+
+        reset_control_assert(rst);
+
+        ret = tegra_powergate_power_on(id);
+        if (ret)
+                goto err_power;
+
+        ret = clk_prepare_enable(clk);
+        if (ret)
+                goto err_clk;
+
+        usleep_range(10, 20);
+
+        ret = tegra_powergate_remove_clamping(id);
+        if (ret)
+                goto err_clamp;
+
+        usleep_range(10, 20);
+        reset_control_deassert(rst);
+
+        return 0;
+
+err_clamp:
+        clk_disable_unprepare(clk);
+err_clk:
+        tegra_powergate_power_off(id);
+err_power:
+        return ret;
+}
+EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
+
+#ifdef CONFIG_SMP
+/**
+ * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
+ * @cpuid: CPU partition ID
+ *
+ * Returns the partition ID corresponding to the CPU partition ID or a
+ * negative error code on failure.
+ */
+static int tegra_get_cpu_powergate_id(int cpuid)
+{
+        if (pmc->soc && cpuid > 0 && cpuid < pmc->soc->num_cpu_powergates)
+                return pmc->soc->cpu_powergates[cpuid];
+
+        return -EINVAL;
+}
+
+/**
+ * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
+ * @cpuid: CPU partition ID
+ */
+bool tegra_pmc_cpu_is_powered(int cpuid)
+{
+        int id;
+
+        id = tegra_get_cpu_powergate_id(cpuid);
+        if (id < 0)
+                return false;
+
+        return tegra_powergate_is_powered(id);
+}
+
+/**
+ * tegra_pmc_cpu_power_on() - power on CPU partition
+ * @cpuid: CPU partition ID
+ */
+int tegra_pmc_cpu_power_on(int cpuid)
+{
+        int id;
+
+        id = tegra_get_cpu_powergate_id(cpuid);
+        if (id < 0)
+                return id;
+
+        return tegra_powergate_set(id, true);
+}
+
+/**
+ * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
+ * @cpuid: CPU partition ID
+ */
+int tegra_pmc_cpu_remove_clamping(int cpuid)
+{
+        int id;
+
+        id = tegra_get_cpu_powergate_id(cpuid);
+        if (id < 0)
+                return id;
+
+        return tegra_powergate_remove_clamping(id);
+}
+#endif /* CONFIG_SMP */
+
+/**
+ * tegra_pmc_restart() - reboot the system
+ * @mode: which mode to reboot in
+ * @cmd: reboot command
+ */
+void tegra_pmc_restart(enum reboot_mode mode, const char *cmd)
+{
+        u32 value;
+
+        value = tegra_pmc_readl(PMC_SCRATCH0);
+        value &= ~PMC_SCRATCH0_MODE_MASK;
+
+        if (cmd) {
+                if (strcmp(cmd, "recovery") == 0)
+                        value |= PMC_SCRATCH0_MODE_RECOVERY;
+
+                if (strcmp(cmd, "bootloader") == 0)
+                        value |= PMC_SCRATCH0_MODE_BOOTLOADER;
+
+                if (strcmp(cmd, "forced-recovery") == 0)
+                        value |= PMC_SCRATCH0_MODE_RCM;
+        }
+
+        tegra_pmc_writel(value, PMC_SCRATCH0);
+
+        value = tegra_pmc_readl(0);
+        value |= 0x10;
+        tegra_pmc_writel(value, 0);
+}
+
+static int powergate_show(struct seq_file *s, void *data)
+{
+        unsigned int i;
+
+        seq_printf(s, " powergate powered\n");
+        seq_printf(s, "------------------\n");
+
+        for (i = 0; i < pmc->soc->num_powergates; i++) {
+                if (!pmc->soc->powergates[i])
+                        continue;
+
+                seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
+                           tegra_powergate_is_powered(i) ? "yes" : "no");
+        }
+
+        return 0;
+}
+
+static int powergate_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, powergate_show, inode->i_private);
+}
+
+static const struct file_operations powergate_fops = {
+        .open = powergate_open,
+        .read = seq_read,
+        .llseek = seq_lseek,
+        .release = single_release,
+};
+
+static int tegra_powergate_debugfs_init(void)
+{
+        struct dentry *d;
+
+        d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
+                                &powergate_fops);
+        if (!d)
+                return -ENOMEM;
+
+        return 0;
+}
+
+static int tegra_io_rail_prepare(int id, unsigned long *request,
+                                 unsigned long *status, unsigned int *bit)
+{
+        unsigned long rate, value;
+        struct clk *clk;
+
+        *bit = id % 32;
+
+        /*
+         * There are two sets of 30 bits to select IO rails, but bits 30 and
+         * 31 are control bits rather than IO rail selection bits.
+         */
+        if (id > 63 || *bit == 30 || *bit == 31)
+                return -EINVAL;
+
+        if (id < 32) {
+                *status = IO_DPD_STATUS;
+                *request = IO_DPD_REQ;
+        } else {
+                *status = IO_DPD2_STATUS;
+                *request = IO_DPD2_REQ;
+        }
+
+        clk = clk_get_sys(NULL, "pclk");
+        if (IS_ERR(clk))
+                return PTR_ERR(clk);
+
+        rate = clk_get_rate(clk);
+        clk_put(clk);
+
+        tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE);
+
+        /* must be at least 200 ns, in APB (PCLK) clock cycles */
+        value = DIV_ROUND_UP(1000000000, rate);
+        value = DIV_ROUND_UP(200, value);
+        tegra_pmc_writel(value, SEL_DPD_TIM);
+
+        return 0;
+}
+
+static int tegra_io_rail_poll(unsigned long offset, unsigned long mask,
+                              unsigned long val, unsigned long timeout)
+{
+        unsigned long value;
+
+        timeout = jiffies + msecs_to_jiffies(timeout);
+
+        while (time_after(timeout, jiffies)) {
+                value = tegra_pmc_readl(offset);
+                if ((value & mask) == val)
+                        return 0;
+
+                usleep_range(250, 1000);
+        }
+
+        return -ETIMEDOUT;
+}
+
+static void tegra_io_rail_unprepare(void)
+{
+        tegra_pmc_writel(DPD_SAMPLE_DISABLE, DPD_SAMPLE);
+}
+
+int tegra_io_rail_power_on(int id)
+{
+        unsigned long request, status, value;
+        unsigned int bit, mask;
+        int err;
+
+        err = tegra_io_rail_prepare(id, &request, &status, &bit);
+        if (err < 0)
+                return err;
+
+        mask = 1 << bit;
+
+        value = tegra_pmc_readl(request);
+        value |= mask;
+        value &= ~IO_DPD_REQ_CODE_MASK;
+        value |= IO_DPD_REQ_CODE_OFF;
+        tegra_pmc_writel(value, request);
+
+        err = tegra_io_rail_poll(status, mask, 0, 250);
+        if (err < 0)
+                return err;
+
+        tegra_io_rail_unprepare();
+
+        return 0;
+}
+EXPORT_SYMBOL(tegra_io_rail_power_on);
+
+int tegra_io_rail_power_off(int id)
+{
+        unsigned long request, status, value;
+        unsigned int bit, mask;
+        int err;
+
+        err = tegra_io_rail_prepare(id, &request, &status, &bit);
+        if (err < 0)
+                return err;
+
+        mask = 1 << bit;
+
+        value = tegra_pmc_readl(request);
+        value |= mask;
+        value &= ~IO_DPD_REQ_CODE_MASK;
+        value |= IO_DPD_REQ_CODE_ON;
+        tegra_pmc_writel(value, request);
+
+        err = tegra_io_rail_poll(status, mask, mask, 250);
+        if (err < 0)
+                return err;
+
+        tegra_io_rail_unprepare();
+
+        return 0;
+}
+EXPORT_SYMBOL(tegra_io_rail_power_off);
+
+#ifdef CONFIG_PM_SLEEP
+enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
+{
+        return pmc->suspend_mode;
+}
+
+void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
+{
+        if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
+                return;
+
+        pmc->suspend_mode = mode;
+}
+
+void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
+{
+        unsigned long long rate = 0;
+        u32 value;
+
+        switch (mode) {
+        case TEGRA_SUSPEND_LP1:
+                rate = 32768;
+                break;
+
+        case TEGRA_SUSPEND_LP2:
+                rate = clk_get_rate(pmc->clk);
+                break;
+
+        default:
+                break;
+        }
+
+        if (WARN_ON_ONCE(rate == 0))
+                rate = 100000000;
+
+        if (rate != pmc->rate) {
+                u64 ticks;
+
+                ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
+                do_div(ticks, USEC_PER_SEC);
+                tegra_pmc_writel(ticks, PMC_CPUPWRGOOD_TIMER);
+
+                ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
+                do_div(ticks, USEC_PER_SEC);
+                tegra_pmc_writel(ticks, PMC_CPUPWROFF_TIMER);
+
+                wmb();
+
+                pmc->rate = rate;
+        }
+
+        value = tegra_pmc_readl(PMC_CNTRL);
+        value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
+        value |= PMC_CNTRL_CPU_PWRREQ_OE;
+        tegra_pmc_writel(value, PMC_CNTRL);
+}
+#endif
+
+static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
+{
+        u32 value, values[2];
+
+        if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
+        } else {
+                switch (value) {
+                case 0:
+                        pmc->suspend_mode = TEGRA_SUSPEND_LP0;
+                        break;
+
+                case 1:
+                        pmc->suspend_mode = TEGRA_SUSPEND_LP1;
+                        break;
+
+                case 2:
+                        pmc->suspend_mode = TEGRA_SUSPEND_LP2;
+                        break;
+
+                default:
+                        pmc->suspend_mode = TEGRA_SUSPEND_NONE;
+                        break;
+                }
+        }
+
+        pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
+
+        if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
+                pmc->suspend_mode = TEGRA_SUSPEND_NONE;
+
+        pmc->cpu_good_time = value;
+
+        if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
+                pmc->suspend_mode = TEGRA_SUSPEND_NONE;
+
+        pmc->cpu_off_time = value;
+
+        if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
+                                       values, ARRAY_SIZE(values)))
+                pmc->suspend_mode = TEGRA_SUSPEND_NONE;
+
+        pmc->core_osc_time = values[0];
+        pmc->core_pmu_time = values[1];
+
+        if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
+                pmc->suspend_mode = TEGRA_SUSPEND_NONE;
+
+        pmc->core_off_time = value;
+
+        pmc->corereq_high = of_property_read_bool(np,
+                                "nvidia,core-power-req-active-high");
+
+        pmc->sysclkreq_high = of_property_read_bool(np,
+                                "nvidia,sys-clock-req-active-high");
+
+        pmc->combined_req = of_property_read_bool(np,
+                                "nvidia,combined-power-req");
+
+        pmc->cpu_pwr_good_en = of_property_read_bool(np,
+                                "nvidia,cpu-pwr-good-en");
+
+        if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,
+                                       ARRAY_SIZE(values)))
+                if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
+                        pmc->suspend_mode = TEGRA_SUSPEND_LP1;
+
+        pmc->lp0_vec_phys = values[0];
+        pmc->lp0_vec_size = values[1];
+
+        return 0;
+}
+
+static void tegra_pmc_init(struct tegra_pmc *pmc)
+{
+        u32 value;
+
+        /* Always enable CPU power request */
+        value = tegra_pmc_readl(PMC_CNTRL);
+        value |= PMC_CNTRL_CPU_PWRREQ_OE;
+        tegra_pmc_writel(value, PMC_CNTRL);
+
+        value = tegra_pmc_readl(PMC_CNTRL);
+
+        if (pmc->sysclkreq_high)
+                value &= ~PMC_CNTRL_SYSCLK_POLARITY;
+        else
+                value |= PMC_CNTRL_SYSCLK_POLARITY;
+
+        /* configure the output polarity while the request is tristated */
+        tegra_pmc_writel(value, PMC_CNTRL);
+
+        /* now enable the request */
+        value = tegra_pmc_readl(PMC_CNTRL);
+        value |= PMC_CNTRL_SYSCLK_OE;
+        tegra_pmc_writel(value, PMC_CNTRL);
+}
+
+static int tegra_pmc_probe(struct platform_device *pdev)
+{
+        void __iomem *base = pmc->base;
+        struct resource *res;
+        int err;
+
+        err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
+        if (err < 0)
+                return err;
+
+        /* take over the memory region from the early initialization */
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        pmc->base = devm_ioremap_resource(&pdev->dev, res);
+        if (IS_ERR(pmc->base))
+                return PTR_ERR(pmc->base);
+
+        iounmap(base);
+
+        pmc->clk = devm_clk_get(&pdev->dev, "pclk");
+        if (IS_ERR(pmc->clk)) {
+                err = PTR_ERR(pmc->clk);
+                dev_err(&pdev->dev, "failed to get pclk: %d\n", err);
+                return err;
+        }
+
+        tegra_pmc_init(pmc);
+
+        if (IS_ENABLED(CONFIG_DEBUG_FS)) {
+                err = tegra_powergate_debugfs_init();
+                if (err < 0)
+                        return err;
+        }
+
+        return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int tegra_pmc_suspend(struct device *dev)
+{
+        tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41);
+
+        return 0;
+}
+
+static int tegra_pmc_resume(struct device *dev)
+{
+        tegra_pmc_writel(0x0, PMC_SCRATCH41);
+
+        return 0;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
+
+static const char * const tegra20_powergates[] = {
+        [TEGRA_POWERGATE_CPU] = "cpu",
+        [TEGRA_POWERGATE_3D] = "3d",
+        [TEGRA_POWERGATE_VENC] = "venc",
+        [TEGRA_POWERGATE_VDEC] = "vdec",
+        [TEGRA_POWERGATE_PCIE] = "pcie",
+        [TEGRA_POWERGATE_L2] = "l2",
+        [TEGRA_POWERGATE_MPE] = "mpe",
+};
+
+static const struct tegra_pmc_soc tegra20_pmc_soc = {
+        .num_powergates = ARRAY_SIZE(tegra20_powergates),
+        .powergates = tegra20_powergates,
+        .num_cpu_powergates = 0,
+        .cpu_powergates = NULL,
+};
+
+static const char * const tegra30_powergates[] = {
+        [TEGRA_POWERGATE_CPU] = "cpu0",
+        [TEGRA_POWERGATE_3D] = "3d0",
+        [TEGRA_POWERGATE_VENC] = "venc",
+        [TEGRA_POWERGATE_VDEC] = "vdec",
+        [TEGRA_POWERGATE_PCIE] = "pcie",
+        [TEGRA_POWERGATE_L2] = "l2",
+        [TEGRA_POWERGATE_MPE] = "mpe",
+        [TEGRA_POWERGATE_HEG] = "heg",
+        [TEGRA_POWERGATE_SATA] = "sata",
+        [TEGRA_POWERGATE_CPU1] = "cpu1",
+        [TEGRA_POWERGATE_CPU2] = "cpu2",
+        [TEGRA_POWERGATE_CPU3] = "cpu3",
+        [TEGRA_POWERGATE_CELP] = "celp",
+        [TEGRA_POWERGATE_3D1] = "3d1",
+};
+
+static const u8 tegra30_cpu_powergates[] = {
+        TEGRA_POWERGATE_CPU,
+        TEGRA_POWERGATE_CPU1,
+        TEGRA_POWERGATE_CPU2,
+        TEGRA_POWERGATE_CPU3,
+};
+
+static const struct tegra_pmc_soc tegra30_pmc_soc = {
+        .num_powergates = ARRAY_SIZE(tegra30_powergates),
+        .powergates = tegra30_powergates,
+        .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
+        .cpu_powergates = tegra30_cpu_powergates,
+};
+
+static const char * const tegra114_powergates[] = {
+        [TEGRA_POWERGATE_CPU] = "crail",
+        [TEGRA_POWERGATE_3D] = "3d",
+        [TEGRA_POWERGATE_VENC] = "venc",
+        [TEGRA_POWERGATE_VDEC] = "vdec",
+        [TEGRA_POWERGATE_MPE] = "mpe",
+        [TEGRA_POWERGATE_HEG] = "heg",
+        [TEGRA_POWERGATE_CPU1] = "cpu1",
+        [TEGRA_POWERGATE_CPU2] = "cpu2",
+        [TEGRA_POWERGATE_CPU3] = "cpu3",
+        [TEGRA_POWERGATE_CELP] = "celp",
+        [TEGRA_POWERGATE_CPU0] = "cpu0",
+        [TEGRA_POWERGATE_C0NC] = "c0nc",
+        [TEGRA_POWERGATE_C1NC] = "c1nc",
+        [TEGRA_POWERGATE_DIS] = "dis",
+        [TEGRA_POWERGATE_DISB] = "disb",
+        [TEGRA_POWERGATE_XUSBA] = "xusba",
+        [TEGRA_POWERGATE_XUSBB] = "xusbb",
+        [TEGRA_POWERGATE_XUSBC] = "xusbc",
+};
+
+static const u8 tegra114_cpu_powergates[] = {
+        TEGRA_POWERGATE_CPU0,
+        TEGRA_POWERGATE_CPU1,
+        TEGRA_POWERGATE_CPU2,
+        TEGRA_POWERGATE_CPU3,
+};
+
+static const struct tegra_pmc_soc tegra114_pmc_soc = {
+        .num_powergates = ARRAY_SIZE(tegra114_powergates),
+        .powergates = tegra114_powergates,
+        .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
+        .cpu_powergates = tegra114_cpu_powergates,
+};
+
+static const char * const tegra124_powergates[] = {
+        [TEGRA_POWERGATE_CPU] = "crail",
+        [TEGRA_POWERGATE_3D] = "3d",
+        [TEGRA_POWERGATE_VENC] = "venc",
+        [TEGRA_POWERGATE_PCIE] = "pcie",
+        [TEGRA_POWERGATE_VDEC] = "vdec",
+        [TEGRA_POWERGATE_L2] = "l2",
+        [TEGRA_POWERGATE_MPE] = "mpe",
+        [TEGRA_POWERGATE_HEG] = "heg",
+        [TEGRA_POWERGATE_SATA] = "sata",
+        [TEGRA_POWERGATE_CPU1] = "cpu1",
+        [TEGRA_POWERGATE_CPU2] = "cpu2",
+        [TEGRA_POWERGATE_CPU3] = "cpu3",
+        [TEGRA_POWERGATE_CELP] = "celp",
+        [TEGRA_POWERGATE_CPU0] = "cpu0",
+        [TEGRA_POWERGATE_C0NC] = "c0nc",
+        [TEGRA_POWERGATE_C1NC] = "c1nc",
+        [TEGRA_POWERGATE_SOR] = "sor",
+        [TEGRA_POWERGATE_DIS] = "dis",
+        [TEGRA_POWERGATE_DISB] = "disb",
+        [TEGRA_POWERGATE_XUSBA] = "xusba",
+        [TEGRA_POWERGATE_XUSBB] = "xusbb",
+        [TEGRA_POWERGATE_XUSBC] = "xusbc",
+        [TEGRA_POWERGATE_VIC] = "vic",
+        [TEGRA_POWERGATE_IRAM] = "iram",
+};
+
+static const u8 tegra124_cpu_powergates[] = {
+        TEGRA_POWERGATE_CPU0,
+        TEGRA_POWERGATE_CPU1,
+        TEGRA_POWERGATE_CPU2,
+        TEGRA_POWERGATE_CPU3,
+};
+
+static const struct tegra_pmc_soc tegra124_pmc_soc = {
+        .num_powergates = ARRAY_SIZE(tegra124_powergates),
+        .powergates = tegra124_powergates,
+        .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
+        .cpu_powergates = tegra124_cpu_powergates,
+};
+
+static const struct of_device_id tegra_pmc_match[] = {
+        { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
+        { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
+        { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
+        { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
+        { }
+};
+
+static struct platform_driver tegra_pmc_driver = {
+        .driver = {
+                .name = "tegra-pmc",
+                .suppress_bind_attrs = true,
+                .of_match_table = tegra_pmc_match,
+                .pm = &tegra_pmc_pm_ops,
+        },
+        .probe = tegra_pmc_probe,
+};
+module_platform_driver(tegra_pmc_driver);
+
+/*
+ * Early initialization to allow access to registers in the very early boot
+ * process.
+ */
+static int __init tegra_pmc_early_init(void)
+{
+        const struct of_device_id *match;
+        struct device_node *np;
+        struct resource regs;
+        bool invert;
+        u32 value;
+
+        if (!soc_is_tegra())
+                return 0;
+
+        np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
+        if (!np) {
+                pr_warn("PMC device node not found, disabling powergating\n");
+
+                regs.start = 0x7000e400;
+                regs.end = 0x7000e7ff;
+                regs.flags = IORESOURCE_MEM;
+
+                pr_warn("Using memory region %pR\n", &regs);
+        } else {
+                pmc->soc = match->data;
+        }
+
+        if (of_address_to_resource(np, 0, &regs) < 0) {
+                pr_err("failed to get PMC registers\n");
+                return -ENXIO;
+        }
+
+        pmc->base = ioremap_nocache(regs.start, resource_size(&regs));
+        if (!pmc->base) {
+                pr_err("failed to map PMC registers\n");
+                return -ENXIO;
+        }
+
+        mutex_init(&pmc->powergates_lock);
+
+        invert = of_property_read_bool(np, "nvidia,invert-interrupt");
+
+        value = tegra_pmc_readl(PMC_CNTRL);
+
+        if (invert)
+                value |= PMC_CNTRL_INTR_POLARITY;
+        else
+                value &= ~PMC_CNTRL_INTR_POLARITY;
+
+        tegra_pmc_writel(value, PMC_CNTRL);
+
+        return 0;
+}
+early_initcall(tegra_pmc_early_init);
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 1c36311935d7..480133ee1eb3 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -1317,19 +1317,6 @@ static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
         .tx_st_done     = 21,
 };
 
-static struct s3c64xx_spi_port_config s5p64x0_spi_port_config = {
-        .fifo_lvl_mask  = { 0x1ff, 0x7F },
-        .rx_lvl_offset  = 15,
-        .tx_st_done     = 25,
-};
-
-static struct s3c64xx_spi_port_config s5pc100_spi_port_config = {
-        .fifo_lvl_mask  = { 0x7f, 0x7F },
-        .rx_lvl_offset  = 13,
-        .tx_st_done     = 21,
-        .high_speed     = true,
-};
-
 static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
         .fifo_lvl_mask  = { 0x1ff, 0x7F },
         .rx_lvl_offset  = 15,
@@ -1362,12 +1349,6 @@ static struct platform_device_id s3c64xx_spi_driver_ids[] = {
                 .name           = "s3c6410-spi",
                 .driver_data    = (kernel_ulong_t)&s3c6410_spi_port_config,
         }, {
-                .name           = "s5p64x0-spi",
-                .driver_data    = (kernel_ulong_t)&s5p64x0_spi_port_config,
-        }, {
-                .name           = "s5pc100-spi",
-                .driver_data    = (kernel_ulong_t)&s5pc100_spi_port_config,
-        }, {
                 .name           = "s5pv210-spi",
                 .driver_data    = (kernel_ulong_t)&s5pv210_spi_port_config,
         }, {
@@ -1384,9 +1365,6 @@ static const struct of_device_id s3c64xx_spi_dt_match[] = {
         { .compatible = "samsung,s3c6410-spi",
                         .data = (void *)&s3c6410_spi_port_config,
         },
-        { .compatible = "samsung,s5pc100-spi",
-                        .data = (void *)&s5pc100_spi_port_config,
-        },
         { .compatible = "samsung,s5pv210-spi",
                         .data = (void *)&s5pv210_spi_port_config,
         },
diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig
index 59c98bfd5a8a..e05a58d759be 100644
--- a/drivers/video/fbdev/Kconfig
+++ b/drivers/video/fbdev/Kconfig
@@ -290,6 +290,12 @@ config FB_ARMCLCD
           here and read <file:Documentation/kbuild/modules.txt>.  The module
           will be called amba-clcd.
 
+# Helper logic selected only by the ARM Versatile platform family.
+config PLAT_VERSATILE_CLCD
+        def_bool ARCH_VERSATILE || ARCH_REALVIEW || ARCH_VEXPRESS
+        depends on ARM
+        depends on FB_ARMCLCD && FB=y
+
 config FB_ACORN
         bool "Acorn VIDC support"
         depends on (FB = y) && ARM && ARCH_ACORN
@@ -2018,8 +2024,8 @@ config FB_TMIO_ACCELL
 
 config FB_S3C
         tristate "Samsung S3C framebuffer support"
-        depends on FB && (CPU_S3C2416 || ARCH_S3C64XX || ARCH_S5P64X0 || \
-                ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
+        depends on FB && (CPU_S3C2416 || ARCH_S3C64XX || \
+                ARCH_S5PV210 || ARCH_EXYNOS)
         select FB_CFB_FILLRECT
         select FB_CFB_COPYAREA
         select FB_CFB_IMAGEBLIT
diff --git a/drivers/video/fbdev/Makefile b/drivers/video/fbdev/Makefile
index 0284f2a12538..0b2090d2e52e 100644
--- a/drivers/video/fbdev/Makefile
+++ b/drivers/video/fbdev/Makefile
@@ -78,6 +78,7 @@ obj-$(CONFIG_FB_ATMEL)		  += atmel_lcdfb.o
 obj-$(CONFIG_FB_PVR2)             += pvr2fb.o
 obj-$(CONFIG_FB_VOODOO1)          += sstfb.o
 obj-$(CONFIG_FB_ARMCLCD)          += amba-clcd.o
+obj-$(CONFIG_PLAT_VERSATILE_CLCD) += amba-clcd-versatile.o
 obj-$(CONFIG_FB_GOLDFISH)         += goldfishfb.o
 obj-$(CONFIG_FB_68328)            += 68328fb.o
 obj-$(CONFIG_FB_GBE)              += gbefb.o
diff --git a/arch/arm/plat-versatile/clcd.c b/drivers/video/fbdev/amba-clcd-versatile.c
index 6628cc27efc5..7a8afcd4573e 100644
--- a/arch/arm/plat-versatile/clcd.c
+++ b/drivers/video/fbdev/amba-clcd-versatile.c
@@ -2,7 +2,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
-#include <plat/clcd.h>
+#include <linux/platform_data/video-clcd-versatile.h>
 
 static struct clcd_panel vga = {
         .mode           = {
diff --git a/drivers/video/fbdev/s3c-fb.c b/drivers/video/fbdev/s3c-fb.c
index 62acae2694a9..b33abb0a433d 100644
--- a/drivers/video/fbdev/s3c-fb.c
+++ b/drivers/video/fbdev/s3c-fb.c
@@ -1805,38 +1805,6 @@ static struct s3c_fb_driverdata s3c_fb_data_64xx = {
         .win[4] = &s3c_fb_data_64xx_wins[4],
 };
 
-static struct s3c_fb_driverdata s3c_fb_data_s5pc100 = {
-        .variant = {
-                .nr_windows     = 5,
-                .vidtcon        = VIDTCON0,
-                .wincon         = WINCON(0),
-                .winmap         = WINxMAP(0),
-                .keycon         = WKEYCON,
-                .osd            = VIDOSD_BASE,
-                .osd_stride     = 16,
-                .buf_start      = VIDW_BUF_START(0),
-                .buf_size       = VIDW_BUF_SIZE(0),
-                .buf_end        = VIDW_BUF_END(0),
-
-                .palette = {
-                        [0] = 0x2400,
-                        [1] = 0x2800,
-                        [2] = 0x2c00,
-                        [3] = 0x3000,
-                        [4] = 0x3400,
-                },
-
-                .has_prtcon     = 1,
-                .has_blendcon   = 1,
-                .has_clksel     = 1,
-        },
-        .win[0] = &s3c_fb_data_s5p_wins[0],
-        .win[1] = &s3c_fb_data_s5p_wins[1],
-        .win[2] = &s3c_fb_data_s5p_wins[2],
-        .win[3] = &s3c_fb_data_s5p_wins[3],
-        .win[4] = &s3c_fb_data_s5p_wins[4],
-};
-
 static struct s3c_fb_driverdata s3c_fb_data_s5pv210 = {
         .variant = {
                 .nr_windows     = 5,
@@ -1970,41 +1938,11 @@ static struct s3c_fb_driverdata s3c_fb_data_s3c2443 = {
         },
 };
 
-static struct s3c_fb_driverdata s3c_fb_data_s5p64x0 = {
-        .variant = {
-                .nr_windows     = 3,
-                .vidtcon        = VIDTCON0,
-                .wincon         = WINCON(0),
-                .winmap         = WINxMAP(0),
-                .keycon         = WKEYCON,
-                .osd            = VIDOSD_BASE,
-                .osd_stride     = 16,
-                .buf_start      = VIDW_BUF_START(0),
-                .buf_size       = VIDW_BUF_SIZE(0),
-                .buf_end        = VIDW_BUF_END(0),
-
-                .palette = {
-                        [0] = 0x2400,
-                        [1] = 0x2800,
-                        [2] = 0x2c00,
-                },
-
-                .has_blendcon   = 1,
-                .has_fixvclk    = 1,
-        },
-        .win[0] = &s3c_fb_data_s5p_wins[0],
-        .win[1] = &s3c_fb_data_s5p_wins[1],
-        .win[2] = &s3c_fb_data_s5p_wins[2],
-};
-
 static struct platform_device_id s3c_fb_driver_ids[] = {
         {
                 .name           = "s3c-fb",
                 .driver_data    = (unsigned long)&s3c_fb_data_64xx,
         }, {
-                .name           = "s5pc100-fb",
-                .driver_data    = (unsigned long)&s3c_fb_data_s5pc100,
-        }, {
                 .name           = "s5pv210-fb",
                 .driver_data    = (unsigned long)&s3c_fb_data_s5pv210,
         }, {
@@ -2016,9 +1954,6 @@ static struct platform_device_id s3c_fb_driver_ids[] = {
         }, {
                 .name           = "s3c2443-fb",
                 .driver_data    = (unsigned long)&s3c_fb_data_s3c2443,
-        }, {
-                .name           = "s5p64x0-fb",
-                .driver_data    = (unsigned long)&s3c_fb_data_s5p64x0,
         },
         {},
 };
diff --git a/include/linux/platform_data/video-clcd-versatile.h b/include/linux/platform_data/video-clcd-versatile.h
new file mode 100644
index 000000000000..09ccf182af4d
--- /dev/null
+++ b/include/linux/platform_data/video-clcd-versatile.h
@@ -0,0 +1,27 @@
+#ifndef PLAT_CLCD_H
+#define PLAT_CLCD_H
+
+#ifdef CONFIG_PLAT_VERSATILE_CLCD
+struct clcd_panel *versatile_clcd_get_panel(const char *);
+int versatile_clcd_setup_dma(struct clcd_fb *, unsigned long);
+int versatile_clcd_mmap_dma(struct clcd_fb *, struct vm_area_struct *);
+void versatile_clcd_remove_dma(struct clcd_fb *);
+#else
+static inline struct clcd_panel *versatile_clcd_get_panel(const char *s)
+{
+        return NULL;
+}
+static inline int versatile_clcd_setup_dma(struct clcd_fb *fb, unsigned long framesize)
+{
+        return -ENODEV;
+}
+static inline int versatile_clcd_mmap_dma(struct clcd_fb *fb, struct vm_area_struct *vm)
+{
+        return -ENODEV;
+}
+static inline void versatile_clcd_remove_dma(struct clcd_fb *fb)
+{
+}
+#endif
+
+#endif
diff --git a/include/linux/tegra-soc.h b/include/linux/tegra-soc.h
deleted file mode 100644
index 95f611d78f3a..000000000000
--- a/include/linux/tegra-soc.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef __LINUX_TEGRA_SOC_H_
-#define __LINUX_TEGRA_SOC_H_
-
-u32 tegra_read_chipid(void);
-
-#endif /* __LINUX_TEGRA_SOC_H_ */
diff --git a/include/linux/tegra-ahb.h b/include/soc/tegra/ahb.h
index f1cd075ceee1..504eb6f957e5 100644
--- a/include/linux/tegra-ahb.h
+++ b/include/soc/tegra/ahb.h
@@ -11,9 +11,9 @@
  * more details.
  */
 
-#ifndef __LINUX_AHB_H__
-#define __LINUX_AHB_H__
+#ifndef __SOC_TEGRA_AHB_H__
+#define __SOC_TEGRA_AHB_H__
 
 extern int tegra_ahb_enable_smmu(struct device_node *ahb);
 
-#endif  /* __LINUX_AHB_H__ */
+#endif /* __SOC_TEGRA_AHB_H__ */
diff --git a/include/soc/tegra/common.h b/include/soc/tegra/common.h
new file mode 100644
index 000000000000..fc13a9a134e9
--- /dev/null
+++ b/include/soc/tegra/common.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2014 NVIDIA Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __SOC_TEGRA_COMMON_H__
+#define __SOC_TEGRA_COMMON_H__
+
+bool soc_is_tegra(void);
+
+#endif /* __SOC_TEGRA_COMMON_H__ */
diff --git a/include/linux/tegra-cpuidle.h b/include/soc/tegra/cpuidle.h
index 9c6286bbf662..ea04f4225638 100644
--- a/include/linux/tegra-cpuidle.h
+++ b/include/soc/tegra/cpuidle.h
@@ -11,8 +11,8 @@
  * more details.
  */
 
-#ifndef __LINUX_TEGRA_CPUIDLE_H__
-#define __LINUX_TEGRA_CPUIDLE_H__
+#ifndef __SOC_TEGRA_CPUIDLE_H__
+#define __SOC_TEGRA_CPUIDLE_H__
 
 #ifdef CONFIG_CPU_IDLE
 void tegra_cpuidle_pcie_irqs_in_use(void);
@@ -22,4 +22,4 @@ static inline void tegra_cpuidle_pcie_irqs_in_use(void)
 }
 #endif
 
-#endif
+#endif /* __SOC_TEGRA_CPUIDLE_H__ */
diff --git a/include/soc/tegra/fuse.h b/include/soc/tegra/fuse.h
new file mode 100644
index 000000000000..8e1249474e84
--- /dev/null
+++ b/include/soc/tegra/fuse.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __SOC_TEGRA_FUSE_H__
+#define __SOC_TEGRA_FUSE_H__
+
+#define TEGRA20         0x20
+#define TEGRA30         0x30
+#define TEGRA114        0x35
+#define TEGRA124        0x40
+
+#define TEGRA_FUSE_SKU_CALIB_0  0xf0
+#define TEGRA30_FUSE_SATA_CALIB 0x124
+
+#ifndef __ASSEMBLY__
+
+u32 tegra_read_chipid(void);
+u8 tegra_get_chip_id(void);
+
+enum tegra_revision {
+        TEGRA_REVISION_UNKNOWN = 0,
+        TEGRA_REVISION_A01,
+        TEGRA_REVISION_A02,
+        TEGRA_REVISION_A03,
+        TEGRA_REVISION_A03p,
+        TEGRA_REVISION_A04,
+        TEGRA_REVISION_MAX,
+};
+
+struct tegra_sku_info {
+        int sku_id;
+        int cpu_process_id;
+        int cpu_speedo_id;
+        int cpu_speedo_value;
+        int cpu_iddq_value;
+        int core_process_id;
+        int soc_speedo_id;
+        int gpu_speedo_id;
+        int gpu_process_id;
+        int gpu_speedo_value;
+        enum tegra_revision revision;
+};
+
+u32 tegra_read_straps(void);
+u32 tegra_read_chipid(void);
+int tegra_fuse_readl(unsigned long offset, u32 *value);
+
+extern struct tegra_sku_info tegra_sku_info;
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __SOC_TEGRA_FUSE_H__ */
diff --git a/include/soc/tegra/pm.h b/include/soc/tegra/pm.h
new file mode 100644
index 000000000000..30fe2078a547
--- /dev/null
+++ b/include/soc/tegra/pm.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2014 NVIDIA Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __SOC_TEGRA_PM_H__
+#define __SOC_TEGRA_PM_H__
+
+enum tegra_suspend_mode {
+        TEGRA_SUSPEND_NONE = 0,
+        TEGRA_SUSPEND_LP2, /* CPU voltage off */
+        TEGRA_SUSPEND_LP1, /* CPU voltage off, DRAM self-refresh */
+        TEGRA_SUSPEND_LP0, /* CPU + core voltage off, DRAM self-refresh */
+        TEGRA_MAX_SUSPEND_MODE,
+};
+
+#ifdef CONFIG_PM_SLEEP
+enum tegra_suspend_mode
+tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode);
+
+/* low-level resume entry point */
+void tegra_resume(void);
+#else
+static inline enum tegra_suspend_mode
+tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode)
+{
+        return TEGRA_SUSPEND_NONE;
+}
+
+static inline void tegra_resume(void)
+{
+}
+#endif /* CONFIG_PM_SLEEP */
+
+#endif /* __SOC_TEGRA_PM_H__ */
diff --git a/include/linux/tegra-powergate.h b/include/soc/tegra/pmc.h
index 46f0a07812b4..65a93273e72f 100644
--- a/include/linux/tegra-powergate.h
+++ b/include/soc/tegra/pmc.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2010 Google, Inc
+ * Copyright (c) 2014 NVIDIA Corporation
  *
  * Author:
  *      Colin Cross <ccross@google.com>
@@ -15,12 +16,34 @@
  *
  */
 
-#ifndef _MACH_TEGRA_POWERGATE_H_
-#define _MACH_TEGRA_POWERGATE_H_
+#ifndef __SOC_TEGRA_PMC_H__
+#define __SOC_TEGRA_PMC_H__
+
+#include <linux/reboot.h>
+
+#include <soc/tegra/pm.h>
 
 struct clk;
 struct reset_control;
 
+void tegra_pmc_restart(enum reboot_mode mode, const char *cmd);
+
+#ifdef CONFIG_PM_SLEEP
+enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
+void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode);
+void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode);
+#endif /* CONFIG_PM_SLEEP */
+
+#ifdef CONFIG_SMP
+bool tegra_pmc_cpu_is_powered(int cpuid);
+int tegra_pmc_cpu_power_on(int cpuid);
+int tegra_pmc_cpu_remove_clamping(int cpuid);
+#endif /* CONFIG_SMP */
+
+/*
+ * powergate and I/O rail APIs
+ */
+
 #define TEGRA_POWERGATE_CPU     0
 #define TEGRA_POWERGATE_3D      1
 #define TEGRA_POWERGATE_VENC    2
@@ -129,6 +152,6 @@ static inline int tegra_io_rail_power_off(int id)
 {
         return -ENOSYS;
 }
-#endif
+#endif /* CONFIG_ARCH_TEGRA */
 
-#endif /* _MACH_TEGRA_POWERGATE_H_ */
+#endif /* __SOC_TEGRA_PMC_H__ */
diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h
index eaad58b5be4a..a20e4a3a8b15 100644
--- a/include/video/samsung_fimd.h
+++ b/include/video/samsung_fimd.h
@@ -108,7 +108,7 @@
 #define VIDCON2_ORGYCbCr                        (1 << 8)
 #define VIDCON2_YUVORDCrCb                      (1 << 7)
 
-/* PRTCON (S3C6410, S5PC100)
+/* PRTCON (S3C6410)
  * Might not be present in the S3C6410 documentation,
  * but tests prove it's there almost for sure; shouldn't hurt in any case.
  */
diff --git a/sound/soc/samsung/goni_wm8994.c b/sound/soc/samsung/goni_wm8994.c
index 9506d7617223..3b527dcfc0aa 100644
--- a/sound/soc/samsung/goni_wm8994.c
+++ b/sound/soc/samsung/goni_wm8994.c
@@ -16,7 +16,7 @@
 #include <sound/jack.h>
 
 #include <asm/mach-types.h>
-#include <mach/gpio.h>
+#include <mach/gpio-samsung.h>
 
 #include "../codecs/wm8994.h"