59 files changed, 453 insertions, 1204 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 01790958e69b..24d955c21d35 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -920,6 +920,7 @@ config ARCH_U300
        select COMMON_CLK
        select GENERIC_GPIO
        select ARCH_REQUIRE_GPIOLIB
+        select SPARSE_IRQ
        help
          Support for ST-Ericsson U300 series mobile platforms.
diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c
index 45c97b1ee9b1..7799e910e271 100644
--- a/arch/arm/mach-bcmring/arch.c
+++ b/arch/arm/mach-bcmring/arch.c
@@ -38,7 +38,7 @@
 #include <mach/csp/chipcHw_def.h>
 #include <mach/csp/chipcHw_inline.h>
-#include <cfg_global.h>
+#include <mach/cfg_global.h>
 #include "core.h"
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
index adbfb1994582..4b50228a6771 100644
--- a/arch/arm/mach-bcmring/core.c
+++ b/arch/arm/mach-bcmring/core.c
@@ -43,11 +43,10 @@
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <cfg_global.h>
+#include <mach/cfg_global.h>
 #include "clock.h"
-#include <csp/secHw.h>
 #include <mach/csp/secHw_def.h>
 #include <mach/csp/chipcHw_inline.h>
 #include <mach/csp/tmrHw_reg.h>
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
index 96273ff34956..5050833817b7 100644
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
@@ -26,15 +26,15 @@
 /* ---- Include Files ---------------------------------------------------- */
-#include <csp/errno.h>
+#include <linux/errno.h>
-#include <csp/stdint.h>
+#include <linux/types.h>
-#include <csp/module.h>
+#include <linux/export.h>
 #include <mach/csp/chipcHw_def.h>
 #include <mach/csp/chipcHw_inline.h>
-#include <csp/reg.h>
+#include <mach/csp/reg.h>
-#include <csp/delay.h>
+#include <linux/delay.h>
 /* ---- Private Constants and Types --------------------------------------- */
@@ -61,21 +61,21 @@ static int chipcHw_divide(int num, int denom)
 /****************************************************************************/
 chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock    /*  [ IN ] Configurable clock */
    ) {
-        volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
+        uint32_t __iomem *pPLLReg = NULL;
-        volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
+        uint32_t __iomem *pClockCtrl = NULL;
-        volatile uint32_t *pDependentClock = (uint32_t *) 0x0;
+        uint32_t __iomem *pDependentClock = NULL;
        uint32_t vcoFreqPll1Hz = 0;     /* Effective VCO frequency for PLL1 in Hz */
        uint32_t vcoFreqPll2Hz = 0;     /* Effective VCO frequency for PLL2 in Hz */
        uint32_t dependentClockType = 0;
        uint32_t vcoHz = 0;
        /* Get VCO frequencies */
-        if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
+        if ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
                uint64_t adjustFreq = 0;
                vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-                    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+                    ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
                     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
                /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
@@ -86,13 +86,13 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock	/*  [ IN ] Configur
        } else {
                vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-                    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+                    ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
                     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
        }
        vcoFreqPll2Hz =
            chipcHw_XTAL_FREQ_Hz *
                 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-            ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+            ((readl(&pChipcHw->PLLPreDivider2) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
             chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
        switch (clock) {
@@ -187,51 +187,51 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock	/*  [ IN ] Configur
        if (pPLLReg) {
                /* Obtain PLL clock frequency */
-                if (*pPLLReg & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
+                if (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
                        /* Return crystal clock frequency when bypassed */
                        return chipcHw_XTAL_FREQ_Hz;
                } else if (clock == chipcHw_CLOCK_DDR) {
                        /* DDR frequency is configured in PLLDivider register */
-                        return chipcHw_divide (vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256));
+                        return chipcHw_divide (vcoHz, (((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) ? ((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) : 256));
                } else {
                        /* From chip revision number B0, LCD clock is internally divided by 2 */
                        if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
                                vcoHz >>= 1;
                        }
                        /* Obtain PLL clock frequency using VCO dividers */
-                        return chipcHw_divide(vcoHz, ((*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
+                        return chipcHw_divide(vcoHz, ((readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ?  (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
                }
        } else if (pClockCtrl) {
                /* Obtain divider clock frequency */
                uint32_t div;
                uint32_t freq = 0;
-                if (*pClockCtrl & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
+                if (readl(pClockCtrl) & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
                        /* Return crystal clock frequency when bypassed */
                        return chipcHw_XTAL_FREQ_Hz;
                } else if (pDependentClock) {
                        /* Identify the dependent clock frequency */
                        switch (dependentClockType) {
                        case PLL_CLOCK:
-                                if (*pDependentClock & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
+                                if (readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
                                        /* Use crystal clock frequency when dependent PLL clock is bypassed */
                                        freq = chipcHw_XTAL_FREQ_Hz;
                                } else {
                                        /* Obtain PLL clock frequency using VCO dividers */
-                                        div = *pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK;
+                                        div = readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_MDIV_MASK;
                                        freq = div ? chipcHw_divide(vcoHz, div) : 0;
                                }
                                break;
                        case NON_PLL_CLOCK:
-                                if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) {
+                                if (pDependentClock == &pChipcHw->ACLKClock) {
                                        freq = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
                                } else {
-                                        if (*pDependentClock & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
+                                        if (readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
                                                /* Use crystal clock frequency when dependent divider clock is bypassed */
                                                freq = chipcHw_XTAL_FREQ_Hz;
                                        } else {
                                                /* Obtain divider clock frequency using XTAL dividers */
-                                                div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK;
+                                                div = readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_DIV_MASK;
                                                freq = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, (div ? div : 256));
                                        }
                                }
@@ -242,7 +242,7 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock	/*  [ IN ] Configur
                        freq = chipcHw_XTAL_FREQ_Hz;
                }
-                div = *pClockCtrl & chipcHw_REG_DIV_CLOCK_DIV_MASK;
+                div = readl(pClockCtrl) & chipcHw_REG_DIV_CLOCK_DIV_MASK;
                return chipcHw_divide(freq, (div ? div : 256));
        }
        return 0;
@@ -261,9 +261,9 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock	/*  [ IN ] Configur
 chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,   /*  [ IN ] Configurable clock */
                                       uint32_t freq    /*  [ IN ] Clock frequency in Hz */
    ) {
-        volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
+        uint32_t __iomem *pPLLReg = NULL;
-        volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
+        uint32_t __iomem *pClockCtrl = NULL;
-        volatile uint32_t *pDependentClock = (uint32_t *) 0x0;
+        uint32_t __iomem *pDependentClock = NULL;
        uint32_t vcoFreqPll1Hz = 0;     /* Effective VCO frequency for PLL1 in Hz */
        uint32_t desVcoFreqPll1Hz = 0;  /* Desired VCO frequency for PLL1 in Hz */
        uint32_t vcoFreqPll2Hz = 0;     /* Effective VCO frequency for PLL2 in Hz */
@@ -272,12 +272,12 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,	/*  [ IN ] Configu
        uint32_t desVcoHz = 0;
        /* Get VCO frequencies */
-        if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
+        if ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
                uint64_t adjustFreq = 0;
                vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-                    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+                    ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
                     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
                /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
@@ -289,16 +289,16 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,	/*  [ IN ] Configu
                /* Desired VCO frequency */
                desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-                    (((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+                    (((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
                      chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) + 1);
        } else {
                vcoFreqPll1Hz = desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-                    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+                    ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
                     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
        }
        vcoFreqPll2Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-            ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+            ((readl(&pChipcHw->PLLPreDivider2) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
             chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
        switch (clock) {
@@ -307,8 +307,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,	/*  [ IN ] Configu
                {
                        REG_LOCAL_IRQ_SAVE;
                        /* Dvide DDR_phy by two to obtain DDR_ctrl clock */
-                        pChipcHw->DDRClock = (pChipcHw->DDRClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1)
+                        writel((readl(&pChipcHw->DDRClock) & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT), &pChipcHw->DDRClock);
-                                << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT);
                        REG_LOCAL_IRQ_RESTORE;
                }
                pPLLReg = &pChipcHw->DDRClock;
@@ -329,8 +328,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,	/*  [ IN ] Configu
                /* Configure the VPM:BUS ratio settings */
                {
                        REG_LOCAL_IRQ_SAVE;
-                        pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1)
+                        writel((readl(&pChipcHw->VPMClock) & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT), &pChipcHw->VPMClock);
-                                << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT);
                        REG_LOCAL_IRQ_RESTORE;
                }
                pPLLReg = &pChipcHw->VPMClock;
@@ -428,9 +426,9 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,	/*  [ IN ] Configu
                /* For DDR settings use only the PLL divider clock */
                if (pPLLReg == &pChipcHw->DDRClock) {
                        /* Set M1DIV for PLL1, which controls the DDR clock */
-                        reg32_write(&pChipcHw->PLLDivider, (pChipcHw->PLLDivider & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24));
+                        reg32_write(&pChipcHw->PLLDivider, (readl(&pChipcHw->PLLDivider) & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24));
                        /* Calculate expected frequency */
-                        freq = chipcHw_divide(vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256));
+                        freq = chipcHw_divide(vcoHz, (((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) ? ((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) : 256));
                } else {
                        /* From chip revision number B0, LCD clock is internally divided by 2 */
                        if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
@@ -441,7 +439,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,	/*  [ IN ] Configu
                        reg32_modify_and(pPLLReg, ~(chipcHw_REG_PLL_CLOCK_MDIV_MASK));
                        reg32_modify_or(pPLLReg, chipcHw_REG_PLL_DIVIDER_MDIV(desVcoHz, freq));
                        /* Calculate expected frequency */
-                        freq = chipcHw_divide(vcoHz, ((*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
+                        freq = chipcHw_divide(vcoHz, ((readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
                }
                /* Wait for for atleast 200ns as per the protocol to change frequency */
                udelay(1);
@@ -460,16 +458,16 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,	/*  [ IN ] Configu
                if (pDependentClock) {
                        switch (dependentClockType) {
                        case PLL_CLOCK:
-                                divider = chipcHw_divide(chipcHw_divide (desVcoHz, (*pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq);
+                                divider = chipcHw_divide(chipcHw_divide (desVcoHz, (readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq);
                                break;
                        case NON_PLL_CLOCK:
                                {
                                        uint32_t sourceClock = 0;
-                                        if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) {
+                                        if (pDependentClock == &pChipcHw->ACLKClock) {
                                                sourceClock = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
                                        } else {
-                                                uint32_t div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK;
+                                                uint32_t div = readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_DIV_MASK;
                                                sourceClock = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, ((div) ? div : 256));
                                        }
                                        divider = chipcHw_divide(sourceClock, freq);
@@ -483,7 +481,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,	/*  [ IN ] Configu
                if (divider) {
                        REG_LOCAL_IRQ_SAVE;
                        /* Set the divider to obtain the required frequency */
-                        *pClockCtrl = (*pClockCtrl & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK);
+                        writel((readl(pClockCtrl) & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK), pClockCtrl);
                        REG_LOCAL_IRQ_RESTORE;
                        return freq;
                }
@@ -515,25 +513,26 @@ static int vpmPhaseAlignA0(void)
        int count = 0;
        for (iter = 0; (iter < MAX_PHASE_ALIGN_ATTEMPTS) && (adjustCount < MAX_PHASE_ADJUST_COUNT); iter++) {
-                phaseControl = (pChipcHw->VPMClock & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT;
+                phaseControl = (readl(&pChipcHw->VPMClock) & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT;
                phaseValue = 0;
                prevPhaseComp = 0;
                /* Step 1: Look for falling PH_COMP transition */
                /* Read the contents of VPM Clock resgister */
-                phaseValue = pChipcHw->VPMClock;
+                phaseValue = readl(&pChipcHw->VPMClock);
                do {
                        /* Store previous value of phase comparator */
                        prevPhaseComp = phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP;
                        /* Change the value of PH_CTRL. */
-                        reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                        reg32_write(&pChipcHw->VPMClock,
+                        (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
                        /* Wait atleast 20 ns */
                        udelay(1);
                        /* Toggle the LOAD_CH after phase control is written. */
-                        pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+                        writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
                        /* Read the contents of  VPM Clock resgister. */
-                        phaseValue = pChipcHw->VPMClock;
+                        phaseValue = readl(&pChipcHw->VPMClock);
                        if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
                                phaseControl = (0x3F & (phaseControl - 1));
@@ -557,12 +556,13 @@ static int vpmPhaseAlignA0(void)
                for (count = 0; (count < 5) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
                        phaseControl = (0x3F & (phaseControl + 1));
-                        reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                        reg32_write(&pChipcHw->VPMClock,
+                        (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
                        /* Wait atleast 20 ns */
                        udelay(1);
                        /* Toggle the LOAD_CH after phase control is written. */
-                        pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+                        writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
-                        phaseValue = pChipcHw->VPMClock;
+                        phaseValue = readl(&pChipcHw->VPMClock);
                        /* Count number of adjustment made */
                        adjustCount++;
                }
@@ -581,12 +581,13 @@ static int vpmPhaseAlignA0(void)
                for (count = 0; (count < 3) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
                        phaseControl = (0x3F & (phaseControl - 1));
-                        reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                        reg32_write(&pChipcHw->VPMClock,
+                        (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
                        /* Wait atleast 20 ns */
                        udelay(1);
                        /* Toggle the LOAD_CH after phase control is written. */
-                        pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+                        writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
-                        phaseValue = pChipcHw->VPMClock;
+                        phaseValue = readl(&pChipcHw->VPMClock);
                        /* Count number of adjustment made */
                        adjustCount++;
                }
@@ -605,12 +606,13 @@ static int vpmPhaseAlignA0(void)
                for (count = 0; (count < 5); count++) {
                        phaseControl = (0x3F & (phaseControl - 1));
-                        reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                        reg32_write(&pChipcHw->VPMClock,
+                        (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
                        /* Wait atleast 20 ns */
                        udelay(1);
                        /* Toggle the LOAD_CH after phase control is written. */
-                        pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+                        writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
-                        phaseValue = pChipcHw->VPMClock;
+                        phaseValue = readl(&pChipcHw->VPMClock);
                        /* Count number of adjustment made */
                        adjustCount++;
                }
@@ -631,14 +633,14 @@ static int vpmPhaseAlignA0(void)
                        /* Store previous value of phase comparator */
                        prevPhaseComp = phaseValue;
                        /* Change the value of PH_CTRL. */
-                        reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                        reg32_write(&pChipcHw->VPMClock,
+                        (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
                        /* Wait atleast 20 ns */
                        udelay(1);
                        /* Toggle the LOAD_CH after phase control is written. */
-                        pChipcHw->VPMClock ^=
+                        writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
-                            chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
                        /* Read the contents of  VPM Clock resgister. */
-                        phaseValue = pChipcHw->VPMClock;
+                        phaseValue = readl(&pChipcHw->VPMClock);
                        if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
                                phaseControl = (0x3F & (phaseControl - 1));
@@ -661,13 +663,13 @@ static int vpmPhaseAlignA0(void)
        }
        /* For VPM Phase should be perfectly aligned. */
-        phaseControl = (((pChipcHw->VPMClock >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F);
+        phaseControl = (((readl(&pChipcHw->VPMClock) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F);
        {
                REG_LOCAL_IRQ_SAVE;
-                pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT);
+                writel((readl(&pChipcHw->VPMClock) & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT), &pChipcHw->VPMClock);
                /* Load new phase value */
-                pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+                writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
                REG_LOCAL_IRQ_RESTORE;
        }
@@ -697,7 +699,7 @@ int chipcHw_vpmPhaseAlign(void)
                int adjustCount = 0;
                /* Disable VPM access */
-                pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
+                writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1);
                /* Disable HW VPM phase alignment  */
                chipcHw_vpmHwPhaseAlignDisable();
                /* Enable SW VPM phase alignment  */
@@ -715,23 +717,24 @@ int chipcHw_vpmPhaseAlign(void)
                                phaseControl--;
                        } else {
                                /* Enable VPM access */
-                                pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
+                                writel(readl(&pChipcHw->Spare1) | chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1);
                                /* Return adjust count */
                                return adjustCount;
                        }
                        /* Change the value of PH_CTRL. */
-                        reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                        reg32_write(&pChipcHw->VPMClock,
+                        (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
                        /* Wait atleast 20 ns */
                        udelay(1);
                        /* Toggle the LOAD_CH after phase control is written. */
-                        pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+                        writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
                        /* Count adjustment */
                        adjustCount++;
                }
        }
        /* Disable VPM access */
-        pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
+        writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1);
        return -1;
 }
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
index 367df75d4bb3..8377d8054168 100644
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
@@ -26,15 +26,15 @@
 /* ---- Include Files ---------------------------------------------------- */
-#include <csp/errno.h>
+#include <linux/errno.h>
-#include <csp/stdint.h>
+#include <linux/types.h>
-#include <csp/module.h>
+#include <linux/export.h>
 #include <mach/csp/chipcHw_def.h>
 #include <mach/csp/chipcHw_inline.h>
-#include <csp/reg.h>
+#include <mach/csp/reg.h>
-#include <csp/delay.h>
+#include <linux/delay.h>
 /* ---- Private Constants and Types --------------------------------------- */
 /*
@@ -73,9 +73,9 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz)
        {
                REG_LOCAL_IRQ_SAVE;
-                pChipcHw->PLLConfig2 =
+                writel(chipcHw_REG_PLL_CONFIG_D_RESET |
-                    chipcHw_REG_PLL_CONFIG_D_RESET |
+                       chipcHw_REG_PLL_CONFIG_A_RESET,
-                    chipcHw_REG_PLL_CONFIG_A_RESET;
+                        &pChipcHw->PLLConfig2);
                pllPreDivider2 = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
                    chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
@@ -87,28 +87,30 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz)
                     chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
                /* Enable CHIPC registers to control the PLL */
-                pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
+                writel(readl(&pChipcHw->PLLStatus) | chipcHw_REG_PLL_STATUS_CONTROL_ENABLE, &pChipcHw->PLLStatus);
                /* Set pre divider to get desired VCO frequency */
-                pChipcHw->PLLPreDivider2 = pllPreDivider2;
+                writel(pllPreDivider2, &pChipcHw->PLLPreDivider2);
                /* Set NDIV Frac */
-                pChipcHw->PLLDivider2 = chipcHw_REG_PLL_DIVIDER_NDIV_f;
+                writel(chipcHw_REG_PLL_DIVIDER_NDIV_f, &pChipcHw->PLLDivider2);
                /* This has to be removed once the default values are fixed for PLL2. */
-                pChipcHw->PLLControl12 = 0x38000700;
+                writel(0x38000700, &pChipcHw->PLLControl12);
-                pChipcHw->PLLControl22 = 0x00000015;
+                writel(0x00000015, &pChipcHw->PLLControl22);
                /* Reset PLL2 */
                if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
-                        pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
+                        writel(chipcHw_REG_PLL_CONFIG_D_RESET |
                            chipcHw_REG_PLL_CONFIG_A_RESET |
                            chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
-                            chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+                            chipcHw_REG_PLL_CONFIG_POWER_DOWN,
+                            &pChipcHw->PLLConfig2);
                } else {
-                        pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
+                        writel(chipcHw_REG_PLL_CONFIG_D_RESET |
                            chipcHw_REG_PLL_CONFIG_A_RESET |
                            chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
-                            chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+                            chipcHw_REG_PLL_CONFIG_POWER_DOWN,
+                            &pChipcHw->PLLConfig2);
                }
                REG_LOCAL_IRQ_RESTORE;
        }
@@ -119,22 +121,25 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz)
        {
                REG_LOCAL_IRQ_SAVE;
                /* Remove analog reset and Power on the PLL */
-                pChipcHw->PLLConfig2 &=
+                writel(readl(&pChipcHw->PLLConfig2) &
                    ~(chipcHw_REG_PLL_CONFIG_A_RESET |
-                      chipcHw_REG_PLL_CONFIG_POWER_DOWN);
+                      chipcHw_REG_PLL_CONFIG_POWER_DOWN),
+                      &pChipcHw->PLLConfig2);
                REG_LOCAL_IRQ_RESTORE;
        }
        /* Wait until PLL is locked */
-        while (!(pChipcHw->PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
+        while (!(readl(&pChipcHw->PLLStatus2) & chipcHw_REG_PLL_STATUS_LOCKED))
                ;
        {
                REG_LOCAL_IRQ_SAVE;
                /* Remove digital reset */
-                pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
+                writel(readl(&pChipcHw->PLLConfig2) &
+                        ~chipcHw_REG_PLL_CONFIG_D_RESET,
+                        &pChipcHw->PLLConfig2);
                REG_LOCAL_IRQ_RESTORE;
        }
@@ -157,9 +162,9 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport)
        {
                REG_LOCAL_IRQ_SAVE;
-                pChipcHw->PLLConfig =
+                writel(chipcHw_REG_PLL_CONFIG_D_RESET |
-                    chipcHw_REG_PLL_CONFIG_D_RESET |
+                    chipcHw_REG_PLL_CONFIG_A_RESET,
-                    chipcHw_REG_PLL_CONFIG_A_RESET;
+                    &pChipcHw->PLLConfig);
                /* Setting VCO frequency */
                if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
                        pllPreDivider =
@@ -182,30 +187,22 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport)
                }
                /* Enable CHIPC registers to control the PLL */
-                pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
+                writel(readl(&pChipcHw->PLLStatus) | chipcHw_REG_PLL_STATUS_CONTROL_ENABLE, &pChipcHw->PLLStatus);
                /* Set pre divider to get desired VCO frequency */
-                pChipcHw->PLLPreDivider = pllPreDivider;
+                writel(pllPreDivider, &pChipcHw->PLLPreDivider);
                /* Set NDIV Frac */
                if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
-                        pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
+                        writel(chipcHw_REG_PLL_DIVIDER_M1DIV | chipcHw_REG_PLL_DIVIDER_NDIV_f_SS, &pChipcHw->PLLDivider);
-                            chipcHw_REG_PLL_DIVIDER_NDIV_f_SS;
                } else {
-                        pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
+                        writel(chipcHw_REG_PLL_DIVIDER_M1DIV | chipcHw_REG_PLL_DIVIDER_NDIV_f, &pChipcHw->PLLDivider);
-                            chipcHw_REG_PLL_DIVIDER_NDIV_f;
                }
                /* Reset PLL1 */
                if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
-                        pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
+                        writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_1601_3200 | chipcHw_REG_PLL_CONFIG_POWER_DOWN, &pChipcHw->PLLConfig);
-                            chipcHw_REG_PLL_CONFIG_A_RESET |
-                            chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
-                            chipcHw_REG_PLL_CONFIG_POWER_DOWN;
                } else {
-                        pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
+                        writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_800_1600 | chipcHw_REG_PLL_CONFIG_POWER_DOWN, &pChipcHw->PLLConfig);
-                            chipcHw_REG_PLL_CONFIG_A_RESET |
-                            chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
-                            chipcHw_REG_PLL_CONFIG_POWER_DOWN;
                }
                REG_LOCAL_IRQ_RESTORE;
@@ -216,22 +213,19 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport)
                {
                        REG_LOCAL_IRQ_SAVE;
                        /* Remove analog reset and Power on the PLL */
-                        pChipcHw->PLLConfig &=
+                        writel(readl(&pChipcHw->PLLConfig) & ~(chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_POWER_DOWN), &pChipcHw->PLLConfig);
-                            ~(chipcHw_REG_PLL_CONFIG_A_RESET |
-                              chipcHw_REG_PLL_CONFIG_POWER_DOWN);
                        REG_LOCAL_IRQ_RESTORE;
                }
                /* Wait until PLL is locked */
-                while (!(pChipcHw->PLLStatus & chipcHw_REG_PLL_STATUS_LOCKED)
+                while (!(readl(&pChipcHw->PLLStatus) & chipcHw_REG_PLL_STATUS_LOCKED)
-                       || !(pChipcHw->
+                       || !(readl(&pChipcHw->PLLStatus2) & chipcHw_REG_PLL_STATUS_LOCKED))
-                            PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
                        ;
                /* Remove digital reset */
                {
                        REG_LOCAL_IRQ_SAVE;
-                        pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
+                        writel(readl(&pChipcHw->PLLConfig) & ~chipcHw_REG_PLL_CONFIG_D_RESET, &pChipcHw->PLLConfig);
                        REG_LOCAL_IRQ_RESTORE;
                }
        }
@@ -267,11 +261,7 @@ void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam	/*  [ IN ] Misc chip initializ
        chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_SOFT_RESET);
        /* Before configuring the ARM clock, atleast we need to make sure BUS clock maintains the proper ratio with ARM clock */
-        pChipcHw->ACLKClock =
+        writel((readl(&pChipcHw->ACLKClock) & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam-> armBusRatio & chipcHw_REG_ACLKClock_CLK_DIV_MASK), &pChipcHw->ACLKClock);
-            (pChipcHw->
-             ACLKClock & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam->
-                                                                 armBusRatio &
-                                                                 chipcHw_REG_ACLKClock_CLK_DIV_MASK);
        /* Set various core component frequencies. The order in which this is done is important for some. */
        /* The RTBUS (DDR PHY) is derived from the BUS, and the BUS from the ARM, and VPM needs to know BUS */
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
index 2671d8896bbb..f95ce913fa1e 100644
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
@@ -13,11 +13,11 @@
 *****************************************************************************/
 /* ---- Include Files ---------------------------------------------------- */
-#include <csp/stdint.h>
+#include <linux/types.h>
 #include <mach/csp/chipcHw_def.h>
 #include <mach/csp/chipcHw_inline.h>
-#include <csp/intcHw.h>
+#include <mach/csp/intcHw_reg.h>
-#include <csp/cache.h>
+#include <asm/cacheflush.h>
 /* ---- Private Constants and Types --------------------------------------- */
 /* ---- Private Variables ------------------------------------------------- */
@@ -50,17 +50,18 @@ void chipcHw_reset(uint32_t mask)
                        chipcHw_softReset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
                }
                /* Bypass the PLL clocks before reboot */
-                pChipcHw->UARTClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
+                writel(readl(&pChipcHw->UARTClock) | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT,
-                pChipcHw->SPIClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
+                        &pChipcHw->UARTClock);
+                writel(readl(&pChipcHw->SPIClock) | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT,
+                        &pChipcHw->SPIClock);
                /* Copy the chipcHw_warmReset_run_from_aram function into ARAM */
                do {
-                        ((uint32_t *) MM_IO_BASE_ARAM)[i] =
+                        writel(((uint32_t *) &chipcHw_reset_run_from_aram)[i], ((uint32_t __iomem *) MM_IO_BASE_ARAM) + i);
-                            ((uint32_t *) &chipcHw_reset_run_from_aram)[i];
                        i++;
-                } while (((uint32_t *) MM_IO_BASE_ARAM)[i - 1] != 0xe1a0f00f);  /* 0xe1a0f00f == asm ("mov r15, r15"); */
+                } while (readl(((uint32_t __iomem*) MM_IO_BASE_ARAM) + i - 1) != 0xe1a0f00f);   /* 0xe1a0f00f == asm ("mov r15, r15"); */
-                CSP_CACHE_FLUSH_ALL;
+                flush_cache_all();
                /* run the function from ARAM */
                runFunc();
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
index 6b9be2e98e51..547f746c7ff4 100644
--- a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
+++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
@@ -25,11 +25,11 @@
 /****************************************************************************/
 /* ---- Include Files ---------------------------------------------------- */
-#include <csp/stdint.h>
+#include <linux/types.h>
-#include <csp/string.h>
+#include <linux/string.h>
-#include <stddef.h>
+#include <linux/stddef.h>
-#include <csp/dmacHw.h>
+#include <mach/csp/dmacHw.h>
 #include <mach/csp/dmacHw_reg.h>
 #include <mach/csp/dmacHw_priv.h>
 #include <mach/csp/chipcHw_inline.h>
@@ -55,33 +55,32 @@ static uint32_t GetFifoSize(dmacHw_HANDLE_t handle	/*   [ IN ] DMA Channel handl
    ) {
        uint32_t val = 0;
        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-        dmacHw_MISC_t *pMiscReg =
+        dmacHw_MISC_t __iomem *pMiscReg = (void __iomem *)dmacHw_REG_MISC_BASE(pCblk->module);
-            (dmacHw_MISC_t *) dmacHw_REG_MISC_BASE(pCblk->module);
        switch (pCblk->channel) {
        case 0:
-                val = (pMiscReg->CompParm2.lo & 0x70000000) >> 28;
+                val = (readl(&pMiscReg->CompParm2.lo) & 0x70000000) >> 28;
                break;
        case 1:
-                val = (pMiscReg->CompParm3.hi & 0x70000000) >> 28;
+                val = (readl(&pMiscReg->CompParm3.hi) & 0x70000000) >> 28;
                break;
        case 2:
-                val = (pMiscReg->CompParm3.lo & 0x70000000) >> 28;
+                val = (readl(&pMiscReg->CompParm3.lo) & 0x70000000) >> 28;
                break;
        case 3:
-                val = (pMiscReg->CompParm4.hi & 0x70000000) >> 28;
+                val = (readl(&pMiscReg->CompParm4.hi) & 0x70000000) >> 28;
                break;
        case 4:
-                val = (pMiscReg->CompParm4.lo & 0x70000000) >> 28;
+                val = (readl(&pMiscReg->CompParm4.lo) & 0x70000000) >> 28;
                break;
        case 5:
-                val = (pMiscReg->CompParm5.hi & 0x70000000) >> 28;
+                val = (readl(&pMiscReg->CompParm5.hi) & 0x70000000) >> 28;
                break;
        case 6:
-                val = (pMiscReg->CompParm5.lo & 0x70000000) >> 28;
+                val = (readl(&pMiscReg->CompParm5.lo) & 0x70000000) >> 28;
                break;
        case 7:
-                val = (pMiscReg->CompParm6.hi & 0x70000000) >> 28;
+                val = (readl(&pMiscReg->CompParm6.hi) & 0x70000000) >> 28;
                break;
        }
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
index a1f328357aa4..fe438699d11e 100644
--- a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
+++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
@@ -26,10 +26,10 @@
 /* ---- Include Files ---------------------------------------------------- */
-#include <csp/stdint.h>
+#include <linux/types.h>
-#include <stddef.h>
+#include <linux/stddef.h>
-#include <csp/dmacHw.h>
+#include <mach/csp/dmacHw.h>
 #include <mach/csp/dmacHw_reg.h>
 #include <mach/csp/dmacHw_priv.h>
diff --git a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
index 16225e43f3c3..dc4137ff75ca 100644
--- a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
+++ b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
@@ -26,10 +26,10 @@
 /* ---- Include Files ---------------------------------------------------- */
-#include <csp/errno.h>
+#include <linux/errno.h>
-#include <csp/stdint.h>
+#include <linux/types.h>
-#include <csp/tmrHw.h>
+#include <mach/csp/tmrHw.h>
 #include <mach/csp/tmrHw_reg.h>
 #define tmrHw_ASSERT(a)                     if (!(a)) *(char *)0 = 0
diff --git a/arch/arm/mach-bcmring/include/cfg_global.h b/arch/arm/mach-bcmring/include/cfg_global.h
deleted file mode 100644
index f01da877148e..000000000000
--- a/arch/arm/mach-bcmring/include/cfg_global.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _CFG_GLOBAL_H_
-#define _CFG_GLOBAL_H_
-#include <cfg_global_defines.h>
-#define CFG_GLOBAL_CHIP                         BCM11107
-#define CFG_GLOBAL_CHIP_FAMILY                  CFG_GLOBAL_CHIP_FAMILY_BCMRING
-#define CFG_GLOBAL_CHIP_REV                     0xB0
-#define CFG_GLOBAL_RAM_SIZE                     0x10000000
-#define CFG_GLOBAL_RAM_BASE                     0x00000000
-#define CFG_GLOBAL_RAM_RESERVED_SIZE            0x000000
-#endif /* _CFG_GLOBAL_H_ */
diff --git a/arch/arm/mach-bcmring/include/csp/cache.h b/arch/arm/mach-bcmring/include/csp/cache.h
deleted file mode 100644
index caa20e59db99..000000000000
--- a/arch/arm/mach-bcmring/include/csp/cache.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#ifndef CSP_CACHE_H
-#define CSP_CACHE_H
-/* ---- Include Files ---------------------------------------------------- */
-#include <csp/stdint.h>
-/* ---- Public Constants and Types --------------------------------------- */
-#if defined(__KERNEL__) && !defined(STANDALONE)
-#include <asm/cacheflush.h>
-#define CSP_CACHE_FLUSH_ALL      flush_cache_all()
-#else
-#define CSP_CACHE_FLUSH_ALL
-#endif
-#endif /* CSP_CACHE_H */
diff --git a/arch/arm/mach-bcmring/include/csp/delay.h b/arch/arm/mach-bcmring/include/csp/delay.h
deleted file mode 100644
index 8b3d80367293..000000000000
--- a/arch/arm/mach-bcmring/include/csp/delay.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#ifndef CSP_DELAY_H
-#define CSP_DELAY_H
-/* ---- Include Files ---------------------------------------------------- */
-/* Some CSP routines require use of the following delay routines. Use the OS */
-/* version if available, otherwise use a CSP specific definition. */
-/* void udelay(unsigned long usecs); */
-/* void mdelay(unsigned long msecs); */
-#if defined(__KERNEL__) && !defined(STANDALONE)
-   #include <linux/delay.h>
-#else
-   #include <mach/csp/delay.h>
-#endif
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-#endif /*  CSP_DELAY_H */
diff --git a/arch/arm/mach-bcmring/include/csp/errno.h b/arch/arm/mach-bcmring/include/csp/errno.h
deleted file mode 100644
index 51357dd5b666..000000000000
--- a/arch/arm/mach-bcmring/include/csp/errno.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#ifndef CSP_ERRNO_H
-#define CSP_ERRNO_H
-/* ---- Include Files ---------------------------------------------------- */
-#if   defined(__KERNEL__)
-#include <linux/errno.h>
-#elif defined(CSP_SIMULATION)
-#include <asm-generic/errno.h>
-#else
-#include <errno.h>
-#endif
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-#endif /* CSP_ERRNO_H */
diff --git a/arch/arm/mach-bcmring/include/csp/intcHw.h b/arch/arm/mach-bcmring/include/csp/intcHw.h
deleted file mode 100644
index 1c639c8ee08f..000000000000
--- a/arch/arm/mach-bcmring/include/csp/intcHw.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/****************************************************************************/
-/**
-*  @file    intcHw.h
-*
-*  @brief   generic interrupt controller API
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-#ifndef _INTCHW_H
-#define _INTCHW_H
-/* ---- Include Files ---------------------------------------------------- */
-#include <mach/csp/intcHw_reg.h>
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-static inline void intcHw_irq_disable(void *basep, uint32_t mask);
-static inline void intcHw_irq_enable(void *basep, uint32_t mask);
-#endif /* _INTCHW_H */
diff --git a/arch/arm/mach-bcmring/include/csp/module.h b/arch/arm/mach-bcmring/include/csp/module.h
deleted file mode 100644
index c30d2a5975a6..000000000000
--- a/arch/arm/mach-bcmring/include/csp/module.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#ifndef CSP_MODULE_H
-#define CSP_MODULE_H
-/* ---- Include Files ---------------------------------------------------- */
-#ifdef __KERNEL__
-    #include <linux/module.h>
-#else
-    #define EXPORT_SYMBOL(symbol)
-#endif
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-#endif /* CSP_MODULE_H */
diff --git a/arch/arm/mach-bcmring/include/csp/secHw.h b/arch/arm/mach-bcmring/include/csp/secHw.h
deleted file mode 100644
index b9d7e0732dfc..000000000000
--- a/arch/arm/mach-bcmring/include/csp/secHw.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/****************************************************************************/
-/**
-*  @file    secHw.h
-*
-*  @brief   Definitions for accessing low level security features
-*
-*/
-/****************************************************************************/
-#ifndef SECHW_H
-#define SECHW_H
-typedef void (*secHw_FUNC_t) (void);
-typedef enum {
-        secHw_MODE_SECURE = 0x0,        /* Switches processor into secure mode */
-        secHw_MODE_NONSECURE = 0x1      /* Switches processor into non-secure mode */
-} secHw_MODE;
-/****************************************************************************/
-/**
-*  @brief   Requesting to execute the function in secure mode
-*
-*  This function requests the given function to run in secure mode
-*
-*/
-/****************************************************************************/
-void secHw_RunSecure(secHw_FUNC_t       /* Function to run in secure mode */
-    );
-/****************************************************************************/
-/**
-*  @brief   Sets the  mode
-*
-*  his function sets the processor mode (secure/non-secure)
-*
-*/
-/****************************************************************************/
-void secHw_SetMode(secHw_MODE   /* Processor mode */
-    );
-/****************************************************************************/
-/**
-*  @brief   Get the current mode
-*
-*  This function retieves the processor mode (secure/non-secure)
-*
-*/
-/****************************************************************************/
-void secHw_GetMode(secHw_MODE *);
-#endif /* SECHW_H */
diff --git a/arch/arm/mach-bcmring/include/csp/stdint.h b/arch/arm/mach-bcmring/include/csp/stdint.h
deleted file mode 100644
index 3a8718bbf700..000000000000
--- a/arch/arm/mach-bcmring/include/csp/stdint.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#ifndef CSP_STDINT_H
-#define CSP_STDINT_H
-/* ---- Include Files ---------------------------------------------------- */
-#ifdef __KERNEL__
-#include <linux/types.h>
-#else
-#include <stdint.h>
-#endif
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-#endif /* CSP_STDINT_H */
diff --git a/arch/arm/mach-bcmring/include/csp/string.h b/arch/arm/mach-bcmring/include/csp/string.h
deleted file mode 100644
index ad9e4005f141..000000000000
--- a/arch/arm/mach-bcmring/include/csp/string.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#ifndef CSP_STRING_H
-#define CSP_STRING_H
-/* ---- Include Files ---------------------------------------------------- */
-#ifdef __KERNEL__
-   #include <linux/string.h>
-#else
-   #include <string.h>
-#endif
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-#endif /* CSP_STRING_H */
diff --git a/arch/arm/mach-bcmring/include/cfg_global_defines.h b/arch/arm/mach-bcmring/include/mach/cfg_global.h
index b5beb0b30734..449133eacdf5 100644
--- a/arch/arm/mach-bcmring/include/cfg_global_defines.h
+++ b/arch/arm/mach-bcmring/include/mach/cfg_global.h
@@ -38,3 +38,14 @@
 #define IMAGE_HEADER_SIZE_CHECKSUM    4
 #endif
+#ifndef _CFG_GLOBAL_H_
+#define _CFG_GLOBAL_H_
+#define CFG_GLOBAL_CHIP                         BCM11107
+#define CFG_GLOBAL_CHIP_FAMILY                  CFG_GLOBAL_CHIP_FAMILY_BCMRING
+#define CFG_GLOBAL_CHIP_REV                     0xB0
+#define CFG_GLOBAL_RAM_SIZE                     0x10000000
+#define CFG_GLOBAL_RAM_BASE                     0x00000000
+#define CFG_GLOBAL_RAM_RESERVED_SIZE            0x000000
+#endif /* _CFG_GLOBAL_H_ */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h b/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
index 933ce68ed90b..0a89e0c63419 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
@@ -17,7 +17,7 @@
 /* ---- Include Files ---------------------------------------------------- */
 #include <mach/csp/cap.h>
-#include <cfg_global.h>
+#include <mach/cfg_global.h>
 /* ---- Public Constants and Types --------------------------------------- */
 #define CAP_CONFIG0_VPM_DIS          0x00000001
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
index 161973385faf..39f09cb89208 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
@@ -17,9 +17,9 @@
 /* ---- Include Files ----------------------------------------------------- */
-#include <csp/stdint.h>
+#include <linux/types.h>
-#include <csp/errno.h>
+#include <linux/errno.h>
-#include <csp/reg.h>
+#include <mach/csp/reg.h>
 #include <mach/csp/chipcHw_reg.h>
 /* ---- Public Constants and Types ---------------------------------------- */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
index 03238c299001..a66f3f7abb86 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
@@ -17,8 +17,8 @@
 /* ---- Include Files ----------------------------------------------------- */
-#include <csp/errno.h>
+#include <linux/errno.h>
-#include <csp/reg.h>
+#include <mach/csp/reg.h>
 #include <mach/csp/chipcHw_reg.h>
 #include <mach/csp/chipcHw_def.h>
@@ -47,7 +47,7 @@ static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
 /****************************************************************************/
 static inline uint32_t chipcHw_getChipId(void)
 {
-        return pChipcHw->ChipId;
+        return readl(&pChipcHw->ChipId);
 }
 /****************************************************************************/
@@ -59,15 +59,16 @@ static inline uint32_t chipcHw_getChipId(void)
 /****************************************************************************/
 static inline void chipcHw_enableSpreadSpectrum(void)
 {
-        if ((pChipcHw->
+        if ((readl(&pChipcHw->
-             PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) !=
+             PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) !=
            chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
-                ddrcReg_PHY_ADDR_CTL_REGP->ssCfg =
+                writel((0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) |
-                    (0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) |
                    (ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK <<
-                     ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT);
+                     ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT),
-                ddrcReg_PHY_ADDR_CTL_REGP->ssCtl |=
+                     &ddrcReg_PHY_ADDR_CTL_REGP->ssCfg);
-                    ddrcReg_PHY_ADDR_SS_CTRL_ENABLE;
+                writel(readl(&ddrcReg_PHY_ADDR_CTL_REGP->ssCtl) |
+                    ddrcReg_PHY_ADDR_SS_CTRL_ENABLE,
+                    &ddrcReg_PHY_ADDR_CTL_REGP->ssCtl);
        }
 }
@@ -93,8 +94,8 @@ static inline void chipcHw_disableSpreadSpectrum(void)
 /****************************************************************************/
 static inline uint32_t chipcHw_getChipProductId(void)
 {
-        return (pChipcHw->
+        return (readl(&pChipcHw->
-                 ChipId & chipcHw_REG_CHIPID_BASE_MASK) >>
+                 ChipId) & chipcHw_REG_CHIPID_BASE_MASK) >>
                chipcHw_REG_CHIPID_BASE_SHIFT;
 }
@@ -109,7 +110,7 @@ static inline uint32_t chipcHw_getChipProductId(void)
 /****************************************************************************/
 static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void)
 {
-        return pChipcHw->ChipId & chipcHw_REG_CHIPID_REV_MASK;
+        return readl(&pChipcHw->ChipId) & chipcHw_REG_CHIPID_REV_MASK;
 }
 /****************************************************************************/
@@ -156,7 +157,7 @@ static inline void chipcHw_busInterfaceClockDisable(uint32_t mask)
 /****************************************************************************/
 static inline uint32_t chipcHw_getBusInterfaceClockStatus(void)
 {
-        return pChipcHw->BusIntfClock;
+        return readl(&pChipcHw->BusIntfClock);
 }
 /****************************************************************************/
@@ -215,8 +216,9 @@ static inline void chipcHw_softResetDisable(uint64_t mask)
        /* Deassert module soft reset */
        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->SoftReset1 ^= ctrl1;
+        writel(readl(&pChipcHw->SoftReset1) ^ ctrl1, &pChipcHw->SoftReset1);
-        pChipcHw->SoftReset2 ^= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK));
+        writel(readl(&pChipcHw->SoftReset2) ^ (ctrl2 &
+                (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)), &pChipcHw->SoftReset2);
        REG_LOCAL_IRQ_RESTORE;
 }
@@ -227,9 +229,10 @@ static inline void chipcHw_softResetEnable(uint64_t mask)
        uint32_t unhold = 0;
        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->SoftReset1 |= ctrl1;
+        writel(readl(&pChipcHw->SoftReset1) | ctrl1, &pChipcHw->SoftReset1);
        /* Mask out unhold request bits */
-        pChipcHw->SoftReset2 |= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK));
+        writel(readl(&pChipcHw->SoftReset2) | (ctrl2 &
+                (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)), &pChipcHw->SoftReset2);
        /* Process unhold requests */
        if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD) {
@@ -246,7 +249,7 @@ static inline void chipcHw_softResetEnable(uint64_t mask)
        if (unhold) {
                /* Make sure unhold request is effective */
-                pChipcHw->SoftReset1 &= ~unhold;
+                writel(readl(&pChipcHw->SoftReset1) & ~unhold, &pChipcHw->SoftReset1);
        }
        REG_LOCAL_IRQ_RESTORE;
 }
@@ -307,7 +310,7 @@ static inline void chipcHw_setOTPOption(uint64_t mask)
 /****************************************************************************/
 static inline uint32_t chipcHw_getStickyBits(void)
 {
-        return pChipcHw->Sticky;
+        return readl(&pChipcHw->Sticky);
 }
 /****************************************************************************/
@@ -328,7 +331,7 @@ static inline void chipcHw_setStickyBits(uint32_t mask)
                bits |= chipcHw_REG_STICKY_POR_BROM;
        } else {
                uint32_t sticky;
-                sticky = pChipcHw->Sticky;
+                sticky = readl(pChipcHw->Sticky);
                if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
                    && (sticky & chipcHw_REG_STICKY_BOOT_DONE) == 0) {
@@ -355,7 +358,7 @@ static inline void chipcHw_setStickyBits(uint32_t mask)
                        bits |= chipcHw_REG_STICKY_GENERAL_5;
                }
        }
-        pChipcHw->Sticky = bits;
+        writel(bits, pChipcHw->Sticky);
        REG_LOCAL_IRQ_RESTORE;
 }
@@ -377,7 +380,7 @@ static inline void chipcHw_clearStickyBits(uint32_t mask)
            (chipcHw_REG_STICKY_BOOT_DONE | chipcHw_REG_STICKY_GENERAL_1 |
             chipcHw_REG_STICKY_GENERAL_2 | chipcHw_REG_STICKY_GENERAL_3 |
             chipcHw_REG_STICKY_GENERAL_4 | chipcHw_REG_STICKY_GENERAL_5)) {
-                uint32_t sticky = pChipcHw->Sticky;
+                uint32_t sticky = readl(&pChipcHw->Sticky);
                if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
                    && (sticky & chipcHw_REG_STICKY_BOOT_DONE)) {
@@ -410,7 +413,7 @@ static inline void chipcHw_clearStickyBits(uint32_t mask)
                        mask &= ~chipcHw_REG_STICKY_GENERAL_5;
                }
        }
-        pChipcHw->Sticky = bits | mask;
+        writel(bits | mask, &pChipcHw->Sticky);
        REG_LOCAL_IRQ_RESTORE;
 }
@@ -426,7 +429,7 @@ static inline void chipcHw_clearStickyBits(uint32_t mask)
 /****************************************************************************/
 static inline uint32_t chipcHw_getSoftStraps(void)
 {
-        return pChipcHw->SoftStraps;
+        return readl(&pChipcHw->SoftStraps);
 }
 /****************************************************************************/
@@ -456,7 +459,7 @@ static inline void chipcHw_setSoftStraps(uint32_t strapOptions)
 /****************************************************************************/
 static inline uint32_t chipcHw_getPinStraps(void)
 {
-        return pChipcHw->PinStraps;
+        return readl(&pChipcHw->PinStraps);
 }
 /****************************************************************************/
@@ -671,9 +674,9 @@ static inline void chipcHw_selectGE3(void)
 /****************************************************************************/
 static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin)
 {
-        return (*((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) &
+        return (readl(chipcHw_REG_GPIO_MUX(pin))) &
                (chipcHw_REG_GPIO_MUX_MASK <<
-                 chipcHw_REG_GPIO_MUX_POSITION(pin))) >>
+                 chipcHw_REG_GPIO_MUX_POSITION(pin)) >>
            chipcHw_REG_GPIO_MUX_POSITION(pin);
 }
@@ -841,8 +844,8 @@ static inline void chipcHw_setUsbDevice(void)
 static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
                                    chipcHw_OPTYPE_e type, int mode)
 {
-        volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
+        uint32_t __iomem *pPLLReg = NULL;
-        volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
+        uint32_t __iomem *pClockCtrl = NULL;
        switch (clock) {
        case chipcHw_CLOCK_DDR:
@@ -1071,7 +1074,7 @@ static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock)
 /****************************************************************************/
 static inline int chipcHw_isSoftwareStrapsEnable(void)
 {
-        return pChipcHw->SoftStraps & 0x00000001;
+        return readl(&pChipcHw->SoftStraps) & 0x00000001;
 }
 /****************************************************************************/
@@ -1138,7 +1141,7 @@ static inline void chipcHw_pll2TestDisable(void)
 /****************************************************************************/
 static inline int chipcHw_isPllTestEnable(void)
 {
-        return pChipcHw->PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
+        return readl(&pChipcHw->PLLConfig) & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
 }
 /****************************************************************************/
@@ -1147,7 +1150,7 @@ static inline int chipcHw_isPllTestEnable(void)
 /****************************************************************************/
 static inline int chipcHw_isPll2TestEnable(void)
 {
-        return pChipcHw->PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
+        return readl(&pChipcHw->PLLConfig2) & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
 }
 /****************************************************************************/
@@ -1183,8 +1186,8 @@ static inline void chipcHw_pll2TestSelect(uint32_t val)
 /****************************************************************************/
 static inline uint8_t chipcHw_getPllTestSelected(void)
 {
-        return (uint8_t) ((pChipcHw->
+        return (uint8_t) ((readl(&pChipcHw->
-                           PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
+                           PLLConfig) & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
                          >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
 }
@@ -1194,8 +1197,8 @@ static inline uint8_t chipcHw_getPllTestSelected(void)
 /****************************************************************************/
 static inline uint8_t chipcHw_getPll2TestSelected(void)
 {
-        return (uint8_t) ((pChipcHw->
+        return (uint8_t) ((readl(&pChipcHw->
-                           PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
+                           PLLConfig2) & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
                          >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
 }
@@ -1208,7 +1211,8 @@ static inline uint8_t chipcHw_getPll2TestSelected(void)
 static inline void chipcHw_pll1Disable(void)
 {
        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->PLLConfig |= chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+        writel(readl(&pChipcHw->PLLConfig) | chipcHw_REG_PLL_CONFIG_POWER_DOWN,
+                &pChipcHw->PLLConfig);
        REG_LOCAL_IRQ_RESTORE;
 }
@@ -1221,7 +1225,8 @@ static inline void chipcHw_pll1Disable(void)
 static inline void chipcHw_pll2Disable(void)
 {
        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->PLLConfig2 |= chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+        writel(readl(&pChipcHw->PLLConfig2) | chipcHw_REG_PLL_CONFIG_POWER_DOWN,
+                &pChipcHw->PLLConfig2);
        REG_LOCAL_IRQ_RESTORE;
 }
@@ -1233,7 +1238,8 @@ static inline void chipcHw_pll2Disable(void)
 static inline void chipcHw_ddrPhaseAlignInterruptEnable(void)
 {
        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->Spare1 |= chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE;
+        writel(readl(&pChipcHw->Spare1) | chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE,
+                &pChipcHw->Spare1);
        REG_LOCAL_IRQ_RESTORE;
 }
@@ -1245,7 +1251,8 @@ static inline void chipcHw_ddrPhaseAlignInterruptEnable(void)
 static inline void chipcHw_ddrPhaseAlignInterruptDisable(void)
 {
        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE;
+        writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE,
+                &pChipcHw->Spare1);
        REG_LOCAL_IRQ_RESTORE;
 }
@@ -1333,7 +1340,8 @@ static inline void chipcHw_ddrHwPhaseAlignDisable(void)
 static inline void chipcHw_vpmSwPhaseAlignEnable(void)
 {
        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE;
+        writel(readl(&pChipcHw->VPMPhaseCtrl1) | chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE,
+                        &pChipcHw->VPMPhaseCtrl1);
        REG_LOCAL_IRQ_RESTORE;
 }
@@ -1372,7 +1380,8 @@ static inline void chipcHw_vpmHwPhaseAlignEnable(void)
 static inline void chipcHw_vpmHwPhaseAlignDisable(void)
 {
        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE;
+        writel(readl(&pChipcHw->VPMPhaseCtrl1) & ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE,
+                &pChipcHw->VPMPhaseCtrl1);
        REG_LOCAL_IRQ_RESTORE;
 }
@@ -1474,8 +1483,8 @@ chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin)
 /****************************************************************************/
 static inline uint32_t chipcHw_isDdrHwPhaseAligned(void)
 {
-        return (pChipcHw->
+        return (readl(&pChipcHw->
-                PhaseAlignStatus & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0;
+                PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0;
 }
 /****************************************************************************/
@@ -1488,8 +1497,8 @@ static inline uint32_t chipcHw_isDdrHwPhaseAligned(void)
 /****************************************************************************/
 static inline uint32_t chipcHw_isVpmHwPhaseAligned(void)
 {
-        return (pChipcHw->
+        return (readl(&pChipcHw->
-                PhaseAlignStatus & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0;
+                PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0;
 }
 /****************************************************************************/
@@ -1500,8 +1509,8 @@ static inline uint32_t chipcHw_isVpmHwPhaseAligned(void)
 /****************************************************************************/
 static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void)
 {
-        return (pChipcHw->
+        return (readl(&pChipcHw->
-                PhaseAlignStatus & chipcHw_REG_DDR_PHASE_STATUS_MASK) >>
+                PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_STATUS_MASK) >>
            chipcHw_REG_DDR_PHASE_STATUS_SHIFT;
 }
@@ -1513,8 +1522,8 @@ static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void)
 /****************************************************************************/
 static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void)
 {
-        return (pChipcHw->
+        return (readl(&pChipcHw->
-                PhaseAlignStatus & chipcHw_REG_VPM_PHASE_STATUS_MASK) >>
+                PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_STATUS_MASK) >>
            chipcHw_REG_VPM_PHASE_STATUS_SHIFT;
 }
@@ -1526,8 +1535,8 @@ static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void)
 /****************************************************************************/
 static inline uint32_t chipcHw_getDdrPhaseControl(void)
 {
-        return (pChipcHw->
+        return (readl(&pChipcHw->
-                PhaseAlignStatus & chipcHw_REG_DDR_PHASE_CTRL_MASK) >>
+                PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_CTRL_MASK) >>
            chipcHw_REG_DDR_PHASE_CTRL_SHIFT;
 }
@@ -1539,8 +1548,8 @@ static inline uint32_t chipcHw_getDdrPhaseControl(void)
 /****************************************************************************/
 static inline uint32_t chipcHw_getVpmPhaseControl(void)
 {
-        return (pChipcHw->
+        return (readl(&pChipcHw->
-                PhaseAlignStatus & chipcHw_REG_VPM_PHASE_CTRL_MASK) >>
+                PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_CTRL_MASK) >>
            chipcHw_REG_VPM_PHASE_CTRL_SHIFT;
 }
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
index b162448f613c..26f5d0e4e1dd 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
@@ -24,7 +24,7 @@
 #define CHIPCHW_REG_H
 #include <mach/csp/mm_io.h>
-#include <csp/reg.h>
+#include <mach/csp/reg.h>
 #include <mach/csp/ddrcReg.h>
 #define chipcHw_BASE_ADDRESS    MM_IO_BASE_CHIPC
@@ -131,8 +131,8 @@ typedef struct {
        uint32_t MiscInput_0_15;        /* Input type for MISC 0 - 16 */
 } chipcHw_REG_t;
-#define pChipcHw  ((volatile chipcHw_REG_t *) chipcHw_BASE_ADDRESS)
+#define pChipcHw  ((chipcHw_REG_t __iomem *) chipcHw_BASE_ADDRESS)
-#define pChipcPhysical  ((volatile chipcHw_REG_t *) MM_ADDR_IO_CHIPC)
+#define pChipcPhysical  (MM_ADDR_IO_CHIPC)
 #define chipcHw_REG_CHIPID_BASE_MASK                    0xFFFFF000
 #define chipcHw_REG_CHIPID_BASE_SHIFT                   12
diff --git a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
index f1b68e26fa6d..39da2c1fdafb 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
@@ -30,8 +30,8 @@ extern "C" {
 /* ---- Include Files ---------------------------------------------------- */
-#include <csp/reg.h>
+#include <mach/csp/reg.h>
-#include <csp/stdint.h>
+#include <linux/types.h>
 #include <mach/csp/mm_io.h>
@@ -416,7 +416,7 @@ extern "C" {
        } ddrcReg_PHY_ADDR_CTL_REG_t;
 #define ddrcReg_PHY_ADDR_CTL_REG_OFFSET                 0x0400
-#define ddrcReg_PHY_ADDR_CTL_REGP                       ((volatile ddrcReg_PHY_ADDR_CTL_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET))
+#define ddrcReg_PHY_ADDR_CTL_REGP                       ((volatile ddrcReg_PHY_ADDR_CTL_REG_t __iomem*) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET))
 /* @todo These SS definitions are duplicates of ones below */
diff --git a/arch/arm/mach-bcmring/include/csp/dmacHw.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h
index e6a1dc484ca7..9dc90f46a84d 100644
--- a/arch/arm/mach-bcmring/include/csp/dmacHw.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h
@@ -23,9 +23,9 @@
 #ifndef _DMACHW_H
 #define _DMACHW_H
-#include <stddef.h>
+#include <linux/stddef.h>
-#include <csp/stdint.h>
+#include <linux/types.h>
 #include <mach/csp/dmacHw_reg.h>
 /* Define DMA Channel ID using DMA controller number (m) and channel number (c).
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
index d67e2f8c22de..9d9455e0c391 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
@@ -24,7 +24,7 @@
 #ifndef _DMACHW_PRIV_H
 #define _DMACHW_PRIV_H
-#include <csp/stdint.h>
+#include <linux/types.h>
 /* Data type for DMA Link List Item */
 typedef struct {
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
index f1ecf96f2da5..7cd0aafa6f6e 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
@@ -24,7 +24,7 @@
 #ifndef _DMACHW_REG_H
 #define _DMACHW_REG_H
-#include <csp/stdint.h>
+#include <linux/types.h>
 #include <mach/csp/mm_io.h>
 /* Data type for 64 bit little endian register */
@@ -121,75 +121,75 @@ typedef struct {
 } dmacHw_MISC_t;
 /* Base registers */
-#define dmacHw_0_MODULE_BASE_ADDR        (char *) MM_IO_BASE_DMA0       /* DMAC 0 module's base address */
+#define dmacHw_0_MODULE_BASE_ADDR        (char __iomem*) MM_IO_BASE_DMA0        /* DMAC 0 module's base address */
-#define dmacHw_1_MODULE_BASE_ADDR        (char *) MM_IO_BASE_DMA1       /* DMAC 1 module's base address */
+#define dmacHw_1_MODULE_BASE_ADDR        (char __iomem*) MM_IO_BASE_DMA1        /* DMAC 1 module's base address */
 extern uint32_t dmaChannelCount_0;
 extern uint32_t dmaChannelCount_1;
 /* Define channel specific registers */
-#define dmacHw_CHAN_BASE(module, chan)          ((dmacHw_CH_REG_t *) ((char *)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t))))
+#define dmacHw_CHAN_BASE(module, chan)          ((dmacHw_CH_REG_t __iomem*) ((char __iomem*)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t))))
 /* Raw interrupt status registers */
-#define dmacHw_REG_INT_RAW_BASE(module)         ((char *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0)))
+#define dmacHw_REG_INT_RAW_BASE(module)         ((char __iomem *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0)))
-#define dmacHw_REG_INT_RAW_TRAN(module)         (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo)
+#define dmacHw_REG_INT_RAW_TRAN(module)         (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo)
-#define dmacHw_REG_INT_RAW_BLOCK(module)        (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo)
+#define dmacHw_REG_INT_RAW_BLOCK(module)        (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo)
-#define dmacHw_REG_INT_RAW_STRAN(module)        (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo)
+#define dmacHw_REG_INT_RAW_STRAN(module)        (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo)
-#define dmacHw_REG_INT_RAW_DTRAN(module)        (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo)
+#define dmacHw_REG_INT_RAW_DTRAN(module)        (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo)
-#define dmacHw_REG_INT_RAW_ERROR(module)        (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo)
+#define dmacHw_REG_INT_RAW_ERROR(module)        (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo)
 /* Interrupt status registers */
-#define dmacHw_REG_INT_STAT_BASE(module)        ((char *)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t)))
+#define dmacHw_REG_INT_STAT_BASE(module)        ((char __iomem*)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t)))
-#define dmacHw_REG_INT_STAT_TRAN(module)        (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo)
+#define dmacHw_REG_INT_STAT_TRAN(module)        (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo)
-#define dmacHw_REG_INT_STAT_BLOCK(module)       (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo)
+#define dmacHw_REG_INT_STAT_BLOCK(module)       (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo)
-#define dmacHw_REG_INT_STAT_STRAN(module)       (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo)
+#define dmacHw_REG_INT_STAT_STRAN(module)       (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo)
-#define dmacHw_REG_INT_STAT_DTRAN(module)       (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo)
+#define dmacHw_REG_INT_STAT_DTRAN(module)       (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo)
-#define dmacHw_REG_INT_STAT_ERROR(module)       (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo)
+#define dmacHw_REG_INT_STAT_ERROR(module)       (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo)
 /* Interrupt status registers */
-#define dmacHw_REG_INT_MASK_BASE(module)        ((char *)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t)))
+#define dmacHw_REG_INT_MASK_BASE(module)        ((char __iomem*)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t)))
-#define dmacHw_REG_INT_MASK_TRAN(module)        (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo)
+#define dmacHw_REG_INT_MASK_TRAN(module)        (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo)
-#define dmacHw_REG_INT_MASK_BLOCK(module)       (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo)
+#define dmacHw_REG_INT_MASK_BLOCK(module)       (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo)
-#define dmacHw_REG_INT_MASK_STRAN(module)       (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo)
+#define dmacHw_REG_INT_MASK_STRAN(module)       (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo)
-#define dmacHw_REG_INT_MASK_DTRAN(module)       (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo)
+#define dmacHw_REG_INT_MASK_DTRAN(module)       (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo)
-#define dmacHw_REG_INT_MASK_ERROR(module)       (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo)
+#define dmacHw_REG_INT_MASK_ERROR(module)       (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo)
 /* Interrupt clear registers */
-#define dmacHw_REG_INT_CLEAR_BASE(module)       ((char *)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t)))
+#define dmacHw_REG_INT_CLEAR_BASE(module)       ((char __iomem*)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t)))
-#define dmacHw_REG_INT_CLEAR_TRAN(module)       (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo)
+#define dmacHw_REG_INT_CLEAR_TRAN(module)       (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo)
-#define dmacHw_REG_INT_CLEAR_BLOCK(module)      (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo)
+#define dmacHw_REG_INT_CLEAR_BLOCK(module)      (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo)
-#define dmacHw_REG_INT_CLEAR_STRAN(module)      (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo)
+#define dmacHw_REG_INT_CLEAR_STRAN(module)      (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo)
-#define dmacHw_REG_INT_CLEAR_DTRAN(module)      (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo)
+#define dmacHw_REG_INT_CLEAR_DTRAN(module)      (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo)
-#define dmacHw_REG_INT_CLEAR_ERROR(module)      (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo)
+#define dmacHw_REG_INT_CLEAR_ERROR(module)      (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo)
-#define dmacHw_REG_INT_STATUS(module)           (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo)
+#define dmacHw_REG_INT_STATUS(module)           (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo)
 /* Software handshaking registers */
-#define dmacHw_REG_SW_HS_BASE(module)           ((char *)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t)))
+#define dmacHw_REG_SW_HS_BASE(module)           ((char __iomem*)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t)))
-#define dmacHw_REG_SW_HS_SRC_REQ(module)        (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo)
+#define dmacHw_REG_SW_HS_SRC_REQ(module)        (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_REQ(module)        (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo)
+#define dmacHw_REG_SW_HS_DST_REQ(module)        (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo)
-#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module)    (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo)
+#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module)    (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_SGL_REQ(module)    (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo)
+#define dmacHw_REG_SW_HS_DST_SGL_REQ(module)    (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo)
-#define dmacHw_REG_SW_HS_SRC_LST_REQ(module)    (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo)
+#define dmacHw_REG_SW_HS_SRC_LST_REQ(module)    (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_LST_REQ(module)    (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo)
+#define dmacHw_REG_SW_HS_DST_LST_REQ(module)    (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo)
 /* Miscellaneous registers */
-#define dmacHw_REG_MISC_BASE(module)            ((char *)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t)))
+#define dmacHw_REG_MISC_BASE(module)            ((char __iomem*)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t)))
-#define dmacHw_REG_MISC_CFG(module)             (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo)
+#define dmacHw_REG_MISC_CFG(module)             (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo)
-#define dmacHw_REG_MISC_CH_ENABLE(module)       (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo)
+#define dmacHw_REG_MISC_CH_ENABLE(module)       (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo)
-#define dmacHw_REG_MISC_ID(module)              (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo)
+#define dmacHw_REG_MISC_ID(module)              (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo)
-#define dmacHw_REG_MISC_TEST(module)            (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo)
+#define dmacHw_REG_MISC_TEST(module)            (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo)
-#define dmacHw_REG_MISC_COMP_PARAM1_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo)
+#define dmacHw_REG_MISC_COMP_PARAM1_LO(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo)
-#define dmacHw_REG_MISC_COMP_PARAM1_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi)
+#define dmacHw_REG_MISC_COMP_PARAM1_HI(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi)
-#define dmacHw_REG_MISC_COMP_PARAM2_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo)
+#define dmacHw_REG_MISC_COMP_PARAM2_LO(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo)
-#define dmacHw_REG_MISC_COMP_PARAM2_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi)
+#define dmacHw_REG_MISC_COMP_PARAM2_HI(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi)
-#define dmacHw_REG_MISC_COMP_PARAM3_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo)
+#define dmacHw_REG_MISC_COMP_PARAM3_LO(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo)
-#define dmacHw_REG_MISC_COMP_PARAM3_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi)
+#define dmacHw_REG_MISC_COMP_PARAM3_HI(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi)
-#define dmacHw_REG_MISC_COMP_PARAM4_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo)
+#define dmacHw_REG_MISC_COMP_PARAM4_LO(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo)
-#define dmacHw_REG_MISC_COMP_PARAM4_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi)
+#define dmacHw_REG_MISC_COMP_PARAM4_HI(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi)
-#define dmacHw_REG_MISC_COMP_PARAM5_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo)
+#define dmacHw_REG_MISC_COMP_PARAM5_LO(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo)
-#define dmacHw_REG_MISC_COMP_PARAM5_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi)
+#define dmacHw_REG_MISC_COMP_PARAM5_HI(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi)
-#define dmacHw_REG_MISC_COMP_PARAM6_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo)
+#define dmacHw_REG_MISC_COMP_PARAM6_LO(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo)
-#define dmacHw_REG_MISC_COMP_PARAM6_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi)
+#define dmacHw_REG_MISC_COMP_PARAM6_HI(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi)
 /* Channel control registers */
 #define dmacHw_REG_SAR(module, chan)            (dmacHw_CHAN_BASE((module), (chan))->ChannelSar.lo)
diff --git a/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h b/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
index cfa91bed9d34..27f59dd27792 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
@@ -18,7 +18,7 @@
 /* ---- Include Files ---------------------------------------------------- */
-#include <cfg_global.h>
+#include <mach/cfg_global.h>
 #include <mach/csp/cap_inline.h>
 #if defined(__KERNEL__)
diff --git a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
index 0aeb6a6fe7f8..f59db25b5632 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
@@ -27,8 +27,8 @@
 #define _INTCHW_REG_H
 /* ---- Include Files ---------------------------------------------------- */
-#include <csp/stdint.h>
+#include <linux/types.h>
-#include <csp/reg.h>
+#include <mach/csp/reg.h>
 #include <mach/csp/mm_io.h>
 /* ---- Public Constants and Types --------------------------------------- */
@@ -37,9 +37,9 @@
 #define INTCHW_NUM_INTC           3
 /* Defines for interrupt controllers. This simplifies and cleans up the function calls. */
-#define INTCHW_INTC0    ((void *)MM_IO_BASE_INTC0)
+#define INTCHW_INTC0    (MM_IO_BASE_INTC0)
-#define INTCHW_INTC1    ((void *)MM_IO_BASE_INTC1)
+#define INTCHW_INTC1    (MM_IO_BASE_INTC1)
-#define INTCHW_SINTC    ((void *)MM_IO_BASE_SINTC)
+#define INTCHW_SINTC    (MM_IO_BASE_SINTC)
 /* INTC0 - interrupt controller 0 */
 #define INTCHW_INTC0_PIF_BITNUM           31    /* Peripheral interface interrupt */
@@ -232,15 +232,15 @@
 /* ---- Public Variable Externs ------------------------------------------ */
 /* ---- Public Function Prototypes --------------------------------------- */
 /* Clear one or more IRQ interrupts. */
-static inline void intcHw_irq_disable(void *basep, uint32_t mask)
+static inline void intcHw_irq_disable(void __iomem *basep, uint32_t mask)
 {
-        __REG32(basep + INTCHW_INTENCLEAR) = mask;
+        writel(mask, basep + INTCHW_INTENCLEAR);
 }
 /* Enables one or more IRQ interrupts. */
-static inline void intcHw_irq_enable(void *basep, uint32_t mask)
+static inline void intcHw_irq_enable(void __iomem *basep, uint32_t mask)
 {
-        __REG32(basep + INTCHW_INTENABLE) = mask;
+        writel(mask, basep + INTCHW_INTENABLE);
 }
 #endif /* _INTCHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h b/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
index ad58cf873377..d571962f2904 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
@@ -29,7 +29,7 @@
 /* ---- Include Files ---------------------------------------------------- */
 #if !defined(CSP_SIMULATION)
-#include <cfg_global.h>
+#include <mach/cfg_global.h>
 #endif
 /* ---- Public Constants and Types --------------------------------------- */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
index de92ec6a01aa..47450c23685a 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
@@ -30,7 +30,7 @@
 #include <mach/csp/mm_addr.h>
 #if !defined(CSP_SIMULATION)
-#include <cfg_global.h>
+#include <mach/cfg_global.h>
 #endif
 /* ---- Public Constants and Types --------------------------------------- */
@@ -49,7 +49,7 @@
 #ifdef __ASSEMBLY__
 #define MM_IO_PHYS_TO_VIRT(phys)       (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF))
 #else
-#define MM_IO_PHYS_TO_VIRT(phys)       (((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \
+#define MM_IO_PHYS_TO_VIRT(phys)       (void __iomem *)(((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \
                        (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF)))
 #endif
 #endif
@@ -60,8 +60,8 @@
 #ifdef __ASSEMBLY__
 #define MM_IO_VIRT_TO_PHYS(virt)       ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF))
 #else
-#define MM_IO_VIRT_TO_PHYS(virt)       (((virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \
+#define MM_IO_VIRT_TO_PHYS(virt)       (((unsigned long)(virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \
-                        ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF)))
+                        ((((unsigned long)(virt) & 0x0F000000) << 4) | ((unsigned long)(virt) & 0xFFFFFF)))
 #endif
 #endif
diff --git a/arch/arm/mach-bcmring/include/csp/reg.h b/arch/arm/mach-bcmring/include/mach/csp/reg.h
index 56654d23c3d7..d9cbdca8cd25 100644
--- a/arch/arm/mach-bcmring/include/csp/reg.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/reg.h
@@ -25,13 +25,14 @@
 /* ---- Include Files ---------------------------------------------------- */
-#include <csp/stdint.h>
+#include <linux/types.h>
+#include <linux/io.h>
 /* ---- Public Constants and Types --------------------------------------- */
-#define __REG32(x)      (*((volatile uint32_t *)(x)))
+#define __REG32(x)      (*((volatile uint32_t __iomem *)(x)))
-#define __REG16(x)      (*((volatile uint16_t *)(x)))
+#define __REG16(x)      (*((volatile uint16_t __iomem *)(x)))
-#define __REG8(x)       (*((volatile uint8_t *) (x)))
+#define __REG8(x)       (*((volatile uint8_t __iomem *) (x)))
 /* Macros used to define a sequence of reserved registers. The start / end */
 /* are byte offsets in the particular register definition, with the "end" */
@@ -84,31 +85,31 @@
 #endif
-static inline void reg32_modify_and(volatile uint32_t *reg, uint32_t value)
+static inline void reg32_modify_and(volatile uint32_t __iomem *reg, uint32_t value)
 {
        REG_LOCAL_IRQ_SAVE;
-        *reg &= value;
+        __raw_writel(__raw_readl(reg) & value, reg);
        REG_LOCAL_IRQ_RESTORE;
 }
-static inline void reg32_modify_or(volatile uint32_t *reg, uint32_t value)
+static inline void reg32_modify_or(volatile uint32_t __iomem *reg, uint32_t value)
 {
        REG_LOCAL_IRQ_SAVE;
-        *reg |= value;
+        __raw_writel(__raw_readl(reg) | value, reg);
        REG_LOCAL_IRQ_RESTORE;
 }
-static inline void reg32_modify_mask(volatile uint32_t *reg, uint32_t mask,
+static inline void reg32_modify_mask(volatile uint32_t __iomem *reg, uint32_t mask,
                                     uint32_t value)
 {
        REG_LOCAL_IRQ_SAVE;
-        *reg = (*reg & mask) | value;
+        __raw_writel((__raw_readl(reg) & mask) | value, reg);
        REG_LOCAL_IRQ_RESTORE;
 }
-static inline void reg32_write(volatile uint32_t *reg, uint32_t value)
+static inline void reg32_write(volatile uint32_t __iomem *reg, uint32_t value)
 {
-        *reg = value;
+        __raw_writel(value, reg);
 }
 #endif /* CSP_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
index 9cd6a032ab71..55d3cd4fd1e7 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
@@ -34,7 +34,7 @@
 /****************************************************************************/
 static inline void secHw_setSecure(uint32_t mask        /*  mask of type secHw_BLK_MASK_XXXXXX */
    ) {
-        secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
+        secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC;
        if (mask & 0x0000FFFF) {
                regp->reg[secHw_IDX_LS].setSecure = mask & 0x0000FFFF;
@@ -53,13 +53,13 @@ static inline void secHw_setSecure(uint32_t mask	/*  mask of type secHw_BLK_MASK
 /****************************************************************************/
 static inline void secHw_setUnsecure(uint32_t mask      /*  mask of type secHw_BLK_MASK_XXXXXX */
    ) {
-        secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
+        secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC;
        if (mask & 0x0000FFFF) {
-                regp->reg[secHw_IDX_LS].setUnsecure = mask & 0x0000FFFF;
+                writel(mask & 0x0000FFFF, &regp->reg[secHw_IDX_LS].setUnsecure);
        }
        if (mask & 0xFFFF0000) {
-                regp->reg[secHw_IDX_MS].setUnsecure = mask >> 16;
+                writel(mask >> 16, &regp->reg[secHw_IDX_MS].setUnsecure);
        }
 }
@@ -71,7 +71,7 @@ static inline void secHw_setUnsecure(uint32_t mask	/*  mask of type secHw_BLK_MA
 /****************************************************************************/
 static inline uint32_t secHw_getStatus(void)
 {
-        secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
+        secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC;
        return (regp->reg[1].status << 16) + regp->reg[0].status;
 }
diff --git a/arch/arm/mach-bcmring/include/csp/tmrHw.h b/arch/arm/mach-bcmring/include/mach/csp/tmrHw.h
index 2cbb530db8ea..1cc882ae60f5 100644
--- a/arch/arm/mach-bcmring/include/csp/tmrHw.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/tmrHw.h
@@ -23,7 +23,7 @@
 #ifndef _TMRHW_H
 #define _TMRHW_H
-#include <csp/stdint.h>
+#include <linux/types.h>
 typedef uint32_t tmrHw_ID_t;    /* Timer ID */
 typedef uint32_t tmrHw_COUNT_t; /* Timer count */
diff --git a/arch/arm/mach-bcmring/include/mach/dma.h b/arch/arm/mach-bcmring/include/mach/dma.h
index 72543781207b..13e01384d6fc 100644
--- a/arch/arm/mach-bcmring/include/mach/dma.h
+++ b/arch/arm/mach-bcmring/include/mach/dma.h
@@ -27,7 +27,7 @@
 #include <linux/kernel.h>
 #include <linux/semaphore.h>
-#include <csp/dmacHw.h>
+#include <mach/csp/dmacHw.h>
 #include <mach/timer.h>
 /* ---- Constants and Types ---------------------------------------------- */
diff --git a/arch/arm/mach-bcmring/include/mach/hardware.h b/arch/arm/mach-bcmring/include/mach/hardware.h
index 6ae20a649a97..a0c92b4b8c60 100644
--- a/arch/arm/mach-bcmring/include/mach/hardware.h
+++ b/arch/arm/mach-bcmring/include/mach/hardware.h
@@ -22,7 +22,7 @@
 #define __ASM_ARCH_HARDWARE_H
 #include <asm/sizes.h>
-#include <cfg_global.h>
+#include <mach/cfg_global.h>
 #include <mach/csp/mm_io.h>
 /* Hardware addresses of major areas.
diff --git a/arch/arm/mach-bcmring/include/mach/reg_nand.h b/arch/arm/mach-bcmring/include/mach/reg_nand.h
index 387376ffb56b..f8d51a8b0b15 100644
--- a/arch/arm/mach-bcmring/include/mach/reg_nand.h
+++ b/arch/arm/mach-bcmring/include/mach/reg_nand.h
@@ -30,7 +30,7 @@
 #define __ASM_ARCH_REG_NAND_H
 /* ---- Include Files ---------------------------------------------------- */
-#include <csp/reg.h>
+#include <mach/csp/reg.h>
 #include <mach/reg_umi.h>
 /* ---- Constants and Types ---------------------------------------------- */
diff --git a/arch/arm/mach-bcmring/include/mach/reg_umi.h b/arch/arm/mach-bcmring/include/mach/reg_umi.h
index 0992842caa77..56dd9de7d83f 100644
--- a/arch/arm/mach-bcmring/include/mach/reg_umi.h
+++ b/arch/arm/mach-bcmring/include/mach/reg_umi.h
@@ -30,7 +30,7 @@
 #define __ASM_ARCH_REG_UMI_H
 /* ---- Include Files ---------------------------------------------------- */
-#include <csp/reg.h>
+#include <mach/csp/reg.h>
 #include <mach/csp/mm_io.h>
 /* ---- Constants and Types ---------------------------------------------- */
@@ -233,5 +233,5 @@
 #define REG_UMI_BCH_ERR_LOC_WORD              0x00000018
 /* location within a page (512 byte) */
 #define REG_UMI_BCH_ERR_LOC_PAGE              0x00001FE0
-#define REG_UMI_BCH_ERR_LOC_ADDR(index)     (__REG32(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16))
+#define REG_UMI_BCH_ERR_LOC_ADDR(index)     (readl(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16))
 #endif
diff --git a/arch/arm/mach-bcmring/mm.c b/arch/arm/mach-bcmring/mm.c
index 1adec78ec940..33824a81cac4 100644
--- a/arch/arm/mach-bcmring/mm.c
+++ b/arch/arm/mach-bcmring/mm.c
@@ -20,12 +20,12 @@
 #include <mach/hardware.h>
 #include <mach/csp/mm_io.h>
-#define IO_DESC(va, sz) { .virtual = va, \
+#define IO_DESC(va, sz) { .virtual = (unsigned long)va, \
        .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
        .length = sz, \
        .type = MT_DEVICE }
-#define MEM_DESC(va, sz) { .virtual = va, \
+#define MEM_DESC(va, sz) { .virtual = (unsigned long)va, \
        .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
        .length = sz, \
        .type = MT_MEMORY }
diff --git a/arch/arm/mach-bcmring/timer.c b/arch/arm/mach-bcmring/timer.c
index af9c3d7e2a0c..59412903466e 100644
--- a/arch/arm/mach-bcmring/timer.c
+++ b/arch/arm/mach-bcmring/timer.c
@@ -14,7 +14,7 @@
 #include <linux/types.h>
 #include <linux/module.h>
-#include <csp/tmrHw.h>
+#include <mach/csp/tmrHw.h>
 #include <mach/timer.h>
 /* The core.c file initializes timers 1 and 3 as a linux clocksource. */
diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig
index 54d8f34fdee5..f7e12ede008c 100644
--- a/arch/arm/mach-u300/Kconfig
+++ b/arch/arm/mach-u300/Kconfig
@@ -1,6 +1,6 @@
 if ARCH_U300
-menu "ST-Ericsson AB U300/U330/U335/U365 Platform"
+menu "ST-Ericsson AB U300/U335 Platform"
 comment "ST-Ericsson Mobile Platform Products"
@@ -10,46 +10,7 @@ config MACH_U300
        select PINCTRL_U300
        select PINCTRL_COH901
-comment "ST-Ericsson U300/U330/U335/U365 Feature Selections"
+comment "ST-Ericsson U300/U335 Feature Selections"
-choice
-        prompt "U300/U330/U335/U365 system type"
-        default MACH_U300_BS2X
-        ---help---
-        You need to select the target system, i.e. the
-        U300/U330/U335/U365 board that you want to compile your kernel
-        for.
-config MACH_U300_BS2X
-        bool "S26/S26/B25/B26 Test Products"
-        depends on MACH_U300
-        help
-                Select this if you're developing on the
-                S26/S25 test products. (Also works on
-                B26/B25 big boards.)
-config MACH_U300_BS330
-        bool "S330/B330 Test Products"
-        depends on MACH_U300
-        help
-                Select this if you're developing on the
-                S330/B330 test products.
-config MACH_U300_BS335
-        bool "S335/B335 Test Products"
-        depends on MACH_U300
-        help
-                Select this if you're developing on the
-                S335/B335 test products.
-config MACH_U300_BS365
-        bool "S365/B365 Test Products"
-        depends on MACH_U300
-        help
-                Select this if you're developing on the
-                S365/B365 test products.
-endchoice
 config U300_DEBUG
        bool "Debug support for U300"
diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile
index 7e47d37aeb0e..5a86c58da396 100644
--- a/arch/arm/mach-u300/Makefile
+++ b/arch/arm/mach-u300/Makefile
@@ -7,7 +7,6 @@ obj-m		:=
 obj-n           :=
 obj-            :=
-obj-$(CONFIG_ARCH_U300)           += u300.o
 obj-$(CONFIG_SPI_PL022)           += spi.o
 obj-$(CONFIG_MACH_U300_SPIDUMMY)  += dummyspichip.o
 obj-$(CONFIG_I2C_STU300)          += i2c.o
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 03acf1883ec7..ef6f602b7e48 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -3,7 +3,7 @@
 * arch/arm/mach-u300/core.c
 *
 *
- * Copyright (C) 2007-2010 ST-Ericsson SA
+ * Copyright (C) 2007-2012 ST-Ericsson SA
 * License terms: GNU General Public License (GPL) version 2
 * Core platform support, IRQ handling and device definitions.
 * Author: Linus Walleij <linus.walleij@stericsson.com>
@@ -31,23 +31,26 @@
 #include <linux/pinctrl/pinconf-generic.h>
 #include <linux/dma-mapping.h>
 #include <linux/platform_data/clk-u300.h>
+#include <linux/platform_data/pinctrl-coh901.h>
 #include <asm/types.h>
 #include <asm/setup.h>
 #include <asm/memory.h>
 #include <asm/hardware/vic.h>
 #include <asm/mach/map.h>
-#include <asm/mach/irq.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
 #include <mach/coh901318.h>
 #include <mach/hardware.h>
 #include <mach/syscon.h>
-#include <mach/dma_channels.h>
+#include <mach/irqs.h>
-#include <mach/gpio-u300.h>
+#include "timer.h"
 #include "spi.h"
 #include "i2c.h"
 #include "u300-gpio.h"
+#include "dma_channels.h"
 /*
 * Static I/O mappings that are needed for booting the U300 platforms. The
@@ -76,7 +79,7 @@ static struct map_desc u300_io_desc[] __initdata = {
        },
 };
-void __init u300_map_io(void)
+static void __init u300_map_io(void)
 {
        iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
        /* We enable a real big DMA buffer if need be. */
@@ -101,7 +104,6 @@ static AMBA_APB_DEVICE(uart0, "uart0", 0, U300_UART0_BASE,
        { IRQ_U300_UART0 }, &uart0_plat_data);
 /* The U335 have an additional UART1 on the APP CPU */
-#ifdef CONFIG_MACH_U300_BS335
 static struct amba_pl011_data uart1_plat_data = {
 #ifdef CONFIG_COH901318
        .dma_filter = coh901318_filter_id,
@@ -113,7 +115,6 @@ static struct amba_pl011_data uart1_plat_data = {
 /* Fast device at 0x7000 offset */
 static AMBA_APB_DEVICE(uart1, "uart1", 0, U300_UART1_BASE,
        { IRQ_U300_UART1 }, &uart1_plat_data);
-#endif
 /* AHB device at 0x4000 offset */
 static AMBA_APB_DEVICE(pl172, "pl172", 0, U300_EMIF_CFG_BASE, { }, NULL);
@@ -152,9 +153,7 @@ static AMBA_APB_DEVICE(mmcsd, "mmci", 0, U300_MMCSD_BASE,
 */
 static struct amba_device *amba_devs[] __initdata = {
        &uart0_device,
-#ifdef CONFIG_MACH_U300_BS335
        &uart1_device,
-#endif
        &pl022_device,
        &pl172_device,
        &mmcsd_device,
@@ -188,7 +187,6 @@ static struct resource gpio_resources[] = {
                .end   = IRQ_U300_GPIO_PORT2,
                .flags = IORESOURCE_IRQ,
        },
-#if defined(CONFIG_MACH_U300_BS365) || defined(CONFIG_MACH_U300_BS335)
        {
                .name  = "gpio3",
                .start = IRQ_U300_GPIO_PORT3,
@@ -201,8 +199,6 @@ static struct resource gpio_resources[] = {
                .end   = IRQ_U300_GPIO_PORT4,
                .flags = IORESOURCE_IRQ,
        },
-#endif
-#ifdef CONFIG_MACH_U300_BS335
        {
                .name  = "gpio5",
                .start = IRQ_U300_GPIO_PORT5,
@@ -215,7 +211,6 @@ static struct resource gpio_resources[] = {
                .end   = IRQ_U300_GPIO_PORT6,
                .flags = IORESOURCE_IRQ,
        },
-#endif /* CONFIG_MACH_U300_BS335 */
 };
 static struct resource keypad_resources[] = {
@@ -323,7 +318,6 @@ static struct resource dma_resource[] = {
        }
 };
-#ifdef CONFIG_MACH_U300_BS335
 /* points out all dma slave channels.
 * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
 * Select all channels from A to B, end of list is marked with -1,-1
@@ -336,14 +330,6 @@ static int dma_slave_channels[] = {
 static int dma_memcpy_channels[] = {
        U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
-#else /* CONFIG_MACH_U300_BS335 */
-static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1};
-static int dma_memcpy_channels[] = {
-        U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1};
-#endif
 /** register dma for memory access
 *
 * active  1 means dma intends to access memory
@@ -1395,7 +1381,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                .param.ctrl_lli = flags_memcpy_lli,
                .param.ctrl_lli_last = flags_memcpy_lli_last,
        },
-#ifdef CONFIG_MACH_U300_BS335
        {
                .number = U300_DMA_UART1_TX,
                .name = "UART1 TX",
@@ -1406,28 +1391,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                .name = "UART1 RX",
                .priority_high = 0,
        }
-#else
-        {
-                .number = U300_DMA_GENERAL_PURPOSE_9,
-                .name = "GENERAL 09",
-                .priority_high = 0,
-                .param.config = flags_memcpy_config,
-                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-                .param.ctrl_lli = flags_memcpy_lli,
-                .param.ctrl_lli_last = flags_memcpy_lli_last,
-        },
-        {
-                .number = U300_DMA_GENERAL_PURPOSE_10,
-                .name = "GENERAL 10",
-                .priority_high = 0,
-                .param.config = flags_memcpy_config,
-                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-                .param.ctrl_lli = flags_memcpy_lli,
-                .param.ctrl_lli_last = flags_memcpy_lli_last,
-        }
-#endif
 };
@@ -1480,18 +1443,7 @@ static struct platform_device pinctrl_device = {
 * GPIO block, with different number of ports.
 */
 static struct u300_gpio_platform u300_gpio_plat = {
-#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
-        .variant = U300_GPIO_COH901335,
-        .ports = 3,
-#endif
-#ifdef CONFIG_MACH_U300_BS335
-        .variant = U300_GPIO_COH901571_3_BS335,
        .ports = 7,
-#endif
-#ifdef CONFIG_MACH_U300_BS365
-        .variant = U300_GPIO_COH901571_3_BS365,
-        .ports = 5,
-#endif
        .gpio_base = 0,
        .gpio_irq_base = IRQ_U300_GPIO_BASE,
        .pinctrl_device = &pinctrl_device,
@@ -1651,7 +1603,7 @@ static struct platform_device *platform_devs[] __initdata = {
 * together so some interrupts are connected to the first one and some
 * to the second one.
 */
-void __init u300_init_irq(void)
+static void __init u300_init_irq(void)
 {
        u32 mask[2] = {0, 0};
        struct clk *clk;
@@ -1756,29 +1708,11 @@ static void __init u300_init_check_chip(void)
        printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
               "(chip ID 0x%04x)\n", chipname, val);
-#ifdef CONFIG_MACH_U300_BS330
-        if ((val & 0xFF00U) != 0xd800) {
-                printk(KERN_ERR "Platform configured for BS330 " \
-                       "with DB3200 but %s detected, expect problems!",
-                       chipname);
-        }
-#endif
-#ifdef CONFIG_MACH_U300_BS335
        if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
                printk(KERN_ERR "Platform configured for BS335 " \
                       " with DB3350 but %s detected, expect problems!",
                       chipname);
        }
-#endif
-#ifdef CONFIG_MACH_U300_BS365
-        if ((val & 0xFF00U) != 0xe800) {
-                printk(KERN_ERR "Platform configured for BS365 " \
-                       "with DB3210 but %s detected, expect problems!",
-                       chipname);
-        }
-#endif
 }
 /*
@@ -1811,7 +1745,7 @@ static void __init u300_assign_physmem(void)
        }
 }
-void __init u300_init_devices(void)
+static void __init u300_init_machine(void)
 {
        int i;
        u16 val;
@@ -1852,7 +1786,7 @@ void __init u300_init_devices(void)
 /* Forward declare this function from the watchdog */
 void coh901327_watchdog_reset(void);
-void u300_restart(char mode, const char *cmd)
+static void u300_restart(char mode, const char *cmd)
 {
        switch (mode) {
        case 's':
@@ -1868,3 +1802,15 @@ void u300_restart(char mode, const char *cmd)
        /* Wait for system do die/reset. */
        while (1);
 }
+MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board")
+        /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
+        .atag_offset    = 0x100,
+        .map_io         = u300_map_io,
+        .nr_irqs        = NR_IRQS_U300,
+        .init_irq       = u300_init_irq,
+        .handle_irq     = vic_handle_irq,
+        .timer          = &u300_timer,
+        .init_machine   = u300_init_machine,
+        .restart        = u300_restart,
+MACHINE_END
diff --git a/arch/arm/mach-u300/include/mach/dma_channels.h b/arch/arm/mach-u300/dma_channels.h
index b239149ba0d0..4e8a88fbca49 100644
--- a/arch/arm/mach-u300/include/mach/dma_channels.h
+++ b/arch/arm/mach-u300/dma_channels.h
@@ -3,7 +3,7 @@
 * arch/arm/mach-u300/include/mach/dma_channels.h
 *
 *
- * Copyright (C) 2007-2009 ST-Ericsson
+ * Copyright (C) 2007-2012 ST-Ericsson
 * License terms: GNU General Public License (GPL) version 2
 * Map file for the U300 dma driver.
 * Author: Per Friden <per.friden@stericsson.com>
@@ -50,19 +50,10 @@
 #define U300_DMA_GENERAL_PURPOSE_6    35
 #define U300_DMA_GENERAL_PURPOSE_7    36
 #define U300_DMA_GENERAL_PURPOSE_8    37
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_DMA_UART1_TX             38
 #define U300_DMA_UART1_RX             39
-#else
-#define U300_DMA_GENERAL_PURPOSE_9    38
-#define U300_DMA_GENERAL_PURPOSE_10   39
-#endif
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_DMA_DEVICE_CHANNELS      32
-#else
-#define U300_DMA_DEVICE_CHANNELS      30
-#endif
 #define U300_DMA_CHANNELS             40
diff --git a/arch/arm/mach-u300/i2c.c b/arch/arm/mach-u300/i2c.c
index cb04bd6ab3e7..0d4620ed853c 100644
--- a/arch/arm/mach-u300/i2c.c
+++ b/arch/arm/mach-u300/i2c.c
@@ -1,7 +1,7 @@
 /*
 * arch/arm/mach-u300/i2c.c
 *
- * Copyright (C) 2009 ST-Ericsson AB
+ * Copyright (C) 2009-2012 ST-Ericsson AB
 * License terms: GNU General Public License (GPL) version 2
 *
 * Register board i2c devices
@@ -261,7 +261,6 @@ static struct i2c_board_info __initdata bus0_i2c_board_info[] = {
 };
 static struct i2c_board_info __initdata bus1_i2c_board_info[] = {
-#ifdef CONFIG_MACH_U300_BS335
        {
                .type = "fwcam",
                .addr = 0x10,
@@ -270,9 +269,6 @@ static struct i2c_board_info __initdata bus1_i2c_board_info[] = {
                .type = "fwcam",
                .addr = 0x5d,
        },
-#else
-        { },
-#endif
 };
 void __init u300_i2c_register_board_devices(void)
diff --git a/arch/arm/mach-u300/include/mach/clkdev.h b/arch/arm/mach-u300/include/mach/clkdev.h
deleted file mode 100644
index 92e3cc872c66..000000000000
--- a/arch/arm/mach-u300/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __MACH_CLKDEV_H
-#define __MACH_CLKDEV_H
-int __clk_get(struct clk *clk);
-void __clk_put(struct clk *clk);
-#endif
diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h
index ec09c1e07b1a..e27425a63fa1 100644
--- a/arch/arm/mach-u300/include/mach/irqs.h
+++ b/arch/arm/mach-u300/include/mach/irqs.h
@@ -3,7 +3,7 @@
 * arch/arm/mach-u300/include/mach/irqs.h
 *
 *
- * Copyright (C) 2006-2009 ST-Ericsson AB
+ * Copyright (C) 2006-2012 ST-Ericsson AB
 * License terms: GNU General Public License (GPL) version 2
 * IRQ channel definitions for the U300 platforms.
 * Author: Linus Walleij <linus.walleij@stericsson.com>
@@ -31,10 +31,6 @@
 #define IRQ_U300_XGAM_GAMCON            14
 #define IRQ_U300_XGAM_CDI               15
 #define IRQ_U300_XGAM_CDICON            16
-#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
-/* MMIACC not used on the DB3210 or DB3350 chips */
-#define IRQ_U300_XGAM_MMIACC            17
-#endif
 #define IRQ_U300_XGAM_PDI               18
 #define IRQ_U300_XGAM_PDICON            19
 #define IRQ_U300_XGAM_GAMEACC           20
@@ -55,8 +51,6 @@
 #define IRQ_U300_GPIO_PORT1             34
 #define IRQ_U300_GPIO_PORT2             35
-#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \
-    defined(CONFIG_MACH_U300_BS335)
 /* These are for DB3150, DB3200 and DB3350 */
 #define IRQ_U300_WDOG                   36
 #define IRQ_U300_EVHIST                 37
@@ -68,15 +62,8 @@
 #define IRQ_U300_RTC                    43
 #define IRQ_U300_NFIF                   44
 #define IRQ_U300_NFIF2                  45
-#endif
-/* DB3150 and DB3200 have only 45 IRQs */
-#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
-#define U300_VIC_IRQS_END               46
-#endif
 /* The DB3350-specific interrupt lines */
-#ifdef CONFIG_MACH_U300_BS335
 #define IRQ_U300_ISP_F0                 46
 #define IRQ_U300_ISP_F1                 47
 #define IRQ_U300_ISP_F2                 48
@@ -89,25 +76,6 @@
 #define IRQ_U300_GPIO_PORT5             55
 #define IRQ_U300_GPIO_PORT6             56
 #define U300_VIC_IRQS_END               57
-#endif
-/* The DB3210-specific interrupt lines */
-#ifdef CONFIG_MACH_U300_BS365
-#define IRQ_U300_GPIO_PORT3             36
-#define IRQ_U300_GPIO_PORT4             37
-#define IRQ_U300_WDOG                   38
-#define IRQ_U300_EVHIST                 39
-#define IRQ_U300_MSPRO                  40
-#define IRQ_U300_MMCSD_MCIINTR0         41
-#define IRQ_U300_MMCSD_MCIINTR1         42
-#define IRQ_U300_I2C0                   43
-#define IRQ_U300_I2C1                   44
-#define IRQ_U300_RTC                    45
-#define IRQ_U300_NFIF                   46
-#define IRQ_U300_NFIF2                  47
-#define IRQ_U300_SYSCON_PLL_LOCK        48
-#define U300_VIC_IRQS_END               49
-#endif
 /* Maximum 8*7 GPIO lines */
 #ifdef CONFIG_PINCTRL_COH901
@@ -117,6 +85,6 @@
 #define IRQ_U300_GPIO_END               (U300_VIC_IRQS_END)
 #endif
-#define NR_IRQS                         (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START)
+#define NR_IRQS_U300                    (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START)
 #endif
diff --git a/arch/arm/mach-u300/include/mach/platform.h b/arch/arm/mach-u300/include/mach/platform.h
deleted file mode 100644
index 096333f32fc3..000000000000
--- a/arch/arm/mach-u300/include/mach/platform.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/platform.h
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * Basic platform init and mapping functions.
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-#ifndef __ASSEMBLY__
-void u300_map_io(void);
-void u300_init_irq(void);
-void u300_init_devices(void);
-void u300_restart(char, const char *);
-extern struct sys_timer u300_timer;
-#endif
diff --git a/arch/arm/mach-u300/include/mach/syscon.h b/arch/arm/mach-u300/include/mach/syscon.h
index 6e84f07a7c6f..10bdd0be9774 100644
--- a/arch/arm/mach-u300/include/mach/syscon.h
+++ b/arch/arm/mach-u300/include/mach/syscon.h
@@ -3,7 +3,7 @@
 * arch/arm/mach-u300/include/mach/syscon.h
 *
 *
- * Copyright (C) 2008 ST-Ericsson AB
+ * Copyright (C) 2008-2012 ST-Ericsson AB
 *
 * Author: Rickard Andersson <rickard.andersson@stericsson.com>
 */
@@ -36,9 +36,7 @@
 #define U300_SYSCON_CSR_PLL13_LOCK_IND                          (0x0001)
 /* Reset lines for SLOW devices 16bit (R/W) */
 #define U300_SYSCON_RSR                                         (0x0014)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_RSR_PPM_RESET_EN                            (0x0200)
-#endif
 #define U300_SYSCON_RSR_ACC_TMR_RESET_EN                        (0x0100)
 #define U300_SYSCON_RSR_APP_TMR_RESET_EN                        (0x0080)
 #define U300_SYSCON_RSR_RTC_RESET_EN                            (0x0040)
@@ -50,9 +48,7 @@
 #define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN                    (0x0001)
 /* Reset lines for FAST devices 16bit (R/W) */
 #define U300_SYSCON_RFR                                         (0x0018)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_RFR_UART1_RESET_ENABLE                      (0x0080)
-#endif
 #define U300_SYSCON_RFR_SPI_RESET_ENABLE                        (0x0040)
 #define U300_SYSCON_RFR_MMC_RESET_ENABLE                        (0x0020)
 #define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE                   (0x0010)
@@ -62,10 +58,8 @@
 #define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE                (0x0001)
 /* Reset lines for the rest of the peripherals 16bit (R/W) */
 #define U300_SYSCON_RRR                                         (0x001c)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_RRR_CDS_RESET_EN                            (0x4000)
 #define U300_SYSCON_RRR_ISP_RESET_EN                            (0x2000)
-#endif
 #define U300_SYSCON_RRR_INTCON_RESET_EN                         (0x1000)
 #define U300_SYSCON_RRR_MSPRO_RESET_EN                          (0x0800)
 #define U300_SYSCON_RRR_XGAM_RESET_EN                           (0x0100)
@@ -79,9 +73,7 @@
 #define U300_SYSCON_RRR_AAIF_RESET_EN                           (0x0001)
 /* Clock enable for SLOW peripherals 16bit (R/W) */
 #define U300_SYSCON_CESR                                        (0x0020)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_CESR_PPM_CLK_EN                             (0x0200)
-#endif
 #define U300_SYSCON_CESR_ACC_TMR_CLK_EN                         (0x0100)
 #define U300_SYSCON_CESR_APP_TMR_CLK_EN                         (0x0080)
 #define U300_SYSCON_CESR_KEYPAD_CLK_EN                          (0x0040)
@@ -92,24 +84,20 @@
 #define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN                     (0x0001)
 /* Clock enable for FAST peripherals 16bit (R/W) */
 #define U300_SYSCON_CEFR                                        (0x0024)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_CEFR_UART1_CLK_EN                           (0x0200)
-#endif
 #define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN                       (0x0100)
 #define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN                       (0x0080)
 #define U300_SYSCON_CEFR_SPI_CLK_EN                             (0x0040)
 #define U300_SYSCON_CEFR_MMC_CLK_EN                             (0x0020)
-#define U300_SYSCON_CEFR_I2S1_CLK_EN                            (0x0010)
+#define U300_SYSCON_CEFR_I2S1_CLK_EN                            (0x0010)
-#define U300_SYSCON_CEFR_I2S0_CLK_EN                            (0x0008)
+#define U300_SYSCON_CEFR_I2S0_CLK_EN                            (0x0008)
-#define U300_SYSCON_CEFR_I2C1_CLK_EN                            (0x0004)
+#define U300_SYSCON_CEFR_I2C1_CLK_EN                            (0x0004)
-#define U300_SYSCON_CEFR_I2C0_CLK_EN                            (0x0002)
+#define U300_SYSCON_CEFR_I2C0_CLK_EN                            (0x0002)
 #define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN                     (0x0001)
 /* Clock enable for the rest of the peripherals 16bit (R/W) */
 #define U300_SYSCON_CERR                                        (0x0028)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_CERR_CDS_CLK_EN                             (0x2000)
 #define U300_SYSCON_CERR_ISP_CLK_EN                             (0x1000)
-#endif
 #define U300_SYSCON_CERR_MSPRO_CLK_EN                           (0x0800)
 #define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN               (0x0400)
 #define U300_SYSCON_CERR_SEMI_CLK_EN                            (0x0200)
@@ -124,9 +112,7 @@
 #define U300_SYSCON_CERR_AAIF_CLK_EN                            (0x0001)
 /* Single block clock enable 16bit (-/W) */
 #define U300_SYSCON_SBCER                                       (0x002c)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_SBCER_PPM_CLK_EN                            (0x0009)
-#endif
 #define U300_SYSCON_SBCER_ACC_TMR_CLK_EN                        (0x0008)
 #define U300_SYSCON_SBCER_APP_TMR_CLK_EN                        (0x0007)
 #define U300_SYSCON_SBCER_KEYPAD_CLK_EN                         (0x0006)
@@ -135,9 +121,7 @@
 #define U300_SYSCON_SBCER_BTR_CLK_EN                            (0x0002)
 #define U300_SYSCON_SBCER_UART_CLK_EN                           (0x0001)
 #define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN                    (0x0000)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_SBCER_UART1_CLK_EN                          (0x0019)
-#endif
 #define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN                      (0x0018)
 #define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN                      (0x0017)
 #define U300_SYSCON_SBCER_SPI_CLK_EN                            (0x0016)
@@ -147,10 +131,8 @@
 #define U300_SYSCON_SBCER_I2C1_CLK_EN                           (0x0012)
 #define U300_SYSCON_SBCER_I2C0_CLK_EN                           (0x0011)
 #define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN                    (0x0010)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_SBCER_CDS_CLK_EN                            (0x002D)
 #define U300_SYSCON_SBCER_ISP_CLK_EN                            (0x002C)
-#endif
 #define U300_SYSCON_SBCER_MSPRO_CLK_EN                          (0x002B)
 #define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN              (0x002A)
 #define U300_SYSCON_SBCER_SEMI_CLK_EN                           (0x0029)
@@ -168,9 +150,7 @@
 /* Same values as above for SBCER */
 /* Clock force SLOW peripherals 16bit (R/W) */
 #define U300_SYSCON_CFSR                                        (0x003c)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN                       (0x0200)
-#endif
 #define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN                   (0x0100)
 #define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN                   (0x0080)
 #define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN                    (0x0020)
@@ -184,10 +164,8 @@
 /* Values not defined. Define if you want to use them. */
 /* Clock force the rest of the peripherals 16bit (R/W) */
 #define U300_SYSCON_CFRR                                        (0x44)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN                       (0x2000)
 #define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN                       (0x1000)
-#endif
 #define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN                     (0x0800)
 #define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN         (0x0400)
 #define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN                      (0x0200)
diff --git a/arch/arm/mach-u300/include/mach/u300-regs.h b/arch/arm/mach-u300/include/mach/u300-regs.h
index 65f87c523892..1e49d901f2c9 100644
--- a/arch/arm/mach-u300/include/mach/u300-regs.h
+++ b/arch/arm/mach-u300/include/mach/u300-regs.h
@@ -28,7 +28,6 @@
 #define PLAT_NAND_CLE                   (1 << 16)
 #define PLAT_NAND_ALE                   (1 << 17)
 /* AHB Peripherals */
 #define U300_AHB_PER_PHYS_BASE          0xa0000000
 #define U300_AHB_PER_VIRT_BASE          0xff010000
@@ -46,11 +45,7 @@
 #define U300_BOOTROM_VIRT_BASE          0xffff0000
 /* SEMI config base */
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SEMI_CONFIG_BASE           0x2FFE0000
-#else
-#define U300_SEMI_CONFIG_BASE           0x30000000
-#endif
 /*
 * AHB peripherals
@@ -99,10 +94,8 @@
 /* SPI controller */
 #define U300_SPI_BASE                   (U300_FAST_PER_PHYS_BASE+0x6000)
-#ifdef CONFIG_MACH_U300_BS335
 /* Fast UART1 on U335 only */
 #define U300_UART1_BASE                 (U300_SLOW_PER_PHYS_BASE+0x7000)
-#endif
 /*
 * SLOW peripherals
@@ -151,10 +144,8 @@
 * REST peripherals
 */
-/* ISP (image signal processor) is only available in U335 */
+/* ISP (image signal processor) */
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_ISP_BASE                   (0xA0008000)
-#endif
 /* DMA Controller base */
 #define U300_DMAC_BASE                  (0xC0020000)
@@ -166,17 +157,9 @@
 #define U300_APEX_BASE                  (0xc0030000)
 /* Video Encoder Base */
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_VIDEOENC_BASE              (0xc0080000)
-#else
-#define U300_VIDEOENC_BASE              (0xc0040000)
-#endif
 /* XGAM Base */
 #define U300_XGAM_BASE                  (0xd0000000)
-/*
- * Virtual accessor macros for static devices
- */
 #endif
diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c
index a1affacfa59c..02e6659286d5 100644
--- a/arch/arm/mach-u300/spi.c
+++ b/arch/arm/mach-u300/spi.c
@@ -12,7 +12,7 @@
 #include <linux/amba/pl022.h>
 #include <linux/err.h>
 #include <mach/coh901318.h>
-#include <mach/dma_channels.h>
+#include "dma_channels.h"
 /*
 * The following is for the actual devices on the SSP/SPI bus
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index 56ac06d38ec1..1da10e20e996 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -17,14 +17,17 @@
 #include <linux/io.h>
 #include <linux/clk.h>
 #include <linux/err.h>
+#include <linux/irq.h>
 #include <mach/hardware.h>
+#include <mach/irqs.h>
 /* Generic stuff */
 #include <asm/sched_clock.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <asm/mach/irq.h>
+#include "timer.h"
 /*
 * APP side special timer registers
diff --git a/arch/arm/mach-u300/timer.h b/arch/arm/mach-u300/timer.h
new file mode 100644
index 000000000000..b5e9791762e0
--- /dev/null
+++ b/arch/arm/mach-u300/timer.h
@@ -0,0 +1 @@
+extern struct sys_timer u300_timer;
diff --git a/arch/arm/mach-u300/u300-gpio.h b/arch/arm/mach-u300/u300-gpio.h
index 847dc25300c6..83f50772e169 100644
--- a/arch/arm/mach-u300/u300-gpio.h
+++ b/arch/arm/mach-u300/u300-gpio.h
@@ -1,50 +1,11 @@
 /*
- * Individual pin assignments for the B26/S26. Notice that the
+ * Individual pin assignments for the B335/S335.
- * actual usage of these pins depends on the PAD MUX settings, that
- * is why the same number can potentially appear several times.
- * In the reference design each pin is only used for one purpose.
- * These were determined by inspecting the B26/S26 schematic:
- * 2/1911-ROA 128 1603
- */
-#ifdef CONFIG_MACH_U300_BS2X
-#define U300_GPIO_PIN_UART_RX           0
-#define U300_GPIO_PIN_UART_TX           1
-#define U300_GPIO_PIN_GPIO02            2  /* Unrouted */
-#define U300_GPIO_PIN_GPIO03            3  /* Unrouted */
-#define U300_GPIO_PIN_CAM_SLEEP         4
-#define U300_GPIO_PIN_CAM_REG_EN        5
-#define U300_GPIO_PIN_GPIO06            6  /* Unrouted */
-#define U300_GPIO_PIN_GPIO07            7  /* Unrouted */
-#define U300_GPIO_PIN_GPIO08            8  /* Service point SP2321 */
-#define U300_GPIO_PIN_GPIO09            9  /* Service point SP2322 */
-#define U300_GPIO_PIN_PHFSENSE          10 /* Headphone jack sensing */
-#define U300_GPIO_PIN_MMC_CLKRET        11 /* Clock return from MMC/SD card */
-#define U300_GPIO_PIN_MMC_CD            12 /* MMC Card insertion detection */
-#define U300_GPIO_PIN_FLIPSENSE         13 /* Mechanical flip sensing */
-#define U300_GPIO_PIN_GPIO14            14 /* DSP JTAG Port RTCK */
-#define U300_GPIO_PIN_GPIO15            15 /* Unrouted */
-#define U300_GPIO_PIN_GPIO16            16 /* Unrouted */
-#define U300_GPIO_PIN_GPIO17            17 /* Unrouted */
-#define U300_GPIO_PIN_GPIO18            18 /* Unrouted */
-#define U300_GPIO_PIN_GPIO19            19 /* Unrouted */
-#define U300_GPIO_PIN_GPIO20            20 /* Unrouted */
-#define U300_GPIO_PIN_GPIO21            21 /* Unrouted */
-#define U300_GPIO_PIN_GPIO22            22 /* Unrouted */
-#define U300_GPIO_PIN_GPIO23            23 /* Unrouted */
-#endif
-/*
- * Individual pin assignments for the B330/S330 and B365/S365.
 * Notice that the actual usage of these pins depends on the
 * PAD MUX settings, that is why the same number can potentially
 * appear several times. In the reference design each pin is only
 * used for one purpose. These were determined by inspecting the
 * S365 schematic.
 */
-#if defined(CONFIG_MACH_U300_BS330) || defined(CONFIG_MACH_U300_BS365) || \
-    defined(CONFIG_MACH_U300_BS335)
 #define U300_GPIO_PIN_UART_RX           0
 #define U300_GPIO_PIN_UART_TX           1
 #define U300_GPIO_PIN_UART_CTS          2
@@ -90,8 +51,6 @@
 #define U300_GPIO_PIN_GPIO38            38 /* Unrouted */
 #define U300_GPIO_PIN_GPIO39            39 /* Unrouted */
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_GPIO_PIN_GPIO40            40 /* Unrouted */
 #define U300_GPIO_PIN_GPIO41            41 /* Unrouted */
 #define U300_GPIO_PIN_GPIO42            42 /* Unrouted */
@@ -109,6 +68,3 @@
 #define U300_GPIO_PIN_GPIO53            53 /* Unrouted */
 #define U300_GPIO_PIN_GPIO54            54 /* Unrouted */
 #define U300_GPIO_PIN_GPIO55            55 /* Unrouted */
-#endif
-#endif
diff --git a/arch/arm/mach-u300/u300.c b/arch/arm/mach-u300/u300.c
deleted file mode 100644
index f30c69d91d99..000000000000
--- a/arch/arm/mach-u300/u300.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/u300.c
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * Platform machine definition.
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/memblock.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/platform.h>
-#include <asm/hardware/vic.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/memory.h>
-static void __init u300_init_machine(void)
-{
-        u300_init_devices();
-}
-#ifdef CONFIG_MACH_U300_BS2X
-#define MACH_U300_STRING "Ericsson AB U300 S25/S26/B25/B26 Prototype Board"
-#endif
-#ifdef CONFIG_MACH_U300_BS330
-#define MACH_U300_STRING "Ericsson AB U330 S330/B330 Prototype Board"
-#endif
-#ifdef CONFIG_MACH_U300_BS335
-#define MACH_U300_STRING "Ericsson AB U335 S335/B335 Prototype Board"
-#endif
-#ifdef CONFIG_MACH_U300_BS365
-#define MACH_U300_STRING "Ericsson AB U365 S365/B365 Prototype Board"
-#endif
-MACHINE_START(U300, MACH_U300_STRING)
-        /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
-        .atag_offset    = 0x100,
-        .map_io         = u300_map_io,
-        .init_irq       = u300_init_irq,
-        .handle_irq     = vic_handle_irq,
-        .timer          = &u300_timer,
-        .init_machine   = u300_init_machine,
-        .restart        = u300_restart,
-MACHINE_END
diff --git a/drivers/mtd/nand/bcm_umi_nand.c b/drivers/mtd/nand/bcm_umi_nand.c
index c855e7cd337b..d0d1bd4d0e7d 100644
--- a/drivers/mtd/nand/bcm_umi_nand.c
+++ b/drivers/mtd/nand/bcm_umi_nand.c
@@ -249,20 +249,20 @@ static int nand_dev_ready(struct mtd_info *mtd)
 int bcm_umi_nand_inithw(void)
 {
        /* Configure nand timing parameters */
-        REG_UMI_NAND_TCR &= ~0x7ffff;
+        writel(readl(&REG_UMI_NAND_TCR) & ~0x7ffff, &REG_UMI_NAND_TCR);
-        REG_UMI_NAND_TCR |= HW_CFG_NAND_TCR;
+        writel(readl(&REG_UMI_NAND_TCR) | HW_CFG_NAND_TCR, &REG_UMI_NAND_TCR);
 #if !defined(CONFIG_MTD_NAND_BCM_UMI_HWCS)
        /* enable software control of CS */
-        REG_UMI_NAND_TCR |= REG_UMI_NAND_TCR_CS_SWCTRL;
+        writel(readl(&REG_UMI_NAND_TCR) | REG_UMI_NAND_TCR_CS_SWCTRL, &REG_UMI_NAND_TCR);
 #endif
        /* keep NAND chip select asserted */
-        REG_UMI_NAND_RCSR |= REG_UMI_NAND_RCSR_CS_ASSERTED;
+        writel(readl(&REG_UMI_NAND_RCSR) | REG_UMI_NAND_RCSR_CS_ASSERTED, &REG_UMI_NAND_RCSR);
-        REG_UMI_NAND_TCR &= ~REG_UMI_NAND_TCR_WORD16;
+        writel(readl(&REG_UMI_NAND_TCR) & ~REG_UMI_NAND_TCR_WORD16, &REG_UMI_NAND_TCR);
        /* enable writes to flash */
-        REG_UMI_MMD_ICR |= REG_UMI_MMD_ICR_FLASH_WP;
+        writel(readl(&REG_UMI_MMD_ICR) | REG_UMI_MMD_ICR_FLASH_WP, &REG_UMI_MMD_ICR);
        writel(NAND_CMD_RESET, bcm_umi_io_base + REG_NAND_CMD_OFFSET);
        nand_bcm_umi_wait_till_ready();
diff --git a/drivers/mtd/nand/nand_bcm_umi.h b/drivers/mtd/nand/nand_bcm_umi.h
index 198b304d6f72..d90186684db8 100644
--- a/drivers/mtd/nand/nand_bcm_umi.h
+++ b/drivers/mtd/nand/nand_bcm_umi.h
@@ -17,7 +17,7 @@
 /* ---- Include Files ---------------------------------------------------- */
 #include <mach/reg_umi.h>
 #include <mach/reg_nand.h>
-#include <cfg_global.h>
+#include <mach/cfg_global.h>
 /* ---- Constants and Types ---------------------------------------------- */
 #if (CFG_GLOBAL_CHIP_FAMILY == CFG_GLOBAL_CHIP_FAMILY_BCMRING)
@@ -48,7 +48,7 @@ int nand_bcm_umi_bch_correct_page(uint8_t *datap, uint8_t *readEccData,
 /* Check in device is ready */
 static inline int nand_bcm_umi_dev_ready(void)
 {
-        return REG_UMI_NAND_RCSR & REG_UMI_NAND_RCSR_RDY;
+        return readl(&REG_UMI_NAND_RCSR) & REG_UMI_NAND_RCSR_RDY;
 }
 /* Wait until device is ready */
@@ -62,10 +62,11 @@ static inline void nand_bcm_umi_wait_till_ready(void)
 static inline void nand_bcm_umi_hamming_enable_hwecc(void)
 {
        /* disable and reset ECC, 512 byte page */
-        REG_UMI_NAND_ECC_CSR &= ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE |
+        writel(readl(&REG_UMI_NAND_ECC_CSR) & ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE |
-                REG_UMI_NAND_ECC_CSR_256BYTE);
+                REG_UMI_NAND_ECC_CSR_256BYTE), &REG_UMI_NAND_ECC_CSR);
        /* enable ECC */
-        REG_UMI_NAND_ECC_CSR |= REG_UMI_NAND_ECC_CSR_ECC_ENABLE;
+        writel(readl(&REG_UMI_NAND_ECC_CSR) | REG_UMI_NAND_ECC_CSR_ECC_ENABLE,
+                &REG_UMI_NAND_ECC_CSR);
 }
 #if NAND_ECC_BCH
@@ -76,18 +77,18 @@ static inline void nand_bcm_umi_hamming_enable_hwecc(void)
 static inline void nand_bcm_umi_bch_enable_read_hwecc(void)
 {
        /* disable and reset ECC */
-        REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID;
+        writel(REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID, &REG_UMI_BCH_CTRL_STATUS);
        /* Turn on ECC */
-        REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN;
+        writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN, &REG_UMI_BCH_CTRL_STATUS);
 }
 /* Enable BCH Write ECC */
 static inline void nand_bcm_umi_bch_enable_write_hwecc(void)
 {
        /* disable and reset ECC */
-        REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID;
+        writel(REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID, &REG_UMI_BCH_CTRL_STATUS);
        /* Turn on ECC */
-        REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN;
+        writel(REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN, &REG_UMI_BCH_CTRL_STATUS);
 }
 /* Config number of BCH ECC bytes */
@@ -99,9 +100,9 @@ static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes)
        uint32_t numBits = numEccBytes * 8;
        /* disable and reset ECC */
-        REG_UMI_BCH_CTRL_STATUS =
+        writel(REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID |
-            REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID |
+               REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID,
-            REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID;
+               &REG_UMI_BCH_CTRL_STATUS);
        /* Every correctible bit requires 13 ECC bits */
        tValue = (uint32_t) (numBits / ECC_BITS_PER_CORRECTABLE_BIT);
@@ -113,23 +114,21 @@ static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes)
        kValue = nValue - (tValue * ECC_BITS_PER_CORRECTABLE_BIT);
        /* Write the settings */
-        REG_UMI_BCH_N = nValue;
+        writel(nValue, &REG_UMI_BCH_N);
-        REG_UMI_BCH_T = tValue;
+        writel(tValue, &REG_UMI_BCH_T);
-        REG_UMI_BCH_K = kValue;
+        writel(kValue, &REG_UMI_BCH_K);
 }
 /* Pause during ECC read calculation to skip bytes in OOB */
 static inline void nand_bcm_umi_bch_pause_read_ecc_calc(void)
 {
-        REG_UMI_BCH_CTRL_STATUS =
+        writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN | REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC, &REG_UMI_BCH_CTRL_STATUS);
-            REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN |
-            REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC;
 }
 /* Resume during ECC read calculation after skipping bytes in OOB */
 static inline void nand_bcm_umi_bch_resume_read_ecc_calc(void)
 {
-        REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN;
+        writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN, &REG_UMI_BCH_CTRL_STATUS);
 }
 /* Poll read ECC calc to check when hardware completes */
@@ -139,7 +138,7 @@ static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void)
        do {
                /* wait for ECC to be valid */
-                regVal = REG_UMI_BCH_CTRL_STATUS;
+                regVal = readl(&REG_UMI_BCH_CTRL_STATUS);
        } while ((regVal & REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID) == 0);
        return regVal;
@@ -149,7 +148,7 @@ static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void)
 static inline void nand_bcm_umi_bch_poll_write_ecc_calc(void)
 {
        /* wait for ECC to be valid */
-        while ((REG_UMI_BCH_CTRL_STATUS & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID)
+        while ((readl(&REG_UMI_BCH_CTRL_STATUS) & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID)
               == 0)
                ;
 }
@@ -170,9 +169,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
        if (pageSize != NAND_DATA_ACCESS_SIZE) {
                /* skip BI */
 #if defined(__KERNEL__) && !defined(STANDALONE)
-                *oobp++ = REG_NAND_DATA8;
+                *oobp++ = readb(&REG_NAND_DATA8);
 #else
-                REG_NAND_DATA8;
+                readb(&REG_NAND_DATA8);
 #endif
                numToRead--;
        }
@@ -180,9 +179,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
        while (numToRead > numEccBytes) {
                /* skip free oob region */
 #if defined(__KERNEL__) && !defined(STANDALONE)
-                *oobp++ = REG_NAND_DATA8;
+                *oobp++ = readb(&REG_NAND_DATA8);
 #else
-                REG_NAND_DATA8;
+                readb(&REG_NAND_DATA8);
 #endif
                numToRead--;
        }
@@ -193,11 +192,11 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
                while (numToRead > 11) {
 #if defined(__KERNEL__) && !defined(STANDALONE)
-                        *oobp = REG_NAND_DATA8;
+                        *oobp = readb(&REG_NAND_DATA8);
                        eccCalc[eccPos++] = *oobp;
                        oobp++;
 #else
-                        eccCalc[eccPos++] = REG_NAND_DATA8;
+                        eccCalc[eccPos++] = readb(&REG_NAND_DATA8);
 #endif
                        numToRead--;
                }
@@ -207,9 +206,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
                if (numToRead == 11) {
                        /* read BI */
 #if defined(__KERNEL__) && !defined(STANDALONE)
-                        *oobp++ = REG_NAND_DATA8;
+                        *oobp++ = readb(&REG_NAND_DATA8);
 #else
-                        REG_NAND_DATA8;
+                        readb(&REG_NAND_DATA8);
 #endif
                        numToRead--;
                }
@@ -219,11 +218,11 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
        nand_bcm_umi_bch_resume_read_ecc_calc();
        while (numToRead) {
 #if defined(__KERNEL__) && !defined(STANDALONE)
-                *oobp = REG_NAND_DATA8;
+                *oobp = readb(&REG_NAND_DATA8);
                eccCalc[eccPos++] = *oobp;
                oobp++;
 #else
-                eccCalc[eccPos++] = REG_NAND_DATA8;
+                eccCalc[eccPos++] = readb(&REG_NAND_DATA8);
 #endif
                numToRead--;
        }
@@ -255,7 +254,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
        if (pageSize == NAND_DATA_ACCESS_SIZE) {
                /* Now fill in the ECC bytes */
                if (numEccBytes >= 13)
-                        eccVal = REG_UMI_BCH_WR_ECC_3;
+                        eccVal = readl(&REG_UMI_BCH_WR_ECC_3);
                /* Usually we skip CM in oob[0,1] */
                NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[0],
@@ -268,7 +267,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
                        eccVal & 0xff); /* ECC 12 */
                if (numEccBytes >= 9)
-                        eccVal = REG_UMI_BCH_WR_ECC_2;
+                        eccVal = readl(&REG_UMI_BCH_WR_ECC_2);
                NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[3],
                        (eccVal >> 24) & 0xff); /* ECC11 */
@@ -281,7 +280,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
                /* Now fill in the ECC bytes */
                if (numEccBytes >= 13)
-                        eccVal = REG_UMI_BCH_WR_ECC_3;
+                        eccVal = readl(&REG_UMI_BCH_WR_ECC_3);
                /* Usually skip CM in oob[1,2] */
                NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[1],
@@ -294,7 +293,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
                        eccVal & 0xff); /* ECC12 */
                if (numEccBytes >= 9)
-                        eccVal = REG_UMI_BCH_WR_ECC_2;
+                        eccVal = readl(&REG_UMI_BCH_WR_ECC_2);
                NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[4],
                        (eccVal >> 24) & 0xff); /* ECC11 */
@@ -309,7 +308,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
                eccVal & 0xff); /* ECC8 */
        if (numEccBytes >= 5)
-                eccVal = REG_UMI_BCH_WR_ECC_1;
+                eccVal = readl(&REG_UMI_BCH_WR_ECC_1);
        NAND_BCM_UMI_ECC_WRITE(numEccBytes, 8, &oobp[8],
                (eccVal >> 24) & 0xff); /* ECC7 */
@@ -321,7 +320,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
                eccVal & 0xff); /* ECC4 */
        if (numEccBytes >= 1)
-                eccVal = REG_UMI_BCH_WR_ECC_0;
+                eccVal = readl(&REG_UMI_BCH_WR_ECC_0);
        NAND_BCM_UMI_ECC_WRITE(numEccBytes, 4, &oobp[12],
                (eccVal >> 24) & 0xff); /* ECC3 */
diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c
index cc0f00d73d15..b446c9641212 100644
--- a/drivers/pinctrl/pinctrl-coh901.c
+++ b/drivers/pinctrl/pinctrl-coh901.c
@@ -1,11 +1,8 @@
 /*
 * U300 GPIO module.
 *
- * Copyright (C) 2007-2011 ST-Ericsson AB
+ * Copyright (C) 2007-2012 ST-Ericsson AB
 * License terms: GNU General Public License (GPL) version 2
- * This can driver either of the two basic GPIO cores
- * available in the U300 platforms:
- * COH 901 335   - Used in DB3150 (U300 1.0) and DB3200 (U330 1.0)
 * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
 * Author: Linus Walleij <linus.walleij@linaro.org>
 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
@@ -24,19 +21,22 @@
 #include <linux/slab.h>
 #include <linux/pinctrl/consumer.h>
 #include <linux/pinctrl/pinconf-generic.h>
-#include <mach/gpio-u300.h>
+#include <linux/platform_data/pinctrl-coh901.h>
 #include "pinctrl-coh901.h"
+#define U300_GPIO_PORT_STRIDE                           (0x30)
 /*
- * Register definitions for COH 901 335 variant
+ * Control Register 32bit (R/W)
+ * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
+ * gives the number of GPIO pins.
+ * bit 8-2  (mask 0x000001FC) contains the core version ID.
 */
-#define U300_335_PORT_STRIDE                            (0x1C)
+#define U300_GPIO_CR                                    (0x00)
-/* Port X Pin Data Register 32bit, this is both input and output (R/W) */
+#define U300_GPIO_CR_SYNC_SEL_ENABLE                    (0x00000002UL)
-#define U300_335_PXPDIR                                 (0x00)
+#define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE                 (0x00000001UL)
-#define U300_335_PXPDOR                                 (0x00)
+#define U300_GPIO_PXPDIR                                (0x04)
-/* Port X Pin Config Register 32bit (R/W) */
+#define U300_GPIO_PXPDOR                                (0x08)
-#define U300_335_PXPCR                                  (0x04)
+#define U300_GPIO_PXPCR                                 (0x0C)
-/* This register layout is the same in both blocks */
 #define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK              (0x0000FFFFUL)
 #define U300_GPIO_PXPCR_PIN_MODE_MASK                   (0x00000003UL)
 #define U300_GPIO_PXPCR_PIN_MODE_SHIFT                  (0x00000002UL)
@@ -44,53 +44,17 @@
 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL       (0x00000001UL)
 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN      (0x00000002UL)
 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE     (0x00000003UL)
-/* Port X Interrupt Event Register 32bit (R/W) */
+#define U300_GPIO_PXPER                                 (0x10)
-#define U300_335_PXIEV                                  (0x08)
+#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK        (0x000000FFUL)
-/* Port X Interrupt Enable Register 32bit (R/W) */
+#define U300_GPIO_PXPER_PULL_UP_DISABLE                 (0x00000001UL)
-#define U300_335_PXIEN                                  (0x0C)
+#define U300_GPIO_PXIEV                                 (0x14)
-/* Port X Interrupt Force Register 32bit (R/W) */
+#define U300_GPIO_PXIEN                                 (0x18)
-#define U300_335_PXIFR                                  (0x10)
+#define U300_GPIO_PXIFR                                 (0x1C)
-/* Port X Interrupt Config Register 32bit (R/W) */
+#define U300_GPIO_PXICR                                 (0x20)
-#define U300_335_PXICR                                  (0x14)
-/* This register layout is the same in both blocks */
 #define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK             (0x000000FFUL)
 #define U300_GPIO_PXICR_IRQ_CONFIG_MASK                 (0x00000001UL)
 #define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE         (0x00000000UL)
 #define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE          (0x00000001UL)
-/* Port X Pull-up Enable Register 32bit (R/W) */
-#define U300_335_PXPER                                  (0x18)
-/* This register layout is the same in both blocks */
-#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK        (0x000000FFUL)
-#define U300_GPIO_PXPER_PULL_UP_DISABLE                 (0x00000001UL)
-/* Control Register 32bit (R/W) */
-#define U300_335_CR                                     (0x54)
-#define U300_335_CR_BLOCK_CLOCK_ENABLE                  (0x00000001UL)
-/*
- * Register definitions for COH 901 571 / 3 variant
- */
-#define U300_571_PORT_STRIDE                            (0x30)
-/*
- * Control Register 32bit (R/W)
- * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
- * gives the number of GPIO pins.
- * bit 8-2  (mask 0x000001FC) contains the core version ID.
- */
-#define U300_571_CR                                     (0x00)
-#define U300_571_CR_SYNC_SEL_ENABLE                     (0x00000002UL)
-#define U300_571_CR_BLOCK_CLKRQ_ENABLE                  (0x00000001UL)
-/*
- * These registers have the same layout and function as the corresponding
- * COH 901 335 registers, just at different offset.
- */
-#define U300_571_PXPDIR                                 (0x04)
-#define U300_571_PXPDOR                                 (0x08)
-#define U300_571_PXPCR                                  (0x0C)
-#define U300_571_PXPER                                  (0x10)
-#define U300_571_PXIEV                                  (0x14)
-#define U300_571_PXIEN                                  (0x18)
-#define U300_571_PXIFR                                  (0x1C)
-#define U300_571_PXICR                                  (0x20)
 /* 8 bits per port, no version has more than 7 ports */
 #define U300_GPIO_PINS_PER_PORT 8
@@ -149,8 +113,6 @@ struct u300_gpio_confdata {
 /* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */
 #define BS335_GPIO_NUM_PORTS 7
-/* BS365 has five ports of 8 bits each = GPIO pins 0..39 */
-#define BS365_GPIO_NUM_PORTS 5
 #define U300_FLOATING_INPUT { \
        .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \
@@ -172,7 +134,6 @@ struct u300_gpio_confdata {
        .outval = 1, \
 }
 /* Initial configuration */
 static const struct __initconst u300_gpio_confdata
 bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
@@ -255,66 +216,6 @@ bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
        }
 };
-static const struct __initconst u300_gpio_confdata
-bs365_gpio_config[BS365_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
-        /* Port 0, pins 0-7 */
-        {
-                U300_FLOATING_INPUT,
-                U300_OUTPUT_LOW,
-                U300_FLOATING_INPUT,
-                U300_OUTPUT_LOW,
-                U300_OUTPUT_LOW,
-                U300_OUTPUT_LOW,
-                U300_PULL_UP_INPUT,
-                U300_FLOATING_INPUT,
-        },
-        /* Port 1, pins 0-7 */
-        {
-                U300_OUTPUT_LOW,
-                U300_FLOATING_INPUT,
-                U300_OUTPUT_LOW,
-                U300_FLOATING_INPUT,
-                U300_FLOATING_INPUT,
-                U300_OUTPUT_HIGH,
-                U300_OUTPUT_LOW,
-                U300_OUTPUT_LOW,
-        },
-        /* Port 2, pins 0-7 */
-        {
-                U300_FLOATING_INPUT,
-                U300_PULL_UP_INPUT,
-                U300_OUTPUT_LOW,
-                U300_OUTPUT_LOW,
-                U300_PULL_UP_INPUT,
-                U300_PULL_UP_INPUT,
-                U300_PULL_UP_INPUT,
-                U300_PULL_UP_INPUT,
-        },
-        /* Port 3, pins 0-7 */
-        {
-                U300_PULL_UP_INPUT,
-                U300_PULL_UP_INPUT,
-                U300_PULL_UP_INPUT,
-                U300_PULL_UP_INPUT,
-                U300_PULL_UP_INPUT,
-                U300_PULL_UP_INPUT,
-                U300_PULL_UP_INPUT,
-                U300_PULL_UP_INPUT,
-        },
-        /* Port 4, pins 0-7 */
-        {
-                U300_PULL_UP_INPUT,
-                U300_PULL_UP_INPUT,
-                U300_PULL_UP_INPUT,
-                U300_PULL_UP_INPUT,
-                /* These 4 pins doesn't exist on DB3210 */
-                U300_OUTPUT_LOW,
-                U300_OUTPUT_LOW,
-                U300_OUTPUT_LOW,
-                U300_OUTPUT_LOW,
-        }
-};
 /**
 * to_u300_gpio() - get the pointer to u300_gpio
 * @chip: the gpio chip member of the structure u300_gpio
@@ -716,13 +617,7 @@ static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio,
                        const struct u300_gpio_confdata *conf;
                        int offset = (i*8) + j;
-                        if (plat->variant == U300_GPIO_COH901571_3_BS335)
+                        conf = &bs335_gpio_config[i][j];
-                                conf = &bs335_gpio_config[i][j];
-                        else if (plat->variant == U300_GPIO_COH901571_3_BS365)
-                                conf = &bs365_gpio_config[i][j];
-                        else
-                                break;
                        u300_gpio_init_pin(gpio, offset, conf);
                }
        }
@@ -796,50 +691,27 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
                goto err_no_ioremap;
        }
-        if (plat->variant == U300_GPIO_COH901335) {
+        dev_info(gpio->dev,
-                dev_info(gpio->dev,
+                 "initializing GPIO Controller COH 901 571/3\n");
-                         "initializing GPIO Controller COH 901 335\n");
+        gpio->stride = U300_GPIO_PORT_STRIDE;
-                gpio->stride = U300_335_PORT_STRIDE;
+        gpio->pcr = U300_GPIO_PXPCR;
-                gpio->pcr = U300_335_PXPCR;
+        gpio->dor = U300_GPIO_PXPDOR;
-                gpio->dor = U300_335_PXPDOR;
+        gpio->dir = U300_GPIO_PXPDIR;
-                gpio->dir = U300_335_PXPDIR;
+        gpio->per = U300_GPIO_PXPER;
-                gpio->per = U300_335_PXPER;
+        gpio->icr = U300_GPIO_PXICR;
-                gpio->icr = U300_335_PXICR;
+        gpio->ien = U300_GPIO_PXIEN;
-                gpio->ien = U300_335_PXIEN;
+        gpio->iev = U300_GPIO_PXIEV;
-                gpio->iev = U300_335_PXIEV;
+        ifr = U300_GPIO_PXIFR;
-                ifr = U300_335_PXIFR;
+        val = readl(gpio->base + U300_GPIO_CR);
-                /* Turn on the GPIO block */
+        dev_info(gpio->dev, "COH901571/3 block version: %d, " \
-                writel(U300_335_CR_BLOCK_CLOCK_ENABLE,
+                 "number of cores: %d totalling %d pins\n",
-                       gpio->base + U300_335_CR);
+                 ((val & 0x000001FC) >> 2),
-        } else if (plat->variant == U300_GPIO_COH901571_3_BS335 ||
+                 ((val & 0x0000FE00) >> 9),
-                   plat->variant == U300_GPIO_COH901571_3_BS365) {
+                 ((val & 0x0000FE00) >> 9) * 8);
-                dev_info(gpio->dev,
+        writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE,
-                         "initializing GPIO Controller COH 901 571/3\n");
+               gpio->base + U300_GPIO_CR);
-                gpio->stride = U300_571_PORT_STRIDE;
+        u300_gpio_init_coh901571(gpio, plat);
-                gpio->pcr = U300_571_PXPCR;
-                gpio->dor = U300_571_PXPDOR;
-                gpio->dir = U300_571_PXPDIR;
-                gpio->per = U300_571_PXPER;
-                gpio->icr = U300_571_PXICR;
-                gpio->ien = U300_571_PXIEN;
-                gpio->iev = U300_571_PXIEV;
-                ifr = U300_571_PXIFR;
-                val = readl(gpio->base + U300_571_CR);
-                dev_info(gpio->dev, "COH901571/3 block version: %d, " \
-                         "number of cores: %d totalling %d pins\n",
-                         ((val & 0x000001FC) >> 2),
-                         ((val & 0x0000FE00) >> 9),
-                         ((val & 0x0000FE00) >> 9) * 8);
-                writel(U300_571_CR_BLOCK_CLKRQ_ENABLE,
-                       gpio->base + U300_571_CR);
-                u300_gpio_init_coh901571(gpio, plat);
-        } else {
-                dev_err(gpio->dev, "unknown block variant\n");
-                err = -ENODEV;
-                goto err_unknown_variant;
-        }
        /* Add each port with its IRQ separately */
        INIT_LIST_HEAD(&gpio->port_list);
@@ -906,7 +778,6 @@ err_no_pinctrl:
 err_no_chip:
 err_no_port:
        u300_gpio_free_ports(gpio);
-err_unknown_variant:
        iounmap(gpio->base);
 err_no_ioremap:
        release_mem_region(gpio->memres->start, resource_size(gpio->memres));
@@ -923,16 +794,11 @@ err_no_clk:
 static int __exit u300_gpio_remove(struct platform_device *pdev)
 {
-        struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev);
        struct u300_gpio *gpio = platform_get_drvdata(pdev);
        int err;
        /* Turn off the GPIO block */
-        if (plat->variant == U300_GPIO_COH901335)
+        writel(0x00000000U, gpio->base + U300_GPIO_CR);
-                writel(0x00000000U, gpio->base + U300_335_CR);
-        if (plat->variant == U300_GPIO_COH901571_3_BS335 ||
-            plat->variant == U300_GPIO_COH901571_3_BS365)
-                writel(0x00000000U, gpio->base + U300_571_CR);
        err = gpiochip_remove(&gpio->chip);
        if (err < 0) {
diff --git a/arch/arm/mach-u300/include/mach/gpio-u300.h b/include/linux/platform_data/pinctrl-coh901.h
index e81400c1753a..30dea251b835 100644
--- a/arch/arm/mach-u300/include/mach/gpio-u300.h
+++ b/include/linux/platform_data/pinctrl-coh901.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2007-2011 ST-Ericsson AB
+ * Copyright (C) 2007-2012 ST-Ericsson AB
 * License terms: GNU General Public License (GPL) version 2
 * GPIO block resgister definitions and inline macros for
 * U300 GPIO COH 901 335 or COH 901 571/3
@@ -10,24 +10,13 @@
 #define __MACH_U300_GPIO_U300_H
 /**
- * enum u300_gpio_variant - the type of U300 GPIO employed
- */
-enum u300_gpio_variant {
-        U300_GPIO_COH901335,
-        U300_GPIO_COH901571_3_BS335,
-        U300_GPIO_COH901571_3_BS365,
-};
-/**
 * struct u300_gpio_platform - U300 GPIO platform data
- * @variant: IP block variant
 * @ports: number of GPIO block ports
 * @gpio_base: first GPIO number for this block (use a free range)
 * @gpio_irq_base: first GPIO IRQ number for this block (use a free range)
 * @pinctrl_device: pin control device to spawn as child
 */
 struct u300_gpio_platform {
-        enum u300_gpio_variant variant;
        u8 ports;
        int gpio_base;
        int gpio_irq_base;