diff options
446 files changed, 29480 insertions, 7223 deletions
diff --git a/Documentation/arm/Marvell/README b/Documentation/arm/Marvell/README index 5a930c1528ad..963ec445e15a 100644 --- a/Documentation/arm/Marvell/README +++ b/Documentation/arm/Marvell/README | |||
| @@ -83,14 +83,24 @@ EBU Armada family | |||
| 83 | 88F6710 | 83 | 88F6710 |
| 84 | 88F6707 | 84 | 88F6707 |
| 85 | 88F6W11 | 85 | 88F6W11 |
| 86 | Product Brief: http://www.marvell.com/embedded-processors/armada-300/assets/Marvell_ARMADA_370_SoC.pdf | ||
| 87 | |||
| 88 | Armada 375 Flavors: | ||
| 89 | 88F6720 | ||
| 90 | Product Brief: http://www.marvell.com/embedded-processors/armada-300/assets/ARMADA_375_SoC-01_product_brief.pdf | ||
| 91 | |||
| 92 | Armada 380/385 Flavors: | ||
| 93 | 88F6810 | ||
| 94 | 88F6820 | ||
| 95 | 88F6828 | ||
| 86 | 96 | ||
| 87 | Armada XP Flavors: | 97 | Armada XP Flavors: |
| 88 | MV78230 | 98 | MV78230 |
| 89 | MV78260 | 99 | MV78260 |
| 90 | MV78460 | 100 | MV78460 |
| 91 | NOTE: not to be confused with the non-SMP 78xx0 SoCs | 101 | NOTE: not to be confused with the non-SMP 78xx0 SoCs |
| 102 | Product Brief: http://www.marvell.com/embedded-processors/armada-xp/assets/Marvell-ArmadaXP-SoC-product%20brief.pdf | ||
| 92 | 103 | ||
| 93 | Product Brief: http://www.marvell.com/embedded-processors/armada-xp/assets/Marvell-ArmadaXP-SoC-product%20brief.pdf | ||
| 94 | No public datasheet available. | 104 | No public datasheet available. |
| 95 | 105 | ||
| 96 | Core: Sheeva ARMv7 compatible | 106 | Core: Sheeva ARMv7 compatible |
diff --git a/Documentation/devicetree/bindings/arm/armada-375.txt b/Documentation/devicetree/bindings/arm/armada-375.txt new file mode 100644 index 000000000000..867d0b80cb8f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/armada-375.txt | |||
| @@ -0,0 +1,9 @@ | |||
| 1 | Marvell Armada 375 Platforms Device Tree Bindings | ||
| 2 | ------------------------------------------------- | ||
| 3 | |||
| 4 | Boards with a SoC of the Marvell Armada 375 family shall have the | ||
| 5 | following property: | ||
| 6 | |||
| 7 | Required root node property: | ||
| 8 | |||
| 9 | compatible: must contain "marvell,armada375" | ||
diff --git a/Documentation/devicetree/bindings/arm/armada-38x.txt b/Documentation/devicetree/bindings/arm/armada-38x.txt new file mode 100644 index 000000000000..11f2330a6554 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/armada-38x.txt | |||
| @@ -0,0 +1,10 @@ | |||
| 1 | Marvell Armada 38x Platforms Device Tree Bindings | ||
| 2 | ------------------------------------------------- | ||
| 3 | |||
| 4 | Boards with a SoC of the Marvell Armada 38x family shall have the | ||
| 5 | following property: | ||
| 6 | |||
| 7 | Required root node property: | ||
| 8 | |||
| 9 | - compatible: must contain either "marvell,armada380" or | ||
| 10 | "marvell,armada385" depending on the variant of the SoC being used. | ||
diff --git a/Documentation/devicetree/bindings/arm/keystone/keystone.txt b/Documentation/devicetree/bindings/arm/keystone/keystone.txt index 63c0e6ae5cf7..ad16e7a58893 100644 --- a/Documentation/devicetree/bindings/arm/keystone/keystone.txt +++ b/Documentation/devicetree/bindings/arm/keystone/keystone.txt | |||
| @@ -8,3 +8,13 @@ Required properties: | |||
| 8 | - compatible: All TI specific devices present in Keystone SOC should be in | 8 | - compatible: All TI specific devices present in Keystone SOC should be in |
| 9 | the form "ti,keystone-*". Generic devices like gic, arch_timers, ns16550 | 9 | the form "ti,keystone-*". Generic devices like gic, arch_timers, ns16550 |
| 10 | type UART should use the specified compatible for those devices. | 10 | type UART should use the specified compatible for those devices. |
| 11 | |||
| 12 | Boards: | ||
| 13 | - Keystone 2 Hawking/Kepler EVM | ||
| 14 | compatible = "ti,k2hk-evm" | ||
| 15 | |||
| 16 | - Keystone 2 Lamarr EVM | ||
| 17 | compatible = "ti,k2l-evm" | ||
| 18 | |||
| 19 | - Keystone 2 Edison EVM | ||
| 20 | compatible = "ti,k2e-evm" | ||
diff --git a/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt b/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt new file mode 100644 index 000000000000..0d244b999d10 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt | |||
| @@ -0,0 +1,16 @@ | |||
| 1 | * Marvell Feroceon Cache | ||
| 2 | |||
| 3 | Required properties: | ||
| 4 | - compatible : Should be either "marvell,feroceon-cache" or | ||
| 5 | "marvell,kirkwood-cache". | ||
| 6 | |||
| 7 | Optional properties: | ||
| 8 | - reg : Address of the L2 cache control register. Mandatory for | ||
| 9 | "marvell,kirkwood-cache", not used by "marvell,feroceon-cache" | ||
| 10 | |||
| 11 | |||
| 12 | Example: | ||
| 13 | l2: l2-cache@20128 { | ||
| 14 | compatible = "marvell,kirkwood-cache"; | ||
| 15 | reg = <0x20128 0x4>; | ||
| 16 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt b/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt index 081c6a786c8a..d24ab2ebf8a7 100644 --- a/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt +++ b/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt | |||
| @@ -1,12 +1,13 @@ | |||
| 1 | MVEBU System Controller | 1 | MVEBU System Controller |
| 2 | ----------------------- | 2 | ----------------------- |
| 3 | MVEBU (Marvell SOCs: Armada 370/XP, Dove, mv78xx0, Kirkwood, Orion5x) | 3 | MVEBU (Marvell SOCs: Armada 370/375/XP, Dove, mv78xx0, Kirkwood, Orion5x) |
| 4 | 4 | ||
| 5 | Required properties: | 5 | Required properties: |
| 6 | 6 | ||
| 7 | - compatible: one of: | 7 | - compatible: one of: |
| 8 | - "marvell,orion-system-controller" | 8 | - "marvell,orion-system-controller" |
| 9 | - "marvell,armada-370-xp-system-controller" | 9 | - "marvell,armada-370-xp-system-controller" |
| 10 | - "marvell,armada-375-system-controller" | ||
| 10 | - reg: Should contain system controller registers location and length. | 11 | - reg: Should contain system controller registers location and length. |
| 11 | 12 | ||
| 12 | Example: | 13 | Example: |
diff --git a/Documentation/devicetree/bindings/arm/omap/dmm.txt b/Documentation/devicetree/bindings/arm/omap/dmm.txt new file mode 100644 index 000000000000..8bd6d0a238a8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/dmm.txt | |||
| @@ -0,0 +1,22 @@ | |||
| 1 | OMAP Dynamic Memory Manager (DMM) bindings | ||
| 2 | |||
| 3 | The dynamic memory manager (DMM) is a module located immediately in front of the | ||
| 4 | SDRAM controllers (called EMIFs on OMAP). DMM manages various aspects of memory | ||
| 5 | accesses such as priority generation amongst initiators, configuration of SDRAM | ||
| 6 | interleaving, optimizing transfer of 2D block objects, and provide MMU-like page | ||
| 7 | translation for initiators which need contiguous dma bus addresses. | ||
| 8 | |||
| 9 | Required properties: | ||
| 10 | - compatible: Should contain "ti,omap4-dmm" for OMAP4 family | ||
| 11 | Should contain "ti,omap5-dmm" for OMAP5 and DRA7x family | ||
| 12 | - reg: Contains DMM register address range (base address and length) | ||
| 13 | - interrupts: Should contain an interrupt-specifier for DMM_IRQ. | ||
| 14 | - ti,hwmods: Name of the hwmod associated to DMM, which is typically "dmm" | ||
| 15 | |||
| 16 | Example: | ||
| 17 | |||
| 18 | dmm@4e000000 { | ||
| 19 | compatible = "ti,omap4-dmm"; | ||
| 20 | reg = <0x4e000000 0x800>; | ||
| 21 | ti,hwmods = "dmm"; | ||
| 22 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt index af9b4a0d902b..36ede19a1630 100644 --- a/Documentation/devicetree/bindings/arm/omap/omap.txt +++ b/Documentation/devicetree/bindings/arm/omap/omap.txt | |||
| @@ -99,6 +99,9 @@ Boards: | |||
| 99 | - OMAP4 PandaBoard : Low cost community board | 99 | - OMAP4 PandaBoard : Low cost community board |
| 100 | compatible = "ti,omap4-panda", "ti,omap4430" | 100 | compatible = "ti,omap4-panda", "ti,omap4430" |
| 101 | 101 | ||
| 102 | - OMAP4 DuoVero with Parlor : Commercial expansion board with daughter board | ||
| 103 | compatible = "gumstix,omap4-duovero-parlor", "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4"; | ||
| 104 | |||
| 102 | - OMAP3 EVM : Software Development Board for OMAP35x, AM/DM37x | 105 | - OMAP3 EVM : Software Development Board for OMAP35x, AM/DM37x |
| 103 | compatible = "ti,omap3-evm", "ti,omap3" | 106 | compatible = "ti,omap3-evm", "ti,omap3" |
| 104 | 107 | ||
| @@ -114,5 +117,8 @@ Boards: | |||
| 114 | - AM43x EPOS EVM | 117 | - AM43x EPOS EVM |
| 115 | compatible = "ti,am43x-epos-evm", "ti,am4372", "ti,am43" | 118 | compatible = "ti,am43x-epos-evm", "ti,am4372", "ti,am43" |
| 116 | 119 | ||
| 120 | - AM437x GP EVM | ||
| 121 | compatible = "ti,am437x-gp-evm", "ti,am4372", "ti,am43" | ||
| 122 | |||
| 117 | - DRA7 EVM: Software Developement Board for DRA7XX | 123 | - DRA7 EVM: Software Developement Board for DRA7XX |
| 118 | compatible = "ti,dra7-evm", "ti,dra7" | 124 | compatible = "ti,dra7-evm", "ti,dra7" |
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt b/Documentation/devicetree/bindings/arm/samsung/pmu.txt new file mode 100644 index 000000000000..f1f155255f28 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt | |||
| @@ -0,0 +1,15 @@ | |||
| 1 | SAMSUNG Exynos SoC series PMU Registers | ||
| 2 | |||
| 3 | Properties: | ||
| 4 | - compatible : should contain two values. First value must be one from following list: | ||
| 5 | - "samsung,exynos5250-pmu" - for Exynos5250 SoC, | ||
| 6 | - "samsung,exynos5420-pmu" - for Exynos5420 SoC. | ||
| 7 | second value must be always "syscon". | ||
| 8 | |||
| 9 | - reg : offset and length of the register set. | ||
| 10 | |||
| 11 | Example : | ||
| 12 | pmu_system_controller: system-controller@10040000 { | ||
| 13 | compatible = "samsung,exynos5250-pmu", "syscon"; | ||
| 14 | reg = <0x10040000 0x5000>; | ||
| 15 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt index a2ac2d9ac71a..f5a5b19ed3b2 100644 --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt | |||
| @@ -15,259 +15,12 @@ Required Properties: | |||
| 15 | 15 | ||
| 16 | - #clock-cells: should be 1. | 16 | - #clock-cells: should be 1. |
| 17 | 17 | ||
| 18 | The following is the list of clocks generated by the controller. Each clock is | 18 | Each clock is assigned an identifier and client nodes can use this identifier |
| 19 | assigned an identifier and client nodes use this identifier to specify the | 19 | to specify the clock which they consume. |
| 20 | clock which they consume. Some of the clocks are available only on a particular | ||
| 21 | Exynos4 SoC and this is specified where applicable. | ||
| 22 | |||
| 23 | |||
| 24 | [Core Clocks] | ||
| 25 | |||
| 26 | Clock ID SoC (if specific) | ||
| 27 | ----------------------------------------------- | ||
| 28 | |||
| 29 | xxti 1 | ||
| 30 | xusbxti 2 | ||
| 31 | fin_pll 3 | ||
| 32 | fout_apll 4 | ||
| 33 | fout_mpll 5 | ||
| 34 | fout_epll 6 | ||
| 35 | fout_vpll 7 | ||
| 36 | sclk_apll 8 | ||
| 37 | sclk_mpll 9 | ||
| 38 | sclk_epll 10 | ||
| 39 | sclk_vpll 11 | ||
| 40 | arm_clk 12 | ||
| 41 | aclk200 13 | ||
| 42 | aclk100 14 | ||
| 43 | aclk160 15 | ||
| 44 | aclk133 16 | ||
| 45 | mout_mpll_user_t 17 Exynos4x12 | ||
| 46 | mout_mpll_user_c 18 Exynos4x12 | ||
| 47 | mout_core 19 | ||
| 48 | mout_apll 20 | ||
| 49 | |||
| 50 | |||
| 51 | [Clock Gate for Special Clocks] | ||
| 52 | |||
| 53 | Clock ID SoC (if specific) | ||
| 54 | ----------------------------------------------- | ||
| 55 | |||
| 56 | sclk_fimc0 128 | ||
| 57 | sclk_fimc1 129 | ||
| 58 | sclk_fimc2 130 | ||
| 59 | sclk_fimc3 131 | ||
| 60 | sclk_cam0 132 | ||
| 61 | sclk_cam1 133 | ||
| 62 | sclk_csis0 134 | ||
| 63 | sclk_csis1 135 | ||
| 64 | sclk_hdmi 136 | ||
| 65 | sclk_mixer 137 | ||
| 66 | sclk_dac 138 | ||
| 67 | sclk_pixel 139 | ||
| 68 | sclk_fimd0 140 | ||
| 69 | sclk_mdnie0 141 Exynos4412 | ||
| 70 | sclk_mdnie_pwm0 12 142 Exynos4412 | ||
| 71 | sclk_mipi0 143 | ||
| 72 | sclk_audio0 144 | ||
| 73 | sclk_mmc0 145 | ||
| 74 | sclk_mmc1 146 | ||
| 75 | sclk_mmc2 147 | ||
| 76 | sclk_mmc3 148 | ||
| 77 | sclk_mmc4 149 | ||
| 78 | sclk_sata 150 Exynos4210 | ||
| 79 | sclk_uart0 151 | ||
| 80 | sclk_uart1 152 | ||
| 81 | sclk_uart2 153 | ||
| 82 | sclk_uart3 154 | ||
| 83 | sclk_uart4 155 | ||
| 84 | sclk_audio1 156 | ||
| 85 | sclk_audio2 157 | ||
| 86 | sclk_spdif 158 | ||
| 87 | sclk_spi0 159 | ||
| 88 | sclk_spi1 160 | ||
| 89 | sclk_spi2 161 | ||
| 90 | sclk_slimbus 162 | ||
| 91 | sclk_fimd1 163 Exynos4210 | ||
| 92 | sclk_mipi1 164 Exynos4210 | ||
| 93 | sclk_pcm1 165 | ||
| 94 | sclk_pcm2 166 | ||
| 95 | sclk_i2s1 167 | ||
| 96 | sclk_i2s2 168 | ||
| 97 | sclk_mipihsi 169 Exynos4412 | ||
| 98 | sclk_mfc 170 | ||
| 99 | sclk_pcm0 171 | ||
| 100 | sclk_g3d 172 | ||
| 101 | sclk_pwm_isp 173 Exynos4x12 | ||
| 102 | sclk_spi0_isp 174 Exynos4x12 | ||
| 103 | sclk_spi1_isp 175 Exynos4x12 | ||
| 104 | sclk_uart_isp 176 Exynos4x12 | ||
| 105 | sclk_fimg2d 177 | ||
| 106 | |||
| 107 | [Peripheral Clock Gates] | ||
| 108 | |||
| 109 | Clock ID SoC (if specific) | ||
| 110 | ----------------------------------------------- | ||
| 111 | |||
| 112 | fimc0 256 | ||
| 113 | fimc1 257 | ||
| 114 | fimc2 258 | ||
| 115 | fimc3 259 | ||
| 116 | csis0 260 | ||
| 117 | csis1 261 | ||
| 118 | jpeg 262 | ||
| 119 | smmu_fimc0 263 | ||
| 120 | smmu_fimc1 264 | ||
| 121 | smmu_fimc2 265 | ||
| 122 | smmu_fimc3 266 | ||
| 123 | smmu_jpeg 267 | ||
| 124 | vp 268 | ||
| 125 | mixer 269 | ||
| 126 | tvenc 270 Exynos4210 | ||
| 127 | hdmi 271 | ||
| 128 | smmu_tv 272 | ||
| 129 | mfc 273 | ||
| 130 | smmu_mfcl 274 | ||
| 131 | smmu_mfcr 275 | ||
| 132 | g3d 276 | ||
| 133 | g2d 277 | ||
| 134 | rotator 278 Exynos4210 | ||
| 135 | mdma 279 Exynos4210 | ||
| 136 | smmu_g2d 280 Exynos4210 | ||
| 137 | smmu_rotator 281 Exynos4210 | ||
| 138 | smmu_mdma 282 Exynos4210 | ||
| 139 | fimd0 283 | ||
| 140 | mie0 284 | ||
| 141 | mdnie0 285 Exynos4412 | ||
| 142 | dsim0 286 | ||
| 143 | smmu_fimd0 287 | ||
| 144 | fimd1 288 Exynos4210 | ||
| 145 | mie1 289 Exynos4210 | ||
| 146 | dsim1 290 Exynos4210 | ||
| 147 | smmu_fimd1 291 Exynos4210 | ||
| 148 | pdma0 292 | ||
| 149 | pdma1 293 | ||
| 150 | pcie_phy 294 | ||
| 151 | sata_phy 295 Exynos4210 | ||
| 152 | tsi 296 | ||
| 153 | sdmmc0 297 | ||
| 154 | sdmmc1 298 | ||
| 155 | sdmmc2 299 | ||
| 156 | sdmmc3 300 | ||
| 157 | sdmmc4 301 | ||
| 158 | sata 302 Exynos4210 | ||
| 159 | sromc 303 | ||
| 160 | usb_host 304 | ||
| 161 | usb_device 305 | ||
| 162 | pcie 306 | ||
| 163 | onenand 307 | ||
| 164 | nfcon 308 | ||
| 165 | smmu_pcie 309 | ||
| 166 | gps 310 | ||
| 167 | smmu_gps 311 | ||
| 168 | uart0 312 | ||
| 169 | uart1 313 | ||
| 170 | uart2 314 | ||
| 171 | uart3 315 | ||
| 172 | uart4 316 | ||
| 173 | i2c0 317 | ||
| 174 | i2c1 318 | ||
| 175 | i2c2 319 | ||
| 176 | i2c3 320 | ||
| 177 | i2c4 321 | ||
| 178 | i2c5 322 | ||
| 179 | i2c6 323 | ||
| 180 | i2c7 324 | ||
| 181 | i2c_hdmi 325 | ||
| 182 | tsadc 326 | ||
| 183 | spi0 327 | ||
| 184 | spi1 328 | ||
| 185 | spi2 329 | ||
| 186 | i2s1 330 | ||
| 187 | i2s2 331 | ||
| 188 | pcm0 332 | ||
| 189 | i2s0 333 | ||
| 190 | pcm1 334 | ||
| 191 | pcm2 335 | ||
| 192 | pwm 336 | ||
| 193 | slimbus 337 | ||
| 194 | spdif 338 | ||
| 195 | ac97 339 | ||
| 196 | modemif 340 | ||
| 197 | chipid 341 | ||
| 198 | sysreg 342 | ||
| 199 | hdmi_cec 343 | ||
| 200 | mct 344 | ||
| 201 | wdt 345 | ||
| 202 | rtc 346 | ||
| 203 | keyif 347 | ||
| 204 | audss 348 | ||
| 205 | mipi_hsi 349 Exynos4210 | ||
| 206 | mdma2 350 Exynos4210 | ||
| 207 | pixelasyncm0 351 | ||
| 208 | pixelasyncm1 352 | ||
| 209 | fimc_lite0 353 Exynos4x12 | ||
| 210 | fimc_lite1 354 Exynos4x12 | ||
| 211 | ppmuispx 355 Exynos4x12 | ||
| 212 | ppmuispmx 356 Exynos4x12 | ||
| 213 | fimc_isp 357 Exynos4x12 | ||
| 214 | fimc_drc 358 Exynos4x12 | ||
| 215 | fimc_fd 359 Exynos4x12 | ||
| 216 | mcuisp 360 Exynos4x12 | ||
| 217 | gicisp 361 Exynos4x12 | ||
| 218 | smmu_isp 362 Exynos4x12 | ||
| 219 | smmu_drc 363 Exynos4x12 | ||
| 220 | smmu_fd 364 Exynos4x12 | ||
| 221 | smmu_lite0 365 Exynos4x12 | ||
| 222 | smmu_lite1 366 Exynos4x12 | ||
| 223 | mcuctl_isp 367 Exynos4x12 | ||
| 224 | mpwm_isp 368 Exynos4x12 | ||
| 225 | i2c0_isp 369 Exynos4x12 | ||
| 226 | i2c1_isp 370 Exynos4x12 | ||
| 227 | mtcadc_isp 371 Exynos4x12 | ||
| 228 | pwm_isp 372 Exynos4x12 | ||
| 229 | wdt_isp 373 Exynos4x12 | ||
| 230 | uart_isp 374 Exynos4x12 | ||
| 231 | asyncaxim 375 Exynos4x12 | ||
| 232 | smmu_ispcx 376 Exynos4x12 | ||
| 233 | spi0_isp 377 Exynos4x12 | ||
| 234 | spi1_isp 378 Exynos4x12 | ||
| 235 | pwm_isp_sclk 379 Exynos4x12 | ||
| 236 | spi0_isp_sclk 380 Exynos4x12 | ||
| 237 | spi1_isp_sclk 381 Exynos4x12 | ||
| 238 | uart_isp_sclk 382 Exynos4x12 | ||
| 239 | tmu_apbif 383 | ||
| 240 | |||
| 241 | [Mux Clocks] | ||
| 242 | |||
| 243 | Clock ID SoC (if specific) | ||
| 244 | ----------------------------------------------- | ||
| 245 | |||
| 246 | mout_fimc0 384 | ||
| 247 | mout_fimc1 385 | ||
| 248 | mout_fimc2 386 | ||
| 249 | mout_fimc3 387 | ||
| 250 | mout_cam0 388 | ||
| 251 | mout_cam1 389 | ||
| 252 | mout_csis0 390 | ||
| 253 | mout_csis1 391 | ||
| 254 | mout_g3d0 392 | ||
| 255 | mout_g3d1 393 | ||
| 256 | mout_g3d 394 | ||
| 257 | aclk400_mcuisp 395 Exynos4x12 | ||
| 258 | |||
| 259 | [Div Clocks] | ||
| 260 | |||
| 261 | Clock ID SoC (if specific) | ||
| 262 | ----------------------------------------------- | ||
| 263 | |||
| 264 | div_isp0 450 Exynos4x12 | ||
| 265 | div_isp1 451 Exynos4x12 | ||
| 266 | div_mcuisp0 452 Exynos4x12 | ||
| 267 | div_mcuisp1 453 Exynos4x12 | ||
| 268 | div_aclk200 454 Exynos4x12 | ||
| 269 | div_aclk400_mcuisp 455 Exynos4x12 | ||
| 270 | 20 | ||
| 21 | All available clocks are defined as preprocessor macros in | ||
| 22 | dt-bindings/clock/exynos4.h header and can be used in device | ||
| 23 | tree sources. | ||
| 271 | 24 | ||
| 272 | Example 1: An example of a clock controller node is listed below. | 25 | Example 1: An example of a clock controller node is listed below. |
| 273 | 26 | ||
| @@ -285,6 +38,6 @@ Example 2: UART controller node that consumes the clock generated by the clock | |||
| 285 | compatible = "samsung,exynos4210-uart"; | 38 | compatible = "samsung,exynos4210-uart"; |
| 286 | reg = <0x13820000 0x100>; | 39 | reg = <0x13820000 0x100>; |
| 287 | interrupts = <0 54 0>; | 40 | interrupts = <0 54 0>; |
| 288 | clocks = <&clock 314>, <&clock 153>; | 41 | clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; |
| 289 | clock-names = "uart", "clk_uart_baud0"; | 42 | clock-names = "uart", "clk_uart_baud0"; |
| 290 | }; | 43 | }; |
diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt index 72ce617dea82..536eacd1063f 100644 --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt | |||
| @@ -13,163 +13,12 @@ Required Properties: | |||
| 13 | 13 | ||
| 14 | - #clock-cells: should be 1. | 14 | - #clock-cells: should be 1. |
| 15 | 15 | ||
| 16 | The following is the list of clocks generated by the controller. Each clock is | 16 | Each clock is assigned an identifier and client nodes can use this identifier |
| 17 | assigned an identifier and client nodes use this identifier to specify the | 17 | to specify the clock which they consume. |
| 18 | clock which they consume. | ||
| 19 | |||
| 20 | |||
| 21 | [Core Clocks] | ||
| 22 | |||
| 23 | Clock ID | ||
| 24 | ---------------------------- | ||
| 25 | |||
| 26 | fin_pll 1 | ||
| 27 | |||
| 28 | [Clock Gate for Special Clocks] | ||
| 29 | |||
| 30 | Clock ID | ||
| 31 | ---------------------------- | ||
| 32 | |||
| 33 | sclk_cam_bayer 128 | ||
| 34 | sclk_cam0 129 | ||
| 35 | sclk_cam1 130 | ||
| 36 | sclk_gscl_wa 131 | ||
| 37 | sclk_gscl_wb 132 | ||
| 38 | sclk_fimd1 133 | ||
| 39 | sclk_mipi1 134 | ||
| 40 | sclk_dp 135 | ||
| 41 | sclk_hdmi 136 | ||
| 42 | sclk_pixel 137 | ||
| 43 | sclk_audio0 138 | ||
| 44 | sclk_mmc0 139 | ||
| 45 | sclk_mmc1 140 | ||
| 46 | sclk_mmc2 141 | ||
| 47 | sclk_mmc3 142 | ||
| 48 | sclk_sata 143 | ||
| 49 | sclk_usb3 144 | ||
| 50 | sclk_jpeg 145 | ||
| 51 | sclk_uart0 146 | ||
| 52 | sclk_uart1 147 | ||
| 53 | sclk_uart2 148 | ||
| 54 | sclk_uart3 149 | ||
| 55 | sclk_pwm 150 | ||
| 56 | sclk_audio1 151 | ||
| 57 | sclk_audio2 152 | ||
| 58 | sclk_spdif 153 | ||
| 59 | sclk_spi0 154 | ||
| 60 | sclk_spi1 155 | ||
| 61 | sclk_spi2 156 | ||
| 62 | div_i2s1 157 | ||
| 63 | div_i2s2 158 | ||
| 64 | sclk_hdmiphy 159 | ||
| 65 | div_pcm0 160 | ||
| 66 | |||
| 67 | |||
| 68 | [Peripheral Clock Gates] | ||
| 69 | |||
| 70 | Clock ID | ||
| 71 | ---------------------------- | ||
| 72 | |||
| 73 | gscl0 256 | ||
| 74 | gscl1 257 | ||
| 75 | gscl2 258 | ||
| 76 | gscl3 259 | ||
| 77 | gscl_wa 260 | ||
| 78 | gscl_wb 261 | ||
| 79 | smmu_gscl0 262 | ||
| 80 | smmu_gscl1 263 | ||
| 81 | smmu_gscl2 264 | ||
| 82 | smmu_gscl3 265 | ||
| 83 | mfc 266 | ||
| 84 | smmu_mfcl 267 | ||
| 85 | smmu_mfcr 268 | ||
| 86 | rotator 269 | ||
| 87 | jpeg 270 | ||
| 88 | mdma1 271 | ||
| 89 | smmu_rotator 272 | ||
| 90 | smmu_jpeg 273 | ||
| 91 | smmu_mdma1 274 | ||
| 92 | pdma0 275 | ||
| 93 | pdma1 276 | ||
| 94 | sata 277 | ||
| 95 | usbotg 278 | ||
| 96 | mipi_hsi 279 | ||
| 97 | sdmmc0 280 | ||
| 98 | sdmmc1 281 | ||
| 99 | sdmmc2 282 | ||
| 100 | sdmmc3 283 | ||
| 101 | sromc 284 | ||
| 102 | usb2 285 | ||
| 103 | usb3 286 | ||
| 104 | sata_phyctrl 287 | ||
| 105 | sata_phyi2c 288 | ||
| 106 | uart0 289 | ||
| 107 | uart1 290 | ||
| 108 | uart2 291 | ||
| 109 | uart3 292 | ||
| 110 | uart4 293 | ||
| 111 | i2c0 294 | ||
| 112 | i2c1 295 | ||
| 113 | i2c2 296 | ||
| 114 | i2c3 297 | ||
| 115 | i2c4 298 | ||
| 116 | i2c5 299 | ||
| 117 | i2c6 300 | ||
| 118 | i2c7 301 | ||
| 119 | i2c_hdmi 302 | ||
| 120 | adc 303 | ||
| 121 | spi0 304 | ||
| 122 | spi1 305 | ||
| 123 | spi2 306 | ||
| 124 | i2s1 307 | ||
| 125 | i2s2 308 | ||
| 126 | pcm1 309 | ||
| 127 | pcm2 310 | ||
| 128 | pwm 311 | ||
| 129 | spdif 312 | ||
| 130 | ac97 313 | ||
| 131 | hsi2c0 314 | ||
| 132 | hsi2c1 315 | ||
| 133 | hs12c2 316 | ||
| 134 | hs12c3 317 | ||
| 135 | chipid 318 | ||
| 136 | sysreg 319 | ||
| 137 | pmu 320 | ||
| 138 | cmu_top 321 | ||
| 139 | cmu_core 322 | ||
| 140 | cmu_mem 323 | ||
| 141 | tzpc0 324 | ||
| 142 | tzpc1 325 | ||
| 143 | tzpc2 326 | ||
| 144 | tzpc3 327 | ||
| 145 | tzpc4 328 | ||
| 146 | tzpc5 329 | ||
| 147 | tzpc6 330 | ||
| 148 | tzpc7 331 | ||
| 149 | tzpc8 332 | ||
| 150 | tzpc9 333 | ||
| 151 | hdmi_cec 334 | ||
| 152 | mct 335 | ||
| 153 | wdt 336 | ||
| 154 | rtc 337 | ||
| 155 | tmu 338 | ||
| 156 | fimd1 339 | ||
| 157 | mie1 340 | ||
| 158 | dsim0 341 | ||
| 159 | dp 342 | ||
| 160 | mixer 343 | ||
| 161 | hdmi 344 | ||
| 162 | g2d 345 | ||
| 163 | mdma0 346 | ||
| 164 | smmu_mdma0 347 | ||
| 165 | |||
| 166 | |||
| 167 | [Clock Muxes] | ||
| 168 | |||
| 169 | Clock ID | ||
| 170 | ---------------------------- | ||
| 171 | mout_hdmi 1024 | ||
| 172 | 18 | ||
| 19 | All available clocks are defined as preprocessor macros in | ||
| 20 | dt-bindings/clock/exynos5250.h header and can be used in device | ||
| 21 | tree sources. | ||
| 173 | 22 | ||
| 174 | Example 1: An example of a clock controller node is listed below. | 23 | Example 1: An example of a clock controller node is listed below. |
| 175 | 24 | ||
| @@ -187,6 +36,6 @@ Example 2: UART controller node that consumes the clock generated by the clock | |||
| 187 | compatible = "samsung,exynos4210-uart"; | 36 | compatible = "samsung,exynos4210-uart"; |
| 188 | reg = <0x13820000 0x100>; | 37 | reg = <0x13820000 0x100>; |
| 189 | interrupts = <0 54 0>; | 38 | interrupts = <0 54 0>; |
| 190 | clocks = <&clock 314>, <&clock 153>; | 39 | clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; |
| 191 | clock-names = "uart", "clk_uart_baud0"; | 40 | clock-names = "uart", "clk_uart_baud0"; |
| 192 | }; | 41 | }; |
diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt index 458f34789e5d..ca88c97a8562 100644 --- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt | |||
| @@ -13,184 +13,12 @@ Required Properties: | |||
| 13 | 13 | ||
| 14 | - #clock-cells: should be 1. | 14 | - #clock-cells: should be 1. |
| 15 | 15 | ||
| 16 | The following is the list of clocks generated by the controller. Each clock is | 16 | Each clock is assigned an identifier and client nodes can use this identifier |
| 17 | assigned an identifier and client nodes use this identifier to specify the | 17 | to specify the clock which they consume. |
| 18 | clock which they consume. | ||
| 19 | 18 | ||
| 20 | 19 | All available clocks are defined as preprocessor macros in | |
| 21 | [Core Clocks] | 20 | dt-bindings/clock/exynos5420.h header and can be used in device |
| 22 | 21 | tree sources. | |
| 23 | Clock ID | ||
| 24 | ---------------------------- | ||
| 25 | |||
| 26 | fin_pll 1 | ||
| 27 | |||
| 28 | [Clock Gate for Special Clocks] | ||
| 29 | |||
| 30 | Clock ID | ||
| 31 | ---------------------------- | ||
| 32 | sclk_uart0 128 | ||
| 33 | sclk_uart1 129 | ||
| 34 | sclk_uart2 130 | ||
| 35 | sclk_uart3 131 | ||
| 36 | sclk_mmc0 132 | ||
| 37 | sclk_mmc1 133 | ||
| 38 | sclk_mmc2 134 | ||
| 39 | sclk_spi0 135 | ||
| 40 | sclk_spi1 136 | ||
| 41 | sclk_spi2 137 | ||
| 42 | sclk_i2s1 138 | ||
| 43 | sclk_i2s2 139 | ||
| 44 | sclk_pcm1 140 | ||
| 45 | sclk_pcm2 141 | ||
| 46 | sclk_spdif 142 | ||
| 47 | sclk_hdmi 143 | ||
| 48 | sclk_pixel 144 | ||
| 49 | sclk_dp1 145 | ||
| 50 | sclk_mipi1 146 | ||
| 51 | sclk_fimd1 147 | ||
| 52 | sclk_maudio0 148 | ||
| 53 | sclk_maupcm0 149 | ||
| 54 | sclk_usbd300 150 | ||
| 55 | sclk_usbd301 151 | ||
| 56 | sclk_usbphy300 152 | ||
| 57 | sclk_usbphy301 153 | ||
| 58 | sclk_unipro 154 | ||
| 59 | sclk_pwm 155 | ||
| 60 | sclk_gscl_wa 156 | ||
| 61 | sclk_gscl_wb 157 | ||
| 62 | sclk_hdmiphy 158 | ||
| 63 | |||
| 64 | [Peripheral Clock Gates] | ||
| 65 | |||
| 66 | Clock ID | ||
| 67 | ---------------------------- | ||
| 68 | |||
| 69 | aclk66_peric 256 | ||
| 70 | uart0 257 | ||
| 71 | uart1 258 | ||
| 72 | uart2 259 | ||
| 73 | uart3 260 | ||
| 74 | i2c0 261 | ||
| 75 | i2c1 262 | ||
| 76 | i2c2 263 | ||
| 77 | i2c3 264 | ||
| 78 | i2c4 265 | ||
| 79 | i2c5 266 | ||
| 80 | i2c6 267 | ||
| 81 | i2c7 268 | ||
| 82 | i2c_hdmi 269 | ||
| 83 | tsadc 270 | ||
| 84 | spi0 271 | ||
| 85 | spi1 272 | ||
| 86 | spi2 273 | ||
| 87 | keyif 274 | ||
| 88 | i2s1 275 | ||
| 89 | i2s2 276 | ||
| 90 | pcm1 277 | ||
| 91 | pcm2 278 | ||
| 92 | pwm 279 | ||
| 93 | spdif 280 | ||
| 94 | i2c8 281 | ||
| 95 | i2c9 282 | ||
| 96 | i2c10 283 | ||
| 97 | aclk66_psgen 300 | ||
| 98 | chipid 301 | ||
| 99 | sysreg 302 | ||
| 100 | tzpc0 303 | ||
| 101 | tzpc1 304 | ||
| 102 | tzpc2 305 | ||
| 103 | tzpc3 306 | ||
| 104 | tzpc4 307 | ||
| 105 | tzpc5 308 | ||
| 106 | tzpc6 309 | ||
| 107 | tzpc7 310 | ||
| 108 | tzpc8 311 | ||
| 109 | tzpc9 312 | ||
| 110 | hdmi_cec 313 | ||
| 111 | seckey 314 | ||
| 112 | mct 315 | ||
| 113 | wdt 316 | ||
| 114 | rtc 317 | ||
| 115 | tmu 318 | ||
| 116 | tmu_gpu 319 | ||
| 117 | pclk66_gpio 330 | ||
| 118 | aclk200_fsys2 350 | ||
| 119 | mmc0 351 | ||
| 120 | mmc1 352 | ||
| 121 | mmc2 353 | ||
| 122 | sromc 354 | ||
| 123 | ufs 355 | ||
| 124 | aclk200_fsys 360 | ||
| 125 | tsi 361 | ||
| 126 | pdma0 362 | ||
| 127 | pdma1 363 | ||
| 128 | rtic 364 | ||
| 129 | usbh20 365 | ||
| 130 | usbd300 366 | ||
| 131 | usbd301 377 | ||
| 132 | aclk400_mscl 380 | ||
| 133 | mscl0 381 | ||
| 134 | mscl1 382 | ||
| 135 | mscl2 383 | ||
| 136 | smmu_mscl0 384 | ||
| 137 | smmu_mscl1 385 | ||
| 138 | smmu_mscl2 386 | ||
| 139 | aclk333 400 | ||
| 140 | mfc 401 | ||
| 141 | smmu_mfcl 402 | ||
| 142 | smmu_mfcr 403 | ||
| 143 | aclk200_disp1 410 | ||
| 144 | dsim1 411 | ||
| 145 | dp1 412 | ||
| 146 | hdmi 413 | ||
| 147 | aclk300_disp1 420 | ||
| 148 | fimd1 421 | ||
| 149 | smmu_fimd1 422 | ||
| 150 | aclk166 430 | ||
| 151 | mixer 431 | ||
| 152 | aclk266 440 | ||
| 153 | rotator 441 | ||
| 154 | mdma1 442 | ||
| 155 | smmu_rotator 443 | ||
| 156 | smmu_mdma1 444 | ||
| 157 | aclk300_jpeg 450 | ||
| 158 | jpeg 451 | ||
| 159 | jpeg2 452 | ||
| 160 | smmu_jpeg 453 | ||
| 161 | aclk300_gscl 460 | ||
| 162 | smmu_gscl0 461 | ||
| 163 | smmu_gscl1 462 | ||
| 164 | gscl_wa 463 | ||
| 165 | gscl_wb 464 | ||
| 166 | gscl0 465 | ||
| 167 | gscl1 466 | ||
| 168 | clk_3aa 467 | ||
| 169 | aclk266_g2d 470 | ||
| 170 | sss 471 | ||
| 171 | slim_sss 472 | ||
| 172 | mdma0 473 | ||
| 173 | aclk333_g2d 480 | ||
| 174 | g2d 481 | ||
| 175 | aclk333_432_gscl 490 | ||
| 176 | smmu_3aa 491 | ||
| 177 | smmu_fimcl0 492 | ||
| 178 | smmu_fimcl1 493 | ||
| 179 | smmu_fimcl3 494 | ||
| 180 | fimc_lite3 495 | ||
| 181 | aclk_g3d 500 | ||
| 182 | g3d 501 | ||
| 183 | smmu_mixer 502 | ||
| 184 | |||
| 185 | Mux ID | ||
| 186 | ---------------------------- | ||
| 187 | |||
| 188 | mout_hdmi 640 | ||
| 189 | |||
| 190 | Divider ID | ||
| 191 | ---------------------------- | ||
| 192 | |||
| 193 | dout_pixel 768 | ||
| 194 | 22 | ||
| 195 | Example 1: An example of a clock controller node is listed below. | 23 | Example 1: An example of a clock controller node is listed below. |
| 196 | 24 | ||
| @@ -208,6 +36,6 @@ Example 2: UART controller node that consumes the clock generated by the clock | |||
| 208 | compatible = "samsung,exynos4210-uart"; | 36 | compatible = "samsung,exynos4210-uart"; |
| 209 | reg = <0x13820000 0x100>; | 37 | reg = <0x13820000 0x100>; |
| 210 | interrupts = <0 54 0>; | 38 | interrupts = <0 54 0>; |
| 211 | clocks = <&clock 259>, <&clock 130>; | 39 | clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; |
| 212 | clock-names = "uart", "clk_uart_baud0"; | 40 | clock-names = "uart", "clk_uart_baud0"; |
| 213 | }; | 41 | }; |
diff --git a/Documentation/devicetree/bindings/clock/exynos5440-clock.txt b/Documentation/devicetree/bindings/clock/exynos5440-clock.txt index 9955dc9c7d96..5f7005f73058 100644 --- a/Documentation/devicetree/bindings/clock/exynos5440-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5440-clock.txt | |||
| @@ -12,45 +12,12 @@ Required Properties: | |||
| 12 | 12 | ||
| 13 | - #clock-cells: should be 1. | 13 | - #clock-cells: should be 1. |
| 14 | 14 | ||
| 15 | The following is the list of clocks generated by the controller. Each clock is | 15 | Each clock is assigned an identifier and client nodes can use this identifier |
| 16 | assigned an identifier and client nodes use this identifier to specify the | 16 | to specify the clock which they consume. |
| 17 | clock which they consume. | 17 | |
| 18 | 18 | All available clocks are defined as preprocessor macros in | |
| 19 | 19 | dt-bindings/clock/exynos5440.h header and can be used in device | |
| 20 | [Core Clocks] | 20 | tree sources. |
| 21 | |||
| 22 | Clock ID | ||
| 23 | ---------------------------- | ||
| 24 | |||
| 25 | xtal 1 | ||
| 26 | arm_clk 2 | ||
| 27 | |||
| 28 | [Peripheral Clock Gates] | ||
| 29 | |||
| 30 | Clock ID | ||
| 31 | ---------------------------- | ||
| 32 | |||
| 33 | spi_baud 16 | ||
| 34 | pb0_250 17 | ||
| 35 | pr0_250 18 | ||
| 36 | pr1_250 19 | ||
| 37 | b_250 20 | ||
| 38 | b_125 21 | ||
| 39 | b_200 22 | ||
| 40 | sata 23 | ||
| 41 | usb 24 | ||
| 42 | gmac0 25 | ||
| 43 | cs250 26 | ||
| 44 | pb0_250_o 27 | ||
| 45 | pr0_250_o 28 | ||
| 46 | pr1_250_o 29 | ||
| 47 | b_250_o 30 | ||
| 48 | b_125_o 31 | ||
| 49 | b_200_o 32 | ||
| 50 | sata_o 33 | ||
| 51 | usb_o 34 | ||
| 52 | gmac0_o 35 | ||
| 53 | cs250_o 36 | ||
| 54 | 21 | ||
| 55 | Example: An example of a clock controller node is listed below. | 22 | Example: An example of a clock controller node is listed below. |
| 56 | 23 | ||
diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt index 1a1ac2e560e9..e11ed0fe770c 100644 --- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt +++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt | |||
| @@ -58,6 +58,7 @@ plx,pex8648 48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch | |||
| 58 | ramtron,24c64 i2c serial eeprom (24cxx) | 58 | ramtron,24c64 i2c serial eeprom (24cxx) |
| 59 | ricoh,rs5c372a I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC | 59 | ricoh,rs5c372a I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC |
| 60 | samsung,24ad0xd1 S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power) | 60 | samsung,24ad0xd1 S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power) |
| 61 | sii,s35390a 2-wire CMOS real-time clock | ||
| 61 | st-micro,24c256 i2c serial eeprom (24cxx) | 62 | st-micro,24c256 i2c serial eeprom (24cxx) |
| 62 | stm,m41t00 Serial Access TIMEKEEPER | 63 | stm,m41t00 Serial Access TIMEKEEPER |
| 63 | stm,m41t62 Serial real-time clock (RTC) with alarm | 64 | stm,m41t62 Serial real-time clock (RTC) with alarm |
diff --git a/Documentation/devicetree/bindings/arm/atmel-adc.txt b/Documentation/devicetree/bindings/iio/adc/at91_adc.txt index d1061469f63d..82061c7e4fea 100644 --- a/Documentation/devicetree/bindings/arm/atmel-adc.txt +++ b/Documentation/devicetree/bindings/iio/adc/at91_adc.txt | |||
| @@ -5,32 +5,32 @@ Required properties: | |||
| 5 | <chip> can be "at91sam9260", "at91sam9g45" or "at91sam9x5" | 5 | <chip> can be "at91sam9260", "at91sam9g45" or "at91sam9x5" |
| 6 | - reg: Should contain ADC registers location and length | 6 | - reg: Should contain ADC registers location and length |
| 7 | - interrupts: Should contain the IRQ line for the ADC | 7 | - interrupts: Should contain the IRQ line for the ADC |
| 8 | - atmel,adc-channels-used: Bitmask of the channels muxed and enable for this | 8 | - atmel,adc-channels-used: Bitmask of the channels muxed and enabled for this |
| 9 | device | 9 | device |
| 10 | - atmel,adc-startup-time: Startup Time of the ADC in microseconds as | 10 | - atmel,adc-startup-time: Startup Time of the ADC in microseconds as |
| 11 | defined in the datasheet | 11 | defined in the datasheet |
| 12 | - atmel,adc-vref: Reference voltage in millivolts for the conversions | 12 | - atmel,adc-vref: Reference voltage in millivolts for the conversions |
| 13 | - atmel,adc-res: List of resolution in bits supported by the ADC. List size | 13 | - atmel,adc-res: List of resolutions in bits supported by the ADC. List size |
| 14 | must be two at least. | 14 | must be two at least. |
| 15 | - atmel,adc-res-names: Contains one identifier string for each resolution | 15 | - atmel,adc-res-names: Contains one identifier string for each resolution |
| 16 | in atmel,adc-res property. "lowres" and "highres" | 16 | in atmel,adc-res property. "lowres" and "highres" |
| 17 | identifiers are required. | 17 | identifiers are required. |
| 18 | 18 | ||
| 19 | Optional properties: | 19 | Optional properties: |
| 20 | - atmel,adc-use-external: Boolean to enable of external triggers | 20 | - atmel,adc-use-external-triggers: Boolean to enable the external triggers |
| 21 | - atmel,adc-use-res: String corresponding to an identifier from | 21 | - atmel,adc-use-res: String corresponding to an identifier from |
| 22 | atmel,adc-res-names property. If not specified, the highest | 22 | atmel,adc-res-names property. If not specified, the highest |
| 23 | resolution will be used. | 23 | resolution will be used. |
| 24 | - atmel,adc-sleep-mode: Boolean to enable sleep mode when no conversion | 24 | - atmel,adc-sleep-mode: Boolean to enable sleep mode when no conversion |
| 25 | - atmel,adc-sample-hold-time: Sample and Hold Time in microseconds | 25 | - atmel,adc-sample-hold-time: Sample and Hold Time in microseconds |
| 26 | - atmel,adc-ts-wires: Number of touch screen wires. Should be 4 or 5. If this | 26 | - atmel,adc-ts-wires: Number of touchscreen wires. Should be 4 or 5. If this |
| 27 | value is set, then adc driver will enable touch screen | 27 | value is set, then the adc driver will enable touchscreen |
| 28 | support. | 28 | support. |
| 29 | NOTE: when adc touch screen enabled, the adc hardware trigger will be | 29 | NOTE: when adc touchscreen is enabled, the adc hardware trigger will be |
| 30 | disabled. Since touch screen will occupied the trigger register. | 30 | disabled. Since touchscreen will occupy the trigger register. |
| 31 | - atmel,adc-ts-pressure-threshold: a pressure threshold for touchscreen. It | 31 | - atmel,adc-ts-pressure-threshold: a pressure threshold for touchscreen. It |
| 32 | make touch detect more precision. | 32 | makes touch detection more precise. |
| 33 | 33 | ||
| 34 | Optional trigger Nodes: | 34 | Optional trigger Nodes: |
| 35 | - Required properties: | 35 | - Required properties: |
| 36 | * trigger-name: Name of the trigger exposed to the user | 36 | * trigger-name: Name of the trigger exposed to the user |
| @@ -41,40 +41,41 @@ Optional trigger Nodes: | |||
| 41 | 41 | ||
| 42 | Examples: | 42 | Examples: |
| 43 | adc0: adc@fffb0000 { | 43 | adc0: adc@fffb0000 { |
| 44 | #address-cells = <1>; | ||
| 45 | #size-cells = <0>; | ||
| 44 | compatible = "atmel,at91sam9260-adc"; | 46 | compatible = "atmel,at91sam9260-adc"; |
| 45 | reg = <0xfffb0000 0x100>; | 47 | reg = <0xfffb0000 0x100>; |
| 46 | interrupts = <20 4>; | 48 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; |
| 47 | atmel,adc-channel-base = <0x30>; | ||
| 48 | atmel,adc-channels-used = <0xff>; | 49 | atmel,adc-channels-used = <0xff>; |
| 49 | atmel,adc-drdy-mask = <0x10000>; | ||
| 50 | atmel,adc-num-channels = <8>; | ||
| 51 | atmel,adc-startup-time = <40>; | 50 | atmel,adc-startup-time = <40>; |
| 52 | atmel,adc-status-register = <0x1c>; | 51 | atmel,adc-use-external-triggers; |
| 53 | atmel,adc-trigger-register = <0x08>; | ||
| 54 | atmel,adc-use-external; | ||
| 55 | atmel,adc-vref = <3300>; | 52 | atmel,adc-vref = <3300>; |
| 56 | atmel,adc-res = <8 10>; | 53 | atmel,adc-res = <8 10>; |
| 57 | atmel,adc-res-names = "lowres", "highres"; | 54 | atmel,adc-res-names = "lowres", "highres"; |
| 58 | atmel,adc-use-res = "lowres"; | 55 | atmel,adc-use-res = "lowres"; |
| 59 | 56 | ||
| 60 | trigger@0 { | 57 | trigger@0 { |
| 58 | reg = <0>; | ||
| 61 | trigger-name = "external-rising"; | 59 | trigger-name = "external-rising"; |
| 62 | trigger-value = <0x1>; | 60 | trigger-value = <0x1>; |
| 63 | trigger-external; | 61 | trigger-external; |
| 64 | }; | 62 | }; |
| 65 | trigger@1 { | 63 | trigger@1 { |
| 64 | reg = <1>; | ||
| 66 | trigger-name = "external-falling"; | 65 | trigger-name = "external-falling"; |
| 67 | trigger-value = <0x2>; | 66 | trigger-value = <0x2>; |
| 68 | trigger-external; | 67 | trigger-external; |
| 69 | }; | 68 | }; |
| 70 | 69 | ||
| 71 | trigger@2 { | 70 | trigger@2 { |
| 71 | reg = <2>; | ||
| 72 | trigger-name = "external-any"; | 72 | trigger-name = "external-any"; |
| 73 | trigger-value = <0x3>; | 73 | trigger-value = <0x3>; |
| 74 | trigger-external; | 74 | trigger-external; |
| 75 | }; | 75 | }; |
| 76 | 76 | ||
| 77 | trigger@3 { | 77 | trigger@3 { |
| 78 | reg = <3>; | ||
| 78 | trigger-name = "continuous"; | 79 | trigger-name = "continuous"; |
| 79 | trigger-value = <0x6>; | 80 | trigger-value = <0x6>; |
| 80 | }; | 81 | }; |
diff --git a/Documentation/devicetree/bindings/serial/atmel-usart.txt b/Documentation/devicetree/bindings/serial/atmel-usart.txt index 9c5d19ac935c..17c1042b2df8 100644 --- a/Documentation/devicetree/bindings/serial/atmel-usart.txt +++ b/Documentation/devicetree/bindings/serial/atmel-usart.txt | |||
| @@ -13,6 +13,8 @@ Required properties: | |||
| 13 | Optional properties: | 13 | Optional properties: |
| 14 | - atmel,use-dma-rx: use of PDC or DMA for receiving data | 14 | - atmel,use-dma-rx: use of PDC or DMA for receiving data |
| 15 | - atmel,use-dma-tx: use of PDC or DMA for transmitting data | 15 | - atmel,use-dma-tx: use of PDC or DMA for transmitting data |
| 16 | - rts-gpios: specify a GPIO for RTS line. It will use specified PIO instead of the peripheral | ||
| 17 | function pin for the USART RTS feature. If unsure, don't specify this property. | ||
| 16 | - add dma bindings for dma transfer: | 18 | - add dma bindings for dma transfer: |
| 17 | - dmas: DMA specifier, consisting of a phandle to DMA controller node, | 19 | - dmas: DMA specifier, consisting of a phandle to DMA controller node, |
| 18 | memory peripheral interface and USART DMA channel ID, FIFO configuration. | 20 | memory peripheral interface and USART DMA channel ID, FIFO configuration. |
| @@ -33,6 +35,7 @@ Example: | |||
| 33 | clock-names = "usart"; | 35 | clock-names = "usart"; |
| 34 | atmel,use-dma-rx; | 36 | atmel,use-dma-rx; |
| 35 | atmel,use-dma-tx; | 37 | atmel,use-dma-tx; |
| 38 | rts-gpios = <&pioD 15 0>; | ||
| 36 | }; | 39 | }; |
| 37 | 40 | ||
| 38 | - use DMA: | 41 | - use DMA: |
diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt b/Documentation/devicetree/bindings/usb/atmel-usb.txt index 55f51af08bc7..bc2222ca3f2a 100644 --- a/Documentation/devicetree/bindings/usb/atmel-usb.txt +++ b/Documentation/devicetree/bindings/usb/atmel-usb.txt | |||
| @@ -57,8 +57,8 @@ Required properties: | |||
| 57 | - ep childnode: To specify the number of endpoints and their properties. | 57 | - ep childnode: To specify the number of endpoints and their properties. |
| 58 | 58 | ||
| 59 | Optional properties: | 59 | Optional properties: |
| 60 | - atmel,vbus-gpio: If present, specifies a gpio that needs to be | 60 | - atmel,vbus-gpio: If present, specifies a gpio that allows to detect whether |
| 61 | activated for the bus to be powered. | 61 | vbus is present (USB is connected). |
| 62 | 62 | ||
| 63 | Required child node properties: | 63 | Required child node properties: |
| 64 | - name: Name of the endpoint. | 64 | - name: Name of the endpoint. |
diff --git a/Documentation/devicetree/bindings/usb/ehci-omap.txt b/Documentation/devicetree/bindings/usb/ehci-omap.txt index 485a9a1efa7a..3dc231c832b0 100644 --- a/Documentation/devicetree/bindings/usb/ehci-omap.txt +++ b/Documentation/devicetree/bindings/usb/ehci-omap.txt | |||
| @@ -21,7 +21,7 @@ Documentation/devicetree/bindings/mfd/omap-usb-host.txt | |||
| 21 | Example for OMAP4: | 21 | Example for OMAP4: |
| 22 | 22 | ||
| 23 | usbhsehci: ehci@4a064c00 { | 23 | usbhsehci: ehci@4a064c00 { |
| 24 | compatible = "ti,ehci-omap", "usb-ehci"; | 24 | compatible = "ti,ehci-omap"; |
| 25 | reg = <0x4a064c00 0x400>; | 25 | reg = <0x4a064c00 0x400>; |
| 26 | interrupts = <0 77 0x4>; | 26 | interrupts = <0 77 0x4>; |
| 27 | }; | 27 | }; |
diff --git a/Documentation/devicetree/bindings/usb/ohci-omap3.txt b/Documentation/devicetree/bindings/usb/ohci-omap3.txt index 14ab42812a8e..ce8c47cff6d0 100644 --- a/Documentation/devicetree/bindings/usb/ohci-omap3.txt +++ b/Documentation/devicetree/bindings/usb/ohci-omap3.txt | |||
| @@ -9,7 +9,7 @@ Required properties: | |||
| 9 | Example for OMAP4: | 9 | Example for OMAP4: |
| 10 | 10 | ||
| 11 | usbhsohci: ohci@4a064800 { | 11 | usbhsohci: ohci@4a064800 { |
| 12 | compatible = "ti,ohci-omap3", "usb-ohci"; | 12 | compatible = "ti,ohci-omap3"; |
| 13 | reg = <0x4a064800 0x400>; | 13 | reg = <0x4a064800 0x400>; |
| 14 | interrupts = <0 76 0x4>; | 14 | interrupts = <0 76 0x4>; |
| 15 | }; | 15 | }; |
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 40ce2df0e0e9..4685ec396c34 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt | |||
| @@ -29,11 +29,13 @@ cortina Cortina Systems, Inc. | |||
| 29 | dallas Maxim Integrated Products (formerly Dallas Semiconductor) | 29 | dallas Maxim Integrated Products (formerly Dallas Semiconductor) |
| 30 | davicom DAVICOM Semiconductor, Inc. | 30 | davicom DAVICOM Semiconductor, Inc. |
| 31 | denx Denx Software Engineering | 31 | denx Denx Software Engineering |
| 32 | dmo Data Modul AG | ||
| 32 | edt Emerging Display Technologies | 33 | edt Emerging Display Technologies |
| 33 | emmicro EM Microelectronic | 34 | emmicro EM Microelectronic |
| 34 | epfl Ecole Polytechnique Fédérale de Lausanne | 35 | epfl Ecole Polytechnique Fédérale de Lausanne |
| 35 | epson Seiko Epson Corp. | 36 | epson Seiko Epson Corp. |
| 36 | est ESTeem Wireless Modems | 37 | est ESTeem Wireless Modems |
| 38 | eukrea Eukréa Electromatique | ||
| 37 | fsl Freescale Semiconductor | 39 | fsl Freescale Semiconductor |
| 38 | GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc. | 40 | GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc. |
| 39 | gef GE Fanuc Intelligent Platforms Embedded Systems, Inc. | 41 | gef GE Fanuc Intelligent Platforms Embedded Systems, Inc. |
| @@ -68,10 +70,12 @@ picochip Picochip Ltd | |||
| 68 | powervr PowerVR (deprecated, use img) | 70 | powervr PowerVR (deprecated, use img) |
| 69 | qca Qualcomm Atheros, Inc. | 71 | qca Qualcomm Atheros, Inc. |
| 70 | qcom Qualcomm Technologies, Inc | 72 | qcom Qualcomm Technologies, Inc |
| 73 | qnap QNAP Systems, Inc. | ||
| 71 | ralink Mediatek/Ralink Technology Corp. | 74 | ralink Mediatek/Ralink Technology Corp. |
| 72 | ramtron Ramtron International | 75 | ramtron Ramtron International |
| 73 | realtek Realtek Semiconductor Corp. | 76 | realtek Realtek Semiconductor Corp. |
| 74 | renesas Renesas Electronics Corporation | 77 | renesas Renesas Electronics Corporation |
| 78 | ricoh Ricoh Co. Ltd. | ||
| 75 | rockchip Fuzhou Rockchip Electronics Co., Ltd | 79 | rockchip Fuzhou Rockchip Electronics Co., Ltd |
| 76 | samsung Samsung Semiconductor | 80 | samsung Samsung Semiconductor |
| 77 | sbs Smart Battery System | 81 | sbs Smart Battery System |
| @@ -79,18 +83,21 @@ schindler Schindler | |||
| 79 | sil Silicon Image | 83 | sil Silicon Image |
| 80 | silabs Silicon Laboratories | 84 | silabs Silicon Laboratories |
| 81 | simtek | 85 | simtek |
| 86 | sii Seiko Instruments, Inc. | ||
| 82 | sirf SiRF Technology, Inc. | 87 | sirf SiRF Technology, Inc. |
| 83 | snps Synopsys, Inc. | 88 | snps Synopsys, Inc. |
| 84 | spansion Spansion Inc. | 89 | spansion Spansion Inc. |
| 85 | st STMicroelectronics | 90 | st STMicroelectronics |
| 86 | ste ST-Ericsson | 91 | ste ST-Ericsson |
| 87 | stericsson ST-Ericsson | 92 | stericsson ST-Ericsson |
| 93 | synology Synology, Inc. | ||
| 88 | ti Texas Instruments | 94 | ti Texas Instruments |
| 89 | tlm Trusted Logic Mobility | 95 | tlm Trusted Logic Mobility |
| 90 | toshiba Toshiba Corporation | 96 | toshiba Toshiba Corporation |
| 91 | toumaz Toumaz | 97 | toumaz Toumaz |
| 92 | v3 V3 Semiconductor | 98 | v3 V3 Semiconductor |
| 93 | via VIA Technologies, Inc. | 99 | via VIA Technologies, Inc. |
| 100 | voipac Voipac Technologies s.r.o. | ||
| 94 | winbond Winbond Electronics corp. | 101 | winbond Winbond Electronics corp. |
| 95 | wlf Wolfson Microelectronics | 102 | wlf Wolfson Microelectronics |
| 96 | wm Wondermedia Technologies, Inc. | 103 | wm Wondermedia Technologies, Inc. |
diff --git a/MAINTAINERS b/MAINTAINERS index 85b3dd8008b7..e4812f9319bd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS | |||
| @@ -1167,6 +1167,14 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) | |||
| 1167 | W: http://www.arm.linux.org.uk/ | 1167 | W: http://www.arm.linux.org.uk/ |
| 1168 | S: Maintained | 1168 | S: Maintained |
| 1169 | 1169 | ||
| 1170 | ARM/QUALCOMM SUPPORT | ||
| 1171 | M: Kumar Gala <galak@codeaurora.org> | ||
| 1172 | M: David Brown <davidb@codeaurora.org> | ||
| 1173 | L: linux-arm-msm@vger.kernel.org | ||
| 1174 | S: Maintained | ||
| 1175 | F: arch/arm/mach-qcom/ | ||
| 1176 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git | ||
| 1177 | |||
| 1170 | ARM/RADISYS ENP2611 MACHINE SUPPORT | 1178 | ARM/RADISYS ENP2611 MACHINE SUPPORT |
| 1171 | M: Lennert Buytenhek <kernel@wantstofly.org> | 1179 | M: Lennert Buytenhek <kernel@wantstofly.org> |
| 1172 | L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) | 1180 | L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) |
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e25419817791..df9266d41b3b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
| @@ -421,9 +421,6 @@ config ARCH_EFM32 | |||
| 421 | depends on !MMU | 421 | depends on !MMU |
| 422 | select ARCH_REQUIRE_GPIOLIB | 422 | select ARCH_REQUIRE_GPIOLIB |
| 423 | select ARM_NVIC | 423 | select ARM_NVIC |
| 424 | # CLKSRC_MMIO is wrong here, but needed until a proper fix is merged, | ||
| 425 | # i.e. CLKSRC_EFM32 selecting CLKSRC_MMIO | ||
| 426 | select CLKSRC_MMIO | ||
| 427 | select CLKSRC_OF | 424 | select CLKSRC_OF |
| 428 | select COMMON_CLK | 425 | select COMMON_CLK |
| 429 | select CPU_V7M | 426 | select CPU_V7M |
| @@ -657,9 +654,8 @@ config ARCH_PXA | |||
| 657 | help | 654 | help |
| 658 | Support for Intel/Marvell's PXA2xx/PXA3xx processor line. | 655 | Support for Intel/Marvell's PXA2xx/PXA3xx processor line. |
| 659 | 656 | ||
| 660 | config ARCH_MSM_NODT | 657 | config ARCH_MSM |
| 661 | bool "Qualcomm MSM" | 658 | bool "Qualcomm MSM (non-multiplatform)" |
| 662 | select ARCH_MSM | ||
| 663 | select ARCH_REQUIRE_GPIOLIB | 659 | select ARCH_REQUIRE_GPIOLIB |
| 664 | select COMMON_CLK | 660 | select COMMON_CLK |
| 665 | select GENERIC_CLOCKEVENTS | 661 | select GENERIC_CLOCKEVENTS |
| @@ -898,7 +894,7 @@ config ARCH_MULTI_V5 | |||
| 898 | bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" | 894 | bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" |
| 899 | depends on !ARCH_MULTI_V6_V7 | 895 | depends on !ARCH_MULTI_V6_V7 |
| 900 | select ARCH_MULTI_V4_V5 | 896 | select ARCH_MULTI_V4_V5 |
| 901 | select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \ | 897 | select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ |
| 902 | CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ | 898 | CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ |
| 903 | CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) | 899 | CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) |
| 904 | 900 | ||
| @@ -1005,6 +1001,8 @@ source "arch/arm/plat-pxa/Kconfig" | |||
| 1005 | 1001 | ||
| 1006 | source "arch/arm/mach-mmp/Kconfig" | 1002 | source "arch/arm/mach-mmp/Kconfig" |
| 1007 | 1003 | ||
| 1004 | source "arch/arm/mach-qcom/Kconfig" | ||
| 1005 | |||
| 1008 | source "arch/arm/mach-realview/Kconfig" | 1006 | source "arch/arm/mach-realview/Kconfig" |
| 1009 | 1007 | ||
| 1010 | source "arch/arm/mach-rockchip/Kconfig" | 1008 | source "arch/arm/mach-rockchip/Kconfig" |
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 0531da8e5216..4491c7b05275 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug | |||
| @@ -956,7 +956,7 @@ config DEBUG_STI_UART | |||
| 956 | 956 | ||
| 957 | config DEBUG_MSM_UART | 957 | config DEBUG_MSM_UART |
| 958 | bool | 958 | bool |
| 959 | depends on ARCH_MSM | 959 | depends on ARCH_MSM || ARCH_QCOM |
| 960 | 960 | ||
| 961 | config DEBUG_LL_INCLUDE | 961 | config DEBUG_LL_INCLUDE |
| 962 | string | 962 | string |
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 08a9ef58d9c3..51e5bede657f 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile | |||
| @@ -180,6 +180,7 @@ machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2 | |||
| 180 | machine-$(CONFIG_ARCH_ORION5X) += orion5x | 180 | machine-$(CONFIG_ARCH_ORION5X) += orion5x |
| 181 | machine-$(CONFIG_ARCH_PICOXCELL) += picoxcell | 181 | machine-$(CONFIG_ARCH_PICOXCELL) += picoxcell |
| 182 | machine-$(CONFIG_ARCH_PXA) += pxa | 182 | machine-$(CONFIG_ARCH_PXA) += pxa |
| 183 | machine-$(CONFIG_ARCH_QCOM) += qcom | ||
| 183 | machine-$(CONFIG_ARCH_REALVIEW) += realview | 184 | machine-$(CONFIG_ARCH_REALVIEW) += realview |
| 184 | machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip | 185 | machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip |
| 185 | machine-$(CONFIG_ARCH_RPC) += rpc | 186 | machine-$(CONFIG_ARCH_RPC) += rpc |
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 6565a7d9a618..abd9100482d3 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile | |||
| @@ -47,19 +47,14 @@ dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb | |||
| 47 | 47 | ||
| 48 | dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb | 48 | dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb |
| 49 | dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb | 49 | dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb |
| 50 | dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \ | 50 | dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb |
| 51 | bcm28155-ap.dtb | ||
| 52 | dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb | 51 | dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb |
| 52 | dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb | ||
| 53 | dtb-$(CONFIG_ARCH_BERLIN) += \ | 53 | dtb-$(CONFIG_ARCH_BERLIN) += \ |
| 54 | berlin2-sony-nsz-gs7.dtb \ | 54 | berlin2-sony-nsz-gs7.dtb \ |
| 55 | berlin2cd-google-chromecast.dtb | 55 | berlin2cd-google-chromecast.dtb |
| 56 | dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \ | 56 | dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \ |
| 57 | da850-evm.dtb | 57 | da850-evm.dtb |
| 58 | dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \ | ||
| 59 | dove-cubox.dtb \ | ||
| 60 | dove-d2plug.dtb \ | ||
| 61 | dove-d3plug.dtb \ | ||
| 62 | dove-dove-db.dtb | ||
| 63 | dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb | 58 | dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb |
| 64 | dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ | 59 | dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ |
| 65 | exynos4210-smdkv310.dtb \ | 60 | exynos4210-smdkv310.dtb \ |
| @@ -82,14 +77,27 @@ dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ | |||
| 82 | ecx-2000.dtb | 77 | ecx-2000.dtb |
| 83 | dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \ | 78 | dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \ |
| 84 | integratorcp.dtb | 79 | integratorcp.dtb |
| 85 | dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb | 80 | kirkwood := \ |
| 86 | dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \ | 81 | kirkwood-b3.dtb \ |
| 82 | kirkwood-cloudbox.dtb \ | ||
| 87 | kirkwood-db-88f6281.dtb \ | 83 | kirkwood-db-88f6281.dtb \ |
| 88 | kirkwood-db-88f6282.dtb \ | 84 | kirkwood-db-88f6282.dtb \ |
| 89 | kirkwood-dns320.dtb \ | 85 | kirkwood-dns320.dtb \ |
| 90 | kirkwood-dns325.dtb \ | 86 | kirkwood-dns325.dtb \ |
| 91 | kirkwood-dockstar.dtb \ | 87 | kirkwood-dockstar.dtb \ |
| 92 | kirkwood-dreamplug.dtb \ | 88 | kirkwood-dreamplug.dtb \ |
| 89 | kirkwood-ds109.dtb \ | ||
| 90 | kirkwood-ds110jv10.dtb \ | ||
| 91 | kirkwood-ds111.dtb \ | ||
| 92 | kirkwood-ds209.dtb \ | ||
| 93 | kirkwood-ds210.dtb \ | ||
| 94 | kirkwood-ds212.dtb \ | ||
| 95 | kirkwood-ds212j.dtb \ | ||
| 96 | kirkwood-ds409.dtb \ | ||
| 97 | kirkwood-ds409slim.dtb \ | ||
| 98 | kirkwood-ds411.dtb \ | ||
| 99 | kirkwood-ds411j.dtb \ | ||
| 100 | kirkwood-ds411slim.dtb \ | ||
| 93 | kirkwood-goflexnet.dtb \ | 101 | kirkwood-goflexnet.dtb \ |
| 94 | kirkwood-guruplug-server-plus.dtb \ | 102 | kirkwood-guruplug-server-plus.dtb \ |
| 95 | kirkwood-ib62x0.dtb \ | 103 | kirkwood-ib62x0.dtb \ |
| @@ -112,54 +120,74 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \ | |||
| 112 | kirkwood-nsa310a.dtb \ | 120 | kirkwood-nsa310a.dtb \ |
| 113 | kirkwood-openblocks_a6.dtb \ | 121 | kirkwood-openblocks_a6.dtb \ |
| 114 | kirkwood-openblocks_a7.dtb \ | 122 | kirkwood-openblocks_a7.dtb \ |
| 123 | kirkwood-rd88f6192.dtb \ | ||
| 124 | kirkwood-rd88f6281-a0.dtb \ | ||
| 125 | kirkwood-rd88f6281-a1.dtb \ | ||
| 126 | kirkwood-rs212.dtb \ | ||
| 127 | kirkwood-rs409.dtb \ | ||
| 128 | kirkwood-rs411.dtb \ | ||
| 115 | kirkwood-sheevaplug.dtb \ | 129 | kirkwood-sheevaplug.dtb \ |
| 116 | kirkwood-sheevaplug-esata.dtb \ | 130 | kirkwood-sheevaplug-esata.dtb \ |
| 131 | kirkwood-t5325.dtb \ | ||
| 117 | kirkwood-topkick.dtb \ | 132 | kirkwood-topkick.dtb \ |
| 118 | kirkwood-ts219-6281.dtb \ | 133 | kirkwood-ts219-6281.dtb \ |
| 119 | kirkwood-ts219-6282.dtb | 134 | kirkwood-ts219-6282.dtb \ |
| 135 | kirkwood-ts419-6281.dtb \ | ||
| 136 | kirkwood-ts419-6282.dtb | ||
| 137 | dtb-$(CONFIG_ARCH_KIRKWOOD) += $(kirkwood) | ||
| 138 | dtb-$(CONFIG_MACH_KIRKWOOD) += $(kirkwood) | ||
| 139 | dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb | ||
| 120 | dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb | 140 | dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb |
| 121 | dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb | 141 | dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb |
| 122 | dtb-$(CONFIG_ARCH_MSM) += qcom-msm8660-surf.dtb \ | ||
| 123 | qcom-msm8960-cdp.dtb \ | ||
| 124 | qcom-apq8074-dragonboard.dtb | ||
| 125 | dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ | ||
| 126 | armada-370-mirabox.dtb \ | ||
| 127 | armada-370-netgear-rn102.dtb \ | ||
| 128 | armada-370-netgear-rn104.dtb \ | ||
| 129 | armada-370-rd.dtb \ | ||
| 130 | armada-xp-axpwifiap.dtb \ | ||
| 131 | armada-xp-db.dtb \ | ||
| 132 | armada-xp-gp.dtb \ | ||
| 133 | armada-xp-netgear-rn2120.dtb \ | ||
| 134 | armada-xp-matrix.dtb \ | ||
| 135 | armada-xp-openblocks-ax3-4.dtb | ||
| 136 | dtb-$(CONFIG_ARCH_MXC) += \ | 142 | dtb-$(CONFIG_ARCH_MXC) += \ |
| 143 | imx25-eukrea-mbimxsd25-baseboard.dtb \ | ||
| 137 | imx25-karo-tx25.dtb \ | 144 | imx25-karo-tx25.dtb \ |
| 138 | imx25-pdk.dtb \ | 145 | imx25-pdk.dtb \ |
| 139 | imx27-apf27.dtb \ | 146 | imx27-apf27.dtb \ |
| 140 | imx27-apf27dev.dtb \ | 147 | imx27-apf27dev.dtb \ |
| 141 | imx27-pdk.dtb \ | 148 | imx27-pdk.dtb \ |
| 142 | imx27-phytec-phycore-som.dtb \ | ||
| 143 | imx27-phytec-phycore-rdk.dtb \ | 149 | imx27-phytec-phycore-rdk.dtb \ |
| 144 | imx27-phytec-phycard-s-som.dtb \ | ||
| 145 | imx27-phytec-phycard-s-rdk.dtb \ | 150 | imx27-phytec-phycard-s-rdk.dtb \ |
| 146 | imx31-bug.dtb \ | 151 | imx31-bug.dtb \ |
| 152 | imx35-eukrea-mbimxsd35-baseboard.dtb \ | ||
| 153 | imx50-evk.dtb \ | ||
| 147 | imx51-apf51.dtb \ | 154 | imx51-apf51.dtb \ |
| 148 | imx51-apf51dev.dtb \ | 155 | imx51-apf51dev.dtb \ |
| 149 | imx51-babbage.dtb \ | 156 | imx51-babbage.dtb \ |
| 157 | imx51-eukrea-mbimxsd51-baseboard.dtb \ | ||
| 150 | imx53-ard.dtb \ | 158 | imx53-ard.dtb \ |
| 151 | imx53-evk.dtb \ | ||
| 152 | imx53-m53evk.dtb \ | 159 | imx53-m53evk.dtb \ |
| 153 | imx53-mba53.dtb \ | 160 | imx53-mba53.dtb \ |
| 154 | imx53-qsb.dtb \ | 161 | imx53-qsb.dtb \ |
| 162 | imx53-qsrb.dtb \ | ||
| 155 | imx53-smd.dtb \ | 163 | imx53-smd.dtb \ |
| 164 | imx53-tx53-x03x.dtb \ | ||
| 165 | imx53-tx53-x13x.dtb \ | ||
| 166 | imx53-voipac-bsb.dtb \ | ||
| 156 | imx6dl-cubox-i.dtb \ | 167 | imx6dl-cubox-i.dtb \ |
| 168 | imx6dl-dfi-fs700-m60.dtb \ | ||
| 169 | imx6dl-gw51xx.dtb \ | ||
| 170 | imx6dl-gw52xx.dtb \ | ||
| 171 | imx6dl-gw53xx.dtb \ | ||
| 172 | imx6dl-gw54xx.dtb \ | ||
| 157 | imx6dl-hummingboard.dtb \ | 173 | imx6dl-hummingboard.dtb \ |
| 174 | imx6dl-nitrogen6x.dtb \ | ||
| 158 | imx6dl-sabreauto.dtb \ | 175 | imx6dl-sabreauto.dtb \ |
| 176 | imx6dl-sabrelite.dtb \ | ||
| 159 | imx6dl-sabresd.dtb \ | 177 | imx6dl-sabresd.dtb \ |
| 160 | imx6dl-wandboard.dtb \ | 178 | imx6dl-wandboard.dtb \ |
| 161 | imx6q-arm2.dtb \ | 179 | imx6q-arm2.dtb \ |
| 180 | imx6q-cm-fx6.dtb \ | ||
| 162 | imx6q-cubox-i.dtb \ | 181 | imx6q-cubox-i.dtb \ |
| 182 | imx6q-dfi-fs700-m60.dtb \ | ||
| 183 | imx6q-dmo-edmqmx6.dtb \ | ||
| 184 | imx6q-gk802.dtb \ | ||
| 185 | imx6q-gw51xx.dtb \ | ||
| 186 | imx6q-gw52xx.dtb \ | ||
| 187 | imx6q-gw53xx.dtb \ | ||
| 188 | imx6q-gw5400-a.dtb \ | ||
| 189 | imx6q-gw54xx.dtb \ | ||
| 190 | imx6q-nitrogen6x.dtb \ | ||
| 163 | imx6q-phytec-pbab01.dtb \ | 191 | imx6q-phytec-pbab01.dtb \ |
| 164 | imx6q-sabreauto.dtb \ | 192 | imx6q-sabreauto.dtb \ |
| 165 | imx6q-sabrelite.dtb \ | 193 | imx6q-sabrelite.dtb \ |
| @@ -183,6 +211,9 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ | |||
| 183 | imx28-cfa10056.dtb \ | 211 | imx28-cfa10056.dtb \ |
| 184 | imx28-cfa10057.dtb \ | 212 | imx28-cfa10057.dtb \ |
| 185 | imx28-cfa10058.dtb \ | 213 | imx28-cfa10058.dtb \ |
| 214 | imx28-duckbill.dtb \ | ||
| 215 | imx28-eukrea-mbmx283lc.dtb \ | ||
| 216 | imx28-eukrea-mbmx287lc.dtb \ | ||
| 186 | imx28-evk.dtb \ | 217 | imx28-evk.dtb \ |
| 187 | imx28-m28cu3.dtb \ | 218 | imx28-m28cu3.dtb \ |
| 188 | imx28-m28evk.dtb \ | 219 | imx28-m28evk.dtb \ |
| @@ -199,6 +230,10 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ | |||
| 199 | omap2420-n810-wimax.dtb \ | 230 | omap2420-n810-wimax.dtb \ |
| 200 | omap3430-sdp.dtb \ | 231 | omap3430-sdp.dtb \ |
| 201 | omap3-beagle.dtb \ | 232 | omap3-beagle.dtb \ |
| 233 | omap3-cm-t3517.dtb \ | ||
| 234 | omap3-sbc-t3517.dtb \ | ||
| 235 | omap3-cm-t3530.dtb \ | ||
| 236 | omap3-sbc-t3530.dtb \ | ||
| 202 | omap3-cm-t3730.dtb \ | 237 | omap3-cm-t3730.dtb \ |
| 203 | omap3-sbc-t3730.dtb \ | 238 | omap3-sbc-t3730.dtb \ |
| 204 | omap3-devkit8000.dtb \ | 239 | omap3-devkit8000.dtb \ |
| @@ -224,7 +259,9 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ | |||
| 224 | omap3-gta04.dtb \ | 259 | omap3-gta04.dtb \ |
| 225 | omap3-igep0020.dtb \ | 260 | omap3-igep0020.dtb \ |
| 226 | omap3-igep0030.dtb \ | 261 | omap3-igep0030.dtb \ |
| 262 | omap3-lilly-dbb056.dtb \ | ||
| 227 | omap3-zoom3.dtb \ | 263 | omap3-zoom3.dtb \ |
| 264 | omap4-duovero-parlor.dtb \ | ||
| 228 | omap4-panda.dtb \ | 265 | omap4-panda.dtb \ |
| 229 | omap4-panda-a4.dtb \ | 266 | omap4-panda-a4.dtb \ |
| 230 | omap4-panda-es.dtb \ | 267 | omap4-panda-es.dtb \ |
| @@ -238,12 +275,17 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ | |||
| 238 | am335x-boneblack.dtb \ | 275 | am335x-boneblack.dtb \ |
| 239 | am335x-nano.dtb \ | 276 | am335x-nano.dtb \ |
| 240 | am335x-base0033.dtb \ | 277 | am335x-base0033.dtb \ |
| 278 | am3517-craneboard.dtb \ | ||
| 241 | am3517-evm.dtb \ | 279 | am3517-evm.dtb \ |
| 242 | am3517_mt_ventoux.dtb \ | 280 | am3517_mt_ventoux.dtb \ |
| 243 | am43x-epos-evm.dtb \ | 281 | am43x-epos-evm.dtb \ |
| 282 | am437x-gp-evm.dtb \ | ||
| 244 | dra7-evm.dtb | 283 | dra7-evm.dtb |
| 245 | dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb | 284 | dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb |
| 246 | dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb | 285 | dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb |
| 286 | dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \ | ||
| 287 | qcom-msm8960-cdp.dtb \ | ||
| 288 | qcom-apq8074-dragonboard.dtb | ||
| 247 | dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \ | 289 | dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \ |
| 248 | ste-hrefprev60-stuib.dtb \ | 290 | ste-hrefprev60-stuib.dtb \ |
| 249 | ste-hrefprev60-tvk.dtb \ | 291 | ste-hrefprev60-tvk.dtb \ |
| @@ -294,6 +336,9 @@ dtb-$(CONFIG_ARCH_SUNXI) += \ | |||
| 294 | sun4i-a10-cubieboard.dtb \ | 336 | sun4i-a10-cubieboard.dtb \ |
| 295 | sun4i-a10-mini-xplus.dtb \ | 337 | sun4i-a10-mini-xplus.dtb \ |
| 296 | sun4i-a10-hackberry.dtb \ | 338 | sun4i-a10-hackberry.dtb \ |
| 339 | sun4i-a10-inet97fv2.dtb \ | ||
| 340 | sun4i-a10-olinuxino-lime.dtb \ | ||
| 341 | sun4i-a10-pcduino.dtb \ | ||
| 297 | sun5i-a10s-olinuxino-micro.dtb \ | 342 | sun5i-a10s-olinuxino-micro.dtb \ |
| 298 | sun5i-a13-olinuxino.dtb \ | 343 | sun5i-a13-olinuxino.dtb \ |
| 299 | sun5i-a13-olinuxino-micro.dtb \ | 344 | sun5i-a13-olinuxino-micro.dtb \ |
| @@ -332,6 +377,29 @@ dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \ | |||
| 332 | dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ | 377 | dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ |
| 333 | zynq-zc706.dtb \ | 378 | zynq-zc706.dtb \ |
| 334 | zynq-zed.dtb | 379 | zynq-zed.dtb |
| 380 | dtb-$(CONFIG_MACH_ARMADA_370) += \ | ||
| 381 | armada-370-db.dtb \ | ||
| 382 | armada-370-mirabox.dtb \ | ||
| 383 | armada-370-netgear-rn102.dtb \ | ||
| 384 | armada-370-netgear-rn104.dtb \ | ||
| 385 | armada-370-rd.dtb | ||
| 386 | dtb-$(CONFIG_MACH_ARMADA_375) += \ | ||
| 387 | armada-375-db.dtb | ||
| 388 | dtb-$(CONFIG_MACH_ARMADA_38X) += \ | ||
| 389 | armada-385-db.dtb \ | ||
| 390 | armada-385-rd.dtb | ||
| 391 | dtb-$(CONFIG_MACH_ARMADA_XP) += \ | ||
| 392 | armada-xp-axpwifiap.dtb \ | ||
| 393 | armada-xp-db.dtb \ | ||
| 394 | armada-xp-gp.dtb \ | ||
| 395 | armada-xp-netgear-rn2120.dtb \ | ||
| 396 | armada-xp-matrix.dtb \ | ||
| 397 | armada-xp-openblocks-ax3-4.dtb | ||
| 398 | dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \ | ||
| 399 | dove-cubox.dtb \ | ||
| 400 | dove-d2plug.dtb \ | ||
| 401 | dove-d3plug.dtb \ | ||
| 402 | dove-dove-db.dtb | ||
| 335 | 403 | ||
| 336 | targets += dtbs | 404 | targets += dtbs |
| 337 | targets += $(dtb-y) | 405 | targets += $(dtb-y) |
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 7e6c64ed966d..28ae040e7c3d 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts | |||
| @@ -260,6 +260,12 @@ | |||
| 260 | >; | 260 | >; |
| 261 | }; | 261 | }; |
| 262 | 262 | ||
| 263 | mmc1_pins: pinmux_mmc1_pins { | ||
| 264 | pinctrl-single,pins = < | ||
| 265 | 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ | ||
| 266 | >; | ||
| 267 | }; | ||
| 268 | |||
| 263 | lcd_pins_s0: lcd_pins_s0 { | 269 | lcd_pins_s0: lcd_pins_s0 { |
| 264 | pinctrl-single,pins = < | 270 | pinctrl-single,pins = < |
| 265 | 0x20 0x01 /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */ | 271 | 0x20 0x01 /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */ |
| @@ -434,9 +440,9 @@ | |||
| 434 | ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ | 440 | ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ |
| 435 | nand@0,0 { | 441 | nand@0,0 { |
| 436 | reg = <0 0 0>; /* CS0, offset 0 */ | 442 | reg = <0 0 0>; /* CS0, offset 0 */ |
| 437 | nand-bus-width = <8>; | ||
| 438 | ti,nand-ecc-opt = "bch8"; | 443 | ti,nand-ecc-opt = "bch8"; |
| 439 | gpmc,device-nand = "true"; | 444 | ti,elm-id = <&elm>; |
| 445 | nand-bus-width = <8>; | ||
| 440 | gpmc,device-width = <1>; | 446 | gpmc,device-width = <1>; |
| 441 | gpmc,sync-clk-ps = <0>; | 447 | gpmc,sync-clk-ps = <0>; |
| 442 | gpmc,cs-on-ns = <0>; | 448 | gpmc,cs-on-ns = <0>; |
| @@ -460,50 +466,51 @@ | |||
| 460 | gpmc,wait-monitoring-ns = <0>; | 466 | gpmc,wait-monitoring-ns = <0>; |
| 461 | gpmc,wr-access-ns = <40>; | 467 | gpmc,wr-access-ns = <40>; |
| 462 | gpmc,wr-data-mux-bus-ns = <0>; | 468 | gpmc,wr-data-mux-bus-ns = <0>; |
| 463 | 469 | /* MTD partition table */ | |
| 470 | /* All SPL-* partitions are sized to minimal length | ||
| 471 | * which can be independently programmable. For | ||
| 472 | * NAND flash this is equal to size of erase-block */ | ||
| 464 | #address-cells = <1>; | 473 | #address-cells = <1>; |
| 465 | #size-cells = <1>; | 474 | #size-cells = <1>; |
| 466 | elm_id = <&elm>; | ||
| 467 | |||
| 468 | /* MTD partition table */ | ||
| 469 | partition@0 { | 475 | partition@0 { |
| 470 | label = "SPL1"; | 476 | label = "NAND.SPL"; |
| 471 | reg = <0x00000000 0x000020000>; | 477 | reg = <0x00000000 0x000020000>; |
| 472 | }; | 478 | }; |
| 473 | |||
| 474 | partition@1 { | 479 | partition@1 { |
| 475 | label = "SPL2"; | 480 | label = "NAND.SPL.backup1"; |
| 476 | reg = <0x00020000 0x00020000>; | 481 | reg = <0x00020000 0x00020000>; |
| 477 | }; | 482 | }; |
| 478 | |||
| 479 | partition@2 { | 483 | partition@2 { |
| 480 | label = "SPL3"; | 484 | label = "NAND.SPL.backup2"; |
| 481 | reg = <0x00040000 0x00020000>; | 485 | reg = <0x00040000 0x00020000>; |
| 482 | }; | 486 | }; |
| 483 | |||
| 484 | partition@3 { | 487 | partition@3 { |
| 485 | label = "SPL4"; | 488 | label = "NAND.SPL.backup3"; |
| 486 | reg = <0x00060000 0x00020000>; | 489 | reg = <0x00060000 0x00020000>; |
| 487 | }; | 490 | }; |
| 488 | |||
| 489 | partition@4 { | 491 | partition@4 { |
| 490 | label = "U-boot"; | 492 | label = "NAND.u-boot-spl"; |
| 491 | reg = <0x00080000 0x001e0000>; | 493 | reg = <0x00080000 0x00040000>; |
| 492 | }; | 494 | }; |
| 493 | |||
| 494 | partition@5 { | 495 | partition@5 { |
| 495 | label = "environment"; | 496 | label = "NAND.u-boot"; |
| 496 | reg = <0x00260000 0x00020000>; | 497 | reg = <0x000C0000 0x00100000>; |
| 497 | }; | 498 | }; |
| 498 | |||
| 499 | partition@6 { | 499 | partition@6 { |
| 500 | label = "Kernel"; | 500 | label = "NAND.u-boot-env"; |
| 501 | reg = <0x00280000 0x00500000>; | 501 | reg = <0x001C0000 0x00020000>; |
| 502 | }; | 502 | }; |
| 503 | |||
| 504 | partition@7 { | 503 | partition@7 { |
| 505 | label = "File-System"; | 504 | label = "NAND.u-boot-env.backup1"; |
| 506 | reg = <0x00780000 0x0F880000>; | 505 | reg = <0x001E0000 0x00020000>; |
| 506 | }; | ||
| 507 | partition@8 { | ||
| 508 | label = "NAND.kernel"; | ||
| 509 | reg = <0x00200000 0x00800000>; | ||
| 510 | }; | ||
| 511 | partition@9 { | ||
| 512 | label = "NAND.file-system"; | ||
| 513 | reg = <0x00A00000 0x0F600000>; | ||
| 507 | }; | 514 | }; |
| 508 | }; | 515 | }; |
| 509 | }; | 516 | }; |
| @@ -643,6 +650,9 @@ | |||
| 643 | status = "okay"; | 650 | status = "okay"; |
| 644 | vmmc-supply = <&vmmc_reg>; | 651 | vmmc-supply = <&vmmc_reg>; |
| 645 | bus-width = <4>; | 652 | bus-width = <4>; |
| 653 | pinctrl-names = "default"; | ||
| 654 | pinctrl-0 = <&mmc1_pins>; | ||
| 655 | cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; | ||
| 646 | }; | 656 | }; |
| 647 | 657 | ||
| 648 | &sham { | 658 | &sham { |
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index 486880b74831..ec08f6f677c3 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts | |||
| @@ -45,6 +45,18 @@ | |||
| 45 | regulator-boot-on; | 45 | regulator-boot-on; |
| 46 | }; | 46 | }; |
| 47 | 47 | ||
| 48 | wl12xx_vmmc: fixedregulator@2 { | ||
| 49 | pinctrl-names = "default"; | ||
| 50 | pinctrl-0 = <&wl12xx_gpio>; | ||
| 51 | compatible = "regulator-fixed"; | ||
| 52 | regulator-name = "vwl1271"; | ||
| 53 | regulator-min-microvolt = <1800000>; | ||
| 54 | regulator-max-microvolt = <1800000>; | ||
| 55 | gpio = <&gpio1 29 0>; | ||
| 56 | startup-delay-us = <70000>; | ||
| 57 | enable-active-high; | ||
| 58 | }; | ||
| 59 | |||
| 48 | leds { | 60 | leds { |
| 49 | pinctrl-names = "default"; | 61 | pinctrl-names = "default"; |
| 50 | pinctrl-0 = <&user_leds_s0>; | 62 | pinctrl-0 = <&user_leds_s0>; |
| @@ -270,6 +282,24 @@ | |||
| 270 | 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ | 282 | 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ |
| 271 | >; | 283 | >; |
| 272 | }; | 284 | }; |
| 285 | |||
| 286 | mmc2_pins: pinmux_mmc2_pins { | ||
| 287 | pinctrl-single,pins = < | ||
| 288 | 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */ | ||
| 289 | 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ | ||
| 290 | 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ | ||
| 291 | 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ | ||
| 292 | 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ | ||
| 293 | 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ | ||
| 294 | 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ | ||
| 295 | >; | ||
| 296 | }; | ||
| 297 | |||
| 298 | wl12xx_gpio: pinmux_wl12xx_gpio { | ||
| 299 | pinctrl-single,pins = < | ||
| 300 | 0x7c (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_csn0.gpio1_29 */ | ||
| 301 | >; | ||
| 302 | }; | ||
| 273 | }; | 303 | }; |
| 274 | 304 | ||
| 275 | &uart0 { | 305 | &uart0 { |
| @@ -342,9 +372,22 @@ | |||
| 342 | status = "okay"; | 372 | status = "okay"; |
| 343 | }; | 373 | }; |
| 344 | 374 | ||
| 375 | usb-phy@47401b00 { | ||
| 376 | status = "okay"; | ||
| 377 | }; | ||
| 378 | |||
| 345 | usb@47401000 { | 379 | usb@47401000 { |
| 346 | status = "okay"; | 380 | status = "okay"; |
| 347 | }; | 381 | }; |
| 382 | |||
| 383 | usb@47401800 { | ||
| 384 | status = "okay"; | ||
| 385 | dr_mode = "host"; | ||
| 386 | }; | ||
| 387 | |||
| 388 | dma-controller@07402000 { | ||
| 389 | status = "okay"; | ||
| 390 | }; | ||
| 348 | }; | 391 | }; |
| 349 | 392 | ||
| 350 | &epwmss2 { | 393 | &epwmss2 { |
| @@ -440,6 +483,7 @@ | |||
| 440 | pinctrl-names = "default", "sleep"; | 483 | pinctrl-names = "default", "sleep"; |
| 441 | pinctrl-0 = <&cpsw_default>; | 484 | pinctrl-0 = <&cpsw_default>; |
| 442 | pinctrl-1 = <&cpsw_sleep>; | 485 | pinctrl-1 = <&cpsw_sleep>; |
| 486 | dual_emac = <1>; | ||
| 443 | }; | 487 | }; |
| 444 | 488 | ||
| 445 | &davinci_mdio { | 489 | &davinci_mdio { |
| @@ -451,11 +495,13 @@ | |||
| 451 | &cpsw_emac0 { | 495 | &cpsw_emac0 { |
| 452 | phy_id = <&davinci_mdio>, <0>; | 496 | phy_id = <&davinci_mdio>, <0>; |
| 453 | phy-mode = "rgmii-txid"; | 497 | phy-mode = "rgmii-txid"; |
| 498 | dual_emac_res_vlan = <1>; | ||
| 454 | }; | 499 | }; |
| 455 | 500 | ||
| 456 | &cpsw_emac1 { | 501 | &cpsw_emac1 { |
| 457 | phy_id = <&davinci_mdio>, <1>; | 502 | phy_id = <&davinci_mdio>, <1>; |
| 458 | phy-mode = "rgmii-txid"; | 503 | phy-mode = "rgmii-txid"; |
| 504 | dual_emac_res_vlan = <2>; | ||
| 459 | }; | 505 | }; |
| 460 | 506 | ||
| 461 | &mmc1 { | 507 | &mmc1 { |
| @@ -479,6 +525,16 @@ | |||
| 479 | ti,no-reset-on-init; | 525 | ti,no-reset-on-init; |
| 480 | }; | 526 | }; |
| 481 | 527 | ||
| 528 | &mmc2 { | ||
| 529 | status = "okay"; | ||
| 530 | vmmc-supply = <&wl12xx_vmmc>; | ||
| 531 | ti,non-removable; | ||
| 532 | bus-width = <4>; | ||
| 533 | cap-power-off-card; | ||
| 534 | pinctrl-names = "default"; | ||
| 535 | pinctrl-0 = <&mmc2_pins>; | ||
| 536 | }; | ||
| 537 | |||
| 482 | &mcasp1 { | 538 | &mcasp1 { |
| 483 | pinctrl-names = "default"; | 539 | pinctrl-names = "default"; |
| 484 | pinctrl-0 = <&mcasp1_pins>; | 540 | pinctrl-0 = <&mcasp1_pins>; |
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 6d95d3df33c7..707342914a6f 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi | |||
| @@ -58,6 +58,10 @@ | |||
| 58 | 275000 1125000 | 58 | 275000 1125000 |
| 59 | >; | 59 | >; |
| 60 | voltage-tolerance = <2>; /* 2 percentage */ | 60 | voltage-tolerance = <2>; /* 2 percentage */ |
| 61 | |||
| 62 | clocks = <&dpll_mpu_ck>; | ||
| 63 | clock-names = "cpu"; | ||
| 64 | |||
| 61 | clock-latency = <300000>; /* From omap-cpufreq driver */ | 65 | clock-latency = <300000>; /* From omap-cpufreq driver */ |
| 62 | }; | 66 | }; |
| 63 | }; | 67 | }; |
| @@ -318,6 +322,7 @@ | |||
| 318 | compatible = "ti,omap4-hwspinlock"; | 322 | compatible = "ti,omap4-hwspinlock"; |
| 319 | reg = <0x480ca000 0x1000>; | 323 | reg = <0x480ca000 0x1000>; |
| 320 | ti,hwmods = "spinlock"; | 324 | ti,hwmods = "spinlock"; |
| 325 | #hwlock-cells = <1>; | ||
| 321 | }; | 326 | }; |
| 322 | 327 | ||
| 323 | wdt2: wdt@44e35000 { | 328 | wdt2: wdt@44e35000 { |
| @@ -399,7 +404,7 @@ | |||
| 399 | ti,timer-pwm; | 404 | ti,timer-pwm; |
| 400 | }; | 405 | }; |
| 401 | 406 | ||
| 402 | rtc@44e3e000 { | 407 | rtc: rtc@44e3e000 { |
| 403 | compatible = "ti,da830-rtc"; | 408 | compatible = "ti,da830-rtc"; |
| 404 | reg = <0x44e3e000 0x1000>; | 409 | reg = <0x44e3e000 0x1000>; |
| 405 | interrupts = <75 | 410 | interrupts = <75 |
| @@ -582,6 +587,8 @@ | |||
| 582 | compatible = "ti,am33xx-ecap"; | 587 | compatible = "ti,am33xx-ecap"; |
| 583 | #pwm-cells = <3>; | 588 | #pwm-cells = <3>; |
| 584 | reg = <0x48300100 0x80>; | 589 | reg = <0x48300100 0x80>; |
| 590 | interrupts = <31>; | ||
| 591 | interrupt-names = "ecap0"; | ||
| 585 | ti,hwmods = "ecap0"; | 592 | ti,hwmods = "ecap0"; |
| 586 | status = "disabled"; | 593 | status = "disabled"; |
| 587 | }; | 594 | }; |
| @@ -610,6 +617,8 @@ | |||
| 610 | compatible = "ti,am33xx-ecap"; | 617 | compatible = "ti,am33xx-ecap"; |
| 611 | #pwm-cells = <3>; | 618 | #pwm-cells = <3>; |
| 612 | reg = <0x48302100 0x80>; | 619 | reg = <0x48302100 0x80>; |
| 620 | interrupts = <47>; | ||
| 621 | interrupt-names = "ecap1"; | ||
| 613 | ti,hwmods = "ecap1"; | 622 | ti,hwmods = "ecap1"; |
| 614 | status = "disabled"; | 623 | status = "disabled"; |
| 615 | }; | 624 | }; |
| @@ -638,6 +647,8 @@ | |||
| 638 | compatible = "ti,am33xx-ecap"; | 647 | compatible = "ti,am33xx-ecap"; |
| 639 | #pwm-cells = <3>; | 648 | #pwm-cells = <3>; |
| 640 | reg = <0x48304100 0x80>; | 649 | reg = <0x48304100 0x80>; |
| 650 | interrupts = <61>; | ||
| 651 | interrupt-names = "ecap2"; | ||
| 641 | ti,hwmods = "ecap2"; | 652 | ti,hwmods = "ecap2"; |
| 642 | status = "disabled"; | 653 | status = "disabled"; |
| 643 | }; | 654 | }; |
diff --git a/arch/arm/boot/dts/am3517-craneboard.dts b/arch/arm/boot/dts/am3517-craneboard.dts new file mode 100644 index 000000000000..2d40b3f241cd --- /dev/null +++ b/arch/arm/boot/dts/am3517-craneboard.dts | |||
| @@ -0,0 +1,174 @@ | |||
| 1 | /* | ||
| 2 | * See craneboard.org for more details | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | /dts-v1/; | ||
| 11 | |||
| 12 | #include "am3517.dtsi" | ||
| 13 | |||
| 14 | / { | ||
| 15 | model = "TI AM3517 CraneBoard (TMDSEVM3517)"; | ||
| 16 | compatible = "ti,am3517-craneboard", "ti,am3517", "ti,omap3"; | ||
| 17 | |||
| 18 | memory { | ||
| 19 | device_type = "memory"; | ||
| 20 | reg = <0x80000000 0x10000000>; /* 256 MB */ | ||
| 21 | }; | ||
| 22 | |||
| 23 | vbat: fixedregulator@0 { | ||
| 24 | compatible = "regulator-fixed"; | ||
| 25 | regulator-name = "vbat"; | ||
| 26 | regulator-min-microvolt = <5000000>; | ||
| 27 | regulator-max-microvolt = <5000000>; | ||
| 28 | regulator-boot-on; | ||
| 29 | }; | ||
| 30 | }; | ||
| 31 | |||
| 32 | &davinci_emac { | ||
| 33 | status = "okay"; | ||
| 34 | }; | ||
| 35 | |||
| 36 | &davinci_mdio { | ||
| 37 | status = "okay"; | ||
| 38 | }; | ||
| 39 | |||
| 40 | &i2c1 { | ||
| 41 | clock-frequency = <2600000>; | ||
| 42 | |||
| 43 | tps: tps@2d { | ||
| 44 | reg = <0x2d>; | ||
| 45 | }; | ||
| 46 | }; | ||
| 47 | |||
| 48 | &i2c2 { | ||
| 49 | clock-frequency = <400000>; | ||
| 50 | /* goes to expansion connector */ | ||
| 51 | status = "disabled"; | ||
| 52 | }; | ||
| 53 | |||
| 54 | &i2c3 { | ||
| 55 | clock-frequency = <400000>; | ||
| 56 | /* goes to expansion connector */ | ||
| 57 | status = "disabled"; | ||
| 58 | }; | ||
| 59 | |||
| 60 | &mmc1 { | ||
| 61 | vmmc-supply = <&vdd2_reg>; | ||
| 62 | bus-width = <8>; | ||
| 63 | }; | ||
| 64 | |||
| 65 | &mmc2 { | ||
| 66 | /* goes to expansion connector */ | ||
| 67 | status = "disabled"; | ||
| 68 | }; | ||
| 69 | |||
| 70 | &mmc3 { | ||
| 71 | /* goes to expansion connector */ | ||
| 72 | status = "disabled"; | ||
| 73 | }; | ||
| 74 | |||
| 75 | #include "tps65910.dtsi" | ||
| 76 | |||
| 77 | &omap3_pmx_core { | ||
| 78 | tps_pins: pinmux_tps_pins { | ||
| 79 | pinctrl-single,pins = < | ||
| 80 | 0x1b0 (PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq.sys_nirq */ | ||
| 81 | >; | ||
| 82 | }; | ||
| 83 | }; | ||
| 84 | |||
| 85 | &tps { | ||
| 86 | pinctrl-names = "default"; | ||
| 87 | pinctrl-0 = <&tps_pins>; | ||
| 88 | |||
| 89 | interrupts = <7>; /* SYS_NIRQ cascaded to intc */ | ||
| 90 | interrupt-parent = <&intc>; | ||
| 91 | |||
| 92 | ti,en-ck32k-xtal; | ||
| 93 | |||
| 94 | vcc1-supply = <&vbat>; | ||
| 95 | vcc2-supply = <&vbat>; | ||
| 96 | vcc3-supply = <&vbat>; | ||
| 97 | vcc4-supply = <&vbat>; | ||
| 98 | vcc5-supply = <&vbat>; | ||
| 99 | vcc6-supply = <&vbat>; | ||
| 100 | vcc7-supply = <&vbat>; | ||
| 101 | vccio-supply = <&vbat>; | ||
| 102 | |||
| 103 | regulators { | ||
| 104 | vrtc_reg: regulator@0 { | ||
| 105 | regulator-always-on; | ||
| 106 | }; | ||
| 107 | |||
| 108 | vio_reg: regulator@1 { | ||
| 109 | regulator-always-on; | ||
| 110 | }; | ||
| 111 | |||
| 112 | /* | ||
| 113 | * Unused: | ||
| 114 | * VDIG1=2.7V,300mA max | ||
| 115 | * VDIG2=1.8V,300mA max | ||
| 116 | */ | ||
| 117 | |||
| 118 | vpll_reg: regulator@7 { | ||
| 119 | /* VDDS_DPLL_1V8 */ | ||
| 120 | regulator-min-microvolt = <1800000>; | ||
| 121 | regulator-max-microvolt = <1800000>; | ||
| 122 | regulator-always-on; | ||
| 123 | }; | ||
| 124 | |||
| 125 | vaux1_reg: regulator@9 { | ||
| 126 | /* VDDS_SRAM_1V8 */ | ||
| 127 | regulator-min-microvolt = <1800000>; | ||
| 128 | regulator-max-microvolt = <1800000>; | ||
| 129 | regulator-always-on; | ||
| 130 | }; | ||
| 131 | |||
| 132 | vaux2_reg: regulator@10 { | ||
| 133 | /* VDDA1P8V_USBPHY */ | ||
| 134 | regulator-min-microvolt = <1800000>; | ||
| 135 | regulator-max-microvolt = <1800000>; | ||
| 136 | regulator-always-on; | ||
| 137 | }; | ||
| 138 | |||
| 139 | /* VAUX33 unused */ | ||
| 140 | |||
| 141 | vdac_reg: regulator@8 { | ||
| 142 | /* VDDA_DAC_1V8 */ | ||
| 143 | regulator-min-microvolt = <1800000>; | ||
| 144 | regulator-max-microvolt = <1800000>; | ||
| 145 | regulator-always-on; | ||
| 146 | }; | ||
| 147 | |||
| 148 | vmmc_reg: regulator@12 { | ||
| 149 | /* VDDA3P3V_USBPHY */ | ||
| 150 | regulator-min-microvolt = <3300000>; | ||
| 151 | regulator-max-microvolt = <3300000>; | ||
| 152 | regulator-always-on; | ||
| 153 | }; | ||
| 154 | |||
| 155 | vdd1_reg: regulator@2 { | ||
| 156 | /* VDD_CORE */ | ||
| 157 | regulator-name = "vdd_core"; | ||
| 158 | regulator-min-microvolt = <1200000>; | ||
| 159 | regulator-max-microvolt = <1200000>; | ||
| 160 | regulator-boot-on; | ||
| 161 | regulator-always-on; | ||
| 162 | }; | ||
| 163 | |||
| 164 | vdd2_reg: regulator@3 { | ||
| 165 | /* VDDSHV_3V3 */ | ||
| 166 | regulator-name = "vdd_shv"; | ||
| 167 | regulator-min-microvolt = <3300000>; | ||
| 168 | regulator-max-microvolt = <3300000>; | ||
| 169 | regulator-always-on; | ||
| 170 | }; | ||
| 171 | |||
| 172 | /* VDD3 unused */ | ||
| 173 | }; | ||
| 174 | }; | ||
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index c6bd4d986c29..36d523a26831 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi | |||
| @@ -8,6 +8,7 @@ | |||
| 8 | * kind, whether express or implied. | 8 | * kind, whether express or implied. |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | #include <dt-bindings/gpio/gpio.h> | ||
| 11 | #include <dt-bindings/interrupt-controller/arm-gic.h> | 12 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 12 | 13 | ||
| 13 | #include "skeleton.dtsi" | 14 | #include "skeleton.dtsi" |
| @@ -33,6 +34,11 @@ | |||
| 33 | compatible = "arm,cortex-a9"; | 34 | compatible = "arm,cortex-a9"; |
| 34 | device_type = "cpu"; | 35 | device_type = "cpu"; |
| 35 | reg = <0>; | 36 | reg = <0>; |
| 37 | |||
| 38 | clocks = <&dpll_mpu_ck>; | ||
| 39 | clock-names = "cpu"; | ||
| 40 | |||
| 41 | clock-latency = <300000>; /* From omap-cpufreq driver */ | ||
| 36 | }; | 42 | }; |
| 37 | }; | 43 | }; |
| 38 | 44 | ||
| @@ -351,6 +357,13 @@ | |||
| 351 | status = "disabled"; | 357 | status = "disabled"; |
| 352 | }; | 358 | }; |
| 353 | 359 | ||
| 360 | hwspinlock: spinlock@480ca000 { | ||
| 361 | compatible = "ti,omap4-hwspinlock"; | ||
| 362 | reg = <0x480ca000 0x1000>; | ||
| 363 | ti,hwmods = "spinlock"; | ||
| 364 | #hwlock-cells = <1>; | ||
| 365 | }; | ||
| 366 | |||
| 354 | i2c0: i2c@44e0b000 { | 367 | i2c0: i2c@44e0b000 { |
| 355 | compatible = "ti,am4372-i2c","ti,omap4-i2c"; | 368 | compatible = "ti,am4372-i2c","ti,omap4-i2c"; |
| 356 | reg = <0x44e0b000 0x1000>; | 369 | reg = <0x44e0b000 0x1000>; |
| @@ -521,6 +534,7 @@ | |||
| 521 | 534 | ||
| 522 | ecap0: ecap@48300100 { | 535 | ecap0: ecap@48300100 { |
| 523 | compatible = "ti,am4372-ecap","ti,am33xx-ecap"; | 536 | compatible = "ti,am4372-ecap","ti,am33xx-ecap"; |
| 537 | #pwm-cells = <3>; | ||
| 524 | reg = <0x48300100 0x80>; | 538 | reg = <0x48300100 0x80>; |
| 525 | ti,hwmods = "ecap0"; | 539 | ti,hwmods = "ecap0"; |
| 526 | status = "disabled"; | 540 | status = "disabled"; |
| @@ -528,6 +542,7 @@ | |||
| 528 | 542 | ||
| 529 | ehrpwm0: ehrpwm@48300200 { | 543 | ehrpwm0: ehrpwm@48300200 { |
| 530 | compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; | 544 | compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; |
| 545 | #pwm-cells = <3>; | ||
| 531 | reg = <0x48300200 0x80>; | 546 | reg = <0x48300200 0x80>; |
| 532 | ti,hwmods = "ehrpwm0"; | 547 | ti,hwmods = "ehrpwm0"; |
| 533 | status = "disabled"; | 548 | status = "disabled"; |
| @@ -545,6 +560,7 @@ | |||
| 545 | 560 | ||
| 546 | ecap1: ecap@48302100 { | 561 | ecap1: ecap@48302100 { |
| 547 | compatible = "ti,am4372-ecap","ti,am33xx-ecap"; | 562 | compatible = "ti,am4372-ecap","ti,am33xx-ecap"; |
| 563 | #pwm-cells = <3>; | ||
| 548 | reg = <0x48302100 0x80>; | 564 | reg = <0x48302100 0x80>; |
| 549 | ti,hwmods = "ecap1"; | 565 | ti,hwmods = "ecap1"; |
| 550 | status = "disabled"; | 566 | status = "disabled"; |
| @@ -552,6 +568,7 @@ | |||
| 552 | 568 | ||
| 553 | ehrpwm1: ehrpwm@48302200 { | 569 | ehrpwm1: ehrpwm@48302200 { |
| 554 | compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; | 570 | compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; |
| 571 | #pwm-cells = <3>; | ||
| 555 | reg = <0x48302200 0x80>; | 572 | reg = <0x48302200 0x80>; |
| 556 | ti,hwmods = "ehrpwm1"; | 573 | ti,hwmods = "ehrpwm1"; |
| 557 | status = "disabled"; | 574 | status = "disabled"; |
| @@ -569,6 +586,7 @@ | |||
| 569 | 586 | ||
| 570 | ecap2: ecap@48304100 { | 587 | ecap2: ecap@48304100 { |
| 571 | compatible = "ti,am4372-ecap","ti,am33xx-ecap"; | 588 | compatible = "ti,am4372-ecap","ti,am33xx-ecap"; |
| 589 | #pwm-cells = <3>; | ||
| 572 | reg = <0x48304100 0x80>; | 590 | reg = <0x48304100 0x80>; |
| 573 | ti,hwmods = "ecap2"; | 591 | ti,hwmods = "ecap2"; |
| 574 | status = "disabled"; | 592 | status = "disabled"; |
| @@ -576,6 +594,7 @@ | |||
| 576 | 594 | ||
| 577 | ehrpwm2: ehrpwm@48304200 { | 595 | ehrpwm2: ehrpwm@48304200 { |
| 578 | compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; | 596 | compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; |
| 597 | #pwm-cells = <3>; | ||
| 579 | reg = <0x48304200 0x80>; | 598 | reg = <0x48304200 0x80>; |
| 580 | ti,hwmods = "ehrpwm2"; | 599 | ti,hwmods = "ehrpwm2"; |
| 581 | status = "disabled"; | 600 | status = "disabled"; |
| @@ -593,6 +612,7 @@ | |||
| 593 | 612 | ||
| 594 | ehrpwm3: ehrpwm@48306200 { | 613 | ehrpwm3: ehrpwm@48306200 { |
| 595 | compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; | 614 | compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; |
| 615 | #pwm-cells = <3>; | ||
| 596 | reg = <0x48306200 0x80>; | 616 | reg = <0x48306200 0x80>; |
| 597 | ti,hwmods = "ehrpwm3"; | 617 | ti,hwmods = "ehrpwm3"; |
| 598 | status = "disabled"; | 618 | status = "disabled"; |
| @@ -610,6 +630,7 @@ | |||
| 610 | 630 | ||
| 611 | ehrpwm4: ehrpwm@48308200 { | 631 | ehrpwm4: ehrpwm@48308200 { |
| 612 | compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; | 632 | compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; |
| 633 | #pwm-cells = <3>; | ||
| 613 | reg = <0x48308200 0x80>; | 634 | reg = <0x48308200 0x80>; |
| 614 | ti,hwmods = "ehrpwm4"; | 635 | ti,hwmods = "ehrpwm4"; |
| 615 | status = "disabled"; | 636 | status = "disabled"; |
| @@ -627,6 +648,7 @@ | |||
| 627 | 648 | ||
| 628 | ehrpwm5: ehrpwm@4830a200 { | 649 | ehrpwm5: ehrpwm@4830a200 { |
| 629 | compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; | 650 | compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; |
| 651 | #pwm-cells = <3>; | ||
| 630 | reg = <0x4830a200 0x80>; | 652 | reg = <0x4830a200 0x80>; |
| 631 | ti,hwmods = "ehrpwm5"; | 653 | ti,hwmods = "ehrpwm5"; |
| 632 | status = "disabled"; | 654 | status = "disabled"; |
| @@ -689,6 +711,30 @@ | |||
| 689 | <&edma 11>; | 711 | <&edma 11>; |
| 690 | dma-names = "tx", "rx"; | 712 | dma-names = "tx", "rx"; |
| 691 | }; | 713 | }; |
| 714 | |||
| 715 | elm: elm@48080000 { | ||
| 716 | compatible = "ti,am3352-elm"; | ||
| 717 | reg = <0x48080000 0x2000>; | ||
| 718 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; | ||
| 719 | ti,hwmods = "elm"; | ||
| 720 | clocks = <&l4ls_gclk>; | ||
| 721 | clock-names = "fck"; | ||
| 722 | status = "disabled"; | ||
| 723 | }; | ||
| 724 | |||
| 725 | gpmc: gpmc@50000000 { | ||
| 726 | compatible = "ti,am3352-gpmc"; | ||
| 727 | ti,hwmods = "gpmc"; | ||
| 728 | clocks = <&l3s_gclk>; | ||
| 729 | clock-names = "fck"; | ||
| 730 | reg = <0x50000000 0x2000>; | ||
| 731 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; | ||
| 732 | gpmc,num-cs = <7>; | ||
| 733 | gpmc,num-waitpins = <2>; | ||
| 734 | #address-cells = <2>; | ||
| 735 | #size-cells = <1>; | ||
| 736 | status = "disabled"; | ||
| 737 | }; | ||
| 692 | }; | 738 | }; |
| 693 | }; | 739 | }; |
| 694 | 740 | ||
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts new file mode 100644 index 000000000000..df8798e8bd25 --- /dev/null +++ b/arch/arm/boot/dts/am437x-gp-evm.dts | |||
| @@ -0,0 +1,127 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | /* AM437x GP EVM */ | ||
| 10 | |||
| 11 | /dts-v1/; | ||
| 12 | |||
| 13 | #include "am4372.dtsi" | ||
| 14 | #include <dt-bindings/pinctrl/am43xx.h> | ||
| 15 | #include <dt-bindings/pwm/pwm.h> | ||
| 16 | #include <dt-bindings/gpio/gpio.h> | ||
| 17 | |||
| 18 | / { | ||
| 19 | model = "TI AM437x GP EVM"; | ||
| 20 | compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43"; | ||
| 21 | |||
| 22 | vmmcsd_fixed: fixedregulator-sd { | ||
| 23 | compatible = "regulator-fixed"; | ||
| 24 | regulator-name = "vmmcsd_fixed"; | ||
| 25 | regulator-min-microvolt = <3300000>; | ||
| 26 | regulator-max-microvolt = <3300000>; | ||
| 27 | enable-active-high; | ||
| 28 | }; | ||
| 29 | |||
| 30 | backlight { | ||
| 31 | compatible = "pwm-backlight"; | ||
| 32 | pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; | ||
| 33 | brightness-levels = <0 51 53 56 62 75 101 152 255>; | ||
| 34 | default-brightness-level = <8>; | ||
| 35 | }; | ||
| 36 | |||
| 37 | matrix_keypad: matrix_keypad@0 { | ||
| 38 | compatible = "gpio-matrix-keypad"; | ||
| 39 | debounce-delay-ms = <5>; | ||
| 40 | col-scan-delay-us = <2>; | ||
| 41 | |||
| 42 | row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */ | ||
| 43 | &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */ | ||
| 44 | &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */ | ||
| 45 | |||
| 46 | col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */ | ||
| 47 | &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */ | ||
| 48 | |||
| 49 | linux,keymap = <0x00000201 /* P1 */ | ||
| 50 | 0x00010202 /* P2 */ | ||
| 51 | 0x01000067 /* UP */ | ||
| 52 | 0x0101006a /* RIGHT */ | ||
| 53 | 0x02000069 /* LEFT */ | ||
| 54 | 0x0201006c>; /* DOWN */ | ||
| 55 | }; | ||
| 56 | }; | ||
| 57 | |||
| 58 | &am43xx_pinmux { | ||
| 59 | i2c0_pins: i2c0_pins { | ||
| 60 | pinctrl-single,pins = < | ||
| 61 | 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ | ||
| 62 | 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ | ||
| 63 | >; | ||
| 64 | }; | ||
| 65 | |||
| 66 | i2c1_pins: i2c1_pins { | ||
| 67 | pinctrl-single,pins = < | ||
| 68 | 0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ | ||
| 69 | 0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ | ||
| 70 | >; | ||
| 71 | }; | ||
| 72 | |||
| 73 | mmc1_pins: pinmux_mmc1_pins { | ||
| 74 | pinctrl-single,pins = < | ||
| 75 | 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ | ||
| 76 | >; | ||
| 77 | }; | ||
| 78 | |||
| 79 | ecap0_pins: backlight_pins { | ||
| 80 | pinctrl-single,pins = < | ||
| 81 | 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ | ||
| 82 | >; | ||
| 83 | }; | ||
| 84 | }; | ||
| 85 | |||
| 86 | &i2c0 { | ||
| 87 | status = "okay"; | ||
| 88 | pinctrl-names = "default"; | ||
| 89 | pinctrl-0 = <&i2c0_pins>; | ||
| 90 | }; | ||
| 91 | |||
| 92 | &i2c1 { | ||
| 93 | status = "okay"; | ||
| 94 | pinctrl-names = "default"; | ||
| 95 | pinctrl-0 = <&i2c1_pins>; | ||
| 96 | }; | ||
| 97 | |||
| 98 | &epwmss0 { | ||
| 99 | status = "okay"; | ||
| 100 | }; | ||
| 101 | |||
| 102 | &ecap0 { | ||
| 103 | status = "okay"; | ||
| 104 | pinctrl-names = "default"; | ||
| 105 | pinctrl-0 = <&ecap0_pins>; | ||
| 106 | }; | ||
| 107 | |||
| 108 | &gpio0 { | ||
| 109 | status = "okay"; | ||
| 110 | }; | ||
| 111 | |||
| 112 | &gpio3 { | ||
| 113 | status = "okay"; | ||
| 114 | }; | ||
| 115 | |||
| 116 | &gpio4 { | ||
| 117 | status = "okay"; | ||
| 118 | }; | ||
| 119 | |||
| 120 | &mmc1 { | ||
| 121 | status = "okay"; | ||
| 122 | vmmc-supply = <&vmmcsd_fixed>; | ||
| 123 | bus-width = <4>; | ||
| 124 | pinctrl-names = "default"; | ||
| 125 | pinctrl-0 = <&mmc1_pins>; | ||
| 126 | cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; | ||
| 127 | }; | ||
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index fbf9c4c7a94f..167dbc8494de 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts | |||
| @@ -13,6 +13,7 @@ | |||
| 13 | #include "am4372.dtsi" | 13 | #include "am4372.dtsi" |
| 14 | #include <dt-bindings/pinctrl/am43xx.h> | 14 | #include <dt-bindings/pinctrl/am43xx.h> |
| 15 | #include <dt-bindings/gpio/gpio.h> | 15 | #include <dt-bindings/gpio/gpio.h> |
| 16 | #include <dt-bindings/pwm/pwm.h> | ||
| 16 | 17 | ||
| 17 | / { | 18 | / { |
| 18 | model = "TI AM43x EPOS EVM"; | 19 | model = "TI AM43x EPOS EVM"; |
| @@ -79,6 +80,64 @@ | |||
| 79 | 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ | 80 | 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ |
| 80 | >; | 81 | >; |
| 81 | }; | 82 | }; |
| 83 | |||
| 84 | nand_flash_x8: nand_flash_x8 { | ||
| 85 | pinctrl-single,pins = < | ||
| 86 | 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */ | ||
| 87 | 0x0 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ | ||
| 88 | 0x4 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ | ||
| 89 | 0x8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ | ||
| 90 | 0xc (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ | ||
| 91 | 0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ | ||
| 92 | 0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ | ||
| 93 | 0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ | ||
| 94 | 0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ | ||
| 95 | 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ | ||
| 96 | 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ | ||
| 97 | 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ | ||
| 98 | 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ | ||
| 99 | 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ | ||
| 100 | 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ | ||
| 101 | 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ | ||
| 102 | >; | ||
| 103 | }; | ||
| 104 | |||
| 105 | ecap0_pins: backlight_pins { | ||
| 106 | pinctrl-single,pins = < | ||
| 107 | 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ | ||
| 108 | >; | ||
| 109 | }; | ||
| 110 | |||
| 111 | i2c2_pins: pinmux_i2c2_pins { | ||
| 112 | pinctrl-single,pins = < | ||
| 113 | 0x1c0 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */ | ||
| 114 | 0x1c4 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */ | ||
| 115 | >; | ||
| 116 | }; | ||
| 117 | |||
| 118 | spi0_pins: pinmux_spi0_pins { | ||
| 119 | pinctrl-single,pins = < | ||
| 120 | 0x150 (PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */ | ||
| 121 | 0x154 (PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ | ||
| 122 | 0x158 (PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */ | ||
| 123 | 0x15c (PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ | ||
| 124 | >; | ||
| 125 | }; | ||
| 126 | |||
| 127 | spi1_pins: pinmux_spi1_pins { | ||
| 128 | pinctrl-single,pins = < | ||
| 129 | 0x190 (PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */ | ||
| 130 | 0x194 (PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ | ||
| 131 | 0x198 (PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ | ||
| 132 | 0x19c (PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ | ||
| 133 | >; | ||
| 134 | }; | ||
| 135 | |||
| 136 | mmc1_pins: pinmux_mmc1_pins { | ||
| 137 | pinctrl-single,pins = < | ||
| 138 | 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ | ||
| 139 | >; | ||
| 140 | }; | ||
| 82 | }; | 141 | }; |
| 83 | 142 | ||
| 84 | matrix_keypad: matrix_keypad@0 { | 143 | matrix_keypad: matrix_keypad@0 { |
| @@ -113,12 +172,22 @@ | |||
| 113 | 0x0203006c /* DOWN */ | 172 | 0x0203006c /* DOWN */ |
| 114 | 0x03030069>; /* LEFT */ | 173 | 0x03030069>; /* LEFT */ |
| 115 | }; | 174 | }; |
| 175 | |||
| 176 | backlight { | ||
| 177 | compatible = "pwm-backlight"; | ||
| 178 | pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; | ||
| 179 | brightness-levels = <0 51 53 56 62 75 101 152 255>; | ||
| 180 | default-brightness-level = <8>; | ||
| 181 | }; | ||
| 116 | }; | 182 | }; |
| 117 | 183 | ||
| 118 | &mmc1 { | 184 | &mmc1 { |
| 119 | status = "okay"; | 185 | status = "okay"; |
| 120 | vmmc-supply = <&vmmcsd_fixed>; | 186 | vmmc-supply = <&vmmcsd_fixed>; |
| 121 | bus-width = <4>; | 187 | bus-width = <4>; |
| 188 | pinctrl-names = "default"; | ||
| 189 | pinctrl-0 = <&mmc1_pins>; | ||
| 190 | cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; | ||
| 122 | }; | 191 | }; |
| 123 | 192 | ||
| 124 | &mac { | 193 | &mac { |
| @@ -169,6 +238,12 @@ | |||
| 169 | }; | 238 | }; |
| 170 | }; | 239 | }; |
| 171 | 240 | ||
| 241 | &i2c2 { | ||
| 242 | pinctrl-names = "default"; | ||
| 243 | pinctrl-0 = <&i2c2_pins>; | ||
| 244 | status = "okay"; | ||
| 245 | }; | ||
| 246 | |||
| 172 | &gpio0 { | 247 | &gpio0 { |
| 173 | status = "okay"; | 248 | status = "okay"; |
| 174 | }; | 249 | }; |
| @@ -184,3 +259,111 @@ | |||
| 184 | &gpio3 { | 259 | &gpio3 { |
| 185 | status = "okay"; | 260 | status = "okay"; |
| 186 | }; | 261 | }; |
| 262 | |||
| 263 | &elm { | ||
| 264 | status = "okay"; | ||
| 265 | }; | ||
| 266 | |||
| 267 | &gpmc { | ||
| 268 | status = "okay"; | ||
| 269 | pinctrl-names = "default"; | ||
| 270 | pinctrl-0 = <&nand_flash_x8>; | ||
| 271 | ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ | ||
| 272 | nand@0,0 { | ||
| 273 | reg = <0 0 0>; /* CS0, offset 0 */ | ||
| 274 | ti,nand-ecc-opt = "bch8"; | ||
| 275 | ti,elm-id = <&elm>; | ||
| 276 | nand-bus-width = <8>; | ||
| 277 | gpmc,device-width = <1>; | ||
| 278 | gpmc,sync-clk-ps = <0>; | ||
| 279 | gpmc,cs-on-ns = <0>; | ||
| 280 | gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */ | ||
| 281 | gpmc,cs-wr-off-ns = <40>; | ||
| 282 | gpmc,adv-on-ns = <0>; /* cs-on-ns */ | ||
| 283 | gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */ | ||
| 284 | gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */ | ||
| 285 | gpmc,we-on-ns = <0>; /* cs-on-ns */ | ||
| 286 | gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */ | ||
| 287 | gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */ | ||
| 288 | gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */ | ||
| 289 | gpmc,access-ns = <30>; /* tCEA + 4*/ | ||
| 290 | gpmc,rd-cycle-ns = <40>; | ||
| 291 | gpmc,wr-cycle-ns = <40>; | ||
| 292 | gpmc,wait-on-read = "true"; | ||
| 293 | gpmc,wait-on-write = "true"; | ||
| 294 | gpmc,bus-turnaround-ns = <0>; | ||
| 295 | gpmc,cycle2cycle-delay-ns = <0>; | ||
| 296 | gpmc,clk-activation-ns = <0>; | ||
| 297 | gpmc,wait-monitoring-ns = <0>; | ||
| 298 | gpmc,wr-access-ns = <40>; | ||
| 299 | gpmc,wr-data-mux-bus-ns = <0>; | ||
| 300 | /* MTD partition table */ | ||
| 301 | /* All SPL-* partitions are sized to minimal length | ||
| 302 | * which can be independently programmable. For | ||
| 303 | * NAND flash this is equal to size of erase-block */ | ||
| 304 | #address-cells = <1>; | ||
| 305 | #size-cells = <1>; | ||
| 306 | partition@0 { | ||
| 307 | label = "NAND.SPL"; | ||
| 308 | reg = <0x00000000 0x00040000>; | ||
| 309 | }; | ||
| 310 | partition@1 { | ||
| 311 | label = "NAND.SPL.backup1"; | ||
| 312 | reg = <0x00040000 0x00040000>; | ||
| 313 | }; | ||
| 314 | partition@2 { | ||
| 315 | label = "NAND.SPL.backup2"; | ||
| 316 | reg = <0x00080000 0x00040000>; | ||
| 317 | }; | ||
| 318 | partition@3 { | ||
| 319 | label = "NAND.SPL.backup3"; | ||
| 320 | reg = <0x000C0000 0x00040000>; | ||
| 321 | }; | ||
| 322 | partition@4 { | ||
| 323 | label = "NAND.u-boot-spl-os"; | ||
| 324 | reg = <0x00100000 0x00080000>; | ||
| 325 | }; | ||
| 326 | partition@5 { | ||
| 327 | label = "NAND.u-boot"; | ||
| 328 | reg = <0x00180000 0x00100000>; | ||
| 329 | }; | ||
| 330 | partition@6 { | ||
| 331 | label = "NAND.u-boot-env"; | ||
| 332 | reg = <0x00280000 0x00040000>; | ||
| 333 | }; | ||
| 334 | partition@7 { | ||
| 335 | label = "NAND.u-boot-env.backup1"; | ||
| 336 | reg = <0x002C0000 0x00040000>; | ||
| 337 | }; | ||
| 338 | partition@8 { | ||
| 339 | label = "NAND.kernel"; | ||
| 340 | reg = <0x00300000 0x00700000>; | ||
| 341 | }; | ||
| 342 | partition@9 { | ||
| 343 | label = "NAND.file-system"; | ||
| 344 | reg = <0x00800000 0x1F600000>; | ||
| 345 | }; | ||
| 346 | }; | ||
| 347 | }; | ||
| 348 | |||
| 349 | &epwmss0 { | ||
| 350 | status = "okay"; | ||
| 351 | }; | ||
| 352 | |||
| 353 | &ecap0 { | ||
| 354 | status = "okay"; | ||
| 355 | pinctrl-names = "default"; | ||
| 356 | pinctrl-0 = <&ecap0_pins>; | ||
| 357 | }; | ||
| 358 | |||
| 359 | &spi0 { | ||
| 360 | pinctrl-names = "default"; | ||
| 361 | pinctrl-0 = <&spi0_pins>; | ||
| 362 | status = "okay"; | ||
| 363 | }; | ||
| 364 | |||
| 365 | &spi1 { | ||
| 366 | pinctrl-names = "default"; | ||
| 367 | pinctrl-0 = <&spi1_pins>; | ||
| 368 | status = "okay"; | ||
| 369 | }; | ||
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts index 08a56bcfc724..82f238a9063f 100644 --- a/arch/arm/boot/dts/armada-370-db.dts +++ b/arch/arm/boot/dts/armada-370-db.dts | |||
| @@ -64,6 +64,22 @@ | |||
| 64 | phy-mode = "rgmii-id"; | 64 | phy-mode = "rgmii-id"; |
| 65 | }; | 65 | }; |
| 66 | 66 | ||
| 67 | i2c@11000 { | ||
| 68 | pinctrl-0 = <&i2c0_pins>; | ||
| 69 | pinctrl-names = "default"; | ||
| 70 | status = "okay"; | ||
| 71 | audio_codec: audio-codec@4a { | ||
| 72 | compatible = "cirrus,cs42l51"; | ||
| 73 | reg = <0x4a>; | ||
| 74 | }; | ||
| 75 | }; | ||
| 76 | |||
| 77 | audio-controller@30000 { | ||
| 78 | pinctrl-0 = <&i2s_pins2>; | ||
| 79 | pinctrl-names = "default"; | ||
| 80 | status = "okay"; | ||
| 81 | }; | ||
| 82 | |||
| 67 | mvsdio@d4000 { | 83 | mvsdio@d4000 { |
| 68 | pinctrl-0 = <&sdio_pins1>; | 84 | pinctrl-0 = <&sdio_pins1>; |
| 69 | pinctrl-names = "default"; | 85 | pinctrl-names = "default"; |
| @@ -80,6 +96,30 @@ | |||
| 80 | broken-cd; | 96 | broken-cd; |
| 81 | }; | 97 | }; |
| 82 | 98 | ||
| 99 | pinctrl { | ||
| 100 | /* | ||
| 101 | * These pins might be muxed as I2S by | ||
| 102 | * the bootloader, but it conflicts | ||
| 103 | * with the real I2S pins that are | ||
| 104 | * muxed using i2s_pins. We must mux | ||
| 105 | * those pins to a function other than | ||
| 106 | * I2S. | ||
| 107 | */ | ||
| 108 | pinctrl-0 = <&hog_pins1 &hog_pins2>; | ||
| 109 | pinctrl-names = "default"; | ||
| 110 | |||
| 111 | hog_pins1: hog-pins1 { | ||
| 112 | marvell,pins = "mpp6", "mpp8", "mpp10", | ||
| 113 | "mpp12", "mpp13"; | ||
| 114 | marvell,function = "gpio"; | ||
| 115 | }; | ||
| 116 | |||
| 117 | hog_pins2: hog-pins2 { | ||
| 118 | marvell,pins = "mpp5", "mpp7", "mpp9"; | ||
| 119 | marvell,function = "gpo"; | ||
| 120 | }; | ||
| 121 | }; | ||
| 122 | |||
| 83 | usb@50000 { | 123 | usb@50000 { |
| 84 | status = "okay"; | 124 | status = "okay"; |
| 85 | }; | 125 | }; |
| @@ -112,10 +152,26 @@ | |||
| 112 | /* Port 0, Lane 0 */ | 152 | /* Port 0, Lane 0 */ |
| 113 | status = "okay"; | 153 | status = "okay"; |
| 114 | }; | 154 | }; |
| 155 | |||
| 115 | pcie@2,0 { | 156 | pcie@2,0 { |
| 116 | /* Port 1, Lane 0 */ | 157 | /* Port 1, Lane 0 */ |
| 117 | status = "okay"; | 158 | status = "okay"; |
| 118 | }; | 159 | }; |
| 119 | }; | 160 | }; |
| 120 | }; | 161 | }; |
| 162 | |||
| 163 | sound { | ||
| 164 | compatible = "marvell,a370db-audio"; | ||
| 165 | marvell,audio-controller = <&audio_controller>; | ||
| 166 | marvell,audio-codec = <&audio_codec &spdif_out &spdif_in>; | ||
| 167 | status = "okay"; | ||
| 168 | }; | ||
| 169 | |||
| 170 | spdif_out: spdif-out { | ||
| 171 | compatible = "linux,spdif-dit"; | ||
| 172 | }; | ||
| 173 | |||
| 174 | spdif_in: spdif-in { | ||
| 175 | compatible = "linux,spdif-dir"; | ||
| 176 | }; | ||
| 121 | }; | 177 | }; |
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts index 944e8785b308..2354fe023ee0 100644 --- a/arch/arm/boot/dts/armada-370-mirabox.dts +++ b/arch/arm/boot/dts/armada-370-mirabox.dts | |||
| @@ -9,6 +9,7 @@ | |||
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | /dts-v1/; | 11 | /dts-v1/; |
| 12 | #include <dt-bindings/gpio/gpio.h> | ||
| 12 | #include "armada-370.dtsi" | 13 | #include "armada-370.dtsi" |
| 13 | 14 | ||
| 14 | / { | 15 | / { |
| @@ -73,19 +74,19 @@ | |||
| 73 | 74 | ||
| 74 | green_pwr_led { | 75 | green_pwr_led { |
| 75 | label = "mirabox:green:pwr"; | 76 | label = "mirabox:green:pwr"; |
| 76 | gpios = <&gpio1 31 1>; | 77 | gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; |
| 77 | default-state = "keep"; | 78 | default-state = "keep"; |
| 78 | }; | 79 | }; |
| 79 | 80 | ||
| 80 | blue_stat_led { | 81 | blue_stat_led { |
| 81 | label = "mirabox:blue:stat"; | 82 | label = "mirabox:blue:stat"; |
| 82 | gpios = <&gpio2 0 1>; | 83 | gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; |
| 83 | default-state = "off"; | 84 | default-state = "off"; |
| 84 | }; | 85 | }; |
| 85 | 86 | ||
| 86 | green_stat_led { | 87 | green_stat_led { |
| 87 | label = "mirabox:green:stat"; | 88 | label = "mirabox:green:stat"; |
| 88 | gpios = <&gpio2 1 1>; | 89 | gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; |
| 89 | default-state = "off"; | 90 | default-state = "off"; |
| 90 | }; | 91 | }; |
| 91 | }; | 92 | }; |
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts index abbb807459d2..3e2c857d6000 100644 --- a/arch/arm/boot/dts/armada-370-rd.dts +++ b/arch/arm/boot/dts/armada-370-rd.dts | |||
| @@ -12,6 +12,8 @@ | |||
| 12 | */ | 12 | */ |
| 13 | 13 | ||
| 14 | /dts-v1/; | 14 | /dts-v1/; |
| 15 | #include <dt-bindings/input/input.h> | ||
| 16 | #include <dt-bindings/gpio/gpio.h> | ||
| 15 | #include "armada-370.dtsi" | 17 | #include "armada-370.dtsi" |
| 16 | 18 | ||
| 17 | / { | 19 | / { |
| @@ -100,8 +102,8 @@ | |||
| 100 | #size-cells = <0>; | 102 | #size-cells = <0>; |
| 101 | button@1 { | 103 | button@1 { |
| 102 | label = "Software Button"; | 104 | label = "Software Button"; |
| 103 | linux,code = <116>; | 105 | linux,code = <KEY_POWER>; |
| 104 | gpios = <&gpio0 6 1>; | 106 | gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; |
| 105 | }; | 107 | }; |
| 106 | }; | 108 | }; |
| 107 | 109 | ||
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 74b5964430ac..bbb40f62037d 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi | |||
| @@ -44,8 +44,8 @@ | |||
| 44 | #size-cells = <1>; | 44 | #size-cells = <1>; |
| 45 | controller = <&mbusc>; | 45 | controller = <&mbusc>; |
| 46 | interrupt-parent = <&mpic>; | 46 | interrupt-parent = <&mpic>; |
| 47 | pcie-mem-aperture = <0xe0000000 0x8000000>; | 47 | pcie-mem-aperture = <0xf8000000 0x7e00000>; |
| 48 | pcie-io-aperture = <0xe8000000 0x100000>; | 48 | pcie-io-aperture = <0xffe00000 0x100000>; |
| 49 | 49 | ||
| 50 | devbus-bootcs { | 50 | devbus-bootcs { |
| 51 | compatible = "marvell,mvebu-devbus"; | 51 | compatible = "marvell,mvebu-devbus"; |
| @@ -199,6 +199,10 @@ | |||
| 199 | interrupts = <37>, <38>, <39>, <40>, <5>, <6>; | 199 | interrupts = <37>, <38>, <39>, <40>, <5>, <6>; |
| 200 | }; | 200 | }; |
| 201 | 201 | ||
| 202 | watchdog@20300 { | ||
| 203 | reg = <0x20300 0x34>, <0x20704 0x4>; | ||
| 204 | }; | ||
| 205 | |||
| 202 | usb@50000 { | 206 | usb@50000 { |
| 203 | compatible = "marvell,orion-ehci"; | 207 | compatible = "marvell,orion-ehci"; |
| 204 | reg = <0x50000 0x500>; | 208 | reg = <0x50000 0x500>; |
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index 0d8530c98cf5..af1f11e9e5a0 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi | |||
| @@ -132,6 +132,25 @@ | |||
| 132 | "mpp51", "mpp52", "mpp53"; | 132 | "mpp51", "mpp52", "mpp53"; |
| 133 | marvell,function = "sd0"; | 133 | marvell,function = "sd0"; |
| 134 | }; | 134 | }; |
| 135 | |||
| 136 | i2c0_pins: i2c0-pins { | ||
| 137 | marvell,pins = "mpp2", "mpp3"; | ||
| 138 | marvell,function = "i2c0"; | ||
| 139 | }; | ||
| 140 | |||
| 141 | i2s_pins1: i2s-pins1 { | ||
| 142 | marvell,pins = "mpp5", "mpp6", "mpp7", | ||
| 143 | "mpp8", "mpp9", "mpp10", | ||
| 144 | "mpp12", "mpp13"; | ||
| 145 | marvell,function = "audio"; | ||
| 146 | }; | ||
| 147 | |||
| 148 | i2s_pins2: i2s-pins2 { | ||
| 149 | marvell,pins = "mpp49", "mpp47", "mpp50", | ||
| 150 | "mpp59", "mpp57", "mpp61", | ||
| 151 | "mpp62", "mpp60", "mpp58"; | ||
| 152 | marvell,function = "audio"; | ||
| 153 | }; | ||
| 135 | }; | 154 | }; |
| 136 | 155 | ||
| 137 | gpio0: gpio@18100 { | 156 | gpio0: gpio@18100 { |
| @@ -196,6 +215,20 @@ | |||
| 196 | clocks = <&coreclk 2>; | 215 | clocks = <&coreclk 2>; |
| 197 | }; | 216 | }; |
| 198 | 217 | ||
| 218 | watchdog@20300 { | ||
| 219 | compatible = "marvell,armada-370-wdt"; | ||
| 220 | clocks = <&coreclk 2>; | ||
| 221 | }; | ||
| 222 | |||
| 223 | audio_controller: audio-controller@30000 { | ||
| 224 | compatible = "marvell,armada370-audio"; | ||
| 225 | reg = <0x30000 0x4000>; | ||
| 226 | interrupts = <93>; | ||
| 227 | clocks = <&gateclk 0>; | ||
| 228 | clock-names = "internal"; | ||
| 229 | status = "disabled"; | ||
| 230 | }; | ||
| 231 | |||
| 199 | usb@50000 { | 232 | usb@50000 { |
| 200 | clocks = <&coreclk 0>; | 233 | clocks = <&coreclk 0>; |
| 201 | }; | 234 | }; |
diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/armada-375-db.dts new file mode 100644 index 000000000000..9378d3136b41 --- /dev/null +++ b/arch/arm/boot/dts/armada-375-db.dts | |||
| @@ -0,0 +1,130 @@ | |||
| 1 | /* | ||
| 2 | * Device Tree file for Marvell Armada 375 evaluation board | ||
| 3 | * (DB-88F6720) | ||
| 4 | * | ||
| 5 | * Copyright (C) 2014 Marvell | ||
| 6 | * | ||
| 7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | ||
| 8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | ||
| 9 | * | ||
| 10 | * This file is licensed under the terms of the GNU General Public | ||
| 11 | * License version 2. This program is licensed "as is" without any | ||
| 12 | * warranty of any kind, whether express or implied. | ||
| 13 | */ | ||
| 14 | |||
| 15 | /dts-v1/; | ||
| 16 | #include <dt-bindings/gpio/gpio.h> | ||
| 17 | #include "armada-375.dtsi" | ||
| 18 | |||
| 19 | / { | ||
| 20 | model = "Marvell Armada 375 Development Board"; | ||
| 21 | compatible = "marvell,a375-db", "marvell,armada375"; | ||
| 22 | |||
| 23 | chosen { | ||
| 24 | bootargs = "console=ttyS0,115200 earlyprintk"; | ||
| 25 | }; | ||
| 26 | |||
| 27 | memory { | ||
| 28 | device_type = "memory"; | ||
| 29 | reg = <0x00000000 0x40000000>; /* 1 GB */ | ||
| 30 | }; | ||
| 31 | |||
| 32 | soc { | ||
| 33 | ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 | ||
| 34 | MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>; | ||
| 35 | |||
| 36 | internal-regs { | ||
| 37 | spi@10600 { | ||
| 38 | pinctrl-0 = <&spi0_pins>; | ||
| 39 | pinctrl-names = "default"; | ||
| 40 | /* | ||
| 41 | * SPI conflicts with NAND, so we disable it | ||
| 42 | * here, and select NAND as the enabled device | ||
| 43 | * by default. | ||
| 44 | */ | ||
| 45 | status = "disabled"; | ||
| 46 | |||
| 47 | spi-flash@0 { | ||
| 48 | #address-cells = <1>; | ||
| 49 | #size-cells = <1>; | ||
| 50 | compatible = "n25q128a13"; | ||
| 51 | reg = <0>; /* Chip select 0 */ | ||
| 52 | spi-max-frequency = <108000000>; | ||
| 53 | }; | ||
| 54 | }; | ||
| 55 | |||
| 56 | i2c@11000 { | ||
| 57 | status = "okay"; | ||
| 58 | clock-frequency = <100000>; | ||
| 59 | pinctrl-0 = <&i2c0_pins>; | ||
| 60 | pinctrl-names = "default"; | ||
| 61 | }; | ||
| 62 | |||
| 63 | i2c@11100 { | ||
| 64 | status = "okay"; | ||
| 65 | clock-frequency = <100000>; | ||
| 66 | pinctrl-0 = <&i2c1_pins>; | ||
| 67 | pinctrl-names = "default"; | ||
| 68 | }; | ||
| 69 | |||
| 70 | serial@12000 { | ||
| 71 | clock-frequency = <200000000>; | ||
| 72 | status = "okay"; | ||
| 73 | }; | ||
| 74 | |||
| 75 | pinctrl { | ||
| 76 | sdio_st_pins: sdio-st-pins { | ||
| 77 | marvell,pins = "mpp44", "mpp45"; | ||
| 78 | marvell,function = "gpio"; | ||
| 79 | }; | ||
| 80 | }; | ||
| 81 | |||
| 82 | nand: nand@d0000 { | ||
| 83 | pinctrl-0 = <&nand_pins>; | ||
| 84 | pinctrl-names = "default"; | ||
| 85 | status = "okay"; | ||
| 86 | num-cs = <1>; | ||
| 87 | marvell,nand-keep-config; | ||
| 88 | marvell,nand-enable-arbiter; | ||
| 89 | nand-on-flash-bbt; | ||
| 90 | |||
| 91 | partition@0 { | ||
| 92 | label = "U-Boot"; | ||
| 93 | reg = <0 0x800000>; | ||
| 94 | }; | ||
| 95 | partition@800000 { | ||
| 96 | label = "Linux"; | ||
| 97 | reg = <0x800000 0x800000>; | ||
| 98 | }; | ||
| 99 | partition@1000000 { | ||
| 100 | label = "Filesystem"; | ||
| 101 | reg = <0x1000000 0x3f000000>; | ||
| 102 | }; | ||
| 103 | }; | ||
| 104 | |||
| 105 | mvsdio@d4000 { | ||
| 106 | pinctrl-0 = <&sdio_pins &sdio_st_pins>; | ||
| 107 | pinctrl-names = "default"; | ||
| 108 | status = "okay"; | ||
| 109 | cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; | ||
| 110 | wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; | ||
| 111 | }; | ||
| 112 | }; | ||
| 113 | |||
| 114 | pcie-controller { | ||
| 115 | status = "okay"; | ||
| 116 | /* | ||
| 117 | * The two PCIe units are accessible through | ||
| 118 | * standard PCIe slots on the board. | ||
| 119 | */ | ||
| 120 | pcie@1,0 { | ||
| 121 | /* Port 0, Lane 0 */ | ||
| 122 | status = "okay"; | ||
| 123 | }; | ||
| 124 | pcie@2,0 { | ||
| 125 | /* Port 1, Lane 0 */ | ||
| 126 | status = "okay"; | ||
| 127 | }; | ||
| 128 | }; | ||
| 129 | }; | ||
| 130 | }; | ||
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi new file mode 100644 index 000000000000..3877693fb2d8 --- /dev/null +++ b/arch/arm/boot/dts/armada-375.dtsi | |||
| @@ -0,0 +1,464 @@ | |||
| 1 | /* | ||
| 2 | * Device Tree Include file for Marvell Armada 375 family SoC | ||
| 3 | * | ||
| 4 | * Copyright (C) 2014 Marvell | ||
| 5 | * | ||
| 6 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | ||
| 7 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include "skeleton.dtsi" | ||
| 15 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 16 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 17 | |||
| 18 | #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) | ||
| 19 | |||
| 20 | / { | ||
| 21 | model = "Marvell Armada 375 family SoC"; | ||
| 22 | compatible = "marvell,armada375"; | ||
| 23 | |||
| 24 | aliases { | ||
| 25 | gpio0 = &gpio0; | ||
| 26 | gpio1 = &gpio1; | ||
| 27 | gpio2 = &gpio2; | ||
| 28 | }; | ||
| 29 | |||
| 30 | clocks { | ||
| 31 | /* 2 GHz fixed main PLL */ | ||
| 32 | mainpll: mainpll { | ||
| 33 | compatible = "fixed-clock"; | ||
| 34 | #clock-cells = <0>; | ||
| 35 | clock-frequency = <2000000000>; | ||
| 36 | }; | ||
| 37 | }; | ||
| 38 | |||
| 39 | cpus { | ||
| 40 | #address-cells = <1>; | ||
| 41 | #size-cells = <0>; | ||
| 42 | cpu@0 { | ||
| 43 | device_type = "cpu"; | ||
| 44 | compatible = "arm,cortex-a9"; | ||
| 45 | reg = <0>; | ||
| 46 | }; | ||
| 47 | cpu@1 { | ||
| 48 | device_type = "cpu"; | ||
| 49 | compatible = "arm,cortex-a9"; | ||
| 50 | reg = <1>; | ||
| 51 | }; | ||
| 52 | }; | ||
| 53 | |||
| 54 | soc { | ||
| 55 | compatible = "marvell,armada375-mbus", "marvell,armada370-mbus", "simple-bus"; | ||
| 56 | #address-cells = <2>; | ||
| 57 | #size-cells = <1>; | ||
| 58 | controller = <&mbusc>; | ||
| 59 | interrupt-parent = <&gic>; | ||
| 60 | pcie-mem-aperture = <0xe0000000 0x8000000>; | ||
| 61 | pcie-io-aperture = <0xe8000000 0x100000>; | ||
| 62 | |||
| 63 | bootrom { | ||
| 64 | compatible = "marvell,bootrom"; | ||
| 65 | reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>; | ||
| 66 | }; | ||
| 67 | |||
| 68 | devbus-bootcs { | ||
| 69 | compatible = "marvell,mvebu-devbus"; | ||
| 70 | reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>; | ||
| 71 | ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; | ||
| 72 | #address-cells = <1>; | ||
| 73 | #size-cells = <1>; | ||
| 74 | clocks = <&coreclk 0>; | ||
| 75 | status = "disabled"; | ||
| 76 | }; | ||
| 77 | |||
| 78 | devbus-cs0 { | ||
| 79 | compatible = "marvell,mvebu-devbus"; | ||
| 80 | reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>; | ||
| 81 | ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; | ||
| 82 | #address-cells = <1>; | ||
| 83 | #size-cells = <1>; | ||
| 84 | clocks = <&coreclk 0>; | ||
| 85 | status = "disabled"; | ||
| 86 | }; | ||
| 87 | |||
| 88 | devbus-cs1 { | ||
| 89 | compatible = "marvell,mvebu-devbus"; | ||
| 90 | reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>; | ||
| 91 | ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; | ||
| 92 | #address-cells = <1>; | ||
| 93 | #size-cells = <1>; | ||
| 94 | clocks = <&coreclk 0>; | ||
| 95 | status = "disabled"; | ||
| 96 | }; | ||
| 97 | |||
| 98 | devbus-cs2 { | ||
| 99 | compatible = "marvell,mvebu-devbus"; | ||
| 100 | reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>; | ||
| 101 | ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; | ||
| 102 | #address-cells = <1>; | ||
| 103 | #size-cells = <1>; | ||
| 104 | clocks = <&coreclk 0>; | ||
| 105 | status = "disabled"; | ||
| 106 | }; | ||
| 107 | |||
| 108 | devbus-cs3 { | ||
| 109 | compatible = "marvell,mvebu-devbus"; | ||
| 110 | reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>; | ||
| 111 | ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; | ||
| 112 | #address-cells = <1>; | ||
| 113 | #size-cells = <1>; | ||
| 114 | clocks = <&coreclk 0>; | ||
| 115 | status = "disabled"; | ||
| 116 | }; | ||
| 117 | |||
| 118 | internal-regs { | ||
| 119 | compatible = "simple-bus"; | ||
| 120 | #address-cells = <1>; | ||
| 121 | #size-cells = <1>; | ||
| 122 | ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; | ||
| 123 | |||
| 124 | L2: cache-controller@8000 { | ||
| 125 | compatible = "arm,pl310-cache"; | ||
| 126 | reg = <0x8000 0x1000>; | ||
| 127 | cache-unified; | ||
| 128 | cache-level = <2>; | ||
| 129 | }; | ||
| 130 | |||
| 131 | timer@c600 { | ||
| 132 | compatible = "arm,cortex-a9-twd-timer"; | ||
| 133 | reg = <0xc600 0x20>; | ||
| 134 | interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; | ||
| 135 | clocks = <&coreclk 2>; | ||
| 136 | }; | ||
| 137 | |||
| 138 | gic: interrupt-controller@d000 { | ||
| 139 | compatible = "arm,cortex-a9-gic"; | ||
| 140 | #interrupt-cells = <3>; | ||
| 141 | #size-cells = <0>; | ||
| 142 | interrupt-controller; | ||
| 143 | reg = <0xd000 0x1000>, | ||
| 144 | <0xc100 0x100>; | ||
| 145 | }; | ||
| 146 | |||
| 147 | spi0: spi@10600 { | ||
| 148 | compatible = "marvell,orion-spi"; | ||
| 149 | reg = <0x10600 0x50>; | ||
| 150 | #address-cells = <1>; | ||
| 151 | #size-cells = <0>; | ||
| 152 | cell-index = <0>; | ||
| 153 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; | ||
| 154 | clocks = <&coreclk 0>; | ||
| 155 | status = "disabled"; | ||
| 156 | }; | ||
| 157 | |||
| 158 | spi1: spi@10680 { | ||
| 159 | compatible = "marvell,orion-spi"; | ||
| 160 | reg = <0x10680 0x50>; | ||
| 161 | #address-cells = <1>; | ||
| 162 | #size-cells = <0>; | ||
| 163 | cell-index = <1>; | ||
| 164 | interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; | ||
| 165 | clocks = <&coreclk 0>; | ||
| 166 | status = "disabled"; | ||
| 167 | }; | ||
| 168 | |||
| 169 | i2c0: i2c@11000 { | ||
| 170 | compatible = "marvell,mv64xxx-i2c"; | ||
| 171 | reg = <0x11000 0x20>; | ||
| 172 | #address-cells = <1>; | ||
| 173 | #size-cells = <0>; | ||
| 174 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; | ||
| 175 | timeout-ms = <1000>; | ||
| 176 | clocks = <&coreclk 0>; | ||
| 177 | status = "disabled"; | ||
| 178 | }; | ||
| 179 | |||
| 180 | i2c1: i2c@11100 { | ||
| 181 | compatible = "marvell,mv64xxx-i2c"; | ||
| 182 | reg = <0x11100 0x20>; | ||
| 183 | #address-cells = <1>; | ||
| 184 | #size-cells = <0>; | ||
| 185 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; | ||
| 186 | timeout-ms = <1000>; | ||
| 187 | clocks = <&coreclk 0>; | ||
| 188 | status = "disabled"; | ||
| 189 | }; | ||
| 190 | |||
| 191 | serial@12000 { | ||
| 192 | compatible = "snps,dw-apb-uart"; | ||
| 193 | reg = <0x12000 0x100>; | ||
| 194 | reg-shift = <2>; | ||
| 195 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; | ||
| 196 | reg-io-width = <1>; | ||
| 197 | status = "disabled"; | ||
| 198 | }; | ||
| 199 | |||
| 200 | serial@12100 { | ||
| 201 | compatible = "snps,dw-apb-uart"; | ||
| 202 | reg = <0x12100 0x100>; | ||
| 203 | reg-shift = <2>; | ||
| 204 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; | ||
| 205 | reg-io-width = <1>; | ||
| 206 | status = "disabled"; | ||
| 207 | }; | ||
| 208 | |||
| 209 | pinctrl { | ||
| 210 | compatible = "marvell,mv88f6720-pinctrl"; | ||
| 211 | reg = <0x18000 0x24>; | ||
| 212 | |||
| 213 | i2c0_pins: i2c0-pins { | ||
| 214 | marvell,pins = "mpp14", "mpp15"; | ||
| 215 | marvell,function = "i2c0"; | ||
| 216 | }; | ||
| 217 | |||
| 218 | i2c1_pins: i2c1-pins { | ||
| 219 | marvell,pins = "mpp61", "mpp62"; | ||
| 220 | marvell,function = "i2c1"; | ||
| 221 | }; | ||
| 222 | |||
| 223 | nand_pins: nand-pins { | ||
| 224 | marvell,pins = "mpp0", "mpp1", "mpp2", | ||
| 225 | "mpp3", "mpp4", "mpp5", | ||
| 226 | "mpp6", "mpp7", "mpp8", | ||
| 227 | "mpp9", "mpp10", "mpp11", | ||
| 228 | "mpp12", "mpp13"; | ||
| 229 | marvell,function = "nand"; | ||
| 230 | }; | ||
| 231 | |||
| 232 | sdio_pins: sdio-pins { | ||
| 233 | marvell,pins = "mpp24", "mpp25", "mpp26", | ||
| 234 | "mpp27", "mpp28", "mpp29"; | ||
| 235 | marvell,function = "sd"; | ||
| 236 | }; | ||
| 237 | |||
| 238 | spi0_pins: spi0-pins { | ||
| 239 | marvell,pins = "mpp0", "mpp1", "mpp4", | ||
| 240 | "mpp5", "mpp8", "mpp9"; | ||
| 241 | marvell,function = "spi0"; | ||
| 242 | }; | ||
| 243 | }; | ||
| 244 | |||
| 245 | gpio0: gpio@18100 { | ||
| 246 | compatible = "marvell,orion-gpio"; | ||
| 247 | reg = <0x18100 0x40>; | ||
| 248 | ngpios = <32>; | ||
| 249 | gpio-controller; | ||
| 250 | #gpio-cells = <2>; | ||
| 251 | interrupt-controller; | ||
| 252 | #interrupt-cells = <2>; | ||
| 253 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, | ||
| 254 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, | ||
| 255 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | ||
| 256 | <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; | ||
| 257 | }; | ||
| 258 | |||
| 259 | gpio1: gpio@18140 { | ||
| 260 | compatible = "marvell,orion-gpio"; | ||
| 261 | reg = <0x18140 0x40>; | ||
| 262 | ngpios = <32>; | ||
| 263 | gpio-controller; | ||
| 264 | #gpio-cells = <2>; | ||
| 265 | interrupt-controller; | ||
| 266 | #interrupt-cells = <2>; | ||
| 267 | interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, | ||
| 268 | <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, | ||
| 269 | <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, | ||
| 270 | <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; | ||
| 271 | }; | ||
| 272 | |||
| 273 | gpio2: gpio@18180 { | ||
| 274 | compatible = "marvell,orion-gpio"; | ||
| 275 | reg = <0x18180 0x40>; | ||
| 276 | ngpios = <3>; | ||
| 277 | gpio-controller; | ||
| 278 | #gpio-cells = <2>; | ||
| 279 | interrupt-controller; | ||
| 280 | #interrupt-cells = <2>; | ||
| 281 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; | ||
| 282 | }; | ||
| 283 | |||
| 284 | system-controller@18200 { | ||
| 285 | compatible = "marvell,armada-375-system-controller"; | ||
| 286 | reg = <0x18200 0x100>; | ||
| 287 | }; | ||
| 288 | |||
| 289 | gateclk: clock-gating-control@18220 { | ||
| 290 | compatible = "marvell,armada-375-gating-clock"; | ||
| 291 | reg = <0x18220 0x4>; | ||
| 292 | clocks = <&coreclk 0>; | ||
| 293 | #clock-cells = <1>; | ||
| 294 | }; | ||
| 295 | |||
| 296 | mbusc: mbus-controller@20000 { | ||
| 297 | compatible = "marvell,mbus-controller"; | ||
| 298 | reg = <0x20000 0x100>, <0x20180 0x20>; | ||
| 299 | }; | ||
| 300 | |||
| 301 | mpic: interrupt-controller@20000 { | ||
| 302 | compatible = "marvell,mpic"; | ||
| 303 | reg = <0x20a00 0x2d0>, <0x21070 0x58>; | ||
| 304 | #interrupt-cells = <1>; | ||
| 305 | #size-cells = <1>; | ||
| 306 | interrupt-controller; | ||
| 307 | msi-controller; | ||
| 308 | interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; | ||
| 309 | }; | ||
| 310 | |||
| 311 | timer@20300 { | ||
| 312 | compatible = "marvell,armada-375-timer", "marvell,armada-370-timer"; | ||
| 313 | reg = <0x20300 0x30>, <0x21040 0x30>; | ||
| 314 | interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, | ||
| 315 | <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, | ||
| 316 | <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, | ||
| 317 | <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, | ||
| 318 | <&mpic 5>, | ||
| 319 | <&mpic 6>; | ||
| 320 | clocks = <&coreclk 0>; | ||
| 321 | }; | ||
| 322 | |||
| 323 | xor@60800 { | ||
| 324 | compatible = "marvell,orion-xor"; | ||
| 325 | reg = <0x60800 0x100 | ||
| 326 | 0x60A00 0x100>; | ||
| 327 | clocks = <&gateclk 22>; | ||
| 328 | status = "okay"; | ||
| 329 | |||
| 330 | xor00 { | ||
| 331 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; | ||
| 332 | dmacap,memcpy; | ||
| 333 | dmacap,xor; | ||
| 334 | }; | ||
| 335 | xor01 { | ||
| 336 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | ||
| 337 | dmacap,memcpy; | ||
| 338 | dmacap,xor; | ||
| 339 | dmacap,memset; | ||
| 340 | }; | ||
| 341 | }; | ||
| 342 | |||
| 343 | xor@60900 { | ||
| 344 | compatible = "marvell,orion-xor"; | ||
| 345 | reg = <0x60900 0x100 | ||
| 346 | 0x60b00 0x100>; | ||
| 347 | clocks = <&gateclk 23>; | ||
| 348 | status = "okay"; | ||
| 349 | |||
| 350 | xor10 { | ||
| 351 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; | ||
| 352 | dmacap,memcpy; | ||
| 353 | dmacap,xor; | ||
| 354 | }; | ||
| 355 | xor11 { | ||
| 356 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; | ||
| 357 | dmacap,memcpy; | ||
| 358 | dmacap,xor; | ||
| 359 | dmacap,memset; | ||
| 360 | }; | ||
| 361 | }; | ||
| 362 | |||
| 363 | sata@a0000 { | ||
| 364 | compatible = "marvell,orion-sata"; | ||
| 365 | reg = <0xa0000 0x5000>; | ||
| 366 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | ||
| 367 | clocks = <&gateclk 14>, <&gateclk 20>; | ||
| 368 | clock-names = "0", "1"; | ||
| 369 | status = "disabled"; | ||
| 370 | }; | ||
| 371 | |||
| 372 | nand@d0000 { | ||
| 373 | compatible = "marvell,armada370-nand"; | ||
| 374 | reg = <0xd0000 0x54>; | ||
| 375 | #address-cells = <1>; | ||
| 376 | #size-cells = <1>; | ||
| 377 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | ||
| 378 | clocks = <&gateclk 11>; | ||
| 379 | status = "disabled"; | ||
| 380 | }; | ||
| 381 | |||
| 382 | mvsdio@d4000 { | ||
| 383 | compatible = "marvell,orion-sdio"; | ||
| 384 | reg = <0xd4000 0x200>; | ||
| 385 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; | ||
| 386 | clocks = <&gateclk 17>; | ||
| 387 | bus-width = <4>; | ||
| 388 | cap-sdio-irq; | ||
| 389 | cap-sd-highspeed; | ||
| 390 | cap-mmc-highspeed; | ||
| 391 | status = "disabled"; | ||
| 392 | }; | ||
| 393 | |||
| 394 | coreclk: mvebu-sar@e8204 { | ||
| 395 | compatible = "marvell,armada-375-core-clock"; | ||
| 396 | reg = <0xe8204 0x04>; | ||
| 397 | #clock-cells = <1>; | ||
| 398 | }; | ||
| 399 | |||
| 400 | coredivclk: corediv-clock@e8250 { | ||
| 401 | compatible = "marvell,armada-375-corediv-clock"; | ||
| 402 | reg = <0xe8250 0xc>; | ||
| 403 | #clock-cells = <1>; | ||
| 404 | clocks = <&mainpll>; | ||
| 405 | clock-output-names = "nand"; | ||
| 406 | }; | ||
| 407 | }; | ||
| 408 | |||
| 409 | pcie-controller { | ||
| 410 | compatible = "marvell,armada-370-pcie"; | ||
| 411 | status = "disabled"; | ||
| 412 | device_type = "pci"; | ||
| 413 | |||
| 414 | #address-cells = <3>; | ||
| 415 | #size-cells = <2>; | ||
| 416 | |||
| 417 | msi-parent = <&mpic>; | ||
| 418 | bus-range = <0x00 0xff>; | ||
| 419 | |||
| 420 | ranges = | ||
| 421 | <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 | ||
| 422 | 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 | ||
| 423 | 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */ | ||
| 424 | 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */ | ||
| 425 | 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */ | ||
| 426 | 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>; | ||
| 427 | |||
| 428 | pcie@1,0 { | ||
| 429 | device_type = "pci"; | ||
| 430 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | ||
| 431 | reg = <0x0800 0 0 0 0>; | ||
| 432 | #address-cells = <3>; | ||
| 433 | #size-cells = <2>; | ||
| 434 | #interrupt-cells = <1>; | ||
| 435 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 | ||
| 436 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; | ||
| 437 | interrupt-map-mask = <0 0 0 0>; | ||
| 438 | interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; | ||
| 439 | marvell,pcie-port = <0>; | ||
| 440 | marvell,pcie-lane = <0>; | ||
| 441 | clocks = <&gateclk 5>; | ||
| 442 | status = "disabled"; | ||
| 443 | }; | ||
| 444 | |||
| 445 | pcie@2,0 { | ||
| 446 | device_type = "pci"; | ||
| 447 | assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; | ||
| 448 | reg = <0x1000 0 0 0 0>; | ||
| 449 | #address-cells = <3>; | ||
| 450 | #size-cells = <2>; | ||
| 451 | #interrupt-cells = <1>; | ||
| 452 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 | ||
| 453 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; | ||
| 454 | interrupt-map-mask = <0 0 0 0>; | ||
| 455 | interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; | ||
| 456 | marvell,pcie-port = <0>; | ||
| 457 | marvell,pcie-lane = <1>; | ||
| 458 | clocks = <&gateclk 6>; | ||
| 459 | status = "disabled"; | ||
| 460 | }; | ||
| 461 | |||
| 462 | }; | ||
| 463 | }; | ||
| 464 | }; | ||
diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi new file mode 100644 index 000000000000..068031f0f263 --- /dev/null +++ b/arch/arm/boot/dts/armada-380.dtsi | |||
| @@ -0,0 +1,117 @@ | |||
| 1 | /* | ||
| 2 | * Device Tree Include file for Marvell Armada 380 SoC. | ||
| 3 | * | ||
| 4 | * Copyright (C) 2014 Marvell | ||
| 5 | * | ||
| 6 | * Lior Amsalem <alior@marvell.com> | ||
| 7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | ||
| 8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | ||
| 9 | * | ||
| 10 | * This file is licensed under the terms of the GNU General Public | ||
| 11 | * License version 2. This program is licensed "as is" without any | ||
| 12 | * warranty of any kind, whether express or implied. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include "armada-38x.dtsi" | ||
| 16 | |||
| 17 | / { | ||
| 18 | model = "Marvell Armada 380 family SoC"; | ||
| 19 | compatible = "marvell,armada380", "marvell,armada38x"; | ||
| 20 | |||
| 21 | cpus { | ||
| 22 | #address-cells = <1>; | ||
| 23 | #size-cells = <0>; | ||
| 24 | cpu@0 { | ||
| 25 | device_type = "cpu"; | ||
| 26 | compatible = "arm,cortex-a9"; | ||
| 27 | reg = <0>; | ||
| 28 | }; | ||
| 29 | }; | ||
| 30 | |||
| 31 | soc { | ||
| 32 | internal-regs { | ||
| 33 | pinctrl { | ||
| 34 | compatible = "marvell,mv88f6810-pinctrl"; | ||
| 35 | reg = <0x18000 0x20>; | ||
| 36 | }; | ||
| 37 | }; | ||
| 38 | |||
| 39 | pcie-controller { | ||
| 40 | compatible = "marvell,armada-370-pcie"; | ||
| 41 | status = "disabled"; | ||
| 42 | device_type = "pci"; | ||
| 43 | |||
| 44 | #address-cells = <3>; | ||
| 45 | #size-cells = <2>; | ||
| 46 | |||
| 47 | msi-parent = <&mpic>; | ||
| 48 | bus-range = <0x00 0xff>; | ||
| 49 | |||
| 50 | ranges = | ||
| 51 | <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 | ||
| 52 | 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 | ||
| 53 | 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 | ||
| 54 | 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 | ||
| 55 | 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ | ||
| 56 | 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ | ||
| 57 | 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ | ||
| 58 | 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ | ||
| 59 | 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ | ||
| 60 | 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>; | ||
| 61 | |||
| 62 | /* x1 port */ | ||
| 63 | pcie@1,0 { | ||
| 64 | device_type = "pci"; | ||
| 65 | assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; | ||
| 66 | reg = <0x0800 0 0 0 0>; | ||
| 67 | #address-cells = <3>; | ||
| 68 | #size-cells = <2>; | ||
| 69 | #interrupt-cells = <1>; | ||
| 70 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 | ||
| 71 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; | ||
| 72 | interrupt-map-mask = <0 0 0 0>; | ||
| 73 | interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; | ||
| 74 | marvell,pcie-port = <0>; | ||
| 75 | marvell,pcie-lane = <0>; | ||
| 76 | clocks = <&gateclk 8>; | ||
| 77 | status = "disabled"; | ||
| 78 | }; | ||
| 79 | |||
| 80 | /* x1 port */ | ||
| 81 | pcie@2,0 { | ||
| 82 | device_type = "pci"; | ||
| 83 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | ||
| 84 | reg = <0x1000 0 0 0 0>; | ||
| 85 | #address-cells = <3>; | ||
| 86 | #size-cells = <2>; | ||
| 87 | #interrupt-cells = <1>; | ||
| 88 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 | ||
| 89 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; | ||
| 90 | interrupt-map-mask = <0 0 0 0>; | ||
| 91 | interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; | ||
| 92 | marvell,pcie-port = <1>; | ||
| 93 | marvell,pcie-lane = <0>; | ||
| 94 | clocks = <&gateclk 5>; | ||
| 95 | status = "disabled"; | ||
| 96 | }; | ||
| 97 | |||
| 98 | /* x1 port */ | ||
| 99 | pcie@3,0 { | ||
| 100 | device_type = "pci"; | ||
| 101 | assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; | ||
| 102 | reg = <0x1000 0 0 0 0>; | ||
| 103 | #address-cells = <3>; | ||
| 104 | #size-cells = <2>; | ||
| 105 | #interrupt-cells = <1>; | ||
| 106 | ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 | ||
| 107 | 0x81000000 0 0 0x81000000 0x3 0 1 0>; | ||
| 108 | interrupt-map-mask = <0 0 0 0>; | ||
| 109 | interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; | ||
| 110 | marvell,pcie-port = <2>; | ||
| 111 | marvell,pcie-lane = <0>; | ||
| 112 | clocks = <&gateclk 6>; | ||
| 113 | status = "disabled"; | ||
| 114 | }; | ||
| 115 | }; | ||
| 116 | }; | ||
| 117 | }; | ||
diff --git a/arch/arm/boot/dts/armada-385-db.dts b/arch/arm/boot/dts/armada-385-db.dts new file mode 100644 index 000000000000..6828d77696a6 --- /dev/null +++ b/arch/arm/boot/dts/armada-385-db.dts | |||
| @@ -0,0 +1,122 @@ | |||
| 1 | /* | ||
| 2 | * Device Tree file for Marvell Armada 385 evaluation board | ||
| 3 | * (DB-88F6820) | ||
| 4 | * | ||
| 5 | * Copyright (C) 2014 Marvell | ||
| 6 | * | ||
| 7 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | /dts-v1/; | ||
| 15 | #include "armada-385.dtsi" | ||
| 16 | |||
| 17 | / { | ||
| 18 | model = "Marvell Armada 385 Development Board"; | ||
| 19 | compatible = "marvell,a385-db", "marvell,armada385", "marvell,armada38x"; | ||
| 20 | |||
| 21 | chosen { | ||
| 22 | bootargs = "console=ttyS0,115200 earlyprintk"; | ||
| 23 | }; | ||
| 24 | |||
| 25 | memory { | ||
| 26 | device_type = "memory"; | ||
| 27 | reg = <0x00000000 0x10000000>; /* 256 MB */ | ||
| 28 | }; | ||
| 29 | |||
| 30 | soc { | ||
| 31 | ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 | ||
| 32 | MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>; | ||
| 33 | |||
| 34 | internal-regs { | ||
| 35 | spi@10600 { | ||
| 36 | status = "okay"; | ||
| 37 | |||
| 38 | spi-flash@0 { | ||
| 39 | #address-cells = <1>; | ||
| 40 | #size-cells = <1>; | ||
| 41 | compatible = "w25q32"; | ||
| 42 | reg = <0>; /* Chip select 0 */ | ||
| 43 | spi-max-frequency = <108000000>; | ||
| 44 | }; | ||
| 45 | }; | ||
| 46 | |||
| 47 | i2c@11000 { | ||
| 48 | status = "okay"; | ||
| 49 | clock-frequency = <100000>; | ||
| 50 | }; | ||
| 51 | |||
| 52 | i2c@11100 { | ||
| 53 | status = "okay"; | ||
| 54 | clock-frequency = <100000>; | ||
| 55 | }; | ||
| 56 | |||
| 57 | serial@12000 { | ||
| 58 | clock-frequency = <200000000>; | ||
| 59 | status = "okay"; | ||
| 60 | }; | ||
| 61 | |||
| 62 | ethernet@30000 { | ||
| 63 | status = "okay"; | ||
| 64 | phy = <&phy1>; | ||
| 65 | phy-mode = "rgmii-id"; | ||
| 66 | }; | ||
| 67 | |||
| 68 | ethernet@70000 { | ||
| 69 | status = "okay"; | ||
| 70 | phy = <&phy0>; | ||
| 71 | phy-mode = "rgmii-id"; | ||
| 72 | }; | ||
| 73 | |||
| 74 | mdio { | ||
| 75 | phy0: ethernet-phy@0 { | ||
| 76 | reg = <0>; | ||
| 77 | }; | ||
| 78 | |||
| 79 | phy1: ethernet-phy@1 { | ||
| 80 | reg = <1>; | ||
| 81 | }; | ||
| 82 | }; | ||
| 83 | |||
| 84 | flash@d0000 { | ||
| 85 | status = "okay"; | ||
| 86 | num-cs = <1>; | ||
| 87 | marvell,nand-keep-config; | ||
| 88 | marvell,nand-enable-arbiter; | ||
| 89 | nand-on-flash-bbt; | ||
| 90 | |||
| 91 | partition@0 { | ||
| 92 | label = "U-Boot"; | ||
| 93 | reg = <0 0x800000>; | ||
| 94 | }; | ||
| 95 | partition@800000 { | ||
| 96 | label = "Linux"; | ||
| 97 | reg = <0x800000 0x800000>; | ||
| 98 | }; | ||
| 99 | partition@1000000 { | ||
| 100 | label = "Filesystem"; | ||
| 101 | reg = <0x1000000 0x3f000000>; | ||
| 102 | }; | ||
| 103 | }; | ||
| 104 | }; | ||
| 105 | |||
| 106 | pcie-controller { | ||
| 107 | status = "okay"; | ||
| 108 | /* | ||
| 109 | * The two PCIe units are accessible through | ||
| 110 | * standard PCIe slots on the board. | ||
| 111 | */ | ||
| 112 | pcie@1,0 { | ||
| 113 | /* Port 0, Lane 0 */ | ||
| 114 | status = "okay"; | ||
| 115 | }; | ||
| 116 | pcie@2,0 { | ||
| 117 | /* Port 1, Lane 0 */ | ||
| 118 | status = "okay"; | ||
| 119 | }; | ||
| 120 | }; | ||
| 121 | }; | ||
| 122 | }; | ||
diff --git a/arch/arm/boot/dts/armada-385-rd.dts b/arch/arm/boot/dts/armada-385-rd.dts new file mode 100644 index 000000000000..45250c88814b --- /dev/null +++ b/arch/arm/boot/dts/armada-385-rd.dts | |||
| @@ -0,0 +1,94 @@ | |||
| 1 | /* | ||
| 2 | * Device Tree file for Marvell Armada 385 Reference Design board | ||
| 3 | * (RD-88F6820-AP) | ||
| 4 | * | ||
| 5 | * Copyright (C) 2014 Marvell | ||
| 6 | * | ||
| 7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | ||
| 8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | ||
| 9 | * | ||
| 10 | * This file is licensed under the terms of the GNU General Public | ||
| 11 | * License version 2. This program is licensed "as is" without any | ||
| 12 | * warranty of any kind, whether express or implied. | ||
| 13 | */ | ||
| 14 | |||
| 15 | /dts-v1/; | ||
| 16 | #include "armada-385.dtsi" | ||
| 17 | |||
| 18 | / { | ||
| 19 | model = "Marvell Armada 385 Reference Design"; | ||
| 20 | compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada38x"; | ||
| 21 | |||
| 22 | chosen { | ||
| 23 | bootargs = "console=ttyS0,115200 earlyprintk"; | ||
| 24 | }; | ||
| 25 | |||
| 26 | memory { | ||
| 27 | device_type = "memory"; | ||
| 28 | reg = <0x00000000 0x10000000>; /* 256 MB */ | ||
| 29 | }; | ||
| 30 | |||
| 31 | soc { | ||
| 32 | ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 | ||
| 33 | MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>; | ||
| 34 | |||
| 35 | internal-regs { | ||
| 36 | spi@10600 { | ||
| 37 | status = "okay"; | ||
| 38 | |||
| 39 | spi-flash@0 { | ||
| 40 | #address-cells = <1>; | ||
| 41 | #size-cells = <1>; | ||
| 42 | compatible = "st,m25p128"; | ||
| 43 | reg = <0>; /* Chip select 0 */ | ||
| 44 | spi-max-frequency = <108000000>; | ||
| 45 | }; | ||
| 46 | }; | ||
| 47 | |||
| 48 | i2c@11000 { | ||
| 49 | status = "okay"; | ||
| 50 | clock-frequency = <100000>; | ||
| 51 | }; | ||
| 52 | |||
| 53 | serial@12000 { | ||
| 54 | clock-frequency = <200000000>; | ||
| 55 | status = "okay"; | ||
| 56 | }; | ||
| 57 | |||
| 58 | ethernet@30000 { | ||
| 59 | status = "okay"; | ||
| 60 | phy = <&phy0>; | ||
| 61 | phy-mode = "rgmii-id"; | ||
| 62 | }; | ||
| 63 | |||
| 64 | ethernet@70000 { | ||
| 65 | status = "okay"; | ||
| 66 | phy = <&phy1>; | ||
| 67 | phy-mode = "rgmii-id"; | ||
| 68 | }; | ||
| 69 | |||
| 70 | |||
| 71 | mdio { | ||
| 72 | phy0: ethernet-phy@0 { | ||
| 73 | reg = <0>; | ||
| 74 | }; | ||
| 75 | |||
| 76 | phy1: ethernet-phy@1 { | ||
| 77 | reg = <1>; | ||
| 78 | }; | ||
| 79 | }; | ||
| 80 | }; | ||
| 81 | |||
| 82 | pcie-controller { | ||
| 83 | status = "okay"; | ||
| 84 | /* | ||
| 85 | * One PCIe units is accessible through | ||
| 86 | * standard PCIe slot on the board. | ||
| 87 | */ | ||
| 88 | pcie@1,0 { | ||
| 89 | /* Port 0, Lane 0 */ | ||
| 90 | status = "okay"; | ||
| 91 | }; | ||
| 92 | }; | ||
| 93 | }; | ||
| 94 | }; | ||
diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi new file mode 100644 index 000000000000..e2919f02e1d4 --- /dev/null +++ b/arch/arm/boot/dts/armada-385.dtsi | |||
| @@ -0,0 +1,149 @@ | |||
| 1 | /* | ||
| 2 | * Device Tree Include file for Marvell Armada 385 SoC. | ||
| 3 | * | ||
| 4 | * Copyright (C) 2014 Marvell | ||
| 5 | * | ||
| 6 | * Lior Amsalem <alior@marvell.com> | ||
| 7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | ||
| 8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | ||
| 9 | * | ||
| 10 | * This file is licensed under the terms of the GNU General Public | ||
| 11 | * License version 2. This program is licensed "as is" without any | ||
| 12 | * warranty of any kind, whether express or implied. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include "armada-38x.dtsi" | ||
| 16 | |||
| 17 | / { | ||
| 18 | model = "Marvell Armada 385 family SoC"; | ||
| 19 | compatible = "marvell,armada385", "marvell,armada38x"; | ||
| 20 | |||
| 21 | cpus { | ||
| 22 | #address-cells = <1>; | ||
| 23 | #size-cells = <0>; | ||
| 24 | cpu@0 { | ||
| 25 | device_type = "cpu"; | ||
| 26 | compatible = "arm,cortex-a9"; | ||
| 27 | reg = <0>; | ||
| 28 | }; | ||
| 29 | cpu@1 { | ||
| 30 | device_type = "cpu"; | ||
| 31 | compatible = "arm,cortex-a9"; | ||
| 32 | reg = <1>; | ||
| 33 | }; | ||
| 34 | }; | ||
| 35 | |||
| 36 | soc { | ||
| 37 | internal-regs { | ||
| 38 | pinctrl { | ||
| 39 | compatible = "marvell,mv88f6820-pinctrl"; | ||
| 40 | reg = <0x18000 0x20>; | ||
| 41 | }; | ||
| 42 | }; | ||
| 43 | |||
| 44 | pcie-controller { | ||
| 45 | compatible = "marvell,armada-370-pcie"; | ||
| 46 | status = "disabled"; | ||
| 47 | device_type = "pci"; | ||
| 48 | |||
| 49 | #address-cells = <3>; | ||
| 50 | #size-cells = <2>; | ||
| 51 | |||
| 52 | msi-parent = <&mpic>; | ||
| 53 | bus-range = <0x00 0xff>; | ||
| 54 | |||
| 55 | ranges = | ||
| 56 | <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 | ||
| 57 | 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 | ||
| 58 | 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 | ||
| 59 | 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 | ||
| 60 | 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ | ||
| 61 | 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ | ||
| 62 | 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ | ||
| 63 | 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ | ||
| 64 | 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ | ||
| 65 | 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */ | ||
| 66 | 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */ | ||
| 67 | 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>; | ||
| 68 | |||
| 69 | /* | ||
| 70 | * This port can be either x4 or x1. When | ||
| 71 | * configured in x4 by the bootloader, then | ||
| 72 | * pcie@4,0 is not available. | ||
| 73 | */ | ||
| 74 | pcie@1,0 { | ||
| 75 | device_type = "pci"; | ||
| 76 | assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; | ||
| 77 | reg = <0x0800 0 0 0 0>; | ||
| 78 | #address-cells = <3>; | ||
| 79 | #size-cells = <2>; | ||
| 80 | #interrupt-cells = <1>; | ||
| 81 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 | ||
| 82 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; | ||
| 83 | interrupt-map-mask = <0 0 0 0>; | ||
| 84 | interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; | ||
| 85 | marvell,pcie-port = <0>; | ||
| 86 | marvell,pcie-lane = <0>; | ||
| 87 | clocks = <&gateclk 8>; | ||
| 88 | status = "disabled"; | ||
| 89 | }; | ||
| 90 | |||
| 91 | /* x1 port */ | ||
| 92 | pcie@2,0 { | ||
| 93 | device_type = "pci"; | ||
| 94 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | ||
| 95 | reg = <0x1000 0 0 0 0>; | ||
| 96 | #address-cells = <3>; | ||
| 97 | #size-cells = <2>; | ||
| 98 | #interrupt-cells = <1>; | ||
| 99 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 | ||
| 100 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; | ||
| 101 | interrupt-map-mask = <0 0 0 0>; | ||
| 102 | interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; | ||
| 103 | marvell,pcie-port = <1>; | ||
| 104 | marvell,pcie-lane = <0>; | ||
| 105 | clocks = <&gateclk 5>; | ||
| 106 | status = "disabled"; | ||
| 107 | }; | ||
| 108 | |||
| 109 | /* x1 port */ | ||
| 110 | pcie@3,0 { | ||
| 111 | device_type = "pci"; | ||
| 112 | assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; | ||
| 113 | reg = <0x1000 0 0 0 0>; | ||
| 114 | #address-cells = <3>; | ||
| 115 | #size-cells = <2>; | ||
| 116 | #interrupt-cells = <1>; | ||
| 117 | ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 | ||
| 118 | 0x81000000 0 0 0x81000000 0x3 0 1 0>; | ||
| 119 | interrupt-map-mask = <0 0 0 0>; | ||
| 120 | interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; | ||
| 121 | marvell,pcie-port = <2>; | ||
| 122 | marvell,pcie-lane = <0>; | ||
| 123 | clocks = <&gateclk 6>; | ||
| 124 | status = "disabled"; | ||
| 125 | }; | ||
| 126 | |||
| 127 | /* | ||
| 128 | * x1 port only available when pcie@1,0 is | ||
| 129 | * configured as a x1 port | ||
| 130 | */ | ||
| 131 | pcie@4,0 { | ||
| 132 | device_type = "pci"; | ||
| 133 | assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; | ||
| 134 | reg = <0x1000 0 0 0 0>; | ||
| 135 | #address-cells = <3>; | ||
| 136 | #size-cells = <2>; | ||
| 137 | #interrupt-cells = <1>; | ||
| 138 | ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 | ||
| 139 | 0x81000000 0 0 0x81000000 0x4 0 1 0>; | ||
| 140 | interrupt-map-mask = <0 0 0 0>; | ||
| 141 | interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; | ||
| 142 | marvell,pcie-port = <3>; | ||
| 143 | marvell,pcie-lane = <0>; | ||
| 144 | clocks = <&gateclk 7>; | ||
| 145 | status = "disabled"; | ||
| 146 | }; | ||
| 147 | }; | ||
| 148 | }; | ||
| 149 | }; | ||
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi new file mode 100644 index 000000000000..a064f59da02d --- /dev/null +++ b/arch/arm/boot/dts/armada-38x.dtsi | |||
| @@ -0,0 +1,376 @@ | |||
| 1 | /* | ||
| 2 | * Device Tree Include file for Marvell Armada 38x family of SoCs. | ||
| 3 | * | ||
| 4 | * Copyright (C) 2014 Marvell | ||
| 5 | * | ||
| 6 | * Lior Amsalem <alior@marvell.com> | ||
| 7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | ||
| 8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | ||
| 9 | * | ||
| 10 | * This file is licensed under the terms of the GNU General Public | ||
| 11 | * License version 2. This program is licensed "as is" without any | ||
| 12 | * warranty of any kind, whether express or implied. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include "skeleton.dtsi" | ||
| 16 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 17 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 18 | |||
| 19 | #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) | ||
| 20 | |||
| 21 | / { | ||
| 22 | model = "Marvell Armada 38x family SoC"; | ||
| 23 | compatible = "marvell,armada38x"; | ||
| 24 | |||
| 25 | aliases { | ||
| 26 | gpio0 = &gpio0; | ||
| 27 | gpio1 = &gpio1; | ||
| 28 | eth0 = ð0; | ||
| 29 | eth1 = ð1; | ||
| 30 | eth2 = ð2; | ||
| 31 | }; | ||
| 32 | |||
| 33 | soc { | ||
| 34 | compatible = "marvell,armada380-mbus", "marvell,armada370-mbus", | ||
| 35 | "simple-bus"; | ||
| 36 | #address-cells = <2>; | ||
| 37 | #size-cells = <1>; | ||
| 38 | controller = <&mbusc>; | ||
| 39 | interrupt-parent = <&gic>; | ||
| 40 | pcie-mem-aperture = <0xe0000000 0x8000000>; | ||
| 41 | pcie-io-aperture = <0xe8000000 0x100000>; | ||
| 42 | |||
| 43 | bootrom { | ||
| 44 | compatible = "marvell,bootrom"; | ||
| 45 | reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>; | ||
| 46 | }; | ||
| 47 | |||
| 48 | devbus-bootcs { | ||
| 49 | compatible = "marvell,mvebu-devbus"; | ||
| 50 | reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>; | ||
| 51 | ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; | ||
| 52 | #address-cells = <1>; | ||
| 53 | #size-cells = <1>; | ||
| 54 | clocks = <&coreclk 0>; | ||
| 55 | status = "disabled"; | ||
| 56 | }; | ||
| 57 | |||
| 58 | devbus-cs0 { | ||
| 59 | compatible = "marvell,mvebu-devbus"; | ||
| 60 | reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>; | ||
| 61 | ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; | ||
| 62 | #address-cells = <1>; | ||
| 63 | #size-cells = <1>; | ||
| 64 | clocks = <&coreclk 0>; | ||
| 65 | status = "disabled"; | ||
| 66 | }; | ||
| 67 | |||
| 68 | devbus-cs1 { | ||
| 69 | compatible = "marvell,mvebu-devbus"; | ||
| 70 | reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>; | ||
| 71 | ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; | ||
| 72 | #address-cells = <1>; | ||
| 73 | #size-cells = <1>; | ||
| 74 | clocks = <&coreclk 0>; | ||
| 75 | status = "disabled"; | ||
| 76 | }; | ||
| 77 | |||
| 78 | devbus-cs2 { | ||
| 79 | compatible = "marvell,mvebu-devbus"; | ||
| 80 | reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>; | ||
| 81 | ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; | ||
| 82 | #address-cells = <1>; | ||
| 83 | #size-cells = <1>; | ||
| 84 | clocks = <&coreclk 0>; | ||
| 85 | status = "disabled"; | ||
| 86 | }; | ||
| 87 | |||
| 88 | devbus-cs3 { | ||
| 89 | compatible = "marvell,mvebu-devbus"; | ||
| 90 | reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>; | ||
| 91 | ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; | ||
| 92 | #address-cells = <1>; | ||
| 93 | #size-cells = <1>; | ||
| 94 | clocks = <&coreclk 0>; | ||
| 95 | status = "disabled"; | ||
| 96 | }; | ||
| 97 | |||
| 98 | internal-regs { | ||
| 99 | compatible = "simple-bus"; | ||
| 100 | #address-cells = <1>; | ||
| 101 | #size-cells = <1>; | ||
| 102 | ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; | ||
| 103 | |||
| 104 | L2: cache-controller@8000 { | ||
| 105 | compatible = "arm,pl310-cache"; | ||
| 106 | reg = <0x8000 0x1000>; | ||
| 107 | cache-unified; | ||
| 108 | cache-level = <2>; | ||
| 109 | }; | ||
| 110 | |||
| 111 | timer@c600 { | ||
| 112 | compatible = "arm,cortex-a9-twd-timer"; | ||
| 113 | reg = <0xc600 0x20>; | ||
| 114 | interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; | ||
| 115 | clocks = <&coreclk 2>; | ||
| 116 | }; | ||
| 117 | |||
| 118 | gic: interrupt-controller@d000 { | ||
| 119 | compatible = "arm,cortex-a9-gic"; | ||
| 120 | #interrupt-cells = <3>; | ||
| 121 | #size-cells = <0>; | ||
| 122 | interrupt-controller; | ||
| 123 | reg = <0xd000 0x1000>, | ||
| 124 | <0xc100 0x100>; | ||
| 125 | }; | ||
| 126 | |||
| 127 | spi0: spi@10600 { | ||
| 128 | compatible = "marvell,orion-spi"; | ||
| 129 | reg = <0x10600 0x50>; | ||
| 130 | #address-cells = <1>; | ||
| 131 | #size-cells = <0>; | ||
| 132 | cell-index = <0>; | ||
| 133 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; | ||
| 134 | clocks = <&coreclk 0>; | ||
| 135 | status = "disabled"; | ||
| 136 | }; | ||
| 137 | |||
| 138 | spi1: spi@10680 { | ||
| 139 | compatible = "marvell,orion-spi"; | ||
| 140 | reg = <0x10680 0x50>; | ||
| 141 | #address-cells = <1>; | ||
| 142 | #size-cells = <0>; | ||
| 143 | cell-index = <1>; | ||
| 144 | interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; | ||
| 145 | clocks = <&coreclk 0>; | ||
| 146 | status = "disabled"; | ||
| 147 | }; | ||
| 148 | |||
| 149 | i2c0: i2c@11000 { | ||
| 150 | compatible = "marvell,mv64xxx-i2c"; | ||
| 151 | reg = <0x11000 0x20>; | ||
| 152 | #address-cells = <1>; | ||
| 153 | #size-cells = <0>; | ||
| 154 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; | ||
| 155 | timeout-ms = <1000>; | ||
| 156 | clocks = <&coreclk 0>; | ||
| 157 | status = "disabled"; | ||
| 158 | }; | ||
| 159 | |||
| 160 | i2c1: i2c@11100 { | ||
| 161 | compatible = "marvell,mv64xxx-i2c"; | ||
| 162 | reg = <0x11100 0x20>; | ||
| 163 | #address-cells = <1>; | ||
| 164 | #size-cells = <0>; | ||
| 165 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; | ||
| 166 | timeout-ms = <1000>; | ||
| 167 | clocks = <&coreclk 0>; | ||
| 168 | status = "disabled"; | ||
| 169 | }; | ||
| 170 | |||
| 171 | serial@12000 { | ||
| 172 | compatible = "snps,dw-apb-uart"; | ||
| 173 | reg = <0x12000 0x100>; | ||
| 174 | reg-shift = <2>; | ||
| 175 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; | ||
| 176 | reg-io-width = <1>; | ||
| 177 | status = "disabled"; | ||
| 178 | }; | ||
| 179 | |||
| 180 | serial@12100 { | ||
| 181 | compatible = "snps,dw-apb-uart"; | ||
| 182 | reg = <0x12100 0x100>; | ||
| 183 | reg-shift = <2>; | ||
| 184 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; | ||
| 185 | reg-io-width = <1>; | ||
| 186 | status = "disabled"; | ||
| 187 | }; | ||
| 188 | |||
| 189 | pinctrl { | ||
| 190 | compatible = "marvell,mv88f6820-pinctrl"; | ||
| 191 | reg = <0x18000 0x20>; | ||
| 192 | }; | ||
| 193 | |||
| 194 | gpio0: gpio@18100 { | ||
| 195 | compatible = "marvell,orion-gpio"; | ||
| 196 | reg = <0x18100 0x40>; | ||
| 197 | ngpios = <32>; | ||
| 198 | gpio-controller; | ||
| 199 | #gpio-cells = <2>; | ||
| 200 | interrupt-controller; | ||
| 201 | #interrupt-cells = <2>; | ||
| 202 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, | ||
| 203 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, | ||
| 204 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | ||
| 205 | <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; | ||
| 206 | }; | ||
| 207 | |||
| 208 | gpio1: gpio@18140 { | ||
| 209 | compatible = "marvell,orion-gpio"; | ||
| 210 | reg = <0x18140 0x40>; | ||
| 211 | ngpios = <28>; | ||
| 212 | gpio-controller; | ||
| 213 | #gpio-cells = <2>; | ||
| 214 | interrupt-controller; | ||
| 215 | #interrupt-cells = <2>; | ||
| 216 | interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, | ||
| 217 | <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, | ||
| 218 | <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, | ||
| 219 | <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; | ||
| 220 | }; | ||
| 221 | |||
| 222 | system-controller@18200 { | ||
| 223 | compatible = "marvell,armada-380-system-controller", | ||
| 224 | "marvell,armada-370-xp-system-controller"; | ||
| 225 | reg = <0x18200 0x100>; | ||
| 226 | }; | ||
| 227 | |||
| 228 | gateclk: clock-gating-control@18220 { | ||
| 229 | compatible = "marvell,armada-380-gating-clock"; | ||
| 230 | reg = <0x18220 0x4>; | ||
| 231 | clocks = <&coreclk 0>; | ||
| 232 | #clock-cells = <1>; | ||
| 233 | }; | ||
| 234 | |||
| 235 | coreclk: mvebu-sar@18600 { | ||
| 236 | compatible = "marvell,armada-380-core-clock"; | ||
| 237 | reg = <0x18600 0x04>; | ||
| 238 | #clock-cells = <1>; | ||
| 239 | }; | ||
| 240 | |||
| 241 | mbusc: mbus-controller@20000 { | ||
| 242 | compatible = "marvell,mbus-controller"; | ||
| 243 | reg = <0x20000 0x100>, <0x20180 0x20>; | ||
| 244 | }; | ||
| 245 | |||
| 246 | mpic: interrupt-controller@20000 { | ||
| 247 | compatible = "marvell,mpic"; | ||
| 248 | reg = <0x20a00 0x2d0>, <0x21070 0x58>; | ||
| 249 | #interrupt-cells = <1>; | ||
| 250 | #size-cells = <1>; | ||
| 251 | interrupt-controller; | ||
| 252 | msi-controller; | ||
| 253 | interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; | ||
| 254 | }; | ||
| 255 | |||
| 256 | timer@20300 { | ||
| 257 | compatible = "marvell,armada-380-timer", | ||
| 258 | "marvell,armada-xp-timer"; | ||
| 259 | reg = <0x20300 0x30>, <0x21040 0x30>; | ||
| 260 | interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, | ||
| 261 | <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, | ||
| 262 | <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, | ||
| 263 | <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, | ||
| 264 | <&mpic 5>, | ||
| 265 | <&mpic 6>; | ||
| 266 | clocks = <&coreclk 2>, <&refclk>; | ||
| 267 | clock-names = "nbclk", "fixed"; | ||
| 268 | }; | ||
| 269 | |||
| 270 | eth1: ethernet@30000 { | ||
| 271 | compatible = "marvell,armada-370-neta"; | ||
| 272 | reg = <0x30000 0x4000>; | ||
| 273 | interrupts-extended = <&mpic 10>; | ||
| 274 | clocks = <&gateclk 3>; | ||
| 275 | status = "disabled"; | ||
| 276 | }; | ||
| 277 | |||
| 278 | eth2: ethernet@34000 { | ||
| 279 | compatible = "marvell,armada-370-neta"; | ||
| 280 | reg = <0x34000 0x4000>; | ||
| 281 | interrupts-extended = <&mpic 12>; | ||
| 282 | clocks = <&gateclk 2>; | ||
| 283 | status = "disabled"; | ||
| 284 | }; | ||
| 285 | |||
| 286 | xor@60800 { | ||
| 287 | compatible = "marvell,orion-xor"; | ||
| 288 | reg = <0x60800 0x100 | ||
| 289 | 0x60a00 0x100>; | ||
| 290 | clocks = <&gateclk 22>; | ||
| 291 | status = "okay"; | ||
| 292 | |||
| 293 | xor00 { | ||
| 294 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; | ||
| 295 | dmacap,memcpy; | ||
| 296 | dmacap,xor; | ||
| 297 | }; | ||
| 298 | xor01 { | ||
| 299 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | ||
| 300 | dmacap,memcpy; | ||
| 301 | dmacap,xor; | ||
| 302 | dmacap,memset; | ||
| 303 | }; | ||
| 304 | }; | ||
| 305 | |||
| 306 | xor@60900 { | ||
| 307 | compatible = "marvell,orion-xor"; | ||
| 308 | reg = <0x60900 0x100 | ||
| 309 | 0x60b00 0x100>; | ||
| 310 | clocks = <&gateclk 28>; | ||
| 311 | status = "okay"; | ||
| 312 | |||
| 313 | xor10 { | ||
| 314 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; | ||
| 315 | dmacap,memcpy; | ||
| 316 | dmacap,xor; | ||
| 317 | }; | ||
| 318 | xor11 { | ||
| 319 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; | ||
| 320 | dmacap,memcpy; | ||
| 321 | dmacap,xor; | ||
| 322 | dmacap,memset; | ||
| 323 | }; | ||
| 324 | }; | ||
| 325 | |||
| 326 | eth0: ethernet@70000 { | ||
| 327 | compatible = "marvell,armada-370-neta"; | ||
| 328 | reg = <0x70000 0x4000>; | ||
| 329 | interrupts-extended = <&mpic 8>; | ||
| 330 | clocks = <&gateclk 4>; | ||
| 331 | status = "disabled"; | ||
| 332 | }; | ||
| 333 | |||
| 334 | mdio { | ||
| 335 | #address-cells = <1>; | ||
| 336 | #size-cells = <0>; | ||
| 337 | compatible = "marvell,orion-mdio"; | ||
| 338 | reg = <0x72004 0x4>; | ||
| 339 | }; | ||
| 340 | |||
| 341 | coredivclk: clock@e4250 { | ||
| 342 | compatible = "marvell,armada-380-corediv-clock"; | ||
| 343 | reg = <0xe4250 0xc>; | ||
| 344 | #clock-cells = <1>; | ||
| 345 | clocks = <&mainpll>; | ||
| 346 | clock-output-names = "nand"; | ||
| 347 | }; | ||
| 348 | |||
| 349 | flash@d0000 { | ||
| 350 | compatible = "marvell,armada370-nand"; | ||
| 351 | reg = <0xd0000 0x54>; | ||
| 352 | #address-cells = <1>; | ||
| 353 | #size-cells = <1>; | ||
| 354 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | ||
| 355 | clocks = <&coredivclk 0>; | ||
| 356 | status = "disabled"; | ||
| 357 | }; | ||
| 358 | }; | ||
| 359 | }; | ||
| 360 | |||
| 361 | clocks { | ||
| 362 | /* 2 GHz fixed main PLL */ | ||
| 363 | mainpll: mainpll { | ||
| 364 | compatible = "fixed-clock"; | ||
| 365 | #clock-cells = <0>; | ||
| 366 | clock-frequency = <2000000000>; | ||
| 367 | }; | ||
| 368 | |||
| 369 | /* 25 MHz reference crystal */ | ||
| 370 | refclk: oscillator { | ||
| 371 | compatible = "fixed-clock"; | ||
| 372 | #clock-cells = <0>; | ||
| 373 | clock-frequency = <25000000>; | ||
| 374 | }; | ||
| 375 | }; | ||
| 376 | }; | ||
diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts index c5fe57269f5a..d83d7d69ac01 100644 --- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts +++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts | |||
| @@ -16,6 +16,8 @@ | |||
| 16 | */ | 16 | */ |
| 17 | 17 | ||
| 18 | /dts-v1/; | 18 | /dts-v1/; |
| 19 | #include <dt-bindings/gpio/gpio.h> | ||
| 20 | #include <dt-bindings/input/input.h> | ||
| 19 | #include "armada-xp-mv78230.dtsi" | 21 | #include "armada-xp-mv78230.dtsi" |
| 20 | 22 | ||
| 21 | / { | 23 | / { |
| @@ -157,8 +159,8 @@ | |||
| 157 | 159 | ||
| 158 | button@1 { | 160 | button@1 { |
| 159 | label = "Factory Reset Button"; | 161 | label = "Factory Reset Button"; |
| 160 | linux,code = <141>; /* KEY_SETUP */ | 162 | linux,code = <KEY_SETUP>; |
| 161 | gpios = <&gpio1 1 1>; | 163 | gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; |
| 162 | }; | 164 | }; |
| 163 | }; | 165 | }; |
| 164 | }; | 166 | }; |
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts index bcf6d79a57ec..448373c4b0e5 100644 --- a/arch/arm/boot/dts/armada-xp-db.dts +++ b/arch/arm/boot/dts/armada-xp-db.dts | |||
| @@ -2,7 +2,7 @@ | |||
| 2 | * Device Tree file for Marvell Armada XP evaluation board | 2 | * Device Tree file for Marvell Armada XP evaluation board |
| 3 | * (DB-78460-BP) | 3 | * (DB-78460-BP) |
| 4 | * | 4 | * |
| 5 | * Copyright (C) 2012 Marvell | 5 | * Copyright (C) 2012-2014 Marvell |
| 6 | * | 6 | * |
| 7 | * Lior Amsalem <alior@marvell.com> | 7 | * Lior Amsalem <alior@marvell.com> |
| 8 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | 8 | * Gregory CLEMENT <gregory.clement@free-electrons.com> |
| @@ -11,6 +11,15 @@ | |||
| 11 | * This file is licensed under the terms of the GNU General Public | 11 | * This file is licensed under the terms of the GNU General Public |
| 12 | * License version 2. This program is licensed "as is" without any | 12 | * License version 2. This program is licensed "as is" without any |
| 13 | * warranty of any kind, whether express or implied. | 13 | * warranty of any kind, whether express or implied. |
| 14 | * | ||
| 15 | * Note: this Device Tree assumes that the bootloader has remapped the | ||
| 16 | * internal registers to 0xf1000000 (instead of the default | ||
| 17 | * 0xd0000000). The 0xf1000000 is the default used by the recent, | ||
| 18 | * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier | ||
| 19 | * boards were delivered with an older version of the bootloader that | ||
| 20 | * left internal registers mapped at 0xd0000000. If you are in this | ||
| 21 | * situation, you should either update your bootloader (preferred | ||
| 22 | * solution) or the below Device Tree should be adjusted. | ||
| 14 | */ | 23 | */ |
| 15 | 24 | ||
| 16 | /dts-v1/; | 25 | /dts-v1/; |
| @@ -30,7 +39,7 @@ | |||
| 30 | }; | 39 | }; |
| 31 | 40 | ||
| 32 | soc { | 41 | soc { |
| 33 | ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 | 42 | ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 |
| 34 | MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 | 43 | MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 |
| 35 | MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; | 44 | MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; |
| 36 | 45 | ||
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts index 274e2ad5f51c..61bda687f782 100644 --- a/arch/arm/boot/dts/armada-xp-gp.dts +++ b/arch/arm/boot/dts/armada-xp-gp.dts | |||
| @@ -2,7 +2,7 @@ | |||
| 2 | * Device Tree file for Marvell Armada XP development board | 2 | * Device Tree file for Marvell Armada XP development board |
| 3 | * (DB-MV784MP-GP) | 3 | * (DB-MV784MP-GP) |
| 4 | * | 4 | * |
| 5 | * Copyright (C) 2013 Marvell | 5 | * Copyright (C) 2013-2014 Marvell |
| 6 | * | 6 | * |
| 7 | * Lior Amsalem <alior@marvell.com> | 7 | * Lior Amsalem <alior@marvell.com> |
| 8 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | 8 | * Gregory CLEMENT <gregory.clement@free-electrons.com> |
| @@ -11,6 +11,15 @@ | |||
| 11 | * This file is licensed under the terms of the GNU General Public | 11 | * This file is licensed under the terms of the GNU General Public |
| 12 | * License version 2. This program is licensed "as is" without any | 12 | * License version 2. This program is licensed "as is" without any |
| 13 | * warranty of any kind, whether express or implied. | 13 | * warranty of any kind, whether express or implied. |
| 14 | * | ||
| 15 | * Note: this Device Tree assumes that the bootloader has remapped the | ||
| 16 | * internal registers to 0xf1000000 (instead of the default | ||
| 17 | * 0xd0000000). The 0xf1000000 is the default used by the recent, | ||
| 18 | * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier | ||
| 19 | * boards were delivered with an older version of the bootloader that | ||
| 20 | * left internal registers mapped at 0xd0000000. If you are in this | ||
| 21 | * situation, you should either update your bootloader (preferred | ||
| 22 | * solution) or the below Device Tree should be adjusted. | ||
| 14 | */ | 23 | */ |
| 15 | 24 | ||
| 16 | /dts-v1/; | 25 | /dts-v1/; |
| @@ -30,16 +39,17 @@ | |||
| 30 | * 8 GB of plug-in RAM modules by default.The amount | 39 | * 8 GB of plug-in RAM modules by default.The amount |
| 31 | * of memory available can be changed by the | 40 | * of memory available can be changed by the |
| 32 | * bootloader according the size of the module | 41 | * bootloader according the size of the module |
| 33 | * actually plugged. Only 7GB are usable because | 42 | * actually plugged. However, memory between |
| 34 | * addresses from 0xC0000000 to 0xffffffff are used by | 43 | * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is |
| 35 | * the internal registers of the SoC. | 44 | * the address range used for I/O (internal registers, |
| 45 | * MBus windows). | ||
| 36 | */ | 46 | */ |
| 37 | reg = <0x00000000 0x00000000 0x00000000 0xC0000000>, | 47 | reg = <0x00000000 0x00000000 0x00000000 0xf0000000>, |
| 38 | <0x00000001 0x00000000 0x00000001 0x00000000>; | 48 | <0x00000001 0x00000000 0x00000001 0x00000000>; |
| 39 | }; | 49 | }; |
| 40 | 50 | ||
| 41 | soc { | 51 | soc { |
| 42 | ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 | 52 | ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 |
| 43 | MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 | 53 | MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 |
| 44 | MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; | 54 | MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; |
| 45 | 55 | ||
diff --git a/arch/arm/boot/dts/armada-xp-matrix.dts b/arch/arm/boot/dts/armada-xp-matrix.dts index e47c49ecd55c..c2242745b9b8 100644 --- a/arch/arm/boot/dts/armada-xp-matrix.dts +++ b/arch/arm/boot/dts/armada-xp-matrix.dts | |||
| @@ -23,7 +23,12 @@ | |||
| 23 | 23 | ||
| 24 | memory { | 24 | memory { |
| 25 | device_type = "memory"; | 25 | device_type = "memory"; |
| 26 | reg = <0 0x00000000 0 0x80000000>; /* 2 GB */ | 26 | /* |
| 27 | * This board has 4 GB of RAM, but the last 256 MB of | ||
| 28 | * RAM are not usable due to the overlap with the MBus | ||
| 29 | * Window address range | ||
| 30 | */ | ||
| 31 | reg = <0 0x00000000 0 0xf0000000>; | ||
| 27 | }; | 32 | }; |
| 28 | 33 | ||
| 29 | soc { | 34 | soc { |
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index 99bcf76e6953..985948ce67b3 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | |||
| @@ -11,6 +11,8 @@ | |||
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | /dts-v1/; | 13 | /dts-v1/; |
| 14 | #include <dt-bindings/gpio/gpio.h> | ||
| 15 | #include <dt-bindings/input/input.h> | ||
| 14 | #include "armada-xp-mv78260.dtsi" | 16 | #include "armada-xp-mv78260.dtsi" |
| 15 | 17 | ||
| 16 | / { | 18 | / { |
| @@ -90,19 +92,19 @@ | |||
| 90 | 92 | ||
| 91 | red_led { | 93 | red_led { |
| 92 | label = "red_led"; | 94 | label = "red_led"; |
| 93 | gpios = <&gpio1 17 1>; | 95 | gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; |
| 94 | default-state = "off"; | 96 | default-state = "off"; |
| 95 | }; | 97 | }; |
| 96 | 98 | ||
| 97 | yellow_led { | 99 | yellow_led { |
| 98 | label = "yellow_led"; | 100 | label = "yellow_led"; |
| 99 | gpios = <&gpio1 19 1>; | 101 | gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; |
| 100 | default-state = "off"; | 102 | default-state = "off"; |
| 101 | }; | 103 | }; |
| 102 | 104 | ||
| 103 | green_led { | 105 | green_led { |
| 104 | label = "green_led"; | 106 | label = "green_led"; |
| 105 | gpios = <&gpio1 21 1>; | 107 | gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; |
| 106 | default-state = "keep"; | 108 | default-state = "keep"; |
| 107 | }; | 109 | }; |
| 108 | }; | 110 | }; |
| @@ -114,8 +116,8 @@ | |||
| 114 | 116 | ||
| 115 | button@1 { | 117 | button@1 { |
| 116 | label = "Init Button"; | 118 | label = "Init Button"; |
| 117 | linux,code = <116>; | 119 | linux,code = <KEY_POWER>; |
| 118 | gpios = <&gpio1 28 0>; | 120 | gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; |
| 119 | }; | 121 | }; |
| 120 | }; | 122 | }; |
| 121 | 123 | ||
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index b8b84a22f0f3..abb9f9dcc525 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi | |||
| @@ -111,6 +111,12 @@ | |||
| 111 | clock-names = "nbclk", "fixed"; | 111 | clock-names = "nbclk", "fixed"; |
| 112 | }; | 112 | }; |
| 113 | 113 | ||
| 114 | watchdog@20300 { | ||
| 115 | compatible = "marvell,armada-xp-wdt"; | ||
| 116 | clocks = <&coreclk 2>, <&refclk>; | ||
| 117 | clock-names = "nbclk", "fixed"; | ||
| 118 | }; | ||
| 119 | |||
| 114 | armada-370-xp-pmsu@22000 { | 120 | armada-370-xp-pmsu@22000 { |
| 115 | compatible = "marvell,armada-370-xp-pmsu"; | 121 | compatible = "marvell,armada-370-xp-pmsu"; |
| 116 | reg = <0x22100 0x400>, <0x20800 0x20>; | 122 | reg = <0x22100 0x400>, <0x20800 0x20>; |
diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/at91-ariag25.dts index cce45f5177f9..55ab6180e350 100644 --- a/arch/arm/boot/dts/at91-ariag25.dts +++ b/arch/arm/boot/dts/at91-ariag25.dts | |||
| @@ -129,7 +129,6 @@ | |||
| 129 | adc0: adc@f804c000 { | 129 | adc0: adc@f804c000 { |
| 130 | status = "okay"; | 130 | status = "okay"; |
| 131 | atmel,adc-channels-used = <0xf>; | 131 | atmel,adc-channels-used = <0xf>; |
| 132 | atmel,adc-num-channels = <4>; | ||
| 133 | }; | 132 | }; |
| 134 | 133 | ||
| 135 | dbgu: serial@fffff200 { | 134 | dbgu: serial@fffff200 { |
diff --git a/arch/arm/boot/dts/at91-cosino.dtsi b/arch/arm/boot/dts/at91-cosino.dtsi index 2093c4d7cd6a..df4b78695695 100644 --- a/arch/arm/boot/dts/at91-cosino.dtsi +++ b/arch/arm/boot/dts/at91-cosino.dtsi | |||
| @@ -64,7 +64,6 @@ | |||
| 64 | }; | 64 | }; |
| 65 | 65 | ||
| 66 | adc0: adc@f804c000 { | 66 | adc0: adc@f804c000 { |
| 67 | atmel,adc-clock-rate = <1000000>; | ||
| 68 | atmel,adc-ts-wires = <4>; | 67 | atmel,adc-ts-wires = <4>; |
| 69 | atmel,adc-ts-pressure-threshold = <10000>; | 68 | atmel,adc-ts-pressure-threshold = <10000>; |
| 70 | status = "okay"; | 69 | status = "okay"; |
diff --git a/arch/arm/boot/dts/at91-cosino_mega2560.dts b/arch/arm/boot/dts/at91-cosino_mega2560.dts index f9415dd11f17..a542d5837a17 100644 --- a/arch/arm/boot/dts/at91-cosino_mega2560.dts +++ b/arch/arm/boot/dts/at91-cosino_mega2560.dts | |||
| @@ -27,7 +27,6 @@ | |||
| 27 | }; | 27 | }; |
| 28 | 28 | ||
| 29 | adc0: adc@f804c000 { | 29 | adc0: adc@f804c000 { |
| 30 | atmel,adc-clock-rate = <1000000>; | ||
| 31 | atmel,adc-ts-wires = <4>; | 30 | atmel,adc-ts-wires = <4>; |
| 32 | atmel,adc-ts-pressure-threshold = <10000>; | 31 | atmel,adc-ts-pressure-threshold = <10000>; |
| 33 | status = "okay"; | 32 | status = "okay"; |
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 997901f7ed73..366fc2cbcd64 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi | |||
| @@ -608,37 +608,38 @@ | |||
| 608 | }; | 608 | }; |
| 609 | 609 | ||
| 610 | adc0: adc@fffe0000 { | 610 | adc0: adc@fffe0000 { |
| 611 | #address-cells = <1>; | ||
| 612 | #size-cells = <0>; | ||
| 611 | compatible = "atmel,at91sam9260-adc"; | 613 | compatible = "atmel,at91sam9260-adc"; |
| 612 | reg = <0xfffe0000 0x100>; | 614 | reg = <0xfffe0000 0x100>; |
| 613 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>; | 615 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>; |
| 614 | atmel,adc-use-external-triggers; | 616 | atmel,adc-use-external-triggers; |
| 615 | atmel,adc-channels-used = <0xf>; | 617 | atmel,adc-channels-used = <0xf>; |
| 616 | atmel,adc-vref = <3300>; | 618 | atmel,adc-vref = <3300>; |
| 617 | atmel,adc-num-channels = <4>; | ||
| 618 | atmel,adc-startup-time = <15>; | 619 | atmel,adc-startup-time = <15>; |
| 619 | atmel,adc-channel-base = <0x30>; | ||
| 620 | atmel,adc-drdy-mask = <0x10000>; | ||
| 621 | atmel,adc-status-register = <0x1c>; | ||
| 622 | atmel,adc-trigger-register = <0x04>; | ||
| 623 | atmel,adc-res = <8 10>; | 620 | atmel,adc-res = <8 10>; |
| 624 | atmel,adc-res-names = "lowres", "highres"; | 621 | atmel,adc-res-names = "lowres", "highres"; |
| 625 | atmel,adc-use-res = "highres"; | 622 | atmel,adc-use-res = "highres"; |
| 626 | 623 | ||
| 627 | trigger@0 { | 624 | trigger@0 { |
| 625 | reg = <0>; | ||
| 628 | trigger-name = "timer-counter-0"; | 626 | trigger-name = "timer-counter-0"; |
| 629 | trigger-value = <0x1>; | 627 | trigger-value = <0x1>; |
| 630 | }; | 628 | }; |
| 631 | trigger@1 { | 629 | trigger@1 { |
| 630 | reg = <1>; | ||
| 632 | trigger-name = "timer-counter-1"; | 631 | trigger-name = "timer-counter-1"; |
| 633 | trigger-value = <0x3>; | 632 | trigger-value = <0x3>; |
| 634 | }; | 633 | }; |
| 635 | 634 | ||
| 636 | trigger@2 { | 635 | trigger@2 { |
| 636 | reg = <2>; | ||
| 637 | trigger-name = "timer-counter-2"; | 637 | trigger-name = "timer-counter-2"; |
| 638 | trigger-value = <0x5>; | 638 | trigger-value = <0x5>; |
| 639 | }; | 639 | }; |
| 640 | 640 | ||
| 641 | trigger@3 { | 641 | trigger@3 { |
| 642 | reg = <3>; | ||
| 642 | trigger-name = "external"; | 643 | trigger-name = "external"; |
| 643 | trigger-value = <0x13>; | 644 | trigger-value = <0x13>; |
| 644 | trigger-external; | 645 | trigger-external; |
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index cbcc058b26b4..9cdaecff13b3 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi | |||
| @@ -632,40 +632,41 @@ | |||
| 632 | }; | 632 | }; |
| 633 | 633 | ||
| 634 | adc0: adc@fffb0000 { | 634 | adc0: adc@fffb0000 { |
| 635 | #address-cells = <1>; | ||
| 636 | #size-cells = <0>; | ||
| 635 | compatible = "atmel,at91sam9260-adc"; | 637 | compatible = "atmel,at91sam9260-adc"; |
| 636 | reg = <0xfffb0000 0x100>; | 638 | reg = <0xfffb0000 0x100>; |
| 637 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; | 639 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; |
| 638 | atmel,adc-use-external-triggers; | 640 | atmel,adc-use-external-triggers; |
| 639 | atmel,adc-channels-used = <0xff>; | 641 | atmel,adc-channels-used = <0xff>; |
| 640 | atmel,adc-vref = <3300>; | 642 | atmel,adc-vref = <3300>; |
| 641 | atmel,adc-num-channels = <8>; | ||
| 642 | atmel,adc-startup-time = <40>; | 643 | atmel,adc-startup-time = <40>; |
| 643 | atmel,adc-channel-base = <0x30>; | ||
| 644 | atmel,adc-drdy-mask = <0x10000>; | ||
| 645 | atmel,adc-status-register = <0x1c>; | ||
| 646 | atmel,adc-trigger-register = <0x08>; | ||
| 647 | atmel,adc-res = <8 10>; | 644 | atmel,adc-res = <8 10>; |
| 648 | atmel,adc-res-names = "lowres", "highres"; | 645 | atmel,adc-res-names = "lowres", "highres"; |
| 649 | atmel,adc-use-res = "highres"; | 646 | atmel,adc-use-res = "highres"; |
| 650 | 647 | ||
| 651 | trigger@0 { | 648 | trigger@0 { |
| 649 | reg = <0>; | ||
| 652 | trigger-name = "external-rising"; | 650 | trigger-name = "external-rising"; |
| 653 | trigger-value = <0x1>; | 651 | trigger-value = <0x1>; |
| 654 | trigger-external; | 652 | trigger-external; |
| 655 | }; | 653 | }; |
| 656 | trigger@1 { | 654 | trigger@1 { |
| 655 | reg = <1>; | ||
| 657 | trigger-name = "external-falling"; | 656 | trigger-name = "external-falling"; |
| 658 | trigger-value = <0x2>; | 657 | trigger-value = <0x2>; |
| 659 | trigger-external; | 658 | trigger-external; |
| 660 | }; | 659 | }; |
| 661 | 660 | ||
| 662 | trigger@2 { | 661 | trigger@2 { |
| 662 | reg = <2>; | ||
| 663 | trigger-name = "external-any"; | 663 | trigger-name = "external-any"; |
| 664 | trigger-value = <0x3>; | 664 | trigger-value = <0x3>; |
| 665 | trigger-external; | 665 | trigger-external; |
| 666 | }; | 666 | }; |
| 667 | 667 | ||
| 668 | trigger@3 { | 668 | trigger@3 { |
| 669 | reg = <3>; | ||
| 669 | trigger-name = "continuous"; | 670 | trigger-name = "continuous"; |
| 670 | trigger-value = <0x6>; | 671 | trigger-value = <0x6>; |
| 671 | }; | 672 | }; |
| @@ -817,6 +818,7 @@ | |||
| 817 | >; | 818 | >; |
| 818 | atmel,nand-addr-offset = <21>; | 819 | atmel,nand-addr-offset = <21>; |
| 819 | atmel,nand-cmd-offset = <22>; | 820 | atmel,nand-cmd-offset = <22>; |
| 821 | atmel,nand-has-dma; | ||
| 820 | pinctrl-names = "default"; | 822 | pinctrl-names = "default"; |
| 821 | pinctrl-0 = <&pinctrl_nand>; | 823 | pinctrl-0 = <&pinctrl_nand>; |
| 822 | gpios = <&pioC 8 GPIO_ACTIVE_HIGH | 824 | gpios = <&pioC 8 GPIO_ACTIVE_HIGH |
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 394e6ce2afb7..9f04808fc697 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi | |||
| @@ -570,6 +570,7 @@ | |||
| 570 | atmel,pmecc-lookup-table-offset = <0x0 0x8000>; | 570 | atmel,pmecc-lookup-table-offset = <0x0 0x8000>; |
| 571 | atmel,nand-addr-offset = <21>; | 571 | atmel,nand-addr-offset = <21>; |
| 572 | atmel,nand-cmd-offset = <22>; | 572 | atmel,nand-cmd-offset = <22>; |
| 573 | atmel,nand-has-dma; | ||
| 573 | pinctrl-names = "default"; | 574 | pinctrl-names = "default"; |
| 574 | pinctrl-0 = <&pinctrl_nand>; | 575 | pinctrl-0 = <&pinctrl_nand>; |
| 575 | gpios = <&pioD 5 GPIO_ACTIVE_HIGH | 576 | gpios = <&pioD 5 GPIO_ACTIVE_HIGH |
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 174219de92fa..fc13c9240da8 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi | |||
| @@ -621,41 +621,42 @@ | |||
| 621 | }; | 621 | }; |
| 622 | 622 | ||
| 623 | adc0: adc@f804c000 { | 623 | adc0: adc@f804c000 { |
| 624 | #address-cells = <1>; | ||
| 625 | #size-cells = <0>; | ||
| 624 | compatible = "atmel,at91sam9260-adc"; | 626 | compatible = "atmel,at91sam9260-adc"; |
| 625 | reg = <0xf804c000 0x100>; | 627 | reg = <0xf804c000 0x100>; |
| 626 | interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; | 628 | interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; |
| 627 | atmel,adc-use-external; | 629 | atmel,adc-use-external-triggers; |
| 628 | atmel,adc-channels-used = <0xffff>; | 630 | atmel,adc-channels-used = <0xffff>; |
| 629 | atmel,adc-vref = <3300>; | 631 | atmel,adc-vref = <3300>; |
| 630 | atmel,adc-num-channels = <12>; | ||
| 631 | atmel,adc-startup-time = <40>; | 632 | atmel,adc-startup-time = <40>; |
| 632 | atmel,adc-channel-base = <0x50>; | ||
| 633 | atmel,adc-drdy-mask = <0x1000000>; | ||
| 634 | atmel,adc-status-register = <0x30>; | ||
| 635 | atmel,adc-trigger-register = <0xc0>; | ||
| 636 | atmel,adc-res = <8 10>; | 633 | atmel,adc-res = <8 10>; |
| 637 | atmel,adc-res-names = "lowres", "highres"; | 634 | atmel,adc-res-names = "lowres", "highres"; |
| 638 | atmel,adc-use-res = "highres"; | 635 | atmel,adc-use-res = "highres"; |
| 639 | 636 | ||
| 640 | trigger@0 { | 637 | trigger@0 { |
| 638 | reg = <0>; | ||
| 641 | trigger-name = "external-rising"; | 639 | trigger-name = "external-rising"; |
| 642 | trigger-value = <0x1>; | 640 | trigger-value = <0x1>; |
| 643 | trigger-external; | 641 | trigger-external; |
| 644 | }; | 642 | }; |
| 645 | 643 | ||
| 646 | trigger@1 { | 644 | trigger@1 { |
| 645 | reg = <1>; | ||
| 647 | trigger-name = "external-falling"; | 646 | trigger-name = "external-falling"; |
| 648 | trigger-value = <0x2>; | 647 | trigger-value = <0x2>; |
| 649 | trigger-external; | 648 | trigger-external; |
| 650 | }; | 649 | }; |
| 651 | 650 | ||
| 652 | trigger@2 { | 651 | trigger@2 { |
| 652 | reg = <2>; | ||
| 653 | trigger-name = "external-any"; | 653 | trigger-name = "external-any"; |
| 654 | trigger-value = <0x3>; | 654 | trigger-value = <0x3>; |
| 655 | trigger-external; | 655 | trigger-external; |
| 656 | }; | 656 | }; |
| 657 | 657 | ||
| 658 | trigger@3 { | 658 | trigger@3 { |
| 659 | reg = <3>; | ||
| 659 | trigger-name = "continuous"; | 660 | trigger-name = "continuous"; |
| 660 | trigger-value = <0x6>; | 661 | trigger-value = <0x6>; |
| 661 | }; | 662 | }; |
| @@ -790,6 +791,7 @@ | |||
| 790 | atmel,pmecc-lookup-table-offset = <0x0 0x8000>; | 791 | atmel,pmecc-lookup-table-offset = <0x0 0x8000>; |
| 791 | atmel,nand-addr-offset = <21>; | 792 | atmel,nand-addr-offset = <21>; |
| 792 | atmel,nand-cmd-offset = <22>; | 793 | atmel,nand-cmd-offset = <22>; |
| 794 | atmel,nand-has-dma; | ||
| 793 | pinctrl-names = "default"; | 795 | pinctrl-names = "default"; |
| 794 | pinctrl-0 = <&pinctrl_nand>; | 796 | pinctrl-0 = <&pinctrl_nand>; |
| 795 | gpios = <&pioD 5 GPIO_ACTIVE_HIGH | 797 | gpios = <&pioD 5 GPIO_ACTIVE_HIGH |
diff --git a/arch/arm/boot/dts/bcm11351-brt.dts b/arch/arm/boot/dts/bcm11351-brt.dts deleted file mode 100644 index 396b70459cdc..000000000000 --- a/arch/arm/boot/dts/bcm11351-brt.dts +++ /dev/null | |||
| @@ -1,54 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2012 Broadcom Corporation | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License as | ||
| 6 | * published by the Free Software Foundation version 2. | ||
| 7 | * | ||
| 8 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
| 9 | * kind, whether express or implied; without even the implied warranty | ||
| 10 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | */ | ||
| 13 | |||
| 14 | /dts-v1/; | ||
| 15 | |||
| 16 | #include "bcm11351.dtsi" | ||
| 17 | |||
| 18 | / { | ||
| 19 | model = "BCM11351 BRT board"; | ||
| 20 | compatible = "brcm,bcm11351-brt", "brcm,bcm11351"; | ||
| 21 | |||
| 22 | memory { | ||
| 23 | reg = <0x80000000 0x40000000>; /* 1 GB */ | ||
| 24 | }; | ||
| 25 | |||
| 26 | uart@3e000000 { | ||
| 27 | status = "okay"; | ||
| 28 | }; | ||
| 29 | |||
| 30 | sdio1: sdio@3f180000 { | ||
| 31 | max-frequency = <48000000>; | ||
| 32 | status = "okay"; | ||
| 33 | }; | ||
| 34 | |||
| 35 | sdio2: sdio@3f190000 { | ||
| 36 | non-removable; | ||
| 37 | max-frequency = <48000000>; | ||
| 38 | status = "okay"; | ||
| 39 | }; | ||
| 40 | |||
| 41 | sdio4: sdio@3f1b0000 { | ||
| 42 | max-frequency = <48000000>; | ||
| 43 | cd-gpios = <&gpio 14 0>; | ||
| 44 | status = "okay"; | ||
| 45 | }; | ||
| 46 | |||
| 47 | usbotg: usb@3f120000 { | ||
| 48 | status = "okay"; | ||
| 49 | }; | ||
| 50 | |||
| 51 | usbphy: usb-phy@3f130000 { | ||
| 52 | status = "okay"; | ||
| 53 | }; | ||
| 54 | }; | ||
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi index e491b82f8d67..94b36f631ed8 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/bcm11351.dtsi | |||
| @@ -14,6 +14,8 @@ | |||
| 14 | #include <dt-bindings/interrupt-controller/arm-gic.h> | 14 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 15 | #include <dt-bindings/interrupt-controller/irq.h> | 15 | #include <dt-bindings/interrupt-controller/irq.h> |
| 16 | 16 | ||
| 17 | #include "dt-bindings/clock/bcm281xx.h" | ||
| 18 | |||
| 17 | #include "skeleton.dtsi" | 19 | #include "skeleton.dtsi" |
| 18 | 20 | ||
| 19 | / { | 21 | / { |
| @@ -43,7 +45,7 @@ | |||
| 43 | compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; | 45 | compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; |
| 44 | status = "disabled"; | 46 | status = "disabled"; |
| 45 | reg = <0x3e000000 0x1000>; | 47 | reg = <0x3e000000 0x1000>; |
| 46 | clocks = <&uartb_clk>; | 48 | clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB>; |
| 47 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; | 49 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
| 48 | reg-shift = <2>; | 50 | reg-shift = <2>; |
| 49 | reg-io-width = <4>; | 51 | reg-io-width = <4>; |
| @@ -53,7 +55,7 @@ | |||
| 53 | compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; | 55 | compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; |
| 54 | status = "disabled"; | 56 | status = "disabled"; |
| 55 | reg = <0x3e001000 0x1000>; | 57 | reg = <0x3e001000 0x1000>; |
| 56 | clocks = <&uartb2_clk>; | 58 | clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB2>; |
| 57 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; | 59 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
| 58 | reg-shift = <2>; | 60 | reg-shift = <2>; |
| 59 | reg-io-width = <4>; | 61 | reg-io-width = <4>; |
| @@ -63,7 +65,7 @@ | |||
| 63 | compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; | 65 | compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; |
| 64 | status = "disabled"; | 66 | status = "disabled"; |
| 65 | reg = <0x3e002000 0x1000>; | 67 | reg = <0x3e002000 0x1000>; |
| 66 | clocks = <&uartb3_clk>; | 68 | clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>; |
| 67 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; | 69 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
| 68 | reg-shift = <2>; | 70 | reg-shift = <2>; |
| 69 | reg-io-width = <4>; | 71 | reg-io-width = <4>; |
| @@ -73,7 +75,7 @@ | |||
| 73 | compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; | 75 | compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; |
| 74 | status = "disabled"; | 76 | status = "disabled"; |
| 75 | reg = <0x3e003000 0x1000>; | 77 | reg = <0x3e003000 0x1000>; |
| 76 | clocks = <&uartb4_clk>; | 78 | clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB4>; |
| 77 | interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; | 79 | interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; |
| 78 | reg-shift = <2>; | 80 | reg-shift = <2>; |
| 79 | reg-io-width = <4>; | 81 | reg-io-width = <4>; |
| @@ -95,7 +97,7 @@ | |||
| 95 | compatible = "brcm,kona-timer"; | 97 | compatible = "brcm,kona-timer"; |
| 96 | reg = <0x35006000 0x1000>; | 98 | reg = <0x35006000 0x1000>; |
| 97 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | 99 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| 98 | clocks = <&hub_timer_clk>; | 100 | clocks = <&aon_ccu BCM281XX_AON_CCU_HUB_TIMER>; |
| 99 | }; | 101 | }; |
| 100 | 102 | ||
| 101 | gpio: gpio@35003000 { | 103 | gpio: gpio@35003000 { |
| @@ -118,7 +120,7 @@ | |||
| 118 | compatible = "brcm,kona-sdhci"; | 120 | compatible = "brcm,kona-sdhci"; |
| 119 | reg = <0x3f180000 0x10000>; | 121 | reg = <0x3f180000 0x10000>; |
| 120 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | 122 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
| 121 | clocks = <&sdio1_clk>; | 123 | clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO1>; |
| 122 | status = "disabled"; | 124 | status = "disabled"; |
| 123 | }; | 125 | }; |
| 124 | 126 | ||
| @@ -126,7 +128,7 @@ | |||
| 126 | compatible = "brcm,kona-sdhci"; | 128 | compatible = "brcm,kona-sdhci"; |
| 127 | reg = <0x3f190000 0x10000>; | 129 | reg = <0x3f190000 0x10000>; |
| 128 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; | 130 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
| 129 | clocks = <&sdio2_clk>; | 131 | clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO2>; |
| 130 | status = "disabled"; | 132 | status = "disabled"; |
| 131 | }; | 133 | }; |
| 132 | 134 | ||
| @@ -134,7 +136,7 @@ | |||
| 134 | compatible = "brcm,kona-sdhci"; | 136 | compatible = "brcm,kona-sdhci"; |
| 135 | reg = <0x3f1a0000 0x10000>; | 137 | reg = <0x3f1a0000 0x10000>; |
| 136 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; | 138 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
| 137 | clocks = <&sdio3_clk>; | 139 | clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO3>; |
| 138 | status = "disabled"; | 140 | status = "disabled"; |
| 139 | }; | 141 | }; |
| 140 | 142 | ||
| @@ -142,7 +144,7 @@ | |||
| 142 | compatible = "brcm,kona-sdhci"; | 144 | compatible = "brcm,kona-sdhci"; |
| 143 | reg = <0x3f1b0000 0x10000>; | 145 | reg = <0x3f1b0000 0x10000>; |
| 144 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; | 146 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| 145 | clocks = <&sdio4_clk>; | 147 | clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO4>; |
| 146 | status = "disabled"; | 148 | status = "disabled"; |
| 147 | }; | 149 | }; |
| 148 | 150 | ||
| @@ -157,7 +159,7 @@ | |||
| 157 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; | 159 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
| 158 | #address-cells = <1>; | 160 | #address-cells = <1>; |
| 159 | #size-cells = <0>; | 161 | #size-cells = <0>; |
| 160 | clocks = <&bsc1_clk>; | 162 | clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC1>; |
| 161 | status = "disabled"; | 163 | status = "disabled"; |
| 162 | }; | 164 | }; |
| 163 | 165 | ||
| @@ -167,7 +169,7 @@ | |||
| 167 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; | 169 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; |
| 168 | #address-cells = <1>; | 170 | #address-cells = <1>; |
| 169 | #size-cells = <0>; | 171 | #size-cells = <0>; |
| 170 | clocks = <&bsc2_clk>; | 172 | clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC2>; |
| 171 | status = "disabled"; | 173 | status = "disabled"; |
| 172 | }; | 174 | }; |
| 173 | 175 | ||
| @@ -177,7 +179,7 @@ | |||
| 177 | interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; | 179 | interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; |
| 178 | #address-cells = <1>; | 180 | #address-cells = <1>; |
| 179 | #size-cells = <0>; | 181 | #size-cells = <0>; |
| 180 | clocks = <&bsc3_clk>; | 182 | clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC3>; |
| 181 | status = "disabled"; | 183 | status = "disabled"; |
| 182 | }; | 184 | }; |
| 183 | 185 | ||
| @@ -187,105 +189,191 @@ | |||
| 187 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | 189 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| 188 | #address-cells = <1>; | 190 | #address-cells = <1>; |
| 189 | #size-cells = <0>; | 191 | #size-cells = <0>; |
| 190 | clocks = <&pmu_bsc_clk>; | 192 | clocks = <&aon_ccu BCM281XX_AON_CCU_PMU_BSC>; |
| 191 | status = "disabled"; | 193 | status = "disabled"; |
| 192 | }; | 194 | }; |
| 193 | 195 | ||
| 194 | clocks { | 196 | clocks { |
| 195 | bsc1_clk: bsc1 { | 197 | #address-cells = <1>; |
| 196 | compatible = "fixed-clock"; | 198 | #size-cells = <1>; |
| 197 | clock-frequency = <13000000>; | 199 | ranges; |
| 200 | |||
| 201 | root_ccu: root_ccu { | ||
| 202 | compatible = "brcm,bcm11351-root-ccu"; | ||
| 203 | reg = <0x35001000 0x0f00>; | ||
| 204 | #clock-cells = <1>; | ||
| 205 | clock-output-names = "frac_1m"; | ||
| 206 | }; | ||
| 207 | |||
| 208 | hub_ccu: hub_ccu { | ||
| 209 | compatible = "brcm,bcm11351-hub-ccu"; | ||
| 210 | reg = <0x34000000 0x0f00>; | ||
| 211 | #clock-cells = <1>; | ||
| 212 | clock-output-names = "tmon_1m"; | ||
| 213 | }; | ||
| 214 | |||
| 215 | aon_ccu: aon_ccu { | ||
| 216 | compatible = "brcm,bcm11351-aon-ccu"; | ||
| 217 | reg = <0x35002000 0x0f00>; | ||
| 218 | #clock-cells = <1>; | ||
| 219 | clock-output-names = "hub_timer", | ||
| 220 | "pmu_bsc", | ||
| 221 | "pmu_bsc_var"; | ||
| 222 | }; | ||
| 223 | |||
| 224 | master_ccu: master_ccu { | ||
| 225 | compatible = "brcm,bcm11351-master-ccu"; | ||
| 226 | reg = <0x3f001000 0x0f00>; | ||
| 227 | #clock-cells = <1>; | ||
| 228 | clock-output-names = "sdio1", | ||
| 229 | "sdio2", | ||
| 230 | "sdio3", | ||
| 231 | "sdio4", | ||
| 232 | "usb_ic", | ||
| 233 | "hsic2_48m", | ||
| 234 | "hsic2_12m"; | ||
| 235 | }; | ||
| 236 | |||
| 237 | slave_ccu: slave_ccu { | ||
| 238 | compatible = "brcm,bcm11351-slave-ccu"; | ||
| 239 | reg = <0x3e011000 0x0f00>; | ||
| 240 | #clock-cells = <1>; | ||
| 241 | clock-output-names = "uartb", | ||
| 242 | "uartb2", | ||
| 243 | "uartb3", | ||
| 244 | "uartb4", | ||
| 245 | "ssp0", | ||
| 246 | "ssp2", | ||
| 247 | "bsc1", | ||
| 248 | "bsc2", | ||
| 249 | "bsc3", | ||
| 250 | "pwm"; | ||
| 251 | }; | ||
| 252 | |||
| 253 | ref_1m_clk: ref_1m { | ||
| 198 | #clock-cells = <0>; | 254 | #clock-cells = <0>; |
| 255 | compatible = "fixed-clock"; | ||
| 256 | clock-frequency = <1000000>; | ||
| 199 | }; | 257 | }; |
| 200 | 258 | ||
| 201 | bsc2_clk: bsc2 { | 259 | ref_32k_clk: ref_32k { |
| 260 | #clock-cells = <0>; | ||
| 202 | compatible = "fixed-clock"; | 261 | compatible = "fixed-clock"; |
| 203 | clock-frequency = <13000000>; | 262 | clock-frequency = <32768>; |
| 263 | }; | ||
| 264 | |||
| 265 | bbl_32k_clk: bbl_32k { | ||
| 204 | #clock-cells = <0>; | 266 | #clock-cells = <0>; |
| 267 | compatible = "fixed-clock"; | ||
| 268 | clock-frequency = <32768>; | ||
| 205 | }; | 269 | }; |
| 206 | 270 | ||
| 207 | bsc3_clk: bsc3 { | 271 | ref_13m_clk: ref_13m { |
| 272 | #clock-cells = <0>; | ||
| 208 | compatible = "fixed-clock"; | 273 | compatible = "fixed-clock"; |
| 209 | clock-frequency = <13000000>; | 274 | clock-frequency = <13000000>; |
| 210 | #clock-cells = <0>; | ||
| 211 | }; | 275 | }; |
| 212 | 276 | ||
| 213 | pmu_bsc_clk: pmu_bsc { | 277 | var_13m_clk: var_13m { |
| 278 | #clock-cells = <0>; | ||
| 214 | compatible = "fixed-clock"; | 279 | compatible = "fixed-clock"; |
| 215 | clock-frequency = <13000000>; | 280 | clock-frequency = <13000000>; |
| 216 | #clock-cells = <0>; | ||
| 217 | }; | 281 | }; |
| 218 | 282 | ||
| 219 | hub_timer_clk: hub_timer { | 283 | dft_19_5m_clk: dft_19_5m { |
| 220 | compatible = "fixed-clock"; | ||
| 221 | clock-frequency = <32768>; | ||
| 222 | #clock-cells = <0>; | 284 | #clock-cells = <0>; |
| 285 | compatible = "fixed-clock"; | ||
| 286 | clock-frequency = <19500000>; | ||
| 223 | }; | 287 | }; |
| 224 | 288 | ||
| 225 | pwm_clk: pwm { | 289 | ref_crystal_clk: ref_crystal { |
| 290 | #clock-cells = <0>; | ||
| 226 | compatible = "fixed-clock"; | 291 | compatible = "fixed-clock"; |
| 227 | clock-frequency = <26000000>; | 292 | clock-frequency = <26000000>; |
| 228 | #clock-cells = <0>; | ||
| 229 | }; | 293 | }; |
| 230 | 294 | ||
| 231 | sdio1_clk: sdio1 { | 295 | ref_cx40_clk: ref_cx40 { |
| 232 | compatible = "fixed-clock"; | ||
| 233 | clock-frequency = <48000000>; | ||
| 234 | #clock-cells = <0>; | 296 | #clock-cells = <0>; |
| 297 | compatible = "fixed-clock"; | ||
| 298 | clock-frequency = <40000000>; | ||
| 235 | }; | 299 | }; |
| 236 | 300 | ||
| 237 | sdio2_clk: sdio2 { | 301 | ref_52m_clk: ref_52m { |
| 238 | compatible = "fixed-clock"; | ||
| 239 | clock-frequency = <48000000>; | ||
| 240 | #clock-cells = <0>; | 302 | #clock-cells = <0>; |
| 303 | compatible = "fixed-clock"; | ||
| 304 | clock-frequency = <52000000>; | ||
| 241 | }; | 305 | }; |
| 242 | 306 | ||
| 243 | sdio3_clk: sdio3 { | 307 | var_52m_clk: var_52m { |
| 244 | compatible = "fixed-clock"; | ||
| 245 | clock-frequency = <48000000>; | ||
| 246 | #clock-cells = <0>; | 308 | #clock-cells = <0>; |
| 309 | compatible = "fixed-clock"; | ||
| 310 | clock-frequency = <52000000>; | ||
| 247 | }; | 311 | }; |
| 248 | 312 | ||
| 249 | sdio4_clk: sdio4 { | 313 | usb_otg_ahb_clk: usb_otg_ahb { |
| 250 | compatible = "fixed-clock"; | 314 | compatible = "fixed-clock"; |
| 251 | clock-frequency = <48000000>; | 315 | clock-frequency = <52000000>; |
| 252 | #clock-cells = <0>; | 316 | #clock-cells = <0>; |
| 253 | }; | 317 | }; |
| 254 | 318 | ||
| 255 | tmon_1m_clk: tmon_1m { | 319 | ref_96m_clk: ref_96m { |
| 256 | compatible = "fixed-clock"; | ||
| 257 | clock-frequency = <1000000>; | ||
| 258 | #clock-cells = <0>; | 320 | #clock-cells = <0>; |
| 321 | compatible = "fixed-clock"; | ||
| 322 | clock-frequency = <96000000>; | ||
| 259 | }; | 323 | }; |
| 260 | 324 | ||
| 261 | uartb_clk: uartb { | 325 | var_96m_clk: var_96m { |
| 262 | compatible = "fixed-clock"; | ||
| 263 | clock-frequency = <13000000>; | ||
| 264 | #clock-cells = <0>; | 326 | #clock-cells = <0>; |
| 327 | compatible = "fixed-clock"; | ||
| 328 | clock-frequency = <96000000>; | ||
| 265 | }; | 329 | }; |
| 266 | 330 | ||
| 267 | uartb2_clk: uartb2 { | 331 | ref_104m_clk: ref_104m { |
| 332 | #clock-cells = <0>; | ||
| 268 | compatible = "fixed-clock"; | 333 | compatible = "fixed-clock"; |
| 269 | clock-frequency = <13000000>; | 334 | clock-frequency = <104000000>; |
| 335 | }; | ||
| 336 | |||
| 337 | var_104m_clk: var_104m { | ||
| 270 | #clock-cells = <0>; | 338 | #clock-cells = <0>; |
| 339 | compatible = "fixed-clock"; | ||
| 340 | clock-frequency = <104000000>; | ||
| 271 | }; | 341 | }; |
| 272 | 342 | ||
| 273 | uartb3_clk: uartb3 { | 343 | ref_156m_clk: ref_156m { |
| 344 | #clock-cells = <0>; | ||
| 274 | compatible = "fixed-clock"; | 345 | compatible = "fixed-clock"; |
| 275 | clock-frequency = <13000000>; | 346 | clock-frequency = <156000000>; |
| 347 | }; | ||
| 348 | |||
| 349 | var_156m_clk: var_156m { | ||
| 276 | #clock-cells = <0>; | 350 | #clock-cells = <0>; |
| 351 | compatible = "fixed-clock"; | ||
| 352 | clock-frequency = <156000000>; | ||
| 277 | }; | 353 | }; |
| 278 | 354 | ||
| 279 | uartb4_clk: uartb4 { | 355 | ref_208m_clk: ref_208m { |
| 356 | #clock-cells = <0>; | ||
| 280 | compatible = "fixed-clock"; | 357 | compatible = "fixed-clock"; |
| 281 | clock-frequency = <13000000>; | 358 | clock-frequency = <208000000>; |
| 359 | }; | ||
| 360 | |||
| 361 | var_208m_clk: var_208m { | ||
| 282 | #clock-cells = <0>; | 362 | #clock-cells = <0>; |
| 363 | compatible = "fixed-clock"; | ||
| 364 | clock-frequency = <208000000>; | ||
| 283 | }; | 365 | }; |
| 284 | 366 | ||
| 285 | usb_otg_ahb_clk: usb_otg_ahb { | 367 | ref_312m_clk: ref_312m { |
| 368 | #clock-cells = <0>; | ||
| 286 | compatible = "fixed-clock"; | 369 | compatible = "fixed-clock"; |
| 287 | clock-frequency = <52000000>; | 370 | clock-frequency = <312000000>; |
| 371 | }; | ||
| 372 | |||
| 373 | var_312m_clk: var_312m { | ||
| 288 | #clock-cells = <0>; | 374 | #clock-cells = <0>; |
| 375 | compatible = "fixed-clock"; | ||
| 376 | clock-frequency = <312000000>; | ||
| 289 | }; | 377 | }; |
| 290 | }; | 378 | }; |
| 291 | 379 | ||
diff --git a/arch/arm/boot/dts/bcm28155-ap.dts b/arch/arm/boot/dts/bcm28155-ap.dts index 5ff2382a49e4..3604554e752c 100644 --- a/arch/arm/boot/dts/bcm28155-ap.dts +++ b/arch/arm/boot/dts/bcm28155-ap.dts | |||
| @@ -49,11 +49,6 @@ | |||
| 49 | clock-frequency = <400000>; | 49 | clock-frequency = <400000>; |
| 50 | }; | 50 | }; |
| 51 | 51 | ||
| 52 | sdio1: sdio@3f180000 { | ||
| 53 | max-frequency = <48000000>; | ||
| 54 | status = "okay"; | ||
| 55 | }; | ||
| 56 | |||
| 57 | sdio2: sdio@3f190000 { | 52 | sdio2: sdio@3f190000 { |
| 58 | non-removable; | 53 | non-removable; |
| 59 | max-frequency = <48000000>; | 54 | max-frequency = <48000000>; |
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi index b021c96d3ba1..b8473c43e888 100644 --- a/arch/arm/boot/dts/bcm2835.dtsi +++ b/arch/arm/boot/dts/bcm2835.dtsi | |||
| @@ -15,39 +15,52 @@ | |||
| 15 | #size-cells = <1>; | 15 | #size-cells = <1>; |
| 16 | ranges = <0x7e000000 0x20000000 0x02000000>; | 16 | ranges = <0x7e000000 0x20000000 0x02000000>; |
| 17 | 17 | ||
| 18 | timer { | 18 | timer@7e003000 { |
| 19 | compatible = "brcm,bcm2835-system-timer"; | 19 | compatible = "brcm,bcm2835-system-timer"; |
| 20 | reg = <0x7e003000 0x1000>; | 20 | reg = <0x7e003000 0x1000>; |
| 21 | interrupts = <1 0>, <1 1>, <1 2>, <1 3>; | 21 | interrupts = <1 0>, <1 1>, <1 2>, <1 3>; |
| 22 | clock-frequency = <1000000>; | 22 | clock-frequency = <1000000>; |
| 23 | }; | 23 | }; |
| 24 | 24 | ||
| 25 | intc: interrupt-controller { | 25 | dma: dma@7e007000 { |
| 26 | compatible = "brcm,bcm2835-dma"; | ||
| 27 | reg = <0x7e007000 0xf00>; | ||
| 28 | interrupts = <1 16>, | ||
| 29 | <1 17>, | ||
| 30 | <1 18>, | ||
| 31 | <1 19>, | ||
| 32 | <1 20>, | ||
| 33 | <1 21>, | ||
| 34 | <1 22>, | ||
| 35 | <1 23>, | ||
| 36 | <1 24>, | ||
| 37 | <1 25>, | ||
| 38 | <1 26>, | ||
| 39 | <1 27>, | ||
| 40 | <1 28>; | ||
| 41 | |||
| 42 | #dma-cells = <1>; | ||
| 43 | brcm,dma-channel-mask = <0x7f35>; | ||
| 44 | }; | ||
| 45 | |||
| 46 | intc: interrupt-controller@7e00b200 { | ||
| 26 | compatible = "brcm,bcm2835-armctrl-ic"; | 47 | compatible = "brcm,bcm2835-armctrl-ic"; |
| 27 | reg = <0x7e00b200 0x200>; | 48 | reg = <0x7e00b200 0x200>; |
| 28 | interrupt-controller; | 49 | interrupt-controller; |
| 29 | #interrupt-cells = <2>; | 50 | #interrupt-cells = <2>; |
| 30 | }; | 51 | }; |
| 31 | 52 | ||
| 32 | watchdog { | 53 | watchdog@7e100000 { |
| 33 | compatible = "brcm,bcm2835-pm-wdt"; | 54 | compatible = "brcm,bcm2835-pm-wdt"; |
| 34 | reg = <0x7e100000 0x28>; | 55 | reg = <0x7e100000 0x28>; |
| 35 | }; | 56 | }; |
| 36 | 57 | ||
| 37 | rng { | 58 | rng@7e104000 { |
| 38 | compatible = "brcm,bcm2835-rng"; | 59 | compatible = "brcm,bcm2835-rng"; |
| 39 | reg = <0x7e104000 0x10>; | 60 | reg = <0x7e104000 0x10>; |
| 40 | }; | 61 | }; |
| 41 | 62 | ||
| 42 | uart@20201000 { | 63 | gpio: gpio@7e200000 { |
| 43 | compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell"; | ||
| 44 | reg = <0x7e201000 0x1000>; | ||
| 45 | interrupts = <2 25>; | ||
| 46 | clock-frequency = <3000000>; | ||
| 47 | arm,primecell-periphid = <0x00241011>; | ||
| 48 | }; | ||
| 49 | |||
| 50 | gpio: gpio { | ||
| 51 | compatible = "brcm,bcm2835-gpio"; | 64 | compatible = "brcm,bcm2835-gpio"; |
| 52 | reg = <0x7e200000 0xb4>; | 65 | reg = <0x7e200000 0xb4>; |
| 53 | /* | 66 | /* |
| @@ -70,7 +83,25 @@ | |||
| 70 | #interrupt-cells = <2>; | 83 | #interrupt-cells = <2>; |
| 71 | }; | 84 | }; |
| 72 | 85 | ||
| 73 | spi: spi@20204000 { | 86 | uart@7e201000 { |
| 87 | compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell"; | ||
| 88 | reg = <0x7e201000 0x1000>; | ||
| 89 | interrupts = <2 25>; | ||
| 90 | clock-frequency = <3000000>; | ||
| 91 | arm,primecell-periphid = <0x00241011>; | ||
| 92 | }; | ||
| 93 | |||
| 94 | i2s: i2s@7e203000 { | ||
| 95 | compatible = "brcm,bcm2835-i2s"; | ||
| 96 | reg = <0x7e203000 0x20>, | ||
| 97 | <0x7e101098 0x02>; | ||
| 98 | |||
| 99 | dmas = <&dma 2>, | ||
| 100 | <&dma 3>; | ||
| 101 | dma-names = "tx", "rx"; | ||
| 102 | }; | ||
| 103 | |||
| 104 | spi: spi@7e204000 { | ||
| 74 | compatible = "brcm,bcm2835-spi"; | 105 | compatible = "brcm,bcm2835-spi"; |
| 75 | reg = <0x7e204000 0x1000>; | 106 | reg = <0x7e204000 0x1000>; |
| 76 | interrupts = <2 22>; | 107 | interrupts = <2 22>; |
| @@ -90,7 +121,15 @@ | |||
| 90 | status = "disabled"; | 121 | status = "disabled"; |
| 91 | }; | 122 | }; |
| 92 | 123 | ||
| 93 | i2c1: i2c@20804000 { | 124 | sdhci: sdhci@7e300000 { |
| 125 | compatible = "brcm,bcm2835-sdhci"; | ||
| 126 | reg = <0x7e300000 0x100>; | ||
| 127 | interrupts = <2 30>; | ||
| 128 | clocks = <&clk_mmc>; | ||
| 129 | status = "disabled"; | ||
| 130 | }; | ||
| 131 | |||
| 132 | i2c1: i2c@7e804000 { | ||
| 94 | compatible = "brcm,bcm2835-i2c"; | 133 | compatible = "brcm,bcm2835-i2c"; |
| 95 | reg = <0x7e804000 0x1000>; | 134 | reg = <0x7e804000 0x1000>; |
| 96 | interrupts = <2 21>; | 135 | interrupts = <2 21>; |
| @@ -100,19 +139,15 @@ | |||
| 100 | status = "disabled"; | 139 | status = "disabled"; |
| 101 | }; | 140 | }; |
| 102 | 141 | ||
| 103 | sdhci: sdhci { | 142 | usb@7e980000 { |
| 104 | compatible = "brcm,bcm2835-sdhci"; | ||
| 105 | reg = <0x7e300000 0x100>; | ||
| 106 | interrupts = <2 30>; | ||
| 107 | clocks = <&clk_mmc>; | ||
| 108 | status = "disabled"; | ||
| 109 | }; | ||
| 110 | |||
| 111 | usb { | ||
| 112 | compatible = "brcm,bcm2835-usb"; | 143 | compatible = "brcm,bcm2835-usb"; |
| 113 | reg = <0x7e980000 0x10000>; | 144 | reg = <0x7e980000 0x10000>; |
| 114 | interrupts = <1 9>; | 145 | interrupts = <1 9>; |
| 115 | }; | 146 | }; |
| 147 | |||
| 148 | arm-pmu { | ||
| 149 | compatible = "arm,arm1176-pmu"; | ||
| 150 | }; | ||
| 116 | }; | 151 | }; |
| 117 | 152 | ||
| 118 | clocks { | 153 | clocks { |
| @@ -120,24 +155,27 @@ | |||
| 120 | #address-cells = <1>; | 155 | #address-cells = <1>; |
| 121 | #size-cells = <0>; | 156 | #size-cells = <0>; |
| 122 | 157 | ||
| 123 | clk_mmc: mmc { | 158 | clk_mmc: clock@0 { |
| 124 | compatible = "fixed-clock"; | 159 | compatible = "fixed-clock"; |
| 125 | reg = <0>; | 160 | reg = <0>; |
| 126 | #clock-cells = <0>; | 161 | #clock-cells = <0>; |
| 162 | clock-output-names = "mmc"; | ||
| 127 | clock-frequency = <100000000>; | 163 | clock-frequency = <100000000>; |
| 128 | }; | 164 | }; |
| 129 | 165 | ||
| 130 | clk_i2c: i2c { | 166 | clk_i2c: clock@1 { |
| 131 | compatible = "fixed-clock"; | 167 | compatible = "fixed-clock"; |
| 132 | reg = <1>; | 168 | reg = <1>; |
| 133 | #clock-cells = <0>; | 169 | #clock-cells = <0>; |
| 170 | clock-output-names = "i2c"; | ||
| 134 | clock-frequency = <250000000>; | 171 | clock-frequency = <250000000>; |
| 135 | }; | 172 | }; |
| 136 | 173 | ||
| 137 | clk_spi: spi { | 174 | clk_spi: clock@2 { |
| 138 | compatible = "fixed-clock"; | 175 | compatible = "fixed-clock"; |
| 139 | reg = <2>; | 176 | reg = <2>; |
| 140 | #clock-cells = <0>; | 177 | #clock-cells = <0>; |
| 178 | clock-output-names = "spi"; | ||
| 141 | clock-frequency = <250000000>; | 179 | clock-frequency = <250000000>; |
| 142 | }; | 180 | }; |
| 143 | }; | 181 | }; |
diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts new file mode 100644 index 000000000000..3b5259de5a38 --- /dev/null +++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts | |||
| @@ -0,0 +1,35 @@ | |||
| 1 | /* | ||
| 2 | * Broadcom BCM470X / BCM5301X arm platform code. | ||
| 3 | * DTS for Netgear R6250 V1 | ||
| 4 | * | ||
| 5 | * Copyright 2013 Hauke Mehrtens <hauke@hauke-m.de> | ||
| 6 | * | ||
| 7 | * Licensed under the GNU/GPL. See COPYING for details. | ||
| 8 | */ | ||
| 9 | |||
| 10 | /dts-v1/; | ||
| 11 | |||
| 12 | #include "bcm4708.dtsi" | ||
| 13 | |||
| 14 | / { | ||
| 15 | compatible = "netgear,r6250v1", "brcm,bcm4708"; | ||
| 16 | model = "Netgear R6250 V1 (BCM4708)"; | ||
| 17 | |||
| 18 | chosen { | ||
| 19 | bootargs = "console=ttyS0,115200"; | ||
| 20 | }; | ||
| 21 | |||
| 22 | memory { | ||
| 23 | reg = <0x00000000 0x08000000>; | ||
| 24 | }; | ||
| 25 | |||
| 26 | chipcommonA { | ||
| 27 | uart0: serial@0300 { | ||
| 28 | status = "okay"; | ||
| 29 | }; | ||
| 30 | |||
| 31 | uart1: serial@0400 { | ||
| 32 | status = "okay"; | ||
| 33 | }; | ||
| 34 | }; | ||
| 35 | }; | ||
diff --git a/arch/arm/boot/dts/bcm4708.dtsi b/arch/arm/boot/dts/bcm4708.dtsi new file mode 100644 index 000000000000..31141e83fedd --- /dev/null +++ b/arch/arm/boot/dts/bcm4708.dtsi | |||
| @@ -0,0 +1,34 @@ | |||
| 1 | /* | ||
| 2 | * Broadcom BCM470X / BCM5301X ARM platform code. | ||
| 3 | * DTS for BCM4708 SoC. | ||
| 4 | * | ||
| 5 | * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de> | ||
| 6 | * | ||
| 7 | * Licensed under the GNU/GPL. See COPYING for details. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #include "bcm5301x.dtsi" | ||
| 11 | |||
| 12 | / { | ||
| 13 | compatible = "brcm,bcm4708"; | ||
| 14 | |||
| 15 | cpus { | ||
| 16 | #address-cells = <1>; | ||
| 17 | #size-cells = <0>; | ||
| 18 | |||
| 19 | cpu@0 { | ||
| 20 | device_type = "cpu"; | ||
| 21 | compatible = "arm,cortex-a9"; | ||
| 22 | next-level-cache = <&L2>; | ||
| 23 | reg = <0x0>; | ||
| 24 | }; | ||
| 25 | |||
| 26 | cpu@1 { | ||
| 27 | device_type = "cpu"; | ||
| 28 | compatible = "arm,cortex-a9"; | ||
| 29 | next-level-cache = <&L2>; | ||
| 30 | reg = <0x1>; | ||
| 31 | }; | ||
| 32 | }; | ||
| 33 | |||
| 34 | }; | ||
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi new file mode 100644 index 000000000000..53c624f766b4 --- /dev/null +++ b/arch/arm/boot/dts/bcm5301x.dtsi | |||
| @@ -0,0 +1,95 @@ | |||
| 1 | /* | ||
| 2 | * Broadcom BCM470X / BCM5301X ARM platform code. | ||
| 3 | * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015, | ||
| 4 | * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs | ||
| 5 | * | ||
| 6 | * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de> | ||
| 7 | * | ||
| 8 | * Licensed under the GNU/GPL. See COPYING for details. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 12 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 13 | #include "skeleton.dtsi" | ||
| 14 | |||
| 15 | / { | ||
| 16 | interrupt-parent = <&gic>; | ||
| 17 | |||
| 18 | chipcommonA { | ||
| 19 | compatible = "simple-bus"; | ||
| 20 | ranges = <0x00000000 0x18000000 0x00001000>; | ||
| 21 | #address-cells = <1>; | ||
| 22 | #size-cells = <1>; | ||
| 23 | |||
| 24 | uart0: serial@0300 { | ||
| 25 | compatible = "ns16550"; | ||
| 26 | reg = <0x0300 0x100>; | ||
| 27 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; | ||
| 28 | clock-frequency = <100000000>; | ||
| 29 | status = "disabled"; | ||
| 30 | }; | ||
| 31 | |||
| 32 | uart1: serial@0400 { | ||
| 33 | compatible = "ns16550"; | ||
| 34 | reg = <0x0400 0x100>; | ||
| 35 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; | ||
| 36 | clock-frequency = <100000000>; | ||
| 37 | status = "disabled"; | ||
| 38 | }; | ||
| 39 | }; | ||
| 40 | |||
| 41 | mpcore { | ||
| 42 | compatible = "simple-bus"; | ||
| 43 | ranges = <0x00000000 0x19020000 0x00003000>; | ||
| 44 | #address-cells = <1>; | ||
| 45 | #size-cells = <1>; | ||
| 46 | |||
| 47 | scu@0000 { | ||
| 48 | compatible = "arm,cortex-a9-scu"; | ||
| 49 | reg = <0x0000 0x100>; | ||
| 50 | }; | ||
| 51 | |||
| 52 | timer@0200 { | ||
| 53 | compatible = "arm,cortex-a9-global-timer"; | ||
| 54 | reg = <0x0200 0x100>; | ||
| 55 | interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; | ||
| 56 | clocks = <&clk_periph>; | ||
| 57 | }; | ||
| 58 | |||
| 59 | local-timer@0600 { | ||
| 60 | compatible = "arm,cortex-a9-twd-timer"; | ||
| 61 | reg = <0x0600 0x100>; | ||
| 62 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; | ||
| 63 | clocks = <&clk_periph>; | ||
| 64 | }; | ||
| 65 | |||
| 66 | gic: interrupt-controller@1000 { | ||
| 67 | compatible = "arm,cortex-a9-gic"; | ||
| 68 | #interrupt-cells = <3>; | ||
| 69 | #address-cells = <0>; | ||
| 70 | interrupt-controller; | ||
| 71 | reg = <0x1000 0x1000>, | ||
| 72 | <0x0100 0x100>; | ||
| 73 | }; | ||
| 74 | |||
| 75 | L2: cache-controller@2000 { | ||
| 76 | compatible = "arm,pl310-cache"; | ||
| 77 | reg = <0x2000 0x1000>; | ||
| 78 | cache-unified; | ||
| 79 | cache-level = <2>; | ||
| 80 | }; | ||
| 81 | }; | ||
| 82 | |||
| 83 | clocks { | ||
| 84 | #address-cells = <1>; | ||
| 85 | #size-cells = <0>; | ||
| 86 | |||
| 87 | /* As long as we do not have a real clock driver us this | ||
| 88 | * fixed clock */ | ||
| 89 | clk_periph: periph { | ||
| 90 | compatible = "fixed-clock"; | ||
| 91 | #clock-cells = <0>; | ||
| 92 | clock-frequency = <400000000>; | ||
| 93 | }; | ||
| 94 | }; | ||
| 95 | }; | ||
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 187fd46b7b5e..3b891dd20993 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi | |||
| @@ -186,6 +186,11 @@ | |||
| 186 | reg = <0x20000 0x80>, <0x800100 0x8>; | 186 | reg = <0x20000 0x80>, <0x800100 0x8>; |
| 187 | }; | 187 | }; |
| 188 | 188 | ||
| 189 | sysc: system-ctrl@20000 { | ||
| 190 | compatible = "marvell,orion-system-controller"; | ||
| 191 | reg = <0x20000 0x110>; | ||
| 192 | }; | ||
| 193 | |||
| 189 | bridge_intc: bridge-interrupt-ctrl@20110 { | 194 | bridge_intc: bridge-interrupt-ctrl@20110 { |
| 190 | compatible = "marvell,orion-bridge-intc"; | 195 | compatible = "marvell,orion-bridge-intc"; |
| 191 | interrupt-controller; | 196 | interrupt-controller; |
| @@ -210,6 +215,14 @@ | |||
| 210 | clocks = <&core_clk 0>; | 215 | clocks = <&core_clk 0>; |
| 211 | }; | 216 | }; |
| 212 | 217 | ||
| 218 | watchdog@20300 { | ||
| 219 | compatible = "marvell,orion-wdt"; | ||
| 220 | reg = <0x20300 0x28>, <0x20108 0x4>; | ||
| 221 | interrupt-parent = <&bridge_intc>; | ||
| 222 | interrupts = <3>; | ||
| 223 | clocks = <&core_clk 0>; | ||
| 224 | }; | ||
| 225 | |||
| 213 | crypto: crypto-engine@30000 { | 226 | crypto: crypto-engine@30000 { |
| 214 | compatible = "marvell,orion-crypto"; | 227 | compatible = "marvell,orion-crypto"; |
| 215 | reg = <0x30000 0x10000>, | 228 | reg = <0x30000 0x10000>, |
| @@ -381,7 +394,8 @@ | |||
| 381 | 394 | ||
| 382 | pinctrl: pin-ctrl@d0200 { | 395 | pinctrl: pin-ctrl@d0200 { |
| 383 | compatible = "marvell,dove-pinctrl"; | 396 | compatible = "marvell,dove-pinctrl"; |
| 384 | reg = <0xd0200 0x10>; | 397 | reg = <0xd0200 0x14>, |
| 398 | <0xd0440 0x04>; | ||
| 385 | clocks = <&gate_clk 22>; | 399 | clocks = <&gate_clk 22>; |
| 386 | 400 | ||
| 387 | pmx_gpio_0: pmx-gpio-0 { | 401 | pmx_gpio_0: pmx-gpio-0 { |
| @@ -603,6 +617,12 @@ | |||
| 603 | reg = <0xd8500 0x20>; | 617 | reg = <0xd8500 0x20>; |
| 604 | }; | 618 | }; |
| 605 | 619 | ||
| 620 | gconf: global-config@e802c { | ||
| 621 | compatible = "marvell,dove-global-config", | ||
| 622 | "syscon"; | ||
| 623 | reg = <0xe802c 0x14>; | ||
| 624 | }; | ||
| 625 | |||
| 606 | gpio2: gpio-ctrl@e8400 { | 626 | gpio2: gpio-ctrl@e8400 { |
| 607 | compatible = "marvell,orion-gpio"; | 627 | compatible = "marvell,orion-gpio"; |
| 608 | #gpio-cells = <2>; | 628 | #gpio-cells = <2>; |
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 1fd75aa4639d..9e3caf3d19fb 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi | |||
| @@ -47,6 +47,11 @@ | |||
| 47 | 1000000 1060000 | 47 | 1000000 1060000 |
| 48 | 1176000 1160000 | 48 | 1176000 1160000 |
| 49 | >; | 49 | >; |
| 50 | |||
| 51 | clocks = <&dpll_mpu_ck>; | ||
| 52 | clock-names = "cpu"; | ||
| 53 | |||
| 54 | clock-latency = <300000>; /* From omap-cpufreq driver */ | ||
| 50 | }; | 55 | }; |
| 51 | cpu@1 { | 56 | cpu@1 { |
| 52 | device_type = "cpu"; | 57 | device_type = "cpu"; |
| @@ -464,6 +469,20 @@ | |||
| 464 | ti,hwmods = "wd_timer2"; | 469 | ti,hwmods = "wd_timer2"; |
| 465 | }; | 470 | }; |
| 466 | 471 | ||
| 472 | hwspinlock: spinlock@4a0f6000 { | ||
| 473 | compatible = "ti,omap4-hwspinlock"; | ||
| 474 | reg = <0x4a0f6000 0x1000>; | ||
| 475 | ti,hwmods = "spinlock"; | ||
| 476 | #hwlock-cells = <1>; | ||
| 477 | }; | ||
| 478 | |||
| 479 | dmm@4e000000 { | ||
| 480 | compatible = "ti,omap5-dmm"; | ||
| 481 | reg = <0x4e000000 0x800>; | ||
| 482 | interrupts = <0 113 0x4>; | ||
| 483 | ti,hwmods = "dmm"; | ||
| 484 | }; | ||
| 485 | |||
| 467 | i2c1: i2c@48070000 { | 486 | i2c1: i2c@48070000 { |
| 468 | compatible = "ti,omap4-i2c"; | 487 | compatible = "ti,omap4-i2c"; |
| 469 | reg = <0x48070000 0x100>; | 488 | reg = <0x48070000 0x100>; |
| @@ -559,6 +578,138 @@ | |||
| 559 | status = "disabled"; | 578 | status = "disabled"; |
| 560 | }; | 579 | }; |
| 561 | 580 | ||
| 581 | abb_mpu: regulator-abb-mpu { | ||
| 582 | compatible = "ti,abb-v3"; | ||
| 583 | regulator-name = "abb_mpu"; | ||
| 584 | #address-cells = <0>; | ||
| 585 | #size-cells = <0>; | ||
| 586 | clocks = <&sys_clkin1>; | ||
| 587 | ti,settling-time = <50>; | ||
| 588 | ti,clock-cycles = <16>; | ||
| 589 | |||
| 590 | reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, | ||
| 591 | <0x4ae06014 0x4>, <0x4a003b20 0x8>, | ||
| 592 | <0x4ae0c158 0x4>; | ||
| 593 | reg-names = "setup-address", "control-address", | ||
| 594 | "int-address", "efuse-address", | ||
| 595 | "ldo-address"; | ||
| 596 | ti,tranxdone-status-mask = <0x80>; | ||
| 597 | /* LDOVBBMPU_FBB_MUX_CTRL */ | ||
| 598 | ti,ldovbb-override-mask = <0x400>; | ||
| 599 | /* LDOVBBMPU_FBB_VSET_OUT */ | ||
| 600 | ti,ldovbb-vset-mask = <0x1F>; | ||
| 601 | |||
| 602 | /* | ||
| 603 | * NOTE: only FBB mode used but actual vset will | ||
| 604 | * determine final biasing | ||
| 605 | */ | ||
| 606 | ti,abb_info = < | ||
| 607 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | ||
| 608 | 1060000 0 0x0 0 0x02000000 0x01F00000 | ||
| 609 | 1160000 0 0x4 0 0x02000000 0x01F00000 | ||
| 610 | 1210000 0 0x8 0 0x02000000 0x01F00000 | ||
| 611 | >; | ||
| 612 | }; | ||
| 613 | |||
| 614 | abb_ivahd: regulator-abb-ivahd { | ||
| 615 | compatible = "ti,abb-v3"; | ||
| 616 | regulator-name = "abb_ivahd"; | ||
| 617 | #address-cells = <0>; | ||
| 618 | #size-cells = <0>; | ||
| 619 | clocks = <&sys_clkin1>; | ||
| 620 | ti,settling-time = <50>; | ||
| 621 | ti,clock-cycles = <16>; | ||
| 622 | |||
| 623 | reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, | ||
| 624 | <0x4ae06010 0x4>, <0x4a0025cc 0x8>, | ||
| 625 | <0x4a002470 0x4>; | ||
| 626 | reg-names = "setup-address", "control-address", | ||
| 627 | "int-address", "efuse-address", | ||
| 628 | "ldo-address"; | ||
| 629 | ti,tranxdone-status-mask = <0x40000000>; | ||
| 630 | /* LDOVBBIVA_FBB_MUX_CTRL */ | ||
| 631 | ti,ldovbb-override-mask = <0x400>; | ||
| 632 | /* LDOVBBIVA_FBB_VSET_OUT */ | ||
| 633 | ti,ldovbb-vset-mask = <0x1F>; | ||
| 634 | |||
| 635 | /* | ||
| 636 | * NOTE: only FBB mode used but actual vset will | ||
| 637 | * determine final biasing | ||
| 638 | */ | ||
| 639 | ti,abb_info = < | ||
| 640 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | ||
| 641 | 1055000 0 0x0 0 0x02000000 0x01F00000 | ||
| 642 | 1150000 0 0x4 0 0x02000000 0x01F00000 | ||
| 643 | 1250000 0 0x8 0 0x02000000 0x01F00000 | ||
| 644 | >; | ||
| 645 | }; | ||
| 646 | |||
| 647 | abb_dspeve: regulator-abb-dspeve { | ||
| 648 | compatible = "ti,abb-v3"; | ||
| 649 | regulator-name = "abb_dspeve"; | ||
| 650 | #address-cells = <0>; | ||
| 651 | #size-cells = <0>; | ||
| 652 | clocks = <&sys_clkin1>; | ||
| 653 | ti,settling-time = <50>; | ||
| 654 | ti,clock-cycles = <16>; | ||
| 655 | |||
| 656 | reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, | ||
| 657 | <0x4ae06010 0x4>, <0x4a0025e0 0x8>, | ||
| 658 | <0x4a00246c 0x4>; | ||
| 659 | reg-names = "setup-address", "control-address", | ||
| 660 | "int-address", "efuse-address", | ||
| 661 | "ldo-address"; | ||
| 662 | ti,tranxdone-status-mask = <0x20000000>; | ||
| 663 | /* LDOVBBDSPEVE_FBB_MUX_CTRL */ | ||
| 664 | ti,ldovbb-override-mask = <0x400>; | ||
| 665 | /* LDOVBBDSPEVE_FBB_VSET_OUT */ | ||
| 666 | ti,ldovbb-vset-mask = <0x1F>; | ||
| 667 | |||
| 668 | /* | ||
| 669 | * NOTE: only FBB mode used but actual vset will | ||
| 670 | * determine final biasing | ||
| 671 | */ | ||
| 672 | ti,abb_info = < | ||
| 673 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | ||
| 674 | 1055000 0 0x0 0 0x02000000 0x01F00000 | ||
| 675 | 1150000 0 0x4 0 0x02000000 0x01F00000 | ||
| 676 | 1250000 0 0x8 0 0x02000000 0x01F00000 | ||
| 677 | >; | ||
| 678 | }; | ||
| 679 | |||
| 680 | abb_gpu: regulator-abb-gpu { | ||
| 681 | compatible = "ti,abb-v3"; | ||
| 682 | regulator-name = "abb_gpu"; | ||
| 683 | #address-cells = <0>; | ||
| 684 | #size-cells = <0>; | ||
| 685 | clocks = <&sys_clkin1>; | ||
| 686 | ti,settling-time = <50>; | ||
| 687 | ti,clock-cycles = <16>; | ||
| 688 | |||
| 689 | reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, | ||
| 690 | <0x4ae06010 0x4>, <0x4a003b08 0x8>, | ||
| 691 | <0x4ae0c154 0x4>; | ||
| 692 | reg-names = "setup-address", "control-address", | ||
| 693 | "int-address", "efuse-address", | ||
| 694 | "ldo-address"; | ||
| 695 | ti,tranxdone-status-mask = <0x10000000>; | ||
| 696 | /* LDOVBBGPU_FBB_MUX_CTRL */ | ||
| 697 | ti,ldovbb-override-mask = <0x400>; | ||
| 698 | /* LDOVBBGPU_FBB_VSET_OUT */ | ||
| 699 | ti,ldovbb-vset-mask = <0x1F>; | ||
| 700 | |||
| 701 | /* | ||
| 702 | * NOTE: only FBB mode used but actual vset will | ||
| 703 | * determine final biasing | ||
| 704 | */ | ||
| 705 | ti,abb_info = < | ||
| 706 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | ||
| 707 | 1090000 0 0x0 0 0x02000000 0x01F00000 | ||
| 708 | 1210000 0 0x4 0 0x02000000 0x01F00000 | ||
| 709 | 1280000 0 0x8 0 0x02000000 0x01F00000 | ||
| 710 | >; | ||
| 711 | }; | ||
| 712 | |||
| 562 | mcspi1: spi@48098000 { | 713 | mcspi1: spi@48098000 { |
| 563 | compatible = "ti,omap4-mcspi"; | 714 | compatible = "ti,omap4-mcspi"; |
| 564 | reg = <0x48098000 0x200>; | 715 | reg = <0x48098000 0x200>; |
diff --git a/arch/arm/boot/dts/efm32gg-dk3750.dts b/arch/arm/boot/dts/efm32gg-dk3750.dts index aa5c0f6363d6..b4031fa4a567 100644 --- a/arch/arm/boot/dts/efm32gg-dk3750.dts +++ b/arch/arm/boot/dts/efm32gg-dk3750.dts | |||
| @@ -26,7 +26,7 @@ | |||
| 26 | }; | 26 | }; |
| 27 | 27 | ||
| 28 | i2c@4000a000 { | 28 | i2c@4000a000 { |
| 29 | location = <3>; | 29 | efm32,location = <3>; |
| 30 | status = "ok"; | 30 | status = "ok"; |
| 31 | 31 | ||
| 32 | temp@48 { | 32 | temp@48 { |
diff --git a/arch/arm/boot/dts/efm32gg.dtsi b/arch/arm/boot/dts/efm32gg.dtsi index a342ab0e6e4f..106d505c5d3d 100644 --- a/arch/arm/boot/dts/efm32gg.dtsi +++ b/arch/arm/boot/dts/efm32gg.dtsi | |||
| @@ -84,7 +84,7 @@ | |||
| 84 | status = "disabled"; | 84 | status = "disabled"; |
| 85 | }; | 85 | }; |
| 86 | 86 | ||
| 87 | spi2: spi@40x4000c800 { /* USART2 */ | 87 | spi2: spi@4000c800 { /* USART2 */ |
| 88 | #address-cells = <1>; | 88 | #address-cells = <1>; |
| 89 | #size-cells = <0>; | 89 | #size-cells = <0>; |
| 90 | compatible = "efm32,spi"; | 90 | compatible = "efm32,spi"; |
| @@ -110,7 +110,7 @@ | |||
| 110 | status = "disabled"; | 110 | status = "disabled"; |
| 111 | }; | 111 | }; |
| 112 | 112 | ||
| 113 | uart2: uart@40x4000c800 { /* USART2 */ | 113 | uart2: uart@4000c800 { /* USART2 */ |
| 114 | compatible = "efm32,uart"; | 114 | compatible = "efm32,uart"; |
| 115 | reg = <0x4000c800 0x400>; | 115 | reg = <0x4000c800 0x400>; |
| 116 | interrupts = <18 19>; | 116 | interrupts = <18 19>; |
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 08452e183b57..28b5ec79f339 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi | |||
| @@ -19,6 +19,7 @@ | |||
| 19 | * published by the Free Software Foundation. | 19 | * published by the Free Software Foundation. |
| 20 | */ | 20 | */ |
| 21 | 21 | ||
| 22 | #include <dt-bindings/clock/exynos4.h> | ||
| 22 | #include "skeleton.dtsi" | 23 | #include "skeleton.dtsi" |
| 23 | 24 | ||
| 24 | / { | 25 | / { |
| @@ -119,7 +120,7 @@ | |||
| 119 | compatible = "samsung,exynos4210-fimc"; | 120 | compatible = "samsung,exynos4210-fimc"; |
| 120 | reg = <0x11800000 0x1000>; | 121 | reg = <0x11800000 0x1000>; |
| 121 | interrupts = <0 84 0>; | 122 | interrupts = <0 84 0>; |
| 122 | clocks = <&clock 256>, <&clock 128>; | 123 | clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>; |
| 123 | clock-names = "fimc", "sclk_fimc"; | 124 | clock-names = "fimc", "sclk_fimc"; |
| 124 | samsung,power-domain = <&pd_cam>; | 125 | samsung,power-domain = <&pd_cam>; |
| 125 | samsung,sysreg = <&sys_reg>; | 126 | samsung,sysreg = <&sys_reg>; |
| @@ -130,7 +131,7 @@ | |||
| 130 | compatible = "samsung,exynos4210-fimc"; | 131 | compatible = "samsung,exynos4210-fimc"; |
| 131 | reg = <0x11810000 0x1000>; | 132 | reg = <0x11810000 0x1000>; |
| 132 | interrupts = <0 85 0>; | 133 | interrupts = <0 85 0>; |
| 133 | clocks = <&clock 257>, <&clock 129>; | 134 | clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>; |
| 134 | clock-names = "fimc", "sclk_fimc"; | 135 | clock-names = "fimc", "sclk_fimc"; |
| 135 | samsung,power-domain = <&pd_cam>; | 136 | samsung,power-domain = <&pd_cam>; |
| 136 | samsung,sysreg = <&sys_reg>; | 137 | samsung,sysreg = <&sys_reg>; |
| @@ -141,7 +142,7 @@ | |||
| 141 | compatible = "samsung,exynos4210-fimc"; | 142 | compatible = "samsung,exynos4210-fimc"; |
| 142 | reg = <0x11820000 0x1000>; | 143 | reg = <0x11820000 0x1000>; |
| 143 | interrupts = <0 86 0>; | 144 | interrupts = <0 86 0>; |
| 144 | clocks = <&clock 258>, <&clock 130>; | 145 | clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>; |
| 145 | clock-names = "fimc", "sclk_fimc"; | 146 | clock-names = "fimc", "sclk_fimc"; |
| 146 | samsung,power-domain = <&pd_cam>; | 147 | samsung,power-domain = <&pd_cam>; |
| 147 | samsung,sysreg = <&sys_reg>; | 148 | samsung,sysreg = <&sys_reg>; |
| @@ -152,7 +153,7 @@ | |||
| 152 | compatible = "samsung,exynos4210-fimc"; | 153 | compatible = "samsung,exynos4210-fimc"; |
| 153 | reg = <0x11830000 0x1000>; | 154 | reg = <0x11830000 0x1000>; |
| 154 | interrupts = <0 87 0>; | 155 | interrupts = <0 87 0>; |
| 155 | clocks = <&clock 259>, <&clock 131>; | 156 | clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>; |
| 156 | clock-names = "fimc", "sclk_fimc"; | 157 | clock-names = "fimc", "sclk_fimc"; |
| 157 | samsung,power-domain = <&pd_cam>; | 158 | samsung,power-domain = <&pd_cam>; |
| 158 | samsung,sysreg = <&sys_reg>; | 159 | samsung,sysreg = <&sys_reg>; |
| @@ -163,7 +164,7 @@ | |||
| 163 | compatible = "samsung,exynos4210-csis"; | 164 | compatible = "samsung,exynos4210-csis"; |
| 164 | reg = <0x11880000 0x4000>; | 165 | reg = <0x11880000 0x4000>; |
| 165 | interrupts = <0 78 0>; | 166 | interrupts = <0 78 0>; |
| 166 | clocks = <&clock 260>, <&clock 134>; | 167 | clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>; |
| 167 | clock-names = "csis", "sclk_csis"; | 168 | clock-names = "csis", "sclk_csis"; |
| 168 | bus-width = <4>; | 169 | bus-width = <4>; |
| 169 | samsung,power-domain = <&pd_cam>; | 170 | samsung,power-domain = <&pd_cam>; |
| @@ -178,7 +179,7 @@ | |||
| 178 | compatible = "samsung,exynos4210-csis"; | 179 | compatible = "samsung,exynos4210-csis"; |
| 179 | reg = <0x11890000 0x4000>; | 180 | reg = <0x11890000 0x4000>; |
| 180 | interrupts = <0 80 0>; | 181 | interrupts = <0 80 0>; |
| 181 | clocks = <&clock 261>, <&clock 135>; | 182 | clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>; |
| 182 | clock-names = "csis", "sclk_csis"; | 183 | clock-names = "csis", "sclk_csis"; |
| 183 | bus-width = <2>; | 184 | bus-width = <2>; |
| 184 | samsung,power-domain = <&pd_cam>; | 185 | samsung,power-domain = <&pd_cam>; |
| @@ -194,7 +195,7 @@ | |||
| 194 | compatible = "samsung,s3c2410-wdt"; | 195 | compatible = "samsung,s3c2410-wdt"; |
| 195 | reg = <0x10060000 0x100>; | 196 | reg = <0x10060000 0x100>; |
| 196 | interrupts = <0 43 0>; | 197 | interrupts = <0 43 0>; |
| 197 | clocks = <&clock 345>; | 198 | clocks = <&clock CLK_WDT>; |
| 198 | clock-names = "watchdog"; | 199 | clock-names = "watchdog"; |
| 199 | status = "disabled"; | 200 | status = "disabled"; |
| 200 | }; | 201 | }; |
| @@ -203,7 +204,7 @@ | |||
| 203 | compatible = "samsung,s3c6410-rtc"; | 204 | compatible = "samsung,s3c6410-rtc"; |
| 204 | reg = <0x10070000 0x100>; | 205 | reg = <0x10070000 0x100>; |
| 205 | interrupts = <0 44 0>, <0 45 0>; | 206 | interrupts = <0 44 0>, <0 45 0>; |
| 206 | clocks = <&clock 346>; | 207 | clocks = <&clock CLK_RTC>; |
| 207 | clock-names = "rtc"; | 208 | clock-names = "rtc"; |
| 208 | status = "disabled"; | 209 | status = "disabled"; |
| 209 | }; | 210 | }; |
| @@ -212,7 +213,7 @@ | |||
| 212 | compatible = "samsung,s5pv210-keypad"; | 213 | compatible = "samsung,s5pv210-keypad"; |
| 213 | reg = <0x100A0000 0x100>; | 214 | reg = <0x100A0000 0x100>; |
| 214 | interrupts = <0 109 0>; | 215 | interrupts = <0 109 0>; |
| 215 | clocks = <&clock 347>; | 216 | clocks = <&clock CLK_KEYIF>; |
| 216 | clock-names = "keypad"; | 217 | clock-names = "keypad"; |
| 217 | status = "disabled"; | 218 | status = "disabled"; |
| 218 | }; | 219 | }; |
| @@ -221,7 +222,7 @@ | |||
| 221 | compatible = "samsung,exynos4210-sdhci"; | 222 | compatible = "samsung,exynos4210-sdhci"; |
| 222 | reg = <0x12510000 0x100>; | 223 | reg = <0x12510000 0x100>; |
| 223 | interrupts = <0 73 0>; | 224 | interrupts = <0 73 0>; |
| 224 | clocks = <&clock 297>, <&clock 145>; | 225 | clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; |
| 225 | clock-names = "hsmmc", "mmc_busclk.2"; | 226 | clock-names = "hsmmc", "mmc_busclk.2"; |
| 226 | status = "disabled"; | 227 | status = "disabled"; |
| 227 | }; | 228 | }; |
| @@ -230,7 +231,7 @@ | |||
| 230 | compatible = "samsung,exynos4210-sdhci"; | 231 | compatible = "samsung,exynos4210-sdhci"; |
| 231 | reg = <0x12520000 0x100>; | 232 | reg = <0x12520000 0x100>; |
| 232 | interrupts = <0 74 0>; | 233 | interrupts = <0 74 0>; |
| 233 | clocks = <&clock 298>, <&clock 146>; | 234 | clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; |
| 234 | clock-names = "hsmmc", "mmc_busclk.2"; | 235 | clock-names = "hsmmc", "mmc_busclk.2"; |
| 235 | status = "disabled"; | 236 | status = "disabled"; |
| 236 | }; | 237 | }; |
| @@ -239,7 +240,7 @@ | |||
| 239 | compatible = "samsung,exynos4210-sdhci"; | 240 | compatible = "samsung,exynos4210-sdhci"; |
| 240 | reg = <0x12530000 0x100>; | 241 | reg = <0x12530000 0x100>; |
| 241 | interrupts = <0 75 0>; | 242 | interrupts = <0 75 0>; |
| 242 | clocks = <&clock 299>, <&clock 147>; | 243 | clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; |
| 243 | clock-names = "hsmmc", "mmc_busclk.2"; | 244 | clock-names = "hsmmc", "mmc_busclk.2"; |
| 244 | status = "disabled"; | 245 | status = "disabled"; |
| 245 | }; | 246 | }; |
| @@ -248,7 +249,7 @@ | |||
| 248 | compatible = "samsung,exynos4210-sdhci"; | 249 | compatible = "samsung,exynos4210-sdhci"; |
| 249 | reg = <0x12540000 0x100>; | 250 | reg = <0x12540000 0x100>; |
| 250 | interrupts = <0 76 0>; | 251 | interrupts = <0 76 0>; |
| 251 | clocks = <&clock 300>, <&clock 148>; | 252 | clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; |
| 252 | clock-names = "hsmmc", "mmc_busclk.2"; | 253 | clock-names = "hsmmc", "mmc_busclk.2"; |
| 253 | status = "disabled"; | 254 | status = "disabled"; |
| 254 | }; | 255 | }; |
| @@ -257,7 +258,7 @@ | |||
| 257 | compatible = "samsung,exynos4210-ehci"; | 258 | compatible = "samsung,exynos4210-ehci"; |
| 258 | reg = <0x12580000 0x100>; | 259 | reg = <0x12580000 0x100>; |
| 259 | interrupts = <0 70 0>; | 260 | interrupts = <0 70 0>; |
| 260 | clocks = <&clock 304>; | 261 | clocks = <&clock CLK_USB_HOST>; |
| 261 | clock-names = "usbhost"; | 262 | clock-names = "usbhost"; |
| 262 | status = "disabled"; | 263 | status = "disabled"; |
| 263 | }; | 264 | }; |
| @@ -266,7 +267,7 @@ | |||
| 266 | compatible = "samsung,exynos4210-ohci"; | 267 | compatible = "samsung,exynos4210-ohci"; |
| 267 | reg = <0x12590000 0x100>; | 268 | reg = <0x12590000 0x100>; |
| 268 | interrupts = <0 70 0>; | 269 | interrupts = <0 70 0>; |
| 269 | clocks = <&clock 304>; | 270 | clocks = <&clock CLK_USB_HOST>; |
| 270 | clock-names = "usbhost"; | 271 | clock-names = "usbhost"; |
| 271 | status = "disabled"; | 272 | status = "disabled"; |
| 272 | }; | 273 | }; |
| @@ -276,7 +277,7 @@ | |||
| 276 | reg = <0x13400000 0x10000>; | 277 | reg = <0x13400000 0x10000>; |
| 277 | interrupts = <0 94 0>; | 278 | interrupts = <0 94 0>; |
| 278 | samsung,power-domain = <&pd_mfc>; | 279 | samsung,power-domain = <&pd_mfc>; |
| 279 | clocks = <&clock 273>; | 280 | clocks = <&clock CLK_MFC>; |
| 280 | clock-names = "mfc"; | 281 | clock-names = "mfc"; |
| 281 | status = "disabled"; | 282 | status = "disabled"; |
| 282 | }; | 283 | }; |
| @@ -285,7 +286,7 @@ | |||
| 285 | compatible = "samsung,exynos4210-uart"; | 286 | compatible = "samsung,exynos4210-uart"; |
| 286 | reg = <0x13800000 0x100>; | 287 | reg = <0x13800000 0x100>; |
| 287 | interrupts = <0 52 0>; | 288 | interrupts = <0 52 0>; |
| 288 | clocks = <&clock 312>, <&clock 151>; | 289 | clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; |
| 289 | clock-names = "uart", "clk_uart_baud0"; | 290 | clock-names = "uart", "clk_uart_baud0"; |
| 290 | status = "disabled"; | 291 | status = "disabled"; |
| 291 | }; | 292 | }; |
| @@ -294,7 +295,7 @@ | |||
| 294 | compatible = "samsung,exynos4210-uart"; | 295 | compatible = "samsung,exynos4210-uart"; |
| 295 | reg = <0x13810000 0x100>; | 296 | reg = <0x13810000 0x100>; |
| 296 | interrupts = <0 53 0>; | 297 | interrupts = <0 53 0>; |
| 297 | clocks = <&clock 313>, <&clock 152>; | 298 | clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; |
| 298 | clock-names = "uart", "clk_uart_baud0"; | 299 | clock-names = "uart", "clk_uart_baud0"; |
| 299 | status = "disabled"; | 300 | status = "disabled"; |
| 300 | }; | 301 | }; |
| @@ -303,7 +304,7 @@ | |||
| 303 | compatible = "samsung,exynos4210-uart"; | 304 | compatible = "samsung,exynos4210-uart"; |
| 304 | reg = <0x13820000 0x100>; | 305 | reg = <0x13820000 0x100>; |
| 305 | interrupts = <0 54 0>; | 306 | interrupts = <0 54 0>; |
| 306 | clocks = <&clock 314>, <&clock 153>; | 307 | clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; |
| 307 | clock-names = "uart", "clk_uart_baud0"; | 308 | clock-names = "uart", "clk_uart_baud0"; |
| 308 | status = "disabled"; | 309 | status = "disabled"; |
| 309 | }; | 310 | }; |
| @@ -312,7 +313,7 @@ | |||
| 312 | compatible = "samsung,exynos4210-uart"; | 313 | compatible = "samsung,exynos4210-uart"; |
| 313 | reg = <0x13830000 0x100>; | 314 | reg = <0x13830000 0x100>; |
| 314 | interrupts = <0 55 0>; | 315 | interrupts = <0 55 0>; |
| 315 | clocks = <&clock 315>, <&clock 154>; | 316 | clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; |
| 316 | clock-names = "uart", "clk_uart_baud0"; | 317 | clock-names = "uart", "clk_uart_baud0"; |
| 317 | status = "disabled"; | 318 | status = "disabled"; |
| 318 | }; | 319 | }; |
| @@ -323,7 +324,7 @@ | |||
| 323 | compatible = "samsung,s3c2440-i2c"; | 324 | compatible = "samsung,s3c2440-i2c"; |
| 324 | reg = <0x13860000 0x100>; | 325 | reg = <0x13860000 0x100>; |
| 325 | interrupts = <0 58 0>; | 326 | interrupts = <0 58 0>; |
| 326 | clocks = <&clock 317>; | 327 | clocks = <&clock CLK_I2C0>; |
| 327 | clock-names = "i2c"; | 328 | clock-names = "i2c"; |
| 328 | pinctrl-names = "default"; | 329 | pinctrl-names = "default"; |
| 329 | pinctrl-0 = <&i2c0_bus>; | 330 | pinctrl-0 = <&i2c0_bus>; |
| @@ -336,7 +337,7 @@ | |||
| 336 | compatible = "samsung,s3c2440-i2c"; | 337 | compatible = "samsung,s3c2440-i2c"; |
| 337 | reg = <0x13870000 0x100>; | 338 | reg = <0x13870000 0x100>; |
| 338 | interrupts = <0 59 0>; | 339 | interrupts = <0 59 0>; |
| 339 | clocks = <&clock 318>; | 340 | clocks = <&clock CLK_I2C1>; |
| 340 | clock-names = "i2c"; | 341 | clock-names = "i2c"; |
| 341 | pinctrl-names = "default"; | 342 | pinctrl-names = "default"; |
| 342 | pinctrl-0 = <&i2c1_bus>; | 343 | pinctrl-0 = <&i2c1_bus>; |
| @@ -349,7 +350,7 @@ | |||
| 349 | compatible = "samsung,s3c2440-i2c"; | 350 | compatible = "samsung,s3c2440-i2c"; |
| 350 | reg = <0x13880000 0x100>; | 351 | reg = <0x13880000 0x100>; |
| 351 | interrupts = <0 60 0>; | 352 | interrupts = <0 60 0>; |
| 352 | clocks = <&clock 319>; | 353 | clocks = <&clock CLK_I2C2>; |
| 353 | clock-names = "i2c"; | 354 | clock-names = "i2c"; |
| 354 | status = "disabled"; | 355 | status = "disabled"; |
| 355 | }; | 356 | }; |
| @@ -360,7 +361,7 @@ | |||
| 360 | compatible = "samsung,s3c2440-i2c"; | 361 | compatible = "samsung,s3c2440-i2c"; |
| 361 | reg = <0x13890000 0x100>; | 362 | reg = <0x13890000 0x100>; |
| 362 | interrupts = <0 61 0>; | 363 | interrupts = <0 61 0>; |
| 363 | clocks = <&clock 320>; | 364 | clocks = <&clock CLK_I2C3>; |
| 364 | clock-names = "i2c"; | 365 | clock-names = "i2c"; |
| 365 | status = "disabled"; | 366 | status = "disabled"; |
| 366 | }; | 367 | }; |
| @@ -371,7 +372,7 @@ | |||
| 371 | compatible = "samsung,s3c2440-i2c"; | 372 | compatible = "samsung,s3c2440-i2c"; |
| 372 | reg = <0x138A0000 0x100>; | 373 | reg = <0x138A0000 0x100>; |
| 373 | interrupts = <0 62 0>; | 374 | interrupts = <0 62 0>; |
| 374 | clocks = <&clock 321>; | 375 | clocks = <&clock CLK_I2C4>; |
| 375 | clock-names = "i2c"; | 376 | clock-names = "i2c"; |
| 376 | status = "disabled"; | 377 | status = "disabled"; |
| 377 | }; | 378 | }; |
| @@ -382,7 +383,7 @@ | |||
| 382 | compatible = "samsung,s3c2440-i2c"; | 383 | compatible = "samsung,s3c2440-i2c"; |
| 383 | reg = <0x138B0000 0x100>; | 384 | reg = <0x138B0000 0x100>; |
| 384 | interrupts = <0 63 0>; | 385 | interrupts = <0 63 0>; |
| 385 | clocks = <&clock 322>; | 386 | clocks = <&clock CLK_I2C5>; |
| 386 | clock-names = "i2c"; | 387 | clock-names = "i2c"; |
| 387 | status = "disabled"; | 388 | status = "disabled"; |
| 388 | }; | 389 | }; |
| @@ -393,7 +394,7 @@ | |||
| 393 | compatible = "samsung,s3c2440-i2c"; | 394 | compatible = "samsung,s3c2440-i2c"; |
| 394 | reg = <0x138C0000 0x100>; | 395 | reg = <0x138C0000 0x100>; |
| 395 | interrupts = <0 64 0>; | 396 | interrupts = <0 64 0>; |
| 396 | clocks = <&clock 323>; | 397 | clocks = <&clock CLK_I2C6>; |
| 397 | clock-names = "i2c"; | 398 | clock-names = "i2c"; |
| 398 | status = "disabled"; | 399 | status = "disabled"; |
| 399 | }; | 400 | }; |
| @@ -404,7 +405,7 @@ | |||
| 404 | compatible = "samsung,s3c2440-i2c"; | 405 | compatible = "samsung,s3c2440-i2c"; |
| 405 | reg = <0x138D0000 0x100>; | 406 | reg = <0x138D0000 0x100>; |
| 406 | interrupts = <0 65 0>; | 407 | interrupts = <0 65 0>; |
| 407 | clocks = <&clock 324>; | 408 | clocks = <&clock CLK_I2C7>; |
| 408 | clock-names = "i2c"; | 409 | clock-names = "i2c"; |
| 409 | status = "disabled"; | 410 | status = "disabled"; |
| 410 | }; | 411 | }; |
| @@ -417,7 +418,7 @@ | |||
| 417 | dma-names = "tx", "rx"; | 418 | dma-names = "tx", "rx"; |
| 418 | #address-cells = <1>; | 419 | #address-cells = <1>; |
| 419 | #size-cells = <0>; | 420 | #size-cells = <0>; |
| 420 | clocks = <&clock 327>, <&clock 159>; | 421 | clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; |
| 421 | clock-names = "spi", "spi_busclk0"; | 422 | clock-names = "spi", "spi_busclk0"; |
| 422 | pinctrl-names = "default"; | 423 | pinctrl-names = "default"; |
| 423 | pinctrl-0 = <&spi0_bus>; | 424 | pinctrl-0 = <&spi0_bus>; |
| @@ -432,7 +433,7 @@ | |||
| 432 | dma-names = "tx", "rx"; | 433 | dma-names = "tx", "rx"; |
| 433 | #address-cells = <1>; | 434 | #address-cells = <1>; |
| 434 | #size-cells = <0>; | 435 | #size-cells = <0>; |
| 435 | clocks = <&clock 328>, <&clock 160>; | 436 | clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; |
| 436 | clock-names = "spi", "spi_busclk0"; | 437 | clock-names = "spi", "spi_busclk0"; |
| 437 | pinctrl-names = "default"; | 438 | pinctrl-names = "default"; |
| 438 | pinctrl-0 = <&spi1_bus>; | 439 | pinctrl-0 = <&spi1_bus>; |
| @@ -447,7 +448,7 @@ | |||
| 447 | dma-names = "tx", "rx"; | 448 | dma-names = "tx", "rx"; |
| 448 | #address-cells = <1>; | 449 | #address-cells = <1>; |
| 449 | #size-cells = <0>; | 450 | #size-cells = <0>; |
| 450 | clocks = <&clock 329>, <&clock 161>; | 451 | clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; |
| 451 | clock-names = "spi", "spi_busclk0"; | 452 | clock-names = "spi", "spi_busclk0"; |
| 452 | pinctrl-names = "default"; | 453 | pinctrl-names = "default"; |
| 453 | pinctrl-0 = <&spi2_bus>; | 454 | pinctrl-0 = <&spi2_bus>; |
| @@ -458,7 +459,7 @@ | |||
| 458 | compatible = "samsung,exynos4210-pwm"; | 459 | compatible = "samsung,exynos4210-pwm"; |
| 459 | reg = <0x139D0000 0x1000>; | 460 | reg = <0x139D0000 0x1000>; |
| 460 | interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>; | 461 | interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>; |
| 461 | clocks = <&clock 336>; | 462 | clocks = <&clock CLK_PWM>; |
| 462 | clock-names = "timers"; | 463 | clock-names = "timers"; |
| 463 | #pwm-cells = <2>; | 464 | #pwm-cells = <2>; |
| 464 | status = "disabled"; | 465 | status = "disabled"; |
| @@ -475,7 +476,7 @@ | |||
| 475 | compatible = "arm,pl330", "arm,primecell"; | 476 | compatible = "arm,pl330", "arm,primecell"; |
| 476 | reg = <0x12680000 0x1000>; | 477 | reg = <0x12680000 0x1000>; |
| 477 | interrupts = <0 35 0>; | 478 | interrupts = <0 35 0>; |
| 478 | clocks = <&clock 292>; | 479 | clocks = <&clock CLK_PDMA0>; |
| 479 | clock-names = "apb_pclk"; | 480 | clock-names = "apb_pclk"; |
| 480 | #dma-cells = <1>; | 481 | #dma-cells = <1>; |
| 481 | #dma-channels = <8>; | 482 | #dma-channels = <8>; |
| @@ -486,7 +487,7 @@ | |||
| 486 | compatible = "arm,pl330", "arm,primecell"; | 487 | compatible = "arm,pl330", "arm,primecell"; |
| 487 | reg = <0x12690000 0x1000>; | 488 | reg = <0x12690000 0x1000>; |
| 488 | interrupts = <0 36 0>; | 489 | interrupts = <0 36 0>; |
| 489 | clocks = <&clock 293>; | 490 | clocks = <&clock CLK_PDMA1>; |
| 490 | clock-names = "apb_pclk"; | 491 | clock-names = "apb_pclk"; |
| 491 | #dma-cells = <1>; | 492 | #dma-cells = <1>; |
| 492 | #dma-channels = <8>; | 493 | #dma-channels = <8>; |
| @@ -497,7 +498,7 @@ | |||
| 497 | compatible = "arm,pl330", "arm,primecell"; | 498 | compatible = "arm,pl330", "arm,primecell"; |
| 498 | reg = <0x12850000 0x1000>; | 499 | reg = <0x12850000 0x1000>; |
| 499 | interrupts = <0 34 0>; | 500 | interrupts = <0 34 0>; |
| 500 | clocks = <&clock 279>; | 501 | clocks = <&clock CLK_MDMA>; |
| 501 | clock-names = "apb_pclk"; | 502 | clock-names = "apb_pclk"; |
| 502 | #dma-cells = <1>; | 503 | #dma-cells = <1>; |
| 503 | #dma-channels = <8>; | 504 | #dma-channels = <8>; |
| @@ -511,7 +512,7 @@ | |||
| 511 | reg = <0x11c00000 0x20000>; | 512 | reg = <0x11c00000 0x20000>; |
| 512 | interrupt-names = "fifo", "vsync", "lcd_sys"; | 513 | interrupt-names = "fifo", "vsync", "lcd_sys"; |
| 513 | interrupts = <11 0>, <11 1>, <11 2>; | 514 | interrupts = <11 0>, <11 1>, <11 2>; |
| 514 | clocks = <&clock 140>, <&clock 283>; | 515 | clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>; |
| 515 | clock-names = "sclk_fimd", "fimd"; | 516 | clock-names = "sclk_fimd", "fimd"; |
| 516 | samsung,power-domain = <&pd_lcd0>; | 517 | samsung,power-domain = <&pd_lcd0>; |
| 517 | status = "disabled"; | 518 | status = "disabled"; |
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 48ecd7a755ab..cb0e768dc6d4 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi | |||
| @@ -53,7 +53,7 @@ | |||
| 53 | reg = <0x10050000 0x800>; | 53 | reg = <0x10050000 0x800>; |
| 54 | interrupt-parent = <&mct_map>; | 54 | interrupt-parent = <&mct_map>; |
| 55 | interrupts = <0>, <1>, <2>, <3>, <4>, <5>; | 55 | interrupts = <0>, <1>, <2>, <3>, <4>, <5>; |
| 56 | clocks = <&clock 3>, <&clock 344>; | 56 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; |
| 57 | clock-names = "fin_pll", "mct"; | 57 | clock-names = "fin_pll", "mct"; |
| 58 | 58 | ||
| 59 | mct_map: mct-map { | 59 | mct_map: mct-map { |
| @@ -109,7 +109,7 @@ | |||
| 109 | interrupt-parent = <&combiner>; | 109 | interrupt-parent = <&combiner>; |
| 110 | reg = <0x100C0000 0x100>; | 110 | reg = <0x100C0000 0x100>; |
| 111 | interrupts = <2 4>; | 111 | interrupts = <2 4>; |
| 112 | clocks = <&clock 383>; | 112 | clocks = <&clock CLK_TMU_APBIF>; |
| 113 | clock-names = "tmu_apbif"; | 113 | clock-names = "tmu_apbif"; |
| 114 | status = "disabled"; | 114 | status = "disabled"; |
| 115 | }; | 115 | }; |
| @@ -118,13 +118,14 @@ | |||
| 118 | compatible = "samsung,s5pv210-g2d"; | 118 | compatible = "samsung,s5pv210-g2d"; |
| 119 | reg = <0x12800000 0x1000>; | 119 | reg = <0x12800000 0x1000>; |
| 120 | interrupts = <0 89 0>; | 120 | interrupts = <0 89 0>; |
| 121 | clocks = <&clock 177>, <&clock 277>; | 121 | clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; |
| 122 | clock-names = "sclk_fimg2d", "fimg2d"; | 122 | clock-names = "sclk_fimg2d", "fimg2d"; |
| 123 | status = "disabled"; | 123 | status = "disabled"; |
| 124 | }; | 124 | }; |
| 125 | 125 | ||
| 126 | camera { | 126 | camera { |
| 127 | clocks = <&clock 132>, <&clock 133>, <&clock 351>, <&clock 352>; | 127 | clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, |
| 128 | <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; | ||
| 128 | clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; | 129 | clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; |
| 129 | 130 | ||
| 130 | fimc_0: fimc@11800000 { | 131 | fimc_0: fimc@11800000 { |
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 9804fcb71f8c..12459b01cca3 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts | |||
| @@ -251,7 +251,7 @@ | |||
| 251 | buck2_reg: BUCK2 { | 251 | buck2_reg: BUCK2 { |
| 252 | regulator-name = "vdd_arm"; | 252 | regulator-name = "vdd_arm"; |
| 253 | regulator-min-microvolt = <900000>; | 253 | regulator-min-microvolt = <900000>; |
| 254 | regulator-max-microvolt = <1300000>; | 254 | regulator-max-microvolt = <1350000>; |
| 255 | regulator-always-on; | 255 | regulator-always-on; |
| 256 | regulator-boot-on; | 256 | regulator-boot-on; |
| 257 | }; | 257 | }; |
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index 6bc053924e9e..388f03579661 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts | |||
| @@ -459,8 +459,8 @@ | |||
| 459 | 459 | ||
| 460 | buck2_reg: BUCK2 { | 460 | buck2_reg: BUCK2 { |
| 461 | regulator-name = "vdd_arm"; | 461 | regulator-name = "vdd_arm"; |
| 462 | regulator-min-microvolt = <925000>; | 462 | regulator-min-microvolt = <900000>; |
| 463 | regulator-max-microvolt = <1300000>; | 463 | regulator-max-microvolt = <1350000>; |
| 464 | regulator-always-on; | 464 | regulator-always-on; |
| 465 | regulator-boot-on; | 465 | regulator-boot-on; |
| 466 | op_mode = <1>; /* Normal Mode */ | 466 | op_mode = <1>; /* Normal Mode */ |
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index 5c412aa14738..e0eb6bb64c34 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi | |||
| @@ -47,7 +47,7 @@ | |||
| 47 | reg = <0x10050000 0x800>; | 47 | reg = <0x10050000 0x800>; |
| 48 | interrupt-parent = <&mct_map>; | 48 | interrupt-parent = <&mct_map>; |
| 49 | interrupts = <0>, <1>, <2>, <3>, <4>; | 49 | interrupts = <0>, <1>, <2>, <3>, <4>; |
| 50 | clocks = <&clock 3>, <&clock 344>; | 50 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; |
| 51 | clock-names = "fin_pll", "mct"; | 51 | clock-names = "fin_pll", "mct"; |
| 52 | 52 | ||
| 53 | mct_map: mct-map { | 53 | mct_map: mct-map { |
| @@ -97,13 +97,14 @@ | |||
| 97 | compatible = "samsung,exynos4212-g2d"; | 97 | compatible = "samsung,exynos4212-g2d"; |
| 98 | reg = <0x10800000 0x1000>; | 98 | reg = <0x10800000 0x1000>; |
| 99 | interrupts = <0 89 0>; | 99 | interrupts = <0 89 0>; |
| 100 | clocks = <&clock 177>, <&clock 277>; | 100 | clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; |
| 101 | clock-names = "sclk_fimg2d", "fimg2d"; | 101 | clock-names = "sclk_fimg2d", "fimg2d"; |
| 102 | status = "disabled"; | 102 | status = "disabled"; |
| 103 | }; | 103 | }; |
| 104 | 104 | ||
| 105 | camera { | 105 | camera { |
| 106 | clocks = <&clock 132>, <&clock 133>, <&clock 351>, <&clock 352>; | 106 | clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, |
| 107 | <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; | ||
| 107 | clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; | 108 | clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; |
| 108 | 109 | ||
| 109 | fimc_0: fimc@11800000 { | 110 | fimc_0: fimc@11800000 { |
| @@ -145,7 +146,7 @@ | |||
| 145 | reg = <0x12390000 0x1000>; | 146 | reg = <0x12390000 0x1000>; |
| 146 | interrupts = <0 105 0>; | 147 | interrupts = <0 105 0>; |
| 147 | samsung,power-domain = <&pd_isp>; | 148 | samsung,power-domain = <&pd_isp>; |
| 148 | clocks = <&clock 353>; | 149 | clocks = <&clock CLK_FIMC_LITE0>; |
| 149 | clock-names = "flite"; | 150 | clock-names = "flite"; |
| 150 | status = "disabled"; | 151 | status = "disabled"; |
| 151 | }; | 152 | }; |
| @@ -155,7 +156,7 @@ | |||
| 155 | reg = <0x123A0000 0x1000>; | 156 | reg = <0x123A0000 0x1000>; |
| 156 | interrupts = <0 106 0>; | 157 | interrupts = <0 106 0>; |
| 157 | samsung,power-domain = <&pd_isp>; | 158 | samsung,power-domain = <&pd_isp>; |
| 158 | clocks = <&clock 354>; | 159 | clocks = <&clock CLK_FIMC_LITE1>; |
| 159 | clock-names = "flite"; | 160 | clock-names = "flite"; |
| 160 | status = "disabled"; | 161 | status = "disabled"; |
| 161 | }; | 162 | }; |
| @@ -165,12 +166,19 @@ | |||
| 165 | reg = <0x12000000 0x260000>; | 166 | reg = <0x12000000 0x260000>; |
| 166 | interrupts = <0 90 0>, <0 95 0>; | 167 | interrupts = <0 90 0>, <0 95 0>; |
| 167 | samsung,power-domain = <&pd_isp>; | 168 | samsung,power-domain = <&pd_isp>; |
| 168 | clocks = <&clock 353>, <&clock 354>, <&clock 355>, | 169 | clocks = <&clock CLK_FIMC_LITE0>, |
| 169 | <&clock 356>, <&clock 17>, <&clock 357>, | 170 | <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>, |
| 170 | <&clock 358>, <&clock 359>, <&clock 360>, | 171 | <&clock CLK_PPMUISPMX>, |
| 171 | <&clock 450>,<&clock 451>, <&clock 452>, | 172 | <&clock CLK_MOUT_MPLL_USER_T>, |
| 172 | <&clock 453>, <&clock 176>, <&clock 13>, | 173 | <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>, |
| 173 | <&clock 454>, <&clock 395>, <&clock 455>; | 174 | <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>, |
| 175 | <&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>, | ||
| 176 | <&clock CLK_DIV_MCUISP0>, | ||
| 177 | <&clock CLK_DIV_MCUISP1>, | ||
| 178 | <&clock CLK_SCLK_UART_ISP>, | ||
| 179 | <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>, | ||
| 180 | <&clock CLK_ACLK400_MCUISP>, | ||
| 181 | <&clock CLK_DIV_ACLK400_MCUISP>; | ||
| 174 | clock-names = "lite0", "lite1", "ppmuispx", | 182 | clock-names = "lite0", "lite1", "ppmuispx", |
| 175 | "ppmuispmx", "mpll", "isp", | 183 | "ppmuispmx", "mpll", "isp", |
| 176 | "drc", "fd", "mcuisp", | 184 | "drc", "fd", "mcuisp", |
| @@ -190,7 +198,7 @@ | |||
| 190 | i2c1_isp: i2c-isp@12140000 { | 198 | i2c1_isp: i2c-isp@12140000 { |
| 191 | compatible = "samsung,exynos4212-i2c-isp"; | 199 | compatible = "samsung,exynos4212-i2c-isp"; |
| 192 | reg = <0x12140000 0x100>; | 200 | reg = <0x12140000 0x100>; |
| 193 | clocks = <&clock 370>; | 201 | clocks = <&clock CLK_I2C1_ISP>; |
| 194 | clock-names = "i2c_isp"; | 202 | clock-names = "i2c_isp"; |
| 195 | #address-cells = <1>; | 203 | #address-cells = <1>; |
| 196 | #size-cells = <0>; | 204 | #size-cells = <0>; |
| @@ -205,7 +213,7 @@ | |||
| 205 | #address-cells = <1>; | 213 | #address-cells = <1>; |
| 206 | #size-cells = <0>; | 214 | #size-cells = <0>; |
| 207 | fifo-depth = <0x80>; | 215 | fifo-depth = <0x80>; |
| 208 | clocks = <&clock 301>, <&clock 149>; | 216 | clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>; |
| 209 | clock-names = "biu", "ciu"; | 217 | clock-names = "biu", "ciu"; |
| 210 | status = "disabled"; | 218 | status = "disabled"; |
| 211 | }; | 219 | }; |
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index 258dca441f36..79d0608d6dcc 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi | |||
| @@ -81,13 +81,6 @@ | |||
| 81 | status = "disabled"; | 81 | status = "disabled"; |
| 82 | }; | 82 | }; |
| 83 | 83 | ||
| 84 | watchdog { | ||
| 85 | compatible = "samsung,s3c2410-wdt"; | ||
| 86 | reg = <0x101D0000 0x100>; | ||
| 87 | interrupts = <0 42 0>; | ||
| 88 | status = "disabled"; | ||
| 89 | }; | ||
| 90 | |||
| 91 | fimd@14400000 { | 84 | fimd@14400000 { |
| 92 | compatible = "samsung,exynos5250-fimd"; | 85 | compatible = "samsung,exynos5250-fimd"; |
| 93 | interrupt-parent = <&combiner>; | 86 | interrupt-parent = <&combiner>; |
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index b42e658876e5..56c40783c3eb 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts | |||
| @@ -25,6 +25,10 @@ | |||
| 25 | bootargs = "console=ttySAC2,115200"; | 25 | bootargs = "console=ttySAC2,115200"; |
| 26 | }; | 26 | }; |
| 27 | 27 | ||
| 28 | rtc@101E0000 { | ||
| 29 | status = "okay"; | ||
| 30 | }; | ||
| 31 | |||
| 28 | codec@11000000 { | 32 | codec@11000000 { |
| 29 | samsung,mfc-r = <0x43000000 0x800000>; | 33 | samsung,mfc-r = <0x43000000 0x800000>; |
| 30 | samsung,mfc-l = <0x51000000 0x800000>; | 34 | samsung,mfc-l = <0x51000000 0x800000>; |
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 3e69837c435c..f76946e97e6a 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts | |||
| @@ -27,6 +27,10 @@ | |||
| 27 | bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; | 27 | bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; |
| 28 | }; | 28 | }; |
| 29 | 29 | ||
| 30 | rtc@101E0000 { | ||
| 31 | status = "okay"; | ||
| 32 | }; | ||
| 33 | |||
| 30 | i2c@12C60000 { | 34 | i2c@12C60000 { |
| 31 | samsung,i2c-sda-delay = <100>; | 35 | samsung,i2c-sda-delay = <100>; |
| 32 | samsung,i2c-max-bus-freq = <20000>; | 36 | samsung,i2c-max-bus-freq = <20000>; |
| @@ -36,6 +40,148 @@ | |||
| 36 | compatible = "samsung,s524ad0xd1"; | 40 | compatible = "samsung,s524ad0xd1"; |
| 37 | reg = <0x50>; | 41 | reg = <0x50>; |
| 38 | }; | 42 | }; |
| 43 | |||
| 44 | max77686@09 { | ||
| 45 | compatible = "maxim,max77686"; | ||
| 46 | reg = <0x09>; | ||
| 47 | |||
| 48 | voltage-regulators { | ||
| 49 | ldo1_reg: LDO1 { | ||
| 50 | regulator-name = "P1.0V_LDO_OUT1"; | ||
| 51 | regulator-min-microvolt = <1000000>; | ||
| 52 | regulator-max-microvolt = <1000000>; | ||
| 53 | regulator-always-on; | ||
| 54 | }; | ||
| 55 | |||
| 56 | ldo2_reg: LDO2 { | ||
| 57 | regulator-name = "P1.2V_LDO_OUT2"; | ||
| 58 | regulator-min-microvolt = <1200000>; | ||
| 59 | regulator-max-microvolt = <1200000>; | ||
| 60 | regulator-always-on; | ||
| 61 | }; | ||
| 62 | |||
| 63 | ldo3_reg: LDO3 { | ||
| 64 | regulator-name = "P1.8V_LDO_OUT3"; | ||
| 65 | regulator-min-microvolt = <1800000>; | ||
| 66 | regulator-max-microvolt = <1800000>; | ||
| 67 | regulator-always-on; | ||
| 68 | }; | ||
| 69 | |||
| 70 | ldo4_reg: LDO4 { | ||
| 71 | regulator-name = "P2.8V_LDO_OUT4"; | ||
| 72 | regulator-min-microvolt = <2800000>; | ||
| 73 | regulator-max-microvolt = <2800000>; | ||
| 74 | }; | ||
| 75 | |||
| 76 | ldo5_reg: LDO5 { | ||
| 77 | regulator-name = "P1.8V_LDO_OUT5"; | ||
| 78 | regulator-min-microvolt = <1800000>; | ||
| 79 | regulator-max-microvolt = <1800000>; | ||
| 80 | }; | ||
| 81 | |||
| 82 | ldo6_reg: LDO6 { | ||
| 83 | regulator-name = "P1.1V_LDO_OUT6"; | ||
| 84 | regulator-min-microvolt = <1100000>; | ||
| 85 | regulator-max-microvolt = <1100000>; | ||
| 86 | regulator-always-on; | ||
| 87 | }; | ||
| 88 | |||
| 89 | ldo7_reg: LDO7 { | ||
| 90 | regulator-name = "P1.1V_LDO_OUT7"; | ||
| 91 | regulator-min-microvolt = <1100000>; | ||
| 92 | regulator-max-microvolt = <1100000>; | ||
| 93 | regulator-always-on; | ||
| 94 | }; | ||
| 95 | |||
| 96 | ldo8_reg: LDO8 { | ||
| 97 | regulator-name = "P1.0V_LDO_OUT8"; | ||
| 98 | regulator-min-microvolt = <1000000>; | ||
| 99 | regulator-max-microvolt = <1000000>; | ||
| 100 | }; | ||
| 101 | |||
| 102 | ldo10_reg: LDO10 { | ||
| 103 | regulator-name = "P1.8V_LDO_OUT10"; | ||
| 104 | regulator-min-microvolt = <1800000>; | ||
| 105 | regulator-max-microvolt = <1800000>; | ||
| 106 | }; | ||
| 107 | |||
| 108 | ldo11_reg: LDO11 { | ||
| 109 | regulator-name = "P1.8V_LDO_OUT11"; | ||
| 110 | regulator-min-microvolt = <1800000>; | ||
| 111 | regulator-max-microvolt = <1800000>; | ||
| 112 | }; | ||
| 113 | |||
| 114 | ldo12_reg: LDO12 { | ||
| 115 | regulator-name = "P3.0V_LDO_OUT12"; | ||
| 116 | regulator-min-microvolt = <3000000>; | ||
| 117 | regulator-max-microvolt = <3000000>; | ||
| 118 | }; | ||
| 119 | |||
| 120 | ldo13_reg: LDO13 { | ||
| 121 | regulator-name = "P1.8V_LDO_OUT13"; | ||
| 122 | regulator-min-microvolt = <1800000>; | ||
| 123 | regulator-max-microvolt = <1800000>; | ||
| 124 | }; | ||
| 125 | |||
| 126 | ldo14_reg: LDO14 { | ||
| 127 | regulator-name = "P1.8V_LDO_OUT14"; | ||
| 128 | regulator-min-microvolt = <1800000>; | ||
| 129 | regulator-max-microvolt = <1800000>; | ||
| 130 | }; | ||
| 131 | |||
| 132 | ldo15_reg: LDO15 { | ||
| 133 | regulator-name = "P1.0V_LDO_OUT15"; | ||
| 134 | regulator-min-microvolt = <1000000>; | ||
| 135 | regulator-max-microvolt = <1000000>; | ||
| 136 | }; | ||
| 137 | |||
| 138 | ldo16_reg: LDO16 { | ||
| 139 | regulator-name = "P1.8V_LDO_OUT16"; | ||
| 140 | regulator-min-microvolt = <1800000>; | ||
| 141 | regulator-max-microvolt = <1800000>; | ||
| 142 | }; | ||
| 143 | |||
| 144 | buck1_reg: BUCK1 { | ||
| 145 | regulator-name = "vdd_mif"; | ||
| 146 | regulator-min-microvolt = <950000>; | ||
| 147 | regulator-max-microvolt = <1300000>; | ||
| 148 | regulator-always-on; | ||
| 149 | regulator-boot-on; | ||
| 150 | }; | ||
| 151 | |||
| 152 | buck2_reg: BUCK2 { | ||
| 153 | regulator-name = "vdd_arm"; | ||
| 154 | regulator-min-microvolt = <850000>; | ||
| 155 | regulator-max-microvolt = <1350000>; | ||
| 156 | regulator-always-on; | ||
| 157 | regulator-boot-on; | ||
| 158 | }; | ||
| 159 | |||
| 160 | buck3_reg: BUCK3 { | ||
| 161 | regulator-name = "vdd_int"; | ||
| 162 | regulator-min-microvolt = <900000>; | ||
| 163 | regulator-max-microvolt = <1200000>; | ||
| 164 | regulator-always-on; | ||
| 165 | regulator-boot-on; | ||
| 166 | }; | ||
| 167 | |||
| 168 | buck4_reg: BUCK4 { | ||
| 169 | regulator-name = "vdd_g3d"; | ||
| 170 | regulator-min-microvolt = <850000>; | ||
| 171 | regulator-max-microvolt = <1300000>; | ||
| 172 | regulator-always-on; | ||
| 173 | regulator-boot-on; | ||
| 174 | }; | ||
| 175 | |||
| 176 | buck5_reg: BUCK5 { | ||
| 177 | regulator-name = "P1.8V_BUCK_OUT5"; | ||
| 178 | regulator-min-microvolt = <1800000>; | ||
| 179 | regulator-max-microvolt = <1800000>; | ||
| 180 | regulator-always-on; | ||
| 181 | regulator-boot-on; | ||
| 182 | }; | ||
| 183 | }; | ||
| 184 | }; | ||
| 39 | }; | 185 | }; |
| 40 | 186 | ||
| 41 | vdd: fixed-regulator@0 { | 187 | vdd: fixed-regulator@0 { |
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index 7e45eea2d78f..b13bf499f5e2 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts | |||
| @@ -20,6 +20,10 @@ | |||
| 20 | i2c104 = &i2c_104; | 20 | i2c104 = &i2c_104; |
| 21 | }; | 21 | }; |
| 22 | 22 | ||
| 23 | rtc@101E0000 { | ||
| 24 | status = "okay"; | ||
| 25 | }; | ||
| 26 | |||
| 23 | pinctrl@11400000 { | 27 | pinctrl@11400000 { |
| 24 | sd3_clk: sd3-clk { | 28 | sd3_clk: sd3-clk { |
| 25 | samsung,pin-drv = <0>; | 29 | samsung,pin-drv = <0>; |
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index b7dec41e32af..987cfbe9634b 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | * published by the Free Software Foundation. | 17 | * published by the Free Software Foundation. |
| 18 | */ | 18 | */ |
| 19 | 19 | ||
| 20 | #include <dt-bindings/clock/exynos5250.h> | ||
| 20 | #include "exynos5.dtsi" | 21 | #include "exynos5.dtsi" |
| 21 | #include "exynos5250-pinctrl.dtsi" | 22 | #include "exynos5250-pinctrl.dtsi" |
| 22 | 23 | ||
| @@ -90,7 +91,8 @@ | |||
| 90 | compatible = "samsung,exynos5250-audss-clock"; | 91 | compatible = "samsung,exynos5250-audss-clock"; |
| 91 | reg = <0x03810000 0x0C>; | 92 | reg = <0x03810000 0x0C>; |
| 92 | #clock-cells = <1>; | 93 | #clock-cells = <1>; |
| 93 | clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>; | 94 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, |
| 95 | <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>; | ||
| 94 | clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; | 96 | clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; |
| 95 | }; | 97 | }; |
| 96 | 98 | ||
| @@ -115,7 +117,7 @@ | |||
| 115 | interrupt-parent = <&mct_map>; | 117 | interrupt-parent = <&mct_map>; |
| 116 | interrupts = <0 0>, <1 0>, <2 0>, <3 0>, | 118 | interrupts = <0 0>, <1 0>, <2 0>, <3 0>, |
| 117 | <4 0>, <5 0>; | 119 | <4 0>, <5 0>; |
| 118 | clocks = <&clock 1>, <&clock 335>; | 120 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; |
| 119 | clock-names = "fin_pll", "mct"; | 121 | clock-names = "fin_pll", "mct"; |
| 120 | 122 | ||
| 121 | mct_map: mct-map { | 123 | mct_map: mct-map { |
| @@ -167,16 +169,25 @@ | |||
| 167 | interrupts = <0 47 0>; | 169 | interrupts = <0 47 0>; |
| 168 | }; | 170 | }; |
| 169 | 171 | ||
| 170 | watchdog { | 172 | pmu_system_controller: system-controller@10040000 { |
| 171 | clocks = <&clock 336>; | 173 | compatible = "samsung,exynos5250-pmu", "syscon"; |
| 174 | reg = <0x10040000 0x5000>; | ||
| 175 | }; | ||
| 176 | |||
| 177 | watchdog@101D0000 { | ||
| 178 | compatible = "samsung,exynos5250-wdt"; | ||
| 179 | reg = <0x101D0000 0x100>; | ||
| 180 | interrupts = <0 42 0>; | ||
| 181 | clocks = <&clock CLK_WDT>; | ||
| 172 | clock-names = "watchdog"; | 182 | clock-names = "watchdog"; |
| 183 | samsung,syscon-phandle = <&pmu_system_controller>; | ||
| 173 | }; | 184 | }; |
| 174 | 185 | ||
| 175 | g2d@10850000 { | 186 | g2d@10850000 { |
| 176 | compatible = "samsung,exynos5250-g2d"; | 187 | compatible = "samsung,exynos5250-g2d"; |
| 177 | reg = <0x10850000 0x1000>; | 188 | reg = <0x10850000 0x1000>; |
| 178 | interrupts = <0 91 0>; | 189 | interrupts = <0 91 0>; |
| 179 | clocks = <&clock 345>; | 190 | clocks = <&clock CLK_G2D>; |
| 180 | clock-names = "fimg2d"; | 191 | clock-names = "fimg2d"; |
| 181 | }; | 192 | }; |
| 182 | 193 | ||
| @@ -185,41 +196,41 @@ | |||
| 185 | reg = <0x11000000 0x10000>; | 196 | reg = <0x11000000 0x10000>; |
| 186 | interrupts = <0 96 0>; | 197 | interrupts = <0 96 0>; |
| 187 | samsung,power-domain = <&pd_mfc>; | 198 | samsung,power-domain = <&pd_mfc>; |
| 188 | clocks = <&clock 266>; | 199 | clocks = <&clock CLK_MFC>; |
| 189 | clock-names = "mfc"; | 200 | clock-names = "mfc"; |
| 190 | }; | 201 | }; |
| 191 | 202 | ||
| 192 | rtc@101E0000 { | 203 | rtc@101E0000 { |
| 193 | clocks = <&clock 337>; | 204 | clocks = <&clock CLK_RTC>; |
| 194 | clock-names = "rtc"; | 205 | clock-names = "rtc"; |
| 195 | status = "okay"; | 206 | status = "disabled"; |
| 196 | }; | 207 | }; |
| 197 | 208 | ||
| 198 | tmu@10060000 { | 209 | tmu@10060000 { |
| 199 | compatible = "samsung,exynos5250-tmu"; | 210 | compatible = "samsung,exynos5250-tmu"; |
| 200 | reg = <0x10060000 0x100>; | 211 | reg = <0x10060000 0x100>; |
| 201 | interrupts = <0 65 0>; | 212 | interrupts = <0 65 0>; |
| 202 | clocks = <&clock 338>; | 213 | clocks = <&clock CLK_TMU>; |
| 203 | clock-names = "tmu_apbif"; | 214 | clock-names = "tmu_apbif"; |
| 204 | }; | 215 | }; |
| 205 | 216 | ||
| 206 | serial@12C00000 { | 217 | serial@12C00000 { |
| 207 | clocks = <&clock 289>, <&clock 146>; | 218 | clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; |
| 208 | clock-names = "uart", "clk_uart_baud0"; | 219 | clock-names = "uart", "clk_uart_baud0"; |
| 209 | }; | 220 | }; |
| 210 | 221 | ||
| 211 | serial@12C10000 { | 222 | serial@12C10000 { |
| 212 | clocks = <&clock 290>, <&clock 147>; | 223 | clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; |
| 213 | clock-names = "uart", "clk_uart_baud0"; | 224 | clock-names = "uart", "clk_uart_baud0"; |
| 214 | }; | 225 | }; |
| 215 | 226 | ||
| 216 | serial@12C20000 { | 227 | serial@12C20000 { |
| 217 | clocks = <&clock 291>, <&clock 148>; | 228 | clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; |
| 218 | clock-names = "uart", "clk_uart_baud0"; | 229 | clock-names = "uart", "clk_uart_baud0"; |
| 219 | }; | 230 | }; |
| 220 | 231 | ||
| 221 | serial@12C30000 { | 232 | serial@12C30000 { |
| 222 | clocks = <&clock 292>, <&clock 149>; | 233 | clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; |
| 223 | clock-names = "uart", "clk_uart_baud0"; | 234 | clock-names = "uart", "clk_uart_baud0"; |
| 224 | }; | 235 | }; |
| 225 | 236 | ||
| @@ -227,7 +238,7 @@ | |||
| 227 | compatible = "samsung,exynos5-sata-ahci"; | 238 | compatible = "samsung,exynos5-sata-ahci"; |
| 228 | reg = <0x122F0000 0x1ff>; | 239 | reg = <0x122F0000 0x1ff>; |
| 229 | interrupts = <0 115 0>; | 240 | interrupts = <0 115 0>; |
| 230 | clocks = <&clock 277>, <&clock 143>; | 241 | clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; |
| 231 | clock-names = "sata", "sclk_sata"; | 242 | clock-names = "sata", "sclk_sata"; |
| 232 | }; | 243 | }; |
| 233 | 244 | ||
| @@ -242,7 +253,7 @@ | |||
| 242 | interrupts = <0 56 0>; | 253 | interrupts = <0 56 0>; |
| 243 | #address-cells = <1>; | 254 | #address-cells = <1>; |
| 244 | #size-cells = <0>; | 255 | #size-cells = <0>; |
| 245 | clocks = <&clock 294>; | 256 | clocks = <&clock CLK_I2C0>; |
| 246 | clock-names = "i2c"; | 257 | clock-names = "i2c"; |
| 247 | pinctrl-names = "default"; | 258 | pinctrl-names = "default"; |
| 248 | pinctrl-0 = <&i2c0_bus>; | 259 | pinctrl-0 = <&i2c0_bus>; |
| @@ -255,7 +266,7 @@ | |||
| 255 | interrupts = <0 57 0>; | 266 | interrupts = <0 57 0>; |
| 256 | #address-cells = <1>; | 267 | #address-cells = <1>; |
| 257 | #size-cells = <0>; | 268 | #size-cells = <0>; |
| 258 | clocks = <&clock 295>; | 269 | clocks = <&clock CLK_I2C1>; |
| 259 | clock-names = "i2c"; | 270 | clock-names = "i2c"; |
| 260 | pinctrl-names = "default"; | 271 | pinctrl-names = "default"; |
| 261 | pinctrl-0 = <&i2c1_bus>; | 272 | pinctrl-0 = <&i2c1_bus>; |
| @@ -268,7 +279,7 @@ | |||
| 268 | interrupts = <0 58 0>; | 279 | interrupts = <0 58 0>; |
| 269 | #address-cells = <1>; | 280 | #address-cells = <1>; |
| 270 | #size-cells = <0>; | 281 | #size-cells = <0>; |
| 271 | clocks = <&clock 296>; | 282 | clocks = <&clock CLK_I2C2>; |
| 272 | clock-names = "i2c"; | 283 | clock-names = "i2c"; |
| 273 | pinctrl-names = "default"; | 284 | pinctrl-names = "default"; |
| 274 | pinctrl-0 = <&i2c2_bus>; | 285 | pinctrl-0 = <&i2c2_bus>; |
| @@ -281,7 +292,7 @@ | |||
| 281 | interrupts = <0 59 0>; | 292 | interrupts = <0 59 0>; |
| 282 | #address-cells = <1>; | 293 | #address-cells = <1>; |
| 283 | #size-cells = <0>; | 294 | #size-cells = <0>; |
| 284 | clocks = <&clock 297>; | 295 | clocks = <&clock CLK_I2C3>; |
| 285 | clock-names = "i2c"; | 296 | clock-names = "i2c"; |
| 286 | pinctrl-names = "default"; | 297 | pinctrl-names = "default"; |
| 287 | pinctrl-0 = <&i2c3_bus>; | 298 | pinctrl-0 = <&i2c3_bus>; |
| @@ -294,7 +305,7 @@ | |||
| 294 | interrupts = <0 60 0>; | 305 | interrupts = <0 60 0>; |
| 295 | #address-cells = <1>; | 306 | #address-cells = <1>; |
| 296 | #size-cells = <0>; | 307 | #size-cells = <0>; |
| 297 | clocks = <&clock 298>; | 308 | clocks = <&clock CLK_I2C4>; |
| 298 | clock-names = "i2c"; | 309 | clock-names = "i2c"; |
| 299 | pinctrl-names = "default"; | 310 | pinctrl-names = "default"; |
| 300 | pinctrl-0 = <&i2c4_bus>; | 311 | pinctrl-0 = <&i2c4_bus>; |
| @@ -307,7 +318,7 @@ | |||
| 307 | interrupts = <0 61 0>; | 318 | interrupts = <0 61 0>; |
| 308 | #address-cells = <1>; | 319 | #address-cells = <1>; |
| 309 | #size-cells = <0>; | 320 | #size-cells = <0>; |
| 310 | clocks = <&clock 299>; | 321 | clocks = <&clock CLK_I2C5>; |
| 311 | clock-names = "i2c"; | 322 | clock-names = "i2c"; |
| 312 | pinctrl-names = "default"; | 323 | pinctrl-names = "default"; |
| 313 | pinctrl-0 = <&i2c5_bus>; | 324 | pinctrl-0 = <&i2c5_bus>; |
| @@ -320,7 +331,7 @@ | |||
| 320 | interrupts = <0 62 0>; | 331 | interrupts = <0 62 0>; |
| 321 | #address-cells = <1>; | 332 | #address-cells = <1>; |
| 322 | #size-cells = <0>; | 333 | #size-cells = <0>; |
| 323 | clocks = <&clock 300>; | 334 | clocks = <&clock CLK_I2C6>; |
| 324 | clock-names = "i2c"; | 335 | clock-names = "i2c"; |
| 325 | pinctrl-names = "default"; | 336 | pinctrl-names = "default"; |
| 326 | pinctrl-0 = <&i2c6_bus>; | 337 | pinctrl-0 = <&i2c6_bus>; |
| @@ -333,7 +344,7 @@ | |||
| 333 | interrupts = <0 63 0>; | 344 | interrupts = <0 63 0>; |
| 334 | #address-cells = <1>; | 345 | #address-cells = <1>; |
| 335 | #size-cells = <0>; | 346 | #size-cells = <0>; |
| 336 | clocks = <&clock 301>; | 347 | clocks = <&clock CLK_I2C7>; |
| 337 | clock-names = "i2c"; | 348 | clock-names = "i2c"; |
| 338 | pinctrl-names = "default"; | 349 | pinctrl-names = "default"; |
| 339 | pinctrl-0 = <&i2c7_bus>; | 350 | pinctrl-0 = <&i2c7_bus>; |
| @@ -346,7 +357,7 @@ | |||
| 346 | interrupts = <0 64 0>; | 357 | interrupts = <0 64 0>; |
| 347 | #address-cells = <1>; | 358 | #address-cells = <1>; |
| 348 | #size-cells = <0>; | 359 | #size-cells = <0>; |
| 349 | clocks = <&clock 302>; | 360 | clocks = <&clock CLK_I2C_HDMI>; |
| 350 | clock-names = "i2c"; | 361 | clock-names = "i2c"; |
| 351 | status = "disabled"; | 362 | status = "disabled"; |
| 352 | }; | 363 | }; |
| @@ -356,7 +367,7 @@ | |||
| 356 | reg = <0x121D0000 0x100>; | 367 | reg = <0x121D0000 0x100>; |
| 357 | #address-cells = <1>; | 368 | #address-cells = <1>; |
| 358 | #size-cells = <0>; | 369 | #size-cells = <0>; |
| 359 | clocks = <&clock 288>; | 370 | clocks = <&clock CLK_SATA_PHYI2C>; |
| 360 | clock-names = "i2c"; | 371 | clock-names = "i2c"; |
| 361 | status = "disabled"; | 372 | status = "disabled"; |
| 362 | }; | 373 | }; |
| @@ -371,7 +382,7 @@ | |||
| 371 | dma-names = "tx", "rx"; | 382 | dma-names = "tx", "rx"; |
| 372 | #address-cells = <1>; | 383 | #address-cells = <1>; |
| 373 | #size-cells = <0>; | 384 | #size-cells = <0>; |
| 374 | clocks = <&clock 304>, <&clock 154>; | 385 | clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; |
| 375 | clock-names = "spi", "spi_busclk0"; | 386 | clock-names = "spi", "spi_busclk0"; |
| 376 | pinctrl-names = "default"; | 387 | pinctrl-names = "default"; |
| 377 | pinctrl-0 = <&spi0_bus>; | 388 | pinctrl-0 = <&spi0_bus>; |
| @@ -387,7 +398,7 @@ | |||
| 387 | dma-names = "tx", "rx"; | 398 | dma-names = "tx", "rx"; |
| 388 | #address-cells = <1>; | 399 | #address-cells = <1>; |
| 389 | #size-cells = <0>; | 400 | #size-cells = <0>; |
| 390 | clocks = <&clock 305>, <&clock 155>; | 401 | clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; |
| 391 | clock-names = "spi", "spi_busclk0"; | 402 | clock-names = "spi", "spi_busclk0"; |
| 392 | pinctrl-names = "default"; | 403 | pinctrl-names = "default"; |
| 393 | pinctrl-0 = <&spi1_bus>; | 404 | pinctrl-0 = <&spi1_bus>; |
| @@ -403,7 +414,7 @@ | |||
| 403 | dma-names = "tx", "rx"; | 414 | dma-names = "tx", "rx"; |
| 404 | #address-cells = <1>; | 415 | #address-cells = <1>; |
| 405 | #size-cells = <0>; | 416 | #size-cells = <0>; |
| 406 | clocks = <&clock 306>, <&clock 156>; | 417 | clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; |
| 407 | clock-names = "spi", "spi_busclk0"; | 418 | clock-names = "spi", "spi_busclk0"; |
| 408 | pinctrl-names = "default"; | 419 | pinctrl-names = "default"; |
| 409 | pinctrl-0 = <&spi2_bus>; | 420 | pinctrl-0 = <&spi2_bus>; |
| @@ -415,7 +426,7 @@ | |||
| 415 | #address-cells = <1>; | 426 | #address-cells = <1>; |
| 416 | #size-cells = <0>; | 427 | #size-cells = <0>; |
| 417 | reg = <0x12200000 0x1000>; | 428 | reg = <0x12200000 0x1000>; |
| 418 | clocks = <&clock 280>, <&clock 139>; | 429 | clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; |
| 419 | clock-names = "biu", "ciu"; | 430 | clock-names = "biu", "ciu"; |
| 420 | fifo-depth = <0x80>; | 431 | fifo-depth = <0x80>; |
| 421 | status = "disabled"; | 432 | status = "disabled"; |
| @@ -427,7 +438,7 @@ | |||
| 427 | #address-cells = <1>; | 438 | #address-cells = <1>; |
| 428 | #size-cells = <0>; | 439 | #size-cells = <0>; |
| 429 | reg = <0x12210000 0x1000>; | 440 | reg = <0x12210000 0x1000>; |
| 430 | clocks = <&clock 281>, <&clock 140>; | 441 | clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; |
| 431 | clock-names = "biu", "ciu"; | 442 | clock-names = "biu", "ciu"; |
| 432 | fifo-depth = <0x80>; | 443 | fifo-depth = <0x80>; |
| 433 | status = "disabled"; | 444 | status = "disabled"; |
| @@ -439,7 +450,7 @@ | |||
| 439 | #address-cells = <1>; | 450 | #address-cells = <1>; |
| 440 | #size-cells = <0>; | 451 | #size-cells = <0>; |
| 441 | reg = <0x12220000 0x1000>; | 452 | reg = <0x12220000 0x1000>; |
| 442 | clocks = <&clock 282>, <&clock 141>; | 453 | clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; |
| 443 | clock-names = "biu", "ciu"; | 454 | clock-names = "biu", "ciu"; |
| 444 | fifo-depth = <0x80>; | 455 | fifo-depth = <0x80>; |
| 445 | status = "disabled"; | 456 | status = "disabled"; |
| @@ -451,7 +462,7 @@ | |||
| 451 | interrupts = <0 78 0>; | 462 | interrupts = <0 78 0>; |
| 452 | #address-cells = <1>; | 463 | #address-cells = <1>; |
| 453 | #size-cells = <0>; | 464 | #size-cells = <0>; |
| 454 | clocks = <&clock 283>, <&clock 142>; | 465 | clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; |
| 455 | clock-names = "biu", "ciu"; | 466 | clock-names = "biu", "ciu"; |
| 456 | fifo-depth = <0x80>; | 467 | fifo-depth = <0x80>; |
| 457 | status = "disabled"; | 468 | status = "disabled"; |
| @@ -481,7 +492,7 @@ | |||
| 481 | dmas = <&pdma1 12 | 492 | dmas = <&pdma1 12 |
| 482 | &pdma1 11>; | 493 | &pdma1 11>; |
| 483 | dma-names = "tx", "rx"; | 494 | dma-names = "tx", "rx"; |
| 484 | clocks = <&clock 307>, <&clock 157>; | 495 | clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>; |
| 485 | clock-names = "iis", "i2s_opclk0"; | 496 | clock-names = "iis", "i2s_opclk0"; |
| 486 | pinctrl-names = "default"; | 497 | pinctrl-names = "default"; |
| 487 | pinctrl-0 = <&i2s1_bus>; | 498 | pinctrl-0 = <&i2s1_bus>; |
| @@ -494,7 +505,7 @@ | |||
| 494 | dmas = <&pdma0 12 | 505 | dmas = <&pdma0 12 |
| 495 | &pdma0 11>; | 506 | &pdma0 11>; |
| 496 | dma-names = "tx", "rx"; | 507 | dma-names = "tx", "rx"; |
| 497 | clocks = <&clock 308>, <&clock 158>; | 508 | clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>; |
| 498 | clock-names = "iis", "i2s_opclk0"; | 509 | clock-names = "iis", "i2s_opclk0"; |
| 499 | pinctrl-names = "default"; | 510 | pinctrl-names = "default"; |
| 500 | pinctrl-0 = <&i2s2_bus>; | 511 | pinctrl-0 = <&i2s2_bus>; |
| @@ -502,7 +513,7 @@ | |||
| 502 | 513 | ||
| 503 | usb@12000000 { | 514 | usb@12000000 { |
| 504 | compatible = "samsung,exynos5250-dwusb3"; | 515 | compatible = "samsung,exynos5250-dwusb3"; |
| 505 | clocks = <&clock 286>; | 516 | clocks = <&clock CLK_USB3>; |
| 506 | clock-names = "usbdrd30"; | 517 | clock-names = "usbdrd30"; |
| 507 | #address-cells = <1>; | 518 | #address-cells = <1>; |
| 508 | #size-cells = <1>; | 519 | #size-cells = <1>; |
| @@ -519,7 +530,7 @@ | |||
| 519 | usb3_phy: usbphy@12100000 { | 530 | usb3_phy: usbphy@12100000 { |
| 520 | compatible = "samsung,exynos5250-usb3phy"; | 531 | compatible = "samsung,exynos5250-usb3phy"; |
| 521 | reg = <0x12100000 0x100>; | 532 | reg = <0x12100000 0x100>; |
| 522 | clocks = <&clock 1>, <&clock 286>; | 533 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB3>; |
| 523 | clock-names = "ext_xtal", "usbdrd30"; | 534 | clock-names = "ext_xtal", "usbdrd30"; |
| 524 | #address-cells = <1>; | 535 | #address-cells = <1>; |
| 525 | #size-cells = <1>; | 536 | #size-cells = <1>; |
| @@ -535,7 +546,7 @@ | |||
| 535 | reg = <0x12110000 0x100>; | 546 | reg = <0x12110000 0x100>; |
| 536 | interrupts = <0 71 0>; | 547 | interrupts = <0 71 0>; |
| 537 | 548 | ||
| 538 | clocks = <&clock 285>; | 549 | clocks = <&clock CLK_USB2>; |
| 539 | clock-names = "usbhost"; | 550 | clock-names = "usbhost"; |
| 540 | }; | 551 | }; |
| 541 | 552 | ||
| @@ -544,14 +555,14 @@ | |||
| 544 | reg = <0x12120000 0x100>; | 555 | reg = <0x12120000 0x100>; |
| 545 | interrupts = <0 71 0>; | 556 | interrupts = <0 71 0>; |
| 546 | 557 | ||
| 547 | clocks = <&clock 285>; | 558 | clocks = <&clock CLK_USB2>; |
| 548 | clock-names = "usbhost"; | 559 | clock-names = "usbhost"; |
| 549 | }; | 560 | }; |
| 550 | 561 | ||
| 551 | usb2_phy: usbphy@12130000 { | 562 | usb2_phy: usbphy@12130000 { |
| 552 | compatible = "samsung,exynos5250-usb2phy"; | 563 | compatible = "samsung,exynos5250-usb2phy"; |
| 553 | reg = <0x12130000 0x100>; | 564 | reg = <0x12130000 0x100>; |
| 554 | clocks = <&clock 1>, <&clock 285>; | 565 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB2>; |
| 555 | clock-names = "ext_xtal", "usbhost"; | 566 | clock-names = "ext_xtal", "usbhost"; |
| 556 | #address-cells = <1>; | 567 | #address-cells = <1>; |
| 557 | #size-cells = <1>; | 568 | #size-cells = <1>; |
| @@ -568,7 +579,7 @@ | |||
| 568 | reg = <0x12dd0000 0x100>; | 579 | reg = <0x12dd0000 0x100>; |
| 569 | samsung,pwm-outputs = <0>, <1>, <2>, <3>; | 580 | samsung,pwm-outputs = <0>, <1>, <2>, <3>; |
| 570 | #pwm-cells = <3>; | 581 | #pwm-cells = <3>; |
| 571 | clocks = <&clock 311>; | 582 | clocks = <&clock CLK_PWM>; |
| 572 | clock-names = "timers"; | 583 | clock-names = "timers"; |
| 573 | }; | 584 | }; |
| 574 | 585 | ||
| @@ -583,7 +594,7 @@ | |||
| 583 | compatible = "arm,pl330", "arm,primecell"; | 594 | compatible = "arm,pl330", "arm,primecell"; |
| 584 | reg = <0x121A0000 0x1000>; | 595 | reg = <0x121A0000 0x1000>; |
| 585 | interrupts = <0 34 0>; | 596 | interrupts = <0 34 0>; |
| 586 | clocks = <&clock 275>; | 597 | clocks = <&clock CLK_PDMA0>; |
| 587 | clock-names = "apb_pclk"; | 598 | clock-names = "apb_pclk"; |
| 588 | #dma-cells = <1>; | 599 | #dma-cells = <1>; |
| 589 | #dma-channels = <8>; | 600 | #dma-channels = <8>; |
| @@ -594,7 +605,7 @@ | |||
| 594 | compatible = "arm,pl330", "arm,primecell"; | 605 | compatible = "arm,pl330", "arm,primecell"; |
| 595 | reg = <0x121B0000 0x1000>; | 606 | reg = <0x121B0000 0x1000>; |
| 596 | interrupts = <0 35 0>; | 607 | interrupts = <0 35 0>; |
| 597 | clocks = <&clock 276>; | 608 | clocks = <&clock CLK_PDMA1>; |
| 598 | clock-names = "apb_pclk"; | 609 | clock-names = "apb_pclk"; |
| 599 | #dma-cells = <1>; | 610 | #dma-cells = <1>; |
| 600 | #dma-channels = <8>; | 611 | #dma-channels = <8>; |
| @@ -605,7 +616,7 @@ | |||
| 605 | compatible = "arm,pl330", "arm,primecell"; | 616 | compatible = "arm,pl330", "arm,primecell"; |
| 606 | reg = <0x10800000 0x1000>; | 617 | reg = <0x10800000 0x1000>; |
| 607 | interrupts = <0 33 0>; | 618 | interrupts = <0 33 0>; |
| 608 | clocks = <&clock 346>; | 619 | clocks = <&clock CLK_MDMA0>; |
| 609 | clock-names = "apb_pclk"; | 620 | clock-names = "apb_pclk"; |
| 610 | #dma-cells = <1>; | 621 | #dma-cells = <1>; |
| 611 | #dma-channels = <8>; | 622 | #dma-channels = <8>; |
| @@ -616,7 +627,7 @@ | |||
| 616 | compatible = "arm,pl330", "arm,primecell"; | 627 | compatible = "arm,pl330", "arm,primecell"; |
| 617 | reg = <0x11C10000 0x1000>; | 628 | reg = <0x11C10000 0x1000>; |
| 618 | interrupts = <0 124 0>; | 629 | interrupts = <0 124 0>; |
| 619 | clocks = <&clock 271>; | 630 | clocks = <&clock CLK_MDMA1>; |
| 620 | clock-names = "apb_pclk"; | 631 | clock-names = "apb_pclk"; |
| 621 | #dma-cells = <1>; | 632 | #dma-cells = <1>; |
| 622 | #dma-channels = <8>; | 633 | #dma-channels = <8>; |
| @@ -629,7 +640,7 @@ | |||
| 629 | reg = <0x13e00000 0x1000>; | 640 | reg = <0x13e00000 0x1000>; |
| 630 | interrupts = <0 85 0>; | 641 | interrupts = <0 85 0>; |
| 631 | samsung,power-domain = <&pd_gsc>; | 642 | samsung,power-domain = <&pd_gsc>; |
| 632 | clocks = <&clock 256>; | 643 | clocks = <&clock CLK_GSCL0>; |
| 633 | clock-names = "gscl"; | 644 | clock-names = "gscl"; |
| 634 | }; | 645 | }; |
| 635 | 646 | ||
| @@ -638,7 +649,7 @@ | |||
| 638 | reg = <0x13e10000 0x1000>; | 649 | reg = <0x13e10000 0x1000>; |
| 639 | interrupts = <0 86 0>; | 650 | interrupts = <0 86 0>; |
| 640 | samsung,power-domain = <&pd_gsc>; | 651 | samsung,power-domain = <&pd_gsc>; |
| 641 | clocks = <&clock 257>; | 652 | clocks = <&clock CLK_GSCL1>; |
| 642 | clock-names = "gscl"; | 653 | clock-names = "gscl"; |
| 643 | }; | 654 | }; |
| 644 | 655 | ||
| @@ -647,7 +658,7 @@ | |||
| 647 | reg = <0x13e20000 0x1000>; | 658 | reg = <0x13e20000 0x1000>; |
| 648 | interrupts = <0 87 0>; | 659 | interrupts = <0 87 0>; |
| 649 | samsung,power-domain = <&pd_gsc>; | 660 | samsung,power-domain = <&pd_gsc>; |
| 650 | clocks = <&clock 258>; | 661 | clocks = <&clock CLK_GSCL2>; |
| 651 | clock-names = "gscl"; | 662 | clock-names = "gscl"; |
| 652 | }; | 663 | }; |
| 653 | 664 | ||
| @@ -656,7 +667,7 @@ | |||
| 656 | reg = <0x13e30000 0x1000>; | 667 | reg = <0x13e30000 0x1000>; |
| 657 | interrupts = <0 88 0>; | 668 | interrupts = <0 88 0>; |
| 658 | samsung,power-domain = <&pd_gsc>; | 669 | samsung,power-domain = <&pd_gsc>; |
| 659 | clocks = <&clock 259>; | 670 | clocks = <&clock CLK_GSCL3>; |
| 660 | clock-names = "gscl"; | 671 | clock-names = "gscl"; |
| 661 | }; | 672 | }; |
| 662 | 673 | ||
| @@ -664,8 +675,9 @@ | |||
| 664 | compatible = "samsung,exynos4212-hdmi"; | 675 | compatible = "samsung,exynos4212-hdmi"; |
| 665 | reg = <0x14530000 0x70000>; | 676 | reg = <0x14530000 0x70000>; |
| 666 | interrupts = <0 95 0>; | 677 | interrupts = <0 95 0>; |
| 667 | clocks = <&clock 344>, <&clock 136>, <&clock 137>, | 678 | clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, |
| 668 | <&clock 159>, <&clock 1024>; | 679 | <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, |
| 680 | <&clock CLK_MOUT_HDMI>; | ||
| 669 | clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", | 681 | clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", |
| 670 | "sclk_hdmiphy", "mout_hdmi"; | 682 | "sclk_hdmiphy", "mout_hdmi"; |
| 671 | }; | 683 | }; |
| @@ -674,7 +686,7 @@ | |||
| 674 | compatible = "samsung,exynos5250-mixer"; | 686 | compatible = "samsung,exynos5250-mixer"; |
| 675 | reg = <0x14450000 0x10000>; | 687 | reg = <0x14450000 0x10000>; |
| 676 | interrupts = <0 94 0>; | 688 | interrupts = <0 94 0>; |
| 677 | clocks = <&clock 343>, <&clock 136>; | 689 | clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>; |
| 678 | clock-names = "mixer", "sclk_hdmi"; | 690 | clock-names = "mixer", "sclk_hdmi"; |
| 679 | }; | 691 | }; |
| 680 | 692 | ||
| @@ -685,14 +697,14 @@ | |||
| 685 | }; | 697 | }; |
| 686 | 698 | ||
| 687 | dp-controller@145B0000 { | 699 | dp-controller@145B0000 { |
| 688 | clocks = <&clock 342>; | 700 | clocks = <&clock CLK_DP>; |
| 689 | clock-names = "dp"; | 701 | clock-names = "dp"; |
| 690 | phys = <&dp_phy>; | 702 | phys = <&dp_phy>; |
| 691 | phy-names = "dp"; | 703 | phy-names = "dp"; |
| 692 | }; | 704 | }; |
| 693 | 705 | ||
| 694 | fimd@14400000 { | 706 | fimd@14400000 { |
| 695 | clocks = <&clock 133>, <&clock 339>; | 707 | clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; |
| 696 | clock-names = "sclk_fimd", "fimd"; | 708 | clock-names = "sclk_fimd", "fimd"; |
| 697 | }; | 709 | }; |
| 698 | 710 | ||
| @@ -700,7 +712,7 @@ | |||
| 700 | compatible = "samsung,exynos-adc-v1"; | 712 | compatible = "samsung,exynos-adc-v1"; |
| 701 | reg = <0x12D10000 0x100>, <0x10040718 0x4>; | 713 | reg = <0x12D10000 0x100>, <0x10040718 0x4>; |
| 702 | interrupts = <0 106 0>; | 714 | interrupts = <0 106 0>; |
| 703 | clocks = <&clock 303>; | 715 | clocks = <&clock CLK_ADC>; |
| 704 | clock-names = "adc"; | 716 | clock-names = "adc"; |
| 705 | #io-channel-cells = <1>; | 717 | #io-channel-cells = <1>; |
| 706 | io-channel-ranges; | 718 | io-channel-ranges; |
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index 7340745ff979..f509e8fc290f 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts | |||
| @@ -11,6 +11,8 @@ | |||
| 11 | 11 | ||
| 12 | /dts-v1/; | 12 | /dts-v1/; |
| 13 | #include "exynos5420.dtsi" | 13 | #include "exynos5420.dtsi" |
| 14 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 15 | #include <dt-bindings/input/input.h> | ||
| 14 | 16 | ||
| 15 | / { | 17 | / { |
| 16 | model = "Insignal Arndale Octa evaluation board based on EXYNOS5420"; | 18 | model = "Insignal Arndale Octa evaluation board based on EXYNOS5420"; |
| @@ -31,6 +33,10 @@ | |||
| 31 | }; | 33 | }; |
| 32 | }; | 34 | }; |
| 33 | 35 | ||
| 36 | rtc@101E0000 { | ||
| 37 | status = "okay"; | ||
| 38 | }; | ||
| 39 | |||
| 34 | mmc@12200000 { | 40 | mmc@12200000 { |
| 35 | status = "okay"; | 41 | status = "okay"; |
| 36 | broken-cd; | 42 | broken-cd; |
| @@ -41,6 +47,7 @@ | |||
| 41 | samsung,dw-mshc-ddr-timing = <0 2>; | 47 | samsung,dw-mshc-ddr-timing = <0 2>; |
| 42 | pinctrl-names = "default"; | 48 | pinctrl-names = "default"; |
| 43 | pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; | 49 | pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; |
| 50 | vmmc-supply = <&ldo10_reg>; | ||
| 44 | 51 | ||
| 45 | slot@0 { | 52 | slot@0 { |
| 46 | reg = <0>; | 53 | reg = <0>; |
| @@ -57,10 +64,301 @@ | |||
| 57 | samsung,dw-mshc-ddr-timing = <1 2>; | 64 | samsung,dw-mshc-ddr-timing = <1 2>; |
| 58 | pinctrl-names = "default"; | 65 | pinctrl-names = "default"; |
| 59 | pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; | 66 | pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; |
| 67 | vmmc-supply = <&ldo10_reg>; | ||
| 60 | 68 | ||
| 61 | slot@0 { | 69 | slot@0 { |
| 62 | reg = <0>; | 70 | reg = <0>; |
| 63 | bus-width = <4>; | 71 | bus-width = <4>; |
| 64 | }; | 72 | }; |
| 65 | }; | 73 | }; |
| 74 | |||
| 75 | hsi2c_4: i2c@12CA0000 { | ||
| 76 | status = "okay"; | ||
| 77 | |||
| 78 | s2mps11_pmic@66 { | ||
| 79 | compatible = "samsung,s2mps11-pmic"; | ||
| 80 | reg = <0x66>; | ||
| 81 | s2mps11,buck2-ramp-delay = <12>; | ||
| 82 | s2mps11,buck34-ramp-delay = <12>; | ||
| 83 | s2mps11,buck16-ramp-delay = <12>; | ||
| 84 | s2mps11,buck6-ramp-enable = <1>; | ||
| 85 | s2mps11,buck2-ramp-enable = <1>; | ||
| 86 | s2mps11,buck3-ramp-enable = <1>; | ||
| 87 | s2mps11,buck4-ramp-enable = <1>; | ||
| 88 | |||
| 89 | interrupt-parent = <&gpx3>; | ||
| 90 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; | ||
| 91 | |||
| 92 | s2mps11_osc: clocks { | ||
| 93 | #clock-cells = <1>; | ||
| 94 | clock-output-names = "s2mps11_ap", | ||
| 95 | "s2mps11_cp", "s2mps11_bt"; | ||
| 96 | }; | ||
| 97 | |||
| 98 | regulators { | ||
| 99 | ldo1_reg: LDO1 { | ||
| 100 | regulator-name = "PVDD_ALIVE_1V0"; | ||
| 101 | regulator-min-microvolt = <1000000>; | ||
| 102 | regulator-max-microvolt = <1000000>; | ||
| 103 | regulator-always-on; | ||
| 104 | }; | ||
| 105 | |||
| 106 | ldo2_reg: LDO2 { | ||
| 107 | regulator-name = "PVDD_APIO_1V8"; | ||
| 108 | regulator-min-microvolt = <1800000>; | ||
| 109 | regulator-max-microvolt = <1800000>; | ||
| 110 | }; | ||
| 111 | |||
| 112 | ldo3_reg: LDO3 { | ||
| 113 | regulator-name = "PVDD_APIO_MMCON_1V8"; | ||
| 114 | regulator-min-microvolt = <1800000>; | ||
| 115 | regulator-max-microvolt = <1800000>; | ||
| 116 | }; | ||
| 117 | |||
| 118 | ldo4_reg: LDO4 { | ||
| 119 | regulator-name = "PVDD_ADC_1V8"; | ||
| 120 | regulator-min-microvolt = <1800000>; | ||
| 121 | regulator-max-microvolt = <1800000>; | ||
| 122 | }; | ||
| 123 | |||
| 124 | ldo5_reg: LDO5 { | ||
| 125 | regulator-name = "PVDD_PLL_1V8"; | ||
| 126 | regulator-min-microvolt = <1800000>; | ||
| 127 | regulator-max-microvolt = <1800000>; | ||
| 128 | regulator-always-on; | ||
| 129 | }; | ||
| 130 | |||
| 131 | ldo6_reg: LDO6 { | ||
| 132 | regulator-name = "PVDD_ANAIP_1V0"; | ||
| 133 | regulator-min-microvolt = <1000000>; | ||
| 134 | regulator-max-microvolt = <1000000>; | ||
| 135 | }; | ||
| 136 | |||
| 137 | ldo7_reg: LDO7 { | ||
| 138 | regulator-name = "PVDD_ANAIP_1V8"; | ||
| 139 | regulator-min-microvolt = <1800000>; | ||
| 140 | regulator-max-microvolt = <1800000>; | ||
| 141 | }; | ||
| 142 | |||
| 143 | ldo8_reg: LDO8 { | ||
| 144 | regulator-name = "PVDD_ABB_1V8"; | ||
| 145 | regulator-min-microvolt = <1800000>; | ||
| 146 | regulator-max-microvolt = <1800000>; | ||
| 147 | }; | ||
| 148 | |||
| 149 | ldo9_reg: LDO9 { | ||
| 150 | regulator-name = "PVDD_USB_3V3"; | ||
| 151 | regulator-min-microvolt = <3000000>; | ||
| 152 | regulator-max-microvolt = <3000000>; | ||
| 153 | }; | ||
| 154 | |||
| 155 | ldo10_reg: LDO10 { | ||
| 156 | regulator-name = "PVDD_PRE_1V8"; | ||
| 157 | regulator-min-microvolt = <1800000>; | ||
| 158 | regulator-max-microvolt = <1800000>; | ||
| 159 | regulator-always-on; | ||
| 160 | }; | ||
| 161 | |||
| 162 | ldo11_reg: LDO11 { | ||
| 163 | regulator-name = "PVDD_USB_1V0"; | ||
| 164 | regulator-min-microvolt = <1000000>; | ||
| 165 | regulator-max-microvolt = <1000000>; | ||
| 166 | regulator-always-on; | ||
| 167 | }; | ||
| 168 | |||
| 169 | ldo12_reg: LDO12 { | ||
| 170 | regulator-name = "PVDD_HSIC_1V8"; | ||
| 171 | regulator-min-microvolt = <1800000>; | ||
| 172 | regulator-max-microvolt = <1800000>; | ||
| 173 | }; | ||
| 174 | |||
| 175 | ldo13_reg: LDO13 { | ||
| 176 | regulator-name = "PVDD_APIO_MMCOFF_2V8"; | ||
| 177 | regulator-min-microvolt = <2800000>; | ||
| 178 | regulator-max-microvolt = <2800000>; | ||
| 179 | }; | ||
| 180 | |||
| 181 | ldo15_reg: LDO15 { | ||
| 182 | regulator-name = "PVDD_PERI_2V8"; | ||
| 183 | regulator-min-microvolt = <3300000>; | ||
| 184 | regulator-max-microvolt = <3300000>; | ||
| 185 | }; | ||
| 186 | |||
| 187 | ldo16_reg: LDO16 { | ||
| 188 | regulator-name = "PVDD_PERI_3V3"; | ||
| 189 | regulator-min-microvolt = <2200000>; | ||
| 190 | regulator-max-microvolt = <2200000>; | ||
| 191 | }; | ||
| 192 | |||
| 193 | ldo18_reg: LDO18 { | ||
| 194 | regulator-name = "PVDD_EMMC_1V8"; | ||
| 195 | regulator-min-microvolt = <1800000>; | ||
| 196 | regulator-max-microvolt = <1800000>; | ||
| 197 | }; | ||
| 198 | |||
| 199 | ldo19_reg: LDO19 { | ||
| 200 | regulator-name = "PVDD_TFLASH_2V8"; | ||
| 201 | regulator-min-microvolt = <2800000>; | ||
| 202 | regulator-max-microvolt = <2800000>; | ||
| 203 | }; | ||
| 204 | |||
| 205 | ldo20_reg: LDO20 { | ||
| 206 | regulator-name = "PVDD_BTWIFI_1V8"; | ||
| 207 | regulator-min-microvolt = <1800000>; | ||
| 208 | regulator-max-microvolt = <1800000>; | ||
| 209 | }; | ||
| 210 | |||
| 211 | ldo21_reg: LDO21 { | ||
| 212 | regulator-name = "PVDD_CAM1IO_1V8"; | ||
| 213 | regulator-min-microvolt = <1800000>; | ||
| 214 | regulator-max-microvolt = <1800000>; | ||
| 215 | }; | ||
| 216 | |||
| 217 | ldo23_reg: LDO23 { | ||
| 218 | regulator-name = "PVDD_MIFS_1V1"; | ||
| 219 | regulator-min-microvolt = <1200000>; | ||
| 220 | regulator-max-microvolt = <1200000>; | ||
| 221 | }; | ||
| 222 | |||
| 223 | ldo24_reg: LDO24 { | ||
| 224 | regulator-name = "PVDD_CAM1_AVDD_2V8"; | ||
| 225 | regulator-min-microvolt = <2800000>; | ||
| 226 | regulator-max-microvolt = <2800000>; | ||
| 227 | }; | ||
| 228 | |||
| 229 | ldo26_reg: LDO26 { | ||
| 230 | regulator-name = "PVDD_CAM0_AF_2V8"; | ||
| 231 | regulator-min-microvolt = <3000000>; | ||
| 232 | regulator-max-microvolt = <3000000>; | ||
| 233 | }; | ||
| 234 | |||
| 235 | ldo27_reg: LDO27 { | ||
| 236 | regulator-name = "PVDD_G3DS_1V0"; | ||
| 237 | regulator-min-microvolt = <1200000>; | ||
| 238 | regulator-max-microvolt = <1200000>; | ||
| 239 | }; | ||
| 240 | |||
| 241 | ldo28_reg: LDO28 { | ||
| 242 | regulator-name = "PVDD_TSP_3V3"; | ||
| 243 | regulator-min-microvolt = <3300000>; | ||
| 244 | regulator-max-microvolt = <3300000>; | ||
| 245 | }; | ||
| 246 | |||
| 247 | ldo29_reg: LDO29 { | ||
| 248 | regulator-name = "PVDD_AUDIO_1V8"; | ||
| 249 | regulator-min-microvolt = <1800000>; | ||
| 250 | regulator-max-microvolt = <1800000>; | ||
| 251 | }; | ||
| 252 | |||
| 253 | ldo31_reg: LDO31 { | ||
| 254 | regulator-name = "PVDD_PERI_1V8"; | ||
| 255 | regulator-min-microvolt = <1800000>; | ||
| 256 | regulator-max-microvolt = <1800000>; | ||
| 257 | }; | ||
| 258 | |||
| 259 | ldo32_reg: LDO32 { | ||
| 260 | regulator-name = "PVDD_LCD_1V8"; | ||
| 261 | regulator-min-microvolt = <1800000>; | ||
| 262 | regulator-max-microvolt = <1800000>; | ||
| 263 | }; | ||
| 264 | |||
| 265 | ldo33_reg: LDO33 { | ||
| 266 | regulator-name = "PVDD_CAM0IO_1V8"; | ||
| 267 | regulator-min-microvolt = <1800000>; | ||
| 268 | regulator-max-microvolt = <1800000>; | ||
| 269 | }; | ||
| 270 | |||
| 271 | ldo35_reg: LDO35 { | ||
| 272 | regulator-name = "PVDD_CAM0_DVDD_1V2"; | ||
| 273 | regulator-min-microvolt = <1200000>; | ||
| 274 | regulator-max-microvolt = <1200000>; | ||
| 275 | }; | ||
| 276 | |||
| 277 | ldo38_reg: LDO38 { | ||
| 278 | regulator-name = "PVDD_CAM0_AVDD_2V8"; | ||
| 279 | regulator-min-microvolt = <2800000>; | ||
| 280 | regulator-max-microvolt = <2800000>; | ||
| 281 | }; | ||
| 282 | |||
| 283 | buck1_reg: BUCK1 { | ||
| 284 | regulator-name = "PVDD_MIF_1V1"; | ||
| 285 | regulator-min-microvolt = <800000>; | ||
| 286 | regulator-max-microvolt = <1100000>; | ||
| 287 | regulator-always-on; | ||
| 288 | }; | ||
| 289 | |||
| 290 | buck2_reg: BUCK2 { | ||
| 291 | regulator-name = "vdd_arm"; | ||
| 292 | regulator-min-microvolt = <800000>; | ||
| 293 | regulator-max-microvolt = <1000000>; | ||
| 294 | regulator-always-on; | ||
| 295 | }; | ||
| 296 | |||
| 297 | buck3_reg: BUCK3 { | ||
| 298 | regulator-name = "PVDD_INT_1V0"; | ||
| 299 | regulator-min-microvolt = <800000>; | ||
| 300 | regulator-max-microvolt = <1000000>; | ||
| 301 | regulator-always-on; | ||
| 302 | }; | ||
| 303 | |||
| 304 | buck4_reg: BUCK4 { | ||
| 305 | regulator-name = "PVDD_G3D_1V0"; | ||
| 306 | regulator-min-microvolt = <800000>; | ||
| 307 | regulator-max-microvolt = <1000000>; | ||
| 308 | }; | ||
| 309 | |||
| 310 | buck5_reg: BUCK5 { | ||
| 311 | regulator-name = "PVDD_LPDDR3_1V2"; | ||
| 312 | regulator-min-microvolt = <800000>; | ||
| 313 | regulator-max-microvolt = <1200000>; | ||
| 314 | regulator-always-on; | ||
| 315 | }; | ||
| 316 | |||
| 317 | buck6_reg: BUCK6 { | ||
| 318 | regulator-name = "PVDD_KFC_1V0"; | ||
| 319 | regulator-min-microvolt = <800000>; | ||
| 320 | regulator-max-microvolt = <1000000>; | ||
| 321 | regulator-always-on; | ||
| 322 | }; | ||
| 323 | |||
| 324 | buck7_reg: BUCK7 { | ||
| 325 | regulator-name = "VIN_LLDO_1V4"; | ||
| 326 | regulator-min-microvolt = <800000>; | ||
| 327 | regulator-max-microvolt = <1400000>; | ||
| 328 | regulator-always-on; | ||
| 329 | }; | ||
| 330 | |||
| 331 | buck8_reg: BUCK8 { | ||
| 332 | regulator-name = "VIN_MLDO_2V0"; | ||
| 333 | regulator-min-microvolt = <800000>; | ||
| 334 | regulator-max-microvolt = <2000000>; | ||
| 335 | regulator-always-on; | ||
| 336 | }; | ||
| 337 | |||
| 338 | buck9_reg: BUCK9 { | ||
| 339 | regulator-name = "VIN_HLDO_3V5"; | ||
| 340 | regulator-min-microvolt = <3000000>; | ||
| 341 | regulator-max-microvolt = <3500000>; | ||
| 342 | regulator-always-on; | ||
| 343 | }; | ||
| 344 | |||
| 345 | buck10_reg: BUCK10 { | ||
| 346 | regulator-name = "PVDD_EMMCF_2V8"; | ||
| 347 | regulator-min-microvolt = <2800000>; | ||
| 348 | regulator-max-microvolt = <2800000>; | ||
| 349 | }; | ||
| 350 | }; | ||
| 351 | }; | ||
| 352 | }; | ||
| 353 | |||
| 354 | gpio_keys { | ||
| 355 | compatible = "gpio-keys"; | ||
| 356 | |||
| 357 | wakeup { | ||
| 358 | label = "SW-TACT1"; | ||
| 359 | gpios = <&gpx2 7 1>; | ||
| 360 | linux,code = <KEY_WAKEUP>; | ||
| 361 | gpio-key,wakeup; | ||
| 362 | }; | ||
| 363 | }; | ||
| 66 | }; | 364 | }; |
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index fb5a1e25c632..ae1ee0470fca 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts | |||
| @@ -31,6 +31,43 @@ | |||
| 31 | }; | 31 | }; |
| 32 | }; | 32 | }; |
| 33 | 33 | ||
| 34 | regulators { | ||
| 35 | compatible = "simple-bus"; | ||
| 36 | #address-cells = <1>; | ||
| 37 | #size-cells = <0>; | ||
| 38 | |||
| 39 | vdd: fixed-regulator@0 { | ||
| 40 | compatible = "regulator-fixed"; | ||
| 41 | reg = <0>; | ||
| 42 | regulator-name = "vdd-supply"; | ||
| 43 | regulator-min-microvolt = <1800000>; | ||
| 44 | regulator-max-microvolt = <1800000>; | ||
| 45 | regulator-always-on; | ||
| 46 | }; | ||
| 47 | |||
| 48 | dbvdd: fixed-regulator@1 { | ||
| 49 | compatible = "regulator-fixed"; | ||
| 50 | reg = <1>; | ||
| 51 | regulator-name = "dbvdd-supply"; | ||
| 52 | regulator-min-microvolt = <3300000>; | ||
| 53 | regulator-max-microvolt = <3300000>; | ||
| 54 | regulator-always-on; | ||
| 55 | }; | ||
| 56 | |||
| 57 | spkvdd: fixed-regulator@2 { | ||
| 58 | compatible = "regulator-fixed"; | ||
| 59 | reg = <2>; | ||
| 60 | regulator-name = "spkvdd-supply"; | ||
| 61 | regulator-min-microvolt = <5000000>; | ||
| 62 | regulator-max-microvolt = <5000000>; | ||
| 63 | regulator-always-on; | ||
| 64 | }; | ||
| 65 | }; | ||
| 66 | |||
| 67 | rtc@101E0000 { | ||
| 68 | status = "okay"; | ||
| 69 | }; | ||
| 70 | |||
| 34 | mmc@12200000 { | 71 | mmc@12200000 { |
| 35 | status = "okay"; | 72 | status = "okay"; |
| 36 | broken-cd; | 73 | broken-cd; |
| @@ -120,4 +157,220 @@ | |||
| 120 | reg = <0x50>; | 157 | reg = <0x50>; |
| 121 | }; | 158 | }; |
| 122 | }; | 159 | }; |
| 160 | |||
| 161 | hsi2c_4: i2c@12CA0000 { | ||
| 162 | status = "okay"; | ||
| 163 | |||
| 164 | s2mps11_pmic@66 { | ||
| 165 | compatible = "samsung,s2mps11-pmic"; | ||
| 166 | reg = <0x66>; | ||
| 167 | s2mps11,buck2-ramp-delay = <12>; | ||
| 168 | s2mps11,buck34-ramp-delay = <12>; | ||
| 169 | s2mps11,buck16-ramp-delay = <12>; | ||
| 170 | s2mps11,buck6-ramp-enable = <1>; | ||
| 171 | s2mps11,buck2-ramp-enable = <1>; | ||
| 172 | s2mps11,buck3-ramp-enable = <1>; | ||
| 173 | s2mps11,buck4-ramp-enable = <1>; | ||
| 174 | |||
| 175 | s2mps11_osc: clocks { | ||
| 176 | #clock-cells = <1>; | ||
| 177 | clock-output-names = "s2mps11_ap", | ||
| 178 | "s2mps11_cp", "s2mps11_bt"; | ||
| 179 | }; | ||
| 180 | |||
| 181 | regulators { | ||
| 182 | ldo1_reg: LDO1 { | ||
| 183 | regulator-name = "vdd_ldo1"; | ||
| 184 | regulator-min-microvolt = <1000000>; | ||
| 185 | regulator-max-microvolt = <1000000>; | ||
| 186 | regulator-always-on; | ||
| 187 | }; | ||
| 188 | |||
| 189 | ldo3_reg: LDO3 { | ||
| 190 | regulator-name = "vdd_ldo3"; | ||
| 191 | regulator-min-microvolt = <1800000>; | ||
| 192 | regulator-max-microvolt = <1800000>; | ||
| 193 | regulator-always-on; | ||
| 194 | }; | ||
| 195 | |||
| 196 | ldo5_reg: LDO5 { | ||
| 197 | regulator-name = "vdd_ldo5"; | ||
| 198 | regulator-min-microvolt = <1800000>; | ||
| 199 | regulator-max-microvolt = <1800000>; | ||
| 200 | regulator-always-on; | ||
| 201 | }; | ||
| 202 | |||
| 203 | ldo6_reg: LDO6 { | ||
| 204 | regulator-name = "vdd_ldo6"; | ||
| 205 | regulator-min-microvolt = <1000000>; | ||
| 206 | regulator-max-microvolt = <1000000>; | ||
| 207 | regulator-always-on; | ||
| 208 | }; | ||
| 209 | |||
| 210 | ldo7_reg: LDO7 { | ||
| 211 | regulator-name = "vdd_ldo7"; | ||
| 212 | regulator-min-microvolt = <1800000>; | ||
| 213 | regulator-max-microvolt = <1800000>; | ||
| 214 | regulator-always-on; | ||
| 215 | }; | ||
| 216 | |||
| 217 | ldo8_reg: LDO8 { | ||
| 218 | regulator-name = "vdd_ldo8"; | ||
| 219 | regulator-min-microvolt = <1800000>; | ||
| 220 | regulator-max-microvolt = <1800000>; | ||
| 221 | regulator-always-on; | ||
| 222 | }; | ||
| 223 | |||
| 224 | ldo9_reg: LDO9 { | ||
| 225 | regulator-name = "vdd_ldo9"; | ||
| 226 | regulator-min-microvolt = <3000000>; | ||
| 227 | regulator-max-microvolt = <3000000>; | ||
| 228 | regulator-always-on; | ||
| 229 | }; | ||
| 230 | |||
| 231 | ldo10_reg: LDO10 { | ||
| 232 | regulator-name = "vdd_ldo10"; | ||
| 233 | regulator-min-microvolt = <1800000>; | ||
| 234 | regulator-max-microvolt = <1800000>; | ||
| 235 | regulator-always-on; | ||
| 236 | }; | ||
| 237 | |||
| 238 | ldo11_reg: LDO11 { | ||
| 239 | regulator-name = "vdd_ldo11"; | ||
| 240 | regulator-min-microvolt = <1000000>; | ||
| 241 | regulator-max-microvolt = <1000000>; | ||
| 242 | regulator-always-on; | ||
| 243 | }; | ||
| 244 | |||
| 245 | ldo12_reg: LDO12 { | ||
| 246 | regulator-name = "vdd_ldo12"; | ||
| 247 | regulator-min-microvolt = <1800000>; | ||
| 248 | regulator-max-microvolt = <1800000>; | ||
| 249 | regulator-always-on; | ||
| 250 | }; | ||
| 251 | |||
| 252 | ldo13_reg: LDO13 { | ||
| 253 | regulator-name = "vdd_ldo13"; | ||
| 254 | regulator-min-microvolt = <2800000>; | ||
| 255 | regulator-max-microvolt = <2800000>; | ||
| 256 | regulator-always-on; | ||
| 257 | }; | ||
| 258 | |||
| 259 | ldo15_reg: LDO15 { | ||
| 260 | regulator-name = "vdd_ldo15"; | ||
| 261 | regulator-min-microvolt = <3100000>; | ||
| 262 | regulator-max-microvolt = <3100000>; | ||
| 263 | regulator-always-on; | ||
| 264 | }; | ||
| 265 | |||
| 266 | ldo16_reg: LDO16 { | ||
| 267 | regulator-name = "vdd_ldo16"; | ||
| 268 | regulator-min-microvolt = <2200000>; | ||
| 269 | regulator-max-microvolt = <2200000>; | ||
| 270 | regulator-always-on; | ||
| 271 | }; | ||
| 272 | |||
| 273 | ldo17_reg: LDO17 { | ||
| 274 | regulator-name = "tsp_avdd"; | ||
| 275 | regulator-min-microvolt = <3300000>; | ||
| 276 | regulator-max-microvolt = <3300000>; | ||
| 277 | regulator-always-on; | ||
| 278 | }; | ||
| 279 | |||
| 280 | ldo19_reg: LDO19 { | ||
| 281 | regulator-name = "vdd_sd"; | ||
| 282 | regulator-min-microvolt = <2800000>; | ||
| 283 | regulator-max-microvolt = <2800000>; | ||
| 284 | regulator-always-on; | ||
| 285 | }; | ||
| 286 | |||
| 287 | ldo24_reg: LDO24 { | ||
| 288 | regulator-name = "tsp_io"; | ||
| 289 | regulator-min-microvolt = <2800000>; | ||
| 290 | regulator-max-microvolt = <2800000>; | ||
| 291 | regulator-always-on; | ||
| 292 | }; | ||
| 293 | |||
| 294 | buck1_reg: BUCK1 { | ||
| 295 | regulator-name = "vdd_mif"; | ||
| 296 | regulator-min-microvolt = <800000>; | ||
| 297 | regulator-max-microvolt = <1300000>; | ||
| 298 | regulator-always-on; | ||
| 299 | regulator-boot-on; | ||
| 300 | }; | ||
| 301 | |||
| 302 | buck2_reg: BUCK2 { | ||
| 303 | regulator-name = "vdd_arm"; | ||
| 304 | regulator-min-microvolt = <800000>; | ||
| 305 | regulator-max-microvolt = <1500000>; | ||
| 306 | regulator-always-on; | ||
| 307 | regulator-boot-on; | ||
| 308 | }; | ||
| 309 | |||
| 310 | buck3_reg: BUCK3 { | ||
| 311 | regulator-name = "vdd_int"; | ||
| 312 | regulator-min-microvolt = <800000>; | ||
| 313 | regulator-max-microvolt = <1400000>; | ||
| 314 | regulator-always-on; | ||
| 315 | regulator-boot-on; | ||
| 316 | }; | ||
| 317 | |||
| 318 | buck4_reg: BUCK4 { | ||
| 319 | regulator-name = "vdd_g3d"; | ||
| 320 | regulator-min-microvolt = <800000>; | ||
| 321 | regulator-max-microvolt = <1400000>; | ||
| 322 | regulator-always-on; | ||
| 323 | regulator-boot-on; | ||
| 324 | }; | ||
| 325 | |||
| 326 | buck5_reg: BUCK5 { | ||
| 327 | regulator-name = "vdd_mem"; | ||
| 328 | regulator-min-microvolt = <800000>; | ||
| 329 | regulator-max-microvolt = <1400000>; | ||
| 330 | regulator-always-on; | ||
| 331 | regulator-boot-on; | ||
| 332 | }; | ||
| 333 | |||
| 334 | buck6_reg: BUCK6 { | ||
| 335 | regulator-name = "vdd_kfc"; | ||
| 336 | regulator-min-microvolt = <800000>; | ||
| 337 | regulator-max-microvolt = <1500000>; | ||
| 338 | regulator-always-on; | ||
| 339 | regulator-boot-on; | ||
| 340 | }; | ||
| 341 | |||
| 342 | buck7_reg: BUCK7 { | ||
| 343 | regulator-name = "vdd_1.0v_ldo"; | ||
| 344 | regulator-min-microvolt = <800000>; | ||
| 345 | regulator-max-microvolt = <1500000>; | ||
| 346 | regulator-always-on; | ||
| 347 | regulator-boot-on; | ||
| 348 | }; | ||
| 349 | |||
| 350 | buck8_reg: BUCK8 { | ||
| 351 | regulator-name = "vdd_1.8v_ldo"; | ||
| 352 | regulator-min-microvolt = <800000>; | ||
| 353 | regulator-max-microvolt = <1500000>; | ||
| 354 | regulator-always-on; | ||
| 355 | regulator-boot-on; | ||
| 356 | }; | ||
| 357 | |||
| 358 | buck9_reg: BUCK9 { | ||
| 359 | regulator-name = "vdd_2.8v_ldo"; | ||
| 360 | regulator-min-microvolt = <3000000>; | ||
| 361 | regulator-max-microvolt = <3750000>; | ||
| 362 | regulator-always-on; | ||
| 363 | regulator-boot-on; | ||
| 364 | }; | ||
| 365 | |||
| 366 | buck10_reg: BUCK10 { | ||
| 367 | regulator-name = "vdd_vmem"; | ||
| 368 | regulator-min-microvolt = <2850000>; | ||
| 369 | regulator-max-microvolt = <2850000>; | ||
| 370 | regulator-always-on; | ||
| 371 | regulator-boot-on; | ||
| 372 | }; | ||
| 373 | }; | ||
| 374 | }; | ||
| 375 | }; | ||
| 123 | }; | 376 | }; |
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 8db792b26f79..e3329afbd8c4 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi | |||
| @@ -13,6 +13,7 @@ | |||
| 13 | * published by the Free Software Foundation. | 13 | * published by the Free Software Foundation. |
| 14 | */ | 14 | */ |
| 15 | 15 | ||
| 16 | #include <dt-bindings/clock/exynos5420.h> | ||
| 16 | #include "exynos5.dtsi" | 17 | #include "exynos5.dtsi" |
| 17 | #include "exynos5420-pinctrl.dtsi" | 18 | #include "exynos5420-pinctrl.dtsi" |
| 18 | 19 | ||
| @@ -119,7 +120,8 @@ | |||
| 119 | compatible = "samsung,exynos5420-audss-clock"; | 120 | compatible = "samsung,exynos5420-audss-clock"; |
| 120 | reg = <0x03810000 0x0C>; | 121 | reg = <0x03810000 0x0C>; |
| 121 | #clock-cells = <1>; | 122 | #clock-cells = <1>; |
| 122 | clocks = <&clock 1>, <&clock 5>, <&clock 148>, <&clock 149>; | 123 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, |
| 124 | <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>; | ||
| 123 | clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; | 125 | clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; |
| 124 | }; | 126 | }; |
| 125 | 127 | ||
| @@ -127,7 +129,7 @@ | |||
| 127 | compatible = "samsung,mfc-v7"; | 129 | compatible = "samsung,mfc-v7"; |
| 128 | reg = <0x11000000 0x10000>; | 130 | reg = <0x11000000 0x10000>; |
| 129 | interrupts = <0 96 0>; | 131 | interrupts = <0 96 0>; |
| 130 | clocks = <&clock 401>; | 132 | clocks = <&clock CLK_MFC>; |
| 131 | clock-names = "mfc"; | 133 | clock-names = "mfc"; |
| 132 | }; | 134 | }; |
| 133 | 135 | ||
| @@ -137,7 +139,7 @@ | |||
| 137 | #address-cells = <1>; | 139 | #address-cells = <1>; |
| 138 | #size-cells = <0>; | 140 | #size-cells = <0>; |
| 139 | reg = <0x12200000 0x2000>; | 141 | reg = <0x12200000 0x2000>; |
| 140 | clocks = <&clock 351>, <&clock 132>; | 142 | clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; |
| 141 | clock-names = "biu", "ciu"; | 143 | clock-names = "biu", "ciu"; |
| 142 | fifo-depth = <0x40>; | 144 | fifo-depth = <0x40>; |
| 143 | status = "disabled"; | 145 | status = "disabled"; |
| @@ -149,7 +151,7 @@ | |||
| 149 | #address-cells = <1>; | 151 | #address-cells = <1>; |
| 150 | #size-cells = <0>; | 152 | #size-cells = <0>; |
| 151 | reg = <0x12210000 0x2000>; | 153 | reg = <0x12210000 0x2000>; |
| 152 | clocks = <&clock 352>, <&clock 133>; | 154 | clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; |
| 153 | clock-names = "biu", "ciu"; | 155 | clock-names = "biu", "ciu"; |
| 154 | fifo-depth = <0x40>; | 156 | fifo-depth = <0x40>; |
| 155 | status = "disabled"; | 157 | status = "disabled"; |
| @@ -161,7 +163,7 @@ | |||
| 161 | #address-cells = <1>; | 163 | #address-cells = <1>; |
| 162 | #size-cells = <0>; | 164 | #size-cells = <0>; |
| 163 | reg = <0x12220000 0x1000>; | 165 | reg = <0x12220000 0x1000>; |
| 164 | clocks = <&clock 353>, <&clock 134>; | 166 | clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; |
| 165 | clock-names = "biu", "ciu"; | 167 | clock-names = "biu", "ciu"; |
| 166 | fifo-depth = <0x40>; | 168 | fifo-depth = <0x40>; |
| 167 | status = "disabled"; | 169 | status = "disabled"; |
| @@ -175,7 +177,7 @@ | |||
| 175 | interrupt-parent = <&mct_map>; | 177 | interrupt-parent = <&mct_map>; |
| 176 | interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, | 178 | interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, |
| 177 | <8>, <9>, <10>, <11>; | 179 | <8>, <9>, <10>, <11>; |
| 178 | clocks = <&clock 1>, <&clock 315>; | 180 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; |
| 179 | clock-names = "fin_pll", "mct"; | 181 | clock-names = "fin_pll", "mct"; |
| 180 | 182 | ||
| 181 | mct_map: mct-map { | 183 | mct_map: mct-map { |
| @@ -269,9 +271,9 @@ | |||
| 269 | }; | 271 | }; |
| 270 | 272 | ||
| 271 | rtc@101E0000 { | 273 | rtc@101E0000 { |
| 272 | clocks = <&clock 317>; | 274 | clocks = <&clock CLK_RTC>; |
| 273 | clock-names = "rtc"; | 275 | clock-names = "rtc"; |
| 274 | status = "okay"; | 276 | status = "disabled"; |
| 275 | }; | 277 | }; |
| 276 | 278 | ||
| 277 | amba { | 279 | amba { |
| @@ -281,11 +283,22 @@ | |||
| 281 | interrupt-parent = <&gic>; | 283 | interrupt-parent = <&gic>; |
| 282 | ranges; | 284 | ranges; |
| 283 | 285 | ||
| 286 | adma: adma@03880000 { | ||
| 287 | compatible = "arm,pl330", "arm,primecell"; | ||
| 288 | reg = <0x03880000 0x1000>; | ||
| 289 | interrupts = <0 110 0>; | ||
| 290 | clocks = <&clock_audss EXYNOS_ADMA>; | ||
| 291 | clock-names = "apb_pclk"; | ||
| 292 | #dma-cells = <1>; | ||
| 293 | #dma-channels = <6>; | ||
| 294 | #dma-requests = <16>; | ||
| 295 | }; | ||
| 296 | |||
| 284 | pdma0: pdma@121A0000 { | 297 | pdma0: pdma@121A0000 { |
| 285 | compatible = "arm,pl330", "arm,primecell"; | 298 | compatible = "arm,pl330", "arm,primecell"; |
| 286 | reg = <0x121A0000 0x1000>; | 299 | reg = <0x121A0000 0x1000>; |
| 287 | interrupts = <0 34 0>; | 300 | interrupts = <0 34 0>; |
| 288 | clocks = <&clock 362>; | 301 | clocks = <&clock CLK_PDMA0>; |
| 289 | clock-names = "apb_pclk"; | 302 | clock-names = "apb_pclk"; |
| 290 | #dma-cells = <1>; | 303 | #dma-cells = <1>; |
| 291 | #dma-channels = <8>; | 304 | #dma-channels = <8>; |
| @@ -296,7 +309,7 @@ | |||
| 296 | compatible = "arm,pl330", "arm,primecell"; | 309 | compatible = "arm,pl330", "arm,primecell"; |
| 297 | reg = <0x121B0000 0x1000>; | 310 | reg = <0x121B0000 0x1000>; |
| 298 | interrupts = <0 35 0>; | 311 | interrupts = <0 35 0>; |
| 299 | clocks = <&clock 363>; | 312 | clocks = <&clock CLK_PDMA1>; |
| 300 | clock-names = "apb_pclk"; | 313 | clock-names = "apb_pclk"; |
| 301 | #dma-cells = <1>; | 314 | #dma-cells = <1>; |
| 302 | #dma-channels = <8>; | 315 | #dma-channels = <8>; |
| @@ -307,7 +320,7 @@ | |||
| 307 | compatible = "arm,pl330", "arm,primecell"; | 320 | compatible = "arm,pl330", "arm,primecell"; |
| 308 | reg = <0x10800000 0x1000>; | 321 | reg = <0x10800000 0x1000>; |
| 309 | interrupts = <0 33 0>; | 322 | interrupts = <0 33 0>; |
| 310 | clocks = <&clock 473>; | 323 | clocks = <&clock CLK_MDMA0>; |
| 311 | clock-names = "apb_pclk"; | 324 | clock-names = "apb_pclk"; |
| 312 | #dma-cells = <1>; | 325 | #dma-cells = <1>; |
| 313 | #dma-channels = <8>; | 326 | #dma-channels = <8>; |
| @@ -318,7 +331,7 @@ | |||
| 318 | compatible = "arm,pl330", "arm,primecell"; | 331 | compatible = "arm,pl330", "arm,primecell"; |
| 319 | reg = <0x11C10000 0x1000>; | 332 | reg = <0x11C10000 0x1000>; |
| 320 | interrupts = <0 124 0>; | 333 | interrupts = <0 124 0>; |
| 321 | clocks = <&clock 442>; | 334 | clocks = <&clock CLK_MDMA1>; |
| 322 | clock-names = "apb_pclk"; | 335 | clock-names = "apb_pclk"; |
| 323 | #dma-cells = <1>; | 336 | #dma-cells = <1>; |
| 324 | #dma-channels = <8>; | 337 | #dma-channels = <8>; |
| @@ -326,6 +339,49 @@ | |||
| 326 | }; | 339 | }; |
| 327 | }; | 340 | }; |
| 328 | 341 | ||
| 342 | i2s0: i2s@03830000 { | ||
| 343 | compatible = "samsung,exynos5420-i2s"; | ||
| 344 | reg = <0x03830000 0x100>; | ||
| 345 | dmas = <&adma 0 | ||
| 346 | &adma 2 | ||
| 347 | &adma 1>; | ||
| 348 | dma-names = "tx", "rx", "tx-sec"; | ||
| 349 | clocks = <&clock_audss EXYNOS_I2S_BUS>, | ||
| 350 | <&clock_audss EXYNOS_I2S_BUS>, | ||
| 351 | <&clock_audss EXYNOS_SCLK_I2S>; | ||
| 352 | clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; | ||
| 353 | samsung,idma-addr = <0x03000000>; | ||
| 354 | pinctrl-names = "default"; | ||
| 355 | pinctrl-0 = <&i2s0_bus>; | ||
| 356 | status = "disabled"; | ||
| 357 | }; | ||
| 358 | |||
| 359 | i2s1: i2s@12D60000 { | ||
| 360 | compatible = "samsung,exynos5420-i2s"; | ||
| 361 | reg = <0x12D60000 0x100>; | ||
| 362 | dmas = <&pdma1 12 | ||
| 363 | &pdma1 11>; | ||
| 364 | dma-names = "tx", "rx"; | ||
| 365 | clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>; | ||
| 366 | clock-names = "iis", "i2s_opclk0"; | ||
| 367 | pinctrl-names = "default"; | ||
| 368 | pinctrl-0 = <&i2s1_bus>; | ||
| 369 | status = "disabled"; | ||
| 370 | }; | ||
| 371 | |||
| 372 | i2s2: i2s@12D70000 { | ||
| 373 | compatible = "samsung,exynos5420-i2s"; | ||
| 374 | reg = <0x12D70000 0x100>; | ||
| 375 | dmas = <&pdma0 12 | ||
| 376 | &pdma0 11>; | ||
| 377 | dma-names = "tx", "rx"; | ||
| 378 | clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>; | ||
| 379 | clock-names = "iis", "i2s_opclk0"; | ||
| 380 | pinctrl-names = "default"; | ||
| 381 | pinctrl-0 = <&i2s2_bus>; | ||
| 382 | status = "disabled"; | ||
| 383 | }; | ||
| 384 | |||
| 329 | spi_0: spi@12d20000 { | 385 | spi_0: spi@12d20000 { |
| 330 | compatible = "samsung,exynos4210-spi"; | 386 | compatible = "samsung,exynos4210-spi"; |
| 331 | reg = <0x12d20000 0x100>; | 387 | reg = <0x12d20000 0x100>; |
| @@ -337,7 +393,7 @@ | |||
| 337 | #size-cells = <0>; | 393 | #size-cells = <0>; |
| 338 | pinctrl-names = "default"; | 394 | pinctrl-names = "default"; |
| 339 | pinctrl-0 = <&spi0_bus>; | 395 | pinctrl-0 = <&spi0_bus>; |
| 340 | clocks = <&clock 271>, <&clock 135>; | 396 | clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; |
| 341 | clock-names = "spi", "spi_busclk0"; | 397 | clock-names = "spi", "spi_busclk0"; |
| 342 | status = "disabled"; | 398 | status = "disabled"; |
| 343 | }; | 399 | }; |
| @@ -353,7 +409,7 @@ | |||
| 353 | #size-cells = <0>; | 409 | #size-cells = <0>; |
| 354 | pinctrl-names = "default"; | 410 | pinctrl-names = "default"; |
| 355 | pinctrl-0 = <&spi1_bus>; | 411 | pinctrl-0 = <&spi1_bus>; |
| 356 | clocks = <&clock 272>, <&clock 136>; | 412 | clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; |
| 357 | clock-names = "spi", "spi_busclk0"; | 413 | clock-names = "spi", "spi_busclk0"; |
| 358 | status = "disabled"; | 414 | status = "disabled"; |
| 359 | }; | 415 | }; |
| @@ -369,28 +425,28 @@ | |||
| 369 | #size-cells = <0>; | 425 | #size-cells = <0>; |
| 370 | pinctrl-names = "default"; | 426 | pinctrl-names = "default"; |
| 371 | pinctrl-0 = <&spi2_bus>; | 427 | pinctrl-0 = <&spi2_bus>; |
| 372 | clocks = <&clock 273>, <&clock 137>; | 428 | clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; |
| 373 | clock-names = "spi", "spi_busclk0"; | 429 | clock-names = "spi", "spi_busclk0"; |
| 374 | status = "disabled"; | 430 | status = "disabled"; |
| 375 | }; | 431 | }; |
| 376 | 432 | ||
| 377 | serial@12C00000 { | 433 | serial@12C00000 { |
| 378 | clocks = <&clock 257>, <&clock 128>; | 434 | clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; |
| 379 | clock-names = "uart", "clk_uart_baud0"; | 435 | clock-names = "uart", "clk_uart_baud0"; |
| 380 | }; | 436 | }; |
| 381 | 437 | ||
| 382 | serial@12C10000 { | 438 | serial@12C10000 { |
| 383 | clocks = <&clock 258>, <&clock 129>; | 439 | clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; |
| 384 | clock-names = "uart", "clk_uart_baud0"; | 440 | clock-names = "uart", "clk_uart_baud0"; |
| 385 | }; | 441 | }; |
| 386 | 442 | ||
| 387 | serial@12C20000 { | 443 | serial@12C20000 { |
| 388 | clocks = <&clock 259>, <&clock 130>; | 444 | clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; |
| 389 | clock-names = "uart", "clk_uart_baud0"; | 445 | clock-names = "uart", "clk_uart_baud0"; |
| 390 | }; | 446 | }; |
| 391 | 447 | ||
| 392 | serial@12C30000 { | 448 | serial@12C30000 { |
| 393 | clocks = <&clock 260>, <&clock 131>; | 449 | clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; |
| 394 | clock-names = "uart", "clk_uart_baud0"; | 450 | clock-names = "uart", "clk_uart_baud0"; |
| 395 | }; | 451 | }; |
| 396 | 452 | ||
| @@ -399,7 +455,7 @@ | |||
| 399 | reg = <0x12dd0000 0x100>; | 455 | reg = <0x12dd0000 0x100>; |
| 400 | samsung,pwm-outputs = <0>, <1>, <2>, <3>; | 456 | samsung,pwm-outputs = <0>, <1>, <2>, <3>; |
| 401 | #pwm-cells = <3>; | 457 | #pwm-cells = <3>; |
| 402 | clocks = <&clock 279>; | 458 | clocks = <&clock CLK_PWM>; |
| 403 | clock-names = "timers"; | 459 | clock-names = "timers"; |
| 404 | }; | 460 | }; |
| 405 | 461 | ||
| @@ -410,7 +466,7 @@ | |||
| 410 | }; | 466 | }; |
| 411 | 467 | ||
| 412 | dp-controller@145B0000 { | 468 | dp-controller@145B0000 { |
| 413 | clocks = <&clock 412>; | 469 | clocks = <&clock CLK_DP1>; |
| 414 | clock-names = "dp"; | 470 | clock-names = "dp"; |
| 415 | phys = <&dp_phy>; | 471 | phys = <&dp_phy>; |
| 416 | phy-names = "dp"; | 472 | phy-names = "dp"; |
| @@ -418,7 +474,7 @@ | |||
| 418 | 474 | ||
| 419 | fimd@14400000 { | 475 | fimd@14400000 { |
| 420 | samsung,power-domain = <&disp_pd>; | 476 | samsung,power-domain = <&disp_pd>; |
| 421 | clocks = <&clock 147>, <&clock 421>; | 477 | clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; |
| 422 | clock-names = "sclk_fimd", "fimd"; | 478 | clock-names = "sclk_fimd", "fimd"; |
| 423 | }; | 479 | }; |
| 424 | 480 | ||
| @@ -426,7 +482,7 @@ | |||
| 426 | compatible = "samsung,exynos-adc-v2"; | 482 | compatible = "samsung,exynos-adc-v2"; |
| 427 | reg = <0x12D10000 0x100>, <0x10040720 0x4>; | 483 | reg = <0x12D10000 0x100>, <0x10040720 0x4>; |
| 428 | interrupts = <0 106 0>; | 484 | interrupts = <0 106 0>; |
| 429 | clocks = <&clock 270>; | 485 | clocks = <&clock CLK_TSADC>; |
| 430 | clock-names = "adc"; | 486 | clock-names = "adc"; |
| 431 | #io-channel-cells = <1>; | 487 | #io-channel-cells = <1>; |
| 432 | io-channel-ranges; | 488 | io-channel-ranges; |
| @@ -439,7 +495,7 @@ | |||
| 439 | interrupts = <0 56 0>; | 495 | interrupts = <0 56 0>; |
| 440 | #address-cells = <1>; | 496 | #address-cells = <1>; |
| 441 | #size-cells = <0>; | 497 | #size-cells = <0>; |
| 442 | clocks = <&clock 261>; | 498 | clocks = <&clock CLK_I2C0>; |
| 443 | clock-names = "i2c"; | 499 | clock-names = "i2c"; |
| 444 | pinctrl-names = "default"; | 500 | pinctrl-names = "default"; |
| 445 | pinctrl-0 = <&i2c0_bus>; | 501 | pinctrl-0 = <&i2c0_bus>; |
| @@ -452,7 +508,7 @@ | |||
| 452 | interrupts = <0 57 0>; | 508 | interrupts = <0 57 0>; |
| 453 | #address-cells = <1>; | 509 | #address-cells = <1>; |
| 454 | #size-cells = <0>; | 510 | #size-cells = <0>; |
| 455 | clocks = <&clock 262>; | 511 | clocks = <&clock CLK_I2C1>; |
| 456 | clock-names = "i2c"; | 512 | clock-names = "i2c"; |
| 457 | pinctrl-names = "default"; | 513 | pinctrl-names = "default"; |
| 458 | pinctrl-0 = <&i2c1_bus>; | 514 | pinctrl-0 = <&i2c1_bus>; |
| @@ -465,7 +521,7 @@ | |||
| 465 | interrupts = <0 58 0>; | 521 | interrupts = <0 58 0>; |
| 466 | #address-cells = <1>; | 522 | #address-cells = <1>; |
| 467 | #size-cells = <0>; | 523 | #size-cells = <0>; |
| 468 | clocks = <&clock 263>; | 524 | clocks = <&clock CLK_I2C2>; |
| 469 | clock-names = "i2c"; | 525 | clock-names = "i2c"; |
| 470 | pinctrl-names = "default"; | 526 | pinctrl-names = "default"; |
| 471 | pinctrl-0 = <&i2c2_bus>; | 527 | pinctrl-0 = <&i2c2_bus>; |
| @@ -478,7 +534,7 @@ | |||
| 478 | interrupts = <0 59 0>; | 534 | interrupts = <0 59 0>; |
| 479 | #address-cells = <1>; | 535 | #address-cells = <1>; |
| 480 | #size-cells = <0>; | 536 | #size-cells = <0>; |
| 481 | clocks = <&clock 264>; | 537 | clocks = <&clock CLK_I2C3>; |
| 482 | clock-names = "i2c"; | 538 | clock-names = "i2c"; |
| 483 | pinctrl-names = "default"; | 539 | pinctrl-names = "default"; |
| 484 | pinctrl-0 = <&i2c3_bus>; | 540 | pinctrl-0 = <&i2c3_bus>; |
| @@ -493,7 +549,7 @@ | |||
| 493 | #size-cells = <0>; | 549 | #size-cells = <0>; |
| 494 | pinctrl-names = "default"; | 550 | pinctrl-names = "default"; |
| 495 | pinctrl-0 = <&i2c4_hs_bus>; | 551 | pinctrl-0 = <&i2c4_hs_bus>; |
| 496 | clocks = <&clock 265>; | 552 | clocks = <&clock CLK_I2C4>; |
| 497 | clock-names = "hsi2c"; | 553 | clock-names = "hsi2c"; |
| 498 | status = "disabled"; | 554 | status = "disabled"; |
| 499 | }; | 555 | }; |
| @@ -506,7 +562,7 @@ | |||
| 506 | #size-cells = <0>; | 562 | #size-cells = <0>; |
| 507 | pinctrl-names = "default"; | 563 | pinctrl-names = "default"; |
| 508 | pinctrl-0 = <&i2c5_hs_bus>; | 564 | pinctrl-0 = <&i2c5_hs_bus>; |
| 509 | clocks = <&clock 266>; | 565 | clocks = <&clock CLK_I2C5>; |
| 510 | clock-names = "hsi2c"; | 566 | clock-names = "hsi2c"; |
| 511 | status = "disabled"; | 567 | status = "disabled"; |
| 512 | }; | 568 | }; |
| @@ -519,7 +575,7 @@ | |||
| 519 | #size-cells = <0>; | 575 | #size-cells = <0>; |
| 520 | pinctrl-names = "default"; | 576 | pinctrl-names = "default"; |
| 521 | pinctrl-0 = <&i2c6_hs_bus>; | 577 | pinctrl-0 = <&i2c6_hs_bus>; |
| 522 | clocks = <&clock 267>; | 578 | clocks = <&clock CLK_I2C6>; |
| 523 | clock-names = "hsi2c"; | 579 | clock-names = "hsi2c"; |
| 524 | status = "disabled"; | 580 | status = "disabled"; |
| 525 | }; | 581 | }; |
| @@ -532,7 +588,7 @@ | |||
| 532 | #size-cells = <0>; | 588 | #size-cells = <0>; |
| 533 | pinctrl-names = "default"; | 589 | pinctrl-names = "default"; |
| 534 | pinctrl-0 = <&i2c7_hs_bus>; | 590 | pinctrl-0 = <&i2c7_hs_bus>; |
| 535 | clocks = <&clock 268>; | 591 | clocks = <&clock CLK_I2C7>; |
| 536 | clock-names = "hsi2c"; | 592 | clock-names = "hsi2c"; |
| 537 | status = "disabled"; | 593 | status = "disabled"; |
| 538 | }; | 594 | }; |
| @@ -545,7 +601,7 @@ | |||
| 545 | #size-cells = <0>; | 601 | #size-cells = <0>; |
| 546 | pinctrl-names = "default"; | 602 | pinctrl-names = "default"; |
| 547 | pinctrl-0 = <&i2c8_hs_bus>; | 603 | pinctrl-0 = <&i2c8_hs_bus>; |
| 548 | clocks = <&clock 281>; | 604 | clocks = <&clock CLK_I2C8>; |
| 549 | clock-names = "hsi2c"; | 605 | clock-names = "hsi2c"; |
| 550 | status = "disabled"; | 606 | status = "disabled"; |
| 551 | }; | 607 | }; |
| @@ -558,7 +614,7 @@ | |||
| 558 | #size-cells = <0>; | 614 | #size-cells = <0>; |
| 559 | pinctrl-names = "default"; | 615 | pinctrl-names = "default"; |
| 560 | pinctrl-0 = <&i2c9_hs_bus>; | 616 | pinctrl-0 = <&i2c9_hs_bus>; |
| 561 | clocks = <&clock 282>; | 617 | clocks = <&clock CLK_I2C9>; |
| 562 | clock-names = "hsi2c"; | 618 | clock-names = "hsi2c"; |
| 563 | status = "disabled"; | 619 | status = "disabled"; |
| 564 | }; | 620 | }; |
| @@ -571,7 +627,7 @@ | |||
| 571 | #size-cells = <0>; | 627 | #size-cells = <0>; |
| 572 | pinctrl-names = "default"; | 628 | pinctrl-names = "default"; |
| 573 | pinctrl-0 = <&i2c10_hs_bus>; | 629 | pinctrl-0 = <&i2c10_hs_bus>; |
| 574 | clocks = <&clock 283>; | 630 | clocks = <&clock CLK_I2C10>; |
| 575 | clock-names = "hsi2c"; | 631 | clock-names = "hsi2c"; |
| 576 | status = "disabled"; | 632 | status = "disabled"; |
| 577 | }; | 633 | }; |
| @@ -580,8 +636,9 @@ | |||
| 580 | compatible = "samsung,exynos4212-hdmi"; | 636 | compatible = "samsung,exynos4212-hdmi"; |
| 581 | reg = <0x14530000 0x70000>; | 637 | reg = <0x14530000 0x70000>; |
| 582 | interrupts = <0 95 0>; | 638 | interrupts = <0 95 0>; |
| 583 | clocks = <&clock 413>, <&clock 143>, <&clock 768>, | 639 | clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, |
| 584 | <&clock 158>, <&clock 640>; | 640 | <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, |
| 641 | <&clock CLK_MOUT_HDMI>; | ||
| 585 | clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", | 642 | clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", |
| 586 | "sclk_hdmiphy", "mout_hdmi"; | 643 | "sclk_hdmiphy", "mout_hdmi"; |
| 587 | status = "disabled"; | 644 | status = "disabled"; |
| @@ -591,7 +648,7 @@ | |||
| 591 | compatible = "samsung,exynos5420-mixer"; | 648 | compatible = "samsung,exynos5420-mixer"; |
| 592 | reg = <0x14450000 0x10000>; | 649 | reg = <0x14450000 0x10000>; |
| 593 | interrupts = <0 94 0>; | 650 | interrupts = <0 94 0>; |
| 594 | clocks = <&clock 431>, <&clock 143>; | 651 | clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>; |
| 595 | clock-names = "mixer", "sclk_hdmi"; | 652 | clock-names = "mixer", "sclk_hdmi"; |
| 596 | }; | 653 | }; |
| 597 | 654 | ||
| @@ -599,7 +656,7 @@ | |||
| 599 | compatible = "samsung,exynos5-gsc"; | 656 | compatible = "samsung,exynos5-gsc"; |
| 600 | reg = <0x13e00000 0x1000>; | 657 | reg = <0x13e00000 0x1000>; |
| 601 | interrupts = <0 85 0>; | 658 | interrupts = <0 85 0>; |
| 602 | clocks = <&clock 465>; | 659 | clocks = <&clock CLK_GSCL0>; |
| 603 | clock-names = "gscl"; | 660 | clock-names = "gscl"; |
| 604 | samsung,power-domain = <&gsc_pd>; | 661 | samsung,power-domain = <&gsc_pd>; |
| 605 | }; | 662 | }; |
| @@ -608,16 +665,21 @@ | |||
| 608 | compatible = "samsung,exynos5-gsc"; | 665 | compatible = "samsung,exynos5-gsc"; |
| 609 | reg = <0x13e10000 0x1000>; | 666 | reg = <0x13e10000 0x1000>; |
| 610 | interrupts = <0 86 0>; | 667 | interrupts = <0 86 0>; |
| 611 | clocks = <&clock 466>; | 668 | clocks = <&clock CLK_GSCL1>; |
| 612 | clock-names = "gscl"; | 669 | clock-names = "gscl"; |
| 613 | samsung,power-domain = <&gsc_pd>; | 670 | samsung,power-domain = <&gsc_pd>; |
| 614 | }; | 671 | }; |
| 615 | 672 | ||
| 673 | pmu_system_controller: system-controller@10040000 { | ||
| 674 | compatible = "samsung,exynos5420-pmu", "syscon"; | ||
| 675 | reg = <0x10040000 0x5000>; | ||
| 676 | }; | ||
| 677 | |||
| 616 | tmu_cpu0: tmu@10060000 { | 678 | tmu_cpu0: tmu@10060000 { |
| 617 | compatible = "samsung,exynos5420-tmu"; | 679 | compatible = "samsung,exynos5420-tmu"; |
| 618 | reg = <0x10060000 0x100>; | 680 | reg = <0x10060000 0x100>; |
| 619 | interrupts = <0 65 0>; | 681 | interrupts = <0 65 0>; |
| 620 | clocks = <&clock 318>; | 682 | clocks = <&clock CLK_TMU>; |
| 621 | clock-names = "tmu_apbif"; | 683 | clock-names = "tmu_apbif"; |
| 622 | }; | 684 | }; |
| 623 | 685 | ||
| @@ -625,7 +687,7 @@ | |||
| 625 | compatible = "samsung,exynos5420-tmu"; | 687 | compatible = "samsung,exynos5420-tmu"; |
| 626 | reg = <0x10064000 0x100>; | 688 | reg = <0x10064000 0x100>; |
| 627 | interrupts = <0 183 0>; | 689 | interrupts = <0 183 0>; |
| 628 | clocks = <&clock 318>; | 690 | clocks = <&clock CLK_TMU>; |
| 629 | clock-names = "tmu_apbif"; | 691 | clock-names = "tmu_apbif"; |
| 630 | }; | 692 | }; |
| 631 | 693 | ||
| @@ -633,7 +695,7 @@ | |||
| 633 | compatible = "samsung,exynos5420-tmu-ext-triminfo"; | 695 | compatible = "samsung,exynos5420-tmu-ext-triminfo"; |
| 634 | reg = <0x10068000 0x100>, <0x1006c000 0x4>; | 696 | reg = <0x10068000 0x100>, <0x1006c000 0x4>; |
| 635 | interrupts = <0 184 0>; | 697 | interrupts = <0 184 0>; |
| 636 | clocks = <&clock 318>, <&clock 318>; | 698 | clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; |
| 637 | clock-names = "tmu_apbif", "tmu_triminfo_apbif"; | 699 | clock-names = "tmu_apbif", "tmu_triminfo_apbif"; |
| 638 | }; | 700 | }; |
| 639 | 701 | ||
| @@ -641,7 +703,7 @@ | |||
| 641 | compatible = "samsung,exynos5420-tmu-ext-triminfo"; | 703 | compatible = "samsung,exynos5420-tmu-ext-triminfo"; |
| 642 | reg = <0x1006c000 0x100>, <0x100a0000 0x4>; | 704 | reg = <0x1006c000 0x100>, <0x100a0000 0x4>; |
| 643 | interrupts = <0 185 0>; | 705 | interrupts = <0 185 0>; |
| 644 | clocks = <&clock 318>, <&clock 319>; | 706 | clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; |
| 645 | clock-names = "tmu_apbif", "tmu_triminfo_apbif"; | 707 | clock-names = "tmu_apbif", "tmu_triminfo_apbif"; |
| 646 | }; | 708 | }; |
| 647 | 709 | ||
| @@ -649,7 +711,16 @@ | |||
| 649 | compatible = "samsung,exynos5420-tmu-ext-triminfo"; | 711 | compatible = "samsung,exynos5420-tmu-ext-triminfo"; |
| 650 | reg = <0x100a0000 0x100>, <0x10068000 0x4>; | 712 | reg = <0x100a0000 0x100>, <0x10068000 0x4>; |
| 651 | interrupts = <0 215 0>; | 713 | interrupts = <0 215 0>; |
| 652 | clocks = <&clock 319>, <&clock 318>; | 714 | clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; |
| 653 | clock-names = "tmu_apbif", "tmu_triminfo_apbif"; | 715 | clock-names = "tmu_apbif", "tmu_triminfo_apbif"; |
| 654 | }; | 716 | }; |
| 717 | |||
| 718 | watchdog@101D0000 { | ||
| 719 | compatible = "samsung,exynos5420-wdt"; | ||
| 720 | reg = <0x101D0000 0x100>; | ||
| 721 | interrupts = <0 42 0>; | ||
| 722 | clocks = <&clock CLK_WDT>; | ||
| 723 | clock-names = "watchdog"; | ||
| 724 | samsung,syscon-phandle = <&pmu_system_controller>; | ||
| 725 | }; | ||
| 655 | }; | 726 | }; |
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi index 02a0a1226cef..75c7b89cec2f 100644 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi | |||
| @@ -9,6 +9,7 @@ | |||
| 9 | * published by the Free Software Foundation. | 9 | * published by the Free Software Foundation. |
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | #include <dt-bindings/clock/exynos5440.h> | ||
| 12 | #include "skeleton.dtsi" | 13 | #include "skeleton.dtsi" |
| 13 | 14 | ||
| 14 | / { | 15 | / { |
| @@ -105,7 +106,7 @@ | |||
| 105 | compatible = "samsung,exynos4210-uart"; | 106 | compatible = "samsung,exynos4210-uart"; |
| 106 | reg = <0xB0000 0x1000>; | 107 | reg = <0xB0000 0x1000>; |
| 107 | interrupts = <0 2 0>; | 108 | interrupts = <0 2 0>; |
| 108 | clocks = <&clock 21>, <&clock 21>; | 109 | clocks = <&clock CLK_B_125>, <&clock CLK_B_125>; |
| 109 | clock-names = "uart", "clk_uart_baud0"; | 110 | clock-names = "uart", "clk_uart_baud0"; |
| 110 | }; | 111 | }; |
| 111 | 112 | ||
| @@ -113,7 +114,7 @@ | |||
| 113 | compatible = "samsung,exynos4210-uart"; | 114 | compatible = "samsung,exynos4210-uart"; |
| 114 | reg = <0xC0000 0x1000>; | 115 | reg = <0xC0000 0x1000>; |
| 115 | interrupts = <0 3 0>; | 116 | interrupts = <0 3 0>; |
| 116 | clocks = <&clock 21>, <&clock 21>; | 117 | clocks = <&clock CLK_B_125>, <&clock CLK_B_125>; |
| 117 | clock-names = "uart", "clk_uart_baud0"; | 118 | clock-names = "uart", "clk_uart_baud0"; |
| 118 | }; | 119 | }; |
| 119 | 120 | ||
| @@ -125,7 +126,7 @@ | |||
| 125 | #size-cells = <0>; | 126 | #size-cells = <0>; |
| 126 | samsung,spi-src-clk = <0>; | 127 | samsung,spi-src-clk = <0>; |
| 127 | num-cs = <1>; | 128 | num-cs = <1>; |
| 128 | clocks = <&clock 21>, <&clock 16>; | 129 | clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>; |
| 129 | clock-names = "spi", "spi_busclk0"; | 130 | clock-names = "spi", "spi_busclk0"; |
| 130 | }; | 131 | }; |
| 131 | 132 | ||
| @@ -161,7 +162,7 @@ | |||
| 161 | interrupts = <0 5 0>; | 162 | interrupts = <0 5 0>; |
| 162 | #address-cells = <1>; | 163 | #address-cells = <1>; |
| 163 | #size-cells = <0>; | 164 | #size-cells = <0>; |
| 164 | clocks = <&clock 21>; | 165 | clocks = <&clock CLK_B_125>; |
| 165 | clock-names = "i2c"; | 166 | clock-names = "i2c"; |
| 166 | }; | 167 | }; |
| 167 | 168 | ||
| @@ -171,7 +172,7 @@ | |||
| 171 | interrupts = <0 6 0>; | 172 | interrupts = <0 6 0>; |
| 172 | #address-cells = <1>; | 173 | #address-cells = <1>; |
| 173 | #size-cells = <0>; | 174 | #size-cells = <0>; |
| 174 | clocks = <&clock 21>; | 175 | clocks = <&clock CLK_B_125>; |
| 175 | clock-names = "i2c"; | 176 | clock-names = "i2c"; |
| 176 | }; | 177 | }; |
| 177 | 178 | ||
| @@ -179,7 +180,7 @@ | |||
| 179 | compatible = "samsung,s3c2410-wdt"; | 180 | compatible = "samsung,s3c2410-wdt"; |
| 180 | reg = <0x110000 0x1000>; | 181 | reg = <0x110000 0x1000>; |
| 181 | interrupts = <0 1 0>; | 182 | interrupts = <0 1 0>; |
| 182 | clocks = <&clock 21>; | 183 | clocks = <&clock CLK_B_125>; |
| 183 | clock-names = "watchdog"; | 184 | clock-names = "watchdog"; |
| 184 | }; | 185 | }; |
| 185 | 186 | ||
| @@ -190,7 +191,7 @@ | |||
| 190 | interrupts = <0 31 4>; | 191 | interrupts = <0 31 4>; |
| 191 | interrupt-names = "macirq"; | 192 | interrupt-names = "macirq"; |
| 192 | phy-mode = "sgmii"; | 193 | phy-mode = "sgmii"; |
| 193 | clocks = <&clock 25>; | 194 | clocks = <&clock CLK_GMAC0>; |
| 194 | clock-names = "stmmaceth"; | 195 | clock-names = "stmmaceth"; |
| 195 | }; | 196 | }; |
| 196 | 197 | ||
| @@ -206,7 +207,7 @@ | |||
| 206 | compatible = "samsung,s3c6410-rtc"; | 207 | compatible = "samsung,s3c6410-rtc"; |
| 207 | reg = <0x130000 0x1000>; | 208 | reg = <0x130000 0x1000>; |
| 208 | interrupts = <0 17 0>, <0 16 0>; | 209 | interrupts = <0 17 0>, <0 16 0>; |
| 209 | clocks = <&clock 21>; | 210 | clocks = <&clock CLK_B_125>; |
| 210 | clock-names = "rtc"; | 211 | clock-names = "rtc"; |
| 211 | }; | 212 | }; |
| 212 | 213 | ||
| @@ -214,7 +215,7 @@ | |||
| 214 | compatible = "samsung,exynos5440-tmu"; | 215 | compatible = "samsung,exynos5440-tmu"; |
| 215 | reg = <0x160118 0x230>, <0x160368 0x10>; | 216 | reg = <0x160118 0x230>, <0x160368 0x10>; |
| 216 | interrupts = <0 58 0>; | 217 | interrupts = <0 58 0>; |
| 217 | clocks = <&clock 21>; | 218 | clocks = <&clock CLK_B_125>; |
| 218 | clock-names = "tmu_apbif"; | 219 | clock-names = "tmu_apbif"; |
| 219 | }; | 220 | }; |
| 220 | 221 | ||
| @@ -222,7 +223,7 @@ | |||
| 222 | compatible = "samsung,exynos5440-tmu"; | 223 | compatible = "samsung,exynos5440-tmu"; |
| 223 | reg = <0x16011C 0x230>, <0x160368 0x10>; | 224 | reg = <0x16011C 0x230>, <0x160368 0x10>; |
| 224 | interrupts = <0 58 0>; | 225 | interrupts = <0 58 0>; |
| 225 | clocks = <&clock 21>; | 226 | clocks = <&clock CLK_B_125>; |
| 226 | clock-names = "tmu_apbif"; | 227 | clock-names = "tmu_apbif"; |
| 227 | }; | 228 | }; |
| 228 | 229 | ||
| @@ -230,7 +231,7 @@ | |||
| 230 | compatible = "samsung,exynos5440-tmu"; | 231 | compatible = "samsung,exynos5440-tmu"; |
| 231 | reg = <0x160120 0x230>, <0x160368 0x10>; | 232 | reg = <0x160120 0x230>, <0x160368 0x10>; |
| 232 | interrupts = <0 58 0>; | 233 | interrupts = <0 58 0>; |
| 233 | clocks = <&clock 21>; | 234 | clocks = <&clock CLK_B_125>; |
| 234 | clock-names = "tmu_apbif"; | 235 | clock-names = "tmu_apbif"; |
| 235 | }; | 236 | }; |
| 236 | 237 | ||
| @@ -238,7 +239,7 @@ | |||
| 238 | compatible = "snps,exynos5440-ahci"; | 239 | compatible = "snps,exynos5440-ahci"; |
| 239 | reg = <0x210000 0x10000>; | 240 | reg = <0x210000 0x10000>; |
| 240 | interrupts = <0 30 0>; | 241 | interrupts = <0 30 0>; |
| 241 | clocks = <&clock 23>; | 242 | clocks = <&clock CLK_SATA>; |
| 242 | clock-names = "sata"; | 243 | clock-names = "sata"; |
| 243 | }; | 244 | }; |
| 244 | 245 | ||
| @@ -246,7 +247,7 @@ | |||
| 246 | compatible = "samsung,exynos5440-ohci"; | 247 | compatible = "samsung,exynos5440-ohci"; |
| 247 | reg = <0x220000 0x1000>; | 248 | reg = <0x220000 0x1000>; |
| 248 | interrupts = <0 29 0>; | 249 | interrupts = <0 29 0>; |
| 249 | clocks = <&clock 24>; | 250 | clocks = <&clock CLK_USB>; |
| 250 | clock-names = "usbhost"; | 251 | clock-names = "usbhost"; |
| 251 | }; | 252 | }; |
| 252 | 253 | ||
| @@ -254,7 +255,7 @@ | |||
| 254 | compatible = "samsung,exynos5440-ehci"; | 255 | compatible = "samsung,exynos5440-ehci"; |
| 255 | reg = <0x221000 0x1000>; | 256 | reg = <0x221000 0x1000>; |
| 256 | interrupts = <0 29 0>; | 257 | interrupts = <0 29 0>; |
| 257 | clocks = <&clock 24>; | 258 | clocks = <&clock CLK_USB>; |
| 258 | clock-names = "usbhost"; | 259 | clock-names = "usbhost"; |
| 259 | }; | 260 | }; |
| 260 | 261 | ||
| @@ -264,7 +265,7 @@ | |||
| 264 | 0x270000 0x1000 | 265 | 0x270000 0x1000 |
| 265 | 0x271000 0x40>; | 266 | 0x271000 0x40>; |
| 266 | interrupts = <0 20 0>, <0 21 0>, <0 22 0>; | 267 | interrupts = <0 20 0>, <0 21 0>, <0 22 0>; |
| 267 | clocks = <&clock 28>, <&clock 27>; | 268 | clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>; |
| 268 | clock-names = "pcie", "pcie_bus"; | 269 | clock-names = "pcie", "pcie_bus"; |
| 269 | #address-cells = <3>; | 270 | #address-cells = <3>; |
| 270 | #size-cells = <2>; | 271 | #size-cells = <2>; |
| @@ -285,7 +286,7 @@ | |||
| 285 | 0x272000 0x1000 | 286 | 0x272000 0x1000 |
| 286 | 0x271040 0x40>; | 287 | 0x271040 0x40>; |
| 287 | interrupts = <0 23 0>, <0 24 0>, <0 25 0>; | 288 | interrupts = <0 23 0>, <0 24 0>, <0 25 0>; |
| 288 | clocks = <&clock 29>, <&clock 27>; | 289 | clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>; |
| 289 | clock-names = "pcie", "pcie_bus"; | 290 | clock-names = "pcie", "pcie_bus"; |
| 290 | #address-cells = <3>; | 291 | #address-cells = <3>; |
| 291 | #size-cells = <2>; | 292 | #size-cells = <2>; |
diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts index 1f026adefd45..a33f66c11b73 100644 --- a/arch/arm/boot/dts/imx23-evk.dts +++ b/arch/arm/boot/dts/imx23-evk.dts | |||
| @@ -127,17 +127,21 @@ | |||
| 127 | 127 | ||
| 128 | regulators { | 128 | regulators { |
| 129 | compatible = "simple-bus"; | 129 | compatible = "simple-bus"; |
| 130 | #address-cells = <1>; | ||
| 131 | #size-cells = <0>; | ||
| 130 | 132 | ||
| 131 | reg_vddio_sd0: vddio-sd0 { | 133 | reg_vddio_sd0: regulator@0 { |
| 132 | compatible = "regulator-fixed"; | 134 | compatible = "regulator-fixed"; |
| 135 | reg = <0>; | ||
| 133 | regulator-name = "vddio-sd0"; | 136 | regulator-name = "vddio-sd0"; |
| 134 | regulator-min-microvolt = <3300000>; | 137 | regulator-min-microvolt = <3300000>; |
| 135 | regulator-max-microvolt = <3300000>; | 138 | regulator-max-microvolt = <3300000>; |
| 136 | gpio = <&gpio1 29 0>; | 139 | gpio = <&gpio1 29 0>; |
| 137 | }; | 140 | }; |
| 138 | 141 | ||
| 139 | reg_lcd_3v3: lcd-3v3 { | 142 | reg_lcd_3v3: regulator@1 { |
| 140 | compatible = "regulator-fixed"; | 143 | compatible = "regulator-fixed"; |
| 144 | reg = <1>; | ||
| 141 | regulator-name = "lcd-3v3"; | 145 | regulator-name = "lcd-3v3"; |
| 142 | regulator-min-microvolt = <3300000>; | 146 | regulator-min-microvolt = <3300000>; |
| 143 | regulator-max-microvolt = <3300000>; | 147 | regulator-max-microvolt = <3300000>; |
diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts index 526bfdbd87f9..7e6eef2488e8 100644 --- a/arch/arm/boot/dts/imx23-olinuxino.dts +++ b/arch/arm/boot/dts/imx23-olinuxino.dts | |||
| @@ -100,9 +100,12 @@ | |||
| 100 | 100 | ||
| 101 | regulators { | 101 | regulators { |
| 102 | compatible = "simple-bus"; | 102 | compatible = "simple-bus"; |
| 103 | #address-cells = <1>; | ||
| 104 | #size-cells = <0>; | ||
| 103 | 105 | ||
| 104 | reg_usb0_vbus: usb0_vbus { | 106 | reg_usb0_vbus: regulator@0 { |
| 105 | compatible = "regulator-fixed"; | 107 | compatible = "regulator-fixed"; |
| 108 | reg = <0>; | ||
| 106 | regulator-name = "usb0_vbus"; | 109 | regulator-name = "usb0_vbus"; |
| 107 | regulator-min-microvolt = <5000000>; | 110 | regulator-min-microvolt = <5000000>; |
| 108 | regulator-max-microvolt = <5000000>; | 111 | regulator-max-microvolt = <5000000>; |
diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/imx23-stmp378x_devb.dts index cb64e2b191ea..455169e99d49 100644 --- a/arch/arm/boot/dts/imx23-stmp378x_devb.dts +++ b/arch/arm/boot/dts/imx23-stmp378x_devb.dts | |||
| @@ -66,9 +66,12 @@ | |||
| 66 | 66 | ||
| 67 | regulators { | 67 | regulators { |
| 68 | compatible = "simple-bus"; | 68 | compatible = "simple-bus"; |
| 69 | #address-cells = <1>; | ||
| 70 | #size-cells = <0>; | ||
| 69 | 71 | ||
| 70 | reg_vddio_sd0: vddio-sd0 { | 72 | reg_vddio_sd0: regulator@0 { |
| 71 | compatible = "regulator-fixed"; | 73 | compatible = "regulator-fixed"; |
| 74 | reg = <0>; | ||
| 72 | regulator-name = "vddio-sd0"; | 75 | regulator-name = "vddio-sd0"; |
| 73 | regulator-min-microvolt = <3300000>; | 76 | regulator-min-microvolt = <3300000>; |
| 74 | regulator-max-microvolt = <3300000>; | 77 | regulator-max-microvolt = <3300000>; |
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index 581b75433be6..bbcfb5a19c77 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi | |||
| @@ -23,6 +23,7 @@ | |||
| 23 | serial1 = &auart1; | 23 | serial1 = &auart1; |
| 24 | spi0 = &ssp0; | 24 | spi0 = &ssp0; |
| 25 | spi1 = &ssp1; | 25 | spi1 = &ssp1; |
| 26 | usbphy0 = &usbphy0; | ||
| 26 | }; | 27 | }; |
| 27 | 28 | ||
| 28 | cpus { | 29 | cpus { |
| @@ -428,7 +429,7 @@ | |||
| 428 | status = "disabled"; | 429 | status = "disabled"; |
| 429 | }; | 430 | }; |
| 430 | 431 | ||
| 431 | lradc@80050000 { | 432 | lradc: lradc@80050000 { |
| 432 | compatible = "fsl,imx23-lradc"; | 433 | compatible = "fsl,imx23-lradc"; |
| 433 | reg = <0x80050000 0x2000>; | 434 | reg = <0x80050000 0x2000>; |
| 434 | interrupts = <36 37 38 39 40 41 42 43 44>; | 435 | interrupts = <36 37 38 39 40 41 42 43 44>; |
| @@ -526,4 +527,9 @@ | |||
| 526 | status = "disabled"; | 527 | status = "disabled"; |
| 527 | }; | 528 | }; |
| 528 | }; | 529 | }; |
| 530 | |||
| 531 | iio_hwmon { | ||
| 532 | compatible = "iio-hwmon"; | ||
| 533 | io-channels = <&lradc 8>; | ||
| 534 | }; | ||
| 529 | }; | 535 | }; |
diff --git a/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi b/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi new file mode 100644 index 000000000000..d6f27641c0ef --- /dev/null +++ b/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi | |||
| @@ -0,0 +1,73 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Eukréa Electromatique <denis@eukrea.com> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation; either version 2 | ||
| 7 | * of the License, or (at your option) any later version. | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include "imx25.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Eukrea CPUIMX25"; | ||
| 18 | compatible = "eukrea,cpuimx25", "fsl,imx25"; | ||
| 19 | |||
| 20 | memory { | ||
| 21 | reg = <0x80000000 0x4000000>; /* 64M */ | ||
| 22 | }; | ||
| 23 | }; | ||
| 24 | |||
| 25 | &fec { | ||
| 26 | phy-mode = "rmii"; | ||
| 27 | pinctrl-names = "default"; | ||
| 28 | pinctrl-0 = <&pinctrl_fec>; | ||
| 29 | status = "okay"; | ||
| 30 | }; | ||
| 31 | |||
| 32 | &i2c1 { | ||
| 33 | pinctrl-names = "default"; | ||
| 34 | pinctrl-0 = <&pinctrl_i2c1>; | ||
| 35 | status = "okay"; | ||
| 36 | |||
| 37 | pcf8563@51 { | ||
| 38 | compatible = "nxp,pcf8563"; | ||
| 39 | reg = <0x51>; | ||
| 40 | }; | ||
| 41 | }; | ||
| 42 | |||
| 43 | &iomuxc { | ||
| 44 | imx25-eukrea-cpuimx25 { | ||
| 45 | pinctrl_fec: fecgrp { | ||
| 46 | fsl,pins = < | ||
| 47 | MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 | ||
| 48 | MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0 | ||
| 49 | MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 | ||
| 50 | MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 | ||
| 51 | MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 | ||
| 52 | MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 | ||
| 53 | MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 | ||
| 54 | MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 | ||
| 55 | MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0 | ||
| 56 | >; | ||
| 57 | }; | ||
| 58 | |||
| 59 | pinctrl_i2c1: i2c1grp { | ||
| 60 | fsl,pins = < | ||
| 61 | MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000 | ||
| 62 | MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000 | ||
| 63 | >; | ||
| 64 | }; | ||
| 65 | }; | ||
| 66 | }; | ||
| 67 | |||
| 68 | &nfc { | ||
| 69 | nand-bus-width = <8>; | ||
| 70 | nand-ecc-mode = "hw"; | ||
| 71 | nand-on-flash-bbt; | ||
| 72 | status = "okay"; | ||
| 73 | }; | ||
diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts new file mode 100644 index 000000000000..62fb3da50bdb --- /dev/null +++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts | |||
| @@ -0,0 +1,174 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Eukréa Electromatique <denis@eukrea.com> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation; either version 2 | ||
| 7 | * of the License, or (at your option) any later version. | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | */ | ||
| 13 | |||
| 14 | /dts-v1/; | ||
| 15 | |||
| 16 | #include <dt-bindings/gpio/gpio.h> | ||
| 17 | #include <dt-bindings/input/input.h> | ||
| 18 | #include "imx25-eukrea-cpuimx25.dtsi" | ||
| 19 | |||
| 20 | / { | ||
| 21 | model = "Eukrea MBIMXSD25"; | ||
| 22 | compatible = "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25"; | ||
| 23 | |||
| 24 | gpio_keys { | ||
| 25 | compatible = "gpio-keys"; | ||
| 26 | pinctrl-names = "default"; | ||
| 27 | pinctrl-0 = <&pinctrl_gpiokeys>; | ||
| 28 | |||
| 29 | bp1 { | ||
| 30 | label = "BP1"; | ||
| 31 | gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; | ||
| 32 | linux,code = <BTN_MISC>; | ||
| 33 | gpio-key,wakeup; | ||
| 34 | }; | ||
| 35 | }; | ||
| 36 | |||
| 37 | leds { | ||
| 38 | compatible = "gpio-leds"; | ||
| 39 | pinctrl-names = "default"; | ||
| 40 | pinctrl-0 = <&pinctrl_gpioled>; | ||
| 41 | |||
| 42 | led1 { | ||
| 43 | label = "led1"; | ||
| 44 | gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; | ||
| 45 | linux,default-trigger = "heartbeat"; | ||
| 46 | }; | ||
| 47 | }; | ||
| 48 | |||
| 49 | sound { | ||
| 50 | compatible = "eukrea,asoc-tlv320"; | ||
| 51 | eukrea,model = "imx25-eukrea-tlv320aic23"; | ||
| 52 | ssi-controller = <&ssi1>; | ||
| 53 | fsl,mux-int-port = <1>; | ||
| 54 | fsl,mux-ext-port = <5>; | ||
| 55 | }; | ||
| 56 | }; | ||
| 57 | |||
| 58 | &audmux { | ||
| 59 | pinctrl-names = "default"; | ||
| 60 | pinctrl-0 = <&pinctrl_audmux>; | ||
| 61 | status = "okay"; | ||
| 62 | }; | ||
| 63 | |||
| 64 | &esdhc1 { | ||
| 65 | pinctrl-names = "default"; | ||
| 66 | pinctrl-0 = <&pinctrl_esdhc1>; | ||
| 67 | cd-gpios = <&gpio1 20>; | ||
| 68 | status = "okay"; | ||
| 69 | }; | ||
| 70 | |||
| 71 | &i2c1 { | ||
| 72 | tlv320aic23: codec@1a { | ||
| 73 | compatible = "ti,tlv320aic23"; | ||
| 74 | reg = <0x1a>; | ||
| 75 | }; | ||
| 76 | }; | ||
| 77 | |||
| 78 | &iomuxc { | ||
| 79 | imx25-eukrea-mbimxsd25-baseboard { | ||
| 80 | pinctrl_audmux: audmuxgrp { | ||
| 81 | fsl,pins = < | ||
| 82 | MX25_PAD_KPP_COL3__AUD5_TXFS 0xe0 | ||
| 83 | MX25_PAD_KPP_COL2__AUD5_TXC 0xe0 | ||
| 84 | MX25_PAD_KPP_COL1__AUD5_RXD 0xe0 | ||
| 85 | MX25_PAD_KPP_COL0__AUD5_TXD 0xe0 | ||
| 86 | >; | ||
| 87 | }; | ||
| 88 | |||
| 89 | pinctrl_esdhc1: esdhc1grp { | ||
| 90 | fsl,pins = < | ||
| 91 | MX25_PAD_SD1_CMD__SD1_CMD 0x400000c0 | ||
| 92 | MX25_PAD_SD1_CLK__SD1_CLK 0x400000c0 | ||
| 93 | MX25_PAD_SD1_DATA0__SD1_DATA0 0x400000c0 | ||
| 94 | MX25_PAD_SD1_DATA1__SD1_DATA1 0x400000c0 | ||
| 95 | MX25_PAD_SD1_DATA2__SD1_DATA2 0x400000c0 | ||
| 96 | MX25_PAD_SD1_DATA3__SD1_DATA3 0x400000c0 | ||
| 97 | >; | ||
| 98 | }; | ||
| 99 | |||
| 100 | pinctrl_gpiokeys: gpiokeysgrp { | ||
| 101 | fsl,pins = <MX25_PAD_VSTBY_ACK__GPIO_3_18 0x80000000>; | ||
| 102 | }; | ||
| 103 | |||
| 104 | pinctrl_gpioled: gpioledgrp { | ||
| 105 | fsl,pins = <MX25_PAD_POWER_FAIL__GPIO_3_19 0x80000000>; | ||
| 106 | }; | ||
| 107 | |||
| 108 | pinctrl_lcdc: lcdcgrp { | ||
| 109 | fsl,pins = < | ||
| 110 | MX25_PAD_LD0__LD0 0x1 | ||
| 111 | MX25_PAD_LD1__LD1 0x1 | ||
| 112 | MX25_PAD_LD2__LD2 0x1 | ||
| 113 | MX25_PAD_LD3__LD3 0x1 | ||
| 114 | MX25_PAD_LD4__LD4 0x1 | ||
| 115 | MX25_PAD_LD5__LD5 0x1 | ||
| 116 | MX25_PAD_LD6__LD6 0x1 | ||
| 117 | MX25_PAD_LD7__LD7 0x1 | ||
| 118 | MX25_PAD_LD8__LD8 0x1 | ||
| 119 | MX25_PAD_LD9__LD9 0x1 | ||
| 120 | MX25_PAD_LD10__LD10 0x1 | ||
| 121 | MX25_PAD_LD11__LD11 0x1 | ||
| 122 | MX25_PAD_LD12__LD12 0x1 | ||
| 123 | MX25_PAD_LD13__LD13 0x1 | ||
| 124 | MX25_PAD_LD14__LD14 0x1 | ||
| 125 | MX25_PAD_LD15__LD15 0x1 | ||
| 126 | MX25_PAD_GPIO_E__LD16 0x1 | ||
| 127 | MX25_PAD_GPIO_F__LD17 0x1 | ||
| 128 | MX25_PAD_HSYNC__HSYNC 0x80000000 | ||
| 129 | MX25_PAD_VSYNC__VSYNC 0x80000000 | ||
| 130 | MX25_PAD_LSCLK__LSCLK 0x80000000 | ||
| 131 | MX25_PAD_OE_ACD__OE_ACD 0x80000000 | ||
| 132 | MX25_PAD_CONTRAST__CONTRAST 0x80000000 | ||
| 133 | >; | ||
| 134 | }; | ||
| 135 | |||
| 136 | pinctrl_uart1: uart1grp { | ||
| 137 | fsl,pins = < | ||
| 138 | MX25_PAD_UART1_RTS__UART1_RTS 0xe0 | ||
| 139 | MX25_PAD_UART1_CTS__UART1_CTS 0xe0 | ||
| 140 | MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 | ||
| 141 | MX25_PAD_UART1_RXD__UART1_RXD 0xc0 | ||
| 142 | >; | ||
| 143 | }; | ||
| 144 | |||
| 145 | pinctrl_uart2: uart2grp { | ||
| 146 | fsl,pins = < | ||
| 147 | MX25_PAD_UART2_RXD__UART2_RXD 0x80000000 | ||
| 148 | MX25_PAD_UART2_TXD__UART2_TXD 0x80000000 | ||
| 149 | MX25_PAD_UART2_RTS__UART2_RTS 0x80000000 | ||
| 150 | MX25_PAD_UART2_CTS__UART2_CTS 0x80000000 | ||
| 151 | >; | ||
| 152 | }; | ||
| 153 | }; | ||
| 154 | }; | ||
| 155 | |||
| 156 | &ssi1 { | ||
| 157 | codec-handle = <&tlv320aic23>; | ||
| 158 | fsl,mode = "i2s-slave"; | ||
| 159 | status = "okay"; | ||
| 160 | }; | ||
| 161 | |||
| 162 | &uart1 { | ||
| 163 | pinctrl-names = "default"; | ||
| 164 | pinctrl-0 = <&pinctrl_uart1>; | ||
| 165 | fsl,uart-has-rtscts; | ||
| 166 | status = "okay"; | ||
| 167 | }; | ||
| 168 | |||
| 169 | &uart2 { | ||
| 170 | pinctrl-names = "default"; | ||
| 171 | pinctrl-0 = <&pinctrl_uart2>; | ||
| 172 | fsl,uart-has-rtscts; | ||
| 173 | status = "okay"; | ||
| 174 | }; | ||
diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h new file mode 100644 index 000000000000..9238a95d8e62 --- /dev/null +++ b/arch/arm/boot/dts/imx25-pinfunc.h | |||
| @@ -0,0 +1,494 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Eukréa Electromatique <denis@eukrea.com> | ||
| 3 | * Based on imx35-pinfunc.h in the same directory Which is: | ||
| 4 | * Copyright 2013 Freescale Semiconductor, Inc. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __DTS_IMX25_PINFUNC_H | ||
| 13 | #define __DTS_IMX25_PINFUNC_H | ||
| 14 | |||
| 15 | /* | ||
| 16 | * The pin function ID is a tuple of | ||
| 17 | * <mux_reg conf_reg input_reg mux_mode input_val> | ||
| 18 | */ | ||
| 19 | |||
| 20 | #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000 | ||
| 21 | #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000 | ||
| 22 | |||
| 23 | #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000 | ||
| 24 | #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000 | ||
| 25 | |||
| 26 | #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x10 0x000 | ||
| 27 | #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x15 0x000 | ||
| 28 | |||
| 29 | #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x10 0x000 | ||
| 30 | #define MX25_PAD_A15__GPIO_2_1 0x014 0x234 0x000 0x15 0x000 | ||
| 31 | |||
| 32 | #define MX25_PAD_A16__A16 0x018 0x000 0x000 0x10 0x000 | ||
| 33 | #define MX25_PAD_A16__GPIO_2_2 0x018 0x000 0x000 0x15 0x000 | ||
| 34 | |||
| 35 | #define MX25_PAD_A17__A17 0x01c 0x238 0x000 0x10 0x000 | ||
| 36 | #define MX25_PAD_A17__GPIO_2_3 0x01c 0x238 0x000 0x15 0x000 | ||
| 37 | |||
| 38 | #define MX25_PAD_A18__A18 0x020 0x23c 0x000 0x10 0x000 | ||
| 39 | #define MX25_PAD_A18__GPIO_2_4 0x020 0x23c 0x000 0x15 0x000 | ||
| 40 | #define MX25_PAD_A18__FEC_COL 0x020 0x23c 0x504 0x17 0x000 | ||
| 41 | |||
| 42 | #define MX25_PAD_A19__A19 0x024 0x240 0x000 0x10 0x000 | ||
| 43 | #define MX25_PAD_A19__FEC_RX_ER 0x024 0x240 0x518 0x17 0x000 | ||
| 44 | #define MX25_PAD_A19__GPIO_2_5 0x024 0x240 0x000 0x15 0x000 | ||
| 45 | |||
| 46 | #define MX25_PAD_A20__A20 0x028 0x244 0x000 0x10 0x000 | ||
| 47 | #define MX25_PAD_A20__GPIO_2_6 0x028 0x244 0x000 0x15 0x000 | ||
| 48 | #define MX25_PAD_A20__FEC_RDATA2 0x028 0x244 0x50c 0x17 0x000 | ||
| 49 | |||
| 50 | #define MX25_PAD_A21__A21 0x02c 0x248 0x000 0x10 0x000 | ||
| 51 | #define MX25_PAD_A21__GPIO_2_7 0x02c 0x248 0x000 0x15 0x000 | ||
| 52 | #define MX25_PAD_A21__FEC_RDATA3 0x02c 0x248 0x510 0x17 0x000 | ||
| 53 | |||
| 54 | #define MX25_PAD_A22__A22 0x030 0x000 0x000 0x10 0x000 | ||
| 55 | #define MX25_PAD_A22__GPIO_2_8 0x030 0x000 0x000 0x15 0x000 | ||
| 56 | |||
| 57 | #define MX25_PAD_A23__A23 0x034 0x24c 0x000 0x10 0x000 | ||
| 58 | #define MX25_PAD_A23__GPIO_2_9 0x034 0x24c 0x000 0x15 0x000 | ||
| 59 | |||
| 60 | #define MX25_PAD_A24__A24 0x038 0x250 0x000 0x10 0x000 | ||
| 61 | #define MX25_PAD_A24__GPIO_2_10 0x038 0x250 0x000 0x15 0x000 | ||
| 62 | #define MX25_PAD_A24__FEC_RX_CLK 0x038 0x250 0x514 0x17 0x000 | ||
| 63 | |||
| 64 | #define MX25_PAD_A25__A25 0x03c 0x254 0x000 0x10 0x000 | ||
| 65 | #define MX25_PAD_A25__GPIO_2_11 0x03c 0x254 0x000 0x15 0x000 | ||
| 66 | #define MX25_PAD_A25__FEC_CRS 0x03c 0x254 0x508 0x17 0x000 | ||
| 67 | |||
| 68 | #define MX25_PAD_EB0__EB0 0x040 0x258 0x000 0x10 0x000 | ||
| 69 | #define MX25_PAD_EB0__AUD4_TXD 0x040 0x258 0x464 0x14 0x000 | ||
| 70 | #define MX25_PAD_EB0__GPIO_2_12 0x040 0x258 0x000 0x15 0x000 | ||
| 71 | |||
| 72 | #define MX25_PAD_EB1__EB1 0x044 0x25c 0x000 0x10 0x000 | ||
| 73 | #define MX25_PAD_EB1__AUD4_RXD 0x044 0x25c 0x460 0x14 0x000 | ||
| 74 | #define MX25_PAD_EB1__GPIO_2_13 0x044 0x25c 0x000 0x15 0x000 | ||
| 75 | |||
| 76 | #define MX25_PAD_OE__OE 0x048 0x260 0x000 0x10 0x000 | ||
| 77 | #define MX25_PAD_OE__AUD4_TXC 0x048 0x260 0x000 0x14 0x000 | ||
| 78 | #define MX25_PAD_OE__GPIO_2_14 0x048 0x260 0x000 0x15 0x000 | ||
| 79 | |||
| 80 | #define MX25_PAD_CS0__CS0 0x04c 0x000 0x000 0x00 0x000 | ||
| 81 | #define MX25_PAD_CS0__GPIO_4_2 0x04c 0x000 0x000 0x05 0x000 | ||
| 82 | |||
| 83 | #define MX25_PAD_CS1__CS1 0x050 0x000 0x000 0x00 0x000 | ||
| 84 | #define MX25_PAD_CS1__NF_CE3 0x050 0x000 0x000 0x01 0x000 | ||
| 85 | #define MX25_PAD_CS1__GPIO_4_3 0x050 0x000 0x000 0x05 0x000 | ||
| 86 | |||
| 87 | #define MX25_PAD_CS4__CS4 0x054 0x264 0x000 0x10 0x000 | ||
| 88 | #define MX25_PAD_CS4__NF_CE1 0x054 0x264 0x000 0x01 0x000 | ||
| 89 | #define MX25_PAD_CS4__UART5_CTS 0x054 0x264 0x000 0x13 0x000 | ||
| 90 | #define MX25_PAD_CS4__GPIO_3_20 0x054 0x264 0x000 0x15 0x000 | ||
| 91 | |||
| 92 | #define MX25_PAD_CS5__CS5 0x058 0x268 0x000 0x10 0x000 | ||
| 93 | #define MX25_PAD_CS5__NF_CE2 0x058 0x268 0x000 0x01 0x000 | ||
| 94 | #define MX25_PAD_CS5__UART5_RTS 0x058 0x268 0x574 0x13 0x000 | ||
| 95 | #define MX25_PAD_CS5__GPIO_3_21 0x058 0x268 0x000 0x15 0x000 | ||
| 96 | |||
| 97 | #define MX25_PAD_NF_CE0__NF_CE0 0x05c 0x26c 0x000 0x10 0x000 | ||
| 98 | #define MX25_PAD_NF_CE0__GPIO_3_22 0x05c 0x26c 0x000 0x15 0x000 | ||
| 99 | |||
| 100 | #define MX25_PAD_ECB__ECB 0x060 0x270 0x000 0x10 0x000 | ||
| 101 | #define MX25_PAD_ECB__UART5_TXD_MUX 0x060 0x270 0x000 0x13 0x000 | ||
| 102 | #define MX25_PAD_ECB__GPIO_3_23 0x060 0x270 0x000 0x15 0x000 | ||
| 103 | |||
| 104 | #define MX25_PAD_LBA__LBA 0x064 0x274 0x000 0x10 0x000 | ||
| 105 | #define MX25_PAD_LBA__UART5_RXD_MUX 0x064 0x274 0x578 0x13 0x000 | ||
| 106 | #define MX25_PAD_LBA__GPIO_3_24 0x064 0x274 0x000 0x15 0x000 | ||
| 107 | |||
| 108 | #define MX25_PAD_BCLK__BCLK 0x068 0x000 0x000 0x00 0x000 | ||
| 109 | #define MX25_PAD_BCLK__GPIO_4_4 0x068 0x000 0x000 0x05 0x000 | ||
| 110 | |||
| 111 | #define MX25_PAD_RW__RW 0x06c 0x278 0x000 0x10 0x000 | ||
| 112 | #define MX25_PAD_RW__AUD4_TXFS 0x06c 0x278 0x474 0x14 0x000 | ||
| 113 | #define MX25_PAD_RW__GPIO_3_25 0x06c 0x278 0x000 0x15 0x000 | ||
| 114 | |||
| 115 | #define MX25_PAD_NFWE_B__NFWE_B 0x070 0x000 0x000 0x10 0x000 | ||
| 116 | #define MX25_PAD_NFWE_B__GPIO_3_26 0x070 0x000 0x000 0x15 0x000 | ||
| 117 | |||
| 118 | #define MX25_PAD_NFRE_B__NFRE_B 0x074 0x000 0x000 0x10 0x000 | ||
| 119 | #define MX25_PAD_NFRE_B__GPIO_3_27 0x074 0x000 0x000 0x15 0x000 | ||
| 120 | |||
| 121 | #define MX25_PAD_NFALE__NFALE 0x078 0x000 0x000 0x10 0x000 | ||
| 122 | #define MX25_PAD_NFALE__GPIO_3_28 0x078 0x000 0x000 0x15 0x000 | ||
| 123 | |||
| 124 | #define MX25_PAD_NFCLE__NFCLE 0x07c 0x000 0x000 0x10 0x000 | ||
| 125 | #define MX25_PAD_NFCLE__GPIO_3_29 0x07c 0x000 0x000 0x15 0x000 | ||
| 126 | |||
| 127 | #define MX25_PAD_NFWP_B__NFWP_B 0x080 0x000 0x000 0x10 0x000 | ||
| 128 | #define MX25_PAD_NFWP_B__GPIO_3_30 0x080 0x000 0x000 0x15 0x000 | ||
| 129 | |||
| 130 | #define MX25_PAD_NFRB__NFRB 0x084 0x27c 0x000 0x10 0x000 | ||
| 131 | #define MX25_PAD_NFRB__GPIO_3_31 0x084 0x27c 0x000 0x15 0x000 | ||
| 132 | |||
| 133 | #define MX25_PAD_D15__D15 0x088 0x280 0x000 0x00 0x000 | ||
| 134 | #define MX25_PAD_D15__LD16 0x088 0x280 0x000 0x01 0x000 | ||
| 135 | #define MX25_PAD_D15__GPIO_4_5 0x088 0x280 0x000 0x05 0x000 | ||
| 136 | |||
| 137 | #define MX25_PAD_D14__D14 0x08c 0x284 0x000 0x00 0x000 | ||
| 138 | #define MX25_PAD_D14__LD17 0x08c 0x284 0x000 0x01 0x000 | ||
| 139 | #define MX25_PAD_D14__GPIO_4_6 0x08c 0x284 0x000 0x05 0x000 | ||
| 140 | |||
| 141 | #define MX25_PAD_D13__D13 0x090 0x288 0x000 0x00 0x000 | ||
| 142 | #define MX25_PAD_D13__LD18 0x090 0x288 0x000 0x01 0x000 | ||
| 143 | #define MX25_PAD_D13__GPIO_4_7 0x090 0x288 0x000 0x05 0x000 | ||
| 144 | |||
| 145 | #define MX25_PAD_D12__D12 0x094 0x28c 0x000 0x00 0x000 | ||
| 146 | #define MX25_PAD_D12__GPIO_4_8 0x094 0x28c 0x000 0x05 0x000 | ||
| 147 | |||
| 148 | #define MX25_PAD_D11__D11 0x098 0x290 0x000 0x00 0x000 | ||
| 149 | #define MX25_PAD_D11__GPIO_4_9 0x098 0x290 0x000 0x05 0x000 | ||
| 150 | |||
| 151 | #define MX25_PAD_D10__D10 0x09c 0x294 0x000 0x00 0x000 | ||
| 152 | #define MX25_PAD_D10__GPIO_4_10 0x09c 0x294 0x000 0x05 0x000 | ||
| 153 | #define MX25_PAD_D10__USBOTG_OC 0x09c 0x294 0x57c 0x06 0x000 | ||
| 154 | |||
| 155 | #define MX25_PAD_D9__D9 0x0a0 0x298 0x000 0x00 0x000 | ||
| 156 | #define MX25_PAD_D9__GPIO_4_11 0x0a0 0x298 0x000 0x05 0x000 | ||
| 157 | #define MX25_PAD_D9__USBH2_PWR 0x0a0 0x298 0x000 0x06 0x000 | ||
| 158 | |||
| 159 | #define MX25_PAD_D8__D8 0x0a4 0x29c 0x000 0x00 0x000 | ||
| 160 | #define MX25_PAD_D8__GPIO_4_12 0x0a4 0x29c 0x000 0x05 0x000 | ||
| 161 | #define MX25_PAD_D8__USBH2_OC 0x0a4 0x29c 0x580 0x06 0x000 | ||
| 162 | |||
| 163 | #define MX25_PAD_D7__D7 0x0a8 0x2a0 0x000 0x00 0x000 | ||
| 164 | #define MX25_PAD_D7__GPIO_4_13 0x0a8 0x2a0 0x000 0x05 0x000 | ||
| 165 | |||
| 166 | #define MX25_PAD_D6__D6 0x0ac 0x2a4 0x000 0x00 0x000 | ||
| 167 | #define MX25_PAD_D6__GPIO_4_14 0x0ac 0x2a4 0x000 0x05 0x000 | ||
| 168 | |||
| 169 | #define MX25_PAD_D5__D5 0x0b0 0x2a8 0x000 0x00 0x000 | ||
| 170 | #define MX25_PAD_D5__GPIO_4_15 0x0b0 0x2a8 0x000 0x05 0x000 | ||
| 171 | |||
| 172 | #define MX25_PAD_D4__D4 0x0b4 0x2ac 0x000 0x00 0x000 | ||
| 173 | #define MX25_PAD_D4__GPIO_4_16 0x0b4 0x2ac 0x000 0x05 0x000 | ||
| 174 | |||
| 175 | #define MX25_PAD_D3__D3 0x0b8 0x2b0 0x000 0x00 0x000 | ||
| 176 | #define MX25_PAD_D3__GPIO_4_17 0x0b8 0x2b0 0x000 0x05 0x000 | ||
| 177 | |||
| 178 | #define MX25_PAD_D2__D2 0x0bc 0x2b4 0x000 0x00 0x000 | ||
| 179 | #define MX25_PAD_D2__GPIO_4_18 0x0bc 0x2b4 0x000 0x05 0x000 | ||
| 180 | |||
| 181 | #define MX25_PAD_D1__D1 0x0c0 0x2b8 0x000 0x00 0x000 | ||
| 182 | #define MX25_PAD_D1__GPIO_4_19 0x0c0 0x2b8 0x000 0x05 0x000 | ||
| 183 | |||
| 184 | #define MX25_PAD_D0__D0 0x0c4 0x2bc 0x000 0x00 0x000 | ||
| 185 | #define MX25_PAD_D0__GPIO_4_20 0x0c4 0x2bc 0x000 0x05 0x000 | ||
| 186 | |||
| 187 | #define MX25_PAD_LD0__LD0 0x0c8 0x2c0 0x000 0x10 0x000 | ||
| 188 | #define MX25_PAD_LD0__CSI_D0 0x0c8 0x2c0 0x488 0x12 0x000 | ||
| 189 | #define MX25_PAD_LD0__GPIO_2_15 0x0c8 0x2c0 0x000 0x15 0x000 | ||
| 190 | |||
| 191 | #define MX25_PAD_LD1__LD1 0x0cc 0x2c4 0x000 0x10 0x000 | ||
| 192 | #define MX25_PAD_LD1__CSI_D1 0x0cc 0x2c4 0x48c 0x12 0x000 | ||
| 193 | #define MX25_PAD_LD1__GPIO_2_16 0x0cc 0x2c4 0x000 0x15 0x000 | ||
| 194 | |||
| 195 | #define MX25_PAD_LD2__LD2 0x0d0 0x2c8 0x000 0x10 0x000 | ||
| 196 | #define MX25_PAD_LD2__GPIO_2_17 0x0d0 0x2c8 0x000 0x15 0x000 | ||
| 197 | |||
| 198 | #define MX25_PAD_LD3__LD3 0x0d4 0x2cc 0x000 0x10 0x000 | ||
| 199 | #define MX25_PAD_LD3__GPIO_2_18 0x0d4 0x2cc 0x000 0x15 0x000 | ||
| 200 | |||
| 201 | #define MX25_PAD_LD4__LD4 0x0d8 0x2d0 0x000 0x10 0x000 | ||
| 202 | #define MX25_PAD_LD4__GPIO_2_19 0x0d8 0x2d0 0x000 0x15 0x000 | ||
| 203 | |||
| 204 | #define MX25_PAD_LD5__LD5 0x0dc 0x2d4 0x000 0x10 0x000 | ||
| 205 | #define MX25_PAD_LD5__GPIO_1_19 0x0dc 0x2d4 0x000 0x15 0x000 | ||
| 206 | |||
| 207 | #define MX25_PAD_LD6__LD6 0x0e0 0x2d8 0x000 0x10 0x000 | ||
| 208 | #define MX25_PAD_LD6__GPIO_1_20 0x0e0 0x2d8 0x000 0x15 0x000 | ||
| 209 | |||
| 210 | #define MX25_PAD_LD7__LD7 0x0e4 0x2dc 0x000 0x10 0x000 | ||
| 211 | #define MX25_PAD_LD7__GPIO_1_21 0x0e4 0x2dc 0x000 0x15 0x000 | ||
| 212 | |||
| 213 | #define MX25_PAD_LD8__LD8 0x0e8 0x2e0 0x000 0x10 0x000 | ||
| 214 | #define MX25_PAD_LD8__FEC_TX_ERR 0x0e8 0x2e0 0x000 0x15 0x000 | ||
| 215 | |||
| 216 | #define MX25_PAD_LD9__LD9 0x0ec 0x2e4 0x000 0x10 0x000 | ||
| 217 | #define MX25_PAD_LD9__FEC_COL 0x0ec 0x2e4 0x504 0x15 0x001 | ||
| 218 | |||
| 219 | #define MX25_PAD_LD10__LD10 0x0f0 0x2e8 0x000 0x10 0x000 | ||
| 220 | #define MX25_PAD_LD10__FEC_RX_ER 0x0f0 0x2e8 0x518 0x15 0x001 | ||
| 221 | |||
| 222 | #define MX25_PAD_LD11__LD11 0x0f4 0x2ec 0x000 0x10 0x000 | ||
| 223 | #define MX25_PAD_LD11__FEC_RDATA2 0x0f4 0x2ec 0x50c 0x15 0x001 | ||
| 224 | |||
| 225 | #define MX25_PAD_LD12__LD12 0x0f8 0x2f0 0x000 0x10 0x000 | ||
| 226 | #define MX25_PAD_LD12__FEC_RDATA3 0x0f8 0x2f0 0x510 0x15 0x001 | ||
| 227 | |||
| 228 | #define MX25_PAD_LD13__LD13 0x0fc 0x2f4 0x000 0x10 0x000 | ||
| 229 | #define MX25_PAD_LD13__FEC_TDATA2 0x0fc 0x2f4 0x000 0x15 0x000 | ||
| 230 | |||
| 231 | #define MX25_PAD_LD14__LD14 0x100 0x2f8 0x000 0x10 0x000 | ||
| 232 | #define MX25_PAD_LD14__FEC_TDATA3 0x100 0x2f8 0x000 0x15 0x000 | ||
| 233 | |||
| 234 | #define MX25_PAD_LD15__LD15 0x104 0x2fc 0x000 0x10 0x000 | ||
| 235 | #define MX25_PAD_LD15__FEC_RX_CLK 0x104 0x2fc 0x514 0x15 0x001 | ||
| 236 | |||
| 237 | #define MX25_PAD_HSYNC__HSYNC 0x108 0x300 0x000 0x10 0x000 | ||
| 238 | #define MX25_PAD_HSYNC__GPIO_1_22 0x108 0x300 0x000 0x15 0x000 | ||
| 239 | |||
| 240 | #define MX25_PAD_VSYNC__VSYNC 0x10c 0x304 0x000 0x10 0x000 | ||
| 241 | #define MX25_PAD_VSYNC__GPIO_1_23 0x10c 0x304 0x000 0x15 0x000 | ||
| 242 | |||
| 243 | #define MX25_PAD_LSCLK__LSCLK 0x110 0x308 0x000 0x10 0x000 | ||
| 244 | #define MX25_PAD_LSCLK__GPIO_1_24 0x110 0x308 0x000 0x15 0x000 | ||
| 245 | |||
| 246 | #define MX25_PAD_OE_ACD__OE_ACD 0x114 0x30c 0x000 0x10 0x000 | ||
| 247 | #define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x15 0x000 | ||
| 248 | |||
| 249 | #define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x10 0x000 | ||
| 250 | #define MX25_PAD_CONTRAST__PWM4_PWMO 0x118 0x310 0x000 0x14 0x000 | ||
| 251 | #define MX25_PAD_CONTRAST__FEC_CRS 0x118 0x310 0x508 0x15 0x001 | ||
| 252 | |||
| 253 | #define MX25_PAD_PWM__PWM 0x11c 0x314 0x000 0x10 0x000 | ||
| 254 | #define MX25_PAD_PWM__GPIO_1_26 0x11c 0x314 0x000 0x15 0x000 | ||
| 255 | #define MX25_PAD_PWM__USBH2_OC 0x11c 0x314 0x580 0x16 0x001 | ||
| 256 | |||
| 257 | #define MX25_PAD_CSI_D2__CSI_D2 0x120 0x318 0x000 0x10 0x000 | ||
| 258 | #define MX25_PAD_CSI_D2__UART5_RXD_MUX 0x120 0x318 0x578 0x11 0x001 | ||
| 259 | #define MX25_PAD_CSI_D2__GPIO_1_27 0x120 0x318 0x000 0x15 0x000 | ||
| 260 | #define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x17 0x000 | ||
| 261 | |||
| 262 | #define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x10 0x000 | ||
| 263 | #define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x15 0x000 | ||
| 264 | #define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x17 0x001 | ||
| 265 | |||
| 266 | #define MX25_PAD_CSI_D4__CSI_D4 0x128 0x320 0x000 0x10 0x000 | ||
| 267 | #define MX25_PAD_CSI_D4__UART5_RTS 0x128 0x320 0x574 0x11 0x001 | ||
| 268 | #define MX25_PAD_CSI_D4__GPIO_1_29 0x128 0x320 0x000 0x15 0x000 | ||
| 269 | #define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x17 0x000 | ||
| 270 | |||
| 271 | #define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x10 0x000 | ||
| 272 | #define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x15 0x000 | ||
| 273 | #define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x17 0x000 | ||
| 274 | |||
| 275 | #define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x10 0x000 | ||
| 276 | #define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x15 0x000 | ||
| 277 | |||
| 278 | #define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x10 0x000 | ||
| 279 | #define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x15 0x000 | ||
| 280 | |||
| 281 | #define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x10 0x000 | ||
| 282 | #define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x15 0x000 | ||
| 283 | |||
| 284 | #define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x10 0x000 | ||
| 285 | #define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x15 0x000 | ||
| 286 | |||
| 287 | #define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x10 0x000 | ||
| 288 | #define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x15 0x000 | ||
| 289 | |||
| 290 | #define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x10 0x000 | ||
| 291 | #define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x15 0x000 | ||
| 292 | |||
| 293 | #define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x10 0x000 | ||
| 294 | #define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x15 0x000 | ||
| 295 | |||
| 296 | #define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x10 0x000 | ||
| 297 | #define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x15 0x000 | ||
| 298 | |||
| 299 | #define MX25_PAD_I2C1_CLK__I2C1_CLK 0x150 0x348 0x000 0x10 0x000 | ||
| 300 | #define MX25_PAD_I2C1_CLK__GPIO_1_12 0x150 0x348 0x000 0x15 0x000 | ||
| 301 | |||
| 302 | #define MX25_PAD_I2C1_DAT__I2C1_DAT 0x154 0x34c 0x000 0x10 0x000 | ||
| 303 | #define MX25_PAD_I2C1_DAT__GPIO_1_13 0x154 0x34c 0x000 0x15 0x000 | ||
| 304 | |||
| 305 | #define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI 0x158 0x350 0x000 0x10 0x000 | ||
| 306 | #define MX25_PAD_CSPI1_MOSI__GPIO_1_14 0x158 0x350 0x000 0x15 0x000 | ||
| 307 | |||
| 308 | #define MX25_PAD_CSPI1_MISO__CSPI1_MISO 0x15c 0x354 0x000 0x10 0x000 | ||
| 309 | #define MX25_PAD_CSPI1_MISO__GPIO_1_15 0x15c 0x354 0x000 0x15 0x000 | ||
| 310 | |||
| 311 | #define MX25_PAD_CSPI1_SS0__CSPI1_SS0 0x160 0x358 0x000 0x10 0x000 | ||
| 312 | #define MX25_PAD_CSPI1_SS0__GPIO_1_16 0x160 0x358 0x000 0x15 0x000 | ||
| 313 | |||
| 314 | #define MX25_PAD_CSPI1_SS1__CSPI1_SS1 0x164 0x35c 0x000 0x10 0x000 | ||
| 315 | #define MX25_PAD_CSPI1_SS1__GPIO_1_17 0x164 0x35c 0x000 0x15 0x000 | ||
| 316 | |||
| 317 | #define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK 0x168 0x360 0x000 0x10 0x000 | ||
| 318 | #define MX25_PAD_CSPI1_SCLK__GPIO_1_18 0x168 0x360 0x000 0x15 0x000 | ||
| 319 | |||
| 320 | #define MX25_PAD_CSPI1_RDY__CSPI1_RDY 0x16c 0x364 0x000 0x10 0x000 | ||
| 321 | #define MX25_PAD_CSPI1_RDY__GPIO_2_22 0x16c 0x364 0x000 0x15 0x000 | ||
| 322 | |||
| 323 | #define MX25_PAD_UART1_RXD__UART1_RXD 0x170 0x368 0x000 0x10 0x000 | ||
| 324 | #define MX25_PAD_UART1_RXD__GPIO_4_22 0x170 0x368 0x000 0x15 0x000 | ||
| 325 | |||
| 326 | #define MX25_PAD_UART1_TXD__UART1_TXD 0x174 0x36c 0x000 0x10 0x000 | ||
| 327 | #define MX25_PAD_UART1_TXD__GPIO_4_23 0x174 0x36c 0x000 0x15 0x000 | ||
| 328 | |||
| 329 | #define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x10 0x000 | ||
| 330 | #define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x11 0x001 | ||
| 331 | #define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x15 0x000 | ||
| 332 | |||
| 333 | #define MX25_PAD_UART1_CTS__UART1_CTS 0x17c 0x374 0x000 0x10 0x000 | ||
| 334 | #define MX25_PAD_UART1_CTS__CSI_D1 0x17c 0x374 0x48c 0x11 0x001 | ||
| 335 | #define MX25_PAD_UART1_CTS__GPIO_4_25 0x17c 0x374 0x000 0x15 0x000 | ||
| 336 | |||
| 337 | #define MX25_PAD_UART2_RXD__UART2_RXD 0x180 0x378 0x000 0x10 0x000 | ||
| 338 | #define MX25_PAD_UART2_RXD__GPIO_4_26 0x180 0x378 0x000 0x15 0x000 | ||
| 339 | |||
| 340 | #define MX25_PAD_UART2_TXD__UART2_TXD 0x184 0x37c 0x000 0x10 0x000 | ||
| 341 | #define MX25_PAD_UART2_TXD__GPIO_4_27 0x184 0x37c 0x000 0x15 0x000 | ||
| 342 | |||
| 343 | #define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x10 0x000 | ||
| 344 | #define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x12 0x002 | ||
| 345 | #define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x15 0x000 | ||
| 346 | |||
| 347 | #define MX25_PAD_UART2_CTS__FEC_RX_ER 0x18c 0x384 0x518 0x12 0x002 | ||
| 348 | #define MX25_PAD_UART2_CTS__UART2_CTS 0x18c 0x384 0x000 0x10 0x000 | ||
| 349 | #define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x15 0x000 | ||
| 350 | |||
| 351 | #define MX25_PAD_SD1_CMD__SD1_CMD 0x190 0x388 0x000 0x10 0x000 | ||
| 352 | #define MX25_PAD_SD1_CMD__FEC_RDATA2 0x190 0x388 0x50c 0x12 0x002 | ||
| 353 | #define MX25_PAD_SD1_CMD__GPIO_2_23 0x190 0x388 0x000 0x15 0x000 | ||
| 354 | |||
| 355 | #define MX25_PAD_SD1_CLK__SD1_CLK 0x194 0x38c 0x000 0x10 0x000 | ||
| 356 | #define MX25_PAD_SD1_CLK__FEC_RDATA3 0x194 0x38c 0x510 0x12 0x002 | ||
| 357 | #define MX25_PAD_SD1_CLK__GPIO_2_24 0x194 0x38c 0x000 0x15 0x000 | ||
| 358 | |||
| 359 | #define MX25_PAD_SD1_DATA0__SD1_DATA0 0x198 0x390 0x000 0x10 0x000 | ||
| 360 | #define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x15 0x000 | ||
| 361 | |||
| 362 | #define MX25_PAD_SD1_DATA1__SD1_DATA1 0x19c 0x394 0x000 0x10 0x000 | ||
| 363 | #define MX25_PAD_SD1_DATA1__AUD7_RXD 0x19c 0x394 0x478 0x13 0x000 | ||
| 364 | #define MX25_PAD_SD1_DATA1__GPIO_2_26 0x19c 0x394 0x000 0x15 0x000 | ||
| 365 | |||
| 366 | #define MX25_PAD_SD1_DATA2__SD1_DATA2 0x1a0 0x398 0x000 0x10 0x000 | ||
| 367 | #define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x15 0x002 | ||
| 368 | #define MX25_PAD_SD1_DATA2__GPIO_2_27 0x1a0 0x398 0x000 0x15 0x000 | ||
| 369 | |||
| 370 | #define MX25_PAD_SD1_DATA3__SD1_DATA3 0x1a4 0x39c 0x000 0x10 0x000 | ||
| 371 | #define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x10 0x002 | ||
| 372 | #define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x15 0x000 | ||
| 373 | |||
| 374 | #define MX25_PAD_KPP_ROW0__KPP_ROW0 0x1a8 0x3a0 0x000 0x10 0x000 | ||
| 375 | #define MX25_PAD_KPP_ROW0__GPIO_2_29 0x1a8 0x3a0 0x000 0x15 0x000 | ||
| 376 | |||
| 377 | #define MX25_PAD_KPP_ROW1__KPP_ROW1 0x1ac 0x3a4 0x000 0x10 0x000 | ||
| 378 | #define MX25_PAD_KPP_ROW1__GPIO_2_30 0x1ac 0x3a4 0x000 0x15 0x000 | ||
| 379 | |||
| 380 | #define MX25_PAD_KPP_ROW2__KPP_ROW2 0x1b0 0x3a8 0x000 0x10 0x000 | ||
| 381 | #define MX25_PAD_KPP_ROW2__CSI_D0 0x1b0 0x3a8 0x488 0x13 0x002 | ||
| 382 | #define MX25_PAD_KPP_ROW2__GPIO_2_31 0x1b0 0x3a8 0x000 0x15 0x000 | ||
| 383 | |||
| 384 | #define MX25_PAD_KPP_ROW3__KPP_ROW3 0x1b4 0x3ac 0x000 0x10 0x000 | ||
| 385 | #define MX25_PAD_KPP_ROW3__CSI_LD1 0x1b4 0x3ac 0x48c 0x13 0x002 | ||
| 386 | #define MX25_PAD_KPP_ROW3__GPIO_3_0 0x1b4 0x3ac 0x000 0x15 0x000 | ||
| 387 | |||
| 388 | #define MX25_PAD_KPP_COL0__KPP_COL0 0x1b8 0x3b0 0x000 0x10 0x000 | ||
| 389 | #define MX25_PAD_KPP_COL0__UART4_RXD_MUX 0x1b8 0x3b0 0x570 0x11 0x001 | ||
| 390 | #define MX25_PAD_KPP_COL0__AUD5_TXD 0x1b8 0x3b0 0x000 0x12 0x000 | ||
| 391 | #define MX25_PAD_KPP_COL0__GPIO_3_1 0x1b8 0x3b0 0x000 0x15 0x000 | ||
| 392 | |||
| 393 | #define MX25_PAD_KPP_COL1__KPP_COL1 0x1bc 0x3b4 0x000 0x10 0x000 | ||
| 394 | #define MX25_PAD_KPP_COL1__UART4_TXD_MUX 0x1bc 0x3b4 0x000 0x11 0x000 | ||
| 395 | #define MX25_PAD_KPP_COL1__AUD5_RXD 0x1bc 0x3b4 0x000 0x12 0x000 | ||
| 396 | #define MX25_PAD_KPP_COL1__GPIO_3_2 0x1bc 0x3b4 0x000 0x15 0x000 | ||
| 397 | |||
| 398 | #define MX25_PAD_KPP_COL2__KPP_COL2 0x1c0 0x3b8 0x000 0x10 0x000 | ||
| 399 | #define MX25_PAD_KPP_COL2__UART4_RTS 0x1c0 0x3b8 0x000 0x11 0x000 | ||
| 400 | #define MX25_PAD_KPP_COL2__AUD5_TXC 0x1c0 0x3b8 0x000 0x12 0x000 | ||
| 401 | #define MX25_PAD_KPP_COL2__GPIO_3_3 0x1c0 0x3b8 0x000 0x15 0x000 | ||
| 402 | |||
| 403 | #define MX25_PAD_KPP_COL3__KPP_COL3 0x1c4 0x3bc 0x000 0x10 0x000 | ||
| 404 | #define MX25_PAD_KPP_COL3__UART4_CTS 0x1c4 0x3bc 0x000 0x11 0x000 | ||
| 405 | #define MX25_PAD_KPP_COL3__AUD5_TXFS 0x1c4 0x3bc 0x000 0x12 0x000 | ||
| 406 | #define MX25_PAD_KPP_COL3__GPIO_3_4 0x1c4 0x3bc 0x000 0x15 0x000 | ||
| 407 | |||
| 408 | #define MX25_PAD_FEC_MDC__FEC_MDC 0x1c8 0x3c0 0x000 0x10 0x000 | ||
| 409 | #define MX25_PAD_FEC_MDC__AUD4_TXD 0x1c8 0x3c0 0x464 0x12 0x001 | ||
| 410 | #define MX25_PAD_FEC_MDC__GPIO_3_5 0x1c8 0x3c0 0x000 0x15 0x000 | ||
| 411 | |||
| 412 | #define MX25_PAD_FEC_MDIO__FEC_MDIO 0x1cc 0x3c4 0x000 0x10 0x000 | ||
| 413 | #define MX25_PAD_FEC_MDIO__AUD4_RXD 0x1cc 0x3c4 0x460 0x12 0x001 | ||
| 414 | #define MX25_PAD_FEC_MDIO__GPIO_3_6 0x1cc 0x3c4 0x000 0x15 0x000 | ||
| 415 | |||
| 416 | #define MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x1d0 0x3c8 0x000 0x10 0x000 | ||
| 417 | #define MX25_PAD_FEC_TDATA0__GPIO_3_7 0x1d0 0x3c8 0x000 0x15 0x000 | ||
| 418 | |||
| 419 | #define MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x1d4 0x3cc 0x000 0x10 0x000 | ||
| 420 | #define MX25_PAD_FEC_TDATA1__AUD4_TXFS 0x1d4 0x3cc 0x474 0x12 0x001 | ||
| 421 | #define MX25_PAD_FEC_TDATA1__GPIO_3_8 0x1d4 0x3cc 0x000 0x15 0x000 | ||
| 422 | |||
| 423 | #define MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x1d8 0x3d0 0x000 0x10 0x000 | ||
| 424 | #define MX25_PAD_FEC_TX_EN__GPIO_3_9 0x1d8 0x3d0 0x000 0x15 0x000 | ||
| 425 | |||
| 426 | #define MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x1dc 0x3d4 0x000 0x10 0x000 | ||
| 427 | #define MX25_PAD_FEC_RDATA0__GPIO_3_10 0x1dc 0x3d4 0x000 0x15 0x000 | ||
| 428 | |||
| 429 | #define MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x1e0 0x3d8 0x000 0x10 0x000 | ||
| 430 | #define MX25_PAD_FEC_RDATA1__GPIO_3_11 0x1e0 0x3d8 0x000 0x15 0x000 | ||
| 431 | |||
| 432 | #define MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x1e4 0x3dc 0x000 0x10 0x000 | ||
| 433 | #define MX25_PAD_FEC_RX_DV__CAN2_RX 0x1e4 0x3dc 0x484 0x14 0x000 | ||
| 434 | #define MX25_PAD_FEC_RX_DV__GPIO_3_12 0x1e4 0x3dc 0x000 0x15 0x000 | ||
| 435 | |||
| 436 | #define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1e8 0x3e0 0x000 0x10 0x000 | ||
| 437 | #define MX25_PAD_FEC_TX_CLK__GPIO_3_13 0x1e8 0x3e0 0x000 0x15 0x000 | ||
| 438 | |||
| 439 | #define MX25_PAD_RTCK__RTCK 0x1ec 0x3e4 0x000 0x10 0x000 | ||
| 440 | #define MX25_PAD_RTCK__OWIRE 0x1ec 0x3e4 0x000 0x11 0x000 | ||
| 441 | #define MX25_PAD_RTCK__GPIO_3_14 0x1ec 0x3e4 0x000 0x15 0x000 | ||
| 442 | |||
| 443 | #define MX25_PAD_DE_B__DE_B 0x1f0 0x3ec 0x000 0x10 0x000 | ||
| 444 | #define MX25_PAD_DE_B__GPIO_2_20 0x1f0 0x3ec 0x000 0x15 0x000 | ||
| 445 | |||
| 446 | #define MX25_PAD_TDO__TDO 0x000 0x3e8 0x000 0x00 0x000 | ||
| 447 | |||
| 448 | #define MX25_PAD_GPIO_A__GPIO_A 0x1f4 0x3f0 0x000 0x10 0x000 | ||
| 449 | #define MX25_PAD_GPIO_A__CAN1_TX 0x1f4 0x3f0 0x000 0x16 0x000 | ||
| 450 | #define MX25_PAD_GPIO_A__USBOTG_PWR 0x1f4 0x3f0 0x000 0x12 0x000 | ||
| 451 | |||
| 452 | #define MX25_PAD_GPIO_B__GPIO_B 0x1f8 0x3f4 0x000 0x10 0x000 | ||
| 453 | #define MX25_PAD_GPIO_B__CAN1_RX 0x1f8 0x3f4 0x480 0x16 0x001 | ||
| 454 | #define MX25_PAD_GPIO_B__USBOTG_OC 0x1f8 0x3f4 0x57c 0x12 0x001 | ||
| 455 | |||
| 456 | #define MX25_PAD_GPIO_C__GPIO_C 0x1fc 0x3f8 0x000 0x10 0x000 | ||
| 457 | #define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x16 0x000 | ||
| 458 | |||
| 459 | #define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x10 0x000 | ||
| 460 | #define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x02 0x000 | ||
| 461 | #define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x16 0x001 | ||
| 462 | |||
| 463 | #define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x10 0x000 | ||
| 464 | #define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x02 0x000 | ||
| 465 | #define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x14 0x000 | ||
| 466 | |||
| 467 | #define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x10 0x000 | ||
| 468 | #define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x14 0x000 | ||
| 469 | |||
| 470 | #define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x10 0x000 | ||
| 471 | #define MX25_PAD_EXT_ARMCLK__GPIO_3_15 0x20c 0x000 0x000 0x15 0x000 | ||
| 472 | |||
| 473 | #define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK 0x210 0x000 0x000 0x10 0x000 | ||
| 474 | #define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 0x210 0x000 0x000 0x15 0x000 | ||
| 475 | |||
| 476 | #define MX25_PAD_VSTBY_REQ__VSTBY_REQ 0x214 0x408 0x000 0x10 0x000 | ||
| 477 | #define MX25_PAD_VSTBY_REQ__AUD7_TXFS 0x214 0x408 0x000 0x14 0x000 | ||
| 478 | #define MX25_PAD_VSTBY_REQ__GPIO_3_17 0x214 0x408 0x000 0x15 0x000 | ||
| 479 | #define MX25_PAD_VSTBY_ACK__VSTBY_ACK 0x218 0x40c 0x000 0x10 0x000 | ||
| 480 | #define MX25_PAD_VSTBY_ACK__GPIO_3_18 0x218 0x40c 0x000 0x15 0x000 | ||
| 481 | |||
| 482 | #define MX25_PAD_POWER_FAIL__POWER_FAIL 0x21c 0x410 0x000 0x10 0x000 | ||
| 483 | #define MX25_PAD_POWER_FAIL__AUD7_RXD 0x21c 0x410 0x478 0x14 0x001 | ||
| 484 | #define MX25_PAD_POWER_FAIL__GPIO_3_19 0x21c 0x410 0x000 0x15 0x000 | ||
| 485 | |||
| 486 | #define MX25_PAD_CLKO__CLKO 0x220 0x414 0x000 0x10 0x000 | ||
| 487 | #define MX25_PAD_CLKO__GPIO_2_21 0x220 0x414 0x000 0x15 0x000 | ||
| 488 | |||
| 489 | #define MX25_PAD_BOOT_MODE0__BOOT_MODE0 0x224 0x000 0x000 0x00 0x000 | ||
| 490 | #define MX25_PAD_BOOT_MODE0__GPIO_4_30 0x224 0x000 0x000 0x05 0x000 | ||
| 491 | #define MX25_PAD_BOOT_MODE1__BOOT_MODE1 0x228 0x000 0x000 0x00 0x000 | ||
| 492 | #define MX25_PAD_BOOT_MODE1__GPIO_4_31 0x228 0x000 0x000 0x05 0x000 | ||
| 493 | |||
| 494 | #endif /* __DTS_IMX25_PINFUNC_H */ | ||
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index 737ed5da8f71..32f760e24898 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi | |||
| @@ -10,6 +10,7 @@ | |||
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | #include "skeleton.dtsi" | 12 | #include "skeleton.dtsi" |
| 13 | #include "imx25-pinfunc.h" | ||
| 13 | 14 | ||
| 14 | / { | 15 | / { |
| 15 | aliases { | 16 | aliases { |
| @@ -173,12 +174,12 @@ | |||
| 173 | status = "disabled"; | 174 | status = "disabled"; |
| 174 | }; | 175 | }; |
| 175 | 176 | ||
| 176 | iomuxc@43fac000{ | 177 | iomuxc: iomuxc@43fac000 { |
| 177 | compatible = "fsl,imx25-iomuxc"; | 178 | compatible = "fsl,imx25-iomuxc"; |
| 178 | reg = <0x43fac000 0x4000>; | 179 | reg = <0x43fac000 0x4000>; |
| 179 | }; | 180 | }; |
| 180 | 181 | ||
| 181 | audmux@43fb0000 { | 182 | audmux: audmux@43fb0000 { |
| 182 | compatible = "fsl,imx25-audmux", "fsl,imx31-audmux"; | 183 | compatible = "fsl,imx25-audmux", "fsl,imx31-audmux"; |
| 183 | reg = <0x43fb0000 0x4000>; | 184 | reg = <0x43fb0000 0x4000>; |
| 184 | status = "disabled"; | 185 | status = "disabled"; |
| @@ -236,6 +237,11 @@ | |||
| 236 | compatible = "fsl,imx25-ssi", "fsl,imx21-ssi"; | 237 | compatible = "fsl,imx25-ssi", "fsl,imx21-ssi"; |
| 237 | reg = <0x50014000 0x4000>; | 238 | reg = <0x50014000 0x4000>; |
| 238 | interrupts = <11>; | 239 | interrupts = <11>; |
| 240 | clocks = <&clks 118>; | ||
| 241 | clock-names = "ipg"; | ||
| 242 | dmas = <&sdma 24 1 0>, | ||
| 243 | <&sdma 25 1 0>; | ||
| 244 | dma-names = "rx", "tx"; | ||
| 239 | status = "disabled"; | 245 | status = "disabled"; |
| 240 | }; | 246 | }; |
| 241 | 247 | ||
| @@ -266,6 +272,11 @@ | |||
| 266 | compatible = "fsl,imx25-ssi", "fsl,imx21-ssi"; | 272 | compatible = "fsl,imx25-ssi", "fsl,imx21-ssi"; |
| 267 | reg = <0x50034000 0x4000>; | 273 | reg = <0x50034000 0x4000>; |
| 268 | interrupts = <12>; | 274 | interrupts = <12>; |
| 275 | clocks = <&clks 117>; | ||
| 276 | clock-names = "ipg"; | ||
| 277 | dmas = <&sdma 28 1 0>, | ||
| 278 | <&sdma 29 1 0>; | ||
| 279 | dma-names = "rx", "tx"; | ||
| 269 | status = "disabled"; | 280 | status = "disabled"; |
| 270 | }; | 281 | }; |
| 271 | 282 | ||
| @@ -436,13 +447,14 @@ | |||
| 436 | #interrupt-cells = <2>; | 447 | #interrupt-cells = <2>; |
| 437 | }; | 448 | }; |
| 438 | 449 | ||
| 439 | sdma@53fd4000 { | 450 | sdma: sdma@53fd4000 { |
| 440 | compatible = "fsl,imx25-sdma", "fsl,imx35-sdma"; | 451 | compatible = "fsl,imx25-sdma", "fsl,imx35-sdma"; |
| 441 | reg = <0x53fd4000 0x4000>; | 452 | reg = <0x53fd4000 0x4000>; |
| 442 | clocks = <&clks 112>, <&clks 68>; | 453 | clocks = <&clks 112>, <&clks 68>; |
| 443 | clock-names = "ipg", "ahb"; | 454 | clock-names = "ipg", "ahb"; |
| 444 | #dma-cells = <3>; | 455 | #dma-cells = <3>; |
| 445 | interrupts = <34>; | 456 | interrupts = <34>; |
| 457 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx25.bin"; | ||
| 446 | }; | 458 | }; |
| 447 | 459 | ||
| 448 | wdog@53fdc000 { | 460 | wdog@53fdc000 { |
diff --git a/arch/arm/boot/dts/imx27-apf27.dts b/arch/arm/boot/dts/imx27-apf27.dts index ba4c6df08ece..09f57b39e3ef 100644 --- a/arch/arm/boot/dts/imx27-apf27.dts +++ b/arch/arm/boot/dts/imx27-apf27.dts | |||
| @@ -34,11 +34,49 @@ | |||
| 34 | }; | 34 | }; |
| 35 | }; | 35 | }; |
| 36 | 36 | ||
| 37 | &iomuxc { | ||
| 38 | imx27-apf27 { | ||
| 39 | pinctrl_fec1: fec1grp { | ||
| 40 | fsl,pins = < | ||
| 41 | MX27_PAD_SD3_CMD__FEC_TXD0 0x0 | ||
| 42 | MX27_PAD_SD3_CLK__FEC_TXD1 0x0 | ||
| 43 | MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 | ||
| 44 | MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 | ||
| 45 | MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 | ||
| 46 | MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 | ||
| 47 | MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 | ||
| 48 | MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 | ||
| 49 | MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 | ||
| 50 | MX27_PAD_ATA_DATA7__FEC_MDC 0x0 | ||
| 51 | MX27_PAD_ATA_DATA8__FEC_CRS 0x0 | ||
| 52 | MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 | ||
| 53 | MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 | ||
| 54 | MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 | ||
| 55 | MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 | ||
| 56 | MX27_PAD_ATA_DATA13__FEC_COL 0x0 | ||
| 57 | MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 | ||
| 58 | MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 | ||
| 59 | >; | ||
| 60 | }; | ||
| 61 | |||
| 62 | pinctrl_uart1: uart1grp { | ||
| 63 | fsl,pins = < | ||
| 64 | MX27_PAD_UART1_TXD__UART1_TXD 0x0 | ||
| 65 | MX27_PAD_UART1_RXD__UART1_RXD 0x0 | ||
| 66 | >; | ||
| 67 | }; | ||
| 68 | }; | ||
| 69 | }; | ||
| 70 | |||
| 37 | &uart1 { | 71 | &uart1 { |
| 72 | pinctrl-names = "default"; | ||
| 73 | pinctrl-0 = <&pinctrl_uart1>; | ||
| 38 | status = "okay"; | 74 | status = "okay"; |
| 39 | }; | 75 | }; |
| 40 | 76 | ||
| 41 | &fec { | 77 | &fec { |
| 78 | pinctrl-names = "default"; | ||
| 79 | pinctrl-0 = <&pinctrl_fec1>; | ||
| 42 | status = "okay"; | 80 | status = "okay"; |
| 43 | }; | 81 | }; |
| 44 | 82 | ||
diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts index 47c8c26012e4..2b6d489dae69 100644 --- a/arch/arm/boot/dts/imx27-apf27dev.dts +++ b/arch/arm/boot/dts/imx27-apf27dev.dts | |||
| @@ -22,10 +22,10 @@ | |||
| 22 | bits-per-pixel = <16>; /* non-standard but required */ | 22 | bits-per-pixel = <16>; /* non-standard but required */ |
| 23 | fsl,pcr = <0xfae80083>; /* non-standard but required */ | 23 | fsl,pcr = <0xfae80083>; /* non-standard but required */ |
| 24 | display-timings { | 24 | display-timings { |
| 25 | timing0: 640x480 { | 25 | timing0: 800x480 { |
| 26 | clock-frequency = <33000033>; | 26 | clock-frequency = <33000033>; |
| 27 | hactive = <800>; | 27 | hactive = <800>; |
| 28 | vactive = <640>; | 28 | vactive = <480>; |
| 29 | hback-porch = <96>; | 29 | hback-porch = <96>; |
| 30 | hfront-porch = <96>; | 30 | hfront-porch = <96>; |
| 31 | vback-porch = <20>; | 31 | vback-porch = <20>; |
| @@ -38,20 +38,24 @@ | |||
| 38 | 38 | ||
| 39 | gpio-keys { | 39 | gpio-keys { |
| 40 | compatible = "gpio-keys"; | 40 | compatible = "gpio-keys"; |
| 41 | pinctrl-names = "default"; | ||
| 42 | pinctrl-0 = <&pinctrl_gpio_keys>; | ||
| 41 | 43 | ||
| 42 | user-key { | 44 | user-key { |
| 43 | label = "user"; | 45 | label = "user"; |
| 44 | gpios = <&gpio6 13 0>; | 46 | gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; |
| 45 | linux,code = <276>; /* BTN_EXTRA */ | 47 | linux,code = <276>; /* BTN_EXTRA */ |
| 46 | }; | 48 | }; |
| 47 | }; | 49 | }; |
| 48 | 50 | ||
| 49 | leds { | 51 | leds { |
| 50 | compatible = "gpio-leds"; | 52 | compatible = "gpio-leds"; |
| 53 | pinctrl-names = "default"; | ||
| 54 | pinctrl-0 = <&pinctrl_gpio_leds>; | ||
| 51 | 55 | ||
| 52 | user { | 56 | user { |
| 53 | label = "Heartbeat"; | 57 | label = "Heartbeat"; |
| 54 | gpios = <&gpio6 14 0>; | 58 | gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; |
| 55 | linux,default-trigger = "heartbeat"; | 59 | linux,default-trigger = "heartbeat"; |
| 56 | }; | 60 | }; |
| 57 | }; | 61 | }; |
| @@ -59,25 +63,34 @@ | |||
| 59 | 63 | ||
| 60 | &cspi1 { | 64 | &cspi1 { |
| 61 | fsl,spi-num-chipselects = <1>; | 65 | fsl,spi-num-chipselects = <1>; |
| 62 | cs-gpios = <&gpio4 28 1>; | 66 | cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; |
| 67 | pinctrl-names = "default"; | ||
| 68 | pinctrl-0 = <&pinctrl_cspi1 &pinctrl_cspi1_cs>; | ||
| 63 | status = "okay"; | 69 | status = "okay"; |
| 64 | }; | 70 | }; |
| 65 | 71 | ||
| 66 | &cspi2 { | 72 | &cspi2 { |
| 67 | fsl,spi-num-chipselects = <3>; | 73 | fsl,spi-num-chipselects = <3>; |
| 68 | cs-gpios = <&gpio4 21 1>, <&gpio4 27 1>, | 74 | cs-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>, |
| 69 | <&gpio2 17 1>; | 75 | <&gpio4 27 GPIO_ACTIVE_LOW>, |
| 76 | <&gpio2 17 GPIO_ACTIVE_LOW>; | ||
| 77 | pinctrl-names = "default"; | ||
| 78 | pinctrl-0 = <&pinctrl_cspi2 &pinctrl_cspi2_cs>; | ||
| 70 | status = "okay"; | 79 | status = "okay"; |
| 71 | }; | 80 | }; |
| 72 | 81 | ||
| 73 | &fb { | 82 | &fb { |
| 74 | display = <&display>; | 83 | display = <&display>; |
| 75 | fsl,dmacr = <0x00020010>; | 84 | fsl,dmacr = <0x00020010>; |
| 85 | pinctrl-names = "default"; | ||
| 86 | pinctrl-0 = <&pinctrl_imxfb1>; | ||
| 76 | status = "okay"; | 87 | status = "okay"; |
| 77 | }; | 88 | }; |
| 78 | 89 | ||
| 79 | &i2c1 { | 90 | &i2c1 { |
| 80 | clock-frequency = <400000>; | 91 | clock-frequency = <400000>; |
| 92 | pinctrl-names = "default"; | ||
| 93 | pinctrl-0 = <&pinctrl_i2c1>; | ||
| 81 | status = "okay"; | 94 | status = "okay"; |
| 82 | 95 | ||
| 83 | rtc@68 { | 96 | rtc@68 { |
| @@ -87,5 +100,127 @@ | |||
| 87 | }; | 100 | }; |
| 88 | 101 | ||
| 89 | &i2c2 { | 102 | &i2c2 { |
| 103 | pinctrl-names = "default"; | ||
| 104 | pinctrl-0 = <&pinctrl_i2c2>; | ||
| 90 | status = "okay"; | 105 | status = "okay"; |
| 91 | }; | 106 | }; |
| 107 | |||
| 108 | &iomuxc { | ||
| 109 | imx27-apf27dev { | ||
| 110 | pinctrl_cspi1: cspi1grp { | ||
| 111 | fsl,pins = < | ||
| 112 | MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 | ||
| 113 | MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 | ||
| 114 | MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 | ||
| 115 | >; | ||
| 116 | }; | ||
| 117 | |||
| 118 | pinctrl_cspi1_cs: cspi1csgrp { | ||
| 119 | fsl,pins = <MX27_PAD_CSPI1_SS0__GPIO4_28 0x0>; | ||
| 120 | }; | ||
| 121 | |||
| 122 | pinctrl_cspi2: cspi2grp { | ||
| 123 | fsl,pins = < | ||
| 124 | MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0 | ||
| 125 | MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0 | ||
| 126 | MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0 | ||
| 127 | >; | ||
| 128 | }; | ||
| 129 | |||
| 130 | pinctrl_cspi2_cs: cspi2csgrp { | ||
| 131 | fsl,pins = < | ||
| 132 | MX27_PAD_CSI_D5__GPIO2_17 0x0 | ||
| 133 | MX27_PAD_CSPI2_SS0__GPIO4_21 0x0 | ||
| 134 | MX27_PAD_CSPI1_SS1__GPIO4_27 0x0 | ||
| 135 | >; | ||
| 136 | }; | ||
| 137 | |||
| 138 | pinctrl_gpio_leds: gpioledsgrp { | ||
| 139 | fsl,pins = <MX27_PAD_PC_VS1__GPIO6_14 0x0>; | ||
| 140 | }; | ||
| 141 | |||
| 142 | pinctrl_gpio_keys: gpiokeysgrp { | ||
| 143 | fsl,pins = <MX27_PAD_PC_VS2__GPIO6_13 0x0>; | ||
| 144 | }; | ||
| 145 | |||
| 146 | pinctrl_imxfb1: imxfbgrp { | ||
| 147 | fsl,pins = < | ||
| 148 | MX27_PAD_CLS__CLS 0x0 | ||
| 149 | MX27_PAD_CONTRAST__CONTRAST 0x0 | ||
| 150 | MX27_PAD_LD0__LD0 0x0 | ||
| 151 | MX27_PAD_LD1__LD1 0x0 | ||
| 152 | MX27_PAD_LD2__LD2 0x0 | ||
| 153 | MX27_PAD_LD3__LD3 0x0 | ||
| 154 | MX27_PAD_LD4__LD4 0x0 | ||
| 155 | MX27_PAD_LD5__LD5 0x0 | ||
| 156 | MX27_PAD_LD6__LD6 0x0 | ||
| 157 | MX27_PAD_LD7__LD7 0x0 | ||
| 158 | MX27_PAD_LD8__LD8 0x0 | ||
| 159 | MX27_PAD_LD9__LD9 0x0 | ||
| 160 | MX27_PAD_LD10__LD10 0x0 | ||
| 161 | MX27_PAD_LD11__LD11 0x0 | ||
| 162 | MX27_PAD_LD12__LD12 0x0 | ||
| 163 | MX27_PAD_LD13__LD13 0x0 | ||
| 164 | MX27_PAD_LD14__LD14 0x0 | ||
| 165 | MX27_PAD_LD15__LD15 0x0 | ||
| 166 | MX27_PAD_LD16__LD16 0x0 | ||
| 167 | MX27_PAD_LD17__LD17 0x0 | ||
| 168 | MX27_PAD_LSCLK__LSCLK 0x0 | ||
| 169 | MX27_PAD_OE_ACD__OE_ACD 0x0 | ||
| 170 | MX27_PAD_PS__PS 0x0 | ||
| 171 | MX27_PAD_REV__REV 0x0 | ||
| 172 | MX27_PAD_SPL_SPR__SPL_SPR 0x0 | ||
| 173 | MX27_PAD_HSYNC__HSYNC 0x0 | ||
| 174 | MX27_PAD_VSYNC__VSYNC 0x0 | ||
| 175 | >; | ||
| 176 | }; | ||
| 177 | |||
| 178 | pinctrl_i2c1: i2c1grp { | ||
| 179 | fsl,pins = < | ||
| 180 | MX27_PAD_I2C_DATA__I2C_DATA 0x0 | ||
| 181 | MX27_PAD_I2C_CLK__I2C_CLK 0x0 | ||
| 182 | >; | ||
| 183 | }; | ||
| 184 | |||
| 185 | pinctrl_i2c2: i2c2grp { | ||
| 186 | fsl,pins = < | ||
| 187 | MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 | ||
| 188 | MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 | ||
| 189 | >; | ||
| 190 | }; | ||
| 191 | |||
| 192 | pinctrl_pwm: pwmgrp { | ||
| 193 | fsl,pins = < | ||
| 194 | MX27_PAD_PWMO__PWMO 0x0 | ||
| 195 | >; | ||
| 196 | }; | ||
| 197 | |||
| 198 | pinctrl_sdhc2: sdhc2grp { | ||
| 199 | fsl,pins = < | ||
| 200 | MX27_PAD_SD2_CLK__SD2_CLK 0x0 | ||
| 201 | MX27_PAD_SD2_CMD__SD2_CMD 0x0 | ||
| 202 | MX27_PAD_SD2_D0__SD2_D0 0x0 | ||
| 203 | MX27_PAD_SD2_D1__SD2_D1 0x0 | ||
| 204 | MX27_PAD_SD2_D2__SD2_D2 0x0 | ||
| 205 | MX27_PAD_SD2_D3__SD2_D3 0x0 | ||
| 206 | >; | ||
| 207 | }; | ||
| 208 | |||
| 209 | pinctrl_sdhc2_cd: sdhc2cdgrp { | ||
| 210 | fsl,pins = <MX27_PAD_TOUT__GPIO3_14 0x0>; | ||
| 211 | }; | ||
| 212 | }; | ||
| 213 | }; | ||
| 214 | |||
| 215 | &sdhci2 { | ||
| 216 | bus-width = <4>; | ||
| 217 | cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; | ||
| 218 | pinctrl-names = "default"; | ||
| 219 | pinctrl-0 = <&pinctrl_sdhc2 &pinctrl_sdhc2_cd>; | ||
| 220 | status = "okay"; | ||
| 221 | }; | ||
| 222 | |||
| 223 | &pwm { | ||
| 224 | pinctrl-names = "default"; | ||
| 225 | pinctrl-0 = <&pinctrl_pwm>; | ||
| 226 | }; | ||
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts index 5a31c776513f..3c3964a99637 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts | |||
| @@ -9,7 +9,7 @@ | |||
| 9 | * http://www.gnu.org/copyleft/gpl.html | 9 | * http://www.gnu.org/copyleft/gpl.html |
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | #include "imx27-phytec-phycard-s-som.dts" | 12 | #include "imx27-phytec-phycard-s-som.dtsi" |
| 13 | 13 | ||
| 14 | / { | 14 | / { |
| 15 | model = "Phytec pca100 rapid development kit"; | 15 | model = "Phytec pca100 rapid development kit"; |
| @@ -37,9 +37,12 @@ | |||
| 37 | 37 | ||
| 38 | regulators { | 38 | regulators { |
| 39 | compatible = "simple-bus"; | 39 | compatible = "simple-bus"; |
| 40 | #address-cells = <1>; | ||
| 41 | #size-cells = <0>; | ||
| 40 | 42 | ||
| 41 | reg_3v3: 3v3 { | 43 | reg_3v3: regulator@0 { |
| 42 | compatible = "regulator-fixed"; | 44 | compatible = "regulator-fixed"; |
| 45 | reg = <0>; | ||
| 43 | regulator-name = "3V3"; | 46 | regulator-name = "3V3"; |
| 44 | regulator-min-microvolt = <3300000>; | 47 | regulator-min-microvolt = <3300000>; |
| 45 | regulator-max-microvolt = <3300000>; | 48 | regulator-max-microvolt = <3300000>; |
| @@ -54,6 +57,8 @@ | |||
| 54 | }; | 57 | }; |
| 55 | 58 | ||
| 56 | &i2c1 { | 59 | &i2c1 { |
| 60 | pinctrl-names = "default"; | ||
| 61 | pinctrl-0 = <&pinctrl_i2c1>; | ||
| 57 | status = "okay"; | 62 | status = "okay"; |
| 58 | 63 | ||
| 59 | rtc@51 { | 64 | rtc@51 { |
| @@ -68,26 +73,92 @@ | |||
| 68 | }; | 73 | }; |
| 69 | }; | 74 | }; |
| 70 | 75 | ||
| 76 | &iomuxc { | ||
| 77 | imx27-phycard-s-rdk { | ||
| 78 | pinctrl_i2c1: i2c1grp { | ||
| 79 | fsl,pins = < | ||
| 80 | MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 | ||
| 81 | MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 | ||
| 82 | >; | ||
| 83 | }; | ||
| 84 | |||
| 85 | pinctrl_owire1: owire1grp { | ||
| 86 | fsl,pins = < | ||
| 87 | MX27_PAD_RTCK__OWIRE 0x0 | ||
| 88 | >; | ||
| 89 | }; | ||
| 90 | |||
| 91 | pinctrl_sdhc2: sdhc2grp { | ||
| 92 | fsl,pins = < | ||
| 93 | MX27_PAD_SD2_CLK__SD2_CLK 0x0 | ||
| 94 | MX27_PAD_SD2_CMD__SD2_CMD 0x0 | ||
| 95 | MX27_PAD_SD2_D0__SD2_D0 0x0 | ||
| 96 | MX27_PAD_SD2_D1__SD2_D1 0x0 | ||
| 97 | MX27_PAD_SD2_D2__SD2_D2 0x0 | ||
| 98 | MX27_PAD_SD2_D3__SD2_D3 0x0 | ||
| 99 | MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */ | ||
| 100 | >; | ||
| 101 | }; | ||
| 102 | |||
| 103 | pinctrl_uart1: uart1grp { | ||
| 104 | fsl,pins = < | ||
| 105 | MX27_PAD_UART1_TXD__UART1_TXD 0x0 | ||
| 106 | MX27_PAD_UART1_RXD__UART1_RXD 0x0 | ||
| 107 | MX27_PAD_UART1_CTS__UART1_CTS 0x0 | ||
| 108 | MX27_PAD_UART1_RTS__UART1_RTS 0x0 | ||
| 109 | >; | ||
| 110 | }; | ||
| 111 | |||
| 112 | pinctrl_uart2: uart2grp { | ||
| 113 | fsl,pins = < | ||
| 114 | MX27_PAD_UART2_TXD__UART2_TXD 0x0 | ||
| 115 | MX27_PAD_UART2_RXD__UART2_RXD 0x0 | ||
| 116 | MX27_PAD_UART2_CTS__UART2_CTS 0x0 | ||
| 117 | MX27_PAD_UART2_RTS__UART2_RTS 0x0 | ||
| 118 | >; | ||
| 119 | }; | ||
| 120 | |||
| 121 | pinctrl_uart3: uart3grp { | ||
| 122 | fsl,pins = < | ||
| 123 | MX27_PAD_UART3_TXD__UART3_TXD 0x0 | ||
| 124 | MX27_PAD_UART3_RXD__UART3_RXD 0x0 | ||
| 125 | MX27_PAD_UART3_CTS__UART3_CTS 0x0 | ||
| 126 | MX27_PAD_UART3_RTS__UART3_RTS 0x0 | ||
| 127 | >; | ||
| 128 | }; | ||
| 129 | }; | ||
| 130 | }; | ||
| 131 | |||
| 71 | &owire { | 132 | &owire { |
| 133 | pinctrl-names = "default"; | ||
| 134 | pinctrl-0 = <&pinctrl_owire1>; | ||
| 72 | status = "okay"; | 135 | status = "okay"; |
| 73 | }; | 136 | }; |
| 74 | 137 | ||
| 75 | &sdhci2 { | 138 | &sdhci2 { |
| 76 | cd-gpios = <&gpio3 29 0>; | 139 | pinctrl-names = "default"; |
| 140 | pinctrl-0 = <&pinctrl_sdhc2>; | ||
| 141 | cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; | ||
| 77 | status = "okay"; | 142 | status = "okay"; |
| 78 | }; | 143 | }; |
| 79 | 144 | ||
| 80 | &uart1 { | 145 | &uart1 { |
| 81 | fsl,uart-has-rtscts; | 146 | fsl,uart-has-rtscts; |
| 147 | pinctrl-names = "default"; | ||
| 148 | pinctrl-0 = <&pinctrl_uart1>; | ||
| 82 | status = "okay"; | 149 | status = "okay"; |
| 83 | }; | 150 | }; |
| 84 | 151 | ||
| 85 | &uart2 { | 152 | &uart2 { |
| 86 | fsl,uart-has-rtscts; | 153 | fsl,uart-has-rtscts; |
| 154 | pinctrl-names = "default"; | ||
| 155 | pinctrl-0 = <&pinctrl_uart2>; | ||
| 87 | status = "okay"; | 156 | status = "okay"; |
| 88 | }; | 157 | }; |
| 89 | 158 | ||
| 90 | &uart3 { | 159 | &uart3 { |
| 91 | fsl,uart-has-rtscts; | 160 | fsl,uart-has-rtscts; |
| 161 | pinctrl-names = "default"; | ||
| 162 | pinctrl-0 = <&pinctrl_uart3>; | ||
| 92 | status = "okay"; | 163 | status = "okay"; |
| 93 | }; | 164 | }; |
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts deleted file mode 100644 index c8d57d1d0743..000000000000 --- a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts +++ /dev/null | |||
| @@ -1,44 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar | ||
| 3 | * and Markus Pargmann, Pengutronix | ||
| 4 | * | ||
| 5 | * The code contained herein is licensed under the GNU General Public | ||
| 6 | * License. You may obtain a copy of the GNU General Public License | ||
| 7 | * Version 2 or later at the following locations: | ||
| 8 | * | ||
| 9 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 10 | * http://www.gnu.org/copyleft/gpl.html | ||
| 11 | */ | ||
| 12 | |||
| 13 | /dts-v1/; | ||
| 14 | #include "imx27.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Phytec pca100"; | ||
| 18 | compatible = "phytec,imx27-pca100", "fsl,imx27"; | ||
| 19 | |||
| 20 | memory { | ||
| 21 | reg = <0xa0000000 0x08000000>; /* 128MB */ | ||
| 22 | }; | ||
| 23 | }; | ||
| 24 | |||
| 25 | &cspi1 { | ||
| 26 | fsl,spi-num-chipselects = <2>; | ||
| 27 | cs-gpios = <&gpio4 28 0>, | ||
| 28 | <&gpio4 27 0>; | ||
| 29 | status = "okay"; | ||
| 30 | }; | ||
| 31 | |||
| 32 | &fec { | ||
| 33 | status = "okay"; | ||
| 34 | }; | ||
| 35 | |||
| 36 | &i2c2 { | ||
| 37 | status = "okay"; | ||
| 38 | |||
| 39 | at24@52 { | ||
| 40 | compatible = "at,24c32"; | ||
| 41 | pagesize = <32>; | ||
| 42 | reg = <0x52>; | ||
| 43 | }; | ||
| 44 | }; | ||
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi new file mode 100644 index 000000000000..1b6248079682 --- /dev/null +++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi | |||
| @@ -0,0 +1,103 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar | ||
| 3 | * and Markus Pargmann, Pengutronix | ||
| 4 | * | ||
| 5 | * The code contained herein is licensed under the GNU General Public | ||
| 6 | * License. You may obtain a copy of the GNU General Public License | ||
| 7 | * Version 2 or later at the following locations: | ||
| 8 | * | ||
| 9 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 10 | * http://www.gnu.org/copyleft/gpl.html | ||
| 11 | */ | ||
| 12 | |||
| 13 | /dts-v1/; | ||
| 14 | #include "imx27.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Phytec pca100"; | ||
| 18 | compatible = "phytec,imx27-pca100", "fsl,imx27"; | ||
| 19 | |||
| 20 | memory { | ||
| 21 | reg = <0xa0000000 0x08000000>; /* 128MB */ | ||
| 22 | }; | ||
| 23 | }; | ||
| 24 | |||
| 25 | &cspi1 { | ||
| 26 | fsl,spi-num-chipselects = <2>; | ||
| 27 | cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>, | ||
| 28 | <&gpio4 27 GPIO_ACTIVE_HIGH>; | ||
| 29 | status = "okay"; | ||
| 30 | }; | ||
| 31 | |||
| 32 | &fec { | ||
| 33 | pinctrl-names = "default"; | ||
| 34 | pinctrl-0 = <&pinctrl_fec1>; | ||
| 35 | status = "okay"; | ||
| 36 | }; | ||
| 37 | |||
| 38 | &i2c2 { | ||
| 39 | pinctrl-names = "default"; | ||
| 40 | pinctrl-0 = <&pinctrl_i2c2>; | ||
| 41 | status = "okay"; | ||
| 42 | |||
| 43 | at24@52 { | ||
| 44 | compatible = "at,24c32"; | ||
| 45 | pagesize = <32>; | ||
| 46 | reg = <0x52>; | ||
| 47 | }; | ||
| 48 | }; | ||
| 49 | |||
| 50 | &iomuxc { | ||
| 51 | imx27-phycard-s-som { | ||
| 52 | pinctrl_fec1: fec1grp { | ||
| 53 | fsl,pins = < | ||
| 54 | MX27_PAD_SD3_CMD__FEC_TXD0 0x0 | ||
| 55 | MX27_PAD_SD3_CLK__FEC_TXD1 0x0 | ||
| 56 | MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 | ||
| 57 | MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 | ||
| 58 | MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 | ||
| 59 | MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 | ||
| 60 | MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 | ||
| 61 | MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 | ||
| 62 | MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 | ||
| 63 | MX27_PAD_ATA_DATA7__FEC_MDC 0x0 | ||
| 64 | MX27_PAD_ATA_DATA8__FEC_CRS 0x0 | ||
| 65 | MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 | ||
| 66 | MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 | ||
| 67 | MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 | ||
| 68 | MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 | ||
| 69 | MX27_PAD_ATA_DATA13__FEC_COL 0x0 | ||
| 70 | MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 | ||
| 71 | MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 | ||
| 72 | >; | ||
| 73 | }; | ||
| 74 | |||
| 75 | pinctrl_i2c2: i2c2grp { | ||
| 76 | fsl,pins = < | ||
| 77 | MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 | ||
| 78 | MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 | ||
| 79 | >; | ||
| 80 | }; | ||
| 81 | |||
| 82 | pinctrl_nfc: nfcgrp { | ||
| 83 | fsl,pins = < | ||
| 84 | MX27_PAD_NFRB__NFRB 0x0 | ||
| 85 | MX27_PAD_NFCLE__NFCLE 0x0 | ||
| 86 | MX27_PAD_NFWP_B__NFWP_B 0x0 | ||
| 87 | MX27_PAD_NFCE_B__NFCE_B 0x0 | ||
| 88 | MX27_PAD_NFALE__NFALE 0x0 | ||
| 89 | MX27_PAD_NFRE_B__NFRE_B 0x0 | ||
| 90 | MX27_PAD_NFWE_B__NFWE_B 0x0 | ||
| 91 | >; | ||
| 92 | }; | ||
| 93 | }; | ||
| 94 | }; | ||
| 95 | |||
| 96 | &nfc { | ||
| 97 | pinctrl-names = "default"; | ||
| 98 | pinctrl-0 = <&pinctrl_nfc>; | ||
| 99 | nand-bus-width = <8>; | ||
| 100 | nand-ecc-mode = "hw"; | ||
| 101 | nand-on-flash-bbt; | ||
| 102 | status = "okay"; | ||
| 103 | }; | ||
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts index 0fc6551786c6..df3b2e731835 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | * http://www.gnu.org/copyleft/gpl.html | 7 | * http://www.gnu.org/copyleft/gpl.html |
| 8 | */ | 8 | */ |
| 9 | 9 | ||
| 10 | #include "imx27-phytec-phycore-som.dts" | 10 | #include "imx27-phytec-phycore-som.dtsi" |
| 11 | 11 | ||
| 12 | / { | 12 | / { |
| 13 | model = "Phytec pcm970"; | 13 | model = "Phytec pcm970"; |
| @@ -16,32 +16,200 @@ | |||
| 16 | 16 | ||
| 17 | &cspi1 { | 17 | &cspi1 { |
| 18 | fsl,spi-num-chipselects = <2>; | 18 | fsl,spi-num-chipselects = <2>; |
| 19 | cs-gpios = <&gpio4 28 0>, <&gpio4 27 0>; | 19 | cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>, |
| 20 | <&gpio4 27 GPIO_ACTIVE_LOW>; | ||
| 21 | }; | ||
| 22 | |||
| 23 | &i2c1 { | ||
| 24 | clock-frequency = <400000>; | ||
| 25 | pinctrl-names = "default"; | ||
| 26 | pinctrl-0 = <&pinctrl_i2c1>; | ||
| 27 | status = "okay"; | ||
| 28 | |||
| 29 | camgpio: pca9536@41 { | ||
| 30 | compatible = "nxp,pca9536"; | ||
| 31 | reg = <0x41>; | ||
| 32 | gpio-controller; | ||
| 33 | #gpio-cells = <2>; | ||
| 34 | }; | ||
| 35 | }; | ||
| 36 | |||
| 37 | &iomuxc { | ||
| 38 | imx27_phycore_rdk { | ||
| 39 | pinctrl_i2c1: i2c1grp { | ||
| 40 | /* Add pullup to DATA line */ | ||
| 41 | fsl,pins = < | ||
| 42 | MX27_PAD_I2C_DATA__I2C_DATA 0x1 | ||
| 43 | MX27_PAD_I2C_CLK__I2C_CLK 0x0 | ||
| 44 | >; | ||
| 45 | }; | ||
| 46 | |||
| 47 | pinctrl_owire1: owire1grp { | ||
| 48 | fsl,pins = < | ||
| 49 | MX27_PAD_RTCK__OWIRE 0x0 | ||
| 50 | >; | ||
| 51 | }; | ||
| 52 | |||
| 53 | pinctrl_sdhc2: sdhc2grp { | ||
| 54 | fsl,pins = < | ||
| 55 | MX27_PAD_SD2_CLK__SD2_CLK 0x0 | ||
| 56 | MX27_PAD_SD2_CMD__SD2_CMD 0x0 | ||
| 57 | MX27_PAD_SD2_D0__SD2_D0 0x0 | ||
| 58 | MX27_PAD_SD2_D1__SD2_D1 0x0 | ||
| 59 | MX27_PAD_SD2_D2__SD2_D2 0x0 | ||
| 60 | MX27_PAD_SD2_D3__SD2_D3 0x0 | ||
| 61 | MX27_PAD_SSI3_FS__GPIO3_28 0x0 /* WP */ | ||
| 62 | MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */ | ||
| 63 | >; | ||
| 64 | }; | ||
| 65 | |||
| 66 | pinctrl_uart1: uart1grp { | ||
| 67 | fsl,pins = < | ||
| 68 | MX27_PAD_UART1_TXD__UART1_TXD 0x0 | ||
| 69 | MX27_PAD_UART1_RXD__UART1_RXD 0x0 | ||
| 70 | MX27_PAD_UART1_CTS__UART1_CTS 0x0 | ||
| 71 | MX27_PAD_UART1_RTS__UART1_RTS 0x0 | ||
| 72 | >; | ||
| 73 | }; | ||
| 74 | |||
| 75 | pinctrl_uart2: uart2grp { | ||
| 76 | fsl,pins = < | ||
| 77 | MX27_PAD_UART2_TXD__UART2_TXD 0x0 | ||
| 78 | MX27_PAD_UART2_RXD__UART2_RXD 0x0 | ||
| 79 | MX27_PAD_UART2_CTS__UART2_CTS 0x0 | ||
| 80 | MX27_PAD_UART2_RTS__UART2_RTS 0x0 | ||
| 81 | >; | ||
| 82 | }; | ||
| 83 | |||
| 84 | pinctrl_usbh2: usbh2grp { | ||
| 85 | fsl,pins = < | ||
| 86 | MX27_PAD_USBH2_CLK__USBH2_CLK 0x0 | ||
| 87 | MX27_PAD_USBH2_DIR__USBH2_DIR 0x0 | ||
| 88 | MX27_PAD_USBH2_NXT__USBH2_NXT 0x0 | ||
| 89 | MX27_PAD_USBH2_STP__USBH2_STP 0x0 | ||
| 90 | MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0 | ||
| 91 | MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0 | ||
| 92 | MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0 | ||
| 93 | MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0 | ||
| 94 | MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0 | ||
| 95 | MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0 | ||
| 96 | MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0 | ||
| 97 | MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0 | ||
| 98 | >; | ||
| 99 | }; | ||
| 100 | |||
| 101 | pinctrl_weim: weimgrp { | ||
| 102 | fsl,pins = < | ||
| 103 | MX27_PAD_CS4_B__CS4_B 0x0 /* CS4 */ | ||
| 104 | MX27_PAD_SD1_D1__GPIO5_19 0x0 /* CAN IRQ */ | ||
| 105 | >; | ||
| 106 | }; | ||
| 107 | }; | ||
| 108 | }; | ||
| 109 | |||
| 110 | &owire { | ||
| 111 | pinctrl-names = "default"; | ||
| 112 | pinctrl-0 = <&pinctrl_owire1>; | ||
| 113 | status = "okay"; | ||
| 114 | }; | ||
| 115 | |||
| 116 | &pmicleds { | ||
| 117 | ledr1: led@3 { | ||
| 118 | reg = <3>; | ||
| 119 | label = "system:red1:user"; | ||
| 120 | }; | ||
| 121 | |||
| 122 | ledg1: led@4 { | ||
| 123 | reg = <4>; | ||
| 124 | label = "system:green1:user"; | ||
| 125 | }; | ||
| 126 | |||
| 127 | ledb1: led@5 { | ||
| 128 | reg = <5>; | ||
| 129 | label = "system:blue1:user"; | ||
| 130 | }; | ||
| 131 | |||
| 132 | ledr2: led@6 { | ||
| 133 | reg = <6>; | ||
| 134 | label = "system:red2:user"; | ||
| 135 | }; | ||
| 136 | |||
| 137 | ledg2: led@7 { | ||
| 138 | reg = <7>; | ||
| 139 | label = "system:green2:user"; | ||
| 140 | }; | ||
| 141 | |||
| 142 | ledb2: led@8 { | ||
| 143 | reg = <8>; | ||
| 144 | label = "system:blue2:user"; | ||
| 145 | }; | ||
| 146 | |||
| 147 | ledr3: led@9 { | ||
| 148 | reg = <9>; | ||
| 149 | label = "system:red3:nand"; | ||
| 150 | linux,default-trigger = "nand-disk"; | ||
| 151 | }; | ||
| 152 | |||
| 153 | ledg3: led@10 { | ||
| 154 | reg = <10>; | ||
| 155 | label = "system:green3:live"; | ||
| 156 | linux,default-trigger = "heartbeat"; | ||
| 157 | }; | ||
| 158 | |||
| 159 | ledb3: led@11 { | ||
| 160 | reg = <11>; | ||
| 161 | label = "system:blue3:cpu"; | ||
| 162 | linux,default-trigger = "cpu0"; | ||
| 163 | }; | ||
| 20 | }; | 164 | }; |
| 21 | 165 | ||
| 22 | &sdhci2 { | 166 | &sdhci2 { |
| 167 | pinctrl-names = "default"; | ||
| 168 | pinctrl-0 = <&pinctrl_sdhc2>; | ||
| 23 | bus-width = <4>; | 169 | bus-width = <4>; |
| 24 | cd-gpios = <&gpio3 29 0>; | 170 | cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; |
| 25 | wp-gpios = <&gpio3 28 0>; | 171 | wp-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; |
| 26 | vmmc-supply = <&vmmc1_reg>; | 172 | vmmc-supply = <&vmmc1_reg>; |
| 27 | status = "okay"; | 173 | status = "okay"; |
| 28 | }; | 174 | }; |
| 29 | 175 | ||
| 30 | &uart1 { | 176 | &uart1 { |
| 31 | fsl,uart-has-rtscts; | 177 | fsl,uart-has-rtscts; |
| 178 | pinctrl-names = "default"; | ||
| 179 | pinctrl-0 = <&pinctrl_uart1>; | ||
| 180 | status = "okay"; | ||
| 32 | }; | 181 | }; |
| 33 | 182 | ||
| 34 | &uart2 { | 183 | &uart2 { |
| 35 | fsl,uart-has-rtscts; | 184 | fsl,uart-has-rtscts; |
| 185 | pinctrl-names = "default"; | ||
| 186 | pinctrl-0 = <&pinctrl_uart2>; | ||
| 187 | status = "okay"; | ||
| 188 | }; | ||
| 189 | |||
| 190 | &usbh2 { | ||
| 191 | pinctrl-names = "default"; | ||
| 192 | pinctrl-0 = <&pinctrl_usbh2>; | ||
| 193 | dr_mode = "host"; | ||
| 194 | phy_type = "ulpi"; | ||
| 195 | vbus-supply = <®_5v0>; | ||
| 196 | disable-over-current; | ||
| 36 | status = "okay"; | 197 | status = "okay"; |
| 37 | }; | 198 | }; |
| 38 | 199 | ||
| 200 | &usbphy2 { | ||
| 201 | vcc-supply = <®_5v0>; | ||
| 202 | }; | ||
| 203 | |||
| 39 | &weim { | 204 | &weim { |
| 205 | pinctrl-names = "default"; | ||
| 206 | pinctrl-0 = <&pinctrl_weim>; | ||
| 207 | |||
| 40 | can@d4000000 { | 208 | can@d4000000 { |
| 41 | compatible = "nxp,sja1000"; | 209 | compatible = "nxp,sja1000"; |
| 42 | reg = <4 0x00000000 0x00000100>; | 210 | reg = <4 0x00000000 0x00000100>; |
| 43 | interrupt-parent = <&gpio5>; | 211 | interrupt-parent = <&gpio5>; |
| 44 | interrupts = <19 0x2>; | 212 | interrupts = <19 IRQ_TYPE_EDGE_FALLING>; |
| 45 | nxp,external-clock-frequency = <16000000>; | 213 | nxp,external-clock-frequency = <16000000>; |
| 46 | nxp,tx-output-config = <0x16>; | 214 | nxp,tx-output-config = <0x16>; |
| 47 | nxp,no-comparator-bypass; | 215 | nxp,no-comparator-bypass; |
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi index 4ec402c38945..cefaa6994623 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | |||
| @@ -19,6 +19,28 @@ | |||
| 19 | memory { | 19 | memory { |
| 20 | reg = <0xa0000000 0x08000000>; | 20 | reg = <0xa0000000 0x08000000>; |
| 21 | }; | 21 | }; |
| 22 | |||
| 23 | regulators { | ||
| 24 | compatible = "simple-bus"; | ||
| 25 | #address-cells = <1>; | ||
| 26 | #size-cells = <0>; | ||
| 27 | |||
| 28 | reg_3v3: regulator@0 { | ||
| 29 | compatible = "regulator-fixed"; | ||
| 30 | reg = <0>; | ||
| 31 | regulator-name = "3V3"; | ||
| 32 | regulator-min-microvolt = <3300000>; | ||
| 33 | regulator-max-microvolt = <3300000>; | ||
| 34 | }; | ||
| 35 | |||
| 36 | reg_5v0: regulator@1 { | ||
| 37 | compatible = "regulator-fixed"; | ||
| 38 | reg = <1>; | ||
| 39 | regulator-name = "5V0"; | ||
| 40 | regulator-min-microvolt = <5000000>; | ||
| 41 | regulator-max-microvolt = <5000000>; | ||
| 42 | }; | ||
| 43 | }; | ||
| 22 | }; | 44 | }; |
| 23 | 45 | ||
| 24 | &audmux { | 46 | &audmux { |
| @@ -37,21 +59,30 @@ | |||
| 37 | }; | 59 | }; |
| 38 | 60 | ||
| 39 | &cspi1 { | 61 | &cspi1 { |
| 62 | pinctrl-names = "default"; | ||
| 63 | pinctrl-0 = <&pinctrl_cspi1>; | ||
| 40 | fsl,spi-num-chipselects = <1>; | 64 | fsl,spi-num-chipselects = <1>; |
| 41 | cs-gpios = <&gpio4 28 0>; | 65 | cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; |
| 42 | status = "okay"; | 66 | status = "okay"; |
| 43 | 67 | ||
| 44 | pmic: mc13783@0 { | 68 | pmic: mc13783@0 { |
| 45 | #address-cells = <1>; | 69 | #address-cells = <1>; |
| 46 | #size-cells = <0>; | 70 | #size-cells = <0>; |
| 47 | compatible = "fsl,mc13783"; | 71 | compatible = "fsl,mc13783"; |
| 48 | spi-max-frequency = <20000000>; | ||
| 49 | reg = <0>; | 72 | reg = <0>; |
| 73 | spi-cs-high; | ||
| 74 | spi-max-frequency = <20000000>; | ||
| 50 | interrupt-parent = <&gpio2>; | 75 | interrupt-parent = <&gpio2>; |
| 51 | interrupts = <23 0x4>; | 76 | interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; |
| 52 | fsl,mc13xxx-uses-adc; | 77 | fsl,mc13xxx-uses-adc; |
| 53 | fsl,mc13xxx-uses-rtc; | 78 | fsl,mc13xxx-uses-rtc; |
| 54 | 79 | ||
| 80 | pmicleds: leds { | ||
| 81 | #address-cells = <1>; | ||
| 82 | #size-cells = <0>; | ||
| 83 | led-control = <0x001 0x000 0x000 0x000 0x000 0x000>; | ||
| 84 | }; | ||
| 85 | |||
| 55 | regulators { | 86 | regulators { |
| 56 | /* SW1A and SW1B joined operation */ | 87 | /* SW1A and SW1B joined operation */ |
| 57 | sw1_reg: sw1a { | 88 | sw1_reg: sw1a { |
| @@ -134,12 +165,18 @@ | |||
| 134 | }; | 165 | }; |
| 135 | 166 | ||
| 136 | &fec { | 167 | &fec { |
| 137 | phy-reset-gpios = <&gpio3 30 0>; | 168 | phy-mode = "mii"; |
| 169 | phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_HIGH>; | ||
| 170 | phy-supply = <®_3v3>; | ||
| 171 | pinctrl-names = "default"; | ||
| 172 | pinctrl-0 = <&pinctrl_fec1>; | ||
| 138 | status = "okay"; | 173 | status = "okay"; |
| 139 | }; | 174 | }; |
| 140 | 175 | ||
| 141 | &i2c2 { | 176 | &i2c2 { |
| 142 | clock-frequency = <400000>; | 177 | clock-frequency = <400000>; |
| 178 | pinctrl-names = "default"; | ||
| 179 | pinctrl-0 = <&pinctrl_i2c2>; | ||
| 143 | status = "okay"; | 180 | status = "okay"; |
| 144 | 181 | ||
| 145 | at24@52 { | 182 | at24@52 { |
| @@ -159,16 +196,102 @@ | |||
| 159 | }; | 196 | }; |
| 160 | }; | 197 | }; |
| 161 | 198 | ||
| 199 | &iomuxc { | ||
| 200 | imx27_phycore_som { | ||
| 201 | pinctrl_cspi1: cspi1grp { | ||
| 202 | fsl,pins = < | ||
| 203 | MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 | ||
| 204 | MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 | ||
| 205 | MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 | ||
| 206 | MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* SPI1 CS0 */ | ||
| 207 | MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */ | ||
| 208 | >; | ||
| 209 | }; | ||
| 210 | |||
| 211 | pinctrl_fec1: fec1grp { | ||
| 212 | fsl,pins = < | ||
| 213 | MX27_PAD_SD3_CMD__FEC_TXD0 0x0 | ||
| 214 | MX27_PAD_SD3_CLK__FEC_TXD1 0x0 | ||
| 215 | MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 | ||
| 216 | MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 | ||
| 217 | MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 | ||
| 218 | MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 | ||
| 219 | MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 | ||
| 220 | MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 | ||
| 221 | MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 | ||
| 222 | MX27_PAD_ATA_DATA7__FEC_MDC 0x0 | ||
| 223 | MX27_PAD_ATA_DATA8__FEC_CRS 0x0 | ||
| 224 | MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 | ||
| 225 | MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 | ||
| 226 | MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 | ||
| 227 | MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 | ||
| 228 | MX27_PAD_ATA_DATA13__FEC_COL 0x0 | ||
| 229 | MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 | ||
| 230 | MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 | ||
| 231 | MX27_PAD_SSI3_TXDAT__GPIO3_30 0x0 /* FEC RST */ | ||
| 232 | >; | ||
| 233 | }; | ||
| 234 | |||
| 235 | pinctrl_i2c2: i2c2grp { | ||
| 236 | fsl,pins = < | ||
| 237 | MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 | ||
| 238 | MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 | ||
| 239 | >; | ||
| 240 | }; | ||
| 241 | |||
| 242 | pinctrl_nfc: nfcgrp { | ||
| 243 | fsl,pins = < | ||
| 244 | MX27_PAD_NFRB__NFRB 0x0 | ||
| 245 | MX27_PAD_NFCLE__NFCLE 0x0 | ||
| 246 | MX27_PAD_NFWP_B__NFWP_B 0x0 | ||
| 247 | MX27_PAD_NFCE_B__NFCE_B 0x0 | ||
| 248 | MX27_PAD_NFALE__NFALE 0x0 | ||
| 249 | MX27_PAD_NFRE_B__NFRE_B 0x0 | ||
| 250 | MX27_PAD_NFWE_B__NFWE_B 0x0 | ||
| 251 | >; | ||
| 252 | }; | ||
| 253 | |||
| 254 | pinctrl_usbotg: usbotggrp { | ||
| 255 | fsl,pins = < | ||
| 256 | MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 | ||
| 257 | MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 | ||
| 258 | MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 | ||
| 259 | MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 | ||
| 260 | MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 | ||
| 261 | MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 | ||
| 262 | MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 | ||
| 263 | MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 | ||
| 264 | MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 | ||
| 265 | MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 | ||
| 266 | MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 | ||
| 267 | MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 | ||
| 268 | >; | ||
| 269 | }; | ||
| 270 | }; | ||
| 271 | }; | ||
| 272 | |||
| 162 | &nfc { | 273 | &nfc { |
| 274 | pinctrl-names = "default"; | ||
| 275 | pinctrl-0 = <&pinctrl_nfc>; | ||
| 163 | nand-bus-width = <8>; | 276 | nand-bus-width = <8>; |
| 164 | nand-ecc-mode = "hw"; | 277 | nand-ecc-mode = "hw"; |
| 278 | nand-on-flash-bbt; | ||
| 165 | status = "okay"; | 279 | status = "okay"; |
| 166 | }; | 280 | }; |
| 167 | 281 | ||
| 168 | &uart1 { | 282 | &usbotg { |
| 283 | pinctrl-names = "default"; | ||
| 284 | pinctrl-0 = <&pinctrl_usbotg>; | ||
| 285 | dr_mode = "otg"; | ||
| 286 | phy_type = "ulpi"; | ||
| 287 | vbus-supply = <&sw3_reg>; | ||
| 169 | status = "okay"; | 288 | status = "okay"; |
| 170 | }; | 289 | }; |
| 171 | 290 | ||
| 291 | &usbphy0 { | ||
| 292 | vcc-supply = <&sw3_reg>; | ||
| 293 | }; | ||
| 294 | |||
| 172 | &weim { | 295 | &weim { |
| 173 | status = "okay"; | 296 | status = "okay"; |
| 174 | 297 | ||
diff --git a/arch/arm/boot/dts/imx27-pinfunc.h b/arch/arm/boot/dts/imx27-pinfunc.h new file mode 100644 index 000000000000..f5387b4de577 --- /dev/null +++ b/arch/arm/boot/dts/imx27-pinfunc.h | |||
| @@ -0,0 +1,526 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Markus Pargmann <mpa@pengutronix.de>, Pengutronix | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __DTS_IMX27_PINFUNC_H | ||
| 13 | #define __DTS_IMX27_PINFUNC_H | ||
| 14 | |||
| 15 | /* | ||
| 16 | * The pin function ID is a tuple of | ||
| 17 | * <pin mux_id> | ||
| 18 | * mux_id consists of | ||
| 19 | * function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10) | ||
| 20 | * | ||
| 21 | * function: 0 - Primary function | ||
| 22 | * 1 - Alternate function | ||
| 23 | * 2 - GPIO | ||
| 24 | * direction: 0 - Input | ||
| 25 | * 1 - Output | ||
| 26 | * gpio_oconf: 0 - A_IN | ||
| 27 | * 1 - B_IN | ||
| 28 | * 2 - C_IN | ||
| 29 | * 3 - Data Register | ||
| 30 | * gpio_iconfa/b: 0 - GPIO_IN | ||
| 31 | * 1 - Interrupt Status Register | ||
| 32 | * 2 - 0 | ||
| 33 | * 3 - 1 | ||
| 34 | * | ||
| 35 | * 'pin' is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable | ||
| 36 | * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin | ||
| 37 | * number on the specific port (between 0 and 31). | ||
| 38 | */ | ||
| 39 | |||
| 40 | #define MX27_PAD_USBH2_CLK__USBH2_CLK 0x00 0x000 | ||
| 41 | #define MX27_PAD_USBH2_CLK__GPIO1_0 0x00 0x032 | ||
| 42 | #define MX27_PAD_USBH2_DIR__USBH2_DIR 0x01 0x000 | ||
| 43 | #define MX27_PAD_USBH2_DIR__GPIO1_1 0x01 0x032 | ||
| 44 | #define MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x02 0x004 | ||
| 45 | #define MX27_PAD_USBH2_DATA7__GPIO1_2 0x02 0x032 | ||
| 46 | #define MX27_PAD_USBH2_NXT__USBH2_NXT 0x03 0x000 | ||
| 47 | #define MX27_PAD_USBH2_NXT__GPIO1_3 0x03 0x032 | ||
| 48 | #define MX27_PAD_USBH2_STP__USBH2_STP 0x04 0x004 | ||
| 49 | #define MX27_PAD_USBH2_STP__GPIO1_4 0x04 0x032 | ||
| 50 | #define MX27_PAD_LSCLK__LSCLK 0x05 0x004 | ||
| 51 | #define MX27_PAD_LSCLK__GPIO1_5 0x05 0x032 | ||
| 52 | #define MX27_PAD_LD0__LD0 0x06 0x004 | ||
| 53 | #define MX27_PAD_LD0__GPIO1_6 0x06 0x032 | ||
| 54 | #define MX27_PAD_LD1__LD1 0x07 0x004 | ||
| 55 | #define MX27_PAD_LD1__GPIO1_7 0x07 0x032 | ||
| 56 | #define MX27_PAD_LD2__LD2 0x08 0x004 | ||
| 57 | #define MX27_PAD_LD2__GPIO1_8 0x08 0x032 | ||
| 58 | #define MX27_PAD_LD3__LD3 0x09 0x004 | ||
| 59 | #define MX27_PAD_LD3__GPIO1_9 0x09 0x032 | ||
| 60 | #define MX27_PAD_LD4__LD4 0x0a 0x004 | ||
| 61 | #define MX27_PAD_LD4__GPIO1_10 0x0a 0x032 | ||
| 62 | #define MX27_PAD_LD5__LD5 0x0b 0x004 | ||
| 63 | #define MX27_PAD_LD5__GPIO1_11 0x0b 0x032 | ||
| 64 | #define MX27_PAD_LD6__LD6 0x0c 0x004 | ||
| 65 | #define MX27_PAD_LD6__GPIO1_12 0x0c 0x032 | ||
| 66 | #define MX27_PAD_LD7__LD7 0x0d 0x004 | ||
| 67 | #define MX27_PAD_LD7__GPIO1_13 0x0d 0x032 | ||
| 68 | #define MX27_PAD_LD8__LD8 0x0e 0x004 | ||
| 69 | #define MX27_PAD_LD8__GPIO1_14 0x0e 0x032 | ||
| 70 | #define MX27_PAD_LD9__LD9 0x0f 0x004 | ||
| 71 | #define MX27_PAD_LD9__GPIO1_15 0x0f 0x032 | ||
| 72 | #define MX27_PAD_LD10__LD10 0x10 0x004 | ||
| 73 | #define MX27_PAD_LD10__GPIO1_16 0x10 0x032 | ||
| 74 | #define MX27_PAD_LD11__LD11 0x11 0x004 | ||
| 75 | #define MX27_PAD_LD11__GPIO1_17 0x11 0x032 | ||
| 76 | #define MX27_PAD_LD12__LD12 0x12 0x004 | ||
| 77 | #define MX27_PAD_LD12__GPIO1_18 0x12 0x032 | ||
| 78 | #define MX27_PAD_LD13__LD13 0x13 0x004 | ||
| 79 | #define MX27_PAD_LD13__GPIO1_19 0x13 0x032 | ||
| 80 | #define MX27_PAD_LD14__LD14 0x14 0x004 | ||
| 81 | #define MX27_PAD_LD14__GPIO1_20 0x14 0x032 | ||
| 82 | #define MX27_PAD_LD15__LD15 0x15 0x004 | ||
| 83 | #define MX27_PAD_LD15__GPIO1_21 0x15 0x032 | ||
| 84 | #define MX27_PAD_LD16__LD16 0x16 0x004 | ||
| 85 | #define MX27_PAD_LD16__GPIO1_22 0x16 0x032 | ||
| 86 | #define MX27_PAD_LD17__LD17 0x17 0x004 | ||
| 87 | #define MX27_PAD_LD17__GPIO1_23 0x17 0x032 | ||
| 88 | #define MX27_PAD_REV__REV 0x18 0x004 | ||
| 89 | #define MX27_PAD_REV__GPIO1_24 0x18 0x032 | ||
| 90 | #define MX27_PAD_CLS__CLS 0x19 0x004 | ||
| 91 | #define MX27_PAD_CLS__GPIO1_25 0x19 0x032 | ||
| 92 | #define MX27_PAD_PS__PS 0x1a 0x004 | ||
| 93 | #define MX27_PAD_PS__GPIO1_26 0x1a 0x032 | ||
| 94 | #define MX27_PAD_SPL_SPR__SPL_SPR 0x1b 0x004 | ||
| 95 | #define MX27_PAD_SPL_SPR__GPIO1_27 0x1b 0x032 | ||
| 96 | #define MX27_PAD_HSYNC__HSYNC 0x1c 0x004 | ||
| 97 | #define MX27_PAD_HSYNC__GPIO1_28 0x1c 0x032 | ||
| 98 | #define MX27_PAD_VSYNC__VSYNC 0x1d 0x004 | ||
| 99 | #define MX27_PAD_VSYNC__GPIO1_29 0x1d 0x032 | ||
| 100 | #define MX27_PAD_CONTRAST__CONTRAST 0x1e 0x004 | ||
| 101 | #define MX27_PAD_CONTRAST__GPIO1_30 0x1e 0x032 | ||
| 102 | #define MX27_PAD_OE_ACD__OE_ACD 0x1f 0x004 | ||
| 103 | #define MX27_PAD_OE_ACD__GPIO1_31 0x1f 0x032 | ||
| 104 | #define MX27_PAD_UNUSED0__UNUSED0 0x20 0x004 | ||
| 105 | #define MX27_PAD_UNUSED0__GPIO2_0 0x20 0x032 | ||
| 106 | #define MX27_PAD_UNUSED1__UNUSED1 0x21 0x004 | ||
| 107 | #define MX27_PAD_UNUSED1__GPIO2_1 0x21 0x032 | ||
| 108 | #define MX27_PAD_UNUSED2__UNUSED2 0x22 0x004 | ||
| 109 | #define MX27_PAD_UNUSED2__GPIO2_2 0x22 0x032 | ||
| 110 | #define MX27_PAD_UNUSED3__UNUSED3 0x23 0x004 | ||
| 111 | #define MX27_PAD_UNUSED3__GPIO2_3 0x23 0x032 | ||
| 112 | #define MX27_PAD_SD2_D0__SD2_D0 0x24 0x004 | ||
| 113 | #define MX27_PAD_SD2_D0__MSHC_DATA0 0x24 0x005 | ||
| 114 | #define MX27_PAD_SD2_D0__GPIO2_4 0x24 0x032 | ||
| 115 | #define MX27_PAD_SD2_D1__SD2_D1 0x25 0x004 | ||
| 116 | #define MX27_PAD_SD2_D1__MSHC_DATA1 0x25 0x005 | ||
| 117 | #define MX27_PAD_SD2_D1__GPIO2_5 0x25 0x032 | ||
| 118 | #define MX27_PAD_SD2_D2__SD2_D2 0x26 0x004 | ||
| 119 | #define MX27_PAD_SD2_D2__MSHC_DATA2 0x26 0x005 | ||
| 120 | #define MX27_PAD_SD2_D2__GPIO2_6 0x26 0x032 | ||
| 121 | #define MX27_PAD_SD2_D3__SD2_D3 0x27 0x004 | ||
| 122 | #define MX27_PAD_SD2_D3__MSHC_DATA3 0x27 0x005 | ||
| 123 | #define MX27_PAD_SD2_D3__GPIO2_7 0x27 0x032 | ||
| 124 | #define MX27_PAD_SD2_CMD__SD2_CMD 0x28 0x004 | ||
| 125 | #define MX27_PAD_SD2_CMD__MSHC_BS 0x28 0x005 | ||
| 126 | #define MX27_PAD_SD2_CMD__GPIO2_8 0x28 0x032 | ||
| 127 | #define MX27_PAD_SD2_CLK__SD2_CLK 0x29 0x004 | ||
| 128 | #define MX27_PAD_SD2_CLK__MSHC_SCLK 0x29 0x005 | ||
| 129 | #define MX27_PAD_SD2_CLK__GPIO2_9 0x29 0x032 | ||
| 130 | #define MX27_PAD_CSI_D0__CSI_D0 0x2a 0x000 | ||
| 131 | #define MX27_PAD_CSI_D0__UART6_TXD 0x2a 0x005 | ||
| 132 | #define MX27_PAD_CSI_D0__GPIO2_10 0x2a 0x032 | ||
| 133 | #define MX27_PAD_CSI_D1__CSI_D1 0x2b 0x000 | ||
| 134 | #define MX27_PAD_CSI_D1__UART6_RXD 0x2b 0x001 | ||
| 135 | #define MX27_PAD_CSI_D1__GPIO2_11 0x2b 0x032 | ||
| 136 | #define MX27_PAD_CSI_D2__CSI_D2 0x2c 0x000 | ||
| 137 | #define MX27_PAD_CSI_D2__UART6_CTS 0x2c 0x005 | ||
| 138 | #define MX27_PAD_CSI_D2__GPIO2_12 0x2c 0x032 | ||
| 139 | #define MX27_PAD_CSI_D3__CSI_D3 0x2d 0x000 | ||
| 140 | #define MX27_PAD_CSI_D3__UART6_RTS 0x2d 0x001 | ||
| 141 | #define MX27_PAD_CSI_D3__GPIO2_13 0x2d 0x032 | ||
| 142 | #define MX27_PAD_CSI_D4__CSI_D4 0x2e 0x000 | ||
| 143 | #define MX27_PAD_CSI_D4__GPIO2_14 0x2e 0x032 | ||
| 144 | #define MX27_PAD_CSI_MCLK__CSI_MCLK 0x2f 0x004 | ||
| 145 | #define MX27_PAD_CSI_MCLK__GPIO2_15 0x2f 0x032 | ||
| 146 | #define MX27_PAD_CSI_PIXCLK__CSI_PIXCLK 0x30 0x000 | ||
| 147 | #define MX27_PAD_CSI_PIXCLK__GPIO2_16 0x30 0x032 | ||
| 148 | #define MX27_PAD_CSI_D5__CSI_D5 0x31 0x000 | ||
| 149 | #define MX27_PAD_CSI_D5__GPIO2_17 0x31 0x032 | ||
| 150 | #define MX27_PAD_CSI_D6__CSI_D6 0x32 0x000 | ||
| 151 | #define MX27_PAD_CSI_D6__UART5_TXD 0x32 0x005 | ||
| 152 | #define MX27_PAD_CSI_D6__GPIO2_18 0x32 0x032 | ||
| 153 | #define MX27_PAD_CSI_D7__CSI_D7 0x33 0x000 | ||
| 154 | #define MX27_PAD_CSI_D7__UART5_RXD 0x33 0x001 | ||
| 155 | #define MX27_PAD_CSI_D7__GPIO2_19 0x33 0x032 | ||
| 156 | #define MX27_PAD_CSI_VSYNC__CSI_VSYNC 0x34 0x000 | ||
| 157 | #define MX27_PAD_CSI_VSYNC__UART5_CTS 0x34 0x005 | ||
| 158 | #define MX27_PAD_CSI_VSYNC__GPIO2_20 0x34 0x032 | ||
| 159 | #define MX27_PAD_CSI_HSYNC__CSI_HSYNC 0x35 0x000 | ||
| 160 | #define MX27_PAD_CSI_HSYNC__UART5_RTS 0x35 0x001 | ||
| 161 | #define MX27_PAD_CSI_HSYNC__GPIO2_21 0x35 0x032 | ||
| 162 | #define MX27_PAD_USBH1_SUSP__USBH1_SUSP 0x36 0x004 | ||
| 163 | #define MX27_PAD_USBH1_SUSP__GPIO2_22 0x36 0x032 | ||
| 164 | #define MX27_PAD_USB_PWR__USB_PWR 0x37 0x004 | ||
| 165 | #define MX27_PAD_USB_PWR__GPIO2_23 0x37 0x032 | ||
| 166 | #define MX27_PAD_USB_OC_B__USB_OC_B 0x38 0x000 | ||
| 167 | #define MX27_PAD_USB_OC_B__GPIO2_24 0x38 0x032 | ||
| 168 | #define MX27_PAD_USBH1_RCV__USBH1_RCV 0x39 0x004 | ||
| 169 | #define MX27_PAD_USBH1_RCV__GPIO2_25 0x39 0x032 | ||
| 170 | #define MX27_PAD_USBH1_FS__USBH1_FS 0x3a 0x004 | ||
| 171 | #define MX27_PAD_USBH1_FS__UART4_RTS 0x3a 0x001 | ||
| 172 | #define MX27_PAD_USBH1_FS__GPIO2_26 0x3a 0x032 | ||
| 173 | #define MX27_PAD_USBH1_OE_B__USBH1_OE_B 0x3b 0x004 | ||
| 174 | #define MX27_PAD_USBH1_OE_B__GPIO2_27 0x3b 0x032 | ||
| 175 | #define MX27_PAD_USBH1_TXDM__USBH1_TXDM 0x3c 0x004 | ||
| 176 | #define MX27_PAD_USBH1_TXDM__UART4_TXD 0x3c 0x005 | ||
| 177 | #define MX27_PAD_USBH1_TXDM__GPIO2_28 0x3c 0x032 | ||
| 178 | #define MX27_PAD_USBH1_TXDP__USBH1_TXDP 0x3d 0x004 | ||
| 179 | #define MX27_PAD_USBH1_TXDP__UART4_CTS 0x3d 0x005 | ||
| 180 | #define MX27_PAD_USBH1_TXDP__GPIO2_29 0x3d 0x032 | ||
| 181 | #define MX27_PAD_USBH1_RXDM__USBH1_RXDM 0x3e 0x004 | ||
| 182 | #define MX27_PAD_USBH1_RXDM__GPIO2_30 0x3e 0x032 | ||
| 183 | #define MX27_PAD_USBH1_RXDP__USBH1_RXDP 0x3f 0x004 | ||
| 184 | #define MX27_PAD_USBH1_RXDP__UART4_RXD 0x3f 0x001 | ||
| 185 | #define MX27_PAD_USBH1_RXDP__GPIO2_31 0x3f 0x032 | ||
| 186 | #define MX27_PAD_UNUSED4__UNUSED4 0x40 0x004 | ||
| 187 | #define MX27_PAD_UNUSED4__GPIO3_0 0x40 0x032 | ||
| 188 | #define MX27_PAD_UNUSED5__UNUSED5 0x41 0x004 | ||
| 189 | #define MX27_PAD_UNUSED5__GPIO3_1 0x41 0x032 | ||
| 190 | #define MX27_PAD_UNUSED6__UNUSED6 0x42 0x004 | ||
| 191 | #define MX27_PAD_UNUSED6__GPIO3_2 0x42 0x032 | ||
| 192 | #define MX27_PAD_UNUSED7__UNUSED7 0x43 0x004 | ||
| 193 | #define MX27_PAD_UNUSED7__GPIO3_3 0x43 0x032 | ||
| 194 | #define MX27_PAD_UNUSED8__UNUSED8 0x44 0x004 | ||
| 195 | #define MX27_PAD_UNUSED8__GPIO3_4 0x44 0x032 | ||
| 196 | #define MX27_PAD_I2C2_SDA__I2C2_SDA 0x45 0x004 | ||
| 197 | #define MX27_PAD_I2C2_SDA__GPIO3_5 0x45 0x032 | ||
| 198 | #define MX27_PAD_I2C2_SCL__I2C2_SCL 0x46 0x004 | ||
| 199 | #define MX27_PAD_I2C2_SCL__GPIO3_6 0x46 0x032 | ||
| 200 | #define MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x47 0x004 | ||
| 201 | #define MX27_PAD_USBOTG_DATA5__GPIO3_7 0x47 0x032 | ||
| 202 | #define MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x48 0x004 | ||
| 203 | #define MX27_PAD_USBOTG_DATA6__GPIO3_8 0x48 0x032 | ||
| 204 | #define MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x49 0x004 | ||
| 205 | #define MX27_PAD_USBOTG_DATA0__GPIO3_9 0x49 0x032 | ||
| 206 | #define MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x4a 0x004 | ||
| 207 | #define MX27_PAD_USBOTG_DATA2__GPIO3_10 0x4a 0x032 | ||
| 208 | #define MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x4b 0x004 | ||
| 209 | #define MX27_PAD_USBOTG_DATA1__GPIO3_11 0x4b 0x032 | ||
| 210 | #define MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x4c 0x004 | ||
| 211 | #define MX27_PAD_USBOTG_DATA4__GPIO3_12 0x4c 0x032 | ||
| 212 | #define MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x4d 0x004 | ||
| 213 | #define MX27_PAD_USBOTG_DATA3__GPIO3_13 0x4d 0x032 | ||
| 214 | #define MX27_PAD_TOUT__TOUT 0x4e 0x004 | ||
| 215 | #define MX27_PAD_TOUT__GPIO3_14 0x4e 0x032 | ||
| 216 | #define MX27_PAD_TIN__TIN 0x4f 0x000 | ||
| 217 | #define MX27_PAD_TIN__GPIO3_15 0x4f 0x032 | ||
| 218 | #define MX27_PAD_SSI4_FS__SSI4_FS 0x50 0x004 | ||
| 219 | #define MX27_PAD_SSI4_FS__GPIO3_16 0x50 0x032 | ||
| 220 | #define MX27_PAD_SSI4_RXDAT__SSI4_RXDAT 0x51 0x004 | ||
| 221 | #define MX27_PAD_SSI4_RXDAT__GPIO3_17 0x51 0x032 | ||
| 222 | #define MX27_PAD_SSI4_TXDAT__SSI4_TXDAT 0x52 0x004 | ||
| 223 | #define MX27_PAD_SSI4_TXDAT__GPIO3_18 0x52 0x032 | ||
| 224 | #define MX27_PAD_SSI4_CLK__SSI4_CLK 0x53 0x004 | ||
| 225 | #define MX27_PAD_SSI4_CLK__GPIO3_19 0x53 0x032 | ||
| 226 | #define MX27_PAD_SSI1_FS__SSI1_FS 0x54 0x004 | ||
| 227 | #define MX27_PAD_SSI1_FS__GPIO3_20 0x54 0x032 | ||
| 228 | #define MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x55 0x004 | ||
| 229 | #define MX27_PAD_SSI1_RXDAT__GPIO3_21 0x55 0x032 | ||
| 230 | #define MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x56 0x004 | ||
| 231 | #define MX27_PAD_SSI1_TXDAT__GPIO3_22 0x56 0x032 | ||
| 232 | #define MX27_PAD_SSI1_CLK__SSI1_CLK 0x57 0x004 | ||
| 233 | #define MX27_PAD_SSI1_CLK__GPIO3_23 0x57 0x032 | ||
| 234 | #define MX27_PAD_SSI2_FS__SSI2_FS 0x58 0x004 | ||
| 235 | #define MX27_PAD_SSI2_FS__GPT5_TOUT 0x58 0x005 | ||
| 236 | #define MX27_PAD_SSI2_FS__GPIO3_24 0x58 0x032 | ||
| 237 | #define MX27_PAD_SSI2_RXDAT__SSI2_RXDAT 0x59 0x004 | ||
| 238 | #define MX27_PAD_SSI2_RXDAT__GPTS_TIN 0x59 0x001 | ||
| 239 | #define MX27_PAD_SSI2_RXDAT__GPIO3_25 0x59 0x032 | ||
| 240 | #define MX27_PAD_SSI2_TXDAT__SSI2_TXDAT 0x5a 0x004 | ||
| 241 | #define MX27_PAD_SSI2_TXDAT__GPT4_TOUT 0x5a 0x005 | ||
| 242 | #define MX27_PAD_SSI2_TXDAT__GPIO3_26 0x5a 0x032 | ||
| 243 | #define MX27_PAD_SSI2_CLK__SSI2_CLK 0x5b 0x004 | ||
| 244 | #define MX27_PAD_SSI2_CLK__GPT4_TIN 0x5b 0x001 | ||
| 245 | #define MX27_PAD_SSI2_CLK__GPIO3_27 0x5b 0x032 | ||
| 246 | #define MX27_PAD_SSI3_FS__SSI3_FS 0x5c 0x004 | ||
| 247 | #define MX27_PAD_SSI3_FS__SLCDC2_D0 0x5c 0x001 | ||
| 248 | #define MX27_PAD_SSI3_FS__GPIO3_28 0x5c 0x032 | ||
| 249 | #define MX27_PAD_SSI3_RXDAT__SSI3_RXDAT 0x5d 0x004 | ||
| 250 | #define MX27_PAD_SSI3_RXDAT__SLCDC2_RS 0x5d 0x001 | ||
| 251 | #define MX27_PAD_SSI3_RXDAT__GPIO3_29 0x5d 0x032 | ||
| 252 | #define MX27_PAD_SSI3_TXDAT__SSI3_TXDAT 0x5e 0x004 | ||
| 253 | #define MX27_PAD_SSI3_TXDAT__SLCDC2_CS 0x5e 0x001 | ||
| 254 | #define MX27_PAD_SSI3_TXDAT__GPIO3_30 0x5e 0x032 | ||
| 255 | #define MX27_PAD_SSI3_CLK__SSI3_CLK 0x5f 0x004 | ||
| 256 | #define MX27_PAD_SSI3_CLK__SLCDC2_CLK 0x5f 0x001 | ||
| 257 | #define MX27_PAD_SSI3_CLK__GPIO3_31 0x5f 0x032 | ||
| 258 | #define MX27_PAD_SD3_CMD__SD3_CMD 0x60 0x004 | ||
| 259 | #define MX27_PAD_SD3_CMD__FEC_TXD0 0x60 0x006 | ||
| 260 | #define MX27_PAD_SD3_CMD__GPIO4_0 0x60 0x032 | ||
| 261 | #define MX27_PAD_SD3_CLK__SD3_CLK 0x61 0x004 | ||
| 262 | #define MX27_PAD_SD3_CLK__ETMTRACEPKT15 0x61 0x005 | ||
| 263 | #define MX27_PAD_SD3_CLK__FEC_TXD1 0x61 0x006 | ||
| 264 | #define MX27_PAD_SD3_CLK__GPIO4_1 0x61 0x032 | ||
| 265 | #define MX27_PAD_ATA_DATA0__ATA_DATA0 0x62 0x004 | ||
| 266 | #define MX27_PAD_ATA_DATA0__SD3_D0 0x62 0x005 | ||
| 267 | #define MX27_PAD_ATA_DATA0__FEC_TXD2 0x62 0x006 | ||
| 268 | #define MX27_PAD_ATA_DATA0__GPIO4_2 0x62 0x032 | ||
| 269 | #define MX27_PAD_ATA_DATA1__ATA_DATA1 0x63 0x004 | ||
| 270 | #define MX27_PAD_ATA_DATA1__SD3_D1 0x63 0x005 | ||
| 271 | #define MX27_PAD_ATA_DATA1__FEC_TXD3 0x63 0x006 | ||
| 272 | #define MX27_PAD_ATA_DATA1__GPIO4_3 0x63 0x032 | ||
| 273 | #define MX27_PAD_ATA_DATA2__ATA_DATA2 0x64 0x004 | ||
| 274 | #define MX27_PAD_ATA_DATA2__SD3_D2 0x64 0x005 | ||
| 275 | #define MX27_PAD_ATA_DATA2__FEC_RX_ER 0x64 0x002 | ||
| 276 | #define MX27_PAD_ATA_DATA2__GPIO4_4 0x64 0x032 | ||
| 277 | #define MX27_PAD_ATA_DATA3__ATA_DATA3 0x65 0x004 | ||
| 278 | #define MX27_PAD_ATA_DATA3__SD3_D3 0x65 0x005 | ||
| 279 | #define MX27_PAD_ATA_DATA3__FEC_RXD1 0x65 0x002 | ||
| 280 | #define MX27_PAD_ATA_DATA3__GPIO4_5 0x65 0x032 | ||
| 281 | #define MX27_PAD_ATA_DATA4__ATA_DATA4 0x66 0x004 | ||
| 282 | #define MX27_PAD_ATA_DATA4__ETMTRACEPKT14 0x66 0x005 | ||
| 283 | #define MX27_PAD_ATA_DATA4__FEC_RXD2 0x66 0x002 | ||
| 284 | #define MX27_PAD_ATA_DATA4__GPIO4_6 0x66 0x032 | ||
| 285 | #define MX27_PAD_ATA_DATA5__ATA_DATA5 0x67 0x004 | ||
| 286 | #define MX27_PAD_ATA_DATA5__ETMTRACEPKT13 0x67 0x005 | ||
| 287 | #define MX27_PAD_ATA_DATA5__FEC_RXD3 0x67 0x002 | ||
| 288 | #define MX27_PAD_ATA_DATA5__GPIO4_7 0x67 0x032 | ||
| 289 | #define MX27_PAD_ATA_DATA6__ATA_DATA6 0x68 0x004 | ||
| 290 | #define MX27_PAD_ATA_DATA6__FEC_MDIO 0x68 0x005 | ||
| 291 | #define MX27_PAD_ATA_DATA6__GPIO4_8 0x68 0x032 | ||
| 292 | #define MX27_PAD_ATA_DATA7__ATA_DATA7 0x69 0x004 | ||
| 293 | #define MX27_PAD_ATA_DATA7__ETMTRACEPKT12 0x69 0x005 | ||
| 294 | #define MX27_PAD_ATA_DATA7__FEC_MDC 0x69 0x006 | ||
| 295 | #define MX27_PAD_ATA_DATA7__GPIO4_9 0x69 0x032 | ||
| 296 | #define MX27_PAD_ATA_DATA8__ATA_DATA8 0x6a 0x004 | ||
| 297 | #define MX27_PAD_ATA_DATA8__ETMTRACEPKT11 0x6a 0x005 | ||
| 298 | #define MX27_PAD_ATA_DATA8__FEC_CRS 0x6a 0x002 | ||
| 299 | #define MX27_PAD_ATA_DATA8__GPIO4_10 0x6a 0x032 | ||
| 300 | #define MX27_PAD_ATA_DATA9__ATA_DATA9 0x6b 0x004 | ||
| 301 | #define MX27_PAD_ATA_DATA9__ETMTRACEPKT10 0x6b 0x005 | ||
| 302 | #define MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x6b 0x002 | ||
| 303 | #define MX27_PAD_ATA_DATA9__GPIO4_11 0x6b 0x032 | ||
| 304 | #define MX27_PAD_ATA_DATA10__ATA_DATA10 0x6c 0x004 | ||
| 305 | #define MX27_PAD_ATA_DATA10__ETMTRACEPKT9 0x6c 0x005 | ||
| 306 | #define MX27_PAD_ATA_DATA10__FEC_RXD0 0x6c 0x002 | ||
| 307 | #define MX27_PAD_ATA_DATA10__GPIO4_12 0x6c 0x032 | ||
| 308 | #define MX27_PAD_ATA_DATA11__ATA_DATA11 0x6d 0x004 | ||
| 309 | #define MX27_PAD_ATA_DATA11__ETMTRACEPKT8 0x6d 0x005 | ||
| 310 | #define MX27_PAD_ATA_DATA11__FEC_RX_DV 0x6d 0x002 | ||
| 311 | #define MX27_PAD_ATA_DATA11__GPIO4_13 0x6d 0x032 | ||
| 312 | #define MX27_PAD_ATA_DATA12__ATA_DATA12 0x6e 0x004 | ||
| 313 | #define MX27_PAD_ATA_DATA12__ETMTRACEPKT7 0x6e 0x005 | ||
| 314 | #define MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x6e 0x002 | ||
| 315 | #define MX27_PAD_ATA_DATA12__GPIO4_14 0x6e 0x032 | ||
| 316 | #define MX27_PAD_ATA_DATA13__ATA_DATA13 0x6f 0x004 | ||
| 317 | #define MX27_PAD_ATA_DATA13__ETMTRACEPKT6 0x6f 0x005 | ||
| 318 | #define MX27_PAD_ATA_DATA13__FEC_COL 0x6f 0x002 | ||
| 319 | #define MX27_PAD_ATA_DATA13__GPIO4_15 0x6f 0x032 | ||
| 320 | #define MX27_PAD_ATA_DATA14__ATA_DATA14 0x70 0x004 | ||
| 321 | #define MX27_PAD_ATA_DATA14__ETMTRACEPKT5 0x70 0x005 | ||
| 322 | #define MX27_PAD_ATA_DATA14__FEC_TX_ER 0x70 0x006 | ||
| 323 | #define MX27_PAD_ATA_DATA14__GPIO4_16 0x70 0x032 | ||
| 324 | #define MX27_PAD_I2C_DATA__I2C_DATA 0x71 0x004 | ||
| 325 | #define MX27_PAD_I2C_DATA__GPIO4_17 0x71 0x032 | ||
| 326 | #define MX27_PAD_I2C_CLK__I2C_CLK 0x72 0x004 | ||
| 327 | #define MX27_PAD_I2C_CLK__GPIO4_18 0x72 0x032 | ||
| 328 | #define MX27_PAD_CSPI2_SS2__CSPI2_SS2 0x73 0x004 | ||
| 329 | #define MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x73 0x005 | ||
| 330 | #define MX27_PAD_CSPI2_SS2__GPIO4_19 0x73 0x032 | ||
| 331 | #define MX27_PAD_CSPI2_SS1__CSPI2_SS1 0x74 0x004 | ||
| 332 | #define MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x74 0x005 | ||
| 333 | #define MX27_PAD_CSPI2_SS1__GPIO4_20 0x74 0x032 | ||
| 334 | #define MX27_PAD_CSPI2_SS0__CSPI2_SS0 0x75 0x004 | ||
| 335 | #define MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x75 0x005 | ||
| 336 | #define MX27_PAD_CSPI2_SS0__GPIO4_21 0x75 0x032 | ||
| 337 | #define MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x76 0x004 | ||
| 338 | #define MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x76 0x005 | ||
| 339 | #define MX27_PAD_CSPI2_SCLK__GPIO4_22 0x76 0x032 | ||
| 340 | #define MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x77 0x004 | ||
| 341 | #define MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x77 0x005 | ||
| 342 | #define MX27_PAD_CSPI2_MISO__GPIO4_23 0x77 0x032 | ||
| 343 | #define MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x78 0x004 | ||
| 344 | #define MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x78 0x005 | ||
| 345 | #define MX27_PAD_CSPI2_MOSI__GPIO4_24 0x78 0x032 | ||
| 346 | #define MX27_PAD_CSPI1_RDY__CSPI1_RDY 0x79 0x000 | ||
| 347 | #define MX27_PAD_CSPI1_RDY__GPIO4_25 0x79 0x032 | ||
| 348 | #define MX27_PAD_CSPI1_SS2__CSPI1_SS2 0x7a 0x004 | ||
| 349 | #define MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x7a 0x005 | ||
| 350 | #define MX27_PAD_CSPI1_SS2__GPIO4_26 0x7a 0x032 | ||
| 351 | #define MX27_PAD_CSPI1_SS1__CSPI1_SS1 0x7b 0x004 | ||
| 352 | #define MX27_PAD_CSPI1_SS1__GPIO4_27 0x7b 0x032 | ||
| 353 | #define MX27_PAD_CSPI1_SS0__CSPI1_SS0 0x7c 0x004 | ||
| 354 | #define MX27_PAD_CSPI1_SS0__GPIO4_28 0x7c 0x032 | ||
| 355 | #define MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x7d 0x004 | ||
| 356 | #define MX27_PAD_CSPI1_SCLK__GPIO4_29 0x7d 0x032 | ||
| 357 | #define MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x7e 0x004 | ||
| 358 | #define MX27_PAD_CSPI1_MISO__GPIO4_30 0x7e 0x032 | ||
| 359 | #define MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x7f 0x004 | ||
| 360 | #define MX27_PAD_CSPI1_MOSI__GPIO4_31 0x7f 0x032 | ||
| 361 | #define MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x80 0x000 | ||
| 362 | #define MX27_PAD_USBOTG_NXT__KP_COL6A 0x80 0x005 | ||
| 363 | #define MX27_PAD_USBOTG_NXT__GPIO5_0 0x80 0x032 | ||
| 364 | #define MX27_PAD_USBOTG_STP__USBOTG_STP 0x81 0x004 | ||
| 365 | #define MX27_PAD_USBOTG_STP__KP_ROW6A 0x81 0x005 | ||
| 366 | #define MX27_PAD_USBOTG_STP__GPIO5_1 0x81 0x032 | ||
| 367 | #define MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x82 0x000 | ||
| 368 | #define MX27_PAD_USBOTG_DIR__KP_ROW7A 0x82 0x005 | ||
| 369 | #define MX27_PAD_USBOTG_DIR__GPIO5_2 0x82 0x032 | ||
| 370 | #define MX27_PAD_UART2_CTS__UART2_CTS 0x83 0x004 | ||
| 371 | #define MX27_PAD_UART2_CTS__KP_COL7 0x83 0x005 | ||
| 372 | #define MX27_PAD_UART2_CTS__GPIO5_3 0x83 0x032 | ||
| 373 | #define MX27_PAD_UART2_RTS__UART2_RTS 0x84 0x000 | ||
| 374 | #define MX27_PAD_UART2_RTS__KP_ROW7 0x84 0x005 | ||
| 375 | #define MX27_PAD_UART2_RTS__GPIO5_4 0x84 0x032 | ||
| 376 | #define MX27_PAD_PWMO__PWMO 0x85 0x004 | ||
| 377 | #define MX27_PAD_PWMO__GPIO5_5 0x85 0x032 | ||
| 378 | #define MX27_PAD_UART2_TXD__UART2_TXD 0x86 0x004 | ||
| 379 | #define MX27_PAD_UART2_TXD__KP_COL6 0x86 0x005 | ||
| 380 | #define MX27_PAD_UART2_TXD__GPIO5_6 0x86 0x032 | ||
| 381 | #define MX27_PAD_UART2_RXD__UART2_RXD 0x87 0x000 | ||
| 382 | #define MX27_PAD_UART2_RXD__KP_ROW6 0x87 0x005 | ||
| 383 | #define MX27_PAD_UART2_RXD__GPIO5_7 0x87 0x032 | ||
| 384 | #define MX27_PAD_UART3_TXD__UART3_TXD 0x88 0x004 | ||
| 385 | #define MX27_PAD_UART3_TXD__GPIO5_8 0x88 0x032 | ||
| 386 | #define MX27_PAD_UART3_RXD__UART3_RXD 0x89 0x000 | ||
| 387 | #define MX27_PAD_UART3_RXD__GPIO5_9 0x89 0x032 | ||
| 388 | #define MX27_PAD_UART3_CTS__UART3_CTS 0x8a 0x004 | ||
| 389 | #define MX27_PAD_UART3_CTS__GPIO5_10 0x8a 0x032 | ||
| 390 | #define MX27_PAD_UART3_RTS__UART3_RTS 0x8b 0x000 | ||
| 391 | #define MX27_PAD_UART3_RTS__GPIO5_11 0x8b 0x032 | ||
| 392 | #define MX27_PAD_UART1_TXD__UART1_TXD 0x8c 0x004 | ||
| 393 | #define MX27_PAD_UART1_TXD__GPIO5_12 0x8c 0x032 | ||
| 394 | #define MX27_PAD_UART1_RXD__UART1_RXD 0x8d 0x000 | ||
| 395 | #define MX27_PAD_UART1_RXD__GPIO5_13 0x8d 0x032 | ||
| 396 | #define MX27_PAD_UART1_CTS__UART1_CTS 0x8e 0x004 | ||
| 397 | #define MX27_PAD_UART1_CTS__GPIO5_14 0x8e 0x032 | ||
| 398 | #define MX27_PAD_UART1_RTS__UART1_RTS 0x8f 0x000 | ||
| 399 | #define MX27_PAD_UART1_RTS__GPIO5_15 0x8f 0x032 | ||
| 400 | #define MX27_PAD_RTCK__RTCK 0x90 0x004 | ||
| 401 | #define MX27_PAD_RTCK__OWIRE 0x90 0x005 | ||
| 402 | #define MX27_PAD_RTCK__GPIO5_16 0x90 0x032 | ||
| 403 | #define MX27_PAD_RESET_OUT_B__RESET_OUT_B 0x91 0x004 | ||
| 404 | #define MX27_PAD_RESET_OUT_B__GPIO5_17 0x91 0x032 | ||
| 405 | #define MX27_PAD_SD1_D0__SD1_D0 0x92 0x004 | ||
| 406 | #define MX27_PAD_SD1_D0__CSPI3_MISO 0x92 0x001 | ||
| 407 | #define MX27_PAD_SD1_D0__GPIO5_18 0x92 0x032 | ||
| 408 | #define MX27_PAD_SD1_D1__SD1_D1 0x93 0x004 | ||
| 409 | #define MX27_PAD_SD1_D1__GPIO5_19 0x93 0x032 | ||
| 410 | #define MX27_PAD_SD1_D2__SD1_D2 0x94 0x004 | ||
| 411 | #define MX27_PAD_SD1_D2__GPIO5_20 0x94 0x032 | ||
| 412 | #define MX27_PAD_SD1_D3__SD1_D3 0x95 0x004 | ||
| 413 | #define MX27_PAD_SD1_D3__CSPI3_SS 0x95 0x005 | ||
| 414 | #define MX27_PAD_SD1_D3__GPIO5_21 0x95 0x032 | ||
| 415 | #define MX27_PAD_SD1_CMD__SD1_CMD 0x96 0x004 | ||
| 416 | #define MX27_PAD_SD1_CMD__CSPI3_MOSI 0x96 0x005 | ||
| 417 | #define MX27_PAD_SD1_CMD__GPIO5_22 0x96 0x032 | ||
| 418 | #define MX27_PAD_SD1_CLK__SD1_CLK 0x97 0x004 | ||
| 419 | #define MX27_PAD_SD1_CLK__CSPI3_SCLK 0x97 0x005 | ||
| 420 | #define MX27_PAD_SD1_CLK__GPIO5_23 0x97 0x032 | ||
| 421 | #define MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x98 0x000 | ||
| 422 | #define MX27_PAD_USBOTG_CLK__GPIO5_24 0x98 0x032 | ||
| 423 | #define MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x99 0x004 | ||
| 424 | #define MX27_PAD_USBOTG_DATA7__GPIO5_25 0x99 0x032 | ||
| 425 | #define MX27_PAD_UNUSED9__UNUSED9 0x9a 0x004 | ||
| 426 | #define MX27_PAD_UNUSED9__GPIO5_26 0x9a 0x032 | ||
| 427 | #define MX27_PAD_UNUSED10__UNUSED10 0x9b 0x004 | ||
| 428 | #define MX27_PAD_UNUSED10__GPIO5_27 0x9b 0x032 | ||
| 429 | #define MX27_PAD_UNUSED11__UNUSED11 0x9c 0x004 | ||
| 430 | #define MX27_PAD_UNUSED11__GPIO5_28 0x9c 0x032 | ||
| 431 | #define MX27_PAD_UNUSED12__UNUSED12 0x9d 0x004 | ||
| 432 | #define MX27_PAD_UNUSED12__GPIO5_29 0x9d 0x032 | ||
| 433 | #define MX27_PAD_UNUSED13__UNUSED13 0x9e 0x004 | ||
| 434 | #define MX27_PAD_UNUSED13__GPIO5_30 0x9e 0x032 | ||
| 435 | #define MX27_PAD_UNUSED14__UNUSED14 0x9f 0x004 | ||
| 436 | #define MX27_PAD_UNUSED14__GPIO5_31 0x9f 0x032 | ||
| 437 | #define MX27_PAD_NFRB__NFRB 0xa0 0x000 | ||
| 438 | #define MX27_PAD_NFRB__ETMTRACEPKT3 0xa0 0x005 | ||
| 439 | #define MX27_PAD_NFRB__GPIO6_0 0xa0 0x032 | ||
| 440 | #define MX27_PAD_NFCLE__NFCLE 0xa1 0x004 | ||
| 441 | #define MX27_PAD_NFCLE__ETMTRACEPKT0 0xa1 0x005 | ||
| 442 | #define MX27_PAD_NFCLE__GPIO6_1 0xa1 0x032 | ||
| 443 | #define MX27_PAD_NFWP_B__NFWP_B 0xa2 0x004 | ||
| 444 | #define MX27_PAD_NFWP_B__ETMTRACEPKT1 0xa2 0x005 | ||
| 445 | #define MX27_PAD_NFWP_B__GPIO6_2 0xa2 0x032 | ||
| 446 | #define MX27_PAD_NFCE_B__NFCE_B 0xa3 0x004 | ||
| 447 | #define MX27_PAD_NFCE_B__ETMTRACEPKT2 0xa3 0x005 | ||
| 448 | #define MX27_PAD_NFCE_B__GPIO6_3 0xa3 0x032 | ||
| 449 | #define MX27_PAD_NFALE__NFALE 0xa4 0x004 | ||
| 450 | #define MX27_PAD_NFALE__ETMPIPESTAT0 0xa4 0x005 | ||
| 451 | #define MX27_PAD_NFALE__GPIO6_4 0xa4 0x032 | ||
| 452 | #define MX27_PAD_NFRE_B__NFRE_B 0xa5 0x004 | ||
| 453 | #define MX27_PAD_NFRE_B__ETMPIPESTAT1 0xa5 0x005 | ||
| 454 | #define MX27_PAD_NFRE_B__GPIO6_5 0xa5 0x032 | ||
| 455 | #define MX27_PAD_NFWE_B__NFWE_B 0xa6 0x004 | ||
| 456 | #define MX27_PAD_NFWE_B__ETMPIPESTAT2 0xa6 0x005 | ||
| 457 | #define MX27_PAD_NFWE_B__GPIO6_6 0xa6 0x032 | ||
| 458 | #define MX27_PAD_PC_POE__PC_POE 0xa7 0x004 | ||
| 459 | #define MX27_PAD_PC_POE__ATA_BUFFER_EN 0xa7 0x005 | ||
| 460 | #define MX27_PAD_PC_POE__GPIO6_7 0xa7 0x032 | ||
| 461 | #define MX27_PAD_PC_RW_B__PC_RW_B 0xa8 0x004 | ||
| 462 | #define MX27_PAD_PC_RW_B__ATA_IORDY 0xa8 0x001 | ||
| 463 | #define MX27_PAD_PC_RW_B__GPIO6_8 0xa8 0x032 | ||
| 464 | #define MX27_PAD_IOIS16__IOIS16 0xa9 0x000 | ||
| 465 | #define MX27_PAD_IOIS16__ATA_INTRQ 0xa9 0x001 | ||
| 466 | #define MX27_PAD_IOIS16__GPIO6_9 0xa9 0x032 | ||
| 467 | #define MX27_PAD_PC_RST__PC_RST 0xaa 0x004 | ||
| 468 | #define MX27_PAD_PC_RST__ATA_RESET_B 0xaa 0x005 | ||
| 469 | #define MX27_PAD_PC_RST__GPIO6_10 0xaa 0x032 | ||
| 470 | #define MX27_PAD_PC_BVD2__PC_BVD2 0xab 0x000 | ||
| 471 | #define MX27_PAD_PC_BVD2__ATA_DMACK 0xab 0x005 | ||
| 472 | #define MX27_PAD_PC_BVD2__GPIO6_11 0xab 0x032 | ||
| 473 | #define MX27_PAD_PC_BVD1__PC_BVD1 0xac 0x000 | ||
| 474 | #define MX27_PAD_PC_BVD1__ATA_DMARQ 0xac 0x001 | ||
| 475 | #define MX27_PAD_PC_BVD1__GPIO6_12 0xac 0x032 | ||
| 476 | #define MX27_PAD_PC_VS2__PC_VS2 0xad 0x000 | ||
| 477 | #define MX27_PAD_PC_VS2__ATA_DA0 0xad 0x005 | ||
| 478 | #define MX27_PAD_PC_VS2__GPIO6_13 0xad 0x032 | ||
| 479 | #define MX27_PAD_PC_VS1__PC_VS1 0xae 0x000 | ||
| 480 | #define MX27_PAD_PC_VS1__ATA_DA1 0xae 0x005 | ||
| 481 | #define MX27_PAD_PC_VS1__GPIO6_14 0xae 0x032 | ||
| 482 | #define MX27_PAD_CLKO__CLKO 0xaf 0x004 | ||
| 483 | #define MX27_PAD_CLKO__GPIO6_15 0xaf 0x032 | ||
| 484 | #define MX27_PAD_PC_PWRON__PC_PWRON 0xb0 0x000 | ||
| 485 | #define MX27_PAD_PC_PWRON__ATA_DA2 0xb0 0x005 | ||
| 486 | #define MX27_PAD_PC_PWRON__GPIO6_16 0xb0 0x032 | ||
| 487 | #define MX27_PAD_PC_READY__PC_READY 0xb1 0x000 | ||
| 488 | #define MX27_PAD_PC_READY__ATA_CS0 0xb1 0x005 | ||
| 489 | #define MX27_PAD_PC_READY__GPIO6_17 0xb1 0x032 | ||
| 490 | #define MX27_PAD_PC_WAIT_B__PC_WAIT_B 0xb2 0x000 | ||
| 491 | #define MX27_PAD_PC_WAIT_B__ATA_CS1 0xb2 0x005 | ||
| 492 | #define MX27_PAD_PC_WAIT_B__GPIO6_18 0xb2 0x032 | ||
| 493 | #define MX27_PAD_PC_CD2_B__PC_CD2_B 0xb3 0x000 | ||
| 494 | #define MX27_PAD_PC_CD2_B__ATA_DIOW 0xb3 0x005 | ||
| 495 | #define MX27_PAD_PC_CD2_B__GPIO6_19 0xb3 0x032 | ||
| 496 | #define MX27_PAD_PC_CD1_B__PC_CD1_B 0xb4 0x000 | ||
| 497 | #define MX27_PAD_PC_CD1_B__ATA_DIOR 0xb4 0x005 | ||
| 498 | #define MX27_PAD_PC_CD1_B__GPIO6_20 0xb4 0x032 | ||
| 499 | #define MX27_PAD_CS4_B__CS4_B 0xb5 0x004 | ||
| 500 | #define MX27_PAD_CS4_B__ETMTRACESYNC 0xb5 0x005 | ||
| 501 | #define MX27_PAD_CS4_B__GPIO6_21 0xb5 0x032 | ||
| 502 | #define MX27_PAD_CS5_B__CS5_B 0xb6 0x004 | ||
| 503 | #define MX27_PAD_CS5_B__ETMTRACECLK 0xb6 0x005 | ||
| 504 | #define MX27_PAD_CS5_B__GPIO6_22 0xb6 0x032 | ||
| 505 | #define MX27_PAD_ATA_DATA15__ATA_DATA15 0xb7 0x004 | ||
| 506 | #define MX27_PAD_ATA_DATA15__ETMTRACEPKT4 0xb7 0x005 | ||
| 507 | #define MX27_PAD_ATA_DATA15__FEC_TX_EN 0xb7 0x006 | ||
| 508 | #define MX27_PAD_ATA_DATA15__GPIO6_23 0xb7 0x032 | ||
| 509 | #define MX27_PAD_UNUSED15__UNUSED15 0xb8 0x004 | ||
| 510 | #define MX27_PAD_UNUSED15__GPIO6_24 0xb8 0x032 | ||
| 511 | #define MX27_PAD_UNUSED16__UNUSED16 0xb9 0x004 | ||
| 512 | #define MX27_PAD_UNUSED16__GPIO6_25 0xb9 0x032 | ||
| 513 | #define MX27_PAD_UNUSED17__UNUSED17 0xba 0x004 | ||
| 514 | #define MX27_PAD_UNUSED17__GPIO6_26 0xba 0x032 | ||
| 515 | #define MX27_PAD_UNUSED18__UNUSED18 0xbb 0x004 | ||
| 516 | #define MX27_PAD_UNUSED18__GPIO6_27 0xbb 0x032 | ||
| 517 | #define MX27_PAD_UNUSED19__UNUSED19 0xbc 0x004 | ||
| 518 | #define MX27_PAD_UNUSED19__GPIO6_28 0xbc 0x032 | ||
| 519 | #define MX27_PAD_UNUSED20__UNUSED20 0xbd 0x004 | ||
| 520 | #define MX27_PAD_UNUSED20__GPIO6_29 0xbd 0x032 | ||
| 521 | #define MX27_PAD_UNUSED21__UNUSED21 0xbe 0x004 | ||
| 522 | #define MX27_PAD_UNUSED21__GPIO6_30 0xbe 0x032 | ||
| 523 | #define MX27_PAD_UNUSED22__UNUSED22 0xbf 0x004 | ||
| 524 | #define MX27_PAD_UNUSED22__GPIO6_31 0xbf 0x032 | ||
| 525 | |||
| 526 | #endif /* __DTS_IMX27_PINFUNC_H */ | ||
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index 826231eb4446..6279e0b4f768 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi | |||
| @@ -10,6 +10,9 @@ | |||
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | #include "skeleton.dtsi" | 12 | #include "skeleton.dtsi" |
| 13 | #include "imx27-pinfunc.h" | ||
| 14 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 15 | #include <dt-bindings/gpio/gpio.h> | ||
| 13 | 16 | ||
| 14 | / { | 17 | / { |
| 15 | aliases { | 18 | aliases { |
| @@ -67,6 +70,26 @@ | |||
| 67 | }; | 70 | }; |
| 68 | }; | 71 | }; |
| 69 | 72 | ||
| 73 | usbphy { | ||
| 74 | compatible = "simple-bus"; | ||
| 75 | #address-cells = <1>; | ||
| 76 | #size-cells = <0>; | ||
| 77 | |||
| 78 | usbphy0: usbphy@0 { | ||
| 79 | compatible = "usb-nop-xceiv"; | ||
| 80 | reg = <0>; | ||
| 81 | clocks = <&clks 75>; | ||
| 82 | clock-names = "main_clk"; | ||
| 83 | }; | ||
| 84 | |||
| 85 | usbphy2: usbphy@2 { | ||
| 86 | compatible = "usb-nop-xceiv"; | ||
| 87 | reg = <2>; | ||
| 88 | clocks = <&clks 75>; | ||
| 89 | clock-names = "main_clk"; | ||
| 90 | }; | ||
| 91 | }; | ||
| 92 | |||
| 70 | soc { | 93 | soc { |
| 71 | #address-cells = <1>; | 94 | #address-cells = <1>; |
| 72 | #size-cells = <1>; | 95 | #size-cells = <1>; |
| @@ -204,6 +227,30 @@ | |||
| 204 | status = "disabled"; | 227 | status = "disabled"; |
| 205 | }; | 228 | }; |
| 206 | 229 | ||
| 230 | ssi1: ssi@10010000 { | ||
| 231 | #sound-dai-cells = <0>; | ||
| 232 | compatible = "fsl,imx27-ssi", "fsl,imx21-ssi"; | ||
| 233 | reg = <0x10010000 0x1000>; | ||
| 234 | interrupts = <14>; | ||
| 235 | clocks = <&clks 26>; | ||
| 236 | dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>; | ||
| 237 | dma-names = "rx0", "tx0", "rx1", "tx1"; | ||
| 238 | fsl,fifo-depth = <8>; | ||
| 239 | status = "disabled"; | ||
| 240 | }; | ||
| 241 | |||
| 242 | ssi2: ssi@10011000 { | ||
| 243 | #sound-dai-cells = <0>; | ||
| 244 | compatible = "fsl,imx27-ssi", "fsl,imx21-ssi"; | ||
| 245 | reg = <0x10011000 0x1000>; | ||
| 246 | interrupts = <13>; | ||
| 247 | clocks = <&clks 25>; | ||
| 248 | dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>; | ||
| 249 | dma-names = "rx0", "tx0", "rx1", "tx1"; | ||
| 250 | fsl,fifo-depth = <8>; | ||
| 251 | status = "disabled"; | ||
| 252 | }; | ||
| 253 | |||
| 207 | i2c1: i2c@10012000 { | 254 | i2c1: i2c@10012000 { |
| 208 | #address-cells = <1>; | 255 | #address-cells = <1>; |
| 209 | #size-cells = <0>; | 256 | #size-cells = <0>; |
| @@ -236,64 +283,72 @@ | |||
| 236 | status = "disabled"; | 283 | status = "disabled"; |
| 237 | }; | 284 | }; |
| 238 | 285 | ||
| 239 | gpio1: gpio@10015000 { | 286 | iomuxc: iomuxc@10015000 { |
| 240 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | 287 | compatible = "fsl,imx27-iomuxc"; |
| 241 | reg = <0x10015000 0x100>; | 288 | reg = <0x10015000 0x600>; |
| 242 | interrupts = <8>; | 289 | #address-cells = <1>; |
| 243 | gpio-controller; | 290 | #size-cells = <1>; |
| 244 | #gpio-cells = <2>; | 291 | ranges; |
| 245 | interrupt-controller; | 292 | |
| 246 | #interrupt-cells = <2>; | 293 | gpio1: gpio@10015000 { |
| 247 | }; | 294 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; |
| 248 | 295 | reg = <0x10015000 0x100>; | |
| 249 | gpio2: gpio@10015100 { | 296 | interrupts = <8>; |
| 250 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | 297 | gpio-controller; |
| 251 | reg = <0x10015100 0x100>; | 298 | #gpio-cells = <2>; |
| 252 | interrupts = <8>; | 299 | interrupt-controller; |
| 253 | gpio-controller; | 300 | #interrupt-cells = <2>; |
| 254 | #gpio-cells = <2>; | 301 | }; |
| 255 | interrupt-controller; | 302 | |
| 256 | #interrupt-cells = <2>; | 303 | gpio2: gpio@10015100 { |
| 257 | }; | 304 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; |
| 258 | 305 | reg = <0x10015100 0x100>; | |
| 259 | gpio3: gpio@10015200 { | 306 | interrupts = <8>; |
| 260 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | 307 | gpio-controller; |
| 261 | reg = <0x10015200 0x100>; | 308 | #gpio-cells = <2>; |
| 262 | interrupts = <8>; | 309 | interrupt-controller; |
| 263 | gpio-controller; | 310 | #interrupt-cells = <2>; |
| 264 | #gpio-cells = <2>; | 311 | }; |
| 265 | interrupt-controller; | 312 | |
| 266 | #interrupt-cells = <2>; | 313 | gpio3: gpio@10015200 { |
| 267 | }; | 314 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; |
| 268 | 315 | reg = <0x10015200 0x100>; | |
| 269 | gpio4: gpio@10015300 { | 316 | interrupts = <8>; |
| 270 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | 317 | gpio-controller; |
| 271 | reg = <0x10015300 0x100>; | 318 | #gpio-cells = <2>; |
| 272 | interrupts = <8>; | 319 | interrupt-controller; |
| 273 | gpio-controller; | 320 | #interrupt-cells = <2>; |
| 274 | #gpio-cells = <2>; | 321 | }; |
| 275 | interrupt-controller; | 322 | |
| 276 | #interrupt-cells = <2>; | 323 | gpio4: gpio@10015300 { |
| 277 | }; | 324 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; |
| 278 | 325 | reg = <0x10015300 0x100>; | |
| 279 | gpio5: gpio@10015400 { | 326 | interrupts = <8>; |
| 280 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | 327 | gpio-controller; |
| 281 | reg = <0x10015400 0x100>; | 328 | #gpio-cells = <2>; |
| 282 | interrupts = <8>; | 329 | interrupt-controller; |
| 283 | gpio-controller; | 330 | #interrupt-cells = <2>; |
| 284 | #gpio-cells = <2>; | 331 | }; |
| 285 | interrupt-controller; | 332 | |
| 286 | #interrupt-cells = <2>; | 333 | gpio5: gpio@10015400 { |
| 287 | }; | 334 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; |
| 288 | 335 | reg = <0x10015400 0x100>; | |
| 289 | gpio6: gpio@10015500 { | 336 | interrupts = <8>; |
| 290 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | 337 | gpio-controller; |
| 291 | reg = <0x10015500 0x100>; | 338 | #gpio-cells = <2>; |
| 292 | interrupts = <8>; | 339 | interrupt-controller; |
| 293 | gpio-controller; | 340 | #interrupt-cells = <2>; |
| 294 | #gpio-cells = <2>; | 341 | }; |
| 295 | interrupt-controller; | 342 | |
| 296 | #interrupt-cells = <2>; | 343 | gpio6: gpio@10015500 { |
| 344 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | ||
| 345 | reg = <0x10015500 0x100>; | ||
| 346 | interrupts = <8>; | ||
| 347 | gpio-controller; | ||
| 348 | #gpio-cells = <2>; | ||
| 349 | interrupt-controller; | ||
| 350 | #interrupt-cells = <2>; | ||
| 351 | }; | ||
| 297 | }; | 352 | }; |
| 298 | 353 | ||
| 299 | audmux: audmux@10016000 { | 354 | audmux: audmux@10016000 { |
| @@ -404,6 +459,42 @@ | |||
| 404 | iram = <&iram>; | 459 | iram = <&iram>; |
| 405 | }; | 460 | }; |
| 406 | 461 | ||
| 462 | usbotg: usb@10024000 { | ||
| 463 | compatible = "fsl,imx27-usb"; | ||
| 464 | reg = <0x10024000 0x200>; | ||
| 465 | interrupts = <56>; | ||
| 466 | clocks = <&clks 15>; | ||
| 467 | fsl,usbmisc = <&usbmisc 0>; | ||
| 468 | fsl,usbphy = <&usbphy0>; | ||
| 469 | status = "disabled"; | ||
| 470 | }; | ||
| 471 | |||
| 472 | usbh1: usb@10024200 { | ||
| 473 | compatible = "fsl,imx27-usb"; | ||
| 474 | reg = <0x10024200 0x200>; | ||
| 475 | interrupts = <54>; | ||
| 476 | clocks = <&clks 15>; | ||
| 477 | fsl,usbmisc = <&usbmisc 1>; | ||
| 478 | status = "disabled"; | ||
| 479 | }; | ||
| 480 | |||
| 481 | usbh2: usb@10024400 { | ||
| 482 | compatible = "fsl,imx27-usb"; | ||
| 483 | reg = <0x10024400 0x200>; | ||
| 484 | interrupts = <55>; | ||
| 485 | clocks = <&clks 15>; | ||
| 486 | fsl,usbmisc = <&usbmisc 2>; | ||
| 487 | fsl,usbphy = <&usbphy2>; | ||
| 488 | status = "disabled"; | ||
| 489 | }; | ||
| 490 | |||
| 491 | usbmisc: usbmisc@10024600 { | ||
| 492 | #index-cells = <1>; | ||
| 493 | compatible = "fsl,imx27-usbmisc"; | ||
| 494 | reg = <0x10024600 0x200>; | ||
| 495 | clocks = <&clks 62>; | ||
| 496 | }; | ||
| 497 | |||
| 407 | sahara2: sahara@10025000 { | 498 | sahara2: sahara@10025000 { |
| 408 | compatible = "fsl,imx27-sahara"; | 499 | compatible = "fsl,imx27-sahara"; |
| 409 | reg = <0x10025000 0x1000>; | 500 | reg = <0x10025000 0x1000>; |
diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts index e2efd8d89c4f..221cac4fb2cd 100644 --- a/arch/arm/boot/dts/imx28-apf28dev.dts +++ b/arch/arm/boot/dts/imx28-apf28dev.dts | |||
| @@ -48,6 +48,7 @@ | |||
| 48 | MX28_PAD_LCD_D20__GPIO_1_20 | 48 | MX28_PAD_LCD_D20__GPIO_1_20 |
| 49 | MX28_PAD_LCD_D21__GPIO_1_21 | 49 | MX28_PAD_LCD_D21__GPIO_1_21 |
| 50 | MX28_PAD_LCD_D22__GPIO_1_22 | 50 | MX28_PAD_LCD_D22__GPIO_1_22 |
| 51 | MX28_PAD_GPMI_CE1N__GPIO_0_17 | ||
| 51 | >; | 52 | >; |
| 52 | fsl,drive-strength = <MXS_DRIVE_4mA>; | 53 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
| 53 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | 54 | fsl,voltage = <MXS_VOLTAGE_HIGH>; |
| @@ -66,6 +67,16 @@ | |||
| 66 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | 67 | fsl,voltage = <MXS_VOLTAGE_HIGH>; |
| 67 | fsl,pull-up = <MXS_PULL_DISABLE>; | 68 | fsl,pull-up = <MXS_PULL_DISABLE>; |
| 68 | }; | 69 | }; |
| 70 | |||
| 71 | usb0_otg_apf28dev: otg-apf28dev@0 { | ||
| 72 | reg = <0>; | ||
| 73 | fsl,pinmux-ids = < | ||
| 74 | MX28_PAD_LCD_D23__GPIO_1_23 | ||
| 75 | >; | ||
| 76 | fsl,drive-strength = <MXS_DRIVE_4mA>; | ||
| 77 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | ||
| 78 | fsl,pull-up = <MXS_PULL_DISABLE>; | ||
| 79 | }; | ||
| 69 | }; | 80 | }; |
| 70 | 81 | ||
| 71 | lcdif@80030000 { | 82 | lcdif@80030000 { |
| @@ -131,6 +142,8 @@ | |||
| 131 | 142 | ||
| 132 | ahb@80080000 { | 143 | ahb@80080000 { |
| 133 | usb0: usb@80080000 { | 144 | usb0: usb@80080000 { |
| 145 | pinctrl-names = "default"; | ||
| 146 | pinctrl-0 = <&usb0_otg_apf28dev>; | ||
| 134 | vbus-supply = <®_usb0_vbus>; | 147 | vbus-supply = <®_usb0_vbus>; |
| 135 | status = "okay"; | 148 | status = "okay"; |
| 136 | }; | 149 | }; |
| @@ -150,13 +163,17 @@ | |||
| 150 | 163 | ||
| 151 | regulators { | 164 | regulators { |
| 152 | compatible = "simple-bus"; | 165 | compatible = "simple-bus"; |
| 166 | #address-cells = <1>; | ||
| 167 | #size-cells = <0>; | ||
| 153 | 168 | ||
| 154 | reg_usb0_vbus: usb0_vbus { | 169 | reg_usb0_vbus: regulator@0 { |
| 155 | compatible = "regulator-fixed"; | 170 | compatible = "regulator-fixed"; |
| 171 | reg = <0>; | ||
| 156 | regulator-name = "usb0_vbus"; | 172 | regulator-name = "usb0_vbus"; |
| 157 | regulator-min-microvolt = <5000000>; | 173 | regulator-min-microvolt = <5000000>; |
| 158 | regulator-max-microvolt = <5000000>; | 174 | regulator-max-microvolt = <5000000>; |
| 159 | gpio = <&gpio1 23 1>; | 175 | gpio = <&gpio1 23 1>; |
| 176 | enable-active-high; | ||
| 160 | }; | 177 | }; |
| 161 | }; | 178 | }; |
| 162 | 179 | ||
| @@ -177,4 +194,14 @@ | |||
| 177 | brightness-levels = <0 4 8 16 32 64 128 255>; | 194 | brightness-levels = <0 4 8 16 32 64 128 255>; |
| 178 | default-brightness-level = <6>; | 195 | default-brightness-level = <6>; |
| 179 | }; | 196 | }; |
| 197 | |||
| 198 | gpio-keys { | ||
| 199 | compatible = "gpio-keys"; | ||
| 200 | |||
| 201 | user-button { | ||
| 202 | label = "User button"; | ||
| 203 | gpios = <&gpio0 17 0>; | ||
| 204 | linux,code = <0x100>; | ||
| 205 | }; | ||
| 206 | }; | ||
| 180 | }; | 207 | }; |
diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts index 6f254ca816cb..e1ce9179db63 100644 --- a/arch/arm/boot/dts/imx28-apx4devkit.dts +++ b/arch/arm/boot/dts/imx28-apx4devkit.dts | |||
| @@ -193,9 +193,12 @@ | |||
| 193 | 193 | ||
| 194 | regulators { | 194 | regulators { |
| 195 | compatible = "simple-bus"; | 195 | compatible = "simple-bus"; |
| 196 | #address-cells = <1>; | ||
| 197 | #size-cells = <0>; | ||
| 196 | 198 | ||
| 197 | reg_3p3v: 3p3v { | 199 | reg_3p3v: regulator@0 { |
| 198 | compatible = "regulator-fixed"; | 200 | compatible = "regulator-fixed"; |
| 201 | reg = <0>; | ||
| 199 | regulator-name = "3P3V"; | 202 | regulator-name = "3P3V"; |
| 200 | regulator-min-microvolt = <3300000>; | 203 | regulator-min-microvolt = <3300000>; |
| 201 | regulator-max-microvolt = <3300000>; | 204 | regulator-max-microvolt = <3300000>; |
diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts index cabb6171a19d..ae7c3390e65a 100644 --- a/arch/arm/boot/dts/imx28-cfa10036.dts +++ b/arch/arm/boot/dts/imx28-cfa10036.dts | |||
| @@ -100,6 +100,8 @@ | |||
| 100 | usb0: usb@80080000 { | 100 | usb0: usb@80080000 { |
| 101 | pinctrl-names = "default"; | 101 | pinctrl-names = "default"; |
| 102 | pinctrl-0 = <&usb0_otg_cfa10036>; | 102 | pinctrl-0 = <&usb0_otg_cfa10036>; |
| 103 | dr_mode = "peripheral"; | ||
| 104 | phy_type = "utmi"; | ||
| 103 | status = "okay"; | 105 | status = "okay"; |
| 104 | }; | 106 | }; |
| 105 | }; | 107 | }; |
diff --git a/arch/arm/boot/dts/imx28-cfa10037.dts b/arch/arm/boot/dts/imx28-cfa10037.dts index f93e9a700e52..e5beaa58bb40 100644 --- a/arch/arm/boot/dts/imx28-cfa10037.dts +++ b/arch/arm/boot/dts/imx28-cfa10037.dts | |||
| @@ -54,7 +54,7 @@ | |||
| 54 | ahb@80080000 { | 54 | ahb@80080000 { |
| 55 | usb1: usb@80090000 { | 55 | usb1: usb@80090000 { |
| 56 | vbus-supply = <®_usb1_vbus>; | 56 | vbus-supply = <®_usb1_vbus>; |
| 57 | pinctrl-0 = <&usbphy1_pins_a>; | 57 | pinctrl-0 = <&usb1_pins_a>; |
| 58 | pinctrl-names = "default"; | 58 | pinctrl-names = "default"; |
| 59 | status = "okay"; | 59 | status = "okay"; |
| 60 | }; | 60 | }; |
| @@ -72,9 +72,12 @@ | |||
| 72 | 72 | ||
| 73 | regulators { | 73 | regulators { |
| 74 | compatible = "simple-bus"; | 74 | compatible = "simple-bus"; |
| 75 | #address-cells = <1>; | ||
| 76 | #size-cells = <0>; | ||
| 75 | 77 | ||
| 76 | reg_usb1_vbus: usb1_vbus { | 78 | reg_usb1_vbus: regulator@0 { |
| 77 | compatible = "regulator-fixed"; | 79 | compatible = "regulator-fixed"; |
| 80 | reg = <0>; | ||
| 78 | pinctrl-names = "default"; | 81 | pinctrl-names = "default"; |
| 79 | pinctrl-0 = <&usb_pins_cfa10037>; | 82 | pinctrl-0 = <&usb_pins_cfa10037>; |
| 80 | regulator-name = "usb1_vbus"; | 83 | regulator-name = "usb1_vbus"; |
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts index 7087b4bf6a8f..7d51459de5e8 100644 --- a/arch/arm/boot/dts/imx28-cfa10049.dts +++ b/arch/arm/boot/dts/imx28-cfa10049.dts | |||
| @@ -229,15 +229,39 @@ | |||
| 229 | i2c-parent = <&i2c1>; | 229 | i2c-parent = <&i2c1>; |
| 230 | 230 | ||
| 231 | i2c@0 { | 231 | i2c@0 { |
| 232 | #address-cells = <1>; | ||
| 233 | #size-cells = <0>; | ||
| 232 | reg = <0>; | 234 | reg = <0>; |
| 235 | |||
| 236 | adc0: nau7802@2a { | ||
| 237 | compatible = "nuvoton,nau7802"; | ||
| 238 | reg = <0x2a>; | ||
| 239 | nuvoton,vldo = <3000>; | ||
| 240 | }; | ||
| 233 | }; | 241 | }; |
| 234 | 242 | ||
| 235 | i2c@1 { | 243 | i2c@1 { |
| 244 | #address-cells = <1>; | ||
| 245 | #size-cells = <0>; | ||
| 236 | reg = <1>; | 246 | reg = <1>; |
| 247 | |||
| 248 | adc1: nau7802@2a { | ||
| 249 | compatible = "nuvoton,nau7802"; | ||
| 250 | reg = <0x2a>; | ||
| 251 | nuvoton,vldo = <3000>; | ||
| 252 | }; | ||
| 237 | }; | 253 | }; |
| 238 | 254 | ||
| 239 | i2c@2 { | 255 | i2c@2 { |
| 256 | #address-cells = <1>; | ||
| 257 | #size-cells = <0>; | ||
| 240 | reg = <2>; | 258 | reg = <2>; |
| 259 | |||
| 260 | adc2: nau7802@2a { | ||
| 261 | compatible = "nuvoton,nau7802"; | ||
| 262 | reg = <0x2a>; | ||
| 263 | nuvoton,vldo = <3000>; | ||
| 264 | }; | ||
| 241 | }; | 265 | }; |
| 242 | 266 | ||
| 243 | i2c@3 { | 267 | i2c@3 { |
| @@ -274,7 +298,7 @@ | |||
| 274 | ahb@80080000 { | 298 | ahb@80080000 { |
| 275 | usb1: usb@80090000 { | 299 | usb1: usb@80090000 { |
| 276 | vbus-supply = <®_usb1_vbus>; | 300 | vbus-supply = <®_usb1_vbus>; |
| 277 | pinctrl-0 = <&usbphy1_pins_a>; | 301 | pinctrl-0 = <&usb1_pins_a>; |
| 278 | pinctrl-names = "default"; | 302 | pinctrl-names = "default"; |
| 279 | status = "okay"; | 303 | status = "okay"; |
| 280 | }; | 304 | }; |
| @@ -282,9 +306,12 @@ | |||
| 282 | 306 | ||
| 283 | regulators { | 307 | regulators { |
| 284 | compatible = "simple-bus"; | 308 | compatible = "simple-bus"; |
| 309 | #address-cells = <1>; | ||
| 310 | #size-cells = <0>; | ||
| 285 | 311 | ||
| 286 | reg_usb1_vbus: usb1_vbus { | 312 | reg_usb1_vbus: regulator@0 { |
| 287 | compatible = "regulator-fixed"; | 313 | compatible = "regulator-fixed"; |
| 314 | reg = <0>; | ||
| 288 | pinctrl-names = "default"; | 315 | pinctrl-names = "default"; |
| 289 | pinctrl-0 = <&usb_pins_cfa10049>; | 316 | pinctrl-0 = <&usb_pins_cfa10049>; |
| 290 | regulator-name = "usb1_vbus"; | 317 | regulator-name = "usb1_vbus"; |
diff --git a/arch/arm/boot/dts/imx28-cfa10057.dts b/arch/arm/boot/dts/imx28-cfa10057.dts index 3c1312885ae0..c4e00ce4b6da 100644 --- a/arch/arm/boot/dts/imx28-cfa10057.dts +++ b/arch/arm/boot/dts/imx28-cfa10057.dts | |||
| @@ -134,7 +134,7 @@ | |||
| 134 | ahb@80080000 { | 134 | ahb@80080000 { |
| 135 | usb1: usb@80090000 { | 135 | usb1: usb@80090000 { |
| 136 | vbus-supply = <®_usb1_vbus>; | 136 | vbus-supply = <®_usb1_vbus>; |
| 137 | pinctrl-0 = <&usbphy1_pins_a>; | 137 | pinctrl-0 = <&usb1_pins_a>; |
| 138 | pinctrl-names = "default"; | 138 | pinctrl-names = "default"; |
| 139 | status = "okay"; | 139 | status = "okay"; |
| 140 | }; | 140 | }; |
| @@ -142,9 +142,12 @@ | |||
| 142 | 142 | ||
| 143 | regulators { | 143 | regulators { |
| 144 | compatible = "simple-bus"; | 144 | compatible = "simple-bus"; |
| 145 | #address-cells = <1>; | ||
| 146 | #size-cells = <0>; | ||
| 145 | 147 | ||
| 146 | reg_usb1_vbus: usb1_vbus { | 148 | reg_usb1_vbus: regulator@0 { |
| 147 | compatible = "regulator-fixed"; | 149 | compatible = "regulator-fixed"; |
| 150 | reg = <0>; | ||
| 148 | pinctrl-names = "default"; | 151 | pinctrl-names = "default"; |
| 149 | pinctrl-0 = <&usb_pins_cfa10057>; | 152 | pinctrl-0 = <&usb_pins_cfa10057>; |
| 150 | regulator-name = "usb1_vbus"; | 153 | regulator-name = "usb1_vbus"; |
diff --git a/arch/arm/boot/dts/imx28-cfa10058.dts b/arch/arm/boot/dts/imx28-cfa10058.dts index 2469d34df0ae..7c9cc783f0d1 100644 --- a/arch/arm/boot/dts/imx28-cfa10058.dts +++ b/arch/arm/boot/dts/imx28-cfa10058.dts | |||
| @@ -101,7 +101,7 @@ | |||
| 101 | ahb@80080000 { | 101 | ahb@80080000 { |
| 102 | usb1: usb@80090000 { | 102 | usb1: usb@80090000 { |
| 103 | vbus-supply = <®_usb1_vbus>; | 103 | vbus-supply = <®_usb1_vbus>; |
| 104 | pinctrl-0 = <&usbphy1_pins_a>; | 104 | pinctrl-0 = <&usb1_pins_a>; |
| 105 | pinctrl-names = "default"; | 105 | pinctrl-names = "default"; |
| 106 | status = "okay"; | 106 | status = "okay"; |
| 107 | }; | 107 | }; |
| @@ -109,11 +109,14 @@ | |||
| 109 | 109 | ||
| 110 | regulators { | 110 | regulators { |
| 111 | compatible = "simple-bus"; | 111 | compatible = "simple-bus"; |
| 112 | #address-cells = <1>; | ||
| 113 | #size-cells = <0>; | ||
| 112 | 114 | ||
| 113 | reg_usb1_vbus: usb1_vbus { | 115 | reg_usb1_vbus: regulator@0 { |
| 114 | pinctrl-names = "default"; | 116 | pinctrl-names = "default"; |
| 115 | pinctrl-0 = <&usb_pins_cfa10058>; | 117 | pinctrl-0 = <&usb_pins_cfa10058>; |
| 116 | compatible = "regulator-fixed"; | 118 | compatible = "regulator-fixed"; |
| 119 | reg = <0>; | ||
| 117 | regulator-name = "usb1_vbus"; | 120 | regulator-name = "usb1_vbus"; |
| 118 | regulator-min-microvolt = <5000000>; | 121 | regulator-min-microvolt = <5000000>; |
| 119 | regulator-max-microvolt = <5000000>; | 122 | regulator-max-microvolt = <5000000>; |
diff --git a/arch/arm/boot/dts/imx28-duckbill.dts b/arch/arm/boot/dts/imx28-duckbill.dts new file mode 100644 index 000000000000..5f326c1c1850 --- /dev/null +++ b/arch/arm/boot/dts/imx28-duckbill.dts | |||
| @@ -0,0 +1,121 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2013 Michael Heimpold <mhei@heimpold.de> | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | #include "imx28.dtsi" | ||
| 14 | |||
| 15 | / { | ||
| 16 | model = "I2SE Duckbill"; | ||
| 17 | compatible = "i2se,duckbill", "fsl,imx28"; | ||
| 18 | |||
| 19 | memory { | ||
| 20 | reg = <0x40000000 0x08000000>; | ||
| 21 | }; | ||
| 22 | |||
| 23 | apb@80000000 { | ||
| 24 | apbh@80000000 { | ||
| 25 | ssp0: ssp@80010000 { | ||
| 26 | compatible = "fsl,imx28-mmc"; | ||
| 27 | pinctrl-names = "default"; | ||
| 28 | pinctrl-0 = <&mmc0_8bit_pins_a | ||
| 29 | &mmc0_cd_cfg &mmc0_sck_cfg>; | ||
| 30 | bus-width = <8>; | ||
| 31 | vmmc-supply = <®_3p3v>; | ||
| 32 | status = "okay"; | ||
| 33 | }; | ||
| 34 | |||
| 35 | pinctrl@80018000 { | ||
| 36 | pinctrl-names = "default"; | ||
| 37 | pinctrl-0 = <&hog_pins_a>; | ||
| 38 | |||
| 39 | hog_pins_a: hog@0 { | ||
| 40 | reg = <0>; | ||
| 41 | fsl,pinmux-ids = < | ||
| 42 | MX28_PAD_ENET0_RX_CLK__GPIO_4_13 /* PHY Reset */ | ||
| 43 | >; | ||
| 44 | fsl,drive-strength = <MXS_DRIVE_4mA>; | ||
| 45 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | ||
| 46 | fsl,pull-up = <MXS_PULL_DISABLE>; | ||
| 47 | }; | ||
| 48 | |||
| 49 | led_pins_a: led_gpio@0 { | ||
| 50 | reg = <0>; | ||
| 51 | fsl,pinmux-ids = < | ||
| 52 | MX28_PAD_AUART1_RX__GPIO_3_4 | ||
| 53 | MX28_PAD_AUART1_TX__GPIO_3_5 | ||
| 54 | >; | ||
| 55 | fsl,drive-strength = <MXS_DRIVE_4mA>; | ||
| 56 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | ||
| 57 | fsl,pull-up = <MXS_PULL_DISABLE>; | ||
| 58 | }; | ||
| 59 | }; | ||
| 60 | }; | ||
| 61 | |||
| 62 | apbx@80040000 { | ||
| 63 | duart: serial@80074000 { | ||
| 64 | pinctrl-names = "default"; | ||
| 65 | pinctrl-0 = <&duart_pins_a>; | ||
| 66 | status = "okay"; | ||
| 67 | }; | ||
| 68 | |||
| 69 | usbphy0: usbphy@8007c000 { | ||
| 70 | status = "okay"; | ||
| 71 | }; | ||
| 72 | }; | ||
| 73 | }; | ||
| 74 | |||
| 75 | ahb@80080000 { | ||
| 76 | usb0: usb@80080000 { | ||
| 77 | status = "okay"; | ||
| 78 | }; | ||
| 79 | |||
| 80 | mac0: ethernet@800f0000 { | ||
| 81 | phy-mode = "rmii"; | ||
| 82 | pinctrl-names = "default"; | ||
| 83 | pinctrl-0 = <&mac0_pins_a>; | ||
| 84 | phy-supply = <®_3p3v>; | ||
| 85 | phy-reset-gpios = <&gpio4 13 0>; | ||
| 86 | phy-reset-duration = <100>; | ||
| 87 | status = "okay"; | ||
| 88 | }; | ||
| 89 | }; | ||
| 90 | |||
| 91 | regulators { | ||
| 92 | compatible = "simple-bus"; | ||
| 93 | #address-cells = <1>; | ||
| 94 | #size-cells = <0>; | ||
| 95 | |||
| 96 | reg_3p3v: regulator@0 { | ||
| 97 | compatible = "regulator-fixed"; | ||
| 98 | reg = <0>; | ||
| 99 | regulator-name = "3P3V"; | ||
| 100 | regulator-min-microvolt = <3300000>; | ||
| 101 | regulator-max-microvolt = <3300000>; | ||
| 102 | regulator-always-on; | ||
| 103 | }; | ||
| 104 | }; | ||
| 105 | |||
| 106 | leds { | ||
| 107 | compatible = "gpio-leds"; | ||
| 108 | pinctrl-names = "default"; | ||
| 109 | pinctrl-0 = <&led_pins_a>; | ||
| 110 | |||
| 111 | status { | ||
| 112 | label = "duckbill:green:status"; | ||
| 113 | gpios = <&gpio3 5 0>; | ||
| 114 | }; | ||
| 115 | |||
| 116 | failure { | ||
| 117 | label = "duckbill:red:status"; | ||
| 118 | gpios = <&gpio3 4 0>; | ||
| 119 | }; | ||
| 120 | }; | ||
| 121 | }; | ||
diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts b/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts new file mode 100644 index 000000000000..7c1572c5a4fb --- /dev/null +++ b/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts | |||
| @@ -0,0 +1,71 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Eukréa Electromatique <eric@eukrea.com> | ||
| 3 | * Copyright 2013 Eukréa Electromatique <denis@eukrea.com> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License | ||
| 7 | * as published by the Free Software Foundation; either version 2 | ||
| 8 | * of the License, or (at your option) any later version. | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | */ | ||
| 14 | |||
| 15 | /* | ||
| 16 | * Module contains : i.MX282 + 64MB DDR2 + NAND + Ethernet PHY + RTC | ||
| 17 | */ | ||
| 18 | |||
| 19 | /dts-v1/; | ||
| 20 | #include "imx28-eukrea-mbmx28lc.dtsi" | ||
| 21 | |||
| 22 | / { | ||
| 23 | model = "Eukrea Electromatique MBMX283LC"; | ||
| 24 | compatible = "eukrea,mbmx283lc", "eukrea,mbmx28lc", "fsl,imx28"; | ||
| 25 | |||
| 26 | memory { | ||
| 27 | reg = <0x40000000 0x04000000>; | ||
| 28 | }; | ||
| 29 | }; | ||
| 30 | |||
| 31 | &gpmi { | ||
| 32 | pinctrl-names = "default"; | ||
| 33 | pinctrl-0 = <&gpmi_pins_a>; | ||
| 34 | status = "okay"; | ||
| 35 | }; | ||
| 36 | |||
| 37 | &i2c0 { | ||
| 38 | pinctrl-names = "default"; | ||
| 39 | pinctrl-0 = <&i2c0_pins_a>; | ||
| 40 | status = "okay"; | ||
| 41 | |||
| 42 | pcf8563: rtc@51 { | ||
| 43 | compatible = "nxp,pcf8563"; | ||
| 44 | reg = <0x51>; | ||
| 45 | }; | ||
| 46 | }; | ||
| 47 | |||
| 48 | |||
| 49 | &mac0 { | ||
| 50 | phy-mode = "rmii"; | ||
| 51 | pinctrl-names = "default"; | ||
| 52 | pinctrl-0 = <&mac0_pins_a>; | ||
| 53 | phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; | ||
| 54 | status = "okay"; | ||
| 55 | }; | ||
| 56 | |||
| 57 | &pinctrl{ | ||
| 58 | pinctrl-names = "default"; | ||
| 59 | pinctrl-0 = <&hog_pins_cpuimx283>; | ||
| 60 | |||
| 61 | hog_pins_cpuimx283: hog-cpuimx283@0 { | ||
| 62 | reg = <0>; | ||
| 63 | fsl,pinmux-ids = < | ||
| 64 | MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | ||
| 65 | MX28_PAD_ENET0_TX_CLK__GPIO_4_5 | ||
| 66 | >; | ||
| 67 | fsl,drive-strength = <MXS_DRIVE_4mA>; | ||
| 68 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | ||
| 69 | fsl,pull-up = <MXS_PULL_ENABLE>; | ||
| 70 | }; | ||
| 71 | }; | ||
diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts b/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts new file mode 100644 index 000000000000..e773144e1e03 --- /dev/null +++ b/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts | |||
| @@ -0,0 +1,50 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Eukréa Electromatique <eric@eukrea.com> | ||
| 3 | * Copyright 2013 Eukréa Electromatique <denis@eukrea.com> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License | ||
| 7 | * as published by the Free Software Foundation; either version 2 | ||
| 8 | * of the License, or (at your option) any later version. | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | */ | ||
| 14 | |||
| 15 | /* | ||
| 16 | * Module contains : i.MX287 + 128MB DDR2 + NAND + 2 x Ethernet PHY + RTC | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include "imx28-eukrea-mbmx283lc.dts" | ||
| 20 | |||
| 21 | / { | ||
| 22 | model = "Eukrea Electromatique MBMX287LC"; | ||
| 23 | compatible = "eukrea,mbmx287lc", "eukrea,mbmx283lc", "eukrea,mbmx28lc", "fsl,imx28"; | ||
| 24 | |||
| 25 | memory { | ||
| 26 | reg = <0x40000000 0x08000000>; | ||
| 27 | }; | ||
| 28 | }; | ||
| 29 | |||
| 30 | &mac1 { | ||
| 31 | phy-mode = "rmii"; | ||
| 32 | pinctrl-names = "default"; | ||
| 33 | pinctrl-0 = <&mac1_pins_a>; | ||
| 34 | phy-reset-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; | ||
| 35 | status = "okay"; | ||
| 36 | }; | ||
| 37 | |||
| 38 | &pinctrl { | ||
| 39 | pinctrl-names = "default"; | ||
| 40 | pinctrl-0 = <&hog_pins_cpuimx283 &hog_pins_cpuimx287>; | ||
| 41 | hog_pins_cpuimx287: hog-cpuimx287@0 { | ||
| 42 | reg = <0>; | ||
| 43 | fsl,pinmux-ids = < | ||
| 44 | MX28_PAD_SPDIF__GPIO_3_27 | ||
| 45 | >; | ||
| 46 | fsl,drive-strength = <MXS_DRIVE_4mA>; | ||
| 47 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | ||
| 48 | fsl,pull-up = <MXS_PULL_ENABLE>; | ||
| 49 | }; | ||
| 50 | }; | ||
diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi b/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi new file mode 100644 index 000000000000..927b391d2058 --- /dev/null +++ b/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi | |||
| @@ -0,0 +1,326 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Eukréa Electromatique <eric@eukrea.com> | ||
| 3 | * Copyright 2013 Eukréa Electromatique <denis@eukrea.com> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License | ||
| 7 | * as published by the Free Software Foundation; either version 2 | ||
| 8 | * of the License, or (at your option) any later version. | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <dt-bindings/input/input.h> | ||
| 16 | #include <dt-bindings/gpio/gpio.h> | ||
| 17 | #include "imx28.dtsi" | ||
| 18 | |||
| 19 | / { | ||
| 20 | model = "Eukrea Electromatique MBMX28LC"; | ||
| 21 | compatible = "eukrea,mbmx28lc", "fsl,imx28"; | ||
| 22 | |||
| 23 | backlight { | ||
| 24 | compatible = "pwm-backlight"; | ||
| 25 | pwms = <&pwm 4 1000000>; | ||
| 26 | brightness-levels = <0 25 50 75 100 125 150 175 200 225 255>; | ||
| 27 | default-brightness-level = <10>; | ||
| 28 | }; | ||
| 29 | |||
| 30 | button-sw3 { | ||
| 31 | compatible = "gpio-keys"; | ||
| 32 | pinctrl-names = "default"; | ||
| 33 | pinctrl-0 = <&gpio_button_sw3_pins_mbmx28lc>; | ||
| 34 | |||
| 35 | sw3 { | ||
| 36 | label = "SW3"; | ||
| 37 | gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; | ||
| 38 | linux,code = <BTN_MISC>; | ||
| 39 | gpio-key,wakeup; | ||
| 40 | }; | ||
| 41 | }; | ||
| 42 | |||
| 43 | button-sw4 { | ||
| 44 | compatible = "gpio-keys"; | ||
| 45 | pinctrl-names = "default"; | ||
| 46 | pinctrl-0 = <&gpio_button_sw4_pins_mbmx28lc>; | ||
| 47 | |||
| 48 | sw4 { | ||
| 49 | label = "SW4"; | ||
| 50 | gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; | ||
| 51 | linux,code = <BTN_MISC>; | ||
| 52 | gpio-key,wakeup; | ||
| 53 | }; | ||
| 54 | }; | ||
| 55 | |||
| 56 | led-d6 { | ||
| 57 | compatible = "gpio-leds"; | ||
| 58 | pinctrl-names = "default"; | ||
| 59 | pinctrl-0 = <&led_d6_pins_mbmx28lc>; | ||
| 60 | |||
| 61 | led1 { | ||
| 62 | label = "d6"; | ||
| 63 | gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; | ||
| 64 | linux,default-trigger = "heartbeat"; | ||
| 65 | }; | ||
| 66 | }; | ||
| 67 | |||
| 68 | led-d7 { | ||
| 69 | compatible = "gpio-leds"; | ||
| 70 | pinctrl-names = "default"; | ||
| 71 | pinctrl-0 = <&led_d7_pins_mbmx28lc>; | ||
| 72 | |||
| 73 | led1 { | ||
| 74 | label = "d7"; | ||
| 75 | gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; | ||
| 76 | linux,default-trigger = "default-on"; | ||
| 77 | }; | ||
| 78 | }; | ||
| 79 | |||
| 80 | regulators { | ||
| 81 | compatible = "simple-bus"; | ||
| 82 | #address-cells = <1>; | ||
| 83 | #size-cells = <0>; | ||
| 84 | |||
| 85 | reg_3p3v: regulator@0 { | ||
| 86 | compatible = "regulator-fixed"; | ||
| 87 | regulator-name = "3P3V"; | ||
| 88 | regulator-min-microvolt = <3300000>; | ||
| 89 | regulator-max-microvolt = <3300000>; | ||
| 90 | regulator-always-on; | ||
| 91 | }; | ||
| 92 | |||
| 93 | reg_lcd_3v3: regulator@1 { | ||
| 94 | compatible = "regulator-fixed"; | ||
| 95 | pinctrl-names = "default"; | ||
| 96 | pinctrl-0 = <®_lcd_3v3_pins_mbmx28lc>; | ||
| 97 | regulator-name = "lcd-3v3"; | ||
| 98 | regulator-min-microvolt = <3300000>; | ||
| 99 | regulator-max-microvolt = <3300000>; | ||
| 100 | gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; | ||
| 101 | enable-active-high; | ||
| 102 | }; | ||
| 103 | |||
| 104 | reg_usb0_vbus: regulator@2 { | ||
| 105 | compatible = "regulator-fixed"; | ||
| 106 | pinctrl-names = "default"; | ||
| 107 | pinctrl-0 = <®_usb0_vbus_pins_mbmx28lc>; | ||
| 108 | regulator-name = "usb0_vbus"; | ||
| 109 | regulator-min-microvolt = <5000000>; | ||
| 110 | regulator-max-microvolt = <5000000>; | ||
| 111 | gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; | ||
| 112 | enable-active-high; | ||
| 113 | }; | ||
| 114 | |||
| 115 | reg_usb1_vbus: regulator@3 { | ||
| 116 | compatible = "regulator-fixed"; | ||
| 117 | pinctrl-names = "default"; | ||
| 118 | pinctrl-0 = <®_usb1_vbus_pins_mbmx28lc>; | ||
| 119 | regulator-name = "usb1_vbus"; | ||
| 120 | regulator-min-microvolt = <5000000>; | ||
| 121 | regulator-max-microvolt = <5000000>; | ||
| 122 | gpio = <&gpio1 19 GPIO_ACTIVE_HIGH>; | ||
| 123 | enable-active-high; | ||
| 124 | }; | ||
| 125 | }; | ||
| 126 | |||
| 127 | sound { | ||
| 128 | compatible = "fsl,imx28-mbmx28lc-sgtl5000", | ||
| 129 | "fsl,mxs-audio-sgtl5000"; | ||
| 130 | model = "imx28-mbmx28lc-sgtl5000"; | ||
| 131 | saif-controllers = <&saif0 &saif1>; | ||
| 132 | audio-codec = <&sgtl5000>; | ||
| 133 | }; | ||
| 134 | }; | ||
| 135 | |||
| 136 | &duart { | ||
| 137 | pinctrl-names = "default"; | ||
| 138 | pinctrl-0 = <&duart_4pins_a>; | ||
| 139 | status = "okay"; | ||
| 140 | }; | ||
| 141 | |||
| 142 | &i2c0 { | ||
| 143 | pinctrl-names = "default"; | ||
| 144 | pinctrl-0 = <&i2c0_pins_a>; | ||
| 145 | status = "okay"; | ||
| 146 | |||
| 147 | sgtl5000: codec@0a { | ||
| 148 | compatible = "fsl,sgtl5000"; | ||
| 149 | reg = <0x0a>; | ||
| 150 | VDDA-supply = <®_3p3v>; | ||
| 151 | VDDIO-supply = <®_3p3v>; | ||
| 152 | clocks = <&saif0>; | ||
| 153 | }; | ||
| 154 | }; | ||
| 155 | |||
| 156 | &lcdif { | ||
| 157 | pinctrl-names = "default"; | ||
| 158 | pinctrl-0 = <&lcdif_18bit_pins_a &lcdif_pins_mbmx28lc>; | ||
| 159 | lcd-supply = <®_lcd_3v3>; | ||
| 160 | display = <&display0>; | ||
| 161 | status = "okay"; | ||
| 162 | |||
| 163 | display0: display0 { | ||
| 164 | model = "43WVF1G-0"; | ||
| 165 | bits-per-pixel = <16>; | ||
| 166 | bus-width = <18>; | ||
| 167 | |||
| 168 | display-timings { | ||
| 169 | native-mode = <&timing0>; | ||
| 170 | timing0: timing0 { | ||
| 171 | clock-frequency = <9072000>; | ||
| 172 | hactive = <480>; | ||
| 173 | vactive = <272>; | ||
| 174 | hback-porch = <10>; | ||
| 175 | hfront-porch = <5>; | ||
| 176 | vback-porch = <8>; | ||
| 177 | vfront-porch = <8>; | ||
| 178 | hsync-len = <40>; | ||
| 179 | vsync-len = <10>; | ||
| 180 | hsync-active = <0>; | ||
| 181 | vsync-active = <0>; | ||
| 182 | de-active = <1>; | ||
| 183 | pixelclk-active = <1>; | ||
| 184 | }; | ||
| 185 | }; | ||
| 186 | }; | ||
| 187 | }; | ||
| 188 | |||
| 189 | &lradc { | ||
| 190 | fsl,lradc-touchscreen-wires = <4>; | ||
| 191 | status = "okay"; | ||
| 192 | }; | ||
| 193 | |||
| 194 | &pinctrl { | ||
| 195 | gpio_button_sw3_pins_mbmx28lc: gpio-button-sw3-mbmx28lc@0 { | ||
| 196 | reg = <0>; | ||
| 197 | fsl,pinmux-ids = < | ||
| 198 | MX28_PAD_LCD_D21__GPIO_1_21 | ||
| 199 | >; | ||
| 200 | fsl,drive-strength = <MXS_DRIVE_4mA>; | ||
| 201 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | ||
| 202 | fsl,pull-up = <MXS_PULL_DISABLE>; | ||
| 203 | }; | ||
| 204 | |||
| 205 | gpio_button_sw4_pins_mbmx28lc: gpio-button-sw4-mbmx28lc@0 { | ||
| 206 | reg = <0>; | ||
| 207 | fsl,pinmux-ids = < | ||
| 208 | MX28_PAD_LCD_D20__GPIO_1_20 | ||
| 209 | >; | ||
| 210 | fsl,drive-strength = <MXS_DRIVE_4mA>; | ||
| 211 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | ||
| 212 | fsl,pull-up = <MXS_PULL_DISABLE>; | ||
| 213 | }; | ||
| 214 | |||
| 215 | lcdif_pins_mbmx28lc: lcdif-mbmx28lc@0 { | ||
| 216 | reg = <0>; | ||
| 217 | fsl,pinmux-ids = < | ||
| 218 | MX28_PAD_LCD_VSYNC__LCD_VSYNC | ||
| 219 | MX28_PAD_LCD_HSYNC__LCD_HSYNC | ||
| 220 | MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | ||
| 221 | MX28_PAD_LCD_ENABLE__LCD_ENABLE | ||
| 222 | >; | ||
| 223 | fsl,drive-strength = <MXS_DRIVE_4mA>; | ||
| 224 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | ||
| 225 | fsl,pull-up = <MXS_PULL_DISABLE>; | ||
| 226 | }; | ||
| 227 | |||
| 228 | led_d6_pins_mbmx28lc: led-d6-mbmx28lc@0 { | ||
| 229 | reg = <0>; | ||
| 230 | fsl,pinmux-ids = < | ||
| 231 | MX28_PAD_LCD_D23__GPIO_1_23 | ||
| 232 | >; | ||
| 233 | fsl,drive-strength = <MXS_DRIVE_4mA>; | ||
| 234 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | ||
| 235 | fsl,pull-up = <MXS_PULL_DISABLE>; | ||
| 236 | }; | ||
| 237 | |||
| 238 | led_d7_pins_mbmx28lc: led-d7-mbmx28lc@0 { | ||
| 239 | reg = <0>; | ||
| 240 | fsl,pinmux-ids = < | ||
| 241 | MX28_PAD_LCD_D22__GPIO_1_22 | ||
| 242 | >; | ||
| 243 | fsl,drive-strength = <MXS_DRIVE_4mA>; | ||
| 244 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | ||
| 245 | fsl,pull-up = <MXS_PULL_DISABLE>; | ||
| 246 | }; | ||
| 247 | |||
| 248 | reg_lcd_3v3_pins_mbmx28lc: lcd-3v3-mbmx28lc@0 { | ||
| 249 | reg = <0>; | ||
| 250 | fsl,pinmux-ids = < | ||
| 251 | MX28_PAD_LCD_RESET__GPIO_3_30 | ||
| 252 | >; | ||
| 253 | fsl,drive-strength = <MXS_DRIVE_4mA>; | ||
| 254 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | ||
| 255 | fsl,pull-up = <MXS_PULL_DISABLE>; | ||
| 256 | }; | ||
| 257 | |||
| 258 | reg_usb0_vbus_pins_mbmx28lc: reg-usb0-vbus-mbmx28lc@0 { | ||
| 259 | reg = <0>; | ||
| 260 | fsl,pinmux-ids = < | ||
| 261 | MX28_PAD_LCD_D18__GPIO_1_18 | ||
| 262 | >; | ||
| 263 | fsl,drive-strength = <MXS_DRIVE_4mA>; | ||
| 264 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | ||
| 265 | fsl,pull-up = <MXS_PULL_DISABLE>; | ||
| 266 | }; | ||
| 267 | |||
| 268 | reg_usb1_vbus_pins_mbmx28lc: reg-usb1-vbus-mbmx28lc@0 { | ||
| 269 | reg = <0>; | ||
| 270 | fsl,pinmux-ids = < | ||
| 271 | MX28_PAD_LCD_D19__GPIO_1_19 | ||
| 272 | >; | ||
| 273 | fsl,drive-strength = <MXS_DRIVE_4mA>; | ||
| 274 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | ||
| 275 | fsl,pull-up = <MXS_PULL_DISABLE>; | ||
| 276 | }; | ||
| 277 | }; | ||
| 278 | |||
| 279 | &pwm { | ||
| 280 | pinctrl-names = "default"; | ||
| 281 | pinctrl-0 = <&pwm4_pins_a>; | ||
| 282 | status = "okay"; | ||
| 283 | }; | ||
| 284 | |||
| 285 | &saif0 { | ||
| 286 | pinctrl-names = "default"; | ||
| 287 | pinctrl-0 = <&saif0_pins_a>; | ||
| 288 | status = "okay"; | ||
| 289 | }; | ||
| 290 | |||
| 291 | &saif1 { | ||
| 292 | pinctrl-names = "default"; | ||
| 293 | pinctrl-0 = <&saif1_pins_a>; | ||
| 294 | fsl,saif-master = <&saif0>; | ||
| 295 | status = "okay"; | ||
| 296 | }; | ||
| 297 | |||
| 298 | &ssp0 { | ||
| 299 | compatible = "fsl,imx28-mmc"; | ||
| 300 | pinctrl-names = "default"; | ||
| 301 | pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_cd_cfg &mmc0_sck_cfg>; | ||
| 302 | bus-width = <4>; | ||
| 303 | cd-inverted; | ||
| 304 | status = "okay"; | ||
| 305 | }; | ||
| 306 | |||
| 307 | &usb0 { | ||
| 308 | disable-over-current; | ||
| 309 | vbus-supply = <®_usb0_vbus>; | ||
| 310 | status = "okay"; | ||
| 311 | pinctrl-names = "default"; | ||
| 312 | pinctrl-0 = <&usb0_id_pins_b>; | ||
| 313 | }; | ||
| 314 | |||
| 315 | &usb1 { | ||
| 316 | vbus-supply = <®_usb1_vbus>; | ||
| 317 | status = "okay"; | ||
| 318 | }; | ||
| 319 | |||
| 320 | &usbphy0 { | ||
| 321 | status = "okay"; | ||
| 322 | }; | ||
| 323 | |||
| 324 | &usbphy1 { | ||
| 325 | status = "okay"; | ||
| 326 | }; | ||
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index 4267c2b05d60..e4cc44c98585 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts | |||
| @@ -193,6 +193,7 @@ | |||
| 193 | i2c0: i2c@80058000 { | 193 | i2c0: i2c@80058000 { |
| 194 | pinctrl-names = "default"; | 194 | pinctrl-names = "default"; |
| 195 | pinctrl-0 = <&i2c0_pins_a>; | 195 | pinctrl-0 = <&i2c0_pins_a>; |
| 196 | clock-frequency = <400000>; | ||
| 196 | status = "okay"; | 197 | status = "okay"; |
| 197 | 198 | ||
| 198 | sgtl5000: codec@0a { | 199 | sgtl5000: codec@0a { |
| @@ -278,33 +279,39 @@ | |||
| 278 | 279 | ||
| 279 | regulators { | 280 | regulators { |
| 280 | compatible = "simple-bus"; | 281 | compatible = "simple-bus"; |
| 282 | #address-cells = <1>; | ||
| 283 | #size-cells = <0>; | ||
| 281 | 284 | ||
| 282 | reg_3p3v: 3p3v { | 285 | reg_3p3v: regulator@0 { |
| 283 | compatible = "regulator-fixed"; | 286 | compatible = "regulator-fixed"; |
| 287 | reg = <0>; | ||
| 284 | regulator-name = "3P3V"; | 288 | regulator-name = "3P3V"; |
| 285 | regulator-min-microvolt = <3300000>; | 289 | regulator-min-microvolt = <3300000>; |
| 286 | regulator-max-microvolt = <3300000>; | 290 | regulator-max-microvolt = <3300000>; |
| 287 | regulator-always-on; | 291 | regulator-always-on; |
| 288 | }; | 292 | }; |
| 289 | 293 | ||
| 290 | reg_vddio_sd0: vddio-sd0 { | 294 | reg_vddio_sd0: regulator@1 { |
| 291 | compatible = "regulator-fixed"; | 295 | compatible = "regulator-fixed"; |
| 296 | reg = <1>; | ||
| 292 | regulator-name = "vddio-sd0"; | 297 | regulator-name = "vddio-sd0"; |
| 293 | regulator-min-microvolt = <3300000>; | 298 | regulator-min-microvolt = <3300000>; |
| 294 | regulator-max-microvolt = <3300000>; | 299 | regulator-max-microvolt = <3300000>; |
| 295 | gpio = <&gpio3 28 0>; | 300 | gpio = <&gpio3 28 0>; |
| 296 | }; | 301 | }; |
| 297 | 302 | ||
| 298 | reg_fec_3v3: fec-3v3 { | 303 | reg_fec_3v3: regulator@2 { |
| 299 | compatible = "regulator-fixed"; | 304 | compatible = "regulator-fixed"; |
| 305 | reg = <2>; | ||
| 300 | regulator-name = "fec-3v3"; | 306 | regulator-name = "fec-3v3"; |
| 301 | regulator-min-microvolt = <3300000>; | 307 | regulator-min-microvolt = <3300000>; |
| 302 | regulator-max-microvolt = <3300000>; | 308 | regulator-max-microvolt = <3300000>; |
| 303 | gpio = <&gpio2 15 0>; | 309 | gpio = <&gpio2 15 0>; |
| 304 | }; | 310 | }; |
| 305 | 311 | ||
| 306 | reg_usb0_vbus: usb0_vbus { | 312 | reg_usb0_vbus: regulator@3 { |
| 307 | compatible = "regulator-fixed"; | 313 | compatible = "regulator-fixed"; |
| 314 | reg = <3>; | ||
| 308 | regulator-name = "usb0_vbus"; | 315 | regulator-name = "usb0_vbus"; |
| 309 | regulator-min-microvolt = <5000000>; | 316 | regulator-min-microvolt = <5000000>; |
| 310 | regulator-max-microvolt = <5000000>; | 317 | regulator-max-microvolt = <5000000>; |
| @@ -312,8 +319,9 @@ | |||
| 312 | enable-active-high; | 319 | enable-active-high; |
| 313 | }; | 320 | }; |
| 314 | 321 | ||
| 315 | reg_usb1_vbus: usb1_vbus { | 322 | reg_usb1_vbus: regulator@4 { |
| 316 | compatible = "regulator-fixed"; | 323 | compatible = "regulator-fixed"; |
| 324 | reg = <4>; | ||
| 317 | regulator-name = "usb1_vbus"; | 325 | regulator-name = "usb1_vbus"; |
| 318 | regulator-min-microvolt = <5000000>; | 326 | regulator-min-microvolt = <5000000>; |
| 319 | regulator-max-microvolt = <5000000>; | 327 | regulator-max-microvolt = <5000000>; |
| @@ -321,8 +329,9 @@ | |||
| 321 | enable-active-high; | 329 | enable-active-high; |
| 322 | }; | 330 | }; |
| 323 | 331 | ||
| 324 | reg_lcd_3v3: lcd-3v3 { | 332 | reg_lcd_3v3: regulator@5 { |
| 325 | compatible = "regulator-fixed"; | 333 | compatible = "regulator-fixed"; |
| 334 | reg = <5>; | ||
| 326 | regulator-name = "lcd-3v3"; | 335 | regulator-name = "lcd-3v3"; |
| 327 | regulator-min-microvolt = <3300000>; | 336 | regulator-min-microvolt = <3300000>; |
| 328 | regulator-max-microvolt = <3300000>; | 337 | regulator-max-microvolt = <3300000>; |
| @@ -330,8 +339,9 @@ | |||
| 330 | enable-active-high; | 339 | enable-active-high; |
| 331 | }; | 340 | }; |
| 332 | 341 | ||
| 333 | reg_can_3v3: can-3v3 { | 342 | reg_can_3v3: regulator@6 { |
| 334 | compatible = "regulator-fixed"; | 343 | compatible = "regulator-fixed"; |
| 344 | reg = <6>; | ||
| 335 | regulator-name = "can-3v3"; | 345 | regulator-name = "can-3v3"; |
| 336 | regulator-min-microvolt = <3300000>; | 346 | regulator-min-microvolt = <3300000>; |
| 337 | regulator-max-microvolt = <3300000>; | 347 | regulator-max-microvolt = <3300000>; |
diff --git a/arch/arm/boot/dts/imx28-m28cu3.dts b/arch/arm/boot/dts/imx28-m28cu3.dts index d3958da60bd7..9348ce59dda4 100644 --- a/arch/arm/boot/dts/imx28-m28cu3.dts +++ b/arch/arm/boot/dts/imx28-m28cu3.dts | |||
| @@ -116,7 +116,6 @@ | |||
| 116 | pinctrl-0 = <&lcdif_24bit_pins_a | 116 | pinctrl-0 = <&lcdif_24bit_pins_a |
| 117 | &lcdif_pins_m28>; | 117 | &lcdif_pins_m28>; |
| 118 | display = <&display>; | 118 | display = <&display>; |
| 119 | reset-active-high; | ||
| 120 | status = "okay"; | 119 | status = "okay"; |
| 121 | 120 | ||
| 122 | display: display0 { | 121 | display: display0 { |
| @@ -180,7 +179,7 @@ | |||
| 180 | usb1: usb@80090000 { | 179 | usb1: usb@80090000 { |
| 181 | vbus-supply = <®_usb1_vbus>; | 180 | vbus-supply = <®_usb1_vbus>; |
| 182 | pinctrl-names = "default"; | 181 | pinctrl-names = "default"; |
| 183 | pinctrl-0 = <&usbphy1_pins_a>; | 182 | pinctrl-0 = <&usb1_pins_a>; |
| 184 | disable-over-current; | 183 | disable-over-current; |
| 185 | status = "okay"; | 184 | status = "okay"; |
| 186 | }; | 185 | }; |
| @@ -229,33 +228,39 @@ | |||
| 229 | 228 | ||
| 230 | regulators { | 229 | regulators { |
| 231 | compatible = "simple-bus"; | 230 | compatible = "simple-bus"; |
| 231 | #address-cells = <1>; | ||
| 232 | #size-cells = <0>; | ||
| 232 | 233 | ||
| 233 | reg_3p3v: 3p3v { | 234 | reg_3p3v: regulator@0 { |
| 234 | compatible = "regulator-fixed"; | 235 | compatible = "regulator-fixed"; |
| 236 | reg = <0>; | ||
| 235 | regulator-name = "3P3V"; | 237 | regulator-name = "3P3V"; |
| 236 | regulator-min-microvolt = <3300000>; | 238 | regulator-min-microvolt = <3300000>; |
| 237 | regulator-max-microvolt = <3300000>; | 239 | regulator-max-microvolt = <3300000>; |
| 238 | regulator-always-on; | 240 | regulator-always-on; |
| 239 | }; | 241 | }; |
| 240 | 242 | ||
| 241 | reg_vddio_sd0: vddio-sd0 { | 243 | reg_vddio_sd0: regulator@1 { |
| 242 | compatible = "regulator-fixed"; | 244 | compatible = "regulator-fixed"; |
| 245 | reg = <1>; | ||
| 243 | regulator-name = "vddio-sd0"; | 246 | regulator-name = "vddio-sd0"; |
| 244 | regulator-min-microvolt = <3300000>; | 247 | regulator-min-microvolt = <3300000>; |
| 245 | regulator-max-microvolt = <3300000>; | 248 | regulator-max-microvolt = <3300000>; |
| 246 | gpio = <&gpio3 29 0>; | 249 | gpio = <&gpio3 29 0>; |
| 247 | }; | 250 | }; |
| 248 | 251 | ||
| 249 | reg_vddio_sd1: vddio-sd1 { | 252 | reg_vddio_sd1: regulator@2 { |
| 250 | compatible = "regulator-fixed"; | 253 | compatible = "regulator-fixed"; |
| 254 | reg = <2>; | ||
| 251 | regulator-name = "vddio-sd1"; | 255 | regulator-name = "vddio-sd1"; |
| 252 | regulator-min-microvolt = <3300000>; | 256 | regulator-min-microvolt = <3300000>; |
| 253 | regulator-max-microvolt = <3300000>; | 257 | regulator-max-microvolt = <3300000>; |
| 254 | gpio = <&gpio2 19 0>; | 258 | gpio = <&gpio2 19 0>; |
| 255 | }; | 259 | }; |
| 256 | 260 | ||
| 257 | reg_usb1_vbus: usb1_vbus { | 261 | reg_usb1_vbus: regulator@3 { |
| 258 | compatible = "regulator-fixed"; | 262 | compatible = "regulator-fixed"; |
| 263 | reg = <3>; | ||
| 259 | regulator-name = "usb1_vbus"; | 264 | regulator-name = "usb1_vbus"; |
| 260 | regulator-min-microvolt = <5000000>; | 265 | regulator-min-microvolt = <5000000>; |
| 261 | regulator-max-microvolt = <5000000>; | 266 | regulator-max-microvolt = <5000000>; |
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts index 8e2477fbe1d7..f0ad7b9b9d9a 100644 --- a/arch/arm/boot/dts/imx28-m28evk.dts +++ b/arch/arm/boot/dts/imx28-m28evk.dts | |||
| @@ -194,7 +194,7 @@ | |||
| 194 | }; | 194 | }; |
| 195 | 195 | ||
| 196 | rtc: rtc@68 { | 196 | rtc: rtc@68 { |
| 197 | compatible = "stm,mt41t62"; | 197 | compatible = "stm,m41t62"; |
| 198 | reg = <0x68>; | 198 | reg = <0x68>; |
| 199 | }; | 199 | }; |
| 200 | }; | 200 | }; |
| @@ -248,14 +248,14 @@ | |||
| 248 | usb0: usb@80080000 { | 248 | usb0: usb@80080000 { |
| 249 | vbus-supply = <®_usb0_vbus>; | 249 | vbus-supply = <®_usb0_vbus>; |
| 250 | pinctrl-names = "default"; | 250 | pinctrl-names = "default"; |
| 251 | pinctrl-0 = <&usbphy0_pins_a>; | 251 | pinctrl-0 = <&usb0_pins_a>; |
| 252 | status = "okay"; | 252 | status = "okay"; |
| 253 | }; | 253 | }; |
| 254 | 254 | ||
| 255 | usb1: usb@80090000 { | 255 | usb1: usb@80090000 { |
| 256 | vbus-supply = <®_usb1_vbus>; | 256 | vbus-supply = <®_usb1_vbus>; |
| 257 | pinctrl-names = "default"; | 257 | pinctrl-names = "default"; |
| 258 | pinctrl-0 = <&usbphy1_pins_a>; | 258 | pinctrl-0 = <&usb1_pins_a>; |
| 259 | status = "okay"; | 259 | status = "okay"; |
| 260 | }; | 260 | }; |
| 261 | 261 | ||
| @@ -285,33 +285,39 @@ | |||
| 285 | 285 | ||
| 286 | regulators { | 286 | regulators { |
| 287 | compatible = "simple-bus"; | 287 | compatible = "simple-bus"; |
| 288 | #address-cells = <1>; | ||
| 289 | #size-cells = <0>; | ||
| 288 | 290 | ||
| 289 | reg_3p3v: 3p3v { | 291 | reg_3p3v: regulator@0 { |
| 290 | compatible = "regulator-fixed"; | 292 | compatible = "regulator-fixed"; |
| 293 | reg = <0>; | ||
| 291 | regulator-name = "3P3V"; | 294 | regulator-name = "3P3V"; |
| 292 | regulator-min-microvolt = <3300000>; | 295 | regulator-min-microvolt = <3300000>; |
| 293 | regulator-max-microvolt = <3300000>; | 296 | regulator-max-microvolt = <3300000>; |
| 294 | regulator-always-on; | 297 | regulator-always-on; |
| 295 | }; | 298 | }; |
| 296 | 299 | ||
| 297 | reg_vddio_sd0: vddio-sd0 { | 300 | reg_vddio_sd0: regulator@1 { |
| 298 | compatible = "regulator-fixed"; | 301 | compatible = "regulator-fixed"; |
| 302 | reg = <1>; | ||
| 299 | regulator-name = "vddio-sd0"; | 303 | regulator-name = "vddio-sd0"; |
| 300 | regulator-min-microvolt = <3300000>; | 304 | regulator-min-microvolt = <3300000>; |
| 301 | regulator-max-microvolt = <3300000>; | 305 | regulator-max-microvolt = <3300000>; |
| 302 | gpio = <&gpio3 28 0>; | 306 | gpio = <&gpio3 28 0>; |
| 303 | }; | 307 | }; |
| 304 | 308 | ||
| 305 | reg_usb0_vbus: usb0_vbus { | 309 | reg_usb0_vbus: regulator@2 { |
| 306 | compatible = "regulator-fixed"; | 310 | compatible = "regulator-fixed"; |
| 311 | reg = <2>; | ||
| 307 | regulator-name = "usb0_vbus"; | 312 | regulator-name = "usb0_vbus"; |
| 308 | regulator-min-microvolt = <5000000>; | 313 | regulator-min-microvolt = <5000000>; |
| 309 | regulator-max-microvolt = <5000000>; | 314 | regulator-max-microvolt = <5000000>; |
| 310 | gpio = <&gpio3 12 0>; | 315 | gpio = <&gpio3 12 0>; |
| 311 | }; | 316 | }; |
| 312 | 317 | ||
| 313 | reg_usb1_vbus: usb1_vbus { | 318 | reg_usb1_vbus: regulator@3 { |
| 314 | compatible = "regulator-fixed"; | 319 | compatible = "regulator-fixed"; |
| 320 | reg = <3>; | ||
| 315 | regulator-name = "usb1_vbus"; | 321 | regulator-name = "usb1_vbus"; |
| 316 | regulator-min-microvolt = <5000000>; | 322 | regulator-min-microvolt = <5000000>; |
| 317 | regulator-max-microvolt = <5000000>; | 323 | regulator-max-microvolt = <5000000>; |
diff --git a/arch/arm/boot/dts/imx28-sps1.dts b/arch/arm/boot/dts/imx28-sps1.dts index 4870f07bf56a..0ce3cb8e7914 100644 --- a/arch/arm/boot/dts/imx28-sps1.dts +++ b/arch/arm/boot/dts/imx28-sps1.dts | |||
| @@ -106,7 +106,7 @@ | |||
| 106 | usb0: usb@80080000 { | 106 | usb0: usb@80080000 { |
| 107 | vbus-supply = <®_usb0_vbus>; | 107 | vbus-supply = <®_usb0_vbus>; |
| 108 | pinctrl-names = "default"; | 108 | pinctrl-names = "default"; |
| 109 | pinctrl-0 = <&usbphy0_pins_b>; | 109 | pinctrl-0 = <&usb0_pins_b>; |
| 110 | status = "okay"; | 110 | status = "okay"; |
| 111 | }; | 111 | }; |
| 112 | 112 | ||
| @@ -127,9 +127,12 @@ | |||
| 127 | 127 | ||
| 128 | regulators { | 128 | regulators { |
| 129 | compatible = "simple-bus"; | 129 | compatible = "simple-bus"; |
| 130 | #address-cells = <1>; | ||
| 131 | #size-cells = <0>; | ||
| 130 | 132 | ||
| 131 | reg_usb0_vbus: usb0_vbus { | 133 | reg_usb0_vbus: regulator@0 { |
| 132 | compatible = "regulator-fixed"; | 134 | compatible = "regulator-fixed"; |
| 135 | reg = <0>; | ||
| 133 | regulator-name = "usb0_vbus"; | 136 | regulator-name = "usb0_vbus"; |
| 134 | regulator-min-microvolt = <5000000>; | 137 | regulator-min-microvolt = <5000000>; |
| 135 | regulator-max-microvolt = <5000000>; | 138 | regulator-max-microvolt = <5000000>; |
diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts index be5a0550d58c..e14bd86f3e99 100644 --- a/arch/arm/boot/dts/imx28-tx28.dts +++ b/arch/arm/boot/dts/imx28-tx28.dts | |||
| @@ -43,9 +43,12 @@ | |||
| 43 | 43 | ||
| 44 | regulators { | 44 | regulators { |
| 45 | compatible = "simple-bus"; | 45 | compatible = "simple-bus"; |
| 46 | #address-cells = <1>; | ||
| 47 | #size-cells = <0>; | ||
| 46 | 48 | ||
| 47 | reg_usb0_vbus: usb0_vbus { | 49 | reg_usb0_vbus: regulator@0 { |
| 48 | compatible = "regulator-fixed"; | 50 | compatible = "regulator-fixed"; |
| 51 | reg = <0>; | ||
| 49 | regulator-name = "usb0_vbus"; | 52 | regulator-name = "usb0_vbus"; |
| 50 | regulator-min-microvolt = <5000000>; | 53 | regulator-min-microvolt = <5000000>; |
| 51 | regulator-max-microvolt = <5000000>; | 54 | regulator-max-microvolt = <5000000>; |
| @@ -53,8 +56,9 @@ | |||
| 53 | enable-active-high; | 56 | enable-active-high; |
| 54 | }; | 57 | }; |
| 55 | 58 | ||
| 56 | reg_usb1_vbus: usb1_vbus { | 59 | reg_usb1_vbus: regulator@1 { |
| 57 | compatible = "regulator-fixed"; | 60 | compatible = "regulator-fixed"; |
| 61 | reg = <1>; | ||
| 58 | regulator-name = "usb1_vbus"; | 62 | regulator-name = "usb1_vbus"; |
| 59 | regulator-min-microvolt = <5000000>; | 63 | regulator-min-microvolt = <5000000>; |
| 60 | regulator-max-microvolt = <5000000>; | 64 | regulator-max-microvolt = <5000000>; |
| @@ -62,35 +66,38 @@ | |||
| 62 | enable-active-high; | 66 | enable-active-high; |
| 63 | }; | 67 | }; |
| 64 | 68 | ||
| 65 | reg_2p5v: 2p5v { | 69 | reg_2p5v: regulator@2 { |
| 66 | compatible = "regulator-fixed"; | 70 | compatible = "regulator-fixed"; |
| 71 | reg = <2>; | ||
| 67 | regulator-name = "2P5V"; | 72 | regulator-name = "2P5V"; |
| 68 | regulator-min-microvolt = <2500000>; | 73 | regulator-min-microvolt = <2500000>; |
| 69 | regulator-max-microvolt = <2500000>; | 74 | regulator-max-microvolt = <2500000>; |
| 70 | regulator-always-on; | 75 | regulator-always-on; |
| 71 | }; | 76 | }; |
| 72 | 77 | ||
| 73 | reg_3p3v: 3p3v { | 78 | reg_3p3v: regulator@3 { |
| 74 | compatible = "regulator-fixed"; | 79 | compatible = "regulator-fixed"; |
| 80 | reg = <3>; | ||
| 75 | regulator-name = "3P3V"; | 81 | regulator-name = "3P3V"; |
| 76 | regulator-min-microvolt = <3300000>; | 82 | regulator-min-microvolt = <3300000>; |
| 77 | regulator-max-microvolt = <3300000>; | 83 | regulator-max-microvolt = <3300000>; |
| 78 | regulator-always-on; | 84 | regulator-always-on; |
| 79 | }; | 85 | }; |
| 80 | 86 | ||
| 81 | reg_can_xcvr: can-xcvr { | 87 | reg_can_xcvr: regulator@4 { |
| 82 | compatible = "regulator-fixed"; | 88 | compatible = "regulator-fixed"; |
| 89 | reg = <4>; | ||
| 83 | regulator-name = "CAN XCVR"; | 90 | regulator-name = "CAN XCVR"; |
| 84 | regulator-min-microvolt = <3300000>; | 91 | regulator-min-microvolt = <3300000>; |
| 85 | regulator-max-microvolt = <3300000>; | 92 | regulator-max-microvolt = <3300000>; |
| 86 | gpio = <&gpio1 0 0>; | 93 | gpio = <&gpio1 0 0>; |
| 87 | enable-active-low; | ||
| 88 | pinctrl-names = "default"; | 94 | pinctrl-names = "default"; |
| 89 | pinctrl-0 = <&tx28_flexcan_xcvr_pins>; | 95 | pinctrl-0 = <&tx28_flexcan_xcvr_pins>; |
| 90 | }; | 96 | }; |
| 91 | 97 | ||
| 92 | reg_lcd: lcd-power { | 98 | reg_lcd: regulator@5 { |
| 93 | compatible = "regulator-fixed"; | 99 | compatible = "regulator-fixed"; |
| 100 | reg = <5>; | ||
| 94 | regulator-name = "LCD POWER"; | 101 | regulator-name = "LCD POWER"; |
| 95 | regulator-min-microvolt = <3300000>; | 102 | regulator-min-microvolt = <3300000>; |
| 96 | regulator-max-microvolt = <3300000>; | 103 | regulator-max-microvolt = <3300000>; |
| @@ -98,8 +105,9 @@ | |||
| 98 | enable-active-high; | 105 | enable-active-high; |
| 99 | }; | 106 | }; |
| 100 | 107 | ||
| 101 | reg_lcd_reset: lcd-reset { | 108 | reg_lcd_reset: regulator@6 { |
| 102 | compatible = "regulator-fixed"; | 109 | compatible = "regulator-fixed"; |
| 110 | reg = <6>; | ||
| 103 | regulator-name = "LCD RESET"; | 111 | regulator-name = "LCD RESET"; |
| 104 | regulator-min-microvolt = <3300000>; | 112 | regulator-min-microvolt = <3300000>; |
| 105 | regulator-max-microvolt = <3300000>; | 113 | regulator-max-microvolt = <3300000>; |
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index f8e9b20f6982..90a579532b8b 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi | |||
| @@ -32,6 +32,8 @@ | |||
| 32 | serial4 = &auart4; | 32 | serial4 = &auart4; |
| 33 | spi0 = &ssp1; | 33 | spi0 = &ssp1; |
| 34 | spi1 = &ssp2; | 34 | spi1 = &ssp2; |
| 35 | usbphy0 = &usbphy0; | ||
| 36 | usbphy1 = &usbphy1; | ||
| 35 | }; | 37 | }; |
| 36 | 38 | ||
| 37 | cpus { | 39 | cpus { |
| @@ -343,6 +345,19 @@ | |||
| 343 | fsl,pull-up = <MXS_PULL_DISABLE>; | 345 | fsl,pull-up = <MXS_PULL_DISABLE>; |
| 344 | }; | 346 | }; |
| 345 | 347 | ||
| 348 | auart2_pins_a: auart2-pins@0 { | ||
| 349 | reg = <0>; | ||
| 350 | fsl,pinmux-ids = < | ||
| 351 | MX28_PAD_AUART2_RX__AUART2_RX | ||
| 352 | MX28_PAD_AUART2_TX__AUART2_TX | ||
| 353 | MX28_PAD_AUART2_CTS__AUART2_CTS | ||
| 354 | MX28_PAD_AUART2_RTS__AUART2_RTS | ||
| 355 | >; | ||
| 356 | fsl,drive-strength = <MXS_DRIVE_4mA>; | ||
| 357 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | ||
| 358 | fsl,pull-up = <MXS_PULL_DISABLE>; | ||
| 359 | }; | ||
| 360 | |||
| 346 | auart3_pins_a: auart3@0 { | 361 | auart3_pins_a: auart3@0 { |
| 347 | reg = <0>; | 362 | reg = <0>; |
| 348 | fsl,pinmux-ids = < | 363 | fsl,pinmux-ids = < |
| @@ -655,6 +670,33 @@ | |||
| 655 | fsl,pull-up = <MXS_PULL_DISABLE>; | 670 | fsl,pull-up = <MXS_PULL_DISABLE>; |
| 656 | }; | 671 | }; |
| 657 | 672 | ||
| 673 | lcdif_18bit_pins_a: lcdif-18bit@0 { | ||
| 674 | reg = <0>; | ||
| 675 | fsl,pinmux-ids = < | ||
| 676 | MX28_PAD_LCD_D00__LCD_D0 | ||
| 677 | MX28_PAD_LCD_D01__LCD_D1 | ||
| 678 | MX28_PAD_LCD_D02__LCD_D2 | ||
| 679 | MX28_PAD_LCD_D03__LCD_D3 | ||
| 680 | MX28_PAD_LCD_D04__LCD_D4 | ||
| 681 | MX28_PAD_LCD_D05__LCD_D5 | ||
| 682 | MX28_PAD_LCD_D06__LCD_D6 | ||
| 683 | MX28_PAD_LCD_D07__LCD_D7 | ||
| 684 | MX28_PAD_LCD_D08__LCD_D8 | ||
| 685 | MX28_PAD_LCD_D09__LCD_D9 | ||
| 686 | MX28_PAD_LCD_D10__LCD_D10 | ||
| 687 | MX28_PAD_LCD_D11__LCD_D11 | ||
| 688 | MX28_PAD_LCD_D12__LCD_D12 | ||
| 689 | MX28_PAD_LCD_D13__LCD_D13 | ||
| 690 | MX28_PAD_LCD_D14__LCD_D14 | ||
| 691 | MX28_PAD_LCD_D15__LCD_D15 | ||
| 692 | MX28_PAD_LCD_D16__LCD_D16 | ||
| 693 | MX28_PAD_LCD_D17__LCD_D17 | ||
| 694 | >; | ||
| 695 | fsl,drive-strength = <MXS_DRIVE_4mA>; | ||
| 696 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | ||
| 697 | fsl,pull-up = <MXS_PULL_DISABLE>; | ||
| 698 | }; | ||
| 699 | |||
| 658 | lcdif_16bit_pins_a: lcdif-16bit@0 { | 700 | lcdif_16bit_pins_a: lcdif-16bit@0 { |
| 659 | reg = <0>; | 701 | reg = <0>; |
| 660 | fsl,pinmux-ids = < | 702 | fsl,pinmux-ids = < |
| @@ -743,7 +785,7 @@ | |||
| 743 | fsl,pull-up = <MXS_PULL_DISABLE>; | 785 | fsl,pull-up = <MXS_PULL_DISABLE>; |
| 744 | }; | 786 | }; |
| 745 | 787 | ||
| 746 | usbphy0_pins_a: usbphy0@0 { | 788 | usb0_pins_a: usb0@0 { |
| 747 | reg = <0>; | 789 | reg = <0>; |
| 748 | fsl,pinmux-ids = < | 790 | fsl,pinmux-ids = < |
| 749 | MX28_PAD_SSP2_SS2__USB0_OVERCURRENT | 791 | MX28_PAD_SSP2_SS2__USB0_OVERCURRENT |
| @@ -753,7 +795,7 @@ | |||
| 753 | fsl,pull-up = <MXS_PULL_DISABLE>; | 795 | fsl,pull-up = <MXS_PULL_DISABLE>; |
| 754 | }; | 796 | }; |
| 755 | 797 | ||
| 756 | usbphy0_pins_b: usbphy0@1 { | 798 | usb0_pins_b: usb0@1 { |
| 757 | reg = <1>; | 799 | reg = <1>; |
| 758 | fsl,pinmux-ids = < | 800 | fsl,pinmux-ids = < |
| 759 | MX28_PAD_AUART1_CTS__USB0_OVERCURRENT | 801 | MX28_PAD_AUART1_CTS__USB0_OVERCURRENT |
| @@ -763,7 +805,7 @@ | |||
| 763 | fsl,pull-up = <MXS_PULL_DISABLE>; | 805 | fsl,pull-up = <MXS_PULL_DISABLE>; |
| 764 | }; | 806 | }; |
| 765 | 807 | ||
| 766 | usbphy1_pins_a: usbphy1@0 { | 808 | usb1_pins_a: usb1@0 { |
| 767 | reg = <0>; | 809 | reg = <0>; |
| 768 | fsl,pinmux-ids = < | 810 | fsl,pinmux-ids = < |
| 769 | MX28_PAD_SSP2_SS1__USB1_OVERCURRENT | 811 | MX28_PAD_SSP2_SS1__USB1_OVERCURRENT |
| @@ -782,6 +824,17 @@ | |||
| 782 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | 824 | fsl,voltage = <MXS_VOLTAGE_HIGH>; |
| 783 | fsl,pull-up = <MXS_PULL_ENABLE>; | 825 | fsl,pull-up = <MXS_PULL_ENABLE>; |
| 784 | }; | 826 | }; |
| 827 | |||
| 828 | usb0_id_pins_b: usb0id1@0 { | ||
| 829 | reg = <0>; | ||
| 830 | fsl,pinmux-ids = < | ||
| 831 | MX28_PAD_PWM2__USB0_ID | ||
| 832 | >; | ||
| 833 | fsl,drive-strength = <MXS_DRIVE_12mA>; | ||
| 834 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | ||
| 835 | fsl,pull-up = <MXS_PULL_ENABLE>; | ||
| 836 | }; | ||
| 837 | |||
| 785 | }; | 838 | }; |
| 786 | 839 | ||
| 787 | digctl: digctl@8001c000 { | 840 | digctl: digctl@8001c000 { |
| @@ -946,6 +999,7 @@ | |||
| 946 | 20 21 22 23 24 25>; | 999 | 20 21 22 23 24 25>; |
| 947 | status = "disabled"; | 1000 | status = "disabled"; |
| 948 | clocks = <&clks 41>; | 1001 | clocks = <&clks 41>; |
| 1002 | #io-channel-cells = <1>; | ||
| 949 | }; | 1003 | }; |
| 950 | 1004 | ||
| 951 | spdif: spdif@80054000 { | 1005 | spdif: spdif@80054000 { |
| @@ -1130,4 +1184,9 @@ | |||
| 1130 | status = "disabled"; | 1184 | status = "disabled"; |
| 1131 | }; | 1185 | }; |
| 1132 | }; | 1186 | }; |
| 1187 | |||
| 1188 | iio_hwmon { | ||
| 1189 | compatible = "iio-hwmon"; | ||
| 1190 | io-channels = <&lradc 8>; | ||
| 1191 | }; | ||
| 1133 | }; | 1192 | }; |
diff --git a/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi b/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi new file mode 100644 index 000000000000..906ae937b013 --- /dev/null +++ b/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi | |||
| @@ -0,0 +1,81 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Eukréa Electromatique <denis@eukrea.com> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation; either version 2 | ||
| 7 | * of the License, or (at your option) any later version. | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include "imx35.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Eukrea CPUIMX35"; | ||
| 18 | compatible = "eukrea,cpuimx35", "fsl,imx35"; | ||
| 19 | |||
| 20 | memory { | ||
| 21 | reg = <0x80000000 0x8000000>; /* 128M */ | ||
| 22 | }; | ||
| 23 | }; | ||
| 24 | |||
| 25 | &fec { | ||
| 26 | pinctrl-names = "default"; | ||
| 27 | pinctrl-0 = <&pinctrl_fec>; | ||
| 28 | status = "okay"; | ||
| 29 | }; | ||
| 30 | |||
| 31 | &i2c1 { | ||
| 32 | pinctrl-names = "default"; | ||
| 33 | pinctrl-0 = <&pinctrl_i2c1>; | ||
| 34 | status = "okay"; | ||
| 35 | |||
| 36 | pcf8563@51 { | ||
| 37 | compatible = "nxp,pcf8563"; | ||
| 38 | reg = <0x51>; | ||
| 39 | }; | ||
| 40 | }; | ||
| 41 | |||
| 42 | &iomuxc { | ||
| 43 | imx35-eukrea { | ||
| 44 | pinctrl_fec: fecgrp { | ||
| 45 | fsl,pins = < | ||
| 46 | MX35_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000 | ||
| 47 | MX35_PAD_FEC_RX_CLK__FEC_RX_CLK 0x80000000 | ||
| 48 | MX35_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 | ||
| 49 | MX35_PAD_FEC_COL__FEC_COL 0x80000000 | ||
| 50 | MX35_PAD_FEC_RDATA0__FEC_RDATA_0 0x80000000 | ||
| 51 | MX35_PAD_FEC_TDATA0__FEC_TDATA_0 0x80000000 | ||
| 52 | MX35_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 | ||
| 53 | MX35_PAD_FEC_MDC__FEC_MDC 0x80000000 | ||
| 54 | MX35_PAD_FEC_MDIO__FEC_MDIO 0x80000000 | ||
| 55 | MX35_PAD_FEC_TX_ERR__FEC_TX_ERR 0x80000000 | ||
| 56 | MX35_PAD_FEC_RX_ERR__FEC_RX_ERR 0x80000000 | ||
| 57 | MX35_PAD_FEC_CRS__FEC_CRS 0x80000000 | ||
| 58 | MX35_PAD_FEC_RDATA1__FEC_RDATA_1 0x80000000 | ||
| 59 | MX35_PAD_FEC_TDATA1__FEC_TDATA_1 0x80000000 | ||
| 60 | MX35_PAD_FEC_RDATA2__FEC_RDATA_2 0x80000000 | ||
| 61 | MX35_PAD_FEC_TDATA2__FEC_TDATA_2 0x80000000 | ||
| 62 | MX35_PAD_FEC_RDATA3__FEC_RDATA_3 0x80000000 | ||
| 63 | MX35_PAD_FEC_TDATA3__FEC_TDATA_3 0x80000000 | ||
| 64 | >; | ||
| 65 | }; | ||
| 66 | |||
| 67 | pinctrl_i2c1: i2c1grp { | ||
| 68 | fsl,pins = < | ||
| 69 | MX35_PAD_I2C1_CLK__I2C1_SCL 0x80000000 | ||
| 70 | MX35_PAD_I2C1_DAT__I2C1_SDA 0x80000000 | ||
| 71 | >; | ||
| 72 | }; | ||
| 73 | }; | ||
| 74 | }; | ||
| 75 | |||
| 76 | &nfc { | ||
| 77 | nand-bus-width = <8>; | ||
| 78 | nand-ecc-mode = "hw"; | ||
| 79 | nand-on-flash-bbt; | ||
| 80 | status = "okay"; | ||
| 81 | }; | ||
diff --git a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts new file mode 100644 index 000000000000..1bdec21f4533 --- /dev/null +++ b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts | |||
| @@ -0,0 +1,143 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Eukréa Electromatique <denis@eukrea.com> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation; either version 2 | ||
| 7 | * of the License, or (at your option) any later version. | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | */ | ||
| 13 | |||
| 14 | /dts-v1/; | ||
| 15 | |||
| 16 | #include <dt-bindings/gpio/gpio.h> | ||
| 17 | #include <dt-bindings/input/input.h> | ||
| 18 | #include "imx35-eukrea-cpuimx35.dtsi" | ||
| 19 | |||
| 20 | / { | ||
| 21 | model = "Eukrea CPUIMX35"; | ||
| 22 | compatible = "eukrea,mbimxsd35-baseboard", "eukrea,cpuimx35", "fsl,imx35"; | ||
| 23 | |||
| 24 | gpio_keys { | ||
| 25 | compatible = "gpio-keys"; | ||
| 26 | pinctrl-names = "default"; | ||
| 27 | pinctrl-0 = <&pinctrl_bp1>; | ||
| 28 | |||
| 29 | bp1 { | ||
| 30 | label = "BP1"; | ||
| 31 | gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; | ||
| 32 | linux,code = <BTN_MISC>; | ||
| 33 | gpio-key,wakeup; | ||
| 34 | linux,input-type = <1>; | ||
| 35 | }; | ||
| 36 | }; | ||
| 37 | |||
| 38 | leds { | ||
| 39 | compatible = "gpio-leds"; | ||
| 40 | pinctrl-names = "default"; | ||
| 41 | pinctrl-0 = <&pinctrl_led1>; | ||
| 42 | |||
| 43 | led1 { | ||
| 44 | label = "led1"; | ||
| 45 | gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; | ||
| 46 | linux,default-trigger = "heartbeat"; | ||
| 47 | }; | ||
| 48 | }; | ||
| 49 | }; | ||
| 50 | |||
| 51 | &audmux { | ||
| 52 | pinctrl-names = "default"; | ||
| 53 | pinctrl-0 = <&pinctrl_audmux>; | ||
| 54 | status = "okay"; | ||
| 55 | }; | ||
| 56 | |||
| 57 | &esdhc1 { | ||
| 58 | pinctrl-names = "default"; | ||
| 59 | pinctrl-0 = <&pinctrl_esdhc1>; | ||
| 60 | cd-gpios = <&gpio3 24>; | ||
| 61 | status = "okay"; | ||
| 62 | }; | ||
| 63 | |||
| 64 | &i2c1 { | ||
| 65 | tlv320aic23: codec@1a { | ||
| 66 | compatible = "ti,tlv320aic23"; | ||
| 67 | reg = <0x1a>; | ||
| 68 | }; | ||
| 69 | }; | ||
| 70 | |||
| 71 | &iomuxc { | ||
| 72 | imx35-eukrea { | ||
| 73 | pinctrl_audmux: audmuxgrp { | ||
| 74 | fsl,pins = < | ||
| 75 | MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS 0x80000000 | ||
| 76 | MX35_PAD_STXD4__AUDMUX_AUD4_TXD 0x80000000 | ||
| 77 | MX35_PAD_SRXD4__AUDMUX_AUD4_RXD 0x80000000 | ||
| 78 | MX35_PAD_SCK4__AUDMUX_AUD4_TXC 0x80000000 | ||
| 79 | >; | ||
| 80 | }; | ||
| 81 | |||
| 82 | pinctrl_bp1: bp1grp { | ||
| 83 | fsl,pins = <MX35_PAD_LD19__GPIO3_25 0x80000000>; | ||
| 84 | }; | ||
| 85 | |||
| 86 | pinctrl_esdhc1: esdhc1grp { | ||
| 87 | fsl,pins = < | ||
| 88 | MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000 | ||
| 89 | MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000 | ||
| 90 | MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000 | ||
| 91 | MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000 | ||
| 92 | MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000 | ||
| 93 | MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000 | ||
| 94 | MX35_PAD_LD18__GPIO3_24 0x80000000 /* CD */ | ||
| 95 | >; | ||
| 96 | }; | ||
| 97 | |||
| 98 | pinctrl_led1: led1grp { | ||
| 99 | fsl,pins = <MX35_PAD_LD23__GPIO3_29 0x80000000>; | ||
| 100 | }; | ||
| 101 | |||
| 102 | pinctrl_reg_lcd_3v3: reg-lcd-3v3 { | ||
| 103 | fsl,pins = <MX35_PAD_D3_CLS__GPIO1_4 0x80000000>; | ||
| 104 | }; | ||
| 105 | |||
| 106 | pinctrl_uart1: uart1grp { | ||
| 107 | fsl,pins = < | ||
| 108 | MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5 | ||
| 109 | MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5 | ||
| 110 | MX35_PAD_CTS1__UART1_CTS 0x1c5 | ||
| 111 | MX35_PAD_RTS1__UART1_RTS 0x1c5 | ||
| 112 | >; | ||
| 113 | }; | ||
| 114 | |||
| 115 | pinctrl_uart2: uart2grp { | ||
| 116 | fsl,pins = < | ||
| 117 | MX35_PAD_RXD2__UART2_RXD_MUX 0x1c5 | ||
| 118 | MX35_PAD_TXD2__UART2_TXD_MUX 0x1c5 | ||
| 119 | MX35_PAD_RTS2__UART2_RTS 0x1c5 | ||
| 120 | MX35_PAD_CTS2__UART2_CTS 0x1c5 | ||
| 121 | >; | ||
| 122 | }; | ||
| 123 | }; | ||
| 124 | }; | ||
| 125 | |||
| 126 | &ssi1 { | ||
| 127 | fsl,mode = "i2s-slave"; | ||
| 128 | status = "okay"; | ||
| 129 | }; | ||
| 130 | |||
| 131 | &uart1 { | ||
| 132 | pinctrl-names = "default"; | ||
| 133 | pinctrl-0 = <&pinctrl_uart1>; | ||
| 134 | fsl,uart-has-rtscts; | ||
| 135 | status = "okay"; | ||
| 136 | }; | ||
| 137 | |||
| 138 | &uart2 { | ||
| 139 | pinctrl-names = "default"; | ||
| 140 | pinctrl-0 = <&pinctrl_uart2>; | ||
| 141 | fsl,uart-has-rtscts; | ||
| 142 | status = "okay"; | ||
| 143 | }; | ||
diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi new file mode 100644 index 000000000000..88b218f8f810 --- /dev/null +++ b/arch/arm/boot/dts/imx35.dtsi | |||
| @@ -0,0 +1,359 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2012 Steffen Trumtrar, Pengutronix | ||
| 3 | * | ||
| 4 | * based on imx27.dtsi | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify it under | ||
| 7 | * the terms of the GNU General Public License version 2 as published by the | ||
| 8 | * Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include "skeleton.dtsi" | ||
| 12 | #include "imx35-pinfunc.h" | ||
| 13 | |||
| 14 | / { | ||
| 15 | aliases { | ||
| 16 | gpio0 = &gpio1; | ||
| 17 | gpio1 = &gpio2; | ||
| 18 | gpio2 = &gpio3; | ||
| 19 | serial0 = &uart1; | ||
| 20 | serial1 = &uart2; | ||
| 21 | serial2 = &uart3; | ||
| 22 | spi0 = &spi1; | ||
| 23 | spi1 = &spi2; | ||
| 24 | }; | ||
| 25 | |||
| 26 | cpus { | ||
| 27 | #address-cells = <0>; | ||
| 28 | #size-cells = <0>; | ||
| 29 | |||
| 30 | cpu { | ||
| 31 | compatible = "arm,arm1136"; | ||
| 32 | device_type = "cpu"; | ||
| 33 | }; | ||
| 34 | }; | ||
| 35 | |||
| 36 | avic: avic-interrupt-controller@68000000 { | ||
| 37 | compatible = "fsl,imx35-avic", "fsl,avic"; | ||
| 38 | interrupt-controller; | ||
| 39 | #interrupt-cells = <1>; | ||
| 40 | reg = <0x68000000 0x10000000>; | ||
| 41 | }; | ||
| 42 | |||
| 43 | soc { | ||
| 44 | #address-cells = <1>; | ||
| 45 | #size-cells = <1>; | ||
| 46 | compatible = "simple-bus"; | ||
| 47 | interrupt-parent = <&avic>; | ||
| 48 | ranges; | ||
| 49 | |||
| 50 | L2: l2-cache@30000000 { | ||
| 51 | compatible = "arm,l210-cache"; | ||
| 52 | reg = <0x30000000 0x1000>; | ||
| 53 | cache-unified; | ||
| 54 | cache-level = <2>; | ||
| 55 | }; | ||
| 56 | |||
| 57 | aips1: aips@43f00000 { | ||
| 58 | compatible = "fsl,aips", "simple-bus"; | ||
| 59 | #address-cells = <1>; | ||
| 60 | #size-cells = <1>; | ||
| 61 | reg = <0x43f00000 0x100000>; | ||
| 62 | ranges; | ||
| 63 | |||
| 64 | i2c1: i2c@43f80000 { | ||
| 65 | #address-cells = <1>; | ||
| 66 | #size-cells = <0>; | ||
| 67 | compatible = "fsl,imx35-i2c", "fsl,imx1-i2c"; | ||
| 68 | reg = <0x43f80000 0x4000>; | ||
| 69 | clocks = <&clks 51>; | ||
| 70 | clock-names = "ipg_per"; | ||
| 71 | interrupts = <10>; | ||
| 72 | status = "disabled"; | ||
| 73 | }; | ||
| 74 | |||
| 75 | i2c3: i2c@43f84000 { | ||
| 76 | #address-cells = <1>; | ||
| 77 | #size-cells = <0>; | ||
| 78 | compatible = "fsl,imx35-i2c", "fsl,imx1-i2c"; | ||
| 79 | reg = <0x43f84000 0x4000>; | ||
| 80 | clocks = <&clks 53>; | ||
| 81 | clock-names = "ipg_per"; | ||
| 82 | interrupts = <3>; | ||
| 83 | status = "disabled"; | ||
| 84 | }; | ||
| 85 | |||
| 86 | uart1: serial@43f90000 { | ||
| 87 | compatible = "fsl,imx35-uart", "fsl,imx21-uart"; | ||
| 88 | reg = <0x43f90000 0x4000>; | ||
| 89 | clocks = <&clks 9>, <&clks 70>; | ||
| 90 | clock-names = "ipg", "per"; | ||
| 91 | interrupts = <45>; | ||
| 92 | status = "disabled"; | ||
| 93 | }; | ||
| 94 | |||
| 95 | uart2: serial@43f94000 { | ||
| 96 | compatible = "fsl,imx35-uart", "fsl,imx21-uart"; | ||
| 97 | reg = <0x43f94000 0x4000>; | ||
| 98 | clocks = <&clks 9>, <&clks 71>; | ||
| 99 | clock-names = "ipg", "per"; | ||
| 100 | interrupts = <32>; | ||
| 101 | status = "disabled"; | ||
| 102 | }; | ||
| 103 | |||
| 104 | i2c2: i2c@43f98000 { | ||
| 105 | #address-cells = <1>; | ||
| 106 | #size-cells = <0>; | ||
| 107 | compatible = "fsl,imx35-i2c", "fsl,imx1-i2c"; | ||
| 108 | reg = <0x43f98000 0x4000>; | ||
| 109 | clocks = <&clks 52>; | ||
| 110 | clock-names = "ipg_per"; | ||
| 111 | interrupts = <4>; | ||
| 112 | status = "disabled"; | ||
| 113 | }; | ||
| 114 | |||
| 115 | ssi1: ssi@43fa0000 { | ||
| 116 | compatible = "fsl,imx35-ssi", "fsl,imx21-ssi"; | ||
| 117 | reg = <0x43fa0000 0x4000>; | ||
| 118 | interrupts = <11>; | ||
| 119 | clocks = <&clks 68>; | ||
| 120 | dmas = <&sdma 28 0 0>, | ||
| 121 | <&sdma 29 0 0>; | ||
| 122 | dma-names = "rx", "tx"; | ||
| 123 | fsl,fifo-depth = <15>; | ||
| 124 | status = "disabled"; | ||
| 125 | }; | ||
| 126 | |||
| 127 | spi1: cspi@43fa4000 { | ||
| 128 | #address-cells = <1>; | ||
| 129 | #size-cells = <0>; | ||
| 130 | compatible = "fsl,imx35-cspi"; | ||
| 131 | reg = <0x43fa4000 0x4000>; | ||
| 132 | clocks = <&clks 35 &clks 35>; | ||
| 133 | clock-names = "ipg", "per"; | ||
| 134 | interrupts = <14>; | ||
| 135 | status = "disabled"; | ||
| 136 | }; | ||
| 137 | |||
| 138 | iomuxc: iomuxc@43fac000 { | ||
| 139 | compatible = "fsl,imx35-iomuxc"; | ||
| 140 | reg = <0x43fac000 0x4000>; | ||
| 141 | }; | ||
| 142 | }; | ||
| 143 | |||
| 144 | spba: spba-bus@50000000 { | ||
| 145 | compatible = "fsl,spba-bus", "simple-bus"; | ||
| 146 | #address-cells = <1>; | ||
| 147 | #size-cells = <1>; | ||
| 148 | reg = <0x50000000 0x100000>; | ||
| 149 | ranges; | ||
| 150 | |||
| 151 | uart3: serial@5000c000 { | ||
| 152 | compatible = "fsl,imx35-uart", "fsl,imx21-uart"; | ||
| 153 | reg = <0x5000c000 0x4000>; | ||
| 154 | clocks = <&clks 9>, <&clks 72>; | ||
| 155 | clock-names = "ipg", "per"; | ||
| 156 | interrupts = <18>; | ||
| 157 | status = "disabled"; | ||
| 158 | }; | ||
| 159 | |||
| 160 | spi2: cspi@50010000 { | ||
| 161 | #address-cells = <1>; | ||
| 162 | #size-cells = <0>; | ||
| 163 | compatible = "fsl,imx35-cspi"; | ||
| 164 | reg = <0x50010000 0x4000>; | ||
| 165 | interrupts = <13>; | ||
| 166 | clocks = <&clks 36 &clks 36>; | ||
| 167 | clock-names = "ipg", "per"; | ||
| 168 | status = "disabled"; | ||
| 169 | }; | ||
| 170 | |||
| 171 | fec: fec@50038000 { | ||
| 172 | compatible = "fsl,imx35-fec", "fsl,imx27-fec"; | ||
| 173 | reg = <0x50038000 0x4000>; | ||
| 174 | clocks = <&clks 46>, <&clks 8>; | ||
| 175 | clock-names = "ipg", "ahb"; | ||
| 176 | interrupts = <57>; | ||
| 177 | status = "disabled"; | ||
| 178 | }; | ||
| 179 | }; | ||
| 180 | |||
| 181 | aips2: aips@53f00000 { | ||
| 182 | compatible = "fsl,aips", "simple-bus"; | ||
| 183 | #address-cells = <1>; | ||
| 184 | #size-cells = <1>; | ||
| 185 | reg = <0x53f00000 0x100000>; | ||
| 186 | ranges; | ||
| 187 | |||
| 188 | clks: ccm@53f80000 { | ||
| 189 | compatible = "fsl,imx35-ccm"; | ||
| 190 | reg = <0x53f80000 0x4000>; | ||
| 191 | interrupts = <31>; | ||
| 192 | #clock-cells = <1>; | ||
| 193 | }; | ||
| 194 | |||
| 195 | gpio3: gpio@53fa4000 { | ||
| 196 | compatible = "fsl,imx35-gpio", "fsl,imx31-gpio"; | ||
| 197 | reg = <0x53fa4000 0x4000>; | ||
| 198 | interrupts = <56>; | ||
| 199 | gpio-controller; | ||
| 200 | #gpio-cells = <2>; | ||
| 201 | interrupt-controller; | ||
| 202 | #interrupt-cells = <2>; | ||
| 203 | }; | ||
| 204 | |||
| 205 | esdhc1: esdhc@53fb4000 { | ||
| 206 | compatible = "fsl,imx35-esdhc"; | ||
| 207 | reg = <0x53fb4000 0x4000>; | ||
| 208 | interrupts = <7>; | ||
| 209 | clocks = <&clks 9>, <&clks 8>, <&clks 43>; | ||
| 210 | clock-names = "ipg", "ahb", "per"; | ||
| 211 | status = "disabled"; | ||
| 212 | }; | ||
| 213 | |||
| 214 | esdhc2: esdhc@53fb8000 { | ||
| 215 | compatible = "fsl,imx35-esdhc"; | ||
| 216 | reg = <0x53fb8000 0x4000>; | ||
| 217 | interrupts = <8>; | ||
| 218 | clocks = <&clks 9>, <&clks 8>, <&clks 44>; | ||
| 219 | clock-names = "ipg", "ahb", "per"; | ||
| 220 | status = "disabled"; | ||
| 221 | }; | ||
| 222 | |||
| 223 | esdhc3: esdhc@53fbc000 { | ||
| 224 | compatible = "fsl,imx35-esdhc"; | ||
| 225 | reg = <0x53fbc000 0x4000>; | ||
| 226 | interrupts = <9>; | ||
| 227 | clocks = <&clks 9>, <&clks 8>, <&clks 45>; | ||
| 228 | clock-names = "ipg", "ahb", "per"; | ||
| 229 | status = "disabled"; | ||
| 230 | }; | ||
| 231 | |||
| 232 | audmux: audmux@53fc4000 { | ||
| 233 | compatible = "fsl,imx35-audmux", "fsl,imx31-audmux"; | ||
| 234 | reg = <0x53fc4000 0x4000>; | ||
| 235 | status = "disabled"; | ||
| 236 | }; | ||
| 237 | |||
| 238 | gpio1: gpio@53fcc000 { | ||
| 239 | compatible = "fsl,imx35-gpio", "fsl,imx31-gpio"; | ||
| 240 | reg = <0x53fcc000 0x4000>; | ||
| 241 | interrupts = <52>; | ||
| 242 | gpio-controller; | ||
| 243 | #gpio-cells = <2>; | ||
| 244 | interrupt-controller; | ||
| 245 | #interrupt-cells = <2>; | ||
| 246 | }; | ||
| 247 | |||
| 248 | gpio2: gpio@53fd0000 { | ||
| 249 | compatible = "fsl,imx35-gpio", "fsl,imx31-gpio"; | ||
| 250 | reg = <0x53fd0000 0x4000>; | ||
| 251 | interrupts = <51>; | ||
| 252 | gpio-controller; | ||
| 253 | #gpio-cells = <2>; | ||
| 254 | interrupt-controller; | ||
| 255 | #interrupt-cells = <2>; | ||
| 256 | }; | ||
| 257 | |||
| 258 | sdma: sdma@53fd4000 { | ||
| 259 | compatible = "fsl,imx35-sdma"; | ||
| 260 | reg = <0x53fd4000 0x4000>; | ||
| 261 | clocks = <&clks 9>, <&clks 65>; | ||
| 262 | clock-names = "ipg", "ahb"; | ||
| 263 | #dma-cells = <3>; | ||
| 264 | interrupts = <34>; | ||
| 265 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx35.bin"; | ||
| 266 | }; | ||
| 267 | |||
| 268 | wdog: wdog@53fdc000 { | ||
| 269 | compatible = "fsl,imx35-wdt", "fsl,imx21-wdt"; | ||
| 270 | reg = <0x53fdc000 0x4000>; | ||
| 271 | clocks = <&clks 74>; | ||
| 272 | clock-names = ""; | ||
| 273 | interrupts = <55>; | ||
| 274 | }; | ||
| 275 | |||
| 276 | can1: can@53fe4000 { | ||
| 277 | compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan"; | ||
| 278 | reg = <0x53fe4000 0x1000>; | ||
| 279 | clocks = <&clks 33>; | ||
| 280 | clock-names = "ipg"; | ||
| 281 | interrupts = <43>; | ||
| 282 | status = "disabled"; | ||
| 283 | }; | ||
| 284 | |||
| 285 | can2: can@53fe8000 { | ||
| 286 | compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan"; | ||
| 287 | reg = <0x53fe8000 0x1000>; | ||
| 288 | clocks = <&clks 34>; | ||
| 289 | clock-names = "ipg"; | ||
| 290 | interrupts = <44>; | ||
| 291 | status = "disabled"; | ||
| 292 | }; | ||
| 293 | |||
| 294 | usbotg: usb@53ff4000 { | ||
| 295 | compatible = "fsl,imx35-usb", "fsl,imx27-usb"; | ||
| 296 | reg = <0x53ff4000 0x0200>; | ||
| 297 | interrupts = <37>; | ||
| 298 | clocks = <&clks 9>, <&clks 73>, <&clks 28>; | ||
| 299 | clock-names = "ipg", "ahb", "per"; | ||
| 300 | fsl,usbmisc = <&usbmisc 0>; | ||
| 301 | status = "disabled"; | ||
| 302 | }; | ||
| 303 | |||
| 304 | usbhost1: usb@53ff4400 { | ||
| 305 | compatible = "fsl,imx35-usb", "fsl,imx27-usb"; | ||
| 306 | reg = <0x53ff4400 0x0200>; | ||
| 307 | interrupts = <35>; | ||
| 308 | clocks = <&clks 9>, <&clks 73>, <&clks 28>; | ||
| 309 | clock-names = "ipg", "ahb", "per"; | ||
| 310 | fsl,usbmisc = <&usbmisc 1>; | ||
| 311 | status = "disabled"; | ||
| 312 | }; | ||
| 313 | |||
| 314 | usbmisc: usbmisc@53ff4600 { | ||
| 315 | #index-cells = <1>; | ||
| 316 | compatible = "fsl,imx35-usbmisc"; | ||
| 317 | clocks = <&clks 9>, <&clks 73>, <&clks 28>; | ||
| 318 | clock-names = "ipg", "ahb", "per"; | ||
| 319 | reg = <0x53ff4600 0x00f>; | ||
| 320 | }; | ||
| 321 | }; | ||
| 322 | |||
| 323 | emi@80000000 { /* External Memory Interface */ | ||
| 324 | compatible = "fsl,emi", "simple-bus"; | ||
| 325 | #address-cells = <1>; | ||
| 326 | #size-cells = <1>; | ||
| 327 | reg = <0x80000000 0x40000000>; | ||
| 328 | ranges; | ||
| 329 | |||
| 330 | nfc: nand@bb000000 { | ||
| 331 | #address-cells = <1>; | ||
| 332 | #size-cells = <1>; | ||
| 333 | compatible = "fsl,imx35-nand", "fsl,imx25-nand"; | ||
| 334 | reg = <0xbb000000 0x2000>; | ||
| 335 | clocks = <&clks 29>; | ||
| 336 | clock-names = ""; | ||
| 337 | interrupts = <33>; | ||
| 338 | status = "disabled"; | ||
| 339 | }; | ||
| 340 | |||
| 341 | weim: weim@b8002000 { | ||
| 342 | #address-cells = <2>; | ||
| 343 | #size-cells = <1>; | ||
| 344 | clocks = <&clks 0>; | ||
| 345 | compatible = "fsl,imx35-weim", "fsl,imx27-weim"; | ||
| 346 | reg = <0xb8002000 0x1000>; | ||
| 347 | ranges = < | ||
| 348 | 0 0 0xa0000000 0x8000000 | ||
| 349 | 1 0 0xa8000000 0x8000000 | ||
| 350 | 2 0 0xb0000000 0x2000000 | ||
| 351 | 3 0 0xb2000000 0x2000000 | ||
| 352 | 4 0 0xb4000000 0x2000000 | ||
| 353 | 5 0 0xb6000000 0x2000000 | ||
| 354 | >; | ||
| 355 | status = "disabled"; | ||
| 356 | }; | ||
| 357 | }; | ||
| 358 | }; | ||
| 359 | }; | ||
diff --git a/arch/arm/boot/dts/imx50-evk.dts b/arch/arm/boot/dts/imx50-evk.dts new file mode 100644 index 000000000000..1b22512c91bd --- /dev/null +++ b/arch/arm/boot/dts/imx50-evk.dts | |||
| @@ -0,0 +1,119 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Greg Ungerer <gerg@uclinux.org> | ||
| 3 | * Copyright 2011 Freescale Semiconductor, Inc. | ||
| 4 | * Copyright 2011 Linaro Ltd. | ||
| 5 | * | ||
| 6 | * The code contained herein is licensed under the GNU General Public | ||
| 7 | * License. You may obtain a copy of the GNU General Public License | ||
| 8 | * Version 2 or later at the following locations: | ||
| 9 | * | ||
| 10 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 11 | * http://www.gnu.org/copyleft/gpl.html | ||
| 12 | */ | ||
| 13 | |||
| 14 | /dts-v1/; | ||
| 15 | #include "imx50.dtsi" | ||
| 16 | |||
| 17 | / { | ||
| 18 | model = "Freescale i.MX50 Evaluation Kit"; | ||
| 19 | compatible = "fsl,imx50-evk", "fsl,imx50"; | ||
| 20 | |||
| 21 | memory { | ||
| 22 | reg = <0x70000000 0x80000000>; | ||
| 23 | }; | ||
| 24 | }; | ||
| 25 | |||
| 26 | &cspi { | ||
| 27 | pinctrl-names = "default"; | ||
| 28 | pinctrl-0 = <&pinctrl_cspi>; | ||
| 29 | fsl,spi-num-chipselects = <2>; | ||
| 30 | cs-gpios = <&gpio4 11 0>, <&gpio4 13 0>; | ||
| 31 | status = "okay"; | ||
| 32 | |||
| 33 | flash: m25p32@1 { | ||
| 34 | #address-cells = <1>; | ||
| 35 | #size-cells = <1>; | ||
| 36 | compatible = "m25p32", "m25p80"; | ||
| 37 | spi-max-frequency = <25000000>; | ||
| 38 | reg = <1>; | ||
| 39 | |||
| 40 | partition@0 { | ||
| 41 | label = "bootloader"; | ||
| 42 | reg = <0x0 0x100000>; | ||
| 43 | read-only; | ||
| 44 | }; | ||
| 45 | |||
| 46 | partition@100000 { | ||
| 47 | label = "kernel"; | ||
| 48 | reg = <0x100000 0x300000>; | ||
| 49 | }; | ||
| 50 | }; | ||
| 51 | }; | ||
| 52 | |||
| 53 | &fec { | ||
| 54 | pinctrl-names = "default"; | ||
| 55 | pinctrl-0 = <&pinctrl_fec>; | ||
| 56 | phy-mode = "rmii"; | ||
| 57 | phy-reset-gpios = <&gpio4 12 0>; | ||
| 58 | status = "okay"; | ||
| 59 | }; | ||
| 60 | |||
| 61 | &iomuxc { | ||
| 62 | imx50-evk { | ||
| 63 | pinctrl_cspi: cspigrp { | ||
| 64 | fsl,pins = < | ||
| 65 | MX50_PAD_CSPI_SCLK__CSPI_SCLK 0x00 | ||
| 66 | MX50_PAD_CSPI_MISO__CSPI_MISO 0x00 | ||
| 67 | MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x00 | ||
| 68 | MX50_PAD_CSPI_SS0__GPIO4_11 0xc4 | ||
| 69 | MX50_PAD_ECSPI1_MOSI__CSPI_SS1 0xf4 | ||
| 70 | >; | ||
| 71 | }; | ||
| 72 | |||
| 73 | pinctrl_fec: fecgrp { | ||
| 74 | fsl,pins = < | ||
| 75 | MX50_PAD_SSI_RXFS__FEC_MDC 0x80 | ||
| 76 | MX50_PAD_SSI_RXC__FEC_MDIO 0x80 | ||
| 77 | MX50_PAD_DISP_D0__FEC_TX_CLK 0x80 | ||
| 78 | MX50_PAD_DISP_D1__FEC_RX_ERR 0x80 | ||
| 79 | MX50_PAD_DISP_D2__FEC_RX_DV 0x80 | ||
| 80 | MX50_PAD_DISP_D3__FEC_RDATA_1 0x80 | ||
| 81 | MX50_PAD_DISP_D4__FEC_RDATA_0 0x80 | ||
| 82 | MX50_PAD_DISP_D5__FEC_TX_EN 0x80 | ||
| 83 | MX50_PAD_DISP_D6__FEC_TDATA_1 0x80 | ||
| 84 | MX50_PAD_DISP_D7__FEC_TDATA_0 0x80 | ||
| 85 | >; | ||
| 86 | }; | ||
| 87 | |||
| 88 | pinctrl_uart1: uart1grp { | ||
| 89 | fsl,pins = < | ||
| 90 | MX50_PAD_UART1_TXD__UART1_TXD_MUX 0x1e4 | ||
| 91 | MX50_PAD_UART1_RXD__UART1_RXD_MUX 0x1e4 | ||
| 92 | MX50_PAD_UART1_RTS__UART1_RTS 0x1e4 | ||
| 93 | MX50_PAD_UART1_CTS__UART1_CTS 0x1e4 | ||
| 94 | >; | ||
| 95 | }; | ||
| 96 | }; | ||
| 97 | }; | ||
| 98 | |||
| 99 | &uart1 { | ||
| 100 | pinctrl-names = "default"; | ||
| 101 | pinctrl-0 = <&pinctrl_uart1>; | ||
| 102 | status = "okay"; | ||
| 103 | }; | ||
| 104 | |||
| 105 | &usbh1 { | ||
| 106 | status = "okay"; | ||
| 107 | }; | ||
| 108 | |||
| 109 | &usbh2 { | ||
| 110 | status = "okay"; | ||
| 111 | }; | ||
| 112 | |||
| 113 | &usbh3 { | ||
| 114 | status = "okay"; | ||
| 115 | }; | ||
| 116 | |||
| 117 | &usbotg { | ||
| 118 | status = "okay"; | ||
| 119 | }; | ||
diff --git a/arch/arm/boot/dts/imx50-pinfunc.h b/arch/arm/boot/dts/imx50-pinfunc.h new file mode 100644 index 000000000000..97e6e7f4ebdd --- /dev/null +++ b/arch/arm/boot/dts/imx50-pinfunc.h | |||
| @@ -0,0 +1,923 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Greg Ungerer <gerg@uclinux.org> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __DTS_IMX50_PINFUNC_H | ||
| 11 | #define __DTS_IMX50_PINFUNC_H | ||
| 12 | |||
| 13 | /* | ||
| 14 | * The pin function ID is a tuple of | ||
| 15 | * <mux_reg conf_reg input_reg mux_mode input_val> | ||
| 16 | */ | ||
| 17 | #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0 | ||
| 18 | #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0 | ||
| 19 | #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0 | ||
| 20 | #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0 | ||
| 21 | #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0 | ||
| 22 | #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0 | ||
| 23 | #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0 | ||
| 24 | #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0 | ||
| 25 | #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0 | ||
| 26 | #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0 | ||
| 27 | #define MX50_PAD_KEY_COL1__KPP_COL_1 0x028 0x2d4 0x000 0x0 0x0 | ||
| 28 | #define MX50_PAD_KEY_COL1__GPIO4_2 0x028 0x2d4 0x000 0x1 0x0 | ||
| 29 | #define MX50_PAD_KEY_COL1__EIM_NANDF_CEN_0 0x028 0x2d4 0x000 0x2 0x0 | ||
| 30 | #define MX50_PAD_KEY_COL1__CTI_TRIGOUT_ACK6 0x028 0x2d4 0x000 0x6 0x0 | ||
| 31 | #define MX50_PAD_KEY_COL1__USBPHY1_RXACTIVE 0x028 0x2d4 0x000 0x7 0x0 | ||
| 32 | #define MX50_PAD_KEY_ROW1__KPP_ROW_1 0x02c 0x2d8 0x000 0x0 0x0 | ||
| 33 | #define MX50_PAD_KEY_ROW1__GPIO4_3 0x02c 0x2d8 0x000 0x1 0x0 | ||
| 34 | #define MX50_PAD_KEY_ROW1__EIM_NANDF_CEN_1 0x02c 0x2d8 0x000 0x2 0x0 | ||
| 35 | #define MX50_PAD_KEY_ROW1__CTI_TRIGOUT_ACK7 0x02c 0x2d8 0x000 0x6 0x0 | ||
| 36 | #define MX50_PAD_KEY_ROW1__USBPHY1_RXERROR 0x02c 0x2d8 0x000 0x7 0x0 | ||
| 37 | #define MX50_PAD_KEY_COL2__KPP_COL_1 0x030 0x2dc 0x000 0x0 0x0 | ||
| 38 | #define MX50_PAD_KEY_COL2__GPIO4_4 0x030 0x2dc 0x000 0x1 0x0 | ||
| 39 | #define MX50_PAD_KEY_COL2__EIM_NANDF_CEN_2 0x030 0x2dc 0x000 0x2 0x0 | ||
| 40 | #define MX50_PAD_KEY_COL2__CTI_TRIGOUT6 0x030 0x2dc 0x000 0x6 0x0 | ||
| 41 | #define MX50_PAD_KEY_COL2__USBPHY1_SIECLOCK 0x030 0x2dc 0x000 0x7 0x0 | ||
| 42 | #define MX50_PAD_KEY_ROW2__KPP_ROW_2 0x034 0x2e0 0x000 0x0 0x0 | ||
| 43 | #define MX50_PAD_KEY_ROW2__GPIO4_5 0x034 0x2e0 0x000 0x1 0x0 | ||
| 44 | #define MX50_PAD_KEY_ROW2__EIM_NANDF_CEN_3 0x034 0x2e0 0x000 0x2 0x0 | ||
| 45 | #define MX50_PAD_KEY_ROW2__CTI_TRIGOUT7 0x034 0x2e0 0x000 0x6 0x0 | ||
| 46 | #define MX50_PAD_KEY_ROW2__USBPHY1_LINESTATE_0 0x034 0x2e0 0x000 0x7 0x0 | ||
| 47 | #define MX50_PAD_KEY_COL3__KPP_COL_2 0x038 0x2e4 0x000 0x0 0x0 | ||
| 48 | #define MX50_PAD_KEY_COL3__GPIO4_6 0x038 0x2e4 0x000 0x1 0x0 | ||
| 49 | #define MX50_PAD_KEY_COL3__EIM_NANDF_READY0 0x038 0x2e4 0x7b4 0x2 0x0 | ||
| 50 | #define MX50_PAD_KEY_COL3__SDMA_EXT_EVENT_0 0x038 0x2e4 0x7b8 0x6 0x0 | ||
| 51 | #define MX50_PAD_KEY_COL3__USBPHY1_LINESTATE_1 0x038 0x2e4 0x000 0x7 0x0 | ||
| 52 | #define MX50_PAD_KEY_ROW3__KPP_ROW_3 0x03c 0x2e8 0x000 0x0 0x0 | ||
| 53 | #define MX50_PAD_KEY_ROW3__GPIO4_7 0x03c 0x2e8 0x000 0x1 0x0 | ||
| 54 | #define MX50_PAD_KEY_ROW3__EIM_NANDF_DQS 0x03c 0x2e8 0x7b0 0x2 0x0 | ||
| 55 | #define MX50_PAD_KEY_ROW3__SDMA_EXT_EVENT_1 0x03c 0x2e8 0x7bc 0x6 0x0 | ||
| 56 | #define MX50_PAD_KEY_ROW3__USBPHY1_VBUSVALID 0x03c 0x2e8 0x000 0x7 0x0 | ||
| 57 | #define MX50_PAD_I2C1_SCL__I2C1_SCL 0x040 0x2ec 0x000 0x0 0x0 | ||
| 58 | #define MX50_PAD_I2C1_SCL__GPIO6_18 0x040 0x2ec 0x000 0x1 0x0 | ||
| 59 | #define MX50_PAD_I2C1_SCL__UART2_TXD_MUX 0x040 0x2ec 0x7cc 0x2 0x0 | ||
| 60 | #define MX50_PAD_I2C1_SDA__I2C1_SDA 0x044 0x2f0 0x000 0x0 0x0 | ||
| 61 | #define MX50_PAD_I2C1_SDA__GPIO6_19 0x044 0x2f0 0x000 0x1 0x0 | ||
| 62 | #define MX50_PAD_I2C1_SDA__UART2_RXD_MUX 0x044 0x2f0 0x7cc 0x2 0x1 | ||
| 63 | #define MX50_PAD_I2C2_SCL__I2C2_SCL 0x048 0x2f4 0x000 0x0 0x0 | ||
| 64 | #define MX50_PAD_I2C2_SCL__GPIO6_20 0x048 0x2f4 0x000 0x1 0x0 | ||
| 65 | #define MX50_PAD_I2C2_SCL__UART2_CTS 0x048 0x2f4 0x000 0x2 0x0 | ||
| 66 | #define MX50_PAD_I2C2_SDA__I2C2_SDA 0x04c 0x2f8 0x000 0x0 0x0 | ||
| 67 | #define MX50_PAD_I2C2_SDA__GPIO6_21 0x04c 0x2f8 0x000 0x1 0x0 | ||
| 68 | #define MX50_PAD_I2C2_SDA__UART2_RTS 0x04c 0x2f8 0x7c8 0x2 0x1 | ||
| 69 | #define MX50_PAD_I2C3_SCL__I2C3_SCL 0x050 0x2fc 0x000 0x0 0x0 | ||
| 70 | #define MX50_PAD_I2C3_SCL__GPIO6_22 0x050 0x2fc 0x000 0x1 0x0 | ||
| 71 | #define MX50_PAD_I2C3_SCL__FEC_MDC 0x050 0x2fc 0x000 0x2 0x0 | ||
| 72 | #define MX50_PAD_I2C3_SCL__GPC_PMIC_RDY 0x050 0x2fc 0x000 0x3 0x0 | ||
| 73 | #define MX50_PAD_I2C3_SCL__GPT_CAPIN1 0x050 0x2fc 0x000 0x5 0x0 | ||
| 74 | #define MX50_PAD_I2C3_SCL__OBSERVE_MUX_OBSRV_INT_OUT0 0x050 0x2fc 0x000 0x6 0x0 | ||
| 75 | #define MX50_PAD_I2C3_SCL__USBOH1_USBOTG_OC 0x050 0x2fc 0x7e8 0x7 0x0 | ||
| 76 | #define MX50_PAD_I2C3_SDA__I2C3_SDA 0x054 0x300 0x000 0x0 0x0 | ||
| 77 | #define MX50_PAD_I2C3_SDA__GPIO6_23 0x054 0x300 0x000 0x1 0x0 | ||
| 78 | #define MX50_PAD_I2C3_SDA__FEC_MDIO 0x054 0x300 0x774 0x2 0x0 | ||
| 79 | #define MX50_PAD_I2C3_SDA__TZIC_PWRFAIL_INT 0x054 0x300 0x000 0x3 0x0 | ||
| 80 | #define MX50_PAD_I2C3_SDA__SRTC_ALARM_DEB 0x054 0x300 0x000 0x4 0x0 | ||
| 81 | #define MX50_PAD_I2C3_SDA__GPT_CAPIN2 0x054 0x300 0x000 0x5 0x0 | ||
| 82 | #define MX50_PAD_I2C3_SDA__OBSERVE_MUX_OBSRV_INT_OUT1 0x054 0x300 0x000 0x6 0x0 | ||
| 83 | #define MX50_PAD_I2C3_SDA__USBOH1_USBOTG_PWR 0x054 0x300 0x000 0x7 0x0 | ||
| 84 | #define MX50_PAD_PWM1__PWM1_PWMO 0x058 0x304 0x000 0x0 0x0 | ||
| 85 | #define MX50_PAD_PWM1__GPIO6_24 0x058 0x304 0x000 0x1 0x0 | ||
| 86 | #define MX50_PAD_PWM1__USBOH1_USBOTG_OC 0x058 0x304 0x7e8 0x2 0x1 | ||
| 87 | #define MX50_PAD_PWM1__GPT_CMPOUT1 0x058 0x304 0x000 0x5 0x0 | ||
| 88 | #define MX50_PAD_PWM1__OBSERVE_MUX_OBSRV_INT_OUT2 0x058 0x304 0x000 0x6 0x0 | ||
| 89 | #define MX50_PAD_PWM1__SJC_FAIL 0x058 0x304 0x000 0x7 0x0 | ||
| 90 | #define MX50_PAD_PWM2__PWM2_PWMO 0x05c 0x308 0x000 0x0 0x0 | ||
| 91 | #define MX50_PAD_PWM2__GPIO6_25 0x05c 0x308 0x000 0x1 0x0 | ||
| 92 | #define MX50_PAD_PWM2__USBOH1_USBOTG_PWR 0x05c 0x308 0x000 0x2 0x0 | ||
| 93 | #define MX50_PAD_PWM2__GPT_CMPOUT2 0x05c 0x308 0x000 0x5 0x0 | ||
| 94 | #define MX50_PAD_PWM2__OBSERVE_MUX_OBSRV_INT_OUT3 0x05c 0x308 0x000 0x6 0x0 | ||
| 95 | #define MX50_PAD_PWM2__SRC_ANY_PU_RST 0x05c 0x308 0x000 0x7 0x0 | ||
| 96 | #define MX50_PAD_OWIRE__OWIRE_LINE 0x060 0x30c 0x000 0x0 0x0 | ||
| 97 | #define MX50_PAD_OWIRE__GPIO6_26 0x060 0x30c 0x000 0x1 0x0 | ||
| 98 | #define MX50_PAD_OWIRE__USBOH1_USBH1_OC 0x060 0x30c 0x000 0x2 0x0 | ||
| 99 | #define MX50_PAD_OWIRE__CCM_SSI_EXT1_CLK 0x060 0x30c 0x000 0x3 0x0 | ||
| 100 | #define MX50_PAD_OWIRE__EPDC_PWRIRQ 0x060 0x30c 0x000 0x4 0x0 | ||
| 101 | #define MX50_PAD_OWIRE__GPT_CMPOUT3 0x060 0x30c 0x000 0x5 0x0 | ||
| 102 | #define MX50_PAD_OWIRE__OBSERVE_MUX_OBSRV_INT_OUT4 0x060 0x30c 0x000 0x6 0x0 | ||
| 103 | #define MX50_PAD_OWIRE__SJC_JTAG_ACT 0x060 0x30c 0x000 0x7 0x0 | ||
| 104 | #define MX50_PAD_EPITO__EPIT1_EPITO 0x064 0x310 0x000 0x0 0x0 | ||
| 105 | #define MX50_PAD_EPITO__GPIO6_27 0x064 0x310 0x000 0x1 0x0 | ||
| 106 | #define MX50_PAD_EPITO__USBOH1_USBH1_PWR 0x064 0x310 0x000 0x2 0x0 | ||
| 107 | #define MX50_PAD_EPITO__CCM_SSI_EXT2_CLK 0x064 0x310 0x000 0x3 0x0 | ||
| 108 | #define MX50_PAD_EPITO__DPLLIP1_TOG_EN 0x064 0x310 0x000 0x4 0x0 | ||
| 109 | #define MX50_PAD_EPITO__GPT_CLK_IN 0x064 0x310 0x000 0x5 0x0 | ||
| 110 | #define MX50_PAD_EPITO__PMU_IRQ_B 0x064 0x310 0x000 0x6 0x0 | ||
| 111 | #define MX50_PAD_EPITO__SJC_DE_B 0x064 0x310 0x000 0x7 0x0 | ||
| 112 | #define MX50_PAD_WDOG__WDOG1_WDOG_B 0x068 0x314 0x000 0x0 0x0 | ||
| 113 | #define MX50_PAD_WDOG__GPIO6_28 0x068 0x314 0x000 0x1 0x0 | ||
| 114 | #define MX50_PAD_WDOG__WDOG1_WDOG_RST_B_DEB 0x068 0x314 0x000 0x2 0x0 | ||
| 115 | #define MX50_PAD_WDOG__CCM_XTAL32K 0x068 0x314 0x000 0x6 0x0 | ||
| 116 | #define MX50_PAD_WDOG__SJC_DONE 0x068 0x314 0x000 0x7 0x0 | ||
| 117 | #define MX50_PAD_SSI_TXFS__AUDMUX_AUD3_TXFS 0x06c 0x318 0x000 0x0 0x0 | ||
| 118 | #define MX50_PAD_SSI_TXFS__GPIO6_0 0x06c 0x318 0x000 0x1 0x0 | ||
| 119 | #define MX50_PAD_SSI_TXFS__SRC_BT_FUSE_RSV_1 0x06c 0x318 0x000 0x6 0x0 | ||
| 120 | #define MX50_PAD_SSI_TXFS__USBPHY1_DATAOUT_8 0x06c 0x318 0x000 0x7 0x0 | ||
| 121 | #define MX50_PAD_SSI_TXC__AUDMUX_AUD3_TXC 0x070 0x31c 0x000 0x0 0x0 | ||
| 122 | #define MX50_PAD_SSI_TXC__GPIO6_1 0x070 0x31c 0x000 0x1 0x0 | ||
| 123 | #define MX50_PAD_SSI_TXC__SRC_BT_FUSE_RSV_0 0x070 0x31c 0x000 0x6 0x0 | ||
| 124 | #define MX50_PAD_SSI_TXC__USBPHY1_DATAOUT_9 0x070 0x31c 0x000 0x7 0x0 | ||
| 125 | #define MX50_PAD_SSI_TXD__AUDMUX_AUD3_TXD 0x074 0x320 0x000 0x0 0x0 | ||
| 126 | #define MX50_PAD_SSI_TXD__GPIO6_2 0x074 0x320 0x000 0x1 0x0 | ||
| 127 | #define MX50_PAD_SSI_TXD__CSPI_RDY 0x074 0x320 0x6e8 0x4 0x0 | ||
| 128 | #define MX50_PAD_SSI_TXD__USBPHY1_DATAOUT_10 0x074 0x320 0x000 0x7 0x0 | ||
| 129 | #define MX50_PAD_SSI_RXD__AUDMUX_AUD3_RXD 0x078 0x324 0x000 0x0 0x0 | ||
| 130 | #define MX50_PAD_SSI_RXD__GPIO6_3 0x078 0x324 0x000 0x1 0x0 | ||
| 131 | #define MX50_PAD_SSI_RXD__CSPI_SS3 0x078 0x324 0x6f4 0x4 0x0 | ||
| 132 | #define MX50_PAD_SSI_RXD__USBPHY1_DATAOUT_11 0x078 0x324 0x000 0x7 0x0 | ||
| 133 | #define MX50_PAD_SSI_RXFS__AUDMUX_AUD3_RXFS 0x07c 0x328 0x000 0x0 0x0 | ||
| 134 | #define MX50_PAD_SSI_RXFS__GPIO6_4 0x07c 0x328 0x000 0x1 0x0 | ||
| 135 | #define MX50_PAD_SSI_RXFS__UART5_TXD_MUX 0x07c 0x328 0x7e4 0x2 0x0 | ||
| 136 | #define MX50_PAD_SSI_RXFS__EIM_WEIM_D_6 0x07c 0x328 0x804 0x3 0x0 | ||
| 137 | #define MX50_PAD_SSI_RXFS__CSPI_SS2 0x07c 0x328 0x6f0 0x4 0x0 | ||
| 138 | #define MX50_PAD_SSI_RXFS__FEC_COL 0x07c 0x328 0x770 0x5 0x0 | ||
| 139 | #define MX50_PAD_SSI_RXFS__FEC_MDC 0x07c 0x328 0x000 0x6 0x0 | ||
| 140 | #define MX50_PAD_SSI_RXFS__USBPHY1_DATAOUT_12 0x07c 0x328 0x000 0x7 0x0 | ||
| 141 | #define MX50_PAD_SSI_RXC__AUDMUX_AUD3_RXC 0x080 0x32c 0x000 0x0 0x0 | ||
| 142 | #define MX50_PAD_SSI_RXC__GPIO6_5 0x080 0x32c 0x000 0x1 0x0 | ||
| 143 | #define MX50_PAD_SSI_RXC__UART5_RXD_MUX 0x080 0x32c 0x7e4 0x2 0x1 | ||
| 144 | #define MX50_PAD_SSI_RXC__EIM_WEIM_D_7 0x080 0x32c 0x808 0x3 0x0 | ||
| 145 | #define MX50_PAD_SSI_RXC__CSPI_SS1 0x080 0x32c 0x6ec 0x4 0x0 | ||
| 146 | #define MX50_PAD_SSI_RXC__FEC_RX_CLK 0x080 0x32c 0x780 0x5 0x0 | ||
| 147 | #define MX50_PAD_SSI_RXC__FEC_MDIO 0x080 0x32c 0x774 0x6 0x1 | ||
| 148 | #define MX50_PAD_SSI_RXC__USBPHY1_DATAOUT_13 0x080 0x32c 0x000 0x7 0x0 | ||
| 149 | #define MX50_PAD_UART1_TXD__UART1_TXD_MUX 0x084 0x330 0x7c4 0x0 0x0 | ||
| 150 | #define MX50_PAD_UART1_TXD__GPIO6_6 0x084 0x330 0x000 0x1 0x0 | ||
| 151 | #define MX50_PAD_UART1_TXD__USBPHY1_DATAOUT_14 0x084 0x330 0x000 0x7 0x0 | ||
| 152 | #define MX50_PAD_UART1_RXD__UART1_RXD_MUX 0x088 0x334 0x7c4 0x0 0x1 | ||
| 153 | #define MX50_PAD_UART1_RXD__GPIO6_7 0x088 0x334 0x000 0x1 0x0 | ||
| 154 | #define MX50_PAD_UART1_RXD__USBPHY1_DATAOUT_15 0x088 0x334 0x000 0x7 0x0 | ||
| 155 | #define MX50_PAD_UART1_CTS__UART1_CTS 0x08c 0x338 0x000 0x0 0x0 | ||
| 156 | #define MX50_PAD_UART1_CTS__GPIO6_8 0x08c 0x338 0x000 0x1 0x0 | ||
| 157 | #define MX50_PAD_UART1_CTS__UART5_TXD_MUX 0x08c 0x338 0x7e4 0x2 0x2 | ||
| 158 | #define MX50_PAD_UART1_CTS__ESDHC4_DAT4 0x08c 0x338 0x760 0x4 0x0 | ||
| 159 | #define MX50_PAD_UART1_CTS__ESDHC4_CMD 0x08c 0x338 0x74c 0x5 0x0 | ||
| 160 | #define MX50_PAD_UART1_CTS__USBPHY2_DATAOUT_8 0x08c 0x338 0x000 0x7 0x0 | ||
| 161 | #define MX50_PAD_UART1_RTS__UART1_RTS 0x090 0x33c 0x7c0 0x0 0x3 | ||
| 162 | #define MX50_PAD_UART1_RTS__GPIO6_9 0x090 0x33c 0x000 0x1 0x0 | ||
| 163 | #define MX50_PAD_UART1_RTS__UART5_RXD_MUX 0x090 0x33c 0x7e4 0x2 0x3 | ||
| 164 | #define MX50_PAD_UART1_RTS__ESDHC4_DAT5 0x090 0x33c 0x764 0x4 0x0 | ||
| 165 | #define MX50_PAD_UART1_RTS__ESDHC4_CLK 0x090 0x33c 0x748 0x5 0x0 | ||
| 166 | #define MX50_PAD_UART1_RTS__USBPHY2_DATAOUT_9 0x090 0x33c 0x000 0x7 0x0 | ||
| 167 | #define MX50_PAD_UART2_TXD__UART2_TXD_MUX 0x094 0x340 0x7cc 0x0 0x2 | ||
| 168 | #define MX50_PAD_UART2_TXD__GPIO6_10 0x094 0x340 0x000 0x1 0x0 | ||
| 169 | #define MX50_PAD_UART2_TXD__ESDHC4_DAT6 0x094 0x340 0x768 0x4 0x0 | ||
| 170 | #define MX50_PAD_UART2_TXD__ESDHC4_DAT4 0x094 0x340 0x760 0x5 0x1 | ||
| 171 | #define MX50_PAD_UART2_TXD__USBPHY2_DATAOUT_10 0x094 0x340 0x000 0x7 0x0 | ||
| 172 | #define MX50_PAD_UART2_RXD__UART2_RXD_MUX 0x098 0x344 0x7cc 0x0 0x3 | ||
| 173 | #define MX50_PAD_UART2_RXD__GPIO6_11 0x098 0x344 0x000 0x1 0x0 | ||
| 174 | #define MX50_PAD_UART2_RXD__ESDHC4_DAT7 0x098 0x344 0x76c 0x4 0x0 | ||
| 175 | #define MX50_PAD_UART2_RXD__ESDHC4_DAT5 0x098 0x344 0x764 0x5 0x1 | ||
| 176 | #define MX50_PAD_UART2_RXD__USBPHY2_DATAOUT_11 0x098 0x344 0x000 0x7 0x0 | ||
| 177 | #define MX50_PAD_UART2_CTS__UART2_CTS 0x09c 0x348 0x000 0x0 0x0 | ||
| 178 | #define MX50_PAD_UART2_CTS__GPIO6_12 0x09c 0x348 0x000 0x1 0x0 | ||
| 179 | #define MX50_PAD_UART2_CTS__ESDHC4_CMD 0x09c 0x348 0x74c 0x4 0x1 | ||
| 180 | #define MX50_PAD_UART2_CTS__ESDHC4_DAT6 0x09c 0x348 0x768 0x5 0x1 | ||
| 181 | #define MX50_PAD_UART2_CTS__USBPHY2_DATAOUT_12 0x09c 0x348 0x000 0x7 0x0 | ||
| 182 | #define MX50_PAD_UART2_RTS__UART2_RTS 0x0a0 0x34c 0x7c8 0x0 0x2 | ||
| 183 | #define MX50_PAD_UART2_RTS__GPIO6_13 0x0a0 0x34c 0x000 0x1 0x0 | ||
| 184 | #define MX50_PAD_UART2_RTS__ESDHC4_CLK 0x0a0 0x34c 0x748 0x4 0x1 | ||
| 185 | #define MX50_PAD_UART2_RTS__ESDHC4_DAT7 0x0a0 0x34c 0x76c 0x5 0x1 | ||
| 186 | #define MX50_PAD_UART2_RTS__USBPHY2_DATAOUT_13 0x0a0 0x34c 0x000 0x7 0x0 | ||
| 187 | #define MX50_PAD_UART3_TXD__UART3_TXD_MUX 0x0a4 0x350 0x7d4 0x0 0x0 | ||
| 188 | #define MX50_PAD_UART3_TXD__GPIO6_14 0x0a4 0x350 0x000 0x1 0x0 | ||
| 189 | #define MX50_PAD_UART3_TXD__ESDHC1_DAT4 0x0a4 0x350 0x000 0x3 0x0 | ||
| 190 | #define MX50_PAD_UART3_TXD__ESDHC4_DAT0 0x0a4 0x350 0x000 0x4 0x0 | ||
| 191 | #define MX50_PAD_UART3_TXD__ESDHC2_WP 0x0a4 0x350 0x744 0x5 0x0 | ||
| 192 | #define MX50_PAD_UART3_TXD__EIM_WEIM_D_12 0x0a4 0x350 0x81c 0x6 0x0 | ||
| 193 | #define MX50_PAD_UART3_TXD__USBPHY2_DATAOUT_14 0x0a4 0x350 0x000 0x7 0x0 | ||
| 194 | #define MX50_PAD_UART3_RXD__UART3_RXD_MUX 0x0a8 0x354 0x7d4 0x0 0x1 | ||
| 195 | #define MX50_PAD_UART3_RXD__GPIO6_15 0x0a8 0x354 0x000 0x1 0x0 | ||
| 196 | #define MX50_PAD_UART3_RXD__ESDHC1_DAT5 0x0a8 0x354 0x000 0x3 0x0 | ||
| 197 | #define MX50_PAD_UART3_RXD__ESDHC4_DAT1 0x0a8 0x354 0x754 0x4 0x0 | ||
| 198 | #define MX50_PAD_UART3_RXD__ESDHC2_CD 0x0a8 0x354 0x740 0x5 0x0 | ||
| 199 | #define MX50_PAD_UART3_RXD__EIM_WEIM_D_13 0x0a8 0x354 0x820 0x6 0x0 | ||
| 200 | #define MX50_PAD_UART3_RXD__USBPHY2_DATAOUT_15 0x0a8 0x354 0x000 0x7 0x0 | ||
| 201 | #define MX50_PAD_UART4_TXD__UART4_TXD_MUX 0x0ac 0x358 0x7dc 0x0 0x0 | ||
| 202 | #define MX50_PAD_UART4_TXD__GPIO6_16 0x0ac 0x358 0x000 0x1 0x0 | ||
| 203 | #define MX50_PAD_UART4_TXD__UART3_CTS 0x0ac 0x358 0x7d0 0x2 0x0 | ||
| 204 | #define MX50_PAD_UART4_TXD__ESDHC1_DAT6 0x0ac 0x358 0x000 0x3 0x0 | ||
| 205 | #define MX50_PAD_UART4_TXD__ESDHC4_DAT2 0x0ac 0x358 0x758 0x4 0x0 | ||
| 206 | #define MX50_PAD_UART4_TXD__ESDHC2_LCTL 0x0ac 0x358 0x000 0x5 0x0 | ||
| 207 | #define MX50_PAD_UART4_TXD__EIM_WEIM_D_14 0x0ac 0x358 0x824 0x6 0x0 | ||
| 208 | #define MX50_PAD_UART4_RXD__UART4_RXD_MUX 0x0b0 0x35c 0x7dc 0x0 0x1 | ||
| 209 | #define MX50_PAD_UART4_RXD__GPIO6_17 0x0b0 0x35c 0x000 0x1 0x0 | ||
| 210 | #define MX50_PAD_UART4_RXD__UART3_RTS 0x0b0 0x35c 0x7d0 0x2 0x1 | ||
| 211 | #define MX50_PAD_UART4_RXD__ESDHC1_DAT7 0x0b0 0x35c 0x000 0x3 0x0 | ||
| 212 | #define MX50_PAD_UART4_RXD__ESDHC4_DAT3 0x0b0 0x35c 0x75c 0x4 0x0 | ||
| 213 | #define MX50_PAD_UART4_RXD__ESDHC1_LCTL 0x0b0 0x35c 0x000 0x5 0x0 | ||
| 214 | #define MX50_PAD_UART4_RXD__EIM_WEIM_D_15 0x0b0 0x35c 0x828 0x6 0x0 | ||
| 215 | #define MX50_PAD_CSPI_SCLK__CSPI_SCLK 0x0b4 0x360 0x000 0x0 0x0 | ||
| 216 | #define MX50_PAD_CSPI_SCLK__GPIO4_8 0x0b4 0x360 0x000 0x1 0x0 | ||
| 217 | #define MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x0b8 0x364 0x000 0x0 0x0 | ||
| 218 | #define MX50_PAD_CSPI_MOSI__GPIO4_9 0x0b8 0x364 0x000 0x1 0x0 | ||
| 219 | #define MX50_PAD_CSPI_MISO__CSPI_MISO 0x0bc 0x368 0x000 0x0 0x0 | ||
| 220 | #define MX50_PAD_CSPI_MISO__GPIO4_10 0x0bc 0x368 0x000 0x1 0x0 | ||
| 221 | #define MX50_PAD_CSPI_SS0__CSPI_SS0 0x0c0 0x36c 0x000 0x0 0x0 | ||
| 222 | #define MX50_PAD_CSPI_SS0__GPIO4_11 0x0c0 0x36c 0x000 0x1 0x0 | ||
| 223 | #define MX50_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x0c4 0x370 0x000 0x0 0x0 | ||
| 224 | #define MX50_PAD_ECSPI1_SCLK__GPIO4_12 0x0c4 0x370 0x000 0x1 0x0 | ||
| 225 | #define MX50_PAD_ECSPI1_SCLK__CSPI_RDY 0x0c4 0x370 0x6e8 0x2 0x1 | ||
| 226 | #define MX50_PAD_ECSPI1_SCLK__ECSPI2_RDY 0x0c4 0x370 0x000 0x3 0x0 | ||
| 227 | #define MX50_PAD_ECSPI1_SCLK__UART3_RTS 0x0c4 0x370 0x7d0 0x4 0x2 | ||
| 228 | #define MX50_PAD_ECSPI1_SCLK__EPDC_SDCE_6 0x0c4 0x370 0x000 0x5 0x0 | ||
| 229 | #define MX50_PAD_ECSPI1_SCLK__EIM_WEIM_D_8 0x0c4 0x370 0x80c 0x7 0x0 | ||
| 230 | #define MX50_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x0c8 0x374 0x000 0x0 0x0 | ||
| 231 | #define MX50_PAD_ECSPI1_MOSI__GPIO4_13 0x0c8 0x374 0x000 0x1 0x0 | ||
| 232 | #define MX50_PAD_ECSPI1_MOSI__CSPI_SS1 0x0c8 0x374 0x6ec 0x2 0x1 | ||
| 233 | #define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1 0x0c8 0x374 0x000 0x3 0x0 | ||
| 234 | #define MX50_PAD_ECSPI1_MOSI__UART3_CTS 0x0c8 0x374 0x000 0x4 0x0 | ||
| 235 | #define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE_7 0x0c8 0x374 0x000 0x5 0x0 | ||
| 236 | #define MX50_PAD_ECSPI1_MOSI__EIM_WEIM_D_9 0x0c8 0x374 0x810 0x7 0x0 | ||
| 237 | #define MX50_PAD_ECSPI1_MISO__ECSPI1_MISO 0x0cc 0x378 0x000 0x0 0x0 | ||
| 238 | #define MX50_PAD_ECSPI1_MISO__GPIO4_14 0x0cc 0x378 0x000 0x1 0x0 | ||
| 239 | #define MX50_PAD_ECSPI1_MISO__CSPI_SS2 0x0cc 0x378 0x6f0 0x2 0x1 | ||
| 240 | #define MX50_PAD_ECSPI1_MISO__ECSPI2_SS2 0x0cc 0x378 0x000 0x3 0x0 | ||
| 241 | #define MX50_PAD_ECSPI1_MISO__UART4_RTS 0x0cc 0x378 0x7d8 0x4 0x0 | ||
| 242 | #define MX50_PAD_ECSPI1_MISO__EPDC_SDCE_8 0x0cc 0x378 0x000 0x5 0x0 | ||
| 243 | #define MX50_PAD_ECSPI1_MISO__EIM_WEIM_D_10 0x0cc 0x378 0x814 0x7 0x0 | ||
| 244 | #define MX50_PAD_ECSPI1_SS0__ECSPI1_SS0 0x0d0 0x37c 0x000 0x0 0x0 | ||
| 245 | #define MX50_PAD_ECSPI1_SS0__GPIO4_15 0x0d0 0x37c 0x000 0x1 0x0 | ||
| 246 | #define MX50_PAD_ECSPI1_SS0__CSPI_SS3 0x0d0 0x37c 0x6f4 0x2 0x1 | ||
| 247 | #define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3 0x0d0 0x37c 0x000 0x3 0x0 | ||
| 248 | #define MX50_PAD_ECSPI1_SS0__UART4_CTS 0x0d0 0x37c 0x000 0x4 0x0 | ||
| 249 | #define MX50_PAD_ECSPI1_SS0__EPDC_SDCE_9 0x0d0 0x37c 0x000 0x5 0x0 | ||
| 250 | #define MX50_PAD_ECSPI1_SS0__EIM_WEIM_D_11 0x0d0 0x37c 0x818 0x7 0x0 | ||
| 251 | #define MX50_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x0d4 0x380 0x000 0x0 0x0 | ||
| 252 | #define MX50_PAD_ECSPI2_SCLK__GPIO4_16 0x0d4 0x380 0x000 0x1 0x0 | ||
| 253 | #define MX50_PAD_ECSPI2_SCLK__ELCDIF_WR_RWN 0x0d4 0x380 0x000 0x2 0x0 | ||
| 254 | #define MX50_PAD_ECSPI2_SCLK__ECSPI1_RDY 0x0d4 0x380 0x000 0x3 0x0 | ||
| 255 | #define MX50_PAD_ECSPI2_SCLK__UART5_RTS 0x0d4 0x380 0x7e0 0x4 0x0 | ||
| 256 | #define MX50_PAD_ECSPI2_SCLK__ELCDIF_DOTCLK 0x0d4 0x380 0x000 0x5 0x0 | ||
| 257 | #define MX50_PAD_ECSPI2_SCLK__EIM_NANDF_CEN_4 0x0d4 0x380 0x000 0x6 0x0 | ||
| 258 | #define MX50_PAD_ECSPI2_SCLK__EIM_WEIM_D_8 0x0d4 0x380 0x80c 0x7 0x1 | ||
| 259 | #define MX50_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x0d8 0x384 0x000 0x0 0x0 | ||
| 260 | #define MX50_PAD_ECSPI2_MOSI__GPIO4_17 0x0d8 0x384 0x000 0x1 0x0 | ||
| 261 | #define MX50_PAD_ECSPI2_MOSI__ELCDIF_RE_E 0x0d8 0x384 0x000 0x2 0x0 | ||
| 262 | #define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1 0x0d8 0x384 0x000 0x3 0x0 | ||
| 263 | #define MX50_PAD_ECSPI2_MOSI__UART5_CTS 0x0d8 0x384 0x7e0 0x4 0x1 | ||
| 264 | #define MX50_PAD_ECSPI2_MOSI__ELCDIF_ENABLE 0x0d8 0x384 0x000 0x5 0x0 | ||
| 265 | #define MX50_PAD_ECSPI2_MOSI__EIM_NANDF_CEN_5 0x0d8 0x384 0x000 0x6 0x0 | ||
| 266 | #define MX50_PAD_ECSPI2_MOSI__EIM_WEIM_D_9 0x0d8 0x384 0x810 0x7 0x1 | ||
| 267 | #define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO 0x0dc 0x388 0x000 0x0 0x0 | ||
| 268 | #define MX50_PAD_ECSPI2_MISO__GPIO4_18 0x0dc 0x388 0x000 0x1 0x0 | ||
| 269 | #define MX50_PAD_ECSPI2_MISO__ELCDIF_RS 0x0dc 0x388 0x000 0x2 0x0 | ||
| 270 | #define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2 0x0dc 0x388 0x000 0x3 0x0 | ||
| 271 | #define MX50_PAD_ECSPI2_MISO__UART5_TXD_MUX 0x0dc 0x388 0x7e4 0x4 0x4 | ||
| 272 | #define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC 0x0dc 0x388 0x73c 0x5 0x0 | ||
| 273 | #define MX50_PAD_ECSPI2_MISO__EIM_NANDF_CEN_6 0x0dc 0x388 0x000 0x6 0x0 | ||
| 274 | #define MX50_PAD_ECSPI2_MISO__EIM_WEIM_D_10 0x0dc 0x388 0x814 0x7 0x1 | ||
| 275 | #define MX50_PAD_ECSPI2_SS0__ECSPI2_SS0 0x0e0 0x38c 0x000 0x0 0x0 | ||
| 276 | #define MX50_PAD_ECSPI2_SS0__GPIO4_19 0x0e0 0x38c 0x000 0x1 0x0 | ||
| 277 | #define MX50_PAD_ECSPI2_SS0__ELCDIF_CS 0x0e0 0x38c 0x000 0x2 0x0 | ||
| 278 | #define MX50_PAD_ECSPI2_SS0__ECSPI2_SS3 0x0e0 0x38c 0x000 0x3 0x0 | ||
| 279 | #define MX50_PAD_ECSPI2_SS0__UART5_RXD_MUX 0x0e0 0x38c 0x7e4 0x4 0x5 | ||
| 280 | #define MX50_PAD_ECSPI2_SS0__ELCDIF_HSYNC 0x0e0 0x38c 0x6f8 0x5 0x0 | ||
| 281 | #define MX50_PAD_ECSPI2_SS0__EIM_NANDF_CEN_7 0x0e0 0x38c 0x000 0x6 0x0 | ||
| 282 | #define MX50_PAD_ECSPI2_SS0__EIM_WEIM_D_11 0x0e0 0x38c 0x818 0x7 0x1 | ||
| 283 | #define MX50_PAD_SD1_CLK__ESDHC1_CLK 0x0e4 0x390 0x000 0x0 0x0 | ||
| 284 | #define MX50_PAD_SD1_CLK__GPIO5_0 0x0e4 0x390 0x000 0x1 0x0 | ||
| 285 | #define MX50_PAD_SD1_CLK__CCM_CLKO 0x0e4 0x390 0x000 0x7 0x0 | ||
| 286 | #define MX50_PAD_SD1_CMD__ESDHC1_CMD 0x0e8 0x394 0x000 0x0 0x0 | ||
| 287 | #define MX50_PAD_SD1_CMD__GPIO5_1 0x0e8 0x394 0x000 0x1 0x0 | ||
| 288 | #define MX50_PAD_SD1_CMD__CCM_CLKO2 0x0e8 0x394 0x000 0x7 0x0 | ||
| 289 | #define MX50_PAD_SD1_D0__ESDHC1_DAT0 0x0ec 0x398 0x000 0x0 0x0 | ||
| 290 | #define MX50_PAD_SD1_D0__GPIO5_2 0x0ec 0x398 0x000 0x1 0x0 | ||
| 291 | #define MX50_PAD_SD1_D0__CCM_PLL1_BYP 0x0ec 0x398 0x6dc 0x7 0x0 | ||
| 292 | #define MX50_PAD_SD1_D1__ESDHC1_DAT1 0x0f0 0x39c 0x000 0x0 0x0 | ||
| 293 | #define MX50_PAD_SD1_D1__GPIO5_3 0x0f0 0x39c 0x000 0x1 0x0 | ||
| 294 | #define MX50_PAD_SD1_D1__CCM_PLL2_BYP 0x0f0 0x39c 0x000 0x7 0x0 | ||
| 295 | #define MX50_PAD_SD1_D2__ESDHC1_DAT2 0x0f4 0x3a0 0x000 0x0 0x0 | ||
| 296 | #define MX50_PAD_SD1_D2__GPIO5_4 0x0f4 0x3a0 0x000 0x1 0x0 | ||
| 297 | #define MX50_PAD_SD1_D2__CCM_PLL3_BYP 0x0f4 0x3a0 0x6e4 0x7 0x0 | ||
| 298 | #define MX50_PAD_SD1_D3__ESDHC1_DAT3 0x0f8 0x3a4 0x000 0x0 0x0 | ||
| 299 | #define MX50_PAD_SD1_D3__GPIO5_5 0x0f8 0x3a4 0x000 0x1 0x0 | ||
| 300 | #define MX50_PAD_SD2_CLK__ESDHC2_CLK 0x0fc 0x3a8 0x000 0x0 0x0 | ||
| 301 | #define MX50_PAD_SD2_CLK__GPIO5_6 0x0fc 0x3a8 0x000 0x1 0x0 | ||
| 302 | #define MX50_PAD_SD2_CLK__MSHC_SCLK 0x0fc 0x3a8 0x000 0x2 0x0 | ||
| 303 | #define MX50_PAD_SD2_CMD__ESDHC2_CMD 0x100 0x3ac 0x000 0x0 0x0 | ||
| 304 | #define MX50_PAD_SD2_CMD__GPIO5_7 0x100 0x3ac 0x000 0x1 0x0 | ||
| 305 | #define MX50_PAD_SD2_CMD__MSHC_BS 0x100 0x3ac 0x000 0x2 0x0 | ||
| 306 | #define MX50_PAD_SD2_D0__ESDHC2_DAT0 0x104 0x3b0 0x000 0x0 0x0 | ||
| 307 | #define MX50_PAD_SD2_D0__GPIO5_8 0x104 0x3b0 0x000 0x1 0x0 | ||
| 308 | #define MX50_PAD_SD2_D0__MSHC_DATA_0 0x104 0x3b0 0x000 0x2 0x0 | ||
| 309 | #define MX50_PAD_SD2_D0__KPP_COL_4 0x104 0x3b0 0x790 0x3 0x0 | ||
| 310 | #define MX50_PAD_SD2_D1__ESDHC2_DAT1 0x108 0x3b4 0x000 0x0 0x0 | ||
| 311 | #define MX50_PAD_SD2_D1__GPIO5_9 0x108 0x3b4 0x000 0x1 0x0 | ||
| 312 | #define MX50_PAD_SD2_D1__MSHC_DATA_1 0x108 0x3b4 0x000 0x2 0x0 | ||
| 313 | #define MX50_PAD_SD2_D1__KPP_ROW_4 0x108 0x3b4 0x7a0 0x3 0x0 | ||
| 314 | #define MX50_PAD_SD2_D2__ESDHC2_DAT2 0x10c 0x3b8 0x000 0x0 0x0 | ||
| 315 | #define MX50_PAD_SD2_D2__GPIO5_10 0x10c 0x3b8 0x000 0x1 0x0 | ||
| 316 | #define MX50_PAD_SD2_D2__MSHC_DATA_2 0x10c 0x3b8 0x000 0x2 0x0 | ||
| 317 | #define MX50_PAD_SD2_D2__KPP_COL_5 0x10c 0x3b8 0x794 0x3 0x0 | ||
| 318 | #define MX50_PAD_SD2_D3__ESDHC2_DAT3 0x110 0x3bc 0x000 0x0 0x0 | ||
| 319 | #define MX50_PAD_SD2_D3__GPIO5_11 0x110 0x3bc 0x000 0x1 0x0 | ||
| 320 | #define MX50_PAD_SD2_D3__MSHC_DATA_3 0x110 0x3bc 0x000 0x2 0x0 | ||
| 321 | #define MX50_PAD_SD2_D3__KPP_ROW_5 0x110 0x3bc 0x7a4 0x3 0x0 | ||
| 322 | #define MX50_PAD_SD2_D4__ESDHC2_DAT4 0x114 0x3c0 0x000 0x0 0x0 | ||
| 323 | #define MX50_PAD_SD2_D4__GPIO5_12 0x114 0x3c0 0x000 0x1 0x0 | ||
| 324 | #define MX50_PAD_SD2_D4__AUDMUX_AUD4_RXFS 0x114 0x3c0 0x6d0 0x2 0x0 | ||
| 325 | #define MX50_PAD_SD2_D4__KPP_COL_6 0x114 0x3c0 0x798 0x3 0x0 | ||
| 326 | #define MX50_PAD_SD2_D4__EIM_WEIM_D_0 0x114 0x3c0 0x7ec 0x4 0x0 | ||
| 327 | #define MX50_PAD_SD2_D4__CCM_CCM_OUT_0 0x114 0x3c0 0x000 0x7 0x0 | ||
| 328 | #define MX50_PAD_SD2_D5__ESDHC2_DAT5 0x118 0x3c4 0x000 0x0 0x0 | ||
| 329 | #define MX50_PAD_SD2_D5__GPIO5_13 0x118 0x3c4 0x000 0x1 0x0 | ||
| 330 | #define MX50_PAD_SD2_D5__AUDMUX_AUD4_RXC 0x118 0x3c4 0x6cc 0x2 0x0 | ||
| 331 | #define MX50_PAD_SD2_D5__KPP_ROW_6 0x118 0x3c4 0x7a8 0x3 0x0 | ||
| 332 | #define MX50_PAD_SD2_D5__EIM_WEIM_D_1 0x118 0x3c4 0x7f0 0x4 0x0 | ||
| 333 | #define MX50_PAD_SD2_D5__CCM_CCM_OUT_1 0x118 0x3c4 0x000 0x7 0x0 | ||
| 334 | #define MX50_PAD_SD2_D6__ESDHC2_DAT6 0x11c 0x3c8 0x000 0x0 0x0 | ||
| 335 | #define MX50_PAD_SD2_D6__GPIO5_14 0x11c 0x3c8 0x000 0x1 0x0 | ||
| 336 | #define MX50_PAD_SD2_D6__AUDMUX_AUD4_RXD 0x11c 0x3c8 0x6c4 0x2 0x0 | ||
| 337 | #define MX50_PAD_SD2_D6__KPP_COL_7 0x11c 0x3c8 0x79c 0x3 0x0 | ||
| 338 | #define MX50_PAD_SD2_D6__EIM_WEIM_D_2 0x11c 0x3c8 0x7f4 0x4 0x0 | ||
| 339 | #define MX50_PAD_SD2_D6__CCM_CCM_OUT_2 0x11c 0x3c8 0x000 0x7 0x0 | ||
| 340 | #define MX50_PAD_SD2_D7__ESDHC2_DAT7 0x120 0x3cc 0x000 0x0 0x0 | ||
| 341 | #define MX50_PAD_SD2_D7__GPIO5_15 0x120 0x3cc 0x000 0x1 0x0 | ||
| 342 | #define MX50_PAD_SD2_D7__AUDMUX_AUD4_TXFS 0x120 0x3cc 0x6d8 0x2 0x0 | ||
| 343 | #define MX50_PAD_SD2_D7__KPP_ROW_7 0x120 0x3cc 0x7ac 0x3 0x0 | ||
| 344 | #define MX50_PAD_SD2_D7__EIM_WEIM_D_3 0x120 0x3cc 0x7f8 0x4 0x0 | ||
| 345 | #define MX50_PAD_SD2_D7__CCM_STOP 0x120 0x3cc 0x000 0x7 0x0 | ||
| 346 | #define MX50_PAD_SD2_WP__ESDHC2_WP 0x124 0x3d0 0x744 0x0 0x1 | ||
| 347 | #define MX50_PAD_SD2_WP__GPIO5_16 0x124 0x3d0 0x000 0x1 0x0 | ||
| 348 | #define MX50_PAD_SD2_WP__AUDMUX_AUD4_TXD 0x124 0x3d0 0x6c8 0x2 0x0 | ||
| 349 | #define MX50_PAD_SD2_WP__EIM_WEIM_D_4 0x124 0x3d0 0x7fc 0x4 0x0 | ||
| 350 | #define MX50_PAD_SD2_WP__CCM_WAIT 0x124 0x3d0 0x000 0x7 0x0 | ||
| 351 | #define MX50_PAD_SD2_CD__ESDHC2_CD 0x128 0x3d4 0x740 0x0 0x1 | ||
| 352 | #define MX50_PAD_SD2_CD__GPIO5_17 0x128 0x3d4 0x000 0x1 0x0 | ||
| 353 | #define MX50_PAD_SD2_CD__AUDMUX_AUD4_TXC 0x128 0x3d4 0x6d4 0x2 0x0 | ||
| 354 | #define MX50_PAD_SD2_CD__EIM_WEIM_D_5 0x128 0x3d4 0x800 0x4 0x0 | ||
| 355 | #define MX50_PAD_SD2_CD__CCM_REF_EN_B 0x128 0x3d4 0x000 0x7 0x0 | ||
| 356 | #define MX50_PAD_DISP_D0__ELCDIF_DAT_0 0x12c 0x40c 0x6fc 0x0 0x0 | ||
| 357 | #define MX50_PAD_DISP_D0__GPIO2_0 0x12c 0x40c 0x000 0x1 0x0 | ||
| 358 | #define MX50_PAD_DISP_D0__FEC_TX_CLK 0x12c 0x40c 0x78c 0x2 0x0 | ||
| 359 | #define MX50_PAD_DISP_D0__EIM_WEIM_A_16 0x12c 0x40c 0x000 0x3 0x0 | ||
| 360 | #define MX50_PAD_DISP_D0__SDMA_DEBUG_PC_0 0x12c 0x40c 0x000 0x6 0x0 | ||
| 361 | #define MX50_PAD_DISP_D0__USBPHY1_VSTATUS_0 0x12c 0x40c 0x000 0x7 0x0 | ||
| 362 | #define MX50_PAD_DISP_D1__ELCDIF_DAT_1 0x130 0x410 0x700 0x0 0x0 | ||
| 363 | #define MX50_PAD_DISP_D1__GPIO2_1 0x130 0x410 0x000 0x1 0x0 | ||
| 364 | #define MX50_PAD_DISP_D1__FEC_RX_ERR 0x130 0x410 0x788 0x2 0x0 | ||
| 365 | #define MX50_PAD_DISP_D1__EIM_WEIM_A_17 0x130 0x410 0x000 0x3 0x0 | ||
| 366 | #define MX50_PAD_DISP_D1__SDMA_DEBUG_PC_1 0x130 0x410 0x000 0x6 0x0 | ||
| 367 | #define MX50_PAD_DISP_D1__USBPHY1_VSTATUS_1 0x130 0x410 0x000 0x7 0x0 | ||
| 368 | #define MX50_PAD_DISP_D2__ELCDIF_DAT_2 0x134 0x414 0x704 0x0 0x0 | ||
| 369 | #define MX50_PAD_DISP_D2__GPIO2_2 0x134 0x414 0x000 0x1 0x0 | ||
| 370 | #define MX50_PAD_DISP_D2__FEC_RX_DV 0x134 0x414 0x784 0x2 0x0 | ||
| 371 | #define MX50_PAD_DISP_D2__EIM_WEIM_A_18 0x134 0x414 0x000 0x3 0x0 | ||
| 372 | #define MX50_PAD_DISP_D2__SDMA_DEBUG_PC_2 0x134 0x414 0x000 0x6 0x0 | ||
| 373 | #define MX50_PAD_DISP_D2__USBPHY1_VSTATUS_2 0x134 0x414 0x000 0x7 0x0 | ||
| 374 | #define MX50_PAD_DISP_D3__ELCDIF_DAT_3 0x138 0x418 0x708 0x0 0x0 | ||
| 375 | #define MX50_PAD_DISP_D3__GPIO2_3 0x138 0x418 0x000 0x1 0x0 | ||
| 376 | #define MX50_PAD_DISP_D3__FEC_RDATA_1 0x138 0x418 0x77c 0x2 0x0 | ||
| 377 | #define MX50_PAD_DISP_D3__EIM_WEIM_A_19 0x138 0x418 0x000 0x3 0x0 | ||
| 378 | #define MX50_PAD_DISP_D3__FEC_COL 0x138 0x418 0x770 0x4 0x1 | ||
| 379 | #define MX50_PAD_DISP_D3__SDMA_DEBUG_PC_3 0x138 0x418 0x000 0x6 0x0 | ||
| 380 | #define MX50_PAD_DISP_D3__USBPHY1_VSTATUS_3 0x138 0x418 0x000 0x7 0x0 | ||
| 381 | #define MX50_PAD_DISP_D4__ELCDIF_DAT_4 0x13c 0x41c 0x70c 0x0 0x0 | ||
| 382 | #define MX50_PAD_DISP_D4__GPIO2_4 0x13c 0x41c 0x000 0x1 0x0 | ||
| 383 | #define MX50_PAD_DISP_D4__FEC_RDATA_0 0x13c 0x41c 0x778 0x2 0x0 | ||
| 384 | #define MX50_PAD_DISP_D4__EIM_WEIM_A_20 0x13c 0x41c 0x000 0x3 0x0 | ||
| 385 | #define MX50_PAD_DISP_D4__SDMA_DEBUG_PC_4 0x13c 0x41c 0x000 0x6 0x0 | ||
| 386 | #define MX50_PAD_DISP_D4__USBPHY1_VSTATUS_4 0x13c 0x41c 0x000 0x7 0x0 | ||
| 387 | #define MX50_PAD_DISP_D5__ELCDIF_DAT_5 0x140 0x420 0x710 0x0 0x0 | ||
| 388 | #define MX50_PAD_DISP_D5__GPIO2_5 0x140 0x420 0x000 0x1 0x0 | ||
| 389 | #define MX50_PAD_DISP_D5__FEC_TX_EN 0x140 0x420 0x000 0x2 0x0 | ||
| 390 | #define MX50_PAD_DISP_D5__EIM_WEIM_A_21 0x140 0x420 0x000 0x3 0x0 | ||
| 391 | #define MX50_PAD_DISP_D5__SDMA_DEBUG_PC_5 0x140 0x420 0x000 0x6 0x0 | ||
| 392 | #define MX50_PAD_DISP_D5__USBPHY1_VSTATUS_5 0x140 0x420 0x000 0x7 0x0 | ||
| 393 | #define MX50_PAD_DISP_D6__ELCDIF_DAT_6 0x144 0x424 0x714 0x0 0x0 | ||
| 394 | #define MX50_PAD_DISP_D6__GPIO2_6 0x144 0x424 0x000 0x1 0x0 | ||
| 395 | #define MX50_PAD_DISP_D6__FEC_TDATA_1 0x144 0x424 0x000 0x2 0x0 | ||
| 396 | #define MX50_PAD_DISP_D6__EIM_WEIM_A_22 0x144 0x424 0x000 0x3 0x0 | ||
| 397 | #define MX50_PAD_DISP_D6__FEC_RX_CLK 0x144 0x424 0x780 0x4 0x1 | ||
| 398 | #define MX50_PAD_DISP_D6__SDMA_DEBUG_PC_6 0x144 0x424 0x000 0x6 0x0 | ||
| 399 | #define MX50_PAD_DISP_D6__USBPHY1_VSTATUS_6 0x144 0x424 0x000 0x7 0x0 | ||
| 400 | #define MX50_PAD_DISP_D7__ELCDIF_DAT_7 0x148 0x428 0x718 0x0 0x0 | ||
| 401 | #define MX50_PAD_DISP_D7__GPIO2_7 0x148 0x428 0x000 0x1 0x0 | ||
| 402 | #define MX50_PAD_DISP_D7__FEC_TDATA_0 0x148 0x428 0x000 0x2 0x0 | ||
| 403 | #define MX50_PAD_DISP_D7__EIM_WEIM_A_23 0x148 0x428 0x000 0x3 0x0 | ||
| 404 | #define MX50_PAD_DISP_D7__SDMA_DEBUG_PC_7 0x148 0x428 0x000 0x6 0x0 | ||
| 405 | #define MX50_PAD_DISP_D7__USBPHY1_VSTATUS_7 0x148 0x428 0x000 0x7 0x0 | ||
| 406 | #define MX50_PAD_DISP_WR__ELCDIF_WR_RWN 0x14c 0x42c 0x000 0x0 0x0 | ||
| 407 | #define MX50_PAD_DISP_WR__GPIO2_16 0x14c 0x42c 0x000 0x1 0x0 | ||
| 408 | #define MX50_PAD_DISP_WR__ELCDIF_DOTCLK 0x14c 0x42c 0x000 0x2 0x0 | ||
| 409 | #define MX50_PAD_DISP_WR__EIM_WEIM_A_24 0x14c 0x42c 0x000 0x3 0x0 | ||
| 410 | #define MX50_PAD_DISP_WR__SDMA_DEBUG_PC_8 0x14c 0x42c 0x000 0x6 0x0 | ||
| 411 | #define MX50_PAD_DISP_WR__USBPHY1_AVALID 0x14c 0x42c 0x000 0x7 0x0 | ||
| 412 | #define MX50_PAD_DISP_RD__ELCDIF_RD_E 0x150 0x430 0x000 0x0 0x0 | ||
| 413 | #define MX50_PAD_DISP_RD__GPIO2_19 0x150 0x430 0x000 0x1 0x0 | ||
| 414 | #define MX50_PAD_DISP_RD__ELCDIF_ENABLE 0x150 0x430 0x000 0x2 0x0 | ||
| 415 | #define MX50_PAD_DISP_RD__EIM_WEIM_A_25 0x150 0x430 0x000 0x3 0x0 | ||
| 416 | #define MX50_PAD_DISP_RD__SDMA_DEBUG_PC_9 0x150 0x430 0x000 0x6 0x0 | ||
| 417 | #define MX50_PAD_DISP_RD__USBPHY1_BVALID 0x150 0x430 0x000 0x7 0x0 | ||
| 418 | #define MX50_PAD_DISP_RS__ELCDIF_RS 0x154 0x434 0x000 0x0 0x0 | ||
| 419 | #define MX50_PAD_DISP_RS__GPIO2_17 0x154 0x434 0x000 0x1 0x0 | ||
| 420 | #define MX50_PAD_DISP_RS__ELCDIF_VSYNC 0x154 0x434 0x73c 0x2 0x1 | ||
| 421 | #define MX50_PAD_DISP_RS__EIM_WEIM_A_26 0x154 0x434 0x000 0x3 0x0 | ||
| 422 | #define MX50_PAD_DISP_RS__SDMA_DEBUG_PC_10 0x154 0x434 0x000 0x6 0x0 | ||
| 423 | #define MX50_PAD_DISP_RS__USBPHY1_ENDSESSION 0x154 0x434 0x000 0x7 0x0 | ||
| 424 | #define MX50_PAD_DISP_CS__ELCDIF_CS 0x158 0x438 0x000 0x0 0x0 | ||
| 425 | #define MX50_PAD_DISP_CS__GPIO2_21 0x158 0x438 0x000 0x1 0x0 | ||
| 426 | #define MX50_PAD_DISP_CS__ELCDIF_HSYNC 0x158 0x438 0x6f8 0x2 0x1 | ||
| 427 | #define MX50_PAD_DISP_CS__EIM_WEIM_A_27 0x158 0x438 0x000 0x3 0x0 | ||
| 428 | #define MX50_PAD_DISP_CS__EIM_WEIM_CS_3 0x158 0x438 0x000 0x4 0x0 | ||
| 429 | #define MX50_PAD_DISP_CS__SDMA_DEBUG_PC_11 0x158 0x438 0x000 0x6 0x0 | ||
| 430 | #define MX50_PAD_DISP_CS__USBPHY1_IDDIG 0x158 0x438 0x000 0x7 0x0 | ||
| 431 | #define MX50_PAD_DISP_BUSY__ELCDIF_BUSY 0x15c 0x43c 0x6f8 0x0 0x2 | ||
| 432 | #define MX50_PAD_DISP_BUSY__GPIO2_18 0x15c 0x43c 0x000 0x1 0x0 | ||
| 433 | #define MX50_PAD_DISP_BUSY__EIM_WEIM_CS_3 0x15c 0x43c 0x000 0x4 0x0 | ||
| 434 | #define MX50_PAD_DISP_BUSY__SDMA_DEBUG_PC_12 0x15c 0x43c 0x000 0x6 0x0 | ||
| 435 | #define MX50_PAD_DISP_BUSY__USBPHY2_HOSTDISCONNECT 0x15c 0x43c 0x000 0x7 0x0 | ||
| 436 | #define MX50_PAD_DISP_RESET__ELCDIF_RESET 0x160 0x440 0x000 0x0 0x0 | ||
| 437 | #define MX50_PAD_DISP_RESET__GPIO2_20 0x160 0x440 0x000 0x1 0x0 | ||
| 438 | #define MX50_PAD_DISP_RESET__EIM_WEIM_CS_3 0x160 0x440 0x000 0x4 0x0 | ||
| 439 | #define MX50_PAD_DISP_RESET__SDMA_DEBUG_PC_13 0x160 0x440 0x000 0x6 0x0 | ||
| 440 | #define MX50_PAD_DISP_RESET__USBPHY2_BISTOK 0x160 0x440 0x000 0x7 0x0 | ||
| 441 | #define MX50_PAD_SD3_CMD__ESDHC3_CMD 0x164 0x444 0x000 0x0 0x0 | ||
| 442 | #define MX50_PAD_SD3_CMD__GPIO5_18 0x164 0x444 0x000 0x1 0x0 | ||
| 443 | #define MX50_PAD_SD3_CMD__EIM_NANDF_WRN 0x164 0x444 0x000 0x2 0x0 | ||
| 444 | #define MX50_PAD_SD3_CMD__SSP_CMD 0x164 0x444 0x000 0x3 0x0 | ||
| 445 | #define MX50_PAD_SD3_CLK__ESDHC3_CLK 0x168 0x448 0x000 0x0 0x0 | ||
| 446 | #define MX50_PAD_SD3_CLK__GPIO5_19 0x168 0x448 0x000 0x1 0x0 | ||
| 447 | #define MX50_PAD_SD3_CLK__EIM_NANDF_RDN 0x168 0x448 0x000 0x2 0x0 | ||
| 448 | #define MX50_PAD_SD3_CLK__SSP_CLK 0x168 0x448 0x000 0x3 0x0 | ||
| 449 | #define MX50_PAD_SD3_D0__ESDHC3_DAT0 0x16c 0x44c 0x000 0x0 0x0 | ||
| 450 | #define MX50_PAD_SD3_D0__GPIO5_20 0x16c 0x44c 0x000 0x1 0x0 | ||
| 451 | #define MX50_PAD_SD3_D0__EIM_NANDF_D_4 0x16c 0x44c 0x000 0x2 0x0 | ||
| 452 | #define MX50_PAD_SD3_D0__SSP_D0 0x16c 0x44c 0x000 0x3 0x0 | ||
| 453 | #define MX50_PAD_SD3_D0__CCM_PLL1_BYP 0x16c 0x44c 0x6dc 0x7 0x1 | ||
| 454 | #define MX50_PAD_SD3_D1__ESDHC3_DAT1 0x170 0x450 0x000 0x0 0x0 | ||
| 455 | #define MX50_PAD_SD3_D1__GPIO5_21 0x170 0x450 0x000 0x1 0x0 | ||
| 456 | #define MX50_PAD_SD3_D1__EIM_NANDF_D_5 0x170 0x450 0x000 0x2 0x0 | ||
| 457 | #define MX50_PAD_SD3_D1__SSP_D1 0x170 0x450 0x000 0x3 0x0 | ||
| 458 | #define MX50_PAD_SD3_D1__CCM_PLL2_BYP 0x170 0x450 0x000 0x7 0x0 | ||
| 459 | #define MX50_PAD_SD3_D2__ESDHC3_DAT2 0x174 0x454 0x000 0x0 0x0 | ||
| 460 | #define MX50_PAD_SD3_D2__GPIO5_22 0x174 0x454 0x000 0x1 0x0 | ||
| 461 | #define MX50_PAD_SD3_D2__EIM_NANDF_D_6 0x174 0x454 0x000 0x2 0x0 | ||
| 462 | #define MX50_PAD_SD3_D2__SSP_D2 0x174 0x454 0x000 0x3 0x0 | ||
| 463 | #define MX50_PAD_SD3_D2__CCM_PLL3_BYP 0x174 0x454 0x6e4 0x7 0x1 | ||
| 464 | #define MX50_PAD_SD3_D3__ESDHC3_DAT3 0x178 0x458 0x000 0x0 0x0 | ||
| 465 | #define MX50_PAD_SD3_D3__GPIO5_23 0x178 0x458 0x000 0x1 0x0 | ||
| 466 | #define MX50_PAD_SD3_D3__EIM_NANDF_D_7 0x178 0x458 0x000 0x2 0x0 | ||
| 467 | #define MX50_PAD_SD3_D3__SSP_D3 0x178 0x458 0x000 0x3 0x0 | ||
| 468 | #define MX50_PAD_SD3_D4__ESDHC3_DAT4 0x17c 0x45c 0x000 0x0 0x0 | ||
| 469 | #define MX50_PAD_SD3_D4__GPIO5_24 0x17c 0x45c 0x000 0x1 0x0 | ||
| 470 | #define MX50_PAD_SD3_D4__EIM_NANDF_D_0 0x17c 0x45c 0x000 0x2 0x0 | ||
| 471 | #define MX50_PAD_SD3_D4__SSP_D4 0x17c 0x45c 0x000 0x3 0x0 | ||
| 472 | #define MX50_PAD_SD3_D5__ESDHC3_DAT5 0x180 0x460 0x000 0x0 0x0 | ||
| 473 | #define MX50_PAD_SD3_D5__GPIO5_25 0x180 0x460 0x000 0x1 0x0 | ||
| 474 | #define MX50_PAD_SD3_D5__EIM_NANDF_D_1 0x180 0x460 0x000 0x2 0x0 | ||
| 475 | #define MX50_PAD_SD3_D5__SSP_D5 0x180 0x460 0x000 0x3 0x0 | ||
| 476 | #define MX50_PAD_SD3_D6__ESDHC3_DAT6 0x184 0x464 0x000 0x0 0x0 | ||
| 477 | #define MX50_PAD_SD3_D6__GPIO5_26 0x184 0x464 0x000 0x1 0x0 | ||
| 478 | #define MX50_PAD_SD3_D6__EIM_NANDF_D_2 0x184 0x464 0x000 0x2 0x0 | ||
| 479 | #define MX50_PAD_SD3_D6__SSP_D6 0x184 0x464 0x000 0x3 0x0 | ||
| 480 | #define MX50_PAD_SD3_D7__ESDHC3_DAT7 0x188 0x468 0x000 0x0 0x0 | ||
| 481 | #define MX50_PAD_SD3_D7__GPIO5_27 0x188 0x468 0x000 0x1 0x0 | ||
| 482 | #define MX50_PAD_SD3_D7__EIM_NANDF_D_3 0x188 0x468 0x000 0x2 0x0 | ||
| 483 | #define MX50_PAD_SD3_D7__SSP_D7 0x188 0x468 0x000 0x3 0x0 | ||
| 484 | #define MX50_PAD_SD3_WP__ESDHC3_WP 0x18c 0x46C 0x000 0x0 0x0 | ||
| 485 | #define MX50_PAD_SD3_WP__GPIO5_28 0x18c 0x46C 0x000 0x1 0x0 | ||
| 486 | #define MX50_PAD_SD3_WP__EIM_NANDF_RESETN 0x18c 0x46C 0x000 0x2 0x0 | ||
| 487 | #define MX50_PAD_SD3_WP__SSP_CD 0x18c 0x46C 0x000 0x3 0x0 | ||
| 488 | #define MX50_PAD_SD3_WP__ESDHC4_LCTL 0x18c 0x46C 0x000 0x4 0x0 | ||
| 489 | #define MX50_PAD_SD3_WP__EIM_WEIM_CS_3 0x18c 0x46C 0x000 0x5 0x0 | ||
| 490 | #define MX50_PAD_DISP_D8__ELCDIF_DAT_8 0x190 0x470 0x71c 0x0 0x0 | ||
| 491 | #define MX50_PAD_DISP_D8__GPIO2_8 0x190 0x470 0x000 0x1 0x0 | ||
| 492 | #define MX50_PAD_DISP_D8__EIM_NANDF_CLE 0x190 0x470 0x000 0x2 0x0 | ||
| 493 | #define MX50_PAD_DISP_D8__ESDHC1_LCTL 0x190 0x470 0x000 0x3 0x0 | ||
| 494 | #define MX50_PAD_DISP_D8__ESDHC4_CMD 0x190 0x470 0x74c 0x4 0x2 | ||
| 495 | #define MX50_PAD_DISP_D8__KPP_COL_4 0x190 0x470 0x790 0x5 0x1 | ||
| 496 | #define MX50_PAD_DISP_D8__FEC_TX_CLK 0x190 0x470 0x78c 0x6 0x1 | ||
| 497 | #define MX50_PAD_DISP_D8__USBPHY1_DATAOUT_0 0x190 0x470 0x000 0x7 0x0 | ||
| 498 | #define MX50_PAD_DISP_D9__ELCDIF_DAT_9 0x194 0x474 0x720 0x0 0x0 | ||
| 499 | #define MX50_PAD_DISP_D9__GPIO2_9 0x194 0x474 0x000 0x1 0x0 | ||
| 500 | #define MX50_PAD_DISP_D9__EIM_NANDF_ALE 0x194 0x474 0x000 0x2 0x0 | ||
| 501 | #define MX50_PAD_DISP_D9__ESDHC2_LCTL 0x194 0x474 0x000 0x3 0x0 | ||
| 502 | #define MX50_PAD_DISP_D9__ESDHC4_CLK 0x194 0x474 0x748 0x4 0x2 | ||
| 503 | #define MX50_PAD_DISP_D9__KPP_ROW_4 0x194 0x474 0x7a0 0x5 0x1 | ||
| 504 | #define MX50_PAD_DISP_D9__FEC_RX_ER 0x194 0x474 0x788 0x6 0x1 | ||
| 505 | #define MX50_PAD_DISP_D9__USBPHY1_DATAOUT_1 0x194 0x474 0x000 0x7 0x0 | ||
| 506 | #define MX50_PAD_DISP_D10__ELCDIF_DAT_10 0x198 0x478 0x724 0x0 0x0 | ||
| 507 | #define MX50_PAD_DISP_D10__GPIO2_10 0x198 0x478 0x000 0x1 0x0 | ||
| 508 | #define MX50_PAD_DISP_D10__EIM_NANDF_CEN_0 0x198 0x478 0x000 0x2 0x0 | ||
| 509 | #define MX50_PAD_DISP_D10__ESDHC3_LCTL 0x198 0x478 0x000 0x3 0x0 | ||
| 510 | #define MX50_PAD_DISP_D10__ESDHC4_DAT0 0x198 0x478 0x000 0x4 0x0 | ||
| 511 | #define MX50_PAD_DISP_D10__KPP_COL_5 0x198 0x478 0x794 0x5 0x1 | ||
| 512 | #define MX50_PAD_DISP_D10__FEC_RX_DV 0x198 0x478 0x784 0x6 0x1 | ||
| 513 | #define MX50_PAD_DISP_D10__USBPHY1_DATAOUT_2 0x198 0x478 0x000 0x7 0x0 | ||
| 514 | #define MX50_PAD_DISP_D11__ELCDIF_DAT_11 0x19c 0x47c 0x728 0x0 0x0 | ||
| 515 | #define MX50_PAD_DISP_D11__GPIO2_11 0x19c 0x47c 0x000 0x1 0x0 | ||
| 516 | #define MX50_PAD_DISP_D11__EIM_NANDF_CEN_1 0x19c 0x47c 0x000 0x2 0x0 | ||
| 517 | #define MX50_PAD_DISP_D11__ESDHC4_DAT1 0x19c 0x47c 0x754 0x4 0x1 | ||
| 518 | #define MX50_PAD_DISP_D11__KPP_ROW_5 0x19c 0x47c 0x7a4 0x5 0x1 | ||
| 519 | #define MX50_PAD_DISP_D11__FEC_RDATA_1 0x19c 0x47c 0x77c 0x6 0x1 | ||
| 520 | #define MX50_PAD_DISP_D11__USBPHY1_DATAOUT_3 0x19c 0x47c 0x000 0x7 0x0 | ||
| 521 | #define MX50_PAD_DISP_D12__ELCDIF_DAT_12 0x1a0 0x480 0x72c 0x0 0x0 | ||
| 522 | #define MX50_PAD_DISP_D12__GPIO2_12 0x1a0 0x480 0x000 0x1 0x0 | ||
| 523 | #define MX50_PAD_DISP_D12__EIM_NANDF_CEN_2 0x1a0 0x480 0x000 0x2 0x0 | ||
| 524 | #define MX50_PAD_DISP_D12__ESDHC1_CD 0x1a0 0x480 0x000 0x3 0x0 | ||
| 525 | #define MX50_PAD_DISP_D12__ESDHC4_DAT2 0x1a0 0x480 0x758 0x4 0x1 | ||
| 526 | #define MX50_PAD_DISP_D12__KPP_COL_6 0x1a0 0x480 0x798 0x5 0x1 | ||
| 527 | #define MX50_PAD_DISP_D12__FEC_RDATA_0 0x1a0 0x480 0x778 0x6 0x1 | ||
| 528 | #define MX50_PAD_DISP_D12__USBPHY1_DATAOUT_4 0x1a0 0x480 0x000 0x7 0x0 | ||
| 529 | #define MX50_PAD_DISP_D13__ELCDIF_DAT_13 0x1a4 0x484 0x730 0x0 0x0 | ||
| 530 | #define MX50_PAD_DISP_D13__GPIO2_13 0x1a4 0x484 0x000 0x1 0x0 | ||
| 531 | #define MX50_PAD_DISP_D13__EIM_NANDF_CEN_3 0x1a4 0x484 0x000 0x2 0x0 | ||
| 532 | #define MX50_PAD_DISP_D13__ESDHC3_CD 0x1a4 0x484 0x000 0x3 0x0 | ||
| 533 | #define MX50_PAD_DISP_D13__ESDHC4_DAT3 0x1a4 0x484 0x75c 0x4 0x1 | ||
| 534 | #define MX50_PAD_DISP_D13__KPP_ROW_6 0x1a4 0x484 0x7a8 0x5 0x1 | ||
| 535 | #define MX50_PAD_DISP_D13__FEC_TX_EN 0x1a4 0x484 0x000 0x6 0x0 | ||
| 536 | #define MX50_PAD_DISP_D13__USBPHY1_DATAOUT_5 0x1a4 0x484 0x000 0x7 0x0 | ||
| 537 | #define MX50_PAD_DISP_D14__ELCDIF_DAT_14 0x1a8 0x488 0x734 0x0 0x0 | ||
| 538 | #define MX50_PAD_DISP_D14__GPIO2_14 0x1a8 0x488 0x000 0x1 0x0 | ||
| 539 | #define MX50_PAD_DISP_D14__EIM_NANDF_READY0 0x1a8 0x488 0x7b4 0x2 0x1 | ||
| 540 | #define MX50_PAD_DISP_D14__ESDHC1_WP 0x1a8 0x488 0x000 0x3 0x0 | ||
| 541 | #define MX50_PAD_DISP_D14__ESDHC4_WP 0x1a8 0x488 0x000 0x4 0x0 | ||
| 542 | #define MX50_PAD_DISP_D14__KPP_COL_7 0x1a8 0x488 0x79c 0x5 0x1 | ||
| 543 | #define MX50_PAD_DISP_D14__FEC_TDATA_1 0x1a8 0x488 0x000 0x6 0x0 | ||
| 544 | #define MX50_PAD_DISP_D14__USBPHY1_DATAOUT_6 0x1a8 0x488 0x000 0x7 0x0 | ||
| 545 | #define MX50_PAD_DISP_D15__ELCDIF_DAT_15 0x1ac 0x48c 0x738 0x0 0x0 | ||
| 546 | #define MX50_PAD_DISP_D15__GPIO2_15 0x1ac 0x48c 0x000 0x1 0x0 | ||
| 547 | #define MX50_PAD_DISP_D15__EIM_NANDF_DQS 0x1ac 0x48c 0x7b0 0x2 0x1 | ||
| 548 | #define MX50_PAD_DISP_D15__ESDHC3_RST 0x1ac 0x48c 0x000 0x3 0x0 | ||
| 549 | #define MX50_PAD_DISP_D15__ESDHC4_CD 0x1ac 0x48c 0x000 0x4 0x0 | ||
| 550 | #define MX50_PAD_DISP_D15__KPP_ROW_7 0x1ac 0x48c 0x7ac 0x5 0x1 | ||
| 551 | #define MX50_PAD_DISP_D15__FEC_TDATA_0 0x1ac 0x48c 0x000 0x6 0x0 | ||
| 552 | #define MX50_PAD_DISP_D15__USBPHY1_DATAOUT_7 0x1ac 0x48c 0x000 0x7 0x0 | ||
| 553 | #define MX50_PAD_EPDC_D0__EPDC_SDDO_0 0x1b0 0x54c 0x000 0x0 0x0 | ||
| 554 | #define MX50_PAD_EPDC_D0__GPIO3_0 0x1b0 0x54c 0x000 0x1 0x0 | ||
| 555 | #define MX50_PAD_EPDC_D0__EIM_WEIM_D_0 0x1b0 0x54c 0x7ec 0x2 0x1 | ||
| 556 | #define MX50_PAD_EPDC_D0__ELCDIF_RS 0x1b0 0x54c 0x000 0x3 0x0 | ||
| 557 | #define MX50_PAD_EPDC_D0__ELCDIF_DOTCLK 0x1b0 0x54c 0x000 0x4 0x0 | ||
| 558 | #define MX50_PAD_EPDC_D0__SDMA_DEBUG_EVT_CHN_LINES_0 0x1b0 0x54c 0x000 0x6 0x0 | ||
| 559 | #define MX50_PAD_EPDC_D0__USBPHY2_DATAOUT_0 0x1b0 0x54c 0x000 0x7 0x0 | ||
| 560 | #define MX50_PAD_EPDC_D1__EPDC_SDDO_1 0x1b4 0x550 0x000 0x0 0x0 | ||
| 561 | #define MX50_PAD_EPDC_D1__GPIO3_1 0x1b4 0x550 0x000 0x1 0x0 | ||
| 562 | #define MX50_PAD_EPDC_D1__EIM_WEIM_D_1 0x1b4 0x550 0x7f0 0x2 0x1 | ||
| 563 | #define MX50_PAD_EPDC_D1__ELCDIF_CS 0x1b4 0x550 0x000 0x3 0x0 | ||
| 564 | #define MX50_PAD_EPDC_D1__ELCDIF_ENABLE 0x1b4 0x550 0x000 0x4 0x0 | ||
| 565 | #define MX50_PAD_EPDC_D1__SDMA_DEBUG_EVT_CHN_LINES_1 0x1b4 0x550 0x000 0x6 0x0 | ||
| 566 | #define MX50_PAD_EPDC_D1__USBPHY2_DATAOUT_1 0x1b4 0x550 0x000 0x7 0x0 | ||
| 567 | #define MX50_PAD_EPDC_D2__EPDC_SDDO_2 0x1b8 0x554 0x000 0x0 0x0 | ||
| 568 | #define MX50_PAD_EPDC_D2__GPIO3_2 0x1b8 0x554 0x000 0x1 0x0 | ||
| 569 | #define MX50_PAD_EPDC_D2__EIM_WEIM_D_2 0x1b8 0x554 0x7f4 0x2 0x1 | ||
| 570 | #define MX50_PAD_EPDC_D2__ELCDIF_WR_RWN 0x1b8 0x554 0x000 0x3 0x0 | ||
| 571 | #define MX50_PAD_EPDC_D2__ELCDIF_VSYNC 0x1b8 0x554 0x73c 0x4 0x2 | ||
| 572 | #define MX50_PAD_EPDC_D2__SDMA_DEBUG_EVT_CHN_LINES_2 0x1b8 0x554 0x000 0x6 0x0 | ||
| 573 | #define MX50_PAD_EPDC_D2__USBPHY2_DATAOUT_2 0x1b8 0x554 0x000 0x7 0x0 | ||
| 574 | #define MX50_PAD_EPDC_D3__EPDC_SDDO_3 0x1bc 0x558 0x000 0x0 0x0 | ||
| 575 | #define MX50_PAD_EPDC_D3__GPIO3_3 0x1bc 0x558 0x000 0x1 0x0 | ||
| 576 | #define MX50_PAD_EPDC_D3__EIM_WEIM_D_3 0x1bc 0x558 0x7f8 0x2 0x1 | ||
| 577 | #define MX50_PAD_EPDC_D3__ELCDIF_RD_E 0x1bc 0x558 0x000 0x3 0x0 | ||
| 578 | #define MX50_PAD_EPDC_D3__ELCDIF_HSYNC 0x1bc 0x558 0x6f8 0x4 0x3 | ||
| 579 | #define MX50_PAD_EPDC_D3__SDMA_DEBUG_EVT_CHN_LINES_3 0x1bc 0x558 0x000 0x6 0x0 | ||
| 580 | #define MX50_PAD_EPDC_D3__USBPHY2_DATAOUT_3 0x1bc 0x558 0x000 0x7 0x0 | ||
| 581 | #define MX50_PAD_EPDC_D4__EPDC_SDDO_4 0x1c0 0x55c 0x000 0x0 0x0 | ||
| 582 | #define MX50_PAD_EPDC_D4__GPIO3_4 0x1c0 0x55c 0x000 0x1 0x0 | ||
| 583 | #define MX50_PAD_EPDC_D4__EIM_WEIM_D_4 0x1c0 0x55c 0x7fc 0x2 0x1 | ||
| 584 | #define MX50_PAD_EPDC_D4__SDMA_DEBUG_EVT_CHN_LINES_4 0x1c0 0x55c 0x000 0x6 0x0 | ||
| 585 | #define MX50_PAD_EPDC_D4__USBPHY2_DATAOUT_4 0x1c0 0x55c 0x000 0x7 0x0 | ||
| 586 | #define MX50_PAD_EPDC_D5__EPDC_SDDO_5 0x1c4 0x560 0x000 0x0 0x0 | ||
| 587 | #define MX50_PAD_EPDC_D5__GPIO3_5 0x1c4 0x560 0x000 0x1 0x0 | ||
| 588 | #define MX50_PAD_EPDC_D5__EIM_WEIM_D_5 0x1c4 0x560 0x800 0x2 0x1 | ||
| 589 | #define MX50_PAD_EPDC_D5__SDMA_DEBUG_EVT_CHN_LINES_5 0x1c4 0x560 0x000 0x6 0x0 | ||
| 590 | #define MX50_PAD_EPDC_D5__USBPHY2_DATAOUT_5 0x1c4 0x560 0x000 0x7 0x0 | ||
| 591 | #define MX50_PAD_EPDC_D6__EPDC_SDDO_6 0x1c8 0x564 0x000 0x0 0x0 | ||
| 592 | #define MX50_PAD_EPDC_D6__GPIO3_6 0x1c8 0x564 0x000 0x1 0x0 | ||
| 593 | #define MX50_PAD_EPDC_D6__EIM_WEIM_D_6 0x1c8 0x564 0x804 0x2 0x1 | ||
| 594 | #define MX50_PAD_EPDC_D6__SDMA_DEBUG_EVT_CHN_LINES_6 0x1c8 0x564 0x000 0x6 0x0 | ||
| 595 | #define MX50_PAD_EPDC_D6__USBPHY2_DATAOUT_6 0x1c8 0x564 0x000 0x7 0x0 | ||
| 596 | #define MX50_PAD_EPDC_D7__EPDC_SDDO_7 0x1cc 0x568 0x000 0x0 0x0 | ||
| 597 | #define MX50_PAD_EPDC_D7__GPIO3_7 0x1cc 0x568 0x000 0x1 0x0 | ||
| 598 | #define MX50_PAD_EPDC_D7__EIM_WEIM_D_7 0x1cc 0x568 0x808 0x2 0x1 | ||
| 599 | #define MX50_PAD_EPDC_D7__SDMA_DEBUG_EVT_CHN_LINES_7 0x1cc 0x568 0x000 0x6 0x0 | ||
| 600 | #define MX50_PAD_EPDC_D7__USBPHY2_DATAOUT_7 0x1cc 0x568 0x000 0x7 0x0 | ||
| 601 | #define MX50_PAD_EPDC_D8__EPDC_SDDO_8 0x1d0 0x56c 0x000 0x0 0x0 | ||
| 602 | #define MX50_PAD_EPDC_D8__GPIO3_8 0x1d0 0x56c 0x000 0x1 0x0 | ||
| 603 | #define MX50_PAD_EPDC_D8__EIM_WEIM_D_8 0x1d0 0x56c 0x80c 0x2 0x2 | ||
| 604 | #define MX50_PAD_EPDC_D8__ELCDIF_DAT_24 0x1d0 0x56c 0x000 0x3 0x0 | ||
| 605 | #define MX50_PAD_EPDC_D8__SDMA_DEBUG_MATCHED_DMBUS 0x1d0 0x56c 0x000 0x6 0x0 | ||
| 606 | #define MX50_PAD_EPDC_D8__USBPHY2_VSTATUS_0 0x1d0 0x56c 0x000 0x7 0x0 | ||
| 607 | #define MX50_PAD_EPDC_D9__EPDC_SDDO_9 0x1d4 0x570 0x000 0x0 0x0 | ||
| 608 | #define MX50_PAD_EPDC_D9__GPIO3_9 0x1d4 0x570 0x000 0x1 0x0 | ||
| 609 | #define MX50_PAD_EPDC_D9__EIM_WEIM_D_9 0x1d4 0x570 0x810 0x2 0x2 | ||
| 610 | #define MX50_PAD_EPDC_D9__ELCDIF_DAT_25 0x1d4 0x570 0x000 0x3 0x0 | ||
| 611 | #define MX50_PAD_EPDC_D9__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x1d4 0x570 0x000 0x6 0x0 | ||
| 612 | #define MX50_PAD_EPDC_D9__USBPHY2_VSTATUS_1 0x1d4 0x570 0x000 0x7 0x0 | ||
| 613 | #define MX50_PAD_EPDC_D10__EPDC_SDDO_10 0x1d8 0x574 0x000 0x0 0x0 | ||
| 614 | #define MX50_PAD_EPDC_D10__GPIO3_10 0x1d8 0x574 0x000 0x1 0x0 | ||
| 615 | #define MX50_PAD_EPDC_D10__EIM_WEIM_D_10 0x1d8 0x574 0x814 0x2 0x2 | ||
| 616 | #define MX50_PAD_EPDC_D10__ELCDIF_DAT_26 0x1d8 0x574 0x000 0x3 0x0 | ||
| 617 | #define MX50_PAD_EPDC_D10__SDMA_DEBUG_EVENT_CHANNEL_0 0x1d8 0x574 0x000 0x6 0x0 | ||
| 618 | #define MX50_PAD_EPDC_D10__USBPHY2_VSTATUS_2 0x1d8 0x574 0x000 0x7 0x0 | ||
| 619 | #define MX50_PAD_EPDC_D11__EPDC_SDDO_11 0x1dc 0x578 0x000 0x0 0x0 | ||
| 620 | #define MX50_PAD_EPDC_D11__GPIO3_11 0x1dc 0x578 0x000 0x1 0x0 | ||
| 621 | #define MX50_PAD_EPDC_D11__EIM_WEIM_D_11 0x1dc 0x578 0x818 0x2 0x2 | ||
| 622 | #define MX50_PAD_EPDC_D11__ELCDIF_DAT_27 0x1dc 0x578 0x000 0x3 0x0 | ||
| 623 | #define MX50_PAD_EPDC_D11__SDMA_DEBUG_EVENT_CHANNEL_1 0x1dc 0x578 0x000 0x6 0x0 | ||
| 624 | #define MX50_PAD_EPDC_D11__USBPHY2_VSTATUS_3 0x1dc 0x578 0x000 0x7 0x0 | ||
| 625 | #define MX50_PAD_EPDC_D12__EPDC_SDDO_12 0x1e0 0x57c 0x000 0x0 0x0 | ||
| 626 | #define MX50_PAD_EPDC_D12__GPIO3_12 0x1e0 0x57c 0x000 0x1 0x0 | ||
| 627 | #define MX50_PAD_EPDC_D12__EIM_WEIM_D_12 0x1e0 0x57c 0x81c 0x2 0x1 | ||
| 628 | #define MX50_PAD_EPDC_D12__ELCDIF_DAT_28 0x1e0 0x57c 0x000 0x3 0x0 | ||
| 629 | #define MX50_PAD_EPDC_D12__SDMA_DEBUG_EVENT_CHANNEL_2 0x1e0 0x57c 0x000 0x6 0x0 | ||
| 630 | #define MX50_PAD_EPDC_D12__USBPHY2_VSTATUS_4 0x1e0 0x57c 0x000 0x7 0x0 | ||
| 631 | #define MX50_PAD_EPDC_D13__EPDC_SDDO_13 0x1e4 0x580 0x000 0x0 0x0 | ||
| 632 | #define MX50_PAD_EPDC_D13__GPIO3_13 0x1e4 0x580 0x000 0x1 0x0 | ||
| 633 | #define MX50_PAD_EPDC_D13__EIM_WEIM_D_13 0x1e4 0x580 0x820 0x2 0x1 | ||
| 634 | #define MX50_PAD_EPDC_D13__ELCDIF_DAT_29 0x1e4 0x580 0x000 0x3 0x0 | ||
| 635 | #define MX50_PAD_EPDC_D13__SDMA_DEBUG_EVENT_CHANNEL_3 0x1e4 0x580 0x000 0x6 0x0 | ||
| 636 | #define MX50_PAD_EPDC_D13__USBPHY2_VSTATUS_5 0x1e4 0x580 0x000 0x7 0x0 | ||
| 637 | #define MX50_PAD_EPDC_D14__EPDC_SDDO_14 0x1e8 0x584 0x000 0x0 0x0 | ||
| 638 | #define MX50_PAD_EPDC_D14__GPIO3_14 0x1e8 0x584 0x000 0x1 0x0 | ||
| 639 | #define MX50_PAD_EPDC_D14__EIM_WEIM_D_14 0x1e8 0x584 0x824 0x2 0x1 | ||
| 640 | #define MX50_PAD_EPDC_D14__ELCDIF_DAT_30 0x1e8 0x584 0x000 0x3 0x0 | ||
| 641 | #define MX50_PAD_EPDC_D14__AUDMUX_AUD6_TXD 0x1e8 0x584 0x000 0x4 0x0 | ||
| 642 | #define MX50_PAD_EPDC_D14__SDMA_DEBUG_EVENT_CHANNEL_4 0x1e8 0x584 0x000 0x6 0x0 | ||
| 643 | #define MX50_PAD_EPDC_D14__USBPHY2_VSTATUS_6 0x1e8 0x584 0x000 0x7 0x0 | ||
| 644 | #define MX50_PAD_EPDC_D15__EPDC_SDDO_15 0x1ec 0x588 0x000 0x0 0x0 | ||
| 645 | #define MX50_PAD_EPDC_D15__GPIO3_15 0x1ec 0x588 0x000 0x1 0x0 | ||
| 646 | #define MX50_PAD_EPDC_D15__EIM_WEIM_D_15 0x1ec 0x588 0x828 0x2 0x1 | ||
| 647 | #define MX50_PAD_EPDC_D15__ELCDIF_DAT_31 0x1ec 0x588 0x000 0x3 0x0 | ||
| 648 | #define MX50_PAD_EPDC_D15__AUDMUX_AUD6_TXC 0x1ec 0x588 0x000 0x4 0x0 | ||
| 649 | #define MX50_PAD_EPDC_D15__SDMA_DEBUG_EVENT_CHANNEL_5 0x1ec 0x588 0x000 0x6 0x0 | ||
| 650 | #define MX50_PAD_EPDC_D15__USBPHY2_VSTATUS_7 0x1ec 0x588 0x000 0x7 0x0 | ||
| 651 | #define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK 0x1f0 0x58c 0x000 0x0 0x0 | ||
| 652 | #define MX50_PAD_EPDC_GDCLK__GPIO3_16 0x1f0 0x58c 0x000 0x1 0x0 | ||
| 653 | #define MX50_PAD_EPDC_GDCLK__EIM_WEIM_D_16 0x1f0 0x58c 0x000 0x2 0x0 | ||
| 654 | #define MX50_PAD_EPDC_GDCLK__ELCDIF_DAT_16 0x1f0 0x58c 0x000 0x3 0x0 | ||
| 655 | #define MX50_PAD_EPDC_GDCLK__AUDMUX_AUD6_TXFS 0x1f0 0x58c 0x000 0x4 0x0 | ||
| 656 | #define MX50_PAD_EPDC_GDCLK__SDMA_DEBUG_CORE_STATE_0 0x1f0 0x58c 0x000 0x6 0x0 | ||
| 657 | #define MX50_PAD_EPDC_GDCLK__USBPHY2_BISTOK 0x1f0 0x58c 0x000 0x7 0x0 | ||
| 658 | #define MX50_PAD_EPDC_GDSP__EPCD_GDSP 0x1f4 0x590 0x000 0x0 0x0 | ||
| 659 | #define MX50_PAD_EPDC_GDSP__GPIO3_17 0x1f4 0x590 0x000 0x1 0x0 | ||
| 660 | #define MX50_PAD_EPDC_GDSP__EIM_WEIM_D_17 0x1f4 0x590 0x000 0x2 0x0 | ||
| 661 | #define MX50_PAD_EPDC_GDSP__ELCDIF_DAT_17 0x1f4 0x590 0x000 0x3 0x0 | ||
| 662 | #define MX50_PAD_EPDC_GDSP__AUDMUX_AUD6_RXD 0x1f4 0x590 0x000 0x4 0x0 | ||
| 663 | #define MX50_PAD_EPDC_GDSP__SDMA_DEBUG_CORE_STATE_1 0x1f4 0x590 0x000 0x6 0x0 | ||
| 664 | #define MX50_PAD_EPDC_GDSP__USBPHY2_BVALID 0x1f4 0x590 0x000 0x7 0x0 | ||
| 665 | #define MX50_PAD_EPDC_GDOE__EPCD_GDOE 0x1f8 0x594 0x000 0x0 0x0 | ||
| 666 | #define MX50_PAD_EPDC_GDOE__GPIO3_18 0x1f8 0x594 0x000 0x1 0x0 | ||
| 667 | #define MX50_PAD_EPDC_GDOE__EIM_WEIM_D_18 0x1f8 0x594 0x000 0x2 0x0 | ||
| 668 | #define MX50_PAD_EPDC_GDOE__ELCDIF_DAT_18 0x1f8 0x594 0x000 0x3 0x0 | ||
| 669 | #define MX50_PAD_EPDC_GDOE__AUDMUX_AUD6_RXC 0x1f8 0x594 0x000 0x4 0x0 | ||
| 670 | #define MX50_PAD_EPDC_GDOE__SDMA_DEBUG_CORE_STATE_2 0x1f8 0x594 0x000 0x6 0x0 | ||
| 671 | #define MX50_PAD_EPDC_GDOE__USBPHY2_ENDSESSION 0x1f8 0x594 0x000 0x7 0x0 | ||
| 672 | #define MX50_PAD_EPDC_GDRL__EPCD_GDRL 0x1fc 0x598 0x000 0x0 0x0 | ||
| 673 | #define MX50_PAD_EPDC_GDRL__GPIO3_19 0x1fc 0x598 0x000 0x1 0x0 | ||
| 674 | #define MX50_PAD_EPDC_GDRL__EIM_WEIM_D_19 0x1f8 0x598 0x000 0x2 0x0 | ||
| 675 | #define MX50_PAD_EPDC_GDRL__ELCDIF_DAT_19 0x1fc 0x598 0x000 0x3 0x0 | ||
| 676 | #define MX50_PAD_EPDC_GDRL__AUDMUX_AUD6_RXFS 0x1fc 0x598 0x000 0x4 0x0 | ||
| 677 | #define MX50_PAD_EPDC_GDRL__SDMA_DEBUG_CORE_STATE_3 0x1fc 0x598 0x000 0x6 0x0 | ||
| 678 | #define MX50_PAD_EPDC_GDRL__USBPHY2_IDDIG 0x1fc 0x598 0x000 0x7 0x0 | ||
| 679 | #define MX50_PAD_EPDC_SDCLK__EPCD_SDCLK 0x200 0x59c 0x000 0x0 0x0 | ||
| 680 | #define MX50_PAD_EPDC_SDCLK__GPIO3_20 0x200 0x59c 0x000 0x1 0x0 | ||
| 681 | #define MX50_PAD_EPDC_SDCLK__EIM_WEIM_D_20 0x200 0x59c 0x000 0x2 0x0 | ||
| 682 | #define MX50_PAD_EPDC_SDCLK__ELCDIF_DAT_20 0x200 0x59c 0x000 0x3 0x0 | ||
| 683 | #define MX50_PAD_EPDC_SDCLK__AUDMUX_AUD5_TXD 0x200 0x59c 0x000 0x4 0x0 | ||
| 684 | #define MX50_PAD_EPDC_SDCLK__SDMA_DEBUG_BUS_DEVICE_0 0x200 0x59c 0x000 0x6 0x0 | ||
| 685 | #define MX50_PAD_EPDC_SDCLK__USBPHY2_HOSTDISCONNECT 0x200 0x59c 0x000 0x7 0x0 | ||
| 686 | #define MX50_PAD_EPDC_SDOEZ__EPCD_SDOEZ 0x204 0x5a0 0x000 0x0 0x0 | ||
| 687 | #define MX50_PAD_EPDC_SDOEZ__GPIO3_21 0x204 0x5a0 0x000 0x1 0x0 | ||
| 688 | #define MX50_PAD_EPDC_SDOEZ__EIM_WEIM_D_21 0x204 0x5a0 0x000 0x2 0x0 | ||
| 689 | #define MX50_PAD_EPDC_SDOEZ__ELCDIF_DAT_21 0x204 0x5a0 0x000 0x3 0x0 | ||
| 690 | #define MX50_PAD_EPDC_SDOEZ__AUDMUX_AUD5_TXC 0x204 0x5a0 0x000 0x4 0x0 | ||
| 691 | #define MX50_PAD_EPDC_SDOEZ__SDMA_DEBUG_BUS_DEVICE_1 0x204 0x5a0 0x000 0x6 0x0 | ||
| 692 | #define MX50_PAD_EPDC_SDOEZ__USBPHY2_TXREADY 0x204 0x5a0 0x000 0x7 0x0 | ||
| 693 | #define MX50_PAD_EPDC_SDOED__EPCD_SDOED 0x208 0x5a4 0x000 0x0 0x0 | ||
| 694 | #define MX50_PAD_EPDC_SDOED__GPIO3_22 0x208 0x5a4 0x000 0x1 0x0 | ||
| 695 | #define MX50_PAD_EPDC_SDOED__EIM_WEIM_D_22 0x208 0x5a4 0x000 0x2 0x0 | ||
| 696 | #define MX50_PAD_EPDC_SDOED__ELCDIF_DAT_22 0x208 0x5a4 0x000 0x3 0x0 | ||
| 697 | #define MX50_PAD_EPDC_SDOED__AUDMUX_AUD5_TXFS 0x208 0x5a4 0x000 0x4 0x0 | ||
| 698 | #define MX50_PAD_EPDC_SDOED__SDMA_DEBUG_BUS_DEVICE_2 0x208 0x5a4 0x000 0x6 0x0 | ||
| 699 | #define MX50_PAD_EPDC_SDOED__USBPHY2_RXVALID 0x208 0x5a4 0x000 0x7 0x0 | ||
| 700 | #define MX50_PAD_EPDC_SDOE__EPCD_SDOE 0x20c 0x5a8 0x000 0x0 0x0 | ||
| 701 | #define MX50_PAD_EPDC_SDOE__GPIO3_23 0x20c 0x5a8 0x000 0x1 0x0 | ||
| 702 | #define MX50_PAD_EPDC_SDOE__EIM_WEIM_D_23 0x20c 0x5a8 0x000 0x2 0x0 | ||
| 703 | #define MX50_PAD_EPDC_SDOE__ELCDIF_DAT_23 0x20c 0x5a8 0x000 0x3 0x0 | ||
| 704 | #define MX50_PAD_EPDC_SDOE__AUDMUX_AUD5_RXD 0x20c 0x5a8 0x000 0x4 0x0 | ||
| 705 | #define MX50_PAD_EPDC_SDOE__SDMA_DEBUG_BUS_DEVICE_3 0x20c 0x5a8 0x000 0x6 0x0 | ||
| 706 | #define MX50_PAD_EPDC_SDOE__USBPHY2_RXACTIVE 0x20c 0x5a8 0x000 0x7 0x0 | ||
| 707 | #define MX50_PAD_EPDC_SDLE__EPCD_SDLE 0x210 0x5ac 0x000 0x0 0x0 | ||
| 708 | #define MX50_PAD_EPDC_SDLE__GPIO3_24 0x210 0x5ac 0x000 0x1 0x0 | ||
| 709 | #define MX50_PAD_EPDC_SDLE__EIM_WEIM_D_24 0x210 0x5ac 0x000 0x2 0x0 | ||
| 710 | #define MX50_PAD_EPDC_SDLE__ELCDIF_DAT_8 0x210 0x5ac 0x71c 0x3 0x1 | ||
| 711 | #define MX50_PAD_EPDC_SDLE__AUDMUX_AUD5_RXC 0x210 0x5ac 0x000 0x4 0x0 | ||
| 712 | #define MX50_PAD_EPDC_SDLE__SDMA_DEBUG_BUS_DEVICE_4 0x210 0x5ac 0x000 0x6 0x0 | ||
| 713 | #define MX50_PAD_EPDC_SDLE__USBPHY2_RXERROR 0x210 0x5ac 0x000 0x7 0x0 | ||
| 714 | #define MX50_PAD_EPDC_SDCLKN__EPCD_SDCLKN 0x214 0x5b0 0x000 0x0 0x0 | ||
| 715 | #define MX50_PAD_EPDC_SDCLKN__GPIO3_25 0x214 0x5b0 0x000 0x1 0x0 | ||
| 716 | #define MX50_PAD_EPDC_SDCLKN__EIM_WEIM_D_25 0x214 0x5b0 0x000 0x2 0x0 | ||
| 717 | #define MX50_PAD_EPDC_SDCLKN__ELCDIF_DAT_9 0x214 0x5b0 0x720 0x3 0x1 | ||
| 718 | #define MX50_PAD_EPDC_SDCLKN__AUDMUX_AUD5_RXFS 0x214 0x5b0 0x000 0x4 0x0 | ||
| 719 | #define MX50_PAD_EPDC_SDCLKN__SDMA_DEBUG_BUS_ERROR 0x214 0x5b0 0x000 0x6 0x0 | ||
| 720 | #define MX50_PAD_EPDC_SDCLKN__USBPHY2_SIECLOCK 0x214 0x5b0 0x000 0x7 0x0 | ||
| 721 | #define MX50_PAD_EPDC_SDSHR__EPCD_SDSHR 0x218 0x5b4 0x000 0x0 0x0 | ||
| 722 | #define MX50_PAD_EPDC_SDSHR__GPIO3_26 0x218 0x5b4 0x000 0x1 0x0 | ||
| 723 | #define MX50_PAD_EPDC_SDSHR__EIM_WEIM_D_26 0x218 0x5b4 0x000 0x2 0x0 | ||
| 724 | #define MX50_PAD_EPDC_SDSHR__ELCDIF_DAT_10 0x218 0x5b4 0x724 0x3 0x1 | ||
| 725 | #define MX50_PAD_EPDC_SDSHR__AUDMUX_AUD4_TXD 0x218 0x5b4 0x6c8 0x4 0x1 | ||
| 726 | #define MX50_PAD_EPDC_SDSHR__SDMA_DEBUG_BUS_RWB 0x218 0x5b4 0x000 0x6 0x0 | ||
| 727 | #define MX50_PAD_EPDC_SDSHR__USBPHY2_LINESTATE_0 0x218 0x5b4 0x000 0x7 0x0 | ||
| 728 | #define MX50_PAD_EPDC_PWRCOM__EPCD_PWRCOM 0x21c 0x5b8 0x000 0x0 0x0 | ||
| 729 | #define MX50_PAD_EPDC_PWRCOM__GPIO3_27 0x21c 0x5b8 0x000 0x1 0x0 | ||
| 730 | #define MX50_PAD_EPDC_PWRCOM__EIM_WEIM_D_27 0x21c 0x5b8 0x000 0x2 0x0 | ||
| 731 | #define MX50_PAD_EPDC_PWRCOM__ELCDIF_DAT_11 0x21c 0x5b8 0x728 0x3 0x1 | ||
| 732 | #define MX50_PAD_EPDC_PWRCOM__AUDMUX_AUD4_TXC 0x21c 0x5b8 0x6d4 0x4 0x1 | ||
| 733 | #define MX50_PAD_EPDC_PWRCOM__SDMA_DEBUG_CORE_RUN 0x21c 0x5b8 0x000 0x6 0x0 | ||
| 734 | #define MX50_PAD_EPDC_PWRCOM__USBPHY2_LINESTATE_1 0x21c 0x5b8 0x000 0x7 0x0 | ||
| 735 | #define MX50_PAD_EPDC_PWRSTAT__EPCD_PWRSTAT 0x220 0x5bc 0x000 0x0 0x0 | ||
| 736 | #define MX50_PAD_EPDC_PWRSTAT__GPIO3_28 0x220 0x5bc 0x000 0x1 0x0 | ||
| 737 | #define MX50_PAD_EPDC_PWRSTAT__EIM_WEIM_D_28 0x220 0x5bc 0x000 0x2 0x0 | ||
| 738 | #define MX50_PAD_EPDC_PWRSTAT__ELCDIF_DAT_12 0x220 0x5bc 0x72c 0x3 0x1 | ||
| 739 | #define MX50_PAD_EPDC_PWRSTAT__AUDMUX_AUD4_TXFS 0x220 0x5bc 0x6d8 0x4 0x1 | ||
| 740 | #define MX50_PAD_EPDC_PWRSTAT__SDMA_DEBUG_MODE 0x220 0x5bc 0x000 0x6 0x0 | ||
| 741 | #define MX50_PAD_EPDC_PWRSTAT__USBPHY2_VBUSVALID 0x220 0x5bc 0x000 0x7 0x0 | ||
| 742 | #define MX50_PAD_EPDC_PWRCTRL0__EPCD_PWRCTRL0 0x224 0x5c0 0x000 0x0 0x0 | ||
| 743 | #define MX50_PAD_EPDC_PWRCTRL0__GPIO3_29 0x224 0x5c0 0x000 0x1 0x0 | ||
| 744 | #define MX50_PAD_EPDC_PWRCTRL0__EIM_WEIM_D_29 0x224 0x5c0 0x000 0x2 0x0 | ||
| 745 | #define MX50_PAD_EPDC_PWRCTRL0__ELCDIF_DAT_13 0x224 0x5c0 0x730 0x3 0x1 | ||
| 746 | #define MX50_PAD_EPDC_PWRCTRL0__AUDMUX_AUD4_RXD 0x224 0x5c0 0x6c4 0x4 0x1 | ||
| 747 | #define MX50_PAD_EPDC_PWRCTRL0__SDMA_DEBUG_RTBUFFER_WRITE 0x224 0x5c0 0x000 0x6 0x0 | ||
| 748 | #define MX50_PAD_EPDC_PWRCTRL0__USBPHY2_AVALID 0x224 0x5c0 0x000 0x7 0x0 | ||
| 749 | #define MX50_PAD_EPDC_PWRCTRL1__EPCD_PWRCTRL1 0x228 0x5c4 0x000 0x0 0x0 | ||
| 750 | #define MX50_PAD_EPDC_PWRCTRL1__GPIO3_30 0x228 0x5c4 0x000 0x1 0x0 | ||
| 751 | #define MX50_PAD_EPDC_PWRCTRL1__EIM_WEIM_D_30 0x228 0x5c4 0x000 0x2 0x0 | ||
| 752 | #define MX50_PAD_EPDC_PWRCTRL1__ELCDIF_DAT_14 0x228 0x5c4 0x734 0x3 0x1 | ||
| 753 | #define MX50_PAD_EPDC_PWRCTRL1__AUDMUX_AUD4_RXC 0x228 0x5c4 0x6cc 0x4 0x1 | ||
| 754 | #define MX50_PAD_EPDC_PWRCTRL1__SDMA_DEBUG_YIELD 0x228 0x5c4 0x000 0x6 0x0 | ||
| 755 | #define MX50_PAD_EPDC_PWRCTRL1__USBPHY1_ONBIST 0x228 0x5c4 0x000 0x7 0x0 | ||
| 756 | #define MX50_PAD_EPDC_PWRCTRL2__EPCD_PWRCTRL2 0x22c 0x5c8 0x000 0x0 0x0 | ||
| 757 | #define MX50_PAD_EPDC_PWRCTRL2__GPIO3_31 0x22c 0x5c8 0x000 0x1 0x0 | ||
| 758 | #define MX50_PAD_EPDC_PWRCTRL2__EIM_WEIM_D_31 0x22c 0x5c8 0x000 0x2 0x0 | ||
| 759 | #define MX50_PAD_EPDC_PWRCTRL2__ELCDIF_DAT_15 0x22c 0x5c8 0x738 0x3 0x1 | ||
| 760 | #define MX50_PAD_EPDC_PWRCTRL2__AUDMUX_AUD4_RXFS 0x22c 0x5c8 0x6d0 0x4 0x1 | ||
| 761 | #define MX50_PAD_EPDC_PWRCTRL2__SDMA_EXT_EVENT_0 0x22c 0x5c8 0x7b8 0x6 0x1 | ||
| 762 | #define MX50_PAD_EPDC_PWRCTRL2__USBPHY2_ONBIST 0x22c 0x5c8 0x000 0x7 0x0 | ||
| 763 | #define MX50_PAD_EPDC_PWRCTRL3__EPCD_PWRCTRL3 0x230 0x5cc 0x000 0x0 0x0 | ||
| 764 | #define MX50_PAD_EPDC_PWRCTRL3__GPIO4_20 0x230 0x5cc 0x000 0x1 0x0 | ||
| 765 | #define MX50_PAD_EPDC_PWRCTRL3__EIM_WEIM_EB_2 0x230 0x5cc 0x000 0x2 0x0 | ||
| 766 | #define MX50_PAD_EPDC_PWRCTRL3__SDMA_EXT_EVENT_1 0x230 0x5cc 0x7bc 0x6 0x1 | ||
| 767 | #define MX50_PAD_EPDC_PWRCTRL3__USBPHY1_BISTOK 0x230 0x5cc 0x000 0x7 0x0 | ||
| 768 | #define MX50_PAD_EPDC_VCOM0__EPCD_VCOM_0 0x234 0x5d0 0x000 0x0 0x0 | ||
| 769 | #define MX50_PAD_EPDC_VCOM0__GPIO4_21 0x234 0x5d0 0x000 0x1 0x0 | ||
| 770 | #define MX50_PAD_EPDC_VCOM0__EIM_WEIM_EB_3 0x234 0x5d0 0x000 0x2 0x0 | ||
| 771 | #define MX50_PAD_EPDC_VCOM0__USBPHY2_BISTOK 0x234 0x5d0 0x000 0x7 0x0 | ||
| 772 | #define MX50_PAD_EPDC_VCOM1__EPCD_VCOM_1 0x238 0x5d4 0x000 0x0 0x0 | ||
| 773 | #define MX50_PAD_EPDC_VCOM1__GPIO4_22 0x238 0x5d4 0x000 0x1 0x0 | ||
| 774 | #define MX50_PAD_EPDC_VCOM1__EIM_WEIM_CS_3 0x238 0x5d4 0x000 0x2 0x0 | ||
| 775 | #define MX50_PAD_EPDC_BDR0__EPCD_BDR_0 0x23c 0x5d8 0x000 0x0 0x0 | ||
| 776 | #define MX50_PAD_EPDC_BDR0__GPIO4_23 0x23c 0x5d8 0x000 0x1 0x0 | ||
| 777 | #define MX50_PAD_EPDC_BDR0__ELCDIF_DAT_7 0x23c 0x5d8 0x718 0x3 0x1 | ||
| 778 | #define MX50_PAD_EPDC_BDR1__EPCD_BDR_1 0x240 0x5dc 0x000 0x0 0x0 | ||
| 779 | #define MX50_PAD_EPDC_BDR1__GPIO4_24 0x240 0x5dc 0x000 0x1 0x0 | ||
| 780 | #define MX50_PAD_EPDC_BDR1__ELCDIF_DAT_6 0x240 0x5dc 0x714 0x3 0x1 | ||
| 781 | #define MX50_PAD_EPDC_SDCE0__EPCD_SDCE_0 0x244 0x5e0 0x000 0x0 0x0 | ||
| 782 | #define MX50_PAD_EPDC_SDCE0__GPIO4_25 0x244 0x5e0 0x000 0x1 0x0 | ||
| 783 | #define MX50_PAD_EPDC_SDCE0__ELCDIF_DAT_5 0x244 0x5e0 0x710 0x3 0x1 | ||
| 784 | #define MX50_PAD_EPDC_SDCE1__EPCD_SDCE_1 0x248 0x5e4 0x000 0x0 0x0 | ||
| 785 | #define MX50_PAD_EPDC_SDCE1__GPIO4_26 0x248 0x5e4 0x000 0x1 0x0 | ||
| 786 | #define MX50_PAD_EPDC_SDCE1__ELCDIF_DAT_4 0x248 0x5e4 0x70c 0x3 0x0 | ||
| 787 | #define MX50_PAD_EPDC_SDCE2__EPCD_SDCE_2 0x24c 0x5e8 0x000 0x0 0x0 | ||
| 788 | #define MX50_PAD_EPDC_SDCE2__GPIO4_27 0x24c 0x5e8 0x000 0x1 0x0 | ||
| 789 | #define MX50_PAD_EPDC_SDCE2__ELCDIF_DAT_3 0x24c 0x5e8 0x708 0x3 0x1 | ||
| 790 | #define MX50_PAD_EPDC_SDCE3__EPCD_SDCE_3 0x250 0x5ec 0x000 0x0 0x0 | ||
| 791 | #define MX50_PAD_EPDC_SDCE3__GPIO4_28 0x250 0x5ec 0x000 0x1 0x0 | ||
| 792 | #define MX50_PAD_EPDC_SDCE3__ELCDIF_DAT_2 0x250 0x5ec 0x704 0x3 0x1 | ||
| 793 | #define MX50_PAD_EPDC_SDCE4__EPCD_SDCE_4 0x254 0x5f0 0x000 0x0 0x0 | ||
| 794 | #define MX50_PAD_EPDC_SDCE4__GPIO4_29 0x254 0x5f0 0x000 0x1 0x0 | ||
| 795 | #define MX50_PAD_EPDC_SDCE4__ELCDIF_DAT_1 0x254 0x5f0 0x700 0x3 0x1 | ||
| 796 | #define MX50_PAD_EPDC_SDCE5__EPCD_SDCE_5 0x258 0x5f4 0x000 0x0 0x0 | ||
| 797 | #define MX50_PAD_EPDC_SDCE5__GPIO4_30 0x258 0x5f4 0x000 0x1 0x0 | ||
| 798 | #define MX50_PAD_EPDC_SDCE5__ELCDIF_DAT_0 0x258 0x5f4 0x6fc 0x3 0x1 | ||
| 799 | #define MX50_PAD_EIM_DA0__EIM_WEIM_A_0 0x25c 0x5f8 0x000 0x0 0x0 | ||
| 800 | #define MX50_PAD_EIM_DA0__GPIO1_0 0x25c 0x5f8 0x000 0x1 0x0 | ||
| 801 | #define MX50_PAD_EIM_DA0__KPP_COL_4 0x25c 0x5f8 0x790 0x3 0x2 | ||
| 802 | #define MX50_PAD_EIM_DA0__TPIU_TRACE_0 0x25c 0x5f8 0x000 0x6 0x0 | ||
| 803 | #define MX50_PAD_EIM_DA0__SRC_BT_CFG1_0 0x25c 0x5f8 0x000 0x7 0x0 | ||
| 804 | #define MX50_PAD_EIM_DA1__EIM_WEIM_A_1 0x260 0x5fc 0x000 0x0 0x0 | ||
| 805 | #define MX50_PAD_EIM_DA1__GPIO1_1 0x260 0x5fc 0x000 0x1 0x0 | ||
| 806 | #define MX50_PAD_EIM_DA1__KPP_ROW_4 0x260 0x5fc 0x7a0 0x3 0x2 | ||
| 807 | #define MX50_PAD_EIM_DA1__TPIU_TRACE_1 0x260 0x5fc 0x000 0x6 0x0 | ||
| 808 | #define MX50_PAD_EIM_DA1__SRC_BT_CFG1_1 0x260 0x5fc 0x000 0x7 0x0 | ||
| 809 | #define MX50_PAD_EIM_DA2__EIM_WEIM_A_2 0x264 0x600 0x000 0x0 0x0 | ||
| 810 | #define MX50_PAD_EIM_DA2__GPIO1_2 0x264 0x600 0x000 0x1 0x0 | ||
| 811 | #define MX50_PAD_EIM_DA2__KPP_COL_5 0x264 0x600 0x794 0x3 0x2 | ||
| 812 | #define MX50_PAD_EIM_DA2__TPIU_TRACE_2 0x264 0x600 0x000 0x6 0x0 | ||
| 813 | #define MX50_PAD_EIM_DA2__SRC_BT_CFG1_2 0x264 0x600 0x000 0x7 0x0 | ||
| 814 | #define MX50_PAD_EIM_DA3__EIM_WEIM_A_3 0x268 0x604 0x000 0x0 0x0 | ||
| 815 | #define MX50_PAD_EIM_DA3__GPIO1_3 0x268 0x604 0x000 0x1 0x0 | ||
| 816 | #define MX50_PAD_EIM_DA3__KPP_ROW_5 0x268 0x604 0x7a4 0x3 0x2 | ||
| 817 | #define MX50_PAD_EIM_DA3__TPIU_TRACE_3 0x268 0x604 0x000 0x6 0x0 | ||
| 818 | #define MX50_PAD_EIM_DA3__SRC_BT_CFG1_3 0x268 0x604 0x000 0x7 0x0 | ||
| 819 | #define MX50_PAD_EIM_DA4__EIM_WEIM_A_4 0x26c 0x608 0x000 0x0 0x0 | ||
| 820 | #define MX50_PAD_EIM_DA4__GPIO1_4 0x26c 0x608 0x000 0x1 0x0 | ||
| 821 | #define MX50_PAD_EIM_DA4__KPP_COL_6 0x26c 0x608 0x798 0x3 0x2 | ||
| 822 | #define MX50_PAD_EIM_DA4__TPIU_TRACE_4 0x26c 0x608 0x000 0x6 0x0 | ||
| 823 | #define MX50_PAD_EIM_DA4__SRC_BT_CFG1_4 0x26c 0x608 0x000 0x7 0x0 | ||
| 824 | #define MX50_PAD_EIM_DA5__EIM_WEIM_A_5 0x270 0x60c 0x000 0x0 0x0 | ||
| 825 | #define MX50_PAD_EIM_DA5__GPIO1_5 0x270 0x60c 0x000 0x1 0x0 | ||
| 826 | #define MX50_PAD_EIM_DA5__KPP_ROW_6 0x270 0x60c 0x7a8 0x3 0x2 | ||
| 827 | #define MX50_PAD_EIM_DA5__TPIU_TRACE_5 0x270 0x60c 0x000 0x6 0x0 | ||
| 828 | #define MX50_PAD_EIM_DA5__SRC_BT_CFG1_5 0x270 0x60c 0x000 0x7 0x0 | ||
| 829 | #define MX50_PAD_EIM_DA6__EIM_WEIM_A_6 0x274 0x610 0x000 0x0 0x0 | ||
| 830 | #define MX50_PAD_EIM_DA6__GPIO1_6 0x274 0x610 0x000 0x1 0x0 | ||
| 831 | #define MX50_PAD_EIM_DA6__KPP_COL_7 0x274 0x610 0x79c 0x3 0x2 | ||
| 832 | #define MX50_PAD_EIM_DA6__TPIU_TRACE_6 0x274 0x610 0x000 0x6 0x0 | ||
| 833 | #define MX50_PAD_EIM_DA6__SRC_BT_CFG1_6 0x274 0x610 0x000 0x7 0x0 | ||
| 834 | #define MX50_PAD_EIM_DA7__EIM_WEIM_A_7 0x278 0x614 0x000 0x0 0x0 | ||
| 835 | #define MX50_PAD_EIM_DA7__GPIO1_7 0x278 0x614 0x000 0x1 0x0 | ||
| 836 | #define MX50_PAD_EIM_DA7__KPP_ROW_7 0x278 0x614 0x7ac 0x3 0x2 | ||
| 837 | #define MX50_PAD_EIM_DA7__TPIU_TRACE_7 0x278 0x614 0x000 0x6 0x0 | ||
| 838 | #define MX50_PAD_EIM_DA7__SRC_BT_CFG1_7 0x278 0x614 0x000 0x7 0x0 | ||
| 839 | #define MX50_PAD_EIM_DA8__EIM_WEIM_A_8 0x27c 0x618 0x000 0x0 0x0 | ||
| 840 | #define MX50_PAD_EIM_DA8__GPIO1_8 0x27c 0x618 0x000 0x1 0x0 | ||
| 841 | #define MX50_PAD_EIM_DA8__EIM_NANDF_CLE 0x27c 0x618 0x000 0x2 0x0 | ||
| 842 | #define MX50_PAD_EIM_DA8__TPIU_TRACE_8 0x27c 0x618 0x000 0x6 0x0 | ||
| 843 | #define MX50_PAD_EIM_DA8__SRC_BT_CFG2_0 0x27c 0x618 0x000 0x7 0x0 | ||
| 844 | #define MX50_PAD_EIM_DA9__EIM_WEIM_A_9 0x280 0x61c 0x000 0x0 0x0 | ||
| 845 | #define MX50_PAD_EIM_DA9__GPIO1_9 0x280 0x61c 0x000 0x1 0x0 | ||
| 846 | #define MX50_PAD_EIM_DA9__EIM_NANDF_ALE 0x280 0x61c 0x000 0x2 0x0 | ||
| 847 | #define MX50_PAD_EIM_DA9__TPIU_TRACE_9 0x280 0x61c 0x000 0x6 0x0 | ||
| 848 | #define MX50_PAD_EIM_DA9__SRC_BT_CFG2_1 0x280 0x61c 0x000 0x7 0x0 | ||
| 849 | #define MX50_PAD_EIM_DA10__EIM_WEIM_A_10 0x284 0x620 0x000 0x0 0x0 | ||
| 850 | #define MX50_PAD_EIM_DA10__GPIO1_10 0x284 0x620 0x000 0x1 0x0 | ||
| 851 | #define MX50_PAD_EIM_DA10__EIM_NANDF_CEN_0 0x284 0x620 0x000 0x2 0x0 | ||
| 852 | #define MX50_PAD_EIM_DA10__TPIU_TRACE_10 0x284 0x620 0x000 0x6 0x0 | ||
| 853 | #define MX50_PAD_EIM_DA10__SRC_BT_CFG2_2 0x284 0x620 0x000 0x7 0x0 | ||
| 854 | #define MX50_PAD_EIM_DA11__EIM_WEIM_A_11 0x288 0x624 0x000 0x0 0x0 | ||
| 855 | #define MX50_PAD_EIM_DA11__GPIO1_11 0x288 0x624 0x000 0x1 0x0 | ||
| 856 | #define MX50_PAD_EIM_DA11__EIM_NANDF_CEN_1 0x288 0x624 0x000 0x2 0x0 | ||
| 857 | #define MX50_PAD_EIM_DA11__TPIU_TRACE_11 0x288 0x624 0x000 0x6 0x0 | ||
| 858 | #define MX50_PAD_EIM_DA11__SRC_BT_CFG2_3 0x288 0x624 0x000 0x7 0x0 | ||
| 859 | #define MX50_PAD_EIM_DA12__EIM_WEIM_A_12 0x28c 0x628 0x000 0x0 0x0 | ||
| 860 | #define MX50_PAD_EIM_DA12__GPIO1_12 0x28c 0x628 0x000 0x1 0x0 | ||
| 861 | #define MX50_PAD_EIM_DA12__EIM_NANDF_CEN_2 0x28c 0x628 0x000 0x2 0x0 | ||
| 862 | #define MX50_PAD_EIM_DA12__EPDC_SDCE_6 0x28c 0x628 0x000 0x3 0x0 | ||
| 863 | #define MX50_PAD_EIM_DA12__TPIU_TRACE_12 0x28c 0x628 0x000 0x6 0x0 | ||
| 864 | #define MX50_PAD_EIM_DA12__SRC_BT_CFG2_4 0x28c 0x628 0x000 0x7 0x0 | ||
| 865 | #define MX50_PAD_EIM_DA13__EIM_WEIM_A_13 0x290 0x62c 0x000 0x0 0x0 | ||
| 866 | #define MX50_PAD_EIM_DA13__GPIO1_13 0x290 0x62c 0x000 0x1 0x0 | ||
| 867 | #define MX50_PAD_EIM_DA13__EIM_NANDF_CEN_3 0x290 0x62c 0x000 0x2 0x0 | ||
| 868 | #define MX50_PAD_EIM_DA13__EPDC_SDCE_7 0x290 0x62c 0x000 0x3 0x0 | ||
| 869 | #define MX50_PAD_EIM_DA13__TPIU_TRACE_13 0x290 0x62c 0x000 0x6 0x0 | ||
| 870 | #define MX50_PAD_EIM_DA13__SRC_BT_CFG2_5 0x290 0x62c 0x000 0x7 0x0 | ||
| 871 | #define MX50_PAD_EIM_DA14__EIM_WEIM_A_14 0x294 0x630 0x000 0x0 0x0 | ||
| 872 | #define MX50_PAD_EIM_DA14__GPIO1_14 0x294 0x630 0x000 0x1 0x0 | ||
| 873 | #define MX50_PAD_EIM_DA14__EIM_NANDF_READY0 0x294 0x630 0x7b4 0x2 0x2 | ||
| 874 | #define MX50_PAD_EIM_DA14__EPDC_SDCE_8 0x294 0x630 0x000 0x3 0x0 | ||
| 875 | #define MX50_PAD_EIM_DA14__TPIU_TRACE_14 0x294 0x630 0x000 0x6 0x0 | ||
| 876 | #define MX50_PAD_EIM_DA14__SRC_BT_CFG2_6 0x294 0x630 0x000 0x7 0x0 | ||
| 877 | #define MX50_PAD_EIM_DA15__EIM_WEIM_A_15 0x298 0x634 0x000 0x0 0x0 | ||
| 878 | #define MX50_PAD_EIM_DA15__GPIO1_15 0x298 0x634 0x000 0x1 0x0 | ||
| 879 | #define MX50_PAD_EIM_DA15__EIM_NANDF_DQS 0x298 0x634 0x7b0 0x2 0x2 | ||
| 880 | #define MX50_PAD_EIM_DA15__EPDC_SDCE_9 0x298 0x634 0x000 0x3 0x0 | ||
| 881 | #define MX50_PAD_EIM_DA15__TPIU_TRACE_15 0x298 0x634 0x000 0x6 0x0 | ||
| 882 | #define MX50_PAD_EIM_DA15__SRC_BT_CFG2_7 0x298 0x634 0x000 0x7 0x0 | ||
| 883 | #define MX50_PAD_EIM_CS2__EIM_WEIM_CS_2 0x29c 0x638 0x000 0x0 0x0 | ||
| 884 | #define MX50_PAD_EIM_CS2__GPIO1_16 0x29c 0x638 0x000 0x1 0x0 | ||
| 885 | #define MX50_PAD_EIM_CS2__EIM_WEIM_A_27 0x29c 0x638 0x000 0x2 0x0 | ||
| 886 | #define MX50_PAD_EIM_CS2__TPIU_TRCLK 0x29c 0x638 0x000 0x6 0x0 | ||
| 887 | #define MX50_PAD_EIM_CS2__SRC_BT_CFG3_0 0x29c 0x638 0x000 0x7 0x0 | ||
| 888 | #define MX50_PAD_EIM_CS1__EIM_WEIM_CS_1 0x2a0 0x63c 0x000 0x0 0x0 | ||
| 889 | #define MX50_PAD_EIM_CS1__GPIO1_17 0x2a0 0x63c 0x000 0x1 0x0 | ||
| 890 | #define MX50_PAD_EIM_CS1__TPIU_TRCTL 0x2a0 0x63c 0x000 0x6 0x0 | ||
| 891 | #define MX50_PAD_EIM_CS1__SRC_BT_CFG3_1 0x2a0 0x63c 0x000 0x7 0x0 | ||
| 892 | #define MX50_PAD_EIM_CS0__EIM_WEIM_CS_0 0x2a4 0x640 0x000 0x0 0x0 | ||
| 893 | #define MX50_PAD_EIM_CS0__GPIO1_18 0x2a4 0x640 0x000 0x1 0x0 | ||
| 894 | #define MX50_PAD_EIM_CS0__SRC_BT_CFG3_2 0x2a4 0x640 0x000 0x7 0x0 | ||
| 895 | #define MX50_PAD_EIM_EB0__EIM_WEIM_EB_0 0x2a8 0x644 0x000 0x0 0x0 | ||
| 896 | #define MX50_PAD_EIM_EB0__GPIO1_19 0x2a8 0x644 0x000 0x1 0x0 | ||
| 897 | #define MX50_PAD_EIM_EB0__SRC_BT_CFG3_3 0x2a8 0x644 0x000 0x7 0x0 | ||
| 898 | #define MX50_PAD_EIM_EB1__EIM_WEIM_EB_1 0x2ac 0x648 0x000 0x0 0x0 | ||
| 899 | #define MX50_PAD_EIM_EB1__GPIO1_20 0x2ac 0x648 0x000 0x1 0x0 | ||
| 900 | #define MX50_PAD_EIM_EB1__SRC_BT_CFG3_4 0x2ac 0x648 0x000 0x7 0x0 | ||
| 901 | #define MX50_PAD_EIM_WAIT__EIM_WEIM_WAIT 0x2b0 0x64c 0x000 0x0 0x0 | ||
| 902 | #define MX50_PAD_EIM_WAIT__GPIO1_21 0x2b0 0x64c 0x000 0x1 0x0 | ||
| 903 | #define MX50_PAD_EIM_WAIT__EIM_WEIM_DTACK_B 0x2b0 0x64c 0x000 0x2 0x0 | ||
| 904 | #define MX50_PAD_EIM_WAIT__SRC_BT_CFG3_5 0x2b0 0x64c 0x000 0x7 0x0 | ||
| 905 | #define MX50_PAD_EIM_BCLK__EIM_WEIM_BCLK 0x2b4 0x650 0x000 0x0 0x0 | ||
| 906 | #define MX50_PAD_EIM_BCLK__GPIO1_22 0x2b4 0x650 0x000 0x1 0x0 | ||
| 907 | #define MX50_PAD_EIM_BCLK__SRC_BT_CFG3_6 0x2b4 0x650 0x000 0x7 0x0 | ||
| 908 | #define MX50_PAD_EIM_RDY__EIM_WEIM_RDY 0x2b8 0x654 0x000 0x0 0x0 | ||
| 909 | #define MX50_PAD_EIM_RDY__GPIO1_23 0x2b8 0x654 0x000 0x1 0x0 | ||
| 910 | #define MX50_PAD_EIM_RDY__SRC_BT_CFG3_7 0x2b8 0x654 0x000 0x7 0x0 | ||
| 911 | #define MX50_PAD_EIM_OE__EIM_WEIM_OE 0x2bc 0x658 0x000 0x0 0x0 | ||
| 912 | #define MX50_PAD_EIM_OE__GPIO1_24 0x2bc 0x658 0x000 0x1 0x0 | ||
| 913 | #define MX50_PAD_EIM_OE__INT_BOOT 0x2bc 0x658 0x000 0x7 0x0 | ||
| 914 | #define MX50_PAD_EIM_RW__EIM_WEIM_RW 0x2c0 0x65c 0x000 0x0 0x0 | ||
| 915 | #define MX50_PAD_EIM_RW__GPIO1_25 0x2c0 0x65c 0x000 0x1 0x0 | ||
| 916 | #define MX50_PAD_EIM_RW__SYSTEM_RST 0x2c0 0x65c 0x000 0x7 0x0 | ||
| 917 | #define MX50_PAD_EIM_LBA__EIM_WEIM_LBA 0x2c4 0x660 0x000 0x0 0x0 | ||
| 918 | #define MX50_PAD_EIM_LBA__GPIO1_26 0x2c4 0x660 0x000 0x1 0x0 | ||
| 919 | #define MX50_PAD_EIM_LBA__TESTER_ACK 0x2c4 0x660 0x000 0x7 0x0 | ||
| 920 | #define MX50_PAD_EIM_CRE__EIM_WEIM_CRE 0x2c8 0x664 0x000 0x0 0x0 | ||
| 921 | #define MX50_PAD_EIM_CRE__GPIO1_27 0x2c8 0x664 0x000 0x1 0x0 | ||
| 922 | |||
| 923 | #endif /* __DTS_IMX50_PINFUNC_H */ | ||
diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi new file mode 100644 index 000000000000..0c75fe3deb35 --- /dev/null +++ b/arch/arm/boot/dts/imx50.dtsi | |||
| @@ -0,0 +1,478 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Greg Ungerer <gerg@uclinux.org> | ||
| 3 | * Copyright 2011 Freescale Semiconductor, Inc. | ||
| 4 | * Copyright 2011 Linaro Ltd. | ||
| 5 | * | ||
| 6 | * The code contained herein is licensed under the GNU General Public | ||
| 7 | * License. You may obtain a copy of the GNU General Public License | ||
| 8 | * Version 2 or later at the following locations: | ||
| 9 | * | ||
| 10 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 11 | * http://www.gnu.org/copyleft/gpl.html | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include "skeleton.dtsi" | ||
| 15 | #include "imx50-pinfunc.h" | ||
| 16 | #include <dt-bindings/clock/imx5-clock.h> | ||
| 17 | |||
| 18 | / { | ||
| 19 | aliases { | ||
| 20 | gpio0 = &gpio1; | ||
| 21 | gpio1 = &gpio2; | ||
| 22 | gpio2 = &gpio3; | ||
| 23 | gpio3 = &gpio4; | ||
| 24 | gpio4 = &gpio5; | ||
| 25 | gpio5 = &gpio6; | ||
| 26 | serial0 = &uart1; | ||
| 27 | serial1 = &uart2; | ||
| 28 | serial2 = &uart3; | ||
| 29 | serial3 = &uart4; | ||
| 30 | serial4 = &uart5; | ||
| 31 | }; | ||
| 32 | |||
| 33 | cpus { | ||
| 34 | #address-cells = <1>; | ||
| 35 | #size-cells = <0>; | ||
| 36 | cpu@0 { | ||
| 37 | device_type = "cpu"; | ||
| 38 | compatible = "arm,cortex-a8"; | ||
| 39 | reg = <0x0>; | ||
| 40 | }; | ||
| 41 | }; | ||
| 42 | |||
| 43 | tzic: tz-interrupt-controller@0fffc000 { | ||
| 44 | compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic"; | ||
| 45 | interrupt-controller; | ||
| 46 | #interrupt-cells = <1>; | ||
| 47 | reg = <0x0fffc000 0x4000>; | ||
| 48 | }; | ||
| 49 | |||
| 50 | clocks { | ||
| 51 | #address-cells = <1>; | ||
| 52 | #size-cells = <0>; | ||
| 53 | |||
| 54 | ckil { | ||
| 55 | compatible = "fsl,imx-ckil", "fixed-clock"; | ||
| 56 | clock-frequency = <32768>; | ||
| 57 | }; | ||
| 58 | |||
| 59 | ckih1 { | ||
| 60 | compatible = "fsl,imx-ckih1", "fixed-clock"; | ||
| 61 | clock-frequency = <22579200>; | ||
| 62 | }; | ||
| 63 | |||
| 64 | ckih2 { | ||
| 65 | compatible = "fsl,imx-ckih2", "fixed-clock"; | ||
| 66 | clock-frequency = <0>; | ||
| 67 | }; | ||
| 68 | |||
| 69 | osc { | ||
| 70 | compatible = "fsl,imx-osc", "fixed-clock"; | ||
| 71 | clock-frequency = <24000000>; | ||
| 72 | }; | ||
| 73 | }; | ||
| 74 | |||
| 75 | soc { | ||
| 76 | #address-cells = <1>; | ||
| 77 | #size-cells = <1>; | ||
| 78 | compatible = "simple-bus"; | ||
| 79 | interrupt-parent = <&tzic>; | ||
| 80 | ranges; | ||
| 81 | |||
| 82 | aips@50000000 { /* AIPS1 */ | ||
| 83 | compatible = "fsl,aips-bus", "simple-bus"; | ||
| 84 | #address-cells = <1>; | ||
| 85 | #size-cells = <1>; | ||
| 86 | reg = <0x50000000 0x10000000>; | ||
| 87 | ranges; | ||
| 88 | |||
| 89 | spba@50000000 { | ||
| 90 | compatible = "fsl,spba-bus", "simple-bus"; | ||
| 91 | #address-cells = <1>; | ||
| 92 | #size-cells = <1>; | ||
| 93 | reg = <0x50000000 0x40000>; | ||
| 94 | ranges; | ||
| 95 | |||
| 96 | esdhc1: esdhc@50004000 { | ||
| 97 | compatible = "fsl,imx50-esdhc"; | ||
| 98 | reg = <0x50004000 0x4000>; | ||
| 99 | interrupts = <1>; | ||
| 100 | clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, | ||
| 101 | <&clks IMX5_CLK_DUMMY>, | ||
| 102 | <&clks IMX5_CLK_ESDHC1_PER_GATE>; | ||
| 103 | clock-names = "ipg", "ahb", "per"; | ||
| 104 | bus-width = <4>; | ||
| 105 | status = "disabled"; | ||
| 106 | }; | ||
| 107 | |||
| 108 | esdhc2: esdhc@50008000 { | ||
| 109 | compatible = "fsl,imx50-esdhc"; | ||
| 110 | reg = <0x50008000 0x4000>; | ||
| 111 | interrupts = <2>; | ||
| 112 | clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, | ||
| 113 | <&clks IMX5_CLK_DUMMY>, | ||
| 114 | <&clks IMX5_CLK_ESDHC2_PER_GATE>; | ||
| 115 | clock-names = "ipg", "ahb", "per"; | ||
| 116 | bus-width = <4>; | ||
| 117 | status = "disabled"; | ||
| 118 | }; | ||
| 119 | |||
| 120 | uart3: serial@5000c000 { | ||
| 121 | compatible = "fsl,imx50-uart", "fsl,imx21-uart"; | ||
| 122 | reg = <0x5000c000 0x4000>; | ||
| 123 | interrupts = <33>; | ||
| 124 | clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, | ||
| 125 | <&clks IMX5_CLK_UART3_PER_GATE>; | ||
| 126 | clock-names = "ipg", "per"; | ||
| 127 | status = "disabled"; | ||
| 128 | }; | ||
| 129 | |||
| 130 | ecspi1: ecspi@50010000 { | ||
| 131 | #address-cells = <1>; | ||
| 132 | #size-cells = <0>; | ||
| 133 | compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi"; | ||
| 134 | reg = <0x50010000 0x4000>; | ||
| 135 | interrupts = <36>; | ||
| 136 | clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, | ||
| 137 | <&clks IMX5_CLK_ECSPI1_PER_GATE>; | ||
| 138 | clock-names = "ipg", "per"; | ||
| 139 | status = "disabled"; | ||
| 140 | }; | ||
| 141 | |||
| 142 | ssi2: ssi@50014000 { | ||
| 143 | compatible = "fsl,imx50-ssi", | ||
| 144 | "fsl,imx51-ssi", | ||
| 145 | "fsl,imx21-ssi"; | ||
| 146 | reg = <0x50014000 0x4000>; | ||
| 147 | interrupts = <30>; | ||
| 148 | clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>; | ||
| 149 | fsl,fifo-depth = <15>; | ||
| 150 | fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ | ||
| 151 | status = "disabled"; | ||
| 152 | }; | ||
| 153 | |||
| 154 | esdhc3: esdhc@50020000 { | ||
| 155 | compatible = "fsl,imx50-esdhc"; | ||
| 156 | reg = <0x50020000 0x4000>; | ||
| 157 | interrupts = <3>; | ||
| 158 | clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, | ||
| 159 | <&clks IMX5_CLK_DUMMY>, | ||
| 160 | <&clks IMX5_CLK_ESDHC3_PER_GATE>; | ||
| 161 | clock-names = "ipg", "ahb", "per"; | ||
| 162 | bus-width = <4>; | ||
| 163 | status = "disabled"; | ||
| 164 | }; | ||
| 165 | |||
| 166 | esdhc4: esdhc@50024000 { | ||
| 167 | compatible = "fsl,imx50-esdhc"; | ||
| 168 | reg = <0x50024000 0x4000>; | ||
| 169 | interrupts = <4>; | ||
| 170 | clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, | ||
| 171 | <&clks IMX5_CLK_DUMMY>, | ||
| 172 | <&clks IMX5_CLK_ESDHC4_PER_GATE>; | ||
| 173 | clock-names = "ipg", "ahb", "per"; | ||
| 174 | bus-width = <4>; | ||
| 175 | status = "disabled"; | ||
| 176 | }; | ||
| 177 | }; | ||
| 178 | |||
| 179 | usbotg: usb@53f80000 { | ||
| 180 | compatible = "fsl,imx50-usb", "fsl,imx27-usb"; | ||
| 181 | reg = <0x53f80000 0x0200>; | ||
| 182 | interrupts = <18>; | ||
| 183 | clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; | ||
| 184 | status = "disabled"; | ||
| 185 | }; | ||
| 186 | |||
| 187 | usbh1: usb@53f80200 { | ||
| 188 | compatible = "fsl,imx50-usb", "fsl,imx27-usb"; | ||
| 189 | reg = <0x53f80200 0x0200>; | ||
| 190 | interrupts = <14>; | ||
| 191 | clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; | ||
| 192 | status = "disabled"; | ||
| 193 | }; | ||
| 194 | |||
| 195 | usbh2: usb@53f80400 { | ||
| 196 | compatible = "fsl,imx50-usb", "fsl,imx27-usb"; | ||
| 197 | reg = <0x53f80400 0x0200>; | ||
| 198 | interrupts = <16>; | ||
| 199 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; | ||
| 200 | status = "disabled"; | ||
| 201 | }; | ||
| 202 | |||
| 203 | usbh3: usb@53f80600 { | ||
| 204 | compatible = "fsl,imx50-usb", "fsl,imx27-usb"; | ||
| 205 | reg = <0x53f80600 0x0200>; | ||
| 206 | interrupts = <17>; | ||
| 207 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; | ||
| 208 | status = "disabled"; | ||
| 209 | }; | ||
| 210 | |||
| 211 | gpio1: gpio@53f84000 { | ||
| 212 | compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; | ||
| 213 | reg = <0x53f84000 0x4000>; | ||
| 214 | interrupts = <50 51>; | ||
| 215 | gpio-controller; | ||
| 216 | #gpio-cells = <2>; | ||
| 217 | interrupt-controller; | ||
| 218 | #interrupt-cells = <2>; | ||
| 219 | }; | ||
| 220 | |||
| 221 | gpio2: gpio@53f88000 { | ||
| 222 | compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; | ||
| 223 | reg = <0x53f88000 0x4000>; | ||
| 224 | interrupts = <52 53>; | ||
| 225 | gpio-controller; | ||
| 226 | #gpio-cells = <2>; | ||
| 227 | interrupt-controller; | ||
| 228 | #interrupt-cells = <2>; | ||
| 229 | }; | ||
| 230 | |||
| 231 | gpio3: gpio@53f8c000 { | ||
| 232 | compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; | ||
| 233 | reg = <0x53f8c000 0x4000>; | ||
| 234 | interrupts = <54 55>; | ||
| 235 | gpio-controller; | ||
| 236 | #gpio-cells = <2>; | ||
| 237 | interrupt-controller; | ||
| 238 | #interrupt-cells = <2>; | ||
| 239 | }; | ||
| 240 | |||
| 241 | gpio4: gpio@53f90000 { | ||
| 242 | compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; | ||
| 243 | reg = <0x53f90000 0x4000>; | ||
| 244 | interrupts = <56 57>; | ||
| 245 | gpio-controller; | ||
| 246 | #gpio-cells = <2>; | ||
| 247 | interrupt-controller; | ||
| 248 | #interrupt-cells = <2>; | ||
| 249 | }; | ||
| 250 | |||
| 251 | wdog1: wdog@53f98000 { | ||
| 252 | compatible = "fsl,imx50-wdt", "fsl,imx21-wdt"; | ||
| 253 | reg = <0x53f98000 0x4000>; | ||
| 254 | interrupts = <58>; | ||
| 255 | clocks = <&clks IMX5_CLK_DUMMY>; | ||
| 256 | }; | ||
| 257 | |||
| 258 | gpt: timer@53fa0000 { | ||
| 259 | compatible = "fsl,imx50-gpt", "fsl,imx31-gpt"; | ||
| 260 | reg = <0x53fa0000 0x4000>; | ||
| 261 | interrupts = <39>; | ||
| 262 | clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, | ||
| 263 | <&clks IMX5_CLK_GPT_HF_GATE>; | ||
| 264 | clock-names = "ipg", "per"; | ||
| 265 | }; | ||
| 266 | |||
| 267 | iomuxc: iomuxc@53fa8000 { | ||
| 268 | compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc"; | ||
| 269 | reg = <0x53fa8000 0x4000>; | ||
| 270 | }; | ||
| 271 | |||
| 272 | gpr: iomuxc-gpr@53fa8000 { | ||
| 273 | compatible = "fsl,imx50-iomuxc-gpr", "syscon"; | ||
| 274 | reg = <0x53fa8000 0xc>; | ||
| 275 | }; | ||
| 276 | |||
| 277 | pwm1: pwm@53fb4000 { | ||
| 278 | #pwm-cells = <2>; | ||
| 279 | compatible = "fsl,imx50-pwm", "fsl,imx27-pwm"; | ||
| 280 | reg = <0x53fb4000 0x4000>; | ||
| 281 | clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, | ||
| 282 | <&clks IMX5_CLK_PWM1_HF_GATE>; | ||
| 283 | clock-names = "ipg", "per"; | ||
| 284 | interrupts = <61>; | ||
| 285 | }; | ||
| 286 | |||
| 287 | pwm2: pwm@53fb8000 { | ||
| 288 | #pwm-cells = <2>; | ||
| 289 | compatible = "fsl,imx50-pwm", "fsl,imx27-pwm"; | ||
| 290 | reg = <0x53fb8000 0x4000>; | ||
| 291 | clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, | ||
| 292 | <&clks IMX5_CLK_PWM2_HF_GATE>; | ||
| 293 | clock-names = "ipg", "per"; | ||
| 294 | interrupts = <94>; | ||
| 295 | }; | ||
| 296 | |||
| 297 | uart1: serial@53fbc000 { | ||
| 298 | compatible = "fsl,imx50-uart", "fsl,imx21-uart"; | ||
| 299 | reg = <0x53fbc000 0x4000>; | ||
| 300 | interrupts = <31>; | ||
| 301 | clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, | ||
| 302 | <&clks IMX5_CLK_UART1_PER_GATE>; | ||
| 303 | clock-names = "ipg", "per"; | ||
| 304 | status = "disabled"; | ||
| 305 | }; | ||
| 306 | |||
| 307 | uart2: serial@53fc0000 { | ||
| 308 | compatible = "fsl,imx50-uart", "fsl,imx21-uart"; | ||
| 309 | reg = <0x53fc0000 0x4000>; | ||
| 310 | interrupts = <32>; | ||
| 311 | clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, | ||
| 312 | <&clks IMX5_CLK_UART2_PER_GATE>; | ||
| 313 | clock-names = "ipg", "per"; | ||
| 314 | status = "disabled"; | ||
| 315 | }; | ||
| 316 | |||
| 317 | src: src@53fd0000 { | ||
| 318 | compatible = "fsl,imx50-src", "fsl,imx51-src"; | ||
| 319 | reg = <0x53fd0000 0x4000>; | ||
| 320 | #reset-cells = <1>; | ||
| 321 | }; | ||
| 322 | |||
| 323 | clks: ccm@53fd4000{ | ||
| 324 | compatible = "fsl,imx50-ccm"; | ||
| 325 | reg = <0x53fd4000 0x4000>; | ||
| 326 | interrupts = <0 71 0x04 0 72 0x04>; | ||
| 327 | #clock-cells = <1>; | ||
| 328 | }; | ||
| 329 | |||
| 330 | gpio5: gpio@53fdc000 { | ||
| 331 | compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; | ||
| 332 | reg = <0x53fdc000 0x4000>; | ||
| 333 | interrupts = <103 104>; | ||
| 334 | gpio-controller; | ||
| 335 | #gpio-cells = <2>; | ||
| 336 | interrupt-controller; | ||
| 337 | #interrupt-cells = <2>; | ||
| 338 | }; | ||
| 339 | |||
| 340 | gpio6: gpio@53fe0000 { | ||
| 341 | compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; | ||
| 342 | reg = <0x53fe0000 0x4000>; | ||
| 343 | interrupts = <105 106>; | ||
| 344 | gpio-controller; | ||
| 345 | #gpio-cells = <2>; | ||
| 346 | interrupt-controller; | ||
| 347 | #interrupt-cells = <2>; | ||
| 348 | }; | ||
| 349 | |||
| 350 | i2c3: i2c@53fec000 { | ||
| 351 | #address-cells = <1>; | ||
| 352 | #size-cells = <0>; | ||
| 353 | compatible = "fsl,imx50-i2c", "fsl,imx21-i2c"; | ||
| 354 | reg = <0x53fec000 0x4000>; | ||
| 355 | interrupts = <64>; | ||
| 356 | clocks = <&clks IMX5_CLK_I2C3_GATE>; | ||
| 357 | status = "disabled"; | ||
| 358 | }; | ||
| 359 | |||
| 360 | uart4: serial@53ff0000 { | ||
| 361 | compatible = "fsl,imx50-uart", "fsl,imx21-uart"; | ||
| 362 | reg = <0x53ff0000 0x4000>; | ||
| 363 | interrupts = <13>; | ||
| 364 | clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, | ||
| 365 | <&clks IMX5_CLK_UART4_PER_GATE>; | ||
| 366 | clock-names = "ipg", "per"; | ||
| 367 | status = "disabled"; | ||
| 368 | }; | ||
| 369 | }; | ||
| 370 | |||
| 371 | aips@60000000 { /* AIPS2 */ | ||
| 372 | compatible = "fsl,aips-bus", "simple-bus"; | ||
| 373 | #address-cells = <1>; | ||
| 374 | #size-cells = <1>; | ||
| 375 | reg = <0x60000000 0x10000000>; | ||
| 376 | ranges; | ||
| 377 | |||
| 378 | uart5: serial@63f90000 { | ||
| 379 | compatible = "fsl,imx50-uart", "fsl,imx21-uart"; | ||
| 380 | reg = <0x63f90000 0x4000>; | ||
| 381 | interrupts = <86>; | ||
| 382 | clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, | ||
| 383 | <&clks IMX5_CLK_UART5_PER_GATE>; | ||
| 384 | clock-names = "ipg", "per"; | ||
| 385 | status = "disabled"; | ||
| 386 | }; | ||
| 387 | |||
| 388 | owire: owire@63fa4000 { | ||
| 389 | compatible = "fsl,imx50-owire", "fsl,imx21-owire"; | ||
| 390 | reg = <0x63fa4000 0x4000>; | ||
| 391 | clocks = <&clks IMX5_CLK_OWIRE_GATE>; | ||
| 392 | status = "disabled"; | ||
| 393 | }; | ||
| 394 | |||
| 395 | ecspi2: ecspi@63fac000 { | ||
| 396 | #address-cells = <1>; | ||
| 397 | #size-cells = <0>; | ||
| 398 | compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi"; | ||
| 399 | reg = <0x63fac000 0x4000>; | ||
| 400 | interrupts = <37>; | ||
| 401 | clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, | ||
| 402 | <&clks IMX5_CLK_ECSPI2_PER_GATE>; | ||
| 403 | clock-names = "ipg", "per"; | ||
| 404 | status = "disabled"; | ||
| 405 | }; | ||
| 406 | |||
| 407 | sdma: sdma@63fb0000 { | ||
| 408 | compatible = "fsl,imx50-sdma", "fsl,imx35-sdma"; | ||
| 409 | reg = <0x63fb0000 0x4000>; | ||
| 410 | interrupts = <6>; | ||
| 411 | clocks = <&clks IMX5_CLK_SDMA_GATE>, | ||
| 412 | <&clks IMX5_CLK_SDMA_GATE>; | ||
| 413 | clock-names = "ipg", "ahb"; | ||
| 414 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin"; | ||
| 415 | }; | ||
| 416 | |||
| 417 | cspi: cspi@63fc0000 { | ||
| 418 | #address-cells = <1>; | ||
| 419 | #size-cells = <0>; | ||
| 420 | compatible = "fsl,imx50-cspi", "fsl,imx35-cspi"; | ||
| 421 | reg = <0x63fc0000 0x4000>; | ||
| 422 | interrupts = <38>; | ||
| 423 | clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, | ||
| 424 | <&clks IMX5_CLK_CSPI_IPG_GATE>; | ||
| 425 | clock-names = "ipg", "per"; | ||
| 426 | status = "disabled"; | ||
| 427 | }; | ||
| 428 | |||
| 429 | i2c2: i2c@63fc4000 { | ||
| 430 | #address-cells = <1>; | ||
| 431 | #size-cells = <0>; | ||
| 432 | compatible = "fsl,imx50-i2c", "fsl,imx21-i2c"; | ||
| 433 | reg = <0x63fc4000 0x4000>; | ||
| 434 | interrupts = <63>; | ||
| 435 | clocks = <&clks IMX5_CLK_I2C2_GATE>; | ||
| 436 | status = "disabled"; | ||
| 437 | }; | ||
| 438 | |||
| 439 | i2c1: i2c@63fc8000 { | ||
| 440 | #address-cells = <1>; | ||
| 441 | #size-cells = <0>; | ||
| 442 | compatible = "fsl,imx50-i2c", "fsl,imx21-i2c"; | ||
| 443 | reg = <0x63fc8000 0x4000>; | ||
| 444 | interrupts = <62>; | ||
| 445 | clocks = <&clks IMX5_CLK_I2C1_GATE>; | ||
| 446 | status = "disabled"; | ||
| 447 | }; | ||
| 448 | |||
| 449 | ssi1: ssi@63fcc000 { | ||
| 450 | compatible = "fsl,imx50-ssi", "fsl,imx51-ssi", | ||
| 451 | "fsl,imx21-ssi"; | ||
| 452 | reg = <0x63fcc000 0x4000>; | ||
| 453 | interrupts = <29>; | ||
| 454 | clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>; | ||
| 455 | fsl,fifo-depth = <15>; | ||
| 456 | fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ | ||
| 457 | status = "disabled"; | ||
| 458 | }; | ||
| 459 | |||
| 460 | audmux: audmux@63fd0000 { | ||
| 461 | compatible = "fsl,imx50-audmux", "fsl,imx31-audmux"; | ||
| 462 | reg = <0x63fd0000 0x4000>; | ||
| 463 | status = "disabled"; | ||
| 464 | }; | ||
| 465 | |||
| 466 | fec: ethernet@63fec000 { | ||
| 467 | compatible = "fsl,imx53-fec", "fsl,imx25-fec"; | ||
| 468 | reg = <0x63fec000 0x4000>; | ||
| 469 | interrupts = <87>; | ||
| 470 | clocks = <&clks IMX5_CLK_FEC_GATE>, | ||
| 471 | <&clks IMX5_CLK_FEC_GATE>, | ||
| 472 | <&clks IMX5_CLK_FEC_GATE>; | ||
| 473 | clock-names = "ipg", "ahb", "ptp"; | ||
| 474 | status = "disabled"; | ||
| 475 | }; | ||
| 476 | }; | ||
| 477 | }; | ||
| 478 | }; | ||
diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts index b3606993f2e8..e88b2a6be079 100644 --- a/arch/arm/boot/dts/imx51-apf51.dts +++ b/arch/arm/boot/dts/imx51-apf51.dts | |||
| @@ -34,13 +34,47 @@ | |||
| 34 | 34 | ||
| 35 | &fec { | 35 | &fec { |
| 36 | pinctrl-names = "default"; | 36 | pinctrl-names = "default"; |
| 37 | pinctrl-0 = <&pinctrl_fec_2>; | 37 | pinctrl-0 = <&pinctrl_fec>; |
| 38 | phy-mode = "mii"; | 38 | phy-mode = "mii"; |
| 39 | phy-reset-gpios = <&gpio3 0 0>; | 39 | phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; |
| 40 | phy-reset-duration = <1>; | 40 | phy-reset-duration = <1>; |
| 41 | status = "okay"; | 41 | status = "okay"; |
| 42 | }; | 42 | }; |
| 43 | 43 | ||
| 44 | &iomuxc { | ||
| 45 | imx51-apf51 { | ||
| 46 | pinctrl_fec: fecgrp { | ||
| 47 | fsl,pins = < | ||
| 48 | MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 | ||
| 49 | MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 | ||
| 50 | MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 | ||
| 51 | MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 | ||
| 52 | MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 | ||
| 53 | MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 | ||
| 54 | MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 | ||
| 55 | MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 | ||
| 56 | MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 | ||
| 57 | MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 | ||
| 58 | MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 | ||
| 59 | MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 | ||
| 60 | MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 | ||
| 61 | MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 | ||
| 62 | MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 | ||
| 63 | MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 | ||
| 64 | MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 | ||
| 65 | MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 | ||
| 66 | >; | ||
| 67 | }; | ||
| 68 | |||
| 69 | pinctrl_uart3: uart3grp { | ||
| 70 | fsl,pins = < | ||
| 71 | MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 | ||
| 72 | MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 | ||
| 73 | >; | ||
| 74 | }; | ||
| 75 | }; | ||
| 76 | }; | ||
| 77 | |||
| 44 | &nfc { | 78 | &nfc { |
| 45 | nand-bus-width = <8>; | 79 | nand-bus-width = <8>; |
| 46 | nand-ecc-mode = "hw"; | 80 | nand-ecc-mode = "hw"; |
| @@ -50,6 +84,6 @@ | |||
| 50 | 84 | ||
| 51 | &uart3 { | 85 | &uart3 { |
| 52 | pinctrl-names = "default"; | 86 | pinctrl-names = "default"; |
| 53 | pinctrl-0 = <&pinctrl_uart3_2>; | 87 | pinctrl-0 = <&pinctrl_uart3>; |
| 54 | status = "okay"; | 88 | status = "okay"; |
| 55 | }; | 89 | }; |
diff --git a/arch/arm/boot/dts/imx51-apf51dev.dts b/arch/arm/boot/dts/imx51-apf51dev.dts index 5a7f552786a1..c29cfa927c98 100644 --- a/arch/arm/boot/dts/imx51-apf51dev.dts +++ b/arch/arm/boot/dts/imx51-apf51dev.dts | |||
| @@ -21,7 +21,7 @@ | |||
| 21 | crtcs = <&ipu 0>; | 21 | crtcs = <&ipu 0>; |
| 22 | interface-pix-fmt = "bgr666"; | 22 | interface-pix-fmt = "bgr666"; |
| 23 | pinctrl-names = "default"; | 23 | pinctrl-names = "default"; |
| 24 | pinctrl-0 = <&pinctrl_ipu_disp1_1>; | 24 | pinctrl-0 = <&pinctrl_ipu_disp1>; |
| 25 | 25 | ||
| 26 | display-timings { | 26 | display-timings { |
| 27 | lw700 { | 27 | lw700 { |
| @@ -48,7 +48,7 @@ | |||
| 48 | 48 | ||
| 49 | user-key { | 49 | user-key { |
| 50 | label = "user"; | 50 | label = "user"; |
| 51 | gpios = <&gpio1 3 0>; | 51 | gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; |
| 52 | linux,code = <256>; /* BTN_0 */ | 52 | linux,code = <256>; /* BTN_0 */ |
| 53 | }; | 53 | }; |
| 54 | }; | 54 | }; |
| @@ -58,7 +58,7 @@ | |||
| 58 | 58 | ||
| 59 | user { | 59 | user { |
| 60 | label = "Heartbeat"; | 60 | label = "Heartbeat"; |
| 61 | gpios = <&gpio1 2 0>; | 61 | gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; |
| 62 | linux,default-trigger = "heartbeat"; | 62 | linux,default-trigger = "heartbeat"; |
| 63 | }; | 63 | }; |
| 64 | }; | 64 | }; |
| @@ -66,31 +66,33 @@ | |||
| 66 | 66 | ||
| 67 | &ecspi1 { | 67 | &ecspi1 { |
| 68 | pinctrl-names = "default"; | 68 | pinctrl-names = "default"; |
| 69 | pinctrl-0 = <&pinctrl_ecspi1_1>; | 69 | pinctrl-0 = <&pinctrl_ecspi1>; |
| 70 | fsl,spi-num-chipselects = <2>; | 70 | fsl,spi-num-chipselects = <2>; |
| 71 | cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>; | 71 | cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, |
| 72 | <&gpio4 25 GPIO_ACTIVE_HIGH>; | ||
| 72 | status = "okay"; | 73 | status = "okay"; |
| 73 | }; | 74 | }; |
| 74 | 75 | ||
| 75 | &ecspi2 { | 76 | &ecspi2 { |
| 76 | pinctrl-names = "default"; | 77 | pinctrl-names = "default"; |
| 77 | pinctrl-0 = <&pinctrl_ecspi2_1>; | 78 | pinctrl-0 = <&pinctrl_ecspi2>; |
| 78 | fsl,spi-num-chipselects = <2>; | 79 | fsl,spi-num-chipselects = <2>; |
| 79 | cs-gpios = <&gpio3 28 1>, <&gpio3 27 1>; | 80 | cs-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>, |
| 81 | <&gpio3 27 GPIO_ACTIVE_LOW>; | ||
| 80 | status = "okay"; | 82 | status = "okay"; |
| 81 | }; | 83 | }; |
| 82 | 84 | ||
| 83 | &esdhc1 { | 85 | &esdhc1 { |
| 84 | pinctrl-names = "default"; | 86 | pinctrl-names = "default"; |
| 85 | pinctrl-0 = <&pinctrl_esdhc1_1>; | 87 | pinctrl-0 = <&pinctrl_esdhc1>; |
| 86 | cd-gpios = <&gpio2 29 0>; | 88 | cd-gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; |
| 87 | bus-width = <4>; | 89 | bus-width = <4>; |
| 88 | status = "okay"; | 90 | status = "okay"; |
| 89 | }; | 91 | }; |
| 90 | 92 | ||
| 91 | &esdhc2 { | 93 | &esdhc2 { |
| 92 | pinctrl-names = "default"; | 94 | pinctrl-names = "default"; |
| 93 | pinctrl-0 = <&pinctrl_esdhc2_1>; | 95 | pinctrl-0 = <&pinctrl_esdhc2>; |
| 94 | bus-width = <4>; | 96 | bus-width = <4>; |
| 95 | non-removable; | 97 | non-removable; |
| 96 | status = "okay"; | 98 | status = "okay"; |
| @@ -98,7 +100,7 @@ | |||
| 98 | 100 | ||
| 99 | &i2c2 { | 101 | &i2c2 { |
| 100 | pinctrl-names = "default"; | 102 | pinctrl-names = "default"; |
| 101 | pinctrl-0 = <&pinctrl_i2c2_2>; | 103 | pinctrl-0 = <&pinctrl_i2c2>; |
| 102 | status = "okay"; | 104 | status = "okay"; |
| 103 | }; | 105 | }; |
| 104 | 106 | ||
| @@ -106,7 +108,7 @@ | |||
| 106 | pinctrl-names = "default"; | 108 | pinctrl-names = "default"; |
| 107 | pinctrl-0 = <&pinctrl_hog>; | 109 | pinctrl-0 = <&pinctrl_hog>; |
| 108 | 110 | ||
| 109 | hog { | 111 | imx51-apf51dev { |
| 110 | pinctrl_hog: hoggrp { | 112 | pinctrl_hog: hoggrp { |
| 111 | fsl,pins = < | 113 | fsl,pins = < |
| 112 | MX51_PAD_EIM_EB2__GPIO2_22 0x0C5 | 114 | MX51_PAD_EIM_EB2__GPIO2_22 0x0C5 |
| @@ -120,5 +122,81 @@ | |||
| 120 | MX51_PAD_GPIO1_3__GPIO1_3 0x0C5 | 122 | MX51_PAD_GPIO1_3__GPIO1_3 0x0C5 |
| 121 | >; | 123 | >; |
| 122 | }; | 124 | }; |
| 125 | |||
| 126 | pinctrl_ecspi1: ecspi1grp { | ||
| 127 | fsl,pins = < | ||
| 128 | MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 | ||
| 129 | MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 | ||
| 130 | MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 | ||
| 131 | >; | ||
| 132 | }; | ||
| 133 | |||
| 134 | pinctrl_ecspi2: ecspi2grp { | ||
| 135 | fsl,pins = < | ||
| 136 | MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185 | ||
| 137 | MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185 | ||
| 138 | MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185 | ||
| 139 | >; | ||
| 140 | }; | ||
| 141 | |||
| 142 | pinctrl_esdhc1: esdhc1grp { | ||
| 143 | fsl,pins = < | ||
| 144 | MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 | ||
| 145 | MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 | ||
| 146 | MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 | ||
| 147 | MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 | ||
| 148 | MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 | ||
| 149 | MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 | ||
| 150 | >; | ||
| 151 | }; | ||
| 152 | |||
| 153 | pinctrl_esdhc2: esdhc2grp { | ||
| 154 | fsl,pins = < | ||
| 155 | MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 | ||
| 156 | MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 | ||
| 157 | MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 | ||
| 158 | MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 | ||
| 159 | MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 | ||
| 160 | MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 | ||
| 161 | >; | ||
| 162 | }; | ||
| 163 | |||
| 164 | pinctrl_i2c2: i2c2grp { | ||
| 165 | fsl,pins = < | ||
| 166 | MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed | ||
| 167 | MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed | ||
| 168 | >; | ||
| 169 | }; | ||
| 170 | |||
| 171 | pinctrl_ipu_disp1: ipudisp1grp { | ||
| 172 | fsl,pins = < | ||
| 173 | MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 | ||
| 174 | MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 | ||
| 175 | MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 | ||
| 176 | MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 | ||
| 177 | MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 | ||
| 178 | MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 | ||
| 179 | MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 | ||
| 180 | MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 | ||
| 181 | MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 | ||
| 182 | MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 | ||
| 183 | MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 | ||
| 184 | MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 | ||
| 185 | MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 | ||
| 186 | MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 | ||
| 187 | MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 | ||
| 188 | MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 | ||
| 189 | MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 | ||
| 190 | MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 | ||
| 191 | MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 | ||
| 192 | MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 | ||
| 193 | MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 | ||
| 194 | MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 | ||
| 195 | MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 | ||
| 196 | MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 | ||
| 197 | MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 | ||
| 198 | MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 | ||
| 199 | >; | ||
| 200 | }; | ||
| 123 | }; | 201 | }; |
| 124 | }; | 202 | }; |
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index be1407cf5abd..121dadd125c0 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts | |||
| @@ -26,7 +26,7 @@ | |||
| 26 | crtcs = <&ipu 0>; | 26 | crtcs = <&ipu 0>; |
| 27 | interface-pix-fmt = "rgb24"; | 27 | interface-pix-fmt = "rgb24"; |
| 28 | pinctrl-names = "default"; | 28 | pinctrl-names = "default"; |
| 29 | pinctrl-0 = <&pinctrl_ipu_disp1_1>; | 29 | pinctrl-0 = <&pinctrl_ipu_disp1>; |
| 30 | display-timings { | 30 | display-timings { |
| 31 | native-mode = <&timing0>; | 31 | native-mode = <&timing0>; |
| 32 | timing0: dvi { | 32 | timing0: dvi { |
| @@ -48,7 +48,7 @@ | |||
| 48 | crtcs = <&ipu 1>; | 48 | crtcs = <&ipu 1>; |
| 49 | interface-pix-fmt = "rgb565"; | 49 | interface-pix-fmt = "rgb565"; |
| 50 | pinctrl-names = "default"; | 50 | pinctrl-names = "default"; |
| 51 | pinctrl-0 = <&pinctrl_ipu_disp2_1>; | 51 | pinctrl-0 = <&pinctrl_ipu_disp2>; |
| 52 | status = "disabled"; | 52 | status = "disabled"; |
| 53 | display-timings { | 53 | display-timings { |
| 54 | native-mode = <&timing1>; | 54 | native-mode = <&timing1>; |
| @@ -75,12 +75,23 @@ | |||
| 75 | 75 | ||
| 76 | power { | 76 | power { |
| 77 | label = "Power Button"; | 77 | label = "Power Button"; |
| 78 | gpios = <&gpio2 21 0>; | 78 | gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; |
| 79 | linux,code = <116>; /* KEY_POWER */ | 79 | linux,code = <116>; /* KEY_POWER */ |
| 80 | gpio-key,wakeup; | 80 | gpio-key,wakeup; |
| 81 | }; | 81 | }; |
| 82 | }; | 82 | }; |
| 83 | 83 | ||
| 84 | leds { | ||
| 85 | compatible = "gpio-leds"; | ||
| 86 | pinctrl-names = "default"; | ||
| 87 | pinctrl-0 = <&pinctrl_gpio_leds>; | ||
| 88 | |||
| 89 | led-diagnostic { | ||
| 90 | label = "diagnostic"; | ||
| 91 | gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; | ||
| 92 | }; | ||
| 93 | }; | ||
| 94 | |||
| 84 | sound { | 95 | sound { |
| 85 | compatible = "fsl,imx51-babbage-sgtl5000", | 96 | compatible = "fsl,imx51-babbage-sgtl5000", |
| 86 | "fsl,imx-audio-sgtl5000"; | 97 | "fsl,imx-audio-sgtl5000"; |
| @@ -105,14 +116,14 @@ | |||
| 105 | reg=<0>; | 116 | reg=<0>; |
| 106 | #clock-cells = <0>; | 117 | #clock-cells = <0>; |
| 107 | clock-frequency = <26000000>; | 118 | clock-frequency = <26000000>; |
| 108 | gpios = <&gpio4 26 1>; | 119 | gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; |
| 109 | }; | 120 | }; |
| 110 | }; | 121 | }; |
| 111 | }; | 122 | }; |
| 112 | 123 | ||
| 113 | &esdhc1 { | 124 | &esdhc1 { |
| 114 | pinctrl-names = "default"; | 125 | pinctrl-names = "default"; |
| 115 | pinctrl-0 = <&pinctrl_esdhc1_1>; | 126 | pinctrl-0 = <&pinctrl_esdhc1>; |
| 116 | fsl,cd-controller; | 127 | fsl,cd-controller; |
| 117 | fsl,wp-controller; | 128 | fsl,wp-controller; |
| 118 | status = "okay"; | 129 | status = "okay"; |
| @@ -120,24 +131,25 @@ | |||
| 120 | 131 | ||
| 121 | &esdhc2 { | 132 | &esdhc2 { |
| 122 | pinctrl-names = "default"; | 133 | pinctrl-names = "default"; |
| 123 | pinctrl-0 = <&pinctrl_esdhc2_1>; | 134 | pinctrl-0 = <&pinctrl_esdhc2>; |
| 124 | cd-gpios = <&gpio1 6 0>; | 135 | cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; |
| 125 | wp-gpios = <&gpio1 5 0>; | 136 | wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; |
| 126 | status = "okay"; | 137 | status = "okay"; |
| 127 | }; | 138 | }; |
| 128 | 139 | ||
| 129 | &uart3 { | 140 | &uart3 { |
| 130 | pinctrl-names = "default"; | 141 | pinctrl-names = "default"; |
| 131 | pinctrl-0 = <&pinctrl_uart3_1 &pinctrl_uart3_rtscts_1>; | 142 | pinctrl-0 = <&pinctrl_uart3>; |
| 132 | fsl,uart-has-rtscts; | 143 | fsl,uart-has-rtscts; |
| 133 | status = "okay"; | 144 | status = "okay"; |
| 134 | }; | 145 | }; |
| 135 | 146 | ||
| 136 | &ecspi1 { | 147 | &ecspi1 { |
| 137 | pinctrl-names = "default"; | 148 | pinctrl-names = "default"; |
| 138 | pinctrl-0 = <&pinctrl_ecspi1_1>; | 149 | pinctrl-0 = <&pinctrl_ecspi1>; |
| 139 | fsl,spi-num-chipselects = <2>; | 150 | fsl,spi-num-chipselects = <2>; |
| 140 | cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>; | 151 | cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, |
| 152 | <&gpio4 25 GPIO_ACTIVE_LOW>; | ||
| 141 | status = "okay"; | 153 | status = "okay"; |
| 142 | 154 | ||
| 143 | pmic: mc13892@0 { | 155 | pmic: mc13892@0 { |
| @@ -148,7 +160,7 @@ | |||
| 148 | spi-cs-high; | 160 | spi-cs-high; |
| 149 | reg = <0>; | 161 | reg = <0>; |
| 150 | interrupt-parent = <&gpio1>; | 162 | interrupt-parent = <&gpio1>; |
| 151 | interrupts = <8 0x4>; | 163 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; |
| 152 | 164 | ||
| 153 | regulators { | 165 | regulators { |
| 154 | sw1_reg: sw1 { | 166 | sw1_reg: sw1 { |
| @@ -267,7 +279,7 @@ | |||
| 267 | pinctrl-names = "default"; | 279 | pinctrl-names = "default"; |
| 268 | pinctrl-0 = <&pinctrl_hog>; | 280 | pinctrl-0 = <&pinctrl_hog>; |
| 269 | 281 | ||
| 270 | hog { | 282 | imx51-babbage { |
| 271 | pinctrl_hog: hoggrp { | 283 | pinctrl_hog: hoggrp { |
| 272 | fsl,pins = < | 284 | fsl,pins = < |
| 273 | MX51_PAD_GPIO1_0__SD1_CD 0x20d5 | 285 | MX51_PAD_GPIO1_0__SD1_CD 0x20d5 |
| @@ -280,25 +292,194 @@ | |||
| 280 | MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000 | 292 | MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000 |
| 281 | >; | 293 | >; |
| 282 | }; | 294 | }; |
| 295 | |||
| 296 | pinctrl_audmux: audmuxgrp { | ||
| 297 | fsl,pins = < | ||
| 298 | MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 | ||
| 299 | MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 | ||
| 300 | MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 | ||
| 301 | MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 | ||
| 302 | >; | ||
| 303 | }; | ||
| 304 | |||
| 305 | pinctrl_ecspi1: ecspi1grp { | ||
| 306 | fsl,pins = < | ||
| 307 | MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 | ||
| 308 | MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 | ||
| 309 | MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 | ||
| 310 | >; | ||
| 311 | }; | ||
| 312 | |||
| 313 | pinctrl_esdhc1: esdhc1grp { | ||
| 314 | fsl,pins = < | ||
| 315 | MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 | ||
| 316 | MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 | ||
| 317 | MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 | ||
| 318 | MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 | ||
| 319 | MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 | ||
| 320 | MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 | ||
| 321 | >; | ||
| 322 | }; | ||
| 323 | |||
| 324 | pinctrl_esdhc2: esdhc2grp { | ||
| 325 | fsl,pins = < | ||
| 326 | MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 | ||
| 327 | MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 | ||
| 328 | MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 | ||
| 329 | MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 | ||
| 330 | MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 | ||
| 331 | MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 | ||
| 332 | >; | ||
| 333 | }; | ||
| 334 | |||
| 335 | pinctrl_fec: fecgrp { | ||
| 336 | fsl,pins = < | ||
| 337 | MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000 | ||
| 338 | MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000 | ||
| 339 | MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000 | ||
| 340 | MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000 | ||
| 341 | MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000 | ||
| 342 | MX51_PAD_EIM_CS5__FEC_CRS 0x80000000 | ||
| 343 | MX51_PAD_NANDF_RB2__FEC_COL 0x80000000 | ||
| 344 | MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000 | ||
| 345 | MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000 | ||
| 346 | MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000 | ||
| 347 | MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000 | ||
| 348 | MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000 | ||
| 349 | MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000 | ||
| 350 | MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000 | ||
| 351 | MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000 | ||
| 352 | MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000 | ||
| 353 | MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000 | ||
| 354 | MX51_PAD_EIM_A20__GPIO2_14 0x85 /* Reset */ | ||
| 355 | >; | ||
| 356 | }; | ||
| 357 | |||
| 358 | pinctrl_gpio_leds: gpioledsgrp { | ||
| 359 | fsl,pins = < | ||
| 360 | MX51_PAD_EIM_D22__GPIO2_6 0x80000000 | ||
| 361 | >; | ||
| 362 | }; | ||
| 363 | |||
| 364 | pinctrl_i2c2: i2c2grp { | ||
| 365 | fsl,pins = < | ||
| 366 | MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed | ||
| 367 | MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed | ||
| 368 | >; | ||
| 369 | }; | ||
| 370 | |||
| 371 | pinctrl_ipu_disp1: ipudisp1grp { | ||
| 372 | fsl,pins = < | ||
| 373 | MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 | ||
| 374 | MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 | ||
| 375 | MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 | ||
| 376 | MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 | ||
| 377 | MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 | ||
| 378 | MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 | ||
| 379 | MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 | ||
| 380 | MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 | ||
| 381 | MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 | ||
| 382 | MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 | ||
| 383 | MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 | ||
| 384 | MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 | ||
| 385 | MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 | ||
| 386 | MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 | ||
| 387 | MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 | ||
| 388 | MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 | ||
| 389 | MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 | ||
| 390 | MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 | ||
| 391 | MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 | ||
| 392 | MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 | ||
| 393 | MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 | ||
| 394 | MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 | ||
| 395 | MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 | ||
| 396 | MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 | ||
| 397 | MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 | ||
| 398 | MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 | ||
| 399 | >; | ||
| 400 | }; | ||
| 401 | |||
| 402 | pinctrl_ipu_disp2: ipudisp2grp { | ||
| 403 | fsl,pins = < | ||
| 404 | MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5 | ||
| 405 | MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5 | ||
| 406 | MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5 | ||
| 407 | MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5 | ||
| 408 | MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5 | ||
| 409 | MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5 | ||
| 410 | MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5 | ||
| 411 | MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5 | ||
| 412 | MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5 | ||
| 413 | MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5 | ||
| 414 | MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5 | ||
| 415 | MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5 | ||
| 416 | MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5 | ||
| 417 | MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5 | ||
| 418 | MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5 | ||
| 419 | MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5 | ||
| 420 | MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 | ||
| 421 | MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 | ||
| 422 | MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 | ||
| 423 | MX51_PAD_DI_GP4__DI2_PIN15 0x5 | ||
| 424 | >; | ||
| 425 | }; | ||
| 426 | |||
| 427 | pinctrl_kpp: kppgrp { | ||
| 428 | fsl,pins = < | ||
| 429 | MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0 | ||
| 430 | MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0 | ||
| 431 | MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0 | ||
| 432 | MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0 | ||
| 433 | MX51_PAD_KEY_COL0__KEY_COL0 0xe8 | ||
| 434 | MX51_PAD_KEY_COL1__KEY_COL1 0xe8 | ||
| 435 | MX51_PAD_KEY_COL2__KEY_COL2 0xe8 | ||
| 436 | MX51_PAD_KEY_COL3__KEY_COL3 0xe8 | ||
| 437 | >; | ||
| 438 | }; | ||
| 439 | |||
| 440 | pinctrl_uart1: uart1grp { | ||
| 441 | fsl,pins = < | ||
| 442 | MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 | ||
| 443 | MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 | ||
| 444 | MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 | ||
| 445 | MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 | ||
| 446 | >; | ||
| 447 | }; | ||
| 448 | |||
| 449 | pinctrl_uart2: uart2grp { | ||
| 450 | fsl,pins = < | ||
| 451 | MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 | ||
| 452 | MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 | ||
| 453 | >; | ||
| 454 | }; | ||
| 455 | |||
| 456 | pinctrl_uart3: uart3grp { | ||
| 457 | fsl,pins = < | ||
| 458 | MX51_PAD_EIM_D25__UART3_RXD 0x1c5 | ||
| 459 | MX51_PAD_EIM_D26__UART3_TXD 0x1c5 | ||
| 460 | MX51_PAD_EIM_D27__UART3_RTS 0x1c5 | ||
| 461 | MX51_PAD_EIM_D24__UART3_CTS 0x1c5 | ||
| 462 | >; | ||
| 463 | }; | ||
| 283 | }; | 464 | }; |
| 284 | }; | 465 | }; |
| 285 | 466 | ||
| 286 | &uart1 { | 467 | &uart1 { |
| 287 | pinctrl-names = "default"; | 468 | pinctrl-names = "default"; |
| 288 | pinctrl-0 = <&pinctrl_uart1_1 &pinctrl_uart1_rtscts_1>; | 469 | pinctrl-0 = <&pinctrl_uart1>; |
| 289 | fsl,uart-has-rtscts; | 470 | fsl,uart-has-rtscts; |
| 290 | status = "okay"; | 471 | status = "okay"; |
| 291 | }; | 472 | }; |
| 292 | 473 | ||
| 293 | &uart2 { | 474 | &uart2 { |
| 294 | pinctrl-names = "default"; | 475 | pinctrl-names = "default"; |
| 295 | pinctrl-0 = <&pinctrl_uart2_1>; | 476 | pinctrl-0 = <&pinctrl_uart2>; |
| 296 | status = "okay"; | 477 | status = "okay"; |
| 297 | }; | 478 | }; |
| 298 | 479 | ||
| 299 | &i2c2 { | 480 | &i2c2 { |
| 300 | pinctrl-names = "default"; | 481 | pinctrl-names = "default"; |
| 301 | pinctrl-0 = <&pinctrl_i2c2_1>; | 482 | pinctrl-0 = <&pinctrl_i2c2>; |
| 302 | status = "okay"; | 483 | status = "okay"; |
| 303 | 484 | ||
| 304 | sgtl5000: codec@0a { | 485 | sgtl5000: codec@0a { |
| @@ -312,35 +493,39 @@ | |||
| 312 | 493 | ||
| 313 | &audmux { | 494 | &audmux { |
| 314 | pinctrl-names = "default"; | 495 | pinctrl-names = "default"; |
| 315 | pinctrl-0 = <&pinctrl_audmux_1>; | 496 | pinctrl-0 = <&pinctrl_audmux>; |
| 316 | status = "okay"; | 497 | status = "okay"; |
| 317 | }; | 498 | }; |
| 318 | 499 | ||
| 319 | &fec { | 500 | &fec { |
| 320 | pinctrl-names = "default"; | 501 | pinctrl-names = "default"; |
| 321 | pinctrl-0 = <&pinctrl_fec_1>; | 502 | pinctrl-0 = <&pinctrl_fec>; |
| 322 | phy-mode = "mii"; | 503 | phy-mode = "mii"; |
| 504 | phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; | ||
| 505 | phy-reset-duration = <1>; | ||
| 323 | status = "okay"; | 506 | status = "okay"; |
| 324 | }; | 507 | }; |
| 325 | 508 | ||
| 326 | &kpp { | 509 | &kpp { |
| 327 | pinctrl-names = "default"; | 510 | pinctrl-names = "default"; |
| 328 | pinctrl-0 = <&pinctrl_kpp_1>; | 511 | pinctrl-0 = <&pinctrl_kpp>; |
| 329 | linux,keymap = <0x00000067 /* KEY_UP */ | 512 | linux,keymap = < |
| 330 | 0x0001006c /* KEY_DOWN */ | 513 | MATRIX_KEY(0, 0, KEY_UP) |
| 331 | 0x00020072 /* KEY_VOLUMEDOWN */ | 514 | MATRIX_KEY(0, 1, KEY_DOWN) |
| 332 | 0x00030066 /* KEY_HOME */ | 515 | MATRIX_KEY(0, 2, KEY_VOLUMEDOWN) |
| 333 | 0x0100006a /* KEY_RIGHT */ | 516 | MATRIX_KEY(0, 3, KEY_HOME) |
| 334 | 0x01010069 /* KEY_LEFT */ | 517 | MATRIX_KEY(1, 0, KEY_RIGHT) |
| 335 | 0x0102001c /* KEY_ENTER */ | 518 | MATRIX_KEY(1, 1, KEY_LEFT) |
| 336 | 0x01030073 /* KEY_VOLUMEUP */ | 519 | MATRIX_KEY(1, 2, KEY_ENTER) |
| 337 | 0x02000040 /* KEY_F6 */ | 520 | MATRIX_KEY(1, 3, KEY_VOLUMEUP) |
| 338 | 0x02010042 /* KEY_F8 */ | 521 | MATRIX_KEY(2, 0, KEY_F6) |
| 339 | 0x02020043 /* KEY_F9 */ | 522 | MATRIX_KEY(2, 1, KEY_F8) |
| 340 | 0x02030044 /* KEY_F10 */ | 523 | MATRIX_KEY(2, 2, KEY_F9) |
| 341 | 0x0300003b /* KEY_F1 */ | 524 | MATRIX_KEY(2, 3, KEY_F10) |
| 342 | 0x0301003c /* KEY_F2 */ | 525 | MATRIX_KEY(3, 0, KEY_F1) |
| 343 | 0x0302003d /* KEY_F3 */ | 526 | MATRIX_KEY(3, 1, KEY_F2) |
| 344 | 0x03030074>; /* KEY_POWER */ | 527 | MATRIX_KEY(3, 2, KEY_F3) |
| 528 | MATRIX_KEY(3, 3, KEY_POWER) | ||
| 529 | >; | ||
| 345 | status = "okay"; | 530 | status = "okay"; |
| 346 | }; | 531 | }; |
diff --git a/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi b/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi new file mode 100644 index 000000000000..9b3acf6e4282 --- /dev/null +++ b/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi | |||
| @@ -0,0 +1,93 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Eukréa Electromatique <denis@eukrea.com> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation; either version 2 | ||
| 7 | * of the License, or (at your option) any later version. | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | * | ||
| 13 | * You should have received a copy of the GNU General Public License | ||
| 14 | * along with this program; if not, write to the Free Software | ||
| 15 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 16 | * MA 02110-1301, USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include "imx51.dtsi" | ||
| 20 | |||
| 21 | / { | ||
| 22 | model = "Eukrea CPUIMX51"; | ||
| 23 | compatible = "eukrea,cpuimx51", "fsl,imx51"; | ||
| 24 | |||
| 25 | memory { | ||
| 26 | reg = <0x90000000 0x10000000>; /* 256M */ | ||
| 27 | }; | ||
| 28 | }; | ||
| 29 | |||
| 30 | &fec { | ||
| 31 | pinctrl-names = "default"; | ||
| 32 | pinctrl-0 = <&pinctrl_fec>; | ||
| 33 | status = "okay"; | ||
| 34 | }; | ||
| 35 | |||
| 36 | &i2c1 { | ||
| 37 | pinctrl-names = "default"; | ||
| 38 | pinctrl-0 = <&pinctrl_i2c1>; | ||
| 39 | status = "okay"; | ||
| 40 | |||
| 41 | pcf8563@51 { | ||
| 42 | compatible = "nxp,pcf8563"; | ||
| 43 | reg = <0x51>; | ||
| 44 | }; | ||
| 45 | }; | ||
| 46 | |||
| 47 | &iomuxc { | ||
| 48 | imx51-eukrea { | ||
| 49 | pinctrl_tsc2007_1: tsc2007grp-1 { | ||
| 50 | fsl,pins = < | ||
| 51 | MX51_PAD_GPIO_NAND__GPIO_NAND 0x1f5 | ||
| 52 | MX51_PAD_NANDF_D8__GPIO4_0 0x1f5 | ||
| 53 | >; | ||
| 54 | }; | ||
| 55 | |||
| 56 | pinctrl_fec: fecgrp { | ||
| 57 | fsl,pins = < | ||
| 58 | MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 | ||
| 59 | MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 | ||
| 60 | MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 | ||
| 61 | MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 | ||
| 62 | MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 | ||
| 63 | MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 | ||
| 64 | MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 | ||
| 65 | MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 | ||
| 66 | MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 | ||
| 67 | MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 | ||
| 68 | MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 | ||
| 69 | MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 | ||
| 70 | MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 | ||
| 71 | MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 | ||
| 72 | MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 | ||
| 73 | MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 | ||
| 74 | MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 | ||
| 75 | MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 | ||
| 76 | >; | ||
| 77 | }; | ||
| 78 | |||
| 79 | pinctrl_i2c1: i2c1grp { | ||
| 80 | fsl,pins = < | ||
| 81 | MX51_PAD_SD2_CMD__I2C1_SCL 0x400001ed | ||
| 82 | MX51_PAD_SD2_CLK__I2C1_SDA 0x400001ed | ||
| 83 | >; | ||
| 84 | }; | ||
| 85 | }; | ||
| 86 | }; | ||
| 87 | |||
| 88 | &nfc { | ||
| 89 | nand-bus-width = <8>; | ||
| 90 | nand-ecc-mode = "hw"; | ||
| 91 | nand-on-flash-bbt; | ||
| 92 | status = "okay"; | ||
| 93 | }; | ||
diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts new file mode 100644 index 000000000000..5cec4f322096 --- /dev/null +++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts | |||
| @@ -0,0 +1,175 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Eukréa Electromatique <denis@eukrea.com> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation; either version 2 | ||
| 7 | * of the License, or (at your option) any later version. | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | * | ||
| 13 | * You should have received a copy of the GNU General Public License | ||
| 14 | * along with this program; if not, write to the Free Software | ||
| 15 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 16 | * MA 02110-1301, USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | /dts-v1/; | ||
| 20 | #include "imx51-eukrea-cpuimx51.dtsi" | ||
| 21 | #include <dt-bindings/gpio/gpio.h> | ||
| 22 | |||
| 23 | / { | ||
| 24 | model = "Eukrea CPUIMX51"; | ||
| 25 | compatible = "eukrea,mbimxsd51","eukrea,cpuimx51", "fsl,imx51"; | ||
| 26 | |||
| 27 | gpio_keys { | ||
| 28 | compatible = "gpio-keys"; | ||
| 29 | pinctrl-names = "default"; | ||
| 30 | pinctrl-0 = <&pinctrl_gpiokeys_1>; | ||
| 31 | |||
| 32 | button-1 { | ||
| 33 | label = "BP1"; | ||
| 34 | gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; | ||
| 35 | linux,code = <256>; | ||
| 36 | gpio-key,wakeup; | ||
| 37 | linux,input-type = <1>; | ||
| 38 | }; | ||
| 39 | }; | ||
| 40 | |||
| 41 | leds { | ||
| 42 | compatible = "gpio-leds"; | ||
| 43 | pinctrl-names = "default"; | ||
| 44 | pinctrl-0 = <&pinctrl_gpioled>; | ||
| 45 | |||
| 46 | led1 { | ||
| 47 | label = "led1"; | ||
| 48 | gpios = <&gpio3 30 GPIO_ACTIVE_LOW>; | ||
| 49 | linux,default-trigger = "heartbeat"; | ||
| 50 | }; | ||
| 51 | }; | ||
| 52 | |||
| 53 | sound { | ||
| 54 | compatible = "eukrea,asoc-tlv320"; | ||
| 55 | eukrea,model = "imx51-eukrea-tlv320aic23"; | ||
| 56 | ssi-controller = <&ssi2>; | ||
| 57 | fsl,mux-int-port = <2>; | ||
| 58 | fsl,mux-ext-port = <3>; | ||
| 59 | }; | ||
| 60 | }; | ||
| 61 | |||
| 62 | &audmux { | ||
| 63 | pinctrl-names = "default"; | ||
| 64 | pinctrl-0 = <&pinctrl_audmux>; | ||
| 65 | status = "okay"; | ||
| 66 | }; | ||
| 67 | |||
| 68 | &esdhc1 { | ||
| 69 | pinctrl-names = "default"; | ||
| 70 | pinctrl-0 = <&pinctrl_esdhc1 &pinctrl_esdhc1_cd>; | ||
| 71 | fsl,cd-controller; | ||
| 72 | status = "okay"; | ||
| 73 | }; | ||
| 74 | |||
| 75 | &i2c1 { | ||
| 76 | tlv320aic23: codec@1a { | ||
| 77 | compatible = "ti,tlv320aic23"; | ||
| 78 | reg = <0x1a>; | ||
| 79 | }; | ||
| 80 | }; | ||
| 81 | |||
| 82 | &iomuxc { | ||
| 83 | imx51-eukrea { | ||
| 84 | pinctrl_audmux: audmuxgrp { | ||
| 85 | fsl,pins = < | ||
| 86 | MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 | ||
| 87 | MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 | ||
| 88 | MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 | ||
| 89 | MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 | ||
| 90 | >; | ||
| 91 | }; | ||
| 92 | |||
| 93 | pinctrl_esdhc1: esdhc1grp { | ||
| 94 | fsl,pins = < | ||
| 95 | MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 | ||
| 96 | MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 | ||
| 97 | MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 | ||
| 98 | MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 | ||
| 99 | MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 | ||
| 100 | MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 | ||
| 101 | >; | ||
| 102 | }; | ||
| 103 | |||
| 104 | pinctrl_uart1: uart1grp { | ||
| 105 | fsl,pins = < | ||
| 106 | MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 | ||
| 107 | MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 | ||
| 108 | >; | ||
| 109 | }; | ||
| 110 | |||
| 111 | pinctrl_uart3: uart3grp { | ||
| 112 | fsl,pins = < | ||
| 113 | MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 | ||
| 114 | MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 | ||
| 115 | >; | ||
| 116 | }; | ||
| 117 | |||
| 118 | pinctrl_uart3_rtscts: uart3rtsctsgrp { | ||
| 119 | fsl,pins = < | ||
| 120 | MX51_PAD_KEY_COL4__UART3_RTS 0x1c5 | ||
| 121 | MX51_PAD_KEY_COL5__UART3_CTS 0x1c5 | ||
| 122 | >; | ||
| 123 | }; | ||
| 124 | |||
| 125 | pinctrl_backlight_1: backlightgrp-1 { | ||
| 126 | fsl,pins = < | ||
| 127 | MX51_PAD_DI1_D1_CS__GPIO3_4 0x1f5 | ||
| 128 | >; | ||
| 129 | }; | ||
| 130 | |||
| 131 | pinctrl_esdhc1_cd: esdhc1_cd { | ||
| 132 | fsl,pins = < | ||
| 133 | MX51_PAD_GPIO1_0__SD1_CD 0x20d5 | ||
| 134 | >; | ||
| 135 | }; | ||
| 136 | |||
| 137 | pinctrl_gpiokeys_1: gpiokeysgrp-1 { | ||
| 138 | fsl,pins = < | ||
| 139 | MX51_PAD_NANDF_D9__GPIO3_31 0x1f5 | ||
| 140 | >; | ||
| 141 | }; | ||
| 142 | |||
| 143 | pinctrl_gpioled: gpioledgrp-1 { | ||
| 144 | fsl,pins = < | ||
| 145 | MX51_PAD_NANDF_D10__GPIO3_30 0x80000000 | ||
| 146 | >; | ||
| 147 | }; | ||
| 148 | |||
| 149 | pinctrl_reg_lcd_3v3: reg_lcd_3v3 { | ||
| 150 | fsl,pins = < | ||
| 151 | MX51_PAD_CSI1_D9__GPIO3_13 0x1f5 | ||
| 152 | >; | ||
| 153 | }; | ||
| 154 | }; | ||
| 155 | }; | ||
| 156 | |||
| 157 | &ssi2 { | ||
| 158 | codec-handle = <&tlv320aic23>; | ||
| 159 | fsl,mode = "i2s-slave"; | ||
| 160 | status = "okay"; | ||
| 161 | }; | ||
| 162 | |||
| 163 | &uart1 { | ||
| 164 | pinctrl-names = "default"; | ||
| 165 | pinctrl-0 = <&pinctrl_uart1>; | ||
| 166 | fsl,uart-has-rtscts; | ||
| 167 | status = "okay"; | ||
| 168 | }; | ||
| 169 | |||
| 170 | &uart3 { | ||
| 171 | pinctrl-names = "default"; | ||
| 172 | pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>; | ||
| 173 | fsl,uart-has-rtscts; | ||
| 174 | status = "okay"; | ||
| 175 | }; | ||
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 4bcdd3ad15e5..e4b07d1a9a56 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi | |||
| @@ -12,6 +12,10 @@ | |||
| 12 | 12 | ||
| 13 | #include "skeleton.dtsi" | 13 | #include "skeleton.dtsi" |
| 14 | #include "imx51-pinfunc.h" | 14 | #include "imx51-pinfunc.h" |
| 15 | #include <dt-bindings/clock/imx5-clock.h> | ||
| 16 | #include <dt-bindings/gpio/gpio.h> | ||
| 17 | #include <dt-bindings/input/input.h> | ||
| 18 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 15 | 19 | ||
| 16 | / { | 20 | / { |
| 17 | aliases { | 21 | aliases { |
| @@ -21,6 +25,10 @@ | |||
| 21 | gpio3 = &gpio4; | 25 | gpio3 = &gpio4; |
| 22 | i2c0 = &i2c1; | 26 | i2c0 = &i2c1; |
| 23 | i2c1 = &i2c2; | 27 | i2c1 = &i2c2; |
| 28 | mmc0 = &esdhc1; | ||
| 29 | mmc1 = &esdhc2; | ||
| 30 | mmc2 = &esdhc3; | ||
| 31 | mmc3 = &esdhc4; | ||
| 24 | serial0 = &uart1; | 32 | serial0 = &uart1; |
| 25 | serial1 = &uart2; | 33 | serial1 = &uart2; |
| 26 | serial2 = &uart3; | 34 | serial2 = &uart3; |
| @@ -64,18 +72,32 @@ | |||
| 64 | cpus { | 72 | cpus { |
| 65 | #address-cells = <1>; | 73 | #address-cells = <1>; |
| 66 | #size-cells = <0>; | 74 | #size-cells = <0>; |
| 67 | cpu@0 { | 75 | cpu: cpu@0 { |
| 68 | device_type = "cpu"; | 76 | device_type = "cpu"; |
| 69 | compatible = "arm,cortex-a8"; | 77 | compatible = "arm,cortex-a8"; |
| 70 | reg = <0>; | 78 | reg = <0>; |
| 71 | clock-latency = <61036>; /* two CLK32 periods */ | 79 | clock-latency = <62500>; |
| 72 | clocks = <&clks 24>; | 80 | clocks = <&clks IMX5_CLK_CPU_PODF>; |
| 73 | clock-names = "cpu"; | 81 | clock-names = "cpu"; |
| 74 | operating-points = < | 82 | operating-points = < |
| 75 | /* kHz uV (No regulator support) */ | 83 | 166000 1000000 |
| 76 | 160000 0 | 84 | 600000 1050000 |
| 77 | 800000 0 | 85 | 800000 1100000 |
| 78 | >; | 86 | >; |
| 87 | voltage-tolerance = <5>; | ||
| 88 | }; | ||
| 89 | }; | ||
| 90 | |||
| 91 | usbphy { | ||
| 92 | #address-cells = <1>; | ||
| 93 | #size-cells = <0>; | ||
| 94 | compatible = "simple-bus"; | ||
| 95 | |||
| 96 | usbphy0: usbphy@0 { | ||
| 97 | compatible = "usb-nop-xceiv"; | ||
| 98 | reg = <0>; | ||
| 99 | clocks = <&clks IMX5_CLK_USB_PHY_GATE>; | ||
| 100 | clock-names = "main_clk"; | ||
| 79 | }; | 101 | }; |
| 80 | }; | 102 | }; |
| 81 | 103 | ||
| @@ -96,7 +118,9 @@ | |||
| 96 | compatible = "fsl,imx51-ipu"; | 118 | compatible = "fsl,imx51-ipu"; |
| 97 | reg = <0x40000000 0x20000000>; | 119 | reg = <0x40000000 0x20000000>; |
| 98 | interrupts = <11 10>; | 120 | interrupts = <11 10>; |
| 99 | clocks = <&clks 59>, <&clks 110>, <&clks 61>; | 121 | clocks = <&clks IMX5_CLK_IPU_GATE>, |
| 122 | <&clks IMX5_CLK_IPU_DI0_GATE>, | ||
| 123 | <&clks IMX5_CLK_IPU_DI1_GATE>; | ||
| 100 | clock-names = "bus", "di0", "di1"; | 124 | clock-names = "bus", "di0", "di1"; |
| 101 | resets = <&src 2>; | 125 | resets = <&src 2>; |
| 102 | }; | 126 | }; |
| @@ -119,7 +143,9 @@ | |||
| 119 | compatible = "fsl,imx51-esdhc"; | 143 | compatible = "fsl,imx51-esdhc"; |
| 120 | reg = <0x70004000 0x4000>; | 144 | reg = <0x70004000 0x4000>; |
| 121 | interrupts = <1>; | 145 | interrupts = <1>; |
| 122 | clocks = <&clks 44>, <&clks 0>, <&clks 71>; | 146 | clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, |
| 147 | <&clks IMX5_CLK_DUMMY>, | ||
| 148 | <&clks IMX5_CLK_ESDHC1_PER_GATE>; | ||
| 123 | clock-names = "ipg", "ahb", "per"; | 149 | clock-names = "ipg", "ahb", "per"; |
| 124 | status = "disabled"; | 150 | status = "disabled"; |
| 125 | }; | 151 | }; |
| @@ -128,7 +154,9 @@ | |||
| 128 | compatible = "fsl,imx51-esdhc"; | 154 | compatible = "fsl,imx51-esdhc"; |
| 129 | reg = <0x70008000 0x4000>; | 155 | reg = <0x70008000 0x4000>; |
| 130 | interrupts = <2>; | 156 | interrupts = <2>; |
| 131 | clocks = <&clks 45>, <&clks 0>, <&clks 72>; | 157 | clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, |
| 158 | <&clks IMX5_CLK_DUMMY>, | ||
| 159 | <&clks IMX5_CLK_ESDHC2_PER_GATE>; | ||
| 132 | clock-names = "ipg", "ahb", "per"; | 160 | clock-names = "ipg", "ahb", "per"; |
| 133 | bus-width = <4>; | 161 | bus-width = <4>; |
| 134 | status = "disabled"; | 162 | status = "disabled"; |
| @@ -138,7 +166,8 @@ | |||
| 138 | compatible = "fsl,imx51-uart", "fsl,imx21-uart"; | 166 | compatible = "fsl,imx51-uart", "fsl,imx21-uart"; |
| 139 | reg = <0x7000c000 0x4000>; | 167 | reg = <0x7000c000 0x4000>; |
| 140 | interrupts = <33>; | 168 | interrupts = <33>; |
| 141 | clocks = <&clks 32>, <&clks 33>; | 169 | clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, |
| 170 | <&clks IMX5_CLK_UART3_PER_GATE>; | ||
| 142 | clock-names = "ipg", "per"; | 171 | clock-names = "ipg", "per"; |
| 143 | status = "disabled"; | 172 | status = "disabled"; |
| 144 | }; | 173 | }; |
| @@ -149,7 +178,8 @@ | |||
| 149 | compatible = "fsl,imx51-ecspi"; | 178 | compatible = "fsl,imx51-ecspi"; |
| 150 | reg = <0x70010000 0x4000>; | 179 | reg = <0x70010000 0x4000>; |
| 151 | interrupts = <36>; | 180 | interrupts = <36>; |
| 152 | clocks = <&clks 51>, <&clks 52>; | 181 | clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, |
| 182 | <&clks IMX5_CLK_ECSPI1_PER_GATE>; | ||
| 153 | clock-names = "ipg", "per"; | 183 | clock-names = "ipg", "per"; |
| 154 | status = "disabled"; | 184 | status = "disabled"; |
| 155 | }; | 185 | }; |
| @@ -158,7 +188,7 @@ | |||
| 158 | compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; | 188 | compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; |
| 159 | reg = <0x70014000 0x4000>; | 189 | reg = <0x70014000 0x4000>; |
| 160 | interrupts = <30>; | 190 | interrupts = <30>; |
| 161 | clocks = <&clks 49>; | 191 | clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>; |
| 162 | dmas = <&sdma 24 1 0>, | 192 | dmas = <&sdma 24 1 0>, |
| 163 | <&sdma 25 1 0>; | 193 | <&sdma 25 1 0>; |
| 164 | dma-names = "rx", "tx"; | 194 | dma-names = "rx", "tx"; |
| @@ -171,7 +201,9 @@ | |||
| 171 | compatible = "fsl,imx51-esdhc"; | 201 | compatible = "fsl,imx51-esdhc"; |
| 172 | reg = <0x70020000 0x4000>; | 202 | reg = <0x70020000 0x4000>; |
| 173 | interrupts = <3>; | 203 | interrupts = <3>; |
| 174 | clocks = <&clks 46>, <&clks 0>, <&clks 73>; | 204 | clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, |
| 205 | <&clks IMX5_CLK_DUMMY>, | ||
| 206 | <&clks IMX5_CLK_ESDHC3_PER_GATE>; | ||
| 175 | clock-names = "ipg", "ahb", "per"; | 207 | clock-names = "ipg", "ahb", "per"; |
| 176 | bus-width = <4>; | 208 | bus-width = <4>; |
| 177 | status = "disabled"; | 209 | status = "disabled"; |
| @@ -181,25 +213,20 @@ | |||
| 181 | compatible = "fsl,imx51-esdhc"; | 213 | compatible = "fsl,imx51-esdhc"; |
| 182 | reg = <0x70024000 0x4000>; | 214 | reg = <0x70024000 0x4000>; |
| 183 | interrupts = <4>; | 215 | interrupts = <4>; |
| 184 | clocks = <&clks 47>, <&clks 0>, <&clks 74>; | 216 | clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, |
| 217 | <&clks IMX5_CLK_DUMMY>, | ||
| 218 | <&clks IMX5_CLK_ESDHC4_PER_GATE>; | ||
| 185 | clock-names = "ipg", "ahb", "per"; | 219 | clock-names = "ipg", "ahb", "per"; |
| 186 | bus-width = <4>; | 220 | bus-width = <4>; |
| 187 | status = "disabled"; | 221 | status = "disabled"; |
| 188 | }; | 222 | }; |
| 189 | }; | 223 | }; |
| 190 | 224 | ||
| 191 | usbphy0: usbphy@0 { | ||
| 192 | compatible = "usb-nop-xceiv"; | ||
| 193 | clocks = <&clks 75>; | ||
| 194 | clock-names = "main_clk"; | ||
| 195 | status = "okay"; | ||
| 196 | }; | ||
| 197 | |||
| 198 | usbotg: usb@73f80000 { | 225 | usbotg: usb@73f80000 { |
| 199 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; | 226 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; |
| 200 | reg = <0x73f80000 0x0200>; | 227 | reg = <0x73f80000 0x0200>; |
| 201 | interrupts = <18>; | 228 | interrupts = <18>; |
| 202 | clocks = <&clks 108>; | 229 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| 203 | fsl,usbmisc = <&usbmisc 0>; | 230 | fsl,usbmisc = <&usbmisc 0>; |
| 204 | fsl,usbphy = <&usbphy0>; | 231 | fsl,usbphy = <&usbphy0>; |
| 205 | status = "disabled"; | 232 | status = "disabled"; |
| @@ -209,7 +236,7 @@ | |||
| 209 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; | 236 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; |
| 210 | reg = <0x73f80200 0x0200>; | 237 | reg = <0x73f80200 0x0200>; |
| 211 | interrupts = <14>; | 238 | interrupts = <14>; |
| 212 | clocks = <&clks 108>; | 239 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| 213 | fsl,usbmisc = <&usbmisc 1>; | 240 | fsl,usbmisc = <&usbmisc 1>; |
| 214 | status = "disabled"; | 241 | status = "disabled"; |
| 215 | }; | 242 | }; |
| @@ -218,7 +245,7 @@ | |||
| 218 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; | 245 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; |
| 219 | reg = <0x73f80400 0x0200>; | 246 | reg = <0x73f80400 0x0200>; |
| 220 | interrupts = <16>; | 247 | interrupts = <16>; |
| 221 | clocks = <&clks 108>; | 248 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| 222 | fsl,usbmisc = <&usbmisc 2>; | 249 | fsl,usbmisc = <&usbmisc 2>; |
| 223 | status = "disabled"; | 250 | status = "disabled"; |
| 224 | }; | 251 | }; |
| @@ -227,7 +254,7 @@ | |||
| 227 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; | 254 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; |
| 228 | reg = <0x73f80600 0x0200>; | 255 | reg = <0x73f80600 0x0200>; |
| 229 | interrupts = <17>; | 256 | interrupts = <17>; |
| 230 | clocks = <&clks 108>; | 257 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| 231 | fsl,usbmisc = <&usbmisc 3>; | 258 | fsl,usbmisc = <&usbmisc 3>; |
| 232 | status = "disabled"; | 259 | status = "disabled"; |
| 233 | }; | 260 | }; |
| @@ -236,7 +263,7 @@ | |||
| 236 | #index-cells = <1>; | 263 | #index-cells = <1>; |
| 237 | compatible = "fsl,imx51-usbmisc"; | 264 | compatible = "fsl,imx51-usbmisc"; |
| 238 | reg = <0x73f80800 0x200>; | 265 | reg = <0x73f80800 0x200>; |
| 239 | clocks = <&clks 108>; | 266 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| 240 | }; | 267 | }; |
| 241 | 268 | ||
| 242 | gpio1: gpio@73f84000 { | 269 | gpio1: gpio@73f84000 { |
| @@ -283,7 +310,7 @@ | |||
| 283 | compatible = "fsl,imx51-kpp", "fsl,imx21-kpp"; | 310 | compatible = "fsl,imx51-kpp", "fsl,imx21-kpp"; |
| 284 | reg = <0x73f94000 0x4000>; | 311 | reg = <0x73f94000 0x4000>; |
| 285 | interrupts = <60>; | 312 | interrupts = <60>; |
| 286 | clocks = <&clks 0>; | 313 | clocks = <&clks IMX5_CLK_DUMMY>; |
| 287 | status = "disabled"; | 314 | status = "disabled"; |
| 288 | }; | 315 | }; |
| 289 | 316 | ||
| @@ -291,14 +318,14 @@ | |||
| 291 | compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; | 318 | compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; |
| 292 | reg = <0x73f98000 0x4000>; | 319 | reg = <0x73f98000 0x4000>; |
| 293 | interrupts = <58>; | 320 | interrupts = <58>; |
| 294 | clocks = <&clks 0>; | 321 | clocks = <&clks IMX5_CLK_DUMMY>; |
| 295 | }; | 322 | }; |
| 296 | 323 | ||
| 297 | wdog2: wdog@73f9c000 { | 324 | wdog2: wdog@73f9c000 { |
| 298 | compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; | 325 | compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; |
| 299 | reg = <0x73f9c000 0x4000>; | 326 | reg = <0x73f9c000 0x4000>; |
| 300 | interrupts = <59>; | 327 | interrupts = <59>; |
| 301 | clocks = <&clks 0>; | 328 | clocks = <&clks IMX5_CLK_DUMMY>; |
| 302 | status = "disabled"; | 329 | status = "disabled"; |
| 303 | }; | 330 | }; |
| 304 | 331 | ||
| @@ -306,7 +333,8 @@ | |||
| 306 | compatible = "fsl,imx51-gpt", "fsl,imx31-gpt"; | 333 | compatible = "fsl,imx51-gpt", "fsl,imx31-gpt"; |
| 307 | reg = <0x73fa0000 0x4000>; | 334 | reg = <0x73fa0000 0x4000>; |
| 308 | interrupts = <39>; | 335 | interrupts = <39>; |
| 309 | clocks = <&clks 36>, <&clks 41>; | 336 | clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, |
| 337 | <&clks IMX5_CLK_GPT_HF_GATE>; | ||
| 310 | clock-names = "ipg", "per"; | 338 | clock-names = "ipg", "per"; |
| 311 | }; | 339 | }; |
| 312 | 340 | ||
| @@ -319,7 +347,8 @@ | |||
| 319 | #pwm-cells = <2>; | 347 | #pwm-cells = <2>; |
| 320 | compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; | 348 | compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; |
| 321 | reg = <0x73fb4000 0x4000>; | 349 | reg = <0x73fb4000 0x4000>; |
| 322 | clocks = <&clks 37>, <&clks 38>; | 350 | clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, |
| 351 | <&clks IMX5_CLK_PWM1_HF_GATE>; | ||
| 323 | clock-names = "ipg", "per"; | 352 | clock-names = "ipg", "per"; |
| 324 | interrupts = <61>; | 353 | interrupts = <61>; |
| 325 | }; | 354 | }; |
| @@ -328,7 +357,8 @@ | |||
| 328 | #pwm-cells = <2>; | 357 | #pwm-cells = <2>; |
| 329 | compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; | 358 | compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; |
| 330 | reg = <0x73fb8000 0x4000>; | 359 | reg = <0x73fb8000 0x4000>; |
| 331 | clocks = <&clks 39>, <&clks 40>; | 360 | clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, |
| 361 | <&clks IMX5_CLK_PWM2_HF_GATE>; | ||
| 332 | clock-names = "ipg", "per"; | 362 | clock-names = "ipg", "per"; |
| 333 | interrupts = <94>; | 363 | interrupts = <94>; |
| 334 | }; | 364 | }; |
| @@ -337,7 +367,8 @@ | |||
| 337 | compatible = "fsl,imx51-uart", "fsl,imx21-uart"; | 367 | compatible = "fsl,imx51-uart", "fsl,imx21-uart"; |
| 338 | reg = <0x73fbc000 0x4000>; | 368 | reg = <0x73fbc000 0x4000>; |
| 339 | interrupts = <31>; | 369 | interrupts = <31>; |
| 340 | clocks = <&clks 28>, <&clks 29>; | 370 | clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, |
| 371 | <&clks IMX5_CLK_UART1_PER_GATE>; | ||
| 341 | clock-names = "ipg", "per"; | 372 | clock-names = "ipg", "per"; |
| 342 | status = "disabled"; | 373 | status = "disabled"; |
| 343 | }; | 374 | }; |
| @@ -346,7 +377,8 @@ | |||
| 346 | compatible = "fsl,imx51-uart", "fsl,imx21-uart"; | 377 | compatible = "fsl,imx51-uart", "fsl,imx21-uart"; |
| 347 | reg = <0x73fc0000 0x4000>; | 378 | reg = <0x73fc0000 0x4000>; |
| 348 | interrupts = <32>; | 379 | interrupts = <32>; |
| 349 | clocks = <&clks 30>, <&clks 31>; | 380 | clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, |
| 381 | <&clks IMX5_CLK_UART2_PER_GATE>; | ||
| 350 | clock-names = "ipg", "per"; | 382 | clock-names = "ipg", "per"; |
| 351 | status = "disabled"; | 383 | status = "disabled"; |
| 352 | }; | 384 | }; |
| @@ -376,14 +408,14 @@ | |||
| 376 | compatible = "fsl,imx51-iim", "fsl,imx27-iim"; | 408 | compatible = "fsl,imx51-iim", "fsl,imx27-iim"; |
| 377 | reg = <0x83f98000 0x4000>; | 409 | reg = <0x83f98000 0x4000>; |
| 378 | interrupts = <69>; | 410 | interrupts = <69>; |
| 379 | clocks = <&clks 107>; | 411 | clocks = <&clks IMX5_CLK_IIM_GATE>; |
| 380 | }; | 412 | }; |
| 381 | 413 | ||
| 382 | owire: owire@83fa4000 { | 414 | owire: owire@83fa4000 { |
| 383 | compatible = "fsl,imx51-owire", "fsl,imx21-owire"; | 415 | compatible = "fsl,imx51-owire", "fsl,imx21-owire"; |
| 384 | reg = <0x83fa4000 0x4000>; | 416 | reg = <0x83fa4000 0x4000>; |
| 385 | interrupts = <88>; | 417 | interrupts = <88>; |
| 386 | clocks = <&clks 159>; | 418 | clocks = <&clks IMX5_CLK_OWIRE_GATE>; |
| 387 | status = "disabled"; | 419 | status = "disabled"; |
| 388 | }; | 420 | }; |
| 389 | 421 | ||
| @@ -393,7 +425,8 @@ | |||
| 393 | compatible = "fsl,imx51-ecspi"; | 425 | compatible = "fsl,imx51-ecspi"; |
| 394 | reg = <0x83fac000 0x4000>; | 426 | reg = <0x83fac000 0x4000>; |
| 395 | interrupts = <37>; | 427 | interrupts = <37>; |
| 396 | clocks = <&clks 53>, <&clks 54>; | 428 | clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, |
| 429 | <&clks IMX5_CLK_ECSPI2_PER_GATE>; | ||
| 397 | clock-names = "ipg", "per"; | 430 | clock-names = "ipg", "per"; |
| 398 | status = "disabled"; | 431 | status = "disabled"; |
| 399 | }; | 432 | }; |
| @@ -402,7 +435,8 @@ | |||
| 402 | compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; | 435 | compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; |
| 403 | reg = <0x83fb0000 0x4000>; | 436 | reg = <0x83fb0000 0x4000>; |
| 404 | interrupts = <6>; | 437 | interrupts = <6>; |
| 405 | clocks = <&clks 56>, <&clks 56>; | 438 | clocks = <&clks IMX5_CLK_SDMA_GATE>, |
| 439 | <&clks IMX5_CLK_SDMA_GATE>; | ||
| 406 | clock-names = "ipg", "ahb"; | 440 | clock-names = "ipg", "ahb"; |
| 407 | #dma-cells = <3>; | 441 | #dma-cells = <3>; |
| 408 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; | 442 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; |
| @@ -414,7 +448,8 @@ | |||
| 414 | compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; | 448 | compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; |
| 415 | reg = <0x83fc0000 0x4000>; | 449 | reg = <0x83fc0000 0x4000>; |
| 416 | interrupts = <38>; | 450 | interrupts = <38>; |
| 417 | clocks = <&clks 55>, <&clks 55>; | 451 | clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, |
| 452 | <&clks IMX5_CLK_CSPI_IPG_GATE>; | ||
| 418 | clock-names = "ipg", "per"; | 453 | clock-names = "ipg", "per"; |
| 419 | status = "disabled"; | 454 | status = "disabled"; |
| 420 | }; | 455 | }; |
| @@ -425,7 +460,7 @@ | |||
| 425 | compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; | 460 | compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; |
| 426 | reg = <0x83fc4000 0x4000>; | 461 | reg = <0x83fc4000 0x4000>; |
| 427 | interrupts = <63>; | 462 | interrupts = <63>; |
| 428 | clocks = <&clks 35>; | 463 | clocks = <&clks IMX5_CLK_I2C2_GATE>; |
| 429 | status = "disabled"; | 464 | status = "disabled"; |
| 430 | }; | 465 | }; |
| 431 | 466 | ||
| @@ -435,7 +470,7 @@ | |||
| 435 | compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; | 470 | compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; |
| 436 | reg = <0x83fc8000 0x4000>; | 471 | reg = <0x83fc8000 0x4000>; |
| 437 | interrupts = <62>; | 472 | interrupts = <62>; |
| 438 | clocks = <&clks 34>; | 473 | clocks = <&clks IMX5_CLK_I2C1_GATE>; |
| 439 | status = "disabled"; | 474 | status = "disabled"; |
| 440 | }; | 475 | }; |
| 441 | 476 | ||
| @@ -443,7 +478,7 @@ | |||
| 443 | compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; | 478 | compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; |
| 444 | reg = <0x83fcc000 0x4000>; | 479 | reg = <0x83fcc000 0x4000>; |
| 445 | interrupts = <29>; | 480 | interrupts = <29>; |
| 446 | clocks = <&clks 48>; | 481 | clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>; |
| 447 | dmas = <&sdma 28 0 0>, | 482 | dmas = <&sdma 28 0 0>, |
| 448 | <&sdma 29 0 0>; | 483 | <&sdma 29 0 0>; |
| 449 | dma-names = "rx", "tx"; | 484 | dma-names = "rx", "tx"; |
| @@ -455,6 +490,8 @@ | |||
| 455 | audmux: audmux@83fd0000 { | 490 | audmux: audmux@83fd0000 { |
| 456 | compatible = "fsl,imx51-audmux", "fsl,imx31-audmux"; | 491 | compatible = "fsl,imx51-audmux", "fsl,imx31-audmux"; |
| 457 | reg = <0x83fd0000 0x4000>; | 492 | reg = <0x83fd0000 0x4000>; |
| 493 | clocks = <&clks IMX5_CLK_DUMMY>; | ||
| 494 | clock-names = "audmux"; | ||
| 458 | status = "disabled"; | 495 | status = "disabled"; |
| 459 | }; | 496 | }; |
| 460 | 497 | ||
| @@ -463,7 +500,7 @@ | |||
| 463 | #size-cells = <1>; | 500 | #size-cells = <1>; |
| 464 | compatible = "fsl,imx51-weim"; | 501 | compatible = "fsl,imx51-weim"; |
| 465 | reg = <0x83fda000 0x1000>; | 502 | reg = <0x83fda000 0x1000>; |
| 466 | clocks = <&clks 57>; | 503 | clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>; |
| 467 | ranges = < | 504 | ranges = < |
| 468 | 0 0 0xb0000000 0x08000000 | 505 | 0 0 0xb0000000 0x08000000 |
| 469 | 1 0 0xb8000000 0x08000000 | 506 | 1 0 0xb8000000 0x08000000 |
| @@ -479,7 +516,7 @@ | |||
| 479 | compatible = "fsl,imx51-nand"; | 516 | compatible = "fsl,imx51-nand"; |
| 480 | reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; | 517 | reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; |
| 481 | interrupts = <8>; | 518 | interrupts = <8>; |
| 482 | clocks = <&clks 60>; | 519 | clocks = <&clks IMX5_CLK_NFC_GATE>; |
| 483 | status = "disabled"; | 520 | status = "disabled"; |
| 484 | }; | 521 | }; |
| 485 | 522 | ||
| @@ -487,7 +524,7 @@ | |||
| 487 | compatible = "fsl,imx51-pata", "fsl,imx27-pata"; | 524 | compatible = "fsl,imx51-pata", "fsl,imx27-pata"; |
| 488 | reg = <0x83fe0000 0x4000>; | 525 | reg = <0x83fe0000 0x4000>; |
| 489 | interrupts = <70>; | 526 | interrupts = <70>; |
| 490 | clocks = <&clks 172>; | 527 | clocks = <&clks IMX5_CLK_PATA_GATE>; |
| 491 | status = "disabled"; | 528 | status = "disabled"; |
| 492 | }; | 529 | }; |
| 493 | 530 | ||
| @@ -495,7 +532,7 @@ | |||
| 495 | compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; | 532 | compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; |
| 496 | reg = <0x83fe8000 0x4000>; | 533 | reg = <0x83fe8000 0x4000>; |
| 497 | interrupts = <96>; | 534 | interrupts = <96>; |
| 498 | clocks = <&clks 50>; | 535 | clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>; |
| 499 | dmas = <&sdma 46 0 0>, | 536 | dmas = <&sdma 46 0 0>, |
| 500 | <&sdma 47 0 0>; | 537 | <&sdma 47 0 0>; |
| 501 | dma-names = "rx", "tx"; | 538 | dma-names = "rx", "tx"; |
| @@ -508,336 +545,12 @@ | |||
| 508 | compatible = "fsl,imx51-fec", "fsl,imx27-fec"; | 545 | compatible = "fsl,imx51-fec", "fsl,imx27-fec"; |
| 509 | reg = <0x83fec000 0x4000>; | 546 | reg = <0x83fec000 0x4000>; |
| 510 | interrupts = <87>; | 547 | interrupts = <87>; |
| 511 | clocks = <&clks 42>, <&clks 42>, <&clks 42>; | 548 | clocks = <&clks IMX5_CLK_FEC_GATE>, |
| 549 | <&clks IMX5_CLK_FEC_GATE>, | ||
| 550 | <&clks IMX5_CLK_FEC_GATE>; | ||
| 512 | clock-names = "ipg", "ahb", "ptp"; | 551 | clock-names = "ipg", "ahb", "ptp"; |
| 513 | status = "disabled"; | 552 | status = "disabled"; |
| 514 | }; | 553 | }; |
| 515 | }; | 554 | }; |
| 516 | }; | 555 | }; |
| 517 | }; | 556 | }; |
| 518 | |||
| 519 | &iomuxc { | ||
| 520 | audmux { | ||
| 521 | pinctrl_audmux_1: audmuxgrp-1 { | ||
| 522 | fsl,pins = < | ||
| 523 | MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 | ||
| 524 | MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 | ||
| 525 | MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 | ||
| 526 | MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 | ||
| 527 | >; | ||
| 528 | }; | ||
| 529 | }; | ||
| 530 | |||
| 531 | fec { | ||
| 532 | pinctrl_fec_1: fecgrp-1 { | ||
| 533 | fsl,pins = < | ||
| 534 | MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000 | ||
| 535 | MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000 | ||
| 536 | MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000 | ||
| 537 | MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000 | ||
| 538 | MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000 | ||
| 539 | MX51_PAD_EIM_CS5__FEC_CRS 0x80000000 | ||
| 540 | MX51_PAD_NANDF_RB2__FEC_COL 0x80000000 | ||
| 541 | MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000 | ||
| 542 | MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000 | ||
| 543 | MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000 | ||
| 544 | MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000 | ||
| 545 | MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000 | ||
| 546 | MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000 | ||
| 547 | MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000 | ||
| 548 | MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000 | ||
| 549 | MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000 | ||
| 550 | MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000 | ||
| 551 | >; | ||
| 552 | }; | ||
| 553 | |||
| 554 | pinctrl_fec_2: fecgrp-2 { | ||
| 555 | fsl,pins = < | ||
| 556 | MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 | ||
| 557 | MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 | ||
| 558 | MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 | ||
| 559 | MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 | ||
| 560 | MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 | ||
| 561 | MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 | ||
| 562 | MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 | ||
| 563 | MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 | ||
| 564 | MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 | ||
| 565 | MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 | ||
| 566 | MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 | ||
| 567 | MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 | ||
| 568 | MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 | ||
| 569 | MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 | ||
| 570 | MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 | ||
| 571 | MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 | ||
| 572 | MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 | ||
| 573 | MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 | ||
| 574 | >; | ||
| 575 | }; | ||
| 576 | }; | ||
| 577 | |||
| 578 | ecspi1 { | ||
| 579 | pinctrl_ecspi1_1: ecspi1grp-1 { | ||
| 580 | fsl,pins = < | ||
| 581 | MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 | ||
| 582 | MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 | ||
| 583 | MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 | ||
| 584 | >; | ||
| 585 | }; | ||
| 586 | }; | ||
| 587 | |||
| 588 | ecspi2 { | ||
| 589 | pinctrl_ecspi2_1: ecspi2grp-1 { | ||
| 590 | fsl,pins = < | ||
| 591 | MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185 | ||
| 592 | MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185 | ||
| 593 | MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185 | ||
| 594 | >; | ||
| 595 | }; | ||
| 596 | }; | ||
| 597 | |||
| 598 | esdhc1 { | ||
| 599 | pinctrl_esdhc1_1: esdhc1grp-1 { | ||
| 600 | fsl,pins = < | ||
| 601 | MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 | ||
| 602 | MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 | ||
| 603 | MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 | ||
| 604 | MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 | ||
| 605 | MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 | ||
| 606 | MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 | ||
| 607 | >; | ||
| 608 | }; | ||
| 609 | }; | ||
| 610 | |||
| 611 | esdhc2 { | ||
| 612 | pinctrl_esdhc2_1: esdhc2grp-1 { | ||
| 613 | fsl,pins = < | ||
| 614 | MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 | ||
| 615 | MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 | ||
| 616 | MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 | ||
| 617 | MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 | ||
| 618 | MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 | ||
| 619 | MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 | ||
| 620 | >; | ||
| 621 | }; | ||
| 622 | }; | ||
| 623 | |||
| 624 | i2c2 { | ||
| 625 | pinctrl_i2c2_1: i2c2grp-1 { | ||
| 626 | fsl,pins = < | ||
| 627 | MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed | ||
| 628 | MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed | ||
| 629 | >; | ||
| 630 | }; | ||
| 631 | |||
| 632 | pinctrl_i2c2_2: i2c2grp-2 { | ||
| 633 | fsl,pins = < | ||
| 634 | MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed | ||
| 635 | MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed | ||
| 636 | >; | ||
| 637 | }; | ||
| 638 | |||
| 639 | pinctrl_i2c2_3: i2c2grp-3 { | ||
| 640 | fsl,pins = < | ||
| 641 | MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed | ||
| 642 | MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed | ||
| 643 | >; | ||
| 644 | }; | ||
| 645 | }; | ||
| 646 | |||
| 647 | ipu_disp1 { | ||
| 648 | pinctrl_ipu_disp1_1: ipudisp1grp-1 { | ||
| 649 | fsl,pins = < | ||
| 650 | MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 | ||
| 651 | MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 | ||
| 652 | MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 | ||
| 653 | MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 | ||
| 654 | MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 | ||
| 655 | MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 | ||
| 656 | MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 | ||
| 657 | MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 | ||
| 658 | MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 | ||
| 659 | MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 | ||
| 660 | MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 | ||
| 661 | MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 | ||
| 662 | MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 | ||
| 663 | MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 | ||
| 664 | MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 | ||
| 665 | MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 | ||
| 666 | MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 | ||
| 667 | MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 | ||
| 668 | MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 | ||
| 669 | MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 | ||
| 670 | MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 | ||
| 671 | MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 | ||
| 672 | MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 | ||
| 673 | MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 | ||
| 674 | MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */ | ||
| 675 | MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */ | ||
| 676 | >; | ||
| 677 | }; | ||
| 678 | }; | ||
| 679 | |||
| 680 | ipu_disp2 { | ||
| 681 | pinctrl_ipu_disp2_1: ipudisp2grp-1 { | ||
| 682 | fsl,pins = < | ||
| 683 | MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5 | ||
| 684 | MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5 | ||
| 685 | MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5 | ||
| 686 | MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5 | ||
| 687 | MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5 | ||
| 688 | MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5 | ||
| 689 | MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5 | ||
| 690 | MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5 | ||
| 691 | MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5 | ||
| 692 | MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5 | ||
| 693 | MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5 | ||
| 694 | MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5 | ||
| 695 | MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5 | ||
| 696 | MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5 | ||
| 697 | MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5 | ||
| 698 | MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5 | ||
| 699 | MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */ | ||
| 700 | MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */ | ||
| 701 | MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 /* CLK */ | ||
| 702 | MX51_PAD_DI_GP4__DI2_PIN15 0x5 /* DE */ | ||
| 703 | >; | ||
| 704 | }; | ||
| 705 | }; | ||
| 706 | |||
| 707 | kpp { | ||
| 708 | pinctrl_kpp_1: kppgrp-1 { | ||
| 709 | fsl,pins = < | ||
| 710 | MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0 | ||
| 711 | MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0 | ||
| 712 | MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0 | ||
| 713 | MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0 | ||
| 714 | MX51_PAD_KEY_COL0__KEY_COL0 0xe8 | ||
| 715 | MX51_PAD_KEY_COL1__KEY_COL1 0xe8 | ||
| 716 | MX51_PAD_KEY_COL2__KEY_COL2 0xe8 | ||
| 717 | MX51_PAD_KEY_COL3__KEY_COL3 0xe8 | ||
| 718 | >; | ||
| 719 | }; | ||
| 720 | }; | ||
| 721 | |||
| 722 | pata { | ||
| 723 | pinctrl_pata_1: patagrp-1 { | ||
| 724 | fsl,pins = < | ||
| 725 | MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004 | ||
| 726 | MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004 | ||
| 727 | MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004 | ||
| 728 | MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004 | ||
| 729 | MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004 | ||
| 730 | MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004 | ||
| 731 | MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004 | ||
| 732 | MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004 | ||
| 733 | MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004 | ||
| 734 | MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004 | ||
| 735 | MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004 | ||
| 736 | MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004 | ||
| 737 | MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004 | ||
| 738 | MX51_PAD_NANDF_D15__PATA_DATA15 0x2004 | ||
| 739 | MX51_PAD_NANDF_D14__PATA_DATA14 0x2004 | ||
| 740 | MX51_PAD_NANDF_D13__PATA_DATA13 0x2004 | ||
| 741 | MX51_PAD_NANDF_D12__PATA_DATA12 0x2004 | ||
| 742 | MX51_PAD_NANDF_D11__PATA_DATA11 0x2004 | ||
| 743 | MX51_PAD_NANDF_D10__PATA_DATA10 0x2004 | ||
| 744 | MX51_PAD_NANDF_D9__PATA_DATA9 0x2004 | ||
| 745 | MX51_PAD_NANDF_D8__PATA_DATA8 0x2004 | ||
| 746 | MX51_PAD_NANDF_D7__PATA_DATA7 0x2004 | ||
| 747 | MX51_PAD_NANDF_D6__PATA_DATA6 0x2004 | ||
| 748 | MX51_PAD_NANDF_D5__PATA_DATA5 0x2004 | ||
| 749 | MX51_PAD_NANDF_D4__PATA_DATA4 0x2004 | ||
| 750 | MX51_PAD_NANDF_D3__PATA_DATA3 0x2004 | ||
| 751 | MX51_PAD_NANDF_D2__PATA_DATA2 0x2004 | ||
| 752 | MX51_PAD_NANDF_D1__PATA_DATA1 0x2004 | ||
| 753 | MX51_PAD_NANDF_D0__PATA_DATA0 0x2004 | ||
| 754 | >; | ||
| 755 | }; | ||
| 756 | }; | ||
| 757 | |||
| 758 | uart1 { | ||
| 759 | pinctrl_uart1_1: uart1grp-1 { | ||
| 760 | fsl,pins = < | ||
| 761 | MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 | ||
| 762 | MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 | ||
| 763 | >; | ||
| 764 | }; | ||
| 765 | |||
| 766 | pinctrl_uart1_rtscts_1: uart1rtscts-1 { | ||
| 767 | fsl,pins = < | ||
| 768 | MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 | ||
| 769 | MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 | ||
| 770 | >; | ||
| 771 | }; | ||
| 772 | }; | ||
| 773 | |||
| 774 | uart2 { | ||
| 775 | pinctrl_uart2_1: uart2grp-1 { | ||
| 776 | fsl,pins = < | ||
| 777 | MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 | ||
| 778 | MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 | ||
| 779 | >; | ||
| 780 | }; | ||
| 781 | }; | ||
| 782 | |||
| 783 | uart3 { | ||
| 784 | pinctrl_uart3_1: uart3grp-1 { | ||
| 785 | fsl,pins = < | ||
| 786 | MX51_PAD_EIM_D25__UART3_RXD 0x1c5 | ||
| 787 | MX51_PAD_EIM_D26__UART3_TXD 0x1c5 | ||
| 788 | >; | ||
| 789 | }; | ||
| 790 | |||
| 791 | pinctrl_uart3_rtscts_1: uart3rtscts-1 { | ||
| 792 | fsl,pins = < | ||
| 793 | MX51_PAD_EIM_D27__UART3_RTS 0x1c5 | ||
| 794 | MX51_PAD_EIM_D24__UART3_CTS 0x1c5 | ||
| 795 | >; | ||
| 796 | }; | ||
| 797 | |||
| 798 | pinctrl_uart3_2: uart3grp-2 { | ||
| 799 | fsl,pins = < | ||
| 800 | MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 | ||
| 801 | MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 | ||
| 802 | >; | ||
| 803 | }; | ||
| 804 | }; | ||
| 805 | |||
| 806 | usbh1 { | ||
| 807 | pinctrl_usbh1_1: usbh1grp-1 { | ||
| 808 | fsl,pins = < | ||
| 809 | MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 | ||
| 810 | MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 | ||
| 811 | MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 | ||
| 812 | MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 | ||
| 813 | MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 | ||
| 814 | MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 | ||
| 815 | MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 | ||
| 816 | MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 | ||
| 817 | MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 | ||
| 818 | MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 | ||
| 819 | MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 | ||
| 820 | MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 | ||
| 821 | >; | ||
| 822 | }; | ||
| 823 | }; | ||
| 824 | |||
| 825 | usbh2 { | ||
| 826 | pinctrl_usbh2_1: usbh2grp-1 { | ||
| 827 | fsl,pins = < | ||
| 828 | MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5 | ||
| 829 | MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5 | ||
| 830 | MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5 | ||
| 831 | MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5 | ||
| 832 | MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5 | ||
| 833 | MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5 | ||
| 834 | MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5 | ||
| 835 | MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5 | ||
| 836 | MX51_PAD_EIM_A24__USBH2_CLK 0x1e5 | ||
| 837 | MX51_PAD_EIM_A25__USBH2_DIR 0x1e5 | ||
| 838 | MX51_PAD_EIM_A27__USBH2_NXT 0x1e5 | ||
| 839 | MX51_PAD_EIM_A26__USBH2_STP 0x1e5 | ||
| 840 | >; | ||
| 841 | }; | ||
| 842 | }; | ||
| 843 | }; | ||
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts index 174f86938c89..e9337ad52f59 100644 --- a/arch/arm/boot/dts/imx53-ard.dts +++ b/arch/arm/boot/dts/imx53-ard.dts | |||
| @@ -49,9 +49,12 @@ | |||
| 49 | 49 | ||
| 50 | regulators { | 50 | regulators { |
| 51 | compatible = "simple-bus"; | 51 | compatible = "simple-bus"; |
| 52 | #address-cells = <1>; | ||
| 53 | #size-cells = <0>; | ||
| 52 | 54 | ||
| 53 | reg_3p3v: 3p3v { | 55 | reg_3p3v: regulator@0 { |
| 54 | compatible = "regulator-fixed"; | 56 | compatible = "regulator-fixed"; |
| 57 | reg = <0>; | ||
| 55 | regulator-name = "3P3V"; | 58 | regulator-name = "3P3V"; |
| 56 | regulator-min-microvolt = <3300000>; | 59 | regulator-min-microvolt = <3300000>; |
| 57 | regulator-max-microvolt = <3300000>; | 60 | regulator-max-microvolt = <3300000>; |
| @@ -99,7 +102,7 @@ | |||
| 99 | 102 | ||
| 100 | &esdhc1 { | 103 | &esdhc1 { |
| 101 | pinctrl-names = "default"; | 104 | pinctrl-names = "default"; |
| 102 | pinctrl-0 = <&pinctrl_esdhc1_2>; | 105 | pinctrl-0 = <&pinctrl_esdhc1>; |
| 103 | cd-gpios = <&gpio1 1 0>; | 106 | cd-gpios = <&gpio1 1 0>; |
| 104 | wp-gpios = <&gpio1 9 0>; | 107 | wp-gpios = <&gpio1 9 0>; |
| 105 | status = "okay"; | 108 | status = "okay"; |
| @@ -109,7 +112,7 @@ | |||
| 109 | pinctrl-names = "default"; | 112 | pinctrl-names = "default"; |
| 110 | pinctrl-0 = <&pinctrl_hog>; | 113 | pinctrl-0 = <&pinctrl_hog>; |
| 111 | 114 | ||
| 112 | hog { | 115 | imx53-ard { |
| 113 | pinctrl_hog: hoggrp { | 116 | pinctrl_hog: hoggrp { |
| 114 | fsl,pins = < | 117 | fsl,pins = < |
| 115 | MX53_PAD_GPIO_1__GPIO1_1 0x80000000 | 118 | MX53_PAD_GPIO_1__GPIO1_1 0x80000000 |
| @@ -148,11 +151,33 @@ | |||
| 148 | MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x80000000 | 151 | MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x80000000 |
| 149 | >; | 152 | >; |
| 150 | }; | 153 | }; |
| 154 | |||
| 155 | pinctrl_esdhc1: esdhc1grp { | ||
| 156 | fsl,pins = < | ||
| 157 | MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 | ||
| 158 | MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 | ||
| 159 | MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 | ||
| 160 | MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 | ||
| 161 | MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5 | ||
| 162 | MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5 | ||
| 163 | MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5 | ||
| 164 | MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5 | ||
| 165 | MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 | ||
| 166 | MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 | ||
| 167 | >; | ||
| 168 | }; | ||
| 169 | |||
| 170 | pinctrl_uart1: uart1grp { | ||
| 171 | fsl,pins = < | ||
| 172 | MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 | ||
| 173 | MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 | ||
| 174 | >; | ||
| 175 | }; | ||
| 151 | }; | 176 | }; |
| 152 | }; | 177 | }; |
| 153 | 178 | ||
| 154 | &uart1 { | 179 | &uart1 { |
| 155 | pinctrl-names = "default"; | 180 | pinctrl-names = "default"; |
| 156 | pinctrl-0 = <&pinctrl_uart1_2>; | 181 | pinctrl-0 = <&pinctrl_uart1>; |
| 157 | status = "okay"; | 182 | status = "okay"; |
| 158 | }; | 183 | }; |
diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts deleted file mode 100644 index 801fda728ed6..000000000000 --- a/arch/arm/boot/dts/imx53-evk.dts +++ /dev/null | |||
| @@ -1,126 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. | ||
| 3 | * Copyright 2011 Linaro Ltd. | ||
| 4 | * | ||
| 5 | * The code contained herein is licensed under the GNU General Public | ||
| 6 | * License. You may obtain a copy of the GNU General Public License | ||
| 7 | * Version 2 or later at the following locations: | ||
| 8 | * | ||
| 9 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 10 | * http://www.gnu.org/copyleft/gpl.html | ||
| 11 | */ | ||
| 12 | |||
| 13 | /dts-v1/; | ||
| 14 | #include "imx53.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Freescale i.MX53 Evaluation Kit"; | ||
| 18 | compatible = "fsl,imx53-evk", "fsl,imx53"; | ||
| 19 | |||
| 20 | memory { | ||
| 21 | reg = <0x70000000 0x80000000>; | ||
| 22 | }; | ||
| 23 | |||
| 24 | leds { | ||
| 25 | compatible = "gpio-leds"; | ||
| 26 | |||
| 27 | green { | ||
| 28 | label = "Heartbeat"; | ||
| 29 | gpios = <&gpio7 7 0>; | ||
| 30 | linux,default-trigger = "heartbeat"; | ||
| 31 | }; | ||
| 32 | }; | ||
| 33 | }; | ||
| 34 | |||
| 35 | &esdhc1 { | ||
| 36 | pinctrl-names = "default"; | ||
| 37 | pinctrl-0 = <&pinctrl_esdhc1_1>; | ||
| 38 | cd-gpios = <&gpio3 13 0>; | ||
| 39 | wp-gpios = <&gpio3 14 0>; | ||
| 40 | status = "okay"; | ||
| 41 | }; | ||
| 42 | |||
| 43 | &ecspi1 { | ||
| 44 | pinctrl-names = "default"; | ||
| 45 | pinctrl-0 = <&pinctrl_ecspi1_1>; | ||
| 46 | fsl,spi-num-chipselects = <2>; | ||
| 47 | cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; | ||
| 48 | status = "okay"; | ||
| 49 | |||
| 50 | flash: at45db321d@1 { | ||
| 51 | #address-cells = <1>; | ||
| 52 | #size-cells = <1>; | ||
| 53 | compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash"; | ||
| 54 | spi-max-frequency = <25000000>; | ||
| 55 | reg = <1>; | ||
| 56 | |||
| 57 | partition@0 { | ||
| 58 | label = "U-Boot"; | ||
| 59 | reg = <0x0 0x40000>; | ||
| 60 | read-only; | ||
| 61 | }; | ||
| 62 | |||
| 63 | partition@40000 { | ||
| 64 | label = "Kernel"; | ||
| 65 | reg = <0x40000 0x3c0000>; | ||
| 66 | }; | ||
| 67 | }; | ||
| 68 | }; | ||
| 69 | |||
| 70 | &esdhc3 { | ||
| 71 | pinctrl-names = "default"; | ||
| 72 | pinctrl-0 = <&pinctrl_esdhc3_1>; | ||
| 73 | cd-gpios = <&gpio3 11 0>; | ||
| 74 | wp-gpios = <&gpio3 12 0>; | ||
| 75 | status = "okay"; | ||
| 76 | }; | ||
| 77 | |||
| 78 | &iomuxc { | ||
| 79 | pinctrl-names = "default"; | ||
| 80 | pinctrl-0 = <&pinctrl_hog>; | ||
| 81 | |||
| 82 | hog { | ||
| 83 | pinctrl_hog: hoggrp { | ||
| 84 | fsl,pins = < | ||
| 85 | MX53_PAD_EIM_EB2__GPIO2_30 0x80000000 | ||
| 86 | MX53_PAD_EIM_D19__GPIO3_19 0x80000000 | ||
| 87 | MX53_PAD_EIM_DA11__GPIO3_11 0x80000000 | ||
| 88 | MX53_PAD_EIM_DA12__GPIO3_12 0x80000000 | ||
| 89 | MX53_PAD_EIM_DA13__GPIO3_13 0x80000000 | ||
| 90 | MX53_PAD_EIM_DA14__GPIO3_14 0x80000000 | ||
| 91 | MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 | ||
| 92 | MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 | ||
| 93 | >; | ||
| 94 | }; | ||
| 95 | }; | ||
| 96 | }; | ||
| 97 | |||
| 98 | &uart1 { | ||
| 99 | pinctrl-names = "default"; | ||
| 100 | pinctrl-0 = <&pinctrl_uart1_1>; | ||
| 101 | status = "okay"; | ||
| 102 | }; | ||
| 103 | |||
| 104 | &i2c2 { | ||
| 105 | pinctrl-names = "default"; | ||
| 106 | pinctrl-0 = <&pinctrl_i2c2_1>; | ||
| 107 | status = "okay"; | ||
| 108 | |||
| 109 | pmic: mc13892@08 { | ||
| 110 | compatible = "fsl,mc13892", "fsl,mc13xxx"; | ||
| 111 | reg = <0x08>; | ||
| 112 | }; | ||
| 113 | |||
| 114 | codec: sgtl5000@0a { | ||
| 115 | compatible = "fsl,sgtl5000"; | ||
| 116 | reg = <0x0a>; | ||
| 117 | }; | ||
| 118 | }; | ||
| 119 | |||
| 120 | &fec { | ||
| 121 | pinctrl-names = "default"; | ||
| 122 | pinctrl-0 = <&pinctrl_fec_1>; | ||
| 123 | phy-mode = "rmii"; | ||
| 124 | phy-reset-gpios = <&gpio7 6 0>; | ||
| 125 | status = "okay"; | ||
| 126 | }; | ||
diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts index 7d304d02ed38..e8d11e2a93cd 100644 --- a/arch/arm/boot/dts/imx53-m53evk.dts +++ b/arch/arm/boot/dts/imx53-m53evk.dts | |||
| @@ -26,7 +26,7 @@ | |||
| 26 | crtcs = <&ipu 1>; | 26 | crtcs = <&ipu 1>; |
| 27 | interface-pix-fmt = "bgr666"; | 27 | interface-pix-fmt = "bgr666"; |
| 28 | pinctrl-names = "default"; | 28 | pinctrl-names = "default"; |
| 29 | pinctrl-0 = <&pinctrl_ipu_disp2_1>; | 29 | pinctrl-0 = <&pinctrl_ipu_disp1>; |
| 30 | 30 | ||
| 31 | display-timings { | 31 | display-timings { |
| 32 | 800x480p60 { | 32 | 800x480p60 { |
| @@ -51,6 +51,7 @@ | |||
| 51 | pwms = <&pwm1 0 3000>; | 51 | pwms = <&pwm1 0 3000>; |
| 52 | brightness-levels = <0 4 8 16 32 64 128 255>; | 52 | brightness-levels = <0 4 8 16 32 64 128 255>; |
| 53 | default-brightness-level = <6>; | 53 | default-brightness-level = <6>; |
| 54 | power-supply = <®_backlight>; | ||
| 54 | }; | 55 | }; |
| 55 | 56 | ||
| 56 | leds { | 57 | leds { |
| @@ -73,14 +74,36 @@ | |||
| 73 | 74 | ||
| 74 | regulators { | 75 | regulators { |
| 75 | compatible = "simple-bus"; | 76 | compatible = "simple-bus"; |
| 77 | #address-cells = <1>; | ||
| 78 | #size-cells = <0>; | ||
| 76 | 79 | ||
| 77 | reg_3p2v: 3p2v { | 80 | reg_3p2v: regulator@0 { |
| 78 | compatible = "regulator-fixed"; | 81 | compatible = "regulator-fixed"; |
| 82 | reg = <0>; | ||
| 79 | regulator-name = "3P2V"; | 83 | regulator-name = "3P2V"; |
| 80 | regulator-min-microvolt = <3200000>; | 84 | regulator-min-microvolt = <3200000>; |
| 81 | regulator-max-microvolt = <3200000>; | 85 | regulator-max-microvolt = <3200000>; |
| 82 | regulator-always-on; | 86 | regulator-always-on; |
| 83 | }; | 87 | }; |
| 88 | |||
| 89 | |||
| 90 | reg_backlight: regulator@1 { | ||
| 91 | compatible = "regulator-fixed"; | ||
| 92 | reg = <1>; | ||
| 93 | regulator-name = "lcd-supply"; | ||
| 94 | regulator-min-microvolt = <3200000>; | ||
| 95 | regulator-max-microvolt = <3200000>; | ||
| 96 | regulator-always-on; | ||
| 97 | }; | ||
| 98 | |||
| 99 | reg_usbh1_vbus: regulator@3 { | ||
| 100 | compatible = "regulator-fixed"; | ||
| 101 | reg = <3>; | ||
| 102 | regulator-name = "vbus"; | ||
| 103 | regulator-min-microvolt = <5000000>; | ||
| 104 | regulator-max-microvolt = <5000000>; | ||
| 105 | gpio = <&gpio1 2 0>; | ||
| 106 | }; | ||
| 84 | }; | 107 | }; |
| 85 | 108 | ||
| 86 | sound { | 109 | sound { |
| @@ -102,25 +125,25 @@ | |||
| 102 | 125 | ||
| 103 | &audmux { | 126 | &audmux { |
| 104 | pinctrl-names = "default"; | 127 | pinctrl-names = "default"; |
| 105 | pinctrl-0 = <&pinctrl_audmux_2>; | 128 | pinctrl-0 = <&pinctrl_audmux>; |
| 106 | status = "okay"; | 129 | status = "okay"; |
| 107 | }; | 130 | }; |
| 108 | 131 | ||
| 109 | &can1 { | 132 | &can1 { |
| 110 | pinctrl-names = "default"; | 133 | pinctrl-names = "default"; |
| 111 | pinctrl-0 = <&pinctrl_can1_3>; | 134 | pinctrl-0 = <&pinctrl_can1>; |
| 112 | status = "okay"; | 135 | status = "okay"; |
| 113 | }; | 136 | }; |
| 114 | 137 | ||
| 115 | &can2 { | 138 | &can2 { |
| 116 | pinctrl-names = "default"; | 139 | pinctrl-names = "default"; |
| 117 | pinctrl-0 = <&pinctrl_can2_1>; | 140 | pinctrl-0 = <&pinctrl_can2>; |
| 118 | status = "okay"; | 141 | status = "okay"; |
| 119 | }; | 142 | }; |
| 120 | 143 | ||
| 121 | &esdhc1 { | 144 | &esdhc1 { |
| 122 | pinctrl-names = "default"; | 145 | pinctrl-names = "default"; |
| 123 | pinctrl-0 = <&pinctrl_esdhc1_1>; | 146 | pinctrl-0 = <&pinctrl_esdhc1>; |
| 124 | cd-gpios = <&gpio1 1 0>; | 147 | cd-gpios = <&gpio1 1 0>; |
| 125 | wp-gpios = <&gpio1 9 0>; | 148 | wp-gpios = <&gpio1 9 0>; |
| 126 | status = "okay"; | 149 | status = "okay"; |
| @@ -128,14 +151,14 @@ | |||
| 128 | 151 | ||
| 129 | &fec { | 152 | &fec { |
| 130 | pinctrl-names = "default"; | 153 | pinctrl-names = "default"; |
| 131 | pinctrl-0 = <&pinctrl_fec_1>; | 154 | pinctrl-0 = <&pinctrl_fec>; |
| 132 | phy-mode = "rmii"; | 155 | phy-mode = "rmii"; |
| 133 | status = "okay"; | 156 | status = "okay"; |
| 134 | }; | 157 | }; |
| 135 | 158 | ||
| 136 | &i2c1 { | 159 | &i2c1 { |
| 137 | pinctrl-names = "default"; | 160 | pinctrl-names = "default"; |
| 138 | pinctrl-0 = <&pinctrl_i2c1_2>; | 161 | pinctrl-0 = <&pinctrl_i2c1>; |
| 139 | status = "okay"; | 162 | status = "okay"; |
| 140 | 163 | ||
| 141 | sgtl5000: codec@0a { | 164 | sgtl5000: codec@0a { |
| @@ -143,13 +166,13 @@ | |||
| 143 | reg = <0x0a>; | 166 | reg = <0x0a>; |
| 144 | VDDA-supply = <®_3p2v>; | 167 | VDDA-supply = <®_3p2v>; |
| 145 | VDDIO-supply = <®_3p2v>; | 168 | VDDIO-supply = <®_3p2v>; |
| 146 | clocks = <&clks 150>; | 169 | clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; |
| 147 | }; | 170 | }; |
| 148 | }; | 171 | }; |
| 149 | 172 | ||
| 150 | &i2c2 { | 173 | &i2c2 { |
| 151 | pinctrl-names = "default"; | 174 | pinctrl-names = "default"; |
| 152 | pinctrl-0 = <&pinctrl_i2c2_2>; | 175 | pinctrl-0 = <&pinctrl_i2c2>; |
| 153 | clock-frequency = <400000>; | 176 | clock-frequency = <400000>; |
| 154 | status = "okay"; | 177 | status = "okay"; |
| 155 | 178 | ||
| @@ -193,7 +216,7 @@ | |||
| 193 | 216 | ||
| 194 | &i2c3 { | 217 | &i2c3 { |
| 195 | pinctrl-names = "default"; | 218 | pinctrl-names = "default"; |
| 196 | pinctrl-0 = <&pinctrl_i2c3_1>; | 219 | pinctrl-0 = <&pinctrl_i2c3>; |
| 197 | status = "okay"; | 220 | status = "okay"; |
| 198 | }; | 221 | }; |
| 199 | 222 | ||
| @@ -201,14 +224,14 @@ | |||
| 201 | pinctrl-names = "default"; | 224 | pinctrl-names = "default"; |
| 202 | pinctrl-0 = <&pinctrl_hog>; | 225 | pinctrl-0 = <&pinctrl_hog>; |
| 203 | 226 | ||
| 204 | hog { | 227 | imx53-m53evk { |
| 205 | pinctrl_hog: hoggrp { | 228 | pinctrl_hog: hoggrp { |
| 206 | fsl,pins = < | 229 | fsl,pins = < |
| 207 | MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 | 230 | MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 |
| 208 | MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 | 231 | MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 |
| 209 | MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 | 232 | MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 |
| 210 | MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5 | 233 | MX53_PAD_GPIO_2__GPIO1_2 0x80000000 |
| 211 | 234 | MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x80000000 | |
| 212 | >; | 235 | >; |
| 213 | }; | 236 | }; |
| 214 | 237 | ||
| @@ -218,12 +241,168 @@ | |||
| 218 | MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000 | 241 | MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000 |
| 219 | >; | 242 | >; |
| 220 | }; | 243 | }; |
| 244 | |||
| 245 | pinctrl_audmux: audmuxgrp { | ||
| 246 | fsl,pins = < | ||
| 247 | MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000 | ||
| 248 | MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000 | ||
| 249 | MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000 | ||
| 250 | MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000 | ||
| 251 | >; | ||
| 252 | }; | ||
| 253 | |||
| 254 | pinctrl_can1: can1grp { | ||
| 255 | fsl,pins = < | ||
| 256 | MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000 | ||
| 257 | MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000 | ||
| 258 | >; | ||
| 259 | }; | ||
| 260 | |||
| 261 | pinctrl_can2: can2grp { | ||
| 262 | fsl,pins = < | ||
| 263 | MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 | ||
| 264 | MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 | ||
| 265 | >; | ||
| 266 | }; | ||
| 267 | |||
| 268 | pinctrl_esdhc1: esdhc1grp { | ||
| 269 | fsl,pins = < | ||
| 270 | MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 | ||
| 271 | MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 | ||
| 272 | MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 | ||
| 273 | MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 | ||
| 274 | MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 | ||
| 275 | MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 | ||
| 276 | >; | ||
| 277 | }; | ||
| 278 | |||
| 279 | pinctrl_fec: fecgrp { | ||
| 280 | fsl,pins = < | ||
| 281 | MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 | ||
| 282 | MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 | ||
| 283 | MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 | ||
| 284 | MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 | ||
| 285 | MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 | ||
| 286 | MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 | ||
| 287 | MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 | ||
| 288 | MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 | ||
| 289 | MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 | ||
| 290 | MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 | ||
| 291 | >; | ||
| 292 | }; | ||
| 293 | |||
| 294 | pinctrl_i2c1: i2c1grp { | ||
| 295 | fsl,pins = < | ||
| 296 | MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000 | ||
| 297 | MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000 | ||
| 298 | >; | ||
| 299 | }; | ||
| 300 | |||
| 301 | pinctrl_i2c2: i2c2grp { | ||
| 302 | fsl,pins = < | ||
| 303 | MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000 | ||
| 304 | MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000 | ||
| 305 | >; | ||
| 306 | }; | ||
| 307 | |||
| 308 | pinctrl_i2c3: i2c3grp { | ||
| 309 | fsl,pins = < | ||
| 310 | MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 | ||
| 311 | MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000 | ||
| 312 | >; | ||
| 313 | }; | ||
| 314 | |||
| 315 | pinctrl_ipu_disp1: ipudisp1grp { | ||
| 316 | fsl,pins = < | ||
| 317 | MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5 | ||
| 318 | MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5 | ||
| 319 | MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5 | ||
| 320 | MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5 | ||
| 321 | MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5 | ||
| 322 | MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5 | ||
| 323 | MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5 | ||
| 324 | MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5 | ||
| 325 | MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5 | ||
| 326 | MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5 | ||
| 327 | MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5 | ||
| 328 | MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5 | ||
| 329 | MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5 | ||
| 330 | MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5 | ||
| 331 | MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5 | ||
| 332 | MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5 | ||
| 333 | MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5 | ||
| 334 | MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5 | ||
| 335 | MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5 | ||
| 336 | MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5 | ||
| 337 | MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5 | ||
| 338 | MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5 | ||
| 339 | MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5 | ||
| 340 | MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5 | ||
| 341 | MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5 | ||
| 342 | MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5 | ||
| 343 | MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5 | ||
| 344 | MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5 | ||
| 345 | MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5 | ||
| 346 | MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5 | ||
| 347 | MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5 | ||
| 348 | MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5 | ||
| 349 | >; | ||
| 350 | }; | ||
| 351 | |||
| 352 | pinctrl_nand: nandgrp { | ||
| 353 | fsl,pins = < | ||
| 354 | MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 | ||
| 355 | MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 | ||
| 356 | MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 | ||
| 357 | MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 | ||
| 358 | MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 | ||
| 359 | MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 | ||
| 360 | MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 | ||
| 361 | MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 | ||
| 362 | MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 | ||
| 363 | MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 | ||
| 364 | MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 | ||
| 365 | MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 | ||
| 366 | MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 | ||
| 367 | MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 | ||
| 368 | MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 | ||
| 369 | >; | ||
| 370 | }; | ||
| 371 | |||
| 372 | pinctrl_pwm1: pwm1grp { | ||
| 373 | fsl,pins = < | ||
| 374 | MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5 | ||
| 375 | >; | ||
| 376 | }; | ||
| 377 | |||
| 378 | pinctrl_uart1: uart1grp { | ||
| 379 | fsl,pins = < | ||
| 380 | MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 | ||
| 381 | MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 | ||
| 382 | >; | ||
| 383 | }; | ||
| 384 | |||
| 385 | pinctrl_uart2: uart2grp { | ||
| 386 | fsl,pins = < | ||
| 387 | MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 | ||
| 388 | MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 | ||
| 389 | >; | ||
| 390 | }; | ||
| 391 | |||
| 392 | pinctrl_uart3: uart3grp { | ||
| 393 | fsl,pins = < | ||
| 394 | MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 | ||
| 395 | MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 | ||
| 396 | MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 | ||
| 397 | MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 | ||
| 398 | >; | ||
| 399 | }; | ||
| 221 | }; | 400 | }; |
| 222 | }; | 401 | }; |
| 223 | 402 | ||
| 224 | &nfc { | 403 | &nfc { |
| 225 | pinctrl-names = "default"; | 404 | pinctrl-names = "default"; |
| 226 | pinctrl-0 = <&pinctrl_nand_1>; | 405 | pinctrl-0 = <&pinctrl_nand>; |
| 227 | nand-bus-width = <8>; | 406 | nand-bus-width = <8>; |
| 228 | nand-ecc-mode = "hw"; | 407 | nand-ecc-mode = "hw"; |
| 229 | status = "okay"; | 408 | status = "okay"; |
| @@ -231,7 +410,11 @@ | |||
| 231 | 410 | ||
| 232 | &pwm1 { | 411 | &pwm1 { |
| 233 | pinctrl-names = "default"; | 412 | pinctrl-names = "default"; |
| 234 | pinctrl-0 = <&pinctrl_pwm1_1>; | 413 | pinctrl-0 = <&pinctrl_pwm1>; |
| 414 | status = "okay"; | ||
| 415 | }; | ||
| 416 | |||
| 417 | &sata { | ||
| 235 | status = "okay"; | 418 | status = "okay"; |
| 236 | }; | 419 | }; |
| 237 | 420 | ||
| @@ -242,18 +425,29 @@ | |||
| 242 | 425 | ||
| 243 | &uart1 { | 426 | &uart1 { |
| 244 | pinctrl-names = "default"; | 427 | pinctrl-names = "default"; |
| 245 | pinctrl-0 = <&pinctrl_uart1_2>; | 428 | pinctrl-0 = <&pinctrl_uart1>; |
| 246 | status = "okay"; | 429 | status = "okay"; |
| 247 | }; | 430 | }; |
| 248 | 431 | ||
| 249 | &uart2 { | 432 | &uart2 { |
| 250 | pinctrl-names = "default"; | 433 | pinctrl-names = "default"; |
| 251 | pinctrl-0 = <&pinctrl_uart2_1>; | 434 | pinctrl-0 = <&pinctrl_uart2>; |
| 252 | status = "okay"; | 435 | status = "okay"; |
| 253 | }; | 436 | }; |
| 254 | 437 | ||
| 255 | &uart3 { | 438 | &uart3 { |
| 256 | pinctrl-names = "default"; | 439 | pinctrl-names = "default"; |
| 257 | pinctrl-0 = <&pinctrl_uart3_1>; | 440 | pinctrl-0 = <&pinctrl_uart3>; |
| 441 | status = "okay"; | ||
| 442 | }; | ||
| 443 | |||
| 444 | &usbh1 { | ||
| 445 | vbus-supply = <®_usbh1_vbus>; | ||
| 446 | phy_type = "utmi"; | ||
| 447 | status = "okay"; | ||
| 448 | }; | ||
| 449 | |||
| 450 | &usbotg { | ||
| 451 | dr_mode = "peripheral"; | ||
| 258 | status = "okay"; | 452 | status = "okay"; |
| 259 | }; | 453 | }; |
diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts index a63090267941..55af11037a00 100644 --- a/arch/arm/boot/dts/imx53-mba53.dts +++ b/arch/arm/boot/dts/imx53-mba53.dts | |||
| @@ -17,14 +17,6 @@ | |||
| 17 | model = "TQ MBa53 starter kit"; | 17 | model = "TQ MBa53 starter kit"; |
| 18 | compatible = "tq,mba53", "tq,tqma53", "fsl,imx53"; | 18 | compatible = "tq,mba53", "tq,tqma53", "fsl,imx53"; |
| 19 | 19 | ||
| 20 | reg_backlight: fixed@0 { | ||
| 21 | compatible = "regulator-fixed"; | ||
| 22 | regulator-name = "lcd-supply"; | ||
| 23 | gpio = <&gpio2 5 0>; | ||
| 24 | startup-delay-us = <5000>; | ||
| 25 | enable-active-low; | ||
| 26 | }; | ||
| 27 | |||
| 28 | backlight { | 20 | backlight { |
| 29 | compatible = "pwm-backlight"; | 21 | compatible = "pwm-backlight"; |
| 30 | pwms = <&pwm2 0 50000>; | 22 | pwms = <&pwm2 0 50000>; |
| @@ -43,12 +35,27 @@ | |||
| 43 | status = "disabled"; | 35 | status = "disabled"; |
| 44 | }; | 36 | }; |
| 45 | 37 | ||
| 46 | reg_3p2v: 3p2v { | 38 | regulators { |
| 47 | compatible = "regulator-fixed"; | 39 | compatible = "simple-bus"; |
| 48 | regulator-name = "3P2V"; | 40 | #address-cells = <1>; |
| 49 | regulator-min-microvolt = <3200000>; | 41 | #size-cells = <0>; |
| 50 | regulator-max-microvolt = <3200000>; | 42 | |
| 51 | regulator-always-on; | 43 | reg_backlight: regulator@0 { |
| 44 | compatible = "regulator-fixed"; | ||
| 45 | reg = <0>; | ||
| 46 | regulator-name = "lcd-supply"; | ||
| 47 | gpio = <&gpio2 5 0>; | ||
| 48 | startup-delay-us = <5000>; | ||
| 49 | }; | ||
| 50 | |||
| 51 | reg_3p2v: regulator@1 { | ||
| 52 | compatible = "regulator-fixed"; | ||
| 53 | reg = <1>; | ||
| 54 | regulator-name = "3P2V"; | ||
| 55 | regulator-min-microvolt = <3200000>; | ||
| 56 | regulator-max-microvolt = <3200000>; | ||
| 57 | regulator-always-on; | ||
| 58 | }; | ||
| 52 | }; | 59 | }; |
| 53 | 60 | ||
| 54 | sound { | 61 | sound { |
| @@ -148,14 +155,14 @@ | |||
| 148 | &audmux { | 155 | &audmux { |
| 149 | status = "okay"; | 156 | status = "okay"; |
| 150 | pinctrl-names = "default"; | 157 | pinctrl-names = "default"; |
| 151 | pinctrl-0 = <&pinctrl_audmux_1>; | 158 | pinctrl-0 = <&pinctrl_audmux>; |
| 152 | }; | 159 | }; |
| 153 | 160 | ||
| 154 | &i2c2 { | 161 | &i2c2 { |
| 155 | codec: sgtl5000@a { | 162 | codec: sgtl5000@a { |
| 156 | compatible = "fsl,sgtl5000"; | 163 | compatible = "fsl,sgtl5000"; |
| 157 | reg = <0x0a>; | 164 | reg = <0x0a>; |
| 158 | clocks = <&clks 150>; | 165 | clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; |
| 159 | VDDA-supply = <®_3p2v>; | 166 | VDDA-supply = <®_3p2v>; |
| 160 | VDDIO-supply = <®_3p2v>; | 167 | VDDIO-supply = <®_3p2v>; |
| 161 | }; | 168 | }; |
diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/imx53-qsb-common.dtsi new file mode 100644 index 000000000000..2dca98b79f48 --- /dev/null +++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi | |||
| @@ -0,0 +1,336 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. | ||
| 3 | * Copyright 2011 Linaro Ltd. | ||
| 4 | * | ||
| 5 | * The code contained herein is licensed under the GNU General Public | ||
| 6 | * License. You may obtain a copy of the GNU General Public License | ||
| 7 | * Version 2 or later at the following locations: | ||
| 8 | * | ||
| 9 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 10 | * http://www.gnu.org/copyleft/gpl.html | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include "imx53.dtsi" | ||
| 14 | |||
| 15 | / { | ||
| 16 | memory { | ||
| 17 | reg = <0x70000000 0x40000000>; | ||
| 18 | }; | ||
| 19 | |||
| 20 | display@di0 { | ||
| 21 | compatible = "fsl,imx-parallel-display"; | ||
| 22 | crtcs = <&ipu 0>; | ||
| 23 | interface-pix-fmt = "rgb565"; | ||
| 24 | pinctrl-names = "default"; | ||
| 25 | pinctrl-0 = <&pinctrl_ipu_disp0>; | ||
| 26 | status = "disabled"; | ||
| 27 | display-timings { | ||
| 28 | claawvga { | ||
| 29 | native-mode; | ||
| 30 | clock-frequency = <27000000>; | ||
| 31 | hactive = <800>; | ||
| 32 | vactive = <480>; | ||
| 33 | hback-porch = <40>; | ||
| 34 | hfront-porch = <60>; | ||
| 35 | vback-porch = <10>; | ||
| 36 | vfront-porch = <10>; | ||
| 37 | hsync-len = <20>; | ||
| 38 | vsync-len = <10>; | ||
| 39 | hsync-active = <0>; | ||
| 40 | vsync-active = <0>; | ||
| 41 | de-active = <1>; | ||
| 42 | pixelclk-active = <0>; | ||
| 43 | }; | ||
| 44 | }; | ||
| 45 | }; | ||
| 46 | |||
| 47 | gpio-keys { | ||
| 48 | compatible = "gpio-keys"; | ||
| 49 | |||
| 50 | power { | ||
| 51 | label = "Power Button"; | ||
| 52 | gpios = <&gpio1 8 0>; | ||
| 53 | linux,code = <116>; /* KEY_POWER */ | ||
| 54 | }; | ||
| 55 | |||
| 56 | volume-up { | ||
| 57 | label = "Volume Up"; | ||
| 58 | gpios = <&gpio2 14 0>; | ||
| 59 | linux,code = <115>; /* KEY_VOLUMEUP */ | ||
| 60 | gpio-key,wakeup; | ||
| 61 | }; | ||
| 62 | |||
| 63 | volume-down { | ||
| 64 | label = "Volume Down"; | ||
| 65 | gpios = <&gpio2 15 0>; | ||
| 66 | linux,code = <114>; /* KEY_VOLUMEDOWN */ | ||
| 67 | gpio-key,wakeup; | ||
| 68 | }; | ||
| 69 | }; | ||
| 70 | |||
| 71 | leds { | ||
| 72 | compatible = "gpio-leds"; | ||
| 73 | pinctrl-names = "default"; | ||
| 74 | pinctrl-0 = <&led_pin_gpio7_7>; | ||
| 75 | |||
| 76 | user { | ||
| 77 | label = "Heartbeat"; | ||
| 78 | gpios = <&gpio7 7 0>; | ||
| 79 | linux,default-trigger = "heartbeat"; | ||
| 80 | }; | ||
| 81 | }; | ||
| 82 | |||
| 83 | regulators { | ||
| 84 | compatible = "simple-bus"; | ||
| 85 | #address-cells = <1>; | ||
| 86 | #size-cells = <0>; | ||
| 87 | |||
| 88 | reg_3p2v: regulator@0 { | ||
| 89 | compatible = "regulator-fixed"; | ||
| 90 | reg = <0>; | ||
| 91 | regulator-name = "3P2V"; | ||
| 92 | regulator-min-microvolt = <3200000>; | ||
| 93 | regulator-max-microvolt = <3200000>; | ||
| 94 | regulator-always-on; | ||
| 95 | }; | ||
| 96 | |||
| 97 | reg_usb_vbus: regulator@1 { | ||
| 98 | compatible = "regulator-fixed"; | ||
| 99 | reg = <1>; | ||
| 100 | regulator-name = "usb_vbus"; | ||
| 101 | regulator-min-microvolt = <5000000>; | ||
| 102 | regulator-max-microvolt = <5000000>; | ||
| 103 | gpio = <&gpio7 8 0>; | ||
| 104 | enable-active-high; | ||
| 105 | }; | ||
| 106 | }; | ||
| 107 | |||
| 108 | sound { | ||
| 109 | compatible = "fsl,imx53-qsb-sgtl5000", | ||
| 110 | "fsl,imx-audio-sgtl5000"; | ||
| 111 | model = "imx53-qsb-sgtl5000"; | ||
| 112 | ssi-controller = <&ssi2>; | ||
| 113 | audio-codec = <&sgtl5000>; | ||
| 114 | audio-routing = | ||
| 115 | "MIC_IN", "Mic Jack", | ||
| 116 | "Mic Jack", "Mic Bias", | ||
| 117 | "Headphone Jack", "HP_OUT"; | ||
| 118 | mux-int-port = <2>; | ||
| 119 | mux-ext-port = <5>; | ||
| 120 | }; | ||
| 121 | }; | ||
| 122 | |||
| 123 | &esdhc1 { | ||
| 124 | pinctrl-names = "default"; | ||
| 125 | pinctrl-0 = <&pinctrl_esdhc1>; | ||
| 126 | status = "okay"; | ||
| 127 | }; | ||
| 128 | |||
| 129 | &ssi2 { | ||
| 130 | fsl,mode = "i2s-slave"; | ||
| 131 | status = "okay"; | ||
| 132 | }; | ||
| 133 | |||
| 134 | &esdhc3 { | ||
| 135 | pinctrl-names = "default"; | ||
| 136 | pinctrl-0 = <&pinctrl_esdhc3>; | ||
| 137 | cd-gpios = <&gpio3 11 0>; | ||
| 138 | wp-gpios = <&gpio3 12 0>; | ||
| 139 | bus-width = <8>; | ||
| 140 | status = "okay"; | ||
| 141 | }; | ||
| 142 | |||
| 143 | &iomuxc { | ||
| 144 | pinctrl-names = "default"; | ||
| 145 | pinctrl-0 = <&pinctrl_hog>; | ||
| 146 | |||
| 147 | imx53-qsb { | ||
| 148 | pinctrl_hog: hoggrp { | ||
| 149 | fsl,pins = < | ||
| 150 | MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 | ||
| 151 | MX53_PAD_GPIO_8__GPIO1_8 0x80000000 | ||
| 152 | MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 | ||
| 153 | MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 | ||
| 154 | MX53_PAD_EIM_DA11__GPIO3_11 0x80000000 | ||
| 155 | MX53_PAD_EIM_DA12__GPIO3_12 0x80000000 | ||
| 156 | MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 | ||
| 157 | MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 | ||
| 158 | MX53_PAD_GPIO_16__GPIO7_11 0x80000000 | ||
| 159 | >; | ||
| 160 | }; | ||
| 161 | |||
| 162 | led_pin_gpio7_7: led_gpio7_7@0 { | ||
| 163 | fsl,pins = < | ||
| 164 | MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 | ||
| 165 | >; | ||
| 166 | }; | ||
| 167 | |||
| 168 | pinctrl_audmux: audmuxgrp { | ||
| 169 | fsl,pins = < | ||
| 170 | MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 | ||
| 171 | MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 | ||
| 172 | MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 | ||
| 173 | MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 | ||
| 174 | >; | ||
| 175 | }; | ||
| 176 | |||
| 177 | pinctrl_esdhc1: esdhc1grp { | ||
| 178 | fsl,pins = < | ||
| 179 | MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 | ||
| 180 | MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 | ||
| 181 | MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 | ||
| 182 | MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 | ||
| 183 | MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 | ||
| 184 | MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 | ||
| 185 | >; | ||
| 186 | }; | ||
| 187 | |||
| 188 | pinctrl_esdhc3: esdhc3grp { | ||
| 189 | fsl,pins = < | ||
| 190 | MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 | ||
| 191 | MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 | ||
| 192 | MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 | ||
| 193 | MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 | ||
| 194 | MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 | ||
| 195 | MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 | ||
| 196 | MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 | ||
| 197 | MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 | ||
| 198 | MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 | ||
| 199 | MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 | ||
| 200 | >; | ||
| 201 | }; | ||
| 202 | |||
| 203 | pinctrl_fec: fecgrp { | ||
| 204 | fsl,pins = < | ||
| 205 | MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 | ||
| 206 | MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 | ||
| 207 | MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 | ||
| 208 | MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 | ||
| 209 | MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 | ||
| 210 | MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 | ||
| 211 | MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 | ||
| 212 | MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 | ||
| 213 | MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 | ||
| 214 | MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 | ||
| 215 | >; | ||
| 216 | }; | ||
| 217 | |||
| 218 | pinctrl_i2c1: i2c1grp { | ||
| 219 | fsl,pins = < | ||
| 220 | MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000 | ||
| 221 | MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000 | ||
| 222 | >; | ||
| 223 | }; | ||
| 224 | |||
| 225 | pinctrl_i2c2: i2c2grp { | ||
| 226 | fsl,pins = < | ||
| 227 | MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 | ||
| 228 | MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 | ||
| 229 | >; | ||
| 230 | }; | ||
| 231 | |||
| 232 | pinctrl_ipu_disp0: ipudisp0grp { | ||
| 233 | fsl,pins = < | ||
| 234 | MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 | ||
| 235 | MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 | ||
| 236 | MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 | ||
| 237 | MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 | ||
| 238 | MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 | ||
| 239 | MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 | ||
| 240 | MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 | ||
| 241 | MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 | ||
| 242 | MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 | ||
| 243 | MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 | ||
| 244 | MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 | ||
| 245 | MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 | ||
| 246 | MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 | ||
| 247 | MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 | ||
| 248 | MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 | ||
| 249 | MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 | ||
| 250 | MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 | ||
| 251 | MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 | ||
| 252 | MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 | ||
| 253 | MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 | ||
| 254 | MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 | ||
| 255 | MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 | ||
| 256 | MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 | ||
| 257 | MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 | ||
| 258 | MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 | ||
| 259 | MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 | ||
| 260 | MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 | ||
| 261 | MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 | ||
| 262 | >; | ||
| 263 | }; | ||
| 264 | |||
| 265 | pinctrl_uart1: uart1grp { | ||
| 266 | fsl,pins = < | ||
| 267 | MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 | ||
| 268 | MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 | ||
| 269 | >; | ||
| 270 | }; | ||
| 271 | }; | ||
| 272 | }; | ||
| 273 | |||
| 274 | &uart1 { | ||
| 275 | pinctrl-names = "default"; | ||
| 276 | pinctrl-0 = <&pinctrl_uart1>; | ||
| 277 | status = "okay"; | ||
| 278 | }; | ||
| 279 | |||
| 280 | &i2c2 { | ||
| 281 | pinctrl-names = "default"; | ||
| 282 | pinctrl-0 = <&pinctrl_i2c2>; | ||
| 283 | status = "okay"; | ||
| 284 | |||
| 285 | sgtl5000: codec@0a { | ||
| 286 | compatible = "fsl,sgtl5000"; | ||
| 287 | reg = <0x0a>; | ||
| 288 | VDDA-supply = <®_3p2v>; | ||
| 289 | VDDIO-supply = <®_3p2v>; | ||
| 290 | clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; | ||
| 291 | }; | ||
| 292 | }; | ||
| 293 | |||
| 294 | &i2c1 { | ||
| 295 | pinctrl-names = "default"; | ||
| 296 | pinctrl-0 = <&pinctrl_i2c1>; | ||
| 297 | status = "okay"; | ||
| 298 | |||
| 299 | accelerometer: mma8450@1c { | ||
| 300 | compatible = "fsl,mma8450"; | ||
| 301 | reg = <0x1c>; | ||
| 302 | }; | ||
| 303 | }; | ||
| 304 | |||
| 305 | &audmux { | ||
| 306 | pinctrl-names = "default"; | ||
| 307 | pinctrl-0 = <&pinctrl_audmux>; | ||
| 308 | status = "okay"; | ||
| 309 | }; | ||
| 310 | |||
| 311 | &fec { | ||
| 312 | pinctrl-names = "default"; | ||
| 313 | pinctrl-0 = <&pinctrl_fec>; | ||
| 314 | phy-mode = "rmii"; | ||
| 315 | phy-reset-gpios = <&gpio7 6 0>; | ||
| 316 | status = "okay"; | ||
| 317 | }; | ||
| 318 | |||
| 319 | &sata { | ||
| 320 | status = "okay"; | ||
| 321 | }; | ||
| 322 | |||
| 323 | &vpu { | ||
| 324 | status = "okay"; | ||
| 325 | }; | ||
| 326 | |||
| 327 | &usbh1 { | ||
| 328 | vbus-supply = <®_usb_vbus>; | ||
| 329 | phy_type = "utmi"; | ||
| 330 | status = "okay"; | ||
| 331 | }; | ||
| 332 | |||
| 333 | &usbotg { | ||
| 334 | dr_mode = "peripheral"; | ||
| 335 | status = "okay"; | ||
| 336 | }; | ||
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts index 91a5935a4aac..dec4b073ceb1 100644 --- a/arch/arm/boot/dts/imx53-qsb.dts +++ b/arch/arm/boot/dts/imx53-qsb.dts | |||
| @@ -11,193 +11,14 @@ | |||
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | /dts-v1/; | 13 | /dts-v1/; |
| 14 | #include "imx53.dtsi" | 14 | #include "imx53-qsb-common.dtsi" |
| 15 | 15 | ||
| 16 | / { | 16 | / { |
| 17 | model = "Freescale i.MX53 Quick Start Board"; | 17 | model = "Freescale i.MX53 Quick Start Board"; |
| 18 | compatible = "fsl,imx53-qsb", "fsl,imx53"; | 18 | compatible = "fsl,imx53-qsb", "fsl,imx53"; |
| 19 | |||
| 20 | memory { | ||
| 21 | reg = <0x70000000 0x40000000>; | ||
| 22 | }; | ||
| 23 | |||
| 24 | display@di0 { | ||
| 25 | compatible = "fsl,imx-parallel-display"; | ||
| 26 | crtcs = <&ipu 0>; | ||
| 27 | interface-pix-fmt = "rgb565"; | ||
| 28 | pinctrl-names = "default"; | ||
| 29 | pinctrl-0 = <&pinctrl_ipu_disp0_1>; | ||
| 30 | status = "disabled"; | ||
| 31 | display-timings { | ||
| 32 | claawvga { | ||
| 33 | native-mode; | ||
| 34 | clock-frequency = <27000000>; | ||
| 35 | hactive = <800>; | ||
| 36 | vactive = <480>; | ||
| 37 | hback-porch = <40>; | ||
| 38 | hfront-porch = <60>; | ||
| 39 | vback-porch = <10>; | ||
| 40 | vfront-porch = <10>; | ||
| 41 | hsync-len = <20>; | ||
| 42 | vsync-len = <10>; | ||
| 43 | hsync-active = <0>; | ||
| 44 | vsync-active = <0>; | ||
| 45 | de-active = <1>; | ||
| 46 | pixelclk-active = <0>; | ||
| 47 | }; | ||
| 48 | }; | ||
| 49 | }; | ||
| 50 | |||
| 51 | gpio-keys { | ||
| 52 | compatible = "gpio-keys"; | ||
| 53 | |||
| 54 | power { | ||
| 55 | label = "Power Button"; | ||
| 56 | gpios = <&gpio1 8 0>; | ||
| 57 | linux,code = <116>; /* KEY_POWER */ | ||
| 58 | }; | ||
| 59 | |||
| 60 | volume-up { | ||
| 61 | label = "Volume Up"; | ||
| 62 | gpios = <&gpio2 14 0>; | ||
| 63 | linux,code = <115>; /* KEY_VOLUMEUP */ | ||
| 64 | gpio-key,wakeup; | ||
| 65 | }; | ||
| 66 | |||
| 67 | volume-down { | ||
| 68 | label = "Volume Down"; | ||
| 69 | gpios = <&gpio2 15 0>; | ||
| 70 | linux,code = <114>; /* KEY_VOLUMEDOWN */ | ||
| 71 | gpio-key,wakeup; | ||
| 72 | }; | ||
| 73 | }; | ||
| 74 | |||
| 75 | leds { | ||
| 76 | compatible = "gpio-leds"; | ||
| 77 | pinctrl-names = "default"; | ||
| 78 | pinctrl-0 = <&led_pin_gpio7_7>; | ||
| 79 | |||
| 80 | user { | ||
| 81 | label = "Heartbeat"; | ||
| 82 | gpios = <&gpio7 7 0>; | ||
| 83 | linux,default-trigger = "heartbeat"; | ||
| 84 | }; | ||
| 85 | }; | ||
| 86 | |||
| 87 | regulators { | ||
| 88 | compatible = "simple-bus"; | ||
| 89 | |||
| 90 | reg_3p2v: 3p2v { | ||
| 91 | compatible = "regulator-fixed"; | ||
| 92 | regulator-name = "3P2V"; | ||
| 93 | regulator-min-microvolt = <3200000>; | ||
| 94 | regulator-max-microvolt = <3200000>; | ||
| 95 | regulator-always-on; | ||
| 96 | }; | ||
| 97 | |||
| 98 | reg_usb_vbus: usb_vbus { | ||
| 99 | compatible = "regulator-fixed"; | ||
| 100 | regulator-name = "usb_vbus"; | ||
| 101 | regulator-min-microvolt = <5000000>; | ||
| 102 | regulator-max-microvolt = <5000000>; | ||
| 103 | gpio = <&gpio7 8 0>; | ||
| 104 | enable-active-high; | ||
| 105 | }; | ||
| 106 | }; | ||
| 107 | |||
| 108 | sound { | ||
| 109 | compatible = "fsl,imx53-qsb-sgtl5000", | ||
| 110 | "fsl,imx-audio-sgtl5000"; | ||
| 111 | model = "imx53-qsb-sgtl5000"; | ||
| 112 | ssi-controller = <&ssi2>; | ||
| 113 | audio-codec = <&sgtl5000>; | ||
| 114 | audio-routing = | ||
| 115 | "MIC_IN", "Mic Jack", | ||
| 116 | "Mic Jack", "Mic Bias", | ||
| 117 | "Headphone Jack", "HP_OUT"; | ||
| 118 | mux-int-port = <2>; | ||
| 119 | mux-ext-port = <5>; | ||
| 120 | }; | ||
| 121 | }; | ||
| 122 | |||
| 123 | &esdhc1 { | ||
| 124 | pinctrl-names = "default"; | ||
| 125 | pinctrl-0 = <&pinctrl_esdhc1_1>; | ||
| 126 | status = "okay"; | ||
| 127 | }; | ||
| 128 | |||
| 129 | &ssi2 { | ||
| 130 | fsl,mode = "i2s-slave"; | ||
| 131 | status = "okay"; | ||
| 132 | }; | ||
| 133 | |||
| 134 | &esdhc3 { | ||
| 135 | pinctrl-names = "default"; | ||
| 136 | pinctrl-0 = <&pinctrl_esdhc3_1>; | ||
| 137 | cd-gpios = <&gpio3 11 0>; | ||
| 138 | wp-gpios = <&gpio3 12 0>; | ||
| 139 | bus-width = <8>; | ||
| 140 | status = "okay"; | ||
| 141 | }; | ||
| 142 | |||
| 143 | &iomuxc { | ||
| 144 | pinctrl-names = "default"; | ||
| 145 | pinctrl-0 = <&pinctrl_hog>; | ||
| 146 | |||
| 147 | hog { | ||
| 148 | pinctrl_hog: hoggrp { | ||
| 149 | fsl,pins = < | ||
| 150 | MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 | ||
| 151 | MX53_PAD_GPIO_8__GPIO1_8 0x80000000 | ||
| 152 | MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 | ||
| 153 | MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 | ||
| 154 | MX53_PAD_EIM_DA11__GPIO3_11 0x80000000 | ||
| 155 | MX53_PAD_EIM_DA12__GPIO3_12 0x80000000 | ||
| 156 | MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 | ||
| 157 | MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 | ||
| 158 | MX53_PAD_GPIO_16__GPIO7_11 0x80000000 | ||
| 159 | >; | ||
| 160 | }; | ||
| 161 | |||
| 162 | led_pin_gpio7_7: led_gpio7_7@0 { | ||
| 163 | fsl,pins = < | ||
| 164 | MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 | ||
| 165 | >; | ||
| 166 | }; | ||
| 167 | }; | ||
| 168 | |||
| 169 | }; | ||
| 170 | |||
| 171 | &uart1 { | ||
| 172 | pinctrl-names = "default"; | ||
| 173 | pinctrl-0 = <&pinctrl_uart1_1>; | ||
| 174 | status = "okay"; | ||
| 175 | }; | ||
| 176 | |||
| 177 | &i2c2 { | ||
| 178 | pinctrl-names = "default"; | ||
| 179 | pinctrl-0 = <&pinctrl_i2c2_1>; | ||
| 180 | status = "okay"; | ||
| 181 | |||
| 182 | sgtl5000: codec@0a { | ||
| 183 | compatible = "fsl,sgtl5000"; | ||
| 184 | reg = <0x0a>; | ||
| 185 | VDDA-supply = <®_3p2v>; | ||
| 186 | VDDIO-supply = <®_3p2v>; | ||
| 187 | clocks = <&clks 150>; | ||
| 188 | }; | ||
| 189 | }; | 19 | }; |
| 190 | 20 | ||
| 191 | &i2c1 { | 21 | &i2c1 { |
| 192 | pinctrl-names = "default"; | ||
| 193 | pinctrl-0 = <&pinctrl_i2c1_1>; | ||
| 194 | status = "okay"; | ||
| 195 | |||
| 196 | accelerometer: mma8450@1c { | ||
| 197 | compatible = "fsl,mma8450"; | ||
| 198 | reg = <0x1c>; | ||
| 199 | }; | ||
| 200 | |||
| 201 | pmic: dialog@48 { | 22 | pmic: dialog@48 { |
| 202 | compatible = "dlg,da9053-aa", "dlg,da9052"; | 23 | compatible = "dlg,da9053-aa", "dlg,da9052"; |
| 203 | reg = <0x48>; | 24 | reg = <0x48>; |
| @@ -292,32 +113,3 @@ | |||
| 292 | }; | 113 | }; |
| 293 | }; | 114 | }; |
| 294 | }; | 115 | }; |
| 295 | |||
| 296 | &audmux { | ||
| 297 | pinctrl-names = "default"; | ||
| 298 | pinctrl-0 = <&pinctrl_audmux_1>; | ||
| 299 | status = "okay"; | ||
| 300 | }; | ||
| 301 | |||
| 302 | &fec { | ||
| 303 | pinctrl-names = "default"; | ||
| 304 | pinctrl-0 = <&pinctrl_fec_1>; | ||
| 305 | phy-mode = "rmii"; | ||
| 306 | phy-reset-gpios = <&gpio7 6 0>; | ||
| 307 | status = "okay"; | ||
| 308 | }; | ||
| 309 | |||
| 310 | &vpu { | ||
| 311 | status = "okay"; | ||
| 312 | }; | ||
| 313 | |||
| 314 | &usbh1 { | ||
| 315 | vbus-supply = <®_usb_vbus>; | ||
| 316 | phy_type = "utmi"; | ||
| 317 | status = "okay"; | ||
| 318 | }; | ||
| 319 | |||
| 320 | &usbotg { | ||
| 321 | dr_mode = "peripheral"; | ||
| 322 | status = "okay"; | ||
| 323 | }; | ||
diff --git a/arch/arm/boot/dts/imx53-qsrb.dts b/arch/arm/boot/dts/imx53-qsrb.dts new file mode 100644 index 000000000000..f1bbf9a32991 --- /dev/null +++ b/arch/arm/boot/dts/imx53-qsrb.dts | |||
| @@ -0,0 +1,158 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. | ||
| 3 | * Copyright 2011 Linaro Ltd. | ||
| 4 | * | ||
| 5 | * The code contained herein is licensed under the GNU General Public | ||
| 6 | * License. You may obtain a copy of the GNU General Public License | ||
| 7 | * Version 2 or later at the following locations: | ||
| 8 | * | ||
| 9 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 10 | * http://www.gnu.org/copyleft/gpl.html | ||
| 11 | */ | ||
| 12 | |||
| 13 | /dts-v1/; | ||
| 14 | |||
| 15 | #include "imx53-qsb-common.dtsi" | ||
| 16 | |||
| 17 | / { | ||
| 18 | model = "Freescale i.MX53 Quick Start-R Board"; | ||
| 19 | compatible = "fsl,imx53-qsrb", "fsl,imx53"; | ||
| 20 | }; | ||
| 21 | |||
| 22 | &iomuxc { | ||
| 23 | i2c1 { | ||
| 24 | /* open drain */ | ||
| 25 | pinctrl_i2c1_qsrb: i2c1grp-1 { | ||
| 26 | fsl,pins = < | ||
| 27 | MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec | ||
| 28 | MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec | ||
| 29 | >; | ||
| 30 | }; | ||
| 31 | }; | ||
| 32 | }; | ||
| 33 | |||
| 34 | &i2c1 { | ||
| 35 | pinctrl-names = "default"; | ||
| 36 | pinctrl-0 = <&pinctrl_i2c1_qsrb>; | ||
| 37 | status = "okay"; | ||
| 38 | |||
| 39 | pmic: mc34708@8 { | ||
| 40 | compatible = "fsl,mc34708"; | ||
| 41 | reg = <0x08>; | ||
| 42 | interrupt-parent = <&gpio5>; | ||
| 43 | interrupts = <23 0x8>; | ||
| 44 | regulators { | ||
| 45 | sw1_reg: sw1a { | ||
| 46 | regulator-name = "SW1"; | ||
| 47 | regulator-min-microvolt = <650000>; | ||
| 48 | regulator-max-microvolt = <1437500>; | ||
| 49 | regulator-boot-on; | ||
| 50 | regulator-always-on; | ||
| 51 | }; | ||
| 52 | |||
| 53 | sw1b_reg: sw1b { | ||
| 54 | regulator-name = "SW1B"; | ||
| 55 | regulator-min-microvolt = <650000>; | ||
| 56 | regulator-max-microvolt = <1437500>; | ||
| 57 | regulator-boot-on; | ||
| 58 | regulator-always-on; | ||
| 59 | }; | ||
| 60 | |||
| 61 | sw2_reg: sw2 { | ||
| 62 | regulator-name = "SW2"; | ||
| 63 | regulator-min-microvolt = <650000>; | ||
| 64 | regulator-max-microvolt = <1437500>; | ||
| 65 | regulator-boot-on; | ||
| 66 | regulator-always-on; | ||
| 67 | }; | ||
| 68 | |||
| 69 | sw3_reg: sw3 { | ||
| 70 | regulator-name = "SW3"; | ||
| 71 | regulator-min-microvolt = <650000>; | ||
| 72 | regulator-max-microvolt = <1425000>; | ||
| 73 | regulator-boot-on; | ||
| 74 | }; | ||
| 75 | |||
| 76 | sw4a_reg: sw4a { | ||
| 77 | regulator-name = "SW4A"; | ||
| 78 | regulator-min-microvolt = <1200000>; | ||
| 79 | regulator-max-microvolt = <3300000>; | ||
| 80 | regulator-boot-on; | ||
| 81 | regulator-always-on; | ||
| 82 | }; | ||
| 83 | |||
| 84 | sw4b_reg: sw4b { | ||
| 85 | regulator-name = "SW4B"; | ||
| 86 | regulator-min-microvolt = <1200000>; | ||
| 87 | regulator-max-microvolt = <3300000>; | ||
| 88 | regulator-boot-on; | ||
| 89 | regulator-always-on; | ||
| 90 | }; | ||
| 91 | |||
| 92 | sw5_reg: sw5 { | ||
| 93 | regulator-name = "SW5"; | ||
| 94 | regulator-min-microvolt = <1200000>; | ||
| 95 | regulator-max-microvolt = <1975000>; | ||
| 96 | regulator-boot-on; | ||
| 97 | regulator-always-on; | ||
| 98 | }; | ||
| 99 | |||
| 100 | swbst_reg: swbst { | ||
| 101 | regulator-name = "SWBST"; | ||
| 102 | regulator-boot-on; | ||
| 103 | regulator-always-on; | ||
| 104 | }; | ||
| 105 | |||
| 106 | vpll_reg: vpll { | ||
| 107 | regulator-name = "VPLL"; | ||
| 108 | regulator-min-microvolt = <1200000>; | ||
| 109 | regulator-max-microvolt = <1800000>; | ||
| 110 | regulator-boot-on; | ||
| 111 | }; | ||
| 112 | |||
| 113 | vrefddr_reg: vrefddr { | ||
| 114 | regulator-name = "VREFDDR"; | ||
| 115 | regulator-boot-on; | ||
| 116 | regulator-always-on; | ||
| 117 | }; | ||
| 118 | |||
| 119 | vusb_reg: vusb { | ||
| 120 | regulator-name = "VUSB"; | ||
| 121 | regulator-boot-on; | ||
| 122 | regulator-always-on; | ||
| 123 | }; | ||
| 124 | |||
| 125 | vusb2_reg: vusb2 { | ||
| 126 | regulator-name = "VUSB2"; | ||
| 127 | regulator-min-microvolt = <2500000>; | ||
| 128 | regulator-max-microvolt = <3000000>; | ||
| 129 | regulator-boot-on; | ||
| 130 | regulator-always-on; | ||
| 131 | }; | ||
| 132 | |||
| 133 | vdac_reg: vdac { | ||
| 134 | regulator-name = "VDAC"; | ||
| 135 | regulator-min-microvolt = <2500000>; | ||
| 136 | regulator-max-microvolt = <2775000>; | ||
| 137 | regulator-boot-on; | ||
| 138 | regulator-always-on; | ||
| 139 | }; | ||
| 140 | |||
| 141 | vgen1_reg: vgen1 { | ||
| 142 | regulator-name = "VGEN1"; | ||
| 143 | regulator-min-microvolt = <1200000>; | ||
| 144 | regulator-max-microvolt = <1550000>; | ||
| 145 | regulator-boot-on; | ||
| 146 | regulator-always-on; | ||
| 147 | }; | ||
| 148 | |||
| 149 | vgen2_reg: vgen2 { | ||
| 150 | regulator-name = "VGEN2"; | ||
| 151 | regulator-min-microvolt = <2500000>; | ||
| 152 | regulator-max-microvolt = <3300000>; | ||
| 153 | regulator-boot-on; | ||
| 154 | regulator-always-on; | ||
| 155 | }; | ||
| 156 | }; | ||
| 157 | }; | ||
| 158 | }; | ||
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts index a9b6e10de0a5..5ec1590ff7bc 100644 --- a/arch/arm/boot/dts/imx53-smd.dts +++ b/arch/arm/boot/dts/imx53-smd.dts | |||
| @@ -40,7 +40,7 @@ | |||
| 40 | 40 | ||
| 41 | &esdhc1 { | 41 | &esdhc1 { |
| 42 | pinctrl-names = "default"; | 42 | pinctrl-names = "default"; |
| 43 | pinctrl-0 = <&pinctrl_esdhc1_1>; | 43 | pinctrl-0 = <&pinctrl_esdhc1>; |
| 44 | cd-gpios = <&gpio3 13 0>; | 44 | cd-gpios = <&gpio3 13 0>; |
| 45 | wp-gpios = <&gpio4 11 0>; | 45 | wp-gpios = <&gpio4 11 0>; |
| 46 | status = "okay"; | 46 | status = "okay"; |
| @@ -48,21 +48,21 @@ | |||
| 48 | 48 | ||
| 49 | &esdhc2 { | 49 | &esdhc2 { |
| 50 | pinctrl-names = "default"; | 50 | pinctrl-names = "default"; |
| 51 | pinctrl-0 = <&pinctrl_esdhc2_1>; | 51 | pinctrl-0 = <&pinctrl_esdhc2>; |
| 52 | non-removable; | 52 | non-removable; |
| 53 | status = "okay"; | 53 | status = "okay"; |
| 54 | }; | 54 | }; |
| 55 | 55 | ||
| 56 | &uart3 { | 56 | &uart3 { |
| 57 | pinctrl-names = "default"; | 57 | pinctrl-names = "default"; |
| 58 | pinctrl-0 = <&pinctrl_uart3_1>; | 58 | pinctrl-0 = <&pinctrl_uart3>; |
| 59 | fsl,uart-has-rtscts; | 59 | fsl,uart-has-rtscts; |
| 60 | status = "okay"; | 60 | status = "okay"; |
| 61 | }; | 61 | }; |
| 62 | 62 | ||
| 63 | &ecspi1 { | 63 | &ecspi1 { |
| 64 | pinctrl-names = "default"; | 64 | pinctrl-names = "default"; |
| 65 | pinctrl-0 = <&pinctrl_ecspi1_1>; | 65 | pinctrl-0 = <&pinctrl_ecspi1>; |
| 66 | fsl,spi-num-chipselects = <2>; | 66 | fsl,spi-num-chipselects = <2>; |
| 67 | cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; | 67 | cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; |
| 68 | status = "okay"; | 68 | status = "okay"; |
| @@ -95,7 +95,7 @@ | |||
| 95 | 95 | ||
| 96 | &esdhc3 { | 96 | &esdhc3 { |
| 97 | pinctrl-names = "default"; | 97 | pinctrl-names = "default"; |
| 98 | pinctrl-0 = <&pinctrl_esdhc3_1>; | 98 | pinctrl-0 = <&pinctrl_esdhc3>; |
| 99 | non-removable; | 99 | non-removable; |
| 100 | status = "okay"; | 100 | status = "okay"; |
| 101 | }; | 101 | }; |
| @@ -104,7 +104,7 @@ | |||
| 104 | pinctrl-names = "default"; | 104 | pinctrl-names = "default"; |
| 105 | pinctrl-0 = <&pinctrl_hog>; | 105 | pinctrl-0 = <&pinctrl_hog>; |
| 106 | 106 | ||
| 107 | hog { | 107 | imx53-smd { |
| 108 | pinctrl_hog: hoggrp { | 108 | pinctrl_hog: hoggrp { |
| 109 | fsl,pins = < | 109 | fsl,pins = < |
| 110 | MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 | 110 | MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 |
| @@ -116,24 +116,121 @@ | |||
| 116 | MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 | 116 | MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 |
| 117 | >; | 117 | >; |
| 118 | }; | 118 | }; |
| 119 | |||
| 120 | pinctrl_ecspi1: ecspi1grp { | ||
| 121 | fsl,pins = < | ||
| 122 | MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 | ||
| 123 | MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 | ||
| 124 | MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 | ||
| 125 | >; | ||
| 126 | }; | ||
| 127 | |||
| 128 | pinctrl_esdhc1: esdhc1grp { | ||
| 129 | fsl,pins = < | ||
| 130 | MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 | ||
| 131 | MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 | ||
| 132 | MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 | ||
| 133 | MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 | ||
| 134 | MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 | ||
| 135 | MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 | ||
| 136 | >; | ||
| 137 | }; | ||
| 138 | |||
| 139 | pinctrl_esdhc2: esdhc2grp { | ||
| 140 | fsl,pins = < | ||
| 141 | MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 | ||
| 142 | MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 | ||
| 143 | MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 | ||
| 144 | MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 | ||
| 145 | MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 | ||
| 146 | MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 | ||
| 147 | >; | ||
| 148 | }; | ||
| 149 | |||
| 150 | pinctrl_esdhc3: esdhc3grp { | ||
| 151 | fsl,pins = < | ||
| 152 | MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 | ||
| 153 | MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 | ||
| 154 | MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 | ||
| 155 | MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 | ||
| 156 | MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 | ||
| 157 | MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 | ||
| 158 | MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 | ||
| 159 | MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 | ||
| 160 | MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 | ||
| 161 | MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 | ||
| 162 | >; | ||
| 163 | }; | ||
| 164 | |||
| 165 | pinctrl_fec: fecgrp { | ||
| 166 | fsl,pins = < | ||
| 167 | MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 | ||
| 168 | MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 | ||
| 169 | MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 | ||
| 170 | MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 | ||
| 171 | MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 | ||
| 172 | MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 | ||
| 173 | MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 | ||
| 174 | MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 | ||
| 175 | MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 | ||
| 176 | MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 | ||
| 177 | >; | ||
| 178 | }; | ||
| 179 | |||
| 180 | pinctrl_i2c1: i2c1grp { | ||
| 181 | fsl,pins = < | ||
| 182 | MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000 | ||
| 183 | MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000 | ||
| 184 | >; | ||
| 185 | }; | ||
| 186 | |||
| 187 | pinctrl_i2c2: i2c2grp { | ||
| 188 | fsl,pins = < | ||
| 189 | MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 | ||
| 190 | MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 | ||
| 191 | >; | ||
| 192 | }; | ||
| 193 | |||
| 194 | pinctrl_uart1: uart1grp { | ||
| 195 | fsl,pins = < | ||
| 196 | MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 | ||
| 197 | MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 | ||
| 198 | >; | ||
| 199 | }; | ||
| 200 | |||
| 201 | pinctrl_uart2: uart2grp { | ||
| 202 | fsl,pins = < | ||
| 203 | MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 | ||
| 204 | MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 | ||
| 205 | >; | ||
| 206 | }; | ||
| 207 | |||
| 208 | pinctrl_uart3: uart3grp { | ||
| 209 | fsl,pins = < | ||
| 210 | MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 | ||
| 211 | MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 | ||
| 212 | MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 | ||
| 213 | MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 | ||
| 214 | >; | ||
| 215 | }; | ||
| 119 | }; | 216 | }; |
| 120 | }; | 217 | }; |
| 121 | 218 | ||
| 122 | &uart1 { | 219 | &uart1 { |
| 123 | pinctrl-names = "default"; | 220 | pinctrl-names = "default"; |
| 124 | pinctrl-0 = <&pinctrl_uart1_1>; | 221 | pinctrl-0 = <&pinctrl_uart1>; |
| 125 | status = "okay"; | 222 | status = "okay"; |
| 126 | }; | 223 | }; |
| 127 | 224 | ||
| 128 | &uart2 { | 225 | &uart2 { |
| 129 | pinctrl-names = "default"; | 226 | pinctrl-names = "default"; |
| 130 | pinctrl-0 = <&pinctrl_uart2_1>; | 227 | pinctrl-0 = <&pinctrl_uart2>; |
| 131 | status = "okay"; | 228 | status = "okay"; |
| 132 | }; | 229 | }; |
| 133 | 230 | ||
| 134 | &i2c2 { | 231 | &i2c2 { |
| 135 | pinctrl-names = "default"; | 232 | pinctrl-names = "default"; |
| 136 | pinctrl-0 = <&pinctrl_i2c2_1>; | 233 | pinctrl-0 = <&pinctrl_i2c2>; |
| 137 | status = "okay"; | 234 | status = "okay"; |
| 138 | 235 | ||
| 139 | codec: sgtl5000@0a { | 236 | codec: sgtl5000@0a { |
| @@ -154,7 +251,7 @@ | |||
| 154 | 251 | ||
| 155 | &i2c1 { | 252 | &i2c1 { |
| 156 | pinctrl-names = "default"; | 253 | pinctrl-names = "default"; |
| 157 | pinctrl-0 = <&pinctrl_i2c1_1>; | 254 | pinctrl-0 = <&pinctrl_i2c1>; |
| 158 | status = "okay"; | 255 | status = "okay"; |
| 159 | 256 | ||
| 160 | accelerometer: mma8450@1c { | 257 | accelerometer: mma8450@1c { |
| @@ -175,7 +272,7 @@ | |||
| 175 | 272 | ||
| 176 | &fec { | 273 | &fec { |
| 177 | pinctrl-names = "default"; | 274 | pinctrl-names = "default"; |
| 178 | pinctrl-0 = <&pinctrl_fec_1>; | 275 | pinctrl-0 = <&pinctrl_fec>; |
| 179 | phy-mode = "rmii"; | 276 | phy-mode = "rmii"; |
| 180 | phy-reset-gpios = <&gpio7 6 0>; | 277 | phy-reset-gpios = <&gpio7 6 0>; |
| 181 | status = "okay"; | 278 | status = "okay"; |
diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/imx53-tqma53.dtsi index abd72af545bf..4f1f0e2868bf 100644 --- a/arch/arm/boot/dts/imx53-tqma53.dtsi +++ b/arch/arm/boot/dts/imx53-tqma53.dtsi | |||
| @@ -22,9 +22,12 @@ | |||
| 22 | 22 | ||
| 23 | regulators { | 23 | regulators { |
| 24 | compatible = "simple-bus"; | 24 | compatible = "simple-bus"; |
| 25 | #address-cells = <1>; | ||
| 26 | #size-cells = <0>; | ||
| 25 | 27 | ||
| 26 | reg_3p3v: 3p3v { | 28 | reg_3p3v: regulator@0 { |
| 27 | compatible = "regulator-fixed"; | 29 | compatible = "regulator-fixed"; |
| 30 | reg = <0>; | ||
| 28 | regulator-name = "3P3V"; | 31 | regulator-name = "3P3V"; |
| 29 | regulator-min-microvolt = <3300000>; | 32 | regulator-min-microvolt = <3300000>; |
| 30 | regulator-max-microvolt = <3300000>; | 33 | regulator-max-microvolt = <3300000>; |
| @@ -35,8 +38,8 @@ | |||
| 35 | 38 | ||
| 36 | &esdhc2 { | 39 | &esdhc2 { |
| 37 | pinctrl-names = "default"; | 40 | pinctrl-names = "default"; |
| 38 | pinctrl-0 = <&pinctrl_esdhc2_1>, | 41 | pinctrl-0 = <&pinctrl_esdhc2>, |
| 39 | <&pinctrl_tqma53_esdhc2_2>; | 42 | <&pinctrl_esdhc2_cdwp>; |
| 40 | vmmc-supply = <®_3p3v>; | 43 | vmmc-supply = <®_3p3v>; |
| 41 | wp-gpios = <&gpio1 2 0>; | 44 | wp-gpios = <&gpio1 2 0>; |
| 42 | cd-gpios = <&gpio1 4 0>; | 45 | cd-gpios = <&gpio1 4 0>; |
| @@ -45,13 +48,13 @@ | |||
| 45 | 48 | ||
| 46 | &uart3 { | 49 | &uart3 { |
| 47 | pinctrl-names = "default"; | 50 | pinctrl-names = "default"; |
| 48 | pinctrl-0 = <&pinctrl_uart3_2>; | 51 | pinctrl-0 = <&pinctrl_uart3>; |
| 49 | status = "disabled"; | 52 | status = "disabled"; |
| 50 | }; | 53 | }; |
| 51 | 54 | ||
| 52 | &ecspi1 { | 55 | &ecspi1 { |
| 53 | pinctrl-names = "default"; | 56 | pinctrl-names = "default"; |
| 54 | pinctrl-0 = <&pinctrl_ecspi1_1>; | 57 | pinctrl-0 = <&pinctrl_ecspi1>; |
| 55 | fsl,spi-num-chipselects = <4>; | 58 | fsl,spi-num-chipselects = <4>; |
| 56 | cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>, | 59 | cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>, |
| 57 | <&gpio3 24 0>, <&gpio3 25 0>; | 60 | <&gpio3 24 0>, <&gpio3 25 0>; |
| @@ -60,7 +63,7 @@ | |||
| 60 | 63 | ||
| 61 | &esdhc3 { /* EMMC */ | 64 | &esdhc3 { /* EMMC */ |
| 62 | pinctrl-names = "default"; | 65 | pinctrl-names = "default"; |
| 63 | pinctrl-0 = <&pinctrl_esdhc3_1>; | 66 | pinctrl-0 = <&pinctrl_esdhc3>; |
| 64 | vmmc-supply = <®_3p3v>; | 67 | vmmc-supply = <®_3p3v>; |
| 65 | non-removable; | 68 | non-removable; |
| 66 | bus-width = <8>; | 69 | bus-width = <8>; |
| @@ -71,27 +74,7 @@ | |||
| 71 | pinctrl-names = "default"; | 74 | pinctrl-names = "default"; |
| 72 | pinctrl-0 = <&pinctrl_hog>; | 75 | pinctrl-0 = <&pinctrl_hog>; |
| 73 | 76 | ||
| 74 | esdhc2_2 { | 77 | imx53-tqma53 { |
| 75 | pinctrl_tqma53_esdhc2_2: esdhc2-tqma53-grp2 { | ||
| 76 | fsl,pins = < | ||
| 77 | MX53_PAD_GPIO_4__GPIO1_4 0x80000000 /* SD2_CD */ | ||
| 78 | MX53_PAD_GPIO_2__GPIO1_2 0x80000000 /* SD2_WP */ | ||
| 79 | >; | ||
| 80 | }; | ||
| 81 | }; | ||
| 82 | |||
| 83 | i2s { | ||
| 84 | pinctrl_i2s_1: i2s-grp1 { | ||
| 85 | fsl,pins = < | ||
| 86 | MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 /* I2S_SCLK */ | ||
| 87 | MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 /* I2S_DOUT */ | ||
| 88 | MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 /* I2S_LRCLK */ | ||
| 89 | MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 /* I2S_DIN */ | ||
| 90 | >; | ||
| 91 | }; | ||
| 92 | }; | ||
| 93 | |||
| 94 | hog { | ||
| 95 | pinctrl_hog: hoggrp { | 78 | pinctrl_hog: hoggrp { |
| 96 | fsl,pins = < | 79 | fsl,pins = < |
| 97 | MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */ | 80 | MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */ |
| @@ -107,43 +90,165 @@ | |||
| 107 | MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 /* LCD_CONTRAST */ | 90 | MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 /* LCD_CONTRAST */ |
| 108 | >; | 91 | >; |
| 109 | }; | 92 | }; |
| 93 | |||
| 94 | pinctrl_audmux: audmuxgrp { | ||
| 95 | fsl,pins = < | ||
| 96 | MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 | ||
| 97 | MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 | ||
| 98 | MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 | ||
| 99 | MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 | ||
| 100 | >; | ||
| 101 | }; | ||
| 102 | |||
| 103 | pinctrl_can1: can1grp { | ||
| 104 | fsl,pins = < | ||
| 105 | MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000 | ||
| 106 | MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000 | ||
| 107 | >; | ||
| 108 | }; | ||
| 109 | |||
| 110 | pinctrl_can2: can2grp { | ||
| 111 | fsl,pins = < | ||
| 112 | MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 | ||
| 113 | MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 | ||
| 114 | >; | ||
| 115 | }; | ||
| 116 | |||
| 117 | pinctrl_cspi: cspigrp { | ||
| 118 | fsl,pins = < | ||
| 119 | MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5 | ||
| 120 | MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5 | ||
| 121 | MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5 | ||
| 122 | >; | ||
| 123 | }; | ||
| 124 | |||
| 125 | pinctrl_ecspi1: ecspi1grp { | ||
| 126 | fsl,pins = < | ||
| 127 | MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 | ||
| 128 | MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 | ||
| 129 | MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 | ||
| 130 | >; | ||
| 131 | }; | ||
| 132 | |||
| 133 | pinctrl_esdhc2: esdhc2grp { | ||
| 134 | fsl,pins = < | ||
| 135 | MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 | ||
| 136 | MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 | ||
| 137 | MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 | ||
| 138 | MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 | ||
| 139 | MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 | ||
| 140 | MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 | ||
| 141 | >; | ||
| 142 | }; | ||
| 143 | |||
| 144 | pinctrl_esdhc2_cdwp: esdhc2cdwp { | ||
| 145 | fsl,pins = < | ||
| 146 | MX53_PAD_GPIO_4__GPIO1_4 0x80000000 /* SD2_CD */ | ||
| 147 | MX53_PAD_GPIO_2__GPIO1_2 0x80000000 /* SD2_WP */ | ||
| 148 | >; | ||
| 149 | }; | ||
| 150 | |||
| 151 | pinctrl_esdhc3: esdhc3grp { | ||
| 152 | fsl,pins = < | ||
| 153 | MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 | ||
| 154 | MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 | ||
| 155 | MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 | ||
| 156 | MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 | ||
| 157 | MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 | ||
| 158 | MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 | ||
| 159 | MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 | ||
| 160 | MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 | ||
| 161 | MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 | ||
| 162 | MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 | ||
| 163 | >; | ||
| 164 | }; | ||
| 165 | |||
| 166 | pinctrl_fec: fecgrp { | ||
| 167 | fsl,pins = < | ||
| 168 | MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 | ||
| 169 | MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 | ||
| 170 | MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 | ||
| 171 | MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 | ||
| 172 | MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 | ||
| 173 | MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 | ||
| 174 | MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 | ||
| 175 | MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 | ||
| 176 | MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 | ||
| 177 | MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 | ||
| 178 | >; | ||
| 179 | }; | ||
| 180 | |||
| 181 | pinctrl_i2c2: i2c2grp { | ||
| 182 | fsl,pins = < | ||
| 183 | MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 | ||
| 184 | MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 | ||
| 185 | >; | ||
| 186 | }; | ||
| 187 | |||
| 188 | pinctrl_i2c3: i2c3grp { | ||
| 189 | fsl,pins = < | ||
| 190 | MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 | ||
| 191 | MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000 | ||
| 192 | >; | ||
| 193 | }; | ||
| 194 | |||
| 195 | pinctrl_uart1: uart1grp { | ||
| 196 | fsl,pins = < | ||
| 197 | MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 | ||
| 198 | MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 | ||
| 199 | >; | ||
| 200 | }; | ||
| 201 | |||
| 202 | pinctrl_uart2: uart2grp { | ||
| 203 | fsl,pins = < | ||
| 204 | MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 | ||
| 205 | MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 | ||
| 206 | >; | ||
| 207 | }; | ||
| 208 | |||
| 209 | pinctrl_uart3: uart3grp { | ||
| 210 | fsl,pins = < | ||
| 211 | MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 | ||
| 212 | MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 | ||
| 213 | >; | ||
| 214 | }; | ||
| 110 | }; | 215 | }; |
| 111 | }; | 216 | }; |
| 112 | 217 | ||
| 113 | &uart1 { | 218 | &uart1 { |
| 114 | pinctrl-names = "default"; | 219 | pinctrl-names = "default"; |
| 115 | pinctrl-0 = <&pinctrl_uart1_2>; | 220 | pinctrl-0 = <&pinctrl_uart1>; |
| 116 | fsl,uart-has-rtscts; | 221 | fsl,uart-has-rtscts; |
| 117 | status = "disabled"; | 222 | status = "disabled"; |
| 118 | }; | 223 | }; |
| 119 | 224 | ||
| 120 | &uart2 { | 225 | &uart2 { |
| 121 | pinctrl-names = "default"; | 226 | pinctrl-names = "default"; |
| 122 | pinctrl-0 = <&pinctrl_uart2_1>; | 227 | pinctrl-0 = <&pinctrl_uart2>; |
| 123 | status = "disabled"; | 228 | status = "disabled"; |
| 124 | }; | 229 | }; |
| 125 | 230 | ||
| 126 | &can1 { | 231 | &can1 { |
| 127 | pinctrl-names = "default"; | 232 | pinctrl-names = "default"; |
| 128 | pinctrl-0 = <&pinctrl_can1_2>; | 233 | pinctrl-0 = <&pinctrl_can1>; |
| 129 | status = "disabled"; | 234 | status = "disabled"; |
| 130 | }; | 235 | }; |
| 131 | 236 | ||
| 132 | &can2 { | 237 | &can2 { |
| 133 | pinctrl-names = "default"; | 238 | pinctrl-names = "default"; |
| 134 | pinctrl-0 = <&pinctrl_can2_1>; | 239 | pinctrl-0 = <&pinctrl_can2>; |
| 135 | status = "disabled"; | 240 | status = "disabled"; |
| 136 | }; | 241 | }; |
| 137 | 242 | ||
| 138 | &i2c3 { | 243 | &i2c3 { |
| 139 | pinctrl-names = "default"; | 244 | pinctrl-names = "default"; |
| 140 | pinctrl-0 = <&pinctrl_i2c3_1>; | 245 | pinctrl-0 = <&pinctrl_i2c3>; |
| 141 | status = "disabled"; | 246 | status = "disabled"; |
| 142 | }; | 247 | }; |
| 143 | 248 | ||
| 144 | &cspi { | 249 | &cspi { |
| 145 | pinctrl-names = "default"; | 250 | pinctrl-names = "default"; |
| 146 | pinctrl-0 = <&pinctrl_cspi_1>; | 251 | pinctrl-0 = <&pinctrl_cspi>; |
| 147 | fsl,spi-num-chipselects = <3>; | 252 | fsl,spi-num-chipselects = <3>; |
| 148 | cs-gpios = <&gpio1 18 0>, <&gpio1 19 0>, | 253 | cs-gpios = <&gpio1 18 0>, <&gpio1 19 0>, |
| 149 | <&gpio1 21 0>; | 254 | <&gpio1 21 0>; |
| @@ -152,7 +257,7 @@ | |||
| 152 | 257 | ||
| 153 | &i2c2 { | 258 | &i2c2 { |
| 154 | pinctrl-names = "default"; | 259 | pinctrl-names = "default"; |
| 155 | pinctrl-0 = <&pinctrl_i2c2_1>; | 260 | pinctrl-0 = <&pinctrl_i2c2>; |
| 156 | status = "okay"; | 261 | status = "okay"; |
| 157 | 262 | ||
| 158 | pmic: mc34708@8 { | 263 | pmic: mc34708@8 { |
| @@ -177,7 +282,7 @@ | |||
| 177 | 282 | ||
| 178 | &fec { | 283 | &fec { |
| 179 | pinctrl-names = "default"; | 284 | pinctrl-names = "default"; |
| 180 | pinctrl-0 = <&pinctrl_fec_1>; | 285 | pinctrl-0 = <&pinctrl_fec>; |
| 181 | phy-mode = "rmii"; | 286 | phy-mode = "rmii"; |
| 182 | status = "disabled"; | 287 | status = "disabled"; |
| 183 | }; | 288 | }; |
diff --git a/arch/arm/boot/dts/imx53-tx53-x03x.dts b/arch/arm/boot/dts/imx53-tx53-x03x.dts new file mode 100644 index 000000000000..0217dde3b36b --- /dev/null +++ b/arch/arm/boot/dts/imx53-tx53-x03x.dts | |||
| @@ -0,0 +1,315 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Lothar Waßmann <LW@KARO-electronics.de> | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | #include "imx53-tx53.dtsi" | ||
| 14 | #include <dt-bindings/input/input.h> | ||
| 15 | #include <dt-bindings/pwm/pwm.h> | ||
| 16 | |||
| 17 | / { | ||
| 18 | model = "Ka-Ro electronics TX53 module (LCD)"; | ||
| 19 | compatible = "karo,tx53", "fsl,imx53"; | ||
| 20 | |||
| 21 | aliases { | ||
| 22 | display = &display; | ||
| 23 | }; | ||
| 24 | |||
| 25 | soc { | ||
| 26 | display: display@di0 { | ||
| 27 | compatible = "fsl,imx-parallel-display"; | ||
| 28 | crtcs = <&ipu 0>; | ||
| 29 | interface-pix-fmt = "rgb24"; | ||
| 30 | pinctrl-names = "default"; | ||
| 31 | pinctrl-0 = <&pinctrl_rgb24_vga1>; | ||
| 32 | status = "okay"; | ||
| 33 | |||
| 34 | display-timings { | ||
| 35 | VGA { | ||
| 36 | clock-frequency = <25200000>; | ||
| 37 | hactive = <640>; | ||
| 38 | vactive = <480>; | ||
| 39 | hback-porch = <48>; | ||
| 40 | hsync-len = <96>; | ||
| 41 | hfront-porch = <16>; | ||
| 42 | vback-porch = <31>; | ||
| 43 | vsync-len = <2>; | ||
| 44 | vfront-porch = <12>; | ||
| 45 | hsync-active = <0>; | ||
| 46 | vsync-active = <0>; | ||
| 47 | de-active = <1>; | ||
| 48 | pixelclk-active = <0>; | ||
| 49 | }; | ||
| 50 | |||
| 51 | ETV570 { | ||
| 52 | clock-frequency = <25200000>; | ||
| 53 | hactive = <640>; | ||
| 54 | vactive = <480>; | ||
| 55 | hback-porch = <114>; | ||
| 56 | hsync-len = <30>; | ||
| 57 | hfront-porch = <16>; | ||
| 58 | vback-porch = <32>; | ||
| 59 | vsync-len = <3>; | ||
| 60 | vfront-porch = <10>; | ||
| 61 | hsync-active = <0>; | ||
| 62 | vsync-active = <0>; | ||
| 63 | de-active = <1>; | ||
| 64 | pixelclk-active = <0>; | ||
| 65 | }; | ||
| 66 | |||
| 67 | ET0350 { | ||
| 68 | clock-frequency = <6413760>; | ||
| 69 | hactive = <320>; | ||
| 70 | vactive = <240>; | ||
| 71 | hback-porch = <34>; | ||
| 72 | hsync-len = <34>; | ||
| 73 | hfront-porch = <20>; | ||
| 74 | vback-porch = <15>; | ||
| 75 | vsync-len = <3>; | ||
| 76 | vfront-porch = <4>; | ||
| 77 | hsync-active = <0>; | ||
| 78 | vsync-active = <0>; | ||
| 79 | de-active = <1>; | ||
| 80 | pixelclk-active = <0>; | ||
| 81 | }; | ||
| 82 | |||
| 83 | ET0430 { | ||
| 84 | clock-frequency = <9009000>; | ||
| 85 | hactive = <480>; | ||
| 86 | vactive = <272>; | ||
| 87 | hback-porch = <2>; | ||
| 88 | hsync-len = <41>; | ||
| 89 | hfront-porch = <2>; | ||
| 90 | vback-porch = <2>; | ||
| 91 | vsync-len = <10>; | ||
| 92 | vfront-porch = <2>; | ||
| 93 | hsync-active = <0>; | ||
| 94 | vsync-active = <0>; | ||
| 95 | de-active = <1>; | ||
| 96 | pixelclk-active = <1>; | ||
| 97 | }; | ||
| 98 | |||
| 99 | ET0500 { | ||
| 100 | clock-frequency = <33264000>; | ||
| 101 | hactive = <800>; | ||
| 102 | vactive = <480>; | ||
| 103 | hback-porch = <88>; | ||
| 104 | hsync-len = <128>; | ||
| 105 | hfront-porch = <40>; | ||
| 106 | vback-porch = <33>; | ||
| 107 | vsync-len = <2>; | ||
| 108 | vfront-porch = <10>; | ||
| 109 | hsync-active = <0>; | ||
| 110 | vsync-active = <0>; | ||
| 111 | de-active = <1>; | ||
| 112 | pixelclk-active = <0>; | ||
| 113 | }; | ||
| 114 | |||
| 115 | ET0700 { /* same as ET0500 */ | ||
| 116 | clock-frequency = <33264000>; | ||
| 117 | hactive = <800>; | ||
| 118 | vactive = <480>; | ||
| 119 | hback-porch = <88>; | ||
| 120 | hsync-len = <128>; | ||
| 121 | hfront-porch = <40>; | ||
| 122 | vback-porch = <33>; | ||
| 123 | vsync-len = <2>; | ||
| 124 | vfront-porch = <10>; | ||
| 125 | hsync-active = <0>; | ||
| 126 | vsync-active = <0>; | ||
| 127 | de-active = <1>; | ||
| 128 | pixelclk-active = <0>; | ||
| 129 | }; | ||
| 130 | |||
| 131 | ETQ570 { | ||
| 132 | clock-frequency = <6596040>; | ||
| 133 | hactive = <320>; | ||
| 134 | vactive = <240>; | ||
| 135 | hback-porch = <38>; | ||
| 136 | hsync-len = <30>; | ||
| 137 | hfront-porch = <30>; | ||
| 138 | vback-porch = <16>; | ||
| 139 | vsync-len = <3>; | ||
| 140 | vfront-porch = <4>; | ||
| 141 | hsync-active = <0>; | ||
| 142 | vsync-active = <0>; | ||
| 143 | de-active = <1>; | ||
| 144 | pixelclk-active = <0>; | ||
| 145 | }; | ||
| 146 | }; | ||
| 147 | }; | ||
| 148 | }; | ||
| 149 | |||
| 150 | backlight: backlight { | ||
| 151 | compatible = "pwm-backlight"; | ||
| 152 | pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; | ||
| 153 | power-supply = <®_3v3>; | ||
| 154 | brightness-levels = < | ||
| 155 | 0 1 2 3 4 5 6 7 8 9 | ||
| 156 | 10 11 12 13 14 15 16 17 18 19 | ||
| 157 | 20 21 22 23 24 25 26 27 28 29 | ||
| 158 | 30 31 32 33 34 35 36 37 38 39 | ||
| 159 | 40 41 42 43 44 45 46 47 48 49 | ||
| 160 | 50 51 52 53 54 55 56 57 58 59 | ||
| 161 | 60 61 62 63 64 65 66 67 68 69 | ||
| 162 | 70 71 72 73 74 75 76 77 78 79 | ||
| 163 | 80 81 82 83 84 85 86 87 88 89 | ||
| 164 | 90 91 92 93 94 95 96 97 98 99 | ||
| 165 | 100 | ||
| 166 | >; | ||
| 167 | default-brightness-level = <50>; | ||
| 168 | }; | ||
| 169 | |||
| 170 | regulators { | ||
| 171 | reg_lcd_pwr: regulator@5 { | ||
| 172 | compatible = "regulator-fixed"; | ||
| 173 | reg = <5>; | ||
| 174 | regulator-name = "LCD POWER"; | ||
| 175 | regulator-min-microvolt = <3300000>; | ||
| 176 | regulator-max-microvolt = <3300000>; | ||
| 177 | gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; | ||
| 178 | enable-active-high; | ||
| 179 | regulator-boot-on; | ||
| 180 | }; | ||
| 181 | |||
| 182 | reg_lcd_reset: regulator@6 { | ||
| 183 | compatible = "regulator-fixed"; | ||
| 184 | reg = <6>; | ||
| 185 | regulator-name = "LCD RESET"; | ||
| 186 | regulator-min-microvolt = <3300000>; | ||
| 187 | regulator-max-microvolt = <3300000>; | ||
| 188 | gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; | ||
| 189 | enable-active-high; | ||
| 190 | regulator-boot-on; | ||
| 191 | }; | ||
| 192 | }; | ||
| 193 | }; | ||
| 194 | |||
| 195 | &i2c3 { | ||
| 196 | pinctrl-names = "default"; | ||
| 197 | pinctrl-0 = <&pinctrl_i2c3>; | ||
| 198 | status = "okay"; | ||
| 199 | |||
| 200 | sgtl5000: codec@0a { | ||
| 201 | compatible = "fsl,sgtl5000"; | ||
| 202 | reg = <0x0a>; | ||
| 203 | VDDA-supply = <®_2v5>; | ||
| 204 | VDDIO-supply = <®_3v3>; | ||
| 205 | clocks = <&mclk>; | ||
| 206 | }; | ||
| 207 | |||
| 208 | polytouch: edt-ft5x06@38 { | ||
| 209 | compatible = "edt,edt-ft5x06"; | ||
| 210 | reg = <0x38>; | ||
| 211 | pinctrl-names = "default"; | ||
| 212 | pinctrl-0 = <&pinctrl_edt_ft5x06_1>; | ||
| 213 | interrupt-parent = <&gpio6>; | ||
| 214 | interrupts = <15 0>; | ||
| 215 | reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; | ||
| 216 | wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; | ||
| 217 | }; | ||
| 218 | |||
| 219 | touchscreen: tsc2007@48 { | ||
| 220 | compatible = "ti,tsc2007"; | ||
| 221 | reg = <0x48>; | ||
| 222 | pinctrl-names = "default"; | ||
| 223 | pinctrl-0 = <&pinctrl_tsc2007>; | ||
| 224 | interrupt-parent = <&gpio3>; | ||
| 225 | interrupts = <26 0>; | ||
| 226 | gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; | ||
| 227 | ti,x-plate-ohms = <660>; | ||
| 228 | linux,wakeup; | ||
| 229 | }; | ||
| 230 | }; | ||
| 231 | |||
| 232 | &iomuxc { | ||
| 233 | imx53-tx53-x03x { | ||
| 234 | pinctrl_edt_ft5x06_1: edt-ft5x06grp-1 { | ||
| 235 | fsl,pins = < | ||
| 236 | MX53_PAD_NANDF_CS2__GPIO6_15 0x1f0 /* Interrupt */ | ||
| 237 | MX53_PAD_EIM_A16__GPIO2_22 0x04 /* Reset */ | ||
| 238 | MX53_PAD_EIM_A17__GPIO2_21 0x04 /* Wake */ | ||
| 239 | >; | ||
| 240 | }; | ||
| 241 | |||
| 242 | pinctrl_kpp: kppgrp { | ||
| 243 | fsl,pins = < | ||
| 244 | MX53_PAD_GPIO_9__KPP_COL_6 0x1f4 | ||
| 245 | MX53_PAD_GPIO_4__KPP_COL_7 0x1f4 | ||
| 246 | MX53_PAD_KEY_COL2__KPP_COL_2 0x1f4 | ||
| 247 | MX53_PAD_KEY_COL3__KPP_COL_3 0x1f4 | ||
| 248 | MX53_PAD_GPIO_2__KPP_ROW_6 0x1f4 | ||
| 249 | MX53_PAD_GPIO_5__KPP_ROW_7 0x1f4 | ||
| 250 | MX53_PAD_KEY_ROW2__KPP_ROW_2 0x1f4 | ||
| 251 | MX53_PAD_KEY_ROW3__KPP_ROW_3 0x1f4 | ||
| 252 | >; | ||
| 253 | }; | ||
| 254 | |||
| 255 | pinctrl_rgb24_vga1: rgb24-vgagrp1 { | ||
| 256 | fsl,pins = < | ||
| 257 | MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 | ||
| 258 | MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 | ||
| 259 | MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 | ||
| 260 | MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 | ||
| 261 | MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 | ||
| 262 | MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 | ||
| 263 | MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 | ||
| 264 | MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 | ||
| 265 | MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 | ||
| 266 | MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 | ||
| 267 | MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 | ||
| 268 | MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 | ||
| 269 | MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 | ||
| 270 | MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 | ||
| 271 | MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 | ||
| 272 | MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 | ||
| 273 | MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 | ||
| 274 | MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 | ||
| 275 | MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 | ||
| 276 | MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 | ||
| 277 | MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 | ||
| 278 | MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 | ||
| 279 | MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 | ||
| 280 | MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 | ||
| 281 | MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 | ||
| 282 | MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 | ||
| 283 | MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 | ||
| 284 | MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 | ||
| 285 | >; | ||
| 286 | }; | ||
| 287 | |||
| 288 | pinctrl_tsc2007: tsc2007grp { | ||
| 289 | fsl,pins = < | ||
| 290 | MX53_PAD_EIM_D26__GPIO3_26 0x1f0 /* Interrupt */ | ||
| 291 | >; | ||
| 292 | }; | ||
| 293 | }; | ||
| 294 | }; | ||
| 295 | |||
| 296 | &kpp { | ||
| 297 | pinctrl-names = "default"; | ||
| 298 | pinctrl-0 = <&pinctrl_kpp>; | ||
| 299 | /* sample keymap */ | ||
| 300 | /* row/col 0,1 are mapped to KPP row/col 6,7 */ | ||
| 301 | linux,keymap = < | ||
| 302 | MATRIX_KEY(6, 6, KEY_POWER) | ||
| 303 | MATRIX_KEY(6, 7, KEY_KP0) | ||
| 304 | MATRIX_KEY(6, 2, KEY_KP1) | ||
| 305 | MATRIX_KEY(6, 3, KEY_KP2) | ||
| 306 | MATRIX_KEY(7, 6, KEY_KP3) | ||
| 307 | MATRIX_KEY(7, 7, KEY_KP4) | ||
| 308 | MATRIX_KEY(7, 2, KEY_KP5) | ||
| 309 | MATRIX_KEY(7, 3, KEY_KP6) | ||
| 310 | MATRIX_KEY(2, 6, KEY_KP7) | ||
| 311 | MATRIX_KEY(2, 7, KEY_KP8) | ||
| 312 | MATRIX_KEY(2, 2, KEY_KP9) | ||
| 313 | >; | ||
| 314 | status = "okay"; | ||
| 315 | }; | ||
diff --git a/arch/arm/boot/dts/imx53-tx53-x13x.dts b/arch/arm/boot/dts/imx53-tx53-x13x.dts new file mode 100644 index 000000000000..64804719f0f4 --- /dev/null +++ b/arch/arm/boot/dts/imx53-tx53-x13x.dts | |||
| @@ -0,0 +1,243 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Lothar Waßmann <LW@KARO-electronics.de> | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | #include "imx53-tx53.dtsi" | ||
| 14 | #include <dt-bindings/input/input.h> | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Ka-Ro electronics TX53 module (LVDS)"; | ||
| 18 | compatible = "karo,tx53", "fsl,imx53"; | ||
| 19 | |||
| 20 | aliases { | ||
| 21 | display = &lvds0; | ||
| 22 | lvds0 = &lvds0; | ||
| 23 | lvds1 = &lvds1; | ||
| 24 | }; | ||
| 25 | |||
| 26 | backlight0: backlight0 { | ||
| 27 | compatible = "pwm-backlight"; | ||
| 28 | pwms = <&pwm2 0 500000 0>; | ||
| 29 | power-supply = <®_3v3>; | ||
| 30 | brightness-levels = < | ||
| 31 | 0 1 2 3 4 5 6 7 8 9 | ||
| 32 | 10 11 12 13 14 15 16 17 18 19 | ||
| 33 | 20 21 22 23 24 25 26 27 28 29 | ||
| 34 | 30 31 32 33 34 35 36 37 38 39 | ||
| 35 | 40 41 42 43 44 45 46 47 48 49 | ||
| 36 | 50 51 52 53 54 55 56 57 58 59 | ||
| 37 | 60 61 62 63 64 65 66 67 68 69 | ||
| 38 | 70 71 72 73 74 75 76 77 78 79 | ||
| 39 | 80 81 82 83 84 85 86 87 88 89 | ||
| 40 | 90 91 92 93 94 95 96 97 98 99 | ||
| 41 | 100 | ||
| 42 | >; | ||
| 43 | default-brightness-level = <50>; | ||
| 44 | }; | ||
| 45 | |||
| 46 | backlight1: backlight1 { | ||
| 47 | compatible = "pwm-backlight"; | ||
| 48 | pwms = <&pwm1 0 500000 0>; | ||
| 49 | power-supply = <®_3v3>; | ||
| 50 | brightness-levels = < | ||
| 51 | 0 1 2 3 4 5 6 7 8 9 | ||
| 52 | 10 11 12 13 14 15 16 17 18 19 | ||
| 53 | 20 21 22 23 24 25 26 27 28 29 | ||
| 54 | 30 31 32 33 34 35 36 37 38 39 | ||
| 55 | 40 41 42 43 44 45 46 47 48 49 | ||
| 56 | 50 51 52 53 54 55 56 57 58 59 | ||
| 57 | 60 61 62 63 64 65 66 67 68 69 | ||
| 58 | 70 71 72 73 74 75 76 77 78 79 | ||
| 59 | 80 81 82 83 84 85 86 87 88 89 | ||
| 60 | 90 91 92 93 94 95 96 97 98 99 | ||
| 61 | 100 | ||
| 62 | >; | ||
| 63 | default-brightness-level = <50>; | ||
| 64 | }; | ||
| 65 | |||
| 66 | regulators { | ||
| 67 | reg_lcd_pwr0: regulator@5 { | ||
| 68 | compatible = "regulator-fixed"; | ||
| 69 | reg = <5>; | ||
| 70 | regulator-name = "LVDS0 POWER"; | ||
| 71 | regulator-min-microvolt = <3300000>; | ||
| 72 | regulator-max-microvolt = <3300000>; | ||
| 73 | gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; | ||
| 74 | enable-active-high; | ||
| 75 | regulator-boot-on; | ||
| 76 | }; | ||
| 77 | |||
| 78 | reg_lcd_pwr1: regulator@6 { | ||
| 79 | compatible = "regulator-fixed"; | ||
| 80 | reg = <6>; | ||
| 81 | regulator-name = "LVDS1 POWER"; | ||
| 82 | regulator-min-microvolt = <3300000>; | ||
| 83 | regulator-max-microvolt = <3300000>; | ||
| 84 | gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; | ||
| 85 | enable-active-high; | ||
| 86 | regulator-boot-on; | ||
| 87 | }; | ||
| 88 | }; | ||
| 89 | }; | ||
| 90 | |||
| 91 | &i2c2 { | ||
| 92 | pinctrl-names = "default"; | ||
| 93 | pinctrl-0 = <&pinctrl_i2c2>; | ||
| 94 | status = "okay"; | ||
| 95 | |||
| 96 | touchscreen2: eeti@04 { | ||
| 97 | compatible = "eeti,egalax_ts"; | ||
| 98 | reg = <0x04>; | ||
| 99 | pinctrl-names = "default"; | ||
| 100 | pinctrl-0 = <&pinctrl_eeti2>; | ||
| 101 | interrupt-parent = <&gpio3>; | ||
| 102 | interrupts = <23 0>; | ||
| 103 | wakeup-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; | ||
| 104 | linux,wakeup; | ||
| 105 | }; | ||
| 106 | }; | ||
| 107 | |||
| 108 | &i2c3 { | ||
| 109 | pinctrl-names = "default"; | ||
| 110 | pinctrl-0 = <&pinctrl_i2c3>; | ||
| 111 | status = "okay"; | ||
| 112 | |||
| 113 | sgtl5000: codec@0a { | ||
| 114 | compatible = "fsl,sgtl5000"; | ||
| 115 | reg = <0x0a>; | ||
| 116 | VDDA-supply = <®_2v5>; | ||
| 117 | VDDIO-supply = <®_3v3>; | ||
| 118 | clocks = <&mclk>; | ||
| 119 | }; | ||
| 120 | |||
| 121 | touchscreen1: eeti@04 { | ||
| 122 | compatible = "eeti,egalax_ts"; | ||
| 123 | reg = <0x04>; | ||
| 124 | pinctrl-names = "default"; | ||
| 125 | pinctrl-0 = <&pinctrl_eeti1>; | ||
| 126 | interrupt-parent = <&gpio3>; | ||
| 127 | interrupts = <22 0>; | ||
| 128 | wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; | ||
| 129 | linux,wakeup; | ||
| 130 | }; | ||
| 131 | }; | ||
| 132 | |||
| 133 | &iomuxc { | ||
| 134 | imx53-tx53-x13x { | ||
| 135 | pinctrl_i2c2: i2c2-grp1 { | ||
| 136 | fsl,pins = < | ||
| 137 | MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 | ||
| 138 | MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 | ||
| 139 | >; | ||
| 140 | }; | ||
| 141 | |||
| 142 | pinctrl_lvds0: lvds0grp { | ||
| 143 | fsl,pins = < | ||
| 144 | MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 | ||
| 145 | MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 | ||
| 146 | MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 | ||
| 147 | MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 | ||
| 148 | MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 | ||
| 149 | >; | ||
| 150 | }; | ||
| 151 | |||
| 152 | pinctrl_lvds1: lvds1grp { | ||
| 153 | fsl,pins = < | ||
| 154 | MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000 | ||
| 155 | MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000 | ||
| 156 | MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000 | ||
| 157 | MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000 | ||
| 158 | MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000 | ||
| 159 | >; | ||
| 160 | }; | ||
| 161 | |||
| 162 | pinctrl_pwm1: pwm1grp { | ||
| 163 | fsl,pins = <MX53_PAD_GPIO_9__PWM1_PWMO 0x04>; | ||
| 164 | }; | ||
| 165 | |||
| 166 | pinctrl_eeti1: eeti1grp { | ||
| 167 | fsl,pins = < | ||
| 168 | MX53_PAD_EIM_D22__GPIO3_22 0x1f0 /* Interrupt */ | ||
| 169 | >; | ||
| 170 | }; | ||
| 171 | |||
| 172 | pinctrl_eeti2: eeti2grp { | ||
| 173 | fsl,pins = < | ||
| 174 | MX53_PAD_EIM_D23__GPIO3_23 0x1f0 /* Interrupt */ | ||
| 175 | >; | ||
| 176 | }; | ||
| 177 | }; | ||
| 178 | }; | ||
| 179 | |||
| 180 | &ldb { | ||
| 181 | pinctrl-names = "default"; | ||
| 182 | pinctrl-0 = <&pinctrl_lvds0 &pinctrl_lvds1>; | ||
| 183 | status = "okay"; | ||
| 184 | |||
| 185 | lvds0: lvds-channel@0 { | ||
| 186 | fsl,data-mapping = "jeida"; | ||
| 187 | fsl,data-width = <24>; | ||
| 188 | status = "okay"; | ||
| 189 | |||
| 190 | display-timings { | ||
| 191 | native-mode = <&lvds_timing0>; | ||
| 192 | lvds_timing0: hsd100pxn1 { | ||
| 193 | clock-frequency = <65000000>; | ||
| 194 | hactive = <1024>; | ||
| 195 | vactive = <768>; | ||
| 196 | hback-porch = <220>; | ||
| 197 | hsync-len = <60>; | ||
| 198 | hfront-porch = <40>; | ||
| 199 | vback-porch = <21>; | ||
| 200 | vsync-len = <10>; | ||
| 201 | vfront-porch = <7>; | ||
| 202 | hsync-active = <0>; | ||
| 203 | vsync-active = <0>; | ||
| 204 | de-active = <1>; | ||
| 205 | pixelclk-active = <0>; | ||
| 206 | }; | ||
| 207 | }; | ||
| 208 | }; | ||
| 209 | |||
| 210 | lvds1: lvds-channel@1 { | ||
| 211 | fsl,data-mapping = "jeida"; | ||
| 212 | fsl,data-width = <24>; | ||
| 213 | status = "okay"; | ||
| 214 | |||
| 215 | display-timings { | ||
| 216 | native-mode = <&lvds_timing1>; | ||
| 217 | lvds_timing1: hsd100pxn1 { | ||
| 218 | clock-frequency = <65000000>; | ||
| 219 | hactive = <1024>; | ||
| 220 | vactive = <768>; | ||
| 221 | hback-porch = <220>; | ||
| 222 | hsync-len = <60>; | ||
| 223 | hfront-porch = <40>; | ||
| 224 | vback-porch = <21>; | ||
| 225 | vsync-len = <10>; | ||
| 226 | vfront-porch = <7>; | ||
| 227 | hsync-active = <0>; | ||
| 228 | vsync-active = <0>; | ||
| 229 | de-active = <1>; | ||
| 230 | pixelclk-active = <0>; | ||
| 231 | }; | ||
| 232 | }; | ||
| 233 | }; | ||
| 234 | }; | ||
| 235 | |||
| 236 | &pwm1 { | ||
| 237 | pinctrl-names = "default"; | ||
| 238 | pinctrl-0 = <&pinctrl_pwm1>; | ||
| 239 | }; | ||
| 240 | |||
| 241 | &sata { | ||
| 242 | status = "okay"; | ||
| 243 | }; | ||
diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi index f494766700a3..e348796ba689 100644 --- a/arch/arm/boot/dts/imx53-tx53.dtsi +++ b/arch/arm/boot/dts/imx53-tx53.dtsi | |||
| @@ -1,122 +1,550 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de> | 2 | * Copyright 2012 <LW@KARO-electronics.de> |
| 3 | * based on imx53-qsb.dts | ||
| 4 | * Copyright 2011 Freescale Semiconductor, Inc. | ||
| 5 | * Copyright 2011 Linaro Ltd. | ||
| 3 | * | 6 | * |
| 4 | * The code contained herein is licensed under the GNU General Public | 7 | * The code contained herein is licensed under the GNU General Public |
| 5 | * License. You may obtain a copy of the GNU General Public License | 8 | * License. You may obtain a copy of the GNU General Public License |
| 6 | * Version 2 or later at the following locations: | 9 | * Version 2 at the following locations: |
| 7 | * | 10 | * |
| 8 | * http://www.opensource.org/licenses/gpl-license.html | 11 | * http://www.opensource.org/licenses/gpl-license.html |
| 9 | * http://www.gnu.org/copyleft/gpl.html | 12 | * http://www.gnu.org/copyleft/gpl.html |
| 10 | */ | 13 | */ |
| 11 | 14 | ||
| 12 | /include/ "imx53.dtsi" | 15 | #include "imx53.dtsi" |
| 16 | #include <dt-bindings/gpio/gpio.h> | ||
| 13 | 17 | ||
| 14 | / { | 18 | / { |
| 15 | model = "Ka-Ro TX53"; | 19 | model = "Ka-Ro electronics TX53 module"; |
| 16 | compatible = "karo,tx53", "fsl,imx53"; | 20 | compatible = "karo,tx53", "fsl,imx53"; |
| 17 | 21 | ||
| 18 | memory { | 22 | aliases { |
| 19 | reg = <0x70000000 0x40000000>; /* Up to 1GiB */ | 23 | can0 = &can2; /* Make the can interface indices consistent with TX28/TX48 modules */ |
| 24 | can1 = &can1; | ||
| 25 | ipu = &ipu; | ||
| 26 | reg_can_xcvr = ®_can_xcvr; | ||
| 27 | usbh1 = &usbh1; | ||
| 28 | usbotg = &usbotg; | ||
| 29 | }; | ||
| 30 | |||
| 31 | clocks { | ||
| 32 | ckih1 { | ||
| 33 | clock-frequency = <0>; | ||
| 34 | }; | ||
| 35 | |||
| 36 | mclk: clock@0 { | ||
| 37 | compatible = "fixed-clock"; | ||
| 38 | reg = <0>; | ||
| 39 | #clock-cells = <0>; | ||
| 40 | clock-frequency = <27000000>; | ||
| 41 | }; | ||
| 42 | }; | ||
| 43 | |||
| 44 | gpio-keys { | ||
| 45 | compatible = "gpio-keys"; | ||
| 46 | pinctrl-names = "default"; | ||
| 47 | pinctrl-0 = <&pinctrl_gpio_key>; | ||
| 48 | |||
| 49 | power { | ||
| 50 | label = "Power Button"; | ||
| 51 | gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; | ||
| 52 | linux,code = <116>; /* KEY_POWER */ | ||
| 53 | gpio-key,wakeup; | ||
| 54 | }; | ||
| 55 | }; | ||
| 56 | |||
| 57 | leds { | ||
| 58 | compatible = "gpio-leds"; | ||
| 59 | pinctrl-names = "default"; | ||
| 60 | pinctrl-0 = <&pinctrl_stk5led>; | ||
| 61 | |||
| 62 | user { | ||
| 63 | label = "Heartbeat"; | ||
| 64 | gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; | ||
| 65 | linux,default-trigger = "heartbeat"; | ||
| 66 | }; | ||
| 20 | }; | 67 | }; |
| 21 | 68 | ||
| 22 | regulators { | 69 | regulators { |
| 23 | compatible = "simple-bus"; | 70 | compatible = "simple-bus"; |
| 71 | #address-cells = <1>; | ||
| 72 | #size-cells = <0>; | ||
| 24 | 73 | ||
| 25 | reg_3p3v: 3p3v { | 74 | reg_2v5: regulator@0 { |
| 26 | compatible = "regulator-fixed"; | 75 | compatible = "regulator-fixed"; |
| 27 | regulator-name = "3P3V"; | 76 | reg = <0>; |
| 77 | regulator-name = "2V5"; | ||
| 78 | regulator-min-microvolt = <2500000>; | ||
| 79 | regulator-max-microvolt = <2500000>; | ||
| 80 | }; | ||
| 81 | |||
| 82 | reg_3v3: regulator@1 { | ||
| 83 | compatible = "regulator-fixed"; | ||
| 84 | reg = <1>; | ||
| 85 | regulator-name = "3V3"; | ||
| 28 | regulator-min-microvolt = <3300000>; | 86 | regulator-min-microvolt = <3300000>; |
| 29 | regulator-max-microvolt = <3300000>; | 87 | regulator-max-microvolt = <3300000>; |
| 30 | regulator-always-on; | ||
| 31 | }; | 88 | }; |
| 89 | |||
| 90 | reg_can_xcvr: regulator@2 { | ||
| 91 | compatible = "regulator-fixed"; | ||
| 92 | reg = <2>; | ||
| 93 | regulator-name = "CAN XCVR"; | ||
| 94 | regulator-min-microvolt = <3300000>; | ||
| 95 | regulator-max-microvolt = <3300000>; | ||
| 96 | pinctrl-names = "default"; | ||
| 97 | pinctrl-0 = <&pinctrl_can_xcvr>; | ||
| 98 | gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; | ||
| 99 | }; | ||
| 100 | |||
| 101 | reg_usbh1_vbus: regulator@3 { | ||
| 102 | compatible = "regulator-fixed"; | ||
| 103 | reg = <3>; | ||
| 104 | regulator-name = "usbh1_vbus"; | ||
| 105 | regulator-min-microvolt = <5000000>; | ||
| 106 | regulator-max-microvolt = <5000000>; | ||
| 107 | pinctrl-names = "default"; | ||
| 108 | pinctrl-0 = <&pinctrl_usbh1_vbus>; | ||
| 109 | gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; | ||
| 110 | enable-active-high; | ||
| 111 | }; | ||
| 112 | |||
| 113 | reg_usbotg_vbus: regulator@4 { | ||
| 114 | compatible = "regulator-fixed"; | ||
| 115 | reg = <4>; | ||
| 116 | regulator-name = "usbotg_vbus"; | ||
| 117 | regulator-min-microvolt = <5000000>; | ||
| 118 | regulator-max-microvolt = <5000000>; | ||
| 119 | pinctrl-names = "default"; | ||
| 120 | pinctrl-0 = <&pinctrl_usbotg_vbus>; | ||
| 121 | gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; | ||
| 122 | enable-active-high; | ||
| 123 | }; | ||
| 124 | }; | ||
| 125 | |||
| 126 | sound { | ||
| 127 | compatible = "karo,tx53-audio-sgtl5000", "fsl,imx-audio-sgtl5000"; | ||
| 128 | model = "tx53-audio-sgtl5000"; | ||
| 129 | ssi-controller = <&ssi1>; | ||
| 130 | audio-codec = <&sgtl5000>; | ||
| 131 | audio-routing = | ||
| 132 | "MIC_IN", "Mic Jack", | ||
| 133 | "Mic Jack", "Mic Bias", | ||
| 134 | "Headphone Jack", "HP_OUT"; | ||
| 135 | /* '1' based port numbers according to datasheet names */ | ||
| 136 | mux-int-port = <1>; | ||
| 137 | mux-ext-port = <5>; | ||
| 32 | }; | 138 | }; |
| 33 | }; | 139 | }; |
| 34 | 140 | ||
| 141 | &audmux { | ||
| 142 | pinctrl-names = "default"; | ||
| 143 | pinctrl-0 = <&pinctrl_ssi1>; | ||
| 144 | status = "okay"; | ||
| 145 | }; | ||
| 146 | |||
| 35 | &can1 { | 147 | &can1 { |
| 36 | pinctrl-names = "default"; | 148 | pinctrl-names = "default"; |
| 37 | pinctrl-0 = <&pinctrl_can1_2>; | 149 | pinctrl-0 = <&pinctrl_can1>; |
| 38 | status = "disabled"; | 150 | xceiver-supply = <®_can_xcvr>; |
| 151 | status = "okay"; | ||
| 39 | }; | 152 | }; |
| 40 | 153 | ||
| 41 | &can2 { | 154 | &can2 { |
| 42 | pinctrl-names = "default"; | 155 | pinctrl-names = "default"; |
| 43 | pinctrl-0 = <&pinctrl_can2_1>; | 156 | pinctrl-0 = <&pinctrl_can2>; |
| 44 | status = "disabled"; | 157 | xceiver-supply = <®_can_xcvr>; |
| 158 | status = "okay"; | ||
| 45 | }; | 159 | }; |
| 46 | 160 | ||
| 47 | &ecspi1 { | 161 | &ecspi1 { |
| 48 | pinctrl-names = "default"; | 162 | pinctrl-names = "default"; |
| 49 | pinctrl-0 = <&pinctrl_ecspi1_2>; | 163 | pinctrl-0 = <&pinctrl_ecspi1>; |
| 50 | status = "disabled"; | 164 | fsl,spi-num-chipselects = <2>; |
| 165 | status = "okay"; | ||
| 166 | |||
| 167 | cs-gpios = < | ||
| 168 | &gpio2 30 GPIO_ACTIVE_HIGH | ||
| 169 | &gpio3 19 GPIO_ACTIVE_HIGH | ||
| 170 | >; | ||
| 171 | |||
| 172 | spidev0: spi@0 { | ||
| 173 | compatible = "spidev"; | ||
| 174 | reg = <0>; | ||
| 175 | spi-max-frequency = <54000000>; | ||
| 176 | }; | ||
| 177 | |||
| 178 | spidev1: spi@1 { | ||
| 179 | compatible = "spidev"; | ||
| 180 | reg = <1>; | ||
| 181 | spi-max-frequency = <54000000>; | ||
| 182 | }; | ||
| 51 | }; | 183 | }; |
| 52 | 184 | ||
| 53 | &esdhc1 { | 185 | &esdhc1 { |
| 186 | cd-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; | ||
| 187 | fsl,wp-controller; | ||
| 54 | pinctrl-names = "default"; | 188 | pinctrl-names = "default"; |
| 55 | pinctrl-0 = <&pinctrl_esdhc1_2>; | 189 | pinctrl-0 = <&pinctrl_esdhc1>; |
| 56 | status = "disabled"; | 190 | status = "okay"; |
| 57 | }; | 191 | }; |
| 58 | 192 | ||
| 59 | &esdhc2 { | 193 | &esdhc2 { |
| 194 | cd-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; | ||
| 195 | fsl,wp-controller; | ||
| 60 | pinctrl-names = "default"; | 196 | pinctrl-names = "default"; |
| 61 | pinctrl-0 = <&pinctrl_esdhc2_1>; | 197 | pinctrl-0 = <&pinctrl_esdhc2>; |
| 62 | status = "disabled"; | 198 | status = "okay"; |
| 63 | }; | 199 | }; |
| 64 | 200 | ||
| 65 | &fec { | 201 | &fec { |
| 66 | pinctrl-names = "default"; | 202 | pinctrl-names = "default"; |
| 67 | pinctrl-0 = <&pinctrl_fec_1>; | 203 | pinctrl-0 = <&pinctrl_fec>; |
| 68 | phy-mode = "rmii"; | 204 | phy-mode = "rmii"; |
| 69 | status = "disabled"; | 205 | phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>; |
| 206 | phy-handle = <&phy0>; | ||
| 207 | mac-address = [000000000000]; /* placeholder; will be overwritten by bootloader */ | ||
| 208 | status = "okay"; | ||
| 209 | |||
| 210 | phy0: ethernet-phy@0 { | ||
| 211 | interrupt-parent = <&gpio2>; | ||
| 212 | interrupts = <4>; | ||
| 213 | device_type = "ethernet-phy"; | ||
| 214 | }; | ||
| 70 | }; | 215 | }; |
| 71 | 216 | ||
| 72 | &i2c3 { | 217 | &i2c1 { |
| 73 | pinctrl-names = "default"; | 218 | pinctrl-names = "default"; |
| 74 | pinctrl-0 = <&pinctrl_i2c3_2>; | 219 | pinctrl-0 = <&pinctrl_i2c1>; |
| 75 | status = "disabled"; | 220 | clock-frequency = <400000>; |
| 221 | status = "okay"; | ||
| 222 | |||
| 223 | rtc1: ds1339@68 { | ||
| 224 | compatible = "dallas,ds1339"; | ||
| 225 | reg = <0x68>; | ||
| 226 | pinctrl-names = "default"; | ||
| 227 | pinctrl-0 = <&pinctrl_ds1339>; | ||
| 228 | interrupt-parent = <&gpio4>; | ||
| 229 | interrupts = <20 0>; | ||
| 230 | }; | ||
| 76 | }; | 231 | }; |
| 77 | 232 | ||
| 78 | &owire { | 233 | &iomuxc { |
| 79 | pinctrl-names = "default"; | 234 | pinctrl-names = "default"; |
| 80 | pinctrl-0 = <&pinctrl_owire_1>; | 235 | pinctrl-0 = <&pinctrl_hog>; |
| 81 | status = "disabled"; | 236 | |
| 237 | imx53-tx53 { | ||
| 238 | pinctrl_hog: hoggrp { | ||
| 239 | /* pins not in use by any device on the Starterkit board series */ | ||
| 240 | fsl,pins = < | ||
| 241 | /* CMOS Sensor Interface */ | ||
| 242 | MX53_PAD_CSI0_DAT12__GPIO5_30 0x1f4 | ||
| 243 | MX53_PAD_CSI0_DAT13__GPIO5_31 0x1f4 | ||
| 244 | MX53_PAD_CSI0_DAT14__GPIO6_0 0x1f4 | ||
| 245 | MX53_PAD_CSI0_DAT15__GPIO6_1 0x1f4 | ||
| 246 | MX53_PAD_CSI0_DAT16__GPIO6_2 0x1f4 | ||
| 247 | MX53_PAD_CSI0_DAT17__GPIO6_3 0x1f4 | ||
| 248 | MX53_PAD_CSI0_DAT18__GPIO6_4 0x1f4 | ||
| 249 | MX53_PAD_CSI0_DAT19__GPIO6_5 0x1f4 | ||
| 250 | MX53_PAD_CSI0_MCLK__GPIO5_19 0x1f4 | ||
| 251 | MX53_PAD_CSI0_VSYNC__GPIO5_21 0x1f4 | ||
| 252 | MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x1f4 | ||
| 253 | MX53_PAD_GPIO_0__GPIO1_0 0x1f4 | ||
| 254 | /* Module Specific Signal */ | ||
| 255 | /* MX53_PAD_NANDF_CS2__GPIO6_15 0x1f4 maybe used by EDT-FT5x06 */ | ||
| 256 | /* MX53_PAD_EIM_A16__GPIO2_22 0x1f4 maybe used by EDT-FT5x06 */ | ||
| 257 | MX53_PAD_EIM_D29__GPIO3_29 0x1f4 | ||
| 258 | MX53_PAD_EIM_EB3__GPIO2_31 0x1f4 | ||
| 259 | /* MX53_PAD_EIM_A17__GPIO2_21 0x1f4 maybe used by EDT-FT5x06 */ | ||
| 260 | /* MX53_PAD_EIM_A18__GPIO2_20 0x1f4 used by LED */ | ||
| 261 | MX53_PAD_EIM_A19__GPIO2_19 0x1f4 | ||
| 262 | MX53_PAD_EIM_A20__GPIO2_18 0x1f4 | ||
| 263 | MX53_PAD_EIM_A21__GPIO2_17 0x1f4 | ||
| 264 | MX53_PAD_EIM_A22__GPIO2_16 0x1f4 | ||
| 265 | MX53_PAD_EIM_A23__GPIO6_6 0x1f4 | ||
| 266 | MX53_PAD_EIM_A24__GPIO5_4 0x1f4 | ||
| 267 | MX53_PAD_CSI0_DAT8__GPIO5_26 0x1f4 | ||
| 268 | MX53_PAD_CSI0_DAT9__GPIO5_27 0x1f4 | ||
| 269 | MX53_PAD_CSI0_DAT10__GPIO5_28 0x1f4 | ||
| 270 | MX53_PAD_CSI0_DAT11__GPIO5_29 0x1f4 | ||
| 271 | /* MX53_PAD_EIM_D22__GPIO3_22 0x1f4 maybe used by EETI touchpanel driver */ | ||
| 272 | /* MX53_PAD_EIM_D23__GPIO3_23 0x1f4 maybe used by EETI touchpanel driver */ | ||
| 273 | MX53_PAD_GPIO_13__GPIO4_3 0x1f4 | ||
| 274 | MX53_PAD_EIM_CS0__GPIO2_23 0x1f4 | ||
| 275 | MX53_PAD_EIM_CS1__GPIO2_24 0x1f4 | ||
| 276 | MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x1f4 | ||
| 277 | MX53_PAD_EIM_WAIT__GPIO5_0 0x1f4 | ||
| 278 | MX53_PAD_EIM_EB0__GPIO2_28 0x1f4 | ||
| 279 | MX53_PAD_EIM_EB1__GPIO2_29 0x1f4 | ||
| 280 | MX53_PAD_EIM_OE__GPIO2_25 0x1f4 | ||
| 281 | MX53_PAD_EIM_LBA__GPIO2_27 0x1f4 | ||
| 282 | MX53_PAD_EIM_RW__GPIO2_26 0x1f4 | ||
| 283 | MX53_PAD_EIM_DA8__GPIO3_8 0x1f4 | ||
| 284 | MX53_PAD_EIM_DA9__GPIO3_9 0x1f4 | ||
| 285 | MX53_PAD_EIM_DA10__GPIO3_10 0x1f4 | ||
| 286 | MX53_PAD_EIM_DA11__GPIO3_11 0x1f4 | ||
| 287 | MX53_PAD_EIM_DA12__GPIO3_12 0x1f4 | ||
| 288 | MX53_PAD_EIM_DA13__GPIO3_13 0x1f4 | ||
| 289 | MX53_PAD_EIM_DA14__GPIO3_14 0x1f4 | ||
| 290 | MX53_PAD_EIM_DA15__GPIO3_15 0x1f4 | ||
| 291 | >; | ||
| 292 | }; | ||
| 293 | |||
| 294 | pinctrl_can1: can1grp { | ||
| 295 | fsl,pins = < | ||
| 296 | MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000 | ||
| 297 | MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000 | ||
| 298 | >; | ||
| 299 | }; | ||
| 300 | |||
| 301 | pinctrl_can2: can2grp { | ||
| 302 | fsl,pins = < | ||
| 303 | MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 | ||
| 304 | MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 | ||
| 305 | >; | ||
| 306 | }; | ||
| 307 | |||
| 308 | pinctrl_can_xcvr: can-xcvrgrp { | ||
| 309 | fsl,pins = <MX53_PAD_DISP0_DAT0__GPIO4_21 0xe0>; /* Flexcan XCVR enable */ | ||
| 310 | }; | ||
| 311 | |||
| 312 | pinctrl_ds1339: ds1339grp { | ||
| 313 | fsl,pins = <MX53_PAD_DI0_PIN4__GPIO4_20 0xe0>; | ||
| 314 | }; | ||
| 315 | |||
| 316 | pinctrl_ecspi1: ecspi1grp { | ||
| 317 | fsl,pins = < | ||
| 318 | MX53_PAD_GPIO_19__ECSPI1_RDY 0x80000000 | ||
| 319 | MX53_PAD_EIM_EB2__ECSPI1_SS0 0x80000000 | ||
| 320 | MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 | ||
| 321 | MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 | ||
| 322 | MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 | ||
| 323 | MX53_PAD_EIM_D19__ECSPI1_SS1 0x80000000 | ||
| 324 | >; | ||
| 325 | }; | ||
| 326 | |||
| 327 | pinctrl_esdhc1: esdhc1grp { | ||
| 328 | fsl,pins = < | ||
| 329 | MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 | ||
| 330 | MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 | ||
| 331 | MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 | ||
| 332 | MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 | ||
| 333 | MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 | ||
| 334 | MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 | ||
| 335 | MX53_PAD_EIM_D24__GPIO3_24 0x1f0 | ||
| 336 | >; | ||
| 337 | }; | ||
| 338 | |||
| 339 | pinctrl_esdhc2: esdhc2grp { | ||
| 340 | fsl,pins = < | ||
| 341 | MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 | ||
| 342 | MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 | ||
| 343 | MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 | ||
| 344 | MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 | ||
| 345 | MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 | ||
| 346 | MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 | ||
| 347 | MX53_PAD_EIM_D25__GPIO3_25 0x1f0 | ||
| 348 | >; | ||
| 349 | }; | ||
| 350 | |||
| 351 | pinctrl_fec: fecgrp { | ||
| 352 | fsl,pins = < | ||
| 353 | MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 | ||
| 354 | MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 | ||
| 355 | MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 | ||
| 356 | MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 | ||
| 357 | MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 | ||
| 358 | MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 | ||
| 359 | MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 | ||
| 360 | MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 | ||
| 361 | MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 | ||
| 362 | MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 | ||
| 363 | >; | ||
| 364 | }; | ||
| 365 | |||
| 366 | pinctrl_gpio_key: gpio-keygrp { | ||
| 367 | fsl,pins = <MX53_PAD_EIM_A25__GPIO5_2 0x1f4>; | ||
| 368 | }; | ||
| 369 | |||
| 370 | pinctrl_i2c1: i2c1grp { | ||
| 371 | fsl,pins = < | ||
| 372 | MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000 | ||
| 373 | MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000 | ||
| 374 | >; | ||
| 375 | }; | ||
| 376 | |||
| 377 | pinctrl_i2c3: i2c3grp { | ||
| 378 | fsl,pins = < | ||
| 379 | MX53_PAD_GPIO_3__I2C3_SCL 0xc0000000 | ||
| 380 | MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 | ||
| 381 | >; | ||
| 382 | }; | ||
| 383 | |||
| 384 | pinctrl_nand: nandgrp { | ||
| 385 | fsl,pins = < | ||
| 386 | MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 | ||
| 387 | MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 | ||
| 388 | MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 | ||
| 389 | MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 | ||
| 390 | MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 | ||
| 391 | MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 | ||
| 392 | MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 | ||
| 393 | MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0xa4 | ||
| 394 | MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0xa4 | ||
| 395 | MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0xa4 | ||
| 396 | MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0xa4 | ||
| 397 | MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0xa4 | ||
| 398 | MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0xa4 | ||
| 399 | MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0xa4 | ||
| 400 | MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0xa4 | ||
| 401 | >; | ||
| 402 | }; | ||
| 403 | |||
| 404 | pinctrl_pwm2: pwm2grp { | ||
| 405 | fsl,pins = < | ||
| 406 | MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 | ||
| 407 | >; | ||
| 408 | }; | ||
| 409 | |||
| 410 | pinctrl_ssi1: ssi1grp { | ||
| 411 | fsl,pins = < | ||
| 412 | MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 | ||
| 413 | MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 | ||
| 414 | MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 | ||
| 415 | MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 | ||
| 416 | >; | ||
| 417 | }; | ||
| 418 | |||
| 419 | pinctrl_ssi2: ssi2grp { | ||
| 420 | fsl,pins = < | ||
| 421 | MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x80000000 | ||
| 422 | MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x80000000 | ||
| 423 | MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x80000000 | ||
| 424 | MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x80000000 | ||
| 425 | MX53_PAD_EIM_D27__GPIO3_27 0x1f0 | ||
| 426 | >; | ||
| 427 | }; | ||
| 428 | |||
| 429 | pinctrl_stk5led: stk5ledgrp { | ||
| 430 | fsl,pins = <MX53_PAD_EIM_A18__GPIO2_20 0xc0>; | ||
| 431 | }; | ||
| 432 | |||
| 433 | pinctrl_uart1: uart1grp { | ||
| 434 | fsl,pins = < | ||
| 435 | MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 | ||
| 436 | MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 | ||
| 437 | MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5 | ||
| 438 | MX53_PAD_PATA_IORDY__UART1_RTS 0x1c5 | ||
| 439 | >; | ||
| 440 | }; | ||
| 441 | |||
| 442 | pinctrl_uart2: uart2grp { | ||
| 443 | fsl,pins = < | ||
| 444 | MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5 | ||
| 445 | MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5 | ||
| 446 | MX53_PAD_PATA_DIOR__UART2_RTS 0x1c5 | ||
| 447 | MX53_PAD_PATA_INTRQ__UART2_CTS 0x1c5 | ||
| 448 | >; | ||
| 449 | }; | ||
| 450 | |||
| 451 | pinctrl_uart3: uart3grp { | ||
| 452 | fsl,pins = < | ||
| 453 | MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 | ||
| 454 | MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 | ||
| 455 | MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 | ||
| 456 | MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 | ||
| 457 | >; | ||
| 458 | }; | ||
| 459 | |||
| 460 | pinctrl_usbh1: usbh1grp { | ||
| 461 | fsl,pins = < | ||
| 462 | MX53_PAD_EIM_D30__GPIO3_30 0x100 /* OC */ | ||
| 463 | >; | ||
| 464 | }; | ||
| 465 | |||
| 466 | pinctrl_usbh1_vbus: usbh1-vbusgrp { | ||
| 467 | fsl,pins = < | ||
| 468 | MX53_PAD_EIM_D31__GPIO3_31 0xe0 /* VBUS ENABLE */ | ||
| 469 | >; | ||
| 470 | }; | ||
| 471 | |||
| 472 | pinctrl_usbotg_vbus: usbotg-vbusgrp { | ||
| 473 | fsl,pins = < | ||
| 474 | MX53_PAD_GPIO_7__GPIO1_7 0xe0 /* VBUS ENABLE */ | ||
| 475 | MX53_PAD_GPIO_8__GPIO1_8 0x100 /* OC */ | ||
| 476 | >; | ||
| 477 | }; | ||
| 478 | }; | ||
| 479 | }; | ||
| 480 | |||
| 481 | &ipu { | ||
| 482 | status = "okay"; | ||
| 483 | }; | ||
| 484 | |||
| 485 | &nfc { | ||
| 486 | pinctrl-names = "default"; | ||
| 487 | pinctrl-0 = <&pinctrl_nand>; | ||
| 488 | nand-bus-width = <8>; | ||
| 489 | nand-ecc-mode = "hw"; | ||
| 490 | nand-on-flash-bbt; | ||
| 491 | status = "okay"; | ||
| 82 | }; | 492 | }; |
| 83 | 493 | ||
| 84 | &pwm2 { | 494 | &pwm2 { |
| 85 | pinctrl-names = "default"; | 495 | pinctrl-names = "default"; |
| 86 | pinctrl-0 = <&pinctrl_pwm2_1>; | 496 | pinctrl-0 = <&pinctrl_pwm2>; |
| 87 | status = "disabled"; | 497 | #pwm-cells = <3>; |
| 498 | }; | ||
| 499 | |||
| 500 | &sdma { | ||
| 501 | fsl,sdma-ram-script-name = "sdma-imx53.bin"; | ||
| 88 | }; | 502 | }; |
| 89 | 503 | ||
| 90 | &ssi1 { | 504 | &ssi1 { |
| 91 | pinctrl-names = "default"; | 505 | fsl,mode = "i2s-slave"; |
| 92 | pinctrl-0 = <&pinctrl_audmux_1>; | 506 | codec-handle = <&sgtl5000>; |
| 93 | status = "disabled"; | 507 | status = "okay"; |
| 94 | }; | 508 | }; |
| 95 | 509 | ||
| 96 | &ssi2 { | 510 | &ssi2 { |
| 97 | pinctrl-names = "default"; | ||
| 98 | pinctrl-0 = <&pinctrl_audmux_2>; | ||
| 99 | status = "disabled"; | 511 | status = "disabled"; |
| 100 | }; | 512 | }; |
| 101 | 513 | ||
| 102 | &uart1 { | 514 | &uart1 { |
| 103 | pinctrl-names = "default"; | 515 | pinctrl-names = "default"; |
| 104 | pinctrl-0 = <&pinctrl_uart1_2>, | 516 | pinctrl-0 = <&pinctrl_uart1>; |
| 105 | <&pinctrl_uart1_3>; | ||
| 106 | fsl,uart-has-rtscts; | 517 | fsl,uart-has-rtscts; |
| 107 | status = "disabled"; | 518 | status = "okay"; |
| 108 | }; | 519 | }; |
| 109 | 520 | ||
| 110 | &uart2 { | 521 | &uart2 { |
| 111 | pinctrl-names = "default"; | 522 | pinctrl-names = "default"; |
| 112 | pinctrl-0 = <&pinctrl_uart2_2>; | 523 | pinctrl-0 = <&pinctrl_uart2>; |
| 113 | fsl,uart-has-rtscts; | 524 | fsl,uart-has-rtscts; |
| 114 | status = "disabled"; | 525 | status = "okay"; |
| 115 | }; | 526 | }; |
| 116 | 527 | ||
| 117 | &uart3 { | 528 | &uart3 { |
| 118 | pinctrl-names = "default"; | 529 | pinctrl-names = "default"; |
| 119 | pinctrl-0 = <&pinctrl_uart3_1>; | 530 | pinctrl-0 = <&pinctrl_uart3>; |
| 120 | fsl,uart-has-rtscts; | 531 | fsl,uart-has-rtscts; |
| 121 | status = "disabled"; | 532 | status = "okay"; |
| 533 | }; | ||
| 534 | |||
| 535 | &usbh1 { | ||
| 536 | pinctrl-names = "default"; | ||
| 537 | pinctrl-0 = <&pinctrl_usbh1>; | ||
| 538 | phy_type = "utmi"; | ||
| 539 | disable-over-current; | ||
| 540 | vbus-supply = <®_usbh1_vbus>; | ||
| 541 | status = "okay"; | ||
| 542 | }; | ||
| 543 | |||
| 544 | &usbotg { | ||
| 545 | phy_type = "utmi"; | ||
| 546 | dr_mode = "peripheral"; | ||
| 547 | disable-over-current; | ||
| 548 | vbus-supply = <®_usbotg_vbus>; | ||
| 549 | status = "okay"; | ||
| 122 | }; | 550 | }; |
diff --git a/arch/arm/boot/dts/imx53-voipac-bsb.dts b/arch/arm/boot/dts/imx53-voipac-bsb.dts new file mode 100644 index 000000000000..7f6711a48615 --- /dev/null +++ b/arch/arm/boot/dts/imx53-voipac-bsb.dts | |||
| @@ -0,0 +1,159 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Rostislav Lisovy <lisovy@gmail.com>, PiKRON s.r.o. | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | #include "imx53-voipac-dmm-668.dtsi" | ||
| 14 | |||
| 15 | / { | ||
| 16 | sound { | ||
| 17 | compatible = "fsl,imx53-voipac-sgtl5000", | ||
| 18 | "fsl,imx-audio-sgtl5000"; | ||
| 19 | model = "imx53-voipac-sgtl5000"; | ||
| 20 | ssi-controller = <&ssi2>; | ||
| 21 | audio-codec = <&sgtl5000>; | ||
| 22 | audio-routing = | ||
| 23 | "Headphone Jack", "HP_OUT"; | ||
| 24 | mux-int-port = <2>; | ||
| 25 | mux-ext-port = <5>; | ||
| 26 | }; | ||
| 27 | |||
| 28 | leds { | ||
| 29 | compatible = "gpio-leds"; | ||
| 30 | pinctrl-names = "default"; | ||
| 31 | pinctrl-0 = <&led_pin_gpio>; | ||
| 32 | |||
| 33 | led1 { | ||
| 34 | label = "led-red"; | ||
| 35 | gpios = <&gpio3 29 0>; | ||
| 36 | default-state = "off"; | ||
| 37 | }; | ||
| 38 | |||
| 39 | led2 { | ||
| 40 | label = "led-orange"; | ||
| 41 | gpios = <&gpio2 31 0>; | ||
| 42 | default-state = "off"; | ||
| 43 | }; | ||
| 44 | }; | ||
| 45 | }; | ||
| 46 | |||
| 47 | &iomuxc { | ||
| 48 | pinctrl-names = "default"; | ||
| 49 | pinctrl-0 = <&pinctrl_hog>; | ||
| 50 | |||
| 51 | imx53-voipac { | ||
| 52 | pinctrl_hog: hoggrp { | ||
| 53 | fsl,pins = < | ||
| 54 | /* SD2_CD */ | ||
| 55 | MX53_PAD_EIM_D25__GPIO3_25 0x80000000 | ||
| 56 | /* SD2_WP */ | ||
| 57 | MX53_PAD_EIM_A19__GPIO2_19 0x80000000 | ||
| 58 | >; | ||
| 59 | }; | ||
| 60 | |||
| 61 | led_pin_gpio: led_gpio { | ||
| 62 | fsl,pins = < | ||
| 63 | MX53_PAD_EIM_D29__GPIO3_29 0x80000000 | ||
| 64 | MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 | ||
| 65 | >; | ||
| 66 | }; | ||
| 67 | |||
| 68 | /* Keyboard controller */ | ||
| 69 | pinctrl_kpp_1: kppgrp-1 { | ||
| 70 | fsl,pins = < | ||
| 71 | MX53_PAD_GPIO_9__KPP_COL_6 0xe8 | ||
| 72 | MX53_PAD_GPIO_4__KPP_COL_7 0xe8 | ||
| 73 | MX53_PAD_KEY_COL2__KPP_COL_2 0xe8 | ||
| 74 | MX53_PAD_KEY_COL3__KPP_COL_3 0xe8 | ||
| 75 | MX53_PAD_KEY_COL4__KPP_COL_4 0xe8 | ||
| 76 | MX53_PAD_GPIO_2__KPP_ROW_6 0xe0 | ||
| 77 | MX53_PAD_GPIO_5__KPP_ROW_7 0xe0 | ||
| 78 | MX53_PAD_KEY_ROW2__KPP_ROW_2 0xe0 | ||
| 79 | MX53_PAD_KEY_ROW3__KPP_ROW_3 0xe0 | ||
| 80 | MX53_PAD_KEY_ROW4__KPP_ROW_4 0xe0 | ||
| 81 | >; | ||
| 82 | }; | ||
| 83 | |||
| 84 | pinctrl_audmux: audmuxgrp { | ||
| 85 | fsl,pins = < | ||
| 86 | MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 | ||
| 87 | MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 | ||
| 88 | MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 | ||
| 89 | MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 | ||
| 90 | >; | ||
| 91 | }; | ||
| 92 | |||
| 93 | pinctrl_esdhc2: esdhc2grp { | ||
| 94 | fsl,pins = < | ||
| 95 | MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 | ||
| 96 | MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 | ||
| 97 | MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 | ||
| 98 | MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 | ||
| 99 | MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 | ||
| 100 | MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 | ||
| 101 | >; | ||
| 102 | }; | ||
| 103 | |||
| 104 | pinctrl_i2c3: i2c3grp { | ||
| 105 | fsl,pins = < | ||
| 106 | MX53_PAD_GPIO_3__I2C3_SCL 0xc0000000 | ||
| 107 | MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 | ||
| 108 | >; | ||
| 109 | }; | ||
| 110 | }; | ||
| 111 | }; | ||
| 112 | |||
| 113 | &audmux { | ||
| 114 | pinctrl-names = "default"; | ||
| 115 | pinctrl-0 = <&pinctrl_audmux>; /* SSI1 */ | ||
| 116 | status = "okay"; | ||
| 117 | }; | ||
| 118 | |||
| 119 | &esdhc2 { | ||
| 120 | pinctrl-names = "default"; | ||
| 121 | pinctrl-0 = <&pinctrl_esdhc2>; | ||
| 122 | cd-gpios = <&gpio3 25 0>; | ||
| 123 | wp-gpios = <&gpio2 19 0>; | ||
| 124 | vmmc-supply = <®_3p3v>; | ||
| 125 | status = "okay"; | ||
| 126 | }; | ||
| 127 | |||
| 128 | &i2c3 { | ||
| 129 | pinctrl-names = "default"; | ||
| 130 | pinctrl-0 = <&pinctrl_i2c3>; | ||
| 131 | status = "okay"; | ||
| 132 | |||
| 133 | sgtl5000: codec@0a { | ||
| 134 | compatible = "fsl,sgtl5000"; | ||
| 135 | reg = <0x0a>; | ||
| 136 | VDDA-supply = <®_3p3v>; | ||
| 137 | VDDIO-supply = <®_3p3v>; | ||
| 138 | clocks = <&clks 150>; | ||
| 139 | }; | ||
| 140 | }; | ||
| 141 | |||
| 142 | &kpp { | ||
| 143 | pinctrl-names = "default"; | ||
| 144 | pinctrl-0 = <&pinctrl_kpp_1>; | ||
| 145 | linux,keymap = < | ||
| 146 | 0x0203003b /* KEY_F1 */ | ||
| 147 | 0x0603003c /* KEY_F2 */ | ||
| 148 | 0x0207003d /* KEY_F3 */ | ||
| 149 | 0x0607003e /* KEY_F4 */ | ||
| 150 | >; | ||
| 151 | keypad,num-rows = <8>; | ||
| 152 | keypad,num-columns = <1>; | ||
| 153 | status = "okay"; | ||
| 154 | }; | ||
| 155 | |||
| 156 | &ssi2 { | ||
| 157 | fsl,mode = "i2s-slave"; | ||
| 158 | status = "okay"; | ||
| 159 | }; | ||
diff --git a/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi b/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi new file mode 100644 index 000000000000..ba689fbd0e41 --- /dev/null +++ b/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi | |||
| @@ -0,0 +1,277 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Rostislav Lisovy <lisovy@gmail.com>, PiKRON s.r.o. | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include "imx53.dtsi" | ||
| 13 | |||
| 14 | / { | ||
| 15 | model = "Voipac i.MX53 X53-DMM-668"; | ||
| 16 | compatible = "voipac,imx53-dmm-668", "fsl,imx53"; | ||
| 17 | |||
| 18 | memory@70000000 { | ||
| 19 | device_type = "memory"; | ||
| 20 | reg = <0x70000000 0x20000000>; | ||
| 21 | }; | ||
| 22 | |||
| 23 | memory@b0000000 { | ||
| 24 | device_type = "memory"; | ||
| 25 | reg = <0xb0000000 0x20000000>; | ||
| 26 | }; | ||
| 27 | |||
| 28 | regulators { | ||
| 29 | compatible = "simple-bus"; | ||
| 30 | #address-cells = <1>; | ||
| 31 | #size-cells = <0>; | ||
| 32 | |||
| 33 | reg_3p3v: regulator@0 { | ||
| 34 | compatible = "regulator-fixed"; | ||
| 35 | reg = <0>; | ||
| 36 | regulator-name = "3P3V"; | ||
| 37 | regulator-min-microvolt = <3300000>; | ||
| 38 | regulator-max-microvolt = <3300000>; | ||
| 39 | regulator-always-on; | ||
| 40 | }; | ||
| 41 | |||
| 42 | reg_usb_vbus: regulator@1 { | ||
| 43 | compatible = "regulator-fixed"; | ||
| 44 | reg = <1>; | ||
| 45 | regulator-name = "usb_vbus"; | ||
| 46 | regulator-min-microvolt = <5000000>; | ||
| 47 | regulator-max-microvolt = <5000000>; | ||
| 48 | gpio = <&gpio3 31 0>; /* PEN */ | ||
| 49 | enable-active-high; | ||
| 50 | }; | ||
| 51 | }; | ||
| 52 | }; | ||
| 53 | |||
| 54 | &iomuxc { | ||
| 55 | pinctrl-names = "default"; | ||
| 56 | pinctrl-0 = <&pinctrl_hog>; | ||
| 57 | |||
| 58 | imx53-voipac { | ||
| 59 | pinctrl_hog: hoggrp { | ||
| 60 | fsl,pins = < | ||
| 61 | /* Make DA9053 regulator functional */ | ||
| 62 | MX53_PAD_GPIO_16__GPIO7_11 0x80000000 | ||
| 63 | /* FEC Power enable */ | ||
| 64 | MX53_PAD_GPIO_11__GPIO4_1 0x80000000 | ||
| 65 | /* FEC RST */ | ||
| 66 | MX53_PAD_GPIO_12__GPIO4_2 0x80000000 | ||
| 67 | >; | ||
| 68 | }; | ||
| 69 | |||
| 70 | pinctrl_ecspi1: ecspi1grp { | ||
| 71 | fsl,pins = < | ||
| 72 | MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 | ||
| 73 | MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 | ||
| 74 | MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 | ||
| 75 | >; | ||
| 76 | }; | ||
| 77 | |||
| 78 | pinctrl_fec: fecgrp { | ||
| 79 | fsl,pins = < | ||
| 80 | MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 | ||
| 81 | MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 | ||
| 82 | MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 | ||
| 83 | MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 | ||
| 84 | MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 | ||
| 85 | MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 | ||
| 86 | MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 | ||
| 87 | MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 | ||
| 88 | MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 | ||
| 89 | MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 | ||
| 90 | >; | ||
| 91 | }; | ||
| 92 | |||
| 93 | pinctrl_i2c1: i2c1grp { | ||
| 94 | fsl,pins = < | ||
| 95 | MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000 | ||
| 96 | MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000 | ||
| 97 | >; | ||
| 98 | }; | ||
| 99 | |||
| 100 | pinctrl_uart1: uart1grp { | ||
| 101 | fsl,pins = < | ||
| 102 | MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 | ||
| 103 | MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 | ||
| 104 | >; | ||
| 105 | }; | ||
| 106 | |||
| 107 | pinctrl_nand: nandgrp { | ||
| 108 | fsl,pins = < | ||
| 109 | MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 | ||
| 110 | MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 | ||
| 111 | MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 | ||
| 112 | MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 | ||
| 113 | MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 | ||
| 114 | MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 | ||
| 115 | MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 | ||
| 116 | MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 | ||
| 117 | MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 | ||
| 118 | MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 | ||
| 119 | MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 | ||
| 120 | MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 | ||
| 121 | MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 | ||
| 122 | MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 | ||
| 123 | MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 | ||
| 124 | >; | ||
| 125 | }; | ||
| 126 | }; | ||
| 127 | }; | ||
| 128 | |||
| 129 | &ecspi1 { | ||
| 130 | pinctrl-names = "default"; | ||
| 131 | pinctrl-0 = <&pinctrl_ecspi1>; | ||
| 132 | fsl,spi-num-chipselects = <4>; | ||
| 133 | cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>, <&gpio2 16 0>, <&gpio2 17 0>; | ||
| 134 | status = "okay"; | ||
| 135 | }; | ||
| 136 | |||
| 137 | &fec { | ||
| 138 | pinctrl-names = "default"; | ||
| 139 | pinctrl-0 = <&pinctrl_fec>; | ||
| 140 | phy-mode = "rmii"; | ||
| 141 | phy-reset-gpios = <&gpio4 2 0>; | ||
| 142 | status = "okay"; | ||
| 143 | }; | ||
| 144 | |||
| 145 | &i2c1 { | ||
| 146 | pinctrl-names = "default"; | ||
| 147 | pinctrl-0 = <&pinctrl_i2c1>; | ||
| 148 | status = "okay"; | ||
| 149 | |||
| 150 | pmic: dialog@48 { | ||
| 151 | compatible = "dlg,da9053-aa", "dlg,da9052"; | ||
| 152 | reg = <0x48>; | ||
| 153 | interrupt-parent = <&gpio7>; | ||
| 154 | interrupts = <11 0x8>; /* low-level active IRQ at GPIO7_11 */ | ||
| 155 | |||
| 156 | regulators { | ||
| 157 | buck1_reg: buck1 { | ||
| 158 | regulator-name = "BUCKCORE"; | ||
| 159 | regulator-min-microvolt = <1200000>; | ||
| 160 | regulator-max-microvolt = <1400000>; | ||
| 161 | regulator-always-on; | ||
| 162 | }; | ||
| 163 | |||
| 164 | buck2_reg: buck2 { | ||
| 165 | regulator-name = "BUCKPRO"; | ||
| 166 | regulator-min-microvolt = <900000>; | ||
| 167 | regulator-max-microvolt = <1350000>; | ||
| 168 | regulator-always-on; | ||
| 169 | }; | ||
| 170 | |||
| 171 | buck3_reg: buck3 { | ||
| 172 | regulator-name = "BUCKMEM"; | ||
| 173 | regulator-min-microvolt = <1420000>; | ||
| 174 | regulator-max-microvolt = <1580000>; | ||
| 175 | regulator-always-on; | ||
| 176 | }; | ||
| 177 | |||
| 178 | buck4_reg: buck4 { | ||
| 179 | regulator-name = "BUCKPERI"; | ||
| 180 | regulator-min-microvolt = <2370000>; | ||
| 181 | regulator-max-microvolt = <2630000>; | ||
| 182 | regulator-always-on; | ||
| 183 | }; | ||
| 184 | |||
| 185 | ldo1_reg: ldo1 { | ||
| 186 | regulator-name = "ldo1_1v3"; | ||
| 187 | regulator-min-microvolt = <1250000>; | ||
| 188 | regulator-max-microvolt = <1350000>; | ||
| 189 | regulator-boot-on; | ||
| 190 | regulator-always-on; | ||
| 191 | }; | ||
| 192 | |||
| 193 | ldo2_reg: ldo2 { | ||
| 194 | regulator-name = "ldo2_1v3"; | ||
| 195 | regulator-min-microvolt = <1250000>; | ||
| 196 | regulator-max-microvolt = <1350000>; | ||
| 197 | regulator-always-on; | ||
| 198 | }; | ||
| 199 | |||
| 200 | ldo3_reg: ldo3 { | ||
| 201 | regulator-name = "ldo3_3v3"; | ||
| 202 | regulator-min-microvolt = <3250000>; | ||
| 203 | regulator-max-microvolt = <3350000>; | ||
| 204 | regulator-always-on; | ||
| 205 | }; | ||
| 206 | |||
| 207 | ldo4_reg: ldo4 { | ||
| 208 | regulator-name = "ldo4_2v775"; | ||
| 209 | regulator-min-microvolt = <2770000>; | ||
| 210 | regulator-max-microvolt = <2780000>; | ||
| 211 | regulator-always-on; | ||
| 212 | }; | ||
| 213 | |||
| 214 | ldo5_reg: ldo5 { | ||
| 215 | regulator-name = "ldo5_3v3"; | ||
| 216 | regulator-min-microvolt = <3250000>; | ||
| 217 | regulator-max-microvolt = <3350000>; | ||
| 218 | regulator-always-on; | ||
| 219 | }; | ||
| 220 | |||
| 221 | ldo6_reg: ldo6 { | ||
| 222 | regulator-name = "ldo6_1v3"; | ||
| 223 | regulator-min-microvolt = <1250000>; | ||
| 224 | regulator-max-microvolt = <1350000>; | ||
| 225 | regulator-always-on; | ||
| 226 | }; | ||
| 227 | |||
| 228 | ldo7_reg: ldo7 { | ||
| 229 | regulator-name = "ldo7_2v75"; | ||
| 230 | regulator-min-microvolt = <2700000>; | ||
| 231 | regulator-max-microvolt = <2800000>; | ||
| 232 | regulator-always-on; | ||
| 233 | }; | ||
| 234 | |||
| 235 | ldo8_reg: ldo8 { | ||
| 236 | regulator-name = "ldo8_1v8"; | ||
| 237 | regulator-min-microvolt = <1750000>; | ||
| 238 | regulator-max-microvolt = <1850000>; | ||
| 239 | regulator-always-on; | ||
| 240 | }; | ||
| 241 | |||
| 242 | ldo9_reg: ldo9 { | ||
| 243 | regulator-name = "ldo9_1v5"; | ||
| 244 | regulator-min-microvolt = <1450000>; | ||
| 245 | regulator-max-microvolt = <1550000>; | ||
| 246 | regulator-always-on; | ||
| 247 | }; | ||
| 248 | |||
| 249 | ldo10_reg: ldo10 { | ||
| 250 | regulator-name = "ldo10_1v3"; | ||
| 251 | regulator-min-microvolt = <1250000>; | ||
| 252 | regulator-max-microvolt = <1350000>; | ||
| 253 | regulator-always-on; | ||
| 254 | }; | ||
| 255 | }; | ||
| 256 | }; | ||
| 257 | }; | ||
| 258 | |||
| 259 | &nfc { | ||
| 260 | pinctrl-names = "default"; | ||
| 261 | pinctrl-0 = <&pinctrl_nand>; | ||
| 262 | nand-bus-width = <8>; | ||
| 263 | nand-ecc-mode = "hw"; | ||
| 264 | status = "okay"; | ||
| 265 | }; | ||
| 266 | |||
| 267 | &uart1 { | ||
| 268 | pinctrl-names = "default"; | ||
| 269 | pinctrl-0 = <&pinctrl_uart1>; | ||
| 270 | status = "okay"; | ||
| 271 | }; | ||
| 272 | |||
| 273 | &usbh1 { | ||
| 274 | vbus-supply = <®_usb_vbus>; | ||
| 275 | phy_type = "utmi"; | ||
| 276 | status = "okay"; | ||
| 277 | }; | ||
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 4307e80b2d2e..80615dfa2177 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi | |||
| @@ -12,6 +12,9 @@ | |||
| 12 | 12 | ||
| 13 | #include "skeleton.dtsi" | 13 | #include "skeleton.dtsi" |
| 14 | #include "imx53-pinfunc.h" | 14 | #include "imx53-pinfunc.h" |
| 15 | #include <dt-bindings/clock/imx5-clock.h> | ||
| 16 | #include <dt-bindings/gpio/gpio.h> | ||
| 17 | #include <dt-bindings/input/input.h> | ||
| 15 | 18 | ||
| 16 | / { | 19 | / { |
| 17 | aliases { | 20 | aliases { |
| @@ -25,6 +28,10 @@ | |||
| 25 | i2c0 = &i2c1; | 28 | i2c0 = &i2c1; |
| 26 | i2c1 = &i2c2; | 29 | i2c1 = &i2c2; |
| 27 | i2c2 = &i2c3; | 30 | i2c2 = &i2c3; |
| 31 | mmc0 = &esdhc1; | ||
| 32 | mmc1 = &esdhc2; | ||
| 33 | mmc2 = &esdhc3; | ||
| 34 | mmc3 = &esdhc4; | ||
| 28 | serial0 = &uart1; | 35 | serial0 = &uart1; |
| 29 | serial1 = &uart2; | 36 | serial1 = &uart2; |
| 30 | serial2 = &uart3; | 37 | serial2 = &uart3; |
| @@ -84,12 +91,25 @@ | |||
| 84 | interrupt-parent = <&tzic>; | 91 | interrupt-parent = <&tzic>; |
| 85 | ranges; | 92 | ranges; |
| 86 | 93 | ||
| 94 | sata: sata@10000000 { | ||
| 95 | compatible = "fsl,imx53-ahci"; | ||
| 96 | reg = <0x10000000 0x1000>; | ||
| 97 | interrupts = <28>; | ||
| 98 | clocks = <&clks IMX5_CLK_SATA_GATE>, | ||
| 99 | <&clks IMX5_CLK_SATA_REF>, | ||
| 100 | <&clks IMX5_CLK_AHB>; | ||
| 101 | clock-names = "sata_gate", "sata_ref", "ahb"; | ||
| 102 | status = "disabled"; | ||
| 103 | }; | ||
| 104 | |||
| 87 | ipu: ipu@18000000 { | 105 | ipu: ipu@18000000 { |
| 88 | #crtc-cells = <1>; | 106 | #crtc-cells = <1>; |
| 89 | compatible = "fsl,imx53-ipu"; | 107 | compatible = "fsl,imx53-ipu"; |
| 90 | reg = <0x18000000 0x080000000>; | 108 | reg = <0x18000000 0x080000000>; |
| 91 | interrupts = <11 10>; | 109 | interrupts = <11 10>; |
| 92 | clocks = <&clks 59>, <&clks 110>, <&clks 61>; | 110 | clocks = <&clks IMX5_CLK_IPU_GATE>, |
| 111 | <&clks IMX5_CLK_IPU_DI0_GATE>, | ||
| 112 | <&clks IMX5_CLK_IPU_DI1_GATE>; | ||
| 93 | clock-names = "bus", "di0", "di1"; | 113 | clock-names = "bus", "di0", "di1"; |
| 94 | resets = <&src 2>; | 114 | resets = <&src 2>; |
| 95 | }; | 115 | }; |
| @@ -112,7 +132,9 @@ | |||
| 112 | compatible = "fsl,imx53-esdhc"; | 132 | compatible = "fsl,imx53-esdhc"; |
| 113 | reg = <0x50004000 0x4000>; | 133 | reg = <0x50004000 0x4000>; |
| 114 | interrupts = <1>; | 134 | interrupts = <1>; |
| 115 | clocks = <&clks 44>, <&clks 0>, <&clks 71>; | 135 | clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, |
| 136 | <&clks IMX5_CLK_DUMMY>, | ||
| 137 | <&clks IMX5_CLK_ESDHC1_PER_GATE>; | ||
| 116 | clock-names = "ipg", "ahb", "per"; | 138 | clock-names = "ipg", "ahb", "per"; |
| 117 | bus-width = <4>; | 139 | bus-width = <4>; |
| 118 | status = "disabled"; | 140 | status = "disabled"; |
| @@ -122,7 +144,9 @@ | |||
| 122 | compatible = "fsl,imx53-esdhc"; | 144 | compatible = "fsl,imx53-esdhc"; |
| 123 | reg = <0x50008000 0x4000>; | 145 | reg = <0x50008000 0x4000>; |
| 124 | interrupts = <2>; | 146 | interrupts = <2>; |
| 125 | clocks = <&clks 45>, <&clks 0>, <&clks 72>; | 147 | clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, |
| 148 | <&clks IMX5_CLK_DUMMY>, | ||
| 149 | <&clks IMX5_CLK_ESDHC2_PER_GATE>; | ||
| 126 | clock-names = "ipg", "ahb", "per"; | 150 | clock-names = "ipg", "ahb", "per"; |
| 127 | bus-width = <4>; | 151 | bus-width = <4>; |
| 128 | status = "disabled"; | 152 | status = "disabled"; |
| @@ -132,7 +156,8 @@ | |||
| 132 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; | 156 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 133 | reg = <0x5000c000 0x4000>; | 157 | reg = <0x5000c000 0x4000>; |
| 134 | interrupts = <33>; | 158 | interrupts = <33>; |
| 135 | clocks = <&clks 32>, <&clks 33>; | 159 | clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, |
| 160 | <&clks IMX5_CLK_UART3_PER_GATE>; | ||
| 136 | clock-names = "ipg", "per"; | 161 | clock-names = "ipg", "per"; |
| 137 | status = "disabled"; | 162 | status = "disabled"; |
| 138 | }; | 163 | }; |
| @@ -143,16 +168,19 @@ | |||
| 143 | compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; | 168 | compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; |
| 144 | reg = <0x50010000 0x4000>; | 169 | reg = <0x50010000 0x4000>; |
| 145 | interrupts = <36>; | 170 | interrupts = <36>; |
| 146 | clocks = <&clks 51>, <&clks 52>; | 171 | clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, |
| 172 | <&clks IMX5_CLK_ECSPI1_PER_GATE>; | ||
| 147 | clock-names = "ipg", "per"; | 173 | clock-names = "ipg", "per"; |
| 148 | status = "disabled"; | 174 | status = "disabled"; |
| 149 | }; | 175 | }; |
| 150 | 176 | ||
| 151 | ssi2: ssi@50014000 { | 177 | ssi2: ssi@50014000 { |
| 152 | compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; | 178 | compatible = "fsl,imx53-ssi", |
| 179 | "fsl,imx51-ssi", | ||
| 180 | "fsl,imx21-ssi"; | ||
| 153 | reg = <0x50014000 0x4000>; | 181 | reg = <0x50014000 0x4000>; |
| 154 | interrupts = <30>; | 182 | interrupts = <30>; |
| 155 | clocks = <&clks 49>; | 183 | clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>; |
| 156 | dmas = <&sdma 24 1 0>, | 184 | dmas = <&sdma 24 1 0>, |
| 157 | <&sdma 25 1 0>; | 185 | <&sdma 25 1 0>; |
| 158 | dma-names = "rx", "tx"; | 186 | dma-names = "rx", "tx"; |
| @@ -165,7 +193,9 @@ | |||
| 165 | compatible = "fsl,imx53-esdhc"; | 193 | compatible = "fsl,imx53-esdhc"; |
| 166 | reg = <0x50020000 0x4000>; | 194 | reg = <0x50020000 0x4000>; |
| 167 | interrupts = <3>; | 195 | interrupts = <3>; |
| 168 | clocks = <&clks 46>, <&clks 0>, <&clks 73>; | 196 | clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, |
| 197 | <&clks IMX5_CLK_DUMMY>, | ||
| 198 | <&clks IMX5_CLK_ESDHC3_PER_GATE>; | ||
| 169 | clock-names = "ipg", "ahb", "per"; | 199 | clock-names = "ipg", "ahb", "per"; |
| 170 | bus-width = <4>; | 200 | bus-width = <4>; |
| 171 | status = "disabled"; | 201 | status = "disabled"; |
| @@ -175,7 +205,9 @@ | |||
| 175 | compatible = "fsl,imx53-esdhc"; | 205 | compatible = "fsl,imx53-esdhc"; |
| 176 | reg = <0x50024000 0x4000>; | 206 | reg = <0x50024000 0x4000>; |
| 177 | interrupts = <4>; | 207 | interrupts = <4>; |
| 178 | clocks = <&clks 47>, <&clks 0>, <&clks 74>; | 208 | clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, |
| 209 | <&clks IMX5_CLK_DUMMY>, | ||
| 210 | <&clks IMX5_CLK_ESDHC4_PER_GATE>; | ||
| 179 | clock-names = "ipg", "ahb", "per"; | 211 | clock-names = "ipg", "ahb", "per"; |
| 180 | bus-width = <4>; | 212 | bus-width = <4>; |
| 181 | status = "disabled"; | 213 | status = "disabled"; |
| @@ -184,14 +216,14 @@ | |||
| 184 | 216 | ||
| 185 | usbphy0: usbphy@0 { | 217 | usbphy0: usbphy@0 { |
| 186 | compatible = "usb-nop-xceiv"; | 218 | compatible = "usb-nop-xceiv"; |
| 187 | clocks = <&clks 124>; | 219 | clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; |
| 188 | clock-names = "main_clk"; | 220 | clock-names = "main_clk"; |
| 189 | status = "okay"; | 221 | status = "okay"; |
| 190 | }; | 222 | }; |
| 191 | 223 | ||
| 192 | usbphy1: usbphy@1 { | 224 | usbphy1: usbphy@1 { |
| 193 | compatible = "usb-nop-xceiv"; | 225 | compatible = "usb-nop-xceiv"; |
| 194 | clocks = <&clks 125>; | 226 | clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; |
| 195 | clock-names = "main_clk"; | 227 | clock-names = "main_clk"; |
| 196 | status = "okay"; | 228 | status = "okay"; |
| 197 | }; | 229 | }; |
| @@ -200,7 +232,7 @@ | |||
| 200 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; | 232 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 201 | reg = <0x53f80000 0x0200>; | 233 | reg = <0x53f80000 0x0200>; |
| 202 | interrupts = <18>; | 234 | interrupts = <18>; |
| 203 | clocks = <&clks 108>; | 235 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| 204 | fsl,usbmisc = <&usbmisc 0>; | 236 | fsl,usbmisc = <&usbmisc 0>; |
| 205 | fsl,usbphy = <&usbphy0>; | 237 | fsl,usbphy = <&usbphy0>; |
| 206 | status = "disabled"; | 238 | status = "disabled"; |
| @@ -210,7 +242,7 @@ | |||
| 210 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; | 242 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 211 | reg = <0x53f80200 0x0200>; | 243 | reg = <0x53f80200 0x0200>; |
| 212 | interrupts = <14>; | 244 | interrupts = <14>; |
| 213 | clocks = <&clks 108>; | 245 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| 214 | fsl,usbmisc = <&usbmisc 1>; | 246 | fsl,usbmisc = <&usbmisc 1>; |
| 215 | fsl,usbphy = <&usbphy1>; | 247 | fsl,usbphy = <&usbphy1>; |
| 216 | status = "disabled"; | 248 | status = "disabled"; |
| @@ -220,7 +252,7 @@ | |||
| 220 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; | 252 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 221 | reg = <0x53f80400 0x0200>; | 253 | reg = <0x53f80400 0x0200>; |
| 222 | interrupts = <16>; | 254 | interrupts = <16>; |
| 223 | clocks = <&clks 108>; | 255 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| 224 | fsl,usbmisc = <&usbmisc 2>; | 256 | fsl,usbmisc = <&usbmisc 2>; |
| 225 | status = "disabled"; | 257 | status = "disabled"; |
| 226 | }; | 258 | }; |
| @@ -229,7 +261,7 @@ | |||
| 229 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; | 261 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 230 | reg = <0x53f80600 0x0200>; | 262 | reg = <0x53f80600 0x0200>; |
| 231 | interrupts = <17>; | 263 | interrupts = <17>; |
| 232 | clocks = <&clks 108>; | 264 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| 233 | fsl,usbmisc = <&usbmisc 3>; | 265 | fsl,usbmisc = <&usbmisc 3>; |
| 234 | status = "disabled"; | 266 | status = "disabled"; |
| 235 | }; | 267 | }; |
| @@ -238,7 +270,7 @@ | |||
| 238 | #index-cells = <1>; | 270 | #index-cells = <1>; |
| 239 | compatible = "fsl,imx53-usbmisc"; | 271 | compatible = "fsl,imx53-usbmisc"; |
| 240 | reg = <0x53f80800 0x200>; | 272 | reg = <0x53f80800 0x200>; |
| 241 | clocks = <&clks 108>; | 273 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| 242 | }; | 274 | }; |
| 243 | 275 | ||
| 244 | gpio1: gpio@53f84000 { | 276 | gpio1: gpio@53f84000 { |
| @@ -281,18 +313,26 @@ | |||
| 281 | #interrupt-cells = <2>; | 313 | #interrupt-cells = <2>; |
| 282 | }; | 314 | }; |
| 283 | 315 | ||
| 316 | kpp: kpp@53f94000 { | ||
| 317 | compatible = "fsl,imx53-kpp", "fsl,imx21-kpp"; | ||
| 318 | reg = <0x53f94000 0x4000>; | ||
| 319 | interrupts = <60>; | ||
| 320 | clocks = <&clks IMX5_CLK_DUMMY>; | ||
| 321 | status = "disabled"; | ||
| 322 | }; | ||
| 323 | |||
| 284 | wdog1: wdog@53f98000 { | 324 | wdog1: wdog@53f98000 { |
| 285 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; | 325 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; |
| 286 | reg = <0x53f98000 0x4000>; | 326 | reg = <0x53f98000 0x4000>; |
| 287 | interrupts = <58>; | 327 | interrupts = <58>; |
| 288 | clocks = <&clks 0>; | 328 | clocks = <&clks IMX5_CLK_DUMMY>; |
| 289 | }; | 329 | }; |
| 290 | 330 | ||
| 291 | wdog2: wdog@53f9c000 { | 331 | wdog2: wdog@53f9c000 { |
| 292 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; | 332 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; |
| 293 | reg = <0x53f9c000 0x4000>; | 333 | reg = <0x53f9c000 0x4000>; |
| 294 | interrupts = <59>; | 334 | interrupts = <59>; |
| 295 | clocks = <&clks 0>; | 335 | clocks = <&clks IMX5_CLK_DUMMY>; |
| 296 | status = "disabled"; | 336 | status = "disabled"; |
| 297 | }; | 337 | }; |
| 298 | 338 | ||
| @@ -300,521 +340,14 @@ | |||
| 300 | compatible = "fsl,imx53-gpt", "fsl,imx31-gpt"; | 340 | compatible = "fsl,imx53-gpt", "fsl,imx31-gpt"; |
| 301 | reg = <0x53fa0000 0x4000>; | 341 | reg = <0x53fa0000 0x4000>; |
| 302 | interrupts = <39>; | 342 | interrupts = <39>; |
| 303 | clocks = <&clks 36>, <&clks 41>; | 343 | clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, |
| 344 | <&clks IMX5_CLK_GPT_HF_GATE>; | ||
| 304 | clock-names = "ipg", "per"; | 345 | clock-names = "ipg", "per"; |
| 305 | }; | 346 | }; |
| 306 | 347 | ||
| 307 | iomuxc: iomuxc@53fa8000 { | 348 | iomuxc: iomuxc@53fa8000 { |
| 308 | compatible = "fsl,imx53-iomuxc"; | 349 | compatible = "fsl,imx53-iomuxc"; |
| 309 | reg = <0x53fa8000 0x4000>; | 350 | reg = <0x53fa8000 0x4000>; |
| 310 | |||
| 311 | audmux { | ||
| 312 | pinctrl_audmux_1: audmuxgrp-1 { | ||
| 313 | fsl,pins = < | ||
| 314 | MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 | ||
| 315 | MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 | ||
| 316 | MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 | ||
| 317 | MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 | ||
| 318 | >; | ||
| 319 | }; | ||
| 320 | |||
| 321 | pinctrl_audmux_2: audmuxgrp-2 { | ||
| 322 | fsl,pins = < | ||
| 323 | MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000 | ||
| 324 | MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000 | ||
| 325 | MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000 | ||
| 326 | MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000 | ||
| 327 | >; | ||
| 328 | }; | ||
| 329 | |||
| 330 | pinctrl_audmux_3: audmuxgrp-3 { | ||
| 331 | fsl,pins = < | ||
| 332 | MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x80000000 | ||
| 333 | MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x80000000 | ||
| 334 | MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x80000000 | ||
| 335 | MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x80000000 | ||
| 336 | >; | ||
| 337 | }; | ||
| 338 | }; | ||
| 339 | |||
| 340 | fec { | ||
| 341 | pinctrl_fec_1: fecgrp-1 { | ||
| 342 | fsl,pins = < | ||
| 343 | MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 | ||
| 344 | MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 | ||
| 345 | MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 | ||
| 346 | MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 | ||
| 347 | MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 | ||
| 348 | MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 | ||
| 349 | MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 | ||
| 350 | MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 | ||
| 351 | MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 | ||
| 352 | MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 | ||
| 353 | >; | ||
| 354 | }; | ||
| 355 | |||
| 356 | pinctrl_fec_2: fecgrp-2 { | ||
| 357 | fsl,pins = < | ||
| 358 | MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 | ||
| 359 | MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 | ||
| 360 | MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 | ||
| 361 | MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 | ||
| 362 | MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 | ||
| 363 | MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 | ||
| 364 | MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 | ||
| 365 | MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 | ||
| 366 | MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 | ||
| 367 | MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 | ||
| 368 | MX53_PAD_KEY_ROW1__FEC_COL 0x80000000 | ||
| 369 | MX53_PAD_KEY_COL3__FEC_CRS 0x80000000 | ||
| 370 | MX53_PAD_KEY_COL2__FEC_RDATA_2 0x80000000 | ||
| 371 | MX53_PAD_KEY_COL0__FEC_RDATA_3 0x80000000 | ||
| 372 | MX53_PAD_KEY_COL1__FEC_RX_CLK 0x80000000 | ||
| 373 | MX53_PAD_KEY_ROW2__FEC_TDATA_2 0x80000000 | ||
| 374 | MX53_PAD_GPIO_19__FEC_TDATA_3 0x80000000 | ||
| 375 | MX53_PAD_KEY_ROW0__FEC_TX_ER 0x80000000 | ||
| 376 | >; | ||
| 377 | }; | ||
| 378 | }; | ||
| 379 | |||
| 380 | csi { | ||
| 381 | pinctrl_csi_1: csigrp-1 { | ||
| 382 | fsl,pins = < | ||
| 383 | MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5 | ||
| 384 | MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5 | ||
| 385 | MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5 | ||
| 386 | MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5 | ||
| 387 | MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5 | ||
| 388 | MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5 | ||
| 389 | MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5 | ||
| 390 | MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5 | ||
| 391 | MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5 | ||
| 392 | MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5 | ||
| 393 | MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5 | ||
| 394 | MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5 | ||
| 395 | MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x1d5 | ||
| 396 | MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x1d5 | ||
| 397 | MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x1d5 | ||
| 398 | MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x1d5 | ||
| 399 | MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x1d5 | ||
| 400 | MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x1d5 | ||
| 401 | MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x1d5 | ||
| 402 | MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x1d5 | ||
| 403 | MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5 | ||
| 404 | >; | ||
| 405 | }; | ||
| 406 | |||
| 407 | pinctrl_csi_2: csigrp-2 { | ||
| 408 | fsl,pins = < | ||
| 409 | MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5 | ||
| 410 | MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5 | ||
| 411 | MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5 | ||
| 412 | MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5 | ||
| 413 | MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5 | ||
| 414 | MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5 | ||
| 415 | MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5 | ||
| 416 | MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5 | ||
| 417 | MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5 | ||
| 418 | MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5 | ||
| 419 | MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5 | ||
| 420 | >; | ||
| 421 | }; | ||
| 422 | }; | ||
| 423 | |||
| 424 | cspi { | ||
| 425 | pinctrl_cspi_1: cspigrp-1 { | ||
| 426 | fsl,pins = < | ||
| 427 | MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5 | ||
| 428 | MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5 | ||
| 429 | MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5 | ||
| 430 | >; | ||
| 431 | }; | ||
| 432 | |||
| 433 | pinctrl_cspi_2: cspigrp-2 { | ||
| 434 | fsl,pins = < | ||
| 435 | MX53_PAD_EIM_D22__CSPI_MISO 0x1d5 | ||
| 436 | MX53_PAD_EIM_D28__CSPI_MOSI 0x1d5 | ||
| 437 | MX53_PAD_EIM_D21__CSPI_SCLK 0x1d5 | ||
| 438 | >; | ||
| 439 | }; | ||
| 440 | }; | ||
| 441 | |||
| 442 | ecspi1 { | ||
| 443 | pinctrl_ecspi1_1: ecspi1grp-1 { | ||
| 444 | fsl,pins = < | ||
| 445 | MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 | ||
| 446 | MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 | ||
| 447 | MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 | ||
| 448 | >; | ||
| 449 | }; | ||
| 450 | |||
| 451 | pinctrl_ecspi1_2: ecspi1grp-2 { | ||
| 452 | fsl,pins = < | ||
| 453 | MX53_PAD_GPIO_19__ECSPI1_RDY 0x80000000 | ||
| 454 | MX53_PAD_EIM_EB2__ECSPI1_SS0 0x80000000 | ||
| 455 | MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 | ||
| 456 | MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 | ||
| 457 | MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 | ||
| 458 | MX53_PAD_EIM_D19__ECSPI1_SS1 0x80000000 | ||
| 459 | >; | ||
| 460 | }; | ||
| 461 | }; | ||
| 462 | |||
| 463 | ecspi2 { | ||
| 464 | pinctrl_ecspi2_1: ecspi2grp-1 { | ||
| 465 | fsl,pins = < | ||
| 466 | MX53_PAD_EIM_OE__ECSPI2_MISO 0x80000000 | ||
| 467 | MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x80000000 | ||
| 468 | MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x80000000 | ||
| 469 | >; | ||
| 470 | }; | ||
| 471 | }; | ||
| 472 | |||
| 473 | esdhc1 { | ||
| 474 | pinctrl_esdhc1_1: esdhc1grp-1 { | ||
| 475 | fsl,pins = < | ||
| 476 | MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 | ||
| 477 | MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 | ||
| 478 | MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 | ||
| 479 | MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 | ||
| 480 | MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 | ||
| 481 | MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 | ||
| 482 | >; | ||
| 483 | }; | ||
| 484 | |||
| 485 | pinctrl_esdhc1_2: esdhc1grp-2 { | ||
| 486 | fsl,pins = < | ||
| 487 | MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 | ||
| 488 | MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 | ||
| 489 | MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 | ||
| 490 | MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 | ||
| 491 | MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5 | ||
| 492 | MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5 | ||
| 493 | MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5 | ||
| 494 | MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5 | ||
| 495 | MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 | ||
| 496 | MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 | ||
| 497 | >; | ||
| 498 | }; | ||
| 499 | }; | ||
| 500 | |||
| 501 | esdhc2 { | ||
| 502 | pinctrl_esdhc2_1: esdhc2grp-1 { | ||
| 503 | fsl,pins = < | ||
| 504 | MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 | ||
| 505 | MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 | ||
| 506 | MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 | ||
| 507 | MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 | ||
| 508 | MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 | ||
| 509 | MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 | ||
| 510 | >; | ||
| 511 | }; | ||
| 512 | }; | ||
| 513 | |||
| 514 | esdhc3 { | ||
| 515 | pinctrl_esdhc3_1: esdhc3grp-1 { | ||
| 516 | fsl,pins = < | ||
| 517 | MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 | ||
| 518 | MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 | ||
| 519 | MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 | ||
| 520 | MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 | ||
| 521 | MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 | ||
| 522 | MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 | ||
| 523 | MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 | ||
| 524 | MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 | ||
| 525 | MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 | ||
| 526 | MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 | ||
| 527 | >; | ||
| 528 | }; | ||
| 529 | }; | ||
| 530 | |||
| 531 | can1 { | ||
| 532 | pinctrl_can1_1: can1grp-1 { | ||
| 533 | fsl,pins = < | ||
| 534 | MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000 | ||
| 535 | MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x80000000 | ||
| 536 | >; | ||
| 537 | }; | ||
| 538 | |||
| 539 | pinctrl_can1_2: can1grp-2 { | ||
| 540 | fsl,pins = < | ||
| 541 | MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000 | ||
| 542 | MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000 | ||
| 543 | >; | ||
| 544 | }; | ||
| 545 | |||
| 546 | pinctrl_can1_3: can1grp-3 { | ||
| 547 | fsl,pins = < | ||
| 548 | MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000 | ||
| 549 | MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000 | ||
| 550 | >; | ||
| 551 | }; | ||
| 552 | }; | ||
| 553 | |||
| 554 | can2 { | ||
| 555 | pinctrl_can2_1: can2grp-1 { | ||
| 556 | fsl,pins = < | ||
| 557 | MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 | ||
| 558 | MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 | ||
| 559 | >; | ||
| 560 | }; | ||
| 561 | }; | ||
| 562 | |||
| 563 | i2c1 { | ||
| 564 | pinctrl_i2c1_1: i2c1grp-1 { | ||
| 565 | fsl,pins = < | ||
| 566 | MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000 | ||
| 567 | MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000 | ||
| 568 | >; | ||
| 569 | }; | ||
| 570 | |||
| 571 | pinctrl_i2c1_2: i2c1grp-2 { | ||
| 572 | fsl,pins = < | ||
| 573 | MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000 | ||
| 574 | MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000 | ||
| 575 | >; | ||
| 576 | }; | ||
| 577 | }; | ||
| 578 | |||
| 579 | i2c2 { | ||
| 580 | pinctrl_i2c2_1: i2c2grp-1 { | ||
| 581 | fsl,pins = < | ||
| 582 | MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 | ||
| 583 | MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 | ||
| 584 | >; | ||
| 585 | }; | ||
| 586 | |||
| 587 | pinctrl_i2c2_2: i2c2grp-2 { | ||
| 588 | fsl,pins = < | ||
| 589 | MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000 | ||
| 590 | MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000 | ||
| 591 | >; | ||
| 592 | }; | ||
| 593 | }; | ||
| 594 | |||
| 595 | i2c3 { | ||
| 596 | pinctrl_i2c3_1: i2c3grp-1 { | ||
| 597 | fsl,pins = < | ||
| 598 | MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 | ||
| 599 | MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000 | ||
| 600 | >; | ||
| 601 | }; | ||
| 602 | }; | ||
| 603 | |||
| 604 | ipu_disp0 { | ||
| 605 | pinctrl_ipu_disp0_1: ipudisp0grp-1 { | ||
| 606 | fsl,pins = < | ||
| 607 | MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 | ||
| 608 | MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 | ||
| 609 | MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 | ||
| 610 | MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 | ||
| 611 | MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 | ||
| 612 | MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 | ||
| 613 | MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 | ||
| 614 | MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 | ||
| 615 | MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 | ||
| 616 | MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 | ||
| 617 | MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 | ||
| 618 | MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 | ||
| 619 | MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 | ||
| 620 | MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 | ||
| 621 | MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 | ||
| 622 | MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 | ||
| 623 | MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 | ||
| 624 | MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 | ||
| 625 | MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 | ||
| 626 | MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 | ||
| 627 | MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 | ||
| 628 | MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 | ||
| 629 | MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 | ||
| 630 | MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 | ||
| 631 | MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 | ||
| 632 | MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 | ||
| 633 | MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 | ||
| 634 | MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 | ||
| 635 | >; | ||
| 636 | }; | ||
| 637 | }; | ||
| 638 | |||
| 639 | ipu_disp1 { | ||
| 640 | pinctrl_ipu_disp1_1: ipudisp1grp-1 { | ||
| 641 | fsl,pins = < | ||
| 642 | MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5 | ||
| 643 | MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5 | ||
| 644 | MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5 | ||
| 645 | MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5 | ||
| 646 | MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5 | ||
| 647 | MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5 | ||
| 648 | MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5 | ||
| 649 | MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5 | ||
| 650 | MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5 | ||
| 651 | MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5 | ||
| 652 | MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5 | ||
| 653 | MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5 | ||
| 654 | MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5 | ||
| 655 | MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5 | ||
| 656 | MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5 | ||
| 657 | MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5 | ||
| 658 | MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5 | ||
| 659 | MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5 | ||
| 660 | MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5 | ||
| 661 | MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5 | ||
| 662 | MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5 | ||
| 663 | MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5 | ||
| 664 | MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5 | ||
| 665 | MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5 | ||
| 666 | MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5 | ||
| 667 | MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5 | ||
| 668 | MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5 | ||
| 669 | MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5 | ||
| 670 | MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5 | ||
| 671 | MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5 | ||
| 672 | MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5 | ||
| 673 | MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5 | ||
| 674 | >; | ||
| 675 | }; | ||
| 676 | }; | ||
| 677 | |||
| 678 | ipu_disp2 { | ||
| 679 | pinctrl_ipu_disp2_1: ipudisp2grp-1 { | ||
| 680 | fsl,pins = < | ||
| 681 | MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 | ||
| 682 | MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 | ||
| 683 | MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 | ||
| 684 | MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 | ||
| 685 | MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 | ||
| 686 | MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000 | ||
| 687 | MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000 | ||
| 688 | MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000 | ||
| 689 | MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000 | ||
| 690 | MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000 | ||
| 691 | >; | ||
| 692 | }; | ||
| 693 | }; | ||
| 694 | |||
| 695 | nand { | ||
| 696 | pinctrl_nand_1: nandgrp-1 { | ||
| 697 | fsl,pins = < | ||
| 698 | MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 | ||
| 699 | MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 | ||
| 700 | MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 | ||
| 701 | MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 | ||
| 702 | MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 | ||
| 703 | MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 | ||
| 704 | MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 | ||
| 705 | MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 | ||
| 706 | MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 | ||
| 707 | MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 | ||
| 708 | MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 | ||
| 709 | MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 | ||
| 710 | MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 | ||
| 711 | MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 | ||
| 712 | MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 | ||
| 713 | >; | ||
| 714 | }; | ||
| 715 | }; | ||
| 716 | |||
| 717 | owire { | ||
| 718 | pinctrl_owire_1: owiregrp-1 { | ||
| 719 | fsl,pins = < | ||
| 720 | MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000 | ||
| 721 | >; | ||
| 722 | }; | ||
| 723 | }; | ||
| 724 | |||
| 725 | pwm1 { | ||
| 726 | pinctrl_pwm1_1: pwm1grp-1 { | ||
| 727 | fsl,pins = < | ||
| 728 | MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5 | ||
| 729 | >; | ||
| 730 | }; | ||
| 731 | }; | ||
| 732 | |||
| 733 | pwm2 { | ||
| 734 | pinctrl_pwm2_1: pwm2grp-1 { | ||
| 735 | fsl,pins = < | ||
| 736 | MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 | ||
| 737 | >; | ||
| 738 | }; | ||
| 739 | }; | ||
| 740 | |||
| 741 | uart1 { | ||
| 742 | pinctrl_uart1_1: uart1grp-1 { | ||
| 743 | fsl,pins = < | ||
| 744 | MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 | ||
| 745 | MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 | ||
| 746 | >; | ||
| 747 | }; | ||
| 748 | |||
| 749 | pinctrl_uart1_2: uart1grp-2 { | ||
| 750 | fsl,pins = < | ||
| 751 | MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 | ||
| 752 | MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 | ||
| 753 | >; | ||
| 754 | }; | ||
| 755 | |||
| 756 | pinctrl_uart1_3: uart1grp-3 { | ||
| 757 | fsl,pins = < | ||
| 758 | MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5 | ||
| 759 | MX53_PAD_PATA_IORDY__UART1_RTS 0x1c5 | ||
| 760 | >; | ||
| 761 | }; | ||
| 762 | }; | ||
| 763 | |||
| 764 | uart2 { | ||
| 765 | pinctrl_uart2_1: uart2grp-1 { | ||
| 766 | fsl,pins = < | ||
| 767 | MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 | ||
| 768 | MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 | ||
| 769 | >; | ||
| 770 | }; | ||
| 771 | |||
| 772 | pinctrl_uart2_2: uart2grp-2 { | ||
| 773 | fsl,pins = < | ||
| 774 | MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5 | ||
| 775 | MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5 | ||
| 776 | MX53_PAD_PATA_DIOR__UART2_RTS 0x1c5 | ||
| 777 | MX53_PAD_PATA_INTRQ__UART2_CTS 0x1c5 | ||
| 778 | >; | ||
| 779 | }; | ||
| 780 | }; | ||
| 781 | |||
| 782 | uart3 { | ||
| 783 | pinctrl_uart3_1: uart3grp-1 { | ||
| 784 | fsl,pins = < | ||
| 785 | MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 | ||
| 786 | MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 | ||
| 787 | MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 | ||
| 788 | MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 | ||
| 789 | >; | ||
| 790 | }; | ||
| 791 | |||
| 792 | pinctrl_uart3_2: uart3grp-2 { | ||
| 793 | fsl,pins = < | ||
| 794 | MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 | ||
| 795 | MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 | ||
| 796 | >; | ||
| 797 | }; | ||
| 798 | |||
| 799 | }; | ||
| 800 | |||
| 801 | uart4 { | ||
| 802 | pinctrl_uart4_1: uart4grp-1 { | ||
| 803 | fsl,pins = < | ||
| 804 | MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4 | ||
| 805 | MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4 | ||
| 806 | >; | ||
| 807 | }; | ||
| 808 | }; | ||
| 809 | |||
| 810 | uart5 { | ||
| 811 | pinctrl_uart5_1: uart5grp-1 { | ||
| 812 | fsl,pins = < | ||
| 813 | MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1e4 | ||
| 814 | MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1e4 | ||
| 815 | >; | ||
| 816 | }; | ||
| 817 | }; | ||
| 818 | }; | 351 | }; |
| 819 | 352 | ||
| 820 | gpr: iomuxc-gpr@53fa8000 { | 353 | gpr: iomuxc-gpr@53fa8000 { |
| @@ -828,9 +361,12 @@ | |||
| 828 | compatible = "fsl,imx53-ldb"; | 361 | compatible = "fsl,imx53-ldb"; |
| 829 | reg = <0x53fa8008 0x4>; | 362 | reg = <0x53fa8008 0x4>; |
| 830 | gpr = <&gpr>; | 363 | gpr = <&gpr>; |
| 831 | clocks = <&clks 122>, <&clks 120>, | 364 | clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, |
| 832 | <&clks 115>, <&clks 116>, | 365 | <&clks IMX5_CLK_LDB_DI1_SEL>, |
| 833 | <&clks 123>, <&clks 85>; | 366 | <&clks IMX5_CLK_IPU_DI0_SEL>, |
| 367 | <&clks IMX5_CLK_IPU_DI1_SEL>, | ||
| 368 | <&clks IMX5_CLK_LDB_DI0_GATE>, | ||
| 369 | <&clks IMX5_CLK_LDB_DI1_GATE>; | ||
| 834 | clock-names = "di0_pll", "di1_pll", | 370 | clock-names = "di0_pll", "di1_pll", |
| 835 | "di0_sel", "di1_sel", | 371 | "di0_sel", "di1_sel", |
| 836 | "di0", "di1"; | 372 | "di0", "di1"; |
| @@ -853,7 +389,8 @@ | |||
| 853 | #pwm-cells = <2>; | 389 | #pwm-cells = <2>; |
| 854 | compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; | 390 | compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; |
| 855 | reg = <0x53fb4000 0x4000>; | 391 | reg = <0x53fb4000 0x4000>; |
| 856 | clocks = <&clks 37>, <&clks 38>; | 392 | clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, |
| 393 | <&clks IMX5_CLK_PWM1_HF_GATE>; | ||
| 857 | clock-names = "ipg", "per"; | 394 | clock-names = "ipg", "per"; |
| 858 | interrupts = <61>; | 395 | interrupts = <61>; |
| 859 | }; | 396 | }; |
| @@ -862,7 +399,8 @@ | |||
| 862 | #pwm-cells = <2>; | 399 | #pwm-cells = <2>; |
| 863 | compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; | 400 | compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; |
| 864 | reg = <0x53fb8000 0x4000>; | 401 | reg = <0x53fb8000 0x4000>; |
| 865 | clocks = <&clks 39>, <&clks 40>; | 402 | clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, |
| 403 | <&clks IMX5_CLK_PWM2_HF_GATE>; | ||
| 866 | clock-names = "ipg", "per"; | 404 | clock-names = "ipg", "per"; |
| 867 | interrupts = <94>; | 405 | interrupts = <94>; |
| 868 | }; | 406 | }; |
| @@ -871,7 +409,8 @@ | |||
| 871 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; | 409 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 872 | reg = <0x53fbc000 0x4000>; | 410 | reg = <0x53fbc000 0x4000>; |
| 873 | interrupts = <31>; | 411 | interrupts = <31>; |
| 874 | clocks = <&clks 28>, <&clks 29>; | 412 | clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, |
| 413 | <&clks IMX5_CLK_UART1_PER_GATE>; | ||
| 875 | clock-names = "ipg", "per"; | 414 | clock-names = "ipg", "per"; |
| 876 | status = "disabled"; | 415 | status = "disabled"; |
| 877 | }; | 416 | }; |
| @@ -880,7 +419,8 @@ | |||
| 880 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; | 419 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 881 | reg = <0x53fc0000 0x4000>; | 420 | reg = <0x53fc0000 0x4000>; |
| 882 | interrupts = <32>; | 421 | interrupts = <32>; |
| 883 | clocks = <&clks 30>, <&clks 31>; | 422 | clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, |
| 423 | <&clks IMX5_CLK_UART2_PER_GATE>; | ||
| 884 | clock-names = "ipg", "per"; | 424 | clock-names = "ipg", "per"; |
| 885 | status = "disabled"; | 425 | status = "disabled"; |
| 886 | }; | 426 | }; |
| @@ -889,7 +429,8 @@ | |||
| 889 | compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; | 429 | compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; |
| 890 | reg = <0x53fc8000 0x4000>; | 430 | reg = <0x53fc8000 0x4000>; |
| 891 | interrupts = <82>; | 431 | interrupts = <82>; |
| 892 | clocks = <&clks 158>, <&clks 157>; | 432 | clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, |
| 433 | <&clks IMX5_CLK_CAN1_SERIAL_GATE>; | ||
| 893 | clock-names = "ipg", "per"; | 434 | clock-names = "ipg", "per"; |
| 894 | status = "disabled"; | 435 | status = "disabled"; |
| 895 | }; | 436 | }; |
| @@ -898,7 +439,8 @@ | |||
| 898 | compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; | 439 | compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; |
| 899 | reg = <0x53fcc000 0x4000>; | 440 | reg = <0x53fcc000 0x4000>; |
| 900 | interrupts = <83>; | 441 | interrupts = <83>; |
| 901 | clocks = <&clks 87>, <&clks 86>; | 442 | clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>, |
| 443 | <&clks IMX5_CLK_CAN2_SERIAL_GATE>; | ||
| 902 | clock-names = "ipg", "per"; | 444 | clock-names = "ipg", "per"; |
| 903 | status = "disabled"; | 445 | status = "disabled"; |
| 904 | }; | 446 | }; |
| @@ -952,7 +494,7 @@ | |||
| 952 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; | 494 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
| 953 | reg = <0x53fec000 0x4000>; | 495 | reg = <0x53fec000 0x4000>; |
| 954 | interrupts = <64>; | 496 | interrupts = <64>; |
| 955 | clocks = <&clks 88>; | 497 | clocks = <&clks IMX5_CLK_I2C3_GATE>; |
| 956 | status = "disabled"; | 498 | status = "disabled"; |
| 957 | }; | 499 | }; |
| 958 | 500 | ||
| @@ -960,7 +502,8 @@ | |||
| 960 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; | 502 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 961 | reg = <0x53ff0000 0x4000>; | 503 | reg = <0x53ff0000 0x4000>; |
| 962 | interrupts = <13>; | 504 | interrupts = <13>; |
| 963 | clocks = <&clks 65>, <&clks 66>; | 505 | clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, |
| 506 | <&clks IMX5_CLK_UART4_PER_GATE>; | ||
| 964 | clock-names = "ipg", "per"; | 507 | clock-names = "ipg", "per"; |
| 965 | status = "disabled"; | 508 | status = "disabled"; |
| 966 | }; | 509 | }; |
| @@ -977,14 +520,15 @@ | |||
| 977 | compatible = "fsl,imx53-iim", "fsl,imx27-iim"; | 520 | compatible = "fsl,imx53-iim", "fsl,imx27-iim"; |
| 978 | reg = <0x63f98000 0x4000>; | 521 | reg = <0x63f98000 0x4000>; |
| 979 | interrupts = <69>; | 522 | interrupts = <69>; |
| 980 | clocks = <&clks 107>; | 523 | clocks = <&clks IMX5_CLK_IIM_GATE>; |
| 981 | }; | 524 | }; |
| 982 | 525 | ||
| 983 | uart5: serial@63f90000 { | 526 | uart5: serial@63f90000 { |
| 984 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; | 527 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 985 | reg = <0x63f90000 0x4000>; | 528 | reg = <0x63f90000 0x4000>; |
| 986 | interrupts = <86>; | 529 | interrupts = <86>; |
| 987 | clocks = <&clks 67>, <&clks 68>; | 530 | clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, |
| 531 | <&clks IMX5_CLK_UART5_PER_GATE>; | ||
| 988 | clock-names = "ipg", "per"; | 532 | clock-names = "ipg", "per"; |
| 989 | status = "disabled"; | 533 | status = "disabled"; |
| 990 | }; | 534 | }; |
| @@ -992,7 +536,7 @@ | |||
| 992 | owire: owire@63fa4000 { | 536 | owire: owire@63fa4000 { |
| 993 | compatible = "fsl,imx53-owire", "fsl,imx21-owire"; | 537 | compatible = "fsl,imx53-owire", "fsl,imx21-owire"; |
| 994 | reg = <0x63fa4000 0x4000>; | 538 | reg = <0x63fa4000 0x4000>; |
| 995 | clocks = <&clks 159>; | 539 | clocks = <&clks IMX5_CLK_OWIRE_GATE>; |
| 996 | status = "disabled"; | 540 | status = "disabled"; |
| 997 | }; | 541 | }; |
| 998 | 542 | ||
| @@ -1002,7 +546,8 @@ | |||
| 1002 | compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; | 546 | compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; |
| 1003 | reg = <0x63fac000 0x4000>; | 547 | reg = <0x63fac000 0x4000>; |
| 1004 | interrupts = <37>; | 548 | interrupts = <37>; |
| 1005 | clocks = <&clks 53>, <&clks 54>; | 549 | clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, |
| 550 | <&clks IMX5_CLK_ECSPI2_PER_GATE>; | ||
| 1006 | clock-names = "ipg", "per"; | 551 | clock-names = "ipg", "per"; |
| 1007 | status = "disabled"; | 552 | status = "disabled"; |
| 1008 | }; | 553 | }; |
| @@ -1011,7 +556,8 @@ | |||
| 1011 | compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; | 556 | compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; |
| 1012 | reg = <0x63fb0000 0x4000>; | 557 | reg = <0x63fb0000 0x4000>; |
| 1013 | interrupts = <6>; | 558 | interrupts = <6>; |
| 1014 | clocks = <&clks 56>, <&clks 56>; | 559 | clocks = <&clks IMX5_CLK_SDMA_GATE>, |
| 560 | <&clks IMX5_CLK_SDMA_GATE>; | ||
| 1015 | clock-names = "ipg", "ahb"; | 561 | clock-names = "ipg", "ahb"; |
| 1016 | #dma-cells = <3>; | 562 | #dma-cells = <3>; |
| 1017 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; | 563 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; |
| @@ -1023,7 +569,8 @@ | |||
| 1023 | compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; | 569 | compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; |
| 1024 | reg = <0x63fc0000 0x4000>; | 570 | reg = <0x63fc0000 0x4000>; |
| 1025 | interrupts = <38>; | 571 | interrupts = <38>; |
| 1026 | clocks = <&clks 55>, <&clks 55>; | 572 | clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, |
| 573 | <&clks IMX5_CLK_CSPI_IPG_GATE>; | ||
| 1027 | clock-names = "ipg", "per"; | 574 | clock-names = "ipg", "per"; |
| 1028 | status = "disabled"; | 575 | status = "disabled"; |
| 1029 | }; | 576 | }; |
| @@ -1034,7 +581,7 @@ | |||
| 1034 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; | 581 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
| 1035 | reg = <0x63fc4000 0x4000>; | 582 | reg = <0x63fc4000 0x4000>; |
| 1036 | interrupts = <63>; | 583 | interrupts = <63>; |
| 1037 | clocks = <&clks 35>; | 584 | clocks = <&clks IMX5_CLK_I2C2_GATE>; |
| 1038 | status = "disabled"; | 585 | status = "disabled"; |
| 1039 | }; | 586 | }; |
| 1040 | 587 | ||
| @@ -1044,15 +591,16 @@ | |||
| 1044 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; | 591 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
| 1045 | reg = <0x63fc8000 0x4000>; | 592 | reg = <0x63fc8000 0x4000>; |
| 1046 | interrupts = <62>; | 593 | interrupts = <62>; |
| 1047 | clocks = <&clks 34>; | 594 | clocks = <&clks IMX5_CLK_I2C1_GATE>; |
| 1048 | status = "disabled"; | 595 | status = "disabled"; |
| 1049 | }; | 596 | }; |
| 1050 | 597 | ||
| 1051 | ssi1: ssi@63fcc000 { | 598 | ssi1: ssi@63fcc000 { |
| 1052 | compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; | 599 | compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", |
| 600 | "fsl,imx21-ssi"; | ||
| 1053 | reg = <0x63fcc000 0x4000>; | 601 | reg = <0x63fcc000 0x4000>; |
| 1054 | interrupts = <29>; | 602 | interrupts = <29>; |
| 1055 | clocks = <&clks 48>; | 603 | clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>; |
| 1056 | dmas = <&sdma 28 0 0>, | 604 | dmas = <&sdma 28 0 0>, |
| 1057 | <&sdma 29 0 0>; | 605 | <&sdma 29 0 0>; |
| 1058 | dma-names = "rx", "tx"; | 606 | dma-names = "rx", "tx"; |
| @@ -1071,15 +619,16 @@ | |||
| 1071 | compatible = "fsl,imx53-nand"; | 619 | compatible = "fsl,imx53-nand"; |
| 1072 | reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; | 620 | reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; |
| 1073 | interrupts = <8>; | 621 | interrupts = <8>; |
| 1074 | clocks = <&clks 60>; | 622 | clocks = <&clks IMX5_CLK_NFC_GATE>; |
| 1075 | status = "disabled"; | 623 | status = "disabled"; |
| 1076 | }; | 624 | }; |
| 1077 | 625 | ||
| 1078 | ssi3: ssi@63fe8000 { | 626 | ssi3: ssi@63fe8000 { |
| 1079 | compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; | 627 | compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", |
| 628 | "fsl,imx21-ssi"; | ||
| 1080 | reg = <0x63fe8000 0x4000>; | 629 | reg = <0x63fe8000 0x4000>; |
| 1081 | interrupts = <96>; | 630 | interrupts = <96>; |
| 1082 | clocks = <&clks 50>; | 631 | clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>; |
| 1083 | dmas = <&sdma 46 0 0>, | 632 | dmas = <&sdma 46 0 0>, |
| 1084 | <&sdma 47 0 0>; | 633 | <&sdma 47 0 0>; |
| 1085 | dma-names = "rx", "tx"; | 634 | dma-names = "rx", "tx"; |
| @@ -1092,7 +641,9 @@ | |||
| 1092 | compatible = "fsl,imx53-fec", "fsl,imx25-fec"; | 641 | compatible = "fsl,imx53-fec", "fsl,imx25-fec"; |
| 1093 | reg = <0x63fec000 0x4000>; | 642 | reg = <0x63fec000 0x4000>; |
| 1094 | interrupts = <87>; | 643 | interrupts = <87>; |
| 1095 | clocks = <&clks 42>, <&clks 42>, <&clks 42>; | 644 | clocks = <&clks IMX5_CLK_FEC_GATE>, |
| 645 | <&clks IMX5_CLK_FEC_GATE>, | ||
| 646 | <&clks IMX5_CLK_FEC_GATE>; | ||
| 1096 | clock-names = "ipg", "ahb", "ptp"; | 647 | clock-names = "ipg", "ahb", "ptp"; |
| 1097 | status = "disabled"; | 648 | status = "disabled"; |
| 1098 | }; | 649 | }; |
| @@ -1101,7 +652,8 @@ | |||
| 1101 | compatible = "fsl,imx53-tve"; | 652 | compatible = "fsl,imx53-tve"; |
| 1102 | reg = <0x63ff0000 0x1000>; | 653 | reg = <0x63ff0000 0x1000>; |
| 1103 | interrupts = <92>; | 654 | interrupts = <92>; |
| 1104 | clocks = <&clks 69>, <&clks 116>; | 655 | clocks = <&clks IMX5_CLK_TVE_GATE>, |
| 656 | <&clks IMX5_CLK_IPU_DI1_SEL>; | ||
| 1105 | clock-names = "tve", "di_sel"; | 657 | clock-names = "tve", "di_sel"; |
| 1106 | crtcs = <&ipu 1>; | 658 | crtcs = <&ipu 1>; |
| 1107 | status = "disabled"; | 659 | status = "disabled"; |
| @@ -1111,7 +663,8 @@ | |||
| 1111 | compatible = "fsl,imx53-vpu"; | 663 | compatible = "fsl,imx53-vpu"; |
| 1112 | reg = <0x63ff4000 0x1000>; | 664 | reg = <0x63ff4000 0x1000>; |
| 1113 | interrupts = <9>; | 665 | interrupts = <9>; |
| 1114 | clocks = <&clks 63>, <&clks 63>; | 666 | clocks = <&clks IMX5_CLK_VPU_GATE>, |
| 667 | <&clks IMX5_CLK_VPU_GATE>; | ||
| 1115 | clock-names = "per", "ahb"; | 668 | clock-names = "per", "ahb"; |
| 1116 | iram = <&ocram>; | 669 | iram = <&ocram>; |
| 1117 | status = "disabled"; | 670 | status = "disabled"; |
| @@ -1121,7 +674,7 @@ | |||
| 1121 | ocram: sram@f8000000 { | 674 | ocram: sram@f8000000 { |
| 1122 | compatible = "mmio-sram"; | 675 | compatible = "mmio-sram"; |
| 1123 | reg = <0xf8000000 0x20000>; | 676 | reg = <0xf8000000 0x20000>; |
| 1124 | clocks = <&clks 186>; | 677 | clocks = <&clks IMX5_CLK_OCRAM>; |
| 1125 | }; | 678 | }; |
| 1126 | }; | 679 | }; |
| 1127 | }; | 680 | }; |
diff --git a/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts b/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts new file mode 100644 index 000000000000..994f96a3fb54 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts | |||
| @@ -0,0 +1,23 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Sascha Hauer <s.hauer@pengutronix.de> | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __DTS_V1__ | ||
| 13 | #define __DTS_V1__ | ||
| 14 | /dts-v1/; | ||
| 15 | #endif | ||
| 16 | |||
| 17 | #include "imx6dl.dtsi" | ||
| 18 | #include "imx6qdl-dfi-fs700-m60.dtsi" | ||
| 19 | |||
| 20 | / { | ||
| 21 | model = "DFI FS700-M60-6DL i.MX6dl Q7 Board"; | ||
| 22 | compatible = "dfi,fs700-m60-6dl", "dfi,fs700e-m60", "fsl,imx6dl"; | ||
| 23 | }; | ||
diff --git a/arch/arm/boot/dts/imx6dl-gw51xx.dts b/arch/arm/boot/dts/imx6dl-gw51xx.dts new file mode 100644 index 000000000000..4bd055f4c930 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-gw51xx.dts | |||
| @@ -0,0 +1,19 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Gateworks Corporation | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | #include "imx6dl.dtsi" | ||
| 14 | #include "imx6qdl-gw51xx.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Gateworks Ventana i.MX6 DualLite GW51XX"; | ||
| 18 | compatible = "gw,imx6dl-gw51xx", "gw,ventana", "fsl,imx6dl"; | ||
| 19 | }; | ||
diff --git a/arch/arm/boot/dts/imx6dl-gw52xx.dts b/arch/arm/boot/dts/imx6dl-gw52xx.dts new file mode 100644 index 000000000000..c9136058f15e --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-gw52xx.dts | |||
| @@ -0,0 +1,19 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Gateworks Corporation | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | #include "imx6dl.dtsi" | ||
| 14 | #include "imx6qdl-gw52xx.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Gateworks Ventana i.MX6 DualLite GW52XX"; | ||
| 18 | compatible = "gw,imx6dl-gw52xx", "gw,ventana", "fsl,imx6dl"; | ||
| 19 | }; | ||
diff --git a/arch/arm/boot/dts/imx6dl-gw53xx.dts b/arch/arm/boot/dts/imx6dl-gw53xx.dts new file mode 100644 index 000000000000..61818a14fde6 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-gw53xx.dts | |||
| @@ -0,0 +1,19 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Gateworks Corporation | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | #include "imx6dl.dtsi" | ||
| 14 | #include "imx6qdl-gw53xx.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Gateworks Ventana i.MX6 DualLite GW53XX"; | ||
| 18 | compatible = "gw,imx6dl-gw53xx", "gw,ventana", "fsl,imx6dl"; | ||
| 19 | }; | ||
diff --git a/arch/arm/boot/dts/imx6dl-gw54xx.dts b/arch/arm/boot/dts/imx6dl-gw54xx.dts new file mode 100644 index 000000000000..ab38b6770a06 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-gw54xx.dts | |||
| @@ -0,0 +1,19 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Gateworks Corporation | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | #include "imx6dl.dtsi" | ||
| 14 | #include "imx6qdl-gw54xx.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Gateworks Ventana i.MX6 DualLite GW54XX"; | ||
| 18 | compatible = "gw,imx6dl-gw54xx", "gw,ventana", "fsl,imx6dl"; | ||
| 19 | }; | ||
diff --git a/arch/arm/boot/dts/imx6dl-nitrogen6x.dts b/arch/arm/boot/dts/imx6dl-nitrogen6x.dts new file mode 100644 index 000000000000..5f4d33ccc4b3 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-nitrogen6x.dts | |||
| @@ -0,0 +1,21 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Boundary Devices, Inc. | ||
| 3 | * Copyright 2012 Freescale Semiconductor, Inc. | ||
| 4 | * Copyright 2011 Linaro Ltd. | ||
| 5 | * | ||
| 6 | * The code contained herein is licensed under the GNU General Public | ||
| 7 | * License. You may obtain a copy of the GNU General Public License | ||
| 8 | * Version 2 or later at the following locations: | ||
| 9 | * | ||
| 10 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 11 | * http://www.gnu.org/copyleft/gpl.html | ||
| 12 | */ | ||
| 13 | |||
| 14 | /dts-v1/; | ||
| 15 | #include "imx6dl.dtsi" | ||
| 16 | #include "imx6qdl-nitrogen6x.dtsi" | ||
| 17 | |||
| 18 | / { | ||
| 19 | model = "Freescale i.MX6 DualLite Nitrogen6x Board"; | ||
| 20 | compatible = "fsl,imx6dl-nitrogen6x", "fsl,imx6dl"; | ||
| 21 | }; | ||
diff --git a/arch/arm/boot/dts/imx6dl-pinfunc.h b/arch/arm/boot/dts/imx6dl-pinfunc.h index b81a7a4ebab6..0ead323fdbd2 100644 --- a/arch/arm/boot/dts/imx6dl-pinfunc.h +++ b/arch/arm/boot/dts/imx6dl-pinfunc.h | |||
| @@ -755,6 +755,7 @@ | |||
| 755 | #define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x230 0x600 0x878 0x6 0x2 | 755 | #define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x230 0x600 0x878 0x6 0x2 |
| 756 | #define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x230 0x600 0x000 0x7 0x0 | 756 | #define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x230 0x600 0x000 0x7 0x0 |
| 757 | #define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x234 0x604 0x840 0x0 0x1 | 757 | #define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x234 0x604 0x840 0x0 0x1 |
| 758 | #define MX6QDL_PAD_GPIO_6__ENET_IRQ 0x234 0x604 0x03c 0x11 0xff000609 | ||
| 758 | #define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x234 0x604 0x87c 0x2 0x2 | 759 | #define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x234 0x604 0x87c 0x2 0x2 |
| 759 | #define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x234 0x604 0x000 0x5 0x0 | 760 | #define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x234 0x604 0x000 0x5 0x0 |
| 760 | #define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x234 0x604 0x000 0x6 0x0 | 761 | #define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x234 0x604 0x000 0x6 0x0 |
| @@ -950,6 +951,7 @@ | |||
| 950 | #define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x2d8 0x6c0 0x000 0x5 0x0 | 951 | #define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x2d8 0x6c0 0x000 0x5 0x0 |
| 951 | #define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x2d8 0x6c0 0x000 0x7 0x0 | 952 | #define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x2d8 0x6c0 0x000 0x7 0x0 |
| 952 | #define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x2dc 0x6c4 0x928 0x0 0x1 | 953 | #define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x2dc 0x6c4 0x928 0x0 0x1 |
| 954 | #define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x2dc 0x6c4 0x000 0x2 0x0 | ||
| 953 | #define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x2dc 0x6c4 0x000 0x3 0x0 | 955 | #define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x2dc 0x6c4 0x000 0x3 0x0 |
| 954 | #define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x2dc 0x6c4 0x000 0x5 0x0 | 956 | #define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x2dc 0x6c4 0x000 0x5 0x0 |
| 955 | #define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x2e0 0x6c8 0x000 0x0 0x0 | 957 | #define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x2e0 0x6c8 0x000 0x0 0x0 |
diff --git a/arch/arm/boot/dts/imx6dl-sabrelite.dts b/arch/arm/boot/dts/imx6dl-sabrelite.dts new file mode 100644 index 000000000000..2de04479dc35 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-sabrelite.dts | |||
| @@ -0,0 +1,20 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. | ||
| 3 | * Copyright 2011 Linaro Ltd. | ||
| 4 | * | ||
| 5 | * The code contained herein is licensed under the GNU General Public | ||
| 6 | * License. You may obtain a copy of the GNU General Public License | ||
| 7 | * Version 2 or later at the following locations: | ||
| 8 | * | ||
| 9 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 10 | * http://www.gnu.org/copyleft/gpl.html | ||
| 11 | */ | ||
| 12 | |||
| 13 | /dts-v1/; | ||
| 14 | #include "imx6dl.dtsi" | ||
| 15 | #include "imx6qdl-sabrelite.dtsi" | ||
| 16 | |||
| 17 | / { | ||
| 18 | model = "Freescale i.MX6 DualLite SABRE Lite Board"; | ||
| 19 | compatible = "fsl,imx6dl-sabrelite", "fsl,imx6dl"; | ||
| 20 | }; | ||
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 9e8ae118fdd4..9c4942f2817a 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi | |||
| @@ -8,6 +8,7 @@ | |||
| 8 | * | 8 | * |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 11 | #include "imx6dl-pinfunc.h" | 12 | #include "imx6dl-pinfunc.h" |
| 12 | #include "imx6qdl.dtsi" | 13 | #include "imx6qdl.dtsi" |
| 13 | 14 | ||
| @@ -21,6 +22,26 @@ | |||
| 21 | device_type = "cpu"; | 22 | device_type = "cpu"; |
| 22 | reg = <0>; | 23 | reg = <0>; |
| 23 | next-level-cache = <&L2>; | 24 | next-level-cache = <&L2>; |
| 25 | operating-points = < | ||
| 26 | /* kHz uV */ | ||
| 27 | 996000 1275000 | ||
| 28 | 792000 1175000 | ||
| 29 | 396000 1075000 | ||
| 30 | >; | ||
| 31 | fsl,soc-operating-points = < | ||
| 32 | /* ARM kHz SOC-PU uV */ | ||
| 33 | 996000 1175000 | ||
| 34 | 792000 1175000 | ||
| 35 | 396000 1175000 | ||
| 36 | >; | ||
| 37 | clock-latency = <61036>; /* two CLK32 periods */ | ||
| 38 | clocks = <&clks 104>, <&clks 6>, <&clks 16>, | ||
| 39 | <&clks 17>, <&clks 170>; | ||
| 40 | clock-names = "arm", "pll2_pfd2_396m", "step", | ||
| 41 | "pll1_sw", "pll1_sys"; | ||
| 42 | arm-supply = <®_arm>; | ||
| 43 | pu-supply = <®_pu>; | ||
| 44 | soc-supply = <®_soc>; | ||
| 24 | }; | 45 | }; |
| 25 | 46 | ||
| 26 | cpu@1 { | 47 | cpu@1 { |
| @@ -45,17 +66,17 @@ | |||
| 45 | 66 | ||
| 46 | pxp: pxp@020f0000 { | 67 | pxp: pxp@020f0000 { |
| 47 | reg = <0x020f0000 0x4000>; | 68 | reg = <0x020f0000 0x4000>; |
| 48 | interrupts = <0 98 0x04>; | 69 | interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; |
| 49 | }; | 70 | }; |
| 50 | 71 | ||
| 51 | epdc: epdc@020f4000 { | 72 | epdc: epdc@020f4000 { |
| 52 | reg = <0x020f4000 0x4000>; | 73 | reg = <0x020f4000 0x4000>; |
| 53 | interrupts = <0 97 0x04>; | 74 | interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; |
| 54 | }; | 75 | }; |
| 55 | 76 | ||
| 56 | lcdif: lcdif@020f8000 { | 77 | lcdif: lcdif@020f8000 { |
| 57 | reg = <0x020f8000 0x4000>; | 78 | reg = <0x020f8000 0x4000>; |
| 58 | interrupts = <0 39 0x04>; | 79 | interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; |
| 59 | }; | 80 | }; |
| 60 | }; | 81 | }; |
| 61 | 82 | ||
| @@ -65,7 +86,7 @@ | |||
| 65 | #size-cells = <0>; | 86 | #size-cells = <0>; |
| 66 | compatible = "fsl,imx1-i2c"; | 87 | compatible = "fsl,imx1-i2c"; |
| 67 | reg = <0x021f8000 0x4000>; | 88 | reg = <0x021f8000 0x4000>; |
| 68 | interrupts = <0 35 0x04>; | 89 | interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; |
| 69 | status = "disabled"; | 90 | status = "disabled"; |
| 70 | }; | 91 | }; |
| 71 | }; | 92 | }; |
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts index edf1bd967164..78df05e9d1ce 100644 --- a/arch/arm/boot/dts/imx6q-arm2.dts +++ b/arch/arm/boot/dts/imx6q-arm2.dts | |||
| @@ -23,14 +23,27 @@ | |||
| 23 | 23 | ||
| 24 | regulators { | 24 | regulators { |
| 25 | compatible = "simple-bus"; | 25 | compatible = "simple-bus"; |
| 26 | #address-cells = <1>; | ||
| 27 | #size-cells = <0>; | ||
| 26 | 28 | ||
| 27 | reg_3p3v: 3p3v { | 29 | reg_3p3v: regulator@0 { |
| 28 | compatible = "regulator-fixed"; | 30 | compatible = "regulator-fixed"; |
| 31 | reg = <0>; | ||
| 29 | regulator-name = "3P3V"; | 32 | regulator-name = "3P3V"; |
| 30 | regulator-min-microvolt = <3300000>; | 33 | regulator-min-microvolt = <3300000>; |
| 31 | regulator-max-microvolt = <3300000>; | 34 | regulator-max-microvolt = <3300000>; |
| 32 | regulator-always-on; | 35 | regulator-always-on; |
| 33 | }; | 36 | }; |
| 37 | |||
| 38 | reg_usb_otg_vbus: regulator@1 { | ||
| 39 | compatible = "regulator-fixed"; | ||
| 40 | reg = <1>; | ||
| 41 | regulator-name = "usb_otg_vbus"; | ||
| 42 | regulator-min-microvolt = <5000000>; | ||
| 43 | regulator-max-microvolt = <5000000>; | ||
| 44 | gpio = <&gpio3 22 0>; | ||
| 45 | enable-active-high; | ||
| 46 | }; | ||
| 34 | }; | 47 | }; |
| 35 | 48 | ||
| 36 | leds { | 49 | leds { |
| @@ -46,7 +59,7 @@ | |||
| 46 | 59 | ||
| 47 | &gpmi { | 60 | &gpmi { |
| 48 | pinctrl-names = "default"; | 61 | pinctrl-names = "default"; |
| 49 | pinctrl-0 = <&pinctrl_gpmi_nand_1>; | 62 | pinctrl-0 = <&pinctrl_gpmi_nand>; |
| 50 | status = "disabled"; /* gpmi nand conflicts with SD */ | 63 | status = "disabled"; /* gpmi nand conflicts with SD */ |
| 51 | }; | 64 | }; |
| 52 | 65 | ||
| @@ -54,28 +67,131 @@ | |||
| 54 | pinctrl-names = "default"; | 67 | pinctrl-names = "default"; |
| 55 | pinctrl-0 = <&pinctrl_hog>; | 68 | pinctrl-0 = <&pinctrl_hog>; |
| 56 | 69 | ||
| 57 | hog { | 70 | imx6q-arm2 { |
| 58 | pinctrl_hog: hoggrp { | 71 | pinctrl_hog: hoggrp { |
| 59 | fsl,pins = < | 72 | fsl,pins = < |
| 60 | MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000 | 73 | MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000 |
| 61 | >; | 74 | >; |
| 62 | }; | 75 | }; |
| 63 | }; | ||
| 64 | 76 | ||
| 65 | arm2 { | 77 | pinctrl_enet: enetgrp { |
| 66 | pinctrl_usdhc3_arm2: usdhc3grp-arm2 { | 78 | fsl,pins = < |
| 79 | MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 | ||
| 80 | MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 | ||
| 81 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 82 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 83 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 84 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 85 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 86 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 87 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 88 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 89 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 90 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 91 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 92 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 93 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 94 | MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 | ||
| 95 | >; | ||
| 96 | }; | ||
| 97 | |||
| 98 | pinctrl_gpmi_nand: gpminandgrp { | ||
| 99 | fsl,pins = < | ||
| 100 | MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 | ||
| 101 | MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 | ||
| 102 | MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 | ||
| 103 | MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 | ||
| 104 | MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 | ||
| 105 | MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 | ||
| 106 | MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 | ||
| 107 | MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 | ||
| 108 | MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 | ||
| 109 | MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 | ||
| 110 | MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 | ||
| 111 | MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 | ||
| 112 | MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 | ||
| 113 | MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 | ||
| 114 | MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 | ||
| 115 | MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 | ||
| 116 | MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 | ||
| 117 | >; | ||
| 118 | }; | ||
| 119 | |||
| 120 | pinctrl_uart2: uart2grp { | ||
| 121 | fsl,pins = < | ||
| 122 | MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 | ||
| 123 | MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 | ||
| 124 | MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 | ||
| 125 | MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 | ||
| 126 | >; | ||
| 127 | }; | ||
| 128 | |||
| 129 | pinctrl_uart4: uart4grp { | ||
| 130 | fsl,pins = < | ||
| 131 | MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 | ||
| 132 | MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 | ||
| 133 | >; | ||
| 134 | }; | ||
| 135 | |||
| 136 | pinctrl_usbotg: usbotggrp { | ||
| 137 | fsl,pins = < | ||
| 138 | MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 | ||
| 139 | >; | ||
| 140 | }; | ||
| 141 | |||
| 142 | pinctrl_usdhc3: usdhc3grp { | ||
| 143 | fsl,pins = < | ||
| 144 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 145 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 146 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 147 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 148 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 149 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 150 | MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 | ||
| 151 | MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 | ||
| 152 | MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 | ||
| 153 | MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 | ||
| 154 | >; | ||
| 155 | }; | ||
| 156 | |||
| 157 | pinctrl_usdhc3_cdwp: usdhc3cdwp { | ||
| 67 | fsl,pins = < | 158 | fsl,pins = < |
| 68 | MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 | 159 | MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 |
| 69 | MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 | 160 | MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 |
| 70 | >; | 161 | >; |
| 71 | }; | 162 | }; |
| 163 | |||
| 164 | pinctrl_usdhc4: usdhc4grp { | ||
| 165 | fsl,pins = < | ||
| 166 | MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 | ||
| 167 | MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 | ||
| 168 | MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 | ||
| 169 | MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 | ||
| 170 | MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 | ||
| 171 | MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 | ||
| 172 | MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 | ||
| 173 | MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 | ||
| 174 | MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 | ||
| 175 | MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 | ||
| 176 | >; | ||
| 177 | }; | ||
| 72 | }; | 178 | }; |
| 73 | }; | 179 | }; |
| 74 | 180 | ||
| 75 | &fec { | 181 | &fec { |
| 76 | pinctrl-names = "default"; | 182 | pinctrl-names = "default"; |
| 77 | pinctrl-0 = <&pinctrl_enet_2>; | 183 | pinctrl-0 = <&pinctrl_enet>; |
| 78 | phy-mode = "rgmii"; | 184 | phy-mode = "rgmii"; |
| 185 | interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, | ||
| 186 | <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; | ||
| 187 | status = "okay"; | ||
| 188 | }; | ||
| 189 | |||
| 190 | &usbotg { | ||
| 191 | vbus-supply = <®_usb_otg_vbus>; | ||
| 192 | pinctrl-names = "default"; | ||
| 193 | pinctrl-0 = <&pinctrl_usbotg>; | ||
| 194 | disable-over-current; | ||
| 79 | status = "okay"; | 195 | status = "okay"; |
| 80 | }; | 196 | }; |
| 81 | 197 | ||
| @@ -84,8 +200,8 @@ | |||
| 84 | wp-gpios = <&gpio6 14 0>; | 200 | wp-gpios = <&gpio6 14 0>; |
| 85 | vmmc-supply = <®_3p3v>; | 201 | vmmc-supply = <®_3p3v>; |
| 86 | pinctrl-names = "default"; | 202 | pinctrl-names = "default"; |
| 87 | pinctrl-0 = <&pinctrl_usdhc3_1 | 203 | pinctrl-0 = <&pinctrl_usdhc3 |
| 88 | &pinctrl_usdhc3_arm2>; | 204 | &pinctrl_usdhc3_cdwp>; |
| 89 | status = "okay"; | 205 | status = "okay"; |
| 90 | }; | 206 | }; |
| 91 | 207 | ||
| @@ -93,13 +209,13 @@ | |||
| 93 | non-removable; | 209 | non-removable; |
| 94 | vmmc-supply = <®_3p3v>; | 210 | vmmc-supply = <®_3p3v>; |
| 95 | pinctrl-names = "default"; | 211 | pinctrl-names = "default"; |
| 96 | pinctrl-0 = <&pinctrl_usdhc4_1>; | 212 | pinctrl-0 = <&pinctrl_usdhc4>; |
| 97 | status = "okay"; | 213 | status = "okay"; |
| 98 | }; | 214 | }; |
| 99 | 215 | ||
| 100 | &uart2 { | 216 | &uart2 { |
| 101 | pinctrl-names = "default"; | 217 | pinctrl-names = "default"; |
| 102 | pinctrl-0 = <&pinctrl_uart2_2>; | 218 | pinctrl-0 = <&pinctrl_uart2>; |
| 103 | fsl,dte-mode; | 219 | fsl,dte-mode; |
| 104 | fsl,uart-has-rtscts; | 220 | fsl,uart-has-rtscts; |
| 105 | status = "okay"; | 221 | status = "okay"; |
| @@ -107,6 +223,6 @@ | |||
| 107 | 223 | ||
| 108 | &uart4 { | 224 | &uart4 { |
| 109 | pinctrl-names = "default"; | 225 | pinctrl-names = "default"; |
| 110 | pinctrl-0 = <&pinctrl_uart4_1>; | 226 | pinctrl-0 = <&pinctrl_uart4>; |
| 111 | status = "okay"; | 227 | status = "okay"; |
| 112 | }; | 228 | }; |
diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts new file mode 100644 index 000000000000..99b46f8030ad --- /dev/null +++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts | |||
| @@ -0,0 +1,107 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 CompuLab Ltd. | ||
| 3 | * | ||
| 4 | * Author: Valentin Raevsky <valentin@compulab.co.il> | ||
| 5 | * | ||
| 6 | * The code contained herein is licensed under the GNU General Public | ||
| 7 | * License. You may obtain a copy of the GNU General Public License | ||
| 8 | * Version 2 or later at the following locations: | ||
| 9 | * | ||
| 10 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 11 | * http://www.gnu.org/copyleft/gpl.html | ||
| 12 | */ | ||
| 13 | |||
| 14 | /dts-v1/; | ||
| 15 | #include "imx6q.dtsi" | ||
| 16 | |||
| 17 | / { | ||
| 18 | model = "CompuLab CM-FX6"; | ||
| 19 | compatible = "compulab,cm-fx6", "fsl,imx6q"; | ||
| 20 | |||
| 21 | memory { | ||
| 22 | reg = <0x10000000 0x80000000>; | ||
| 23 | }; | ||
| 24 | |||
| 25 | leds { | ||
| 26 | compatible = "gpio-leds"; | ||
| 27 | |||
| 28 | heartbeat-led { | ||
| 29 | label = "Heartbeat"; | ||
| 30 | gpios = <&gpio2 31 0>; | ||
| 31 | linux,default-trigger = "heartbeat"; | ||
| 32 | }; | ||
| 33 | }; | ||
| 34 | }; | ||
| 35 | |||
| 36 | &fec { | ||
| 37 | pinctrl-names = "default"; | ||
| 38 | pinctrl-0 = <&pinctrl_enet>; | ||
| 39 | phy-mode = "rgmii"; | ||
| 40 | status = "okay"; | ||
| 41 | }; | ||
| 42 | |||
| 43 | &gpmi { | ||
| 44 | pinctrl-names = "default"; | ||
| 45 | pinctrl-0 = <&pinctrl_gpmi_nand>; | ||
| 46 | status = "okay"; | ||
| 47 | }; | ||
| 48 | |||
| 49 | &iomuxc { | ||
| 50 | imx6q-cm-fx6 { | ||
| 51 | pinctrl_enet: enetgrp { | ||
| 52 | fsl,pins = < | ||
| 53 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 54 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 55 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 56 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 57 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 58 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 59 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 60 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 61 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 62 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 63 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 64 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 65 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 66 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | ||
| 67 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | ||
| 68 | MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 | ||
| 69 | >; | ||
| 70 | }; | ||
| 71 | |||
| 72 | pinctrl_gpmi_nand: gpminandgrp { | ||
| 73 | fsl,pins = < | ||
| 74 | MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 | ||
| 75 | MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 | ||
| 76 | MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 | ||
| 77 | MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 | ||
| 78 | MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 | ||
| 79 | MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 | ||
| 80 | MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 | ||
| 81 | MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 | ||
| 82 | MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 | ||
| 83 | MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 | ||
| 84 | MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 | ||
| 85 | MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 | ||
| 86 | MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 | ||
| 87 | MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 | ||
| 88 | MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 | ||
| 89 | MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 | ||
| 90 | MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 | ||
| 91 | >; | ||
| 92 | }; | ||
| 93 | |||
| 94 | pinctrl_uart4: uart4grp { | ||
| 95 | fsl,pins = < | ||
| 96 | MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 | ||
| 97 | MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 | ||
| 98 | >; | ||
| 99 | }; | ||
| 100 | }; | ||
| 101 | }; | ||
| 102 | |||
| 103 | &uart4 { | ||
| 104 | pinctrl-names = "default"; | ||
| 105 | pinctrl-0 = <&pinctrl_uart4>; | ||
| 106 | status = "okay"; | ||
| 107 | }; | ||
diff --git a/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts b/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts new file mode 100644 index 000000000000..fd0ad9a8866c --- /dev/null +++ b/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts | |||
| @@ -0,0 +1,23 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Sascha Hauer <s.hauer@pengutronix.de> | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __DTS_V1__ | ||
| 13 | #define __DTS_V1__ | ||
| 14 | /dts-v1/; | ||
| 15 | #endif | ||
| 16 | |||
| 17 | #include "imx6q.dtsi" | ||
| 18 | #include "imx6qdl-dfi-fs700-m60.dtsi" | ||
| 19 | |||
| 20 | / { | ||
| 21 | model = "DFI FS700-M60-6QD i.MX6qd Q7 Board"; | ||
| 22 | compatible = "dfi,fs700-m60-6qd", "dfi,fs700e-m60", "fsl,imx6q"; | ||
| 23 | }; | ||
diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts new file mode 100644 index 000000000000..a63bbb3d46bb --- /dev/null +++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | |||
| @@ -0,0 +1,372 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Data Modul AG | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | |||
| 14 | #include <dt-bindings/gpio/gpio.h> | ||
| 15 | #include "imx6q.dtsi" | ||
| 16 | |||
| 17 | / { | ||
| 18 | model = "Data Modul eDM-QMX6 Board"; | ||
| 19 | compatible = "dmo,imx6q-edmqmx6", "fsl,imx6q"; | ||
| 20 | |||
| 21 | aliases { | ||
| 22 | gpio7 = &stmpe_gpio; | ||
| 23 | }; | ||
| 24 | |||
| 25 | memory { | ||
| 26 | reg = <0x10000000 0x80000000>; | ||
| 27 | }; | ||
| 28 | |||
| 29 | regulators { | ||
| 30 | compatible = "simple-bus"; | ||
| 31 | #address-cells = <1>; | ||
| 32 | #size-cells = <0>; | ||
| 33 | |||
| 34 | reg_3p3v: regulator@0 { | ||
| 35 | compatible = "regulator-fixed"; | ||
| 36 | reg = <0>; | ||
| 37 | regulator-name = "3P3V"; | ||
| 38 | regulator-min-microvolt = <3300000>; | ||
| 39 | regulator-max-microvolt = <3300000>; | ||
| 40 | regulator-always-on; | ||
| 41 | }; | ||
| 42 | |||
| 43 | reg_usb_otg_vbus: regulator@1 { | ||
| 44 | compatible = "regulator-fixed"; | ||
| 45 | reg = <1>; | ||
| 46 | regulator-name = "usb_otg_vbus"; | ||
| 47 | regulator-min-microvolt = <5000000>; | ||
| 48 | regulator-max-microvolt = <5000000>; | ||
| 49 | gpio = <&gpio7 12 0>; | ||
| 50 | }; | ||
| 51 | |||
| 52 | reg_usb_host1: regulator@2 { | ||
| 53 | compatible = "regulator-fixed"; | ||
| 54 | reg = <2>; | ||
| 55 | regulator-name = "usb_host1_en"; | ||
| 56 | regulator-min-microvolt = <3300000>; | ||
| 57 | regulator-max-microvolt = <3300000>; | ||
| 58 | gpio = <&gpio3 31 0>; | ||
| 59 | enable-active-high; | ||
| 60 | }; | ||
| 61 | }; | ||
| 62 | |||
| 63 | gpio-leds { | ||
| 64 | compatible = "gpio-leds"; | ||
| 65 | |||
| 66 | led-blue { | ||
| 67 | label = "blue"; | ||
| 68 | gpios = <&stmpe_gpio 8 GPIO_ACTIVE_HIGH>; | ||
| 69 | linux,default-trigger = "heartbeat"; | ||
| 70 | }; | ||
| 71 | |||
| 72 | led-green { | ||
| 73 | label = "green"; | ||
| 74 | gpios = <&stmpe_gpio 9 GPIO_ACTIVE_HIGH>; | ||
| 75 | }; | ||
| 76 | |||
| 77 | led-pink { | ||
| 78 | label = "pink"; | ||
| 79 | gpios = <&stmpe_gpio 10 GPIO_ACTIVE_HIGH>; | ||
| 80 | }; | ||
| 81 | |||
| 82 | led-red { | ||
| 83 | label = "red"; | ||
| 84 | gpios = <&stmpe_gpio 11 GPIO_ACTIVE_HIGH>; | ||
| 85 | }; | ||
| 86 | }; | ||
| 87 | }; | ||
| 88 | |||
| 89 | &fec { | ||
| 90 | pinctrl-names = "default"; | ||
| 91 | pinctrl-0 = <&pinctrl_enet>; | ||
| 92 | phy-mode = "rgmii"; | ||
| 93 | phy-reset-gpios = <&gpio3 23 0>; | ||
| 94 | phy-supply = <&vgen2_1v2_eth>; | ||
| 95 | status = "okay"; | ||
| 96 | }; | ||
| 97 | |||
| 98 | &i2c2 { | ||
| 99 | clock-frequency = <100000>; | ||
| 100 | pinctrl-names = "default"; | ||
| 101 | pinctrl-0 = <&pinctrl_i2c2 | ||
| 102 | &pinctrl_stmpe>; | ||
| 103 | status = "okay"; | ||
| 104 | |||
| 105 | pmic: pfuze100@08 { | ||
| 106 | compatible = "fsl,pfuze100"; | ||
| 107 | reg = <0x08>; | ||
| 108 | interrupt-parent = <&gpio3>; | ||
| 109 | interrupts = <20 8>; | ||
| 110 | |||
| 111 | regulators { | ||
| 112 | sw1a_reg: sw1ab { | ||
| 113 | regulator-min-microvolt = <300000>; | ||
| 114 | regulator-max-microvolt = <1875000>; | ||
| 115 | regulator-boot-on; | ||
| 116 | regulator-always-on; | ||
| 117 | }; | ||
| 118 | |||
| 119 | sw1c_reg: sw1c { | ||
| 120 | regulator-min-microvolt = <300000>; | ||
| 121 | regulator-max-microvolt = <1875000>; | ||
| 122 | regulator-boot-on; | ||
| 123 | regulator-always-on; | ||
| 124 | }; | ||
| 125 | |||
| 126 | sw2_reg: sw2 { | ||
| 127 | regulator-min-microvolt = <800000>; | ||
| 128 | regulator-max-microvolt = <3300000>; | ||
| 129 | regulator-boot-on; | ||
| 130 | regulator-always-on; | ||
| 131 | }; | ||
| 132 | |||
| 133 | sw3a_reg: sw3a { | ||
| 134 | regulator-min-microvolt = <400000>; | ||
| 135 | regulator-max-microvolt = <1975000>; | ||
| 136 | regulator-boot-on; | ||
| 137 | regulator-always-on; | ||
| 138 | }; | ||
| 139 | |||
| 140 | sw3b_reg: sw3b { | ||
| 141 | regulator-min-microvolt = <400000>; | ||
| 142 | regulator-max-microvolt = <1975000>; | ||
| 143 | regulator-boot-on; | ||
| 144 | regulator-always-on; | ||
| 145 | }; | ||
| 146 | |||
| 147 | sw4_reg: sw4 { | ||
| 148 | regulator-min-microvolt = <400000>; | ||
| 149 | regulator-max-microvolt = <1975000>; | ||
| 150 | regulator-always-on; | ||
| 151 | }; | ||
| 152 | |||
| 153 | swbst_reg: swbst { | ||
| 154 | regulator-min-microvolt = <5000000>; | ||
| 155 | regulator-max-microvolt = <5150000>; | ||
| 156 | regulator-always-on; | ||
| 157 | }; | ||
| 158 | |||
| 159 | snvs_reg: vsnvs { | ||
| 160 | regulator-min-microvolt = <1000000>; | ||
| 161 | regulator-max-microvolt = <3000000>; | ||
| 162 | regulator-boot-on; | ||
| 163 | regulator-always-on; | ||
| 164 | }; | ||
| 165 | |||
| 166 | vref_reg: vrefddr { | ||
| 167 | regulator-boot-on; | ||
| 168 | regulator-always-on; | ||
| 169 | }; | ||
| 170 | |||
| 171 | vgen1_reg: vgen1 { | ||
| 172 | regulator-min-microvolt = <800000>; | ||
| 173 | regulator-max-microvolt = <1550000>; | ||
| 174 | }; | ||
| 175 | |||
| 176 | vgen2_1v2_eth: vgen2 { | ||
| 177 | regulator-min-microvolt = <800000>; | ||
| 178 | regulator-max-microvolt = <1550000>; | ||
| 179 | }; | ||
| 180 | |||
| 181 | vdd_high_in: vgen3 { | ||
| 182 | regulator-min-microvolt = <1800000>; | ||
| 183 | regulator-max-microvolt = <3300000>; | ||
| 184 | regulator-boot-on; | ||
| 185 | regulator-always-on; | ||
| 186 | }; | ||
| 187 | |||
| 188 | vgen4_reg: vgen4 { | ||
| 189 | regulator-min-microvolt = <1800000>; | ||
| 190 | regulator-max-microvolt = <3300000>; | ||
| 191 | regulator-always-on; | ||
| 192 | }; | ||
| 193 | |||
| 194 | vgen5_reg: vgen5 { | ||
| 195 | regulator-min-microvolt = <1800000>; | ||
| 196 | regulator-max-microvolt = <3300000>; | ||
| 197 | regulator-always-on; | ||
| 198 | }; | ||
| 199 | |||
| 200 | vgen6_reg: vgen6 { | ||
| 201 | regulator-min-microvolt = <1800000>; | ||
| 202 | regulator-max-microvolt = <3300000>; | ||
| 203 | regulator-always-on; | ||
| 204 | }; | ||
| 205 | }; | ||
| 206 | }; | ||
| 207 | |||
| 208 | stmpe: stmpe1601@40 { | ||
| 209 | compatible = "st,stmpe1601"; | ||
| 210 | reg = <0x40>; | ||
| 211 | interrupts = <30 0>; | ||
| 212 | interrupt-parent = <&gpio3>; | ||
| 213 | |||
| 214 | stmpe_gpio: stmpe_gpio { | ||
| 215 | #gpio-cells = <2>; | ||
| 216 | compatible = "st,stmpe-gpio"; | ||
| 217 | }; | ||
| 218 | }; | ||
| 219 | |||
| 220 | temp1: ad7414@4c { | ||
| 221 | compatible = "ad,ad7414"; | ||
| 222 | reg = <0x4c>; | ||
| 223 | }; | ||
| 224 | |||
| 225 | temp2: ad7414@4d { | ||
| 226 | compatible = "ad,ad7414"; | ||
| 227 | reg = <0x4d>; | ||
| 228 | }; | ||
| 229 | |||
| 230 | rtc: m41t62@68 { | ||
| 231 | compatible = "stm,m41t62"; | ||
| 232 | reg = <0x68>; | ||
| 233 | }; | ||
| 234 | }; | ||
| 235 | |||
| 236 | &iomuxc { | ||
| 237 | pinctrl-names = "default"; | ||
| 238 | pinctrl-0 = <&pinctrl_hog>; | ||
| 239 | |||
| 240 | imx6q-dmo-edmqmx6 { | ||
| 241 | pinctrl_hog: hoggrp { | ||
| 242 | fsl,pins = < | ||
| 243 | MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x80000000 | ||
| 244 | MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x80000000 | ||
| 245 | >; | ||
| 246 | }; | ||
| 247 | |||
| 248 | pinctrl_enet: enetgrp { | ||
| 249 | fsl,pins = < | ||
| 250 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 251 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 252 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 253 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 254 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 255 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 256 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 257 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 258 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 259 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 260 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 261 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 262 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 263 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | ||
| 264 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | ||
| 265 | MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 | ||
| 266 | >; | ||
| 267 | }; | ||
| 268 | |||
| 269 | pinctrl_i2c2: i2c2grp { | ||
| 270 | fsl,pins = < | ||
| 271 | MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 | ||
| 272 | MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 | ||
| 273 | >; | ||
| 274 | }; | ||
| 275 | |||
| 276 | pinctrl_stmpe: stmpegrp { | ||
| 277 | fsl,pins = <MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x80000000>; | ||
| 278 | }; | ||
| 279 | |||
| 280 | pinctrl_uart1: uart1grp { | ||
| 281 | fsl,pins = < | ||
| 282 | MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 | ||
| 283 | MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 | ||
| 284 | >; | ||
| 285 | }; | ||
| 286 | |||
| 287 | pinctrl_uart2: uart2grp { | ||
| 288 | fsl,pins = < | ||
| 289 | MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 | ||
| 290 | MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 | ||
| 291 | >; | ||
| 292 | }; | ||
| 293 | |||
| 294 | pinctrl_usbotg: usbotggrp { | ||
| 295 | fsl,pins = < | ||
| 296 | MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 | ||
| 297 | >; | ||
| 298 | }; | ||
| 299 | |||
| 300 | pinctrl_usdhc3: usdhc3grp { | ||
| 301 | fsl,pins = < | ||
| 302 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 303 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 304 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 305 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 306 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 307 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 308 | >; | ||
| 309 | }; | ||
| 310 | |||
| 311 | pinctrl_usdhc4: usdhc4grp { | ||
| 312 | fsl,pins = < | ||
| 313 | MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 | ||
| 314 | MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 | ||
| 315 | MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 | ||
| 316 | MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 | ||
| 317 | MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 | ||
| 318 | MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 | ||
| 319 | MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 | ||
| 320 | MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 | ||
| 321 | MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 | ||
| 322 | MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 | ||
| 323 | >; | ||
| 324 | }; | ||
| 325 | }; | ||
| 326 | }; | ||
| 327 | |||
| 328 | &sata { | ||
| 329 | status = "okay"; | ||
| 330 | }; | ||
| 331 | |||
| 332 | &uart1 { | ||
| 333 | pinctrl-names = "default"; | ||
| 334 | pinctrl-0 = <&pinctrl_uart1>; | ||
| 335 | status = "okay"; | ||
| 336 | }; | ||
| 337 | |||
| 338 | &uart2 { | ||
| 339 | pinctrl-names = "default"; | ||
| 340 | pinctrl-0 = <&pinctrl_uart2>; | ||
| 341 | status = "okay"; | ||
| 342 | }; | ||
| 343 | |||
| 344 | &usbh1 { | ||
| 345 | vbus-supply = <®_usb_host1>; | ||
| 346 | disable-over-current; | ||
| 347 | status = "okay"; | ||
| 348 | }; | ||
| 349 | |||
| 350 | &usbotg { | ||
| 351 | vbus-supply = <®_usb_otg_vbus>; | ||
| 352 | pinctrl-names = "default"; | ||
| 353 | pinctrl-0 = <&pinctrl_usbotg>; | ||
| 354 | disable-over-current; | ||
| 355 | status = "okay"; | ||
| 356 | }; | ||
| 357 | |||
| 358 | &usdhc3 { | ||
| 359 | pinctrl-names = "default"; | ||
| 360 | pinctrl-0 = <&pinctrl_usdhc3>; | ||
| 361 | vmmc-supply = <®_3p3v>; | ||
| 362 | status = "okay"; | ||
| 363 | }; | ||
| 364 | |||
| 365 | &usdhc4 { | ||
| 366 | pinctrl-names = "default"; | ||
| 367 | pinctrl-0 = <&pinctrl_usdhc4>; | ||
| 368 | vmmc-supply = <®_3p3v>; | ||
| 369 | non-removable; | ||
| 370 | bus-width = <8>; | ||
| 371 | status = "okay"; | ||
| 372 | }; | ||
diff --git a/arch/arm/boot/dts/imx6q-gk802.dts b/arch/arm/boot/dts/imx6q-gk802.dts new file mode 100644 index 000000000000..4a9b4dc9afc0 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-gk802.dts | |||
| @@ -0,0 +1,171 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2013 Philipp Zabel | ||
| 3 | * | ||
| 4 | * This file is licensed under the terms of the GNU General Public License | ||
| 5 | * version 2. This program is licensed "as is" without any warranty of any | ||
| 6 | * kind, whether express or implied. | ||
| 7 | */ | ||
| 8 | |||
| 9 | /dts-v1/; | ||
| 10 | #include "imx6q.dtsi" | ||
| 11 | |||
| 12 | / { | ||
| 13 | model = "Zealz GK802"; | ||
| 14 | compatible = "zealz,imx6q-gk802", "fsl,imx6q"; | ||
| 15 | |||
| 16 | chosen { | ||
| 17 | linux,stdout-path = &uart4; | ||
| 18 | }; | ||
| 19 | |||
| 20 | memory { | ||
| 21 | reg = <0x10000000 0x40000000>; | ||
| 22 | }; | ||
| 23 | |||
| 24 | regulators { | ||
| 25 | compatible = "simple-bus"; | ||
| 26 | #address-cells = <1>; | ||
| 27 | #size-cells = <0>; | ||
| 28 | |||
| 29 | reg_3p3v: regulator@0 { | ||
| 30 | compatible = "regulator-fixed"; | ||
| 31 | reg = <0>; | ||
| 32 | regulator-name = "3P3V"; | ||
| 33 | regulator-min-microvolt = <3300000>; | ||
| 34 | regulator-max-microvolt = <3300000>; | ||
| 35 | regulator-always-on; | ||
| 36 | }; | ||
| 37 | }; | ||
| 38 | |||
| 39 | gpio-keys { | ||
| 40 | compatible = "gpio-keys"; | ||
| 41 | |||
| 42 | recovery-button { | ||
| 43 | label = "recovery"; | ||
| 44 | gpios = <&gpio3 16 1>; | ||
| 45 | linux,code = <0x198>; /* KEY_RESTART */ | ||
| 46 | gpio-key,wakeup; | ||
| 47 | }; | ||
| 48 | }; | ||
| 49 | }; | ||
| 50 | |||
| 51 | /* Internal I2C */ | ||
| 52 | &i2c2 { | ||
| 53 | pinctrl-names = "default"; | ||
| 54 | pinctrl-0 = <&pinctrl_i2c2>; | ||
| 55 | clock-frequency = <100000>; | ||
| 56 | status = "okay"; | ||
| 57 | |||
| 58 | /* SDMC DM2016 1024 bit EEPROM + 128 bit OTP */ | ||
| 59 | eeprom: dm2016@51 { | ||
| 60 | compatible = "sdmc,dm2016"; | ||
| 61 | reg = <0x51>; | ||
| 62 | }; | ||
| 63 | }; | ||
| 64 | |||
| 65 | /* External I2C via HDMI */ | ||
| 66 | &i2c3 { | ||
| 67 | pinctrl-names = "default"; | ||
| 68 | pinctrl-0 = <&pinctrl_i2c3>; | ||
| 69 | clock-frequency = <100000>; | ||
| 70 | status = "okay"; | ||
| 71 | }; | ||
| 72 | |||
| 73 | &iomuxc { | ||
| 74 | pinctrl-names = "default"; | ||
| 75 | pinctrl-0 = <&pinctrl_hog>; | ||
| 76 | |||
| 77 | imx6q-gk802 { | ||
| 78 | pinctrl_hog: hoggrp { | ||
| 79 | fsl,pins = < | ||
| 80 | /* Recovery button, active-low */ | ||
| 81 | MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x100b1 | ||
| 82 | /* RTL8192CU enable GPIO, active-low */ | ||
| 83 | MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 | ||
| 84 | >; | ||
| 85 | }; | ||
| 86 | |||
| 87 | pinctrl_i2c2: i2c2grp { | ||
| 88 | fsl,pins = < | ||
| 89 | MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 | ||
| 90 | MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 | ||
| 91 | >; | ||
| 92 | }; | ||
| 93 | |||
| 94 | pinctrl_i2c3: i2c3grp { | ||
| 95 | fsl,pins = < | ||
| 96 | MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 | ||
| 97 | MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 | ||
| 98 | >; | ||
| 99 | }; | ||
| 100 | |||
| 101 | pinctrl_uart4: uart4grp { | ||
| 102 | fsl,pins = < | ||
| 103 | MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 | ||
| 104 | MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 | ||
| 105 | >; | ||
| 106 | }; | ||
| 107 | |||
| 108 | pinctrl_usdhc3: usdhc3grp { | ||
| 109 | fsl,pins = < | ||
| 110 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 111 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 112 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 113 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 114 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 115 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 116 | >; | ||
| 117 | }; | ||
| 118 | |||
| 119 | pinctrl_usdhc4: usdhc4grp { | ||
| 120 | fsl,pins = < | ||
| 121 | MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 | ||
| 122 | MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 | ||
| 123 | MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 | ||
| 124 | MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 | ||
| 125 | MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 | ||
| 126 | MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 | ||
| 127 | >; | ||
| 128 | }; | ||
| 129 | }; | ||
| 130 | }; | ||
| 131 | |||
| 132 | &uart2 { | ||
| 133 | status = "okay"; | ||
| 134 | }; | ||
| 135 | |||
| 136 | &uart4 { | ||
| 137 | pinctrl-names = "default"; | ||
| 138 | pinctrl-0 = <&pinctrl_uart4>; | ||
| 139 | status = "okay"; | ||
| 140 | }; | ||
| 141 | |||
| 142 | /* External USB-A port (USBOTG) */ | ||
| 143 | &usbotg { | ||
| 144 | disable-over-current; | ||
| 145 | status = "okay"; | ||
| 146 | }; | ||
| 147 | |||
| 148 | /* Internal USB port (USBH1), connected to RTL8192CU */ | ||
| 149 | &usbh1 { | ||
| 150 | disable-over-current; | ||
| 151 | status = "okay"; | ||
| 152 | }; | ||
| 153 | |||
| 154 | /* External microSD */ | ||
| 155 | &usdhc3 { | ||
| 156 | pinctrl-names = "default"; | ||
| 157 | pinctrl-0 = <&pinctrl_usdhc3>; | ||
| 158 | bus-width = <4>; | ||
| 159 | cd-gpios = <&gpio6 11 0>; | ||
| 160 | vmmc-supply = <®_3p3v>; | ||
| 161 | status = "okay"; | ||
| 162 | }; | ||
| 163 | |||
| 164 | /* Internal microSD */ | ||
| 165 | &usdhc4 { | ||
| 166 | pinctrl-names = "default"; | ||
| 167 | pinctrl-0 = <&pinctrl_usdhc4>; | ||
| 168 | bus-width = <4>; | ||
| 169 | vmmc-supply = <®_3p3v>; | ||
| 170 | status = "okay"; | ||
| 171 | }; | ||
diff --git a/arch/arm/boot/dts/imx6q-gw51xx.dts b/arch/arm/boot/dts/imx6q-gw51xx.dts new file mode 100644 index 000000000000..af4929aee075 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-gw51xx.dts | |||
| @@ -0,0 +1,19 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Gateworks Corporation | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | #include "imx6q.dtsi" | ||
| 14 | #include "imx6qdl-gw54xx.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Gateworks Ventana i.MX6 Quad GW51XX"; | ||
| 18 | compatible = "gw,imx6q-gw51xx", "gw,ventana", "fsl,imx6q"; | ||
| 19 | }; | ||
diff --git a/arch/arm/boot/dts/imx6q-gw52xx.dts b/arch/arm/boot/dts/imx6q-gw52xx.dts new file mode 100644 index 000000000000..5f71ddbc7f05 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-gw52xx.dts | |||
| @@ -0,0 +1,23 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Gateworks Corporation | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | #include "imx6q.dtsi" | ||
| 14 | #include "imx6qdl-gw52xx.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Gateworks Ventana i.MX6 Quad GW52XX"; | ||
| 18 | compatible = "gw,imx6q-gw52xx", "gw,ventana", "fsl,imx6q"; | ||
| 19 | }; | ||
| 20 | |||
| 21 | &sata { | ||
| 22 | status = "okay"; | ||
| 23 | }; | ||
diff --git a/arch/arm/boot/dts/imx6q-gw53xx.dts b/arch/arm/boot/dts/imx6q-gw53xx.dts new file mode 100644 index 000000000000..360c316b4740 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-gw53xx.dts | |||
| @@ -0,0 +1,23 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Gateworks Corporation | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | #include "imx6q.dtsi" | ||
| 14 | #include "imx6qdl-gw53xx.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Gateworks Ventana i.MX6 Quad GW53XX"; | ||
| 18 | compatible = "gw,imx6q-gw53xx", "gw,ventana", "fsl,imx6q"; | ||
| 19 | }; | ||
| 20 | |||
| 21 | &sata { | ||
| 22 | status = "okay"; | ||
| 23 | }; | ||
diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts new file mode 100644 index 000000000000..902f98310481 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts | |||
| @@ -0,0 +1,546 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Gateworks Corporation | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | #include "imx6q.dtsi" | ||
| 14 | |||
| 15 | / { | ||
| 16 | model = "Gateworks Ventana GW5400-A"; | ||
| 17 | compatible = "gw,imx6q-gw5400-a", "gw,ventana", "fsl,imx6q"; | ||
| 18 | |||
| 19 | /* these are used by bootloader for disabling nodes */ | ||
| 20 | aliases { | ||
| 21 | ethernet0 = &fec; | ||
| 22 | ethernet1 = ð1; | ||
| 23 | i2c0 = &i2c1; | ||
| 24 | i2c1 = &i2c2; | ||
| 25 | i2c2 = &i2c3; | ||
| 26 | led0 = &led0; | ||
| 27 | led1 = &led1; | ||
| 28 | led2 = &led2; | ||
| 29 | sky2 = ð1; | ||
| 30 | ssi0 = &ssi1; | ||
| 31 | spi0 = &ecspi1; | ||
| 32 | usb0 = &usbh1; | ||
| 33 | usb1 = &usbotg; | ||
| 34 | usdhc2 = &usdhc3; | ||
| 35 | }; | ||
| 36 | |||
| 37 | chosen { | ||
| 38 | bootargs = "console=ttymxc1,115200"; | ||
| 39 | }; | ||
| 40 | |||
| 41 | leds { | ||
| 42 | compatible = "gpio-leds"; | ||
| 43 | |||
| 44 | led0: user1 { | ||
| 45 | label = "user1"; | ||
| 46 | gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ | ||
| 47 | default-state = "on"; | ||
| 48 | linux,default-trigger = "heartbeat"; | ||
| 49 | }; | ||
| 50 | |||
| 51 | led1: user2 { | ||
| 52 | label = "user2"; | ||
| 53 | gpios = <&gpio4 10 0>; /* 106 -> MX6_PANLEDR */ | ||
| 54 | default-state = "off"; | ||
| 55 | }; | ||
| 56 | |||
| 57 | led2: user3 { | ||
| 58 | label = "user3"; | ||
| 59 | gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */ | ||
| 60 | default-state = "off"; | ||
| 61 | }; | ||
| 62 | }; | ||
| 63 | |||
| 64 | memory { | ||
| 65 | reg = <0x10000000 0x40000000>; | ||
| 66 | }; | ||
| 67 | |||
| 68 | pps { | ||
| 69 | compatible = "pps-gpio"; | ||
| 70 | gpios = <&gpio1 5 0>; | ||
| 71 | status = "okay"; | ||
| 72 | }; | ||
| 73 | |||
| 74 | regulators { | ||
| 75 | compatible = "simple-bus"; | ||
| 76 | #address-cells = <1>; | ||
| 77 | #size-cells = <0>; | ||
| 78 | |||
| 79 | reg_1p0v: regulator@0 { | ||
| 80 | compatible = "regulator-fixed"; | ||
| 81 | reg = <0>; | ||
| 82 | regulator-name = "1P0V"; | ||
| 83 | regulator-min-microvolt = <1000000>; | ||
| 84 | regulator-max-microvolt = <1000000>; | ||
| 85 | regulator-always-on; | ||
| 86 | }; | ||
| 87 | |||
| 88 | reg_3p3v: regulator@1 { | ||
| 89 | compatible = "regulator-fixed"; | ||
| 90 | reg = <1>; | ||
| 91 | regulator-name = "3P3V"; | ||
| 92 | regulator-min-microvolt = <3300000>; | ||
| 93 | regulator-max-microvolt = <3300000>; | ||
| 94 | regulator-always-on; | ||
| 95 | }; | ||
| 96 | |||
| 97 | reg_usb_h1_vbus: regulator@2 { | ||
| 98 | compatible = "regulator-fixed"; | ||
| 99 | reg = <2>; | ||
| 100 | regulator-name = "usb_h1_vbus"; | ||
| 101 | regulator-min-microvolt = <5000000>; | ||
| 102 | regulator-max-microvolt = <5000000>; | ||
| 103 | regulator-always-on; | ||
| 104 | }; | ||
| 105 | |||
| 106 | reg_usb_otg_vbus: regulator@3 { | ||
| 107 | compatible = "regulator-fixed"; | ||
| 108 | reg = <3>; | ||
| 109 | regulator-name = "usb_otg_vbus"; | ||
| 110 | regulator-min-microvolt = <5000000>; | ||
| 111 | regulator-max-microvolt = <5000000>; | ||
| 112 | gpio = <&gpio3 22 0>; | ||
| 113 | enable-active-high; | ||
| 114 | }; | ||
| 115 | }; | ||
| 116 | |||
| 117 | sound { | ||
| 118 | compatible = "fsl,imx6q-sabrelite-sgtl5000", | ||
| 119 | "fsl,imx-audio-sgtl5000"; | ||
| 120 | model = "imx6q-sabrelite-sgtl5000"; | ||
| 121 | ssi-controller = <&ssi1>; | ||
| 122 | audio-codec = <&codec>; | ||
| 123 | audio-routing = | ||
| 124 | "MIC_IN", "Mic Jack", | ||
| 125 | "Mic Jack", "Mic Bias", | ||
| 126 | "Headphone Jack", "HP_OUT"; | ||
| 127 | mux-int-port = <1>; | ||
| 128 | mux-ext-port = <4>; | ||
| 129 | }; | ||
| 130 | }; | ||
| 131 | |||
| 132 | &audmux { | ||
| 133 | pinctrl-names = "default"; | ||
| 134 | pinctrl-0 = <&pinctrl_audmux>; | ||
| 135 | status = "okay"; | ||
| 136 | }; | ||
| 137 | |||
| 138 | &ecspi1 { | ||
| 139 | fsl,spi-num-chipselects = <1>; | ||
| 140 | cs-gpios = <&gpio3 19 0>; | ||
| 141 | pinctrl-names = "default"; | ||
| 142 | pinctrl-0 = <&pinctrl_ecspi1>; | ||
| 143 | status = "okay"; | ||
| 144 | |||
| 145 | flash: m25p80@0 { | ||
| 146 | compatible = "sst,w25q256"; | ||
| 147 | spi-max-frequency = <30000000>; | ||
| 148 | reg = <0>; | ||
| 149 | }; | ||
| 150 | }; | ||
| 151 | |||
| 152 | &fec { | ||
| 153 | pinctrl-names = "default"; | ||
| 154 | pinctrl-0 = <&pinctrl_enet>; | ||
| 155 | phy-mode = "rgmii"; | ||
| 156 | phy-reset-gpios = <&gpio1 30 0>; | ||
| 157 | status = "okay"; | ||
| 158 | }; | ||
| 159 | |||
| 160 | &i2c1 { | ||
| 161 | clock-frequency = <100000>; | ||
| 162 | pinctrl-names = "default"; | ||
| 163 | pinctrl-0 = <&pinctrl_i2c1>; | ||
| 164 | status = "okay"; | ||
| 165 | |||
| 166 | eeprom1: eeprom@50 { | ||
| 167 | compatible = "atmel,24c02"; | ||
| 168 | reg = <0x50>; | ||
| 169 | pagesize = <16>; | ||
| 170 | }; | ||
| 171 | |||
| 172 | eeprom2: eeprom@51 { | ||
| 173 | compatible = "atmel,24c02"; | ||
| 174 | reg = <0x51>; | ||
| 175 | pagesize = <16>; | ||
| 176 | }; | ||
| 177 | |||
| 178 | eeprom3: eeprom@52 { | ||
| 179 | compatible = "atmel,24c02"; | ||
| 180 | reg = <0x52>; | ||
| 181 | pagesize = <16>; | ||
| 182 | }; | ||
| 183 | |||
| 184 | eeprom4: eeprom@53 { | ||
| 185 | compatible = "atmel,24c02"; | ||
| 186 | reg = <0x53>; | ||
| 187 | pagesize = <16>; | ||
| 188 | }; | ||
| 189 | |||
| 190 | gpio: pca9555@23 { | ||
| 191 | compatible = "nxp,pca9555"; | ||
| 192 | reg = <0x23>; | ||
| 193 | gpio-controller; | ||
| 194 | #gpio-cells = <2>; | ||
| 195 | }; | ||
| 196 | |||
| 197 | hwmon: gsc@29 { | ||
| 198 | compatible = "gw,gsp"; | ||
| 199 | reg = <0x29>; | ||
| 200 | }; | ||
| 201 | |||
| 202 | rtc: ds1672@68 { | ||
| 203 | compatible = "dallas,ds1672"; | ||
| 204 | reg = <0x68>; | ||
| 205 | }; | ||
| 206 | }; | ||
| 207 | |||
| 208 | &i2c2 { | ||
| 209 | clock-frequency = <100000>; | ||
| 210 | pinctrl-names = "default"; | ||
| 211 | pinctrl-0 = <&pinctrl_i2c2>; | ||
| 212 | status = "okay"; | ||
| 213 | |||
| 214 | pmic: pfuze100@08 { | ||
| 215 | compatible = "fsl,pfuze100"; | ||
| 216 | reg = <0x08>; | ||
| 217 | |||
| 218 | regulators { | ||
| 219 | sw1a_reg: sw1ab { | ||
| 220 | regulator-min-microvolt = <300000>; | ||
| 221 | regulator-max-microvolt = <1875000>; | ||
| 222 | regulator-boot-on; | ||
| 223 | regulator-always-on; | ||
| 224 | regulator-ramp-delay = <6250>; | ||
| 225 | }; | ||
| 226 | |||
| 227 | sw1c_reg: sw1c { | ||
| 228 | regulator-min-microvolt = <300000>; | ||
| 229 | regulator-max-microvolt = <1875000>; | ||
| 230 | regulator-boot-on; | ||
| 231 | regulator-always-on; | ||
| 232 | regulator-ramp-delay = <6250>; | ||
| 233 | }; | ||
| 234 | |||
| 235 | sw2_reg: sw2 { | ||
| 236 | regulator-min-microvolt = <800000>; | ||
| 237 | regulator-max-microvolt = <3950000>; | ||
| 238 | regulator-boot-on; | ||
| 239 | regulator-always-on; | ||
| 240 | }; | ||
| 241 | |||
| 242 | sw3a_reg: sw3a { | ||
| 243 | regulator-min-microvolt = <400000>; | ||
| 244 | regulator-max-microvolt = <1975000>; | ||
| 245 | regulator-boot-on; | ||
| 246 | regulator-always-on; | ||
| 247 | }; | ||
| 248 | |||
| 249 | sw3b_reg: sw3b { | ||
| 250 | regulator-min-microvolt = <400000>; | ||
| 251 | regulator-max-microvolt = <1975000>; | ||
| 252 | regulator-boot-on; | ||
| 253 | regulator-always-on; | ||
| 254 | }; | ||
| 255 | |||
| 256 | sw4_reg: sw4 { | ||
| 257 | regulator-min-microvolt = <800000>; | ||
| 258 | regulator-max-microvolt = <3300000>; | ||
| 259 | }; | ||
| 260 | |||
| 261 | swbst_reg: swbst { | ||
| 262 | regulator-min-microvolt = <5000000>; | ||
| 263 | regulator-max-microvolt = <5150000>; | ||
| 264 | }; | ||
| 265 | |||
| 266 | snvs_reg: vsnvs { | ||
| 267 | regulator-min-microvolt = <1000000>; | ||
| 268 | regulator-max-microvolt = <3000000>; | ||
| 269 | regulator-boot-on; | ||
| 270 | regulator-always-on; | ||
| 271 | }; | ||
| 272 | |||
| 273 | vref_reg: vrefddr { | ||
| 274 | regulator-boot-on; | ||
| 275 | regulator-always-on; | ||
| 276 | }; | ||
| 277 | |||
| 278 | vgen1_reg: vgen1 { | ||
| 279 | regulator-min-microvolt = <800000>; | ||
| 280 | regulator-max-microvolt = <1550000>; | ||
| 281 | }; | ||
| 282 | |||
| 283 | vgen2_reg: vgen2 { | ||
| 284 | regulator-min-microvolt = <800000>; | ||
| 285 | regulator-max-microvolt = <1550000>; | ||
| 286 | }; | ||
| 287 | |||
| 288 | vgen3_reg: vgen3 { | ||
| 289 | regulator-min-microvolt = <1800000>; | ||
| 290 | regulator-max-microvolt = <3300000>; | ||
| 291 | }; | ||
| 292 | |||
| 293 | vgen4_reg: vgen4 { | ||
| 294 | regulator-min-microvolt = <1800000>; | ||
| 295 | regulator-max-microvolt = <3300000>; | ||
| 296 | regulator-always-on; | ||
| 297 | }; | ||
| 298 | |||
| 299 | vgen5_reg: vgen5 { | ||
| 300 | regulator-min-microvolt = <1800000>; | ||
| 301 | regulator-max-microvolt = <3300000>; | ||
| 302 | regulator-always-on; | ||
| 303 | }; | ||
| 304 | |||
| 305 | vgen6_reg: vgen6 { | ||
| 306 | regulator-min-microvolt = <1800000>; | ||
| 307 | regulator-max-microvolt = <3300000>; | ||
| 308 | regulator-always-on; | ||
| 309 | }; | ||
| 310 | }; | ||
| 311 | }; | ||
| 312 | |||
| 313 | pciswitch: pex8609@3f { | ||
| 314 | compatible = "plx,pex8609"; | ||
| 315 | reg = <0x3f>; | ||
| 316 | }; | ||
| 317 | |||
| 318 | pciclkgen: si52147@6b { | ||
| 319 | compatible = "sil,si52147"; | ||
| 320 | reg = <0x6b>; | ||
| 321 | }; | ||
| 322 | }; | ||
| 323 | |||
| 324 | &i2c3 { | ||
| 325 | clock-frequency = <100000>; | ||
| 326 | pinctrl-names = "default"; | ||
| 327 | pinctrl-0 = <&pinctrl_i2c3>; | ||
| 328 | status = "okay"; | ||
| 329 | |||
| 330 | accelerometer: mma8450@1c { | ||
| 331 | compatible = "fsl,mma8450"; | ||
| 332 | reg = <0x1c>; | ||
| 333 | }; | ||
| 334 | |||
| 335 | codec: sgtl5000@0a { | ||
| 336 | compatible = "fsl,sgtl5000"; | ||
| 337 | reg = <0x0a>; | ||
| 338 | clocks = <&clks 201>; | ||
| 339 | VDDA-supply = <&sw4_reg>; | ||
| 340 | VDDIO-supply = <®_3p3v>; | ||
| 341 | }; | ||
| 342 | |||
| 343 | hdmiin: adv7611@4c { | ||
| 344 | compatible = "adi,adv7611"; | ||
| 345 | reg = <0x4c>; | ||
| 346 | }; | ||
| 347 | |||
| 348 | touchscreen: egalax_ts@04 { | ||
| 349 | compatible = "eeti,egalax_ts"; | ||
| 350 | reg = <0x04>; | ||
| 351 | interrupt-parent = <&gpio7>; | ||
| 352 | interrupts = <12 2>; /* gpio7_12 active low */ | ||
| 353 | wakeup-gpios = <&gpio7 12 0>; | ||
| 354 | }; | ||
| 355 | |||
| 356 | videoout: adv7393@2a { | ||
| 357 | compatible = "adi,adv7393"; | ||
| 358 | reg = <0x2a>; | ||
| 359 | }; | ||
| 360 | |||
| 361 | videoin: adv7180@20 { | ||
| 362 | compatible = "adi,adv7180"; | ||
| 363 | reg = <0x20>; | ||
| 364 | }; | ||
| 365 | }; | ||
| 366 | |||
| 367 | &iomuxc { | ||
| 368 | pinctrl-names = "default"; | ||
| 369 | pinctrl-0 = <&pinctrl_hog>; | ||
| 370 | |||
| 371 | imx6q-gw5400-a { | ||
| 372 | pinctrl_hog: hoggrp { | ||
| 373 | fsl,pins = < | ||
| 374 | MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ | ||
| 375 | MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* SPINOR_CS0# */ | ||
| 376 | MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */ | ||
| 377 | MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */ | ||
| 378 | MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ | ||
| 379 | MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 /* GPS_PPS */ | ||
| 380 | MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */ | ||
| 381 | MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ | ||
| 382 | MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000 /* user2 led */ | ||
| 383 | MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ | ||
| 384 | MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 /* USBHUB_RST# */ | ||
| 385 | MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x80000000 /* MIPI_DIO */ | ||
| 386 | >; | ||
| 387 | }; | ||
| 388 | |||
| 389 | pinctrl_audmux: audmuxgrp { | ||
| 390 | fsl,pins = < | ||
| 391 | MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 | ||
| 392 | MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 | ||
| 393 | MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 | ||
| 394 | MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 | ||
| 395 | >; | ||
| 396 | }; | ||
| 397 | |||
| 398 | pinctrl_ecspi1: ecspi1grp { | ||
| 399 | fsl,pins = < | ||
| 400 | MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 | ||
| 401 | MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 | ||
| 402 | MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 | ||
| 403 | >; | ||
| 404 | }; | ||
| 405 | |||
| 406 | pinctrl_enet: enetgrp { | ||
| 407 | fsl,pins = < | ||
| 408 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 409 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 410 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 411 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 412 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 413 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 414 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 415 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 416 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 417 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 418 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 419 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 420 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 421 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | ||
| 422 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | ||
| 423 | MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 | ||
| 424 | >; | ||
| 425 | }; | ||
| 426 | |||
| 427 | pinctrl_i2c1: i2c1grp { | ||
| 428 | fsl,pins = < | ||
| 429 | MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 | ||
| 430 | MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 | ||
| 431 | >; | ||
| 432 | }; | ||
| 433 | |||
| 434 | pinctrl_i2c2: i2c2grp { | ||
| 435 | fsl,pins = < | ||
| 436 | MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 | ||
| 437 | MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 | ||
| 438 | >; | ||
| 439 | }; | ||
| 440 | |||
| 441 | pinctrl_i2c3: i2c3grp { | ||
| 442 | fsl,pins = < | ||
| 443 | MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 | ||
| 444 | MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 | ||
| 445 | >; | ||
| 446 | }; | ||
| 447 | |||
| 448 | pinctrl_uart1: uart1grp { | ||
| 449 | fsl,pins = < | ||
| 450 | MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 | ||
| 451 | MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 | ||
| 452 | >; | ||
| 453 | }; | ||
| 454 | |||
| 455 | pinctrl_uart2: uart2grp { | ||
| 456 | fsl,pins = < | ||
| 457 | MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 | ||
| 458 | MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 | ||
| 459 | >; | ||
| 460 | }; | ||
| 461 | |||
| 462 | pinctrl_uart5: uart5grp { | ||
| 463 | fsl,pins = < | ||
| 464 | MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 | ||
| 465 | MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 | ||
| 466 | >; | ||
| 467 | }; | ||
| 468 | |||
| 469 | pinctrl_usbotg: usbotggrp { | ||
| 470 | fsl,pins = < | ||
| 471 | MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 | ||
| 472 | >; | ||
| 473 | }; | ||
| 474 | |||
| 475 | pinctrl_usdhc3: usdhc3grp { | ||
| 476 | fsl,pins = < | ||
| 477 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 478 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 479 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 480 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 481 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 482 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 483 | >; | ||
| 484 | }; | ||
| 485 | }; | ||
| 486 | }; | ||
| 487 | |||
| 488 | &ldb { | ||
| 489 | status = "okay"; | ||
| 490 | lvds-channel@0 { | ||
| 491 | crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>; | ||
| 492 | }; | ||
| 493 | }; | ||
| 494 | |||
| 495 | &pcie { | ||
| 496 | reset-gpio = <&gpio1 29 0>; | ||
| 497 | status = "okay"; | ||
| 498 | |||
| 499 | eth1: sky2@8 { /* MAC/PHY on bus 8 */ | ||
| 500 | compatible = "marvell,sky2"; | ||
| 501 | }; | ||
| 502 | }; | ||
| 503 | |||
| 504 | &ssi1 { | ||
| 505 | fsl,mode = "i2s-slave"; | ||
| 506 | status = "okay"; | ||
| 507 | }; | ||
| 508 | |||
| 509 | &uart1 { | ||
| 510 | pinctrl-names = "default"; | ||
| 511 | pinctrl-0 = <&pinctrl_uart1>; | ||
| 512 | status = "okay"; | ||
| 513 | }; | ||
| 514 | |||
| 515 | &uart2 { | ||
| 516 | pinctrl-names = "default"; | ||
| 517 | pinctrl-0 = <&pinctrl_uart2>; | ||
| 518 | status = "okay"; | ||
| 519 | }; | ||
| 520 | |||
| 521 | &uart5 { | ||
| 522 | pinctrl-names = "default"; | ||
| 523 | pinctrl-0 = <&pinctrl_uart5>; | ||
| 524 | status = "okay"; | ||
| 525 | }; | ||
| 526 | |||
| 527 | &usbotg { | ||
| 528 | vbus-supply = <®_usb_otg_vbus>; | ||
| 529 | pinctrl-names = "default"; | ||
| 530 | pinctrl-0 = <&pinctrl_usbotg>; | ||
| 531 | disable-over-current; | ||
| 532 | status = "okay"; | ||
| 533 | }; | ||
| 534 | |||
| 535 | &usbh1 { | ||
| 536 | vbus-supply = <®_usb_h1_vbus>; | ||
| 537 | status = "okay"; | ||
| 538 | }; | ||
| 539 | |||
| 540 | &usdhc3 { | ||
| 541 | pinctrl-names = "default"; | ||
| 542 | pinctrl-0 = <&pinctrl_usdhc3>; | ||
| 543 | cd-gpios = <&gpio7 0 0>; | ||
| 544 | vmmc-supply = <®_3p3v>; | ||
| 545 | status = "okay"; | ||
| 546 | }; | ||
diff --git a/arch/arm/boot/dts/imx6q-gw54xx.dts b/arch/arm/boot/dts/imx6q-gw54xx.dts new file mode 100644 index 000000000000..ab518d66a75e --- /dev/null +++ b/arch/arm/boot/dts/imx6q-gw54xx.dts | |||
| @@ -0,0 +1,23 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Gateworks Corporation | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | #include "imx6q.dtsi" | ||
| 14 | #include "imx6qdl-gw54xx.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Gateworks Ventana i.MX6 Quad GW54XX"; | ||
| 18 | compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q"; | ||
| 19 | }; | ||
| 20 | |||
| 21 | &sata { | ||
| 22 | status = "okay"; | ||
| 23 | }; | ||
diff --git a/arch/arm/boot/dts/imx6q-nitrogen6x.dts b/arch/arm/boot/dts/imx6q-nitrogen6x.dts new file mode 100644 index 000000000000..a57866b2e97e --- /dev/null +++ b/arch/arm/boot/dts/imx6q-nitrogen6x.dts | |||
| @@ -0,0 +1,25 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Boundary Devices, Inc. | ||
| 3 | * Copyright 2012 Freescale Semiconductor, Inc. | ||
| 4 | * Copyright 2011 Linaro Ltd. | ||
| 5 | * | ||
| 6 | * The code contained herein is licensed under the GNU General Public | ||
| 7 | * License. You may obtain a copy of the GNU General Public License | ||
| 8 | * Version 2 or later at the following locations: | ||
| 9 | * | ||
| 10 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 11 | * http://www.gnu.org/copyleft/gpl.html | ||
| 12 | */ | ||
| 13 | |||
| 14 | /dts-v1/; | ||
| 15 | #include "imx6q.dtsi" | ||
| 16 | #include "imx6qdl-nitrogen6x.dtsi" | ||
| 17 | |||
| 18 | / { | ||
| 19 | model = "Freescale i.MX6 Quad Nitrogen6x Board"; | ||
| 20 | compatible = "fsl,imx6q-nitrogen6x", "fsl,imx6q"; | ||
| 21 | }; | ||
| 22 | |||
| 23 | &sata { | ||
| 24 | status = "okay"; | ||
| 25 | }; | ||
diff --git a/arch/arm/boot/dts/imx6q-phytec-pbab01.dts b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts index 7d37ec60d58d..5607c331fca8 100644 --- a/arch/arm/boot/dts/imx6q-phytec-pbab01.dts +++ b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts | |||
| @@ -21,10 +21,26 @@ | |||
| 21 | status = "okay"; | 21 | status = "okay"; |
| 22 | }; | 22 | }; |
| 23 | 23 | ||
| 24 | &gpmi { | ||
| 25 | status = "okay"; | ||
| 26 | }; | ||
| 27 | |||
| 28 | &sata { | ||
| 29 | status = "okay"; | ||
| 30 | }; | ||
| 31 | |||
| 24 | &uart4 { | 32 | &uart4 { |
| 25 | status = "okay"; | 33 | status = "okay"; |
| 26 | }; | 34 | }; |
| 27 | 35 | ||
| 36 | &usbh1 { | ||
| 37 | status = "okay"; | ||
| 38 | }; | ||
| 39 | |||
| 40 | &usbotg { | ||
| 41 | status = "okay"; | ||
| 42 | }; | ||
| 43 | |||
| 28 | &usdhc2 { | 44 | &usdhc2 { |
| 29 | status = "okay"; | 45 | status = "okay"; |
| 30 | }; | 46 | }; |
diff --git a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi index 1a3b50d4d8fa..324f1550976b 100644 --- a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi | |||
| @@ -18,11 +18,35 @@ | |||
| 18 | memory { | 18 | memory { |
| 19 | reg = <0x10000000 0x80000000>; | 19 | reg = <0x10000000 0x80000000>; |
| 20 | }; | 20 | }; |
| 21 | |||
| 22 | regulators { | ||
| 23 | compatible = "simple-bus"; | ||
| 24 | #address-cells = <1>; | ||
| 25 | #size-cells = <0>; | ||
| 26 | |||
| 27 | reg_usb_otg_vbus: regulator@0 { | ||
| 28 | compatible = "regulator-fixed"; | ||
| 29 | reg = <0>; | ||
| 30 | regulator-name = "usb_otg_vbus"; | ||
| 31 | regulator-min-microvolt = <5000000>; | ||
| 32 | regulator-max-microvolt = <5000000>; | ||
| 33 | gpio = <&gpio4 15 0>; | ||
| 34 | }; | ||
| 35 | |||
| 36 | reg_usb_h1_vbus: regulator@1 { | ||
| 37 | compatible = "regulator-fixed"; | ||
| 38 | reg = <1>; | ||
| 39 | regulator-name = "usb_h1_vbus"; | ||
| 40 | regulator-min-microvolt = <5000000>; | ||
| 41 | regulator-max-microvolt = <5000000>; | ||
| 42 | gpio = <&gpio1 0 0>; | ||
| 43 | }; | ||
| 44 | }; | ||
| 21 | }; | 45 | }; |
| 22 | 46 | ||
| 23 | &ecspi3 { | 47 | &ecspi3 { |
| 24 | pinctrl-names = "default"; | 48 | pinctrl-names = "default"; |
| 25 | pinctrl-0 = <&pinctrl_ecspi3_1>; | 49 | pinctrl-0 = <&pinctrl_ecspi3>; |
| 26 | status = "okay"; | 50 | status = "okay"; |
| 27 | fsl,spi-num-chipselects = <1>; | 51 | fsl,spi-num-chipselects = <1>; |
| 28 | cs-gpios = <&gpio4 24 0>; | 52 | cs-gpios = <&gpio4 24 0>; |
| @@ -36,7 +60,7 @@ | |||
| 36 | 60 | ||
| 37 | &i2c1 { | 61 | &i2c1 { |
| 38 | pinctrl-names = "default"; | 62 | pinctrl-names = "default"; |
| 39 | pinctrl-0 = <&pinctrl_i2c1_1>; | 63 | pinctrl-0 = <&pinctrl_i2c1>; |
| 40 | status = "okay"; | 64 | status = "okay"; |
| 41 | 65 | ||
| 42 | eeprom@50 { | 66 | eeprom@50 { |
| @@ -128,7 +152,7 @@ | |||
| 128 | pinctrl-names = "default"; | 152 | pinctrl-names = "default"; |
| 129 | pinctrl-0 = <&pinctrl_hog>; | 153 | pinctrl-0 = <&pinctrl_hog>; |
| 130 | 154 | ||
| 131 | hog { | 155 | imx6q-phytec-pfla02 { |
| 132 | pinctrl_hog: hoggrp { | 156 | pinctrl_hog: hoggrp { |
| 133 | fsl,pins = < | 157 | fsl,pins = < |
| 134 | MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 | 158 | MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 |
| @@ -136,10 +160,109 @@ | |||
| 136 | MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000 /* PMIC interrupt */ | 160 | MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000 /* PMIC interrupt */ |
| 137 | >; | 161 | >; |
| 138 | }; | 162 | }; |
| 139 | }; | ||
| 140 | 163 | ||
| 141 | pfla02 { | 164 | pinctrl_ecspi3: ecspi3grp { |
| 142 | pinctrl_usdhc3_pfla02: usdhc3grp-pfla02 { | 165 | fsl,pins = < |
| 166 | MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 | ||
| 167 | MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 | ||
| 168 | MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 | ||
| 169 | >; | ||
| 170 | }; | ||
| 171 | |||
| 172 | pinctrl_enet: enetgrp { | ||
| 173 | fsl,pins = < | ||
| 174 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | ||
| 175 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | ||
| 176 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 177 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 178 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 179 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 180 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 181 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 182 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 183 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 184 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 185 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 186 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 187 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 188 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 189 | MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 | ||
| 190 | >; | ||
| 191 | }; | ||
| 192 | |||
| 193 | pinctrl_gpmi_nand: gpminandgrp { | ||
| 194 | fsl,pins = < | ||
| 195 | MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 | ||
| 196 | MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 | ||
| 197 | MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 | ||
| 198 | MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 | ||
| 199 | MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 | ||
| 200 | MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 | ||
| 201 | MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 | ||
| 202 | MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 | ||
| 203 | MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 | ||
| 204 | MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 | ||
| 205 | MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 | ||
| 206 | MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 | ||
| 207 | MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 | ||
| 208 | MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 | ||
| 209 | MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 | ||
| 210 | MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 | ||
| 211 | MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 | ||
| 212 | >; | ||
| 213 | }; | ||
| 214 | |||
| 215 | pinctrl_i2c1: i2c1grp { | ||
| 216 | fsl,pins = < | ||
| 217 | MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 | ||
| 218 | MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 | ||
| 219 | >; | ||
| 220 | }; | ||
| 221 | |||
| 222 | pinctrl_uart4: uart4grp { | ||
| 223 | fsl,pins = < | ||
| 224 | MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 | ||
| 225 | MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 | ||
| 226 | >; | ||
| 227 | }; | ||
| 228 | |||
| 229 | pinctrl_usbh1: usbh1grp { | ||
| 230 | fsl,pins = < | ||
| 231 | MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x80000000 | ||
| 232 | >; | ||
| 233 | }; | ||
| 234 | |||
| 235 | pinctrl_usbotg: usbotggrp { | ||
| 236 | fsl,pins = < | ||
| 237 | MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 | ||
| 238 | MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 | ||
| 239 | MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 | ||
| 240 | >; | ||
| 241 | }; | ||
| 242 | |||
| 243 | pinctrl_usdhc2: usdhc2grp { | ||
| 244 | fsl,pins = < | ||
| 245 | MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 | ||
| 246 | MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 | ||
| 247 | MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 | ||
| 248 | MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 | ||
| 249 | MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 | ||
| 250 | MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 | ||
| 251 | >; | ||
| 252 | }; | ||
| 253 | |||
| 254 | pinctrl_usdhc3: usdhc3grp { | ||
| 255 | fsl,pins = < | ||
| 256 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 257 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 258 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 259 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 260 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 261 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 262 | >; | ||
| 263 | }; | ||
| 264 | |||
| 265 | pinctrl_usdhc3_cdwp: usdhc3cdwp { | ||
| 143 | fsl,pins = < | 266 | fsl,pins = < |
| 144 | MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 | 267 | MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 |
| 145 | MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 | 268 | MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 |
| @@ -150,21 +273,43 @@ | |||
| 150 | 273 | ||
| 151 | &fec { | 274 | &fec { |
| 152 | pinctrl-names = "default"; | 275 | pinctrl-names = "default"; |
| 153 | pinctrl-0 = <&pinctrl_enet_3>; | 276 | pinctrl-0 = <&pinctrl_enet>; |
| 154 | phy-mode = "rgmii"; | 277 | phy-mode = "rgmii"; |
| 155 | phy-reset-gpios = <&gpio3 23 0>; | 278 | phy-reset-gpios = <&gpio3 23 0>; |
| 156 | status = "disabled"; | 279 | status = "disabled"; |
| 157 | }; | 280 | }; |
| 158 | 281 | ||
| 282 | &gpmi { | ||
| 283 | pinctrl-names = "default"; | ||
| 284 | pinctrl-0 = <&pinctrl_gpmi_nand>; | ||
| 285 | nand-on-flash-bbt; | ||
| 286 | status = "disabled"; | ||
| 287 | }; | ||
| 288 | |||
| 159 | &uart4 { | 289 | &uart4 { |
| 160 | pinctrl-names = "default"; | 290 | pinctrl-names = "default"; |
| 161 | pinctrl-0 = <&pinctrl_uart4_1>; | 291 | pinctrl-0 = <&pinctrl_uart4>; |
| 292 | status = "disabled"; | ||
| 293 | }; | ||
| 294 | |||
| 295 | &usbh1 { | ||
| 296 | vbus-supply = <®_usb_h1_vbus>; | ||
| 297 | pinctrl-names = "default"; | ||
| 298 | pinctrl-0 = <&pinctrl_usbh1>; | ||
| 299 | status = "disabled"; | ||
| 300 | }; | ||
| 301 | |||
| 302 | &usbotg { | ||
| 303 | vbus-supply = <®_usb_otg_vbus>; | ||
| 304 | pinctrl-names = "default"; | ||
| 305 | pinctrl-0 = <&pinctrl_usbotg>; | ||
| 306 | disable-over-current; | ||
| 162 | status = "disabled"; | 307 | status = "disabled"; |
| 163 | }; | 308 | }; |
| 164 | 309 | ||
| 165 | &usdhc2 { | 310 | &usdhc2 { |
| 166 | pinctrl-names = "default"; | 311 | pinctrl-names = "default"; |
| 167 | pinctrl-0 = <&pinctrl_usdhc2_2>; | 312 | pinctrl-0 = <&pinctrl_usdhc2>; |
| 168 | cd-gpios = <&gpio1 4 0>; | 313 | cd-gpios = <&gpio1 4 0>; |
| 169 | wp-gpios = <&gpio1 2 0>; | 314 | wp-gpios = <&gpio1 2 0>; |
| 170 | status = "disabled"; | 315 | status = "disabled"; |
| @@ -172,8 +317,8 @@ | |||
| 172 | 317 | ||
| 173 | &usdhc3 { | 318 | &usdhc3 { |
| 174 | pinctrl-names = "default"; | 319 | pinctrl-names = "default"; |
| 175 | pinctrl-0 = <&pinctrl_usdhc3_2 | 320 | pinctrl-0 = <&pinctrl_usdhc3 |
| 176 | &pinctrl_usdhc3_pfla02>; | 321 | &pinctrl_usdhc3_cdwp>; |
| 177 | cd-gpios = <&gpio1 27 0>; | 322 | cd-gpios = <&gpio1 27 0>; |
| 178 | wp-gpios = <&gpio1 29 0>; | 323 | wp-gpios = <&gpio1 29 0>; |
| 179 | status = "disabled"; | 324 | status = "disabled"; |
diff --git a/arch/arm/boot/dts/imx6q-pinfunc.h b/arch/arm/boot/dts/imx6q-pinfunc.h index 97ed0816a6e0..9fc6120a1853 100644 --- a/arch/arm/boot/dts/imx6q-pinfunc.h +++ b/arch/arm/boot/dts/imx6q-pinfunc.h | |||
| @@ -673,6 +673,7 @@ | |||
| 673 | #define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x22c 0x5fc 0x948 0x6 0x1 | 673 | #define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x22c 0x5fc 0x948 0x6 0x1 |
| 674 | #define MX6QDL_PAD_GPIO_3__MLB_CLK 0x22c 0x5fc 0x900 0x7 0x1 | 674 | #define MX6QDL_PAD_GPIO_3__MLB_CLK 0x22c 0x5fc 0x900 0x7 0x1 |
| 675 | #define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x230 0x600 0x870 0x0 0x1 | 675 | #define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x230 0x600 0x870 0x0 0x1 |
| 676 | #define MX6QDL_PAD_GPIO_6__ENET_IRQ 0x230 0x600 0x03c 0x11 0xff000609 | ||
| 676 | #define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x230 0x600 0x8ac 0x2 0x1 | 677 | #define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x230 0x600 0x8ac 0x2 0x1 |
| 677 | #define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x230 0x600 0x000 0x5 0x0 | 678 | #define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x230 0x600 0x000 0x5 0x0 |
| 678 | #define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x230 0x600 0x000 0x6 0x0 | 679 | #define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x230 0x600 0x000 0x6 0x0 |
| @@ -1024,6 +1025,7 @@ | |||
| 1024 | #define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x34c 0x734 0x000 0x6 0x0 | 1025 | #define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x34c 0x734 0x000 0x6 0x0 |
| 1025 | #define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x350 0x738 0x000 0x0 0x0 | 1026 | #define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x350 0x738 0x000 0x0 0x0 |
| 1026 | #define MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x350 0x738 0x828 0x1 0x0 | 1027 | #define MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x350 0x738 0x828 0x1 0x0 |
| 1028 | #define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x350 0x738 0x000 0x2 0x0 | ||
| 1027 | #define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x350 0x738 0x000 0x3 0x0 | 1029 | #define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x350 0x738 0x000 0x3 0x0 |
| 1028 | #define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x350 0x738 0x000 0x5 0x0 | 1030 | #define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x350 0x738 0x000 0x5 0x0 |
| 1029 | #define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x354 0x73c 0x000 0x0 0x0 | 1031 | #define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x354 0x73c 0x000 0x0 0x0 |
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts index f004913f7d80..96e4688be77c 100644 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts | |||
| @@ -12,189 +12,13 @@ | |||
| 12 | 12 | ||
| 13 | /dts-v1/; | 13 | /dts-v1/; |
| 14 | #include "imx6q.dtsi" | 14 | #include "imx6q.dtsi" |
| 15 | #include "imx6qdl-sabrelite.dtsi" | ||
| 15 | 16 | ||
| 16 | / { | 17 | / { |
| 17 | model = "Freescale i.MX6 Quad SABRE Lite Board"; | 18 | model = "Freescale i.MX6 Quad SABRE Lite Board"; |
| 18 | compatible = "fsl,imx6q-sabrelite", "fsl,imx6q"; | 19 | compatible = "fsl,imx6q-sabrelite", "fsl,imx6q"; |
| 19 | |||
| 20 | memory { | ||
| 21 | reg = <0x10000000 0x40000000>; | ||
| 22 | }; | ||
| 23 | |||
| 24 | regulators { | ||
| 25 | compatible = "simple-bus"; | ||
| 26 | |||
| 27 | reg_2p5v: 2p5v { | ||
| 28 | compatible = "regulator-fixed"; | ||
| 29 | regulator-name = "2P5V"; | ||
| 30 | regulator-min-microvolt = <2500000>; | ||
| 31 | regulator-max-microvolt = <2500000>; | ||
| 32 | regulator-always-on; | ||
| 33 | }; | ||
| 34 | |||
| 35 | reg_3p3v: 3p3v { | ||
| 36 | compatible = "regulator-fixed"; | ||
| 37 | regulator-name = "3P3V"; | ||
| 38 | regulator-min-microvolt = <3300000>; | ||
| 39 | regulator-max-microvolt = <3300000>; | ||
| 40 | regulator-always-on; | ||
| 41 | }; | ||
| 42 | |||
| 43 | reg_usb_otg_vbus: usb_otg_vbus { | ||
| 44 | compatible = "regulator-fixed"; | ||
| 45 | regulator-name = "usb_otg_vbus"; | ||
| 46 | regulator-min-microvolt = <5000000>; | ||
| 47 | regulator-max-microvolt = <5000000>; | ||
| 48 | gpio = <&gpio3 22 0>; | ||
| 49 | enable-active-high; | ||
| 50 | }; | ||
| 51 | }; | ||
| 52 | |||
| 53 | sound { | ||
| 54 | compatible = "fsl,imx6q-sabrelite-sgtl5000", | ||
| 55 | "fsl,imx-audio-sgtl5000"; | ||
| 56 | model = "imx6q-sabrelite-sgtl5000"; | ||
| 57 | ssi-controller = <&ssi1>; | ||
| 58 | audio-codec = <&codec>; | ||
| 59 | audio-routing = | ||
| 60 | "MIC_IN", "Mic Jack", | ||
| 61 | "Mic Jack", "Mic Bias", | ||
| 62 | "Headphone Jack", "HP_OUT"; | ||
| 63 | mux-int-port = <1>; | ||
| 64 | mux-ext-port = <4>; | ||
| 65 | }; | ||
| 66 | }; | ||
| 67 | |||
| 68 | &audmux { | ||
| 69 | status = "okay"; | ||
| 70 | pinctrl-names = "default"; | ||
| 71 | pinctrl-0 = <&pinctrl_audmux_1>; | ||
| 72 | }; | ||
| 73 | |||
| 74 | &ecspi1 { | ||
| 75 | fsl,spi-num-chipselects = <1>; | ||
| 76 | cs-gpios = <&gpio3 19 0>; | ||
| 77 | pinctrl-names = "default"; | ||
| 78 | pinctrl-0 = <&pinctrl_ecspi1_1>; | ||
| 79 | status = "okay"; | ||
| 80 | |||
| 81 | flash: m25p80@0 { | ||
| 82 | compatible = "sst,sst25vf016b"; | ||
| 83 | spi-max-frequency = <20000000>; | ||
| 84 | reg = <0>; | ||
| 85 | }; | ||
| 86 | }; | ||
| 87 | |||
| 88 | &fec { | ||
| 89 | pinctrl-names = "default"; | ||
| 90 | pinctrl-0 = <&pinctrl_enet_1>; | ||
| 91 | phy-mode = "rgmii"; | ||
| 92 | phy-reset-gpios = <&gpio3 23 0>; | ||
| 93 | status = "okay"; | ||
| 94 | }; | ||
| 95 | |||
| 96 | &i2c1 { | ||
| 97 | status = "okay"; | ||
| 98 | clock-frequency = <100000>; | ||
| 99 | pinctrl-names = "default"; | ||
| 100 | pinctrl-0 = <&pinctrl_i2c1_1>; | ||
| 101 | |||
| 102 | codec: sgtl5000@0a { | ||
| 103 | compatible = "fsl,sgtl5000"; | ||
| 104 | reg = <0x0a>; | ||
| 105 | clocks = <&clks 201>; | ||
| 106 | VDDA-supply = <®_2p5v>; | ||
| 107 | VDDIO-supply = <®_3p3v>; | ||
| 108 | }; | ||
| 109 | }; | ||
| 110 | |||
| 111 | &iomuxc { | ||
| 112 | pinctrl-names = "default"; | ||
| 113 | pinctrl-0 = <&pinctrl_hog>; | ||
| 114 | |||
| 115 | hog { | ||
| 116 | pinctrl_hog: hoggrp { | ||
| 117 | fsl,pins = < | ||
| 118 | MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 | ||
| 119 | MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 | ||
| 120 | MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 | ||
| 121 | MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 | ||
| 122 | MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 | ||
| 123 | MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 | ||
| 124 | MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 | ||
| 125 | MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x80000000 | ||
| 126 | MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 | ||
| 127 | >; | ||
| 128 | }; | ||
| 129 | }; | ||
| 130 | }; | ||
| 131 | |||
| 132 | &ldb { | ||
| 133 | status = "okay"; | ||
| 134 | |||
| 135 | lvds-channel@0 { | ||
| 136 | fsl,data-mapping = "spwg"; | ||
| 137 | fsl,data-width = <18>; | ||
| 138 | status = "okay"; | ||
| 139 | |||
| 140 | display-timings { | ||
| 141 | native-mode = <&timing0>; | ||
| 142 | timing0: hsd100pxn1 { | ||
| 143 | clock-frequency = <65000000>; | ||
| 144 | hactive = <1024>; | ||
| 145 | vactive = <768>; | ||
| 146 | hback-porch = <220>; | ||
| 147 | hfront-porch = <40>; | ||
| 148 | vback-porch = <21>; | ||
| 149 | vfront-porch = <7>; | ||
| 150 | hsync-len = <60>; | ||
| 151 | vsync-len = <10>; | ||
| 152 | }; | ||
| 153 | }; | ||
| 154 | }; | ||
| 155 | }; | 20 | }; |
| 156 | 21 | ||
| 157 | &sata { | 22 | &sata { |
| 158 | status = "okay"; | 23 | status = "okay"; |
| 159 | }; | 24 | }; |
| 160 | |||
| 161 | &ssi1 { | ||
| 162 | fsl,mode = "i2s-slave"; | ||
| 163 | status = "okay"; | ||
| 164 | }; | ||
| 165 | |||
| 166 | &uart2 { | ||
| 167 | status = "okay"; | ||
| 168 | pinctrl-names = "default"; | ||
| 169 | pinctrl-0 = <&pinctrl_uart2_1>; | ||
| 170 | }; | ||
| 171 | |||
| 172 | &usbh1 { | ||
| 173 | status = "okay"; | ||
| 174 | }; | ||
| 175 | |||
| 176 | &usbotg { | ||
| 177 | vbus-supply = <®_usb_otg_vbus>; | ||
| 178 | pinctrl-names = "default"; | ||
| 179 | pinctrl-0 = <&pinctrl_usbotg_1>; | ||
| 180 | disable-over-current; | ||
| 181 | status = "okay"; | ||
| 182 | }; | ||
| 183 | |||
| 184 | &usdhc3 { | ||
| 185 | pinctrl-names = "default"; | ||
| 186 | pinctrl-0 = <&pinctrl_usdhc3_2>; | ||
| 187 | cd-gpios = <&gpio7 0 0>; | ||
| 188 | wp-gpios = <&gpio7 1 0>; | ||
| 189 | vmmc-supply = <®_3p3v>; | ||
| 190 | status = "okay"; | ||
| 191 | }; | ||
| 192 | |||
| 193 | &usdhc4 { | ||
| 194 | pinctrl-names = "default"; | ||
| 195 | pinctrl-0 = <&pinctrl_usdhc4_2>; | ||
| 196 | cd-gpios = <&gpio2 6 0>; | ||
| 197 | wp-gpios = <&gpio2 7 0>; | ||
| 198 | vmmc-supply = <®_3p3v>; | ||
| 199 | status = "okay"; | ||
| 200 | }; | ||
diff --git a/arch/arm/boot/dts/imx6q-sbc6x.dts b/arch/arm/boot/dts/imx6q-sbc6x.dts index ee6addf149af..86cf09364664 100644 --- a/arch/arm/boot/dts/imx6q-sbc6x.dts +++ b/arch/arm/boot/dts/imx6q-sbc6x.dts | |||
| @@ -17,28 +17,78 @@ | |||
| 17 | }; | 17 | }; |
| 18 | }; | 18 | }; |
| 19 | 19 | ||
| 20 | |||
| 20 | &fec { | 21 | &fec { |
| 21 | pinctrl-names = "default"; | 22 | pinctrl-names = "default"; |
| 22 | pinctrl-0 = <&pinctrl_enet_1>; | 23 | pinctrl-0 = <&pinctrl_enet>; |
| 23 | phy-mode = "rgmii"; | 24 | phy-mode = "rgmii"; |
| 24 | status = "okay"; | 25 | status = "okay"; |
| 25 | }; | 26 | }; |
| 26 | 27 | ||
| 28 | &iomuxc { | ||
| 29 | imx6q-sbc6x { | ||
| 30 | pinctrl_enet: enetgrp { | ||
| 31 | fsl,pins = < | ||
| 32 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | ||
| 33 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | ||
| 34 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 35 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 36 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 37 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 38 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 39 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 40 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 41 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 42 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 43 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 44 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 45 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 46 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 47 | MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 | ||
| 48 | >; | ||
| 49 | }; | ||
| 50 | |||
| 51 | pinctrl_uart1: uart1grp { | ||
| 52 | fsl,pins = < | ||
| 53 | MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 | ||
| 54 | MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 | ||
| 55 | >; | ||
| 56 | }; | ||
| 57 | |||
| 58 | pinctrl_usbotg: usbotggrp { | ||
| 59 | fsl,pins = < | ||
| 60 | MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 | ||
| 61 | >; | ||
| 62 | }; | ||
| 63 | |||
| 64 | pinctrl_usdhc3: usdhc3grp { | ||
| 65 | fsl,pins = < | ||
| 66 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 67 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 68 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 69 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 70 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 71 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 72 | >; | ||
| 73 | }; | ||
| 74 | }; | ||
| 75 | }; | ||
| 76 | |||
| 27 | &uart1 { | 77 | &uart1 { |
| 28 | pinctrl-names = "default"; | 78 | pinctrl-names = "default"; |
| 29 | pinctrl-0 = <&pinctrl_uart1_1>; | 79 | pinctrl-0 = <&pinctrl_uart1>; |
| 30 | status = "okay"; | 80 | status = "okay"; |
| 31 | }; | 81 | }; |
| 32 | 82 | ||
| 33 | &usbotg { | 83 | &usbotg { |
| 34 | pinctrl-names = "default"; | 84 | pinctrl-names = "default"; |
| 35 | pinctrl-0 = <&pinctrl_usbotg_1>; | 85 | pinctrl-0 = <&pinctrl_usbotg>; |
| 36 | disable-over-current; | 86 | disable-over-current; |
| 37 | status = "okay"; | 87 | status = "okay"; |
| 38 | }; | 88 | }; |
| 39 | 89 | ||
| 40 | &usdhc3 { | 90 | &usdhc3 { |
| 41 | pinctrl-names = "default"; | 91 | pinctrl-names = "default"; |
| 42 | pinctrl-0 = <&pinctrl_usdhc3_2>; | 92 | pinctrl-0 = <&pinctrl_usdhc3>; |
| 43 | status = "okay"; | 93 | status = "okay"; |
| 44 | }; | 94 | }; |
diff --git a/arch/arm/boot/dts/imx6q-udoo.dts b/arch/arm/boot/dts/imx6q-udoo.dts index 6e1ccdc019a7..ed397d149ab6 100644 --- a/arch/arm/boot/dts/imx6q-udoo.dts +++ b/arch/arm/boot/dts/imx6q-udoo.dts | |||
| @@ -21,19 +21,69 @@ | |||
| 21 | }; | 21 | }; |
| 22 | }; | 22 | }; |
| 23 | 23 | ||
| 24 | &fec { | ||
| 25 | pinctrl-names = "default"; | ||
| 26 | pinctrl-0 = <&pinctrl_enet>; | ||
| 27 | phy-mode = "rgmii"; | ||
| 28 | status = "okay"; | ||
| 29 | }; | ||
| 30 | |||
| 31 | &iomuxc { | ||
| 32 | imx6q-udoo { | ||
| 33 | pinctrl_enet: enetgrp { | ||
| 34 | fsl,pins = < | ||
| 35 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 36 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 37 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 38 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 39 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 40 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 41 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 42 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 43 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 44 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 45 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 46 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 47 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 48 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | ||
| 49 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | ||
| 50 | MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 | ||
| 51 | >; | ||
| 52 | }; | ||
| 53 | |||
| 54 | pinctrl_uart2: uart2grp { | ||
| 55 | fsl,pins = < | ||
| 56 | MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 | ||
| 57 | MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 | ||
| 58 | >; | ||
| 59 | }; | ||
| 60 | |||
| 61 | pinctrl_usdhc3: usdhc3grp { | ||
| 62 | fsl,pins = < | ||
| 63 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 64 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 65 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 66 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 67 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 68 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 69 | >; | ||
| 70 | }; | ||
| 71 | }; | ||
| 72 | }; | ||
| 73 | |||
| 24 | &sata { | 74 | &sata { |
| 25 | status = "okay"; | 75 | status = "okay"; |
| 26 | }; | 76 | }; |
| 27 | 77 | ||
| 28 | &uart2 { | 78 | &uart2 { |
| 29 | pinctrl-names = "default"; | 79 | pinctrl-names = "default"; |
| 30 | pinctrl-0 = <&pinctrl_uart2_1>; | 80 | pinctrl-0 = <&pinctrl_uart2>; |
| 31 | status = "okay"; | 81 | status = "okay"; |
| 32 | }; | 82 | }; |
| 33 | 83 | ||
| 34 | &usdhc3 { | 84 | &usdhc3 { |
| 35 | pinctrl-names = "default"; | 85 | pinctrl-names = "default"; |
| 36 | pinctrl-0 = <&pinctrl_usdhc3_2>; | 86 | pinctrl-0 = <&pinctrl_usdhc3>; |
| 37 | non-removable; | 87 | non-removable; |
| 38 | status = "okay"; | 88 | status = "okay"; |
| 39 | }; | 89 | }; |
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index f024ef28b34b..fadf4981c0ca 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi | |||
| @@ -8,10 +8,15 @@ | |||
| 8 | * | 8 | * |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 11 | #include "imx6q-pinfunc.h" | 12 | #include "imx6q-pinfunc.h" |
| 12 | #include "imx6qdl.dtsi" | 13 | #include "imx6qdl.dtsi" |
| 13 | 14 | ||
| 14 | / { | 15 | / { |
| 16 | aliases { | ||
| 17 | spi4 = &ecspi5; | ||
| 18 | }; | ||
| 19 | |||
| 15 | cpus { | 20 | cpus { |
| 16 | #address-cells = <1>; | 21 | #address-cells = <1>; |
| 17 | #size-cells = <0>; | 22 | #size-cells = <0>; |
| @@ -25,8 +30,17 @@ | |||
| 25 | /* kHz uV */ | 30 | /* kHz uV */ |
| 26 | 1200000 1275000 | 31 | 1200000 1275000 |
| 27 | 996000 1250000 | 32 | 996000 1250000 |
| 33 | 852000 1250000 | ||
| 28 | 792000 1150000 | 34 | 792000 1150000 |
| 29 | 396000 950000 | 35 | 396000 975000 |
| 36 | >; | ||
| 37 | fsl,soc-operating-points = < | ||
| 38 | /* ARM kHz SOC-PU uV */ | ||
| 39 | 1200000 1275000 | ||
| 40 | 996000 1250000 | ||
| 41 | 852000 1250000 | ||
| 42 | 792000 1175000 | ||
| 43 | 396000 1175000 | ||
| 30 | >; | 44 | >; |
| 31 | clock-latency = <61036>; /* two CLK32 periods */ | 45 | clock-latency = <61036>; /* two CLK32 periods */ |
| 32 | clocks = <&clks 104>, <&clks 6>, <&clks 16>, | 46 | clocks = <&clks 104>, <&clks 6>, <&clks 16>, |
| @@ -74,7 +88,7 @@ | |||
| 74 | #size-cells = <0>; | 88 | #size-cells = <0>; |
| 75 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | 89 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| 76 | reg = <0x02018000 0x4000>; | 90 | reg = <0x02018000 0x4000>; |
| 77 | interrupts = <0 35 0x04>; | 91 | interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; |
| 78 | clocks = <&clks 116>, <&clks 116>; | 92 | clocks = <&clks 116>, <&clks 116>; |
| 79 | clock-names = "ipg", "per"; | 93 | clock-names = "ipg", "per"; |
| 80 | status = "disabled"; | 94 | status = "disabled"; |
| @@ -125,7 +139,7 @@ | |||
| 125 | sata: sata@02200000 { | 139 | sata: sata@02200000 { |
| 126 | compatible = "fsl,imx6q-ahci"; | 140 | compatible = "fsl,imx6q-ahci"; |
| 127 | reg = <0x02200000 0x4000>; | 141 | reg = <0x02200000 0x4000>; |
| 128 | interrupts = <0 39 0x04>; | 142 | interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; |
| 129 | clocks = <&clks 154>, <&clks 187>, <&clks 105>; | 143 | clocks = <&clks 154>, <&clks 187>, <&clks 105>; |
| 130 | clock-names = "sata", "sata_ref", "ahb"; | 144 | clock-names = "sata", "sata_ref", "ahb"; |
| 131 | status = "disabled"; | 145 | status = "disabled"; |
| @@ -135,7 +149,8 @@ | |||
| 135 | #crtc-cells = <1>; | 149 | #crtc-cells = <1>; |
| 136 | compatible = "fsl,imx6q-ipu"; | 150 | compatible = "fsl,imx6q-ipu"; |
| 137 | reg = <0x02800000 0x400000>; | 151 | reg = <0x02800000 0x400000>; |
| 138 | interrupts = <0 8 0x4 0 7 0x4>; | 152 | interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, |
| 153 | <0 7 IRQ_TYPE_LEVEL_HIGH>; | ||
| 139 | clocks = <&clks 133>, <&clks 134>, <&clks 137>; | 154 | clocks = <&clks 133>, <&clks 134>, <&clks 137>; |
| 140 | clock-names = "bus", "di0", "di1"; | 155 | clock-names = "bus", "di0", "di1"; |
| 141 | resets = <&src 4>; | 156 | resets = <&src 4>; |
diff --git a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi new file mode 100644 index 000000000000..25cf035dd36e --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi | |||
| @@ -0,0 +1,199 @@ | |||
| 1 | / { | ||
| 2 | regulators { | ||
| 3 | compatible = "simple-bus"; | ||
| 4 | #address-cells = <1>; | ||
| 5 | #size-cells = <0>; | ||
| 6 | |||
| 7 | dummy_reg: regulator@0 { | ||
| 8 | compatible = "regulator-fixed"; | ||
| 9 | reg = <0>; | ||
| 10 | regulator-name = "dummy-supply"; | ||
| 11 | }; | ||
| 12 | |||
| 13 | reg_usb_otg_vbus: regulator@1 { | ||
| 14 | compatible = "regulator-fixed"; | ||
| 15 | reg = <1>; | ||
| 16 | regulator-name = "usb_otg_vbus"; | ||
| 17 | regulator-min-microvolt = <5000000>; | ||
| 18 | regulator-max-microvolt = <5000000>; | ||
| 19 | gpio = <&gpio3 22 0>; | ||
| 20 | enable-active-high; | ||
| 21 | }; | ||
| 22 | }; | ||
| 23 | |||
| 24 | chosen { | ||
| 25 | linux,stdout-path = &uart1; | ||
| 26 | }; | ||
| 27 | }; | ||
| 28 | |||
| 29 | &ecspi3 { | ||
| 30 | fsl,spi-num-chipselects = <1>; | ||
| 31 | cs-gpios = <&gpio4 24 0>; | ||
| 32 | pinctrl-names = "default"; | ||
| 33 | pinctrl-0 = <&pinctrl_ecspi3>; | ||
| 34 | status = "okay"; | ||
| 35 | |||
| 36 | flash: m25p80@0 { | ||
| 37 | #address-cells = <1>; | ||
| 38 | #size-cells = <1>; | ||
| 39 | compatible = "sst,sst25vf040b", "m25p80"; | ||
| 40 | spi-max-frequency = <20000000>; | ||
| 41 | reg = <0>; | ||
| 42 | }; | ||
| 43 | }; | ||
| 44 | |||
| 45 | &fec { | ||
| 46 | pinctrl-names = "default"; | ||
| 47 | pinctrl-0 = <&pinctrl_enet>; | ||
| 48 | status = "okay"; | ||
| 49 | phy-mode = "rgmii"; | ||
| 50 | }; | ||
| 51 | |||
| 52 | &iomuxc { | ||
| 53 | pinctrl-names = "default"; | ||
| 54 | pinctrl-0 = <&pinctrl_hog>; | ||
| 55 | |||
| 56 | imx6qdl-dfi-fs700-m60 { | ||
| 57 | pinctrl_hog: hoggrp { | ||
| 58 | fsl,pins = < | ||
| 59 | MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 | ||
| 60 | MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* PMIC irq */ | ||
| 61 | MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000 /* MAX11801 irq */ | ||
| 62 | MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000030b0 /* Backlight enable */ | ||
| 63 | >; | ||
| 64 | }; | ||
| 65 | |||
| 66 | pinctrl_enet: enetgrp { | ||
| 67 | fsl,pins = < | ||
| 68 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 69 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 70 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 71 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 72 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 73 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 74 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 75 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 76 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 77 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 78 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 79 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 80 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 81 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | ||
| 82 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | ||
| 83 | MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 | ||
| 84 | >; | ||
| 85 | }; | ||
| 86 | |||
| 87 | pinctrl_i2c2: i2c2grp { | ||
| 88 | fsl,pins = < | ||
| 89 | MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 | ||
| 90 | MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 | ||
| 91 | >; | ||
| 92 | }; | ||
| 93 | |||
| 94 | pinctrl_uart1: uart1grp { | ||
| 95 | fsl,pins = < | ||
| 96 | MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 | ||
| 97 | MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 | ||
| 98 | >; | ||
| 99 | }; | ||
| 100 | |||
| 101 | pinctrl_usbotg: usbotggrp { | ||
| 102 | fsl,pins = < | ||
| 103 | MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 | ||
| 104 | >; | ||
| 105 | }; | ||
| 106 | |||
| 107 | pinctrl_usdhc2: usdhc2grp { | ||
| 108 | fsl,pins = < | ||
| 109 | MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 | ||
| 110 | MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 | ||
| 111 | MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 | ||
| 112 | MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 | ||
| 113 | MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 | ||
| 114 | MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 | ||
| 115 | MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* card detect */ | ||
| 116 | >; | ||
| 117 | }; | ||
| 118 | |||
| 119 | pinctrl_usdhc3: usdhc3grp { | ||
| 120 | fsl,pins = < | ||
| 121 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 122 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 123 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 124 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 125 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 126 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 127 | >; | ||
| 128 | }; | ||
| 129 | |||
| 130 | pinctrl_usdhc4: usdhc4grp { | ||
| 131 | fsl,pins = < | ||
| 132 | MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 | ||
| 133 | MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 | ||
| 134 | MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 | ||
| 135 | MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 | ||
| 136 | MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 | ||
| 137 | MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 | ||
| 138 | MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 | ||
| 139 | MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 | ||
| 140 | MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 | ||
| 141 | MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 | ||
| 142 | >; | ||
| 143 | }; | ||
| 144 | |||
| 145 | pinctrl_ecspi3: ecspi3grp { | ||
| 146 | fsl,pins = < | ||
| 147 | MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 | ||
| 148 | MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 | ||
| 149 | MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 | ||
| 150 | MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */ | ||
| 151 | >; | ||
| 152 | }; | ||
| 153 | }; | ||
| 154 | }; | ||
| 155 | |||
| 156 | &i2c2 { | ||
| 157 | pinctrl-names = "default"; | ||
| 158 | pinctrl-0 = <&pinctrl_i2c2>; | ||
| 159 | status = "okay"; | ||
| 160 | }; | ||
| 161 | |||
| 162 | &uart1 { | ||
| 163 | pinctrl-names = "default"; | ||
| 164 | pinctrl-0 = <&pinctrl_uart1>; | ||
| 165 | status = "okay"; | ||
| 166 | }; | ||
| 167 | |||
| 168 | &usbh1 { | ||
| 169 | status = "okay"; | ||
| 170 | }; | ||
| 171 | |||
| 172 | &usbotg { | ||
| 173 | vbus-supply = <®_usb_otg_vbus>; | ||
| 174 | pinctrl-names = "default"; | ||
| 175 | pinctrl-0 = <&pinctrl_usbotg>; | ||
| 176 | disable-over-current; | ||
| 177 | dr_mode = "host"; | ||
| 178 | status = "okay"; | ||
| 179 | }; | ||
| 180 | |||
| 181 | &usdhc2 { /* module slot */ | ||
| 182 | pinctrl-names = "default"; | ||
| 183 | pinctrl-0 = <&pinctrl_usdhc2>; | ||
| 184 | cd-gpios = <&gpio2 2 0>; | ||
| 185 | status = "okay"; | ||
| 186 | }; | ||
| 187 | |||
| 188 | &usdhc3 { /* baseboard slot */ | ||
| 189 | pinctrl-names = "default"; | ||
| 190 | pinctrl-0 = <&pinctrl_usdhc3>; | ||
| 191 | }; | ||
| 192 | |||
| 193 | &usdhc4 { /* eMMC */ | ||
| 194 | pinctrl-names = "default"; | ||
| 195 | pinctrl-0 = <&pinctrl_usdhc4>; | ||
| 196 | bus-width = <8>; | ||
| 197 | non-removable; | ||
| 198 | status = "okay"; | ||
| 199 | }; | ||
diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi new file mode 100644 index 000000000000..98a422153ce7 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi | |||
| @@ -0,0 +1,374 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Gateworks Corporation | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | / { | ||
| 13 | /* these are used by bootloader for disabling nodes */ | ||
| 14 | aliases { | ||
| 15 | can0 = &can1; | ||
| 16 | ethernet0 = &fec; | ||
| 17 | led0 = &led0; | ||
| 18 | led1 = &led1; | ||
| 19 | nand = &gpmi; | ||
| 20 | usb0 = &usbh1; | ||
| 21 | usb1 = &usbotg; | ||
| 22 | }; | ||
| 23 | |||
| 24 | chosen { | ||
| 25 | bootargs = "console=ttymxc1,115200"; | ||
| 26 | }; | ||
| 27 | |||
| 28 | leds { | ||
| 29 | compatible = "gpio-leds"; | ||
| 30 | |||
| 31 | led0: user1 { | ||
| 32 | label = "user1"; | ||
| 33 | gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ | ||
| 34 | default-state = "on"; | ||
| 35 | linux,default-trigger = "heartbeat"; | ||
| 36 | }; | ||
| 37 | |||
| 38 | led1: user2 { | ||
| 39 | label = "user2"; | ||
| 40 | gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ | ||
| 41 | default-state = "off"; | ||
| 42 | }; | ||
| 43 | }; | ||
| 44 | |||
| 45 | memory { | ||
| 46 | reg = <0x10000000 0x20000000>; | ||
| 47 | }; | ||
| 48 | |||
| 49 | pps { | ||
| 50 | compatible = "pps-gpio"; | ||
| 51 | gpios = <&gpio1 26 0>; | ||
| 52 | status = "okay"; | ||
| 53 | }; | ||
| 54 | |||
| 55 | regulators { | ||
| 56 | compatible = "simple-bus"; | ||
| 57 | #address-cells = <1>; | ||
| 58 | #size-cells = <0>; | ||
| 59 | |||
| 60 | reg_3p3v: regulator@0 { | ||
| 61 | compatible = "regulator-fixed"; | ||
| 62 | reg = <0>; | ||
| 63 | regulator-name = "3P3V"; | ||
| 64 | regulator-min-microvolt = <3300000>; | ||
| 65 | regulator-max-microvolt = <3300000>; | ||
| 66 | regulator-always-on; | ||
| 67 | }; | ||
| 68 | |||
| 69 | reg_5p0v: regulator@1 { | ||
| 70 | compatible = "regulator-fixed"; | ||
| 71 | reg = <1>; | ||
| 72 | regulator-name = "5P0V"; | ||
| 73 | regulator-min-microvolt = <5000000>; | ||
| 74 | regulator-max-microvolt = <5000000>; | ||
| 75 | regulator-always-on; | ||
| 76 | }; | ||
| 77 | |||
| 78 | reg_usb_otg_vbus: regulator@2 { | ||
| 79 | compatible = "regulator-fixed"; | ||
| 80 | reg = <2>; | ||
| 81 | regulator-name = "usb_otg_vbus"; | ||
| 82 | regulator-min-microvolt = <5000000>; | ||
| 83 | regulator-max-microvolt = <5000000>; | ||
| 84 | gpio = <&gpio3 22 0>; | ||
| 85 | enable-active-high; | ||
| 86 | }; | ||
| 87 | }; | ||
| 88 | }; | ||
| 89 | |||
| 90 | &fec { | ||
| 91 | pinctrl-names = "default"; | ||
| 92 | pinctrl-0 = <&pinctrl_enet>; | ||
| 93 | phy-mode = "rgmii"; | ||
| 94 | phy-reset-gpios = <&gpio1 30 0>; | ||
| 95 | status = "okay"; | ||
| 96 | }; | ||
| 97 | |||
| 98 | &gpmi { | ||
| 99 | pinctrl-names = "default"; | ||
| 100 | pinctrl-0 = <&pinctrl_gpmi_nand>; | ||
| 101 | status = "okay"; | ||
| 102 | }; | ||
| 103 | |||
| 104 | &i2c1 { | ||
| 105 | clock-frequency = <100000>; | ||
| 106 | pinctrl-names = "default"; | ||
| 107 | pinctrl-0 = <&pinctrl_i2c1>; | ||
| 108 | status = "okay"; | ||
| 109 | |||
| 110 | eeprom1: eeprom@50 { | ||
| 111 | compatible = "atmel,24c02"; | ||
| 112 | reg = <0x50>; | ||
| 113 | pagesize = <16>; | ||
| 114 | }; | ||
| 115 | |||
| 116 | eeprom2: eeprom@51 { | ||
| 117 | compatible = "atmel,24c02"; | ||
| 118 | reg = <0x51>; | ||
| 119 | pagesize = <16>; | ||
| 120 | }; | ||
| 121 | |||
| 122 | eeprom3: eeprom@52 { | ||
| 123 | compatible = "atmel,24c02"; | ||
| 124 | reg = <0x52>; | ||
| 125 | pagesize = <16>; | ||
| 126 | }; | ||
| 127 | |||
| 128 | eeprom4: eeprom@53 { | ||
| 129 | compatible = "atmel,24c02"; | ||
| 130 | reg = <0x53>; | ||
| 131 | pagesize = <16>; | ||
| 132 | }; | ||
| 133 | |||
| 134 | gpio: pca9555@23 { | ||
| 135 | compatible = "nxp,pca9555"; | ||
| 136 | reg = <0x23>; | ||
| 137 | gpio-controller; | ||
| 138 | #gpio-cells = <2>; | ||
| 139 | }; | ||
| 140 | |||
| 141 | hwmon: gsc@29 { | ||
| 142 | compatible = "gw,gsp"; | ||
| 143 | reg = <0x29>; | ||
| 144 | }; | ||
| 145 | |||
| 146 | rtc: ds1672@68 { | ||
| 147 | compatible = "dallas,ds1672"; | ||
| 148 | reg = <0x68>; | ||
| 149 | }; | ||
| 150 | }; | ||
| 151 | |||
| 152 | &i2c2 { | ||
| 153 | clock-frequency = <100000>; | ||
| 154 | pinctrl-names = "default"; | ||
| 155 | pinctrl-0 = <&pinctrl_i2c2>; | ||
| 156 | status = "okay"; | ||
| 157 | |||
| 158 | pmic: ltc3676@3c { | ||
| 159 | compatible = "ltc,ltc3676"; | ||
| 160 | reg = <0x3c>; | ||
| 161 | |||
| 162 | regulators { | ||
| 163 | sw1_reg: ltc3676__sw1 { | ||
| 164 | regulator-min-microvolt = <1175000>; | ||
| 165 | regulator-max-microvolt = <1175000>; | ||
| 166 | regulator-boot-on; | ||
| 167 | regulator-always-on; | ||
| 168 | }; | ||
| 169 | |||
| 170 | sw2_reg: ltc3676__sw2 { | ||
| 171 | regulator-min-microvolt = <1800000>; | ||
| 172 | regulator-max-microvolt = <1800000>; | ||
| 173 | regulator-boot-on; | ||
| 174 | regulator-always-on; | ||
| 175 | }; | ||
| 176 | |||
| 177 | sw3_reg: ltc3676__sw3 { | ||
| 178 | regulator-min-microvolt = <1175000>; | ||
| 179 | regulator-max-microvolt = <1175000>; | ||
| 180 | regulator-boot-on; | ||
| 181 | regulator-always-on; | ||
| 182 | }; | ||
| 183 | |||
| 184 | sw4_reg: ltc3676__sw4 { | ||
| 185 | regulator-min-microvolt = <1500000>; | ||
| 186 | regulator-max-microvolt = <1500000>; | ||
| 187 | regulator-boot-on; | ||
| 188 | regulator-always-on; | ||
| 189 | }; | ||
| 190 | |||
| 191 | ldo2_reg: ltc3676__ldo2 { | ||
| 192 | regulator-min-microvolt = <2500000>; | ||
| 193 | regulator-max-microvolt = <2500000>; | ||
| 194 | regulator-boot-on; | ||
| 195 | regulator-always-on; | ||
| 196 | }; | ||
| 197 | |||
| 198 | ldo4_reg: ltc3676__ldo4 { | ||
| 199 | regulator-min-microvolt = <3000000>; | ||
| 200 | regulator-max-microvolt = <3000000>; | ||
| 201 | }; | ||
| 202 | }; | ||
| 203 | }; | ||
| 204 | }; | ||
| 205 | |||
| 206 | &i2c3 { | ||
| 207 | clock-frequency = <100000>; | ||
| 208 | pinctrl-names = "default"; | ||
| 209 | pinctrl-0 = <&pinctrl_i2c3>; | ||
| 210 | status = "okay"; | ||
| 211 | |||
| 212 | videoin: adv7180@20 { | ||
| 213 | compatible = "adi,adv7180"; | ||
| 214 | reg = <0x20>; | ||
| 215 | }; | ||
| 216 | }; | ||
| 217 | |||
| 218 | &iomuxc { | ||
| 219 | pinctrl-names = "default"; | ||
| 220 | pinctrl-0 = <&pinctrl_hog>; | ||
| 221 | |||
| 222 | imx6qdl-gw51xx { | ||
| 223 | pinctrl_hog: hoggrp { | ||
| 224 | fsl,pins = < | ||
| 225 | MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* MEZZ_DIO0 */ | ||
| 226 | MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* MEZZ_DIO1 */ | ||
| 227 | MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ | ||
| 228 | MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ | ||
| 229 | MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */ | ||
| 230 | MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x80000000 /* PCIE_RST# */ | ||
| 231 | MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ | ||
| 232 | MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ | ||
| 233 | >; | ||
| 234 | }; | ||
| 235 | |||
| 236 | pinctrl_enet: enetgrp { | ||
| 237 | fsl,pins = < | ||
| 238 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 239 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 240 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 241 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 242 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 243 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 244 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 245 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 246 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 247 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 248 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 249 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 250 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 251 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | ||
| 252 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | ||
| 253 | MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 | ||
| 254 | >; | ||
| 255 | }; | ||
| 256 | |||
| 257 | pinctrl_gpmi_nand: gpminandgrp { | ||
| 258 | fsl,pins = < | ||
| 259 | MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 | ||
| 260 | MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 | ||
| 261 | MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 | ||
| 262 | MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 | ||
| 263 | MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 | ||
| 264 | MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 | ||
| 265 | MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 | ||
| 266 | MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 | ||
| 267 | MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 | ||
| 268 | MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 | ||
| 269 | MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 | ||
| 270 | MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 | ||
| 271 | MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 | ||
| 272 | MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 | ||
| 273 | MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 | ||
| 274 | MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 | ||
| 275 | >; | ||
| 276 | }; | ||
| 277 | |||
| 278 | pinctrl_i2c1: i2c1grp { | ||
| 279 | fsl,pins = < | ||
| 280 | MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 | ||
| 281 | MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 | ||
| 282 | >; | ||
| 283 | }; | ||
| 284 | |||
| 285 | pinctrl_i2c2: i2c2grp { | ||
| 286 | fsl,pins = < | ||
| 287 | MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 | ||
| 288 | MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 | ||
| 289 | >; | ||
| 290 | }; | ||
| 291 | |||
| 292 | pinctrl_i2c3: i2c3grp { | ||
| 293 | fsl,pins = < | ||
| 294 | MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 | ||
| 295 | MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 | ||
| 296 | >; | ||
| 297 | }; | ||
| 298 | |||
| 299 | pinctrl_uart1: uart1grp { | ||
| 300 | fsl,pins = < | ||
| 301 | MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 | ||
| 302 | MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 | ||
| 303 | >; | ||
| 304 | }; | ||
| 305 | |||
| 306 | pinctrl_uart2: uart2grp { | ||
| 307 | fsl,pins = < | ||
| 308 | MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 | ||
| 309 | MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 | ||
| 310 | >; | ||
| 311 | }; | ||
| 312 | |||
| 313 | pinctrl_uart3: uart3grp { | ||
| 314 | fsl,pins = < | ||
| 315 | MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 | ||
| 316 | MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 | ||
| 317 | >; | ||
| 318 | }; | ||
| 319 | |||
| 320 | pinctrl_uart5: uart5grp { | ||
| 321 | fsl,pins = < | ||
| 322 | MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 | ||
| 323 | MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 | ||
| 324 | >; | ||
| 325 | }; | ||
| 326 | |||
| 327 | pinctrl_usbotg: usbotggrp { | ||
| 328 | fsl,pins = < | ||
| 329 | MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 | ||
| 330 | >; | ||
| 331 | }; | ||
| 332 | }; | ||
| 333 | }; | ||
| 334 | |||
| 335 | &pcie { | ||
| 336 | reset-gpio = <&gpio1 0 0>; | ||
| 337 | status = "okay"; | ||
| 338 | }; | ||
| 339 | |||
| 340 | &uart1 { | ||
| 341 | pinctrl-names = "default"; | ||
| 342 | pinctrl-0 = <&pinctrl_uart1>; | ||
| 343 | status = "okay"; | ||
| 344 | }; | ||
| 345 | |||
| 346 | &uart2 { | ||
| 347 | pinctrl-names = "default"; | ||
| 348 | pinctrl-0 = <&pinctrl_uart2>; | ||
| 349 | status = "okay"; | ||
| 350 | }; | ||
| 351 | |||
| 352 | &uart3 { | ||
| 353 | pinctrl-names = "default"; | ||
| 354 | pinctrl-0 = <&pinctrl_uart3>; | ||
| 355 | status = "okay"; | ||
| 356 | }; | ||
| 357 | |||
| 358 | &uart5 { | ||
| 359 | pinctrl-names = "default"; | ||
| 360 | pinctrl-0 = <&pinctrl_uart5>; | ||
| 361 | status = "okay"; | ||
| 362 | }; | ||
| 363 | |||
| 364 | &usbotg { | ||
| 365 | vbus-supply = <®_usb_otg_vbus>; | ||
| 366 | pinctrl-names = "default"; | ||
| 367 | pinctrl-0 = <&pinctrl_usbotg>; | ||
| 368 | disable-over-current; | ||
| 369 | status = "okay"; | ||
| 370 | }; | ||
| 371 | |||
| 372 | &usbh1 { | ||
| 373 | status = "okay"; | ||
| 374 | }; | ||
diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi new file mode 100644 index 000000000000..8e99c9a9bc76 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | |||
| @@ -0,0 +1,490 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Gateworks Corporation | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | / { | ||
| 13 | /* these are used by bootloader for disabling nodes */ | ||
| 14 | aliases { | ||
| 15 | ethernet0 = &fec; | ||
| 16 | led0 = &led0; | ||
| 17 | led1 = &led1; | ||
| 18 | led2 = &led2; | ||
| 19 | nand = &gpmi; | ||
| 20 | ssi0 = &ssi1; | ||
| 21 | usb0 = &usbh1; | ||
| 22 | usb1 = &usbotg; | ||
| 23 | usdhc2 = &usdhc3; | ||
| 24 | }; | ||
| 25 | |||
| 26 | chosen { | ||
| 27 | bootargs = "console=ttymxc1,115200"; | ||
| 28 | }; | ||
| 29 | |||
| 30 | leds { | ||
| 31 | compatible = "gpio-leds"; | ||
| 32 | |||
| 33 | led0: user1 { | ||
| 34 | label = "user1"; | ||
| 35 | gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ | ||
| 36 | default-state = "on"; | ||
| 37 | linux,default-trigger = "heartbeat"; | ||
| 38 | }; | ||
| 39 | |||
| 40 | led1: user2 { | ||
| 41 | label = "user2"; | ||
| 42 | gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ | ||
| 43 | default-state = "off"; | ||
| 44 | }; | ||
| 45 | |||
| 46 | led2: user3 { | ||
| 47 | label = "user3"; | ||
| 48 | gpios = <&gpio4 15 1>; /* 111 - MX6_LOCLED# */ | ||
| 49 | default-state = "off"; | ||
| 50 | }; | ||
| 51 | }; | ||
| 52 | |||
| 53 | memory { | ||
| 54 | reg = <0x10000000 0x20000000>; | ||
| 55 | }; | ||
| 56 | |||
| 57 | pps { | ||
| 58 | compatible = "pps-gpio"; | ||
| 59 | gpios = <&gpio1 26 0>; | ||
| 60 | status = "okay"; | ||
| 61 | }; | ||
| 62 | |||
| 63 | regulators { | ||
| 64 | compatible = "simple-bus"; | ||
| 65 | #address-cells = <1>; | ||
| 66 | #size-cells = <0>; | ||
| 67 | |||
| 68 | reg_1p0v: regulator@0 { | ||
| 69 | compatible = "regulator-fixed"; | ||
| 70 | reg = <0>; | ||
| 71 | regulator-name = "1P0V"; | ||
| 72 | regulator-min-microvolt = <1000000>; | ||
| 73 | regulator-max-microvolt = <1000000>; | ||
| 74 | regulator-always-on; | ||
| 75 | }; | ||
| 76 | |||
| 77 | /* remove this fixed regulator once ltc3676__sw2 driver available */ | ||
| 78 | reg_1p8v: regulator@1 { | ||
| 79 | compatible = "regulator-fixed"; | ||
| 80 | reg = <1>; | ||
| 81 | regulator-name = "1P8V"; | ||
| 82 | regulator-min-microvolt = <1800000>; | ||
| 83 | regulator-max-microvolt = <1800000>; | ||
| 84 | regulator-always-on; | ||
| 85 | }; | ||
| 86 | |||
| 87 | reg_3p3v: regulator@2 { | ||
| 88 | compatible = "regulator-fixed"; | ||
| 89 | reg = <2>; | ||
| 90 | regulator-name = "3P3V"; | ||
| 91 | regulator-min-microvolt = <3300000>; | ||
| 92 | regulator-max-microvolt = <3300000>; | ||
| 93 | regulator-always-on; | ||
| 94 | }; | ||
| 95 | |||
| 96 | reg_5p0v: regulator@3 { | ||
| 97 | compatible = "regulator-fixed"; | ||
| 98 | reg = <3>; | ||
| 99 | regulator-name = "5P0V"; | ||
| 100 | regulator-min-microvolt = <5000000>; | ||
| 101 | regulator-max-microvolt = <5000000>; | ||
| 102 | regulator-always-on; | ||
| 103 | }; | ||
| 104 | |||
| 105 | reg_usb_otg_vbus: regulator@4 { | ||
| 106 | compatible = "regulator-fixed"; | ||
| 107 | reg = <4>; | ||
| 108 | regulator-name = "usb_otg_vbus"; | ||
| 109 | regulator-min-microvolt = <5000000>; | ||
| 110 | regulator-max-microvolt = <5000000>; | ||
| 111 | gpio = <&gpio3 22 0>; | ||
| 112 | enable-active-high; | ||
| 113 | }; | ||
| 114 | }; | ||
| 115 | |||
| 116 | sound { | ||
| 117 | compatible = "fsl,imx6q-sabrelite-sgtl5000", | ||
| 118 | "fsl,imx-audio-sgtl5000"; | ||
| 119 | model = "imx6q-sabrelite-sgtl5000"; | ||
| 120 | ssi-controller = <&ssi1>; | ||
| 121 | audio-codec = <&codec>; | ||
| 122 | audio-routing = | ||
| 123 | "MIC_IN", "Mic Jack", | ||
| 124 | "Mic Jack", "Mic Bias", | ||
| 125 | "Headphone Jack", "HP_OUT"; | ||
| 126 | mux-int-port = <1>; | ||
| 127 | mux-ext-port = <4>; | ||
| 128 | }; | ||
| 129 | }; | ||
| 130 | |||
| 131 | &audmux { | ||
| 132 | pinctrl-names = "default"; | ||
| 133 | pinctrl-0 = <&pinctrl_audmux>; | ||
| 134 | status = "okay"; | ||
| 135 | }; | ||
| 136 | |||
| 137 | &fec { | ||
| 138 | pinctrl-names = "default"; | ||
| 139 | pinctrl-0 = <&pinctrl_enet>; | ||
| 140 | phy-mode = "rgmii"; | ||
| 141 | phy-reset-gpios = <&gpio1 30 0>; | ||
| 142 | status = "okay"; | ||
| 143 | }; | ||
| 144 | |||
| 145 | &gpmi { | ||
| 146 | pinctrl-names = "default"; | ||
| 147 | pinctrl-0 = <&pinctrl_gpmi_nand>; | ||
| 148 | status = "okay"; | ||
| 149 | }; | ||
| 150 | |||
| 151 | &i2c1 { | ||
| 152 | clock-frequency = <100000>; | ||
| 153 | pinctrl-names = "default"; | ||
| 154 | pinctrl-0 = <&pinctrl_i2c1>; | ||
| 155 | status = "okay"; | ||
| 156 | |||
| 157 | eeprom1: eeprom@50 { | ||
| 158 | compatible = "atmel,24c02"; | ||
| 159 | reg = <0x50>; | ||
| 160 | pagesize = <16>; | ||
| 161 | }; | ||
| 162 | |||
| 163 | eeprom2: eeprom@51 { | ||
| 164 | compatible = "atmel,24c02"; | ||
| 165 | reg = <0x51>; | ||
| 166 | pagesize = <16>; | ||
| 167 | }; | ||
| 168 | |||
| 169 | eeprom3: eeprom@52 { | ||
| 170 | compatible = "atmel,24c02"; | ||
| 171 | reg = <0x52>; | ||
| 172 | pagesize = <16>; | ||
| 173 | }; | ||
| 174 | |||
| 175 | eeprom4: eeprom@53 { | ||
| 176 | compatible = "atmel,24c02"; | ||
| 177 | reg = <0x53>; | ||
| 178 | pagesize = <16>; | ||
| 179 | }; | ||
| 180 | |||
| 181 | gpio: pca9555@23 { | ||
| 182 | compatible = "nxp,pca9555"; | ||
| 183 | reg = <0x23>; | ||
| 184 | gpio-controller; | ||
| 185 | #gpio-cells = <2>; | ||
| 186 | }; | ||
| 187 | |||
| 188 | hwmon: gsc@29 { | ||
| 189 | compatible = "gw,gsp"; | ||
| 190 | reg = <0x29>; | ||
| 191 | }; | ||
| 192 | |||
| 193 | rtc: ds1672@68 { | ||
| 194 | compatible = "dallas,ds1672"; | ||
| 195 | reg = <0x68>; | ||
| 196 | }; | ||
| 197 | }; | ||
| 198 | |||
| 199 | &i2c2 { | ||
| 200 | clock-frequency = <100000>; | ||
| 201 | pinctrl-names = "default"; | ||
| 202 | pinctrl-0 = <&pinctrl_i2c2>; | ||
| 203 | status = "okay"; | ||
| 204 | |||
| 205 | pciswitch: pex8609@3f { | ||
| 206 | compatible = "plx,pex8609"; | ||
| 207 | reg = <0x3f>; | ||
| 208 | }; | ||
| 209 | |||
| 210 | pmic: ltc3676@3c { | ||
| 211 | compatible = "ltc,ltc3676"; | ||
| 212 | reg = <0x3c>; | ||
| 213 | |||
| 214 | regulators { | ||
| 215 | sw1_reg: ltc3676__sw1 { | ||
| 216 | regulator-min-microvolt = <1175000>; | ||
| 217 | regulator-max-microvolt = <1175000>; | ||
| 218 | regulator-boot-on; | ||
| 219 | regulator-always-on; | ||
| 220 | }; | ||
| 221 | |||
| 222 | sw2_reg: ltc3676__sw2 { | ||
| 223 | regulator-min-microvolt = <1800000>; | ||
| 224 | regulator-max-microvolt = <1800000>; | ||
| 225 | regulator-boot-on; | ||
| 226 | regulator-always-on; | ||
| 227 | }; | ||
| 228 | |||
| 229 | sw3_reg: ltc3676__sw3 { | ||
| 230 | regulator-min-microvolt = <1175000>; | ||
| 231 | regulator-max-microvolt = <1175000>; | ||
| 232 | regulator-boot-on; | ||
| 233 | regulator-always-on; | ||
| 234 | }; | ||
| 235 | |||
| 236 | sw4_reg: ltc3676__sw4 { | ||
| 237 | regulator-min-microvolt = <1500000>; | ||
| 238 | regulator-max-microvolt = <1500000>; | ||
| 239 | regulator-boot-on; | ||
| 240 | regulator-always-on; | ||
| 241 | }; | ||
| 242 | |||
| 243 | ldo2_reg: ltc3676__ldo2 { | ||
| 244 | regulator-min-microvolt = <2500000>; | ||
| 245 | regulator-max-microvolt = <2500000>; | ||
| 246 | regulator-boot-on; | ||
| 247 | regulator-always-on; | ||
| 248 | }; | ||
| 249 | |||
| 250 | ldo3_reg: ltc3676__ldo3 { | ||
| 251 | regulator-min-microvolt = <1800000>; | ||
| 252 | regulator-max-microvolt = <1800000>; | ||
| 253 | regulator-boot-on; | ||
| 254 | regulator-always-on; | ||
| 255 | }; | ||
| 256 | |||
| 257 | ldo4_reg: ltc3676__ldo4 { | ||
| 258 | regulator-min-microvolt = <3000000>; | ||
| 259 | regulator-max-microvolt = <3000000>; | ||
| 260 | }; | ||
| 261 | }; | ||
| 262 | }; | ||
| 263 | }; | ||
| 264 | |||
| 265 | &i2c3 { | ||
| 266 | clock-frequency = <100000>; | ||
| 267 | pinctrl-names = "default"; | ||
| 268 | pinctrl-0 = <&pinctrl_i2c3>; | ||
| 269 | status = "okay"; | ||
| 270 | |||
| 271 | accelerometer: fxos8700@1e { | ||
| 272 | compatible = "fsl,fxos8700"; | ||
| 273 | reg = <0x13>; | ||
| 274 | }; | ||
| 275 | |||
| 276 | codec: sgtl5000@0a { | ||
| 277 | compatible = "fsl,sgtl5000"; | ||
| 278 | reg = <0x0a>; | ||
| 279 | clocks = <&clks 169>; | ||
| 280 | VDDA-supply = <®_1p8v>; | ||
| 281 | VDDIO-supply = <®_3p3v>; | ||
| 282 | }; | ||
| 283 | |||
| 284 | touchscreen: egalax_ts@04 { | ||
| 285 | compatible = "eeti,egalax_ts"; | ||
| 286 | reg = <0x04>; | ||
| 287 | interrupt-parent = <&gpio7>; | ||
| 288 | interrupts = <12 2>; /* gpio7_12 active low */ | ||
| 289 | wakeup-gpios = <&gpio7 12 0>; | ||
| 290 | }; | ||
| 291 | |||
| 292 | videoin: adv7180@20 { | ||
| 293 | compatible = "adi,adv7180"; | ||
| 294 | reg = <0x20>; | ||
| 295 | }; | ||
| 296 | }; | ||
| 297 | |||
| 298 | &iomuxc { | ||
| 299 | pinctrl-names = "default"; | ||
| 300 | pinctrl-0 = <&pinctrl_hog>; | ||
| 301 | |||
| 302 | imx6qdl-gw52xx { | ||
| 303 | pinctrl_hog: hoggrp { | ||
| 304 | fsl,pins = < | ||
| 305 | MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* MEZZ_DIO0 */ | ||
| 306 | MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* MEZZ_DIO1 */ | ||
| 307 | MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ | ||
| 308 | MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x80000000 /* VIDDEC_PDN# */ | ||
| 309 | MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */ | ||
| 310 | MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE_RST# */ | ||
| 311 | MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 /* GPS_PWDN */ | ||
| 312 | MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ | ||
| 313 | MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ | ||
| 314 | MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* USB_SEL_PCI */ | ||
| 315 | MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */ | ||
| 316 | MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ | ||
| 317 | MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ | ||
| 318 | MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ | ||
| 319 | MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x80000000 /* LVDS_TCH# */ | ||
| 320 | MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3_CD# */ | ||
| 321 | MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000 /* UART2_EN# */ | ||
| 322 | >; | ||
| 323 | }; | ||
| 324 | |||
| 325 | pinctrl_audmux: audmuxgrp { | ||
| 326 | fsl,pins = < | ||
| 327 | MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 | ||
| 328 | MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 | ||
| 329 | MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 | ||
| 330 | MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 | ||
| 331 | >; | ||
| 332 | }; | ||
| 333 | |||
| 334 | pinctrl_enet: enetgrp { | ||
| 335 | fsl,pins = < | ||
| 336 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 337 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 338 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 339 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 340 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 341 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 342 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 343 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 344 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 345 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 346 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 347 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 348 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 349 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | ||
| 350 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | ||
| 351 | MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 | ||
| 352 | >; | ||
| 353 | }; | ||
| 354 | |||
| 355 | pinctrl_gpmi_nand: gpminandgrp { | ||
| 356 | fsl,pins = < | ||
| 357 | MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 | ||
| 358 | MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 | ||
| 359 | MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 | ||
| 360 | MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 | ||
| 361 | MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 | ||
| 362 | MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 | ||
| 363 | MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 | ||
| 364 | MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 | ||
| 365 | MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 | ||
| 366 | MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 | ||
| 367 | MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 | ||
| 368 | MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 | ||
| 369 | MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 | ||
| 370 | MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 | ||
| 371 | MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 | ||
| 372 | MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 | ||
| 373 | >; | ||
| 374 | }; | ||
| 375 | |||
| 376 | pinctrl_i2c1: i2c1grp { | ||
| 377 | fsl,pins = < | ||
| 378 | MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 | ||
| 379 | MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 | ||
| 380 | >; | ||
| 381 | }; | ||
| 382 | |||
| 383 | pinctrl_i2c2: i2c2grp { | ||
| 384 | fsl,pins = < | ||
| 385 | MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 | ||
| 386 | MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 | ||
| 387 | >; | ||
| 388 | }; | ||
| 389 | |||
| 390 | pinctrl_i2c3: i2c3grp { | ||
| 391 | fsl,pins = < | ||
| 392 | MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 | ||
| 393 | MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 | ||
| 394 | >; | ||
| 395 | }; | ||
| 396 | |||
| 397 | pinctrl_uart1: uart1grp { | ||
| 398 | fsl,pins = < | ||
| 399 | MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 | ||
| 400 | MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 | ||
| 401 | >; | ||
| 402 | }; | ||
| 403 | |||
| 404 | pinctrl_uart2: uart2grp { | ||
| 405 | fsl,pins = < | ||
| 406 | MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 | ||
| 407 | MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 | ||
| 408 | >; | ||
| 409 | }; | ||
| 410 | |||
| 411 | pinctrl_uart5: uart5grp { | ||
| 412 | fsl,pins = < | ||
| 413 | MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 | ||
| 414 | MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 | ||
| 415 | >; | ||
| 416 | }; | ||
| 417 | |||
| 418 | pinctrl_usbotg: usbotggrp { | ||
| 419 | fsl,pins = < | ||
| 420 | MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 | ||
| 421 | >; | ||
| 422 | }; | ||
| 423 | |||
| 424 | pinctrl_usdhc3: usdhc3grp { | ||
| 425 | fsl,pins = < | ||
| 426 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 427 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 428 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 429 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 430 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 431 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 432 | >; | ||
| 433 | }; | ||
| 434 | }; | ||
| 435 | }; | ||
| 436 | |||
| 437 | &ldb { | ||
| 438 | status = "okay"; | ||
| 439 | lvds-channel@0 { | ||
| 440 | crtcs = <&ipu1 0>, <&ipu1 1>; | ||
| 441 | }; | ||
| 442 | }; | ||
| 443 | |||
| 444 | &pcie { | ||
| 445 | reset-gpio = <&gpio1 29 0>; | ||
| 446 | status = "okay"; | ||
| 447 | }; | ||
| 448 | |||
| 449 | &ssi1 { | ||
| 450 | fsl,mode = "i2s-slave"; | ||
| 451 | status = "okay"; | ||
| 452 | }; | ||
| 453 | |||
| 454 | &uart1 { | ||
| 455 | pinctrl-names = "default"; | ||
| 456 | pinctrl-0 = <&pinctrl_uart1>; | ||
| 457 | status = "okay"; | ||
| 458 | }; | ||
| 459 | |||
| 460 | &uart2 { | ||
| 461 | pinctrl-names = "default"; | ||
| 462 | pinctrl-0 = <&pinctrl_uart2>; | ||
| 463 | status = "okay"; | ||
| 464 | }; | ||
| 465 | |||
| 466 | &uart5 { | ||
| 467 | pinctrl-names = "default"; | ||
| 468 | pinctrl-0 = <&pinctrl_uart5>; | ||
| 469 | status = "okay"; | ||
| 470 | }; | ||
| 471 | |||
| 472 | &usbotg { | ||
| 473 | vbus-supply = <®_usb_otg_vbus>; | ||
| 474 | pinctrl-names = "default"; | ||
| 475 | pinctrl-0 = <&pinctrl_usbotg>; | ||
| 476 | disable-over-current; | ||
| 477 | status = "okay"; | ||
| 478 | }; | ||
| 479 | |||
| 480 | &usbh1 { | ||
| 481 | status = "okay"; | ||
| 482 | }; | ||
| 483 | |||
| 484 | &usdhc3 { | ||
| 485 | pinctrl-names = "default"; | ||
| 486 | pinctrl-0 = <&pinctrl_usdhc3>; | ||
| 487 | cd-gpios = <&gpio7 0 0>; | ||
| 488 | vmmc-supply = <®_3p3v>; | ||
| 489 | status = "okay"; | ||
| 490 | }; | ||
diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi new file mode 100644 index 000000000000..c8e5ae06deaf --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | |||
| @@ -0,0 +1,553 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Gateworks Corporation | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | / { | ||
| 13 | /* these are used by bootloader for disabling nodes */ | ||
| 14 | aliases { | ||
| 15 | can0 = &can1; | ||
| 16 | ethernet0 = &fec; | ||
| 17 | ethernet1 = ð1; | ||
| 18 | led0 = &led0; | ||
| 19 | led1 = &led1; | ||
| 20 | led2 = &led2; | ||
| 21 | nand = &gpmi; | ||
| 22 | sky2 = ð1; | ||
| 23 | ssi0 = &ssi1; | ||
| 24 | usb0 = &usbh1; | ||
| 25 | usb1 = &usbotg; | ||
| 26 | usdhc2 = &usdhc3; | ||
| 27 | }; | ||
| 28 | |||
| 29 | chosen { | ||
| 30 | bootargs = "console=ttymxc1,115200"; | ||
| 31 | }; | ||
| 32 | |||
| 33 | leds { | ||
| 34 | compatible = "gpio-leds"; | ||
| 35 | |||
| 36 | led0: user1 { | ||
| 37 | label = "user1"; | ||
| 38 | gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ | ||
| 39 | default-state = "on"; | ||
| 40 | linux,default-trigger = "heartbeat"; | ||
| 41 | }; | ||
| 42 | |||
| 43 | led1: user2 { | ||
| 44 | label = "user2"; | ||
| 45 | gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ | ||
| 46 | default-state = "off"; | ||
| 47 | }; | ||
| 48 | |||
| 49 | led2: user3 { | ||
| 50 | label = "user3"; | ||
| 51 | gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */ | ||
| 52 | default-state = "off"; | ||
| 53 | }; | ||
| 54 | }; | ||
| 55 | |||
| 56 | memory { | ||
| 57 | reg = <0x10000000 0x40000000>; | ||
| 58 | }; | ||
| 59 | |||
| 60 | pps { | ||
| 61 | compatible = "pps-gpio"; | ||
| 62 | gpios = <&gpio1 26 0>; | ||
| 63 | status = "okay"; | ||
| 64 | }; | ||
| 65 | |||
| 66 | regulators { | ||
| 67 | compatible = "simple-bus"; | ||
| 68 | #address-cells = <1>; | ||
| 69 | #size-cells = <0>; | ||
| 70 | |||
| 71 | reg_1p0v: regulator@0 { | ||
| 72 | compatible = "regulator-fixed"; | ||
| 73 | reg = <0>; | ||
| 74 | regulator-name = "1P0V"; | ||
| 75 | regulator-min-microvolt = <1000000>; | ||
| 76 | regulator-max-microvolt = <1000000>; | ||
| 77 | regulator-always-on; | ||
| 78 | }; | ||
| 79 | |||
| 80 | /* remove when pmic 1p8 regulator available */ | ||
| 81 | reg_1p8v: regulator@1 { | ||
| 82 | compatible = "regulator-fixed"; | ||
| 83 | reg = <1>; | ||
| 84 | regulator-name = "1P8V"; | ||
| 85 | regulator-min-microvolt = <1800000>; | ||
| 86 | regulator-max-microvolt = <1800000>; | ||
| 87 | regulator-always-on; | ||
| 88 | }; | ||
| 89 | |||
| 90 | reg_3p3v: regulator@2 { | ||
| 91 | compatible = "regulator-fixed"; | ||
| 92 | reg = <2>; | ||
| 93 | regulator-name = "3P3V"; | ||
| 94 | regulator-min-microvolt = <3300000>; | ||
| 95 | regulator-max-microvolt = <3300000>; | ||
| 96 | regulator-always-on; | ||
| 97 | }; | ||
| 98 | |||
| 99 | reg_usb_h1_vbus: regulator@3 { | ||
| 100 | compatible = "regulator-fixed"; | ||
| 101 | reg = <3>; | ||
| 102 | regulator-name = "usb_h1_vbus"; | ||
| 103 | regulator-min-microvolt = <5000000>; | ||
| 104 | regulator-max-microvolt = <5000000>; | ||
| 105 | regulator-always-on; | ||
| 106 | }; | ||
| 107 | |||
| 108 | reg_usb_otg_vbus: regulator@4 { | ||
| 109 | compatible = "regulator-fixed"; | ||
| 110 | reg = <4>; | ||
| 111 | regulator-name = "usb_otg_vbus"; | ||
| 112 | regulator-min-microvolt = <5000000>; | ||
| 113 | regulator-max-microvolt = <5000000>; | ||
| 114 | gpio = <&gpio3 22 0>; | ||
| 115 | enable-active-high; | ||
| 116 | }; | ||
| 117 | }; | ||
| 118 | |||
| 119 | sound { | ||
| 120 | compatible = "fsl,imx6q-sabrelite-sgtl5000", | ||
| 121 | "fsl,imx-audio-sgtl5000"; | ||
| 122 | model = "imx6q-sabrelite-sgtl5000"; | ||
| 123 | ssi-controller = <&ssi1>; | ||
| 124 | audio-codec = <&codec>; | ||
| 125 | audio-routing = | ||
| 126 | "MIC_IN", "Mic Jack", | ||
| 127 | "Mic Jack", "Mic Bias", | ||
| 128 | "Headphone Jack", "HP_OUT"; | ||
| 129 | mux-int-port = <1>; | ||
| 130 | mux-ext-port = <4>; | ||
| 131 | }; | ||
| 132 | }; | ||
| 133 | |||
| 134 | &audmux { | ||
| 135 | pinctrl-names = "default"; | ||
| 136 | pinctrl-0 = <&pinctrl_audmux>; | ||
| 137 | status = "okay"; | ||
| 138 | }; | ||
| 139 | |||
| 140 | &can1 { | ||
| 141 | pinctrl-names = "default"; | ||
| 142 | pinctrl-0 = <&pinctrl_flexcan1>; | ||
| 143 | status = "okay"; | ||
| 144 | }; | ||
| 145 | |||
| 146 | &fec { | ||
| 147 | pinctrl-names = "default"; | ||
| 148 | pinctrl-0 = <&pinctrl_enet>; | ||
| 149 | phy-mode = "rgmii"; | ||
| 150 | phy-reset-gpios = <&gpio1 30 0>; | ||
| 151 | status = "okay"; | ||
| 152 | }; | ||
| 153 | |||
| 154 | &gpmi { | ||
| 155 | pinctrl-names = "default"; | ||
| 156 | pinctrl-0 = <&pinctrl_gpmi_nand>; | ||
| 157 | status = "okay"; | ||
| 158 | }; | ||
| 159 | |||
| 160 | &i2c1 { | ||
| 161 | clock-frequency = <100000>; | ||
| 162 | pinctrl-names = "default"; | ||
| 163 | pinctrl-0 = <&pinctrl_i2c1>; | ||
| 164 | status = "okay"; | ||
| 165 | |||
| 166 | eeprom1: eeprom@50 { | ||
| 167 | compatible = "atmel,24c02"; | ||
| 168 | reg = <0x50>; | ||
| 169 | pagesize = <16>; | ||
| 170 | }; | ||
| 171 | |||
| 172 | eeprom2: eeprom@51 { | ||
| 173 | compatible = "atmel,24c02"; | ||
| 174 | reg = <0x51>; | ||
| 175 | pagesize = <16>; | ||
| 176 | }; | ||
| 177 | |||
| 178 | eeprom3: eeprom@52 { | ||
| 179 | compatible = "atmel,24c02"; | ||
| 180 | reg = <0x52>; | ||
| 181 | pagesize = <16>; | ||
| 182 | }; | ||
| 183 | |||
| 184 | eeprom4: eeprom@53 { | ||
| 185 | compatible = "atmel,24c02"; | ||
| 186 | reg = <0x53>; | ||
| 187 | pagesize = <16>; | ||
| 188 | }; | ||
| 189 | |||
| 190 | gpio: pca9555@23 { | ||
| 191 | compatible = "nxp,pca9555"; | ||
| 192 | reg = <0x23>; | ||
| 193 | gpio-controller; | ||
| 194 | #gpio-cells = <2>; | ||
| 195 | }; | ||
| 196 | |||
| 197 | hwmon: gsc@29 { | ||
| 198 | compatible = "gw,gsp"; | ||
| 199 | reg = <0x29>; | ||
| 200 | }; | ||
| 201 | |||
| 202 | rtc: ds1672@68 { | ||
| 203 | compatible = "dallas,ds1672"; | ||
| 204 | reg = <0x68>; | ||
| 205 | }; | ||
| 206 | }; | ||
| 207 | |||
| 208 | &i2c2 { | ||
| 209 | clock-frequency = <100000>; | ||
| 210 | pinctrl-names = "default"; | ||
| 211 | pinctrl-0 = <&pinctrl_i2c2>; | ||
| 212 | status = "okay"; | ||
| 213 | |||
| 214 | pciclkgen: si53156@6b { | ||
| 215 | compatible = "sil,si53156"; | ||
| 216 | reg = <0x6b>; | ||
| 217 | }; | ||
| 218 | |||
| 219 | pciswitch: pex8606@3f { | ||
| 220 | compatible = "plx,pex8606"; | ||
| 221 | reg = <0x3f>; | ||
| 222 | }; | ||
| 223 | |||
| 224 | pmic: ltc3676@3c { | ||
| 225 | compatible = "ltc,ltc3676"; | ||
| 226 | reg = <0x3c>; | ||
| 227 | |||
| 228 | regulators { | ||
| 229 | /* VDD_SOC */ | ||
| 230 | sw1_reg: ltc3676__sw1 { | ||
| 231 | regulator-min-microvolt = <1175000>; | ||
| 232 | regulator-max-microvolt = <1175000>; | ||
| 233 | regulator-boot-on; | ||
| 234 | regulator-always-on; | ||
| 235 | }; | ||
| 236 | |||
| 237 | /* VDD_1P8 */ | ||
| 238 | sw2_reg: ltc3676__sw2 { | ||
| 239 | regulator-min-microvolt = <1800000>; | ||
| 240 | regulator-max-microvolt = <1800000>; | ||
| 241 | regulator-boot-on; | ||
| 242 | regulator-always-on; | ||
| 243 | }; | ||
| 244 | |||
| 245 | /* VDD_ARM */ | ||
| 246 | sw3_reg: ltc3676__sw3 { | ||
| 247 | regulator-min-microvolt = <1175000>; | ||
| 248 | regulator-max-microvolt = <1175000>; | ||
| 249 | regulator-boot-on; | ||
| 250 | regulator-always-on; | ||
| 251 | }; | ||
| 252 | |||
| 253 | /* VDD_DDR */ | ||
| 254 | sw4_reg: ltc3676__sw4 { | ||
| 255 | regulator-min-microvolt = <1500000>; | ||
| 256 | regulator-max-microvolt = <1500000>; | ||
| 257 | regulator-boot-on; | ||
| 258 | regulator-always-on; | ||
| 259 | }; | ||
| 260 | |||
| 261 | /* VDD_2P5 */ | ||
| 262 | ldo2_reg: ltc3676__ldo2 { | ||
| 263 | regulator-min-microvolt = <2500000>; | ||
| 264 | regulator-max-microvolt = <2500000>; | ||
| 265 | regulator-boot-on; | ||
| 266 | regulator-always-on; | ||
| 267 | }; | ||
| 268 | |||
| 269 | /* VDD_1P8 */ | ||
| 270 | ldo3_reg: ltc3676__ldo3 { | ||
| 271 | regulator-min-microvolt = <1800000>; | ||
| 272 | regulator-max-microvolt = <1800000>; | ||
| 273 | regulator-boot-on; | ||
| 274 | regulator-always-on; | ||
| 275 | }; | ||
| 276 | |||
| 277 | /* VDD_HIGH */ | ||
| 278 | ldo4_reg: ltc3676__ldo4 { | ||
| 279 | regulator-min-microvolt = <3000000>; | ||
| 280 | regulator-max-microvolt = <3000000>; | ||
| 281 | }; | ||
| 282 | }; | ||
| 283 | }; | ||
| 284 | }; | ||
| 285 | |||
| 286 | &i2c3 { | ||
| 287 | clock-frequency = <100000>; | ||
| 288 | pinctrl-names = "default"; | ||
| 289 | pinctrl-0 = <&pinctrl_i2c3>; | ||
| 290 | status = "okay"; | ||
| 291 | |||
| 292 | accelerometer: fxos8700@1e { | ||
| 293 | compatible = "fsl,fxos8700"; | ||
| 294 | reg = <0x1e>; | ||
| 295 | }; | ||
| 296 | |||
| 297 | codec: sgtl5000@0a { | ||
| 298 | compatible = "fsl,sgtl5000"; | ||
| 299 | reg = <0x0a>; | ||
| 300 | clocks = <&clks 201>; | ||
| 301 | VDDA-supply = <®_1p8v>; | ||
| 302 | VDDIO-supply = <®_3p3v>; | ||
| 303 | }; | ||
| 304 | |||
| 305 | hdmiin: adv7611@4c { | ||
| 306 | compatible = "adi,adv7611"; | ||
| 307 | reg = <0x4c>; | ||
| 308 | }; | ||
| 309 | |||
| 310 | touchscreen: egalax_ts@04 { | ||
| 311 | compatible = "eeti,egalax_ts"; | ||
| 312 | reg = <0x04>; | ||
| 313 | interrupt-parent = <&gpio1>; | ||
| 314 | interrupts = <11 2>; /* gpio1_11 active low */ | ||
| 315 | wakeup-gpios = <&gpio1 11 0>; | ||
| 316 | }; | ||
| 317 | |||
| 318 | videoout: adv7393@2a { | ||
| 319 | compatible = "adi,adv7393"; | ||
| 320 | reg = <0x2a>; | ||
| 321 | }; | ||
| 322 | |||
| 323 | videoin: adv7180@20 { | ||
| 324 | compatible = "adi,adv7180"; | ||
| 325 | reg = <0x20>; | ||
| 326 | }; | ||
| 327 | }; | ||
| 328 | |||
| 329 | &iomuxc { | ||
| 330 | pinctrl-names = "default"; | ||
| 331 | pinctrl-0 = <&pinctrl_hog>; | ||
| 332 | |||
| 333 | imx6qdl-gw53xx { | ||
| 334 | pinctrl_hog: hoggrp { | ||
| 335 | fsl,pins = < | ||
| 336 | MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* PCIE6EXP_DIO0 */ | ||
| 337 | MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* PCIE6EXP_DIO1 */ | ||
| 338 | MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ | ||
| 339 | MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 /* GPS_SHDN */ | ||
| 340 | MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ | ||
| 341 | MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */ | ||
| 342 | MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */ | ||
| 343 | MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ | ||
| 344 | MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAN_STBY */ | ||
| 345 | MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x80000000 /* PMIC_IRQ# */ | ||
| 346 | MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 /* HUB_RST# */ | ||
| 347 | MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* PCIE_WDIS# */ | ||
| 348 | MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* ACCEL_IRQ# */ | ||
| 349 | MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ | ||
| 350 | MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x80000000 /* USBOTG_OC# */ | ||
| 351 | MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ | ||
| 352 | MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ | ||
| 353 | MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x80000000 /* TOUCH_IRQ# */ | ||
| 354 | MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3_DET# */ | ||
| 355 | >; | ||
| 356 | }; | ||
| 357 | |||
| 358 | pinctrl_audmux: audmuxgrp { | ||
| 359 | fsl,pins = < | ||
| 360 | MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 | ||
| 361 | MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 | ||
| 362 | MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 | ||
| 363 | MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 | ||
| 364 | >; | ||
| 365 | }; | ||
| 366 | |||
| 367 | pinctrl_enet: enetgrp { | ||
| 368 | fsl,pins = < | ||
| 369 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 370 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 371 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 372 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 373 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 374 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 375 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 376 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 377 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 378 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 379 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 380 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 381 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 382 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | ||
| 383 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | ||
| 384 | MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 | ||
| 385 | >; | ||
| 386 | }; | ||
| 387 | |||
| 388 | pinctrl_flexcan1: flexcan1grp { | ||
| 389 | fsl,pins = < | ||
| 390 | MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 | ||
| 391 | MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 | ||
| 392 | >; | ||
| 393 | }; | ||
| 394 | |||
| 395 | pinctrl_gpmi_nand: gpminandgrp { | ||
| 396 | fsl,pins = < | ||
| 397 | MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 | ||
| 398 | MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 | ||
| 399 | MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 | ||
| 400 | MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 | ||
| 401 | MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 | ||
| 402 | MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 | ||
| 403 | MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 | ||
| 404 | MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 | ||
| 405 | MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 | ||
| 406 | MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 | ||
| 407 | MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 | ||
| 408 | MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 | ||
| 409 | MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 | ||
| 410 | MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 | ||
| 411 | MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 | ||
| 412 | MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 | ||
| 413 | >; | ||
| 414 | }; | ||
| 415 | |||
| 416 | pinctrl_i2c1: i2c1grp { | ||
| 417 | fsl,pins = < | ||
| 418 | MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 | ||
| 419 | MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 | ||
| 420 | >; | ||
| 421 | }; | ||
| 422 | |||
| 423 | pinctrl_i2c2: i2c2grp { | ||
| 424 | fsl,pins = < | ||
| 425 | MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 | ||
| 426 | MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 | ||
| 427 | >; | ||
| 428 | }; | ||
| 429 | |||
| 430 | pinctrl_i2c3: i2c3grp { | ||
| 431 | fsl,pins = < | ||
| 432 | MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 | ||
| 433 | MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 | ||
| 434 | >; | ||
| 435 | }; | ||
| 436 | |||
| 437 | pinctrl_uart1: uart1grp { | ||
| 438 | fsl,pins = < | ||
| 439 | MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 | ||
| 440 | MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 | ||
| 441 | >; | ||
| 442 | }; | ||
| 443 | |||
| 444 | pinctrl_uart2: uart2grp { | ||
| 445 | fsl,pins = < | ||
| 446 | MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 | ||
| 447 | MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 | ||
| 448 | >; | ||
| 449 | }; | ||
| 450 | |||
| 451 | pinctrl_uart5: uart5grp { | ||
| 452 | fsl,pins = < | ||
| 453 | MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 | ||
| 454 | MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 | ||
| 455 | >; | ||
| 456 | }; | ||
| 457 | |||
| 458 | pinctrl_usbotg: usbotggrp { | ||
| 459 | fsl,pins = < | ||
| 460 | MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 | ||
| 461 | >; | ||
| 462 | }; | ||
| 463 | |||
| 464 | pinctrl_usdhc3: usdhc3grp { | ||
| 465 | fsl,pins = < | ||
| 466 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 467 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 468 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 469 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 470 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 471 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 472 | >; | ||
| 473 | }; | ||
| 474 | }; | ||
| 475 | }; | ||
| 476 | |||
| 477 | &ldb { | ||
| 478 | status = "okay"; | ||
| 479 | |||
| 480 | lvds-channel@1 { | ||
| 481 | fsl,data-mapping = "spwg"; | ||
| 482 | fsl,data-width = <18>; | ||
| 483 | status = "okay"; | ||
| 484 | |||
| 485 | display-timings { | ||
| 486 | native-mode = <&timing0>; | ||
| 487 | timing0: hsd100pxn1 { | ||
| 488 | clock-frequency = <65000000>; | ||
| 489 | hactive = <1024>; | ||
| 490 | vactive = <768>; | ||
| 491 | hback-porch = <220>; | ||
| 492 | hfront-porch = <40>; | ||
| 493 | vback-porch = <21>; | ||
| 494 | vfront-porch = <7>; | ||
| 495 | hsync-len = <60>; | ||
| 496 | vsync-len = <10>; | ||
| 497 | }; | ||
| 498 | }; | ||
| 499 | }; | ||
| 500 | }; | ||
| 501 | |||
| 502 | &pcie { | ||
| 503 | reset-gpio = <&gpio1 29 0>; | ||
| 504 | status = "okay"; | ||
| 505 | |||
| 506 | eth1: sky2@8 { /* MAC/PHY on bus 8 */ | ||
| 507 | compatible = "marvell,sky2"; | ||
| 508 | }; | ||
| 509 | }; | ||
| 510 | |||
| 511 | &ssi1 { | ||
| 512 | fsl,mode = "i2s-slave"; | ||
| 513 | status = "okay"; | ||
| 514 | }; | ||
| 515 | |||
| 516 | &uart1 { | ||
| 517 | pinctrl-names = "default"; | ||
| 518 | pinctrl-0 = <&pinctrl_uart1>; | ||
| 519 | status = "okay"; | ||
| 520 | }; | ||
| 521 | |||
| 522 | &uart2 { | ||
| 523 | pinctrl-names = "default"; | ||
| 524 | pinctrl-0 = <&pinctrl_uart2>; | ||
| 525 | status = "okay"; | ||
| 526 | }; | ||
| 527 | |||
| 528 | &uart5 { | ||
| 529 | pinctrl-names = "default"; | ||
| 530 | pinctrl-0 = <&pinctrl_uart5>; | ||
| 531 | status = "okay"; | ||
| 532 | }; | ||
| 533 | |||
| 534 | &usbotg { | ||
| 535 | vbus-supply = <®_usb_otg_vbus>; | ||
| 536 | pinctrl-names = "default"; | ||
| 537 | pinctrl-0 = <&pinctrl_usbotg>; | ||
| 538 | disable-over-current; | ||
| 539 | status = "okay"; | ||
| 540 | }; | ||
| 541 | |||
| 542 | &usbh1 { | ||
| 543 | vbus-supply = <®_usb_h1_vbus>; | ||
| 544 | status = "okay"; | ||
| 545 | }; | ||
| 546 | |||
| 547 | &usdhc3 { | ||
| 548 | pinctrl-names = "default"; | ||
| 549 | pinctrl-0 = <&pinctrl_usdhc3>; | ||
| 550 | cd-gpios = <&gpio7 0 0>; | ||
| 551 | vmmc-supply = <®_3p3v>; | ||
| 552 | status = "okay"; | ||
| 553 | }; | ||
diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi new file mode 100644 index 000000000000..2795dfc8c926 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | |||
| @@ -0,0 +1,580 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Gateworks Corporation | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | / { | ||
| 13 | /* these are used by bootloader for disabling nodes */ | ||
| 14 | aliases { | ||
| 15 | can0 = &can1; | ||
| 16 | ethernet0 = &fec; | ||
| 17 | ethernet1 = ð1; | ||
| 18 | led0 = &led0; | ||
| 19 | led1 = &led1; | ||
| 20 | led2 = &led2; | ||
| 21 | nand = &gpmi; | ||
| 22 | sky2 = ð1; | ||
| 23 | ssi0 = &ssi1; | ||
| 24 | usb0 = &usbh1; | ||
| 25 | usb1 = &usbotg; | ||
| 26 | usdhc2 = &usdhc3; | ||
| 27 | }; | ||
| 28 | |||
| 29 | chosen { | ||
| 30 | bootargs = "console=ttymxc1,115200"; | ||
| 31 | }; | ||
| 32 | |||
| 33 | leds { | ||
| 34 | compatible = "gpio-leds"; | ||
| 35 | |||
| 36 | led0: user1 { | ||
| 37 | label = "user1"; | ||
| 38 | gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ | ||
| 39 | default-state = "on"; | ||
| 40 | linux,default-trigger = "heartbeat"; | ||
| 41 | }; | ||
| 42 | |||
| 43 | led1: user2 { | ||
| 44 | label = "user2"; | ||
| 45 | gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ | ||
| 46 | default-state = "off"; | ||
| 47 | }; | ||
| 48 | |||
| 49 | led2: user3 { | ||
| 50 | label = "user3"; | ||
| 51 | gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */ | ||
| 52 | default-state = "off"; | ||
| 53 | }; | ||
| 54 | }; | ||
| 55 | |||
| 56 | memory { | ||
| 57 | reg = <0x10000000 0x40000000>; | ||
| 58 | }; | ||
| 59 | |||
| 60 | pps { | ||
| 61 | compatible = "pps-gpio"; | ||
| 62 | gpios = <&gpio1 26 0>; | ||
| 63 | status = "okay"; | ||
| 64 | }; | ||
| 65 | |||
| 66 | regulators { | ||
| 67 | compatible = "simple-bus"; | ||
| 68 | #address-cells = <1>; | ||
| 69 | #size-cells = <0>; | ||
| 70 | |||
| 71 | reg_1p0v: regulator@0 { | ||
| 72 | compatible = "regulator-fixed"; | ||
| 73 | reg = <0>; | ||
| 74 | regulator-name = "1P0V"; | ||
| 75 | regulator-min-microvolt = <1000000>; | ||
| 76 | regulator-max-microvolt = <1000000>; | ||
| 77 | regulator-always-on; | ||
| 78 | }; | ||
| 79 | |||
| 80 | reg_3p3v: regulator@1 { | ||
| 81 | compatible = "regulator-fixed"; | ||
| 82 | reg = <1>; | ||
| 83 | regulator-name = "3P3V"; | ||
| 84 | regulator-min-microvolt = <3300000>; | ||
| 85 | regulator-max-microvolt = <3300000>; | ||
| 86 | regulator-always-on; | ||
| 87 | }; | ||
| 88 | |||
| 89 | reg_usb_h1_vbus: regulator@2 { | ||
| 90 | compatible = "regulator-fixed"; | ||
| 91 | reg = <2>; | ||
| 92 | regulator-name = "usb_h1_vbus"; | ||
| 93 | regulator-min-microvolt = <5000000>; | ||
| 94 | regulator-max-microvolt = <5000000>; | ||
| 95 | regulator-always-on; | ||
| 96 | }; | ||
| 97 | |||
| 98 | reg_usb_otg_vbus: regulator@3 { | ||
| 99 | compatible = "regulator-fixed"; | ||
| 100 | reg = <3>; | ||
| 101 | regulator-name = "usb_otg_vbus"; | ||
| 102 | regulator-min-microvolt = <5000000>; | ||
| 103 | regulator-max-microvolt = <5000000>; | ||
| 104 | gpio = <&gpio3 22 0>; | ||
| 105 | enable-active-high; | ||
| 106 | }; | ||
| 107 | }; | ||
| 108 | |||
| 109 | sound { | ||
| 110 | compatible = "fsl,imx6q-sabrelite-sgtl5000", | ||
| 111 | "fsl,imx-audio-sgtl5000"; | ||
| 112 | model = "imx6q-sabrelite-sgtl5000"; | ||
| 113 | ssi-controller = <&ssi1>; | ||
| 114 | audio-codec = <&codec>; | ||
| 115 | audio-routing = | ||
| 116 | "MIC_IN", "Mic Jack", | ||
| 117 | "Mic Jack", "Mic Bias", | ||
| 118 | "Headphone Jack", "HP_OUT"; | ||
| 119 | mux-int-port = <1>; | ||
| 120 | mux-ext-port = <4>; | ||
| 121 | }; | ||
| 122 | }; | ||
| 123 | |||
| 124 | &audmux { | ||
| 125 | pinctrl-names = "default"; | ||
| 126 | pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */ | ||
| 127 | status = "okay"; | ||
| 128 | }; | ||
| 129 | |||
| 130 | &can1 { | ||
| 131 | pinctrl-names = "default"; | ||
| 132 | pinctrl-0 = <&pinctrl_flexcan1>; | ||
| 133 | status = "okay"; | ||
| 134 | }; | ||
| 135 | |||
| 136 | &fec { | ||
| 137 | pinctrl-names = "default"; | ||
| 138 | pinctrl-0 = <&pinctrl_enet>; | ||
| 139 | phy-mode = "rgmii"; | ||
| 140 | phy-reset-gpios = <&gpio1 30 0>; | ||
| 141 | status = "okay"; | ||
| 142 | }; | ||
| 143 | |||
| 144 | &gpmi { | ||
| 145 | pinctrl-names = "default"; | ||
| 146 | pinctrl-0 = <&pinctrl_gpmi_nand>; | ||
| 147 | status = "okay"; | ||
| 148 | }; | ||
| 149 | |||
| 150 | &i2c1 { | ||
| 151 | clock-frequency = <100000>; | ||
| 152 | pinctrl-names = "default"; | ||
| 153 | pinctrl-0 = <&pinctrl_i2c1>; | ||
| 154 | status = "okay"; | ||
| 155 | |||
| 156 | eeprom1: eeprom@50 { | ||
| 157 | compatible = "atmel,24c02"; | ||
| 158 | reg = <0x50>; | ||
| 159 | pagesize = <16>; | ||
| 160 | }; | ||
| 161 | |||
| 162 | eeprom2: eeprom@51 { | ||
| 163 | compatible = "atmel,24c02"; | ||
| 164 | reg = <0x51>; | ||
| 165 | pagesize = <16>; | ||
| 166 | }; | ||
| 167 | |||
| 168 | eeprom3: eeprom@52 { | ||
| 169 | compatible = "atmel,24c02"; | ||
| 170 | reg = <0x52>; | ||
| 171 | pagesize = <16>; | ||
| 172 | }; | ||
| 173 | |||
| 174 | eeprom4: eeprom@53 { | ||
| 175 | compatible = "atmel,24c02"; | ||
| 176 | reg = <0x53>; | ||
| 177 | pagesize = <16>; | ||
| 178 | }; | ||
| 179 | |||
| 180 | gpio: pca9555@23 { | ||
| 181 | compatible = "nxp,pca9555"; | ||
| 182 | reg = <0x23>; | ||
| 183 | gpio-controller; | ||
| 184 | #gpio-cells = <2>; | ||
| 185 | }; | ||
| 186 | |||
| 187 | hwmon: gsc@29 { | ||
| 188 | compatible = "gw,gsp"; | ||
| 189 | reg = <0x29>; | ||
| 190 | }; | ||
| 191 | |||
| 192 | rtc: ds1672@68 { | ||
| 193 | compatible = "dallas,ds1672"; | ||
| 194 | reg = <0x68>; | ||
| 195 | }; | ||
| 196 | }; | ||
| 197 | |||
| 198 | &i2c2 { | ||
| 199 | clock-frequency = <100000>; | ||
| 200 | pinctrl-names = "default"; | ||
| 201 | pinctrl-0 = <&pinctrl_i2c2>; | ||
| 202 | status = "okay"; | ||
| 203 | |||
| 204 | pmic: pfuze100@08 { | ||
| 205 | compatible = "fsl,pfuze100"; | ||
| 206 | reg = <0x08>; | ||
| 207 | |||
| 208 | regulators { | ||
| 209 | sw1a_reg: sw1ab { | ||
| 210 | regulator-min-microvolt = <300000>; | ||
| 211 | regulator-max-microvolt = <1875000>; | ||
| 212 | regulator-boot-on; | ||
| 213 | regulator-always-on; | ||
| 214 | regulator-ramp-delay = <6250>; | ||
| 215 | }; | ||
| 216 | |||
| 217 | sw1c_reg: sw1c { | ||
| 218 | regulator-min-microvolt = <300000>; | ||
| 219 | regulator-max-microvolt = <1875000>; | ||
| 220 | regulator-boot-on; | ||
| 221 | regulator-always-on; | ||
| 222 | regulator-ramp-delay = <6250>; | ||
| 223 | }; | ||
| 224 | |||
| 225 | sw2_reg: sw2 { | ||
| 226 | regulator-min-microvolt = <800000>; | ||
| 227 | regulator-max-microvolt = <3950000>; | ||
| 228 | regulator-boot-on; | ||
| 229 | regulator-always-on; | ||
| 230 | }; | ||
| 231 | |||
| 232 | sw3a_reg: sw3a { | ||
| 233 | regulator-min-microvolt = <400000>; | ||
| 234 | regulator-max-microvolt = <1975000>; | ||
| 235 | regulator-boot-on; | ||
| 236 | regulator-always-on; | ||
| 237 | }; | ||
| 238 | |||
| 239 | sw3b_reg: sw3b { | ||
| 240 | regulator-min-microvolt = <400000>; | ||
| 241 | regulator-max-microvolt = <1975000>; | ||
| 242 | regulator-boot-on; | ||
| 243 | regulator-always-on; | ||
| 244 | }; | ||
| 245 | |||
| 246 | sw4_reg: sw4 { | ||
| 247 | regulator-min-microvolt = <800000>; | ||
| 248 | regulator-max-microvolt = <3300000>; | ||
| 249 | }; | ||
| 250 | |||
| 251 | swbst_reg: swbst { | ||
| 252 | regulator-min-microvolt = <5000000>; | ||
| 253 | regulator-max-microvolt = <5150000>; | ||
| 254 | }; | ||
| 255 | |||
| 256 | snvs_reg: vsnvs { | ||
| 257 | regulator-min-microvolt = <1000000>; | ||
| 258 | regulator-max-microvolt = <3000000>; | ||
| 259 | regulator-boot-on; | ||
| 260 | regulator-always-on; | ||
| 261 | }; | ||
| 262 | |||
| 263 | vref_reg: vrefddr { | ||
| 264 | regulator-boot-on; | ||
| 265 | regulator-always-on; | ||
| 266 | }; | ||
| 267 | |||
| 268 | vgen1_reg: vgen1 { | ||
| 269 | regulator-min-microvolt = <800000>; | ||
| 270 | regulator-max-microvolt = <1550000>; | ||
| 271 | }; | ||
| 272 | |||
| 273 | vgen2_reg: vgen2 { | ||
| 274 | regulator-min-microvolt = <800000>; | ||
| 275 | regulator-max-microvolt = <1550000>; | ||
| 276 | }; | ||
| 277 | |||
| 278 | vgen3_reg: vgen3 { | ||
| 279 | regulator-min-microvolt = <1800000>; | ||
| 280 | regulator-max-microvolt = <3300000>; | ||
| 281 | }; | ||
| 282 | |||
| 283 | vgen4_reg: vgen4 { | ||
| 284 | regulator-min-microvolt = <1800000>; | ||
| 285 | regulator-max-microvolt = <3300000>; | ||
| 286 | regulator-always-on; | ||
| 287 | }; | ||
| 288 | |||
| 289 | vgen5_reg: vgen5 { | ||
| 290 | regulator-min-microvolt = <1800000>; | ||
| 291 | regulator-max-microvolt = <3300000>; | ||
| 292 | regulator-always-on; | ||
| 293 | }; | ||
| 294 | |||
| 295 | vgen6_reg: vgen6 { | ||
| 296 | regulator-min-microvolt = <1800000>; | ||
| 297 | regulator-max-microvolt = <3300000>; | ||
| 298 | regulator-always-on; | ||
| 299 | }; | ||
| 300 | }; | ||
| 301 | }; | ||
| 302 | |||
| 303 | pciswitch: pex8609@3f { | ||
| 304 | compatible = "plx,pex8609"; | ||
| 305 | reg = <0x3f>; | ||
| 306 | }; | ||
| 307 | |||
| 308 | pciclkgen: si52147@6b { | ||
| 309 | compatible = "sil,si52147"; | ||
| 310 | reg = <0x6b>; | ||
| 311 | }; | ||
| 312 | }; | ||
| 313 | |||
| 314 | &i2c3 { | ||
| 315 | clock-frequency = <100000>; | ||
| 316 | pinctrl-names = "default"; | ||
| 317 | pinctrl-0 = <&pinctrl_i2c3>; | ||
| 318 | status = "okay"; | ||
| 319 | |||
| 320 | accelerometer: fxos8700@1e { | ||
| 321 | compatible = "fsl,fxos8700"; | ||
| 322 | reg = <0x1e>; | ||
| 323 | }; | ||
| 324 | |||
| 325 | codec: sgtl5000@0a { | ||
| 326 | compatible = "fsl,sgtl5000"; | ||
| 327 | reg = <0x0a>; | ||
| 328 | clocks = <&clks 201>; | ||
| 329 | VDDA-supply = <&sw4_reg>; | ||
| 330 | VDDIO-supply = <®_3p3v>; | ||
| 331 | }; | ||
| 332 | |||
| 333 | hdmiin: adv7611@4c { | ||
| 334 | compatible = "adi,adv7611"; | ||
| 335 | reg = <0x4c>; | ||
| 336 | }; | ||
| 337 | |||
| 338 | touchscreen: egalax_ts@04 { | ||
| 339 | compatible = "eeti,egalax_ts"; | ||
| 340 | reg = <0x04>; | ||
| 341 | interrupt-parent = <&gpio7>; | ||
| 342 | interrupts = <12 2>; /* gpio7_12 active low */ | ||
| 343 | wakeup-gpios = <&gpio7 12 0>; | ||
| 344 | }; | ||
| 345 | |||
| 346 | videoout: adv7393@2a { | ||
| 347 | compatible = "adi,adv7393"; | ||
| 348 | reg = <0x2a>; | ||
| 349 | }; | ||
| 350 | |||
| 351 | videoin: adv7180@20 { | ||
| 352 | compatible = "adi,adv7180"; | ||
| 353 | reg = <0x20>; | ||
| 354 | }; | ||
| 355 | }; | ||
| 356 | |||
| 357 | &iomuxc { | ||
| 358 | pinctrl-names = "default"; | ||
| 359 | pinctrl-0 = <&pinctrl_hog>; | ||
| 360 | |||
| 361 | imx6qdl-gw54xx { | ||
| 362 | pinctrl_hog: hoggrp { | ||
| 363 | fsl,pins = < | ||
| 364 | MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ | ||
| 365 | MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* SPINOR_CS0# */ | ||
| 366 | MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ | ||
| 367 | MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */ | ||
| 368 | MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */ | ||
| 369 | MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ | ||
| 370 | MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAN_STBY */ | ||
| 371 | MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */ | ||
| 372 | MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ | ||
| 373 | MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ | ||
| 374 | MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ | ||
| 375 | MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 /* USBHUB_RST# */ | ||
| 376 | MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x80000000 /* MIPI_DIO */ | ||
| 377 | >; | ||
| 378 | }; | ||
| 379 | |||
| 380 | pinctrl_audmux: audmuxgrp { | ||
| 381 | fsl,pins = < | ||
| 382 | MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 | ||
| 383 | MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 | ||
| 384 | MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 | ||
| 385 | MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 | ||
| 386 | >; | ||
| 387 | }; | ||
| 388 | |||
| 389 | pinctrl_enet: enetgrp { | ||
| 390 | fsl,pins = < | ||
| 391 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 392 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 393 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 394 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 395 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 396 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 397 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 398 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 399 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 400 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 401 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 402 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 403 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 404 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | ||
| 405 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | ||
| 406 | MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 | ||
| 407 | >; | ||
| 408 | }; | ||
| 409 | |||
| 410 | pinctrl_flexcan1: flexcan1grp { | ||
| 411 | fsl,pins = < | ||
| 412 | MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 | ||
| 413 | MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 | ||
| 414 | >; | ||
| 415 | }; | ||
| 416 | |||
| 417 | pinctrl_gpmi_nand: gpminandgrp { | ||
| 418 | fsl,pins = < | ||
| 419 | MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 | ||
| 420 | MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 | ||
| 421 | MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 | ||
| 422 | MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 | ||
| 423 | MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 | ||
| 424 | MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 | ||
| 425 | MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 | ||
| 426 | MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 | ||
| 427 | MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 | ||
| 428 | MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 | ||
| 429 | MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 | ||
| 430 | MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 | ||
| 431 | MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 | ||
| 432 | MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 | ||
| 433 | MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 | ||
| 434 | MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 | ||
| 435 | >; | ||
| 436 | }; | ||
| 437 | |||
| 438 | pinctrl_i2c1: i2c1grp { | ||
| 439 | fsl,pins = < | ||
| 440 | MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 | ||
| 441 | MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 | ||
| 442 | >; | ||
| 443 | }; | ||
| 444 | |||
| 445 | pinctrl_i2c2: i2c2grp { | ||
| 446 | fsl,pins = < | ||
| 447 | MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 | ||
| 448 | MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 | ||
| 449 | >; | ||
| 450 | }; | ||
| 451 | |||
| 452 | pinctrl_i2c3: i2c3grp { | ||
| 453 | fsl,pins = < | ||
| 454 | MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 | ||
| 455 | MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 | ||
| 456 | >; | ||
| 457 | }; | ||
| 458 | |||
| 459 | pinctrl_uart1: uart1grp { | ||
| 460 | fsl,pins = < | ||
| 461 | MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 | ||
| 462 | MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 | ||
| 463 | >; | ||
| 464 | }; | ||
| 465 | |||
| 466 | pinctrl_uart2: uart2grp { | ||
| 467 | fsl,pins = < | ||
| 468 | MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 | ||
| 469 | MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 | ||
| 470 | >; | ||
| 471 | }; | ||
| 472 | |||
| 473 | pinctrl_uart5: uart5grp { | ||
| 474 | fsl,pins = < | ||
| 475 | MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 | ||
| 476 | MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 | ||
| 477 | >; | ||
| 478 | }; | ||
| 479 | |||
| 480 | pinctrl_usbotg: usbotggrp { | ||
| 481 | fsl,pins = < | ||
| 482 | MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 | ||
| 483 | >; | ||
| 484 | }; | ||
| 485 | |||
| 486 | pinctrl_usdhc3: usdhc3grp { | ||
| 487 | fsl,pins = < | ||
| 488 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 489 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 490 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 491 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 492 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 493 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 494 | >; | ||
| 495 | }; | ||
| 496 | }; | ||
| 497 | }; | ||
| 498 | |||
| 499 | &ldb { | ||
| 500 | status = "okay"; | ||
| 501 | |||
| 502 | lvds-channel@1 { | ||
| 503 | fsl,data-mapping = "spwg"; | ||
| 504 | fsl,data-width = <18>; | ||
| 505 | status = "okay"; | ||
| 506 | |||
| 507 | display-timings { | ||
| 508 | native-mode = <&timing0>; | ||
| 509 | timing0: hsd100pxn1 { | ||
| 510 | clock-frequency = <65000000>; | ||
| 511 | hactive = <1024>; | ||
| 512 | vactive = <768>; | ||
| 513 | hback-porch = <220>; | ||
| 514 | hfront-porch = <40>; | ||
| 515 | vback-porch = <21>; | ||
| 516 | vfront-porch = <7>; | ||
| 517 | hsync-len = <60>; | ||
| 518 | vsync-len = <10>; | ||
| 519 | }; | ||
| 520 | }; | ||
| 521 | }; | ||
| 522 | }; | ||
| 523 | |||
| 524 | &pcie { | ||
| 525 | reset-gpio = <&gpio1 29 0>; | ||
| 526 | status = "okay"; | ||
| 527 | |||
| 528 | eth1: sky2@8 { /* MAC/PHY on bus 8 */ | ||
| 529 | compatible = "marvell,sky2"; | ||
| 530 | }; | ||
| 531 | }; | ||
| 532 | |||
| 533 | &ssi1 { | ||
| 534 | fsl,mode = "i2s-slave"; | ||
| 535 | status = "okay"; | ||
| 536 | }; | ||
| 537 | |||
| 538 | &ssi2 { | ||
| 539 | fsl,mode = "i2s-slave"; | ||
| 540 | status = "okay"; | ||
| 541 | }; | ||
| 542 | |||
| 543 | &uart1 { | ||
| 544 | pinctrl-names = "default"; | ||
| 545 | pinctrl-0 = <&pinctrl_uart1>; | ||
| 546 | status = "okay"; | ||
| 547 | }; | ||
| 548 | |||
| 549 | &uart2 { | ||
| 550 | pinctrl-names = "default"; | ||
| 551 | pinctrl-0 = <&pinctrl_uart2>; | ||
| 552 | status = "okay"; | ||
| 553 | }; | ||
| 554 | |||
| 555 | &uart5 { | ||
| 556 | pinctrl-names = "default"; | ||
| 557 | pinctrl-0 = <&pinctrl_uart5>; | ||
| 558 | status = "okay"; | ||
| 559 | }; | ||
| 560 | |||
| 561 | &usbotg { | ||
| 562 | vbus-supply = <®_usb_otg_vbus>; | ||
| 563 | pinctrl-names = "default"; | ||
| 564 | pinctrl-0 = <&pinctrl_usbotg>; | ||
| 565 | disable-over-current; | ||
| 566 | status = "okay"; | ||
| 567 | }; | ||
| 568 | |||
| 569 | &usbh1 { | ||
| 570 | vbus-supply = <®_usb_h1_vbus>; | ||
| 571 | status = "okay"; | ||
| 572 | }; | ||
| 573 | |||
| 574 | &usdhc3 { | ||
| 575 | pinctrl-names = "default"; | ||
| 576 | pinctrl-0 = <&pinctrl_usdhc3>; | ||
| 577 | cd-gpios = <&gpio7 0 0>; | ||
| 578 | vmmc-supply = <®_3p3v>; | ||
| 579 | status = "okay"; | ||
| 580 | }; | ||
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi new file mode 100644 index 000000000000..99be301b5232 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | |||
| @@ -0,0 +1,422 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Boundary Devices, Inc. | ||
| 3 | * Copyright 2011 Freescale Semiconductor, Inc. | ||
| 4 | * Copyright 2011 Linaro Ltd. | ||
| 5 | * | ||
| 6 | * The code contained herein is licensed under the GNU General Public | ||
| 7 | * License. You may obtain a copy of the GNU General Public License | ||
| 8 | * Version 2 or later at the following locations: | ||
| 9 | * | ||
| 10 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 11 | * http://www.gnu.org/copyleft/gpl.html | ||
| 12 | */ | ||
| 13 | #include <dt-bindings/gpio/gpio.h> | ||
| 14 | #include <dt-bindings/input/input.h> | ||
| 15 | |||
| 16 | / { | ||
| 17 | memory { | ||
| 18 | reg = <0x10000000 0x40000000>; | ||
| 19 | }; | ||
| 20 | |||
| 21 | regulators { | ||
| 22 | compatible = "simple-bus"; | ||
| 23 | #address-cells = <1>; | ||
| 24 | #size-cells = <0>; | ||
| 25 | |||
| 26 | reg_2p5v: regulator@0 { | ||
| 27 | compatible = "regulator-fixed"; | ||
| 28 | reg = <0>; | ||
| 29 | regulator-name = "2P5V"; | ||
| 30 | regulator-min-microvolt = <2500000>; | ||
| 31 | regulator-max-microvolt = <2500000>; | ||
| 32 | regulator-always-on; | ||
| 33 | }; | ||
| 34 | |||
| 35 | reg_3p3v: regulator@1 { | ||
| 36 | compatible = "regulator-fixed"; | ||
| 37 | reg = <1>; | ||
| 38 | regulator-name = "3P3V"; | ||
| 39 | regulator-min-microvolt = <3300000>; | ||
| 40 | regulator-max-microvolt = <3300000>; | ||
| 41 | regulator-always-on; | ||
| 42 | }; | ||
| 43 | |||
| 44 | reg_usb_otg_vbus: regulator@2 { | ||
| 45 | compatible = "regulator-fixed"; | ||
| 46 | reg = <2>; | ||
| 47 | regulator-name = "usb_otg_vbus"; | ||
| 48 | regulator-min-microvolt = <5000000>; | ||
| 49 | regulator-max-microvolt = <5000000>; | ||
| 50 | gpio = <&gpio3 22 0>; | ||
| 51 | enable-active-high; | ||
| 52 | }; | ||
| 53 | }; | ||
| 54 | |||
| 55 | gpio-keys { | ||
| 56 | compatible = "gpio-keys"; | ||
| 57 | pinctrl-names = "default"; | ||
| 58 | pinctrl-0 = <&pinctrl_gpio_keys>; | ||
| 59 | |||
| 60 | power { | ||
| 61 | label = "Power Button"; | ||
| 62 | gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; | ||
| 63 | linux,code = <KEY_POWER>; | ||
| 64 | gpio-key,wakeup; | ||
| 65 | }; | ||
| 66 | |||
| 67 | menu { | ||
| 68 | label = "Menu"; | ||
| 69 | gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; | ||
| 70 | linux,code = <KEY_MENU>; | ||
| 71 | }; | ||
| 72 | |||
| 73 | home { | ||
| 74 | label = "Home"; | ||
| 75 | gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; | ||
| 76 | linux,code = <KEY_HOME>; | ||
| 77 | }; | ||
| 78 | |||
| 79 | back { | ||
| 80 | label = "Back"; | ||
| 81 | gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; | ||
| 82 | linux,code = <KEY_BACK>; | ||
| 83 | }; | ||
| 84 | |||
| 85 | volume-up { | ||
| 86 | label = "Volume Up"; | ||
| 87 | gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; | ||
| 88 | linux,code = <KEY_VOLUMEUP>; | ||
| 89 | }; | ||
| 90 | |||
| 91 | volume-down { | ||
| 92 | label = "Volume Down"; | ||
| 93 | gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; | ||
| 94 | linux,code = <KEY_VOLUMEDOWN>; | ||
| 95 | }; | ||
| 96 | }; | ||
| 97 | |||
| 98 | sound { | ||
| 99 | compatible = "fsl,imx6q-nitrogen6x-sgtl5000", | ||
| 100 | "fsl,imx-audio-sgtl5000"; | ||
| 101 | model = "imx6q-nitrogen6x-sgtl5000"; | ||
| 102 | ssi-controller = <&ssi1>; | ||
| 103 | audio-codec = <&codec>; | ||
| 104 | audio-routing = | ||
| 105 | "MIC_IN", "Mic Jack", | ||
| 106 | "Mic Jack", "Mic Bias", | ||
| 107 | "Headphone Jack", "HP_OUT"; | ||
| 108 | mux-int-port = <1>; | ||
| 109 | mux-ext-port = <3>; | ||
| 110 | }; | ||
| 111 | |||
| 112 | backlight_lcd { | ||
| 113 | compatible = "pwm-backlight"; | ||
| 114 | pwms = <&pwm1 0 5000000>; | ||
| 115 | brightness-levels = <0 4 8 16 32 64 128 255>; | ||
| 116 | default-brightness-level = <7>; | ||
| 117 | power-supply = <®_3p3v>; | ||
| 118 | status = "okay"; | ||
| 119 | }; | ||
| 120 | |||
| 121 | backlight_lvds { | ||
| 122 | compatible = "pwm-backlight"; | ||
| 123 | pwms = <&pwm4 0 5000000>; | ||
| 124 | brightness-levels = <0 4 8 16 32 64 128 255>; | ||
| 125 | default-brightness-level = <7>; | ||
| 126 | power-supply = <®_3p3v>; | ||
| 127 | status = "okay"; | ||
| 128 | }; | ||
| 129 | }; | ||
| 130 | |||
| 131 | &audmux { | ||
| 132 | pinctrl-names = "default"; | ||
| 133 | pinctrl-0 = <&pinctrl_audmux>; | ||
| 134 | status = "okay"; | ||
| 135 | }; | ||
| 136 | |||
| 137 | &ecspi1 { | ||
| 138 | fsl,spi-num-chipselects = <1>; | ||
| 139 | cs-gpios = <&gpio3 19 0>; | ||
| 140 | pinctrl-names = "default"; | ||
| 141 | pinctrl-0 = <&pinctrl_ecspi1>; | ||
| 142 | status = "okay"; | ||
| 143 | |||
| 144 | flash: m25p80@0 { | ||
| 145 | compatible = "sst,sst25vf016b"; | ||
| 146 | spi-max-frequency = <20000000>; | ||
| 147 | reg = <0>; | ||
| 148 | }; | ||
| 149 | }; | ||
| 150 | |||
| 151 | &fec { | ||
| 152 | pinctrl-names = "default"; | ||
| 153 | pinctrl-0 = <&pinctrl_enet>; | ||
| 154 | phy-mode = "rgmii"; | ||
| 155 | phy-reset-gpios = <&gpio1 27 0>; | ||
| 156 | txen-skew-ps = <0>; | ||
| 157 | txc-skew-ps = <3000>; | ||
| 158 | rxdv-skew-ps = <0>; | ||
| 159 | rxc-skew-ps = <3000>; | ||
| 160 | rxd0-skew-ps = <0>; | ||
| 161 | rxd1-skew-ps = <0>; | ||
| 162 | rxd2-skew-ps = <0>; | ||
| 163 | rxd3-skew-ps = <0>; | ||
| 164 | txd0-skew-ps = <0>; | ||
| 165 | txd1-skew-ps = <0>; | ||
| 166 | txd2-skew-ps = <0>; | ||
| 167 | txd3-skew-ps = <0>; | ||
| 168 | interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, | ||
| 169 | <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; | ||
| 170 | status = "okay"; | ||
| 171 | }; | ||
| 172 | |||
| 173 | &i2c1 { | ||
| 174 | clock-frequency = <100000>; | ||
| 175 | pinctrl-names = "default"; | ||
| 176 | pinctrl-0 = <&pinctrl_i2c1>; | ||
| 177 | status = "okay"; | ||
| 178 | |||
| 179 | codec: sgtl5000@0a { | ||
| 180 | compatible = "fsl,sgtl5000"; | ||
| 181 | reg = <0x0a>; | ||
| 182 | clocks = <&clks 201>; | ||
| 183 | VDDA-supply = <®_2p5v>; | ||
| 184 | VDDIO-supply = <®_3p3v>; | ||
| 185 | }; | ||
| 186 | }; | ||
| 187 | |||
| 188 | &iomuxc { | ||
| 189 | pinctrl-names = "default"; | ||
| 190 | pinctrl-0 = <&pinctrl_hog>; | ||
| 191 | |||
| 192 | imx6q-nitrogen6x { | ||
| 193 | pinctrl_hog: hoggrp { | ||
| 194 | fsl,pins = < | ||
| 195 | /* SGTL5000 sys_mclk */ | ||
| 196 | MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 | ||
| 197 | >; | ||
| 198 | }; | ||
| 199 | |||
| 200 | pinctrl_audmux: audmuxgrp { | ||
| 201 | fsl,pins = < | ||
| 202 | MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 | ||
| 203 | MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 | ||
| 204 | MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 | ||
| 205 | MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 | ||
| 206 | >; | ||
| 207 | }; | ||
| 208 | |||
| 209 | pinctrl_ecspi1: ecspi1grp { | ||
| 210 | fsl,pins = < | ||
| 211 | MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 | ||
| 212 | MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 | ||
| 213 | MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 | ||
| 214 | MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */ | ||
| 215 | >; | ||
| 216 | }; | ||
| 217 | |||
| 218 | pinctrl_enet: enetgrp { | ||
| 219 | fsl,pins = < | ||
| 220 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 | ||
| 221 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 | ||
| 222 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 | ||
| 223 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 | ||
| 224 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 | ||
| 225 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 | ||
| 226 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 | ||
| 227 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 | ||
| 228 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 | ||
| 229 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 230 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 231 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 232 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 233 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 234 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 235 | /* Phy reset */ | ||
| 236 | MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x000b0 | ||
| 237 | MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 | ||
| 238 | >; | ||
| 239 | }; | ||
| 240 | |||
| 241 | pinctrl_gpio_keys: gpio_keysgrp { | ||
| 242 | fsl,pins = < | ||
| 243 | /* Power Button */ | ||
| 244 | MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 | ||
| 245 | /* Menu Button */ | ||
| 246 | MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 | ||
| 247 | /* Home Button */ | ||
| 248 | MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 | ||
| 249 | /* Back Button */ | ||
| 250 | MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 | ||
| 251 | /* Volume Up Button */ | ||
| 252 | MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 | ||
| 253 | /* Volume Down Button */ | ||
| 254 | MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 | ||
| 255 | >; | ||
| 256 | }; | ||
| 257 | |||
| 258 | pinctrl_i2c1: i2c1grp { | ||
| 259 | fsl,pins = < | ||
| 260 | MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 | ||
| 261 | MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 | ||
| 262 | >; | ||
| 263 | }; | ||
| 264 | |||
| 265 | pinctrl_pwm1: pwm1grp { | ||
| 266 | fsl,pins = < | ||
| 267 | MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 | ||
| 268 | >; | ||
| 269 | }; | ||
| 270 | |||
| 271 | pinctrl_pwm3: pwm3grp { | ||
| 272 | fsl,pins = < | ||
| 273 | MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 | ||
| 274 | >; | ||
| 275 | }; | ||
| 276 | |||
| 277 | pinctrl_pwm4: pwm4grp { | ||
| 278 | fsl,pins = < | ||
| 279 | MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 | ||
| 280 | >; | ||
| 281 | }; | ||
| 282 | |||
| 283 | pinctrl_uart1: uart1grp { | ||
| 284 | fsl,pins = < | ||
| 285 | MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 | ||
| 286 | MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 | ||
| 287 | >; | ||
| 288 | }; | ||
| 289 | |||
| 290 | pinctrl_uart2: uart2grp { | ||
| 291 | fsl,pins = < | ||
| 292 | MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 | ||
| 293 | MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 | ||
| 294 | >; | ||
| 295 | }; | ||
| 296 | |||
| 297 | pinctrl_usbotg: usbotggrp { | ||
| 298 | fsl,pins = < | ||
| 299 | MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 | ||
| 300 | MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 | ||
| 301 | /* power enable, high active */ | ||
| 302 | MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 | ||
| 303 | >; | ||
| 304 | }; | ||
| 305 | |||
| 306 | pinctrl_usdhc3: usdhc3grp { | ||
| 307 | fsl,pins = < | ||
| 308 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 309 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 310 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 311 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 312 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 313 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 314 | MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ | ||
| 315 | >; | ||
| 316 | }; | ||
| 317 | |||
| 318 | pinctrl_usdhc4: usdhc4grp { | ||
| 319 | fsl,pins = < | ||
| 320 | MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 | ||
| 321 | MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 | ||
| 322 | MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 | ||
| 323 | MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 | ||
| 324 | MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 | ||
| 325 | MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 | ||
| 326 | MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */ | ||
| 327 | >; | ||
| 328 | }; | ||
| 329 | }; | ||
| 330 | }; | ||
| 331 | |||
| 332 | &ldb { | ||
| 333 | status = "okay"; | ||
| 334 | |||
| 335 | lvds-channel@0 { | ||
| 336 | fsl,data-mapping = "spwg"; | ||
| 337 | fsl,data-width = <18>; | ||
| 338 | status = "okay"; | ||
| 339 | |||
| 340 | display-timings { | ||
| 341 | native-mode = <&timing0>; | ||
| 342 | timing0: hsd100pxn1 { | ||
| 343 | clock-frequency = <65000000>; | ||
| 344 | hactive = <1024>; | ||
| 345 | vactive = <768>; | ||
| 346 | hback-porch = <220>; | ||
| 347 | hfront-porch = <40>; | ||
| 348 | vback-porch = <21>; | ||
| 349 | vfront-porch = <7>; | ||
| 350 | hsync-len = <60>; | ||
| 351 | vsync-len = <10>; | ||
| 352 | }; | ||
| 353 | }; | ||
| 354 | }; | ||
| 355 | }; | ||
| 356 | |||
| 357 | &pcie { | ||
| 358 | status = "okay"; | ||
| 359 | }; | ||
| 360 | |||
| 361 | &pwm1 { | ||
| 362 | pinctrl-names = "default"; | ||
| 363 | pinctrl-0 = <&pinctrl_pwm1>; | ||
| 364 | status = "okay"; | ||
| 365 | }; | ||
| 366 | |||
| 367 | &pwm3 { | ||
| 368 | pinctrl-names = "default"; | ||
| 369 | pinctrl-0 = <&pinctrl_pwm3>; | ||
| 370 | status = "okay"; | ||
| 371 | }; | ||
| 372 | |||
| 373 | &pwm4 { | ||
| 374 | pinctrl-names = "default"; | ||
| 375 | pinctrl-0 = <&pinctrl_pwm4>; | ||
| 376 | status = "okay"; | ||
| 377 | }; | ||
| 378 | |||
| 379 | &ssi1 { | ||
| 380 | fsl,mode = "i2s-slave"; | ||
| 381 | status = "okay"; | ||
| 382 | }; | ||
| 383 | |||
| 384 | &uart1 { | ||
| 385 | pinctrl-names = "default"; | ||
| 386 | pinctrl-0 = <&pinctrl_uart1>; | ||
| 387 | status = "okay"; | ||
| 388 | }; | ||
| 389 | |||
| 390 | &uart2 { | ||
| 391 | pinctrl-names = "default"; | ||
| 392 | pinctrl-0 = <&pinctrl_uart2>; | ||
| 393 | status = "okay"; | ||
| 394 | }; | ||
| 395 | |||
| 396 | &usbh1 { | ||
| 397 | status = "okay"; | ||
| 398 | }; | ||
| 399 | |||
| 400 | &usbotg { | ||
| 401 | vbus-supply = <®_usb_otg_vbus>; | ||
| 402 | pinctrl-names = "default"; | ||
| 403 | pinctrl-0 = <&pinctrl_usbotg>; | ||
| 404 | disable-over-current; | ||
| 405 | status = "okay"; | ||
| 406 | }; | ||
| 407 | |||
| 408 | &usdhc3 { | ||
| 409 | pinctrl-names = "default"; | ||
| 410 | pinctrl-0 = <&pinctrl_usdhc3>; | ||
| 411 | cd-gpios = <&gpio7 0 0>; | ||
| 412 | vmmc-supply = <®_3p3v>; | ||
| 413 | status = "okay"; | ||
| 414 | }; | ||
| 415 | |||
| 416 | &usdhc4 { | ||
| 417 | pinctrl-names = "default"; | ||
| 418 | pinctrl-0 = <&pinctrl_usdhc4>; | ||
| 419 | cd-gpios = <&gpio2 6 0>; | ||
| 420 | vmmc-supply = <®_3p3v>; | ||
| 421 | status = "okay"; | ||
| 422 | }; | ||
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index ff6f1e8f2dd9..009abd69385d 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | |||
| @@ -10,17 +10,46 @@ | |||
| 10 | * http://www.gnu.org/copyleft/gpl.html | 10 | * http://www.gnu.org/copyleft/gpl.html |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | #include <dt-bindings/gpio/gpio.h> | ||
| 14 | |||
| 13 | / { | 15 | / { |
| 14 | memory { | 16 | memory { |
| 15 | reg = <0x10000000 0x80000000>; | 17 | reg = <0x10000000 0x80000000>; |
| 16 | }; | 18 | }; |
| 19 | |||
| 20 | leds { | ||
| 21 | compatible = "gpio-leds"; | ||
| 22 | pinctrl-names = "default"; | ||
| 23 | pinctrl-0 = <&pinctrl_gpio_leds>; | ||
| 24 | |||
| 25 | user { | ||
| 26 | label = "debug"; | ||
| 27 | gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; | ||
| 28 | }; | ||
| 29 | }; | ||
| 30 | |||
| 31 | sound-spdif { | ||
| 32 | compatible = "fsl,imx-audio-spdif", | ||
| 33 | "fsl,imx-sabreauto-spdif"; | ||
| 34 | model = "imx-spdif"; | ||
| 35 | spdif-controller = <&spdif>; | ||
| 36 | spdif-in; | ||
| 37 | }; | ||
| 38 | |||
| 39 | backlight { | ||
| 40 | compatible = "pwm-backlight"; | ||
| 41 | pwms = <&pwm3 0 5000000>; | ||
| 42 | brightness-levels = <0 4 8 16 32 64 128 255>; | ||
| 43 | default-brightness-level = <7>; | ||
| 44 | status = "okay"; | ||
| 45 | }; | ||
| 17 | }; | 46 | }; |
| 18 | 47 | ||
| 19 | &ecspi1 { | 48 | &ecspi1 { |
| 20 | fsl,spi-num-chipselects = <1>; | 49 | fsl,spi-num-chipselects = <1>; |
| 21 | cs-gpios = <&gpio3 19 0>; | 50 | cs-gpios = <&gpio3 19 0>; |
| 22 | pinctrl-names = "default"; | 51 | pinctrl-names = "default"; |
| 23 | pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_sabreauto>; | 52 | pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; |
| 24 | status = "disabled"; /* pin conflict with WEIM NOR */ | 53 | status = "disabled"; /* pin conflict with WEIM NOR */ |
| 25 | 54 | ||
| 26 | flash: m25p80@0 { | 55 | flash: m25p80@0 { |
| @@ -34,22 +63,130 @@ | |||
| 34 | 63 | ||
| 35 | &fec { | 64 | &fec { |
| 36 | pinctrl-names = "default"; | 65 | pinctrl-names = "default"; |
| 37 | pinctrl-0 = <&pinctrl_enet_2>; | 66 | pinctrl-0 = <&pinctrl_enet>; |
| 38 | phy-mode = "rgmii"; | 67 | phy-mode = "rgmii"; |
| 68 | interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, | ||
| 69 | <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; | ||
| 39 | status = "okay"; | 70 | status = "okay"; |
| 40 | }; | 71 | }; |
| 41 | 72 | ||
| 42 | &gpmi { | 73 | &gpmi { |
| 43 | pinctrl-names = "default"; | 74 | pinctrl-names = "default"; |
| 44 | pinctrl-0 = <&pinctrl_gpmi_nand_1>; | 75 | pinctrl-0 = <&pinctrl_gpmi_nand>; |
| 76 | status = "okay"; | ||
| 77 | }; | ||
| 78 | |||
| 79 | &i2c2 { | ||
| 80 | clock-frequency = <100000>; | ||
| 81 | pinctrl-names = "default"; | ||
| 82 | pinctrl-0 = <&pinctrl_i2c2>; | ||
| 45 | status = "okay"; | 83 | status = "okay"; |
| 84 | |||
| 85 | pmic: pfuze100@08 { | ||
| 86 | compatible = "fsl,pfuze100"; | ||
| 87 | reg = <0x08>; | ||
| 88 | |||
| 89 | regulators { | ||
| 90 | sw1a_reg: sw1ab { | ||
| 91 | regulator-min-microvolt = <300000>; | ||
| 92 | regulator-max-microvolt = <1875000>; | ||
| 93 | regulator-boot-on; | ||
| 94 | regulator-always-on; | ||
| 95 | regulator-ramp-delay = <6250>; | ||
| 96 | }; | ||
| 97 | |||
| 98 | sw1c_reg: sw1c { | ||
| 99 | regulator-min-microvolt = <300000>; | ||
| 100 | regulator-max-microvolt = <1875000>; | ||
| 101 | regulator-boot-on; | ||
| 102 | regulator-always-on; | ||
| 103 | regulator-ramp-delay = <6250>; | ||
| 104 | }; | ||
| 105 | |||
| 106 | sw2_reg: sw2 { | ||
| 107 | regulator-min-microvolt = <800000>; | ||
| 108 | regulator-max-microvolt = <3300000>; | ||
| 109 | regulator-boot-on; | ||
| 110 | regulator-always-on; | ||
| 111 | }; | ||
| 112 | |||
| 113 | sw3a_reg: sw3a { | ||
| 114 | regulator-min-microvolt = <400000>; | ||
| 115 | regulator-max-microvolt = <1975000>; | ||
| 116 | regulator-boot-on; | ||
| 117 | regulator-always-on; | ||
| 118 | }; | ||
| 119 | |||
| 120 | sw3b_reg: sw3b { | ||
| 121 | regulator-min-microvolt = <400000>; | ||
| 122 | regulator-max-microvolt = <1975000>; | ||
| 123 | regulator-boot-on; | ||
| 124 | regulator-always-on; | ||
| 125 | }; | ||
| 126 | |||
| 127 | sw4_reg: sw4 { | ||
| 128 | regulator-min-microvolt = <800000>; | ||
| 129 | regulator-max-microvolt = <3300000>; | ||
| 130 | }; | ||
| 131 | |||
| 132 | swbst_reg: swbst { | ||
| 133 | regulator-min-microvolt = <5000000>; | ||
| 134 | regulator-max-microvolt = <5150000>; | ||
| 135 | }; | ||
| 136 | |||
| 137 | snvs_reg: vsnvs { | ||
| 138 | regulator-min-microvolt = <1000000>; | ||
| 139 | regulator-max-microvolt = <3000000>; | ||
| 140 | regulator-boot-on; | ||
| 141 | regulator-always-on; | ||
| 142 | }; | ||
| 143 | |||
| 144 | vref_reg: vrefddr { | ||
| 145 | regulator-boot-on; | ||
| 146 | regulator-always-on; | ||
| 147 | }; | ||
| 148 | |||
| 149 | vgen1_reg: vgen1 { | ||
| 150 | regulator-min-microvolt = <800000>; | ||
| 151 | regulator-max-microvolt = <1550000>; | ||
| 152 | }; | ||
| 153 | |||
| 154 | vgen2_reg: vgen2 { | ||
| 155 | regulator-min-microvolt = <800000>; | ||
| 156 | regulator-max-microvolt = <1550000>; | ||
| 157 | }; | ||
| 158 | |||
| 159 | vgen3_reg: vgen3 { | ||
| 160 | regulator-min-microvolt = <1800000>; | ||
| 161 | regulator-max-microvolt = <3300000>; | ||
| 162 | }; | ||
| 163 | |||
| 164 | vgen4_reg: vgen4 { | ||
| 165 | regulator-min-microvolt = <1800000>; | ||
| 166 | regulator-max-microvolt = <3300000>; | ||
| 167 | regulator-always-on; | ||
| 168 | }; | ||
| 169 | |||
| 170 | vgen5_reg: vgen5 { | ||
| 171 | regulator-min-microvolt = <1800000>; | ||
| 172 | regulator-max-microvolt = <3300000>; | ||
| 173 | regulator-always-on; | ||
| 174 | }; | ||
| 175 | |||
| 176 | vgen6_reg: vgen6 { | ||
| 177 | regulator-min-microvolt = <1800000>; | ||
| 178 | regulator-max-microvolt = <3300000>; | ||
| 179 | regulator-always-on; | ||
| 180 | }; | ||
| 181 | }; | ||
| 182 | }; | ||
| 46 | }; | 183 | }; |
| 47 | 184 | ||
| 48 | &iomuxc { | 185 | &iomuxc { |
| 49 | pinctrl-names = "default"; | 186 | pinctrl-names = "default"; |
| 50 | pinctrl-0 = <&pinctrl_hog>; | 187 | pinctrl-0 = <&pinctrl_hog>; |
| 51 | 188 | ||
| 52 | hog { | 189 | imx6qdl-sabreauto { |
| 53 | pinctrl_hog: hoggrp { | 190 | pinctrl_hog: hoggrp { |
| 54 | fsl,pins = < | 191 | fsl,pins = < |
| 55 | MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 | 192 | MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 |
| @@ -57,28 +194,245 @@ | |||
| 57 | MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059 | 194 | MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059 |
| 58 | >; | 195 | >; |
| 59 | }; | 196 | }; |
| 60 | }; | ||
| 61 | 197 | ||
| 62 | ecspi1 { | 198 | pinctrl_ecspi1: ecspi1grp { |
| 63 | pinctrl_ecspi1_sabreauto: ecspi1-sabreauto { | 199 | fsl,pins = < |
| 200 | MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 | ||
| 201 | MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 | ||
| 202 | MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 | ||
| 203 | >; | ||
| 204 | }; | ||
| 205 | |||
| 206 | pinctrl_ecspi1_cs: ecspi1cs { | ||
| 64 | fsl,pins = < | 207 | fsl,pins = < |
| 65 | MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 | 208 | MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 |
| 66 | >; | 209 | >; |
| 67 | }; | 210 | }; |
| 211 | |||
| 212 | pinctrl_enet: enetgrp { | ||
| 213 | fsl,pins = < | ||
| 214 | MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 | ||
| 215 | MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 | ||
| 216 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 217 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 218 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 219 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 220 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 221 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 222 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 223 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 224 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 225 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 226 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 227 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 228 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 229 | MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 | ||
| 230 | >; | ||
| 231 | }; | ||
| 232 | |||
| 233 | pinctrl_gpio_leds: gpioledsgrp { | ||
| 234 | fsl,pins = < | ||
| 235 | MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000 | ||
| 236 | >; | ||
| 237 | }; | ||
| 238 | |||
| 239 | pinctrl_gpmi_nand: gpminandgrp { | ||
| 240 | fsl,pins = < | ||
| 241 | MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 | ||
| 242 | MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 | ||
| 243 | MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 | ||
| 244 | MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 | ||
| 245 | MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 | ||
| 246 | MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 | ||
| 247 | MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 | ||
| 248 | MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 | ||
| 249 | MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 | ||
| 250 | MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 | ||
| 251 | MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 | ||
| 252 | MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 | ||
| 253 | MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 | ||
| 254 | MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 | ||
| 255 | MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 | ||
| 256 | MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 | ||
| 257 | MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 | ||
| 258 | >; | ||
| 259 | }; | ||
| 260 | |||
| 261 | pinctrl_i2c2: i2c2grp { | ||
| 262 | fsl,pins = < | ||
| 263 | MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 | ||
| 264 | MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 | ||
| 265 | >; | ||
| 266 | }; | ||
| 267 | |||
| 268 | pinctrl_pwm3: pwm1grp { | ||
| 269 | fsl,pins = < | ||
| 270 | MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 | ||
| 271 | >; | ||
| 272 | }; | ||
| 273 | |||
| 274 | pinctrl_spdif: spdifgrp { | ||
| 275 | fsl,pins = < | ||
| 276 | MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0 | ||
| 277 | >; | ||
| 278 | }; | ||
| 279 | |||
| 280 | pinctrl_uart4: uart4grp { | ||
| 281 | fsl,pins = < | ||
| 282 | MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 | ||
| 283 | MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 | ||
| 284 | >; | ||
| 285 | }; | ||
| 286 | |||
| 287 | pinctrl_usdhc3: usdhc3grp { | ||
| 288 | fsl,pins = < | ||
| 289 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 290 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 291 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 292 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 293 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 294 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 295 | MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 | ||
| 296 | MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 | ||
| 297 | MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 | ||
| 298 | MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 | ||
| 299 | >; | ||
| 300 | }; | ||
| 301 | |||
| 302 | pinctrl_usdhc3_100mhz: usdhc3grp100mhz { | ||
| 303 | fsl,pins = < | ||
| 304 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 | ||
| 305 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 | ||
| 306 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 | ||
| 307 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 | ||
| 308 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 | ||
| 309 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 | ||
| 310 | MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 | ||
| 311 | MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 | ||
| 312 | MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 | ||
| 313 | MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 | ||
| 314 | >; | ||
| 315 | }; | ||
| 316 | |||
| 317 | pinctrl_usdhc3_200mhz: usdhc3grp200mhz { | ||
| 318 | fsl,pins = < | ||
| 319 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 | ||
| 320 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 | ||
| 321 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 | ||
| 322 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 | ||
| 323 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 | ||
| 324 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 | ||
| 325 | MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 | ||
| 326 | MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 | ||
| 327 | MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 | ||
| 328 | MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 | ||
| 329 | >; | ||
| 330 | }; | ||
| 331 | |||
| 332 | pinctrl_weim_cs0: weimcs0grp { | ||
| 333 | fsl,pins = < | ||
| 334 | MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 | ||
| 335 | >; | ||
| 336 | }; | ||
| 337 | |||
| 338 | pinctrl_weim_nor: weimnorgrp { | ||
| 339 | fsl,pins = < | ||
| 340 | MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 | ||
| 341 | MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 | ||
| 342 | MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 | ||
| 343 | MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 | ||
| 344 | MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 | ||
| 345 | MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 | ||
| 346 | MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 | ||
| 347 | MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 | ||
| 348 | MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 | ||
| 349 | MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 | ||
| 350 | MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 | ||
| 351 | MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 | ||
| 352 | MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 | ||
| 353 | MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 | ||
| 354 | MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 | ||
| 355 | MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 | ||
| 356 | MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 | ||
| 357 | MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 | ||
| 358 | MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 | ||
| 359 | MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 | ||
| 360 | MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 | ||
| 361 | MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 | ||
| 362 | MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 | ||
| 363 | MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 | ||
| 364 | MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 | ||
| 365 | MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 | ||
| 366 | MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 | ||
| 367 | MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 | ||
| 368 | MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 | ||
| 369 | MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 | ||
| 370 | MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 | ||
| 371 | MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 | ||
| 372 | MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 | ||
| 373 | MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 | ||
| 374 | MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 | ||
| 375 | MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 | ||
| 376 | MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 | ||
| 377 | MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 | ||
| 378 | MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 | ||
| 379 | MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 | ||
| 380 | MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 | ||
| 381 | MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 | ||
| 382 | MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 | ||
| 383 | >; | ||
| 384 | }; | ||
| 385 | }; | ||
| 386 | }; | ||
| 387 | |||
| 388 | &ldb { | ||
| 389 | status = "okay"; | ||
| 390 | |||
| 391 | lvds-channel@0 { | ||
| 392 | fsl,data-mapping = "spwg"; | ||
| 393 | fsl,data-width = <18>; | ||
| 394 | status = "okay"; | ||
| 395 | |||
| 396 | display-timings { | ||
| 397 | native-mode = <&timing0>; | ||
| 398 | timing0: hsd100pxn1 { | ||
| 399 | clock-frequency = <65000000>; | ||
| 400 | hactive = <1024>; | ||
| 401 | vactive = <768>; | ||
| 402 | hback-porch = <220>; | ||
| 403 | hfront-porch = <40>; | ||
| 404 | vback-porch = <21>; | ||
| 405 | vfront-porch = <7>; | ||
| 406 | hsync-len = <60>; | ||
| 407 | vsync-len = <10>; | ||
| 408 | }; | ||
| 409 | }; | ||
| 68 | }; | 410 | }; |
| 69 | }; | 411 | }; |
| 70 | 412 | ||
| 413 | &pwm3 { | ||
| 414 | pinctrl-names = "default"; | ||
| 415 | pinctrl-0 = <&pinctrl_pwm3>; | ||
| 416 | status = "okay"; | ||
| 417 | }; | ||
| 418 | |||
| 419 | &spdif { | ||
| 420 | pinctrl-names = "default"; | ||
| 421 | pinctrl-0 = <&pinctrl_spdif>; | ||
| 422 | status = "okay"; | ||
| 423 | }; | ||
| 424 | |||
| 71 | &uart4 { | 425 | &uart4 { |
| 72 | pinctrl-names = "default"; | 426 | pinctrl-names = "default"; |
| 73 | pinctrl-0 = <&pinctrl_uart4_1>; | 427 | pinctrl-0 = <&pinctrl_uart4>; |
| 74 | status = "okay"; | 428 | status = "okay"; |
| 75 | }; | 429 | }; |
| 76 | 430 | ||
| 77 | &usdhc3 { | 431 | &usdhc3 { |
| 78 | pinctrl-names = "default", "state_100mhz", "state_200mhz"; | 432 | pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| 79 | pinctrl-0 = <&pinctrl_usdhc3_1>; | 433 | pinctrl-0 = <&pinctrl_usdhc3>; |
| 80 | pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>; | 434 | pinctrl-1 = <&pinctrl_usdhc3_100mhz>; |
| 81 | pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>; | 435 | pinctrl-2 = <&pinctrl_usdhc3_200mhz>; |
| 82 | cd-gpios = <&gpio6 15 0>; | 436 | cd-gpios = <&gpio6 15 0>; |
| 83 | wp-gpios = <&gpio1 13 0>; | 437 | wp-gpios = <&gpio1 13 0>; |
| 84 | status = "okay"; | 438 | status = "okay"; |
| @@ -86,7 +440,7 @@ | |||
| 86 | 440 | ||
| 87 | &weim { | 441 | &weim { |
| 88 | pinctrl-names = "default"; | 442 | pinctrl-names = "default"; |
| 89 | pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>; | 443 | pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>; |
| 90 | #address-cells = <2>; | 444 | #address-cells = <2>; |
| 91 | #size-cells = <1>; | 445 | #size-cells = <1>; |
| 92 | ranges = <0 0 0x08000000 0x08000000>; | 446 | ranges = <0 0 0x08000000 0x08000000>; |
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi new file mode 100644 index 000000000000..3bec128c7971 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | |||
| @@ -0,0 +1,423 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. | ||
| 3 | * Copyright 2011 Linaro Ltd. | ||
| 4 | * | ||
| 5 | * The code contained herein is licensed under the GNU General Public | ||
| 6 | * License. You may obtain a copy of the GNU General Public License | ||
| 7 | * Version 2 or later at the following locations: | ||
| 8 | * | ||
| 9 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 10 | * http://www.gnu.org/copyleft/gpl.html | ||
| 11 | */ | ||
| 12 | #include <dt-bindings/gpio/gpio.h> | ||
| 13 | #include <dt-bindings/input/input.h> | ||
| 14 | |||
| 15 | / { | ||
| 16 | memory { | ||
| 17 | reg = <0x10000000 0x40000000>; | ||
| 18 | }; | ||
| 19 | |||
| 20 | regulators { | ||
| 21 | compatible = "simple-bus"; | ||
| 22 | #address-cells = <1>; | ||
| 23 | #size-cells = <0>; | ||
| 24 | |||
| 25 | reg_2p5v: regulator@0 { | ||
| 26 | compatible = "regulator-fixed"; | ||
| 27 | reg = <0>; | ||
| 28 | regulator-name = "2P5V"; | ||
| 29 | regulator-min-microvolt = <2500000>; | ||
| 30 | regulator-max-microvolt = <2500000>; | ||
| 31 | regulator-always-on; | ||
| 32 | }; | ||
| 33 | |||
| 34 | reg_3p3v: regulator@1 { | ||
| 35 | compatible = "regulator-fixed"; | ||
| 36 | reg = <1>; | ||
| 37 | regulator-name = "3P3V"; | ||
| 38 | regulator-min-microvolt = <3300000>; | ||
| 39 | regulator-max-microvolt = <3300000>; | ||
| 40 | regulator-always-on; | ||
| 41 | }; | ||
| 42 | |||
| 43 | reg_usb_otg_vbus: regulator@2 { | ||
| 44 | compatible = "regulator-fixed"; | ||
| 45 | reg = <2>; | ||
| 46 | regulator-name = "usb_otg_vbus"; | ||
| 47 | regulator-min-microvolt = <5000000>; | ||
| 48 | regulator-max-microvolt = <5000000>; | ||
| 49 | gpio = <&gpio3 22 0>; | ||
| 50 | enable-active-high; | ||
| 51 | }; | ||
| 52 | }; | ||
| 53 | |||
| 54 | gpio-keys { | ||
| 55 | compatible = "gpio-keys"; | ||
| 56 | pinctrl-names = "default"; | ||
| 57 | pinctrl-0 = <&pinctrl_gpio_keys>; | ||
| 58 | |||
| 59 | power { | ||
| 60 | label = "Power Button"; | ||
| 61 | gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; | ||
| 62 | linux,code = <KEY_POWER>; | ||
| 63 | gpio-key,wakeup; | ||
| 64 | }; | ||
| 65 | |||
| 66 | menu { | ||
| 67 | label = "Menu"; | ||
| 68 | gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; | ||
| 69 | linux,code = <KEY_MENU>; | ||
| 70 | }; | ||
| 71 | |||
| 72 | home { | ||
| 73 | label = "Home"; | ||
| 74 | gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; | ||
| 75 | linux,code = <KEY_HOME>; | ||
| 76 | }; | ||
| 77 | |||
| 78 | back { | ||
| 79 | label = "Back"; | ||
| 80 | gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; | ||
| 81 | linux,code = <KEY_BACK>; | ||
| 82 | }; | ||
| 83 | |||
| 84 | volume-up { | ||
| 85 | label = "Volume Up"; | ||
| 86 | gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; | ||
| 87 | linux,code = <KEY_VOLUMEUP>; | ||
| 88 | }; | ||
| 89 | |||
| 90 | volume-down { | ||
| 91 | label = "Volume Down"; | ||
| 92 | gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; | ||
| 93 | linux,code = <KEY_VOLUMEDOWN>; | ||
| 94 | }; | ||
| 95 | }; | ||
| 96 | |||
| 97 | sound { | ||
| 98 | compatible = "fsl,imx6q-sabrelite-sgtl5000", | ||
| 99 | "fsl,imx-audio-sgtl5000"; | ||
| 100 | model = "imx6q-sabrelite-sgtl5000"; | ||
| 101 | ssi-controller = <&ssi1>; | ||
| 102 | audio-codec = <&codec>; | ||
| 103 | audio-routing = | ||
| 104 | "MIC_IN", "Mic Jack", | ||
| 105 | "Mic Jack", "Mic Bias", | ||
| 106 | "Headphone Jack", "HP_OUT"; | ||
| 107 | mux-int-port = <1>; | ||
| 108 | mux-ext-port = <4>; | ||
| 109 | }; | ||
| 110 | |||
| 111 | backlight_lcd { | ||
| 112 | compatible = "pwm-backlight"; | ||
| 113 | pwms = <&pwm1 0 5000000>; | ||
| 114 | brightness-levels = <0 4 8 16 32 64 128 255>; | ||
| 115 | default-brightness-level = <7>; | ||
| 116 | power-supply = <®_3p3v>; | ||
| 117 | status = "okay"; | ||
| 118 | }; | ||
| 119 | |||
| 120 | backlight_lvds { | ||
| 121 | compatible = "pwm-backlight"; | ||
| 122 | pwms = <&pwm4 0 5000000>; | ||
| 123 | brightness-levels = <0 4 8 16 32 64 128 255>; | ||
| 124 | default-brightness-level = <7>; | ||
| 125 | power-supply = <®_3p3v>; | ||
| 126 | status = "okay"; | ||
| 127 | }; | ||
| 128 | }; | ||
| 129 | |||
| 130 | &audmux { | ||
| 131 | pinctrl-names = "default"; | ||
| 132 | pinctrl-0 = <&pinctrl_audmux>; | ||
| 133 | status = "okay"; | ||
| 134 | }; | ||
| 135 | |||
| 136 | &ecspi1 { | ||
| 137 | fsl,spi-num-chipselects = <1>; | ||
| 138 | cs-gpios = <&gpio3 19 0>; | ||
| 139 | pinctrl-names = "default"; | ||
| 140 | pinctrl-0 = <&pinctrl_ecspi1>; | ||
| 141 | status = "okay"; | ||
| 142 | |||
| 143 | flash: m25p80@0 { | ||
| 144 | compatible = "sst,sst25vf016b"; | ||
| 145 | spi-max-frequency = <20000000>; | ||
| 146 | reg = <0>; | ||
| 147 | }; | ||
| 148 | }; | ||
| 149 | |||
| 150 | &fec { | ||
| 151 | pinctrl-names = "default"; | ||
| 152 | pinctrl-0 = <&pinctrl_enet>; | ||
| 153 | phy-mode = "rgmii"; | ||
| 154 | phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; | ||
| 155 | txen-skew-ps = <0>; | ||
| 156 | txc-skew-ps = <3000>; | ||
| 157 | rxdv-skew-ps = <0>; | ||
| 158 | rxc-skew-ps = <3000>; | ||
| 159 | rxd0-skew-ps = <0>; | ||
| 160 | rxd1-skew-ps = <0>; | ||
| 161 | rxd2-skew-ps = <0>; | ||
| 162 | rxd3-skew-ps = <0>; | ||
| 163 | txd0-skew-ps = <0>; | ||
| 164 | txd1-skew-ps = <0>; | ||
| 165 | txd2-skew-ps = <0>; | ||
| 166 | txd3-skew-ps = <0>; | ||
| 167 | interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, | ||
| 168 | <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; | ||
| 169 | status = "okay"; | ||
| 170 | }; | ||
| 171 | |||
| 172 | &i2c1 { | ||
| 173 | clock-frequency = <100000>; | ||
| 174 | pinctrl-names = "default"; | ||
| 175 | pinctrl-0 = <&pinctrl_i2c1>; | ||
| 176 | status = "okay"; | ||
| 177 | |||
| 178 | codec: sgtl5000@0a { | ||
| 179 | compatible = "fsl,sgtl5000"; | ||
| 180 | reg = <0x0a>; | ||
| 181 | clocks = <&clks 201>; | ||
| 182 | VDDA-supply = <®_2p5v>; | ||
| 183 | VDDIO-supply = <®_3p3v>; | ||
| 184 | }; | ||
| 185 | }; | ||
| 186 | |||
| 187 | &iomuxc { | ||
| 188 | pinctrl-names = "default"; | ||
| 189 | pinctrl-0 = <&pinctrl_hog>; | ||
| 190 | |||
| 191 | imx6q-sabrelite { | ||
| 192 | pinctrl_hog: hoggrp { | ||
| 193 | fsl,pins = < | ||
| 194 | /* SGTL5000 sys_mclk */ | ||
| 195 | MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 | ||
| 196 | >; | ||
| 197 | }; | ||
| 198 | |||
| 199 | pinctrl_audmux: audmuxgrp { | ||
| 200 | fsl,pins = < | ||
| 201 | MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 | ||
| 202 | MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 | ||
| 203 | MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 | ||
| 204 | MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 | ||
| 205 | >; | ||
| 206 | }; | ||
| 207 | |||
| 208 | pinctrl_ecspi1: ecspi1grp { | ||
| 209 | fsl,pins = < | ||
| 210 | MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 | ||
| 211 | MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 | ||
| 212 | MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 | ||
| 213 | MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */ | ||
| 214 | >; | ||
| 215 | }; | ||
| 216 | |||
| 217 | pinctrl_enet: enetgrp { | ||
| 218 | fsl,pins = < | ||
| 219 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 | ||
| 220 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 | ||
| 221 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 | ||
| 222 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 | ||
| 223 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 | ||
| 224 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 | ||
| 225 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 | ||
| 226 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 | ||
| 227 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 | ||
| 228 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 229 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 230 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 231 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 232 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 233 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 234 | /* Phy reset */ | ||
| 235 | MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x000b0 | ||
| 236 | MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 | ||
| 237 | >; | ||
| 238 | }; | ||
| 239 | |||
| 240 | pinctrl_gpio_keys: gpio_keysgrp { | ||
| 241 | fsl,pins = < | ||
| 242 | /* Power Button */ | ||
| 243 | MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 | ||
| 244 | /* Menu Button */ | ||
| 245 | MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 | ||
| 246 | /* Home Button */ | ||
| 247 | MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 | ||
| 248 | /* Back Button */ | ||
| 249 | MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 | ||
| 250 | /* Volume Up Button */ | ||
| 251 | MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 | ||
| 252 | /* Volume Down Button */ | ||
| 253 | MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 | ||
| 254 | >; | ||
| 255 | }; | ||
| 256 | |||
| 257 | pinctrl_i2c1: i2c1grp { | ||
| 258 | fsl,pins = < | ||
| 259 | MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 | ||
| 260 | MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 | ||
| 261 | >; | ||
| 262 | }; | ||
| 263 | |||
| 264 | pinctrl_pwm1: pwm1grp { | ||
| 265 | fsl,pins = < | ||
| 266 | MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 | ||
| 267 | >; | ||
| 268 | }; | ||
| 269 | |||
| 270 | pinctrl_pwm3: pwm3grp { | ||
| 271 | fsl,pins = < | ||
| 272 | MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 | ||
| 273 | >; | ||
| 274 | }; | ||
| 275 | |||
| 276 | pinctrl_pwm4: pwm4grp { | ||
| 277 | fsl,pins = < | ||
| 278 | MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 | ||
| 279 | >; | ||
| 280 | }; | ||
| 281 | |||
| 282 | pinctrl_uart1: uart1grp { | ||
| 283 | fsl,pins = < | ||
| 284 | MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 | ||
| 285 | MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 | ||
| 286 | >; | ||
| 287 | }; | ||
| 288 | |||
| 289 | pinctrl_uart2: uart2grp { | ||
| 290 | fsl,pins = < | ||
| 291 | MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 | ||
| 292 | MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 | ||
| 293 | >; | ||
| 294 | }; | ||
| 295 | |||
| 296 | pinctrl_usbotg: usbotggrp { | ||
| 297 | fsl,pins = < | ||
| 298 | MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 | ||
| 299 | MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 | ||
| 300 | /* power enable, high active */ | ||
| 301 | MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 | ||
| 302 | >; | ||
| 303 | }; | ||
| 304 | |||
| 305 | pinctrl_usdhc3: usdhc3grp { | ||
| 306 | fsl,pins = < | ||
| 307 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 308 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 309 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 310 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 311 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 312 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 313 | MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ | ||
| 314 | MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* WP */ | ||
| 315 | >; | ||
| 316 | }; | ||
| 317 | |||
| 318 | pinctrl_usdhc4: usdhc4grp { | ||
| 319 | fsl,pins = < | ||
| 320 | MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 | ||
| 321 | MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 | ||
| 322 | MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 | ||
| 323 | MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 | ||
| 324 | MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 | ||
| 325 | MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 | ||
| 326 | MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */ | ||
| 327 | >; | ||
| 328 | }; | ||
| 329 | }; | ||
| 330 | }; | ||
| 331 | |||
| 332 | &ldb { | ||
| 333 | status = "okay"; | ||
| 334 | |||
| 335 | lvds-channel@0 { | ||
| 336 | fsl,data-mapping = "spwg"; | ||
| 337 | fsl,data-width = <18>; | ||
| 338 | status = "okay"; | ||
| 339 | |||
| 340 | display-timings { | ||
| 341 | native-mode = <&timing0>; | ||
| 342 | timing0: hsd100pxn1 { | ||
| 343 | clock-frequency = <65000000>; | ||
| 344 | hactive = <1024>; | ||
| 345 | vactive = <768>; | ||
| 346 | hback-porch = <220>; | ||
| 347 | hfront-porch = <40>; | ||
| 348 | vback-porch = <21>; | ||
| 349 | vfront-porch = <7>; | ||
| 350 | hsync-len = <60>; | ||
| 351 | vsync-len = <10>; | ||
| 352 | }; | ||
| 353 | }; | ||
| 354 | }; | ||
| 355 | }; | ||
| 356 | |||
| 357 | &pcie { | ||
| 358 | status = "okay"; | ||
| 359 | }; | ||
| 360 | |||
| 361 | &pwm1 { | ||
| 362 | pinctrl-names = "default"; | ||
| 363 | pinctrl-0 = <&pinctrl_pwm1>; | ||
| 364 | status = "okay"; | ||
| 365 | }; | ||
| 366 | |||
| 367 | &pwm3 { | ||
| 368 | pinctrl-names = "default"; | ||
| 369 | pinctrl-0 = <&pinctrl_pwm3>; | ||
| 370 | status = "okay"; | ||
| 371 | }; | ||
| 372 | |||
| 373 | &pwm4 { | ||
| 374 | pinctrl-names = "default"; | ||
| 375 | pinctrl-0 = <&pinctrl_pwm4>; | ||
| 376 | status = "okay"; | ||
| 377 | }; | ||
| 378 | |||
| 379 | &ssi1 { | ||
| 380 | fsl,mode = "i2s-slave"; | ||
| 381 | status = "okay"; | ||
| 382 | }; | ||
| 383 | |||
| 384 | &uart1 { | ||
| 385 | pinctrl-names = "default"; | ||
| 386 | pinctrl-0 = <&pinctrl_uart1>; | ||
| 387 | status = "okay"; | ||
| 388 | }; | ||
| 389 | |||
| 390 | &uart2 { | ||
| 391 | pinctrl-names = "default"; | ||
| 392 | pinctrl-0 = <&pinctrl_uart2>; | ||
| 393 | status = "okay"; | ||
| 394 | }; | ||
| 395 | |||
| 396 | &usbh1 { | ||
| 397 | status = "okay"; | ||
| 398 | }; | ||
| 399 | |||
| 400 | &usbotg { | ||
| 401 | vbus-supply = <®_usb_otg_vbus>; | ||
| 402 | pinctrl-names = "default"; | ||
| 403 | pinctrl-0 = <&pinctrl_usbotg>; | ||
| 404 | disable-over-current; | ||
| 405 | status = "okay"; | ||
| 406 | }; | ||
| 407 | |||
| 408 | &usdhc3 { | ||
| 409 | pinctrl-names = "default"; | ||
| 410 | pinctrl-0 = <&pinctrl_usdhc3>; | ||
| 411 | cd-gpios = <&gpio7 0 0>; | ||
| 412 | wp-gpios = <&gpio7 1 0>; | ||
| 413 | vmmc-supply = <®_3p3v>; | ||
| 414 | status = "okay"; | ||
| 415 | }; | ||
| 416 | |||
| 417 | &usdhc4 { | ||
| 418 | pinctrl-names = "default"; | ||
| 419 | pinctrl-0 = <&pinctrl_usdhc4>; | ||
| 420 | cd-gpios = <&gpio2 6 0>; | ||
| 421 | vmmc-supply = <®_3p3v>; | ||
| 422 | status = "okay"; | ||
| 423 | }; | ||
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index e75e11b36dff..0d816d3be4b6 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi | |||
| @@ -10,6 +10,9 @@ | |||
| 10 | * http://www.gnu.org/copyleft/gpl.html | 10 | * http://www.gnu.org/copyleft/gpl.html |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | #include <dt-bindings/gpio/gpio.h> | ||
| 14 | #include <dt-bindings/input/input.h> | ||
| 15 | |||
| 13 | / { | 16 | / { |
| 14 | memory { | 17 | memory { |
| 15 | reg = <0x10000000 0x40000000>; | 18 | reg = <0x10000000 0x40000000>; |
| @@ -17,9 +20,12 @@ | |||
| 17 | 20 | ||
| 18 | regulators { | 21 | regulators { |
| 19 | compatible = "simple-bus"; | 22 | compatible = "simple-bus"; |
| 23 | #address-cells = <1>; | ||
| 24 | #size-cells = <0>; | ||
| 20 | 25 | ||
| 21 | reg_usb_otg_vbus: usb_otg_vbus { | 26 | reg_usb_otg_vbus: regulator@0 { |
| 22 | compatible = "regulator-fixed"; | 27 | compatible = "regulator-fixed"; |
| 28 | reg = <0>; | ||
| 23 | regulator-name = "usb_otg_vbus"; | 29 | regulator-name = "usb_otg_vbus"; |
| 24 | regulator-min-microvolt = <5000000>; | 30 | regulator-min-microvolt = <5000000>; |
| 25 | regulator-max-microvolt = <5000000>; | 31 | regulator-max-microvolt = <5000000>; |
| @@ -27,8 +33,9 @@ | |||
| 27 | enable-active-high; | 33 | enable-active-high; |
| 28 | }; | 34 | }; |
| 29 | 35 | ||
| 30 | reg_usb_h1_vbus: usb_h1_vbus { | 36 | reg_usb_h1_vbus: regulator@1 { |
| 31 | compatible = "regulator-fixed"; | 37 | compatible = "regulator-fixed"; |
| 38 | reg = <1>; | ||
| 32 | regulator-name = "usb_h1_vbus"; | 39 | regulator-name = "usb_h1_vbus"; |
| 33 | regulator-min-microvolt = <5000000>; | 40 | regulator-min-microvolt = <5000000>; |
| 34 | regulator-max-microvolt = <5000000>; | 41 | regulator-max-microvolt = <5000000>; |
| @@ -36,8 +43,9 @@ | |||
| 36 | enable-active-high; | 43 | enable-active-high; |
| 37 | }; | 44 | }; |
| 38 | 45 | ||
| 39 | reg_audio: wm8962_supply { | 46 | reg_audio: regulator@2 { |
| 40 | compatible = "regulator-fixed"; | 47 | compatible = "regulator-fixed"; |
| 48 | reg = <2>; | ||
| 41 | regulator-name = "wm8962-supply"; | 49 | regulator-name = "wm8962-supply"; |
| 42 | gpio = <&gpio4 10 0>; | 50 | gpio = <&gpio4 10 0>; |
| 43 | enable-active-high; | 51 | enable-active-high; |
| @@ -46,19 +54,28 @@ | |||
| 46 | 54 | ||
| 47 | gpio-keys { | 55 | gpio-keys { |
| 48 | compatible = "gpio-keys"; | 56 | compatible = "gpio-keys"; |
| 57 | pinctrl-names = "default"; | ||
| 58 | pinctrl-0 = <&pinctrl_gpio_keys>; | ||
| 59 | |||
| 60 | power { | ||
| 61 | label = "Power Button"; | ||
| 62 | gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; | ||
| 63 | gpio-key,wakeup; | ||
| 64 | linux,code = <KEY_POWER>; | ||
| 65 | }; | ||
| 49 | 66 | ||
| 50 | volume-up { | 67 | volume-up { |
| 51 | label = "Volume Up"; | 68 | label = "Volume Up"; |
| 52 | gpios = <&gpio1 4 0>; | 69 | gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; |
| 53 | gpio-key,wakeup; | 70 | gpio-key,wakeup; |
| 54 | linux,code = <115>; /* KEY_VOLUMEUP */ | 71 | linux,code = <KEY_VOLUMEUP>; |
| 55 | }; | 72 | }; |
| 56 | 73 | ||
| 57 | volume-down { | 74 | volume-down { |
| 58 | label = "Volume Down"; | 75 | label = "Volume Down"; |
| 59 | gpios = <&gpio1 5 0>; | 76 | gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; |
| 60 | gpio-key,wakeup; | 77 | gpio-key,wakeup; |
| 61 | linux,code = <114>; /* KEY_VOLUMEDOWN */ | 78 | linux,code = <KEY_VOLUMEDOWN>; |
| 62 | }; | 79 | }; |
| 63 | }; | 80 | }; |
| 64 | 81 | ||
| @@ -92,7 +109,7 @@ | |||
| 92 | 109 | ||
| 93 | &audmux { | 110 | &audmux { |
| 94 | pinctrl-names = "default"; | 111 | pinctrl-names = "default"; |
| 95 | pinctrl-0 = <&pinctrl_audmux_2>; | 112 | pinctrl-0 = <&pinctrl_audmux>; |
| 96 | status = "okay"; | 113 | status = "okay"; |
| 97 | }; | 114 | }; |
| 98 | 115 | ||
| @@ -100,7 +117,7 @@ | |||
| 100 | fsl,spi-num-chipselects = <1>; | 117 | fsl,spi-num-chipselects = <1>; |
| 101 | cs-gpios = <&gpio4 9 0>; | 118 | cs-gpios = <&gpio4 9 0>; |
| 102 | pinctrl-names = "default"; | 119 | pinctrl-names = "default"; |
| 103 | pinctrl-0 = <&pinctrl_ecspi1_2>; | 120 | pinctrl-0 = <&pinctrl_ecspi1>; |
| 104 | status = "okay"; | 121 | status = "okay"; |
| 105 | 122 | ||
| 106 | flash: m25p80@0 { | 123 | flash: m25p80@0 { |
| @@ -114,7 +131,7 @@ | |||
| 114 | 131 | ||
| 115 | &fec { | 132 | &fec { |
| 116 | pinctrl-names = "default"; | 133 | pinctrl-names = "default"; |
| 117 | pinctrl-0 = <&pinctrl_enet_1>; | 134 | pinctrl-0 = <&pinctrl_enet>; |
| 118 | phy-mode = "rgmii"; | 135 | phy-mode = "rgmii"; |
| 119 | phy-reset-gpios = <&gpio1 25 0>; | 136 | phy-reset-gpios = <&gpio1 25 0>; |
| 120 | status = "okay"; | 137 | status = "okay"; |
| @@ -123,7 +140,7 @@ | |||
| 123 | &i2c1 { | 140 | &i2c1 { |
| 124 | clock-frequency = <100000>; | 141 | clock-frequency = <100000>; |
| 125 | pinctrl-names = "default"; | 142 | pinctrl-names = "default"; |
| 126 | pinctrl-0 = <&pinctrl_i2c1_2>; | 143 | pinctrl-0 = <&pinctrl_i2c1>; |
| 127 | status = "okay"; | 144 | status = "okay"; |
| 128 | 145 | ||
| 129 | codec: wm8962@1a { | 146 | codec: wm8962@1a { |
| @@ -149,10 +166,116 @@ | |||
| 149 | }; | 166 | }; |
| 150 | }; | 167 | }; |
| 151 | 168 | ||
| 169 | &i2c2 { | ||
| 170 | clock-frequency = <100000>; | ||
| 171 | pinctrl-names = "default"; | ||
| 172 | pinctrl-0 = <&pinctrl_i2c2>; | ||
| 173 | status = "okay"; | ||
| 174 | |||
| 175 | pmic: pfuze100@08 { | ||
| 176 | compatible = "fsl,pfuze100"; | ||
| 177 | reg = <0x08>; | ||
| 178 | |||
| 179 | regulators { | ||
| 180 | sw1a_reg: sw1ab { | ||
| 181 | regulator-min-microvolt = <300000>; | ||
| 182 | regulator-max-microvolt = <1875000>; | ||
| 183 | regulator-boot-on; | ||
| 184 | regulator-always-on; | ||
| 185 | regulator-ramp-delay = <6250>; | ||
| 186 | }; | ||
| 187 | |||
| 188 | sw1c_reg: sw1c { | ||
| 189 | regulator-min-microvolt = <300000>; | ||
| 190 | regulator-max-microvolt = <1875000>; | ||
| 191 | regulator-boot-on; | ||
| 192 | regulator-always-on; | ||
| 193 | regulator-ramp-delay = <6250>; | ||
| 194 | }; | ||
| 195 | |||
| 196 | sw2_reg: sw2 { | ||
| 197 | regulator-min-microvolt = <800000>; | ||
| 198 | regulator-max-microvolt = <3300000>; | ||
| 199 | regulator-boot-on; | ||
| 200 | regulator-always-on; | ||
| 201 | }; | ||
| 202 | |||
| 203 | sw3a_reg: sw3a { | ||
| 204 | regulator-min-microvolt = <400000>; | ||
| 205 | regulator-max-microvolt = <1975000>; | ||
| 206 | regulator-boot-on; | ||
| 207 | regulator-always-on; | ||
| 208 | }; | ||
| 209 | |||
| 210 | sw3b_reg: sw3b { | ||
| 211 | regulator-min-microvolt = <400000>; | ||
| 212 | regulator-max-microvolt = <1975000>; | ||
| 213 | regulator-boot-on; | ||
| 214 | regulator-always-on; | ||
| 215 | }; | ||
| 216 | |||
| 217 | sw4_reg: sw4 { | ||
| 218 | regulator-min-microvolt = <800000>; | ||
| 219 | regulator-max-microvolt = <3300000>; | ||
| 220 | }; | ||
| 221 | |||
| 222 | swbst_reg: swbst { | ||
| 223 | regulator-min-microvolt = <5000000>; | ||
| 224 | regulator-max-microvolt = <5150000>; | ||
| 225 | }; | ||
| 226 | |||
| 227 | snvs_reg: vsnvs { | ||
| 228 | regulator-min-microvolt = <1000000>; | ||
| 229 | regulator-max-microvolt = <3000000>; | ||
| 230 | regulator-boot-on; | ||
| 231 | regulator-always-on; | ||
| 232 | }; | ||
| 233 | |||
| 234 | vref_reg: vrefddr { | ||
| 235 | regulator-boot-on; | ||
| 236 | regulator-always-on; | ||
| 237 | }; | ||
| 238 | |||
| 239 | vgen1_reg: vgen1 { | ||
| 240 | regulator-min-microvolt = <800000>; | ||
| 241 | regulator-max-microvolt = <1550000>; | ||
| 242 | }; | ||
| 243 | |||
| 244 | vgen2_reg: vgen2 { | ||
| 245 | regulator-min-microvolt = <800000>; | ||
| 246 | regulator-max-microvolt = <1550000>; | ||
| 247 | }; | ||
| 248 | |||
| 249 | vgen3_reg: vgen3 { | ||
| 250 | regulator-min-microvolt = <1800000>; | ||
| 251 | regulator-max-microvolt = <3300000>; | ||
| 252 | }; | ||
| 253 | |||
| 254 | vgen4_reg: vgen4 { | ||
| 255 | regulator-min-microvolt = <1800000>; | ||
| 256 | regulator-max-microvolt = <3300000>; | ||
| 257 | regulator-always-on; | ||
| 258 | }; | ||
| 259 | |||
| 260 | vgen5_reg: vgen5 { | ||
| 261 | regulator-min-microvolt = <1800000>; | ||
| 262 | regulator-max-microvolt = <3300000>; | ||
| 263 | regulator-always-on; | ||
| 264 | }; | ||
| 265 | |||
| 266 | vgen6_reg: vgen6 { | ||
| 267 | regulator-min-microvolt = <1800000>; | ||
| 268 | regulator-max-microvolt = <3300000>; | ||
| 269 | regulator-always-on; | ||
| 270 | }; | ||
| 271 | }; | ||
| 272 | }; | ||
| 273 | }; | ||
| 274 | |||
| 152 | &i2c3 { | 275 | &i2c3 { |
| 153 | clock-frequency = <100000>; | 276 | clock-frequency = <100000>; |
| 154 | pinctrl-names = "default"; | 277 | pinctrl-names = "default"; |
| 155 | pinctrl-0 = <&pinctrl_i2c3_2>; | 278 | pinctrl-0 = <&pinctrl_i2c3>; |
| 156 | status = "okay"; | 279 | status = "okay"; |
| 157 | 280 | ||
| 158 | egalax_ts@04 { | 281 | egalax_ts@04 { |
| @@ -168,11 +291,9 @@ | |||
| 168 | pinctrl-names = "default"; | 291 | pinctrl-names = "default"; |
| 169 | pinctrl-0 = <&pinctrl_hog>; | 292 | pinctrl-0 = <&pinctrl_hog>; |
| 170 | 293 | ||
| 171 | hog { | 294 | imx6qdl-sabresd { |
| 172 | pinctrl_hog: hoggrp { | 295 | pinctrl_hog: hoggrp { |
| 173 | fsl,pins = < | 296 | fsl,pins = < |
| 174 | MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 | ||
| 175 | MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 | ||
| 176 | MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 | 297 | MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 |
| 177 | MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 | 298 | MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 |
| 178 | MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 | 299 | MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 |
| @@ -184,6 +305,122 @@ | |||
| 184 | MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 | 305 | MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 |
| 185 | >; | 306 | >; |
| 186 | }; | 307 | }; |
| 308 | |||
| 309 | pinctrl_audmux: audmuxgrp { | ||
| 310 | fsl,pins = < | ||
| 311 | MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 | ||
| 312 | MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 | ||
| 313 | MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 | ||
| 314 | MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 | ||
| 315 | >; | ||
| 316 | }; | ||
| 317 | |||
| 318 | pinctrl_ecspi1: ecspi1grp { | ||
| 319 | fsl,pins = < | ||
| 320 | MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 | ||
| 321 | MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 | ||
| 322 | MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 | ||
| 323 | >; | ||
| 324 | }; | ||
| 325 | |||
| 326 | pinctrl_enet: enetgrp { | ||
| 327 | fsl,pins = < | ||
| 328 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | ||
| 329 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | ||
| 330 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 331 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 332 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 333 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 334 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 335 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 336 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 337 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 338 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 339 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 340 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 341 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 342 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 343 | MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 | ||
| 344 | >; | ||
| 345 | }; | ||
| 346 | |||
| 347 | pinctrl_gpio_keys: gpio_keysgrp { | ||
| 348 | fsl,pins = < | ||
| 349 | MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 | ||
| 350 | MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 | ||
| 351 | MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 | ||
| 352 | >; | ||
| 353 | }; | ||
| 354 | |||
| 355 | pinctrl_i2c1: i2c1grp { | ||
| 356 | fsl,pins = < | ||
| 357 | MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 | ||
| 358 | MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 | ||
| 359 | >; | ||
| 360 | }; | ||
| 361 | |||
| 362 | pinctrl_i2c2: i2c2grp { | ||
| 363 | fsl,pins = < | ||
| 364 | MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 | ||
| 365 | MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 | ||
| 366 | >; | ||
| 367 | }; | ||
| 368 | |||
| 369 | pinctrl_i2c3: i2c3grp { | ||
| 370 | fsl,pins = < | ||
| 371 | MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 | ||
| 372 | MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 | ||
| 373 | >; | ||
| 374 | }; | ||
| 375 | |||
| 376 | pinctrl_pwm1: pwm1grp { | ||
| 377 | fsl,pins = < | ||
| 378 | MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 | ||
| 379 | >; | ||
| 380 | }; | ||
| 381 | |||
| 382 | pinctrl_uart1: uart1grp { | ||
| 383 | fsl,pins = < | ||
| 384 | MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 | ||
| 385 | MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 | ||
| 386 | >; | ||
| 387 | }; | ||
| 388 | |||
| 389 | pinctrl_usbotg: usbotggrp { | ||
| 390 | fsl,pins = < | ||
| 391 | MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 | ||
| 392 | >; | ||
| 393 | }; | ||
| 394 | |||
| 395 | pinctrl_usdhc2: usdhc2grp { | ||
| 396 | fsl,pins = < | ||
| 397 | MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 | ||
| 398 | MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 | ||
| 399 | MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 | ||
| 400 | MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 | ||
| 401 | MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 | ||
| 402 | MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 | ||
| 403 | MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 | ||
| 404 | MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 | ||
| 405 | MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 | ||
| 406 | MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 | ||
| 407 | >; | ||
| 408 | }; | ||
| 409 | |||
| 410 | pinctrl_usdhc3: usdhc3grp { | ||
| 411 | fsl,pins = < | ||
| 412 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 413 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 414 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 415 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 416 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 417 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 418 | MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 | ||
| 419 | MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 | ||
| 420 | MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 | ||
| 421 | MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 | ||
| 422 | >; | ||
| 423 | }; | ||
| 187 | }; | 424 | }; |
| 188 | }; | 425 | }; |
| 189 | 426 | ||
| @@ -214,7 +451,7 @@ | |||
| 214 | 451 | ||
| 215 | &pwm1 { | 452 | &pwm1 { |
| 216 | pinctrl-names = "default"; | 453 | pinctrl-names = "default"; |
| 217 | pinctrl-0 = <&pinctrl_pwm0_1>; | 454 | pinctrl-0 = <&pinctrl_pwm1>; |
| 218 | status = "okay"; | 455 | status = "okay"; |
| 219 | }; | 456 | }; |
| 220 | 457 | ||
| @@ -225,7 +462,7 @@ | |||
| 225 | 462 | ||
| 226 | &uart1 { | 463 | &uart1 { |
| 227 | pinctrl-names = "default"; | 464 | pinctrl-names = "default"; |
| 228 | pinctrl-0 = <&pinctrl_uart1_1>; | 465 | pinctrl-0 = <&pinctrl_uart1>; |
| 229 | status = "okay"; | 466 | status = "okay"; |
| 230 | }; | 467 | }; |
| 231 | 468 | ||
| @@ -237,14 +474,14 @@ | |||
| 237 | &usbotg { | 474 | &usbotg { |
| 238 | vbus-supply = <®_usb_otg_vbus>; | 475 | vbus-supply = <®_usb_otg_vbus>; |
| 239 | pinctrl-names = "default"; | 476 | pinctrl-names = "default"; |
| 240 | pinctrl-0 = <&pinctrl_usbotg_2>; | 477 | pinctrl-0 = <&pinctrl_usbotg>; |
| 241 | disable-over-current; | 478 | disable-over-current; |
| 242 | status = "okay"; | 479 | status = "okay"; |
| 243 | }; | 480 | }; |
| 244 | 481 | ||
| 245 | &usdhc2 { | 482 | &usdhc2 { |
| 246 | pinctrl-names = "default"; | 483 | pinctrl-names = "default"; |
| 247 | pinctrl-0 = <&pinctrl_usdhc2_1>; | 484 | pinctrl-0 = <&pinctrl_usdhc2>; |
| 248 | bus-width = <8>; | 485 | bus-width = <8>; |
| 249 | cd-gpios = <&gpio2 2 0>; | 486 | cd-gpios = <&gpio2 2 0>; |
| 250 | wp-gpios = <&gpio2 3 0>; | 487 | wp-gpios = <&gpio2 3 0>; |
| @@ -253,7 +490,7 @@ | |||
| 253 | 490 | ||
| 254 | &usdhc3 { | 491 | &usdhc3 { |
| 255 | pinctrl-names = "default"; | 492 | pinctrl-names = "default"; |
| 256 | pinctrl-0 = <&pinctrl_usdhc3_1>; | 493 | pinctrl-0 = <&pinctrl_usdhc3>; |
| 257 | bus-width = <8>; | 494 | bus-width = <8>; |
| 258 | cd-gpios = <&gpio2 0 0>; | 495 | cd-gpios = <&gpio2 0 0>; |
| 259 | wp-gpios = <&gpio2 1 0>; | 496 | wp-gpios = <&gpio2 1 0>; |
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi index 35f547929167..bdfdf89d405f 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi | |||
| @@ -12,17 +12,21 @@ | |||
| 12 | / { | 12 | / { |
| 13 | regulators { | 13 | regulators { |
| 14 | compatible = "simple-bus"; | 14 | compatible = "simple-bus"; |
| 15 | #address-cells = <1>; | ||
| 16 | #size-cells = <0>; | ||
| 15 | 17 | ||
| 16 | reg_2p5v: 2p5v { | 18 | reg_2p5v: regulator@0 { |
| 17 | compatible = "regulator-fixed"; | 19 | compatible = "regulator-fixed"; |
| 20 | reg = <0>; | ||
| 18 | regulator-name = "2P5V"; | 21 | regulator-name = "2P5V"; |
| 19 | regulator-min-microvolt = <2500000>; | 22 | regulator-min-microvolt = <2500000>; |
| 20 | regulator-max-microvolt = <2500000>; | 23 | regulator-max-microvolt = <2500000>; |
| 21 | regulator-always-on; | 24 | regulator-always-on; |
| 22 | }; | 25 | }; |
| 23 | 26 | ||
| 24 | reg_3p3v: 3p3v { | 27 | reg_3p3v: regulator@1 { |
| 25 | compatible = "regulator-fixed"; | 28 | compatible = "regulator-fixed"; |
| 29 | reg = <1>; | ||
| 26 | regulator-name = "3P3V"; | 30 | regulator-name = "3P3V"; |
| 27 | regulator-min-microvolt = <3300000>; | 31 | regulator-min-microvolt = <3300000>; |
| 28 | regulator-max-microvolt = <3300000>; | 32 | regulator-max-microvolt = <3300000>; |
| @@ -54,14 +58,14 @@ | |||
| 54 | 58 | ||
| 55 | &audmux { | 59 | &audmux { |
| 56 | pinctrl-names = "default"; | 60 | pinctrl-names = "default"; |
| 57 | pinctrl-0 = <&pinctrl_audmux_2>; | 61 | pinctrl-0 = <&pinctrl_audmux>; |
| 58 | status = "okay"; | 62 | status = "okay"; |
| 59 | }; | 63 | }; |
| 60 | 64 | ||
| 61 | &i2c2 { | 65 | &i2c2 { |
| 62 | clock-frequency = <100000>; | 66 | clock-frequency = <100000>; |
| 63 | pinctrl-names = "default"; | 67 | pinctrl-names = "default"; |
| 64 | pinctrl-0 = <&pinctrl_i2c2_2>; | 68 | pinctrl-0 = <&pinctrl_i2c2>; |
| 65 | status = "okay"; | 69 | status = "okay"; |
| 66 | 70 | ||
| 67 | codec: sgtl5000@0a { | 71 | codec: sgtl5000@0a { |
| @@ -77,7 +81,7 @@ | |||
| 77 | pinctrl-names = "default"; | 81 | pinctrl-names = "default"; |
| 78 | pinctrl-0 = <&pinctrl_hog>; | 82 | pinctrl-0 = <&pinctrl_hog>; |
| 79 | 83 | ||
| 80 | hog { | 84 | imx6qdl-wandboard { |
| 81 | pinctrl_hog: hoggrp { | 85 | pinctrl_hog: hoggrp { |
| 82 | fsl,pins = < | 86 | fsl,pins = < |
| 83 | MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 | 87 | MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 |
| @@ -91,20 +95,121 @@ | |||
| 91 | MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 | 95 | MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 |
| 92 | >; | 96 | >; |
| 93 | }; | 97 | }; |
| 98 | |||
| 99 | pinctrl_audmux: audmuxgrp { | ||
| 100 | fsl,pins = < | ||
| 101 | MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 | ||
| 102 | MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 | ||
| 103 | MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 | ||
| 104 | MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 | ||
| 105 | >; | ||
| 106 | }; | ||
| 107 | |||
| 108 | pinctrl_enet: enetgrp { | ||
| 109 | fsl,pins = < | ||
| 110 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | ||
| 111 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | ||
| 112 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 113 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 114 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 115 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 116 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 117 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 118 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 119 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 120 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 121 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 122 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 123 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 124 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 125 | MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 | ||
| 126 | MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 | ||
| 127 | >; | ||
| 128 | }; | ||
| 129 | |||
| 130 | pinctrl_i2c2: i2c2grp { | ||
| 131 | fsl,pins = < | ||
| 132 | MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 | ||
| 133 | MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 | ||
| 134 | >; | ||
| 135 | }; | ||
| 136 | |||
| 137 | pinctrl_spdif: spdifgrp { | ||
| 138 | fsl,pins = < | ||
| 139 | MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0 | ||
| 140 | >; | ||
| 141 | }; | ||
| 142 | |||
| 143 | pinctrl_uart1: uart1grp { | ||
| 144 | fsl,pins = < | ||
| 145 | MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 | ||
| 146 | MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 | ||
| 147 | >; | ||
| 148 | }; | ||
| 149 | |||
| 150 | pinctrl_uart3: uart3grp { | ||
| 151 | fsl,pins = < | ||
| 152 | MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 | ||
| 153 | MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 | ||
| 154 | MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 | ||
| 155 | MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 | ||
| 156 | >; | ||
| 157 | }; | ||
| 158 | |||
| 159 | pinctrl_usbotg: usbotggrp { | ||
| 160 | fsl,pins = < | ||
| 161 | MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 | ||
| 162 | >; | ||
| 163 | }; | ||
| 164 | |||
| 165 | pinctrl_usdhc1: usdhc1grp { | ||
| 166 | fsl,pins = < | ||
| 167 | MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 | ||
| 168 | MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 | ||
| 169 | MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 | ||
| 170 | MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 | ||
| 171 | MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 | ||
| 172 | MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 | ||
| 173 | >; | ||
| 174 | }; | ||
| 175 | |||
| 176 | pinctrl_usdhc2: usdhc2grp { | ||
| 177 | fsl,pins = < | ||
| 178 | MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 | ||
| 179 | MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 | ||
| 180 | MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 | ||
| 181 | MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 | ||
| 182 | MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 | ||
| 183 | MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 | ||
| 184 | >; | ||
| 185 | }; | ||
| 186 | |||
| 187 | pinctrl_usdhc3: usdhc3grp { | ||
| 188 | fsl,pins = < | ||
| 189 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 190 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 191 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 192 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 193 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 194 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 195 | >; | ||
| 196 | }; | ||
| 94 | }; | 197 | }; |
| 95 | }; | 198 | }; |
| 96 | 199 | ||
| 97 | &fec { | 200 | &fec { |
| 98 | pinctrl-names = "default"; | 201 | pinctrl-names = "default"; |
| 99 | pinctrl-0 = <&pinctrl_enet_1>; | 202 | pinctrl-0 = <&pinctrl_enet>; |
| 100 | phy-mode = "rgmii"; | 203 | phy-mode = "rgmii"; |
| 101 | phy-reset-gpios = <&gpio3 29 0>; | 204 | phy-reset-gpios = <&gpio3 29 0>; |
| 205 | interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, | ||
| 206 | <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; | ||
| 102 | status = "okay"; | 207 | status = "okay"; |
| 103 | }; | 208 | }; |
| 104 | 209 | ||
| 105 | &spdif { | 210 | &spdif { |
| 106 | pinctrl-names = "default"; | 211 | pinctrl-names = "default"; |
| 107 | pinctrl-0 = <&pinctrl_spdif_3>; | 212 | pinctrl-0 = <&pinctrl_spdif>; |
| 108 | status = "okay"; | 213 | status = "okay"; |
| 109 | }; | 214 | }; |
| 110 | 215 | ||
| @@ -115,13 +220,13 @@ | |||
| 115 | 220 | ||
| 116 | &uart1 { | 221 | &uart1 { |
| 117 | pinctrl-names = "default"; | 222 | pinctrl-names = "default"; |
| 118 | pinctrl-0 = <&pinctrl_uart1_1>; | 223 | pinctrl-0 = <&pinctrl_uart1>; |
| 119 | status = "okay"; | 224 | status = "okay"; |
| 120 | }; | 225 | }; |
| 121 | 226 | ||
| 122 | &uart3 { | 227 | &uart3 { |
| 123 | pinctrl-names = "default"; | 228 | pinctrl-names = "default"; |
| 124 | pinctrl-0 = <&pinctrl_uart3_2>; | 229 | pinctrl-0 = <&pinctrl_uart3>; |
| 125 | fsl,uart-has-rtscts; | 230 | fsl,uart-has-rtscts; |
| 126 | status = "okay"; | 231 | status = "okay"; |
| 127 | }; | 232 | }; |
| @@ -132,7 +237,7 @@ | |||
| 132 | 237 | ||
| 133 | &usbotg { | 238 | &usbotg { |
| 134 | pinctrl-names = "default"; | 239 | pinctrl-names = "default"; |
| 135 | pinctrl-0 = <&pinctrl_usbotg_1>; | 240 | pinctrl-0 = <&pinctrl_usbotg>; |
| 136 | disable-over-current; | 241 | disable-over-current; |
| 137 | dr_mode = "peripheral"; | 242 | dr_mode = "peripheral"; |
| 138 | status = "okay"; | 243 | status = "okay"; |
| @@ -140,21 +245,21 @@ | |||
| 140 | 245 | ||
| 141 | &usdhc1 { | 246 | &usdhc1 { |
| 142 | pinctrl-names = "default"; | 247 | pinctrl-names = "default"; |
| 143 | pinctrl-0 = <&pinctrl_usdhc1_2>; | 248 | pinctrl-0 = <&pinctrl_usdhc1>; |
| 144 | cd-gpios = <&gpio1 2 0>; | 249 | cd-gpios = <&gpio1 2 0>; |
| 145 | status = "okay"; | 250 | status = "okay"; |
| 146 | }; | 251 | }; |
| 147 | 252 | ||
| 148 | &usdhc2 { | 253 | &usdhc2 { |
| 149 | pinctrl-names = "default"; | 254 | pinctrl-names = "default"; |
| 150 | pinctrl-0 = <&pinctrl_usdhc2_2>; | 255 | pinctrl-0 = <&pinctrl_usdhc2>; |
| 151 | non-removable; | 256 | non-removable; |
| 152 | status = "okay"; | 257 | status = "okay"; |
| 153 | }; | 258 | }; |
| 154 | 259 | ||
| 155 | &usdhc3 { | 260 | &usdhc3 { |
| 156 | pinctrl-names = "default"; | 261 | pinctrl-names = "default"; |
| 157 | pinctrl-0 = <&pinctrl_usdhc3_2>; | 262 | pinctrl-0 = <&pinctrl_usdhc3>; |
| 158 | cd-gpios = <&gpio3 9 0>; | 263 | cd-gpios = <&gpio3 9 0>; |
| 159 | status = "okay"; | 264 | status = "okay"; |
| 160 | }; | 265 | }; |
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index fb28b2ecb1db..947e463a2b2f 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi | |||
| @@ -14,6 +14,8 @@ | |||
| 14 | 14 | ||
| 15 | / { | 15 | / { |
| 16 | aliases { | 16 | aliases { |
| 17 | can0 = &can1; | ||
| 18 | can1 = &can2; | ||
| 17 | gpio0 = &gpio1; | 19 | gpio0 = &gpio1; |
| 18 | gpio1 = &gpio2; | 20 | gpio1 = &gpio2; |
| 19 | gpio2 = &gpio3; | 21 | gpio2 = &gpio3; |
| @@ -24,6 +26,10 @@ | |||
| 24 | i2c0 = &i2c1; | 26 | i2c0 = &i2c1; |
| 25 | i2c1 = &i2c2; | 27 | i2c1 = &i2c2; |
| 26 | i2c2 = &i2c3; | 28 | i2c2 = &i2c3; |
| 29 | mmc0 = &usdhc1; | ||
| 30 | mmc1 = &usdhc2; | ||
| 31 | mmc2 = &usdhc3; | ||
| 32 | mmc3 = &usdhc4; | ||
| 27 | serial0 = &uart1; | 33 | serial0 = &uart1; |
| 28 | serial1 = &uart2; | 34 | serial1 = &uart2; |
| 29 | serial2 = &uart3; | 35 | serial2 = &uart3; |
| @@ -33,6 +39,8 @@ | |||
| 33 | spi1 = &ecspi2; | 39 | spi1 = &ecspi2; |
| 34 | spi2 = &ecspi3; | 40 | spi2 = &ecspi3; |
| 35 | spi3 = &ecspi4; | 41 | spi3 = &ecspi4; |
| 42 | usbphy0 = &usbphy1; | ||
| 43 | usbphy1 = &usbphy2; | ||
| 36 | }; | 44 | }; |
| 37 | 45 | ||
| 38 | intc: interrupt-controller@00a01000 { | 46 | intc: interrupt-controller@00a01000 { |
| @@ -75,7 +83,10 @@ | |||
| 75 | dma_apbh: dma-apbh@00110000 { | 83 | dma_apbh: dma-apbh@00110000 { |
| 76 | compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; | 84 | compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; |
| 77 | reg = <0x00110000 0x2000>; | 85 | reg = <0x00110000 0x2000>; |
| 78 | interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>; | 86 | interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, |
| 87 | <0 13 IRQ_TYPE_LEVEL_HIGH>, | ||
| 88 | <0 13 IRQ_TYPE_LEVEL_HIGH>, | ||
| 89 | <0 13 IRQ_TYPE_LEVEL_HIGH>; | ||
| 79 | interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; | 90 | interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; |
| 80 | #dma-cells = <1>; | 91 | #dma-cells = <1>; |
| 81 | dma-channels = <4>; | 92 | dma-channels = <4>; |
| @@ -88,7 +99,7 @@ | |||
| 88 | #size-cells = <1>; | 99 | #size-cells = <1>; |
| 89 | reg = <0x00112000 0x2000>, <0x00114000 0x2000>; | 100 | reg = <0x00112000 0x2000>, <0x00114000 0x2000>; |
| 90 | reg-names = "gpmi-nand", "bch"; | 101 | reg-names = "gpmi-nand", "bch"; |
| 91 | interrupts = <0 15 0x04>; | 102 | interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; |
| 92 | interrupt-names = "bch"; | 103 | interrupt-names = "bch"; |
| 93 | clocks = <&clks 152>, <&clks 153>, <&clks 151>, | 104 | clocks = <&clks 152>, <&clks 153>, <&clks 151>, |
| 94 | <&clks 150>, <&clks 149>; | 105 | <&clks 150>, <&clks 149>; |
| @@ -109,7 +120,7 @@ | |||
| 109 | L2: l2-cache@00a02000 { | 120 | L2: l2-cache@00a02000 { |
| 110 | compatible = "arm,pl310-cache"; | 121 | compatible = "arm,pl310-cache"; |
| 111 | reg = <0x00a02000 0x1000>; | 122 | reg = <0x00a02000 0x1000>; |
| 112 | interrupts = <0 92 0x04>; | 123 | interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; |
| 113 | cache-unified; | 124 | cache-unified; |
| 114 | cache-level = <2>; | 125 | cache-level = <2>; |
| 115 | arm,tag-latency = <4 2 3>; | 126 | arm,tag-latency = <4 2 3>; |
| @@ -126,7 +137,7 @@ | |||
| 126 | 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ | 137 | 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ |
| 127 | 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ | 138 | 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ |
| 128 | num-lanes = <1>; | 139 | num-lanes = <1>; |
| 129 | interrupts = <0 123 0x04>; | 140 | interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>; |
| 130 | clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>; | 141 | clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>; |
| 131 | clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi"; | 142 | clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi"; |
| 132 | status = "disabled"; | 143 | status = "disabled"; |
| @@ -134,7 +145,7 @@ | |||
| 134 | 145 | ||
| 135 | pmu { | 146 | pmu { |
| 136 | compatible = "arm,cortex-a9-pmu"; | 147 | compatible = "arm,cortex-a9-pmu"; |
| 137 | interrupts = <0 94 0x04>; | 148 | interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; |
| 138 | }; | 149 | }; |
| 139 | 150 | ||
| 140 | aips-bus@02000000 { /* AIPS1 */ | 151 | aips-bus@02000000 { /* AIPS1 */ |
| @@ -154,7 +165,7 @@ | |||
| 154 | spdif: spdif@02004000 { | 165 | spdif: spdif@02004000 { |
| 155 | compatible = "fsl,imx35-spdif"; | 166 | compatible = "fsl,imx35-spdif"; |
| 156 | reg = <0x02004000 0x4000>; | 167 | reg = <0x02004000 0x4000>; |
| 157 | interrupts = <0 52 0x04>; | 168 | interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; |
| 158 | dmas = <&sdma 14 18 0>, | 169 | dmas = <&sdma 14 18 0>, |
| 159 | <&sdma 15 18 0>; | 170 | <&sdma 15 18 0>; |
| 160 | dma-names = "rx", "tx"; | 171 | dma-names = "rx", "tx"; |
| @@ -176,9 +187,11 @@ | |||
| 176 | #size-cells = <0>; | 187 | #size-cells = <0>; |
| 177 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | 188 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| 178 | reg = <0x02008000 0x4000>; | 189 | reg = <0x02008000 0x4000>; |
| 179 | interrupts = <0 31 0x04>; | 190 | interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; |
| 180 | clocks = <&clks 112>, <&clks 112>; | 191 | clocks = <&clks 112>, <&clks 112>; |
| 181 | clock-names = "ipg", "per"; | 192 | clock-names = "ipg", "per"; |
| 193 | dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; | ||
| 194 | dma-names = "rx", "tx"; | ||
| 182 | status = "disabled"; | 195 | status = "disabled"; |
| 183 | }; | 196 | }; |
| 184 | 197 | ||
| @@ -187,9 +200,11 @@ | |||
| 187 | #size-cells = <0>; | 200 | #size-cells = <0>; |
| 188 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | 201 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| 189 | reg = <0x0200c000 0x4000>; | 202 | reg = <0x0200c000 0x4000>; |
| 190 | interrupts = <0 32 0x04>; | 203 | interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; |
| 191 | clocks = <&clks 113>, <&clks 113>; | 204 | clocks = <&clks 113>, <&clks 113>; |
| 192 | clock-names = "ipg", "per"; | 205 | clock-names = "ipg", "per"; |
| 206 | dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; | ||
| 207 | dma-names = "rx", "tx"; | ||
| 193 | status = "disabled"; | 208 | status = "disabled"; |
| 194 | }; | 209 | }; |
| 195 | 210 | ||
| @@ -198,9 +213,11 @@ | |||
| 198 | #size-cells = <0>; | 213 | #size-cells = <0>; |
| 199 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | 214 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| 200 | reg = <0x02010000 0x4000>; | 215 | reg = <0x02010000 0x4000>; |
| 201 | interrupts = <0 33 0x04>; | 216 | interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; |
| 202 | clocks = <&clks 114>, <&clks 114>; | 217 | clocks = <&clks 114>, <&clks 114>; |
| 203 | clock-names = "ipg", "per"; | 218 | clock-names = "ipg", "per"; |
| 219 | dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; | ||
| 220 | dma-names = "rx", "tx"; | ||
| 204 | status = "disabled"; | 221 | status = "disabled"; |
| 205 | }; | 222 | }; |
| 206 | 223 | ||
| @@ -209,16 +226,18 @@ | |||
| 209 | #size-cells = <0>; | 226 | #size-cells = <0>; |
| 210 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | 227 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| 211 | reg = <0x02014000 0x4000>; | 228 | reg = <0x02014000 0x4000>; |
| 212 | interrupts = <0 34 0x04>; | 229 | interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; |
| 213 | clocks = <&clks 115>, <&clks 115>; | 230 | clocks = <&clks 115>, <&clks 115>; |
| 214 | clock-names = "ipg", "per"; | 231 | clock-names = "ipg", "per"; |
| 232 | dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; | ||
| 233 | dma-names = "rx", "tx"; | ||
| 215 | status = "disabled"; | 234 | status = "disabled"; |
| 216 | }; | 235 | }; |
| 217 | 236 | ||
| 218 | uart1: serial@02020000 { | 237 | uart1: serial@02020000 { |
| 219 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; | 238 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 220 | reg = <0x02020000 0x4000>; | 239 | reg = <0x02020000 0x4000>; |
| 221 | interrupts = <0 26 0x04>; | 240 | interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; |
| 222 | clocks = <&clks 160>, <&clks 161>; | 241 | clocks = <&clks 160>, <&clks 161>; |
| 223 | clock-names = "ipg", "per"; | 242 | clock-names = "ipg", "per"; |
| 224 | dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; | 243 | dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; |
| @@ -228,13 +247,15 @@ | |||
| 228 | 247 | ||
| 229 | esai: esai@02024000 { | 248 | esai: esai@02024000 { |
| 230 | reg = <0x02024000 0x4000>; | 249 | reg = <0x02024000 0x4000>; |
| 231 | interrupts = <0 51 0x04>; | 250 | interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; |
| 232 | }; | 251 | }; |
| 233 | 252 | ||
| 234 | ssi1: ssi@02028000 { | 253 | ssi1: ssi@02028000 { |
| 235 | compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; | 254 | compatible = "fsl,imx6q-ssi", |
| 255 | "fsl,imx51-ssi", | ||
| 256 | "fsl,imx21-ssi"; | ||
| 236 | reg = <0x02028000 0x4000>; | 257 | reg = <0x02028000 0x4000>; |
| 237 | interrupts = <0 46 0x04>; | 258 | interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; |
| 238 | clocks = <&clks 178>; | 259 | clocks = <&clks 178>; |
| 239 | dmas = <&sdma 37 1 0>, | 260 | dmas = <&sdma 37 1 0>, |
| 240 | <&sdma 38 1 0>; | 261 | <&sdma 38 1 0>; |
| @@ -245,9 +266,11 @@ | |||
| 245 | }; | 266 | }; |
| 246 | 267 | ||
| 247 | ssi2: ssi@0202c000 { | 268 | ssi2: ssi@0202c000 { |
| 248 | compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; | 269 | compatible = "fsl,imx6q-ssi", |
| 270 | "fsl,imx51-ssi", | ||
| 271 | "fsl,imx21-ssi"; | ||
| 249 | reg = <0x0202c000 0x4000>; | 272 | reg = <0x0202c000 0x4000>; |
| 250 | interrupts = <0 47 0x04>; | 273 | interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; |
| 251 | clocks = <&clks 179>; | 274 | clocks = <&clks 179>; |
| 252 | dmas = <&sdma 41 1 0>, | 275 | dmas = <&sdma 41 1 0>, |
| 253 | <&sdma 42 1 0>; | 276 | <&sdma 42 1 0>; |
| @@ -258,9 +281,11 @@ | |||
| 258 | }; | 281 | }; |
| 259 | 282 | ||
| 260 | ssi3: ssi@02030000 { | 283 | ssi3: ssi@02030000 { |
| 261 | compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; | 284 | compatible = "fsl,imx6q-ssi", |
| 285 | "fsl,imx51-ssi", | ||
| 286 | "fsl,imx21-ssi"; | ||
| 262 | reg = <0x02030000 0x4000>; | 287 | reg = <0x02030000 0x4000>; |
| 263 | interrupts = <0 48 0x04>; | 288 | interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; |
| 264 | clocks = <&clks 180>; | 289 | clocks = <&clks 180>; |
| 265 | dmas = <&sdma 45 1 0>, | 290 | dmas = <&sdma 45 1 0>, |
| 266 | <&sdma 46 1 0>; | 291 | <&sdma 46 1 0>; |
| @@ -272,7 +297,7 @@ | |||
| 272 | 297 | ||
| 273 | asrc: asrc@02034000 { | 298 | asrc: asrc@02034000 { |
| 274 | reg = <0x02034000 0x4000>; | 299 | reg = <0x02034000 0x4000>; |
| 275 | interrupts = <0 50 0x04>; | 300 | interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; |
| 276 | }; | 301 | }; |
| 277 | 302 | ||
| 278 | spba@0203c000 { | 303 | spba@0203c000 { |
| @@ -282,7 +307,8 @@ | |||
| 282 | 307 | ||
| 283 | vpu: vpu@02040000 { | 308 | vpu: vpu@02040000 { |
| 284 | reg = <0x02040000 0x3c000>; | 309 | reg = <0x02040000 0x3c000>; |
| 285 | interrupts = <0 3 0x04 0 12 0x04>; | 310 | interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>, |
| 311 | <0 12 IRQ_TYPE_LEVEL_HIGH>; | ||
| 286 | }; | 312 | }; |
| 287 | 313 | ||
| 288 | aipstz@0207c000 { /* AIPSTZ1 */ | 314 | aipstz@0207c000 { /* AIPSTZ1 */ |
| @@ -293,7 +319,7 @@ | |||
| 293 | #pwm-cells = <2>; | 319 | #pwm-cells = <2>; |
| 294 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | 320 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; |
| 295 | reg = <0x02080000 0x4000>; | 321 | reg = <0x02080000 0x4000>; |
| 296 | interrupts = <0 83 0x04>; | 322 | interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; |
| 297 | clocks = <&clks 62>, <&clks 145>; | 323 | clocks = <&clks 62>, <&clks 145>; |
| 298 | clock-names = "ipg", "per"; | 324 | clock-names = "ipg", "per"; |
| 299 | }; | 325 | }; |
| @@ -302,7 +328,7 @@ | |||
| 302 | #pwm-cells = <2>; | 328 | #pwm-cells = <2>; |
| 303 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | 329 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; |
| 304 | reg = <0x02084000 0x4000>; | 330 | reg = <0x02084000 0x4000>; |
| 305 | interrupts = <0 84 0x04>; | 331 | interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; |
| 306 | clocks = <&clks 62>, <&clks 146>; | 332 | clocks = <&clks 62>, <&clks 146>; |
| 307 | clock-names = "ipg", "per"; | 333 | clock-names = "ipg", "per"; |
| 308 | }; | 334 | }; |
| @@ -311,7 +337,7 @@ | |||
| 311 | #pwm-cells = <2>; | 337 | #pwm-cells = <2>; |
| 312 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | 338 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; |
| 313 | reg = <0x02088000 0x4000>; | 339 | reg = <0x02088000 0x4000>; |
| 314 | interrupts = <0 85 0x04>; | 340 | interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; |
| 315 | clocks = <&clks 62>, <&clks 147>; | 341 | clocks = <&clks 62>, <&clks 147>; |
| 316 | clock-names = "ipg", "per"; | 342 | clock-names = "ipg", "per"; |
| 317 | }; | 343 | }; |
| @@ -320,7 +346,7 @@ | |||
| 320 | #pwm-cells = <2>; | 346 | #pwm-cells = <2>; |
| 321 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | 347 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; |
| 322 | reg = <0x0208c000 0x4000>; | 348 | reg = <0x0208c000 0x4000>; |
| 323 | interrupts = <0 86 0x04>; | 349 | interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; |
| 324 | clocks = <&clks 62>, <&clks 148>; | 350 | clocks = <&clks 62>, <&clks 148>; |
| 325 | clock-names = "ipg", "per"; | 351 | clock-names = "ipg", "per"; |
| 326 | }; | 352 | }; |
| @@ -328,23 +354,25 @@ | |||
| 328 | can1: flexcan@02090000 { | 354 | can1: flexcan@02090000 { |
| 329 | compatible = "fsl,imx6q-flexcan"; | 355 | compatible = "fsl,imx6q-flexcan"; |
| 330 | reg = <0x02090000 0x4000>; | 356 | reg = <0x02090000 0x4000>; |
| 331 | interrupts = <0 110 0x04>; | 357 | interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; |
| 332 | clocks = <&clks 108>, <&clks 109>; | 358 | clocks = <&clks 108>, <&clks 109>; |
| 333 | clock-names = "ipg", "per"; | 359 | clock-names = "ipg", "per"; |
| 360 | status = "disabled"; | ||
| 334 | }; | 361 | }; |
| 335 | 362 | ||
| 336 | can2: flexcan@02094000 { | 363 | can2: flexcan@02094000 { |
| 337 | compatible = "fsl,imx6q-flexcan"; | 364 | compatible = "fsl,imx6q-flexcan"; |
| 338 | reg = <0x02094000 0x4000>; | 365 | reg = <0x02094000 0x4000>; |
| 339 | interrupts = <0 111 0x04>; | 366 | interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; |
| 340 | clocks = <&clks 110>, <&clks 111>; | 367 | clocks = <&clks 110>, <&clks 111>; |
| 341 | clock-names = "ipg", "per"; | 368 | clock-names = "ipg", "per"; |
| 369 | status = "disabled"; | ||
| 342 | }; | 370 | }; |
| 343 | 371 | ||
| 344 | gpt: gpt@02098000 { | 372 | gpt: gpt@02098000 { |
| 345 | compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; | 373 | compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; |
| 346 | reg = <0x02098000 0x4000>; | 374 | reg = <0x02098000 0x4000>; |
| 347 | interrupts = <0 55 0x04>; | 375 | interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; |
| 348 | clocks = <&clks 119>, <&clks 120>; | 376 | clocks = <&clks 119>, <&clks 120>; |
| 349 | clock-names = "ipg", "per"; | 377 | clock-names = "ipg", "per"; |
| 350 | }; | 378 | }; |
| @@ -352,7 +380,8 @@ | |||
| 352 | gpio1: gpio@0209c000 { | 380 | gpio1: gpio@0209c000 { |
| 353 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; | 381 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| 354 | reg = <0x0209c000 0x4000>; | 382 | reg = <0x0209c000 0x4000>; |
| 355 | interrupts = <0 66 0x04 0 67 0x04>; | 383 | interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, |
| 384 | <0 67 IRQ_TYPE_LEVEL_HIGH>; | ||
| 356 | gpio-controller; | 385 | gpio-controller; |
| 357 | #gpio-cells = <2>; | 386 | #gpio-cells = <2>; |
| 358 | interrupt-controller; | 387 | interrupt-controller; |
| @@ -362,7 +391,8 @@ | |||
| 362 | gpio2: gpio@020a0000 { | 391 | gpio2: gpio@020a0000 { |
| 363 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; | 392 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| 364 | reg = <0x020a0000 0x4000>; | 393 | reg = <0x020a0000 0x4000>; |
| 365 | interrupts = <0 68 0x04 0 69 0x04>; | 394 | interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, |
| 395 | <0 69 IRQ_TYPE_LEVEL_HIGH>; | ||
| 366 | gpio-controller; | 396 | gpio-controller; |
| 367 | #gpio-cells = <2>; | 397 | #gpio-cells = <2>; |
| 368 | interrupt-controller; | 398 | interrupt-controller; |
| @@ -372,7 +402,8 @@ | |||
| 372 | gpio3: gpio@020a4000 { | 402 | gpio3: gpio@020a4000 { |
| 373 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; | 403 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| 374 | reg = <0x020a4000 0x4000>; | 404 | reg = <0x020a4000 0x4000>; |
| 375 | interrupts = <0 70 0x04 0 71 0x04>; | 405 | interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, |
| 406 | <0 71 IRQ_TYPE_LEVEL_HIGH>; | ||
| 376 | gpio-controller; | 407 | gpio-controller; |
| 377 | #gpio-cells = <2>; | 408 | #gpio-cells = <2>; |
| 378 | interrupt-controller; | 409 | interrupt-controller; |
| @@ -382,7 +413,8 @@ | |||
| 382 | gpio4: gpio@020a8000 { | 413 | gpio4: gpio@020a8000 { |
| 383 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; | 414 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| 384 | reg = <0x020a8000 0x4000>; | 415 | reg = <0x020a8000 0x4000>; |
| 385 | interrupts = <0 72 0x04 0 73 0x04>; | 416 | interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, |
| 417 | <0 73 IRQ_TYPE_LEVEL_HIGH>; | ||
| 386 | gpio-controller; | 418 | gpio-controller; |
| 387 | #gpio-cells = <2>; | 419 | #gpio-cells = <2>; |
| 388 | interrupt-controller; | 420 | interrupt-controller; |
| @@ -392,7 +424,8 @@ | |||
| 392 | gpio5: gpio@020ac000 { | 424 | gpio5: gpio@020ac000 { |
| 393 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; | 425 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| 394 | reg = <0x020ac000 0x4000>; | 426 | reg = <0x020ac000 0x4000>; |
| 395 | interrupts = <0 74 0x04 0 75 0x04>; | 427 | interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, |
| 428 | <0 75 IRQ_TYPE_LEVEL_HIGH>; | ||
| 396 | gpio-controller; | 429 | gpio-controller; |
| 397 | #gpio-cells = <2>; | 430 | #gpio-cells = <2>; |
| 398 | interrupt-controller; | 431 | interrupt-controller; |
| @@ -402,7 +435,8 @@ | |||
| 402 | gpio6: gpio@020b0000 { | 435 | gpio6: gpio@020b0000 { |
| 403 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; | 436 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| 404 | reg = <0x020b0000 0x4000>; | 437 | reg = <0x020b0000 0x4000>; |
| 405 | interrupts = <0 76 0x04 0 77 0x04>; | 438 | interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>, |
| 439 | <0 77 IRQ_TYPE_LEVEL_HIGH>; | ||
| 406 | gpio-controller; | 440 | gpio-controller; |
| 407 | #gpio-cells = <2>; | 441 | #gpio-cells = <2>; |
| 408 | interrupt-controller; | 442 | interrupt-controller; |
| @@ -412,7 +446,8 @@ | |||
| 412 | gpio7: gpio@020b4000 { | 446 | gpio7: gpio@020b4000 { |
| 413 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; | 447 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| 414 | reg = <0x020b4000 0x4000>; | 448 | reg = <0x020b4000 0x4000>; |
| 415 | interrupts = <0 78 0x04 0 79 0x04>; | 449 | interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>, |
| 450 | <0 79 IRQ_TYPE_LEVEL_HIGH>; | ||
| 416 | gpio-controller; | 451 | gpio-controller; |
| 417 | #gpio-cells = <2>; | 452 | #gpio-cells = <2>; |
| 418 | interrupt-controller; | 453 | interrupt-controller; |
| @@ -421,20 +456,20 @@ | |||
| 421 | 456 | ||
| 422 | kpp: kpp@020b8000 { | 457 | kpp: kpp@020b8000 { |
| 423 | reg = <0x020b8000 0x4000>; | 458 | reg = <0x020b8000 0x4000>; |
| 424 | interrupts = <0 82 0x04>; | 459 | interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; |
| 425 | }; | 460 | }; |
| 426 | 461 | ||
| 427 | wdog1: wdog@020bc000 { | 462 | wdog1: wdog@020bc000 { |
| 428 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; | 463 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
| 429 | reg = <0x020bc000 0x4000>; | 464 | reg = <0x020bc000 0x4000>; |
| 430 | interrupts = <0 80 0x04>; | 465 | interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; |
| 431 | clocks = <&clks 0>; | 466 | clocks = <&clks 0>; |
| 432 | }; | 467 | }; |
| 433 | 468 | ||
| 434 | wdog2: wdog@020c0000 { | 469 | wdog2: wdog@020c0000 { |
| 435 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; | 470 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
| 436 | reg = <0x020c0000 0x4000>; | 471 | reg = <0x020c0000 0x4000>; |
| 437 | interrupts = <0 81 0x04>; | 472 | interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; |
| 438 | clocks = <&clks 0>; | 473 | clocks = <&clks 0>; |
| 439 | status = "disabled"; | 474 | status = "disabled"; |
| 440 | }; | 475 | }; |
| @@ -442,14 +477,17 @@ | |||
| 442 | clks: ccm@020c4000 { | 477 | clks: ccm@020c4000 { |
| 443 | compatible = "fsl,imx6q-ccm"; | 478 | compatible = "fsl,imx6q-ccm"; |
| 444 | reg = <0x020c4000 0x4000>; | 479 | reg = <0x020c4000 0x4000>; |
| 445 | interrupts = <0 87 0x04 0 88 0x04>; | 480 | interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, |
| 481 | <0 88 IRQ_TYPE_LEVEL_HIGH>; | ||
| 446 | #clock-cells = <1>; | 482 | #clock-cells = <1>; |
| 447 | }; | 483 | }; |
| 448 | 484 | ||
| 449 | anatop: anatop@020c8000 { | 485 | anatop: anatop@020c8000 { |
| 450 | compatible = "fsl,imx6q-anatop", "syscon", "simple-bus"; | 486 | compatible = "fsl,imx6q-anatop", "syscon", "simple-bus"; |
| 451 | reg = <0x020c8000 0x1000>; | 487 | reg = <0x020c8000 0x1000>; |
| 452 | interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; | 488 | interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, |
| 489 | <0 54 IRQ_TYPE_LEVEL_HIGH>, | ||
| 490 | <0 127 IRQ_TYPE_LEVEL_HIGH>; | ||
| 453 | 491 | ||
| 454 | regulator-1p1@110 { | 492 | regulator-1p1@110 { |
| 455 | compatible = "fsl,anatop-regulator"; | 493 | compatible = "fsl,anatop-regulator"; |
| @@ -495,7 +533,7 @@ | |||
| 495 | 533 | ||
| 496 | reg_arm: regulator-vddcore@140 { | 534 | reg_arm: regulator-vddcore@140 { |
| 497 | compatible = "fsl,anatop-regulator"; | 535 | compatible = "fsl,anatop-regulator"; |
| 498 | regulator-name = "cpu"; | 536 | regulator-name = "vddarm"; |
| 499 | regulator-min-microvolt = <725000>; | 537 | regulator-min-microvolt = <725000>; |
| 500 | regulator-max-microvolt = <1450000>; | 538 | regulator-max-microvolt = <1450000>; |
| 501 | regulator-always-on; | 539 | regulator-always-on; |
| @@ -547,23 +585,26 @@ | |||
| 547 | 585 | ||
| 548 | tempmon: tempmon { | 586 | tempmon: tempmon { |
| 549 | compatible = "fsl,imx6q-tempmon"; | 587 | compatible = "fsl,imx6q-tempmon"; |
| 550 | interrupts = <0 49 0x04>; | 588 | interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; |
| 551 | fsl,tempmon = <&anatop>; | 589 | fsl,tempmon = <&anatop>; |
| 552 | fsl,tempmon-data = <&ocotp>; | 590 | fsl,tempmon-data = <&ocotp>; |
| 591 | clocks = <&clks 172>; | ||
| 553 | }; | 592 | }; |
| 554 | 593 | ||
| 555 | usbphy1: usbphy@020c9000 { | 594 | usbphy1: usbphy@020c9000 { |
| 556 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; | 595 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; |
| 557 | reg = <0x020c9000 0x1000>; | 596 | reg = <0x020c9000 0x1000>; |
| 558 | interrupts = <0 44 0x04>; | 597 | interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; |
| 559 | clocks = <&clks 182>; | 598 | clocks = <&clks 182>; |
| 599 | fsl,anatop = <&anatop>; | ||
| 560 | }; | 600 | }; |
| 561 | 601 | ||
| 562 | usbphy2: usbphy@020ca000 { | 602 | usbphy2: usbphy@020ca000 { |
| 563 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; | 603 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; |
| 564 | reg = <0x020ca000 0x1000>; | 604 | reg = <0x020ca000 0x1000>; |
| 565 | interrupts = <0 45 0x04>; | 605 | interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; |
| 566 | clocks = <&clks 183>; | 606 | clocks = <&clks 183>; |
| 607 | fsl,anatop = <&anatop>; | ||
| 567 | }; | 608 | }; |
| 568 | 609 | ||
| 569 | snvs@020cc000 { | 610 | snvs@020cc000 { |
| @@ -575,31 +616,34 @@ | |||
| 575 | snvs-rtc-lp@34 { | 616 | snvs-rtc-lp@34 { |
| 576 | compatible = "fsl,sec-v4.0-mon-rtc-lp"; | 617 | compatible = "fsl,sec-v4.0-mon-rtc-lp"; |
| 577 | reg = <0x34 0x58>; | 618 | reg = <0x34 0x58>; |
| 578 | interrupts = <0 19 0x04 0 20 0x04>; | 619 | interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, |
| 620 | <0 20 IRQ_TYPE_LEVEL_HIGH>; | ||
| 579 | }; | 621 | }; |
| 580 | }; | 622 | }; |
| 581 | 623 | ||
| 582 | epit1: epit@020d0000 { /* EPIT1 */ | 624 | epit1: epit@020d0000 { /* EPIT1 */ |
| 583 | reg = <0x020d0000 0x4000>; | 625 | reg = <0x020d0000 0x4000>; |
| 584 | interrupts = <0 56 0x04>; | 626 | interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; |
| 585 | }; | 627 | }; |
| 586 | 628 | ||
| 587 | epit2: epit@020d4000 { /* EPIT2 */ | 629 | epit2: epit@020d4000 { /* EPIT2 */ |
| 588 | reg = <0x020d4000 0x4000>; | 630 | reg = <0x020d4000 0x4000>; |
| 589 | interrupts = <0 57 0x04>; | 631 | interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; |
| 590 | }; | 632 | }; |
| 591 | 633 | ||
| 592 | src: src@020d8000 { | 634 | src: src@020d8000 { |
| 593 | compatible = "fsl,imx6q-src", "fsl,imx51-src"; | 635 | compatible = "fsl,imx6q-src", "fsl,imx51-src"; |
| 594 | reg = <0x020d8000 0x4000>; | 636 | reg = <0x020d8000 0x4000>; |
| 595 | interrupts = <0 91 0x04 0 96 0x04>; | 637 | interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, |
| 638 | <0 96 IRQ_TYPE_LEVEL_HIGH>; | ||
| 596 | #reset-cells = <1>; | 639 | #reset-cells = <1>; |
| 597 | }; | 640 | }; |
| 598 | 641 | ||
| 599 | gpc: gpc@020dc000 { | 642 | gpc: gpc@020dc000 { |
| 600 | compatible = "fsl,imx6q-gpc"; | 643 | compatible = "fsl,imx6q-gpc"; |
| 601 | reg = <0x020dc000 0x4000>; | 644 | reg = <0x020dc000 0x4000>; |
| 602 | interrupts = <0 89 0x04 0 90 0x04>; | 645 | interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, |
| 646 | <0 90 IRQ_TYPE_LEVEL_HIGH>; | ||
| 603 | }; | 647 | }; |
| 604 | 648 | ||
| 605 | gpr: iomuxc-gpr@020e0000 { | 649 | gpr: iomuxc-gpr@020e0000 { |
| @@ -610,744 +654,6 @@ | |||
| 610 | iomuxc: iomuxc@020e0000 { | 654 | iomuxc: iomuxc@020e0000 { |
| 611 | compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; | 655 | compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; |
| 612 | reg = <0x020e0000 0x4000>; | 656 | reg = <0x020e0000 0x4000>; |
| 613 | |||
| 614 | audmux { | ||
| 615 | pinctrl_audmux_1: audmux-1 { | ||
| 616 | fsl,pins = < | ||
| 617 | MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x80000000 | ||
| 618 | MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x80000000 | ||
| 619 | MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x80000000 | ||
| 620 | MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000 | ||
| 621 | >; | ||
| 622 | }; | ||
| 623 | |||
| 624 | pinctrl_audmux_2: audmux-2 { | ||
| 625 | fsl,pins = < | ||
| 626 | MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000 | ||
| 627 | MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000 | ||
| 628 | MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000 | ||
| 629 | MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000 | ||
| 630 | >; | ||
| 631 | }; | ||
| 632 | |||
| 633 | pinctrl_audmux_3: audmux-3 { | ||
| 634 | fsl,pins = < | ||
| 635 | MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x80000000 | ||
| 636 | MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000 | ||
| 637 | MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x80000000 | ||
| 638 | >; | ||
| 639 | }; | ||
| 640 | }; | ||
| 641 | |||
| 642 | ecspi1 { | ||
| 643 | pinctrl_ecspi1_1: ecspi1grp-1 { | ||
| 644 | fsl,pins = < | ||
| 645 | MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 | ||
| 646 | MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 | ||
| 647 | MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 | ||
| 648 | >; | ||
| 649 | }; | ||
| 650 | |||
| 651 | pinctrl_ecspi1_2: ecspi1grp-2 { | ||
| 652 | fsl,pins = < | ||
| 653 | MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 | ||
| 654 | MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 | ||
| 655 | MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 | ||
| 656 | >; | ||
| 657 | }; | ||
| 658 | }; | ||
| 659 | |||
| 660 | ecspi3 { | ||
| 661 | pinctrl_ecspi3_1: ecspi3grp-1 { | ||
| 662 | fsl,pins = < | ||
| 663 | MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 | ||
| 664 | MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 | ||
| 665 | MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 | ||
| 666 | >; | ||
| 667 | }; | ||
| 668 | }; | ||
| 669 | |||
| 670 | enet { | ||
| 671 | pinctrl_enet_1: enetgrp-1 { | ||
| 672 | fsl,pins = < | ||
| 673 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | ||
| 674 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | ||
| 675 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 676 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 677 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 678 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 679 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 680 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 681 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 682 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 683 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 684 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 685 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 686 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 687 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 688 | MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 | ||
| 689 | >; | ||
| 690 | }; | ||
| 691 | |||
| 692 | pinctrl_enet_2: enetgrp-2 { | ||
| 693 | fsl,pins = < | ||
| 694 | MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 | ||
| 695 | MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 | ||
| 696 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 697 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 698 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 699 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 700 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 701 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 702 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 703 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 704 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 705 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 706 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 707 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 708 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 709 | >; | ||
| 710 | }; | ||
| 711 | |||
| 712 | pinctrl_enet_3: enetgrp-3 { | ||
| 713 | fsl,pins = < | ||
| 714 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | ||
| 715 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | ||
| 716 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 717 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 718 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 719 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 720 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 721 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 722 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 723 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 724 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 725 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 726 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 727 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 728 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 729 | MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 | ||
| 730 | >; | ||
| 731 | }; | ||
| 732 | }; | ||
| 733 | |||
| 734 | esai { | ||
| 735 | pinctrl_esai_1: esaigrp-1 { | ||
| 736 | fsl,pins = < | ||
| 737 | MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030 | ||
| 738 | MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 | ||
| 739 | MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 | ||
| 740 | MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 | ||
| 741 | MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030 | ||
| 742 | MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 | ||
| 743 | MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 | ||
| 744 | MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030 | ||
| 745 | MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 | ||
| 746 | >; | ||
| 747 | }; | ||
| 748 | |||
| 749 | pinctrl_esai_2: esaigrp-2 { | ||
| 750 | fsl,pins = < | ||
| 751 | MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 | ||
| 752 | MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 | ||
| 753 | MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 | ||
| 754 | MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030 | ||
| 755 | MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 | ||
| 756 | MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 | ||
| 757 | MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030 | ||
| 758 | MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 | ||
| 759 | MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030 | ||
| 760 | MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030 | ||
| 761 | >; | ||
| 762 | }; | ||
| 763 | }; | ||
| 764 | |||
| 765 | flexcan1 { | ||
| 766 | pinctrl_flexcan1_1: flexcan1grp-1 { | ||
| 767 | fsl,pins = < | ||
| 768 | MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 | ||
| 769 | MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 | ||
| 770 | >; | ||
| 771 | }; | ||
| 772 | |||
| 773 | pinctrl_flexcan1_2: flexcan1grp-2 { | ||
| 774 | fsl,pins = < | ||
| 775 | MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000 | ||
| 776 | MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 | ||
| 777 | >; | ||
| 778 | }; | ||
| 779 | }; | ||
| 780 | |||
| 781 | flexcan2 { | ||
| 782 | pinctrl_flexcan2_1: flexcan2grp-1 { | ||
| 783 | fsl,pins = < | ||
| 784 | MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000 | ||
| 785 | MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000 | ||
| 786 | >; | ||
| 787 | }; | ||
| 788 | }; | ||
| 789 | |||
| 790 | gpmi-nand { | ||
| 791 | pinctrl_gpmi_nand_1: gpmi-nand-1 { | ||
| 792 | fsl,pins = < | ||
| 793 | MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 | ||
| 794 | MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 | ||
| 795 | MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 | ||
| 796 | MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 | ||
| 797 | MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 | ||
| 798 | MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 | ||
| 799 | MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 | ||
| 800 | MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 | ||
| 801 | MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 | ||
| 802 | MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 | ||
| 803 | MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 | ||
| 804 | MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 | ||
| 805 | MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 | ||
| 806 | MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 | ||
| 807 | MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 | ||
| 808 | MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 | ||
| 809 | MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 | ||
| 810 | >; | ||
| 811 | }; | ||
| 812 | }; | ||
| 813 | |||
| 814 | hdmi_hdcp { | ||
| 815 | pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 { | ||
| 816 | fsl,pins = < | ||
| 817 | MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 | ||
| 818 | MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 | ||
| 819 | >; | ||
| 820 | }; | ||
| 821 | |||
| 822 | pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 { | ||
| 823 | fsl,pins = < | ||
| 824 | MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 | ||
| 825 | MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1 | ||
| 826 | >; | ||
| 827 | }; | ||
| 828 | |||
| 829 | pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 { | ||
| 830 | fsl,pins = < | ||
| 831 | MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 | ||
| 832 | MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 | ||
| 833 | >; | ||
| 834 | }; | ||
| 835 | }; | ||
| 836 | |||
| 837 | hdmi_cec { | ||
| 838 | pinctrl_hdmi_cec_1: hdmicecgrp-1 { | ||
| 839 | fsl,pins = < | ||
| 840 | MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 | ||
| 841 | >; | ||
| 842 | }; | ||
| 843 | |||
| 844 | pinctrl_hdmi_cec_2: hdmicecgrp-2 { | ||
| 845 | fsl,pins = < | ||
| 846 | MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 | ||
| 847 | >; | ||
| 848 | }; | ||
| 849 | }; | ||
| 850 | |||
| 851 | i2c1 { | ||
| 852 | pinctrl_i2c1_1: i2c1grp-1 { | ||
| 853 | fsl,pins = < | ||
| 854 | MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 | ||
| 855 | MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 | ||
| 856 | >; | ||
| 857 | }; | ||
| 858 | |||
| 859 | pinctrl_i2c1_2: i2c1grp-2 { | ||
| 860 | fsl,pins = < | ||
| 861 | MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 | ||
| 862 | MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 | ||
| 863 | >; | ||
| 864 | }; | ||
| 865 | }; | ||
| 866 | |||
| 867 | i2c2 { | ||
| 868 | pinctrl_i2c2_1: i2c2grp-1 { | ||
| 869 | fsl,pins = < | ||
| 870 | MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 | ||
| 871 | MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 | ||
| 872 | >; | ||
| 873 | }; | ||
| 874 | |||
| 875 | pinctrl_i2c2_2: i2c2grp-2 { | ||
| 876 | fsl,pins = < | ||
| 877 | MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 | ||
| 878 | MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 | ||
| 879 | >; | ||
| 880 | }; | ||
| 881 | |||
| 882 | pinctrl_i2c2_3: i2c2grp-3 { | ||
| 883 | fsl,pins = < | ||
| 884 | MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 | ||
| 885 | MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 | ||
| 886 | >; | ||
| 887 | }; | ||
| 888 | }; | ||
| 889 | |||
| 890 | i2c3 { | ||
| 891 | pinctrl_i2c3_1: i2c3grp-1 { | ||
| 892 | fsl,pins = < | ||
| 893 | MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 | ||
| 894 | MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 | ||
| 895 | >; | ||
| 896 | }; | ||
| 897 | |||
| 898 | pinctrl_i2c3_2: i2c3grp-2 { | ||
| 899 | fsl,pins = < | ||
| 900 | MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 | ||
| 901 | MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 | ||
| 902 | >; | ||
| 903 | }; | ||
| 904 | |||
| 905 | pinctrl_i2c3_3: i2c3grp-3 { | ||
| 906 | fsl,pins = < | ||
| 907 | MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 | ||
| 908 | MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 | ||
| 909 | >; | ||
| 910 | }; | ||
| 911 | |||
| 912 | pinctrl_i2c3_4: i2c3grp-4 { | ||
| 913 | fsl,pins = < | ||
| 914 | MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 | ||
| 915 | MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 | ||
| 916 | >; | ||
| 917 | }; | ||
| 918 | }; | ||
| 919 | |||
| 920 | ipu1 { | ||
| 921 | pinctrl_ipu1_1: ipu1grp-1 { | ||
| 922 | fsl,pins = < | ||
| 923 | MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 | ||
| 924 | MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 | ||
| 925 | MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 | ||
| 926 | MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 | ||
| 927 | MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000 | ||
| 928 | MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 | ||
| 929 | MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 | ||
| 930 | MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 | ||
| 931 | MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 | ||
| 932 | MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 | ||
| 933 | MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 | ||
| 934 | MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 | ||
| 935 | MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 | ||
| 936 | MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 | ||
| 937 | MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 | ||
| 938 | MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 | ||
| 939 | MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 | ||
| 940 | MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 | ||
| 941 | MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 | ||
| 942 | MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 | ||
| 943 | MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 | ||
| 944 | MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 | ||
| 945 | MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 | ||
| 946 | MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 | ||
| 947 | MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 | ||
| 948 | MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 | ||
| 949 | MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 | ||
| 950 | MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 | ||
| 951 | MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 | ||
| 952 | >; | ||
| 953 | }; | ||
| 954 | |||
| 955 | pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */ | ||
| 956 | fsl,pins = < | ||
| 957 | MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 | ||
| 958 | MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 | ||
| 959 | MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 | ||
| 960 | MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 | ||
| 961 | MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 | ||
| 962 | MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 | ||
| 963 | MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 | ||
| 964 | MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 | ||
| 965 | MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000 | ||
| 966 | MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 | ||
| 967 | MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 | ||
| 968 | MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 | ||
| 969 | >; | ||
| 970 | }; | ||
| 971 | |||
| 972 | pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */ | ||
| 973 | fsl,pins = < | ||
| 974 | MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000 | ||
| 975 | MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000 | ||
| 976 | MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000 | ||
| 977 | MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000 | ||
| 978 | MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000 | ||
| 979 | MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000 | ||
| 980 | MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000 | ||
| 981 | MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000 | ||
| 982 | MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 | ||
| 983 | MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 | ||
| 984 | MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 | ||
| 985 | MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 | ||
| 986 | MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 | ||
| 987 | MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 | ||
| 988 | MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 | ||
| 989 | MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 | ||
| 990 | MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 | ||
| 991 | MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 | ||
| 992 | MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 | ||
| 993 | >; | ||
| 994 | }; | ||
| 995 | }; | ||
| 996 | |||
| 997 | mlb { | ||
| 998 | pinctrl_mlb_1: mlbgrp-1 { | ||
| 999 | fsl,pins = < | ||
| 1000 | MX6QDL_PAD_GPIO_3__MLB_CLK 0x71 | ||
| 1001 | MX6QDL_PAD_GPIO_6__MLB_SIG 0x71 | ||
| 1002 | MX6QDL_PAD_GPIO_2__MLB_DATA 0x71 | ||
| 1003 | >; | ||
| 1004 | }; | ||
| 1005 | |||
| 1006 | pinctrl_mlb_2: mlbgrp-2 { | ||
| 1007 | fsl,pins = < | ||
| 1008 | MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71 | ||
| 1009 | MX6QDL_PAD_GPIO_6__MLB_SIG 0x71 | ||
| 1010 | MX6QDL_PAD_GPIO_2__MLB_DATA 0x71 | ||
| 1011 | >; | ||
| 1012 | }; | ||
| 1013 | }; | ||
| 1014 | |||
| 1015 | pwm0 { | ||
| 1016 | pinctrl_pwm0_1: pwm0grp-1 { | ||
| 1017 | fsl,pins = < | ||
| 1018 | MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 | ||
| 1019 | >; | ||
| 1020 | }; | ||
| 1021 | }; | ||
| 1022 | |||
| 1023 | pwm3 { | ||
| 1024 | pinctrl_pwm3_1: pwm3grp-1 { | ||
| 1025 | fsl,pins = < | ||
| 1026 | MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 | ||
| 1027 | >; | ||
| 1028 | }; | ||
| 1029 | }; | ||
| 1030 | |||
| 1031 | spdif { | ||
| 1032 | pinctrl_spdif_1: spdifgrp-1 { | ||
| 1033 | fsl,pins = < | ||
| 1034 | MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0 | ||
| 1035 | >; | ||
| 1036 | }; | ||
| 1037 | |||
| 1038 | pinctrl_spdif_2: spdifgrp-2 { | ||
| 1039 | fsl,pins = < | ||
| 1040 | MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 | ||
| 1041 | MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 | ||
| 1042 | >; | ||
| 1043 | }; | ||
| 1044 | |||
| 1045 | pinctrl_spdif_3: spdifgrp-3 { | ||
| 1046 | fsl,pins = < | ||
| 1047 | MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0 | ||
| 1048 | >; | ||
| 1049 | }; | ||
| 1050 | }; | ||
| 1051 | |||
| 1052 | uart1 { | ||
| 1053 | pinctrl_uart1_1: uart1grp-1 { | ||
| 1054 | fsl,pins = < | ||
| 1055 | MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 | ||
| 1056 | MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 | ||
| 1057 | >; | ||
| 1058 | }; | ||
| 1059 | }; | ||
| 1060 | |||
| 1061 | uart2 { | ||
| 1062 | pinctrl_uart2_1: uart2grp-1 { | ||
| 1063 | fsl,pins = < | ||
| 1064 | MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 | ||
| 1065 | MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 | ||
| 1066 | >; | ||
| 1067 | }; | ||
| 1068 | |||
| 1069 | pinctrl_uart2_2: uart2grp-2 { /* DTE mode */ | ||
| 1070 | fsl,pins = < | ||
| 1071 | MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 | ||
| 1072 | MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 | ||
| 1073 | MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 | ||
| 1074 | MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 | ||
| 1075 | >; | ||
| 1076 | }; | ||
| 1077 | }; | ||
| 1078 | |||
| 1079 | uart3 { | ||
| 1080 | pinctrl_uart3_1: uart3grp-1 { | ||
| 1081 | fsl,pins = < | ||
| 1082 | MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 | ||
| 1083 | MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 | ||
| 1084 | MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 | ||
| 1085 | MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 | ||
| 1086 | >; | ||
| 1087 | }; | ||
| 1088 | |||
| 1089 | pinctrl_uart3_2: uart3grp-2 { | ||
| 1090 | fsl,pins = < | ||
| 1091 | MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 | ||
| 1092 | MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 | ||
| 1093 | MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 | ||
| 1094 | MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 | ||
| 1095 | >; | ||
| 1096 | }; | ||
| 1097 | }; | ||
| 1098 | |||
| 1099 | uart4 { | ||
| 1100 | pinctrl_uart4_1: uart4grp-1 { | ||
| 1101 | fsl,pins = < | ||
| 1102 | MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 | ||
| 1103 | MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 | ||
| 1104 | >; | ||
| 1105 | }; | ||
| 1106 | }; | ||
| 1107 | |||
| 1108 | usbotg { | ||
| 1109 | pinctrl_usbotg_1: usbotggrp-1 { | ||
| 1110 | fsl,pins = < | ||
| 1111 | MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 | ||
| 1112 | >; | ||
| 1113 | }; | ||
| 1114 | |||
| 1115 | pinctrl_usbotg_2: usbotggrp-2 { | ||
| 1116 | fsl,pins = < | ||
| 1117 | MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 | ||
| 1118 | >; | ||
| 1119 | }; | ||
| 1120 | }; | ||
| 1121 | |||
| 1122 | usbh2 { | ||
| 1123 | pinctrl_usbh2_1: usbh2grp-1 { | ||
| 1124 | fsl,pins = < | ||
| 1125 | MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030 | ||
| 1126 | MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030 | ||
| 1127 | >; | ||
| 1128 | }; | ||
| 1129 | |||
| 1130 | pinctrl_usbh2_2: usbh2grp-2 { | ||
| 1131 | fsl,pins = < | ||
| 1132 | MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030 | ||
| 1133 | >; | ||
| 1134 | }; | ||
| 1135 | }; | ||
| 1136 | |||
| 1137 | usbh3 { | ||
| 1138 | pinctrl_usbh3_1: usbh3grp-1 { | ||
| 1139 | fsl,pins = < | ||
| 1140 | MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030 | ||
| 1141 | MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030 | ||
| 1142 | >; | ||
| 1143 | }; | ||
| 1144 | |||
| 1145 | pinctrl_usbh3_2: usbh3grp-2 { | ||
| 1146 | fsl,pins = < | ||
| 1147 | MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030 | ||
| 1148 | >; | ||
| 1149 | }; | ||
| 1150 | }; | ||
| 1151 | |||
| 1152 | usdhc1 { | ||
| 1153 | pinctrl_usdhc1_1: usdhc1grp-1 { | ||
| 1154 | fsl,pins = < | ||
| 1155 | MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 | ||
| 1156 | MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 | ||
| 1157 | MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 | ||
| 1158 | MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 | ||
| 1159 | MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 | ||
| 1160 | MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 | ||
| 1161 | MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059 | ||
| 1162 | MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059 | ||
| 1163 | MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059 | ||
| 1164 | MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059 | ||
| 1165 | >; | ||
| 1166 | }; | ||
| 1167 | |||
| 1168 | pinctrl_usdhc1_2: usdhc1grp-2 { | ||
| 1169 | fsl,pins = < | ||
| 1170 | MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 | ||
| 1171 | MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 | ||
| 1172 | MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 | ||
| 1173 | MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 | ||
| 1174 | MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 | ||
| 1175 | MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 | ||
| 1176 | >; | ||
| 1177 | }; | ||
| 1178 | }; | ||
| 1179 | |||
| 1180 | usdhc2 { | ||
| 1181 | pinctrl_usdhc2_1: usdhc2grp-1 { | ||
| 1182 | fsl,pins = < | ||
| 1183 | MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 | ||
| 1184 | MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 | ||
| 1185 | MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 | ||
| 1186 | MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 | ||
| 1187 | MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 | ||
| 1188 | MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 | ||
| 1189 | MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 | ||
| 1190 | MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 | ||
| 1191 | MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 | ||
| 1192 | MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 | ||
| 1193 | >; | ||
| 1194 | }; | ||
| 1195 | |||
| 1196 | pinctrl_usdhc2_2: usdhc2grp-2 { | ||
| 1197 | fsl,pins = < | ||
| 1198 | MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 | ||
| 1199 | MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 | ||
| 1200 | MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 | ||
| 1201 | MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 | ||
| 1202 | MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 | ||
| 1203 | MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 | ||
| 1204 | >; | ||
| 1205 | }; | ||
| 1206 | }; | ||
| 1207 | |||
| 1208 | usdhc3 { | ||
| 1209 | pinctrl_usdhc3_1: usdhc3grp-1 { | ||
| 1210 | fsl,pins = < | ||
| 1211 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 1212 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 1213 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 1214 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 1215 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 1216 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 1217 | MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 | ||
| 1218 | MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 | ||
| 1219 | MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 | ||
| 1220 | MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 | ||
| 1221 | >; | ||
| 1222 | }; | ||
| 1223 | |||
| 1224 | pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { /* 100Mhz */ | ||
| 1225 | fsl,pins = < | ||
| 1226 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 | ||
| 1227 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 | ||
| 1228 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 | ||
| 1229 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 | ||
| 1230 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 | ||
| 1231 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 | ||
| 1232 | MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 | ||
| 1233 | MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 | ||
| 1234 | MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 | ||
| 1235 | MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 | ||
| 1236 | >; | ||
| 1237 | }; | ||
| 1238 | |||
| 1239 | pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { /* 200Mhz */ | ||
| 1240 | fsl,pins = < | ||
| 1241 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 | ||
| 1242 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 | ||
| 1243 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 | ||
| 1244 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 | ||
| 1245 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 | ||
| 1246 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 | ||
| 1247 | MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 | ||
| 1248 | MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 | ||
| 1249 | MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 | ||
| 1250 | MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 | ||
| 1251 | >; | ||
| 1252 | }; | ||
| 1253 | |||
| 1254 | pinctrl_usdhc3_2: usdhc3grp-2 { | ||
| 1255 | fsl,pins = < | ||
| 1256 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 1257 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 1258 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 1259 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 1260 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 1261 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 1262 | >; | ||
| 1263 | }; | ||
| 1264 | }; | ||
| 1265 | |||
| 1266 | usdhc4 { | ||
| 1267 | pinctrl_usdhc4_1: usdhc4grp-1 { | ||
| 1268 | fsl,pins = < | ||
| 1269 | MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 | ||
| 1270 | MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 | ||
| 1271 | MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 | ||
| 1272 | MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 | ||
| 1273 | MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 | ||
| 1274 | MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 | ||
| 1275 | MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 | ||
| 1276 | MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 | ||
| 1277 | MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 | ||
| 1278 | MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 | ||
| 1279 | >; | ||
| 1280 | }; | ||
| 1281 | |||
| 1282 | pinctrl_usdhc4_2: usdhc4grp-2 { | ||
| 1283 | fsl,pins = < | ||
| 1284 | MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 | ||
| 1285 | MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 | ||
| 1286 | MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 | ||
| 1287 | MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 | ||
| 1288 | MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 | ||
| 1289 | MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 | ||
| 1290 | >; | ||
| 1291 | }; | ||
| 1292 | }; | ||
| 1293 | |||
| 1294 | weim { | ||
| 1295 | pinctrl_weim_cs0_1: weim_cs0grp-1 { | ||
| 1296 | fsl,pins = < | ||
| 1297 | MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 | ||
| 1298 | >; | ||
| 1299 | }; | ||
| 1300 | |||
| 1301 | pinctrl_weim_nor_1: weim_norgrp-1 { | ||
| 1302 | fsl,pins = < | ||
| 1303 | MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 | ||
| 1304 | MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 | ||
| 1305 | MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 | ||
| 1306 | /* data */ | ||
| 1307 | MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 | ||
| 1308 | MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 | ||
| 1309 | MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 | ||
| 1310 | MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 | ||
| 1311 | MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 | ||
| 1312 | MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 | ||
| 1313 | MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 | ||
| 1314 | MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 | ||
| 1315 | MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 | ||
| 1316 | MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 | ||
| 1317 | MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 | ||
| 1318 | MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 | ||
| 1319 | MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 | ||
| 1320 | MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 | ||
| 1321 | MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 | ||
| 1322 | MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 | ||
| 1323 | /* address */ | ||
| 1324 | MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 | ||
| 1325 | MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 | ||
| 1326 | MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 | ||
| 1327 | MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 | ||
| 1328 | MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 | ||
| 1329 | MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 | ||
| 1330 | MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 | ||
| 1331 | MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 | ||
| 1332 | MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 | ||
| 1333 | MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 | ||
| 1334 | MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 | ||
| 1335 | MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 | ||
| 1336 | MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 | ||
| 1337 | MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 | ||
| 1338 | MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 | ||
| 1339 | MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 | ||
| 1340 | MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 | ||
| 1341 | MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 | ||
| 1342 | MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 | ||
| 1343 | MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 | ||
| 1344 | MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 | ||
| 1345 | MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 | ||
| 1346 | MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 | ||
| 1347 | MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 | ||
| 1348 | >; | ||
| 1349 | }; | ||
| 1350 | }; | ||
| 1351 | }; | 657 | }; |
| 1352 | 658 | ||
| 1353 | ldb: ldb@020e0008 { | 659 | ldb: ldb@020e0008 { |
| @@ -1370,18 +676,18 @@ | |||
| 1370 | 676 | ||
| 1371 | dcic1: dcic@020e4000 { | 677 | dcic1: dcic@020e4000 { |
| 1372 | reg = <0x020e4000 0x4000>; | 678 | reg = <0x020e4000 0x4000>; |
| 1373 | interrupts = <0 124 0x04>; | 679 | interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; |
| 1374 | }; | 680 | }; |
| 1375 | 681 | ||
| 1376 | dcic2: dcic@020e8000 { | 682 | dcic2: dcic@020e8000 { |
| 1377 | reg = <0x020e8000 0x4000>; | 683 | reg = <0x020e8000 0x4000>; |
| 1378 | interrupts = <0 125 0x04>; | 684 | interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; |
| 1379 | }; | 685 | }; |
| 1380 | 686 | ||
| 1381 | sdma: sdma@020ec000 { | 687 | sdma: sdma@020ec000 { |
| 1382 | compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; | 688 | compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; |
| 1383 | reg = <0x020ec000 0x4000>; | 689 | reg = <0x020ec000 0x4000>; |
| 1384 | interrupts = <0 2 0x04>; | 690 | interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; |
| 1385 | clocks = <&clks 155>, <&clks 155>; | 691 | clocks = <&clks 155>, <&clks 155>; |
| 1386 | clock-names = "ipg", "ahb"; | 692 | clock-names = "ipg", "ahb"; |
| 1387 | #dma-cells = <3>; | 693 | #dma-cells = <3>; |
| @@ -1398,7 +704,8 @@ | |||
| 1398 | 704 | ||
| 1399 | caam@02100000 { | 705 | caam@02100000 { |
| 1400 | reg = <0x02100000 0x40000>; | 706 | reg = <0x02100000 0x40000>; |
| 1401 | interrupts = <0 105 0x04 0 106 0x04>; | 707 | interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>, |
| 708 | <0 106 IRQ_TYPE_LEVEL_HIGH>; | ||
| 1402 | }; | 709 | }; |
| 1403 | 710 | ||
| 1404 | aipstz@0217c000 { /* AIPSTZ2 */ | 711 | aipstz@0217c000 { /* AIPSTZ2 */ |
| @@ -1408,7 +715,7 @@ | |||
| 1408 | usbotg: usb@02184000 { | 715 | usbotg: usb@02184000 { |
| 1409 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; | 716 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| 1410 | reg = <0x02184000 0x200>; | 717 | reg = <0x02184000 0x200>; |
| 1411 | interrupts = <0 43 0x04>; | 718 | interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; |
| 1412 | clocks = <&clks 162>; | 719 | clocks = <&clks 162>; |
| 1413 | fsl,usbphy = <&usbphy1>; | 720 | fsl,usbphy = <&usbphy1>; |
| 1414 | fsl,usbmisc = <&usbmisc 0>; | 721 | fsl,usbmisc = <&usbmisc 0>; |
| @@ -1418,7 +725,7 @@ | |||
| 1418 | usbh1: usb@02184200 { | 725 | usbh1: usb@02184200 { |
| 1419 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; | 726 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| 1420 | reg = <0x02184200 0x200>; | 727 | reg = <0x02184200 0x200>; |
| 1421 | interrupts = <0 40 0x04>; | 728 | interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; |
| 1422 | clocks = <&clks 162>; | 729 | clocks = <&clks 162>; |
| 1423 | fsl,usbphy = <&usbphy2>; | 730 | fsl,usbphy = <&usbphy2>; |
| 1424 | fsl,usbmisc = <&usbmisc 1>; | 731 | fsl,usbmisc = <&usbmisc 1>; |
| @@ -1428,7 +735,7 @@ | |||
| 1428 | usbh2: usb@02184400 { | 735 | usbh2: usb@02184400 { |
| 1429 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; | 736 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| 1430 | reg = <0x02184400 0x200>; | 737 | reg = <0x02184400 0x200>; |
| 1431 | interrupts = <0 41 0x04>; | 738 | interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; |
| 1432 | clocks = <&clks 162>; | 739 | clocks = <&clks 162>; |
| 1433 | fsl,usbmisc = <&usbmisc 2>; | 740 | fsl,usbmisc = <&usbmisc 2>; |
| 1434 | status = "disabled"; | 741 | status = "disabled"; |
| @@ -1437,7 +744,7 @@ | |||
| 1437 | usbh3: usb@02184600 { | 744 | usbh3: usb@02184600 { |
| 1438 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; | 745 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| 1439 | reg = <0x02184600 0x200>; | 746 | reg = <0x02184600 0x200>; |
| 1440 | interrupts = <0 42 0x04>; | 747 | interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; |
| 1441 | clocks = <&clks 162>; | 748 | clocks = <&clks 162>; |
| 1442 | fsl,usbmisc = <&usbmisc 3>; | 749 | fsl,usbmisc = <&usbmisc 3>; |
| 1443 | status = "disabled"; | 750 | status = "disabled"; |
| @@ -1453,7 +760,9 @@ | |||
| 1453 | fec: ethernet@02188000 { | 760 | fec: ethernet@02188000 { |
| 1454 | compatible = "fsl,imx6q-fec"; | 761 | compatible = "fsl,imx6q-fec"; |
| 1455 | reg = <0x02188000 0x4000>; | 762 | reg = <0x02188000 0x4000>; |
| 1456 | interrupts = <0 118 0x04 0 119 0x04>; | 763 | interrupts-extended = |
| 764 | <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>, | ||
| 765 | <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; | ||
| 1457 | clocks = <&clks 117>, <&clks 117>, <&clks 190>; | 766 | clocks = <&clks 117>, <&clks 117>, <&clks 190>; |
| 1458 | clock-names = "ipg", "ahb", "ptp"; | 767 | clock-names = "ipg", "ahb", "ptp"; |
| 1459 | status = "disabled"; | 768 | status = "disabled"; |
| @@ -1461,13 +770,15 @@ | |||
| 1461 | 770 | ||
| 1462 | mlb@0218c000 { | 771 | mlb@0218c000 { |
| 1463 | reg = <0x0218c000 0x4000>; | 772 | reg = <0x0218c000 0x4000>; |
| 1464 | interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>; | 773 | interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>, |
| 774 | <0 117 IRQ_TYPE_LEVEL_HIGH>, | ||
| 775 | <0 126 IRQ_TYPE_LEVEL_HIGH>; | ||
| 1465 | }; | 776 | }; |
| 1466 | 777 | ||
| 1467 | usdhc1: usdhc@02190000 { | 778 | usdhc1: usdhc@02190000 { |
| 1468 | compatible = "fsl,imx6q-usdhc"; | 779 | compatible = "fsl,imx6q-usdhc"; |
| 1469 | reg = <0x02190000 0x4000>; | 780 | reg = <0x02190000 0x4000>; |
| 1470 | interrupts = <0 22 0x04>; | 781 | interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; |
| 1471 | clocks = <&clks 163>, <&clks 163>, <&clks 163>; | 782 | clocks = <&clks 163>, <&clks 163>, <&clks 163>; |
| 1472 | clock-names = "ipg", "ahb", "per"; | 783 | clock-names = "ipg", "ahb", "per"; |
| 1473 | bus-width = <4>; | 784 | bus-width = <4>; |
| @@ -1477,7 +788,7 @@ | |||
| 1477 | usdhc2: usdhc@02194000 { | 788 | usdhc2: usdhc@02194000 { |
| 1478 | compatible = "fsl,imx6q-usdhc"; | 789 | compatible = "fsl,imx6q-usdhc"; |
| 1479 | reg = <0x02194000 0x4000>; | 790 | reg = <0x02194000 0x4000>; |
| 1480 | interrupts = <0 23 0x04>; | 791 | interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; |
| 1481 | clocks = <&clks 164>, <&clks 164>, <&clks 164>; | 792 | clocks = <&clks 164>, <&clks 164>, <&clks 164>; |
| 1482 | clock-names = "ipg", "ahb", "per"; | 793 | clock-names = "ipg", "ahb", "per"; |
| 1483 | bus-width = <4>; | 794 | bus-width = <4>; |
| @@ -1487,7 +798,7 @@ | |||
| 1487 | usdhc3: usdhc@02198000 { | 798 | usdhc3: usdhc@02198000 { |
| 1488 | compatible = "fsl,imx6q-usdhc"; | 799 | compatible = "fsl,imx6q-usdhc"; |
| 1489 | reg = <0x02198000 0x4000>; | 800 | reg = <0x02198000 0x4000>; |
| 1490 | interrupts = <0 24 0x04>; | 801 | interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; |
| 1491 | clocks = <&clks 165>, <&clks 165>, <&clks 165>; | 802 | clocks = <&clks 165>, <&clks 165>, <&clks 165>; |
| 1492 | clock-names = "ipg", "ahb", "per"; | 803 | clock-names = "ipg", "ahb", "per"; |
| 1493 | bus-width = <4>; | 804 | bus-width = <4>; |
| @@ -1497,7 +808,7 @@ | |||
| 1497 | usdhc4: usdhc@0219c000 { | 808 | usdhc4: usdhc@0219c000 { |
| 1498 | compatible = "fsl,imx6q-usdhc"; | 809 | compatible = "fsl,imx6q-usdhc"; |
| 1499 | reg = <0x0219c000 0x4000>; | 810 | reg = <0x0219c000 0x4000>; |
| 1500 | interrupts = <0 25 0x04>; | 811 | interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; |
| 1501 | clocks = <&clks 166>, <&clks 166>, <&clks 166>; | 812 | clocks = <&clks 166>, <&clks 166>, <&clks 166>; |
| 1502 | clock-names = "ipg", "ahb", "per"; | 813 | clock-names = "ipg", "ahb", "per"; |
| 1503 | bus-width = <4>; | 814 | bus-width = <4>; |
| @@ -1509,7 +820,7 @@ | |||
| 1509 | #size-cells = <0>; | 820 | #size-cells = <0>; |
| 1510 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; | 821 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
| 1511 | reg = <0x021a0000 0x4000>; | 822 | reg = <0x021a0000 0x4000>; |
| 1512 | interrupts = <0 36 0x04>; | 823 | interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; |
| 1513 | clocks = <&clks 125>; | 824 | clocks = <&clks 125>; |
| 1514 | status = "disabled"; | 825 | status = "disabled"; |
| 1515 | }; | 826 | }; |
| @@ -1519,7 +830,7 @@ | |||
| 1519 | #size-cells = <0>; | 830 | #size-cells = <0>; |
| 1520 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; | 831 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
| 1521 | reg = <0x021a4000 0x4000>; | 832 | reg = <0x021a4000 0x4000>; |
| 1522 | interrupts = <0 37 0x04>; | 833 | interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; |
| 1523 | clocks = <&clks 126>; | 834 | clocks = <&clks 126>; |
| 1524 | status = "disabled"; | 835 | status = "disabled"; |
| 1525 | }; | 836 | }; |
| @@ -1529,7 +840,7 @@ | |||
| 1529 | #size-cells = <0>; | 840 | #size-cells = <0>; |
| 1530 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; | 841 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
| 1531 | reg = <0x021a8000 0x4000>; | 842 | reg = <0x021a8000 0x4000>; |
| 1532 | interrupts = <0 38 0x04>; | 843 | interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; |
| 1533 | clocks = <&clks 127>; | 844 | clocks = <&clks 127>; |
| 1534 | status = "disabled"; | 845 | status = "disabled"; |
| 1535 | }; | 846 | }; |
| @@ -1550,7 +861,7 @@ | |||
| 1550 | weim: weim@021b8000 { | 861 | weim: weim@021b8000 { |
| 1551 | compatible = "fsl,imx6q-weim"; | 862 | compatible = "fsl,imx6q-weim"; |
| 1552 | reg = <0x021b8000 0x4000>; | 863 | reg = <0x021b8000 0x4000>; |
| 1553 | interrupts = <0 14 0x04>; | 864 | interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; |
| 1554 | clocks = <&clks 196>; | 865 | clocks = <&clks 196>; |
| 1555 | }; | 866 | }; |
| 1556 | 867 | ||
| @@ -1561,12 +872,12 @@ | |||
| 1561 | 872 | ||
| 1562 | tzasc@021d0000 { /* TZASC1 */ | 873 | tzasc@021d0000 { /* TZASC1 */ |
| 1563 | reg = <0x021d0000 0x4000>; | 874 | reg = <0x021d0000 0x4000>; |
| 1564 | interrupts = <0 108 0x04>; | 875 | interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; |
| 1565 | }; | 876 | }; |
| 1566 | 877 | ||
| 1567 | tzasc@021d4000 { /* TZASC2 */ | 878 | tzasc@021d4000 { /* TZASC2 */ |
| 1568 | reg = <0x021d4000 0x4000>; | 879 | reg = <0x021d4000 0x4000>; |
| 1569 | interrupts = <0 109 0x04>; | 880 | interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; |
| 1570 | }; | 881 | }; |
| 1571 | 882 | ||
| 1572 | audmux: audmux@021d8000 { | 883 | audmux: audmux@021d8000 { |
| @@ -1575,7 +886,7 @@ | |||
| 1575 | status = "disabled"; | 886 | status = "disabled"; |
| 1576 | }; | 887 | }; |
| 1577 | 888 | ||
| 1578 | mipi@021dc000 { /* MIPI-CSI */ | 889 | mipi_csi: mipi@021dc000 { |
| 1579 | reg = <0x021dc000 0x4000>; | 890 | reg = <0x021dc000 0x4000>; |
| 1580 | }; | 891 | }; |
| 1581 | 892 | ||
| @@ -1585,13 +896,13 @@ | |||
| 1585 | 896 | ||
| 1586 | vdoa@021e4000 { | 897 | vdoa@021e4000 { |
| 1587 | reg = <0x021e4000 0x4000>; | 898 | reg = <0x021e4000 0x4000>; |
| 1588 | interrupts = <0 18 0x04>; | 899 | interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; |
| 1589 | }; | 900 | }; |
| 1590 | 901 | ||
| 1591 | uart2: serial@021e8000 { | 902 | uart2: serial@021e8000 { |
| 1592 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; | 903 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 1593 | reg = <0x021e8000 0x4000>; | 904 | reg = <0x021e8000 0x4000>; |
| 1594 | interrupts = <0 27 0x04>; | 905 | interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; |
| 1595 | clocks = <&clks 160>, <&clks 161>; | 906 | clocks = <&clks 160>, <&clks 161>; |
| 1596 | clock-names = "ipg", "per"; | 907 | clock-names = "ipg", "per"; |
| 1597 | dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; | 908 | dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; |
| @@ -1602,7 +913,7 @@ | |||
| 1602 | uart3: serial@021ec000 { | 913 | uart3: serial@021ec000 { |
| 1603 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; | 914 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 1604 | reg = <0x021ec000 0x4000>; | 915 | reg = <0x021ec000 0x4000>; |
| 1605 | interrupts = <0 28 0x04>; | 916 | interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; |
| 1606 | clocks = <&clks 160>, <&clks 161>; | 917 | clocks = <&clks 160>, <&clks 161>; |
| 1607 | clock-names = "ipg", "per"; | 918 | clock-names = "ipg", "per"; |
| 1608 | dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; | 919 | dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; |
| @@ -1613,7 +924,7 @@ | |||
| 1613 | uart4: serial@021f0000 { | 924 | uart4: serial@021f0000 { |
| 1614 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; | 925 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 1615 | reg = <0x021f0000 0x4000>; | 926 | reg = <0x021f0000 0x4000>; |
| 1616 | interrupts = <0 29 0x04>; | 927 | interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; |
| 1617 | clocks = <&clks 160>, <&clks 161>; | 928 | clocks = <&clks 160>, <&clks 161>; |
| 1618 | clock-names = "ipg", "per"; | 929 | clock-names = "ipg", "per"; |
| 1619 | dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; | 930 | dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; |
| @@ -1624,7 +935,7 @@ | |||
| 1624 | uart5: serial@021f4000 { | 935 | uart5: serial@021f4000 { |
| 1625 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; | 936 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 1626 | reg = <0x021f4000 0x4000>; | 937 | reg = <0x021f4000 0x4000>; |
| 1627 | interrupts = <0 30 0x04>; | 938 | interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; |
| 1628 | clocks = <&clks 160>, <&clks 161>; | 939 | clocks = <&clks 160>, <&clks 161>; |
| 1629 | clock-names = "ipg", "per"; | 940 | clock-names = "ipg", "per"; |
| 1630 | dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; | 941 | dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; |
| @@ -1637,7 +948,8 @@ | |||
| 1637 | #crtc-cells = <1>; | 948 | #crtc-cells = <1>; |
| 1638 | compatible = "fsl,imx6q-ipu"; | 949 | compatible = "fsl,imx6q-ipu"; |
| 1639 | reg = <0x02400000 0x400000>; | 950 | reg = <0x02400000 0x400000>; |
| 1640 | interrupts = <0 6 0x4 0 5 0x4>; | 951 | interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>, |
| 952 | <0 5 IRQ_TYPE_LEVEL_HIGH>; | ||
| 1641 | clocks = <&clks 130>, <&clks 131>, <&clks 132>; | 953 | clocks = <&clks 130>, <&clks 131>, <&clks 132>; |
| 1642 | clock-names = "bus", "di0", "di1"; | 954 | clock-names = "bus", "di0", "di1"; |
| 1643 | resets = <&src 2>; | 955 | resets = <&src 2>; |
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index cc68e19c5163..864d8dfb51ca 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts | |||
| @@ -8,6 +8,8 @@ | |||
| 8 | 8 | ||
| 9 | /dts-v1/; | 9 | /dts-v1/; |
| 10 | 10 | ||
| 11 | #include <dt-bindings/gpio/gpio.h> | ||
| 12 | #include <dt-bindings/input/input.h> | ||
| 11 | #include "imx6sl.dtsi" | 13 | #include "imx6sl.dtsi" |
| 12 | 14 | ||
| 13 | / { | 15 | / { |
| @@ -18,11 +20,26 @@ | |||
| 18 | reg = <0x80000000 0x40000000>; | 20 | reg = <0x80000000 0x40000000>; |
| 19 | }; | 21 | }; |
| 20 | 22 | ||
| 23 | leds { | ||
| 24 | compatible = "gpio-leds"; | ||
| 25 | pinctrl-names = "default"; | ||
| 26 | pinctrl-0 = <&pinctrl_led>; | ||
| 27 | |||
| 28 | user { | ||
| 29 | label = "debug"; | ||
| 30 | gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; | ||
| 31 | linux,default-trigger = "heartbeat"; | ||
| 32 | }; | ||
| 33 | }; | ||
| 34 | |||
| 21 | regulators { | 35 | regulators { |
| 22 | compatible = "simple-bus"; | 36 | compatible = "simple-bus"; |
| 37 | #address-cells = <1>; | ||
| 38 | #size-cells = <0>; | ||
| 23 | 39 | ||
| 24 | reg_usb_otg1_vbus: usb_otg1_vbus { | 40 | reg_usb_otg1_vbus: regulator@0 { |
| 25 | compatible = "regulator-fixed"; | 41 | compatible = "regulator-fixed"; |
| 42 | reg = <0>; | ||
| 26 | regulator-name = "usb_otg1_vbus"; | 43 | regulator-name = "usb_otg1_vbus"; |
| 27 | regulator-min-microvolt = <5000000>; | 44 | regulator-min-microvolt = <5000000>; |
| 28 | regulator-max-microvolt = <5000000>; | 45 | regulator-max-microvolt = <5000000>; |
| @@ -30,22 +47,63 @@ | |||
| 30 | enable-active-high; | 47 | enable-active-high; |
| 31 | }; | 48 | }; |
| 32 | 49 | ||
| 33 | reg_usb_otg2_vbus: usb_otg2_vbus { | 50 | reg_usb_otg2_vbus: regulator@1 { |
| 34 | compatible = "regulator-fixed"; | 51 | compatible = "regulator-fixed"; |
| 52 | reg = <1>; | ||
| 35 | regulator-name = "usb_otg2_vbus"; | 53 | regulator-name = "usb_otg2_vbus"; |
| 36 | regulator-min-microvolt = <5000000>; | 54 | regulator-min-microvolt = <5000000>; |
| 37 | regulator-max-microvolt = <5000000>; | 55 | regulator-max-microvolt = <5000000>; |
| 38 | gpio = <&gpio4 2 0>; | 56 | gpio = <&gpio4 2 0>; |
| 39 | enable-active-high; | 57 | enable-active-high; |
| 40 | }; | 58 | }; |
| 59 | |||
| 60 | reg_aud3v: regulator@2 { | ||
| 61 | compatible = "regulator-fixed"; | ||
| 62 | reg = <2>; | ||
| 63 | regulator-name = "wm8962-supply-3v15"; | ||
| 64 | regulator-min-microvolt = <3150000>; | ||
| 65 | regulator-max-microvolt = <3150000>; | ||
| 66 | regulator-boot-on; | ||
| 67 | }; | ||
| 68 | |||
| 69 | reg_aud4v: regulator@3 { | ||
| 70 | compatible = "regulator-fixed"; | ||
| 71 | reg = <3>; | ||
| 72 | regulator-name = "wm8962-supply-4v2"; | ||
| 73 | regulator-min-microvolt = <4325000>; | ||
| 74 | regulator-max-microvolt = <4325000>; | ||
| 75 | regulator-boot-on; | ||
| 76 | }; | ||
| 77 | }; | ||
| 78 | |||
| 79 | sound { | ||
| 80 | compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962"; | ||
| 81 | model = "wm8962-audio"; | ||
| 82 | ssi-controller = <&ssi2>; | ||
| 83 | audio-codec = <&codec>; | ||
| 84 | audio-routing = | ||
| 85 | "Headphone Jack", "HPOUTL", | ||
| 86 | "Headphone Jack", "HPOUTR", | ||
| 87 | "Ext Spk", "SPKOUTL", | ||
| 88 | "Ext Spk", "SPKOUTR", | ||
| 89 | "AMIC", "MICBIAS", | ||
| 90 | "IN3R", "AMIC"; | ||
| 91 | mux-int-port = <2>; | ||
| 92 | mux-ext-port = <3>; | ||
| 41 | }; | 93 | }; |
| 42 | }; | 94 | }; |
| 43 | 95 | ||
| 96 | &audmux { | ||
| 97 | pinctrl-names = "default"; | ||
| 98 | pinctrl-0 = <&pinctrl_audmux3>; | ||
| 99 | status = "okay"; | ||
| 100 | }; | ||
| 101 | |||
| 44 | &ecspi1 { | 102 | &ecspi1 { |
| 45 | fsl,spi-num-chipselects = <1>; | 103 | fsl,spi-num-chipselects = <1>; |
| 46 | cs-gpios = <&gpio4 11 0>; | 104 | cs-gpios = <&gpio4 11 0>; |
| 47 | pinctrl-names = "default"; | 105 | pinctrl-names = "default"; |
| 48 | pinctrl-0 = <&pinctrl_ecspi1_1>; | 106 | pinctrl-0 = <&pinctrl_ecspi1>; |
| 49 | status = "okay"; | 107 | status = "okay"; |
| 50 | 108 | ||
| 51 | flash: m25p80@0 { | 109 | flash: m25p80@0 { |
| @@ -59,16 +117,144 @@ | |||
| 59 | 117 | ||
| 60 | &fec { | 118 | &fec { |
| 61 | pinctrl-names = "default"; | 119 | pinctrl-names = "default"; |
| 62 | pinctrl-0 = <&pinctrl_fec_1>; | 120 | pinctrl-0 = <&pinctrl_fec>; |
| 63 | phy-mode = "rmii"; | 121 | phy-mode = "rmii"; |
| 64 | status = "okay"; | 122 | status = "okay"; |
| 65 | }; | 123 | }; |
| 66 | 124 | ||
| 125 | &i2c1 { | ||
| 126 | clock-frequency = <100000>; | ||
| 127 | pinctrl-names = "default"; | ||
| 128 | pinctrl-0 = <&pinctrl_i2c1>; | ||
| 129 | status = "okay"; | ||
| 130 | |||
| 131 | pmic: pfuze100@08 { | ||
| 132 | compatible = "fsl,pfuze100"; | ||
| 133 | reg = <0x08>; | ||
| 134 | |||
| 135 | regulators { | ||
| 136 | sw1a_reg: sw1ab { | ||
| 137 | regulator-min-microvolt = <300000>; | ||
| 138 | regulator-max-microvolt = <1875000>; | ||
| 139 | regulator-boot-on; | ||
| 140 | regulator-always-on; | ||
| 141 | regulator-ramp-delay = <6250>; | ||
| 142 | }; | ||
| 143 | |||
| 144 | sw1c_reg: sw1c { | ||
| 145 | regulator-min-microvolt = <300000>; | ||
| 146 | regulator-max-microvolt = <1875000>; | ||
| 147 | regulator-boot-on; | ||
| 148 | regulator-always-on; | ||
| 149 | regulator-ramp-delay = <6250>; | ||
| 150 | }; | ||
| 151 | |||
| 152 | sw2_reg: sw2 { | ||
| 153 | regulator-min-microvolt = <800000>; | ||
| 154 | regulator-max-microvolt = <3300000>; | ||
| 155 | regulator-boot-on; | ||
| 156 | regulator-always-on; | ||
| 157 | }; | ||
| 158 | |||
| 159 | sw3a_reg: sw3a { | ||
| 160 | regulator-min-microvolt = <400000>; | ||
| 161 | regulator-max-microvolt = <1975000>; | ||
| 162 | regulator-boot-on; | ||
| 163 | regulator-always-on; | ||
| 164 | }; | ||
| 165 | |||
| 166 | sw3b_reg: sw3b { | ||
| 167 | regulator-min-microvolt = <400000>; | ||
| 168 | regulator-max-microvolt = <1975000>; | ||
| 169 | regulator-boot-on; | ||
| 170 | regulator-always-on; | ||
| 171 | }; | ||
| 172 | |||
| 173 | sw4_reg: sw4 { | ||
| 174 | regulator-min-microvolt = <800000>; | ||
| 175 | regulator-max-microvolt = <3300000>; | ||
| 176 | }; | ||
| 177 | |||
| 178 | swbst_reg: swbst { | ||
| 179 | regulator-min-microvolt = <5000000>; | ||
| 180 | regulator-max-microvolt = <5150000>; | ||
| 181 | }; | ||
| 182 | |||
| 183 | snvs_reg: vsnvs { | ||
| 184 | regulator-min-microvolt = <1000000>; | ||
| 185 | regulator-max-microvolt = <3000000>; | ||
| 186 | regulator-boot-on; | ||
| 187 | regulator-always-on; | ||
| 188 | }; | ||
| 189 | |||
| 190 | vref_reg: vrefddr { | ||
| 191 | regulator-boot-on; | ||
| 192 | regulator-always-on; | ||
| 193 | }; | ||
| 194 | |||
| 195 | vgen1_reg: vgen1 { | ||
| 196 | regulator-min-microvolt = <800000>; | ||
| 197 | regulator-max-microvolt = <1550000>; | ||
| 198 | regulator-always-on; | ||
| 199 | }; | ||
| 200 | |||
| 201 | vgen2_reg: vgen2 { | ||
| 202 | regulator-min-microvolt = <800000>; | ||
| 203 | regulator-max-microvolt = <1550000>; | ||
| 204 | }; | ||
| 205 | |||
| 206 | vgen3_reg: vgen3 { | ||
| 207 | regulator-min-microvolt = <1800000>; | ||
| 208 | regulator-max-microvolt = <3300000>; | ||
| 209 | }; | ||
| 210 | |||
| 211 | vgen4_reg: vgen4 { | ||
| 212 | regulator-min-microvolt = <1800000>; | ||
| 213 | regulator-max-microvolt = <3300000>; | ||
| 214 | regulator-always-on; | ||
| 215 | }; | ||
| 216 | |||
| 217 | vgen5_reg: vgen5 { | ||
| 218 | regulator-min-microvolt = <1800000>; | ||
| 219 | regulator-max-microvolt = <3300000>; | ||
| 220 | regulator-always-on; | ||
| 221 | }; | ||
| 222 | |||
| 223 | vgen6_reg: vgen6 { | ||
| 224 | regulator-min-microvolt = <1800000>; | ||
| 225 | regulator-max-microvolt = <3300000>; | ||
| 226 | regulator-always-on; | ||
| 227 | }; | ||
| 228 | }; | ||
| 229 | }; | ||
| 230 | }; | ||
| 231 | |||
| 232 | &i2c2 { | ||
| 233 | clock-frequency = <100000>; | ||
| 234 | pinctrl-names = "default"; | ||
| 235 | pinctrl-0 = <&pinctrl_i2c2>; | ||
| 236 | status = "okay"; | ||
| 237 | |||
| 238 | codec: wm8962@1a { | ||
| 239 | compatible = "wlf,wm8962"; | ||
| 240 | reg = <0x1a>; | ||
| 241 | clocks = <&clks IMX6SL_CLK_EXTERN_AUDIO>; | ||
| 242 | DCVDD-supply = <&vgen3_reg>; | ||
| 243 | DBVDD-supply = <®_aud3v>; | ||
| 244 | AVDD-supply = <&vgen3_reg>; | ||
| 245 | CPVDD-supply = <&vgen3_reg>; | ||
| 246 | MICVDD-supply = <®_aud3v>; | ||
| 247 | PLLVDD-supply = <&vgen3_reg>; | ||
| 248 | SPKVDD1-supply = <®_aud4v>; | ||
| 249 | SPKVDD2-supply = <®_aud4v>; | ||
| 250 | }; | ||
| 251 | }; | ||
| 252 | |||
| 67 | &iomuxc { | 253 | &iomuxc { |
| 68 | pinctrl-names = "default"; | 254 | pinctrl-names = "default"; |
| 69 | pinctrl-0 = <&pinctrl_hog>; | 255 | pinctrl-0 = <&pinctrl_hog>; |
| 70 | 256 | ||
| 71 | hog { | 257 | imx6sl-evk { |
| 72 | pinctrl_hog: hoggrp { | 258 | pinctrl_hog: hoggrp { |
| 73 | fsl,pins = < | 259 | fsl,pins = < |
| 74 | MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059 | 260 | MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059 |
| @@ -78,21 +264,230 @@ | |||
| 78 | MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 | 264 | MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 |
| 79 | MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000 | 265 | MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000 |
| 80 | MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000 | 266 | MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000 |
| 267 | MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0 | ||
| 268 | >; | ||
| 269 | }; | ||
| 270 | |||
| 271 | pinctrl_audmux3: audmux3grp { | ||
| 272 | fsl,pins = < | ||
| 273 | MX6SL_PAD_AUD_RXD__AUD3_RXD 0x4130b0 | ||
| 274 | MX6SL_PAD_AUD_TXC__AUD3_TXC 0x4130b0 | ||
| 275 | MX6SL_PAD_AUD_TXD__AUD3_TXD 0x4110b0 | ||
| 276 | MX6SL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0 | ||
| 277 | >; | ||
| 278 | }; | ||
| 279 | |||
| 280 | pinctrl_ecspi1: ecspi1grp { | ||
| 281 | fsl,pins = < | ||
| 282 | MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1 | ||
| 283 | MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1 | ||
| 284 | MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1 | ||
| 285 | >; | ||
| 286 | }; | ||
| 287 | |||
| 288 | pinctrl_fec: fecgrp { | ||
| 289 | fsl,pins = < | ||
| 290 | MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0 | ||
| 291 | MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0 | ||
| 292 | MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0 | ||
| 293 | MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0 | ||
| 294 | MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0 | ||
| 295 | MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0 | ||
| 296 | MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0 | ||
| 297 | MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0 | ||
| 298 | MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8 | ||
| 299 | >; | ||
| 300 | }; | ||
| 301 | |||
| 302 | pinctrl_i2c1: i2c1grp { | ||
| 303 | fsl,pins = < | ||
| 304 | MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1 | ||
| 305 | MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1 | ||
| 306 | >; | ||
| 307 | }; | ||
| 308 | |||
| 309 | |||
| 310 | pinctrl_i2c2: i2c2grp { | ||
| 311 | fsl,pins = < | ||
| 312 | MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001b8b1 | ||
| 313 | MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001b8b1 | ||
| 314 | >; | ||
| 315 | }; | ||
| 316 | |||
| 317 | pinctrl_led: ledgrp { | ||
| 318 | fsl,pins = < | ||
| 319 | MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059 | ||
| 320 | >; | ||
| 321 | }; | ||
| 322 | |||
| 323 | pinctrl_kpp: kppgrp { | ||
| 324 | fsl,pins = < | ||
| 325 | MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010 | ||
| 326 | MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x1b010 | ||
| 327 | MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b0 | ||
| 328 | MX6SL_PAD_KEY_COL0__KEY_COL0 0x110b0 | ||
| 329 | MX6SL_PAD_KEY_COL1__KEY_COL1 0x110b0 | ||
| 330 | MX6SL_PAD_KEY_COL2__KEY_COL2 0x110b0 | ||
| 331 | >; | ||
| 332 | }; | ||
| 333 | |||
| 334 | pinctrl_uart1: uart1grp { | ||
| 335 | fsl,pins = < | ||
| 336 | MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 | ||
| 337 | MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 | ||
| 338 | >; | ||
| 339 | }; | ||
| 340 | |||
| 341 | pinctrl_usbotg1: usbotg1grp { | ||
| 342 | fsl,pins = < | ||
| 343 | MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 | ||
| 344 | >; | ||
| 345 | }; | ||
| 346 | |||
| 347 | pinctrl_usdhc1: usdhc1grp { | ||
| 348 | fsl,pins = < | ||
| 349 | MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059 | ||
| 350 | MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059 | ||
| 351 | MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059 | ||
| 352 | MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059 | ||
| 353 | MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059 | ||
| 354 | MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059 | ||
| 355 | MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059 | ||
| 356 | MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059 | ||
| 357 | MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059 | ||
| 358 | MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059 | ||
| 359 | >; | ||
| 360 | }; | ||
| 361 | |||
| 362 | pinctrl_usdhc1_100mhz: usdhc1grp100mhz { | ||
| 363 | fsl,pins = < | ||
| 364 | MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9 | ||
| 365 | MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9 | ||
| 366 | MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9 | ||
| 367 | MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9 | ||
| 368 | MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9 | ||
| 369 | MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9 | ||
| 370 | MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9 | ||
| 371 | MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9 | ||
| 372 | MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9 | ||
| 373 | MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9 | ||
| 374 | >; | ||
| 375 | }; | ||
| 376 | |||
| 377 | pinctrl_usdhc1_200mhz: usdhc1grp200mhz { | ||
| 378 | fsl,pins = < | ||
| 379 | MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9 | ||
| 380 | MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9 | ||
| 381 | MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 | ||
| 382 | MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 | ||
| 383 | MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 | ||
| 384 | MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 | ||
| 385 | MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9 | ||
| 386 | MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9 | ||
| 387 | MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9 | ||
| 388 | MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9 | ||
| 389 | >; | ||
| 390 | }; | ||
| 391 | |||
| 392 | pinctrl_usdhc2: usdhc2grp { | ||
| 393 | fsl,pins = < | ||
| 394 | MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 | ||
| 395 | MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059 | ||
| 396 | MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 | ||
| 397 | MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 | ||
| 398 | MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 | ||
| 399 | MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 | ||
| 400 | >; | ||
| 401 | }; | ||
| 402 | |||
| 403 | pinctrl_usdhc2_100mhz: usdhc2grp100mhz { | ||
| 404 | fsl,pins = < | ||
| 405 | MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 | ||
| 406 | MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9 | ||
| 407 | MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 | ||
| 408 | MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 | ||
| 409 | MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 | ||
| 410 | MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 | ||
| 411 | >; | ||
| 412 | }; | ||
| 413 | |||
| 414 | pinctrl_usdhc2_200mhz: usdhc2grp200mhz { | ||
| 415 | fsl,pins = < | ||
| 416 | MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 | ||
| 417 | MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9 | ||
| 418 | MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 | ||
| 419 | MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 | ||
| 420 | MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 | ||
| 421 | MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 | ||
| 422 | >; | ||
| 423 | }; | ||
| 424 | |||
| 425 | pinctrl_usdhc3: usdhc3grp { | ||
| 426 | fsl,pins = < | ||
| 427 | MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 428 | MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 429 | MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 430 | MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 431 | MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 432 | MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 433 | >; | ||
| 434 | }; | ||
| 435 | |||
| 436 | pinctrl_usdhc3_100mhz: usdhc3grp100mhz { | ||
| 437 | fsl,pins = < | ||
| 438 | MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 | ||
| 439 | MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9 | ||
| 440 | MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 | ||
| 441 | MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 | ||
| 442 | MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 | ||
| 443 | MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 | ||
| 444 | >; | ||
| 445 | }; | ||
| 446 | |||
| 447 | pinctrl_usdhc3_200mhz: usdhc3grp200mhz { | ||
| 448 | fsl,pins = < | ||
| 449 | MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 | ||
| 450 | MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9 | ||
| 451 | MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 | ||
| 452 | MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 | ||
| 453 | MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 | ||
| 454 | MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 | ||
| 81 | >; | 455 | >; |
| 82 | }; | 456 | }; |
| 83 | }; | 457 | }; |
| 84 | }; | 458 | }; |
| 85 | 459 | ||
| 460 | &kpp { | ||
| 461 | pinctrl-names = "default"; | ||
| 462 | pinctrl-0 = <&pinctrl_kpp>; | ||
| 463 | linux,keymap = < | ||
| 464 | MATRIX_KEY(0x0, 0x0, KEY_UP) /* ROW0, COL0 */ | ||
| 465 | MATRIX_KEY(0x0, 0x1, KEY_DOWN) /* ROW0, COL1 */ | ||
| 466 | MATRIX_KEY(0x0, 0x2, KEY_ENTER) /* ROW0, COL2 */ | ||
| 467 | MATRIX_KEY(0x1, 0x0, KEY_HOME) /* ROW1, COL0 */ | ||
| 468 | MATRIX_KEY(0x1, 0x1, KEY_RIGHT) /* ROW1, COL1 */ | ||
| 469 | MATRIX_KEY(0x1, 0x2, KEY_LEFT) /* ROW1, COL2 */ | ||
| 470 | MATRIX_KEY(0x2, 0x0, KEY_VOLUMEDOWN) /* ROW2, COL0 */ | ||
| 471 | MATRIX_KEY(0x2, 0x1, KEY_VOLUMEUP) /* ROW2, COL1 */ | ||
| 472 | >; | ||
| 473 | status = "okay"; | ||
| 474 | }; | ||
| 475 | |||
| 476 | &ssi2 { | ||
| 477 | fsl,mode = "i2s-slave"; | ||
| 478 | status = "okay"; | ||
| 479 | }; | ||
| 480 | |||
| 86 | &uart1 { | 481 | &uart1 { |
| 87 | pinctrl-names = "default"; | 482 | pinctrl-names = "default"; |
| 88 | pinctrl-0 = <&pinctrl_uart1_1>; | 483 | pinctrl-0 = <&pinctrl_uart1>; |
| 89 | status = "okay"; | 484 | status = "okay"; |
| 90 | }; | 485 | }; |
| 91 | 486 | ||
| 92 | &usbotg1 { | 487 | &usbotg1 { |
| 93 | vbus-supply = <®_usb_otg1_vbus>; | 488 | vbus-supply = <®_usb_otg1_vbus>; |
| 94 | pinctrl-names = "default"; | 489 | pinctrl-names = "default"; |
| 95 | pinctrl-0 = <&pinctrl_usbotg1_1>; | 490 | pinctrl-0 = <&pinctrl_usbotg1>; |
| 96 | disable-over-current; | 491 | disable-over-current; |
| 97 | status = "okay"; | 492 | status = "okay"; |
| 98 | }; | 493 | }; |
| @@ -106,9 +501,9 @@ | |||
| 106 | 501 | ||
| 107 | &usdhc1 { | 502 | &usdhc1 { |
| 108 | pinctrl-names = "default", "state_100mhz", "state_200mhz"; | 503 | pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| 109 | pinctrl-0 = <&pinctrl_usdhc1_1>; | 504 | pinctrl-0 = <&pinctrl_usdhc1>; |
| 110 | pinctrl-1 = <&pinctrl_usdhc1_1_100mhz>; | 505 | pinctrl-1 = <&pinctrl_usdhc1_100mhz>; |
| 111 | pinctrl-2 = <&pinctrl_usdhc1_1_200mhz>; | 506 | pinctrl-2 = <&pinctrl_usdhc1_200mhz>; |
| 112 | bus-width = <8>; | 507 | bus-width = <8>; |
| 113 | cd-gpios = <&gpio4 7 0>; | 508 | cd-gpios = <&gpio4 7 0>; |
| 114 | wp-gpios = <&gpio4 6 0>; | 509 | wp-gpios = <&gpio4 6 0>; |
| @@ -117,9 +512,9 @@ | |||
| 117 | 512 | ||
| 118 | &usdhc2 { | 513 | &usdhc2 { |
| 119 | pinctrl-names = "default", "state_100mhz", "state_200mhz"; | 514 | pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| 120 | pinctrl-0 = <&pinctrl_usdhc2_1>; | 515 | pinctrl-0 = <&pinctrl_usdhc2>; |
| 121 | pinctrl-1 = <&pinctrl_usdhc2_1_100mhz>; | 516 | pinctrl-1 = <&pinctrl_usdhc2_100mhz>; |
| 122 | pinctrl-2 = <&pinctrl_usdhc2_1_200mhz>; | 517 | pinctrl-2 = <&pinctrl_usdhc2_200mhz>; |
| 123 | cd-gpios = <&gpio5 0 0>; | 518 | cd-gpios = <&gpio5 0 0>; |
| 124 | wp-gpios = <&gpio4 29 0>; | 519 | wp-gpios = <&gpio4 29 0>; |
| 125 | status = "okay"; | 520 | status = "okay"; |
| @@ -127,9 +522,9 @@ | |||
| 127 | 522 | ||
| 128 | &usdhc3 { | 523 | &usdhc3 { |
| 129 | pinctrl-names = "default", "state_100mhz", "state_200mhz"; | 524 | pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| 130 | pinctrl-0 = <&pinctrl_usdhc3_1>; | 525 | pinctrl-0 = <&pinctrl_usdhc3>; |
| 131 | pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>; | 526 | pinctrl-1 = <&pinctrl_usdhc3_100mhz>; |
| 132 | pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>; | 527 | pinctrl-2 = <&pinctrl_usdhc3_200mhz>; |
| 133 | cd-gpios = <&gpio3 22 0>; | 528 | cd-gpios = <&gpio3 22 0>; |
| 134 | status = "okay"; | 529 | status = "okay"; |
| 135 | }; | 530 | }; |
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 28558f1aaf2d..3cb4941afeef 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi | |||
| @@ -7,6 +7,7 @@ | |||
| 7 | * | 7 | * |
| 8 | */ | 8 | */ |
| 9 | 9 | ||
| 10 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 10 | #include "skeleton.dtsi" | 11 | #include "skeleton.dtsi" |
| 11 | #include "imx6sl-pinfunc.h" | 12 | #include "imx6sl-pinfunc.h" |
| 12 | #include <dt-bindings/clock/imx6sl-clock.h> | 13 | #include <dt-bindings/clock/imx6sl-clock.h> |
| @@ -27,6 +28,8 @@ | |||
| 27 | spi1 = &ecspi2; | 28 | spi1 = &ecspi2; |
| 28 | spi2 = &ecspi3; | 29 | spi2 = &ecspi3; |
| 29 | spi3 = &ecspi4; | 30 | spi3 = &ecspi4; |
| 31 | usbphy0 = &usbphy1; | ||
| 32 | usbphy1 = &usbphy2; | ||
| 30 | }; | 33 | }; |
| 31 | 34 | ||
| 32 | cpus { | 35 | cpus { |
| @@ -38,6 +41,27 @@ | |||
| 38 | device_type = "cpu"; | 41 | device_type = "cpu"; |
| 39 | reg = <0x0>; | 42 | reg = <0x0>; |
| 40 | next-level-cache = <&L2>; | 43 | next-level-cache = <&L2>; |
| 44 | operating-points = < | ||
| 45 | /* kHz uV */ | ||
| 46 | 996000 1275000 | ||
| 47 | 792000 1175000 | ||
| 48 | 396000 975000 | ||
| 49 | >; | ||
| 50 | fsl,soc-operating-points = < | ||
| 51 | /* ARM kHz SOC-PU uV */ | ||
| 52 | 996000 1225000 | ||
| 53 | 792000 1175000 | ||
| 54 | 396000 1175000 | ||
| 55 | >; | ||
| 56 | clock-latency = <61036>; /* two CLK32 periods */ | ||
| 57 | clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>, | ||
| 58 | <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>, | ||
| 59 | <&clks IMX6SL_CLK_PLL1_SYS>; | ||
| 60 | clock-names = "arm", "pll2_pfd2_396m", "step", | ||
| 61 | "pll1_sw", "pll1_sys"; | ||
| 62 | arm-supply = <®_arm>; | ||
| 63 | pu-supply = <®_pu>; | ||
| 64 | soc-supply = <®_soc>; | ||
| 41 | }; | 65 | }; |
| 42 | }; | 66 | }; |
| 43 | 67 | ||
| @@ -73,10 +97,16 @@ | |||
| 73 | interrupt-parent = <&intc>; | 97 | interrupt-parent = <&intc>; |
| 74 | ranges; | 98 | ranges; |
| 75 | 99 | ||
| 100 | ocram: sram@00900000 { | ||
| 101 | compatible = "mmio-sram"; | ||
| 102 | reg = <0x00900000 0x20000>; | ||
| 103 | clocks = <&clks IMX6SL_CLK_OCRAM>; | ||
| 104 | }; | ||
| 105 | |||
| 76 | L2: l2-cache@00a02000 { | 106 | L2: l2-cache@00a02000 { |
| 77 | compatible = "arm,pl310-cache"; | 107 | compatible = "arm,pl310-cache"; |
| 78 | reg = <0x00a02000 0x1000>; | 108 | reg = <0x00a02000 0x1000>; |
| 79 | interrupts = <0 92 0x04>; | 109 | interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; |
| 80 | cache-unified; | 110 | cache-unified; |
| 81 | cache-level = <2>; | 111 | cache-level = <2>; |
| 82 | arm,tag-latency = <4 2 3>; | 112 | arm,tag-latency = <4 2 3>; |
| @@ -85,7 +115,7 @@ | |||
| 85 | 115 | ||
| 86 | pmu { | 116 | pmu { |
| 87 | compatible = "arm,cortex-a9-pmu"; | 117 | compatible = "arm,cortex-a9-pmu"; |
| 88 | interrupts = <0 94 0x04>; | 118 | interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; |
| 89 | }; | 119 | }; |
| 90 | 120 | ||
| 91 | aips1: aips-bus@02000000 { | 121 | aips1: aips-bus@02000000 { |
| @@ -104,7 +134,7 @@ | |||
| 104 | 134 | ||
| 105 | spdif: spdif@02004000 { | 135 | spdif: spdif@02004000 { |
| 106 | reg = <0x02004000 0x4000>; | 136 | reg = <0x02004000 0x4000>; |
| 107 | interrupts = <0 52 0x04>; | 137 | interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; |
| 108 | }; | 138 | }; |
| 109 | 139 | ||
| 110 | ecspi1: ecspi@02008000 { | 140 | ecspi1: ecspi@02008000 { |
| @@ -112,7 +142,7 @@ | |||
| 112 | #size-cells = <0>; | 142 | #size-cells = <0>; |
| 113 | compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; | 143 | compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; |
| 114 | reg = <0x02008000 0x4000>; | 144 | reg = <0x02008000 0x4000>; |
| 115 | interrupts = <0 31 0x04>; | 145 | interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; |
| 116 | clocks = <&clks IMX6SL_CLK_ECSPI1>, | 146 | clocks = <&clks IMX6SL_CLK_ECSPI1>, |
| 117 | <&clks IMX6SL_CLK_ECSPI1>; | 147 | <&clks IMX6SL_CLK_ECSPI1>; |
| 118 | clock-names = "ipg", "per"; | 148 | clock-names = "ipg", "per"; |
| @@ -124,7 +154,7 @@ | |||
| 124 | #size-cells = <0>; | 154 | #size-cells = <0>; |
| 125 | compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; | 155 | compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; |
| 126 | reg = <0x0200c000 0x4000>; | 156 | reg = <0x0200c000 0x4000>; |
| 127 | interrupts = <0 32 0x04>; | 157 | interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; |
| 128 | clocks = <&clks IMX6SL_CLK_ECSPI2>, | 158 | clocks = <&clks IMX6SL_CLK_ECSPI2>, |
| 129 | <&clks IMX6SL_CLK_ECSPI2>; | 159 | <&clks IMX6SL_CLK_ECSPI2>; |
| 130 | clock-names = "ipg", "per"; | 160 | clock-names = "ipg", "per"; |
| @@ -136,7 +166,7 @@ | |||
| 136 | #size-cells = <0>; | 166 | #size-cells = <0>; |
| 137 | compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; | 167 | compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; |
| 138 | reg = <0x02010000 0x4000>; | 168 | reg = <0x02010000 0x4000>; |
| 139 | interrupts = <0 33 0x04>; | 169 | interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; |
| 140 | clocks = <&clks IMX6SL_CLK_ECSPI3>, | 170 | clocks = <&clks IMX6SL_CLK_ECSPI3>, |
| 141 | <&clks IMX6SL_CLK_ECSPI3>; | 171 | <&clks IMX6SL_CLK_ECSPI3>; |
| 142 | clock-names = "ipg", "per"; | 172 | clock-names = "ipg", "per"; |
| @@ -148,7 +178,7 @@ | |||
| 148 | #size-cells = <0>; | 178 | #size-cells = <0>; |
| 149 | compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; | 179 | compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; |
| 150 | reg = <0x02014000 0x4000>; | 180 | reg = <0x02014000 0x4000>; |
| 151 | interrupts = <0 34 0x04>; | 181 | interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; |
| 152 | clocks = <&clks IMX6SL_CLK_ECSPI4>, | 182 | clocks = <&clks IMX6SL_CLK_ECSPI4>, |
| 153 | <&clks IMX6SL_CLK_ECSPI4>; | 183 | <&clks IMX6SL_CLK_ECSPI4>; |
| 154 | clock-names = "ipg", "per"; | 184 | clock-names = "ipg", "per"; |
| @@ -159,7 +189,7 @@ | |||
| 159 | compatible = "fsl,imx6sl-uart", | 189 | compatible = "fsl,imx6sl-uart", |
| 160 | "fsl,imx6q-uart", "fsl,imx21-uart"; | 190 | "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 161 | reg = <0x02018000 0x4000>; | 191 | reg = <0x02018000 0x4000>; |
| 162 | interrupts = <0 30 0x04>; | 192 | interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; |
| 163 | clocks = <&clks IMX6SL_CLK_UART>, | 193 | clocks = <&clks IMX6SL_CLK_UART>, |
| 164 | <&clks IMX6SL_CLK_UART_SERIAL>; | 194 | <&clks IMX6SL_CLK_UART_SERIAL>; |
| 165 | clock-names = "ipg", "per"; | 195 | clock-names = "ipg", "per"; |
| @@ -172,7 +202,7 @@ | |||
| 172 | compatible = "fsl,imx6sl-uart", | 202 | compatible = "fsl,imx6sl-uart", |
| 173 | "fsl,imx6q-uart", "fsl,imx21-uart"; | 203 | "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 174 | reg = <0x02020000 0x4000>; | 204 | reg = <0x02020000 0x4000>; |
| 175 | interrupts = <0 26 0x04>; | 205 | interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; |
| 176 | clocks = <&clks IMX6SL_CLK_UART>, | 206 | clocks = <&clks IMX6SL_CLK_UART>, |
| 177 | <&clks IMX6SL_CLK_UART_SERIAL>; | 207 | <&clks IMX6SL_CLK_UART_SERIAL>; |
| 178 | clock-names = "ipg", "per"; | 208 | clock-names = "ipg", "per"; |
| @@ -185,7 +215,7 @@ | |||
| 185 | compatible = "fsl,imx6sl-uart", | 215 | compatible = "fsl,imx6sl-uart", |
| 186 | "fsl,imx6q-uart", "fsl,imx21-uart"; | 216 | "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 187 | reg = <0x02024000 0x4000>; | 217 | reg = <0x02024000 0x4000>; |
| 188 | interrupts = <0 27 0x04>; | 218 | interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; |
| 189 | clocks = <&clks IMX6SL_CLK_UART>, | 219 | clocks = <&clks IMX6SL_CLK_UART>, |
| 190 | <&clks IMX6SL_CLK_UART_SERIAL>; | 220 | <&clks IMX6SL_CLK_UART_SERIAL>; |
| 191 | clock-names = "ipg", "per"; | 221 | clock-names = "ipg", "per"; |
| @@ -195,9 +225,11 @@ | |||
| 195 | }; | 225 | }; |
| 196 | 226 | ||
| 197 | ssi1: ssi@02028000 { | 227 | ssi1: ssi@02028000 { |
| 198 | compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi"; | 228 | compatible = "fsl,imx6sl-ssi", |
| 229 | "fsl,imx51-ssi", | ||
| 230 | "fsl,imx21-ssi"; | ||
| 199 | reg = <0x02028000 0x4000>; | 231 | reg = <0x02028000 0x4000>; |
| 200 | interrupts = <0 46 0x04>; | 232 | interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; |
| 201 | clocks = <&clks IMX6SL_CLK_SSI1>; | 233 | clocks = <&clks IMX6SL_CLK_SSI1>; |
| 202 | dmas = <&sdma 37 1 0>, | 234 | dmas = <&sdma 37 1 0>, |
| 203 | <&sdma 38 1 0>; | 235 | <&sdma 38 1 0>; |
| @@ -207,9 +239,11 @@ | |||
| 207 | }; | 239 | }; |
| 208 | 240 | ||
| 209 | ssi2: ssi@0202c000 { | 241 | ssi2: ssi@0202c000 { |
| 210 | compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi"; | 242 | compatible = "fsl,imx6sl-ssi", |
| 243 | "fsl,imx51-ssi", | ||
| 244 | "fsl,imx21-ssi"; | ||
| 211 | reg = <0x0202c000 0x4000>; | 245 | reg = <0x0202c000 0x4000>; |
| 212 | interrupts = <0 47 0x04>; | 246 | interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; |
| 213 | clocks = <&clks IMX6SL_CLK_SSI2>; | 247 | clocks = <&clks IMX6SL_CLK_SSI2>; |
| 214 | dmas = <&sdma 41 1 0>, | 248 | dmas = <&sdma 41 1 0>, |
| 215 | <&sdma 42 1 0>; | 249 | <&sdma 42 1 0>; |
| @@ -219,9 +253,11 @@ | |||
| 219 | }; | 253 | }; |
| 220 | 254 | ||
| 221 | ssi3: ssi@02030000 { | 255 | ssi3: ssi@02030000 { |
| 222 | compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi"; | 256 | compatible = "fsl,imx6sl-ssi", |
| 257 | "fsl,imx51-ssi", | ||
| 258 | "fsl,imx21-ssi"; | ||
| 223 | reg = <0x02030000 0x4000>; | 259 | reg = <0x02030000 0x4000>; |
| 224 | interrupts = <0 48 0x04>; | 260 | interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; |
| 225 | clocks = <&clks IMX6SL_CLK_SSI3>; | 261 | clocks = <&clks IMX6SL_CLK_SSI3>; |
| 226 | dmas = <&sdma 45 1 0>, | 262 | dmas = <&sdma 45 1 0>, |
| 227 | <&sdma 46 1 0>; | 263 | <&sdma 46 1 0>; |
| @@ -234,7 +270,7 @@ | |||
| 234 | compatible = "fsl,imx6sl-uart", | 270 | compatible = "fsl,imx6sl-uart", |
| 235 | "fsl,imx6q-uart", "fsl,imx21-uart"; | 271 | "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 236 | reg = <0x02034000 0x4000>; | 272 | reg = <0x02034000 0x4000>; |
| 237 | interrupts = <0 28 0x04>; | 273 | interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; |
| 238 | clocks = <&clks IMX6SL_CLK_UART>, | 274 | clocks = <&clks IMX6SL_CLK_UART>, |
| 239 | <&clks IMX6SL_CLK_UART_SERIAL>; | 275 | <&clks IMX6SL_CLK_UART_SERIAL>; |
| 240 | clock-names = "ipg", "per"; | 276 | clock-names = "ipg", "per"; |
| @@ -247,7 +283,7 @@ | |||
| 247 | compatible = "fsl,imx6sl-uart", | 283 | compatible = "fsl,imx6sl-uart", |
| 248 | "fsl,imx6q-uart", "fsl,imx21-uart"; | 284 | "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 249 | reg = <0x02038000 0x4000>; | 285 | reg = <0x02038000 0x4000>; |
| 250 | interrupts = <0 29 0x04>; | 286 | interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; |
| 251 | clocks = <&clks IMX6SL_CLK_UART>, | 287 | clocks = <&clks IMX6SL_CLK_UART>, |
| 252 | <&clks IMX6SL_CLK_UART_SERIAL>; | 288 | <&clks IMX6SL_CLK_UART_SERIAL>; |
| 253 | clock-names = "ipg", "per"; | 289 | clock-names = "ipg", "per"; |
| @@ -261,7 +297,7 @@ | |||
| 261 | #pwm-cells = <2>; | 297 | #pwm-cells = <2>; |
| 262 | compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; | 298 | compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; |
| 263 | reg = <0x02080000 0x4000>; | 299 | reg = <0x02080000 0x4000>; |
| 264 | interrupts = <0 83 0x04>; | 300 | interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; |
| 265 | clocks = <&clks IMX6SL_CLK_PWM1>, | 301 | clocks = <&clks IMX6SL_CLK_PWM1>, |
| 266 | <&clks IMX6SL_CLK_PWM1>; | 302 | <&clks IMX6SL_CLK_PWM1>; |
| 267 | clock-names = "ipg", "per"; | 303 | clock-names = "ipg", "per"; |
| @@ -271,7 +307,7 @@ | |||
| 271 | #pwm-cells = <2>; | 307 | #pwm-cells = <2>; |
| 272 | compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; | 308 | compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; |
| 273 | reg = <0x02084000 0x4000>; | 309 | reg = <0x02084000 0x4000>; |
| 274 | interrupts = <0 84 0x04>; | 310 | interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; |
| 275 | clocks = <&clks IMX6SL_CLK_PWM2>, | 311 | clocks = <&clks IMX6SL_CLK_PWM2>, |
| 276 | <&clks IMX6SL_CLK_PWM2>; | 312 | <&clks IMX6SL_CLK_PWM2>; |
| 277 | clock-names = "ipg", "per"; | 313 | clock-names = "ipg", "per"; |
| @@ -281,7 +317,7 @@ | |||
| 281 | #pwm-cells = <2>; | 317 | #pwm-cells = <2>; |
| 282 | compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; | 318 | compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; |
| 283 | reg = <0x02088000 0x4000>; | 319 | reg = <0x02088000 0x4000>; |
| 284 | interrupts = <0 85 0x04>; | 320 | interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; |
| 285 | clocks = <&clks IMX6SL_CLK_PWM3>, | 321 | clocks = <&clks IMX6SL_CLK_PWM3>, |
| 286 | <&clks IMX6SL_CLK_PWM3>; | 322 | <&clks IMX6SL_CLK_PWM3>; |
| 287 | clock-names = "ipg", "per"; | 323 | clock-names = "ipg", "per"; |
| @@ -291,7 +327,7 @@ | |||
| 291 | #pwm-cells = <2>; | 327 | #pwm-cells = <2>; |
| 292 | compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; | 328 | compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; |
| 293 | reg = <0x0208c000 0x4000>; | 329 | reg = <0x0208c000 0x4000>; |
| 294 | interrupts = <0 86 0x04>; | 330 | interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; |
| 295 | clocks = <&clks IMX6SL_CLK_PWM4>, | 331 | clocks = <&clks IMX6SL_CLK_PWM4>, |
| 296 | <&clks IMX6SL_CLK_PWM4>; | 332 | <&clks IMX6SL_CLK_PWM4>; |
| 297 | clock-names = "ipg", "per"; | 333 | clock-names = "ipg", "per"; |
| @@ -300,7 +336,7 @@ | |||
| 300 | gpt: gpt@02098000 { | 336 | gpt: gpt@02098000 { |
| 301 | compatible = "fsl,imx6sl-gpt"; | 337 | compatible = "fsl,imx6sl-gpt"; |
| 302 | reg = <0x02098000 0x4000>; | 338 | reg = <0x02098000 0x4000>; |
| 303 | interrupts = <0 55 0x04>; | 339 | interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; |
| 304 | clocks = <&clks IMX6SL_CLK_GPT>, | 340 | clocks = <&clks IMX6SL_CLK_GPT>, |
| 305 | <&clks IMX6SL_CLK_GPT_SERIAL>; | 341 | <&clks IMX6SL_CLK_GPT_SERIAL>; |
| 306 | clock-names = "ipg", "per"; | 342 | clock-names = "ipg", "per"; |
| @@ -309,7 +345,8 @@ | |||
| 309 | gpio1: gpio@0209c000 { | 345 | gpio1: gpio@0209c000 { |
| 310 | compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; | 346 | compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; |
| 311 | reg = <0x0209c000 0x4000>; | 347 | reg = <0x0209c000 0x4000>; |
| 312 | interrupts = <0 66 0x04 0 67 0x04>; | 348 | interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, |
| 349 | <0 67 IRQ_TYPE_LEVEL_HIGH>; | ||
| 313 | gpio-controller; | 350 | gpio-controller; |
| 314 | #gpio-cells = <2>; | 351 | #gpio-cells = <2>; |
| 315 | interrupt-controller; | 352 | interrupt-controller; |
| @@ -319,7 +356,8 @@ | |||
| 319 | gpio2: gpio@020a0000 { | 356 | gpio2: gpio@020a0000 { |
| 320 | compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; | 357 | compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; |
| 321 | reg = <0x020a0000 0x4000>; | 358 | reg = <0x020a0000 0x4000>; |
| 322 | interrupts = <0 68 0x04 0 69 0x04>; | 359 | interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, |
| 360 | <0 69 IRQ_TYPE_LEVEL_HIGH>; | ||
| 323 | gpio-controller; | 361 | gpio-controller; |
| 324 | #gpio-cells = <2>; | 362 | #gpio-cells = <2>; |
| 325 | interrupt-controller; | 363 | interrupt-controller; |
| @@ -329,7 +367,8 @@ | |||
| 329 | gpio3: gpio@020a4000 { | 367 | gpio3: gpio@020a4000 { |
| 330 | compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; | 368 | compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; |
| 331 | reg = <0x020a4000 0x4000>; | 369 | reg = <0x020a4000 0x4000>; |
| 332 | interrupts = <0 70 0x04 0 71 0x04>; | 370 | interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, |
| 371 | <0 71 IRQ_TYPE_LEVEL_HIGH>; | ||
| 333 | gpio-controller; | 372 | gpio-controller; |
| 334 | #gpio-cells = <2>; | 373 | #gpio-cells = <2>; |
| 335 | interrupt-controller; | 374 | interrupt-controller; |
| @@ -339,7 +378,8 @@ | |||
| 339 | gpio4: gpio@020a8000 { | 378 | gpio4: gpio@020a8000 { |
| 340 | compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; | 379 | compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; |
| 341 | reg = <0x020a8000 0x4000>; | 380 | reg = <0x020a8000 0x4000>; |
| 342 | interrupts = <0 72 0x04 0 73 0x04>; | 381 | interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, |
| 382 | <0 73 IRQ_TYPE_LEVEL_HIGH>; | ||
| 343 | gpio-controller; | 383 | gpio-controller; |
| 344 | #gpio-cells = <2>; | 384 | #gpio-cells = <2>; |
| 345 | interrupt-controller; | 385 | interrupt-controller; |
| @@ -349,7 +389,8 @@ | |||
| 349 | gpio5: gpio@020ac000 { | 389 | gpio5: gpio@020ac000 { |
| 350 | compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; | 390 | compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; |
| 351 | reg = <0x020ac000 0x4000>; | 391 | reg = <0x020ac000 0x4000>; |
| 352 | interrupts = <0 74 0x04 0 75 0x04>; | 392 | interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, |
| 393 | <0 75 IRQ_TYPE_LEVEL_HIGH>; | ||
| 353 | gpio-controller; | 394 | gpio-controller; |
| 354 | #gpio-cells = <2>; | 395 | #gpio-cells = <2>; |
| 355 | interrupt-controller; | 396 | interrupt-controller; |
| @@ -357,21 +398,23 @@ | |||
| 357 | }; | 398 | }; |
| 358 | 399 | ||
| 359 | kpp: kpp@020b8000 { | 400 | kpp: kpp@020b8000 { |
| 401 | compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp"; | ||
| 360 | reg = <0x020b8000 0x4000>; | 402 | reg = <0x020b8000 0x4000>; |
| 361 | interrupts = <0 82 0x04>; | 403 | interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; |
| 404 | clocks = <&clks IMX6SL_CLK_DUMMY>; | ||
| 362 | }; | 405 | }; |
| 363 | 406 | ||
| 364 | wdog1: wdog@020bc000 { | 407 | wdog1: wdog@020bc000 { |
| 365 | compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; | 408 | compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; |
| 366 | reg = <0x020bc000 0x4000>; | 409 | reg = <0x020bc000 0x4000>; |
| 367 | interrupts = <0 80 0x04>; | 410 | interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; |
| 368 | clocks = <&clks IMX6SL_CLK_DUMMY>; | 411 | clocks = <&clks IMX6SL_CLK_DUMMY>; |
| 369 | }; | 412 | }; |
| 370 | 413 | ||
| 371 | wdog2: wdog@020c0000 { | 414 | wdog2: wdog@020c0000 { |
| 372 | compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; | 415 | compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; |
| 373 | reg = <0x020c0000 0x4000>; | 416 | reg = <0x020c0000 0x4000>; |
| 374 | interrupts = <0 81 0x04>; | 417 | interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; |
| 375 | clocks = <&clks IMX6SL_CLK_DUMMY>; | 418 | clocks = <&clks IMX6SL_CLK_DUMMY>; |
| 376 | status = "disabled"; | 419 | status = "disabled"; |
| 377 | }; | 420 | }; |
| @@ -379,7 +422,8 @@ | |||
| 379 | clks: ccm@020c4000 { | 422 | clks: ccm@020c4000 { |
| 380 | compatible = "fsl,imx6sl-ccm"; | 423 | compatible = "fsl,imx6sl-ccm"; |
| 381 | reg = <0x020c4000 0x4000>; | 424 | reg = <0x020c4000 0x4000>; |
| 382 | interrupts = <0 87 0x04 0 88 0x04>; | 425 | interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, |
| 426 | <0 88 IRQ_TYPE_LEVEL_HIGH>; | ||
| 383 | #clock-cells = <1>; | 427 | #clock-cells = <1>; |
| 384 | }; | 428 | }; |
| 385 | 429 | ||
| @@ -388,7 +432,9 @@ | |||
| 388 | "fsl,imx6q-anatop", | 432 | "fsl,imx6q-anatop", |
| 389 | "syscon", "simple-bus"; | 433 | "syscon", "simple-bus"; |
| 390 | reg = <0x020c8000 0x1000>; | 434 | reg = <0x020c8000 0x1000>; |
| 391 | interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; | 435 | interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, |
| 436 | <0 54 IRQ_TYPE_LEVEL_HIGH>, | ||
| 437 | <0 127 IRQ_TYPE_LEVEL_HIGH>; | ||
| 392 | 438 | ||
| 393 | regulator-1p1@110 { | 439 | regulator-1p1@110 { |
| 394 | compatible = "fsl,anatop-regulator"; | 440 | compatible = "fsl,anatop-regulator"; |
| @@ -434,7 +480,7 @@ | |||
| 434 | 480 | ||
| 435 | reg_arm: regulator-vddcore@140 { | 481 | reg_arm: regulator-vddcore@140 { |
| 436 | compatible = "fsl,anatop-regulator"; | 482 | compatible = "fsl,anatop-regulator"; |
| 437 | regulator-name = "cpu"; | 483 | regulator-name = "vddarm"; |
| 438 | regulator-min-microvolt = <725000>; | 484 | regulator-min-microvolt = <725000>; |
| 439 | regulator-max-microvolt = <1450000>; | 485 | regulator-max-microvolt = <1450000>; |
| 440 | regulator-always-on; | 486 | regulator-always-on; |
| @@ -487,15 +533,17 @@ | |||
| 487 | usbphy1: usbphy@020c9000 { | 533 | usbphy1: usbphy@020c9000 { |
| 488 | compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; | 534 | compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; |
| 489 | reg = <0x020c9000 0x1000>; | 535 | reg = <0x020c9000 0x1000>; |
| 490 | interrupts = <0 44 0x04>; | 536 | interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; |
| 491 | clocks = <&clks IMX6SL_CLK_USBPHY1>; | 537 | clocks = <&clks IMX6SL_CLK_USBPHY1>; |
| 538 | fsl,anatop = <&anatop>; | ||
| 492 | }; | 539 | }; |
| 493 | 540 | ||
| 494 | usbphy2: usbphy@020ca000 { | 541 | usbphy2: usbphy@020ca000 { |
| 495 | compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; | 542 | compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; |
| 496 | reg = <0x020ca000 0x1000>; | 543 | reg = <0x020ca000 0x1000>; |
| 497 | interrupts = <0 45 0x04>; | 544 | interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; |
| 498 | clocks = <&clks IMX6SL_CLK_USBPHY2>; | 545 | clocks = <&clks IMX6SL_CLK_USBPHY2>; |
| 546 | fsl,anatop = <&anatop>; | ||
| 499 | }; | 547 | }; |
| 500 | 548 | ||
| 501 | snvs@020cc000 { | 549 | snvs@020cc000 { |
| @@ -507,31 +555,33 @@ | |||
| 507 | snvs-rtc-lp@34 { | 555 | snvs-rtc-lp@34 { |
| 508 | compatible = "fsl,sec-v4.0-mon-rtc-lp"; | 556 | compatible = "fsl,sec-v4.0-mon-rtc-lp"; |
| 509 | reg = <0x34 0x58>; | 557 | reg = <0x34 0x58>; |
| 510 | interrupts = <0 19 0x04 0 20 0x04>; | 558 | interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, |
| 559 | <0 20 IRQ_TYPE_LEVEL_HIGH>; | ||
| 511 | }; | 560 | }; |
| 512 | }; | 561 | }; |
| 513 | 562 | ||
| 514 | epit1: epit@020d0000 { | 563 | epit1: epit@020d0000 { |
| 515 | reg = <0x020d0000 0x4000>; | 564 | reg = <0x020d0000 0x4000>; |
| 516 | interrupts = <0 56 0x04>; | 565 | interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; |
| 517 | }; | 566 | }; |
| 518 | 567 | ||
| 519 | epit2: epit@020d4000 { | 568 | epit2: epit@020d4000 { |
| 520 | reg = <0x020d4000 0x4000>; | 569 | reg = <0x020d4000 0x4000>; |
| 521 | interrupts = <0 57 0x04>; | 570 | interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; |
| 522 | }; | 571 | }; |
| 523 | 572 | ||
| 524 | src: src@020d8000 { | 573 | src: src@020d8000 { |
| 525 | compatible = "fsl,imx6sl-src", "fsl,imx51-src"; | 574 | compatible = "fsl,imx6sl-src", "fsl,imx51-src"; |
| 526 | reg = <0x020d8000 0x4000>; | 575 | reg = <0x020d8000 0x4000>; |
| 527 | interrupts = <0 91 0x04 0 96 0x04>; | 576 | interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, |
| 577 | <0 96 IRQ_TYPE_LEVEL_HIGH>; | ||
| 528 | #reset-cells = <1>; | 578 | #reset-cells = <1>; |
| 529 | }; | 579 | }; |
| 530 | 580 | ||
| 531 | gpc: gpc@020dc000 { | 581 | gpc: gpc@020dc000 { |
| 532 | compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc"; | 582 | compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc"; |
| 533 | reg = <0x020dc000 0x4000>; | 583 | reg = <0x020dc000 0x4000>; |
| 534 | interrupts = <0 89 0x04>; | 584 | interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; |
| 535 | }; | 585 | }; |
| 536 | 586 | ||
| 537 | gpr: iomuxc-gpr@020e0000 { | 587 | gpr: iomuxc-gpr@020e0000 { |
| @@ -543,235 +593,22 @@ | |||
| 543 | iomuxc: iomuxc@020e0000 { | 593 | iomuxc: iomuxc@020e0000 { |
| 544 | compatible = "fsl,imx6sl-iomuxc"; | 594 | compatible = "fsl,imx6sl-iomuxc"; |
| 545 | reg = <0x020e0000 0x4000>; | 595 | reg = <0x020e0000 0x4000>; |
| 546 | |||
| 547 | ecspi1 { | ||
| 548 | pinctrl_ecspi1_1: ecspi1grp-1 { | ||
| 549 | fsl,pins = < | ||
| 550 | MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1 | ||
| 551 | MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1 | ||
| 552 | MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1 | ||
| 553 | >; | ||
| 554 | }; | ||
| 555 | }; | ||
| 556 | |||
| 557 | fec { | ||
| 558 | pinctrl_fec_1: fecgrp-1 { | ||
| 559 | fsl,pins = < | ||
| 560 | MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0 | ||
| 561 | MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0 | ||
| 562 | MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0 | ||
| 563 | MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0 | ||
| 564 | MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0 | ||
| 565 | MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0 | ||
| 566 | MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0 | ||
| 567 | MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0 | ||
| 568 | MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8 | ||
| 569 | >; | ||
| 570 | }; | ||
| 571 | }; | ||
| 572 | |||
| 573 | uart1 { | ||
| 574 | pinctrl_uart1_1: uart1grp-1 { | ||
| 575 | fsl,pins = < | ||
| 576 | MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 | ||
| 577 | MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 | ||
| 578 | >; | ||
| 579 | }; | ||
| 580 | }; | ||
| 581 | |||
| 582 | usbotg1 { | ||
| 583 | pinctrl_usbotg1_1: usbotg1grp-1 { | ||
| 584 | fsl,pins = < | ||
| 585 | MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 | ||
| 586 | >; | ||
| 587 | }; | ||
| 588 | |||
| 589 | pinctrl_usbotg1_2: usbotg1grp-2 { | ||
| 590 | fsl,pins = < | ||
| 591 | MX6SL_PAD_FEC_RXD0__USB_OTG1_ID 0x17059 | ||
| 592 | >; | ||
| 593 | }; | ||
| 594 | |||
| 595 | pinctrl_usbotg1_3: usbotg1grp-3 { | ||
| 596 | fsl,pins = < | ||
| 597 | MX6SL_PAD_LCD_DAT1__USB_OTG1_ID 0x17059 | ||
| 598 | >; | ||
| 599 | }; | ||
| 600 | |||
| 601 | pinctrl_usbotg1_4: usbotg1grp-4 { | ||
| 602 | fsl,pins = < | ||
| 603 | MX6SL_PAD_REF_CLK_32K__USB_OTG1_ID 0x17059 | ||
| 604 | >; | ||
| 605 | }; | ||
| 606 | |||
| 607 | pinctrl_usbotg1_5: usbotg1grp-5 { | ||
| 608 | fsl,pins = < | ||
| 609 | MX6SL_PAD_SD3_DAT0__USB_OTG1_ID 0x17059 | ||
| 610 | >; | ||
| 611 | }; | ||
| 612 | }; | ||
| 613 | |||
| 614 | usbotg2 { | ||
| 615 | pinctrl_usbotg2_1: usbotg2grp-1 { | ||
| 616 | fsl,pins = < | ||
| 617 | MX6SL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x17059 | ||
| 618 | >; | ||
| 619 | }; | ||
| 620 | |||
| 621 | pinctrl_usbotg2_2: usbotg2grp-2 { | ||
| 622 | fsl,pins = < | ||
| 623 | MX6SL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x17059 | ||
| 624 | >; | ||
| 625 | }; | ||
| 626 | |||
| 627 | pinctrl_usbotg2_3: usbotg2grp-3 { | ||
| 628 | fsl,pins = < | ||
| 629 | MX6SL_PAD_KEY_ROW5__USB_OTG2_OC 0x17059 | ||
| 630 | >; | ||
| 631 | }; | ||
| 632 | |||
| 633 | pinctrl_usbotg2_4: usbotg2grp-4 { | ||
| 634 | fsl,pins = < | ||
| 635 | MX6SL_PAD_SD3_DAT2__USB_OTG2_OC 0x17059 | ||
| 636 | >; | ||
| 637 | }; | ||
| 638 | }; | ||
| 639 | |||
| 640 | usdhc1 { | ||
| 641 | pinctrl_usdhc1_1: usdhc1grp-1 { | ||
| 642 | fsl,pins = < | ||
| 643 | MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059 | ||
| 644 | MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059 | ||
| 645 | MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059 | ||
| 646 | MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059 | ||
| 647 | MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059 | ||
| 648 | MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059 | ||
| 649 | MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059 | ||
| 650 | MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059 | ||
| 651 | MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059 | ||
| 652 | MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059 | ||
| 653 | >; | ||
| 654 | }; | ||
| 655 | |||
| 656 | pinctrl_usdhc1_1_100mhz: usdhc1grp-1-100mhz { | ||
| 657 | fsl,pins = < | ||
| 658 | MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9 | ||
| 659 | MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9 | ||
| 660 | MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9 | ||
| 661 | MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9 | ||
| 662 | MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9 | ||
| 663 | MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9 | ||
| 664 | MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9 | ||
| 665 | MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9 | ||
| 666 | MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9 | ||
| 667 | MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9 | ||
| 668 | >; | ||
| 669 | }; | ||
| 670 | |||
| 671 | pinctrl_usdhc1_1_200mhz: usdhc1grp-1-200mhz { | ||
| 672 | fsl,pins = < | ||
| 673 | MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9 | ||
| 674 | MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9 | ||
| 675 | MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 | ||
| 676 | MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 | ||
| 677 | MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 | ||
| 678 | MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 | ||
| 679 | MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9 | ||
| 680 | MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9 | ||
| 681 | MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9 | ||
| 682 | MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9 | ||
| 683 | >; | ||
| 684 | }; | ||
| 685 | |||
| 686 | |||
| 687 | }; | ||
| 688 | |||
| 689 | usdhc2 { | ||
| 690 | pinctrl_usdhc2_1: usdhc2grp-1 { | ||
| 691 | fsl,pins = < | ||
| 692 | MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 | ||
| 693 | MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059 | ||
| 694 | MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 | ||
| 695 | MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 | ||
| 696 | MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 | ||
| 697 | MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 | ||
| 698 | >; | ||
| 699 | }; | ||
| 700 | |||
| 701 | pinctrl_usdhc2_1_100mhz: usdhc2grp-1-100mhz { | ||
| 702 | fsl,pins = < | ||
| 703 | MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 | ||
| 704 | MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9 | ||
| 705 | MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 | ||
| 706 | MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 | ||
| 707 | MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 | ||
| 708 | MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 | ||
| 709 | >; | ||
| 710 | }; | ||
| 711 | |||
| 712 | pinctrl_usdhc2_1_200mhz: usdhc2grp-1-200mhz { | ||
| 713 | fsl,pins = < | ||
| 714 | MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 | ||
| 715 | MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9 | ||
| 716 | MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 | ||
| 717 | MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 | ||
| 718 | MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 | ||
| 719 | MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 | ||
| 720 | >; | ||
| 721 | }; | ||
| 722 | |||
| 723 | }; | ||
| 724 | |||
| 725 | usdhc3 { | ||
| 726 | pinctrl_usdhc3_1: usdhc3grp-1 { | ||
| 727 | fsl,pins = < | ||
| 728 | MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 729 | MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 730 | MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 731 | MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 732 | MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 733 | MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 734 | >; | ||
| 735 | }; | ||
| 736 | |||
| 737 | pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { | ||
| 738 | fsl,pins = < | ||
| 739 | MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 | ||
| 740 | MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9 | ||
| 741 | MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 | ||
| 742 | MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 | ||
| 743 | MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 | ||
| 744 | MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 | ||
| 745 | >; | ||
| 746 | }; | ||
| 747 | |||
| 748 | pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { | ||
| 749 | fsl,pins = < | ||
| 750 | MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 | ||
| 751 | MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9 | ||
| 752 | MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 | ||
| 753 | MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 | ||
| 754 | MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 | ||
| 755 | MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 | ||
| 756 | >; | ||
| 757 | }; | ||
| 758 | }; | ||
| 759 | }; | 596 | }; |
| 760 | 597 | ||
| 761 | csi: csi@020e4000 { | 598 | csi: csi@020e4000 { |
| 762 | reg = <0x020e4000 0x4000>; | 599 | reg = <0x020e4000 0x4000>; |
| 763 | interrupts = <0 7 0x04>; | 600 | interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; |
| 764 | }; | 601 | }; |
| 765 | 602 | ||
| 766 | spdc: spdc@020e8000 { | 603 | spdc: spdc@020e8000 { |
| 767 | reg = <0x020e8000 0x4000>; | 604 | reg = <0x020e8000 0x4000>; |
| 768 | interrupts = <0 6 0x04>; | 605 | interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; |
| 769 | }; | 606 | }; |
| 770 | 607 | ||
| 771 | sdma: sdma@020ec000 { | 608 | sdma: sdma@020ec000 { |
| 772 | compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma"; | 609 | compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma"; |
| 773 | reg = <0x020ec000 0x4000>; | 610 | reg = <0x020ec000 0x4000>; |
| 774 | interrupts = <0 2 0x04>; | 611 | interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; |
| 775 | clocks = <&clks IMX6SL_CLK_SDMA>, | 612 | clocks = <&clks IMX6SL_CLK_SDMA>, |
| 776 | <&clks IMX6SL_CLK_SDMA>; | 613 | <&clks IMX6SL_CLK_SDMA>; |
| 777 | clock-names = "ipg", "ahb"; | 614 | clock-names = "ipg", "ahb"; |
| @@ -782,22 +619,22 @@ | |||
| 782 | 619 | ||
| 783 | pxp: pxp@020f0000 { | 620 | pxp: pxp@020f0000 { |
| 784 | reg = <0x020f0000 0x4000>; | 621 | reg = <0x020f0000 0x4000>; |
| 785 | interrupts = <0 98 0x04>; | 622 | interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; |
| 786 | }; | 623 | }; |
| 787 | 624 | ||
| 788 | epdc: epdc@020f4000 { | 625 | epdc: epdc@020f4000 { |
| 789 | reg = <0x020f4000 0x4000>; | 626 | reg = <0x020f4000 0x4000>; |
| 790 | interrupts = <0 97 0x04>; | 627 | interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; |
| 791 | }; | 628 | }; |
| 792 | 629 | ||
| 793 | lcdif: lcdif@020f8000 { | 630 | lcdif: lcdif@020f8000 { |
| 794 | reg = <0x020f8000 0x4000>; | 631 | reg = <0x020f8000 0x4000>; |
| 795 | interrupts = <0 39 0x04>; | 632 | interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; |
| 796 | }; | 633 | }; |
| 797 | 634 | ||
| 798 | dcp: dcp@020fc000 { | 635 | dcp: dcp@020fc000 { |
| 799 | reg = <0x020fc000 0x4000>; | 636 | reg = <0x020fc000 0x4000>; |
| 800 | interrupts = <0 99 0x04>; | 637 | interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>; |
| 801 | }; | 638 | }; |
| 802 | }; | 639 | }; |
| 803 | 640 | ||
| @@ -811,7 +648,7 @@ | |||
| 811 | usbotg1: usb@02184000 { | 648 | usbotg1: usb@02184000 { |
| 812 | compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; | 649 | compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; |
| 813 | reg = <0x02184000 0x200>; | 650 | reg = <0x02184000 0x200>; |
| 814 | interrupts = <0 43 0x04>; | 651 | interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; |
| 815 | clocks = <&clks IMX6SL_CLK_USBOH3>; | 652 | clocks = <&clks IMX6SL_CLK_USBOH3>; |
| 816 | fsl,usbphy = <&usbphy1>; | 653 | fsl,usbphy = <&usbphy1>; |
| 817 | fsl,usbmisc = <&usbmisc 0>; | 654 | fsl,usbmisc = <&usbmisc 0>; |
| @@ -821,7 +658,7 @@ | |||
| 821 | usbotg2: usb@02184200 { | 658 | usbotg2: usb@02184200 { |
| 822 | compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; | 659 | compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; |
| 823 | reg = <0x02184200 0x200>; | 660 | reg = <0x02184200 0x200>; |
| 824 | interrupts = <0 42 0x04>; | 661 | interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; |
| 825 | clocks = <&clks IMX6SL_CLK_USBOH3>; | 662 | clocks = <&clks IMX6SL_CLK_USBOH3>; |
| 826 | fsl,usbphy = <&usbphy2>; | 663 | fsl,usbphy = <&usbphy2>; |
| 827 | fsl,usbmisc = <&usbmisc 1>; | 664 | fsl,usbmisc = <&usbmisc 1>; |
| @@ -831,7 +668,7 @@ | |||
| 831 | usbh: usb@02184400 { | 668 | usbh: usb@02184400 { |
| 832 | compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; | 669 | compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; |
| 833 | reg = <0x02184400 0x200>; | 670 | reg = <0x02184400 0x200>; |
| 834 | interrupts = <0 40 0x04>; | 671 | interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; |
| 835 | clocks = <&clks IMX6SL_CLK_USBOH3>; | 672 | clocks = <&clks IMX6SL_CLK_USBOH3>; |
| 836 | fsl,usbmisc = <&usbmisc 2>; | 673 | fsl,usbmisc = <&usbmisc 2>; |
| 837 | status = "disabled"; | 674 | status = "disabled"; |
| @@ -847,7 +684,7 @@ | |||
| 847 | fec: ethernet@02188000 { | 684 | fec: ethernet@02188000 { |
| 848 | compatible = "fsl,imx6sl-fec", "fsl,imx25-fec"; | 685 | compatible = "fsl,imx6sl-fec", "fsl,imx25-fec"; |
| 849 | reg = <0x02188000 0x4000>; | 686 | reg = <0x02188000 0x4000>; |
| 850 | interrupts = <0 114 0x04>; | 687 | interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>; |
| 851 | clocks = <&clks IMX6SL_CLK_ENET_REF>, | 688 | clocks = <&clks IMX6SL_CLK_ENET_REF>, |
| 852 | <&clks IMX6SL_CLK_ENET_REF>; | 689 | <&clks IMX6SL_CLK_ENET_REF>; |
| 853 | clock-names = "ipg", "ahb"; | 690 | clock-names = "ipg", "ahb"; |
| @@ -857,7 +694,7 @@ | |||
| 857 | usdhc1: usdhc@02190000 { | 694 | usdhc1: usdhc@02190000 { |
| 858 | compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; | 695 | compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; |
| 859 | reg = <0x02190000 0x4000>; | 696 | reg = <0x02190000 0x4000>; |
| 860 | interrupts = <0 22 0x04>; | 697 | interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; |
| 861 | clocks = <&clks IMX6SL_CLK_USDHC1>, | 698 | clocks = <&clks IMX6SL_CLK_USDHC1>, |
| 862 | <&clks IMX6SL_CLK_USDHC1>, | 699 | <&clks IMX6SL_CLK_USDHC1>, |
| 863 | <&clks IMX6SL_CLK_USDHC1>; | 700 | <&clks IMX6SL_CLK_USDHC1>; |
| @@ -869,7 +706,7 @@ | |||
| 869 | usdhc2: usdhc@02194000 { | 706 | usdhc2: usdhc@02194000 { |
| 870 | compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; | 707 | compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; |
| 871 | reg = <0x02194000 0x4000>; | 708 | reg = <0x02194000 0x4000>; |
| 872 | interrupts = <0 23 0x04>; | 709 | interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; |
| 873 | clocks = <&clks IMX6SL_CLK_USDHC2>, | 710 | clocks = <&clks IMX6SL_CLK_USDHC2>, |
| 874 | <&clks IMX6SL_CLK_USDHC2>, | 711 | <&clks IMX6SL_CLK_USDHC2>, |
| 875 | <&clks IMX6SL_CLK_USDHC2>; | 712 | <&clks IMX6SL_CLK_USDHC2>; |
| @@ -881,7 +718,7 @@ | |||
| 881 | usdhc3: usdhc@02198000 { | 718 | usdhc3: usdhc@02198000 { |
| 882 | compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; | 719 | compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; |
| 883 | reg = <0x02198000 0x4000>; | 720 | reg = <0x02198000 0x4000>; |
| 884 | interrupts = <0 24 0x04>; | 721 | interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; |
| 885 | clocks = <&clks IMX6SL_CLK_USDHC3>, | 722 | clocks = <&clks IMX6SL_CLK_USDHC3>, |
| 886 | <&clks IMX6SL_CLK_USDHC3>, | 723 | <&clks IMX6SL_CLK_USDHC3>, |
| 887 | <&clks IMX6SL_CLK_USDHC3>; | 724 | <&clks IMX6SL_CLK_USDHC3>; |
| @@ -893,7 +730,7 @@ | |||
| 893 | usdhc4: usdhc@0219c000 { | 730 | usdhc4: usdhc@0219c000 { |
| 894 | compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; | 731 | compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; |
| 895 | reg = <0x0219c000 0x4000>; | 732 | reg = <0x0219c000 0x4000>; |
| 896 | interrupts = <0 25 0x04>; | 733 | interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; |
| 897 | clocks = <&clks IMX6SL_CLK_USDHC4>, | 734 | clocks = <&clks IMX6SL_CLK_USDHC4>, |
| 898 | <&clks IMX6SL_CLK_USDHC4>, | 735 | <&clks IMX6SL_CLK_USDHC4>, |
| 899 | <&clks IMX6SL_CLK_USDHC4>; | 736 | <&clks IMX6SL_CLK_USDHC4>; |
| @@ -907,7 +744,7 @@ | |||
| 907 | #size-cells = <0>; | 744 | #size-cells = <0>; |
| 908 | compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; | 745 | compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; |
| 909 | reg = <0x021a0000 0x4000>; | 746 | reg = <0x021a0000 0x4000>; |
| 910 | interrupts = <0 36 0x04>; | 747 | interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; |
| 911 | clocks = <&clks IMX6SL_CLK_I2C1>; | 748 | clocks = <&clks IMX6SL_CLK_I2C1>; |
| 912 | status = "disabled"; | 749 | status = "disabled"; |
| 913 | }; | 750 | }; |
| @@ -917,7 +754,7 @@ | |||
| 917 | #size-cells = <0>; | 754 | #size-cells = <0>; |
| 918 | compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; | 755 | compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; |
| 919 | reg = <0x021a4000 0x4000>; | 756 | reg = <0x021a4000 0x4000>; |
| 920 | interrupts = <0 37 0x04>; | 757 | interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; |
| 921 | clocks = <&clks IMX6SL_CLK_I2C2>; | 758 | clocks = <&clks IMX6SL_CLK_I2C2>; |
| 922 | status = "disabled"; | 759 | status = "disabled"; |
| 923 | }; | 760 | }; |
| @@ -927,7 +764,7 @@ | |||
| 927 | #size-cells = <0>; | 764 | #size-cells = <0>; |
| 928 | compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; | 765 | compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; |
| 929 | reg = <0x021a8000 0x4000>; | 766 | reg = <0x021a8000 0x4000>; |
| 930 | interrupts = <0 38 0x04>; | 767 | interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; |
| 931 | clocks = <&clks IMX6SL_CLK_I2C3>; | 768 | clocks = <&clks IMX6SL_CLK_I2C3>; |
| 932 | status = "disabled"; | 769 | status = "disabled"; |
| 933 | }; | 770 | }; |
| @@ -939,12 +776,12 @@ | |||
| 939 | 776 | ||
| 940 | rngb: rngb@021b4000 { | 777 | rngb: rngb@021b4000 { |
| 941 | reg = <0x021b4000 0x4000>; | 778 | reg = <0x021b4000 0x4000>; |
| 942 | interrupts = <0 5 0x04>; | 779 | interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; |
| 943 | }; | 780 | }; |
| 944 | 781 | ||
| 945 | weim: weim@021b8000 { | 782 | weim: weim@021b8000 { |
| 946 | reg = <0x021b8000 0x4000>; | 783 | reg = <0x021b8000 0x4000>; |
| 947 | interrupts = <0 14 0x04>; | 784 | interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; |
| 948 | }; | 785 | }; |
| 949 | 786 | ||
| 950 | ocotp: ocotp@021bc000 { | 787 | ocotp: ocotp@021bc000 { |
diff --git a/arch/arm/boot/dts/k2e-clocks.dtsi b/arch/arm/boot/dts/k2e-clocks.dtsi new file mode 100644 index 000000000000..90774d604bc1 --- /dev/null +++ b/arch/arm/boot/dts/k2e-clocks.dtsi | |||
| @@ -0,0 +1,78 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2014 Texas Instruments, Inc. | ||
| 3 | * | ||
| 4 | * Keystone 2 Edison SoC specific device tree | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | clocks { | ||
| 12 | mainpllclk: mainpllclk@2310110 { | ||
| 13 | #clock-cells = <0>; | ||
| 14 | compatible = "ti,keystone,main-pll-clock"; | ||
| 15 | clocks = <&refclksys>; | ||
| 16 | reg = <0x02620350 4>, <0x02310110 4>; | ||
| 17 | reg-names = "control", "multiplier"; | ||
| 18 | fixed-postdiv = <2>; | ||
| 19 | }; | ||
| 20 | |||
| 21 | papllclk: papllclk@2620358 { | ||
| 22 | #clock-cells = <0>; | ||
| 23 | compatible = "ti,keystone,pll-clock"; | ||
| 24 | clocks = <&refclkpass>; | ||
| 25 | clock-output-names = "pa-pll-clk"; | ||
| 26 | reg = <0x02620358 4>; | ||
| 27 | reg-names = "control"; | ||
| 28 | }; | ||
| 29 | |||
| 30 | ddr3apllclk: ddr3apllclk@2620360 { | ||
| 31 | #clock-cells = <0>; | ||
| 32 | compatible = "ti,keystone,pll-clock"; | ||
| 33 | clocks = <&refclkddr3a>; | ||
| 34 | clock-output-names = "ddr-3a-pll-clk"; | ||
| 35 | reg = <0x02620360 4>; | ||
| 36 | reg-names = "control"; | ||
| 37 | }; | ||
| 38 | |||
| 39 | clkusb1: clkusb1 { | ||
| 40 | #clock-cells = <0>; | ||
| 41 | compatible = "ti,keystone,psc-clock"; | ||
| 42 | clocks = <&chipclk16>; | ||
| 43 | clock-output-names = "usb"; | ||
| 44 | reg = <0x02350004 0xb00>, <0x02350000 0x400>; | ||
| 45 | reg-names = "control", "domain"; | ||
| 46 | domain-id = <0>; | ||
| 47 | }; | ||
| 48 | |||
| 49 | clkhyperlink0: clkhyperlink0 { | ||
| 50 | #clock-cells = <0>; | ||
| 51 | compatible = "ti,keystone,psc-clock"; | ||
| 52 | clocks = <&chipclk12>; | ||
| 53 | clock-output-names = "hyperlink-0"; | ||
| 54 | reg = <0x02350030 0xb00>, <0x02350014 0x400>; | ||
| 55 | reg-names = "control", "domain"; | ||
| 56 | domain-id = <5>; | ||
| 57 | }; | ||
| 58 | |||
| 59 | clkpcie1: clkpcie1 { | ||
| 60 | #clock-cells = <0>; | ||
| 61 | compatible = "ti,keystone,psc-clock"; | ||
| 62 | clocks = <&chipclk12>; | ||
| 63 | clock-output-names = "pcie"; | ||
| 64 | reg = <0x0235006c 0xb00>, <0x02350000 0x400>; | ||
| 65 | reg-names = "control", "domain"; | ||
| 66 | domain-id = <18>; | ||
| 67 | }; | ||
| 68 | |||
| 69 | clkxge: clkxge { | ||
| 70 | #clock-cells = <0>; | ||
| 71 | compatible = "ti,keystone,psc-clock"; | ||
| 72 | clocks = <&chipclk13>; | ||
| 73 | clock-output-names = "xge"; | ||
| 74 | reg = <0x023500c8 0xb00>, <0x02350074 0x400>; | ||
| 75 | reg-names = "control", "domain"; | ||
| 76 | domain-id = <29>; | ||
| 77 | }; | ||
| 78 | }; | ||
diff --git a/arch/arm/boot/dts/k2e-evm.dts b/arch/arm/boot/dts/k2e-evm.dts new file mode 100644 index 000000000000..bb8faeb1a2f8 --- /dev/null +++ b/arch/arm/boot/dts/k2e-evm.dts | |||
| @@ -0,0 +1,60 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013-2014 Texas Instruments, Inc. | ||
| 3 | * | ||
| 4 | * Keystone 2 Edison EVM device tree | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | /dts-v1/; | ||
| 11 | |||
| 12 | #include "keystone.dtsi" | ||
| 13 | #include "k2e.dtsi" | ||
| 14 | |||
| 15 | / { | ||
| 16 | compatible = "ti,k2e-evm"; | ||
| 17 | model = "Texas Instruments Keystone 2 Edison EVM"; | ||
| 18 | |||
| 19 | soc { | ||
| 20 | |||
| 21 | clocks { | ||
| 22 | refclksys: refclksys { | ||
| 23 | #clock-cells = <0>; | ||
| 24 | compatible = "fixed-clock"; | ||
| 25 | clock-frequency = <100000000>; | ||
| 26 | clock-output-names = "refclk-sys"; | ||
| 27 | }; | ||
| 28 | |||
| 29 | refclkpass: refclkpass { | ||
| 30 | #clock-cells = <0>; | ||
| 31 | compatible = "fixed-clock"; | ||
| 32 | clock-frequency = <100000000>; | ||
| 33 | clock-output-names = "refclk-pass"; | ||
| 34 | }; | ||
| 35 | |||
| 36 | refclkddr3a: refclkddr3a { | ||
| 37 | #clock-cells = <0>; | ||
| 38 | compatible = "fixed-clock"; | ||
| 39 | clock-frequency = <100000000>; | ||
| 40 | clock-output-names = "refclk-ddr3a"; | ||
| 41 | }; | ||
| 42 | }; | ||
| 43 | }; | ||
| 44 | }; | ||
| 45 | |||
| 46 | &usb_phy { | ||
| 47 | status = "okay"; | ||
| 48 | }; | ||
| 49 | |||
| 50 | &usb { | ||
| 51 | status = "okay"; | ||
| 52 | }; | ||
| 53 | |||
| 54 | &usb1_phy { | ||
| 55 | status = "okay"; | ||
| 56 | }; | ||
| 57 | |||
| 58 | &usb1 { | ||
| 59 | status = "okay"; | ||
| 60 | }; | ||
diff --git a/arch/arm/boot/dts/k2e.dtsi b/arch/arm/boot/dts/k2e.dtsi new file mode 100644 index 000000000000..03d01909525b --- /dev/null +++ b/arch/arm/boot/dts/k2e.dtsi | |||
| @@ -0,0 +1,80 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013-2014 Texas Instruments, Inc. | ||
| 3 | * | ||
| 4 | * Keystone 2 Edison soc device tree | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | / { | ||
| 12 | cpus { | ||
| 13 | #address-cells = <1>; | ||
| 14 | #size-cells = <0>; | ||
| 15 | |||
| 16 | interrupt-parent = <&gic>; | ||
| 17 | |||
| 18 | cpu@0 { | ||
| 19 | compatible = "arm,cortex-a15"; | ||
| 20 | device_type = "cpu"; | ||
| 21 | reg = <0>; | ||
| 22 | }; | ||
| 23 | |||
| 24 | cpu@1 { | ||
| 25 | compatible = "arm,cortex-a15"; | ||
| 26 | device_type = "cpu"; | ||
| 27 | reg = <1>; | ||
| 28 | }; | ||
| 29 | |||
| 30 | cpu@2 { | ||
| 31 | compatible = "arm,cortex-a15"; | ||
| 32 | device_type = "cpu"; | ||
| 33 | reg = <2>; | ||
| 34 | }; | ||
| 35 | |||
| 36 | cpu@3 { | ||
| 37 | compatible = "arm,cortex-a15"; | ||
| 38 | device_type = "cpu"; | ||
| 39 | reg = <3>; | ||
| 40 | }; | ||
| 41 | }; | ||
| 42 | |||
| 43 | soc { | ||
| 44 | /include/ "k2e-clocks.dtsi" | ||
| 45 | |||
| 46 | usb: usb@2680000 { | ||
| 47 | interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>; | ||
| 48 | dwc3@2690000 { | ||
| 49 | interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>; | ||
| 50 | }; | ||
| 51 | }; | ||
| 52 | |||
| 53 | usb1_phy: usb_phy@2620750 { | ||
| 54 | compatible = "ti,keystone-usbphy"; | ||
| 55 | #address-cells = <1>; | ||
| 56 | #size-cells = <1>; | ||
| 57 | reg = <0x2620750 24>; | ||
| 58 | status = "disabled"; | ||
| 59 | }; | ||
| 60 | |||
| 61 | usb1: usb@25000000 { | ||
| 62 | compatible = "ti,keystone-dwc3"; | ||
| 63 | #address-cells = <1>; | ||
| 64 | #size-cells = <1>; | ||
| 65 | reg = <0x25000000 0x10000>; | ||
| 66 | clocks = <&clkusb1>; | ||
| 67 | clock-names = "usb"; | ||
| 68 | interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>; | ||
| 69 | ranges; | ||
| 70 | status = "disabled"; | ||
| 71 | |||
| 72 | dwc3@25010000 { | ||
| 73 | compatible = "synopsys,dwc3"; | ||
| 74 | reg = <0x25010000 0x70000>; | ||
| 75 | interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>; | ||
| 76 | usb-phy = <&usb1_phy>, <&usb1_phy>; | ||
| 77 | }; | ||
| 78 | }; | ||
| 79 | }; | ||
| 80 | }; | ||
diff --git a/arch/arm/boot/dts/k2hk-clocks.dtsi b/arch/arm/boot/dts/k2hk-clocks.dtsi new file mode 100644 index 000000000000..a71aa2996321 --- /dev/null +++ b/arch/arm/boot/dts/k2hk-clocks.dtsi | |||
| @@ -0,0 +1,426 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013-2014 Texas Instruments, Inc. | ||
| 3 | * | ||
| 4 | * Keystone 2 Kepler/Hawking SoC clock nodes | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | clocks { | ||
| 12 | armpllclk: armpllclk@2620370 { | ||
| 13 | #clock-cells = <0>; | ||
| 14 | compatible = "ti,keystone,pll-clock"; | ||
| 15 | clocks = <&refclkarm>; | ||
| 16 | clock-output-names = "arm-pll-clk"; | ||
| 17 | reg = <0x02620370 4>; | ||
| 18 | reg-names = "control"; | ||
| 19 | }; | ||
| 20 | |||
| 21 | mainpllclk: mainpllclk@2310110 { | ||
| 22 | #clock-cells = <0>; | ||
| 23 | compatible = "ti,keystone,main-pll-clock"; | ||
| 24 | clocks = <&refclksys>; | ||
| 25 | reg = <0x02620350 4>, <0x02310110 4>; | ||
| 26 | reg-names = "control", "multiplier"; | ||
| 27 | fixed-postdiv = <2>; | ||
| 28 | }; | ||
| 29 | |||
| 30 | papllclk: papllclk@2620358 { | ||
| 31 | #clock-cells = <0>; | ||
| 32 | compatible = "ti,keystone,pll-clock"; | ||
| 33 | clocks = <&refclkpass>; | ||
| 34 | clock-output-names = "pa-pll-clk"; | ||
| 35 | reg = <0x02620358 4>; | ||
| 36 | reg-names = "control"; | ||
| 37 | }; | ||
| 38 | |||
| 39 | ddr3apllclk: ddr3apllclk@2620360 { | ||
| 40 | #clock-cells = <0>; | ||
| 41 | compatible = "ti,keystone,pll-clock"; | ||
| 42 | clocks = <&refclkddr3a>; | ||
| 43 | clock-output-names = "ddr-3a-pll-clk"; | ||
| 44 | reg = <0x02620360 4>; | ||
| 45 | reg-names = "control"; | ||
| 46 | }; | ||
| 47 | |||
| 48 | ddr3bpllclk: ddr3bpllclk@2620368 { | ||
| 49 | #clock-cells = <0>; | ||
| 50 | compatible = "ti,keystone,pll-clock"; | ||
| 51 | clocks = <&refclkddr3b>; | ||
| 52 | clock-output-names = "ddr-3b-pll-clk"; | ||
| 53 | reg = <0x02620368 4>; | ||
| 54 | reg-names = "control"; | ||
| 55 | }; | ||
| 56 | |||
| 57 | clktsip: clktsip { | ||
| 58 | #clock-cells = <0>; | ||
| 59 | compatible = "ti,keystone,psc-clock"; | ||
| 60 | clocks = <&chipclk16>; | ||
| 61 | clock-output-names = "tsip"; | ||
| 62 | reg = <0x0235000c 0xb00>, <0x02350000 0x400>; | ||
| 63 | reg-names = "control", "domain"; | ||
| 64 | domain-id = <0>; | ||
| 65 | }; | ||
| 66 | |||
| 67 | clksrio: clksrio { | ||
| 68 | #clock-cells = <0>; | ||
| 69 | compatible = "ti,keystone,psc-clock"; | ||
| 70 | clocks = <&chipclk1rstiso13>; | ||
| 71 | clock-output-names = "srio"; | ||
| 72 | reg = <0x0235002c 0xb00>, <0x02350010 0x400>; | ||
| 73 | reg-names = "control", "domain"; | ||
| 74 | domain-id = <4>; | ||
| 75 | }; | ||
| 76 | |||
| 77 | clkhyperlink0: clkhyperlink0 { | ||
| 78 | #clock-cells = <0>; | ||
| 79 | compatible = "ti,keystone,psc-clock"; | ||
| 80 | clocks = <&chipclk12>; | ||
| 81 | clock-output-names = "hyperlink-0"; | ||
| 82 | reg = <0x02350030 0xb00>, <0x02350014 0x400>; | ||
| 83 | reg-names = "control", "domain"; | ||
| 84 | domain-id = <5>; | ||
| 85 | }; | ||
| 86 | |||
| 87 | clkgem1: clkgem1 { | ||
| 88 | #clock-cells = <0>; | ||
| 89 | compatible = "ti,keystone,psc-clock"; | ||
| 90 | clocks = <&chipclk1>; | ||
| 91 | clock-output-names = "gem1"; | ||
| 92 | reg = <0x02350040 0xb00>, <0x02350024 0x400>; | ||
| 93 | reg-names = "control", "domain"; | ||
| 94 | domain-id = <9>; | ||
| 95 | }; | ||
| 96 | |||
| 97 | clkgem2: clkgem2 { | ||
| 98 | #clock-cells = <0>; | ||
| 99 | compatible = "ti,keystone,psc-clock"; | ||
| 100 | clocks = <&chipclk1>; | ||
| 101 | clock-output-names = "gem2"; | ||
| 102 | reg = <0x02350044 0xb00>, <0x02350028 0x400>; | ||
| 103 | reg-names = "control", "domain"; | ||
| 104 | domain-id = <10>; | ||
| 105 | }; | ||
| 106 | |||
| 107 | clkgem3: clkgem3 { | ||
| 108 | #clock-cells = <0>; | ||
| 109 | compatible = "ti,keystone,psc-clock"; | ||
| 110 | clocks = <&chipclk1>; | ||
| 111 | clock-output-names = "gem3"; | ||
| 112 | reg = <0x02350048 0xb00>, <0x0235002c 0x400>; | ||
| 113 | reg-names = "control", "domain"; | ||
| 114 | domain-id = <11>; | ||
| 115 | }; | ||
| 116 | |||
| 117 | clkgem4: clkgem4 { | ||
| 118 | #clock-cells = <0>; | ||
| 119 | compatible = "ti,keystone,psc-clock"; | ||
| 120 | clocks = <&chipclk1>; | ||
| 121 | clock-output-names = "gem4"; | ||
| 122 | reg = <0x0235004c 0xb00>, <0x02350030 0x400>; | ||
| 123 | reg-names = "control", "domain"; | ||
| 124 | domain-id = <12>; | ||
| 125 | }; | ||
| 126 | |||
| 127 | clkgem5: clkgem5 { | ||
| 128 | #clock-cells = <0>; | ||
| 129 | compatible = "ti,keystone,psc-clock"; | ||
| 130 | clocks = <&chipclk1>; | ||
| 131 | clock-output-names = "gem5"; | ||
| 132 | reg = <0x02350050 0xb00>, <0x02350034 0x400>; | ||
| 133 | reg-names = "control", "domain"; | ||
| 134 | domain-id = <13>; | ||
| 135 | }; | ||
| 136 | |||
| 137 | clkgem6: clkgem6 { | ||
| 138 | #clock-cells = <0>; | ||
| 139 | compatible = "ti,keystone,psc-clock"; | ||
| 140 | clocks = <&chipclk1>; | ||
| 141 | clock-output-names = "gem6"; | ||
| 142 | reg = <0x02350054 0xb00>, <0x02350038 0x400>; | ||
| 143 | reg-names = "control", "domain"; | ||
| 144 | domain-id = <14>; | ||
| 145 | }; | ||
| 146 | |||
| 147 | clkgem7: clkgem7 { | ||
| 148 | #clock-cells = <0>; | ||
| 149 | compatible = "ti,keystone,psc-clock"; | ||
| 150 | clocks = <&chipclk1>; | ||
| 151 | clock-output-names = "gem7"; | ||
| 152 | reg = <0x02350058 0xb00>, <0x0235003c 0x400>; | ||
| 153 | reg-names = "control", "domain"; | ||
| 154 | domain-id = <15>; | ||
| 155 | }; | ||
| 156 | |||
| 157 | clkddr31: clkddr31 { | ||
| 158 | #clock-cells = <0>; | ||
| 159 | compatible = "ti,keystone,psc-clock"; | ||
| 160 | clocks = <&chipclk13>; | ||
| 161 | clock-output-names = "ddr3-1"; | ||
| 162 | reg = <0x02350060 0xb00>, <0x02350040 0x400>; | ||
| 163 | reg-names = "control", "domain"; | ||
| 164 | domain-id = <16>; | ||
| 165 | }; | ||
| 166 | |||
| 167 | clktac: clktac { | ||
| 168 | #clock-cells = <0>; | ||
| 169 | compatible = "ti,keystone,psc-clock"; | ||
| 170 | clocks = <&chipclk13>; | ||
| 171 | clock-output-names = "tac"; | ||
| 172 | reg = <0x02350064 0xb00>, <0x02350044 0x400>; | ||
| 173 | reg-names = "control", "domain"; | ||
| 174 | domain-id = <17>; | ||
| 175 | }; | ||
| 176 | |||
| 177 | clkrac01: clkrac01 { | ||
| 178 | #clock-cells = <0>; | ||
| 179 | compatible = "ti,keystone,psc-clock"; | ||
| 180 | clocks = <&chipclk13>; | ||
| 181 | clock-output-names = "rac-01"; | ||
| 182 | reg = <0x02350068 0xb00>, <0x02350044 0x400>; | ||
| 183 | reg-names = "control", "domain"; | ||
| 184 | domain-id = <17>; | ||
| 185 | }; | ||
| 186 | |||
| 187 | clkrac23: clkrac23 { | ||
| 188 | #clock-cells = <0>; | ||
| 189 | compatible = "ti,keystone,psc-clock"; | ||
| 190 | clocks = <&chipclk13>; | ||
| 191 | clock-output-names = "rac-23"; | ||
| 192 | reg = <0x0235006c 0xb00>, <0x02350048 0x400>; | ||
| 193 | reg-names = "control", "domain"; | ||
| 194 | domain-id = <18>; | ||
| 195 | }; | ||
| 196 | |||
| 197 | clkfftc0: clkfftc0 { | ||
| 198 | #clock-cells = <0>; | ||
| 199 | compatible = "ti,keystone,psc-clock"; | ||
| 200 | clocks = <&chipclk13>; | ||
| 201 | clock-output-names = "fftc-0"; | ||
| 202 | reg = <0x02350070 0xb00>, <0x0235004c 0x400>; | ||
| 203 | reg-names = "control", "domain"; | ||
| 204 | domain-id = <19>; | ||
| 205 | }; | ||
| 206 | |||
| 207 | clkfftc1: clkfftc1 { | ||
| 208 | #clock-cells = <0>; | ||
| 209 | compatible = "ti,keystone,psc-clock"; | ||
| 210 | clocks = <&chipclk13>; | ||
| 211 | clock-output-names = "fftc-1"; | ||
| 212 | reg = <0x02350074 0xb00>, <0x023504c0 0x400>; | ||
| 213 | reg-names = "control", "domain"; | ||
| 214 | domain-id = <19>; | ||
| 215 | }; | ||
| 216 | |||
| 217 | clkfftc2: clkfftc2 { | ||
| 218 | #clock-cells = <0>; | ||
| 219 | compatible = "ti,keystone,psc-clock"; | ||
| 220 | clocks = <&chipclk13>; | ||
| 221 | clock-output-names = "fftc-2"; | ||
| 222 | reg = <0x02350078 0xb00>, <0x02350050 0x400>; | ||
| 223 | reg-names = "control", "domain"; | ||
| 224 | domain-id = <20>; | ||
| 225 | }; | ||
| 226 | |||
| 227 | clkfftc3: clkfftc3 { | ||
| 228 | #clock-cells = <0>; | ||
| 229 | compatible = "ti,keystone,psc-clock"; | ||
| 230 | clocks = <&chipclk13>; | ||
| 231 | clock-output-names = "fftc-3"; | ||
| 232 | reg = <0x0235007c 0xb00>, <0x02350050 0x400>; | ||
| 233 | reg-names = "control", "domain"; | ||
| 234 | domain-id = <20>; | ||
| 235 | }; | ||
| 236 | |||
| 237 | clkfftc4: clkfftc4 { | ||
| 238 | #clock-cells = <0>; | ||
| 239 | compatible = "ti,keystone,psc-clock"; | ||
| 240 | clocks = <&chipclk13>; | ||
| 241 | clock-output-names = "fftc-4"; | ||
| 242 | reg = <0x02350080 0xb00>, <0x02350050 0x400>; | ||
| 243 | reg-names = "control", "domain"; | ||
| 244 | domain-id = <20>; | ||
| 245 | }; | ||
| 246 | |||
| 247 | clkfftc5: clkfftc5 { | ||
| 248 | #clock-cells = <0>; | ||
| 249 | compatible = "ti,keystone,psc-clock"; | ||
| 250 | clocks = <&chipclk13>; | ||
| 251 | clock-output-names = "fftc-5"; | ||
| 252 | reg = <0x02350084 0xb00>, <0x02350050 0x400>; | ||
| 253 | reg-names = "control", "domain"; | ||
| 254 | domain-id = <20>; | ||
| 255 | }; | ||
| 256 | |||
| 257 | clkaif: clkaif { | ||
| 258 | #clock-cells = <0>; | ||
| 259 | compatible = "ti,keystone,psc-clock"; | ||
| 260 | clocks = <&chipclk13>; | ||
| 261 | clock-output-names = "aif"; | ||
| 262 | reg = <0x02350088 0xb00>, <0x02350054 0x400>; | ||
| 263 | reg-names = "control", "domain"; | ||
| 264 | domain-id = <21>; | ||
| 265 | }; | ||
| 266 | |||
| 267 | clktcp3d0: clktcp3d0 { | ||
| 268 | #clock-cells = <0>; | ||
| 269 | compatible = "ti,keystone,psc-clock"; | ||
| 270 | clocks = <&chipclk13>; | ||
| 271 | clock-output-names = "tcp3d-0"; | ||
| 272 | reg = <0x0235008c 0xb00>, <0x02350058 0x400>; | ||
| 273 | reg-names = "control", "domain"; | ||
| 274 | domain-id = <22>; | ||
| 275 | }; | ||
| 276 | |||
| 277 | clktcp3d1: clktcp3d1 { | ||
| 278 | #clock-cells = <0>; | ||
| 279 | compatible = "ti,keystone,psc-clock"; | ||
| 280 | clocks = <&chipclk13>; | ||
| 281 | clock-output-names = "tcp3d-1"; | ||
| 282 | reg = <0x02350090 0xb00>, <0x02350058 0x400>; | ||
| 283 | reg-names = "control", "domain"; | ||
| 284 | domain-id = <22>; | ||
| 285 | }; | ||
| 286 | |||
| 287 | clktcp3d2: clktcp3d2 { | ||
| 288 | #clock-cells = <0>; | ||
| 289 | compatible = "ti,keystone,psc-clock"; | ||
| 290 | clocks = <&chipclk13>; | ||
| 291 | clock-output-names = "tcp3d-2"; | ||
| 292 | reg = <0x02350094 0xb00>, <0x0235005c 0x400>; | ||
| 293 | reg-names = "control", "domain"; | ||
| 294 | domain-id = <23>; | ||
| 295 | }; | ||
| 296 | |||
| 297 | clktcp3d3: clktcp3d3 { | ||
| 298 | #clock-cells = <0>; | ||
| 299 | compatible = "ti,keystone,psc-clock"; | ||
| 300 | clocks = <&chipclk13>; | ||
| 301 | clock-output-names = "tcp3d-3"; | ||
| 302 | reg = <0x02350098 0xb00>, <0x0235005c 0x400>; | ||
| 303 | reg-names = "control", "domain"; | ||
| 304 | domain-id = <23>; | ||
| 305 | }; | ||
| 306 | |||
| 307 | clkvcp0: clkvcp0 { | ||
| 308 | #clock-cells = <0>; | ||
| 309 | compatible = "ti,keystone,psc-clock"; | ||
| 310 | clocks = <&chipclk13>; | ||
| 311 | clock-output-names = "vcp-0"; | ||
| 312 | reg = <0x0235009c 0xb00>, <0x02350060 0x400>; | ||
| 313 | reg-names = "control", "domain"; | ||
| 314 | domain-id = <24>; | ||
| 315 | }; | ||
| 316 | |||
| 317 | clkvcp1: clkvcp1 { | ||
| 318 | #clock-cells = <0>; | ||
| 319 | compatible = "ti,keystone,psc-clock"; | ||
| 320 | clocks = <&chipclk13>; | ||
| 321 | clock-output-names = "vcp-1"; | ||
| 322 | reg = <0x023500a0 0xb00>, <0x02350060 0x400>; | ||
| 323 | reg-names = "control", "domain"; | ||
| 324 | domain-id = <24>; | ||
| 325 | }; | ||
| 326 | |||
| 327 | clkvcp2: clkvcp2 { | ||
| 328 | #clock-cells = <0>; | ||
| 329 | compatible = "ti,keystone,psc-clock"; | ||
| 330 | clocks = <&chipclk13>; | ||
| 331 | clock-output-names = "vcp-2"; | ||
| 332 | reg = <0x023500a4 0xb00>, <0x02350060 0x400>; | ||
| 333 | reg-names = "control", "domain"; | ||
| 334 | domain-id = <24>; | ||
| 335 | }; | ||
| 336 | |||
| 337 | clkvcp3: clkvcp3 { | ||
| 338 | #clock-cells = <0>; | ||
| 339 | compatible = "ti,keystone,psc-clock"; | ||
| 340 | clocks = <&chipclk13>; | ||
| 341 | clock-output-names = "vcp-3"; | ||
| 342 | reg = <0x023500a8 0xb00>, <0x02350060 0x400>; | ||
| 343 | reg-names = "control", "domain"; | ||
| 344 | domain-id = <24>; | ||
| 345 | }; | ||
| 346 | |||
| 347 | clkvcp4: clkvcp4 { | ||
| 348 | #clock-cells = <0>; | ||
| 349 | compatible = "ti,keystone,psc-clock"; | ||
| 350 | clocks = <&chipclk13>; | ||
| 351 | clock-output-names = "vcp-4"; | ||
| 352 | reg = <0x023500ac 0xb00>, <0x02350064 0x400>; | ||
| 353 | reg-names = "control", "domain"; | ||
| 354 | domain-id = <25>; | ||
| 355 | }; | ||
| 356 | |||
| 357 | clkvcp5: clkvcp5 { | ||
| 358 | #clock-cells = <0>; | ||
| 359 | compatible = "ti,keystone,psc-clock"; | ||
| 360 | clocks = <&chipclk13>; | ||
| 361 | clock-output-names = "vcp-5"; | ||
| 362 | reg = <0x023500b0 0xb00>, <0x02350064 0x400>; | ||
| 363 | reg-names = "control", "domain"; | ||
| 364 | domain-id = <25>; | ||
| 365 | }; | ||
| 366 | |||
| 367 | clkvcp6: clkvcp6 { | ||
| 368 | #clock-cells = <0>; | ||
| 369 | compatible = "ti,keystone,psc-clock"; | ||
| 370 | clocks = <&chipclk13>; | ||
| 371 | clock-output-names = "vcp-6"; | ||
| 372 | reg = <0x023500b4 0xb00>, <0x02350064 0x400>; | ||
| 373 | reg-names = "control", "domain"; | ||
| 374 | domain-id = <25>; | ||
| 375 | }; | ||
| 376 | |||
| 377 | clkvcp7: clkvcp7 { | ||
| 378 | #clock-cells = <0>; | ||
| 379 | compatible = "ti,keystone,psc-clock"; | ||
| 380 | clocks = <&chipclk13>; | ||
| 381 | clock-output-names = "vcp-7"; | ||
| 382 | reg = <0x023500b8 0xb00>, <0x02350064 0x400>; | ||
| 383 | reg-names = "control", "domain"; | ||
| 384 | domain-id = <25>; | ||
| 385 | }; | ||
| 386 | |||
| 387 | clkbcp: clkbcp { | ||
| 388 | #clock-cells = <0>; | ||
| 389 | compatible = "ti,keystone,psc-clock"; | ||
| 390 | clocks = <&chipclk13>; | ||
| 391 | clock-output-names = "bcp"; | ||
| 392 | reg = <0x023500bc 0xb00>, <0x02350068 0x400>; | ||
| 393 | reg-names = "control", "domain"; | ||
| 394 | domain-id = <26>; | ||
| 395 | }; | ||
| 396 | |||
| 397 | clkdxb: clkdxb { | ||
| 398 | #clock-cells = <0>; | ||
| 399 | compatible = "ti,keystone,psc-clock"; | ||
| 400 | clocks = <&chipclk13>; | ||
| 401 | clock-output-names = "dxb"; | ||
| 402 | reg = <0x023500c0 0xb00>, <0x0235006c 0x400>; | ||
| 403 | reg-names = "control", "domain"; | ||
| 404 | domain-id = <27>; | ||
| 405 | }; | ||
| 406 | |||
| 407 | clkhyperlink1: clkhyperlink1 { | ||
| 408 | #clock-cells = <0>; | ||
| 409 | compatible = "ti,keystone,psc-clock"; | ||
| 410 | clocks = <&chipclk12>; | ||
| 411 | clock-output-names = "hyperlink-1"; | ||
| 412 | reg = <0x023500c4 0xb00>, <0x02350070 0x400>; | ||
| 413 | reg-names = "control", "domain"; | ||
| 414 | domain-id = <28>; | ||
| 415 | }; | ||
| 416 | |||
| 417 | clkxge: clkxge { | ||
| 418 | #clock-cells = <0>; | ||
| 419 | compatible = "ti,keystone,psc-clock"; | ||
| 420 | clocks = <&chipclk13>; | ||
| 421 | clock-output-names = "xge"; | ||
| 422 | reg = <0x023500c8 0xb00>, <0x02350074 0x400>; | ||
| 423 | reg-names = "control", "domain"; | ||
| 424 | domain-id = <29>; | ||
| 425 | }; | ||
| 426 | }; | ||
diff --git a/arch/arm/boot/dts/k2hk-evm.dts b/arch/arm/boot/dts/k2hk-evm.dts index eaefdfef65c3..1a1335b4a0b1 100644 --- a/arch/arm/boot/dts/k2hk-evm.dts +++ b/arch/arm/boot/dts/k2hk-evm.dts | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright 2013 Texas Instruments, Inc. | 2 | * Copyright 2013-2014 Texas Instruments, Inc. |
| 3 | * | 3 | * |
| 4 | * Keystone 2 Kepler/Hawking EVM device tree | 4 | * Keystone 2 Kepler/Hawking EVM device tree |
| 5 | * | 5 | * |
| @@ -10,12 +10,14 @@ | |||
| 10 | /dts-v1/; | 10 | /dts-v1/; |
| 11 | 11 | ||
| 12 | #include "keystone.dtsi" | 12 | #include "keystone.dtsi" |
| 13 | #include "k2hk.dtsi" | ||
| 13 | 14 | ||
| 14 | / { | 15 | / { |
| 15 | compatible = "ti,keystone-evm"; | 16 | compatible = "ti,k2hk-evm"; |
| 17 | model = "Texas Instruments Keystone 2 Kepler/Hawking EVM"; | ||
| 16 | 18 | ||
| 17 | soc { | 19 | soc { |
| 18 | clock { | 20 | clocks { |
| 19 | refclksys: refclksys { | 21 | refclksys: refclksys { |
| 20 | #clock-cells = <0>; | 22 | #clock-cells = <0>; |
| 21 | compatible = "fixed-clock"; | 23 | compatible = "fixed-clock"; |
| @@ -52,6 +54,29 @@ | |||
| 52 | }; | 54 | }; |
| 53 | }; | 55 | }; |
| 54 | }; | 56 | }; |
| 57 | |||
| 58 | leds { | ||
| 59 | compatible = "gpio-leds"; | ||
| 60 | debug1_1 { | ||
| 61 | label = "keystone:green:debug1"; | ||
| 62 | gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */ | ||
| 63 | }; | ||
| 64 | |||
| 65 | debug1_2 { | ||
| 66 | label = "keystone:red:debug1"; | ||
| 67 | gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */ | ||
| 68 | }; | ||
| 69 | |||
| 70 | debug2 { | ||
| 71 | label = "keystone:blue:debug2"; | ||
| 72 | gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */ | ||
| 73 | }; | ||
| 74 | |||
| 75 | debug3 { | ||
| 76 | label = "keystone:blue:debug3"; | ||
| 77 | gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */ | ||
| 78 | }; | ||
| 79 | }; | ||
| 55 | }; | 80 | }; |
| 56 | 81 | ||
| 57 | &usb_phy { | 82 | &usb_phy { |
| @@ -61,3 +86,55 @@ | |||
| 61 | &usb { | 86 | &usb { |
| 62 | status = "okay"; | 87 | status = "okay"; |
| 63 | }; | 88 | }; |
| 89 | |||
| 90 | &aemif { | ||
| 91 | cs0 { | ||
| 92 | #address-cells = <2>; | ||
| 93 | #size-cells = <1>; | ||
| 94 | clock-ranges; | ||
| 95 | ranges; | ||
| 96 | |||
| 97 | ti,cs-chipselect = <0>; | ||
| 98 | /* all timings in nanoseconds */ | ||
| 99 | ti,cs-min-turnaround-ns = <12>; | ||
| 100 | ti,cs-read-hold-ns = <6>; | ||
| 101 | ti,cs-read-strobe-ns = <23>; | ||
| 102 | ti,cs-read-setup-ns = <9>; | ||
| 103 | ti,cs-write-hold-ns = <8>; | ||
| 104 | ti,cs-write-strobe-ns = <23>; | ||
| 105 | ti,cs-write-setup-ns = <8>; | ||
| 106 | |||
| 107 | nand@0,0 { | ||
| 108 | compatible = "ti,keystone-nand","ti,davinci-nand"; | ||
| 109 | #address-cells = <1>; | ||
| 110 | #size-cells = <1>; | ||
| 111 | reg = <0 0 0x4000000 | ||
| 112 | 1 0 0x0000100>; | ||
| 113 | |||
| 114 | ti,davinci-chipselect = <0>; | ||
| 115 | ti,davinci-mask-ale = <0x2000>; | ||
| 116 | ti,davinci-mask-cle = <0x4000>; | ||
| 117 | ti,davinci-mask-chipsel = <0>; | ||
| 118 | nand-ecc-mode = "hw"; | ||
| 119 | ti,davinci-ecc-bits = <4>; | ||
| 120 | nand-on-flash-bbt; | ||
| 121 | |||
| 122 | partition@0 { | ||
| 123 | label = "u-boot"; | ||
| 124 | reg = <0x0 0x100000>; | ||
| 125 | read-only; | ||
| 126 | }; | ||
| 127 | |||
| 128 | partition@100000 { | ||
| 129 | label = "params"; | ||
| 130 | reg = <0x100000 0x80000>; | ||
| 131 | read-only; | ||
| 132 | }; | ||
| 133 | |||
| 134 | partition@180000 { | ||
| 135 | label = "ubifs"; | ||
| 136 | reg = <0x180000 0x7E80000>; | ||
| 137 | }; | ||
| 138 | }; | ||
| 139 | }; | ||
| 140 | }; | ||
diff --git a/arch/arm/boot/dts/k2hk.dtsi b/arch/arm/boot/dts/k2hk.dtsi new file mode 100644 index 000000000000..c73899c73118 --- /dev/null +++ b/arch/arm/boot/dts/k2hk.dtsi | |||
| @@ -0,0 +1,46 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013-2014 Texas Instruments, Inc. | ||
| 3 | * | ||
| 4 | * Keystone 2 Kepler/Hawking soc specific device tree | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | / { | ||
| 12 | cpus { | ||
| 13 | #address-cells = <1>; | ||
| 14 | #size-cells = <0>; | ||
| 15 | |||
| 16 | interrupt-parent = <&gic>; | ||
| 17 | |||
| 18 | cpu@0 { | ||
| 19 | compatible = "arm,cortex-a15"; | ||
| 20 | device_type = "cpu"; | ||
| 21 | reg = <0>; | ||
| 22 | }; | ||
| 23 | |||
| 24 | cpu@1 { | ||
| 25 | compatible = "arm,cortex-a15"; | ||
| 26 | device_type = "cpu"; | ||
| 27 | reg = <1>; | ||
| 28 | }; | ||
| 29 | |||
| 30 | cpu@2 { | ||
| 31 | compatible = "arm,cortex-a15"; | ||
| 32 | device_type = "cpu"; | ||
| 33 | reg = <2>; | ||
| 34 | }; | ||
| 35 | |||
| 36 | cpu@3 { | ||
| 37 | compatible = "arm,cortex-a15"; | ||
| 38 | device_type = "cpu"; | ||
| 39 | reg = <3>; | ||
| 40 | }; | ||
| 41 | }; | ||
| 42 | |||
| 43 | soc { | ||
| 44 | /include/ "k2hk-clocks.dtsi" | ||
| 45 | }; | ||
| 46 | }; | ||
diff --git a/arch/arm/boot/dts/k2l-clocks.dtsi b/arch/arm/boot/dts/k2l-clocks.dtsi new file mode 100644 index 000000000000..f584b80200f8 --- /dev/null +++ b/arch/arm/boot/dts/k2l-clocks.dtsi | |||
| @@ -0,0 +1,267 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013-2014 Texas Instruments, Inc. | ||
| 3 | * | ||
| 4 | * Keystone 2 lamarr SoC clock nodes | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | clocks { | ||
| 12 | armpllclk: armpllclk@2620370 { | ||
| 13 | #clock-cells = <0>; | ||
| 14 | compatible = "ti,keystone,pll-clock"; | ||
| 15 | clocks = <&refclksys>; | ||
| 16 | clock-output-names = "arm-pll-clk"; | ||
| 17 | reg = <0x02620370 4>; | ||
| 18 | reg-names = "control"; | ||
| 19 | }; | ||
| 20 | |||
| 21 | mainpllclk: mainpllclk@2310110 { | ||
| 22 | #clock-cells = <0>; | ||
| 23 | compatible = "ti,keystone,main-pll-clock"; | ||
| 24 | clocks = <&refclksys>; | ||
| 25 | reg = <0x02620350 4>, <0x02310110 4>; | ||
| 26 | reg-names = "control", "multiplier"; | ||
| 27 | fixed-postdiv = <2>; | ||
| 28 | }; | ||
| 29 | |||
| 30 | papllclk: papllclk@2620358 { | ||
| 31 | #clock-cells = <0>; | ||
| 32 | compatible = "ti,keystone,pll-clock"; | ||
| 33 | clocks = <&refclksys>; | ||
| 34 | clock-output-names = "pa-pll-clk"; | ||
| 35 | reg = <0x02620358 4>; | ||
| 36 | reg-names = "control"; | ||
| 37 | }; | ||
| 38 | |||
| 39 | ddr3apllclk: ddr3apllclk@2620360 { | ||
| 40 | #clock-cells = <0>; | ||
| 41 | compatible = "ti,keystone,pll-clock"; | ||
| 42 | clocks = <&refclksys>; | ||
| 43 | clock-output-names = "ddr-3a-pll-clk"; | ||
| 44 | reg = <0x02620360 4>; | ||
| 45 | reg-names = "control"; | ||
| 46 | }; | ||
| 47 | |||
| 48 | clkdfeiqnsys: clkdfeiqnsys { | ||
| 49 | #clock-cells = <0>; | ||
| 50 | compatible = "ti,keystone,psc-clock"; | ||
| 51 | clocks = <&chipclk12>; | ||
| 52 | clock-output-names = "dfe"; | ||
| 53 | reg-names = "control", "domain"; | ||
| 54 | reg = <0x02350004 0xb00>, <0x02350000 0x400>; | ||
| 55 | domain-id = <0>; | ||
| 56 | }; | ||
| 57 | |||
| 58 | clkpcie1: clkpcie1 { | ||
| 59 | #clock-cells = <0>; | ||
| 60 | compatible = "ti,keystone,psc-clock"; | ||
| 61 | clocks = <&chipclk12>; | ||
| 62 | clock-output-names = "pcie"; | ||
| 63 | reg = <0x0235002c 0xb00>, <0x02350000 0x400>; | ||
| 64 | reg-names = "control", "domain"; | ||
| 65 | domain-id = <4>; | ||
| 66 | }; | ||
| 67 | |||
| 68 | clkgem1: clkgem1 { | ||
| 69 | #clock-cells = <0>; | ||
| 70 | compatible = "ti,keystone,psc-clock"; | ||
| 71 | clocks = <&chipclk1>; | ||
| 72 | clock-output-names = "gem1"; | ||
| 73 | reg = <0x02350040 0xb00>, <0x02350024 0x400>; | ||
| 74 | reg-names = "control", "domain"; | ||
| 75 | domain-id = <9>; | ||
| 76 | }; | ||
| 77 | |||
| 78 | clkgem2: clkgem2 { | ||
| 79 | #clock-cells = <0>; | ||
| 80 | compatible = "ti,keystone,psc-clock"; | ||
| 81 | clocks = <&chipclk1>; | ||
| 82 | clock-output-names = "gem2"; | ||
| 83 | reg = <0x02350044 0xb00>, <0x02350028 0x400>; | ||
| 84 | reg-names = "control", "domain"; | ||
| 85 | domain-id = <10>; | ||
| 86 | }; | ||
| 87 | |||
| 88 | clkgem3: clkgem3 { | ||
| 89 | #clock-cells = <0>; | ||
| 90 | compatible = "ti,keystone,psc-clock"; | ||
| 91 | clocks = <&chipclk1>; | ||
| 92 | clock-output-names = "gem3"; | ||
| 93 | reg = <0x02350048 0xb00>, <0x0235002c 0x400>; | ||
| 94 | reg-names = "control", "domain"; | ||
| 95 | domain-id = <11>; | ||
| 96 | }; | ||
| 97 | |||
| 98 | clktac: clktac { | ||
| 99 | #clock-cells = <0>; | ||
| 100 | compatible = "ti,keystone,psc-clock"; | ||
| 101 | clocks = <&chipclk13>; | ||
| 102 | clock-output-names = "tac"; | ||
| 103 | reg = <0x02350064 0xb00>, <0x02350044 0x400>; | ||
| 104 | reg-names = "control", "domain"; | ||
| 105 | domain-id = <17>; | ||
| 106 | }; | ||
| 107 | |||
| 108 | clkrac: clkrac { | ||
| 109 | #clock-cells = <0>; | ||
| 110 | compatible = "ti,keystone,psc-clock"; | ||
| 111 | clocks = <&chipclk13>; | ||
| 112 | clock-output-names = "rac"; | ||
| 113 | reg = <0x02350068 0xb00>, <0x02350044 0x400>; | ||
| 114 | reg-names = "control", "domain"; | ||
| 115 | domain-id = <17>; | ||
| 116 | }; | ||
| 117 | |||
| 118 | clkdfepd0: clkdfepd0 { | ||
| 119 | #clock-cells = <0>; | ||
| 120 | compatible = "ti,keystone,psc-clock"; | ||
| 121 | clocks = <&chipclk13>; | ||
| 122 | clock-output-names = "dfe-pd0"; | ||
| 123 | reg = <0x0235006c 0xb00>, <0x02350044 0x400>; | ||
| 124 | reg-names = "control", "domain"; | ||
| 125 | domain-id = <18>; | ||
| 126 | }; | ||
| 127 | |||
| 128 | clkfftc0: clkfftc0 { | ||
| 129 | #clock-cells = <0>; | ||
| 130 | compatible = "ti,keystone,psc-clock"; | ||
| 131 | clocks = <&chipclk13>; | ||
| 132 | clock-output-names = "fftc-0"; | ||
| 133 | reg = <0x02350070 0xb00>, <0x0235004c 0x400>; | ||
| 134 | reg-names = "control", "domain"; | ||
| 135 | domain-id = <19>; | ||
| 136 | }; | ||
| 137 | |||
| 138 | clkosr: clkosr { | ||
| 139 | #clock-cells = <0>; | ||
| 140 | compatible = "ti,keystone,psc-clock"; | ||
| 141 | clocks = <&chipclk13>; | ||
| 142 | clock-output-names = "osr"; | ||
| 143 | reg = <0x02350088 0xb00>, <0x0235004c 0x400>; | ||
| 144 | reg-names = "control", "domain"; | ||
| 145 | domain-id = <21>; | ||
| 146 | }; | ||
| 147 | |||
| 148 | clktcp3d0: clktcp3d0 { | ||
| 149 | #clock-cells = <0>; | ||
| 150 | compatible = "ti,keystone,psc-clock"; | ||
| 151 | clocks = <&chipclk13>; | ||
| 152 | clock-output-names = "tcp3d-0"; | ||
| 153 | reg = <0x0235008c 0xb00>, <0x02350058 0x400>; | ||
| 154 | reg-names = "control", "domain"; | ||
| 155 | domain-id = <22>; | ||
| 156 | }; | ||
| 157 | |||
| 158 | clktcp3d1: clktcp3d1 { | ||
| 159 | #clock-cells = <0>; | ||
| 160 | compatible = "ti,keystone,psc-clock"; | ||
| 161 | clocks = <&chipclk13>; | ||
| 162 | clock-output-names = "tcp3d-1"; | ||
| 163 | reg = <0x02350094 0xb00>, <0x02350058 0x400>; | ||
| 164 | reg-names = "control", "domain"; | ||
| 165 | domain-id = <23>; | ||
| 166 | }; | ||
| 167 | |||
| 168 | clkvcp0: clkvcp0 { | ||
| 169 | #clock-cells = <0>; | ||
| 170 | compatible = "ti,keystone,psc-clock"; | ||
| 171 | clocks = <&chipclk13>; | ||
| 172 | clock-output-names = "vcp-0"; | ||
| 173 | reg = <0x0235009c 0xb00>, <0x02350060 0x400>; | ||
| 174 | reg-names = "control", "domain"; | ||
| 175 | domain-id = <24>; | ||
| 176 | }; | ||
| 177 | |||
| 178 | clkvcp1: clkvcp1 { | ||
| 179 | #clock-cells = <0>; | ||
| 180 | compatible = "ti,keystone,psc-clock"; | ||
| 181 | clocks = <&chipclk13>; | ||
| 182 | clock-output-names = "vcp-1"; | ||
| 183 | reg = <0x023500a0 0xb00>, <0x02350060 0x400>; | ||
| 184 | reg-names = "control", "domain"; | ||
| 185 | domain-id = <24>; | ||
| 186 | }; | ||
| 187 | |||
| 188 | clkvcp2: clkvcp2 { | ||
| 189 | #clock-cells = <0>; | ||
| 190 | compatible = "ti,keystone,psc-clock"; | ||
| 191 | clocks = <&chipclk13>; | ||
| 192 | clock-output-names = "vcp-2"; | ||
| 193 | reg = <0x023500a4 0xb00>, <0x02350060 0x400>; | ||
| 194 | reg-names = "control", "domain"; | ||
| 195 | domain-id = <24>; | ||
| 196 | }; | ||
| 197 | |||
| 198 | clkvcp3: clkvcp3 { | ||
| 199 | #clock-cells = <0>; | ||
| 200 | compatible = "ti,keystone,psc-clock"; | ||
| 201 | clocks = <&chipclk13>; | ||
| 202 | clock-output-names = "vcp-3"; | ||
| 203 | reg = <0x023500a8 0xb00>, <0x02350060 0x400>; | ||
| 204 | reg-names = "control", "domain"; | ||
| 205 | domain-id = <24>; | ||
| 206 | }; | ||
| 207 | |||
| 208 | clkbcp: clkbcp { | ||
| 209 | #clock-cells = <0>; | ||
| 210 | compatible = "ti,keystone,psc-clock"; | ||
| 211 | clocks = <&chipclk13>; | ||
| 212 | clock-output-names = "bcp"; | ||
| 213 | reg = <0x023500bc 0xb00>, <0x02350068 0x400>; | ||
| 214 | reg-names = "control", "domain"; | ||
| 215 | domain-id = <26>; | ||
| 216 | }; | ||
| 217 | |||
| 218 | clkdfepd1: clkdfepd1 { | ||
| 219 | #clock-cells = <0>; | ||
| 220 | compatible = "ti,keystone,psc-clock"; | ||
| 221 | clocks = <&chipclk13>; | ||
| 222 | clock-output-names = "dfe-pd1"; | ||
| 223 | reg = <0x023500c0 0xb00>, <0x02350044 0x400>; | ||
| 224 | reg-names = "control", "domain"; | ||
| 225 | domain-id = <27>; | ||
| 226 | }; | ||
| 227 | |||
| 228 | clkfftc1: clkfftc1 { | ||
| 229 | #clock-cells = <0>; | ||
| 230 | compatible = "ti,keystone,psc-clock"; | ||
| 231 | clocks = <&chipclk13>; | ||
| 232 | clock-output-names = "fftc-1"; | ||
| 233 | reg = <0x023500c4 0xb00>, <0x023504c0 0x400>; | ||
| 234 | reg-names = "control", "domain"; | ||
| 235 | domain-id = <28>; | ||
| 236 | }; | ||
| 237 | |||
| 238 | clkiqnail: clkiqnail { | ||
| 239 | #clock-cells = <0>; | ||
| 240 | compatible = "ti,keystone,psc-clock"; | ||
| 241 | clocks = <&chipclk13>; | ||
| 242 | clock-output-names = "iqn-ail"; | ||
| 243 | reg = <0x023500c8 0xb00>, <0x0235004c 0x400>; | ||
| 244 | reg-names = "control", "domain"; | ||
| 245 | domain-id = <29>; | ||
| 246 | }; | ||
| 247 | |||
| 248 | clkuart2: clkuart2 { | ||
| 249 | #clock-cells = <0>; | ||
| 250 | compatible = "ti,keystone,psc-clock"; | ||
| 251 | clocks = <&clkmodrst0>; | ||
| 252 | clock-output-names = "uart2"; | ||
| 253 | reg = <0x02350000 0xb00>, <0x02350000 0x400>; | ||
| 254 | reg-names = "control", "domain"; | ||
| 255 | domain-id = <0>; | ||
| 256 | }; | ||
| 257 | |||
| 258 | clkuart3: clkuart3 { | ||
| 259 | #clock-cells = <0>; | ||
| 260 | compatible = "ti,keystone,psc-clock"; | ||
| 261 | clocks = <&clkmodrst0>; | ||
| 262 | clock-output-names = "uart3"; | ||
| 263 | reg = <0x02350000 0xb00>, <0x02350000 0x400>; | ||
| 264 | reg-names = "control", "domain"; | ||
| 265 | domain-id = <0>; | ||
| 266 | }; | ||
| 267 | }; | ||
diff --git a/arch/arm/boot/dts/k2l-evm.dts b/arch/arm/boot/dts/k2l-evm.dts new file mode 100644 index 000000000000..ebf316a1bf6b --- /dev/null +++ b/arch/arm/boot/dts/k2l-evm.dts | |||
| @@ -0,0 +1,37 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2014 Texas Instruments, Inc. | ||
| 3 | * | ||
| 4 | * Keystone 2 Lamarr EVM device tree | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | /dts-v1/; | ||
| 11 | |||
| 12 | #include "keystone.dtsi" | ||
| 13 | #include "k2l.dtsi" | ||
| 14 | |||
| 15 | / { | ||
| 16 | compatible = "ti,k2l-evm"; | ||
| 17 | model = "Texas Instruments Keystone 2 Lamarr EVM"; | ||
| 18 | |||
| 19 | soc { | ||
| 20 | clocks { | ||
| 21 | refclksys: refclksys { | ||
| 22 | #clock-cells = <0>; | ||
| 23 | compatible = "fixed-clock"; | ||
| 24 | clock-frequency = <122880000>; | ||
| 25 | clock-output-names = "refclk-sys"; | ||
| 26 | }; | ||
| 27 | }; | ||
| 28 | }; | ||
| 29 | }; | ||
| 30 | |||
| 31 | &usb_phy { | ||
| 32 | status = "okay"; | ||
| 33 | }; | ||
| 34 | |||
| 35 | &usb { | ||
| 36 | status = "okay"; | ||
| 37 | }; | ||
diff --git a/arch/arm/boot/dts/k2l.dtsi b/arch/arm/boot/dts/k2l.dtsi new file mode 100644 index 000000000000..1f7f479589e1 --- /dev/null +++ b/arch/arm/boot/dts/k2l.dtsi | |||
| @@ -0,0 +1,55 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2014 Texas Instruments, Inc. | ||
| 3 | * | ||
| 4 | * Keystone 2 Lamarr SoC specific device tree | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | / { | ||
| 12 | cpus { | ||
| 13 | #address-cells = <1>; | ||
| 14 | #size-cells = <0>; | ||
| 15 | |||
| 16 | interrupt-parent = <&gic>; | ||
| 17 | |||
| 18 | cpu@0 { | ||
| 19 | compatible = "arm,cortex-a15"; | ||
| 20 | device_type = "cpu"; | ||
| 21 | reg = <0>; | ||
| 22 | }; | ||
| 23 | |||
| 24 | cpu@1 { | ||
| 25 | compatible = "arm,cortex-a15"; | ||
| 26 | device_type = "cpu"; | ||
| 27 | reg = <1>; | ||
| 28 | }; | ||
| 29 | }; | ||
| 30 | |||
| 31 | soc { | ||
| 32 | |||
| 33 | /include/ "k2l-clocks.dtsi" | ||
| 34 | |||
| 35 | uart2: serial@02348400 { | ||
| 36 | compatible = "ns16550a"; | ||
| 37 | current-speed = <115200>; | ||
| 38 | reg-shift = <2>; | ||
| 39 | reg-io-width = <4>; | ||
| 40 | reg = <0x02348400 0x100>; | ||
| 41 | clocks = <&clkuart2>; | ||
| 42 | interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>; | ||
| 43 | }; | ||
| 44 | |||
| 45 | uart3: serial@02348800 { | ||
| 46 | compatible = "ns16550a"; | ||
| 47 | current-speed = <115200>; | ||
| 48 | reg-shift = <2>; | ||
| 49 | reg-io-width = <4>; | ||
| 50 | reg = <0x02348800 0x100>; | ||
| 51 | clocks = <&clkuart3>; | ||
| 52 | interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>; | ||
| 53 | }; | ||
| 54 | }; | ||
| 55 | }; | ||
diff --git a/arch/arm/boot/dts/keystone-clocks.dtsi b/arch/arm/boot/dts/keystone-clocks.dtsi index 2363593e1050..93f82c7010ab 100644 --- a/arch/arm/boot/dts/keystone-clocks.dtsi +++ b/arch/arm/boot/dts/keystone-clocks.dtsi | |||
| @@ -13,51 +13,6 @@ clocks { | |||
| 13 | #size-cells = <1>; | 13 | #size-cells = <1>; |
| 14 | ranges; | 14 | ranges; |
| 15 | 15 | ||
| 16 | mainpllclk: mainpllclk@2310110 { | ||
| 17 | #clock-cells = <0>; | ||
| 18 | compatible = "ti,keystone,main-pll-clock"; | ||
| 19 | clocks = <&refclksys>; | ||
| 20 | reg = <0x02620350 4>, <0x02310110 4>; | ||
| 21 | reg-names = "control", "multiplier"; | ||
| 22 | fixed-postdiv = <2>; | ||
| 23 | }; | ||
| 24 | |||
| 25 | papllclk: papllclk@2620358 { | ||
| 26 | #clock-cells = <0>; | ||
| 27 | compatible = "ti,keystone,pll-clock"; | ||
| 28 | clocks = <&refclkpass>; | ||
| 29 | clock-output-names = "pa-pll-clk"; | ||
| 30 | reg = <0x02620358 4>; | ||
| 31 | reg-names = "control"; | ||
| 32 | }; | ||
| 33 | |||
| 34 | ddr3apllclk: ddr3apllclk@2620360 { | ||
| 35 | #clock-cells = <0>; | ||
| 36 | compatible = "ti,keystone,pll-clock"; | ||
| 37 | clocks = <&refclkddr3a>; | ||
| 38 | clock-output-names = "ddr-3a-pll-clk"; | ||
| 39 | reg = <0x02620360 4>; | ||
| 40 | reg-names = "control"; | ||
| 41 | }; | ||
| 42 | |||
| 43 | ddr3bpllclk: ddr3bpllclk@2620368 { | ||
| 44 | #clock-cells = <0>; | ||
| 45 | compatible = "ti,keystone,pll-clock"; | ||
| 46 | clocks = <&refclkddr3b>; | ||
| 47 | clock-output-names = "ddr-3b-pll-clk"; | ||
| 48 | reg = <0x02620368 4>; | ||
| 49 | reg-names = "control"; | ||
| 50 | }; | ||
| 51 | |||
| 52 | armpllclk: armpllclk@2620370 { | ||
| 53 | #clock-cells = <0>; | ||
| 54 | compatible = "ti,keystone,pll-clock"; | ||
| 55 | clocks = <&refclkarm>; | ||
| 56 | clock-output-names = "arm-pll-clk"; | ||
| 57 | reg = <0x02620370 4>; | ||
| 58 | reg-names = "control"; | ||
| 59 | }; | ||
| 60 | |||
| 61 | mainmuxclk: mainmuxclk@2310108 { | 16 | mainmuxclk: mainmuxclk@2310108 { |
| 62 | #clock-cells = <0>; | 17 | #clock-cells = <0>; |
| 63 | compatible = "ti,keystone,pll-mux-clock"; | 18 | compatible = "ti,keystone,pll-mux-clock"; |
| @@ -244,7 +199,7 @@ clocks { | |||
| 244 | clock-output-names = "debugss-trc"; | 199 | clock-output-names = "debugss-trc"; |
| 245 | reg = <0x02350014 0xb00>, <0x02350000 0x400>; | 200 | reg = <0x02350014 0xb00>, <0x02350000 0x400>; |
| 246 | reg-names = "control", "domain"; | 201 | reg-names = "control", "domain"; |
| 247 | domain-id = <0>; | 202 | domain-id = <1>; |
| 248 | }; | 203 | }; |
| 249 | 204 | ||
| 250 | clktetbtrc: clktetbtrc { | 205 | clktetbtrc: clktetbtrc { |
| @@ -297,26 +252,6 @@ clocks { | |||
| 297 | domain-id = <3>; | 252 | domain-id = <3>; |
| 298 | }; | 253 | }; |
| 299 | 254 | ||
| 300 | clksrio: clksrio { | ||
| 301 | #clock-cells = <0>; | ||
| 302 | compatible = "ti,keystone,psc-clock"; | ||
| 303 | clocks = <&chipclk1rstiso13>; | ||
| 304 | clock-output-names = "srio"; | ||
| 305 | reg = <0x0235002c 0xb00>, <0x02350010 0x400>; | ||
| 306 | reg-names = "control", "domain"; | ||
| 307 | domain-id = <4>; | ||
| 308 | }; | ||
| 309 | |||
| 310 | clkhyperlink0: clkhyperlink0 { | ||
| 311 | #clock-cells = <0>; | ||
| 312 | compatible = "ti,keystone,psc-clock"; | ||
| 313 | clocks = <&chipclk12>; | ||
| 314 | clock-output-names = "hyperlink-0"; | ||
| 315 | reg = <0x02350030 0xb00>, <0x02350014 0x400>; | ||
| 316 | reg-names = "control", "domain"; | ||
| 317 | domain-id = <5>; | ||
| 318 | }; | ||
| 319 | |||
| 320 | clksr: clksr { | 255 | clksr: clksr { |
| 321 | #clock-cells = <0>; | 256 | #clock-cells = <0>; |
| 322 | compatible = "ti,keystone,psc-clock"; | 257 | compatible = "ti,keystone,psc-clock"; |
| @@ -327,16 +262,6 @@ clocks { | |||
| 327 | domain-id = <6>; | 262 | domain-id = <6>; |
| 328 | }; | 263 | }; |
| 329 | 264 | ||
| 330 | clkmsmcsram: clkmsmcsram { | ||
| 331 | #clock-cells = <0>; | ||
| 332 | compatible = "ti,keystone,psc-clock"; | ||
| 333 | clocks = <&chipclk1>; | ||
| 334 | clock-output-names = "msmcsram"; | ||
| 335 | reg = <0x02350038 0xb00>, <0x0235001c 0x400>; | ||
| 336 | reg-names = "control", "domain"; | ||
| 337 | domain-id = <7>; | ||
| 338 | }; | ||
| 339 | |||
| 340 | clkgem0: clkgem0 { | 265 | clkgem0: clkgem0 { |
| 341 | #clock-cells = <0>; | 266 | #clock-cells = <0>; |
| 342 | compatible = "ti,keystone,psc-clock"; | 267 | compatible = "ti,keystone,psc-clock"; |
| @@ -347,76 +272,6 @@ clocks { | |||
| 347 | domain-id = <8>; | 272 | domain-id = <8>; |
| 348 | }; | 273 | }; |
| 349 | 274 | ||
| 350 | clkgem1: clkgem1 { | ||
| 351 | #clock-cells = <0>; | ||
| 352 | compatible = "ti,keystone,psc-clock"; | ||
| 353 | clocks = <&chipclk1>; | ||
| 354 | clock-output-names = "gem1"; | ||
| 355 | reg = <0x02350040 0xb00>, <0x02350024 0x400>; | ||
| 356 | reg-names = "control", "domain"; | ||
| 357 | domain-id = <9>; | ||
| 358 | }; | ||
| 359 | |||
| 360 | clkgem2: clkgem2 { | ||
| 361 | #clock-cells = <0>; | ||
| 362 | compatible = "ti,keystone,psc-clock"; | ||
| 363 | clocks = <&chipclk1>; | ||
| 364 | clock-output-names = "gem2"; | ||
| 365 | reg = <0x02350044 0xb00>, <0x02350028 0x400>; | ||
| 366 | reg-names = "control", "domain"; | ||
| 367 | domain-id = <10>; | ||
| 368 | }; | ||
| 369 | |||
| 370 | clkgem3: clkgem3 { | ||
| 371 | #clock-cells = <0>; | ||
| 372 | compatible = "ti,keystone,psc-clock"; | ||
| 373 | clocks = <&chipclk1>; | ||
| 374 | clock-output-names = "gem3"; | ||
| 375 | reg = <0x02350048 0xb00>, <0x0235002c 0x400>; | ||
| 376 | reg-names = "control", "domain"; | ||
| 377 | domain-id = <11>; | ||
| 378 | }; | ||
| 379 | |||
| 380 | clkgem4: clkgem4 { | ||
| 381 | #clock-cells = <0>; | ||
| 382 | compatible = "ti,keystone,psc-clock"; | ||
| 383 | clocks = <&chipclk1>; | ||
| 384 | clock-output-names = "gem4"; | ||
| 385 | reg = <0x0235004c 0xb00>, <0x02350030 0x400>; | ||
| 386 | reg-names = "control", "domain"; | ||
| 387 | domain-id = <12>; | ||
| 388 | }; | ||
| 389 | |||
| 390 | clkgem5: clkgem5 { | ||
| 391 | #clock-cells = <0>; | ||
| 392 | compatible = "ti,keystone,psc-clock"; | ||
| 393 | clocks = <&chipclk1>; | ||
| 394 | clock-output-names = "gem5"; | ||
| 395 | reg = <0x02350050 0xb00>, <0x02350034 0x400>; | ||
| 396 | reg-names = "control", "domain"; | ||
| 397 | domain-id = <13>; | ||
| 398 | }; | ||
| 399 | |||
| 400 | clkgem6: clkgem6 { | ||
| 401 | #clock-cells = <0>; | ||
| 402 | compatible = "ti,keystone,psc-clock"; | ||
| 403 | clocks = <&chipclk1>; | ||
| 404 | clock-output-names = "gem6"; | ||
| 405 | reg = <0x02350054 0xb00>, <0x02350038 0x400>; | ||
| 406 | reg-names = "control", "domain"; | ||
| 407 | domain-id = <14>; | ||
| 408 | }; | ||
| 409 | |||
| 410 | clkgem7: clkgem7 { | ||
| 411 | #clock-cells = <0>; | ||
| 412 | compatible = "ti,keystone,psc-clock"; | ||
| 413 | clocks = <&chipclk1>; | ||
| 414 | clock-output-names = "gem7"; | ||
| 415 | reg = <0x02350058 0xb00>, <0x0235003c 0x400>; | ||
| 416 | reg-names = "control", "domain"; | ||
| 417 | domain-id = <15>; | ||
| 418 | }; | ||
| 419 | |||
| 420 | clkddr30: clkddr30 { | 275 | clkddr30: clkddr30 { |
| 421 | #clock-cells = <0>; | 276 | #clock-cells = <0>; |
| 422 | compatible = "ti,keystone,psc-clock"; | 277 | compatible = "ti,keystone,psc-clock"; |
| @@ -427,276 +282,6 @@ clocks { | |||
| 427 | domain-id = <16>; | 282 | domain-id = <16>; |
| 428 | }; | 283 | }; |
| 429 | 284 | ||
| 430 | clkddr31: clkddr31 { | ||
| 431 | #clock-cells = <0>; | ||
| 432 | compatible = "ti,keystone,psc-clock"; | ||
| 433 | clocks = <&chipclk13>; | ||
| 434 | clock-output-names = "ddr3-1"; | ||
| 435 | reg = <0x02350060 0xb00>, <0x02350040 0x400>; | ||
| 436 | reg-names = "control", "domain"; | ||
| 437 | domain-id = <16>; | ||
| 438 | }; | ||
| 439 | |||
| 440 | clktac: clktac { | ||
| 441 | #clock-cells = <0>; | ||
| 442 | compatible = "ti,keystone,psc-clock"; | ||
| 443 | clocks = <&chipclk13>; | ||
| 444 | clock-output-names = "tac"; | ||
| 445 | reg = <0x02350064 0xb00>, <0x02350044 0x400>; | ||
| 446 | reg-names = "control", "domain"; | ||
| 447 | domain-id = <17>; | ||
| 448 | }; | ||
| 449 | |||
| 450 | clkrac01: clktac01 { | ||
| 451 | #clock-cells = <0>; | ||
| 452 | compatible = "ti,keystone,psc-clock"; | ||
| 453 | clocks = <&chipclk13>; | ||
| 454 | clock-output-names = "rac-01"; | ||
| 455 | reg = <0x02350068 0xb00>, <0x02350044 0x400>; | ||
| 456 | reg-names = "control", "domain"; | ||
| 457 | domain-id = <17>; | ||
| 458 | }; | ||
| 459 | |||
| 460 | clkrac23: clktac23 { | ||
| 461 | #clock-cells = <0>; | ||
| 462 | compatible = "ti,keystone,psc-clock"; | ||
| 463 | clocks = <&chipclk13>; | ||
| 464 | clock-output-names = "rac-23"; | ||
| 465 | reg = <0x0235006c 0xb00>, <0x02350048 0x400>; | ||
| 466 | reg-names = "control", "domain"; | ||
| 467 | domain-id = <18>; | ||
| 468 | }; | ||
| 469 | |||
| 470 | clkfftc0: clkfftc0 { | ||
| 471 | #clock-cells = <0>; | ||
| 472 | compatible = "ti,keystone,psc-clock"; | ||
| 473 | clocks = <&chipclk13>; | ||
| 474 | clock-output-names = "fftc-0"; | ||
| 475 | reg = <0x02350070 0xb00>, <0x0235004c 0x400>; | ||
| 476 | reg-names = "control", "domain"; | ||
| 477 | domain-id = <19>; | ||
| 478 | }; | ||
| 479 | |||
| 480 | clkfftc1: clkfftc1 { | ||
| 481 | #clock-cells = <0>; | ||
| 482 | compatible = "ti,keystone,psc-clock"; | ||
| 483 | clocks = <&chipclk13>; | ||
| 484 | clock-output-names = "fftc-1"; | ||
| 485 | reg = <0x02350074 0xb00>, <0x023504c0 0x400>; | ||
| 486 | reg-names = "control", "domain"; | ||
| 487 | domain-id = <19>; | ||
| 488 | }; | ||
| 489 | |||
| 490 | clkfftc2: clkfftc2 { | ||
| 491 | #clock-cells = <0>; | ||
| 492 | compatible = "ti,keystone,psc-clock"; | ||
| 493 | clocks = <&chipclk13>; | ||
| 494 | clock-output-names = "fftc-2"; | ||
| 495 | reg = <0x02350078 0xb00>, <0x02350050 0x400>; | ||
| 496 | reg-names = "control", "domain"; | ||
| 497 | domain-id = <20>; | ||
| 498 | }; | ||
| 499 | |||
| 500 | clkfftc3: clkfftc3 { | ||
| 501 | #clock-cells = <0>; | ||
| 502 | compatible = "ti,keystone,psc-clock"; | ||
| 503 | clocks = <&chipclk13>; | ||
| 504 | clock-output-names = "fftc-3"; | ||
| 505 | reg = <0x0235007c 0xb00>, <0x02350050 0x400>; | ||
| 506 | reg-names = "control", "domain"; | ||
| 507 | domain-id = <20>; | ||
| 508 | }; | ||
| 509 | |||
| 510 | clkfftc4: clkfftc4 { | ||
| 511 | #clock-cells = <0>; | ||
| 512 | compatible = "ti,keystone,psc-clock"; | ||
| 513 | clocks = <&chipclk13>; | ||
| 514 | clock-output-names = "fftc-4"; | ||
| 515 | reg = <0x02350080 0xb00>, <0x02350050 0x400>; | ||
| 516 | reg-names = "control", "domain"; | ||
| 517 | domain-id = <20>; | ||
| 518 | }; | ||
| 519 | |||
| 520 | clkfftc5: clkfftc5 { | ||
| 521 | #clock-cells = <0>; | ||
| 522 | compatible = "ti,keystone,psc-clock"; | ||
| 523 | clocks = <&chipclk13>; | ||
| 524 | clock-output-names = "fftc-5"; | ||
| 525 | reg = <0x02350084 0xb00>, <0x02350050 0x400>; | ||
| 526 | reg-names = "control", "domain"; | ||
| 527 | domain-id = <20>; | ||
| 528 | }; | ||
| 529 | |||
| 530 | clkaif: clkaif { | ||
| 531 | #clock-cells = <0>; | ||
| 532 | compatible = "ti,keystone,psc-clock"; | ||
| 533 | clocks = <&chipclk13>; | ||
| 534 | clock-output-names = "aif"; | ||
| 535 | reg = <0x02350088 0xb00>, <0x02350054 0x400>; | ||
| 536 | reg-names = "control", "domain"; | ||
| 537 | domain-id = <21>; | ||
| 538 | }; | ||
| 539 | |||
| 540 | clktcp3d0: clktcp3d0 { | ||
| 541 | #clock-cells = <0>; | ||
| 542 | compatible = "ti,keystone,psc-clock"; | ||
| 543 | clocks = <&chipclk13>; | ||
| 544 | clock-output-names = "tcp3d-0"; | ||
| 545 | reg = <0x0235008c 0xb00>, <0x02350058 0x400>; | ||
| 546 | reg-names = "control", "domain"; | ||
| 547 | domain-id = <22>; | ||
| 548 | }; | ||
| 549 | |||
| 550 | clktcp3d1: clktcp3d1 { | ||
| 551 | #clock-cells = <0>; | ||
| 552 | compatible = "ti,keystone,psc-clock"; | ||
| 553 | clocks = <&chipclk13>; | ||
| 554 | clock-output-names = "tcp3d-1"; | ||
| 555 | reg = <0x02350090 0xb00>, <0x02350058 0x400>; | ||
| 556 | reg-names = "control", "domain"; | ||
| 557 | domain-id = <22>; | ||
| 558 | }; | ||
| 559 | |||
| 560 | clktcp3d2: clktcp3d2 { | ||
| 561 | #clock-cells = <0>; | ||
| 562 | compatible = "ti,keystone,psc-clock"; | ||
| 563 | clocks = <&chipclk13>; | ||
| 564 | clock-output-names = "tcp3d-2"; | ||
| 565 | reg = <0x02350094 0xb00>, <0x0235005c 0x400>; | ||
| 566 | reg-names = "control", "domain"; | ||
| 567 | domain-id = <23>; | ||
| 568 | }; | ||
| 569 | |||
| 570 | clktcp3d3: clktcp3d3 { | ||
| 571 | #clock-cells = <0>; | ||
| 572 | compatible = "ti,keystone,psc-clock"; | ||
| 573 | clocks = <&chipclk13>; | ||
| 574 | clock-output-names = "tcp3d-3"; | ||
| 575 | reg = <0x02350098 0xb00>, <0x0235005c 0x400>; | ||
| 576 | reg-names = "control", "domain"; | ||
| 577 | domain-id = <23>; | ||
| 578 | }; | ||
| 579 | |||
| 580 | clkvcp0: clkvcp0 { | ||
| 581 | #clock-cells = <0>; | ||
| 582 | compatible = "ti,keystone,psc-clock"; | ||
| 583 | clocks = <&chipclk13>; | ||
| 584 | clock-output-names = "vcp-0"; | ||
| 585 | reg = <0x0235009c 0xb00>, <0x02350060 0x400>; | ||
| 586 | reg-names = "control", "domain"; | ||
| 587 | domain-id = <24>; | ||
| 588 | }; | ||
| 589 | |||
| 590 | clkvcp1: clkvcp1 { | ||
| 591 | #clock-cells = <0>; | ||
| 592 | compatible = "ti,keystone,psc-clock"; | ||
| 593 | clocks = <&chipclk13>; | ||
| 594 | clock-output-names = "vcp-1"; | ||
| 595 | reg = <0x023500a0 0xb00>, <0x02350060 0x400>; | ||
| 596 | reg-names = "control", "domain"; | ||
| 597 | domain-id = <24>; | ||
| 598 | }; | ||
| 599 | |||
| 600 | clkvcp2: clkvcp2 { | ||
| 601 | #clock-cells = <0>; | ||
| 602 | compatible = "ti,keystone,psc-clock"; | ||
| 603 | clocks = <&chipclk13>; | ||
| 604 | clock-output-names = "vcp-2"; | ||
| 605 | reg = <0x023500a4 0xb00>, <0x02350060 0x400>; | ||
| 606 | reg-names = "control", "domain"; | ||
| 607 | domain-id = <24>; | ||
| 608 | }; | ||
| 609 | |||
| 610 | clkvcp3: clkvcp3 { | ||
| 611 | #clock-cells = <0>; | ||
| 612 | compatible = "ti,keystone,psc-clock"; | ||
| 613 | clocks = <&chipclk13>; | ||
| 614 | clock-output-names = "vcp-3"; | ||
| 615 | reg = <0x0235000a8 0xb00>, <0x02350060 0x400>; | ||
| 616 | reg-names = "control", "domain"; | ||
| 617 | domain-id = <24>; | ||
| 618 | }; | ||
| 619 | |||
| 620 | clkvcp4: clkvcp4 { | ||
| 621 | #clock-cells = <0>; | ||
| 622 | compatible = "ti,keystone,psc-clock"; | ||
| 623 | clocks = <&chipclk13>; | ||
| 624 | clock-output-names = "vcp-4"; | ||
| 625 | reg = <0x023500ac 0xb00>, <0x02350064 0x400>; | ||
| 626 | reg-names = "control", "domain"; | ||
| 627 | domain-id = <25>; | ||
| 628 | }; | ||
| 629 | |||
| 630 | clkvcp5: clkvcp5 { | ||
| 631 | #clock-cells = <0>; | ||
| 632 | compatible = "ti,keystone,psc-clock"; | ||
| 633 | clocks = <&chipclk13>; | ||
| 634 | clock-output-names = "vcp-5"; | ||
| 635 | reg = <0x023500b0 0xb00>, <0x02350064 0x400>; | ||
| 636 | reg-names = "control", "domain"; | ||
| 637 | domain-id = <25>; | ||
| 638 | }; | ||
| 639 | |||
| 640 | clkvcp6: clkvcp6 { | ||
| 641 | #clock-cells = <0>; | ||
| 642 | compatible = "ti,keystone,psc-clock"; | ||
| 643 | clocks = <&chipclk13>; | ||
| 644 | clock-output-names = "vcp-6"; | ||
| 645 | reg = <0x023500b4 0xb00>, <0x02350064 0x400>; | ||
| 646 | reg-names = "control", "domain"; | ||
| 647 | domain-id = <25>; | ||
| 648 | }; | ||
| 649 | |||
| 650 | clkvcp7: clkvcp7 { | ||
| 651 | #clock-cells = <0>; | ||
| 652 | compatible = "ti,keystone,psc-clock"; | ||
| 653 | clocks = <&chipclk13>; | ||
| 654 | clock-output-names = "vcp-7"; | ||
| 655 | reg = <0x023500b8 0xb00>, <0x02350064 0x400>; | ||
| 656 | reg-names = "control", "domain"; | ||
| 657 | domain-id = <25>; | ||
| 658 | }; | ||
| 659 | |||
| 660 | clkbcp: clkbcp { | ||
| 661 | #clock-cells = <0>; | ||
| 662 | compatible = "ti,keystone,psc-clock"; | ||
| 663 | clocks = <&chipclk13>; | ||
| 664 | clock-output-names = "bcp"; | ||
| 665 | reg = <0x023500bc 0xb00>, <0x02350068 0x400>; | ||
| 666 | reg-names = "control", "domain"; | ||
| 667 | domain-id = <26>; | ||
| 668 | }; | ||
| 669 | |||
| 670 | clkdxb: clkdxb { | ||
| 671 | #clock-cells = <0>; | ||
| 672 | compatible = "ti,keystone,psc-clock"; | ||
| 673 | clocks = <&chipclk13>; | ||
| 674 | clock-output-names = "dxb"; | ||
| 675 | reg = <0x023500c0 0xb00>, <0x0235006c 0x400>; | ||
| 676 | reg-names = "control", "domain"; | ||
| 677 | domain-id = <27>; | ||
| 678 | }; | ||
| 679 | |||
| 680 | clkhyperlink1: clkhyperlink1 { | ||
| 681 | #clock-cells = <0>; | ||
| 682 | compatible = "ti,keystone,psc-clock"; | ||
| 683 | clocks = <&chipclk12>; | ||
| 684 | clock-output-names = "hyperlink-1"; | ||
| 685 | reg = <0x023500c4 0xb00>, <0x02350070 0x400>; | ||
| 686 | reg-names = "control", "domain"; | ||
| 687 | domain-id = <28>; | ||
| 688 | }; | ||
| 689 | |||
| 690 | clkxge: clkxge { | ||
| 691 | #clock-cells = <0>; | ||
| 692 | compatible = "ti,keystone,psc-clock"; | ||
| 693 | clocks = <&chipclk13>; | ||
| 694 | clock-output-names = "xge"; | ||
| 695 | reg = <0x023500c8 0xb00>, <0x02350074 0x400>; | ||
| 696 | reg-names = "control", "domain"; | ||
| 697 | domain-id = <29>; | ||
| 698 | }; | ||
| 699 | |||
| 700 | clkwdtimer0: clkwdtimer0 { | 285 | clkwdtimer0: clkwdtimer0 { |
| 701 | #clock-cells = <0>; | 286 | #clock-cells = <0>; |
| 702 | compatible = "ti,keystone,psc-clock"; | 287 | compatible = "ti,keystone,psc-clock"; |
| @@ -737,6 +322,16 @@ clocks { | |||
| 737 | domain-id = <0>; | 322 | domain-id = <0>; |
| 738 | }; | 323 | }; |
| 739 | 324 | ||
| 325 | clktimer15: clktimer15 { | ||
| 326 | #clock-cells = <0>; | ||
| 327 | compatible = "ti,keystone,psc-clock"; | ||
| 328 | clocks = <&clkmodrst0>; | ||
| 329 | clock-output-names = "timer15"; | ||
| 330 | reg = <0x02350000 0xb00>, <0x02350000 0x400>; | ||
| 331 | reg-names = "control", "domain"; | ||
| 332 | domain-id = <0>; | ||
| 333 | }; | ||
| 334 | |||
| 740 | clkuart0: clkuart0 { | 335 | clkuart0: clkuart0 { |
| 741 | #clock-cells = <0>; | 336 | #clock-cells = <0>; |
| 742 | compatible = "ti,keystone,psc-clock"; | 337 | compatible = "ti,keystone,psc-clock"; |
diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi index b4202907a27b..90823eb90c1b 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/keystone.dtsi | |||
| @@ -7,6 +7,7 @@ | |||
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | #include <dt-bindings/interrupt-controller/arm-gic.h> | 9 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 10 | #include <dt-bindings/gpio/gpio.h> | ||
| 10 | 11 | ||
| 11 | #include "skeleton.dtsi" | 12 | #include "skeleton.dtsi" |
| 12 | 13 | ||
| @@ -24,37 +25,6 @@ | |||
| 24 | reg = <0x00000000 0x80000000 0x00000000 0x40000000>; | 25 | reg = <0x00000000 0x80000000 0x00000000 0x40000000>; |
| 25 | }; | 26 | }; |
| 26 | 27 | ||
| 27 | cpus { | ||
| 28 | #address-cells = <1>; | ||
| 29 | #size-cells = <0>; | ||
| 30 | |||
| 31 | interrupt-parent = <&gic>; | ||
| 32 | |||
| 33 | cpu@0 { | ||
| 34 | compatible = "arm,cortex-a15"; | ||
| 35 | device_type = "cpu"; | ||
| 36 | reg = <0>; | ||
| 37 | }; | ||
| 38 | |||
| 39 | cpu@1 { | ||
| 40 | compatible = "arm,cortex-a15"; | ||
| 41 | device_type = "cpu"; | ||
| 42 | reg = <1>; | ||
| 43 | }; | ||
| 44 | |||
| 45 | cpu@2 { | ||
| 46 | compatible = "arm,cortex-a15"; | ||
| 47 | device_type = "cpu"; | ||
| 48 | reg = <2>; | ||
| 49 | }; | ||
| 50 | |||
| 51 | cpu@3 { | ||
| 52 | compatible = "arm,cortex-a15"; | ||
| 53 | device_type = "cpu"; | ||
| 54 | reg = <3>; | ||
| 55 | }; | ||
| 56 | }; | ||
| 57 | |||
| 58 | gic: interrupt-controller { | 28 | gic: interrupt-controller { |
| 59 | compatible = "arm,cortex-a15-gic"; | 29 | compatible = "arm,cortex-a15-gic"; |
| 60 | #interrupt-cells = <3>; | 30 | #interrupt-cells = <3>; |
| @@ -208,5 +178,75 @@ | |||
| 208 | usb-phy = <&usb_phy>, <&usb_phy>; | 178 | usb-phy = <&usb_phy>, <&usb_phy>; |
| 209 | }; | 179 | }; |
| 210 | }; | 180 | }; |
| 181 | |||
| 182 | wdt: wdt@022f0080 { | ||
| 183 | compatible = "ti,keystone-wdt","ti,davinci-wdt"; | ||
| 184 | reg = <0x022f0080 0x80>; | ||
| 185 | clocks = <&clkwdtimer0>; | ||
| 186 | }; | ||
| 187 | |||
| 188 | clock_event: timer@22f0000 { | ||
| 189 | compatible = "ti,keystone-timer"; | ||
| 190 | reg = <0x022f0000 0x80>; | ||
| 191 | interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>; | ||
| 192 | clocks = <&clktimer15>; | ||
| 193 | }; | ||
| 194 | |||
| 195 | gpio0: gpio@260bf00 { | ||
| 196 | compatible = "ti,keystone-gpio"; | ||
| 197 | reg = <0x0260bf00 0x100>; | ||
| 198 | gpio-controller; | ||
| 199 | #gpio-cells = <2>; | ||
| 200 | /* HW Interrupts mapped to GPIO pins */ | ||
| 201 | interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>, | ||
| 202 | <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>, | ||
| 203 | <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, | ||
| 204 | <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>, | ||
| 205 | <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>, | ||
| 206 | <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, | ||
| 207 | <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, | ||
| 208 | <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, | ||
| 209 | <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, | ||
| 210 | <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, | ||
| 211 | <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, | ||
| 212 | <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, | ||
| 213 | <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, | ||
| 214 | <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, | ||
| 215 | <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, | ||
| 216 | <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, | ||
| 217 | <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, | ||
| 218 | <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, | ||
| 219 | <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, | ||
| 220 | <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, | ||
| 221 | <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>, | ||
| 222 | <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, | ||
| 223 | <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>, | ||
| 224 | <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>, | ||
| 225 | <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>, | ||
| 226 | <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>, | ||
| 227 | <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>, | ||
| 228 | <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>, | ||
| 229 | <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>, | ||
| 230 | <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, | ||
| 231 | <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>, | ||
| 232 | <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>; | ||
| 233 | clocks = <&clkgpio>; | ||
| 234 | clock-names = "gpio"; | ||
| 235 | ti,ngpio = <32>; | ||
| 236 | ti,davinci-gpio-unbanked = <32>; | ||
| 237 | }; | ||
| 238 | |||
| 239 | aemif: aemif@21000A00 { | ||
| 240 | compatible = "ti,keystone-aemif", "ti,davinci-aemif"; | ||
| 241 | #address-cells = <2>; | ||
| 242 | #size-cells = <1>; | ||
| 243 | clocks = <&clkaemif>; | ||
| 244 | clock-names = "aemif"; | ||
| 245 | clock-ranges; | ||
| 246 | |||
| 247 | reg = <0x21000A00 0x00000100>; | ||
| 248 | ranges = <0 0 0x30000000 0x10000000 | ||
| 249 | 1 0 0x21000A00 0x00000100>; | ||
| 250 | }; | ||
| 211 | }; | 251 | }; |
| 212 | }; | 252 | }; |
diff --git a/arch/arm/boot/dts/kirkwood-b3.dts b/arch/arm/boot/dts/kirkwood-b3.dts new file mode 100644 index 000000000000..40791053106b --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-b3.dts | |||
| @@ -0,0 +1,204 @@ | |||
| 1 | /* | ||
| 2 | * Device Tree file for Excito Bubba B3 | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013, Andrew Lunn <andrew@lunn.ch> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public License | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the License, or (at your option) any later version. | ||
| 10 | * | ||
| 11 | * Note: This requires a new'ish version of u-boot, which disables the | ||
| 12 | * L2 cache. If your B3 silently fails to boot, u-boot is probably too | ||
| 13 | * old. Either upgrade, or consider the following email: | ||
| 14 | * | ||
| 15 | * http://lists.debian.org/debian-arm/2012/08/msg00128.html | ||
| 16 | */ | ||
| 17 | |||
| 18 | /dts-v1/; | ||
| 19 | |||
| 20 | #include "kirkwood.dtsi" | ||
| 21 | #include "kirkwood-6281.dtsi" | ||
| 22 | |||
| 23 | / { | ||
| 24 | model = "Excito B3"; | ||
| 25 | compatible = "excito,b3", "marvell,kirkwood-88f6281", "marvell,kirkwood"; | ||
| 26 | memory { /* 512 MB */ | ||
| 27 | device_type = "memory"; | ||
| 28 | reg = <0x00000000 0x20000000>; | ||
| 29 | }; | ||
| 30 | |||
| 31 | chosen { | ||
| 32 | bootargs = "console=ttyS0,115200n8 earlyprintk"; | ||
| 33 | }; | ||
| 34 | |||
| 35 | mbus { | ||
| 36 | pcie-controller { | ||
| 37 | status = "okay"; | ||
| 38 | |||
| 39 | /* Wifi model has Atheros chipset on pcie port */ | ||
| 40 | pcie@1,0 { | ||
| 41 | status = "okay"; | ||
| 42 | }; | ||
| 43 | }; | ||
| 44 | }; | ||
| 45 | |||
| 46 | ocp@f1000000 { | ||
| 47 | pinctrl: pinctrl@10000 { | ||
| 48 | pmx_button_power: pmx-button-power { | ||
| 49 | marvell,pins = "mpp39"; | ||
| 50 | marvell,function = "gpio"; | ||
| 51 | }; | ||
| 52 | pmx_led_green: pmx-led-green { | ||
| 53 | marvell,pins = "mpp38"; | ||
| 54 | marvell,function = "gpio"; | ||
| 55 | }; | ||
| 56 | pmx_led_red: pmx-led-red { | ||
| 57 | marvell,pins = "mpp41"; | ||
| 58 | marvell,function = "gpio"; | ||
| 59 | }; | ||
| 60 | pmx_led_blue: pmx-led-blue { | ||
| 61 | marvell,pins = "mpp42"; | ||
| 62 | marvell,function = "gpio"; | ||
| 63 | }; | ||
| 64 | pmx_beeper: pmx-beeper { | ||
| 65 | marvell,pins = "mpp40"; | ||
| 66 | marvell,function = "gpio"; | ||
| 67 | }; | ||
| 68 | }; | ||
| 69 | |||
| 70 | spi@10600 { | ||
| 71 | status = "okay"; | ||
| 72 | pinctrl-0 = <&pmx_spi>; | ||
| 73 | pinctrl-names = "default"; | ||
| 74 | |||
| 75 | m25p16@0 { | ||
| 76 | #address-cells = <1>; | ||
| 77 | #size-cells = <1>; | ||
| 78 | compatible = "m25p16"; | ||
| 79 | reg = <0>; | ||
| 80 | spi-max-frequency = <40000000>; | ||
| 81 | mode = <0>; | ||
| 82 | |||
| 83 | partition@0 { | ||
| 84 | reg = <0x0 0xc0000>; | ||
| 85 | label = "u-boot"; | ||
| 86 | }; | ||
| 87 | |||
| 88 | partition@c0000 { | ||
| 89 | reg = <0xc0000 0x20000>; | ||
| 90 | label = "u-boot env"; | ||
| 91 | }; | ||
| 92 | |||
| 93 | partition@e0000 { | ||
| 94 | reg = <0xe0000 0x120000>; | ||
| 95 | label = "data"; | ||
| 96 | }; | ||
| 97 | }; | ||
| 98 | }; | ||
| 99 | |||
| 100 | i2c@11000 { | ||
| 101 | status = "okay"; | ||
| 102 | /* | ||
| 103 | * There is something on the bus at address 0x64. | ||
| 104 | * Not yet identified what it is, maybe the eeprom | ||
| 105 | * for the Atheros WiFi chip? | ||
| 106 | */ | ||
| 107 | }; | ||
| 108 | |||
| 109 | |||
| 110 | serial@12000 { | ||
| 111 | /* Internal on test pins, 3.3v TTL | ||
| 112 | * UART0_RX = Testpoint 65 | ||
| 113 | * UART0_TX = Testpoint 66 | ||
| 114 | * See the Excito Wiki for more details. | ||
| 115 | */ | ||
| 116 | pinctrl-0 = <&pmx_uart0>; | ||
| 117 | pinctrl-names = "default"; | ||
| 118 | status = "okay"; | ||
| 119 | }; | ||
| 120 | |||
| 121 | sata@80000 { | ||
| 122 | /* One internal, the second as eSATA */ | ||
| 123 | status = "okay"; | ||
| 124 | nr-ports = <2>; | ||
| 125 | }; | ||
| 126 | }; | ||
| 127 | |||
| 128 | gpio-leds { | ||
| 129 | /* | ||
| 130 | * There is one LED "port" on the front and the colours | ||
| 131 | * mix together giving some interesting combinations. | ||
| 132 | */ | ||
| 133 | compatible = "gpio-leds"; | ||
| 134 | pinctrl-0 = < &pmx_led_green &pmx_led_red | ||
| 135 | &pmx_led_blue >; | ||
| 136 | pinctrl-names = "default"; | ||
| 137 | |||
| 138 | programming_led { | ||
| 139 | label = "bubba3:green:programming"; | ||
| 140 | gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; | ||
| 141 | default-state = "off"; | ||
| 142 | }; | ||
| 143 | |||
| 144 | error_led { | ||
| 145 | label = "bubba3:red:error"; | ||
| 146 | gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; | ||
| 147 | }; | ||
| 148 | |||
| 149 | active_led { | ||
| 150 | label = "bubba3:blue:active"; | ||
| 151 | gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; | ||
| 152 | }; | ||
| 153 | }; | ||
| 154 | |||
| 155 | gpio-keys { | ||
| 156 | compatible = "gpio-keys"; | ||
| 157 | pinctrl-0 = <&pmx_button_power>; | ||
| 158 | pinctrl-names = "default"; | ||
| 159 | |||
| 160 | power-button { | ||
| 161 | /* On the back */ | ||
| 162 | label = "Power Button"; | ||
| 163 | linux,code = <KEY_POWER>; | ||
| 164 | gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; | ||
| 165 | }; | ||
| 166 | }; | ||
| 167 | |||
| 168 | beeper: beeper { | ||
| 169 | /* 4KHz Piezoelectric buzzer */ | ||
| 170 | compatible = "gpio-beeper"; | ||
| 171 | pinctrl-0 = <&pmx_beeper>; | ||
| 172 | pinctrl-names = "default"; | ||
| 173 | gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; | ||
| 174 | }; | ||
| 175 | }; | ||
| 176 | |||
| 177 | &mdio { | ||
| 178 | status = "okay"; | ||
| 179 | |||
| 180 | ethphy0: ethernet-phy@8 { | ||
| 181 | device_type = "ethernet-phy"; | ||
| 182 | reg = <8>; | ||
| 183 | }; | ||
| 184 | |||
| 185 | ethphy1: ethernet-phy@24 { | ||
| 186 | device_type = "ethernet-phy"; | ||
| 187 | reg = <24>; | ||
| 188 | }; | ||
| 189 | }; | ||
| 190 | |||
| 191 | ð0 { | ||
| 192 | status = "okay"; | ||
| 193 | ethernet0-port@0 { | ||
| 194 | phy-handle = <ðphy0>; | ||
| 195 | }; | ||
| 196 | }; | ||
| 197 | |||
| 198 | ð1 { | ||
| 199 | status = "okay"; | ||
| 200 | ethernet1-port@0 { | ||
| 201 | phy-handle = <ðphy1>; | ||
| 202 | }; | ||
| 203 | }; | ||
| 204 | |||
diff --git a/arch/arm/boot/dts/kirkwood-ds109.dts b/arch/arm/boot/dts/kirkwood-ds109.dts new file mode 100644 index 000000000000..772092c94ca3 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-ds109.dts | |||
| @@ -0,0 +1,41 @@ | |||
| 1 | /* | ||
| 2 | * Andrew Lunn <andrew@lunn.ch> | ||
| 3 | * Ben Peddell <klightspeed@killerwolves.net> | ||
| 4 | * | ||
| 5 | * This file is licensed under the terms of the GNU General Public | ||
| 6 | * License version 2. This program is licensed "as is" without any | ||
| 7 | * warranty of any kind, whether express or implied. | ||
| 8 | */ | ||
| 9 | |||
| 10 | /dts-v1/; | ||
| 11 | |||
| 12 | #include "kirkwood.dtsi" | ||
| 13 | #include "kirkwood-6281.dtsi" | ||
| 14 | #include "kirkwood-synology.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Synology DS109, DS110, DS110jv20"; | ||
| 18 | compatible = "synology,ds109", "synology,ds110jv20", | ||
| 19 | "synology,ds110", "marvell,kirkwood"; | ||
| 20 | |||
| 21 | memory { | ||
| 22 | device_type = "memory"; | ||
| 23 | reg = <0x00000000 0x8000000>; | ||
| 24 | }; | ||
| 25 | |||
| 26 | chosen { | ||
| 27 | bootargs = "console=ttyS0,115200n8"; | ||
| 28 | }; | ||
| 29 | |||
| 30 | gpio-fan-150-32-35 { | ||
| 31 | status = "okay"; | ||
| 32 | }; | ||
| 33 | |||
| 34 | gpio-leds-hdd-21-1 { | ||
| 35 | status = "okay"; | ||
| 36 | }; | ||
| 37 | }; | ||
| 38 | |||
| 39 | &rs5c372 { | ||
| 40 | status = "okay"; | ||
| 41 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-ds110jv10.dts b/arch/arm/boot/dts/kirkwood-ds110jv10.dts new file mode 100644 index 000000000000..aabafbe0da4c --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-ds110jv10.dts | |||
| @@ -0,0 +1,41 @@ | |||
| 1 | /* | ||
| 2 | * Andrew Lunn <andrew@lunn.ch> | ||
| 3 | * Ben Peddell <klightspeed@killerwolves.net> | ||
| 4 | * | ||
| 5 | * This file is licensed under the terms of the GNU General Public | ||
| 6 | * License version 2. This program is licensed "as is" without any | ||
| 7 | * warranty of any kind, whether express or implied. | ||
| 8 | */ | ||
| 9 | |||
| 10 | /dts-v1/; | ||
| 11 | |||
| 12 | #include "kirkwood.dtsi" | ||
| 13 | #include "kirkwood-6281.dtsi" | ||
| 14 | #include "kirkwood-synology.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Synology DS110j v10 and v30"; | ||
| 18 | compatible = "synology,ds110jv10", "synology,ds110jv30", | ||
| 19 | "marvell,kirkwood"; | ||
| 20 | |||
| 21 | memory { | ||
| 22 | device_type = "memory"; | ||
| 23 | reg = <0x00000000 0x8000000>; | ||
| 24 | }; | ||
| 25 | |||
| 26 | chosen { | ||
| 27 | bootargs = "console=ttyS0,115200n8"; | ||
| 28 | }; | ||
| 29 | |||
| 30 | gpio-fan-150-32-35 { | ||
| 31 | status = "okay"; | ||
| 32 | }; | ||
| 33 | |||
| 34 | gpio-leds-hdd-21-1 { | ||
| 35 | status = "okay"; | ||
| 36 | }; | ||
| 37 | }; | ||
| 38 | |||
| 39 | &s35390a { | ||
| 40 | status = "okay"; | ||
| 41 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-ds111.dts b/arch/arm/boot/dts/kirkwood-ds111.dts new file mode 100644 index 000000000000..16ec7fbab573 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-ds111.dts | |||
| @@ -0,0 +1,44 @@ | |||
| 1 | /* | ||
| 2 | * Andrew Lunn <andrew@lunn.ch> | ||
| 3 | * Ben Peddell <klightspeed@killerwolves.net> | ||
| 4 | * | ||
| 5 | * This file is licensed under the terms of the GNU General Public | ||
| 6 | * License version 2. This program is licensed "as is" without any | ||
| 7 | * warranty of any kind, whether express or implied. | ||
| 8 | */ | ||
| 9 | |||
| 10 | /dts-v1/; | ||
| 11 | |||
| 12 | #include "kirkwood.dtsi" | ||
| 13 | #include "kirkwood-6282.dtsi" | ||
| 14 | #include "kirkwood-synology.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Synology DS111"; | ||
| 18 | compatible = "synology,ds111", "marvell,kirkwood"; | ||
| 19 | |||
| 20 | memory { | ||
| 21 | device_type = "memory"; | ||
| 22 | reg = <0x00000000 0x8000000>; | ||
| 23 | }; | ||
| 24 | |||
| 25 | chosen { | ||
| 26 | bootargs = "console=ttyS0,115200n8"; | ||
| 27 | }; | ||
| 28 | |||
| 29 | gpio-fan-100-15-35-1 { | ||
| 30 | status = "okay"; | ||
| 31 | }; | ||
| 32 | |||
| 33 | gpio-leds-hdd-21-1 { | ||
| 34 | status = "okay"; | ||
| 35 | }; | ||
| 36 | }; | ||
| 37 | |||
| 38 | &s35390a { | ||
| 39 | status = "okay"; | ||
| 40 | }; | ||
| 41 | |||
| 42 | &pcie2 { | ||
| 43 | status = "okay"; | ||
| 44 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-ds112.dts b/arch/arm/boot/dts/kirkwood-ds112.dts new file mode 100644 index 000000000000..cff1b2388765 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-ds112.dts | |||
| @@ -0,0 +1,48 @@ | |||
| 1 | /* | ||
| 2 | * Andrew Lunn <andrew@lunn.ch> | ||
| 3 | * Ben Peddell <klightspeed@killerwolves.net> | ||
| 4 | * | ||
| 5 | * This file is licensed under the terms of the GNU General Public | ||
| 6 | * License version 2. This program is licensed "as is" without any | ||
| 7 | * warranty of any kind, whether express or implied. | ||
| 8 | */ | ||
| 9 | |||
| 10 | /dts-v1/; | ||
| 11 | |||
| 12 | #include "kirkwood.dtsi" | ||
| 13 | #include "kirkwood-6282.dtsi" | ||
| 14 | #include "kirkwood-synology.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Synology DS111"; | ||
| 18 | compatible = "synology,ds111", "marvell,kirkwood"; | ||
| 19 | |||
| 20 | memory { | ||
| 21 | device_type = "memory"; | ||
| 22 | reg = <0x00000000 0x8000000>; | ||
| 23 | }; | ||
| 24 | |||
| 25 | chosen { | ||
| 26 | bootargs = "console=ttyS0,115200n8"; | ||
| 27 | }; | ||
| 28 | |||
| 29 | gpio-fan-100-15-35-1 { | ||
| 30 | status = "okay"; | ||
| 31 | }; | ||
| 32 | |||
| 33 | gpio-leds-21-2 { | ||
| 34 | status = "okay"; | ||
| 35 | }; | ||
| 36 | |||
| 37 | regulators-hdd-30 { | ||
| 38 | status = "okay"; | ||
| 39 | }; | ||
| 40 | }; | ||
| 41 | |||
| 42 | &s35390a { | ||
| 43 | status = "okay"; | ||
| 44 | }; | ||
| 45 | |||
| 46 | &pcie2 { | ||
| 47 | status = "okay"; | ||
| 48 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-ds209.dts b/arch/arm/boot/dts/kirkwood-ds209.dts new file mode 100644 index 000000000000..330411993d38 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-ds209.dts | |||
| @@ -0,0 +1,44 @@ | |||
| 1 | /* | ||
| 2 | * Andrew Lunn <andrew@lunn.ch> | ||
| 3 | * Ben Peddell <klightspeed@killerwolves.net> | ||
| 4 | * | ||
| 5 | * This file is licensed under the terms of the GNU General Public | ||
| 6 | * License version 2. This program is licensed "as is" without any | ||
| 7 | * warranty of any kind, whether express or implied. | ||
| 8 | */ | ||
| 9 | |||
| 10 | /dts-v1/; | ||
| 11 | |||
| 12 | #include "kirkwood.dtsi" | ||
| 13 | #include "kirkwood-6281.dtsi" | ||
| 14 | #include "kirkwood-synology.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Synology DS209"; | ||
| 18 | compatible = "synology,ds209", "marvell,kirkwood"; | ||
| 19 | |||
| 20 | memory { | ||
| 21 | device_type = "memory"; | ||
| 22 | reg = <0x00000000 0x8000000>; | ||
| 23 | }; | ||
| 24 | |||
| 25 | chosen { | ||
| 26 | bootargs = "console=ttyS0,115200n8"; | ||
| 27 | }; | ||
| 28 | |||
| 29 | gpio-fan-150-32-35 { | ||
| 30 | status = "okay"; | ||
| 31 | }; | ||
| 32 | |||
| 33 | gpio-leds-hdd-21-2 { | ||
| 34 | status = "okay"; | ||
| 35 | }; | ||
| 36 | |||
| 37 | regulators-hdd-31 { | ||
| 38 | status = "okay"; | ||
| 39 | }; | ||
| 40 | }; | ||
| 41 | |||
| 42 | &rs5c372 { | ||
| 43 | status = "okay"; | ||
| 44 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-ds210.dts b/arch/arm/boot/dts/kirkwood-ds210.dts new file mode 100644 index 000000000000..6052eaa37d4f --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-ds210.dts | |||
| @@ -0,0 +1,46 @@ | |||
| 1 | /* | ||
| 2 | * Andrew Lunn <andrew@lunn.ch> | ||
| 3 | * Ben Peddell <klightspeed@killerwolves.net> | ||
| 4 | * | ||
| 5 | * This file is licensed under the terms of the GNU General Public | ||
| 6 | * License version 2. This program is licensed "as is" without any | ||
| 7 | * warranty of any kind, whether express or implied. | ||
| 8 | */ | ||
| 9 | |||
| 10 | /dts-v1/; | ||
| 11 | |||
| 12 | #include "kirkwood.dtsi" | ||
| 13 | #include "kirkwood-6281.dtsi" | ||
| 14 | #include "kirkwood-synology.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Synology DS210 v10, v20, v30, DS211j"; | ||
| 18 | compatible = "synology,ds210jv10", "synology,ds210jv20", | ||
| 19 | "synology,ds210jv30", "synology,ds211j", | ||
| 20 | "marvell,kirkwood"; | ||
| 21 | |||
| 22 | memory { | ||
| 23 | device_type = "memory"; | ||
| 24 | reg = <0x00000000 0x8000000>; | ||
| 25 | }; | ||
| 26 | |||
| 27 | chosen { | ||
| 28 | bootargs = "console=ttyS0,115200n8"; | ||
| 29 | }; | ||
| 30 | |||
| 31 | gpio-fan-150-32-35 { | ||
| 32 | status = "okay"; | ||
| 33 | }; | ||
| 34 | |||
| 35 | gpio-leds-hdd-21-2 { | ||
| 36 | status = "okay"; | ||
| 37 | }; | ||
| 38 | |||
| 39 | regulators-hdd-31 { | ||
| 40 | status = "okay"; | ||
| 41 | }; | ||
| 42 | }; | ||
| 43 | |||
| 44 | &s35390a { | ||
| 45 | status = "okay"; | ||
| 46 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-ds212.dts b/arch/arm/boot/dts/kirkwood-ds212.dts new file mode 100644 index 000000000000..7f76cd30e84e --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-ds212.dts | |||
| @@ -0,0 +1,47 @@ | |||
| 1 | /* | ||
| 2 | * Andrew Lunn <andrew@lunn.ch> | ||
| 3 | * Ben Peddell <klightspeed@killerwolves.net> | ||
| 4 | * | ||
| 5 | * This file is licensed under the terms of the GNU General Public | ||
| 6 | * License version 2. This program is licensed "as is" without any | ||
| 7 | * warranty of any kind, whether express or implied. | ||
| 8 | */ | ||
| 9 | |||
| 10 | /dts-v1/; | ||
| 11 | |||
| 12 | #include "kirkwood.dtsi" | ||
| 13 | #include "kirkwood-6282.dtsi" | ||
| 14 | #include "kirkwood-synology.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Synology DS212, DS212p v10, v20, DS213air v10, DS213 v10"; | ||
| 18 | compatible = "synology,ds212", "synology,ds212pv10", | ||
| 19 | "synology,ds212pv10", "synology,ds212pv20", | ||
| 20 | "synology,ds213airv10", "synology,ds213v10", | ||
| 21 | "marvell,kirkwood"; | ||
| 22 | |||
| 23 | memory { | ||
| 24 | device_type = "memory"; | ||
| 25 | reg = <0x00000000 0x8000000>; | ||
| 26 | }; | ||
| 27 | |||
| 28 | chosen { | ||
| 29 | bootargs = "console=ttyS0,115200n8"; | ||
| 30 | }; | ||
| 31 | |||
| 32 | gpio-fan-100-15-35-1 { | ||
| 33 | status = "okay"; | ||
| 34 | }; | ||
| 35 | |||
| 36 | gpio-leds-hdd-21-2 { | ||
| 37 | status = "okay"; | ||
| 38 | }; | ||
| 39 | }; | ||
| 40 | |||
| 41 | &s35390a { | ||
| 42 | status = "okay"; | ||
| 43 | }; | ||
| 44 | |||
| 45 | &pcie2 { | ||
| 46 | status = "okay"; | ||
| 47 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-ds212j.dts b/arch/arm/boot/dts/kirkwood-ds212j.dts new file mode 100644 index 000000000000..1f83a00f1f74 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-ds212j.dts | |||
| @@ -0,0 +1,41 @@ | |||
| 1 | /* | ||
| 2 | * Andrew Lunn <andrew@lunn.ch> | ||
| 3 | * Ben Peddell <klightspeed@killerwolves.net> | ||
| 4 | * | ||
| 5 | * This file is licensed under the terms of the GNU General Public | ||
| 6 | * License version 2. This program is licensed "as is" without any | ||
| 7 | * warranty of any kind, whether express or implied. | ||
| 8 | */ | ||
| 9 | |||
| 10 | /dts-v1/; | ||
| 11 | |||
| 12 | #include "kirkwood.dtsi" | ||
| 13 | #include "kirkwood-6281.dtsi" | ||
| 14 | #include "kirkwood-synology.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Synology DS212j v10, v20"; | ||
| 18 | compatible = "synology,ds212jv10", "synology,ds212jv20", | ||
| 19 | "marvell,kirkwood"; | ||
| 20 | |||
| 21 | memory { | ||
| 22 | device_type = "memory"; | ||
| 23 | reg = <0x00000000 0x8000000>; | ||
| 24 | }; | ||
| 25 | |||
| 26 | chosen { | ||
| 27 | bootargs = "console=ttyS0,115200n8"; | ||
| 28 | }; | ||
| 29 | |||
| 30 | gpio-fan-100-32-35 { | ||
| 31 | status = "okay"; | ||
| 32 | }; | ||
| 33 | |||
| 34 | gpio-leds-hdd-21-2 { | ||
| 35 | status = "okay"; | ||
| 36 | }; | ||
| 37 | }; | ||
| 38 | |||
| 39 | &s35390a { | ||
| 40 | status = "okay"; | ||
| 41 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-ds409.dts b/arch/arm/boot/dts/kirkwood-ds409.dts new file mode 100644 index 000000000000..0a573add44a2 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-ds409.dts | |||
| @@ -0,0 +1,48 @@ | |||
| 1 | /* | ||
| 2 | * Andrew Lunn <andrew@lunn.ch> | ||
| 3 | * Ben Peddell <klightspeed@killerwolves.net> | ||
| 4 | * | ||
| 5 | * This file is licensed under the terms of the GNU General Public | ||
| 6 | * License version 2. This program is licensed "as is" without any | ||
| 7 | * warranty of any kind, whether express or implied. | ||
| 8 | */ | ||
| 9 | |||
| 10 | /dts-v1/; | ||
| 11 | |||
| 12 | #include "kirkwood.dtsi" | ||
| 13 | #include "kirkwood-6281.dtsi" | ||
| 14 | #include "kirkwood-synology.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Synology DS409, DS410j"; | ||
| 18 | compatible = "synology,ds409", "synology,ds410j", "marvell,kirkwood"; | ||
| 19 | |||
| 20 | memory { | ||
| 21 | device_type = "memory"; | ||
| 22 | reg = <0x00000000 0x8000000>; | ||
| 23 | }; | ||
| 24 | |||
| 25 | chosen { | ||
| 26 | bootargs = "console=ttyS0,115200n8"; | ||
| 27 | }; | ||
| 28 | |||
| 29 | gpio-fan-150-15-18 { | ||
| 30 | status = "okay"; | ||
| 31 | }; | ||
| 32 | |||
| 33 | gpio-leds-hdd-36 { | ||
| 34 | status = "okay"; | ||
| 35 | }; | ||
| 36 | |||
| 37 | gpio-leds-alarm-12 { | ||
| 38 | status = "okay"; | ||
| 39 | }; | ||
| 40 | }; | ||
| 41 | |||
| 42 | ð1 { | ||
| 43 | status = "okay"; | ||
| 44 | }; | ||
| 45 | |||
| 46 | &rs5c372 { | ||
| 47 | status = "okay"; | ||
| 48 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-ds409slim.dts b/arch/arm/boot/dts/kirkwood-ds409slim.dts new file mode 100644 index 000000000000..1848a6245fd3 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-ds409slim.dts | |||
| @@ -0,0 +1,40 @@ | |||
| 1 | /* | ||
| 2 | * Andrew Lunn <andrew@lunn.ch> | ||
| 3 | * Ben Peddell <klightspeed@killerwolves.net> | ||
| 4 | * | ||
| 5 | * This file is licensed under the terms of the GNU General Public | ||
| 6 | * License version 2. This program is licensed "as is" without any | ||
| 7 | * warranty of any kind, whether express or implied. | ||
| 8 | */ | ||
| 9 | |||
| 10 | /dts-v1/; | ||
| 11 | |||
| 12 | #include "kirkwood.dtsi" | ||
| 13 | #include "kirkwood-6281.dtsi" | ||
| 14 | #include "kirkwood-synology.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Synology 409slim"; | ||
| 18 | compatible = "synology,ds409slim", "marvell,kirkwood"; | ||
| 19 | |||
| 20 | memory { | ||
| 21 | device_type = "memory"; | ||
| 22 | reg = <0x00000000 0x8000000>; | ||
| 23 | }; | ||
| 24 | |||
| 25 | chosen { | ||
| 26 | bootargs = "console=ttyS0,115200n8"; | ||
| 27 | }; | ||
| 28 | |||
| 29 | gpio-fan-150-32-35 { | ||
| 30 | status = "okay"; | ||
| 31 | }; | ||
| 32 | |||
| 33 | gpio-leds-hdd-20 { | ||
| 34 | status = "okay"; | ||
| 35 | }; | ||
| 36 | }; | ||
| 37 | |||
| 38 | &rs5c372 { | ||
| 39 | status = "okay"; | ||
| 40 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-ds411.dts b/arch/arm/boot/dts/kirkwood-ds411.dts new file mode 100644 index 000000000000..a1737b4311c6 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-ds411.dts | |||
| @@ -0,0 +1,52 @@ | |||
| 1 | /* | ||
| 2 | * Andrew Lunn <andrew@lunn.ch> | ||
| 3 | * Ben Peddell <klightspeed@killerwolves.net> | ||
| 4 | * | ||
| 5 | * This file is licensed under the terms of the GNU General Public | ||
| 6 | * License version 2. This program is licensed "as is" without any | ||
| 7 | * warranty of any kind, whether express or implied. | ||
| 8 | */ | ||
| 9 | |||
| 10 | /dts-v1/; | ||
| 11 | |||
| 12 | #include "kirkwood.dtsi" | ||
| 13 | #include "kirkwood-6282.dtsi" | ||
| 14 | #include "kirkwood-synology.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Synology DS411, DS413jv10"; | ||
| 18 | compatible = "synology,ds411", "synology,ds413jv10", "marvell,kirkwood"; | ||
| 19 | |||
| 20 | memory { | ||
| 21 | device_type = "memory"; | ||
| 22 | reg = <0x00000000 0x8000000>; | ||
| 23 | }; | ||
| 24 | |||
| 25 | chosen { | ||
| 26 | bootargs = "console=ttyS0,115200n8"; | ||
| 27 | }; | ||
| 28 | |||
| 29 | gpio-fan-100-15-35-1 { | ||
| 30 | status = "okay"; | ||
| 31 | }; | ||
| 32 | |||
| 33 | gpio-leds-hdd-36 { | ||
| 34 | status = "okay"; | ||
| 35 | }; | ||
| 36 | |||
| 37 | regulators-hdd-34 { | ||
| 38 | status = "okay"; | ||
| 39 | }; | ||
| 40 | }; | ||
| 41 | |||
| 42 | ð1 { | ||
| 43 | status = "okay"; | ||
| 44 | }; | ||
| 45 | |||
| 46 | &s35390a { | ||
| 47 | status = "okay"; | ||
| 48 | }; | ||
| 49 | |||
| 50 | &pcie2 { | ||
| 51 | status = "okay"; | ||
| 52 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-ds411j.dts b/arch/arm/boot/dts/kirkwood-ds411j.dts new file mode 100644 index 000000000000..0cde914eceae --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-ds411j.dts | |||
| @@ -0,0 +1,48 @@ | |||
| 1 | /* | ||
| 2 | * Andrew Lunn <andrew@lunn.ch> | ||
| 3 | * Ben Peddell <klightspeed@killerwolves.net> | ||
| 4 | * | ||
| 5 | * This file is licensed under the terms of the GNU General Public | ||
| 6 | * License version 2. This program is licensed "as is" without any | ||
| 7 | * warranty of any kind, whether express or implied. | ||
| 8 | */ | ||
| 9 | |||
| 10 | /dts-v1/; | ||
| 11 | |||
| 12 | #include "kirkwood.dtsi" | ||
| 13 | #include "kirkwood-6281.dtsi" | ||
| 14 | #include "kirkwood-synology.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Synology DS411j"; | ||
| 18 | compatible = "synology,ds411j", "marvell,kirkwood"; | ||
| 19 | |||
| 20 | memory { | ||
| 21 | device_type = "memory"; | ||
| 22 | reg = <0x00000000 0x8000000>; | ||
| 23 | }; | ||
| 24 | |||
| 25 | chosen { | ||
| 26 | bootargs = "console=ttyS0,115200n8"; | ||
| 27 | }; | ||
| 28 | |||
| 29 | gpio-fan-150-15-18 { | ||
| 30 | status = "okay"; | ||
| 31 | }; | ||
| 32 | |||
| 33 | gpio-leds-hdd-36 { | ||
| 34 | status = "okay"; | ||
| 35 | }; | ||
| 36 | |||
| 37 | gpio-leds-alarm-12 { | ||
| 38 | status = "okay"; | ||
| 39 | }; | ||
| 40 | }; | ||
| 41 | |||
| 42 | ð1 { | ||
| 43 | status = "okay"; | ||
| 44 | }; | ||
| 45 | |||
| 46 | &s35390a { | ||
| 47 | status = "okay"; | ||
| 48 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-ds411slim.dts b/arch/arm/boot/dts/kirkwood-ds411slim.dts new file mode 100644 index 000000000000..aef0cadc2c78 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-ds411slim.dts | |||
| @@ -0,0 +1,48 @@ | |||
| 1 | /* | ||
| 2 | * Andrew Lunn <andrew@lunn.ch> | ||
| 3 | * Ben Peddell <klightspeed@killerwolves.net> | ||
| 4 | * | ||
| 5 | * This file is licensed under the terms of the GNU General Public | ||
| 6 | * License version 2. This program is licensed "as is" without any | ||
| 7 | * warranty of any kind, whether express or implied. | ||
| 8 | */ | ||
| 9 | |||
| 10 | /dts-v1/; | ||
| 11 | |||
| 12 | #include "kirkwood.dtsi" | ||
| 13 | #include "kirkwood-6282.dtsi" | ||
| 14 | #include "kirkwood-synology.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Synology DS411slim"; | ||
| 18 | compatible = "synology,ds411slim", "marvell,kirkwood"; | ||
| 19 | |||
| 20 | memory { | ||
| 21 | device_type = "memory"; | ||
| 22 | reg = <0x00000000 0x8000000>; | ||
| 23 | }; | ||
| 24 | |||
| 25 | chosen { | ||
| 26 | bootargs = "console=ttyS0,115200n8"; | ||
| 27 | }; | ||
| 28 | |||
| 29 | gpio-fan-100-15-35-1 { | ||
| 30 | status = "okay"; | ||
| 31 | }; | ||
| 32 | |||
| 33 | gpio-leds-hdd-36 { | ||
| 34 | status = "okay"; | ||
| 35 | }; | ||
| 36 | }; | ||
| 37 | |||
| 38 | ð1 { | ||
| 39 | status = "okay"; | ||
| 40 | }; | ||
| 41 | |||
| 42 | &s35390a { | ||
| 43 | status = "okay"; | ||
| 44 | }; | ||
| 45 | |||
| 46 | &pcie2 { | ||
| 47 | status = "okay"; | ||
| 48 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts index dc86429756d7..2cb0dc529165 100644 --- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts +++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts | |||
| @@ -122,4 +122,66 @@ | |||
| 122 | gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; | 122 | gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; |
| 123 | }; | 123 | }; |
| 124 | }; | 124 | }; |
| 125 | |||
| 126 | dsa@0 { | ||
| 127 | compatible = "marvell,dsa"; | ||
| 128 | #address-cells = <2>; | ||
| 129 | #size-cells = <0>; | ||
| 130 | |||
| 131 | dsa,ethernet = <ð0>; | ||
| 132 | dsa,mii-bus = <ðphy0>; | ||
| 133 | |||
| 134 | switch@0 { | ||
| 135 | #address-cells = <1>; | ||
| 136 | #size-cells = <0>; | ||
| 137 | reg = <0 0>; /* MDIO address 0, switch 0 in tree */ | ||
| 138 | |||
| 139 | port@0 { | ||
| 140 | reg = <0>; | ||
| 141 | label = "lan1"; | ||
| 142 | }; | ||
| 143 | |||
| 144 | port@1 { | ||
| 145 | reg = <1>; | ||
| 146 | label = "lan2"; | ||
| 147 | }; | ||
| 148 | |||
| 149 | port@2 { | ||
| 150 | reg = <2>; | ||
| 151 | label = "lan3"; | ||
| 152 | }; | ||
| 153 | |||
| 154 | port@3 { | ||
| 155 | reg = <3>; | ||
| 156 | label = "lan4"; | ||
| 157 | }; | ||
| 158 | |||
| 159 | port@4 { | ||
| 160 | reg = <4>; | ||
| 161 | label = "wan"; | ||
| 162 | }; | ||
| 163 | |||
| 164 | port@5 { | ||
| 165 | reg = <5>; | ||
| 166 | label = "cpu"; | ||
| 167 | }; | ||
| 168 | }; | ||
| 169 | }; | ||
| 170 | }; | ||
| 171 | |||
| 172 | &mdio { | ||
| 173 | status = "okay"; | ||
| 174 | |||
| 175 | ethphy0: ethernet-phy@ff { | ||
| 176 | reg = <0xff>; /* No phy attached */ | ||
| 177 | speed = <1000>; | ||
| 178 | duplex = <1>; | ||
| 179 | }; | ||
| 180 | }; | ||
| 181 | |||
| 182 | ð0 { | ||
| 183 | status = "okay"; | ||
| 184 | ethernet0-port@0 { | ||
| 185 | phy-handle = <ðphy0>; | ||
| 186 | }; | ||
| 125 | }; | 187 | }; |
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6192.dts b/arch/arm/boot/dts/kirkwood-rd88f6192.dts new file mode 100644 index 000000000000..e9dd85049297 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-rd88f6192.dts | |||
| @@ -0,0 +1,112 @@ | |||
| 1 | /* | ||
| 2 | * Marvell RD88F6192 Board descrition | ||
| 3 | * | ||
| 4 | * Andrew Lunn <andrew@lunn.ch> | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | * | ||
| 10 | * This file contains the definitions that are common between the three | ||
| 11 | * variants of the Marvell Kirkwood Development Board. | ||
| 12 | */ | ||
| 13 | /dts-v1/; | ||
| 14 | |||
| 15 | #include "kirkwood.dtsi" | ||
| 16 | #include "kirkwood-6192.dtsi" | ||
| 17 | |||
| 18 | / { | ||
| 19 | model = "Marvell RD88F6192 reference design"; | ||
| 20 | compatible = "marvell,rd88f6192", "marvell,kirkwood-88f6192", "marvell,kirkwood"; | ||
| 21 | |||
| 22 | memory { | ||
| 23 | device_type = "memory"; | ||
| 24 | reg = <0x00000000 0x20000000>; | ||
| 25 | }; | ||
| 26 | |||
| 27 | chosen { | ||
| 28 | bootargs = "console=ttyS0,115200n8"; | ||
| 29 | }; | ||
| 30 | |||
| 31 | mbus { | ||
| 32 | pcie-controller { | ||
| 33 | status = "okay"; | ||
| 34 | |||
| 35 | pcie@1,0 { | ||
| 36 | status = "okay"; | ||
| 37 | }; | ||
| 38 | }; | ||
| 39 | }; | ||
| 40 | |||
| 41 | ocp@f1000000 { | ||
| 42 | pinctrl: pinctrl@10000 { | ||
| 43 | pinctrl-0 = <&pmx_usb_power>; | ||
| 44 | pinctrl-names = "default"; | ||
| 45 | |||
| 46 | pmx_usb_power: pmx-usb-power { | ||
| 47 | marvell,pins = "mpp10"; | ||
| 48 | marvell,function = "gpo"; | ||
| 49 | }; | ||
| 50 | }; | ||
| 51 | |||
| 52 | serial@12000 { | ||
| 53 | status = "okay"; | ||
| 54 | |||
| 55 | }; | ||
| 56 | |||
| 57 | spi@10600 { | ||
| 58 | status = "okay"; | ||
| 59 | pinctrl-0 = <&pmx_spi>; | ||
| 60 | pinctrl-names = "default"; | ||
| 61 | |||
| 62 | m25p128@0 { | ||
| 63 | #address-cells = <1>; | ||
| 64 | #size-cells = <1>; | ||
| 65 | compatible = "st,m25p128"; | ||
| 66 | reg = <0>; | ||
| 67 | spi-max-frequency = <20000000>; | ||
| 68 | mode = <0>; | ||
| 69 | }; | ||
| 70 | }; | ||
| 71 | |||
| 72 | sata@80000 { | ||
| 73 | status = "okay"; | ||
| 74 | nr-ports = <2>; | ||
| 75 | }; | ||
| 76 | }; | ||
| 77 | |||
| 78 | regulators { | ||
| 79 | compatible = "simple-bus"; | ||
| 80 | #address-cells = <1>; | ||
| 81 | #size-cells = <0>; | ||
| 82 | pinctrl-0 = <&pmx_usb_power>; | ||
| 83 | pinctrl-names = "default"; | ||
| 84 | |||
| 85 | usb_power: regulator@0 { | ||
| 86 | compatible = "regulator-fixed"; | ||
| 87 | reg = <0>; | ||
| 88 | regulator-name = "USB VBUS"; | ||
| 89 | regulator-min-microvolt = <5000000>; | ||
| 90 | regulator-max-microvolt = <5000000>; | ||
| 91 | enable-active-high; | ||
| 92 | regulator-always-on; | ||
| 93 | regulator-boot-on; | ||
| 94 | gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>; | ||
| 95 | }; | ||
| 96 | }; | ||
| 97 | }; | ||
| 98 | |||
| 99 | &mdio { | ||
| 100 | status = "okay"; | ||
| 101 | |||
| 102 | ethphy0: ethernet-phy@8 { | ||
| 103 | reg = <8>; | ||
| 104 | }; | ||
| 105 | }; | ||
| 106 | |||
| 107 | ð0 { | ||
| 108 | status = "okay"; | ||
| 109 | ethernet0-port@0 { | ||
| 110 | phy-handle = <ðphy0>; | ||
| 111 | }; | ||
| 112 | }; \ No newline at end of file | ||
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-a0.dts b/arch/arm/boot/dts/kirkwood-rd88f6281-a0.dts new file mode 100644 index 000000000000..a803bbb70bc8 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-rd88f6281-a0.dts | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | /* | ||
| 2 | * Marvell RD88F6181 A0 Board descrition | ||
| 3 | * | ||
| 4 | * Andrew Lunn <andrew@lunn.ch> | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | * | ||
| 10 | * This file contains the definitions for the board with the A0 variant of | ||
| 11 | * the SoC. The ethernet switch does not have a "wan" port. | ||
| 12 | */ | ||
| 13 | |||
| 14 | /dts-v1/; | ||
| 15 | #include "kirkwood-rd88f6281.dtsi" | ||
| 16 | |||
| 17 | / { | ||
| 18 | model = "Marvell RD88f6281 Reference design, with A0 SoC"; | ||
| 19 | compatible = "marvell,rd88f6281-a0", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood"; | ||
| 20 | |||
| 21 | dsa@0 { | ||
| 22 | switch@0 { | ||
| 23 | reg = <10 0>; /* MDIO address 10, switch 0 in tree */ | ||
| 24 | }; | ||
| 25 | }; | ||
| 26 | }; \ No newline at end of file | ||
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-a1.dts b/arch/arm/boot/dts/kirkwood-rd88f6281-a1.dts new file mode 100644 index 000000000000..baeebbf1d8c7 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-rd88f6281-a1.dts | |||
| @@ -0,0 +1,31 @@ | |||
| 1 | /* | ||
| 2 | * Marvell RD88F6181 A1 Board descrition | ||
| 3 | * | ||
| 4 | * Andrew Lunn <andrew@lunn.ch> | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | * | ||
| 10 | * This file contains the definitions for the board with the A1 variant of | ||
| 11 | * the SoC. The ethernet switch has a "wan" port. | ||
| 12 | */ | ||
| 13 | |||
| 14 | /dts-v1/; | ||
| 15 | |||
| 16 | #include "kirkwood-rd88f6281.dtsi" | ||
| 17 | |||
| 18 | / { | ||
| 19 | model = "Marvell RD88f6281 Reference design, with A1 SoC"; | ||
| 20 | compatible = "marvell,rd88f6281-a1", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood"; | ||
| 21 | |||
| 22 | dsa@0 { | ||
| 23 | switch@0 { | ||
| 24 | reg = <0 0>; /* MDIO address 0, switch 0 in tree */ | ||
| 25 | port@4 { | ||
| 26 | reg = <4>; | ||
| 27 | label = "wan"; | ||
| 28 | }; | ||
| 29 | }; | ||
| 30 | }; | ||
| 31 | }; \ No newline at end of file | ||
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi new file mode 100644 index 000000000000..d6368c39102e --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi | |||
| @@ -0,0 +1,152 @@ | |||
| 1 | /* | ||
| 2 | * Marvell RD88F6181 Common Board descrition | ||
| 3 | * | ||
| 4 | * Andrew Lunn <andrew@lunn.ch> | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | * | ||
| 10 | * This file contains the definitions that are common between the two | ||
| 11 | * variants of the Marvell Kirkwood Development Board. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include "kirkwood.dtsi" | ||
| 15 | #include "kirkwood-6281.dtsi" | ||
| 16 | |||
| 17 | / { | ||
| 18 | memory { | ||
| 19 | device_type = "memory"; | ||
| 20 | reg = <0x00000000 0x20000000>; | ||
| 21 | }; | ||
| 22 | |||
| 23 | chosen { | ||
| 24 | bootargs = "console=ttyS0,115200n8"; | ||
| 25 | }; | ||
| 26 | |||
| 27 | mbus { | ||
| 28 | pcie-controller { | ||
| 29 | status = "okay"; | ||
| 30 | |||
| 31 | pcie@1,0 { | ||
| 32 | status = "okay"; | ||
| 33 | }; | ||
| 34 | }; | ||
| 35 | }; | ||
| 36 | |||
| 37 | ocp@f1000000 { | ||
| 38 | pinctrl: pinctrl@10000 { | ||
| 39 | pinctrl-0 = <&pmx_sdio_cd>; | ||
| 40 | pinctrl-names = "default"; | ||
| 41 | |||
| 42 | pmx_sdio_cd: pmx-sdio-cd { | ||
| 43 | marvell,pins = "mpp28"; | ||
| 44 | marvell,function = "gpio"; | ||
| 45 | }; | ||
| 46 | }; | ||
| 47 | |||
| 48 | serial@12000 { | ||
| 49 | status = "okay"; | ||
| 50 | |||
| 51 | }; | ||
| 52 | |||
| 53 | sata@80000 { | ||
| 54 | status = "okay"; | ||
| 55 | nr-ports = <2>; | ||
| 56 | }; | ||
| 57 | mvsdio@90000 { | ||
| 58 | pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>; | ||
| 59 | pinctrl-names = "default"; | ||
| 60 | status = "okay"; | ||
| 61 | cd-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; | ||
| 62 | /* No WP GPIO */ | ||
| 63 | }; | ||
| 64 | }; | ||
| 65 | |||
| 66 | dsa@0 { | ||
| 67 | compatible = "marvell,dsa"; | ||
| 68 | #address-cells = <2>; | ||
| 69 | #size-cells = <0>; | ||
| 70 | |||
| 71 | dsa,ethernet = <ð0>; | ||
| 72 | dsa,mii-bus = <ðphy1>; | ||
| 73 | |||
| 74 | switch@0 { | ||
| 75 | #address-cells = <1>; | ||
| 76 | #size-cells = <0>; | ||
| 77 | |||
| 78 | port@0 { | ||
| 79 | reg = <0>; | ||
| 80 | label = "lan1"; | ||
| 81 | }; | ||
| 82 | |||
| 83 | port@1 { | ||
| 84 | reg = <1>; | ||
| 85 | label = "lan2"; | ||
| 86 | }; | ||
| 87 | |||
| 88 | port@2 { | ||
| 89 | reg = <2>; | ||
| 90 | label = "lan3"; | ||
| 91 | }; | ||
| 92 | |||
| 93 | port@3 { | ||
| 94 | reg = <3>; | ||
| 95 | label = "lan4"; | ||
| 96 | }; | ||
| 97 | |||
| 98 | port@5 { | ||
| 99 | reg = <5>; | ||
| 100 | label = "cpu"; | ||
| 101 | }; | ||
| 102 | }; | ||
| 103 | }; | ||
| 104 | }; | ||
| 105 | |||
| 106 | &nand { | ||
| 107 | status = "okay"; | ||
| 108 | |||
| 109 | partition@0 { | ||
| 110 | label = "u-boot"; | ||
| 111 | reg = <0x0000000 0x100000>; | ||
| 112 | read-only; | ||
| 113 | }; | ||
| 114 | |||
| 115 | partition@100000 { | ||
| 116 | label = "uImage"; | ||
| 117 | reg = <0x0100000 0x200000>; | ||
| 118 | }; | ||
| 119 | |||
| 120 | partition@300000 { | ||
| 121 | label = "data"; | ||
| 122 | reg = <0x0300000 0x500000>; | ||
| 123 | }; | ||
| 124 | }; | ||
| 125 | |||
| 126 | &mdio { | ||
| 127 | status = "okay"; | ||
| 128 | |||
| 129 | ethphy0: ethernet-phy@0 { | ||
| 130 | reg = <0>; | ||
| 131 | }; | ||
| 132 | |||
| 133 | ethphy1: ethernet-phy@ff { | ||
| 134 | reg = <0xff>; /* No PHY attached */ | ||
| 135 | speed = <1000>; | ||
| 136 | duple = <1>; | ||
| 137 | }; | ||
| 138 | }; | ||
| 139 | |||
| 140 | ð0 { | ||
| 141 | status = "okay"; | ||
| 142 | ethernet0-port@0 { | ||
| 143 | phy-handle = <ðphy0>; | ||
| 144 | }; | ||
| 145 | }; | ||
| 146 | |||
| 147 | ð1 { | ||
| 148 | status = "okay"; | ||
| 149 | ethernet1-port@0 { | ||
| 150 | phy-handle = <ðphy1>; | ||
| 151 | }; | ||
| 152 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-rs212.dts b/arch/arm/boot/dts/kirkwood-rs212.dts new file mode 100644 index 000000000000..93ec3d00c6ab --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-rs212.dts | |||
| @@ -0,0 +1,48 @@ | |||
| 1 | /* | ||
| 2 | * Andrew Lunn <andrew@lunn.ch> | ||
| 3 | * Ben Peddell <klightspeed@killerwolves.net> | ||
| 4 | * | ||
| 5 | * This file is licensed under the terms of the GNU General Public | ||
| 6 | * License version 2. This program is licensed "as is" without any | ||
| 7 | * warranty of any kind, whether express or implied. | ||
| 8 | */ | ||
| 9 | |||
| 10 | /dts-v1/; | ||
| 11 | |||
| 12 | #include "kirkwood.dtsi" | ||
| 13 | #include "kirkwood-6282.dtsi" | ||
| 14 | #include "kirkwood-synology.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Synology RS212"; | ||
| 18 | compatible = "synology,rs212", "marvell,kirkwood"; | ||
| 19 | |||
| 20 | memory { | ||
| 21 | device_type = "memory"; | ||
| 22 | reg = <0x00000000 0x8000000>; | ||
| 23 | }; | ||
| 24 | |||
| 25 | chosen { | ||
| 26 | bootargs = "console=ttyS0,115200n8"; | ||
| 27 | }; | ||
| 28 | |||
| 29 | gpio-fan-100-15-35-3 { | ||
| 30 | status = "okay"; | ||
| 31 | }; | ||
| 32 | |||
| 33 | gpio-leds-hdd-38 { | ||
| 34 | status = "okay"; | ||
| 35 | }; | ||
| 36 | |||
| 37 | regulators-hdd-30-2 { | ||
| 38 | status = "okay"; | ||
| 39 | }; | ||
| 40 | }; | ||
| 41 | |||
| 42 | &s35390a { | ||
| 43 | status = "okay"; | ||
| 44 | }; | ||
| 45 | |||
| 46 | &pcie2 { | ||
| 47 | status = "okay"; | ||
| 48 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-rs409.dts b/arch/arm/boot/dts/kirkwood-rs409.dts new file mode 100644 index 000000000000..311df4e5aa28 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-rs409.dts | |||
| @@ -0,0 +1,44 @@ | |||
| 1 | /* | ||
| 2 | * Andrew Lunn <andrew@lunn.ch> | ||
| 3 | * Ben Peddell <klightspeed@killerwolves.net> | ||
| 4 | * | ||
| 5 | * This file is licensed under the terms of the GNU General Public | ||
| 6 | * License version 2. This program is licensed "as is" without any | ||
| 7 | * warranty of any kind, whether express or implied. | ||
| 8 | */ | ||
| 9 | |||
| 10 | /dts-v1/; | ||
| 11 | |||
| 12 | #include "kirkwood.dtsi" | ||
| 13 | #include "kirkwood-6281.dtsi" | ||
| 14 | #include "kirkwood-synology.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Synology RS409"; | ||
| 18 | compatible = "synology,rs409", "marvell,kirkwood"; | ||
| 19 | |||
| 20 | memory { | ||
| 21 | device_type = "memory"; | ||
| 22 | reg = <0x00000000 0x8000000>; | ||
| 23 | }; | ||
| 24 | |||
| 25 | chosen { | ||
| 26 | bootargs = "console=ttyS0,115200n8"; | ||
| 27 | }; | ||
| 28 | |||
| 29 | gpio-fan-150-15-18 { | ||
| 30 | status = "okay"; | ||
| 31 | }; | ||
| 32 | |||
| 33 | gpio-leds-hdd-36 { | ||
| 34 | status = "okay"; | ||
| 35 | }; | ||
| 36 | }; | ||
| 37 | |||
| 38 | ð1 { | ||
| 39 | status = "okay"; | ||
| 40 | }; | ||
| 41 | |||
| 42 | &rs5c372 { | ||
| 43 | status = "okay"; | ||
| 44 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-rs411.dts b/arch/arm/boot/dts/kirkwood-rs411.dts new file mode 100644 index 000000000000..f90da850bb31 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-rs411.dts | |||
| @@ -0,0 +1,44 @@ | |||
| 1 | /* | ||
| 2 | * Andrew Lunn <andrew@lunn.ch> | ||
| 3 | * Ben Peddell <klightspeed@killerwolves.net> | ||
| 4 | * | ||
| 5 | * This file is licensed under the terms of the GNU General Public | ||
| 6 | * License version 2. This program is licensed "as is" without any | ||
| 7 | * warranty of any kind, whether express or implied. | ||
| 8 | */ | ||
| 9 | |||
| 10 | /dts-v1/; | ||
| 11 | |||
| 12 | #include "kirkwood.dtsi" | ||
| 13 | #include "kirkwood-6282.dtsi" | ||
| 14 | #include "kirkwood-synology.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Synology RS411 RS812"; | ||
| 18 | compatible = "synology,rs411", "synology,rs812", "marvell,kirkwood"; | ||
| 19 | |||
| 20 | memory { | ||
| 21 | device_type = "memory"; | ||
| 22 | reg = <0x00000000 0x8000000>; | ||
| 23 | }; | ||
| 24 | |||
| 25 | chosen { | ||
| 26 | bootargs = "console=ttyS0,115200n8"; | ||
| 27 | }; | ||
| 28 | |||
| 29 | gpio-fan-100-15-35-3 { | ||
| 30 | status = "okay"; | ||
| 31 | }; | ||
| 32 | |||
| 33 | gpio-leds-hdd-36 { | ||
| 34 | status = "okay"; | ||
| 35 | }; | ||
| 36 | }; | ||
| 37 | |||
| 38 | ð1 { | ||
| 39 | status = "okay"; | ||
| 40 | }; | ||
| 41 | |||
| 42 | &s35390a { | ||
| 43 | status = "okay"; | ||
| 44 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-synology.dtsi b/arch/arm/boot/dts/kirkwood-synology.dtsi new file mode 100644 index 000000000000..4227c974729d --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-synology.dtsi | |||
| @@ -0,0 +1,871 @@ | |||
| 1 | /* | ||
| 2 | * Nodes for Marvell 628x Synology devices | ||
| 3 | * | ||
| 4 | * Andrew Lunn <andrew@lunn.ch> | ||
| 5 | * Ben Peddell <klightspeed@killerwolves.net> | ||
| 6 | * | ||
| 7 | * This file is licensed under the terms of the GNU General Public | ||
| 8 | * License version 2. This program is licensed "as is" without any | ||
| 9 | * warranty of any kind, whether express or implied. | ||
| 10 | */ | ||
| 11 | |||
| 12 | / { | ||
| 13 | mbus { | ||
| 14 | pcie-controller { | ||
| 15 | status = "okay"; | ||
| 16 | |||
| 17 | pcie@1,0 { | ||
| 18 | status = "okay"; | ||
| 19 | }; | ||
| 20 | |||
| 21 | pcie2: pcie@2,0 { | ||
| 22 | status = "disabled"; | ||
| 23 | }; | ||
| 24 | }; | ||
| 25 | }; | ||
| 26 | |||
| 27 | ocp@f1000000 { | ||
| 28 | pinctrl: pinctrl@10000 { | ||
| 29 | pmx_alarmled_12: pmx-alarmled-12 { | ||
| 30 | marvell,pins = "mpp12"; | ||
| 31 | marvell,function = "gpio"; | ||
| 32 | }; | ||
| 33 | |||
| 34 | pmx_fanctrl_15: pmx-fanctrl-15 { | ||
| 35 | marvell,pins = "mpp15"; | ||
| 36 | marvell,function = "gpio"; | ||
| 37 | }; | ||
| 38 | |||
| 39 | pmx_fanctrl_16: pmx-fanctrl-16 { | ||
| 40 | marvell,pins = "mpp16"; | ||
| 41 | marvell,function = "gpio"; | ||
| 42 | }; | ||
| 43 | |||
| 44 | pmx_fanctrl_17: pmx-fanctrl-17 { | ||
| 45 | marvell,pins = "mpp17"; | ||
| 46 | marvell,function = "gpio"; | ||
| 47 | }; | ||
| 48 | |||
| 49 | pmx_fanalarm_18: pmx-fanalarm-18 { | ||
| 50 | marvell,pins = "mpp18"; | ||
| 51 | marvell,function = "gpo"; | ||
| 52 | }; | ||
| 53 | |||
| 54 | pmx_hddled_20: pmx-hddled-20 { | ||
| 55 | marvell,pins = "mpp20"; | ||
| 56 | marvell,function = "gpio"; | ||
| 57 | }; | ||
| 58 | |||
| 59 | pmx_hddled_21: pmx-hddled-21 { | ||
| 60 | marvell,pins = "mpp21"; | ||
| 61 | marvell,function = "gpio"; | ||
| 62 | }; | ||
| 63 | |||
| 64 | pmx_hddled_22: pmx-hddled-22 { | ||
| 65 | marvell,pins = "mpp22"; | ||
| 66 | marvell,function = "gpio"; | ||
| 67 | }; | ||
| 68 | |||
| 69 | pmx_hddled_23: pmx-hddled-23 { | ||
| 70 | marvell,pins = "mpp23"; | ||
| 71 | marvell,function = "gpio"; | ||
| 72 | }; | ||
| 73 | |||
| 74 | pmx_hddled_24: pmx-hddled-24 { | ||
| 75 | marvell,pins = "mpp24"; | ||
| 76 | marvell,function = "gpio"; | ||
| 77 | }; | ||
| 78 | |||
| 79 | pmx_hddled_25: pmx-hddled-25 { | ||
| 80 | marvell,pins = "mpp25"; | ||
| 81 | marvell,function = "gpio"; | ||
| 82 | }; | ||
| 83 | |||
| 84 | pmx_hddled_26: pmx-hddled-26 { | ||
| 85 | marvell,pins = "mpp26"; | ||
| 86 | marvell,function = "gpio"; | ||
| 87 | }; | ||
| 88 | |||
| 89 | pmx_hddled_27: pmx-hddled-27 { | ||
| 90 | marvell,pins = "mpp27"; | ||
| 91 | marvell,function = "gpio"; | ||
| 92 | }; | ||
| 93 | |||
| 94 | pmx_hddled_28: pmx-hddled-28 { | ||
| 95 | marvell,pins = "mpp28"; | ||
| 96 | marvell,function = "gpio"; | ||
| 97 | }; | ||
| 98 | |||
| 99 | pmx_hdd1_pwr_29: pmx-hdd1-pwr-29 { | ||
| 100 | marvell,pins = "mpp29"; | ||
| 101 | marvell,function = "gpio"; | ||
| 102 | }; | ||
| 103 | |||
| 104 | pmx_hdd1_pwr_30: pmx-hdd-pwr-30 { | ||
| 105 | marvell,pins = "mpp30"; | ||
| 106 | marvell,function = "gpio"; | ||
| 107 | }; | ||
| 108 | |||
| 109 | pmx_hdd2_pwr_31: pmx-hdd2-pwr-31 { | ||
| 110 | marvell,pins = "mpp31"; | ||
| 111 | marvell,function = "gpio"; | ||
| 112 | }; | ||
| 113 | |||
| 114 | pmx_fanctrl_32: pmx-fanctrl-32 { | ||
| 115 | marvell,pins = "mpp32"; | ||
| 116 | marvell,function = "gpio"; | ||
| 117 | }; | ||
| 118 | |||
| 119 | pmx_fanctrl_33: pmx-fanctrl-33 { | ||
| 120 | marvell,pins = "mpp33"; | ||
| 121 | marvell,function = "gpo"; | ||
| 122 | }; | ||
| 123 | |||
| 124 | pmx_fanctrl_34: pmx-fanctrl-34 { | ||
| 125 | marvell,pins = "mpp34"; | ||
| 126 | marvell,function = "gpio"; | ||
| 127 | }; | ||
| 128 | |||
| 129 | pmx_hdd2_pwr_34: pmx-hdd2-pwr-34 { | ||
| 130 | marvell,pins = "mpp34"; | ||
| 131 | marvell,function = "gpio"; | ||
| 132 | }; | ||
| 133 | |||
| 134 | pmx_fanalarm_35: pmx-fanalarm-35 { | ||
| 135 | marvell,pins = "mpp35"; | ||
| 136 | marvell,function = "gpio"; | ||
| 137 | }; | ||
| 138 | |||
| 139 | pmx_hddled_36: pmx-hddled-36 { | ||
| 140 | marvell,pins = "mpp36"; | ||
| 141 | marvell,function = "gpio"; | ||
| 142 | }; | ||
| 143 | |||
| 144 | pmx_hddled_37: pmx-hddled-37 { | ||
| 145 | marvell,pins = "mpp37"; | ||
| 146 | marvell,function = "gpio"; | ||
| 147 | }; | ||
| 148 | |||
| 149 | pmx_hddled_38: pmx-hddled-38 { | ||
| 150 | marvell,pins = "mpp38"; | ||
| 151 | marvell,function = "gpio"; | ||
| 152 | }; | ||
| 153 | |||
| 154 | pmx_hddled_39: pmx-hddled-39 { | ||
| 155 | marvell,pins = "mpp39"; | ||
| 156 | marvell,function = "gpio"; | ||
| 157 | }; | ||
| 158 | |||
| 159 | pmx_hddled_40: pmx-hddled-40 { | ||
| 160 | marvell,pins = "mpp40"; | ||
| 161 | marvell,function = "gpio"; | ||
| 162 | }; | ||
| 163 | |||
| 164 | pmx_hddled_41: pmx-hddled-41 { | ||
| 165 | marvell,pins = "mpp41"; | ||
| 166 | marvell,function = "gpio"; | ||
| 167 | }; | ||
| 168 | |||
| 169 | pmx_hddled_42: pmx-hddled-42 { | ||
| 170 | marvell,pins = "mpp42"; | ||
| 171 | marvell,function = "gpio"; | ||
| 172 | }; | ||
| 173 | |||
| 174 | pmx_hddled_43: pmx-hddled-43 { | ||
| 175 | marvell,pins = "mpp43"; | ||
| 176 | marvell,function = "gpio"; | ||
| 177 | }; | ||
| 178 | |||
| 179 | pmx_hddled_44: pmx-hddled-44 { | ||
| 180 | marvell,pins = "mpp44"; | ||
| 181 | marvell,function = "gpio"; | ||
| 182 | }; | ||
| 183 | |||
| 184 | pmx_hddled_45: pmx-hddled-45 { | ||
| 185 | marvell,pins = "mpp45"; | ||
| 186 | marvell,function = "gpio"; | ||
| 187 | }; | ||
| 188 | |||
| 189 | pmx_hdd3_pwr_44: pmx-hdd3-pwr-44 { | ||
| 190 | marvell,pins = "mpp44"; | ||
| 191 | marvell,function = "gpio"; | ||
| 192 | }; | ||
| 193 | |||
| 194 | pmx_hdd4_pwr_45: pmx-hdd4-pwr-45 { | ||
| 195 | marvell,pins = "mpp45"; | ||
| 196 | marvell,function = "gpio"; | ||
| 197 | }; | ||
| 198 | |||
| 199 | pmx_fanalarm_44: pmx-fanalarm-44 { | ||
| 200 | marvell,pins = "mpp44"; | ||
| 201 | marvell,function = "gpio"; | ||
| 202 | }; | ||
| 203 | |||
| 204 | pmx_fanalarm_45: pmx-fanalarm-45 { | ||
| 205 | marvell,pins = "mpp45"; | ||
| 206 | marvell,function = "gpio"; | ||
| 207 | }; | ||
| 208 | }; | ||
| 209 | |||
| 210 | rtc@10300 { | ||
| 211 | status = "disabled"; | ||
| 212 | }; | ||
| 213 | |||
| 214 | spi@10600 { | ||
| 215 | status = "okay"; | ||
| 216 | pinctrl-0 = <&pmx_spi>; | ||
| 217 | pinctrl-names = "default"; | ||
| 218 | |||
| 219 | m25p80@0 { | ||
| 220 | #address-cells = <1>; | ||
| 221 | #size-cells = <1>; | ||
| 222 | compatible = "st,m25p80"; | ||
| 223 | reg = <0>; | ||
| 224 | spi-max-frequency = <20000000>; | ||
| 225 | mode = <0>; | ||
| 226 | |||
| 227 | partition@00000000 { | ||
| 228 | reg = <0x00000000 0x00080000>; | ||
| 229 | label = "RedBoot"; | ||
| 230 | }; | ||
| 231 | |||
| 232 | partition@00080000 { | ||
| 233 | reg = <0x00080000 0x00200000>; | ||
| 234 | label = "zImage"; | ||
| 235 | }; | ||
| 236 | |||
| 237 | partition@00280000 { | ||
| 238 | reg = <0x00280000 0x00140000>; | ||
| 239 | label = "rd.gz"; | ||
| 240 | }; | ||
| 241 | |||
| 242 | partition@003c0000 { | ||
| 243 | reg = <0x003c0000 0x00010000>; | ||
| 244 | label = "vendor"; | ||
| 245 | }; | ||
| 246 | |||
| 247 | partition@003d0000 { | ||
| 248 | reg = <0x003d0000 0x00020000>; | ||
| 249 | label = "RedBoot config"; | ||
| 250 | }; | ||
| 251 | |||
| 252 | partition@003f0000 { | ||
| 253 | reg = <0x003f0000 0x00010000>; | ||
| 254 | label = "FIS directory"; | ||
| 255 | }; | ||
| 256 | }; | ||
| 257 | }; | ||
| 258 | |||
| 259 | i2c@11000 { | ||
| 260 | status = "okay"; | ||
| 261 | clock-frequency = <400000>; | ||
| 262 | pinctrl-0 = <&pmx_twsi0>; | ||
| 263 | pinctrl-names = "default"; | ||
| 264 | |||
| 265 | rs5c372: rs5c372@32 { | ||
| 266 | status = "disabled"; | ||
| 267 | compatible = "ricoh,rs5c372"; | ||
| 268 | reg = <0x32>; | ||
| 269 | }; | ||
| 270 | |||
| 271 | s35390a: s35390a@30 { | ||
| 272 | status = "disabled"; | ||
| 273 | compatible = "ssi,s35390a"; | ||
| 274 | reg = <0x30>; | ||
| 275 | }; | ||
| 276 | }; | ||
| 277 | |||
| 278 | serial@12000 { | ||
| 279 | status = "okay"; | ||
| 280 | pinctrl-0 = <&pmx_uart0>; | ||
| 281 | pinctrl-names = "default"; | ||
| 282 | }; | ||
| 283 | |||
| 284 | serial@12100 { | ||
| 285 | status = "okay"; | ||
| 286 | pinctrl-0 = <&pmx_uart1>; | ||
| 287 | pinctrl-names = "default"; | ||
| 288 | }; | ||
| 289 | |||
| 290 | poweroff@12100 { | ||
| 291 | compatible = "synology,power-off"; | ||
| 292 | reg = <0x12100 0x100>; | ||
| 293 | clocks = <&gate_clk 7>; | ||
| 294 | }; | ||
| 295 | |||
| 296 | sata@80000 { | ||
| 297 | pinctrl-0 = <&pmx_sata0 &pmx_sata1>; | ||
| 298 | pinctrl-names = "default"; | ||
| 299 | status = "okay"; | ||
| 300 | nr-ports = <2>; | ||
| 301 | }; | ||
| 302 | }; | ||
| 303 | |||
| 304 | gpio-fan-150-32-35 { | ||
| 305 | status = "disabled"; | ||
| 306 | compatible = "gpio-fan"; | ||
| 307 | pinctrl-0 = <&pmx_fanctrl_32 &pmx_fanctrl_33 &pmx_fanctrl_34 | ||
| 308 | &pmx_fanalarm_35>; | ||
| 309 | pinctrl-names = "default"; | ||
| 310 | gpios = <&gpio1 0 GPIO_ACTIVE_HIGH | ||
| 311 | &gpio1 1 GPIO_ACTIVE_HIGH | ||
| 312 | &gpio1 2 GPIO_ACTIVE_HIGH>; | ||
| 313 | gpio-fan,speed-map = < 0 0 | ||
| 314 | 2200 1 | ||
| 315 | 2500 2 | ||
| 316 | 3000 4 | ||
| 317 | 3300 3 | ||
| 318 | 3700 5 | ||
| 319 | 3800 6 | ||
| 320 | 4200 7 >; | ||
| 321 | }; | ||
| 322 | |||
| 323 | gpio-fan-150-15-18 { | ||
| 324 | status = "disabled"; | ||
| 325 | compatible = "gpio-fan"; | ||
| 326 | pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 | ||
| 327 | &pmx_fanalarm_18>; | ||
| 328 | pinctrl-names = "default"; | ||
| 329 | gpios = <&gpio0 15 GPIO_ACTIVE_HIGH | ||
| 330 | &gpio0 16 GPIO_ACTIVE_HIGH | ||
| 331 | &gpio0 17 GPIO_ACTIVE_HIGH>; | ||
| 332 | alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; | ||
| 333 | gpio-fan,speed-map = < 0 0 | ||
| 334 | 2200 1 | ||
| 335 | 2500 2 | ||
| 336 | 3000 4 | ||
| 337 | 3300 3 | ||
| 338 | 3700 5 | ||
| 339 | 3800 6 | ||
| 340 | 4200 7 >; | ||
| 341 | }; | ||
| 342 | |||
| 343 | gpio-fan-100-32-35 { | ||
| 344 | status = "disabled"; | ||
| 345 | compatible = "gpio-fan"; | ||
| 346 | pinctrl-0 = <&pmx_fanctrl_32 &pmx_fanctrl_33 &pmx_fanctrl_34 | ||
| 347 | &pmx_fanalarm_35>; | ||
| 348 | pinctrl-names = "default"; | ||
| 349 | gpios = <&gpio1 0 GPIO_ACTIVE_HIGH | ||
| 350 | &gpio1 1 GPIO_ACTIVE_HIGH | ||
| 351 | &gpio1 2 GPIO_ACTIVE_HIGH>; | ||
| 352 | alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; | ||
| 353 | gpio-fan,speed-map = < 0 0 | ||
| 354 | 2500 1 | ||
| 355 | 3100 2 | ||
| 356 | 3800 3 | ||
| 357 | 4600 4 | ||
| 358 | 4800 5 | ||
| 359 | 4900 6 | ||
| 360 | 5000 7 >; | ||
| 361 | }; | ||
| 362 | |||
| 363 | gpio-fan-100-15-18 { | ||
| 364 | status = "disabled"; | ||
| 365 | compatible = "gpio-fan"; | ||
| 366 | pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 | ||
| 367 | &pmx_fanalarm_18>; | ||
| 368 | pinctrl-names = "default"; | ||
| 369 | gpios = <&gpio0 15 GPIO_ACTIVE_HIGH | ||
| 370 | &gpio0 16 GPIO_ACTIVE_HIGH | ||
| 371 | &gpio0 17 GPIO_ACTIVE_HIGH>; | ||
| 372 | alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; | ||
| 373 | gpio-fan,speed-map = < 0 0 | ||
| 374 | 2500 1 | ||
| 375 | 3100 2 | ||
| 376 | 3800 3 | ||
| 377 | 4600 4 | ||
| 378 | 4800 5 | ||
| 379 | 4900 6 | ||
| 380 | 5000 7 >; | ||
| 381 | }; | ||
| 382 | |||
| 383 | gpio-fan-100-15-35-1 { | ||
| 384 | status = "disabled"; | ||
| 385 | compatible = "gpio-fan"; | ||
| 386 | pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 | ||
| 387 | &pmx_fanalarm_35>; | ||
| 388 | pinctrl-names = "default"; | ||
| 389 | gpios = <&gpio0 15 GPIO_ACTIVE_HIGH | ||
| 390 | &gpio0 16 GPIO_ACTIVE_HIGH | ||
| 391 | &gpio0 17 GPIO_ACTIVE_HIGH>; | ||
| 392 | alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; | ||
| 393 | gpio-fan,speed-map = < 0 0 | ||
| 394 | 2500 1 | ||
| 395 | 3100 2 | ||
| 396 | 3800 3 | ||
| 397 | 4600 4 | ||
| 398 | 4800 5 | ||
| 399 | 4900 6 | ||
| 400 | 5000 7 >; | ||
| 401 | }; | ||
| 402 | |||
| 403 | gpio-fan-100-15-35-3 { | ||
| 404 | status = "disabled"; | ||
| 405 | compatible = "gpio-fan"; | ||
| 406 | pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 | ||
| 407 | &pmx_fanalarm_35 &pmx_fanalarm_44 &pmx_fanalarm_45>; | ||
| 408 | pinctrl-names = "default"; | ||
| 409 | gpios = <&gpio0 15 GPIO_ACTIVE_HIGH | ||
| 410 | &gpio0 16 GPIO_ACTIVE_HIGH | ||
| 411 | &gpio0 17 GPIO_ACTIVE_HIGH>; | ||
| 412 | alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH | ||
| 413 | &gpio1 12 GPIO_ACTIVE_HIGH | ||
| 414 | &gpio1 13 GPIO_ACTIVE_HIGH>; | ||
| 415 | gpio-fan,speed-map = < 0 0 | ||
| 416 | 2500 1 | ||
| 417 | 3100 2 | ||
| 418 | 3800 3 | ||
| 419 | 4600 4 | ||
| 420 | 4800 5 | ||
| 421 | 4900 6 | ||
| 422 | 5000 7 >; | ||
| 423 | }; | ||
| 424 | |||
| 425 | gpio-leds-alarm-12 { | ||
| 426 | status = "disabled"; | ||
| 427 | compatible = "gpio-leds"; | ||
| 428 | pinctrl-0 = <&pmx_alarmled_12>; | ||
| 429 | pinctrl-names = "default"; | ||
| 430 | |||
| 431 | hdd1-green { | ||
| 432 | label = "synology:alarm"; | ||
| 433 | gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; | ||
| 434 | }; | ||
| 435 | }; | ||
| 436 | |||
| 437 | gpio-leds-hdd-20 { | ||
| 438 | status = "disabled"; | ||
| 439 | compatible = "gpio-leds"; | ||
| 440 | pinctrl-0 = <&pmx_hddled_20 &pmx_hddled_21 &pmx_hddled_22 | ||
| 441 | &pmx_hddled_23 &pmx_hddled_24 &pmx_hddled_25 | ||
| 442 | &pmx_hddled_26 &pmx_hddled_27>; | ||
| 443 | pinctrl-names = "default"; | ||
| 444 | |||
| 445 | hdd1-green { | ||
| 446 | label = "synology:green:hdd1"; | ||
| 447 | gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; | ||
| 448 | }; | ||
| 449 | |||
| 450 | hdd1-amber { | ||
| 451 | label = "synology:amber:hdd1"; | ||
| 452 | gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; | ||
| 453 | }; | ||
| 454 | |||
| 455 | hdd2-green { | ||
| 456 | label = "synology:green:hdd2"; | ||
| 457 | gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; | ||
| 458 | }; | ||
| 459 | |||
| 460 | hdd2-amber { | ||
| 461 | label = "synology:amber:hdd2"; | ||
| 462 | gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; | ||
| 463 | }; | ||
| 464 | |||
| 465 | hdd3-green { | ||
| 466 | label = "synology:green:hdd3"; | ||
| 467 | gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; | ||
| 468 | }; | ||
| 469 | |||
| 470 | hdd3-amber { | ||
| 471 | label = "synology:amber:hdd3"; | ||
| 472 | gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; | ||
| 473 | }; | ||
| 474 | |||
| 475 | hdd4-green { | ||
| 476 | label = "synology:green:hdd4"; | ||
| 477 | gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; | ||
| 478 | }; | ||
| 479 | |||
| 480 | hdd4-amber { | ||
| 481 | label = "synology:amber:hdd4"; | ||
| 482 | gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; | ||
| 483 | }; | ||
| 484 | }; | ||
| 485 | |||
| 486 | gpio-leds-hdd-21-1 { | ||
| 487 | status = "disabled"; | ||
| 488 | compatible = "gpio-leds"; | ||
| 489 | pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23>; | ||
| 490 | pinctrl-names = "default"; | ||
| 491 | |||
| 492 | hdd1-green { | ||
| 493 | label = "synology:green:hdd1"; | ||
| 494 | gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; | ||
| 495 | }; | ||
| 496 | |||
| 497 | hdd1-amber { | ||
| 498 | label = "synology:amber:hdd1"; | ||
| 499 | gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; | ||
| 500 | }; | ||
| 501 | }; | ||
| 502 | |||
| 503 | gpio-leds-hdd-21-2 { | ||
| 504 | status = "disabled"; | ||
| 505 | compatible = "gpio-leds"; | ||
| 506 | pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23 &pmx_hddled_20 &pmx_hddled_22>; | ||
| 507 | pinctrl-names = "default"; | ||
| 508 | |||
| 509 | hdd1-green { | ||
| 510 | label = "synology:green:hdd1"; | ||
| 511 | gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; | ||
| 512 | }; | ||
| 513 | |||
| 514 | hdd1-amber { | ||
| 515 | label = "synology:amber:hdd1"; | ||
| 516 | gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; | ||
| 517 | }; | ||
| 518 | |||
| 519 | hdd2-green { | ||
| 520 | label = "synology:green:hdd2"; | ||
| 521 | gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; | ||
| 522 | }; | ||
| 523 | |||
| 524 | hdd2-amber { | ||
| 525 | label = "synology:amber:hdd2"; | ||
| 526 | gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; | ||
| 527 | }; | ||
| 528 | }; | ||
| 529 | |||
| 530 | gpio-leds-hdd-36 { | ||
| 531 | status = "disabled"; | ||
| 532 | compatible = "gpio-leds"; | ||
| 533 | pinctrl-0 = <&pmx_hddled_36 &pmx_hddled_37 &pmx_hddled_38 | ||
| 534 | &pmx_hddled_39 &pmx_hddled_40 &pmx_hddled_41 | ||
| 535 | &pmx_hddled_42 &pmx_hddled_43 &pmx_hddled_44 | ||
| 536 | &pmx_hddled_45>; | ||
| 537 | pinctrl-names = "default"; | ||
| 538 | |||
| 539 | hdd1-green { | ||
| 540 | label = "synology:green:hdd1"; | ||
| 541 | gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; | ||
| 542 | }; | ||
| 543 | |||
| 544 | hdd1-amber { | ||
| 545 | label = "synology:amber:hdd1"; | ||
| 546 | gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; | ||
| 547 | }; | ||
| 548 | |||
| 549 | hdd2-green { | ||
| 550 | label = "synology:green:hdd2"; | ||
| 551 | gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; | ||
| 552 | }; | ||
| 553 | |||
| 554 | hdd2-amber { | ||
| 555 | label = "synology:amber:hdd2"; | ||
| 556 | gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; | ||
| 557 | }; | ||
| 558 | |||
| 559 | hdd3-green { | ||
| 560 | label = "synology:green:hdd3"; | ||
| 561 | gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; | ||
| 562 | }; | ||
| 563 | |||
| 564 | hdd3-amber { | ||
| 565 | label = "synology:amber:hdd3"; | ||
| 566 | gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; | ||
| 567 | }; | ||
| 568 | |||
| 569 | hdd4-green { | ||
| 570 | label = "synology:green:hdd4"; | ||
| 571 | gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; | ||
| 572 | }; | ||
| 573 | |||
| 574 | hdd4-amber { | ||
| 575 | label = "synology:amber:hdd4"; | ||
| 576 | gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; | ||
| 577 | }; | ||
| 578 | |||
| 579 | hdd5-green { | ||
| 580 | label = "synology:green:hdd5"; | ||
| 581 | gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; | ||
| 582 | }; | ||
| 583 | |||
| 584 | hdd5-amber { | ||
| 585 | label = "synology:amber:hdd5"; | ||
| 586 | gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; | ||
| 587 | }; | ||
| 588 | }; | ||
| 589 | |||
| 590 | gpio-leds-hdd-38 { | ||
| 591 | status = "disabled"; | ||
| 592 | compatible = "gpio-leds"; | ||
| 593 | pinctrl-0 = <&pmx_hddled_38 &pmx_hddled_39 &pmx_hddled_36 &pmx_hddled_37>; | ||
| 594 | pinctrl-names = "default"; | ||
| 595 | |||
| 596 | hdd1-green { | ||
| 597 | label = "synology:green:hdd1"; | ||
| 598 | gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; | ||
| 599 | }; | ||
| 600 | |||
| 601 | hdd1-amber { | ||
| 602 | label = "synology:amber:hdd1"; | ||
| 603 | gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; | ||
| 604 | }; | ||
| 605 | |||
| 606 | hdd2-green { | ||
| 607 | label = "synology:green:hdd2"; | ||
| 608 | gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; | ||
| 609 | }; | ||
| 610 | |||
| 611 | hdd2-amber { | ||
| 612 | label = "synology:amber:hdd2"; | ||
| 613 | gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; | ||
| 614 | }; | ||
| 615 | }; | ||
| 616 | |||
| 617 | regulators-hdd-29 { | ||
| 618 | status = "disabled"; | ||
| 619 | compatible = "simple-bus"; | ||
| 620 | #address-cells = <1>; | ||
| 621 | #size-cells = <0>; | ||
| 622 | pinctrl-0 = <&pmx_hdd1_pwr_29 &pmx_hdd2_pwr_31>; | ||
| 623 | pinctrl-names = "default"; | ||
| 624 | |||
| 625 | regulator@1 { | ||
| 626 | compatible = "regulator-fixed"; | ||
| 627 | reg = <1>; | ||
| 628 | regulator-name = "hdd1power"; | ||
| 629 | regulator-min-microvolt = <5000000>; | ||
| 630 | regulator-max-microvolt = <5000000>; | ||
| 631 | enable-active-high; | ||
| 632 | regulator-always-on; | ||
| 633 | regulator-boot-on; | ||
| 634 | startup-delay-us = <5000000>; | ||
| 635 | gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; | ||
| 636 | }; | ||
| 637 | |||
| 638 | regulator@2 { | ||
| 639 | compatible = "regulator-fixed"; | ||
| 640 | reg = <2>; | ||
| 641 | regulator-name = "hdd2power"; | ||
| 642 | regulator-min-microvolt = <5000000>; | ||
| 643 | regulator-max-microvolt = <5000000>; | ||
| 644 | enable-active-high; | ||
| 645 | regulator-always-on; | ||
| 646 | regulator-boot-on; | ||
| 647 | startup-delay-us = <5000000>; | ||
| 648 | gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>; | ||
| 649 | }; | ||
| 650 | }; | ||
| 651 | |||
| 652 | regulators-hdd-30-1 { | ||
| 653 | status = "disabled"; | ||
| 654 | compatible = "simple-bus"; | ||
| 655 | #address-cells = <1>; | ||
| 656 | #size-cells = <0>; | ||
| 657 | pinctrl-0 = <&pmx_hdd1_pwr_30>; | ||
| 658 | pinctrl-names = "default"; | ||
| 659 | |||
| 660 | regulator@1 { | ||
| 661 | compatible = "regulator-fixed"; | ||
| 662 | reg = <1>; | ||
| 663 | regulator-name = "hdd1power"; | ||
| 664 | regulator-min-microvolt = <5000000>; | ||
| 665 | regulator-max-microvolt = <5000000>; | ||
| 666 | enable-active-high; | ||
| 667 | regulator-always-on; | ||
| 668 | regulator-boot-on; | ||
| 669 | startup-delay-us = <5000000>; | ||
| 670 | gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; | ||
| 671 | }; | ||
| 672 | }; | ||
| 673 | |||
| 674 | regulators-hdd-30-2 { | ||
| 675 | status = "disabled"; | ||
| 676 | compatible = "simple-bus"; | ||
| 677 | #address-cells = <1>; | ||
| 678 | #size-cells = <0>; | ||
| 679 | pinctrl-0 = <&pmx_hdd1_pwr_30 &pmx_hdd2_pwr_34>; | ||
| 680 | pinctrl-names = "default"; | ||
| 681 | |||
| 682 | regulator@1 { | ||
| 683 | compatible = "regulator-fixed"; | ||
| 684 | reg = <1>; | ||
| 685 | regulator-name = "hdd1power"; | ||
| 686 | regulator-min-microvolt = <5000000>; | ||
| 687 | regulator-max-microvolt = <5000000>; | ||
| 688 | enable-active-high; | ||
| 689 | regulator-always-on; | ||
| 690 | regulator-boot-on; | ||
| 691 | startup-delay-us = <5000000>; | ||
| 692 | gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; | ||
| 693 | }; | ||
| 694 | |||
| 695 | regulator@2 { | ||
| 696 | compatible = "regulator-fixed"; | ||
| 697 | reg = <2>; | ||
| 698 | regulator-name = "hdd2power"; | ||
| 699 | regulator-min-microvolt = <5000000>; | ||
| 700 | regulator-max-microvolt = <5000000>; | ||
| 701 | enable-active-high; | ||
| 702 | regulator-always-on; | ||
| 703 | regulator-boot-on; | ||
| 704 | startup-delay-us = <5000000>; | ||
| 705 | gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; | ||
| 706 | }; | ||
| 707 | }; | ||
| 708 | |||
| 709 | regulators-hdd-30-4 { | ||
| 710 | status = "disabled"; | ||
| 711 | compatible = "simple-bus"; | ||
| 712 | #address-cells = <1>; | ||
| 713 | #size-cells = <0>; | ||
| 714 | pinctrl-0 = <&pmx_hdd1_pwr_30 &pmx_hdd2_pwr_34 | ||
| 715 | &pmx_hdd3_pwr_44 &pmx_hdd4_pwr_45>; | ||
| 716 | pinctrl-names = "default"; | ||
| 717 | |||
| 718 | regulator@1 { | ||
| 719 | compatible = "regulator-fixed"; | ||
| 720 | reg = <1>; | ||
| 721 | regulator-name = "hdd1power"; | ||
| 722 | regulator-min-microvolt = <5000000>; | ||
| 723 | regulator-max-microvolt = <5000000>; | ||
| 724 | enable-active-high; | ||
| 725 | regulator-always-on; | ||
| 726 | regulator-boot-on; | ||
| 727 | startup-delay-us = <5000000>; | ||
| 728 | gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; | ||
| 729 | }; | ||
| 730 | |||
| 731 | regulator@2 { | ||
| 732 | compatible = "regulator-fixed"; | ||
| 733 | reg = <2>; | ||
| 734 | regulator-name = "hdd2power"; | ||
| 735 | regulator-min-microvolt = <5000000>; | ||
| 736 | regulator-max-microvolt = <5000000>; | ||
| 737 | enable-active-high; | ||
| 738 | regulator-always-on; | ||
| 739 | regulator-boot-on; | ||
| 740 | startup-delay-us = <5000000>; | ||
| 741 | gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; | ||
| 742 | }; | ||
| 743 | |||
| 744 | regulator@3 { | ||
| 745 | compatible = "regulator-fixed"; | ||
| 746 | reg = <3>; | ||
| 747 | regulator-name = "hdd3power"; | ||
| 748 | regulator-min-microvolt = <5000000>; | ||
| 749 | regulator-max-microvolt = <5000000>; | ||
| 750 | enable-active-high; | ||
| 751 | regulator-always-on; | ||
| 752 | regulator-boot-on; | ||
| 753 | startup-delay-us = <5000000>; | ||
| 754 | gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; | ||
| 755 | }; | ||
| 756 | |||
| 757 | regulator@4 { | ||
| 758 | compatible = "regulator-fixed"; | ||
| 759 | reg = <4>; | ||
| 760 | regulator-name = "hdd4power"; | ||
| 761 | regulator-min-microvolt = <5000000>; | ||
| 762 | regulator-max-microvolt = <5000000>; | ||
| 763 | enable-active-high; | ||
| 764 | regulator-always-on; | ||
| 765 | regulator-boot-on; | ||
| 766 | startup-delay-us = <5000000>; | ||
| 767 | gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; | ||
| 768 | }; | ||
| 769 | }; | ||
| 770 | |||
| 771 | regulators-hdd-31 { | ||
| 772 | status = "disabled"; | ||
| 773 | compatible = "simple-bus"; | ||
| 774 | #address-cells = <1>; | ||
| 775 | #size-cells = <0>; | ||
| 776 | pinctrl-0 = <&pmx_hdd2_pwr_31>; | ||
| 777 | pinctrl-names = "default"; | ||
| 778 | |||
| 779 | regulator@1 { | ||
| 780 | compatible = "regulator-fixed"; | ||
| 781 | reg = <1>; | ||
| 782 | regulator-name = "hdd2power"; | ||
| 783 | regulator-min-microvolt = <5000000>; | ||
| 784 | regulator-max-microvolt = <5000000>; | ||
| 785 | enable-active-high; | ||
| 786 | regulator-always-on; | ||
| 787 | regulator-boot-on; | ||
| 788 | startup-delay-us = <5000000>; | ||
| 789 | gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>; | ||
| 790 | }; | ||
| 791 | }; | ||
| 792 | |||
| 793 | regulators-hdd-34 { | ||
| 794 | status = "disabled"; | ||
| 795 | compatible = "simple-bus"; | ||
| 796 | #address-cells = <1>; | ||
| 797 | #size-cells = <0>; | ||
| 798 | pinctrl-0 = <&pmx_hdd2_pwr_34 &pmx_hdd3_pwr_44 | ||
| 799 | &pmx_hdd4_pwr_45>; | ||
| 800 | pinctrl-names = "default"; | ||
| 801 | |||
| 802 | regulator@2 { | ||
| 803 | compatible = "regulator-fixed"; | ||
| 804 | reg = <2>; | ||
| 805 | regulator-name = "hdd2power"; | ||
| 806 | regulator-min-microvolt = <5000000>; | ||
| 807 | regulator-max-microvolt = <5000000>; | ||
| 808 | enable-active-high; | ||
| 809 | regulator-always-on; | ||
| 810 | regulator-boot-on; | ||
| 811 | startup-delay-us = <5000000>; | ||
| 812 | gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; | ||
| 813 | }; | ||
| 814 | |||
| 815 | regulator@3 { | ||
| 816 | compatible = "regulator-fixed"; | ||
| 817 | reg = <3>; | ||
| 818 | regulator-name = "hdd3power"; | ||
| 819 | regulator-min-microvolt = <5000000>; | ||
| 820 | regulator-max-microvolt = <5000000>; | ||
| 821 | enable-active-high; | ||
| 822 | regulator-always-on; | ||
| 823 | regulator-boot-on; | ||
| 824 | startup-delay-us = <5000000>; | ||
| 825 | gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; | ||
| 826 | }; | ||
| 827 | |||
| 828 | regulator@4 { | ||
| 829 | compatible = "regulator-fixed"; | ||
| 830 | reg = <4>; | ||
| 831 | regulator-name = "hdd4power"; | ||
| 832 | regulator-min-microvolt = <5000000>; | ||
| 833 | regulator-max-microvolt = <5000000>; | ||
| 834 | enable-active-high; | ||
| 835 | regulator-always-on; | ||
| 836 | regulator-boot-on; | ||
| 837 | startup-delay-us = <5000000>; | ||
| 838 | gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; | ||
| 839 | }; | ||
| 840 | }; | ||
| 841 | }; | ||
| 842 | |||
| 843 | &mdio { | ||
| 844 | status = "okay"; | ||
| 845 | |||
| 846 | ethphy0: ethernet-phy@0 { | ||
| 847 | device_type = "ethernet-phy"; | ||
| 848 | reg = <8>; | ||
| 849 | }; | ||
| 850 | |||
| 851 | ethphy1: ethernet-phy@1 { | ||
| 852 | device_type = "ethernet-phy"; | ||
| 853 | reg = <9>; | ||
| 854 | }; | ||
| 855 | }; | ||
| 856 | |||
| 857 | ð0 { | ||
| 858 | status = "okay"; | ||
| 859 | |||
| 860 | ethernet0-port@0 { | ||
| 861 | phy-handle = <ðphy0>; | ||
| 862 | }; | ||
| 863 | }; | ||
| 864 | |||
| 865 | ð1 { | ||
| 866 | status = "disabled"; | ||
| 867 | |||
| 868 | ethernet1-port@0 { | ||
| 869 | phy-handle = <ðphy1>; | ||
| 870 | }; | ||
| 871 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-t5325.dts b/arch/arm/boot/dts/kirkwood-t5325.dts new file mode 100644 index 000000000000..7d1c7677a18f --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-t5325.dts | |||
| @@ -0,0 +1,208 @@ | |||
| 1 | /* | ||
| 2 | * Device Tree file for HP t5325 Thin Client" | ||
| 3 | * | ||
| 4 | * Copyright (C) 2014 | ||
| 5 | * | ||
| 6 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | ||
| 7 | * Andrew Lunn <andrew@lunn.ch> | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | /dts-v1/; | ||
| 15 | |||
| 16 | #include "kirkwood.dtsi" | ||
| 17 | #include "kirkwood-6281.dtsi" | ||
| 18 | |||
| 19 | / { | ||
| 20 | model = "HP t5325 Thin Client"; | ||
| 21 | compatible = "hp,t5325", "marvell,kirkwood-88f6281", "marvell,kirkwood"; | ||
| 22 | |||
| 23 | memory { | ||
| 24 | device_type = "memory"; | ||
| 25 | reg = <0x00000000 0x20000000>; | ||
| 26 | }; | ||
| 27 | |||
| 28 | chosen { | ||
| 29 | bootargs = "console=ttyS0,115200n8"; | ||
| 30 | }; | ||
| 31 | |||
| 32 | mbus { | ||
| 33 | pcie-controller { | ||
| 34 | status = "okay"; | ||
| 35 | |||
| 36 | pcie@1,0 { | ||
| 37 | status = "okay"; | ||
| 38 | }; | ||
| 39 | }; | ||
| 40 | }; | ||
| 41 | |||
| 42 | ocp@f1000000 { | ||
| 43 | pinctrl: pinctrl@10000 { | ||
| 44 | pinctrl-0 = <&pmx_i2s &pmx_sysrst>; | ||
| 45 | pinctrl-names = "default"; | ||
| 46 | |||
| 47 | pmx_button_power: pmx-button_power { | ||
| 48 | marvell,pins = "mpp45"; | ||
| 49 | marvell,function = "gpio"; | ||
| 50 | }; | ||
| 51 | |||
| 52 | pmx_power_off: pmx-power-off { | ||
| 53 | marvell,pins = "mpp48"; | ||
| 54 | marvell,function = "gpio"; | ||
| 55 | }; | ||
| 56 | |||
| 57 | pmx_led: pmx-led { | ||
| 58 | marvell,pins = "mpp21"; | ||
| 59 | marvell,function = "gpio"; | ||
| 60 | }; | ||
| 61 | |||
| 62 | pmx_usb_sata_power_enable: pmx-usb-sata-power-enable { | ||
| 63 | marvell,pins = "mpp44"; | ||
| 64 | marvell,function = "gpio"; | ||
| 65 | }; | ||
| 66 | |||
| 67 | /* | ||
| 68 | * Redefined from kirkwood-6281.dtsi, because | ||
| 69 | * we don't use SPI CS on MPP0, but on MPP7. | ||
| 70 | */ | ||
| 71 | pmx_spi: pmx-spi { | ||
| 72 | marvell,pins = "mpp1", "mpp2", "mpp3", "mpp7"; | ||
| 73 | marvell,function = "spi"; | ||
| 74 | }; | ||
| 75 | |||
| 76 | pmx_sysrst: pmx-sysrst { | ||
| 77 | marvell,pins = "mpp6"; | ||
| 78 | marvell,function = "sysrst"; | ||
| 79 | }; | ||
| 80 | |||
| 81 | pmx_i2s: pmx-i2s { | ||
| 82 | marvell,pins = "mpp39", "mpp40", "mpp41", "mpp42", | ||
| 83 | "mpp43"; | ||
| 84 | marvell,function = "audio"; | ||
| 85 | }; | ||
| 86 | }; | ||
| 87 | |||
| 88 | spi@10600 { | ||
| 89 | pinctrl-0 = <&pmx_spi>; | ||
| 90 | pinctrl-names = "default"; | ||
| 91 | status = "okay"; | ||
| 92 | |||
| 93 | flash@0 { | ||
| 94 | #address-cells = <1>; | ||
| 95 | #size-cells = <1>; | ||
| 96 | compatible = "st,m25p80"; | ||
| 97 | spi-max-frequency = <86000000>; | ||
| 98 | reg = <0>; | ||
| 99 | mode = <0>; | ||
| 100 | |||
| 101 | partition@0 { | ||
| 102 | reg = <0x0 0x80000>; | ||
| 103 | label = "u-boot"; | ||
| 104 | }; | ||
| 105 | |||
| 106 | partition@1 { | ||
| 107 | reg = <0x80000 0x40000>; | ||
| 108 | label = "SSD firmware"; | ||
| 109 | }; | ||
| 110 | |||
| 111 | partition@2 { | ||
| 112 | reg = <0xc0000 0x10000>; | ||
| 113 | label = "u-boot env"; | ||
| 114 | }; | ||
| 115 | |||
| 116 | partition@3 { | ||
| 117 | reg = <0xd0000 0x10000>; | ||
| 118 | label = "permanent u-boot env"; | ||
| 119 | }; | ||
| 120 | |||
| 121 | partition@4 { | ||
| 122 | reg = <0xd0000 0x10000>; | ||
| 123 | label = "permanent u-boot env"; | ||
| 124 | }; | ||
| 125 | }; | ||
| 126 | }; | ||
| 127 | |||
| 128 | i2c@11000 { | ||
| 129 | status = "okay"; | ||
| 130 | |||
| 131 | alc5621: alc5621@1a { | ||
| 132 | compatible = "realtek,alc5621"; | ||
| 133 | reg = <0x1a>; | ||
| 134 | }; | ||
| 135 | }; | ||
| 136 | |||
| 137 | serial@12000 { | ||
| 138 | status = "okay"; | ||
| 139 | }; | ||
| 140 | |||
| 141 | sata@80000 { | ||
| 142 | status = "okay"; | ||
| 143 | nr-ports = <2>; | ||
| 144 | }; | ||
| 145 | |||
| 146 | audio: audio-controller@a0000 { | ||
| 147 | status = "okay"; | ||
| 148 | }; | ||
| 149 | }; | ||
| 150 | |||
| 151 | regulators { | ||
| 152 | compatible = "simple-bus"; | ||
| 153 | #address-cells = <1>; | ||
| 154 | #size-cells = <0>; | ||
| 155 | pinctrl-0 = <&pmx_usb_sata_power_enable>; | ||
| 156 | pinctrl-names = "default"; | ||
| 157 | |||
| 158 | usb_power: regulator@1 { | ||
| 159 | compatible = "regulator-fixed"; | ||
| 160 | reg = <1>; | ||
| 161 | regulator-name = "USB-SATA Power"; | ||
| 162 | regulator-min-microvolt = <5000000>; | ||
| 163 | regulator-max-microvolt = <5000000>; | ||
| 164 | enable-active-high; | ||
| 165 | regulator-always-on; | ||
| 166 | regulator-boot-on; | ||
| 167 | gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; | ||
| 168 | }; | ||
| 169 | }; | ||
| 170 | |||
| 171 | gpio_keys { | ||
| 172 | compatible = "gpio-keys"; | ||
| 173 | #address-cells = <1>; | ||
| 174 | #size-cells = <0>; | ||
| 175 | pinctrl-0 = <&pmx_button_power>; | ||
| 176 | pinctrl-names = "default"; | ||
| 177 | |||
| 178 | button@1 { | ||
| 179 | label = "Power Button"; | ||
| 180 | linux,code = <KEY_POWER>; | ||
| 181 | gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; | ||
| 182 | }; | ||
| 183 | }; | ||
| 184 | |||
| 185 | gpio_poweroff { | ||
| 186 | compatible = "gpio-poweroff"; | ||
| 187 | pinctrl-0 = <&pmx_power_off>; | ||
| 188 | pinctrl-names = "default"; | ||
| 189 | gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; | ||
| 190 | }; | ||
| 191 | |||
| 192 | }; | ||
| 193 | |||
| 194 | &mdio { | ||
| 195 | status = "okay"; | ||
| 196 | |||
| 197 | ethphy0: ethernet-phy { | ||
| 198 | device_type = "ethernet-phy"; | ||
| 199 | reg = <8>; | ||
| 200 | }; | ||
| 201 | }; | ||
| 202 | |||
| 203 | ð0 { | ||
| 204 | status = "okay"; | ||
| 205 | ethernet0-port@0 { | ||
| 206 | phy-handle = <ðphy0>; | ||
| 207 | }; | ||
| 208 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-ts419-6281.dts b/arch/arm/boot/dts/kirkwood-ts419-6281.dts new file mode 100644 index 000000000000..aa22aa862857 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-ts419-6281.dts | |||
| @@ -0,0 +1,20 @@ | |||
| 1 | /* | ||
| 2 | * Device Tree file for QNAP TS41X with 6281 SoC | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013, Andrew Lunn <andrew@lunn.ch> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public License | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the License, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | |||
| 14 | #include "kirkwood.dtsi" | ||
| 15 | #include "kirkwood-6281.dtsi" | ||
| 16 | #include "kirkwood-ts219.dtsi" | ||
| 17 | #include "kirkwood-ts419.dtsi" | ||
| 18 | |||
| 19 | ðphy0 { reg = <8>; }; | ||
| 20 | ðphy1 { reg = <0>; }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-ts419-6282.dts b/arch/arm/boot/dts/kirkwood-ts419-6282.dts new file mode 100644 index 000000000000..d7512d4cdced --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-ts419-6282.dts | |||
| @@ -0,0 +1,32 @@ | |||
| 1 | /* | ||
| 2 | * Device Tree file for QNAP TS41X with 6282 SoC | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013, Andrew Lunn <andrew@lunn.ch> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public License | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the License, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | |||
| 14 | #include "kirkwood.dtsi" | ||
| 15 | #include "kirkwood-6282.dtsi" | ||
| 16 | #include "kirkwood-ts219.dtsi" | ||
| 17 | #include "kirkwood-ts419.dtsi" | ||
| 18 | |||
| 19 | / { | ||
| 20 | mbus { | ||
| 21 | pcie-controller { | ||
| 22 | status = "okay"; | ||
| 23 | |||
| 24 | pcie@2,0 { | ||
| 25 | status = "okay"; | ||
| 26 | }; | ||
| 27 | }; | ||
| 28 | }; | ||
| 29 | }; | ||
| 30 | |||
| 31 | ðphy0 { reg = <0>; }; | ||
| 32 | ðphy1 { reg = <1>; }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-ts419.dtsi b/arch/arm/boot/dts/kirkwood-ts419.dtsi new file mode 100644 index 000000000000..1a9c624c7a92 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-ts419.dtsi | |||
| @@ -0,0 +1,75 @@ | |||
| 1 | /* | ||
| 2 | * Device Tree include file for QNAP TS41X | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013, Andrew Lunn <andrew@lunn.ch> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public License | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the License, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | / { | ||
| 13 | model = "QNAP TS419 family"; | ||
| 14 | compatible = "qnap,ts419", "marvell,kirkwood"; | ||
| 15 | |||
| 16 | ocp@f1000000 { | ||
| 17 | pinctrl: pinctrl@10000 { | ||
| 18 | pinctrl-names = "default"; | ||
| 19 | |||
| 20 | pmx_USB_copy_button: pmx-USB-copy-button { | ||
| 21 | marvell,pins = "mpp43"; | ||
| 22 | marvell,function = "gpio"; | ||
| 23 | }; | ||
| 24 | pmx_reset_button: pmx-reset-button { | ||
| 25 | marvell,pins = "mpp37"; | ||
| 26 | marvell,function = "gpio"; | ||
| 27 | }; | ||
| 28 | /* | ||
| 29 | * JP1 indicates if an LCD module is installed | ||
| 30 | * on the serial port (0), or if the port is used | ||
| 31 | * as a console (1). | ||
| 32 | */ | ||
| 33 | pmx_jumper_jp1: pmx-jumper_jp1 { | ||
| 34 | marvell,pins = "mpp45"; | ||
| 35 | marvell,function = "gpio"; | ||
| 36 | }; | ||
| 37 | |||
| 38 | }; | ||
| 39 | }; | ||
| 40 | |||
| 41 | gpio_keys { | ||
| 42 | compatible = "gpio-keys"; | ||
| 43 | #address-cells = <1>; | ||
| 44 | #size-cells = <0>; | ||
| 45 | pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; | ||
| 46 | pinctrl-names = "default"; | ||
| 47 | |||
| 48 | button@1 { | ||
| 49 | label = "USB Copy"; | ||
| 50 | linux,code = <KEY_COPY>; | ||
| 51 | gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; | ||
| 52 | }; | ||
| 53 | button@2 { | ||
| 54 | label = "Reset"; | ||
| 55 | linux,code = <KEY_RESTART>; | ||
| 56 | gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; | ||
| 57 | }; | ||
| 58 | }; | ||
| 59 | }; | ||
| 60 | |||
| 61 | &mdio { | ||
| 62 | status = "okay"; | ||
| 63 | |||
| 64 | ethphy1: ethernet-phy@1 { | ||
| 65 | device_type = "ethernet-phy"; | ||
| 66 | /* overwrite reg property in board file */ | ||
| 67 | }; | ||
| 68 | }; | ||
| 69 | |||
| 70 | ð1 { | ||
| 71 | status = "okay"; | ||
| 72 | ethernet1-port@0 { | ||
| 73 | phy-handle = <ðphy1>; | ||
| 74 | }; | ||
| 75 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 6abf44d257df..90384587c278 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | aliases { | 24 | aliases { |
| 25 | gpio0 = &gpio0; | 25 | gpio0 = &gpio0; |
| 26 | gpio1 = &gpio1; | 26 | gpio1 = &gpio1; |
| 27 | i2c0 = &i2c0; | ||
| 27 | }; | 28 | }; |
| 28 | 29 | ||
| 29 | mbus { | 30 | mbus { |
| @@ -111,7 +112,7 @@ | |||
| 111 | clocks = <&gate_clk 7>; | 112 | clocks = <&gate_clk 7>; |
| 112 | }; | 113 | }; |
| 113 | 114 | ||
| 114 | i2c@11000 { | 115 | i2c0: i2c@11000 { |
| 115 | compatible = "marvell,mv64xxx-i2c"; | 116 | compatible = "marvell,mv64xxx-i2c"; |
| 116 | reg = <0x11000 0x20>; | 117 | reg = <0x11000 0x20>; |
| 117 | #address-cells = <1>; | 118 | #address-cells = <1>; |
| @@ -145,6 +146,11 @@ | |||
| 145 | reg = <0x20000 0x80>, <0x1500 0x20>; | 146 | reg = <0x20000 0x80>, <0x1500 0x20>; |
| 146 | }; | 147 | }; |
| 147 | 148 | ||
| 149 | system-controller@20000 { | ||
| 150 | compatible = "marvell,orion-system-controller"; | ||
| 151 | reg = <0x20000 0x120>; | ||
| 152 | }; | ||
| 153 | |||
| 148 | bridge_intc: bridge-interrupt-ctrl@20110 { | 154 | bridge_intc: bridge-interrupt-ctrl@20110 { |
| 149 | compatible = "marvell,orion-bridge-intc"; | 155 | compatible = "marvell,orion-bridge-intc"; |
| 150 | interrupt-controller; | 156 | interrupt-controller; |
| @@ -161,6 +167,11 @@ | |||
| 161 | #clock-cells = <1>; | 167 | #clock-cells = <1>; |
| 162 | }; | 168 | }; |
| 163 | 169 | ||
| 170 | l2: l2-cache@20128 { | ||
| 171 | compatible = "marvell,kirkwood-cache"; | ||
| 172 | reg = <0x20128 0x4>; | ||
| 173 | }; | ||
| 174 | |||
| 164 | intc: main-interrupt-ctrl@20200 { | 175 | intc: main-interrupt-ctrl@20200 { |
| 165 | compatible = "marvell,orion-intc"; | 176 | compatible = "marvell,orion-intc"; |
| 166 | interrupt-controller; | 177 | interrupt-controller; |
| @@ -178,7 +189,7 @@ | |||
| 178 | 189 | ||
| 179 | wdt: watchdog-timer@20300 { | 190 | wdt: watchdog-timer@20300 { |
| 180 | compatible = "marvell,orion-wdt"; | 191 | compatible = "marvell,orion-wdt"; |
| 181 | reg = <0x20300 0x28>; | 192 | reg = <0x20300 0x28>, <0x20108 0x4>; |
| 182 | interrupt-parent = <&bridge_intc>; | 193 | interrupt-parent = <&bridge_intc>; |
| 183 | interrupts = <3>; | 194 | interrupts = <3>; |
| 184 | clocks = <&gate_clk 7>; | 195 | clocks = <&gate_clk 7>; |
| @@ -300,5 +311,14 @@ | |||
| 300 | #phy-cells = <0>; | 311 | #phy-cells = <0>; |
| 301 | status = "ok"; | 312 | status = "ok"; |
| 302 | }; | 313 | }; |
| 314 | |||
| 315 | audio0: audio-controller@a0000 { | ||
| 316 | compatible = "marvell,kirkwood-audio"; | ||
| 317 | reg = <0xa0000 0x2210>; | ||
| 318 | interrupts = <24>; | ||
| 319 | clocks = <&gate_clk 9>; | ||
| 320 | clock-names = "internal"; | ||
| 321 | status = "disabled"; | ||
| 322 | }; | ||
| 303 | }; | 323 | }; |
| 304 | }; | 324 | }; |
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi index 60c605de22dd..85b1fb014c43 100644 --- a/arch/arm/boot/dts/omap2420.dtsi +++ b/arch/arm/boot/dts/omap2420.dtsi | |||
| @@ -99,6 +99,7 @@ | |||
| 99 | dmas = <&sdma 31>, | 99 | dmas = <&sdma 31>, |
| 100 | <&sdma 32>; | 100 | <&sdma 32>; |
| 101 | dma-names = "tx", "rx"; | 101 | dma-names = "tx", "rx"; |
| 102 | status = "disabled"; | ||
| 102 | }; | 103 | }; |
| 103 | 104 | ||
| 104 | mcbsp2: mcbsp@48076000 { | 105 | mcbsp2: mcbsp@48076000 { |
| @@ -112,6 +113,7 @@ | |||
| 112 | dmas = <&sdma 33>, | 113 | dmas = <&sdma 33>, |
| 113 | <&sdma 34>; | 114 | <&sdma 34>; |
| 114 | dma-names = "tx", "rx"; | 115 | dma-names = "tx", "rx"; |
| 116 | status = "disabled"; | ||
| 115 | }; | 117 | }; |
| 116 | 118 | ||
| 117 | msdi1: mmc@4809c000 { | 119 | msdi1: mmc@4809c000 { |
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi index d624345666f5..9d2f028fd687 100644 --- a/arch/arm/boot/dts/omap2430.dtsi +++ b/arch/arm/boot/dts/omap2430.dtsi | |||
| @@ -113,6 +113,7 @@ | |||
| 113 | dmas = <&sdma 31>, | 113 | dmas = <&sdma 31>, |
| 114 | <&sdma 32>; | 114 | <&sdma 32>; |
| 115 | dma-names = "tx", "rx"; | 115 | dma-names = "tx", "rx"; |
| 116 | status = "disabled"; | ||
| 116 | }; | 117 | }; |
| 117 | 118 | ||
| 118 | mcbsp2: mcbsp@48076000 { | 119 | mcbsp2: mcbsp@48076000 { |
| @@ -128,6 +129,7 @@ | |||
| 128 | dmas = <&sdma 33>, | 129 | dmas = <&sdma 33>, |
| 129 | <&sdma 34>; | 130 | <&sdma 34>; |
| 130 | dma-names = "tx", "rx"; | 131 | dma-names = "tx", "rx"; |
| 132 | status = "disabled"; | ||
| 131 | }; | 133 | }; |
| 132 | 134 | ||
| 133 | mcbsp3: mcbsp@4808c000 { | 135 | mcbsp3: mcbsp@4808c000 { |
| @@ -143,6 +145,7 @@ | |||
| 143 | dmas = <&sdma 17>, | 145 | dmas = <&sdma 17>, |
| 144 | <&sdma 18>; | 146 | <&sdma 18>; |
| 145 | dma-names = "tx", "rx"; | 147 | dma-names = "tx", "rx"; |
| 148 | status = "disabled"; | ||
| 146 | }; | 149 | }; |
| 147 | 150 | ||
| 148 | mcbsp4: mcbsp@4808e000 { | 151 | mcbsp4: mcbsp@4808e000 { |
| @@ -158,6 +161,7 @@ | |||
| 158 | dmas = <&sdma 19>, | 161 | dmas = <&sdma 19>, |
| 159 | <&sdma 20>; | 162 | <&sdma 20>; |
| 160 | dma-names = "tx", "rx"; | 163 | dma-names = "tx", "rx"; |
| 164 | status = "disabled"; | ||
| 161 | }; | 165 | }; |
| 162 | 166 | ||
| 163 | mcbsp5: mcbsp@48096000 { | 167 | mcbsp5: mcbsp@48096000 { |
| @@ -173,6 +177,7 @@ | |||
| 173 | dmas = <&sdma 21>, | 177 | dmas = <&sdma 21>, |
| 174 | <&sdma 22>; | 178 | <&sdma 22>; |
| 175 | dma-names = "tx", "rx"; | 179 | dma-names = "tx", "rx"; |
| 180 | status = "disabled"; | ||
| 176 | }; | 181 | }; |
| 177 | 182 | ||
| 178 | mmc1: mmc@4809c000 { | 183 | mmc1: mmc@4809c000 { |
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts index 447e714d435b..cba357023878 100644 --- a/arch/arm/boot/dts/omap3-beagle-xm.dts +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts | |||
| @@ -234,3 +234,7 @@ | |||
| 234 | regulator-max-microvolt = <1800000>; | 234 | regulator-max-microvolt = <1800000>; |
| 235 | regulator-always-on; | 235 | regulator-always-on; |
| 236 | }; | 236 | }; |
| 237 | |||
| 238 | &mcbsp2 { | ||
| 239 | status = "okay"; | ||
| 240 | }; | ||
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts index 5053766d369b..d01e9a76c5da 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts | |||
| @@ -211,3 +211,7 @@ | |||
| 211 | regulator-max-microvolt = <1800000>; | 211 | regulator-max-microvolt = <1800000>; |
| 212 | regulator-always-on; | 212 | regulator-always-on; |
| 213 | }; | 213 | }; |
| 214 | |||
| 215 | &mcbsp2 { | ||
| 216 | status = "okay"; | ||
| 217 | }; | ||
diff --git a/arch/arm/boot/dts/omap3-cm-t3517.dts b/arch/arm/boot/dts/omap3-cm-t3517.dts new file mode 100644 index 000000000000..d00502f4fd9b --- /dev/null +++ b/arch/arm/boot/dts/omap3-cm-t3517.dts | |||
| @@ -0,0 +1,136 @@ | |||
| 1 | /* | ||
| 2 | * Support for CompuLab CM-T3517 | ||
| 3 | */ | ||
| 4 | /dts-v1/; | ||
| 5 | |||
| 6 | #include "am3517.dtsi" | ||
| 7 | #include "omap3-cm-t3x.dtsi" | ||
| 8 | |||
| 9 | / { | ||
| 10 | model = "CompuLab CM-T3517"; | ||
| 11 | compatible = "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3"; | ||
| 12 | |||
| 13 | vmmc: regulator-vmmc { | ||
| 14 | compatible = "regulator-fixed"; | ||
| 15 | regulator-name = "vmmc"; | ||
| 16 | regulator-min-microvolt = <3300000>; | ||
| 17 | regulator-max-microvolt = <3300000>; | ||
| 18 | }; | ||
| 19 | |||
| 20 | wl12xx_vmmc2: wl12xx_vmmc2 { | ||
| 21 | compatible = "regulator-fixed"; | ||
| 22 | regulator-name = "vw1271"; | ||
| 23 | pinctrl-names = "default"; | ||
| 24 | pinctrl-0 = < | ||
| 25 | &wl12xx_wkup_pins | ||
| 26 | &wl12xx_core_pins | ||
| 27 | >; | ||
| 28 | regulator-min-microvolt = <1800000>; | ||
| 29 | regulator-max-microvolt = <1800000>; | ||
| 30 | gpio = <&gpio1 6 GPIO_ACTIVE_HIGH >; /* gpio6 */ | ||
| 31 | startup-delay-us = <20000>; | ||
| 32 | enable-active-high; | ||
| 33 | }; | ||
| 34 | |||
| 35 | wl12xx_vaux2: wl12xx_vaux2 { | ||
| 36 | compatible = "regulator-fixed"; | ||
| 37 | regulator-name = "vwl1271_vaux2"; | ||
| 38 | regulator-min-microvolt = <1800000>; | ||
| 39 | regulator-max-microvolt = <1800000>; | ||
| 40 | }; | ||
| 41 | }; | ||
| 42 | |||
| 43 | &omap3_pmx_wkup { | ||
| 44 | |||
| 45 | wl12xx_wkup_pins: pinmux_wl12xx_wkup_pins { | ||
| 46 | pinctrl-single,pins = < | ||
| 47 | OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */ | ||
| 48 | OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE4) /* sys_boot4.gpio_6 */ | ||
| 49 | >; | ||
| 50 | }; | ||
| 51 | }; | ||
| 52 | |||
| 53 | &omap3_pmx_core { | ||
| 54 | |||
| 55 | phy1_reset_pins: pinmux_hsusb1_phy_reset_pins { | ||
| 56 | pinctrl-single,pins = < | ||
| 57 | OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE4) /* uart2_tx.gpio_146 */ | ||
| 58 | >; | ||
| 59 | }; | ||
| 60 | |||
| 61 | phy2_reset_pins: pinmux_hsusb2_phy_reset_pins { | ||
| 62 | pinctrl-single,pins = < | ||
| 63 | OMAP3_CORE1_IOPAD(0x217a, PIN_OUTPUT | MUX_MODE4) /* uart2_rx.gpio_147 */ | ||
| 64 | >; | ||
| 65 | }; | ||
| 66 | |||
| 67 | otg_drv_vbus: pinmux_otg_drv_vbus { | ||
| 68 | pinctrl-single,pins = < | ||
| 69 | OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50Mhz_clk.usb0_drvvbus */ | ||
| 70 | >; | ||
| 71 | }; | ||
| 72 | |||
| 73 | mmc2_pins: pinmux_mmc2_pins { | ||
| 74 | pinctrl-single,pins = < | ||
| 75 | OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ | ||
| 76 | OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ | ||
| 77 | OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ | ||
| 78 | OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ | ||
| 79 | OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ | ||
| 80 | OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ | ||
| 81 | >; | ||
| 82 | }; | ||
| 83 | |||
| 84 | wl12xx_core_pins: pinmux_wl12xx_core_pins { | ||
| 85 | pinctrl-single,pins = < | ||
| 86 | OMAP3_CORE1_IOPAD(0x20b8, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs5.gpio_56 */ | ||
| 87 | OMAP3_CORE1_IOPAD(0x2176, PIN_INPUT_PULLUP | MUX_MODE4) /* uart2_rts.gpio_145 */ | ||
| 88 | >; | ||
| 89 | }; | ||
| 90 | |||
| 91 | usb_hub_pins: pinmux_usb_hub_pins { | ||
| 92 | pinctrl-single,pins = < | ||
| 93 | OMAP3_CORE1_IOPAD(0x2184, PIN_OUTPUT | MUX_MODE4) /* mcbsp4_clkx.gpio_152 - USB HUB RST */ | ||
| 94 | >; | ||
| 95 | }; | ||
| 96 | }; | ||
| 97 | |||
| 98 | &hsusb1_phy { | ||
| 99 | pinctrl-names = "default"; | ||
| 100 | pinctrl-0 = <&phy1_reset_pins>; | ||
| 101 | reset-gpios = <&gpio5 18 GPIO_ACTIVE_LOW>; | ||
| 102 | }; | ||
| 103 | |||
| 104 | &hsusb2_phy { | ||
| 105 | pinctrl-names = "default"; | ||
| 106 | pinctrl-0 = <&phy2_reset_pins>; | ||
| 107 | reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; | ||
| 108 | }; | ||
| 109 | |||
| 110 | &davinci_emac { | ||
| 111 | status = "okay"; | ||
| 112 | }; | ||
| 113 | |||
| 114 | &davinci_mdio { | ||
| 115 | status = "okay"; | ||
| 116 | }; | ||
| 117 | |||
| 118 | &am35x_otg_hs { | ||
| 119 | status = "okay"; | ||
| 120 | pinctrl-names = "default"; | ||
| 121 | pinctrl-0 = <&otg_drv_vbus>; | ||
| 122 | }; | ||
| 123 | |||
| 124 | &mmc1 { | ||
| 125 | vmmc-supply = <&vmmc>; | ||
| 126 | }; | ||
| 127 | |||
| 128 | &mmc2 { | ||
| 129 | pinctrl-names = "default"; | ||
| 130 | pinctrl-0 = <&mmc2_pins>; | ||
| 131 | vmmc-supply = <&wl12xx_vmmc2>; | ||
| 132 | vmmc_aux-supply = <&wl12xx_vaux2>; | ||
| 133 | non-removable; | ||
| 134 | bus-width = <4>; | ||
| 135 | cap-power-off-card; | ||
| 136 | }; | ||
diff --git a/arch/arm/boot/dts/omap3-cm-t3530.dts b/arch/arm/boot/dts/omap3-cm-t3530.dts new file mode 100644 index 000000000000..d1458496520e --- /dev/null +++ b/arch/arm/boot/dts/omap3-cm-t3530.dts | |||
| @@ -0,0 +1,48 @@ | |||
| 1 | /* | ||
| 2 | * Support for CompuLab CM-T3530 | ||
| 3 | */ | ||
| 4 | /dts-v1/; | ||
| 5 | |||
| 6 | #include "omap34xx.dtsi" | ||
| 7 | #include "omap3-cm-t3x30.dtsi" | ||
| 8 | |||
| 9 | / { | ||
| 10 | model = "CompuLab CM-T3530"; | ||
| 11 | compatible = "compulab,omap3-cm-t3530", "ti,omap34xx", "ti,omap3"; | ||
| 12 | |||
| 13 | /* Regulator to trigger the reset signal of the Wifi module */ | ||
| 14 | mmc2_sdio_reset: regulator-mmc2-sdio-reset { | ||
| 15 | compatible = "regulator-fixed"; | ||
| 16 | regulator-name = "regulator-mmc2-sdio-reset"; | ||
| 17 | regulator-min-microvolt = <3300000>; | ||
| 18 | regulator-max-microvolt = <3300000>; | ||
| 19 | gpio = <&twl_gpio 2 GPIO_ACTIVE_HIGH>; | ||
| 20 | enable-active-high; | ||
| 21 | }; | ||
| 22 | }; | ||
| 23 | |||
| 24 | &omap3_pmx_core { | ||
| 25 | mmc2_pins: pinmux_mmc2_pins { | ||
| 26 | pinctrl-single,pins = < | ||
| 27 | OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ | ||
| 28 | OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ | ||
| 29 | OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ | ||
| 30 | OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ | ||
| 31 | OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ | ||
| 32 | OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ | ||
| 33 | OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */ | ||
| 34 | OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */ | ||
| 35 | OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */ | ||
| 36 | OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ | ||
| 37 | >; | ||
| 38 | }; | ||
| 39 | }; | ||
| 40 | |||
| 41 | &mmc2 { | ||
| 42 | pinctrl-names = "default"; | ||
| 43 | pinctrl-0 = <&mmc2_pins>; | ||
| 44 | vmmc-supply = <&mmc2_sdio_reset>; | ||
| 45 | non-removable; | ||
| 46 | bus-width = <4>; | ||
| 47 | cap-power-off-card; | ||
| 48 | }; | ||
diff --git a/arch/arm/boot/dts/omap3-cm-t3730.dts b/arch/arm/boot/dts/omap3-cm-t3730.dts index 486f4d6c4219..b3f9a50b3bc8 100644 --- a/arch/arm/boot/dts/omap3-cm-t3730.dts +++ b/arch/arm/boot/dts/omap3-cm-t3730.dts | |||
| @@ -32,57 +32,26 @@ | |||
| 32 | }; | 32 | }; |
| 33 | 33 | ||
| 34 | &omap3_pmx_core { | 34 | &omap3_pmx_core { |
| 35 | mmc1_pins: pinmux_mmc1_pins { | ||
| 36 | pinctrl-single,pins = < | ||
| 37 | 0x114 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ | ||
| 38 | 0x116 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ | ||
| 39 | 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ | ||
| 40 | 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ | ||
| 41 | 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ | ||
| 42 | 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ | ||
| 43 | >; | ||
| 44 | }; | ||
| 45 | 35 | ||
| 46 | mmc2_pins: pinmux_mmc2_pins { | 36 | mmc2_pins: pinmux_mmc2_pins { |
| 47 | pinctrl-single,pins = < | 37 | pinctrl-single,pins = < |
| 48 | 0x128 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ | 38 | OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ |
| 49 | 0x12a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ | 39 | OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ |
| 50 | 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ | 40 | OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ |
| 51 | 0x12e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ | 41 | OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ |
| 52 | 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ | 42 | OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ |
| 53 | 0x132 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ | 43 | OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ |
| 54 | >; | ||
| 55 | }; | ||
| 56 | |||
| 57 | smsc1_pins: pinmux_smsc1_pins { | ||
| 58 | pinctrl-single,pins = < | ||
| 59 | 0x88 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs5.gpmc_ncs5 */ | ||
| 60 | 0x16a (PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_163 */ | ||
| 61 | >; | ||
| 62 | }; | ||
| 63 | |||
| 64 | uart3_pins: pinmux_uart3_pins { | ||
| 65 | pinctrl-single,pins = < | ||
| 66 | 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ | ||
| 67 | 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ | ||
| 68 | >; | 44 | >; |
| 69 | }; | 45 | }; |
| 70 | 46 | ||
| 71 | wl12xx_gpio: pinmux_wl12xx_gpio { | 47 | wl12xx_gpio: pinmux_wl12xx_gpio { |
| 72 | pinctrl-single,pins = < | 48 | pinctrl-single,pins = < |
| 73 | 0xb2 (PIN_OUTPUT | MUX_MODE4) /* dss_data3.gpio_73 */ | 49 | OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* dss_data3.gpio_73 */ |
| 74 | 0x134 (PIN_INPUT | MUX_MODE4) /* sdmmc2_dat4.gpio_136 */ | 50 | OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE4) /* sdmmc2_dat4.gpio_136 */ |
| 75 | >; | 51 | >; |
| 76 | }; | 52 | }; |
| 77 | }; | 53 | }; |
| 78 | 54 | ||
| 79 | &mmc1 { | ||
| 80 | vmmc-supply = <&vmmc1>; | ||
| 81 | bus-width = <4>; | ||
| 82 | pinctrl-names = "default"; | ||
| 83 | pinctrl-0 = <&mmc1_pins>; | ||
| 84 | }; | ||
| 85 | |||
| 86 | &mmc2 { | 55 | &mmc2 { |
| 87 | pinctrl-names = "default"; | 56 | pinctrl-names = "default"; |
| 88 | pinctrl-0 = <&mmc2_pins>; | 57 | pinctrl-0 = <&mmc2_pins>; |
| @@ -92,13 +61,3 @@ | |||
| 92 | bus-width = <4>; | 61 | bus-width = <4>; |
| 93 | cap-power-off-card; | 62 | cap-power-off-card; |
| 94 | }; | 63 | }; |
| 95 | |||
| 96 | &smsc1 { | ||
| 97 | pinctrl-names = "default"; | ||
| 98 | pinctrl-0 = <&smsc1_pins>; | ||
| 99 | }; | ||
| 100 | |||
| 101 | &uart3 { | ||
| 102 | pinctrl-names = "default"; | ||
| 103 | pinctrl-0 = <&uart3_pins>; | ||
| 104 | }; | ||
diff --git a/arch/arm/boot/dts/omap3-cm-t3x.dtsi b/arch/arm/boot/dts/omap3-cm-t3x.dtsi new file mode 100644 index 000000000000..c671a2299ea8 --- /dev/null +++ b/arch/arm/boot/dts/omap3-cm-t3x.dtsi | |||
| @@ -0,0 +1,110 @@ | |||
| 1 | /* | ||
| 2 | * Common support for CompuLab CM-T3x CoMs | ||
| 3 | */ | ||
| 4 | |||
| 5 | / { | ||
| 6 | |||
| 7 | memory { | ||
| 8 | device_type = "memory"; | ||
| 9 | reg = <0x80000000 0x10000000>; /* 256 MB */ | ||
| 10 | }; | ||
| 11 | |||
| 12 | leds { | ||
| 13 | compatible = "gpio-leds"; | ||
| 14 | pinctrl-names = "default"; | ||
| 15 | pinctrl-0 = <&green_led_pins>; | ||
| 16 | ledb { | ||
| 17 | label = "cm-t3x:green"; | ||
| 18 | gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>; /* gpio186 */ | ||
| 19 | linux,default-trigger = "heartbeat"; | ||
| 20 | }; | ||
| 21 | }; | ||
| 22 | |||
| 23 | /* HS USB Port 1 Power */ | ||
| 24 | hsusb1_power: hsusb1_power_reg { | ||
| 25 | compatible = "regulator-fixed"; | ||
| 26 | regulator-name = "hsusb1_vbus"; | ||
| 27 | regulator-min-microvolt = <3300000>; | ||
| 28 | regulator-max-microvolt = <3300000>; | ||
| 29 | startup-delay-us = <70000>; | ||
| 30 | }; | ||
| 31 | |||
| 32 | /* HS USB Port 2 Power */ | ||
| 33 | hsusb2_power: hsusb2_power_reg { | ||
| 34 | compatible = "regulator-fixed"; | ||
| 35 | regulator-name = "hsusb2_vbus"; | ||
| 36 | regulator-min-microvolt = <3300000>; | ||
| 37 | regulator-max-microvolt = <3300000>; | ||
| 38 | startup-delay-us = <70000>; | ||
| 39 | }; | ||
| 40 | |||
| 41 | /* HS USB Host PHY on PORT 1 */ | ||
| 42 | hsusb1_phy: hsusb1_phy { | ||
| 43 | compatible = "usb-nop-xceiv"; | ||
| 44 | vcc-supply = <&hsusb1_power>; | ||
| 45 | }; | ||
| 46 | |||
| 47 | /* HS USB Host PHY on PORT 2 */ | ||
| 48 | hsusb2_phy: hsusb2_phy { | ||
| 49 | compatible = "usb-nop-xceiv"; | ||
| 50 | vcc-supply = <&hsusb2_power>; | ||
| 51 | }; | ||
| 52 | }; | ||
| 53 | |||
| 54 | &omap3_pmx_core { | ||
| 55 | |||
| 56 | uart3_pins: pinmux_uart3_pins { | ||
| 57 | pinctrl-single,pins = < | ||
| 58 | OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ | ||
| 59 | OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ | ||
| 60 | >; | ||
| 61 | }; | ||
| 62 | |||
| 63 | mmc1_pins: pinmux_mmc1_pins { | ||
| 64 | pinctrl-single,pins = < | ||
| 65 | OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ | ||
| 66 | OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ | ||
| 67 | OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ | ||
| 68 | OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ | ||
| 69 | OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ | ||
| 70 | OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ | ||
| 71 | >; | ||
| 72 | }; | ||
| 73 | |||
| 74 | green_led_pins: pinmux_green_led_pins { | ||
| 75 | pinctrl-single,pins = < | ||
| 76 | OMAP3_CORE1_IOPAD(0x21e2, PIN_OUTPUT | MUX_MODE4) /* sys_clkout2.gpio_186 */ | ||
| 77 | >; | ||
| 78 | }; | ||
| 79 | }; | ||
| 80 | |||
| 81 | &uart3 { | ||
| 82 | pinctrl-names = "default"; | ||
| 83 | pinctrl-0 = <&uart3_pins>; | ||
| 84 | }; | ||
| 85 | |||
| 86 | &mmc1 { | ||
| 87 | pinctrl-names = "default"; | ||
| 88 | pinctrl-0 = <&mmc1_pins>; | ||
| 89 | bus-width = <4>; | ||
| 90 | }; | ||
| 91 | |||
| 92 | &mmc3 { | ||
| 93 | status = "disabled"; | ||
| 94 | }; | ||
| 95 | |||
| 96 | &i2c1 { | ||
| 97 | clock-frequency = <400000>; | ||
| 98 | }; | ||
| 99 | |||
| 100 | &i2c3 { | ||
| 101 | clock-frequency = <400000>; | ||
| 102 | }; | ||
| 103 | &usbhshost { | ||
| 104 | port1-mode = "ehci-phy"; | ||
| 105 | port2-mode = "ehci-phy"; | ||
| 106 | }; | ||
| 107 | |||
| 108 | &usbhsehci { | ||
| 109 | phys = <&hsusb1_phy &hsusb2_phy>; | ||
| 110 | }; | ||
diff --git a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi index 3a9f004d8924..d00055809e31 100644 --- a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi +++ b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi | |||
| @@ -1,28 +1,16 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Common support for CompuLab CM-T3530 and CM-T3730 | 2 | * Common support for CompuLab CM-T3x30 CoMs |
| 3 | */ | 3 | */ |
| 4 | 4 | ||
| 5 | / { | 5 | #include "omap3-cm-t3x.dtsi" |
| 6 | memory { | ||
| 7 | device_type = "memory"; | ||
| 8 | reg = <0x80000000 0x10000000>; /* 256 MB */ | ||
| 9 | }; | ||
| 10 | 6 | ||
| 7 | / { | ||
| 11 | cpus { | 8 | cpus { |
| 12 | cpu@0 { | 9 | cpu@0 { |
| 13 | cpu0-supply = <&vcc>; | 10 | cpu0-supply = <&vcc>; |
| 14 | }; | 11 | }; |
| 15 | }; | 12 | }; |
| 16 | 13 | ||
| 17 | leds { | ||
| 18 | compatible = "gpio-leds"; | ||
| 19 | ledb { | ||
| 20 | label = "cm-t35:green"; | ||
| 21 | gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>; /* gpio186 */ | ||
| 22 | linux,default-trigger = "heartbeat"; | ||
| 23 | }; | ||
| 24 | }; | ||
| 25 | |||
| 26 | vddvario: regulator-vddvario { | 14 | vddvario: regulator-vddvario { |
| 27 | compatible = "regulator-fixed"; | 15 | compatible = "regulator-fixed"; |
| 28 | regulator-name = "vddvario"; | 16 | regulator-name = "vddvario"; |
| @@ -36,11 +24,40 @@ | |||
| 36 | }; | 24 | }; |
| 37 | }; | 25 | }; |
| 38 | 26 | ||
| 27 | &omap3_pmx_core { | ||
| 28 | |||
| 29 | smsc1_pins: pinmux_smsc1_pins { | ||
| 30 | pinctrl-single,pins = < | ||
| 31 | OMAP3_CORE1_IOPAD(0x20b8, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs5.gpmc_ncs5 */ | ||
| 32 | OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_163 */ | ||
| 33 | >; | ||
| 34 | }; | ||
| 35 | |||
| 36 | hsusb0_pins: pinmux_hsusb0_pins { | ||
| 37 | pinctrl-single,pins = < | ||
| 38 | OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ | ||
| 39 | OMAP3_CORE1_IOPAD(0x21a2, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ | ||
| 40 | OMAP3_CORE1_IOPAD(0x21a4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ | ||
| 41 | OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ | ||
| 42 | OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data0.hsusb2_data0 */ | ||
| 43 | OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ | ||
| 44 | OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ | ||
| 45 | OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data3 */ | ||
| 46 | OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data4 */ | ||
| 47 | OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data5 */ | ||
| 48 | OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data6 */ | ||
| 49 | OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ | ||
| 50 | >; | ||
| 51 | }; | ||
| 52 | }; | ||
| 53 | |||
| 39 | &gpmc { | 54 | &gpmc { |
| 40 | ranges = <5 0 0x2c000000 0x01000000>; | 55 | ranges = <5 0 0x2c000000 0x01000000>; |
| 41 | 56 | ||
| 42 | smsc1: ethernet@5,0 { | 57 | smsc1: ethernet@5,0 { |
| 43 | compatible = "smsc,lan9221", "smsc,lan9115"; | 58 | compatible = "smsc,lan9221", "smsc,lan9115"; |
| 59 | pinctrl-names = "default"; | ||
| 60 | pinctrl-0 = <&smsc1_pins>; | ||
| 44 | interrupt-parent = <&gpio6>; | 61 | interrupt-parent = <&gpio6>; |
| 45 | interrupts = <3 IRQ_TYPE_LEVEL_LOW>; | 62 | interrupts = <3 IRQ_TYPE_LEVEL_LOW>; |
| 46 | reg = <5 0 0xff>; | 63 | reg = <5 0 0xff>; |
| @@ -74,8 +91,6 @@ | |||
| 74 | }; | 91 | }; |
| 75 | 92 | ||
| 76 | &i2c1 { | 93 | &i2c1 { |
| 77 | clock-frequency = <400000>; | ||
| 78 | |||
| 79 | twl: twl@48 { | 94 | twl: twl@48 { |
| 80 | reg = <0x48>; | 95 | reg = <0x48>; |
| 81 | interrupts = <7>; /* SYS_NIRQ cascaded to intc */ | 96 | interrupts = <7>; /* SYS_NIRQ cascaded to intc */ |
| @@ -86,10 +101,31 @@ | |||
| 86 | #include "twl4030.dtsi" | 101 | #include "twl4030.dtsi" |
| 87 | #include "twl4030_omap3.dtsi" | 102 | #include "twl4030_omap3.dtsi" |
| 88 | 103 | ||
| 89 | &i2c3 { | 104 | &mmc1 { |
| 90 | clock-frequency = <400000>; | 105 | vmmc-supply = <&vmmc1>; |
| 91 | }; | 106 | }; |
| 92 | 107 | ||
| 93 | &twl_gpio { | 108 | &twl_gpio { |
| 94 | ti,use-leds; | 109 | ti,use-leds; |
| 110 | /* pullups: BIT(0) */ | ||
| 111 | ti,pullups = <0x000001>; | ||
| 112 | }; | ||
| 113 | |||
| 114 | &hsusb1_phy { | ||
| 115 | reset-gpios = <&twl_gpio 6 GPIO_ACTIVE_LOW>; | ||
| 116 | }; | ||
| 117 | |||
| 118 | &hsusb2_phy { | ||
| 119 | reset-gpios = <&twl_gpio 7 GPIO_ACTIVE_LOW>; | ||
| 120 | }; | ||
| 121 | |||
| 122 | &usb_otg_hs { | ||
| 123 | pinctrl-names = "default"; | ||
| 124 | pinctrl-0 = <&hsusb0_pins>; | ||
| 125 | interface-type = <0>; | ||
| 126 | usb-phy = <&usb2_phy>; | ||
| 127 | phys = <&usb2_phy>; | ||
| 128 | phy-names = "usb2-phy"; | ||
| 129 | mode = <3>; | ||
| 130 | power = <50>; | ||
| 95 | }; | 131 | }; |
diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts index 4665421bb7bc..bf5a515a3247 100644 --- a/arch/arm/boot/dts/omap3-devkit8000.dts +++ b/arch/arm/boot/dts/omap3-devkit8000.dts | |||
| @@ -101,20 +101,8 @@ | |||
| 101 | status = "disabled"; | 101 | status = "disabled"; |
| 102 | }; | 102 | }; |
| 103 | 103 | ||
| 104 | &mcbsp1 { | 104 | &mcbsp2 { |
| 105 | status = "disabled"; | 105 | status = "okay"; |
| 106 | }; | ||
| 107 | |||
| 108 | &mcbsp3 { | ||
| 109 | status = "disabled"; | ||
| 110 | }; | ||
| 111 | |||
| 112 | &mcbsp4 { | ||
| 113 | status = "disabled"; | ||
| 114 | }; | ||
| 115 | |||
| 116 | &mcbsp5 { | ||
| 117 | status = "disabled"; | ||
| 118 | }; | 106 | }; |
| 119 | 107 | ||
| 120 | &gpmc { | 108 | &gpmc { |
diff --git a/arch/arm/boot/dts/omap3-gta04.dts b/arch/arm/boot/dts/omap3-gta04.dts index c551e4af4d83..7d760aa4ed15 100644 --- a/arch/arm/boot/dts/omap3-gta04.dts +++ b/arch/arm/boot/dts/omap3-gta04.dts | |||
| @@ -36,6 +36,14 @@ | |||
| 36 | gpio-key,wakeup; | 36 | gpio-key,wakeup; |
| 37 | }; | 37 | }; |
| 38 | }; | 38 | }; |
| 39 | |||
| 40 | sound { | ||
| 41 | compatible = "ti,omap-twl4030"; | ||
| 42 | ti,model = "gta04"; | ||
| 43 | |||
| 44 | ti,mcbsp = <&mcbsp2>; | ||
| 45 | ti,codec = <&twl_audio>; | ||
| 46 | }; | ||
| 39 | }; | 47 | }; |
| 40 | 48 | ||
| 41 | &omap3_pmx_core { | 49 | &omap3_pmx_core { |
| @@ -80,6 +88,12 @@ | |||
| 80 | interrupts = <7>; /* SYS_NIRQ cascaded to intc */ | 88 | interrupts = <7>; /* SYS_NIRQ cascaded to intc */ |
| 81 | interrupt-parent = <&intc>; | 89 | interrupt-parent = <&intc>; |
| 82 | }; | 90 | }; |
| 91 | |||
| 92 | twl_audio: audio { | ||
| 93 | compatible = "ti,twl4030-audio"; | ||
| 94 | codec { | ||
| 95 | }; | ||
| 96 | }; | ||
| 83 | }; | 97 | }; |
| 84 | 98 | ||
| 85 | #include "twl4030.dtsi" | 99 | #include "twl4030.dtsi" |
| @@ -96,6 +110,14 @@ | |||
| 96 | interrupts = <17 IRQ_TYPE_EDGE_RISING>; | 110 | interrupts = <17 IRQ_TYPE_EDGE_RISING>; |
| 97 | }; | 111 | }; |
| 98 | 112 | ||
| 113 | /* accelerometer */ | ||
| 114 | bma180@41 { | ||
| 115 | compatible = "bosch,bma180"; | ||
| 116 | reg = <0x41>; | ||
| 117 | interrupt-parent = <&gpio3>; | ||
| 118 | interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; | ||
| 119 | }; | ||
| 120 | |||
| 99 | /* leds */ | 121 | /* leds */ |
| 100 | tca6507@45 { | 122 | tca6507@45 { |
| 101 | compatible = "ti,tca6507"; | 123 | compatible = "ti,tca6507"; |
| @@ -124,6 +146,22 @@ | |||
| 124 | reg = <0x4>; | 146 | reg = <0x4>; |
| 125 | }; | 147 | }; |
| 126 | }; | 148 | }; |
| 149 | |||
| 150 | /* compass aka magnetometer */ | ||
| 151 | hmc5843@1e { | ||
| 152 | compatible = "honeywell,hmc5843"; | ||
| 153 | reg = <0x1e>; | ||
| 154 | }; | ||
| 155 | |||
| 156 | /* touchscreen */ | ||
| 157 | tsc2007@48 { | ||
| 158 | compatible = "ti,tsc2007"; | ||
| 159 | reg = <0x48>; | ||
| 160 | interrupt-parent = <&gpio6>; | ||
| 161 | interrupts = <0 IRQ_TYPE_EDGE_FALLING>; | ||
| 162 | gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; | ||
| 163 | ti,x-plate-ohms = <600>; | ||
| 164 | }; | ||
| 127 | }; | 165 | }; |
| 128 | 166 | ||
| 129 | &i2c3 { | 167 | &i2c3 { |
| @@ -148,7 +186,9 @@ | |||
| 148 | }; | 186 | }; |
| 149 | 187 | ||
| 150 | &mmc2 { | 188 | &mmc2 { |
| 151 | status = "disabled"; | 189 | vmmc-supply = <&vaux4>; |
| 190 | bus-width = <4>; | ||
| 191 | ti,non-removable; | ||
| 152 | }; | 192 | }; |
| 153 | 193 | ||
| 154 | &mmc3 { | 194 | &mmc3 { |
| @@ -170,3 +210,12 @@ | |||
| 170 | pinctrl-0 = <&uart3_pins>; | 210 | pinctrl-0 = <&uart3_pins>; |
| 171 | }; | 211 | }; |
| 172 | 212 | ||
| 213 | &charger { | ||
| 214 | bb_uvolt = <3200000>; | ||
| 215 | bb_uamp = <150>; | ||
| 216 | }; | ||
| 217 | |||
| 218 | &vaux4 { | ||
| 219 | regulator-min-microvolt = <2800000>; | ||
| 220 | regulator-max-microvolt = <3150000>; | ||
| 221 | }; | ||
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi index c17009323520..b97736d98a64 100644 --- a/arch/arm/boot/dts/omap3-igep.dtsi +++ b/arch/arm/boot/dts/omap3-igep.dtsi | |||
| @@ -170,6 +170,7 @@ | |||
| 170 | &mcbsp2 { | 170 | &mcbsp2 { |
| 171 | pinctrl-names = "default"; | 171 | pinctrl-names = "default"; |
| 172 | pinctrl-0 = <&mcbsp2_pins>; | 172 | pinctrl-0 = <&mcbsp2_pins>; |
| 173 | status = "okay"; | ||
| 173 | }; | 174 | }; |
| 174 | 175 | ||
| 175 | &mmc1 { | 176 | &mmc1 { |
diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi new file mode 100644 index 000000000000..6369d9f43ca2 --- /dev/null +++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi | |||
| @@ -0,0 +1,459 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2014 Christoph Fritz <chf.fritzc@googlemail.com> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #include "omap36xx.dtsi" | ||
| 11 | |||
| 12 | / { | ||
| 13 | model = "INCOstartec LILLY-A83X module (DM3730)"; | ||
| 14 | compatible = "incostartec,omap3-lilly-a83x", "ti,omap36xx", "ti,omap3"; | ||
| 15 | |||
| 16 | chosen { | ||
| 17 | bootargs = "console=ttyO0,115200n8 vt.global_cursor_default=0 consoleblank=0"; | ||
| 18 | }; | ||
| 19 | |||
| 20 | memory { | ||
| 21 | device_type = "memory"; | ||
| 22 | reg = <0x80000000 0x8000000>; /* 128 MB */ | ||
| 23 | }; | ||
| 24 | |||
| 25 | leds { | ||
| 26 | compatible = "gpio-leds"; | ||
| 27 | |||
| 28 | led1 { | ||
| 29 | label = "lilly-a83x::led1"; | ||
| 30 | gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; | ||
| 31 | linux,default-trigger = "default-on"; | ||
| 32 | }; | ||
| 33 | |||
| 34 | }; | ||
| 35 | |||
| 36 | sound { | ||
| 37 | compatible = "ti,omap-twl4030"; | ||
| 38 | ti,model = "lilly-a83x"; | ||
| 39 | |||
| 40 | ti,mcbsp = <&mcbsp2>; | ||
| 41 | ti,codec = <&twl_audio>; | ||
| 42 | }; | ||
| 43 | |||
| 44 | reg_vcc3: vcc3 { | ||
| 45 | compatible = "regulator-fixed"; | ||
| 46 | regulator-name = "VCC3"; | ||
| 47 | regulator-min-microvolt = <3300000>; | ||
| 48 | regulator-max-microvolt = <3300000>; | ||
| 49 | regulator-always-on; | ||
| 50 | }; | ||
| 51 | |||
| 52 | hsusb1_phy: hsusb1_phy { | ||
| 53 | compatible = "usb-nop-xceiv"; | ||
| 54 | vcc-supply = <®_vcc3>; | ||
| 55 | }; | ||
| 56 | }; | ||
| 57 | |||
| 58 | &omap3_pmx_wkup { | ||
| 59 | pinctrl-names = "default"; | ||
| 60 | |||
| 61 | lan9221_pins: pinmux_lan9221_pins { | ||
| 62 | pinctrl-single,pins = < | ||
| 63 | OMAP3_WKUP_IOPAD(0x2a5a, PIN_INPUT | MUX_MODE4) /* reserved.gpio_129 */ | ||
| 64 | >; | ||
| 65 | }; | ||
| 66 | |||
| 67 | tsc2048_pins: pinmux_tsc2048_pins { | ||
| 68 | pinctrl-single,pins = < | ||
| 69 | OMAP3_WKUP_IOPAD(0x2a16, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot6.gpio_8 */ | ||
| 70 | >; | ||
| 71 | }; | ||
| 72 | |||
| 73 | mmc1cd_pins: pinmux_mmc1cd_pins { | ||
| 74 | pinctrl-single,pins = < | ||
| 75 | OMAP3_WKUP_IOPAD(0x2a56, PIN_INPUT | MUX_MODE4) /* reserved.gpio_126 */ | ||
| 76 | >; | ||
| 77 | }; | ||
| 78 | }; | ||
| 79 | |||
| 80 | &omap3_pmx_core { | ||
| 81 | pinctrl-names = "default"; | ||
| 82 | |||
| 83 | uart1_pins: pinmux_uart1_pins { | ||
| 84 | pinctrl-single,pins = < | ||
| 85 | OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ | ||
| 86 | OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */ | ||
| 87 | OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */ | ||
| 88 | OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ | ||
| 89 | >; | ||
| 90 | }; | ||
| 91 | |||
| 92 | uart2_pins: pinmux_uart2_pins { | ||
| 93 | pinctrl-single,pins = < | ||
| 94 | OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clkx.uart2_tx */ | ||
| 95 | OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */ | ||
| 96 | >; | ||
| 97 | }; | ||
| 98 | |||
| 99 | uart3_pins: pinmux_uart3_pins { | ||
| 100 | pinctrl-single,pins = < | ||
| 101 | OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ | ||
| 102 | OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ | ||
| 103 | >; | ||
| 104 | }; | ||
| 105 | |||
| 106 | i2c1_pins: pinmux_i2c1_pins { | ||
| 107 | pinctrl-single,pins = < | ||
| 108 | OMAP3_CORE1_IOPAD(0x21ba ,PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */ | ||
| 109 | OMAP3_CORE1_IOPAD(0x21bc ,PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */ | ||
| 110 | >; | ||
| 111 | }; | ||
| 112 | |||
| 113 | i2c2_pins: pinmux_i2c2_pins { | ||
| 114 | pinctrl-single,pins = < | ||
| 115 | OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */ | ||
| 116 | OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */ | ||
| 117 | >; | ||
| 118 | }; | ||
| 119 | |||
| 120 | i2c3_pins: pinmux_i2c3_pins { | ||
| 121 | pinctrl-single,pins = < | ||
| 122 | OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ | ||
| 123 | OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */ | ||
| 124 | >; | ||
| 125 | }; | ||
| 126 | |||
| 127 | hsusb1_pins: pinmux_hsusb1_pins { | ||
| 128 | pinctrl-single,pins = < | ||
| 129 | |||
| 130 | /* GPIO 182 controls USB-Hub reset. But USB-Phy its | ||
| 131 | * reset can't be controlled. So we clamp this GPIO to | ||
| 132 | * high (PIN_OFF_OUTPUT_HIGH) to always enable USB-Hub. | ||
| 133 | */ | ||
| 134 | |||
| 135 | OMAP3_CORE1_IOPAD(0x21de, PIN_OUTPUT_PULLUP | PIN_OFF_OUTPUT_HIGH | MUX_MODE4) /* mcspi2_cs1.gpio_182 */ | ||
| 136 | >; | ||
| 137 | }; | ||
| 138 | |||
| 139 | hsusb_otg_pins: pinmux_hsusb_otg_pins { | ||
| 140 | pinctrl-single,pins = < | ||
| 141 | OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ | ||
| 142 | OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ | ||
| 143 | OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ | ||
| 144 | OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ | ||
| 145 | OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ | ||
| 146 | OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ | ||
| 147 | OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ | ||
| 148 | OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */ | ||
| 149 | OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */ | ||
| 150 | OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */ | ||
| 151 | OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ | ||
| 152 | OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ | ||
| 153 | >; | ||
| 154 | }; | ||
| 155 | |||
| 156 | mmc1_pins: pinmux_mmc1_pins { | ||
| 157 | pinctrl-single,pins = < | ||
| 158 | OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ | ||
| 159 | OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ | ||
| 160 | OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ | ||
| 161 | OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ | ||
| 162 | OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ | ||
| 163 | OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ | ||
| 164 | >; | ||
| 165 | }; | ||
| 166 | |||
| 167 | spi2_pins: pinmux_spi2_pins { | ||
| 168 | pinctrl-single,pins = < | ||
| 169 | OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_clk.mcspi2_clk */ | ||
| 170 | OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_simo.mcspi2_simo */ | ||
| 171 | OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_somi.mcspi2_somi */ | ||
| 172 | OMAP3_CORE1_IOPAD(0x21dc, PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0.mcspi2_cs0 */ | ||
| 173 | >; | ||
| 174 | }; | ||
| 175 | }; | ||
| 176 | |||
| 177 | &omap3_pmx_core2 { | ||
| 178 | pinctrl-names = "default"; | ||
| 179 | pinctrl-0 = < | ||
| 180 | &hsusb1_2_pins | ||
| 181 | >; | ||
| 182 | |||
| 183 | hsusb1_2_pins: pinmux_hsusb1_2_pins { | ||
| 184 | pinctrl-single,pins = < | ||
| 185 | OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ | ||
| 186 | OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ | ||
| 187 | OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE3) /* etk_d0.hsusb1_data0 */ | ||
| 188 | OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT | MUX_MODE3) /* etk_d1.hsusb1_data1 */ | ||
| 189 | OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT | MUX_MODE3) /* etk_d2.hsusb1_data2 */ | ||
| 190 | OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT | MUX_MODE3) /* etk_d3.hsusb1_data7 */ | ||
| 191 | OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE3) /* etk_d4.hsusb1_data4 */ | ||
| 192 | OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT | MUX_MODE3) /* etk_d5.hsusb1_data5 */ | ||
| 193 | OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT | MUX_MODE3) /* etk_d6.hsusb1_data6 */ | ||
| 194 | OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE3) /* etk_d7.hsusb1_data3 */ | ||
| 195 | OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT | MUX_MODE3) /* etk_d8.hsusb1_dir */ | ||
| 196 | OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE3) /* etk_d9.hsusb1_nxt */ | ||
| 197 | >; | ||
| 198 | }; | ||
| 199 | |||
| 200 | gpio1_pins: pinmux_gpio1_pins { | ||
| 201 | pinctrl-single,pins = < | ||
| 202 | OMAP3630_CORE2_IOPAD(0x25fa, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* etk_d15.gpio_29 */ | ||
| 203 | >; | ||
| 204 | }; | ||
| 205 | |||
| 206 | }; | ||
| 207 | |||
| 208 | &gpio1 { | ||
| 209 | pinctrl-names = "default"; | ||
| 210 | pinctrl-0 = <&gpio1_pins>; | ||
| 211 | }; | ||
| 212 | |||
| 213 | &gpio6 { | ||
| 214 | pinctrl-names = "default"; | ||
| 215 | pinctrl-0 = <&hsusb1_pins>; | ||
| 216 | }; | ||
| 217 | |||
| 218 | &i2c1 { | ||
| 219 | clock-frequency = <2600000>; | ||
| 220 | pinctrl-names = "default"; | ||
| 221 | pinctrl-0 = <&i2c1_pins>; | ||
| 222 | |||
| 223 | twl: twl@48 { | ||
| 224 | reg = <0x48>; | ||
| 225 | interrupts = <7>; /* SYS_NIRQ cascaded to intc */ | ||
| 226 | interrupt-parent = <&intc>; | ||
| 227 | |||
| 228 | twl_audio: audio { | ||
| 229 | compatible = "ti,twl4030-audio"; | ||
| 230 | codec { | ||
| 231 | }; | ||
| 232 | }; | ||
| 233 | }; | ||
| 234 | }; | ||
| 235 | |||
| 236 | #include "twl4030.dtsi" | ||
| 237 | #include "twl4030_omap3.dtsi" | ||
| 238 | |||
| 239 | &twl { | ||
| 240 | vmmc1: regulator-vmmc1 { | ||
| 241 | regulator-always-on; | ||
| 242 | }; | ||
| 243 | |||
| 244 | vdd1: regulator-vdd1 { | ||
| 245 | regulator-always-on; | ||
| 246 | }; | ||
| 247 | |||
| 248 | vdd2: regulator-vdd2 { | ||
| 249 | regulator-always-on; | ||
| 250 | }; | ||
| 251 | }; | ||
| 252 | |||
| 253 | &i2c2 { | ||
| 254 | clock-frequency = <2600000>; | ||
| 255 | pinctrl-names = "default"; | ||
| 256 | pinctrl-0 = <&i2c2_pins>; | ||
| 257 | }; | ||
| 258 | |||
| 259 | &i2c3 { | ||
| 260 | clock-frequency = <2600000>; | ||
| 261 | pinctrl-names = "default"; | ||
| 262 | pinctrl-0 = <&i2c3_pins>; | ||
| 263 | gpiom1: gpio@20 { | ||
| 264 | compatible = "mcp,mcp23017"; | ||
| 265 | gpio-controller; | ||
| 266 | #gpio-cells = <2>; | ||
| 267 | reg = <0x20>; | ||
| 268 | }; | ||
| 269 | }; | ||
| 270 | |||
| 271 | &uart1 { | ||
| 272 | pinctrl-names = "default"; | ||
| 273 | pinctrl-0 = <&uart1_pins>; | ||
| 274 | }; | ||
| 275 | |||
| 276 | &uart2 { | ||
| 277 | pinctrl-names = "default"; | ||
| 278 | pinctrl-0 = <&uart2_pins>; | ||
| 279 | }; | ||
| 280 | |||
| 281 | &uart3 { | ||
| 282 | pinctrl-names = "default"; | ||
| 283 | pinctrl-0 = <&uart3_pins>; | ||
| 284 | }; | ||
| 285 | |||
| 286 | &uart4 { | ||
| 287 | status = "disabled"; | ||
| 288 | }; | ||
| 289 | |||
| 290 | &mmc1 { | ||
| 291 | cd-gpios = <&gpio4 30 IRQ_TYPE_LEVEL_LOW>; | ||
| 292 | cd-inverted; | ||
| 293 | vmmc-supply = <&vmmc1>; | ||
| 294 | bus-width = <4>; | ||
| 295 | pinctrl-names = "default"; | ||
| 296 | pinctrl-0 = <&mmc1_pins &mmc1cd_pins>; | ||
| 297 | cap-sdio-irq; | ||
| 298 | cap-sd-highspeed; | ||
| 299 | cap-mmc-highspeed; | ||
| 300 | }; | ||
| 301 | |||
| 302 | &mmc2 { | ||
| 303 | status = "disabled"; | ||
| 304 | }; | ||
| 305 | |||
| 306 | &mmc3 { | ||
| 307 | status = "disabled"; | ||
| 308 | }; | ||
| 309 | |||
| 310 | &mcspi2 { | ||
| 311 | status = "okay"; | ||
| 312 | pinctrl-names = "default"; | ||
| 313 | pinctrl-0 = <&spi2_pins>; | ||
| 314 | |||
| 315 | tsc2046@0 { | ||
| 316 | reg = <0>; /* CS0 */ | ||
| 317 | compatible = "ti,tsc2046"; | ||
| 318 | interrupt-parent = <&gpio1>; | ||
| 319 | interrupts = <8 0>; /* boot6 / gpio_8 */ | ||
| 320 | spi-max-frequency = <1000000>; | ||
| 321 | pendown-gpio = <&gpio1 8 0>; | ||
| 322 | vcc-supply = <®_vcc3>; | ||
| 323 | pinctrl-names = "default"; | ||
| 324 | pinctrl-0 = <&tsc2048_pins>; | ||
| 325 | |||
| 326 | ti,x-min = <300>; | ||
| 327 | ti,x-max = <3000>; | ||
| 328 | ti,y-min = <600>; | ||
| 329 | ti,y-max = <3600>; | ||
| 330 | ti,x-plate-ohms = <80>; | ||
| 331 | ti,pressure-max = <255>; | ||
| 332 | ti,swap-xy; | ||
| 333 | |||
| 334 | linux,wakeup; | ||
| 335 | }; | ||
| 336 | }; | ||
| 337 | |||
| 338 | &usbhsehci { | ||
| 339 | phys = <&hsusb1_phy>; | ||
| 340 | }; | ||
| 341 | |||
| 342 | &usbhshost { | ||
| 343 | pinctrl-names = "default"; | ||
| 344 | pinctrl-0 = <&hsusb1_2_pins>; | ||
| 345 | num-ports = <2>; | ||
| 346 | port1-mode = "ehci-phy"; | ||
| 347 | }; | ||
| 348 | |||
| 349 | &usb_otg_hs { | ||
| 350 | pinctrl-names = "default"; | ||
| 351 | pinctrl-0 = <&hsusb_otg_pins>; | ||
| 352 | interface-type = <0>; | ||
| 353 | usb-phy = <&usb2_phy>; | ||
| 354 | phys = <&usb2_phy>; | ||
| 355 | phy-names = "usb2-phy"; | ||
| 356 | mode = <3>; | ||
| 357 | power = <50>; | ||
| 358 | }; | ||
| 359 | |||
| 360 | &gpmc { | ||
| 361 | ranges = <0 0 0x30000000 0x1000000>, | ||
| 362 | <7 0 0x15000000 0x01000000>; | ||
| 363 | |||
| 364 | nand@0,0 { | ||
| 365 | reg = <0 0 0x1000000>; | ||
| 366 | nand-bus-width = <16>; | ||
| 367 | ti,nand-ecc-opt = "bch8"; | ||
| 368 | /* no elm on omap3 */ | ||
| 369 | |||
| 370 | gpmc,mux-add-data = <0>; | ||
| 371 | gpmc,device-nand; | ||
| 372 | gpmc,device-width = <2>; | ||
| 373 | gpmc,wait-pin = <0>; | ||
| 374 | gpmc,wait-monitoring-ns = <0>; | ||
| 375 | gpmc,burst-length= <4>; | ||
| 376 | gpmc,cs-on-ns = <0>; | ||
| 377 | gpmc,cs-rd-off-ns = <100>; | ||
| 378 | gpmc,cs-wr-off-ns = <100>; | ||
| 379 | gpmc,adv-on-ns = <0>; | ||
| 380 | gpmc,adv-rd-off-ns = <100>; | ||
| 381 | gpmc,adv-wr-off-ns = <100>; | ||
| 382 | gpmc,oe-on-ns = <5>; | ||
| 383 | gpmc,oe-off-ns = <75>; | ||
| 384 | gpmc,we-on-ns = <5>; | ||
| 385 | gpmc,we-off-ns = <75>; | ||
| 386 | gpmc,rd-cycle-ns = <100>; | ||
| 387 | gpmc,wr-cycle-ns = <100>; | ||
| 388 | gpmc,access-ns = <60>; | ||
| 389 | gpmc,page-burst-access-ns = <5>; | ||
| 390 | gpmc,bus-turnaround-ns = <0>; | ||
| 391 | gpmc,cycle2cycle-samecsen; | ||
| 392 | gpmc,cycle2cycle-delay-ns = <50>; | ||
| 393 | gpmc,wr-data-mux-bus-ns = <75>; | ||
| 394 | gpmc,wr-access-ns = <155>; | ||
| 395 | |||
| 396 | #address-cells = <1>; | ||
| 397 | #size-cells = <1>; | ||
| 398 | |||
| 399 | partition@0 { | ||
| 400 | label = "MLO"; | ||
| 401 | reg = <0 0x80000>; | ||
| 402 | }; | ||
| 403 | |||
| 404 | partition@0x80000 { | ||
| 405 | label = "u-boot"; | ||
| 406 | reg = <0x80000 0x1e0000>; | ||
| 407 | }; | ||
| 408 | |||
| 409 | partition@0x260000 { | ||
| 410 | label = "u-boot-environment"; | ||
| 411 | reg = <0x260000 0x20000>; | ||
| 412 | }; | ||
| 413 | |||
| 414 | partition@0x280000 { | ||
| 415 | label = "kernel"; | ||
| 416 | reg = <0x280000 0x500000>; | ||
| 417 | }; | ||
| 418 | |||
| 419 | partition@0x780000 { | ||
| 420 | label = "filesystem"; | ||
| 421 | reg = <0x780000 0xf880000>; | ||
| 422 | }; | ||
| 423 | }; | ||
| 424 | |||
| 425 | ethernet@7,0 { | ||
| 426 | compatible = "smsc,lan9221", "smsc,lan9115"; | ||
| 427 | bank-width = <2>; | ||
| 428 | gpmc,mux-add-data = <2>; | ||
| 429 | gpmc,cs-on-ns = <10>; | ||
| 430 | gpmc,cs-rd-off-ns = <60>; | ||
| 431 | gpmc,cs-wr-off-ns = <60>; | ||
| 432 | gpmc,adv-on-ns = <0>; | ||
| 433 | gpmc,adv-rd-off-ns = <10>; | ||
| 434 | gpmc,adv-wr-off-ns = <10>; | ||
| 435 | gpmc,oe-on-ns = <10>; | ||
| 436 | gpmc,oe-off-ns = <60>; | ||
| 437 | gpmc,we-on-ns = <10>; | ||
| 438 | gpmc,we-off-ns = <60>; | ||
| 439 | gpmc,rd-cycle-ns = <100>; | ||
| 440 | gpmc,wr-cycle-ns = <100>; | ||
| 441 | gpmc,access-ns = <50>; | ||
| 442 | gpmc,page-burst-access-ns = <5>; | ||
| 443 | gpmc,bus-turnaround-ns = <0>; | ||
| 444 | gpmc,cycle2cycle-delay-ns = <75>; | ||
| 445 | gpmc,wr-data-mux-bus-ns = <15>; | ||
| 446 | gpmc,wr-access-ns = <75>; | ||
| 447 | gpmc,cycle2cycle-samecsen; | ||
| 448 | gpmc,cycle2cycle-diffcsen; | ||
| 449 | vddvario-supply = <®_vcc3>; | ||
| 450 | vdd33a-supply = <®_vcc3>; | ||
| 451 | reg-io-width = <4>; | ||
| 452 | interrupt-parent = <&gpio5>; | ||
| 453 | interrupts = <1 0x2>; | ||
| 454 | reg = <7 0 0xff>; | ||
| 455 | pinctrl-names = "default"; | ||
| 456 | pinctrl-0 = <&lan9221_pins>; | ||
| 457 | phy-mode = "mii"; | ||
| 458 | }; | ||
| 459 | }; | ||
diff --git a/arch/arm/boot/dts/omap3-lilly-dbb056.dts b/arch/arm/boot/dts/omap3-lilly-dbb056.dts new file mode 100644 index 000000000000..834f7c65f62d --- /dev/null +++ b/arch/arm/boot/dts/omap3-lilly-dbb056.dts | |||
| @@ -0,0 +1,170 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2014 Christoph Fritz <chf.fritzc@googlemail.com> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | */ | ||
| 9 | /dts-v1/; | ||
| 10 | |||
| 11 | #include "omap3-lilly-a83x.dtsi" | ||
| 12 | |||
| 13 | / { | ||
| 14 | model = "INCOstartec LILLY-DBB056 (DM3730)"; | ||
| 15 | compatible = "incostartec,omap3-lilly-dbb056", "incostartec,omap3-lilly-a83x", "ti,omap36xx", "ti,omap3"; | ||
| 16 | }; | ||
| 17 | |||
| 18 | &twl { | ||
| 19 | vaux2: regulator-vaux2 { | ||
| 20 | compatible = "ti,twl4030-vaux2"; | ||
| 21 | regulator-min-microvolt = <2800000>; | ||
| 22 | regulator-max-microvolt = <2800000>; | ||
| 23 | regulator-always-on; | ||
| 24 | }; | ||
| 25 | }; | ||
| 26 | |||
| 27 | &omap3_pmx_core { | ||
| 28 | pinctrl-names = "default"; | ||
| 29 | pinctrl-0 = <&lcd_pins>; | ||
| 30 | |||
| 31 | lan9117_pins: pinmux_lan9117_pins { | ||
| 32 | pinctrl-single,pins = < | ||
| 33 | OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE4) /* cam_fld.gpio_98 */ | ||
| 34 | >; | ||
| 35 | }; | ||
| 36 | |||
| 37 | gpio4_pins: pinmux_gpio4_pins { | ||
| 38 | pinctrl-single,pins = < | ||
| 39 | OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT | MUX_MODE4) /* cam_xclkb.gpio_111 -> sja1000 IRQ */ | ||
| 40 | >; | ||
| 41 | }; | ||
| 42 | |||
| 43 | gpio5_pins: pinmux_gpio5_pins { | ||
| 44 | pinctrl-single,pins = < | ||
| 45 | OMAP3_CORE1_IOPAD(0x218c, PIN_OUTPUT | PIN_OFF_OUTPUT_HIGH | MUX_MODE4) /* mcbsp1_clk.gpio_156 -> enable DSS */ | ||
| 46 | >; | ||
| 47 | }; | ||
| 48 | |||
| 49 | lcd_pins: pinmux_lcd_pins { | ||
| 50 | pinctrl-single,pins = < | ||
| 51 | OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ | ||
| 52 | OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ | ||
| 53 | OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ | ||
| 54 | OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ | ||
| 55 | OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ | ||
| 56 | OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ | ||
| 57 | OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ | ||
| 58 | OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ | ||
| 59 | OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ | ||
| 60 | OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ | ||
| 61 | OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ | ||
| 62 | OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ | ||
| 63 | OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ | ||
| 64 | OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ | ||
| 65 | OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ | ||
| 66 | OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ | ||
| 67 | OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ | ||
| 68 | OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ | ||
| 69 | OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ | ||
| 70 | OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ | ||
| 71 | OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ | ||
| 72 | OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ | ||
| 73 | >; | ||
| 74 | }; | ||
| 75 | |||
| 76 | mmc2_pins: pinmux_mmc2_pins { | ||
| 77 | pinctrl-single,pins = < | ||
| 78 | OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ | ||
| 79 | OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ | ||
| 80 | OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ | ||
| 81 | OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ | ||
| 82 | OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ | ||
| 83 | OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ | ||
| 84 | OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */ | ||
| 85 | OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */ | ||
| 86 | OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */ | ||
| 87 | OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ | ||
| 88 | OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_163 -> wp */ | ||
| 89 | OMAP3_CORE1_IOPAD(0x219c, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_rts_sd.gpio_164 -> cd */ | ||
| 90 | >; | ||
| 91 | }; | ||
| 92 | |||
| 93 | spi1_pins: pinmux_spi1_pins { | ||
| 94 | pinctrl-single,pins = < | ||
| 95 | OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ | ||
| 96 | OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ | ||
| 97 | OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ | ||
| 98 | OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ | ||
| 99 | >; | ||
| 100 | }; | ||
| 101 | }; | ||
| 102 | |||
| 103 | &gpio4 { | ||
| 104 | pinctrl-names = "default"; | ||
| 105 | pinctrl-0 = <&gpio4_pins>; | ||
| 106 | }; | ||
| 107 | |||
| 108 | &gpio5 { | ||
| 109 | pinctrl-names = "default"; | ||
| 110 | pinctrl-0 = <&gpio5_pins>; | ||
| 111 | }; | ||
| 112 | |||
| 113 | &mmc2 { | ||
| 114 | status = "okay"; | ||
| 115 | bus-width = <4>; | ||
| 116 | vmmc-supply = <&vmmc1>; | ||
| 117 | cd-gpios = <&gpio6 4 0>; /* gpio_164 */ | ||
| 118 | wp-gpios = <&gpio6 3 0>; /* gpio_163 */ | ||
| 119 | pinctrl-names = "default"; | ||
| 120 | pinctrl-0 = <&mmc2_pins>; | ||
| 121 | ti,dual-volt; | ||
| 122 | }; | ||
| 123 | |||
| 124 | &mcspi1 { | ||
| 125 | status = "okay"; | ||
| 126 | pinctrl-names = "default"; | ||
| 127 | pinctrl-0 = <&spi1_pins>; | ||
| 128 | }; | ||
| 129 | |||
| 130 | &gpmc { | ||
| 131 | ranges = <0 0 0x30000000 0x1000000>, /* nand assigned by COM a83x */ | ||
| 132 | <4 0 0x20000000 0x01000000>, | ||
| 133 | <7 0 0x15000000 0x01000000>; /* eth assigend by COM a83x */ | ||
| 134 | |||
| 135 | ethernet@4,0 { | ||
| 136 | compatible = "smsc,lan9117", "smsc,lan9115"; | ||
| 137 | bank-width = <2>; | ||
| 138 | gpmc,mux-add-data = <2>; | ||
| 139 | gpmc,cs-on-ns = <10>; | ||
| 140 | gpmc,cs-rd-off-ns = <65>; | ||
| 141 | gpmc,cs-wr-off-ns = <65>; | ||
| 142 | gpmc,adv-on-ns = <0>; | ||
| 143 | gpmc,adv-rd-off-ns = <10>; | ||
| 144 | gpmc,adv-wr-off-ns = <10>; | ||
| 145 | gpmc,oe-on-ns = <10>; | ||
| 146 | gpmc,oe-off-ns = <65>; | ||
| 147 | gpmc,we-on-ns = <10>; | ||
| 148 | gpmc,we-off-ns = <65>; | ||
| 149 | gpmc,rd-cycle-ns = <100>; | ||
| 150 | gpmc,wr-cycle-ns = <100>; | ||
| 151 | gpmc,access-ns = <60>; | ||
| 152 | gpmc,page-burst-access-ns = <5>; | ||
| 153 | gpmc,bus-turnaround-ns = <0>; | ||
| 154 | gpmc,cycle2cycle-delay-ns = <75>; | ||
| 155 | gpmc,wr-data-mux-bus-ns = <15>; | ||
| 156 | gpmc,wr-access-ns = <75>; | ||
| 157 | gpmc,cycle2cycle-samecsen; | ||
| 158 | gpmc,cycle2cycle-diffcsen; | ||
| 159 | vddvario-supply = <®_vcc3>; | ||
| 160 | vdd33a-supply = <®_vcc3>; | ||
| 161 | reg-io-width = <4>; | ||
| 162 | interrupt-parent = <&gpio4>; | ||
| 163 | interrupts = <2 0x2>; | ||
| 164 | reg = <4 0 0xff>; | ||
| 165 | pinctrl-names = "default"; | ||
| 166 | pinctrl-0 = <&lan9117_pins>; | ||
| 167 | phy-mode = "mii"; | ||
| 168 | smsc,force-internal-phy; | ||
| 169 | }; | ||
| 170 | }; | ||
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 0bf40c90faba..d1c3d99dc947 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts | |||
| @@ -74,6 +74,11 @@ | |||
| 74 | }; | 74 | }; |
| 75 | }; | 75 | }; |
| 76 | 76 | ||
| 77 | isp1704: isp1704 { | ||
| 78 | compatible = "nxp,isp1704"; | ||
| 79 | nxp,enable-gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>; | ||
| 80 | usb-phy = <&usb2_phy>; | ||
| 81 | }; | ||
| 77 | }; | 82 | }; |
| 78 | 83 | ||
| 79 | &omap3_pmx_core { | 84 | &omap3_pmx_core { |
| @@ -254,6 +259,61 @@ | |||
| 254 | }; | 259 | }; |
| 255 | }; | 260 | }; |
| 256 | 261 | ||
| 262 | &twl_keypad { | ||
| 263 | linux,keymap = < 0x00000010 /* KEY_Q */ | ||
| 264 | 0x00010018 /* KEY_O */ | ||
| 265 | 0x00020019 /* KEY_P */ | ||
| 266 | 0x00030033 /* KEY_COMMA */ | ||
| 267 | 0x0004000e /* KEY_BACKSPACE */ | ||
| 268 | 0x0006001e /* KEY_A */ | ||
| 269 | 0x0007001f /* KEY_S */ | ||
| 270 | |||
| 271 | 0x01000011 /* KEY_W */ | ||
| 272 | 0x01010020 /* KEY_D */ | ||
| 273 | 0x01020021 /* KEY_F */ | ||
| 274 | 0x01030022 /* KEY_G */ | ||
| 275 | 0x01040023 /* KEY_H */ | ||
| 276 | 0x01050024 /* KEY_J */ | ||
| 277 | 0x01060025 /* KEY_K */ | ||
| 278 | 0x01070026 /* KEY_L */ | ||
| 279 | |||
| 280 | 0x02000012 /* KEY_E */ | ||
| 281 | 0x02010034 /* KEY_DOT */ | ||
| 282 | 0x02020067 /* KEY_UP */ | ||
| 283 | 0x0203001c /* KEY_ENTER */ | ||
| 284 | 0x0205002c /* KEY_Z */ | ||
| 285 | 0x0206002d /* KEY_X */ | ||
| 286 | 0x0207002e /* KEY_C */ | ||
| 287 | 0x02080043 /* KEY_F9 */ | ||
| 288 | |||
| 289 | 0x03000013 /* KEY_R */ | ||
| 290 | 0x0301002f /* KEY_V */ | ||
| 291 | 0x03020030 /* KEY_B */ | ||
| 292 | 0x03030031 /* KEY_N */ | ||
| 293 | 0x03040032 /* KEY_M */ | ||
| 294 | 0x03050039 /* KEY_SPACE */ | ||
| 295 | 0x03060039 /* KEY_SPACE */ | ||
| 296 | 0x03070069 /* KEY_LEFT */ | ||
| 297 | |||
| 298 | 0x04000014 /* KEY_T */ | ||
| 299 | 0x0401006c /* KEY_DOWN */ | ||
| 300 | 0x0402006a /* KEY_RIGHT */ | ||
| 301 | 0x0404001d /* KEY_LEFTCTRL */ | ||
| 302 | 0x04050064 /* KEY_RIGHTALT */ | ||
| 303 | 0x0406002a /* KEY_LEFTSHIFT */ | ||
| 304 | 0x04080044 /* KEY_F10 */ | ||
| 305 | |||
| 306 | 0x05000015 /* KEY_Y */ | ||
| 307 | 0x05080057 /* KEY_F11 */ | ||
| 308 | |||
| 309 | 0x06000016 /* KEY_U */ | ||
| 310 | |||
| 311 | 0x07000017 /* KEY_I */ | ||
| 312 | 0x07010041 /* KEY_F7 */ | ||
| 313 | 0x07020042 /* KEY_F8 */ | ||
| 314 | >; | ||
| 315 | }; | ||
| 316 | |||
| 257 | &twl_gpio { | 317 | &twl_gpio { |
| 258 | ti,pullups = <0x0>; | 318 | ti,pullups = <0x0>; |
| 259 | ti,pulldowns = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */ | 319 | ti,pulldowns = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */ |
| @@ -291,6 +351,13 @@ | |||
| 291 | DVDD-supply = <&vio>; | 351 | DVDD-supply = <&vio>; |
| 292 | }; | 352 | }; |
| 293 | 353 | ||
| 354 | tsl2563: tsl2563@29 { | ||
| 355 | compatible = "amstaos,tsl2563"; | ||
| 356 | reg = <0x29>; | ||
| 357 | |||
| 358 | amstaos,cover-comp-gain = <16>; | ||
| 359 | }; | ||
| 360 | |||
| 294 | lp5523: lp5523@32 { | 361 | lp5523: lp5523@32 { |
| 295 | compatible = "national,lp5523"; | 362 | compatible = "national,lp5523"; |
| 296 | reg = <0x32>; | 363 | reg = <0x32>; |
| @@ -356,6 +423,29 @@ | |||
| 356 | compatible = "ti,bq27200"; | 423 | compatible = "ti,bq27200"; |
| 357 | reg = <0x55>; | 424 | reg = <0x55>; |
| 358 | }; | 425 | }; |
| 426 | |||
| 427 | tpa6130a2: tpa6130a2@60 { | ||
| 428 | compatible = "ti,tpa6130a2"; | ||
| 429 | reg = <0x60>; | ||
| 430 | |||
| 431 | Vdd-supply = <&vmmc2>; | ||
| 432 | |||
| 433 | power-gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; /* 98 */ | ||
| 434 | }; | ||
| 435 | |||
| 436 | bq24150a: bq24150a@6b { | ||
| 437 | compatible = "ti,bq24150a"; | ||
| 438 | reg = <0x6b>; | ||
| 439 | |||
| 440 | ti,current-limit = <100>; | ||
| 441 | ti,weak-battery-voltage = <3400>; | ||
| 442 | ti,battery-regulation-voltage = <4200>; | ||
| 443 | ti,charge-current = <650>; | ||
| 444 | ti,termination-current = <100>; | ||
| 445 | ti,resistor-sense = <68>; | ||
| 446 | |||
| 447 | ti,usb-charger-detection = <&isp1704>; | ||
| 448 | }; | ||
| 359 | }; | 449 | }; |
| 360 | 450 | ||
| 361 | &i2c3 { | 451 | &i2c3 { |
diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi index c37b1301115b..69ca7c45bca2 100644 --- a/arch/arm/boot/dts/omap3-overo.dtsi +++ b/arch/arm/boot/dts/omap3-overo.dtsi | |||
| @@ -33,3 +33,6 @@ | |||
| 33 | }; | 33 | }; |
| 34 | }; | 34 | }; |
| 35 | 35 | ||
| 36 | &mcbsp2 { | ||
| 37 | status = "okay"; | ||
| 38 | }; | ||
diff --git a/arch/arm/boot/dts/omap3-sb-t35.dtsi b/arch/arm/boot/dts/omap3-sb-t35.dtsi index b9a2fedce7ee..7909c51b05a5 100644 --- a/arch/arm/boot/dts/omap3-sb-t35.dtsi +++ b/arch/arm/boot/dts/omap3-sb-t35.dtsi | |||
| @@ -2,11 +2,36 @@ | |||
| 2 | * Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730 | 2 | * Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730 |
| 3 | */ | 3 | */ |
| 4 | 4 | ||
| 5 | / { | ||
| 6 | vddvario_sb_t35: regulator-vddvario-sb-t35 { | ||
| 7 | compatible = "regulator-fixed"; | ||
| 8 | regulator-name = "vddvario"; | ||
| 9 | regulator-always-on; | ||
| 10 | }; | ||
| 11 | |||
| 12 | vdd33a_sb_t35: regulator-vdd33a-sb-t35 { | ||
| 13 | compatible = "regulator-fixed"; | ||
| 14 | regulator-name = "vdd33a"; | ||
| 15 | regulator-always-on; | ||
| 16 | }; | ||
| 17 | }; | ||
| 18 | |||
| 19 | &omap3_pmx_core { | ||
| 20 | smsc2_pins: pinmux_smsc2_pins { | ||
| 21 | pinctrl-single,pins = < | ||
| 22 | OMAP3_CORE1_IOPAD(0x20b6, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs4.gpmc_ncs4 */ | ||
| 23 | OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_wait3.gpio_65 */ | ||
| 24 | >; | ||
| 25 | }; | ||
| 26 | }; | ||
| 27 | |||
| 5 | &gpmc { | 28 | &gpmc { |
| 6 | ranges = <4 0 0x2d000000 0x01000000>; | 29 | ranges = <4 0 0x2d000000 0x01000000>; |
| 7 | 30 | ||
| 8 | smsc2: ethernet@4,0 { | 31 | smsc2: ethernet@4,0 { |
| 9 | compatible = "smsc,lan9221", "smsc,lan9115"; | 32 | compatible = "smsc,lan9221", "smsc,lan9115"; |
| 33 | pinctrl-names = "default"; | ||
| 34 | pinctrl-0 = <&smsc2_pins>; | ||
| 10 | interrupt-parent = <&gpio3>; | 35 | interrupt-parent = <&gpio3>; |
| 11 | interrupts = <1 IRQ_TYPE_LEVEL_LOW>; | 36 | interrupts = <1 IRQ_TYPE_LEVEL_LOW>; |
| 12 | reg = <4 0 0xff>; | 37 | reg = <4 0 0xff>; |
| @@ -32,8 +57,8 @@ | |||
| 32 | gpmc,wr-access-ns = <186>; | 57 | gpmc,wr-access-ns = <186>; |
| 33 | gpmc,cycle2cycle-samecsen; | 58 | gpmc,cycle2cycle-samecsen; |
| 34 | gpmc,cycle2cycle-diffcsen; | 59 | gpmc,cycle2cycle-diffcsen; |
| 35 | vddvario-supply = <&vddvario>; | 60 | vddvario-supply = <&vddvario_sb_t35>; |
| 36 | vdd33a-supply = <&vdd33a>; | 61 | vdd33a-supply = <&vdd33a_sb_t35>; |
| 37 | reg-io-width = <4>; | 62 | reg-io-width = <4>; |
| 38 | smsc,save-mac-address; | 63 | smsc,save-mac-address; |
| 39 | }; | 64 | }; |
diff --git a/arch/arm/boot/dts/omap3-sbc-t3517.dts b/arch/arm/boot/dts/omap3-sbc-t3517.dts new file mode 100644 index 000000000000..024c9c6c682d --- /dev/null +++ b/arch/arm/boot/dts/omap3-sbc-t3517.dts | |||
| @@ -0,0 +1,43 @@ | |||
| 1 | /* | ||
| 2 | * Suppport for CompuLab SBC-T3517 with CM-T3517 | ||
| 3 | */ | ||
| 4 | |||
| 5 | #include "omap3-cm-t3517.dts" | ||
| 6 | #include "omap3-sb-t35.dtsi" | ||
| 7 | |||
| 8 | / { | ||
| 9 | model = "CompuLab SBC-T3517 with CM-T3517"; | ||
| 10 | compatible = "compulab,omap3-sbc-t3517", "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3"; | ||
| 11 | }; | ||
| 12 | |||
| 13 | &omap3_pmx_core { | ||
| 14 | pinctrl-names = "default"; | ||
| 15 | pinctrl-0 = < | ||
| 16 | &sb_t35_usb_hub_pins | ||
| 17 | &usb_hub_pins | ||
| 18 | >; | ||
| 19 | |||
| 20 | mmc1_aux_pins: pinmux_mmc1_aux_pins { | ||
| 21 | pinctrl-single,pins = < | ||
| 22 | OMAP3_CORE1_IOPAD(0x20c0, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_clk.gpio_59 */ | ||
| 23 | OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE4) /* uart2_cts.gpio_144 */ | ||
| 24 | >; | ||
| 25 | }; | ||
| 26 | |||
| 27 | sb_t35_usb_hub_pins: pinmux_sb_t35_usb_hub_pins { | ||
| 28 | pinctrl-single,pins = < | ||
| 29 | OMAP3_CORE1_IOPAD(0x21ec, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_98 - SB-T35 USB HUB RST */ | ||
| 30 | >; | ||
| 31 | }; | ||
| 32 | }; | ||
| 33 | |||
| 34 | &mmc1 { | ||
| 35 | pinctrl-names = "default"; | ||
| 36 | pinctrl-0 = < | ||
| 37 | &mmc1_pins | ||
| 38 | &mmc1_aux_pins | ||
| 39 | >; | ||
| 40 | |||
| 41 | wp-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio_59 */ | ||
| 42 | cd-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio_144 */ | ||
| 43 | }; | ||
diff --git a/arch/arm/boot/dts/omap3-sbc-t3530.dts b/arch/arm/boot/dts/omap3-sbc-t3530.dts new file mode 100644 index 000000000000..bbbeea6b1988 --- /dev/null +++ b/arch/arm/boot/dts/omap3-sbc-t3530.dts | |||
| @@ -0,0 +1,36 @@ | |||
| 1 | /* | ||
| 2 | * Suppport for CompuLab SBC-T3530 with CM-T3530 | ||
| 3 | */ | ||
| 4 | |||
| 5 | #include "omap3-cm-t3530.dts" | ||
| 6 | #include "omap3-sb-t35.dtsi" | ||
| 7 | |||
| 8 | / { | ||
| 9 | model = "CompuLab SBC-T3530 with CM-T3530"; | ||
| 10 | compatible = "compulab,omap3-sbc-t3530", "compulab,omap3-cm-t3530", "ti,omap34xx", "ti,omap3"; | ||
| 11 | }; | ||
| 12 | |||
| 13 | &omap3_pmx_core { | ||
| 14 | pinctrl-names = "default"; | ||
| 15 | pinctrl-0 = <&sb_t35_usb_hub_pins>; | ||
| 16 | |||
| 17 | sb_t35_usb_hub_pins: pinmux_sb_t35_usb_hub_pins { | ||
| 18 | pinctrl-single,pins = < | ||
| 19 | OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_167 - SB-T35 USB HUB RST */ | ||
| 20 | >; | ||
| 21 | }; | ||
| 22 | }; | ||
| 23 | |||
| 24 | /* | ||
| 25 | * The following ranges correspond to SMSC9x eth chips on CM-T3530 CoM and | ||
| 26 | * SB-T35 baseboard respectively. | ||
| 27 | * This setting includes both chips in SBC-T3530 board device tree. | ||
| 28 | */ | ||
| 29 | &gpmc { | ||
| 30 | ranges = <5 0 0x2c000000 0x01000000>, | ||
| 31 | <4 0 0x2d000000 0x01000000>; | ||
| 32 | }; | ||
| 33 | |||
| 34 | &mmc1 { | ||
| 35 | cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_HIGH>; | ||
| 36 | }; | ||
diff --git a/arch/arm/boot/dts/omap3-sbc-t3730.dts b/arch/arm/boot/dts/omap3-sbc-t3730.dts index c119bd545053..08e4a7086f22 100644 --- a/arch/arm/boot/dts/omap3-sbc-t3730.dts +++ b/arch/arm/boot/dts/omap3-sbc-t3730.dts | |||
| @@ -10,21 +10,18 @@ | |||
| 10 | compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3"; | 10 | compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3"; |
| 11 | }; | 11 | }; |
| 12 | 12 | ||
| 13 | &gpmc { | 13 | &omap3_pmx_core { |
| 14 | ranges = <5 0 0x2c000000 0x01000000>, | ||
| 15 | <4 0 0x2d000000 0x01000000>; | ||
| 16 | }; | ||
| 17 | |||
| 18 | &smsc2 { | ||
| 19 | pinctrl-names = "default"; | 14 | pinctrl-names = "default"; |
| 20 | pinctrl-0 = <&smsc2_pins>; | 15 | pinctrl-0 = <&sb_t35_usb_hub_pins>; |
| 21 | }; | ||
| 22 | 16 | ||
| 23 | &omap3_pmx_core { | 17 | sb_t35_usb_hub_pins: pinmux_sb_t35_usb_hub_pins { |
| 24 | smsc2_pins: pinmux_smsc2_pins { | ||
| 25 | pinctrl-single,pins = < | 18 | pinctrl-single,pins = < |
| 26 | 0x86 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs4.gpmc_ncs4 */ | 19 | OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_167 - SB-T35 USB HUB RST */ |
| 27 | 0xa2 (PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_wait3.gpio_65 */ | ||
| 28 | >; | 20 | >; |
| 29 | }; | 21 | }; |
| 30 | }; \ No newline at end of file | 22 | }; |
| 23 | |||
| 24 | &gpmc { | ||
| 25 | ranges = <5 0 0x2c000000 0x01000000>, | ||
| 26 | <4 0 0x2d000000 0x01000000>; | ||
| 27 | }; | ||
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index a5fc83b9c835..a089e6e00457 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi | |||
| @@ -35,6 +35,11 @@ | |||
| 35 | compatible = "arm,cortex-a8"; | 35 | compatible = "arm,cortex-a8"; |
| 36 | device_type = "cpu"; | 36 | device_type = "cpu"; |
| 37 | reg = <0x0>; | 37 | reg = <0x0>; |
| 38 | |||
| 39 | clocks = <&dpll1_ck>; | ||
| 40 | clock-names = "cpu"; | ||
| 41 | |||
| 42 | clock-latency = <300000>; /* From omap-cpufreq driver */ | ||
| 38 | }; | 43 | }; |
| 39 | }; | 44 | }; |
| 40 | 45 | ||
| @@ -411,10 +416,19 @@ | |||
| 411 | }; | 416 | }; |
| 412 | 417 | ||
| 413 | mmu_isp: mmu@480bd400 { | 418 | mmu_isp: mmu@480bd400 { |
| 414 | compatible = "ti,omap3-mmu-isp"; | 419 | compatible = "ti,omap2-iommu"; |
| 415 | ti,hwmods = "mmu_isp"; | ||
| 416 | reg = <0x480bd400 0x80>; | 420 | reg = <0x480bd400 0x80>; |
| 417 | interrupts = <8>; | 421 | interrupts = <24>; |
| 422 | ti,hwmods = "mmu_isp"; | ||
| 423 | ti,#tlb-entries = <8>; | ||
| 424 | }; | ||
| 425 | |||
| 426 | mmu_iva: mmu@5d000000 { | ||
| 427 | compatible = "ti,omap2-iommu"; | ||
| 428 | reg = <0x5d000000 0x80>; | ||
| 429 | interrupts = <28>; | ||
| 430 | ti,hwmods = "mmu_iva"; | ||
| 431 | status = "disabled"; | ||
| 418 | }; | 432 | }; |
| 419 | 433 | ||
| 420 | wdt2: wdt@48314000 { | 434 | wdt2: wdt@48314000 { |
| @@ -436,6 +450,7 @@ | |||
| 436 | dmas = <&sdma 31>, | 450 | dmas = <&sdma 31>, |
| 437 | <&sdma 32>; | 451 | <&sdma 32>; |
| 438 | dma-names = "tx", "rx"; | 452 | dma-names = "tx", "rx"; |
| 453 | status = "disabled"; | ||
| 439 | }; | 454 | }; |
| 440 | 455 | ||
| 441 | mcbsp2: mcbsp@49022000 { | 456 | mcbsp2: mcbsp@49022000 { |
| @@ -453,6 +468,7 @@ | |||
| 453 | dmas = <&sdma 33>, | 468 | dmas = <&sdma 33>, |
| 454 | <&sdma 34>; | 469 | <&sdma 34>; |
| 455 | dma-names = "tx", "rx"; | 470 | dma-names = "tx", "rx"; |
| 471 | status = "disabled"; | ||
| 456 | }; | 472 | }; |
| 457 | 473 | ||
| 458 | mcbsp3: mcbsp@49024000 { | 474 | mcbsp3: mcbsp@49024000 { |
| @@ -470,6 +486,7 @@ | |||
| 470 | dmas = <&sdma 17>, | 486 | dmas = <&sdma 17>, |
| 471 | <&sdma 18>; | 487 | <&sdma 18>; |
| 472 | dma-names = "tx", "rx"; | 488 | dma-names = "tx", "rx"; |
| 489 | status = "disabled"; | ||
| 473 | }; | 490 | }; |
| 474 | 491 | ||
| 475 | mcbsp4: mcbsp@49026000 { | 492 | mcbsp4: mcbsp@49026000 { |
| @@ -485,6 +502,7 @@ | |||
| 485 | dmas = <&sdma 19>, | 502 | dmas = <&sdma 19>, |
| 486 | <&sdma 20>; | 503 | <&sdma 20>; |
| 487 | dma-names = "tx", "rx"; | 504 | dma-names = "tx", "rx"; |
| 505 | status = "disabled"; | ||
| 488 | }; | 506 | }; |
| 489 | 507 | ||
| 490 | mcbsp5: mcbsp@48096000 { | 508 | mcbsp5: mcbsp@48096000 { |
| @@ -500,6 +518,7 @@ | |||
| 500 | dmas = <&sdma 21>, | 518 | dmas = <&sdma 21>, |
| 501 | <&sdma 22>; | 519 | <&sdma 22>; |
| 502 | dma-names = "tx", "rx"; | 520 | dma-names = "tx", "rx"; |
| 521 | status = "disabled"; | ||
| 503 | }; | 522 | }; |
| 504 | 523 | ||
| 505 | sham: sham@480c3000 { | 524 | sham: sham@480c3000 { |
| @@ -634,14 +653,14 @@ | |||
| 634 | ranges; | 653 | ranges; |
| 635 | 654 | ||
| 636 | usbhsohci: ohci@48064400 { | 655 | usbhsohci: ohci@48064400 { |
| 637 | compatible = "ti,ohci-omap3", "usb-ohci"; | 656 | compatible = "ti,ohci-omap3"; |
| 638 | reg = <0x48064400 0x400>; | 657 | reg = <0x48064400 0x400>; |
| 639 | interrupt-parent = <&intc>; | 658 | interrupt-parent = <&intc>; |
| 640 | interrupts = <76>; | 659 | interrupts = <76>; |
| 641 | }; | 660 | }; |
| 642 | 661 | ||
| 643 | usbhsehci: ehci@48064800 { | 662 | usbhsehci: ehci@48064800 { |
| 644 | compatible = "ti,ehci-omap", "usb-ehci"; | 663 | compatible = "ti,ehci-omap"; |
| 645 | reg = <0x48064800 0x400>; | 664 | reg = <0x48064800 0x400>; |
| 646 | interrupt-parent = <&intc>; | 665 | interrupt-parent = <&intc>; |
| 647 | interrupts = <77>; | 666 | interrupts = <77>; |
diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts index 281914ed0151..02f69f4a8fd3 100644 --- a/arch/arm/boot/dts/omap3430-sdp.dts +++ b/arch/arm/boot/dts/omap3430-sdp.dts | |||
| @@ -34,6 +34,10 @@ | |||
| 34 | &mmc1 { | 34 | &mmc1 { |
| 35 | vmmc-supply = <&vmmc1>; | 35 | vmmc-supply = <&vmmc1>; |
| 36 | vmmc_aux-supply = <&vsim>; | 36 | vmmc_aux-supply = <&vsim>; |
| 37 | /* | ||
| 38 | * S6-3 must be in ON position for 8 bit mode to function | ||
| 39 | * Else, use 4 bit mode | ||
| 40 | */ | ||
| 37 | bus-width = <8>; | 41 | bus-width = <8>; |
| 38 | }; | 42 | }; |
| 39 | 43 | ||
| @@ -103,9 +107,8 @@ | |||
| 103 | #address-cells = <1>; | 107 | #address-cells = <1>; |
| 104 | #size-cells = <1>; | 108 | #size-cells = <1>; |
| 105 | reg = <1 0 0x08000000>; | 109 | reg = <1 0 0x08000000>; |
| 110 | ti,nand-ecc-opt = "ham1"; | ||
| 106 | nand-bus-width = <8>; | 111 | nand-bus-width = <8>; |
| 107 | |||
| 108 | ti,nand-ecc-opt = "sw"; | ||
| 109 | gpmc,cs-on-ns = <0>; | 112 | gpmc,cs-on-ns = <0>; |
| 110 | gpmc,cs-rd-off-ns = <36>; | 113 | gpmc,cs-rd-off-ns = <36>; |
| 111 | gpmc,cs-wr-off-ns = <36>; | 114 | gpmc,cs-wr-off-ns = <36>; |
diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi index 02f6c7fabbec..6f31954636a1 100644 --- a/arch/arm/boot/dts/omap3430es1-clocks.dtsi +++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi | |||
| @@ -82,16 +82,16 @@ | |||
| 82 | ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; | 82 | ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; |
| 83 | }; | 83 | }; |
| 84 | 84 | ||
| 85 | ssi_ssr_fck_3430es1: ssi_ssr_fck_3430es1 { | 85 | ssi_ssr_fck: ssi_ssr_fck_3430es1 { |
| 86 | #clock-cells = <0>; | 86 | #clock-cells = <0>; |
| 87 | compatible = "ti,composite-clock"; | 87 | compatible = "ti,composite-clock"; |
| 88 | clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>; | 88 | clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>; |
| 89 | }; | 89 | }; |
| 90 | 90 | ||
| 91 | ssi_sst_fck_3430es1: ssi_sst_fck_3430es1 { | 91 | ssi_sst_fck: ssi_sst_fck_3430es1 { |
| 92 | #clock-cells = <0>; | 92 | #clock-cells = <0>; |
| 93 | compatible = "fixed-factor-clock"; | 93 | compatible = "fixed-factor-clock"; |
| 94 | clocks = <&ssi_ssr_fck_3430es1>; | 94 | clocks = <&ssi_ssr_fck>; |
| 95 | clock-mult = <1>; | 95 | clock-mult = <1>; |
| 96 | clock-div = <2>; | 96 | clock-div = <2>; |
| 97 | }; | 97 | }; |
| @@ -120,7 +120,7 @@ | |||
| 120 | clock-div = <1>; | 120 | clock-div = <1>; |
| 121 | }; | 121 | }; |
| 122 | 122 | ||
| 123 | ssi_ick_3430es1: ssi_ick_3430es1 { | 123 | ssi_ick: ssi_ick_3430es1 { |
| 124 | #clock-cells = <0>; | 124 | #clock-cells = <0>; |
| 125 | compatible = "ti,omap3-no-wait-interface-clock"; | 125 | compatible = "ti,omap3-no-wait-interface-clock"; |
| 126 | clocks = <&ssi_l4_ick>; | 126 | clocks = <&ssi_l4_ick>; |
| @@ -203,6 +203,6 @@ | |||
| 203 | <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, | 203 | <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, |
| 204 | <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, | 204 | <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, |
| 205 | <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, | 205 | <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, |
| 206 | <&fshostusb_fck>, <&fac_ick>, <&ssi_ick_3430es1>; | 206 | <&fshostusb_fck>, <&fac_ick>, <&ssi_ick>; |
| 207 | }; | 207 | }; |
| 208 | }; | 208 | }; |
diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi index 8ed475dd63c9..877318c28364 100644 --- a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi | |||
| @@ -25,16 +25,16 @@ | |||
| 25 | ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; | 25 | ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; |
| 26 | }; | 26 | }; |
| 27 | 27 | ||
| 28 | ssi_ssr_fck_3430es2: ssi_ssr_fck_3430es2 { | 28 | ssi_ssr_fck: ssi_ssr_fck_3430es2 { |
| 29 | #clock-cells = <0>; | 29 | #clock-cells = <0>; |
| 30 | compatible = "ti,composite-clock"; | 30 | compatible = "ti,composite-clock"; |
| 31 | clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>; | 31 | clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>; |
| 32 | }; | 32 | }; |
| 33 | 33 | ||
| 34 | ssi_sst_fck_3430es2: ssi_sst_fck_3430es2 { | 34 | ssi_sst_fck: ssi_sst_fck_3430es2 { |
| 35 | #clock-cells = <0>; | 35 | #clock-cells = <0>; |
| 36 | compatible = "fixed-factor-clock"; | 36 | compatible = "fixed-factor-clock"; |
| 37 | clocks = <&ssi_ssr_fck_3430es2>; | 37 | clocks = <&ssi_ssr_fck>; |
| 38 | clock-mult = <1>; | 38 | clock-mult = <1>; |
| 39 | clock-div = <2>; | 39 | clock-div = <2>; |
| 40 | }; | 40 | }; |
| @@ -55,7 +55,7 @@ | |||
| 55 | clock-div = <1>; | 55 | clock-div = <1>; |
| 56 | }; | 56 | }; |
| 57 | 57 | ||
| 58 | ssi_ick_3430es2: ssi_ick_3430es2 { | 58 | ssi_ick: ssi_ick_3430es2 { |
| 59 | #clock-cells = <0>; | 59 | #clock-cells = <0>; |
| 60 | compatible = "ti,omap3-ssi-interface-clock"; | 60 | compatible = "ti,omap3-ssi-interface-clock"; |
| 61 | clocks = <&ssi_l4_ick>; | 61 | clocks = <&ssi_l4_ick>; |
| @@ -193,6 +193,6 @@ | |||
| 193 | <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, | 193 | <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, |
| 194 | <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, | 194 | <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, |
| 195 | <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, | 195 | <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, |
| 196 | <&ssi_ick_3430es2>; | 196 | <&ssi_ick>; |
| 197 | }; | 197 | }; |
| 198 | }; | 198 | }; |
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi index 7e8dee9175d6..ba077cd95e4e 100644 --- a/arch/arm/boot/dts/omap36xx.dtsi +++ b/arch/arm/boot/dts/omap36xx.dtsi | |||
| @@ -39,6 +39,26 @@ | |||
| 39 | clock-frequency = <48000000>; | 39 | clock-frequency = <48000000>; |
| 40 | }; | 40 | }; |
| 41 | 41 | ||
| 42 | abb_mpu_iva: regulator-abb-mpu { | ||
| 43 | compatible = "ti,abb-v1"; | ||
| 44 | regulator-name = "abb_mpu_iva"; | ||
| 45 | #address-cell = <0>; | ||
| 46 | #size-cells = <0>; | ||
| 47 | reg = <0x483072f0 0x8>, <0x48306818 0x4>; | ||
| 48 | reg-names = "base-address", "int-address"; | ||
| 49 | ti,tranxdone-status-mask = <0x4000000>; | ||
| 50 | clocks = <&sys_ck>; | ||
| 51 | ti,settling-time = <30>; | ||
| 52 | ti,clock-cycles = <8>; | ||
| 53 | ti,abb_info = < | ||
| 54 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | ||
| 55 | 1012500 0 0 0 0 0 | ||
| 56 | 1200000 0 0 0 0 0 | ||
| 57 | 1325000 0 0 0 0 0 | ||
| 58 | 1375000 1 0 0 0 0 | ||
| 59 | >; | ||
| 60 | }; | ||
| 61 | |||
| 42 | omap3_pmx_core2: pinmux@480025a0 { | 62 | omap3_pmx_core2: pinmux@480025a0 { |
| 43 | compatible = "ti,omap3-padconf", "pinctrl-single"; | 63 | compatible = "ti,omap3-padconf", "pinctrl-single"; |
| 44 | reg = <0x480025a0 0x5c>; | 64 | reg = <0x480025a0 0x5c>; |
diff --git a/arch/arm/boot/dts/omap4-duovero-parlor.dts b/arch/arm/boot/dts/omap4-duovero-parlor.dts new file mode 100644 index 000000000000..96f51d870812 --- /dev/null +++ b/arch/arm/boot/dts/omap4-duovero-parlor.dts | |||
| @@ -0,0 +1,146 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | /dts-v1/; | ||
| 9 | |||
| 10 | #include "omap4-duovero.dtsi" | ||
| 11 | |||
| 12 | #include <dt-bindings/input/input.h> | ||
| 13 | |||
| 14 | / { | ||
| 15 | model = "OMAP4430 Gumstix Duovero on Parlor"; | ||
| 16 | compatible = "gumstix,omap4-duovero-parlor", "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4"; | ||
| 17 | |||
| 18 | leds { | ||
| 19 | compatible = "gpio-leds"; | ||
| 20 | led0 { | ||
| 21 | label = "duovero:blue:led0"; | ||
| 22 | gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio_122 */ | ||
| 23 | linux,default-trigger = "heartbeat"; | ||
| 24 | }; | ||
| 25 | }; | ||
| 26 | |||
| 27 | gpio_keys { | ||
| 28 | compatible = "gpio-keys"; | ||
| 29 | #address-cells = <1>; | ||
| 30 | #size-cells = <0>; | ||
| 31 | button0@121 { | ||
| 32 | label = "button0"; | ||
| 33 | linux,code = <BTN_0>; | ||
| 34 | gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; /* gpio_121 */ | ||
| 35 | gpio-key,wakeup; | ||
| 36 | }; | ||
| 37 | }; | ||
| 38 | }; | ||
| 39 | |||
| 40 | &omap4_pmx_core { | ||
| 41 | pinctrl-0 = < | ||
| 42 | &led_pins | ||
| 43 | &button_pins | ||
| 44 | &smsc_pins | ||
| 45 | >; | ||
| 46 | |||
| 47 | led_pins: pinmux_led_pins { | ||
| 48 | pinctrl-single,pins = < | ||
| 49 | 0xd6 (PIN_OUTPUT | MUX_MODE3) /* abe_dmic_din3.gpio_122 */ | ||
| 50 | >; | ||
| 51 | }; | ||
| 52 | |||
| 53 | button_pins: pinmux_button_pins { | ||
| 54 | pinctrl-single,pins = < | ||
| 55 | 0xd4 (PIN_INPUT_PULLUP | MUX_MODE3) /* abe_dmic_din2.gpio_121 */ | ||
| 56 | >; | ||
| 57 | }; | ||
| 58 | |||
| 59 | i2c2_pins: pinmux_i2c2_pins { | ||
| 60 | pinctrl-single,pins = < | ||
| 61 | 0xe6 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ | ||
| 62 | 0xe8 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ | ||
| 63 | >; | ||
| 64 | }; | ||
| 65 | |||
| 66 | i2c3_pins: pinmux_i2c3_pins { | ||
| 67 | pinctrl-single,pins = < | ||
| 68 | 0xea (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ | ||
| 69 | 0xec (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ | ||
| 70 | >; | ||
| 71 | }; | ||
| 72 | |||
| 73 | smsc_pins: pinmux_smsc_pins { | ||
| 74 | pinctrl-single,pins = < | ||
| 75 | 0x28 (PIN_INPUT | MUX_MODE3) /* gpmc_a20.gpio_44: IRQ */ | ||
| 76 | 0x2a (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a21.gpio_45: nReset */ | ||
| 77 | 0x30 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48: amdix enabled */ | ||
| 78 | >; | ||
| 79 | }; | ||
| 80 | }; | ||
| 81 | |||
| 82 | &i2c2 { | ||
| 83 | pinctrl-names = "default"; | ||
| 84 | pinctrl-0 = <&i2c2_pins>; | ||
| 85 | |||
| 86 | clock-frequency = <400000>; | ||
| 87 | }; | ||
| 88 | |||
| 89 | &i2c3 { | ||
| 90 | pinctrl-names = "default"; | ||
| 91 | pinctrl-0 = <&i2c3_pins>; | ||
| 92 | |||
| 93 | clock-frequency = <100000>; | ||
| 94 | |||
| 95 | /* optional 1K EEPROM with revision information */ | ||
| 96 | eeprom@51 { | ||
| 97 | compatible = "atmel,24c01"; | ||
| 98 | reg = <0x51>; | ||
| 99 | pagesize = <8>; | ||
| 100 | }; | ||
| 101 | }; | ||
| 102 | |||
| 103 | &mmc3 { | ||
| 104 | status = "disabled"; | ||
| 105 | }; | ||
| 106 | |||
| 107 | #include "omap-gpmc-smsc911x.dtsi" | ||
| 108 | |||
| 109 | &gpmc { | ||
| 110 | ranges = <5 0 0x2c000000 0x1000000>; /* CS5 */ | ||
| 111 | |||
| 112 | ethernet@gpmc { | ||
| 113 | reg = <5 0 0xff>; | ||
| 114 | interrupt-parent = <&gpio2>; | ||
| 115 | interrupts = <12 IRQ_TYPE_LEVEL_LOW>; /* gpio_44 */ | ||
| 116 | |||
| 117 | phy-mode = "mii"; | ||
| 118 | |||
| 119 | gpmc,cs-on-ns = <10>; | ||
| 120 | gpmc,cs-rd-off-ns = <50>; | ||
| 121 | gpmc,cs-wr-off-ns = <50>; | ||
| 122 | gpmc,adv-on-ns = <0>; | ||
| 123 | gpmc,adv-rd-off-ns = <10>; | ||
| 124 | gpmc,adv-wr-off-ns = <10>; | ||
| 125 | gpmc,oe-on-ns = <15>; | ||
| 126 | gpmc,oe-off-ns = <50>; | ||
| 127 | gpmc,we-on-ns = <15>; | ||
| 128 | gpmc,we-off-ns = <50>; | ||
| 129 | gpmc,rd-cycle-ns = <50>; | ||
| 130 | gpmc,wr-cycle-ns = <50>; | ||
| 131 | gpmc,access-ns = <50>; | ||
| 132 | gpmc,page-burst-access-ns = <0>; | ||
| 133 | gpmc,bus-turnaround-ns = <35>; | ||
| 134 | gpmc,cycle2cycle-delay-ns = <35>; | ||
| 135 | gpmc,wr-data-mux-bus-ns = <35>; | ||
| 136 | gpmc,wr-access-ns = <50>; | ||
| 137 | |||
| 138 | gpmc,mux-add-data = <2>; | ||
| 139 | gpmc,sync-read; | ||
| 140 | gpmc,sync-write; | ||
| 141 | gpmc,clk-activation-ns = <5>; | ||
| 142 | gpmc,sync-clk-ps = <20000>; | ||
| 143 | }; | ||
| 144 | }; | ||
| 145 | |||
| 146 | |||
diff --git a/arch/arm/boot/dts/omap4-duovero.dtsi b/arch/arm/boot/dts/omap4-duovero.dtsi new file mode 100644 index 000000000000..a514791154eb --- /dev/null +++ b/arch/arm/boot/dts/omap4-duovero.dtsi | |||
| @@ -0,0 +1,252 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include "omap443x.dtsi" | ||
| 10 | |||
| 11 | / { | ||
| 12 | model = "Gumstix Duovero"; | ||
| 13 | compatible = "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4"; | ||
| 14 | |||
| 15 | memory { | ||
| 16 | device_type = "memory"; | ||
| 17 | reg = <0x80000000 0x40000000>; /* 1 GB */ | ||
| 18 | }; | ||
| 19 | |||
| 20 | sound { | ||
| 21 | compatible = "ti,abe-twl6040"; | ||
| 22 | ti,model = "DuoVero"; | ||
| 23 | |||
| 24 | ti,mclk-freq = <38400000>; | ||
| 25 | |||
| 26 | ti,mcpdm = <&mcpdm>; | ||
| 27 | |||
| 28 | ti,twl6040 = <&twl6040>; | ||
| 29 | |||
| 30 | /* Audio routing */ | ||
| 31 | ti,audio-routing = | ||
| 32 | "Headset Stereophone", "HSOL", | ||
| 33 | "Headset Stereophone", "HSOR", | ||
| 34 | "HSMIC", "Headset Mic", | ||
| 35 | "Headset Mic", "Headset Mic Bias"; | ||
| 36 | }; | ||
| 37 | |||
| 38 | /* HS USB Host PHY on PORT 1 */ | ||
| 39 | hsusb1_phy: hsusb1_phy { | ||
| 40 | compatible = "usb-nop-xceiv"; | ||
| 41 | reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */ | ||
| 42 | |||
| 43 | pinctrl-names = "default"; | ||
| 44 | pinctrl-0 = <&hsusb1phy_pins>; | ||
| 45 | |||
| 46 | clocks = <&auxclk3_ck>; | ||
| 47 | clock-names = "main_clk"; | ||
| 48 | clock-frequency = <19200000>; | ||
| 49 | }; | ||
| 50 | |||
| 51 | /* regulator for w2cbw0015 on sdio5 */ | ||
| 52 | w2cbw0015_vmmc: w2cbw0015_vmmc { | ||
| 53 | pinctrl-names = "default"; | ||
| 54 | pinctrl-0 = <&w2cbw0015_pins>; | ||
| 55 | compatible = "regulator-fixed"; | ||
| 56 | regulator-name = "w2cbw0015"; | ||
| 57 | regulator-min-microvolt = <3000000>; | ||
| 58 | regulator-max-microvolt = <3000000>; | ||
| 59 | gpio = <&gpio2 11 GPIO_ACTIVE_LOW>; /* gpio_43 */ | ||
| 60 | startup-delay-us = <70000>; | ||
| 61 | enable-active-high; | ||
| 62 | regulator-boot-on; | ||
| 63 | }; | ||
| 64 | }; | ||
| 65 | |||
| 66 | &omap4_pmx_core { | ||
| 67 | pinctrl-names = "default"; | ||
| 68 | pinctrl-0 = < | ||
| 69 | &twl6040_pins | ||
| 70 | &mcpdm_pins | ||
| 71 | &mcbsp1_pins | ||
| 72 | &hsusbb1_pins | ||
| 73 | >; | ||
| 74 | |||
| 75 | twl6040_pins: pinmux_twl6040_pins { | ||
| 76 | pinctrl-single,pins = < | ||
| 77 | 0x126 (PIN_OUTPUT | MUX_MODE3) /* usbb2_ulpitll_nxt.gpio_160 */ | ||
| 78 | 0x160 (PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ | ||
| 79 | >; | ||
| 80 | }; | ||
| 81 | |||
| 82 | mcpdm_pins: pinmux_mcpdm_pins { | ||
| 83 | pinctrl-single,pins = < | ||
| 84 | 0xc6 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_ul_data.abe_pdm_ul_data */ | ||
| 85 | 0xc8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_dl_data.abe_pdm_dl_data */ | ||
| 86 | 0xca (PIN_INPUT_PULLUP | MUX_MODE0) /* abe_pdm_frame.abe_pdm_frame */ | ||
| 87 | 0xcc (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_lb_clk.abe_pdm_lb_clk */ | ||
| 88 | 0xce (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ | ||
| 89 | >; | ||
| 90 | }; | ||
| 91 | |||
| 92 | mcbsp1_pins: pinmux_mcbsp1_pins { | ||
| 93 | pinctrl-single,pins = < | ||
| 94 | 0xbe (PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ | ||
| 95 | 0xc0 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */ | ||
| 96 | 0xc2 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */ | ||
| 97 | 0xc4 (PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */ | ||
| 98 | >; | ||
| 99 | }; | ||
| 100 | |||
| 101 | hsusbb1_pins: pinmux_hsusbb1_pins { | ||
| 102 | pinctrl-single,pins = < | ||
| 103 | 0x82 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */ | ||
| 104 | 0x84 (PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */ | ||
| 105 | 0x86 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */ | ||
| 106 | 0x88 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */ | ||
| 107 | 0x8a (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */ | ||
| 108 | 0x8c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */ | ||
| 109 | 0x8e (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */ | ||
| 110 | 0x90 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */ | ||
| 111 | 0x92 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */ | ||
| 112 | 0x94 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */ | ||
| 113 | 0x96 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */ | ||
| 114 | 0x98 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */ | ||
| 115 | >; | ||
| 116 | }; | ||
| 117 | |||
| 118 | hsusb1phy_pins: pinmux_hsusb1phy_pins { | ||
| 119 | pinctrl-single,pins = < | ||
| 120 | 0x4c (PIN_OUTPUT | MUX_MODE3) /* gpmc_wait1.gpio_62 */ | ||
| 121 | >; | ||
| 122 | }; | ||
| 123 | |||
| 124 | w2cbw0015_pins: pinmux_w2cbw0015_pins { | ||
| 125 | pinctrl-single,pins = < | ||
| 126 | 0x26 (PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */ | ||
| 127 | 0x3a (PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ | ||
| 128 | >; | ||
| 129 | }; | ||
| 130 | |||
| 131 | i2c1_pins: pinmux_i2c1_pins { | ||
| 132 | pinctrl-single,pins = < | ||
| 133 | 0xe2 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ | ||
| 134 | 0xe4 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ | ||
| 135 | >; | ||
| 136 | }; | ||
| 137 | |||
| 138 | i2c4_pins: pinmux_i2c4_pins { | ||
| 139 | pinctrl-single,pins = < | ||
| 140 | 0xee (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ | ||
| 141 | 0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ | ||
| 142 | >; | ||
| 143 | }; | ||
| 144 | |||
| 145 | mmc1_pins: pinmux_mmc1_pins { | ||
| 146 | pinctrl-single,pins = < | ||
| 147 | 0xa2 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */ | ||
| 148 | 0xa4 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc1_cmd */ | ||
| 149 | 0xa6 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc1_dat0 */ | ||
| 150 | 0xa8 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1 */ | ||
| 151 | 0xaa (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2 */ | ||
| 152 | 0xac (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */ | ||
| 153 | >; | ||
| 154 | }; | ||
| 155 | |||
| 156 | mmc5_pins: pinmux_mmc5_pins { | ||
| 157 | pinctrl-single,pins = < | ||
| 158 | 0x108 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk */ | ||
| 159 | 0x10a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc5_cmd */ | ||
| 160 | 0x10c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc5_dat0 */ | ||
| 161 | 0x10e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1 */ | ||
| 162 | 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2 */ | ||
| 163 | 0x112 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3 */ | ||
| 164 | >; | ||
| 165 | }; | ||
| 166 | }; | ||
| 167 | |||
| 168 | /* PMIC */ | ||
| 169 | &i2c1 { | ||
| 170 | pinctrl-names = "default"; | ||
| 171 | pinctrl-0 = <&i2c1_pins>; | ||
| 172 | |||
| 173 | clock-frequency = <400000>; | ||
| 174 | |||
| 175 | twl: twl@48 { | ||
| 176 | reg = <0x48>; | ||
| 177 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */ | ||
| 178 | interrupt-parent = <&gic>; | ||
| 179 | }; | ||
| 180 | |||
| 181 | twl6040: twl@4b { | ||
| 182 | compatible = "ti,twl6040"; | ||
| 183 | reg = <0x4b>; | ||
| 184 | interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */ | ||
| 185 | interrupt-parent = <&gic>; | ||
| 186 | ti,audpwron-gpio = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* gpio_160 */ | ||
| 187 | |||
| 188 | vio-supply = <&v1v8>; | ||
| 189 | v2v1-supply = <&v2v1>; | ||
| 190 | enable-active-high; | ||
| 191 | }; | ||
| 192 | }; | ||
| 193 | |||
| 194 | #include "twl6030.dtsi" | ||
| 195 | #include "twl6030_omap4.dtsi" | ||
| 196 | |||
| 197 | /* on-board bluetooth / WiFi module */ | ||
| 198 | &i2c4 { | ||
| 199 | pinctrl-names = "default"; | ||
| 200 | pinctrl-0 = <&i2c4_pins>; | ||
| 201 | |||
| 202 | clock-frequency = <400000>; | ||
| 203 | }; | ||
| 204 | |||
| 205 | &mmc1 { | ||
| 206 | pinctrl-names = "default"; | ||
| 207 | pinctrl-0 = <&mmc1_pins>; | ||
| 208 | |||
| 209 | vmmc-supply = <&vmmc>; | ||
| 210 | ti,bus-width = <4>; | ||
| 211 | ti,non-removable; /* FIXME: use PMIC_MMC detect */ | ||
| 212 | }; | ||
| 213 | |||
| 214 | &mmc2 { | ||
| 215 | status = "disabled"; | ||
| 216 | }; | ||
| 217 | |||
| 218 | /* mmc3 is available to the expansion board */ | ||
| 219 | |||
| 220 | &mmc4 { | ||
| 221 | status = "disabled"; | ||
| 222 | }; | ||
| 223 | |||
| 224 | /* on-board WiFi module */ | ||
| 225 | &mmc5 { | ||
| 226 | pinctrl-names = "default"; | ||
| 227 | pinctrl-0 = <&mmc5_pins>; | ||
| 228 | |||
| 229 | vmmc-supply = <&w2cbw0015_vmmc>; | ||
| 230 | ti,bus-width = <4>; | ||
| 231 | ti,non-removable; | ||
| 232 | cap-power-off-card; | ||
| 233 | }; | ||
| 234 | |||
| 235 | &twl_usb_comparator { | ||
| 236 | usb-supply = <&vusb>; | ||
| 237 | }; | ||
| 238 | |||
| 239 | &usb_otg_hs { | ||
| 240 | interface-type = <1>; | ||
| 241 | mode = <3>; | ||
| 242 | power = <50>; | ||
| 243 | }; | ||
| 244 | |||
| 245 | &usbhshost { | ||
| 246 | port1-mode = "ehci-phy"; | ||
| 247 | }; | ||
| 248 | |||
| 249 | &usbhsehci { | ||
| 250 | phys = <&hsusb1_phy>; | ||
| 251 | }; | ||
| 252 | |||
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 88c6a05cab41..cbc45cfc44e9 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi | |||
| @@ -83,12 +83,8 @@ | |||
| 83 | compatible = "usb-nop-xceiv"; | 83 | compatible = "usb-nop-xceiv"; |
| 84 | reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */ | 84 | reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */ |
| 85 | vcc-supply = <&hsusb1_power>; | 85 | vcc-supply = <&hsusb1_power>; |
| 86 | /** | 86 | clocks = <&auxclk3_ck>; |
| 87 | * FIXME: | 87 | clock-names = "main_clk"; |
| 88 | * put the right clock phandle here when available | ||
| 89 | * clocks = <&auxclk3>; | ||
| 90 | * clock-names = "main_clk"; | ||
| 91 | */ | ||
| 92 | clock-frequency = <19200000>; | 88 | clock-frequency = <19200000>; |
| 93 | }; | 89 | }; |
| 94 | 90 | ||
| @@ -109,9 +105,6 @@ | |||
| 109 | &omap4_pmx_core { | 105 | &omap4_pmx_core { |
| 110 | pinctrl-names = "default"; | 106 | pinctrl-names = "default"; |
| 111 | pinctrl-0 = < | 107 | pinctrl-0 = < |
| 112 | &twl6040_pins | ||
| 113 | &mcpdm_pins | ||
| 114 | &mcbsp1_pins | ||
| 115 | &dss_dpi_pins | 108 | &dss_dpi_pins |
| 116 | &tfp410_pins | 109 | &tfp410_pins |
| 117 | &dss_hdmi_pins | 110 | &dss_hdmi_pins |
| @@ -300,6 +293,10 @@ | |||
| 300 | twl6040: twl@4b { | 293 | twl6040: twl@4b { |
| 301 | compatible = "ti,twl6040"; | 294 | compatible = "ti,twl6040"; |
| 302 | reg = <0x4b>; | 295 | reg = <0x4b>; |
| 296 | |||
| 297 | pinctrl-names = "default"; | ||
| 298 | pinctrl-0 = <&twl6040_pins>; | ||
| 299 | |||
| 303 | /* IRQ# = 119 */ | 300 | /* IRQ# = 119 */ |
| 304 | interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */ | 301 | interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */ |
| 305 | interrupt-parent = <&gic>; | 302 | interrupt-parent = <&gic>; |
| @@ -380,16 +377,16 @@ | |||
| 380 | device-handle = <&elpida_ECB240ABACN>; | 377 | device-handle = <&elpida_ECB240ABACN>; |
| 381 | }; | 378 | }; |
| 382 | 379 | ||
| 383 | &mcbsp2 { | 380 | &mcbsp1 { |
| 384 | status = "disabled"; | 381 | pinctrl-names = "default"; |
| 385 | }; | 382 | pinctrl-0 = <&mcbsp1_pins>; |
| 386 | 383 | status = "okay"; | |
| 387 | &mcbsp3 { | ||
| 388 | status = "disabled"; | ||
| 389 | }; | 384 | }; |
| 390 | 385 | ||
| 391 | &dmic { | 386 | &mcpdm { |
| 392 | status = "disabled"; | 387 | pinctrl-names = "default"; |
| 388 | pinctrl-0 = <&mcpdm_pins>; | ||
| 389 | status = "okay"; | ||
| 393 | }; | 390 | }; |
| 394 | 391 | ||
| 395 | &twl_usb_comparator { | 392 | &twl_usb_comparator { |
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index dbc81fb6ef03..9bbbbec1d63d 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts | |||
| @@ -158,11 +158,6 @@ | |||
| 158 | &omap4_pmx_core { | 158 | &omap4_pmx_core { |
| 159 | pinctrl-names = "default"; | 159 | pinctrl-names = "default"; |
| 160 | pinctrl-0 = < | 160 | pinctrl-0 = < |
| 161 | &twl6040_pins | ||
| 162 | &mcpdm_pins | ||
| 163 | &dmic_pins | ||
| 164 | &mcbsp1_pins | ||
| 165 | &mcbsp2_pins | ||
| 166 | &dss_hdmi_pins | 161 | &dss_hdmi_pins |
| 167 | &tpd12s015_pins | 162 | &tpd12s015_pins |
| 168 | >; | 163 | >; |
| @@ -326,6 +321,10 @@ | |||
| 326 | twl6040: twl@4b { | 321 | twl6040: twl@4b { |
| 327 | compatible = "ti,twl6040"; | 322 | compatible = "ti,twl6040"; |
| 328 | reg = <0x4b>; | 323 | reg = <0x4b>; |
| 324 | |||
| 325 | pinctrl-names = "default"; | ||
| 326 | pinctrl-0 = <&twl6040_pins>; | ||
| 327 | |||
| 329 | /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ | 328 | /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ |
| 330 | interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */ | 329 | interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */ |
| 331 | interrupt-parent = <&gic>; | 330 | interrupt-parent = <&gic>; |
| @@ -537,8 +536,28 @@ | |||
| 537 | pinctrl-0 = <&uart4_pins>; | 536 | pinctrl-0 = <&uart4_pins>; |
| 538 | }; | 537 | }; |
| 539 | 538 | ||
| 540 | &mcbsp3 { | 539 | &mcbsp1 { |
| 541 | status = "disabled"; | 540 | pinctrl-names = "default"; |
| 541 | pinctrl-0 = <&mcbsp1_pins>; | ||
| 542 | status = "okay"; | ||
| 543 | }; | ||
| 544 | |||
| 545 | &mcbsp2 { | ||
| 546 | pinctrl-names = "default"; | ||
| 547 | pinctrl-0 = <&mcbsp2_pins>; | ||
| 548 | status = "okay"; | ||
| 549 | }; | ||
| 550 | |||
| 551 | &dmic { | ||
| 552 | pinctrl-names = "default"; | ||
| 553 | pinctrl-0 = <&dmic_pins>; | ||
| 554 | status = "okay"; | ||
| 555 | }; | ||
| 556 | |||
| 557 | &mcpdm { | ||
| 558 | pinctrl-names = "default"; | ||
| 559 | pinctrl-0 = <&mcpdm_pins>; | ||
| 560 | status = "okay"; | ||
| 542 | }; | 561 | }; |
| 543 | 562 | ||
| 544 | &twl_usb_comparator { | 563 | &twl_usb_comparator { |
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index d3f8a6e8ca20..3dfec86c1dc9 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi | |||
| @@ -36,6 +36,11 @@ | |||
| 36 | device_type = "cpu"; | 36 | device_type = "cpu"; |
| 37 | next-level-cache = <&L2>; | 37 | next-level-cache = <&L2>; |
| 38 | reg = <0x0>; | 38 | reg = <0x0>; |
| 39 | |||
| 40 | clocks = <&dpll_mpu_ck>; | ||
| 41 | clock-names = "cpu"; | ||
| 42 | |||
| 43 | clock-latency = <300000>; /* From omap-cpufreq driver */ | ||
| 39 | }; | 44 | }; |
| 40 | cpu@1 { | 45 | cpu@1 { |
| 41 | compatible = "arm,cortex-a9"; | 46 | compatible = "arm,cortex-a9"; |
| @@ -313,6 +318,7 @@ | |||
| 313 | compatible = "ti,omap4-hwspinlock"; | 318 | compatible = "ti,omap4-hwspinlock"; |
| 314 | reg = <0x4a0f6000 0x1000>; | 319 | reg = <0x4a0f6000 0x1000>; |
| 315 | ti,hwmods = "spinlock"; | 320 | ti,hwmods = "spinlock"; |
| 321 | #hwlock-cells = <1>; | ||
| 316 | }; | 322 | }; |
| 317 | 323 | ||
| 318 | i2c1: i2c@48070000 { | 324 | i2c1: i2c@48070000 { |
| @@ -461,6 +467,21 @@ | |||
| 461 | dma-names = "tx", "rx"; | 467 | dma-names = "tx", "rx"; |
| 462 | }; | 468 | }; |
| 463 | 469 | ||
| 470 | mmu_dsp: mmu@4a066000 { | ||
| 471 | compatible = "ti,omap4-iommu"; | ||
| 472 | reg = <0x4a066000 0x100>; | ||
| 473 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | ||
| 474 | ti,hwmods = "mmu_dsp"; | ||
| 475 | }; | ||
| 476 | |||
| 477 | mmu_ipu: mmu@55082000 { | ||
| 478 | compatible = "ti,omap4-iommu"; | ||
| 479 | reg = <0x55082000 0x100>; | ||
| 480 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; | ||
| 481 | ti,hwmods = "mmu_ipu"; | ||
| 482 | ti,iommu-bus-err-back; | ||
| 483 | }; | ||
| 484 | |||
| 464 | wdt2: wdt@4a314000 { | 485 | wdt2: wdt@4a314000 { |
| 465 | compatible = "ti,omap4-wdt", "ti,omap3-wdt"; | 486 | compatible = "ti,omap4-wdt", "ti,omap3-wdt"; |
| 466 | reg = <0x4a314000 0x80>; | 487 | reg = <0x4a314000 0x80>; |
| @@ -478,6 +499,7 @@ | |||
| 478 | dmas = <&sdma 65>, | 499 | dmas = <&sdma 65>, |
| 479 | <&sdma 66>; | 500 | <&sdma 66>; |
| 480 | dma-names = "up_link", "dn_link"; | 501 | dma-names = "up_link", "dn_link"; |
| 502 | status = "disabled"; | ||
| 481 | }; | 503 | }; |
| 482 | 504 | ||
| 483 | dmic: dmic@4012e000 { | 505 | dmic: dmic@4012e000 { |
| @@ -489,6 +511,7 @@ | |||
| 489 | ti,hwmods = "dmic"; | 511 | ti,hwmods = "dmic"; |
| 490 | dmas = <&sdma 67>; | 512 | dmas = <&sdma 67>; |
| 491 | dma-names = "up_link"; | 513 | dma-names = "up_link"; |
| 514 | status = "disabled"; | ||
| 492 | }; | 515 | }; |
| 493 | 516 | ||
| 494 | mcbsp1: mcbsp@40122000 { | 517 | mcbsp1: mcbsp@40122000 { |
| @@ -503,6 +526,7 @@ | |||
| 503 | dmas = <&sdma 33>, | 526 | dmas = <&sdma 33>, |
| 504 | <&sdma 34>; | 527 | <&sdma 34>; |
| 505 | dma-names = "tx", "rx"; | 528 | dma-names = "tx", "rx"; |
| 529 | status = "disabled"; | ||
| 506 | }; | 530 | }; |
| 507 | 531 | ||
| 508 | mcbsp2: mcbsp@40124000 { | 532 | mcbsp2: mcbsp@40124000 { |
| @@ -517,6 +541,7 @@ | |||
| 517 | dmas = <&sdma 17>, | 541 | dmas = <&sdma 17>, |
| 518 | <&sdma 18>; | 542 | <&sdma 18>; |
| 519 | dma-names = "tx", "rx"; | 543 | dma-names = "tx", "rx"; |
| 544 | status = "disabled"; | ||
| 520 | }; | 545 | }; |
| 521 | 546 | ||
| 522 | mcbsp3: mcbsp@40126000 { | 547 | mcbsp3: mcbsp@40126000 { |
| @@ -531,6 +556,7 @@ | |||
| 531 | dmas = <&sdma 19>, | 556 | dmas = <&sdma 19>, |
| 532 | <&sdma 20>; | 557 | <&sdma 20>; |
| 533 | dma-names = "tx", "rx"; | 558 | dma-names = "tx", "rx"; |
| 559 | status = "disabled"; | ||
| 534 | }; | 560 | }; |
| 535 | 561 | ||
| 536 | mcbsp4: mcbsp@48096000 { | 562 | mcbsp4: mcbsp@48096000 { |
| @@ -544,6 +570,7 @@ | |||
| 544 | dmas = <&sdma 31>, | 570 | dmas = <&sdma 31>, |
| 545 | <&sdma 32>; | 571 | <&sdma 32>; |
| 546 | dma-names = "tx", "rx"; | 572 | dma-names = "tx", "rx"; |
| 573 | status = "disabled"; | ||
| 547 | }; | 574 | }; |
| 548 | 575 | ||
| 549 | keypad: keypad@4a31c000 { | 576 | keypad: keypad@4a31c000 { |
| @@ -554,6 +581,13 @@ | |||
| 554 | ti,hwmods = "kbd"; | 581 | ti,hwmods = "kbd"; |
| 555 | }; | 582 | }; |
| 556 | 583 | ||
| 584 | dmm@4e000000 { | ||
| 585 | compatible = "ti,omap4-dmm"; | ||
| 586 | reg = <0x4e000000 0x800>; | ||
| 587 | interrupts = <0 113 0x4>; | ||
| 588 | ti,hwmods = "dmm"; | ||
| 589 | }; | ||
| 590 | |||
| 557 | emif1: emif@4c000000 { | 591 | emif1: emif@4c000000 { |
| 558 | compatible = "ti,emif-4d"; | 592 | compatible = "ti,emif-4d"; |
| 559 | reg = <0x4c000000 0x100>; | 593 | reg = <0x4c000000 0x100>; |
| @@ -699,14 +733,14 @@ | |||
| 699 | ranges; | 733 | ranges; |
| 700 | 734 | ||
| 701 | usbhsohci: ohci@4a064800 { | 735 | usbhsohci: ohci@4a064800 { |
| 702 | compatible = "ti,ohci-omap3", "usb-ohci"; | 736 | compatible = "ti,ohci-omap3"; |
| 703 | reg = <0x4a064800 0x400>; | 737 | reg = <0x4a064800 0x400>; |
| 704 | interrupt-parent = <&gic>; | 738 | interrupt-parent = <&gic>; |
| 705 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; | 739 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
| 706 | }; | 740 | }; |
| 707 | 741 | ||
| 708 | usbhsehci: ehci@4a064c00 { | 742 | usbhsehci: ehci@4a064c00 { |
| 709 | compatible = "ti,ehci-omap", "usb-ehci"; | 743 | compatible = "ti,ehci-omap"; |
| 710 | reg = <0x4a064c00 0x400>; | 744 | reg = <0x4a064c00 0x400>; |
| 711 | interrupt-parent = <&gic>; | 745 | interrupt-parent = <&gic>; |
| 712 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | 746 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -757,6 +791,32 @@ | |||
| 757 | dmas = <&sdma 117>, <&sdma 116>; | 791 | dmas = <&sdma 117>, <&sdma 116>; |
| 758 | dma-names = "tx", "rx"; | 792 | dma-names = "tx", "rx"; |
| 759 | }; | 793 | }; |
| 794 | |||
| 795 | abb_mpu: regulator-abb-mpu { | ||
| 796 | compatible = "ti,abb-v2"; | ||
| 797 | regulator-name = "abb_mpu"; | ||
| 798 | #address-cells = <0>; | ||
| 799 | #size-cells = <0>; | ||
| 800 | ti,tranxdone-status-mask = <0x80>; | ||
| 801 | clocks = <&sys_clkin_ck>; | ||
| 802 | ti,settling-time = <50>; | ||
| 803 | ti,clock-cycles = <16>; | ||
| 804 | |||
| 805 | status = "disabled"; | ||
| 806 | }; | ||
| 807 | |||
| 808 | abb_iva: regulator-abb-iva { | ||
| 809 | compatible = "ti,abb-v2"; | ||
| 810 | regulator-name = "abb_iva"; | ||
| 811 | #address-cells = <0>; | ||
| 812 | #size-cells = <0>; | ||
| 813 | ti,tranxdone-status-mask = <0x80000000>; | ||
| 814 | clocks = <&sys_clkin_ck>; | ||
| 815 | ti,settling-time = <50>; | ||
| 816 | ti,clock-cycles = <16>; | ||
| 817 | |||
| 818 | status = "disabled"; | ||
| 819 | }; | ||
| 760 | }; | 820 | }; |
| 761 | }; | 821 | }; |
| 762 | 822 | ||
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi index 8c1cfad30d60..0adfa1d1ef20 100644 --- a/arch/arm/boot/dts/omap443x.dtsi +++ b/arch/arm/boot/dts/omap443x.dtsi | |||
| @@ -43,6 +43,32 @@ | |||
| 43 | #thermal-sensor-cells = <0>; | 43 | #thermal-sensor-cells = <0>; |
| 44 | }; | 44 | }; |
| 45 | }; | 45 | }; |
| 46 | |||
| 47 | ocp { | ||
| 48 | abb_mpu: regulator-abb-mpu { | ||
| 49 | status = "okay"; | ||
| 50 | |||
| 51 | reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>; | ||
| 52 | reg-names = "base-address", "int-address"; | ||
| 53 | |||
| 54 | ti,abb_info = < | ||
| 55 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | ||
| 56 | 1025000 0 0 0 0 0 | ||
| 57 | 1200000 0 0 0 0 0 | ||
| 58 | 1313000 0 0 0 0 0 | ||
| 59 | 1375000 1 0 0 0 0 | ||
| 60 | 1389000 1 0 0 0 0 | ||
| 61 | >; | ||
| 62 | }; | ||
| 63 | |||
| 64 | /* Default unused, just provide register info for record */ | ||
| 65 | abb_iva: regulator-abb-iva { | ||
| 66 | reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>; | ||
| 67 | reg-names = "base-address", "int-address"; | ||
| 68 | }; | ||
| 69 | |||
| 70 | }; | ||
| 71 | |||
| 46 | }; | 72 | }; |
| 47 | 73 | ||
| 48 | /include/ "omap443x-clocks.dtsi" | 74 | /include/ "omap443x-clocks.dtsi" |
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi index 6b32f520741a..194f9ef0a009 100644 --- a/arch/arm/boot/dts/omap4460.dtsi +++ b/arch/arm/boot/dts/omap4460.dtsi | |||
| @@ -50,7 +50,44 @@ | |||
| 50 | 50 | ||
| 51 | #thermal-sensor-cells = <0>; | 51 | #thermal-sensor-cells = <0>; |
| 52 | }; | 52 | }; |
| 53 | |||
| 54 | abb_mpu: regulator-abb-mpu { | ||
| 55 | status = "okay"; | ||
| 56 | |||
| 57 | reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>, | ||
| 58 | <0x4A002268 0x4>; | ||
| 59 | reg-names = "base-address", "int-address", | ||
| 60 | "efuse-address"; | ||
| 61 | |||
| 62 | ti,abb_info = < | ||
| 63 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | ||
| 64 | 1025000 0 0 0 0 0 | ||
| 65 | 1200000 0 0 0 0 0 | ||
| 66 | 1313000 0 0 0x100000 0x40000 0 | ||
| 67 | 1375000 1 0 0 0 0 | ||
| 68 | 1389000 1 0 0 0 0 | ||
| 69 | >; | ||
| 70 | }; | ||
| 71 | |||
| 72 | abb_iva: regulator-abb-iva { | ||
| 73 | status = "okay"; | ||
| 74 | |||
| 75 | reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>, | ||
| 76 | <0x4A002268 0x4>; | ||
| 77 | reg-names = "base-address", "int-address", | ||
| 78 | "efuse-address"; | ||
| 79 | |||
| 80 | ti,abb_info = < | ||
| 81 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | ||
| 82 | 950000 0 0 0 0 0 | ||
| 83 | 1140000 0 0 0 0 0 | ||
| 84 | 1291000 0 0 0x200000 0 0 | ||
| 85 | 1375000 1 0 0 0 0 | ||
| 86 | 1376000 1 0 0 0 0 | ||
| 87 | >; | ||
| 88 | }; | ||
| 53 | }; | 89 | }; |
| 90 | |||
| 54 | }; | 91 | }; |
| 55 | 92 | ||
| 56 | /include/ "omap446x-clocks.dtsi" | 93 | /include/ "omap446x-clocks.dtsi" |
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index 002fa70180a5..3b99ec25b748 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts | |||
| @@ -31,12 +31,8 @@ | |||
| 31 | hsusb2_phy: hsusb2_phy { | 31 | hsusb2_phy: hsusb2_phy { |
| 32 | compatible = "usb-nop-xceiv"; | 32 | compatible = "usb-nop-xceiv"; |
| 33 | reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; /* gpio3_80 HUB_NRESET */ | 33 | reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; /* gpio3_80 HUB_NRESET */ |
| 34 | /** | 34 | clocks = <&auxclk1_ck>; |
| 35 | * FIXME | 35 | clock-names = "main_clk"; |
| 36 | * Put the right clock phandle here when available | ||
| 37 | * clocks = <&auxclk1>; | ||
| 38 | * clock-names = "main_clk"; | ||
| 39 | */ | ||
| 40 | clock-frequency = <19200000>; | 36 | clock-frequency = <19200000>; |
| 41 | }; | 37 | }; |
| 42 | 38 | ||
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index a72813a9663e..757f0b9343c2 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi | |||
| @@ -49,6 +49,12 @@ | |||
| 49 | 1000000 1060000 | 49 | 1000000 1060000 |
| 50 | 1500000 1250000 | 50 | 1500000 1250000 |
| 51 | >; | 51 | >; |
| 52 | |||
| 53 | clocks = <&dpll_mpu_ck>; | ||
| 54 | clock-names = "cpu"; | ||
| 55 | |||
| 56 | clock-latency = <300000>; /* From omap-cpufreq driver */ | ||
| 57 | |||
| 52 | /* cooling options */ | 58 | /* cooling options */ |
| 53 | cooling-min-level = <0>; | 59 | cooling-min-level = <0>; |
| 54 | cooling-max-level = <2>; | 60 | cooling-max-level = <2>; |
| @@ -353,6 +359,7 @@ | |||
| 353 | compatible = "ti,omap4-hwspinlock"; | 359 | compatible = "ti,omap4-hwspinlock"; |
| 354 | reg = <0x4a0f6000 0x1000>; | 360 | reg = <0x4a0f6000 0x1000>; |
| 355 | ti,hwmods = "spinlock"; | 361 | ti,hwmods = "spinlock"; |
| 362 | #hwlock-cells = <1>; | ||
| 356 | }; | 363 | }; |
| 357 | 364 | ||
| 358 | mcspi1: spi@48098000 { | 365 | mcspi1: spi@48098000 { |
| @@ -513,6 +520,21 @@ | |||
| 513 | dma-names = "tx", "rx"; | 520 | dma-names = "tx", "rx"; |
| 514 | }; | 521 | }; |
| 515 | 522 | ||
| 523 | mmu_dsp: mmu@4a066000 { | ||
| 524 | compatible = "ti,omap4-iommu"; | ||
| 525 | reg = <0x4a066000 0x100>; | ||
| 526 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | ||
| 527 | ti,hwmods = "mmu_dsp"; | ||
| 528 | }; | ||
| 529 | |||
| 530 | mmu_ipu: mmu@55082000 { | ||
| 531 | compatible = "ti,omap4-iommu"; | ||
| 532 | reg = <0x55082000 0x100>; | ||
| 533 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; | ||
| 534 | ti,hwmods = "mmu_ipu"; | ||
| 535 | ti,iommu-bus-err-back; | ||
| 536 | }; | ||
| 537 | |||
| 516 | keypad: keypad@4ae1c000 { | 538 | keypad: keypad@4ae1c000 { |
| 517 | compatible = "ti,omap4-keypad"; | 539 | compatible = "ti,omap4-keypad"; |
| 518 | reg = <0x4ae1c000 0x400>; | 540 | reg = <0x4ae1c000 0x400>; |
| @@ -529,6 +551,7 @@ | |||
| 529 | dmas = <&sdma 65>, | 551 | dmas = <&sdma 65>, |
| 530 | <&sdma 66>; | 552 | <&sdma 66>; |
| 531 | dma-names = "up_link", "dn_link"; | 553 | dma-names = "up_link", "dn_link"; |
| 554 | status = "disabled"; | ||
| 532 | }; | 555 | }; |
| 533 | 556 | ||
| 534 | dmic: dmic@4012e000 { | 557 | dmic: dmic@4012e000 { |
| @@ -540,6 +563,7 @@ | |||
| 540 | ti,hwmods = "dmic"; | 563 | ti,hwmods = "dmic"; |
| 541 | dmas = <&sdma 67>; | 564 | dmas = <&sdma 67>; |
| 542 | dma-names = "up_link"; | 565 | dma-names = "up_link"; |
| 566 | status = "disabled"; | ||
| 543 | }; | 567 | }; |
| 544 | 568 | ||
| 545 | mcbsp1: mcbsp@40122000 { | 569 | mcbsp1: mcbsp@40122000 { |
| @@ -554,6 +578,7 @@ | |||
| 554 | dmas = <&sdma 33>, | 578 | dmas = <&sdma 33>, |
| 555 | <&sdma 34>; | 579 | <&sdma 34>; |
| 556 | dma-names = "tx", "rx"; | 580 | dma-names = "tx", "rx"; |
| 581 | status = "disabled"; | ||
| 557 | }; | 582 | }; |
| 558 | 583 | ||
| 559 | mcbsp2: mcbsp@40124000 { | 584 | mcbsp2: mcbsp@40124000 { |
| @@ -568,6 +593,7 @@ | |||
| 568 | dmas = <&sdma 17>, | 593 | dmas = <&sdma 17>, |
| 569 | <&sdma 18>; | 594 | <&sdma 18>; |
| 570 | dma-names = "tx", "rx"; | 595 | dma-names = "tx", "rx"; |
| 596 | status = "disabled"; | ||
| 571 | }; | 597 | }; |
| 572 | 598 | ||
| 573 | mcbsp3: mcbsp@40126000 { | 599 | mcbsp3: mcbsp@40126000 { |
| @@ -582,6 +608,7 @@ | |||
| 582 | dmas = <&sdma 19>, | 608 | dmas = <&sdma 19>, |
| 583 | <&sdma 20>; | 609 | <&sdma 20>; |
| 584 | dma-names = "tx", "rx"; | 610 | dma-names = "tx", "rx"; |
| 611 | status = "disabled"; | ||
| 585 | }; | 612 | }; |
| 586 | 613 | ||
| 587 | timer1: timer@4ae18000 { | 614 | timer1: timer@4ae18000 { |
| @@ -683,6 +710,13 @@ | |||
| 683 | ti,hwmods = "wd_timer2"; | 710 | ti,hwmods = "wd_timer2"; |
| 684 | }; | 711 | }; |
| 685 | 712 | ||
| 713 | dmm@4e000000 { | ||
| 714 | compatible = "ti,omap5-dmm"; | ||
| 715 | reg = <0x4e000000 0x800>; | ||
| 716 | interrupts = <0 113 0x4>; | ||
| 717 | ti,hwmods = "dmm"; | ||
| 718 | }; | ||
| 719 | |||
| 686 | emif1: emif@4c000000 { | 720 | emif1: emif@4c000000 { |
| 687 | compatible = "ti,emif-4d5"; | 721 | compatible = "ti,emif-4d5"; |
| 688 | ti,hwmods = "emif1"; | 722 | ti,hwmods = "emif1"; |
| @@ -732,7 +766,8 @@ | |||
| 732 | compatible = "snps,dwc3"; | 766 | compatible = "snps,dwc3"; |
| 733 | reg = <0x4a030000 0x10000>; | 767 | reg = <0x4a030000 0x10000>; |
| 734 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; | 768 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
| 735 | usb-phy = <&usb2_phy>, <&usb3_phy>; | 769 | phys = <&usb2_phy>, <&usb3_phy>; |
| 770 | phy-names = "usb2-phy", "usb3-phy"; | ||
| 736 | dr_mode = "peripheral"; | 771 | dr_mode = "peripheral"; |
| 737 | tx-fifo-resize; | 772 | tx-fifo-resize; |
| 738 | }; | 773 | }; |
| @@ -749,6 +784,7 @@ | |||
| 749 | compatible = "ti,omap-usb2"; | 784 | compatible = "ti,omap-usb2"; |
| 750 | reg = <0x4a084000 0x7c>; | 785 | reg = <0x4a084000 0x7c>; |
| 751 | ctrl-module = <&omap_control_usb2phy>; | 786 | ctrl-module = <&omap_control_usb2phy>; |
| 787 | #phy-cells = <0>; | ||
| 752 | }; | 788 | }; |
| 753 | 789 | ||
| 754 | usb3_phy: usb3phy@4a084400 { | 790 | usb3_phy: usb3phy@4a084400 { |
| @@ -758,6 +794,7 @@ | |||
| 758 | <0x4a084c00 0x40>; | 794 | <0x4a084c00 0x40>; |
| 759 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; | 795 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; |
| 760 | ctrl-module = <&omap_control_usb3phy>; | 796 | ctrl-module = <&omap_control_usb3phy>; |
| 797 | #phy-cells = <0>; | ||
| 761 | }; | 798 | }; |
| 762 | }; | 799 | }; |
| 763 | 800 | ||
| @@ -777,14 +814,14 @@ | |||
| 777 | ranges; | 814 | ranges; |
| 778 | 815 | ||
| 779 | usbhsohci: ohci@4a064800 { | 816 | usbhsohci: ohci@4a064800 { |
| 780 | compatible = "ti,ohci-omap3", "usb-ohci"; | 817 | compatible = "ti,ohci-omap3"; |
| 781 | reg = <0x4a064800 0x400>; | 818 | reg = <0x4a064800 0x400>; |
| 782 | interrupt-parent = <&gic>; | 819 | interrupt-parent = <&gic>; |
| 783 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; | 820 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
| 784 | }; | 821 | }; |
| 785 | 822 | ||
| 786 | usbhsehci: ehci@4a064c00 { | 823 | usbhsehci: ehci@4a064c00 { |
| 787 | compatible = "ti,ehci-omap", "usb-ehci"; | 824 | compatible = "ti,ehci-omap"; |
| 788 | reg = <0x4a064c00 0x400>; | 825 | reg = <0x4a064c00 0x400>; |
| 789 | interrupt-parent = <&gic>; | 826 | interrupt-parent = <&gic>; |
| 790 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | 827 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts index 68a72f5507b9..169bad90dac9 100644 --- a/arch/arm/boot/dts/qcom-msm8660-surf.dts +++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts | |||
| @@ -1,63 +1,6 @@ | |||
| 1 | /dts-v1/; | 1 | #include "qcom-msm8660.dtsi" |
| 2 | |||
| 3 | /include/ "skeleton.dtsi" | ||
| 4 | |||
| 5 | #include <dt-bindings/clock/qcom,gcc-msm8660.h> | ||
| 6 | 2 | ||
| 7 | / { | 3 | / { |
| 8 | model = "Qualcomm MSM8660 SURF"; | 4 | model = "Qualcomm MSM8660 SURF"; |
| 9 | compatible = "qcom,msm8660-surf", "qcom,msm8660"; | 5 | compatible = "qcom,msm8660-surf", "qcom,msm8660"; |
| 10 | interrupt-parent = <&intc>; | ||
| 11 | |||
| 12 | intc: interrupt-controller@2080000 { | ||
| 13 | compatible = "qcom,msm-8660-qgic"; | ||
| 14 | interrupt-controller; | ||
| 15 | #interrupt-cells = <3>; | ||
| 16 | reg = < 0x02080000 0x1000 >, | ||
| 17 | < 0x02081000 0x1000 >; | ||
| 18 | }; | ||
| 19 | |||
| 20 | timer@2000000 { | ||
| 21 | compatible = "qcom,scss-timer", "qcom,msm-timer"; | ||
| 22 | interrupts = <1 0 0x301>, | ||
| 23 | <1 1 0x301>, | ||
| 24 | <1 2 0x301>; | ||
| 25 | reg = <0x02000000 0x100>; | ||
| 26 | clock-frequency = <27000000>, | ||
| 27 | <32768>; | ||
| 28 | cpu-offset = <0x40000>; | ||
| 29 | }; | ||
| 30 | |||
| 31 | msmgpio: gpio@800000 { | ||
| 32 | compatible = "qcom,msm-gpio"; | ||
| 33 | reg = <0x00800000 0x4000>; | ||
| 34 | gpio-controller; | ||
| 35 | #gpio-cells = <2>; | ||
| 36 | ngpio = <173>; | ||
| 37 | interrupts = <0 16 0x4>; | ||
| 38 | interrupt-controller; | ||
| 39 | #interrupt-cells = <2>; | ||
| 40 | }; | ||
| 41 | |||
| 42 | gcc: clock-controller@900000 { | ||
| 43 | compatible = "qcom,gcc-msm8660"; | ||
| 44 | #clock-cells = <1>; | ||
| 45 | #reset-cells = <1>; | ||
| 46 | reg = <0x900000 0x4000>; | ||
| 47 | }; | ||
| 48 | |||
| 49 | serial@19c40000 { | ||
| 50 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; | ||
| 51 | reg = <0x19c40000 0x1000>, | ||
| 52 | <0x19c00000 0x1000>; | ||
| 53 | interrupts = <0 195 0x0>; | ||
| 54 | clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; | ||
| 55 | clock-names = "core", "iface"; | ||
| 56 | }; | ||
| 57 | |||
| 58 | qcom,ssbi@500000 { | ||
| 59 | compatible = "qcom,ssbi"; | ||
| 60 | reg = <0x500000 0x1000>; | ||
| 61 | qcom,controller-type = "pmic-arbiter"; | ||
| 62 | }; | ||
| 63 | }; | 6 | }; |
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi new file mode 100644 index 000000000000..c52a9e964a44 --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi | |||
| @@ -0,0 +1,87 @@ | |||
| 1 | /dts-v1/; | ||
| 2 | |||
| 3 | /include/ "skeleton.dtsi" | ||
| 4 | |||
| 5 | #include <dt-bindings/clock/qcom,gcc-msm8660.h> | ||
| 6 | |||
| 7 | / { | ||
| 8 | model = "Qualcomm MSM8660"; | ||
| 9 | compatible = "qcom,msm8660"; | ||
| 10 | interrupt-parent = <&intc>; | ||
| 11 | |||
| 12 | cpus { | ||
| 13 | #address-cells = <1>; | ||
| 14 | #size-cells = <0>; | ||
| 15 | compatible = "qcom,scorpion"; | ||
| 16 | enable-method = "qcom,gcc-msm8660"; | ||
| 17 | |||
| 18 | cpu@0 { | ||
| 19 | device_type = "cpu"; | ||
| 20 | reg = <0>; | ||
| 21 | next-level-cache = <&L2>; | ||
| 22 | }; | ||
| 23 | |||
| 24 | cpu@1 { | ||
| 25 | device_type = "cpu"; | ||
| 26 | reg = <1>; | ||
| 27 | next-level-cache = <&L2>; | ||
| 28 | }; | ||
| 29 | |||
| 30 | L2: l2-cache { | ||
| 31 | compatible = "cache"; | ||
| 32 | cache-level = <2>; | ||
| 33 | }; | ||
| 34 | }; | ||
| 35 | |||
| 36 | intc: interrupt-controller@2080000 { | ||
| 37 | compatible = "qcom,msm-8660-qgic"; | ||
| 38 | interrupt-controller; | ||
| 39 | #interrupt-cells = <3>; | ||
| 40 | reg = < 0x02080000 0x1000 >, | ||
| 41 | < 0x02081000 0x1000 >; | ||
| 42 | }; | ||
| 43 | |||
| 44 | timer@2000000 { | ||
| 45 | compatible = "qcom,scss-timer", "qcom,msm-timer"; | ||
| 46 | interrupts = <1 0 0x301>, | ||
| 47 | <1 1 0x301>, | ||
| 48 | <1 2 0x301>; | ||
| 49 | reg = <0x02000000 0x100>; | ||
| 50 | clock-frequency = <27000000>, | ||
| 51 | <32768>; | ||
| 52 | cpu-offset = <0x40000>; | ||
| 53 | }; | ||
| 54 | |||
| 55 | msmgpio: gpio@800000 { | ||
| 56 | compatible = "qcom,msm-gpio"; | ||
| 57 | reg = <0x00800000 0x4000>; | ||
| 58 | gpio-controller; | ||
| 59 | #gpio-cells = <2>; | ||
| 60 | ngpio = <173>; | ||
| 61 | interrupts = <0 16 0x4>; | ||
| 62 | interrupt-controller; | ||
| 63 | #interrupt-cells = <2>; | ||
| 64 | }; | ||
| 65 | |||
| 66 | gcc: clock-controller@900000 { | ||
| 67 | compatible = "qcom,gcc-msm8660"; | ||
| 68 | #clock-cells = <1>; | ||
| 69 | #reset-cells = <1>; | ||
| 70 | reg = <0x900000 0x4000>; | ||
| 71 | }; | ||
| 72 | |||
| 73 | serial@19c40000 { | ||
| 74 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; | ||
| 75 | reg = <0x19c40000 0x1000>, | ||
| 76 | <0x19c00000 0x1000>; | ||
| 77 | interrupts = <0 195 0x0>; | ||
| 78 | clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; | ||
| 79 | clock-names = "core", "iface"; | ||
| 80 | }; | ||
| 81 | |||
| 82 | qcom,ssbi@500000 { | ||
| 83 | compatible = "qcom,ssbi"; | ||
| 84 | reg = <0x500000 0x1000>; | ||
| 85 | qcom,controller-type = "pmic-arbiter"; | ||
| 86 | }; | ||
| 87 | }; | ||
diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts index 7c30de4fa302..a58fb88315f6 100644 --- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts +++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts | |||
| @@ -1,70 +1,6 @@ | |||
| 1 | /dts-v1/; | 1 | #include "qcom-msm8960.dtsi" |
| 2 | |||
| 3 | /include/ "skeleton.dtsi" | ||
| 4 | |||
| 5 | #include <dt-bindings/clock/qcom,gcc-msm8960.h> | ||
| 6 | 2 | ||
| 7 | / { | 3 | / { |
| 8 | model = "Qualcomm MSM8960 CDP"; | 4 | model = "Qualcomm MSM8960 CDP"; |
| 9 | compatible = "qcom,msm8960-cdp", "qcom,msm8960"; | 5 | compatible = "qcom,msm8960-cdp", "qcom,msm8960"; |
| 10 | interrupt-parent = <&intc>; | ||
| 11 | |||
| 12 | intc: interrupt-controller@2000000 { | ||
| 13 | compatible = "qcom,msm-qgic2"; | ||
| 14 | interrupt-controller; | ||
| 15 | #interrupt-cells = <3>; | ||
| 16 | reg = < 0x02000000 0x1000 >, | ||
| 17 | < 0x02002000 0x1000 >; | ||
| 18 | }; | ||
| 19 | |||
| 20 | timer@200a000 { | ||
| 21 | compatible = "qcom,kpss-timer", "qcom,msm-timer"; | ||
| 22 | interrupts = <1 1 0x301>, | ||
| 23 | <1 2 0x301>, | ||
| 24 | <1 3 0x301>; | ||
| 25 | reg = <0x0200a000 0x100>; | ||
| 26 | clock-frequency = <27000000>, | ||
| 27 | <32768>; | ||
| 28 | cpu-offset = <0x80000>; | ||
| 29 | }; | ||
| 30 | |||
| 31 | msmgpio: gpio@800000 { | ||
| 32 | compatible = "qcom,msm-gpio"; | ||
| 33 | gpio-controller; | ||
| 34 | #gpio-cells = <2>; | ||
| 35 | ngpio = <150>; | ||
| 36 | interrupts = <0 16 0x4>; | ||
| 37 | interrupt-controller; | ||
| 38 | #interrupt-cells = <2>; | ||
| 39 | reg = <0x800000 0x4000>; | ||
| 40 | }; | ||
| 41 | |||
| 42 | gcc: clock-controller@900000 { | ||
| 43 | compatible = "qcom,gcc-msm8960"; | ||
| 44 | #clock-cells = <1>; | ||
| 45 | #reset-cells = <1>; | ||
| 46 | reg = <0x900000 0x4000>; | ||
| 47 | }; | ||
| 48 | |||
| 49 | clock-controller@4000000 { | ||
| 50 | compatible = "qcom,mmcc-msm8960"; | ||
| 51 | reg = <0x4000000 0x1000>; | ||
| 52 | #clock-cells = <1>; | ||
| 53 | #reset-cells = <1>; | ||
| 54 | }; | ||
| 55 | |||
| 56 | serial@16440000 { | ||
| 57 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; | ||
| 58 | reg = <0x16440000 0x1000>, | ||
| 59 | <0x16400000 0x1000>; | ||
| 60 | interrupts = <0 154 0x0>; | ||
| 61 | clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; | ||
| 62 | clock-names = "core", "iface"; | ||
| 63 | }; | ||
| 64 | |||
| 65 | qcom,ssbi@500000 { | ||
| 66 | compatible = "qcom,ssbi"; | ||
| 67 | reg = <0x500000 0x1000>; | ||
| 68 | qcom,controller-type = "pmic-arbiter"; | ||
| 69 | }; | ||
| 70 | }; | 6 | }; |
diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi new file mode 100644 index 000000000000..ecfba7254205 --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi | |||
| @@ -0,0 +1,129 @@ | |||
| 1 | /dts-v1/; | ||
| 2 | |||
| 3 | /include/ "skeleton.dtsi" | ||
| 4 | |||
| 5 | #include <dt-bindings/clock/qcom,gcc-msm8960.h> | ||
| 6 | |||
| 7 | / { | ||
| 8 | model = "Qualcomm MSM8960"; | ||
| 9 | compatible = "qcom,msm8960"; | ||
| 10 | interrupt-parent = <&intc>; | ||
| 11 | |||
| 12 | cpus { | ||
| 13 | #address-cells = <1>; | ||
| 14 | #size-cells = <0>; | ||
| 15 | interrupts = <1 14 0x304>; | ||
| 16 | compatible = "qcom,krait"; | ||
| 17 | enable-method = "qcom,kpss-acc-v1"; | ||
| 18 | |||
| 19 | cpu@0 { | ||
| 20 | device_type = "cpu"; | ||
| 21 | reg = <0>; | ||
| 22 | next-level-cache = <&L2>; | ||
| 23 | qcom,acc = <&acc0>; | ||
| 24 | qcom,saw = <&saw0>; | ||
| 25 | }; | ||
| 26 | |||
| 27 | cpu@1 { | ||
| 28 | device_type = "cpu"; | ||
| 29 | reg = <1>; | ||
| 30 | next-level-cache = <&L2>; | ||
| 31 | qcom,acc = <&acc1>; | ||
| 32 | qcom,saw = <&saw1>; | ||
| 33 | }; | ||
| 34 | |||
| 35 | L2: l2-cache { | ||
| 36 | compatible = "cache"; | ||
| 37 | cache-level = <2>; | ||
| 38 | interrupts = <0 2 0x4>; | ||
| 39 | }; | ||
| 40 | }; | ||
| 41 | |||
| 42 | intc: interrupt-controller@2000000 { | ||
| 43 | compatible = "qcom,msm-qgic2"; | ||
| 44 | interrupt-controller; | ||
| 45 | #interrupt-cells = <3>; | ||
| 46 | reg = < 0x02000000 0x1000 >, | ||
| 47 | < 0x02002000 0x1000 >; | ||
| 48 | }; | ||
| 49 | |||
| 50 | timer@200a000 { | ||
| 51 | compatible = "qcom,kpss-timer", "qcom,msm-timer"; | ||
| 52 | interrupts = <1 1 0x301>, | ||
| 53 | <1 2 0x301>, | ||
| 54 | <1 3 0x301>; | ||
| 55 | reg = <0x0200a000 0x100>; | ||
| 56 | clock-frequency = <27000000>, | ||
| 57 | <32768>; | ||
| 58 | cpu-offset = <0x80000>; | ||
| 59 | }; | ||
| 60 | |||
| 61 | msmgpio: gpio@800000 { | ||
| 62 | compatible = "qcom,msm-gpio"; | ||
| 63 | gpio-controller; | ||
| 64 | #gpio-cells = <2>; | ||
| 65 | ngpio = <150>; | ||
| 66 | interrupts = <0 16 0x4>; | ||
| 67 | interrupt-controller; | ||
| 68 | #interrupt-cells = <2>; | ||
| 69 | reg = <0x800000 0x4000>; | ||
| 70 | }; | ||
| 71 | |||
| 72 | gcc: clock-controller@900000 { | ||
| 73 | compatible = "qcom,gcc-msm8960"; | ||
| 74 | #clock-cells = <1>; | ||
| 75 | #reset-cells = <1>; | ||
| 76 | reg = <0x900000 0x4000>; | ||
| 77 | }; | ||
| 78 | |||
| 79 | clock-controller@4000000 { | ||
| 80 | compatible = "qcom,mmcc-msm8960"; | ||
| 81 | reg = <0x4000000 0x1000>; | ||
| 82 | #clock-cells = <1>; | ||
| 83 | #reset-cells = <1>; | ||
| 84 | }; | ||
| 85 | |||
| 86 | acc0: clock-controller@2088000 { | ||
| 87 | compatible = "qcom,kpss-acc-v1"; | ||
| 88 | reg = <0x02088000 0x1000>, <0x02008000 0x1000>; | ||
| 89 | }; | ||
| 90 | |||
| 91 | acc1: clock-controller@2098000 { | ||
| 92 | compatible = "qcom,kpss-acc-v1"; | ||
| 93 | reg = <0x02098000 0x1000>, <0x02008000 0x1000>; | ||
| 94 | }; | ||
| 95 | |||
| 96 | saw0: regulator@2089000 { | ||
| 97 | compatible = "qcom,saw2"; | ||
| 98 | reg = <0x02089000 0x1000>, <0x02009000 0x1000>; | ||
| 99 | regulator; | ||
| 100 | }; | ||
| 101 | |||
| 102 | saw1: regulator@2099000 { | ||
| 103 | compatible = "qcom,saw2"; | ||
| 104 | reg = <0x02099000 0x1000>, <0x02009000 0x1000>; | ||
| 105 | regulator; | ||
| 106 | }; | ||
| 107 | |||
| 108 | serial@16440000 { | ||
| 109 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; | ||
| 110 | reg = <0x16440000 0x1000>, | ||
| 111 | <0x16400000 0x1000>; | ||
| 112 | interrupts = <0 154 0x0>; | ||
| 113 | clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; | ||
| 114 | clock-names = "core", "iface"; | ||
| 115 | }; | ||
| 116 | |||
| 117 | qcom,ssbi@500000 { | ||
| 118 | compatible = "qcom,ssbi"; | ||
| 119 | reg = <0x500000 0x1000>; | ||
| 120 | qcom,controller-type = "pmic-arbiter"; | ||
| 121 | }; | ||
| 122 | |||
| 123 | rng@1a500000 { | ||
| 124 | compatible = "qcom,prng"; | ||
| 125 | reg = <0x1a500000 0x200>; | ||
| 126 | clocks = <&gcc PRNG_CLK>; | ||
| 127 | clock-names = "core"; | ||
| 128 | }; | ||
| 129 | }; | ||
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 9e5dadb101eb..011eb0937e58 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi | |||
| @@ -9,6 +9,49 @@ | |||
| 9 | compatible = "qcom,msm8974"; | 9 | compatible = "qcom,msm8974"; |
| 10 | interrupt-parent = <&intc>; | 10 | interrupt-parent = <&intc>; |
| 11 | 11 | ||
| 12 | cpus { | ||
| 13 | #address-cells = <1>; | ||
| 14 | #size-cells = <0>; | ||
| 15 | interrupts = <1 9 0xf04>; | ||
| 16 | compatible = "qcom,krait"; | ||
| 17 | enable-method = "qcom,kpss-acc-v2"; | ||
| 18 | |||
| 19 | cpu@0 { | ||
| 20 | device_type = "cpu"; | ||
| 21 | reg = <0>; | ||
| 22 | next-level-cache = <&L2>; | ||
| 23 | qcom,acc = <&acc0>; | ||
| 24 | }; | ||
| 25 | |||
| 26 | cpu@1 { | ||
| 27 | device_type = "cpu"; | ||
| 28 | reg = <1>; | ||
| 29 | next-level-cache = <&L2>; | ||
| 30 | qcom,acc = <&acc1>; | ||
| 31 | }; | ||
| 32 | |||
| 33 | cpu@2 { | ||
| 34 | device_type = "cpu"; | ||
| 35 | reg = <2>; | ||
| 36 | next-level-cache = <&L2>; | ||
| 37 | qcom,acc = <&acc2>; | ||
| 38 | }; | ||
| 39 | |||
| 40 | cpu@3 { | ||
| 41 | device_type = "cpu"; | ||
| 42 | reg = <3>; | ||
| 43 | next-level-cache = <&L2>; | ||
| 44 | qcom,acc = <&acc3>; | ||
| 45 | }; | ||
| 46 | |||
| 47 | L2: l2-cache { | ||
| 48 | compatible = "cache"; | ||
| 49 | cache-level = <2>; | ||
| 50 | interrupts = <0 2 0x4>; | ||
| 51 | qcom,saw = <&saw_l2>; | ||
| 52 | }; | ||
| 53 | }; | ||
| 54 | |||
| 12 | soc: soc { | 55 | soc: soc { |
| 13 | #address-cells = <1>; | 56 | #address-cells = <1>; |
| 14 | #size-cells = <1>; | 57 | #size-cells = <1>; |
| @@ -91,6 +134,32 @@ | |||
| 91 | }; | 134 | }; |
| 92 | }; | 135 | }; |
| 93 | 136 | ||
| 137 | saw_l2: regulator@f9012000 { | ||
| 138 | compatible = "qcom,saw2"; | ||
| 139 | reg = <0xf9012000 0x1000>; | ||
| 140 | regulator; | ||
| 141 | }; | ||
| 142 | |||
| 143 | acc0: clock-controller@f9088000 { | ||
| 144 | compatible = "qcom,kpss-acc-v2"; | ||
| 145 | reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; | ||
| 146 | }; | ||
| 147 | |||
| 148 | acc1: clock-controller@f9098000 { | ||
| 149 | compatible = "qcom,kpss-acc-v2"; | ||
| 150 | reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; | ||
| 151 | }; | ||
| 152 | |||
| 153 | acc2: clock-controller@f90a8000 { | ||
| 154 | compatible = "qcom,kpss-acc-v2"; | ||
| 155 | reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; | ||
| 156 | }; | ||
| 157 | |||
| 158 | acc3: clock-controller@f90b8000 { | ||
| 159 | compatible = "qcom,kpss-acc-v2"; | ||
| 160 | reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; | ||
| 161 | }; | ||
| 162 | |||
| 94 | restart@fc4ab000 { | 163 | restart@fc4ab000 { |
| 95 | compatible = "qcom,pshold"; | 164 | compatible = "qcom,pshold"; |
| 96 | reg = <0xfc4ab000 0x4>; | 165 | reg = <0xfc4ab000 0x4>; |
| @@ -117,5 +186,12 @@ | |||
| 117 | clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; | 186 | clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; |
| 118 | clock-names = "core", "iface"; | 187 | clock-names = "core", "iface"; |
| 119 | }; | 188 | }; |
| 189 | |||
| 190 | rng@f9bff000 { | ||
| 191 | compatible = "qcom,prng"; | ||
| 192 | reg = <0xf9bff000 0x200>; | ||
| 193 | clocks = <&gcc GCC_PRNG_AHB_CLK>; | ||
| 194 | clock-names = "core"; | ||
| 195 | }; | ||
| 120 | }; | 196 | }; |
| 121 | }; | 197 | }; |
diff --git a/arch/arm/boot/dts/r7s72100-genmai-reference.dts b/arch/arm/boot/dts/r7s72100-genmai-reference.dts index da19c70ed82b..e664611a47c8 100644 --- a/arch/arm/boot/dts/r7s72100-genmai-reference.dts +++ b/arch/arm/boot/dts/r7s72100-genmai-reference.dts | |||
| @@ -9,7 +9,7 @@ | |||
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | /dts-v1/; | 11 | /dts-v1/; |
| 12 | /include/ "r7s72100.dtsi" | 12 | #include "r7s72100.dtsi" |
| 13 | 13 | ||
| 14 | / { | 14 | / { |
| 15 | model = "Genmai"; | 15 | model = "Genmai"; |
| @@ -29,3 +29,14 @@ | |||
| 29 | #size-cells = <1>; | 29 | #size-cells = <1>; |
| 30 | }; | 30 | }; |
| 31 | }; | 31 | }; |
| 32 | |||
| 33 | &i2c2 { | ||
| 34 | status = "okay"; | ||
| 35 | clock-frequency = <400000>; | ||
| 36 | |||
| 37 | eeprom@50 { | ||
| 38 | compatible = "renesas,24c128"; | ||
| 39 | reg = <0x50>; | ||
| 40 | pagesize = <64>; | ||
| 41 | }; | ||
| 42 | }; | ||
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 46b82aa7dc4e..ee700717a34b 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi | |||
| @@ -8,12 +8,26 @@ | |||
| 8 | * kind, whether express or implied. | 8 | * kind, whether express or implied. |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 12 | |||
| 11 | / { | 13 | / { |
| 12 | compatible = "renesas,r7s72100"; | 14 | compatible = "renesas,r7s72100"; |
| 13 | interrupt-parent = <&gic>; | 15 | interrupt-parent = <&gic>; |
| 14 | #address-cells = <1>; | 16 | #address-cells = <1>; |
| 15 | #size-cells = <1>; | 17 | #size-cells = <1>; |
| 16 | 18 | ||
| 19 | aliases { | ||
| 20 | i2c0 = &i2c0; | ||
| 21 | i2c1 = &i2c1; | ||
| 22 | i2c2 = &i2c2; | ||
| 23 | i2c3 = &i2c3; | ||
| 24 | spi0 = &spi0; | ||
| 25 | spi1 = &spi1; | ||
| 26 | spi2 = &spi2; | ||
| 27 | spi3 = &spi3; | ||
| 28 | spi4 = &spi4; | ||
| 29 | }; | ||
| 30 | |||
| 17 | cpus { | 31 | cpus { |
| 18 | #address-cells = <1>; | 32 | #address-cells = <1>; |
| 19 | #size-cells = <0>; | 33 | #size-cells = <0>; |
| @@ -33,4 +47,137 @@ | |||
| 33 | reg = <0xe8201000 0x1000>, | 47 | reg = <0xe8201000 0x1000>, |
| 34 | <0xe8202000 0x1000>; | 48 | <0xe8202000 0x1000>; |
| 35 | }; | 49 | }; |
| 50 | |||
| 51 | i2c0: i2c@fcfee000 { | ||
| 52 | #address-cells = <1>; | ||
| 53 | #size-cells = <0>; | ||
| 54 | compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; | ||
| 55 | reg = <0xfcfee000 0x44>; | ||
| 56 | interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>, | ||
| 57 | <0 158 IRQ_TYPE_EDGE_RISING>, | ||
| 58 | <0 159 IRQ_TYPE_EDGE_RISING>, | ||
| 59 | <0 160 IRQ_TYPE_LEVEL_HIGH>, | ||
| 60 | <0 161 IRQ_TYPE_LEVEL_HIGH>, | ||
| 61 | <0 162 IRQ_TYPE_LEVEL_HIGH>, | ||
| 62 | <0 163 IRQ_TYPE_LEVEL_HIGH>, | ||
| 63 | <0 164 IRQ_TYPE_LEVEL_HIGH>; | ||
| 64 | clock-frequency = <100000>; | ||
| 65 | status = "disabled"; | ||
| 66 | }; | ||
| 67 | |||
| 68 | i2c1: i2c@fcfee400 { | ||
| 69 | #address-cells = <1>; | ||
| 70 | #size-cells = <0>; | ||
| 71 | compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; | ||
| 72 | reg = <0xfcfee400 0x44>; | ||
| 73 | interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>, | ||
| 74 | <0 166 IRQ_TYPE_EDGE_RISING>, | ||
| 75 | <0 167 IRQ_TYPE_EDGE_RISING>, | ||
| 76 | <0 168 IRQ_TYPE_LEVEL_HIGH>, | ||
| 77 | <0 169 IRQ_TYPE_LEVEL_HIGH>, | ||
| 78 | <0 170 IRQ_TYPE_LEVEL_HIGH>, | ||
| 79 | <0 171 IRQ_TYPE_LEVEL_HIGH>, | ||
| 80 | <0 172 IRQ_TYPE_LEVEL_HIGH>; | ||
| 81 | clock-frequency = <100000>; | ||
| 82 | status = "disabled"; | ||
| 83 | }; | ||
| 84 | |||
| 85 | i2c2: i2c@fcfee800 { | ||
| 86 | #address-cells = <1>; | ||
| 87 | #size-cells = <0>; | ||
| 88 | compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; | ||
| 89 | reg = <0xfcfee800 0x44>; | ||
| 90 | interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>, | ||
| 91 | <0 174 IRQ_TYPE_EDGE_RISING>, | ||
| 92 | <0 175 IRQ_TYPE_EDGE_RISING>, | ||
| 93 | <0 176 IRQ_TYPE_LEVEL_HIGH>, | ||
| 94 | <0 177 IRQ_TYPE_LEVEL_HIGH>, | ||
| 95 | <0 178 IRQ_TYPE_LEVEL_HIGH>, | ||
| 96 | <0 179 IRQ_TYPE_LEVEL_HIGH>, | ||
| 97 | <0 180 IRQ_TYPE_LEVEL_HIGH>; | ||
| 98 | clock-frequency = <100000>; | ||
| 99 | status = "disabled"; | ||
| 100 | }; | ||
| 101 | |||
| 102 | i2c3: i2c@fcfeec00 { | ||
| 103 | #address-cells = <1>; | ||
| 104 | #size-cells = <0>; | ||
| 105 | compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; | ||
| 106 | reg = <0xfcfeec00 0x44>; | ||
| 107 | interrupts = <0 181 IRQ_TYPE_LEVEL_HIGH>, | ||
| 108 | <0 182 IRQ_TYPE_EDGE_RISING>, | ||
| 109 | <0 183 IRQ_TYPE_EDGE_RISING>, | ||
| 110 | <0 184 IRQ_TYPE_LEVEL_HIGH>, | ||
| 111 | <0 185 IRQ_TYPE_LEVEL_HIGH>, | ||
| 112 | <0 186 IRQ_TYPE_LEVEL_HIGH>, | ||
| 113 | <0 187 IRQ_TYPE_LEVEL_HIGH>, | ||
| 114 | <0 188 IRQ_TYPE_LEVEL_HIGH>; | ||
| 115 | clock-frequency = <100000>; | ||
| 116 | status = "disabled"; | ||
| 117 | }; | ||
| 118 | |||
| 119 | spi0: spi@e800c800 { | ||
| 120 | compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; | ||
| 121 | reg = <0xe800c800 0x24>; | ||
| 122 | interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>, | ||
| 123 | <0 239 IRQ_TYPE_LEVEL_HIGH>, | ||
| 124 | <0 240 IRQ_TYPE_LEVEL_HIGH>; | ||
| 125 | interrupt-names = "error", "rx", "tx"; | ||
| 126 | num-cs = <1>; | ||
| 127 | #address-cells = <1>; | ||
| 128 | #size-cells = <0>; | ||
| 129 | status = "disabled"; | ||
| 130 | }; | ||
| 131 | |||
| 132 | spi1: spi@e800d000 { | ||
| 133 | compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; | ||
| 134 | reg = <0xe800d000 0x24>; | ||
| 135 | interrupts = <0 241 IRQ_TYPE_LEVEL_HIGH>, | ||
| 136 | <0 242 IRQ_TYPE_LEVEL_HIGH>, | ||
| 137 | <0 243 IRQ_TYPE_LEVEL_HIGH>; | ||
| 138 | interrupt-names = "error", "rx", "tx"; | ||
| 139 | num-cs = <1>; | ||
| 140 | #address-cells = <1>; | ||
| 141 | #size-cells = <0>; | ||
| 142 | status = "disabled"; | ||
| 143 | }; | ||
| 144 | |||
| 145 | spi2: spi@e800d800 { | ||
| 146 | compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; | ||
| 147 | reg = <0xe800d800 0x24>; | ||
| 148 | interrupts = <0 244 IRQ_TYPE_LEVEL_HIGH>, | ||
| 149 | <0 245 IRQ_TYPE_LEVEL_HIGH>, | ||
| 150 | <0 246 IRQ_TYPE_LEVEL_HIGH>; | ||
| 151 | interrupt-names = "error", "rx", "tx"; | ||
| 152 | num-cs = <1>; | ||
| 153 | #address-cells = <1>; | ||
| 154 | #size-cells = <0>; | ||
| 155 | status = "disabled"; | ||
| 156 | }; | ||
| 157 | |||
| 158 | spi3: spi@e800e000 { | ||
| 159 | compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; | ||
| 160 | reg = <0xe800e000 0x24>; | ||
| 161 | interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>, | ||
| 162 | <0 248 IRQ_TYPE_LEVEL_HIGH>, | ||
| 163 | <0 249 IRQ_TYPE_LEVEL_HIGH>; | ||
| 164 | interrupt-names = "error", "rx", "tx"; | ||
| 165 | num-cs = <1>; | ||
| 166 | #address-cells = <1>; | ||
| 167 | #size-cells = <0>; | ||
| 168 | status = "disabled"; | ||
| 169 | }; | ||
| 170 | |||
| 171 | spi4: spi@e800e800 { | ||
| 172 | compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; | ||
| 173 | reg = <0xe800e800 0x24>; | ||
| 174 | interrupts = <0 250 IRQ_TYPE_LEVEL_HIGH>, | ||
| 175 | <0 251 IRQ_TYPE_LEVEL_HIGH>, | ||
| 176 | <0 252 IRQ_TYPE_LEVEL_HIGH>; | ||
| 177 | interrupt-names = "error", "rx", "tx"; | ||
| 178 | num-cs = <1>; | ||
| 179 | #address-cells = <1>; | ||
| 180 | #size-cells = <0>; | ||
| 181 | status = "disabled"; | ||
| 182 | }; | ||
| 36 | }; | 183 | }; |
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index ddb3bd7a8838..85c5b3b99f5e 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi | |||
| @@ -203,46 +203,6 @@ | |||
| 203 | status = "disabled"; | 203 | status = "disabled"; |
| 204 | }; | 204 | }; |
| 205 | 205 | ||
| 206 | i2c0: i2c@ffc70000 { | ||
| 207 | #address-cells = <1>; | ||
| 208 | #size-cells = <0>; | ||
| 209 | compatible = "renesas,i2c-r8a7778"; | ||
| 210 | reg = <0xffc70000 0x1000>; | ||
| 211 | interrupt-parent = <&gic>; | ||
| 212 | interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; | ||
| 213 | status = "disabled"; | ||
| 214 | }; | ||
| 215 | |||
| 216 | i2c1: i2c@ffc71000 { | ||
| 217 | #address-cells = <1>; | ||
| 218 | #size-cells = <0>; | ||
| 219 | compatible = "renesas,i2c-r8a7778"; | ||
| 220 | reg = <0xffc71000 0x1000>; | ||
| 221 | interrupt-parent = <&gic>; | ||
| 222 | interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; | ||
| 223 | status = "disabled"; | ||
| 224 | }; | ||
| 225 | |||
| 226 | i2c2: i2c@ffc72000 { | ||
| 227 | #address-cells = <1>; | ||
| 228 | #size-cells = <0>; | ||
| 229 | compatible = "renesas,i2c-r8a7778"; | ||
| 230 | reg = <0xffc72000 0x1000>; | ||
| 231 | interrupt-parent = <&gic>; | ||
| 232 | interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>; | ||
| 233 | status = "disabled"; | ||
| 234 | }; | ||
| 235 | |||
| 236 | i2c3: i2c@ffc73000 { | ||
| 237 | #address-cells = <1>; | ||
| 238 | #size-cells = <0>; | ||
| 239 | compatible = "renesas,i2c-r8a7778"; | ||
| 240 | reg = <0xffc73000 0x1000>; | ||
| 241 | interrupt-parent = <&gic>; | ||
| 242 | interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>; | ||
| 243 | status = "disabled"; | ||
| 244 | }; | ||
| 245 | |||
| 246 | hspi0: spi@fffc7000 { | 206 | hspi0: spi@fffc7000 { |
| 247 | compatible = "renesas,hspi"; | 207 | compatible = "renesas,hspi"; |
| 248 | reg = <0xfffc7000 0x18>; | 208 | reg = <0xfffc7000 0x18>; |
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 57569cba1528..6e99eb2df076 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts | |||
| @@ -1,7 +1,8 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Device Tree Source for the Lager board | 2 | * Device Tree Source for the Lager board |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2013 Renesas Solutions Corp. | 4 | * Copyright (C) 2013-2014 Renesas Solutions Corp. |
| 5 | * Copyright (C) 2014 Cogent Embedded, Inc. | ||
| 5 | * | 6 | * |
| 6 | * This file is licensed under the terms of the GNU General Public License | 7 | * This file is licensed under the terms of the GNU General Public License |
| 7 | * version 2. This program is licensed "as is" without any warranty of any | 8 | * version 2. This program is licensed "as is" without any warranty of any |
| @@ -56,6 +57,54 @@ | |||
| 56 | regulator-boot-on; | 57 | regulator-boot-on; |
| 57 | regulator-always-on; | 58 | regulator-always-on; |
| 58 | }; | 59 | }; |
| 60 | |||
| 61 | vcc_sdhi0: regulator@1 { | ||
| 62 | compatible = "regulator-fixed"; | ||
| 63 | |||
| 64 | regulator-name = "SDHI0 Vcc"; | ||
| 65 | regulator-min-microvolt = <3300000>; | ||
| 66 | regulator-max-microvolt = <3300000>; | ||
| 67 | |||
| 68 | gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>; | ||
| 69 | enable-active-high; | ||
| 70 | }; | ||
| 71 | |||
| 72 | vccq_sdhi0: regulator@2 { | ||
| 73 | compatible = "regulator-gpio"; | ||
| 74 | |||
| 75 | regulator-name = "SDHI0 VccQ"; | ||
| 76 | regulator-min-microvolt = <1800000>; | ||
| 77 | regulator-max-microvolt = <3300000>; | ||
| 78 | |||
| 79 | gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; | ||
| 80 | gpios-states = <1>; | ||
| 81 | states = <3300000 1 | ||
| 82 | 1800000 0>; | ||
| 83 | }; | ||
| 84 | |||
| 85 | vcc_sdhi2: regulator@3 { | ||
| 86 | compatible = "regulator-fixed"; | ||
| 87 | |||
| 88 | regulator-name = "SDHI2 Vcc"; | ||
| 89 | regulator-min-microvolt = <3300000>; | ||
| 90 | regulator-max-microvolt = <3300000>; | ||
| 91 | |||
| 92 | gpio = <&gpio5 25 GPIO_ACTIVE_HIGH>; | ||
| 93 | enable-active-high; | ||
| 94 | }; | ||
| 95 | |||
| 96 | vccq_sdhi2: regulator@4 { | ||
| 97 | compatible = "regulator-gpio"; | ||
| 98 | |||
| 99 | regulator-name = "SDHI2 VccQ"; | ||
| 100 | regulator-min-microvolt = <1800000>; | ||
| 101 | regulator-max-microvolt = <3300000>; | ||
| 102 | |||
| 103 | gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>; | ||
| 104 | gpios-states = <1>; | ||
| 105 | states = <3300000 1 | ||
| 106 | 1800000 0>; | ||
| 107 | }; | ||
| 59 | }; | 108 | }; |
| 60 | 109 | ||
| 61 | &extal_clk { | 110 | &extal_clk { |
| @@ -63,23 +112,68 @@ | |||
| 63 | }; | 112 | }; |
| 64 | 113 | ||
| 65 | &pfc { | 114 | &pfc { |
| 66 | pinctrl-0 = <&scif0_pins &scif1_pins>; | 115 | pinctrl-0 = <&du_pins &scif0_pins &scif1_pins>; |
| 67 | pinctrl-names = "default"; | 116 | pinctrl-names = "default"; |
| 68 | 117 | ||
| 118 | du_pins: du { | ||
| 119 | renesas,groups = "du_rgb666", "du_sync_1", "du_clk_out_0"; | ||
| 120 | renesas,function = "du"; | ||
| 121 | }; | ||
| 122 | |||
| 69 | scif0_pins: serial0 { | 123 | scif0_pins: serial0 { |
| 70 | renesas,groups = "scif0_data"; | 124 | renesas,groups = "scif0_data"; |
| 71 | renesas,function = "scif0"; | 125 | renesas,function = "scif0"; |
| 72 | }; | 126 | }; |
| 73 | 127 | ||
| 128 | ether_pins: ether { | ||
| 129 | renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; | ||
| 130 | renesas,function = "eth"; | ||
| 131 | }; | ||
| 132 | |||
| 133 | phy1_pins: phy1 { | ||
| 134 | renesas,groups = "intc_irq0"; | ||
| 135 | renesas,function = "intc"; | ||
| 136 | }; | ||
| 137 | |||
| 74 | scif1_pins: serial1 { | 138 | scif1_pins: serial1 { |
| 75 | renesas,groups = "scif1_data"; | 139 | renesas,groups = "scif1_data"; |
| 76 | renesas,function = "scif1"; | 140 | renesas,function = "scif1"; |
| 77 | }; | 141 | }; |
| 78 | 142 | ||
| 143 | sdhi0_pins: sd0 { | ||
| 144 | renesas,gpios = "sdhi0_data4", "sdhi0_ctrl"; | ||
| 145 | renesas,function = "sdhi0"; | ||
| 146 | }; | ||
| 147 | |||
| 148 | sdhi2_pins: sd2 { | ||
| 149 | renesas,gpios = "sdhi2_data4", "sdhi2_ctrl"; | ||
| 150 | renesas,function = "sdhi2"; | ||
| 151 | }; | ||
| 152 | |||
| 79 | mmc1_pins: mmc1 { | 153 | mmc1_pins: mmc1 { |
| 80 | renesas,groups = "mmc1_data8", "mmc1_ctrl"; | 154 | renesas,groups = "mmc1_data8", "mmc1_ctrl"; |
| 81 | renesas,function = "mmc1"; | 155 | renesas,function = "mmc1"; |
| 82 | }; | 156 | }; |
| 157 | |||
| 158 | qspi_pins: spi { | ||
| 159 | renesas,groups = "qspi_ctrl", "qspi_data4"; | ||
| 160 | renesas,function = "qspi"; | ||
| 161 | }; | ||
| 162 | }; | ||
| 163 | |||
| 164 | ðer { | ||
| 165 | pinctrl-0 = <ðer_pins &phy1_pins>; | ||
| 166 | pinctrl-names = "default"; | ||
| 167 | |||
| 168 | phy-handle = <&phy1>; | ||
| 169 | renesas,ether-link-active-low; | ||
| 170 | status = "ok"; | ||
| 171 | |||
| 172 | phy1: ethernet-phy@1 { | ||
| 173 | reg = <1>; | ||
| 174 | interrupt-parent = <&irqc0>; | ||
| 175 | interrupts = <0 IRQ_TYPE_LEVEL_LOW>; | ||
| 176 | }; | ||
| 83 | }; | 177 | }; |
| 84 | 178 | ||
| 85 | &mmcif1 { | 179 | &mmcif1 { |
| @@ -91,3 +185,58 @@ | |||
| 91 | non-removable; | 185 | non-removable; |
| 92 | status = "okay"; | 186 | status = "okay"; |
| 93 | }; | 187 | }; |
| 188 | |||
| 189 | &sata1 { | ||
| 190 | status = "okay"; | ||
| 191 | }; | ||
| 192 | |||
| 193 | &spi { | ||
| 194 | pinctrl-0 = <&qspi_pins>; | ||
| 195 | pinctrl-names = "default"; | ||
| 196 | |||
| 197 | status = "okay"; | ||
| 198 | |||
| 199 | flash: flash@0 { | ||
| 200 | #address-cells = <1>; | ||
| 201 | #size-cells = <1>; | ||
| 202 | compatible = "spansion,s25fl512s"; | ||
| 203 | reg = <0>; | ||
| 204 | spi-max-frequency = <30000000>; | ||
| 205 | m25p,fast-read; | ||
| 206 | |||
| 207 | partition@0 { | ||
| 208 | label = "loader"; | ||
| 209 | reg = <0x00000000 0x00040000>; | ||
| 210 | read-only; | ||
| 211 | }; | ||
| 212 | partition@40000 { | ||
| 213 | label = "user"; | ||
| 214 | reg = <0x00040000 0x00400000>; | ||
| 215 | read-only; | ||
| 216 | }; | ||
| 217 | partition@440000 { | ||
| 218 | label = "flash"; | ||
| 219 | reg = <0x00440000 0x03bc0000>; | ||
| 220 | }; | ||
| 221 | }; | ||
| 222 | }; | ||
| 223 | |||
| 224 | &sdhi0 { | ||
| 225 | pinctrl-0 = <&sdhi0_pins>; | ||
| 226 | pinctrl-names = "default"; | ||
| 227 | |||
| 228 | vmmc-supply = <&vcc_sdhi0>; | ||
| 229 | vqmmc-supply = <&vccq_sdhi0>; | ||
| 230 | cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; | ||
| 231 | status = "okay"; | ||
| 232 | }; | ||
| 233 | |||
| 234 | &sdhi2 { | ||
| 235 | pinctrl-0 = <&sdhi2_pins>; | ||
| 236 | pinctrl-names = "default"; | ||
| 237 | |||
| 238 | vmmc-supply = <&vcc_sdhi2>; | ||
| 239 | vqmmc-supply = <&vccq_sdhi2>; | ||
| 240 | cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; | ||
| 241 | status = "okay"; | ||
| 242 | }; | ||
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 71b1251f79c7..e22520dff8c6 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi | |||
| @@ -1,7 +1,8 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Device Tree Source for the r8a7790 SoC | 2 | * Device Tree Source for the r8a7790 SoC |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2013 Renesas Solutions Corp. | 4 | * Copyright (C) 2013-2014 Renesas Solutions Corp. |
| 5 | * Copyright (C) 2014 Cogent Embedded Inc. | ||
| 5 | * | 6 | * |
| 6 | * This file is licensed under the terms of the GNU General Public License | 7 | * This file is licensed under the terms of the GNU General Public License |
| 7 | * version 2. This program is licensed "as is" without any warranty of any | 8 | * version 2. This program is licensed "as is" without any warranty of any |
| @@ -18,6 +19,13 @@ | |||
| 18 | #address-cells = <2>; | 19 | #address-cells = <2>; |
| 19 | #size-cells = <2>; | 20 | #size-cells = <2>; |
| 20 | 21 | ||
| 22 | aliases { | ||
| 23 | i2c0 = &i2c0; | ||
| 24 | i2c1 = &i2c1; | ||
| 25 | i2c2 = &i2c2; | ||
| 26 | i2c3 = &i2c3; | ||
| 27 | }; | ||
| 28 | |||
| 21 | cpus { | 29 | cpus { |
| 22 | #address-cells = <1>; | 30 | #address-cells = <1>; |
| 23 | #size-cells = <0>; | 31 | #size-cells = <0>; |
| @@ -94,7 +102,6 @@ | |||
| 94 | gpio0: gpio@e6050000 { | 102 | gpio0: gpio@e6050000 { |
| 95 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; | 103 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
| 96 | reg = <0 0xe6050000 0 0x50>; | 104 | reg = <0 0xe6050000 0 0x50>; |
| 97 | interrupt-parent = <&gic>; | ||
| 98 | interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; | 105 | interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; |
| 99 | #gpio-cells = <2>; | 106 | #gpio-cells = <2>; |
| 100 | gpio-controller; | 107 | gpio-controller; |
| @@ -106,7 +113,6 @@ | |||
| 106 | gpio1: gpio@e6051000 { | 113 | gpio1: gpio@e6051000 { |
| 107 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; | 114 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
| 108 | reg = <0 0xe6051000 0 0x50>; | 115 | reg = <0 0xe6051000 0 0x50>; |
| 109 | interrupt-parent = <&gic>; | ||
| 110 | interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; | 116 | interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; |
| 111 | #gpio-cells = <2>; | 117 | #gpio-cells = <2>; |
| 112 | gpio-controller; | 118 | gpio-controller; |
| @@ -118,7 +124,6 @@ | |||
| 118 | gpio2: gpio@e6052000 { | 124 | gpio2: gpio@e6052000 { |
| 119 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; | 125 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
| 120 | reg = <0 0xe6052000 0 0x50>; | 126 | reg = <0 0xe6052000 0 0x50>; |
| 121 | interrupt-parent = <&gic>; | ||
| 122 | interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; | 127 | interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; |
| 123 | #gpio-cells = <2>; | 128 | #gpio-cells = <2>; |
| 124 | gpio-controller; | 129 | gpio-controller; |
| @@ -130,7 +135,6 @@ | |||
| 130 | gpio3: gpio@e6053000 { | 135 | gpio3: gpio@e6053000 { |
| 131 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; | 136 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
| 132 | reg = <0 0xe6053000 0 0x50>; | 137 | reg = <0 0xe6053000 0 0x50>; |
| 133 | interrupt-parent = <&gic>; | ||
| 134 | interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; | 138 | interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; |
| 135 | #gpio-cells = <2>; | 139 | #gpio-cells = <2>; |
| 136 | gpio-controller; | 140 | gpio-controller; |
| @@ -142,7 +146,6 @@ | |||
| 142 | gpio4: gpio@e6054000 { | 146 | gpio4: gpio@e6054000 { |
| 143 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; | 147 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
| 144 | reg = <0 0xe6054000 0 0x50>; | 148 | reg = <0 0xe6054000 0 0x50>; |
| 145 | interrupt-parent = <&gic>; | ||
| 146 | interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; | 149 | interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; |
| 147 | #gpio-cells = <2>; | 150 | #gpio-cells = <2>; |
| 148 | gpio-controller; | 151 | gpio-controller; |
| @@ -154,7 +157,6 @@ | |||
| 154 | gpio5: gpio@e6055000 { | 157 | gpio5: gpio@e6055000 { |
| 155 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; | 158 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
| 156 | reg = <0 0xe6055000 0 0x50>; | 159 | reg = <0 0xe6055000 0 0x50>; |
| 157 | interrupt-parent = <&gic>; | ||
| 158 | interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; | 160 | interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; |
| 159 | #gpio-cells = <2>; | 161 | #gpio-cells = <2>; |
| 160 | gpio-controller; | 162 | gpio-controller; |
| @@ -166,8 +168,8 @@ | |||
| 166 | thermal@e61f0000 { | 168 | thermal@e61f0000 { |
| 167 | compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal"; | 169 | compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal"; |
| 168 | reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; | 170 | reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; |
| 169 | interrupt-parent = <&gic>; | ||
| 170 | interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; | 171 | interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; |
| 172 | clocks = <&mstp5_clks R8A7790_CLK_THERMAL>; | ||
| 171 | }; | 173 | }; |
| 172 | 174 | ||
| 173 | timer { | 175 | timer { |
| @@ -183,7 +185,6 @@ | |||
| 183 | #interrupt-cells = <2>; | 185 | #interrupt-cells = <2>; |
| 184 | interrupt-controller; | 186 | interrupt-controller; |
| 185 | reg = <0 0xe61c0000 0 0x200>; | 187 | reg = <0 0xe61c0000 0 0x200>; |
| 186 | interrupt-parent = <&gic>; | ||
| 187 | interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, | 188 | interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, |
| 188 | <0 1 IRQ_TYPE_LEVEL_HIGH>, | 189 | <0 1 IRQ_TYPE_LEVEL_HIGH>, |
| 189 | <0 2 IRQ_TYPE_LEVEL_HIGH>, | 190 | <0 2 IRQ_TYPE_LEVEL_HIGH>, |
| @@ -195,7 +196,6 @@ | |||
| 195 | #size-cells = <0>; | 196 | #size-cells = <0>; |
| 196 | compatible = "renesas,i2c-r8a7790"; | 197 | compatible = "renesas,i2c-r8a7790"; |
| 197 | reg = <0 0xe6508000 0 0x40>; | 198 | reg = <0 0xe6508000 0 0x40>; |
| 198 | interrupt-parent = <&gic>; | ||
| 199 | interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; | 199 | interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; |
| 200 | clocks = <&mstp9_clks R8A7790_CLK_I2C0>; | 200 | clocks = <&mstp9_clks R8A7790_CLK_I2C0>; |
| 201 | status = "disabled"; | 201 | status = "disabled"; |
| @@ -206,7 +206,6 @@ | |||
| 206 | #size-cells = <0>; | 206 | #size-cells = <0>; |
| 207 | compatible = "renesas,i2c-r8a7790"; | 207 | compatible = "renesas,i2c-r8a7790"; |
| 208 | reg = <0 0xe6518000 0 0x40>; | 208 | reg = <0 0xe6518000 0 0x40>; |
| 209 | interrupt-parent = <&gic>; | ||
| 210 | interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>; | 209 | interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>; |
| 211 | clocks = <&mstp9_clks R8A7790_CLK_I2C1>; | 210 | clocks = <&mstp9_clks R8A7790_CLK_I2C1>; |
| 212 | status = "disabled"; | 211 | status = "disabled"; |
| @@ -217,7 +216,6 @@ | |||
| 217 | #size-cells = <0>; | 216 | #size-cells = <0>; |
| 218 | compatible = "renesas,i2c-r8a7790"; | 217 | compatible = "renesas,i2c-r8a7790"; |
| 219 | reg = <0 0xe6530000 0 0x40>; | 218 | reg = <0 0xe6530000 0 0x40>; |
| 220 | interrupt-parent = <&gic>; | ||
| 221 | interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>; | 219 | interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>; |
| 222 | clocks = <&mstp9_clks R8A7790_CLK_I2C2>; | 220 | clocks = <&mstp9_clks R8A7790_CLK_I2C2>; |
| 223 | status = "disabled"; | 221 | status = "disabled"; |
| @@ -228,7 +226,6 @@ | |||
| 228 | #size-cells = <0>; | 226 | #size-cells = <0>; |
| 229 | compatible = "renesas,i2c-r8a7790"; | 227 | compatible = "renesas,i2c-r8a7790"; |
| 230 | reg = <0 0xe6540000 0 0x40>; | 228 | reg = <0 0xe6540000 0 0x40>; |
| 231 | interrupt-parent = <&gic>; | ||
| 232 | interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>; | 229 | interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>; |
| 233 | clocks = <&mstp9_clks R8A7790_CLK_I2C3>; | 230 | clocks = <&mstp9_clks R8A7790_CLK_I2C3>; |
| 234 | status = "disabled"; | 231 | status = "disabled"; |
| @@ -237,7 +234,6 @@ | |||
| 237 | mmcif0: mmcif@ee200000 { | 234 | mmcif0: mmcif@ee200000 { |
| 238 | compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; | 235 | compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; |
| 239 | reg = <0 0xee200000 0 0x80>; | 236 | reg = <0 0xee200000 0 0x80>; |
| 240 | interrupt-parent = <&gic>; | ||
| 241 | interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; | 237 | interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; |
| 242 | clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; | 238 | clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; |
| 243 | reg-io-width = <4>; | 239 | reg-io-width = <4>; |
| @@ -247,7 +243,6 @@ | |||
| 247 | mmcif1: mmc@ee220000 { | 243 | mmcif1: mmc@ee220000 { |
| 248 | compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; | 244 | compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; |
| 249 | reg = <0 0xee220000 0 0x80>; | 245 | reg = <0 0xee220000 0 0x80>; |
| 250 | interrupt-parent = <&gic>; | ||
| 251 | interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; | 246 | interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; |
| 252 | clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>; | 247 | clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>; |
| 253 | reg-io-width = <4>; | 248 | reg-io-width = <4>; |
| @@ -262,7 +257,6 @@ | |||
| 262 | sdhi0: sd@ee100000 { | 257 | sdhi0: sd@ee100000 { |
| 263 | compatible = "renesas,sdhi-r8a7790"; | 258 | compatible = "renesas,sdhi-r8a7790"; |
| 264 | reg = <0 0xee100000 0 0x200>; | 259 | reg = <0 0xee100000 0 0x200>; |
| 265 | interrupt-parent = <&gic>; | ||
| 266 | interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; | 260 | interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; |
| 267 | clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; | 261 | clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; |
| 268 | cap-sd-highspeed; | 262 | cap-sd-highspeed; |
| @@ -272,7 +266,6 @@ | |||
| 272 | sdhi1: sd@ee120000 { | 266 | sdhi1: sd@ee120000 { |
| 273 | compatible = "renesas,sdhi-r8a7790"; | 267 | compatible = "renesas,sdhi-r8a7790"; |
| 274 | reg = <0 0xee120000 0 0x200>; | 268 | reg = <0 0xee120000 0 0x200>; |
| 275 | interrupt-parent = <&gic>; | ||
| 276 | interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; | 269 | interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; |
| 277 | clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; | 270 | clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; |
| 278 | cap-sd-highspeed; | 271 | cap-sd-highspeed; |
| @@ -282,7 +275,6 @@ | |||
| 282 | sdhi2: sd@ee140000 { | 275 | sdhi2: sd@ee140000 { |
| 283 | compatible = "renesas,sdhi-r8a7790"; | 276 | compatible = "renesas,sdhi-r8a7790"; |
| 284 | reg = <0 0xee140000 0 0x100>; | 277 | reg = <0 0xee140000 0 0x100>; |
| 285 | interrupt-parent = <&gic>; | ||
| 286 | interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; | 278 | interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; |
| 287 | clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; | 279 | clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; |
| 288 | cap-sd-highspeed; | 280 | cap-sd-highspeed; |
| @@ -292,13 +284,129 @@ | |||
| 292 | sdhi3: sd@ee160000 { | 284 | sdhi3: sd@ee160000 { |
| 293 | compatible = "renesas,sdhi-r8a7790"; | 285 | compatible = "renesas,sdhi-r8a7790"; |
| 294 | reg = <0 0xee160000 0 0x100>; | 286 | reg = <0 0xee160000 0 0x100>; |
| 295 | interrupt-parent = <&gic>; | ||
| 296 | interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; | 287 | interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; |
| 297 | clocks = <&mstp3_clks R8A7790_CLK_SDHI3>; | 288 | clocks = <&mstp3_clks R8A7790_CLK_SDHI3>; |
| 298 | cap-sd-highspeed; | 289 | cap-sd-highspeed; |
| 299 | status = "disabled"; | 290 | status = "disabled"; |
| 300 | }; | 291 | }; |
| 301 | 292 | ||
| 293 | scifa0: serial@e6c40000 { | ||
| 294 | compatible = "renesas,scifa-r8a7790", "renesas,scifa"; | ||
| 295 | reg = <0 0xe6c40000 0 64>; | ||
| 296 | interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; | ||
| 297 | clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>; | ||
| 298 | clock-names = "sci_ick"; | ||
| 299 | status = "disabled"; | ||
| 300 | }; | ||
| 301 | |||
| 302 | scifa1: serial@e6c50000 { | ||
| 303 | compatible = "renesas,scifa-r8a7790", "renesas,scifa"; | ||
| 304 | reg = <0 0xe6c50000 0 64>; | ||
| 305 | interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; | ||
| 306 | clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>; | ||
| 307 | clock-names = "sci_ick"; | ||
| 308 | status = "disabled"; | ||
| 309 | }; | ||
| 310 | |||
| 311 | scifa2: serial@e6c60000 { | ||
| 312 | compatible = "renesas,scifa-r8a7790", "renesas,scifa"; | ||
| 313 | reg = <0 0xe6c60000 0 64>; | ||
| 314 | interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; | ||
| 315 | clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>; | ||
| 316 | clock-names = "sci_ick"; | ||
| 317 | status = "disabled"; | ||
| 318 | }; | ||
| 319 | |||
| 320 | scifb0: serial@e6c20000 { | ||
| 321 | compatible = "renesas,scifb-r8a7790", "renesas,scifb"; | ||
| 322 | reg = <0 0xe6c20000 0 64>; | ||
| 323 | interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; | ||
| 324 | clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>; | ||
| 325 | clock-names = "sci_ick"; | ||
| 326 | status = "disabled"; | ||
| 327 | }; | ||
| 328 | |||
| 329 | scifb1: serial@e6c30000 { | ||
| 330 | compatible = "renesas,scifb-r8a7790", "renesas,scifb"; | ||
| 331 | reg = <0 0xe6c30000 0 64>; | ||
| 332 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; | ||
| 333 | clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>; | ||
| 334 | clock-names = "sci_ick"; | ||
| 335 | status = "disabled"; | ||
| 336 | }; | ||
| 337 | |||
| 338 | scifb2: serial@e6ce0000 { | ||
| 339 | compatible = "renesas,scifb-r8a7790", "renesas,scifb"; | ||
| 340 | reg = <0 0xe6ce0000 0 64>; | ||
| 341 | interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; | ||
| 342 | clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>; | ||
| 343 | clock-names = "sci_ick"; | ||
| 344 | status = "disabled"; | ||
| 345 | }; | ||
| 346 | |||
| 347 | scif0: serial@e6e60000 { | ||
| 348 | compatible = "renesas,scif-r8a7790", "renesas,scif"; | ||
| 349 | reg = <0 0xe6e60000 0 64>; | ||
| 350 | interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; | ||
| 351 | clocks = <&mstp7_clks R8A7790_CLK_SCIF0>; | ||
| 352 | clock-names = "sci_ick"; | ||
| 353 | status = "disabled"; | ||
| 354 | }; | ||
| 355 | |||
| 356 | scif1: serial@e6e68000 { | ||
| 357 | compatible = "renesas,scif-r8a7790", "renesas,scif"; | ||
| 358 | reg = <0 0xe6e68000 0 64>; | ||
| 359 | interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; | ||
| 360 | clocks = <&mstp7_clks R8A7790_CLK_SCIF1>; | ||
| 361 | clock-names = "sci_ick"; | ||
| 362 | status = "disabled"; | ||
| 363 | }; | ||
| 364 | |||
| 365 | hscif0: serial@e62c0000 { | ||
| 366 | compatible = "renesas,hscif-r8a7790", "renesas,hscif"; | ||
| 367 | reg = <0 0xe62c0000 0 96>; | ||
| 368 | interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; | ||
| 369 | clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>; | ||
| 370 | clock-names = "sci_ick"; | ||
| 371 | status = "disabled"; | ||
| 372 | }; | ||
| 373 | |||
| 374 | hscif1: serial@e62c8000 { | ||
| 375 | compatible = "renesas,hscif-r8a7790", "renesas,hscif"; | ||
| 376 | reg = <0 0xe62c8000 0 96>; | ||
| 377 | interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; | ||
| 378 | clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>; | ||
| 379 | clock-names = "sci_ick"; | ||
| 380 | status = "disabled"; | ||
| 381 | }; | ||
| 382 | |||
| 383 | ether: ethernet@ee700000 { | ||
| 384 | compatible = "renesas,ether-r8a7790"; | ||
| 385 | reg = <0 0xee700000 0 0x400>; | ||
| 386 | interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; | ||
| 387 | clocks = <&mstp8_clks R8A7790_CLK_ETHER>; | ||
| 388 | phy-mode = "rmii"; | ||
| 389 | #address-cells = <1>; | ||
| 390 | #size-cells = <0>; | ||
| 391 | status = "disabled"; | ||
| 392 | }; | ||
| 393 | |||
| 394 | sata0: sata@ee300000 { | ||
| 395 | compatible = "renesas,sata-r8a7790"; | ||
| 396 | reg = <0 0xee300000 0 0x2000>; | ||
| 397 | interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; | ||
| 398 | clocks = <&mstp8_clks R8A7790_CLK_SATA0>; | ||
| 399 | status = "disabled"; | ||
| 400 | }; | ||
| 401 | |||
| 402 | sata1: sata@ee500000 { | ||
| 403 | compatible = "renesas,sata-r8a7790"; | ||
| 404 | reg = <0 0xee500000 0 0x2000>; | ||
| 405 | interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; | ||
| 406 | clocks = <&mstp8_clks R8A7790_CLK_SATA1>; | ||
| 407 | status = "disabled"; | ||
| 408 | }; | ||
| 409 | |||
| 302 | clocks { | 410 | clocks { |
| 303 | #address-cells = <2>; | 411 | #address-cells = <2>; |
| 304 | #size-cells = <2>; | 412 | #size-cells = <2>; |
| @@ -607,10 +715,16 @@ | |||
| 607 | mstp8_clks: mstp8_clks@e6150990 { | 715 | mstp8_clks: mstp8_clks@e6150990 { |
| 608 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | 716 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 609 | reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; | 717 | reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; |
| 610 | clocks = <&p_clk>; | 718 | clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, |
| 719 | <&zs_clk>, <&zs_clk>; | ||
| 611 | #clock-cells = <1>; | 720 | #clock-cells = <1>; |
| 612 | renesas,clock-indices = <R8A7790_CLK_ETHER>; | 721 | renesas,clock-indices = < |
| 613 | clock-output-names = "ether"; | 722 | R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1 |
| 723 | R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1 | ||
| 724 | R8A7790_CLK_SATA0 | ||
| 725 | >; | ||
| 726 | clock-output-names = | ||
| 727 | "vin3", "vin2", "vin1", "vin0", "ether", "sata1", "sata0"; | ||
| 614 | }; | 728 | }; |
| 615 | mstp9_clks: mstp9_clks@e6150994 { | 729 | mstp9_clks: mstp9_clks@e6150994 { |
| 616 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | 730 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| @@ -627,4 +741,15 @@ | |||
| 627 | "rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0"; | 741 | "rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0"; |
| 628 | }; | 742 | }; |
| 629 | }; | 743 | }; |
| 744 | |||
| 745 | spi: spi@e6b10000 { | ||
| 746 | compatible = "renesas,qspi-r8a7790", "renesas,qspi"; | ||
| 747 | reg = <0 0xe6b10000 0 0x2c>; | ||
| 748 | interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; | ||
| 749 | clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>; | ||
| 750 | num-cs = <1>; | ||
| 751 | #address-cells = <1>; | ||
| 752 | #size-cells = <0>; | ||
| 753 | status = "disabled"; | ||
| 754 | }; | ||
| 630 | }; | 755 | }; |
diff --git a/arch/arm/boot/dts/r8a7791-koelsch-reference.dts b/arch/arm/boot/dts/r8a7791-koelsch-reference.dts deleted file mode 100644 index 588ca17ea1f0..000000000000 --- a/arch/arm/boot/dts/r8a7791-koelsch-reference.dts +++ /dev/null | |||
| @@ -1,115 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Device Tree Source for the Koelsch board | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Renesas Electronics Corporation | ||
| 5 | * Copyright (C) 2013 Renesas Solutions Corp. | ||
| 6 | * | ||
| 7 | * This file is licensed under the terms of the GNU General Public License | ||
| 8 | * version 2. This program is licensed "as is" without any warranty of any | ||
| 9 | * kind, whether express or implied. | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | #include "r8a7791.dtsi" | ||
| 14 | #include <dt-bindings/gpio/gpio.h> | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Koelsch"; | ||
| 18 | compatible = "renesas,koelsch-reference", "renesas,r8a7791"; | ||
| 19 | |||
| 20 | chosen { | ||
| 21 | bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp"; | ||
| 22 | }; | ||
| 23 | |||
| 24 | memory@40000000 { | ||
| 25 | device_type = "memory"; | ||
| 26 | reg = <0 0x40000000 0 0x80000000>; | ||
| 27 | }; | ||
| 28 | |||
| 29 | lbsc { | ||
| 30 | #address-cells = <1>; | ||
| 31 | #size-cells = <1>; | ||
| 32 | }; | ||
| 33 | |||
| 34 | gpio-keys { | ||
| 35 | compatible = "gpio-keys"; | ||
| 36 | |||
| 37 | key-a { | ||
| 38 | gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; | ||
| 39 | linux,code = <30>; | ||
| 40 | label = "SW30"; | ||
| 41 | gpio-key,wakeup; | ||
| 42 | debounce-interval = <20>; | ||
| 43 | }; | ||
| 44 | key-b { | ||
| 45 | gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; | ||
| 46 | linux,code = <48>; | ||
| 47 | label = "SW31"; | ||
| 48 | gpio-key,wakeup; | ||
| 49 | debounce-interval = <20>; | ||
| 50 | }; | ||
| 51 | key-c { | ||
| 52 | gpios = <&gpio7 2 GPIO_ACTIVE_LOW>; | ||
| 53 | linux,code = <46>; | ||
| 54 | label = "SW32"; | ||
| 55 | gpio-key,wakeup; | ||
| 56 | debounce-interval = <20>; | ||
| 57 | }; | ||
| 58 | key-d { | ||
| 59 | gpios = <&gpio7 3 GPIO_ACTIVE_LOW>; | ||
| 60 | linux,code = <32>; | ||
| 61 | label = "SW33"; | ||
| 62 | gpio-key,wakeup; | ||
| 63 | debounce-interval = <20>; | ||
| 64 | }; | ||
| 65 | key-e { | ||
| 66 | gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; | ||
| 67 | linux,code = <18>; | ||
| 68 | label = "SW34"; | ||
| 69 | gpio-key,wakeup; | ||
| 70 | debounce-interval = <20>; | ||
| 71 | }; | ||
| 72 | key-f { | ||
| 73 | gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; | ||
| 74 | linux,code = <33>; | ||
| 75 | label = "SW35"; | ||
| 76 | gpio-key,wakeup; | ||
| 77 | debounce-interval = <20>; | ||
| 78 | }; | ||
| 79 | key-g { | ||
| 80 | gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; | ||
| 81 | linux,code = <34>; | ||
| 82 | label = "SW36"; | ||
| 83 | gpio-key,wakeup; | ||
| 84 | debounce-interval = <20>; | ||
| 85 | }; | ||
| 86 | }; | ||
| 87 | |||
| 88 | leds { | ||
| 89 | compatible = "gpio-leds"; | ||
| 90 | led6 { | ||
| 91 | gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; | ||
| 92 | }; | ||
| 93 | led7 { | ||
| 94 | gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; | ||
| 95 | }; | ||
| 96 | led8 { | ||
| 97 | gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; | ||
| 98 | }; | ||
| 99 | }; | ||
| 100 | }; | ||
| 101 | |||
| 102 | &pfc { | ||
| 103 | pinctrl-0 = <&scif0_pins &scif1_pins>; | ||
| 104 | pinctrl-names = "default"; | ||
| 105 | |||
| 106 | scif0_pins: serial0 { | ||
| 107 | renesas,groups = "scif0_data_d"; | ||
| 108 | renesas,function = "scif0"; | ||
| 109 | }; | ||
| 110 | |||
| 111 | scif1_pins: serial1 { | ||
| 112 | renesas,groups = "scif1_data_d"; | ||
| 113 | renesas,function = "scif1"; | ||
| 114 | }; | ||
| 115 | }; | ||
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index fd556c3483e3..bdd73e6657b2 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts | |||
| @@ -2,7 +2,8 @@ | |||
| 2 | * Device Tree Source for the Koelsch board | 2 | * Device Tree Source for the Koelsch board |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2013 Renesas Electronics Corporation | 4 | * Copyright (C) 2013 Renesas Electronics Corporation |
| 5 | * Copyright (C) 2013 Renesas Solutions Corp. | 5 | * Copyright (C) 2013-2014 Renesas Solutions Corp. |
| 6 | * Copyright (C) 2014 Cogent Embedded, Inc. | ||
| 6 | * | 7 | * |
| 7 | * This file is licensed under the terms of the GNU General Public License | 8 | * This file is licensed under the terms of the GNU General Public License |
| 8 | * version 2. This program is licensed "as is" without any warranty of any | 9 | * version 2. This program is licensed "as is" without any warranty of any |
| @@ -23,7 +24,12 @@ | |||
| 23 | 24 | ||
| 24 | memory@40000000 { | 25 | memory@40000000 { |
| 25 | device_type = "memory"; | 26 | device_type = "memory"; |
| 26 | reg = <0 0x40000000 0 0x80000000>; | 27 | reg = <0 0x40000000 0 0x40000000>; |
| 28 | }; | ||
| 29 | |||
| 30 | memory@200000000 { | ||
| 31 | device_type = "memory"; | ||
| 32 | reg = <2 0x00000000 0 0x40000000>; | ||
| 27 | }; | 33 | }; |
| 28 | 34 | ||
| 29 | lbsc { | 35 | lbsc { |
| @@ -31,6 +37,60 @@ | |||
| 31 | #size-cells = <1>; | 37 | #size-cells = <1>; |
| 32 | }; | 38 | }; |
| 33 | 39 | ||
| 40 | gpio-keys { | ||
| 41 | compatible = "gpio-keys"; | ||
| 42 | |||
| 43 | key-a { | ||
| 44 | gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; | ||
| 45 | linux,code = <30>; | ||
| 46 | label = "SW30"; | ||
| 47 | gpio-key,wakeup; | ||
| 48 | debounce-interval = <20>; | ||
| 49 | }; | ||
| 50 | key-b { | ||
| 51 | gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; | ||
| 52 | linux,code = <48>; | ||
| 53 | label = "SW31"; | ||
| 54 | gpio-key,wakeup; | ||
| 55 | debounce-interval = <20>; | ||
| 56 | }; | ||
| 57 | key-c { | ||
| 58 | gpios = <&gpio7 2 GPIO_ACTIVE_LOW>; | ||
| 59 | linux,code = <46>; | ||
| 60 | label = "SW32"; | ||
| 61 | gpio-key,wakeup; | ||
| 62 | debounce-interval = <20>; | ||
| 63 | }; | ||
| 64 | key-d { | ||
| 65 | gpios = <&gpio7 3 GPIO_ACTIVE_LOW>; | ||
| 66 | linux,code = <32>; | ||
| 67 | label = "SW33"; | ||
| 68 | gpio-key,wakeup; | ||
| 69 | debounce-interval = <20>; | ||
| 70 | }; | ||
| 71 | key-e { | ||
| 72 | gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; | ||
| 73 | linux,code = <18>; | ||
| 74 | label = "SW34"; | ||
| 75 | gpio-key,wakeup; | ||
| 76 | debounce-interval = <20>; | ||
| 77 | }; | ||
| 78 | key-f { | ||
| 79 | gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; | ||
| 80 | linux,code = <33>; | ||
| 81 | label = "SW35"; | ||
| 82 | gpio-key,wakeup; | ||
| 83 | debounce-interval = <20>; | ||
| 84 | }; | ||
| 85 | key-g { | ||
| 86 | gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; | ||
| 87 | linux,code = <34>; | ||
| 88 | label = "SW36"; | ||
| 89 | gpio-key,wakeup; | ||
| 90 | debounce-interval = <20>; | ||
| 91 | }; | ||
| 92 | }; | ||
| 93 | |||
| 34 | leds { | 94 | leds { |
| 35 | compatible = "gpio-leds"; | 95 | compatible = "gpio-leds"; |
| 36 | led6 { | 96 | led6 { |
| @@ -43,16 +103,112 @@ | |||
| 43 | gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; | 103 | gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; |
| 44 | }; | 104 | }; |
| 45 | }; | 105 | }; |
| 106 | |||
| 107 | vcc_sdhi0: regulator@0 { | ||
| 108 | compatible = "regulator-fixed"; | ||
| 109 | |||
| 110 | regulator-name = "SDHI0 Vcc"; | ||
| 111 | regulator-min-microvolt = <3300000>; | ||
| 112 | regulator-max-microvolt = <3300000>; | ||
| 113 | |||
| 114 | gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>; | ||
| 115 | enable-active-high; | ||
| 116 | }; | ||
| 117 | |||
| 118 | vccq_sdhi0: regulator@1 { | ||
| 119 | compatible = "regulator-gpio"; | ||
| 120 | |||
| 121 | regulator-name = "SDHI0 VccQ"; | ||
| 122 | regulator-min-microvolt = <1800000>; | ||
| 123 | regulator-max-microvolt = <3300000>; | ||
| 124 | |||
| 125 | gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; | ||
| 126 | gpios-states = <1>; | ||
| 127 | states = <3300000 1 | ||
| 128 | 1800000 0>; | ||
| 129 | }; | ||
| 130 | |||
| 131 | vcc_sdhi1: regulator@2 { | ||
| 132 | compatible = "regulator-fixed"; | ||
| 133 | |||
| 134 | regulator-name = "SDHI1 Vcc"; | ||
| 135 | regulator-min-microvolt = <3300000>; | ||
| 136 | regulator-max-microvolt = <3300000>; | ||
| 137 | |||
| 138 | gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>; | ||
| 139 | enable-active-high; | ||
| 140 | }; | ||
| 141 | |||
| 142 | vccq_sdhi1: regulator@3 { | ||
| 143 | compatible = "regulator-gpio"; | ||
| 144 | |||
| 145 | regulator-name = "SDHI1 VccQ"; | ||
| 146 | regulator-min-microvolt = <1800000>; | ||
| 147 | regulator-max-microvolt = <3300000>; | ||
| 148 | |||
| 149 | gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; | ||
| 150 | gpios-states = <1>; | ||
| 151 | states = <3300000 1 | ||
| 152 | 1800000 0>; | ||
| 153 | }; | ||
| 154 | |||
| 155 | vcc_sdhi2: regulator@4 { | ||
| 156 | compatible = "regulator-fixed"; | ||
| 157 | |||
| 158 | regulator-name = "SDHI2 Vcc"; | ||
| 159 | regulator-min-microvolt = <3300000>; | ||
| 160 | regulator-max-microvolt = <3300000>; | ||
| 161 | |||
| 162 | gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>; | ||
| 163 | enable-active-high; | ||
| 164 | }; | ||
| 165 | |||
| 166 | vccq_sdhi2: regulator@5 { | ||
| 167 | compatible = "regulator-gpio"; | ||
| 168 | |||
| 169 | regulator-name = "SDHI2 VccQ"; | ||
| 170 | regulator-min-microvolt = <1800000>; | ||
| 171 | regulator-max-microvolt = <3300000>; | ||
| 172 | |||
| 173 | gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; | ||
| 174 | gpios-states = <1>; | ||
| 175 | states = <3300000 1 | ||
| 176 | 1800000 0>; | ||
| 177 | }; | ||
| 46 | }; | 178 | }; |
| 47 | 179 | ||
| 48 | &extal_clk { | 180 | &extal_clk { |
| 49 | clock-frequency = <20000000>; | 181 | clock-frequency = <20000000>; |
| 50 | }; | 182 | }; |
| 51 | 183 | ||
| 184 | &i2c2 { | ||
| 185 | pinctrl-0 = <&i2c2_pins>; | ||
| 186 | pinctrl-names = "default"; | ||
| 187 | |||
| 188 | status = "okay"; | ||
| 189 | clock-frequency = <400000>; | ||
| 190 | |||
| 191 | eeprom@50 { | ||
| 192 | compatible = "renesas,24c02"; | ||
| 193 | reg = <0x50>; | ||
| 194 | pagesize = <16>; | ||
| 195 | }; | ||
| 196 | }; | ||
| 197 | |||
| 52 | &pfc { | 198 | &pfc { |
| 53 | pinctrl-0 = <&scif0_pins &scif1_pins>; | 199 | pinctrl-0 = <&du_pins &scif0_pins &scif1_pins>; |
| 54 | pinctrl-names = "default"; | 200 | pinctrl-names = "default"; |
| 55 | 201 | ||
| 202 | i2c2_pins: i2c { | ||
| 203 | renesas,groups = "i2c2"; | ||
| 204 | renesas,function = "i2c2"; | ||
| 205 | }; | ||
| 206 | |||
| 207 | du_pins: du { | ||
| 208 | renesas,groups = "du_rgb666", "du_sync", "du_clk_out_0"; | ||
| 209 | renesas,function = "du"; | ||
| 210 | }; | ||
| 211 | |||
| 56 | scif0_pins: serial0 { | 212 | scif0_pins: serial0 { |
| 57 | renesas,groups = "scif0_data_d"; | 213 | renesas,groups = "scif0_data_d"; |
| 58 | renesas,function = "scif0"; | 214 | renesas,function = "scif0"; |
| @@ -62,4 +218,116 @@ | |||
| 62 | renesas,groups = "scif1_data_d"; | 218 | renesas,groups = "scif1_data_d"; |
| 63 | renesas,function = "scif1"; | 219 | renesas,function = "scif1"; |
| 64 | }; | 220 | }; |
| 221 | |||
| 222 | ether_pins: ether { | ||
| 223 | renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; | ||
| 224 | renesas,function = "eth"; | ||
| 225 | }; | ||
| 226 | |||
| 227 | phy1_pins: phy1 { | ||
| 228 | renesas,groups = "intc_irq0"; | ||
| 229 | renesas,function = "intc"; | ||
| 230 | }; | ||
| 231 | |||
| 232 | sdhi0_pins: sd0 { | ||
| 233 | renesas,gpios = "sdhi0_data4", "sdhi0_ctrl"; | ||
| 234 | renesas,function = "sdhi0"; | ||
| 235 | }; | ||
| 236 | |||
| 237 | sdhi1_pins: sd1 { | ||
| 238 | renesas,gpios = "sdhi1_data4", "sdhi1_ctrl"; | ||
| 239 | renesas,function = "sdhi1"; | ||
| 240 | }; | ||
| 241 | |||
| 242 | sdhi2_pins: sd2 { | ||
| 243 | renesas,gpios = "sdhi2_data4", "sdhi2_ctrl"; | ||
| 244 | renesas,function = "sdhi2"; | ||
| 245 | }; | ||
| 246 | |||
| 247 | qspi_pins: spi { | ||
| 248 | renesas,groups = "qspi_ctrl", "qspi_data4"; | ||
| 249 | renesas,function = "qspi"; | ||
| 250 | }; | ||
| 251 | }; | ||
| 252 | |||
| 253 | ðer { | ||
| 254 | pinctrl-0 = <ðer_pins &phy1_pins>; | ||
| 255 | pinctrl-names = "default"; | ||
| 256 | |||
| 257 | phy-handle = <&phy1>; | ||
| 258 | renesas,ether-link-active-low; | ||
| 259 | status = "ok"; | ||
| 260 | |||
| 261 | phy1: ethernet-phy@1 { | ||
| 262 | reg = <1>; | ||
| 263 | interrupt-parent = <&irqc0>; | ||
| 264 | interrupts = <0 IRQ_TYPE_LEVEL_LOW>; | ||
| 265 | }; | ||
| 266 | }; | ||
| 267 | |||
| 268 | &sata0 { | ||
| 269 | status = "okay"; | ||
| 270 | }; | ||
| 271 | |||
| 272 | &sdhi0 { | ||
| 273 | pinctrl-0 = <&sdhi0_pins>; | ||
| 274 | pinctrl-names = "default"; | ||
| 275 | |||
| 276 | vmmc-supply = <&vcc_sdhi0>; | ||
| 277 | vqmmc-supply = <&vccq_sdhi0>; | ||
| 278 | cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; | ||
| 279 | wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; | ||
| 280 | status = "okay"; | ||
| 281 | }; | ||
| 282 | |||
| 283 | &sdhi1 { | ||
| 284 | pinctrl-0 = <&sdhi1_pins>; | ||
| 285 | pinctrl-names = "default"; | ||
| 286 | |||
| 287 | vmmc-supply = <&vcc_sdhi1>; | ||
| 288 | vqmmc-supply = <&vccq_sdhi1>; | ||
| 289 | cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; | ||
| 290 | wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; | ||
| 291 | status = "okay"; | ||
| 292 | }; | ||
| 293 | |||
| 294 | &sdhi2 { | ||
| 295 | pinctrl-0 = <&sdhi2_pins>; | ||
| 296 | pinctrl-names = "default"; | ||
| 297 | |||
| 298 | vmmc-supply = <&vcc_sdhi2>; | ||
| 299 | vqmmc-supply = <&vccq_sdhi2>; | ||
| 300 | cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>; | ||
| 301 | status = "okay"; | ||
| 302 | }; | ||
| 303 | |||
| 304 | &spi { | ||
| 305 | pinctrl-0 = <&qspi_pins>; | ||
| 306 | pinctrl-names = "default"; | ||
| 307 | |||
| 308 | status = "okay"; | ||
| 309 | |||
| 310 | flash: flash@0 { | ||
| 311 | #address-cells = <1>; | ||
| 312 | #size-cells = <1>; | ||
| 313 | compatible = "spansion,s25fl512s"; | ||
| 314 | reg = <0>; | ||
| 315 | spi-max-frequency = <30000000>; | ||
| 316 | m25p,fast-read; | ||
| 317 | |||
| 318 | partition@0 { | ||
| 319 | label = "loader"; | ||
| 320 | reg = <0x00000000 0x00080000>; | ||
| 321 | read-only; | ||
| 322 | }; | ||
| 323 | partition@80000 { | ||
| 324 | label = "bootenv"; | ||
| 325 | reg = <0x00080000 0x00080000>; | ||
| 326 | read-only; | ||
| 327 | }; | ||
| 328 | partition@100000 { | ||
| 329 | label = "data"; | ||
| 330 | reg = <0x00100000 0x03f00000>; | ||
| 331 | }; | ||
| 332 | }; | ||
| 65 | }; | 333 | }; |
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 19c65509a22d..b007f9e04ef4 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi | |||
| @@ -2,7 +2,8 @@ | |||
| 2 | * Device Tree Source for the r8a7791 SoC | 2 | * Device Tree Source for the r8a7791 SoC |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2013 Renesas Electronics Corporation | 4 | * Copyright (C) 2013 Renesas Electronics Corporation |
| 5 | * Copyright (C) 2013 Renesas Solutions Corp. | 5 | * Copyright (C) 2013-2014 Renesas Solutions Corp. |
| 6 | * Copyright (C) 2014 Cogent Embedded Inc. | ||
| 6 | * | 7 | * |
| 7 | * This file is licensed under the terms of the GNU General Public License | 8 | * This file is licensed under the terms of the GNU General Public License |
| 8 | * version 2. This program is licensed "as is" without any warranty of any | 9 | * version 2. This program is licensed "as is" without any warranty of any |
| @@ -19,6 +20,15 @@ | |||
| 19 | #address-cells = <2>; | 20 | #address-cells = <2>; |
| 20 | #size-cells = <2>; | 21 | #size-cells = <2>; |
| 21 | 22 | ||
| 23 | aliases { | ||
| 24 | i2c0 = &i2c0; | ||
| 25 | i2c1 = &i2c1; | ||
| 26 | i2c2 = &i2c2; | ||
| 27 | i2c3 = &i2c3; | ||
| 28 | i2c4 = &i2c4; | ||
| 29 | i2c5 = &i2c5; | ||
| 30 | }; | ||
| 31 | |||
| 22 | cpus { | 32 | cpus { |
| 23 | #address-cells = <1>; | 33 | #address-cells = <1>; |
| 24 | #size-cells = <0>; | 34 | #size-cells = <0>; |
| @@ -53,7 +63,6 @@ | |||
| 53 | gpio0: gpio@e6050000 { | 63 | gpio0: gpio@e6050000 { |
| 54 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; | 64 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
| 55 | reg = <0 0xe6050000 0 0x50>; | 65 | reg = <0 0xe6050000 0 0x50>; |
| 56 | interrupt-parent = <&gic>; | ||
| 57 | interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; | 66 | interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; |
| 58 | #gpio-cells = <2>; | 67 | #gpio-cells = <2>; |
| 59 | gpio-controller; | 68 | gpio-controller; |
| @@ -65,7 +74,6 @@ | |||
| 65 | gpio1: gpio@e6051000 { | 74 | gpio1: gpio@e6051000 { |
| 66 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; | 75 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
| 67 | reg = <0 0xe6051000 0 0x50>; | 76 | reg = <0 0xe6051000 0 0x50>; |
| 68 | interrupt-parent = <&gic>; | ||
| 69 | interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; | 77 | interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; |
| 70 | #gpio-cells = <2>; | 78 | #gpio-cells = <2>; |
| 71 | gpio-controller; | 79 | gpio-controller; |
| @@ -77,7 +85,6 @@ | |||
| 77 | gpio2: gpio@e6052000 { | 85 | gpio2: gpio@e6052000 { |
| 78 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; | 86 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
| 79 | reg = <0 0xe6052000 0 0x50>; | 87 | reg = <0 0xe6052000 0 0x50>; |
| 80 | interrupt-parent = <&gic>; | ||
| 81 | interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; | 88 | interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; |
| 82 | #gpio-cells = <2>; | 89 | #gpio-cells = <2>; |
| 83 | gpio-controller; | 90 | gpio-controller; |
| @@ -89,7 +96,6 @@ | |||
| 89 | gpio3: gpio@e6053000 { | 96 | gpio3: gpio@e6053000 { |
| 90 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; | 97 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
| 91 | reg = <0 0xe6053000 0 0x50>; | 98 | reg = <0 0xe6053000 0 0x50>; |
| 92 | interrupt-parent = <&gic>; | ||
| 93 | interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; | 99 | interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; |
| 94 | #gpio-cells = <2>; | 100 | #gpio-cells = <2>; |
| 95 | gpio-controller; | 101 | gpio-controller; |
| @@ -101,7 +107,6 @@ | |||
| 101 | gpio4: gpio@e6054000 { | 107 | gpio4: gpio@e6054000 { |
| 102 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; | 108 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
| 103 | reg = <0 0xe6054000 0 0x50>; | 109 | reg = <0 0xe6054000 0 0x50>; |
| 104 | interrupt-parent = <&gic>; | ||
| 105 | interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; | 110 | interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; |
| 106 | #gpio-cells = <2>; | 111 | #gpio-cells = <2>; |
| 107 | gpio-controller; | 112 | gpio-controller; |
| @@ -113,7 +118,6 @@ | |||
| 113 | gpio5: gpio@e6055000 { | 118 | gpio5: gpio@e6055000 { |
| 114 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; | 119 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
| 115 | reg = <0 0xe6055000 0 0x50>; | 120 | reg = <0 0xe6055000 0 0x50>; |
| 116 | interrupt-parent = <&gic>; | ||
| 117 | interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; | 121 | interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; |
| 118 | #gpio-cells = <2>; | 122 | #gpio-cells = <2>; |
| 119 | gpio-controller; | 123 | gpio-controller; |
| @@ -125,7 +129,6 @@ | |||
| 125 | gpio6: gpio@e6055400 { | 129 | gpio6: gpio@e6055400 { |
| 126 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; | 130 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
| 127 | reg = <0 0xe6055400 0 0x50>; | 131 | reg = <0 0xe6055400 0 0x50>; |
| 128 | interrupt-parent = <&gic>; | ||
| 129 | interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; | 132 | interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; |
| 130 | #gpio-cells = <2>; | 133 | #gpio-cells = <2>; |
| 131 | gpio-controller; | 134 | gpio-controller; |
| @@ -137,7 +140,6 @@ | |||
| 137 | gpio7: gpio@e6055800 { | 140 | gpio7: gpio@e6055800 { |
| 138 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; | 141 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
| 139 | reg = <0 0xe6055800 0 0x50>; | 142 | reg = <0 0xe6055800 0 0x50>; |
| 140 | interrupt-parent = <&gic>; | ||
| 141 | interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; | 143 | interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; |
| 142 | #gpio-cells = <2>; | 144 | #gpio-cells = <2>; |
| 143 | gpio-controller; | 145 | gpio-controller; |
| @@ -149,8 +151,8 @@ | |||
| 149 | thermal@e61f0000 { | 151 | thermal@e61f0000 { |
| 150 | compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal"; | 152 | compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal"; |
| 151 | reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; | 153 | reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; |
| 152 | interrupt-parent = <&gic>; | ||
| 153 | interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; | 154 | interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; |
| 155 | clocks = <&mstp5_clks R8A7791_CLK_THERMAL>; | ||
| 154 | }; | 156 | }; |
| 155 | 157 | ||
| 156 | timer { | 158 | timer { |
| @@ -166,7 +168,6 @@ | |||
| 166 | #interrupt-cells = <2>; | 168 | #interrupt-cells = <2>; |
| 167 | interrupt-controller; | 169 | interrupt-controller; |
| 168 | reg = <0 0xe61c0000 0 0x200>; | 170 | reg = <0 0xe61c0000 0 0x200>; |
| 169 | interrupt-parent = <&gic>; | ||
| 170 | interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, | 171 | interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, |
| 171 | <0 1 IRQ_TYPE_LEVEL_HIGH>, | 172 | <0 1 IRQ_TYPE_LEVEL_HIGH>, |
| 172 | <0 2 IRQ_TYPE_LEVEL_HIGH>, | 173 | <0 2 IRQ_TYPE_LEVEL_HIGH>, |
| @@ -179,12 +180,288 @@ | |||
| 179 | <0 17 IRQ_TYPE_LEVEL_HIGH>; | 180 | <0 17 IRQ_TYPE_LEVEL_HIGH>; |
| 180 | }; | 181 | }; |
| 181 | 182 | ||
| 183 | i2c0: i2c@e6508000 { | ||
| 184 | #address-cells = <1>; | ||
| 185 | #size-cells = <0>; | ||
| 186 | compatible = "renesas,i2c-r8a7791"; | ||
| 187 | reg = <0 0xe6508000 0 0x40>; | ||
| 188 | interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; | ||
| 189 | clocks = <&mstp9_clks R8A7791_CLK_I2C0>; | ||
| 190 | status = "disabled"; | ||
| 191 | }; | ||
| 192 | |||
| 193 | i2c1: i2c@e6518000 { | ||
| 194 | #address-cells = <1>; | ||
| 195 | #size-cells = <0>; | ||
| 196 | compatible = "renesas,i2c-r8a7791"; | ||
| 197 | reg = <0 0xe6518000 0 0x40>; | ||
| 198 | interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>; | ||
| 199 | clocks = <&mstp9_clks R8A7791_CLK_I2C1>; | ||
| 200 | status = "disabled"; | ||
| 201 | }; | ||
| 202 | |||
| 203 | i2c2: i2c@e6530000 { | ||
| 204 | #address-cells = <1>; | ||
| 205 | #size-cells = <0>; | ||
| 206 | compatible = "renesas,i2c-r8a7791"; | ||
| 207 | reg = <0 0xe6530000 0 0x40>; | ||
| 208 | interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>; | ||
| 209 | clocks = <&mstp9_clks R8A7791_CLK_I2C2>; | ||
| 210 | status = "disabled"; | ||
| 211 | }; | ||
| 212 | |||
| 213 | i2c3: i2c@e6540000 { | ||
| 214 | #address-cells = <1>; | ||
| 215 | #size-cells = <0>; | ||
| 216 | compatible = "renesas,i2c-r8a7791"; | ||
| 217 | reg = <0 0xe6540000 0 0x40>; | ||
| 218 | interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>; | ||
| 219 | clocks = <&mstp9_clks R8A7791_CLK_I2C3>; | ||
| 220 | status = "disabled"; | ||
| 221 | }; | ||
| 222 | |||
| 223 | i2c4: i2c@e6520000 { | ||
| 224 | #address-cells = <1>; | ||
| 225 | #size-cells = <0>; | ||
| 226 | compatible = "renesas,i2c-r8a7791"; | ||
| 227 | reg = <0 0xe6520000 0 0x40>; | ||
| 228 | interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; | ||
| 229 | clocks = <&mstp9_clks R8A7791_CLK_I2C4>; | ||
| 230 | status = "disabled"; | ||
| 231 | }; | ||
| 232 | |||
| 233 | i2c5: i2c@e6528000 { | ||
| 234 | #address-cells = <1>; | ||
| 235 | #size-cells = <0>; | ||
| 236 | compatible = "renesas,i2c-r8a7791"; | ||
| 237 | reg = <0 0xe6528000 0 0x40>; | ||
| 238 | interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; | ||
| 239 | clocks = <&mstp9_clks R8A7791_CLK_I2C5>; | ||
| 240 | status = "disabled"; | ||
| 241 | }; | ||
| 242 | |||
| 182 | pfc: pfc@e6060000 { | 243 | pfc: pfc@e6060000 { |
| 183 | compatible = "renesas,pfc-r8a7791"; | 244 | compatible = "renesas,pfc-r8a7791"; |
| 184 | reg = <0 0xe6060000 0 0x250>; | 245 | reg = <0 0xe6060000 0 0x250>; |
| 185 | #gpio-range-cells = <3>; | 246 | #gpio-range-cells = <3>; |
| 186 | }; | 247 | }; |
| 187 | 248 | ||
| 249 | sdhi0: sd@ee100000 { | ||
| 250 | compatible = "renesas,sdhi-r8a7791"; | ||
| 251 | reg = <0 0xee100000 0 0x200>; | ||
| 252 | interrupt-parent = <&gic>; | ||
| 253 | interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; | ||
| 254 | clocks = <&mstp3_clks R8A7791_CLK_SDHI0>; | ||
| 255 | status = "disabled"; | ||
| 256 | }; | ||
| 257 | |||
| 258 | sdhi1: sd@ee140000 { | ||
| 259 | compatible = "renesas,sdhi-r8a7791"; | ||
| 260 | reg = <0 0xee140000 0 0x100>; | ||
| 261 | interrupt-parent = <&gic>; | ||
| 262 | interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; | ||
| 263 | clocks = <&mstp3_clks R8A7791_CLK_SDHI1>; | ||
| 264 | status = "disabled"; | ||
| 265 | }; | ||
| 266 | |||
| 267 | sdhi2: sd@ee160000 { | ||
| 268 | compatible = "renesas,sdhi-r8a7791"; | ||
| 269 | reg = <0 0xee160000 0 0x100>; | ||
| 270 | interrupt-parent = <&gic>; | ||
| 271 | interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; | ||
| 272 | clocks = <&mstp3_clks R8A7791_CLK_SDHI2>; | ||
| 273 | status = "disabled"; | ||
| 274 | }; | ||
| 275 | |||
| 276 | scifa0: serial@e6c40000 { | ||
| 277 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | ||
| 278 | reg = <0 0xe6c40000 0 64>; | ||
| 279 | interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; | ||
| 280 | clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>; | ||
| 281 | clock-names = "sci_ick"; | ||
| 282 | status = "disabled"; | ||
| 283 | }; | ||
| 284 | |||
| 285 | scifa1: serial@e6c50000 { | ||
| 286 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | ||
| 287 | reg = <0 0xe6c50000 0 64>; | ||
| 288 | interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; | ||
| 289 | clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>; | ||
| 290 | clock-names = "sci_ick"; | ||
| 291 | status = "disabled"; | ||
| 292 | }; | ||
| 293 | |||
| 294 | scifa2: serial@e6c60000 { | ||
| 295 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | ||
| 296 | reg = <0 0xe6c60000 0 64>; | ||
| 297 | interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; | ||
| 298 | clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>; | ||
| 299 | clock-names = "sci_ick"; | ||
| 300 | status = "disabled"; | ||
| 301 | }; | ||
| 302 | |||
| 303 | scifa3: serial@e6c70000 { | ||
| 304 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | ||
| 305 | reg = <0 0xe6c70000 0 64>; | ||
| 306 | interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; | ||
| 307 | clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>; | ||
| 308 | clock-names = "sci_ick"; | ||
| 309 | status = "disabled"; | ||
| 310 | }; | ||
| 311 | |||
| 312 | scifa4: serial@e6c78000 { | ||
| 313 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | ||
| 314 | reg = <0 0xe6c78000 0 64>; | ||
| 315 | interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; | ||
| 316 | clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>; | ||
| 317 | clock-names = "sci_ick"; | ||
| 318 | status = "disabled"; | ||
| 319 | }; | ||
| 320 | |||
| 321 | scifa5: serial@e6c80000 { | ||
| 322 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | ||
| 323 | reg = <0 0xe6c80000 0 64>; | ||
| 324 | interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; | ||
| 325 | clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>; | ||
| 326 | clock-names = "sci_ick"; | ||
| 327 | status = "disabled"; | ||
| 328 | }; | ||
| 329 | |||
| 330 | scifb0: serial@e6c20000 { | ||
| 331 | compatible = "renesas,scifb-r8a7791", "renesas,scifb"; | ||
| 332 | reg = <0 0xe6c20000 0 64>; | ||
| 333 | interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; | ||
| 334 | clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>; | ||
| 335 | clock-names = "sci_ick"; | ||
| 336 | status = "disabled"; | ||
| 337 | }; | ||
| 338 | |||
| 339 | scifb1: serial@e6c30000 { | ||
| 340 | compatible = "renesas,scifb-r8a7791", "renesas,scifb"; | ||
| 341 | reg = <0 0xe6c30000 0 64>; | ||
| 342 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; | ||
| 343 | clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>; | ||
| 344 | clock-names = "sci_ick"; | ||
| 345 | status = "disabled"; | ||
| 346 | }; | ||
| 347 | |||
| 348 | scifb2: serial@e6ce0000 { | ||
| 349 | compatible = "renesas,scifb-r8a7791", "renesas,scifb"; | ||
| 350 | reg = <0 0xe6ce0000 0 64>; | ||
| 351 | interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; | ||
| 352 | clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>; | ||
| 353 | clock-names = "sci_ick"; | ||
| 354 | status = "disabled"; | ||
| 355 | }; | ||
| 356 | |||
| 357 | scif0: serial@e6e60000 { | ||
| 358 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | ||
| 359 | reg = <0 0xe6e60000 0 64>; | ||
| 360 | interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; | ||
| 361 | clocks = <&mstp7_clks R8A7791_CLK_SCIF0>; | ||
| 362 | clock-names = "sci_ick"; | ||
| 363 | status = "disabled"; | ||
| 364 | }; | ||
| 365 | |||
| 366 | scif1: serial@e6e68000 { | ||
| 367 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | ||
| 368 | reg = <0 0xe6e68000 0 64>; | ||
| 369 | interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; | ||
| 370 | clocks = <&mstp7_clks R8A7791_CLK_SCIF1>; | ||
| 371 | clock-names = "sci_ick"; | ||
| 372 | status = "disabled"; | ||
| 373 | }; | ||
| 374 | |||
| 375 | scif2: serial@e6e58000 { | ||
| 376 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | ||
| 377 | reg = <0 0xe6e58000 0 64>; | ||
| 378 | interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; | ||
| 379 | clocks = <&mstp7_clks R8A7791_CLK_SCIF2>; | ||
| 380 | clock-names = "sci_ick"; | ||
| 381 | status = "disabled"; | ||
| 382 | }; | ||
| 383 | |||
| 384 | scif3: serial@e6ea8000 { | ||
| 385 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | ||
| 386 | reg = <0 0xe6ea8000 0 64>; | ||
| 387 | interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; | ||
| 388 | clocks = <&mstp7_clks R8A7791_CLK_SCIF3>; | ||
| 389 | clock-names = "sci_ick"; | ||
| 390 | status = "disabled"; | ||
| 391 | }; | ||
| 392 | |||
| 393 | scif4: serial@e6ee0000 { | ||
| 394 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | ||
| 395 | reg = <0 0xe6ee0000 0 64>; | ||
| 396 | interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; | ||
| 397 | clocks = <&mstp7_clks R8A7791_CLK_SCIF4>; | ||
| 398 | clock-names = "sci_ick"; | ||
| 399 | status = "disabled"; | ||
| 400 | }; | ||
| 401 | |||
| 402 | scif5: serial@e6ee8000 { | ||
| 403 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | ||
| 404 | reg = <0 0xe6ee8000 0 64>; | ||
| 405 | interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; | ||
| 406 | clocks = <&mstp7_clks R8A7791_CLK_SCIF5>; | ||
| 407 | clock-names = "sci_ick"; | ||
| 408 | status = "disabled"; | ||
| 409 | }; | ||
| 410 | |||
| 411 | hscif0: serial@e62c0000 { | ||
| 412 | compatible = "renesas,hscif-r8a7791", "renesas,hscif"; | ||
| 413 | reg = <0 0xe62c0000 0 96>; | ||
| 414 | interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; | ||
| 415 | clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>; | ||
| 416 | clock-names = "sci_ick"; | ||
| 417 | status = "disabled"; | ||
| 418 | }; | ||
| 419 | |||
| 420 | hscif1: serial@e62c8000 { | ||
| 421 | compatible = "renesas,hscif-r8a7791", "renesas,hscif"; | ||
| 422 | reg = <0 0xe62c8000 0 96>; | ||
| 423 | interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; | ||
| 424 | clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>; | ||
| 425 | clock-names = "sci_ick"; | ||
| 426 | status = "disabled"; | ||
| 427 | }; | ||
| 428 | |||
| 429 | hscif2: serial@e62d0000 { | ||
| 430 | compatible = "renesas,hscif-r8a7791", "renesas,hscif"; | ||
| 431 | reg = <0 0xe62d0000 0 96>; | ||
| 432 | interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; | ||
| 433 | clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>; | ||
| 434 | clock-names = "sci_ick"; | ||
| 435 | status = "disabled"; | ||
| 436 | }; | ||
| 437 | |||
| 438 | ether: ethernet@ee700000 { | ||
| 439 | compatible = "renesas,ether-r8a7791"; | ||
| 440 | reg = <0 0xee700000 0 0x400>; | ||
| 441 | interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; | ||
| 442 | clocks = <&mstp8_clks R8A7791_CLK_ETHER>; | ||
| 443 | phy-mode = "rmii"; | ||
| 444 | #address-cells = <1>; | ||
| 445 | #size-cells = <0>; | ||
| 446 | status = "disabled"; | ||
| 447 | }; | ||
| 448 | |||
| 449 | sata0: sata@ee300000 { | ||
| 450 | compatible = "renesas,sata-r8a7791"; | ||
| 451 | reg = <0 0xee300000 0 0x2000>; | ||
| 452 | interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; | ||
| 453 | clocks = <&mstp8_clks R8A7791_CLK_SATA0>; | ||
| 454 | status = "disabled"; | ||
| 455 | }; | ||
| 456 | |||
| 457 | sata1: sata@ee500000 { | ||
| 458 | compatible = "renesas,sata-r8a7791"; | ||
| 459 | reg = <0 0xee500000 0 0x2000>; | ||
| 460 | interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; | ||
| 461 | clocks = <&mstp8_clks R8A7791_CLK_SATA1>; | ||
| 462 | status = "disabled"; | ||
| 463 | }; | ||
| 464 | |||
| 188 | clocks { | 465 | clocks { |
| 189 | #address-cells = <2>; | 466 | #address-cells = <2>; |
| 190 | #size-cells = <2>; | 467 | #size-cells = <2>; |
| @@ -474,10 +751,15 @@ | |||
| 474 | mstp8_clks: mstp8_clks@e6150990 { | 751 | mstp8_clks: mstp8_clks@e6150990 { |
| 475 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | 752 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 476 | reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; | 753 | reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; |
| 477 | clocks = <&p_clk>; | 754 | clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>, |
| 755 | <&zs_clk>; | ||
| 478 | #clock-cells = <1>; | 756 | #clock-cells = <1>; |
| 479 | renesas,clock-indices = <R8A7791_CLK_ETHER>; | 757 | renesas,clock-indices = < |
| 480 | clock-output-names = "ether"; | 758 | R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0 |
| 759 | R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0 | ||
| 760 | >; | ||
| 761 | clock-output-names = | ||
| 762 | "vin2", "vin1", "vin0", "ether", "sata1", "sata0"; | ||
| 481 | }; | 763 | }; |
| 482 | mstp9_clks: mstp9_clks@e6150994 { | 764 | mstp9_clks: mstp9_clks@e6150994 { |
| 483 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | 765 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| @@ -488,7 +770,7 @@ | |||
| 488 | #clock-cells = <1>; | 770 | #clock-cells = <1>; |
| 489 | renesas,clock-indices = < | 771 | renesas,clock-indices = < |
| 490 | R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD | 772 | R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD |
| 491 | R8A7791_CLK_I2C4 R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 | 773 | R8A7791_CLK_I2C5 R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 |
| 492 | R8A7791_CLK_I2C2 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0 | 774 | R8A7791_CLK_I2C2 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0 |
| 493 | >; | 775 | >; |
| 494 | clock-output-names = | 776 | clock-output-names = |
| @@ -506,4 +788,15 @@ | |||
| 506 | clock-output-names = "scifa3", "scifa4", "scifa5"; | 788 | clock-output-names = "scifa3", "scifa4", "scifa5"; |
| 507 | }; | 789 | }; |
| 508 | }; | 790 | }; |
| 791 | |||
| 792 | spi: spi@e6b10000 { | ||
| 793 | compatible = "renesas,qspi-r8a7791", "renesas,qspi"; | ||
| 794 | reg = <0 0xe6b10000 0 0x2c>; | ||
| 795 | interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; | ||
| 796 | clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>; | ||
| 797 | num-cs = <1>; | ||
| 798 | #address-cells = <1>; | ||
| 799 | #size-cells = <0>; | ||
| 800 | status = "disabled"; | ||
| 801 | }; | ||
| 509 | }; | 802 | }; |
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 3d5faf85f51b..eabcfdbb403a 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi | |||
| @@ -239,7 +239,9 @@ | |||
| 239 | }; | 239 | }; |
| 240 | 240 | ||
| 241 | adc0: adc@f8018000 { | 241 | adc0: adc@f8018000 { |
| 242 | compatible = "atmel,at91sam9260-adc"; | 242 | #address-cells = <1>; |
| 243 | #size-cells = <0>; | ||
| 244 | compatible = "atmel,at91sam9x5-adc"; | ||
| 243 | reg = <0xf8018000 0x100>; | 245 | reg = <0xf8018000 0x100>; |
| 244 | interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; | 246 | interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; |
| 245 | pinctrl-names = "default"; | 247 | pinctrl-names = "default"; |
| @@ -261,52 +263,39 @@ | |||
| 261 | clocks = <&adc_clk>, | 263 | clocks = <&adc_clk>, |
| 262 | <&adc_op_clk>; | 264 | <&adc_op_clk>; |
| 263 | clock-names = "adc_clk", "adc_op_clk"; | 265 | clock-names = "adc_clk", "adc_op_clk"; |
| 264 | atmel,adc-channel-base = <0x50>; | ||
| 265 | atmel,adc-channels-used = <0xfff>; | 266 | atmel,adc-channels-used = <0xfff>; |
| 266 | atmel,adc-drdy-mask = <0x1000000>; | ||
| 267 | atmel,adc-num-channels = <12>; | ||
| 268 | atmel,adc-startup-time = <40>; | 267 | atmel,adc-startup-time = <40>; |
| 269 | atmel,adc-status-register = <0x30>; | 268 | atmel,adc-use-external-triggers; |
| 270 | atmel,adc-trigger-register = <0xc0>; | ||
| 271 | atmel,adc-use-external; | ||
| 272 | atmel,adc-vref = <3000>; | 269 | atmel,adc-vref = <3000>; |
| 273 | atmel,adc-res = <10 12>; | 270 | atmel,adc-res = <10 12>; |
| 274 | atmel,adc-res-names = "lowres", "highres"; | 271 | atmel,adc-res-names = "lowres", "highres"; |
| 275 | status = "disabled"; | 272 | status = "disabled"; |
| 276 | 273 | ||
| 277 | trigger@0 { | 274 | trigger@0 { |
| 275 | reg = <0>; | ||
| 278 | trigger-name = "external-rising"; | 276 | trigger-name = "external-rising"; |
| 279 | trigger-value = <0x1>; | 277 | trigger-value = <0x1>; |
| 280 | trigger-external; | 278 | trigger-external; |
| 281 | }; | 279 | }; |
| 282 | trigger@1 { | 280 | trigger@1 { |
| 281 | reg = <1>; | ||
| 283 | trigger-name = "external-falling"; | 282 | trigger-name = "external-falling"; |
| 284 | trigger-value = <0x2>; | 283 | trigger-value = <0x2>; |
| 285 | trigger-external; | 284 | trigger-external; |
| 286 | }; | 285 | }; |
| 287 | trigger@2 { | 286 | trigger@2 { |
| 287 | reg = <2>; | ||
| 288 | trigger-name = "external-any"; | 288 | trigger-name = "external-any"; |
| 289 | trigger-value = <0x3>; | 289 | trigger-value = <0x3>; |
| 290 | trigger-external; | 290 | trigger-external; |
| 291 | }; | 291 | }; |
| 292 | trigger@3 { | 292 | trigger@3 { |
| 293 | reg = <3>; | ||
| 293 | trigger-name = "continuous"; | 294 | trigger-name = "continuous"; |
| 294 | trigger-value = <0x6>; | 295 | trigger-value = <0x6>; |
| 295 | }; | 296 | }; |
| 296 | }; | 297 | }; |
| 297 | 298 | ||
| 298 | tsadcc: tsadcc@f8018000 { | ||
| 299 | compatible = "atmel,at91sam9x5-tsadcc"; | ||
| 300 | reg = <0xf8018000 0x4000>; | ||
| 301 | interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; | ||
| 302 | atmel,tsadcc_clock = <300000>; | ||
| 303 | atmel,filtering_average = <0x03>; | ||
| 304 | atmel,pendet_debounce = <0x08>; | ||
| 305 | atmel,pendet_sensitivity = <0x02>; | ||
| 306 | atmel,ts_sample_hold_time = <0x0a>; | ||
| 307 | status = "disabled"; | ||
| 308 | }; | ||
| 309 | |||
| 310 | i2c2: i2c@f801c000 { | 299 | i2c2: i2c@f801c000 { |
| 311 | compatible = "atmel,at91sam9x5-i2c"; | 300 | compatible = "atmel,at91sam9x5-i2c"; |
| 312 | reg = <0xf801c000 0x4000>; | 301 | reg = <0xf801c000 0x4000>; |
| @@ -1256,6 +1245,7 @@ | |||
| 1256 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; | 1245 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; |
| 1257 | atmel,nand-addr-offset = <21>; | 1246 | atmel,nand-addr-offset = <21>; |
| 1258 | atmel,nand-cmd-offset = <22>; | 1247 | atmel,nand-cmd-offset = <22>; |
| 1248 | atmel,nand-has-dma; | ||
| 1259 | pinctrl-names = "default"; | 1249 | pinctrl-names = "default"; |
| 1260 | pinctrl-0 = <&pinctrl_nand0_ale_cle>; | 1250 | pinctrl-0 = <&pinctrl_nand0_ale_cle>; |
| 1261 | atmel,pmecc-lookup-table-offset = <0x0 0x8000>; | 1251 | atmel,pmecc-lookup-table-offset = <0x0 0x8000>; |
diff --git a/arch/arm/boot/dts/sama5d3xdm.dtsi b/arch/arm/boot/dts/sama5d3xdm.dtsi index f9bdde542ced..035ab72b3990 100644 --- a/arch/arm/boot/dts/sama5d3xdm.dtsi +++ b/arch/arm/boot/dts/sama5d3xdm.dtsi | |||
| @@ -23,10 +23,8 @@ | |||
| 23 | }; | 23 | }; |
| 24 | 24 | ||
| 25 | adc0: adc@f8018000 { | 25 | adc0: adc@f8018000 { |
| 26 | status = "disabled"; | 26 | atmel,adc-ts-wires = <4>; |
| 27 | }; | 27 | atmel,adc-ts-pressure-threshold = <10000>; |
| 28 | |||
| 29 | tsadcc: tsadcc@f8018000 { | ||
| 30 | status = "okay"; | 28 | status = "okay"; |
| 31 | }; | 29 | }; |
| 32 | 30 | ||
diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index e0853ea02df2..e41eedca3ce3 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi | |||
| @@ -705,7 +705,7 @@ | |||
| 705 | #address-cells = <1>; | 705 | #address-cells = <1>; |
| 706 | #size-cells = <0>; | 706 | #size-cells = <0>; |
| 707 | clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>; | 707 | clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>; |
| 708 | clock-names = "ssp0clk", "apb_pclk"; | 708 | clock-names = "SSPCLK", "apb_pclk"; |
| 709 | dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */ | 709 | dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */ |
| 710 | <&dma 8 0 0x0>; /* Logical - MemToDev */ | 710 | <&dma 8 0 0x0>; /* Logical - MemToDev */ |
| 711 | dma-names = "rx", "tx"; | 711 | dma-names = "rx", "tx"; |
| @@ -718,7 +718,7 @@ | |||
| 718 | #address-cells = <1>; | 718 | #address-cells = <1>; |
| 719 | #size-cells = <0>; | 719 | #size-cells = <0>; |
| 720 | clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>; | 720 | clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>; |
| 721 | clock-names = "ssp1clk", "apb_pclk"; | 721 | clock-names = "SSPCLK", "apb_pclk"; |
| 722 | dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */ | 722 | dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */ |
| 723 | <&dma 9 0 0x0>; /* Logical - MemToDev */ | 723 | <&dma 9 0 0x0>; /* Logical - MemToDev */ |
| 724 | dma-names = "rx", "tx"; | 724 | dma-names = "rx", "tx"; |
| @@ -732,7 +732,7 @@ | |||
| 732 | #size-cells = <0>; | 732 | #size-cells = <0>; |
| 733 | /* Same clock wired to kernel and pclk */ | 733 | /* Same clock wired to kernel and pclk */ |
| 734 | clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>; | 734 | clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>; |
| 735 | clock-names = "spi0clk", "apb_pclk"; | 735 | clock-names = "SSPCLK", "apb_pclk"; |
| 736 | dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */ | 736 | dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */ |
| 737 | <&dma 0 0 0x0>; /* Logical - MemToDev */ | 737 | <&dma 0 0 0x0>; /* Logical - MemToDev */ |
| 738 | dma-names = "rx", "tx"; | 738 | dma-names = "rx", "tx"; |
| @@ -746,7 +746,7 @@ | |||
| 746 | #size-cells = <0>; | 746 | #size-cells = <0>; |
| 747 | /* Same clock wired to kernel and pclk */ | 747 | /* Same clock wired to kernel and pclk */ |
| 748 | clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>; | 748 | clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>; |
| 749 | clock-names = "spi1clk", "apb_pclk"; | 749 | clock-names = "SSPCLK", "apb_pclk"; |
| 750 | dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */ | 750 | dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */ |
| 751 | <&dma 35 0 0x0>; /* Logical - MemToDev */ | 751 | <&dma 35 0 0x0>; /* Logical - MemToDev */ |
| 752 | dma-names = "rx", "tx"; | 752 | dma-names = "rx", "tx"; |
| @@ -760,7 +760,7 @@ | |||
| 760 | #size-cells = <0>; | 760 | #size-cells = <0>; |
| 761 | /* Same clock wired to kernel and pclk */ | 761 | /* Same clock wired to kernel and pclk */ |
| 762 | clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>; | 762 | clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>; |
| 763 | clock-names = "spi2clk", "apb_pclk"; | 763 | clock-names = "SSPCLK", "apb_pclk"; |
| 764 | dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */ | 764 | dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */ |
| 765 | <&dma 33 0 0x0>; /* Logical - MemToDev */ | 765 | <&dma 33 0 0x0>; /* Logical - MemToDev */ |
| 766 | dma-names = "rx", "tx"; | 766 | dma-names = "rx", "tx"; |
| @@ -774,7 +774,7 @@ | |||
| 774 | #size-cells = <0>; | 774 | #size-cells = <0>; |
| 775 | /* Same clock wired to kernel and pclk */ | 775 | /* Same clock wired to kernel and pclk */ |
| 776 | clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>; | 776 | clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>; |
| 777 | clock-names = "spi3clk", "apb_pclk"; | 777 | clock-names = "SSPCLK", "apb_pclk"; |
| 778 | dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */ | 778 | dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */ |
| 779 | <&dma 40 0 0x0>; /* Logical - MemToDev */ | 779 | <&dma 40 0 0x0>; /* Logical - MemToDev */ |
| 780 | dma-names = "rx", "tx"; | 780 | dma-names = "rx", "tx"; |
diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi new file mode 100644 index 000000000000..30f8601da323 --- /dev/null +++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi | |||
| @@ -0,0 +1,428 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2014 Linaro Ltd. | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | / { | ||
| 13 | soc { | ||
| 14 | prcmu@80157000 { | ||
| 15 | ab8500 { | ||
| 16 | ab8500-gpio { | ||
| 17 | /* Hog a few default settings */ | ||
| 18 | pinctrl-names = "default"; | ||
| 19 | pinctrl-0 = <&gpio2_default_mode>, | ||
| 20 | <&gpio4_default_mode>, | ||
| 21 | <&gpio10_default_mode>, | ||
| 22 | <&gpio11_default_mode>, | ||
| 23 | <&gpio12_default_mode>, | ||
| 24 | <&gpio13_default_mode>, | ||
| 25 | <&gpio16_default_mode>, | ||
| 26 | <&gpio24_default_mode>, | ||
| 27 | <&gpio25_default_mode>, | ||
| 28 | <&gpio36_default_mode>, | ||
| 29 | <&gpio37_default_mode>, | ||
| 30 | <&gpio38_default_mode>, | ||
| 31 | <&gpio39_default_mode>, | ||
| 32 | <&gpio42_default_mode>, | ||
| 33 | <&gpio26_default_mode>, | ||
| 34 | <&gpio35_default_mode>, | ||
| 35 | <&ycbcr_default_mode>, | ||
| 36 | <&pwm_default_mode>, | ||
| 37 | <&adi1_default_mode>, | ||
| 38 | <&usbuicc_default_mode>, | ||
| 39 | <&dmic_default_mode>, | ||
| 40 | <&extcpena_default_mode>, | ||
| 41 | <&modsclsda_default_mode>; | ||
| 42 | |||
| 43 | /* | ||
| 44 | * Pins 2, 4, 10, 11, 12, 13, 16, 24, 25, 36, 37, 38, 39 and 42 | ||
| 45 | * are muxed in as GPIO, and configured as INPUT PULL DOWN | ||
| 46 | */ | ||
| 47 | gpio2 { | ||
| 48 | gpio2_default_mode: gpio2_default { | ||
| 49 | default_mux { | ||
| 50 | ste,function = "gpio"; | ||
| 51 | ste,pins = "gpio2_a_1"; | ||
| 52 | }; | ||
| 53 | default_cfg { | ||
| 54 | ste,pins = "GPIO2_T9"; | ||
| 55 | input-enable; | ||
| 56 | bias-pull-down; | ||
| 57 | }; | ||
| 58 | }; | ||
| 59 | }; | ||
| 60 | gpio4 { | ||
| 61 | gpio4_default_mode: gpio4_default { | ||
| 62 | default_mux { | ||
| 63 | ste,function = "gpio"; | ||
| 64 | ste,pins = "gpio4_a_1"; | ||
| 65 | }; | ||
| 66 | default_cfg { | ||
| 67 | ste,pins = "GPIO4_W2"; | ||
| 68 | input-enable; | ||
| 69 | bias-pull-down; | ||
| 70 | }; | ||
| 71 | }; | ||
| 72 | }; | ||
| 73 | gpio10 { | ||
| 74 | gpio10_default_mode: gpio10_default { | ||
| 75 | default_mux { | ||
| 76 | ste,function = "gpio"; | ||
| 77 | ste,pins = "gpio10_d_1"; | ||
| 78 | }; | ||
| 79 | default_cfg { | ||
| 80 | ste,pins = "GPIO10_U17"; | ||
| 81 | input-enable; | ||
| 82 | bias-pull-down; | ||
| 83 | }; | ||
| 84 | }; | ||
| 85 | }; | ||
| 86 | gpio11 { | ||
| 87 | gpio11_default_mode: gpio11_default { | ||
| 88 | default_mux { | ||
| 89 | ste,function = "gpio"; | ||
| 90 | ste,pins = "gpio11_d_1"; | ||
| 91 | }; | ||
| 92 | default_cfg { | ||
| 93 | ste,pins = "GPIO11_AA18"; | ||
| 94 | input-enable; | ||
| 95 | bias-pull-down; | ||
| 96 | }; | ||
| 97 | }; | ||
| 98 | }; | ||
| 99 | gpio12 { | ||
| 100 | gpio12_default_mode: gpio12_default { | ||
| 101 | default_mux { | ||
| 102 | ste,function = "gpio"; | ||
| 103 | ste,pins = "gpio12_d_1"; | ||
| 104 | }; | ||
| 105 | default_cfg { | ||
| 106 | ste,pins = "GPIO12_U16"; | ||
| 107 | input-enable; | ||
| 108 | bias-pull-down; | ||
| 109 | }; | ||
| 110 | }; | ||
| 111 | }; | ||
| 112 | gpio13 { | ||
| 113 | gpio13_default_mode: gpio13_default { | ||
| 114 | default_mux { | ||
| 115 | ste,function = "gpio"; | ||
| 116 | ste,pins = "gpio13_d_1"; | ||
| 117 | }; | ||
| 118 | default_cfg { | ||
| 119 | ste,pins = "GPIO13_W17"; | ||
| 120 | input-enable; | ||
| 121 | bias-pull-down; | ||
| 122 | }; | ||
| 123 | }; | ||
| 124 | }; | ||
| 125 | gpio16 { | ||
| 126 | gpio16_default_mode: gpio16_default { | ||
| 127 | default_mux { | ||
| 128 | ste,function = "gpio"; | ||
| 129 | ste,pins = "gpio16_a_1"; | ||
| 130 | }; | ||
| 131 | default_cfg { | ||
| 132 | ste,pins = "GPIO16_F15"; | ||
| 133 | input-enable; | ||
| 134 | bias-pull-down; | ||
| 135 | }; | ||
| 136 | }; | ||
| 137 | }; | ||
| 138 | gpio24 { | ||
| 139 | gpio24_default_mode: gpio24_default { | ||
| 140 | default_mux { | ||
| 141 | ste,function = "gpio"; | ||
| 142 | ste,pins = "gpio24_a_1"; | ||
| 143 | }; | ||
| 144 | default_cfg { | ||
| 145 | ste,pins = "GPIO24_T14"; | ||
| 146 | input-enable; | ||
| 147 | bias-pull-down; | ||
| 148 | }; | ||
| 149 | }; | ||
| 150 | }; | ||
| 151 | gpio25 { | ||
| 152 | gpio25_default_mode: gpio25_default { | ||
| 153 | default_mux { | ||
| 154 | ste,function = "gpio"; | ||
| 155 | ste,pins = "gpio25_a_1"; | ||
| 156 | }; | ||
| 157 | default_cfg { | ||
| 158 | ste,pins = "GPIO25_R16"; | ||
| 159 | input-enable; | ||
| 160 | bias-pull-down; | ||
| 161 | }; | ||
| 162 | }; | ||
| 163 | }; | ||
| 164 | gpio36 { | ||
| 165 | gpio36_default_mode: gpio36_default { | ||
| 166 | default_mux { | ||
| 167 | ste,function = "gpio"; | ||
| 168 | ste,pins = "gpio36_a_1"; | ||
| 169 | }; | ||
| 170 | default_cfg { | ||
| 171 | ste,pins = "GPIO36_A17"; | ||
| 172 | input-enable; | ||
| 173 | bias-pull-down; | ||
| 174 | }; | ||
| 175 | }; | ||
| 176 | }; | ||
| 177 | gpio37 { | ||
| 178 | gpio37_default_mode: gpio37_default { | ||
| 179 | default_mux { | ||
| 180 | ste,function = "gpio"; | ||
| 181 | ste,pins = "gpio37_a_1"; | ||
| 182 | }; | ||
| 183 | default_cfg { | ||
| 184 | ste,pins = "GPIO37_E15"; | ||
| 185 | input-enable; | ||
| 186 | bias-pull-down; | ||
| 187 | }; | ||
| 188 | }; | ||
| 189 | }; | ||
| 190 | gpio38 { | ||
| 191 | gpio38_default_mode: gpio38_default { | ||
| 192 | default_mux { | ||
| 193 | ste,function = "gpio"; | ||
| 194 | ste,pins = "gpio38_a_1"; | ||
| 195 | }; | ||
| 196 | default_cfg { | ||
| 197 | ste,pins = "GPIO38_C17"; | ||
| 198 | input-enable; | ||
| 199 | bias-pull-down; | ||
| 200 | }; | ||
| 201 | }; | ||
| 202 | }; | ||
| 203 | gpio39 { | ||
| 204 | gpio39_default_mode: gpio39_default { | ||
| 205 | default_mux { | ||
| 206 | ste,function = "gpio"; | ||
| 207 | ste,pins = "gpio39_a_1"; | ||
| 208 | }; | ||
| 209 | default_cfg { | ||
| 210 | ste,pins = "GPIO39_E16"; | ||
| 211 | input-enable; | ||
| 212 | bias-pull-down; | ||
| 213 | }; | ||
| 214 | }; | ||
| 215 | }; | ||
| 216 | gpio42 { | ||
| 217 | gpio42_default_mode: gpio42_default { | ||
| 218 | default_mux { | ||
| 219 | ste,function = "gpio"; | ||
| 220 | ste,pins = "gpio42_a_1"; | ||
| 221 | }; | ||
| 222 | default_cfg { | ||
| 223 | ste,pins = "GPIO42_U2"; | ||
| 224 | input-enable; | ||
| 225 | bias-pull-down; | ||
| 226 | }; | ||
| 227 | }; | ||
| 228 | }; | ||
| 229 | /* | ||
| 230 | * Pins 26 and 35 muxed in as GPIO, and configured as OUTPUT LOW | ||
| 231 | */ | ||
| 232 | gpio26 { | ||
| 233 | gpio26_default_mode: gpio26_default { | ||
| 234 | default_mux { | ||
| 235 | ste,function = "gpio"; | ||
| 236 | ste,pins = "gpio26_d_1"; | ||
| 237 | }; | ||
| 238 | default_cfg { | ||
| 239 | ste,pins = "GPIO26_M16"; | ||
| 240 | output-low; | ||
| 241 | }; | ||
| 242 | }; | ||
| 243 | }; | ||
| 244 | gpio35 { | ||
| 245 | gpio35_default_mode: gpio35_default { | ||
| 246 | default_mux { | ||
| 247 | ste,function = "gpio"; | ||
| 248 | ste,pins = "gpio35_d_1"; | ||
| 249 | }; | ||
| 250 | default_cfg { | ||
| 251 | ste,pins = "GPIO35_W15"; | ||
| 252 | output-low; | ||
| 253 | }; | ||
| 254 | }; | ||
| 255 | }; | ||
| 256 | /* | ||
| 257 | * This sets up the YCBCR connector pins, i.e. analog video out. | ||
| 258 | * Set as input with no bias. | ||
| 259 | */ | ||
| 260 | ycbcr { | ||
| 261 | ycbcr_default_mode: ycbcr_default { | ||
| 262 | default_mux { | ||
| 263 | ste,function = "ycbcr"; | ||
| 264 | ste,pins = "ycbcr0123_d_1"; | ||
| 265 | }; | ||
| 266 | default_cfg { | ||
| 267 | ste,pins = "GPIO6_Y18", | ||
| 268 | "GPIO7_AA20", | ||
| 269 | "GPIO8_W18", | ||
| 270 | "GPIO9_AA19"; | ||
| 271 | input-enable; | ||
| 272 | bias-disable; | ||
| 273 | }; | ||
| 274 | }; | ||
| 275 | }; | ||
| 276 | /* This sets up the PWM pins 14 and 15 */ | ||
| 277 | pwm { | ||
| 278 | pwm_default_mode: pwm_default { | ||
| 279 | default_mux { | ||
| 280 | ste,function = "pwmout"; | ||
| 281 | ste,pins = "pwmout1_d_1", "pwmout2_d_1"; | ||
| 282 | }; | ||
| 283 | default_cfg { | ||
| 284 | ste,pins = "GPIO14_F14", | ||
| 285 | "GPIO15_B17"; | ||
| 286 | input-enable; | ||
| 287 | bias-pull-down; | ||
| 288 | }; | ||
| 289 | }; | ||
| 290 | }; | ||
| 291 | /* This sets up audio interface 1 */ | ||
| 292 | adi1 { | ||
| 293 | adi1_default_mode: adi1_default { | ||
| 294 | default_mux { | ||
| 295 | ste,function = "adi1"; | ||
| 296 | ste,pins = "adi1_d_1"; | ||
| 297 | }; | ||
| 298 | default_cfg { | ||
| 299 | ste,pins = "GPIO17_P5", | ||
| 300 | "GPIO18_R5", | ||
| 301 | "GPIO19_U5", | ||
| 302 | "GPIO20_T5"; | ||
| 303 | input-enable; | ||
| 304 | bias-pull-down; | ||
| 305 | }; | ||
| 306 | }; | ||
| 307 | }; | ||
| 308 | /* This sets up the USB UICC pins */ | ||
| 309 | usbuicc { | ||
| 310 | usbuicc_default_mode: usbuicc_default { | ||
| 311 | default_mux { | ||
| 312 | ste,function = "usbuicc"; | ||
| 313 | ste,pins = "usbuicc_d_1"; | ||
| 314 | }; | ||
| 315 | default_cfg { | ||
| 316 | ste,pins = "GPIO21_H19", | ||
| 317 | "GPIO22_G20", | ||
| 318 | "GPIO23_G19"; | ||
| 319 | input-enable; | ||
| 320 | bias-pull-down; | ||
| 321 | }; | ||
| 322 | }; | ||
| 323 | }; | ||
| 324 | /* This sets up the microphone pins */ | ||
| 325 | dmic { | ||
| 326 | dmic_default_mode: dmic_default { | ||
| 327 | default_mux { | ||
| 328 | ste,function = "dmic"; | ||
| 329 | ste,pins = "dmic12_d_1", | ||
| 330 | "dmic34_d_1", | ||
| 331 | "dmic56_d_1"; | ||
| 332 | }; | ||
| 333 | default_cfg { | ||
| 334 | ste,pins = "GPIO27_J6", | ||
| 335 | "GPIO28_K6", | ||
| 336 | "GPIO29_G6", | ||
| 337 | "GPIO30_H6", | ||
| 338 | "GPIO31_F5", | ||
| 339 | "GPIO32_G5"; | ||
| 340 | input-enable; | ||
| 341 | bias-pull-down; | ||
| 342 | }; | ||
| 343 | }; | ||
| 344 | }; | ||
| 345 | extcpena { | ||
| 346 | extcpena_default_mode: extcpena_default { | ||
| 347 | default_mux { | ||
| 348 | ste,function = "extcpena"; | ||
| 349 | ste,pins = "extcpena_d_1"; | ||
| 350 | }; | ||
| 351 | default_cfg { | ||
| 352 | ste,pins = "GPIO34_R17"; | ||
| 353 | input-enable; | ||
| 354 | bias-pull-down; | ||
| 355 | }; | ||
| 356 | }; | ||
| 357 | }; | ||
| 358 | /* Modem I2C setup (SCL and SDA pins) */ | ||
| 359 | modsclsda { | ||
| 360 | modsclsda_default_mode: modsclsda_default { | ||
| 361 | default_mux { | ||
| 362 | ste,function = "modsclsda"; | ||
| 363 | ste,pins = "modsclsda_d_1"; | ||
| 364 | }; | ||
| 365 | default_cfg { | ||
| 366 | ste,pins = "GPIO40_T19", | ||
| 367 | "GPIO41_U19"; | ||
| 368 | input-enable; | ||
| 369 | bias-pull-down; | ||
| 370 | }; | ||
| 371 | }; | ||
| 372 | }; | ||
| 373 | /* | ||
| 374 | * Clock output pins associated with regulators. | ||
| 375 | */ | ||
| 376 | sysclkreq2 { | ||
| 377 | sysclkreq2_default_mode: sysclkreq2_default { | ||
| 378 | default_mux { | ||
| 379 | ste,function = "sysclkreq"; | ||
| 380 | ste,pins = "sysclkreq2_d_1"; | ||
| 381 | }; | ||
| 382 | default_cfg { | ||
| 383 | ste,pins = "GPIO1_T10"; | ||
| 384 | input-enable; | ||
| 385 | bias-disable; | ||
| 386 | }; | ||
| 387 | }; | ||
| 388 | sysclkreq2_sleep_mode: sysclkreq2_sleep { | ||
| 389 | default_mux { | ||
| 390 | ste,function = "gpio"; | ||
| 391 | ste,pins = "gpio1_a_1"; | ||
| 392 | }; | ||
| 393 | default_cfg { | ||
| 394 | ste,pins = "GPIO1_T10"; | ||
| 395 | input-enable; | ||
| 396 | bias-pull-down; | ||
| 397 | }; | ||
| 398 | }; | ||
| 399 | }; | ||
| 400 | sysclkreq4 { | ||
| 401 | sysclkreq4_default_mode: sysclkreq4_default { | ||
| 402 | default_mux { | ||
| 403 | ste,function = "sysclkreq"; | ||
| 404 | ste,pins = "sysclkreq4_d_1"; | ||
| 405 | }; | ||
| 406 | default_cfg { | ||
| 407 | ste,pins = "GPIO3_U9"; | ||
| 408 | input-enable; | ||
| 409 | bias-disable; | ||
| 410 | }; | ||
| 411 | }; | ||
| 412 | sysclkreq4_sleep_mode: sysclkreq4_sleep { | ||
| 413 | default_mux { | ||
| 414 | ste,function = "gpio"; | ||
| 415 | ste,pins = "gpio3_a_1"; | ||
| 416 | }; | ||
| 417 | default_cfg { | ||
| 418 | ste,pins = "GPIO3_U9"; | ||
| 419 | input-enable; | ||
| 420 | bias-pull-down; | ||
| 421 | }; | ||
| 422 | }; | ||
| 423 | }; | ||
| 424 | }; | ||
| 425 | }; | ||
| 426 | }; | ||
| 427 | }; | ||
| 428 | }; | ||
diff --git a/arch/arm/boot/dts/ste-href-ab8505.dtsi b/arch/arm/boot/dts/ste-href-ab8505.dtsi new file mode 100644 index 000000000000..6006d62086a2 --- /dev/null +++ b/arch/arm/boot/dts/ste-href-ab8505.dtsi | |||
| @@ -0,0 +1,240 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2014 Linaro Ltd. | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | / { | ||
| 13 | soc { | ||
| 14 | prcmu@80157000 { | ||
| 15 | ab8505 { | ||
| 16 | ab8505-gpio { | ||
| 17 | /* Hog a few default settings */ | ||
| 18 | pinctrl-names = "default"; | ||
| 19 | pinctrl-0 = <&gpio2_default_mode>, | ||
| 20 | <&gpio10_default_mode>, | ||
| 21 | <&gpio11_default_mode>, | ||
| 22 | <&gpio13_default_mode>, | ||
| 23 | <&gpio34_default_mode>, | ||
| 24 | <&gpio50_default_mode>, | ||
| 25 | <&pwm_default_mode>, | ||
| 26 | <&adi2_default_mode>, | ||
| 27 | <&modsclsda_default_mode>, | ||
| 28 | <&resethw_default_mode>, | ||
| 29 | <&service_default_mode>; | ||
| 30 | |||
| 31 | /* | ||
| 32 | * Pins 2, 10, 11, 13, 34 and 50 | ||
| 33 | * are muxed in as GPIO, and configured as INPUT PULL DOWN | ||
| 34 | */ | ||
| 35 | gpio2 { | ||
| 36 | gpio2_default_mode: gpio2_default { | ||
| 37 | default_mux { | ||
| 38 | ste,function = "gpio"; | ||
| 39 | ste,pins = "gpio2_a_1"; | ||
| 40 | }; | ||
| 41 | default_cfg { | ||
| 42 | ste,pins = "GPIO2_R5"; | ||
| 43 | input-enable; | ||
| 44 | bias-pull-down; | ||
| 45 | }; | ||
| 46 | }; | ||
| 47 | }; | ||
| 48 | gpio10 { | ||
| 49 | gpio10_default_mode: gpio10_default { | ||
| 50 | default_mux { | ||
| 51 | ste,function = "gpio"; | ||
| 52 | ste,pins = "gpio10_d_1"; | ||
| 53 | }; | ||
| 54 | default_cfg { | ||
| 55 | ste,pins = "GPIO10_B16"; | ||
| 56 | input-enable; | ||
| 57 | bias-pull-down; | ||
| 58 | }; | ||
| 59 | }; | ||
| 60 | }; | ||
| 61 | gpio11 { | ||
| 62 | gpio11_default_mode: gpio11_default { | ||
| 63 | default_mux { | ||
| 64 | ste,function = "gpio"; | ||
| 65 | ste,pins = "gpio11_d_1"; | ||
| 66 | }; | ||
| 67 | default_cfg { | ||
| 68 | ste,pins = "GPIO11_B17"; | ||
| 69 | input-enable; | ||
| 70 | bias-pull-down; | ||
| 71 | }; | ||
| 72 | }; | ||
| 73 | }; | ||
| 74 | gpio13 { | ||
| 75 | gpio13_default_mode: gpio13_default { | ||
| 76 | default_mux { | ||
| 77 | ste,function = "gpio"; | ||
| 78 | ste,pins = "gpio13_d_1"; | ||
| 79 | }; | ||
| 80 | default_cfg { | ||
| 81 | ste,pins = "GPIO13_D17"; | ||
| 82 | input-enable; | ||
| 83 | bias-disable; | ||
| 84 | }; | ||
| 85 | }; | ||
| 86 | }; | ||
| 87 | gpio34 { | ||
| 88 | gpio34_default_mode: gpio34_default { | ||
| 89 | default_mux { | ||
| 90 | ste,function = "gpio"; | ||
| 91 | ste,pins = "gpio34_a_1"; | ||
| 92 | }; | ||
| 93 | default_cfg { | ||
| 94 | ste,pins = "GPIO34_H14"; | ||
| 95 | input-enable; | ||
| 96 | bias-pull-down; | ||
| 97 | }; | ||
| 98 | }; | ||
| 99 | }; | ||
| 100 | gpio50 { | ||
| 101 | gpio50_default_mode: gpio50_default { | ||
| 102 | default_mux { | ||
| 103 | ste,function = "gpio"; | ||
| 104 | ste,pins = "gpio50_d_1"; | ||
| 105 | }; | ||
| 106 | default_cfg { | ||
| 107 | ste,pins = "GPIO50_L4"; | ||
| 108 | input-enable; | ||
| 109 | bias-disable; | ||
| 110 | }; | ||
| 111 | }; | ||
| 112 | }; | ||
| 113 | /* This sets up the PWM pin 14 */ | ||
| 114 | pwm { | ||
| 115 | pwm_default_mode: pwm_default { | ||
| 116 | default_mux { | ||
| 117 | ste,function = "pwmout"; | ||
| 118 | ste,pins = "pwmout1_d_1"; | ||
| 119 | }; | ||
| 120 | default_cfg { | ||
| 121 | ste,pins = "GPIO14_C16"; | ||
| 122 | input-enable; | ||
| 123 | bias-pull-down; | ||
| 124 | }; | ||
| 125 | }; | ||
| 126 | }; | ||
| 127 | /* This sets up audio interface 2 */ | ||
| 128 | adi2 { | ||
| 129 | adi2_default_mode: adi2_default { | ||
| 130 | default_mux { | ||
| 131 | ste,function = "adi2"; | ||
| 132 | ste,pins = "adi2_d_1"; | ||
| 133 | }; | ||
| 134 | default_cfg { | ||
| 135 | ste,pins = "GPIO17_P2", | ||
| 136 | "GPIO18_N3", | ||
| 137 | "GPIO19_T1", | ||
| 138 | "GPIO20_P3"; | ||
| 139 | input-enable; | ||
| 140 | bias-pull-down; | ||
| 141 | }; | ||
| 142 | }; | ||
| 143 | }; | ||
| 144 | /* Modem I2C setup (SCL and SDA pins) */ | ||
| 145 | modsclsda { | ||
| 146 | modsclsda_default_mode: modsclsda_default { | ||
| 147 | default_mux { | ||
| 148 | ste,function = "modsclsda"; | ||
| 149 | ste,pins = "modsclsda_d_1"; | ||
| 150 | }; | ||
| 151 | default_cfg { | ||
| 152 | ste,pins = "GPIO40_J15", | ||
| 153 | "GPIO41_J14"; | ||
| 154 | input-enable; | ||
| 155 | bias-pull-down; | ||
| 156 | }; | ||
| 157 | }; | ||
| 158 | }; | ||
| 159 | resethw { | ||
| 160 | resethw_default_mode: resethw_default { | ||
| 161 | default_mux { | ||
| 162 | ste,function = "resethw"; | ||
| 163 | ste,pins = "resethw_d_1"; | ||
| 164 | }; | ||
| 165 | default_cfg { | ||
| 166 | ste,pins = "GPIO52_D16"; | ||
| 167 | input-enable; | ||
| 168 | bias-pull-down; | ||
| 169 | }; | ||
| 170 | }; | ||
| 171 | }; | ||
| 172 | service { | ||
| 173 | service_default_mode: service_default { | ||
| 174 | default_mux { | ||
| 175 | ste,function = "service"; | ||
| 176 | ste,pins = "service_d_1"; | ||
| 177 | }; | ||
| 178 | default_cfg { | ||
| 179 | ste,pins = "GPIO53_D15"; | ||
| 180 | input-enable; | ||
| 181 | bias-pull-down; | ||
| 182 | }; | ||
| 183 | }; | ||
| 184 | }; | ||
| 185 | /* | ||
| 186 | * Clock output pins associated with regulators. | ||
| 187 | */ | ||
| 188 | sysclkreq2 { | ||
| 189 | sysclkreq2_default_mode: sysclkreq2_default { | ||
| 190 | default_mux { | ||
| 191 | ste,function = "sysclkreq"; | ||
| 192 | ste,pins = "sysclkreq2_d_1"; | ||
| 193 | }; | ||
| 194 | default_cfg { | ||
| 195 | ste,pins = "GPIO1_N4"; | ||
| 196 | input-enable; | ||
| 197 | bias-disable; | ||
| 198 | }; | ||
| 199 | }; | ||
| 200 | sysclkreq2_sleep_mode: sysclkreq2_sleep { | ||
| 201 | default_mux { | ||
| 202 | ste,function = "gpio"; | ||
| 203 | ste,pins = "gpio1_a_1"; | ||
| 204 | }; | ||
| 205 | default_cfg { | ||
| 206 | ste,pins = "GPIO1_N4"; | ||
| 207 | input-enable; | ||
| 208 | bias-pull-down; | ||
| 209 | }; | ||
| 210 | }; | ||
| 211 | }; | ||
| 212 | sysclkreq4 { | ||
| 213 | sysclkreq4_default_mode: sysclkreq4_default { | ||
| 214 | default_mux { | ||
| 215 | ste,function = "sysclkreq"; | ||
| 216 | ste,pins = "sysclkreq4_d_1"; | ||
| 217 | }; | ||
| 218 | default_cfg { | ||
| 219 | ste,pins = "GPIO3_P5"; | ||
| 220 | input-enable; | ||
| 221 | bias-disable; | ||
| 222 | }; | ||
| 223 | }; | ||
| 224 | sysclkreq4_sleep_mode: sysclkreq4_sleep { | ||
| 225 | default_mux { | ||
| 226 | ste,function = "gpio"; | ||
| 227 | ste,pins = "gpio3_a_1"; | ||
| 228 | }; | ||
| 229 | default_cfg { | ||
| 230 | ste,pins = "GPIO3_P5"; | ||
| 231 | input-enable; | ||
| 232 | bias-pull-down; | ||
| 233 | }; | ||
| 234 | }; | ||
| 235 | }; | ||
| 236 | }; | ||
| 237 | }; | ||
| 238 | }; | ||
| 239 | }; | ||
| 240 | }; | ||
diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dtsi index 40f0ecdf9303..abc762e24fcb 100644 --- a/arch/arm/boot/dts/ste-hrefprev60.dtsi +++ b/arch/arm/boot/dts/ste-hrefprev60.dtsi | |||
| @@ -12,6 +12,7 @@ | |||
| 12 | */ | 12 | */ |
| 13 | 13 | ||
| 14 | #include "ste-dbx5x0.dtsi" | 14 | #include "ste-dbx5x0.dtsi" |
| 15 | #include "ste-href-ab8500.dtsi" | ||
| 15 | #include "ste-href.dtsi" | 16 | #include "ste-href.dtsi" |
| 16 | 17 | ||
| 17 | / { | 18 | / { |
diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi index 3b6d1181939b..c2341061b943 100644 --- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi +++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi | |||
| @@ -10,6 +10,7 @@ | |||
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | #include "ste-dbx5x0.dtsi" | 12 | #include "ste-dbx5x0.dtsi" |
| 13 | #include "ste-href-ab8500.dtsi" | ||
| 13 | #include "ste-href.dtsi" | 14 | #include "ste-href.dtsi" |
| 14 | 15 | ||
| 15 | / { | 16 | / { |
diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index 97d5d21b7db7..a2f632d0be2a 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts | |||
| @@ -11,6 +11,7 @@ | |||
| 11 | 11 | ||
| 12 | /dts-v1/; | 12 | /dts-v1/; |
| 13 | #include "ste-dbx5x0.dtsi" | 13 | #include "ste-dbx5x0.dtsi" |
| 14 | #include "ste-href-ab8500.dtsi" | ||
| 14 | #include "ste-href-family-pinctrl.dtsi" | 15 | #include "ste-href-family-pinctrl.dtsi" |
| 15 | 16 | ||
| 16 | / { | 17 | / { |
diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts index a9da4800daf0..6fe688e9e4da 100644 --- a/arch/arm/boot/dts/ste-u300.dts +++ b/arch/arm/boot/dts/ste-u300.dts | |||
| @@ -457,7 +457,7 @@ | |||
| 457 | interrupt-parent = <&vica>; | 457 | interrupt-parent = <&vica>; |
| 458 | interrupts = <23>; | 458 | interrupts = <23>; |
| 459 | clocks = <&spi_clk>, <&spi_clk>; | 459 | clocks = <&spi_clk>, <&spi_clk>; |
| 460 | clock-names = "apb_pclk", "spi_clk"; | 460 | clock-names = "SSPCLK", "apb_pclk"; |
| 461 | dmas = <&dmac 27 &dmac 28>; | 461 | dmas = <&dmac 27 &dmac 28>; |
| 462 | dma-names = "tx", "rx"; | 462 | dma-names = "tx", "rx"; |
| 463 | num-cs = <3>; | 463 | num-cs = <3>; |
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts index d4b081d6a167..fa746aea5e66 100644 --- a/arch/arm/boot/dts/sun4i-a10-a1000.dts +++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts | |||
| @@ -13,6 +13,7 @@ | |||
| 13 | 13 | ||
| 14 | /dts-v1/; | 14 | /dts-v1/; |
| 15 | /include/ "sun4i-a10.dtsi" | 15 | /include/ "sun4i-a10.dtsi" |
| 16 | /include/ "sunxi-common-regulators.dtsi" | ||
| 16 | 17 | ||
| 17 | / { | 18 | / { |
| 18 | model = "Mele A1000"; | 19 | model = "Mele A1000"; |
| @@ -35,6 +36,32 @@ | |||
| 35 | }; | 36 | }; |
| 36 | }; | 37 | }; |
| 37 | 38 | ||
| 39 | usbphy: phy@01c13400 { | ||
| 40 | usb1_vbus-supply = <®_usb1_vbus>; | ||
| 41 | usb2_vbus-supply = <®_usb2_vbus>; | ||
| 42 | status = "okay"; | ||
| 43 | }; | ||
| 44 | |||
| 45 | ehci0: usb@01c14000 { | ||
| 46 | status = "okay"; | ||
| 47 | }; | ||
| 48 | |||
| 49 | ohci0: usb@01c14400 { | ||
| 50 | status = "okay"; | ||
| 51 | }; | ||
| 52 | |||
| 53 | ahci: sata@01c18000 { | ||
| 54 | status = "okay"; | ||
| 55 | }; | ||
| 56 | |||
| 57 | ehci1: usb@01c1c000 { | ||
| 58 | status = "okay"; | ||
| 59 | }; | ||
| 60 | |||
| 61 | ohci1: usb@01c1c400 { | ||
| 62 | status = "okay"; | ||
| 63 | }; | ||
| 64 | |||
| 38 | pinctrl@01c20800 { | 65 | pinctrl@01c20800 { |
| 39 | emac_power_pin_a1000: emac_power_pin@0 { | 66 | emac_power_pin_a1000: emac_power_pin@0 { |
| 40 | allwinner,pins = "PH15"; | 67 | allwinner,pins = "PH15"; |
| @@ -80,18 +107,22 @@ | |||
| 80 | }; | 107 | }; |
| 81 | }; | 108 | }; |
| 82 | 109 | ||
| 83 | regulators { | 110 | reg_emac_3v3: emac-3v3 { |
| 84 | compatible = "simple-bus"; | 111 | compatible = "regulator-fixed"; |
| 112 | pinctrl-names = "default"; | ||
| 113 | pinctrl-0 = <&emac_power_pin_a1000>; | ||
| 114 | regulator-name = "emac-3v3"; | ||
| 115 | regulator-min-microvolt = <3300000>; | ||
| 116 | regulator-max-microvolt = <3300000>; | ||
| 117 | enable-active-high; | ||
| 118 | gpio = <&pio 7 15 0>; | ||
| 119 | }; | ||
| 85 | 120 | ||
| 86 | reg_emac_3v3: emac-3v3 { | 121 | reg_usb1_vbus: usb1-vbus { |
| 87 | compatible = "regulator-fixed"; | 122 | status = "okay"; |
| 88 | pinctrl-names = "default"; | 123 | }; |
| 89 | pinctrl-0 = <&emac_power_pin_a1000>; | 124 | |
| 90 | regulator-name = "emac-3v3"; | 125 | reg_usb2_vbus: usb2-vbus { |
| 91 | regulator-min-microvolt = <3300000>; | 126 | status = "okay"; |
| 92 | regulator-max-microvolt = <3300000>; | ||
| 93 | enable-active-high; | ||
| 94 | gpio = <&pio 7 15 0>; | ||
| 95 | }; | ||
| 96 | }; | 127 | }; |
| 97 | }; | 128 | }; |
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts index b139ee6bcf99..4684cbe6843b 100644 --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts | |||
| @@ -12,6 +12,7 @@ | |||
| 12 | 12 | ||
| 13 | /dts-v1/; | 13 | /dts-v1/; |
| 14 | /include/ "sun4i-a10.dtsi" | 14 | /include/ "sun4i-a10.dtsi" |
| 15 | /include/ "sunxi-common-regulators.dtsi" | ||
| 15 | 16 | ||
| 16 | / { | 17 | / { |
| 17 | model = "Cubietech Cubieboard"; | 18 | model = "Cubietech Cubieboard"; |
| @@ -33,6 +34,33 @@ | |||
| 33 | }; | 34 | }; |
| 34 | }; | 35 | }; |
| 35 | 36 | ||
| 37 | usbphy: phy@01c13400 { | ||
| 38 | usb1_vbus-supply = <®_usb1_vbus>; | ||
| 39 | usb2_vbus-supply = <®_usb2_vbus>; | ||
| 40 | status = "okay"; | ||
| 41 | }; | ||
| 42 | |||
| 43 | ehci0: usb@01c14000 { | ||
| 44 | status = "okay"; | ||
| 45 | }; | ||
| 46 | |||
| 47 | ohci0: usb@01c14400 { | ||
| 48 | status = "okay"; | ||
| 49 | }; | ||
| 50 | |||
| 51 | ahci: sata@01c18000 { | ||
| 52 | target-supply = <®_ahci_5v>; | ||
| 53 | status = "okay"; | ||
| 54 | }; | ||
| 55 | |||
| 56 | ehci1: usb@01c1c000 { | ||
| 57 | status = "okay"; | ||
| 58 | }; | ||
| 59 | |||
| 60 | ohci1: usb@01c1c400 { | ||
| 61 | status = "okay"; | ||
| 62 | }; | ||
| 63 | |||
| 36 | pinctrl@01c20800 { | 64 | pinctrl@01c20800 { |
| 37 | led_pins_cubieboard: led_pins@0 { | 65 | led_pins_cubieboard: led_pins@0 { |
| 38 | allwinner,pins = "PH20", "PH21"; | 66 | allwinner,pins = "PH20", "PH21"; |
| @@ -77,4 +105,16 @@ | |||
| 77 | linux,default-trigger = "heartbeat"; | 105 | linux,default-trigger = "heartbeat"; |
| 78 | }; | 106 | }; |
| 79 | }; | 107 | }; |
| 108 | |||
| 109 | reg_ahci_5v: ahci-5v { | ||
| 110 | status = "okay"; | ||
| 111 | }; | ||
| 112 | |||
| 113 | reg_usb1_vbus: usb1-vbus { | ||
| 114 | status = "okay"; | ||
| 115 | }; | ||
| 116 | |||
| 117 | reg_usb2_vbus: usb2-vbus { | ||
| 118 | status = "okay"; | ||
| 119 | }; | ||
| 80 | }; | 120 | }; |
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts index 3a1595f67823..d7c17e46ce23 100644 --- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts +++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts | |||
| @@ -13,6 +13,7 @@ | |||
| 13 | 13 | ||
| 14 | /dts-v1/; | 14 | /dts-v1/; |
| 15 | /include/ "sun4i-a10.dtsi" | 15 | /include/ "sun4i-a10.dtsi" |
| 16 | /include/ "sunxi-common-regulators.dtsi" | ||
| 16 | 17 | ||
| 17 | / { | 18 | / { |
| 18 | model = "Miniand Hackberry"; | 19 | model = "Miniand Hackberry"; |
| @@ -35,6 +36,28 @@ | |||
| 35 | }; | 36 | }; |
| 36 | }; | 37 | }; |
| 37 | 38 | ||
| 39 | usbphy: phy@01c13400 { | ||
| 40 | usb1_vbus-supply = <®_usb1_vbus>; | ||
| 41 | usb2_vbus-supply = <®_usb2_vbus>; | ||
| 42 | status = "okay"; | ||
| 43 | }; | ||
| 44 | |||
| 45 | ehci0: usb@01c14000 { | ||
| 46 | status = "okay"; | ||
| 47 | }; | ||
| 48 | |||
| 49 | ohci0: usb@01c14400 { | ||
| 50 | status = "okay"; | ||
| 51 | }; | ||
| 52 | |||
| 53 | ehci1: usb@01c1c000 { | ||
| 54 | status = "okay"; | ||
| 55 | }; | ||
| 56 | |||
| 57 | ohci1: usb@01c1c400 { | ||
| 58 | status = "okay"; | ||
| 59 | }; | ||
| 60 | |||
| 38 | pio: pinctrl@01c20800 { | 61 | pio: pinctrl@01c20800 { |
| 39 | pinctrl-names = "default"; | 62 | pinctrl-names = "default"; |
| 40 | pinctrl-0 = <&hackberry_hogs>; | 63 | pinctrl-0 = <&hackberry_hogs>; |
| @@ -45,6 +68,13 @@ | |||
| 45 | allwinner,drive = <0>; | 68 | allwinner,drive = <0>; |
| 46 | allwinner,pull = <0>; | 69 | allwinner,pull = <0>; |
| 47 | }; | 70 | }; |
| 71 | |||
| 72 | usb2_vbus_pin_hackberry: usb2_vbus_pin@0 { | ||
| 73 | allwinner,pins = "PH12"; | ||
| 74 | allwinner,function = "gpio_out"; | ||
| 75 | allwinner,drive = <0>; | ||
| 76 | allwinner,pull = <0>; | ||
| 77 | }; | ||
| 48 | }; | 78 | }; |
| 49 | 79 | ||
| 50 | uart0: serial@01c28000 { | 80 | uart0: serial@01c28000 { |
| @@ -54,16 +84,22 @@ | |||
| 54 | }; | 84 | }; |
| 55 | }; | 85 | }; |
| 56 | 86 | ||
| 57 | regulators { | 87 | reg_emac_3v3: emac-3v3 { |
| 58 | compatible = "simple-bus"; | 88 | compatible = "regulator-fixed"; |
| 89 | regulator-name = "emac-3v3"; | ||
| 90 | regulator-min-microvolt = <3300000>; | ||
| 91 | regulator-max-microvolt = <3300000>; | ||
| 92 | enable-active-high; | ||
| 93 | gpio = <&pio 7 19 0>; | ||
| 94 | }; | ||
| 59 | 95 | ||
| 60 | reg_emac_3v3: emac-3v3 { | 96 | reg_usb1_vbus: usb1-vbus { |
| 61 | compatible = "regulator-fixed"; | 97 | status = "okay"; |
| 62 | regulator-name = "emac-3v3"; | 98 | }; |
| 63 | regulator-min-microvolt = <3300000>; | 99 | |
| 64 | regulator-max-microvolt = <3300000>; | 100 | reg_usb2_vbus: usb2-vbus { |
| 65 | enable-active-high; | 101 | pinctrl-0 = <&usb2_vbus_pin_hackberry>; |
| 66 | gpio = <&pio 7 19 0>; | 102 | gpio = <&pio 7 12 0>; |
| 67 | }; | 103 | status = "okay"; |
| 68 | }; | 104 | }; |
| 69 | }; | 105 | }; |
diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts new file mode 100644 index 000000000000..fe9272ee55c3 --- /dev/null +++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts | |||
| @@ -0,0 +1,69 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2014 Open Source Support GmbH | ||
| 3 | * | ||
| 4 | * David Lanzendörfer <david.lanzendoerfer@o2s.ch> | ||
| 5 | * | ||
| 6 | * The code contained herein is licensed under the GNU General Public | ||
| 7 | * License. You may obtain a copy of the GNU General Public License | ||
| 8 | * Version 2 or later at the following locations: | ||
| 9 | * | ||
| 10 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 11 | * http://www.gnu.org/copyleft/gpl.html | ||
| 12 | */ | ||
| 13 | |||
| 14 | /dts-v1/; | ||
| 15 | /include/ "sun4i-a10.dtsi" | ||
| 16 | /include/ "sunxi-common-regulators.dtsi" | ||
| 17 | |||
| 18 | / { | ||
| 19 | model = "INet-97F Rev 02"; | ||
| 20 | compatible = "primux,inet97fv2", "allwinner,sun4i-a10"; | ||
| 21 | |||
| 22 | aliases { | ||
| 23 | serial0 = &uart0; | ||
| 24 | }; | ||
| 25 | |||
| 26 | soc@01c00000 { | ||
| 27 | uart0: serial@01c28000 { | ||
| 28 | pinctrl-names = "default"; | ||
| 29 | pinctrl-0 = <&uart0_pins_a>; | ||
| 30 | status = "okay"; | ||
| 31 | }; | ||
| 32 | |||
| 33 | i2c0: i2c@01c2ac00 { | ||
| 34 | pinctrl-names = "default"; | ||
| 35 | pinctrl-0 = <&i2c0_pins_a>; | ||
| 36 | status = "okay"; | ||
| 37 | }; | ||
| 38 | |||
| 39 | usbphy: phy@01c13400 { | ||
| 40 | usb1_vbus-supply = <®_usb1_vbus>; | ||
| 41 | usb2_vbus-supply = <®_usb2_vbus>; | ||
| 42 | status = "okay"; | ||
| 43 | }; | ||
| 44 | |||
| 45 | ehci0: usb@01c14000 { | ||
| 46 | status = "okay"; | ||
| 47 | }; | ||
| 48 | |||
| 49 | ohci0: usb@01c14400 { | ||
| 50 | status = "okay"; | ||
| 51 | }; | ||
| 52 | |||
| 53 | ehci1: usb@01c1c000 { | ||
| 54 | status = "okay"; | ||
| 55 | }; | ||
| 56 | |||
| 57 | ohci1: usb@01c1c400 { | ||
| 58 | status = "okay"; | ||
| 59 | }; | ||
| 60 | }; | ||
| 61 | |||
| 62 | reg_usb1_vbus: usb1-vbus { | ||
| 63 | status = "okay"; | ||
| 64 | }; | ||
| 65 | |||
| 66 | reg_usb2_vbus: usb2-vbus { | ||
| 67 | status = "okay"; | ||
| 68 | }; | ||
| 69 | }; | ||
diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts index 70b3323caf1a..dd84a9e313b3 100644 --- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts +++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts | |||
| @@ -13,16 +13,47 @@ | |||
| 13 | 13 | ||
| 14 | /dts-v1/; | 14 | /dts-v1/; |
| 15 | /include/ "sun4i-a10.dtsi" | 15 | /include/ "sun4i-a10.dtsi" |
| 16 | /include/ "sunxi-common-regulators.dtsi" | ||
| 16 | 17 | ||
| 17 | / { | 18 | / { |
| 18 | model = "PineRiver Mini X-Plus"; | 19 | model = "PineRiver Mini X-Plus"; |
| 19 | compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10"; | 20 | compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10"; |
| 20 | 21 | ||
| 21 | soc@01c00000 { | 22 | soc@01c00000 { |
| 23 | usbphy: phy@01c13400 { | ||
| 24 | usb1_vbus-supply = <®_usb1_vbus>; | ||
| 25 | usb2_vbus-supply = <®_usb2_vbus>; | ||
| 26 | status = "okay"; | ||
| 27 | }; | ||
| 28 | |||
| 29 | ehci0: usb@01c14000 { | ||
| 30 | status = "okay"; | ||
| 31 | }; | ||
| 32 | |||
| 33 | ohci0: usb@01c14400 { | ||
| 34 | status = "okay"; | ||
| 35 | }; | ||
| 36 | |||
| 37 | ehci1: usb@01c1c000 { | ||
| 38 | status = "okay"; | ||
| 39 | }; | ||
| 40 | |||
| 41 | ohci1: usb@01c1c400 { | ||
| 42 | status = "okay"; | ||
| 43 | }; | ||
| 44 | |||
| 22 | uart0: serial@01c28000 { | 45 | uart0: serial@01c28000 { |
| 23 | pinctrl-names = "default"; | 46 | pinctrl-names = "default"; |
| 24 | pinctrl-0 = <&uart0_pins_a>; | 47 | pinctrl-0 = <&uart0_pins_a>; |
| 25 | status = "okay"; | 48 | status = "okay"; |
| 26 | }; | 49 | }; |
| 27 | }; | 50 | }; |
| 51 | |||
| 52 | reg_usb1_vbus: usb1-vbus { | ||
| 53 | status = "okay"; | ||
| 54 | }; | ||
| 55 | |||
| 56 | reg_usb2_vbus: usb2-vbus { | ||
| 57 | status = "okay"; | ||
| 58 | }; | ||
| 28 | }; | 59 | }; |
diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts new file mode 100644 index 000000000000..66cf0c7cf5b7 --- /dev/null +++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts | |||
| @@ -0,0 +1,111 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2014 - Hans de Goede <hdegoede@redhat.com> | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | /include/ "sun4i-a10.dtsi" | ||
| 14 | /include/ "sunxi-common-regulators.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Olimex A10-OLinuXino-LIME"; | ||
| 18 | compatible = "olimex,a10-olinuxino-lime", "allwinner,sun4i-a10"; | ||
| 19 | |||
| 20 | soc@01c00000 { | ||
| 21 | emac: ethernet@01c0b000 { | ||
| 22 | pinctrl-names = "default"; | ||
| 23 | pinctrl-0 = <&emac_pins_a>; | ||
| 24 | phy = <&phy1>; | ||
| 25 | status = "okay"; | ||
| 26 | }; | ||
| 27 | |||
| 28 | mdio@01c0b080 { | ||
| 29 | status = "okay"; | ||
| 30 | |||
| 31 | phy1: ethernet-phy@1 { | ||
| 32 | reg = <1>; | ||
| 33 | }; | ||
| 34 | }; | ||
| 35 | |||
| 36 | usbphy: phy@01c13400 { | ||
| 37 | usb1_vbus-supply = <®_usb1_vbus>; | ||
| 38 | usb2_vbus-supply = <®_usb2_vbus>; | ||
| 39 | status = "okay"; | ||
| 40 | }; | ||
| 41 | |||
| 42 | ehci0: usb@01c14000 { | ||
| 43 | status = "okay"; | ||
| 44 | }; | ||
| 45 | |||
| 46 | ohci0: usb@01c14400 { | ||
| 47 | status = "okay"; | ||
| 48 | }; | ||
| 49 | |||
| 50 | ahci: sata@01c18000 { | ||
| 51 | target-supply = <®_ahci_5v>; | ||
| 52 | status = "okay"; | ||
| 53 | }; | ||
| 54 | |||
| 55 | ehci1: usb@01c1c000 { | ||
| 56 | status = "okay"; | ||
| 57 | }; | ||
| 58 | |||
| 59 | ohci1: usb@01c1c400 { | ||
| 60 | status = "okay"; | ||
| 61 | }; | ||
| 62 | |||
| 63 | pinctrl@01c20800 { | ||
| 64 | ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 { | ||
| 65 | allwinner,pins = "PC3"; | ||
| 66 | allwinner,function = "gpio_out"; | ||
| 67 | allwinner,drive = <0>; | ||
| 68 | allwinner,pull = <0>; | ||
| 69 | }; | ||
| 70 | |||
| 71 | led_pins_olinuxinolime: led_pins@0 { | ||
| 72 | allwinner,pins = "PH2"; | ||
| 73 | allwinner,function = "gpio_out"; | ||
| 74 | allwinner,drive = <1>; | ||
| 75 | allwinner,pull = <0>; | ||
| 76 | }; | ||
| 77 | }; | ||
| 78 | |||
| 79 | uart0: serial@01c28000 { | ||
| 80 | pinctrl-names = "default"; | ||
| 81 | pinctrl-0 = <&uart0_pins_a>; | ||
| 82 | status = "okay"; | ||
| 83 | }; | ||
| 84 | }; | ||
| 85 | |||
| 86 | leds { | ||
| 87 | compatible = "gpio-leds"; | ||
| 88 | pinctrl-names = "default"; | ||
| 89 | pinctrl-0 = <&led_pins_olinuxinolime>; | ||
| 90 | |||
| 91 | green { | ||
| 92 | label = "a10-olinuxino-lime:green:usr"; | ||
| 93 | gpios = <&pio 7 2 0>; | ||
| 94 | default-state = "on"; | ||
| 95 | }; | ||
| 96 | }; | ||
| 97 | |||
| 98 | reg_ahci_5v: ahci-5v { | ||
| 99 | pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>; | ||
| 100 | gpio = <&pio 2 3 0>; | ||
| 101 | status = "okay"; | ||
| 102 | }; | ||
| 103 | |||
| 104 | reg_usb1_vbus: usb1-vbus { | ||
| 105 | status = "okay"; | ||
| 106 | }; | ||
| 107 | |||
| 108 | reg_usb2_vbus: usb2-vbus { | ||
| 109 | status = "okay"; | ||
| 110 | }; | ||
| 111 | }; | ||
diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts new file mode 100644 index 000000000000..255b47e7019c --- /dev/null +++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts | |||
| @@ -0,0 +1,79 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2014 Zoltan HERPAI | ||
| 3 | * Zoltan HERPAI <wigyori@uid0.hu> | ||
| 4 | * | ||
| 5 | * The code contained herein is licensed under the GNU General Public | ||
| 6 | * License. You may obtain a copy of the GNU General Public License | ||
| 7 | * Version 2 or later at the following locations: | ||
| 8 | * | ||
| 9 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 10 | * http://www.gnu.org/copyleft/gpl.html | ||
| 11 | */ | ||
| 12 | |||
| 13 | /dts-v1/; | ||
| 14 | /include/ "sun4i-a10.dtsi" | ||
| 15 | /include/ "sunxi-common-regulators.dtsi" | ||
| 16 | |||
| 17 | / { | ||
| 18 | model = "LinkSprite pcDuino"; | ||
| 19 | compatible = "linksprite,a10-pcduino", "allwinner,sun4i-a10"; | ||
| 20 | |||
| 21 | soc@01c00000 { | ||
| 22 | emac: ethernet@01c0b000 { | ||
| 23 | pinctrl-names = "default"; | ||
| 24 | pinctrl-0 = <&emac_pins_a>; | ||
| 25 | phy = <&phy1>; | ||
| 26 | status = "okay"; | ||
| 27 | }; | ||
| 28 | |||
| 29 | mdio@01c0b080 { | ||
| 30 | status = "okay"; | ||
| 31 | |||
| 32 | phy1: ethernet-phy@1 { | ||
| 33 | reg = <1>; | ||
| 34 | }; | ||
| 35 | }; | ||
| 36 | |||
| 37 | usbphy: phy@01c13400 { | ||
| 38 | usb1_vbus-supply = <®_usb1_vbus>; | ||
| 39 | usb2_vbus-supply = <®_usb2_vbus>; | ||
| 40 | status = "okay"; | ||
| 41 | }; | ||
| 42 | |||
| 43 | ehci0: usb@01c14000 { | ||
| 44 | status = "okay"; | ||
| 45 | }; | ||
| 46 | |||
| 47 | ohci0: usb@01c14400 { | ||
| 48 | status = "okay"; | ||
| 49 | }; | ||
| 50 | |||
| 51 | ehci1: usb@01c1c000 { | ||
| 52 | status = "okay"; | ||
| 53 | }; | ||
| 54 | |||
| 55 | ohci1: usb@01c1c400 { | ||
| 56 | status = "okay"; | ||
| 57 | }; | ||
| 58 | |||
| 59 | uart0: serial@01c28000 { | ||
| 60 | pinctrl-names = "default"; | ||
| 61 | pinctrl-0 = <&uart0_pins_a>; | ||
| 62 | status = "okay"; | ||
| 63 | }; | ||
| 64 | |||
| 65 | i2c0: i2c@01c2ac00 { | ||
| 66 | pinctrl-names = "default"; | ||
| 67 | pinctrl-0 = <&i2c0_pins_a>; | ||
| 68 | status = "okay"; | ||
| 69 | }; | ||
| 70 | }; | ||
| 71 | |||
| 72 | reg_usb1_vbus: usb1-vbus { | ||
| 73 | status = "okay"; | ||
| 74 | }; | ||
| 75 | |||
| 76 | reg_usb2_vbus: usb2-vbus { | ||
| 77 | status = "okay"; | ||
| 78 | }; | ||
| 79 | }; | ||
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 10666ca8aee1..6af23323e18c 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi | |||
| @@ -19,6 +19,12 @@ | |||
| 19 | ethernet0 = &emac; | 19 | ethernet0 = &emac; |
| 20 | serial0 = &uart0; | 20 | serial0 = &uart0; |
| 21 | serial1 = &uart1; | 21 | serial1 = &uart1; |
| 22 | serial2 = &uart2; | ||
| 23 | serial3 = &uart3; | ||
| 24 | serial4 = &uart4; | ||
| 25 | serial5 = &uart5; | ||
| 26 | serial6 = &uart6; | ||
| 27 | serial7 = &uart7; | ||
| 22 | }; | 28 | }; |
| 23 | 29 | ||
| 24 | cpus { | 30 | cpus { |
| @@ -52,44 +58,48 @@ | |||
| 52 | clock-frequency = <0>; | 58 | clock-frequency = <0>; |
| 53 | }; | 59 | }; |
| 54 | 60 | ||
| 55 | osc24M: osc24M@01c20050 { | 61 | osc24M: clk@01c20050 { |
| 56 | #clock-cells = <0>; | 62 | #clock-cells = <0>; |
| 57 | compatible = "allwinner,sun4i-osc-clk"; | 63 | compatible = "allwinner,sun4i-a10-osc-clk"; |
| 58 | reg = <0x01c20050 0x4>; | 64 | reg = <0x01c20050 0x4>; |
| 59 | clock-frequency = <24000000>; | 65 | clock-frequency = <24000000>; |
| 66 | clock-output-names = "osc24M"; | ||
| 60 | }; | 67 | }; |
| 61 | 68 | ||
| 62 | osc32k: osc32k { | 69 | osc32k: clk@0 { |
| 63 | #clock-cells = <0>; | 70 | #clock-cells = <0>; |
| 64 | compatible = "fixed-clock"; | 71 | compatible = "fixed-clock"; |
| 65 | clock-frequency = <32768>; | 72 | clock-frequency = <32768>; |
| 73 | clock-output-names = "osc32k"; | ||
| 66 | }; | 74 | }; |
| 67 | 75 | ||
| 68 | pll1: pll1@01c20000 { | 76 | pll1: clk@01c20000 { |
| 69 | #clock-cells = <0>; | 77 | #clock-cells = <0>; |
| 70 | compatible = "allwinner,sun4i-pll1-clk"; | 78 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
| 71 | reg = <0x01c20000 0x4>; | 79 | reg = <0x01c20000 0x4>; |
| 72 | clocks = <&osc24M>; | 80 | clocks = <&osc24M>; |
| 81 | clock-output-names = "pll1"; | ||
| 73 | }; | 82 | }; |
| 74 | 83 | ||
| 75 | pll4: pll4@01c20018 { | 84 | pll4: clk@01c20018 { |
| 76 | #clock-cells = <0>; | 85 | #clock-cells = <0>; |
| 77 | compatible = "allwinner,sun4i-pll1-clk"; | 86 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
| 78 | reg = <0x01c20018 0x4>; | 87 | reg = <0x01c20018 0x4>; |
| 79 | clocks = <&osc24M>; | 88 | clocks = <&osc24M>; |
| 89 | clock-output-names = "pll4"; | ||
| 80 | }; | 90 | }; |
| 81 | 91 | ||
| 82 | pll5: pll5@01c20020 { | 92 | pll5: clk@01c20020 { |
| 83 | #clock-cells = <1>; | 93 | #clock-cells = <1>; |
| 84 | compatible = "allwinner,sun4i-pll5-clk"; | 94 | compatible = "allwinner,sun4i-a10-pll5-clk"; |
| 85 | reg = <0x01c20020 0x4>; | 95 | reg = <0x01c20020 0x4>; |
| 86 | clocks = <&osc24M>; | 96 | clocks = <&osc24M>; |
| 87 | clock-output-names = "pll5_ddr", "pll5_other"; | 97 | clock-output-names = "pll5_ddr", "pll5_other"; |
| 88 | }; | 98 | }; |
| 89 | 99 | ||
| 90 | pll6: pll6@01c20028 { | 100 | pll6: clk@01c20028 { |
| 91 | #clock-cells = <1>; | 101 | #clock-cells = <1>; |
| 92 | compatible = "allwinner,sun4i-pll6-clk"; | 102 | compatible = "allwinner,sun4i-a10-pll6-clk"; |
| 93 | reg = <0x01c20028 0x4>; | 103 | reg = <0x01c20028 0x4>; |
| 94 | clocks = <&osc24M>; | 104 | clocks = <&osc24M>; |
| 95 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; | 105 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; |
| @@ -98,21 +108,23 @@ | |||
| 98 | /* dummy is 200M */ | 108 | /* dummy is 200M */ |
| 99 | cpu: cpu@01c20054 { | 109 | cpu: cpu@01c20054 { |
| 100 | #clock-cells = <0>; | 110 | #clock-cells = <0>; |
| 101 | compatible = "allwinner,sun4i-cpu-clk"; | 111 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
| 102 | reg = <0x01c20054 0x4>; | 112 | reg = <0x01c20054 0x4>; |
| 103 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; | 113 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; |
| 114 | clock-output-names = "cpu"; | ||
| 104 | }; | 115 | }; |
| 105 | 116 | ||
| 106 | axi: axi@01c20054 { | 117 | axi: axi@01c20054 { |
| 107 | #clock-cells = <0>; | 118 | #clock-cells = <0>; |
| 108 | compatible = "allwinner,sun4i-axi-clk"; | 119 | compatible = "allwinner,sun4i-a10-axi-clk"; |
| 109 | reg = <0x01c20054 0x4>; | 120 | reg = <0x01c20054 0x4>; |
| 110 | clocks = <&cpu>; | 121 | clocks = <&cpu>; |
| 122 | clock-output-names = "axi"; | ||
| 111 | }; | 123 | }; |
| 112 | 124 | ||
| 113 | axi_gates: axi_gates@01c2005c { | 125 | axi_gates: clk@01c2005c { |
| 114 | #clock-cells = <1>; | 126 | #clock-cells = <1>; |
| 115 | compatible = "allwinner,sun4i-axi-gates-clk"; | 127 | compatible = "allwinner,sun4i-a10-axi-gates-clk"; |
| 116 | reg = <0x01c2005c 0x4>; | 128 | reg = <0x01c2005c 0x4>; |
| 117 | clocks = <&axi>; | 129 | clocks = <&axi>; |
| 118 | clock-output-names = "axi_dram"; | 130 | clock-output-names = "axi_dram"; |
| @@ -120,14 +132,15 @@ | |||
| 120 | 132 | ||
| 121 | ahb: ahb@01c20054 { | 133 | ahb: ahb@01c20054 { |
| 122 | #clock-cells = <0>; | 134 | #clock-cells = <0>; |
| 123 | compatible = "allwinner,sun4i-ahb-clk"; | 135 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
| 124 | reg = <0x01c20054 0x4>; | 136 | reg = <0x01c20054 0x4>; |
| 125 | clocks = <&axi>; | 137 | clocks = <&axi>; |
| 138 | clock-output-names = "ahb"; | ||
| 126 | }; | 139 | }; |
| 127 | 140 | ||
| 128 | ahb_gates: ahb_gates@01c20060 { | 141 | ahb_gates: clk@01c20060 { |
| 129 | #clock-cells = <1>; | 142 | #clock-cells = <1>; |
| 130 | compatible = "allwinner,sun4i-ahb-gates-clk"; | 143 | compatible = "allwinner,sun4i-a10-ahb-gates-clk"; |
| 131 | reg = <0x01c20060 0x8>; | 144 | reg = <0x01c20060 0x8>; |
| 132 | clocks = <&ahb>; | 145 | clocks = <&ahb>; |
| 133 | clock-output-names = "ahb_usb0", "ahb_ehci0", | 146 | clock-output-names = "ahb_usb0", "ahb_ehci0", |
| @@ -145,14 +158,15 @@ | |||
| 145 | 158 | ||
| 146 | apb0: apb0@01c20054 { | 159 | apb0: apb0@01c20054 { |
| 147 | #clock-cells = <0>; | 160 | #clock-cells = <0>; |
| 148 | compatible = "allwinner,sun4i-apb0-clk"; | 161 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
| 149 | reg = <0x01c20054 0x4>; | 162 | reg = <0x01c20054 0x4>; |
| 150 | clocks = <&ahb>; | 163 | clocks = <&ahb>; |
| 164 | clock-output-names = "apb0"; | ||
| 151 | }; | 165 | }; |
| 152 | 166 | ||
| 153 | apb0_gates: apb0_gates@01c20068 { | 167 | apb0_gates: clk@01c20068 { |
| 154 | #clock-cells = <1>; | 168 | #clock-cells = <1>; |
| 155 | compatible = "allwinner,sun4i-apb0-gates-clk"; | 169 | compatible = "allwinner,sun4i-a10-apb0-gates-clk"; |
| 156 | reg = <0x01c20068 0x4>; | 170 | reg = <0x01c20068 0x4>; |
| 157 | clocks = <&apb0>; | 171 | clocks = <&apb0>; |
| 158 | clock-output-names = "apb0_codec", "apb0_spdif", | 172 | clock-output-names = "apb0_codec", "apb0_spdif", |
| @@ -162,21 +176,23 @@ | |||
| 162 | 176 | ||
| 163 | apb1_mux: apb1_mux@01c20058 { | 177 | apb1_mux: apb1_mux@01c20058 { |
| 164 | #clock-cells = <0>; | 178 | #clock-cells = <0>; |
| 165 | compatible = "allwinner,sun4i-apb1-mux-clk"; | 179 | compatible = "allwinner,sun4i-a10-apb1-mux-clk"; |
| 166 | reg = <0x01c20058 0x4>; | 180 | reg = <0x01c20058 0x4>; |
| 167 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; | 181 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; |
| 182 | clock-output-names = "apb1_mux"; | ||
| 168 | }; | 183 | }; |
| 169 | 184 | ||
| 170 | apb1: apb1@01c20058 { | 185 | apb1: apb1@01c20058 { |
| 171 | #clock-cells = <0>; | 186 | #clock-cells = <0>; |
| 172 | compatible = "allwinner,sun4i-apb1-clk"; | 187 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
| 173 | reg = <0x01c20058 0x4>; | 188 | reg = <0x01c20058 0x4>; |
| 174 | clocks = <&apb1_mux>; | 189 | clocks = <&apb1_mux>; |
| 190 | clock-output-names = "apb1"; | ||
| 175 | }; | 191 | }; |
| 176 | 192 | ||
| 177 | apb1_gates: apb1_gates@01c2006c { | 193 | apb1_gates: clk@01c2006c { |
| 178 | #clock-cells = <1>; | 194 | #clock-cells = <1>; |
| 179 | compatible = "allwinner,sun4i-apb1-gates-clk"; | 195 | compatible = "allwinner,sun4i-a10-apb1-gates-clk"; |
| 180 | reg = <0x01c2006c 0x4>; | 196 | reg = <0x01c2006c 0x4>; |
| 181 | clocks = <&apb1>; | 197 | clocks = <&apb1>; |
| 182 | clock-output-names = "apb1_i2c0", "apb1_i2c1", | 198 | clock-output-names = "apb1_i2c0", "apb1_i2c1", |
| @@ -189,7 +205,7 @@ | |||
| 189 | 205 | ||
| 190 | nand_clk: clk@01c20080 { | 206 | nand_clk: clk@01c20080 { |
| 191 | #clock-cells = <0>; | 207 | #clock-cells = <0>; |
| 192 | compatible = "allwinner,sun4i-mod0-clk"; | 208 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 193 | reg = <0x01c20080 0x4>; | 209 | reg = <0x01c20080 0x4>; |
| 194 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 210 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 195 | clock-output-names = "nand"; | 211 | clock-output-names = "nand"; |
| @@ -197,7 +213,7 @@ | |||
| 197 | 213 | ||
| 198 | ms_clk: clk@01c20084 { | 214 | ms_clk: clk@01c20084 { |
| 199 | #clock-cells = <0>; | 215 | #clock-cells = <0>; |
| 200 | compatible = "allwinner,sun4i-mod0-clk"; | 216 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 201 | reg = <0x01c20084 0x4>; | 217 | reg = <0x01c20084 0x4>; |
| 202 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 218 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 203 | clock-output-names = "ms"; | 219 | clock-output-names = "ms"; |
| @@ -205,7 +221,7 @@ | |||
| 205 | 221 | ||
| 206 | mmc0_clk: clk@01c20088 { | 222 | mmc0_clk: clk@01c20088 { |
| 207 | #clock-cells = <0>; | 223 | #clock-cells = <0>; |
| 208 | compatible = "allwinner,sun4i-mod0-clk"; | 224 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 209 | reg = <0x01c20088 0x4>; | 225 | reg = <0x01c20088 0x4>; |
| 210 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 226 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 211 | clock-output-names = "mmc0"; | 227 | clock-output-names = "mmc0"; |
| @@ -213,7 +229,7 @@ | |||
| 213 | 229 | ||
| 214 | mmc1_clk: clk@01c2008c { | 230 | mmc1_clk: clk@01c2008c { |
| 215 | #clock-cells = <0>; | 231 | #clock-cells = <0>; |
| 216 | compatible = "allwinner,sun4i-mod0-clk"; | 232 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 217 | reg = <0x01c2008c 0x4>; | 233 | reg = <0x01c2008c 0x4>; |
| 218 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 234 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 219 | clock-output-names = "mmc1"; | 235 | clock-output-names = "mmc1"; |
| @@ -221,7 +237,7 @@ | |||
| 221 | 237 | ||
| 222 | mmc2_clk: clk@01c20090 { | 238 | mmc2_clk: clk@01c20090 { |
| 223 | #clock-cells = <0>; | 239 | #clock-cells = <0>; |
| 224 | compatible = "allwinner,sun4i-mod0-clk"; | 240 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 225 | reg = <0x01c20090 0x4>; | 241 | reg = <0x01c20090 0x4>; |
| 226 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 242 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 227 | clock-output-names = "mmc2"; | 243 | clock-output-names = "mmc2"; |
| @@ -229,7 +245,7 @@ | |||
| 229 | 245 | ||
| 230 | mmc3_clk: clk@01c20094 { | 246 | mmc3_clk: clk@01c20094 { |
| 231 | #clock-cells = <0>; | 247 | #clock-cells = <0>; |
| 232 | compatible = "allwinner,sun4i-mod0-clk"; | 248 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 233 | reg = <0x01c20094 0x4>; | 249 | reg = <0x01c20094 0x4>; |
| 234 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 250 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 235 | clock-output-names = "mmc3"; | 251 | clock-output-names = "mmc3"; |
| @@ -237,7 +253,7 @@ | |||
| 237 | 253 | ||
| 238 | ts_clk: clk@01c20098 { | 254 | ts_clk: clk@01c20098 { |
| 239 | #clock-cells = <0>; | 255 | #clock-cells = <0>; |
| 240 | compatible = "allwinner,sun4i-mod0-clk"; | 256 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 241 | reg = <0x01c20098 0x4>; | 257 | reg = <0x01c20098 0x4>; |
| 242 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 258 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 243 | clock-output-names = "ts"; | 259 | clock-output-names = "ts"; |
| @@ -245,7 +261,7 @@ | |||
| 245 | 261 | ||
| 246 | ss_clk: clk@01c2009c { | 262 | ss_clk: clk@01c2009c { |
| 247 | #clock-cells = <0>; | 263 | #clock-cells = <0>; |
| 248 | compatible = "allwinner,sun4i-mod0-clk"; | 264 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 249 | reg = <0x01c2009c 0x4>; | 265 | reg = <0x01c2009c 0x4>; |
| 250 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 266 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 251 | clock-output-names = "ss"; | 267 | clock-output-names = "ss"; |
| @@ -253,7 +269,7 @@ | |||
| 253 | 269 | ||
| 254 | spi0_clk: clk@01c200a0 { | 270 | spi0_clk: clk@01c200a0 { |
| 255 | #clock-cells = <0>; | 271 | #clock-cells = <0>; |
| 256 | compatible = "allwinner,sun4i-mod0-clk"; | 272 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 257 | reg = <0x01c200a0 0x4>; | 273 | reg = <0x01c200a0 0x4>; |
| 258 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 274 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 259 | clock-output-names = "spi0"; | 275 | clock-output-names = "spi0"; |
| @@ -261,7 +277,7 @@ | |||
| 261 | 277 | ||
| 262 | spi1_clk: clk@01c200a4 { | 278 | spi1_clk: clk@01c200a4 { |
| 263 | #clock-cells = <0>; | 279 | #clock-cells = <0>; |
| 264 | compatible = "allwinner,sun4i-mod0-clk"; | 280 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 265 | reg = <0x01c200a4 0x4>; | 281 | reg = <0x01c200a4 0x4>; |
| 266 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 282 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 267 | clock-output-names = "spi1"; | 283 | clock-output-names = "spi1"; |
| @@ -269,7 +285,7 @@ | |||
| 269 | 285 | ||
| 270 | spi2_clk: clk@01c200a8 { | 286 | spi2_clk: clk@01c200a8 { |
| 271 | #clock-cells = <0>; | 287 | #clock-cells = <0>; |
| 272 | compatible = "allwinner,sun4i-mod0-clk"; | 288 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 273 | reg = <0x01c200a8 0x4>; | 289 | reg = <0x01c200a8 0x4>; |
| 274 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 290 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 275 | clock-output-names = "spi2"; | 291 | clock-output-names = "spi2"; |
| @@ -277,7 +293,7 @@ | |||
| 277 | 293 | ||
| 278 | pata_clk: clk@01c200ac { | 294 | pata_clk: clk@01c200ac { |
| 279 | #clock-cells = <0>; | 295 | #clock-cells = <0>; |
| 280 | compatible = "allwinner,sun4i-mod0-clk"; | 296 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 281 | reg = <0x01c200ac 0x4>; | 297 | reg = <0x01c200ac 0x4>; |
| 282 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 298 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 283 | clock-output-names = "pata"; | 299 | clock-output-names = "pata"; |
| @@ -285,7 +301,7 @@ | |||
| 285 | 301 | ||
| 286 | ir0_clk: clk@01c200b0 { | 302 | ir0_clk: clk@01c200b0 { |
| 287 | #clock-cells = <0>; | 303 | #clock-cells = <0>; |
| 288 | compatible = "allwinner,sun4i-mod0-clk"; | 304 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 289 | reg = <0x01c200b0 0x4>; | 305 | reg = <0x01c200b0 0x4>; |
| 290 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 306 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 291 | clock-output-names = "ir0"; | 307 | clock-output-names = "ir0"; |
| @@ -293,15 +309,24 @@ | |||
| 293 | 309 | ||
| 294 | ir1_clk: clk@01c200b4 { | 310 | ir1_clk: clk@01c200b4 { |
| 295 | #clock-cells = <0>; | 311 | #clock-cells = <0>; |
| 296 | compatible = "allwinner,sun4i-mod0-clk"; | 312 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 297 | reg = <0x01c200b4 0x4>; | 313 | reg = <0x01c200b4 0x4>; |
| 298 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 314 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 299 | clock-output-names = "ir1"; | 315 | clock-output-names = "ir1"; |
| 300 | }; | 316 | }; |
| 301 | 317 | ||
| 318 | usb_clk: clk@01c200cc { | ||
| 319 | #clock-cells = <1>; | ||
| 320 | #reset-cells = <1>; | ||
| 321 | compatible = "allwinner,sun4i-a10-usb-clk"; | ||
| 322 | reg = <0x01c200cc 0x4>; | ||
| 323 | clocks = <&pll6 1>; | ||
| 324 | clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy"; | ||
| 325 | }; | ||
| 326 | |||
| 302 | spi3_clk: clk@01c200d4 { | 327 | spi3_clk: clk@01c200d4 { |
| 303 | #clock-cells = <0>; | 328 | #clock-cells = <0>; |
| 304 | compatible = "allwinner,sun4i-mod0-clk"; | 329 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 305 | reg = <0x01c200d4 0x4>; | 330 | reg = <0x01c200d4 0x4>; |
| 306 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 331 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 307 | clock-output-names = "spi3"; | 332 | clock-output-names = "spi3"; |
| @@ -314,6 +339,28 @@ | |||
| 314 | #size-cells = <1>; | 339 | #size-cells = <1>; |
| 315 | ranges; | 340 | ranges; |
| 316 | 341 | ||
| 342 | spi0: spi@01c05000 { | ||
| 343 | compatible = "allwinner,sun4i-a10-spi"; | ||
| 344 | reg = <0x01c05000 0x1000>; | ||
| 345 | interrupts = <10>; | ||
| 346 | clocks = <&ahb_gates 20>, <&spi0_clk>; | ||
| 347 | clock-names = "ahb", "mod"; | ||
| 348 | status = "disabled"; | ||
| 349 | #address-cells = <1>; | ||
| 350 | #size-cells = <0>; | ||
| 351 | }; | ||
| 352 | |||
| 353 | spi1: spi@01c06000 { | ||
| 354 | compatible = "allwinner,sun4i-a10-spi"; | ||
| 355 | reg = <0x01c06000 0x1000>; | ||
| 356 | interrupts = <11>; | ||
| 357 | clocks = <&ahb_gates 21>, <&spi1_clk>; | ||
| 358 | clock-names = "ahb", "mod"; | ||
| 359 | status = "disabled"; | ||
| 360 | #address-cells = <1>; | ||
| 361 | #size-cells = <0>; | ||
| 362 | }; | ||
| 363 | |||
| 317 | emac: ethernet@01c0b000 { | 364 | emac: ethernet@01c0b000 { |
| 318 | compatible = "allwinner,sun4i-a10-emac"; | 365 | compatible = "allwinner,sun4i-a10-emac"; |
| 319 | reg = <0x01c0b000 0x1000>; | 366 | reg = <0x01c0b000 0x1000>; |
| @@ -330,6 +377,88 @@ | |||
| 330 | #size-cells = <0>; | 377 | #size-cells = <0>; |
| 331 | }; | 378 | }; |
| 332 | 379 | ||
| 380 | usbphy: phy@01c13400 { | ||
| 381 | #phy-cells = <1>; | ||
| 382 | compatible = "allwinner,sun4i-a10-usb-phy"; | ||
| 383 | reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; | ||
| 384 | reg-names = "phy_ctrl", "pmu1", "pmu2"; | ||
| 385 | clocks = <&usb_clk 8>; | ||
| 386 | clock-names = "usb_phy"; | ||
| 387 | resets = <&usb_clk 1>, <&usb_clk 2>; | ||
| 388 | reset-names = "usb1_reset", "usb2_reset"; | ||
| 389 | status = "disabled"; | ||
| 390 | }; | ||
| 391 | |||
| 392 | ehci0: usb@01c14000 { | ||
| 393 | compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; | ||
| 394 | reg = <0x01c14000 0x100>; | ||
| 395 | interrupts = <39>; | ||
| 396 | clocks = <&ahb_gates 1>; | ||
| 397 | phys = <&usbphy 1>; | ||
| 398 | phy-names = "usb"; | ||
| 399 | status = "disabled"; | ||
| 400 | }; | ||
| 401 | |||
| 402 | ohci0: usb@01c14400 { | ||
| 403 | compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; | ||
| 404 | reg = <0x01c14400 0x100>; | ||
| 405 | interrupts = <64>; | ||
| 406 | clocks = <&usb_clk 6>, <&ahb_gates 2>; | ||
| 407 | phys = <&usbphy 1>; | ||
| 408 | phy-names = "usb"; | ||
| 409 | status = "disabled"; | ||
| 410 | }; | ||
| 411 | |||
| 412 | spi2: spi@01c17000 { | ||
| 413 | compatible = "allwinner,sun4i-a10-spi"; | ||
| 414 | reg = <0x01c17000 0x1000>; | ||
| 415 | interrupts = <12>; | ||
| 416 | clocks = <&ahb_gates 22>, <&spi2_clk>; | ||
| 417 | clock-names = "ahb", "mod"; | ||
| 418 | status = "disabled"; | ||
| 419 | #address-cells = <1>; | ||
| 420 | #size-cells = <0>; | ||
| 421 | }; | ||
| 422 | |||
| 423 | ahci: sata@01c18000 { | ||
| 424 | compatible = "allwinner,sun4i-a10-ahci"; | ||
| 425 | reg = <0x01c18000 0x1000>; | ||
| 426 | interrupts = <56>; | ||
| 427 | clocks = <&pll6 0>, <&ahb_gates 25>; | ||
| 428 | status = "disabled"; | ||
| 429 | }; | ||
| 430 | |||
| 431 | ehci1: usb@01c1c000 { | ||
| 432 | compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; | ||
| 433 | reg = <0x01c1c000 0x100>; | ||
| 434 | interrupts = <40>; | ||
| 435 | clocks = <&ahb_gates 3>; | ||
| 436 | phys = <&usbphy 2>; | ||
| 437 | phy-names = "usb"; | ||
| 438 | status = "disabled"; | ||
| 439 | }; | ||
| 440 | |||
| 441 | ohci1: usb@01c1c400 { | ||
| 442 | compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; | ||
| 443 | reg = <0x01c1c400 0x100>; | ||
| 444 | interrupts = <65>; | ||
| 445 | clocks = <&usb_clk 7>, <&ahb_gates 4>; | ||
| 446 | phys = <&usbphy 2>; | ||
| 447 | phy-names = "usb"; | ||
| 448 | status = "disabled"; | ||
| 449 | }; | ||
| 450 | |||
| 451 | spi3: spi@01c1f000 { | ||
| 452 | compatible = "allwinner,sun4i-a10-spi"; | ||
| 453 | reg = <0x01c1f000 0x1000>; | ||
| 454 | interrupts = <50>; | ||
| 455 | clocks = <&ahb_gates 23>, <&spi3_clk>; | ||
| 456 | clock-names = "ahb", "mod"; | ||
| 457 | status = "disabled"; | ||
| 458 | #address-cells = <1>; | ||
| 459 | #size-cells = <0>; | ||
| 460 | }; | ||
| 461 | |||
| 333 | intc: interrupt-controller@01c20400 { | 462 | intc: interrupt-controller@01c20400 { |
| 334 | compatible = "allwinner,sun4i-ic"; | 463 | compatible = "allwinner,sun4i-ic"; |
| 335 | reg = <0x01c20400 0x400>; | 464 | reg = <0x01c20400 0x400>; |
| @@ -410,7 +539,7 @@ | |||
| 410 | }; | 539 | }; |
| 411 | 540 | ||
| 412 | wdt: watchdog@01c20c90 { | 541 | wdt: watchdog@01c20c90 { |
| 413 | compatible = "allwinner,sun4i-wdt"; | 542 | compatible = "allwinner,sun4i-a10-wdt"; |
| 414 | reg = <0x01c20c90 0x10>; | 543 | reg = <0x01c20c90 0x10>; |
| 415 | }; | 544 | }; |
| 416 | 545 | ||
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts index 3c9f8b3cd3e3..23611b71d3aa 100644 --- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | |||
| @@ -13,6 +13,7 @@ | |||
| 13 | 13 | ||
| 14 | /dts-v1/; | 14 | /dts-v1/; |
| 15 | /include/ "sun5i-a10s.dtsi" | 15 | /include/ "sun5i-a10s.dtsi" |
| 16 | /include/ "sunxi-common-regulators.dtsi" | ||
| 16 | 17 | ||
| 17 | / { | 18 | / { |
| 18 | model = "Olimex A10s-Olinuxino Micro"; | 19 | model = "Olimex A10s-Olinuxino Micro"; |
| @@ -34,6 +35,19 @@ | |||
| 34 | }; | 35 | }; |
| 35 | }; | 36 | }; |
| 36 | 37 | ||
| 38 | usbphy: phy@01c13400 { | ||
| 39 | usb1_vbus-supply = <®_usb1_vbus>; | ||
| 40 | status = "okay"; | ||
| 41 | }; | ||
| 42 | |||
| 43 | ehci0: usb@01c14000 { | ||
| 44 | status = "okay"; | ||
| 45 | }; | ||
| 46 | |||
| 47 | ohci0: usb@01c14400 { | ||
| 48 | status = "okay"; | ||
| 49 | }; | ||
| 50 | |||
| 37 | pinctrl@01c20800 { | 51 | pinctrl@01c20800 { |
| 38 | led_pins_olinuxino: led_pins@0 { | 52 | led_pins_olinuxino: led_pins@0 { |
| 39 | allwinner,pins = "PE3"; | 53 | allwinner,pins = "PE3"; |
| @@ -41,6 +55,13 @@ | |||
| 41 | allwinner,drive = <1>; | 55 | allwinner,drive = <1>; |
| 42 | allwinner,pull = <0>; | 56 | allwinner,pull = <0>; |
| 43 | }; | 57 | }; |
| 58 | |||
| 59 | usb1_vbus_pin_olinuxino_m: usb1_vbus_pin@0 { | ||
| 60 | allwinner,pins = "PB10"; | ||
| 61 | allwinner,function = "gpio_out"; | ||
| 62 | allwinner,drive = <0>; | ||
| 63 | allwinner,pull = <0>; | ||
| 64 | }; | ||
| 44 | }; | 65 | }; |
| 45 | 66 | ||
| 46 | uart0: serial@01c28000 { | 67 | uart0: serial@01c28000 { |
| @@ -98,4 +119,10 @@ | |||
| 98 | default-state = "on"; | 119 | default-state = "on"; |
| 99 | }; | 120 | }; |
| 100 | }; | 121 | }; |
| 122 | |||
| 123 | reg_usb1_vbus: usb1-vbus { | ||
| 124 | pinctrl-0 = <&usb1_vbus_pin_olinuxino_m>; | ||
| 125 | gpio = <&pio 1 10 0>; | ||
| 126 | status = "okay"; | ||
| 127 | }; | ||
| 101 | }; | 128 | }; |
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index 64961595e8d6..8681f6c18fdc 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi | |||
| @@ -18,6 +18,10 @@ | |||
| 18 | 18 | ||
| 19 | aliases { | 19 | aliases { |
| 20 | ethernet0 = &emac; | 20 | ethernet0 = &emac; |
| 21 | serial0 = &uart0; | ||
| 22 | serial1 = &uart1; | ||
| 23 | serial2 = &uart2; | ||
| 24 | serial3 = &uart3; | ||
| 21 | }; | 25 | }; |
| 22 | 26 | ||
| 23 | cpus { | 27 | cpus { |
| @@ -47,44 +51,48 @@ | |||
| 47 | clock-frequency = <0>; | 51 | clock-frequency = <0>; |
| 48 | }; | 52 | }; |
| 49 | 53 | ||
| 50 | osc24M: osc24M@01c20050 { | 54 | osc24M: clk@01c20050 { |
| 51 | #clock-cells = <0>; | 55 | #clock-cells = <0>; |
| 52 | compatible = "allwinner,sun4i-osc-clk"; | 56 | compatible = "allwinner,sun4i-a10-osc-clk"; |
| 53 | reg = <0x01c20050 0x4>; | 57 | reg = <0x01c20050 0x4>; |
| 54 | clock-frequency = <24000000>; | 58 | clock-frequency = <24000000>; |
| 59 | clock-output-names = "osc24M"; | ||
| 55 | }; | 60 | }; |
| 56 | 61 | ||
| 57 | osc32k: osc32k { | 62 | osc32k: clk@0 { |
| 58 | #clock-cells = <0>; | 63 | #clock-cells = <0>; |
| 59 | compatible = "fixed-clock"; | 64 | compatible = "fixed-clock"; |
| 60 | clock-frequency = <32768>; | 65 | clock-frequency = <32768>; |
| 66 | clock-output-names = "osc32k"; | ||
| 61 | }; | 67 | }; |
| 62 | 68 | ||
| 63 | pll1: pll1@01c20000 { | 69 | pll1: clk@01c20000 { |
| 64 | #clock-cells = <0>; | 70 | #clock-cells = <0>; |
| 65 | compatible = "allwinner,sun4i-pll1-clk"; | 71 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
| 66 | reg = <0x01c20000 0x4>; | 72 | reg = <0x01c20000 0x4>; |
| 67 | clocks = <&osc24M>; | 73 | clocks = <&osc24M>; |
| 74 | clock-output-names = "pll1"; | ||
| 68 | }; | 75 | }; |
| 69 | 76 | ||
| 70 | pll4: pll4@01c20018 { | 77 | pll4: clk@01c20018 { |
| 71 | #clock-cells = <0>; | 78 | #clock-cells = <0>; |
| 72 | compatible = "allwinner,sun4i-pll1-clk"; | 79 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
| 73 | reg = <0x01c20018 0x4>; | 80 | reg = <0x01c20018 0x4>; |
| 74 | clocks = <&osc24M>; | 81 | clocks = <&osc24M>; |
| 82 | clock-output-names = "pll4"; | ||
| 75 | }; | 83 | }; |
| 76 | 84 | ||
| 77 | pll5: pll5@01c20020 { | 85 | pll5: clk@01c20020 { |
| 78 | #clock-cells = <1>; | 86 | #clock-cells = <1>; |
| 79 | compatible = "allwinner,sun4i-pll5-clk"; | 87 | compatible = "allwinner,sun4i-a10-pll5-clk"; |
| 80 | reg = <0x01c20020 0x4>; | 88 | reg = <0x01c20020 0x4>; |
| 81 | clocks = <&osc24M>; | 89 | clocks = <&osc24M>; |
| 82 | clock-output-names = "pll5_ddr", "pll5_other"; | 90 | clock-output-names = "pll5_ddr", "pll5_other"; |
| 83 | }; | 91 | }; |
| 84 | 92 | ||
| 85 | pll6: pll6@01c20028 { | 93 | pll6: clk@01c20028 { |
| 86 | #clock-cells = <1>; | 94 | #clock-cells = <1>; |
| 87 | compatible = "allwinner,sun4i-pll6-clk"; | 95 | compatible = "allwinner,sun4i-a10-pll6-clk"; |
| 88 | reg = <0x01c20028 0x4>; | 96 | reg = <0x01c20028 0x4>; |
| 89 | clocks = <&osc24M>; | 97 | clocks = <&osc24M>; |
| 90 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; | 98 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; |
| @@ -93,21 +101,23 @@ | |||
| 93 | /* dummy is 200M */ | 101 | /* dummy is 200M */ |
| 94 | cpu: cpu@01c20054 { | 102 | cpu: cpu@01c20054 { |
| 95 | #clock-cells = <0>; | 103 | #clock-cells = <0>; |
| 96 | compatible = "allwinner,sun4i-cpu-clk"; | 104 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
| 97 | reg = <0x01c20054 0x4>; | 105 | reg = <0x01c20054 0x4>; |
| 98 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; | 106 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; |
| 107 | clock-output-names = "cpu"; | ||
| 99 | }; | 108 | }; |
| 100 | 109 | ||
| 101 | axi: axi@01c20054 { | 110 | axi: axi@01c20054 { |
| 102 | #clock-cells = <0>; | 111 | #clock-cells = <0>; |
| 103 | compatible = "allwinner,sun4i-axi-clk"; | 112 | compatible = "allwinner,sun4i-a10-axi-clk"; |
| 104 | reg = <0x01c20054 0x4>; | 113 | reg = <0x01c20054 0x4>; |
| 105 | clocks = <&cpu>; | 114 | clocks = <&cpu>; |
| 115 | clock-output-names = "axi"; | ||
| 106 | }; | 116 | }; |
| 107 | 117 | ||
| 108 | axi_gates: axi_gates@01c2005c { | 118 | axi_gates: clk@01c2005c { |
| 109 | #clock-cells = <1>; | 119 | #clock-cells = <1>; |
| 110 | compatible = "allwinner,sun4i-axi-gates-clk"; | 120 | compatible = "allwinner,sun4i-a10-axi-gates-clk"; |
| 111 | reg = <0x01c2005c 0x4>; | 121 | reg = <0x01c2005c 0x4>; |
| 112 | clocks = <&axi>; | 122 | clocks = <&axi>; |
| 113 | clock-output-names = "axi_dram"; | 123 | clock-output-names = "axi_dram"; |
| @@ -115,12 +125,13 @@ | |||
| 115 | 125 | ||
| 116 | ahb: ahb@01c20054 { | 126 | ahb: ahb@01c20054 { |
| 117 | #clock-cells = <0>; | 127 | #clock-cells = <0>; |
| 118 | compatible = "allwinner,sun4i-ahb-clk"; | 128 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
| 119 | reg = <0x01c20054 0x4>; | 129 | reg = <0x01c20054 0x4>; |
| 120 | clocks = <&axi>; | 130 | clocks = <&axi>; |
| 131 | clock-output-names = "ahb"; | ||
| 121 | }; | 132 | }; |
| 122 | 133 | ||
| 123 | ahb_gates: ahb_gates@01c20060 { | 134 | ahb_gates: clk@01c20060 { |
| 124 | #clock-cells = <1>; | 135 | #clock-cells = <1>; |
| 125 | compatible = "allwinner,sun5i-a10s-ahb-gates-clk"; | 136 | compatible = "allwinner,sun5i-a10s-ahb-gates-clk"; |
| 126 | reg = <0x01c20060 0x8>; | 137 | reg = <0x01c20060 0x8>; |
| @@ -136,12 +147,13 @@ | |||
| 136 | 147 | ||
| 137 | apb0: apb0@01c20054 { | 148 | apb0: apb0@01c20054 { |
| 138 | #clock-cells = <0>; | 149 | #clock-cells = <0>; |
| 139 | compatible = "allwinner,sun4i-apb0-clk"; | 150 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
| 140 | reg = <0x01c20054 0x4>; | 151 | reg = <0x01c20054 0x4>; |
| 141 | clocks = <&ahb>; | 152 | clocks = <&ahb>; |
| 153 | clock-output-names = "apb0"; | ||
| 142 | }; | 154 | }; |
| 143 | 155 | ||
| 144 | apb0_gates: apb0_gates@01c20068 { | 156 | apb0_gates: clk@01c20068 { |
| 145 | #clock-cells = <1>; | 157 | #clock-cells = <1>; |
| 146 | compatible = "allwinner,sun5i-a10s-apb0-gates-clk"; | 158 | compatible = "allwinner,sun5i-a10s-apb0-gates-clk"; |
| 147 | reg = <0x01c20068 0x4>; | 159 | reg = <0x01c20068 0x4>; |
| @@ -152,19 +164,21 @@ | |||
| 152 | 164 | ||
| 153 | apb1_mux: apb1_mux@01c20058 { | 165 | apb1_mux: apb1_mux@01c20058 { |
| 154 | #clock-cells = <0>; | 166 | #clock-cells = <0>; |
| 155 | compatible = "allwinner,sun4i-apb1-mux-clk"; | 167 | compatible = "allwinner,sun4i-a10-apb1-mux-clk"; |
| 156 | reg = <0x01c20058 0x4>; | 168 | reg = <0x01c20058 0x4>; |
| 157 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; | 169 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; |
| 170 | clock-output-names = "apb1_mux"; | ||
| 158 | }; | 171 | }; |
| 159 | 172 | ||
| 160 | apb1: apb1@01c20058 { | 173 | apb1: apb1@01c20058 { |
| 161 | #clock-cells = <0>; | 174 | #clock-cells = <0>; |
| 162 | compatible = "allwinner,sun4i-apb1-clk"; | 175 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
| 163 | reg = <0x01c20058 0x4>; | 176 | reg = <0x01c20058 0x4>; |
| 164 | clocks = <&apb1_mux>; | 177 | clocks = <&apb1_mux>; |
| 178 | clock-output-names = "apb1"; | ||
| 165 | }; | 179 | }; |
| 166 | 180 | ||
| 167 | apb1_gates: apb1_gates@01c2006c { | 181 | apb1_gates: clk@01c2006c { |
| 168 | #clock-cells = <1>; | 182 | #clock-cells = <1>; |
| 169 | compatible = "allwinner,sun5i-a10s-apb1-gates-clk"; | 183 | compatible = "allwinner,sun5i-a10s-apb1-gates-clk"; |
| 170 | reg = <0x01c2006c 0x4>; | 184 | reg = <0x01c2006c 0x4>; |
| @@ -176,7 +190,7 @@ | |||
| 176 | 190 | ||
| 177 | nand_clk: clk@01c20080 { | 191 | nand_clk: clk@01c20080 { |
| 178 | #clock-cells = <0>; | 192 | #clock-cells = <0>; |
| 179 | compatible = "allwinner,sun4i-mod0-clk"; | 193 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 180 | reg = <0x01c20080 0x4>; | 194 | reg = <0x01c20080 0x4>; |
| 181 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 195 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 182 | clock-output-names = "nand"; | 196 | clock-output-names = "nand"; |
| @@ -184,7 +198,7 @@ | |||
| 184 | 198 | ||
| 185 | ms_clk: clk@01c20084 { | 199 | ms_clk: clk@01c20084 { |
| 186 | #clock-cells = <0>; | 200 | #clock-cells = <0>; |
| 187 | compatible = "allwinner,sun4i-mod0-clk"; | 201 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 188 | reg = <0x01c20084 0x4>; | 202 | reg = <0x01c20084 0x4>; |
| 189 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 203 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 190 | clock-output-names = "ms"; | 204 | clock-output-names = "ms"; |
| @@ -192,7 +206,7 @@ | |||
| 192 | 206 | ||
| 193 | mmc0_clk: clk@01c20088 { | 207 | mmc0_clk: clk@01c20088 { |
| 194 | #clock-cells = <0>; | 208 | #clock-cells = <0>; |
| 195 | compatible = "allwinner,sun4i-mod0-clk"; | 209 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 196 | reg = <0x01c20088 0x4>; | 210 | reg = <0x01c20088 0x4>; |
| 197 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 211 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 198 | clock-output-names = "mmc0"; | 212 | clock-output-names = "mmc0"; |
| @@ -200,7 +214,7 @@ | |||
| 200 | 214 | ||
| 201 | mmc1_clk: clk@01c2008c { | 215 | mmc1_clk: clk@01c2008c { |
| 202 | #clock-cells = <0>; | 216 | #clock-cells = <0>; |
| 203 | compatible = "allwinner,sun4i-mod0-clk"; | 217 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 204 | reg = <0x01c2008c 0x4>; | 218 | reg = <0x01c2008c 0x4>; |
| 205 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 219 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 206 | clock-output-names = "mmc1"; | 220 | clock-output-names = "mmc1"; |
| @@ -208,7 +222,7 @@ | |||
| 208 | 222 | ||
| 209 | mmc2_clk: clk@01c20090 { | 223 | mmc2_clk: clk@01c20090 { |
| 210 | #clock-cells = <0>; | 224 | #clock-cells = <0>; |
| 211 | compatible = "allwinner,sun4i-mod0-clk"; | 225 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 212 | reg = <0x01c20090 0x4>; | 226 | reg = <0x01c20090 0x4>; |
| 213 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 227 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 214 | clock-output-names = "mmc2"; | 228 | clock-output-names = "mmc2"; |
| @@ -216,7 +230,7 @@ | |||
| 216 | 230 | ||
| 217 | ts_clk: clk@01c20098 { | 231 | ts_clk: clk@01c20098 { |
| 218 | #clock-cells = <0>; | 232 | #clock-cells = <0>; |
| 219 | compatible = "allwinner,sun4i-mod0-clk"; | 233 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 220 | reg = <0x01c20098 0x4>; | 234 | reg = <0x01c20098 0x4>; |
| 221 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 235 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 222 | clock-output-names = "ts"; | 236 | clock-output-names = "ts"; |
| @@ -224,7 +238,7 @@ | |||
| 224 | 238 | ||
| 225 | ss_clk: clk@01c2009c { | 239 | ss_clk: clk@01c2009c { |
| 226 | #clock-cells = <0>; | 240 | #clock-cells = <0>; |
| 227 | compatible = "allwinner,sun4i-mod0-clk"; | 241 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 228 | reg = <0x01c2009c 0x4>; | 242 | reg = <0x01c2009c 0x4>; |
| 229 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 243 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 230 | clock-output-names = "ss"; | 244 | clock-output-names = "ss"; |
| @@ -232,7 +246,7 @@ | |||
| 232 | 246 | ||
| 233 | spi0_clk: clk@01c200a0 { | 247 | spi0_clk: clk@01c200a0 { |
| 234 | #clock-cells = <0>; | 248 | #clock-cells = <0>; |
| 235 | compatible = "allwinner,sun4i-mod0-clk"; | 249 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 236 | reg = <0x01c200a0 0x4>; | 250 | reg = <0x01c200a0 0x4>; |
| 237 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 251 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 238 | clock-output-names = "spi0"; | 252 | clock-output-names = "spi0"; |
| @@ -240,7 +254,7 @@ | |||
| 240 | 254 | ||
| 241 | spi1_clk: clk@01c200a4 { | 255 | spi1_clk: clk@01c200a4 { |
| 242 | #clock-cells = <0>; | 256 | #clock-cells = <0>; |
| 243 | compatible = "allwinner,sun4i-mod0-clk"; | 257 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 244 | reg = <0x01c200a4 0x4>; | 258 | reg = <0x01c200a4 0x4>; |
| 245 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 259 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 246 | clock-output-names = "spi1"; | 260 | clock-output-names = "spi1"; |
| @@ -248,7 +262,7 @@ | |||
| 248 | 262 | ||
| 249 | spi2_clk: clk@01c200a8 { | 263 | spi2_clk: clk@01c200a8 { |
| 250 | #clock-cells = <0>; | 264 | #clock-cells = <0>; |
| 251 | compatible = "allwinner,sun4i-mod0-clk"; | 265 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 252 | reg = <0x01c200a8 0x4>; | 266 | reg = <0x01c200a8 0x4>; |
| 253 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 267 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 254 | clock-output-names = "spi2"; | 268 | clock-output-names = "spi2"; |
| @@ -256,15 +270,24 @@ | |||
| 256 | 270 | ||
| 257 | ir0_clk: clk@01c200b0 { | 271 | ir0_clk: clk@01c200b0 { |
| 258 | #clock-cells = <0>; | 272 | #clock-cells = <0>; |
| 259 | compatible = "allwinner,sun4i-mod0-clk"; | 273 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 260 | reg = <0x01c200b0 0x4>; | 274 | reg = <0x01c200b0 0x4>; |
| 261 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 275 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 262 | clock-output-names = "ir0"; | 276 | clock-output-names = "ir0"; |
| 263 | }; | 277 | }; |
| 264 | 278 | ||
| 279 | usb_clk: clk@01c200cc { | ||
| 280 | #clock-cells = <1>; | ||
| 281 | #reset-cells = <1>; | ||
| 282 | compatible = "allwinner,sun5i-a13-usb-clk"; | ||
| 283 | reg = <0x01c200cc 0x4>; | ||
| 284 | clocks = <&pll6 1>; | ||
| 285 | clock-output-names = "usb_ohci0", "usb_phy"; | ||
| 286 | }; | ||
| 287 | |||
| 265 | mbus_clk: clk@01c2015c { | 288 | mbus_clk: clk@01c2015c { |
| 266 | #clock-cells = <0>; | 289 | #clock-cells = <0>; |
| 267 | compatible = "allwinner,sun4i-mod0-clk"; | 290 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 268 | reg = <0x01c2015c 0x4>; | 291 | reg = <0x01c2015c 0x4>; |
| 269 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 292 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 270 | clock-output-names = "mbus"; | 293 | clock-output-names = "mbus"; |
| @@ -277,6 +300,28 @@ | |||
| 277 | #size-cells = <1>; | 300 | #size-cells = <1>; |
| 278 | ranges; | 301 | ranges; |
| 279 | 302 | ||
| 303 | spi0: spi@01c05000 { | ||
| 304 | compatible = "allwinner,sun4i-a10-spi"; | ||
| 305 | reg = <0x01c05000 0x1000>; | ||
| 306 | interrupts = <10>; | ||
| 307 | clocks = <&ahb_gates 20>, <&spi0_clk>; | ||
| 308 | clock-names = "ahb", "mod"; | ||
| 309 | status = "disabled"; | ||
| 310 | #address-cells = <1>; | ||
| 311 | #size-cells = <0>; | ||
| 312 | }; | ||
| 313 | |||
| 314 | spi1: spi@01c06000 { | ||
| 315 | compatible = "allwinner,sun4i-a10-spi"; | ||
| 316 | reg = <0x01c06000 0x1000>; | ||
| 317 | interrupts = <11>; | ||
| 318 | clocks = <&ahb_gates 21>, <&spi1_clk>; | ||
| 319 | clock-names = "ahb", "mod"; | ||
| 320 | status = "disabled"; | ||
| 321 | #address-cells = <1>; | ||
| 322 | #size-cells = <0>; | ||
| 323 | }; | ||
| 324 | |||
| 280 | emac: ethernet@01c0b000 { | 325 | emac: ethernet@01c0b000 { |
| 281 | compatible = "allwinner,sun4i-a10-emac"; | 326 | compatible = "allwinner,sun4i-a10-emac"; |
| 282 | reg = <0x01c0b000 0x1000>; | 327 | reg = <0x01c0b000 0x1000>; |
| @@ -293,6 +338,49 @@ | |||
| 293 | #size-cells = <0>; | 338 | #size-cells = <0>; |
| 294 | }; | 339 | }; |
| 295 | 340 | ||
| 341 | usbphy: phy@01c13400 { | ||
| 342 | #phy-cells = <1>; | ||
| 343 | compatible = "allwinner,sun5i-a13-usb-phy"; | ||
| 344 | reg = <0x01c13400 0x10 0x01c14800 0x4>; | ||
| 345 | reg-names = "phy_ctrl", "pmu1"; | ||
| 346 | clocks = <&usb_clk 8>; | ||
| 347 | clock-names = "usb_phy"; | ||
| 348 | resets = <&usb_clk 1>; | ||
| 349 | reset-names = "usb1_reset"; | ||
| 350 | status = "disabled"; | ||
| 351 | }; | ||
| 352 | |||
| 353 | ehci0: usb@01c14000 { | ||
| 354 | compatible = "allwinner,sun5i-a10s-ehci", "generic-ehci"; | ||
| 355 | reg = <0x01c14000 0x100>; | ||
| 356 | interrupts = <39>; | ||
| 357 | clocks = <&ahb_gates 1>; | ||
| 358 | phys = <&usbphy 1>; | ||
| 359 | phy-names = "usb"; | ||
| 360 | status = "disabled"; | ||
| 361 | }; | ||
| 362 | |||
| 363 | ohci0: usb@01c14400 { | ||
| 364 | compatible = "allwinner,sun5i-a10s-ohci", "generic-ohci"; | ||
| 365 | reg = <0x01c14400 0x100>; | ||
| 366 | interrupts = <40>; | ||
| 367 | clocks = <&usb_clk 6>, <&ahb_gates 2>; | ||
| 368 | phys = <&usbphy 1>; | ||
| 369 | phy-names = "usb"; | ||
| 370 | status = "disabled"; | ||
| 371 | }; | ||
| 372 | |||
| 373 | spi2: spi@01c17000 { | ||
| 374 | compatible = "allwinner,sun4i-a10-spi"; | ||
| 375 | reg = <0x01c17000 0x1000>; | ||
| 376 | interrupts = <12>; | ||
| 377 | clocks = <&ahb_gates 22>, <&spi2_clk>; | ||
| 378 | clock-names = "ahb", "mod"; | ||
| 379 | status = "disabled"; | ||
| 380 | #address-cells = <1>; | ||
| 381 | #size-cells = <0>; | ||
| 382 | }; | ||
| 383 | |||
| 296 | intc: interrupt-controller@01c20400 { | 384 | intc: interrupt-controller@01c20400 { |
| 297 | compatible = "allwinner,sun4i-ic"; | 385 | compatible = "allwinner,sun4i-ic"; |
| 298 | reg = <0x01c20400 0x400>; | 386 | reg = <0x01c20400 0x400>; |
| @@ -373,7 +461,7 @@ | |||
| 373 | }; | 461 | }; |
| 374 | 462 | ||
| 375 | wdt: watchdog@01c20c90 { | 463 | wdt: watchdog@01c20c90 { |
| 376 | compatible = "allwinner,sun4i-wdt"; | 464 | compatible = "allwinner,sun4i-a10-wdt"; |
| 377 | reg = <0x01c20c90 0x10>; | 465 | reg = <0x01c20c90 0x10>; |
| 378 | }; | 466 | }; |
| 379 | 467 | ||
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts index fe2ce0acdb06..11169d5b5b86 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | |||
| @@ -14,12 +14,26 @@ | |||
| 14 | 14 | ||
| 15 | /dts-v1/; | 15 | /dts-v1/; |
| 16 | /include/ "sun5i-a13.dtsi" | 16 | /include/ "sun5i-a13.dtsi" |
| 17 | /include/ "sunxi-common-regulators.dtsi" | ||
| 17 | 18 | ||
| 18 | / { | 19 | / { |
| 19 | model = "Olimex A13-Olinuxino Micro"; | 20 | model = "Olimex A13-Olinuxino Micro"; |
| 20 | compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13"; | 21 | compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13"; |
| 21 | 22 | ||
| 22 | soc@01c00000 { | 23 | soc@01c00000 { |
| 24 | usbphy: phy@01c13400 { | ||
| 25 | usb1_vbus-supply = <®_usb1_vbus>; | ||
| 26 | status = "okay"; | ||
| 27 | }; | ||
| 28 | |||
| 29 | ehci0: usb@01c14000 { | ||
| 30 | status = "okay"; | ||
| 31 | }; | ||
| 32 | |||
| 33 | ohci0: usb@01c14400 { | ||
| 34 | status = "okay"; | ||
| 35 | }; | ||
| 36 | |||
| 23 | pinctrl@01c20800 { | 37 | pinctrl@01c20800 { |
| 24 | led_pins_olinuxinom: led_pins@0 { | 38 | led_pins_olinuxinom: led_pins@0 { |
| 25 | allwinner,pins = "PG9"; | 39 | allwinner,pins = "PG9"; |
| @@ -27,6 +41,13 @@ | |||
| 27 | allwinner,drive = <1>; | 41 | allwinner,drive = <1>; |
| 28 | allwinner,pull = <0>; | 42 | allwinner,pull = <0>; |
| 29 | }; | 43 | }; |
| 44 | |||
| 45 | usb1_vbus_pin_olinuxinom: usb1_vbus_pin@0 { | ||
| 46 | allwinner,pins = "PG11"; | ||
| 47 | allwinner,function = "gpio_out"; | ||
| 48 | allwinner,drive = <0>; | ||
| 49 | allwinner,pull = <0>; | ||
| 50 | }; | ||
| 30 | }; | 51 | }; |
| 31 | 52 | ||
| 32 | uart1: serial@01c28400 { | 53 | uart1: serial@01c28400 { |
| @@ -65,4 +86,10 @@ | |||
| 65 | default-state = "on"; | 86 | default-state = "on"; |
| 66 | }; | 87 | }; |
| 67 | }; | 88 | }; |
| 89 | |||
| 90 | reg_usb1_vbus: usb1-vbus { | ||
| 91 | pinctrl-0 = <&usb1_vbus_pin_olinuxinom>; | ||
| 92 | gpio = <&pio 6 11 0>; | ||
| 93 | status = "okay"; | ||
| 94 | }; | ||
| 68 | }; | 95 | }; |
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts index a4ba5ff010cf..7a9187bbeb28 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts | |||
| @@ -13,12 +13,26 @@ | |||
| 13 | 13 | ||
| 14 | /dts-v1/; | 14 | /dts-v1/; |
| 15 | /include/ "sun5i-a13.dtsi" | 15 | /include/ "sun5i-a13.dtsi" |
| 16 | /include/ "sunxi-common-regulators.dtsi" | ||
| 16 | 17 | ||
| 17 | / { | 18 | / { |
| 18 | model = "Olimex A13-Olinuxino"; | 19 | model = "Olimex A13-Olinuxino"; |
| 19 | compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13"; | 20 | compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13"; |
| 20 | 21 | ||
| 21 | soc@01c00000 { | 22 | soc@01c00000 { |
| 23 | usbphy: phy@01c13400 { | ||
| 24 | usb1_vbus-supply = <®_usb1_vbus>; | ||
| 25 | status = "okay"; | ||
| 26 | }; | ||
| 27 | |||
| 28 | ehci0: usb@01c14000 { | ||
| 29 | status = "okay"; | ||
| 30 | }; | ||
| 31 | |||
| 32 | ohci0: usb@01c14400 { | ||
| 33 | status = "okay"; | ||
| 34 | }; | ||
| 35 | |||
| 22 | pinctrl@01c20800 { | 36 | pinctrl@01c20800 { |
| 23 | led_pins_olinuxino: led_pins@0 { | 37 | led_pins_olinuxino: led_pins@0 { |
| 24 | allwinner,pins = "PG9"; | 38 | allwinner,pins = "PG9"; |
| @@ -26,6 +40,13 @@ | |||
| 26 | allwinner,drive = <1>; | 40 | allwinner,drive = <1>; |
| 27 | allwinner,pull = <0>; | 41 | allwinner,pull = <0>; |
| 28 | }; | 42 | }; |
| 43 | |||
| 44 | usb1_vbus_pin_olinuxino: usb1_vbus_pin@0 { | ||
| 45 | allwinner,pins = "PG11"; | ||
| 46 | allwinner,function = "gpio_out"; | ||
| 47 | allwinner,drive = <0>; | ||
| 48 | allwinner,pull = <0>; | ||
| 49 | }; | ||
| 29 | }; | 50 | }; |
| 30 | 51 | ||
| 31 | uart1: serial@01c28400 { | 52 | uart1: serial@01c28400 { |
| @@ -63,4 +84,10 @@ | |||
| 63 | default-state = "on"; | 84 | default-state = "on"; |
| 64 | }; | 85 | }; |
| 65 | }; | 86 | }; |
| 87 | |||
| 88 | reg_usb1_vbus: usb1-vbus { | ||
| 89 | pinctrl-0 = <&usb1_vbus_pin_olinuxino>; | ||
| 90 | gpio = <&pio 6 11 0>; | ||
| 91 | status = "okay"; | ||
| 92 | }; | ||
| 66 | }; | 93 | }; |
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index 320335abfccd..7c6bb1bde9dd 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi | |||
| @@ -16,6 +16,11 @@ | |||
| 16 | / { | 16 | / { |
| 17 | interrupt-parent = <&intc>; | 17 | interrupt-parent = <&intc>; |
| 18 | 18 | ||
| 19 | aliases { | ||
| 20 | serial0 = &uart1; | ||
| 21 | serial1 = &uart3; | ||
| 22 | }; | ||
| 23 | |||
| 19 | cpus { | 24 | cpus { |
| 20 | #address-cells = <1>; | 25 | #address-cells = <1>; |
| 21 | #size-cells = <0>; | 26 | #size-cells = <0>; |
| @@ -47,44 +52,48 @@ | |||
| 47 | clock-frequency = <0>; | 52 | clock-frequency = <0>; |
| 48 | }; | 53 | }; |
| 49 | 54 | ||
| 50 | osc24M: osc24M@01c20050 { | 55 | osc24M: clk@01c20050 { |
| 51 | #clock-cells = <0>; | 56 | #clock-cells = <0>; |
| 52 | compatible = "allwinner,sun4i-osc-clk"; | 57 | compatible = "allwinner,sun4i-a10-osc-clk"; |
| 53 | reg = <0x01c20050 0x4>; | 58 | reg = <0x01c20050 0x4>; |
| 54 | clock-frequency = <24000000>; | 59 | clock-frequency = <24000000>; |
| 60 | clock-output-names = "osc24M"; | ||
| 55 | }; | 61 | }; |
| 56 | 62 | ||
| 57 | osc32k: osc32k { | 63 | osc32k: clk@0 { |
| 58 | #clock-cells = <0>; | 64 | #clock-cells = <0>; |
| 59 | compatible = "fixed-clock"; | 65 | compatible = "fixed-clock"; |
| 60 | clock-frequency = <32768>; | 66 | clock-frequency = <32768>; |
| 67 | clock-output-names = "osc32k"; | ||
| 61 | }; | 68 | }; |
| 62 | 69 | ||
| 63 | pll1: pll1@01c20000 { | 70 | pll1: clk@01c20000 { |
| 64 | #clock-cells = <0>; | 71 | #clock-cells = <0>; |
| 65 | compatible = "allwinner,sun4i-pll1-clk"; | 72 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
| 66 | reg = <0x01c20000 0x4>; | 73 | reg = <0x01c20000 0x4>; |
| 67 | clocks = <&osc24M>; | 74 | clocks = <&osc24M>; |
| 75 | clock-output-names = "pll1"; | ||
| 68 | }; | 76 | }; |
| 69 | 77 | ||
| 70 | pll4: pll4@01c20018 { | 78 | pll4: clk@01c20018 { |
| 71 | #clock-cells = <0>; | 79 | #clock-cells = <0>; |
| 72 | compatible = "allwinner,sun4i-pll1-clk"; | 80 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
| 73 | reg = <0x01c20018 0x4>; | 81 | reg = <0x01c20018 0x4>; |
| 74 | clocks = <&osc24M>; | 82 | clocks = <&osc24M>; |
| 83 | clock-output-names = "pll4"; | ||
| 75 | }; | 84 | }; |
| 76 | 85 | ||
| 77 | pll5: pll5@01c20020 { | 86 | pll5: clk@01c20020 { |
| 78 | #clock-cells = <1>; | 87 | #clock-cells = <1>; |
| 79 | compatible = "allwinner,sun4i-pll5-clk"; | 88 | compatible = "allwinner,sun4i-a10-pll5-clk"; |
| 80 | reg = <0x01c20020 0x4>; | 89 | reg = <0x01c20020 0x4>; |
| 81 | clocks = <&osc24M>; | 90 | clocks = <&osc24M>; |
| 82 | clock-output-names = "pll5_ddr", "pll5_other"; | 91 | clock-output-names = "pll5_ddr", "pll5_other"; |
| 83 | }; | 92 | }; |
| 84 | 93 | ||
| 85 | pll6: pll6@01c20028 { | 94 | pll6: clk@01c20028 { |
| 86 | #clock-cells = <1>; | 95 | #clock-cells = <1>; |
| 87 | compatible = "allwinner,sun4i-pll6-clk"; | 96 | compatible = "allwinner,sun4i-a10-pll6-clk"; |
| 88 | reg = <0x01c20028 0x4>; | 97 | reg = <0x01c20028 0x4>; |
| 89 | clocks = <&osc24M>; | 98 | clocks = <&osc24M>; |
| 90 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; | 99 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; |
| @@ -93,21 +102,23 @@ | |||
| 93 | /* dummy is 200M */ | 102 | /* dummy is 200M */ |
| 94 | cpu: cpu@01c20054 { | 103 | cpu: cpu@01c20054 { |
| 95 | #clock-cells = <0>; | 104 | #clock-cells = <0>; |
| 96 | compatible = "allwinner,sun4i-cpu-clk"; | 105 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
| 97 | reg = <0x01c20054 0x4>; | 106 | reg = <0x01c20054 0x4>; |
| 98 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; | 107 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; |
| 108 | clock-output-names = "cpu"; | ||
| 99 | }; | 109 | }; |
| 100 | 110 | ||
| 101 | axi: axi@01c20054 { | 111 | axi: axi@01c20054 { |
| 102 | #clock-cells = <0>; | 112 | #clock-cells = <0>; |
| 103 | compatible = "allwinner,sun4i-axi-clk"; | 113 | compatible = "allwinner,sun4i-a10-axi-clk"; |
| 104 | reg = <0x01c20054 0x4>; | 114 | reg = <0x01c20054 0x4>; |
| 105 | clocks = <&cpu>; | 115 | clocks = <&cpu>; |
| 116 | clock-output-names = "axi"; | ||
| 106 | }; | 117 | }; |
| 107 | 118 | ||
| 108 | axi_gates: axi_gates@01c2005c { | 119 | axi_gates: clk@01c2005c { |
| 109 | #clock-cells = <1>; | 120 | #clock-cells = <1>; |
| 110 | compatible = "allwinner,sun4i-axi-gates-clk"; | 121 | compatible = "allwinner,sun4i-a10-axi-gates-clk"; |
| 111 | reg = <0x01c2005c 0x4>; | 122 | reg = <0x01c2005c 0x4>; |
| 112 | clocks = <&axi>; | 123 | clocks = <&axi>; |
| 113 | clock-output-names = "axi_dram"; | 124 | clock-output-names = "axi_dram"; |
| @@ -115,12 +126,13 @@ | |||
| 115 | 126 | ||
| 116 | ahb: ahb@01c20054 { | 127 | ahb: ahb@01c20054 { |
| 117 | #clock-cells = <0>; | 128 | #clock-cells = <0>; |
| 118 | compatible = "allwinner,sun4i-ahb-clk"; | 129 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
| 119 | reg = <0x01c20054 0x4>; | 130 | reg = <0x01c20054 0x4>; |
| 120 | clocks = <&axi>; | 131 | clocks = <&axi>; |
| 132 | clock-output-names = "ahb"; | ||
| 121 | }; | 133 | }; |
| 122 | 134 | ||
| 123 | ahb_gates: ahb_gates@01c20060 { | 135 | ahb_gates: clk@01c20060 { |
| 124 | #clock-cells = <1>; | 136 | #clock-cells = <1>; |
| 125 | compatible = "allwinner,sun5i-a13-ahb-gates-clk"; | 137 | compatible = "allwinner,sun5i-a13-ahb-gates-clk"; |
| 126 | reg = <0x01c20060 0x8>; | 138 | reg = <0x01c20060 0x8>; |
| @@ -135,12 +147,13 @@ | |||
| 135 | 147 | ||
| 136 | apb0: apb0@01c20054 { | 148 | apb0: apb0@01c20054 { |
| 137 | #clock-cells = <0>; | 149 | #clock-cells = <0>; |
| 138 | compatible = "allwinner,sun4i-apb0-clk"; | 150 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
| 139 | reg = <0x01c20054 0x4>; | 151 | reg = <0x01c20054 0x4>; |
| 140 | clocks = <&ahb>; | 152 | clocks = <&ahb>; |
| 153 | clock-output-names = "apb0"; | ||
| 141 | }; | 154 | }; |
| 142 | 155 | ||
| 143 | apb0_gates: apb0_gates@01c20068 { | 156 | apb0_gates: clk@01c20068 { |
| 144 | #clock-cells = <1>; | 157 | #clock-cells = <1>; |
| 145 | compatible = "allwinner,sun5i-a13-apb0-gates-clk"; | 158 | compatible = "allwinner,sun5i-a13-apb0-gates-clk"; |
| 146 | reg = <0x01c20068 0x4>; | 159 | reg = <0x01c20068 0x4>; |
| @@ -150,19 +163,21 @@ | |||
| 150 | 163 | ||
| 151 | apb1_mux: apb1_mux@01c20058 { | 164 | apb1_mux: apb1_mux@01c20058 { |
| 152 | #clock-cells = <0>; | 165 | #clock-cells = <0>; |
| 153 | compatible = "allwinner,sun4i-apb1-mux-clk"; | 166 | compatible = "allwinner,sun4i-a10-apb1-mux-clk"; |
| 154 | reg = <0x01c20058 0x4>; | 167 | reg = <0x01c20058 0x4>; |
| 155 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; | 168 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; |
| 169 | clock-output-names = "apb1_mux"; | ||
| 156 | }; | 170 | }; |
| 157 | 171 | ||
| 158 | apb1: apb1@01c20058 { | 172 | apb1: apb1@01c20058 { |
| 159 | #clock-cells = <0>; | 173 | #clock-cells = <0>; |
| 160 | compatible = "allwinner,sun4i-apb1-clk"; | 174 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
| 161 | reg = <0x01c20058 0x4>; | 175 | reg = <0x01c20058 0x4>; |
| 162 | clocks = <&apb1_mux>; | 176 | clocks = <&apb1_mux>; |
| 177 | clock-output-names = "apb1"; | ||
| 163 | }; | 178 | }; |
| 164 | 179 | ||
| 165 | apb1_gates: apb1_gates@01c2006c { | 180 | apb1_gates: clk@01c2006c { |
| 166 | #clock-cells = <1>; | 181 | #clock-cells = <1>; |
| 167 | compatible = "allwinner,sun5i-a13-apb1-gates-clk"; | 182 | compatible = "allwinner,sun5i-a13-apb1-gates-clk"; |
| 168 | reg = <0x01c2006c 0x4>; | 183 | reg = <0x01c2006c 0x4>; |
| @@ -173,7 +188,7 @@ | |||
| 173 | 188 | ||
| 174 | nand_clk: clk@01c20080 { | 189 | nand_clk: clk@01c20080 { |
| 175 | #clock-cells = <0>; | 190 | #clock-cells = <0>; |
| 176 | compatible = "allwinner,sun4i-mod0-clk"; | 191 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 177 | reg = <0x01c20080 0x4>; | 192 | reg = <0x01c20080 0x4>; |
| 178 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 193 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 179 | clock-output-names = "nand"; | 194 | clock-output-names = "nand"; |
| @@ -181,7 +196,7 @@ | |||
| 181 | 196 | ||
| 182 | ms_clk: clk@01c20084 { | 197 | ms_clk: clk@01c20084 { |
| 183 | #clock-cells = <0>; | 198 | #clock-cells = <0>; |
| 184 | compatible = "allwinner,sun4i-mod0-clk"; | 199 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 185 | reg = <0x01c20084 0x4>; | 200 | reg = <0x01c20084 0x4>; |
| 186 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 201 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 187 | clock-output-names = "ms"; | 202 | clock-output-names = "ms"; |
| @@ -189,7 +204,7 @@ | |||
| 189 | 204 | ||
| 190 | mmc0_clk: clk@01c20088 { | 205 | mmc0_clk: clk@01c20088 { |
| 191 | #clock-cells = <0>; | 206 | #clock-cells = <0>; |
| 192 | compatible = "allwinner,sun4i-mod0-clk"; | 207 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 193 | reg = <0x01c20088 0x4>; | 208 | reg = <0x01c20088 0x4>; |
| 194 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 209 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 195 | clock-output-names = "mmc0"; | 210 | clock-output-names = "mmc0"; |
| @@ -197,7 +212,7 @@ | |||
| 197 | 212 | ||
| 198 | mmc1_clk: clk@01c2008c { | 213 | mmc1_clk: clk@01c2008c { |
| 199 | #clock-cells = <0>; | 214 | #clock-cells = <0>; |
| 200 | compatible = "allwinner,sun4i-mod0-clk"; | 215 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 201 | reg = <0x01c2008c 0x4>; | 216 | reg = <0x01c2008c 0x4>; |
| 202 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 217 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 203 | clock-output-names = "mmc1"; | 218 | clock-output-names = "mmc1"; |
| @@ -205,7 +220,7 @@ | |||
| 205 | 220 | ||
| 206 | mmc2_clk: clk@01c20090 { | 221 | mmc2_clk: clk@01c20090 { |
| 207 | #clock-cells = <0>; | 222 | #clock-cells = <0>; |
| 208 | compatible = "allwinner,sun4i-mod0-clk"; | 223 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 209 | reg = <0x01c20090 0x4>; | 224 | reg = <0x01c20090 0x4>; |
| 210 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 225 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 211 | clock-output-names = "mmc2"; | 226 | clock-output-names = "mmc2"; |
| @@ -213,7 +228,7 @@ | |||
| 213 | 228 | ||
| 214 | ts_clk: clk@01c20098 { | 229 | ts_clk: clk@01c20098 { |
| 215 | #clock-cells = <0>; | 230 | #clock-cells = <0>; |
| 216 | compatible = "allwinner,sun4i-mod0-clk"; | 231 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 217 | reg = <0x01c20098 0x4>; | 232 | reg = <0x01c20098 0x4>; |
| 218 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 233 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 219 | clock-output-names = "ts"; | 234 | clock-output-names = "ts"; |
| @@ -221,7 +236,7 @@ | |||
| 221 | 236 | ||
| 222 | ss_clk: clk@01c2009c { | 237 | ss_clk: clk@01c2009c { |
| 223 | #clock-cells = <0>; | 238 | #clock-cells = <0>; |
| 224 | compatible = "allwinner,sun4i-mod0-clk"; | 239 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 225 | reg = <0x01c2009c 0x4>; | 240 | reg = <0x01c2009c 0x4>; |
| 226 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 241 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 227 | clock-output-names = "ss"; | 242 | clock-output-names = "ss"; |
| @@ -229,7 +244,7 @@ | |||
| 229 | 244 | ||
| 230 | spi0_clk: clk@01c200a0 { | 245 | spi0_clk: clk@01c200a0 { |
| 231 | #clock-cells = <0>; | 246 | #clock-cells = <0>; |
| 232 | compatible = "allwinner,sun4i-mod0-clk"; | 247 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 233 | reg = <0x01c200a0 0x4>; | 248 | reg = <0x01c200a0 0x4>; |
| 234 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 249 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 235 | clock-output-names = "spi0"; | 250 | clock-output-names = "spi0"; |
| @@ -237,7 +252,7 @@ | |||
| 237 | 252 | ||
| 238 | spi1_clk: clk@01c200a4 { | 253 | spi1_clk: clk@01c200a4 { |
| 239 | #clock-cells = <0>; | 254 | #clock-cells = <0>; |
| 240 | compatible = "allwinner,sun4i-mod0-clk"; | 255 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 241 | reg = <0x01c200a4 0x4>; | 256 | reg = <0x01c200a4 0x4>; |
| 242 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 257 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 243 | clock-output-names = "spi1"; | 258 | clock-output-names = "spi1"; |
| @@ -245,7 +260,7 @@ | |||
| 245 | 260 | ||
| 246 | spi2_clk: clk@01c200a8 { | 261 | spi2_clk: clk@01c200a8 { |
| 247 | #clock-cells = <0>; | 262 | #clock-cells = <0>; |
| 248 | compatible = "allwinner,sun4i-mod0-clk"; | 263 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 249 | reg = <0x01c200a8 0x4>; | 264 | reg = <0x01c200a8 0x4>; |
| 250 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 265 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 251 | clock-output-names = "spi2"; | 266 | clock-output-names = "spi2"; |
| @@ -253,15 +268,24 @@ | |||
| 253 | 268 | ||
| 254 | ir0_clk: clk@01c200b0 { | 269 | ir0_clk: clk@01c200b0 { |
| 255 | #clock-cells = <0>; | 270 | #clock-cells = <0>; |
| 256 | compatible = "allwinner,sun4i-mod0-clk"; | 271 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 257 | reg = <0x01c200b0 0x4>; | 272 | reg = <0x01c200b0 0x4>; |
| 258 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 273 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 259 | clock-output-names = "ir0"; | 274 | clock-output-names = "ir0"; |
| 260 | }; | 275 | }; |
| 261 | 276 | ||
| 277 | usb_clk: clk@01c200cc { | ||
| 278 | #clock-cells = <1>; | ||
| 279 | #reset-cells = <1>; | ||
| 280 | compatible = "allwinner,sun5i-a13-usb-clk"; | ||
| 281 | reg = <0x01c200cc 0x4>; | ||
| 282 | clocks = <&pll6 1>; | ||
| 283 | clock-output-names = "usb_ohci0", "usb_phy"; | ||
| 284 | }; | ||
| 285 | |||
| 262 | mbus_clk: clk@01c2015c { | 286 | mbus_clk: clk@01c2015c { |
| 263 | #clock-cells = <0>; | 287 | #clock-cells = <0>; |
| 264 | compatible = "allwinner,sun4i-mod0-clk"; | 288 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 265 | reg = <0x01c2015c 0x4>; | 289 | reg = <0x01c2015c 0x4>; |
| 266 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 290 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 267 | clock-output-names = "mbus"; | 291 | clock-output-names = "mbus"; |
| @@ -274,6 +298,71 @@ | |||
| 274 | #size-cells = <1>; | 298 | #size-cells = <1>; |
| 275 | ranges; | 299 | ranges; |
| 276 | 300 | ||
| 301 | spi0: spi@01c05000 { | ||
| 302 | compatible = "allwinner,sun4i-a10-spi"; | ||
| 303 | reg = <0x01c05000 0x1000>; | ||
| 304 | interrupts = <10>; | ||
| 305 | clocks = <&ahb_gates 20>, <&spi0_clk>; | ||
| 306 | clock-names = "ahb", "mod"; | ||
| 307 | status = "disabled"; | ||
| 308 | #address-cells = <1>; | ||
| 309 | #size-cells = <0>; | ||
| 310 | }; | ||
| 311 | |||
| 312 | spi1: spi@01c06000 { | ||
| 313 | compatible = "allwinner,sun4i-a10-spi"; | ||
| 314 | reg = <0x01c06000 0x1000>; | ||
| 315 | interrupts = <11>; | ||
| 316 | clocks = <&ahb_gates 21>, <&spi1_clk>; | ||
| 317 | clock-names = "ahb", "mod"; | ||
| 318 | status = "disabled"; | ||
| 319 | #address-cells = <1>; | ||
| 320 | #size-cells = <0>; | ||
| 321 | }; | ||
| 322 | |||
| 323 | usbphy: phy@01c13400 { | ||
| 324 | #phy-cells = <1>; | ||
| 325 | compatible = "allwinner,sun5i-a13-usb-phy"; | ||
| 326 | reg = <0x01c13400 0x10 0x01c14800 0x4>; | ||
| 327 | reg-names = "phy_ctrl", "pmu1"; | ||
| 328 | clocks = <&usb_clk 8>; | ||
| 329 | clock-names = "usb_phy"; | ||
| 330 | resets = <&usb_clk 1>; | ||
| 331 | reset-names = "usb1_reset"; | ||
| 332 | status = "disabled"; | ||
| 333 | }; | ||
| 334 | |||
| 335 | ehci0: usb@01c14000 { | ||
| 336 | compatible = "allwinner,sun5i-a13-ehci", "generic-ehci"; | ||
| 337 | reg = <0x01c14000 0x100>; | ||
| 338 | interrupts = <39>; | ||
| 339 | clocks = <&ahb_gates 1>; | ||
| 340 | phys = <&usbphy 1>; | ||
| 341 | phy-names = "usb"; | ||
| 342 | status = "disabled"; | ||
| 343 | }; | ||
| 344 | |||
| 345 | ohci0: usb@01c14400 { | ||
| 346 | compatible = "allwinner,sun5i-a13-ohci", "generic-ohci"; | ||
| 347 | reg = <0x01c14400 0x100>; | ||
| 348 | interrupts = <40>; | ||
| 349 | clocks = <&usb_clk 6>, <&ahb_gates 2>; | ||
| 350 | phys = <&usbphy 1>; | ||
| 351 | phy-names = "usb"; | ||
| 352 | status = "disabled"; | ||
| 353 | }; | ||
| 354 | |||
| 355 | spi2: spi@01c17000 { | ||
| 356 | compatible = "allwinner,sun4i-a10-spi"; | ||
| 357 | reg = <0x01c17000 0x1000>; | ||
| 358 | interrupts = <12>; | ||
| 359 | clocks = <&ahb_gates 22>, <&spi2_clk>; | ||
| 360 | clock-names = "ahb", "mod"; | ||
| 361 | status = "disabled"; | ||
| 362 | #address-cells = <1>; | ||
| 363 | #size-cells = <0>; | ||
| 364 | }; | ||
| 365 | |||
| 277 | intc: interrupt-controller@01c20400 { | 366 | intc: interrupt-controller@01c20400 { |
| 278 | compatible = "allwinner,sun4i-ic"; | 367 | compatible = "allwinner,sun4i-ic"; |
| 279 | reg = <0x01c20400 0x400>; | 368 | reg = <0x01c20400 0x400>; |
| @@ -336,7 +425,7 @@ | |||
| 336 | }; | 425 | }; |
| 337 | 426 | ||
| 338 | wdt: watchdog@01c20c90 { | 427 | wdt: watchdog@01c20c90 { |
| 339 | compatible = "allwinner,sun4i-wdt"; | 428 | compatible = "allwinner,sun4i-a10-wdt"; |
| 340 | reg = <0x01c20c90 0x10>; | 429 | reg = <0x01c20c90 0x10>; |
| 341 | }; | 430 | }; |
| 342 | 431 | ||
diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts index e5adae30899b..3898a7bce831 100644 --- a/arch/arm/boot/dts/sun6i-a31-colombus.dts +++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts | |||
| @@ -28,5 +28,23 @@ | |||
| 28 | pinctrl-0 = <&uart0_pins_a>; | 28 | pinctrl-0 = <&uart0_pins_a>; |
| 29 | status = "okay"; | 29 | status = "okay"; |
| 30 | }; | 30 | }; |
| 31 | |||
| 32 | i2c0: i2c@01c2ac00 { | ||
| 33 | pinctrl-names = "default"; | ||
| 34 | pinctrl-0 = <&i2c0_pins_a>; | ||
| 35 | status = "fail"; | ||
| 36 | }; | ||
| 37 | |||
| 38 | i2c1: i2c@01c2b000 { | ||
| 39 | pinctrl-names = "default"; | ||
| 40 | pinctrl-0 = <&i2c1_pins_a>; | ||
| 41 | status = "okay"; | ||
| 42 | }; | ||
| 43 | |||
| 44 | i2c2: i2c@01c2b400 { | ||
| 45 | pinctrl-names = "default"; | ||
| 46 | pinctrl-0 = <&i2c2_pins_a>; | ||
| 47 | status = "okay"; | ||
| 48 | }; | ||
| 31 | }; | 49 | }; |
| 32 | }; | 50 | }; |
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 5256ad9be52c..922864c2e1a1 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi | |||
| @@ -16,6 +16,16 @@ | |||
| 16 | / { | 16 | / { |
| 17 | interrupt-parent = <&gic>; | 17 | interrupt-parent = <&gic>; |
| 18 | 18 | ||
| 19 | aliases { | ||
| 20 | serial0 = &uart0; | ||
| 21 | serial1 = &uart1; | ||
| 22 | serial2 = &uart2; | ||
| 23 | serial3 = &uart3; | ||
| 24 | serial4 = &uart4; | ||
| 25 | serial5 = &uart5; | ||
| 26 | }; | ||
| 27 | |||
| 28 | |||
| 19 | cpus { | 29 | cpus { |
| 20 | #address-cells = <1>; | 30 | #address-cells = <1>; |
| 21 | #size-cells = <0>; | 31 | #size-cells = <0>; |
| @@ -60,34 +70,32 @@ | |||
| 60 | clock-frequency = <24000000>; | 70 | clock-frequency = <24000000>; |
| 61 | }; | 71 | }; |
| 62 | 72 | ||
| 63 | osc32k: osc32k { | 73 | osc32k: clk@0 { |
| 64 | #clock-cells = <0>; | 74 | #clock-cells = <0>; |
| 65 | compatible = "fixed-clock"; | 75 | compatible = "fixed-clock"; |
| 66 | clock-frequency = <32768>; | 76 | clock-frequency = <32768>; |
| 77 | clock-output-names = "osc32k"; | ||
| 67 | }; | 78 | }; |
| 68 | 79 | ||
| 69 | pll1: pll1@01c20000 { | 80 | pll1: clk@01c20000 { |
| 70 | #clock-cells = <0>; | 81 | #clock-cells = <0>; |
| 71 | compatible = "allwinner,sun6i-a31-pll1-clk"; | 82 | compatible = "allwinner,sun6i-a31-pll1-clk"; |
| 72 | reg = <0x01c20000 0x4>; | 83 | reg = <0x01c20000 0x4>; |
| 73 | clocks = <&osc24M>; | 84 | clocks = <&osc24M>; |
| 85 | clock-output-names = "pll1"; | ||
| 74 | }; | 86 | }; |
| 75 | 87 | ||
| 76 | /* | 88 | pll6: clk@01c20028 { |
| 77 | * This is a dummy clock, to be used as placeholder on | ||
| 78 | * other mux clocks when a specific parent clock is not | ||
| 79 | * yet implemented. It should be dropped when the driver | ||
| 80 | * is complete. | ||
| 81 | */ | ||
| 82 | pll6: pll6 { | ||
| 83 | #clock-cells = <0>; | 89 | #clock-cells = <0>; |
| 84 | compatible = "fixed-clock"; | 90 | compatible = "allwinner,sun6i-a31-pll6-clk"; |
| 85 | clock-frequency = <0>; | 91 | reg = <0x01c20028 0x4>; |
| 92 | clocks = <&osc24M>; | ||
| 93 | clock-output-names = "pll6"; | ||
| 86 | }; | 94 | }; |
| 87 | 95 | ||
| 88 | cpu: cpu@01c20050 { | 96 | cpu: cpu@01c20050 { |
| 89 | #clock-cells = <0>; | 97 | #clock-cells = <0>; |
| 90 | compatible = "allwinner,sun4i-cpu-clk"; | 98 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
| 91 | reg = <0x01c20050 0x4>; | 99 | reg = <0x01c20050 0x4>; |
| 92 | 100 | ||
| 93 | /* | 101 | /* |
| @@ -97,13 +105,15 @@ | |||
| 97 | * Allwinner. | 105 | * Allwinner. |
| 98 | */ | 106 | */ |
| 99 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; | 107 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; |
| 108 | clock-output-names = "cpu"; | ||
| 100 | }; | 109 | }; |
| 101 | 110 | ||
| 102 | axi: axi@01c20050 { | 111 | axi: axi@01c20050 { |
| 103 | #clock-cells = <0>; | 112 | #clock-cells = <0>; |
| 104 | compatible = "allwinner,sun4i-axi-clk"; | 113 | compatible = "allwinner,sun4i-a10-axi-clk"; |
| 105 | reg = <0x01c20050 0x4>; | 114 | reg = <0x01c20050 0x4>; |
| 106 | clocks = <&cpu>; | 115 | clocks = <&cpu>; |
| 116 | clock-output-names = "axi"; | ||
| 107 | }; | 117 | }; |
| 108 | 118 | ||
| 109 | ahb1_mux: ahb1_mux@01c20054 { | 119 | ahb1_mux: ahb1_mux@01c20054 { |
| @@ -111,16 +121,18 @@ | |||
| 111 | compatible = "allwinner,sun6i-a31-ahb1-mux-clk"; | 121 | compatible = "allwinner,sun6i-a31-ahb1-mux-clk"; |
| 112 | reg = <0x01c20054 0x4>; | 122 | reg = <0x01c20054 0x4>; |
| 113 | clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>; | 123 | clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>; |
| 124 | clock-output-names = "ahb1_mux"; | ||
| 114 | }; | 125 | }; |
| 115 | 126 | ||
| 116 | ahb1: ahb1@01c20054 { | 127 | ahb1: ahb1@01c20054 { |
| 117 | #clock-cells = <0>; | 128 | #clock-cells = <0>; |
| 118 | compatible = "allwinner,sun4i-ahb-clk"; | 129 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
| 119 | reg = <0x01c20054 0x4>; | 130 | reg = <0x01c20054 0x4>; |
| 120 | clocks = <&ahb1_mux>; | 131 | clocks = <&ahb1_mux>; |
| 132 | clock-output-names = "ahb1"; | ||
| 121 | }; | 133 | }; |
| 122 | 134 | ||
| 123 | ahb1_gates: ahb1_gates@01c20060 { | 135 | ahb1_gates: clk@01c20060 { |
| 124 | #clock-cells = <1>; | 136 | #clock-cells = <1>; |
| 125 | compatible = "allwinner,sun6i-a31-ahb1-gates-clk"; | 137 | compatible = "allwinner,sun6i-a31-ahb1-gates-clk"; |
| 126 | reg = <0x01c20060 0x8>; | 138 | reg = <0x01c20060 0x8>; |
| @@ -143,12 +155,13 @@ | |||
| 143 | 155 | ||
| 144 | apb1: apb1@01c20054 { | 156 | apb1: apb1@01c20054 { |
| 145 | #clock-cells = <0>; | 157 | #clock-cells = <0>; |
| 146 | compatible = "allwinner,sun4i-apb0-clk"; | 158 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
| 147 | reg = <0x01c20054 0x4>; | 159 | reg = <0x01c20054 0x4>; |
| 148 | clocks = <&ahb1>; | 160 | clocks = <&ahb1>; |
| 161 | clock-output-names = "apb1"; | ||
| 149 | }; | 162 | }; |
| 150 | 163 | ||
| 151 | apb1_gates: apb1_gates@01c20060 { | 164 | apb1_gates: clk@01c20068 { |
| 152 | #clock-cells = <1>; | 165 | #clock-cells = <1>; |
| 153 | compatible = "allwinner,sun6i-a31-apb1-gates-clk"; | 166 | compatible = "allwinner,sun6i-a31-apb1-gates-clk"; |
| 154 | reg = <0x01c20068 0x4>; | 167 | reg = <0x01c20068 0x4>; |
| @@ -160,9 +173,10 @@ | |||
| 160 | 173 | ||
| 161 | apb2_mux: apb2_mux@01c20058 { | 174 | apb2_mux: apb2_mux@01c20058 { |
| 162 | #clock-cells = <0>; | 175 | #clock-cells = <0>; |
| 163 | compatible = "allwinner,sun4i-apb1-mux-clk"; | 176 | compatible = "allwinner,sun4i-a10-apb1-mux-clk"; |
| 164 | reg = <0x01c20058 0x4>; | 177 | reg = <0x01c20058 0x4>; |
| 165 | clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; | 178 | clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; |
| 179 | clock-output-names = "apb2_mux"; | ||
| 166 | }; | 180 | }; |
| 167 | 181 | ||
| 168 | apb2: apb2@01c20058 { | 182 | apb2: apb2@01c20058 { |
| @@ -170,9 +184,10 @@ | |||
| 170 | compatible = "allwinner,sun6i-a31-apb2-div-clk"; | 184 | compatible = "allwinner,sun6i-a31-apb2-div-clk"; |
| 171 | reg = <0x01c20058 0x4>; | 185 | reg = <0x01c20058 0x4>; |
| 172 | clocks = <&apb2_mux>; | 186 | clocks = <&apb2_mux>; |
| 187 | clock-output-names = "apb2"; | ||
| 173 | }; | 188 | }; |
| 174 | 189 | ||
| 175 | apb2_gates: apb2_gates@01c2006c { | 190 | apb2_gates: clk@01c2006c { |
| 176 | #clock-cells = <1>; | 191 | #clock-cells = <1>; |
| 177 | compatible = "allwinner,sun6i-a31-apb2-gates-clk"; | 192 | compatible = "allwinner,sun6i-a31-apb2-gates-clk"; |
| 178 | reg = <0x01c2006c 0x4>; | 193 | reg = <0x01c2006c 0x4>; |
| @@ -182,6 +197,38 @@ | |||
| 182 | "apb2_uart1", "apb2_uart2", "apb2_uart3", | 197 | "apb2_uart1", "apb2_uart2", "apb2_uart3", |
| 183 | "apb2_uart4", "apb2_uart5"; | 198 | "apb2_uart4", "apb2_uart5"; |
| 184 | }; | 199 | }; |
| 200 | |||
| 201 | spi0_clk: clk@01c200a0 { | ||
| 202 | #clock-cells = <0>; | ||
| 203 | compatible = "allwinner,sun4i-a10-mod0-clk"; | ||
| 204 | reg = <0x01c200a0 0x4>; | ||
| 205 | clocks = <&osc24M>, <&pll6>; | ||
| 206 | clock-output-names = "spi0"; | ||
| 207 | }; | ||
| 208 | |||
| 209 | spi1_clk: clk@01c200a4 { | ||
| 210 | #clock-cells = <0>; | ||
| 211 | compatible = "allwinner,sun4i-a10-mod0-clk"; | ||
| 212 | reg = <0x01c200a4 0x4>; | ||
| 213 | clocks = <&osc24M>, <&pll6>; | ||
| 214 | clock-output-names = "spi1"; | ||
| 215 | }; | ||
| 216 | |||
| 217 | spi2_clk: clk@01c200a8 { | ||
| 218 | #clock-cells = <0>; | ||
| 219 | compatible = "allwinner,sun4i-a10-mod0-clk"; | ||
| 220 | reg = <0x01c200a8 0x4>; | ||
| 221 | clocks = <&osc24M>, <&pll6>; | ||
| 222 | clock-output-names = "spi2"; | ||
| 223 | }; | ||
| 224 | |||
| 225 | spi3_clk: clk@01c200ac { | ||
| 226 | #clock-cells = <0>; | ||
| 227 | compatible = "allwinner,sun4i-a10-mod0-clk"; | ||
| 228 | reg = <0x01c200ac 0x4>; | ||
| 229 | clocks = <&osc24M>, <&pll6>; | ||
| 230 | clock-output-names = "spi3"; | ||
| 231 | }; | ||
| 185 | }; | 232 | }; |
| 186 | 233 | ||
| 187 | soc@01c00000 { | 234 | soc@01c00000 { |
| @@ -210,6 +257,27 @@ | |||
| 210 | allwinner,drive = <0>; | 257 | allwinner,drive = <0>; |
| 211 | allwinner,pull = <0>; | 258 | allwinner,pull = <0>; |
| 212 | }; | 259 | }; |
| 260 | |||
| 261 | i2c0_pins_a: i2c0@0 { | ||
| 262 | allwinner,pins = "PH14", "PH15"; | ||
| 263 | allwinner,function = "i2c0"; | ||
| 264 | allwinner,drive = <0>; | ||
| 265 | allwinner,pull = <0>; | ||
| 266 | }; | ||
| 267 | |||
| 268 | i2c1_pins_a: i2c1@0 { | ||
| 269 | allwinner,pins = "PH16", "PH17"; | ||
| 270 | allwinner,function = "i2c1"; | ||
| 271 | allwinner,drive = <0>; | ||
| 272 | allwinner,pull = <0>; | ||
| 273 | }; | ||
| 274 | |||
| 275 | i2c2_pins_a: i2c2@0 { | ||
| 276 | allwinner,pins = "PH18", "PH19"; | ||
| 277 | allwinner,function = "i2c2"; | ||
| 278 | allwinner,drive = <0>; | ||
| 279 | allwinner,pull = <0>; | ||
| 280 | }; | ||
| 213 | }; | 281 | }; |
| 214 | 282 | ||
| 215 | ahb1_rst: reset@01c202c0 { | 283 | ahb1_rst: reset@01c202c0 { |
| @@ -242,7 +310,7 @@ | |||
| 242 | }; | 310 | }; |
| 243 | 311 | ||
| 244 | wdt1: watchdog@01c20ca0 { | 312 | wdt1: watchdog@01c20ca0 { |
| 245 | compatible = "allwinner,sun6i-wdt"; | 313 | compatible = "allwinner,sun6i-a31-wdt"; |
| 246 | reg = <0x01c20ca0 0x20>; | 314 | reg = <0x01c20ca0 0x20>; |
| 247 | }; | 315 | }; |
| 248 | 316 | ||
| @@ -312,6 +380,86 @@ | |||
| 312 | status = "disabled"; | 380 | status = "disabled"; |
| 313 | }; | 381 | }; |
| 314 | 382 | ||
| 383 | i2c0: i2c@01c2ac00 { | ||
| 384 | compatible = "allwinner,sun6i-a31-i2c"; | ||
| 385 | reg = <0x01c2ac00 0x400>; | ||
| 386 | interrupts = <0 6 4>; | ||
| 387 | clocks = <&apb2_gates 0>; | ||
| 388 | clock-frequency = <100000>; | ||
| 389 | resets = <&apb2_rst 0>; | ||
| 390 | status = "disabled"; | ||
| 391 | }; | ||
| 392 | |||
| 393 | i2c1: i2c@01c2b000 { | ||
| 394 | compatible = "allwinner,sun6i-a31-i2c"; | ||
| 395 | reg = <0x01c2b000 0x400>; | ||
| 396 | interrupts = <0 7 4>; | ||
| 397 | clocks = <&apb2_gates 1>; | ||
| 398 | clock-frequency = <100000>; | ||
| 399 | resets = <&apb2_rst 1>; | ||
| 400 | status = "disabled"; | ||
| 401 | }; | ||
| 402 | |||
| 403 | i2c2: i2c@01c2b400 { | ||
| 404 | compatible = "allwinner,sun6i-a31-i2c"; | ||
| 405 | reg = <0x01c2b400 0x400>; | ||
| 406 | interrupts = <0 8 4>; | ||
| 407 | clocks = <&apb2_gates 2>; | ||
| 408 | clock-frequency = <100000>; | ||
| 409 | resets = <&apb2_rst 2>; | ||
| 410 | status = "disabled"; | ||
| 411 | }; | ||
| 412 | |||
| 413 | i2c3: i2c@01c2b800 { | ||
| 414 | compatible = "allwinner,sun6i-a31-i2c"; | ||
| 415 | reg = <0x01c2b800 0x400>; | ||
| 416 | interrupts = <0 9 4>; | ||
| 417 | clocks = <&apb2_gates 3>; | ||
| 418 | clock-frequency = <100000>; | ||
| 419 | resets = <&apb2_rst 3>; | ||
| 420 | status = "disabled"; | ||
| 421 | }; | ||
| 422 | |||
| 423 | spi0: spi@01c68000 { | ||
| 424 | compatible = "allwinner,sun6i-a31-spi"; | ||
| 425 | reg = <0x01c68000 0x1000>; | ||
| 426 | interrupts = <0 65 4>; | ||
| 427 | clocks = <&ahb1_gates 20>, <&spi0_clk>; | ||
| 428 | clock-names = "ahb", "mod"; | ||
| 429 | resets = <&ahb1_rst 20>; | ||
| 430 | status = "disabled"; | ||
| 431 | }; | ||
| 432 | |||
| 433 | spi1: spi@01c69000 { | ||
| 434 | compatible = "allwinner,sun6i-a31-spi"; | ||
| 435 | reg = <0x01c69000 0x1000>; | ||
| 436 | interrupts = <0 66 4>; | ||
| 437 | clocks = <&ahb1_gates 21>, <&spi1_clk>; | ||
| 438 | clock-names = "ahb", "mod"; | ||
| 439 | resets = <&ahb1_rst 21>; | ||
| 440 | status = "disabled"; | ||
| 441 | }; | ||
| 442 | |||
| 443 | spi2: spi@01c6a000 { | ||
| 444 | compatible = "allwinner,sun6i-a31-spi"; | ||
| 445 | reg = <0x01c6a000 0x1000>; | ||
| 446 | interrupts = <0 67 4>; | ||
| 447 | clocks = <&ahb1_gates 22>, <&spi2_clk>; | ||
| 448 | clock-names = "ahb", "mod"; | ||
| 449 | resets = <&ahb1_rst 22>; | ||
| 450 | status = "disabled"; | ||
| 451 | }; | ||
| 452 | |||
| 453 | spi3: spi@01c6b000 { | ||
| 454 | compatible = "allwinner,sun6i-a31-spi"; | ||
| 455 | reg = <0x01c6b000 0x1000>; | ||
| 456 | interrupts = <0 68 4>; | ||
| 457 | clocks = <&ahb1_gates 23>, <&spi3_clk>; | ||
| 458 | clock-names = "ahb", "mod"; | ||
| 459 | resets = <&ahb1_rst 23>; | ||
| 460 | status = "disabled"; | ||
| 461 | }; | ||
| 462 | |||
| 315 | gic: interrupt-controller@01c81000 { | 463 | gic: interrupt-controller@01c81000 { |
| 316 | compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; | 464 | compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; |
| 317 | reg = <0x01c81000 0x1000>, | 465 | reg = <0x01c81000 0x1000>, |
diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts index 5c51cb8a98b0..68de89ffbdfa 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | |||
| @@ -13,25 +13,38 @@ | |||
| 13 | 13 | ||
| 14 | /dts-v1/; | 14 | /dts-v1/; |
| 15 | /include/ "sun7i-a20.dtsi" | 15 | /include/ "sun7i-a20.dtsi" |
| 16 | /include/ "sunxi-common-regulators.dtsi" | ||
| 16 | 17 | ||
| 17 | / { | 18 | / { |
| 18 | model = "Cubietech Cubieboard2"; | 19 | model = "Cubietech Cubieboard2"; |
| 19 | compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20"; | 20 | compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20"; |
| 20 | 21 | ||
| 21 | soc@01c00000 { | 22 | soc@01c00000 { |
| 22 | emac: ethernet@01c0b000 { | 23 | usbphy: phy@01c13400 { |
| 23 | pinctrl-names = "default"; | 24 | usb1_vbus-supply = <®_usb1_vbus>; |
| 24 | pinctrl-0 = <&emac_pins_a>; | 25 | usb2_vbus-supply = <®_usb2_vbus>; |
| 25 | phy = <&phy1>; | ||
| 26 | status = "okay"; | 26 | status = "okay"; |
| 27 | }; | 27 | }; |
| 28 | 28 | ||
| 29 | mdio@01c0b080 { | 29 | ehci0: usb@01c14000 { |
| 30 | status = "okay"; | 30 | status = "okay"; |
| 31 | }; | ||
| 31 | 32 | ||
| 32 | phy1: ethernet-phy@1 { | 33 | ohci0: usb@01c14400 { |
| 33 | reg = <1>; | 34 | status = "okay"; |
| 34 | }; | 35 | }; |
| 36 | |||
| 37 | ahci: sata@01c18000 { | ||
| 38 | target-supply = <®_ahci_5v>; | ||
| 39 | status = "okay"; | ||
| 40 | }; | ||
| 41 | |||
| 42 | ehci1: usb@01c1c000 { | ||
| 43 | status = "okay"; | ||
| 44 | }; | ||
| 45 | |||
| 46 | ohci1: usb@01c1c400 { | ||
| 47 | status = "okay"; | ||
| 35 | }; | 48 | }; |
| 36 | 49 | ||
| 37 | pinctrl@01c20800 { | 50 | pinctrl@01c20800 { |
| @@ -60,6 +73,18 @@ | |||
| 60 | pinctrl-0 = <&i2c1_pins_a>; | 73 | pinctrl-0 = <&i2c1_pins_a>; |
| 61 | status = "okay"; | 74 | status = "okay"; |
| 62 | }; | 75 | }; |
| 76 | |||
| 77 | gmac: ethernet@01c50000 { | ||
| 78 | pinctrl-names = "default"; | ||
| 79 | pinctrl-0 = <&gmac_pins_mii_a>; | ||
| 80 | phy = <&phy1>; | ||
| 81 | phy-mode = "mii"; | ||
| 82 | status = "okay"; | ||
| 83 | |||
| 84 | phy1: ethernet-phy@1 { | ||
| 85 | reg = <1>; | ||
| 86 | }; | ||
| 87 | }; | ||
| 63 | }; | 88 | }; |
| 64 | 89 | ||
| 65 | leds { | 90 | leds { |
| @@ -77,4 +102,16 @@ | |||
| 77 | gpios = <&pio 7 20 0>; | 102 | gpios = <&pio 7 20 0>; |
| 78 | }; | 103 | }; |
| 79 | }; | 104 | }; |
| 105 | |||
| 106 | reg_ahci_5v: ahci-5v { | ||
| 107 | status = "okay"; | ||
| 108 | }; | ||
| 109 | |||
| 110 | reg_usb1_vbus: usb1-vbus { | ||
| 111 | status = "okay"; | ||
| 112 | }; | ||
| 113 | |||
| 114 | reg_usb2_vbus: usb2-vbus { | ||
| 115 | status = "okay"; | ||
| 116 | }; | ||
| 80 | }; | 117 | }; |
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index f9dcb61a5305..cb25d3c8da58 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts | |||
| @@ -13,13 +13,48 @@ | |||
| 13 | 13 | ||
| 14 | /dts-v1/; | 14 | /dts-v1/; |
| 15 | /include/ "sun7i-a20.dtsi" | 15 | /include/ "sun7i-a20.dtsi" |
| 16 | /include/ "sunxi-common-regulators.dtsi" | ||
| 16 | 17 | ||
| 17 | / { | 18 | / { |
| 18 | model = "Cubietech Cubietruck"; | 19 | model = "Cubietech Cubietruck"; |
| 19 | compatible = "cubietech,cubietruck", "allwinner,sun7i-a20"; | 20 | compatible = "cubietech,cubietruck", "allwinner,sun7i-a20"; |
| 20 | 21 | ||
| 21 | soc@01c00000 { | 22 | soc@01c00000 { |
| 23 | usbphy: phy@01c13400 { | ||
| 24 | usb1_vbus-supply = <®_usb1_vbus>; | ||
| 25 | usb2_vbus-supply = <®_usb2_vbus>; | ||
| 26 | status = "okay"; | ||
| 27 | }; | ||
| 28 | |||
| 29 | ehci0: usb@01c14000 { | ||
| 30 | status = "okay"; | ||
| 31 | }; | ||
| 32 | |||
| 33 | ohci0: usb@01c14400 { | ||
| 34 | status = "okay"; | ||
| 35 | }; | ||
| 36 | |||
| 37 | ahci: sata@01c18000 { | ||
| 38 | target-supply = <®_ahci_5v>; | ||
| 39 | status = "okay"; | ||
| 40 | }; | ||
| 41 | |||
| 42 | ehci1: usb@01c1c000 { | ||
| 43 | status = "okay"; | ||
| 44 | }; | ||
| 45 | |||
| 46 | ohci1: usb@01c1c400 { | ||
| 47 | status = "okay"; | ||
| 48 | }; | ||
| 49 | |||
| 22 | pinctrl@01c20800 { | 50 | pinctrl@01c20800 { |
| 51 | ahci_pwr_pin_cubietruck: ahci_pwr_pin@1 { | ||
| 52 | allwinner,pins = "PH12"; | ||
| 53 | allwinner,function = "gpio_out"; | ||
| 54 | allwinner,drive = <0>; | ||
| 55 | allwinner,pull = <0>; | ||
| 56 | }; | ||
| 57 | |||
| 23 | led_pins_cubietruck: led_pins@0 { | 58 | led_pins_cubietruck: led_pins@0 { |
| 24 | allwinner,pins = "PH7", "PH11", "PH20", "PH21"; | 59 | allwinner,pins = "PH7", "PH11", "PH20", "PH21"; |
| 25 | allwinner,function = "gpio_out"; | 60 | allwinner,function = "gpio_out"; |
| @@ -51,6 +86,18 @@ | |||
| 51 | pinctrl-0 = <&i2c2_pins_a>; | 86 | pinctrl-0 = <&i2c2_pins_a>; |
| 52 | status = "okay"; | 87 | status = "okay"; |
| 53 | }; | 88 | }; |
| 89 | |||
| 90 | gmac: ethernet@01c50000 { | ||
| 91 | pinctrl-names = "default"; | ||
| 92 | pinctrl-0 = <&gmac_pins_rgmii_a>; | ||
| 93 | phy = <&phy1>; | ||
| 94 | phy-mode = "rgmii"; | ||
| 95 | status = "okay"; | ||
| 96 | |||
| 97 | phy1: ethernet-phy@1 { | ||
| 98 | reg = <1>; | ||
| 99 | }; | ||
| 100 | }; | ||
| 54 | }; | 101 | }; |
| 55 | 102 | ||
| 56 | leds { | 103 | leds { |
| @@ -78,4 +125,18 @@ | |||
| 78 | gpios = <&pio 7 7 0>; | 125 | gpios = <&pio 7 7 0>; |
| 79 | }; | 126 | }; |
| 80 | }; | 127 | }; |
| 128 | |||
| 129 | reg_ahci_5v: ahci-5v { | ||
| 130 | pinctrl-0 = <&ahci_pwr_pin_cubietruck>; | ||
| 131 | gpio = <&pio 7 12 0>; | ||
| 132 | status = "okay"; | ||
| 133 | }; | ||
| 134 | |||
| 135 | reg_usb1_vbus: usb1-vbus { | ||
| 136 | status = "okay"; | ||
| 137 | }; | ||
| 138 | |||
| 139 | reg_usb2_vbus: usb2-vbus { | ||
| 140 | status = "okay"; | ||
| 141 | }; | ||
| 81 | }; | 142 | }; |
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts index ead3013f9aca..eeadf76362fa 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | |||
| @@ -13,25 +13,55 @@ | |||
| 13 | 13 | ||
| 14 | /dts-v1/; | 14 | /dts-v1/; |
| 15 | /include/ "sun7i-a20.dtsi" | 15 | /include/ "sun7i-a20.dtsi" |
| 16 | /include/ "sunxi-common-regulators.dtsi" | ||
| 16 | 17 | ||
| 17 | / { | 18 | / { |
| 18 | model = "Olimex A20-Olinuxino Micro"; | 19 | model = "Olimex A20-Olinuxino Micro"; |
| 19 | compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20"; | 20 | compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20"; |
| 20 | 21 | ||
| 22 | aliases { | ||
| 23 | spi0 = &spi1; | ||
| 24 | spi1 = &spi2; | ||
| 25 | }; | ||
| 26 | |||
| 21 | soc@01c00000 { | 27 | soc@01c00000 { |
| 22 | emac: ethernet@01c0b000 { | 28 | spi1: spi@01c06000 { |
| 23 | pinctrl-names = "default"; | 29 | pinctrl-names = "default"; |
| 24 | pinctrl-0 = <&emac_pins_a>; | 30 | pinctrl-0 = <&spi1_pins_a>; |
| 25 | phy = <&phy1>; | ||
| 26 | status = "okay"; | 31 | status = "okay"; |
| 27 | }; | 32 | }; |
| 28 | 33 | ||
| 29 | mdio@01c0b080 { | 34 | usbphy: phy@01c13400 { |
| 35 | usb1_vbus-supply = <®_usb1_vbus>; | ||
| 36 | usb2_vbus-supply = <®_usb2_vbus>; | ||
| 30 | status = "okay"; | 37 | status = "okay"; |
| 38 | }; | ||
| 31 | 39 | ||
| 32 | phy1: ethernet-phy@1 { | 40 | ehci0: usb@01c14000 { |
| 33 | reg = <1>; | 41 | status = "okay"; |
| 34 | }; | 42 | }; |
| 43 | |||
| 44 | ohci0: usb@01c14400 { | ||
| 45 | status = "okay"; | ||
| 46 | }; | ||
| 47 | |||
| 48 | spi2: spi@01c17000 { | ||
| 49 | pinctrl-names = "default"; | ||
| 50 | pinctrl-0 = <&spi2_pins_a>; | ||
| 51 | status = "okay"; | ||
| 52 | }; | ||
| 53 | |||
| 54 | ahci: sata@01c18000 { | ||
| 55 | target-supply = <®_ahci_5v>; | ||
| 56 | status = "okay"; | ||
| 57 | }; | ||
| 58 | |||
| 59 | ehci1: usb@01c1c000 { | ||
| 60 | status = "okay"; | ||
| 61 | }; | ||
| 62 | |||
| 63 | ohci1: usb@01c1c400 { | ||
| 64 | status = "okay"; | ||
| 35 | }; | 65 | }; |
| 36 | 66 | ||
| 37 | pinctrl@01c20800 { | 67 | pinctrl@01c20800 { |
| @@ -78,6 +108,18 @@ | |||
| 78 | pinctrl-0 = <&i2c2_pins_a>; | 108 | pinctrl-0 = <&i2c2_pins_a>; |
| 79 | status = "okay"; | 109 | status = "okay"; |
| 80 | }; | 110 | }; |
| 111 | |||
| 112 | gmac: ethernet@01c50000 { | ||
| 113 | pinctrl-names = "default"; | ||
| 114 | pinctrl-0 = <&gmac_pins_mii_a>; | ||
| 115 | phy = <&phy1>; | ||
| 116 | phy-mode = "mii"; | ||
| 117 | status = "okay"; | ||
| 118 | |||
| 119 | phy1: ethernet-phy@1 { | ||
| 120 | reg = <1>; | ||
| 121 | }; | ||
| 122 | }; | ||
| 81 | }; | 123 | }; |
| 82 | 124 | ||
| 83 | leds { | 125 | leds { |
| @@ -91,4 +133,16 @@ | |||
| 91 | default-state = "on"; | 133 | default-state = "on"; |
| 92 | }; | 134 | }; |
| 93 | }; | 135 | }; |
| 136 | |||
| 137 | reg_ahci_5v: ahci-5v { | ||
| 138 | status = "okay"; | ||
| 139 | }; | ||
| 140 | |||
| 141 | reg_usb1_vbus: usb1-vbus { | ||
| 142 | status = "okay"; | ||
| 143 | }; | ||
| 144 | |||
| 145 | reg_usb2_vbus: usb2-vbus { | ||
| 146 | status = "okay"; | ||
| 147 | }; | ||
| 94 | }; | 148 | }; |
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 9ff09484847b..dadb3812342f 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi | |||
| @@ -17,7 +17,15 @@ | |||
| 17 | interrupt-parent = <&gic>; | 17 | interrupt-parent = <&gic>; |
| 18 | 18 | ||
| 19 | aliases { | 19 | aliases { |
| 20 | ethernet0 = &emac; | 20 | ethernet0 = &gmac; |
| 21 | serial0 = &uart0; | ||
| 22 | serial1 = &uart1; | ||
| 23 | serial2 = &uart2; | ||
| 24 | serial3 = &uart3; | ||
| 25 | serial4 = &uart4; | ||
| 26 | serial5 = &uart5; | ||
| 27 | serial6 = &uart6; | ||
| 28 | serial7 = &uart7; | ||
| 21 | }; | 29 | }; |
| 22 | 30 | ||
| 23 | cpus { | 31 | cpus { |
| @@ -41,16 +49,25 @@ | |||
| 41 | reg = <0x40000000 0x80000000>; | 49 | reg = <0x40000000 0x80000000>; |
| 42 | }; | 50 | }; |
| 43 | 51 | ||
| 52 | timer { | ||
| 53 | compatible = "arm,armv7-timer"; | ||
| 54 | interrupts = <1 13 0xf08>, | ||
| 55 | <1 14 0xf08>, | ||
| 56 | <1 11 0xf08>, | ||
| 57 | <1 10 0xf08>; | ||
| 58 | }; | ||
| 59 | |||
| 44 | clocks { | 60 | clocks { |
| 45 | #address-cells = <1>; | 61 | #address-cells = <1>; |
| 46 | #size-cells = <1>; | 62 | #size-cells = <1>; |
| 47 | ranges; | 63 | ranges; |
| 48 | 64 | ||
| 49 | osc24M: osc24M@01c20050 { | 65 | osc24M: clk@01c20050 { |
| 50 | #clock-cells = <0>; | 66 | #clock-cells = <0>; |
| 51 | compatible = "allwinner,sun4i-osc-clk"; | 67 | compatible = "allwinner,sun4i-a10-osc-clk"; |
| 52 | reg = <0x01c20050 0x4>; | 68 | reg = <0x01c20050 0x4>; |
| 53 | clock-frequency = <24000000>; | 69 | clock-frequency = <24000000>; |
| 70 | clock-output-names = "osc24M"; | ||
| 54 | }; | 71 | }; |
| 55 | 72 | ||
| 56 | osc32k: clk@0 { | 73 | osc32k: clk@0 { |
| @@ -60,31 +77,33 @@ | |||
| 60 | clock-output-names = "osc32k"; | 77 | clock-output-names = "osc32k"; |
| 61 | }; | 78 | }; |
| 62 | 79 | ||
| 63 | pll1: pll1@01c20000 { | 80 | pll1: clk@01c20000 { |
| 64 | #clock-cells = <0>; | 81 | #clock-cells = <0>; |
| 65 | compatible = "allwinner,sun4i-pll1-clk"; | 82 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
| 66 | reg = <0x01c20000 0x4>; | 83 | reg = <0x01c20000 0x4>; |
| 67 | clocks = <&osc24M>; | 84 | clocks = <&osc24M>; |
| 85 | clock-output-names = "pll1"; | ||
| 68 | }; | 86 | }; |
| 69 | 87 | ||
| 70 | pll4: pll4@01c20018 { | 88 | pll4: clk@01c20018 { |
| 71 | #clock-cells = <0>; | 89 | #clock-cells = <0>; |
| 72 | compatible = "allwinner,sun4i-pll1-clk"; | 90 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
| 73 | reg = <0x01c20018 0x4>; | 91 | reg = <0x01c20018 0x4>; |
| 74 | clocks = <&osc24M>; | 92 | clocks = <&osc24M>; |
| 93 | clock-output-names = "pll4"; | ||
| 75 | }; | 94 | }; |
| 76 | 95 | ||
| 77 | pll5: pll5@01c20020 { | 96 | pll5: clk@01c20020 { |
| 78 | #clock-cells = <1>; | 97 | #clock-cells = <1>; |
| 79 | compatible = "allwinner,sun4i-pll5-clk"; | 98 | compatible = "allwinner,sun4i-a10-pll5-clk"; |
| 80 | reg = <0x01c20020 0x4>; | 99 | reg = <0x01c20020 0x4>; |
| 81 | clocks = <&osc24M>; | 100 | clocks = <&osc24M>; |
| 82 | clock-output-names = "pll5_ddr", "pll5_other"; | 101 | clock-output-names = "pll5_ddr", "pll5_other"; |
| 83 | }; | 102 | }; |
| 84 | 103 | ||
| 85 | pll6: pll6@01c20028 { | 104 | pll6: clk@01c20028 { |
| 86 | #clock-cells = <1>; | 105 | #clock-cells = <1>; |
| 87 | compatible = "allwinner,sun4i-pll6-clk"; | 106 | compatible = "allwinner,sun4i-a10-pll6-clk"; |
| 88 | reg = <0x01c20028 0x4>; | 107 | reg = <0x01c20028 0x4>; |
| 89 | clocks = <&osc24M>; | 108 | clocks = <&osc24M>; |
| 90 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; | 109 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; |
| @@ -92,26 +111,29 @@ | |||
| 92 | 111 | ||
| 93 | cpu: cpu@01c20054 { | 112 | cpu: cpu@01c20054 { |
| 94 | #clock-cells = <0>; | 113 | #clock-cells = <0>; |
| 95 | compatible = "allwinner,sun4i-cpu-clk"; | 114 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
| 96 | reg = <0x01c20054 0x4>; | 115 | reg = <0x01c20054 0x4>; |
| 97 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; | 116 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; |
| 117 | clock-output-names = "cpu"; | ||
| 98 | }; | 118 | }; |
| 99 | 119 | ||
| 100 | axi: axi@01c20054 { | 120 | axi: axi@01c20054 { |
| 101 | #clock-cells = <0>; | 121 | #clock-cells = <0>; |
| 102 | compatible = "allwinner,sun4i-axi-clk"; | 122 | compatible = "allwinner,sun4i-a10-axi-clk"; |
| 103 | reg = <0x01c20054 0x4>; | 123 | reg = <0x01c20054 0x4>; |
| 104 | clocks = <&cpu>; | 124 | clocks = <&cpu>; |
| 125 | clock-output-names = "axi"; | ||
| 105 | }; | 126 | }; |
| 106 | 127 | ||
| 107 | ahb: ahb@01c20054 { | 128 | ahb: ahb@01c20054 { |
| 108 | #clock-cells = <0>; | 129 | #clock-cells = <0>; |
| 109 | compatible = "allwinner,sun4i-ahb-clk"; | 130 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
| 110 | reg = <0x01c20054 0x4>; | 131 | reg = <0x01c20054 0x4>; |
| 111 | clocks = <&axi>; | 132 | clocks = <&axi>; |
| 133 | clock-output-names = "ahb"; | ||
| 112 | }; | 134 | }; |
| 113 | 135 | ||
| 114 | ahb_gates: ahb_gates@01c20060 { | 136 | ahb_gates: clk@01c20060 { |
| 115 | #clock-cells = <1>; | 137 | #clock-cells = <1>; |
| 116 | compatible = "allwinner,sun7i-a20-ahb-gates-clk"; | 138 | compatible = "allwinner,sun7i-a20-ahb-gates-clk"; |
| 117 | reg = <0x01c20060 0x8>; | 139 | reg = <0x01c20060 0x8>; |
| @@ -133,12 +155,13 @@ | |||
| 133 | 155 | ||
| 134 | apb0: apb0@01c20054 { | 156 | apb0: apb0@01c20054 { |
| 135 | #clock-cells = <0>; | 157 | #clock-cells = <0>; |
| 136 | compatible = "allwinner,sun4i-apb0-clk"; | 158 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
| 137 | reg = <0x01c20054 0x4>; | 159 | reg = <0x01c20054 0x4>; |
| 138 | clocks = <&ahb>; | 160 | clocks = <&ahb>; |
| 161 | clock-output-names = "apb0"; | ||
| 139 | }; | 162 | }; |
| 140 | 163 | ||
| 141 | apb0_gates: apb0_gates@01c20068 { | 164 | apb0_gates: clk@01c20068 { |
| 142 | #clock-cells = <1>; | 165 | #clock-cells = <1>; |
| 143 | compatible = "allwinner,sun7i-a20-apb0-gates-clk"; | 166 | compatible = "allwinner,sun7i-a20-apb0-gates-clk"; |
| 144 | reg = <0x01c20068 0x4>; | 167 | reg = <0x01c20068 0x4>; |
| @@ -151,19 +174,21 @@ | |||
| 151 | 174 | ||
| 152 | apb1_mux: apb1_mux@01c20058 { | 175 | apb1_mux: apb1_mux@01c20058 { |
| 153 | #clock-cells = <0>; | 176 | #clock-cells = <0>; |
| 154 | compatible = "allwinner,sun4i-apb1-mux-clk"; | 177 | compatible = "allwinner,sun4i-a10-apb1-mux-clk"; |
| 155 | reg = <0x01c20058 0x4>; | 178 | reg = <0x01c20058 0x4>; |
| 156 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; | 179 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; |
| 180 | clock-output-names = "apb1_mux"; | ||
| 157 | }; | 181 | }; |
| 158 | 182 | ||
| 159 | apb1: apb1@01c20058 { | 183 | apb1: apb1@01c20058 { |
| 160 | #clock-cells = <0>; | 184 | #clock-cells = <0>; |
| 161 | compatible = "allwinner,sun4i-apb1-clk"; | 185 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
| 162 | reg = <0x01c20058 0x4>; | 186 | reg = <0x01c20058 0x4>; |
| 163 | clocks = <&apb1_mux>; | 187 | clocks = <&apb1_mux>; |
| 188 | clock-output-names = "apb1"; | ||
| 164 | }; | 189 | }; |
| 165 | 190 | ||
| 166 | apb1_gates: apb1_gates@01c2006c { | 191 | apb1_gates: clk@01c2006c { |
| 167 | #clock-cells = <1>; | 192 | #clock-cells = <1>; |
| 168 | compatible = "allwinner,sun7i-a20-apb1-gates-clk"; | 193 | compatible = "allwinner,sun7i-a20-apb1-gates-clk"; |
| 169 | reg = <0x01c2006c 0x4>; | 194 | reg = <0x01c2006c 0x4>; |
| @@ -178,7 +203,7 @@ | |||
| 178 | 203 | ||
| 179 | nand_clk: clk@01c20080 { | 204 | nand_clk: clk@01c20080 { |
| 180 | #clock-cells = <0>; | 205 | #clock-cells = <0>; |
| 181 | compatible = "allwinner,sun4i-mod0-clk"; | 206 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 182 | reg = <0x01c20080 0x4>; | 207 | reg = <0x01c20080 0x4>; |
| 183 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 208 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 184 | clock-output-names = "nand"; | 209 | clock-output-names = "nand"; |
| @@ -186,7 +211,7 @@ | |||
| 186 | 211 | ||
| 187 | ms_clk: clk@01c20084 { | 212 | ms_clk: clk@01c20084 { |
| 188 | #clock-cells = <0>; | 213 | #clock-cells = <0>; |
| 189 | compatible = "allwinner,sun4i-mod0-clk"; | 214 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 190 | reg = <0x01c20084 0x4>; | 215 | reg = <0x01c20084 0x4>; |
| 191 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 216 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 192 | clock-output-names = "ms"; | 217 | clock-output-names = "ms"; |
| @@ -194,7 +219,7 @@ | |||
| 194 | 219 | ||
| 195 | mmc0_clk: clk@01c20088 { | 220 | mmc0_clk: clk@01c20088 { |
| 196 | #clock-cells = <0>; | 221 | #clock-cells = <0>; |
| 197 | compatible = "allwinner,sun4i-mod0-clk"; | 222 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 198 | reg = <0x01c20088 0x4>; | 223 | reg = <0x01c20088 0x4>; |
| 199 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 224 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 200 | clock-output-names = "mmc0"; | 225 | clock-output-names = "mmc0"; |
| @@ -202,7 +227,7 @@ | |||
| 202 | 227 | ||
| 203 | mmc1_clk: clk@01c2008c { | 228 | mmc1_clk: clk@01c2008c { |
| 204 | #clock-cells = <0>; | 229 | #clock-cells = <0>; |
| 205 | compatible = "allwinner,sun4i-mod0-clk"; | 230 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 206 | reg = <0x01c2008c 0x4>; | 231 | reg = <0x01c2008c 0x4>; |
| 207 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 232 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 208 | clock-output-names = "mmc1"; | 233 | clock-output-names = "mmc1"; |
| @@ -210,7 +235,7 @@ | |||
| 210 | 235 | ||
| 211 | mmc2_clk: clk@01c20090 { | 236 | mmc2_clk: clk@01c20090 { |
| 212 | #clock-cells = <0>; | 237 | #clock-cells = <0>; |
| 213 | compatible = "allwinner,sun4i-mod0-clk"; | 238 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 214 | reg = <0x01c20090 0x4>; | 239 | reg = <0x01c20090 0x4>; |
| 215 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 240 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 216 | clock-output-names = "mmc2"; | 241 | clock-output-names = "mmc2"; |
| @@ -218,7 +243,7 @@ | |||
| 218 | 243 | ||
| 219 | mmc3_clk: clk@01c20094 { | 244 | mmc3_clk: clk@01c20094 { |
| 220 | #clock-cells = <0>; | 245 | #clock-cells = <0>; |
| 221 | compatible = "allwinner,sun4i-mod0-clk"; | 246 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 222 | reg = <0x01c20094 0x4>; | 247 | reg = <0x01c20094 0x4>; |
| 223 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 248 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 224 | clock-output-names = "mmc3"; | 249 | clock-output-names = "mmc3"; |
| @@ -226,7 +251,7 @@ | |||
| 226 | 251 | ||
| 227 | ts_clk: clk@01c20098 { | 252 | ts_clk: clk@01c20098 { |
| 228 | #clock-cells = <0>; | 253 | #clock-cells = <0>; |
| 229 | compatible = "allwinner,sun4i-mod0-clk"; | 254 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 230 | reg = <0x01c20098 0x4>; | 255 | reg = <0x01c20098 0x4>; |
| 231 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 256 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 232 | clock-output-names = "ts"; | 257 | clock-output-names = "ts"; |
| @@ -234,7 +259,7 @@ | |||
| 234 | 259 | ||
| 235 | ss_clk: clk@01c2009c { | 260 | ss_clk: clk@01c2009c { |
| 236 | #clock-cells = <0>; | 261 | #clock-cells = <0>; |
| 237 | compatible = "allwinner,sun4i-mod0-clk"; | 262 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 238 | reg = <0x01c2009c 0x4>; | 263 | reg = <0x01c2009c 0x4>; |
| 239 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 264 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 240 | clock-output-names = "ss"; | 265 | clock-output-names = "ss"; |
| @@ -242,7 +267,7 @@ | |||
| 242 | 267 | ||
| 243 | spi0_clk: clk@01c200a0 { | 268 | spi0_clk: clk@01c200a0 { |
| 244 | #clock-cells = <0>; | 269 | #clock-cells = <0>; |
| 245 | compatible = "allwinner,sun4i-mod0-clk"; | 270 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 246 | reg = <0x01c200a0 0x4>; | 271 | reg = <0x01c200a0 0x4>; |
| 247 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 272 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 248 | clock-output-names = "spi0"; | 273 | clock-output-names = "spi0"; |
| @@ -250,7 +275,7 @@ | |||
| 250 | 275 | ||
| 251 | spi1_clk: clk@01c200a4 { | 276 | spi1_clk: clk@01c200a4 { |
| 252 | #clock-cells = <0>; | 277 | #clock-cells = <0>; |
| 253 | compatible = "allwinner,sun4i-mod0-clk"; | 278 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 254 | reg = <0x01c200a4 0x4>; | 279 | reg = <0x01c200a4 0x4>; |
| 255 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 280 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 256 | clock-output-names = "spi1"; | 281 | clock-output-names = "spi1"; |
| @@ -258,7 +283,7 @@ | |||
| 258 | 283 | ||
| 259 | spi2_clk: clk@01c200a8 { | 284 | spi2_clk: clk@01c200a8 { |
| 260 | #clock-cells = <0>; | 285 | #clock-cells = <0>; |
| 261 | compatible = "allwinner,sun4i-mod0-clk"; | 286 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 262 | reg = <0x01c200a8 0x4>; | 287 | reg = <0x01c200a8 0x4>; |
| 263 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 288 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 264 | clock-output-names = "spi2"; | 289 | clock-output-names = "spi2"; |
| @@ -266,7 +291,7 @@ | |||
| 266 | 291 | ||
| 267 | pata_clk: clk@01c200ac { | 292 | pata_clk: clk@01c200ac { |
| 268 | #clock-cells = <0>; | 293 | #clock-cells = <0>; |
| 269 | compatible = "allwinner,sun4i-mod0-clk"; | 294 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 270 | reg = <0x01c200ac 0x4>; | 295 | reg = <0x01c200ac 0x4>; |
| 271 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 296 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 272 | clock-output-names = "pata"; | 297 | clock-output-names = "pata"; |
| @@ -274,7 +299,7 @@ | |||
| 274 | 299 | ||
| 275 | ir0_clk: clk@01c200b0 { | 300 | ir0_clk: clk@01c200b0 { |
| 276 | #clock-cells = <0>; | 301 | #clock-cells = <0>; |
| 277 | compatible = "allwinner,sun4i-mod0-clk"; | 302 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 278 | reg = <0x01c200b0 0x4>; | 303 | reg = <0x01c200b0 0x4>; |
| 279 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 304 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 280 | clock-output-names = "ir0"; | 305 | clock-output-names = "ir0"; |
| @@ -282,15 +307,24 @@ | |||
| 282 | 307 | ||
| 283 | ir1_clk: clk@01c200b4 { | 308 | ir1_clk: clk@01c200b4 { |
| 284 | #clock-cells = <0>; | 309 | #clock-cells = <0>; |
| 285 | compatible = "allwinner,sun4i-mod0-clk"; | 310 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 286 | reg = <0x01c200b4 0x4>; | 311 | reg = <0x01c200b4 0x4>; |
| 287 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 312 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 288 | clock-output-names = "ir1"; | 313 | clock-output-names = "ir1"; |
| 289 | }; | 314 | }; |
| 290 | 315 | ||
| 316 | usb_clk: clk@01c200cc { | ||
| 317 | #clock-cells = <1>; | ||
| 318 | #reset-cells = <1>; | ||
| 319 | compatible = "allwinner,sun4i-a10-usb-clk"; | ||
| 320 | reg = <0x01c200cc 0x4>; | ||
| 321 | clocks = <&pll6 1>; | ||
| 322 | clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy"; | ||
| 323 | }; | ||
| 324 | |||
| 291 | spi3_clk: clk@01c200d4 { | 325 | spi3_clk: clk@01c200d4 { |
| 292 | #clock-cells = <0>; | 326 | #clock-cells = <0>; |
| 293 | compatible = "allwinner,sun4i-mod0-clk"; | 327 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 294 | reg = <0x01c200d4 0x4>; | 328 | reg = <0x01c200d4 0x4>; |
| 295 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 329 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 296 | clock-output-names = "spi3"; | 330 | clock-output-names = "spi3"; |
| @@ -298,13 +332,41 @@ | |||
| 298 | 332 | ||
| 299 | mbus_clk: clk@01c2015c { | 333 | mbus_clk: clk@01c2015c { |
| 300 | #clock-cells = <0>; | 334 | #clock-cells = <0>; |
| 301 | compatible = "allwinner,sun4i-mod0-clk"; | 335 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 302 | reg = <0x01c2015c 0x4>; | 336 | reg = <0x01c2015c 0x4>; |
| 303 | clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; | 337 | clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; |
| 304 | clock-output-names = "mbus"; | 338 | clock-output-names = "mbus"; |
| 305 | }; | 339 | }; |
| 306 | 340 | ||
| 307 | /* | 341 | /* |
| 342 | * The following two are dummy clocks, placeholders used in the gmac_tx | ||
| 343 | * clock. The gmac driver will choose one parent depending on the PHY | ||
| 344 | * interface mode, using clk_set_rate auto-reparenting. | ||
| 345 | * The actual TX clock rate is not controlled by the gmac_tx clock. | ||
| 346 | */ | ||
| 347 | mii_phy_tx_clk: clk@2 { | ||
| 348 | #clock-cells = <0>; | ||
| 349 | compatible = "fixed-clock"; | ||
| 350 | clock-frequency = <25000000>; | ||
| 351 | clock-output-names = "mii_phy_tx"; | ||
| 352 | }; | ||
| 353 | |||
| 354 | gmac_int_tx_clk: clk@3 { | ||
| 355 | #clock-cells = <0>; | ||
| 356 | compatible = "fixed-clock"; | ||
| 357 | clock-frequency = <125000000>; | ||
| 358 | clock-output-names = "gmac_int_tx"; | ||
| 359 | }; | ||
| 360 | |||
| 361 | gmac_tx_clk: clk@01c20164 { | ||
| 362 | #clock-cells = <0>; | ||
| 363 | compatible = "allwinner,sun7i-a20-gmac-clk"; | ||
| 364 | reg = <0x01c20164 0x4>; | ||
| 365 | clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; | ||
| 366 | clock-output-names = "gmac_tx"; | ||
| 367 | }; | ||
| 368 | |||
| 369 | /* | ||
| 308 | * Dummy clock used by output clocks | 370 | * Dummy clock used by output clocks |
| 309 | */ | 371 | */ |
| 310 | osc24M_32k: clk@1 { | 372 | osc24M_32k: clk@1 { |
| @@ -339,6 +401,28 @@ | |||
| 339 | #size-cells = <1>; | 401 | #size-cells = <1>; |
| 340 | ranges; | 402 | ranges; |
| 341 | 403 | ||
| 404 | spi0: spi@01c05000 { | ||
| 405 | compatible = "allwinner,sun4i-a10-spi"; | ||
| 406 | reg = <0x01c05000 0x1000>; | ||
| 407 | interrupts = <0 10 4>; | ||
| 408 | clocks = <&ahb_gates 20>, <&spi0_clk>; | ||
| 409 | clock-names = "ahb", "mod"; | ||
| 410 | status = "disabled"; | ||
| 411 | #address-cells = <1>; | ||
| 412 | #size-cells = <0>; | ||
| 413 | }; | ||
| 414 | |||
| 415 | spi1: spi@01c06000 { | ||
| 416 | compatible = "allwinner,sun4i-a10-spi"; | ||
| 417 | reg = <0x01c06000 0x1000>; | ||
| 418 | interrupts = <0 11 4>; | ||
| 419 | clocks = <&ahb_gates 21>, <&spi1_clk>; | ||
| 420 | clock-names = "ahb", "mod"; | ||
| 421 | status = "disabled"; | ||
| 422 | #address-cells = <1>; | ||
| 423 | #size-cells = <0>; | ||
| 424 | }; | ||
| 425 | |||
| 342 | emac: ethernet@01c0b000 { | 426 | emac: ethernet@01c0b000 { |
| 343 | compatible = "allwinner,sun4i-a10-emac"; | 427 | compatible = "allwinner,sun4i-a10-emac"; |
| 344 | reg = <0x01c0b000 0x1000>; | 428 | reg = <0x01c0b000 0x1000>; |
| @@ -355,6 +439,88 @@ | |||
| 355 | #size-cells = <0>; | 439 | #size-cells = <0>; |
| 356 | }; | 440 | }; |
| 357 | 441 | ||
| 442 | usbphy: phy@01c13400 { | ||
| 443 | #phy-cells = <1>; | ||
| 444 | compatible = "allwinner,sun7i-a20-usb-phy"; | ||
| 445 | reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; | ||
| 446 | reg-names = "phy_ctrl", "pmu1", "pmu2"; | ||
| 447 | clocks = <&usb_clk 8>; | ||
| 448 | clock-names = "usb_phy"; | ||
| 449 | resets = <&usb_clk 1>, <&usb_clk 2>; | ||
| 450 | reset-names = "usb1_reset", "usb2_reset"; | ||
| 451 | status = "disabled"; | ||
| 452 | }; | ||
| 453 | |||
| 454 | ehci0: usb@01c14000 { | ||
| 455 | compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; | ||
| 456 | reg = <0x01c14000 0x100>; | ||
| 457 | interrupts = <0 39 4>; | ||
| 458 | clocks = <&ahb_gates 1>; | ||
| 459 | phys = <&usbphy 1>; | ||
| 460 | phy-names = "usb"; | ||
| 461 | status = "disabled"; | ||
| 462 | }; | ||
| 463 | |||
| 464 | ohci0: usb@01c14400 { | ||
| 465 | compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; | ||
| 466 | reg = <0x01c14400 0x100>; | ||
| 467 | interrupts = <0 64 4>; | ||
| 468 | clocks = <&usb_clk 6>, <&ahb_gates 2>; | ||
| 469 | phys = <&usbphy 1>; | ||
| 470 | phy-names = "usb"; | ||
| 471 | status = "disabled"; | ||
| 472 | }; | ||
| 473 | |||
| 474 | spi2: spi@01c17000 { | ||
| 475 | compatible = "allwinner,sun4i-a10-spi"; | ||
| 476 | reg = <0x01c17000 0x1000>; | ||
| 477 | interrupts = <0 12 4>; | ||
| 478 | clocks = <&ahb_gates 22>, <&spi2_clk>; | ||
| 479 | clock-names = "ahb", "mod"; | ||
| 480 | status = "disabled"; | ||
| 481 | #address-cells = <1>; | ||
| 482 | #size-cells = <0>; | ||
| 483 | }; | ||
| 484 | |||
| 485 | ahci: sata@01c18000 { | ||
| 486 | compatible = "allwinner,sun4i-a10-ahci"; | ||
| 487 | reg = <0x01c18000 0x1000>; | ||
| 488 | interrupts = <0 56 4>; | ||
| 489 | clocks = <&pll6 0>, <&ahb_gates 25>; | ||
| 490 | status = "disabled"; | ||
| 491 | }; | ||
| 492 | |||
| 493 | ehci1: usb@01c1c000 { | ||
| 494 | compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; | ||
| 495 | reg = <0x01c1c000 0x100>; | ||
| 496 | interrupts = <0 40 4>; | ||
| 497 | clocks = <&ahb_gates 3>; | ||
| 498 | phys = <&usbphy 2>; | ||
| 499 | phy-names = "usb"; | ||
| 500 | status = "disabled"; | ||
| 501 | }; | ||
| 502 | |||
| 503 | ohci1: usb@01c1c400 { | ||
| 504 | compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; | ||
| 505 | reg = <0x01c1c400 0x100>; | ||
| 506 | interrupts = <0 65 4>; | ||
| 507 | clocks = <&usb_clk 7>, <&ahb_gates 4>; | ||
| 508 | phys = <&usbphy 2>; | ||
| 509 | phy-names = "usb"; | ||
| 510 | status = "disabled"; | ||
| 511 | }; | ||
| 512 | |||
| 513 | spi3: spi@01c1f000 { | ||
| 514 | compatible = "allwinner,sun4i-a10-spi"; | ||
| 515 | reg = <0x01c1f000 0x1000>; | ||
| 516 | interrupts = <0 50 4>; | ||
| 517 | clocks = <&ahb_gates 23>, <&spi3_clk>; | ||
| 518 | clock-names = "ahb", "mod"; | ||
| 519 | status = "disabled"; | ||
| 520 | #address-cells = <1>; | ||
| 521 | #size-cells = <0>; | ||
| 522 | }; | ||
| 523 | |||
| 358 | pio: pinctrl@01c20800 { | 524 | pio: pinctrl@01c20800 { |
| 359 | compatible = "allwinner,sun7i-a20-pinctrl"; | 525 | compatible = "allwinner,sun7i-a20-pinctrl"; |
| 360 | reg = <0x01c20800 0x400>; | 526 | reg = <0x01c20800 0x400>; |
| @@ -373,6 +539,13 @@ | |||
| 373 | allwinner,pull = <0>; | 539 | allwinner,pull = <0>; |
| 374 | }; | 540 | }; |
| 375 | 541 | ||
| 542 | uart2_pins_a: uart2@0 { | ||
| 543 | allwinner,pins = "PI16", "PI17", "PI18", "PI19"; | ||
| 544 | allwinner,function = "uart2"; | ||
| 545 | allwinner,drive = <0>; | ||
| 546 | allwinner,pull = <0>; | ||
| 547 | }; | ||
| 548 | |||
| 376 | uart6_pins_a: uart6@0 { | 549 | uart6_pins_a: uart6@0 { |
| 377 | allwinner,pins = "PI12", "PI13"; | 550 | allwinner,pins = "PI12", "PI13"; |
| 378 | allwinner,function = "uart6"; | 551 | allwinner,function = "uart6"; |
| @@ -432,6 +605,46 @@ | |||
| 432 | allwinner,drive = <0>; | 605 | allwinner,drive = <0>; |
| 433 | allwinner,pull = <0>; | 606 | allwinner,pull = <0>; |
| 434 | }; | 607 | }; |
| 608 | |||
| 609 | gmac_pins_mii_a: gmac_mii@0 { | ||
| 610 | allwinner,pins = "PA0", "PA1", "PA2", | ||
| 611 | "PA3", "PA4", "PA5", "PA6", | ||
| 612 | "PA7", "PA8", "PA9", "PA10", | ||
| 613 | "PA11", "PA12", "PA13", "PA14", | ||
| 614 | "PA15", "PA16"; | ||
| 615 | allwinner,function = "gmac"; | ||
| 616 | allwinner,drive = <0>; | ||
| 617 | allwinner,pull = <0>; | ||
| 618 | }; | ||
| 619 | |||
| 620 | gmac_pins_rgmii_a: gmac_rgmii@0 { | ||
| 621 | allwinner,pins = "PA0", "PA1", "PA2", | ||
| 622 | "PA3", "PA4", "PA5", "PA6", | ||
| 623 | "PA7", "PA8", "PA10", | ||
| 624 | "PA11", "PA12", "PA13", | ||
| 625 | "PA15", "PA16"; | ||
| 626 | allwinner,function = "gmac"; | ||
| 627 | /* | ||
| 628 | * data lines in RGMII mode use DDR mode | ||
| 629 | * and need a higher signal drive strength | ||
| 630 | */ | ||
| 631 | allwinner,drive = <3>; | ||
| 632 | allwinner,pull = <0>; | ||
| 633 | }; | ||
| 634 | |||
| 635 | spi1_pins_a: spi1@0 { | ||
| 636 | allwinner,pins = "PI16", "PI17", "PI18", "PI19"; | ||
| 637 | allwinner,function = "spi1"; | ||
| 638 | allwinner,drive = <0>; | ||
| 639 | allwinner,pull = <0>; | ||
| 640 | }; | ||
| 641 | |||
| 642 | spi2_pins_a: spi2@0 { | ||
| 643 | allwinner,pins = "PC19", "PC20", "PC21", "PC22"; | ||
| 644 | allwinner,function = "spi2"; | ||
| 645 | allwinner,drive = <0>; | ||
| 646 | allwinner,pull = <0>; | ||
| 647 | }; | ||
| 435 | }; | 648 | }; |
| 436 | 649 | ||
| 437 | timer@01c20c00 { | 650 | timer@01c20c00 { |
| @@ -447,7 +660,7 @@ | |||
| 447 | }; | 660 | }; |
| 448 | 661 | ||
| 449 | wdt: watchdog@01c20c90 { | 662 | wdt: watchdog@01c20c90 { |
| 450 | compatible = "allwinner,sun4i-wdt"; | 663 | compatible = "allwinner,sun4i-a10-wdt"; |
| 451 | reg = <0x01c20c90 0x10>; | 664 | reg = <0x01c20c90 0x10>; |
| 452 | }; | 665 | }; |
| 453 | 666 | ||
| @@ -593,6 +806,21 @@ | |||
| 593 | status = "disabled"; | 806 | status = "disabled"; |
| 594 | }; | 807 | }; |
| 595 | 808 | ||
| 809 | gmac: ethernet@01c50000 { | ||
| 810 | compatible = "allwinner,sun7i-a20-gmac"; | ||
| 811 | reg = <0x01c50000 0x10000>; | ||
| 812 | interrupts = <0 85 4>; | ||
| 813 | interrupt-names = "macirq"; | ||
| 814 | clocks = <&ahb_gates 49>, <&gmac_tx_clk>; | ||
| 815 | clock-names = "stmmaceth", "allwinner_gmac_tx"; | ||
| 816 | snps,pbl = <2>; | ||
| 817 | snps,fixed-burst; | ||
| 818 | snps,force_sf_dma_mode; | ||
| 819 | status = "disabled"; | ||
| 820 | #address-cells = <1>; | ||
| 821 | #size-cells = <0>; | ||
| 822 | }; | ||
| 823 | |||
| 596 | hstimer@01c60000 { | 824 | hstimer@01c60000 { |
| 597 | compatible = "allwinner,sun7i-a20-hstimer"; | 825 | compatible = "allwinner,sun7i-a20-hstimer"; |
| 598 | reg = <0x01c60000 0x1000>; | 826 | reg = <0x01c60000 0x1000>; |
diff --git a/arch/arm/boot/dts/sunxi-common-regulators.dtsi b/arch/arm/boot/dts/sunxi-common-regulators.dtsi new file mode 100644 index 000000000000..18eeac0670b9 --- /dev/null +++ b/arch/arm/boot/dts/sunxi-common-regulators.dtsi | |||
| @@ -0,0 +1,75 @@ | |||
| 1 | /* | ||
| 2 | * sunxi boards common regulator (ahci target power supply, usb-vbus) code | ||
| 3 | * | ||
| 4 | * Copyright 2014 - Hans de Goede <hdegoede@redhat.com> | ||
| 5 | * | ||
| 6 | * The code contained herein is licensed under the GNU General Public | ||
| 7 | * License. You may obtain a copy of the GNU General Public License | ||
| 8 | * Version 2 or later at the following locations: | ||
| 9 | * | ||
| 10 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 11 | * http://www.gnu.org/copyleft/gpl.html | ||
| 12 | */ | ||
| 13 | |||
| 14 | / { | ||
| 15 | soc@01c00000 { | ||
| 16 | pio: pinctrl@01c20800 { | ||
| 17 | ahci_pwr_pin_a: ahci_pwr_pin@0 { | ||
| 18 | allwinner,pins = "PB8"; | ||
| 19 | allwinner,function = "gpio_out"; | ||
| 20 | allwinner,drive = <0>; | ||
| 21 | allwinner,pull = <0>; | ||
| 22 | }; | ||
| 23 | |||
| 24 | usb1_vbus_pin_a: usb1_vbus_pin@0 { | ||
| 25 | allwinner,pins = "PH6"; | ||
| 26 | allwinner,function = "gpio_out"; | ||
| 27 | allwinner,drive = <0>; | ||
| 28 | allwinner,pull = <0>; | ||
| 29 | }; | ||
| 30 | |||
| 31 | usb2_vbus_pin_a: usb2_vbus_pin@0 { | ||
| 32 | allwinner,pins = "PH3"; | ||
| 33 | allwinner,function = "gpio_out"; | ||
| 34 | allwinner,drive = <0>; | ||
| 35 | allwinner,pull = <0>; | ||
| 36 | }; | ||
| 37 | }; | ||
| 38 | }; | ||
| 39 | |||
| 40 | reg_ahci_5v: ahci-5v { | ||
| 41 | compatible = "regulator-fixed"; | ||
| 42 | pinctrl-names = "default"; | ||
| 43 | pinctrl-0 = <&ahci_pwr_pin_a>; | ||
| 44 | regulator-name = "ahci-5v"; | ||
| 45 | regulator-min-microvolt = <5000000>; | ||
| 46 | regulator-max-microvolt = <5000000>; | ||
| 47 | enable-active-high; | ||
| 48 | gpio = <&pio 1 8 0>; | ||
| 49 | status = "disabled"; | ||
| 50 | }; | ||
| 51 | |||
| 52 | reg_usb1_vbus: usb1-vbus { | ||
| 53 | compatible = "regulator-fixed"; | ||
| 54 | pinctrl-names = "default"; | ||
| 55 | pinctrl-0 = <&usb1_vbus_pin_a>; | ||
| 56 | regulator-name = "usb1-vbus"; | ||
| 57 | regulator-min-microvolt = <5000000>; | ||
| 58 | regulator-max-microvolt = <5000000>; | ||
| 59 | enable-active-high; | ||
| 60 | gpio = <&pio 7 6 0>; | ||
| 61 | status = "disabled"; | ||
| 62 | }; | ||
| 63 | |||
| 64 | reg_usb2_vbus: usb2-vbus { | ||
| 65 | compatible = "regulator-fixed"; | ||
| 66 | pinctrl-names = "default"; | ||
| 67 | pinctrl-0 = <&usb2_vbus_pin_a>; | ||
| 68 | regulator-name = "usb2-vbus"; | ||
| 69 | regulator-min-microvolt = <5000000>; | ||
| 70 | regulator-max-microvolt = <5000000>; | ||
| 71 | enable-active-high; | ||
| 72 | gpio = <&pio 7 3 0>; | ||
| 73 | status = "disabled"; | ||
| 74 | }; | ||
| 75 | }; | ||
diff --git a/arch/arm/boot/dts/tps65910.dtsi b/arch/arm/boot/dts/tps65910.dtsi index 92693a89160e..b0ac6657a170 100644 --- a/arch/arm/boot/dts/tps65910.dtsi +++ b/arch/arm/boot/dts/tps65910.dtsi | |||
| @@ -82,5 +82,10 @@ | |||
| 82 | reg = <12>; | 82 | reg = <12>; |
| 83 | regulator-compatible = "vmmc"; | 83 | regulator-compatible = "vmmc"; |
| 84 | }; | 84 | }; |
| 85 | |||
| 86 | vbb_reg: regulator@13 { | ||
| 87 | reg = <13>; | ||
| 88 | regulator-compatible = "vbb"; | ||
| 89 | }; | ||
| 85 | }; | 90 | }; |
| 86 | }; | 91 | }; |
diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi index 4217096ee677..86cfc7d15ca7 100644 --- a/arch/arm/boot/dts/twl4030.dtsi +++ b/arch/arm/boot/dts/twl4030.dtsi | |||
| @@ -145,4 +145,11 @@ | |||
| 145 | compatible = "ti,twl4030-pwrbutton"; | 145 | compatible = "ti,twl4030-pwrbutton"; |
| 146 | interrupts = <8>; | 146 | interrupts = <8>; |
| 147 | }; | 147 | }; |
| 148 | |||
| 149 | twl_keypad: keypad { | ||
| 150 | compatible = "ti,twl4030-keypad"; | ||
| 151 | interrupts = <1>; | ||
| 152 | keypad,num-rows = <8>; | ||
| 153 | keypad,num-columns = <8>; | ||
| 154 | }; | ||
| 148 | }; | 155 | }; |
diff --git a/arch/arm/boot/dts/vf610-cosmic.dts b/arch/arm/boot/dts/vf610-cosmic.dts index c42e4f938dcd..3fd1b74e1216 100644 --- a/arch/arm/boot/dts/vf610-cosmic.dts +++ b/arch/arm/boot/dts/vf610-cosmic.dts | |||
| @@ -36,12 +36,37 @@ | |||
| 36 | &fec1 { | 36 | &fec1 { |
| 37 | phy-mode = "rmii"; | 37 | phy-mode = "rmii"; |
| 38 | pinctrl-names = "default"; | 38 | pinctrl-names = "default"; |
| 39 | pinctrl-0 = <&pinctrl_fec1_1>; | 39 | pinctrl-0 = <&pinctrl_fec1>; |
| 40 | status = "okay"; | 40 | status = "okay"; |
| 41 | }; | 41 | }; |
| 42 | 42 | ||
| 43 | &iomuxc { | ||
| 44 | vf610-cosmic { | ||
| 45 | pinctrl_fec1: fec1grp { | ||
| 46 | fsl,pins = < | ||
| 47 | VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 | ||
| 48 | VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 | ||
| 49 | VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 | ||
| 50 | VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1 | ||
| 51 | VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 | ||
| 52 | VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 | ||
| 53 | VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 | ||
| 54 | VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 | ||
| 55 | VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 | ||
| 56 | >; | ||
| 57 | }; | ||
| 58 | |||
| 59 | pinctrl_uart1: uart1grp { | ||
| 60 | fsl,pins = < | ||
| 61 | VF610_PAD_PTB4__UART1_TX 0x21a2 | ||
| 62 | VF610_PAD_PTB5__UART1_RX 0x21a1 | ||
| 63 | >; | ||
| 64 | }; | ||
| 65 | }; | ||
| 66 | }; | ||
| 67 | |||
| 43 | &uart1 { | 68 | &uart1 { |
| 44 | pinctrl-names = "default"; | 69 | pinctrl-names = "default"; |
| 45 | pinctrl-0 = <&pinctrl_uart1_1>; | 70 | pinctrl-0 = <&pinctrl_uart1>; |
| 46 | status = "okay"; | 71 | status = "okay"; |
| 47 | }; | 72 | }; |
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts index c8047ca16501..7dd1d6ede525 100644 --- a/arch/arm/boot/dts/vf610-twr.dts +++ b/arch/arm/boot/dts/vf610-twr.dts | |||
| @@ -34,12 +34,70 @@ | |||
| 34 | }; | 34 | }; |
| 35 | }; | 35 | }; |
| 36 | 36 | ||
| 37 | regulators { | ||
| 38 | compatible = "simple-bus"; | ||
| 39 | #address-cells = <1>; | ||
| 40 | #size-cells = <0>; | ||
| 41 | |||
| 42 | reg_3p3v: regulator@0 { | ||
| 43 | compatible = "regulator-fixed"; | ||
| 44 | reg = <0>; | ||
| 45 | regulator-name = "3P3V"; | ||
| 46 | regulator-min-microvolt = <3300000>; | ||
| 47 | regulator-max-microvolt = <3300000>; | ||
| 48 | regulator-always-on; | ||
| 49 | }; | ||
| 50 | |||
| 51 | reg_vcc_3v3_mcu: regulator@1 { | ||
| 52 | compatible = "regulator-fixed"; | ||
| 53 | reg = <1>; | ||
| 54 | regulator-name = "vcc_3v3_mcu"; | ||
| 55 | regulator-min-microvolt = <3300000>; | ||
| 56 | regulator-max-microvolt = <3300000>; | ||
| 57 | }; | ||
| 58 | }; | ||
| 59 | |||
| 60 | sound { | ||
| 61 | compatible = "simple-audio-card"; | ||
| 62 | simple-audio-card,format = "i2s"; | ||
| 63 | simple-audio-card,widgets = | ||
| 64 | "Microphone", "Microphone Jack", | ||
| 65 | "Headphone", "Headphone Jack", | ||
| 66 | "Speaker", "Speaker Ext", | ||
| 67 | "Line", "Line In Jack"; | ||
| 68 | simple-audio-card,routing = | ||
| 69 | "MIC_IN", "Microphone Jack", | ||
| 70 | "Microphone Jack", "Mic Bias", | ||
| 71 | "LINE_IN", "Line In Jack", | ||
| 72 | "Headphone Jack", "HP_OUT", | ||
| 73 | "Speaker Ext", "LINE_OUT"; | ||
| 74 | |||
| 75 | simple-audio-card,cpu { | ||
| 76 | sound-dai = <&sai2>; | ||
| 77 | master-clkdir-out; | ||
| 78 | frame-master; | ||
| 79 | bitclock-master; | ||
| 80 | }; | ||
| 81 | |||
| 82 | simple-audio-card,codec { | ||
| 83 | sound-dai = <&codec>; | ||
| 84 | frame-master; | ||
| 85 | bitclock-master; | ||
| 86 | }; | ||
| 87 | }; | ||
| 88 | }; | ||
| 89 | |||
| 90 | &adc0 { | ||
| 91 | pinctrl-names = "default"; | ||
| 92 | pinctrl-0 = <&pinctrl_adc0_ad5>; | ||
| 93 | vref-supply = <®_vcc_3v3_mcu>; | ||
| 94 | status = "okay"; | ||
| 37 | }; | 95 | }; |
| 38 | 96 | ||
| 39 | &dspi0 { | 97 | &dspi0 { |
| 40 | bus-num = <0>; | 98 | bus-num = <0>; |
| 41 | pinctrl-names = "default"; | 99 | pinctrl-names = "default"; |
| 42 | pinctrl-0 = <&pinctrl_dspi0_1>; | 100 | pinctrl-0 = <&pinctrl_dspi0>; |
| 43 | status = "okay"; | 101 | status = "okay"; |
| 44 | 102 | ||
| 45 | sflash: at26df081a@0 { | 103 | sflash: at26df081a@0 { |
| @@ -56,26 +114,116 @@ | |||
| 56 | &fec0 { | 114 | &fec0 { |
| 57 | phy-mode = "rmii"; | 115 | phy-mode = "rmii"; |
| 58 | pinctrl-names = "default"; | 116 | pinctrl-names = "default"; |
| 59 | pinctrl-0 = <&pinctrl_fec0_1>; | 117 | pinctrl-0 = <&pinctrl_fec0>; |
| 60 | status = "okay"; | 118 | status = "okay"; |
| 61 | }; | 119 | }; |
| 62 | 120 | ||
| 63 | &fec1 { | 121 | &fec1 { |
| 64 | phy-mode = "rmii"; | 122 | phy-mode = "rmii"; |
| 65 | pinctrl-names = "default"; | 123 | pinctrl-names = "default"; |
| 66 | pinctrl-0 = <&pinctrl_fec1_1>; | 124 | pinctrl-0 = <&pinctrl_fec1>; |
| 67 | status = "okay"; | 125 | status = "okay"; |
| 68 | }; | 126 | }; |
| 69 | 127 | ||
| 70 | &i2c0 { | 128 | &i2c0 { |
| 71 | clock-frequency = <100000>; | 129 | clock-frequency = <100000>; |
| 72 | pinctrl-names = "default"; | 130 | pinctrl-names = "default"; |
| 73 | pinctrl-0 = <&pinctrl_i2c0_1>; | 131 | pinctrl-0 = <&pinctrl_i2c0>; |
| 132 | status = "okay"; | ||
| 133 | |||
| 134 | codec: sgtl5000@0a { | ||
| 135 | #sound-dai-cells = <0>; | ||
| 136 | compatible = "fsl,sgtl5000"; | ||
| 137 | reg = <0x0a>; | ||
| 138 | VDDA-supply = <®_3p3v>; | ||
| 139 | VDDIO-supply = <®_3p3v>; | ||
| 140 | clocks = <&clks VF610_CLK_SAI2>; | ||
| 141 | }; | ||
| 142 | }; | ||
| 143 | |||
| 144 | &iomuxc { | ||
| 145 | vf610-twr { | ||
| 146 | pinctrl_adc0_ad5: adc0ad5grp { | ||
| 147 | fsl,pins = < | ||
| 148 | VF610_PAD_PTC30__ADC0_SE5 0xa1 | ||
| 149 | >; | ||
| 150 | }; | ||
| 151 | |||
| 152 | pinctrl_dspi0: dspi0grp { | ||
| 153 | fsl,pins = < | ||
| 154 | VF610_PAD_PTB19__DSPI0_CS0 0x1182 | ||
| 155 | VF610_PAD_PTB20__DSPI0_SIN 0x1181 | ||
| 156 | VF610_PAD_PTB21__DSPI0_SOUT 0x1182 | ||
| 157 | VF610_PAD_PTB22__DSPI0_SCK 0x1182 | ||
| 158 | >; | ||
| 159 | }; | ||
| 160 | |||
| 161 | pinctrl_fec0: fec0grp { | ||
| 162 | fsl,pins = < | ||
| 163 | VF610_PAD_PTA6__RMII_CLKIN 0x30d1 | ||
| 164 | VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3 | ||
| 165 | VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1 | ||
| 166 | VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1 | ||
| 167 | VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1 | ||
| 168 | VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1 | ||
| 169 | VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1 | ||
| 170 | VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2 | ||
| 171 | VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2 | ||
| 172 | VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2 | ||
| 173 | >; | ||
| 174 | }; | ||
| 175 | |||
| 176 | pinctrl_fec1: fec1grp { | ||
| 177 | fsl,pins = < | ||
| 178 | VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 | ||
| 179 | VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 | ||
| 180 | VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 | ||
| 181 | VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1 | ||
| 182 | VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 | ||
| 183 | VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 | ||
| 184 | VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 | ||
| 185 | VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 | ||
| 186 | VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 | ||
| 187 | >; | ||
| 188 | }; | ||
| 189 | |||
| 190 | pinctrl_i2c0: i2c0grp { | ||
| 191 | fsl,pins = < | ||
| 192 | VF610_PAD_PTB14__I2C0_SCL 0x30d3 | ||
| 193 | VF610_PAD_PTB15__I2C0_SDA 0x30d3 | ||
| 194 | >; | ||
| 195 | }; | ||
| 196 | |||
| 197 | pinctrl_sai2: sai2grp { | ||
| 198 | fsl,pins = < | ||
| 199 | VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed | ||
| 200 | VF610_PAD_PTA18__SAI2_TX_DATA 0x02ee | ||
| 201 | VF610_PAD_PTA19__SAI2_TX_SYNC 0x02ed | ||
| 202 | VF610_PAD_PTA21__SAI2_RX_BCLK 0x02ed | ||
| 203 | VF610_PAD_PTA22__SAI2_RX_DATA 0x02ed | ||
| 204 | VF610_PAD_PTA23__SAI2_RX_SYNC 0x02ed | ||
| 205 | VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed | ||
| 206 | >; | ||
| 207 | }; | ||
| 208 | |||
| 209 | pinctrl_uart1: uart1grp { | ||
| 210 | fsl,pins = < | ||
| 211 | VF610_PAD_PTB4__UART1_TX 0x21a2 | ||
| 212 | VF610_PAD_PTB5__UART1_RX 0x21a1 | ||
| 213 | >; | ||
| 214 | }; | ||
| 215 | }; | ||
| 216 | }; | ||
| 217 | |||
| 218 | &sai2 { | ||
| 219 | #sound-dai-cells = <0>; | ||
| 220 | pinctrl-names = "default"; | ||
| 221 | pinctrl-0 = <&pinctrl_sai2>; | ||
| 74 | status = "okay"; | 222 | status = "okay"; |
| 75 | }; | 223 | }; |
| 76 | 224 | ||
| 77 | &uart1 { | 225 | &uart1 { |
| 78 | pinctrl-names = "default"; | 226 | pinctrl-names = "default"; |
| 79 | pinctrl-0 = <&pinctrl_uart1_1>; | 227 | pinctrl-0 = <&pinctrl_uart1>; |
| 80 | status = "okay"; | 228 | status = "okay"; |
| 81 | }; | 229 | }; |
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi index d31ce1b4a7b0..804873367669 100644 --- a/arch/arm/boot/dts/vf610.dtsi +++ b/arch/arm/boot/dts/vf610.dtsi | |||
| @@ -10,6 +10,7 @@ | |||
| 10 | #include "skeleton.dtsi" | 10 | #include "skeleton.dtsi" |
| 11 | #include "vf610-pinfunc.h" | 11 | #include "vf610-pinfunc.h" |
| 12 | #include <dt-bindings/clock/vf610-clock.h> | 12 | #include <dt-bindings/clock/vf610-clock.h> |
| 13 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 13 | 14 | ||
| 14 | / { | 15 | / { |
| 15 | aliases { | 16 | aliases { |
| @@ -87,39 +88,66 @@ | |||
| 87 | arm,tag-latency = <2 2 2>; | 88 | arm,tag-latency = <2 2 2>; |
| 88 | }; | 89 | }; |
| 89 | 90 | ||
| 91 | edma0: dma-controller@40018000 { | ||
| 92 | #dma-cells = <2>; | ||
| 93 | compatible = "fsl,vf610-edma"; | ||
| 94 | reg = <0x40018000 0x2000>, | ||
| 95 | <0x40024000 0x1000>, | ||
| 96 | <0x40025000 0x1000>; | ||
| 97 | interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, | ||
| 98 | <0 9 IRQ_TYPE_LEVEL_HIGH>; | ||
| 99 | interrupt-names = "edma-tx", "edma-err"; | ||
| 100 | dma-channels = <32>; | ||
| 101 | clock-names = "dmamux0", "dmamux1"; | ||
| 102 | clocks = <&clks VF610_CLK_DMAMUX0>, | ||
| 103 | <&clks VF610_CLK_DMAMUX1>; | ||
| 104 | }; | ||
| 105 | |||
| 90 | uart0: serial@40027000 { | 106 | uart0: serial@40027000 { |
| 91 | compatible = "fsl,vf610-lpuart"; | 107 | compatible = "fsl,vf610-lpuart"; |
| 92 | reg = <0x40027000 0x1000>; | 108 | reg = <0x40027000 0x1000>; |
| 93 | interrupts = <0 61 0x00>; | 109 | interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>; |
| 94 | clocks = <&clks VF610_CLK_UART0>; | 110 | clocks = <&clks VF610_CLK_UART0>; |
| 95 | clock-names = "ipg"; | 111 | clock-names = "ipg"; |
| 112 | dmas = <&edma0 0 2>, | ||
| 113 | <&edma0 0 3>; | ||
| 114 | dma-names = "rx","tx"; | ||
| 96 | status = "disabled"; | 115 | status = "disabled"; |
| 97 | }; | 116 | }; |
| 98 | 117 | ||
| 99 | uart1: serial@40028000 { | 118 | uart1: serial@40028000 { |
| 100 | compatible = "fsl,vf610-lpuart"; | 119 | compatible = "fsl,vf610-lpuart"; |
| 101 | reg = <0x40028000 0x1000>; | 120 | reg = <0x40028000 0x1000>; |
| 102 | interrupts = <0 62 0x04>; | 121 | interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>; |
| 103 | clocks = <&clks VF610_CLK_UART1>; | 122 | clocks = <&clks VF610_CLK_UART1>; |
| 104 | clock-names = "ipg"; | 123 | clock-names = "ipg"; |
| 124 | dmas = <&edma0 0 4>, | ||
| 125 | <&edma0 0 5>; | ||
| 126 | dma-names = "rx","tx"; | ||
| 105 | status = "disabled"; | 127 | status = "disabled"; |
| 106 | }; | 128 | }; |
| 107 | 129 | ||
| 108 | uart2: serial@40029000 { | 130 | uart2: serial@40029000 { |
| 109 | compatible = "fsl,vf610-lpuart"; | 131 | compatible = "fsl,vf610-lpuart"; |
| 110 | reg = <0x40029000 0x1000>; | 132 | reg = <0x40029000 0x1000>; |
| 111 | interrupts = <0 63 0x04>; | 133 | interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>; |
| 112 | clocks = <&clks VF610_CLK_UART2>; | 134 | clocks = <&clks VF610_CLK_UART2>; |
| 113 | clock-names = "ipg"; | 135 | clock-names = "ipg"; |
| 136 | dmas = <&edma0 0 6>, | ||
| 137 | <&edma0 0 7>; | ||
| 138 | dma-names = "rx","tx"; | ||
| 114 | status = "disabled"; | 139 | status = "disabled"; |
| 115 | }; | 140 | }; |
| 116 | 141 | ||
| 117 | uart3: serial@4002a000 { | 142 | uart3: serial@4002a000 { |
| 118 | compatible = "fsl,vf610-lpuart"; | 143 | compatible = "fsl,vf610-lpuart"; |
| 119 | reg = <0x4002a000 0x1000>; | 144 | reg = <0x4002a000 0x1000>; |
| 120 | interrupts = <0 64 0x04>; | 145 | interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>; |
| 121 | clocks = <&clks VF610_CLK_UART3>; | 146 | clocks = <&clks VF610_CLK_UART3>; |
| 122 | clock-names = "ipg"; | 147 | clock-names = "ipg"; |
| 148 | dmas = <&edma0 0 8>, | ||
| 149 | <&edma0 0 9>; | ||
| 150 | dma-names = "rx","tx"; | ||
| 123 | status = "disabled"; | 151 | status = "disabled"; |
| 124 | }; | 152 | }; |
| 125 | 153 | ||
| @@ -128,7 +156,7 @@ | |||
| 128 | #size-cells = <0>; | 156 | #size-cells = <0>; |
| 129 | compatible = "fsl,vf610-dspi"; | 157 | compatible = "fsl,vf610-dspi"; |
| 130 | reg = <0x4002c000 0x1000>; | 158 | reg = <0x4002c000 0x1000>; |
| 131 | interrupts = <0 67 0x04>; | 159 | interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; |
| 132 | clocks = <&clks VF610_CLK_DSPI0>; | 160 | clocks = <&clks VF610_CLK_DSPI0>; |
| 133 | clock-names = "dspi"; | 161 | clock-names = "dspi"; |
| 134 | spi-num-chipselects = <5>; | 162 | spi-num-chipselects = <5>; |
| @@ -138,20 +166,32 @@ | |||
| 138 | sai2: sai@40031000 { | 166 | sai2: sai@40031000 { |
| 139 | compatible = "fsl,vf610-sai"; | 167 | compatible = "fsl,vf610-sai"; |
| 140 | reg = <0x40031000 0x1000>; | 168 | reg = <0x40031000 0x1000>; |
| 141 | interrupts = <0 86 0x04>; | 169 | interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; |
| 142 | clocks = <&clks VF610_CLK_SAI2>; | 170 | clocks = <&clks VF610_CLK_SAI2>; |
| 143 | clock-names = "sai"; | 171 | clock-names = "sai"; |
| 172 | dma-names = "tx", "rx"; | ||
| 173 | dmas = <&edma0 0 21>, | ||
| 174 | <&edma0 0 20>; | ||
| 144 | status = "disabled"; | 175 | status = "disabled"; |
| 145 | }; | 176 | }; |
| 146 | 177 | ||
| 147 | pit: pit@40037000 { | 178 | pit: pit@40037000 { |
| 148 | compatible = "fsl,vf610-pit"; | 179 | compatible = "fsl,vf610-pit"; |
| 149 | reg = <0x40037000 0x1000>; | 180 | reg = <0x40037000 0x1000>; |
| 150 | interrupts = <0 39 0x04>; | 181 | interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; |
| 151 | clocks = <&clks VF610_CLK_PIT>; | 182 | clocks = <&clks VF610_CLK_PIT>; |
| 152 | clock-names = "pit"; | 183 | clock-names = "pit"; |
| 153 | }; | 184 | }; |
| 154 | 185 | ||
| 186 | adc0: adc@4003b000 { | ||
| 187 | compatible = "fsl,vf610-adc"; | ||
| 188 | reg = <0x4003b000 0x1000>; | ||
| 189 | interrupts = <0 53 0x04>; | ||
| 190 | clocks = <&clks VF610_CLK_ADC0>; | ||
| 191 | clock-names = "adc"; | ||
| 192 | status = "disabled"; | ||
| 193 | }; | ||
| 194 | |||
| 155 | wdog@4003e000 { | 195 | wdog@4003e000 { |
| 156 | compatible = "fsl,vf610-wdt", "fsl,imx21-wdt"; | 196 | compatible = "fsl,vf610-wdt", "fsl,imx21-wdt"; |
| 157 | reg = <0x4003e000 0x1000>; | 197 | reg = <0x4003e000 0x1000>; |
| @@ -164,7 +204,7 @@ | |||
| 164 | #size-cells = <0>; | 204 | #size-cells = <0>; |
| 165 | compatible = "fsl,vf610-qspi"; | 205 | compatible = "fsl,vf610-qspi"; |
| 166 | reg = <0x40044000 0x1000>; | 206 | reg = <0x40044000 0x1000>; |
| 167 | interrupts = <0 24 0x04>; | 207 | interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; |
| 168 | clocks = <&clks VF610_CLK_QSPI0_EN>, | 208 | clocks = <&clks VF610_CLK_QSPI0_EN>, |
| 169 | <&clks VF610_CLK_QSPI0>; | 209 | <&clks VF610_CLK_QSPI0>; |
| 170 | clock-names = "qspi_en", "qspi"; | 210 | clock-names = "qspi_en", "qspi"; |
| @@ -175,182 +215,12 @@ | |||
| 175 | compatible = "fsl,vf610-iomuxc"; | 215 | compatible = "fsl,vf610-iomuxc"; |
| 176 | reg = <0x40048000 0x1000>; | 216 | reg = <0x40048000 0x1000>; |
| 177 | #gpio-range-cells = <3>; | 217 | #gpio-range-cells = <3>; |
| 178 | |||
| 179 | /* functions and groups pins */ | ||
| 180 | |||
| 181 | dcu0 { | ||
| 182 | pinctrl_dcu0_1: dcu0grp_1 { | ||
| 183 | fsl,pins = < | ||
| 184 | VF610_PAD_PTB8__GPIO_30 0x42 | ||
| 185 | VF610_PAD_PTE0__DCU0_HSYNC 0x42 | ||
| 186 | VF610_PAD_PTE1__DCU0_VSYNC 0x42 | ||
| 187 | VF610_PAD_PTE2__DCU0_PCLK 0x42 | ||
| 188 | VF610_PAD_PTE4__DCU0_DE 0x42 | ||
| 189 | VF610_PAD_PTE5__DCU0_R0 0x42 | ||
| 190 | VF610_PAD_PTE6__DCU0_R1 0x42 | ||
| 191 | VF610_PAD_PTE7__DCU0_R2 0x42 | ||
| 192 | VF610_PAD_PTE8__DCU0_R3 0x42 | ||
| 193 | VF610_PAD_PTE9__DCU0_R4 0x42 | ||
| 194 | VF610_PAD_PTE10__DCU0_R5 0x42 | ||
| 195 | VF610_PAD_PTE11__DCU0_R6 0x42 | ||
| 196 | VF610_PAD_PTE12__DCU0_R7 0x42 | ||
| 197 | VF610_PAD_PTE13__DCU0_G0 0x42 | ||
| 198 | VF610_PAD_PTE14__DCU0_G1 0x42 | ||
| 199 | VF610_PAD_PTE15__DCU0_G2 0x42 | ||
| 200 | VF610_PAD_PTE16__DCU0_G3 0x42 | ||
| 201 | VF610_PAD_PTE17__DCU0_G4 0x42 | ||
| 202 | VF610_PAD_PTE18__DCU0_G5 0x42 | ||
| 203 | VF610_PAD_PTE19__DCU0_G6 0x42 | ||
| 204 | VF610_PAD_PTE20__DCU0_G7 0x42 | ||
| 205 | VF610_PAD_PTE21__DCU0_B0 0x42 | ||
| 206 | VF610_PAD_PTE22__DCU0_B1 0x42 | ||
| 207 | VF610_PAD_PTE23__DCU0_B2 0x42 | ||
| 208 | VF610_PAD_PTE24__DCU0_B3 0x42 | ||
| 209 | VF610_PAD_PTE25__DCU0_B4 0x42 | ||
| 210 | VF610_PAD_PTE26__DCU0_B5 0x42 | ||
| 211 | VF610_PAD_PTE27__DCU0_B6 0x42 | ||
| 212 | VF610_PAD_PTE28__DCU0_B7 0x42 | ||
| 213 | >; | ||
| 214 | }; | ||
| 215 | }; | ||
| 216 | |||
| 217 | dspi0 { | ||
| 218 | pinctrl_dspi0_1: dspi0grp_1 { | ||
| 219 | fsl,pins = < | ||
| 220 | VF610_PAD_PTB19__DSPI0_CS0 0x1182 | ||
| 221 | VF610_PAD_PTB20__DSPI0_SIN 0x1181 | ||
| 222 | VF610_PAD_PTB21__DSPI0_SOUT 0x1182 | ||
| 223 | VF610_PAD_PTB22__DSPI0_SCK 0x1182 | ||
| 224 | >; | ||
| 225 | }; | ||
| 226 | }; | ||
| 227 | |||
| 228 | esdhc1 { | ||
| 229 | pinctrl_esdhc1_1: esdhc1grp_1 { | ||
| 230 | fsl,pins = < | ||
| 231 | VF610_PAD_PTA24__ESDHC1_CLK 0x31ef | ||
| 232 | VF610_PAD_PTA25__ESDHC1_CMD 0x31ef | ||
| 233 | VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef | ||
| 234 | VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef | ||
| 235 | VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef | ||
| 236 | VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef | ||
| 237 | VF610_PAD_PTA7__GPIO_134 0x219d | ||
| 238 | >; | ||
| 239 | }; | ||
| 240 | }; | ||
| 241 | |||
| 242 | fec0 { | ||
| 243 | pinctrl_fec0_1: fec0grp_1 { | ||
| 244 | fsl,pins = < | ||
| 245 | VF610_PAD_PTA6__RMII_CLKIN 0x30d1 | ||
| 246 | VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3 | ||
| 247 | VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1 | ||
| 248 | VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1 | ||
| 249 | VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1 | ||
| 250 | VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1 | ||
| 251 | VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1 | ||
| 252 | VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2 | ||
| 253 | VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2 | ||
| 254 | VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2 | ||
| 255 | >; | ||
| 256 | }; | ||
| 257 | }; | ||
| 258 | |||
| 259 | fec1 { | ||
| 260 | pinctrl_fec1_1: fec1grp_1 { | ||
| 261 | fsl,pins = < | ||
| 262 | VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 | ||
| 263 | VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 | ||
| 264 | VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 | ||
| 265 | VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1 | ||
| 266 | VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 | ||
| 267 | VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 | ||
| 268 | VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 | ||
| 269 | VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 | ||
| 270 | VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 | ||
| 271 | >; | ||
| 272 | }; | ||
| 273 | }; | ||
| 274 | |||
| 275 | i2c0 { | ||
| 276 | pinctrl_i2c0_1: i2c0grp_1 { | ||
| 277 | fsl,pins = < | ||
| 278 | VF610_PAD_PTB14__I2C0_SCL 0x30d3 | ||
| 279 | VF610_PAD_PTB15__I2C0_SDA 0x30d3 | ||
| 280 | >; | ||
| 281 | }; | ||
| 282 | }; | ||
| 283 | |||
| 284 | pwm0 { | ||
| 285 | pinctrl_pwm0_1: pwm0grp_1 { | ||
| 286 | fsl,pins = < | ||
| 287 | VF610_PAD_PTB0__FTM0_CH0 0x1582 | ||
| 288 | VF610_PAD_PTB1__FTM0_CH1 0x1582 | ||
| 289 | VF610_PAD_PTB2__FTM0_CH2 0x1582 | ||
| 290 | VF610_PAD_PTB3__FTM0_CH3 0x1582 | ||
| 291 | VF610_PAD_PTB6__FTM0_CH6 0x1582 | ||
| 292 | VF610_PAD_PTB7__FTM0_CH7 0x1582 | ||
| 293 | >; | ||
| 294 | }; | ||
| 295 | }; | ||
| 296 | |||
| 297 | qspi0 { | ||
| 298 | pinctrl_qspi0_1: qspi0grp_1 { | ||
| 299 | fsl,pins = < | ||
| 300 | VF610_PAD_PTD0__QSPI0_A_QSCK 0x307b | ||
| 301 | VF610_PAD_PTD1__QSPI0_A_CS0 0x307f | ||
| 302 | VF610_PAD_PTD2__QSPI0_A_DATA3 0x3073 | ||
| 303 | VF610_PAD_PTD3__QSPI0_A_DATA2 0x3073 | ||
| 304 | VF610_PAD_PTD4__QSPI0_A_DATA1 0x3073 | ||
| 305 | VF610_PAD_PTD5__QSPI0_A_DATA0 0x307b | ||
| 306 | VF610_PAD_PTD7__QSPI0_B_QSCK 0x307b | ||
| 307 | VF610_PAD_PTD8__QSPI0_B_CS0 0x307f | ||
| 308 | VF610_PAD_PTD9__QSPI0_B_DATA3 0x3073 | ||
| 309 | VF610_PAD_PTD10__QSPI0_B_DATA2 0x3073 | ||
| 310 | VF610_PAD_PTD11__QSPI0_B_DATA1 0x3073 | ||
| 311 | VF610_PAD_PTD12__QSPI0_B_DATA0 0x307b | ||
| 312 | >; | ||
| 313 | }; | ||
| 314 | }; | ||
| 315 | |||
| 316 | sai2 { | ||
| 317 | pinctrl_sai2_1: sai2grp_1 { | ||
| 318 | fsl,pins = < | ||
| 319 | VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed | ||
| 320 | VF610_PAD_PTA18__SAI2_TX_DATA 0x02ee | ||
| 321 | VF610_PAD_PTA19__SAI2_TX_SYNC 0x02ed | ||
| 322 | VF610_PAD_PTA21__SAI2_RX_BCLK 0x02ed | ||
| 323 | VF610_PAD_PTA22__SAI2_RX_DATA 0x02ed | ||
| 324 | VF610_PAD_PTA23__SAI2_RX_SYNC 0x02ed | ||
| 325 | VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed | ||
| 326 | >; | ||
| 327 | }; | ||
| 328 | }; | ||
| 329 | |||
| 330 | uart1 { | ||
| 331 | pinctrl_uart1_1: uart1grp_1 { | ||
| 332 | fsl,pins = < | ||
| 333 | VF610_PAD_PTB4__UART1_TX 0x21a2 | ||
| 334 | VF610_PAD_PTB5__UART1_RX 0x21a1 | ||
| 335 | >; | ||
| 336 | }; | ||
| 337 | }; | ||
| 338 | |||
| 339 | usbvbus { | ||
| 340 | pinctrl_usbvbus_1: usbvbusgrp_1 { | ||
| 341 | fsl,pins = < | ||
| 342 | VF610_PAD_PTA24__USB1_VBUS_EN 0x219c | ||
| 343 | VF610_PAD_PTA16__USB0_VBUS_EN 0x219c | ||
| 344 | >; | ||
| 345 | }; | ||
| 346 | }; | ||
| 347 | |||
| 348 | }; | 218 | }; |
| 349 | 219 | ||
| 350 | gpio1: gpio@40049000 { | 220 | gpio1: gpio@40049000 { |
| 351 | compatible = "fsl,vf610-gpio"; | 221 | compatible = "fsl,vf610-gpio"; |
| 352 | reg = <0x40049000 0x1000 0x400ff000 0x40>; | 222 | reg = <0x40049000 0x1000 0x400ff000 0x40>; |
| 353 | interrupts = <0 107 0x04>; | 223 | interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; |
| 354 | gpio-controller; | 224 | gpio-controller; |
| 355 | #gpio-cells = <2>; | 225 | #gpio-cells = <2>; |
| 356 | interrupt-controller; | 226 | interrupt-controller; |
| @@ -361,7 +231,7 @@ | |||
| 361 | gpio2: gpio@4004a000 { | 231 | gpio2: gpio@4004a000 { |
| 362 | compatible = "fsl,vf610-gpio"; | 232 | compatible = "fsl,vf610-gpio"; |
| 363 | reg = <0x4004a000 0x1000 0x400ff040 0x40>; | 233 | reg = <0x4004a000 0x1000 0x400ff040 0x40>; |
| 364 | interrupts = <0 108 0x04>; | 234 | interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; |
| 365 | gpio-controller; | 235 | gpio-controller; |
| 366 | #gpio-cells = <2>; | 236 | #gpio-cells = <2>; |
| 367 | interrupt-controller; | 237 | interrupt-controller; |
| @@ -372,7 +242,7 @@ | |||
| 372 | gpio3: gpio@4004b000 { | 242 | gpio3: gpio@4004b000 { |
| 373 | compatible = "fsl,vf610-gpio"; | 243 | compatible = "fsl,vf610-gpio"; |
| 374 | reg = <0x4004b000 0x1000 0x400ff080 0x40>; | 244 | reg = <0x4004b000 0x1000 0x400ff080 0x40>; |
| 375 | interrupts = <0 109 0x04>; | 245 | interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; |
| 376 | gpio-controller; | 246 | gpio-controller; |
| 377 | #gpio-cells = <2>; | 247 | #gpio-cells = <2>; |
| 378 | interrupt-controller; | 248 | interrupt-controller; |
| @@ -383,7 +253,7 @@ | |||
| 383 | gpio4: gpio@4004c000 { | 253 | gpio4: gpio@4004c000 { |
| 384 | compatible = "fsl,vf610-gpio"; | 254 | compatible = "fsl,vf610-gpio"; |
| 385 | reg = <0x4004c000 0x1000 0x400ff0c0 0x40>; | 255 | reg = <0x4004c000 0x1000 0x400ff0c0 0x40>; |
| 386 | interrupts = <0 110 0x04>; | 256 | interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; |
| 387 | gpio-controller; | 257 | gpio-controller; |
| 388 | #gpio-cells = <2>; | 258 | #gpio-cells = <2>; |
| 389 | interrupt-controller; | 259 | interrupt-controller; |
| @@ -394,7 +264,7 @@ | |||
| 394 | gpio5: gpio@4004d000 { | 264 | gpio5: gpio@4004d000 { |
| 395 | compatible = "fsl,vf610-gpio"; | 265 | compatible = "fsl,vf610-gpio"; |
| 396 | reg = <0x4004d000 0x1000 0x400ff100 0x40>; | 266 | reg = <0x4004d000 0x1000 0x400ff100 0x40>; |
| 397 | interrupts = <0 111 0x04>; | 267 | interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; |
| 398 | gpio-controller; | 268 | gpio-controller; |
| 399 | #gpio-cells = <2>; | 269 | #gpio-cells = <2>; |
| 400 | interrupt-controller; | 270 | interrupt-controller; |
| @@ -412,9 +282,12 @@ | |||
| 412 | #size-cells = <0>; | 282 | #size-cells = <0>; |
| 413 | compatible = "fsl,vf610-i2c"; | 283 | compatible = "fsl,vf610-i2c"; |
| 414 | reg = <0x40066000 0x1000>; | 284 | reg = <0x40066000 0x1000>; |
| 415 | interrupts =<0 71 0x04>; | 285 | interrupts =<0 71 IRQ_TYPE_LEVEL_HIGH>; |
| 416 | clocks = <&clks VF610_CLK_I2C0>; | 286 | clocks = <&clks VF610_CLK_I2C0>; |
| 417 | clock-names = "ipg"; | 287 | clock-names = "ipg"; |
| 288 | dmas = <&edma0 0 50>, | ||
| 289 | <&edma0 0 51>; | ||
| 290 | dma-names = "rx","tx"; | ||
| 418 | status = "disabled"; | 291 | status = "disabled"; |
| 419 | }; | 292 | }; |
| 420 | 293 | ||
| @@ -432,10 +305,25 @@ | |||
| 432 | reg = <0x40080000 0x80000>; | 305 | reg = <0x40080000 0x80000>; |
| 433 | ranges; | 306 | ranges; |
| 434 | 307 | ||
| 308 | edma1: dma-controller@40098000 { | ||
| 309 | #dma-cells = <2>; | ||
| 310 | compatible = "fsl,vf610-edma"; | ||
| 311 | reg = <0x40098000 0x2000>, | ||
| 312 | <0x400a1000 0x1000>, | ||
| 313 | <0x400a2000 0x1000>; | ||
| 314 | interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>, | ||
| 315 | <0 11 IRQ_TYPE_LEVEL_HIGH>; | ||
| 316 | interrupt-names = "edma-tx", "edma-err"; | ||
| 317 | dma-channels = <32>; | ||
| 318 | clock-names = "dmamux0", "dmamux1"; | ||
| 319 | clocks = <&clks VF610_CLK_DMAMUX2>, | ||
| 320 | <&clks VF610_CLK_DMAMUX3>; | ||
| 321 | }; | ||
| 322 | |||
| 435 | uart4: serial@400a9000 { | 323 | uart4: serial@400a9000 { |
| 436 | compatible = "fsl,vf610-lpuart"; | 324 | compatible = "fsl,vf610-lpuart"; |
| 437 | reg = <0x400a9000 0x1000>; | 325 | reg = <0x400a9000 0x1000>; |
| 438 | interrupts = <0 65 0x04>; | 326 | interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>; |
| 439 | clocks = <&clks VF610_CLK_UART4>; | 327 | clocks = <&clks VF610_CLK_UART4>; |
| 440 | clock-names = "ipg"; | 328 | clock-names = "ipg"; |
| 441 | status = "disabled"; | 329 | status = "disabled"; |
| @@ -444,16 +332,25 @@ | |||
| 444 | uart5: serial@400aa000 { | 332 | uart5: serial@400aa000 { |
| 445 | compatible = "fsl,vf610-lpuart"; | 333 | compatible = "fsl,vf610-lpuart"; |
| 446 | reg = <0x400aa000 0x1000>; | 334 | reg = <0x400aa000 0x1000>; |
| 447 | interrupts = <0 66 0x04>; | 335 | interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>; |
| 448 | clocks = <&clks VF610_CLK_UART5>; | 336 | clocks = <&clks VF610_CLK_UART5>; |
| 449 | clock-names = "ipg"; | 337 | clock-names = "ipg"; |
| 450 | status = "disabled"; | 338 | status = "disabled"; |
| 451 | }; | 339 | }; |
| 452 | 340 | ||
| 341 | adc1: adc@400bb000 { | ||
| 342 | compatible = "fsl,vf610-adc"; | ||
| 343 | reg = <0x400bb000 0x1000>; | ||
| 344 | interrupts = <0 54 0x04>; | ||
| 345 | clocks = <&clks VF610_CLK_ADC1>; | ||
| 346 | clock-names = "adc"; | ||
| 347 | status = "disabled"; | ||
| 348 | }; | ||
| 349 | |||
| 453 | fec0: ethernet@400d0000 { | 350 | fec0: ethernet@400d0000 { |
| 454 | compatible = "fsl,mvf600-fec"; | 351 | compatible = "fsl,mvf600-fec"; |
| 455 | reg = <0x400d0000 0x1000>; | 352 | reg = <0x400d0000 0x1000>; |
| 456 | interrupts = <0 78 0x04>; | 353 | interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; |
| 457 | clocks = <&clks VF610_CLK_ENET0>, | 354 | clocks = <&clks VF610_CLK_ENET0>, |
| 458 | <&clks VF610_CLK_ENET0>, | 355 | <&clks VF610_CLK_ENET0>, |
| 459 | <&clks VF610_CLK_ENET>; | 356 | <&clks VF610_CLK_ENET>; |
| @@ -464,7 +361,7 @@ | |||
| 464 | fec1: ethernet@400d1000 { | 361 | fec1: ethernet@400d1000 { |
| 465 | compatible = "fsl,mvf600-fec"; | 362 | compatible = "fsl,mvf600-fec"; |
| 466 | reg = <0x400d1000 0x1000>; | 363 | reg = <0x400d1000 0x1000>; |
| 467 | interrupts = <0 79 0x04>; | 364 | interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; |
| 468 | clocks = <&clks VF610_CLK_ENET1>, | 365 | clocks = <&clks VF610_CLK_ENET1>, |
| 469 | <&clks VF610_CLK_ENET1>, | 366 | <&clks VF610_CLK_ENET1>, |
| 470 | <&clks VF610_CLK_ENET>; | 367 | <&clks VF610_CLK_ENET>; |
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 8b67b19392ec..93d1980a755d 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi | |||
| @@ -134,6 +134,7 @@ | |||
| 134 | #clock-cells = <1>; | 134 | #clock-cells = <1>; |
| 135 | compatible = "xlnx,ps7-clkc"; | 135 | compatible = "xlnx,ps7-clkc"; |
| 136 | ps-clk-frequency = <33333333>; | 136 | ps-clk-frequency = <33333333>; |
| 137 | fclk-enable = <0>; | ||
| 137 | clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", | 138 | clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", |
| 138 | "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", | 139 | "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", |
| 139 | "dci", "lqspi", "smc", "pcap", "gem0", "gem1", | 140 | "dci", "lqspi", "smc", "pcap", "gem0", "gem1", |
diff --git a/arch/arm/plat-orion/include/plat/cache-feroceon-l2.h b/arch/arm/include/asm/hardware/cache-feroceon-l2.h index 06f982d55697..12e1588dc4f1 100644 --- a/arch/arm/plat-orion/include/plat/cache-feroceon-l2.h +++ b/arch/arm/include/asm/hardware/cache-feroceon-l2.h | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/plat-orion/include/plat/cache-feroceon-l2.h | 2 | * arch/arm/include/asm/hardware/cache-feroceon-l2.h |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2008 Marvell Semiconductor | 4 | * Copyright (C) 2008 Marvell Semiconductor |
| 5 | * | 5 | * |
| @@ -9,3 +9,5 @@ | |||
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | extern void __init feroceon_l2_init(int l2_wt_override); | 11 | extern void __init feroceon_l2_init(int l2_wt_override); |
| 12 | extern int __init feroceon_of_init(void); | ||
| 13 | |||
diff --git a/arch/arm/include/asm/timex.h b/arch/arm/include/asm/timex.h index 83f2aa83899c..f6fcc67ef06e 100644 --- a/arch/arm/include/asm/timex.h +++ b/arch/arm/include/asm/timex.h | |||
| @@ -12,12 +12,6 @@ | |||
| 12 | #ifndef _ASMARM_TIMEX_H | 12 | #ifndef _ASMARM_TIMEX_H |
| 13 | #define _ASMARM_TIMEX_H | 13 | #define _ASMARM_TIMEX_H |
| 14 | 14 | ||
| 15 | #ifdef CONFIG_ARCH_MULTIPLATFORM | ||
| 16 | #define CLOCK_TICK_RATE 1000000 | ||
| 17 | #else | ||
| 18 | #include <mach/timex.h> | ||
| 19 | #endif | ||
| 20 | |||
| 21 | typedef unsigned long cycles_t; | 15 | typedef unsigned long cycles_t; |
| 22 | #define get_cycles() ({ cycles_t c; read_current_timer(&c) ? 0 : c; }) | 16 | #define get_cycles() ({ cycles_t c; read_current_timer(&c) ? 0 : c; }) |
| 23 | 17 | ||
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c index e47f5fd232f5..787bb50a4dff 100644 --- a/arch/arm/mach-at91/at91rm9200.c +++ b/arch/arm/mach-at91/at91rm9200.c | |||
| @@ -21,6 +21,7 @@ | |||
| 21 | #include <mach/at91rm9200.h> | 21 | #include <mach/at91rm9200.h> |
| 22 | #include <mach/at91_st.h> | 22 | #include <mach/at91_st.h> |
| 23 | #include <mach/cpu.h> | 23 | #include <mach/cpu.h> |
| 24 | #include <mach/hardware.h> | ||
| 24 | 25 | ||
| 25 | #include "at91_aic.h" | 26 | #include "at91_aic.h" |
| 26 | #include "soc.h" | 27 | #include "soc.h" |
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c index 3ebc9792560c..f3f19f21352a 100644 --- a/arch/arm/mach-at91/at91rm9200_devices.c +++ b/arch/arm/mach-at91/at91rm9200_devices.c | |||
| @@ -21,6 +21,7 @@ | |||
| 21 | #include <mach/at91rm9200.h> | 21 | #include <mach/at91rm9200.h> |
| 22 | #include <mach/at91rm9200_mc.h> | 22 | #include <mach/at91rm9200_mc.h> |
| 23 | #include <mach/at91_ramc.h> | 23 | #include <mach/at91_ramc.h> |
| 24 | #include <mach/hardware.h> | ||
| 24 | 25 | ||
| 25 | #include "board.h" | 26 | #include "board.h" |
| 26 | #include "generic.h" | 27 | #include "generic.h" |
| @@ -922,6 +923,7 @@ static struct resource dbgu_resources[] = { | |||
| 922 | static struct atmel_uart_data dbgu_data = { | 923 | static struct atmel_uart_data dbgu_data = { |
| 923 | .use_dma_tx = 0, | 924 | .use_dma_tx = 0, |
| 924 | .use_dma_rx = 0, /* DBGU not capable of receive DMA */ | 925 | .use_dma_rx = 0, /* DBGU not capable of receive DMA */ |
| 926 | .rts_gpio = -EINVAL, | ||
| 925 | }; | 927 | }; |
| 926 | 928 | ||
| 927 | static u64 dbgu_dmamask = DMA_BIT_MASK(32); | 929 | static u64 dbgu_dmamask = DMA_BIT_MASK(32); |
| @@ -960,6 +962,7 @@ static struct resource uart0_resources[] = { | |||
| 960 | static struct atmel_uart_data uart0_data = { | 962 | static struct atmel_uart_data uart0_data = { |
| 961 | .use_dma_tx = 1, | 963 | .use_dma_tx = 1, |
| 962 | .use_dma_rx = 1, | 964 | .use_dma_rx = 1, |
| 965 | .rts_gpio = -EINVAL, | ||
| 963 | }; | 966 | }; |
| 964 | 967 | ||
| 965 | static u64 uart0_dmamask = DMA_BIT_MASK(32); | 968 | static u64 uart0_dmamask = DMA_BIT_MASK(32); |
| @@ -987,9 +990,10 @@ static inline void configure_usart0_pins(unsigned pins) | |||
| 987 | if (pins & ATMEL_UART_RTS) { | 990 | if (pins & ATMEL_UART_RTS) { |
| 988 | /* | 991 | /* |
| 989 | * AT91RM9200 Errata #39 - RTS0 is not internally connected to PA21. | 992 | * AT91RM9200 Errata #39 - RTS0 is not internally connected to PA21. |
| 990 | * We need to drive the pin manually. Default is off (RTS is active low). | 993 | * We need to drive the pin manually. The serial driver will driver |
| 994 | * this to high when initializing. | ||
| 991 | */ | 995 | */ |
| 992 | at91_set_gpio_output(AT91_PIN_PA21, 1); | 996 | uart0_data.rts_gpio = AT91_PIN_PA21; |
| 993 | } | 997 | } |
| 994 | } | 998 | } |
| 995 | 999 | ||
| @@ -1009,6 +1013,7 @@ static struct resource uart1_resources[] = { | |||
| 1009 | static struct atmel_uart_data uart1_data = { | 1013 | static struct atmel_uart_data uart1_data = { |
| 1010 | .use_dma_tx = 1, | 1014 | .use_dma_tx = 1, |
| 1011 | .use_dma_rx = 1, | 1015 | .use_dma_rx = 1, |
| 1016 | .rts_gpio = -EINVAL, | ||
| 1012 | }; | 1017 | }; |
| 1013 | 1018 | ||
| 1014 | static u64 uart1_dmamask = DMA_BIT_MASK(32); | 1019 | static u64 uart1_dmamask = DMA_BIT_MASK(32); |
| @@ -1060,6 +1065,7 @@ static struct resource uart2_resources[] = { | |||
| 1060 | static struct atmel_uart_data uart2_data = { | 1065 | static struct atmel_uart_data uart2_data = { |
| 1061 | .use_dma_tx = 1, | 1066 | .use_dma_tx = 1, |
| 1062 | .use_dma_rx = 1, | 1067 | .use_dma_rx = 1, |
| 1068 | .rts_gpio = -EINVAL, | ||
| 1063 | }; | 1069 | }; |
| 1064 | 1070 | ||
| 1065 | static u64 uart2_dmamask = DMA_BIT_MASK(32); | 1071 | static u64 uart2_dmamask = DMA_BIT_MASK(32); |
| @@ -1103,6 +1109,7 @@ static struct resource uart3_resources[] = { | |||
| 1103 | static struct atmel_uart_data uart3_data = { | 1109 | static struct atmel_uart_data uart3_data = { |
| 1104 | .use_dma_tx = 1, | 1110 | .use_dma_tx = 1, |
| 1105 | .use_dma_rx = 1, | 1111 | .use_dma_rx = 1, |
| 1112 | .rts_gpio = -EINVAL, | ||
| 1106 | }; | 1113 | }; |
| 1107 | 1114 | ||
| 1108 | static u64 uart3_dmamask = DMA_BIT_MASK(32); | 1115 | static u64 uart3_dmamask = DMA_BIT_MASK(32); |
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c index bc7b363a3083..7fd13aef9827 100644 --- a/arch/arm/mach-at91/at91rm9200_time.c +++ b/arch/arm/mach-at91/at91rm9200_time.c | |||
| @@ -31,6 +31,7 @@ | |||
| 31 | #include <asm/mach/time.h> | 31 | #include <asm/mach/time.h> |
| 32 | 32 | ||
| 33 | #include <mach/at91_st.h> | 33 | #include <mach/at91_st.h> |
| 34 | #include <mach/hardware.h> | ||
| 34 | 35 | ||
| 35 | static unsigned long last_crtr; | 36 | static unsigned long last_crtr; |
| 36 | static u32 irqmask; | 37 | static u32 irqmask; |
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c index 6c821e562159..c3d22be73b7c 100644 --- a/arch/arm/mach-at91/at91sam9260.c +++ b/arch/arm/mach-at91/at91sam9260.c | |||
| @@ -21,6 +21,7 @@ | |||
| 21 | #include <mach/cpu.h> | 21 | #include <mach/cpu.h> |
| 22 | #include <mach/at91_dbgu.h> | 22 | #include <mach/at91_dbgu.h> |
| 23 | #include <mach/at91sam9260.h> | 23 | #include <mach/at91sam9260.h> |
| 24 | #include <mach/hardware.h> | ||
| 24 | 25 | ||
| 25 | #include "at91_aic.h" | 26 | #include "at91_aic.h" |
| 26 | #include "at91_rstc.h" | 27 | #include "at91_rstc.h" |
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c index eda8d1679d40..2ae7715f1309 100644 --- a/arch/arm/mach-at91/at91sam9260_devices.c +++ b/arch/arm/mach-at91/at91sam9260_devices.c | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | #include <mach/at91_matrix.h> | 25 | #include <mach/at91_matrix.h> |
| 26 | #include <mach/at91sam9_smc.h> | 26 | #include <mach/at91sam9_smc.h> |
| 27 | #include <mach/at91_adc.h> | 27 | #include <mach/at91_adc.h> |
| 28 | #include <mach/hardware.h> | ||
| 28 | 29 | ||
| 29 | #include "board.h" | 30 | #include "board.h" |
| 30 | #include "generic.h" | 31 | #include "generic.h" |
| @@ -819,6 +820,7 @@ static struct resource dbgu_resources[] = { | |||
| 819 | static struct atmel_uart_data dbgu_data = { | 820 | static struct atmel_uart_data dbgu_data = { |
| 820 | .use_dma_tx = 0, | 821 | .use_dma_tx = 0, |
| 821 | .use_dma_rx = 0, /* DBGU not capable of receive DMA */ | 822 | .use_dma_rx = 0, /* DBGU not capable of receive DMA */ |
| 823 | .rts_gpio = -EINVAL, | ||
| 822 | }; | 824 | }; |
| 823 | 825 | ||
| 824 | static u64 dbgu_dmamask = DMA_BIT_MASK(32); | 826 | static u64 dbgu_dmamask = DMA_BIT_MASK(32); |
| @@ -857,6 +859,7 @@ static struct resource uart0_resources[] = { | |||
| 857 | static struct atmel_uart_data uart0_data = { | 859 | static struct atmel_uart_data uart0_data = { |
| 858 | .use_dma_tx = 1, | 860 | .use_dma_tx = 1, |
| 859 | .use_dma_rx = 1, | 861 | .use_dma_rx = 1, |
| 862 | .rts_gpio = -EINVAL, | ||
| 860 | }; | 863 | }; |
| 861 | 864 | ||
| 862 | static u64 uart0_dmamask = DMA_BIT_MASK(32); | 865 | static u64 uart0_dmamask = DMA_BIT_MASK(32); |
| @@ -908,6 +911,7 @@ static struct resource uart1_resources[] = { | |||
| 908 | static struct atmel_uart_data uart1_data = { | 911 | static struct atmel_uart_data uart1_data = { |
| 909 | .use_dma_tx = 1, | 912 | .use_dma_tx = 1, |
| 910 | .use_dma_rx = 1, | 913 | .use_dma_rx = 1, |
| 914 | .rts_gpio = -EINVAL, | ||
| 911 | }; | 915 | }; |
| 912 | 916 | ||
| 913 | static u64 uart1_dmamask = DMA_BIT_MASK(32); | 917 | static u64 uart1_dmamask = DMA_BIT_MASK(32); |
| @@ -951,6 +955,7 @@ static struct resource uart2_resources[] = { | |||
| 951 | static struct atmel_uart_data uart2_data = { | 955 | static struct atmel_uart_data uart2_data = { |
| 952 | .use_dma_tx = 1, | 956 | .use_dma_tx = 1, |
| 953 | .use_dma_rx = 1, | 957 | .use_dma_rx = 1, |
| 958 | .rts_gpio = -EINVAL, | ||
| 954 | }; | 959 | }; |
| 955 | 960 | ||
| 956 | static u64 uart2_dmamask = DMA_BIT_MASK(32); | 961 | static u64 uart2_dmamask = DMA_BIT_MASK(32); |
| @@ -994,6 +999,7 @@ static struct resource uart3_resources[] = { | |||
| 994 | static struct atmel_uart_data uart3_data = { | 999 | static struct atmel_uart_data uart3_data = { |
| 995 | .use_dma_tx = 1, | 1000 | .use_dma_tx = 1, |
| 996 | .use_dma_rx = 1, | 1001 | .use_dma_rx = 1, |
| 1002 | .rts_gpio = -EINVAL, | ||
| 997 | }; | 1003 | }; |
| 998 | 1004 | ||
| 999 | static u64 uart3_dmamask = DMA_BIT_MASK(32); | 1005 | static u64 uart3_dmamask = DMA_BIT_MASK(32); |
| @@ -1037,6 +1043,7 @@ static struct resource uart4_resources[] = { | |||
| 1037 | static struct atmel_uart_data uart4_data = { | 1043 | static struct atmel_uart_data uart4_data = { |
| 1038 | .use_dma_tx = 1, | 1044 | .use_dma_tx = 1, |
| 1039 | .use_dma_rx = 1, | 1045 | .use_dma_rx = 1, |
| 1046 | .rts_gpio = -EINVAL, | ||
| 1040 | }; | 1047 | }; |
| 1041 | 1048 | ||
| 1042 | static u64 uart4_dmamask = DMA_BIT_MASK(32); | 1049 | static u64 uart4_dmamask = DMA_BIT_MASK(32); |
| @@ -1075,6 +1082,7 @@ static struct resource uart5_resources[] = { | |||
| 1075 | static struct atmel_uart_data uart5_data = { | 1082 | static struct atmel_uart_data uart5_data = { |
| 1076 | .use_dma_tx = 1, | 1083 | .use_dma_tx = 1, |
| 1077 | .use_dma_rx = 1, | 1084 | .use_dma_rx = 1, |
| 1085 | .rts_gpio = -EINVAL, | ||
| 1078 | }; | 1086 | }; |
| 1079 | 1087 | ||
| 1080 | static u64 uart5_dmamask = DMA_BIT_MASK(32); | 1088 | static u64 uart5_dmamask = DMA_BIT_MASK(32); |
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c index 6276b4c1acfe..48b51f796d6a 100644 --- a/arch/arm/mach-at91/at91sam9261.c +++ b/arch/arm/mach-at91/at91sam9261.c | |||
| @@ -20,6 +20,7 @@ | |||
| 20 | #include <asm/system_misc.h> | 20 | #include <asm/system_misc.h> |
| 21 | #include <mach/cpu.h> | 21 | #include <mach/cpu.h> |
| 22 | #include <mach/at91sam9261.h> | 22 | #include <mach/at91sam9261.h> |
| 23 | #include <mach/hardware.h> | ||
| 23 | 24 | ||
| 24 | #include "at91_aic.h" | 25 | #include "at91_aic.h" |
| 25 | #include "at91_rstc.h" | 26 | #include "at91_rstc.h" |
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c index b2a34740146a..80e35895d28f 100644 --- a/arch/arm/mach-at91/at91sam9261_devices.c +++ b/arch/arm/mach-at91/at91sam9261_devices.c | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | #include <mach/at91sam9261_matrix.h> | 25 | #include <mach/at91sam9261_matrix.h> |
| 26 | #include <mach/at91_matrix.h> | 26 | #include <mach/at91_matrix.h> |
| 27 | #include <mach/at91sam9_smc.h> | 27 | #include <mach/at91sam9_smc.h> |
| 28 | #include <mach/hardware.h> | ||
| 28 | 29 | ||
| 29 | #include "board.h" | 30 | #include "board.h" |
| 30 | #include "generic.h" | 31 | #include "generic.h" |
| @@ -880,6 +881,7 @@ static struct resource dbgu_resources[] = { | |||
| 880 | static struct atmel_uart_data dbgu_data = { | 881 | static struct atmel_uart_data dbgu_data = { |
| 881 | .use_dma_tx = 0, | 882 | .use_dma_tx = 0, |
| 882 | .use_dma_rx = 0, /* DBGU not capable of receive DMA */ | 883 | .use_dma_rx = 0, /* DBGU not capable of receive DMA */ |
| 884 | .rts_gpio = -EINVAL, | ||
| 883 | }; | 885 | }; |
| 884 | 886 | ||
| 885 | static u64 dbgu_dmamask = DMA_BIT_MASK(32); | 887 | static u64 dbgu_dmamask = DMA_BIT_MASK(32); |
| @@ -918,6 +920,7 @@ static struct resource uart0_resources[] = { | |||
| 918 | static struct atmel_uart_data uart0_data = { | 920 | static struct atmel_uart_data uart0_data = { |
| 919 | .use_dma_tx = 1, | 921 | .use_dma_tx = 1, |
| 920 | .use_dma_rx = 1, | 922 | .use_dma_rx = 1, |
| 923 | .rts_gpio = -EINVAL, | ||
| 921 | }; | 924 | }; |
| 922 | 925 | ||
| 923 | static u64 uart0_dmamask = DMA_BIT_MASK(32); | 926 | static u64 uart0_dmamask = DMA_BIT_MASK(32); |
| @@ -961,6 +964,7 @@ static struct resource uart1_resources[] = { | |||
| 961 | static struct atmel_uart_data uart1_data = { | 964 | static struct atmel_uart_data uart1_data = { |
| 962 | .use_dma_tx = 1, | 965 | .use_dma_tx = 1, |
| 963 | .use_dma_rx = 1, | 966 | .use_dma_rx = 1, |
| 967 | .rts_gpio = -EINVAL, | ||
| 964 | }; | 968 | }; |
| 965 | 969 | ||
| 966 | static u64 uart1_dmamask = DMA_BIT_MASK(32); | 970 | static u64 uart1_dmamask = DMA_BIT_MASK(32); |
| @@ -1004,6 +1008,7 @@ static struct resource uart2_resources[] = { | |||
| 1004 | static struct atmel_uart_data uart2_data = { | 1008 | static struct atmel_uart_data uart2_data = { |
| 1005 | .use_dma_tx = 1, | 1009 | .use_dma_tx = 1, |
| 1006 | .use_dma_rx = 1, | 1010 | .use_dma_rx = 1, |
| 1011 | .rts_gpio = -EINVAL, | ||
| 1007 | }; | 1012 | }; |
| 1008 | 1013 | ||
| 1009 | static u64 uart2_dmamask = DMA_BIT_MASK(32); | 1014 | static u64 uart2_dmamask = DMA_BIT_MASK(32); |
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c index 37b90f4b990c..486530c3973b 100644 --- a/arch/arm/mach-at91/at91sam9263.c +++ b/arch/arm/mach-at91/at91sam9263.c | |||
| @@ -19,6 +19,7 @@ | |||
| 19 | #include <asm/mach/map.h> | 19 | #include <asm/mach/map.h> |
| 20 | #include <asm/system_misc.h> | 20 | #include <asm/system_misc.h> |
| 21 | #include <mach/at91sam9263.h> | 21 | #include <mach/at91sam9263.h> |
| 22 | #include <mach/hardware.h> | ||
| 22 | 23 | ||
| 23 | #include "at91_aic.h" | 24 | #include "at91_aic.h" |
| 24 | #include "at91_rstc.h" | 25 | #include "at91_rstc.h" |
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c index 4aeadddbc181..43d53d6156dd 100644 --- a/arch/arm/mach-at91/at91sam9263_devices.c +++ b/arch/arm/mach-at91/at91sam9263_devices.c | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | #include <mach/at91sam9263_matrix.h> | 24 | #include <mach/at91sam9263_matrix.h> |
| 25 | #include <mach/at91_matrix.h> | 25 | #include <mach/at91_matrix.h> |
| 26 | #include <mach/at91sam9_smc.h> | 26 | #include <mach/at91sam9_smc.h> |
| 27 | #include <mach/hardware.h> | ||
| 27 | 28 | ||
| 28 | #include "board.h" | 29 | #include "board.h" |
| 29 | #include "generic.h" | 30 | #include "generic.h" |
| @@ -1324,6 +1325,7 @@ static struct resource dbgu_resources[] = { | |||
| 1324 | static struct atmel_uart_data dbgu_data = { | 1325 | static struct atmel_uart_data dbgu_data = { |
| 1325 | .use_dma_tx = 0, | 1326 | .use_dma_tx = 0, |
| 1326 | .use_dma_rx = 0, /* DBGU not capable of receive DMA */ | 1327 | .use_dma_rx = 0, /* DBGU not capable of receive DMA */ |
| 1328 | .rts_gpio = -EINVAL, | ||
| 1327 | }; | 1329 | }; |
| 1328 | 1330 | ||
| 1329 | static u64 dbgu_dmamask = DMA_BIT_MASK(32); | 1331 | static u64 dbgu_dmamask = DMA_BIT_MASK(32); |
| @@ -1362,6 +1364,7 @@ static struct resource uart0_resources[] = { | |||
| 1362 | static struct atmel_uart_data uart0_data = { | 1364 | static struct atmel_uart_data uart0_data = { |
| 1363 | .use_dma_tx = 1, | 1365 | .use_dma_tx = 1, |
| 1364 | .use_dma_rx = 1, | 1366 | .use_dma_rx = 1, |
| 1367 | .rts_gpio = -EINVAL, | ||
| 1365 | }; | 1368 | }; |
| 1366 | 1369 | ||
| 1367 | static u64 uart0_dmamask = DMA_BIT_MASK(32); | 1370 | static u64 uart0_dmamask = DMA_BIT_MASK(32); |
| @@ -1405,6 +1408,7 @@ static struct resource uart1_resources[] = { | |||
| 1405 | static struct atmel_uart_data uart1_data = { | 1408 | static struct atmel_uart_data uart1_data = { |
| 1406 | .use_dma_tx = 1, | 1409 | .use_dma_tx = 1, |
| 1407 | .use_dma_rx = 1, | 1410 | .use_dma_rx = 1, |
| 1411 | .rts_gpio = -EINVAL, | ||
| 1408 | }; | 1412 | }; |
| 1409 | 1413 | ||
| 1410 | static u64 uart1_dmamask = DMA_BIT_MASK(32); | 1414 | static u64 uart1_dmamask = DMA_BIT_MASK(32); |
| @@ -1448,6 +1452,7 @@ static struct resource uart2_resources[] = { | |||
| 1448 | static struct atmel_uart_data uart2_data = { | 1452 | static struct atmel_uart_data uart2_data = { |
| 1449 | .use_dma_tx = 1, | 1453 | .use_dma_tx = 1, |
| 1450 | .use_dma_rx = 1, | 1454 | .use_dma_rx = 1, |
| 1455 | .rts_gpio = -EINVAL, | ||
| 1451 | }; | 1456 | }; |
| 1452 | 1457 | ||
| 1453 | static u64 uart2_dmamask = DMA_BIT_MASK(32); | 1458 | static u64 uart2_dmamask = DMA_BIT_MASK(32); |
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c index 0f04ffe9c5a8..0a9e2fc8f796 100644 --- a/arch/arm/mach-at91/at91sam926x_time.c +++ b/arch/arm/mach-at91/at91sam926x_time.c | |||
| @@ -19,6 +19,7 @@ | |||
| 19 | #include <linux/of_irq.h> | 19 | #include <linux/of_irq.h> |
| 20 | 20 | ||
| 21 | #include <asm/mach/time.h> | 21 | #include <asm/mach/time.h> |
| 22 | #include <mach/hardware.h> | ||
| 22 | 23 | ||
| 23 | #define AT91_PIT_MR 0x00 /* Mode Register */ | 24 | #define AT91_PIT_MR 0x00 /* Mode Register */ |
| 24 | #define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */ | 25 | #define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */ |
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index 2f455ce35268..8c11696f606e 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c | |||
| @@ -20,6 +20,7 @@ | |||
| 20 | #include <asm/system_misc.h> | 20 | #include <asm/system_misc.h> |
| 21 | #include <mach/at91sam9g45.h> | 21 | #include <mach/at91sam9g45.h> |
| 22 | #include <mach/cpu.h> | 22 | #include <mach/cpu.h> |
| 23 | #include <mach/hardware.h> | ||
| 23 | 24 | ||
| 24 | #include "at91_aic.h" | 25 | #include "at91_aic.h" |
| 25 | #include "soc.h" | 26 | #include "soc.h" |
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c index cb36fa872d30..77b04c2edd78 100644 --- a/arch/arm/mach-at91/at91sam9g45_devices.c +++ b/arch/arm/mach-at91/at91sam9g45_devices.c | |||
| @@ -32,6 +32,7 @@ | |||
| 32 | #include <mach/at91sam9_smc.h> | 32 | #include <mach/at91sam9_smc.h> |
| 33 | #include <linux/platform_data/dma-atmel.h> | 33 | #include <linux/platform_data/dma-atmel.h> |
| 34 | #include <mach/atmel-mci.h> | 34 | #include <mach/atmel-mci.h> |
| 35 | #include <mach/hardware.h> | ||
| 35 | 36 | ||
| 36 | #include <media/atmel-isi.h> | 37 | #include <media/atmel-isi.h> |
| 37 | 38 | ||
| @@ -1587,6 +1588,7 @@ static struct resource dbgu_resources[] = { | |||
| 1587 | static struct atmel_uart_data dbgu_data = { | 1588 | static struct atmel_uart_data dbgu_data = { |
| 1588 | .use_dma_tx = 0, | 1589 | .use_dma_tx = 0, |
| 1589 | .use_dma_rx = 0, | 1590 | .use_dma_rx = 0, |
| 1591 | .rts_gpio = -EINVAL, | ||
| 1590 | }; | 1592 | }; |
| 1591 | 1593 | ||
| 1592 | static u64 dbgu_dmamask = DMA_BIT_MASK(32); | 1594 | static u64 dbgu_dmamask = DMA_BIT_MASK(32); |
| @@ -1625,6 +1627,7 @@ static struct resource uart0_resources[] = { | |||
| 1625 | static struct atmel_uart_data uart0_data = { | 1627 | static struct atmel_uart_data uart0_data = { |
| 1626 | .use_dma_tx = 1, | 1628 | .use_dma_tx = 1, |
| 1627 | .use_dma_rx = 1, | 1629 | .use_dma_rx = 1, |
| 1630 | .rts_gpio = -EINVAL, | ||
| 1628 | }; | 1631 | }; |
| 1629 | 1632 | ||
| 1630 | static u64 uart0_dmamask = DMA_BIT_MASK(32); | 1633 | static u64 uart0_dmamask = DMA_BIT_MASK(32); |
| @@ -1668,6 +1671,7 @@ static struct resource uart1_resources[] = { | |||
| 1668 | static struct atmel_uart_data uart1_data = { | 1671 | static struct atmel_uart_data uart1_data = { |
| 1669 | .use_dma_tx = 1, | 1672 | .use_dma_tx = 1, |
| 1670 | .use_dma_rx = 1, | 1673 | .use_dma_rx = 1, |
| 1674 | .rts_gpio = -EINVAL, | ||
| 1671 | }; | 1675 | }; |
| 1672 | 1676 | ||
| 1673 | static u64 uart1_dmamask = DMA_BIT_MASK(32); | 1677 | static u64 uart1_dmamask = DMA_BIT_MASK(32); |
| @@ -1711,6 +1715,7 @@ static struct resource uart2_resources[] = { | |||
| 1711 | static struct atmel_uart_data uart2_data = { | 1715 | static struct atmel_uart_data uart2_data = { |
| 1712 | .use_dma_tx = 1, | 1716 | .use_dma_tx = 1, |
| 1713 | .use_dma_rx = 1, | 1717 | .use_dma_rx = 1, |
| 1718 | .rts_gpio = -EINVAL, | ||
| 1714 | }; | 1719 | }; |
| 1715 | 1720 | ||
| 1716 | static u64 uart2_dmamask = DMA_BIT_MASK(32); | 1721 | static u64 uart2_dmamask = DMA_BIT_MASK(32); |
| @@ -1754,6 +1759,7 @@ static struct resource uart3_resources[] = { | |||
| 1754 | static struct atmel_uart_data uart3_data = { | 1759 | static struct atmel_uart_data uart3_data = { |
| 1755 | .use_dma_tx = 1, | 1760 | .use_dma_tx = 1, |
| 1756 | .use_dma_rx = 1, | 1761 | .use_dma_rx = 1, |
| 1762 | .rts_gpio = -EINVAL, | ||
| 1757 | }; | 1763 | }; |
| 1758 | 1764 | ||
| 1759 | static u64 uart3_dmamask = DMA_BIT_MASK(32); | 1765 | static u64 uart3_dmamask = DMA_BIT_MASK(32); |
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c index 3651517abedf..c0d5474706f8 100644 --- a/arch/arm/mach-at91/at91sam9rl.c +++ b/arch/arm/mach-at91/at91sam9rl.c | |||
| @@ -20,6 +20,7 @@ | |||
| 20 | #include <mach/cpu.h> | 20 | #include <mach/cpu.h> |
| 21 | #include <mach/at91_dbgu.h> | 21 | #include <mach/at91_dbgu.h> |
| 22 | #include <mach/at91sam9rl.h> | 22 | #include <mach/at91sam9rl.h> |
| 23 | #include <mach/hardware.h> | ||
| 23 | 24 | ||
| 24 | #include "at91_aic.h" | 25 | #include "at91_aic.h" |
| 25 | #include "at91_rstc.h" | 26 | #include "at91_rstc.h" |
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c index a698bdab2cce..428fc412aaf1 100644 --- a/arch/arm/mach-at91/at91sam9rl_devices.c +++ b/arch/arm/mach-at91/at91sam9rl_devices.c | |||
| @@ -21,6 +21,7 @@ | |||
| 21 | #include <mach/at91sam9rl_matrix.h> | 21 | #include <mach/at91sam9rl_matrix.h> |
| 22 | #include <mach/at91_matrix.h> | 22 | #include <mach/at91_matrix.h> |
| 23 | #include <mach/at91sam9_smc.h> | 23 | #include <mach/at91sam9_smc.h> |
| 24 | #include <mach/hardware.h> | ||
| 24 | #include <linux/platform_data/dma-atmel.h> | 25 | #include <linux/platform_data/dma-atmel.h> |
| 25 | 26 | ||
| 26 | #include "board.h" | 27 | #include "board.h" |
| @@ -956,6 +957,7 @@ static struct resource dbgu_resources[] = { | |||
| 956 | static struct atmel_uart_data dbgu_data = { | 957 | static struct atmel_uart_data dbgu_data = { |
| 957 | .use_dma_tx = 0, | 958 | .use_dma_tx = 0, |
| 958 | .use_dma_rx = 0, /* DBGU not capable of receive DMA */ | 959 | .use_dma_rx = 0, /* DBGU not capable of receive DMA */ |
| 960 | .rts_gpio = -EINVAL, | ||
| 959 | }; | 961 | }; |
| 960 | 962 | ||
| 961 | static u64 dbgu_dmamask = DMA_BIT_MASK(32); | 963 | static u64 dbgu_dmamask = DMA_BIT_MASK(32); |
| @@ -994,6 +996,7 @@ static struct resource uart0_resources[] = { | |||
| 994 | static struct atmel_uart_data uart0_data = { | 996 | static struct atmel_uart_data uart0_data = { |
| 995 | .use_dma_tx = 1, | 997 | .use_dma_tx = 1, |
| 996 | .use_dma_rx = 1, | 998 | .use_dma_rx = 1, |
| 999 | .rts_gpio = -EINVAL, | ||
| 997 | }; | 1000 | }; |
| 998 | 1001 | ||
| 999 | static u64 uart0_dmamask = DMA_BIT_MASK(32); | 1002 | static u64 uart0_dmamask = DMA_BIT_MASK(32); |
| @@ -1045,6 +1048,7 @@ static struct resource uart1_resources[] = { | |||
| 1045 | static struct atmel_uart_data uart1_data = { | 1048 | static struct atmel_uart_data uart1_data = { |
| 1046 | .use_dma_tx = 1, | 1049 | .use_dma_tx = 1, |
| 1047 | .use_dma_rx = 1, | 1050 | .use_dma_rx = 1, |
| 1051 | .rts_gpio = -EINVAL, | ||
| 1048 | }; | 1052 | }; |
| 1049 | 1053 | ||
| 1050 | static u64 uart1_dmamask = DMA_BIT_MASK(32); | 1054 | static u64 uart1_dmamask = DMA_BIT_MASK(32); |
| @@ -1088,6 +1092,7 @@ static struct resource uart2_resources[] = { | |||
| 1088 | static struct atmel_uart_data uart2_data = { | 1092 | static struct atmel_uart_data uart2_data = { |
| 1089 | .use_dma_tx = 1, | 1093 | .use_dma_tx = 1, |
| 1090 | .use_dma_rx = 1, | 1094 | .use_dma_rx = 1, |
| 1095 | .rts_gpio = -EINVAL, | ||
| 1091 | }; | 1096 | }; |
| 1092 | 1097 | ||
| 1093 | static u64 uart2_dmamask = DMA_BIT_MASK(32); | 1098 | static u64 uart2_dmamask = DMA_BIT_MASK(32); |
| @@ -1131,6 +1136,7 @@ static struct resource uart3_resources[] = { | |||
| 1131 | static struct atmel_uart_data uart3_data = { | 1136 | static struct atmel_uart_data uart3_data = { |
| 1132 | .use_dma_tx = 1, | 1137 | .use_dma_tx = 1, |
| 1133 | .use_dma_rx = 1, | 1138 | .use_dma_rx = 1, |
| 1139 | .rts_gpio = -EINVAL, | ||
| 1134 | }; | 1140 | }; |
| 1135 | 1141 | ||
| 1136 | static u64 uart3_dmamask = DMA_BIT_MASK(32); | 1142 | static u64 uart3_dmamask = DMA_BIT_MASK(32); |
diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c index bad94b84a46f..7523f1cdfe1d 100644 --- a/arch/arm/mach-at91/at91x40.c +++ b/arch/arm/mach-at91/at91x40.c | |||
| @@ -19,7 +19,7 @@ | |||
| 19 | #include <asm/mach/arch.h> | 19 | #include <asm/mach/arch.h> |
| 20 | #include <mach/at91x40.h> | 20 | #include <mach/at91x40.h> |
| 21 | #include <mach/at91_st.h> | 21 | #include <mach/at91_st.h> |
| 22 | #include <mach/timex.h> | 22 | #include <mach/hardware.h> |
| 23 | 23 | ||
| 24 | #include "at91_aic.h" | 24 | #include "at91_aic.h" |
| 25 | #include "generic.h" | 25 | #include "generic.h" |
diff --git a/arch/arm/mach-at91/at91x40_time.c b/arch/arm/mach-at91/at91x40_time.c index c0e637adf65d..07d0bf2ac2da 100644 --- a/arch/arm/mach-at91/at91x40_time.c +++ b/arch/arm/mach-at91/at91x40_time.c | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | #include <linux/time.h> | 25 | #include <linux/time.h> |
| 26 | #include <linux/io.h> | 26 | #include <linux/io.h> |
| 27 | #include <mach/hardware.h> | 27 | #include <mach/hardware.h> |
| 28 | #include <mach/at91x40.h> | ||
| 28 | #include <asm/mach/time.h> | 29 | #include <asm/mach/time.h> |
| 29 | 30 | ||
| 30 | #include "at91_tc.h" | 31 | #include "at91_tc.h" |
diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c index c1d61d247790..416bae8435ee 100644 --- a/arch/arm/mach-at91/board-gsia18s.c +++ b/arch/arm/mach-at91/board-gsia18s.c | |||
| @@ -31,6 +31,7 @@ | |||
| 31 | #include <asm/mach/arch.h> | 31 | #include <asm/mach/arch.h> |
| 32 | 32 | ||
| 33 | #include <mach/at91sam9_smc.h> | 33 | #include <mach/at91sam9_smc.h> |
| 34 | #include <mach/hardware.h> | ||
| 34 | 35 | ||
| 35 | #include "at91_aic.h" | 36 | #include "at91_aic.h" |
| 36 | #include "board.h" | 37 | #include "board.h" |
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c index 65c0d6b5ecba..5f25fa54eb93 100644 --- a/arch/arm/mach-at91/board-pcontrol-g20.c +++ b/arch/arm/mach-at91/board-pcontrol-g20.c | |||
| @@ -30,6 +30,7 @@ | |||
| 30 | #include <asm/mach/arch.h> | 30 | #include <asm/mach/arch.h> |
| 31 | 31 | ||
| 32 | #include <mach/at91sam9_smc.h> | 32 | #include <mach/at91sam9_smc.h> |
| 33 | #include <mach/hardware.h> | ||
| 33 | 34 | ||
| 34 | #include "at91_aic.h" | 35 | #include "at91_aic.h" |
| 35 | #include "board.h" | 36 | #include "board.h" |
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c index 869cbecf00b7..e4a5ac17cdbc 100644 --- a/arch/arm/mach-at91/board-stamp9g20.c +++ b/arch/arm/mach-at91/board-stamp9g20.c | |||
| @@ -26,6 +26,7 @@ | |||
| 26 | #include <asm/mach/arch.h> | 26 | #include <asm/mach/arch.h> |
| 27 | 27 | ||
| 28 | #include <mach/at91sam9_smc.h> | 28 | #include <mach/at91sam9_smc.h> |
| 29 | #include <mach/hardware.h> | ||
| 29 | 30 | ||
| 30 | #include "at91_aic.h" | 31 | #include "at91_aic.h" |
| 31 | #include "board.h" | 32 | #include "board.h" |
diff --git a/arch/arm/mach-at91/include/mach/at91x40.h b/arch/arm/mach-at91/include/mach/at91x40.h index 90680217064e..38dca2bb027f 100644 --- a/arch/arm/mach-at91/include/mach/at91x40.h +++ b/arch/arm/mach-at91/include/mach/at91x40.h | |||
| @@ -55,4 +55,6 @@ | |||
| 55 | #define AT91_PS_CR (AT91_PS + 0) /* PS Control register */ | 55 | #define AT91_PS_CR (AT91_PS + 0) /* PS Control register */ |
| 56 | #define AT91_PS_CR_CPU (1 << 0) /* CPU clock disable bit */ | 56 | #define AT91_PS_CR_CPU (1 << 0) /* CPU clock disable bit */ |
| 57 | 57 | ||
| 58 | #define AT91X40_MASTER_CLOCK 40000000 | ||
| 59 | |||
| 58 | #endif /* AT91X40_H */ | 60 | #endif /* AT91X40_H */ |
diff --git a/arch/arm/mach-at91/include/mach/timex.h b/arch/arm/mach-at91/include/mach/timex.h deleted file mode 100644 index 5e917a66edd7..000000000000 --- a/arch/arm/mach-at91/include/mach/timex.h +++ /dev/null | |||
| @@ -1,37 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/timex.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 SAN People | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_TIMEX_H | ||
| 22 | #define __ASM_ARCH_TIMEX_H | ||
| 23 | |||
| 24 | #include <mach/hardware.h> | ||
| 25 | |||
| 26 | #ifdef CONFIG_ARCH_AT91X40 | ||
| 27 | |||
| 28 | #define AT91X40_MASTER_CLOCK 40000000 | ||
| 29 | #define CLOCK_TICK_RATE (AT91X40_MASTER_CLOCK) | ||
| 30 | |||
| 31 | #else | ||
| 32 | |||
| 33 | #define CLOCK_TICK_RATE 12345678 | ||
| 34 | |||
| 35 | #endif | ||
| 36 | |||
| 37 | #endif /* __ASM_ARCH_TIMEX_H */ | ||
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 590b52dea9f7..8bda1cefdf96 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c | |||
| @@ -27,6 +27,7 @@ | |||
| 27 | #include <asm/mach/irq.h> | 27 | #include <asm/mach/irq.h> |
| 28 | 28 | ||
| 29 | #include <mach/cpu.h> | 29 | #include <mach/cpu.h> |
| 30 | #include <mach/hardware.h> | ||
| 30 | 31 | ||
| 31 | #include "at91_aic.h" | 32 | #include "at91_aic.h" |
| 32 | #include "generic.h" | 33 | #include "generic.h" |
diff --git a/arch/arm/mach-clps711x/include/mach/timex.h b/arch/arm/mach-clps711x/include/mach/timex.h deleted file mode 100644 index de6fd192d1c3..000000000000 --- a/arch/arm/mach-clps711x/include/mach/timex.h +++ /dev/null | |||
| @@ -1,2 +0,0 @@ | |||
| 1 | /* Bogus value */ | ||
| 2 | #define CLOCK_TICK_RATE 512000 | ||
diff --git a/arch/arm/mach-davinci/include/mach/timex.h b/arch/arm/mach-davinci/include/mach/timex.h deleted file mode 100644 index 9b885298f106..000000000000 --- a/arch/arm/mach-davinci/include/mach/timex.h +++ /dev/null | |||
| @@ -1,22 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * DaVinci timer defines | ||
| 3 | * | ||
| 4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
| 5 | * | ||
| 6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
| 7 | * the terms of the GNU General Public License version 2. This program | ||
| 8 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 9 | * or implied. | ||
| 10 | */ | ||
| 11 | #ifndef __ASM_ARCH_TIMEX_H | ||
| 12 | #define __ASM_ARCH_TIMEX_H | ||
| 13 | |||
| 14 | /* | ||
| 15 | * Alert: Not all timers of the DaVinci family run at a frequency of 27MHz, | ||
| 16 | * but we should be fine as long as CLOCK_TICK_RATE or LATCH (see include/ | ||
| 17 | * linux/jiffies.h) are not used directly in code. Currently none of the | ||
| 18 | * code relevant to DaVinci platform depends on these values directly. | ||
| 19 | */ | ||
| 20 | #define CLOCK_TICK_RATE 27000000 | ||
| 21 | |||
| 22 | #endif /* __ASM_ARCH_TIMEX_H__ */ | ||
diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig index 0bc7cdf8cf46..d8c439c89ea9 100644 --- a/arch/arm/mach-dove/Kconfig +++ b/arch/arm/mach-dove/Kconfig | |||
| @@ -20,18 +20,6 @@ config MACH_CM_A510 | |||
| 20 | Say 'Y' here if you want your kernel to support the | 20 | Say 'Y' here if you want your kernel to support the |
| 21 | CompuLab CM-A510 Board. | 21 | CompuLab CM-A510 Board. |
| 22 | 22 | ||
| 23 | config MACH_DOVE_DT | ||
| 24 | bool "Marvell Dove Flattened Device Tree" | ||
| 25 | select DOVE_CLK | ||
| 26 | select ORION_IRQCHIP | ||
| 27 | select ORION_TIMER | ||
| 28 | select REGULATOR | ||
| 29 | select REGULATOR_FIXED_VOLTAGE | ||
| 30 | select USE_OF | ||
| 31 | help | ||
| 32 | Say 'Y' here if you want your kernel to support the | ||
| 33 | Marvell Dove using flattened device tree. | ||
| 34 | |||
| 35 | endmenu | 23 | endmenu |
| 36 | 24 | ||
| 37 | endif | 25 | endif |
diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile index cbc5c0618788..b608a21919fb 100644 --- a/arch/arm/mach-dove/Makefile +++ b/arch/arm/mach-dove/Makefile | |||
| @@ -2,5 +2,4 @@ obj-y += common.o | |||
| 2 | obj-$(CONFIG_DOVE_LEGACY) += irq.o mpp.o | 2 | obj-$(CONFIG_DOVE_LEGACY) += irq.o mpp.o |
| 3 | obj-$(CONFIG_PCI) += pcie.o | 3 | obj-$(CONFIG_PCI) += pcie.o |
| 4 | obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o | 4 | obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o |
| 5 | obj-$(CONFIG_MACH_DOVE_DT) += board-dt.o | ||
| 6 | obj-$(CONFIG_MACH_CM_A510) += cm-a510.o | 5 | obj-$(CONFIG_MACH_CM_A510) += cm-a510.o |
diff --git a/arch/arm/mach-dove/include/mach/timex.h b/arch/arm/mach-dove/include/mach/timex.h deleted file mode 100644 index 251d538541db..000000000000 --- a/arch/arm/mach-dove/include/mach/timex.h +++ /dev/null | |||
| @@ -1,9 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-dove/include/mach/timex.h | ||
| 3 | * | ||
| 4 | * This file is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2. This program is licensed "as is" without any | ||
| 6 | * warranty of any kind, whether express or implied. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #define CLOCK_TICK_RATE (100 * HZ) | ||
diff --git a/arch/arm/mach-ebsa110/include/mach/timex.h b/arch/arm/mach-ebsa110/include/mach/timex.h deleted file mode 100644 index 4fb43b22a102..000000000000 --- a/arch/arm/mach-ebsa110/include/mach/timex.h +++ /dev/null | |||
| @@ -1,19 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-ebsa110/include/mach/timex.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1997, 1998 Russell King | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * EBSA110 architecture timex specifications | ||
| 11 | */ | ||
| 12 | |||
| 13 | /* | ||
| 14 | * On the EBSA, the clock ticks at weird rates. | ||
| 15 | * This is therefore not used to calculate the | ||
| 16 | * divisor. | ||
| 17 | */ | ||
| 18 | #define CLOCK_TICK_RATE 47894000 | ||
| 19 | |||
diff --git a/arch/arm/mach-efm32/include/mach/entry-macro.S b/arch/arm/mach-efm32/include/mach/entry-macro.S deleted file mode 100644 index 322159d5ed91..000000000000 --- a/arch/arm/mach-efm32/include/mach/entry-macro.S +++ /dev/null | |||
| @@ -1,4 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Empty file waiting for deletion once <mach/entry-macro.S> isn't needed any | ||
| 3 | * more. Patch "ARM: v7-M: drop using mach/entry-macro.S" sitting in next. | ||
| 4 | */ | ||
diff --git a/arch/arm/mach-efm32/include/mach/timex.h b/arch/arm/mach-efm32/include/mach/timex.h deleted file mode 100644 index 7a8b26da6599..000000000000 --- a/arch/arm/mach-efm32/include/mach/timex.h +++ /dev/null | |||
| @@ -1,3 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Empty file waiting for deletion once <mach/timex.h> isn't needed any more. | ||
| 3 | */ | ||
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index 157ba88433c9..6c705472da6c 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c | |||
| @@ -117,7 +117,7 @@ void __init ep93xx_map_io(void) | |||
| 117 | #define EP93XX_TIMER4_CLOCK 983040 | 117 | #define EP93XX_TIMER4_CLOCK 983040 |
| 118 | 118 | ||
| 119 | #define TIMER1_RELOAD ((EP93XX_TIMER123_CLOCK / HZ) - 1) | 119 | #define TIMER1_RELOAD ((EP93XX_TIMER123_CLOCK / HZ) - 1) |
| 120 | #define TIMER4_TICKS_PER_JIFFY DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ) | 120 | #define TIMER4_TICKS_PER_JIFFY DIV_ROUND_CLOSEST(EP93XX_TIMER4_CLOCK, HZ) |
| 121 | 121 | ||
| 122 | static unsigned int last_jiffy_time; | 122 | static unsigned int last_jiffy_time; |
| 123 | 123 | ||
diff --git a/arch/arm/mach-ep93xx/include/mach/timex.h b/arch/arm/mach-ep93xx/include/mach/timex.h deleted file mode 100644 index 6b3503b01fa6..000000000000 --- a/arch/arm/mach-ep93xx/include/mach/timex.h +++ /dev/null | |||
| @@ -1,5 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-ep93xx/include/mach/timex.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #define CLOCK_TICK_RATE 983040 | ||
diff --git a/arch/arm/mach-exynos/include/mach/timex.h b/arch/arm/mach-exynos/include/mach/timex.h deleted file mode 100644 index 6d138750a708..000000000000 --- a/arch/arm/mach-exynos/include/mach/timex.h +++ /dev/null | |||
| @@ -1,29 +0,0 @@ | |||
| 1 | /* linux/arch/arm/mach-exynos4/include/mach/timex.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com | ||
| 5 | * | ||
| 6 | * Copyright (c) 2003-2010 Simtec Electronics | ||
| 7 | * Ben Dooks <ben@simtec.co.uk> | ||
| 8 | * | ||
| 9 | * Based on arch/arm/mach-s5p6442/include/mach/timex.h | ||
| 10 | * | ||
| 11 | * EXYNOS4 - time parameters | ||
| 12 | * | ||
| 13 | * This program is free software; you can redistribute it and/or modify | ||
| 14 | * it under the terms of the GNU General Public License version 2 as | ||
| 15 | * published by the Free Software Foundation. | ||
| 16 | */ | ||
| 17 | |||
| 18 | #ifndef __ASM_ARCH_TIMEX_H | ||
| 19 | #define __ASM_ARCH_TIMEX_H __FILE__ | ||
| 20 | |||
| 21 | /* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it | ||
| 22 | * a variable is useless. It seems as long as we make our timers an | ||
| 23 | * exact multiple of HZ, any value that makes a 1->1 correspondence | ||
| 24 | * for the time conversion functions to/from jiffies is acceptable. | ||
| 25 | */ | ||
| 26 | |||
| 27 | #define CLOCK_TICK_RATE 12000000 | ||
| 28 | |||
| 29 | #endif /* __ASM_ARCH_TIMEX_H */ | ||
diff --git a/arch/arm/mach-footbridge/include/mach/timex.h b/arch/arm/mach-footbridge/include/mach/timex.h deleted file mode 100644 index d0fea9d6d4ab..000000000000 --- a/arch/arm/mach-footbridge/include/mach/timex.h +++ /dev/null | |||
| @@ -1,18 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-footbridge/include/mach/timex.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1998 Russell King | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * EBSA285 architecture timex specifications | ||
| 11 | */ | ||
| 12 | |||
| 13 | /* | ||
| 14 | * We assume a constant here; this satisfies the maths in linux/timex.h | ||
| 15 | * and linux/time.h. CLOCK_TICK_RATE is actually system dependent, but | ||
| 16 | * this must be a constant. | ||
| 17 | */ | ||
| 18 | #define CLOCK_TICK_RATE (50000000/16) | ||
diff --git a/arch/arm/mach-gemini/include/mach/timex.h b/arch/arm/mach-gemini/include/mach/timex.h deleted file mode 100644 index dc5690ba975c..000000000000 --- a/arch/arm/mach-gemini/include/mach/timex.h +++ /dev/null | |||
| @@ -1,13 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Gemini timex specifications | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | /* When AHB bus frequency is 150MHz */ | ||
| 13 | #define CLOCK_TICK_RATE 38000000 | ||
diff --git a/arch/arm/mach-integrator/include/mach/timex.h b/arch/arm/mach-integrator/include/mach/timex.h deleted file mode 100644 index 1dcb42028c82..000000000000 --- a/arch/arm/mach-integrator/include/mach/timex.h +++ /dev/null | |||
| @@ -1,26 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-integrator/include/mach/timex.h | ||
| 3 | * | ||
| 4 | * Integrator architecture timex specifications | ||
| 5 | * | ||
| 6 | * Copyright (C) 1999 ARM Limited | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License | ||
| 19 | * along with this program; if not, write to the Free Software | ||
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 21 | */ | ||
| 22 | |||
| 23 | /* | ||
| 24 | * ?? | ||
| 25 | */ | ||
| 26 | #define CLOCK_TICK_RATE (50000000 / 16) | ||
diff --git a/arch/arm/mach-iop13xx/include/mach/timex.h b/arch/arm/mach-iop13xx/include/mach/timex.h deleted file mode 100644 index 45fb2745bb54..000000000000 --- a/arch/arm/mach-iop13xx/include/mach/timex.h +++ /dev/null | |||
| @@ -1 +0,0 @@ | |||
| 1 | #define CLOCK_TICK_RATE (100 * HZ) | ||
diff --git a/arch/arm/mach-iop32x/include/mach/timex.h b/arch/arm/mach-iop32x/include/mach/timex.h deleted file mode 100644 index 7262ab81419d..000000000000 --- a/arch/arm/mach-iop32x/include/mach/timex.h +++ /dev/null | |||
| @@ -1,6 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-iop32x/include/mach/timex.h | ||
| 3 | * | ||
| 4 | * IOP32x architecture timex specifications | ||
| 5 | */ | ||
| 6 | #define CLOCK_TICK_RATE (100 * HZ) | ||
diff --git a/arch/arm/mach-iop33x/include/mach/timex.h b/arch/arm/mach-iop33x/include/mach/timex.h deleted file mode 100644 index 54c589091d6e..000000000000 --- a/arch/arm/mach-iop33x/include/mach/timex.h +++ /dev/null | |||
| @@ -1,6 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-iop33x/include/mach/timex.h | ||
| 3 | * | ||
| 4 | * IOP3xx architecture timex specifications | ||
| 5 | */ | ||
| 6 | #define CLOCK_TICK_RATE (100 * HZ) | ||
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index 6d68aed6548a..dc5d7a0e5d9c 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c | |||
| @@ -23,7 +23,6 @@ | |||
| 23 | #include <linux/interrupt.h> | 23 | #include <linux/interrupt.h> |
| 24 | #include <linux/bitops.h> | 24 | #include <linux/bitops.h> |
| 25 | #include <linux/time.h> | 25 | #include <linux/time.h> |
| 26 | #include <linux/timex.h> | ||
| 27 | #include <linux/clocksource.h> | 26 | #include <linux/clocksource.h> |
| 28 | #include <linux/clockchips.h> | 27 | #include <linux/clockchips.h> |
| 29 | #include <linux/io.h> | 28 | #include <linux/io.h> |
| @@ -45,6 +44,17 @@ | |||
| 45 | #include <asm/mach/irq.h> | 44 | #include <asm/mach/irq.h> |
| 46 | #include <asm/mach/time.h> | 45 | #include <asm/mach/time.h> |
| 47 | 46 | ||
| 47 | #define IXP4XX_TIMER_FREQ 66666000 | ||
| 48 | |||
| 49 | /* | ||
| 50 | * The timer register doesn't allow to specify the two least significant bits of | ||
| 51 | * the timeout value and assumes them being zero. So make sure IXP4XX_LATCH is | ||
| 52 | * the best value with the two least significant bits unset. | ||
| 53 | */ | ||
| 54 | #define IXP4XX_LATCH DIV_ROUND_CLOSEST(IXP4XX_TIMER_FREQ, \ | ||
| 55 | (IXP4XX_OST_RELOAD_MASK + 1) * HZ) * \ | ||
| 56 | (IXP4XX_OST_RELOAD_MASK + 1) | ||
| 57 | |||
| 48 | static void __init ixp4xx_clocksource_init(void); | 58 | static void __init ixp4xx_clocksource_init(void); |
| 49 | static void __init ixp4xx_clockevent_init(void); | 59 | static void __init ixp4xx_clockevent_init(void); |
| 50 | static struct clock_event_device clockevent_ixp4xx; | 60 | static struct clock_event_device clockevent_ixp4xx; |
| @@ -520,7 +530,7 @@ static void ixp4xx_set_mode(enum clock_event_mode mode, | |||
| 520 | 530 | ||
| 521 | switch (mode) { | 531 | switch (mode) { |
| 522 | case CLOCK_EVT_MODE_PERIODIC: | 532 | case CLOCK_EVT_MODE_PERIODIC: |
| 523 | osrt = LATCH & ~IXP4XX_OST_RELOAD_MASK; | 533 | osrt = IXP4XX_LATCH & ~IXP4XX_OST_RELOAD_MASK; |
| 524 | opts = IXP4XX_OST_ENABLE; | 534 | opts = IXP4XX_OST_ENABLE; |
| 525 | break; | 535 | break; |
| 526 | case CLOCK_EVT_MODE_ONESHOT: | 536 | case CLOCK_EVT_MODE_ONESHOT: |
diff --git a/arch/arm/mach-ixp4xx/include/mach/timex.h b/arch/arm/mach-ixp4xx/include/mach/timex.h deleted file mode 100644 index 0396d89f947c..000000000000 --- a/arch/arm/mach-ixp4xx/include/mach/timex.h +++ /dev/null | |||
| @@ -1,16 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-ixp4xx/include/mach/timex.h | ||
| 3 | * | ||
| 4 | */ | ||
| 5 | |||
| 6 | #include <mach/ixp4xx-regs.h> | ||
| 7 | |||
| 8 | /* | ||
| 9 | * We use IXP425 General purpose timer for our timer needs, it runs at | ||
| 10 | * 66.66... MHz. We do a convulted calculation of CLOCK_TICK_RATE b/c the | ||
| 11 | * timer register ignores the bottom 2 bits of the LATCH value. | ||
| 12 | */ | ||
| 13 | #define IXP4XX_TIMER_FREQ 66666000 | ||
| 14 | #define CLOCK_TICK_RATE \ | ||
| 15 | (((IXP4XX_TIMER_FREQ / HZ & ~IXP4XX_OST_RELOAD_MASK) + 1) * HZ) | ||
| 16 | |||
diff --git a/arch/arm/mach-keystone/keystone.c b/arch/arm/mach-keystone/keystone.c index 6e6bb7d5ea30..aa0d2121449f 100644 --- a/arch/arm/mach-keystone/keystone.c +++ b/arch/arm/mach-keystone/keystone.c | |||
| @@ -47,6 +47,9 @@ static void __init keystone_init(void) | |||
| 47 | 47 | ||
| 48 | static const char *keystone_match[] __initconst = { | 48 | static const char *keystone_match[] __initconst = { |
| 49 | "ti,keystone-evm", | 49 | "ti,keystone-evm", |
| 50 | "ti,k2hk-evm", | ||
| 51 | "ti,k2l-evm", | ||
| 52 | "ti,k2e-evm", | ||
| 50 | NULL, | 53 | NULL, |
| 51 | }; | 54 | }; |
| 52 | 55 | ||
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index fe8319ad3158..df4b26340ae4 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig | |||
| @@ -106,13 +106,6 @@ config ARCH_KIRKWOOD_DT | |||
| 106 | Say 'Y' here if you want your kernel to support the | 106 | Say 'Y' here if you want your kernel to support the |
| 107 | Marvell Kirkwood using flattened device tree. | 107 | Marvell Kirkwood using flattened device tree. |
| 108 | 108 | ||
| 109 | config MACH_MV88F6281GTW_GE_DT | ||
| 110 | bool "Marvell 88F6281 GTW GE Board (Flattened Device Tree)" | ||
| 111 | depends on ARCH_KIRKWOOD_DT | ||
| 112 | help | ||
| 113 | Say 'Y' here if you want your kernel to support the | ||
| 114 | Marvell 88F6281 GTW GE Board (Flattened Device Tree). | ||
| 115 | |||
| 116 | endmenu | 109 | endmenu |
| 117 | 110 | ||
| 118 | endif | 111 | endif |
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index 144b51102939..3a72c5c6e747 100644 --- a/arch/arm/mach-kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile | |||
| @@ -1,5 +1,4 @@ | |||
| 1 | obj-y += common.o pcie.o | 1 | obj-$(CONFIG_KIRKWOOD_LEGACY) += irq.o mpp.o common.o pcie.o |
| 2 | obj-$(CONFIG_KIRKWOOD_LEGACY) += irq.o mpp.o | ||
| 3 | obj-$(CONFIG_PM) += pm.o | 2 | obj-$(CONFIG_PM) += pm.o |
| 4 | 3 | ||
| 5 | obj-$(CONFIG_MACH_D2NET_V2) += d2net_v2-setup.o lacie_v2-common.o | 4 | obj-$(CONFIG_MACH_D2NET_V2) += d2net_v2-setup.o lacie_v2-common.o |
| @@ -13,4 +12,3 @@ obj-$(CONFIG_MACH_TS219) += ts219-setup.o tsx1x-common.o | |||
| 13 | obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o | 12 | obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o |
| 14 | 13 | ||
| 15 | obj-$(CONFIG_ARCH_KIRKWOOD_DT) += board-dt.o | 14 | obj-$(CONFIG_ARCH_KIRKWOOD_DT) += board-dt.o |
| 16 | obj-$(CONFIG_MACH_MV88F6281GTW_GE_DT) += board-mv88f6281gtw_ge.o | ||
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c index 78188159484d..2801da49e2a3 100644 --- a/arch/arm/mach-kirkwood/board-dt.c +++ b/arch/arm/mach-kirkwood/board-dt.c | |||
| @@ -19,11 +19,84 @@ | |||
| 19 | #include <linux/of_platform.h> | 19 | #include <linux/of_platform.h> |
| 20 | #include <linux/dma-mapping.h> | 20 | #include <linux/dma-mapping.h> |
| 21 | #include <linux/irqchip.h> | 21 | #include <linux/irqchip.h> |
| 22 | #include <linux/kexec.h> | 22 | #include <asm/hardware/cache-feroceon-l2.h> |
| 23 | #include <asm/mach/arch.h> | 23 | #include <asm/mach/arch.h> |
| 24 | #include <asm/mach/map.h> | ||
| 24 | #include <mach/bridge-regs.h> | 25 | #include <mach/bridge-regs.h> |
| 25 | #include <plat/common.h> | 26 | #include <plat/common.h> |
| 26 | #include "common.h" | 27 | #include <plat/pcie.h> |
| 28 | #include "pm.h" | ||
| 29 | |||
| 30 | static struct map_desc kirkwood_io_desc[] __initdata = { | ||
| 31 | { | ||
| 32 | .virtual = (unsigned long) KIRKWOOD_REGS_VIRT_BASE, | ||
| 33 | .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE), | ||
| 34 | .length = KIRKWOOD_REGS_SIZE, | ||
| 35 | .type = MT_DEVICE, | ||
| 36 | }, | ||
| 37 | }; | ||
| 38 | |||
| 39 | static void __init kirkwood_map_io(void) | ||
| 40 | { | ||
| 41 | iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc)); | ||
| 42 | } | ||
| 43 | |||
| 44 | static struct resource kirkwood_cpufreq_resources[] = { | ||
| 45 | [0] = { | ||
| 46 | .start = CPU_CONTROL_PHYS, | ||
| 47 | .end = CPU_CONTROL_PHYS + 3, | ||
| 48 | .flags = IORESOURCE_MEM, | ||
| 49 | }, | ||
| 50 | }; | ||
| 51 | |||
| 52 | static struct platform_device kirkwood_cpufreq_device = { | ||
| 53 | .name = "kirkwood-cpufreq", | ||
| 54 | .id = -1, | ||
| 55 | .num_resources = ARRAY_SIZE(kirkwood_cpufreq_resources), | ||
| 56 | .resource = kirkwood_cpufreq_resources, | ||
| 57 | }; | ||
| 58 | |||
| 59 | static void __init kirkwood_cpufreq_init(void) | ||
| 60 | { | ||
| 61 | platform_device_register(&kirkwood_cpufreq_device); | ||
| 62 | } | ||
| 63 | |||
| 64 | static struct resource kirkwood_cpuidle_resource[] = { | ||
| 65 | { | ||
| 66 | .flags = IORESOURCE_MEM, | ||
| 67 | .start = DDR_OPERATION_BASE, | ||
| 68 | .end = DDR_OPERATION_BASE + 3, | ||
| 69 | }, | ||
| 70 | }; | ||
| 71 | |||
| 72 | static struct platform_device kirkwood_cpuidle = { | ||
| 73 | .name = "kirkwood_cpuidle", | ||
| 74 | .id = -1, | ||
| 75 | .resource = kirkwood_cpuidle_resource, | ||
| 76 | .num_resources = 1, | ||
| 77 | }; | ||
| 78 | |||
| 79 | static void __init kirkwood_cpuidle_init(void) | ||
| 80 | { | ||
| 81 | platform_device_register(&kirkwood_cpuidle); | ||
| 82 | } | ||
| 83 | |||
| 84 | /* Temporary here since mach-mvebu has a function we can use */ | ||
| 85 | static void kirkwood_restart(enum reboot_mode mode, const char *cmd) | ||
| 86 | { | ||
| 87 | /* | ||
| 88 | * Enable soft reset to assert RSTOUTn. | ||
| 89 | */ | ||
| 90 | writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); | ||
| 91 | |||
| 92 | /* | ||
| 93 | * Assert soft reset. | ||
| 94 | */ | ||
| 95 | writel(SOFT_RESET, SYSTEM_SOFT_RESET); | ||
| 96 | |||
| 97 | while (1) | ||
| 98 | ; | ||
| 99 | } | ||
| 27 | 100 | ||
| 28 | #define MV643XX_ETH_MAC_ADDR_LOW 0x0414 | 101 | #define MV643XX_ETH_MAC_ADDR_LOW 0x0414 |
| 29 | #define MV643XX_ETH_MAC_ADDR_HIGH 0x0418 | 102 | #define MV643XX_ETH_MAC_ADDR_HIGH 0x0418 |
| @@ -104,35 +177,35 @@ eth_fixup_skip: | |||
| 104 | } | 177 | } |
| 105 | } | 178 | } |
| 106 | 179 | ||
| 107 | static void __init kirkwood_dt_init(void) | 180 | /* |
| 181 | * Disable propagation of mbus errors to the CPU local bus, as this | ||
| 182 | * causes mbus errors (which can occur for example for PCI aborts) to | ||
| 183 | * throw CPU aborts, which we're not set up to deal with. | ||
| 184 | */ | ||
| 185 | static void __init kirkwood_disable_mbus_error_propagation(void) | ||
| 108 | { | 186 | { |
| 109 | pr_info("Kirkwood: %s.\n", kirkwood_id()); | 187 | void __iomem *cpu_config; |
| 110 | 188 | ||
| 111 | /* | 189 | cpu_config = ioremap(CPU_CONFIG_PHYS, 4); |
| 112 | * Disable propagation of mbus errors to the CPU local bus, | 190 | writel(readl(cpu_config) & ~CPU_CONFIG_ERROR_PROP, cpu_config); |
| 113 | * as this causes mbus errors (which can occur for example | 191 | iounmap(cpu_config); |
| 114 | * for PCI aborts) to throw CPU aborts, which we're not set | 192 | } |
| 115 | * up to deal with. | ||
| 116 | */ | ||
| 117 | writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG); | ||
| 118 | 193 | ||
| 119 | BUG_ON(mvebu_mbus_dt_init()); | 194 | static void __init kirkwood_dt_init(void) |
| 195 | { | ||
| 196 | kirkwood_disable_mbus_error_propagation(); | ||
| 120 | 197 | ||
| 121 | kirkwood_l2_init(); | 198 | BUG_ON(mvebu_mbus_dt_init()); |
| 122 | 199 | ||
| 200 | #ifdef CONFIG_CACHE_FEROCEON_L2 | ||
| 201 | feroceon_of_init(); | ||
| 202 | #endif | ||
| 123 | kirkwood_cpufreq_init(); | 203 | kirkwood_cpufreq_init(); |
| 124 | kirkwood_cpuidle_init(); | 204 | kirkwood_cpuidle_init(); |
| 125 | 205 | ||
| 126 | kirkwood_pm_init(); | 206 | kirkwood_pm_init(); |
| 127 | kirkwood_dt_eth_fixup(); | 207 | kirkwood_dt_eth_fixup(); |
| 128 | 208 | ||
| 129 | #ifdef CONFIG_KEXEC | ||
| 130 | kexec_reinit = kirkwood_enable_pcie; | ||
| 131 | #endif | ||
| 132 | |||
| 133 | if (of_machine_is_compatible("marvell,mv88f6281gtw-ge")) | ||
| 134 | mv88f6281gtw_ge_init(); | ||
| 135 | |||
| 136 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | 209 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
| 137 | } | 210 | } |
| 138 | 211 | ||
diff --git a/arch/arm/mach-kirkwood/board-mv88f6281gtw_ge.c b/arch/arm/mach-kirkwood/board-mv88f6281gtw_ge.c deleted file mode 100644 index ee5eea678c11..000000000000 --- a/arch/arm/mach-kirkwood/board-mv88f6281gtw_ge.c +++ /dev/null | |||
| @@ -1,50 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-kirkwood/board-mv88f6281gtw_ge.c | ||
| 3 | * | ||
| 4 | * Marvell 88F6281 GTW GE Board Setup | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/init.h> | ||
| 13 | #include <linux/platform_device.h> | ||
| 14 | #include <linux/irq.h> | ||
| 15 | #include <linux/timer.h> | ||
| 16 | #include <linux/mv643xx_eth.h> | ||
| 17 | #include <linux/ethtool.h> | ||
| 18 | #include <linux/gpio.h> | ||
| 19 | #include <net/dsa.h> | ||
| 20 | #include <asm/mach-types.h> | ||
| 21 | #include <asm/mach/arch.h> | ||
| 22 | #include <asm/mach/pci.h> | ||
| 23 | #include <mach/kirkwood.h> | ||
| 24 | #include "common.h" | ||
| 25 | |||
| 26 | static struct mv643xx_eth_platform_data mv88f6281gtw_ge_ge00_data = { | ||
| 27 | .phy_addr = MV643XX_ETH_PHY_NONE, | ||
| 28 | .speed = SPEED_1000, | ||
| 29 | .duplex = DUPLEX_FULL, | ||
| 30 | }; | ||
| 31 | |||
| 32 | static struct dsa_chip_data mv88f6281gtw_ge_switch_chip_data = { | ||
| 33 | .port_names[0] = "lan1", | ||
| 34 | .port_names[1] = "lan2", | ||
| 35 | .port_names[2] = "lan3", | ||
| 36 | .port_names[3] = "lan4", | ||
| 37 | .port_names[4] = "wan", | ||
| 38 | .port_names[5] = "cpu", | ||
| 39 | }; | ||
| 40 | |||
| 41 | static struct dsa_platform_data mv88f6281gtw_ge_switch_plat_data = { | ||
| 42 | .nr_chips = 1, | ||
| 43 | .chip = &mv88f6281gtw_ge_switch_chip_data, | ||
| 44 | }; | ||
| 45 | |||
| 46 | void __init mv88f6281gtw_ge_init(void) | ||
| 47 | { | ||
| 48 | kirkwood_ge00_init(&mv88f6281gtw_ge_ge00_data); | ||
| 49 | kirkwood_ge00_switch_init(&mv88f6281gtw_ge_switch_plat_data, NO_IRQ); | ||
| 50 | } | ||
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index f3407a5db216..255f33a3903c 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c | |||
| @@ -25,10 +25,10 @@ | |||
| 25 | #include <asm/page.h> | 25 | #include <asm/page.h> |
| 26 | #include <asm/mach/map.h> | 26 | #include <asm/mach/map.h> |
| 27 | #include <asm/mach/time.h> | 27 | #include <asm/mach/time.h> |
| 28 | #include <asm/hardware/cache-feroceon-l2.h> | ||
| 28 | #include <mach/kirkwood.h> | 29 | #include <mach/kirkwood.h> |
| 29 | #include <mach/bridge-regs.h> | 30 | #include <mach/bridge-regs.h> |
| 30 | #include <linux/platform_data/asoc-kirkwood.h> | 31 | #include <linux/platform_data/asoc-kirkwood.h> |
| 31 | #include <plat/cache-feroceon-l2.h> | ||
| 32 | #include <linux/platform_data/mmc-mvsdio.h> | 32 | #include <linux/platform_data/mmc-mvsdio.h> |
| 33 | #include <linux/platform_data/mtd-orion_nand.h> | 33 | #include <linux/platform_data/mtd-orion_nand.h> |
| 34 | #include <linux/platform_data/usb-ehci-orion.h> | 34 | #include <linux/platform_data/usb-ehci-orion.h> |
| @@ -36,6 +36,7 @@ | |||
| 36 | #include <plat/time.h> | 36 | #include <plat/time.h> |
| 37 | #include <linux/platform_data/dma-mv_xor.h> | 37 | #include <linux/platform_data/dma-mv_xor.h> |
| 38 | #include "common.h" | 38 | #include "common.h" |
| 39 | #include "pm.h" | ||
| 39 | 40 | ||
| 40 | /* These can go away once Kirkwood uses the mvebu-mbus DT binding */ | 41 | /* These can go away once Kirkwood uses the mvebu-mbus DT binding */ |
| 41 | #define KIRKWOOD_MBUS_NAND_TARGET 0x01 | 42 | #define KIRKWOOD_MBUS_NAND_TARGET 0x01 |
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h index 05fd648df543..832a4e2ab8d7 100644 --- a/arch/arm/mach-kirkwood/common.h +++ b/arch/arm/mach-kirkwood/common.h | |||
| @@ -58,19 +58,6 @@ void kirkwood_cpufreq_init(void); | |||
| 58 | void kirkwood_restart(enum reboot_mode, const char *); | 58 | void kirkwood_restart(enum reboot_mode, const char *); |
| 59 | void kirkwood_clk_init(void); | 59 | void kirkwood_clk_init(void); |
| 60 | 60 | ||
| 61 | #ifdef CONFIG_PM | ||
| 62 | void kirkwood_pm_init(void); | ||
| 63 | #else | ||
| 64 | static inline void kirkwood_pm_init(void) {}; | ||
| 65 | #endif | ||
| 66 | |||
| 67 | /* board init functions for boards not fully converted to fdt */ | ||
| 68 | #ifdef CONFIG_MACH_MV88F6281GTW_GE_DT | ||
| 69 | void mv88f6281gtw_ge_init(void); | ||
| 70 | #else | ||
| 71 | static inline void mv88f6281gtw_ge_init(void) {}; | ||
| 72 | #endif | ||
| 73 | |||
| 74 | /* early init functions not converted to fdt yet */ | 61 | /* early init functions not converted to fdt yet */ |
| 75 | char *kirkwood_id(void); | 62 | char *kirkwood_id(void); |
| 76 | void kirkwood_l2_init(void); | 63 | void kirkwood_l2_init(void); |
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h index 8b9d1c9ff199..6e5077e2ec26 100644 --- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h +++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h | |||
| @@ -14,6 +14,7 @@ | |||
| 14 | #include <mach/kirkwood.h> | 14 | #include <mach/kirkwood.h> |
| 15 | 15 | ||
| 16 | #define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0100) | 16 | #define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0100) |
| 17 | #define CPU_CONFIG_PHYS (BRIDGE_PHYS_BASE + 0x0100) | ||
| 17 | #define CPU_CONFIG_ERROR_PROP 0x00000004 | 18 | #define CPU_CONFIG_ERROR_PROP 0x00000004 |
| 18 | 19 | ||
| 19 | #define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) | 20 | #define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) |
| @@ -79,5 +80,6 @@ | |||
| 79 | #define CGC_RESERVED (0x6 << 21) | 80 | #define CGC_RESERVED (0x6 << 21) |
| 80 | 81 | ||
| 81 | #define MEMORY_PM_CTRL (BRIDGE_VIRT_BASE + 0x118) | 82 | #define MEMORY_PM_CTRL (BRIDGE_VIRT_BASE + 0x118) |
| 83 | #define MEMORY_PM_CTRL_PHYS (BRIDGE_PHYS_BASE + 0x118) | ||
| 82 | 84 | ||
| 83 | #endif | 85 | #endif |
diff --git a/arch/arm/mach-kirkwood/include/mach/timex.h b/arch/arm/mach-kirkwood/include/mach/timex.h deleted file mode 100644 index c923cd169b9c..000000000000 --- a/arch/arm/mach-kirkwood/include/mach/timex.h +++ /dev/null | |||
| @@ -1,10 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-kirkwood/include/mach/timex.h | ||
| 3 | * | ||
| 4 | * This file is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2. This program is licensed "as is" without any | ||
| 6 | * warranty of any kind, whether express or implied. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #define CLOCK_TICK_RATE (100 * HZ) | ||
| 10 | |||
diff --git a/arch/arm/mach-kirkwood/pm.c b/arch/arm/mach-kirkwood/pm.c index c6ab8d9303a5..8e5e0329d04c 100644 --- a/arch/arm/mach-kirkwood/pm.c +++ b/arch/arm/mach-kirkwood/pm.c | |||
| @@ -21,15 +21,16 @@ | |||
| 21 | #include "common.h" | 21 | #include "common.h" |
| 22 | 22 | ||
| 23 | static void __iomem *ddr_operation_base; | 23 | static void __iomem *ddr_operation_base; |
| 24 | static void __iomem *memory_pm_ctrl; | ||
| 24 | 25 | ||
| 25 | static void kirkwood_low_power(void) | 26 | static void kirkwood_low_power(void) |
| 26 | { | 27 | { |
| 27 | u32 mem_pm_ctrl; | 28 | u32 mem_pm_ctrl; |
| 28 | 29 | ||
| 29 | mem_pm_ctrl = readl(MEMORY_PM_CTRL); | 30 | mem_pm_ctrl = readl(memory_pm_ctrl); |
| 30 | 31 | ||
| 31 | /* Set peripherals to low-power mode */ | 32 | /* Set peripherals to low-power mode */ |
| 32 | writel_relaxed(~0, MEMORY_PM_CTRL); | 33 | writel_relaxed(~0, memory_pm_ctrl); |
| 33 | 34 | ||
| 34 | /* Set DDR in self-refresh */ | 35 | /* Set DDR in self-refresh */ |
| 35 | writel_relaxed(0x7, ddr_operation_base); | 36 | writel_relaxed(0x7, ddr_operation_base); |
| @@ -41,7 +42,7 @@ static void kirkwood_low_power(void) | |||
| 41 | */ | 42 | */ |
| 42 | cpu_do_idle(); | 43 | cpu_do_idle(); |
| 43 | 44 | ||
| 44 | writel_relaxed(mem_pm_ctrl, MEMORY_PM_CTRL); | 45 | writel_relaxed(mem_pm_ctrl, memory_pm_ctrl); |
| 45 | } | 46 | } |
| 46 | 47 | ||
| 47 | static int kirkwood_suspend_enter(suspend_state_t state) | 48 | static int kirkwood_suspend_enter(suspend_state_t state) |
| @@ -69,5 +70,7 @@ static const struct platform_suspend_ops kirkwood_suspend_ops = { | |||
| 69 | void __init kirkwood_pm_init(void) | 70 | void __init kirkwood_pm_init(void) |
| 70 | { | 71 | { |
| 71 | ddr_operation_base = ioremap(DDR_OPERATION_BASE, 4); | 72 | ddr_operation_base = ioremap(DDR_OPERATION_BASE, 4); |
| 73 | memory_pm_ctrl = ioremap(MEMORY_PM_CTRL_PHYS, 4); | ||
| 74 | |||
| 72 | suspend_set_ops(&kirkwood_suspend_ops); | 75 | suspend_set_ops(&kirkwood_suspend_ops); |
| 73 | } | 76 | } |
diff --git a/arch/arm/mach-kirkwood/pm.h b/arch/arm/mach-kirkwood/pm.h new file mode 100644 index 000000000000..21e7530f368b --- /dev/null +++ b/arch/arm/mach-kirkwood/pm.h | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | /* | ||
| 2 | * Power Management driver for Marvell Kirkwood SoCs | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Ezequiel Garcia <ezequiel@free-electrons.com> | ||
| 5 | * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License, | ||
| 9 | * version 2 of the License. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef __ARCH_KIRKWOOD_PM_H | ||
| 18 | #define __ARCH_KIRKWOOD_PM_H | ||
| 19 | |||
| 20 | #ifdef CONFIG_PM | ||
| 21 | void kirkwood_pm_init(void); | ||
| 22 | #else | ||
| 23 | static inline void kirkwood_pm_init(void) {}; | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #endif | ||
diff --git a/arch/arm/mach-ks8695/include/mach/timex.h b/arch/arm/mach-ks8695/include/mach/timex.h deleted file mode 100644 index 10f716371bd3..000000000000 --- a/arch/arm/mach-ks8695/include/mach/timex.h +++ /dev/null | |||
| @@ -1,21 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-ks8695/include/mach/timex.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Simtec Electronics | ||
| 5 | * Ben Dooks <ben@simtec.co.uk> | ||
| 6 | * | ||
| 7 | * KS8695 - Time Parameters | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_TIMEX_H | ||
| 15 | #define __ASM_ARCH_TIMEX_H | ||
| 16 | |||
| 17 | #include <mach/hardware.h> | ||
| 18 | |||
| 19 | #define CLOCK_TICK_RATE KS8695_CLOCK_RATE | ||
| 20 | |||
| 21 | #endif | ||
diff --git a/arch/arm/mach-lpc32xx/include/mach/timex.h b/arch/arm/mach-lpc32xx/include/mach/timex.h deleted file mode 100644 index 8d4066b16b3f..000000000000 --- a/arch/arm/mach-lpc32xx/include/mach/timex.h +++ /dev/null | |||
| @@ -1,28 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-lpc32xx/include/mach/timex.h | ||
| 3 | * | ||
| 4 | * Author: Kevin Wells <kevin.wells@nxp.com> | ||
| 5 | * | ||
| 6 | * Copyright (C) 2010 NXP Semiconductors | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef __ASM_ARCH_TIMEX_H | ||
| 20 | #define __ASM_ARCH_TIMEX_H | ||
| 21 | |||
| 22 | /* | ||
| 23 | * Rate in Hz of the main system oscillator. This value should match | ||
| 24 | * the value 'MAIN_OSC_FREQ' in platform.h | ||
| 25 | */ | ||
| 26 | #define CLOCK_TICK_RATE 13000000 | ||
| 27 | |||
| 28 | #endif | ||
diff --git a/arch/arm/mach-mmp/include/mach/timex.h b/arch/arm/mach-mmp/include/mach/timex.h deleted file mode 100644 index 70c9f1d88c02..000000000000 --- a/arch/arm/mach-mmp/include/mach/timex.h +++ /dev/null | |||
| @@ -1,13 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/include/mach/timex.h | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifdef CONFIG_CPU_MMP2 | ||
| 10 | #define CLOCK_TICK_RATE 6500000 | ||
| 11 | #else | ||
| 12 | #define CLOCK_TICK_RATE 3250000 | ||
| 13 | #endif | ||
diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c index 024022d91fe3..048997e75dd0 100644 --- a/arch/arm/mach-mmp/time.c +++ b/arch/arm/mach-mmp/time.c | |||
| @@ -39,6 +39,12 @@ | |||
| 39 | 39 | ||
| 40 | #include "clock.h" | 40 | #include "clock.h" |
| 41 | 41 | ||
| 42 | #ifdef CONFIG_CPU_MMP2 | ||
| 43 | #define MMP_CLOCK_FREQ 6500000 | ||
| 44 | #else | ||
| 45 | #define MMP_CLOCK_FREQ 3250000 | ||
| 46 | #endif | ||
| 47 | |||
| 42 | #define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE | 48 | #define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE |
| 43 | 49 | ||
| 44 | #define MAX_DELTA (0xfffffffe) | 50 | #define MAX_DELTA (0xfffffffe) |
| @@ -195,14 +201,14 @@ void __init timer_init(int irq) | |||
| 195 | { | 201 | { |
| 196 | timer_config(); | 202 | timer_config(); |
| 197 | 203 | ||
| 198 | sched_clock_register(mmp_read_sched_clock, 32, CLOCK_TICK_RATE); | 204 | sched_clock_register(mmp_read_sched_clock, 32, MMP_CLOCK_FREQ); |
| 199 | 205 | ||
| 200 | ckevt.cpumask = cpumask_of(0); | 206 | ckevt.cpumask = cpumask_of(0); |
| 201 | 207 | ||
| 202 | setup_irq(irq, &timer_irq); | 208 | setup_irq(irq, &timer_irq); |
| 203 | 209 | ||
| 204 | clocksource_register_hz(&cksrc, CLOCK_TICK_RATE); | 210 | clocksource_register_hz(&cksrc, MMP_CLOCK_FREQ); |
| 205 | clockevents_config_and_register(&ckevt, CLOCK_TICK_RATE, | 211 | clockevents_config_and_register(&ckevt, MMP_CLOCK_FREQ, |
| 206 | MIN_DELTA, MAX_DELTA); | 212 | MIN_DELTA, MAX_DELTA); |
| 207 | } | 213 | } |
| 208 | 214 | ||
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index 9625cf378931..a7f959e58c3d 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig | |||
| @@ -1,50 +1,9 @@ | |||
| 1 | config ARCH_MSM | ||
| 2 | bool | ||
| 3 | |||
| 4 | config ARCH_MSM_DT | ||
| 5 | bool "Qualcomm MSM DT Support" if ARCH_MULTI_V7 | ||
| 6 | select ARCH_MSM | ||
| 7 | select ARCH_REQUIRE_GPIOLIB | ||
| 8 | select CLKSRC_OF | ||
| 9 | select GENERIC_CLOCKEVENTS | ||
| 10 | help | ||
| 11 | Support for Qualcomm's devicetree based MSM systems. | ||
| 12 | |||
| 13 | if ARCH_MSM | 1 | if ARCH_MSM |
| 14 | 2 | ||
| 15 | menu "Qualcomm MSM SoC Selection" | ||
| 16 | depends on ARCH_MSM_DT | ||
| 17 | |||
| 18 | config ARCH_MSM8X60 | ||
| 19 | bool "Enable support for MSM8X60" | ||
| 20 | select ARM_GIC | ||
| 21 | select CPU_V7 | ||
| 22 | select HAVE_SMP | ||
| 23 | select MSM_SCM if SMP | ||
| 24 | select MSM_TIMER | ||
| 25 | |||
| 26 | config ARCH_MSM8960 | ||
| 27 | bool "Enable support for MSM8960" | ||
| 28 | select ARM_GIC | ||
| 29 | select CPU_V7 | ||
| 30 | select HAVE_SMP | ||
| 31 | select MSM_SCM if SMP | ||
| 32 | select MSM_TIMER | ||
| 33 | |||
| 34 | config ARCH_MSM8974 | ||
| 35 | bool "Enable support for MSM8974" | ||
| 36 | select ARM_GIC | ||
| 37 | select CPU_V7 | ||
| 38 | select HAVE_ARM_ARCH_TIMER | ||
| 39 | select HAVE_SMP | ||
| 40 | select MSM_SCM if SMP | ||
| 41 | |||
| 42 | endmenu | ||
| 43 | |||
| 44 | choice | 3 | choice |
| 45 | prompt "Qualcomm MSM SoC Type" | 4 | prompt "Qualcomm MSM SoC Type" |
| 46 | default ARCH_MSM7X00A | 5 | default ARCH_MSM7X00A |
| 47 | depends on ARCH_MSM_NODT | 6 | depends on ARCH_MSM |
| 48 | 7 | ||
| 49 | config ARCH_MSM7X00A | 8 | config ARCH_MSM7X00A |
| 50 | bool "MSM7x00A / MSM7x01A" | 9 | bool "MSM7x00A / MSM7x01A" |
| @@ -54,7 +13,7 @@ config ARCH_MSM7X00A | |||
| 54 | select MACH_TROUT if !MACH_HALIBUT | 13 | select MACH_TROUT if !MACH_HALIBUT |
| 55 | select MSM_PROC_COMM | 14 | select MSM_PROC_COMM |
| 56 | select MSM_SMD | 15 | select MSM_SMD |
| 57 | select MSM_TIMER | 16 | select CLKSRC_QCOM |
| 58 | select MSM_SMD_PKG3 | 17 | select MSM_SMD_PKG3 |
| 59 | 18 | ||
| 60 | config ARCH_MSM7X30 | 19 | config ARCH_MSM7X30 |
| @@ -66,7 +25,7 @@ config ARCH_MSM7X30 | |||
| 66 | select MSM_GPIOMUX | 25 | select MSM_GPIOMUX |
| 67 | select MSM_PROC_COMM | 26 | select MSM_PROC_COMM |
| 68 | select MSM_SMD | 27 | select MSM_SMD |
| 69 | select MSM_TIMER | 28 | select CLKSRC_QCOM |
| 70 | select MSM_VIC | 29 | select MSM_VIC |
| 71 | 30 | ||
| 72 | config ARCH_QSD8X50 | 31 | config ARCH_QSD8X50 |
| @@ -78,7 +37,7 @@ config ARCH_QSD8X50 | |||
| 78 | select MSM_GPIOMUX | 37 | select MSM_GPIOMUX |
| 79 | select MSM_PROC_COMM | 38 | select MSM_PROC_COMM |
| 80 | select MSM_SMD | 39 | select MSM_SMD |
| 81 | select MSM_TIMER | 40 | select CLKSRC_QCOM |
| 82 | select MSM_VIC | 41 | select MSM_VIC |
| 83 | 42 | ||
| 84 | endchoice | 43 | endchoice |
| @@ -99,7 +58,7 @@ config MSM_VIC | |||
| 99 | bool | 58 | bool |
| 100 | 59 | ||
| 101 | menu "Qualcomm MSM Board Type" | 60 | menu "Qualcomm MSM Board Type" |
| 102 | depends on ARCH_MSM_NODT | 61 | depends on ARCH_MSM |
| 103 | 62 | ||
| 104 | config MACH_HALIBUT | 63 | config MACH_HALIBUT |
| 105 | depends on ARCH_MSM | 64 | depends on ARCH_MSM |
| @@ -153,7 +112,4 @@ config MSM_GPIOMUX | |||
| 153 | config MSM_SCM | 112 | config MSM_SCM |
| 154 | bool | 113 | bool |
| 155 | 114 | ||
| 156 | config MSM_TIMER | ||
| 157 | bool | ||
| 158 | |||
| 159 | endif | 115 | endif |
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index 8e307a10d3c3..27c078a568df 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile | |||
| @@ -1,4 +1,3 @@ | |||
| 1 | obj-$(CONFIG_MSM_TIMER) += timer.o | ||
| 2 | obj-$(CONFIG_MSM_PROC_COMM) += clock.o | 1 | obj-$(CONFIG_MSM_PROC_COMM) += clock.o |
| 3 | 2 | ||
| 4 | obj-$(CONFIG_MSM_VIC) += irq-vic.o | 3 | obj-$(CONFIG_MSM_VIC) += irq-vic.o |
| @@ -14,18 +13,11 @@ obj-$(CONFIG_ARCH_QSD8X50) += dma.o io.o | |||
| 14 | 13 | ||
| 15 | obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o | 14 | obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o |
| 16 | obj-$(CONFIG_MSM_SMD) += last_radio_log.o | 15 | obj-$(CONFIG_MSM_SMD) += last_radio_log.o |
| 17 | obj-$(CONFIG_MSM_SCM) += scm.o scm-boot.o | ||
| 18 | |||
| 19 | CFLAGS_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1) | ||
| 20 | |||
| 21 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o | ||
| 22 | obj-$(CONFIG_SMP) += headsmp.o platsmp.o | ||
| 23 | 16 | ||
| 24 | obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o devices-msm7x00.o | 17 | obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o devices-msm7x00.o |
| 25 | obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o board-trout-panel.o devices-msm7x00.o | 18 | obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o board-trout-panel.o devices-msm7x00.o |
| 26 | obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o | 19 | obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o |
| 27 | obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o | 20 | obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o |
| 28 | obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o | 21 | obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o |
| 29 | obj-$(CONFIG_ARCH_MSM_DT) += board-dt.o | ||
| 30 | obj-$(CONFIG_MSM_GPIOMUX) += gpiomux.o | 22 | obj-$(CONFIG_MSM_GPIOMUX) += gpiomux.o |
| 31 | obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o | 23 | obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o |
diff --git a/arch/arm/mach-msm/common.h b/arch/arm/mach-msm/common.h index 33c7725adae2..0a4899b7d85c 100644 --- a/arch/arm/mach-msm/common.h +++ b/arch/arm/mach-msm/common.h | |||
| @@ -24,7 +24,6 @@ extern void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size, | |||
| 24 | unsigned int mtype, void *caller); | 24 | unsigned int mtype, void *caller); |
| 25 | 25 | ||
| 26 | extern struct smp_operations msm_smp_ops; | 26 | extern struct smp_operations msm_smp_ops; |
| 27 | extern void msm_cpu_die(unsigned int cpu); | ||
| 28 | 27 | ||
| 29 | struct msm_mmc_platform_data; | 28 | struct msm_mmc_platform_data; |
| 30 | 29 | ||
diff --git a/arch/arm/mach-msm/headsmp.S b/arch/arm/mach-msm/headsmp.S deleted file mode 100644 index 6c62c3f82fe6..000000000000 --- a/arch/arm/mach-msm/headsmp.S +++ /dev/null | |||
| @@ -1,39 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-realview/headsmp.S | ||
| 3 | * | ||
| 4 | * Copyright (c) 2003 ARM Limited | ||
| 5 | * All Rights Reserved | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #include <linux/linkage.h> | ||
| 12 | #include <linux/init.h> | ||
| 13 | |||
| 14 | /* | ||
| 15 | * MSM specific entry point for secondary CPUs. This provides | ||
| 16 | * a "holding pen" into which all secondary cores are held until we're | ||
| 17 | * ready for them to initialise. | ||
| 18 | */ | ||
| 19 | ENTRY(msm_secondary_startup) | ||
| 20 | mrc p15, 0, r0, c0, c0, 5 | ||
| 21 | and r0, r0, #15 | ||
| 22 | adr r4, 1f | ||
| 23 | ldmia r4, {r5, r6} | ||
| 24 | sub r4, r4, r5 | ||
| 25 | add r6, r6, r4 | ||
| 26 | pen: ldr r7, [r6] | ||
| 27 | cmp r7, r0 | ||
| 28 | bne pen | ||
| 29 | |||
| 30 | /* | ||
| 31 | * we've been released from the holding pen: secondary_stack | ||
| 32 | * should now contain the SVC stack for this core | ||
| 33 | */ | ||
| 34 | b secondary_startup | ||
| 35 | ENDPROC(msm_secondary_startup) | ||
| 36 | |||
| 37 | .align | ||
| 38 | 1: .long . | ||
| 39 | .long pen_release | ||
diff --git a/arch/arm/mach-msm/hotplug.c b/arch/arm/mach-msm/hotplug.c deleted file mode 100644 index 326a87261f9a..000000000000 --- a/arch/arm/mach-msm/hotplug.c +++ /dev/null | |||
| @@ -1,74 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2002 ARM Ltd. | ||
| 3 | * All Rights Reserved | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License version 2 as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include <linux/kernel.h> | ||
| 10 | #include <linux/errno.h> | ||
| 11 | #include <linux/smp.h> | ||
| 12 | |||
| 13 | #include <asm/smp_plat.h> | ||
| 14 | |||
| 15 | #include "common.h" | ||
| 16 | |||
| 17 | static inline void cpu_enter_lowpower(void) | ||
| 18 | { | ||
| 19 | } | ||
| 20 | |||
| 21 | static inline void cpu_leave_lowpower(void) | ||
| 22 | { | ||
| 23 | } | ||
| 24 | |||
| 25 | static inline void platform_do_lowpower(unsigned int cpu) | ||
| 26 | { | ||
| 27 | /* Just enter wfi for now. TODO: Properly shut off the cpu. */ | ||
| 28 | for (;;) { | ||
| 29 | /* | ||
| 30 | * here's the WFI | ||
| 31 | */ | ||
| 32 | asm("wfi" | ||
| 33 | : | ||
| 34 | : | ||
| 35 | : "memory", "cc"); | ||
| 36 | |||
| 37 | if (pen_release == cpu_logical_map(cpu)) { | ||
| 38 | /* | ||
| 39 | * OK, proper wakeup, we're done | ||
| 40 | */ | ||
| 41 | break; | ||
| 42 | } | ||
| 43 | |||
| 44 | /* | ||
| 45 | * getting here, means that we have come out of WFI without | ||
| 46 | * having been woken up - this shouldn't happen | ||
| 47 | * | ||
| 48 | * The trouble is, letting people know about this is not really | ||
| 49 | * possible, since we are currently running incoherently, and | ||
| 50 | * therefore cannot safely call printk() or anything else | ||
| 51 | */ | ||
| 52 | pr_debug("CPU%u: spurious wakeup call\n", cpu); | ||
| 53 | } | ||
| 54 | } | ||
| 55 | |||
| 56 | /* | ||
| 57 | * platform-specific code to shutdown a CPU | ||
| 58 | * | ||
| 59 | * Called with IRQs disabled | ||
| 60 | */ | ||
| 61 | void __ref msm_cpu_die(unsigned int cpu) | ||
| 62 | { | ||
| 63 | /* | ||
| 64 | * we're ready for shutdown now, so do it | ||
| 65 | */ | ||
| 66 | cpu_enter_lowpower(); | ||
| 67 | platform_do_lowpower(cpu); | ||
| 68 | |||
| 69 | /* | ||
| 70 | * bring this CPU back into the world of cache | ||
| 71 | * coherency, and then restore interrupts | ||
| 72 | */ | ||
| 73 | cpu_leave_lowpower(); | ||
| 74 | } | ||
diff --git a/arch/arm/mach-msm/include/mach/timex.h b/arch/arm/mach-msm/include/mach/timex.h deleted file mode 100644 index a62e6b215aec..000000000000 --- a/arch/arm/mach-msm/include/mach/timex.h +++ /dev/null | |||
| @@ -1,21 +0,0 @@ | |||
| 1 | /* arch/arm/mach-msm/include/mach/timex.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Google, Inc. | ||
| 4 | * | ||
| 5 | * This software is licensed under the terms of the GNU General Public | ||
| 6 | * License version 2, as published by the Free Software Foundation, and | ||
| 7 | * may be copied, distributed, and modified under those terms. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef __ASM_ARCH_MSM_TIMEX_H | ||
| 17 | #define __ASM_ARCH_MSM_TIMEX_H | ||
| 18 | |||
| 19 | #define CLOCK_TICK_RATE 1000000 | ||
| 20 | |||
| 21 | #endif | ||
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index 75062eff2494..e6ac679bece9 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c | |||
| @@ -15,11 +15,11 @@ | |||
| 15 | #include <linux/ata_platform.h> | 15 | #include <linux/ata_platform.h> |
| 16 | #include <linux/clk-provider.h> | 16 | #include <linux/clk-provider.h> |
| 17 | #include <linux/ethtool.h> | 17 | #include <linux/ethtool.h> |
| 18 | #include <asm/hardware/cache-feroceon-l2.h> | ||
| 18 | #include <asm/mach/map.h> | 19 | #include <asm/mach/map.h> |
| 19 | #include <asm/mach/time.h> | 20 | #include <asm/mach/time.h> |
| 20 | #include <mach/mv78xx0.h> | 21 | #include <mach/mv78xx0.h> |
| 21 | #include <mach/bridge-regs.h> | 22 | #include <mach/bridge-regs.h> |
| 22 | #include <plat/cache-feroceon-l2.h> | ||
| 23 | #include <linux/platform_data/usb-ehci-orion.h> | 23 | #include <linux/platform_data/usb-ehci-orion.h> |
| 24 | #include <linux/platform_data/mtd-orion_nand.h> | 24 | #include <linux/platform_data/mtd-orion_nand.h> |
| 25 | #include <plat/time.h> | 25 | #include <plat/time.h> |
diff --git a/arch/arm/mach-mv78xx0/include/mach/timex.h b/arch/arm/mach-mv78xx0/include/mach/timex.h deleted file mode 100644 index 0e8c443c723a..000000000000 --- a/arch/arm/mach-mv78xx0/include/mach/timex.h +++ /dev/null | |||
| @@ -1,9 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-mv78xx0/include/mach/timex.h | ||
| 3 | * | ||
| 4 | * This file is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2. This program is licensed "as is" without any | ||
| 6 | * warranty of any kind, whether express or implied. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #define CLOCK_TICK_RATE (100 * HZ) | ||
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 5e269d7263ce..4fecf5d41d8d 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | config ARCH_MVEBU | 1 | config ARCH_MVEBU |
| 2 | bool "Marvell SOCs with Device Tree support" if ARCH_MULTI_V7 | 2 | bool "Marvell Engineering Business Unit (MVEBU) SoCs" if (ARCH_MULTI_V7 || ARCH_MULTI_V5) |
| 3 | select ARCH_SUPPORTS_BIG_ENDIAN | 3 | select ARCH_SUPPORTS_BIG_ENDIAN |
| 4 | select CLKSRC_MMIO | 4 | select CLKSRC_MMIO |
| 5 | select COMMON_CLK | 5 | select COMMON_CLK |
| @@ -19,33 +19,98 @@ config ARCH_MVEBU | |||
| 19 | 19 | ||
| 20 | if ARCH_MVEBU | 20 | if ARCH_MVEBU |
| 21 | 21 | ||
| 22 | menu "Marvell SOC with device tree" | 22 | menu "Marvell EBU SoC variants" |
| 23 | 23 | ||
| 24 | config MACH_ARMADA_370_XP | 24 | config MACH_MVEBU_V7 |
| 25 | bool | 25 | bool |
| 26 | select ARMADA_370_XP_TIMER | 26 | select ARMADA_370_XP_TIMER |
| 27 | select HAVE_SMP | 27 | select HAVE_SMP |
| 28 | select CACHE_L2X0 | 28 | select CACHE_L2X0 |
| 29 | select CPU_PJ4B | ||
| 30 | 29 | ||
| 31 | config MACH_ARMADA_370 | 30 | config MACH_ARMADA_370 |
| 32 | bool "Marvell Armada 370 boards" | 31 | bool "Marvell Armada 370 boards" if ARCH_MULTI_V7 |
| 33 | select ARMADA_370_CLK | 32 | select ARMADA_370_CLK |
| 34 | select MACH_ARMADA_370_XP | 33 | select CPU_PJ4B |
| 34 | select MACH_MVEBU_V7 | ||
| 35 | select PINCTRL_ARMADA_370 | 35 | select PINCTRL_ARMADA_370 |
| 36 | help | 36 | help |
| 37 | Say 'Y' here if you want your kernel to support boards based | 37 | Say 'Y' here if you want your kernel to support boards based |
| 38 | on the Marvell Armada 370 SoC with device tree. | 38 | on the Marvell Armada 370 SoC with device tree. |
| 39 | 39 | ||
| 40 | config MACH_ARMADA_375 | ||
| 41 | bool "Marvell Armada 375 boards" if ARCH_MULTI_V7 | ||
| 42 | select ARM_ERRATA_720789 | ||
| 43 | select ARM_ERRATA_753970 | ||
| 44 | select ARM_GIC | ||
| 45 | select ARMADA_375_CLK | ||
| 46 | select CPU_V7 | ||
| 47 | select MACH_MVEBU_V7 | ||
| 48 | select NEON | ||
| 49 | select PINCTRL_ARMADA_375 | ||
| 50 | help | ||
| 51 | Say 'Y' here if you want your kernel to support boards based | ||
| 52 | on the Marvell Armada 375 SoC with device tree. | ||
| 53 | |||
| 54 | config MACH_ARMADA_38X | ||
| 55 | bool "Marvell Armada 380/385 boards" if ARCH_MULTI_V7 | ||
| 56 | select ARM_ERRATA_720789 | ||
| 57 | select ARM_ERRATA_753970 | ||
| 58 | select ARM_GIC | ||
| 59 | select ARMADA_38X_CLK | ||
| 60 | select CPU_V7 | ||
| 61 | select MACH_MVEBU_V7 | ||
| 62 | select NEON | ||
| 63 | select PINCTRL_ARMADA_38X | ||
| 64 | help | ||
| 65 | Say 'Y' here if you want your kernel to support boards based | ||
| 66 | on the Marvell Armada 380/385 SoC with device tree. | ||
| 67 | |||
| 40 | config MACH_ARMADA_XP | 68 | config MACH_ARMADA_XP |
| 41 | bool "Marvell Armada XP boards" | 69 | bool "Marvell Armada XP boards" if ARCH_MULTI_V7 |
| 42 | select ARMADA_XP_CLK | 70 | select ARMADA_XP_CLK |
| 43 | select MACH_ARMADA_370_XP | 71 | select CPU_PJ4B |
| 72 | select MACH_MVEBU_V7 | ||
| 44 | select PINCTRL_ARMADA_XP | 73 | select PINCTRL_ARMADA_XP |
| 45 | help | 74 | help |
| 46 | Say 'Y' here if you want your kernel to support boards based | 75 | Say 'Y' here if you want your kernel to support boards based |
| 47 | on the Marvell Armada XP SoC with device tree. | 76 | on the Marvell Armada XP SoC with device tree. |
| 48 | 77 | ||
| 78 | config MACH_DOVE | ||
| 79 | bool "Marvell Dove boards" if ARCH_MULTI_V7 | ||
| 80 | select CACHE_L2X0 | ||
| 81 | select CPU_PJ4 | ||
| 82 | select DOVE_CLK | ||
| 83 | select ORION_IRQCHIP | ||
| 84 | select ORION_TIMER | ||
| 85 | select PINCTRL_DOVE | ||
| 86 | help | ||
| 87 | Say 'Y' here if you want your kernel to support the | ||
| 88 | Marvell Dove using flattened device tree. | ||
| 89 | |||
| 90 | config MACH_KIRKWOOD | ||
| 91 | bool "Marvell Kirkwood boards" if ARCH_MULTI_V5 | ||
| 92 | select ARCH_HAS_CPUFREQ | ||
| 93 | select ARCH_REQUIRE_GPIOLIB | ||
| 94 | select CPU_FEROCEON | ||
| 95 | select KIRKWOOD_CLK | ||
| 96 | select OF_IRQ | ||
| 97 | select ORION_IRQCHIP | ||
| 98 | select ORION_TIMER | ||
| 99 | select PCI | ||
| 100 | select PCI_QUIRKS | ||
| 101 | select PINCTRL_KIRKWOOD | ||
| 102 | select USE_OF | ||
| 103 | help | ||
| 104 | Say 'Y' here if you want your kernel to support boards based | ||
| 105 | on the Marvell Kirkwood device tree. | ||
| 106 | |||
| 107 | config MACH_T5325 | ||
| 108 | bool "HP T5325 thin client" | ||
| 109 | depends on MACH_KIRKWOOD | ||
| 110 | help | ||
| 111 | Say 'Y' here if you want your kernel to support the | ||
| 112 | HP T5325 Thin client | ||
| 113 | |||
| 49 | endmenu | 114 | endmenu |
| 50 | 115 | ||
| 51 | endif | 116 | endif |
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index 878aebe98dcc..a63e43b6b451 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile | |||
| @@ -4,7 +4,10 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \ | |||
| 4 | AFLAGS_coherency_ll.o := -Wa,-march=armv7-a | 4 | AFLAGS_coherency_ll.o := -Wa,-march=armv7-a |
| 5 | 5 | ||
| 6 | obj-y += system-controller.o mvebu-soc-id.o | 6 | obj-y += system-controller.o mvebu-soc-id.o |
| 7 | obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o | 7 | obj-$(CONFIG_MACH_MVEBU_V7) += board-v7.o |
| 8 | obj-$(CONFIG_MACH_DOVE) += dove.o | ||
| 8 | obj-$(CONFIG_ARCH_MVEBU) += coherency.o coherency_ll.o pmsu.o | 9 | obj-$(CONFIG_ARCH_MVEBU) += coherency.o coherency_ll.o pmsu.o |
| 9 | obj-$(CONFIG_SMP) += platsmp.o headsmp.o | 10 | obj-$(CONFIG_SMP) += platsmp.o headsmp.o |
| 10 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o | 11 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o |
| 12 | obj-$(CONFIG_MACH_KIRKWOOD) += kirkwood.o kirkwood-pm.o | ||
| 13 | obj-$(CONFIG_MACH_T5325) += board-t5325.o | ||
diff --git a/arch/arm/mach-mvebu/board-t5325.c b/arch/arm/mach-mvebu/board-t5325.c new file mode 100644 index 000000000000..65ace6db9f28 --- /dev/null +++ b/arch/arm/mach-mvebu/board-t5325.c | |||
| @@ -0,0 +1,41 @@ | |||
| 1 | /* | ||
| 2 | * HP T5325 Board Setup | ||
| 3 | * | ||
| 4 | * Copyright (C) 2014 | ||
| 5 | * | ||
| 6 | * Andrew Lunn <andrew@lunn.ch> | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/i2c.h> | ||
| 15 | #include <linux/init.h> | ||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <sound/alc5623.h> | ||
| 18 | #include "board.h" | ||
| 19 | |||
| 20 | static struct platform_device hp_t5325_audio_device = { | ||
| 21 | .name = "t5325-audio", | ||
| 22 | .id = -1, | ||
| 23 | }; | ||
| 24 | |||
| 25 | static struct alc5623_platform_data alc5621_data = { | ||
| 26 | .add_ctrl = 0x3700, | ||
| 27 | .jack_det_ctrl = 0x4810, | ||
| 28 | }; | ||
| 29 | |||
| 30 | static struct i2c_board_info i2c_board_info[] __initdata = { | ||
| 31 | { | ||
| 32 | I2C_BOARD_INFO("alc5621", 0x1a), | ||
| 33 | .platform_data = &alc5621_data, | ||
| 34 | }, | ||
| 35 | }; | ||
| 36 | |||
| 37 | void __init t5325_init(void) | ||
| 38 | { | ||
| 39 | i2c_register_board_info(0, i2c_board_info, ARRAY_SIZE(i2c_board_info)); | ||
| 40 | platform_device_register(&hp_t5325_audio_device); | ||
| 41 | } | ||
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/board-v7.c index f6c9d1d85c14..746134ecdfc2 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.c +++ b/arch/arm/mach-mvebu/board-v7.c | |||
| @@ -31,12 +31,28 @@ | |||
| 31 | #include "coherency.h" | 31 | #include "coherency.h" |
| 32 | #include "mvebu-soc-id.h" | 32 | #include "mvebu-soc-id.h" |
| 33 | 33 | ||
| 34 | static void __init armada_370_xp_map_io(void) | 34 | /* |
| 35 | * Early versions of Armada 375 SoC have a bug where the BootROM | ||
| 36 | * leaves an external data abort pending. The kernel is hit by this | ||
| 37 | * data abort as soon as it enters userspace, because it unmasks the | ||
| 38 | * data aborts at this moment. We register a custom abort handler | ||
| 39 | * below to ignore the first data abort to work around this | ||
| 40 | * problem. | ||
| 41 | */ | ||
| 42 | static int armada_375_external_abort_wa(unsigned long addr, unsigned int fsr, | ||
| 43 | struct pt_regs *regs) | ||
| 35 | { | 44 | { |
| 36 | debug_ll_io_init(); | 45 | static int ignore_first; |
| 46 | |||
| 47 | if (!ignore_first && fsr == 0x1406) { | ||
| 48 | ignore_first = 1; | ||
| 49 | return 0; | ||
| 50 | } | ||
| 51 | |||
| 52 | return 1; | ||
| 37 | } | 53 | } |
| 38 | 54 | ||
| 39 | static void __init armada_370_xp_timer_and_clk_init(void) | 55 | static void __init mvebu_timer_and_clk_init(void) |
| 40 | { | 56 | { |
| 41 | of_clk_init(NULL); | 57 | of_clk_init(NULL); |
| 42 | clocksource_of_init(); | 58 | clocksource_of_init(); |
| @@ -45,6 +61,10 @@ static void __init armada_370_xp_timer_and_clk_init(void) | |||
| 45 | #ifdef CONFIG_CACHE_L2X0 | 61 | #ifdef CONFIG_CACHE_L2X0 |
| 46 | l2x0_of_init(0, ~0UL); | 62 | l2x0_of_init(0, ~0UL); |
| 47 | #endif | 63 | #endif |
| 64 | |||
| 65 | if (of_machine_is_compatible("marvell,armada375")) | ||
| 66 | hook_fault_code(16 + 6, armada_375_external_abort_wa, SIGBUS, 0, | ||
| 67 | "imprecise external abort"); | ||
| 48 | } | 68 | } |
| 49 | 69 | ||
| 50 | static void __init i2c_quirk(void) | 70 | static void __init i2c_quirk(void) |
| @@ -75,7 +95,7 @@ static void __init i2c_quirk(void) | |||
| 75 | return; | 95 | return; |
| 76 | } | 96 | } |
| 77 | 97 | ||
| 78 | static void __init armada_370_xp_dt_init(void) | 98 | static void __init mvebu_dt_init(void) |
| 79 | { | 99 | { |
| 80 | if (of_machine_is_compatible("plathome,openblocks-ax3-4")) | 100 | if (of_machine_is_compatible("plathome,openblocks-ax3-4")) |
| 81 | i2c_quirk(); | 101 | i2c_quirk(); |
| @@ -87,11 +107,33 @@ static const char * const armada_370_xp_dt_compat[] = { | |||
| 87 | NULL, | 107 | NULL, |
| 88 | }; | 108 | }; |
| 89 | 109 | ||
| 90 | DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 370/XP (Device Tree)") | 110 | DT_MACHINE_START(ARMADA_370_XP_DT, "Marvell Armada 370/XP (Device Tree)") |
| 91 | .smp = smp_ops(armada_xp_smp_ops), | 111 | .smp = smp_ops(armada_xp_smp_ops), |
| 92 | .init_machine = armada_370_xp_dt_init, | 112 | .init_machine = mvebu_dt_init, |
| 93 | .map_io = armada_370_xp_map_io, | 113 | .init_time = mvebu_timer_and_clk_init, |
| 94 | .init_time = armada_370_xp_timer_and_clk_init, | ||
| 95 | .restart = mvebu_restart, | 114 | .restart = mvebu_restart, |
| 96 | .dt_compat = armada_370_xp_dt_compat, | 115 | .dt_compat = armada_370_xp_dt_compat, |
| 97 | MACHINE_END | 116 | MACHINE_END |
| 117 | |||
| 118 | static const char * const armada_375_dt_compat[] = { | ||
| 119 | "marvell,armada375", | ||
| 120 | NULL, | ||
| 121 | }; | ||
| 122 | |||
| 123 | DT_MACHINE_START(ARMADA_375_DT, "Marvell Armada 375 (Device Tree)") | ||
| 124 | .init_time = mvebu_timer_and_clk_init, | ||
| 125 | .restart = mvebu_restart, | ||
| 126 | .dt_compat = armada_375_dt_compat, | ||
| 127 | MACHINE_END | ||
| 128 | |||
| 129 | static const char * const armada_38x_dt_compat[] = { | ||
| 130 | "marvell,armada380", | ||
| 131 | "marvell,armada385", | ||
| 132 | NULL, | ||
| 133 | }; | ||
| 134 | |||
| 135 | DT_MACHINE_START(ARMADA_38X_DT, "Marvell Armada 380/385 (Device Tree)") | ||
| 136 | .init_time = mvebu_timer_and_clk_init, | ||
| 137 | .restart = mvebu_restart, | ||
| 138 | .dt_compat = armada_38x_dt_compat, | ||
| 139 | MACHINE_END | ||
diff --git a/arch/arm/mach-mvebu/board.h b/arch/arm/mach-mvebu/board.h new file mode 100644 index 000000000000..de7f0a191394 --- /dev/null +++ b/arch/arm/mach-mvebu/board.h | |||
| @@ -0,0 +1,22 @@ | |||
| 1 | /* | ||
| 2 | * Board functions for Marvell System On Chip | ||
| 3 | * | ||
| 4 | * Copyright (C) 2014 | ||
| 5 | * | ||
| 6 | * Andrew Lunn <andrew@lunn.ch> | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ARCH_MVEBU_BOARD_H | ||
| 14 | #define __ARCH_MVEBU_BOARD_H | ||
| 15 | |||
| 16 | #ifdef CONFIG_MACH_T5325 | ||
| 17 | void t5325_init(void); | ||
| 18 | #else | ||
| 19 | static inline void t5325_init(void) {}; | ||
| 20 | #endif | ||
| 21 | |||
| 22 | #endif | ||
diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-mvebu/dove.c index 49fa9abd09da..5e5a43624237 100644 --- a/arch/arm/mach-dove/board-dt.c +++ b/arch/arm/mach-mvebu/dove.c | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-dove/board-dt.c | 2 | * arch/arm/mach-mvebu/dove.c |
| 3 | * | 3 | * |
| 4 | * Marvell Dove 88AP510 System On Chip FDT Board | 4 | * Marvell Dove 88AP510 System On Chip FDT Board |
| 5 | * | 5 | * |
| @@ -9,17 +9,14 @@ | |||
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | #include <linux/init.h> | 11 | #include <linux/init.h> |
| 12 | #include <linux/clk-provider.h> | 12 | #include <linux/mbus.h> |
| 13 | #include <linux/of.h> | 13 | #include <linux/of.h> |
| 14 | #include <linux/of_platform.h> | 14 | #include <linux/of_platform.h> |
| 15 | #include <asm/hardware/cache-tauros2.h> | 15 | #include <asm/hardware/cache-tauros2.h> |
| 16 | #include <asm/mach/arch.h> | 16 | #include <asm/mach/arch.h> |
| 17 | #include <mach/dove.h> | ||
| 18 | #include <mach/pm.h> | ||
| 19 | #include <plat/common.h> | ||
| 20 | #include "common.h" | 17 | #include "common.h" |
| 21 | 18 | ||
| 22 | static void __init dove_dt_init(void) | 19 | static void __init dove_init(void) |
| 23 | { | 20 | { |
| 24 | pr_info("Dove 88AP510 SoC\n"); | 21 | pr_info("Dove 88AP510 SoC\n"); |
| 25 | 22 | ||
| @@ -30,14 +27,13 @@ static void __init dove_dt_init(void) | |||
| 30 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | 27 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
| 31 | } | 28 | } |
| 32 | 29 | ||
| 33 | static const char * const dove_dt_board_compat[] = { | 30 | static const char * const dove_dt_compat[] = { |
| 34 | "marvell,dove", | 31 | "marvell,dove", |
| 35 | NULL | 32 | NULL |
| 36 | }; | 33 | }; |
| 37 | 34 | ||
| 38 | DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)") | 35 | DT_MACHINE_START(DOVE_DT, "Marvell Dove") |
| 39 | .map_io = dove_map_io, | 36 | .init_machine = dove_init, |
| 40 | .init_machine = dove_dt_init, | 37 | .restart = mvebu_restart, |
| 41 | .restart = dove_restart, | 38 | .dt_compat = dove_dt_compat, |
| 42 | .dt_compat = dove_dt_board_compat, | ||
| 43 | MACHINE_END | 39 | MACHINE_END |
diff --git a/arch/arm/mach-mvebu/kirkwood-pm.c b/arch/arm/mach-mvebu/kirkwood-pm.c new file mode 100644 index 000000000000..cbb816f2120c --- /dev/null +++ b/arch/arm/mach-mvebu/kirkwood-pm.c | |||
| @@ -0,0 +1,76 @@ | |||
| 1 | /* | ||
| 2 | * Power Management driver for Marvell Kirkwood SoCs | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Ezequiel Garcia <ezequiel@free-electrons.com> | ||
| 5 | * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License, | ||
| 9 | * version 2 of the License. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include <linux/kernel.h> | ||
| 18 | #include <linux/suspend.h> | ||
| 19 | #include <linux/io.h> | ||
| 20 | #include "kirkwood.h" | ||
| 21 | |||
| 22 | static void __iomem *ddr_operation_base; | ||
| 23 | static void __iomem *memory_pm_ctrl; | ||
| 24 | |||
| 25 | static void kirkwood_low_power(void) | ||
| 26 | { | ||
| 27 | u32 mem_pm_ctrl; | ||
| 28 | |||
| 29 | mem_pm_ctrl = readl(memory_pm_ctrl); | ||
| 30 | |||
| 31 | /* Set peripherals to low-power mode */ | ||
| 32 | writel_relaxed(~0, memory_pm_ctrl); | ||
| 33 | |||
| 34 | /* Set DDR in self-refresh */ | ||
| 35 | writel_relaxed(0x7, ddr_operation_base); | ||
| 36 | |||
| 37 | /* | ||
| 38 | * Set CPU in wait-for-interrupt state. | ||
| 39 | * This disables the CPU core clocks, | ||
| 40 | * the array clocks, and also the L2 controller. | ||
| 41 | */ | ||
| 42 | cpu_do_idle(); | ||
| 43 | |||
| 44 | writel_relaxed(mem_pm_ctrl, memory_pm_ctrl); | ||
| 45 | } | ||
| 46 | |||
| 47 | static int kirkwood_suspend_enter(suspend_state_t state) | ||
| 48 | { | ||
| 49 | switch (state) { | ||
| 50 | case PM_SUSPEND_STANDBY: | ||
| 51 | kirkwood_low_power(); | ||
| 52 | break; | ||
| 53 | default: | ||
| 54 | return -EINVAL; | ||
| 55 | } | ||
| 56 | return 0; | ||
| 57 | } | ||
| 58 | |||
| 59 | static int kirkwood_pm_valid_standby(suspend_state_t state) | ||
| 60 | { | ||
| 61 | return state == PM_SUSPEND_STANDBY; | ||
| 62 | } | ||
| 63 | |||
| 64 | static const struct platform_suspend_ops kirkwood_suspend_ops = { | ||
| 65 | .enter = kirkwood_suspend_enter, | ||
| 66 | .valid = kirkwood_pm_valid_standby, | ||
| 67 | }; | ||
| 68 | |||
| 69 | int __init kirkwood_pm_init(void) | ||
| 70 | { | ||
| 71 | ddr_operation_base = ioremap(DDR_OPERATION_BASE, 4); | ||
| 72 | memory_pm_ctrl = ioremap(MEMORY_PM_CTRL_PHYS, 4); | ||
| 73 | |||
| 74 | suspend_set_ops(&kirkwood_suspend_ops); | ||
| 75 | return 0; | ||
| 76 | } | ||
diff --git a/arch/arm/mach-mvebu/kirkwood-pm.h b/arch/arm/mach-mvebu/kirkwood-pm.h new file mode 100644 index 000000000000..21e7530f368b --- /dev/null +++ b/arch/arm/mach-mvebu/kirkwood-pm.h | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | /* | ||
| 2 | * Power Management driver for Marvell Kirkwood SoCs | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Ezequiel Garcia <ezequiel@free-electrons.com> | ||
| 5 | * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License, | ||
| 9 | * version 2 of the License. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef __ARCH_KIRKWOOD_PM_H | ||
| 18 | #define __ARCH_KIRKWOOD_PM_H | ||
| 19 | |||
| 20 | #ifdef CONFIG_PM | ||
| 21 | void kirkwood_pm_init(void); | ||
| 22 | #else | ||
| 23 | static inline void kirkwood_pm_init(void) {}; | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #endif | ||
diff --git a/arch/arm/mach-mvebu/kirkwood.c b/arch/arm/mach-mvebu/kirkwood.c new file mode 100644 index 000000000000..120207fc36f1 --- /dev/null +++ b/arch/arm/mach-mvebu/kirkwood.c | |||
| @@ -0,0 +1,199 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2012 (C), Jason Cooper <jason@lakedaemon.net> | ||
| 3 | * | ||
| 4 | * arch/arm/mach-mvebu/kirkwood.c | ||
| 5 | * | ||
| 6 | * Flattened Device Tree board initialization | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/clk.h> | ||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/init.h> | ||
| 16 | #include <linux/mbus.h> | ||
| 17 | #include <linux/of.h> | ||
| 18 | #include <linux/of_address.h> | ||
| 19 | #include <linux/of_net.h> | ||
| 20 | #include <linux/of_platform.h> | ||
| 21 | #include <linux/slab.h> | ||
| 22 | #include <asm/hardware/cache-feroceon-l2.h> | ||
| 23 | #include <asm/mach/arch.h> | ||
| 24 | #include <asm/mach/map.h> | ||
| 25 | #include "kirkwood.h" | ||
| 26 | #include "kirkwood-pm.h" | ||
| 27 | #include "common.h" | ||
| 28 | #include "board.h" | ||
| 29 | |||
| 30 | static struct resource kirkwood_cpufreq_resources[] = { | ||
| 31 | [0] = { | ||
| 32 | .start = CPU_CONTROL_PHYS, | ||
| 33 | .end = CPU_CONTROL_PHYS + 3, | ||
| 34 | .flags = IORESOURCE_MEM, | ||
| 35 | }, | ||
| 36 | }; | ||
| 37 | |||
| 38 | static struct platform_device kirkwood_cpufreq_device = { | ||
| 39 | .name = "kirkwood-cpufreq", | ||
| 40 | .id = -1, | ||
| 41 | .num_resources = ARRAY_SIZE(kirkwood_cpufreq_resources), | ||
| 42 | .resource = kirkwood_cpufreq_resources, | ||
| 43 | }; | ||
| 44 | |||
| 45 | static void __init kirkwood_cpufreq_init(void) | ||
| 46 | { | ||
| 47 | platform_device_register(&kirkwood_cpufreq_device); | ||
| 48 | } | ||
| 49 | |||
| 50 | static struct resource kirkwood_cpuidle_resource[] = { | ||
| 51 | { | ||
| 52 | .flags = IORESOURCE_MEM, | ||
| 53 | .start = DDR_OPERATION_BASE, | ||
| 54 | .end = DDR_OPERATION_BASE + 3, | ||
| 55 | }, | ||
| 56 | }; | ||
| 57 | |||
| 58 | static struct platform_device kirkwood_cpuidle = { | ||
| 59 | .name = "kirkwood_cpuidle", | ||
| 60 | .id = -1, | ||
| 61 | .resource = kirkwood_cpuidle_resource, | ||
| 62 | .num_resources = 1, | ||
| 63 | }; | ||
| 64 | |||
| 65 | static void __init kirkwood_cpuidle_init(void) | ||
| 66 | { | ||
| 67 | platform_device_register(&kirkwood_cpuidle); | ||
| 68 | } | ||
| 69 | |||
| 70 | #define MV643XX_ETH_MAC_ADDR_LOW 0x0414 | ||
| 71 | #define MV643XX_ETH_MAC_ADDR_HIGH 0x0418 | ||
| 72 | |||
| 73 | static void __init kirkwood_dt_eth_fixup(void) | ||
| 74 | { | ||
| 75 | struct device_node *np; | ||
| 76 | |||
| 77 | /* | ||
| 78 | * The ethernet interfaces forget the MAC address assigned by u-boot | ||
| 79 | * if the clocks are turned off. Usually, u-boot on kirkwood boards | ||
| 80 | * has no DT support to properly set local-mac-address property. | ||
| 81 | * As a workaround, we get the MAC address from mv643xx_eth registers | ||
| 82 | * and update the port device node if no valid MAC address is set. | ||
| 83 | */ | ||
| 84 | for_each_compatible_node(np, NULL, "marvell,kirkwood-eth-port") { | ||
| 85 | struct device_node *pnp = of_get_parent(np); | ||
| 86 | struct clk *clk; | ||
| 87 | struct property *pmac; | ||
| 88 | void __iomem *io; | ||
| 89 | u8 *macaddr; | ||
| 90 | u32 reg; | ||
| 91 | |||
| 92 | if (!pnp) | ||
| 93 | continue; | ||
| 94 | |||
| 95 | /* skip disabled nodes or nodes with valid MAC address*/ | ||
| 96 | if (!of_device_is_available(pnp) || of_get_mac_address(np)) | ||
| 97 | goto eth_fixup_skip; | ||
| 98 | |||
| 99 | clk = of_clk_get(pnp, 0); | ||
| 100 | if (IS_ERR(clk)) | ||
| 101 | goto eth_fixup_skip; | ||
| 102 | |||
| 103 | io = of_iomap(pnp, 0); | ||
| 104 | if (!io) | ||
| 105 | goto eth_fixup_no_map; | ||
| 106 | |||
| 107 | /* ensure port clock is not gated to not hang CPU */ | ||
| 108 | clk_prepare_enable(clk); | ||
| 109 | |||
| 110 | /* store MAC address register contents in local-mac-address */ | ||
| 111 | pr_err(FW_INFO "%s: local-mac-address is not set\n", | ||
| 112 | np->full_name); | ||
| 113 | |||
| 114 | pmac = kzalloc(sizeof(*pmac) + 6, GFP_KERNEL); | ||
| 115 | if (!pmac) | ||
| 116 | goto eth_fixup_no_mem; | ||
| 117 | |||
| 118 | pmac->value = pmac + 1; | ||
| 119 | pmac->length = 6; | ||
| 120 | pmac->name = kstrdup("local-mac-address", GFP_KERNEL); | ||
| 121 | if (!pmac->name) { | ||
| 122 | kfree(pmac); | ||
| 123 | goto eth_fixup_no_mem; | ||
| 124 | } | ||
| 125 | |||
| 126 | macaddr = pmac->value; | ||
| 127 | reg = readl(io + MV643XX_ETH_MAC_ADDR_HIGH); | ||
| 128 | macaddr[0] = (reg >> 24) & 0xff; | ||
| 129 | macaddr[1] = (reg >> 16) & 0xff; | ||
| 130 | macaddr[2] = (reg >> 8) & 0xff; | ||
| 131 | macaddr[3] = reg & 0xff; | ||
| 132 | |||
| 133 | reg = readl(io + MV643XX_ETH_MAC_ADDR_LOW); | ||
| 134 | macaddr[4] = (reg >> 8) & 0xff; | ||
| 135 | macaddr[5] = reg & 0xff; | ||
| 136 | |||
| 137 | of_update_property(np, pmac); | ||
| 138 | |||
| 139 | eth_fixup_no_mem: | ||
| 140 | iounmap(io); | ||
| 141 | clk_disable_unprepare(clk); | ||
| 142 | eth_fixup_no_map: | ||
| 143 | clk_put(clk); | ||
| 144 | eth_fixup_skip: | ||
| 145 | of_node_put(pnp); | ||
| 146 | } | ||
| 147 | } | ||
| 148 | |||
| 149 | /* | ||
| 150 | * Disable propagation of mbus errors to the CPU local bus, as this | ||
| 151 | * causes mbus errors (which can occur for example for PCI aborts) to | ||
| 152 | * throw CPU aborts, which we're not set up to deal with. | ||
| 153 | */ | ||
| 154 | void kirkwood_disable_mbus_error_propagation(void) | ||
| 155 | { | ||
| 156 | void __iomem *cpu_config; | ||
| 157 | |||
| 158 | cpu_config = ioremap(CPU_CONFIG_PHYS, 4); | ||
| 159 | writel(readl(cpu_config) & ~CPU_CONFIG_ERROR_PROP, cpu_config); | ||
| 160 | } | ||
| 161 | |||
| 162 | static struct of_dev_auxdata auxdata[] __initdata = { | ||
| 163 | OF_DEV_AUXDATA("marvell,kirkwood-audio", 0xf10a0000, | ||
| 164 | "mvebu-audio", NULL), | ||
| 165 | { /* sentinel */ } | ||
| 166 | }; | ||
| 167 | |||
| 168 | static void __init kirkwood_dt_init(void) | ||
| 169 | { | ||
| 170 | kirkwood_disable_mbus_error_propagation(); | ||
| 171 | |||
| 172 | BUG_ON(mvebu_mbus_dt_init()); | ||
| 173 | |||
| 174 | #ifdef CONFIG_CACHE_FEROCEON_L2 | ||
| 175 | feroceon_of_init(); | ||
| 176 | #endif | ||
| 177 | kirkwood_cpufreq_init(); | ||
| 178 | kirkwood_cpuidle_init(); | ||
| 179 | |||
| 180 | kirkwood_pm_init(); | ||
| 181 | kirkwood_dt_eth_fixup(); | ||
| 182 | |||
| 183 | if (of_machine_is_compatible("hp,t5325")) | ||
| 184 | t5325_init(); | ||
| 185 | |||
| 186 | of_platform_populate(NULL, of_default_bus_match_table, auxdata, NULL); | ||
| 187 | } | ||
| 188 | |||
| 189 | static const char * const kirkwood_dt_board_compat[] = { | ||
| 190 | "marvell,kirkwood", | ||
| 191 | NULL | ||
| 192 | }; | ||
| 193 | |||
| 194 | DT_MACHINE_START(KIRKWOOD_DT, "Marvell Kirkwood (Flattened Device Tree)") | ||
| 195 | /* Maintainer: Jason Cooper <jason@lakedaemon.net> */ | ||
| 196 | .init_machine = kirkwood_dt_init, | ||
| 197 | .restart = mvebu_restart, | ||
| 198 | .dt_compat = kirkwood_dt_board_compat, | ||
| 199 | MACHINE_END | ||
diff --git a/arch/arm/mach-mvebu/kirkwood.h b/arch/arm/mach-mvebu/kirkwood.h new file mode 100644 index 000000000000..89f3d1f51643 --- /dev/null +++ b/arch/arm/mach-mvebu/kirkwood.h | |||
| @@ -0,0 +1,22 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-mvebu/kirkwood.h | ||
| 3 | * | ||
| 4 | * Generic definitions for Marvell Kirkwood SoC flavors: | ||
| 5 | * 88F6180, 88F6192 and 88F6281. | ||
| 6 | * | ||
| 7 | * This file is licensed under the terms of the GNU General Public | ||
| 8 | * License version 2. This program is licensed "as is" without any | ||
| 9 | * warranty of any kind, whether express or implied. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #define KIRKWOOD_REGS_PHYS_BASE 0xf1000000 | ||
| 13 | #define DDR_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x00000) | ||
| 14 | #define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x20000) | ||
| 15 | |||
| 16 | #define DDR_OPERATION_BASE (DDR_PHYS_BASE + 0x1418) | ||
| 17 | |||
| 18 | #define CPU_CONFIG_PHYS (BRIDGE_PHYS_BASE + 0x0100) | ||
| 19 | #define CPU_CONFIG_ERROR_PROP 0x00000004 | ||
| 20 | |||
| 21 | #define CPU_CONTROL_PHYS (BRIDGE_PHYS_BASE + 0x0104) | ||
| 22 | #define MEMORY_PM_CTRL_PHYS (BRIDGE_PHYS_BASE + 0x0118) | ||
diff --git a/arch/arm/mach-mvebu/mvebu-soc-id.c b/arch/arm/mach-mvebu/mvebu-soc-id.c index f3b325f6cbd4..f3d4cf53f746 100644 --- a/arch/arm/mach-mvebu/mvebu-soc-id.c +++ b/arch/arm/mach-mvebu/mvebu-soc-id.c | |||
| @@ -38,6 +38,7 @@ static bool is_id_valid; | |||
| 38 | static const struct of_device_id mvebu_pcie_of_match_table[] = { | 38 | static const struct of_device_id mvebu_pcie_of_match_table[] = { |
| 39 | { .compatible = "marvell,armada-xp-pcie", }, | 39 | { .compatible = "marvell,armada-xp-pcie", }, |
| 40 | { .compatible = "marvell,armada-370-pcie", }, | 40 | { .compatible = "marvell,armada-370-pcie", }, |
| 41 | { .compatible = "marvell,kirkwood-pcie" }, | ||
| 41 | {}, | 42 | {}, |
| 42 | }; | 43 | }; |
| 43 | 44 | ||
diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c index a7fb89a5b5d9..614ba6832ff3 100644 --- a/arch/arm/mach-mvebu/system-controller.c +++ b/arch/arm/mach-mvebu/system-controller.c | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * System controller support for Armada 370 and XP platforms. | 2 | * System controller support for Armada 370, 375 and XP platforms. |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2012 Marvell | 4 | * Copyright (C) 2012 Marvell |
| 5 | * | 5 | * |
| @@ -11,7 +11,7 @@ | |||
| 11 | * License version 2. This program is licensed "as is" without any | 11 | * License version 2. This program is licensed "as is" without any |
| 12 | * warranty of any kind, whether express or implied. | 12 | * warranty of any kind, whether express or implied. |
| 13 | * | 13 | * |
| 14 | * The Armada 370 and Armada XP SoCs both have a range of | 14 | * The Armada 370, 375 and Armada XP SoCs have a range of |
| 15 | * miscellaneous registers, that do not belong to a particular device, | 15 | * miscellaneous registers, that do not belong to a particular device, |
| 16 | * but rather provide system-level features. This basic | 16 | * but rather provide system-level features. This basic |
| 17 | * system-controller driver provides a device tree binding for those | 17 | * system-controller driver provides a device tree binding for those |
| @@ -47,6 +47,13 @@ static const struct mvebu_system_controller armada_370_xp_system_controller = { | |||
| 47 | .system_soft_reset = 0x1, | 47 | .system_soft_reset = 0x1, |
| 48 | }; | 48 | }; |
| 49 | 49 | ||
| 50 | static const struct mvebu_system_controller armada_375_system_controller = { | ||
| 51 | .rstoutn_mask_offset = 0x54, | ||
| 52 | .system_soft_reset_offset = 0x58, | ||
| 53 | .rstoutn_mask_reset_out_en = 0x1, | ||
| 54 | .system_soft_reset = 0x1, | ||
| 55 | }; | ||
| 56 | |||
| 50 | static const struct mvebu_system_controller orion_system_controller = { | 57 | static const struct mvebu_system_controller orion_system_controller = { |
| 51 | .rstoutn_mask_offset = 0x108, | 58 | .rstoutn_mask_offset = 0x108, |
| 52 | .system_soft_reset_offset = 0x10c, | 59 | .system_soft_reset_offset = 0x10c, |
| @@ -54,13 +61,16 @@ static const struct mvebu_system_controller orion_system_controller = { | |||
| 54 | .system_soft_reset = 0x1, | 61 | .system_soft_reset = 0x1, |
| 55 | }; | 62 | }; |
| 56 | 63 | ||
| 57 | static struct of_device_id of_system_controller_table[] = { | 64 | static const struct of_device_id of_system_controller_table[] = { |
| 58 | { | 65 | { |
| 59 | .compatible = "marvell,orion-system-controller", | 66 | .compatible = "marvell,orion-system-controller", |
| 60 | .data = (void *) &orion_system_controller, | 67 | .data = (void *) &orion_system_controller, |
| 61 | }, { | 68 | }, { |
| 62 | .compatible = "marvell,armada-370-xp-system-controller", | 69 | .compatible = "marvell,armada-370-xp-system-controller", |
| 63 | .data = (void *) &armada_370_xp_system_controller, | 70 | .data = (void *) &armada_370_xp_system_controller, |
| 71 | }, { | ||
| 72 | .compatible = "marvell,armada-375-system-controller", | ||
| 73 | .data = (void *) &armada_375_system_controller, | ||
| 64 | }, | 74 | }, |
| 65 | { /* end of list */ }, | 75 | { /* end of list */ }, |
| 66 | }; | 76 | }; |
| @@ -90,13 +100,12 @@ void mvebu_restart(enum reboot_mode mode, const char *cmd) | |||
| 90 | 100 | ||
| 91 | static int __init mvebu_system_controller_init(void) | 101 | static int __init mvebu_system_controller_init(void) |
| 92 | { | 102 | { |
| 103 | const struct of_device_id *match; | ||
| 93 | struct device_node *np; | 104 | struct device_node *np; |
| 94 | 105 | ||
| 95 | np = of_find_matching_node(NULL, of_system_controller_table); | 106 | np = of_find_matching_node_and_match(NULL, of_system_controller_table, |
| 107 | &match); | ||
| 96 | if (np) { | 108 | if (np) { |
| 97 | const struct of_device_id *match = | ||
| 98 | of_match_node(of_system_controller_table, np); | ||
| 99 | BUG_ON(!match); | ||
| 100 | system_controller_base = of_iomap(np, 0); | 109 | system_controller_base = of_iomap(np, 0); |
| 101 | mvebu_sc = (struct mvebu_system_controller *)match->data; | 110 | mvebu_sc = (struct mvebu_system_controller *)match->data; |
| 102 | of_node_put(np); | 111 | of_node_put(np); |
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index 1dc5acd4fc99..2e7cec86e50e 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c | |||
| @@ -157,6 +157,8 @@ enum mac_oui { | |||
| 157 | OUI_FSL, | 157 | OUI_FSL, |
| 158 | OUI_DENX, | 158 | OUI_DENX, |
| 159 | OUI_CRYSTALFONTZ, | 159 | OUI_CRYSTALFONTZ, |
| 160 | OUI_I2SE, | ||
| 161 | OUI_ARMADEUS, | ||
| 160 | }; | 162 | }; |
| 161 | 163 | ||
| 162 | static void __init update_fec_mac_prop(enum mac_oui oui) | 164 | static void __init update_fec_mac_prop(enum mac_oui oui) |
| @@ -211,6 +213,16 @@ static void __init update_fec_mac_prop(enum mac_oui oui) | |||
| 211 | macaddr[1] = 0xb9; | 213 | macaddr[1] = 0xb9; |
| 212 | macaddr[2] = 0xe1; | 214 | macaddr[2] = 0xe1; |
| 213 | break; | 215 | break; |
| 216 | case OUI_I2SE: | ||
| 217 | macaddr[0] = 0x00; | ||
| 218 | macaddr[1] = 0x01; | ||
| 219 | macaddr[2] = 0x87; | ||
| 220 | break; | ||
| 221 | case OUI_ARMADEUS: | ||
| 222 | macaddr[0] = 0x00; | ||
| 223 | macaddr[1] = 0x1e; | ||
| 224 | macaddr[2] = 0xac; | ||
| 225 | break; | ||
| 214 | } | 226 | } |
| 215 | val = ocotp[i]; | 227 | val = ocotp[i]; |
| 216 | macaddr[3] = (val >> 16) & 0xff; | 228 | macaddr[3] = (val >> 16) & 0xff; |
| @@ -236,6 +248,11 @@ static void __init imx28_evk_init(void) | |||
| 236 | mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0); | 248 | mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0); |
| 237 | } | 249 | } |
| 238 | 250 | ||
| 251 | static void __init imx28_apf28_init(void) | ||
| 252 | { | ||
| 253 | update_fec_mac_prop(OUI_ARMADEUS); | ||
| 254 | } | ||
| 255 | |||
| 239 | static int apx4devkit_phy_fixup(struct phy_device *phy) | 256 | static int apx4devkit_phy_fixup(struct phy_device *phy) |
| 240 | { | 257 | { |
| 241 | phy->dev_flags |= MICREL_PHY_50MHZ_CLK; | 258 | phy->dev_flags |= MICREL_PHY_50MHZ_CLK; |
| @@ -330,6 +347,11 @@ static void __init crystalfontz_init(void) | |||
| 330 | update_fec_mac_prop(OUI_CRYSTALFONTZ); | 347 | update_fec_mac_prop(OUI_CRYSTALFONTZ); |
| 331 | } | 348 | } |
| 332 | 349 | ||
| 350 | static void __init duckbill_init(void) | ||
| 351 | { | ||
| 352 | update_fec_mac_prop(OUI_I2SE); | ||
| 353 | } | ||
| 354 | |||
| 333 | static void __init m28cu3_init(void) | 355 | static void __init m28cu3_init(void) |
| 334 | { | 356 | { |
| 335 | update_fec_mac_prop(OUI_DENX); | 357 | update_fec_mac_prop(OUI_DENX); |
| @@ -426,6 +448,11 @@ static int __init mxs_restart_init(void) | |||
| 426 | return 0; | 448 | return 0; |
| 427 | } | 449 | } |
| 428 | 450 | ||
| 451 | static void __init eukrea_mbmx283lc_init(void) | ||
| 452 | { | ||
| 453 | mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0); | ||
| 454 | } | ||
| 455 | |||
| 429 | static void __init mxs_machine_init(void) | 456 | static void __init mxs_machine_init(void) |
| 430 | { | 457 | { |
| 431 | struct device_node *root; | 458 | struct device_node *root; |
| @@ -458,10 +485,16 @@ static void __init mxs_machine_init(void) | |||
| 458 | 485 | ||
| 459 | if (of_machine_is_compatible("fsl,imx28-evk")) | 486 | if (of_machine_is_compatible("fsl,imx28-evk")) |
| 460 | imx28_evk_init(); | 487 | imx28_evk_init(); |
| 488 | if (of_machine_is_compatible("armadeus,imx28-apf28")) | ||
| 489 | imx28_apf28_init(); | ||
| 461 | else if (of_machine_is_compatible("bluegiga,apx4devkit")) | 490 | else if (of_machine_is_compatible("bluegiga,apx4devkit")) |
| 462 | apx4devkit_init(); | 491 | apx4devkit_init(); |
| 463 | else if (of_machine_is_compatible("crystalfontz,cfa10036")) | 492 | else if (of_machine_is_compatible("crystalfontz,cfa10036")) |
| 464 | crystalfontz_init(); | 493 | crystalfontz_init(); |
| 494 | else if (of_machine_is_compatible("eukrea,mbmx283lc")) | ||
| 495 | eukrea_mbmx283lc_init(); | ||
| 496 | else if (of_machine_is_compatible("i2se,duckbill")) | ||
| 497 | duckbill_init(); | ||
| 465 | else if (of_machine_is_compatible("msr,m28cu3")) | 498 | else if (of_machine_is_compatible("msr,m28cu3")) |
| 466 | m28cu3_init(); | 499 | m28cu3_init(); |
| 467 | 500 | ||
diff --git a/arch/arm/mach-netx/include/mach/timex.h b/arch/arm/mach-netx/include/mach/timex.h deleted file mode 100644 index 1120dd0ba393..000000000000 --- a/arch/arm/mach-netx/include/mach/timex.h +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-netx/include/mach/timex.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 | ||
| 8 | * as published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 18 | */ | ||
| 19 | |||
| 20 | #define CLOCK_TICK_RATE 100000000 | ||
diff --git a/arch/arm/mach-netx/time.c b/arch/arm/mach-netx/time.c index 6df42e643031..e2346013e227 100644 --- a/arch/arm/mach-netx/time.c +++ b/arch/arm/mach-netx/time.c | |||
| @@ -28,6 +28,9 @@ | |||
| 28 | #include <asm/mach/time.h> | 28 | #include <asm/mach/time.h> |
| 29 | #include <mach/netx-regs.h> | 29 | #include <mach/netx-regs.h> |
| 30 | 30 | ||
| 31 | #define NETX_CLOCK_FREQ 100000000 | ||
| 32 | #define NETX_LATCH DIV_ROUND_CLOSEST(NETX_CLOCK_FREQ, HZ) | ||
| 33 | |||
| 31 | #define TIMER_CLOCKEVENT 0 | 34 | #define TIMER_CLOCKEVENT 0 |
| 32 | #define TIMER_CLOCKSOURCE 1 | 35 | #define TIMER_CLOCKSOURCE 1 |
| 33 | 36 | ||
| @@ -41,7 +44,7 @@ static void netx_set_mode(enum clock_event_mode mode, | |||
| 41 | 44 | ||
| 42 | switch (mode) { | 45 | switch (mode) { |
| 43 | case CLOCK_EVT_MODE_PERIODIC: | 46 | case CLOCK_EVT_MODE_PERIODIC: |
| 44 | writel(LATCH, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT)); | 47 | writel(NETX_LATCH, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT)); |
| 45 | tmode = NETX_GPIO_COUNTER_CTRL_RST_EN | | 48 | tmode = NETX_GPIO_COUNTER_CTRL_RST_EN | |
| 46 | NETX_GPIO_COUNTER_CTRL_IRQ_EN | | 49 | NETX_GPIO_COUNTER_CTRL_IRQ_EN | |
| 47 | NETX_GPIO_COUNTER_CTRL_RUN; | 50 | NETX_GPIO_COUNTER_CTRL_RUN; |
| @@ -114,7 +117,7 @@ void __init netx_timer_init(void) | |||
| 114 | /* Reset the timer value to zero */ | 117 | /* Reset the timer value to zero */ |
| 115 | writel(0, NETX_GPIO_COUNTER_CURRENT(0)); | 118 | writel(0, NETX_GPIO_COUNTER_CURRENT(0)); |
| 116 | 119 | ||
| 117 | writel(LATCH, NETX_GPIO_COUNTER_MAX(0)); | 120 | writel(NETX_LATCH, NETX_GPIO_COUNTER_MAX(0)); |
| 118 | 121 | ||
| 119 | /* acknowledge interrupt */ | 122 | /* acknowledge interrupt */ |
| 120 | writel(COUNTER_BIT(0), NETX_GPIO_IRQ); | 123 | writel(COUNTER_BIT(0), NETX_GPIO_IRQ); |
| @@ -137,11 +140,11 @@ void __init netx_timer_init(void) | |||
| 137 | NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE)); | 140 | NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE)); |
| 138 | 141 | ||
| 139 | clocksource_mmio_init(NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE), | 142 | clocksource_mmio_init(NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE), |
| 140 | "netx_timer", CLOCK_TICK_RATE, 200, 32, clocksource_mmio_readl_up); | 143 | "netx_timer", NETX_CLOCK_FREQ, 200, 32, clocksource_mmio_readl_up); |
| 141 | 144 | ||
| 142 | /* with max_delta_ns >= delta2ns(0x800) the system currently runs fine. | 145 | /* with max_delta_ns >= delta2ns(0x800) the system currently runs fine. |
| 143 | * Adding some safety ... */ | 146 | * Adding some safety ... */ |
| 144 | netx_clockevent.cpumask = cpumask_of(0); | 147 | netx_clockevent.cpumask = cpumask_of(0); |
| 145 | clockevents_config_and_register(&netx_clockevent, CLOCK_TICK_RATE, | 148 | clockevents_config_and_register(&netx_clockevent, NETX_CLOCK_FREQ, |
| 146 | 0xa00, 0xfffffffe); | 149 | 0xa00, 0xfffffffe); |
| 147 | } | 150 | } |
diff --git a/arch/arm/mach-omap1/include/mach/timex.h b/arch/arm/mach-omap1/include/mach/timex.h deleted file mode 100644 index 4793790d53cc..000000000000 --- a/arch/arm/mach-omap1/include/mach/timex.h +++ /dev/null | |||
| @@ -1,5 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-omap1/include/mach/timex.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #include <plat/timex.h> | ||
diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c index e6b91e552d3d..f03dc97921ad 100644 --- a/arch/arm/mach-omap2/clockdomains3xxx_data.c +++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c | |||
| @@ -247,7 +247,7 @@ static struct clockdomain neon_clkdm = { | |||
| 247 | static struct clockdomain iva2_clkdm = { | 247 | static struct clockdomain iva2_clkdm = { |
| 248 | .name = "iva2_clkdm", | 248 | .name = "iva2_clkdm", |
| 249 | .pwrdm = { .name = "iva2_pwrdm" }, | 249 | .pwrdm = { .name = "iva2_pwrdm" }, |
| 250 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 250 | .flags = CLKDM_CAN_SWSUP, |
| 251 | .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT, | 251 | .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT, |
| 252 | .wkdep_srcs = iva2_wkdeps, | 252 | .wkdep_srcs = iva2_wkdeps, |
| 253 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK, | 253 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK, |
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 0dd6398bade4..e58609b312c7 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c | |||
| @@ -229,6 +229,9 @@ static struct omap_iommu_arch_data omap3_isp_iommu = { | |||
| 229 | 229 | ||
| 230 | int omap3_init_camera(struct isp_platform_data *pdata) | 230 | int omap3_init_camera(struct isp_platform_data *pdata) |
| 231 | { | 231 | { |
| 232 | if (of_have_populated_dt()) | ||
| 233 | omap3_isp_iommu.name = "480bd400.mmu"; | ||
| 234 | |||
| 232 | omap3isp_device.dev.platform_data = pdata; | 235 | omap3isp_device.dev.platform_data = pdata; |
| 233 | omap3isp_device.dev.archdata.iommu = &omap3_isp_iommu; | 236 | omap3isp_device.dev.archdata.iommu = &omap3_isp_iommu; |
| 234 | 237 | ||
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index 174caecc3186..4349e82debfe 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c | |||
| @@ -45,24 +45,31 @@ static struct platform_device gpmc_nand_device = { | |||
| 45 | 45 | ||
| 46 | static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) | 46 | static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) |
| 47 | { | 47 | { |
| 48 | /* support only OMAP3 class */ | 48 | /* platforms which support all ECC schemes */ |
| 49 | if (!cpu_is_omap34xx() && !soc_is_am33xx()) { | 49 | if (soc_is_am33xx() || cpu_is_omap44xx() || |
| 50 | pr_err("BCH ecc is not supported on this CPU\n"); | 50 | soc_is_omap54xx() || soc_is_dra7xx()) |
| 51 | return 1; | ||
| 52 | |||
| 53 | /* OMAP3xxx do not have ELM engine, so cannot support ECC schemes | ||
| 54 | * which require H/W based ECC error detection */ | ||
| 55 | if ((cpu_is_omap34xx() || cpu_is_omap3630()) && | ||
| 56 | ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) || | ||
| 57 | (ecc_opt == OMAP_ECC_BCH8_CODE_HW))) | ||
| 51 | return 0; | 58 | return 0; |
| 52 | } | ||
| 53 | 59 | ||
| 54 | /* | 60 | /* |
| 55 | * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1 | 61 | * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1 |
| 56 | * and AM33xx derivates. Other chips may be added if confirmed to work. | 62 | * and AM33xx derivates. Other chips may be added if confirmed to work. |
| 57 | */ | 63 | */ |
| 58 | if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) && | 64 | if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW_DETECTION_SW) && |
| 59 | (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)) && | 65 | (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) |
| 60 | (!soc_is_am33xx())) { | ||
| 61 | pr_err("BCH 4-bit mode is not supported on this CPU\n"); | ||
| 62 | return 0; | 66 | return 0; |
| 63 | } | ||
| 64 | 67 | ||
| 65 | return 1; | 68 | /* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */ |
| 69 | if (ecc_opt == OMAP_ECC_HAM1_CODE_HW) | ||
| 70 | return 1; | ||
| 71 | else | ||
| 72 | return 0; | ||
| 66 | } | 73 | } |
| 67 | 74 | ||
| 68 | /* This function will go away once the device-tree convertion is complete */ | 75 | /* This function will go away once the device-tree convertion is complete */ |
| @@ -133,8 +140,10 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, | |||
| 133 | 140 | ||
| 134 | gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); | 141 | gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); |
| 135 | 142 | ||
| 136 | if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) | 143 | if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) { |
| 144 | dev_err(dev, "Unsupported NAND ECC scheme selected\n"); | ||
| 137 | return -EINVAL; | 145 | return -EINVAL; |
| 146 | } | ||
| 138 | 147 | ||
| 139 | err = platform_device_register(&gpmc_nand_device); | 148 | err = platform_device_register(&gpmc_nand_device); |
| 140 | if (err < 0) { | 149 | if (err < 0) { |
diff --git a/arch/arm/mach-omap2/include/mach/timex.h b/arch/arm/mach-omap2/include/mach/timex.h deleted file mode 100644 index de9f8fc40e7c..000000000000 --- a/arch/arm/mach-omap2/include/mach/timex.h +++ /dev/null | |||
| @@ -1,5 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-omap2/include/mach/timex.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #include <plat/timex.h> | ||
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 4c3b1e6df508..9c7e23aa0e7f 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | |||
| @@ -3029,8 +3029,6 @@ static struct omap_hwmod omap3xxx_mmu_isp_hwmod = { | |||
| 3029 | .flags = HWMOD_NO_IDLEST, | 3029 | .flags = HWMOD_NO_IDLEST, |
| 3030 | }; | 3030 | }; |
| 3031 | 3031 | ||
| 3032 | #ifdef CONFIG_OMAP_IOMMU_IVA2 | ||
| 3033 | |||
| 3034 | /* mmu iva */ | 3032 | /* mmu iva */ |
| 3035 | 3033 | ||
| 3036 | static struct omap_mmu_dev_attr mmu_iva_dev_attr = { | 3034 | static struct omap_mmu_dev_attr mmu_iva_dev_attr = { |
| @@ -3070,20 +3068,22 @@ static struct omap_hwmod omap3xxx_mmu_iva_hwmod = { | |||
| 3070 | .name = "mmu_iva", | 3068 | .name = "mmu_iva", |
| 3071 | .class = &omap3xxx_mmu_hwmod_class, | 3069 | .class = &omap3xxx_mmu_hwmod_class, |
| 3072 | .mpu_irqs = omap3xxx_mmu_iva_irqs, | 3070 | .mpu_irqs = omap3xxx_mmu_iva_irqs, |
| 3071 | .clkdm_name = "iva2_clkdm", | ||
| 3073 | .rst_lines = omap3xxx_mmu_iva_resets, | 3072 | .rst_lines = omap3xxx_mmu_iva_resets, |
| 3074 | .rst_lines_cnt = ARRAY_SIZE(omap3xxx_mmu_iva_resets), | 3073 | .rst_lines_cnt = ARRAY_SIZE(omap3xxx_mmu_iva_resets), |
| 3075 | .main_clk = "iva2_ck", | 3074 | .main_clk = "iva2_ck", |
| 3076 | .prcm = { | 3075 | .prcm = { |
| 3077 | .omap2 = { | 3076 | .omap2 = { |
| 3078 | .module_offs = OMAP3430_IVA2_MOD, | 3077 | .module_offs = OMAP3430_IVA2_MOD, |
| 3078 | .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, | ||
| 3079 | .idlest_reg_id = 1, | ||
| 3080 | .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT, | ||
| 3079 | }, | 3081 | }, |
| 3080 | }, | 3082 | }, |
| 3081 | .dev_attr = &mmu_iva_dev_attr, | 3083 | .dev_attr = &mmu_iva_dev_attr, |
| 3082 | .flags = HWMOD_NO_IDLEST, | 3084 | .flags = HWMOD_NO_IDLEST, |
| 3083 | }; | 3085 | }; |
| 3084 | 3086 | ||
| 3085 | #endif | ||
| 3086 | |||
| 3087 | /* l4_per -> gpio4 */ | 3087 | /* l4_per -> gpio4 */ |
| 3088 | static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { | 3088 | static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { |
| 3089 | { | 3089 | { |
| @@ -3855,9 +3855,7 @@ static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = { | |||
| 3855 | &omap3xxx_l4_core__hdq1w, | 3855 | &omap3xxx_l4_core__hdq1w, |
| 3856 | &omap3xxx_sad2d__l3, | 3856 | &omap3xxx_sad2d__l3, |
| 3857 | &omap3xxx_l4_core__mmu_isp, | 3857 | &omap3xxx_l4_core__mmu_isp, |
| 3858 | #ifdef CONFIG_OMAP_IOMMU_IVA2 | ||
| 3859 | &omap3xxx_l3_main__mmu_iva, | 3858 | &omap3xxx_l3_main__mmu_iva, |
| 3860 | #endif | ||
| 3861 | &omap34xx_l4_core__ssi, | 3859 | &omap34xx_l4_core__ssi, |
| 3862 | NULL | 3860 | NULL |
| 3863 | }; | 3861 | }; |
| @@ -3881,9 +3879,7 @@ static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = { | |||
| 3881 | &omap3xxx_l4_core__hdq1w, | 3879 | &omap3xxx_l4_core__hdq1w, |
| 3882 | &omap3xxx_sad2d__l3, | 3880 | &omap3xxx_sad2d__l3, |
| 3883 | &omap3xxx_l4_core__mmu_isp, | 3881 | &omap3xxx_l4_core__mmu_isp, |
| 3884 | #ifdef CONFIG_OMAP_IOMMU_IVA2 | ||
| 3885 | &omap3xxx_l3_main__mmu_iva, | 3882 | &omap3xxx_l3_main__mmu_iva, |
| 3886 | #endif | ||
| 3887 | NULL | 3883 | NULL |
| 3888 | }; | 3884 | }; |
| 3889 | 3885 | ||
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c index e297d6231c3a..892317294fdc 100644 --- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c | |||
| @@ -1122,6 +1122,71 @@ static struct omap_hwmod omap54xx_mmc5_hwmod = { | |||
| 1122 | }; | 1122 | }; |
| 1123 | 1123 | ||
| 1124 | /* | 1124 | /* |
| 1125 | * 'mmu' class | ||
| 1126 | * The memory management unit performs virtual to physical address translation | ||
| 1127 | * for its requestors. | ||
| 1128 | */ | ||
| 1129 | |||
| 1130 | static struct omap_hwmod_class_sysconfig omap54xx_mmu_sysc = { | ||
| 1131 | .rev_offs = 0x0000, | ||
| 1132 | .sysc_offs = 0x0010, | ||
| 1133 | .syss_offs = 0x0014, | ||
| 1134 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | ||
| 1135 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | ||
| 1136 | SYSS_HAS_RESET_STATUS), | ||
| 1137 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
| 1138 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
| 1139 | }; | ||
| 1140 | |||
| 1141 | static struct omap_hwmod_class omap54xx_mmu_hwmod_class = { | ||
| 1142 | .name = "mmu", | ||
| 1143 | .sysc = &omap54xx_mmu_sysc, | ||
| 1144 | }; | ||
| 1145 | |||
| 1146 | static struct omap_hwmod_rst_info omap54xx_mmu_dsp_resets[] = { | ||
| 1147 | { .name = "mmu_cache", .rst_shift = 1 }, | ||
| 1148 | }; | ||
| 1149 | |||
| 1150 | static struct omap_hwmod omap54xx_mmu_dsp_hwmod = { | ||
| 1151 | .name = "mmu_dsp", | ||
| 1152 | .class = &omap54xx_mmu_hwmod_class, | ||
| 1153 | .clkdm_name = "dsp_clkdm", | ||
| 1154 | .rst_lines = omap54xx_mmu_dsp_resets, | ||
| 1155 | .rst_lines_cnt = ARRAY_SIZE(omap54xx_mmu_dsp_resets), | ||
| 1156 | .main_clk = "dpll_iva_h11x2_ck", | ||
| 1157 | .prcm = { | ||
| 1158 | .omap4 = { | ||
| 1159 | .clkctrl_offs = OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET, | ||
| 1160 | .rstctrl_offs = OMAP54XX_RM_DSP_RSTCTRL_OFFSET, | ||
| 1161 | .context_offs = OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET, | ||
| 1162 | .modulemode = MODULEMODE_HWCTRL, | ||
| 1163 | }, | ||
| 1164 | }, | ||
| 1165 | }; | ||
| 1166 | |||
| 1167 | /* mmu ipu */ | ||
| 1168 | static struct omap_hwmod_rst_info omap54xx_mmu_ipu_resets[] = { | ||
| 1169 | { .name = "mmu_cache", .rst_shift = 2 }, | ||
| 1170 | }; | ||
| 1171 | |||
| 1172 | static struct omap_hwmod omap54xx_mmu_ipu_hwmod = { | ||
| 1173 | .name = "mmu_ipu", | ||
| 1174 | .class = &omap54xx_mmu_hwmod_class, | ||
| 1175 | .clkdm_name = "ipu_clkdm", | ||
| 1176 | .rst_lines = omap54xx_mmu_ipu_resets, | ||
| 1177 | .rst_lines_cnt = ARRAY_SIZE(omap54xx_mmu_ipu_resets), | ||
| 1178 | .main_clk = "dpll_core_h22x2_ck", | ||
| 1179 | .prcm = { | ||
| 1180 | .omap4 = { | ||
| 1181 | .clkctrl_offs = OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET, | ||
| 1182 | .rstctrl_offs = OMAP54XX_RM_IPU_RSTCTRL_OFFSET, | ||
| 1183 | .context_offs = OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET, | ||
| 1184 | .modulemode = MODULEMODE_HWCTRL, | ||
| 1185 | }, | ||
| 1186 | }, | ||
| 1187 | }; | ||
| 1188 | |||
| 1189 | /* | ||
| 1125 | * 'mpu' class | 1190 | * 'mpu' class |
| 1126 | * mpu sub-system | 1191 | * mpu sub-system |
| 1127 | */ | 1192 | */ |
| @@ -1763,6 +1828,14 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = { | |||
| 1763 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 1828 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1764 | }; | 1829 | }; |
| 1765 | 1830 | ||
| 1831 | /* l4_cfg -> mmu_dsp */ | ||
| 1832 | static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mmu_dsp = { | ||
| 1833 | .master = &omap54xx_l4_cfg_hwmod, | ||
| 1834 | .slave = &omap54xx_mmu_dsp_hwmod, | ||
| 1835 | .clk = "l4_root_clk_div", | ||
| 1836 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 1837 | }; | ||
| 1838 | |||
| 1766 | /* mpu -> l3_main_1 */ | 1839 | /* mpu -> l3_main_1 */ |
| 1767 | static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = { | 1840 | static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = { |
| 1768 | .master = &omap54xx_mpu_hwmod, | 1841 | .master = &omap54xx_mpu_hwmod, |
| @@ -1787,6 +1860,14 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = { | |||
| 1787 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 1860 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1788 | }; | 1861 | }; |
| 1789 | 1862 | ||
| 1863 | /* l3_main_2 -> mmu_ipu */ | ||
| 1864 | static struct omap_hwmod_ocp_if omap54xx_l3_main_2__mmu_ipu = { | ||
| 1865 | .master = &omap54xx_l3_main_2_hwmod, | ||
| 1866 | .slave = &omap54xx_mmu_ipu_hwmod, | ||
| 1867 | .clk = "l3_iclk_div", | ||
| 1868 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 1869 | }; | ||
| 1870 | |||
| 1790 | /* l3_main_1 -> l3_main_3 */ | 1871 | /* l3_main_1 -> l3_main_3 */ |
| 1791 | static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = { | 1872 | static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = { |
| 1792 | .master = &omap54xx_l3_main_1_hwmod, | 1873 | .master = &omap54xx_l3_main_1_hwmod, |
| @@ -2345,6 +2426,7 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = { | |||
| 2345 | &omap54xx_l4_wkup__counter_32k, | 2426 | &omap54xx_l4_wkup__counter_32k, |
| 2346 | &omap54xx_l4_cfg__dma_system, | 2427 | &omap54xx_l4_cfg__dma_system, |
| 2347 | &omap54xx_l4_abe__dmic, | 2428 | &omap54xx_l4_abe__dmic, |
| 2429 | &omap54xx_l4_cfg__mmu_dsp, | ||
| 2348 | &omap54xx_mpu__emif1, | 2430 | &omap54xx_mpu__emif1, |
| 2349 | &omap54xx_mpu__emif2, | 2431 | &omap54xx_mpu__emif2, |
| 2350 | &omap54xx_l4_wkup__gpio1, | 2432 | &omap54xx_l4_wkup__gpio1, |
| @@ -2360,6 +2442,7 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = { | |||
| 2360 | &omap54xx_l4_per__i2c3, | 2442 | &omap54xx_l4_per__i2c3, |
| 2361 | &omap54xx_l4_per__i2c4, | 2443 | &omap54xx_l4_per__i2c4, |
| 2362 | &omap54xx_l4_per__i2c5, | 2444 | &omap54xx_l4_per__i2c5, |
| 2445 | &omap54xx_l3_main_2__mmu_ipu, | ||
| 2363 | &omap54xx_l4_wkup__kbd, | 2446 | &omap54xx_l4_wkup__kbd, |
| 2364 | &omap54xx_l4_cfg__mailbox, | 2447 | &omap54xx_l4_cfg__mailbox, |
| 2365 | &omap54xx_l4_abe__mcbsp1, | 2448 | &omap54xx_l4_abe__mcbsp1, |
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index 3d5b24dcd9a4..db242c483dc0 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c | |||
| @@ -16,12 +16,14 @@ | |||
| 16 | #include <linux/wl12xx.h> | 16 | #include <linux/wl12xx.h> |
| 17 | 17 | ||
| 18 | #include <linux/platform_data/pinctrl-single.h> | 18 | #include <linux/platform_data/pinctrl-single.h> |
| 19 | #include <linux/platform_data/iommu-omap.h> | ||
| 19 | 20 | ||
| 20 | #include "am35xx.h" | 21 | #include "am35xx.h" |
| 21 | #include "common.h" | 22 | #include "common.h" |
| 22 | #include "common-board-devices.h" | 23 | #include "common-board-devices.h" |
| 23 | #include "dss-common.h" | 24 | #include "dss-common.h" |
| 24 | #include "control.h" | 25 | #include "control.h" |
| 26 | #include "omap_device.h" | ||
| 25 | 27 | ||
| 26 | struct pdata_init { | 28 | struct pdata_init { |
| 27 | const char *compatible; | 29 | const char *compatible; |
| @@ -31,20 +33,6 @@ struct pdata_init { | |||
| 31 | struct of_dev_auxdata omap_auxdata_lookup[]; | 33 | struct of_dev_auxdata omap_auxdata_lookup[]; |
| 32 | static struct twl4030_gpio_platform_data twl_gpio_auxdata; | 34 | static struct twl4030_gpio_platform_data twl_gpio_auxdata; |
| 33 | 35 | ||
| 34 | /* | ||
| 35 | * Create alias for USB host PHY clock. | ||
| 36 | * Remove this when clock phandle can be provided via DT | ||
| 37 | */ | ||
| 38 | static void __init __used legacy_init_ehci_clk(char *clkname) | ||
| 39 | { | ||
| 40 | int ret; | ||
| 41 | |||
| 42 | ret = clk_add_alias("main_clk", NULL, clkname, NULL); | ||
| 43 | if (ret) | ||
| 44 | pr_err("%s:Failed to add main_clk alias to %s :%d\n", | ||
| 45 | __func__, clkname, ret); | ||
| 46 | } | ||
| 47 | |||
| 48 | #if IS_ENABLED(CONFIG_WL12XX) | 36 | #if IS_ENABLED(CONFIG_WL12XX) |
| 49 | 37 | ||
| 50 | static struct wl12xx_platform_data wl12xx __initdata; | 38 | static struct wl12xx_platform_data wl12xx __initdata; |
| @@ -92,6 +80,12 @@ static void __init hsmmc2_internal_input_clk(void) | |||
| 92 | omap_ctrl_writel(reg, OMAP343X_CONTROL_DEVCONF1); | 80 | omap_ctrl_writel(reg, OMAP343X_CONTROL_DEVCONF1); |
| 93 | } | 81 | } |
| 94 | 82 | ||
| 83 | static struct iommu_platform_data omap3_iommu_pdata = { | ||
| 84 | .reset_name = "mmu", | ||
| 85 | .assert_reset = omap_device_assert_hardreset, | ||
| 86 | .deassert_reset = omap_device_deassert_hardreset, | ||
| 87 | }; | ||
| 88 | |||
| 95 | static int omap3_sbc_t3730_twl_callback(struct device *dev, | 89 | static int omap3_sbc_t3730_twl_callback(struct device *dev, |
| 96 | unsigned gpio, | 90 | unsigned gpio, |
| 97 | unsigned ngpio) | 91 | unsigned ngpio) |
| @@ -99,7 +93,7 @@ static int omap3_sbc_t3730_twl_callback(struct device *dev, | |||
| 99 | int res; | 93 | int res; |
| 100 | 94 | ||
| 101 | res = gpio_request_one(gpio + 2, GPIOF_OUT_INIT_HIGH, | 95 | res = gpio_request_one(gpio + 2, GPIOF_OUT_INIT_HIGH, |
| 102 | "wlan rst"); | 96 | "wlan pwr"); |
| 103 | if (res) | 97 | if (res) |
| 104 | return res; | 98 | return res; |
| 105 | 99 | ||
| @@ -108,6 +102,23 @@ static int omap3_sbc_t3730_twl_callback(struct device *dev, | |||
| 108 | return 0; | 102 | return 0; |
| 109 | } | 103 | } |
| 110 | 104 | ||
| 105 | static void __init omap3_sbc_t3x_usb_hub_init(int gpio, char *hub_name) | ||
| 106 | { | ||
| 107 | int err = gpio_request_one(gpio, GPIOF_OUT_INIT_LOW, hub_name); | ||
| 108 | |||
| 109 | if (err) { | ||
| 110 | pr_err("SBC-T3x: %s reset gpio request failed: %d\n", | ||
| 111 | hub_name, err); | ||
| 112 | return; | ||
| 113 | } | ||
| 114 | |||
| 115 | gpio_export(gpio, 0); | ||
| 116 | |||
| 117 | udelay(10); | ||
| 118 | gpio_set_value(gpio, 1); | ||
| 119 | msleep(1); | ||
| 120 | } | ||
| 121 | |||
| 111 | static void __init omap3_sbc_t3730_twl_init(void) | 122 | static void __init omap3_sbc_t3730_twl_init(void) |
| 112 | { | 123 | { |
| 113 | twl_gpio_auxdata.setup = omap3_sbc_t3730_twl_callback; | 124 | twl_gpio_auxdata.setup = omap3_sbc_t3730_twl_callback; |
| @@ -115,10 +126,17 @@ static void __init omap3_sbc_t3730_twl_init(void) | |||
| 115 | 126 | ||
| 116 | static void __init omap3_sbc_t3730_legacy_init(void) | 127 | static void __init omap3_sbc_t3730_legacy_init(void) |
| 117 | { | 128 | { |
| 129 | omap3_sbc_t3x_usb_hub_init(167, "sb-t35 usb hub"); | ||
| 118 | legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 136); | 130 | legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 136); |
| 119 | omap_ads7846_init(1, 57, 0, NULL); | 131 | omap_ads7846_init(1, 57, 0, NULL); |
| 120 | } | 132 | } |
| 121 | 133 | ||
| 134 | static void __init omap3_sbc_t3530_legacy_init(void) | ||
| 135 | { | ||
| 136 | omap3_sbc_t3x_usb_hub_init(167, "sb-t35 usb hub"); | ||
| 137 | omap_ads7846_init(1, 57, 0, NULL); | ||
| 138 | } | ||
| 139 | |||
| 122 | static void __init omap3_igep0020_legacy_init(void) | 140 | static void __init omap3_igep0020_legacy_init(void) |
| 123 | { | 141 | { |
| 124 | omap3_igep2_display_init_of(); | 142 | omap3_igep2_display_init_of(); |
| @@ -160,7 +178,7 @@ static struct emac_platform_data am35xx_emac_pdata = { | |||
| 160 | .interrupt_disable = am35xx_disable_emac_int, | 178 | .interrupt_disable = am35xx_disable_emac_int, |
| 161 | }; | 179 | }; |
| 162 | 180 | ||
| 163 | static void __init am3517_evm_legacy_init(void) | 181 | static void __init am35xx_emac_reset(void) |
| 164 | { | 182 | { |
| 165 | u32 v; | 183 | u32 v; |
| 166 | 184 | ||
| @@ -169,6 +187,43 @@ static void __init am3517_evm_legacy_init(void) | |||
| 169 | omap_ctrl_writel(v, AM35XX_CONTROL_IP_SW_RESET); | 187 | omap_ctrl_writel(v, AM35XX_CONTROL_IP_SW_RESET); |
| 170 | omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); /* OCP barrier */ | 188 | omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); /* OCP barrier */ |
| 171 | } | 189 | } |
| 190 | |||
| 191 | static struct gpio cm_t3517_wlan_gpios[] __initdata = { | ||
| 192 | { 56, GPIOF_OUT_INIT_HIGH, "wlan pwr" }, | ||
| 193 | { 4, GPIOF_OUT_INIT_HIGH, "xcvr noe" }, | ||
| 194 | }; | ||
| 195 | |||
| 196 | static void __init omap3_sbc_t3517_wifi_init(void) | ||
| 197 | { | ||
| 198 | int err = gpio_request_array(cm_t3517_wlan_gpios, | ||
| 199 | ARRAY_SIZE(cm_t3517_wlan_gpios)); | ||
| 200 | if (err) { | ||
| 201 | pr_err("SBC-T3517: wl12xx gpios request failed: %d\n", err); | ||
| 202 | return; | ||
| 203 | } | ||
| 204 | |||
| 205 | gpio_export(cm_t3517_wlan_gpios[0].gpio, 0); | ||
| 206 | gpio_export(cm_t3517_wlan_gpios[1].gpio, 0); | ||
| 207 | |||
| 208 | msleep(100); | ||
| 209 | gpio_set_value(cm_t3517_wlan_gpios[1].gpio, 0); | ||
| 210 | } | ||
| 211 | |||
| 212 | static void __init omap3_sbc_t3517_legacy_init(void) | ||
| 213 | { | ||
| 214 | omap3_sbc_t3x_usb_hub_init(152, "cm-t3517 usb hub"); | ||
| 215 | omap3_sbc_t3x_usb_hub_init(98, "sb-t35 usb hub"); | ||
| 216 | am35xx_emac_reset(); | ||
| 217 | hsmmc2_internal_input_clk(); | ||
| 218 | omap3_sbc_t3517_wifi_init(); | ||
| 219 | legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 145); | ||
| 220 | omap_ads7846_init(1, 57, 0, NULL); | ||
| 221 | } | ||
| 222 | |||
| 223 | static void __init am3517_evm_legacy_init(void) | ||
| 224 | { | ||
| 225 | am35xx_emac_reset(); | ||
| 226 | } | ||
| 172 | #endif /* CONFIG_ARCH_OMAP3 */ | 227 | #endif /* CONFIG_ARCH_OMAP3 */ |
| 173 | 228 | ||
| 174 | #ifdef CONFIG_ARCH_OMAP4 | 229 | #ifdef CONFIG_ARCH_OMAP4 |
| @@ -182,15 +237,28 @@ static void __init omap4_sdp_legacy_init(void) | |||
| 182 | static void __init omap4_panda_legacy_init(void) | 237 | static void __init omap4_panda_legacy_init(void) |
| 183 | { | 238 | { |
| 184 | omap4_panda_display_init_of(); | 239 | omap4_panda_display_init_of(); |
| 185 | legacy_init_ehci_clk("auxclk3_ck"); | ||
| 186 | legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 53); | 240 | legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 53); |
| 187 | } | 241 | } |
| 188 | #endif | 242 | #endif |
| 189 | 243 | ||
| 244 | #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) | ||
| 245 | static struct iommu_platform_data omap4_iommu_pdata = { | ||
| 246 | .reset_name = "mmu_cache", | ||
| 247 | .assert_reset = omap_device_assert_hardreset, | ||
| 248 | .deassert_reset = omap_device_deassert_hardreset, | ||
| 249 | }; | ||
| 250 | #endif | ||
| 251 | |||
| 252 | #ifdef CONFIG_SOC_AM33XX | ||
| 253 | static void __init am335x_evmsk_legacy_init(void) | ||
| 254 | { | ||
| 255 | legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 31); | ||
| 256 | } | ||
| 257 | #endif | ||
| 258 | |||
| 190 | #ifdef CONFIG_SOC_OMAP5 | 259 | #ifdef CONFIG_SOC_OMAP5 |
| 191 | static void __init omap5_uevm_legacy_init(void) | 260 | static void __init omap5_uevm_legacy_init(void) |
| 192 | { | 261 | { |
| 193 | legacy_init_ehci_clk("auxclk1_ck"); | ||
| 194 | } | 262 | } |
| 195 | #endif | 263 | #endif |
| 196 | 264 | ||
| @@ -240,6 +308,8 @@ struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { | |||
| 240 | #ifdef CONFIG_ARCH_OMAP3 | 308 | #ifdef CONFIG_ARCH_OMAP3 |
| 241 | OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002030, "48002030.pinmux", &pcs_pdata), | 309 | OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002030, "48002030.pinmux", &pcs_pdata), |
| 242 | OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002a00, "48002a00.pinmux", &pcs_pdata), | 310 | OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002a00, "48002a00.pinmux", &pcs_pdata), |
| 311 | OF_DEV_AUXDATA("ti,omap2-iommu", 0x5d000000, "5d000000.mmu", | ||
| 312 | &omap3_iommu_pdata), | ||
| 243 | /* Only on am3517 */ | 313 | /* Only on am3517 */ |
| 244 | OF_DEV_AUXDATA("ti,davinci_mdio", 0x5c030000, "davinci_mdio.0", NULL), | 314 | OF_DEV_AUXDATA("ti,davinci_mdio", 0x5c030000, "davinci_mdio.0", NULL), |
| 245 | OF_DEV_AUXDATA("ti,am3517-emac", 0x5c000000, "davinci_emac.0", | 315 | OF_DEV_AUXDATA("ti,am3517-emac", 0x5c000000, "davinci_emac.0", |
| @@ -249,6 +319,12 @@ struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { | |||
| 249 | OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a100040, "4a100040.pinmux", &pcs_pdata), | 319 | OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a100040, "4a100040.pinmux", &pcs_pdata), |
| 250 | OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a31e040, "4a31e040.pinmux", &pcs_pdata), | 320 | OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a31e040, "4a31e040.pinmux", &pcs_pdata), |
| 251 | #endif | 321 | #endif |
| 322 | #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) | ||
| 323 | OF_DEV_AUXDATA("ti,omap4-iommu", 0x4a066000, "4a066000.mmu", | ||
| 324 | &omap4_iommu_pdata), | ||
| 325 | OF_DEV_AUXDATA("ti,omap4-iommu", 0x55082000, "55082000.mmu", | ||
| 326 | &omap4_iommu_pdata), | ||
| 327 | #endif | ||
| 252 | { /* sentinel */ }, | 328 | { /* sentinel */ }, |
| 253 | }; | 329 | }; |
| 254 | 330 | ||
| @@ -258,6 +334,8 @@ struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { | |||
| 258 | */ | 334 | */ |
| 259 | static struct pdata_init pdata_quirks[] __initdata = { | 335 | static struct pdata_init pdata_quirks[] __initdata = { |
| 260 | #ifdef CONFIG_ARCH_OMAP3 | 336 | #ifdef CONFIG_ARCH_OMAP3 |
| 337 | { "compulab,omap3-sbc-t3517", omap3_sbc_t3517_legacy_init, }, | ||
| 338 | { "compulab,omap3-sbc-t3530", omap3_sbc_t3530_legacy_init, }, | ||
| 261 | { "compulab,omap3-sbc-t3730", omap3_sbc_t3730_legacy_init, }, | 339 | { "compulab,omap3-sbc-t3730", omap3_sbc_t3730_legacy_init, }, |
| 262 | { "nokia,omap3-n900", hsmmc2_internal_input_clk, }, | 340 | { "nokia,omap3-n900", hsmmc2_internal_input_clk, }, |
| 263 | { "nokia,omap3-n9", hsmmc2_internal_input_clk, }, | 341 | { "nokia,omap3-n9", hsmmc2_internal_input_clk, }, |
| @@ -271,6 +349,9 @@ static struct pdata_init pdata_quirks[] __initdata = { | |||
| 271 | { "ti,omap4-sdp", omap4_sdp_legacy_init, }, | 349 | { "ti,omap4-sdp", omap4_sdp_legacy_init, }, |
| 272 | { "ti,omap4-panda", omap4_panda_legacy_init, }, | 350 | { "ti,omap4-panda", omap4_panda_legacy_init, }, |
| 273 | #endif | 351 | #endif |
| 352 | #ifdef CONFIG_SOC_AM33XX | ||
| 353 | { "ti,am335x-evmsk", am335x_evmsk_legacy_init, }, | ||
| 354 | #endif | ||
| 274 | #ifdef CONFIG_SOC_OMAP5 | 355 | #ifdef CONFIG_SOC_OMAP5 |
| 275 | { "ti,omap5-uevm", omap5_uevm_legacy_init, }, | 356 | { "ti,omap5-uevm", omap5_uevm_legacy_init, }, |
| 276 | #endif | 357 | #endif |
diff --git a/arch/arm/mach-orion5x/include/mach/timex.h b/arch/arm/mach-orion5x/include/mach/timex.h deleted file mode 100644 index 4c69820e0810..000000000000 --- a/arch/arm/mach-orion5x/include/mach/timex.h +++ /dev/null | |||
| @@ -1,11 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-orion5x/include/mach/timex.h | ||
| 3 | * | ||
| 4 | * Tzachi Perelstein <tzachi@marvell.com> | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #define CLOCK_TICK_RATE (100 * HZ) | ||
diff --git a/arch/arm/mach-pxa/include/mach/timex.h b/arch/arm/mach-pxa/include/mach/timex.h deleted file mode 100644 index af6760a50e1a..000000000000 --- a/arch/arm/mach-pxa/include/mach/timex.h +++ /dev/null | |||
| @@ -1,34 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-pxa/include/mach/timex.h | ||
| 3 | * | ||
| 4 | * Author: Nicolas Pitre | ||
| 5 | * Created: Jun 15, 2001 | ||
| 6 | * Copyright: MontaVista Software Inc. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | /* Various drivers are still using the constant of CLOCK_TICK_RATE, for | ||
| 14 | * those drivers to at least work, the definition is provided here. | ||
| 15 | * | ||
| 16 | * NOTE: this is no longer accurate when multiple processors and boards | ||
| 17 | * are selected, newer drivers should not depend on this any more. Use | ||
| 18 | * either the clocksource/clockevent or get this at run-time by calling | ||
| 19 | * get_clock_tick_rate() (as defined in generic.c). | ||
| 20 | */ | ||
| 21 | |||
| 22 | #if defined(CONFIG_PXA25x) | ||
| 23 | /* PXA250/210 timer base */ | ||
| 24 | #define CLOCK_TICK_RATE 3686400 | ||
| 25 | #elif defined(CONFIG_PXA27x) | ||
| 26 | /* PXA27x timer base */ | ||
| 27 | #ifdef CONFIG_MACH_MAINSTONE | ||
| 28 | #define CLOCK_TICK_RATE 3249600 | ||
| 29 | #else | ||
| 30 | #define CLOCK_TICK_RATE 3250000 | ||
| 31 | #endif | ||
| 32 | #else | ||
| 33 | #define CLOCK_TICK_RATE 3250000 | ||
| 34 | #endif | ||
diff --git a/arch/arm/mach-qcom/Kconfig b/arch/arm/mach-qcom/Kconfig new file mode 100644 index 000000000000..a028be234334 --- /dev/null +++ b/arch/arm/mach-qcom/Kconfig | |||
| @@ -0,0 +1,33 @@ | |||
| 1 | config ARCH_QCOM | ||
| 2 | bool "Qualcomm Support" if ARCH_MULTI_V7 | ||
| 3 | select ARCH_REQUIRE_GPIOLIB | ||
| 4 | select ARM_GIC | ||
| 5 | select CLKSRC_OF | ||
| 6 | select GENERIC_CLOCKEVENTS | ||
| 7 | select HAVE_SMP | ||
| 8 | select QCOM_SCM if SMP | ||
| 9 | help | ||
| 10 | Support for Qualcomm's devicetree based systems. | ||
| 11 | |||
| 12 | if ARCH_QCOM | ||
| 13 | |||
| 14 | menu "Qualcomm SoC Selection" | ||
| 15 | |||
| 16 | config ARCH_MSM8X60 | ||
| 17 | bool "Enable support for MSM8X60" | ||
| 18 | select CLKSRC_QCOM | ||
| 19 | |||
| 20 | config ARCH_MSM8960 | ||
| 21 | bool "Enable support for MSM8960" | ||
| 22 | select CLKSRC_QCOM | ||
| 23 | |||
| 24 | config ARCH_MSM8974 | ||
| 25 | bool "Enable support for MSM8974" | ||
| 26 | select HAVE_ARM_ARCH_TIMER | ||
| 27 | |||
| 28 | endmenu | ||
| 29 | |||
| 30 | config QCOM_SCM | ||
| 31 | bool | ||
| 32 | |||
| 33 | endif | ||
diff --git a/arch/arm/mach-qcom/Makefile b/arch/arm/mach-qcom/Makefile new file mode 100644 index 000000000000..8f756ae1ae31 --- /dev/null +++ b/arch/arm/mach-qcom/Makefile | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | obj-y := board.o | ||
| 2 | obj-$(CONFIG_SMP) += platsmp.o | ||
| 3 | obj-$(CONFIG_QCOM_SCM) += scm.o scm-boot.o | ||
| 4 | |||
| 5 | CFLAGS_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1) | ||
diff --git a/arch/arm/mach-msm/board-dt.c b/arch/arm/mach-qcom/board.c index 1f11d93e700e..830f69c3a3ce 100644 --- a/arch/arm/mach-msm/board-dt.c +++ b/arch/arm/mach-qcom/board.c | |||
| @@ -1,4 +1,4 @@ | |||
| 1 | /* Copyright (c) 2010-2012,2013 The Linux Foundation. All rights reserved. | 1 | /* Copyright (c) 2010-2014 The Linux Foundation. All rights reserved. |
| 2 | * | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify | 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and | 4 | * it under the terms of the GNU General Public License version 2 and |
| @@ -17,10 +17,9 @@ | |||
| 17 | #include <asm/mach/arch.h> | 17 | #include <asm/mach/arch.h> |
| 18 | #include <asm/mach/map.h> | 18 | #include <asm/mach/map.h> |
| 19 | 19 | ||
| 20 | #include "common.h" | 20 | extern struct smp_operations qcom_smp_ops; |
| 21 | 21 | ||
| 22 | static const char * const msm_dt_match[] __initconst = { | 22 | static const char * const qcom_dt_match[] __initconst = { |
| 23 | "qcom,msm8660-fluid", | ||
| 24 | "qcom,msm8660-surf", | 23 | "qcom,msm8660-surf", |
| 25 | "qcom,msm8960-cdp", | 24 | "qcom,msm8960-cdp", |
| 26 | NULL | 25 | NULL |
| @@ -31,11 +30,11 @@ static const char * const apq8074_dt_match[] __initconst = { | |||
| 31 | NULL | 30 | NULL |
| 32 | }; | 31 | }; |
| 33 | 32 | ||
| 34 | DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)") | 33 | DT_MACHINE_START(QCOM_DT, "Qualcomm (Flattened Device Tree)") |
| 35 | .smp = smp_ops(msm_smp_ops), | 34 | .smp = smp_ops(qcom_smp_ops), |
| 36 | .dt_compat = msm_dt_match, | 35 | .dt_compat = qcom_dt_match, |
| 37 | MACHINE_END | 36 | MACHINE_END |
| 38 | 37 | ||
| 39 | DT_MACHINE_START(APQ_DT, "Qualcomm MSM (Flattened Device Tree)") | 38 | DT_MACHINE_START(APQ_DT, "Qualcomm (Flattened Device Tree)") |
| 40 | .dt_compat = apq8074_dt_match, | 39 | .dt_compat = apq8074_dt_match, |
| 41 | MACHINE_END | 40 | MACHINE_END |
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-qcom/platsmp.c index f10a1f58fde9..9c53ea70550d 100644 --- a/arch/arm/mach-msm/platsmp.c +++ b/arch/arm/mach-qcom/platsmp.c | |||
| @@ -2,6 +2,7 @@ | |||
| 2 | * Copyright (C) 2002 ARM Ltd. | 2 | * Copyright (C) 2002 ARM Ltd. |
| 3 | * All Rights Reserved | 3 | * All Rights Reserved |
| 4 | * Copyright (c) 2010, Code Aurora Forum. All rights reserved. | 4 | * Copyright (c) 2010, Code Aurora Forum. All rights reserved. |
| 5 | * Copyright (c) 2014 The Linux Foundation. All rights reserved. | ||
| 5 | * | 6 | * |
| 6 | * This program is free software; you can redistribute it and/or modify | 7 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as | 8 | * it under the terms of the GNU General Public License version 2 as |
| @@ -12,42 +13,38 @@ | |||
| 12 | #include <linux/errno.h> | 13 | #include <linux/errno.h> |
| 13 | #include <linux/delay.h> | 14 | #include <linux/delay.h> |
| 14 | #include <linux/device.h> | 15 | #include <linux/device.h> |
| 15 | #include <linux/jiffies.h> | ||
| 16 | #include <linux/smp.h> | 16 | #include <linux/smp.h> |
| 17 | #include <linux/io.h> | 17 | #include <linux/io.h> |
| 18 | 18 | ||
| 19 | #include <asm/cacheflush.h> | ||
| 20 | #include <asm/cputype.h> | 19 | #include <asm/cputype.h> |
| 21 | #include <asm/mach-types.h> | ||
| 22 | #include <asm/smp_plat.h> | 20 | #include <asm/smp_plat.h> |
| 23 | 21 | ||
| 24 | #include "scm-boot.h" | 22 | #include "scm-boot.h" |
| 25 | #include "common.h" | ||
| 26 | 23 | ||
| 27 | #define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0 | 24 | #define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0 |
| 28 | #define SCSS_CPU1CORE_RESET 0xD80 | 25 | #define SCSS_CPU1CORE_RESET 0xD80 |
| 29 | #define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64 | 26 | #define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64 |
| 30 | 27 | ||
| 31 | extern void msm_secondary_startup(void); | 28 | extern void secondary_startup(void); |
| 32 | 29 | ||
| 33 | static DEFINE_SPINLOCK(boot_lock); | 30 | static DEFINE_SPINLOCK(boot_lock); |
| 34 | 31 | ||
| 32 | #ifdef CONFIG_HOTPLUG_CPU | ||
| 33 | static void __ref qcom_cpu_die(unsigned int cpu) | ||
| 34 | { | ||
| 35 | wfi(); | ||
| 36 | } | ||
| 37 | #endif | ||
| 38 | |||
| 35 | static inline int get_core_count(void) | 39 | static inline int get_core_count(void) |
| 36 | { | 40 | { |
| 37 | /* 1 + the PART[1:0] field of MIDR */ | 41 | /* 1 + the PART[1:0] field of MIDR */ |
| 38 | return ((read_cpuid_id() >> 4) & 3) + 1; | 42 | return ((read_cpuid_id() >> 4) & 3) + 1; |
| 39 | } | 43 | } |
| 40 | 44 | ||
| 41 | static void msm_secondary_init(unsigned int cpu) | 45 | static void qcom_secondary_init(unsigned int cpu) |
| 42 | { | 46 | { |
| 43 | /* | 47 | /* |
| 44 | * let the primary processor know we're out of the | ||
| 45 | * pen, then head off into the C entry point | ||
| 46 | */ | ||
| 47 | pen_release = -1; | ||
| 48 | smp_wmb(); | ||
| 49 | |||
| 50 | /* | ||
| 51 | * Synchronise with the boot thread. | 48 | * Synchronise with the boot thread. |
| 52 | */ | 49 | */ |
| 53 | spin_lock(&boot_lock); | 50 | spin_lock(&boot_lock); |
| @@ -57,7 +54,7 @@ static void msm_secondary_init(unsigned int cpu) | |||
| 57 | static void prepare_cold_cpu(unsigned int cpu) | 54 | static void prepare_cold_cpu(unsigned int cpu) |
| 58 | { | 55 | { |
| 59 | int ret; | 56 | int ret; |
| 60 | ret = scm_set_boot_addr(virt_to_phys(msm_secondary_startup), | 57 | ret = scm_set_boot_addr(virt_to_phys(secondary_startup), |
| 61 | SCM_FLAG_COLDBOOT_CPU1); | 58 | SCM_FLAG_COLDBOOT_CPU1); |
| 62 | if (ret == 0) { | 59 | if (ret == 0) { |
| 63 | void __iomem *sc1_base_ptr; | 60 | void __iomem *sc1_base_ptr; |
| @@ -73,9 +70,8 @@ static void prepare_cold_cpu(unsigned int cpu) | |||
| 73 | "address\n"); | 70 | "address\n"); |
| 74 | } | 71 | } |
| 75 | 72 | ||
| 76 | static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle) | 73 | static int qcom_boot_secondary(unsigned int cpu, struct task_struct *idle) |
| 77 | { | 74 | { |
| 78 | unsigned long timeout; | ||
| 79 | static int cold_boot_done; | 75 | static int cold_boot_done; |
| 80 | 76 | ||
| 81 | /* Only need to bring cpu out of reset this way once */ | 77 | /* Only need to bring cpu out of reset this way once */ |
| @@ -91,39 +87,19 @@ static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle) | |||
| 91 | spin_lock(&boot_lock); | 87 | spin_lock(&boot_lock); |
| 92 | 88 | ||
| 93 | /* | 89 | /* |
| 94 | * The secondary processor is waiting to be released from | ||
| 95 | * the holding pen - release it, then wait for it to flag | ||
| 96 | * that it has been released by resetting pen_release. | ||
| 97 | * | ||
| 98 | * Note that "pen_release" is the hardware CPU ID, whereas | ||
| 99 | * "cpu" is Linux's internal ID. | ||
| 100 | */ | ||
| 101 | pen_release = cpu_logical_map(cpu); | ||
| 102 | sync_cache_w(&pen_release); | ||
| 103 | |||
| 104 | /* | ||
| 105 | * Send the secondary CPU a soft interrupt, thereby causing | 90 | * Send the secondary CPU a soft interrupt, thereby causing |
| 106 | * the boot monitor to read the system wide flags register, | 91 | * the boot monitor to read the system wide flags register, |
| 107 | * and branch to the address found there. | 92 | * and branch to the address found there. |
| 108 | */ | 93 | */ |
| 109 | arch_send_wakeup_ipi_mask(cpumask_of(cpu)); | 94 | arch_send_wakeup_ipi_mask(cpumask_of(cpu)); |
| 110 | 95 | ||
| 111 | timeout = jiffies + (1 * HZ); | ||
| 112 | while (time_before(jiffies, timeout)) { | ||
| 113 | smp_rmb(); | ||
| 114 | if (pen_release == -1) | ||
| 115 | break; | ||
| 116 | |||
| 117 | udelay(10); | ||
| 118 | } | ||
| 119 | |||
| 120 | /* | 96 | /* |
| 121 | * now the secondary core is starting up let it run its | 97 | * now the secondary core is starting up let it run its |
| 122 | * calibrations, then wait for it to finish | 98 | * calibrations, then wait for it to finish |
| 123 | */ | 99 | */ |
| 124 | spin_unlock(&boot_lock); | 100 | spin_unlock(&boot_lock); |
| 125 | 101 | ||
| 126 | return pen_release != -1 ? -ENOSYS : 0; | 102 | return 0; |
| 127 | } | 103 | } |
| 128 | 104 | ||
| 129 | /* | 105 | /* |
| @@ -132,7 +108,7 @@ static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle) | |||
| 132 | * does not support the ARM SCU, so just set the possible cpu mask to | 108 | * does not support the ARM SCU, so just set the possible cpu mask to |
| 133 | * NR_CPUS. | 109 | * NR_CPUS. |
| 134 | */ | 110 | */ |
| 135 | static void __init msm_smp_init_cpus(void) | 111 | static void __init qcom_smp_init_cpus(void) |
| 136 | { | 112 | { |
| 137 | unsigned int i, ncores = get_core_count(); | 113 | unsigned int i, ncores = get_core_count(); |
| 138 | 114 | ||
| @@ -146,16 +122,16 @@ static void __init msm_smp_init_cpus(void) | |||
| 146 | set_cpu_possible(i, true); | 122 | set_cpu_possible(i, true); |
| 147 | } | 123 | } |
| 148 | 124 | ||
| 149 | static void __init msm_smp_prepare_cpus(unsigned int max_cpus) | 125 | static void __init qcom_smp_prepare_cpus(unsigned int max_cpus) |
| 150 | { | 126 | { |
| 151 | } | 127 | } |
| 152 | 128 | ||
| 153 | struct smp_operations msm_smp_ops __initdata = { | 129 | struct smp_operations qcom_smp_ops __initdata = { |
| 154 | .smp_init_cpus = msm_smp_init_cpus, | 130 | .smp_init_cpus = qcom_smp_init_cpus, |
| 155 | .smp_prepare_cpus = msm_smp_prepare_cpus, | 131 | .smp_prepare_cpus = qcom_smp_prepare_cpus, |
| 156 | .smp_secondary_init = msm_secondary_init, | 132 | .smp_secondary_init = qcom_secondary_init, |
| 157 | .smp_boot_secondary = msm_boot_secondary, | 133 | .smp_boot_secondary = qcom_boot_secondary, |
| 158 | #ifdef CONFIG_HOTPLUG_CPU | 134 | #ifdef CONFIG_HOTPLUG_CPU |
| 159 | .cpu_die = msm_cpu_die, | 135 | .cpu_die = qcom_cpu_die, |
| 160 | #endif | 136 | #endif |
| 161 | }; | 137 | }; |
diff --git a/arch/arm/mach-msm/scm-boot.c b/arch/arm/mach-qcom/scm-boot.c index 45cee3e469a5..45cee3e469a5 100644 --- a/arch/arm/mach-msm/scm-boot.c +++ b/arch/arm/mach-qcom/scm-boot.c | |||
diff --git a/arch/arm/mach-msm/scm-boot.h b/arch/arm/mach-qcom/scm-boot.h index 7be32ff5d687..7be32ff5d687 100644 --- a/arch/arm/mach-msm/scm-boot.h +++ b/arch/arm/mach-qcom/scm-boot.h | |||
diff --git a/arch/arm/mach-msm/scm.c b/arch/arm/mach-qcom/scm.c index c536fd6bf827..c536fd6bf827 100644 --- a/arch/arm/mach-msm/scm.c +++ b/arch/arm/mach-qcom/scm.c | |||
diff --git a/arch/arm/mach-msm/scm.h b/arch/arm/mach-qcom/scm.h index 00b31ea58f29..00b31ea58f29 100644 --- a/arch/arm/mach-msm/scm.h +++ b/arch/arm/mach-qcom/scm.h | |||
diff --git a/arch/arm/mach-realview/include/mach/timex.h b/arch/arm/mach-realview/include/mach/timex.h deleted file mode 100644 index 4eeb069373c2..000000000000 --- a/arch/arm/mach-realview/include/mach/timex.h +++ /dev/null | |||
| @@ -1,23 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-realview/include/mach/timex.h | ||
| 3 | * | ||
| 4 | * RealView architecture timex specifications | ||
| 5 | * | ||
| 6 | * Copyright (C) 2003 ARM Limited | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License | ||
| 19 | * along with this program; if not, write to the Free Software | ||
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 21 | */ | ||
| 22 | |||
| 23 | #define CLOCK_TICK_RATE (50000000 / 16) | ||
diff --git a/arch/arm/mach-rpc/include/mach/timex.h b/arch/arm/mach-rpc/include/mach/timex.h deleted file mode 100644 index dd75e7387bbe..000000000000 --- a/arch/arm/mach-rpc/include/mach/timex.h +++ /dev/null | |||
| @@ -1,17 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-rpc/include/mach/timex.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1997, 1998 Russell King | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * RiscPC architecture timex specifications | ||
| 11 | */ | ||
| 12 | |||
| 13 | /* | ||
| 14 | * On the RiscPC, the clock ticks at 2MHz. | ||
| 15 | */ | ||
| 16 | #define CLOCK_TICK_RATE 2000000 | ||
| 17 | |||
diff --git a/arch/arm/mach-rpc/time.c b/arch/arm/mach-rpc/time.c index 9a6def14df01..99363ae5cac7 100644 --- a/arch/arm/mach-rpc/time.c +++ b/arch/arm/mach-rpc/time.c | |||
| @@ -24,6 +24,9 @@ | |||
| 24 | 24 | ||
| 25 | #include <asm/mach/time.h> | 25 | #include <asm/mach/time.h> |
| 26 | 26 | ||
| 27 | #define RPC_CLOCK_FREQ 2000000 | ||
| 28 | #define RPC_LATCH DIV_ROUND_CLOSEST(RPC_CLOCK_FREQ, HZ) | ||
| 29 | |||
| 27 | static u32 ioc_timer_gettimeoffset(void) | 30 | static u32 ioc_timer_gettimeoffset(void) |
| 28 | { | 31 | { |
| 29 | unsigned int count1, count2, status; | 32 | unsigned int count1, count2, status; |
| @@ -46,23 +49,23 @@ static u32 ioc_timer_gettimeoffset(void) | |||
| 46 | * and count2. | 49 | * and count2. |
| 47 | */ | 50 | */ |
| 48 | if (status & (1 << 5)) | 51 | if (status & (1 << 5)) |
| 49 | offset -= LATCH; | 52 | offset -= RPC_LATCH; |
| 50 | } else if (count2 > count1) { | 53 | } else if (count2 > count1) { |
| 51 | /* | 54 | /* |
| 52 | * We have just had another interrupt between reading | 55 | * We have just had another interrupt between reading |
| 53 | * count1 and count2. | 56 | * count1 and count2. |
| 54 | */ | 57 | */ |
| 55 | offset -= LATCH; | 58 | offset -= RPC_LATCH; |
| 56 | } | 59 | } |
| 57 | 60 | ||
| 58 | offset = (LATCH - offset) * (tick_nsec / 1000); | 61 | offset = (RPC_LATCH - offset) * (tick_nsec / 1000); |
| 59 | return ((offset + LATCH/2) / LATCH) * 1000; | 62 | return DIV_ROUND_CLOSEST(offset, RPC_LATCH) * 1000; |
| 60 | } | 63 | } |
| 61 | 64 | ||
| 62 | void __init ioctime_init(void) | 65 | void __init ioctime_init(void) |
| 63 | { | 66 | { |
| 64 | ioc_writeb(LATCH & 255, IOC_T0LTCHL); | 67 | ioc_writeb(RPC_LATCH & 255, IOC_T0LTCHL); |
| 65 | ioc_writeb(LATCH >> 8, IOC_T0LTCHH); | 68 | ioc_writeb(RPC_LATCH >> 8, IOC_T0LTCHH); |
| 66 | ioc_writeb(0, IOC_T0GO); | 69 | ioc_writeb(0, IOC_T0GO); |
| 67 | } | 70 | } |
| 68 | 71 | ||
diff --git a/arch/arm/mach-s3c24xx/include/mach/timex.h b/arch/arm/mach-s3c24xx/include/mach/timex.h deleted file mode 100644 index fe9ca1ffd51b..000000000000 --- a/arch/arm/mach-s3c24xx/include/mach/timex.h +++ /dev/null | |||
| @@ -1,24 +0,0 @@ | |||
| 1 | /* arch/arm/mach-s3c2410/include/mach/timex.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2003-2005 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * | ||
| 6 | * S3C2410 - time parameters | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_TIMEX_H | ||
| 14 | #define __ASM_ARCH_TIMEX_H | ||
| 15 | |||
| 16 | /* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it | ||
| 17 | * a variable is useless. It seems as long as we make our timers an | ||
| 18 | * exact multiple of HZ, any value that makes a 1->1 correspondence | ||
| 19 | * for the time conversion functions to/from jiffies is acceptable. | ||
| 20 | */ | ||
| 21 | |||
| 22 | #define CLOCK_TICK_RATE 12000000 | ||
| 23 | |||
| 24 | #endif /* __ASM_ARCH_TIMEX_H */ | ||
diff --git a/arch/arm/mach-s3c64xx/include/mach/timex.h b/arch/arm/mach-s3c64xx/include/mach/timex.h deleted file mode 100644 index fb2e8cd40829..000000000000 --- a/arch/arm/mach-s3c64xx/include/mach/timex.h +++ /dev/null | |||
| @@ -1,24 +0,0 @@ | |||
| 1 | /* arch/arm/mach-s3c64xx/include/mach/timex.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2003-2005 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * | ||
| 6 | * S3C6400 - time parameters | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_TIMEX_H | ||
| 14 | #define __ASM_ARCH_TIMEX_H | ||
| 15 | |||
| 16 | /* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it | ||
| 17 | * a variable is useless. It seems as long as we make our timers an | ||
| 18 | * exact multiple of HZ, any value that makes a 1->1 correspondence | ||
| 19 | * for the time conversion functions to/from jiffies is acceptable. | ||
| 20 | */ | ||
| 21 | |||
| 22 | #define CLOCK_TICK_RATE 12000000 | ||
| 23 | |||
| 24 | #endif /* __ASM_ARCH_TIMEX_H */ | ||
diff --git a/arch/arm/mach-s5p64x0/include/mach/timex.h b/arch/arm/mach-s5p64x0/include/mach/timex.h deleted file mode 100644 index 4b91faa195a8..000000000000 --- a/arch/arm/mach-s5p64x0/include/mach/timex.h +++ /dev/null | |||
| @@ -1,27 +0,0 @@ | |||
| 1 | /* linux/arch/arm/mach-s5p64x0/include/mach/timex.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com | ||
| 5 | * | ||
| 6 | * Copyright (c) 2003-2005 Simtec Electronics | ||
| 7 | * Ben Dooks <ben@simtec.co.uk> | ||
| 8 | * | ||
| 9 | * S5P64X0 - time parameters | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License version 2 as | ||
| 13 | * published by the Free Software Foundation. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef __ASM_ARCH_TIMEX_H | ||
| 17 | #define __ASM_ARCH_TIMEX_H | ||
| 18 | |||
| 19 | /* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it | ||
| 20 | * a variable is useless. It seems as long as we make our timers an | ||
| 21 | * exact multiple of HZ, any value that makes a 1->1 correspondence | ||
| 22 | * for the time conversion functions to/from jiffies is acceptable. | ||
| 23 | */ | ||
| 24 | |||
| 25 | #define CLOCK_TICK_RATE 12000000 | ||
| 26 | |||
| 27 | #endif /* __ASM_ARCH_TIMEX_H */ | ||
diff --git a/arch/arm/mach-s5pc100/include/mach/timex.h b/arch/arm/mach-s5pc100/include/mach/timex.h deleted file mode 100644 index 47ffb17aff96..000000000000 --- a/arch/arm/mach-s5pc100/include/mach/timex.h +++ /dev/null | |||
| @@ -1,24 +0,0 @@ | |||
| 1 | /* arch/arm/mach-s5pc100/include/mach/timex.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2003-2005 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * | ||
| 6 | * S3C6400 - time parameters | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_TIMEX_H | ||
| 14 | #define __ASM_ARCH_TIMEX_H | ||
| 15 | |||
| 16 | /* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it | ||
| 17 | * a variable is useless. It seems as long as we make our timers an | ||
| 18 | * exact multiple of HZ, any value that makes a 1->1 correspondence | ||
| 19 | * for the time conversion functions to/from jiffies is acceptable. | ||
| 20 | */ | ||
| 21 | |||
| 22 | #define CLOCK_TICK_RATE 12000000 | ||
| 23 | |||
| 24 | #endif /* __ASM_ARCH_TIMEX_H */ | ||
diff --git a/arch/arm/mach-s5pv210/include/mach/timex.h b/arch/arm/mach-s5pv210/include/mach/timex.h deleted file mode 100644 index 73dc85496a83..000000000000 --- a/arch/arm/mach-s5pv210/include/mach/timex.h +++ /dev/null | |||
| @@ -1,29 +0,0 @@ | |||
| 1 | /* linux/arch/arm/mach-s5pv210/include/mach/timex.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2003-2010 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * | ||
| 6 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
| 7 | * http://www.samsung.com/ | ||
| 8 | * | ||
| 9 | * Based on arch/arm/mach-s5p6442/include/mach/timex.h | ||
| 10 | * | ||
| 11 | * S5PV210 - time parameters | ||
| 12 | * | ||
| 13 | * This program is free software; you can redistribute it and/or modify | ||
| 14 | * it under the terms of the GNU General Public License version 2 as | ||
| 15 | * published by the Free Software Foundation. | ||
| 16 | */ | ||
| 17 | |||
| 18 | #ifndef __ASM_ARCH_TIMEX_H | ||
| 19 | #define __ASM_ARCH_TIMEX_H __FILE__ | ||
| 20 | |||
| 21 | /* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it | ||
| 22 | * a variable is useless. It seems as long as we make our timers an | ||
| 23 | * exact multiple of HZ, any value that makes a 1->1 correspondence | ||
| 24 | * for the time conversion functions to/from jiffies is acceptable. | ||
| 25 | */ | ||
| 26 | |||
| 27 | #define CLOCK_TICK_RATE 12000000 | ||
| 28 | |||
| 29 | #endif /* __ASM_ARCH_TIMEX_H */ | ||
diff --git a/arch/arm/mach-sa1100/include/mach/timex.h b/arch/arm/mach-sa1100/include/mach/timex.h deleted file mode 100644 index 7a5d017b58b3..000000000000 --- a/arch/arm/mach-sa1100/include/mach/timex.h +++ /dev/null | |||
| @@ -1,12 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-sa1100/include/mach/timex.h | ||
| 3 | * | ||
| 4 | * SA1100 architecture timex specifications | ||
| 5 | * | ||
| 6 | * Copyright (C) 1998 | ||
| 7 | */ | ||
| 8 | |||
| 9 | /* | ||
| 10 | * SA1100 timer | ||
| 11 | */ | ||
| 12 | #define CLOCK_TICK_RATE 3686400 | ||
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c index 6fd4acb8f187..7aaac005e036 100644 --- a/arch/arm/mach-sa1100/time.c +++ b/arch/arm/mach-sa1100/time.c | |||
| @@ -9,6 +9,7 @@ | |||
| 9 | * | 9 | * |
| 10 | */ | 10 | */ |
| 11 | #include <linux/init.h> | 11 | #include <linux/init.h> |
| 12 | #include <linux/kernel.h> | ||
| 12 | #include <linux/errno.h> | 13 | #include <linux/errno.h> |
| 13 | #include <linux/interrupt.h> | 14 | #include <linux/interrupt.h> |
| 14 | #include <linux/irq.h> | 15 | #include <linux/irq.h> |
| @@ -20,6 +21,9 @@ | |||
| 20 | #include <mach/hardware.h> | 21 | #include <mach/hardware.h> |
| 21 | #include <mach/irqs.h> | 22 | #include <mach/irqs.h> |
| 22 | 23 | ||
| 24 | #define SA1100_CLOCK_FREQ 3686400 | ||
| 25 | #define SA1100_LATCH DIV_ROUND_CLOSEST(SA1100_CLOCK_FREQ, HZ) | ||
| 26 | |||
| 23 | static u64 notrace sa1100_read_sched_clock(void) | 27 | static u64 notrace sa1100_read_sched_clock(void) |
| 24 | { | 28 | { |
| 25 | return readl_relaxed(OSCR); | 29 | return readl_relaxed(OSCR); |
| @@ -93,7 +97,7 @@ static void sa1100_timer_resume(struct clock_event_device *cedev) | |||
| 93 | /* | 97 | /* |
| 94 | * OSMR0 is the system timer: make sure OSCR is sufficiently behind | 98 | * OSMR0 is the system timer: make sure OSCR is sufficiently behind |
| 95 | */ | 99 | */ |
| 96 | writel_relaxed(OSMR0 - LATCH, OSCR); | 100 | writel_relaxed(OSMR0 - SA1100_LATCH, OSCR); |
| 97 | } | 101 | } |
| 98 | #else | 102 | #else |
| 99 | #define sa1100_timer_suspend NULL | 103 | #define sa1100_timer_suspend NULL |
| @@ -128,7 +132,7 @@ void __init sa1100_timer_init(void) | |||
| 128 | 132 | ||
| 129 | setup_irq(IRQ_OST0, &sa1100_timer_irq); | 133 | setup_irq(IRQ_OST0, &sa1100_timer_irq); |
| 130 | 134 | ||
| 131 | clocksource_mmio_init(OSCR, "oscr", CLOCK_TICK_RATE, 200, 32, | 135 | clocksource_mmio_init(OSCR, "oscr", SA1100_CLOCK_FREQ, 200, 32, |
| 132 | clocksource_mmio_readl_up); | 136 | clocksource_mmio_readl_up); |
| 133 | clockevents_config_and_register(&ckevt_sa1100_osmr0, 3686400, | 137 | clockevents_config_and_register(&ckevt_sa1100_osmr0, 3686400, |
| 134 | MIN_OSCR_DELTA * 2, 0x7fffffff); | 138 | MIN_OSCR_DELTA * 2, 0x7fffffff); |
diff --git a/arch/arm/mach-shmobile/include/mach/timex.h b/arch/arm/mach-shmobile/include/mach/timex.h deleted file mode 100644 index ae0d8d825c23..000000000000 --- a/arch/arm/mach-shmobile/include/mach/timex.h +++ /dev/null | |||
| @@ -1,6 +0,0 @@ | |||
| 1 | #ifndef __ASM_MACH_TIMEX_H | ||
| 2 | #define __ASM_MACH_TIMEX_H | ||
| 3 | |||
| 4 | #define CLOCK_TICK_RATE 1193180 /* unused i8253 PIT value */ | ||
| 5 | |||
| 6 | #endif /* __ASM_MACH_TIMEX_H */ | ||
diff --git a/arch/arm/mach-spear/include/mach/timex.h b/arch/arm/mach-spear/include/mach/timex.h deleted file mode 100644 index ef95e5b780bd..000000000000 --- a/arch/arm/mach-spear/include/mach/timex.h +++ /dev/null | |||
| @@ -1,19 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-spear/include/plat/timex.h | ||
| 3 | * | ||
| 4 | * SPEAr platform specific timex definitions | ||
| 5 | * | ||
| 6 | * Copyright (C) 2009 ST Microelectronics | ||
| 7 | * Viresh Kumar <viresh.linux@gmail.com> | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __PLAT_TIMEX_H | ||
| 15 | #define __PLAT_TIMEX_H | ||
| 16 | |||
| 17 | #define CLOCK_TICK_RATE 48000000 | ||
| 18 | |||
| 19 | #endif /* __PLAT_TIMEX_H */ | ||
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index 0034d2cd6973..b2019dc50e40 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig | |||
| @@ -73,11 +73,6 @@ config UX500_AUTO_PLATFORM | |||
| 73 | a working kernel. If everything else is disabled, this | 73 | a working kernel. If everything else is disabled, this |
| 74 | automatically enables MACH_MOP500. | 74 | automatically enables MACH_MOP500. |
| 75 | 75 | ||
| 76 | config MACH_UX500_DT | ||
| 77 | bool "Generic U8500 support using device tree" | ||
| 78 | depends on MACH_MOP500 | ||
| 79 | select USE_OF | ||
| 80 | |||
| 81 | endmenu | 76 | endmenu |
| 82 | 77 | ||
| 83 | config UX500_DEBUG_UART | 78 | config UX500_DEBUG_UART |
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile index d05ba759da30..de544aabf292 100644 --- a/arch/arm/mach-ux500/Makefile +++ b/arch/arm/mach-ux500/Makefile | |||
| @@ -7,7 +7,6 @@ obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o | |||
| 7 | obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o | 7 | obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o |
| 8 | obj-$(CONFIG_MACH_MOP500) += board-mop500-sdi.o \ | 8 | obj-$(CONFIG_MACH_MOP500) += board-mop500-sdi.o \ |
| 9 | board-mop500-regulators.o \ | 9 | board-mop500-regulators.o \ |
| 10 | board-mop500-pins.o \ | ||
| 11 | board-mop500-audio.o | 10 | board-mop500-audio.o |
| 12 | obj-$(CONFIG_SMP) += platsmp.o headsmp.o | 11 | obj-$(CONFIG_SMP) += platsmp.o headsmp.o |
| 13 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o | 12 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o |
diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c index 9309ad4cbd09..b2a0899e7453 100644 --- a/arch/arm/mach-ux500/board-mop500-audio.c +++ b/arch/arm/mach-ux500/board-mop500-audio.c | |||
| @@ -9,7 +9,6 @@ | |||
| 9 | #include <linux/gpio.h> | 9 | #include <linux/gpio.h> |
| 10 | #include <linux/platform_data/dma-ste-dma40.h> | 10 | #include <linux/platform_data/dma-ste-dma40.h> |
| 11 | 11 | ||
| 12 | #include "irqs.h" | ||
| 13 | #include <linux/platform_data/asoc-ux500-msp.h> | 12 | #include <linux/platform_data/asoc-ux500-msp.h> |
| 14 | 13 | ||
| 15 | #include "ste-dma40-db8500.h" | 14 | #include "ste-dma40-db8500.h" |
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c deleted file mode 100644 index f63619b69113..000000000000 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ /dev/null | |||
| @@ -1,291 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) ST-Ericsson SA 2010 | ||
| 3 | * | ||
| 4 | * License terms: GNU General Public License (GPL) version 2 | ||
| 5 | */ | ||
| 6 | |||
| 7 | #include <linux/kernel.h> | ||
| 8 | #include <linux/init.h> | ||
| 9 | #include <linux/bug.h> | ||
| 10 | #include <linux/string.h> | ||
| 11 | #include <linux/pinctrl/machine.h> | ||
| 12 | #include <linux/pinctrl/pinconf-generic.h> | ||
| 13 | |||
| 14 | #include <asm/mach-types.h> | ||
| 15 | |||
| 16 | #include "board-mop500.h" | ||
| 17 | |||
| 18 | /* These simply sets bias for pins */ | ||
| 19 | #define BIAS(a,b) static unsigned long a[] = { b } | ||
| 20 | |||
| 21 | BIAS(abx500_out_lo, PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0)); | ||
| 22 | BIAS(abx500_in_pd, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 1)); | ||
| 23 | BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0)); | ||
| 24 | |||
| 25 | #define AB8500_MUX_HOG(group, func) \ | ||
| 26 | PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8500.0", group, func) | ||
| 27 | #define AB8500_PIN_HOG(pin, conf) \ | ||
| 28 | PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8500.0", pin, abx500_##conf) | ||
| 29 | |||
| 30 | #define AB8500_MUX_STATE(group, func, dev, state) \ | ||
| 31 | PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8500.0", group, func) | ||
| 32 | #define AB8500_PIN_STATE(pin, conf, dev, state) \ | ||
| 33 | PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8500.0", pin, abx500_##conf) | ||
| 34 | |||
| 35 | #define AB8505_MUX_HOG(group, func) \ | ||
| 36 | PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8505.0", group, func) | ||
| 37 | #define AB8505_PIN_HOG(pin, conf) \ | ||
| 38 | PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8505.0", pin, abx500_##conf) | ||
| 39 | |||
| 40 | #define AB8505_MUX_STATE(group, func, dev, state) \ | ||
| 41 | PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8505.0", group, func) | ||
| 42 | #define AB8505_PIN_STATE(pin, conf, dev, state) \ | ||
| 43 | PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8505.0", pin, abx500_##conf) | ||
| 44 | |||
| 45 | static struct pinctrl_map __initdata ab8500_pinmap[] = { | ||
| 46 | /* Sysclkreq2 */ | ||
| 47 | AB8500_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.35", PINCTRL_STATE_DEFAULT), | ||
| 48 | AB8500_PIN_STATE("GPIO1_T10", in_nopull, "regulator.35", PINCTRL_STATE_DEFAULT), | ||
| 49 | /* sysclkreq2 disable, mux in gpio configured in input pulldown */ | ||
| 50 | AB8500_MUX_STATE("gpio1_a_1", "gpio", "regulator.35", PINCTRL_STATE_SLEEP), | ||
| 51 | AB8500_PIN_STATE("GPIO1_T10", in_pd, "regulator.35", PINCTRL_STATE_SLEEP), | ||
| 52 | |||
| 53 | /* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */ | ||
| 54 | AB8500_MUX_HOG("gpio2_a_1", "gpio"), | ||
| 55 | AB8500_PIN_HOG("GPIO2_T9", in_pd), | ||
| 56 | |||
| 57 | /* Sysclkreq4 */ | ||
| 58 | AB8500_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT), | ||
| 59 | AB8500_PIN_STATE("GPIO3_U9", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT), | ||
| 60 | /* sysclkreq4 disable, mux in gpio configured in input pulldown */ | ||
| 61 | AB8500_MUX_STATE("gpio3_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP), | ||
| 62 | AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP), | ||
| 63 | |||
| 64 | /* pins 4 is muxed in GPIO, configured in INPUT PULL DOWN */ | ||
| 65 | AB8500_MUX_HOG("gpio4_a_1", "gpio"), | ||
| 66 | AB8500_PIN_HOG("GPIO4_W2", in_pd), | ||
| 67 | |||
| 68 | /* | ||
| 69 | * pins 6,7,8 and 9 are muxed in YCBCR0123 | ||
| 70 | * configured in INPUT PULL UP | ||
| 71 | */ | ||
| 72 | AB8500_MUX_HOG("ycbcr0123_d_1", "ycbcr"), | ||
| 73 | AB8500_PIN_HOG("GPIO6_Y18", in_nopull), | ||
| 74 | AB8500_PIN_HOG("GPIO7_AA20", in_nopull), | ||
| 75 | AB8500_PIN_HOG("GPIO8_W18", in_nopull), | ||
| 76 | AB8500_PIN_HOG("GPIO9_AA19", in_nopull), | ||
| 77 | |||
| 78 | /* | ||
| 79 | * pins 10,11,12 and 13 are muxed in GPIO | ||
| 80 | * configured in INPUT PULL DOWN | ||
| 81 | */ | ||
| 82 | AB8500_MUX_HOG("gpio10_d_1", "gpio"), | ||
| 83 | AB8500_PIN_HOG("GPIO10_U17", in_pd), | ||
| 84 | |||
| 85 | AB8500_MUX_HOG("gpio11_d_1", "gpio"), | ||
| 86 | AB8500_PIN_HOG("GPIO11_AA18", in_pd), | ||
| 87 | |||
| 88 | AB8500_MUX_HOG("gpio12_d_1", "gpio"), | ||
| 89 | AB8500_PIN_HOG("GPIO12_U16", in_pd), | ||
| 90 | |||
| 91 | AB8500_MUX_HOG("gpio13_d_1", "gpio"), | ||
| 92 | AB8500_PIN_HOG("GPIO13_W17", in_pd), | ||
| 93 | |||
| 94 | /* | ||
| 95 | * pins 14,15 are muxed in PWM1 and PWM2 | ||
| 96 | * configured in INPUT PULL DOWN | ||
| 97 | */ | ||
| 98 | AB8500_MUX_HOG("pwmout1_d_1", "pwmout"), | ||
| 99 | AB8500_PIN_HOG("GPIO14_F14", in_pd), | ||
| 100 | |||
| 101 | AB8500_MUX_HOG("pwmout2_d_1", "pwmout"), | ||
| 102 | AB8500_PIN_HOG("GPIO15_B17", in_pd), | ||
| 103 | |||
| 104 | /* | ||
| 105 | * pins 16 is muxed in GPIO | ||
| 106 | * configured in INPUT PULL DOWN | ||
| 107 | */ | ||
| 108 | AB8500_MUX_HOG("gpio16_a_1", "gpio"), | ||
| 109 | AB8500_PIN_HOG("GPIO14_F14", in_pd), | ||
| 110 | |||
| 111 | /* | ||
| 112 | * pins 17,18,19 and 20 are muxed in AUDIO interface 1 | ||
| 113 | * configured in INPUT PULL DOWN | ||
| 114 | */ | ||
| 115 | AB8500_MUX_HOG("adi1_d_1", "adi1"), | ||
| 116 | AB8500_PIN_HOG("GPIO17_P5", in_pd), | ||
| 117 | AB8500_PIN_HOG("GPIO18_R5", in_pd), | ||
| 118 | AB8500_PIN_HOG("GPIO19_U5", in_pd), | ||
| 119 | AB8500_PIN_HOG("GPIO20_T5", in_pd), | ||
| 120 | |||
| 121 | /* | ||
| 122 | * pins 21,22 and 23 are muxed in USB UICC | ||
| 123 | * configured in INPUT PULL DOWN | ||
| 124 | */ | ||
| 125 | AB8500_MUX_HOG("usbuicc_d_1", "usbuicc"), | ||
| 126 | AB8500_PIN_HOG("GPIO21_H19", in_pd), | ||
| 127 | AB8500_PIN_HOG("GPIO22_G20", in_pd), | ||
| 128 | AB8500_PIN_HOG("GPIO23_G19", in_pd), | ||
| 129 | |||
| 130 | /* | ||
| 131 | * pins 24,25 are muxed in GPIO | ||
| 132 | * configured in INPUT PULL DOWN | ||
| 133 | */ | ||
| 134 | AB8500_MUX_HOG("gpio24_a_1", "gpio"), | ||
| 135 | AB8500_PIN_HOG("GPIO24_T14", in_pd), | ||
| 136 | |||
| 137 | AB8500_MUX_HOG("gpio25_a_1", "gpio"), | ||
| 138 | AB8500_PIN_HOG("GPIO25_R16", in_pd), | ||
| 139 | |||
| 140 | /* | ||
| 141 | * pins 26 is muxed in GPIO | ||
| 142 | * configured in OUTPUT LOW | ||
| 143 | */ | ||
| 144 | AB8500_MUX_HOG("gpio26_d_1", "gpio"), | ||
| 145 | AB8500_PIN_HOG("GPIO26_M16", out_lo), | ||
| 146 | |||
| 147 | /* | ||
| 148 | * pins 27,28 are muxed in DMIC12 | ||
| 149 | * configured in INPUT PULL DOWN | ||
| 150 | */ | ||
| 151 | AB8500_MUX_HOG("dmic12_d_1", "dmic"), | ||
| 152 | AB8500_PIN_HOG("GPIO27_J6", in_pd), | ||
| 153 | AB8500_PIN_HOG("GPIO28_K6", in_pd), | ||
| 154 | |||
| 155 | /* | ||
| 156 | * pins 29,30 are muxed in DMIC34 | ||
| 157 | * configured in INPUT PULL DOWN | ||
| 158 | */ | ||
| 159 | AB8500_MUX_HOG("dmic34_d_1", "dmic"), | ||
| 160 | AB8500_PIN_HOG("GPIO29_G6", in_pd), | ||
| 161 | AB8500_PIN_HOG("GPIO30_H6", in_pd), | ||
| 162 | |||
| 163 | /* | ||
| 164 | * pins 31,32 are muxed in DMIC56 | ||
| 165 | * configured in INPUT PULL DOWN | ||
| 166 | */ | ||
| 167 | AB8500_MUX_HOG("dmic56_d_1", "dmic"), | ||
| 168 | AB8500_PIN_HOG("GPIO31_F5", in_pd), | ||
| 169 | AB8500_PIN_HOG("GPIO32_G5", in_pd), | ||
| 170 | |||
| 171 | /* | ||
| 172 | * pins 34 is muxed in EXTCPENA | ||
| 173 | * configured INPUT PULL DOWN | ||
| 174 | */ | ||
| 175 | AB8500_MUX_HOG("extcpena_d_1", "extcpena"), | ||
| 176 | AB8500_PIN_HOG("GPIO34_R17", in_pd), | ||
| 177 | |||
| 178 | /* | ||
| 179 | * pins 35 is muxed in GPIO | ||
| 180 | * configured in OUTPUT LOW | ||
| 181 | */ | ||
| 182 | AB8500_MUX_HOG("gpio35_d_1", "gpio"), | ||
| 183 | AB8500_PIN_HOG("GPIO35_W15", in_pd), | ||
| 184 | |||
| 185 | /* | ||
| 186 | * pins 36,37,38 and 39 are muxed in GPIO | ||
| 187 | * configured in INPUT PULL DOWN | ||
| 188 | */ | ||
| 189 | AB8500_MUX_HOG("gpio36_a_1", "gpio"), | ||
| 190 | AB8500_PIN_HOG("GPIO36_A17", in_pd), | ||
| 191 | |||
| 192 | AB8500_MUX_HOG("gpio37_a_1", "gpio"), | ||
| 193 | AB8500_PIN_HOG("GPIO37_E15", in_pd), | ||
| 194 | |||
| 195 | AB8500_MUX_HOG("gpio38_a_1", "gpio"), | ||
| 196 | AB8500_PIN_HOG("GPIO38_C17", in_pd), | ||
| 197 | |||
| 198 | AB8500_MUX_HOG("gpio39_a_1", "gpio"), | ||
| 199 | AB8500_PIN_HOG("GPIO39_E16", in_pd), | ||
| 200 | |||
| 201 | /* | ||
| 202 | * pins 40 and 41 are muxed in MODCSLSDA | ||
| 203 | * configured INPUT PULL DOWN | ||
| 204 | */ | ||
| 205 | AB8500_MUX_HOG("modsclsda_d_1", "modsclsda"), | ||
| 206 | AB8500_PIN_HOG("GPIO40_T19", in_pd), | ||
| 207 | AB8500_PIN_HOG("GPIO41_U19", in_pd), | ||
| 208 | |||
| 209 | /* | ||
| 210 | * pins 42 is muxed in GPIO | ||
| 211 | * configured INPUT PULL DOWN | ||
| 212 | */ | ||
| 213 | AB8500_MUX_HOG("gpio42_a_1", "gpio"), | ||
| 214 | AB8500_PIN_HOG("GPIO42_U2", in_pd), | ||
| 215 | }; | ||
| 216 | |||
| 217 | static struct pinctrl_map __initdata ab8505_pinmap[] = { | ||
| 218 | /* Sysclkreq2 */ | ||
| 219 | AB8505_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT), | ||
| 220 | AB8505_PIN_STATE("GPIO1_N4", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT), | ||
| 221 | /* sysclkreq2 disable, mux in gpio configured in input pulldown */ | ||
| 222 | AB8505_MUX_STATE("gpio1_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP), | ||
| 223 | AB8505_PIN_STATE("GPIO1_N4", in_pd, "regulator.36", PINCTRL_STATE_SLEEP), | ||
| 224 | |||
| 225 | /* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */ | ||
| 226 | AB8505_MUX_HOG("gpio2_a_1", "gpio"), | ||
| 227 | AB8505_PIN_HOG("GPIO2_R5", in_pd), | ||
| 228 | |||
| 229 | /* Sysclkreq4 */ | ||
| 230 | AB8505_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.37", PINCTRL_STATE_DEFAULT), | ||
| 231 | AB8505_PIN_STATE("GPIO3_P5", in_nopull, "regulator.37", PINCTRL_STATE_DEFAULT), | ||
| 232 | /* sysclkreq4 disable, mux in gpio configured in input pulldown */ | ||
| 233 | AB8505_MUX_STATE("gpio3_a_1", "gpio", "regulator.37", PINCTRL_STATE_SLEEP), | ||
| 234 | AB8505_PIN_STATE("GPIO3_P5", in_pd, "regulator.37", PINCTRL_STATE_SLEEP), | ||
| 235 | |||
| 236 | AB8505_MUX_HOG("gpio10_d_1", "gpio"), | ||
| 237 | AB8505_PIN_HOG("GPIO10_B16", in_pd), | ||
| 238 | |||
| 239 | AB8505_MUX_HOG("gpio11_d_1", "gpio"), | ||
| 240 | AB8505_PIN_HOG("GPIO11_B17", in_pd), | ||
| 241 | |||
| 242 | AB8505_MUX_HOG("gpio13_d_1", "gpio"), | ||
| 243 | AB8505_PIN_HOG("GPIO13_D17", in_nopull), | ||
| 244 | |||
| 245 | AB8505_MUX_HOG("pwmout1_d_1", "pwmout"), | ||
| 246 | AB8505_PIN_HOG("GPIO14_C16", in_pd), | ||
| 247 | |||
| 248 | AB8505_MUX_HOG("adi2_d_1", "adi2"), | ||
| 249 | AB8505_PIN_HOG("GPIO17_P2", in_pd), | ||
| 250 | AB8505_PIN_HOG("GPIO18_N3", in_pd), | ||
| 251 | AB8505_PIN_HOG("GPIO19_T1", in_pd), | ||
| 252 | AB8505_PIN_HOG("GPIO20_P3", in_pd), | ||
| 253 | |||
| 254 | AB8505_MUX_HOG("gpio34_a_1", "gpio"), | ||
| 255 | AB8505_PIN_HOG("GPIO34_H14", in_pd), | ||
| 256 | |||
| 257 | AB8505_MUX_HOG("modsclsda_d_1", "modsclsda"), | ||
| 258 | AB8505_PIN_HOG("GPIO40_J15", in_pd), | ||
| 259 | AB8505_PIN_HOG("GPIO41_J14", in_pd), | ||
| 260 | |||
| 261 | AB8505_MUX_HOG("gpio50_d_1", "gpio"), | ||
| 262 | AB8505_PIN_HOG("GPIO50_L4", in_nopull), | ||
| 263 | |||
| 264 | AB8505_MUX_HOG("resethw_d_1", "resethw"), | ||
| 265 | AB8505_PIN_HOG("GPIO52_D16", in_pd), | ||
| 266 | |||
| 267 | AB8505_MUX_HOG("service_d_1", "service"), | ||
| 268 | AB8505_PIN_HOG("GPIO53_D15", in_pd), | ||
| 269 | }; | ||
| 270 | |||
| 271 | void __init mop500_pinmaps_init(void) | ||
| 272 | { | ||
| 273 | if (machine_is_u8520()) | ||
| 274 | pinctrl_register_mappings(ab8505_pinmap, | ||
| 275 | ARRAY_SIZE(ab8505_pinmap)); | ||
| 276 | else | ||
| 277 | pinctrl_register_mappings(ab8500_pinmap, | ||
| 278 | ARRAY_SIZE(ab8500_pinmap)); | ||
| 279 | } | ||
| 280 | |||
| 281 | void __init snowball_pinmaps_init(void) | ||
| 282 | { | ||
| 283 | pinctrl_register_mappings(ab8500_pinmap, | ||
| 284 | ARRAY_SIZE(ab8500_pinmap)); | ||
| 285 | } | ||
| 286 | |||
| 287 | void __init hrefv60_pinmaps_init(void) | ||
| 288 | { | ||
| 289 | pinctrl_register_mappings(ab8500_pinmap, | ||
| 290 | ARRAY_SIZE(ab8500_pinmap)); | ||
| 291 | } | ||
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h index d48e8662c676..32cc0d8d8a0e 100644 --- a/arch/arm/mach-ux500/board-mop500.h +++ b/arch/arm/mach-ux500/board-mop500.h | |||
| @@ -7,78 +7,9 @@ | |||
| 7 | #ifndef __BOARD_MOP500_H | 7 | #ifndef __BOARD_MOP500_H |
| 8 | #define __BOARD_MOP500_H | 8 | #define __BOARD_MOP500_H |
| 9 | 9 | ||
| 10 | /* For NOMADIK_NR_GPIO */ | ||
| 11 | #include "irqs.h" | ||
| 12 | #include <linux/platform_data/asoc-ux500-msp.h> | 10 | #include <linux/platform_data/asoc-ux500-msp.h> |
| 13 | #include <linux/amba/mmci.h> | 11 | #include <linux/amba/mmci.h> |
| 14 | 12 | ||
| 15 | /* Snowball specific GPIO assignments, this board has no GPIO expander */ | ||
| 16 | #define SNOWBALL_ACCEL_INT1_GPIO 163 | ||
| 17 | #define SNOWBALL_ACCEL_INT2_GPIO 164 | ||
| 18 | #define SNOWBALL_MAGNET_DRDY_GPIO 165 | ||
| 19 | #define SNOWBALL_SDMMC_EN_GPIO 217 | ||
| 20 | #define SNOWBALL_SDMMC_1V8_3V_GPIO 228 | ||
| 21 | #define SNOWBALL_SDMMC_CD_GPIO 218 | ||
| 22 | |||
| 23 | /* HREFv60-specific GPIO assignments, this board has no GPIO expander */ | ||
| 24 | #define HREFV60_SDMMC_1V8_3V_GPIO 5 | ||
| 25 | #define HREFV60_CAMERA_FLASH_ENABLE 21 | ||
| 26 | #define HREFV60_MAGNET_DRDY_GPIO 32 | ||
| 27 | #define HREFV60_DISP1_RST_GPIO 65 | ||
| 28 | #define HREFV60_DISP2_RST_GPIO 66 | ||
| 29 | #define HREFV60_ACCEL_INT1_GPIO 82 | ||
| 30 | #define HREFV60_ACCEL_INT2_GPIO 83 | ||
| 31 | #define HREFV60_SDMMC_CD_GPIO 95 | ||
| 32 | #define HREFV60_XSHUTDOWN_SECONDARY_SENSOR 140 | ||
| 33 | #define HREFV60_TOUCH_RST_GPIO 143 | ||
| 34 | #define HREFV60_HAL_SW_GPIO 145 | ||
| 35 | #define HREFV60_SDMMC_EN_GPIO 169 | ||
| 36 | #define HREFV60_MMIO_XENON_CHARGE 170 | ||
| 37 | #define HREFV60_PROX_SENSE_GPIO 217 | ||
| 38 | |||
| 39 | /* MOP500 generic GPIOs */ | ||
| 40 | #define CAMERA_FLASH_INT_PIN 7 | ||
| 41 | #define CYPRESS_TOUCH_INT_PIN 84 | ||
| 42 | #define XSHUTDOWN_PRIMARY_SENSOR 141 | ||
| 43 | #define XSHUTDOWN_SECONDARY_SENSOR 142 | ||
| 44 | #define CYPRESS_TOUCH_RST_GPIO 143 | ||
| 45 | #define MOP500_HDMI_RST_GPIO 196 | ||
| 46 | #define CYPRESS_SLAVE_SELECT_GPIO 216 | ||
| 47 | |||
| 48 | /* GPIOs on the TC35892 expander */ | ||
| 49 | #define MOP500_EGPIO(x) (NOMADIK_NR_GPIO + (x)) | ||
| 50 | #define GPIO_MAGNET_DRDY MOP500_EGPIO(1) | ||
| 51 | #define GPIO_SDMMC_CD MOP500_EGPIO(3) | ||
| 52 | #define GPIO_CAMERA_FLASH_ENABLE MOP500_EGPIO(4) | ||
| 53 | #define GPIO_MMIO_XENON_CHARGE MOP500_EGPIO(5) | ||
| 54 | #define GPIO_PROX_SENSOR MOP500_EGPIO(7) | ||
| 55 | #define GPIO_HAL_SENSOR MOP500_EGPIO(8) | ||
| 56 | #define GPIO_ACCEL_INT1 MOP500_EGPIO(10) | ||
| 57 | #define GPIO_ACCEL_INT2 MOP500_EGPIO(11) | ||
| 58 | #define GPIO_BU21013_CS MOP500_EGPIO(13) | ||
| 59 | #define MOP500_DISP2_RST_GPIO MOP500_EGPIO(14) | ||
| 60 | #define MOP500_DISP1_RST_GPIO MOP500_EGPIO(15) | ||
| 61 | #define GPIO_SDMMC_EN MOP500_EGPIO(17) | ||
| 62 | #define GPIO_SDMMC_1V8_3V_SEL MOP500_EGPIO(18) | ||
| 63 | #define MOP500_EGPIO_END MOP500_EGPIO(24) | ||
| 64 | |||
| 65 | /* | ||
| 66 | * GPIOs on the AB8500 mixed-signals circuit | ||
| 67 | * Notice that we subtract 1 from the number passed into the macro, this is | ||
| 68 | * because the AB8500 GPIO pins are enumbered starting from 1, so the value in | ||
| 69 | * parens matches the GPIO pin number in the data sheet. | ||
| 70 | */ | ||
| 71 | #define MOP500_AB8500_PIN_GPIO(x) (MOP500_EGPIO_END + (x) - 1) | ||
| 72 | /*Snowball AB8500 GPIO */ | ||
| 73 | #define SNOWBALL_VSMPS2_1V8_GPIO MOP500_AB8500_PIN_GPIO(1) /* SYSCLKREQ2/GPIO1 */ | ||
| 74 | #define SNOWBALL_PM_GPIO1_GPIO MOP500_AB8500_PIN_GPIO(2) /* SYSCLKREQ3/GPIO2 */ | ||
| 75 | #define SNOWBALL_WLAN_CLK_REQ_GPIO MOP500_AB8500_PIN_GPIO(3) /* SYSCLKREQ4/GPIO3 */ | ||
| 76 | #define SNOWBALL_PM_GPIO4_GPIO MOP500_AB8500_PIN_GPIO(4) /* SYSCLKREQ6/GPIO4 */ | ||
| 77 | #define SNOWBALL_EN_3V6_GPIO MOP500_AB8500_PIN_GPIO(16) /* PWMOUT3/GPIO16 */ | ||
| 78 | #define SNOWBALL_PME_ETH_GPIO MOP500_AB8500_PIN_GPIO(24) /* SYSCLKREQ7/GPIO24 */ | ||
| 79 | #define SNOWBALL_EN_3V3_ETH_GPIO MOP500_AB8500_PIN_GPIO(26) /* GPIO26 */ | ||
| 80 | |||
| 81 | struct device; | ||
| 82 | extern struct mmci_platform_data mop500_sdi0_data; | 13 | extern struct mmci_platform_data mop500_sdi0_data; |
| 83 | extern struct mmci_platform_data mop500_sdi1_data; | 14 | extern struct mmci_platform_data mop500_sdi1_data; |
| 84 | extern struct mmci_platform_data mop500_sdi2_data; | 15 | extern struct mmci_platform_data mop500_sdi2_data; |
| @@ -88,8 +19,4 @@ extern struct msp_i2s_platform_data msp1_platform_data; | |||
| 88 | extern struct msp_i2s_platform_data msp2_platform_data; | 19 | extern struct msp_i2s_platform_data msp2_platform_data; |
| 89 | extern struct msp_i2s_platform_data msp3_platform_data; | 20 | extern struct msp_i2s_platform_data msp3_platform_data; |
| 90 | 21 | ||
| 91 | void __init mop500_pinmaps_init(void); | ||
| 92 | void __init snowball_pinmaps_init(void); | ||
| 93 | void __init hrefv60_pinmaps_init(void); | ||
| 94 | |||
| 95 | #endif | 22 | #endif |
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index bc8a6183560d..8820f602fcd2 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c | |||
| @@ -27,7 +27,6 @@ | |||
| 27 | #include <asm/mach/map.h> | 27 | #include <asm/mach/map.h> |
| 28 | 28 | ||
| 29 | #include "setup.h" | 29 | #include "setup.h" |
| 30 | #include "irqs.h" | ||
| 31 | 30 | ||
| 32 | #include "board-mop500-regulators.h" | 31 | #include "board-mop500-regulators.h" |
| 33 | #include "board-mop500.h" | 32 | #include "board-mop500.h" |
| @@ -35,14 +34,11 @@ | |||
| 35 | #include "id.h" | 34 | #include "id.h" |
| 36 | 35 | ||
| 37 | struct ab8500_platform_data ab8500_platdata = { | 36 | struct ab8500_platform_data ab8500_platdata = { |
| 38 | .irq_base = MOP500_AB8500_IRQ_BASE, | ||
| 39 | .regulator = &ab8500_regulator_plat_data, | 37 | .regulator = &ab8500_regulator_plat_data, |
| 40 | }; | 38 | }; |
| 41 | 39 | ||
| 42 | struct prcmu_pdata db8500_prcmu_pdata = { | 40 | struct prcmu_pdata db8500_prcmu_pdata = { |
| 43 | .ab_platdata = &ab8500_platdata, | 41 | .ab_platdata = &ab8500_platdata, |
| 44 | .ab_irq = IRQ_DB8500_AB8500, | ||
| 45 | .irq_base = IRQ_PRCMU_BASE, | ||
| 46 | .version_offset = DB8500_PRCMU_FW_VERSION_OFFSET, | 42 | .version_offset = DB8500_PRCMU_FW_VERSION_OFFSET, |
| 47 | .legacy_offset = DB8500_PRCMU_LEGACY_OFFSET, | 43 | .legacy_offset = DB8500_PRCMU_LEGACY_OFFSET, |
| 48 | }; | 44 | }; |
| @@ -146,7 +142,6 @@ static struct device * __init db8500_soc_device_init(void) | |||
| 146 | return ux500_soc_device_init(soc_id); | 142 | return ux500_soc_device_init(soc_id); |
| 147 | } | 143 | } |
| 148 | 144 | ||
| 149 | #ifdef CONFIG_MACH_UX500_DT | ||
| 150 | static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { | 145 | static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { |
| 151 | /* Requires call-back bindings. */ | 146 | /* Requires call-back bindings. */ |
| 152 | OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata), | 147 | OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata), |
| @@ -191,16 +186,6 @@ static void __init u8500_init_machine(void) | |||
| 191 | { | 186 | { |
| 192 | struct device *parent = db8500_soc_device_init(); | 187 | struct device *parent = db8500_soc_device_init(); |
| 193 | 188 | ||
| 194 | /* Pinmaps must be in place before devices register */ | ||
| 195 | if (of_machine_is_compatible("st-ericsson,mop500")) | ||
| 196 | mop500_pinmaps_init(); | ||
| 197 | else if (of_machine_is_compatible("calaosystems,snowball-a9500")) { | ||
| 198 | snowball_pinmaps_init(); | ||
| 199 | } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) | ||
| 200 | hrefv60_pinmaps_init(); | ||
| 201 | else if (of_machine_is_compatible("st-ericsson,ccu9540")) {} | ||
| 202 | /* TODO: Add pinmaps for ccu9540 board. */ | ||
| 203 | |||
| 204 | /* automatically probe child nodes of dbx5x0 devices */ | 189 | /* automatically probe child nodes of dbx5x0 devices */ |
| 205 | if (of_machine_is_compatible("st-ericsson,u8540")) | 190 | if (of_machine_is_compatible("st-ericsson,u8540")) |
| 206 | of_platform_populate(NULL, u8500_local_bus_nodes, | 191 | of_platform_populate(NULL, u8500_local_bus_nodes, |
| @@ -229,5 +214,3 @@ DT_MACHINE_START(U8500_DT, "ST-Ericsson Ux5x0 platform (Device Tree Support)") | |||
| 229 | .dt_compat = stericsson_dt_platform_compat, | 214 | .dt_compat = stericsson_dt_platform_compat, |
| 230 | .restart = ux500_restart, | 215 | .restart = ux500_restart, |
| 231 | MACHINE_END | 216 | MACHINE_END |
| 232 | |||
| 233 | #endif | ||
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index d11ac4bf336c..db16b5a04ad5 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c | |||
| @@ -52,17 +52,7 @@ void ux500_restart(enum reboot_mode mode, const char *cmd) | |||
| 52 | */ | 52 | */ |
| 53 | void __init ux500_init_irq(void) | 53 | void __init ux500_init_irq(void) |
| 54 | { | 54 | { |
| 55 | void __iomem *dist_base; | ||
| 56 | void __iomem *cpu_base; | ||
| 57 | |||
| 58 | gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND; | 55 | gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND; |
| 59 | |||
| 60 | if (cpu_is_u8500_family() || cpu_is_ux540_family()) { | ||
| 61 | dist_base = __io_address(U8500_GIC_DIST_BASE); | ||
| 62 | cpu_base = __io_address(U8500_GIC_CPU_BASE); | ||
| 63 | } else | ||
| 64 | ux500_unknown_soc(); | ||
| 65 | |||
| 66 | irqchip_init(); | 56 | irqchip_init(); |
| 67 | 57 | ||
| 68 | /* | 58 | /* |
diff --git a/arch/arm/mach-ux500/irqs-board-mop500.h b/arch/arm/mach-ux500/irqs-board-mop500.h deleted file mode 100644 index d526dd8e87d3..000000000000 --- a/arch/arm/mach-ux500/irqs-board-mop500.h +++ /dev/null | |||
| @@ -1,55 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) ST-Ericsson SA 2010 | ||
| 3 | * | ||
| 4 | * Author: Rabin Vincent <rabin.vincent@stericsson.com> | ||
| 5 | * License terms: GNU General Public License (GPL) version 2 | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifndef __MACH_IRQS_BOARD_MOP500_H | ||
| 9 | #define __MACH_IRQS_BOARD_MOP500_H | ||
| 10 | |||
| 11 | /* Number of AB8500 irqs is taken from header file */ | ||
| 12 | #include <linux/mfd/abx500/ab8500.h> | ||
| 13 | |||
| 14 | #define MOP500_AB8500_IRQ_BASE IRQ_BOARD_START | ||
| 15 | #define MOP500_AB8500_IRQ_END (MOP500_AB8500_IRQ_BASE \ | ||
| 16 | + AB8500_MAX_NR_IRQS) | ||
| 17 | |||
| 18 | /* TC35892 */ | ||
| 19 | #define TC35892_NR_INTERNAL_IRQS 8 | ||
| 20 | #define TC35892_INT_GPIO(x) (TC35892_NR_INTERNAL_IRQS + (x)) | ||
| 21 | #define TC35892_NR_GPIOS 24 | ||
| 22 | #define TC35892_NR_IRQS TC35892_INT_GPIO(TC35892_NR_GPIOS) | ||
| 23 | |||
| 24 | #define MOP500_EGPIO_NR_IRQS TC35892_NR_IRQS | ||
| 25 | |||
| 26 | #define MOP500_EGPIO_IRQ_BASE MOP500_AB8500_IRQ_END | ||
| 27 | #define MOP500_EGPIO_IRQ_END (MOP500_EGPIO_IRQ_BASE \ | ||
| 28 | + MOP500_EGPIO_NR_IRQS) | ||
| 29 | /* STMPE1601 irqs */ | ||
| 30 | #define STMPE_NR_INTERNAL_IRQS 9 | ||
| 31 | #define STMPE_INT_GPIO(x) (STMPE_NR_INTERNAL_IRQS + (x)) | ||
| 32 | #define STMPE_NR_GPIOS 24 | ||
| 33 | #define STMPE_NR_IRQS STMPE_INT_GPIO(STMPE_NR_GPIOS) | ||
| 34 | |||
| 35 | #define MOP500_STMPE1601_IRQBASE MOP500_EGPIO_IRQ_END | ||
| 36 | #define MOP500_STMPE1601_IRQ(x) (MOP500_STMPE1601_IRQBASE + (x)) | ||
| 37 | |||
| 38 | #define MOP500_STMPE1601_IRQ_END \ | ||
| 39 | MOP500_STMPE1601_IRQ(STMPE_NR_INTERNAL_IRQS) | ||
| 40 | |||
| 41 | #define MOP500_NR_IRQS MOP500_STMPE1601_IRQ_END | ||
| 42 | |||
| 43 | #define MOP500_IRQ_END MOP500_NR_IRQS | ||
| 44 | |||
| 45 | /* | ||
| 46 | * We may have several boards, but only one will run at a | ||
| 47 | * time, so the one with most IRQs will bump this ahead, | ||
| 48 | * but the IRQ_BOARD_START remains the same for either board. | ||
| 49 | */ | ||
| 50 | #if MOP500_IRQ_END > IRQ_BOARD_END | ||
| 51 | #undef IRQ_BOARD_END | ||
| 52 | #define IRQ_BOARD_END MOP500_IRQ_END | ||
| 53 | #endif | ||
| 54 | |||
| 55 | #endif | ||
diff --git a/arch/arm/mach-ux500/irqs-db8500.h b/arch/arm/mach-ux500/irqs-db8500.h deleted file mode 100644 index f3a9d5947ef3..000000000000 --- a/arch/arm/mach-ux500/irqs-db8500.h +++ /dev/null | |||
| @@ -1,125 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) ST-Ericsson SA 2010 | ||
| 3 | * | ||
| 4 | * Author: Rabin Vincent <rabin.vincent@stericsson.com> | ||
| 5 | * License terms: GNU General Public License (GPL) version 2 | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifndef __MACH_IRQS_DB8500_H | ||
| 9 | #define __MACH_IRQS_DB8500_H | ||
| 10 | |||
| 11 | #define IRQ_DB8500_MTU0 (IRQ_SHPI_START + 4) | ||
| 12 | #define IRQ_DB8500_SPI2 (IRQ_SHPI_START + 6) | ||
| 13 | #define IRQ_DB8500_PMU (IRQ_SHPI_START + 7) | ||
| 14 | #define IRQ_DB8500_SPI0 (IRQ_SHPI_START + 8) | ||
| 15 | #define IRQ_DB8500_RTT (IRQ_SHPI_START + 9) | ||
| 16 | #define IRQ_DB8500_PKA (IRQ_SHPI_START + 10) | ||
| 17 | #define IRQ_DB8500_UART0 (IRQ_SHPI_START + 11) | ||
| 18 | #define IRQ_DB8500_I2C3 (IRQ_SHPI_START + 12) | ||
| 19 | #define IRQ_DB8500_L2CC (IRQ_SHPI_START + 13) | ||
| 20 | #define IRQ_DB8500_SSP0 (IRQ_SHPI_START + 14) | ||
| 21 | #define IRQ_DB8500_CRYP1 (IRQ_SHPI_START + 15) | ||
| 22 | #define IRQ_DB8500_MSP1_RX (IRQ_SHPI_START + 16) | ||
| 23 | #define IRQ_DB8500_MTU1 (IRQ_SHPI_START + 17) | ||
| 24 | #define IRQ_DB8500_RTC (IRQ_SHPI_START + 18) | ||
| 25 | #define IRQ_DB8500_UART1 (IRQ_SHPI_START + 19) | ||
| 26 | #define IRQ_DB8500_USB_WAKEUP (IRQ_SHPI_START + 20) | ||
| 27 | #define IRQ_DB8500_I2C0 (IRQ_SHPI_START + 21) | ||
| 28 | #define IRQ_DB8500_I2C1 (IRQ_SHPI_START + 22) | ||
| 29 | #define IRQ_DB8500_USBOTG (IRQ_SHPI_START + 23) | ||
| 30 | #define IRQ_DB8500_DMA_SECURE (IRQ_SHPI_START + 24) | ||
| 31 | #define IRQ_DB8500_DMA (IRQ_SHPI_START + 25) | ||
| 32 | #define IRQ_DB8500_UART2 (IRQ_SHPI_START + 26) | ||
| 33 | #define IRQ_DB8500_ICN_PMU1 (IRQ_SHPI_START + 27) | ||
| 34 | #define IRQ_DB8500_ICN_PMU2 (IRQ_SHPI_START + 28) | ||
| 35 | #define IRQ_DB8500_HSIR_EXCEP (IRQ_SHPI_START + 29) | ||
| 36 | #define IRQ_DB8500_MSP0 (IRQ_SHPI_START + 31) | ||
| 37 | #define IRQ_DB8500_HSIR_CH0_OVRRUN (IRQ_SHPI_START + 32) | ||
| 38 | #define IRQ_DB8500_HSIR_CH1_OVRRUN (IRQ_SHPI_START + 33) | ||
| 39 | #define IRQ_DB8500_HSIR_CH2_OVRRUN (IRQ_SHPI_START + 34) | ||
| 40 | #define IRQ_DB8500_HSIR_CH3_OVRRUN (IRQ_SHPI_START + 35) | ||
| 41 | #define IRQ_DB8500_HSIR_CH4_OVRRUN (IRQ_SHPI_START + 36) | ||
| 42 | #define IRQ_DB8500_HSIR_CH5_OVRRUN (IRQ_SHPI_START + 37) | ||
| 43 | #define IRQ_DB8500_HSIR_CH6_OVRRUN (IRQ_SHPI_START + 38) | ||
| 44 | #define IRQ_DB8500_HSIR_CH7_OVRRUN (IRQ_SHPI_START + 39) | ||
| 45 | #define IRQ_DB8500_AB8500 (IRQ_SHPI_START + 40) | ||
| 46 | #define IRQ_DB8500_SDMMC2 (IRQ_SHPI_START + 41) | ||
| 47 | #define IRQ_DB8500_SIA (IRQ_SHPI_START + 42) | ||
| 48 | #define IRQ_DB8500_SIA2 (IRQ_SHPI_START + 43) | ||
| 49 | #define IRQ_DB8500_SVA (IRQ_SHPI_START + 44) | ||
| 50 | #define IRQ_DB8500_SVA2 (IRQ_SHPI_START + 45) | ||
| 51 | #define IRQ_DB8500_PRCMU0 (IRQ_SHPI_START + 46) | ||
| 52 | #define IRQ_DB8500_PRCMU1 (IRQ_SHPI_START + 47) | ||
| 53 | #define IRQ_DB8500_DISP (IRQ_SHPI_START + 48) | ||
| 54 | #define IRQ_DB8500_SPI3 (IRQ_SHPI_START + 49) | ||
| 55 | #define IRQ_DB8500_SDMMC1 (IRQ_SHPI_START + 50) | ||
| 56 | #define IRQ_DB8500_I2C4 (IRQ_SHPI_START + 51) | ||
| 57 | #define IRQ_DB8500_SSP1 (IRQ_SHPI_START + 52) | ||
| 58 | #define IRQ_DB8500_SKE (IRQ_SHPI_START + 53) | ||
| 59 | #define IRQ_DB8500_KB (IRQ_SHPI_START + 54) | ||
| 60 | #define IRQ_DB8500_I2C2 (IRQ_SHPI_START + 55) | ||
| 61 | #define IRQ_DB8500_B2R2 (IRQ_SHPI_START + 56) | ||
| 62 | #define IRQ_DB8500_CRYP0 (IRQ_SHPI_START + 57) | ||
| 63 | #define IRQ_DB8500_SDMMC3 (IRQ_SHPI_START + 59) | ||
| 64 | #define IRQ_DB8500_SDMMC0 (IRQ_SHPI_START + 60) | ||
| 65 | #define IRQ_DB8500_HSEM (IRQ_SHPI_START + 61) | ||
| 66 | #define IRQ_DB8500_MSP1 (IRQ_SHPI_START + 62) | ||
| 67 | #define IRQ_DB8500_SBAG (IRQ_SHPI_START + 63) | ||
| 68 | #define IRQ_DB8500_SPI1 (IRQ_SHPI_START + 96) | ||
| 69 | #define IRQ_DB8500_SRPTIMER (IRQ_SHPI_START + 97) | ||
| 70 | #define IRQ_DB8500_MSP2 (IRQ_SHPI_START + 98) | ||
| 71 | #define IRQ_DB8500_SDMMC4 (IRQ_SHPI_START + 99) | ||
| 72 | #define IRQ_DB8500_SDMMC5 (IRQ_SHPI_START + 100) | ||
| 73 | #define IRQ_DB8500_HSIRD0 (IRQ_SHPI_START + 104) | ||
| 74 | #define IRQ_DB8500_HSIRD1 (IRQ_SHPI_START + 105) | ||
| 75 | #define IRQ_DB8500_HSITD0 (IRQ_SHPI_START + 106) | ||
| 76 | #define IRQ_DB8500_HSITD1 (IRQ_SHPI_START + 107) | ||
| 77 | #define IRQ_DB8500_CTI0 (IRQ_SHPI_START + 108) | ||
| 78 | #define IRQ_DB8500_CTI1 (IRQ_SHPI_START + 109) | ||
| 79 | #define IRQ_DB8500_ICN_ERR (IRQ_SHPI_START + 110) | ||
| 80 | #define IRQ_DB8500_MALI_PPMMU (IRQ_SHPI_START + 112) | ||
| 81 | #define IRQ_DB8500_MALI_PP (IRQ_SHPI_START + 113) | ||
| 82 | #define IRQ_DB8500_MALI_GPMMU (IRQ_SHPI_START + 114) | ||
| 83 | #define IRQ_DB8500_MALI_GP (IRQ_SHPI_START + 115) | ||
| 84 | #define IRQ_DB8500_MALI (IRQ_SHPI_START + 116) | ||
| 85 | #define IRQ_DB8500_PRCMU_SEM (IRQ_SHPI_START + 118) | ||
| 86 | #define IRQ_DB8500_GPIO0 (IRQ_SHPI_START + 119) | ||
| 87 | #define IRQ_DB8500_GPIO1 (IRQ_SHPI_START + 120) | ||
| 88 | #define IRQ_DB8500_GPIO2 (IRQ_SHPI_START + 121) | ||
| 89 | #define IRQ_DB8500_GPIO3 (IRQ_SHPI_START + 122) | ||
| 90 | #define IRQ_DB8500_GPIO4 (IRQ_SHPI_START + 123) | ||
| 91 | #define IRQ_DB8500_GPIO5 (IRQ_SHPI_START + 124) | ||
| 92 | #define IRQ_DB8500_GPIO6 (IRQ_SHPI_START + 125) | ||
| 93 | #define IRQ_DB8500_GPIO7 (IRQ_SHPI_START + 126) | ||
| 94 | #define IRQ_DB8500_GPIO8 (IRQ_SHPI_START + 127) | ||
| 95 | |||
| 96 | #define IRQ_CA_WAKE_REQ_ED (IRQ_SHPI_START + 71) | ||
| 97 | #define IRQ_AC_READ_NOTIFICATION_0_ED (IRQ_SHPI_START + 66) | ||
| 98 | #define IRQ_AC_READ_NOTIFICATION_1_ED (IRQ_SHPI_START + 64) | ||
| 99 | #define IRQ_CA_MSG_PEND_NOTIFICATION_0_ED (IRQ_SHPI_START + 67) | ||
| 100 | #define IRQ_CA_MSG_PEND_NOTIFICATION_1_ED (IRQ_SHPI_START + 65) | ||
| 101 | |||
| 102 | #define IRQ_CA_WAKE_REQ_V1 (IRQ_SHPI_START + 83) | ||
| 103 | #define IRQ_AC_READ_NOTIFICATION_0_V1 (IRQ_SHPI_START + 78) | ||
| 104 | #define IRQ_AC_READ_NOTIFICATION_1_V1 (IRQ_SHPI_START + 76) | ||
| 105 | #define IRQ_CA_MSG_PEND_NOTIFICATION_0_V1 (IRQ_SHPI_START + 79) | ||
| 106 | #define IRQ_CA_MSG_PEND_NOTIFICATION_1_V1 (IRQ_SHPI_START + 77) | ||
| 107 | |||
| 108 | #ifdef CONFIG_UX500_SOC_DB8500 | ||
| 109 | |||
| 110 | /* Virtual interrupts corresponding to the PRCMU wakeups. */ | ||
| 111 | #define IRQ_PRCMU_BASE IRQ_SOC_START | ||
| 112 | #define IRQ_PRCMU_END (IRQ_PRCMU_BASE + 23) | ||
| 113 | |||
| 114 | /* | ||
| 115 | * We may have several SoCs, but only one will run at a | ||
| 116 | * time, so the one with most IRQs will bump this ahead, | ||
| 117 | * but the IRQ_SOC_START remains the same for either SoC. | ||
| 118 | */ | ||
| 119 | #if IRQ_SOC_END < IRQ_PRCMU_END | ||
| 120 | #undef IRQ_SOC_END | ||
| 121 | #define IRQ_SOC_END IRQ_PRCMU_END | ||
| 122 | #endif | ||
| 123 | |||
| 124 | #endif /* CONFIG_UX500_SOC_DB8500 */ | ||
| 125 | #endif | ||
diff --git a/arch/arm/mach-ux500/irqs.h b/arch/arm/mach-ux500/irqs.h deleted file mode 100644 index 15b2af698ed7..000000000000 --- a/arch/arm/mach-ux500/irqs.h +++ /dev/null | |||
| @@ -1,49 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2008 STMicroelectronics | ||
| 3 | * Copyright (C) 2009 ST-Ericsson. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License as published by | ||
| 7 | * the Free Software Foundation; either version 2 of the License, or | ||
| 8 | * (at your option) any later version. | ||
| 9 | */ | ||
| 10 | #ifndef ASM_ARCH_IRQS_H | ||
| 11 | #define ASM_ARCH_IRQS_H | ||
| 12 | |||
| 13 | #define IRQ_LOCALTIMER 29 | ||
| 14 | #define IRQ_LOCALWDOG 30 | ||
| 15 | |||
| 16 | /* Shared Peripheral Interrupt (SHPI) */ | ||
| 17 | #define IRQ_SHPI_START 32 | ||
| 18 | |||
| 19 | /* | ||
| 20 | * MTU0 preserved for now until plat-nomadik is taught not to use it. Don't | ||
| 21 | * add any other IRQs here, use the irqs-dbx500.h files. | ||
| 22 | */ | ||
| 23 | #define IRQ_MTU0 (IRQ_SHPI_START + 4) | ||
| 24 | |||
| 25 | #define DBX500_NR_INTERNAL_IRQS 166 | ||
| 26 | |||
| 27 | /* After chip-specific IRQ numbers we have the GPIO ones */ | ||
| 28 | #define NOMADIK_NR_GPIO 288 | ||
| 29 | #define NOMADIK_GPIO_TO_IRQ(gpio) ((gpio) + DBX500_NR_INTERNAL_IRQS) | ||
| 30 | #define NOMADIK_IRQ_TO_GPIO(irq) ((irq) - DBX500_NR_INTERNAL_IRQS) | ||
| 31 | #define IRQ_GPIO_END NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO) | ||
| 32 | |||
| 33 | #define IRQ_SOC_START IRQ_GPIO_END | ||
| 34 | /* This will be overridden by SoC-specific irq headers */ | ||
| 35 | #define IRQ_SOC_END IRQ_SOC_START | ||
| 36 | |||
| 37 | #include "irqs-db8500.h" | ||
| 38 | |||
| 39 | #define IRQ_BOARD_START IRQ_SOC_END | ||
| 40 | /* This will be overridden by board-specific irq headers */ | ||
| 41 | #define IRQ_BOARD_END IRQ_BOARD_START | ||
| 42 | |||
| 43 | #ifdef CONFIG_MACH_MOP500 | ||
| 44 | #include "irqs-board-mop500.h" | ||
| 45 | #endif | ||
| 46 | |||
| 47 | #define UX500_NR_IRQS IRQ_BOARD_END | ||
| 48 | |||
| 49 | #endif /* ASM_ARCH_IRQS_H */ | ||
diff --git a/arch/arm/mach-versatile/include/mach/timex.h b/arch/arm/mach-versatile/include/mach/timex.h deleted file mode 100644 index 426199b1add5..000000000000 --- a/arch/arm/mach-versatile/include/mach/timex.h +++ /dev/null | |||
| @@ -1,23 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-versatile/include/mach/timex.h | ||
| 3 | * | ||
| 4 | * Versatile architecture timex specifications | ||
| 5 | * | ||
| 6 | * Copyright (C) 2003 ARM Limited | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License | ||
| 19 | * along with this program; if not, write to the Free Software | ||
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 21 | */ | ||
| 22 | |||
| 23 | #define CLOCK_TICK_RATE (50000000 / 16) | ||
diff --git a/arch/arm/mach-w90x900/include/mach/timex.h b/arch/arm/mach-w90x900/include/mach/timex.h deleted file mode 100644 index 164dce0b64db..000000000000 --- a/arch/arm/mach-w90x900/include/mach/timex.h +++ /dev/null | |||
| @@ -1,25 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-w90x900/include/mach/timex.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 2008 Nuvoton technology corporation | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * Wan ZongShun <mcuos.com@gmail.com> | ||
| 8 | * | ||
| 9 | * Based on arch/arm/mach-s3c2410/include/mach/timex.h | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License as published by | ||
| 13 | * the Free Software Foundation; either version 2 of the License, or | ||
| 14 | * (at your option) any later version. | ||
| 15 | * | ||
| 16 | */ | ||
| 17 | |||
| 18 | #ifndef __ASM_ARCH_TIMEX_H | ||
| 19 | #define __ASM_ARCH_TIMEX_H | ||
| 20 | |||
| 21 | /* CLOCK_TICK_RATE Now, I don't use it. */ | ||
| 22 | |||
| 23 | #define CLOCK_TICK_RATE 15000000 | ||
| 24 | |||
| 25 | #endif /* __ASM_ARCH_TIMEX_H */ | ||
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 1f8fed94c2a4..dccd7e177653 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig | |||
| @@ -855,7 +855,7 @@ config OUTER_CACHE_SYNC | |||
| 855 | 855 | ||
| 856 | config CACHE_FEROCEON_L2 | 856 | config CACHE_FEROCEON_L2 |
| 857 | bool "Enable the Feroceon L2 cache controller" | 857 | bool "Enable the Feroceon L2 cache controller" |
| 858 | depends on ARCH_KIRKWOOD || ARCH_MV78XX0 | 858 | depends on ARCH_KIRKWOOD || ARCH_MV78XX0 || ARCH_MVEBU |
| 859 | default y | 859 | default y |
| 860 | select OUTER_CACHE | 860 | select OUTER_CACHE |
| 861 | help | 861 | help |
diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c index 48bc3c0a87ce..8dc1a2b5a8ed 100644 --- a/arch/arm/mm/cache-feroceon-l2.c +++ b/arch/arm/mm/cache-feroceon-l2.c | |||
| @@ -13,10 +13,15 @@ | |||
| 13 | */ | 13 | */ |
| 14 | 14 | ||
| 15 | #include <linux/init.h> | 15 | #include <linux/init.h> |
| 16 | #include <linux/of.h> | ||
| 17 | #include <linux/of_address.h> | ||
| 16 | #include <linux/highmem.h> | 18 | #include <linux/highmem.h> |
| 19 | #include <linux/io.h> | ||
| 17 | #include <asm/cacheflush.h> | 20 | #include <asm/cacheflush.h> |
| 18 | #include <asm/cp15.h> | 21 | #include <asm/cp15.h> |
| 19 | #include <plat/cache-feroceon-l2.h> | 22 | #include <asm/hardware/cache-feroceon-l2.h> |
| 23 | |||
| 24 | #define L2_WRITETHROUGH_KIRKWOOD BIT(4) | ||
| 20 | 25 | ||
| 21 | /* | 26 | /* |
| 22 | * Low-level cache maintenance operations. | 27 | * Low-level cache maintenance operations. |
| @@ -350,3 +355,41 @@ void __init feroceon_l2_init(int __l2_wt_override) | |||
| 350 | printk(KERN_INFO "Feroceon L2: Cache support initialised%s.\n", | 355 | printk(KERN_INFO "Feroceon L2: Cache support initialised%s.\n", |
| 351 | l2_wt_override ? ", in WT override mode" : ""); | 356 | l2_wt_override ? ", in WT override mode" : ""); |
| 352 | } | 357 | } |
| 358 | #ifdef CONFIG_OF | ||
| 359 | static const struct of_device_id feroceon_ids[] __initconst = { | ||
| 360 | { .compatible = "marvell,kirkwood-cache"}, | ||
| 361 | { .compatible = "marvell,feroceon-cache"}, | ||
| 362 | {} | ||
| 363 | }; | ||
| 364 | |||
| 365 | int __init feroceon_of_init(void) | ||
| 366 | { | ||
| 367 | struct device_node *node; | ||
| 368 | void __iomem *base; | ||
| 369 | bool l2_wt_override = false; | ||
| 370 | struct resource res; | ||
| 371 | |||
| 372 | #if defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH) | ||
| 373 | l2_wt_override = true; | ||
| 374 | #endif | ||
| 375 | |||
| 376 | node = of_find_matching_node(NULL, feroceon_ids); | ||
| 377 | if (node && of_device_is_compatible(node, "marvell,kirkwood-cache")) { | ||
| 378 | if (of_address_to_resource(node, 0, &res)) | ||
| 379 | return -ENODEV; | ||
| 380 | |||
| 381 | base = ioremap(res.start, resource_size(&res)); | ||
| 382 | if (!base) | ||
| 383 | return -ENOMEM; | ||
| 384 | |||
| 385 | if (l2_wt_override) | ||
| 386 | writel(readl(base) | L2_WRITETHROUGH_KIRKWOOD, base); | ||
| 387 | else | ||
| 388 | writel(readl(base) & ~L2_WRITETHROUGH_KIRKWOOD, base); | ||
| 389 | } | ||
| 390 | |||
| 391 | feroceon_l2_init(l2_wt_override); | ||
| 392 | |||
| 393 | return 0; | ||
| 394 | } | ||
| 395 | #endif | ||
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index 436ea97074cd..02fc10d2d63b 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig | |||
| @@ -86,9 +86,6 @@ config OMAP_MUX_WARNINGS | |||
| 86 | to change the pin multiplexing setup. When there are no warnings | 86 | to change the pin multiplexing setup. When there are no warnings |
| 87 | printed, it's safe to deselect OMAP_MUX for your product. | 87 | printed, it's safe to deselect OMAP_MUX for your product. |
| 88 | 88 | ||
| 89 | config OMAP_IOMMU_IVA2 | ||
| 90 | bool | ||
| 91 | |||
| 92 | config OMAP_MPU_TIMER | 89 | config OMAP_MPU_TIMER |
| 93 | bool "Use mpu timer" | 90 | bool "Use mpu timer" |
| 94 | depends on ARCH_OMAP1 | 91 | depends on ARCH_OMAP1 |
diff --git a/arch/arm/plat-omap/include/plat/timex.h b/arch/arm/plat-omap/include/plat/timex.h deleted file mode 100644 index e27d2daa7790..000000000000 --- a/arch/arm/plat-omap/include/plat/timex.h +++ /dev/null | |||
| @@ -1,33 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/include/mach/timex.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2000 RidgeRun, Inc. | ||
| 5 | * Author: Greg Lonnon <glonnon@ridgerun.com> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License as published by the | ||
| 9 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 10 | * option) any later version. | ||
| 11 | * | ||
| 12 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 13 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 14 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 15 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 16 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 17 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 18 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 19 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 20 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 21 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 22 | * | ||
| 23 | * You should have received a copy of the GNU General Public License along | ||
| 24 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 25 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 26 | */ | ||
| 27 | |||
| 28 | #if !defined(__ASM_ARCH_OMAP_TIMEX_H) | ||
| 29 | #define __ASM_ARCH_OMAP_TIMEX_H | ||
| 30 | |||
| 31 | #define CLOCK_TICK_RATE (HZ * 100000UL) | ||
| 32 | |||
| 33 | #endif /* __ASM_ARCH_OMAP_TIMEX_H */ | ||
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index cd6950fd8caf..6510ec4f45ff 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig | |||
| @@ -140,3 +140,6 @@ config VF_PIT_TIMER | |||
| 140 | bool | 140 | bool |
| 141 | help | 141 | help |
| 142 | Support for Period Interrupt Timer on Freescale Vybrid Family SoCs. | 142 | Support for Period Interrupt Timer on Freescale Vybrid Family SoCs. |
| 143 | |||
| 144 | config CLKSRC_QCOM | ||
| 145 | bool | ||
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index c7ca50a9c232..2e0c0cc0a014 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile | |||
| @@ -32,6 +32,7 @@ obj-$(CONFIG_CLKSRC_EFM32) += time-efm32.o | |||
| 32 | obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exynos_mct.o | 32 | obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exynos_mct.o |
| 33 | obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o | 33 | obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o |
| 34 | obj-$(CONFIG_VF_PIT_TIMER) += vf_pit_timer.o | 34 | obj-$(CONFIG_VF_PIT_TIMER) += vf_pit_timer.o |
| 35 | obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o | ||
| 35 | 36 | ||
| 36 | obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o | 37 | obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o |
| 37 | obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o | 38 | obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o |
diff --git a/arch/arm/mach-msm/timer.c b/drivers/clocksource/qcom-timer.c index fd1644987534..e807acf4c665 100644 --- a/arch/arm/mach-msm/timer.c +++ b/drivers/clocksource/qcom-timer.c | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * | 2 | * |
| 3 | * Copyright (C) 2007 Google, Inc. | 3 | * Copyright (C) 2007 Google, Inc. |
| 4 | * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved. | 4 | * Copyright (c) 2009-2012,2014, The Linux Foundation. All rights reserved. |
| 5 | * | 5 | * |
| 6 | * This software is licensed under the terms of the GNU General Public | 6 | * This software is licensed under the terms of the GNU General Public |
| 7 | * License version 2, as published by the Free Software Foundation, and | 7 | * License version 2, as published by the Free Software Foundation, and |
| @@ -26,10 +26,6 @@ | |||
| 26 | #include <linux/of_irq.h> | 26 | #include <linux/of_irq.h> |
| 27 | #include <linux/sched_clock.h> | 27 | #include <linux/sched_clock.h> |
| 28 | 28 | ||
| 29 | #include <asm/mach/time.h> | ||
| 30 | |||
| 31 | #include "common.h" | ||
| 32 | |||
| 33 | #define TIMER_MATCH_VAL 0x0000 | 29 | #define TIMER_MATCH_VAL 0x0000 |
| 34 | #define TIMER_COUNT_VAL 0x0004 | 30 | #define TIMER_COUNT_VAL 0x0004 |
| 35 | #define TIMER_ENABLE 0x0008 | 31 | #define TIMER_ENABLE 0x0008 |
| @@ -110,15 +106,6 @@ static notrace cycle_t msm_read_timer_count(struct clocksource *cs) | |||
| 110 | return readl_relaxed(source_base + TIMER_COUNT_VAL); | 106 | return readl_relaxed(source_base + TIMER_COUNT_VAL); |
| 111 | } | 107 | } |
| 112 | 108 | ||
| 113 | static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs) | ||
| 114 | { | ||
| 115 | /* | ||
| 116 | * Shift timer count down by a constant due to unreliable lower bits | ||
| 117 | * on some targets. | ||
| 118 | */ | ||
| 119 | return msm_read_timer_count(cs) >> MSM_DGT_SHIFT; | ||
| 120 | } | ||
| 121 | |||
| 122 | static struct clocksource msm_clocksource = { | 109 | static struct clocksource msm_clocksource = { |
| 123 | .name = "dg_timer", | 110 | .name = "dg_timer", |
| 124 | .rating = 300, | 111 | .rating = 300, |
| @@ -232,7 +219,7 @@ err: | |||
| 232 | sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz); | 219 | sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz); |
| 233 | } | 220 | } |
| 234 | 221 | ||
| 235 | #ifdef CONFIG_OF | 222 | #ifdef CONFIG_ARCH_QCOM |
| 236 | static void __init msm_dt_timer_init(struct device_node *np) | 223 | static void __init msm_dt_timer_init(struct device_node *np) |
| 237 | { | 224 | { |
| 238 | u32 freq; | 225 | u32 freq; |
| @@ -285,7 +272,7 @@ static void __init msm_dt_timer_init(struct device_node *np) | |||
| 285 | } | 272 | } |
| 286 | CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init); | 273 | CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init); |
| 287 | CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init); | 274 | CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init); |
| 288 | #endif | 275 | #else |
| 289 | 276 | ||
| 290 | static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source, | 277 | static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source, |
| 291 | u32 sts) | 278 | u32 sts) |
| @@ -305,6 +292,15 @@ static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source, | |||
| 305 | return 0; | 292 | return 0; |
| 306 | } | 293 | } |
| 307 | 294 | ||
| 295 | static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs) | ||
| 296 | { | ||
| 297 | /* | ||
| 298 | * Shift timer count down by a constant due to unreliable lower bits | ||
| 299 | * on some targets. | ||
| 300 | */ | ||
| 301 | return msm_read_timer_count(cs) >> MSM_DGT_SHIFT; | ||
| 302 | } | ||
| 303 | |||
| 308 | void __init msm7x01_timer_init(void) | 304 | void __init msm7x01_timer_init(void) |
| 309 | { | 305 | { |
| 310 | struct clocksource *cs = &msm_clocksource; | 306 | struct clocksource *cs = &msm_clocksource; |
| @@ -331,3 +327,4 @@ void __init qsd8x50_timer_init(void) | |||
| 331 | return; | 327 | return; |
| 332 | msm_timer_init(19200000 / 4, 32, 7, false); | 328 | msm_timer_init(19200000 / 4, 32, 7, false); |
| 333 | } | 329 | } |
| 330 | #endif | ||
diff --git a/drivers/clocksource/timer-marco.c b/drivers/clocksource/timer-marco.c index 09a17d9a6594..b52e1c078b99 100644 --- a/drivers/clocksource/timer-marco.c +++ b/drivers/clocksource/timer-marco.c | |||
| @@ -19,7 +19,8 @@ | |||
| 19 | #include <linux/of_irq.h> | 19 | #include <linux/of_irq.h> |
| 20 | #include <linux/of_address.h> | 20 | #include <linux/of_address.h> |
| 21 | #include <linux/sched_clock.h> | 21 | #include <linux/sched_clock.h> |
| 22 | #include <asm/mach/time.h> | 22 | |
| 23 | #define MARCO_CLOCK_FREQ 1000000 | ||
| 23 | 24 | ||
| 24 | #define SIRFSOC_TIMER_32COUNTER_0_CTRL 0x0000 | 25 | #define SIRFSOC_TIMER_32COUNTER_0_CTRL 0x0000 |
| 25 | #define SIRFSOC_TIMER_32COUNTER_1_CTRL 0x0004 | 26 | #define SIRFSOC_TIMER_32COUNTER_1_CTRL 0x0004 |
| @@ -191,7 +192,7 @@ static int sirfsoc_local_timer_setup(struct clock_event_device *ce) | |||
| 191 | ce->rating = 200; | 192 | ce->rating = 200; |
| 192 | ce->set_mode = sirfsoc_timer_set_mode; | 193 | ce->set_mode = sirfsoc_timer_set_mode; |
| 193 | ce->set_next_event = sirfsoc_timer_set_next_event; | 194 | ce->set_next_event = sirfsoc_timer_set_next_event; |
| 194 | clockevents_calc_mult_shift(ce, CLOCK_TICK_RATE, 60); | 195 | clockevents_calc_mult_shift(ce, MARCO_CLOCK_FREQ, 60); |
| 195 | ce->max_delta_ns = clockevent_delta2ns(-2, ce); | 196 | ce->max_delta_ns = clockevent_delta2ns(-2, ce); |
| 196 | ce->min_delta_ns = clockevent_delta2ns(2, ce); | 197 | ce->min_delta_ns = clockevent_delta2ns(2, ce); |
| 197 | ce->cpumask = cpumask_of(cpu); | 198 | ce->cpumask = cpumask_of(cpu); |
| @@ -263,11 +264,11 @@ static void __init sirfsoc_marco_timer_init(void) | |||
| 263 | BUG_ON(IS_ERR(clk)); | 264 | BUG_ON(IS_ERR(clk)); |
| 264 | rate = clk_get_rate(clk); | 265 | rate = clk_get_rate(clk); |
| 265 | 266 | ||
| 266 | BUG_ON(rate < CLOCK_TICK_RATE); | 267 | BUG_ON(rate < MARCO_CLOCK_FREQ); |
| 267 | BUG_ON(rate % CLOCK_TICK_RATE); | 268 | BUG_ON(rate % MARCO_CLOCK_FREQ); |
| 268 | 269 | ||
| 269 | /* Initialize the timer dividers */ | 270 | /* Initialize the timer dividers */ |
| 270 | timer_div = rate / CLOCK_TICK_RATE - 1; | 271 | timer_div = rate / MARCO_CLOCK_FREQ - 1; |
| 271 | writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL); | 272 | writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL); |
| 272 | writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL); | 273 | writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL); |
| 273 | writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL); | 274 | writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL); |
| @@ -283,7 +284,7 @@ static void __init sirfsoc_marco_timer_init(void) | |||
| 283 | /* Clear all interrupts */ | 284 | /* Clear all interrupts */ |
| 284 | writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS); | 285 | writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS); |
| 285 | 286 | ||
| 286 | BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE)); | 287 | BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, MARCO_CLOCK_FREQ)); |
| 287 | 288 | ||
| 288 | sirfsoc_clockevent_init(); | 289 | sirfsoc_clockevent_init(); |
| 289 | } | 290 | } |
diff --git a/drivers/clocksource/timer-prima2.c b/drivers/clocksource/timer-prima2.c index 8a492d34ff9f..1a6b2d6356d6 100644 --- a/drivers/clocksource/timer-prima2.c +++ b/drivers/clocksource/timer-prima2.c | |||
| @@ -21,6 +21,8 @@ | |||
| 21 | #include <linux/sched_clock.h> | 21 | #include <linux/sched_clock.h> |
| 22 | #include <asm/mach/time.h> | 22 | #include <asm/mach/time.h> |
| 23 | 23 | ||
| 24 | #define PRIMA2_CLOCK_FREQ 1000000 | ||
| 25 | |||
| 24 | #define SIRFSOC_TIMER_COUNTER_LO 0x0000 | 26 | #define SIRFSOC_TIMER_COUNTER_LO 0x0000 |
| 25 | #define SIRFSOC_TIMER_COUNTER_HI 0x0004 | 27 | #define SIRFSOC_TIMER_COUNTER_HI 0x0004 |
| 26 | #define SIRFSOC_TIMER_MATCH_0 0x0008 | 28 | #define SIRFSOC_TIMER_MATCH_0 0x0008 |
| @@ -173,7 +175,7 @@ static u64 notrace sirfsoc_read_sched_clock(void) | |||
| 173 | static void __init sirfsoc_clockevent_init(void) | 175 | static void __init sirfsoc_clockevent_init(void) |
| 174 | { | 176 | { |
| 175 | sirfsoc_clockevent.cpumask = cpumask_of(0); | 177 | sirfsoc_clockevent.cpumask = cpumask_of(0); |
| 176 | clockevents_config_and_register(&sirfsoc_clockevent, CLOCK_TICK_RATE, | 178 | clockevents_config_and_register(&sirfsoc_clockevent, PRIMA2_CLOCK_FREQ, |
| 177 | 2, -2); | 179 | 2, -2); |
| 178 | } | 180 | } |
| 179 | 181 | ||
| @@ -190,8 +192,8 @@ static void __init sirfsoc_prima2_timer_init(struct device_node *np) | |||
| 190 | 192 | ||
| 191 | rate = clk_get_rate(clk); | 193 | rate = clk_get_rate(clk); |
| 192 | 194 | ||
| 193 | BUG_ON(rate < CLOCK_TICK_RATE); | 195 | BUG_ON(rate < PRIMA2_CLOCK_FREQ); |
| 194 | BUG_ON(rate % CLOCK_TICK_RATE); | 196 | BUG_ON(rate % PRIMA2_CLOCK_FREQ); |
| 195 | 197 | ||
| 196 | sirfsoc_timer_base = of_iomap(np, 0); | 198 | sirfsoc_timer_base = of_iomap(np, 0); |
| 197 | if (!sirfsoc_timer_base) | 199 | if (!sirfsoc_timer_base) |
| @@ -199,14 +201,16 @@ static void __init sirfsoc_prima2_timer_init(struct device_node *np) | |||
| 199 | 201 | ||
| 200 | sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0); | 202 | sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0); |
| 201 | 203 | ||
| 202 | writel_relaxed(rate / CLOCK_TICK_RATE / 2 - 1, sirfsoc_timer_base + SIRFSOC_TIMER_DIV); | 204 | writel_relaxed(rate / PRIMA2_CLOCK_FREQ / 2 - 1, |
| 205 | sirfsoc_timer_base + SIRFSOC_TIMER_DIV); | ||
| 203 | writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO); | 206 | writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO); |
| 204 | writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI); | 207 | writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI); |
| 205 | writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS); | 208 | writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS); |
| 206 | 209 | ||
| 207 | BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE)); | 210 | BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, |
| 211 | PRIMA2_CLOCK_FREQ)); | ||
| 208 | 212 | ||
| 209 | sched_clock_register(sirfsoc_read_sched_clock, 64, CLOCK_TICK_RATE); | 213 | sched_clock_register(sirfsoc_read_sched_clock, 64, PRIMA2_CLOCK_FREQ); |
| 210 | 214 | ||
| 211 | BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq)); | 215 | BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq)); |
| 212 | 216 | ||
diff --git a/drivers/input/misc/ixp4xx-beeper.c b/drivers/input/misc/ixp4xx-beeper.c index 17ccba88d636..ed8e5e8449d3 100644 --- a/drivers/input/misc/ixp4xx-beeper.c +++ b/drivers/input/misc/ixp4xx-beeper.c | |||
| @@ -67,7 +67,7 @@ static int ixp4xx_spkr_event(struct input_dev *dev, unsigned int type, unsigned | |||
| 67 | } | 67 | } |
| 68 | 68 | ||
| 69 | if (value > 20 && value < 32767) | 69 | if (value > 20 && value < 32767) |
| 70 | count = (IXP4XX_TIMER_FREQ / (value * 4)) - 1; | 70 | count = (ixp4xx_timer_freq / (value * 4)) - 1; |
| 71 | 71 | ||
| 72 | ixp4xx_spkr_control(pin, count); | 72 | ixp4xx_spkr_control(pin, count); |
| 73 | 73 | ||
diff --git a/drivers/mfd/ab8500-core.c b/drivers/mfd/ab8500-core.c index aaff683cd37d..a8ee4a36a1d8 100644 --- a/drivers/mfd/ab8500-core.c +++ b/drivers/mfd/ab8500-core.c | |||
| @@ -592,7 +592,7 @@ static int ab8500_irq_init(struct ab8500 *ab8500, struct device_node *np) | |||
| 592 | 592 | ||
| 593 | /* If ->irq_base is zero this will give a linear mapping */ | 593 | /* If ->irq_base is zero this will give a linear mapping */ |
| 594 | ab8500->domain = irq_domain_add_simple(NULL, | 594 | ab8500->domain = irq_domain_add_simple(NULL, |
| 595 | num_irqs, ab8500->irq_base, | 595 | num_irqs, 0, |
| 596 | &ab8500_irq_ops, ab8500); | 596 | &ab8500_irq_ops, ab8500); |
| 597 | 597 | ||
| 598 | if (!ab8500->domain) { | 598 | if (!ab8500->domain) { |
| @@ -1583,14 +1583,13 @@ static int ab8500_probe(struct platform_device *pdev) | |||
| 1583 | if (!ab8500) | 1583 | if (!ab8500) |
| 1584 | return -ENOMEM; | 1584 | return -ENOMEM; |
| 1585 | 1585 | ||
| 1586 | if (plat) | ||
| 1587 | ab8500->irq_base = plat->irq_base; | ||
| 1588 | |||
| 1589 | ab8500->dev = &pdev->dev; | 1586 | ab8500->dev = &pdev->dev; |
| 1590 | 1587 | ||
| 1591 | resource = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | 1588 | resource = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
| 1592 | if (!resource) | 1589 | if (!resource) { |
| 1590 | dev_err(&pdev->dev, "no IRQ resource\n"); | ||
| 1593 | return -ENODEV; | 1591 | return -ENODEV; |
| 1592 | } | ||
| 1594 | 1593 | ||
| 1595 | ab8500->irq = resource->start; | 1594 | ab8500->irq = resource->start; |
| 1596 | 1595 | ||
| @@ -1612,8 +1611,10 @@ static int ab8500_probe(struct platform_device *pdev) | |||
| 1612 | else { | 1611 | else { |
| 1613 | ret = get_register_interruptible(ab8500, AB8500_MISC, | 1612 | ret = get_register_interruptible(ab8500, AB8500_MISC, |
| 1614 | AB8500_IC_NAME_REG, &value); | 1613 | AB8500_IC_NAME_REG, &value); |
| 1615 | if (ret < 0) | 1614 | if (ret < 0) { |
| 1615 | dev_err(&pdev->dev, "could not probe HW\n"); | ||
| 1616 | return ret; | 1616 | return ret; |
| 1617 | } | ||
| 1617 | 1618 | ||
| 1618 | ab8500->version = value; | 1619 | ab8500->version = value; |
| 1619 | } | 1620 | } |
| @@ -1759,30 +1760,30 @@ static int ab8500_probe(struct platform_device *pdev) | |||
| 1759 | if (is_ab9540(ab8500)) | 1760 | if (is_ab9540(ab8500)) |
| 1760 | ret = mfd_add_devices(ab8500->dev, 0, ab9540_devs, | 1761 | ret = mfd_add_devices(ab8500->dev, 0, ab9540_devs, |
| 1761 | ARRAY_SIZE(ab9540_devs), NULL, | 1762 | ARRAY_SIZE(ab9540_devs), NULL, |
| 1762 | ab8500->irq_base, ab8500->domain); | 1763 | 0, ab8500->domain); |
| 1763 | else if (is_ab8540(ab8500)) { | 1764 | else if (is_ab8540(ab8500)) { |
| 1764 | ret = mfd_add_devices(ab8500->dev, 0, ab8540_devs, | 1765 | ret = mfd_add_devices(ab8500->dev, 0, ab8540_devs, |
| 1765 | ARRAY_SIZE(ab8540_devs), NULL, | 1766 | ARRAY_SIZE(ab8540_devs), NULL, |
| 1766 | ab8500->irq_base, NULL); | 1767 | 0, ab8500->domain); |
| 1767 | if (ret) | 1768 | if (ret) |
| 1768 | return ret; | 1769 | return ret; |
| 1769 | 1770 | ||
| 1770 | if (is_ab8540_1p2_or_earlier(ab8500)) | 1771 | if (is_ab8540_1p2_or_earlier(ab8500)) |
| 1771 | ret = mfd_add_devices(ab8500->dev, 0, ab8540_cut1_devs, | 1772 | ret = mfd_add_devices(ab8500->dev, 0, ab8540_cut1_devs, |
| 1772 | ARRAY_SIZE(ab8540_cut1_devs), NULL, | 1773 | ARRAY_SIZE(ab8540_cut1_devs), NULL, |
| 1773 | ab8500->irq_base, NULL); | 1774 | 0, ab8500->domain); |
| 1774 | else /* ab8540 >= cut2 */ | 1775 | else /* ab8540 >= cut2 */ |
| 1775 | ret = mfd_add_devices(ab8500->dev, 0, ab8540_cut2_devs, | 1776 | ret = mfd_add_devices(ab8500->dev, 0, ab8540_cut2_devs, |
| 1776 | ARRAY_SIZE(ab8540_cut2_devs), NULL, | 1777 | ARRAY_SIZE(ab8540_cut2_devs), NULL, |
| 1777 | ab8500->irq_base, NULL); | 1778 | 0, ab8500->domain); |
| 1778 | } else if (is_ab8505(ab8500)) | 1779 | } else if (is_ab8505(ab8500)) |
| 1779 | ret = mfd_add_devices(ab8500->dev, 0, ab8505_devs, | 1780 | ret = mfd_add_devices(ab8500->dev, 0, ab8505_devs, |
| 1780 | ARRAY_SIZE(ab8505_devs), NULL, | 1781 | ARRAY_SIZE(ab8505_devs), NULL, |
| 1781 | ab8500->irq_base, ab8500->domain); | 1782 | 0, ab8500->domain); |
| 1782 | else | 1783 | else |
| 1783 | ret = mfd_add_devices(ab8500->dev, 0, ab8500_devs, | 1784 | ret = mfd_add_devices(ab8500->dev, 0, ab8500_devs, |
| 1784 | ARRAY_SIZE(ab8500_devs), NULL, | 1785 | ARRAY_SIZE(ab8500_devs), NULL, |
| 1785 | ab8500->irq_base, ab8500->domain); | 1786 | 0, ab8500->domain); |
| 1786 | if (ret) | 1787 | if (ret) |
| 1787 | return ret; | 1788 | return ret; |
| 1788 | 1789 | ||
| @@ -1790,7 +1791,7 @@ static int ab8500_probe(struct platform_device *pdev) | |||
| 1790 | /* Add battery management devices */ | 1791 | /* Add battery management devices */ |
| 1791 | ret = mfd_add_devices(ab8500->dev, 0, ab8500_bm_devs, | 1792 | ret = mfd_add_devices(ab8500->dev, 0, ab8500_bm_devs, |
| 1792 | ARRAY_SIZE(ab8500_bm_devs), NULL, | 1793 | ARRAY_SIZE(ab8500_bm_devs), NULL, |
| 1793 | ab8500->irq_base, ab8500->domain); | 1794 | 0, ab8500->domain); |
| 1794 | if (ret) | 1795 | if (ret) |
| 1795 | dev_err(ab8500->dev, "error adding bm devices\n"); | 1796 | dev_err(ab8500->dev, "error adding bm devices\n"); |
| 1796 | } | 1797 | } |
diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c index e43e6e821117..7694e0700d34 100644 --- a/drivers/mfd/db8500-prcmu.c +++ b/drivers/mfd/db8500-prcmu.c | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | #include <linux/bitops.h> | 25 | #include <linux/bitops.h> |
| 26 | #include <linux/fs.h> | 26 | #include <linux/fs.h> |
| 27 | #include <linux/of.h> | 27 | #include <linux/of.h> |
| 28 | #include <linux/of_irq.h> | ||
| 28 | #include <linux/platform_device.h> | 29 | #include <linux/platform_device.h> |
| 29 | #include <linux/uaccess.h> | 30 | #include <linux/uaccess.h> |
| 30 | #include <linux/mfd/core.h> | 31 | #include <linux/mfd/core.h> |
| @@ -2678,16 +2679,12 @@ static struct irq_domain_ops db8500_irq_ops = { | |||
| 2678 | .xlate = irq_domain_xlate_twocell, | 2679 | .xlate = irq_domain_xlate_twocell, |
| 2679 | }; | 2680 | }; |
| 2680 | 2681 | ||
| 2681 | static int db8500_irq_init(struct device_node *np, int irq_base) | 2682 | static int db8500_irq_init(struct device_node *np) |
| 2682 | { | 2683 | { |
| 2683 | int i; | 2684 | int i; |
| 2684 | 2685 | ||
| 2685 | /* In the device tree case, just take some IRQs */ | ||
| 2686 | if (np) | ||
| 2687 | irq_base = 0; | ||
| 2688 | |||
| 2689 | db8500_irq_domain = irq_domain_add_simple( | 2686 | db8500_irq_domain = irq_domain_add_simple( |
| 2690 | np, NUM_PRCMU_WAKEUPS, irq_base, | 2687 | np, NUM_PRCMU_WAKEUPS, 0, |
| 2691 | &db8500_irq_ops, NULL); | 2688 | &db8500_irq_ops, NULL); |
| 2692 | 2689 | ||
| 2693 | if (!db8500_irq_domain) { | 2690 | if (!db8500_irq_domain) { |
| @@ -3114,10 +3111,10 @@ static void db8500_prcmu_update_cpufreq(void) | |||
| 3114 | } | 3111 | } |
| 3115 | 3112 | ||
| 3116 | static int db8500_prcmu_register_ab8500(struct device *parent, | 3113 | static int db8500_prcmu_register_ab8500(struct device *parent, |
| 3117 | struct ab8500_platform_data *pdata, | 3114 | struct ab8500_platform_data *pdata) |
| 3118 | int irq) | ||
| 3119 | { | 3115 | { |
| 3120 | struct resource ab8500_resource = DEFINE_RES_IRQ(irq); | 3116 | struct device_node *np; |
| 3117 | struct resource ab8500_resource; | ||
| 3121 | struct mfd_cell ab8500_cell = { | 3118 | struct mfd_cell ab8500_cell = { |
| 3122 | .name = "ab8500-core", | 3119 | .name = "ab8500-core", |
| 3123 | .of_compatible = "stericsson,ab8500", | 3120 | .of_compatible = "stericsson,ab8500", |
| @@ -3128,6 +3125,20 @@ static int db8500_prcmu_register_ab8500(struct device *parent, | |||
| 3128 | .num_resources = 1, | 3125 | .num_resources = 1, |
| 3129 | }; | 3126 | }; |
| 3130 | 3127 | ||
| 3128 | if (!parent->of_node) | ||
| 3129 | return -ENODEV; | ||
| 3130 | |||
| 3131 | /* Look up the device node, sneak the IRQ out of it */ | ||
| 3132 | for_each_child_of_node(parent->of_node, np) { | ||
| 3133 | if (of_device_is_compatible(np, ab8500_cell.of_compatible)) | ||
| 3134 | break; | ||
| 3135 | } | ||
| 3136 | if (!np) { | ||
| 3137 | dev_info(parent, "could not find AB8500 node in the device tree\n"); | ||
| 3138 | return -ENODEV; | ||
| 3139 | } | ||
| 3140 | of_irq_to_resource_table(np, &ab8500_resource, 1); | ||
| 3141 | |||
| 3131 | return mfd_add_devices(parent, 0, &ab8500_cell, 1, NULL, 0, NULL); | 3142 | return mfd_add_devices(parent, 0, &ab8500_cell, 1, NULL, 0, NULL); |
| 3132 | } | 3143 | } |
| 3133 | 3144 | ||
| @@ -3180,7 +3191,7 @@ static int db8500_prcmu_probe(struct platform_device *pdev) | |||
| 3180 | goto no_irq_return; | 3191 | goto no_irq_return; |
| 3181 | } | 3192 | } |
| 3182 | 3193 | ||
| 3183 | db8500_irq_init(np, pdata->irq_base); | 3194 | db8500_irq_init(np); |
| 3184 | 3195 | ||
| 3185 | prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET); | 3196 | prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET); |
| 3186 | 3197 | ||
| @@ -3205,8 +3216,7 @@ static int db8500_prcmu_probe(struct platform_device *pdev) | |||
| 3205 | } | 3216 | } |
| 3206 | } | 3217 | } |
| 3207 | 3218 | ||
| 3208 | err = db8500_prcmu_register_ab8500(&pdev->dev, pdata->ab_platdata, | 3219 | err = db8500_prcmu_register_ab8500(&pdev->dev, pdata->ab_platdata); |
| 3209 | pdata->ab_irq); | ||
| 3210 | if (err) { | 3220 | if (err) { |
| 3211 | mfd_remove_devices(&pdev->dev); | 3221 | mfd_remove_devices(&pdev->dev); |
| 3212 | pr_err("prcmu: Failed to add ab8500 subdevice\n"); | 3222 | pr_err("prcmu: Failed to add ab8500 subdevice\n"); |
diff --git a/drivers/rtc/rtc-at91sam9.c b/drivers/rtc/rtc-at91sam9.c index 309b8b342d9c..596374304532 100644 --- a/drivers/rtc/rtc-at91sam9.c +++ b/drivers/rtc/rtc-at91sam9.c | |||
| @@ -24,7 +24,7 @@ | |||
| 24 | 24 | ||
| 25 | #include <mach/at91_rtt.h> | 25 | #include <mach/at91_rtt.h> |
| 26 | #include <mach/cpu.h> | 26 | #include <mach/cpu.h> |
| 27 | 27 | #include <mach/hardware.h> | |
| 28 | 28 | ||
| 29 | /* | 29 | /* |
| 30 | * This driver uses two configurable hardware resources that live in the | 30 | * This driver uses two configurable hardware resources that live in the |
diff --git a/drivers/rtc/rtc-pxa.c b/drivers/rtc/rtc-pxa.c index a355f2b82bb8..cccbf9d89729 100644 --- a/drivers/rtc/rtc-pxa.c +++ b/drivers/rtc/rtc-pxa.c | |||
| @@ -32,7 +32,6 @@ | |||
| 32 | 32 | ||
| 33 | #include <mach/hardware.h> | 33 | #include <mach/hardware.h> |
| 34 | 34 | ||
| 35 | #define TIMER_FREQ CLOCK_TICK_RATE | ||
| 36 | #define RTC_DEF_DIVIDER (32768 - 1) | 35 | #define RTC_DEF_DIVIDER (32768 - 1) |
| 37 | #define RTC_DEF_TRIM 0 | 36 | #define RTC_DEF_TRIM 0 |
| 38 | #define MAXFREQ_PERIODIC 1000 | 37 | #define MAXFREQ_PERIODIC 1000 |
diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c index a49f10d269b2..91c0d8839570 100644 --- a/drivers/tty/serial/atmel_serial.c +++ b/drivers/tty/serial/atmel_serial.c | |||
| @@ -35,21 +35,18 @@ | |||
| 35 | #include <linux/platform_device.h> | 35 | #include <linux/platform_device.h> |
| 36 | #include <linux/of.h> | 36 | #include <linux/of.h> |
| 37 | #include <linux/of_device.h> | 37 | #include <linux/of_device.h> |
| 38 | #include <linux/of_gpio.h> | ||
| 38 | #include <linux/dma-mapping.h> | 39 | #include <linux/dma-mapping.h> |
| 39 | #include <linux/atmel_pdc.h> | 40 | #include <linux/atmel_pdc.h> |
| 40 | #include <linux/atmel_serial.h> | 41 | #include <linux/atmel_serial.h> |
| 41 | #include <linux/uaccess.h> | 42 | #include <linux/uaccess.h> |
| 42 | #include <linux/platform_data/atmel.h> | 43 | #include <linux/platform_data/atmel.h> |
| 43 | #include <linux/timer.h> | 44 | #include <linux/timer.h> |
| 45 | #include <linux/gpio.h> | ||
| 44 | 46 | ||
| 45 | #include <asm/io.h> | 47 | #include <asm/io.h> |
| 46 | #include <asm/ioctls.h> | 48 | #include <asm/ioctls.h> |
| 47 | 49 | ||
| 48 | #ifdef CONFIG_ARM | ||
| 49 | #include <mach/cpu.h> | ||
| 50 | #include <asm/gpio.h> | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #define PDC_BUFFER_SIZE 512 | 50 | #define PDC_BUFFER_SIZE 512 |
| 54 | /* Revisit: We should calculate this based on the actual port settings */ | 51 | /* Revisit: We should calculate this based on the actual port settings */ |
| 55 | #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */ | 52 | #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */ |
| @@ -168,6 +165,7 @@ struct atmel_uart_port { | |||
| 168 | struct circ_buf rx_ring; | 165 | struct circ_buf rx_ring; |
| 169 | 166 | ||
| 170 | struct serial_rs485 rs485; /* rs485 settings */ | 167 | struct serial_rs485 rs485; /* rs485 settings */ |
| 168 | int rts_gpio; /* optional RTS GPIO */ | ||
| 171 | unsigned int tx_done_mask; | 169 | unsigned int tx_done_mask; |
| 172 | bool is_usart; /* usart or uart */ | 170 | bool is_usart; /* usart or uart */ |
| 173 | struct timer_list uart_timer; /* uart timer */ | 171 | struct timer_list uart_timer; /* uart timer */ |
| @@ -301,20 +299,16 @@ static void atmel_set_mctrl(struct uart_port *port, u_int mctrl) | |||
| 301 | unsigned int mode; | 299 | unsigned int mode; |
| 302 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | 300 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
| 303 | 301 | ||
| 304 | #ifdef CONFIG_ARCH_AT91RM9200 | 302 | /* |
| 305 | if (cpu_is_at91rm9200()) { | 303 | * AT91RM9200 Errata #39: RTS0 is not internally connected |
| 306 | /* | 304 | * to PA21. We need to drive the pin as a GPIO. |
| 307 | * AT91RM9200 Errata #39: RTS0 is not internally connected | 305 | */ |
| 308 | * to PA21. We need to drive the pin manually. | 306 | if (gpio_is_valid(atmel_port->rts_gpio)) { |
| 309 | */ | 307 | if (mctrl & TIOCM_RTS) |
| 310 | if (port->mapbase == AT91RM9200_BASE_US0) { | 308 | gpio_set_value(atmel_port->rts_gpio, 0); |
| 311 | if (mctrl & TIOCM_RTS) | 309 | else |
| 312 | at91_set_gpio_value(AT91_PIN_PA21, 0); | 310 | gpio_set_value(atmel_port->rts_gpio, 1); |
| 313 | else | ||
| 314 | at91_set_gpio_value(AT91_PIN_PA21, 1); | ||
| 315 | } | ||
| 316 | } | 311 | } |
| 317 | #endif | ||
| 318 | 312 | ||
| 319 | if (mctrl & TIOCM_RTS) | 313 | if (mctrl & TIOCM_RTS) |
| 320 | control |= ATMEL_US_RTSEN; | 314 | control |= ATMEL_US_RTSEN; |
| @@ -2389,6 +2383,25 @@ static int atmel_serial_probe(struct platform_device *pdev) | |||
| 2389 | port = &atmel_ports[ret]; | 2383 | port = &atmel_ports[ret]; |
| 2390 | port->backup_imr = 0; | 2384 | port->backup_imr = 0; |
| 2391 | port->uart.line = ret; | 2385 | port->uart.line = ret; |
| 2386 | port->rts_gpio = -EINVAL; /* Invalid, zero could be valid */ | ||
| 2387 | if (pdata) | ||
| 2388 | port->rts_gpio = pdata->rts_gpio; | ||
| 2389 | else if (np) | ||
| 2390 | port->rts_gpio = of_get_named_gpio(np, "rts-gpios", 0); | ||
| 2391 | |||
| 2392 | if (gpio_is_valid(port->rts_gpio)) { | ||
| 2393 | ret = devm_gpio_request(&pdev->dev, port->rts_gpio, "RTS"); | ||
| 2394 | if (ret) { | ||
| 2395 | dev_err(&pdev->dev, "error requesting RTS GPIO\n"); | ||
| 2396 | goto err; | ||
| 2397 | } | ||
| 2398 | /* Default to 1 as RTS is active low */ | ||
| 2399 | ret = gpio_direction_output(port->rts_gpio, 1); | ||
| 2400 | if (ret) { | ||
| 2401 | dev_err(&pdev->dev, "error setting up RTS GPIO\n"); | ||
| 2402 | goto err; | ||
| 2403 | } | ||
| 2404 | } | ||
| 2392 | 2405 | ||
| 2393 | ret = atmel_init_port(port, pdev); | 2406 | ret = atmel_init_port(port, pdev); |
| 2394 | if (ret) | 2407 | if (ret) |
diff --git a/include/dt-bindings/pinctrl/am43xx.h b/include/dt-bindings/pinctrl/am43xx.h index eb6c366adfba..9c2e4f82381e 100644 --- a/include/dt-bindings/pinctrl/am43xx.h +++ b/include/dt-bindings/pinctrl/am43xx.h | |||
| @@ -13,6 +13,7 @@ | |||
| 13 | #define MUX_MODE5 5 | 13 | #define MUX_MODE5 5 |
| 14 | #define MUX_MODE6 6 | 14 | #define MUX_MODE6 6 |
| 15 | #define MUX_MODE7 7 | 15 | #define MUX_MODE7 7 |
| 16 | #define MUX_MODE8 8 | ||
| 16 | 17 | ||
| 17 | #define PULL_DISABLE (1 << 16) | 18 | #define PULL_DISABLE (1 << 16) |
| 18 | #define PULL_UP (1 << 17) | 19 | #define PULL_UP (1 << 17) |
diff --git a/include/linux/mfd/abx500/ab8500.h b/include/linux/mfd/abx500/ab8500.h index a86ca1406fb8..4e7fe7417fc9 100644 --- a/include/linux/mfd/abx500/ab8500.h +++ b/include/linux/mfd/abx500/ab8500.h | |||
| @@ -347,7 +347,6 @@ struct ab8500 { | |||
| 347 | struct mutex lock; | 347 | struct mutex lock; |
| 348 | struct mutex irq_lock; | 348 | struct mutex irq_lock; |
| 349 | atomic_t transfer_ongoing; | 349 | atomic_t transfer_ongoing; |
| 350 | int irq_base; | ||
| 351 | int irq; | 350 | int irq; |
| 352 | struct irq_domain *domain; | 351 | struct irq_domain *domain; |
| 353 | enum ab8500_version version; | 352 | enum ab8500_version version; |
| @@ -378,7 +377,6 @@ struct ab8500_sysctrl_platform_data; | |||
| 378 | * @regulator: machine-specific constraints for regulators | 377 | * @regulator: machine-specific constraints for regulators |
| 379 | */ | 378 | */ |
| 380 | struct ab8500_platform_data { | 379 | struct ab8500_platform_data { |
| 381 | int irq_base; | ||
| 382 | void (*init) (struct ab8500 *); | 380 | void (*init) (struct ab8500 *); |
| 383 | struct ab8500_regulator_platform_data *regulator; | 381 | struct ab8500_regulator_platform_data *regulator; |
| 384 | struct ab8500_codec_platform_data *codec; | 382 | struct ab8500_codec_platform_data *codec; |
diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h index 060e11256fbc..bf5109d38a26 100644 --- a/include/linux/mfd/dbx500-prcmu.h +++ b/include/linux/mfd/dbx500-prcmu.h | |||
| @@ -183,8 +183,6 @@ struct prcmu_pdata | |||
| 183 | bool enable_set_ddr_opp; | 183 | bool enable_set_ddr_opp; |
| 184 | bool enable_ape_opp_100_voltage; | 184 | bool enable_ape_opp_100_voltage; |
| 185 | struct ab8500_platform_data *ab_platdata; | 185 | struct ab8500_platform_data *ab_platdata; |
| 186 | int ab_irq; | ||
| 187 | int irq_base; | ||
| 188 | u32 version_offset; | 186 | u32 version_offset; |
| 189 | u32 legacy_offset; | 187 | u32 legacy_offset; |
| 190 | u32 adt_offset; | 188 | u32 adt_offset; |
diff --git a/include/linux/platform_data/atmel.h b/include/linux/platform_data/atmel.h index cea9f70133c5..e26b0c14edea 100644 --- a/include/linux/platform_data/atmel.h +++ b/include/linux/platform_data/atmel.h | |||
| @@ -84,6 +84,7 @@ struct atmel_uart_data { | |||
| 84 | short use_dma_rx; /* use receive DMA? */ | 84 | short use_dma_rx; /* use receive DMA? */ |
| 85 | void __iomem *regs; /* virt. base address, if any */ | 85 | void __iomem *regs; /* virt. base address, if any */ |
| 86 | struct serial_rs485 rs485; /* rs485 settings */ | 86 | struct serial_rs485 rs485; /* rs485 settings */ |
| 87 | int rts_gpio; /* optional RTS GPIO */ | ||
| 87 | }; | 88 | }; |
| 88 | 89 | ||
| 89 | /* Touchscreen Controller */ | 90 | /* Touchscreen Controller */ |