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-rw-r--r--arch/i386/kernel/cpu/intel_cacheinfo.c8
1 files changed, 1 insertions, 7 deletions
diff --git a/arch/i386/kernel/cpu/intel_cacheinfo.c b/arch/i386/kernel/cpu/intel_cacheinfo.c
index c802206274c2..7cc84a4a6df9 100644
--- a/arch/i386/kernel/cpu/intel_cacheinfo.c
+++ b/arch/i386/kernel/cpu/intel_cacheinfo.c
@@ -278,13 +278,7 @@ unsigned int __devinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
278 if ( l3 ) 278 if ( l3 )
279 printk(KERN_INFO "CPU: L3 cache: %dK\n", l3); 279 printk(KERN_INFO "CPU: L3 cache: %dK\n", l3);
280 280
281 /* 281 c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d));
282 * This assumes the L3 cache is shared; it typically lives in
283 * the northbridge. The L1 caches are included by the L2
284 * cache, and so should not be included for the purpose of
285 * SMP switching weights.
286 */
287 c->x86_cache_size = l2 ? l2 : (l1i+l1d);
288 } 282 }
289 283
290 return l2; 284 return l2;