diff options
| -rw-r--r-- | arch/mips/cavium-octeon/octeon-irq.c | 45 |
1 files changed, 43 insertions, 2 deletions
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index 01bb01cf49ee..1b25998fe1ea 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c | |||
| @@ -752,6 +752,18 @@ static struct irq_chip octeon_irq_chip_ciu_v2 = { | |||
| 752 | .name = "CIU", | 752 | .name = "CIU", |
| 753 | .irq_enable = octeon_irq_ciu_enable_v2, | 753 | .irq_enable = octeon_irq_ciu_enable_v2, |
| 754 | .irq_disable = octeon_irq_ciu_disable_all_v2, | 754 | .irq_disable = octeon_irq_ciu_disable_all_v2, |
| 755 | .irq_mask = octeon_irq_ciu_disable_local_v2, | ||
| 756 | .irq_unmask = octeon_irq_ciu_enable_v2, | ||
| 757 | #ifdef CONFIG_SMP | ||
| 758 | .irq_set_affinity = octeon_irq_ciu_set_affinity_v2, | ||
| 759 | .irq_cpu_offline = octeon_irq_cpu_offline_ciu, | ||
| 760 | #endif | ||
| 761 | }; | ||
| 762 | |||
| 763 | static struct irq_chip octeon_irq_chip_ciu_v2_edge = { | ||
| 764 | .name = "CIU", | ||
| 765 | .irq_enable = octeon_irq_ciu_enable_v2, | ||
| 766 | .irq_disable = octeon_irq_ciu_disable_all_v2, | ||
| 755 | .irq_ack = octeon_irq_ciu_ack, | 767 | .irq_ack = octeon_irq_ciu_ack, |
| 756 | .irq_mask = octeon_irq_ciu_disable_local_v2, | 768 | .irq_mask = octeon_irq_ciu_disable_local_v2, |
| 757 | .irq_unmask = octeon_irq_ciu_enable_v2, | 769 | .irq_unmask = octeon_irq_ciu_enable_v2, |
| @@ -765,6 +777,18 @@ static struct irq_chip octeon_irq_chip_ciu = { | |||
| 765 | .name = "CIU", | 777 | .name = "CIU", |
| 766 | .irq_enable = octeon_irq_ciu_enable, | 778 | .irq_enable = octeon_irq_ciu_enable, |
| 767 | .irq_disable = octeon_irq_ciu_disable_all, | 779 | .irq_disable = octeon_irq_ciu_disable_all, |
| 780 | .irq_mask = octeon_irq_ciu_disable_local, | ||
| 781 | .irq_unmask = octeon_irq_ciu_enable, | ||
| 782 | #ifdef CONFIG_SMP | ||
| 783 | .irq_set_affinity = octeon_irq_ciu_set_affinity, | ||
| 784 | .irq_cpu_offline = octeon_irq_cpu_offline_ciu, | ||
| 785 | #endif | ||
| 786 | }; | ||
| 787 | |||
| 788 | static struct irq_chip octeon_irq_chip_ciu_edge = { | ||
| 789 | .name = "CIU", | ||
| 790 | .irq_enable = octeon_irq_ciu_enable, | ||
| 791 | .irq_disable = octeon_irq_ciu_disable_all, | ||
| 768 | .irq_ack = octeon_irq_ciu_ack, | 792 | .irq_ack = octeon_irq_ciu_ack, |
| 769 | .irq_mask = octeon_irq_ciu_disable_local, | 793 | .irq_mask = octeon_irq_ciu_disable_local, |
| 770 | .irq_unmask = octeon_irq_ciu_enable, | 794 | .irq_unmask = octeon_irq_ciu_enable, |
| @@ -984,6 +1008,7 @@ static int octeon_irq_ciu_xlat(struct irq_domain *d, | |||
| 984 | } | 1008 | } |
| 985 | 1009 | ||
| 986 | static struct irq_chip *octeon_irq_ciu_chip; | 1010 | static struct irq_chip *octeon_irq_ciu_chip; |
| 1011 | static struct irq_chip *octeon_irq_ciu_chip_edge; | ||
| 987 | static struct irq_chip *octeon_irq_gpio_chip; | 1012 | static struct irq_chip *octeon_irq_gpio_chip; |
| 988 | 1013 | ||
| 989 | static bool octeon_irq_virq_in_range(unsigned int virq) | 1014 | static bool octeon_irq_virq_in_range(unsigned int virq) |
| @@ -1014,7 +1039,7 @@ static int octeon_irq_ciu_map(struct irq_domain *d, | |||
| 1014 | 1039 | ||
| 1015 | if (octeon_irq_ciu_is_edge(line, bit)) | 1040 | if (octeon_irq_ciu_is_edge(line, bit)) |
| 1016 | octeon_irq_set_ciu_mapping(virq, line, bit, 0, | 1041 | octeon_irq_set_ciu_mapping(virq, line, bit, 0, |
| 1017 | octeon_irq_ciu_chip, | 1042 | octeon_irq_ciu_chip_edge, |
| 1018 | handle_edge_irq); | 1043 | handle_edge_irq); |
| 1019 | else | 1044 | else |
| 1020 | octeon_irq_set_ciu_mapping(virq, line, bit, 0, | 1045 | octeon_irq_set_ciu_mapping(virq, line, bit, 0, |
| @@ -1196,6 +1221,7 @@ static void __init octeon_irq_init_ciu(void) | |||
| 1196 | { | 1221 | { |
| 1197 | unsigned int i; | 1222 | unsigned int i; |
| 1198 | struct irq_chip *chip; | 1223 | struct irq_chip *chip; |
| 1224 | struct irq_chip *chip_edge; | ||
| 1199 | struct irq_chip *chip_mbox; | 1225 | struct irq_chip *chip_mbox; |
| 1200 | struct irq_chip *chip_wd; | 1226 | struct irq_chip *chip_wd; |
| 1201 | struct device_node *gpio_node; | 1227 | struct device_node *gpio_node; |
| @@ -1212,16 +1238,19 @@ static void __init octeon_irq_init_ciu(void) | |||
| 1212 | OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X) || | 1238 | OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X) || |
| 1213 | OCTEON_IS_OCTEON2() || OCTEON_IS_OCTEON3()) { | 1239 | OCTEON_IS_OCTEON2() || OCTEON_IS_OCTEON3()) { |
| 1214 | chip = &octeon_irq_chip_ciu_v2; | 1240 | chip = &octeon_irq_chip_ciu_v2; |
| 1241 | chip_edge = &octeon_irq_chip_ciu_v2_edge; | ||
| 1215 | chip_mbox = &octeon_irq_chip_ciu_mbox_v2; | 1242 | chip_mbox = &octeon_irq_chip_ciu_mbox_v2; |
| 1216 | chip_wd = &octeon_irq_chip_ciu_wd_v2; | 1243 | chip_wd = &octeon_irq_chip_ciu_wd_v2; |
| 1217 | octeon_irq_gpio_chip = &octeon_irq_chip_ciu_gpio_v2; | 1244 | octeon_irq_gpio_chip = &octeon_irq_chip_ciu_gpio_v2; |
| 1218 | } else { | 1245 | } else { |
| 1219 | chip = &octeon_irq_chip_ciu; | 1246 | chip = &octeon_irq_chip_ciu; |
| 1247 | chip_edge = &octeon_irq_chip_ciu_edge; | ||
| 1220 | chip_mbox = &octeon_irq_chip_ciu_mbox; | 1248 | chip_mbox = &octeon_irq_chip_ciu_mbox; |
| 1221 | chip_wd = &octeon_irq_chip_ciu_wd; | 1249 | chip_wd = &octeon_irq_chip_ciu_wd; |
| 1222 | octeon_irq_gpio_chip = &octeon_irq_chip_ciu_gpio; | 1250 | octeon_irq_gpio_chip = &octeon_irq_chip_ciu_gpio; |
| 1223 | } | 1251 | } |
| 1224 | octeon_irq_ciu_chip = chip; | 1252 | octeon_irq_ciu_chip = chip; |
| 1253 | octeon_irq_ciu_chip_edge = chip_edge; | ||
| 1225 | octeon_irq_ip4 = octeon_irq_ip4_mask; | 1254 | octeon_irq_ip4 = octeon_irq_ip4_mask; |
| 1226 | 1255 | ||
| 1227 | /* Mips internal */ | 1256 | /* Mips internal */ |
| @@ -1473,6 +1502,18 @@ static struct irq_chip octeon_irq_chip_ciu2 = { | |||
| 1473 | .name = "CIU2-E", | 1502 | .name = "CIU2-E", |
| 1474 | .irq_enable = octeon_irq_ciu2_enable, | 1503 | .irq_enable = octeon_irq_ciu2_enable, |
| 1475 | .irq_disable = octeon_irq_ciu2_disable_all, | 1504 | .irq_disable = octeon_irq_ciu2_disable_all, |
| 1505 | .irq_mask = octeon_irq_ciu2_disable_local, | ||
| 1506 | .irq_unmask = octeon_irq_ciu2_enable, | ||
| 1507 | #ifdef CONFIG_SMP | ||
| 1508 | .irq_set_affinity = octeon_irq_ciu2_set_affinity, | ||
| 1509 | .irq_cpu_offline = octeon_irq_cpu_offline_ciu, | ||
| 1510 | #endif | ||
| 1511 | }; | ||
| 1512 | |||
| 1513 | static struct irq_chip octeon_irq_chip_ciu2_edge = { | ||
| 1514 | .name = "CIU2-E", | ||
| 1515 | .irq_enable = octeon_irq_ciu2_enable, | ||
| 1516 | .irq_disable = octeon_irq_ciu2_disable_all, | ||
| 1476 | .irq_ack = octeon_irq_ciu2_ack, | 1517 | .irq_ack = octeon_irq_ciu2_ack, |
| 1477 | .irq_mask = octeon_irq_ciu2_disable_local, | 1518 | .irq_mask = octeon_irq_ciu2_disable_local, |
| 1478 | .irq_unmask = octeon_irq_ciu2_enable, | 1519 | .irq_unmask = octeon_irq_ciu2_enable, |
| @@ -1582,7 +1623,7 @@ static int octeon_irq_ciu2_map(struct irq_domain *d, | |||
| 1582 | 1623 | ||
| 1583 | if (octeon_irq_ciu2_is_edge(line, bit)) | 1624 | if (octeon_irq_ciu2_is_edge(line, bit)) |
| 1584 | octeon_irq_set_ciu_mapping(virq, line, bit, 0, | 1625 | octeon_irq_set_ciu_mapping(virq, line, bit, 0, |
| 1585 | &octeon_irq_chip_ciu2, | 1626 | &octeon_irq_chip_ciu2_edge, |
| 1586 | handle_edge_irq); | 1627 | handle_edge_irq); |
| 1587 | else | 1628 | else |
| 1588 | octeon_irq_set_ciu_mapping(virq, line, bit, 0, | 1629 | octeon_irq_set_ciu_mapping(virq, line, bit, 0, |
