4 files changed, 153 insertions, 78 deletions

diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 47d46c6d8468..a6f67ec8882f 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -27,7 +27,7 @@ config PCI_TEGRA
 
 config PCI_RCAR_GEN2
         bool "Renesas R-Car Gen2 Internal PCI controller"
-        depends on ARM && (ARCH_R8A7790 || ARCH_R8A7791 || COMPILE_TEST)
+        depends on ARCH_SHMOBILE || (ARM && COMPILE_TEST)
         help
           Say Y here if you want internal PCI support on R-Car Gen2 SoC.
           There are 3 internal PCI controllers available with a single
diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
index e8663a8c3406..ee082509b0ba 100644
--- a/drivers/pci/host/pci-imx6.c
+++ b/drivers/pci/host/pci-imx6.c
@@ -424,20 +424,40 @@ static void imx6_pcie_reset_phy(struct pcie_port *pp)
 
 static int imx6_pcie_link_up(struct pcie_port *pp)
 {
-        u32 rc, ltssm, rx_valid;
+        u32 rc, debug_r0, rx_valid;
+        int count = 5;
 
         /*
-         * Test if the PHY reports that the link is up and also that
-         * the link training finished.  It might happen that the PHY
-         * reports the link is already up, but the link training bit
-         * is still set, so make sure to check the training is done
-         * as well here.
+         * Test if the PHY reports that the link is up and also that the LTSSM
+         * training finished. There are three possible states of the link when
+         * this code is called:
+         * 1) The link is DOWN (unlikely)
+         *     The link didn't come up yet for some reason. This usually means
+         *     we have a real problem somewhere. Reset the PHY and exit. This
+         *     state calls for inspection of the DEBUG registers.
+         * 2) The link is UP, but still in LTSSM training
+         *     Wait for the training to finish, which should take a very short
+         *     time. If the training does not finish, we have a problem and we
+         *     need to inspect the DEBUG registers. If the training does finish,
+         *     the link is up and operating correctly.
+         * 3) The link is UP and no longer in LTSSM training
+         *     The link is up and operating correctly.
          */
-        rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
-        if ((rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP) &&
-            !(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING))
-                return 1;
-
+        while (1) {
+                rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
+                if (!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP))
+                        break;
+                if (!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING))
+                        return 1;
+                if (!count--)
+                        break;
+                dev_dbg(pp->dev, "Link is up, but still in training\n");
+                /*
+                 * Wait a little bit, then re-check if the link finished
+                 * the training.
+                 */
+                usleep_range(1000, 2000);
+        }
         /*
          * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
          * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
@@ -446,15 +466,16 @@ static int imx6_pcie_link_up(struct pcie_port *pp)
          * to gen2 is stuck
          */
         pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
-        ltssm = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F;
+        debug_r0 = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0);
 
         if (rx_valid & 0x01)
                 return 0;
 
-        if (ltssm != 0x0d)
+        if ((debug_r0 & 0x3f) != 0x0d)
                 return 0;
 
         dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");
+        dev_dbg(pp->dev, "debug_r0=%08x debug_r1=%08x\n", debug_r0, rc);
 
         imx6_pcie_reset_phy(pp);
 
diff --git a/drivers/pci/host/pci-rcar-gen2.c b/drivers/pci/host/pci-rcar-gen2.c
index ceec147baec3..fd3e3ab56509 100644
--- a/drivers/pci/host/pci-rcar-gen2.c
+++ b/drivers/pci/host/pci-rcar-gen2.c
@@ -18,6 +18,7 @@
 #include <linux/pci.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/sizes.h>
 #include <linux/slab.h>
 
 /* AHB-PCI Bridge PCI communication registers */
@@ -39,9 +40,26 @@
 
 #define RCAR_PCI_INT_ENABLE_REG         (RCAR_AHBPCI_PCICOM_OFFSET + 0x20)
 #define RCAR_PCI_INT_STATUS_REG         (RCAR_AHBPCI_PCICOM_OFFSET + 0x24)
+#define RCAR_PCI_INT_SIGTABORT          (1 << 0)
+#define RCAR_PCI_INT_SIGRETABORT        (1 << 1)
+#define RCAR_PCI_INT_REMABORT           (1 << 2)
+#define RCAR_PCI_INT_PERR               (1 << 3)
+#define RCAR_PCI_INT_SIGSERR            (1 << 4)
+#define RCAR_PCI_INT_RESERR             (1 << 5)
+#define RCAR_PCI_INT_WIN1ERR            (1 << 12)
+#define RCAR_PCI_INT_WIN2ERR            (1 << 13)
 #define RCAR_PCI_INT_A                  (1 << 16)
 #define RCAR_PCI_INT_B                  (1 << 17)
 #define RCAR_PCI_INT_PME                (1 << 19)
+#define RCAR_PCI_INT_ALLERRORS (RCAR_PCI_INT_SIGTABORT          | \
+                                RCAR_PCI_INT_SIGRETABORT        | \
+                                RCAR_PCI_INT_SIGRETABORT        | \
+                                RCAR_PCI_INT_REMABORT           | \
+                                RCAR_PCI_INT_PERR               | \
+                                RCAR_PCI_INT_SIGSERR            | \
+                                RCAR_PCI_INT_RESERR             | \
+                                RCAR_PCI_INT_WIN1ERR            | \
+                                RCAR_PCI_INT_WIN2ERR)
 
 #define RCAR_AHB_BUS_CTR_REG            (RCAR_AHBPCI_PCICOM_OFFSET + 0x30)
 #define RCAR_AHB_BUS_MMODE_HTRANS       (1 << 0)
@@ -74,9 +92,6 @@
 
 #define RCAR_PCI_UNIT_REV_REG           (RCAR_AHBPCI_PCICOM_OFFSET + 0x48)
 
-/* Number of internal PCI controllers */
-#define RCAR_PCI_NR_CONTROLLERS         3
-
 struct rcar_pci_priv {
         struct device *dev;
         void __iomem *reg;
@@ -84,6 +99,7 @@ struct rcar_pci_priv {
         struct resource mem_res;
         struct resource *cfg_res;
         int irq;
+        unsigned long window_size;
 };
 
 /* PCI configuration space operations */
@@ -102,6 +118,10 @@ static void __iomem *rcar_pci_cfg_base(struct pci_bus *bus, unsigned int devfn,
         if (slot > 2)
                 return NULL;
 
+        /* bridge logic only has registers to 0x40 */
+        if (slot == 0x0 && where >= 0x40)
+                return NULL;
+
         val = slot ? RCAR_AHBPCI_WIN1_DEVICE | RCAR_AHBPCI_WIN_CTR_CFG :
                      RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG;
 
@@ -156,7 +176,7 @@ static int rcar_pci_write_config(struct pci_bus *bus, unsigned int devfn,
 }
 
 /* PCI interrupt mapping */
-static int __init rcar_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+static int rcar_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
         struct pci_sys_data *sys = dev->bus->sysdata;
         struct rcar_pci_priv *priv = sys->private_data;
@@ -164,8 +184,48 @@ static int __init rcar_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
         return priv->irq;
 }
 
+#ifdef CONFIG_PCI_DEBUG
+/* if debug enabled, then attach an error handler irq to the bridge */
+
+static irqreturn_t rcar_pci_err_irq(int irq, void *pw)
+{
+        struct rcar_pci_priv *priv = pw;
+        u32 status = ioread32(priv->reg + RCAR_PCI_INT_STATUS_REG);
+
+        if (status & RCAR_PCI_INT_ALLERRORS) {
+                dev_err(priv->dev, "error irq: status %08x\n", status);
+
+                /* clear the error(s) */
+                iowrite32(status & RCAR_PCI_INT_ALLERRORS,
+                          priv->reg + RCAR_PCI_INT_STATUS_REG);
+                return IRQ_HANDLED;
+        }
+
+        return IRQ_NONE;
+}
+
+static void rcar_pci_setup_errirq(struct rcar_pci_priv *priv)
+{
+        int ret;
+        u32 val;
+
+        ret = devm_request_irq(priv->dev, priv->irq, rcar_pci_err_irq,
+                               IRQF_SHARED, "error irq", priv);
+        if (ret) {
+                dev_err(priv->dev, "cannot claim IRQ for error handling\n");
+                return;
+        }
+
+        val = ioread32(priv->reg + RCAR_PCI_INT_ENABLE_REG);
+        val |= RCAR_PCI_INT_ALLERRORS;
+        iowrite32(val, priv->reg + RCAR_PCI_INT_ENABLE_REG);
+}
+#else
+static inline void rcar_pci_setup_errirq(struct rcar_pci_priv *priv) { }
+#endif
+
 /* PCI host controller setup */
-static int __init rcar_pci_setup(int nr, struct pci_sys_data *sys)
+static int rcar_pci_setup(int nr, struct pci_sys_data *sys)
 {
         struct rcar_pci_priv *priv = sys->private_data;
         void __iomem *reg = priv->reg;
@@ -183,10 +243,31 @@ static int __init rcar_pci_setup(int nr, struct pci_sys_data *sys)
         iowrite32(val, reg + RCAR_USBCTR_REG);
         udelay(4);
 
-        /* De-assert reset and set PCIAHB window1 size to 1GB */
+        /* De-assert reset and reset PCIAHB window1 size */
         val &= ~(RCAR_USBCTR_PCIAHB_WIN1_MASK | RCAR_USBCTR_PCICLK_MASK |
                  RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST);
-        iowrite32(val | RCAR_USBCTR_PCIAHB_WIN1_1G, reg + RCAR_USBCTR_REG);
+
+        /* Setup PCIAHB window1 size */
+        switch (priv->window_size) {
+        case SZ_2G:
+                val |= RCAR_USBCTR_PCIAHB_WIN1_2G;
+                break;
+        case SZ_1G:
+                val |= RCAR_USBCTR_PCIAHB_WIN1_1G;
+                break;
+        case SZ_512M:
+                val |= RCAR_USBCTR_PCIAHB_WIN1_512M;
+                break;
+        default:
+                pr_warn("unknown window size %ld - defaulting to 256M\n",
+                        priv->window_size);
+                priv->window_size = SZ_256M;
+                /* fall-through */
+        case SZ_256M:
+                val |= RCAR_USBCTR_PCIAHB_WIN1_256M;
+                break;
+        }
+        iowrite32(val, reg + RCAR_USBCTR_REG);
 
         /* Configure AHB master and slave modes */
         iowrite32(RCAR_AHB_BUS_MODE, reg + RCAR_AHB_BUS_CTR_REG);
@@ -197,7 +278,7 @@ static int __init rcar_pci_setup(int nr, struct pci_sys_data *sys)
                RCAR_PCI_ARBITER_PCIBP_MODE;
         iowrite32(val, reg + RCAR_PCI_ARBITER_CTR_REG);
 
-        /* PCI-AHB mapping: 0x40000000-0x80000000 */
+        /* PCI-AHB mapping: 0x40000000 base */
         iowrite32(0x40000000 | RCAR_PCIAHB_PREFETCH16,
                   reg + RCAR_PCIAHB_WIN1_CTR_REG);
 
@@ -224,10 +305,15 @@ static int __init rcar_pci_setup(int nr, struct pci_sys_data *sys)
         iowrite32(RCAR_PCI_INT_A | RCAR_PCI_INT_B | RCAR_PCI_INT_PME,
                   reg + RCAR_PCI_INT_ENABLE_REG);
 
+        if (priv->irq > 0)
+                rcar_pci_setup_errirq(priv);
+
         /* Add PCI resources */
         pci_add_resource(&sys->resources, &priv->io_res);
         pci_add_resource(&sys->resources, &priv->mem_res);
 
+        /* Setup bus number based on platform device id */
+        sys->busnr = to_platform_device(priv->dev)->id;
         return 1;
 }
 
@@ -236,48 +322,13 @@ static struct pci_ops rcar_pci_ops = {
         .write  = rcar_pci_write_config,
 };
 
-static struct hw_pci rcar_hw_pci __initdata = {
-        .map_irq        = rcar_pci_map_irq,
-        .ops            = &rcar_pci_ops,
-        .setup          = rcar_pci_setup,
-};
-
-static int rcar_pci_count __initdata;
-
-static int __init rcar_pci_add_controller(struct rcar_pci_priv *priv)
-{
-        void **private_data;
-        int count;
-
-        if (rcar_hw_pci.nr_controllers < rcar_pci_count)
-                goto add_priv;
-
-        /* (Re)allocate private data pointer array if needed */
-        count = rcar_pci_count + RCAR_PCI_NR_CONTROLLERS;
-        private_data = kzalloc(count * sizeof(void *), GFP_KERNEL);
-        if (!private_data)
-                return -ENOMEM;
-
-        rcar_pci_count = count;
-        if (rcar_hw_pci.private_data) {
-                memcpy(private_data, rcar_hw_pci.private_data,
-                       rcar_hw_pci.nr_controllers * sizeof(void *));
-                kfree(rcar_hw_pci.private_data);
-        }
-
-        rcar_hw_pci.private_data = private_data;
-
-add_priv:
-        /* Add private data pointer to the array */
-        rcar_hw_pci.private_data[rcar_hw_pci.nr_controllers++] = priv;
-        return 0;
-}
-
-static int __init rcar_pci_probe(struct platform_device *pdev)
+static int rcar_pci_probe(struct platform_device *pdev)
 {
         struct resource *cfg_res, *mem_res;
         struct rcar_pci_priv *priv;
         void __iomem *reg;
+        struct hw_pci hw;
+        void *hw_private[1];
 
         cfg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         reg = devm_ioremap_resource(&pdev->dev, cfg_res);
@@ -308,31 +359,34 @@ static int __init rcar_pci_probe(struct platform_device *pdev)
         priv->reg = reg;
         priv->dev = &pdev->dev;
 
-        return rcar_pci_add_controller(priv);
+        if (priv->irq < 0) {
+                dev_err(&pdev->dev, "no valid irq found\n");
+                return priv->irq;
+        }
+
+        priv->window_size = SZ_1G;
+
+        hw_private[0] = priv;
+        memset(&hw, 0, sizeof(hw));
+        hw.nr_controllers = ARRAY_SIZE(hw_private);
+        hw.private_data = hw_private;
+        hw.map_irq = rcar_pci_map_irq;
+        hw.ops = &rcar_pci_ops;
+        hw.setup = rcar_pci_setup;
+        pci_common_init_dev(&pdev->dev, &hw);
+        return 0;
 }
 
 static struct platform_driver rcar_pci_driver = {
         .driver = {
                 .name = "pci-rcar-gen2",
+                .owner = THIS_MODULE,
+                .suppress_bind_attrs = true,
         },
+        .probe = rcar_pci_probe,
 };
 
-static int __init rcar_pci_init(void)
-{
-        int retval;
-
-        retval = platform_driver_probe(&rcar_pci_driver, rcar_pci_probe);
-        if (!retval)
-                pci_common_init(&rcar_hw_pci);
-
-        /* Private data pointer array is not needed any more */
-        kfree(rcar_hw_pci.private_data);
-        rcar_hw_pci.private_data = NULL;
-
-        return retval;
-}
-
-subsys_initcall(rcar_pci_init);
+module_platform_driver(rcar_pci_driver);
 
 MODULE_LICENSE("GPL v2");
 MODULE_DESCRIPTION("Renesas R-Car Gen2 internal PCI");
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 17ce88f79d2b..6d23d8c893cd 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -800,7 +800,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
 
         /* setup RC BARs */
         dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
-        dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_1);
+        dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1);
 
         /* setup interrupt pins */
         dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);